diff --git a/hardware/digistump/avr/boards.txt b/hardware/digistump/avr/boards.txt new file mode 100644 index 0000000..372a42c --- /dev/null +++ b/hardware/digistump/avr/boards.txt @@ -0,0 +1,65 @@ +# See: http://code.google.com/p/arduino/wiki/Platforms + +menu.cpu=Processor + +############################################################## + + + + +digispark-tiny.name=Digispark (Default - 16.5mhz) +digispark-tiny.upload.using=micronucleusprog +digispark-tiny.upload.protocol=usb +digispark-tiny.upload.tool=micronucleus +digispark-tiny.upload.maximum_size=6012 +digispark-tiny.build.mcu=attiny85 +digispark-tiny.build.f_cpu=16500000L +digispark-tiny.build.board=AVR_DIGISPARK +digispark-tiny.build.core=tiny +digispark-tiny.build.variant=digispark +digispark-tiny.upload.wait_for_upload_port = false +digispark-tiny.upload.use_1200bps_touch = false +digispark-tiny.upload.disable_flushing = false + + +digispark-pro.name=Digispark Pro (Default 16 Mhz) +digispark-pro.upload.using=micronucleusprog +digispark-pro.upload.protocol=usb +digispark-pro.upload.tool=micronucleus +digispark-pro.upload.maximum_size=14844 +digispark-pro.build.mcu=attiny167 +digispark-pro.build.f_cpu=16000000L +digispark-pro.build.board=AVR_DIGISPARKPRO +digispark-pro.build.core=pro +digispark-pro.build.variant=pro +digispark-pro.upload.wait_for_upload_port = false +digispark-pro.upload.use_1200bps_touch = false +digispark-pro.upload.disable_flushing = false + +digispark-pro32.name=Digispark Pro (16 Mhz) (32 byte buffer) +digispark-pro32.upload.using=micronucleusprog +digispark-pro32.upload.protocol=usb +digispark-pro32.upload.tool=micronucleus +digispark-pro32.upload.maximum_size=14844 +digispark-pro32.build.mcu=attiny167 +digispark-pro32.build.f_cpu=16000000L +digispark-pro32.build.board=AVR_DIGISPARKPRO +digispark-pro32.build.core=pro +digispark-pro32.build.variant=pro32buffer +digispark-pro32.upload.wait_for_upload_port = false +digispark-pro32.upload.use_1200bps_touch = false +digispark-pro32.upload.disable_flushing = false + +digispark-pro64.name=Digispark Pro (16 Mhz) (64 byte buffer) +digispark-pro64.upload.using=micronucleusprog +digispark-pro64.upload.protocol=usb +digispark-pro64.upload.tool=micronucleus +digispark-pro64.upload.maximum_size=14844 +digispark-pro64.build.mcu=attiny167 +digispark-pro64.build.f_cpu=16000000L +digispark-pro64.build.board=AVR_DIGISPARKPRO +digispark-pro64.build.core=pro +digispark-pro64.build.variant=pro64buffer +digispark-pro64.upload.wait_for_upload_port = false +digispark-pro64.upload.use_1200bps_touch = false +digispark-pro64.upload.disable_flushing = false \ No newline at end of file diff --git a/hardware/digistump/avr/cores/license.txt b/hardware/digistump/avr/cores/license.txt new file mode 100644 index 0000000..0433f82 --- /dev/null +++ b/hardware/digistump/avr/cores/license.txt @@ -0,0 +1,465 @@ +..................................................................... + +This file includes licensing information for Arduino-Tiny. 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To prevent divide by 0, it is rounded up to 1. +static inline unsigned long clockCyclesPerMicrosecond() __attribute__ ((always_inline)); +static inline unsigned long clockCyclesPerMicrosecond() +{ +//Inline function will be optimised out. + return 1; +} +#else +#define clockCyclesPerMicrosecond() ( F_CPU / 1000000L ) +#endif + +#define clockCyclesToMicroseconds(a) ( ((a) * 1000L) / (F_CPU / 1000L) ) +#define microsecondsToClockCycles(a) ( ((a) * (F_CPU / 1000L)) / 1000L ) + +#define lowByte(w) ((uint8_t) ((w) & 0xff)) +#define highByte(w) ((uint8_t) ((w) >> 8)) + +#define bitRead(value, bit) (((value) >> (bit)) & 0x01) +#define bitSet(value, bit) ((value) |= (1UL << (bit))) +#define bitClear(value, bit) ((value) &= ~(1UL << (bit))) +#define bitWrite(value, bit, bitvalue) (bitvalue ? bitSet(value, bit) : bitClear(value, bit)) + + +typedef unsigned int word; + +#define bit(b) (1UL << (b)) + +typedef uint8_t boolean; +typedef uint8_t byte; + +void initToneTimer(void); +void init(void); + +void pinMode(uint8_t, uint8_t); +void digitalWrite(uint8_t, uint8_t); +int digitalRead(uint8_t); +int analogRead(uint8_t); +void analogReference(uint8_t mode); +void analogWrite(uint8_t, int); + +unsigned long millis(void); +unsigned long micros(void); +void delay(unsigned long); +void delayMicroseconds(unsigned int us); +unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout); + +void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t val); +uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder); + +void attachInterrupt(uint8_t, void (*)(void), int mode); +void detachInterrupt(uint8_t); + +void setup(void); +void loop(void); + +// Get the bit location within the hardware port of the given virtual pin. +// This comes from the pins_*.c file for the active board configuration. + +#define analogInPinToBit(P) (P) + +extern const uint16_t PROGMEM port_to_mode_PGM[]; +extern const uint16_t PROGMEM port_to_input_PGM[]; +extern const uint16_t PROGMEM port_to_output_PGM[]; + +extern const uint8_t PROGMEM digital_pin_to_port_PGM[]; +extern const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[]; +extern const uint8_t PROGMEM digital_pin_to_timer_PGM[]; + +// Get the bit location within the hardware port of the given virtual pin. +// This comes from the pins_*.c file for the active board configuration. +// +// These perform slightly better as macros compared to inline functions +// +#define digitalPinToPort(P) ( pgm_read_byte( digital_pin_to_port_PGM + (P) ) ) +#define digitalPinToBitMask(P) ( pgm_read_byte( digital_pin_to_bit_mask_PGM + (P) ) ) +#define digitalPinToTimer(P) ( pgm_read_byte( digital_pin_to_timer_PGM + (P) ) ) +#define analogInPinToBit(P) (P) +#define portOutputRegister(P) ( (volatile uint8_t *)( pgm_read_word( port_to_output_PGM + (P))) ) +#define portInputRegister(P) ( (volatile uint8_t *)( pgm_read_word( port_to_input_PGM + (P))) ) +#define portModeRegister(P) ( (volatile uint8_t *)( pgm_read_word( port_to_mode_PGM + (P))) ) + +#define NOT_A_PIN 0 +#define NOT_A_PORT 0 + +#define PA 1 +#define PB 2 +#define PC 3 +#define PD 4 + +#define NOT_ON_TIMER 0 +#define TIMER0A 1 +#define TIMER0B 2 +#define TIMER1A 3 +#define TIMER1B 4 +#define TIMER1D 5 + +#include "pins_arduino.h" + +#ifndef USE_SOFTWARE_SERIAL +//Default to hardware serial. +#define USE_SOFTWARE_SERIAL 0 +#endif + +/*============================================================================= + Allow the ADC to be optional for low-power applications +=============================================================================*/ + +#ifndef TIMER_TO_USE_FOR_MILLIS +#define TIMER_TO_USE_FOR_MILLIS 0 +#endif +/* + Tone goes on whichever timer was not used for millis. +*/ +#if TIMER_TO_USE_FOR_MILLIS == 1 +#define TIMER_TO_USE_FOR_TONE 0 +#else +#define TIMER_TO_USE_FOR_TONE 1 +#endif + +#if NUM_ANALOG_INPUTS > 0 + #define HAVE_ADC 1 + #ifndef INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER + #define INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER 1 + #endif +#else + #define HAVE_ADC 0 + #if defined(INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER) + #undef INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER + #endif + #define INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER 0 +#endif + +#if !HAVE_ADC + #undef INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER + #define INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER 0 +#else + #ifndef INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER + #define INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER 1 + #endif +#endif + +/*============================================================================= + Allow the "secondary timers" to be optional for low-power applications +=============================================================================*/ + +#ifndef INITIALIZE_SECONDARY_TIMERS + #define INITIALIZE_SECONDARY_TIMERS 1 +#endif + + +#ifdef __cplusplus +} // extern "C" +#endif + +#ifdef __cplusplus +#include "WCharacter.h" +#include "WString.h" +#include "HardwareSerial.h" +#include "TinySoftwareSerial.h" + +uint16_t makeWord(uint16_t w); +uint16_t makeWord(byte h, byte l); + +#define word(...) makeWord(__VA_ARGS__) + +unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout = 1000000L); + +void tone(uint8_t _pin, unsigned int frequency, unsigned long duration = 0); +void noTone(uint8_t _pin = 255); + +// WMath prototypes +long random(long); +long random(long, long); +void randomSeed(unsigned int); +long map(long, long, long, long, long); + +#endif + +/*============================================================================= + Aliases for the interrupt service routine vector numbers so the code + doesn't have to be riddled with #ifdefs. +=============================================================================*/ + +#if defined( TIM0_COMPA_vect ) && ! defined( TIMER0_COMPA_vect ) +#define TIMER0_COMPA_vect TIM0_COMPA_vect +#endif + +#if defined( TIM0_COMPB_vect ) && ! defined( TIMER0_COMPB_vect ) +#define TIMER0_COMPB_vect TIM0_COMPB_vect +#endif + +#if defined( TIM0_OVF_vect ) && ! defined( TIMER0_OVF_vect ) +#define TIMER0_OVF_vect TIM0_OVF_vect +#endif + +#if defined( TIM1_COMPA_vect ) && ! defined( TIMER1_COMPA_vect ) +#define TIMER1_COMPA_vect TIM1_COMPA_vect +#endif + +#if defined( TIM1_COMPB_vect ) && ! defined( TIMER1_COMPB_vect ) +#define TIMER1_COMPB_vect TIM1_COMPB_vect +#endif + +#if defined( TIM1_OVF_vect ) && ! defined( TIMER1_OVF_vect ) +#define TIMER1_OVF_vect TIM1_OVF_vect +#endif + +#endif diff --git a/hardware/digistump/avr/cores/pro/HardwareSerial.cpp b/hardware/digistump/avr/cores/pro/HardwareSerial.cpp new file mode 100644 index 0000000..c740ba7 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/HardwareSerial.cpp @@ -0,0 +1,411 @@ +/* + HardwareSerial.cpp - Hardware serial library for Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 23 November 2006 by David A. Mellis + Modified 28 September 2010 by Mark Sproul +*/ + +#include +#include +#include +#include + +#include "Arduino.h" +#include "wiring_private.h" + +// this next line disables the entire HardwareSerial.cpp, +// this is so I can support Attiny series and any other chip without a uart +#if ( defined(UBRRH) || defined(UBRR0H) || defined(UBRR1H) || defined(LINBRRH)) && !USE_SOFTWARE_SERIAL + +#include "HardwareSerial.h" + +// Define constants and variables for buffering incoming serial data. We're +// using a ring buffer (I think), in which rx_buffer_head is the index of the +// location to which to write the next incoming character and rx_buffer_tail +// is the index of the location from which to read. +#ifndef SERIAL_BUFFER_SIZE + #if (RAMEND < 1000) + #define SERIAL_BUFFER_SIZE 16 + #else + #define SERIAL_BUFFER_SIZE 64 + #endif +#endif +struct ring_buffer +{ + unsigned char buffer[SERIAL_BUFFER_SIZE]; + byte head; + byte tail; +}; + +#if defined(UBRRH) || defined(UBRR0H) || defined(LINBRRH) + ring_buffer rx_buffer = { { 0 }, 0, 0 }; + ring_buffer tx_buffer = { { 0 }, 0, 0 }; +#endif +#if defined(UBRR1H) + ring_buffer rx_buffer1 = { { 0 }, 0, 0 }; + ring_buffer tx_buffer1 = { { 0 }, 0, 0 }; +#endif + +inline void store_char(unsigned char c, ring_buffer *buffer) +{ + byte i = (buffer->head + 1) % SERIAL_BUFFER_SIZE; + + // if we should be storing the received character into the location + // just before the tail (meaning that the head would advance to the + // current location of the tail), we're about to overflow the buffer + // and so we don't write the character or advance the head. + if (i != buffer->tail) { + buffer->buffer[buffer->head] = c; + buffer->head = i; + } +} + +#if defined(USART_RX_vect) + SIGNAL(USART_RX_vect) + { + #if defined(UDR0) + unsigned char c = UDR0; + #elif defined(UDR) + unsigned char c = UDR; // atmega8535 + #else + #error UDR not defined + #endif + store_char(c, &rx_buffer); + } +#elif defined(SIG_USART0_RECV) && defined(UDR0) + SIGNAL(SIG_USART0_RECV) + { + unsigned char c = UDR0; + store_char(c, &rx_buffer); + } +#elif defined(SIG_UART0_RECV) && defined(UDR0) + SIGNAL(SIG_UART0_RECV) + { + unsigned char c = UDR0; + store_char(c, &rx_buffer); + } +//#elif defined(SIG_USART_RECV) +#elif defined(USART0_RX_vect) + // fixed by Mark Sproul this is on the 644/644p + //SIGNAL(SIG_USART_RECV) + SIGNAL(USART0_RX_vect) + { + #if defined(UDR0) + unsigned char c = UDR0; + #elif defined(UDR) + unsigned char c = UDR; // atmega8, atmega32 + #else + #error UDR not defined + #endif + store_char(c, &rx_buffer); + } +#elif defined(SIG_UART_RECV) + // this is for atmega8 + SIGNAL(SIG_UART_RECV) + { + #if defined(UDR0) + unsigned char c = UDR0; // atmega645 + #elif defined(UDR) + unsigned char c = UDR; // atmega8 + #endif + store_char(c, &rx_buffer); + } +#elif defined(LIN_TC_vect) + // this is for attinyX7 + SIGNAL(LIN_TC_vect) + { + if(LINSIR & _BV(LRXOK)) { + unsigned char c = LINDAT; + store_char(c, &rx_buffer); + } + if(LINSIR & _BV(LTXOK)){ + PINA |= _BV(PINA5); + if (tx_buffer.head == tx_buffer.tail) { + // Buffer empty, so disable interrupts + cbi(LINENIR,LENTXOK); + } else { + // There is more data in the output buffer. Send the next byte + unsigned char c = tx_buffer.buffer[tx_buffer.tail]; + tx_buffer.tail = (tx_buffer.tail + 1) % SERIAL_BUFFER_SIZE; + + LINDAT = c; + } + } + } +#else + #error No interrupt handler for usart 0 +#endif + +//#if defined(SIG_USART1_RECV) +#if defined(USART1_RX_vect) + //SIGNAL(SIG_USART1_RECV) + SIGNAL(USART1_RX_vect) + { + unsigned char c = UDR1; + store_char(c, &rx_buffer1); + } +#elif defined(SIG_USART1_RECV) + #error SIG_USART1_RECV +#endif + +#if !defined(UART0_UDRE_vect) && !defined(UART_UDRE_vect) && !defined(USART0_UDRE_vect) && !defined(USART_UDRE_vect) && !defined(LIN_TC_vect) + #error "Don't know what the Data Register Empty vector is called for the first UART" +#elif ( defined(UBRRH) || defined(UBRR0H) || defined(UBRR1H)) +#if defined(UART0_UDRE_vect) +ISR(UART0_UDRE_vect) +#elif defined(UART_UDRE_vect) +ISR(UART_UDRE_vect) +#elif defined(USART0_UDRE_vect) +ISR(USART0_UDRE_vect) +#elif defined(USART_UDRE_vect) +ISR(USART_UDRE_vect) +#endif +{ + if (tx_buffer.head == tx_buffer.tail) { + // Buffer empty, so disable interrupts +#if defined(UCSR0B) + cbi(UCSR0B, UDRIE0); +#else + cbi(UCSRB, UDRIE); +#endif + } + else { + // There is more data in the output buffer. Send the next byte + unsigned char c = tx_buffer.buffer[tx_buffer.tail]; + tx_buffer.tail = (tx_buffer.tail + 1) % SERIAL_BUFFER_SIZE; + + #if defined(UDR0) + UDR0 = c; + #elif defined(UDR) + UDR = c; + #else + #error UDR not defined + #endif + } +} +#endif + +#ifdef USART1_UDRE_vect +ISR(USART1_UDRE_vect) +{ + if (tx_buffer1.head == tx_buffer1.tail) { + // Buffer empty, so disable interrupts + cbi(UCSR1B, UDRIE1); + } + else { + // There is more data in the output buffer. Send the next byte + unsigned char c = tx_buffer1.buffer[tx_buffer1.tail]; + tx_buffer1.tail = (tx_buffer1.tail + 1) % SERIAL_BUFFER_SIZE; + + UDR1 = c; + } +} +#endif + + +// Constructors //////////////////////////////////////////////////////////////// + +HardwareSerial::HardwareSerial(ring_buffer *rx_buffer, ring_buffer *tx_buffer +#if ( defined(UBRRH) || defined(UBRR0H) || defined(UBRR1H)) + , + volatile uint8_t *ubrrh, volatile uint8_t *ubrrl, + volatile uint8_t *ucsra, volatile uint8_t *ucsrb, + volatile uint8_t *udr, + uint8_t rxen, uint8_t txen, uint8_t rxcie, uint8_t udrie, uint8_t u2x + ) +{ + _rx_buffer = rx_buffer; + _tx_buffer = tx_buffer; + _ubrrh = ubrrh; + _ubrrl = ubrrl; + _ucsra = ucsra; + _ucsrb = ucsrb; + _udr = udr; + _rxen = rxen; + _txen = txen; + _rxcie = rxcie; + _udrie = udrie; + _u2x = u2x; +} +#else + ) +{ + _rx_buffer = rx_buffer; + _tx_buffer = tx_buffer; +} +#endif + +// Public Methods ////////////////////////////////////////////////////////////// + + + + + +void HardwareSerial::begin(long baud) +{ +#if ( defined(UBRRH) || defined(UBRR0H) || defined(UBRR1H)) + uint16_t baud_setting; + bool use_u2x = true; + +#if F_CPU == 16000000UL + // hardcoded exception for compatibility with the bootloader shipped + // with the Duemilanove and previous boards and the firmware on the 8U2 + // on the Uno and Mega 2560. + if (baud == 57600) { + use_u2x = false; + } +#endif + +try_again: + + if (use_u2x) { + *_ucsra = 1 << _u2x; + baud_setting = (F_CPU / 4 / baud - 1) / 2; + } else { + *_ucsra = 0; + baud_setting = (F_CPU / 8 / baud - 1) / 2; + } + + if ((baud_setting > 4095) && use_u2x) + { + use_u2x = false; + goto try_again; + } + + // assign the baud_setting, a.k.a. ubbr (USART Baud Rate Register) + *_ubrrh = baud_setting >> 8; + *_ubrrl = baud_setting; + + sbi(*_ucsrb, _rxen); + sbi(*_ucsrb, _txen); + sbi(*_ucsrb, _rxcie); + cbi(*_ucsrb, _udrie); +#else + LINCR = (1 << LSWRES); + LINBRR = (((F_CPU * 10L / 16L / baud) + 5L) / 10L) - 1; + LINBTR = (1 << LDISR) | (16 << LBT0); + LINCR = _BV(LENA) | _BV(LCMD2) | _BV(LCMD1) | _BV(LCMD0); + sbi(LINENIR,LENRXOK); +#endif +} + +void HardwareSerial::end() +{ + while (_tx_buffer->head != _tx_buffer->tail) + ; +#if ( defined(UBRRH) || defined(UBRR0H) || defined(UBRR1H)) + cbi(*_ucsrb, _rxen); + cbi(*_ucsrb, _txen); + cbi(*_ucsrb, _rxcie); + cbi(*_ucsrb, _udrie); +#else + cbi(LINENIR,LENTXOK); + cbi(LINENIR,LENRXOK); + cbi(LINCR,LENA); + cbi(LINCR,LCMD0); + cbi(LINCR,LCMD1); + cbi(LINCR,LCMD2); +#endif + _rx_buffer->head = _rx_buffer->tail; +} + +int HardwareSerial::available(void) +{ + return (unsigned int)(SERIAL_BUFFER_SIZE + _rx_buffer->head - _rx_buffer->tail) % SERIAL_BUFFER_SIZE; +} + +int HardwareSerial::peek(void) +{ + if (_rx_buffer->head == _rx_buffer->tail) { + return -1; + } else { + return _rx_buffer->buffer[_rx_buffer->tail]; + } +} + +int HardwareSerial::read(void) +{ + // if the head isn't ahead of the tail, we don't have any characters + if (_rx_buffer->head == _rx_buffer->tail) { + return -1; + } else { + unsigned char c = _rx_buffer->buffer[_rx_buffer->tail]; + _rx_buffer->tail = (_rx_buffer->tail + 1) % SERIAL_BUFFER_SIZE; + return c; + } +} + +void HardwareSerial::flush() +{ + while (_tx_buffer->head != _tx_buffer->tail) + ; +} + +unsigned int HardwareSerial::txfree() +{ + if (_tx_buffer->head >= _tx_buffer->tail) return SERIAL_BUFFER_SIZE - 1 - _tx_buffer->head + _tx_buffer->tail; + return _tx_buffer->tail - _tx_buffer->head - 1; +} + + +size_t HardwareSerial::write(uint8_t c) +{ + byte i = (_tx_buffer->head + 1) % SERIAL_BUFFER_SIZE; + + // If the output buffer is full, there's nothing for it other than to + // wait for the interrupt handler to empty it a bit + // ???: return 0 here instead? + while (txfree() == 0); + + _tx_buffer->buffer[_tx_buffer->head] = c; + _tx_buffer->head = i; + #if ( defined(UBRRH) || defined(UBRR0H) || defined(UBRR1H) ) + sbi(*_ucsrb, _udrie); + #else + if(!(LINENIR & _BV(LENTXOK))){ + //The buffer was previously empty, so enable TX Complete interrupt and load first byte. + sbi(LINENIR,LENTXOK); + unsigned char c = tx_buffer.buffer[tx_buffer.tail]; + tx_buffer.tail = (tx_buffer.tail + 1) % SERIAL_BUFFER_SIZE; + LINDAT = c; + } + #endif + return 1; +} + +HardwareSerial::operator bool() { + return true; +} + +// Preinstantiate Objects ////////////////////////////////////////////////////// + +#if defined(UBRRH) && defined(UBRRL) + HardwareSerial Serial(&rx_buffer, &tx_buffer, &UBRRH, &UBRRL, &UCSRA, &UCSRB, &UDR, RXEN, TXEN, RXCIE, UDRE, U2X); +#elif defined(UBRR0H) && defined(UBRR0L) + HardwareSerial Serial(&rx_buffer, &tx_buffer, &UBRR0H, &UBRR0L, &UCSR0A, &UCSR0B, &UDR0, RXEN0, TXEN0, RXCIE0, UDRE0, U2X0); +#elif defined(LINBRRH) + HardwareSerial Serial(&rx_buffer, &tx_buffer); +#endif + +#if defined(UBRR1H) + HardwareSerial Serial1(&rx_buffer1, &tx_buffer1, &UBRR1H, &UBRR1L, &UCSR1A, &UCSR1B, &UDR1, RXEN1, TXEN1, RXCIE1, UDRE1, U2X1); +#endif + +#elif !USE_SOFTWARE_SERIAL +#warning There is no Hardware UART, and Sofware Serial is not enabled. There will be no serial port. +#endif // whole file diff --git a/hardware/digistump/avr/cores/pro/HardwareSerial.h b/hardware/digistump/avr/cores/pro/HardwareSerial.h new file mode 100644 index 0000000..15bde12 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/HardwareSerial.h @@ -0,0 +1,80 @@ +/* + HardwareSerial.h - Hardware serial library for Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 28 September 2010 by Mark Sproul +*/ + +#ifndef HardwareSerial_h +#define HardwareSerial_h + +#if ( defined(UBRRH) || defined(UBRR0H) || defined(UBRR1H) || defined(LINBRRH)) && !USE_SOFTWARE_SERIAL +#include + +#include "Stream.h" + +struct ring_buffer; + +class HardwareSerial : public Stream +{ + private: + ring_buffer *_rx_buffer; + ring_buffer *_tx_buffer; + #if ( defined(UBRRH) || defined(UBRR0H) || defined(UBRR1H)) + volatile uint8_t *_ubrrh; + volatile uint8_t *_ubrrl; + volatile uint8_t *_ucsra; + volatile uint8_t *_ucsrb; + volatile uint8_t *_udr; + uint8_t _rxen; + uint8_t _txen; + uint8_t _rxcie; + uint8_t _udrie; + uint8_t _u2x; + #endif + public: + HardwareSerial(ring_buffer *rx_buffer, ring_buffer *tx_buffer + #if ( defined(UBRRH) || defined(UBRR0H) || defined(UBRR1H)) + , + volatile uint8_t *ubrrh, volatile uint8_t *ubrrl, + volatile uint8_t *ucsra, volatile uint8_t *ucsrb, + volatile uint8_t *udr, + uint8_t rxen, uint8_t txen, uint8_t rxcie, uint8_t udrie, uint8_t u2x); + #else + ); + #endif + void begin(long); + void end(); + virtual int available(void); + virtual int peek(void); + virtual unsigned int txfree(void); + virtual int read(void); + virtual void flush(void); + virtual size_t write(uint8_t); + using Print::write; // pull in write(str) and write(buf, size) from Print + operator bool(); +}; +#endif + +#if (defined(UBRRH) || defined(UBRR0H) || defined(LINBRRH)) && !USE_SOFTWARE_SERIAL + extern HardwareSerial Serial; +#endif +#if defined(UBRR1H) + extern HardwareSerial Serial1; +#endif + +#endif diff --git a/hardware/digistump/avr/cores/pro/Print.cpp b/hardware/digistump/avr/cores/pro/Print.cpp new file mode 100644 index 0000000..7165721 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/Print.cpp @@ -0,0 +1,262 @@ +/* + Print.cpp - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 23 November 2006 by David A. Mellis + */ + +#include +#include +#include +#include + +#include "Arduino.h" +#include "Print.h" + +// Public Methods ////////////////////////////////////////////////////////////// + +/* default implementation: may be overridden */ +size_t Print::write(const uint8_t *buffer, size_t size) +{ + size_t n = 0; + while (size--) { + n += write(*buffer++); + } + return n; +} + +size_t Print::print(const String &s) +{ + size_t n = 0; + for (uint16_t i = 0; i < s.length(); i++) { + n += write(s[i]); + } + return n; +} + +size_t Print::print(const char str[]) +{ + return write(str); +} + +size_t Print::print(char c) +{ + return write(c); +} + +size_t Print::print(unsigned char b, int base) +{ + return print((unsigned long) b, base); +} + +size_t Print::print(int n, int base) +{ + return print((long) n, base); +} + +size_t Print::print(unsigned int n, int base) +{ + return print((unsigned long) n, base); +} + +size_t Print::print(long n, int base) +{ + if (base == 0) { + return write(n); + } else if (base == 10) { + int t = 0; + if (n < 0) { + t = print('-'); + n = -n; + } + return printNumber(n, 10) + t; + } else { + return printNumber(n, base); + } +} + +size_t Print::print(unsigned long n, int base) +{ + if (base == 0) return write(n); + else return printNumber(n, base); +} + +size_t Print::print(double n, int digits) +{ + return printFloat(n, digits); +} + +size_t Print::print( fstr_t* s ) +{ + size_t n = 0; + char ch; + + ch = pgm_read_byte( s ); + while ( ch != 0 ) + { + write( ch ); + ++s; + ++n; + ch = pgm_read_byte( s ); + } + return( n ); +} + +size_t Print::println(void) +{ + size_t n = print('\r'); + n += print('\n'); + return n; +} + +size_t Print::println(const String &s) +{ + size_t n = print(s); + n += println(); + return n; +} + +size_t Print::println(const char c[]) +{ + size_t n = print(c); + n += println(); + return n; +} + +size_t Print::println(char c) +{ + size_t n = print(c); + n += println(); + return n; +} + +size_t Print::println(unsigned char b, int base) +{ + size_t n = print(b, base); + n += println(); + return n; +} + +size_t Print::println(int num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(unsigned int num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(long num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(long long num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(unsigned long num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(double num, int digits) +{ + size_t n = print(num, digits); + n += println(); + return n; +} + +size_t Print::println( fstr_t* s ) +{ + size_t n = print( s ); + n += println(); + return( n ); +} + +// Private Methods ///////////////////////////////////////////////////////////// + +size_t Print::printNumber(unsigned long n, uint8_t base) { + char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte. + char *str = &buf[sizeof(buf) - 1]; + + *str = '\0'; + + // prevent crash if called with base == 1 + if (base < 2) base = 10; + + do { + unsigned long m = n; + n /= base; + char c = m - base * n; + *--str = c < 10 ? c + '0' : c + 'A' - 10; + } while(n); + + return write(str); +} + +size_t Print::printFloat(double number, uint8_t digits) +{ + size_t n = 0; + + // Handle negative numbers + if (number < 0.0) + { + n += print('-'); + number = -number; + } + + // Round correctly so that print(1.999, 2) prints as "2.00" + double rounding = 0.5; + for (uint8_t i=0; i 0) { + n += print("."); + } + + // Extract digits from the remainder one at a time + while (digits-- > 0) + { + remainder *= 10.0; + int toPrint = int(remainder); + n += print(toPrint); + remainder -= toPrint; + } + + return n; +} diff --git a/hardware/digistump/avr/cores/pro/Print.h b/hardware/digistump/avr/cores/pro/Print.h new file mode 100644 index 0000000..8ca2fe3 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/Print.h @@ -0,0 +1,108 @@ +/* + Print.h - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 20-11-2010 by B.Cook ... + + http://arduiniana.org/libraries/flash/ + Printable support thanks to Mikal Hart +*/ + +#ifndef Print_h +#define Print_h + +#include +#include // for size_t + +#include "WString.h" + +#define DEC 10 +#define HEX 16 +#define OCT 8 +#ifdef BIN +#define ABIN BIN +//One of the ATtiny84 registers has a bit called BIN, so rename it to avoid compiler warnings. +#undef BIN +#endif +#define BIN 2 + +#define ARDUINO_CORE_PRINTABLE_SUPPORT + +class Print; + +/* Printable...*/ + +class _Printable +{ +public: + virtual void print(Print &stream) const = 0; +}; + +/* ...Printable */ + +typedef struct +{ + char c; +} +fstr_t; + + +class Print +{ + private: + int write_error; + size_t printNumber(unsigned long, uint8_t); + size_t printFloat(double, uint8_t); + protected: + void setWriteError(int err = 1) { write_error = err; } + public: + Print() : write_error(0) {} + + int getWriteError() { return write_error; } + void clearWriteError() { setWriteError(0); } + + virtual size_t write(uint8_t) = 0; + size_t write(const char *str) { return write((const uint8_t *)str, strlen(str)); } + virtual size_t write(const uint8_t *buffer, size_t size); + + size_t print(fstr_t*); + size_t print(const String &); + size_t print(const char[]); + size_t print(char); + size_t print(unsigned char, int = DEC); + size_t print(int, int = DEC); + size_t print(unsigned int, int = DEC); + size_t print(long, int = DEC); + size_t print(long long, int = DEC); + size_t print(unsigned long, int = DEC); + size_t print(double, int = 2); + + size_t println(fstr_t*); + size_t println(const String &s); + size_t println(const char[]); + size_t println(char); + size_t println(unsigned char, int = DEC); + size_t println(int, int = DEC); + size_t println(unsigned int, int = DEC); + size_t println(long, int = DEC); + size_t println(long long, int = DEC); + size_t println(unsigned long, int = DEC); + size_t println(double, int = 2); + size_t println(void); +}; + +#endif diff --git a/hardware/digistump/avr/cores/pro/Printable.h b/hardware/digistump/avr/cores/pro/Printable.h new file mode 100644 index 0000000..d03c9af --- /dev/null +++ b/hardware/digistump/avr/cores/pro/Printable.h @@ -0,0 +1,40 @@ +/* + Printable.h - Interface class that allows printing of complex types + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef Printable_h +#define Printable_h + +#include + +class Print; + +/** The Printable class provides a way for new classes to allow themselves to be printed. + By deriving from Printable and implementing the printTo method, it will then be possible + for users to print out instances of this class by passing them into the usual + Print::print and Print::println methods. +*/ + +class Printable +{ + public: + virtual size_t printTo(Print& p) const = 0; +}; + +#endif + diff --git a/hardware/digistump/avr/cores/pro/Stream.cpp b/hardware/digistump/avr/cores/pro/Stream.cpp new file mode 100644 index 0000000..f21a411 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/Stream.cpp @@ -0,0 +1,270 @@ +/* + Stream.cpp - adds parsing methods to Stream class + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Created July 2011 + parsing functions based on TextFinder library by Michael Margolis + */ + +#include "Arduino.h" +#include "Stream.h" + +#define PARSE_TIMEOUT 1000 // default number of milli-seconds to wait +#define NO_SKIP_CHAR 1 // a magic char not found in a valid ASCII numeric field + +// private method to read stream with timeout +int Stream::timedRead() +{ + int c; + _startMillis = millis(); + do { + c = read(); + if (c >= 0) return c; + } while(millis() - _startMillis < _timeout); + return -1; // -1 indicates timeout +} + +// private method to peek stream with timeout +int Stream::timedPeek() +{ + int c; + _startMillis = millis(); + do { + c = peek(); + if (c >= 0) return c; + } while(millis() - _startMillis < _timeout); + return -1; // -1 indicates timeout +} + +// returns peek of the next digit in the stream or -1 if timeout +// discards non-numeric characters +int Stream::peekNextDigit() +{ + int c; + while (1) { + c = timedPeek(); + if (c < 0) return c; // timeout + if (c == '-') return c; + if (c >= '0' && c <= '9') return c; + read(); // discard non-numeric + } +} + +// Public Methods +////////////////////////////////////////////////////////////// + +void Stream::setTimeout(unsigned long timeout) // sets the maximum number of milliseconds to wait +{ + _timeout = timeout; +} + + // find returns true if the target string is found +bool Stream::find(char *target) +{ + return findUntil(target, ""); +} + +// reads data from the stream until the target string of given length is found +// returns true if target string is found, false if timed out +bool Stream::find(char *target, size_t length) +{ + return findUntil(target, length, NULL, 0); +} + +// as find but search ends if the terminator string is found +bool Stream::findUntil(char *target, char *terminator) +{ + return findUntil(target, strlen(target), terminator, strlen(terminator)); +} + +// reads data from the stream until the target string of the given length is found +// search terminated if the terminator string is found +// returns true if target string is found, false if terminated or timed out +bool Stream::findUntil(char *target, size_t targetLen, char *terminator, size_t termLen) +{ + size_t index = 0; // maximum target string length is 64k bytes! + size_t termIndex = 0; + int c; + + if( *target == 0) + return true; // return true if target is a null string + while( (c = timedRead()) > 0){ + + if(c != target[index]) + index = 0; // reset index if any char does not match + + if( c == target[index]){ + //////Serial.print("found "); Serial.write(c); Serial.print("index now"); Serial.println(index+1); + if(++index >= targetLen){ // return true if all chars in the target match + return true; + } + } + + if(termLen > 0 && c == terminator[termIndex]){ + if(++termIndex >= termLen) + return false; // return false if terminate string found before target string + } + else + termIndex = 0; + } + return false; +} + + +// returns the first valid (long) integer value from the current position. +// initial characters that are not digits (or the minus sign) are skipped +// function is terminated by the first character that is not a digit. +long Stream::parseInt() +{ + return parseInt(NO_SKIP_CHAR); // terminate on first non-digit character (or timeout) +} + +// as above but a given skipChar is ignored +// this allows format characters (typically commas) in values to be ignored +long Stream::parseInt(char skipChar) +{ + boolean isNegative = false; + long value = 0; + int c; + + c = peekNextDigit(); + // ignore non numeric leading characters + if(c < 0) + return 0; // zero returned if timeout + + do{ + if(c == skipChar) + ; // ignore this charactor + else if(c == '-') + isNegative = true; + else if(c >= '0' && c <= '9') // is c a digit? + value = value * 10 + c - '0'; + read(); // consume the character we got with peek + c = timedPeek(); + } + while( (c >= '0' && c <= '9') || c == skipChar ); + + if(isNegative) + value = -value; + return value; +} + + +// as parseInt but returns a floating point value +float Stream::parseFloat() +{ + return parseFloat(NO_SKIP_CHAR); +} + +// as above but the given skipChar is ignored +// this allows format characters (typically commas) in values to be ignored +float Stream::parseFloat(char skipChar){ + boolean isNegative = false; + boolean isFraction = false; + long value = 0; + char c; + float fraction = 1.0; + + c = peekNextDigit(); + // ignore non numeric leading characters + if(c < 0) + return 0; // zero returned if timeout + + do{ + if(c == skipChar) + ; // ignore + else if(c == '-') + isNegative = true; + else if (c == '.') + isFraction = true; + else if(c >= '0' && c <= '9') { // is c a digit? + value = value * 10 + c - '0'; + if(isFraction) + fraction *= 0.1; + } + read(); // consume the character we got with peek + c = timedPeek(); + } + while( (c >= '0' && c <= '9') || c == '.' || c == skipChar ); + + if(isNegative) + value = -value; + if(isFraction) + return value * fraction; + else + return value; +} + +// read characters from stream into buffer +// terminates if length characters have been read, or timeout (see setTimeout) +// returns the number of characters placed in the buffer +// the buffer is NOT null terminated. +// +size_t Stream::readBytes(char *buffer, size_t length) +{ + size_t count = 0; + while (count < length) { + int c = timedRead(); + if (c < 0) break; + *buffer++ = (char)c; + count++; + } + return count; +} + + +// as readBytes with terminator character +// terminates if length characters have been read, timeout, or if the terminator character detected +// returns the number of characters placed in the buffer (0 means no valid data found) + +size_t Stream::readBytesUntil(char terminator, char *buffer, size_t length) +{ + if (length < 1) return 0; + size_t index = 0; + while (index < length) { + int c = timedRead(); + if (c < 0 || c == terminator) break; + *buffer++ = (char)c; + index++; + } + return index; // return number of characters, not including null terminator +} + +String Stream::readString() +{ + String ret; + int c = timedRead(); + while (c >= 0) + { + ret += (char)c; + c = timedRead(); + } + return ret; +} + +String Stream::readStringUntil(char terminator) +{ + String ret; + int c = timedRead(); + while (c >= 0 && c != terminator) + { + ret += (char)c; + c = timedRead(); + } + return ret; +} + diff --git a/hardware/digistump/avr/cores/pro/Stream.h b/hardware/digistump/avr/cores/pro/Stream.h new file mode 100644 index 0000000..007b4bc --- /dev/null +++ b/hardware/digistump/avr/cores/pro/Stream.h @@ -0,0 +1,96 @@ +/* + Stream.h - base class for character-based streams. + Copyright (c) 2010 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + parsing functions based on TextFinder library by Michael Margolis +*/ + +#ifndef Stream_h +#define Stream_h + +#include +#include "Print.h" + +// compatability macros for testing +/* +#define getInt() parseInt() +#define getInt(skipChar) parseInt(skipchar) +#define getFloat() parseFloat() +#define getFloat(skipChar) parseFloat(skipChar) +#define getString( pre_string, post_string, buffer, length) +readBytesBetween( pre_string, terminator, buffer, length) +*/ + +class Stream : public Print +{ + protected: + unsigned long _timeout; // number of milliseconds to wait for the next char before aborting timed read + unsigned long _startMillis; // used for timeout measurement + int timedRead(); // private method to read stream with timeout + int timedPeek(); // private method to peek stream with timeout + int peekNextDigit(); // returns the next numeric digit in the stream or -1 if timeout + + public: + virtual int available() = 0; + virtual int read() = 0; + virtual int peek() = 0; + virtual void flush() = 0; + + Stream() {_timeout=1000;} + +// parsing methods + + void setTimeout(unsigned long timeout); // sets maximum milliseconds to wait for stream data, default is 1 second + + bool find(char *target); // reads data from the stream until the target string is found + // returns true if target string is found, false if timed out (see setTimeout) + + bool find(char *target, size_t length); // reads data from the stream until the target string of given length is found + // returns true if target string is found, false if timed out + + bool findUntil(char *target, char *terminator); // as find but search ends if the terminator string is found + + bool findUntil(char *target, size_t targetLen, char *terminate, size_t termLen); // as above but search ends if the terminate string is found + + + long parseInt(); // returns the first valid (long) integer value from the current position. + // initial characters that are not digits (or the minus sign) are skipped + // integer is terminated by the first character that is not a digit. + + float parseFloat(); // float version of parseInt + + size_t readBytes( char *buffer, size_t length); // read chars from stream into buffer + // terminates if length characters have been read or timeout (see setTimeout) + // returns the number of characters placed in the buffer (0 means no valid data found) + + size_t readBytesUntil( char terminator, char *buffer, size_t length); // as readBytes with terminator character + // terminates if length characters have been read, timeout, or if the terminator character detected + // returns the number of characters placed in the buffer (0 means no valid data found) + + // Arduino String functions to be added here + String readString(); + String readStringUntil(char terminator); + + protected: + long parseInt(char skipChar); // as above but the given skipChar is ignored + // as above but the given skipChar is ignored + // this allows format characters (typically commas) in values to be ignored + + float parseFloat(char skipChar); // as above but the given skipChar is ignored +}; + +#endif diff --git a/hardware/digistump/avr/cores/pro/Stream_old.h b/hardware/digistump/avr/cores/pro/Stream_old.h new file mode 100644 index 0000000..93d8275 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/Stream_old.h @@ -0,0 +1,35 @@ +/* + Stream.h - base class for character-based streams. + Copyright (c) 2010 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef Stream_h +#define Stream_h + +#include +#include "Print.h" + +class Stream : public Print +{ + public: + virtual int available() = 0; + virtual int read() = 0; + virtual int peek() = 0; + virtual void flush() = 0; +}; + +#endif diff --git a/hardware/digistump/avr/cores/pro/TinySoftwareSPI.cpp b/hardware/digistump/avr/cores/pro/TinySoftwareSPI.cpp new file mode 100644 index 0000000..a788718 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/TinySoftwareSPI.cpp @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2012 by Thomas Carpenter + * Software based SPI Master Library for Tiny core. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of either the GNU General Public License version 2 + * or the GNU Lesser General Public License version 2.1, both as + * published by the Free Software Foundation. + * + * Currently, this runs at 125kHz on an 8MHz clock. + */ + +#include "TinySoftwareSPI.h" +#include "Arduino.h" + +SoftSPIClass::SoftSPIClass(){ + _bitOrder = MSBFIRST; + _mode = SPI_MODE0; + _running = false; + transferType = &SoftSPIClass::noTransfer; +} + +#if defined(SS) && defined(MOSI) && defined(MISO) && defined(SCK) +void SoftSPIClass::begin(){ + begin(SCK,MOSI,MISO,SS); +} +#endif + +void SoftSPIClass::writeSS(boolean state){ + if (state) { + *_SS_PORT |= _SS_HIGH; + } else { + *_SS_PORT &= _SS_LOW; + } +} + +void SoftSPIClass::begin(byte SCK_, byte MOSI_, byte MISO_, byte SS_){ + _SS = SS_; + _SCK = SCK_; + _MISO = MISO_; + _MOSI = MOSI_; + + byte MOSIport = digitalPinToPort(_MOSI); + byte SSport = digitalPinToPort(_SS); + byte SCKport = digitalPinToPort(_SCK); + byte MISOport = digitalPinToPort(_MISO); + + if ((MOSIport == NOT_A_PIN) || + ( SSport == NOT_A_PIN) || + ( SCKport == NOT_A_PIN) || + (MISOport == NOT_A_PIN) ){ + end(); + } else { + _running = true; + pinMode(_MOSI, OUTPUT); + pinMode(_MISO, INPUT); + pinMode(_SCK, OUTPUT); + pinMode(_SS, OUTPUT); + _MOSI_PORT = portOutputRegister(MOSIport); + _MOSI_HIGH = digitalPinToBitMask(_MOSI); + _MOSI_LOW = ~_MOSI_HIGH; + _SCK_PORT = portOutputRegister(SCKport); + _SCK_HIGH = digitalPinToBitMask(_SCK); + _SCK_LOW = ~_SCK_HIGH; + _SS_PORT = portOutputRegister(SSport); + _SS_HIGH = digitalPinToBitMask(_SS); + _SS_LOW = ~_SS_HIGH; + _MISO_PIN = portInputRegister(MISOport); + _MISO_MASK = digitalPinToBitMask(_MISO); + *_SS_PORT |= _SS_HIGH; + *_SCK_PORT &= _SCK_LOW; + *_MOSI_PORT &= _MOSI_LOW; + + //Default to Mode0. + _mode = SPI_MODE0; + transferType = &SoftSPIClass::transferMode0; + } +} + +byte SoftSPIClass::noTransfer(byte _data){ + //This does nothing. If you call SPI.transfer() before calling begin() or after calling end(), the call will be redirected here to avoid crash. + return 0xFF; +} + +byte SoftSPIClass::transferMode0(byte _data){ + byte _newData = 0; + for (byte i = 0;i < 8; i++){ + if(_data & 0x80){ + *_MOSI_PORT |= _MOSI_HIGH; + } else { + *_MOSI_PORT &= _MOSI_LOW; + } + _data <<= 1; + *_SCK_PORT |= _SCK_HIGH; + _newData <<= 1; + _newData |= ((*_MISO_PIN & _MISO_MASK) ? 1 : 0); + *_SCK_PORT &= _SCK_LOW; + } + return _newData; +} +byte SoftSPIClass::transferMode1(byte _data){ + byte _newData = 0; + for (byte i = 0;i < 8; i++){ + *_SCK_PORT |= _SCK_HIGH; + if(_data & 0x80){ + *_MOSI_PORT |= _MOSI_HIGH; + } else { + *_MOSI_PORT &= _MOSI_LOW; + } + _data <<= 1; + *_SCK_PORT &= _SCK_LOW; + _newData <<= 1; + _newData |= ((*_MISO_PIN & _MISO_MASK) ? 1 : 0); + } + return _newData; +} +byte SoftSPIClass::transferMode2(byte _data){ + byte _newData = 0; + for (byte i = 0;i < 8; i++){ + if(_data & 0x80){ + *_MOSI_PORT |= _MOSI_HIGH; + } else { + *_MOSI_PORT &= _MOSI_LOW; + } + _data <<= 1; + *_SCK_PORT &= _SCK_LOW; + _newData <<= 1; + _newData |= ((*_MISO_PIN & _MISO_MASK) ? 1 : 0); + *_SCK_PORT |= _SCK_HIGH; + } + return _newData; +} +byte SoftSPIClass::transferMode3(byte _data){ + byte _newData = 0; + for (byte i = 0;i < 8; i++){ + *_SCK_PORT &= _SCK_LOW; + if(_data & 0x80){ + *_MOSI_PORT |= _MOSI_HIGH; + } else { + *_MOSI_PORT &= _MOSI_LOW; + } + _data <<= 1; + *_SCK_PORT |= _SCK_HIGH; + _newData <<= 1; + _newData |= ((*_MISO_PIN & _MISO_MASK) ? 1 : 0); + } + return _newData; +} + +byte SoftSPIClass::transfer(byte _data){ + byte _newData = 0; + byte oldSREG = SREG; + cli(); + if (_bitOrder == MSBFIRST){ + //Send data + _newData = (*this.*transferType)(_data); + SREG = oldSREG; + return _newData; + } else { + //flip the data + for(byte i = 0; i < 8; i++){ + _newData <<= 1; + _newData |= _data & 1; + _data >>= 1; + } + //SPI transfer + _newData = (*this.*transferType)(_newData); + SREG = oldSREG; + //flip data back. + _data = 0; + for(byte i = 0; i < 8; i++){ + _data <<= 1; + _data |= _newData & 1; + _newData >>= 1; + } + return _data; + } +} + +void SoftSPIClass::end(){ + _running = false; + transferType = &SoftSPIClass::noTransfer; +} + +void SoftSPIClass::setBitOrder(uint8_t bitOrder) { + _bitOrder = bitOrder; +} + +void SoftSPIClass::setDataMode(uint8_t mode) +{ + _mode = mode; + if(_mode == SPI_MODE0){ + transferType = &SoftSPIClass::transferMode0; + } else if (_mode == SPI_MODE1){ + transferType = &SoftSPIClass::transferMode1; + } else if (_mode == SPI_MODE2){ + transferType = &SoftSPIClass::transferMode2; + } else if (_mode == SPI_MODE3){ + transferType = &SoftSPIClass::transferMode3; + } else { + _mode = SPI_MODE0; + transferType = &SoftSPIClass::transferMode0; + } + if(_mode & 0x02){ + *_SCK_PORT |= _SCK_HIGH; + } else { + *_SCK_PORT &= _SCK_LOW; + } +} + +void SoftSPIClass::setClockDivider(uint8_t rate) +{ + + //does nothing as the speed cannot be changed - fixed at Fcpu/16 + +} + +SoftSPIClass SPI; \ No newline at end of file diff --git a/hardware/digistump/avr/cores/pro/TinySoftwareSPI.h b/hardware/digistump/avr/cores/pro/TinySoftwareSPI.h new file mode 100644 index 0000000..f8cd85d --- /dev/null +++ b/hardware/digistump/avr/cores/pro/TinySoftwareSPI.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2012 by Thomas Carpenter + * Software based SPI Master Library for Tiny core. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of either the GNU General Public License version 2 + * or the GNU Lesser General Public License version 2.1, both as + * published by the Free Software Foundation. + */ + +#ifndef _SPI_H_INCLUDED +//Uses the same guard as the SPI class as the two cannot be used together +#define _SPI_H_INCLUDED + +#include +#include + +#define SPI_MODE0 0 +#define SPI_MODE1 1 +#define SPI_MODE2 2 +#define SPI_MODE3 3 + +#define SPI_CLOCK_DIV4 0x00 +#define SPI_CLOCK_DIV16 0x01 +#define SPI_CLOCK_DIV64 0x02 +#define SPI_CLOCK_DIV128 0x03 +#define SPI_CLOCK_DIV2 0x04 +#define SPI_CLOCK_DIV8 0x05 +#define SPI_CLOCK_DIV32 0x06 + +class SoftSPIClass; +typedef byte (SoftSPIClass::*TransferFunction)(byte _data); + +class SoftSPIClass { +public: + SoftSPIClass(); +private: + TransferFunction transferType; + byte noTransfer(byte _data); + byte transferMode0(byte _data); + byte transferMode1(byte _data); + byte transferMode2(byte _data); + byte transferMode3(byte _data); +public: + byte transfer(byte _data); + + // SPI Configuration methods + #if defined(SS) && defined(MOSI) && defined(MISO) && defined(SCK) + void begin(); // Default to the preset SPI pins + #endif + void begin(byte SCK_, byte MOSI_, byte MISO_, byte SS_); //No SS specified, so require pin designation + void end(); + + void setBitOrder(uint8_t); + void setDataMode(uint8_t); + void setClockDivider(uint8_t); + + void writeSS(boolean state); +private: + byte _rate; + byte _bitOrder; + byte _mode; + boolean _running; + byte _SS; + byte _SCK; + byte _MISO; + byte _MOSI; + volatile uint8_t* _MOSI_PORT; + volatile uint8_t* _SS_PORT; + volatile uint8_t* _SCK_PORT; + volatile uint8_t* _MISO_PIN; + byte _SS_HIGH; + byte _MOSI_HIGH; + byte _SCK_HIGH; + byte _SS_LOW; + byte _MOSI_LOW; + byte _SCK_LOW; + byte _MISO_MASK; +}; + +extern SoftSPIClass SPI; + +#endif \ No newline at end of file diff --git a/hardware/digistump/avr/cores/pro/TinySoftwareSerial.cpp b/hardware/digistump/avr/cores/pro/TinySoftwareSerial.cpp new file mode 100644 index 0000000..93c96c9 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/TinySoftwareSerial.cpp @@ -0,0 +1,266 @@ +/* + TinySoftwareSerial.cpp - Hardware serial library for Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 23 November 2006 by David A. Mellis + Modified 28 September 2010 by Mark Sproul +*/ + +#include +#include +#include +#include + +#include "Arduino.h" +#include "wiring_private.h" + +#if USE_SOFTWARE_SERIAL +#include "TinySoftwareSerial.h" + +// Define constants and variables for buffering incoming serial data. We're +// using a ring buffer (I think), in which rx_buffer_head is the index of the +// location to which to write the next incoming character and rx_buffer_tail +// is the index of the location from which to read. + +extern "C"{ +uint8_t getch() { + uint8_t ch = 0; + __asm__ __volatile__ ( + " rcall uartDelay\n" // Get to 0.25 of start bit (our baud is too fast, so give room to correct) + "1: rcall uartDelay\n" // Wait 0.25 bit period + " rcall uartDelay\n" // Wait 0.25 bit period + " rcall uartDelay\n" // Wait 0.25 bit period + " rcall uartDelay\n" // Wait 0.25 bit period + " clc\n" + " in r23,%[pin]\n" + " and r23, %[mask]\n" + " breq 2f\n" + " sec\n" + "2: ror %0\n" + " dec %[count]\n" + " breq 3f\n" + " rjmp 1b\n" + "3: rcall uartDelay\n" // Wait 0.25 bit period + " rcall uartDelay\n" // Wait 0.25 bit period + : + "=r" (ch) + : + "0" ((uint8_t)0), + [count] "r" ((uint8_t)8), + [pin] "I" (_SFR_IO_ADDR(ANALOG_COMP_PIN)), + [mask] "r" (Serial._rxmask) + : + "r23", + "r24", + "r25" + ); + return ch; +} + +void uartDelay() { + __asm__ __volatile__ ( + "mov r25,%[count]\n" + "1:dec r25\n" + "brne 1b\n" + "ret\n" + ::[count] "r" ((uint8_t)Serial._delayCount) + ); +} + +#if !defined (ANALOG_COMP_vect) && defined(ANA_COMP_vect) +//rename the vector so we can use it. + #define ANALOG_COMP_vect ANA_COMP_vect +#elif !defined (ANALOG_COMP_vect) + #error Tiny Software Serial cant find the Analog comparator interrupt vector! +#endif +ISR(ANALOG_COMP_vect){ + char ch = getch(); //read in the character softwarily - I know its not a word, but it sounded cool, so you know what: #define softwarily 1 + store_char(ch, Serial._rx_buffer); + sbi(ACSR,ACI); //clear the flag. +} + +} +soft_ring_buffer rx_buffer = { { 0 }, 0, 0 }; + +// Constructor //////////////////////////////////////////////////////////////// + +TinySoftwareSerial::TinySoftwareSerial(soft_ring_buffer *rx_buffer, uint8_t txBit, uint8_t rxBit) +{ + _rx_buffer = rx_buffer; + + _rxmask = _BV(rxBit); + _txmask = _BV(txBit); + _txunmask = ~_txmask; + + _delayCount = 0; +} + +// Public Methods ////////////////////////////////////////////////////////////// + +void TinySoftwareSerial::begin(long baud) +{ + long tempDelay = (((F_CPU/baud)-39)/12); + if ((tempDelay > 255) || (tempDelay <= 0)){ + end(); //Cannot start as it would screw up uartDelay(). + } + _delayCount = (uint8_t)tempDelay; + cbi(ACSR,ACIE); //turn off the comparator interrupt to allow change of ACD +#ifdef ACBG + sbi(ACSR,ACBG); //enable the internal bandgap reference - used instead of AIN0 to allow it to be used for TX. +#endif + cbi(ACSR,ACD); //turn on the comparator for RX +#ifdef ACIC + cbi(ACSR,ACIC); //prevent the comparator from affecting timer1 - just to be safe. +#endif + sbi(ACSR,ACIS1); //interrupt on rising edge (this means RX has gone from Mark state to Start bit state). + sbi(ACSR,ACIS0); + //Setup the pins in case someone messed with them. + ANALOG_COMP_DDR &= ~_rxmask; //set RX to an input + ANALOG_COMP_PORT |= _rxmask; //enable pullup on RX pin - to prevent accidental interrupt triggers. + ANALOG_COMP_DDR |= _txmask; //set TX to an output. + ANALOG_COMP_PORT |= _txmask; //set TX pin high + sbi(ACSR,ACI); //clear the flag. + sbi(ACSR,ACIE); //turn on the comparator interrupt to allow us to use it for RX +#ifdef ACSRB + ACSRB = 0; //Use AIN0 as +, AIN1 as -, no hysteresis - just like ones without this register. +#endif +} + +void TinySoftwareSerial::end() +{ + sbi(ACSR,ACI); //clear the flag. + cbi(ACSR,ACIE); //turn off the comparator interrupt to allow change of ACD, and because it needs to be turned off now too! +#ifdef ACBG + cbi(ACSR,ACBG); //disable the bandgap reference +#endif + sbi(ACSR,ACD); //turn off the comparator to save power + _delayCount = 0; + _rx_buffer->head = _rx_buffer->tail; +} + +int TinySoftwareSerial::available(void) +{ + return (unsigned int)(SERIAL_BUFFER_SIZE + _rx_buffer->head - _rx_buffer->tail) % SERIAL_BUFFER_SIZE; +} + +void store_char(unsigned char c, soft_ring_buffer *buffer) +{ + int i = (unsigned int)(buffer->head + 1) % SERIAL_BUFFER_SIZE; + + // if we should be storing the received character into the location + // just before the tail (meaning that the head would advance to the + // current location of the tail), we're about to overflow the buffer + // and so we don't write the character or advance the head. + if (i != buffer->tail) { + buffer->buffer[buffer->head] = c; + buffer->head = i; + } +} + +int TinySoftwareSerial::peek(void) +{ + if (_rx_buffer->head == _rx_buffer->tail) { + return -1; + } else { + return _rx_buffer->buffer[_rx_buffer->tail]; + } +} + +int TinySoftwareSerial::read(void) +{ + // if the head isn't ahead of the tail, we don't have any characters + if (_rx_buffer->head == _rx_buffer->tail) { + return -1; + } else { + unsigned char c = _rx_buffer->buffer[_rx_buffer->tail]; + _rx_buffer->tail = (unsigned int)(_rx_buffer->tail + 1) % SERIAL_BUFFER_SIZE; + return c; + } +} + +size_t TinySoftwareSerial::write(uint8_t ch) +{ + uint8_t oldSREG = SREG; + cli(); //Prevent interrupts from breaking the transmission. Note: TinySoftwareSerial is half duplex. + //it can either recieve or send, not both (because recieving requires an interrupt and would stall transmission + __asm__ __volatile__ ( + " com %[ch]\n" // ones complement, carry set + " sec\n" + "1: brcc 2f\n" + " in r23,%[uartPort] \n" + " and r23,%[uartUnmask]\n" + " out %[uartPort],r23 \n" + " rjmp 3f\n" + "2: in r23,%[uartPort] \n" + " or r23,%[uartMask]\n" + " out %[uartPort],r23 \n" + " nop\n" + "3: rcall uartDelay\n" + " rcall uartDelay\n" + " rcall uartDelay\n" + " rcall uartDelay\n" + " lsr %[ch]\n" + " dec %[count]\n" + " brne 1b\n" + : + : + [ch] "r" (ch), + [count] "r" ((uint8_t)10), + [uartPort] "I" (_SFR_IO_ADDR(ANALOG_COMP_PORT)), + [uartMask] "r" (_txmask), + [uartUnmask] "r" (_txunmask) + : "r23", + "r24", + "r25" + ); + SREG = oldSREG; + return 1; +} + +void TinySoftwareSerial::flush() +{ + +} + +TinySoftwareSerial::operator bool() { + return true; +} + +// Preinstantiate Objects ////////////////////////////////////////////////////// +#ifndef ANALOG_COMP_DDR +#error Please define ANALOG_COMP_DDR in the pins_arduino.h file! +#endif + +#ifndef ANALOG_COMP_PORT +#error Please define ANALOG_COMP_PORT in the pins_arduino.h file! +#endif + +#ifndef ANALOG_COMP_PIN +#error Please define ANALOG_COMP_PIN in the pins_arduino.h file! +#endif + +#ifndef ANALOG_COMP_AIN0_BIT +#error Please define ANALOG_COMP_AIN0_BIT in the pins_arduino.h file! +#endif + +#ifndef ANALOG_COMP_AIN1_BIT +#error Please define ANALOG_COMP_AIN1_BIT in the pins_arduino.h file! +#endif + +TinySoftwareSerial Serial(&rx_buffer, ANALOG_COMP_AIN0_BIT, ANALOG_COMP_AIN1_BIT); + +#endif // whole file diff --git a/hardware/digistump/avr/cores/pro/TinySoftwareSerial.h b/hardware/digistump/avr/cores/pro/TinySoftwareSerial.h new file mode 100644 index 0000000..f143211 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/TinySoftwareSerial.h @@ -0,0 +1,61 @@ + +#if USE_SOFTWARE_SERIAL +#ifndef TinySoftwareSerial_h +#define TinySoftwareSerial_h +#include +#include "Stream.h" + +#if !defined(ACSR) && defined(ACSRA) +#define ACSR ACSRA +#endif + +#if (RAMEND < 250) + #define SERIAL_BUFFER_SIZE 8 +#elif (RAMEND < 500) + #define SERIAL_BUFFER_SIZE 16 +#elif (RAMEND < 1000) + #define SERIAL_BUFFER_SIZE 32 +#else + #define SERIAL_BUFFER_SIZE 128 +#endif +struct soft_ring_buffer +{ + unsigned char buffer[SERIAL_BUFFER_SIZE]; + int head; + int tail; +}; + +extern "C"{ + void uartDelay() __attribute__ ((naked)); + uint8_t getch(); + void store_char(unsigned char c, soft_ring_buffer *buffer); +} + +class TinySoftwareSerial : public Stream +{ + public: //should be private but needed by extern "C" {} functions. + uint8_t _rxmask; + uint8_t _txmask; + uint8_t _txunmask; + soft_ring_buffer *_rx_buffer; + uint8_t _delayCount; + public: + TinySoftwareSerial(soft_ring_buffer *rx_buffer, uint8_t txBit, uint8_t rxBit); + void begin(long); + void end(); + virtual int available(void); + virtual int peek(void); + virtual int read(void); + virtual void flush(void); + virtual size_t write(uint8_t); + using Print::write; // pull in write(str) and write(buf, size) from Print + operator bool(); +}; + +#if (!defined(UBRRH) && !defined(UBRR0H)) || USE_SOFTWARE_SERIAL + extern TinySoftwareSerial Serial; +#endif + +//extern void putch(uint8_t); +#endif +#endif diff --git a/hardware/digistump/avr/cores/pro/Tone.cpp b/hardware/digistump/avr/cores/pro/Tone.cpp new file mode 100644 index 0000000..b6f4c23 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/Tone.cpp @@ -0,0 +1,546 @@ +/* Tone.cpp + + A Tone Generator Library + + Written by Brett Hagman + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +Version Modified By Date Comments +------- ----------- -------- -------- +0001 B Hagman 09/08/02 Initial coding +0002 B Hagman 09/08/18 Multiple pins +0003 B Hagman 09/08/18 Moved initialization from constructor to begin() +0004 B Hagman 09/09/26 Fixed problems with ATmega8 +0005 B Hagman 09/11/23 Scanned prescalars for best fit on 8 bit timers + 09/11/25 Changed pin toggle method to XOR + 09/11/25 Fixed timer0 from being excluded +0006 D Mellis 09/12/29 Replaced objects with functions +0007 B Cook 10/05/03 Rewritten to only work with Timer1 and support direct hardware output +0008 B Cook 10/05/03 Rewritten so the timer can be selected at compile time +0009 T Carpenter 12/08/06 Rewritten to remove requirement for all the wierd timer name creation macros. + +*************************************************/ + +#include +#include "Arduino.h" +#include "wiring_private.h" +#include "pins_arduino.h" + +// timerx_toggle_count: +// > 0 - duration specified +// = 0 - stopped +// < 0 - infinitely (until stop() method called, or new play() called) + +static volatile long tone_timer_toggle_count; +static volatile uint8_t *tone_timer_pin_register; +static volatile uint8_t tone_timer_pin_mask; + +static uint8_t tone_pin = 255; + + +void tone( uint8_t _pin, unsigned int frequency, unsigned long duration ) +{ + if ( tone_pin == 255 ) + { + /* Set the timer to power-up conditions so we start from a known state */ + // Ensure the timer is in the same state as power-up + #if (TIMER_TO_USE_FOR_TONE == 0) + TCCR0B = (0< 0 ) + { + /* Determine which prescaler to use */ + /* Set the Output Compare Register (rounding up) */ + + #if TIMER_TO_USE_FOR_TONE == 1 + uint16_t ocr = F_CPU / frequency / 2; + #if defined(TCCR1E) + uint8_t prescalarbits = 0b0001; + if (ocr > 256) + { + ocr >>= 3; //divide by 8 + prescalarbits = 0b0100; // ck/8 + if (ocr > 256) + { + ocr >>= 3; //divide by a further 8 + prescalarbits = 0b0111; //ck/64 + if (ocr > 256) + { + ocr >>= 2; //divide by a further 4 + prescalarbits = 0b1001; //ck/256 + if (ocr > 256) + { + // can't do any better than /1024 + ocr >>= 2; //divide by a further 4 + prescalarbits = 0b1011; //ck/1024 + } + } + } + } + #else + #if defined(TCCR1) + uint8_t prescalarbits = 0b0001; + #else + uint8_t prescalarbits = 0b001; + #endif + if (ocr > 0xffff) + { + ocr /= 64; + #if defined(TCCR1) + prescalarbits = 0b0111; + #else + prescalarbits = 0b011; + #endif + } + #endif + ocr -= 1; //Note we are doing the subtraction of 1 here to save repeatedly calculating ocr from just the frequency in the if tree above + OCR1A = ocr; + + #elif TIMER_TO_USE_FOR_TONE == 0 + uint16_t ocr = F_CPU / frequency / 2; + uint8_t prescalarbits = 0b001; // ck/1 + if (ocr > 256) + { + ocr >>= 3; //divide by 8 + prescalarbits = 0b010; // ck/8 + if (ocr > 256) + { + ocr >>= 3; //divide by a further 8 + prescalarbits = 0b011; //ck/64 + if (ocr > 256) + { + ocr >>= 2; //divide by a further 4 + prescalarbits = 0b100; //ck/256 + if (ocr > 256) + { + // can't do any better than /1024 + ocr >>= 2; //divide by a further 4 + prescalarbits = 0b101; //ck/1024 + } + } + } + } + ocr -= 1; //Note we are doing the subtraction of 1 here to save repeatedly calculating ocr from just the frequency in the if tree above + OCR0A = ocr; + #endif + + /* Does the caller want a specific duration? */ + if ( duration > 0 ) + { + /* Determine how many times the value toggles */ + tone_timer_toggle_count = (2 * frequency * duration) / 1000; + /* Output Compare A Match Interrupt Enable */ + #if (TIMER_TO_USE_FOR_TONE == 1) + #if defined (TIMSK) + TIMSK |= (1< 0 ) + { + --tone_timer_toggle_count; + + if ( tone_timer_toggle_count == 0 ) + { + // Shutdown the hardware + noTone( 255 ); + + // Skip the rest. We're finished. + return; + } + } + *tone_timer_pin_register ^= tone_timer_pin_mask; + } + else + { + // Shutdown the hardware + noTone( 255 ); + } +} diff --git a/hardware/digistump/avr/cores/pro/WCharacter.h b/hardware/digistump/avr/cores/pro/WCharacter.h new file mode 100644 index 0000000..79733b5 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/WCharacter.h @@ -0,0 +1,168 @@ +/* + WCharacter.h - Character utility functions for Wiring & Arduino + Copyright (c) 2010 Hernando Barragan. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Character_h +#define Character_h + +#include + +// WCharacter.h prototypes +inline boolean isAlphaNumeric(int c) __attribute__((always_inline)); +inline boolean isAlpha(int c) __attribute__((always_inline)); +inline boolean isAscii(int c) __attribute__((always_inline)); +inline boolean isWhitespace(int c) __attribute__((always_inline)); +inline boolean isControl(int c) __attribute__((always_inline)); +inline boolean isDigit(int c) __attribute__((always_inline)); +inline boolean isGraph(int c) __attribute__((always_inline)); +inline boolean isLowerCase(int c) __attribute__((always_inline)); +inline boolean isPrintable(int c) __attribute__((always_inline)); +inline boolean isPunct(int c) __attribute__((always_inline)); +inline boolean isSpace(int c) __attribute__((always_inline)); +inline boolean isUpperCase(int c) __attribute__((always_inline)); +inline boolean isHexadecimalDigit(int c) __attribute__((always_inline)); +inline int toAscii(int c) __attribute__((always_inline)); +inline int toLowerCase(int c) __attribute__((always_inline)); +inline int toUpperCase(int c)__attribute__((always_inline)); + + +// Checks for an alphanumeric character. +// It is equivalent to (isalpha(c) || isdigit(c)). +inline boolean isAlphaNumeric(int c) +{ + return ( isalnum(c) == 0 ? false : true); +} + + +// Checks for an alphabetic character. +// It is equivalent to (isupper(c) || islower(c)). +inline boolean isAlpha(int c) +{ + return ( isalpha(c) == 0 ? false : true); +} + + +// Checks whether c is a 7-bit unsigned char value +// that fits into the ASCII character set. +inline boolean isAscii(int c) +{ + return ( isascii (c) == 0 ? false : true); +} + + +// Checks for a blank character, that is, a space or a tab. +inline boolean isWhitespace(int c) +{ + return ( isblank (c) == 0 ? false : true); +} + + +// Checks for a control character. +inline boolean isControl(int c) +{ + return ( iscntrl (c) == 0 ? false : true); +} + + +// Checks for a digit (0 through 9). +inline boolean isDigit(int c) +{ + return ( isdigit (c) == 0 ? false : true); +} + + +// Checks for any printable character except space. +inline boolean isGraph(int c) +{ + return ( isgraph (c) == 0 ? false : true); +} + + +// Checks for a lower-case character. +inline boolean isLowerCase(int c) +{ + return (islower (c) == 0 ? false : true); +} + + +// Checks for any printable character including space. +inline boolean isPrintable(int c) +{ + return ( isprint (c) == 0 ? false : true); +} + + +// Checks for any printable character which is not a space +// or an alphanumeric character. +inline boolean isPunct(int c) +{ + return ( ispunct (c) == 0 ? false : true); +} + + +// Checks for white-space characters. For the avr-libc library, +// these are: space, formfeed ('\f'), newline ('\n'), carriage +// return ('\r'), horizontal tab ('\t'), and vertical tab ('\v'). +inline boolean isSpace(int c) +{ + return ( isspace (c) == 0 ? false : true); +} + + +// Checks for an uppercase letter. +inline boolean isUpperCase(int c) +{ + return ( isupper (c) == 0 ? false : true); +} + + +// Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7 +// 8 9 a b c d e f A B C D E F. +inline boolean isHexadecimalDigit(int c) +{ + return ( isxdigit (c) == 0 ? false : true); +} + + +// Converts c to a 7-bit unsigned char value that fits into the +// ASCII character set, by clearing the high-order bits. +inline int toAscii(int c) +{ + return toascii (c); +} + + +// Warning: +// Many people will be unhappy if you use this function. +// This function will convert accented letters into random +// characters. + +// Converts the letter c to lower case, if possible. +inline int toLowerCase(int c) +{ + return tolower (c); +} + + +// Converts the letter c to upper case, if possible. +inline int toUpperCase(int c) +{ + return toupper (c); +} + +#endif \ No newline at end of file diff --git a/hardware/digistump/avr/cores/pro/WInterrupts.c b/hardware/digistump/avr/cores/pro/WInterrupts.c new file mode 100644 index 0000000..eb6687b --- /dev/null +++ b/hardware/digistump/avr/cores/pro/WInterrupts.c @@ -0,0 +1,155 @@ +/* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */ + +/* + Part of the Wiring project - http://wiring.uniandes.edu.co + + Copyright (c) 2004-05 Hernando Barragan + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + Modified 24 November 2006 by David A. Mellis + + Modified 28-08-2009 for attiny84 R.Wiersma + Modified 09-10-2009 for attiny45 A.Saporetti + Modified 20-11-2010 - B.Cook - Correct a minor bug in attachInterrupt +*/ + +#include +#include +#include +#include +#include + +#include "wiring_private.h" + +volatile static voidFuncPtr intFunc[NUMBER_EXTERNAL_INTERRUPTS]; + +#if defined( MCUCR ) && ! defined( EICRA ) + #define EICRA MCUCR +#endif + +#if defined( GIMSK ) && ! defined( EIMSK ) + #define EIMSK GIMSK +#endif + +void attachInterrupt(uint8_t interruptNum, void (*userFunc)(void), int mode) +{ + if ( interruptNum < NUMBER_EXTERNAL_INTERRUPTS ) + { + /* + If attachInterrupt is called in succession for the same + interruptNum but a different userFunc then the following line + is not safe. Changing intFunc is not atomic. + intFunc[interruptNum] = userFunc; + */ + { + // save interrupt flag + uint8_t SaveSREG = SREG; + // disable interrupts + cli(); + // access the shared data + intFunc[interruptNum] = userFunc; + // restore the interrupt flag + SREG = SaveSREG; + } + + // Configure the interrupt mode (trigger on low input, any change, rising + // edge, or falling edge). The mode constants were chosen to correspond + // to the configuration bits in the hardware register, so we simply shift + // the mode into place. + + // Enable the interrupt. + + switch ( interruptNum ) + { + #if NUMBER_EXTERNAL_INTERRUPTS >= 1 + case EXTERNAL_INTERRUPT_0: + EICRA = (EICRA & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00); + EIMSK |= (1 << INT0); + break; + #endif + + #if NUMBER_EXTERNAL_INTERRUPTS >= 2 && !defined(ISC11) + //For ATtiny861, but interrupts share the same vector. + case EXTERNAL_INTERRUPT_1: + EICRA = (EICRA & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00); + EIMSK |= (1 << INT1); + break; + #endif + + #if NUMBER_EXTERNAL_INTERRUPTS >= 2 && defined(ISC11) + case EXTERNAL_INTERRUPT_1: + EICRA = (EICRA & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10); + EIMSK |= (1 << INT1); + break; + #endif + + #if NUMBER_EXTERNAL_INTERRUPTS > 2 + #error Add handlers for the additional interrupts. + #endif + } + } +} + +void detachInterrupt(uint8_t interruptNum) +{ + if ( interruptNum < NUMBER_EXTERNAL_INTERRUPTS ) + { + // Disable the interrupt. (We can't assume that interruptNum is equal + // to the number of the EIMSK bit to clear, as this isn't true on the + // ATmega8. There, INT0 is 6 and INT1 is 7.) + + switch (interruptNum) + { + #if NUMBER_EXTERNAL_INTERRUPTS >= 1 + case EXTERNAL_INTERRUPT_0: + EIMSK &= ~(1 << INT0); + break;; + #endif + + #if NUMBER_EXTERNAL_INTERRUPTS >= 2 + case EXTERNAL_INTERRUPT_1: + EIMSK &= ~(1 << INT1); + break;; + #endif + + #if NUMBER_EXTERNAL_INTERRUPTS > 2 + #error Add handlers for the additional interrupts. + #endif + } + intFunc[interruptNum] = 0; + } +} + +#if NUMBER_EXTERNAL_INTERRUPTS >= 1 +ISR(EXTERNAL_INTERRUPT_0_vect) +{ + if(intFunc[EXTERNAL_INTERRUPT_0]) + intFunc[EXTERNAL_INTERRUPT_0](); +} +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 2 +ISR(EXTERNAL_INTERRUPT_1_vect) +{ + if(intFunc[EXTERNAL_INTERRUPT_1]) + intFunc[EXTERNAL_INTERRUPT_1](); +} +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS > 2 +#error Add handlers for the additional interrupts. +#endif diff --git a/hardware/digistump/avr/cores/pro/WMath.cpp b/hardware/digistump/avr/cores/pro/WMath.cpp new file mode 100644 index 0000000..2120c4c --- /dev/null +++ b/hardware/digistump/avr/cores/pro/WMath.cpp @@ -0,0 +1,60 @@ +/* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */ + +/* + Part of the Wiring project - http://wiring.org.co + Copyright (c) 2004-06 Hernando Barragan + Modified 13 August 2006, David A. Mellis for Arduino - http://www.arduino.cc/ + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id$ +*/ + +extern "C" { + #include "stdlib.h" +} + +void randomSeed(unsigned int seed) +{ + if (seed != 0) { + srandom(seed); + } +} + +long random(long howbig) +{ + if (howbig == 0) { + return 0; + } + return random() % howbig; +} + +long random(long howsmall, long howbig) +{ + if (howsmall >= howbig) { + return howsmall; + } + long diff = howbig - howsmall; + return random(diff) + howsmall; +} + +long map(long x, long in_min, long in_max, long out_min, long out_max) +{ + return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min; +} + +unsigned int makeWord(unsigned int w) { return w; } +unsigned int makeWord(unsigned char h, unsigned char l) { return (h << 8) | l; } \ No newline at end of file diff --git a/hardware/digistump/avr/cores/pro/WProgram.h b/hardware/digistump/avr/cores/pro/WProgram.h new file mode 100644 index 0000000..3a14eb5 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/WProgram.h @@ -0,0 +1,2 @@ +//For compatibility with older programs +#include "Arduino.h" \ No newline at end of file diff --git a/hardware/digistump/avr/cores/pro/WString.cpp b/hardware/digistump/avr/cores/pro/WString.cpp new file mode 100644 index 0000000..ed880ce --- /dev/null +++ b/hardware/digistump/avr/cores/pro/WString.cpp @@ -0,0 +1,744 @@ +/* + WString.cpp - String library for Wiring & Arduino + ...mostly rewritten by Paul Stoffregen... + Copyright (c) 2009-10 Hernando Barragan. All rights reserved. + Copyright 2011, Paul Stoffregen, paul@pjrc.com + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "WString.h" + +/*********************************************/ +/* Constructors */ +/*********************************************/ + +String::String(const char *cstr) +{ + init(); + if (cstr) copy(cstr, strlen(cstr)); +} + +String::String(const String &value) +{ + init(); + *this = value; +} + +String::String(const __FlashStringHelper *pstr) +{ + init(); + *this = pstr; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +String::String(String &&rval) +{ + init(); + move(rval); +} +String::String(StringSumHelper &&rval) +{ + init(); + move(rval); +} +#endif + +String::String(char c) +{ + init(); + char buf[2]; + buf[0] = c; + buf[1] = 0; + *this = buf; +} + +String::String(unsigned char value, unsigned char base) +{ + init(); + char buf[1 + 8 * sizeof(unsigned char)]; + utoa(value, buf, base); + *this = buf; +} + +String::String(int value, unsigned char base) +{ + init(); + char buf[2 + 8 * sizeof(int)]; + itoa(value, buf, base); + *this = buf; +} + +String::String(unsigned int value, unsigned char base) +{ + init(); + char buf[1 + 8 * sizeof(unsigned int)]; + utoa(value, buf, base); + *this = buf; +} + +String::String(long value, unsigned char base) +{ + init(); + char buf[2 + 8 * sizeof(long)]; + ltoa(value, buf, base); + *this = buf; +} + +String::String(unsigned long value, unsigned char base) +{ + init(); + char buf[1 + 8 * sizeof(unsigned long)]; + ultoa(value, buf, base); + *this = buf; +} + +String::String(float value, unsigned char decimalPlaces) +{ + init(); + char buf[33]; + *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf); +} + +String::String(double value, unsigned char decimalPlaces) +{ + init(); + char buf[33]; + *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf); +} + +String::~String() +{ + free(buffer); +} + +/*********************************************/ +/* Memory Management */ +/*********************************************/ + +inline void String::init(void) +{ + buffer = NULL; + capacity = 0; + len = 0; +} + +void String::invalidate(void) +{ + if (buffer) free(buffer); + buffer = NULL; + capacity = len = 0; +} + +unsigned char String::reserve(unsigned int size) +{ + if (buffer && capacity >= size) return 1; + if (changeBuffer(size)) { + if (len == 0) buffer[0] = 0; + return 1; + } + return 0; +} + +unsigned char String::changeBuffer(unsigned int maxStrLen) +{ + char *newbuffer = (char *)realloc(buffer, maxStrLen + 1); + if (newbuffer) { + buffer = newbuffer; + capacity = maxStrLen; + return 1; + } + return 0; +} + +/*********************************************/ +/* Copy and Move */ +/*********************************************/ + +String & String::copy(const char *cstr, unsigned int length) +{ + if (!reserve(length)) { + invalidate(); + return *this; + } + len = length; + strcpy(buffer, cstr); + return *this; +} + +String & String::copy(const __FlashStringHelper *pstr, unsigned int length) +{ + if (!reserve(length)) { + invalidate(); + return *this; + } + len = length; + strcpy_P(buffer, (PGM_P)pstr); + return *this; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +void String::move(String &rhs) +{ + if (buffer) { + if (capacity >= rhs.len) { + strcpy(buffer, rhs.buffer); + len = rhs.len; + rhs.len = 0; + return; + } else { + free(buffer); + } + } + buffer = rhs.buffer; + capacity = rhs.capacity; + len = rhs.len; + rhs.buffer = NULL; + rhs.capacity = 0; + rhs.len = 0; +} +#endif + +String & String::operator = (const String &rhs) +{ + if (this == &rhs) return *this; + + if (rhs.buffer) copy(rhs.buffer, rhs.len); + else invalidate(); + + return *this; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +String & String::operator = (String &&rval) +{ + if (this != &rval) move(rval); + return *this; +} + +String & String::operator = (StringSumHelper &&rval) +{ + if (this != &rval) move(rval); + return *this; +} +#endif + +String & String::operator = (const char *cstr) +{ + if (cstr) copy(cstr, strlen(cstr)); + else invalidate(); + + return *this; +} + +String & String::operator = (const __FlashStringHelper *pstr) +{ + if (pstr) copy(pstr, strlen_P((PGM_P)pstr)); + else invalidate(); + + return *this; +} + +/*********************************************/ +/* concat */ +/*********************************************/ + +unsigned char String::concat(const String &s) +{ + return concat(s.buffer, s.len); +} + +unsigned char String::concat(const char *cstr, unsigned int length) +{ + unsigned int newlen = len + length; + if (!cstr) return 0; + if (length == 0) return 1; + if (!reserve(newlen)) return 0; + strcpy(buffer + len, cstr); + len = newlen; + return 1; +} + +unsigned char String::concat(const char *cstr) +{ + if (!cstr) return 0; + return concat(cstr, strlen(cstr)); +} + +unsigned char String::concat(char c) +{ + char buf[2]; + buf[0] = c; + buf[1] = 0; + return concat(buf, 1); +} + +unsigned char String::concat(unsigned char num) +{ + char buf[1 + 3 * sizeof(unsigned char)]; + itoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(int num) +{ + char buf[2 + 3 * sizeof(int)]; + itoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(unsigned int num) +{ + char buf[1 + 3 * sizeof(unsigned int)]; + utoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(long num) +{ + char buf[2 + 3 * sizeof(long)]; + ltoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(unsigned long num) +{ + char buf[1 + 3 * sizeof(unsigned long)]; + ultoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(float num) +{ + char buf[20]; + char* string = dtostrf(num, 4, 2, buf); + return concat(string, strlen(string)); +} + +unsigned char String::concat(double num) +{ + char buf[20]; + char* string = dtostrf(num, 4, 2, buf); + return concat(string, strlen(string)); +} + +unsigned char String::concat(const __FlashStringHelper * str) +{ + if (!str) return 0; + int length = strlen_P((const char *) str); + if (length == 0) return 1; + unsigned int newlen = len + length; + if (!reserve(newlen)) return 0; + strcpy_P(buffer + len, (const char *) str); + len = newlen; + return 1; +} + +/*********************************************/ +/* Concatenate */ +/*********************************************/ + +StringSumHelper & operator + (const StringSumHelper &lhs, const String &rhs) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(rhs.buffer, rhs.len)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, const char *cstr) +{ + StringSumHelper &a = const_cast(lhs); + if (!cstr || !a.concat(cstr, strlen(cstr))) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, char c) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(c)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, unsigned char num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, int num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, unsigned int num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, long num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, unsigned long num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, float num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, double num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, const __FlashStringHelper *rhs) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(rhs)) a.invalidate(); + return a; +} + +/*********************************************/ +/* Comparison */ +/*********************************************/ + +int String::compareTo(const String &s) const +{ + if (!buffer || !s.buffer) { + if (s.buffer && s.len > 0) return 0 - *(unsigned char *)s.buffer; + if (buffer && len > 0) return *(unsigned char *)buffer; + return 0; + } + return strcmp(buffer, s.buffer); +} + +unsigned char String::equals(const String &s2) const +{ + return (len == s2.len && compareTo(s2) == 0); +} + +unsigned char String::equals(const char *cstr) const +{ + if (len == 0) return (cstr == NULL || *cstr == 0); + if (cstr == NULL) return buffer[0] == 0; + return strcmp(buffer, cstr) == 0; +} + +unsigned char String::operator<(const String &rhs) const +{ + return compareTo(rhs) < 0; +} + +unsigned char String::operator>(const String &rhs) const +{ + return compareTo(rhs) > 0; +} + +unsigned char String::operator<=(const String &rhs) const +{ + return compareTo(rhs) <= 0; +} + +unsigned char String::operator>=(const String &rhs) const +{ + return compareTo(rhs) >= 0; +} + +unsigned char String::equalsIgnoreCase( const String &s2 ) const +{ + if (this == &s2) return 1; + if (len != s2.len) return 0; + if (len == 0) return 1; + const char *p1 = buffer; + const char *p2 = s2.buffer; + while (*p1) { + if (tolower(*p1++) != tolower(*p2++)) return 0; + } + return 1; +} + +unsigned char String::startsWith( const String &s2 ) const +{ + if (len < s2.len) return 0; + return startsWith(s2, 0); +} + +unsigned char String::startsWith( const String &s2, unsigned int offset ) const +{ + if (offset > len - s2.len || !buffer || !s2.buffer) return 0; + return strncmp( &buffer[offset], s2.buffer, s2.len ) == 0; +} + +unsigned char String::endsWith( const String &s2 ) const +{ + if ( len < s2.len || !buffer || !s2.buffer) return 0; + return strcmp(&buffer[len - s2.len], s2.buffer) == 0; +} + +/*********************************************/ +/* Character Access */ +/*********************************************/ + +char String::charAt(unsigned int loc) const +{ + return operator[](loc); +} + +void String::setCharAt(unsigned int loc, char c) +{ + if (loc < len) buffer[loc] = c; +} + +char & String::operator[](unsigned int index) +{ + static char dummy_writable_char; + if (index >= len || !buffer) { + dummy_writable_char = 0; + return dummy_writable_char; + } + return buffer[index]; +} + +char String::operator[]( unsigned int index ) const +{ + if (index >= len || !buffer) return 0; + return buffer[index]; +} + +void String::getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index) const +{ + if (!bufsize || !buf) return; + if (index >= len) { + buf[0] = 0; + return; + } + unsigned int n = bufsize - 1; + if (n > len - index) n = len - index; + strncpy((char *)buf, buffer + index, n); + buf[n] = 0; +} + +/*********************************************/ +/* Search */ +/*********************************************/ + +int String::indexOf(char c) const +{ + return indexOf(c, 0); +} + +int String::indexOf( char ch, unsigned int fromIndex ) const +{ + if (fromIndex >= len) return -1; + const char* temp = strchr(buffer + fromIndex, ch); + if (temp == NULL) return -1; + return temp - buffer; +} + +int String::indexOf(const String &s2) const +{ + return indexOf(s2, 0); +} + +int String::indexOf(const String &s2, unsigned int fromIndex) const +{ + if (fromIndex >= len) return -1; + const char *found = strstr(buffer + fromIndex, s2.buffer); + if (found == NULL) return -1; + return found - buffer; +} + +int String::lastIndexOf( char theChar ) const +{ + return lastIndexOf(theChar, len - 1); +} + +int String::lastIndexOf(char ch, unsigned int fromIndex) const +{ + if (fromIndex >= len) return -1; + char tempchar = buffer[fromIndex + 1]; + buffer[fromIndex + 1] = '\0'; + char* temp = strrchr( buffer, ch ); + buffer[fromIndex + 1] = tempchar; + if (temp == NULL) return -1; + return temp - buffer; +} + +int String::lastIndexOf(const String &s2) const +{ + return lastIndexOf(s2, len - s2.len); +} + +int String::lastIndexOf(const String &s2, unsigned int fromIndex) const +{ + if (s2.len == 0 || len == 0 || s2.len > len) return -1; + if (fromIndex >= len) fromIndex = len - 1; + int found = -1; + for (char *p = buffer; p <= buffer + fromIndex; p++) { + p = strstr(p, s2.buffer); + if (!p) break; + if ((unsigned int)(p - buffer) <= fromIndex) found = p - buffer; + } + return found; +} + +String String::substring(unsigned int left, unsigned int right) const +{ + if (left > right) { + unsigned int temp = right; + right = left; + left = temp; + } + String out; + if (left > len) return out; + if (right > len) right = len; + char temp = buffer[right]; // save the replaced character + buffer[right] = '\0'; + out = buffer + left; // pointer arithmetic + buffer[right] = temp; //restore character + return out; +} + +/*********************************************/ +/* Modification */ +/*********************************************/ + +void String::replace(char find, char replace) +{ + if (!buffer) return; + for (char *p = buffer; *p; p++) { + if (*p == find) *p = replace; + } +} + +void String::replace(const String& find, const String& replace) +{ + if (len == 0 || find.len == 0) return; + int diff = replace.len - find.len; + char *readFrom = buffer; + char *foundAt; + if (diff == 0) { + while ((foundAt = strstr(readFrom, find.buffer)) != NULL) { + memcpy(foundAt, replace.buffer, replace.len); + readFrom = foundAt + replace.len; + } + } else if (diff < 0) { + char *writeTo = buffer; + while ((foundAt = strstr(readFrom, find.buffer)) != NULL) { + unsigned int n = foundAt - readFrom; + memcpy(writeTo, readFrom, n); + writeTo += n; + memcpy(writeTo, replace.buffer, replace.len); + writeTo += replace.len; + readFrom = foundAt + find.len; + len += diff; + } + strcpy(writeTo, readFrom); + } else { + unsigned int size = len; // compute size needed for result + while ((foundAt = strstr(readFrom, find.buffer)) != NULL) { + readFrom = foundAt + find.len; + size += diff; + } + if (size == len) return; + if (size > capacity && !changeBuffer(size)) return; // XXX: tell user! + int index = len - 1; + while (index >= 0 && (index = lastIndexOf(find, index)) >= 0) { + readFrom = buffer + index + find.len; + memmove(readFrom + diff, readFrom, len - (readFrom - buffer)); + len += diff; + buffer[len] = 0; + memcpy(buffer + index, replace.buffer, replace.len); + index--; + } + } +} + +void String::remove(unsigned int index){ + if (index >= len) { return; } + int count = len - index; + remove(index, count); +} + +void String::remove(unsigned int index, unsigned int count){ + if (index >= len) { return; } + if (count <= 0) { return; } + if (index + count > len) { count = len - index; } + char *writeTo = buffer + index; + len = len - count; + strncpy(writeTo, buffer + index + count,len - index); + buffer[len] = 0; +} + +void String::toLowerCase(void) +{ + if (!buffer) return; + for (char *p = buffer; *p; p++) { + *p = tolower(*p); + } +} + +void String::toUpperCase(void) +{ + if (!buffer) return; + for (char *p = buffer; *p; p++) { + *p = toupper(*p); + } +} + +void String::trim(void) +{ + if (!buffer || len == 0) return; + char *begin = buffer; + while (isspace(*begin)) begin++; + char *end = buffer + len - 1; + while (isspace(*end) && end >= begin) end--; + len = end + 1 - begin; + if (begin > buffer) memcpy(buffer, begin, len); + buffer[len] = 0; +} + +/*********************************************/ +/* Parsing / Conversion */ +/*********************************************/ + +long String::toInt(void) const +{ + if (buffer) return atol(buffer); + return 0; +} + +float String::toFloat(void) const +{ + if (buffer) return float(atof(buffer)); + return 0; +} diff --git a/hardware/digistump/avr/cores/pro/WString.h b/hardware/digistump/avr/cores/pro/WString.h new file mode 100644 index 0000000..7402430 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/WString.h @@ -0,0 +1,224 @@ +/* + WString.h - String library for Wiring & Arduino + ...mostly rewritten by Paul Stoffregen... + Copyright (c) 2009-10 Hernando Barragan. All right reserved. + Copyright 2011, Paul Stoffregen, paul@pjrc.com + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef String_class_h +#define String_class_h +#ifdef __cplusplus + +#include +#include +#include +#include + +// When compiling programs with this class, the following gcc parameters +// dramatically increase performance and memory (RAM) efficiency, typically +// with little or no increase in code size. +// -felide-constructors +// -std=c++0x + +class __FlashStringHelper; +#define F(string_literal) (reinterpret_cast(PSTR(string_literal))) + +// An inherited class for holding the result of a concatenation. These +// result objects are assumed to be writable by subsequent concatenations. +class StringSumHelper; + +// The string class +class String +{ + // use a function pointer to allow for "if (s)" without the + // complications of an operator bool(). for more information, see: + // http://www.artima.com/cppsource/safebool.html + typedef void (String::*StringIfHelperType)() const; + void StringIfHelper() const {} + +public: + // constructors + // creates a copy of the initial value. + // if the initial value is null or invalid, or if memory allocation + // fails, the string will be marked as invalid (i.e. "if (s)" will + // be false). + String(const char *cstr = ""); + String(const String &str); + String(const __FlashStringHelper *str); + #ifdef __GXX_EXPERIMENTAL_CXX0X__ + String(String &&rval); + String(StringSumHelper &&rval); + #endif + explicit String(char c); + explicit String(unsigned char, unsigned char base=10); + explicit String(int, unsigned char base=10); + explicit String(unsigned int, unsigned char base=10); + explicit String(long, unsigned char base=10); + explicit String(unsigned long, unsigned char base=10); + explicit String(float, unsigned char decimalPlaces=2); + explicit String(double, unsigned char decimalPlaces=2); + ~String(void); + + // memory management + // return true on success, false on failure (in which case, the string + // is left unchanged). reserve(0), if successful, will validate an + // invalid string (i.e., "if (s)" will be true afterwards) + unsigned char reserve(unsigned int size); + inline unsigned int length(void) const {return len;} + + // creates a copy of the assigned value. if the value is null or + // invalid, or if the memory allocation fails, the string will be + // marked as invalid ("if (s)" will be false). + String & operator = (const String &rhs); + String & operator = (const char *cstr); + String & operator = (const __FlashStringHelper *str); + #ifdef __GXX_EXPERIMENTAL_CXX0X__ + String & operator = (String &&rval); + String & operator = (StringSumHelper &&rval); + #endif + + // concatenate (works w/ built-in types) + + // returns true on success, false on failure (in which case, the string + // is left unchanged). if the argument is null or invalid, the + // concatenation is considered unsucessful. + unsigned char concat(const String &str); + unsigned char concat(const char *cstr); + unsigned char concat(char c); + unsigned char concat(unsigned char c); + unsigned char concat(int num); + unsigned char concat(unsigned int num); + unsigned char concat(long num); + unsigned char concat(unsigned long num); + unsigned char concat(float num); + unsigned char concat(double num); + unsigned char concat(const __FlashStringHelper * str); + + // if there's not enough memory for the concatenated value, the string + // will be left unchanged (but this isn't signalled in any way) + String & operator += (const String &rhs) {concat(rhs); return (*this);} + String & operator += (const char *cstr) {concat(cstr); return (*this);} + String & operator += (char c) {concat(c); return (*this);} + String & operator += (unsigned char num) {concat(num); return (*this);} + String & operator += (int num) {concat(num); return (*this);} + String & operator += (unsigned int num) {concat(num); return (*this);} + String & operator += (long num) {concat(num); return (*this);} + String & operator += (unsigned long num) {concat(num); return (*this);} + String & operator += (float num) {concat(num); return (*this);} + String & operator += (double num) {concat(num); return (*this);} + String & operator += (const __FlashStringHelper *str){concat(str); return (*this);} + + friend StringSumHelper & operator + (const StringSumHelper &lhs, const String &rhs); + friend StringSumHelper & operator + (const StringSumHelper &lhs, const char *cstr); + friend StringSumHelper & operator + (const StringSumHelper &lhs, char c); + friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned char num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, int num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned int num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, long num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned long num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, float num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, double num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, const __FlashStringHelper *rhs); + + // comparison (only works w/ Strings and "strings") + operator StringIfHelperType() const { return buffer ? &String::StringIfHelper : 0; } + int compareTo(const String &s) const; + unsigned char equals(const String &s) const; + unsigned char equals(const char *cstr) const; + unsigned char operator == (const String &rhs) const {return equals(rhs);} + unsigned char operator == (const char *cstr) const {return equals(cstr);} + unsigned char operator != (const String &rhs) const {return !equals(rhs);} + unsigned char operator != (const char *cstr) const {return !equals(cstr);} + unsigned char operator < (const String &rhs) const; + unsigned char operator > (const String &rhs) const; + unsigned char operator <= (const String &rhs) const; + unsigned char operator >= (const String &rhs) const; + unsigned char equalsIgnoreCase(const String &s) const; + unsigned char startsWith( const String &prefix) const; + unsigned char startsWith(const String &prefix, unsigned int offset) const; + unsigned char endsWith(const String &suffix) const; + + // character acccess + char charAt(unsigned int index) const; + void setCharAt(unsigned int index, char c); + char operator [] (unsigned int index) const; + char& operator [] (unsigned int index); + void getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index=0) const; + void toCharArray(char *buf, unsigned int bufsize, unsigned int index=0) const + {getBytes((unsigned char *)buf, bufsize, index);} + const char * c_str() const { return buffer; } + + // search + int indexOf( char ch ) const; + int indexOf( char ch, unsigned int fromIndex ) const; + int indexOf( const String &str ) const; + int indexOf( const String &str, unsigned int fromIndex ) const; + int lastIndexOf( char ch ) const; + int lastIndexOf( char ch, unsigned int fromIndex ) const; + int lastIndexOf( const String &str ) const; + int lastIndexOf( const String &str, unsigned int fromIndex ) const; + String substring( unsigned int beginIndex ) const { return substring(beginIndex, len); }; + String substring( unsigned int beginIndex, unsigned int endIndex ) const; + + // modification + void replace(char find, char replace); + void replace(const String& find, const String& replace); + void remove(unsigned int index); + void remove(unsigned int index, unsigned int count); + void toLowerCase(void); + void toUpperCase(void); + void trim(void); + + // parsing/conversion + long toInt(void) const; + float toFloat(void) const; + +protected: + char *buffer; // the actual char array + unsigned int capacity; // the array length minus one (for the '\0') + unsigned int len; // the String length (not counting the '\0') +protected: + void init(void); + void invalidate(void); + unsigned char changeBuffer(unsigned int maxStrLen); + unsigned char concat(const char *cstr, unsigned int length); + + // copy and move + String & copy(const char *cstr, unsigned int length); + String & copy(const __FlashStringHelper *pstr, unsigned int length); + #ifdef __GXX_EXPERIMENTAL_CXX0X__ + void move(String &rhs); + #endif +}; + +class StringSumHelper : public String +{ +public: + StringSumHelper(const String &s) : String(s) {} + StringSumHelper(const char *p) : String(p) {} + StringSumHelper(char c) : String(c) {} + StringSumHelper(unsigned char num) : String(num) {} + StringSumHelper(int num) : String(num) {} + StringSumHelper(unsigned int num) : String(num) {} + StringSumHelper(long num) : String(num) {} + StringSumHelper(unsigned long num) : String(num) {} + StringSumHelper(float num) : String(num) {} + StringSumHelper(double num) : String(num) {} +}; + +#endif // __cplusplus +#endif // String_class_h diff --git a/hardware/digistump/avr/cores/pro/binary.h b/hardware/digistump/avr/cores/pro/binary.h new file mode 100644 index 0000000..af14980 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/binary.h @@ -0,0 +1,515 @@ +#ifndef Binary_h +#define Binary_h + +#define B0 0 +#define B00 0 +#define B000 0 +#define B0000 0 +#define B00000 0 +#define B000000 0 +#define B0000000 0 +#define B00000000 0 +#define B1 1 +#define B01 1 +#define B001 1 +#define B0001 1 +#define B00001 1 +#define B000001 1 +#define B0000001 1 +#define B00000001 1 +#define B10 2 +#define B010 2 +#define B0010 2 +#define B00010 2 +#define B000010 2 +#define B0000010 2 +#define B00000010 2 +#define B11 3 +#define B011 3 +#define B0011 3 +#define B00011 3 +#define B000011 3 +#define B0000011 3 +#define B00000011 3 +#define B100 4 +#define B0100 4 +#define B00100 4 +#define B000100 4 +#define B0000100 4 +#define B00000100 4 +#define B101 5 +#define B0101 5 +#define B00101 5 +#define B000101 5 +#define B0000101 5 +#define B00000101 5 +#define B110 6 +#define B0110 6 +#define B00110 6 +#define B000110 6 +#define B0000110 6 +#define B00000110 6 +#define B111 7 +#define B0111 7 +#define B00111 7 +#define B000111 7 +#define B0000111 7 +#define B00000111 7 +#define B1000 8 +#define B01000 8 +#define B001000 8 +#define B0001000 8 +#define B00001000 8 +#define B1001 9 +#define B01001 9 +#define B001001 9 +#define B0001001 9 +#define B00001001 9 +#define B1010 10 +#define B01010 10 +#define B001010 10 +#define B0001010 10 +#define B00001010 10 +#define B1011 11 +#define B01011 11 +#define B001011 11 +#define B0001011 11 +#define B00001011 11 +#define B1100 12 +#define B01100 12 +#define B001100 12 +#define B0001100 12 +#define B00001100 12 +#define B1101 13 +#define B01101 13 +#define B001101 13 +#define B0001101 13 +#define B00001101 13 +#define B1110 14 +#define B01110 14 +#define B001110 14 +#define B0001110 14 +#define B00001110 14 +#define B1111 15 +#define B01111 15 +#define B001111 15 +#define B0001111 15 +#define B00001111 15 +#define B10000 16 +#define B010000 16 +#define B0010000 16 +#define B00010000 16 +#define B10001 17 +#define B010001 17 +#define B0010001 17 +#define B00010001 17 +#define B10010 18 +#define B010010 18 +#define B0010010 18 +#define B00010010 18 +#define B10011 19 +#define B010011 19 +#define B0010011 19 +#define B00010011 19 +#define B10100 20 +#define B010100 20 +#define B0010100 20 +#define B00010100 20 +#define B10101 21 +#define B010101 21 +#define B0010101 21 +#define B00010101 21 +#define B10110 22 +#define B010110 22 +#define B0010110 22 +#define B00010110 22 +#define B10111 23 +#define B010111 23 +#define B0010111 23 +#define B00010111 23 +#define B11000 24 +#define B011000 24 +#define B0011000 24 +#define B00011000 24 +#define B11001 25 +#define B011001 25 +#define B0011001 25 +#define B00011001 25 +#define B11010 26 +#define B011010 26 +#define B0011010 26 +#define B00011010 26 +#define B11011 27 +#define B011011 27 +#define B0011011 27 +#define B00011011 27 +#define B11100 28 +#define B011100 28 +#define B0011100 28 +#define B00011100 28 +#define B11101 29 +#define B011101 29 +#define B0011101 29 +#define B00011101 29 +#define B11110 30 +#define B011110 30 +#define B0011110 30 +#define B00011110 30 +#define B11111 31 +#define B011111 31 +#define B0011111 31 +#define B00011111 31 +#define B100000 32 +#define B0100000 32 +#define B00100000 32 +#define B100001 33 +#define B0100001 33 +#define B00100001 33 +#define B100010 34 +#define B0100010 34 +#define B00100010 34 +#define B100011 35 +#define B0100011 35 +#define B00100011 35 +#define B100100 36 +#define B0100100 36 +#define B00100100 36 +#define B100101 37 +#define B0100101 37 +#define B00100101 37 +#define B100110 38 +#define B0100110 38 +#define B00100110 38 +#define B100111 39 +#define B0100111 39 +#define B00100111 39 +#define B101000 40 +#define B0101000 40 +#define B00101000 40 +#define B101001 41 +#define B0101001 41 +#define B00101001 41 +#define B101010 42 +#define B0101010 42 +#define B00101010 42 +#define B101011 43 +#define B0101011 43 +#define B00101011 43 +#define B101100 44 +#define B0101100 44 +#define B00101100 44 +#define B101101 45 +#define B0101101 45 +#define B00101101 45 +#define B101110 46 +#define B0101110 46 +#define B00101110 46 +#define B101111 47 +#define B0101111 47 +#define B00101111 47 +#define B110000 48 +#define B0110000 48 +#define B00110000 48 +#define B110001 49 +#define B0110001 49 +#define B00110001 49 +#define B110010 50 +#define B0110010 50 +#define B00110010 50 +#define B110011 51 +#define B0110011 51 +#define B00110011 51 +#define B110100 52 +#define B0110100 52 +#define B00110100 52 +#define B110101 53 +#define B0110101 53 +#define B00110101 53 +#define B110110 54 +#define B0110110 54 +#define B00110110 54 +#define B110111 55 +#define B0110111 55 +#define B00110111 55 +#define B111000 56 +#define B0111000 56 +#define B00111000 56 +#define B111001 57 +#define B0111001 57 +#define B00111001 57 +#define B111010 58 +#define B0111010 58 +#define B00111010 58 +#define B111011 59 +#define B0111011 59 +#define B00111011 59 +#define B111100 60 +#define B0111100 60 +#define B00111100 60 +#define B111101 61 +#define B0111101 61 +#define B00111101 61 +#define B111110 62 +#define B0111110 62 +#define B00111110 62 +#define B111111 63 +#define B0111111 63 +#define B00111111 63 +#define B1000000 64 +#define B01000000 64 +#define B1000001 65 +#define B01000001 65 +#define B1000010 66 +#define B01000010 66 +#define B1000011 67 +#define B01000011 67 +#define B1000100 68 +#define B01000100 68 +#define B1000101 69 +#define B01000101 69 +#define B1000110 70 +#define B01000110 70 +#define B1000111 71 +#define B01000111 71 +#define B1001000 72 +#define B01001000 72 +#define B1001001 73 +#define B01001001 73 +#define B1001010 74 +#define B01001010 74 +#define B1001011 75 +#define B01001011 75 +#define B1001100 76 +#define B01001100 76 +#define B1001101 77 +#define B01001101 77 +#define B1001110 78 +#define B01001110 78 +#define B1001111 79 +#define B01001111 79 +#define B1010000 80 +#define B01010000 80 +#define B1010001 81 +#define B01010001 81 +#define B1010010 82 +#define B01010010 82 +#define B1010011 83 +#define B01010011 83 +#define B1010100 84 +#define B01010100 84 +#define B1010101 85 +#define B01010101 85 +#define B1010110 86 +#define B01010110 86 +#define B1010111 87 +#define B01010111 87 +#define B1011000 88 +#define B01011000 88 +#define B1011001 89 +#define B01011001 89 +#define B1011010 90 +#define B01011010 90 +#define B1011011 91 +#define B01011011 91 +#define B1011100 92 +#define B01011100 92 +#define B1011101 93 +#define B01011101 93 +#define B1011110 94 +#define B01011110 94 +#define B1011111 95 +#define B01011111 95 +#define B1100000 96 +#define B01100000 96 +#define B1100001 97 +#define B01100001 97 +#define B1100010 98 +#define B01100010 98 +#define B1100011 99 +#define B01100011 99 +#define B1100100 100 +#define B01100100 100 +#define B1100101 101 +#define B01100101 101 +#define B1100110 102 +#define B01100110 102 +#define B1100111 103 +#define B01100111 103 +#define B1101000 104 +#define B01101000 104 +#define B1101001 105 +#define B01101001 105 +#define B1101010 106 +#define B01101010 106 +#define B1101011 107 +#define B01101011 107 +#define B1101100 108 +#define B01101100 108 +#define B1101101 109 +#define B01101101 109 +#define B1101110 110 +#define B01101110 110 +#define B1101111 111 +#define B01101111 111 +#define B1110000 112 +#define B01110000 112 +#define B1110001 113 +#define B01110001 113 +#define B1110010 114 +#define B01110010 114 +#define B1110011 115 +#define B01110011 115 +#define B1110100 116 +#define B01110100 116 +#define B1110101 117 +#define B01110101 117 +#define B1110110 118 +#define B01110110 118 +#define B1110111 119 +#define B01110111 119 +#define B1111000 120 +#define B01111000 120 +#define B1111001 121 +#define B01111001 121 +#define B1111010 122 +#define B01111010 122 +#define B1111011 123 +#define B01111011 123 +#define B1111100 124 +#define B01111100 124 +#define B1111101 125 +#define B01111101 125 +#define B1111110 126 +#define B01111110 126 +#define B1111111 127 +#define B01111111 127 +#define B10000000 128 +#define B10000001 129 +#define B10000010 130 +#define B10000011 131 +#define B10000100 132 +#define B10000101 133 +#define B10000110 134 +#define B10000111 135 +#define B10001000 136 +#define B10001001 137 +#define B10001010 138 +#define B10001011 139 +#define B10001100 140 +#define B10001101 141 +#define B10001110 142 +#define B10001111 143 +#define B10010000 144 +#define B10010001 145 +#define B10010010 146 +#define B10010011 147 +#define B10010100 148 +#define B10010101 149 +#define B10010110 150 +#define B10010111 151 +#define B10011000 152 +#define B10011001 153 +#define B10011010 154 +#define B10011011 155 +#define B10011100 156 +#define B10011101 157 +#define B10011110 158 +#define B10011111 159 +#define B10100000 160 +#define B10100001 161 +#define B10100010 162 +#define B10100011 163 +#define B10100100 164 +#define B10100101 165 +#define B10100110 166 +#define B10100111 167 +#define B10101000 168 +#define B10101001 169 +#define B10101010 170 +#define B10101011 171 +#define B10101100 172 +#define B10101101 173 +#define B10101110 174 +#define B10101111 175 +#define B10110000 176 +#define B10110001 177 +#define B10110010 178 +#define B10110011 179 +#define B10110100 180 +#define B10110101 181 +#define B10110110 182 +#define B10110111 183 +#define B10111000 184 +#define B10111001 185 +#define B10111010 186 +#define B10111011 187 +#define B10111100 188 +#define B10111101 189 +#define B10111110 190 +#define B10111111 191 +#define B11000000 192 +#define B11000001 193 +#define B11000010 194 +#define B11000011 195 +#define B11000100 196 +#define B11000101 197 +#define B11000110 198 +#define B11000111 199 +#define B11001000 200 +#define B11001001 201 +#define B11001010 202 +#define B11001011 203 +#define B11001100 204 +#define B11001101 205 +#define B11001110 206 +#define B11001111 207 +#define B11010000 208 +#define B11010001 209 +#define B11010010 210 +#define B11010011 211 +#define B11010100 212 +#define B11010101 213 +#define B11010110 214 +#define B11010111 215 +#define B11011000 216 +#define B11011001 217 +#define B11011010 218 +#define B11011011 219 +#define B11011100 220 +#define B11011101 221 +#define B11011110 222 +#define B11011111 223 +#define B11100000 224 +#define B11100001 225 +#define B11100010 226 +#define B11100011 227 +#define B11100100 228 +#define B11100101 229 +#define B11100110 230 +#define B11100111 231 +#define B11101000 232 +#define B11101001 233 +#define B11101010 234 +#define B11101011 235 +#define B11101100 236 +#define B11101101 237 +#define B11101110 238 +#define B11101111 239 +#define B11110000 240 +#define B11110001 241 +#define B11110010 242 +#define B11110011 243 +#define B11110100 244 +#define B11110101 245 +#define B11110110 246 +#define B11110111 247 +#define B11111000 248 +#define B11111001 249 +#define B11111010 250 +#define B11111011 251 +#define B11111100 252 +#define B11111101 253 +#define B11111110 254 +#define B11111111 255 + +#endif diff --git a/hardware/digistump/avr/cores/pro/main.cpp b/hardware/digistump/avr/cores/pro/main.cpp new file mode 100644 index 0000000..f95ad17 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/main.cpp @@ -0,0 +1,15 @@ +#include + +int main(void) +{ + //OSCCAL = TUNED_OSCCAL_VALUE; //set the oscillator calibration value based on the pins_arduino.h file. If this is not set, it will be optimised away - it would boil down to 1 = 1; + init(); + + setup(); + + for (;;) + loop(); + + return 0; +} + diff --git a/hardware/digistump/avr/cores/pro/wiring.c b/hardware/digistump/avr/cores/pro/wiring.c new file mode 100644 index 0000000..82c8ac0 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/wiring.c @@ -0,0 +1,692 @@ +/* + wiring.c - Partial implementation of the Wiring API for the ATmega8. + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.c 970 2010-05-25 20:16:15Z dmellis $ + + Modified 28-08-2009 for attiny84 R.Wiersma + Modified 14-10-2009 for attiny45 Saposoft + Modified 20-11-2010 - B.Cook - Rewritten to use the various Veneers. +*/ + +#include "wiring_private.h" + +#if F_CPU >= 3000000L + +#if !defined(__AVR_ATtiny167__) && !defined(__AVR_ATtiny87__) +#define timer0Prescaler 0b011 +#else +#define timer0Prescaler 0b100 +#endif + +//Timers with TCCR1 are slightly different. +#if defined(TCCR1) && (TIMER_TO_USE_FOR_MILLIS == 1) + #define MillisTimer_Prescale_Index (0b0111) + #define ToneTimer_Prescale_Index (timer0Prescaler) +#elif defined(TCCR1) && (TIMER_TO_USE_FOR_MILLIS == 0) + #define MillisTimer_Prescale_Index (timer0Prescaler) + #define ToneTimer_Prescale_Index (0b0111) +#elif defined(TCCR1E) && (TIMER_TO_USE_FOR_MILLIS == 1) + #define MillisTimer_Prescale_Index (0b0111) + #define ToneTimer_Prescale_Index (timer0Prescaler) +#elif defined(TCCR1E) && (TIMER_TO_USE_FOR_MILLIS == 0) + #define MillisTimer_Prescale_Index (timer0Prescaler) + #define ToneTimer_Prescale_Index (0b0111) +#elif (TIMER_TO_USE_FOR_MILLIS == 1) + #define MillisTimer_Prescale_Index (0b011) + #define ToneTimer_Prescale_Index (timer0Prescaler) +#else + #define MillisTimer_Prescale_Index (timer0Prescaler) + #define ToneTimer_Prescale_Index (0b011) +#endif + + #define MillisTimer_Prescale_Value (64) + #define ToneTimer_Prescale_Value (64) + +#else + +#if defined(TCCR1) && (TIMER_TO_USE_FOR_MILLIS == 1) + #define MillisTimer_Prescale_Index (0b0100) + #define ToneTimer_Prescale_Index (0b010) +#elif defined(TCCR1) && (TIMER_TO_USE_FOR_MILLIS == 0) + #define MillisTimer_Prescale_Index (0b010) + #define ToneTimer_Prescale_Index (0b0100) +#elif defined(TCCR1E) && (TIMER_TO_USE_FOR_MILLIS == 1) + #define MillisTimer_Prescale_Index (0b0100) + #define ToneTimer_Prescale_Index (0b010) +#elif defined(TCCR1E) && (TIMER_TO_USE_FOR_MILLIS == 0) + #define MillisTimer_Prescale_Index (0b010) + #define ToneTimer_Prescale_Index (0b0100) +#else + #define MillisTimer_Prescale_Index (0b010) + #define ToneTimer_Prescale_Index (0b010) +#endif + + #define MillisTimer_Prescale_Value (8) + #define ToneTimer_Prescale_Value (8) + +#endif + +// the prescaler is set so that the millis timer ticks every MillisTimer_Prescale_Value (64) clock cycles, and the +// the overflow handler is called every 256 ticks. +#define MICROSECONDS_PER_MILLIS_OVERFLOW (clockCyclesToMicroseconds(MillisTimer_Prescale_Value * 256)) + +// the whole number of milliseconds per millis timer overflow +#define MILLIS_INC (MICROSECONDS_PER_MILLIS_OVERFLOW / 1000) + +// the fractional number of milliseconds per millis timer overflow. we shift right +// by three to fit these numbers into a byte. (for the clock speeds we care +// about - 8 and 16 MHz - this doesn't lose precision.) +#define FRACT_INC ((MICROSECONDS_PER_MILLIS_OVERFLOW % 1000) >> 3) +#define FRACT_MAX (1000 >> 3) + +volatile unsigned long millis_timer_overflow_count = 0; +volatile unsigned long millis_timer_millis = 0; +static unsigned char millis_timer_fract = 0; +#if (TIMER_TO_USE_FOR_MILLIS == 0) + +#if defined(TIMER0_OVF_vect) +SIGNAL(TIMER0_OVF_vect) +#elif defined(TIM0_OVF_vect) +SIGNAL(TIM0_OVF_vect) +#else +#error cannot find Millis() timer overflow vector +#endif + +#elif (TIMER_TO_USE_FOR_MILLIS == 1) + +#if defined(TIMER1_OVF_vect) +SIGNAL(TIMER1_OVF_vect) +#elif defined(TIM1_OVF_vect) +SIGNAL(TIM1_OVF_vect) +#else +#error cannot find Millis() timer overflow vector +#endif + +#else + +#error Millis() timer not defined! + +#endif +{ + // copy these to local variables so they can be stored in registers + // (volatile variables must be read from memory on every access) + unsigned long m = millis_timer_millis; + unsigned char f = millis_timer_fract; + +/* rmv: The code below generates considerably less code (emtpy Sketch is 326 versus 304)... + + m += MILLIS_INC; + f += FRACT_INC; + if (f >= FRACT_MAX) { + f -= FRACT_MAX; + m += 1; + } +...rmv */ + + f += FRACT_INC; + + if (f >= FRACT_MAX) + { + f -= FRACT_MAX; + m += 1; + m += MILLIS_INC; + } + else + { + m += MILLIS_INC; + } + + millis_timer_fract = f; + millis_timer_millis = m; + millis_timer_overflow_count++; + + +//MICROSECONDS_PER_MILLIS_OVERFLOW=2048 +//MILLIS_INC=2 +//FRACT_INC=6 +//FRACT_MAX=125 +} + +unsigned long millis() +{ + unsigned long m; + uint8_t oldSREG = SREG; + + // disable interrupts while we read millis_timer_millis or we might get an + // inconsistent value (e.g. in the middle of a write to millis_timer_millis) + cli(); + m = millis_timer_millis; + SREG = oldSREG; + + return m; +} + +unsigned long micros() +{ + unsigned long m; + uint8_t oldSREG = SREG, t; + + cli(); + m = millis_timer_overflow_count; +#if defined(TCNT0) && (TIMER_TO_USE_FOR_MILLIS == 0) && !defined(TCW0) + t = TCNT0; +#elif defined(TCNT0L) && (TIMER_TO_USE_FOR_MILLIS == 0) + t = TCNT0L; +#elif defined(TCNT1) && (TIMER_TO_USE_FOR_MILLIS == 1) + t = TCNT1; +#elif defined(TCNT1L) && (TIMER_TO_USE_FOR_MILLIS == 1) + t = TCNT1L; +#else + #error Millis()/Micros() timer not defined +#endif + +#if defined(TIFR0) && (TIMER_TO_USE_FOR_MILLIS == 0) + if ((TIFR0 & _BV(TOV0)) && (t < 255)) + m++; +#elif defined(TIFR) && (TIMER_TO_USE_FOR_MILLIS == 0) + if ((TIFR & _BV(TOV0)) && (t < 255)) + m++; +#elif defined(TIFR1) && (TIMER_TO_USE_FOR_MILLIS == 1) + if ((TIFR1 & _BV(TOV1)) && (t < 255)) + m++; +#elif defined(TIFR) && (TIMER_TO_USE_FOR_MILLIS == 1) + if ((TIFR & _BV(TOV1)) && (t < 255)) + m++; +#endif + + SREG = oldSREG; + + return ((m << 8) + t) * (MillisTimer_Prescale_Value / clockCyclesPerMicrosecond()); +} + +void delay(unsigned long ms) +{ + uint16_t start = (uint16_t)micros(); + while (ms > 0) { + if (((uint16_t)micros() - start) >= 1000) { + ms--; + start += 1000; + } + } +} + +/* Delay for the given number of microseconds. Assumes a 1, 8, 12, 16, 20 or 24 MHz clock. */ +void delayMicroseconds(unsigned int us) +{ + // call = 4 cycles + 2 to 4 cycles to init us(2 for constant delay, 4 for variable) + + // calling avrlib's delay_us() function with low values (e.g. 1 or + // 2 microseconds) gives delays longer than desired. + //delay_us(us); +#if F_CPU >= 24000000L + // for the 24 MHz clock for the aventurous ones, trying to overclock + + // zero delay fix + if (!us) return; // = 3 cycles, (4 when true) + + // the following loop takes a 1/6 of a microsecond (4 cycles) + // per iteration, so execute it six times for each microsecond of + // delay requested. + us *= 6; // x6 us, = 7 cycles + + // account for the time taken in the preceeding commands. + // we just burned 22 (24) cycles above, remove 5, (5*4=20) + // us is at least 6 so we can substract 5 + us -= 5; //=2 cycles + +#elif F_CPU >= 20000000L + // for the 20 MHz clock on rare Arduino boards + + // for a one-microsecond delay, simply return. the overhead + // of the function call takes 18 (20) cycles, which is 1us + __asm__ __volatile__ ( + "nop" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "nop"); //just waiting 4 cycles + if (us <= 1) return; // = 3 cycles, (4 when true) + + // the following loop takes a 1/5 of a microsecond (4 cycles) + // per iteration, so execute it five times for each microsecond of + // delay requested. + us = (us << 2) + us; // x5 us, = 7 cycles + + // account for the time taken in the preceeding commands. + // we just burned 26 (28) cycles above, remove 7, (7*4=28) + // us is at least 10 so we can substract 7 + us -= 7; // 2 cycles + +#elif F_CPU >= 16000000L + // for the 16 MHz clock on most Arduino boards + + // for a one-microsecond delay, simply return. the overhead + // of the function call takes 14 (16) cycles, which is 1us + if (us <= 1) return; // = 3 cycles, (4 when true) + + // the following loop takes 1/4 of a microsecond (4 cycles) + // per iteration, so execute it four times for each microsecond of + // delay requested. + us <<= 2; // x4 us, = 4 cycles + + // account for the time taken in the preceeding commands. + // we just burned 19 (21) cycles above, remove 5, (5*4=20) + // us is at least 8 so we can substract 5 + us -= 5; // = 2 cycles, + +#elif F_CPU >= 12000000L + // for the 12 MHz clock if somebody is working with USB + + // for a 1 microsecond delay, simply return. the overhead + // of the function call takes 14 (16) cycles, which is 1.5us + if (us <= 1) return; // = 3 cycles, (4 when true) + + // the following loop takes 1/3 of a microsecond (4 cycles) + // per iteration, so execute it three times for each microsecond of + // delay requested. + us = (us << 1) + us; // x3 us, = 5 cycles + + // account for the time taken in the preceeding commands. + // we just burned 20 (22) cycles above, remove 5, (5*4=20) + // us is at least 6 so we can substract 5 + us -= 5; //2 cycles + +#elif F_CPU >= 8000000L + // for the 8 MHz internal clock + + // for a 1 and 2 microsecond delay, simply return. the overhead + // of the function call takes 14 (16) cycles, which is 2us + if (us <= 2) return; // = 3 cycles, (4 when true) + + // the following loop takes 1/2 of a microsecond (4 cycles) + // per iteration, so execute it twice for each microsecond of + // delay requested. + us <<= 1; //x2 us, = 2 cycles + + // account for the time taken in the preceeding commands. + // we just burned 17 (19) cycles above, remove 4, (4*4=16) + // us is at least 6 so we can substract 4 + us -= 4; // = 2 cycles + +#else + // for the 1 MHz internal clock (default settings for common AVR microcontrollers) + + // the overhead of the function calls is 14 (16) cycles + if (us <= 16) return; //= 3 cycles, (4 when true) + if (us <= 25) return; //= 3 cycles, (4 when true), (must be at least 25 if we want to substract 22) + + // compensate for the time taken by the preceeding and next commands (about 22 cycles) + us -= 22; // = 2 cycles + // the following loop takes 4 microseconds (4 cycles) + // per iteration, so execute it us/4 times + // us is at least 4, divided by 4 gives us 1 (no zero delay bug) + us >>= 2; // us div 4, = 4 cycles + + +#endif + + // busy wait + __asm__ __volatile__ ( + "1: sbiw %0,1" "\n\t" // 2 cycles + "brne 1b" : "=w" (us) : "0" (us) // 2 cycles + ); + // return = 4 cycles +} + +#if INITIALIZE_SECONDARY_TIMERS +static void initToneTimerInternal(void) +{ + // Timer is processor clock divided by ToneTimer_Prescale_Index + #if (TIMER_TO_USE_FOR_TONE == 0) + TCCR0B &= ~((1< This is the closest you can get, the prescaler is 2 + #define ADC_ARDUINO_PRESCALER B000 +#else + #error Add an entry for the selected processor speed. +#endif + +void init(void) +{ + + // In case the bootloader left our millis timer in a bad way + #if defined( HAVE_BOOTLOADER ) && HAVE_BOOTLOADER + // Ensure the timer is in the same state as power-up + #if (TIMER_TO_USE_FOR_MILLIS == 0) && defined(WGM01) + TCCR0B = 0; + TCCR0A = 0; + // Reset the count to zero + TCNT0 = 0; + // Set the output compare registers to zero + OCR0A = 0; + #ifdef OCR0B + OCR0B = 0; + #endif + #if defined(TIMSK) + // Disable all Timer0 interrupts + TIMSK &= ~((1<= NUM_DIGITAL_PINS ) pin -= NUM_DIGITAL_PINS; // allow for channel or pin numbers + #endif + + // fix? Validate pin? + if(pin >= NUM_ANALOG_INPUTS) return 0; //Not a valid pin. + //if(pin < 4) return 9; //Not a valid pin. + #ifndef ADCSRA + return digitalRead(analogInputToDigitalPin(pin)) ? 1023 : 0; //No ADC, so read as a digital pin instead. + #endif + + #if defined(ADMUX) + #if defined(MUX4) + ADMUX = ((analog_reference & 0x03) << REFS0) | ((pin & 0x1F) << MUX0); //select the channel and reference + #elif defined(MUX3) + ADMUX = ((analog_reference & 0x03) << REFS0) | ((pin & 0x0F) << MUX0); //select the channel and reference + #else + ADMUX = ((analog_reference & 0x03) << REFS0) | ((pin & 0x07) << MUX0); //select the channel and reference + #endif + #endif + #if defined(REFS2) + ADMUX |= (((analog_reference & 0x04) >> 2) << REFS2); //some have an extra reference bit in a weird position. + #endif + + #if defined(HAVE_ADC) && HAVE_ADC + sbi(ADCSRA, ADSC); //Start conversion + + while(ADCSRA & (1<= 255) + { + digitalWrite(pin, HIGH); + } + else + { + uint8_t timer = digitalPinToTimer(pin); + + +/* + if( timer == TIMER0B){ + // connect pwm to pin on timer 0, channel B + sbi(TCCR0A, COM0B1); + cbi(TCCR0A, COM0B0); + OCR0B = val; // set pwm duty + } else +*/ + + + if( timer == TIMER1A){ + // connect pwm to pin on timer 1, channel A + sbi(TCCR1A, COM1A1); + sbi(TCCR1A, WGM10); + cbi(TCCR1A, COM1A0); + sbi(TCCR1B, WGM10); + sbi(TCCR1B, CS11); + //sbi(TCCR1B, CS10); + + cbi(TCCR1D, OC1AV); + sbi(TCCR1D, OC1AU); + cbi(TCCR1D, OC1AW); + cbi(TCCR1D, OC1AX); + + OCR1A = val; // set pwm duty + } else + + + + + + if( timer == TIMER1B){ + // connect pwm to pin on timer 1, channel B + sbi(TCCR1A, COM1B1); + sbi(TCCR1A, WGM10); + cbi(TCCR1A, COM1B0); + sbi(TCCR1B, WGM10); + sbi(TCCR1B, CS11); + //sbi(TCCR1B, CS10); + + cbi(TCCR1D, OC1BV); + sbi(TCCR1D, OC1BU); + cbi(TCCR1D, OC1BW); + cbi(TCCR1D, OC1BX); + + OCR1B = val; // set pwm duty + } else + + + + + { + if (val < 128) + { + digitalWrite(pin, LOW); + } + else + { + digitalWrite(pin, HIGH); + } + } + + } +} diff --git a/hardware/digistump/avr/cores/pro/wiring_digital.c b/hardware/digistump/avr/cores/pro/wiring_digital.c new file mode 100644 index 0000000..52fff0a --- /dev/null +++ b/hardware/digistump/avr/cores/pro/wiring_digital.c @@ -0,0 +1,160 @@ +/* + wiring_digital.c - digital input and output functions + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $ + + Modified 28-08-2009 for attiny84 R.Wiersma + Modified 14-10-2009 for attiny45 Saposoft +*/ + +#define ARDUINO_MAIN +#include "wiring_private.h" +#include "pins_arduino.h" + +void pinMode(uint8_t pin, uint8_t mode) +{ + uint8_t bit = digitalPinToBitMask(pin); + uint8_t port = digitalPinToPort(pin); + volatile uint8_t *reg, *out; + + if (port == NOT_A_PIN) return; + + reg = portModeRegister(port); + out = portOutputRegister(port); + + if (mode == INPUT) { + uint8_t oldSREG = SREG; + cli(); + *reg &= ~bit; + *out &= ~bit; + SREG = oldSREG; + } else if (mode == INPUT_PULLUP) { + uint8_t oldSREG = SREG; + cli(); + *reg &= ~bit; + *out |= bit; + SREG = oldSREG; + } else { + uint8_t oldSREG = SREG; + cli(); + *reg |= bit; + SREG = oldSREG; + } +} + +static void turnOffPWM(uint8_t timer) +{ + #if defined(TCCR0A) && defined(COM0A1) + if( timer == TIMER0A){ + cbi(TCCR0A, COM0A1); + cbi(TCCR0A, COM0A0); + } else + #endif + + #if defined(TCCR0A) && defined(COM0B1) + if( timer == TIMER0B){ + cbi(TCCR0A, COM0B1); + cbi(TCCR0A, COM0B0); + } else + #endif + + #if defined(TCCR1A) && defined(COM1A1) + if( timer == TIMER1A){ + cbi(TCCR1A, COM1A1); + cbi(TCCR1A, COM1A0); + } else + #endif + + #if defined(TCCR1) && defined(COM1A1) + if(timer == TIMER1A){ + cbi(TCCR1, COM1A1); + cbi(TCCR1, COM1A0); + #ifdef OC1AX + cbi(TCCR1D, OC1AX); + #endif + } else + #endif + + #if defined(TCCR1A) && defined(COM1B1) + if( timer == TIMER1B){ + cbi(TCCR1A, COM1B1); + cbi(TCCR1A, COM1B0); + #ifdef OC1BV + cbi(TCCR1D, OC1BV); + #endif + } else + #endif + + #if defined(TCCR1) && defined(COM1B1) + if( timer == TIMER1B){ + cbi(GTCCR, COM1B1); + cbi(GTCCR, COM1B0); + } else + #endif + + { + } + +} + +void digitalWrite(uint8_t pin, uint8_t val) +{ + uint8_t timer = digitalPinToTimer(pin); + uint8_t bit = digitalPinToBitMask(pin); + uint8_t port = digitalPinToPort(pin); + volatile uint8_t *out; + + if (port == NOT_A_PIN) return; + + // If the pin that support PWM output, we need to turn it off + // before doing a digital write. + if (timer != NOT_ON_TIMER) turnOffPWM(timer); + + out = portOutputRegister(port); + + if (val == LOW) { + uint8_t oldSREG = SREG; + cli(); + *out &= ~bit; + SREG = oldSREG; + } else { + uint8_t oldSREG = SREG; + cli(); + *out |= bit; + SREG = oldSREG; + } +} + +int digitalRead(uint8_t pin) +{ + uint8_t timer = digitalPinToTimer(pin); + uint8_t bit = digitalPinToBitMask(pin); + uint8_t port = digitalPinToPort(pin); + + if (port == NOT_A_PIN) return LOW; + + // If the pin that support PWM output, we need to turn it off + // before getting a digital reading. + if (timer != NOT_ON_TIMER) turnOffPWM(timer); + + if (*portInputRegister(port) & bit) return HIGH; + return LOW; +} diff --git a/hardware/digistump/avr/cores/pro/wiring_private.h b/hardware/digistump/avr/cores/pro/wiring_private.h new file mode 100644 index 0000000..776ac28 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/wiring_private.h @@ -0,0 +1,178 @@ +/* + wiring_private.h - Internal header file. + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.h 239 2007-01-12 17:58:39Z mellis $ + + Modified 28-08-2009 for attiny84 R.Wiersma +*/ + +#ifndef WiringPrivate_h +#define WiringPrivate_h + +#include +#include +#include +#include + +#include "Arduino.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +#ifndef cbi +#define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit)) +#endif +#ifndef sbi +#define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit)) +#endif + +#if defined( EXT_INT0_vect ) + #define EXTERNAL_INTERRUPT_0_vect EXT_INT0_vect +#elif defined( INT0_vect ) + #define EXTERNAL_INTERRUPT_0_vect INT0_vect +#endif + +#if defined( EXT_INT1_vect ) + #define EXTERNAL_INTERRUPT_1_vect EXT_INT1_vect +#elif defined( INT1_vect ) + #define EXTERNAL_INTERRUPT_1_vect INT1_vect +#endif + +#if defined( EXT_INT2_vect ) + #define EXTERNAL_INTERRUPT_2_vect EXT_INT2_vect +#elif defined( INT2_vect ) + #define EXTERNAL_INTERRUPT_2_vect INT2_vect +#endif + +#if defined( EXT_INT3_vect ) + #define EXTERNAL_INTERRUPT_3_vect EXT_INT3_vect +#elif defined( INT3_vect ) + #define EXTERNAL_INTERRUPT_3_vect INT3_vect +#endif + +#if defined( EXT_INT4_vect ) + #define EXTERNAL_INTERRUPT_4_vect EXT_INT4_vect +#elif defined( INT4_vect ) + #define EXTERNAL_INTERRUPT_4_vect INT4_vect +#endif + +#if defined( EXT_INT5_vect ) + #define EXTERNAL_INTERRUPT_5_vect EXT_INT5_vect +#elif defined( INT5_vect ) + #define EXTERNAL_INTERRUPT_5_vect INT5_vect +#endif + +#if defined( EXT_INT6_vect ) + #define EXTERNAL_INTERRUPT_6_vect EXT_INT6_vect +#elif defined( INT6_vect ) + #define EXTERNAL_INTERRUPT_6_vect INT6_vect +#endif + +#if defined( EXT_INT7_vect ) + #define EXTERNAL_INTERRUPT_7_vect EXT_INT7_vect +#elif defined( INT7_vect ) + #define EXTERNAL_INTERRUPT_7_vect INT7_vect +#endif + +#if defined( EXT_INT8_vect ) + #define EXTERNAL_INTERRUPT_8_vect EXT_INT8_vect +#elif defined( INT8_vect ) + #define EXTERNAL_INTERRUPT_8_vect INT8_vect +#endif + +#if defined( EXT_INT9_vect ) + #define EXTERNAL_INTERRUPT_9_vect EXT_INT9_vect +#elif defined( INT9_vect ) + #define EXTERNAL_INTERRUPT_9_vect INT9_vect +#endif + +#if defined( EXTERNAL_INTERRUPT_9_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (10) +#elif defined( EXTERNAL_INTERRUPT_8_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (9) +#elif defined( EXTERNAL_INTERRUPT_7_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (8) +#elif defined( EXTERNAL_INTERRUPT_6_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (7) +#elif defined( EXTERNAL_INTERRUPT_5_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (6) +#elif defined( EXTERNAL_INTERRUPT_4_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (5) +#elif defined( EXTERNAL_INTERRUPT_3_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (4) +#elif defined( EXTERNAL_INTERRUPT_2_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (3) +#elif defined( EXTERNAL_INTERRUPT_1_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (2) +#elif defined( EXTERNAL_INTERRUPT_0_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (1) +#else + #define NUMBER_EXTERNAL_INTERRUPTS (0) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 1 + #define EXTERNAL_INTERRUPT_0 (0) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 2 + #define EXTERNAL_INTERRUPT_1 (1) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 3 + #define EXTERNAL_INTERRUPT_2 (2) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 4 + #define EXTERNAL_INTERRUPT_3 (3) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 5 + #define EXTERNAL_INTERRUPT_4 (4) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 6 + #define EXTERNAL_INTERRUPT_5 (5) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 7 + #define EXTERNAL_INTERRUPT_6 (6) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 8 + #define EXTERNAL_INTERRUPT_7 (7) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 9 + #define EXTERNAL_INTERRUPT_8 (8) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 10 + #define EXTERNAL_INTERRUPT_9 (9) +#endif + +typedef void (*voidFuncPtr)(void); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/hardware/digistump/avr/cores/pro/wiring_pulse.c b/hardware/digistump/avr/cores/pro/wiring_pulse.c new file mode 100644 index 0000000..0d96886 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/wiring_pulse.c @@ -0,0 +1,69 @@ +/* + wiring_pulse.c - pulseIn() function + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $ +*/ + +#include "wiring_private.h" +#include "pins_arduino.h" + +/* Measures the length (in microseconds) of a pulse on the pin; state is HIGH + * or LOW, the type of pulse to measure. Works on pulses from 2-3 microseconds + * to 3 minutes in length, but must be called at least a few dozen microseconds + * before the start of the pulse. */ +unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout) +{ + // cache the port and bit of the pin in order to speed up the + // pulse width measuring loop and achieve finer resolution. calling + // digitalRead() instead yields much coarser resolution. + uint8_t bit = digitalPinToBitMask(pin); + uint8_t port = digitalPinToPort(pin); + uint8_t stateMask = (state ? bit : 0); + unsigned long width = 0; // keep initialization out of time critical area + + // convert the timeout from microseconds to a number of times through + // the initial loop; it takes 16 clock cycles per iteration. + unsigned long numloops = 0; + unsigned long maxloops = microsecondsToClockCycles(timeout) / 16; + + // wait for any previous pulse to end + while ((*portInputRegister(port) & bit) == stateMask) + if (numloops++ == maxloops) + return 0; + + // wait for the pulse to start + while ((*portInputRegister(port) & bit) != stateMask) + if (numloops++ == maxloops) + return 0; + + // wait for the pulse to stop + while ((*portInputRegister(port) & bit) == stateMask) { + if (numloops++ == maxloops) + return 0; + width++; + } + + // convert the reading to microseconds. The loop has been determined + // to be 20 clock cycles long and have about 16 clocks between the edge + // and the start of the loop. There will be some error introduced by + // the interrupt handlers. + return clockCyclesToMicroseconds(width * 21 + 16); +} diff --git a/hardware/digistump/avr/cores/pro/wiring_shift.c b/hardware/digistump/avr/cores/pro/wiring_shift.c new file mode 100644 index 0000000..cfe7867 --- /dev/null +++ b/hardware/digistump/avr/cores/pro/wiring_shift.c @@ -0,0 +1,55 @@ +/* + wiring_shift.c - shiftOut() function + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $ +*/ + +#include "wiring_private.h" + +uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) { + uint8_t value = 0; + uint8_t i; + + for (i = 0; i < 8; ++i) { + digitalWrite(clockPin, HIGH); + if (bitOrder == LSBFIRST) + value |= digitalRead(dataPin) << i; + else + value |= digitalRead(dataPin) << (7 - i); + digitalWrite(clockPin, LOW); + } + return value; +} + +void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t val) +{ + uint8_t i; + + for (i = 0; i < 8; i++) { + if (bitOrder == LSBFIRST) + digitalWrite(dataPin, !!(val & (1 << i))); + else + digitalWrite(dataPin, !!(val & (1 << (7 - i)))); + + digitalWrite(clockPin, HIGH); + digitalWrite(clockPin, LOW); + } +} diff --git a/hardware/digistump/avr/cores/tiny/Arduino.h b/hardware/digistump/avr/cores/tiny/Arduino.h new file mode 100644 index 0000000..b1b9d66 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/Arduino.h @@ -0,0 +1,6 @@ +#ifndef Arduino_h +#define Arduino_h + +#include + +#endif diff --git a/hardware/digistump/avr/cores/tiny/HardwareSerial.cpp b/hardware/digistump/avr/cores/tiny/HardwareSerial.cpp new file mode 100644 index 0000000..24465da --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/HardwareSerial.cpp @@ -0,0 +1,308 @@ +/* + HardwareSerial.cpp - Hardware serial library for Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 23 November 2006 by David A. Mellis + Modified 28 September 2010 by Mark Sproul +*/ + +#include +#include +#include +#include + +#include "core_build_options.h" +#include "wiring.h" +#include "wiring_private.h" + +// this next line disables the entire HardwareSerial.cpp, +// this is so I can support Attiny series and any other chip without a uart +#if defined(UBRRH) || defined(UBRR0H) || defined(UBRR1H) || defined(UBRR2H) || defined(UBRR3H) + +#include "HardwareSerial.h" + +// Define constants and variables for buffering incoming serial data. We're +// using a ring buffer (I think), in which rx_buffer_head is the index of the +// location to which to write the next incoming character and rx_buffer_tail +// is the index of the location from which to read. +#if (RAMEND < 1000) + #define RX_BUFFER_SIZE 32 +#else + #define RX_BUFFER_SIZE 128 +#endif + +struct ring_buffer +{ + unsigned char buffer[RX_BUFFER_SIZE]; + int head; + int tail; +}; + +#if defined(UBRRH) || defined(UBRR0H) + ring_buffer rx_buffer = { { 0 }, 0, 0 }; +#endif +#if defined(UBRR1H) + ring_buffer rx_buffer1 = { { 0 }, 0, 0 }; +#endif +#if defined(UBRR2H) + ring_buffer rx_buffer2 = { { 0 }, 0, 0 }; +#endif +#if defined(UBRR3H) + ring_buffer rx_buffer3 = { { 0 }, 0, 0 }; +#endif + +inline void store_char(unsigned char c, ring_buffer *rx_buffer) +{ + int i = (unsigned int)(rx_buffer->head + 1) % RX_BUFFER_SIZE; + + // if we should be storing the received character into the location + // just before the tail (meaning that the head would advance to the + // current location of the tail), we're about to overflow the buffer + // and so we don't write the character or advance the head. + if (i != rx_buffer->tail) { + rx_buffer->buffer[rx_buffer->head] = c; + rx_buffer->head = i; + } +} + +#if defined(USART_RX_vect) + SIGNAL(USART_RX_vect) + { + #if defined(UDR0) + unsigned char c = UDR0; + #elif defined(UDR) + unsigned char c = UDR; // atmega8535 + #else + #error UDR not defined + #endif + store_char(c, &rx_buffer); + } +#elif defined(SIG_USART0_RECV) && defined(UDR0) + SIGNAL(SIG_USART0_RECV) + { + unsigned char c = UDR0; + store_char(c, &rx_buffer); + } +#elif defined(SIG_UART0_RECV) && defined(UDR0) + SIGNAL(SIG_UART0_RECV) + { + unsigned char c = UDR0; + store_char(c, &rx_buffer); + } +//#elif defined(SIG_USART_RECV) +#elif defined(USART0_RX_vect) + // fixed by Mark Sproul this is on the 644/644p + //SIGNAL(SIG_USART_RECV) + SIGNAL(USART0_RX_vect) + { + #if defined(UDR0) + unsigned char c = UDR0; + #elif defined(UDR) + unsigned char c = UDR; // atmega8, atmega32 + #else + #error UDR not defined + #endif + store_char(c, &rx_buffer); + } +#elif defined(SIG_UART_RECV) + // this is for atmega8 + SIGNAL(SIG_UART_RECV) + { + #if defined(UDR0) + unsigned char c = UDR0; // atmega645 + #elif defined(UDR) + unsigned char c = UDR; // atmega8 + #endif + store_char(c, &rx_buffer); + } +#elif defined(USBCON) + #warning No interrupt handler for usart 0 + #warning Serial(0) is on USB interface +#else + #error No interrupt handler for usart 0 +#endif + +//#if defined(SIG_USART1_RECV) +#if defined(USART1_RX_vect) + //SIGNAL(SIG_USART1_RECV) + SIGNAL(USART1_RX_vect) + { + unsigned char c = UDR1; + store_char(c, &rx_buffer1); + } +#elif defined(SIG_USART1_RECV) + #error SIG_USART1_RECV +#endif + +#if defined(USART2_RX_vect) && defined(UDR2) + SIGNAL(USART2_RX_vect) + { + unsigned char c = UDR2; + store_char(c, &rx_buffer2); + } +#elif defined(SIG_USART2_RECV) + #error SIG_USART2_RECV +#endif + +#if defined(USART3_RX_vect) && defined(UDR3) + SIGNAL(USART3_RX_vect) + { + unsigned char c = UDR3; + store_char(c, &rx_buffer3); + } +#elif defined(SIG_USART3_RECV) + #error SIG_USART3_RECV +#endif + + + +// Constructors //////////////////////////////////////////////////////////////// + +HardwareSerial::HardwareSerial(ring_buffer *rx_buffer, + volatile uint8_t *ubrrh, volatile uint8_t *ubrrl, + volatile uint8_t *ucsra, volatile uint8_t *ucsrb, + volatile uint8_t *udr, + uint8_t rxen, uint8_t txen, uint8_t rxcie, uint8_t udre, uint8_t u2x) +{ + _rx_buffer = rx_buffer; + _ubrrh = ubrrh; + _ubrrl = ubrrl; + _ucsra = ucsra; + _ucsrb = ucsrb; + _udr = udr; + _rxen = rxen; + _txen = txen; + _rxcie = rxcie; + _udre = udre; + _u2x = u2x; +} + +// Public Methods ////////////////////////////////////////////////////////////// + +void HardwareSerial::begin(long baud) +{ + uint16_t baud_setting; + bool use_u2x = true; + +#if F_CPU == 16000000UL + // hardcoded exception for compatibility with the bootloader shipped + // with the Duemilanove and previous boards and the firmware on the 8U2 + // on the Uno and Mega 2560. + if (baud == 57600) { + use_u2x = false; + } +#endif + + if (use_u2x) { + *_ucsra = 1 << _u2x; + baud_setting = (F_CPU / 4 / baud - 1) / 2; + } else { + *_ucsra = 0; + baud_setting = (F_CPU / 8 / baud - 1) / 2; + } + + // assign the baud_setting, a.k.a. ubbr (USART Baud Rate Register) + *_ubrrh = baud_setting >> 8; + *_ubrrl = baud_setting; + + sbi(*_ucsrb, _rxen); + sbi(*_ucsrb, _txen); + sbi(*_ucsrb, _rxcie); +} + +void HardwareSerial::end() +{ + cbi(*_ucsrb, _rxen); + cbi(*_ucsrb, _txen); + cbi(*_ucsrb, _rxcie); +} + +int HardwareSerial::available(void) +{ + return (unsigned int)(RX_BUFFER_SIZE + _rx_buffer->head - _rx_buffer->tail) % RX_BUFFER_SIZE; +} + +int HardwareSerial::peek(void) +{ + if (_rx_buffer->head == _rx_buffer->tail) { + return -1; + } else { + return _rx_buffer->buffer[_rx_buffer->tail]; + } +} + +int HardwareSerial::read(void) +{ + // if the head isn't ahead of the tail, we don't have any characters + if (_rx_buffer->head == _rx_buffer->tail) { + return -1; + } else { + unsigned char c = _rx_buffer->buffer[_rx_buffer->tail]; + _rx_buffer->tail = (unsigned int)(_rx_buffer->tail + 1) % RX_BUFFER_SIZE; + return c; + } +} + +void HardwareSerial::flush() +{ + // don't reverse this or there may be problems if the RX interrupt + // occurs after reading the value of rx_buffer_head but before writing + // the value to rx_buffer_tail; the previous value of rx_buffer_head + // may be written to rx_buffer_tail, making it appear as if the buffer + // don't reverse this or there may be problems if the RX interrupt + // occurs after reading the value of rx_buffer_head but before writing + // the value to rx_buffer_tail; the previous value of rx_buffer_head + // may be written to rx_buffer_tail, making it appear as if the buffer + // were full, not empty. + _rx_buffer->head = _rx_buffer->tail; +} + +size_t HardwareSerial::write(uint8_t c) +{ + while (!((*_ucsra) & (1 << _udre))) + ; + + *_udr = c; + + return( 1 ); +} + +// Preinstantiate Objects ////////////////////////////////////////////////////// + +#if ! DEFAULT_TO_TINY_DEBUG_SERIAL + #if defined(UBRRH) && defined(UBRRL) + HardwareSerial Serial(&rx_buffer, &UBRRH, &UBRRL, &UCSRA, &UCSRB, &UDR, RXEN, TXEN, RXCIE, UDRE, U2X); + #elif defined(UBRR0H) && defined(UBRR0L) + HardwareSerial Serial(&rx_buffer, &UBRR0H, &UBRR0L, &UCSR0A, &UCSR0B, &UDR0, RXEN0, TXEN0, RXCIE0, UDRE0, U2X0); + #elif defined(USBCON) + #warning no serial port defined (port 0) + #else + #error no serial port defined (port 0) + #endif +#endif + +#if defined(UBRR1H) + HardwareSerial Serial1(&rx_buffer1, &UBRR1H, &UBRR1L, &UCSR1A, &UCSR1B, &UDR1, RXEN1, TXEN1, RXCIE1, UDRE1, U2X1); +#endif +#if defined(UBRR2H) + HardwareSerial Serial2(&rx_buffer2, &UBRR2H, &UBRR2L, &UCSR2A, &UCSR2B, &UDR2, RXEN2, TXEN2, RXCIE2, UDRE2, U2X2); +#endif +#if defined(UBRR3H) + HardwareSerial Serial3(&rx_buffer3, &UBRR3H, &UBRR3L, &UCSR3A, &UCSR3B, &UDR3, RXEN3, TXEN3, RXCIE3, UDRE3, U2X3); +#endif + +#endif // whole file diff --git a/hardware/digistump/avr/cores/tiny/HardwareSerial.h b/hardware/digistump/avr/cores/tiny/HardwareSerial.h new file mode 100644 index 0000000..5d85683 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/HardwareSerial.h @@ -0,0 +1,77 @@ +/* + HardwareSerial.h - Hardware serial library for Wiring + Copyright (c) 2006 Nicholas Zambetti. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 28 September 2010 by Mark Sproul +*/ + +#ifndef HardwareSerial_h +#define HardwareSerial_h + +#include + +#include "core_build_options.h" +#include "Stream.h" + +struct ring_buffer; + +class HardwareSerial : public Stream +{ + private: + ring_buffer *_rx_buffer; + volatile uint8_t *_ubrrh; + volatile uint8_t *_ubrrl; + volatile uint8_t *_ucsra; + volatile uint8_t *_ucsrb; + volatile uint8_t *_udr; + uint8_t _rxen; + uint8_t _txen; + uint8_t _rxcie; + uint8_t _udre; + uint8_t _u2x; + public: + HardwareSerial(ring_buffer *rx_buffer, + volatile uint8_t *ubrrh, volatile uint8_t *ubrrl, + volatile uint8_t *ucsra, volatile uint8_t *ucsrb, + volatile uint8_t *udr, + uint8_t rxen, uint8_t txen, uint8_t rxcie, uint8_t udre, uint8_t u2x); + void begin(long); + void end(); + virtual int available(void); + virtual int peek(void); + virtual int read(void); + virtual void flush(void); + virtual size_t write(uint8_t); + using Print::write; // pull in write(str) and write(buf, size) from Print +}; + +#if (defined(UBRRH) || defined(UBRR0H)) && ! DEFAULT_TO_TINY_DEBUG_SERIAL + extern HardwareSerial Serial; +#elif defined(USBCON) + #include "usb_api.h" +#endif +#if defined(UBRR1H) + extern HardwareSerial Serial1; +#endif +#if defined(UBRR2H) + extern HardwareSerial Serial2; +#endif +#if defined(UBRR3H) + extern HardwareSerial Serial3; +#endif + +#endif diff --git a/hardware/digistump/avr/cores/tiny/Print.cpp b/hardware/digistump/avr/cores/tiny/Print.cpp new file mode 100644 index 0000000..7d303b7 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/Print.cpp @@ -0,0 +1,247 @@ +/* + Print.cpp - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 23 November 2006 by David A. Mellis + */ + +#include +#include +#include +#include + +#include "wiring.h" +#include "Print.h" + +// Public Methods ////////////////////////////////////////////////////////////// + +/* default implementation: may be overridden */ +void Print::write(const char *str) +{ + while (*str) + write(*str++); +} + +/* default implementation: may be overridden */ +void Print::write(const uint8_t *buffer, size_t size) +{ + while (size--) + write(*buffer++); +} + +void Print::print(const String &s) +{ + for (int i = 0; i < s.length(); i++) { + write(s[i]); + } +} + +void Print::print(const char str[]) +{ + write(str); +} + +void Print::print(char c, int base) +{ + print((long) c, base); +} + +void Print::print(unsigned char b, int base) +{ + print((unsigned long) b, base); +} + +void Print::print(int n, int base) +{ + print((long) n, base); +} + +void Print::print(unsigned int n, int base) +{ + print((unsigned long) n, base); +} + +void Print::print(long n, int base) +{ + if (base == 0) { + write(n); + } else if (base == 10) { + if (n < 0) { + print('-'); + n = -n; + } + printNumber(n, 10); + } else { + printNumber(n, base); + } +} + +void Print::print(unsigned long n, int base) +{ + if (base == 0) write(n); + else printNumber(n, base); +} + +void Print::print(double n, int digits) +{ + printFloat(n, digits); +} + +int Print::print( fstr_t* s ) +{ + int rv; + char ch; + + rv = 0; + ch = pgm_read_byte( s ); + while ( ch != 0 ) + { + write( ch ); + ++s; + ++rv; + ch = pgm_read_byte( s ); + } + return( rv ); +} + +int Print::println(void) +{ + print('\r'); + print('\n'); + return( 2 ); +} + +void Print::println(const String &s) +{ + print(s); + println(); +} + +void Print::println(const char c[]) +{ + print(c); + println(); +} + +void Print::println(char c, int base) +{ + print(c, base); + println(); +} + +void Print::println(unsigned char b, int base) +{ + print(b, base); + println(); +} + +void Print::println(int n, int base) +{ + print(n, base); + println(); +} + +void Print::println(unsigned int n, int base) +{ + print(n, base); + println(); +} + +void Print::println(long n, int base) +{ + print(n, base); + println(); +} + +void Print::println(unsigned long n, int base) +{ + print(n, base); + println(); +} + +void Print::println(double n, int digits) +{ + print(n, digits); + println(); +} + +int Print::println( fstr_t* s ) +{ + int rv; + + rv = print( s ); + rv += println(); + return( rv ); +} + +// Private Methods ///////////////////////////////////////////////////////////// + +void Print::printNumber(unsigned long n, uint8_t base) +{ + unsigned char buf[8 * sizeof(long)]; // Assumes 8-bit chars. + unsigned long i = 0; + + if (n == 0) { + print('0'); + return; + } + + while (n > 0) { + buf[i++] = n % base; + n /= base; + } + + for (; i > 0; i--) + print((char) (buf[i - 1] < 10 ? + '0' + buf[i - 1] : + 'A' + buf[i - 1] - 10)); +} + +void Print::printFloat(double number, uint8_t digits) +{ + // Handle negative numbers + if (number < 0.0) + { + print('-'); + number = -number; + } + + // Round correctly so that print(1.999, 2) prints as "2.00" + double rounding = 0.5; + for (uint8_t i=0; i 0) + print("."); + + // Extract digits from the remainder one at a time + while (digits-- > 0) + { + remainder *= 10.0; + int toPrint = int(remainder); + print(toPrint); + remainder -= toPrint; + } +} diff --git a/hardware/digistump/avr/cores/tiny/Print.h b/hardware/digistump/avr/cores/tiny/Print.h new file mode 100644 index 0000000..0e964b0 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/Print.h @@ -0,0 +1,108 @@ +/* + Print.h - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 20-11-2010 by B.Cook ... + + http://arduiniana.org/libraries/flash/ + Printable support thanks to Mikal Hart +*/ + +#ifndef Print_h +#define Print_h + +#include +#include // for size_t +#include + +#include "WString.h" + +#define DEC 10 +#define HEX 16 +#define OCT 8 +#define BIN 2 +#define BYTE 0 + +#define ARDUINO_CORE_PRINTABLE_SUPPORT + +class Print; + +/* Printable...*/ + +class _Printable +{ +public: + virtual void print(Print &stream) const = 0; +}; + +/* ...Printable */ + +typedef struct +{ + char c; +} +fstr_t; + +/* rmv: Use the macro below in preparation for the next Arduino release. +# define FSTR(s) ((fstr_t*)PSTR(s)) +*/ +# define F(s) ((fstr_t*)PSTR(s)) + +class Print +{ + private: + void printNumber(unsigned long, uint8_t); + void printFloat(double, uint8_t); + protected: + void setWriteError(int err = 1) { /*write_error = err;*/ } + public: + virtual size_t write(uint8_t) = 0; + virtual void write(const char *str); + virtual void write(const uint8_t *buffer, size_t size); + + void print(const String &); + void print(const char[]); + void print(char, int = BYTE); + void print(unsigned char, int = BYTE); + void print(int, int = DEC); + void print(unsigned int, int = DEC); + void print(long, int = DEC); + void print(unsigned long, int = DEC); + void print(double, int = 2); + int print( fstr_t* ); + + void println(const String &s); + void println(const char[]); + void println(char, int = BYTE); + void println(unsigned char, int = BYTE); + void println(int, int = DEC); + void println(unsigned int, int = DEC); + void println(long, int = DEC); + void println(unsigned long, int = DEC); + void println(double, int = 2); + int println( fstr_t* ); + int println(void); + public: + /* Printable...*/ + void println(const _Printable &obj) + { obj.print(*this); println(); } + void print(const _Printable &obj) + { obj.print(*this); }; + /* ...Printable */ +}; + +#endif diff --git a/hardware/digistump/avr/cores/tiny/PwmTimer.h b/hardware/digistump/avr/cores/tiny/PwmTimer.h new file mode 100644 index 0000000..b95796a --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/PwmTimer.h @@ -0,0 +1,65 @@ +/*============================================================================== + + PwmTimer.h - Veneer for the PWM timers. + + Copyright 2010 Rowdy Dog Software. + + This file is part of Arduino-Tiny. + + Arduino-Tiny is free software: you can redistribute it and/or modify it + under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation, either version 3 of the License, or (at your + option) any later version. + + Arduino-Tiny is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with Arduino-Tiny. If not, see . + +==============================================================================*/ + +#ifndef PwmTimer_h +#define PwmTimer_h + +#include "core_pins.h" +#include "core_timers.h" + +#define PwmTimer3_(t,f,c) TIMER_PASTE_CHANNEL_A( Timer, t, f, c ) +#define PwmTimer2_(t,f) TIMER_PASTE_A( Timer, t, f ) + +#if CORE_PWM_COUNT >= 1 +#define Pwm0_SetCompareOutputMode PwmTimer3_( CORE_PWM0_TIMER, SetCompareOutputMode, CORE_PWM0_CHANNEL ) +#define Pwm0_Disconnected PwmTimer2_( CORE_PWM0_TIMER, Disconnected ) +#define Pwm0_Clear PwmTimer2_( CORE_PWM0_TIMER, Clear ) +#define Pwm0_SetOutputCompareMatch PwmTimer3_( CORE_PWM0_TIMER, SetOutputCompareMatch, CORE_PWM0_CHANNEL ) +#endif + +#if CORE_PWM_COUNT >= 2 +#define Pwm1_SetCompareOutputMode PwmTimer3_( CORE_PWM1_TIMER, SetCompareOutputMode, CORE_PWM1_CHANNEL ) +#define Pwm1_Disconnected PwmTimer2_( CORE_PWM1_TIMER, Disconnected ) +#define Pwm1_Clear PwmTimer2_( CORE_PWM1_TIMER, Clear ) +#define Pwm1_SetOutputCompareMatch PwmTimer3_( CORE_PWM1_TIMER, SetOutputCompareMatch, CORE_PWM1_CHANNEL ) +#endif + +#if CORE_PWM_COUNT >= 3 +#define Pwm2_SetCompareOutputMode PwmTimer3_( CORE_PWM2_TIMER, SetCompareOutputMode, CORE_PWM2_CHANNEL ) +#define Pwm2_Disconnected PwmTimer2_( CORE_PWM2_TIMER, Disconnected ) +#define Pwm2_Clear PwmTimer2_( CORE_PWM2_TIMER, Clear ) +#define Pwm2_SetOutputCompareMatch PwmTimer3_( CORE_PWM2_TIMER, SetOutputCompareMatch, CORE_PWM2_CHANNEL ) +#endif + +#if CORE_PWM_COUNT >= 4 +#define Pwm3_SetCompareOutputMode PwmTimer3_( CORE_PWM3_TIMER, SetCompareOutputMode, CORE_PWM3_CHANNEL ) +#define Pwm3_Disconnected PwmTimer2_( CORE_PWM3_TIMER, Disconnected ) +#define Pwm3_Clear PwmTimer2_( CORE_PWM3_TIMER, Clear ) +#define Pwm3_SetOutputCompareMatch PwmTimer3_( CORE_PWM3_TIMER, SetOutputCompareMatch, CORE_PWM3_CHANNEL ) +#endif + +#if CORE_PWM_COUNT >= 5 +#error Only 4 pins PWM are supported. Add more macro defintions. +#endif + +#endif diff --git a/hardware/digistump/avr/cores/tiny/Stream.h b/hardware/digistump/avr/cores/tiny/Stream.h new file mode 100644 index 0000000..93d8275 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/Stream.h @@ -0,0 +1,35 @@ +/* + Stream.h - base class for character-based streams. + Copyright (c) 2010 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef Stream_h +#define Stream_h + +#include +#include "Print.h" + +class Stream : public Print +{ + public: + virtual int available() = 0; + virtual int read() = 0; + virtual int peek() = 0; + virtual void flush() = 0; +}; + +#endif diff --git a/hardware/digistump/avr/cores/tiny/TinyDebugSerial.cpp b/hardware/digistump/avr/cores/tiny/TinyDebugSerial.cpp new file mode 100644 index 0000000..dd0b7e9 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/TinyDebugSerial.cpp @@ -0,0 +1,42 @@ +/*============================================================================== + + TinyDebugSerial.cpp - Tiny write-only software serial. + + Copyright 2010 Rowdy Dog Software. + + This file is part of Arduino-Tiny. + + Arduino-Tiny is free software: you can redistribute it and/or modify it + under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation, either version 3 of the License, or (at your + option) any later version. + + Arduino-Tiny is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with Arduino-Tiny. If not, see . + +==============================================================================*/ + +#include "core_build_options.h" +#include "TinyDebugSerial.h" + +static TinyDebugSerialWriter stub; + +void TinyDebugSerial::useStub( void ) +{ + _writer = &stub; + _writer->init(); +} + +TinyDebugSerial::TinyDebugSerial( void ) +{ + useStub(); +} + +#if defined( DEFAULT_TO_TINY_DEBUG_SERIAL ) && DEFAULT_TO_TINY_DEBUG_SERIAL +TinyDebugSerial Serial; +#endif diff --git a/hardware/digistump/avr/cores/tiny/TinyDebugSerial.h b/hardware/digistump/avr/cores/tiny/TinyDebugSerial.h new file mode 100644 index 0000000..4c1b79b --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/TinyDebugSerial.h @@ -0,0 +1,749 @@ +/*============================================================================== + + TinyDebugSerial.h - Tiny write-only software serial. + + Copyright 2010 Rowdy Dog Software. + + This file is part of Arduino-Tiny. + + Arduino-Tiny is free software: you can redistribute it and/or modify it + under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation, either version 3 of the License, or (at your + option) any later version. + + Arduino-Tiny is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with Arduino-Tiny. If not, see . + +==============================================================================*/ + +#ifndef TinyDebugSerial_h +#define TinyDebugSerial_h + +#include + +#include "binary.h" +#include "core_build_options.h" +#include "Stream.h" + + +class TinyDebugSerialWriter; +class TinyDebugSerial; + + +class TinyDebugSerialWriter +{ + protected: + + virtual void init( void ) + { + } + + virtual void write( uint8_t ) + { + } + + friend class TinyDebugSerial; +}; + +void TinyDebugSerialWriterInternalBug( void ) __attribute__((error("Serial (TinyDebugSerial) has an internal problem. Contact the developer."))); + +__attribute__((always_inline, unused)) static inline void TinyDebugSerialWriterBangOneByte( uint8_t value, uint8_t SER_REG, uint8_t SER_BIT, uint8_t lom, uint8_t him, uint8_t oloops, uint8_t iloops, uint8_t nops ) +{ + if ( __builtin_constant_p( SER_REG ) + && __builtin_constant_p( SER_BIT ) + && __builtin_constant_p( lom ) + && __builtin_constant_p( him ) + && __builtin_constant_p( oloops ) + && __builtin_constant_p( iloops ) + && __builtin_constant_p( nops ) ) + { + uint8_t i; + uint8_t j; + uint8_t ol; + uint8_t il; + uint8_t b; // Initialized to the low bits + uint8_t hib; + uint8_t m; + + b = ((value << 1) & 0x1F); + hib = ((value >> 4) & 0x1F) | 0x10; + + asm volatile + ( + "ldi %[j], 2" "\n\t" + "ldi %[i], 5" "\n\t" + "ldi %[m], %[lom]" "\n\t" + + // Note: 8 MHz, 9600 baud ---> disabling interrupts does not appear to be necessary + + "cli" "\n\t" + + "rjmp L%=ntop" "\n\t" + + "L%=btop: " + "nop" "\n\t" // ---> 7 + "nop" "\n\t" // + "nop" "\n\t" // + "nop" "\n\t" // + "nop" "\n\t" // + "nop" "\n\t" // + "nop" "\n\t" // + + "L%=ntop: " + "ror %[b]" "\n\t" // ---> 1 + + "brcs L%=bxh" "\n\t" // 1 (not taken) + "cbi %[serreg], %[serbit]" "\n\t" // 2 + "rjmp L%=bxz" "\n\t" // 2 + + "L%=bxh: " // 2 (taken) + "sbi %[serreg], %[serbit]" "\n\t" // 2 + "nop" "\n\t" // 1 + + // ---> 5 + "L%=bxz: " + + "ror %[m]" "\n\t" // ---> 3 or 4 + "brcc L%=bnoe" "\n\t" // + "nop" "\n\t" // + "nop" "\n\t" // + "L%=bnoe: " + + // ---> 1 + ".if %[oloops] >= 1" "\n\t" // if oloops >= 1 then... + "ldi %[ol], %[oloops]" "\n\t" // 4*oloops + oloops*(3*iloops) or oloops*((3*iloops)+4) + "L%=odelay: " "\n\t" + ".endif" "\n\t" + "ldi %[il], %[iloops]" "\n\t" // if oloops == 0 then... + "L%=idelay: " "\n\t" // (3*iloops) + "dec %[il]" "\n\t" + "brne L%=idelay" "\n\t" + "nop" "\n\t" + ".if %[oloops] >= 1" "\n\t" + "dec %[ol]" "\n\t" + "brne L%=odelay" "\n\t" + "nop" "\n\t" + ".endif" "\n\t" + + ".if %[nops] >= 1" "\n\t" + "nop" "\n\t" // + ".endif" "\n\t" + ".if %[nops] >= 2" "\n\t" + "nop" "\n\t" // + ".endif" "\n\t" + + "dec %[i]" "\n\t" // ---> 3 + "brne L%=btop" "\n\t" // + "nop" "\n\t" // + + "dec %[j]" "\n\t" // ---> 7 + "breq L%=bfin" "\n\t" // + "ldi %[i], 5" "\n\t" // + "mov %[b], %[hib]" "\n\t" // + "ldi %[m], %[him]" "\n\t" // + "rjmp L%=ntop" "\n\t" // + + "L%=bfin: " + + "sei" "\n\t" + : + [i] "=&r" ( i ), + [j] "=&r" ( j ), + [ol] "=&r" ( ol ), + [il] "=&r" ( il ), + [m] "=&r" ( m ) + : + [b] "r" ( b ), + [hib] "r" ( hib ), + [serreg] "I" ( SER_REG ), + [serbit] "M" ( SER_BIT ), + [lom] "M" ( lom ), + [him] "M" ( him ), + [oloops] "M" ( oloops ), + [iloops] "M" ( iloops ), + [nops] "M" ( nops ) + : + "r31", + "r30" + ); + } + else + { + TinyDebugSerialWriterInternalBug(); + } +} + + +template + < + uint8_t SER_REG, + uint8_t SER_BIT + > +class TinyDebugSerialWriter_1_9600 : public TinyDebugSerialWriter +{ + protected: + + virtual void init( void ) + { + asm volatile + ( + "sbi %[serreg]-1, %[serbit]" "\n\t" + "sbi %[serreg], %[serbit]" "\n\t" + : + : + [serreg] "I" ( SER_REG ), + [serbit] "I" ( SER_BIT ) + : + ); + } + + virtual void write( uint8_t value ) + { + TinyDebugSerialWriterBangOneByte( value, SER_REG, SER_BIT, B00100, B00010, 0, 28, 2 ); + } +}; + + +template + < + uint8_t SER_REG, + uint8_t SER_BIT + > +class TinyDebugSerialWriter_1_38400 : public TinyDebugSerialWriter +{ + protected: + + virtual void init( void ) + { + asm volatile + ( + "sbi %[serreg]-1, %[serbit]" "\n\t" + "sbi %[serreg], %[serbit]" "\n\t" + : + : + [serreg] "I" ( SER_REG ), + [serbit] "I" ( SER_BIT ) + : + ); + } + + virtual void write( uint8_t value ) + { + TinyDebugSerialWriterBangOneByte( value, SER_REG, SER_BIT, B00000, B00000, 0, 2, 0 ); + } +}; + + +template + < + uint8_t SER_REG, + uint8_t SER_BIT + > +class TinyDebugSerialWriter_1_115200 : public TinyDebugSerialWriter +{ + protected: + + virtual void init( void ) + { + asm volatile + ( + "sbi %[serreg]-1, %[serbit]" "\n\t" + "sbi %[serreg], %[serbit]" "\n\t" + : + : + [serreg] "I" ( SER_REG ), + [serbit] "I" ( SER_BIT ) + : + ); + } + + virtual void write( uint8_t value ) + { + asm volatile + ( + "cli" "\n\t" + + "cbi %[serreg], %[serbit]" "\n\t" /* 2 <--- 0 */ + "ror %[value]" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + + "brcs L%=b0h" "\n\t" /* 1 (not taken) */ + "nop" "\n\t" /* 1 */ + "cbi %[serreg], %[serbit]" "\n\t" /* 2 <--- st is 9 cycles */ + "rjmp L%=b0z" "\n\t" /* 2 */ + "L%=b0h: " /* 2 (taken) */ + "sbi %[serreg], %[serbit]" "\n\t" /* 2 <--- st is 9 cycles */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "L%=b0z: " + "ror %[value]" "\n\t" /* 1 */ + + "nop" "\n\t" /* 1 */ + + "brcs L%=b1h" "\n\t" /* 1 (not taken) */ + "nop" "\n\t" /* 1 */ + "cbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b0 is 8 cycles */ + "rjmp L%=b1z" "\n\t" /* 2 */ + "L%=b1h: " /* 2 (taken) */ + "sbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b0 is 8 cycles */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "L%=b1z: " + "ror %[value]" "\n\t" /* 1 */ + + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + + "brcs L%=b2h" "\n\t" /* 1 (not taken) */ + "nop" "\n\t" /* 1 */ + "cbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b1 is 9 cycles */ + "rjmp L%=b2z" "\n\t" /* 2 */ + "L%=b2h: " /* 2 (taken) */ + "sbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b1 is 9 cycles */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "L%=b2z: " + "ror %[value]" "\n\t" /* 1 */ + + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + + "brcs L%=b3h" "\n\t" /* 1 (not taken) */ + "nop" "\n\t" /* 1 */ + "cbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b2 is 9 cycles */ + "rjmp L%=b3z" "\n\t" /* 2 */ + "L%=b3h: " /* 2 (taken) */ + "sbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b2 is 9 cycles */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "L%=b3z: " + "ror %[value]" "\n\t" /* 1 */ + + "nop" "\n\t" /* 1 */ + + "brcs L%=b4h" "\n\t" /* 1 (not taken) */ + "nop" "\n\t" /* 1 */ + "cbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b3 is 8 cycles */ + "rjmp L%=b4z" "\n\t" /* 2 */ + "L%=b4h: " /* 2 (taken) */ + "sbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b3 is 8 cycles */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "L%=b4z: " + "ror %[value]" "\n\t" /* 1 */ + + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + + "brcs L%=b5h" "\n\t" /* 1 (not taken) */ + "nop" "\n\t" /* 1 */ + "cbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b4 is 9 cycles */ + "rjmp L%=b5z" "\n\t" /* 2 */ + "L%=b5h: " /* 2 (taken) */ + "sbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b4 is 9 cycles */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "L%=b5z: " + "ror %[value]" "\n\t" /* 1 */ + + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + + "brcs L%=b6h" "\n\t" /* 1 (not taken) */ + "nop" "\n\t" /* 1 */ + "cbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b5 is 9 cycles */ + "rjmp L%=b6z" "\n\t" /* 2 */ + "L%=b6h: " /* 2 (taken) */ + "sbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b5 is 9 cycles */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "L%=b6z: " + "ror %[value]" "\n\t" /* 1 */ + + "nop" "\n\t" /* 1 */ + + "brcs L%=b7h" "\n\t" /* 1 (not taken) */ + "nop" "\n\t" /* 1 */ + "cbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b6 is 8 cycles */ + "rjmp L%=b7z" "\n\t" /* 2 */ + "L%=b7h: " /* 2 (taken) */ + "sbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b6 is 8 cycles */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "L%=b7z: " + "nop" "\n\t" /* 1 */ + + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "sbi %[serreg], %[serbit]" "\n\t" /* 2 <--- b7 is 9 cycles */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + "nop" "\n\t" /* 1 */ + /* <---sp is 9 cycles */ + + "sei" "\n\t" + + : + : + [value] "r" ( value ), + [serreg] "I" ( SER_REG ), + [serbit] "I" ( SER_BIT ) + ); + } +}; + + +template + < + uint8_t SER_REG, + uint8_t SER_BIT + > +class TinyDebugSerialWriter_8_9600 : public TinyDebugSerialWriter +{ + protected: + + virtual void init( void ) + { + asm volatile + ( + "sbi %[serreg]-1, %[serbit]" "\n\t" + "sbi %[serreg], %[serbit]" "\n\t" + : + : + [serreg] "I" ( SER_REG ), + [serbit] "I" ( SER_BIT ) + : + ); + } + + virtual void write( uint8_t value ) + { + TinyDebugSerialWriterBangOneByte( value, SER_REG, SER_BIT, B01001, B00100, 3, 89, 0 ); + } +}; + + +template + < + uint8_t SER_REG, + uint8_t SER_BIT + > +class TinyDebugSerialWriter_8_38400 : public TinyDebugSerialWriter +{ + protected: + + virtual void init( void ) + { + asm volatile + ( + "sbi %[serreg]-1, %[serbit]" "\n\t" + "sbi %[serreg], %[serbit]" "\n\t" + : + : + [serreg] "I" ( SER_REG ), + [serbit] "I" ( SER_BIT ) + : + ); + } + + virtual void write( uint8_t value ) + { + TinyDebugSerialWriterBangOneByte( value, SER_REG, SER_BIT, B01001, B00100, 0, 62, 2 ); + } +}; + + +template + < + uint8_t SER_REG, + uint8_t SER_BIT + > +class TinyDebugSerialWriter_8_115200 : public TinyDebugSerialWriter +{ + protected: + + virtual void init( void ) + { + asm volatile + ( + "sbi %[serreg]-1, %[serbit]" "\n\t" + "sbi %[serreg], %[serbit]" "\n\t" + : + : + [serreg] "I" ( SER_REG ), + [serbit] "I" ( SER_BIT ) + : + ); + } + + virtual void write( uint8_t value ) + { + TinyDebugSerialWriterBangOneByte( value, SER_REG, SER_BIT, B01010, B10100, 0, 16, 1 ); + } +}; + + +template + < + uint8_t SER_REG, + uint8_t SER_BIT + > +class TinyDebugSerialWriter_16_9600 : public TinyDebugSerialWriter +{ + protected: + + virtual void init( void ) + { + asm volatile + ( + "sbi %[serreg]-1, %[serbit]" "\n\t" + "sbi %[serreg], %[serbit]" "\n\t" + : + : + [serreg] "I" ( SER_REG ), + [serbit] "I" ( SER_BIT ) + : + ); + } + + virtual void write( uint8_t value ) + { + TinyDebugSerialWriterBangOneByte( value, SER_REG, SER_BIT, B10110, B11011, 6, 90, 2 ); + } +}; + + +template + < + uint8_t SER_REG, + uint8_t SER_BIT + > +class TinyDebugSerialWriter_16_38400 : public TinyDebugSerialWriter +{ + protected: + + virtual void init( void ) + { + asm volatile + ( + "sbi %[serreg]-1, %[serbit]" "\n\t" + "sbi %[serreg], %[serbit]" "\n\t" + : + : + [serreg] "I" ( SER_REG ), + [serbit] "I" ( SER_BIT ) + : + ); + } + + virtual void write( uint8_t value ) + { + TinyDebugSerialWriterBangOneByte( value, SER_REG, SER_BIT, B10110, B11011, 5, 25, 1 ); + } +}; + + +template + < + uint8_t SER_REG, + uint8_t SER_BIT + > +class TinyDebugSerialWriter_16_115200 : public TinyDebugSerialWriter +{ + protected: + + virtual void init( void ) + { + asm volatile + ( + "sbi %[serreg]-1, %[serbit]" "\n\t" + "sbi %[serreg], %[serbit]" "\n\t" + : + : + [serreg] "I" ( SER_REG ), + [serbit] "I" ( SER_BIT ) + : + ); + } + + virtual void write( uint8_t value ) + { + TinyDebugSerialWriterBangOneByte( value, SER_REG, SER_BIT, B11110, B11111, 0, 39, 1 ); + } +}; + + +#if defined( __AVR_ATtinyX313__ ) + + #define TINY_DEBUG_SERIAL_REGISTER 0x1B + #define TINY_DEBUG_SERIAL_BIT 1 + +#elif defined( __AVR_ATtinyX4__ ) + + #if F_CPU <= 8000000L + // port B bit 0 (PB0) + #define TINY_DEBUG_SERIAL_REGISTER 0x18 + #define TINY_DEBUG_SERIAL_BIT 0 + #else + // port A bit 0 (PA0) + #define TINY_DEBUG_SERIAL_REGISTER 0x1B + #define TINY_DEBUG_SERIAL_BIT 0 + #endif + +#elif defined( __AVR_ATtinyX5__ ) + + #if F_CPU <= 8000000L + // port B bit 3 (PB3) + #define TINY_DEBUG_SERIAL_REGISTER 0x18 + #define TINY_DEBUG_SERIAL_BIT 3 + #else + // port B bit 2 (PB2) + #define TINY_DEBUG_SERIAL_REGISTER 0x18 + #define TINY_DEBUG_SERIAL_BIT 2 + #endif + +#endif + + +#if F_CPU == 1000000L + typedef TinyDebugSerialWriter_1_9600 TinyDebugSerialWriter_9600; + typedef TinyDebugSerialWriter_1_38400 TinyDebugSerialWriter_38400; + typedef TinyDebugSerialWriter_1_115200 TinyDebugSerialWriter_115200; + #define TINY_DEBUG_SERIAL_SUPPORTED 1 +#elif F_CPU == 8000000L + typedef TinyDebugSerialWriter_8_9600 TinyDebugSerialWriter_9600; + typedef TinyDebugSerialWriter_8_38400 TinyDebugSerialWriter_38400; + typedef TinyDebugSerialWriter_8_115200 TinyDebugSerialWriter_115200; + #define TINY_DEBUG_SERIAL_SUPPORTED 1 +#elif F_CPU == 16000000L + typedef TinyDebugSerialWriter_16_9600 TinyDebugSerialWriter_9600; + typedef TinyDebugSerialWriter_16_38400 TinyDebugSerialWriter_38400; + typedef TinyDebugSerialWriter_16_115200 TinyDebugSerialWriter_115200; + #define TINY_DEBUG_SERIAL_SUPPORTED 1 +#elif F_CPU == 16500000L + typedef TinyDebugSerialWriter_16_9600 TinyDebugSerialWriter_9600; + typedef TinyDebugSerialWriter_16_38400 TinyDebugSerialWriter_38400; + typedef TinyDebugSerialWriter_16_115200 TinyDebugSerialWriter_115200; + #define TINY_DEBUG_SERIAL_SUPPORTED 1 +/* + 9600... + 6, 90, 2 + 7, 77, 1 + 38400... + 1, 130, 2 + 5, 25, 1 + 18, 6, 0 + 115200... + 0, 39, 1 + 1, 38, 0 + 2, 18, 2 + 9, 3, 1 +*/ +#endif + + +#if TINY_DEBUG_SERIAL_SUPPORTED + +extern TinyDebugSerialWriter_9600 tdsw9600; +extern TinyDebugSerialWriter_38400 tdsw38400; +extern TinyDebugSerialWriter_115200 tdsw115200; + +void TinyDebugSerialBadBaud( void ) __attribute__((error("Serial (TinyDebugSerial) supports three baud rates: 9600, 38400, or 115200."))); +void TinyDebugSerialBaudMustBeConstant( void ) __attribute__((error("The baud rate for Serial (TinyDebugSerial) cannot be changed at run-time. Use 9600, 38400, or 115200."))); + +class TinyDebugSerial : public Stream +{ + protected: + + TinyDebugSerialWriter* _writer; + + void useStub( void ); + + public: + + TinyDebugSerial( void ); + + inline void begin( long baud ) + { + if ( __builtin_constant_p( baud ) ) + { + if ( baud == 9600 ) + { + _writer = &tdsw9600; + } + else if ( baud == 38400 ) + { + _writer = &tdsw38400; + } + else if ( baud == 115200 ) + { + _writer = &tdsw115200; + } + else + { + TinyDebugSerialBadBaud(); + } + } + else + { + TinyDebugSerialBaudMustBeConstant(); + } + _writer->init(); + } + + void end( void ) + { + useStub(); + } + + virtual int available( void ) + { + return( 0 ); + } + + virtual int peek( void ) + { + return( -1 ); + } + + virtual int read( void ) + { + return( -1 ); + } + + virtual void flush( void ) + { + } + + virtual size_t write( uint8_t c ) + { + _writer->write( c ); + return( 1 ); + } + + using Print::write; // pull in write(str) and write(buf, size) from Print +}; + +#if DEFAULT_TO_TINY_DEBUG_SERIAL +extern TinyDebugSerial Serial; +#endif + +#endif + + +#endif diff --git a/hardware/digistump/avr/cores/tiny/TinyDebugSerial115200.cpp b/hardware/digistump/avr/cores/tiny/TinyDebugSerial115200.cpp new file mode 100644 index 0000000..b9a45f2 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/TinyDebugSerial115200.cpp @@ -0,0 +1,26 @@ +/*============================================================================== + + TinyDebugSerial.cpp - Tiny write-only software serial. + + Copyright 2010 Rowdy Dog Software. + + This file is part of Arduino-Tiny. + + Arduino-Tiny is free software: you can redistribute it and/or modify it + under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation, either version 3 of the License, or (at your + option) any later version. + + Arduino-Tiny is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with Arduino-Tiny. If not, see . + +==============================================================================*/ + +#include "TinyDebugSerial.h" + +TinyDebugSerialWriter_115200 tdsw115200; diff --git a/hardware/digistump/avr/cores/tiny/TinyDebugSerial38400.cpp b/hardware/digistump/avr/cores/tiny/TinyDebugSerial38400.cpp new file mode 100644 index 0000000..daff205 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/TinyDebugSerial38400.cpp @@ -0,0 +1,26 @@ +/*============================================================================== + + TinyDebugSerial.cpp - Tiny write-only software serial. + + Copyright 2010 Rowdy Dog Software. + + This file is part of Arduino-Tiny. + + Arduino-Tiny is free software: you can redistribute it and/or modify it + under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation, either version 3 of the License, or (at your + option) any later version. + + Arduino-Tiny is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with Arduino-Tiny. If not, see . + +==============================================================================*/ + +#include "TinyDebugSerial.h" + +TinyDebugSerialWriter_38400 tdsw38400; diff --git a/hardware/digistump/avr/cores/tiny/TinyDebugSerial9600.cpp b/hardware/digistump/avr/cores/tiny/TinyDebugSerial9600.cpp new file mode 100644 index 0000000..678fcfd --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/TinyDebugSerial9600.cpp @@ -0,0 +1,26 @@ +/*============================================================================== + + TinyDebugSerial.cpp - Tiny write-only software serial. + + Copyright 2010 Rowdy Dog Software. + + This file is part of Arduino-Tiny. + + Arduino-Tiny is free software: you can redistribute it and/or modify it + under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation, either version 3 of the License, or (at your + option) any later version. + + Arduino-Tiny is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with Arduino-Tiny. If not, see . + +==============================================================================*/ + +#include "TinyDebugSerial.h" + +TinyDebugSerialWriter_9600 tdsw9600; diff --git a/hardware/digistump/avr/cores/tiny/TinyDebugSerialErrors.cpp b/hardware/digistump/avr/cores/tiny/TinyDebugSerialErrors.cpp new file mode 100644 index 0000000..d0085d2 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/TinyDebugSerialErrors.cpp @@ -0,0 +1,28 @@ +/*============================================================================== + + TinyDebugSerial.cpp - Tiny write-only software serial. + + Copyright 2010 Rowdy Dog Software. + + This file is part of Arduino-Tiny. + + Arduino-Tiny is free software: you can redistribute it and/or modify it + under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation, either version 3 of the License, or (at your + option) any later version. + + Arduino-Tiny is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with Arduino-Tiny. If not, see . + +==============================================================================*/ + +#include "TinyDebugSerial.h" + +void TinyDebugSerialWriterInternalBug( void ) { } +void TinyDebugSerialBadBaud( void ) { } +void TinyDebugSerialBaudMustBeConstant( void ) { } diff --git a/hardware/digistump/avr/cores/tiny/Tone.cpp b/hardware/digistump/avr/cores/tiny/Tone.cpp new file mode 100644 index 0000000..f8ea4eb --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/Tone.cpp @@ -0,0 +1,504 @@ +/* Tone.cpp + + A Tone Generator Library + + Written by Brett Hagman + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +Version Modified By Date Comments +------- ----------- -------- -------- +0001 B Hagman 09/08/02 Initial coding +0002 B Hagman 09/08/18 Multiple pins +0003 B Hagman 09/08/18 Moved initialization from constructor to begin() +0004 B Hagman 09/09/26 Fixed problems with ATmega8 +0005 B Hagman 09/11/23 Scanned prescalars for best fit on 8 bit timers + 09/11/25 Changed pin toggle method to XOR + 09/11/25 Fixed timer0 from being excluded +0006 D Mellis 09/12/29 Replaced objects with functions +0007 B Cook 10/05/03 Rewritten to only work with Timer1 and support direct hardware output +0008 B Cook 10/05/03 Rewritten so the timer can be selected at compile time + +*************************************************/ + +#define DEBUG_TONE 0 + +#include +#include "core_build_options.h" +#include "ToneTimer.h" +#include "pins_arduino.h" +#include "wiring.h" + +#if (TONETIMER_NUMBER_PRESCALERS != 5) && (TONETIMER_NUMBER_PRESCALERS != 15) +#error Only five or fifteen prescalers are supported. Update the code to support the number of actual prescalers. +#endif + +#if TONETIMER_NUMBER_PRESCALERS == 15 +#define TONETIMER_MAXIMUM_DIVISOR ( (unsigned long)(TONETIMER_(PRESCALER_VALUE_15)) * (1L + (unsigned long)(TONETIMER_(MAXIMUM_OCR))) ) +#endif + +#if TONETIMER_NUMBER_PRESCALERS == 5 +#define TONETIMER_MAXIMUM_DIVISOR ( (unsigned long)(TONETIMER_(PRESCALER_VALUE_5)) * (1L + (unsigned long)(TONETIMER_(MAXIMUM_OCR))) ) +#endif + +const unsigned int Tone_Lowest_Frequency = (F_CPU + (2L * TONETIMER_MAXIMUM_DIVISOR - 1L)) / (2L * TONETIMER_MAXIMUM_DIVISOR); + +#if (TONETIMER_(MAXIMUM_OCR) == 65535) && (TONETIMER_(PRESCALE_SET) == 1) +#if F_CPU <= 1000000 + #define TONE_FREQUENCY_CUTOFF_2 (7) + #define TONE_FREQUENCY_CUTOFF_1 (65535) +#elif F_CPU <= 8000000 + #define TONE_FREQUENCY_CUTOFF_3 (7) + #define TONE_FREQUENCY_CUTOFF_2 (61) + #define TONE_FREQUENCY_CUTOFF_1 (65535) +#elif F_CPU <= 16000000 + #define TONE_FREQUENCY_CUTOFF_4 (1) + #define TONE_FREQUENCY_CUTOFF_3 (15) + #define TONE_FREQUENCY_CUTOFF_2 (122) + #define TONE_FREQUENCY_CUTOFF_1 (65535) +#elif F_CPU <= 16500000 + #define TONE_FREQUENCY_CUTOFF_4 (1) + #define TONE_FREQUENCY_CUTOFF_3 (15) + #define TONE_FREQUENCY_CUTOFF_2 (122) + #define TONE_FREQUENCY_CUTOFF_1 (65535) +#endif +#endif + +#if (TONETIMER_(MAXIMUM_OCR) == 255) && (TONETIMER_(PRESCALE_SET) == 1) +#if F_CPU <= 1000000 + #define TONE_FREQUENCY_CUTOFF_5 (7) + #define TONE_FREQUENCY_CUTOFF_4 (30) + #define TONE_FREQUENCY_CUTOFF_3 (243) + #define TONE_FREQUENCY_CUTOFF_2 (1949) + #define TONE_FREQUENCY_CUTOFF_1 (65535) +#elif F_CPU <= 8000000 + #define TONE_FREQUENCY_CUTOFF_5 (60) + #define TONE_FREQUENCY_CUTOFF_4 (243) + #define TONE_FREQUENCY_CUTOFF_3 (1949) + #define TONE_FREQUENCY_CUTOFF_2 (15594) + #define TONE_FREQUENCY_CUTOFF_1 (65535) +#elif F_CPU <= 16000000 + #define TONE_FREQUENCY_CUTOFF_5 (121) + #define TONE_FREQUENCY_CUTOFF_4 (487) + #define TONE_FREQUENCY_CUTOFF_3 (3898) + #define TONE_FREQUENCY_CUTOFF_2 (31189) + #define TONE_FREQUENCY_CUTOFF_1 (65535) +#elif F_CPU <= 16500000 + #define TONE_FREQUENCY_CUTOFF_5 (121) + #define TONE_FREQUENCY_CUTOFF_4 (487) + #define TONE_FREQUENCY_CUTOFF_3 (3898) + #define TONE_FREQUENCY_CUTOFF_2 (31189) + #define TONE_FREQUENCY_CUTOFF_1 (65535) +#endif +#endif + +#if (TONETIMER_(MAXIMUM_OCR) == 255) && (TONETIMER_(PRESCALE_SET) == 2) +#if F_CPU <= 1000000 + #define TONE_FREQUENCY_CUTOFF_12 (1) + #define TONE_FREQUENCY_CUTOFF_11 (3) + #define TONE_FREQUENCY_CUTOFF_10 (7) + #define TONE_FREQUENCY_CUTOFF_9 (15) + #define TONE_FREQUENCY_CUTOFF_8 (30) + #define TONE_FREQUENCY_CUTOFF_7 (60) + #define TONE_FREQUENCY_CUTOFF_6 (121) + #define TONE_FREQUENCY_CUTOFF_5 (243) + #define TONE_FREQUENCY_CUTOFF_4 (487) + #define TONE_FREQUENCY_CUTOFF_3 (974) + #define TONE_FREQUENCY_CUTOFF_2 (1949) + #define TONE_FREQUENCY_CUTOFF_1 (65535) +#elif F_CPU <= 8000000 + #define TONE_FREQUENCY_CUTOFF_15 (1) + #define TONE_FREQUENCY_CUTOFF_14 (3) + #define TONE_FREQUENCY_CUTOFF_13 (7) + #define TONE_FREQUENCY_CUTOFF_12 (15) + #define TONE_FREQUENCY_CUTOFF_11 (30) + #define TONE_FREQUENCY_CUTOFF_10 (60) + #define TONE_FREQUENCY_CUTOFF_9 (121) + #define TONE_FREQUENCY_CUTOFF_8 (243) + #define TONE_FREQUENCY_CUTOFF_7 (487) + #define TONE_FREQUENCY_CUTOFF_6 (974) + #define TONE_FREQUENCY_CUTOFF_5 (1949) + #define TONE_FREQUENCY_CUTOFF_4 (3898) + #define TONE_FREQUENCY_CUTOFF_3 (7797) + #define TONE_FREQUENCY_CUTOFF_2 (15594) + #define TONE_FREQUENCY_CUTOFF_1 (65535) +#elif F_CPU <= 16000000 + #define TONE_FREQUENCY_CUTOFF_15 (3) + #define TONE_FREQUENCY_CUTOFF_14 (7) + #define TONE_FREQUENCY_CUTOFF_13 (15) + #define TONE_FREQUENCY_CUTOFF_12 (30) + #define TONE_FREQUENCY_CUTOFF_11 (60) + #define TONE_FREQUENCY_CUTOFF_10 (121) + #define TONE_FREQUENCY_CUTOFF_9 (243) + #define TONE_FREQUENCY_CUTOFF_8 (487) + #define TONE_FREQUENCY_CUTOFF_7 (974) + #define TONE_FREQUENCY_CUTOFF_6 (1949) + #define TONE_FREQUENCY_CUTOFF_5 (3898) + #define TONE_FREQUENCY_CUTOFF_4 (7797) + #define TONE_FREQUENCY_CUTOFF_3 (15594) + #define TONE_FREQUENCY_CUTOFF_2 (31189) + #define TONE_FREQUENCY_CUTOFF_1 (65535) +#elif F_CPU <= 16500000 + #define TONE_FREQUENCY_CUTOFF_15 (3) + #define TONE_FREQUENCY_CUTOFF_14 (7) + #define TONE_FREQUENCY_CUTOFF_13 (15) + #define TONE_FREQUENCY_CUTOFF_12 (30) + #define TONE_FREQUENCY_CUTOFF_11 (60) + #define TONE_FREQUENCY_CUTOFF_10 (121) + #define TONE_FREQUENCY_CUTOFF_9 (243) + #define TONE_FREQUENCY_CUTOFF_8 (487) + #define TONE_FREQUENCY_CUTOFF_7 (974) + #define TONE_FREQUENCY_CUTOFF_6 (1949) + #define TONE_FREQUENCY_CUTOFF_5 (3898) + #define TONE_FREQUENCY_CUTOFF_4 (7797) + #define TONE_FREQUENCY_CUTOFF_3 (15594) + #define TONE_FREQUENCY_CUTOFF_2 (31189) + #define TONE_FREQUENCY_CUTOFF_1 (65535) +#endif +#endif + + +#if DEBUG_TONE +uint16_t debug_tone_last_OCRxA; +uint16_t debug_tone_last_CSV; +#endif + + +// timerx_toggle_count: +// > 0 - duration specified +// = 0 - stopped +// < 0 - infinitely (until stop() method called, or new play() called) + +static volatile long tone_timer_toggle_count; +static volatile uint8_t *tone_timer_pin_register; +static volatile uint8_t tone_timer_pin_mask; + +static uint8_t tone_pin = 255; + + +void tone( uint8_t _pin, unsigned int frequency, unsigned long duration ) +{ + tonetimer_(ocr_t) ocr; + tonetimer_(prescale_value_t) csv; + tonetimer_(cs_t) csi; + + if ( tone_pin == 255 ) + { + /* Set the timer to power-up conditions so we start from a known state */ + ToneTimer_SetToPowerup(); + + /* + Compare Output Mode = Normal port operation, OCxA/OCxB disconnected. + Waveform Generation Mode = 4; 0100; CTC; (Clear Timer on Compare); OCR1A; Immediate; MAX + Clock Select = No clock source (Timer/Counter stopped). + Note: Turn off the clock first to avoid ticks and scratches. + */ + ToneTimer_SetWaveformGenerationMode( ToneTimer_(CTC_OCR) ); + + /* If the tone pin can be driven directly from the timer */ + + if ( (_pin == ToneTimer_OutputComparePinA) || (_pin == ToneTimer_OutputComparePinB) ) + { + /* Pin toggling is handled by the hardware */ + tone_timer_pin_register = NULL; + tone_timer_pin_mask = 0; + + if ( _pin == ToneTimer_OutputComparePinA ) + { + /* Compare Output Mode = Toggle OCxA on Compare Match. */ + ToneTimer_SetCompareOutputModeA( ToneTimer_(Toggle) ); + } + else // if ( _pin == ToneTimer_OutputComparePinB ) + { + /* Compare Output Mode = Toggle OCxA on Compare Match. */ + ToneTimer_SetCompareOutputModeB( ToneTimer_(Toggle) ); + } + } + else + { + /* Save information needed by the interrupt service routine */ + tone_timer_pin_register = portOutputRegister( digitalPinToPort( _pin ) ); + tone_timer_pin_mask = digitalPinToBitMask( _pin ); + + /* Compare Output Mode = Normal port operation, OCxA disconnected. */ + ToneTimer_DisconnectOutputs(); + } + + /* Ensure the pin is configured for output */ + pinMode( _pin, OUTPUT ); + + tone_pin = _pin; + } + + if ( tone_pin == _pin ) + { + /* Stop the clock while we make changes. */ + + ToneTimer_ClockSelect( ToneTimer_(Stopped) ); + + /* Start the counter at zero to reduce ticks and scratches. */ + + ToneTimer_SetCount( 0 ); + + if ( frequency > 0 ) + { + if ( frequency < Tone_Lowest_Frequency ) + { + frequency = Tone_Lowest_Frequency; + } + + /* Determine which prescaler to use */ + /* Set the Output Compare Register (rounding up) */ + + #if defined( TONE_FREQUENCY_CUTOFF_15 ) + if ( frequency <= TONE_FREQUENCY_CUTOFF_15 ) + { + csv = TONETIMER_(PRESCALER_VALUE_15); + csi = ToneTimer_(Prescale_Index_15); + } + else + #endif + + #if defined( TONE_FREQUENCY_CUTOFF_14 ) + if ( frequency <= TONE_FREQUENCY_CUTOFF_14 ) + { + csv = TONETIMER_(PRESCALER_VALUE_14); + csi = ToneTimer_(Prescale_Index_14); + } + else + #endif + + #if defined( TONE_FREQUENCY_CUTOFF_13 ) + if ( frequency <= TONE_FREQUENCY_CUTOFF_13 ) + { + csv = TONETIMER_(PRESCALER_VALUE_13); + csi = ToneTimer_(Prescale_Index_13); + } + else + #endif + + #if defined( TONE_FREQUENCY_CUTOFF_12 ) + if ( frequency <= TONE_FREQUENCY_CUTOFF_12 ) + { + csv = TONETIMER_(PRESCALER_VALUE_12); + csi = ToneTimer_(Prescale_Index_12); + } + else + #endif + + #if defined( TONE_FREQUENCY_CUTOFF_11 ) + if ( frequency <= TONE_FREQUENCY_CUTOFF_11 ) + { + csv = TONETIMER_(PRESCALER_VALUE_11); + csi = ToneTimer_(Prescale_Index_11); + } + else + #endif + + #if defined( TONE_FREQUENCY_CUTOFF_10 ) + if ( frequency <= TONE_FREQUENCY_CUTOFF_10 ) + { + csv = TONETIMER_(PRESCALER_VALUE_10); + csi = ToneTimer_(Prescale_Index_10); + } + else + #endif + + #if defined( TONE_FREQUENCY_CUTOFF_9 ) + if ( frequency <= TONE_FREQUENCY_CUTOFF_9 ) + { + csv = TONETIMER_(PRESCALER_VALUE_9); + csi = ToneTimer_(Prescale_Index_9); + } + else + #endif + + #if defined( TONE_FREQUENCY_CUTOFF_8 ) + if ( frequency <= TONE_FREQUENCY_CUTOFF_8 ) + { + csv = TONETIMER_(PRESCALER_VALUE_8); + csi = ToneTimer_(Prescale_Index_8); + } + else + #endif + + #if defined( TONE_FREQUENCY_CUTOFF_7 ) + if ( frequency <= TONE_FREQUENCY_CUTOFF_7 ) + { + csv = TONETIMER_(PRESCALER_VALUE_7); + csi = ToneTimer_(Prescale_Index_7); + } + else + #endif + + #if defined( TONE_FREQUENCY_CUTOFF_6 ) + if ( frequency <= TONE_FREQUENCY_CUTOFF_6 ) + { + csv = TONETIMER_(PRESCALER_VALUE_6); + csi = ToneTimer_(Prescale_Index_6); + } + else + #endif + + #if defined( TONE_FREQUENCY_CUTOFF_5 ) + if ( frequency <= TONE_FREQUENCY_CUTOFF_5 ) + { + csv = TONETIMER_(PRESCALER_VALUE_5); + csi = ToneTimer_(Prescale_Index_5); + } + else + #endif + + #if defined( TONE_FREQUENCY_CUTOFF_4 ) + if ( frequency <= TONE_FREQUENCY_CUTOFF_4 ) + { + csv = TONETIMER_(PRESCALER_VALUE_4); + csi = ToneTimer_(Prescale_Index_4); + } + else + #endif + + #if defined( TONE_FREQUENCY_CUTOFF_3 ) + if ( frequency <= TONE_FREQUENCY_CUTOFF_3 ) + { + csv = TONETIMER_(PRESCALER_VALUE_3); + csi = ToneTimer_(Prescale_Index_3); + } + else + #endif + + if ( frequency <= TONE_FREQUENCY_CUTOFF_2 ) + { + csv = TONETIMER_(PRESCALER_VALUE_2); + csi = ToneTimer_(Prescale_Index_2); + } + + else // if ( frequency <= TONE_FREQUENCY_CUTOFF_1 ) + { + csv = TONETIMER_(PRESCALER_VALUE_1); + csi = ToneTimer_(Prescale_Index_1); + } + + ocr = ( (2L * F_CPU) / (frequency * 2L * csv) + 1L ) / 2L - 1L; + ToneTimer_SetOutputCompareMatchAndClear( ocr ); + + #if DEBUG_TONE + debug_tone_last_OCRxA = ocr; + debug_tone_last_CSV = csv; + #endif + + /* Does the caller want a specific duration? */ + if ( duration > 0 ) + { + /* Determine how many times the value toggles */ + tone_timer_toggle_count = (2 * frequency * duration) / 1000; + + /* Output Compare A Match Interrupt Enable */ + ToneTimer_EnableOutputCompareInterruptA(); + } + else + { + /* Indicate to the interrupt service routine that we'll be running until further notice */ + tone_timer_toggle_count = -1; + + /* All pins but the OCxA / OCxB pins have to be driven by software */ + if ( (_pin != ToneTimer_OutputComparePinA) && (_pin != ToneTimer_OutputComparePinB) ) + { + /* Output Compare A Match Interrupt Enable */ + ToneTimer_EnableOutputCompareInterruptA(); + } + } + + /* Start the clock... */ + + ToneTimer_ClockSelect( csi ); + } + else + { + /* To be on the safe side, turn off all interrupts */ + ToneTimer_InterruptsOff(); + + /* Clock is stopped. Counter is zero. The only thing left to do is turn off the output. */ + digitalWrite( _pin, 0 ); + } + } +} + + +void noTone( uint8_t _pin ) +{ + if ( (tone_pin != 255) + && ((tone_pin == _pin) || (_pin == 255)) ) + { + // Turn off all interrupts + ToneTimer_InterruptsOff(); + + // Stop the clock while we make changes. + ToneTimer_ClockSelect( ToneTimer_(Stopped) ); + + // Set the Tone Timer exactly the same as init did... + initToneTimer(); + +//rmv ToneTimer_SetToPowerup(); + + /* rmv + // put timer 1 in 8-bit phase correct pwm mode + TCCR1A = (0< 0 ) + { + --tone_timer_toggle_count; + + if ( tone_timer_toggle_count == 0 ) + { + // Shutdown the hardware + noTone( 255 ); + + // Skip the rest. We're finished. + return; + } + } + *tone_timer_pin_register ^= tone_timer_pin_mask; + } + else + { + // Shutdown the hardware + noTone( 255 ); + } +} diff --git a/hardware/digistump/avr/cores/tiny/ToneTimer.h b/hardware/digistump/avr/cores/tiny/ToneTimer.h new file mode 100644 index 0000000..e71c7a1 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/ToneTimer.h @@ -0,0 +1,50 @@ +/*============================================================================== + + ToneTimer.h - Veneer for the Tone Timer. + + Copyright 2010 Rowdy Dog Software. + + This file is part of Arduino-Tiny. + + Arduino-Tiny is free software: you can redistribute it and/or modify it + under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation, either version 3 of the License, or (at your + option) any later version. + + Arduino-Tiny is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with Arduino-Tiny. If not, see . + +==============================================================================*/ + +#ifndef ToneTimer_h +#define ToneTimer_h + +#include "core_build_options.h" +#include "core_timers.h" + +#define tonetimer_(t) TIMER_PASTE_A( timer, TIMER_TO_USE_FOR_TONE, t ) +#define ToneTimer_(f) TIMER_PASTE_A( Timer, TIMER_TO_USE_FOR_TONE, f ) +#define TONETIMER_(c) TIMER_PASTE_A( TIMER, TIMER_TO_USE_FOR_TONE, c ) + +#define ToneTimer_SetToPowerup ToneTimer_(SetToPowerup) +#define ToneTimer_SetWaveformGenerationMode ToneTimer_(SetWaveformGenerationMode) +#define ToneTimer_OutputComparePinA ToneTimer_(OutputComparePinA) +#define ToneTimer_OutputComparePinB ToneTimer_(OutputComparePinB) +#define ToneTimer_SetCompareOutputModeA ToneTimer_(SetCompareOutputModeA) +#define ToneTimer_SetCompareOutputModeB ToneTimer_(SetCompareOutputModeB) +#define ToneTimer_DisconnectOutputs ToneTimer_(DisconnectOutputs) +#define ToneTimer_ClockSelect ToneTimer_(ClockSelect) +#define ToneTimer_SetCount ToneTimer_(SetCount) +#define TONETIMER_NUMBER_PRESCALERS TONETIMER_(NUMBER_PRESCALERS) +#define ToneTimer_SetOutputCompareMatchAndClear ToneTimer_(SetOutputCompareMatchAndClear) +#define ToneTimer_InterruptsOff ToneTimer_(InterruptsOff) +#define ToneTimer_EnableOutputCompareInterruptA ToneTimer_(EnableOutputCompareInterruptA) +#define TONETIMER_COMPA_vect TONETIMER_(COMPA_vect) +#define TONETIMER_SUPPORTS_PHASE_CORRECT_PWM TONETIMER_(SUPPORTS_PHASE_CORRECT_PWM) + +#endif diff --git a/hardware/digistump/avr/cores/tiny/UserTimer.h b/hardware/digistump/avr/cores/tiny/UserTimer.h new file mode 100644 index 0000000..64fa551 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/UserTimer.h @@ -0,0 +1,78 @@ +/*============================================================================== + + UserTimer.h - Veneer for the User Timer (same timer as the one used for + Tone) + + Copyright 2010 Rowdy Dog Software. + + This file is part of Arduino-Tiny. + + Arduino-Tiny is free software: you can redistribute it and/or modify it + under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation, either version 3 of the License, or (at your + option) any later version. + + Arduino-Tiny is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with Arduino-Tiny. If not, see . + +==============================================================================*/ + +#ifndef UserTimer_h +#define UserTimer_h + +#include "core_build_options.h" +#include "core_timers.h" + + +/*============================================================================= + Assume there are only two timers. One for millis and one for everything + else. +=============================================================================*/ + +#if TIMER_TO_USE_FOR_MILLIS == 0 +#define TIMER_TO_USE_FOR_USER 1 +#elif TIMER_TO_USE_FOR_MILLIS == 1 +#define TIMER_TO_USE_FOR_USER 0 +#else +#error Unexpected condition in UserTimer.h. +#endif + + +/*============================================================================= + Macros to help generate the macros below +=============================================================================*/ + +#define usertimer_(t) TIMER_PASTE_A( timer, TIMER_TO_USE_FOR_USER, t ) +#define UserTimer_(f) TIMER_PASTE_A( Timer, TIMER_TO_USE_FOR_USER, f ) +#define USERTIMER_(c) TIMER_PASTE_A( TIMER, TIMER_TO_USE_FOR_USER, c ) + + +/*============================================================================= + Macros to provide a veneer over the data-types, functions, and constants in + core_timers.h +=============================================================================*/ + +#define UserTimer_SetToPowerup UserTimer_(SetToPowerup) +#define UserTimer_InterruptsOff UserTimer_(InterruptsOff) +#define UserTimer_ClockSelect UserTimer_(ClockSelect) +#define UserTimer_SetWaveformGenerationMode UserTimer_(SetWaveformGenerationMode) +#define UserTimer_SetCompareOutputModeA UserTimer_(SetCompareOutputModeA) +#define UserTimer_SetCompareOutputModeB UserTimer_(SetCompareOutputModeB) +#define UserTimer_SetOutputCompareMatchAndClear UserTimer_(SetOutputCompareMatchAndClear) +#define UserTimer_EnableOutputCompareInterruptA UserTimer_(EnableOutputCompareInterruptA) +#define UserTimer_EnableOverflowInterrupt UserTimer_(EnableOverflowInterrupt) +#define UserTimer_GetCount UserTimer_(GetCount) +#define UserTimer_SetCount UserTimer_(SetCount) +#define UserTimer_IsOverflowSet UserTimer_(IsOverflowSet) + +#define USERTIMER_OVF_vect USERTIMER_(OVF_vect) +#define USERTIMER_COMPA_vect USERTIMER_(COMPA_vect) +#define USERTIMER_COMPB_vect USERTIMER_(COMPB_vect) + + +#endif diff --git a/hardware/digistump/avr/cores/tiny/WCharacter.h b/hardware/digistump/avr/cores/tiny/WCharacter.h new file mode 100644 index 0000000..79733b5 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/WCharacter.h @@ -0,0 +1,168 @@ +/* + WCharacter.h - Character utility functions for Wiring & Arduino + Copyright (c) 2010 Hernando Barragan. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Character_h +#define Character_h + +#include + +// WCharacter.h prototypes +inline boolean isAlphaNumeric(int c) __attribute__((always_inline)); +inline boolean isAlpha(int c) __attribute__((always_inline)); +inline boolean isAscii(int c) __attribute__((always_inline)); +inline boolean isWhitespace(int c) __attribute__((always_inline)); +inline boolean isControl(int c) __attribute__((always_inline)); +inline boolean isDigit(int c) __attribute__((always_inline)); +inline boolean isGraph(int c) __attribute__((always_inline)); +inline boolean isLowerCase(int c) __attribute__((always_inline)); +inline boolean isPrintable(int c) __attribute__((always_inline)); +inline boolean isPunct(int c) __attribute__((always_inline)); +inline boolean isSpace(int c) __attribute__((always_inline)); +inline boolean isUpperCase(int c) __attribute__((always_inline)); +inline boolean isHexadecimalDigit(int c) __attribute__((always_inline)); +inline int toAscii(int c) __attribute__((always_inline)); +inline int toLowerCase(int c) __attribute__((always_inline)); +inline int toUpperCase(int c)__attribute__((always_inline)); + + +// Checks for an alphanumeric character. +// It is equivalent to (isalpha(c) || isdigit(c)). +inline boolean isAlphaNumeric(int c) +{ + return ( isalnum(c) == 0 ? false : true); +} + + +// Checks for an alphabetic character. +// It is equivalent to (isupper(c) || islower(c)). +inline boolean isAlpha(int c) +{ + return ( isalpha(c) == 0 ? false : true); +} + + +// Checks whether c is a 7-bit unsigned char value +// that fits into the ASCII character set. +inline boolean isAscii(int c) +{ + return ( isascii (c) == 0 ? false : true); +} + + +// Checks for a blank character, that is, a space or a tab. +inline boolean isWhitespace(int c) +{ + return ( isblank (c) == 0 ? false : true); +} + + +// Checks for a control character. +inline boolean isControl(int c) +{ + return ( iscntrl (c) == 0 ? false : true); +} + + +// Checks for a digit (0 through 9). +inline boolean isDigit(int c) +{ + return ( isdigit (c) == 0 ? false : true); +} + + +// Checks for any printable character except space. +inline boolean isGraph(int c) +{ + return ( isgraph (c) == 0 ? false : true); +} + + +// Checks for a lower-case character. +inline boolean isLowerCase(int c) +{ + return (islower (c) == 0 ? false : true); +} + + +// Checks for any printable character including space. +inline boolean isPrintable(int c) +{ + return ( isprint (c) == 0 ? false : true); +} + + +// Checks for any printable character which is not a space +// or an alphanumeric character. +inline boolean isPunct(int c) +{ + return ( ispunct (c) == 0 ? false : true); +} + + +// Checks for white-space characters. For the avr-libc library, +// these are: space, formfeed ('\f'), newline ('\n'), carriage +// return ('\r'), horizontal tab ('\t'), and vertical tab ('\v'). +inline boolean isSpace(int c) +{ + return ( isspace (c) == 0 ? false : true); +} + + +// Checks for an uppercase letter. +inline boolean isUpperCase(int c) +{ + return ( isupper (c) == 0 ? false : true); +} + + +// Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7 +// 8 9 a b c d e f A B C D E F. +inline boolean isHexadecimalDigit(int c) +{ + return ( isxdigit (c) == 0 ? false : true); +} + + +// Converts c to a 7-bit unsigned char value that fits into the +// ASCII character set, by clearing the high-order bits. +inline int toAscii(int c) +{ + return toascii (c); +} + + +// Warning: +// Many people will be unhappy if you use this function. +// This function will convert accented letters into random +// characters. + +// Converts the letter c to lower case, if possible. +inline int toLowerCase(int c) +{ + return tolower (c); +} + + +// Converts the letter c to upper case, if possible. +inline int toUpperCase(int c) +{ + return toupper (c); +} + +#endif \ No newline at end of file diff --git a/hardware/digistump/avr/cores/tiny/WConstants.h b/hardware/digistump/avr/cores/tiny/WConstants.h new file mode 100644 index 0000000..3e19ac4 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/WConstants.h @@ -0,0 +1 @@ +#include "wiring.h" diff --git a/hardware/digistump/avr/cores/tiny/WInterrupts.c b/hardware/digistump/avr/cores/tiny/WInterrupts.c new file mode 100644 index 0000000..4c1410b --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/WInterrupts.c @@ -0,0 +1,148 @@ +/* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */ + +/* + Part of the Wiring project - http://wiring.uniandes.edu.co + + Copyright (c) 2004-05 Hernando Barragan + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + Modified 24 November 2006 by David A. Mellis + + Modified 28-08-2009 for attiny84 R.Wiersma + Modified 09-10-2009 for attiny45 A.Saporetti + Modified 20-11-2010 - B.Cook - Correct a minor bug in attachInterrupt +*/ + +#include +#include +#include +#include +#include + +#include "WConstants.h" +#include "wiring_private.h" + +volatile static voidFuncPtr intFunc[NUMBER_EXTERNAL_INTERRUPTS]; + +#if defined( MCUCR ) && ! defined( EICRA ) + #define EICRA MCUCR +#endif + +#if defined( GIMSK ) && ! defined( EIMSK ) + #define EIMSK GIMSK +#endif + +void attachInterrupt(uint8_t interruptNum, void (*userFunc)(void), int mode) +{ + if ( interruptNum < NUMBER_EXTERNAL_INTERRUPTS ) + { + /* + If attachInterrupt is called in succession for the same + interruptNum but a different userFunc then the following line + is not safe. Changing intFunc is not atomic. + intFunc[interruptNum] = userFunc; + */ + { + // save interrupt flag + uint8_t SaveSREG = SREG; + // disable interrupts + cli(); + // access the shared data + intFunc[interruptNum] = userFunc; + // restore the interrupt flag + SREG = SaveSREG; + } + + // Configure the interrupt mode (trigger on low input, any change, rising + // edge, or falling edge). The mode constants were chosen to correspond + // to the configuration bits in the hardware register, so we simply shift + // the mode into place. + + // Enable the interrupt. + + switch ( interruptNum ) + { + #if NUMBER_EXTERNAL_INTERRUPTS >= 1 + case EXTERNAL_INTERRUPT_0: + EICRA = (EICRA & ~((1 << ISC00) | (1 << ISC01))) | (mode << ISC00); + EIMSK |= (1 << INT0); + break; + #endif + + #if NUMBER_EXTERNAL_INTERRUPTS >= 2 + case EXTERNAL_INTERRUPT_1: + EICRA = (EICRA & ~((1 << ISC10) | (1 << ISC11))) | (mode << ISC10); + EIMSK |= (1 << INT1); + break; + #endif + + #if NUMBER_EXTERNAL_INTERRUPTS > 2 + #error Add handlers for the additional interrupts. + #endif + } + } +} + +void detachInterrupt(uint8_t interruptNum) +{ + if ( interruptNum < NUMBER_EXTERNAL_INTERRUPTS ) + { + // Disable the interrupt. (We can't assume that interruptNum is equal + // to the number of the EIMSK bit to clear, as this isn't true on the + // ATmega8. There, INT0 is 6 and INT1 is 7.) + + switch (interruptNum) + { + #if NUMBER_EXTERNAL_INTERRUPTS >= 1 + case EXTERNAL_INTERRUPT_0: + EIMSK &= ~(1 << INT0); + break;; + #endif + + #if NUMBER_EXTERNAL_INTERRUPTS >= 2 + case EXTERNAL_INTERRUPT_1: + EIMSK &= ~(1 << INT1); + break;; + #endif + + #if NUMBER_EXTERNAL_INTERRUPTS > 2 + #error Add handlers for the additional interrupts. + #endif + } + intFunc[interruptNum] = 0; + } +} + +#if NUMBER_EXTERNAL_INTERRUPTS >= 1 +ISR(EXTERNAL_INTERRUPT_0_vect, ISR_NOBLOCK) +{ + if(intFunc[EXTERNAL_INTERRUPT_0]) + intFunc[EXTERNAL_INTERRUPT_0](); +} +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 2 +ISR(EXTERNAL_INTERRUPT_1_vect, ISR_NOBLOCK) +{ + if(intFunc[EXTERNAL_INTERRUPT_1]) + intFunc[EXTERNAL_INTERRUPT_1](); +} +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS > 2 +#error Add handlers for the additional interrupts. +#endif diff --git a/hardware/digistump/avr/cores/tiny/WMath.cpp b/hardware/digistump/avr/cores/tiny/WMath.cpp new file mode 100644 index 0000000..2120c4c --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/WMath.cpp @@ -0,0 +1,60 @@ +/* -*- mode: jde; c-basic-offset: 2; indent-tabs-mode: nil -*- */ + +/* + Part of the Wiring project - http://wiring.org.co + Copyright (c) 2004-06 Hernando Barragan + Modified 13 August 2006, David A. Mellis for Arduino - http://www.arduino.cc/ + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id$ +*/ + +extern "C" { + #include "stdlib.h" +} + +void randomSeed(unsigned int seed) +{ + if (seed != 0) { + srandom(seed); + } +} + +long random(long howbig) +{ + if (howbig == 0) { + return 0; + } + return random() % howbig; +} + +long random(long howsmall, long howbig) +{ + if (howsmall >= howbig) { + return howsmall; + } + long diff = howbig - howsmall; + return random(diff) + howsmall; +} + +long map(long x, long in_min, long in_max, long out_min, long out_max) +{ + return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min; +} + +unsigned int makeWord(unsigned int w) { return w; } +unsigned int makeWord(unsigned char h, unsigned char l) { return (h << 8) | l; } \ No newline at end of file diff --git a/hardware/digistump/avr/cores/tiny/WProgram.h b/hardware/digistump/avr/cores/tiny/WProgram.h new file mode 100644 index 0000000..aaa83dc --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/WProgram.h @@ -0,0 +1,83 @@ +#ifndef WProgram_h +#define WProgram_h + +#include +#include +#include + +#include + +#include "core_build_options.h" +#include "core_pins.h" +#include "wiring.h" +#include "pins_arduino.h" + +#ifdef __cplusplus +#include "WCharacter.h" +#include "WString.h" +#include "TinyDebugSerial.h" +#include "HardwareSerial.h" + +uint16_t makeWord(uint16_t w); +uint16_t makeWord(byte h, byte l); + +#define word(...) makeWord(__VA_ARGS__) + +unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout = 1000000L); + +void tone(uint8_t _pin, unsigned int frequency, unsigned long duration = 0); +void noTone(uint8_t _pin = 255); + +// WMath prototypes +long random(long); +long random(long, long); +void randomSeed(unsigned int); +long map(long, long, long, long, long); + +/* + fix? On the Mega processors, the analogs are also "extended" digital pins. + To (sort of) work the same way with this core, the following constants + would have to be valid arguments to digitalRead, digitalWrite, and pinMode + ("the digitals"). Which means the digitals would have to check for pins + over A0 and then subtract A0. The current plan is to wait until someone + wants this feature. +*/ +#if CORE_ANALOG_COUNT >= 1 +const static uint8_t A0 = CORE_ANALOG_FIRST + 0; +#endif + +#if CORE_ANALOG_COUNT >= 2 +const static uint8_t A1 = CORE_ANALOG_FIRST + 1; +#endif + +#if CORE_ANALOG_COUNT >= 3 +const static uint8_t A2 = CORE_ANALOG_FIRST + 2; +#endif + +#if CORE_ANALOG_COUNT >= 4 +const static uint8_t A3 = CORE_ANALOG_FIRST + 3; +#endif + +#if CORE_ANALOG_COUNT >= 5 +const static uint8_t A4 = CORE_ANALOG_FIRST + 4; +#endif + +#if CORE_ANALOG_COUNT >= 6 +const static uint8_t A5 = CORE_ANALOG_FIRST + 5; +#endif + +#if CORE_ANALOG_COUNT >= 7 +const static uint8_t A6 = CORE_ANALOG_FIRST + 6; +#endif + +#if CORE_ANALOG_COUNT >= 8 +const static uint8_t A7 = CORE_ANALOG_FIRST + 7; +#endif + +#if CORE_ANALOG_COUNT >= 9 +#error Update the A* definitions for the selected processor. +#endif + +#endif + +#endif diff --git a/hardware/digistump/avr/cores/tiny/WString.cpp b/hardware/digistump/avr/cores/tiny/WString.cpp new file mode 100644 index 0000000..db5a441 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/WString.cpp @@ -0,0 +1,443 @@ +/* + WString.cpp - String library for Wiring & Arduino + Copyright (c) 2009-10 Hernando Barragan. All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include +#include "WProgram.h" +#include "WString.h" + + +String::String( const char *value ) +{ + if ( value == NULL ) + value = ""; + getBuffer( _length = strlen( value ) ); + if ( _buffer != NULL ) + strcpy( _buffer, value ); +} + +String::String( const String &value ) +{ + getBuffer( _length = value._length ); + if ( _buffer != NULL ) + strcpy( _buffer, value._buffer ); +} + +String::String( const char value ) +{ + _length = 1; + getBuffer(1); + if ( _buffer != NULL ) { + _buffer[0] = value; + _buffer[1] = 0; + } +} + +String::String( const unsigned char value ) +{ + _length = 1; + getBuffer(1); + if ( _buffer != NULL) { + _buffer[0] = value; + _buffer[1] = 0; + } +} + +String::String( const int value, const int base ) +{ + char buf[33]; + itoa((signed long)value, buf, base); + getBuffer( _length = strlen(buf) ); + if ( _buffer != NULL ) + strcpy( _buffer, buf ); +} + +String::String( const unsigned int value, const int base ) +{ + char buf[33]; + ultoa((unsigned long)value, buf, base); + getBuffer( _length = strlen(buf) ); + if ( _buffer != NULL ) + strcpy( _buffer, buf ); +} + +String::String( const long value, const int base ) +{ + char buf[33]; + ltoa(value, buf, base); + getBuffer( _length = strlen(buf) ); + if ( _buffer != NULL ) + strcpy( _buffer, buf ); +} + +String::String( const unsigned long value, const int base ) +{ + char buf[33]; + ultoa(value, buf, 10); + getBuffer( _length = strlen(buf) ); + if ( _buffer != NULL ) + strcpy( _buffer, buf ); +} + +char String::charAt( unsigned int loc ) const +{ + return operator[]( loc ); +} + +void String::setCharAt( unsigned int loc, const char aChar ) +{ + if(_buffer == NULL) return; + if(_length > loc) { + _buffer[loc] = aChar; + } +} + +int String::compareTo( const String &s2 ) const +{ + return strcmp( _buffer, s2._buffer ); +} + +const String & String::concat( const String &s2 ) +{ + return (*this) += s2; +} + +const String & String::operator=( const String &rhs ) +{ + if ( this == &rhs ) + return *this; + + if ( rhs._length > _length ) + { + free(_buffer); + getBuffer( rhs._length ); + } + + if ( _buffer != NULL ) { + _length = rhs._length; + strcpy( _buffer, rhs._buffer ); + } + return *this; +} + +//const String & String::operator+=( const char aChar ) +//{ +// if ( _length == _capacity ) +// doubleBuffer(); +// +// _buffer[ _length++ ] = aChar; +// _buffer[ _length ] = '\0'; +// return *this; +//} + +const String & String::operator+=( const String &other ) +{ + _length += other._length; + if ( _length > _capacity ) + { + char *temp = (char *)realloc(_buffer, _length + 1); + if ( temp != NULL ) { + _buffer = temp; + _capacity = _length; + } else { + _length -= other._length; + return *this; + } + } + strcat( _buffer, other._buffer ); + return *this; +} + + +int String::operator==( const String &rhs ) const +{ + return ( _length == rhs._length && strcmp( _buffer, rhs._buffer ) == 0 ); +} + +int String::operator!=( const String &rhs ) const +{ + return ( _length != rhs.length() || strcmp( _buffer, rhs._buffer ) != 0 ); +} + +int String::operator<( const String &rhs ) const +{ + return strcmp( _buffer, rhs._buffer ) < 0; +} + +int String::operator>( const String &rhs ) const +{ + return strcmp( _buffer, rhs._buffer ) > 0; +} + +int String::operator<=( const String &rhs ) const +{ + return strcmp( _buffer, rhs._buffer ) <= 0; +} + +int String::operator>=( const String & rhs ) const +{ + return strcmp( _buffer, rhs._buffer ) >= 0; +} + +char & String::operator[]( unsigned int index ) +{ + static char dummy_writable_char; + if (index >= _length || !_buffer) { + dummy_writable_char = 0; + return dummy_writable_char; + } + return _buffer[ index ]; +} + +char String::operator[]( unsigned int index ) const +{ + // need to check for valid index, to do later + return _buffer[ index ]; +} + +boolean String::endsWith( const String &s2 ) const +{ + if ( _length < s2._length ) + return 0; + + return strcmp( &_buffer[ _length - s2._length], s2._buffer ) == 0; +} + +boolean String::equals( const String &s2 ) const +{ + return ( _length == s2._length && strcmp( _buffer,s2._buffer ) == 0 ); +} + +boolean String::equalsIgnoreCase( const String &s2 ) const +{ + if ( this == &s2 ) + return true; //1; + else if ( _length != s2._length ) + return false; //0; + + return strcmp(toLowerCase()._buffer, s2.toLowerCase()._buffer) == 0; +} + +String String::replace( char findChar, char replaceChar ) +{ + if ( _buffer == NULL ) return *this; + String theReturn = _buffer; + char* temp = theReturn._buffer; + while( (temp = strchr( temp, findChar )) != 0 ) + *temp = replaceChar; + + return theReturn; +} + +String String::replace( const String& match, const String& replace ) +{ + if ( _buffer == NULL ) return *this; + String temp = _buffer, newString; + + int loc; + while ( (loc = temp.indexOf( match )) != -1 ) + { + newString += temp.substring( 0, loc ); + newString += replace; + temp = temp.substring( loc + match._length ); + } + newString += temp; + return newString; +} + +int String::indexOf( char temp ) const +{ + return indexOf( temp, 0 ); +} + +int String::indexOf( char ch, unsigned int fromIndex ) const +{ + if ( fromIndex >= _length ) + return -1; + + const char* temp = strchr( &_buffer[fromIndex], ch ); + if ( temp == NULL ) + return -1; + + return temp - _buffer; +} + +int String::indexOf( const String &s2 ) const +{ + return indexOf( s2, 0 ); +} + +int String::indexOf( const String &s2, unsigned int fromIndex ) const +{ + if ( fromIndex >= _length ) + return -1; + + const char *theFind = strstr( &_buffer[ fromIndex ], s2._buffer ); + + if ( theFind == NULL ) + return -1; + + return theFind - _buffer; // pointer subtraction +} + +int String::lastIndexOf( char theChar ) const +{ + return lastIndexOf( theChar, _length - 1 ); +} + +int String::lastIndexOf( char ch, unsigned int fromIndex ) const +{ + if ( fromIndex >= _length ) + return -1; + + char tempchar = _buffer[fromIndex + 1]; + _buffer[fromIndex + 1] = '\0'; + char* temp = strrchr( _buffer, ch ); + _buffer[fromIndex + 1] = tempchar; + + if ( temp == NULL ) + return -1; + + return temp - _buffer; +} + +int String::lastIndexOf( const String &s2 ) const +{ + return lastIndexOf( s2, _length - s2._length ); +} + +int String::lastIndexOf( const String &s2, unsigned int fromIndex ) const +{ + // check for empty strings + if ( s2._length == 0 || s2._length - 1 > fromIndex || fromIndex >= _length ) + return -1; + + // matching first character + char temp = s2[ 0 ]; + + for ( int i = fromIndex; i >= 0; i-- ) + { + if ( _buffer[ i ] == temp && (*this).substring( i, i + s2._length ).equals( s2 ) ) + return i; + } + return -1; +} + +boolean String::startsWith( const String &s2 ) const +{ + if ( _length < s2._length ) + return 0; + + return startsWith( s2, 0 ); +} + +boolean String::startsWith( const String &s2, unsigned int offset ) const +{ + if ( offset > _length - s2._length ) + return 0; + + return strncmp( &_buffer[offset], s2._buffer, s2._length ) == 0; +} + +String String::substring( unsigned int left ) const +{ + return substring( left, _length ); +} + +String String::substring( unsigned int left, unsigned int right ) const +{ + if ( left > right ) + { + int temp = right; + right = left; + left = temp; + } + + if ( right > _length ) + { + right = _length; + } + + char temp = _buffer[ right ]; // save the replaced character + _buffer[ right ] = '\0'; + String outPut = ( _buffer + left ); // pointer arithmetic + _buffer[ right ] = temp; //restore character + return outPut; +} + +String String::toLowerCase() const +{ + String temp = _buffer; + + for ( unsigned int i = 0; i < _length; i++ ) + temp._buffer[ i ] = (char)tolower( temp._buffer[ i ] ); + return temp; +} + +String String::toUpperCase() const +{ + String temp = _buffer; + + for ( unsigned int i = 0; i < _length; i++ ) + temp._buffer[ i ] = (char)toupper( temp._buffer[ i ] ); + return temp; +} + +String String::trim() const +{ + if ( _buffer == NULL ) return *this; + String temp = _buffer; + unsigned int i,j; + + for ( i = 0; i < _length; i++ ) + { + if ( !isspace(_buffer[i]) ) + break; + } + + for ( j = temp._length - 1; j > i; j-- ) + { + if ( !isspace(_buffer[j]) ) + break; + } + + return temp.substring( i, j + 1); +} + +void String::getBytes(unsigned char *buf, unsigned int bufsize) +{ + if (!bufsize || !buf) return; + unsigned int len = bufsize - 1; + if (len > _length) len = _length; + strncpy((char *)buf, _buffer, len); + buf[len] = 0; +} + +void String::toCharArray(char *buf, unsigned int bufsize) +{ + if (!bufsize || !buf) return; + unsigned int len = bufsize - 1; + if (len > _length) len = _length; + strncpy(buf, _buffer, len); + buf[len] = 0; +} + + +long String::toInt() { + return atol(_buffer); +} diff --git a/hardware/digistump/avr/cores/tiny/WString.h b/hardware/digistump/avr/cores/tiny/WString.h new file mode 100644 index 0000000..cadddb9 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/WString.h @@ -0,0 +1,112 @@ +/* + WString.h - String library for Wiring & Arduino + Copyright (c) 2009-10 Hernando Barragan. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef String_h +#define String_h + +//#include "WProgram.h" +#include +#include +#include + +class String +{ + public: + // constructors + String( const char *value = "" ); + String( const String &value ); + String( const char ); + String( const unsigned char ); + String( const int, const int base=10); + String( const unsigned int, const int base=10 ); + String( const long, const int base=10 ); + String( const unsigned long, const int base=10 ); + ~String() { free(_buffer); _length = _capacity = 0;} //added _length = _capacity = 0; + + // operators + const String & operator = ( const String &rhs ); + const String & operator +=( const String &rhs ); + //const String & operator +=( const char ); + int operator ==( const String &rhs ) const; + int operator !=( const String &rhs ) const; + int operator < ( const String &rhs ) const; + int operator > ( const String &rhs ) const; + int operator <=( const String &rhs ) const; + int operator >=( const String &rhs ) const; + char operator []( unsigned int index ) const; + char& operator []( unsigned int index ); + //operator const char *() const { return _buffer; } + + // general methods + char charAt( unsigned int index ) const; + int compareTo( const String &anotherString ) const; + unsigned char endsWith( const String &suffix ) const; + unsigned char equals( const String &anObject ) const; + unsigned char equalsIgnoreCase( const String &anotherString ) const; + int indexOf( char ch ) const; + int indexOf( char ch, unsigned int fromIndex ) const; + int indexOf( const String &str ) const; + int indexOf( const String &str, unsigned int fromIndex ) const; + int lastIndexOf( char ch ) const; + int lastIndexOf( char ch, unsigned int fromIndex ) const; + int lastIndexOf( const String &str ) const; + int lastIndexOf( const String &str, unsigned int fromIndex ) const; + const unsigned int length( ) const { return _length; } + void setCharAt(unsigned int index, const char ch); + unsigned char startsWith( const String &prefix ) const; + unsigned char startsWith( const String &prefix, unsigned int toffset ) const; + String substring( unsigned int beginIndex ) const; + String substring( unsigned int beginIndex, unsigned int endIndex ) const; + String toLowerCase( ) const; + String toUpperCase( ) const; + String trim( ) const; + void getBytes(unsigned char *buf, unsigned int bufsize); + void toCharArray(char *buf, unsigned int bufsize); + long toInt( ); + const String& concat( const String &str ); + String replace( char oldChar, char newChar ); + String replace( const String& match, const String& replace ); + friend String operator + ( String lhs, const String &rhs ); + + protected: + char *_buffer; // the actual char array + unsigned int _capacity; // the array length minus one (for the '\0') + unsigned int _length; // the String length (not counting the '\0') + + void getBuffer(unsigned int maxStrLen); + + private: + +}; + +// allocate buffer space +inline void String::getBuffer(unsigned int maxStrLen) +{ + _capacity = maxStrLen; + _buffer = (char *) malloc(_capacity + 1); + if (_buffer == NULL) _length = _capacity = 0; +} + +inline String operator+( String lhs, const String &rhs ) +{ + return lhs += rhs; +} + + +#endif diff --git a/hardware/digistump/avr/cores/tiny/binary.h b/hardware/digistump/avr/cores/tiny/binary.h new file mode 100644 index 0000000..af14980 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/binary.h @@ -0,0 +1,515 @@ +#ifndef Binary_h +#define Binary_h + +#define B0 0 +#define B00 0 +#define B000 0 +#define B0000 0 +#define B00000 0 +#define B000000 0 +#define B0000000 0 +#define B00000000 0 +#define B1 1 +#define B01 1 +#define B001 1 +#define B0001 1 +#define B00001 1 +#define B000001 1 +#define B0000001 1 +#define B00000001 1 +#define B10 2 +#define B010 2 +#define B0010 2 +#define B00010 2 +#define B000010 2 +#define B0000010 2 +#define B00000010 2 +#define B11 3 +#define B011 3 +#define B0011 3 +#define B00011 3 +#define B000011 3 +#define B0000011 3 +#define B00000011 3 +#define B100 4 +#define B0100 4 +#define B00100 4 +#define B000100 4 +#define B0000100 4 +#define B00000100 4 +#define B101 5 +#define B0101 5 +#define B00101 5 +#define B000101 5 +#define B0000101 5 +#define B00000101 5 +#define B110 6 +#define B0110 6 +#define B00110 6 +#define B000110 6 +#define B0000110 6 +#define B00000110 6 +#define B111 7 +#define B0111 7 +#define B00111 7 +#define B000111 7 +#define B0000111 7 +#define B00000111 7 +#define B1000 8 +#define B01000 8 +#define B001000 8 +#define B0001000 8 +#define B00001000 8 +#define B1001 9 +#define B01001 9 +#define B001001 9 +#define B0001001 9 +#define B00001001 9 +#define B1010 10 +#define B01010 10 +#define B001010 10 +#define B0001010 10 +#define B00001010 10 +#define B1011 11 +#define B01011 11 +#define B001011 11 +#define B0001011 11 +#define B00001011 11 +#define B1100 12 +#define B01100 12 +#define B001100 12 +#define B0001100 12 +#define B00001100 12 +#define B1101 13 +#define B01101 13 +#define B001101 13 +#define B0001101 13 +#define B00001101 13 +#define B1110 14 +#define B01110 14 +#define B001110 14 +#define B0001110 14 +#define B00001110 14 +#define B1111 15 +#define B01111 15 +#define B001111 15 +#define B0001111 15 +#define B00001111 15 +#define B10000 16 +#define B010000 16 +#define B0010000 16 +#define B00010000 16 +#define B10001 17 +#define B010001 17 +#define B0010001 17 +#define B00010001 17 +#define B10010 18 +#define B010010 18 +#define B0010010 18 +#define B00010010 18 +#define B10011 19 +#define B010011 19 +#define B0010011 19 +#define B00010011 19 +#define B10100 20 +#define B010100 20 +#define B0010100 20 +#define B00010100 20 +#define B10101 21 +#define B010101 21 +#define B0010101 21 +#define B00010101 21 +#define B10110 22 +#define B010110 22 +#define B0010110 22 +#define B00010110 22 +#define B10111 23 +#define B010111 23 +#define B0010111 23 +#define B00010111 23 +#define B11000 24 +#define B011000 24 +#define B0011000 24 +#define B00011000 24 +#define B11001 25 +#define B011001 25 +#define B0011001 25 +#define B00011001 25 +#define B11010 26 +#define B011010 26 +#define B0011010 26 +#define B00011010 26 +#define B11011 27 +#define B011011 27 +#define B0011011 27 +#define B00011011 27 +#define B11100 28 +#define B011100 28 +#define B0011100 28 +#define B00011100 28 +#define B11101 29 +#define B011101 29 +#define B0011101 29 +#define B00011101 29 +#define B11110 30 +#define B011110 30 +#define B0011110 30 +#define B00011110 30 +#define B11111 31 +#define B011111 31 +#define B0011111 31 +#define B00011111 31 +#define B100000 32 +#define B0100000 32 +#define B00100000 32 +#define B100001 33 +#define B0100001 33 +#define B00100001 33 +#define B100010 34 +#define B0100010 34 +#define B00100010 34 +#define B100011 35 +#define B0100011 35 +#define B00100011 35 +#define B100100 36 +#define B0100100 36 +#define B00100100 36 +#define B100101 37 +#define B0100101 37 +#define B00100101 37 +#define B100110 38 +#define B0100110 38 +#define B00100110 38 +#define B100111 39 +#define B0100111 39 +#define B00100111 39 +#define B101000 40 +#define B0101000 40 +#define B00101000 40 +#define B101001 41 +#define B0101001 41 +#define B00101001 41 +#define B101010 42 +#define B0101010 42 +#define B00101010 42 +#define B101011 43 +#define B0101011 43 +#define B00101011 43 +#define B101100 44 +#define B0101100 44 +#define B00101100 44 +#define B101101 45 +#define B0101101 45 +#define B00101101 45 +#define B101110 46 +#define B0101110 46 +#define B00101110 46 +#define B101111 47 +#define B0101111 47 +#define B00101111 47 +#define B110000 48 +#define B0110000 48 +#define B00110000 48 +#define B110001 49 +#define B0110001 49 +#define B00110001 49 +#define B110010 50 +#define B0110010 50 +#define B00110010 50 +#define B110011 51 +#define B0110011 51 +#define B00110011 51 +#define B110100 52 +#define B0110100 52 +#define B00110100 52 +#define B110101 53 +#define B0110101 53 +#define B00110101 53 +#define B110110 54 +#define B0110110 54 +#define B00110110 54 +#define B110111 55 +#define B0110111 55 +#define B00110111 55 +#define B111000 56 +#define B0111000 56 +#define B00111000 56 +#define B111001 57 +#define B0111001 57 +#define B00111001 57 +#define B111010 58 +#define B0111010 58 +#define B00111010 58 +#define B111011 59 +#define B0111011 59 +#define B00111011 59 +#define B111100 60 +#define B0111100 60 +#define B00111100 60 +#define B111101 61 +#define B0111101 61 +#define B00111101 61 +#define B111110 62 +#define B0111110 62 +#define B00111110 62 +#define B111111 63 +#define B0111111 63 +#define B00111111 63 +#define B1000000 64 +#define B01000000 64 +#define B1000001 65 +#define B01000001 65 +#define B1000010 66 +#define B01000010 66 +#define B1000011 67 +#define B01000011 67 +#define B1000100 68 +#define B01000100 68 +#define B1000101 69 +#define B01000101 69 +#define B1000110 70 +#define B01000110 70 +#define B1000111 71 +#define B01000111 71 +#define B1001000 72 +#define B01001000 72 +#define B1001001 73 +#define B01001001 73 +#define B1001010 74 +#define B01001010 74 +#define B1001011 75 +#define B01001011 75 +#define B1001100 76 +#define B01001100 76 +#define B1001101 77 +#define B01001101 77 +#define B1001110 78 +#define B01001110 78 +#define B1001111 79 +#define B01001111 79 +#define B1010000 80 +#define B01010000 80 +#define B1010001 81 +#define B01010001 81 +#define B1010010 82 +#define B01010010 82 +#define B1010011 83 +#define B01010011 83 +#define B1010100 84 +#define B01010100 84 +#define B1010101 85 +#define B01010101 85 +#define B1010110 86 +#define B01010110 86 +#define B1010111 87 +#define B01010111 87 +#define B1011000 88 +#define B01011000 88 +#define B1011001 89 +#define B01011001 89 +#define B1011010 90 +#define B01011010 90 +#define B1011011 91 +#define B01011011 91 +#define B1011100 92 +#define B01011100 92 +#define B1011101 93 +#define B01011101 93 +#define B1011110 94 +#define B01011110 94 +#define B1011111 95 +#define B01011111 95 +#define B1100000 96 +#define B01100000 96 +#define B1100001 97 +#define B01100001 97 +#define B1100010 98 +#define B01100010 98 +#define B1100011 99 +#define B01100011 99 +#define B1100100 100 +#define B01100100 100 +#define B1100101 101 +#define B01100101 101 +#define B1100110 102 +#define B01100110 102 +#define B1100111 103 +#define B01100111 103 +#define B1101000 104 +#define B01101000 104 +#define B1101001 105 +#define B01101001 105 +#define B1101010 106 +#define B01101010 106 +#define B1101011 107 +#define B01101011 107 +#define B1101100 108 +#define B01101100 108 +#define B1101101 109 +#define B01101101 109 +#define B1101110 110 +#define B01101110 110 +#define B1101111 111 +#define B01101111 111 +#define B1110000 112 +#define B01110000 112 +#define B1110001 113 +#define B01110001 113 +#define B1110010 114 +#define B01110010 114 +#define B1110011 115 +#define B01110011 115 +#define B1110100 116 +#define B01110100 116 +#define B1110101 117 +#define B01110101 117 +#define B1110110 118 +#define B01110110 118 +#define B1110111 119 +#define B01110111 119 +#define B1111000 120 +#define B01111000 120 +#define B1111001 121 +#define B01111001 121 +#define B1111010 122 +#define B01111010 122 +#define B1111011 123 +#define B01111011 123 +#define B1111100 124 +#define B01111100 124 +#define B1111101 125 +#define B01111101 125 +#define B1111110 126 +#define B01111110 126 +#define B1111111 127 +#define B01111111 127 +#define B10000000 128 +#define B10000001 129 +#define B10000010 130 +#define B10000011 131 +#define B10000100 132 +#define B10000101 133 +#define B10000110 134 +#define B10000111 135 +#define B10001000 136 +#define B10001001 137 +#define B10001010 138 +#define B10001011 139 +#define B10001100 140 +#define B10001101 141 +#define B10001110 142 +#define B10001111 143 +#define B10010000 144 +#define B10010001 145 +#define B10010010 146 +#define B10010011 147 +#define B10010100 148 +#define B10010101 149 +#define B10010110 150 +#define B10010111 151 +#define B10011000 152 +#define B10011001 153 +#define B10011010 154 +#define B10011011 155 +#define B10011100 156 +#define B10011101 157 +#define B10011110 158 +#define B10011111 159 +#define B10100000 160 +#define B10100001 161 +#define B10100010 162 +#define B10100011 163 +#define B10100100 164 +#define B10100101 165 +#define B10100110 166 +#define B10100111 167 +#define B10101000 168 +#define B10101001 169 +#define B10101010 170 +#define B10101011 171 +#define B10101100 172 +#define B10101101 173 +#define B10101110 174 +#define B10101111 175 +#define B10110000 176 +#define B10110001 177 +#define B10110010 178 +#define B10110011 179 +#define B10110100 180 +#define B10110101 181 +#define B10110110 182 +#define B10110111 183 +#define B10111000 184 +#define B10111001 185 +#define B10111010 186 +#define B10111011 187 +#define B10111100 188 +#define B10111101 189 +#define B10111110 190 +#define B10111111 191 +#define B11000000 192 +#define B11000001 193 +#define B11000010 194 +#define B11000011 195 +#define B11000100 196 +#define B11000101 197 +#define B11000110 198 +#define B11000111 199 +#define B11001000 200 +#define B11001001 201 +#define B11001010 202 +#define B11001011 203 +#define B11001100 204 +#define B11001101 205 +#define B11001110 206 +#define B11001111 207 +#define B11010000 208 +#define B11010001 209 +#define B11010010 210 +#define B11010011 211 +#define B11010100 212 +#define B11010101 213 +#define B11010110 214 +#define B11010111 215 +#define B11011000 216 +#define B11011001 217 +#define B11011010 218 +#define B11011011 219 +#define B11011100 220 +#define B11011101 221 +#define B11011110 222 +#define B11011111 223 +#define B11100000 224 +#define B11100001 225 +#define B11100010 226 +#define B11100011 227 +#define B11100100 228 +#define B11100101 229 +#define B11100110 230 +#define B11100111 231 +#define B11101000 232 +#define B11101001 233 +#define B11101010 234 +#define B11101011 235 +#define B11101100 236 +#define B11101101 237 +#define B11101110 238 +#define B11101111 239 +#define B11110000 240 +#define B11110001 241 +#define B11110010 242 +#define B11110011 243 +#define B11110100 244 +#define B11110101 245 +#define B11110110 246 +#define B11110111 247 +#define B11111000 248 +#define B11111001 249 +#define B11111010 250 +#define B11111011 251 +#define B11111100 252 +#define B11111101 253 +#define B11111110 254 +#define B11111111 255 + +#endif diff --git a/hardware/digistump/avr/cores/tiny/core_adc.h b/hardware/digistump/avr/cores/tiny/core_adc.h new file mode 100644 index 0000000..5b4e1be --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/core_adc.h @@ -0,0 +1,320 @@ +/*============================================================================== + + core_adc.h - Veneer for the analog-to-digital converter. + + Copyright 2010 Rowdy Dog Software. + + This file is part of Arduino-Tiny. + + Arduino-Tiny is free software: you can redistribute it and/or modify it + under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation, either version 3 of the License, or (at your + option) any later version. + + Arduino-Tiny is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with Arduino-Tiny. If not, see . + +==============================================================================*/ + +#ifndef core_adc_h +#define core_adc_h + +#include +#include + +#include "core_build_options.h" +#include "core_macros.h" + + +/*============================================================================= + Some common things +=============================================================================*/ + +#if defined( __AVR_ATtinyX4__ ) || defined( __AVR_ATtinyX5__ ) + +/* + From the '84 and '85 datasheets... By default, the successive approximation + circuitry requires an input clock frequency between 50 kHz and 200 kHz to + get maximum resolution. +*/ +#if F_CPU == 16000000 + // 16 MHz / 128 = 125 KHz + #define ADC_ARDUINO_PRESCALER ADC_Prescaler_Value_128 +#elif F_CPU == 16500000 + // 8 MHz / 64 = 125 KHz + #define ADC_ARDUINO_PRESCALER ADC_Prescaler_Value_128 +#elif F_CPU == 8000000 + // 8 MHz / 64 = 125 KHz + #define ADC_ARDUINO_PRESCALER ADC_Prescaler_Value_64 +#elif F_CPU == 1000000 + // 1 MHz / 8 = 125 KHz + #define ADC_ARDUINO_PRESCALER ADC_Prescaler_Value_8 +#else + #error Add an entry for the selected processor speed. +#endif + +typedef enum +{ + ADC_Prescaler_Value_2 = B001, + ADC_Prescaler_Value_4 = B010, + ADC_Prescaler_Value_8 = B011, + ADC_Prescaler_Value_16 = B100, + ADC_Prescaler_Value_32 = B101, + ADC_Prescaler_Value_64 = B110, + ADC_Prescaler_Value_128 = B111, + ADC_Prescaler_Index_1 = B001, + ADC_Prescaler_Index_2 = B010, + ADC_Prescaler_Index_3 = B011, + ADC_Prescaler_Index_4 = B100, + ADC_Prescaler_Index_5 = B101, + ADC_Prescaler_Index_6 = B110, + ADC_Prescaler_Index_7 = B111 +} +adc_ps_t; + +__attribute__((always_inline)) static inline void ADC_PrescalerSelect( adc_ps_t ps ) +{ + ADCSRA = (ADCSRA & ~MASK3(ADPS2,ADPS1,ADPS0)) | (ps << ADPS0); +} + +__attribute__((always_inline)) static inline void ADC_Enable( void ) +{ + ADCSRA |= MASK1( ADEN ); +} + +#endif + + +/*============================================================================= + Veneer for the ATtiny84 ADC +=============================================================================*/ + +#if defined( __AVR_ATtinyX4__ ) + +typedef enum +{ + ADC_Reference_VCC = B00, + ADC_Reference_External = B01, + ADC_Reference_Internal_1p1 = B10, + ADC_Reference_Reserved_1 = B11 +} +adc_vr_t; + +__attribute__((always_inline)) static inline void ADC_SetVoltageReference( adc_vr_t vr ) +{ + ADMUX = (ADMUX & ~MASK2(REFS1,REFS0)) | (((vr & B11) >> 0) << REFS0); +} + +typedef enum +{ + ADC_Input_ADC0 = B000000, + ADC_Input_ADC1 = B000001, + ADC_Input_ADC2 = B000010, + ADC_Input_ADC3 = B000011, + ADC_Input_ADC4 = B000100, + ADC_Input_ADC5 = B000101, + ADC_Input_ADC6 = B000110, + ADC_Input_ADC7 = B000111, + + ADC_Input_GND = B100000, // 0V (AGND) + ADC_Input_1p1 = B100001, // 1.1V (I Ref) + ADC_Input_ADC8 = B100010, // For temperature sensor. + + ADC_Input_Pos0_Neg0_20x = B100011, // For offset calibration, only. + ADC_Input_Pos0_Neg1_1x = B001000, + ADC_Input_Pos0_Neg1_20x = B001001, + ADC_Input_Pos0_Neg3_1x = B001010, + ADC_Input_Pos0_Neg3_20x = B001011, + ADC_Input_Pos1_Neg0_1x = B101000, + ADC_Input_Pos1_Neg0_20x = B101001, + ADC_Input_Pos1_Neg2_1x = B001100, + ADC_Input_Pos1_Neg2_20x = B001101, + ADC_Input_Pos1_Neg3_1x = B001110, + ADC_Input_Pos1_Neg3_20x = B001111, + ADC_Input_Pos2_Neg1_1x = B101100, + ADC_Input_Pos2_Neg1_20x = B101101, + ADC_Input_Pos2_Neg3_1x = B010000, + ADC_Input_Pos2_Neg3_20x = B010001, + ADC_Input_Pos3_Neg0_1x = B101010, + ADC_Input_Pos3_Neg0_20x = B101011, + ADC_Input_Pos3_Neg1_1x = B101110, + ADC_Input_Pos3_Neg1_20x = B101111, + ADC_Input_Pos3_Neg2_1x = B110000, + ADC_Input_Pos3_Neg2_20x = B110001, + ADC_Input_Pos3_Neg3_1x = B100100, // For offset calibration, only. + ADC_Input_Pos3_Neg3_20x = B100101, // For offset calibration, only. + ADC_Input_Pos3_Neg4_1x = B010010, + ADC_Input_Pos3_Neg4_20x = B010011, + ADC_Input_Pos3_Neg5_1x = B010100, + ADC_Input_Pos3_Neg5_20x = B010101, + ADC_Input_Pos3_Neg6_1x = B010110, + ADC_Input_Pos3_Neg6_20x = B010111, + ADC_Input_Pos3_Neg7_1x = B011000, + ADC_Input_Pos3_Neg7_20x = B011001, + ADC_Input_Pos4_Neg3_1x = B110010, + ADC_Input_Pos4_Neg3_20x = B110011, + ADC_Input_Pos4_Neg5_1x = B011010, + ADC_Input_Pos4_Neg5_20x = B011011, + ADC_Input_Pos5_Neg3_1x = B110100, + ADC_Input_Pos5_Neg3_20x = B110101, + ADC_Input_Pos5_Neg4_1x = B111010, + ADC_Input_Pos5_Neg4_20x = B111011, + ADC_Input_Pos5_Neg6_1x = B011100, + ADC_Input_Pos5_Neg6_20x = B011101, + ADC_Input_Pos6_Neg3_1x = B110110, + ADC_Input_Pos6_Neg3_20x = B110111, + ADC_Input_Pos6_Neg5_1x = B111100, + ADC_Input_Pos6_Neg5_20x = B111101, + ADC_Input_Pos6_Neg7_1x = B011110, + ADC_Input_Pos6_Neg7_20x = B011111, + ADC_Input_Pos7_Neg3_1x = B111000, + ADC_Input_Pos7_Neg3_20x = B111001, + ADC_Input_Pos7_Neg6_1x = B111110, + ADC_Input_Pos7_Neg6_20x = B111111, + ADC_Input_Pos7_Neg7_1x = B100110, // For offset calibration, only. + ADC_Input_Pos7_Neg7_20x = B100111 // For offset calibration, only. +} +adc_ic_t; + +__attribute__((always_inline)) static inline void ADC_SetInputChannel( adc_ic_t ic ) +{ + ADMUX = (ADMUX & ~MASK6(MUX5,MUX4,MUX3,MUX2,MUX1,MUX0)) | (ic << MUX0); +} + +__attribute__((always_inline)) static inline void ADC_StartConversion( void ) +{ + ADCSRA |= MASK1( ADSC ); +} + +__attribute__((always_inline)) static inline uint8_t ADC_ConversionInProgress( void ) +{ + return( (ADCSRA & (1<> 0) << REFS0) + | (((vr & B100) >> 2) << REFS2); +} + +typedef enum +{ + ADC_Input_ADC0 = B0000, + ADC_Input_ADC1 = B0001, + ADC_Input_ADC2 = B0010, + ADC_Input_ADC3 = B0011, + + ADC_Input_Pos2_Neg2_1x = B0100, // For offset calibration, only. + ADC_Input_Pos2_Neg2_20x = B0101, // For offset calibration, only. + ADC_Input_Pos2_Neg3_1x = B0110, + ADC_Input_Pos2_Neg3_20x = B0111, + ADC_Input_Pos0_Neg0_1x = B1000, + ADC_Input_Pos0_Neg0_20x = B1001, + ADC_Input_Pos0_Neg1_1x = B1010, + ADC_Input_Pos0_Neg1_20x = B1011, + + ADC_Input_VBG = B1100, + ADC_Input_GND = B1101, + ADC_Input_NA = B1110, + ADC_Input_ADC4 = B1111 // For temperature sensor. +} +adc_ic_t; + +__attribute__((always_inline)) static inline void ADC_SetInputChannel( adc_ic_t ic ) +{ + ADMUX = (ADMUX & ~MASK4(MUX3,MUX2,MUX1,MUX0)) | (ic << MUX0); +} + +__attribute__((always_inline)) static inline void ADC_StartConversion( void ) +{ + ADCSRA |= MASK1( ADSC ); +} + +__attribute__((always_inline)) static inline uint8_t ADC_ConversionInProgress( void ) +{ + return( (ADCSRA & (1<. + +==============================================================================*/ + +#ifndef core_build_options_h +#define core_build_options_h + + +/*============================================================================= + Low power / smaller code options +=============================================================================*/ + +#define INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER 1 +#define INITIALIZE_SECONDARY_TIMERS 1 + + +/*============================================================================= + Build options for the ATtinyX313 processor +=============================================================================*/ + +#if defined( __AVR_ATtiny2313__ ) || defined( __AVR_ATtiny4313__ ) +#define __AVR_ATtinyX313__ +#endif + +#if defined( __AVR_ATtinyX313__ ) + +/* + The old standby ... millis on Timer 0. +*/ +#define TIMER_TO_USE_FOR_MILLIS 0 + +/* + Tone goes on whichever timer was not used for millis. +*/ +#if TIMER_TO_USE_FOR_MILLIS == 1 +#define TIMER_TO_USE_FOR_TONE 0 +#else +#define TIMER_TO_USE_FOR_TONE 1 +#endif + +#define HAVE_ADC 0 + +#define DEFAULT_TO_TINY_DEBUG_SERIAL 0 + +#endif + + +/*============================================================================= + Build options for the ATtiny84 processor +=============================================================================*/ + +#if defined( __AVR_ATtiny24__ ) || defined( __AVR_ATtiny44__ ) || defined( __AVR_ATtiny84__ ) +#define __AVR_ATtinyX4__ +#endif + +#if defined( __AVR_ATtinyX4__ ) + +/* + The old standby ... millis on Timer 0. +*/ +#define TIMER_TO_USE_FOR_MILLIS 0 + +/* + Tone goes on whichever timer was not used for millis. +*/ +#if TIMER_TO_USE_FOR_MILLIS == 1 +#define TIMER_TO_USE_FOR_TONE 0 +#else +#define TIMER_TO_USE_FOR_TONE 1 +#endif + +#define HAVE_ADC 1 + +#define DEFAULT_TO_TINY_DEBUG_SERIAL 1 + +#endif + + +/*============================================================================= + Build options for the ATtiny85 processor +=============================================================================*/ + +#if defined( __AVR_ATtiny25__ ) || defined( __AVR_ATtiny45__ ) || defined( __AVR_ATtiny85__ ) +#define __AVR_ATtinyX5__ +#endif + +#if defined( __AVR_ATtinyX5__ ) + +/* + For various reasons, Timer 1 is a better choice for the millis timer on the + '85 processor. +*/ +#define TIMER_TO_USE_FOR_MILLIS 1 + +/* + If the following is true (non-zero) there will be two phase-correct PWM + pins and one fast PWM pin. If false there will be one phase-correct PWM + pin and two fast PWM pins. +*/ +#define FAVOR_PHASE_CORRECT_PWM 1 + +/* + Tone goes on whichever timer was not used for millis. +*/ +#if TIMER_TO_USE_FOR_MILLIS == 1 +#define TIMER_TO_USE_FOR_TONE 0 +#else +#define TIMER_TO_USE_FOR_TONE 1 +#endif + +#define HAVE_ADC 1 + +#define DEFAULT_TO_TINY_DEBUG_SERIAL 1 + +#endif + + +/*============================================================================= + There doesn't seem to be many people using a bootloader so we'll assume + there isn't one. If the following is true (non-zero), the timers are + reinitialized to their power-up state in init just in case the bootloader + left them in a bad way. +=============================================================================*/ + +#define HAVE_BOOTLOADER 0 + + +/*============================================================================= + Allow the ADC to be optional for low-power applications +=============================================================================*/ + +#if ! defined( HAVE_ADC ) + #define HAVE_ADC 0 +#endif + +#if ! HAVE_ADC + #undef INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER + #define INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER 0 +#else + #if ! defined( INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER ) + #define INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER 1 + #endif +#endif + + +/*============================================================================= + Allow the "secondary timers" to be optional for low-power applications +=============================================================================*/ + +#if ! defined( INITIALIZE_SECONDARY_TIMERS ) + #define INITIALIZE_SECONDARY_TIMERS 1 +#endif + + +#endif diff --git a/hardware/digistump/avr/cores/tiny/core_macros.h b/hardware/digistump/avr/cores/tiny/core_macros.h new file mode 100644 index 0000000..715e479 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/core_macros.h @@ -0,0 +1,42 @@ +/*============================================================================== + + core_macros.h - Simple but handy macros. + + Copyright 2010 Rowdy Dog Software. + + This file is part of Arduino-Tiny. + + Arduino-Tiny is free software: you can redistribute it and/or modify it + under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation, either version 3 of the License, or (at your + option) any later version. + + Arduino-Tiny is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with Arduino-Tiny. If not, see . + +==============================================================================*/ + +#ifndef core_macros_h +#define core_macros_h + + +/*============================================================================= + Bitmask macros +=============================================================================*/ + +#define MASK1(b1) ( (1<. + +==============================================================================*/ + +#ifndef core_pins_h +#define core_pins_h + +#include "core_build_options.h" + + +/*============================================================================= + Pin definitions for the ATtinyX313 +=============================================================================*/ + +#if defined( __AVR_ATtinyX313__ ) + +#define PIN_D0 ( 0) +#define PIN_D1 ( 1) +#define PIN_A1 ( 2) +#define PIN_A0 ( 3) +#define PIN_D2 ( 4) +#define PIN_D3 ( 5) +#define PIN_D4 ( 6) +#define PIN_D5 ( 7) +#define PIN_D6 ( 8) +#define PIN_B0 ( 9) +#define PIN_B1 (10) +#define PIN_B2 (11) +#define PIN_B3 (12) +#define PIN_B4 (13) +#define PIN_B5 (14) +#define PIN_B6 (15) +#define PIN_B7 (16) +#define PIN_A2 (17) /* RESET */ + +#define CORE_DIGITAL_FIRST (0) +#define CORE_DIGITAL_LAST (17) +#define CORE_DIGITAL_COUNT (CORE_DIGITAL_LAST-CORE_DIGITAL_FIRST+1) +#define CORE_RESET_INCLUDED (1) + +#define CORE_ANALOG_COUNT (0) + +#define CORE_INT0_PIN PIN_D2 +#define CORE_INT1_PIN PIN_D3 + +#define CORE_OC0A_PIN PIN_B2 +#define CORE_OC0B_PIN PIN_D5 +#define CORE_OC1A_PIN PIN_B3 +#define CORE_OC1B_PIN PIN_B4 + +#define CORE_PWM0_PIN CORE_OC0A_PIN +#define CORE_PWM0_TIMER 0 +#define CORE_PWM0_CHANNEL A + +#define CORE_PWM1_PIN CORE_OC0B_PIN +#define CORE_PWM1_TIMER 0 +#define CORE_PWM1_CHANNEL B + +#define CORE_PWM2_PIN CORE_OC1A_PIN +#define CORE_PWM2_TIMER 1 +#define CORE_PWM2_CHANNEL A + +#define CORE_PWM3_PIN CORE_OC1B_PIN +#define CORE_PWM3_TIMER 1 +#define CORE_PWM3_CHANNEL B + +#define CORE_PWM_COUNT (4) + +#endif + + +/*============================================================================= + Pin definitions for the ATtiny84 +=============================================================================*/ + +#if defined( __AVR_ATtinyX4__ ) + +#define PIN_A0 (10) +#define PIN_A1 ( 9) +#define PIN_A2 ( 8) +#define PIN_A3 ( 7) +#define PIN_A4 ( 6) +#define PIN_A5 ( 5) +#define PIN_A6 ( 4) +#define PIN_A7 ( 3) +#define PIN_B0 ( 0) +#define PIN_B1 ( 1) +#define PIN_B2 ( 2) +#define PIN_B3 (11) /* RESET */ + +#define CORE_DIGITAL_FIRST (0) +#define CORE_DIGITAL_LAST (11) +#define CORE_DIGITAL_COUNT (CORE_DIGITAL_LAST-CORE_DIGITAL_FIRST+1) +#define CORE_RESET_INCLUDED (1) + +#define CORE_ANALOG_FIRST (CORE_DIGITAL_LAST+1) +#define CORE_ANALOG_COUNT (8) +#define CORE_ANALOG_LAST (CORE_ANALOG_FIRST+CORE_ANALOG_COUNT-1) + +#define CORE_INT0_PIN PIN_B2 + +#define CORE_OC0A_PIN PIN_B2 +#define CORE_OC0B_PIN PIN_A7 +#define CORE_OC1A_PIN PIN_A6 +#define CORE_OC1B_PIN PIN_A5 + +#define CORE_PWM0_PIN CORE_OC0A_PIN +#define CORE_PWM0_TIMER 0 +#define CORE_PWM0_CHANNEL A + +#define CORE_PWM1_PIN CORE_OC0B_PIN +#define CORE_PWM1_TIMER 0 +#define CORE_PWM1_CHANNEL B + +#define CORE_PWM2_PIN CORE_OC1A_PIN +#define CORE_PWM2_TIMER 1 +#define CORE_PWM2_CHANNEL A + +#define CORE_PWM3_PIN CORE_OC1B_PIN +#define CORE_PWM3_TIMER 1 +#define CORE_PWM3_CHANNEL B + +#define CORE_PWM_COUNT (4) + +#endif + + +/*============================================================================= + Pin definitions for the ATtiny85 +=============================================================================*/ + +#if defined( __AVR_ATtinyX5__ ) + +#define PIN_B0 ( 0) +#define PIN_B1 ( 1) +#define PIN_B2 ( 2) +#define PIN_B3 ( 3) +#define PIN_B4 ( 4) +#define PIN_B5 ( 5) /* RESET */ + +#define CORE_DIGITAL_FIRST (0) +#define CORE_DIGITAL_LAST (5) +#define CORE_DIGITAL_COUNT (CORE_DIGITAL_LAST-CORE_DIGITAL_FIRST+1) +#define CORE_RESET_INCLUDED (1) + +#define CORE_ANALOG_FIRST (CORE_DIGITAL_LAST+1) +#define CORE_ANALOG_COUNT (4) +#define CORE_ANALOG_LAST (CORE_ANALOG_FIRST+CORE_ANALOG_COUNT-1) + +#define CORE_INT0_PIN PIN_B2 + +#define CORE_OC0A_PIN PIN_B0 +#define CORE_OC0B_PIN PIN_B1 +#define CORE_OC1A_PIN PIN_B1 +#define CORE_OC1B_PIN PIN_B4 + +/* Note: By default, CORE_OC1A_PIN is not used for PWM. It overlaps with +CORE_OC0B_PIN. CORE_OC0B_PIN was used because it supports phase-correct PWM. +There is a build option in "core_build_options.h" to determine which channel +to use */ + +#define CORE_PWM0_PIN CORE_OC0A_PIN +#define CORE_PWM0_TIMER 0 +#define CORE_PWM0_CHANNEL A + +#if FAVOR_PHASE_CORRECT_PWM +#define CORE_PWM1_PIN CORE_OC0B_PIN +#define CORE_PWM1_TIMER 0 +#define CORE_PWM1_CHANNEL B +#else +#define CORE_PWM1_PIN CORE_OC1A_PIN +#define CORE_PWM1_TIMER 1 +#define CORE_PWM1_CHANNEL A +#endif + +#define CORE_PWM2_PIN CORE_OC1B_PIN +#define CORE_PWM2_TIMER 1 +#define CORE_PWM2_CHANNEL B + +#define CORE_PWM_COUNT (3) + +#endif + + +#endif diff --git a/hardware/digistump/avr/cores/tiny/core_timers.h b/hardware/digistump/avr/cores/tiny/core_timers.h new file mode 100644 index 0000000..64f0b0b --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/core_timers.h @@ -0,0 +1,1075 @@ +/*============================================================================== + + core_timers.h - Veneer for the timers. + + Copyright 2010 Rowdy Dog Software. + + This file is part of Arduino-Tiny. + + Arduino-Tiny is free software: you can redistribute it and/or modify it + under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation, either version 3 of the License, or (at your + option) any later version. + + Arduino-Tiny is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public + License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with Arduino-Tiny. If not, see . + +==============================================================================*/ + +#ifndef core_timers_h +#define core_timers_h + +#include +#include + +#include "core_pins.h" +#include "core_build_options.h" +#include "core_macros.h" + + +/*============================================================================= + Macros for generating application specific names for the stuff here (like + Millis_SetToPowerup as an alias for Timer1_SetToPowerup). +=============================================================================*/ + +#define TIMER_PASTE_A(lft,t,rgt) TIMER_PASTE_B(lft,t,rgt) +#define TIMER_PASTE_B(lft,t,rgt) lft##t##_##rgt + +#define TIMER_PASTE_CHANNEL_A(lft,t,rgt,ch) TIMER_PASTE_CHANNEL_B(lft,t,rgt,ch) +#define TIMER_PASTE_CHANNEL_B(lft,t,rgt,ch) lft##t##_##rgt##ch + + +/*============================================================================= + Notes... + + - The 2313, X4, and X5 Timer0 code only differs by TIMSK0 / TIMSK and TIFR0 + / TIFR. It's time to make the Timer0 code reusable. + + - The 2313 and X4 Timer1 code is source code compatible (interchangeable). + It's time to make the Timer1 code reusable. + +=============================================================================*/ + +/*============================================================================= + Veneer for the two ATtinyX313 timers +=============================================================================*/ + +#if defined( __AVR_ATtinyX313__ ) + +#define Timer0_OutputComparePinA CORE_OC0A_PIN +#define Timer0_OutputComparePinB CORE_OC0B_PIN + +#define TIMER0_SUPPORTS_PHASE_CORRECT_PWM (1) + +__attribute__((always_inline)) static inline void Timer0_SetToPowerup( void ) +{ + // Stop the clock, set waveform generation to normal, and set output mode to normal + TCCR0B = (0<> 0) << WGM00); + TCCR0B = (TCCR0B & ~MASK1(WGM02)) | (((wgm & B100) >> 2) << WGM02); +} + +typedef enum +{ + Timer0_Disconnected = 0, + Timer0_Toggle = B01, + Timer0_Clear = B10, + Timer0_Set = B11 +} +timer0_com_t; + +__attribute__((always_inline)) static inline void Timer0_SetCompareOutputModeA( timer0_com_t com ) +{ + TCCR0A = (TCCR0A & ~MASK2(COM0A1,COM0A0)) | (com << COM0A0); +} + +__attribute__((always_inline)) static inline void Timer0_SetCompareOutputModeB( timer0_com_t com ) +{ + TCCR0A = (TCCR0A & ~MASK2(COM0B1,COM0B0)) | (com << COM0B0); +} + +__attribute__((always_inline)) static inline void Timer0_DisconnectOutputs( void ) +{ + TCCR0A &= ~MASK4(COM0A1,COM0A0,COM0B1,COM0B0); +} + +#define TIMER0_MAXIMUM_OCR (255) +#define TIMER0_PRESCALE_SET (1) + +typedef uint8_t timer0_ocr_t; +typedef uint8_t timer0_tcnt_t; + +__attribute__((always_inline)) static inline void Timer0_SetOutputCompareMatchAndClear( timer0_ocr_t oc ) +{ + OCR0A = oc; +} + +__attribute__((always_inline)) static inline void Timer0_SetOutputCompareMatchA( timer0_ocr_t oc ) +{ + OCR0A = oc; +} + +__attribute__((always_inline)) static inline void Timer0_SetOutputCompareMatchB( timer0_ocr_t oc ) +{ + OCR0B = oc; +} + +__attribute__((always_inline)) static inline void Timer0_EnableOutputCompareInterruptA( void ) +{ + TIMSK |= (1<> 0) << WGM10); + TCCR1B = (TCCR1B & ~MASK2(WGM13,WGM12)) | (((wgm & B1100) >> 2) << WGM12); +} + +typedef enum +{ + Timer1_Disconnected = 0, + Timer1_Toggle = B01, + Timer1_Clear = B10, + Timer1_Set = B11 +} +timer1_com_t; + +__attribute__((always_inline)) static inline void Timer1_SetCompareOutputModeA( timer1_com_t com ) +{ + TCCR1A = (TCCR1A & ~MASK2(COM1A1,COM1A0)) | (com << COM1A0); +} + +__attribute__((always_inline)) static inline void Timer1_SetCompareOutputModeB( timer1_com_t com ) +{ + TCCR1A = (TCCR1A & ~MASK2(COM1B1,COM1B0)) | (com << COM1B0); +} + +__attribute__((always_inline)) static inline void Timer1_DisconnectOutputs( void ) +{ + TCCR1A &= ~MASK4(COM1A1,COM1A0,COM1B1,COM1B0); +} + +#define TIMER1_MAXIMUM_OCR (65535) +#define TIMER1_PRESCALE_SET (1) + +typedef uint16_t timer1_ocr_t; +typedef uint16_t timer1_tcnt_t; + +__attribute__((always_inline)) static inline void Timer1_SetOutputCompareMatchAndClear( timer1_ocr_t oc ) +{ + OCR1A = oc; +} + +__attribute__((always_inline)) static inline void Timer1_SetOutputCompareMatchA( timer1_ocr_t oc ) +{ + OCR1A = oc; +} + +__attribute__((always_inline)) static inline void Timer1_SetOutputCompareMatchB( timer1_ocr_t oc ) +{ + OCR1B = oc; +} + +__attribute__((always_inline)) static inline void Timer1_EnableOutputCompareInterruptA( void ) +{ + TIMSK |= (1<> 0) << WGM00); + TCCR0B = (TCCR0B & ~MASK1(WGM02)) | (((wgm & B100) >> 2) << WGM02); +} + +typedef enum +{ + Timer0_Disconnected = 0, + Timer0_Toggle = B01, + Timer0_Clear = B10, + Timer0_Set = B11 +} +timer0_com_t; + +__attribute__((always_inline)) static inline void Timer0_SetCompareOutputModeA( timer0_com_t com ) +{ + TCCR0A = (TCCR0A & ~MASK2(COM0A1,COM0A0)) | (com << COM0A0); +} + +__attribute__((always_inline)) static inline void Timer0_SetCompareOutputModeB( timer0_com_t com ) +{ + TCCR0A = (TCCR0A & ~MASK2(COM0B1,COM0B0)) | (com << COM0B0); +} + +__attribute__((always_inline)) static inline void Timer0_DisconnectOutputs( void ) +{ + TCCR0A &= ~MASK4(COM0A1,COM0A0,COM0B1,COM0B0); +} + +#define TIMER0_MAXIMUM_OCR (255) +#define TIMER0_PRESCALE_SET (1) + +typedef uint8_t timer0_ocr_t; +typedef uint8_t timer0_tcnt_t; + +__attribute__((always_inline)) static inline void Timer0_SetOutputCompareMatchAndClear( timer0_ocr_t oc ) +{ + OCR0A = oc; +} + +__attribute__((always_inline)) static inline void Timer0_SetOutputCompareMatchA( timer0_ocr_t oc ) +{ + OCR0A = oc; +} + +__attribute__((always_inline)) static inline void Timer0_SetOutputCompareMatchB( timer0_ocr_t oc ) +{ + OCR0B = oc; +} + +__attribute__((always_inline)) static inline void Timer0_EnableOutputCompareInterruptA( void ) +{ + TIMSK0 |= (1<> 0) << WGM10); + TCCR1B = (TCCR1B & ~MASK2(WGM13,WGM12)) | (((wgm & B1100) >> 2) << WGM12); +} + +typedef enum +{ + Timer1_Disconnected = 0, + Timer1_Toggle = B01, + Timer1_Clear = B10, + Timer1_Set = B11 +} +timer1_com_t; + +__attribute__((always_inline)) static inline void Timer1_SetCompareOutputModeA( timer1_com_t com ) +{ + TCCR1A = (TCCR1A & ~MASK2(COM1A1,COM1A0)) | (com << COM1A0); +} + +__attribute__((always_inline)) static inline void Timer1_SetCompareOutputModeB( timer1_com_t com ) +{ + TCCR1A = (TCCR1A & ~MASK2(COM1B1,COM1B0)) | (com << COM1B0); +} + +__attribute__((always_inline)) static inline void Timer1_DisconnectOutputs( void ) +{ + TCCR1A &= ~MASK4(COM1A1,COM1A0,COM1B1,COM1B0); +} + +#define TIMER1_MAXIMUM_OCR (65535) +#define TIMER1_PRESCALE_SET (1) + +typedef uint16_t timer1_ocr_t; +typedef uint16_t timer1_tcnt_t; + +__attribute__((always_inline)) static inline void Timer1_SetOutputCompareMatchAndClear( timer1_ocr_t oc ) +{ + OCR1A = oc; +} + +__attribute__((always_inline)) static inline void Timer1_SetOutputCompareMatchA( timer1_ocr_t oc ) +{ + OCR1A = oc; +} + +__attribute__((always_inline)) static inline void Timer1_SetOutputCompareMatchB( timer1_ocr_t oc ) +{ + OCR1B = oc; +} + +__attribute__((always_inline)) static inline void Timer1_EnableOutputCompareInterruptA( void ) +{ + TIMSK1 |= (1<> 0) << WGM00); + TCCR0B = (TCCR0B & ~MASK1(WGM02)) | (((wgm & B100) >> 2) << WGM02); +} + +typedef enum +{ + Timer0_Disconnected = 0, + Timer0_Toggle = B01, + Timer0_Clear = B10, + Timer0_Set = B11 +} +timer0_com_t; + +__attribute__((always_inline)) static inline void Timer0_SetCompareOutputModeA( timer0_com_t com ) +{ + TCCR0A = (TCCR0A & ~MASK2(COM0A1,COM0A0)) | (com << COM0A0); +} + +__attribute__((always_inline)) static inline void Timer0_SetCompareOutputModeB( timer0_com_t com ) +{ + TCCR0A = (TCCR0A & ~MASK2(COM0B1,COM0B0)) | (com << COM0B0); +} + +__attribute__((always_inline)) static inline void Timer0_DisconnectOutputs( void ) +{ + TCCR0A &= ~MASK4(COM0A1,COM0A0,COM0B1,COM0B0); +} + +#define TIMER0_MAXIMUM_OCR (255) +#define TIMER0_PRESCALE_SET (1) + +typedef uint8_t timer0_ocr_t; +typedef uint8_t timer0_tcnt_t; + +__attribute__((always_inline)) static inline void Timer0_SetOutputCompareMatchAndClear( timer0_ocr_t oc ) +{ + OCR0A = oc; +} + +__attribute__((always_inline)) static inline void Timer0_SetOutputCompareMatchA( timer0_ocr_t oc ) +{ + OCR0A = oc; +} + +__attribute__((always_inline)) static inline void Timer0_SetOutputCompareMatchB( timer0_ocr_t oc ) +{ + OCR0B = oc; +} + +__attribute__((always_inline)) static inline void Timer0_EnableOutputCompareInterruptA( void ) +{ + TIMSK |= (1< + +int main(void) +{ + init(); + + setup(); + + for (;;) + loop(); + + return 0; +} + diff --git a/hardware/digistump/avr/cores/tiny/new.cpp b/hardware/digistump/avr/cores/tiny/new.cpp new file mode 100644 index 0000000..0f6d422 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/new.cpp @@ -0,0 +1,18 @@ +#include + +void * operator new(size_t size) +{ + return malloc(size); +} + +void operator delete(void * ptr) +{ + free(ptr); +} + +int __cxa_guard_acquire(__guard *g) {return !*(char *)(g);}; +void __cxa_guard_release (__guard *g) {*(char *)g = 1;}; +void __cxa_guard_abort (__guard *) {}; + +void __cxa_pure_virtual(void) {}; + diff --git a/hardware/digistump/avr/cores/tiny/new.h b/hardware/digistump/avr/cores/tiny/new.h new file mode 100644 index 0000000..cd940ce --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/new.h @@ -0,0 +1,22 @@ +/* Header to define new/delete operators as they aren't provided by avr-gcc by default + Taken from http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&t=59453 + */ + +#ifndef NEW_H +#define NEW_H + +#include + +void * operator new(size_t size); +void operator delete(void * ptr); + +__extension__ typedef int __guard __attribute__((mode (__DI__))); + +extern "C" int __cxa_guard_acquire(__guard *); +extern "C" void __cxa_guard_release (__guard *); +extern "C" void __cxa_guard_abort (__guard *); + +extern "C" void __cxa_pure_virtual(void); + +#endif + diff --git a/hardware/digistump/avr/cores/tiny/pins_arduino.c b/hardware/digistump/avr/cores/tiny/pins_arduino.c new file mode 100644 index 0000000..ea70922 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/pins_arduino.c @@ -0,0 +1,321 @@ +/* + pins_arduino.c - pin definitions for the Arduino board + Part of Arduino / Wiring Lite + + Copyright (c) 2005 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: pins_arduino.c 565 2009-03-25 10:50:00Z dmellis $ + + Modified 28-08-2009 for attiny84 R.Wiersma + Modified 09-10-2009 for attiny45 A.Saporetti + Modified for Atmel ATTiny2313 mcu by René Bohne + + Corrected 17-05-2010 for ATtiny84 B.Cook ... + + The default analog_reference leaves chip pin 13 (digital pin 10; PA0) + unconnected. So the pin can be set to a non-floating state and so the + pin can be used as another digital pin, support for digital pin 10 was + added. +*/ + +#include +#include "pins_arduino.h" +#include "wiring_private.h" + + +#if defined( __AVR_ATtinyX313__ ) + +// On the Arduino board, digital pins are also used +// for the analog output (software PWM). Analog input +// pins are a separate set. + +// ATMEL ATTINY2313 +// +// +-\/-+ +// (D 17) PA2 1| |29 VCC +// RX (D 0) PD0 2| |19 PB7 (D 16) +// TX (D 1) PD1 3| |18 PB6 (D 15) +// (D 2) PA1 4| |17 PB5 (D 14) +// (D 3) PA0 5| |16 PB4 (D 13)* +// INT0 (D 4) PD2 6| |15 PB3 (D 12)* +// INT1 (D 5) PD3 7| |14 PB2 (D 11)* +// (D 6) PD4 8| |13 PB1 (D 10) +// *(D 7) PD5 9| |12 PB0 (D 9) +// GND 10| |11 PD6 (D 8) +// +----+ +// +// * indicates PWM port + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) +const uint8_t PROGMEM port_to_mode_PGM[] = +{ + NOT_A_PORT, + &DDRA, + &DDRB, + NOT_A_PORT, + &DDRD, +}; + +const uint8_t PROGMEM port_to_output_PGM[] = +{ + NOT_A_PORT, + &PORTA, + &PORTB, + NOT_A_PORT, + &PORTD, +}; + +const uint8_t PROGMEM port_to_input_PGM[] = +{ + NOT_A_PORT, + &PINA, + &PINB, + NOT_A_PORT, + &PIND, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = +{ + PORT_D_ID, /* 0 */ + PORT_D_ID, + PORT_A_ID, + PORT_A_ID, + PORT_D_ID, + PORT_D_ID, + PORT_D_ID, + PORT_D_ID, + PORT_D_ID, /* 8 */ + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, /* 14 */ + PORT_B_ID, + PORT_B_ID, + PORT_A_ID, +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = +{ + _BV(0), /* 0 */ + _BV(1), + _BV(1), + _BV(0), + _BV(2), + _BV(3), + _BV(4), + _BV(5), + _BV(6), /* 8 */ + _BV(0), + _BV(1), + _BV(2), + _BV(3), + _BV(4), + _BV(5), /* 14 */ + _BV(6), + _BV(7), + _BV(2), +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = +{ + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + TIMER0B, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + TIMER0A, + TIMER1A, + TIMER1B, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +#endif + + +#if defined( __AVR_ATtinyX4__ ) + +// ATMEL ATTINY84 / ARDUINO +// +// +-\/-+ +// VCC 1| |14 GND +// (D 0) PB0 2| |13 AREF (D 10) +// (D 1) PB1 3| |12 PA1 (D 9) +// PB3 4| |11 PA2 (D 8) +// PWM INT0 (D 2) PB2 5| |10 PA3 (D 7) +// PWM (D 3) PA7 6| |9 PA4 (D 6) +// PWM (D 4) PA6 7| |8 PA5 (D 5) PWM +// +----+ + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) +const uint8_t PROGMEM port_to_mode_PGM[] = +{ + NOT_A_PORT, + &DDRA, + &DDRB, +}; + +const uint8_t PROGMEM port_to_output_PGM[] = +{ + NOT_A_PORT, + &PORTA, + &PORTB, +}; + +const uint8_t PROGMEM port_to_input_PGM[] = +{ + NOT_A_PORT, + &PINA, + &PINB, +}; + +const uint8_t PROGMEM port_to_pcmask_PGM[] = +{ + NOT_A_PORT, + &PCMSK0, + &PCMSK1, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = +{ + PORT_B_ID, /* 0 */ + PORT_B_ID, + PORT_B_ID, + PORT_A_ID, + PORT_A_ID, + PORT_A_ID, + PORT_A_ID, + PORT_A_ID, + PORT_A_ID, /* 8 */ + PORT_A_ID, + PORT_A_ID, +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = +{ + _BV(0), /* 0, port B */ + _BV(1), + _BV(2), + _BV(7), /* 3 port B */ + _BV(6), + _BV(5), + _BV(4), + _BV(3), + _BV(2), + _BV(1), + _BV(0), +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = +{ + NOT_ON_TIMER, + NOT_ON_TIMER, + TIMER0A, /* OC0A */ + TIMER0B, /* OC0B */ + TIMER1A, /* OC1A */ + TIMER1B, /* OC1B */ + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +#endif + + +#if defined( __AVR_ATtinyX5__ ) + +// ATMEL ATTINY45 / ARDUINO +// +// +-\/-+ +// Ain0 (D 5) PB5 1| |8 VCC +// Ain3 (D 3) PB3 2| |7 PB2 (D 2) INT0 Ain1 +// Ain2 (D 4) PB4 3| |6 PB1 (D 1) pwm1 +// GND 4| |5 PB0 (D 0) pwm0 +// +----+ + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) tiny45 only port B +const uint8_t PROGMEM port_to_mode_PGM[] = +{ + NOT_A_PORT, + &DDRB, +}; + +const uint8_t PROGMEM port_to_output_PGM[] = +{ + NOT_A_PORT, + &PORTB, +}; + +const uint8_t PROGMEM port_to_input_PGM[] = +{ + NOT_A_PIN, + &PINB, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = +{ + PORT_B_ID, /* 0 */ + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, /* 5 */ + +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = +{ + _BV(0), /* 0, port B */ + _BV(1), + _BV(2), + _BV(3), /* 3 port B */ + _BV(4), + _BV(5), + +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = +{ + TIMER0A, /* OC0A */ + TIMER1A, /* OC1A? */ + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +#endif diff --git a/hardware/digistump/avr/cores/tiny/pins_arduino.h b/hardware/digistump/avr/cores/tiny/pins_arduino.h new file mode 100644 index 0000000..b49b33c --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/pins_arduino.h @@ -0,0 +1,115 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.h 249 2007-02-03 16:52:51Z mellis $ + + Modified 28-08-2009 for attiny84 R.Wiersma + Modified 14-10-2009 for attiny45 Saposoft +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#include "core_build_options.h" + +#if defined( __AVR_ATtinyX313__ ) +#define PORT_A_ID 1 +#define PORT_B_ID 2 +#define PORT_D_ID 4 +#endif + +#if defined( __AVR_ATtinyX4__ ) +#define PORT_A_ID 1 +#define PORT_B_ID 2 +#endif + +#if defined( __AVR_ATtinyX5__ ) +#define PORT_B_ID 1 +#endif + +#define NOT_A_PIN 0 +#define NOT_A_PORT 0 + +#define NOT_ON_TIMER 0 +#define TIMER0A 1 +#define TIMER0B 2 +#define TIMER1A 3 +#define TIMER1B 4 + +//changed it to uint16_t to uint8_t +extern const uint8_t PROGMEM port_to_mode_PGM[]; +extern const uint8_t PROGMEM port_to_input_PGM[]; +extern const uint8_t PROGMEM port_to_output_PGM[]; +extern const uint8_t PROGMEM port_to_pcmask_PGM[]; + +extern const uint8_t PROGMEM digital_pin_to_port_PGM[]; +// extern const uint8_t PROGMEM digital_pin_to_bit_PGM[]; +extern const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[]; +extern const uint8_t PROGMEM digital_pin_to_timer_PGM[]; + +// Get the bit location within the hardware port of the given virtual pin. +// This comes from the pins_*.c file for the active board configuration. +// +// These perform slightly better as macros compared to inline functions +// +#define digitalPinToPort(P) ( pgm_read_byte( digital_pin_to_port_PGM + (P) ) ) +#define digitalPinToBitMask(P) ( pgm_read_byte( digital_pin_to_bit_mask_PGM + (P) ) ) +#define digitalPinToTimer(P) ( pgm_read_byte( digital_pin_to_timer_PGM + (P) ) ) +#define analogInPinToBit(P) (P) +// in the following lines modified pgm_read_word in pgm_read_byte, word doesn't work on attiny45 +#define portOutputRegister(P) ( (volatile uint8_t *)( pgm_read_byte( port_to_output_PGM + (P))) ) +#define portInputRegister(P) ( (volatile uint8_t *)( pgm_read_byte( port_to_input_PGM + (P))) ) +#define portModeRegister(P) ( (volatile uint8_t *)( pgm_read_byte( port_to_mode_PGM + (P))) ) +#define portPcMaskRegister(P) ( (volatile uint8_t *)( pgm_read_byte( port_to_pcmask_PGM + (P))) ) + +#if defined(__AVR_ATtinyX5__) +#define digitalPinToPCICR(p) (((p) >= 0 && (p) <= 5) ? (&GIMSK) : ((uint8_t *)NULL)) +#define digitalPinToPCICRbit(p) (PCIE) +#define digitalPinToPCMSK(p) (((p) >= 0 && (p) <= 5) ? (&PCMSK) : ((uint8_t *)NULL)) +#define digitalPinToPCMSKbit(p) (p) +#endif + +#if defined(__AVR_ATtinyX4__) +#define digitalPinToPCICR(p) (((p) >= 0 && (p) <= 10) ? (&GIMSK) : ((uint8_t *)NULL)) +#define digitalPinToPCICRbit(p) (((p) <= 2) ? PCIE1 : PCIE0) +#define digitalPinToPCMSK(p) (((p) <= 2) ? (&PCMSK1) : (((p) <= 10) ? (&PCMSK0) : ((uint8_t *)NULL))) +#define digitalPinToPCMSKbit(p) (((p) <= 2) ? (p) : (10 - (p))) +#endif + +#if defined(__AVR_ATtiny4313__) +#define digitalPinToPCX(p,s1,s2,s3,s4,s5) \ + (((p) >= 0) \ + ? (((p) <= 1) ? (s1) /* 0 - 1 ==> D0 - D1 */ \ + : (((p) <= 3) ? (s2) /* 2 - 3 ==> A1 - A0 */ \ + : (((p) <= 8) ? (s3) /* 4 - 8 ==> D2 - D6 */ \ + : (((p) <= 16) ? (s4) /* 9 - 16 ==> B0 - B7 */ \ + : (s5))))) \ + : (s5)) +// s1 D s2 A s3 D s4 B +#define digitalPinToPCICR(p) digitalPinToPCX( p, &GIMSK, &GIMSK, &GIMSK, &GIMSK, NULL ) +#define digitalPinToPCICRbit(p) digitalPinToPCX( p, PCIE2, PCIE1, PCIE2, PCIE0, 0 ) +#define digitalPinToPCMSK(p) digitalPinToPCX( p, &PCMSK2, &PCMSK1, &PCMSK2, &PCMSK0, NULL ) +#define digitalPinToPCMSKbit(p) digitalPinToPCX( p, p, 3-p, p-2, p-9, 0 ) +#endif + +#endif diff --git a/hardware/digistump/avr/cores/tiny/wiring.c b/hardware/digistump/avr/cores/tiny/wiring.c new file mode 100644 index 0000000..be21ca4 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/wiring.c @@ -0,0 +1,366 @@ +/* + wiring.c - Partial implementation of the Wiring API for the ATmega8. + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.c 970 2010-05-25 20:16:15Z dmellis $ + + Modified 28-08-2009 for attiny84 R.Wiersma + Modified 14-10-2009 for attiny45 Saposoft + Modified 20-11-2010 - B.Cook - Rewritten to use the various Veneers. +*/ + +#include "core_build_options.h" +#include "core_adc.h" +#include "core_timers.h" +#include "wiring_private.h" +#include "ToneTimer.h" +#if F_CPU != 16500000L + #include +#endif + +#define millistimer_(t) TIMER_PASTE_A( timer, TIMER_TO_USE_FOR_MILLIS, t ) +#define MillisTimer_(f) TIMER_PASTE_A( Timer, TIMER_TO_USE_FOR_MILLIS, f ) +#define MILLISTIMER_(c) TIMER_PASTE_A( TIMER, TIMER_TO_USE_FOR_MILLIS, c ) + +#define MillisTimer_SetToPowerup MillisTimer_(SetToPowerup) +#define MillisTimer_SetWaveformGenerationMode MillisTimer_(SetWaveformGenerationMode) +#define MillisTimer_GetCount MillisTimer_(GetCount) +#define MillisTimer_IsOverflowSet MillisTimer_(IsOverflowSet) +#define MillisTimer_ClockSelect MillisTimer_(ClockSelect) +#define MillisTimer_EnableOverflowInterrupt MillisTimer_(EnableOverflowInterrupt) +#define MILLISTIMER_OVF_vect MILLISTIMER_(OVF_vect) + + +#define MS_TIMER_TICK_EVERY_X_CYCLES 64 /* Shall be a within 1, 8, 64, 256 or 1024. (default = 64) If set to 1, HW PWM is around 64.5KHz@16.5MHz with Digispark */ + +#if F_CPU >= 3000000L +#if !defined(MS_TIMER_TICK_EVERY_X_CYCLES) + #define MillisTimer_Prescale_Index MillisTimer_(Prescale_Value_64) + #define MillisTimer_Prescale_Value (64) + #define ToneTimer_Prescale_Index ToneTimer_(Prescale_Value_64) + #define ToneTimer_Prescale_Value (64) +#else + #define Prescaler_Value(Val) PRESCALER_VALUE(Val) + #define PRESCALER_VALUE(Val) Prescale_Value_##Val + #define MillisTimer_Prescale_Index MillisTimer_(Prescaler_Value(MS_TIMER_TICK_EVERY_X_CYCLES)) + #define MillisTimer_Prescale_Value (MS_TIMER_TICK_EVERY_X_CYCLES) + #define ToneTimer_Prescale_Index ToneTimer_(Prescaler_Value(MS_TIMER_TICK_EVERY_X_CYCLES)) + #define ToneTimer_Prescale_Value (MS_TIMER_TICK_EVERY_X_CYCLES) +#endif +#else + #define MillisTimer_Prescale_Index MillisTimer_(Prescale_Value_8) + #define MillisTimer_Prescale_Value (8) + #define ToneTimer_Prescale_Index ToneTimer_(Prescale_Value_8) + #define ToneTimer_Prescale_Value (8) +#endif + +// the prescaler is set so that the millis timer ticks every MillisTimer_Prescale_Value (64) clock cycles, and the +// the overflow handler is called every 256 ticks. +#define MICROSECONDS_PER_MILLIS_OVERFLOW (clockCyclesToMicroseconds(MillisTimer_Prescale_Value * 256)) + +// the whole number of milliseconds per millis timer overflow +#define MILLIS_INC (MICROSECONDS_PER_MILLIS_OVERFLOW / 1000) + +// the fractional number of milliseconds per millis timer overflow. we shift right +// by three to fit these numbers into a byte. (for the clock speeds we care +// about - 8 and 16 MHz - this doesn't lose precision.) +#define FRACT_INC ((MICROSECONDS_PER_MILLIS_OVERFLOW % 1000) >> 3) +#define FRACT_MAX (1000 >> 3) + +volatile unsigned long millis_timer_overflow_count = 0; +volatile unsigned long millis_timer_millis = 0; +static unsigned char millis_timer_fract = 0; + +// bluebie changed isr to noblock so it wouldn't mess up USB libraries +ISR(MILLISTIMER_OVF_vect, ISR_NOBLOCK) +{ + // copy these to local variables so they can be stored in registers + // (volatile variables must be read from memory on every access) + unsigned long m = millis_timer_millis; + unsigned char f = millis_timer_fract; + +/* rmv: The code below generates considerably less code (emtpy Sketch is 326 versus 304)... + + m += MILLIS_INC; + f += FRACT_INC; + if (f >= FRACT_MAX) { + f -= FRACT_MAX; + m += 1; + } +...rmv */ + + f += FRACT_INC; + + if (f >= FRACT_MAX) + { + f -= FRACT_MAX; + m = m + MILLIS_INC + 1; + } + else + { + m += MILLIS_INC; + } + + millis_timer_fract = f; + millis_timer_millis = m; + millis_timer_overflow_count++; +} + +unsigned long millis() +{ + unsigned long m; + uint8_t oldSREG = SREG; + + // disable interrupts while we read millis_timer_millis or we might get an + // inconsistent value (e.g. in the middle of a write to millis_timer_millis) + cli(); + m = millis_timer_millis; + SREG = oldSREG; + + return m; +} + +unsigned long micros() +{ + unsigned long m; + uint8_t oldSREG = SREG, t; + + cli(); + m = millis_timer_overflow_count; + t = MillisTimer_GetCount(); + + if (MillisTimer_IsOverflowSet() && (t < 255)) + m++; + + SREG = oldSREG; + +#if (MillisTimer_Prescale_Value >= clockCyclesPerMicrosecond()) + return ((m << 8) + t) * (MillisTimer_Prescale_Value / clockCyclesPerMicrosecond()); +#else + return ((m << 8) + t) / (clockCyclesPerMicrosecond() / MillisTimer_Prescale_Value); +#endif +} + +void delay(unsigned long ms) +{ + uint16_t start = (uint16_t)micros(); + + while (ms > 0) { + if (((uint16_t)micros() - start) >= 1000) { + ms--; + start += 1000; + } + } +} + +#if F_CPU == 16500000L + // optimised delay loop from Bluebie contributed to Digispark project + // deals accurately with half-mhz clock speed, but can only delay in increments of 2us rounded down + // this loop has been tuned empirically with an oscilloscope and works in avr-gcc 4.5.1 + void delayMicroseconds(unsigned int us){ + us &= ((unsigned int) 0) - ((unsigned int) 2); // remove least signifficant bit + while (us > 1) { + // 16 nops + asm("NOP");asm("NOP");asm("NOP");asm("NOP");asm("NOP");asm("NOP");asm("NOP");asm("NOP"); + asm("NOP");asm("NOP");asm("NOP");asm("NOP");asm("NOP");asm("NOP");asm("NOP");asm("NOP"); + // 11 nops + asm("NOP");asm("NOP");asm("NOP");asm("NOP");asm("NOP");asm("NOP");asm("NOP");asm("NOP"); + asm("NOP");asm("NOP");asm("NOP"); + + us -= 2; + } + } +#else + /* Improved delayMicroseconds function + * Copyright (c) 2011, Paul Stoffregen, paul at pjrc dot com + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + // modified by Bluebie in 2013 for Digispark project + // #include + // #include + + void delayMicroseconds(uint16_t usec) { + asm volatile( + #if F_CPU == 16000000L + "sbiw %A0, 2" "\n\t" // 2 + "brcs L_%=_end" "\n\t" // 1 + "breq L_%=_end" "\n\t" // 1 + "lsl %A0" "\n\t" // 1 + "rol %B0" "\n\t" // 1 + "lsl %A0" "\n\t" // 1 + "rol %B0" "\n\t" // 1 overhead: (8)/4 = 2us + #elif F_CPU == 8000000L + "sbiw %A0, 3" "\n\t" // 2 + "brcs L_%=_end" "\n\t" // 1 + "breq L_%=_end" "\n\t" // 1 + "lsl %A0" "\n\t" // 1 + "rol %B0" "\n\t" // 1 overhead: (6)/2 = 3 us + #elif F_CPU == 4000000L + "sbiw %A0, 4" "\n\t" // 2 + "brcs L_%=_end" "\n\t" // 1 + "breq L_%=_end" "\n\t" // 1 overhead: (4) = 4 us + #elif F_CPU == 2000000L + "sbiw %A0, 12" "\n\t" // 2 + "brcs L_%=_end" "\n\t" // 1 + "breq L_%=_end" "\n\t" // 1 + "lsr %B0" "\n\t" // 1 + "ror %A0" "\n\t" // 1 overhead: (6)*2 = 12 us + #elif F_CPU == 1000000L + "sbiw %A0, 32" "\n\t" // 2 + "brcs L_%=_end" "\n\t" // 1 + "breq L_%=_end" "\n\t" // 1 + "lsr %B0" "\n\t" // 1 + "ror %A0" "\n\t" // 1 + "lsr %B0" "\n\t" // 1 + "ror %A0" "\n\t" // 1 overhead: (8)*4 = 32 us + #endif + "L_%=_loop:" + "sbiw %A0, 1" "\n\t" // 2 + "brne L_%=_loop" "\n\t" // 2 + "L_%=_end:" + : "+w" (usec) + : "0" (usec) + ); + } +#endif + +static void initToneTimerInternal(void) +{ + // Stop the clock while we make changes + ToneTimer_ClockSelect( ToneTimer_(Stopped) ); + + // Set the timer to phase-correct PWM + #if defined( TONETIMER_SUPPORTS_PHASE_CORRECT_PWM ) && TONETIMER_SUPPORTS_PHASE_CORRECT_PWM + ToneTimer_SetWaveformGenerationMode( ToneTimer_(Phase_Correct_PWM_FF) ); + #else + ToneTimer_SetWaveformGenerationMode( ToneTimer_(Fast_PWM_FF) ); + #endif + + // Timer is processor clock divided by ToneTimer_Prescale_Index (64) + ToneTimer_ClockSelect( ToneTimer_Prescale_Index ); +} + +void initToneTimer(void) +{ + // Ensure the timer is in the same state as power-up + ToneTimer_SetToPowerup(); + + #if defined( INITIALIZE_SECONDARY_TIMERS ) && INITIALIZE_SECONDARY_TIMERS + // Prepare the timer for PWM + initToneTimerInternal(); + #endif +} + +#if F_CPU != 16500000L + // used to detect bootloader applying calibration in init + byte read_factory_calibration(void) + { + byte SIGRD = 5; // for some reason this isn't defined... + byte value = boot_signature_byte_get(1); + return value; + } +#endif + +void init(void) +{ + // clock calibration stuff + // recalibrate clock if it was calibrated by bootloader (like micronucleus) + #if F_CPU != 16500000L + if (OSCCAL != read_factory_calibration()) { + // adjust the calibration down from 16.5mhz to 16.0mhz + if (OSCCAL >= 128) { + // maybe 8 is better? oh well - only about 0.3% out anyway + OSCCAL -= 7; + } else { + OSCCAL -= 5; + } + } + #endif + + // TODO: detect if fuses set to PLL, regular internal oscillator or external and change behaviour in this next section... + #if F_CPU < 16000000L + cli(); + CLKPR = 0b10000000; + #if F_CPU == 8000000L + CLKPR = 1; // div 2 + #elif F_CPU == 4000000L + CLKPR = 2 // div 4 + #elif F_CPU == 2000000L + CLKPR = 3; // div 8 + #elif F_CPU == 1000000L + CLKPR = 4; // div 16 + #elif F_CPU == 500000L + CLKPR = 5; // div 32 = 500khz + #elif F_CPU == 250000L + CLKPR = 6; // div 64 = 250khz + #elif F_CPU == 125000L + CLKPR = 7; // div 128 = 125khz cpu clock + #else + #warning "Cannot prescale chip to specified F_CPU speed" + #endif + #endif + + // this needs to be called before setup() or some functions won't work there + sei(); + + // In case the bootloader left our millis timer in a bad way + #if defined( HAVE_BOOTLOADER ) && HAVE_BOOTLOADER + MillisTimer_SetToPowerup(); + #endif + + // Use the Millis Timer for fast PWM + MillisTimer_SetWaveformGenerationMode( MillisTimer_(Fast_PWM_FF) ); + + // Millis timer is always processor clock divided by MillisTimer_Prescale_Value (64) + MillisTimer_ClockSelect( MillisTimer_Prescale_Index ); + + // Enable the overlow interrupt (this is the basic system tic-toc for millis) + MillisTimer_EnableOverflowInterrupt(); + + // Initialize the timer used for Tone + #if defined( INITIALIZE_SECONDARY_TIMERS ) && INITIALIZE_SECONDARY_TIMERS + initToneTimerInternal(); + #endif + + // Initialize the ADC + #if defined( INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER ) && INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER + ADC_PrescalerSelect( ADC_ARDUINO_PRESCALER ); + ADC_Enable(); + #endif +} + diff --git a/hardware/digistump/avr/cores/tiny/wiring.h b/hardware/digistump/avr/cores/tiny/wiring.h new file mode 100644 index 0000000..6946ab2 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/wiring.h @@ -0,0 +1,194 @@ +/* + wiring.h - Partial implementation of the Wiring API for the ATmega8. + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.h 1073 2010-08-17 21:50:41Z dmellis $ + + Modified 28-08-2009 for attiny84 R.Wiersma + Modified 14-108-2009 for attiny45 Saposoft +*/ + +#ifndef Wiring_h +#define Wiring_h + +#include +#include + +#include "binary.h" +#include "core_build_options.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +#define HIGH 0x1 +#define LOW 0x0 + +#define INPUT 0x0 +#define OUTPUT 0x1 + +#define true 0x1 +#define false 0x0 + +#define PI 3.1415926535897932384626433832795 +#define HALF_PI 1.5707963267948966192313216916398 +#define TWO_PI 6.283185307179586476925286766559 +#define DEG_TO_RAD 0.017453292519943295769236907684886 +#define RAD_TO_DEG 57.295779513082320876798154814105 + +#define SERIAL 0x0 +#define DISPLAY 0x1 + +#define LSBFIRST 0 +#define MSBFIRST 1 + +#define CHANGE 1 +#define FALLING 2 +#define RISING 3 + +/* rmv or fix +#if defined(__AVR_ATmega1280__) +#define INTERNAL1V1 2 +#define INTERNAL2V56 3 +#else +#define INTERNAL 3 +#endif +#define DEFAULT 1 +#define EXTERNAL 0 +*/ + +/* rmv +analogReference constants for ATmega168. These are NOT correct for the ATtiny84 nor for the ATtiny85. The correct values are below. + +// Internal 1.1V Voltage Reference with external capacitor at AREF pin +#define INTERNAL 3 + +// AVCC with external capacitor at AREF pin +#define DEFAULT 1 + +// AREF, Internal Vref turned off +#define EXTERNAL 0 +*/ + + +#if defined( __AVR_ATtinyX313__ ) + +#define DEFAULT (0) + +#elif defined( __AVR_ATtinyX4__ ) + +// VCC used as analog reference, disconnected from PA0 (AREF) +#define DEFAULT (0) + +// External voltage reference at PA0 (AREF) pin, internal reference turned off +#define EXTERNAL (1) + +// Internal 1.1V voltage reference +#define INTERNAL (2) + +#elif defined( __AVR_ATtinyX5__ ) + +// X 0 0 VCC used as Voltage Reference, disconnected from PB0 (AREF). +#define DEFAULT (0) + +// X 0 1 External Voltage Reference at PB0 (AREF) pin, Internal Voltage Reference turned off. +#define EXTERNAL (1) + +// 0 1 0 Internal 1.1V Voltage Reference. +#define INTERNAL (2) +#define INTERNAL1V1 INTERNAL + +// 1 1 1 Internal 2.56V Voltage Reference with external bypass capacitor at PB0 (AREF) pin(1). +#define INTERNAL2V56 (7) + +// An alternative for INTERNAL2V56 is (6) ... +// 1 1 0 Internal 2.56V Voltage Reference without external bypass capacitor, disconnected from PB0 (AREF)(1). + +#endif + + +// undefine stdlib's abs if encountered +#ifdef abs +#undef abs +#endif + +#define min(a,b) ((a)<(b)?(a):(b)) +#define max(a,b) ((a)>(b)?(a):(b)) +#define abs(x) ((x)>0?(x):-(x)) +#define constrain(amt,low,high) ((amt)<(low)?(low):((amt)>(high)?(high):(amt))) +#if __AVR_LIBC_VERSION__ < 10701UL + #define round(x) ((x)>=0?(long)((x)+0.5):(long)((x)-0.5)) +#endif +#define radians(deg) ((deg)*DEG_TO_RAD) +#define degrees(rad) ((rad)*RAD_TO_DEG) +#define sq(x) ((x)*(x)) + +#define interrupts() sei() +#define noInterrupts() cli() + +#define clockCyclesPerMicrosecond() ( F_CPU / 1000000L ) +#define clockCyclesToMicroseconds(a) ( ((a) * 1000L) / (F_CPU / 1000L) ) +#define microsecondsToClockCycles(a) ( ((a) * (F_CPU / 1000L)) / 1000L ) + +#define lowByte(w) ((uint8_t) ((w) & 0xff)) +#define highByte(w) ((uint8_t) ((w) >> 8)) + +#define bitRead(value, bit) (((value) >> (bit)) & 0x01) +#define bitSet(value, bit) ((value) |= (1UL << (bit))) +#define bitClear(value, bit) ((value) &= ~(1UL << (bit))) +#define bitWrite(value, bit, bitvalue) (bitvalue ? bitSet(value, bit) : bitClear(value, bit)) + +typedef unsigned int word; + +#define bit(b) (1UL << (b)) + +typedef uint8_t boolean; +typedef uint8_t byte; + +void initToneTimer(void); +void init(void); + +void pinMode(uint8_t, uint8_t); +void digitalWrite(uint8_t, uint8_t); +int digitalRead(uint8_t); +int analogRead(uint8_t); +void analogReference(uint8_t mode); +void analogWrite(uint8_t, int); + +unsigned long millis(void); +unsigned long micros(void); +void delay(unsigned long); +void delayMicroseconds(unsigned int us); +unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout); + +void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t val); +uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder); + +void attachInterrupt(uint8_t, void (*)(void), int mode); +void detachInterrupt(uint8_t); + +void setup(void); +void loop(void); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/hardware/digistump/avr/cores/tiny/wiring_analog.c b/hardware/digistump/avr/cores/tiny/wiring_analog.c new file mode 100644 index 0000000..798e879 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/wiring_analog.c @@ -0,0 +1,140 @@ +/* + wiring_analog.c - analog input and output + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $ + + Modified 28-08-2009 for attiny84 R.Wiersma + Modified 14-10-2009 for attiny45 Saposoft + Corrected 17-05-2010 for ATtiny84 B.Cook +*/ + +#include "wiring_private.h" +#include "pins_arduino.h" +#include "core_adc.h" +#include "core_pins.h" +#include "core_timers.h" +#include "PwmTimer.h" + +uint8_t analog_reference = DEFAULT; + +void analogReference(uint8_t mode) +{ + // can't actually set the register here because the default setting + // will connect AVCC and the AREF pin, which would cause a short if + // there's something connected to AREF. + // fix? Validate the mode? + analog_reference = mode; +} + +int analogRead(uint8_t pin) +{ + #if defined( CORE_ANALOG_FIRST ) + if ( pin >= CORE_ANALOG_FIRST ) pin -= CORE_ANALOG_FIRST; // allow for channel or pin numbers + #endif + + // fix? Validate pin? + + ADC_SetVoltageReference( analog_reference ); + ADC_SetInputChannel( pin ); + + ADC_StartConversion(); + + while( ADC_ConversionInProgress() ); + + return( ADC_GetDataRegister() ); +} + +// Right now, PWM output only works on the pins with +// hardware support. These are defined in the appropriate +// pins_*.c file. For the rest of the pins, we default +// to digital output. +void analogWrite(uint8_t pin, int val) +{ + // We need to make sure the PWM output is enabled for those pins + // that support it, as we turn it off when digitally reading or + // writing with them. Also, make sure the pin is in output mode + // for consistenty with Wiring, which doesn't require a pinMode + // call for the analog output pins. + pinMode(pin, OUTPUT); + + if (val <= 0) + { + digitalWrite(pin, LOW); + } + else if (val >= 255) + { + digitalWrite(pin, HIGH); + } + else + { + #if CORE_PWM_COUNT >= 1 + if ( pin == CORE_PWM0_PIN ) + { + Pwm0_SetCompareOutputMode( Pwm0_Clear ); + Pwm0_SetOutputCompareMatch( val ); + } + else + #endif + + #if CORE_PWM_COUNT >= 2 + if ( pin == CORE_PWM1_PIN ) + { + Pwm1_SetCompareOutputMode( Pwm1_Clear ); + Pwm1_SetOutputCompareMatch( val ); + } + else + #endif + + #if CORE_PWM_COUNT >= 3 + if ( pin == CORE_PWM2_PIN ) + { + Pwm2_SetCompareOutputMode( Pwm2_Clear ); + Pwm2_SetOutputCompareMatch( val ); + } + else + #endif + + #if CORE_PWM_COUNT >= 4 + if ( pin == CORE_PWM3_PIN ) + { + Pwm3_SetCompareOutputMode( Pwm3_Clear ); + Pwm3_SetOutputCompareMatch( val ); + } + else + #endif + + #if CORE_PWM_COUNT >= 5 + #error Only 4 PWM pins are supported. Add more conditions. + #endif + + { + if (val < 128) + { + digitalWrite(pin, LOW); + } + else + { + digitalWrite(pin, HIGH); + } + } + + } +} diff --git a/hardware/digistump/avr/cores/tiny/wiring_digital.c b/hardware/digistump/avr/cores/tiny/wiring_digital.c new file mode 100644 index 0000000..48ee476 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/wiring_digital.c @@ -0,0 +1,148 @@ +/* + wiring_digital.c - digital input and output functions + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $ + + Modified 28-08-2009 for attiny84 R.Wiersma + Modified 14-10-2009 for attiny45 Saposoft +*/ + +#include "wiring_private.h" +#include "pins_arduino.h" +#include "core_pins.h" +#include "core_timers.h" +#include "PwmTimer.h" + +void pinMode(uint8_t pin, uint8_t mode) +{ + uint8_t bit = digitalPinToBitMask(pin); + uint8_t port = digitalPinToPort(pin); + volatile uint8_t *reg; + + if (port == NOT_A_PIN) return; + + // JWS: can I let the optimizer do this? + reg = portModeRegister(port); + + if (mode == INPUT) { + uint8_t oldSREG = SREG; + cli(); + *reg &= ~bit; + SREG = oldSREG; + } else { + uint8_t oldSREG = SREG; + cli(); + *reg |= bit; + SREG = oldSREG; + } +} + +// Forcing this inline keeps the callers from having to push their own stuff +// on the stack. It is a good performance win and only takes 1 more byte per +// user than calling. (It will take more bytes on the 168.) +// +// But shouldn't this be moved into pinMode? Seems silly to check and do on +// each digitalread or write. +// +__attribute__((always_inline)) static inline void turnOffPWM( uint8_t pin ) +{ + #if CORE_PWM_COUNT >= 1 + if ( pin == CORE_PWM0_PIN ) + { + Pwm0_SetCompareOutputMode( Pwm0_Disconnected ); + } + else + #endif + + #if CORE_PWM_COUNT >= 2 + if ( pin == CORE_PWM1_PIN ) + { + Pwm1_SetCompareOutputMode( Pwm1_Disconnected ); + } + else + #endif + + #if CORE_PWM_COUNT >= 3 + if ( pin == CORE_PWM2_PIN ) + { + Pwm2_SetCompareOutputMode( Pwm2_Disconnected ); + } + else + #endif + + #if CORE_PWM_COUNT >= 4 + if ( pin == CORE_PWM3_PIN ) + { + Pwm3_SetCompareOutputMode( Pwm3_Disconnected ); + } + else + #endif + + #if CORE_PWM_COUNT >= 5 + #error Only 4 PWM pins are supported. Add more conditions. + #endif + + { + } + +} + +void digitalWrite(uint8_t pin, uint8_t val) +{ + uint8_t bit = digitalPinToBitMask(pin); + uint8_t port = digitalPinToPort(pin); + volatile uint8_t *out; + + if (port == NOT_A_PIN) return; + + // If the pin that support PWM output, we need to turn it off + // before doing a digital write. + turnOffPWM( pin ); + + out = portOutputRegister(port); + + if (val == LOW) { + uint8_t oldSREG = SREG; + cli(); + *out &= ~bit; + SREG = oldSREG; + } else { + uint8_t oldSREG = SREG; + cli(); + *out |= bit; + SREG = oldSREG; + } +} + +int digitalRead(uint8_t pin) +{ + uint8_t bit = digitalPinToBitMask(pin); + uint8_t port = digitalPinToPort(pin); + + if (port == NOT_A_PIN) return LOW; + + // If the pin that support PWM output, we need to turn it off + // before getting a digital reading. + turnOffPWM( pin ); + + if (*portInputRegister(port) & bit) return HIGH; + return LOW; +} diff --git a/hardware/digistump/avr/cores/tiny/wiring_private.h b/hardware/digistump/avr/cores/tiny/wiring_private.h new file mode 100644 index 0000000..b16eb43 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/wiring_private.h @@ -0,0 +1,179 @@ +/* + wiring_private.h - Internal header file. + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.h 239 2007-01-12 17:58:39Z mellis $ + + Modified 28-08-2009 for attiny84 R.Wiersma +*/ + +#ifndef WiringPrivate_h +#define WiringPrivate_h + +#include +#include +#include +#include +#include + +#include "wiring.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +#ifndef cbi +#define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit)) +#endif +#ifndef sbi +#define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit)) +#endif + +#if defined( EXT_INT0_vect ) + #define EXTERNAL_INTERRUPT_0_vect EXT_INT0_vect +#elif defined( INT0_vect ) + #define EXTERNAL_INTERRUPT_0_vect INT0_vect +#endif + +#if defined( EXT_INT1_vect ) + #define EXTERNAL_INTERRUPT_1_vect EXT_INT1_vect +#elif defined( INT1_vect ) + #define EXTERNAL_INTERRUPT_1_vect INT1_vect +#endif + +#if defined( EXT_INT2_vect ) + #define EXTERNAL_INTERRUPT_2_vect EXT_INT2_vect +#elif defined( INT2_vect ) + #define EXTERNAL_INTERRUPT_2_vect INT2_vect +#endif + +#if defined( EXT_INT3_vect ) + #define EXTERNAL_INTERRUPT_3_vect EXT_INT3_vect +#elif defined( INT3_vect ) + #define EXTERNAL_INTERRUPT_3_vect INT3_vect +#endif + +#if defined( EXT_INT4_vect ) + #define EXTERNAL_INTERRUPT_4_vect EXT_INT4_vect +#elif defined( INT4_vect ) + #define EXTERNAL_INTERRUPT_4_vect INT4_vect +#endif + +#if defined( EXT_INT5_vect ) + #define EXTERNAL_INTERRUPT_5_vect EXT_INT5_vect +#elif defined( INT5_vect ) + #define EXTERNAL_INTERRUPT_5_vect INT5_vect +#endif + +#if defined( EXT_INT6_vect ) + #define EXTERNAL_INTERRUPT_6_vect EXT_INT6_vect +#elif defined( INT6_vect ) + #define EXTERNAL_INTERRUPT_6_vect INT6_vect +#endif + +#if defined( EXT_INT7_vect ) + #define EXTERNAL_INTERRUPT_7_vect EXT_INT7_vect +#elif defined( INT7_vect ) + #define EXTERNAL_INTERRUPT_7_vect INT7_vect +#endif + +#if defined( EXT_INT8_vect ) + #define EXTERNAL_INTERRUPT_8_vect EXT_INT8_vect +#elif defined( INT8_vect ) + #define EXTERNAL_INTERRUPT_8_vect INT8_vect +#endif + +#if defined( EXT_INT9_vect ) + #define EXTERNAL_INTERRUPT_9_vect EXT_INT9_vect +#elif defined( INT9_vect ) + #define EXTERNAL_INTERRUPT_9_vect INT9_vect +#endif + +#if defined( EXTERNAL_INTERRUPT_9_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (10) +#elif defined( EXTERNAL_INTERRUPT_8_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (9) +#elif defined( EXTERNAL_INTERRUPT_7_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (8) +#elif defined( EXTERNAL_INTERRUPT_6_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (7) +#elif defined( EXTERNAL_INTERRUPT_5_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (6) +#elif defined( EXTERNAL_INTERRUPT_4_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (5) +#elif defined( EXTERNAL_INTERRUPT_3_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (4) +#elif defined( EXTERNAL_INTERRUPT_2_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (3) +#elif defined( EXTERNAL_INTERRUPT_1_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (2) +#elif defined( EXTERNAL_INTERRUPT_0_vect ) + #define NUMBER_EXTERNAL_INTERRUPTS (1) +#else + #define NUMBER_EXTERNAL_INTERRUPTS (0) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 1 + #define EXTERNAL_INTERRUPT_0 (0) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 2 + #define EXTERNAL_INTERRUPT_1 (1) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 3 + #define EXTERNAL_INTERRUPT_2 (2) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 4 + #define EXTERNAL_INTERRUPT_3 (3) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 5 + #define EXTERNAL_INTERRUPT_4 (4) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 6 + #define EXTERNAL_INTERRUPT_5 (5) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 7 + #define EXTERNAL_INTERRUPT_6 (6) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 8 + #define EXTERNAL_INTERRUPT_7 (7) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 9 + #define EXTERNAL_INTERRUPT_8 (8) +#endif + +#if NUMBER_EXTERNAL_INTERRUPTS >= 10 + #define EXTERNAL_INTERRUPT_9 (9) +#endif + +typedef void (*voidFuncPtr)(void); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif diff --git a/hardware/digistump/avr/cores/tiny/wiring_pulse.c b/hardware/digistump/avr/cores/tiny/wiring_pulse.c new file mode 100644 index 0000000..0d96886 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/wiring_pulse.c @@ -0,0 +1,69 @@ +/* + wiring_pulse.c - pulseIn() function + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $ +*/ + +#include "wiring_private.h" +#include "pins_arduino.h" + +/* Measures the length (in microseconds) of a pulse on the pin; state is HIGH + * or LOW, the type of pulse to measure. Works on pulses from 2-3 microseconds + * to 3 minutes in length, but must be called at least a few dozen microseconds + * before the start of the pulse. */ +unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout) +{ + // cache the port and bit of the pin in order to speed up the + // pulse width measuring loop and achieve finer resolution. calling + // digitalRead() instead yields much coarser resolution. + uint8_t bit = digitalPinToBitMask(pin); + uint8_t port = digitalPinToPort(pin); + uint8_t stateMask = (state ? bit : 0); + unsigned long width = 0; // keep initialization out of time critical area + + // convert the timeout from microseconds to a number of times through + // the initial loop; it takes 16 clock cycles per iteration. + unsigned long numloops = 0; + unsigned long maxloops = microsecondsToClockCycles(timeout) / 16; + + // wait for any previous pulse to end + while ((*portInputRegister(port) & bit) == stateMask) + if (numloops++ == maxloops) + return 0; + + // wait for the pulse to start + while ((*portInputRegister(port) & bit) != stateMask) + if (numloops++ == maxloops) + return 0; + + // wait for the pulse to stop + while ((*portInputRegister(port) & bit) == stateMask) { + if (numloops++ == maxloops) + return 0; + width++; + } + + // convert the reading to microseconds. The loop has been determined + // to be 20 clock cycles long and have about 16 clocks between the edge + // and the start of the loop. There will be some error introduced by + // the interrupt handlers. + return clockCyclesToMicroseconds(width * 21 + 16); +} diff --git a/hardware/digistump/avr/cores/tiny/wiring_shift.c b/hardware/digistump/avr/cores/tiny/wiring_shift.c new file mode 100644 index 0000000..cfe7867 --- /dev/null +++ b/hardware/digistump/avr/cores/tiny/wiring_shift.c @@ -0,0 +1,55 @@ +/* + wiring_shift.c - shiftOut() function + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2005-2006 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.c 248 2007-02-03 15:36:30Z mellis $ +*/ + +#include "wiring_private.h" + +uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) { + uint8_t value = 0; + uint8_t i; + + for (i = 0; i < 8; ++i) { + digitalWrite(clockPin, HIGH); + if (bitOrder == LSBFIRST) + value |= digitalRead(dataPin) << i; + else + value |= digitalRead(dataPin) << (7 - i); + digitalWrite(clockPin, LOW); + } + return value; +} + +void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t val) +{ + uint8_t i; + + for (i = 0; i < 8; i++) { + if (bitOrder == LSBFIRST) + digitalWrite(dataPin, !!(val & (1 << i))); + else + digitalWrite(dataPin, !!(val & (1 << (7 - i)))); + + digitalWrite(clockPin, HIGH); + digitalWrite(clockPin, LOW); + } +} diff --git a/hardware/digistump/avr/libraries/Adafruit_NeoPixel/Adafruit_NeoPixel.cpp b/hardware/digistump/avr/libraries/Adafruit_NeoPixel/Adafruit_NeoPixel.cpp new file mode 100644 index 0000000..00cf9ca --- /dev/null +++ b/hardware/digistump/avr/libraries/Adafruit_NeoPixel/Adafruit_NeoPixel.cpp @@ -0,0 +1,937 @@ +/*------------------------------------------------------------------------- + Arduino library to control a wide variety of WS2811- and WS2812-based RGB + LED devices such as Adafruit FLORA RGB Smart Pixels and NeoPixel strips. + Currently handles 400 and 800 KHz bitstreams on 8, 12 and 16 MHz ATmega + MCUs, with LEDs wired for RGB or GRB color order. 8 MHz MCUs provide + output on PORTB and PORTD, while 16 MHz chips can handle most output pins + (possible exception with upper PORT registers on the Arduino Mega). + + Written by Phil Burgess / Paint Your Dragon for Adafruit Industries, + contributions by PJRC and other members of the open source community. + + Adafruit invests time and resources providing this open source code, + please support Adafruit and open-source hardware by purchasing products + from Adafruit! + + ------------------------------------------------------------------------- + This file is part of the Adafruit NeoPixel library. + + NeoPixel is free software: you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as + published by the Free Software Foundation, either version 3 of + the License, or (at your option) any later version. + + NeoPixel is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with NeoPixel. If not, see + . + -------------------------------------------------------------------------*/ + +#include "Adafruit_NeoPixel.h" + +Adafruit_NeoPixel::Adafruit_NeoPixel(uint16_t n, uint8_t p, uint8_t t) : numLEDs(n), numBytes(n * 3), pin(p), pixels(NULL) + ,type(t), brightness(0), endTime(0) +#ifdef __AVR__ + ,port(portOutputRegister(digitalPinToPort(p))), + pinMask(digitalPinToBitMask(p)) +#endif +{ + if((pixels = (uint8_t *)malloc(numBytes))) { + memset(pixels, 0, numBytes); + } + if(t & NEO_GRB) { // GRB vs RGB; might add others if needed + rOffset = 1; + gOffset = 0; + bOffset = 2; + } else if (t & NEO_BRG) { + rOffset = 1; + gOffset = 2; + bOffset = 0; + } else { + rOffset = 0; + gOffset = 1; + bOffset = 2; + } + +} + +Adafruit_NeoPixel::~Adafruit_NeoPixel() { + if(pixels) free(pixels); + pinMode(pin, INPUT); +} + +void Adafruit_NeoPixel::begin(void) { + pinMode(pin, OUTPUT); + digitalWrite(pin, LOW); +} + +void Adafruit_NeoPixel::show(void) { + + if(!pixels) return; + + // Data latch = 50+ microsecond pause in the output stream. Rather than + // put a delay at the end of the function, the ending time is noted and + // the function will simply hold off (if needed) on issuing the + // subsequent round of data until the latch time has elapsed. This + // allows the mainline code to start generating the next frame of data + // rather than stalling for the latch. + while(!canShow()); + // endTime is a private member (rather than global var) so that mutliple + // instances on different pins can be quickly issued in succession (each + // instance doesn't delay the next). + + // In order to make this code runtime-configurable to work with any pin, + // SBI/CBI instructions are eschewed in favor of full PORT writes via the + // OUT or ST instructions. It relies on two facts: that peripheral + // functions (such as PWM) take precedence on output pins, so our PORT- + // wide writes won't interfere, and that interrupts are globally disabled + // while data is being issued to the LEDs, so no other code will be + // accessing the PORT. The code takes an initial 'snapshot' of the PORT + // state, computes 'pin high' and 'pin low' values, and writes these back + // to the PORT register as needed. + + noInterrupts(); // Need 100% focus on instruction timing + +#ifdef __AVR__ + + volatile uint16_t + i = numBytes; // Loop counter + volatile uint8_t + *ptr = pixels, // Pointer to next byte + b = *ptr++, // Current byte value + hi, // PORT w/output bit set high + lo; // PORT w/output bit set low + + // Hand-tuned assembly code issues data to the LED drivers at a specific + // rate. There's separate code for different CPU speeds (8, 12, 16 MHz) + // for both the WS2811 (400 KHz) and WS2812 (800 KHz) drivers. The + // datastream timing for the LED drivers allows a little wiggle room each + // way (listed in the datasheets), so the conditions for compiling each + // case are set up for a range of frequencies rather than just the exact + // 8, 12 or 16 MHz values, permitting use with some close-but-not-spot-on + // devices (e.g. 16.5 MHz DigiSpark). The ranges were arrived at based + // on the datasheet figures and have not been extensively tested outside + // the canonical 8/12/16 MHz speeds; there's no guarantee these will work + // close to the extremes (or possibly they could be pushed further). + // Keep in mind only one CPU speed case actually gets compiled; the + // resulting program isn't as massive as it might look from source here. + +// 8 MHz(ish) AVR --------------------------------------------------------- +#if (F_CPU >= 7400000UL) && (F_CPU <= 9500000UL) + +#ifdef NEO_KHZ400 + if((type & NEO_SPDMASK) == NEO_KHZ800) { // 800 KHz bitstream +#endif + + volatile uint8_t n1, n2 = 0; // First, next bits out + + // Squeezing an 800 KHz stream out of an 8 MHz chip requires code + // specific to each PORT register. At present this is only written + // to work with pins on PORTD or PORTB, the most likely use case -- + // this covers all the pins on the Adafruit Flora and the bulk of + // digital pins on the Arduino Pro 8 MHz (keep in mind, this code + // doesn't even get compiled for 16 MHz boards like the Uno, Mega, + // Leonardo, etc., so don't bother extending this out of hand). + // Additional PORTs could be added if you really need them, just + // duplicate the else and loop and change the PORT. Each add'l + // PORT will require about 150(ish) bytes of program space. + + // 10 instruction clocks per bit: HHxxxxxLLL + // OUT instructions: ^ ^ ^ (T=0,2,7) + +#ifdef PORTD // PORTD isn't present on ATtiny85, etc. + + if(port == &PORTD) { + + hi = PORTD | pinMask; + lo = PORTD & ~pinMask; + n1 = lo; + if(b & 0x80) n1 = hi; + + // Dirty trick: RJMPs proceeding to the next instruction are used + // to delay two clock cycles in one instruction word (rather than + // using two NOPs). This was necessary in order to squeeze the + // loop down to exactly 64 words -- the maximum possible for a + // relative branch. + + asm volatile( + "headD:" "\n\t" // Clk Pseudocode + // Bit 7: + "out %[port] , %[hi]" "\n\t" // 1 PORT = hi + "mov %[n2] , %[lo]" "\n\t" // 1 n2 = lo + "out %[port] , %[n1]" "\n\t" // 1 PORT = n1 + "rjmp .+0" "\n\t" // 2 nop nop + "sbrc %[byte] , 6" "\n\t" // 1-2 if(b & 0x40) + "mov %[n2] , %[hi]" "\n\t" // 0-1 n2 = hi + "out %[port] , %[lo]" "\n\t" // 1 PORT = lo + "rjmp .+0" "\n\t" // 2 nop nop + // Bit 6: + "out %[port] , %[hi]" "\n\t" // 1 PORT = hi + "mov %[n1] , %[lo]" "\n\t" // 1 n1 = lo + "out %[port] , %[n2]" "\n\t" // 1 PORT = n2 + "rjmp .+0" "\n\t" // 2 nop nop + "sbrc %[byte] , 5" "\n\t" // 1-2 if(b & 0x20) + "mov %[n1] , %[hi]" "\n\t" // 0-1 n1 = hi + "out %[port] , %[lo]" "\n\t" // 1 PORT = lo + "rjmp .+0" "\n\t" // 2 nop nop + // Bit 5: + "out %[port] , %[hi]" "\n\t" // 1 PORT = hi + "mov %[n2] , %[lo]" "\n\t" // 1 n2 = lo + "out %[port] , %[n1]" "\n\t" // 1 PORT = n1 + "rjmp .+0" "\n\t" // 2 nop nop + "sbrc %[byte] , 4" "\n\t" // 1-2 if(b & 0x10) + "mov %[n2] , %[hi]" "\n\t" // 0-1 n2 = hi + "out %[port] , %[lo]" "\n\t" // 1 PORT = lo + "rjmp .+0" "\n\t" // 2 nop nop + // Bit 4: + "out %[port] , %[hi]" "\n\t" // 1 PORT = hi + "mov %[n1] , %[lo]" "\n\t" // 1 n1 = lo + "out %[port] , %[n2]" "\n\t" // 1 PORT = n2 + "rjmp .+0" "\n\t" // 2 nop nop + "sbrc %[byte] , 3" "\n\t" // 1-2 if(b & 0x08) + "mov %[n1] , %[hi]" "\n\t" // 0-1 n1 = hi + "out %[port] , %[lo]" "\n\t" // 1 PORT = lo + "rjmp .+0" "\n\t" // 2 nop nop + // Bit 3: + "out %[port] , %[hi]" "\n\t" // 1 PORT = hi + "mov %[n2] , %[lo]" "\n\t" // 1 n2 = lo + "out %[port] , %[n1]" "\n\t" // 1 PORT = n1 + "rjmp .+0" "\n\t" // 2 nop nop + "sbrc %[byte] , 2" "\n\t" // 1-2 if(b & 0x04) + "mov %[n2] , %[hi]" "\n\t" // 0-1 n2 = hi + "out %[port] , %[lo]" "\n\t" // 1 PORT = lo + "rjmp .+0" "\n\t" // 2 nop nop + // Bit 2: + "out %[port] , %[hi]" "\n\t" // 1 PORT = hi + "mov %[n1] , %[lo]" "\n\t" // 1 n1 = lo + "out %[port] , %[n2]" "\n\t" // 1 PORT = n2 + "rjmp .+0" "\n\t" // 2 nop nop + "sbrc %[byte] , 1" "\n\t" // 1-2 if(b & 0x02) + "mov %[n1] , %[hi]" "\n\t" // 0-1 n1 = hi + "out %[port] , %[lo]" "\n\t" // 1 PORT = lo + "rjmp .+0" "\n\t" // 2 nop nop + // Bit 1: + "out %[port] , %[hi]" "\n\t" // 1 PORT = hi + "mov %[n2] , %[lo]" "\n\t" // 1 n2 = lo + "out %[port] , %[n1]" "\n\t" // 1 PORT = n1 + "rjmp .+0" "\n\t" // 2 nop nop + "sbrc %[byte] , 0" "\n\t" // 1-2 if(b & 0x01) + "mov %[n2] , %[hi]" "\n\t" // 0-1 n2 = hi + "out %[port] , %[lo]" "\n\t" // 1 PORT = lo + "sbiw %[count], 1" "\n\t" // 2 i-- (don't act on Z flag yet) + // Bit 0: + "out %[port] , %[hi]" "\n\t" // 1 PORT = hi + "mov %[n1] , %[lo]" "\n\t" // 1 n1 = lo + "out %[port] , %[n2]" "\n\t" // 1 PORT = n2 + "ld %[byte] , %a[ptr]+" "\n\t" // 2 b = *ptr++ + "sbrc %[byte] , 7" "\n\t" // 1-2 if(b & 0x80) + "mov %[n1] , %[hi]" "\n\t" // 0-1 n1 = hi + "out %[port] , %[lo]" "\n\t" // 1 PORT = lo + "brne headD" "\n" // 2 while(i) (Z flag set above) + : [byte] "+r" (b), + [n1] "+r" (n1), + [n2] "+r" (n2), + [count] "+w" (i) + : [port] "I" (_SFR_IO_ADDR(PORTD)), + [ptr] "e" (ptr), + [hi] "r" (hi), + [lo] "r" (lo)); + + } else if(port == &PORTB) { + +#endif // PORTD + + // Same as above, just switched to PORTB and stripped of comments. + hi = PORTB | pinMask; + lo = PORTB & ~pinMask; + n1 = lo; + if(b & 0x80) n1 = hi; + + asm volatile( + "headB:" "\n\t" + "out %[port] , %[hi]" "\n\t" + "mov %[n2] , %[lo]" "\n\t" + "out %[port] , %[n1]" "\n\t" + "rjmp .+0" "\n\t" + "sbrc %[byte] , 6" "\n\t" + "mov %[n2] , %[hi]" "\n\t" + "out %[port] , %[lo]" "\n\t" + "rjmp .+0" "\n\t" + "out %[port] , %[hi]" "\n\t" + "mov %[n1] , %[lo]" "\n\t" + "out %[port] , %[n2]" "\n\t" + "rjmp .+0" "\n\t" + "sbrc %[byte] , 5" "\n\t" + "mov %[n1] , %[hi]" "\n\t" + "out %[port] , %[lo]" "\n\t" + "rjmp .+0" "\n\t" + "out %[port] , %[hi]" "\n\t" + "mov %[n2] , %[lo]" "\n\t" + "out %[port] , %[n1]" "\n\t" + "rjmp .+0" "\n\t" + "sbrc %[byte] , 4" "\n\t" + "mov %[n2] , %[hi]" "\n\t" + "out %[port] , %[lo]" "\n\t" + "rjmp .+0" "\n\t" + "out %[port] , %[hi]" "\n\t" + "mov %[n1] , %[lo]" "\n\t" + "out %[port] , %[n2]" "\n\t" + "rjmp .+0" "\n\t" + "sbrc %[byte] , 3" "\n\t" + "mov %[n1] , %[hi]" "\n\t" + "out %[port] , %[lo]" "\n\t" + "rjmp .+0" "\n\t" + "out %[port] , %[hi]" "\n\t" + "mov %[n2] , %[lo]" "\n\t" + "out %[port] , %[n1]" "\n\t" + "rjmp .+0" "\n\t" + "sbrc %[byte] , 2" "\n\t" + "mov %[n2] , %[hi]" "\n\t" + "out %[port] , %[lo]" "\n\t" + "rjmp .+0" "\n\t" + "out %[port] , %[hi]" "\n\t" + "mov %[n1] , %[lo]" "\n\t" + "out %[port] , %[n2]" "\n\t" + "rjmp .+0" "\n\t" + "sbrc %[byte] , 1" "\n\t" + "mov %[n1] , %[hi]" "\n\t" + "out %[port] , %[lo]" "\n\t" + "rjmp .+0" "\n\t" + "out %[port] , %[hi]" "\n\t" + "mov %[n2] , %[lo]" "\n\t" + "out %[port] , %[n1]" "\n\t" + "rjmp .+0" "\n\t" + "sbrc %[byte] , 0" "\n\t" + "mov %[n2] , %[hi]" "\n\t" + "out %[port] , %[lo]" "\n\t" + "sbiw %[count], 1" "\n\t" + "out %[port] , %[hi]" "\n\t" + "mov %[n1] , %[lo]" "\n\t" + "out %[port] , %[n2]" "\n\t" + "ld %[byte] , %a[ptr]+" "\n\t" + "sbrc %[byte] , 7" "\n\t" + "mov %[n1] , %[hi]" "\n\t" + "out %[port] , %[lo]" "\n\t" + "brne headB" "\n" + : [byte] "+r" (b), [n1] "+r" (n1), [n2] "+r" (n2), [count] "+w" (i) + : [port] "I" (_SFR_IO_ADDR(PORTB)), [ptr] "e" (ptr), [hi] "r" (hi), + [lo] "r" (lo)); + +#ifdef PORTD + } // endif PORTB +#endif + +#ifdef NEO_KHZ400 + } else { // end 800 KHz, do 400 KHz + + // Timing is more relaxed; unrolling the inner loop for each bit is + // not necessary. Still using the peculiar RJMPs as 2X NOPs, not out + // of need but just to trim the code size down a little. + // This 400-KHz-datastream-on-8-MHz-CPU code is not quite identical + // to the 800-on-16 code later -- the hi/lo timing between WS2811 and + // WS2812 is not simply a 2:1 scale! + + // 20 inst. clocks per bit: HHHHxxxxxxLLLLLLLLLL + // ST instructions: ^ ^ ^ (T=0,4,10) + + volatile uint8_t next, bit; + + hi = *port | pinMask; + lo = *port & ~pinMask; + next = lo; + bit = 8; + + asm volatile( + "head20:" "\n\t" // Clk Pseudocode (T = 0) + "st %a[port], %[hi]" "\n\t" // 2 PORT = hi (T = 2) + "sbrc %[byte] , 7" "\n\t" // 1-2 if(b & 128) + "mov %[next], %[hi]" "\n\t" // 0-1 next = hi (T = 4) + "st %a[port], %[next]" "\n\t" // 2 PORT = next (T = 6) + "mov %[next] , %[lo]" "\n\t" // 1 next = lo (T = 7) + "dec %[bit]" "\n\t" // 1 bit-- (T = 8) + "breq nextbyte20" "\n\t" // 1-2 if(bit == 0) + "rol %[byte]" "\n\t" // 1 b <<= 1 (T = 10) + "st %a[port], %[lo]" "\n\t" // 2 PORT = lo (T = 12) + "rjmp .+0" "\n\t" // 2 nop nop (T = 14) + "rjmp .+0" "\n\t" // 2 nop nop (T = 16) + "rjmp .+0" "\n\t" // 2 nop nop (T = 18) + "rjmp head20" "\n\t" // 2 -> head20 (next bit out) + "nextbyte20:" "\n\t" // (T = 10) + "st %a[port], %[lo]" "\n\t" // 2 PORT = lo (T = 12) + "nop" "\n\t" // 1 nop (T = 13) + "ldi %[bit] , 8" "\n\t" // 1 bit = 8 (T = 14) + "ld %[byte] , %a[ptr]+" "\n\t" // 2 b = *ptr++ (T = 16) + "sbiw %[count], 1" "\n\t" // 2 i-- (T = 18) + "brne head20" "\n" // 2 if(i != 0) -> (next byte) + : [port] "+e" (port), + [byte] "+r" (b), + [bit] "+r" (bit), + [next] "+r" (next), + [count] "+w" (i) + : [hi] "r" (hi), + [lo] "r" (lo), + [ptr] "e" (ptr)); + } +#endif + +// 12 MHz(ish) AVR -------------------------------------------------------- +#elif (F_CPU >= 11100000UL) && (F_CPU <= 14300000UL) + +#ifdef NEO_KHZ400 + if((type & NEO_SPDMASK) == NEO_KHZ800) { // 800 KHz bitstream +#endif + + // In the 12 MHz case, an optimized 800 KHz datastream (no dead time + // between bytes) requires a PORT-specific loop similar to the 8 MHz + // code (but a little more relaxed in this case). + + // 15 instruction clocks per bit: HHHHxxxxxxLLLLL + // OUT instructions: ^ ^ ^ (T=0,4,10) + + volatile uint8_t next; + +#ifdef PORTD + + if(port == &PORTD) { + + hi = PORTD | pinMask; + lo = PORTD & ~pinMask; + next = lo; + if(b & 0x80) next = hi; + + // Don't "optimize" the OUT calls into the bitTime subroutine; + // we're exploiting the RCALL and RET as 3- and 4-cycle NOPs! + asm volatile( + "headD:" "\n\t" // (T = 0) + "out %[port], %[hi]" "\n\t" // (T = 1) + "rcall bitTimeD" "\n\t" // Bit 7 (T = 15) + "out %[port], %[hi]" "\n\t" + "rcall bitTimeD" "\n\t" // Bit 6 + "out %[port], %[hi]" "\n\t" + "rcall bitTimeD" "\n\t" // Bit 5 + "out %[port], %[hi]" "\n\t" + "rcall bitTimeD" "\n\t" // Bit 4 + "out %[port], %[hi]" "\n\t" + "rcall bitTimeD" "\n\t" // Bit 3 + "out %[port], %[hi]" "\n\t" + "rcall bitTimeD" "\n\t" // Bit 2 + "out %[port], %[hi]" "\n\t" + "rcall bitTimeD" "\n\t" // Bit 1 + // Bit 0: + "out %[port] , %[hi]" "\n\t" // 1 PORT = hi (T = 1) + "rjmp .+0" "\n\t" // 2 nop nop (T = 3) + "ld %[byte] , %a[ptr]+" "\n\t" // 2 b = *ptr++ (T = 5) + "out %[port] , %[next]" "\n\t" // 1 PORT = next (T = 6) + "mov %[next] , %[lo]" "\n\t" // 1 next = lo (T = 7) + "sbrc %[byte] , 7" "\n\t" // 1-2 if(b & 0x80) (T = 8) + "mov %[next] , %[hi]" "\n\t" // 0-1 next = hi (T = 9) + "nop" "\n\t" // 1 (T = 10) + "out %[port] , %[lo]" "\n\t" // 1 PORT = lo (T = 11) + "sbiw %[count], 1" "\n\t" // 2 i-- (T = 13) + "brne headD" "\n\t" // 2 if(i != 0) -> (next byte) + "rjmp doneD" "\n\t" + "bitTimeD:" "\n\t" // nop nop nop (T = 4) + "out %[port], %[next]" "\n\t" // 1 PORT = next (T = 5) + "mov %[next], %[lo]" "\n\t" // 1 next = lo (T = 6) + "rol %[byte]" "\n\t" // 1 b <<= 1 (T = 7) + "sbrc %[byte], 7" "\n\t" // 1-2 if(b & 0x80) (T = 8) + "mov %[next], %[hi]" "\n\t" // 0-1 next = hi (T = 9) + "nop" "\n\t" // 1 (T = 10) + "out %[port], %[lo]" "\n\t" // 1 PORT = lo (T = 11) + "ret" "\n\t" // 4 nop nop nop nop (T = 15) + "doneD:" "\n" + : [byte] "+r" (b), + [next] "+r" (next), + [count] "+w" (i) + : [port] "I" (_SFR_IO_ADDR(PORTD)), + [ptr] "e" (ptr), + [hi] "r" (hi), + [lo] "r" (lo)); + + } else if(port == &PORTB) { + +#endif // PORTD + + hi = PORTB | pinMask; + lo = PORTB & ~pinMask; + next = lo; + if(b & 0x80) next = hi; + + // Same as above, just set for PORTB & stripped of comments + asm volatile( + "headB:" "\n\t" + "out %[port], %[hi]" "\n\t" + "rcall bitTimeB" "\n\t" + "out %[port], %[hi]" "\n\t" + "rcall bitTimeB" "\n\t" + "out %[port], %[hi]" "\n\t" + "rcall bitTimeB" "\n\t" + "out %[port], %[hi]" "\n\t" + "rcall bitTimeB" "\n\t" + "out %[port], %[hi]" "\n\t" + "rcall bitTimeB" "\n\t" + "out %[port], %[hi]" "\n\t" + "rcall bitTimeB" "\n\t" + "out %[port], %[hi]" "\n\t" + "rcall bitTimeB" "\n\t" + "out %[port] , %[hi]" "\n\t" + "rjmp .+0" "\n\t" + "ld %[byte] , %a[ptr]+" "\n\t" + "out %[port] , %[next]" "\n\t" + "mov %[next] , %[lo]" "\n\t" + "sbrc %[byte] , 7" "\n\t" + "mov %[next] , %[hi]" "\n\t" + "nop" "\n\t" + "out %[port] , %[lo]" "\n\t" + "sbiw %[count], 1" "\n\t" + "brne headB" "\n\t" + "rjmp doneB" "\n\t" + "bitTimeB:" "\n\t" + "out %[port], %[next]" "\n\t" + "mov %[next], %[lo]" "\n\t" + "rol %[byte]" "\n\t" + "sbrc %[byte], 7" "\n\t" + "mov %[next], %[hi]" "\n\t" + "nop" "\n\t" + "out %[port], %[lo]" "\n\t" + "ret" "\n\t" + "doneB:" "\n" + : [byte] "+r" (b), [next] "+r" (next), [count] "+w" (i) + : [port] "I" (_SFR_IO_ADDR(PORTB)), [ptr] "e" (ptr), [hi] "r" (hi), + [lo] "r" (lo)); + +#ifdef PORTD + } +#endif + +#ifdef NEO_KHZ400 + } else { // 400 KHz + + // 30 instruction clocks per bit: HHHHHHxxxxxxxxxLLLLLLLLLLLLLLL + // ST instructions: ^ ^ ^ (T=0,6,15) + + volatile uint8_t next, bit; + + hi = *port | pinMask; + lo = *port & ~pinMask; + next = lo; + bit = 8; + + asm volatile( + "head30:" "\n\t" // Clk Pseudocode (T = 0) + "st %a[port], %[hi]" "\n\t" // 2 PORT = hi (T = 2) + "sbrc %[byte] , 7" "\n\t" // 1-2 if(b & 128) + "mov %[next], %[hi]" "\n\t" // 0-1 next = hi (T = 4) + "rjmp .+0" "\n\t" // 2 nop nop (T = 6) + "st %a[port], %[next]" "\n\t" // 2 PORT = next (T = 8) + "rjmp .+0" "\n\t" // 2 nop nop (T = 10) + "rjmp .+0" "\n\t" // 2 nop nop (T = 12) + "rjmp .+0" "\n\t" // 2 nop nop (T = 14) + "nop" "\n\t" // 1 nop (T = 15) + "st %a[port], %[lo]" "\n\t" // 2 PORT = lo (T = 17) + "rjmp .+0" "\n\t" // 2 nop nop (T = 19) + "dec %[bit]" "\n\t" // 1 bit-- (T = 20) + "breq nextbyte30" "\n\t" // 1-2 if(bit == 0) + "rol %[byte]" "\n\t" // 1 b <<= 1 (T = 22) + "rjmp .+0" "\n\t" // 2 nop nop (T = 24) + "rjmp .+0" "\n\t" // 2 nop nop (T = 26) + "rjmp .+0" "\n\t" // 2 nop nop (T = 28) + "rjmp head30" "\n\t" // 2 -> head30 (next bit out) + "nextbyte30:" "\n\t" // (T = 22) + "nop" "\n\t" // 1 nop (T = 23) + "ldi %[bit] , 8" "\n\t" // 1 bit = 8 (T = 24) + "ld %[byte] , %a[ptr]+" "\n\t" // 2 b = *ptr++ (T = 26) + "sbiw %[count], 1" "\n\t" // 2 i-- (T = 28) + "brne head30" "\n" // 1-2 if(i != 0) -> (next byte) + : [port] "+e" (port), + [byte] "+r" (b), + [bit] "+r" (bit), + [next] "+r" (next), + [count] "+w" (i) + : [hi] "r" (hi), + [lo] "r" (lo), + [ptr] "e" (ptr)); + } +#endif + +// 16 MHz(ish) AVR -------------------------------------------------------- +#elif (F_CPU >= 15400000UL) && (F_CPU <= 19000000L) + +#ifdef NEO_KHZ400 + if((type & NEO_SPDMASK) == NEO_KHZ800) { // 800 KHz bitstream +#endif + + // WS2811 and WS2812 have different hi/lo duty cycles; this is + // similar but NOT an exact copy of the prior 400-on-8 code. + + // 20 inst. clocks per bit: HHHHHxxxxxxxxLLLLLLL + // ST instructions: ^ ^ ^ (T=0,5,13) + + volatile uint8_t next, bit; + + hi = *port | pinMask; + lo = *port & ~pinMask; + next = lo; + bit = 8; + + asm volatile( + "head20:" "\n\t" // Clk Pseudocode (T = 0) + "st %a[port], %[hi]" "\n\t" // 2 PORT = hi (T = 2) + "sbrc %[byte], 7" "\n\t" // 1-2 if(b & 128) + "mov %[next], %[hi]" "\n\t" // 0-1 next = hi (T = 4) + "dec %[bit]" "\n\t" // 1 bit-- (T = 5) + "st %a[port], %[next]" "\n\t" // 2 PORT = next (T = 7) + "mov %[next] , %[lo]" "\n\t" // 1 next = lo (T = 8) + "breq nextbyte20" "\n\t" // 1-2 if(bit == 0) (from dec above) + "rol %[byte]" "\n\t" // 1 b <<= 1 (T = 10) + "rjmp .+0" "\n\t" // 2 nop nop (T = 12) + "nop" "\n\t" // 1 nop (T = 13) + "st %a[port], %[lo]" "\n\t" // 2 PORT = lo (T = 15) + "nop" "\n\t" // 1 nop (T = 16) + "rjmp .+0" "\n\t" // 2 nop nop (T = 18) + "rjmp head20" "\n\t" // 2 -> head20 (next bit out) + "nextbyte20:" "\n\t" // (T = 10) + "ldi %[bit] , 8" "\n\t" // 1 bit = 8 (T = 11) + "ld %[byte] , %a[ptr]+" "\n\t" // 2 b = *ptr++ (T = 13) + "st %a[port], %[lo]" "\n\t" // 2 PORT = lo (T = 15) + "nop" "\n\t" // 1 nop (T = 16) + "sbiw %[count], 1" "\n\t" // 2 i-- (T = 18) + "brne head20" "\n" // 2 if(i != 0) -> (next byte) + : [port] "+e" (port), + [byte] "+r" (b), + [bit] "+r" (bit), + [next] "+r" (next), + [count] "+w" (i) + : [ptr] "e" (ptr), + [hi] "r" (hi), + [lo] "r" (lo)); + +#ifdef NEO_KHZ400 + } else { // 400 KHz + + // The 400 KHz clock on 16 MHz MCU is the most 'relaxed' version. + + // 40 inst. clocks per bit: HHHHHHHHxxxxxxxxxxxxLLLLLLLLLLLLLLLLLLLL + // ST instructions: ^ ^ ^ (T=0,8,20) + + volatile uint8_t next, bit; + + hi = *port | pinMask; + lo = *port & ~pinMask; + next = lo; + bit = 8; + + asm volatile( + "head40:" "\n\t" // Clk Pseudocode (T = 0) + "st %a[port], %[hi]" "\n\t" // 2 PORT = hi (T = 2) + "sbrc %[byte] , 7" "\n\t" // 1-2 if(b & 128) + "mov %[next] , %[hi]" "\n\t" // 0-1 next = hi (T = 4) + "rjmp .+0" "\n\t" // 2 nop nop (T = 6) + "rjmp .+0" "\n\t" // 2 nop nop (T = 8) + "st %a[port], %[next]" "\n\t" // 2 PORT = next (T = 10) + "rjmp .+0" "\n\t" // 2 nop nop (T = 12) + "rjmp .+0" "\n\t" // 2 nop nop (T = 14) + "rjmp .+0" "\n\t" // 2 nop nop (T = 16) + "rjmp .+0" "\n\t" // 2 nop nop (T = 18) + "rjmp .+0" "\n\t" // 2 nop nop (T = 20) + "st %a[port], %[lo]" "\n\t" // 2 PORT = lo (T = 22) + "nop" "\n\t" // 1 nop (T = 23) + "mov %[next] , %[lo]" "\n\t" // 1 next = lo (T = 24) + "dec %[bit]" "\n\t" // 1 bit-- (T = 25) + "breq nextbyte40" "\n\t" // 1-2 if(bit == 0) + "rol %[byte]" "\n\t" // 1 b <<= 1 (T = 27) + "nop" "\n\t" // 1 nop (T = 28) + "rjmp .+0" "\n\t" // 2 nop nop (T = 30) + "rjmp .+0" "\n\t" // 2 nop nop (T = 32) + "rjmp .+0" "\n\t" // 2 nop nop (T = 34) + "rjmp .+0" "\n\t" // 2 nop nop (T = 36) + "rjmp .+0" "\n\t" // 2 nop nop (T = 38) + "rjmp head40" "\n\t" // 2 -> head40 (next bit out) + "nextbyte40:" "\n\t" // (T = 27) + "ldi %[bit] , 8" "\n\t" // 1 bit = 8 (T = 28) + "ld %[byte] , %a[ptr]+" "\n\t" // 2 b = *ptr++ (T = 30) + "rjmp .+0" "\n\t" // 2 nop nop (T = 32) + "st %a[port], %[lo]" "\n\t" // 2 PORT = lo (T = 34) + "rjmp .+0" "\n\t" // 2 nop nop (T = 36) + "sbiw %[count], 1" "\n\t" // 2 i-- (T = 38) + "brne head40" "\n" // 1-2 if(i != 0) -> (next byte) + : [port] "+e" (port), + [byte] "+r" (b), + [bit] "+r" (bit), + [next] "+r" (next), + [count] "+w" (i) + : [ptr] "e" (ptr), + [hi] "r" (hi), + [lo] "r" (lo)); + } +#endif + +#else + #error "CPU SPEED NOT SUPPORTED" +#endif + +#elif defined(__arm__) + +#if defined(__MK20DX128__) || defined(__MK20DX256__) // Teensy 3.0 & 3.1 +#define CYCLES_800_T0H (F_CPU / 2500000) +#define CYCLES_800_T1H (F_CPU / 1250000) +#define CYCLES_800 (F_CPU / 800000) +#define CYCLES_400_T0H (F_CPU / 2000000) +#define CYCLES_400_T1H (F_CPU / 833333) +#define CYCLES_400 (F_CPU / 400000) + + uint8_t *p = pixels, + *end = p + numBytes, pix, mask; + volatile uint8_t *set = portSetRegister(pin), + *clr = portClearRegister(pin); + uint32_t cyc; + + ARM_DEMCR |= ARM_DEMCR_TRCENA; + ARM_DWT_CTRL |= ARM_DWT_CTRL_CYCCNTENA; + +#ifdef NEO_KHZ400 + if((type & NEO_SPDMASK) == NEO_KHZ800) { // 800 KHz bitstream +#endif + cyc = ARM_DWT_CYCCNT + CYCLES_800; + while(p < end) { + pix = *p++; + for(mask = 0x80; mask; mask >>= 1) { + while(ARM_DWT_CYCCNT - cyc < CYCLES_800); + cyc = ARM_DWT_CYCCNT; + *set = 1; + if(pix & mask) { + while(ARM_DWT_CYCCNT - cyc < CYCLES_800_T1H); + } else { + while(ARM_DWT_CYCCNT - cyc < CYCLES_800_T0H); + } + *clr = 1; + } + } + while(ARM_DWT_CYCCNT - cyc < CYCLES_800); +#ifdef NEO_KHZ400 + } else { // 400 kHz bitstream + cyc = ARM_DWT_CYCCNT + CYCLES_400; + while(p < end) { + pix = *p++; + for(mask = 0x80; mask; mask >>= 1) { + while(ARM_DWT_CYCCNT - cyc < CYCLES_400); + cyc = ARM_DWT_CYCCNT; + *set = 1; + if(pix & mask) { + while(ARM_DWT_CYCCNT - cyc < CYCLES_400_T1H); + } else { + while(ARM_DWT_CYCCNT - cyc < CYCLES_400_T0H); + } + *clr = 1; + } + } + while(ARM_DWT_CYCCNT - cyc < CYCLES_400); + } +#endif + +#else // Arduino Due + + #define SCALE VARIANT_MCK / 2UL / 1000000UL + #define INST (2UL * F_CPU / VARIANT_MCK) + #define TIME_800_0 ((int)(0.40 * SCALE + 0.5) - (5 * INST)) + #define TIME_800_1 ((int)(0.80 * SCALE + 0.5) - (5 * INST)) + #define PERIOD_800 ((int)(1.25 * SCALE + 0.5) - (5 * INST)) + #define TIME_400_0 ((int)(0.50 * SCALE + 0.5) - (5 * INST)) + #define TIME_400_1 ((int)(1.20 * SCALE + 0.5) - (5 * INST)) + #define PERIOD_400 ((int)(2.50 * SCALE + 0.5) - (5 * INST)) + + int pinMask, time0, time1, period, t; + Pio *port; + volatile WoReg *portSet, *portClear, *timeValue, *timeReset; + uint8_t *p, *end, pix, mask; + + pmc_set_writeprotect(false); + pmc_enable_periph_clk((uint32_t)TC3_IRQn); + TC_Configure(TC1, 0, + TC_CMR_WAVE | TC_CMR_WAVSEL_UP | TC_CMR_TCCLKS_TIMER_CLOCK1); + TC_Start(TC1, 0); + + pinMask = g_APinDescription[pin].ulPin; // Don't 'optimize' these into + port = g_APinDescription[pin].pPort; // declarations above. Want to + portSet = &(port->PIO_SODR); // burn a few cycles after + portClear = &(port->PIO_CODR); // starting timer to minimize + timeValue = &(TC1->TC_CHANNEL[0].TC_CV); // the initial 'while'. + timeReset = &(TC1->TC_CHANNEL[0].TC_CCR); + p = pixels; + end = p + numBytes; + pix = *p++; + mask = 0x80; + +#ifdef NEO_KHZ400 + if((type & NEO_SPDMASK) == NEO_KHZ800) { // 800 KHz bitstream +#endif + time0 = TIME_800_0; + time1 = TIME_800_1; + period = PERIOD_800; +#ifdef NEO_KHZ400 + } else { // 400 KHz bitstream + time0 = TIME_400_0; + time1 = TIME_400_1; + period = PERIOD_400; + } +#endif + + for(t = time0;; t = time0) { + if(pix & mask) t = time1; + while(*timeValue < period); + *portSet = pinMask; + *timeReset = TC_CCR_CLKEN | TC_CCR_SWTRG; + while(*timeValue < t); + *portClear = pinMask; + if(!(mask >>= 1)) { // This 'inside-out' loop logic utilizes + if(p >= end) break; // idle time to minimize inter-byte delays. + pix = *p++; + mask = 0x80; + } + } + while(*timeValue < period); // Wait for last bit + TC_Stop(TC1, 0); + +#endif // end Arduino Due + +#endif // end Architecture select + + interrupts(); + endTime = micros(); // Save EOD time for latch on next call +} + +// Set the output pin number +void Adafruit_NeoPixel::setPin(uint8_t p) { + pinMode(pin, INPUT); + pin = p; + pinMode(p, OUTPUT); + digitalWrite(p, LOW); +#ifdef __AVR__ + port = portOutputRegister(digitalPinToPort(p)); + pinMask = digitalPinToBitMask(p); +#endif +} + +// Set pixel color from separate R,G,B components: +void Adafruit_NeoPixel::setPixelColor( + uint16_t n, uint8_t r, uint8_t g, uint8_t b) { + if(n < numLEDs) { + if(brightness) { // See notes in setBrightness() + r = (r * brightness) >> 8; + g = (g * brightness) >> 8; + b = (b * brightness) >> 8; + } + uint8_t *p = &pixels[n * 3]; + p[rOffset] = r; + p[gOffset] = g; + p[bOffset] = b; + } +} + +// Set pixel color from 'packed' 32-bit RGB color: +void Adafruit_NeoPixel::setPixelColor(uint16_t n, uint32_t c) { + if(n < numLEDs) { + uint8_t + r = (uint8_t)(c >> 16), + g = (uint8_t)(c >> 8), + b = (uint8_t)c; + if(brightness) { // See notes in setBrightness() + r = (r * brightness) >> 8; + g = (g * brightness) >> 8; + b = (b * brightness) >> 8; + } + uint8_t *p = &pixels[n * 3]; + p[rOffset] = r; + p[gOffset] = g; + p[bOffset] = b; + } +} + +// Convert separate R,G,B into packed 32-bit RGB color. +// Packed format is always RGB, regardless of LED strand color order. +uint32_t Adafruit_NeoPixel::Color(uint8_t r, uint8_t g, uint8_t b) { + return ((uint32_t)r << 16) | ((uint32_t)g << 8) | b; +} + +// Query color from previously-set pixel (returns packed 32-bit RGB value) +uint32_t Adafruit_NeoPixel::getPixelColor(uint16_t n) const { + if(n >= numLEDs) { + // Out of bounds, return no color. + return 0; + } + uint8_t *p = &pixels[n * 3]; + uint32_t c = ((uint32_t)p[rOffset] << 16) | + ((uint32_t)p[gOffset] << 8) | + (uint32_t)p[bOffset]; + // Adjust this back up to the true color, as setting a pixel color will + // scale it back down again. + if(brightness) { // See notes in setBrightness() + //Cast the color to a byte array + uint8_t * c_ptr =reinterpret_cast(&c); + c_ptr[0] = (c_ptr[0] << 8)/brightness; + c_ptr[1] = (c_ptr[1] << 8)/brightness; + c_ptr[2] = (c_ptr[2] << 8)/brightness; + } + return c; // Pixel # is out of bounds +} + +// Returns pointer to pixels[] array. Pixel data is stored in device- +// native format and is not translated here. Application will need to be +// aware whether pixels are RGB vs. GRB and handle colors appropriately. +uint8_t *Adafruit_NeoPixel::getPixels(void) const { + return pixels; +} + +uint16_t Adafruit_NeoPixel::numPixels(void) const { + return numLEDs; +} + +// Adjust output brightness; 0=darkest (off), 255=brightest. This does +// NOT immediately affect what's currently displayed on the LEDs. The +// next call to show() will refresh the LEDs at this level. However, +// this process is potentially "lossy," especially when increasing +// brightness. The tight timing in the WS2811/WS2812 code means there +// aren't enough free cycles to perform this scaling on the fly as data +// is issued. So we make a pass through the existing color data in RAM +// and scale it (subsequent graphics commands also work at this +// brightness level). If there's a significant step up in brightness, +// the limited number of steps (quantization) in the old data will be +// quite visible in the re-scaled version. For a non-destructive +// change, you'll need to re-render the full strip data. C'est la vie. +void Adafruit_NeoPixel::setBrightness(uint8_t b) { + // Stored brightness value is different than what's passed. + // This simplifies the actual scaling math later, allowing a fast + // 8x8-bit multiply and taking the MSB. 'brightness' is a uint8_t, + // adding 1 here may (intentionally) roll over...so 0 = max brightness + // (color values are interpreted literally; no scaling), 1 = min + // brightness (off), 255 = just below max brightness. + uint8_t newBrightness = b + 1; + if(newBrightness != brightness) { // Compare against prior value + // Brightness has changed -- re-scale existing data in RAM + uint8_t c, + *ptr = pixels, + oldBrightness = brightness - 1; // De-wrap old brightness value + uint16_t scale; + if(oldBrightness == 0) scale = 0; // Avoid /0 + else if(b == 255) scale = 65535 / oldBrightness; + else scale = (((uint16_t)newBrightness << 8) - 1) / oldBrightness; + for(uint16_t i=0; i> 8; + } + brightness = newBrightness; + } +} + +//Return the brightness value +uint8_t Adafruit_NeoPixel::getBrightness(void) const { + return brightness - 1; +} + +void Adafruit_NeoPixel::clear() { + memset(pixels, 0, numBytes); +} diff --git a/hardware/digistump/avr/libraries/Adafruit_NeoPixel/Adafruit_NeoPixel.h b/hardware/digistump/avr/libraries/Adafruit_NeoPixel/Adafruit_NeoPixel.h new file mode 100644 index 0000000..264c199 --- /dev/null +++ b/hardware/digistump/avr/libraries/Adafruit_NeoPixel/Adafruit_NeoPixel.h @@ -0,0 +1,97 @@ +/*-------------------------------------------------------------------- + This file is part of the Adafruit NeoPixel library. + + NeoPixel is free software: you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as + published by the Free Software Foundation, either version 3 of + the License, or (at your option) any later version. + + NeoPixel is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with NeoPixel. If not, see + . + --------------------------------------------------------------------*/ + +#ifndef ADAFRUIT_NEOPIXEL_H +#define ADAFRUIT_NEOPIXEL_H + +#if (ARDUINO >= 100) + #include +#else + #include + #include +#endif + +// 'type' flags for LED pixels (third parameter to constructor): +#define NEO_RGB 0x00 // Wired for RGB data order +#define NEO_GRB 0x01 // Wired for GRB data order +#define NEO_BRG 0x04 + +#define NEO_COLMASK 0x01 +#define NEO_KHZ800 0x02 // 800 KHz datastream +#define NEO_SPDMASK 0x02 +// Trinket flash space is tight, v1 NeoPixels aren't handled by default. +// Remove the ifndef/endif to add support -- but code will be bigger. +// Conversely, can comment out the #defines to save space on other MCUs. +#ifndef __AVR_ATtiny85__ +#define NEO_KHZ400 0x00 // 400 KHz datastream +#endif + +class Adafruit_NeoPixel { + + public: + + // Constructor: number of LEDs, pin number, LED type + Adafruit_NeoPixel(uint16_t n, uint8_t p=6, uint8_t t=NEO_GRB + NEO_KHZ800); + ~Adafruit_NeoPixel(); + + void + begin(void), + show(void), + setPin(uint8_t p), + setPixelColor(uint16_t n, uint8_t r, uint8_t g, uint8_t b), + setPixelColor(uint16_t n, uint32_t c), + setBrightness(uint8_t), + clear(); + uint8_t + *getPixels(void) const, + getBrightness(void) const; + uint16_t + numPixels(void) const; + static uint32_t + Color(uint8_t r, uint8_t g, uint8_t b); + uint32_t + getPixelColor(uint16_t n) const; + inline bool + canShow(void) { return (micros() - endTime) >= 50L; } + + private: + + const uint16_t + numLEDs, // Number of RGB LEDs in strip + numBytes; // Size of 'pixels' buffer below + uint8_t + pin, // Output pin number + brightness, + *pixels, // Holds LED color values (3 bytes each) + rOffset, // Index of red byte within each 3-byte pixel + gOffset, // Index of green byte + bOffset; // Index of blue byte + const uint8_t + type; // Pixel flags (400 vs 800 KHz, RGB vs GRB color) + uint32_t + endTime; // Latch timing reference +#ifdef __AVR__ + const volatile uint8_t + *port; // Output PORT register + uint8_t + pinMask; // Output PORT bitmask +#endif + +}; + +#endif // ADAFRUIT_NEOPIXEL_H diff --git a/hardware/digistump/avr/libraries/Adafruit_NeoPixel/COPYING b/hardware/digistump/avr/libraries/Adafruit_NeoPixel/COPYING new file mode 100644 index 0000000..7dcf8e8 --- /dev/null +++ b/hardware/digistump/avr/libraries/Adafruit_NeoPixel/COPYING @@ -0,0 +1,794 @@ + + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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Such new +versions will be similar in spirit to the present version, but may +differ in detail to address new problems or concerns. + + Each version is given a distinguishing version number. If the +Library as you received it specifies that a certain numbered version +of the GNU Lesser General Public License "or any later version" +applies to it, you have the option of following the terms and +conditions either of that published version or of any later version +published by the Free Software Foundation. If the Library as you +received it does not specify a version number of the GNU Lesser +General Public License, you may choose any version of the GNU Lesser +General Public License ever published by the Free Software Foundation. + + If the Library as you received it specifies that a proxy can decide +whether future versions of the GNU Lesser General Public License shall +apply, that proxy's public statement of acceptance of any version is +permanent authorization for you to choose that version for the +Library. diff --git a/hardware/digistump/avr/libraries/Adafruit_NeoPixel/README.md b/hardware/digistump/avr/libraries/Adafruit_NeoPixel/README.md new file mode 100644 index 0000000..2eeda47 --- /dev/null +++ b/hardware/digistump/avr/libraries/Adafruit_NeoPixel/README.md @@ -0,0 +1,12 @@ +Adafruit NeoPixel library +========================= + +Arduino library for controlling single-wire-based LED pixels and strip such as the [Adafruit 60 LED/meter Digital LED strip][strip], the [Adafruit FLORA RGB Smart Pixel][flora], the [Adafruit Breadboard-friendly RGB Smart Pixel][pixel], the [Adafruit NeoPixel Stick][stick], and the [Adafruit NeoPixel Shield][shield]. + +After downloading, rename folder to 'Adafruit_NeoPixel' and install in Arduino Libraries folder. Restart Arduino IDE, then open File->Sketchbook->Library->Adafruit_NeoPixel->strandtest sketch. + +[flora]: http://adafruit.com/products/1060 +[strip]: http://adafruit.com/products/1138 +[pixel]: http://adafruit.com/products/1312 +[stick]: http://adafruit.com/products/1426 +[shield]: http://adafruit.com/products/1430 diff --git a/hardware/digistump/avr/libraries/Adafruit_NeoPixel/examples/buttoncycler/buttoncycler.ino b/hardware/digistump/avr/libraries/Adafruit_NeoPixel/examples/buttoncycler/buttoncycler.ino new file mode 100644 index 0000000..45d9c6a --- /dev/null +++ b/hardware/digistump/avr/libraries/Adafruit_NeoPixel/examples/buttoncycler/buttoncycler.ino @@ -0,0 +1,165 @@ +// This is a demonstration on how to use an input device to trigger changes on your neo pixels. +// You should wire a momentary push button to connect from ground to a digital IO pin. When you +// press the button it will change to a new pixel animation. Note that you need to press the +// button once to start the first animation! + +#include + +#define BUTTON_PIN 2 // Digital IO pin connected to the button. This will be + // driven with a pull-up resistor so the switch should + // pull the pin to ground momentarily. On a high -> low + // transition the button press logic will execute. + +#define PIXEL_PIN 6 // Digital IO pin connected to the NeoPixels. + +#define PIXEL_COUNT 16 + +// Parameter 1 = number of pixels in strip, neopixel stick has 8 +// Parameter 2 = pin number (most are valid) +// Parameter 3 = pixel type flags, add together as needed: +// NEO_RGB Pixels are wired for RGB bitstream +// NEO_GRB Pixels are wired for GRB bitstream, correct for neopixel stick +// NEO_KHZ400 400 KHz bitstream (e.g. FLORA pixels) +// NEO_KHZ800 800 KHz bitstream (e.g. High Density LED strip), correct for neopixel stick +Adafruit_NeoPixel strip = Adafruit_NeoPixel(PIXEL_COUNT, PIXEL_PIN, NEO_GRB + NEO_KHZ800); + +bool oldState = HIGH; +int showType = 0; + +void setup() { + pinMode(BUTTON_PIN, INPUT_PULLUP); + strip.begin(); + strip.show(); // Initialize all pixels to 'off' +} + +void loop() { + // Get current button state. + bool newState = digitalRead(BUTTON_PIN); + + // Check if state changed from high to low (button press). + if (newState == LOW && oldState == HIGH) { + // Short delay to debounce button. + delay(20); + // Check if button is still low after debounce. + newState = digitalRead(BUTTON_PIN); + if (newState == LOW) { + showType++; + if (showType > 9) + showType=0; + startShow(showType); + } + } + + // Set the last button state to the old state. + oldState = newState; +} + +void startShow(int i) { + switch(i){ + case 0: colorWipe(strip.Color(0, 0, 0), 50); // Black/off + break; + case 1: colorWipe(strip.Color(255, 0, 0), 50); // Red + break; + case 2: colorWipe(strip.Color(0, 255, 0), 50); // Green + break; + case 3: colorWipe(strip.Color(0, 0, 255), 50); // Blue + break; + case 4: theaterChase(strip.Color(127, 127, 127), 50); // White + break; + case 5: theaterChase(strip.Color(127, 0, 0), 50); // Red + break; + case 6: theaterChase(strip.Color( 0, 0, 127), 50); // Blue + break; + case 7: rainbow(20); + break; + case 8: rainbowCycle(20); + break; + case 9: theaterChaseRainbow(50); + break; + } +} + +// Fill the dots one after the other with a color +void colorWipe(uint32_t c, uint8_t wait) { + for(uint16_t i=0; i + +// Which pin on the Arduino is connected to the NeoPixels? +#define PIN 1 + +// How many NeoPixels are attached to the Arduino? +#define NUMPIXELS 1 + +// When we setup the NeoPixel library, we tell it how many pixels, and which pin to use to send signals. +// Note that for older NeoPixel strips you might need to change the third parameter--see the strandtest +// example for more information on possible values. +Adafruit_NeoPixel pixels = Adafruit_NeoPixel(NUMPIXELS, PIN, NEO_RGB + NEO_KHZ800); + +int delayval = 500; // delay for half a second + +void setup() { + pixels.begin(); // This initializes the NeoPixel library. +} + +void loop() { + // For a set of NeoPixels the first NeoPixel is 0, second is 1, all the way up to the count of pixels minus one. + for(int i=0;i + +// Which pin on the Arduino is connected to the NeoPixels? +#define PIN 6 + +// How many NeoPixels are attached to the Arduino? +#define NUMPIXELS 16 + +// When we setup the NeoPixel library, we tell it how many pixels, and which pin to use to send signals. +// Note that for older NeoPixel strips you might need to change the third parameter--see the strandtest +// example for more information on possible values. +Adafruit_NeoPixel pixels = Adafruit_NeoPixel(NUMPIXELS, PIN, NEO_GRB + NEO_KHZ800); + +int delayval = 500; // delay for half a second + +void setup() { + pixels.begin(); // This initializes the NeoPixel library. +} + +void loop() { + // For a set of NeoPixels the first NeoPixel is 0, second is 1, all the way up to the count of pixels minus one. + for(int i=0;i + +#define PIN 6 + +// Parameter 1 = number of pixels in strip +// Parameter 2 = Arduino pin number (most are valid) +// Parameter 3 = pixel type flags, add together as needed: +// NEO_KHZ800 800 KHz bitstream (most NeoPixel products w/WS2812 LEDs) +// NEO_KHZ400 400 KHz (classic 'v1' (not v2) FLORA pixels, WS2811 drivers) +// NEO_GRB Pixels are wired for GRB bitstream (most NeoPixel products) +// NEO_RGB Pixels are wired for RGB bitstream (v1 FLORA pixels, not v2) +Adafruit_NeoPixel strip = Adafruit_NeoPixel(60, PIN, NEO_GRB + NEO_KHZ800); + +// IMPORTANT: To reduce NeoPixel burnout risk, add 1000 uF capacitor across +// pixel power leads, add 300 - 500 Ohm resistor on first pixel's data input +// and minimize distance between Arduino and first pixel. Avoid connecting +// on a live circuit...if you must, connect GND first. + +void setup() { + strip.begin(); + strip.show(); // Initialize all pixels to 'off' +} + +void loop() { + // Some example procedures showing how to display to the pixels: + colorWipe(strip.Color(255, 0, 0), 50); // Red + colorWipe(strip.Color(0, 255, 0), 50); // Green + colorWipe(strip.Color(0, 0, 255), 50); // Blue + // Send a theater pixel chase in... + theaterChase(strip.Color(127, 127, 127), 50); // White + theaterChase(strip.Color(127, 0, 0), 50); // Red + theaterChase(strip.Color( 0, 0, 127), 50); // Blue + + rainbow(20); + rainbowCycle(20); + theaterChaseRainbow(50); +} + +// Fill the dots one after the other with a color +void colorWipe(uint32_t c, uint8_t wait) { + for(uint16_t i=0; i when compiling with IAR. + - Introduced USB_CFG_DESCR_PROPS_* in usbconfig.h to configure how each + USB descriptor should be handled. It is now possible to provide descriptor + data in Flash, RAM or dynamically at runtime. + - STALL is now a status in usbTxLen* instead of a message. We can now conform + to the spec and leave the stall status pending until it is cleared. + - Made usbTxPacketCnt1 and usbTxPacketCnt3 public. This allows the + application code to reset data toggling on interrupt pipes. + +* Release 2006-07-18 + + - Added an #if !defined __ASSEMBLER__ to the warning in usbdrv.h. This fixes + an assembler error. + - usbDeviceDisconnect() takes pull-up resistor to high impedance now. + +* Release 2007-02-01 + + - Merged in some code size improvements from usbtiny (thanks to Dick + Streefland for these optimizations!) + - Special alignment requirement for usbRxBuf not required any more. Thanks + again to Dick Streefland for this hint! + - Reverted to "#warning" instead of unused static variables -- new versions + of IAR CC should handle this directive. + - Changed Open Source license to GNU GPL v2 in order to make linking against + other free libraries easier. We no longer require publication of the + circuit diagrams, but we STRONGLY encourage it. If you improve the driver + itself, PLEASE grant us a royalty free license to your changes for our + commercial license. + +* Release 2007-03-29 + + - New configuration option "USB_PUBLIC" in usbconfig.h. + - Set USB version number to 1.10 instead of 1.01. + - Code used USB_CFG_DESCR_PROPS_STRING_DEVICE and + USB_CFG_DESCR_PROPS_STRING_PRODUCT inconsistently. Changed all occurrences + to USB_CFG_DESCR_PROPS_STRING_PRODUCT. + - New assembler module for 16.5 MHz RC oscillator clock with PLL in receiver + code. + - New assembler module for 16 MHz crystal. + - usbdrvasm.S contains common code only, clock-specific parts have been moved + to usbdrvasm12.S, usbdrvasm16.S and usbdrvasm165.S respectively. + +* Release 2007-06-25 + + - 16 MHz module: Do SE0 check in stuffed bits as well. + +* Release 2007-07-07 + + - Define hi8(x) for IAR compiler to limit result to 8 bits. This is necessary + for negative values. + - Added 15 MHz module contributed by V. Bosch. + - Interrupt vector name can now be configured. This is useful if somebody + wants to use a different hardware interrupt than INT0. + +* Release 2007-08-07 + + - Moved handleIn3 routine in usbdrvasm16.S so that relative jump range is + not exceeded. + - More config options: USB_RX_USER_HOOK(), USB_INITIAL_DATATOKEN, + USB_COUNT_SOF + - USB_INTR_PENDING can now be a memory address, not just I/O + +* Release 2007-09-19 + + - Split out common parts of assembler modules into separate include file + - Made endpoint numbers configurable so that given interface definitions + can be matched. See USB_CFG_EP3_NUMBER in usbconfig-prototype.h. + - Store endpoint number for interrupt/bulk-out so that usbFunctionWriteOut() + can handle any number of endpoints. + - Define usbDeviceConnect() and usbDeviceDisconnect() even if no + USB_CFG_PULLUP_IOPORTNAME is defined. Directly set D+ and D- to 0 in this + case. + +* Release 2007-12-01 + + - Optimize usbDeviceConnect() and usbDeviceDisconnect() for less code size + when USB_CFG_PULLUP_IOPORTNAME is not defined. + +* Release 2007-12-13 + + - Renamed all include-only assembler modules from *.S to *.inc so that + people don't add them to their project sources. + - Distribute leap bits in tx loop more evenly for 16 MHz module. + - Use "macro" and "endm" instead of ".macro" and ".endm" for IAR + - Avoid compiler warnings for constant expr range by casting some values in + USB descriptors. + +* Release 2008-01-21 + + - Fixed bug in 15 and 16 MHz module where the new address set with + SET_ADDRESS was already accepted at the next NAK or ACK we send, not at + the next data packet we send. This caused problems when the host polled + too fast. Thanks to Alexander Neumann for his help and patience debugging + this issue! + +* Release 2008-02-05 + + - Fixed bug in 16.5 MHz module where a register was used in the interrupt + handler before it was pushed. This bug was introduced with version + 2007-09-19 when common parts were moved to a separate file. + - Optimized CRC routine (thanks to Reimar Doeffinger). + +* Release 2008-02-16 + + - Removed outdated IAR compatibility stuff (code sections). + - Added hook macros for USB_RESET_HOOK() and USB_SET_ADDRESS_HOOK(). + - Added optional routine usbMeasureFrameLength() for calibration of the + internal RC oscillator. + +* Release 2008-02-28 + + - USB_INITIAL_DATATOKEN defaults to USBPID_DATA1 now, which means that we + start with sending USBPID_DATA0. + - Changed defaults in usbconfig-prototype.h + - Added free USB VID/PID pair for MIDI class devices + - Restructured AVR-USB as separate package, not part of PowerSwitch any more. + +* Release 2008-04-18 + + - Restructured usbdrv.c so that it is easier to read and understand. + - Better code optimization with gcc 4. + - If a second interrupt in endpoint is enabled, also add it to config + descriptor. + - Added config option for long transfers (above 254 bytes), see + USB_CFG_LONG_TRANSFERS in usbconfig.h. + - Added 20 MHz module contributed by Jeroen Benschop. + +* Release 2008-05-13 + + - Fixed bug in libs-host/hiddata.c function usbhidGetReport(): length + was not incremented, pointer to length was incremented instead. + - Added code to command line tool(s) which claims an interface. This code + is disabled by default, but may be necessary on newer Linux kernels. + - Added usbconfig.h option "USB_CFG_CHECK_DATA_TOGGLING". + - New header "usbportability.h" prepares ports to other development + environments. + - Long transfers (above 254 bytes) did not work when usbFunctionRead() was + used to supply the data. Fixed this bug. [Thanks to Alexander Neumann!] + - In hiddata.c (example code for sending/receiving data over HID), use + USB_RECIP_DEVICE instead of USB_RECIP_INTERFACE for control transfers so + that we need not claim the interface. + - in usbPoll() loop 20 times polling for RESET state instead of 10 times. + This accounts for the higher clock rates we now support. + - Added a module for 12.8 MHz RC oscillator with PLL in receiver loop. + - Added hook to SOF code so that oscillator can be tuned to USB frame clock. + - Added timeout to waitForJ loop. Helps preventing unexpected hangs. + - Added example code for oscillator tuning to libs-device (thanks to + Henrik Haftmann for the idea to this routine). + - Implemented option USB_CFG_SUPPRESS_INTR_CODE. + +* Release 2008-10-22 + + - Fixed libs-device/osctune.h: OSCCAL is memory address on ATMega88 and + similar, not offset of 0x20 needs to be added. + - Allow distribution under GPLv3 for those who have to link against other + code distributed under GPLv3. + +* Release 2008-11-26 + + - Removed libusb-win32 dependency for hid-data example in Makefile.windows. + It was never required and confused many people. + - Added extern uchar usbRxToken to usbdrv.h. + - Integrated a module with CRC checks at 18 MHz by Lukas Schrittwieser. + +* Release 2009-03-23 + + - Hid-mouse example used settings from hid-data example, fixed that. + - Renamed project to V-USB due to a trademark issue with Atmel(r). + - Changed CommercialLicense.txt and USBID-License.txt to make the + background of USB ID registration clearer. + +* Release 2009-04-15 + + - Changed CommercialLicense.txt to reflect the new range of PIDs from + Jason Kotzin. + - Removed USBID-License.txt in favor of USB-IDs-for-free.txt and + USB-ID-FAQ.txt + - Fixed a bug in the 12.8 MHz module: End Of Packet decection was made in + the center between bit 0 and 1 of each byte. This is where the data lines + are expected to change and the sampled data may therefore be nonsense. + We therefore check EOP ONLY if bits 0 AND 1 have both been read as 0 on D-. + - Fixed a bitstuffing problem in the 16 MHz module: If bit 6 was stuffed, + the unstuffing code in the receiver routine was 1 cycle too long. If + multiple bytes had the unstuffing in bit 6, the error summed up until the + receiver was out of sync. + - Included option for faster CRC routine. + Thanks to Slawomir Fras (BoskiDialer) for this code! + - Updated bits in Configuration Descriptor's bmAttributes according to + USB 1.1 (in particular bit 7, it is a must-be-set bit now). + +* Release 2009-08-22 + + - Moved first DBG1() after odDebugInit() in all examples. + - Use vector INT0_vect instead of SIG_INTERRUPT0 if defined. This makes + V-USB compatible with the new "p" suffix devices (e.g. ATMega328p). + - USB_CFG_CLOCK_KHZ setting is now required in usbconfig.h (no default any + more). + - New option USB_CFG_DRIVER_FLASH_PAGE allows boot loaders on devices with + more than 64 kB flash. + - Built-in configuration descriptor allows custom definition for second + endpoint now. + +* Release 2010-07-15 diff --git a/hardware/digistump/avr/libraries/DigiCDC/CommercialLicense.txt b/hardware/digistump/avr/libraries/DigiCDC/CommercialLicense.txt new file mode 100644 index 0000000..11d07d9 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/CommercialLicense.txt @@ -0,0 +1,166 @@ +V-USB Driver Software License Agreement +Version 2009-08-03 + +THIS LICENSE AGREEMENT GRANTS YOU CERTAIN RIGHTS IN A SOFTWARE. YOU CAN +ENTER INTO THIS AGREEMENT AND ACQUIRE THE RIGHTS OUTLINED BELOW BY PAYING +THE AMOUNT ACCORDING TO SECTION 4 ("PAYMENT") TO OBJECTIVE DEVELOPMENT. + + +1 DEFINITIONS + +1.1 "OBJECTIVE DEVELOPMENT" shall mean OBJECTIVE DEVELOPMENT Software GmbH, +Grosse Schiffgasse 1A/7, 1020 Wien, AUSTRIA. + +1.2 "You" shall mean the Licensee. + +1.3 "V-USB" shall mean all files included in the package distributed under +the name "vusb" by OBJECTIVE DEVELOPMENT (http://www.obdev.at/vusb/) +unless otherwise noted. This includes the firmware-only USB device +implementation for Atmel AVR microcontrollers, some simple device examples +and host side software examples and libraries. + + +2 LICENSE GRANTS + +2.1 Source Code. OBJECTIVE DEVELOPMENT shall furnish you with the source +code of V-USB. + +2.2 Distribution and Use. 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This document represents the entire agreement between +OBJECTIVE DEVELOPMENT and you. It may only be modified in writing signed by +an authorized representative of both, OBJECTIVE DEVELOPMENT and you. + +8.3 Severability. In case a provision of these terms and conditions should +be or become partly or entirely invalid, ineffective, or not executable, +the validity of all other provisions shall not be affected. + +8.4 Applicable Law. This agreement is governed by the laws of the Republic +of Austria. + +8.5 Responsible Courts. The responsible courts in Vienna/Austria will have +exclusive jurisdiction regarding all disputes in connection with this +agreement. + diff --git a/hardware/digistump/avr/libraries/DigiCDC/DigiCDC.cpp b/hardware/digistump/avr/libraries/DigiCDC/DigiCDC.cpp new file mode 100644 index 0000000..5323eda --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/DigiCDC.cpp @@ -0,0 +1,380 @@ +/* + +CDC Arduino Library by Ihsan Kehribar (kehribar.me) +and Digistump LLC (digistump.com) +- all changes made under the same license as V-USB + + +*/ + +#include "DigiCDC.h" +#include +#include +#include +#include +#include + +uchar sendEmptyFrame; +static uchar intr3Status; /* used to control interrupt endpoint transmissions */ + + +DigiCDCDevice::DigiCDCDevice(void){} + + +void DigiCDCDevice::delay(long milli) { + unsigned long last = millis(); + while (milli > 0) { + unsigned long now = millis(); + milli -= now - last; + last = now; + refresh(); + } +} + +void DigiCDCDevice::flush(){ + cli(); + RingBuffer_InitBuffer(&rxBuf,rxBuf_Data,sizeof(rxBuf_Data)); + sei(); +} + +void DigiCDCDevice::begin(){ + + usbBegin(); + +} +size_t DigiCDCDevice::write(uint8_t chr) +{ + if(RingBuffer_IsFull(&txBuf)) + { + return 0; + } + else + { + RingBuffer_Insert(&txBuf,chr); + return 1; + } +} + +int DigiCDCDevice::available() +{ + return RingBuffer_GetCount(&rxBuf); +} + +int DigiCDCDevice::read() +{ + if(RingBuffer_IsEmpty(&rxBuf)) + { + return 0; + } + else + { + return RingBuffer_Remove(&rxBuf); + } +} + +int DigiCDCDevice::peek() +{ + if(RingBuffer_IsEmpty(&rxBuf)) + { + return 0; + } + else + { + return RingBuffer_Peek(&rxBuf); + } +} + + +void DigiCDCDevice::task(void) +{ + + usbPollWrapper(); + +} + +void DigiCDCDevice::refresh(void) +{ + + usbPollWrapper(); + + +} + + +void DigiCDCDevice::end(void) +{ + // drive both USB pins low to disconnect + usbDeviceDisconnect(); + cli(); + RingBuffer_InitBuffer(&rxBuf,rxBuf_Data,sizeof(rxBuf_Data)); + sei(); + +} + +DigiCDCDevice::operator bool() { + usbPollWrapper(); + return true; +} + + + + + + +void DigiCDCDevice::usbBegin() +{ + cli(); + + PORTB &= ~(_BV(USB_CFG_DMINUS_BIT) | _BV(USB_CFG_DPLUS_BIT)); + usbDeviceDisconnect(); + _delay_ms(250); + usbDeviceConnect(); + usbInit(); + + RingBuffer_InitBuffer(&txBuf,txBuf_Data,sizeof(txBuf_Data)); + RingBuffer_InitBuffer(&rxBuf,rxBuf_Data,sizeof(rxBuf_Data)); + + intr3Status = 0; + sendEmptyFrame = 0; + + sei(); +} + +void DigiCDCDevice::usbPollWrapper() +{ + usbPoll(); + while((!(RingBuffer_IsEmpty(&txBuf)))&&(index<9)) + { + tmp[index++] = RingBuffer_Remove(&txBuf); + } + + if(usbInterruptIsReady()) + { + if(sendEmptyFrame) + { + usbSetInterrupt(tmp,0); + sendEmptyFrame = 0; + } + else if(index>0) + { + usbSetInterrupt(tmp,index); + usbEnableAllRequests(); + sendEmptyFrame = 1; + index = 0; + } + } + + /* We need to report rx and tx carrier after open attempt */ + if(intr3Status != 0 && usbInterruptIsReady3()){ + static uchar serialStateNotification[10] = {0xa1, 0x20, 0, 0, 0, 0, 2, 0, 3, 0}; + + if(intr3Status == 2){ + usbSetInterrupt3(serialStateNotification, 8); + }else{ + usbSetInterrupt3(serialStateNotification+8, 2); + } + intr3Status--; + } + +} + + + + + + + +#ifdef __cplusplus +extern "C"{ +#endif + +enum { + SEND_ENCAPSULATED_COMMAND = 0, + GET_ENCAPSULATED_RESPONSE, + SET_COMM_FEATURE, + GET_COMM_FEATURE, + CLEAR_COMM_FEATURE, + SET_LINE_CODING = 0x20, + GET_LINE_CODING, + SET_CONTROL_LINE_STATE, + SEND_BREAK +}; + +static const PROGMEM char configDescrCDC[] = { /* USB configuration descriptor */ + 9, /* sizeof(usbDescrConfig): length of descriptor in bytes */ + USBDESCR_CONFIG, /* descriptor type */ + 67, + 0, /* total length of data returned (including inlined descriptors) */ + 2, /* number of interfaces in this configuration */ + 1, /* index of this configuration */ + 0, /* configuration name string index */ +#if USB_CFG_IS_SELF_POWERED + (1 << 7) | USBATTR_SELFPOWER, /* attributes */ +#else + (1 << 7), /* attributes */ +#endif + USB_CFG_MAX_BUS_POWER/2, /* max USB current in 2mA units */ + + /* interface descriptor follows inline: */ + 9, /* sizeof(usbDescrInterface): length of descriptor in bytes */ + USBDESCR_INTERFACE, /* descriptor type */ + 0, /* index of this interface */ + 0, /* alternate setting for this interface */ + USB_CFG_HAVE_INTRIN_ENDPOINT, /* endpoints excl 0: number of endpoint descriptors to follow */ + USB_CFG_INTERFACE_CLASS, + USB_CFG_INTERFACE_SUBCLASS, + USB_CFG_INTERFACE_PROTOCOL, + 0, /* string index for interface */ + + /* CDC Class-Specific descriptor */ + 5, /* sizeof(usbDescrCDC_HeaderFn): length of descriptor in bytes */ + 0x24, /* descriptor type */ + 0, /* header functional descriptor */ + 0x10, 0x01, + + 4, /* sizeof(usbDescrCDC_AcmFn): length of descriptor in bytes */ + 0x24, /* descriptor type */ + 2, /* abstract control management functional descriptor */ + 0x02, /* SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE */ + + 5, /* sizeof(usbDescrCDC_UnionFn): length of descriptor in bytes */ + 0x24, /* descriptor type */ + 6, /* union functional descriptor */ + 0, /* CDC_COMM_INTF_ID */ + 1, /* CDC_DATA_INTF_ID */ + + 5, /* sizeof(usbDescrCDC_CallMgtFn): length of descriptor in bytes */ + 0x24, /* descriptor type */ + 1, /* call management functional descriptor */ + 3, /* allow management on data interface, handles call management by itself */ + 1, /* CDC_DATA_INTF_ID */ + + /* Endpoint Descriptor */ + 7, /* sizeof(usbDescrEndpoint) */ + USBDESCR_ENDPOINT, /* descriptor type = endpoint */ + 0x80|USB_CFG_EP3_NUMBER, /* IN endpoint number 3 */ + 0x03, /* attrib: Interrupt endpoint */ + 8, 0, /* maximum packet size */ + USB_CFG_INTR_POLL_INTERVAL, /* in ms */ + + /* Interface Descriptor */ + 9, /* sizeof(usbDescrInterface): length of descriptor in bytes */ + USBDESCR_INTERFACE, /* descriptor type */ + 1, /* index of this interface */ + 0, /* alternate setting for this interface */ + 2, /* endpoints excl 0: number of endpoint descriptors to follow */ + 0x0A, /* Data Interface Class Codes */ + 0, + 0, /* Data Interface Class Protocol Codes */ + 0, /* string index for interface */ + + /* Endpoint Descriptor */ + 7, /* sizeof(usbDescrEndpoint) */ + USBDESCR_ENDPOINT, /* descriptor type = endpoint */ + 0x01, /* OUT endpoint number 1 */ + 0x02, /* attrib: Bulk endpoint */ + HW_CDC_BULK_OUT_SIZE, 0, /* maximum packet size */ + 0, /* in ms */ + + /* Endpoint Descriptor */ + 7, /* sizeof(usbDescrEndpoint) */ + USBDESCR_ENDPOINT, /* descriptor type = endpoint */ + 0x81, /* IN endpoint number 1 */ + 0x02, /* attrib: Bulk endpoint */ + HW_CDC_BULK_IN_SIZE, 0, /* maximum packet size */ + 0, /* in ms */ +}; + +uchar usbFunctionDescriptor(usbRequest_t *rq) +{ + if(rq->wValue.bytes[1] == USBDESCR_DEVICE){ + usbMsgPtr = (uchar *)usbDescriptorDevice; + return usbDescriptorDevice[0]; + }else{ /* must be config descriptor */ + usbMsgPtr = (uchar *)configDescrCDC; + return sizeof(configDescrCDC); + } +} + +/* ------------------------------------------------------------------------- */ +/* ----------------------------- USB interface ----------------------------- */ +/* ------------------------------------------------------------------------- */ + +uchar usbFunctionSetup(uchar data[8]) +{ +usbRequest_t *rq = (usbRequest_t*)((void *)data); + + if((rq->bmRequestType & USBRQ_TYPE_MASK) == USBRQ_TYPE_CLASS){ /* class request type */ + + if( rq->bRequest==GET_LINE_CODING || rq->bRequest==SET_LINE_CODING ){ + return 0xff; + /* GET_LINE_CODING -> usbFunctionRead() */ + /* SET_LINE_CODING -> usbFunctionWrite() */ + } + if(rq->bRequest == SET_CONTROL_LINE_STATE){ + /* Report serial state (carrier detect). On several Unix platforms, + * tty devices can only be opened when carrier detect is set. + */ + if( intr3Status==0 ) + intr3Status = 2; + } + + /* Prepare bulk-in endpoint to respond to early termination */ + if((rq->bmRequestType & USBRQ_DIR_MASK) == USBRQ_DIR_HOST_TO_DEVICE) + sendEmptyFrame = 1; + } + + return 0; +} + +/*---------------------------------------------------------------------------*/ +/* usbFunctionRead */ +/*---------------------------------------------------------------------------*/ +uchar usbFunctionRead( uchar *data, uchar len ) +{ + // data[0] = 0; + // data[1] = 0; + // data[2] = 0; + // data[3] = 0; + // data[4] = 0; + // data[5] = 0; + // data[6] = 8; + + return 7; +} + +/*---------------------------------------------------------------------------*/ +/* usbFunctionWrite */ +/*---------------------------------------------------------------------------*/ +uchar usbFunctionWrite( uchar *data, uchar len ) +{ + // baud.bytes[0] = data[0]; + // baud.bytes[1] = data[1]; + + return 1; +} + +void usbFunctionWriteOut( uchar *data, uchar len ) +{ + uint8_t qw = 0; + for(qw=0;qw= HW_CDC_BULK_OUT_SIZE) + { + usbDisableAllRequests(); + } +} + + +#ifdef __cplusplus +} // extern "C" +#endif + +DigiCDCDevice SerialUSB; \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigiCDC/DigiCDC.h b/hardware/digistump/avr/libraries/DigiCDC/DigiCDC.h new file mode 100644 index 0000000..46179f4 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/DigiCDC.h @@ -0,0 +1,65 @@ +/* + +CDC Arduino Library by Ihsan Kehribar (kehribar.me) +and Digistump LLC (digistump.com) +- all changes made under the same license as V-USB + + + */ +#ifndef __DigiCDC_h__ +#define __DigiCDC_h__ +#include "usbdrv.h" + + + +#include "Stream.h" +#include "ringBuffer.h" + + +#define HW_CDC_TX_BUF_SIZE 32 +#define HW_CDC_RX_BUF_SIZE 32 +#define HW_CDC_BULK_OUT_SIZE 8 +#define HW_CDC_BULK_IN_SIZE 8 + + + +/* library functions and variables start */ +static uint8_t tmp[HW_CDC_BULK_IN_SIZE]; +static uint8_t index = 0; + +static RingBuffer_t rxBuf; +static uint8_t rxBuf_Data[HW_CDC_RX_BUF_SIZE]; + +static RingBuffer_t txBuf; +static uint8_t txBuf_Data[HW_CDC_TX_BUF_SIZE]; + + +class DigiCDCDevice : public Stream { + public: + DigiCDCDevice(); + void begin(), begin(unsigned long x); + void end(); + void refresh(); + void task(); + void delay(long milli); + virtual int available(void); + virtual int peek(void); + virtual int read(void); + virtual void flush(void); + virtual size_t write(uint8_t); + inline size_t write(unsigned long n) { return write((uint8_t)n); } + inline size_t write(long n) { return write((uint8_t)n); } + inline size_t write(unsigned int n) { return write((uint8_t)n); } + inline size_t write(int n) { return write((uint8_t)n); } + using Print::write; + operator bool(); + private: + void usbBegin(); + void usbPollWrapper(); + }; + + +extern DigiCDCDevice SerialUSB; + + +#endif // __DigiCDC_h__ \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigiCDC/License.txt b/hardware/digistump/avr/libraries/DigiCDC/License.txt new file mode 100644 index 0000000..4460cfb --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/License.txt @@ -0,0 +1,361 @@ +OBJECTIVE DEVELOPMENT GmbH's V-USB driver software is distributed under the +terms and conditions of the GNU GPL version 2 or the GNU GPL version 3. It is +your choice whether you apply the terms of version 2 or version 3. The full +text of GPLv2 is included below. In addition to the requirements in the GPL, +we STRONGLY ENCOURAGE you to do the following: + +(1) Publish your entire project on a web site and drop us a note with the URL. +Use the form at http://www.obdev.at/vusb/feedback.html for your submission. + +(2) Adhere to minimum publication standards. Please include AT LEAST: + - a circuit diagram in PDF, PNG or GIF format + - full source code for the host software + - a Readme.txt file in ASCII format which describes the purpose of the + project and what can be found in which directories and which files + - a reference to http://www.obdev.at/vusb/ + +(3) If you improve the driver firmware itself, please give us a free license +to your modifications for our commercial license offerings. + + + + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/hardware/digistump/avr/libraries/DigiCDC/Readme.txt b/hardware/digistump/avr/libraries/DigiCDC/Readme.txt new file mode 100644 index 0000000..970dc66 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/Readme.txt @@ -0,0 +1,172 @@ +This is the Readme file to Objective Development's firmware-only USB driver +for Atmel AVR microcontrollers. For more information please visit +http://www.obdev.at/vusb/ + +This directory contains the USB firmware only. Copy it as-is to your own +project and add all .c and .S files to your project (these files are marked +with an asterisk in the list below). Then copy usbconfig-prototype.h as +usbconfig.h to your project and edit it according to your configuration. + + +TECHNICAL DOCUMENTATION +======================= +The technical documentation (API) for the firmware driver is contained in the +file "usbdrv.h". Please read all of it carefully! Configuration options are +documented in "usbconfig-prototype.h". + +The driver consists of the following files: + Readme.txt ............. The file you are currently reading. + Changelog.txt .......... Release notes for all versions of the driver. + usbdrv.h ............... Driver interface definitions and technical docs. +* usbdrv.c ............... High level language part of the driver. Link this + module to your code! +* usbdrvasm.S ............ Assembler part of the driver. This module is mostly + a stub and includes one of the usbdrvasm*.S files + depending on processor clock. Link this module to + your code! + usbdrvasm*.inc ......... Assembler routines for particular clock frequencies. + Included by usbdrvasm.S, don't link it directly! + asmcommon.inc .......... Common assembler routines. Included by + usbdrvasm*.inc, don't link it directly! + usbconfig-prototype.h .. Prototype for your own usbdrv.h file. +* oddebug.c .............. Debug functions. Only used when DEBUG_LEVEL is + defined to a value greater than 0. Link this module + to your code! + oddebug.h .............. Interface definitions of the debug module. + usbportability.h ....... Header with compiler-dependent stuff. + usbdrvasm.asm .......... Compatibility stub for IAR-C-compiler. Use this + module instead of usbdrvasm.S when you assembler + with IAR's tools. + License.txt ............ Open Source license for this driver. + CommercialLicense.txt .. Optional commercial license for this driver. + USB-ID-FAQ.txt ......... General infos about USB Product- and Vendor-IDs. + USB-IDs-for-free.txt ... List and terms of use for free shared PIDs. + +(*) ... These files should be linked to your project. + + +CPU CORE CLOCK FREQUENCY +======================== +We supply assembler modules for clock frequencies of 12 MHz, 12.8 MHz, 15 MHz, +16 MHz, 16.5 MHz 18 MHz and 20 MHz. Other clock rates are not supported. The +actual clock rate must be configured in usbconfig.h. + +12 MHz Clock +This is the traditional clock rate of V-USB because it's the lowest clock +rate where the timing constraints of the USB spec can be met. + +15 MHz Clock +Similar to 12 MHz, but some NOPs inserted. On the other hand, the higher clock +rate allows for some loops which make the resulting code size somewhat smaller +than the 12 MHz version. + +16 MHz Clock +This clock rate has been added for users of the Arduino board and other +ready-made boards which come with a fixed 16 MHz crystal. It's also an option +if you need the slightly higher clock rate for performance reasons. Since +16 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code +is somewhat tricky and has to insert a leap cycle every third byte. + +12.8 MHz and 16.5 MHz Clock +The assembler modules for these clock rates differ from the other modules +because they have been built for an RC oscillator with only 1% precision. The +receiver code inserts leap cycles to compensate for clock deviations. 1% is +also the precision which can be achieved by calibrating the internal RC +oscillator of the AVR. Please note that only AVRs with internal 64 MHz PLL +oscillator can reach 16.5 MHz with the RC oscillator. This includes the very +popular ATTiny25, ATTiny45, ATTiny85 series as well as the ATTiny26. Almost +all AVRs can reach 12.8 MHz, although this is outside the specified range. + +See the EasyLogger example at http://www.obdev.at/vusb/easylogger.html for +code which calibrates the RC oscillator based on the USB frame clock. + +18 MHz Clock +This module is closer to the USB specification because it performs an on the +fly CRC check for incoming packets. Packets with invalid checksum are +discarded as required by the spec. If you also implement checks for data +PID toggling on application level (see option USB_CFG_CHECK_DATA_TOGGLING +in usbconfig.h for more info), this ensures data integrity. Due to the CRC +tables and alignment requirements, this code is bigger than modules for other +clock rates. To activate this module, you must define USB_CFG_CHECK_CRC to 1 +and USB_CFG_CLOCK_KHZ to 18000 in usbconfig.h. + +20 MHz Clock +This module is for people who won't do it with less than the maximum. Since +20 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code +uses similar tricks as the 16 MHz module to insert leap cycles. + + +USB IDENTIFIERS +=============== +Every USB device needs a vendor- and a product-identifier (VID and PID). VIDs +are obtained from usb.org for a price of 1,500 USD. Once you have a VID, you +can assign PIDs at will. + +Since an entry level cost of 1,500 USD is too high for most small companies +and hobbyists, we provide some VID/PID pairs for free. See the file +USB-IDs-for-free.txt for details. + +Objective Development also has some license offerings which include product +IDs. See http://www.obdev.at/vusb/ for details. + + +DEVELOPMENT SYSTEM +================== +This driver has been developed and optimized for the GNU compiler version 3 +and 4. We recommend that you use the GNU compiler suite because it is freely +available. V-USB has also been ported to the IAR compiler and assembler. It +has been tested with IAR 4.10B/W32 and 4.12A/W32 on an ATmega8 with the +"small" and "tiny" memory model. Not every release is tested with IAR CC and +the driver may therefore fail to compile with IAR. Please note that gcc is +more efficient for usbdrv.c because this module has been deliberately +optimized for gcc. + +Gcc version 3 produces smaller code than version 4 due to new optimizing +capabilities which don't always improve things on 8 bit CPUs. The code size +generated by gcc 4 can be reduced with the compiler options +-fno-move-loop-invariants, -fno-tree-scev-cprop and +-fno-inline-small-functions in addition to -Os. On devices with more than +8k of flash memory, we also recommend the linker option --relax (written as +-Wl,--relax for gcc) to convert absolute calls into relative where possible. + +For more information about optimizing options see: + + http://www.tty1.net/blog/2008-04-29-avr-gcc-optimisations_en.html + +These optimizations are good for gcc 4.x. Version 3.x of gcc does not support +most of these options and produces good code anyway. + + +USING V-USB FOR FREE +==================== +The AVR firmware driver is published under the GNU General Public License +Version 2 (GPL2) and the GNU General Public License Version 3 (GPL3). It is +your choice whether you apply the terms of version 2 or version 3. + +If you decide for the free GPL2 or GPL3, we STRONGLY ENCOURAGE you to do the +following things IN ADDITION to the obligations from the GPL: + +(1) Publish your entire project on a web site and drop us a note with the URL. +Use the form at http://www.obdev.at/vusb/feedback.html for your submission. +If you don't have a web site, you can publish the project in obdev's +documentation wiki at +http://www.obdev.at/goto.php?t=vusb-wiki&p=hosted-projects. + +(2) Adhere to minimum publication standards. Please include AT LEAST: + - a circuit diagram in PDF, PNG or GIF format + - full source code for the host software + - a Readme.txt file in ASCII format which describes the purpose of the + project and what can be found in which directories and which files + - a reference to http://www.obdev.at/vusb/ + +(3) If you improve the driver firmware itself, please give us a free license +to your modifications for our commercial license offerings. + + +COMMERCIAL LICENSES FOR V-USB +============================= +If you don't want to publish your source code under the terms of the GPL, +you can simply pay money for V-USB. As an additional benefit you get +USB PIDs for free, reserved exclusively to you. See the file +"CommercialLicense.txt" for details. + diff --git a/hardware/digistump/avr/libraries/DigiCDC/asmcommon.inc b/hardware/digistump/avr/libraries/DigiCDC/asmcommon.inc new file mode 100644 index 0000000..07d692b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/asmcommon.inc @@ -0,0 +1,188 @@ +/* Name: asmcommon.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2007-11-05 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id$ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file contains assembler code which is shared among the USB driver +implementations for different CPU cocks. Since the code must be inserted +in the middle of the module, it's split out into this file and #included. + +Jump destinations called from outside: + sofError: Called when no start sequence was found. + se0: Called when a package has been successfully received. + overflow: Called when receive buffer overflows. + doReturn: Called after sending data. + +Outside jump destinations used by this module: + waitForJ: Called to receive an already arriving packet. + sendAckAndReti: + sendNakAndReti: + sendCntAndReti: + usbSendAndReti: + +The following macros must be defined before this file is included: + .macro POP_STANDARD + .endm + .macro POP_RETI + .endm +*/ + +#define token x1 + +overflow: + ldi x2, 1< +void setup() { + // initialize the digital pin as an output. + SerialUSB.begin(); + SerialUSB.println("CDC Test"); +} + +// the loop routine runs over and over again forever: +void loop() { + + if (SerialUSB.available()) { + SerialUSB.write(SerialUSB.read()); + } + + SerialUSB.delay(10); // keep usb alive // can alos use SerialUSB.refresh(); +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigiCDC/libs-device/Readme.txt b/hardware/digistump/avr/libraries/DigiCDC/libs-device/Readme.txt new file mode 100644 index 0000000..76518dc --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/libs-device/Readme.txt @@ -0,0 +1,22 @@ +This is the Readme file for the libs-device directory. This directory contains +code snippets which may be useful for USB device firmware. + + +WHAT IS INCLUDED IN THIS DIRECTORY? +=================================== + +osccal.c and osccal.h + This module contains a function which calibrates the AVR's built-in RC + oscillator based on the USB frame clock. See osccal.h for a documentation + of the API. + +osctune.h + This header file contains a code snippet for usbconfig.h. With this code, + you can keep the AVR's internal RC oscillator in sync with the USB frame + clock. This is a continuous synchronization, not a single calibration at + USB reset as with osccal.c above. Please note that this code works only + if D- is wired to the interrupt, not D+. + +---------------------------------------------------------------------------- +(c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH. +http://www.obdev.at/ diff --git a/hardware/digistump/avr/libraries/DigiCDC/oddebug.c b/hardware/digistump/avr/libraries/DigiCDC/oddebug.c new file mode 100644 index 0000000..945457c --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/oddebug.c @@ -0,0 +1,50 @@ +/* Name: oddebug.c + * Project: AVR library + * Author: Christian Starkjohann + * Creation Date: 2005-01-16 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: oddebug.c 692 2008-11-07 15:07:40Z cs $ + */ + +#include "oddebug.h" + +#if DEBUG_LEVEL > 0 + +#warning "Never compile production devices with debugging enabled" + +static void uartPutc(char c) +{ + while(!(ODDBG_USR & (1 << ODDBG_UDRE))); /* wait for data register empty */ + ODDBG_UDR = c; +} + +static uchar hexAscii(uchar h) +{ + h &= 0xf; + if(h >= 10) + h += 'a' - (uchar)10 - '0'; + h += '0'; + return h; +} + +static void printHex(uchar c) +{ + uartPutc(hexAscii(c >> 4)); + uartPutc(hexAscii(c)); +} + +void odDebug(uchar prefix, uchar *data, uchar len) +{ + printHex(prefix); + uartPutc(':'); + while(len--){ + uartPutc(' '); + printHex(*data++); + } + uartPutc('\r'); + uartPutc('\n'); +} + +#endif diff --git a/hardware/digistump/avr/libraries/DigiCDC/oddebug.h b/hardware/digistump/avr/libraries/DigiCDC/oddebug.h new file mode 100644 index 0000000..d61309d --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/oddebug.h @@ -0,0 +1,123 @@ +/* Name: oddebug.h + * Project: AVR library + * Author: Christian Starkjohann + * Creation Date: 2005-01-16 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: oddebug.h 692 2008-11-07 15:07:40Z cs $ + */ + +#ifndef __oddebug_h_included__ +#define __oddebug_h_included__ + +/* +General Description: +This module implements a function for debug logs on the serial line of the +AVR microcontroller. Debugging can be configured with the define +'DEBUG_LEVEL'. If this macro is not defined or defined to 0, all debugging +calls are no-ops. If it is 1, DBG1 logs will appear, but not DBG2. If it is +2, DBG1 and DBG2 logs will be printed. + +A debug log consists of a label ('prefix') to indicate which debug log created +the output and a memory block to dump in hex ('data' and 'len'). +*/ + + +#ifndef F_CPU +# define F_CPU 12000000 /* 12 MHz */ +#endif + +/* make sure we have the UART defines: */ +#include "usbportability.h" + +#ifndef uchar +# define uchar unsigned char +#endif + +#if DEBUG_LEVEL > 0 && !(defined TXEN || defined TXEN0) /* no UART in device */ +# warning "Debugging disabled because device has no UART" +# undef DEBUG_LEVEL +#endif + +#ifndef DEBUG_LEVEL +# define DEBUG_LEVEL 0 +#endif + +/* ------------------------------------------------------------------------- */ + +#if DEBUG_LEVEL > 0 +# define DBG1(prefix, data, len) odDebug(prefix, data, len) +#else +# define DBG1(prefix, data, len) +#endif + +#if DEBUG_LEVEL > 1 +# define DBG2(prefix, data, len) odDebug(prefix, data, len) +#else +# define DBG2(prefix, data, len) +#endif + +/* ------------------------------------------------------------------------- */ + +#if DEBUG_LEVEL > 0 +extern void odDebug(uchar prefix, uchar *data, uchar len); + +/* Try to find our control registers; ATMEL likes to rename these */ + +#if defined UBRR +# define ODDBG_UBRR UBRR +#elif defined UBRRL +# define ODDBG_UBRR UBRRL +#elif defined UBRR0 +# define ODDBG_UBRR UBRR0 +#elif defined UBRR0L +# define ODDBG_UBRR UBRR0L +#endif + +#if defined UCR +# define ODDBG_UCR UCR +#elif defined UCSRB +# define ODDBG_UCR UCSRB +#elif defined UCSR0B +# define ODDBG_UCR UCSR0B +#endif + +#if defined TXEN +# define ODDBG_TXEN TXEN +#else +# define ODDBG_TXEN TXEN0 +#endif + +#if defined USR +# define ODDBG_USR USR +#elif defined UCSRA +# define ODDBG_USR UCSRA +#elif defined UCSR0A +# define ODDBG_USR UCSR0A +#endif + +#if defined UDRE +# define ODDBG_UDRE UDRE +#else +# define ODDBG_UDRE UDRE0 +#endif + +#if defined UDR +# define ODDBG_UDR UDR +#elif defined UDR0 +# define ODDBG_UDR UDR0 +#endif + +static inline void odDebugInit(void) +{ + ODDBG_UCR |= (1< + +#ifndef uchar +#define uchar unsigned char +#endif + +/* ------------------------------------------------------------------------- */ +/* ------------------------ Oscillator Calibration ------------------------- */ +/* ------------------------------------------------------------------------- */ + +/* Calibrate the RC oscillator. Our timing reference is the Start Of Frame + * signal (a single SE0 bit) repeating every millisecond immediately after + * a USB RESET. We first do a binary search for the OSCCAL value and then + * optimize this value with a neighboorhod search. + */ +void calibrateOscillator(void) +{ +uchar step = 128; +uchar trialValue = 0, optimumValue; +int x, optimumDev, targetValue = (unsigned)(1499 * (double)F_CPU / 10.5e6 + 0.5); + + /* do a binary search: */ + do{ + OSCCAL = trialValue + step; + x = usbMeasureFrameLength(); /* proportional to current real frequency */ + if(x < targetValue) /* frequency still too low */ + trialValue += step; + step >>= 1; + }while(step > 0); + /* We have a precision of +/- 1 for optimum OSCCAL here */ + /* now do a neighborhood search for optimum value */ + optimumValue = trialValue; + optimumDev = x; /* this is certainly far away from optimum */ + for(OSCCAL = trialValue - 1; OSCCAL <= trialValue + 1; OSCCAL++){ + x = usbMeasureFrameLength() - targetValue; + if(x < 0) + x = -x; + if(x < optimumDev){ + optimumDev = x; + optimumValue = OSCCAL; + } + } + OSCCAL = optimumValue; +} +/* +Note: This calibration algorithm may try OSCCAL values of up to 192 even if +the optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +You may replace this search algorithm with any other algorithm you like if +you have additional constraints such as a maximum CPU clock. +For version 5.x RC oscillators (those with a split range of 2x128 steps, e.g. +ATTiny25, ATTiny45, ATTiny85), it may be useful to search for the optimum in +both regions. +*/ diff --git a/hardware/digistump/avr/libraries/DigiCDC/osccal.h b/hardware/digistump/avr/libraries/DigiCDC/osccal.h new file mode 100644 index 0000000..710ce05 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/osccal.h @@ -0,0 +1,65 @@ +/* Name: osccal.h + * Author: Christian Starkjohann + * Creation Date: 2008-04-10 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osccal.h 762 2009-08-12 17:10:30Z cs $ + */ + +/* +General Description: +This module contains a function which calibrates the AVR's internal RC +oscillator so that the CPU runs at F_CPU (F_CPU is a macro which must be +defined when the module is compiled, best passed in the compiler command +line). The time reference is the USB frame clock of 1 kHz available +immediately after a USB RESET condition. Timing is done by counting CPU +cycles, so all interrupts must be disabled while the calibration runs. For +low level timing measurements, usbMeasureFrameLength() is called. This +function must be enabled in usbconfig.h by defining +USB_CFG_HAVE_MEASURE_FRAME_LENGTH to 1. It is recommended to call +calibrateOscillator() from the reset hook in usbconfig.h: +*/ + +#ifndef __ASSEMBLER__ +#include // for sei() +extern void calibrateOscillator(void); +#endif +#define USB_RESET_HOOK(resetStarts) if(!resetStarts){cli(); calibrateOscillator(); sei();} + +/* +This routine is an alternative to the continuous synchronization described +in osctune.h. + +Algorithm used: +calibrateOscillator() first does a binary search in the OSCCAL register for +the best matching oscillator frequency. Then it does a next neighbor search +to find the value with the lowest clock rate deviation. It is guaranteed to +find the best match among neighboring values, but for version 5 oscillators +(which have a discontinuous relationship between OSCCAL and frequency) a +better match might be available in another OSCCAL region. + +Limitations: +This calibration algorithm may try OSCCAL values of up to 192 even if the +optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +Precision depends on the OSCCAL vs. frequency dependency of the oscillator. +Typical precision for an ATMega168 (derived from the OSCCAL vs. F_RC diagram +in the data sheet) should be in the range of 0.4%. Only the 12.8 MHz and +16.5 MHz versions of V-USB (with built-in receiver PLL) can tolerate this +deviation! All other frequency modules require at least 0.2% precision. +*/ + +#ifndef __OSCCAL_H_INCLUDED__ +#define __OSCCAL_H_INCLUDED__ + +//void calibrateOscillator(void); +/* This function calibrates the RC oscillator so that the CPU runs at F_CPU. + * It MUST be called immediately after the end of a USB RESET condition! + * Disable all interrupts during the call! + * It is recommended that you store the resulting value in EEPROM so that a + * good guess value is available after the next reset. + */ + + +#endif /* __OSCCAL_H_INCLUDED__ */ diff --git a/hardware/digistump/avr/libraries/DigiCDC/osctune.h b/hardware/digistump/avr/libraries/DigiCDC/osctune.h new file mode 100644 index 0000000..c751648 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/osctune.h @@ -0,0 +1,88 @@ +/* Name: osctune.h + * Author: Christian Starkjohann + * Creation Date: 2008-10-18 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osctune.h 692 2008-11-07 15:07:40Z cs $ + */ + +/* +General Description: +This file is declared as C-header file although it is mostly documentation +how the RC oscillator can be kept in sync to the USB frame rate. The code +shown here must be added to usbconfig.h or this header file is included from +there. This code works only if D- is wired to the interrupt, not D+!!! + +This is an alternative to the osccal routine in osccal.c. It has the advantage +that the synchronization is done continuously and that it has more compact +code size. The disadvantages are slow synchronization (it may take a while +until the driver works), that messages immediately after the SOF pulse may be +lost (and need to be retried by the host) and that the interrupt is on D- +contrary to most examples. + +You may want to store a good calibration value in EEPROM for the next startup. +You know that the calibration value is good when the first USB message is +received. Do not store the value on every received message because the EEPROM +has a limited endurance. + +Notes: +(*) You must declare the global character variable "lastTimer0Value" in your +main code. + +(*) Timer 0 must be free running (not written by your code) and the prescaling +must be consistent with the TIMER0_PRESCALING define. + +(*) Good values for Timer 0 prescaling depend on how precise the clock must +be tuned and how far away from the default clock rate the target clock is. +For precise tuning, choose a low prescaler factor, for a broad range of tuning +choose a high one. A prescaler factor of 64 is good for the entire OSCCAL +range and allows a precision of better than +/-1%. A prescaler factor of 8 +allows tuning to slightly more than +/-6% of the default frequency and is +more precise than one step of OSCCAL. It is therefore not suitable to tune an +8 MHz oscillator to 12.5 MHz. + +Thanks to Henrik Haftmann for the idea to this routine! +*/ + +#define TIMER0_PRESCALING 64 /* must match the configuration for TIMER0 in main */ +#define TOLERATED_DEVIATION_PPT 5 /* max clock deviation before we tune in 1/10 % */ +/* derived constants: */ +#define EXPECTED_TIMER0_INCREMENT ((F_CPU / (1000 * TIMER0_PRESCALING)) & 0xff) +#define TOLERATED_DEVIATION (TOLERATED_DEVIATION_PPT * F_CPU / (1000000 * TIMER0_PRESCALING)) + +#ifdef __ASSEMBLER__ +macro tuneOsccal + push YH ;[0] + in YL, TCNT0 ;[2] + lds YH, lastTimer0Value ;[3] + sts lastTimer0Value, YL ;[5] + sub YL, YH ;[7] time passed since last frame + subi YL, EXPECTED_TIMER0_INCREMENT ;[8] +#if OSCCAL > 0x3f /* outside I/O addressable range */ + lds YH, OSCCAL ;[6] +#else + in YH, OSCCAL ;[6] assembler modle uses __SFR_OFFSET == 0 +#endif + cpi YL, TOLERATED_DEVIATION + 1 ;[10] + brmi notTooHigh ;[11] + subi YH, 1 ;[12] clock rate was too high +; brcs tuningOverflow ; optionally check for overflow + rjmp osctuneDone ;[13] +notTooHigh: + cpi YL, -TOLERATED_DEVIATION ;[13] + brpl osctuneDone ;[14] not too low + inc YH ;[15] clock rate was too low +; breq tuningOverflow ; optionally check for overflow +osctuneDone: +#if OSCCAL > 0x3f /* outside I/O addressable range */ + sts OSCCAL, YH ;[12-13] store tuned value +#else + out OSCCAL, YH ;[12-13] store tuned value +#endif +tuningOverflow: + pop YH ;[17] + endm ;[19] max number of cycles +#endif + +#define USB_SOF_HOOK tuneOsccal diff --git a/hardware/digistump/avr/libraries/DigiCDC/ringBuffer.h b/hardware/digistump/avr/libraries/DigiCDC/ringBuffer.h new file mode 100644 index 0000000..b0ddddd --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/ringBuffer.h @@ -0,0 +1,87 @@ +/******************************************************************************************************************* +* +* See the http://www.fourwalledcubicle.com/files/LightweightRingBuff.h for the license information. +* +*******************************************************************************************************************/ +#include +#include +#include +/*----------------------------------------------------------------------------------------------------------------*/ +typedef struct +{ + uint8_t* In; /**< Current storage location in the circular buffer. */ + uint8_t* Out; /**< Current retrieval location in the circular buffer. */ + uint8_t* Start; /**< Pointer to the start of the buffer's underlying storage array. */ + uint8_t* End; /**< Pointer to the end of the buffer's underlying storage array. */ + uint16_t Size; /**< Size of the buffer's underlying storage array. */ + uint16_t Count; /**< Number of bytes currently stored in the buffer. */ +} RingBuffer_t; +/*----------------------------------------------------------------------------------------------------------------*/ +static inline void RingBuffer_InitBuffer(RingBuffer_t* Buffer,uint8_t* const DataPtr,const uint16_t Size) +{ + Buffer->In = DataPtr; + Buffer->Out = DataPtr; + Buffer->Start = &DataPtr[0]; + Buffer->End = &DataPtr[Size]; + Buffer->Size = Size; + Buffer->Count = 0; +} +/*----------------------------------------------------------------------------------------------------------------*/ +static inline uint16_t RingBuffer_GetCount(RingBuffer_t* const Buffer) +{ + uint16_t Count; + ATOMIC_BLOCK(ATOMIC_RESTORESTATE) + { + Count = Buffer->Count; + } + return Count; +} +/*----------------------------------------------------------------------------------------------------------------*/ +static inline uint16_t RingBuffer_GetFreeCount(RingBuffer_t* const Buffer) +{ + return (Buffer->Size - RingBuffer_GetCount(Buffer)); +} +/*----------------------------------------------------------------------------------------------------------------*/ +static inline uint8_t RingBuffer_IsEmpty(RingBuffer_t* const Buffer) +{ + return (RingBuffer_GetCount(Buffer) == 0); +} +/*----------------------------------------------------------------------------------------------------------------*/ +static inline uint8_t RingBuffer_IsFull(RingBuffer_t* const Buffer) +{ + return (RingBuffer_GetCount(Buffer) == Buffer->Size); +} +/*----------------------------------------------------------------------------------------------------------------*/ +static inline void RingBuffer_Insert(RingBuffer_t* Buffer, const uint8_t Data) +{ + *Buffer->In = Data; + + if (++Buffer->In == Buffer->End) + Buffer->In = Buffer->Start; + + ATOMIC_BLOCK(ATOMIC_RESTORESTATE) + { + Buffer->Count++; + } +} +/*----------------------------------------------------------------------------------------------------------------*/ +static inline uint8_t RingBuffer_Remove(RingBuffer_t* Buffer) +{ + uint8_t Data = *Buffer->Out; + + if (++Buffer->Out == Buffer->End) + Buffer->Out = Buffer->Start; + + ATOMIC_BLOCK(ATOMIC_RESTORESTATE) + { + Buffer->Count--; + } + + return Data; +} +/*----------------------------------------------------------------------------------------------------------------*/ +static inline uint8_t RingBuffer_Peek(RingBuffer_t* const Buffer) +{ + return *Buffer->Out; +} +/*----------------------------------------------------------------------------------------------------------------*/ diff --git a/hardware/digistump/avr/libraries/DigiCDC/usbconfig-prototype.h b/hardware/digistump/avr/libraries/DigiCDC/usbconfig-prototype.h new file mode 100644 index 0000000..cc2bd77 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/usbconfig-prototype.h @@ -0,0 +1,376 @@ +/* Name: usbconfig.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2005-04-01 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbconfig-prototype.h 785 2010-05-30 17:57:07Z cs $ + */ + +#ifndef __usbconfig_h_included__ +#define __usbconfig_h_included__ + +/* +General Description: +This file is an example configuration (with inline documentation) for the USB +driver. It configures V-USB for USB D+ connected to Port D bit 2 (which is +also hardware interrupt 0 on many devices) and USB D- to Port D bit 4. You may +wire the lines to any other port, as long as D+ is also wired to INT0 (or any +other hardware interrupt, as long as it is the highest level interrupt, see +section at the end of this file). ++ To create your own usbconfig.h file, copy this file to your project's ++ firmware source directory) and rename it to "usbconfig.h". ++ Then edit it accordingly. +*/ + +/* ---------------------------- Hardware Config ---------------------------- */ + +#define USB_CFG_IOPORTNAME D +/* This is the port where the USB bus is connected. When you configure it to + * "B", the registers PORTB, PINB and DDRB will be used. + */ +#define USB_CFG_DMINUS_BIT 4 +/* This is the bit number in USB_CFG_IOPORT where the USB D- line is connected. + * This may be any bit in the port. + */ +#define USB_CFG_DPLUS_BIT 2 +/* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected. + * This may be any bit in the port. Please note that D+ must also be connected + * to interrupt pin INT0! [You can also use other interrupts, see section + * "Optional MCU Description" below, or you can connect D- to the interrupt, as + * it is required if you use the USB_COUNT_SOF feature. If you use D- for the + * interrupt, the USB interrupt will also be triggered at Start-Of-Frame + * markers every millisecond.] + */ +#define USB_CFG_CLOCK_KHZ (F_CPU/1000) +/* Clock rate of the AVR in kHz. Legal values are 12000, 12800, 15000, 16000, + * 16500, 18000 and 20000. The 12.8 MHz and 16.5 MHz versions of the code + * require no crystal, they tolerate +/- 1% deviation from the nominal + * frequency. All other rates require a precision of 2000 ppm and thus a + * crystal! + * Since F_CPU should be defined to your actual clock rate anyway, you should + * not need to modify this setting. + */ +#define USB_CFG_CHECK_CRC 0 +/* Define this to 1 if you want that the driver checks integrity of incoming + * data packets (CRC checks). CRC checks cost quite a bit of code size and are + * currently only available for 18 MHz crystal clock. You must choose + * USB_CFG_CLOCK_KHZ = 18000 if you enable this option. + */ + +/* ----------------------- Optional Hardware Config ------------------------ */ + +/* #define USB_CFG_PULLUP_IOPORTNAME D */ +/* If you connect the 1.5k pullup resistor from D- to a port pin instead of + * V+, you can connect and disconnect the device from firmware by calling + * the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h). + * This constant defines the port on which the pullup resistor is connected. + */ +/* #define USB_CFG_PULLUP_BIT 4 */ +/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined + * above) where the 1.5k pullup resistor is connected. See description + * above for details. + */ + +/* --------------------------- Functional Range ---------------------------- */ + +#define USB_CFG_HAVE_INTRIN_ENDPOINT 0 +/* Define this to 1 if you want to compile a version with two endpoints: The + * default control endpoint 0 and an interrupt-in endpoint (any other endpoint + * number). + */ +#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0 +/* Define this to 1 if you want to compile a version with three endpoints: The + * default control endpoint 0, an interrupt-in endpoint 3 (or the number + * configured below) and a catch-all default interrupt-in endpoint as above. + * You must also define USB_CFG_HAVE_INTRIN_ENDPOINT to 1 for this feature. + */ +#define USB_CFG_EP3_NUMBER 3 +/* If the so-called endpoint 3 is used, it can now be configured to any other + * endpoint number (except 0) with this macro. Default if undefined is 3. + */ +/* #define USB_INITIAL_DATATOKEN USBPID_DATA1 */ +/* The above macro defines the startup condition for data toggling on the + * interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA1. + * Since the token is toggled BEFORE sending any data, the first packet is + * sent with the oposite value of this configuration! + */ +#define USB_CFG_IMPLEMENT_HALT 0 +/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature + * for endpoint 1 (interrupt endpoint). Although you may not need this feature, + * it is required by the standard. We have made it a config option because it + * bloats the code considerably. + */ +#define USB_CFG_SUPPRESS_INTR_CODE 0 +/* Define this to 1 if you want to declare interrupt-in endpoints, but don't + * want to send any data over them. If this macro is defined to 1, functions + * usbSetInterrupt() and usbSetInterrupt3() are omitted. This is useful if + * you need the interrupt-in endpoints in order to comply to an interface + * (e.g. HID), but never want to send any data. This option saves a couple + * of bytes in flash memory and the transmit buffers in RAM. + */ +#define USB_CFG_INTR_POLL_INTERVAL 10 +/* If you compile a version with endpoint 1 (interrupt-in), this is the poll + * interval. The value is in milliseconds and must not be less than 10 ms for + * low speed devices. + */ +#define USB_CFG_IS_SELF_POWERED 0 +/* Define this to 1 if the device has its own power supply. Set it to 0 if the + * device is powered from the USB bus. + */ +#define USB_CFG_MAX_BUS_POWER 100 +/* Set this variable to the maximum USB bus power consumption of your device. + * The value is in milliamperes. [It will be divided by two since USB + * communicates power requirements in units of 2 mA.] + */ +#define USB_CFG_IMPLEMENT_FN_WRITE 0 +/* Set this to 1 if you want usbFunctionWrite() to be called for control-out + * transfers. Set it to 0 if you don't need it and want to save a couple of + * bytes. + */ +#define USB_CFG_IMPLEMENT_FN_READ 0 +/* Set this to 1 if you need to send control replies which are generated + * "on the fly" when usbFunctionRead() is called. If you only want to send + * data from a static buffer, set it to 0 and return the data from + * usbFunctionSetup(). This saves a couple of bytes. + */ +#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0 +/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints. + * You must implement the function usbFunctionWriteOut() which receives all + * interrupt/bulk data sent to any endpoint other than 0. The endpoint number + * can be found in 'usbRxToken'. + */ +#define USB_CFG_HAVE_FLOWCONTROL 0 +/* Define this to 1 if you want flowcontrol over USB data. See the definition + * of the macros usbDisableAllRequests() and usbEnableAllRequests() in + * usbdrv.h. + */ +#define USB_CFG_DRIVER_FLASH_PAGE 0 +/* If the device has more than 64 kBytes of flash, define this to the 64 k page + * where the driver's constants (descriptors) are located. Or in other words: + * Define this to 1 for boot loaders on the ATMega128. + */ +#define USB_CFG_LONG_TRANSFERS 0 +/* Define this to 1 if you want to send/receive blocks of more than 254 bytes + * in a single control-in or control-out transfer. Note that the capability + * for long transfers increases the driver size. + */ +/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */ +/* This macro is a hook if you want to do unconventional things. If it is + * defined, it's inserted at the beginning of received message processing. + * If you eat the received message and don't want default processing to + * proceed, do a return after doing your things. One possible application + * (besides debugging) is to flash a status LED on each packet. + */ +/* #define USB_RESET_HOOK(resetStarts) if(!resetStarts){hadUsbReset();} */ +/* This macro is a hook if you need to know when an USB RESET occurs. It has + * one parameter which distinguishes between the start of RESET state and its + * end. + */ +/* #define USB_SET_ADDRESS_HOOK() hadAddressAssigned(); */ +/* This macro (if defined) is executed when a USB SET_ADDRESS request was + * received. + */ +#define USB_COUNT_SOF 0 +/* define this macro to 1 if you need the global variable "usbSofCount" which + * counts SOF packets. This feature requires that the hardware interrupt is + * connected to D- instead of D+. + */ +/* #ifdef __ASSEMBLER__ + * macro myAssemblerMacro + * in YL, TCNT0 + * sts timer0Snapshot, YL + * endm + * #endif + * #define USB_SOF_HOOK myAssemblerMacro + * This macro (if defined) is executed in the assembler module when a + * Start Of Frame condition is detected. It is recommended to define it to + * the name of an assembler macro which is defined here as well so that more + * than one assembler instruction can be used. The macro may use the register + * YL and modify SREG. If it lasts longer than a couple of cycles, USB messages + * immediately after an SOF pulse may be lost and must be retried by the host. + * What can you do with this hook? Since the SOF signal occurs exactly every + * 1 ms (unless the host is in sleep mode), you can use it to tune OSCCAL in + * designs running on the internal RC oscillator. + * Please note that Start Of Frame detection works only if D- is wired to the + * interrupt, not D+. THIS IS DIFFERENT THAN MOST EXAMPLES! + */ +#define USB_CFG_CHECK_DATA_TOGGLING 0 +/* define this macro to 1 if you want to filter out duplicate data packets + * sent by the host. Duplicates occur only as a consequence of communication + * errors, when the host does not receive an ACK. Please note that you need to + * implement the filtering yourself in usbFunctionWriteOut() and + * usbFunctionWrite(). Use the global usbCurrentDataToken and a static variable + * for each control- and out-endpoint to check for duplicate packets. + */ +#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 0 +/* define this macro to 1 if you want the function usbMeasureFrameLength() + * compiled in. This function can be used to calibrate the AVR's RC oscillator. + */ +#define USB_USE_FAST_CRC 0 +/* The assembler module has two implementations for the CRC algorithm. One is + * faster, the other is smaller. This CRC routine is only used for transmitted + * messages where timing is not critical. The faster routine needs 31 cycles + * per byte while the smaller one needs 61 to 69 cycles. The faster routine + * may be worth the 32 bytes bigger code size if you transmit lots of data and + * run the AVR close to its limit. + */ + +/* -------------------------- Device Description --------------------------- */ + +#define USB_CFG_VENDOR_ID 0xc0, 0x16 /* = 0x16c0 = 5824 = voti.nl */ +/* USB vendor ID for the device, low byte first. If you have registered your + * own Vendor ID, define it here. Otherwise you may use one of obdev's free + * shared VID/PID pairs. Be sure to read USB-IDs-for-free.txt for rules! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_ID 0xdc, 0x05 /* = 0x05dc = 1500 */ +/* This is the ID of the product, low byte first. It is interpreted in the + * scope of the vendor ID. If you have registered your own VID with usb.org + * or if you have licensed a PID from somebody else, define it here. Otherwise + * you may use one of obdev's free shared VID/PID pairs. See the file + * USB-IDs-for-free.txt for details! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_VERSION 0x00, 0x01 +/* Version number of the device: Minor number first, then major number. + */ +#define USB_CFG_VENDOR_NAME 'o', 'b', 'd', 'e', 'v', '.', 'a', 't' +#define USB_CFG_VENDOR_NAME_LEN 8 +/* These two values define the vendor name returned by the USB device. The name + * must be given as a list of characters under single quotes. The characters + * are interpreted as Unicode (UTF-16) entities. + * If you don't want a vendor name string, undefine these macros. + * ALWAYS define a vendor name containing your Internet domain name if you use + * obdev's free shared VID/PID pair. See the file USB-IDs-for-free.txt for + * details. + */ +#define USB_CFG_DEVICE_NAME 'T', 'e', 'm', 'p', 'l', 'a', 't', 'e' +#define USB_CFG_DEVICE_NAME_LEN 8 +/* Same as above for the device name. If you don't want a device name, undefine + * the macros. See the file USB-IDs-for-free.txt before you assign a name if + * you use a shared VID/PID. + */ +/*#define USB_CFG_SERIAL_NUMBER 'N', 'o', 'n', 'e' */ +/*#define USB_CFG_SERIAL_NUMBER_LEN 0 */ +/* Same as above for the serial number. If you don't want a serial number, + * undefine the macros. + * It may be useful to provide the serial number through other means than at + * compile time. See the section about descriptor properties below for how + * to fine tune control over USB descriptors such as the string descriptor + * for the serial number. + */ +#define USB_CFG_DEVICE_CLASS 0xff /* set to 0 if deferred to interface */ +#define USB_CFG_DEVICE_SUBCLASS 0 +/* See USB specification if you want to conform to an existing device class. + * Class 0xff is "vendor specific". + */ +#define USB_CFG_INTERFACE_CLASS 0 /* define class here if not at device level */ +#define USB_CFG_INTERFACE_SUBCLASS 0 +#define USB_CFG_INTERFACE_PROTOCOL 0 +/* See USB specification if you want to conform to an existing device class or + * protocol. The following classes must be set at interface level: + * HID class is 3, no subclass and protocol required (but may be useful!) + * CDC class is 2, use subclass 2 and protocol 1 for ACM + */ +/* #define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 42 */ +/* Define this to the length of the HID report descriptor, if you implement + * an HID device. Otherwise don't define it or define it to 0. + * If you use this define, you must add a const PROGMEM character array named + * "usbHidReportDescriptor" to your code which contains the report descriptor. + * Don't forget to keep the array and this define in sync! + */ + +/* #define USB_PUBLIC static */ +/* Use the define above if you #include usbdrv.c instead of linking against it. + * This technique saves a couple of bytes in flash memory. + */ + +/* ------------------- Fine Control over USB Descriptors ------------------- */ +/* If you don't want to use the driver's default USB descriptors, you can + * provide our own. These can be provided as (1) fixed length static data in + * flash memory, (2) fixed length static data in RAM or (3) dynamically at + * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more + * information about this function. + * Descriptor handling is configured through the descriptor's properties. If + * no properties are defined or if they are 0, the default descriptor is used. + * Possible properties are: + * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched + * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is + * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if + * you want RAM pointers. + * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found + * in static memory is in RAM, not in flash memory. + * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash), + * the driver must know the descriptor's length. The descriptor itself is + * found at the address of a well known identifier (see below). + * List of static descriptor names (must be declared const PROGMEM if in flash): + * char usbDescriptorDevice[]; + * char usbDescriptorConfiguration[]; + * char usbDescriptorHidReport[]; + * char usbDescriptorString0[]; + * int usbDescriptorStringVendor[]; + * int usbDescriptorStringDevice[]; + * int usbDescriptorStringSerialNumber[]; + * Other descriptors can't be provided statically, they must be provided + * dynamically at runtime. + * + * Descriptor properties are or-ed or added together, e.g.: + * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18)) + * + * The following descriptors are defined: + * USB_CFG_DESCR_PROPS_DEVICE + * USB_CFG_DESCR_PROPS_CONFIGURATION + * USB_CFG_DESCR_PROPS_STRINGS + * USB_CFG_DESCR_PROPS_STRING_0 + * USB_CFG_DESCR_PROPS_STRING_VENDOR + * USB_CFG_DESCR_PROPS_STRING_PRODUCT + * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER + * USB_CFG_DESCR_PROPS_HID + * USB_CFG_DESCR_PROPS_HID_REPORT + * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver) + * + * Note about string descriptors: String descriptors are not just strings, they + * are Unicode strings prefixed with a 2 byte header. Example: + * int serialNumberDescriptor[] = { + * USB_STRING_DESCRIPTOR_HEADER(6), + * 'S', 'e', 'r', 'i', 'a', 'l' + * }; + */ + +#define USB_CFG_DESCR_PROPS_DEVICE 0 +#define USB_CFG_DESCR_PROPS_CONFIGURATION 0 +#define USB_CFG_DESCR_PROPS_STRINGS 0 +#define USB_CFG_DESCR_PROPS_STRING_0 0 +#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0 +#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0 +#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0 +#define USB_CFG_DESCR_PROPS_HID 0 +#define USB_CFG_DESCR_PROPS_HID_REPORT 0 +#define USB_CFG_DESCR_PROPS_UNKNOWN 0 + +/* ----------------------- Optional MCU Description ------------------------ */ + +/* The following configurations have working defaults in usbdrv.h. You + * usually don't need to set them explicitly. Only if you want to run + * the driver on a device which is not yet supported or with a compiler + * which is not fully supported (such as IAR C) or if you use a differnt + * interrupt than INT0, you may have to define some of these. + */ +/* #define USB_INTR_CFG MCUCR */ +/* #define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) */ +/* #define USB_INTR_CFG_CLR 0 */ +/* #define USB_INTR_ENABLE GIMSK */ +/* #define USB_INTR_ENABLE_BIT INT0 */ +/* #define USB_INTR_PENDING GIFR */ +/* #define USB_INTR_PENDING_BIT INTF0 */ +/* #define USB_INTR_VECTOR INT0_vect */ + +#endif /* __usbconfig_h_included__ */ diff --git a/hardware/digistump/avr/libraries/DigiCDC/usbconfig.h b/hardware/digistump/avr/libraries/DigiCDC/usbconfig.h new file mode 100644 index 0000000..0ccc9f2 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/usbconfig.h @@ -0,0 +1,438 @@ +/* Name: usbconfig.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2005-04-01 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbconfig-prototype.h 785 2010-05-30 17:57:07Z cs $ + */ + +#ifndef __usbconfig_h_included__ +#define __usbconfig_h_included__ + +/* +General Description: +This file is an example configuration (with inline documentation) for the USB +driver. It configures V-USB for USB D+ connected to Port D bit 2 (which is +also hardware interrupt 0 on many devices) and USB D- to Port D bit 4. You may +wire the lines to any other port, as long as D+ is also wired to INT0 (or any +other hardware interrupt, as long as it is the highest level interrupt, see +section at the end of this file). ++ To create your own usbconfig.h file, copy this file to your project's ++ firmware source directory) and rename it to "usbconfig.h". ++ Then edit it accordingly. +*/ + +/* ---------------------------- Hardware Config ---------------------------- */ + +/* #define USB_CFG_IOPORTNAME D */ +/* This is the port where the USB bus is connected. When you configure it to + * "B", the registers PORTB, PINB and DDRB will be used. + */ +/* #define USB_CFG_DMINUS_BIT 4 */ +/* This is the bit number in USB_CFG_IOPORT where the USB D- line is connected. + * This may be any bit in the port. + */ +/* #define USB_CFG_DPLUS_BIT 2 */ +/* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected. + * This may be any bit in the port. Please note that D+ must also be connected + * to interrupt pin INT0! [You can also use other interrupts, see section + * "Optional MCU Description" below, or you can connect D- to the interrupt, as + * it is required if you use the USB_COUNT_SOF feature. If you use D- for the + * interrupt, the USB interrupt will also be triggered at Start-Of-Frame + * markers every millisecond.] + */ +#if defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 1 +#define USB_CFG_DPLUS_BIT 2 + +#elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 4 + +#elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 6 + +#elif defined (__AVR_ATtiny461__) || defined (__AVR_ATtiny861__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 5 +#define USB_CFG_DPLUS_BIT 6 +#else +/* ATtiny2313, ATmega8/48/88/168 */ +#define USB_CFG_IOPORTNAME D +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 2 +#endif + +#define USB_CFG_CLOCK_KHZ (F_CPU/1000) +/* Clock rate of the AVR in kHz. Legal values are 12000, 12800, 15000, 16000, + * 16500, 18000 and 20000. The 12.8 MHz and 16.5 MHz versions of the code + * require no crystal, they tolerate +/- 1% deviation from the nominal + * frequency. All other rates require a precision of 2000 ppm and thus a + * crystal! + * Since F_CPU should be defined to your actual clock rate anyway, you should + * not need to modify this setting. + */ +#if USB_CFG_CLOCK_KHZ==18000 +#define USB_CFG_CHECK_CRC 1 +#else +#define USB_CFG_CHECK_CRC 0 +#endif + +/* Define this to 1 if you want that the driver checks integrity of incoming + * data packets (CRC checks). CRC checks cost quite a bit of code size and are + * currently only available for 18 MHz crystal clock. You must choose + * USB_CFG_CLOCK_KHZ = 18000 if you enable this option. + */ + +/* ----------------------- Optional Hardware Config ------------------------ */ + +/* #define USB_CFG_PULLUP_IOPORTNAME D */ +/* If you connect the 1.5k pullup resistor from D- to a port pin instead of + * V+, you can connect and disconnect the device from firmware by calling + * the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h). + * This constant defines the port on which the pullup resistor is connected. + */ +/* #define USB_CFG_PULLUP_BIT 4 */ +/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined + * above) where the 1.5k pullup resistor is connected. See description + * above for details. + */ + +/* --------------------------- Functional Range ---------------------------- */ + +#define USB_CFG_HAVE_INTRIN_ENDPOINT 1 +/* Define this to 1 if you want to compile a version with two endpoints: The + * default control endpoint 0 and an interrupt-in endpoint (any other endpoint + * number). + */ +#define USB_CFG_HAVE_INTRIN_ENDPOINT3 1 +/* Define this to 1 if you want to compile a version with three endpoints: The + * default control endpoint 0, an interrupt-in endpoint 3 (or the number + * configured below) and a catch-all default interrupt-in endpoint as above. + * You must also define USB_CFG_HAVE_INTRIN_ENDPOINT to 1 for this feature. + */ +#define USB_CFG_EP3_NUMBER 3 +/* If the so-called endpoint 3 is used, it can now be configured to any other + * endpoint number (except 0) with this macro. Default if undefined is 3. + */ +/* #define USB_INITIAL_DATATOKEN USBPID_DATA1 */ +/* The above macro defines the startup condition for data toggling on the + * interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA1. + * Since the token is toggled BEFORE sending any data, the first packet is + * sent with the oposite value of this configuration! + */ +#define USB_CFG_IMPLEMENT_HALT 0 +/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature + * for endpoint 1 (interrupt endpoint). Although you may not need this feature, + * it is required by the standard. We have made it a config option because it + * bloats the code considerably. + */ +#define USB_CFG_SUPPRESS_INTR_CODE 0 +/* Define this to 1 if you want to declare interrupt-in endpoints, but don't + * want to send any data over them. If this macro is defined to 1, functions + * usbSetInterrupt() and usbSetInterrupt3() are omitted. This is useful if + * you need the interrupt-in endpoints in order to comply to an interface + * (e.g. HID), but never want to send any data. This option saves a couple + * of bytes in flash memory and the transmit buffers in RAM. + */ +#define USB_CFG_INTR_POLL_INTERVAL 255 +/* If you compile a version with endpoint 1 (interrupt-in), this is the poll + * interval. The value is in milliseconds and must not be less than 10 ms for + * low speed devices. + */ +#define USB_CFG_IS_SELF_POWERED 0 +/* Define this to 1 if the device has its own power supply. Set it to 0 if the + * device is powered from the USB bus. + */ +#define USB_CFG_MAX_BUS_POWER 100 +/* Set this variable to the maximum USB bus power consumption of your device. + * The value is in milliamperes. [It will be divided by two since USB + * communicates power requirements in units of 2 mA.] + */ +#define USB_CFG_IMPLEMENT_FN_WRITE 1 +/* Set this to 1 if you want usbFunctionWrite() to be called for control-out + * transfers. Set it to 0 if you don't need it and want to save a couple of + * bytes. + */ +#define USB_CFG_IMPLEMENT_FN_READ 1 +/* Set this to 1 if you need to send control replies which are generated + * "on the fly" when usbFunctionRead() is called. If you only want to send + * data from a static buffer, set it to 0 and return the data from + * usbFunctionSetup(). This saves a couple of bytes. + */ +#define USB_CFG_IMPLEMENT_FN_WRITEOUT 1 +/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints. + * You must implement the function usbFunctionWriteOut() which receives all + * interrupt/bulk data sent to any endpoint other than 0. The endpoint number + * can be found in 'usbRxToken'. + */ +#define USB_CFG_HAVE_FLOWCONTROL 1 +/* Define this to 1 if you want flowcontrol over USB data. See the definition + * of the macros usbDisableAllRequests() and usbEnableAllRequests() in + * usbdrv.h. + */ +#define USB_CFG_DRIVER_FLASH_PAGE 0 +/* If the device has more than 64 kBytes of flash, define this to the 64 k page + * where the driver's constants (descriptors) are located. Or in other words: + * Define this to 1 for boot loaders on the ATMega128. + */ +#define USB_CFG_LONG_TRANSFERS 0 +/* Define this to 1 if you want to send/receive blocks of more than 254 bytes + * in a single control-in or control-out transfer. Note that the capability + * for long transfers increases the driver size. + */ +/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */ +/* This macro is a hook if you want to do unconventional things. If it is + * defined, it's inserted at the beginning of received message processing. + * If you eat the received message and don't want default processing to + * proceed, do a return after doing your things. One possible application + * (besides debugging) is to flash a status LED on each packet. + */ +/* #define USB_RESET_HOOK(resetStarts) if(!resetStarts){hadUsbReset();} */ +/* This macro is a hook if you need to know when an USB RESET occurs. It has + * one parameter which distinguishes between the start of RESET state and its + * end. + */ +/* #define USB_SET_ADDRESS_HOOK() hadAddressAssigned(); */ +/* This macro (if defined) is executed when a USB SET_ADDRESS request was + * received. + */ +#define USB_COUNT_SOF 0 +/* define this macro to 1 if you need the global variable "usbSofCount" which + * counts SOF packets. This feature requires that the hardware interrupt is + * connected to D- instead of D+. + */ +/* #ifdef __ASSEMBLER__ + * macro myAssemblerMacro + * in YL, TCNT0 + * sts timer0Snapshot, YL + * endm + * #endif + * #define USB_SOF_HOOK myAssemblerMacro + * This macro (if defined) is executed in the assembler module when a + * Start Of Frame condition is detected. It is recommended to define it to + * the name of an assembler macro which is defined here as well so that more + * than one assembler instruction can be used. The macro may use the register + * YL and modify SREG. If it lasts longer than a couple of cycles, USB messages + * immediately after an SOF pulse may be lost and must be retried by the host. + * What can you do with this hook? Since the SOF signal occurs exactly every + * 1 ms (unless the host is in sleep mode), you can use it to tune OSCCAL in + * designs running on the internal RC oscillator. + * Please note that Start Of Frame detection works only if D- is wired to the + * interrupt, not D+. THIS IS DIFFERENT THAN MOST EXAMPLES! + */ +#define USB_CFG_CHECK_DATA_TOGGLING 0 +/* define this macro to 1 if you want to filter out duplicate data packets + * sent by the host. Duplicates occur only as a consequence of communication + * errors, when the host does not receive an ACK. Please note that you need to + * implement the filtering yourself in usbFunctionWriteOut() and + * usbFunctionWrite(). Use the global usbCurrentDataToken and a static variable + * for each control- and out-endpoint to check for duplicate packets. + */ + +#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 1 +#include "osccal.h" + +/* define this macro to 1 if you want the function usbMeasureFrameLength() + * compiled in. This function can be used to calibrate the AVR's RC oscillator. + */ +#define USB_USE_FAST_CRC 0 +/* The assembler module has two implementations for the CRC algorithm. One is + * faster, the other is smaller. This CRC routine is only used for transmitted + * messages where timing is not critical. The faster routine needs 31 cycles + * per byte while the smaller one needs 61 to 69 cycles. The faster routine + * may be worth the 32 bytes bigger code size if you transmit lots of data and + * run the AVR close to its limit. + */ + +/* -------------------------- Device Description --------------------------- */ + +#define USB_CFG_VENDOR_ID 0xd0, 0x16 /* = 0x16c0 = 5824 = voti.nl */ +/* USB vendor ID for the device, low byte first. If you have registered your + * own Vendor ID, define it here. Otherwise you may use one of obdev's free + * shared VID/PID pairs. Be sure to read USB-IDs-for-free.txt for rules! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_ID 0x7e, 0x08 /* = 0x05e1 = 1505 */ +/* This is the ID of the product, low byte first. It is interpreted in the + * scope of the vendor ID. If you have registered your own VID with usb.org + * or if you have licensed a PID from somebody else, define it here. Otherwise + * you may use one of obdev's free shared VID/PID pairs. See the file + * USB-IDs-for-free.txt for details! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_VERSION 0x00, 0x01 +/* Version number of the device: Minor number first, then major number. + */ +#define USB_CFG_VENDOR_NAME 'd','i','g','i','s','t','u','m','p','.','c','o','m' +#define USB_CFG_VENDOR_NAME_LEN 13 +/* These two values define the vendor name returned by the USB device. The name + * must be given as a list of characters under single quotes. The characters + * are interpreted as Unicode (UTF-16) entities. + * If you don't want a vendor name string, undefine these macros. + * ALWAYS define a vendor name containing your Internet domain name if you use + * obdev's free shared VID/PID pair. See the file USB-IDs-for-free.txt for + * details. + */ + + +#define USB_CFG_DEVICE_NAME 'D','i','g','i','s','p','a','r','k',' ','S','e','r','i','a','l' +#define USB_CFG_DEVICE_NAME_LEN 16 + + +/* Same as above for the device name. If you don't want a device name, undefine + * the macros. See the file USB-IDs-for-free.txt before you assign a name if + * you use a shared VID/PID. + */ +/*#define USB_CFG_SERIAL_NUMBER 'N', 'o', 'n', 'e' */ +/*#define USB_CFG_SERIAL_NUMBER_LEN 0 */ +/* Same as above for the serial number. If you don't want a serial number, + * undefine the macros. + * It may be useful to provide the serial number through other means than at + * compile time. See the section about descriptor properties below for how + * to fine tune control over USB descriptors such as the string descriptor + * for the serial number. + */ +#define USB_CFG_DEVICE_CLASS 2 /* set to 0 if deferred to interface */ +#define USB_CFG_DEVICE_SUBCLASS 0 +/* See USB specification if you want to conform to an existing device class. + * Class 0xff is "vendor specific". + */ +#define USB_CFG_INTERFACE_CLASS 2 /* CDC class */ +#define USB_CFG_INTERFACE_SUBCLASS 2 /* Abstract (Modem) */ +#define USB_CFG_INTERFACE_PROTOCOL 1 /* AT-Commands */ +/* See USB specification if you want to conform to an existing device class or + * protocol. The following classes must be set at interface level: + * HID class is 3, no subclass and protocol required (but may be useful!) + * CDC class is 2, use subclass 2 and protocol 1 for ACM + */ +/* #define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 42 */ +/* Define this to the length of the HID report descriptor, if you implement + * an HID device. Otherwise don't define it or define it to 0. + * If you use this define, you must add a const PROGMEM character array named + * "usbHidReportDescriptor" to your code which contains the report descriptor. + * Don't forget to keep the array and this define in sync! + */ + +/* #define USB_PUBLIC static */ +/* Use the define above if you #include usbdrv.c instead of linking against it. + * This technique saves a couple of bytes in flash memory. + */ + +/* ------------------- Fine Control over USB Descriptors ------------------- */ +/* If you don't want to use the driver's default USB descriptors, you can + * provide our own. These can be provided as (1) fixed length static data in + * flash memory, (2) fixed length static data in RAM or (3) dynamically at + * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more + * information about this function. + * Descriptor handling is configured through the descriptor's properties. If + * no properties are defined or if they are 0, the default descriptor is used. + * Possible properties are: + * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched + * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is + * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if + * you want RAM pointers. + * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found + * in static memory is in RAM, not in flash memory. + * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash), + * the driver must know the descriptor's length. The descriptor itself is + * found at the address of a well known identifier (see below). + * List of static descriptor names (must be declared const PROGMEM if in flash): + * char usbDescriptorDevice[]; + * char usbDescriptorConfiguration[]; + * char usbDescriptorHidReport[]; + * char usbDescriptorString0[]; + * int usbDescriptorStringVendor[]; + * int usbDescriptorStringDevice[]; + * int usbDescriptorStringSerialNumber[]; + * Other descriptors can't be provided statically, they must be provided + * dynamically at runtime. + * + * Descriptor properties are or-ed or added together, e.g.: + * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18)) + * + * The following descriptors are defined: + * USB_CFG_DESCR_PROPS_DEVICE + * USB_CFG_DESCR_PROPS_CONFIGURATION + * USB_CFG_DESCR_PROPS_STRINGS + * USB_CFG_DESCR_PROPS_STRING_0 + * USB_CFG_DESCR_PROPS_STRING_VENDOR + * USB_CFG_DESCR_PROPS_STRING_PRODUCT + * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER + * USB_CFG_DESCR_PROPS_HID + * USB_CFG_DESCR_PROPS_HID_REPORT + * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver) + * + * Note about string descriptors: String descriptors are not just strings, they + * are Unicode strings prefixed with a 2 byte header. Example: + * int serialNumberDescriptor[] = { + * USB_STRING_DESCRIPTOR_HEADER(6), + * 'S', 'e', 'r', 'i', 'a', 'l' + * }; + */ + +#define USB_CFG_DESCR_PROPS_DEVICE 0 +#define USB_CFG_DESCR_PROPS_CONFIGURATION USB_PROP_IS_DYNAMIC +#define USB_CFG_DESCR_PROPS_STRINGS 0 +#define USB_CFG_DESCR_PROPS_STRING_0 0 +#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0 +#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0 +#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0 +#define USB_CFG_DESCR_PROPS_HID 0 +#define USB_CFG_DESCR_PROPS_HID_REPORT 0 +#define USB_CFG_DESCR_PROPS_UNKNOWN 0 + +/* ----------------------- Optional MCU Description ------------------------ */ + +/* ATmega***p/pa needs SIG_ definitions */ +#ifndef SIG_INTERRUPT0 +#define SIG_INTERRUPT0 _VECTOR(1) +#endif + +/* The following configurations have working defaults in usbdrv.h. You + * usually don't need to set them explicitly. Only if you want to run + * the driver on a device which is not yet supported or with a compiler + * which is not fully supported (such as IAR C) or if you use a differnt + * interrupt than INT0, you may have to define some of these. + */ +/* #define USB_INTR_CFG MCUCR */ +/* #define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) */ +/* #define USB_INTR_CFG_CLR 0 */ +/* #define USB_INTR_ENABLE GIMSK */ +/* #define USB_INTR_ENABLE_BIT INT0 */ +/* #define USB_INTR_PENDING GIFR */ +/* #define USB_INTR_PENDING_BIT INTF0 */ +/* #define USB_INTR_VECTOR INT0_vect */ + + #if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define USB_INTR_CFG PCMSK +#define USB_INTR_CFG_SET (1<len & 0x10){ /* packet buffer was empty */ + txStatus->buffer[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */ + }else{ + txStatus->len = USBPID_NAK; /* avoid sending outdated (overwritten) interrupt data */ + } + p = txStatus->buffer + 1; + i = len; + do{ /* if len == 0, we still copy 1 byte, but that's no problem */ + *p++ = *data++; + }while(--i > 0); /* loop control at the end is 2 bytes shorter than at beginning */ + usbCrc16Append(&txStatus->buffer[1], len); + txStatus->len = len + 4; /* len must be given including sync byte */ + DBG2(0x21 + (((int)txStatus >> 3) & 3), txStatus->buffer, len + 3); +} + +USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len) +{ + usbGenericSetInterrupt(data, len, &usbTxStatus1); +} +#endif + +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 +USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len) +{ + usbGenericSetInterrupt(data, len, &usbTxStatus3); +} +#endif +#endif /* USB_CFG_SUPPRESS_INTR_CODE */ + +/* ------------------ utilities for code following below ------------------- */ + +/* Use defines for the switch statement so that we can choose between an + * if()else if() and a switch/case based implementation. switch() is more + * efficient for a LARGE set of sequential choices, if() is better in all other + * cases. + */ +#if USB_CFG_USE_SWITCH_STATEMENT +# define SWITCH_START(cmd) switch(cmd){{ +# define SWITCH_CASE(value) }break; case (value):{ +# define SWITCH_CASE2(v1,v2) }break; case (v1): case(v2):{ +# define SWITCH_CASE3(v1,v2,v3) }break; case (v1): case(v2): case(v3):{ +# define SWITCH_DEFAULT }break; default:{ +# define SWITCH_END }} +#else +# define SWITCH_START(cmd) {uchar _cmd = cmd; if(0){ +# define SWITCH_CASE(value) }else if(_cmd == (value)){ +# define SWITCH_CASE2(v1,v2) }else if(_cmd == (v1) || _cmd == (v2)){ +# define SWITCH_CASE3(v1,v2,v3) }else if(_cmd == (v1) || _cmd == (v2) || (_cmd == v3)){ +# define SWITCH_DEFAULT }else{ +# define SWITCH_END }} +#endif + +#ifndef USB_RX_USER_HOOK +#define USB_RX_USER_HOOK(data, len) +#endif +#ifndef USB_SET_ADDRESS_HOOK +#define USB_SET_ADDRESS_HOOK() +#endif + +/* ------------------------------------------------------------------------- */ + +/* We use if() instead of #if in the macro below because #if can't be used + * in macros and the compiler optimizes constant conditions anyway. + * This may cause problems with undefined symbols if compiled without + * optimizing! + */ +#define GET_DESCRIPTOR(cfgProp, staticName) \ + if(cfgProp){ \ + if((cfgProp) & USB_PROP_IS_RAM) \ + flags = 0; \ + if((cfgProp) & USB_PROP_IS_DYNAMIC){ \ + len = usbFunctionDescriptor(rq); \ + }else{ \ + len = USB_PROP_LENGTH(cfgProp); \ + usbMsgPtr = (uchar *)(staticName); \ + } \ + } + +/* usbDriverDescriptor() is similar to usbFunctionDescriptor(), but used + * internally for all types of descriptors. + */ +static inline usbMsgLen_t usbDriverDescriptor(usbRequest_t *rq) +{ +usbMsgLen_t len = 0; +uchar flags = USB_FLG_MSGPTR_IS_ROM; + + SWITCH_START(rq->wValue.bytes[1]) + SWITCH_CASE(USBDESCR_DEVICE) /* 1 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_DEVICE, usbDescriptorDevice) + SWITCH_CASE(USBDESCR_CONFIG) /* 2 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_CONFIGURATION, usbDescriptorConfiguration) + SWITCH_CASE(USBDESCR_STRING) /* 3 */ +#if USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC + if(USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_RAM) + flags = 0; + len = usbFunctionDescriptor(rq); +#else /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */ + SWITCH_START(rq->wValue.bytes[0]) + SWITCH_CASE(0) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_0, usbDescriptorString0) + SWITCH_CASE(1) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_VENDOR, usbDescriptorStringVendor) + SWITCH_CASE(2) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_PRODUCT, usbDescriptorStringDevice) + SWITCH_CASE(3) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER, usbDescriptorStringSerialNumber) + SWITCH_DEFAULT + if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){ + len = usbFunctionDescriptor(rq); + } + SWITCH_END +#endif /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */ +#if USB_CFG_DESCR_PROPS_HID_REPORT /* only support HID descriptors if enabled */ + SWITCH_CASE(USBDESCR_HID) /* 0x21 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID, usbDescriptorConfiguration + 18) + SWITCH_CASE(USBDESCR_HID_REPORT)/* 0x22 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID_REPORT, usbDescriptorHidReport) +#endif + SWITCH_DEFAULT + if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){ + len = usbFunctionDescriptor(rq); + } + SWITCH_END + usbMsgFlags = flags; + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbDriverSetup() is similar to usbFunctionSetup(), but it's used for + * standard requests instead of class and custom requests. + */ +static inline usbMsgLen_t usbDriverSetup(usbRequest_t *rq) +{ +uchar len = 0, *dataPtr = usbTxBuf + 9; /* there are 2 bytes free space at the end of the buffer */ +uchar value = rq->wValue.bytes[0]; +#if USB_CFG_IMPLEMENT_HALT +uchar index = rq->wIndex.bytes[0]; +#endif + + dataPtr[0] = 0; /* default reply common to USBRQ_GET_STATUS and USBRQ_GET_INTERFACE */ + SWITCH_START(rq->bRequest) + SWITCH_CASE(USBRQ_GET_STATUS) /* 0 */ + uchar recipient = rq->bmRequestType & USBRQ_RCPT_MASK; /* assign arith ops to variables to enforce byte size */ + if(USB_CFG_IS_SELF_POWERED && recipient == USBRQ_RCPT_DEVICE) + dataPtr[0] = USB_CFG_IS_SELF_POWERED; +#if USB_CFG_IMPLEMENT_HALT + if(recipient == USBRQ_RCPT_ENDPOINT && index == 0x81) /* request status for endpoint 1 */ + dataPtr[0] = usbTxLen1 == USBPID_STALL; +#endif + dataPtr[1] = 0; + len = 2; +#if USB_CFG_IMPLEMENT_HALT + SWITCH_CASE2(USBRQ_CLEAR_FEATURE, USBRQ_SET_FEATURE) /* 1, 3 */ + if(value == 0 && index == 0x81){ /* feature 0 == HALT for endpoint == 1 */ + usbTxLen1 = rq->bRequest == USBRQ_CLEAR_FEATURE ? USBPID_NAK : USBPID_STALL; + usbResetDataToggling(); + } +#endif + SWITCH_CASE(USBRQ_SET_ADDRESS) /* 5 */ + usbNewDeviceAddr = value; + USB_SET_ADDRESS_HOOK(); + SWITCH_CASE(USBRQ_GET_DESCRIPTOR) /* 6 */ + len = usbDriverDescriptor(rq); + goto skipMsgPtrAssignment; + SWITCH_CASE(USBRQ_GET_CONFIGURATION) /* 8 */ + dataPtr = &usbConfiguration; /* send current configuration value */ + len = 1; + SWITCH_CASE(USBRQ_SET_CONFIGURATION) /* 9 */ + usbConfiguration = value; + usbResetStall(); + SWITCH_CASE(USBRQ_GET_INTERFACE) /* 10 */ + len = 1; +#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE + SWITCH_CASE(USBRQ_SET_INTERFACE) /* 11 */ + usbResetDataToggling(); + usbResetStall(); +#endif + SWITCH_DEFAULT /* 7=SET_DESCRIPTOR, 12=SYNC_FRAME */ + /* Should we add an optional hook here? */ + SWITCH_END + usbMsgPtr = dataPtr; +skipMsgPtrAssignment: + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbProcessRx() is called for every message received by the interrupt + * routine. It distinguishes between SETUP and DATA packets and processes + * them accordingly. + */ +static inline void usbProcessRx(uchar *data, uchar len) +{ +usbRequest_t *rq = (void *)data; + +/* usbRxToken can be: + * 0x2d 00101101 (USBPID_SETUP for setup data) + * 0xe1 11100001 (USBPID_OUT: data phase of setup transfer) + * 0...0x0f for OUT on endpoint X + */ + DBG2(0x10 + (usbRxToken & 0xf), data, len + 2); /* SETUP=1d, SETUP-DATA=11, OUTx=1x */ + USB_RX_USER_HOOK(data, len) +#if USB_CFG_IMPLEMENT_FN_WRITEOUT + if(usbRxToken < 0x10){ /* OUT to endpoint != 0: endpoint number in usbRxToken */ + usbFunctionWriteOut(data, len); + return; + } +#endif + if(usbRxToken == (uchar)USBPID_SETUP){ + if(len != 8) /* Setup size must be always 8 bytes. Ignore otherwise. */ + return; + usbMsgLen_t replyLen; + usbTxBuf[0] = USBPID_DATA0; /* initialize data toggling */ + usbTxLen = USBPID_NAK; /* abort pending transmit */ + usbMsgFlags = 0; + uchar type = rq->bmRequestType & USBRQ_TYPE_MASK; + if(type != USBRQ_TYPE_STANDARD){ /* standard requests are handled by driver */ + replyLen = usbFunctionSetup(data); + }else{ + replyLen = usbDriverSetup(rq); + } +#if USB_CFG_IMPLEMENT_FN_READ || USB_CFG_IMPLEMENT_FN_WRITE + if(replyLen == USB_NO_MSG){ /* use user-supplied read/write function */ + /* do some conditioning on replyLen, but on IN transfers only */ + if((rq->bmRequestType & USBRQ_DIR_MASK) != USBRQ_DIR_HOST_TO_DEVICE){ + if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */ + replyLen = rq->wLength.bytes[0]; + }else{ + replyLen = rq->wLength.word; + } + } + usbMsgFlags = USB_FLG_USE_USER_RW; + }else /* The 'else' prevents that we limit a replyLen of USB_NO_MSG to the maximum transfer len. */ +#endif + if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */ + if(!rq->wLength.bytes[1] && replyLen > rq->wLength.bytes[0]) /* limit length to max */ + replyLen = rq->wLength.bytes[0]; + }else{ + if(replyLen > rq->wLength.word) /* limit length to max */ + replyLen = rq->wLength.word; + } + usbMsgLen = replyLen; + }else{ /* usbRxToken must be USBPID_OUT, which means data phase of setup (control-out) */ +#if USB_CFG_IMPLEMENT_FN_WRITE + if(usbMsgFlags & USB_FLG_USE_USER_RW){ + uchar rval = usbFunctionWrite(data, len); + if(rval == 0xff){ /* an error occurred */ + usbTxLen = USBPID_STALL; + }else if(rval != 0){ /* This was the final package */ + usbMsgLen = 0; /* answer with a zero-sized data packet */ + } + } +#endif + } +} + +/* ------------------------------------------------------------------------- */ + +/* This function is similar to usbFunctionRead(), but it's also called for + * data handled automatically by the driver (e.g. descriptor reads). + */ +static uchar usbDeviceRead(uchar *data, uchar len) +{ + if(len > 0){ /* don't bother app with 0 sized reads */ +#if USB_CFG_IMPLEMENT_FN_READ + if(usbMsgFlags & USB_FLG_USE_USER_RW){ + len = usbFunctionRead(data, len); + }else +#endif + { + uchar i = len, *r = usbMsgPtr; + if(usbMsgFlags & USB_FLG_MSGPTR_IS_ROM){ /* ROM data */ + do{ + uchar c = USB_READ_FLASH(r); /* assign to char size variable to enforce byte ops */ + *data++ = c; + r++; + }while(--i); + }else{ /* RAM data */ + do{ + *data++ = *r++; + }while(--i); + } + usbMsgPtr = r; + } + } + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbBuildTxBlock() is called when we have data to transmit and the + * interrupt routine's transmit buffer is empty. + */ +static inline void usbBuildTxBlock(void) +{ +usbMsgLen_t wantLen; +uchar len; + + wantLen = usbMsgLen; + if(wantLen > 8) + wantLen = 8; + usbMsgLen -= wantLen; + usbTxBuf[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* DATA toggling */ + len = usbDeviceRead(usbTxBuf + 1, wantLen); + if(len <= 8){ /* valid data packet */ + usbCrc16Append(&usbTxBuf[1], len); + len += 4; /* length including sync byte */ + if(len < 12) /* a partial package identifies end of message */ + usbMsgLen = USB_NO_MSG; + }else{ + len = USBPID_STALL; /* stall the endpoint */ + usbMsgLen = USB_NO_MSG; + } + usbTxLen = len; + DBG2(0x20, usbTxBuf, len-1); +} + +/* ------------------------------------------------------------------------- */ + +static inline void usbHandleResetHook(uchar notResetState) +{ +#ifdef USB_RESET_HOOK +static uchar wasReset; +uchar isReset = !notResetState; + + if(wasReset != isReset){ + USB_RESET_HOOK(isReset); + wasReset = isReset; + } +#endif +} + +/* ------------------------------------------------------------------------- */ + +USB_PUBLIC void usbPoll(void) +{ +schar len; +uchar i; + + len = usbRxLen - 3; + if(len >= 0){ +/* We could check CRC16 here -- but ACK has already been sent anyway. If you + * need data integrity checks with this driver, check the CRC in your app + * code and report errors back to the host. Since the ACK was already sent, + * retries must be handled on application level. + * unsigned crc = usbCrc16(buffer + 1, usbRxLen - 3); + */ + usbProcessRx(usbRxBuf + USB_BUFSIZE + 1 - usbInputBufOffset, len); +#if USB_CFG_HAVE_FLOWCONTROL + if(usbRxLen > 0) /* only mark as available if not inactivated */ + usbRxLen = 0; +#else + usbRxLen = 0; /* mark rx buffer as available */ +#endif + } + if(usbTxLen & 0x10){ /* transmit system idle */ + if(usbMsgLen != USB_NO_MSG){ /* transmit data pending? */ + usbBuildTxBlock(); + } + } + for(i = 20; i > 0; i--){ + uchar usbLineStatus = USBIN & USBMASK; + if(usbLineStatus != 0) /* SE0 has ended */ + goto isNotReset; + } + /* RESET condition, called multiple times during reset */ + usbNewDeviceAddr = 0; + usbDeviceAddr = 0; + usbResetStall(); + DBG1(0xff, 0, 0); +isNotReset: + usbHandleResetHook(i); +} + +/* ------------------------------------------------------------------------- */ + +USB_PUBLIC void usbInit(void) +{ +#if USB_INTR_CFG_SET != 0 + USB_INTR_CFG |= USB_INTR_CFG_SET; +#endif +#if USB_INTR_CFG_CLR != 0 + USB_INTR_CFG &= ~(USB_INTR_CFG_CLR); +#endif + USB_INTR_ENABLE |= (1 << USB_INTR_ENABLE_BIT); + usbResetDataToggling(); +#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE + usbTxLen1 = USBPID_NAK; +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 + usbTxLen3 = USBPID_NAK; +#endif +#endif +} + +/* ------------------------------------------------------------------------- */ diff --git a/hardware/digistump/avr/libraries/DigiCDC/usbdrv.h b/hardware/digistump/avr/libraries/DigiCDC/usbdrv.h new file mode 100644 index 0000000..660cb1b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/usbdrv.h @@ -0,0 +1,790 @@ +/* Name: usbdrv.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2004-12-29 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbdrv.h 793 2010-07-15 15:58:11Z cs $ + */ + +#ifndef __usbdrv_h_included__ +#define __usbdrv_h_included__ +#include "usbconfig.h" +#include "usbportability.h" + +/* +Hardware Prerequisites: +======================= +USB lines D+ and D- MUST be wired to the same I/O port. We recommend that D+ +triggers the interrupt (best achieved by using INT0 for D+), but it is also +possible to trigger the interrupt from D-. If D- is used, interrupts are also +triggered by SOF packets. D- requires a pull-up of 1.5k to +3.5V (and the +device must be powered at 3.5V) to identify as low-speed USB device. A +pull-down or pull-up of 1M SHOULD be connected from D+ to +3.5V to prevent +interference when no USB master is connected. If you use Zener diodes to limit +the voltage on D+ and D-, you MUST use a pull-down resistor, not a pull-up. +We use D+ as interrupt source and not D- because it does not trigger on +keep-alive and RESET states. If you want to count keep-alive events with +USB_COUNT_SOF, you MUST use D- as an interrupt source. + +As a compile time option, the 1.5k pull-up resistor on D- can be made +switchable to allow the device to disconnect at will. See the definition of +usbDeviceConnect() and usbDeviceDisconnect() further down in this file. + +Please adapt the values in usbconfig.h according to your hardware! + +The device MUST be clocked at exactly 12 MHz, 15 MHz, 16 MHz or 20 MHz +or at 12.8 MHz resp. 16.5 MHz +/- 1%. See usbconfig-prototype.h for details. + + +Limitations: +============ +Robustness with respect to communication errors: +The driver assumes error-free communication. It DOES check for errors in +the PID, but does NOT check bit stuffing errors, SE0 in middle of a byte, +token CRC (5 bit) and data CRC (16 bit). CRC checks can not be performed due +to timing constraints: We must start sending a reply within 7 bit times. +Bit stuffing and misplaced SE0 would have to be checked in real-time, but CPU +performance does not permit that. The driver does not check Data0/Data1 +toggling, but application software can implement the check. + +Input characteristics: +Since no differential receiver circuit is used, electrical interference +robustness may suffer. The driver samples only one of the data lines with +an ordinary I/O pin's input characteristics. However, since this is only a +low speed USB implementation and the specification allows for 8 times the +bit rate over the same hardware, we should be on the safe side. Even the spec +requires detection of asymmetric states at high bit rate for SE0 detection. + +Number of endpoints: +The driver supports the following endpoints: + +- Endpoint 0, the default control endpoint. +- Any number of interrupt- or bulk-out endpoints. The data is sent to + usbFunctionWriteOut() and USB_CFG_IMPLEMENT_FN_WRITEOUT must be defined + to 1 to activate this feature. The endpoint number can be found in the + global variable 'usbRxToken'. +- One default interrupt- or bulk-in endpoint. This endpoint is used for + interrupt- or bulk-in transfers which are not handled by any other endpoint. + You must define USB_CFG_HAVE_INTRIN_ENDPOINT in order to activate this + feature and call usbSetInterrupt() to send interrupt/bulk data. +- One additional interrupt- or bulk-in endpoint. This was endpoint 3 in + previous versions of this driver but can now be configured to any endpoint + number. You must define USB_CFG_HAVE_INTRIN_ENDPOINT3 in order to activate + this feature and call usbSetInterrupt3() to send interrupt/bulk data. The + endpoint number can be set with USB_CFG_EP3_NUMBER. + +Please note that the USB standard forbids bulk endpoints for low speed devices! +Most operating systems allow them anyway, but the AVR will spend 90% of the CPU +time in the USB interrupt polling for bulk data. + +Maximum data payload: +Data payload of control in and out transfers may be up to 254 bytes. In order +to accept payload data of out transfers, you need to implement +'usbFunctionWrite()'. + +USB Suspend Mode supply current: +The USB standard limits power consumption to 500uA when the bus is in suspend +mode. This is not a problem for self-powered devices since they don't need +bus power anyway. Bus-powered devices can achieve this only by putting the +CPU in sleep mode. The driver does not implement suspend handling by itself. +However, the application may implement activity monitoring and wakeup from +sleep. The host sends regular SE0 states on the bus to keep it active. These +SE0 states can be detected by using D- as the interrupt source. Define +USB_COUNT_SOF to 1 and use the global variable usbSofCount to check for bus +activity. + +Operation without an USB master: +The driver behaves neutral without connection to an USB master if D- reads +as 1. To avoid spurious interrupts, we recommend a high impedance (e.g. 1M) +pull-down or pull-up resistor on D+ (interrupt). If Zener diodes are used, +use a pull-down. If D- becomes statically 0, the driver may block in the +interrupt routine. + +Interrupt latency: +The application must ensure that the USB interrupt is not disabled for more +than 25 cycles (this is for 12 MHz, faster clocks allow longer latency). +This implies that all interrupt routines must either have the "ISR_NOBLOCK" +attribute set (see "avr/interrupt.h") or be written in assembler with "sei" +as the first instruction. + +Maximum interrupt duration / CPU cycle consumption: +The driver handles all USB communication during the interrupt service +routine. The routine will not return before an entire USB message is received +and the reply is sent. This may be up to ca. 1200 cycles @ 12 MHz (= 100us) if +the host conforms to the standard. The driver will consume CPU cycles for all +USB messages, even if they address another (low-speed) device on the same bus. + +*/ + +/* ------------------------------------------------------------------------- */ +/* --------------------------- Module Interface ---------------------------- */ +/* ------------------------------------------------------------------------- */ + +#define USBDRV_VERSION 20100715 +/* This define uniquely identifies a driver version. It is a decimal number + * constructed from the driver's release date in the form YYYYMMDD. If the + * driver's behavior or interface changes, you can use this constant to + * distinguish versions. If it is not defined, the driver's release date is + * older than 2006-01-25. + */ + + +#ifndef USB_PUBLIC +#define USB_PUBLIC +#endif +/* USB_PUBLIC is used as declaration attribute for all functions exported by + * the USB driver. The default is no attribute (see above). You may define it + * to static either in usbconfig.h or from the command line if you include + * usbdrv.c instead of linking against it. Including the C module of the driver + * directly in your code saves a couple of bytes in flash memory. + */ + +#ifndef __ASSEMBLER__ +#ifndef uchar +#define uchar unsigned char +#endif +#ifndef schar +#define schar signed char +#endif +/* shortcuts for well defined 8 bit integer types */ + +#if USB_CFG_LONG_TRANSFERS /* if more than 254 bytes transfer size required */ +# define usbMsgLen_t unsigned +#else +# define usbMsgLen_t uchar +#endif +/* usbMsgLen_t is the data type used for transfer lengths. By default, it is + * defined to uchar, allowing a maximum of 254 bytes (255 is reserved for + * USB_NO_MSG below). If the usbconfig.h defines USB_CFG_LONG_TRANSFERS to 1, + * a 16 bit data type is used, allowing up to 16384 bytes (the rest is used + * for flags in the descriptor configuration). + */ +#define USB_NO_MSG ((usbMsgLen_t)-1) /* constant meaning "no message" */ + +struct usbRequest; /* forward declaration */ + +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbInit(void); +/* This function must be called before interrupts are enabled and the main + * loop is entered. We exepct that the PORT and DDR bits for D+ and D- have + * not been changed from their default status (which is 0). If you have changed + * them, set both back to 0 (configure them as input with no internal pull-up). + */ +USB_PUBLIC void usbPoll(void); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function must be called at regular intervals from the main loop. + * Maximum delay between calls is somewhat less than 50ms (USB timeout for + * accepting a Setup message). Otherwise the device will not be recognized. + * Please note that debug outputs through the UART take ~ 0.5ms per byte + * at 19200 bps. + */ +extern uchar *usbMsgPtr; +/* This variable may be used to pass transmit data to the driver from the + * implementation of usbFunctionWrite(). It is also used internally by the + * driver for standard control requests. + */ + #ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC usbMsgLen_t usbFunctionSetup(uchar data[8]); +/* This function is called when the driver receives a SETUP transaction from + * the host which is not answered by the driver itself (in practice: class and + * vendor requests). All control transfers start with a SETUP transaction where + * the host communicates the parameters of the following (optional) data + * transfer. The SETUP data is available in the 'data' parameter which can + * (and should) be casted to 'usbRequest_t *' for a more user-friendly access + * to parameters. + * + * If the SETUP indicates a control-in transfer, you should provide the + * requested data to the driver. There are two ways to transfer this data: + * (1) Set the global pointer 'usbMsgPtr' to the base of the static RAM data + * block and return the length of the data in 'usbFunctionSetup()'. The driver + * will handle the rest. Or (2) return USB_NO_MSG in 'usbFunctionSetup()'. The + * driver will then call 'usbFunctionRead()' when data is needed. See the + * documentation for usbFunctionRead() for details. + * + * If the SETUP indicates a control-out transfer, the only way to receive the + * data from the host is through the 'usbFunctionWrite()' call. If you + * implement this function, you must return USB_NO_MSG in 'usbFunctionSetup()' + * to indicate that 'usbFunctionWrite()' should be used. See the documentation + * of this function for more information. If you just want to ignore the data + * sent by the host, return 0 in 'usbFunctionSetup()'. + * + * Note that calls to the functions usbFunctionRead() and usbFunctionWrite() + * are only done if enabled by the configuration in usbconfig.h. + */ +USB_PUBLIC usbMsgLen_t usbFunctionDescriptor(struct usbRequest *rq); + +#ifdef __cplusplus +} // extern "C" +#endif +/* You need to implement this function ONLY if you provide USB descriptors at + * runtime (which is an expert feature). It is very similar to + * usbFunctionSetup() above, but it is called only to request USB descriptor + * data. See the documentation of usbFunctionSetup() above for more info. + */ +#if USB_CFG_HAVE_INTRIN_ENDPOINT + #ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function sets the message which will be sent during the next interrupt + * IN transfer. The message is copied to an internal buffer and must not exceed + * a length of 8 bytes. The message may be 0 bytes long just to indicate the + * interrupt status to the host. + * If you need to transfer more bytes, use a control read after the interrupt. + */ +#define usbInterruptIsReady() (usbTxLen1 & 0x10) +/* This macro indicates whether the last interrupt message has already been + * sent. If you set a new interrupt message before the old was sent, the + * message already buffered will be lost. + */ +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 + #ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +#define usbInterruptIsReady3() (usbTxLen3 & 0x10) +/* Same as above for endpoint 3 */ +#endif +#endif /* USB_CFG_HAVE_INTRIN_ENDPOINT */ +#if USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH /* simplified interface for backward compatibility */ +#define usbHidReportDescriptor usbDescriptorHidReport +/* should be declared as: const PROGMEM char usbHidReportDescriptor[]; */ +/* If you implement an HID device, you need to provide a report descriptor. + * The HID report descriptor syntax is a bit complex. If you understand how + * report descriptors are constructed, we recommend that you use the HID + * Descriptor Tool from usb.org, see http://www.usb.org/developers/hidpage/. + * Otherwise you should probably start with a working example. + */ +#endif /* USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH */ +#if USB_CFG_IMPLEMENT_FN_WRITE + #ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC uchar usbFunctionWrite(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function is called by the driver to provide a control transfer's + * payload data (control-out). It is called in chunks of up to 8 bytes. The + * total count provided in the current control transfer can be obtained from + * the 'length' property in the setup data. If an error occurred during + * processing, return 0xff (== -1). The driver will answer the entire transfer + * with a STALL token in this case. If you have received the entire payload + * successfully, return 1. If you expect more data, return 0. If you don't + * know whether the host will send more data (you should know, the total is + * provided in the usbFunctionSetup() call!), return 1. + * NOTE: If you return 0xff for STALL, 'usbFunctionWrite()' may still be called + * for the remaining data. You must continue to return 0xff for STALL in these + * calls. + * In order to get usbFunctionWrite() called, define USB_CFG_IMPLEMENT_FN_WRITE + * to 1 in usbconfig.h and return 0xff in usbFunctionSetup().. + */ +#endif /* USB_CFG_IMPLEMENT_FN_WRITE */ +#if USB_CFG_IMPLEMENT_FN_READ + #ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC uchar usbFunctionRead(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function is called by the driver to ask the application for a control + * transfer's payload data (control-in). It is called in chunks of up to 8 + * bytes each. You should copy the data to the location given by 'data' and + * return the actual number of bytes copied. If you return less than requested, + * the control-in transfer is terminated. If you return 0xff, the driver aborts + * the transfer with a STALL token. + * In order to get usbFunctionRead() called, define USB_CFG_IMPLEMENT_FN_READ + * to 1 in usbconfig.h and return 0xff in usbFunctionSetup().. + */ +#endif /* USB_CFG_IMPLEMENT_FN_READ */ + +extern uchar usbRxToken; /* may be used in usbFunctionWriteOut() below */ +#if USB_CFG_IMPLEMENT_FN_WRITEOUT + #ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbFunctionWriteOut(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function is called by the driver when data is received on an interrupt- + * or bulk-out endpoint. The endpoint number can be found in the global + * variable usbRxToken. You must define USB_CFG_IMPLEMENT_FN_WRITEOUT to 1 in + * usbconfig.h to get this function called. + */ +#endif /* USB_CFG_IMPLEMENT_FN_WRITEOUT */ +#ifdef USB_CFG_PULLUP_IOPORTNAME +#define usbDeviceConnect() ((USB_PULLUP_DDR |= (1<device, 1=device->host + * t ..... type: 0=standard, 1=class, 2=vendor, 3=reserved + * r ..... recipient: 0=device, 1=interface, 2=endpoint, 3=other + */ + +/* USB setup recipient values */ +#define USBRQ_RCPT_MASK 0x1f +#define USBRQ_RCPT_DEVICE 0 +#define USBRQ_RCPT_INTERFACE 1 +#define USBRQ_RCPT_ENDPOINT 2 + +/* USB request type values */ +#define USBRQ_TYPE_MASK 0x60 +#define USBRQ_TYPE_STANDARD (0<<5) +#define USBRQ_TYPE_CLASS (1<<5) +#define USBRQ_TYPE_VENDOR (2<<5) + +/* USB direction values: */ +#define USBRQ_DIR_MASK 0x80 +#define USBRQ_DIR_HOST_TO_DEVICE (0<<7) +#define USBRQ_DIR_DEVICE_TO_HOST (1<<7) + +/* USB Standard Requests */ +#define USBRQ_GET_STATUS 0 +#define USBRQ_CLEAR_FEATURE 1 +#define USBRQ_SET_FEATURE 3 +#define USBRQ_SET_ADDRESS 5 +#define USBRQ_GET_DESCRIPTOR 6 +#define USBRQ_SET_DESCRIPTOR 7 +#define USBRQ_GET_CONFIGURATION 8 +#define USBRQ_SET_CONFIGURATION 9 +#define USBRQ_GET_INTERFACE 10 +#define USBRQ_SET_INTERFACE 11 +#define USBRQ_SYNCH_FRAME 12 + +/* USB descriptor constants */ +#define USBDESCR_DEVICE 1 +#define USBDESCR_CONFIG 2 +#define USBDESCR_STRING 3 +#define USBDESCR_INTERFACE 4 +#define USBDESCR_ENDPOINT 5 +#define USBDESCR_HID 0x21 +#define USBDESCR_HID_REPORT 0x22 +#define USBDESCR_HID_PHYS 0x23 + +//#define USBATTR_BUSPOWER 0x80 // USB 1.1 does not define this value any more +#define USBATTR_SELFPOWER 0x40 +#define USBATTR_REMOTEWAKE 0x20 + +/* USB HID Requests */ +#define USBRQ_HID_GET_REPORT 0x01 +#define USBRQ_HID_GET_IDLE 0x02 +#define USBRQ_HID_GET_PROTOCOL 0x03 +#define USBRQ_HID_SET_REPORT 0x09 +#define USBRQ_HID_SET_IDLE 0x0a +#define USBRQ_HID_SET_PROTOCOL 0x0b + +/* ------------------------------------------------------------------------- */ + +#endif /* __usbdrv_h_included__ */ diff --git a/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm.S b/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm.S new file mode 100644 index 0000000..45fcf18 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm.S @@ -0,0 +1,393 @@ +/* Name: usbdrvasm.S + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2007-06-13 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm.S 785 2010-05-30 17:57:07Z cs $ + */ + +/* +General Description: +This module is the assembler part of the USB driver. This file contains +general code (preprocessor acrobatics and CRC computation) and then includes +the file appropriate for the given clock rate. +*/ + +#define __SFR_OFFSET 0 /* used by avr-libc's register definitions */ +#include "usbportability.h" +#include "usbdrv.h" /* for common defs */ + +/* register names */ +#define x1 r16 +#define x2 r17 +#define shift r18 +#define cnt r19 +#define x3 r20 +#define x4 r21 +#define x5 r22 +#define bitcnt x5 +#define phase x4 +#define leap x4 + +/* Some assembler dependent definitions and declarations: */ + +#ifdef __IAR_SYSTEMS_ASM__ + extern usbRxBuf, usbDeviceAddr, usbNewDeviceAddr, usbInputBufOffset + extern usbCurrentTok, usbRxLen, usbRxToken, usbTxLen + extern usbTxBuf, usbTxStatus1, usbTxStatus3 +# if USB_COUNT_SOF + extern usbSofCount +# endif + public usbCrc16 + public usbCrc16Append + + COMMON INTVEC +# ifndef USB_INTR_VECTOR + ORG INT0_vect +# else /* USB_INTR_VECTOR */ + ORG USB_INTR_VECTOR +# undef USB_INTR_VECTOR +# endif /* USB_INTR_VECTOR */ +# define USB_INTR_VECTOR usbInterruptHandler + rjmp USB_INTR_VECTOR + RSEG CODE + +#else /* __IAR_SYSTEMS_ASM__ */ + +# ifndef USB_INTR_VECTOR /* default to hardware interrupt INT0 */ +# ifdef INT0_vect +# define USB_INTR_VECTOR INT0_vect // this is the "new" define for the vector +# else +# define USB_INTR_VECTOR SIG_INTERRUPT0 // this is the "old" vector +# endif +# endif + .text + .global USB_INTR_VECTOR + .type USB_INTR_VECTOR, @function + .global usbCrc16 + .global usbCrc16Append +#endif /* __IAR_SYSTEMS_ASM__ */ + + +#if USB_INTR_PENDING < 0x40 /* This is an I/O address, use in and out */ +# define USB_LOAD_PENDING(reg) in reg, USB_INTR_PENDING +# define USB_STORE_PENDING(reg) out USB_INTR_PENDING, reg +#else /* It's a memory address, use lds and sts */ +# define USB_LOAD_PENDING(reg) lds reg, USB_INTR_PENDING +# define USB_STORE_PENDING(reg) sts USB_INTR_PENDING, reg +#endif + +#define usbTxLen1 usbTxStatus1 +#define usbTxBuf1 (usbTxStatus1 + 1) +#define usbTxLen3 usbTxStatus3 +#define usbTxBuf3 (usbTxStatus3 + 1) + + +;---------------------------------------------------------------------------- +; Utility functions +;---------------------------------------------------------------------------- + +#ifdef __IAR_SYSTEMS_ASM__ +/* Register assignments for usbCrc16 on IAR cc */ +/* Calling conventions on IAR: + * First parameter passed in r16/r17, second in r18/r19 and so on. + * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer) + * Result is passed in r16/r17 + * In case of the "tiny" memory model, pointers are only 8 bit with no + * padding. We therefore pass argument 1 as "16 bit unsigned". + */ +RTMODEL "__rt_version", "3" +/* The line above will generate an error if cc calling conventions change. + * The value "3" above is valid for IAR 4.10B/W32 + */ +# define argLen r18 /* argument 2 */ +# define argPtrL r16 /* argument 1 */ +# define argPtrH r17 /* argument 1 */ + +# define resCrcL r16 /* result */ +# define resCrcH r17 /* result */ + +# define ptrL ZL +# define ptrH ZH +# define ptr Z +# define byte r22 +# define bitCnt r19 +# define polyL r20 +# define polyH r21 +# define scratch r23 + +#else /* __IAR_SYSTEMS_ASM__ */ +/* Register assignments for usbCrc16 on gcc */ +/* Calling conventions on gcc: + * First parameter passed in r24/r25, second in r22/23 and so on. + * Callee must preserve r1-r17, r28/r29 + * Result is passed in r24/r25 + */ +# define argLen r22 /* argument 2 */ +# define argPtrL r24 /* argument 1 */ +# define argPtrH r25 /* argument 1 */ + +# define resCrcL r24 /* result */ +# define resCrcH r25 /* result */ + +# define ptrL XL +# define ptrH XH +# define ptr x +# define byte r18 +# define bitCnt r19 +# define polyL r20 +# define polyH r21 +# define scratch r23 + +#endif + +#if USB_USE_FAST_CRC + +; This implementation is faster, but has bigger code size +; Thanks to Slawomir Fras (BoskiDialer) for this code! +; It implements the following C pseudo-code: +; unsigned table(unsigned char x) +; { +; unsigned value; +; +; value = (unsigned)x << 6; +; value ^= (unsigned)x << 7; +; if(parity(x)) +; value ^= 0xc001; +; return value; +; } +; unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen) +; { +; unsigned crc = 0xffff; +; +; while(argLen--) +; crc = table(lo8(crc) ^ *argPtr++) ^ hi8(crc); +; return ~crc; +; } + +; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen); +; argPtr r24+25 / r16+r17 +; argLen r22 / r18 +; temp variables: +; byte r18 / r22 +; scratch r23 +; resCrc r24+r25 / r16+r17 +; ptr X / Z +usbCrc16: + mov ptrL, argPtrL + mov ptrH, argPtrH + ldi resCrcL, 0xFF + ldi resCrcH, 0xFF + rjmp usbCrc16LoopTest +usbCrc16ByteLoop: + ld byte, ptr+ + eor resCrcL, byte ; resCrcL is now 'x' in table() + mov byte, resCrcL ; compute parity of 'x' + swap byte + eor byte, resCrcL + mov scratch, byte + lsr byte + lsr byte + eor byte, scratch + inc byte + lsr byte + andi byte, 1 ; byte is now parity(x) + mov scratch, resCrcL + mov resCrcL, resCrcH + eor resCrcL, byte ; low byte of if(parity(x)) value ^= 0xc001; + neg byte + andi byte, 0xc0 + mov resCrcH, byte ; high byte of if(parity(x)) value ^= 0xc001; + clr byte + lsr scratch + ror byte + eor resCrcH, scratch + eor resCrcL, byte + lsr scratch + ror byte + eor resCrcH, scratch + eor resCrcL, byte +usbCrc16LoopTest: + subi argLen, 1 + brsh usbCrc16ByteLoop + com resCrcL + com resCrcH + ret + +#else /* USB_USE_FAST_CRC */ + +; This implementation is slower, but has less code size +; +; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen); +; argPtr r24+25 / r16+r17 +; argLen r22 / r18 +; temp variables: +; byte r18 / r22 +; bitCnt r19 +; poly r20+r21 +; scratch r23 +; resCrc r24+r25 / r16+r17 +; ptr X / Z +usbCrc16: + mov ptrL, argPtrL + mov ptrH, argPtrH + ldi resCrcL, 0 + ldi resCrcH, 0 + ldi polyL, lo8(0xa001) + ldi polyH, hi8(0xa001) + com argLen ; argLen = -argLen - 1: modified loop to ensure that carry is set + ldi bitCnt, 0 ; loop counter with starnd condition = end condition + rjmp usbCrcLoopEntry +usbCrcByteLoop: + ld byte, ptr+ + eor resCrcL, byte +usbCrcBitLoop: + ror resCrcH ; carry is always set here (see brcs jumps to here) + ror resCrcL + brcs usbCrcNoXor + eor resCrcL, polyL + eor resCrcH, polyH +usbCrcNoXor: + subi bitCnt, 224 ; (8 * 224) % 256 = 0; this loop iterates 8 times + brcs usbCrcBitLoop +usbCrcLoopEntry: + subi argLen, -1 + brcs usbCrcByteLoop +usbCrcReady: + ret +; Thanks to Reimar Doeffinger for optimizing this CRC routine! + +#endif /* USB_USE_FAST_CRC */ + +; extern unsigned usbCrc16Append(unsigned char *data, unsigned char len); +usbCrc16Append: + rcall usbCrc16 + st ptr+, resCrcL + st ptr+, resCrcH + ret + +#undef argLen +#undef argPtrL +#undef argPtrH +#undef resCrcL +#undef resCrcH +#undef ptrL +#undef ptrH +#undef ptr +#undef byte +#undef bitCnt +#undef polyL +#undef polyH +#undef scratch + + +#if USB_CFG_HAVE_MEASURE_FRAME_LENGTH +#ifdef __IAR_SYSTEMS_ASM__ +/* Register assignments for usbMeasureFrameLength on IAR cc */ +/* Calling conventions on IAR: + * First parameter passed in r16/r17, second in r18/r19 and so on. + * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer) + * Result is passed in r16/r17 + * In case of the "tiny" memory model, pointers are only 8 bit with no + * padding. We therefore pass argument 1 as "16 bit unsigned". + */ +# define resL r16 +# define resH r17 +# define cnt16L r30 +# define cnt16H r31 +# define cntH r18 + +#else /* __IAR_SYSTEMS_ASM__ */ +/* Register assignments for usbMeasureFrameLength on gcc */ +/* Calling conventions on gcc: + * First parameter passed in r24/r25, second in r22/23 and so on. + * Callee must preserve r1-r17, r28/r29 + * Result is passed in r24/r25 + */ +# define resL r24 +# define resH r25 +# define cnt16L r24 +# define cnt16H r25 +# define cntH r26 +#endif +# define cnt16 cnt16L + +; extern unsigned usbMeasurePacketLength(void); +; returns time between two idle strobes in multiples of 7 CPU clocks +.global usbMeasureFrameLength +usbMeasureFrameLength: + ldi cntH, 6 ; wait ~ 10 ms for D- == 0 + clr cnt16L + clr cnt16H +usbMFTime16: + dec cntH + breq usbMFTimeout +usbMFWaitStrobe: ; first wait for D- == 0 (idle strobe) + sbiw cnt16, 1 ;[0] [6] + breq usbMFTime16 ;[2] + sbic USBIN, USBMINUS ;[3] + rjmp usbMFWaitStrobe ;[4] +usbMFWaitIdle: ; then wait until idle again + sbis USBIN, USBMINUS ;1 wait for D- == 1 + rjmp usbMFWaitIdle ;2 + ldi cnt16L, 1 ;1 represents cycles so far + clr cnt16H ;1 +usbMFWaitLoop: + in cntH, USBIN ;[0] [7] + adiw cnt16, 1 ;[1] + breq usbMFTimeout ;[3] + andi cntH, USBMASK ;[4] + brne usbMFWaitLoop ;[5] +usbMFTimeout: +#if resL != cnt16L + mov resL, cnt16L + mov resH, cnt16H +#endif + ret + +#undef resL +#undef resH +#undef cnt16 +#undef cnt16L +#undef cnt16H +#undef cntH + +#endif /* USB_CFG_HAVE_MEASURE_FRAME_LENGTH */ + +;---------------------------------------------------------------------------- +; Now include the clock rate specific code +;---------------------------------------------------------------------------- + +#ifndef USB_CFG_CLOCK_KHZ +# ifdef F_CPU +# define USB_CFG_CLOCK_KHZ (F_CPU/1000) +# else +# error "USB_CFG_CLOCK_KHZ not defined in usbconfig.h and no F_CPU set!" +# endif +#endif + +#if USB_CFG_CHECK_CRC /* separate dispatcher for CRC type modules */ +# if USB_CFG_CLOCK_KHZ == 18000 +# include "usbdrvasm18-crc.inc" +# else +# error "USB_CFG_CLOCK_KHZ is not one of the supported crc-rates!" +# endif +#else /* USB_CFG_CHECK_CRC */ +# if USB_CFG_CLOCK_KHZ == 12000 +# include "usbdrvasm12.inc" +# elif USB_CFG_CLOCK_KHZ == 12800 +# include "usbdrvasm128.inc" +# elif USB_CFG_CLOCK_KHZ == 15000 +# include "usbdrvasm15.inc" +# elif USB_CFG_CLOCK_KHZ == 16000 +# include "usbdrvasm16.inc" +# elif USB_CFG_CLOCK_KHZ == 16500 +# include "usbdrvasm165.inc" +# elif USB_CFG_CLOCK_KHZ == 20000 +# include "usbdrvasm20.inc" +# else +# error "USB_CFG_CLOCK_KHZ is not one of the supported non-crc-rates!" +# endif +#endif /* USB_CFG_CHECK_CRC */ diff --git a/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm.asm b/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm.asm new file mode 100644 index 0000000..9cc4e4d --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm.asm @@ -0,0 +1,21 @@ +/* Name: usbdrvasm.asm + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2006-03-01 + * Tabsize: 4 + * Copyright: (c) 2006 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id$ + */ + +/* +General Description: +The IAR compiler/assembler system prefers assembler files with file extension +".asm". We simply provide this file as an alias for usbdrvasm.S. + +Thanks to Oleg Semyonov for his help with the IAR tools port! +*/ + +#include "usbdrvasm.S" + +end diff --git a/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm12.inc b/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm12.inc new file mode 100644 index 0000000..c116758 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm12.inc @@ -0,0 +1,393 @@ +/* Name: usbdrvasm12.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2004-12-29 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbdrvasm12.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 12 MHz version of the asssembler part of the USB driver. It +requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! + + +Timing constraints according to spec (in bit times): +timing subject min max CPUcycles +--------------------------------------------------------------------------- +EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128 +EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60 +DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60 +*/ + +;Software-receiver engine. Strict timing! Don't change unless you can preserve timing! +;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled +;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable +;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes +;Numbers in brackets are maximum cycles since SOF. +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt + push YL ;2 [35] push only what is necessary to sync with edge ASAP + in YL, SREG ;1 [37] + push YL ;2 [39] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of 1/4 bit which meets the spec. + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push YH ;2 [2] + lds YL, usbInputBufOffset;2 [4] + clr YH ;1 [5] + subi YL, lo8(-(usbRxBuf));1 [6] + sbci YH, hi8(-(usbRxBuf));1 [7] + + sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early] + rjmp haveTwoBitsK ;2 [10] + pop YH ;2 [11] undo the push from before + rjmp waitForK ;2 [13] this was not the end of sync, retry +haveTwoBitsK: +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- + push shift ;2 [16] + push x1 ;2 [12] + push x2 ;2 [14] + + in x1, USBIN ;1 [17] <-- sample bit 0 + ldi shift, 0xff ;1 [18] + bst x1, USBMINUS ;1 [19] + bld shift, 0 ;1 [20] + push x3 ;2 [22] + push cnt ;2 [24] + + in x2, USBIN ;1 [25] <-- sample bit 1 + ser x3 ;1 [26] [inserted init instruction] + eor x1, x2 ;1 [27] + bst x1, USBMINUS ;1 [28] + bld shift, 1 ;1 [29] + ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction] + rjmp rxbit2 ;2 [32] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- + +unstuff0: ;1 (branch taken) + andi x3, ~0x01 ;1 [15] + mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit + in x2, USBIN ;1 [17] <-- sample bit 1 again + ori shift, 0x01 ;1 [18] + rjmp didUnstuff0 ;2 [20] + +unstuff1: ;1 (branch taken) + mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit + andi x3, ~0x02 ;1 [22] + ori shift, 0x02 ;1 [23] + nop ;1 [24] + in x1, USBIN ;1 [25] <-- sample bit 2 again + rjmp didUnstuff1 ;2 [27] + +unstuff2: ;1 (branch taken) + andi x3, ~0x04 ;1 [29] + ori shift, 0x04 ;1 [30] + mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit + nop ;1 [32] + in x2, USBIN ;1 [33] <-- sample bit 3 + rjmp didUnstuff2 ;2 [35] + +unstuff3: ;1 (branch taken) + in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late] + andi x3, ~0x08 ;1 [35] + ori shift, 0x08 ;1 [36] + rjmp didUnstuff3 ;2 [38] + +unstuff4: ;1 (branch taken) + andi x3, ~0x10 ;1 [40] + in x1, USBIN ;1 [41] <-- sample stuffed bit 4 + ori shift, 0x10 ;1 [42] + rjmp didUnstuff4 ;2 [44] + +unstuff5: ;1 (branch taken) + andi x3, ~0x20 ;1 [48] + in x2, USBIN ;1 [49] <-- sample stuffed bit 5 + ori shift, 0x20 ;1 [50] + rjmp didUnstuff5 ;2 [52] + +unstuff6: ;1 (branch taken) + andi x3, ~0x40 ;1 [56] + in x1, USBIN ;1 [57] <-- sample stuffed bit 6 + ori shift, 0x40 ;1 [58] + rjmp didUnstuff6 ;2 [60] + +; extra jobs done during bit interval: +; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs] +; bit 1: se0 check +; bit 2: overflow check +; bit 3: recovery from delay [bit 0 tasks took too long] +; bit 4: none +; bit 5: none +; bit 6: none +; bit 7: jump, eor +rxLoop: + eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others + in x1, USBIN ;1 [1] <-- sample bit 0 + st y+, x3 ;2 [3] store data + ser x3 ;1 [4] + nop ;1 [5] + eor x2, x1 ;1 [6] + bst x2, USBMINUS;1 [7] + bld shift, 0 ;1 [8] + in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed) + andi x2, USBMASK ;1 [10] + breq se0 ;1 [11] SE0 check for bit 1 + andi shift, 0xf9 ;1 [12] +didUnstuff0: + breq unstuff0 ;1 [13] + eor x1, x2 ;1 [14] + bst x1, USBMINUS;1 [15] + bld shift, 1 ;1 [16] +rxbit2: + in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed) + andi shift, 0xf3 ;1 [18] + breq unstuff1 ;1 [19] do remaining work for bit 1 +didUnstuff1: + subi cnt, 1 ;1 [20] + brcs overflow ;1 [21] loop control + eor x2, x1 ;1 [22] + bst x2, USBMINUS;1 [23] + bld shift, 2 ;1 [24] + in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed) + andi shift, 0xe7 ;1 [26] + breq unstuff2 ;1 [27] +didUnstuff2: + eor x1, x2 ;1 [28] + bst x1, USBMINUS;1 [29] + bld shift, 3 ;1 [30] +didUnstuff3: + andi shift, 0xcf ;1 [31] + breq unstuff3 ;1 [32] + in x1, USBIN ;1 [33] <-- sample bit 4 + eor x2, x1 ;1 [34] + bst x2, USBMINUS;1 [35] + bld shift, 4 ;1 [36] +didUnstuff4: + andi shift, 0x9f ;1 [37] + breq unstuff4 ;1 [38] + nop2 ;2 [40] + in x2, USBIN ;1 [41] <-- sample bit 5 + eor x1, x2 ;1 [42] + bst x1, USBMINUS;1 [43] + bld shift, 5 ;1 [44] +didUnstuff5: + andi shift, 0x3f ;1 [45] + breq unstuff5 ;1 [46] + nop2 ;2 [48] + in x1, USBIN ;1 [49] <-- sample bit 6 + eor x2, x1 ;1 [50] + bst x2, USBMINUS;1 [51] + bld shift, 6 ;1 [52] +didUnstuff6: + cpi shift, 0x02 ;1 [53] + brlo unstuff6 ;1 [54] + nop2 ;2 [56] + in x2, USBIN ;1 [57] <-- sample bit 7 + eor x1, x2 ;1 [58] + bst x1, USBMINUS;1 [59] + bld shift, 7 ;1 [60] +didUnstuff7: + cpi shift, 0x04 ;1 [61] + brsh rxLoop ;2 [63] loop control +unstuff7: + andi x3, ~0x80 ;1 [63] + ori shift, 0x80 ;1 [64] + in x2, USBIN ;1 [65] <-- sample stuffed bit 7 + nop ;1 [66] + rjmp didUnstuff7 ;2 [68] + +macro POP_STANDARD ; 12 cycles + pop cnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;---------------------------------------------------------------------------- +; Transmitting data +;---------------------------------------------------------------------------- + +txByteLoop: +txBitloop: +stuffN1Delay: ; [03] + ror shift ;[-5] [11] [59] + brcc doExorN1 ;[-4] [60] + subi x4, 1 ;[-3] + brne commonN1 ;[-2] + lsl shift ;[-1] compensate ror after rjmp stuffDelay + nop ;[00] stuffing consists of just waiting 8 cycles + rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear + +sendNakAndReti: ;0 [-19] 19 cycles until SOP + ldi x3, USBPID_NAK ;1 [-18] + rjmp usbSendX3 ;2 [-16] +sendAckAndReti: ;0 [-19] 19 cycles until SOP + ldi x3, USBPID_ACK ;1 [-18] + rjmp usbSendX3 ;2 [-16] +sendCntAndReti: ;0 [-17] 17 cycles until SOP + mov x3, cnt ;1 [-16] +usbSendX3: ;0 [-16] + ldi YL, 20 ;1 [-15] 'x3' is R20 + ldi YH, 0 ;1 [-14] + ldi cnt, 2 ;1 [-13] +; rjmp usbSendAndReti fallthrough + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) or USBOUT = 0x01 +; K = (D+ = 1), (D- = 0) or USBOUT = 0x02 +; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles) + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte +;uses: x1...x2, x4, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x4 = bitstuff cnt] +;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction) +usbSendAndReti: + in x2, USBDDR ;[-12] 12 cycles until SOP + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS ;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + out USBDDR, x2 ;[-8] <--- acquire bus + in x1, USBOUT ;[-7] port mirror for tx loop + ldi shift, 0x40 ;[-6] sync byte is first byte sent (we enter loop after ror) + ldi x2, USBMASK ;[-5] + push x4 ;[-4] +doExorN1: + eor x1, x2 ;[-2] [06] [62] + ldi x4, 6 ;[-1] [07] [63] +commonN1: +stuffN2Delay: + out USBOUT, x1 ;[00] [08] [64] <--- set bit + ror shift ;[01] + brcc doExorN2 ;[02] + subi x4, 1 ;[03] + brne commonN2 ;[04] + lsl shift ;[05] compensate ror after rjmp stuffDelay + rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear +doExorN2: + eor x1, x2 ;[04] [12] + ldi x4, 6 ;[05] [13] +commonN2: + nop ;[06] [14] + subi cnt, 171 ;[07] [15] trick: (3 * 171) & 0xff = 1 + out USBOUT, x1 ;[08] [16] <--- set bit + brcs txBitloop ;[09] [25] [41] + +stuff6Delay: + ror shift ;[42] [50] + brcc doExor6 ;[43] + subi x4, 1 ;[44] + brne common6 ;[45] + lsl shift ;[46] compensate ror after rjmp stuffDelay + nop ;[47] stuffing consists of just waiting 8 cycles + rjmp stuff6Delay ;[48] after ror, C bit is reliably clear +doExor6: + eor x1, x2 ;[45] [53] + ldi x4, 6 ;[46] +common6: +stuff7Delay: + ror shift ;[47] [55] + out USBOUT, x1 ;[48] <--- set bit + brcc doExor7 ;[49] + subi x4, 1 ;[50] + brne common7 ;[51] + lsl shift ;[52] compensate ror after rjmp stuffDelay + rjmp stuff7Delay ;[53] after ror, C bit is reliably clear +doExor7: + eor x1, x2 ;[51] [59] + ldi x4, 6 ;[52] +common7: + ld shift, y+ ;[53] + tst cnt ;[55] + out USBOUT, x1 ;[56] <--- set bit + brne txByteLoop ;[57] + +;make SE0: + cbr x1, USBMASK ;[58] prepare SE0 [spec says EOP may be 15 to 18 cycles] + lds x2, usbNewDeviceAddr;[59] + lsl x2 ;[61] we compare with left shifted address + subi YL, 2 + 20 ;[62] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[63] + out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[01] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 12.5625 MHz +max frequency: 69.286 cycles for 8 bit -> 12.99 MHz +nominal frequency: 12.77 MHz ( = sqrt(min * max)) + +sampling positions: (next even number in range [+/- 0.5]) +cycle index range: 0 ... 66 +bits: +.5, 8.875, 17.25, 25.625, 34, 42.375, 50.75, 59.125 +[0/1], [9], [17], [25/+26], [34], [+42/43], [51], [59] + +bit number: 0 1 2 3 4 5 6 7 +spare cycles 1 2 1 2 1 1 1 0 + +operations to perform: duration cycle + ---------------- + eor fix, shift 1 -> 00 + andi phase, USBMASK 1 -> 08 + breq se0 1 -> 16 (moved to 11) + st y+, data 2 -> 24, 25 + mov data, fix 1 -> 33 + ser data 1 -> 41 + subi cnt, 1 1 -> 49 + brcs overflow 1 -> 50 + +layout of samples and operations: +[##] = sample bit +<##> = sample phase +*##* = operation + +0: *00* [01] 02 03 04 <05> 06 07 +1: *08* [09] 10 11 12 <13> 14 15 *16* +2: [17] 18 19 20 <21> 22 23 +3: *24* *25* [26] 27 28 29 <30> 31 32 +4: *33* [34] 35 36 37 <38> 39 40 +5: *41* [42] 43 44 45 <46> 47 48 +6: *49* *50* [51] 52 53 54 <55> 56 57 58 +7: [59] 60 61 62 <63> 64 65 66 +*****************************************************************************/ + +/* we prefer positive expressions (do if condition) instead of negative + * (skip if condition), therefore use defines for skip instructions: + */ +#define ifioclr sbis +#define ifioset sbic +#define ifrclr sbrs +#define ifrset sbrc + +/* The registers "fix" and "data" swap their meaning during the loop. Use + * defines to keep their name constant. + */ +#define fix x2 +#define data x1 +#undef phase /* phase has a default definition to x4 */ +#define phase x3 + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt, r0 + push YL ;2 push only what is necessary to sync with edge ASAP + in YL, SREG ;1 + push YL ;2 +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of 1/4 bit which meets the spec. + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS ;[0] + rjmp foundK ;[1] +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError + +foundK: +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push YH ;[2] + lds YL, usbInputBufOffset;[4] + clr YH ;[6] + subi YL, lo8(-(usbRxBuf));[7] + sbci YH, hi8(-(usbRxBuf));[8] + + sbis USBIN, USBMINUS ;[9] we want two bits K [we want to sample at 8 + 4 - 1.5 = 10.5] + rjmp haveTwoBitsK ;[10] + pop YH ;[11] undo the push from before + rjmp waitForK ;[13] this was not the end of sync, retry +haveTwoBitsK: +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +#define fix x2 +#define data x1 + + push shift ;[12] + push x1 ;[14] + push x2 ;[16] + ldi shift, 0x80 ;[18] prevent bit-unstuffing but init low bits to 0 + ifioset USBIN, USBMINUS ;[19] [01] <--- bit 0 [10.5 + 8 = 18.5] + ori shift, 1<<0 ;[02] + push x3 ;[03] + push cnt ;[05] + push r0 ;[07] + ifioset USBIN, USBMINUS ;[09] <--- bit 1 + ori shift, 1<<1 ;[10] + ser fix ;[11] + ldi cnt, USB_BUFSIZE ;[12] + mov data, shift ;[13] + lsl shift ;[14] + nop2 ;[15] + ifioset USBIN, USBMINUS ;[17] <--- bit 2 + ori data, 3<<2 ;[18] store in bit 2 AND bit 3 + eor shift, data ;[19] do nrzi decoding + andi data, 1<<3 ;[20] + in phase, USBIN ;[21] <- phase + brne jumpToEntryAfterSet ;[22] if USBMINS at bit 3 was 1 + nop ;[23] + rjmp entryAfterClr ;[24] +jumpToEntryAfterSet: + rjmp entryAfterSet ;[24] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +#undef fix +#define fix x1 +#undef data +#define data x2 + +bit7IsSet: + ifrclr phase, USBMINUS ;[62] check phase only if D- changed + lpm ;[63] + in phase, USBIN ;[64] <- phase (one cycle too late) + ori shift, 1 << 7 ;[65] + nop ;[66] +;;;;rjmp bit0AfterSet ; -> [00] == [67] moved block up to save jump +bit0AfterSet: + eor fix, shift ;[00] +#undef fix +#define fix x2 +#undef data +#define data x1 /* we now have result in data, fix is reset to 0xff */ + ifioclr USBIN, USBMINUS ;[01] <--- sample 0 + rjmp bit0IsClr ;[02] + andi shift, ~(7 << 0) ;[03] + breq unstuff0s ;[04] + in phase, USBIN ;[05] <- phase + rjmp bit1AfterSet ;[06] +unstuff0s: + in phase, USBIN ;[06] <- phase (one cycle too late) + andi fix, ~(1 << 0) ;[07] + ifioclr USBIN, USBMINUS ;[00] + ifioset USBIN, USBPLUS ;[01] + rjmp bit0IsClr ;[02] executed if first expr false or second true +se0AndStore: ; executed only if both bits 0 + st y+, x1 ;[15/17] cycles after start of byte + rjmp se0 ;[17/19] + +bit0IsClr: + ifrset phase, USBMINUS ;[04] check phase only if D- changed + lpm ;[05] + in phase, USBIN ;[06] <- phase (one cycle too late) + ori shift, 1 << 0 ;[07] +bit1AfterClr: + andi phase, USBMASK ;[08] + ifioset USBIN, USBMINUS ;[09] <--- sample 1 + rjmp bit1IsSet ;[10] + breq se0AndStore ;[11] if D- was 0 in bits 0 AND 1 and D+ was 0 in between, we have SE0 + andi shift, ~(7 << 1) ;[12] + in phase, USBIN ;[13] <- phase + breq unstuff1c ;[14] + rjmp bit2AfterClr ;[15] +unstuff1c: + andi fix, ~(1 << 1) ;[16] + nop2 ;[08] + nop2 ;[10] +bit1IsSet: + ifrclr phase, USBMINUS ;[12] check phase only if D- changed + lpm ;[13] + in phase, USBIN ;[14] <- phase (one cycle too late) + ori shift, 1 << 1 ;[15] + nop ;[16] +bit2AfterSet: + ifioclr USBIN, USBMINUS ;[17] <--- sample 2 + rjmp bit2IsClr ;[18] + andi shift, ~(7 << 2) ;[19] + breq unstuff2s ;[20] + in phase, USBIN ;[21] <- phase + rjmp bit3AfterSet ;[22] +unstuff2s: + in phase, USBIN ;[22] <- phase (one cycle too late) + andi fix, ~(1 << 2) ;[23] + nop2 ;[16] + nop2 ;[18] +bit2IsClr: + ifrset phase, USBMINUS ;[20] check phase only if D- changed + lpm ;[21] + in phase, USBIN ;[22] <- phase (one cycle too late) + ori shift, 1 << 2 ;[23] +bit3AfterClr: + st y+, data ;[24] +entryAfterClr: + ifioset USBIN, USBMINUS ;[26] <--- sample 3 + rjmp bit3IsSet ;[27] + andi shift, ~(7 << 3) ;[28] + breq unstuff3c ;[29] + in phase, USBIN ;[30] <- phase + rjmp bit4AfterClr ;[31] +unstuff3c: + in phase, USBIN ;[31] <- phase (one cycle too late) + andi fix, ~(1 << 3) ;[32] + nop2 ;[25] + nop2 ;[27] +bit3IsSet: + ifrclr phase, USBMINUS ;[29] check phase only if D- changed + lpm ;[30] + in phase, USBIN ;[31] <- phase (one cycle too late) + ori shift, 1 << 3 ;[32] +bit4AfterSet: + mov data, fix ;[33] undo this move by swapping defines +#undef fix +#define fix x1 +#undef data +#define data x2 + ifioclr USBIN, USBMINUS ;[34] <--- sample 4 + rjmp bit4IsClr ;[35] + andi shift, ~(7 << 4) ;[36] + breq unstuff4s ;[37] + in phase, USBIN ;[38] <- phase + rjmp bit5AfterSet ;[39] +unstuff4s: + in phase, USBIN ;[39] <- phase (one cycle too late) + andi fix, ~(1 << 4) ;[40] + nop2 ;[33] + nop2 ;[35] +bit4IsClr: + ifrset phase, USBMINUS ;[37] check phase only if D- changed + lpm ;[38] + in phase, USBIN ;[39] <- phase (one cycle too late) + ori shift, 1 << 4 ;[40] +bit5AfterClr: + ser data ;[41] + ifioset USBIN, USBMINUS ;[42] <--- sample 5 + rjmp bit5IsSet ;[43] + andi shift, ~(7 << 5) ;[44] + breq unstuff5c ;[45] + in phase, USBIN ;[46] <- phase + rjmp bit6AfterClr ;[47] +unstuff5c: + in phase, USBIN ;[47] <- phase (one cycle too late) + andi fix, ~(1 << 5) ;[48] + nop2 ;[41] + nop2 ;[43] +bit5IsSet: + ifrclr phase, USBMINUS ;[45] check phase only if D- changed + lpm ;[46] + in phase, USBIN ;[47] <- phase (one cycle too late) + ori shift, 1 << 5 ;[48] +bit6AfterSet: + subi cnt, 1 ;[49] + brcs jumpToOverflow ;[50] + ifioclr USBIN, USBMINUS ;[51] <--- sample 6 + rjmp bit6IsClr ;[52] + andi shift, ~(3 << 6) ;[53] + cpi shift, 2 ;[54] + in phase, USBIN ;[55] <- phase + brlt unstuff6s ;[56] + rjmp bit7AfterSet ;[57] + +jumpToOverflow: + rjmp overflow + +unstuff6s: + andi fix, ~(1 << 6) ;[50] + lpm ;[51] +bit6IsClr: + ifrset phase, USBMINUS ;[54] check phase only if D- changed + lpm ;[55] + in phase, USBIN ;[56] <- phase (one cycle too late) + ori shift, 1 << 6 ;[57] + nop ;[58] +bit7AfterClr: + ifioset USBIN, USBMINUS ;[59] <--- sample 7 + rjmp bit7IsSet ;[60] + andi shift, ~(1 << 7) ;[61] + cpi shift, 4 ;[62] + in phase, USBIN ;[63] <- phase + brlt unstuff7c ;[64] + rjmp bit0AfterClr ;[65] -> [00] == [67] +unstuff7c: + andi fix, ~(1 << 7) ;[58] + nop ;[59] + rjmp bit7IsSet ;[60] + +bit7IsClr: + ifrset phase, USBMINUS ;[62] check phase only if D- changed + lpm ;[63] + in phase, USBIN ;[64] <- phase (one cycle too late) + ori shift, 1 << 7 ;[65] + nop ;[66] +;;;;rjmp bit0AfterClr ; -> [00] == [67] moved block up to save jump +bit0AfterClr: + eor fix, shift ;[00] +#undef fix +#define fix x2 +#undef data +#define data x1 /* we now have result in data, fix is reset to 0xff */ + ifioset USBIN, USBMINUS ;[01] <--- sample 0 + rjmp bit0IsSet ;[02] + andi shift, ~(7 << 0) ;[03] + breq unstuff0c ;[04] + in phase, USBIN ;[05] <- phase + rjmp bit1AfterClr ;[06] +unstuff0c: + in phase, USBIN ;[06] <- phase (one cycle too late) + andi fix, ~(1 << 0) ;[07] + ifioclr USBIN, USBMINUS ;[00] + ifioset USBIN, USBPLUS ;[01] + rjmp bit0IsSet ;[02] executed if first expr false or second true + rjmp se0AndStore ;[03] executed only if both bits 0 +bit0IsSet: + ifrclr phase, USBMINUS ;[04] check phase only if D- changed + lpm ;[05] + in phase, USBIN ;[06] <- phase (one cycle too late) + ori shift, 1 << 0 ;[07] +bit1AfterSet: + andi shift, ~(7 << 1) ;[08] compensated by "ori shift, 1<<1" if bit1IsClr + ifioclr USBIN, USBMINUS ;[09] <--- sample 1 + rjmp bit1IsClr ;[10] + breq unstuff1s ;[11] + nop2 ;[12] do not check for SE0 if bit 0 was 1 + in phase, USBIN ;[14] <- phase (one cycle too late) + rjmp bit2AfterSet ;[15] +unstuff1s: + in phase, USBIN ;[13] <- phase + andi fix, ~(1 << 1) ;[14] + lpm ;[07] + nop2 ;[10] +bit1IsClr: + ifrset phase, USBMINUS ;[12] check phase only if D- changed + lpm ;[13] + in phase, USBIN ;[14] <- phase (one cycle too late) + ori shift, 1 << 1 ;[15] + nop ;[16] +bit2AfterClr: + ifioset USBIN, USBMINUS ;[17] <--- sample 2 + rjmp bit2IsSet ;[18] + andi shift, ~(7 << 2) ;[19] + breq unstuff2c ;[20] + in phase, USBIN ;[21] <- phase + rjmp bit3AfterClr ;[22] +unstuff2c: + in phase, USBIN ;[22] <- phase (one cycle too late) + andi fix, ~(1 << 2) ;[23] + nop2 ;[16] + nop2 ;[18] +bit2IsSet: + ifrclr phase, USBMINUS ;[20] check phase only if D- changed + lpm ;[21] + in phase, USBIN ;[22] <- phase (one cycle too late) + ori shift, 1 << 2 ;[23] +bit3AfterSet: + st y+, data ;[24] +entryAfterSet: + ifioclr USBIN, USBMINUS ;[26] <--- sample 3 + rjmp bit3IsClr ;[27] + andi shift, ~(7 << 3) ;[28] + breq unstuff3s ;[29] + in phase, USBIN ;[30] <- phase + rjmp bit4AfterSet ;[31] +unstuff3s: + in phase, USBIN ;[31] <- phase (one cycle too late) + andi fix, ~(1 << 3) ;[32] + nop2 ;[25] + nop2 ;[27] +bit3IsClr: + ifrset phase, USBMINUS ;[29] check phase only if D- changed + lpm ;[30] + in phase, USBIN ;[31] <- phase (one cycle too late) + ori shift, 1 << 3 ;[32] +bit4AfterClr: + mov data, fix ;[33] undo this move by swapping defines +#undef fix +#define fix x1 +#undef data +#define data x2 + ifioset USBIN, USBMINUS ;[34] <--- sample 4 + rjmp bit4IsSet ;[35] + andi shift, ~(7 << 4) ;[36] + breq unstuff4c ;[37] + in phase, USBIN ;[38] <- phase + rjmp bit5AfterClr ;[39] +unstuff4c: + in phase, USBIN ;[39] <- phase (one cycle too late) + andi fix, ~(1 << 4) ;[40] + nop2 ;[33] + nop2 ;[35] +bit4IsSet: + ifrclr phase, USBMINUS ;[37] check phase only if D- changed + lpm ;[38] + in phase, USBIN ;[39] <- phase (one cycle too late) + ori shift, 1 << 4 ;[40] +bit5AfterSet: + ser data ;[41] + ifioclr USBIN, USBMINUS ;[42] <--- sample 5 + rjmp bit5IsClr ;[43] + andi shift, ~(7 << 5) ;[44] + breq unstuff5s ;[45] + in phase, USBIN ;[46] <- phase + rjmp bit6AfterSet ;[47] +unstuff5s: + in phase, USBIN ;[47] <- phase (one cycle too late) + andi fix, ~(1 << 5) ;[48] + nop2 ;[41] + nop2 ;[43] +bit5IsClr: + ifrset phase, USBMINUS ;[45] check phase only if D- changed + lpm ;[46] + in phase, USBIN ;[47] <- phase (one cycle too late) + ori shift, 1 << 5 ;[48] +bit6AfterClr: + subi cnt, 1 ;[49] + brcs overflow ;[50] + ifioset USBIN, USBMINUS ;[51] <--- sample 6 + rjmp bit6IsSet ;[52] + andi shift, ~(3 << 6) ;[53] + cpi shift, 2 ;[54] + in phase, USBIN ;[55] <- phase + brlt unstuff6c ;[56] + rjmp bit7AfterClr ;[57] +unstuff6c: + andi fix, ~(1 << 6) ;[50] + lpm ;[51] +bit6IsSet: + ifrclr phase, USBMINUS ;[54] check phase only if D- changed + lpm ;[55] + in phase, USBIN ;[56] <- phase (one cycle too late) + ori shift, 1 << 6 ;[57] +bit7AfterSet: + ifioclr USBIN, USBMINUS ;[59] <--- sample 7 + rjmp bit7IsClr ;[60] + andi shift, ~(1 << 7) ;[61] + cpi shift, 4 ;[62] + in phase, USBIN ;[63] <- phase + brlt unstuff7s ;[64] + rjmp bit0AfterSet ;[65] -> [00] == [67] +unstuff7s: + andi fix, ~(1 << 7) ;[58] + nop ;[59] + rjmp bit7IsClr ;[60] + +macro POP_STANDARD ; 14 cycles + pop r0 + pop cnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;---------------------------------------------------------------------------- +; Transmitting data +;---------------------------------------------------------------------------- + +txByteLoop: +txBitloop: +stuffN1Delay: ; [03] + ror shift ;[-5] [11] [63] + brcc doExorN1 ;[-4] [64] + subi x3, 1 ;[-3] + brne commonN1 ;[-2] + lsl shift ;[-1] compensate ror after rjmp stuffDelay + nop ;[00] stuffing consists of just waiting 8 cycles + rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear + +sendNakAndReti: + ldi cnt, USBPID_NAK ;[-19] + rjmp sendCntAndReti ;[-18] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov r0, cnt ;[-16] + ldi YL, 0 ;[-15] R0 address is 0 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) or USBOUT = 0x01 +; K = (D+ = 1), (D- = 0) or USBOUT = 0x02 +; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles) + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte +;uses: x1...x3, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x3 = bitstuff cnt] +;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction) +usbSendAndReti: + in x2, USBDDR ;[-10] 10 cycles until SOP + ori x2, USBMASK ;[-9] + sbi USBOUT, USBMINUS ;[-8] prepare idle state; D+ and D- must have been 0 (no pullups) + out USBDDR, x2 ;[-6] <--- acquire bus + in x1, USBOUT ;[-5] port mirror for tx loop + ldi shift, 0x40 ;[-4] sync byte is first byte sent (we enter loop after ror) + ldi x2, USBMASK ;[-3] +doExorN1: + eor x1, x2 ;[-2] [06] [62] + ldi x3, 6 ;[-1] [07] [63] +commonN1: +stuffN2Delay: + out USBOUT, x1 ;[00] [08] [64] <--- set bit + ror shift ;[01] + brcc doExorN2 ;[02] + subi x3, 1 ;[03] + brne commonN2 ;[04] + lsl shift ;[05] compensate ror after rjmp stuffDelay + rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear +doExorN2: + eor x1, x2 ;[04] [12] + ldi x3, 6 ;[05] [13] +commonN2: + nop2 ;[06] [14] + subi cnt, 171 ;[08] [16] trick: (3 * 171) & 0xff = 1 + out USBOUT, x1 ;[09] [17] <--- set bit + brcs txBitloop ;[10] [27] [44] + +stuff6Delay: + ror shift ;[45] [53] + brcc doExor6 ;[46] + subi x3, 1 ;[47] + brne common6 ;[48] + lsl shift ;[49] compensate ror after rjmp stuffDelay + nop ;[50] stuffing consists of just waiting 8 cycles + rjmp stuff6Delay ;[51] after ror, C bit is reliably clear +doExor6: + eor x1, x2 ;[48] [56] + ldi x3, 6 ;[49] +common6: +stuff7Delay: + ror shift ;[50] [58] + out USBOUT, x1 ;[51] <--- set bit + brcc doExor7 ;[52] + subi x3, 1 ;[53] + brne common7 ;[54] + lsl shift ;[55] compensate ror after rjmp stuffDelay + rjmp stuff7Delay ;[56] after ror, C bit is reliably clear +doExor7: + eor x1, x2 ;[54] [62] + ldi x3, 6 ;[55] +common7: + ld shift, y+ ;[56] + nop ;[58] + tst cnt ;[59] + out USBOUT, x1 ;[60] [00]<--- set bit + brne txByteLoop ;[61] [01] +;make SE0: + cbr x1, USBMASK ;[02] prepare SE0 [spec says EOP may be 15 to 18 cycles] + lds x2, usbNewDeviceAddr;[03] + lsl x2 ;[05] we compare with left shifted address + subi YL, 2 + 0 ;[06] Only assign address on data packets, not ACK/NAK in r0 + sbci YH, 0 ;[07] + out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[01] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 0) + echo "$s\n"; + } +} + +function printBit($isAfterSet, $bitNum) +{ + ob_start(); + if($isAfterSet){ +?> + ifioclr USBIN, USBMINUS ;[00] <--- sample + rjmp bit#IsClr ;[01] + andi shift, ~(7 << #) ;[02] + breq unstuff#s ;[03] + in phase, USBIN ;[04] <- phase + rjmp bit@AfterSet ;[05] +unstuff#s: + in phase, USBIN ;[05] <- phase (one cycle too late) + andi fix, ~(1 << #) ;[06] + nop2 ;[-1] + nop2 ;[01] +bit#IsClr: + ifrset phase, USBMINUS ;[03] check phase only if D- changed + lpm ;[04] + in phase, USBIN ;[05] <- phase (one cycle too late) + ori shift, 1 << # ;[06] + + ifioset USBIN, USBMINUS ;[00] <--- sample + rjmp bit#IsSet ;[01] + andi shift, ~(7 << #) ;[02] + breq unstuff#c ;[03] + in phase, USBIN ;[04] <- phase + rjmp bit@AfterClr ;[05] +unstuff#c: + in phase, USBIN ;[05] <- phase (one cycle too late) + andi fix, ~(1 << #) ;[06] + nop2 ;[-1] + nop2 ;[01] +bit#IsSet: + ifrclr phase, USBMINUS ;[03] check phase only if D- changed + lpm ;[04] + in phase, USBIN ;[05] <- phase (one cycle too late) + ori shift, 1 << # ;[06] + +*****************************************************************************/ diff --git a/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm15.inc b/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm15.inc new file mode 100644 index 0000000..401b7f8 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm15.inc @@ -0,0 +1,423 @@ +/* Name: usbdrvasm15.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: contributed by V. Bosch + * Creation Date: 2007-08-06 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm15.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 15 MHz version of the asssembler part of the USB driver. It +requires a 15 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! +*/ + +;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + +;---------------------------------------------------------------------------- +; order of registers pushed: +; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4 +;---------------------------------------------------------------------------- +USB_INTR_VECTOR: + push YL ;2 push only what is necessary to sync with edge ASAP + in YL, SREG ;1 + push YL ;2 +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +; +; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +; sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +;------------------------------------------------------------------------------- +; The following code results in a sampling window of < 1/4 bit +; which meets the spec. +;------------------------------------------------------------------------------- +waitForK: ;- + sbis USBIN, USBMINUS ;1 [00] <-- sample + rjmp foundK ;2 [01] + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +;------------------------------------------------------------------------------ +; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for +; center sampling] +; we have 1 bit time for setup purposes, then sample again. +; Numbers in brackets are cycles from center of first sync (double K) +; bit after the instruction +;------------------------------------------------------------------------------ +foundK: ;- [02] + lds YL, usbInputBufOffset;2 [03+04] tx loop + push YH ;2 [05+06] + clr YH ;1 [07] + subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init] + sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init] + push shift ;2 [10+11] + ser shift ;1 [12] + sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early) + rjmp haveTwoBitsK ;2 [00] [14] + pop shift ;2 [15+16] undo the push from before + pop YH ;2 [17+18] undo the push from before + rjmp waitForK ;2 [19+20] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 20 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: ;- [01] + push x1 ;2 [02+03] + push x2 ;2 [04+05] + push x3 ;2 [06+07] + push bitcnt ;2 [08+09] + in x1, USBIN ;1 [00] [10] <-- sample bit 0 + bst x1, USBMINUS ;1 [01] + bld shift, 0 ;1 [02] + push cnt ;2 [03+04] + ldi cnt, USB_BUFSIZE ;1 [05] + push x4 ;2 [06+07] tx loop + rjmp rxLoop ;2 [08] +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +unstuff0: ;- [07] (branch taken) + andi x3, ~0x01 ;1 [08] + mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit + in x2, USBIN ;1 [00] [10] <-- sample bit 1 again + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 1 + ori shift, 0x01 ;1 [03] 0b00000001 + nop ;1 [04] + rjmp didUnstuff0 ;2 [05] +;----------------------------------------------------- +unstuff1: ;- [05] (branch taken) + mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit + andi x3, ~0x02 ;1 [07] + ori shift, 0x02 ;1 [08] 0b00000010 + nop ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 2 again + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 2 + rjmp didUnstuff1 ;2 [03] +;----------------------------------------------------- +unstuff2: ;- [05] (branch taken) + andi x3, ~0x04 ;1 [06] + ori shift, 0x04 ;1 [07] 0b00000100 + mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit + nop ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample bit 3 + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 3 + rjmp didUnstuff2 ;2 [03] +;----------------------------------------------------- +unstuff3: ;- [00] [10] (branch taken) + in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late + andi x2, USBMASK ;1 [02] + breq se0Hop ;1 [03] SE0 check for stuffed bit 3 + andi x3, ~0x08 ;1 [04] + ori shift, 0x08 ;1 [05] 0b00001000 + rjmp didUnstuff3 ;2 [06] +;---------------------------------------------------------------------------- +; extra jobs done during bit interval: +; +; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs], +; overflow check, jump to the head of rxLoop +; bit 1: SE0 check +; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long] +; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long] +; bit 4: SE0 check, none +; bit 5: SE0 check, none +; bit 6: SE0 check, none +; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others +;---------------------------------------------------------------------------- +rxLoop: ;- [09] + in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed) + andi x2, USBMASK ;1 [01] + brne SkipSe0Hop ;1 [02] +se0Hop: ;- [02] + rjmp se0 ;2 [03] SE0 check for bit 1 +SkipSe0Hop: ;- [03] + ser x3 ;1 [04] + andi shift, 0xf9 ;1 [05] 0b11111001 + breq unstuff0 ;1 [06] +didUnstuff0: ;- [06] + eor x1, x2 ;1 [07] + bst x1, USBMINUS ;1 [08] + bld shift, 1 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed) + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 2 + andi shift, 0xf3 ;1 [03] 0b11110011 + breq unstuff1 ;1 [04] do remaining work for bit 1 +didUnstuff1: ;- [04] + eor x2, x1 ;1 [05] + bst x2, USBMINUS ;1 [06] + bld shift, 2 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed) + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 3 + andi shift, 0xe7 ;1 [03] 0b11100111 + breq unstuff2 ;1 [04] +didUnstuff2: ;- [04] + eor x1, x2 ;1 [05] + bst x1, USBMINUS ;1 [06] + bld shift, 3 ;1 [07] +didUnstuff3: ;- [07] + andi shift, 0xcf ;1 [08] 0b11001111 + breq unstuff3 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 4 + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 4 + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 4 ;1 [05] +didUnstuff4: ;- [05] + andi shift, 0x9f ;1 [06] 0b10011111 + breq unstuff4 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 5 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 5 + eor x1, x2 ;1 [03] + bst x1, USBMINUS ;1 [04] + bld shift, 5 ;1 [05] +didUnstuff5: ;- [05] + andi shift, 0x3f ;1 [06] 0b00111111 + breq unstuff5 ;1 [07] + nop2 ;2 [08+09] + in x1, USBIN ;1 [00] [10] <-- sample bit 6 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 6 + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 6 ;1 [05] +didUnstuff6: ;- [05] + cpi shift, 0x02 ;1 [06] 0b00000010 + brlo unstuff6 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 7 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 7 + eor x1, x2 ;1 [03] + bst x1, USBMINUS ;1 [04] + bld shift, 7 ;1 [05] +didUnstuff7: ;- [05] + cpi shift, 0x04 ;1 [06] 0b00000100 + brlo unstuff7 ;1 [07] + eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others + nop ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 0 + st y+, x3 ;2 [01+02] store data + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 0 ;1 [05] + subi cnt, 1 ;1 [06] + brcs overflow ;1 [07] + rjmp rxLoop ;2 [08] +;----------------------------------------------------- +unstuff4: ;- [08] + andi x3, ~0x10 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 4 + ori shift, 0x10 ;1 [03] + rjmp didUnstuff4 ;2 [04] +;----------------------------------------------------- +unstuff5: ;- [08] + ori shift, 0x20 ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 5 + andi x3, ~0x20 ;1 [03] + rjmp didUnstuff5 ;2 [04] +;----------------------------------------------------- +unstuff6: ;- [08] + andi x3, ~0x40 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 6 + ori shift, 0x40 ;1 [03] + rjmp didUnstuff6 ;2 [04] +;----------------------------------------------------- +unstuff7: ;- [08] + andi x3, ~0x80 ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 7 + ori shift, 0x80 ;1 [03] + rjmp didUnstuff7 ;2 [04] + +macro POP_STANDARD ; 16 cycles + pop x4 + pop cnt + pop bitcnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;--------------------------------------------------------------------------- +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies +;--------------------------------------------------------------------------- +bitstuffN: ;- [04] + eor x1, x4 ;1 [05] + clr x2 ;1 [06] + nop ;1 [07] + rjmp didStuffN ;1 [08] +;--------------------------------------------------------------------------- +bitstuff6: ;- [04] + eor x1, x4 ;1 [05] + clr x2 ;1 [06] + rjmp didStuff6 ;1 [07] +;--------------------------------------------------------------------------- +bitstuff7: ;- [02] + eor x1, x4 ;1 [03] + clr x2 ;1 [06] + nop ;1 [05] + rjmp didStuff7 ;1 [06] +;--------------------------------------------------------------------------- +sendNakAndReti: ;- [-19] + ldi x3, USBPID_NAK ;1 [-18] + rjmp sendX3AndReti ;1 [-17] +;--------------------------------------------------------------------------- +sendAckAndReti: ;- [-17] + ldi cnt, USBPID_ACK ;1 [-16] +sendCntAndReti: ;- [-16] + mov x3, cnt ;1 [-15] +sendX3AndReti: ;- [-15] + ldi YL, 20 ;1 [-14] x3==r20 address is 20 + ldi YH, 0 ;1 [-13] + ldi cnt, 2 ;1 [-12] +; rjmp usbSendAndReti fallthrough +;--------------------------------------------------------------------------- +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +;We need not to match the transfer rate exactly because the spec demands +;only 1.5% precision anyway. +usbSendAndReti: ;- [-13] 13 cycles until SOP + in x2, USBDDR ;1 [-12] + ori x2, USBMASK ;1 [-11] + sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;1 [-08] port mirror for tx loop + out USBDDR, x2 ;1 [-07] <- acquire bus + ; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;1 [-06] exor mask + ldi shift, 0x80 ;1 [-05] sync byte is first byte sent + ldi bitcnt, 6 ;1 [-04] +txBitLoop: ;- [-04] [06] + sbrs shift, 0 ;1 [-03] [07] + eor x1, x4 ;1 [-02] [08] + ror shift ;1 [-01] [09] +didStuffN: ;- [09] + out USBOUT, x1 ;1 [00] [10] <-- out N + ror x2 ;1 [01] + cpi x2, 0xfc ;1 [02] + brcc bitstuffN ;1 [03] + dec bitcnt ;1 [04] + brne txBitLoop ;1 [05] + sbrs shift, 0 ;1 [06] + eor x1, x4 ;1 [07] + ror shift ;1 [08] +didStuff6: ;- [08] + nop ;1 [09] + out USBOUT, x1 ;1 [00] [10] <-- out 6 + ror x2 ;1 [01] + cpi x2, 0xfc ;1 [02] + brcc bitstuff6 ;1 [03] + sbrs shift, 0 ;1 [04] + eor x1, x4 ;1 [05] + ror shift ;1 [06] + ror x2 ;1 [07] +didStuff7: ;- [07] + ldi bitcnt, 6 ;1 [08] + cpi x2, 0xfc ;1 [09] + out USBOUT, x1 ;1 [00] [10] <-- out 7 + brcc bitstuff7 ;1 [01] + ld shift, y+ ;2 [02+03] + dec cnt ;1 [04] + brne txBitLoop ;1 [05] +makeSE0: + cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles] + lds x2, usbNewDeviceAddr;2 [07+08] + lsl x2 ;1 [09] we compare with left shifted address +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle + subi YL, 20 + 2 ;1 [01] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;1 [02] + breq skipAddrAssign ;1 [03] + sts usbDeviceAddr, x2 ;2 [04+05] if not skipped: SE0 is one cycle longer +;---------------------------------------------------------------------------- +;end of usbDeviceAddress transfer +skipAddrAssign: ;- [03/04] + ldi x2, 1< 10.6666666 cycles per bit, 85.333333333 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt + push YL ;[-25] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-23] + push YL ;[-22] + push YH ;[-20] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-15] + rjmp foundK ;[-14] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-12] +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push bitcnt ;[-12] +; [---] ;[-11] + lds YL, usbInputBufOffset;[-10] +; [---] ;[-9] + clr YH ;[-8] + subi YL, lo8(-(usbRxBuf));[-7] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init] + push shift ;[-5] +; [---] ;[-4] + ldi bitcnt, 0x55 ;[-3] [rx loop init] + sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early) + rjmp haveTwoBitsK ;[-1] + pop shift ;[0] undo the push from before + pop bitcnt ;[2] undo the push from before + rjmp waitForK ;[4] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 21 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[1] + push x2 ;[3] + push x3 ;[5] + ldi shift, 0 ;[7] + ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that + push x4 ;[9] == leap + + in x1, USBIN ;[11] <-- sample bit 0 + andi x1, USBMASK ;[12] + bst x1, USBMINUS ;[13] + bld shift, 7 ;[14] + push cnt ;[15] + ldi leap, 0 ;[17] [rx loop init] + ldi cnt, USB_BUFSIZE;[18] [rx loop init] + rjmp rxbit1 ;[19] arrives at [21] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- + +; duration of unstuffing code should be 10.66666667 cycles. We adjust "leap" +; accordingly to approximate this value in the long run. + +unstuff6: + andi x2, USBMASK ;[03] + ori x3, 1<<6 ;[04] will not be shifted any more + andi shift, ~0x80;[05] + mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6 + subi leap, -1 ;[07] total duration = 11 bits -> subtract 1/3 + rjmp didUnstuff6 ;[08] + +unstuff7: + ori x3, 1<<7 ;[09] will not be shifted any more + in x2, USBIN ;[00] [10] re-sample bit 7 + andi x2, USBMASK ;[01] + andi shift, ~0x80;[02] + subi leap, 2 ;[03] total duration = 10 bits -> add 1/3 + rjmp didUnstuff7 ;[04] + +unstuffEven: + ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0 + in x1, USBIN ;[00] [10] + andi shift, ~0x80;[01] + andi x1, USBMASK ;[02] + breq se0 ;[03] + subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3 + nop2 ;[05] + rjmp didUnstuffE ;[06] + +unstuffOdd: + ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1 + in x2, USBIN ;[00] [10] + andi shift, ~0x80;[01] + andi x2, USBMASK ;[02] + breq se0 ;[03] + subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3 + nop2 ;[05] + rjmp didUnstuffO ;[06] + +rxByteLoop: + andi x1, USBMASK ;[03] + eor x2, x1 ;[04] + subi leap, 1 ;[05] + brpl skipLeap ;[06] + subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte + nop ;1 +skipLeap: + subi x2, 1 ;[08] + ror shift ;[09] +didUnstuff6: + cpi shift, 0xfc ;[10] + in x2, USBIN ;[00] [11] <-- sample bit 7 + brcc unstuff6 ;[01] + andi x2, USBMASK ;[02] + eor x1, x2 ;[03] + subi x1, 1 ;[04] + ror shift ;[05] +didUnstuff7: + cpi shift, 0xfc ;[06] + brcc unstuff7 ;[07] + eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others + st y+, x3 ;[09] store data +rxBitLoop: + in x1, USBIN ;[00] [11] <-- sample bit 0/2/4 + andi x1, USBMASK ;[01] + eor x2, x1 ;[02] + andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7 + subi x2, 1 ;[04] + ror shift ;[05] + cpi shift, 0xfc ;[06] + brcc unstuffEven ;[07] +didUnstuffE: + lsr x3 ;[08] + lsr x3 ;[09] +rxbit1: + in x2, USBIN ;[00] [10] <-- sample bit 1/3/5 + andi x2, USBMASK ;[01] + breq se0 ;[02] + eor x1, x2 ;[03] + subi x1, 1 ;[04] + ror shift ;[05] + cpi shift, 0xfc ;[06] + brcc unstuffOdd ;[07] +didUnstuffO: + subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3 + brcs rxBitLoop ;[09] + + subi cnt, 1 ;[10] + in x1, USBIN ;[00] [11] <-- sample bit 6 + brcc rxByteLoop ;[01] + rjmp overflow + +macro POP_STANDARD ; 14 cycles + pop cnt + pop x4 + pop x3 + pop x2 + pop x1 + pop shift + pop bitcnt + endm +macro POP_RETI ; 7 cycles + pop YH + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies + +bitstuffN: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] + nop2 ;[7] + nop ;[9] + out USBOUT, x1 ;[10] <-- out + rjmp didStuffN ;[0] + +bitstuff6: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] Carry is zero due to brcc + rol shift ;[7] compensate for ror shift at branch destination + rjmp didStuff6 ;[8] + +bitstuff7: + ldi x2, 0 ;[2] Carry is zero due to brcc + rjmp didStuff7 ;[3] + + +sendNakAndReti: + ldi x3, USBPID_NAK ;[-18] + rjmp sendX3AndReti ;[-17] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov x3, cnt ;[-16] +sendX3AndReti: + ldi YL, 20 ;[-15] x3==r20 address is 20 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +;We don't match the transfer rate exactly (don't insert leap cycles every third +;byte) because the spec demands only 1.5% precision anyway. +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-7] <- acquire bus +; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-6] exor mask + ldi shift, 0x80 ;[-5] sync byte is first byte sent +txByteLoop: + ldi bitcnt, 0x35 ;[-4] [6] binary 0011 0101 +txBitLoop: + sbrs shift, 0 ;[-3] [7] + eor x1, x4 ;[-2] [8] + out USBOUT, x1 ;[-1] [9] <-- out N + ror shift ;[0] [10] + ror x2 ;[1] +didStuffN: + cpi x2, 0xfc ;[2] + brcc bitstuffN ;[3] + lsr bitcnt ;[4] + brcc txBitLoop ;[5] + brne txBitLoop ;[6] + + sbrs shift, 0 ;[7] + eor x1, x4 ;[8] +didStuff6: + out USBOUT, x1 ;[-1] [9] <-- out 6 + ror shift ;[0] [10] + ror x2 ;[1] + cpi x2, 0xfc ;[2] + brcc bitstuff6 ;[3] + ror shift ;[4] +didStuff7: + ror x2 ;[5] + sbrs x2, 7 ;[6] + eor x1, x4 ;[7] + nop ;[8] + cpi x2, 0xfc ;[9] + out USBOUT, x1 ;[-1][10] <-- out 7 + brcc bitstuff7 ;[0] [11] + ld shift, y+ ;[1] + dec cnt ;[3] + brne txByteLoop ;[4] +;make SE0: + cbr x1, USBMASK ;[5] prepare SE0 [spec says EOP may be 21 to 25 cycles] + lds x2, usbNewDeviceAddr;[6] + lsl x2 ;[8] we compare with left shifted address + subi YL, 20 + 2 ;[9] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[10] + out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[0] + sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< max 52 cycles interrupt disable +;max stack usage: [ret(2), r0, SREG, YL, YH, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 16.5 MHz -> 11 cycles per bit +; 16.3125 MHz < F_CPU < 16.6875 MHz (+/- 1.1%) +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], r0, YH, shift, x1, x2, x3, x4, cnt + push YL ;[-23] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-21] + push YL ;[-20] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-15] + rjmp foundK ;[-14] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-12] +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push r0 ;[-12] +; [---] ;[-11] + push YH ;[-10] +; [---] ;[-9] + lds YL, usbInputBufOffset;[-8] +; [---] ;[-7] + clr YH ;[-6] + subi YL, lo8(-(usbRxBuf));[-5] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-4] [rx loop init] + mov r0, x2 ;[-3] [rx loop init] + sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early) + rjmp haveTwoBitsK ;[-1] + pop YH ;[0] undo the pushes from before + pop r0 ;[2] + rjmp waitForK ;[4] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 22 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: ;[1] + push shift ;[1] + push x1 ;[3] + push x2 ;[5] + push x3 ;[7] + ldi shift, 0xff ;[9] [rx loop init] + ori x3, 0xff ;[10] [rx loop init] == ser x3, clear zero flag + + in x1, USBIN ;[11] <-- sample bit 0 + bst x1, USBMINUS ;[12] + bld shift, 0 ;[13] + push x4 ;[14] == phase +; [---] ;[15] + push cnt ;[16] +; [---] ;[17] + ldi phase, 0 ;[18] [rx loop init] + ldi cnt, USB_BUFSIZE;[19] [rx loop init] + rjmp rxbit1 ;[20] +; [---] ;[21] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +/* +byte oriented operations done during loop: +bit 0: store data +bit 1: SE0 check +bit 2: overflow check +bit 3: catch up +bit 4: rjmp to achieve conditional jump range +bit 5: PLL +bit 6: catch up +bit 7: jump, fixup bitstuff +; 87 [+ 2] cycles +------------------------------------------------------------------ +*/ +continueWithBit5: + in x2, USBIN ;[055] <-- bit 5 + eor r0, x2 ;[056] + or phase, r0 ;[057] + sbrc phase, USBMINUS ;[058] + lpm ;[059] optional nop3; modifies r0 + in phase, USBIN ;[060] <-- phase + eor x1, x2 ;[061] + bst x1, USBMINUS ;[062] + bld shift, 5 ;[063] + andi shift, 0x3f ;[064] + in x1, USBIN ;[065] <-- bit 6 + breq unstuff5 ;[066] *** unstuff escape + eor phase, x1 ;[067] + eor x2, x1 ;[068] + bst x2, USBMINUS ;[069] + bld shift, 6 ;[070] +didUnstuff6: ;[ ] + in r0, USBIN ;[071] <-- phase + cpi shift, 0x02 ;[072] + brlo unstuff6 ;[073] *** unstuff escape +didUnstuff5: ;[ ] + nop2 ;[074] +; [---] ;[075] + in x2, USBIN ;[076] <-- bit 7 + eor x1, x2 ;[077] + bst x1, USBMINUS ;[078] + bld shift, 7 ;[079] +didUnstuff7: ;[ ] + eor r0, x2 ;[080] + or phase, r0 ;[081] + in r0, USBIN ;[082] <-- phase + cpi shift, 0x04 ;[083] + brsh rxLoop ;[084] +; [---] ;[085] +unstuff7: ;[ ] + andi x3, ~0x80 ;[085] + ori shift, 0x80 ;[086] + in x2, USBIN ;[087] <-- sample stuffed bit 7 + nop ;[088] + rjmp didUnstuff7 ;[089] +; [---] ;[090] + ;[080] + +unstuff5: ;[067] + eor phase, x1 ;[068] + andi x3, ~0x20 ;[069] + ori shift, 0x20 ;[070] + in r0, USBIN ;[071] <-- phase + mov x2, x1 ;[072] + nop ;[073] + nop2 ;[074] +; [---] ;[075] + in x1, USBIN ;[076] <-- bit 6 + eor r0, x1 ;[077] + or phase, r0 ;[078] + eor x2, x1 ;[079] + bst x2, USBMINUS ;[080] + bld shift, 6 ;[081] no need to check bitstuffing, we just had one + in r0, USBIN ;[082] <-- phase + rjmp didUnstuff5 ;[083] +; [---] ;[084] + ;[074] + +unstuff6: ;[074] + andi x3, ~0x40 ;[075] + in x1, USBIN ;[076] <-- bit 6 again + ori shift, 0x40 ;[077] + nop2 ;[078] +; [---] ;[079] + rjmp didUnstuff6 ;[080] +; [---] ;[081] + ;[071] + +unstuff0: ;[013] + eor r0, x2 ;[014] + or phase, r0 ;[015] + andi x2, USBMASK ;[016] check for SE0 + in r0, USBIN ;[017] <-- phase + breq didUnstuff0 ;[018] direct jump to se0 would be too long + andi x3, ~0x01 ;[019] + ori shift, 0x01 ;[020] + mov x1, x2 ;[021] mov existing sample + in x2, USBIN ;[022] <-- bit 1 again + rjmp didUnstuff0 ;[023] +; [---] ;[024] + ;[014] + +unstuff1: ;[024] + eor r0, x1 ;[025] + or phase, r0 ;[026] + andi x3, ~0x02 ;[027] + in r0, USBIN ;[028] <-- phase + ori shift, 0x02 ;[029] + mov x2, x1 ;[030] + rjmp didUnstuff1 ;[031] +; [---] ;[032] + ;[022] + +unstuff2: ;[035] + eor r0, x2 ;[036] + or phase, r0 ;[037] + andi x3, ~0x04 ;[038] + in r0, USBIN ;[039] <-- phase + ori shift, 0x04 ;[040] + mov x1, x2 ;[041] + rjmp didUnstuff2 ;[042] +; [---] ;[043] + ;[033] + +unstuff3: ;[043] + in x2, USBIN ;[044] <-- bit 3 again + eor r0, x2 ;[045] + or phase, r0 ;[046] + andi x3, ~0x08 ;[047] + ori shift, 0x08 ;[048] + nop ;[049] + in r0, USBIN ;[050] <-- phase + rjmp didUnstuff3 ;[051] +; [---] ;[052] + ;[042] + +unstuff4: ;[053] + andi x3, ~0x10 ;[054] + in x1, USBIN ;[055] <-- bit 4 again + ori shift, 0x10 ;[056] + rjmp didUnstuff4 ;[057] +; [---] ;[058] + ;[048] + +rxLoop: ;[085] + eor x3, shift ;[086] reconstruct: x3 is 0 at bit locations we changed, 1 at others + in x1, USBIN ;[000] <-- bit 0 + st y+, x3 ;[001] +; [---] ;[002] + eor r0, x1 ;[003] + or phase, r0 ;[004] + eor x2, x1 ;[005] + in r0, USBIN ;[006] <-- phase + ser x3 ;[007] + bst x2, USBMINUS ;[008] + bld shift, 0 ;[009] + andi shift, 0xf9 ;[010] +rxbit1: ;[ ] + in x2, USBIN ;[011] <-- bit 1 + breq unstuff0 ;[012] *** unstuff escape + andi x2, USBMASK ;[013] SE0 check for bit 1 +didUnstuff0: ;[ ] Z only set if we detected SE0 in bitstuff + breq se0 ;[014] + eor r0, x2 ;[015] + or phase, r0 ;[016] + in r0, USBIN ;[017] <-- phase + eor x1, x2 ;[018] + bst x1, USBMINUS ;[019] + bld shift, 1 ;[020] + andi shift, 0xf3 ;[021] +didUnstuff1: ;[ ] + in x1, USBIN ;[022] <-- bit 2 + breq unstuff1 ;[023] *** unstuff escape + eor r0, x1 ;[024] + or phase, r0 ;[025] + subi cnt, 1 ;[026] overflow check + brcs overflow ;[027] + in r0, USBIN ;[028] <-- phase + eor x2, x1 ;[029] + bst x2, USBMINUS ;[030] + bld shift, 2 ;[031] + andi shift, 0xe7 ;[032] +didUnstuff2: ;[ ] + in x2, USBIN ;[033] <-- bit 3 + breq unstuff2 ;[034] *** unstuff escape + eor r0, x2 ;[035] + or phase, r0 ;[036] + eor x1, x2 ;[037] + bst x1, USBMINUS ;[038] + in r0, USBIN ;[039] <-- phase + bld shift, 3 ;[040] + andi shift, 0xcf ;[041] +didUnstuff3: ;[ ] + breq unstuff3 ;[042] *** unstuff escape + nop ;[043] + in x1, USBIN ;[044] <-- bit 4 + eor x2, x1 ;[045] + bst x2, USBMINUS ;[046] + bld shift, 4 ;[047] +didUnstuff4: ;[ ] + eor r0, x1 ;[048] + or phase, r0 ;[049] + in r0, USBIN ;[050] <-- phase + andi shift, 0x9f ;[051] + breq unstuff4 ;[052] *** unstuff escape + rjmp continueWithBit5;[053] +; [---] ;[054] + +macro POP_STANDARD ; 16 cycles + pop cnt + pop x4 + pop x3 + pop x2 + pop x1 + pop shift + pop YH + pop r0 + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies + +bitstuff7: + eor x1, x4 ;[4] + ldi x2, 0 ;[5] + nop2 ;[6] C is zero (brcc) + rjmp didStuff7 ;[8] + +bitstuffN: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] + lpm ;[7] 3 cycle NOP, modifies r0 + out USBOUT, x1 ;[10] <-- out + rjmp didStuffN ;[0] + +#define bitStatus x3 + +sendNakAndReti: + ldi cnt, USBPID_NAK ;[-19] + rjmp sendCntAndReti ;[-18] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov r0, cnt ;[-16] + ldi YL, 0 ;[-15] R0 address is 0 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-7] <- acquire bus +; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-6] exor mask + ldi shift, 0x80 ;[-5] sync byte is first byte sent + ldi bitStatus, 0xff ;[-4] init bit loop counter, works for up to 12 bytes +byteloop: +bitloop: + sbrs shift, 0 ;[8] [-3] + eor x1, x4 ;[9] [-2] + out USBOUT, x1 ;[10] [-1] <-- out + ror shift ;[0] + ror x2 ;[1] +didStuffN: + cpi x2, 0xfc ;[2] + brcc bitstuffN ;[3] + nop ;[4] + subi bitStatus, 37 ;[5] 256 / 7 ~=~ 37 + brcc bitloop ;[6] when we leave the loop, bitStatus has almost the initial value + sbrs shift, 0 ;[7] + eor x1, x4 ;[8] + ror shift ;[9] +didStuff7: + out USBOUT, x1 ;[10] <-- out + ror x2 ;[0] + cpi x2, 0xfc ;[1] + brcc bitstuff7 ;[2] + ld shift, y+ ;[3] + dec cnt ;[5] + brne byteloop ;[6] +;make SE0: + cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles] + lds x2, usbNewDeviceAddr;[8] + lsl x2 ;[10] we compare with left shifted address + out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + subi YL, 2 ;[0] Only assign address on data packets, not ACK/NAK in r0 + sbci YH, 0 ;[1] + breq skipAddrAssign ;[2] + sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 12 cycles per bit +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts +;register use in receive loop to receive the data bytes: +; shift assembles the byte currently being received +; x1 holds the D+ and D- line state +; x2 holds the previous line state +; cnt holds the number of bytes left in the receive buffer +; x3 holds the higher crc byte (see algorithm below) +; x4 is used as temporary register for the crc algorithm +; x5 is used for unstuffing: when unstuffing the last received bit is inverted in shift (to prevent further +; unstuffing calls. In the same time the corresponding bit in x5 is cleared to mark the bit as beening iverted +; zl lower crc value and crc table index +; zh used for crc table accesses + +;-------------------------------------------------------------------------------------------------------------- +; CRC mods: +; table driven crc checker, Z points to table in prog space +; ZL is the lower crc byte, x3 is the higher crc byte +; x4 is used as temp register to store different results +; the initialization of the crc register is not 0xFFFF but 0xFE54. This is because during the receipt of the +; first data byte an virtual zero data byte is added to the crc register, this results in the correct initial +; value of 0xFFFF at beginning of the second data byte before the first data byte is added to the crc. +; The magic number 0xFE54 results form the crc table: At tabH[0x54] = 0xFF = crcH (required) and +; tabL[0x54] = 0x01 -> crcL = 0x01 xor 0xFE = 0xFF +; bitcnt is renamed to x5 and is used for unstuffing purposes, the unstuffing works like in the 12MHz version +;-------------------------------------------------------------------------------------------------------------- +; CRC algorithm: +; The crc register is formed by x3 (higher byte) and ZL (lower byte). The algorithm uses a 'reversed' form +; i.e. that it takes the least significant bit first and shifts to the right. So in fact the highest order +; bit seen from the polynomial devision point of view is the lsb of ZL. (If this sounds strange to you i +; propose a research on CRC :-) ) +; Each data byte received is xored to ZL, the lower crc byte. This byte now builds the crc +; table index. Next the new high byte is loaded from the table and stored in x4 until we have space in x3 +; (its destination). +; Afterwards the lower table is loaded from the table and stored in ZL (the old index is overwritten as +; we don't need it anymore. In fact this is a right shift by 8 bits.) Now the old crc high value is xored +; to ZL, this is the second shift of the old crc value. Now x4 (the temp reg) is moved to x3 and the crc +; calculation is done. +; Prior to the first byte the two CRC register have to be initialized to 0xFFFF (as defined in usb spec) +; however the crc engine also runs during the receipt of the first byte, therefore x3 and zl are initialized +; to a magic number which results in a crc value of 0xFFFF after the first complete byte. +; +; This algorithm is split into the extra cycles of the different bits: +; bit7: XOR the received byte to ZL +; bit5: load the new high byte to x4 +; bit6: load the lower xor byte from the table, xor zl and x3, store result in zl (=the new crc low value) +; move x4 (the new high byte) to x3, the crc value is ready +; + + +macro POP_STANDARD ; 18 cycles + pop ZH + pop ZL + pop cnt + pop x5 + pop x3 + pop x2 + pop x1 + pop shift + pop x4 + endm +macro POP_RETI ; 7 cycles + pop YH + pop YL + out SREG, YL + pop YL + endm + +macro CRC_CLEANUP_AND_CHECK + ; the last byte has already been xored with the lower crc byte, we have to do the table lookup and xor + ; x3 is the higher crc byte, zl the lower one + ldi ZH, hi8(usbCrcTableHigh);[+1] get the new high byte from the table + lpm x2, Z ;[+2][+3][+4] + ldi ZH, hi8(usbCrcTableLow);[+5] get the new low xor byte from the table + lpm ZL, Z ;[+6][+7][+8] + eor ZL, x3 ;[+7] xor the old high byte with the value from the table, x2:ZL now holds the crc value + cpi ZL, 0x01 ;[+8] if the crc is ok we have a fixed remainder value of 0xb001 in x2:ZL (see usb spec) + brne ignorePacket ;[+9] detected a crc fault -> paket is ignored and retransmitted by the host + cpi x2, 0xb0 ;[+10] + brne ignorePacket ;[+11] detected a crc fault -> paket is ignored and retransmitted by the host + endm + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG, YH, [sofError], x4, shift, x1, x2, x3, x5, cnt, ZL, ZH + push YL ;[-28] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-26] + push YL ;[-25] + push YH ;[-23] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-17] + rjmp foundK ;[-16] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-15] +;{3, 5} after falling D- edge, average delay: 4 cycles +;bit0 should be at 30 (2.5 bits) for center sampling. Currently at 4 so 26 cylces till bit 0 sample +;use 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push x4 ;[-14] +; [---] ;[-13] + lds YL, usbInputBufOffset;[-12] used to toggle the two usb receive buffers +; [---] ;[-11] + clr YH ;[-10] + subi YL, lo8(-(usbRxBuf));[-9] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-8] [rx loop init] + push shift ;[-7] +; [---] ;[-6] + ldi shift, 0x80 ;[-5] the last bit is the end of byte marker for the pid receiver loop + clc ;[-4] the carry has to be clear for receipt of pid bit 0 + sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) + rjmp haveTwoBitsK ;[-2] + pop shift ;[-1] undo the push from before + pop x4 ;[1] + rjmp waitForK ;[3] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 24 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[0] + push x2 ;[2] + push x3 ;[4] crc high byte + ldi x2, 1< jump back and store the byte + ori shift, 0x01 ;[11] invert the last received bit to prevent furhter unstuffing + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + andi x5, 0xFE ;[1] mark this bit as inverted (will be corrected before storing shift) + eor x1, x2 ;[2] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[3] mask the interesting bits + breq stuffErr ;[4] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[5] the next bit expects the last state to be in x1 + rjmp didunstuff0 ;[6] + ;[7] jump delay of rjmp didunstuffX + +unstuff1: ;[11] this is the jump delay of breq unstuffX + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + ori shift, 0x02 ;[1] invert the last received bit to prevent furhter unstuffing + andi x5, 0xFD ;[2] mark this bit as inverted (will be corrected before storing shift) + eor x2, x1 ;[3] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[4] mask the interesting bits + breq stuffErr ;[5] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[6] the next bit expects the last state to be in x2 + nop2 ;[7] + ;[8] + rjmp didunstuff1 ;[9] + ;[10] jump delay of rjmp didunstuffX + +unstuff2: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x04 ;[10] invert the last received bit to prevent furhter unstuffing + andi x5, 0xFB ;[11] mark this bit as inverted (will be corrected before storing shift) + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[4] the next bit expects the last state to be in x1 + nop2 ;[5] + ;[6] + rjmp didunstuff2 ;[7] + ;[8] jump delay of rjmp didunstuffX + +unstuff3: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x08 ;[10] invert the last received bit to prevent furhter unstuffing + andi x5, 0xF7 ;[11] mark this bit as inverted (will be corrected before storing shift) + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[4] the next bit expects the last state to be in x2 + nop2 ;[5] + ;[6] + rjmp didunstuff3 ;[7] + ;[8] jump delay of rjmp didunstuffX + + + +; the include has to be here due to branch distance restirctions +#define __USE_CRC__ +#include "asmcommon.inc" + + + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies +; 7.5 bit times is 90 cycles. ...there is plenty of time + + +sendNakAndReti: + ldi x3, USBPID_NAK ;[-18] + rjmp sendX3AndReti ;[-17] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov x3, cnt ;[-16] +sendX3AndReti: + ldi YL, 20 ;[-15] x3==r20 address is 20 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent + +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-6] <- acquire bus + ldi x2, 0 ;[-6] init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-5] exor mask + ldi shift, 0x80 ;[-4] sync byte is first byte sent +txByteLoop: + ldi bitcnt, 0x40 ;[-3]=[9] binary 01000000 +txBitLoop: ; the loop sends the first 7 bits of the byte + sbrs shift, 0 ;[-2]=[10] if we have to send a 1 don't change the line state + eor x1, x4 ;[-1]=[11] + out USBOUT, x1 ;[0] + ror shift ;[1] + ror x2 ;[2] transfers the last sent bit to the stuffing history +didStuffN: + nop ;[3] + nop ;[4] + cpi x2, 0xfc ;[5] if we sent six consecutive ones + brcc bitstuffN ;[6] + lsr bitcnt ;[7] + brne txBitLoop ;[8] restart the loop while the 1 is still in the bitcount + +; transmit bit 7 + sbrs shift, 0 ;[9] + eor x1, x4 ;[10] +didStuff7: + ror shift ;[11] + out USBOUT, x1 ;[0] transfer bit 7 to the pins + ror x2 ;[1] move the bit into the stuffing history + cpi x2, 0xfc ;[2] + brcc bitstuff7 ;[3] + ld shift, y+ ;[4] get next byte to transmit + dec cnt ;[5] decrement byte counter + brne txByteLoop ;[7] if we have more bytes start next one + ;[8] branch delay + +;make SE0: + cbr x1, USBMASK ;[8] prepare SE0 [spec says EOP may be 25 to 30 cycles] + lds x2, usbNewDeviceAddr;[9] + lsl x2 ;[11] we compare with left shifted address + out USBOUT, x1 ;[0] <-- out SE0 -- from now 2 bits = 24 cycles until bus idle + subi YL, 20 + 2 ;[1] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[2] +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[3] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< +int main (int argc, char **argv) +{ + int i, j; + for (i=0; i<512; i++){ + unsigned short crc = i & 0xff; + for(j=0; j<8; j++) crc = (crc >> 1) ^ ((crc & 1) ? 0xa001 : 0); + if((i & 7) == 0) printf("\n.byte "); + printf("0x%02x, ", (i > 0xff ? (crc >> 8) : crc) & 0xff); + if(i == 255) printf("\n"); + } + return 0; +} + +// Use the following algorithm to compute CRC values: +ushort computeCrc(uchar *msg, uchar msgLen) +{ + uchar i; + ushort crc = 0xffff; + for(i = 0; i < msgLen; i++) + crc = usbCrcTable16[lo8(crc) ^ msg[i]] ^ hi8(crc); + return crc; +} +*/ + +.balign 256 +usbCrcTableLow: +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 + +; .balign 256 +usbCrcTableHigh: +.byte 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2 +.byte 0xC6, 0x06, 0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04 +.byte 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E +.byte 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8 +.byte 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A +.byte 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC +.byte 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6 +.byte 0xD2, 0x12, 0x13, 0xD3, 0x11, 0xD1, 0xD0, 0x10 +.byte 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32 +.byte 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4 +.byte 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE +.byte 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38 +.byte 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA +.byte 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C +.byte 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26 +.byte 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0 +.byte 0xA0, 0x60, 0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62 +.byte 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4 +.byte 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE +.byte 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68 +.byte 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA +.byte 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C +.byte 0xB4, 0x74, 0x75, 0xB5, 0x77, 0xB7, 0xB6, 0x76 +.byte 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0 +.byte 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92 +.byte 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54 +.byte 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E +.byte 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98 +.byte 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A +.byte 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C +.byte 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86 +.byte 0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 0x40 + diff --git a/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm20.inc b/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm20.inc new file mode 100644 index 0000000..303abaf --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiCDC/usbdrvasm20.inc @@ -0,0 +1,360 @@ +/* Name: usbdrvasm20.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Jeroen Benschop + * Based on usbdrvasm16.inc from Christian Starkjohann + * Creation Date: 2008-03-05 + * Tabsize: 4 + * Copyright: (c) 2008 by Jeroen Benschop and OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm20.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 20 MHz version of the asssembler part of the USB driver. It +requires a 20 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! +*/ + +#define leap2 x3 +#ifdef __IAR_SYSTEMS_ASM__ +#define nextInst $+2 +#else +#define nextInst .+0 +#endif + +;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 20 MHz -> 13.333333 cycles per bit, 106.666667 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts +;register use in receive loop: +; shift assembles the byte currently being received +; x1 holds the D+ and D- line state +; x2 holds the previous line state +; x4 (leap) is used to add a leap cycle once every three bytes received +; X3 (leap2) is used to add a leap cycle once every three stuff bits received +; bitcnt is used to determine when a stuff bit is due +; cnt holds the number of bytes left in the receive buffer + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt + push YL ;[-28] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-26] + push YL ;[-25] + push YH ;[-23] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-19] + rjmp foundK ;[-18] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-16] +;{3, 5} after falling D- edge, average delay: 4 cycles +;bit0 should be at 34 for center sampling. Currently at 4 so 30 cylces till bit 0 sample +;use 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push bitcnt ;[-16] +; [---] ;[-15] + lds YL, usbInputBufOffset;[-14] +; [---] ;[-13] + clr YH ;[-12] + subi YL, lo8(-(usbRxBuf));[-11] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-10] [rx loop init] + push shift ;[-9] +; [---] ;[-8] + ldi shift,0x40 ;[-7] set msb to "1" so processing bit7 can be detected + nop2 ;[-6] +; [---] ;[-5] + ldi bitcnt, 5 ;[-4] [rx loop init] + sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) + rjmp haveTwoBitsK ;[-2] + pop shift ;[-1] undo the push from before + pop bitcnt ;[1] + rjmp waitForK ;[3] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 27 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[0] + push x2 ;[2] + push x3 ;[4] (leap2) + ldi leap2, 0x55 ;[6] add leap cycle on 2nd,5th,8th,... stuff bit + push x4 ;[7] == leap + ldi leap, 0x55 ;[9] skip leap cycle on 2nd,5th,8th,... byte received + push cnt ;[10] + ldi cnt, USB_BUFSIZE ;[12] [rx loop init] + ldi x2, 1< +#ifndef __IAR_SYSTEMS_ASM__ +# include +#endif + +#define __attribute__(arg) /* not supported on IAR */ + +#ifdef __IAR_SYSTEMS_ASM__ +# define __ASSEMBLER__ /* IAR does not define standard macro for asm */ +#endif + +#ifdef __HAS_ELPM__ +# define const PROGMEM __farflash +#else +# define const PROGMEM __flash +#endif + +#define USB_READ_FLASH(addr) (*(const PROGMEM char *)(addr)) + +/* The following definitions are not needed by the driver, but may be of some + * help if you port a gcc based project to IAR. + */ +#define cli() __disable_interrupt() +#define sei() __enable_interrupt() +#define wdt_reset() __watchdog_reset() +#define _BV(x) (1 << (x)) + +/* assembler compatibility macros */ +#define nop2 rjmp $+2 /* jump to next instruction */ +#define XL r26 +#define XH r27 +#define YL r28 +#define YH r29 +#define ZL r30 +#define ZH r31 +#define lo8(x) LOW(x) +#define hi8(x) (((x)>>8) & 0xff) /* not HIGH to allow XLINK to make a proper range check */ + +/* Depending on the device you use, you may get problems with the way usbdrv.h + * handles the differences between devices. Since IAR does not use #defines + * for MCU registers, we can't check for the existence of a particular + * register with an #ifdef. If the autodetection mechanism fails, include + * definitions for the required USB_INTR_* macros in your usbconfig.h. See + * usbconfig-prototype.h and usbdrv.h for details. + */ + +/* ------------------------------------------------------------------------- */ +#elif __CODEVISIONAVR__ /* check for CodeVision AVR */ +/* ------------------------------------------------------------------------- */ +/* This port is not working (yet) */ + +/* #define F_CPU _MCU_CLOCK_FREQUENCY_ seems to be defined automatically */ + +#include +#include + +#define __attribute__(arg) /* not supported on IAR */ + +#define const PROGMEM __flash +#define USB_READ_FLASH(addr) (*(const PROGMEM char *)(addr)) + +#ifndef __ASSEMBLER__ +static inline void cli(void) +{ + #asm("cli"); +} +static inline void sei(void) +{ + #asm("sei"); +} +#endif +#define _delay_ms(t) delay_ms(t) +#define _BV(x) (1 << (x)) +#define USB_CFG_USE_SWITCH_STATEMENT 1 /* macro for if() cascase fails for unknown reason */ + +#define macro .macro +#define endm .endmacro +#define nop2 rjmp .+0 /* jump to next instruction */ + +/* ------------------------------------------------------------------------- */ +#else /* default development environment is avr-gcc/avr-libc */ +/* ------------------------------------------------------------------------- */ + +#include +#ifdef __ASSEMBLER__ +# define _VECTOR(N) __vector_ ## N /* io.h does not define this for asm */ +#else +# include +#endif + +#if USB_CFG_DRIVER_FLASH_PAGE +# define USB_READ_FLASH(addr) pgm_read_byte_far(((long)USB_CFG_DRIVER_FLASH_PAGE << 16) | (long)(addr)) +#else +# define USB_READ_FLASH(addr) pgm_read_byte(addr) +#endif + +#define macro .macro +#define endm .endm +#define nop2 rjmp .+0 /* jump to next instruction */ + +#endif /* development environment */ + +/* for conveniecne, ensure that PRG_RDB exists */ +#ifndef PRG_RDB +# define PRG_RDB(addr) USB_READ_FLASH(addr) +#endif +#endif /* __usbportability_h_INCLUDED__ */ diff --git a/hardware/digistump/avr/libraries/DigiJoystick/ArduinoNotes.txt b/hardware/digistump/avr/libraries/DigiJoystick/ArduinoNotes.txt new file mode 100644 index 0000000..e05398b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/ArduinoNotes.txt @@ -0,0 +1,34 @@ +Notes On Integrating AVRUSB with Arduino +======================================== + +* Note the license(s) under which AVRUSB is distributed. + +* See also: http://code.rancidbacon.com/ProjectLogArduinoUSB + +* Note: The pins we use on the PCB (not protoboard) hardware shield are: + + INT0 == PD2 == IC Pin 4 == Arduino Digital Pin 2 == D+ + + ---- == PD4 == -------- == Arduino Digital Pin 4 == D- + + ---- == PD5 == -------- == Arduino Digital Pin 5 == pull-up + + (DONE: Change to not use PD3 so INT1 is left free?) + +* In order to compile a valid 'usbconfig.h' file must exit. The content of this + file will vary depending on whether the device is a generic USB device, + generic HID device or specific class of HID device for example. + + The file 'usbconfig-prototype.h' can be used as a starting point, however + it might be easier to use the 'usbconfig.h' from one of the example projects. + + TODO: Specify the settings that need to be changed to match the shield + design we use. + +* (NOTE: Initial 'usbconfig.h' used will be based on the file from + 'HIDKeys.2007-03-29'.) (Note: Have now upgraded to V-USB 2009-08-22.) + +* Versions of the Arduino IDE prior to 0018 won't compile our library + so it needs to be pre-compiled with: + + avr-g++ -Wall -Os -I. -DF_CPU=16000000 -mmcu=atmega168 -c usbdrvasm.S -c usbdrv.c diff --git a/hardware/digistump/avr/libraries/DigiJoystick/Changelog.txt b/hardware/digistump/avr/libraries/DigiJoystick/Changelog.txt new file mode 100644 index 0000000..655a9d4 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/Changelog.txt @@ -0,0 +1,296 @@ +This file documents changes in the firmware-only USB driver for atmel's AVR +microcontrollers. New entries are always appended to the end of the file. +Scroll down to the bottom to see the most recent changes. + +2005-04-01: + - Implemented endpoint 1 as interrupt-in endpoint. + - Moved all configuration options to usbconfig.h which is not part of the + driver. + - Changed interface for usbVendorSetup(). + - Fixed compatibility with ATMega8 device. + - Various minor optimizations. + +2005-04-11: + - Changed interface to application: Use usbFunctionSetup(), usbFunctionRead() + and usbFunctionWrite() now. Added configuration options to choose which + of these functions to compile in. + - Assembler module delivers receive data non-inverted now. + - Made register and bit names compatible with more AVR devices. + +2005-05-03: + - Allow address of usbRxBuf on any memory page as long as the buffer does + not cross 256 byte page boundaries. + - Better device compatibility: works with Mega88 now. + - Code optimization in debugging module. + - Documentation updates. + +2006-01-02: + - Added (free) default Vendor- and Product-IDs bought from voti.nl. + - Added USBID-License.txt file which defines the rules for using the free + shared VID/PID pair. + - Added Readme.txt to the usbdrv directory which clarifies administrative + issues. + +2006-01-25: + - Added "configured state" to become more standards compliant. + - Added "HALT" state for interrupt endpoint. + - Driver passes the "USB Command Verifier" test from usb.org now. + - Made "serial number" a configuration option. + - Minor optimizations, we now recommend compiler option "-Os" for best + results. + - Added a version number to usbdrv.h + +2006-02-03: + - New configuration variable USB_BUFFER_SECTION for the memory section where + the USB rx buffer will go. This defaults to ".bss" if not defined. Since + this buffer MUST NOT cross 256 byte pages (not even touch a page at the + end), the user may want to pass a linker option similar to + "-Wl,--section-start=.mybuffer=0x800060". + - Provide structure for usbRequest_t. + - New defines for USB constants. + - Prepared for HID implementations. + - Increased data size limit for interrupt transfers to 8 bytes. + - New macro usbInterruptIsReady() to query interrupt buffer state. + +2006-02-18: + - Ensure that the data token which is sent as an ack to an OUT transfer is + always zero sized. This fixes a bug where the host reports an error after + sending an out transfer to the device, although all data arrived at the + device. + - Updated docs in usbdrv.h to reflect changed API in usbFunctionWrite(). + +* Release 2006-02-20 + + - Give a compiler warning when compiling with debugging turned on. + - Added Oleg Semyonov's changes for IAR-cc compatibility. + - Added new (optional) functions usbDeviceConnect() and usbDeviceDisconnect() + (also thanks to Oleg!). + - Rearranged tests in usbPoll() to save a couple of instructions in the most + likely case that no actions are pending. + - We need a delay between the SET ADDRESS request until the new address + becomes active. This delay was handled in usbPoll() until now. Since the + spec says that the delay must not exceed 2ms, previous versions required + aggressive polling during the enumeration phase. We have now moved the + handling of the delay into the interrupt routine. + - We must not reply with NAK to a SETUP transaction. We can only achieve this + by making sure that the rx buffer is empty when SETUP tokens are expected. + We therefore don't pass zero sized data packets from the status phase of + a transfer to usbPoll(). This change MAY cause troubles if you rely on + receiving a less than 8 bytes long packet in usbFunctionWrite() to + identify the end of a transfer. usbFunctionWrite() will NEVER be called + with a zero length. + +* Release 2006-03-14 + + - Improved IAR C support: tiny memory model, more devices + - Added template usbconfig.h file under the name usbconfig-prototype.h + +* Release 2006-03-26 + + - Added provision for one more interrupt-in endpoint (endpoint 3). + - Added provision for one interrupt-out endpoint (endpoint 1). + - Added flowcontrol macros for USB. + - Added provision for custom configuration descriptor. + - Allow ANY two port bits for D+ and D-. + - Merged (optional) receive endpoint number into global usbRxToken variable. + - Use USB_CFG_IOPORTNAME instead of USB_CFG_IOPORT. We now construct the + variable name from the single port letter instead of computing the address + of related ports from the output-port address. + +* Release 2006-06-26 + + - Updated documentation in usbdrv.h and usbconfig-prototype.h to reflect the + new features. + - Removed "#warning" directives because IAR does not understand them. Use + unused static variables instead to generate a warning. + - Do not include when compiling with IAR. + - Introduced USB_CFG_DESCR_PROPS_* in usbconfig.h to configure how each + USB descriptor should be handled. It is now possible to provide descriptor + data in Flash, RAM or dynamically at runtime. + - STALL is now a status in usbTxLen* instead of a message. We can now conform + to the spec and leave the stall status pending until it is cleared. + - Made usbTxPacketCnt1 and usbTxPacketCnt3 public. This allows the + application code to reset data toggling on interrupt pipes. + +* Release 2006-07-18 + + - Added an #if !defined __ASSEMBLER__ to the warning in usbdrv.h. This fixes + an assembler error. + - usbDeviceDisconnect() takes pull-up resistor to high impedance now. + +* Release 2007-02-01 + + - Merged in some code size improvements from usbtiny (thanks to Dick + Streefland for these optimizations!) + - Special alignment requirement for usbRxBuf not required any more. Thanks + again to Dick Streefland for this hint! + - Reverted to "#warning" instead of unused static variables -- new versions + of IAR CC should handle this directive. + - Changed Open Source license to GNU GPL v2 in order to make linking against + other free libraries easier. We no longer require publication of the + circuit diagrams, but we STRONGLY encourage it. If you improve the driver + itself, PLEASE grant us a royalty free license to your changes for our + commercial license. + +* Release 2007-03-29 + + - New configuration option "USB_PUBLIC" in usbconfig.h. + - Set USB version number to 1.10 instead of 1.01. + - Code used USB_CFG_DESCR_PROPS_STRING_DEVICE and + USB_CFG_DESCR_PROPS_STRING_PRODUCT inconsistently. Changed all occurrences + to USB_CFG_DESCR_PROPS_STRING_PRODUCT. + - New assembler module for 16.5 MHz RC oscillator clock with PLL in receiver + code. + - New assembler module for 16 MHz crystal. + - usbdrvasm.S contains common code only, clock-specific parts have been moved + to usbdrvasm12.S, usbdrvasm16.S and usbdrvasm165.S respectively. + +* Release 2007-06-25 + + - 16 MHz module: Do SE0 check in stuffed bits as well. + +* Release 2007-07-07 + + - Define hi8(x) for IAR compiler to limit result to 8 bits. This is necessary + for negative values. + - Added 15 MHz module contributed by V. Bosch. + - Interrupt vector name can now be configured. This is useful if somebody + wants to use a different hardware interrupt than INT0. + +* Release 2007-08-07 + + - Moved handleIn3 routine in usbdrvasm16.S so that relative jump range is + not exceeded. + - More config options: USB_RX_USER_HOOK(), USB_INITIAL_DATATOKEN, + USB_COUNT_SOF + - USB_INTR_PENDING can now be a memory address, not just I/O + +* Release 2007-09-19 + + - Split out common parts of assembler modules into separate include file + - Made endpoint numbers configurable so that given interface definitions + can be matched. See USB_CFG_EP3_NUMBER in usbconfig-prototype.h. + - Store endpoint number for interrupt/bulk-out so that usbFunctionWriteOut() + can handle any number of endpoints. + - Define usbDeviceConnect() and usbDeviceDisconnect() even if no + USB_CFG_PULLUP_IOPORTNAME is defined. Directly set D+ and D- to 0 in this + case. + +* Release 2007-12-01 + + - Optimize usbDeviceConnect() and usbDeviceDisconnect() for less code size + when USB_CFG_PULLUP_IOPORTNAME is not defined. + +* Release 2007-12-13 + + - Renamed all include-only assembler modules from *.S to *.inc so that + people don't add them to their project sources. + - Distribute leap bits in tx loop more evenly for 16 MHz module. + - Use "macro" and "endm" instead of ".macro" and ".endm" for IAR + - Avoid compiler warnings for constant expr range by casting some values in + USB descriptors. + +* Release 2008-01-21 + + - Fixed bug in 15 and 16 MHz module where the new address set with + SET_ADDRESS was already accepted at the next NAK or ACK we send, not at + the next data packet we send. This caused problems when the host polled + too fast. Thanks to Alexander Neumann for his help and patience debugging + this issue! + +* Release 2008-02-05 + + - Fixed bug in 16.5 MHz module where a register was used in the interrupt + handler before it was pushed. This bug was introduced with version + 2007-09-19 when common parts were moved to a separate file. + - Optimized CRC routine (thanks to Reimar Doeffinger). + +* Release 2008-02-16 + + - Removed outdated IAR compatibility stuff (code sections). + - Added hook macros for USB_RESET_HOOK() and USB_SET_ADDRESS_HOOK(). + - Added optional routine usbMeasureFrameLength() for calibration of the + internal RC oscillator. + +* Release 2008-02-28 + + - USB_INITIAL_DATATOKEN defaults to USBPID_DATA1 now, which means that we + start with sending USBPID_DATA0. + - Changed defaults in usbconfig-prototype.h + - Added free USB VID/PID pair for MIDI class devices + - Restructured AVR-USB as separate package, not part of PowerSwitch any more. + +* Release 2008-04-18 + + - Restructured usbdrv.c so that it is easier to read and understand. + - Better code optimization with gcc 4. + - If a second interrupt in endpoint is enabled, also add it to config + descriptor. + - Added config option for long transfers (above 254 bytes), see + USB_CFG_LONG_TRANSFERS in usbconfig.h. + - Added 20 MHz module contributed by Jeroen Benschop. + +* Release 2008-05-13 + + - Fixed bug in libs-host/hiddata.c function usbhidGetReport(): length + was not incremented, pointer to length was incremented instead. + - Added code to command line tool(s) which claims an interface. This code + is disabled by default, but may be necessary on newer Linux kernels. + - Added usbconfig.h option "USB_CFG_CHECK_DATA_TOGGLING". + - New header "usbportability.h" prepares ports to other development + environments. + - Long transfers (above 254 bytes) did not work when usbFunctionRead() was + used to supply the data. Fixed this bug. [Thanks to Alexander Neumann!] + - In hiddata.c (example code for sending/receiving data over HID), use + USB_RECIP_DEVICE instead of USB_RECIP_INTERFACE for control transfers so + that we need not claim the interface. + - in usbPoll() loop 20 times polling for RESET state instead of 10 times. + This accounts for the higher clock rates we now support. + - Added a module for 12.8 MHz RC oscillator with PLL in receiver loop. + - Added hook to SOF code so that oscillator can be tuned to USB frame clock. + - Added timeout to waitForJ loop. Helps preventing unexpected hangs. + - Added example code for oscillator tuning to libs-device (thanks to + Henrik Haftmann for the idea to this routine). + - Implemented option USB_CFG_SUPPRESS_INTR_CODE. + +* Release 2008-10-22 + + - Fixed libs-device/osctune.h: OSCCAL is memory address on ATMega88 and + similar, not offset of 0x20 needs to be added. + - Allow distribution under GPLv3 for those who have to link against other + code distributed under GPLv3. + +* Release 2008-11-26 + + - Removed libusb-win32 dependency for hid-data example in Makefile.windows. + It was never required and confused many people. + - Added extern uchar usbRxToken to usbdrv.h. + - Integrated a module with CRC checks at 18 MHz by Lukas Schrittwieser. + +* Release 2009-03-23 + + - Hid-mouse example used settings from hid-data example, fixed that. + - Renamed project to V-USB due to a trademark issue with Atmel(r). + - Changed CommercialLicense.txt and USBID-License.txt to make the + background of USB ID registration clearer. + +* Release 2009-04-15 + + - Changed CommercialLicense.txt to reflect the new range of PIDs from + Jason Kotzin. + - Removed USBID-License.txt in favor of USB-IDs-for-free.txt and + USB-ID-FAQ.txt + - Fixed a bug in the 12.8 MHz module: End Of Packet decection was made in + the center between bit 0 and 1 of each byte. This is where the data lines + are expected to change and the sampled data may therefore be nonsense. + We therefore check EOP ONLY if bits 0 AND 1 have both been read as 0 on D-. + - Fixed a bitstuffing problem in the 16 MHz module: If bit 6 was stuffed, + the unstuffing code in the receiver routine was 1 cycle too long. If + multiple bytes had the unstuffing in bit 6, the error summed up until the + receiver was out of sync. + - Included option for faster CRC routine. + Thanks to Slawomir Fras (BoskiDialer) for this code! + - Updated bits in Configuration Descriptor's bmAttributes according to + USB 1.1 (in particular bit 7, it is a must-be-set bit now). + +* Release 2009-08-22 diff --git a/hardware/digistump/avr/libraries/DigiJoystick/CommercialLicense.txt b/hardware/digistump/avr/libraries/DigiJoystick/CommercialLicense.txt new file mode 100644 index 0000000..11d07d9 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/CommercialLicense.txt @@ -0,0 +1,166 @@ +V-USB Driver Software License Agreement +Version 2009-08-03 + +THIS LICENSE AGREEMENT GRANTS YOU CERTAIN RIGHTS IN A SOFTWARE. YOU CAN +ENTER INTO THIS AGREEMENT AND ACQUIRE THE RIGHTS OUTLINED BELOW BY PAYING +THE AMOUNT ACCORDING TO SECTION 4 ("PAYMENT") TO OBJECTIVE DEVELOPMENT. + + +1 DEFINITIONS + +1.1 "OBJECTIVE DEVELOPMENT" shall mean OBJECTIVE DEVELOPMENT Software GmbH, +Grosse Schiffgasse 1A/7, 1020 Wien, AUSTRIA. + +1.2 "You" shall mean the Licensee. + +1.3 "V-USB" shall mean all files included in the package distributed under +the name "vusb" by OBJECTIVE DEVELOPMENT (http://www.obdev.at/vusb/) +unless otherwise noted. This includes the firmware-only USB device +implementation for Atmel AVR microcontrollers, some simple device examples +and host side software examples and libraries. + + +2 LICENSE GRANTS + +2.1 Source Code. OBJECTIVE DEVELOPMENT shall furnish you with the source +code of V-USB. + +2.2 Distribution and Use. OBJECTIVE DEVELOPMENT grants you the +non-exclusive right to use, copy and distribute V-USB with your hardware +product(s), restricted by the limitations in section 3 below. + +2.3 Modifications. OBJECTIVE DEVELOPMENT grants you the right to modify +the source code and your copy of V-USB according to your needs. + +2.4 USB IDs. OBJECTIVE DEVELOPMENT furnishes you with one or two USB +Product ID(s), sent to you in e-mail. These Product IDs are reserved +exclusively for you. OBJECTIVE DEVELOPMENT has obtained USB Product ID +ranges under the Vendor ID 5824 from Wouter van Ooijen (Van Ooijen +Technische Informatica, www.voti.nl) and under the Vendor ID 8352 from +Jason Kotzin (Clay Logic, www.claylogic.com). Both owners of the Vendor IDs +have obtained these IDs from the USB Implementers Forum, Inc. +(www.usb.org). OBJECTIVE DEVELOPMENT disclaims all liability which might +arise from the assignment of USB IDs. + +2.5 USB Certification. Although not part of this agreement, we want to make +it clear that you cannot become USB certified when you use V-USB or a USB +Product ID assigned by OBJECTIVE DEVELOPMENT. AVR microcontrollers don't +meet the electrical specifications required by the USB specification and +the USB Implementers Forum certifies only members who bought a Vendor ID of +their own. + + +3 LICENSE RESTRICTIONS + +3.1 Number of Units. Only one of the following three definitions is +applicable. Which one is determined by the amount you pay to OBJECTIVE +DEVELOPMENT, see section 4 ("Payment") below. + +Hobby License: You may use V-USB according to section 2 above in no more +than 5 hardware units. These units must not be sold for profit. + +Entry Level License: You may use V-USB according to section 2 above in no +more than 150 hardware units. + +Professional License: You may use V-USB according to section 2 above in +any number of hardware units, except for large scale production ("unlimited +fair use"). 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This document represents the entire agreement between +OBJECTIVE DEVELOPMENT and you. It may only be modified in writing signed by +an authorized representative of both, OBJECTIVE DEVELOPMENT and you. + +8.3 Severability. In case a provision of these terms and conditions should +be or become partly or entirely invalid, ineffective, or not executable, +the validity of all other provisions shall not be affected. + +8.4 Applicable Law. This agreement is governed by the laws of the Republic +of Austria. + +8.5 Responsible Courts. The responsible courts in Vienna/Austria will have +exclusive jurisdiction regarding all disputes in connection with this +agreement. + diff --git a/hardware/digistump/avr/libraries/DigiJoystick/DigiJoystick.h b/hardware/digistump/avr/libraries/DigiJoystick/DigiJoystick.h new file mode 100644 index 0000000..5f5d314 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/DigiJoystick.h @@ -0,0 +1,362 @@ +/* + * Based on Obdev's AVRUSB code and under the same license. + * + * TODO: Make a proper file header. :-) + * Modified for Digispark by Digistump + * And now modified by Sean Murphy (duckythescientist) from a keyboard device to a joystick device + * And now modified by Bluebie to have better code style, not ruin system timers, and have delay() function + * Most of the credit for the joystick code should go to Raphaël Assénat + */ +#ifndef __DigiJoystick_h__ +#define __DigiJoystick_h__ + +#define GCN64_REPORT_SIZE 8 + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "usbdrv.h" +//#include "devdesc.h" +#include "oddebug.h" +#include "usbconfig.h" + +static uchar *rt_usbHidReportDescriptor=NULL; +static uchar rt_usbHidReportDescriptorSize=0; +static uchar *rt_usbDeviceDescriptor=NULL; +static uchar rt_usbDeviceDescriptorSize=0; +byte buttonLowByte = 0; +byte buttonHighByte = 0; + +// TODO: Work around Arduino 12 issues better. +//#include +//#undef int() + +//typedef uint8_t byte; + +/* What was most recently read from the controller */ +unsigned char last_built_report[GCN64_REPORT_SIZE]; + +/* What was most recently sent to the host */ +unsigned char last_sent_report[GCN64_REPORT_SIZE]; + +uchar reportBuffer[8]; + +// report frequency set to default of 50hz +#define DIGIJOYSTICK_DEFAULT_REPORT_INTERVAL 20 +static unsigned char must_report = 0; +static unsigned char idle_rate = DIGIJOYSTICK_DEFAULT_REPORT_INTERVAL / 4; // in units of 4ms +// new minimum report frequency system: +static unsigned long last_report_time = 0; +char usb_hasCommed = 0; + +unsigned char gcn64_usbHidReportDescriptor[] PROGMEM = { + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x05, // USAGE (Gamepad) + 0xa1, 0x01, // COLLECTION (Application) + + 0x09, 0x01, // USAGE (Pointer) + 0xa1, 0x00, // COLLECTION (Physical) + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x30, // USAGE (X) + 0x09, 0x31, // USAGE (Y) + + 0x09, 0x33, // USAGE (Rx) + 0x09, 0x34, // USAGE (Ry) + + 0x09, 0x35, // USAGE (Rz) + 0x09, 0x36, // USAGE (Slider) + + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x26, 0xFF, 0x00, // LOGICAL_MAXIMUM (255) + 0x75, 0x08, // REPORT_SIZE (8) + 0x95, 0x06, // REPORT_COUNT (6) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0xc0, // END_COLLECTION (Physical) + + 0x05, 0x09, // USAGE_PAGE (Button) + 0x19, 0x01, // USAGE_MINIMUM (Button 1) + 0x29, 0x10, // USAGE_MAXIMUM (Button 14) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x75, 0x01, // REPORT_SIZE (1) + 0x95, 0x10, // REPORT_COUNT (16) + 0x81, 0x02, // INPUT (Data,Var,Abs) + + 0xc0 // END_COLLECTION (Application) +}; + +#define USBDESCR_DEVICE 1 + +unsigned char usbDescrDevice[] PROGMEM = { /* USB device descriptor */ + 18, /* sizeof(usbDescrDevice): length of descriptor in bytes */ + USBDESCR_DEVICE, /* descriptor type */ + 0x01, 0x01, /* USB version supported */ + USB_CFG_DEVICE_CLASS, + USB_CFG_DEVICE_SUBCLASS, + 0, /* protocol */ + 8, /* max packet size */ + USB_CFG_VENDOR_ID, /* 2 bytes */ + USB_CFG_DEVICE_ID, /* 2 bytes */ + USB_CFG_DEVICE_VERSION, /* 2 bytes */ +#if USB_CFG_VENDOR_NAME_LEN + 1, /* manufacturer string index */ +#else + 0, /* manufacturer string index */ +#endif +#if USB_CFG_DEVICE_NAME_LEN + 2, /* product string index */ +#else + 0, /* product string index */ +#endif +#if USB_CFG_SERIAL_NUMBER_LENGTH + 3, /* serial number string index */ +#else + 0, /* serial number string index */ +#endif + 1, /* number of configurations */ +}; + + + +void gamecubeBuildReport(unsigned char *reportBuf) { + if (reportBuf != NULL) { + memcpy(reportBuf, last_built_report, GCN64_REPORT_SIZE); + } + + memcpy(last_sent_report, last_built_report, GCN64_REPORT_SIZE); +} + +int getGamepadReport(unsigned char *dstbuf) { + gamecubeBuildReport(dstbuf); + return GCN64_REPORT_SIZE; +} + + + +class DigiJoystickDevice { + public: + DigiJoystickDevice () { + + } + + void begin(){ + + cli(); + PORTB &= ~(_BV(USB_CFG_DMINUS_BIT) | _BV(USB_CFG_DPLUS_BIT)); + usbDeviceDisconnect(); + _delay_ms(250); + usbDeviceConnect(); + + rt_usbHidReportDescriptor = gcn64_usbHidReportDescriptor; + rt_usbHidReportDescriptorSize = sizeof(gcn64_usbHidReportDescriptor); + rt_usbDeviceDescriptor = usbDescrDevice; + rt_usbDeviceDescriptorSize = sizeof(usbDescrDevice); + + usbInit(); + + sei(); + + last_report_time = millis(); + + + } + + char isConnected() + { + return usb_hasCommed; + } + + void refresh() { + update(); + } + + void poll() { + update(); + } + + void update() { + usbPoll(); + + // instead of above code, use millis arduino system to enforce minimum reporting frequency + unsigned long time_since_last_report = millis() - last_report_time; + if (time_since_last_report >= (idle_rate * 4 /* in units of 4ms - usb spec stuff */)) { + last_report_time += idle_rate * 4; + must_report = 1; + } + + // if the report has changed, try force an update anyway + if (memcmp(last_built_report, last_sent_report, GCN64_REPORT_SIZE)) { + must_report = 1; + } + + // if we want to send a report, signal the host computer to ask us for it with a usb 'interrupt' + if (must_report) { + if (usbInterruptIsReady()) { + must_report = 0; + + gamecubeBuildReport(reportBuffer); + usbSetInterrupt(reportBuffer, GCN64_REPORT_SIZE); + } + } + } + + // delay while updating until we are finished delaying + void delay(long milli) { + unsigned long last = millis(); + while (milli > 0) { + unsigned long now = millis(); + milli -= now - last; + last = now; + update(); + } + } + + void setX(byte value) { + last_built_report[0] = value; + } + + void setY(byte value) { + last_built_report[1] = value; + } + + void setXROT(byte value) { + last_built_report[2] = value; + } + + void setYROT(byte value) { + last_built_report[3] = value; + } + + void setZROT(byte value) { + last_built_report[4] = value; + } + + void setSLIDER(byte value) { + last_built_report[5] = value; + } + + void setX(char value) { + setX(*(reinterpret_cast(&value))); + } + + void setY(char value) { + setY(*(reinterpret_cast(&value))); + } + + void setXROT(char value) { + setXROT(*(reinterpret_cast(&value))); + } + + void setYROT(char value) { + setYROT(*(reinterpret_cast(&value))); + } + + void setZROT(char value) { + setZROT(*(reinterpret_cast(&value))); + } + void setSLIDER(char value) { + setSLIDER(*(reinterpret_cast(&value))); + } + + void setButton(unsigned char button, unsigned char state) { + if(button<8){ + bitWrite(buttonLowByte, button, state); + setButtons(buttonByte, (byte) 0); + } + else{ + button = button - 8; + bitWrite(buttonHighByte, button, state); + setButtons((byte) 0, buttonByte); + } + } + + void setButtons(unsigned char low, unsigned char high) { + last_built_report[6] = low; + last_built_report[7] = high; + } + + void setButtons(char low,char high) { + setButtons(*reinterpret_cast(&low),*reinterpret_cast(&high)); + } + + void setValues(unsigned char values[]) { + memcpy(last_built_report, values, GCN64_REPORT_SIZE); + } + + void setValues(char values[]) { + unsigned char *foo = reinterpret_cast(values);//preserves bit values in cast + memcpy(last_built_report, foo, GCN64_REPORT_SIZE); + } +}; + +// Create global singleton object for users to make use of +DigiJoystickDevice DigiJoystick = DigiJoystickDevice(); + + + + + +#ifdef __cplusplus +extern "C"{ +#endif + // USB_PUBLIC uchar usbFunctionSetup + + uchar usbFunctionSetup(uchar data[8]) { + usb_hasCommed = 1; + usbRequest_t *rq = (usbRequest_t *)data; + + usbMsgPtr = reportBuffer; + if ((rq->bmRequestType & USBRQ_TYPE_MASK) == USBRQ_TYPE_CLASS) { // class request type + if (rq->bRequest == USBRQ_HID_GET_REPORT){ // wValue: ReportType (highbyte), ReportID (lowbyte) + // we only have one report type, so don't look at wValue + //curGamepad->buildReport(reportBuffer); + //return curGamepad->report_size; + return GCN64_REPORT_SIZE; + } else if (rq->bRequest == USBRQ_HID_GET_IDLE) { + usbMsgPtr = &idle_rate; + return 1; + } else if (rq->bRequest == USBRQ_HID_SET_IDLE) { + idle_rate = rq->wValue.bytes[1]; + } + } else { + /* no vendor specific requests implemented */ + } + return 0; + } + + uchar usbFunctionDescriptor(struct usbRequest *rq) { + if ((rq->bmRequestType & USBRQ_TYPE_MASK) != USBRQ_TYPE_STANDARD) { + return 0; + } + + if (rq->bRequest == USBRQ_GET_DESCRIPTOR) { + // USB spec 9.4.3, high byte is descriptor type + switch (rq->wValue.bytes[1]) { + case USBDESCR_DEVICE: + usbMsgPtr = rt_usbDeviceDescriptor; + return rt_usbDeviceDescriptorSize; + break; + + case USBDESCR_HID_REPORT: + usbMsgPtr = rt_usbHidReportDescriptor; + return rt_usbHidReportDescriptorSize; + break; + + } + } + + return 0; + } + +#ifdef __cplusplus +} // extern "C" +#endif + + +#endif // __DigiKeyboard_h__ diff --git a/hardware/digistump/avr/libraries/DigiJoystick/DigiKeyboard.h.old b/hardware/digistump/avr/libraries/DigiJoystick/DigiKeyboard.h.old new file mode 100644 index 0000000..3ff0df5 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/DigiKeyboard.h.old @@ -0,0 +1,230 @@ +/* + * Based on Obdev's AVRUSB code and under the same license. + * + * TODO: Make a proper file header. :-) + * Modified for Digispark by Digistump + */ +#ifndef __DigiKeyboard_h__ +#define __DigiKeyboard_h__ + +#include +#include +#include +#include + +#include "usbdrv.h" + +// TODO: Work around Arduino 12 issues better. +//#include +//#undef int() + +typedef uint8_t byte; + + +#define BUFFER_SIZE 2 // Minimum of 2: 1 for modifiers + 1 for keystroke + + +static uchar idleRate; // in 4 ms units + + +/* We use a simplifed keyboard report descriptor which does not support the + * boot protocol. We don't allow setting status LEDs and but we do allow + * simultaneous key presses. + * The report descriptor has been created with usb.org's "HID Descriptor Tool" + * which can be downloaded from http://www.usb.org/developers/hidpage/. + * Redundant entries (such as LOGICAL_MINIMUM and USAGE_PAGE) have been omitted + * for the second INPUT item. + */ +PROGMEM char usbHidReportDescriptor[USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH] = { /* USB report descriptor */ + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x06, // USAGE (Keyboard) + 0xa1, 0x01, // COLLECTION (Application) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + 0x19, 0xe0, // USAGE_MINIMUM (Keyboard LeftControl) + 0x29, 0xe7, // USAGE_MAXIMUM (Keyboard Right GUI) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x75, 0x01, // REPORT_SIZE (1) + 0x95, 0x08, // REPORT_COUNT (8) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (simultaneous keystrokes) + 0x75, 0x08, // REPORT_SIZE (8) + 0x25, 0x65, // LOGICAL_MAXIMUM (101) + 0x19, 0x00, // USAGE_MINIMUM (Reserved (no event indicated)) + 0x29, 0x65, // USAGE_MAXIMUM (Keyboard Application) + 0x81, 0x00, // INPUT (Data,Ary,Abs) + 0xc0 // END_COLLECTION +}; + + + +/* Keyboard usage values, see usb.org's HID-usage-tables document, chapter + * 10 Keyboard/Keypad Page for more codes. + */ +#define MOD_CONTROL_LEFT (1<<0) +#define MOD_SHIFT_LEFT (1<<1) +#define MOD_ALT_LEFT (1<<2) +#define MOD_GUI_LEFT (1<<3) +#define MOD_CONTROL_RIGHT (1<<4) +#define MOD_SHIFT_RIGHT (1<<5) +#define MOD_ALT_RIGHT (1<<6) +#define MOD_GUI_RIGHT (1<<7) + +#define KEY_A 4 +#define KEY_B 5 +#define KEY_C 6 +#define KEY_D 7 +#define KEY_E 8 +#define KEY_F 9 +#define KEY_G 10 +#define KEY_H 11 +#define KEY_I 12 +#define KEY_J 13 +#define KEY_K 14 +#define KEY_L 15 +#define KEY_M 16 +#define KEY_N 17 +#define KEY_O 18 +#define KEY_P 19 +#define KEY_Q 20 +#define KEY_R 21 +#define KEY_S 22 +#define KEY_T 23 +#define KEY_U 24 +#define KEY_V 25 +#define KEY_W 26 +#define KEY_X 27 +#define KEY_Y 28 +#define KEY_Z 29 +#define KEY_1 30 +#define KEY_2 31 +#define KEY_3 32 +#define KEY_4 33 +#define KEY_5 34 +#define KEY_6 35 +#define KEY_7 36 +#define KEY_8 37 +#define KEY_9 38 +#define KEY_0 39 + +#define KEY_ENTER 40 + +#define KEY_SPACE 44 + +#define KEY_F1 58 +#define KEY_F2 59 +#define KEY_F3 60 +#define KEY_F4 61 +#define KEY_F5 62 +#define KEY_F6 63 +#define KEY_F7 64 +#define KEY_F8 65 +#define KEY_F9 66 +#define KEY_F10 67 +#define KEY_F11 68 +#define KEY_F12 69 + +#define KEY_ARROW_LEFT 0x50 + + +class DigiKeyboardDevice { + public: + DigiKeyboardDevice () { + TIMSK &= !(1bmRequestType & USBRQ_TYPE_MASK) == USBRQ_TYPE_CLASS){ + /* class request type */ + + if(rq->bRequest == USBRQ_HID_GET_REPORT){ + /* wValue: ReportType (highbyte), ReportID (lowbyte) */ + + /* we only have one report type, so don't look at wValue */ + // TODO: Ensure it's okay not to return anything here? + return 0; + + }else if(rq->bRequest == USBRQ_HID_GET_IDLE){ + // usbMsgPtr = &idleRate; + // return 1; + return 0; + }else if(rq->bRequest == USBRQ_HID_SET_IDLE){ + idleRate = rq->wValue.bytes[1]; + } + }else{ + /* no vendor specific requests implemented */ + } + return 0; + } +#ifdef __cplusplus +} // extern "C" +#endif + + +#endif // __DigiKeyboard_h__ diff --git a/hardware/digistump/avr/libraries/DigiJoystick/JoystickReadme.txt b/hardware/digistump/avr/libraries/DigiJoystick/JoystickReadme.txt new file mode 100644 index 0000000..64ce3d9 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/JoystickReadme.txt @@ -0,0 +1,11 @@ +JoystickReadme.txt + +This library is for the attiny85 running tiny core Arduino (e.g. the Digispark) + +This implements a USB HID joystick device (currently 6 analog and 16 digital) +The code was borrowed mostly from the Digispark Keyboard library and from Raphaël Assénat's code on using an atmega8 as a Nintendo Gamecube/N64 controller to USB bridge: http://www.raphnet.net/electronique/gc_n64_usb/index_en.php +Raphaël's work is truly marvelous. + +Because most of this code is coming from other projects with GNU GPL, I am letting my modifications inherit the same protection. A copy of this license is included in the source. + +As to the use of this code in Arduino, include DigiJoystick.h as you would any other library. See the included sample for use of the functions. diff --git a/hardware/digistump/avr/libraries/DigiJoystick/License.txt b/hardware/digistump/avr/libraries/DigiJoystick/License.txt new file mode 100644 index 0000000..4460cfb --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/License.txt @@ -0,0 +1,361 @@ +OBJECTIVE DEVELOPMENT GmbH's V-USB driver software is distributed under the +terms and conditions of the GNU GPL version 2 or the GNU GPL version 3. It is +your choice whether you apply the terms of version 2 or version 3. The full +text of GPLv2 is included below. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/hardware/digistump/avr/libraries/DigiJoystick/Readme.txt b/hardware/digistump/avr/libraries/DigiJoystick/Readme.txt new file mode 100644 index 0000000..a010d97 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/Readme.txt @@ -0,0 +1,158 @@ +This is the Readme file to Objective Development's firmware-only USB driver +for Atmel AVR microcontrollers. For more information please visit +http://www.obdev.at/vusb/ + +This directory contains the USB firmware only. Copy it as-is to your own +project and add all .c and .S files to your project (these files are marked +with an asterisk in the list below). Then copy usbconfig-prototype.h as +usbconfig.h to your project and edit it according to your configuration. + + +TECHNICAL DOCUMENTATION +======================= +The technical documentation (API) for the firmware driver is contained in the +file "usbdrv.h". Please read all of it carefully! Configuration options are +documented in "usbconfig-prototype.h". + +The driver consists of the following files: + Readme.txt ............. The file you are currently reading. + Changelog.txt .......... Release notes for all versions of the driver. + usbdrv.h ............... Driver interface definitions and technical docs. +* usbdrv.c ............... High level language part of the driver. Link this + module to your code! +* usbdrvasm.S ............ Assembler part of the driver. This module is mostly + a stub and includes one of the usbdrvasm*.S files + depending on processor clock. Link this module to + your code! + usbdrvasm*.inc ......... Assembler routines for particular clock frequencies. + Included by usbdrvasm.S, don't link it directly! + asmcommon.inc .......... Common assembler routines. Included by + usbdrvasm*.inc, don't link it directly! + usbconfig-prototype.h .. Prototype for your own usbdrv.h file. +* oddebug.c .............. Debug functions. Only used when DEBUG_LEVEL is + defined to a value greater than 0. Link this module + to your code! + oddebug.h .............. Interface definitions of the debug module. + usbportability.h ....... Header with compiler-dependent stuff. + usbdrvasm.asm .......... Compatibility stub for IAR-C-compiler. Use this + module instead of usbdrvasm.S when you assembler + with IAR's tools. + License.txt ............ Open Source license for this driver. + CommercialLicense.txt .. Optional commercial license for this driver. + USB-ID-FAQ.txt ......... General infos about USB Product- and Vendor-IDs. + USB-IDs-for-free.txt ... List and terms of use for free shared PIDs. + +(*) ... These files should be linked to your project. + + +CPU CORE CLOCK FREQUENCY +======================== +We supply assembler modules for clock frequencies of 12 MHz, 12.8 MHz, 15 MHz, +16 MHz, 16.5 MHz 18 MHz and 20 MHz. Other clock rates are not supported. The +actual clock rate must be configured in usbdrv.h unless you use the default +12 MHz. + +12 MHz Clock +This is the traditional clock rate of V-USB because it's the lowest clock +rate where the timing constraints of the USB spec can be met. + +15 MHz Clock +Similar to 12 MHz, but some NOPs inserted. On the other hand, the higher clock +rate allows for some loops which make the resulting code size somewhat smaller +than the 12 MHz version. + +16 MHz Clock +This clock rate has been added for users of the Arduino board and other +ready-made boards which come with a fixed 16 MHz crystal. It's also an option +if you need the slightly higher clock rate for performance reasons. Since +16 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code +is somewhat tricky and has to insert a leap cycle every third byte. + +12.8 MHz and 16.5 MHz Clock +The assembler modules for these clock rates differ from the other modules +because they have been built for an RC oscillator with only 1% precision. The +receiver code inserts leap cycles to compensate for clock deviations. 1% is +also the precision which can be achieved by calibrating the internal RC +oscillator of the AVR. Please note that only AVRs with internal 64 MHz PLL +oscillator can reach 16.5 MHz with the RC oscillator. This includes the very +popular ATTiny25, ATTiny45, ATTiny85 series as well as the ATTiny26. Almost +all AVRs can reach 12.8 MHz, although this is outside the specified range. + +See the EasyLogger example at http://www.obdev.at/vusb/easylogger.html for +code which calibrates the RC oscillator based on the USB frame clock. + +18 MHz Clock +This module is closer to the USB specification because it performs an on the +fly CRC check for incoming packets. Packets with invalid checksum are +discarded as required by the spec. If you also implement checks for data +PID toggling on application level (see option USB_CFG_CHECK_DATA_TOGGLING +in usbconfig.h for more info), this ensures data integrity. Due to the CRC +tables and alignment requirements, this code is bigger than modules for other +clock rates. To activate this module, you must define USB_CFG_CHECK_CRC to 1 +and USB_CFG_CLOCK_KHZ to 18000 in usbconfig.h. + +20 MHz Clock +This module is for people who won't do it with less than the maximum. Since +20 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code +uses similar tricks as the 16 MHz module to insert leap cycles. + + +USB IDENTIFIERS +=============== +Every USB device needs a vendor- and a product-identifier (VID and PID). VIDs +are obtained from usb.org for a price of 1,500 USD. Once you have a VID, you +can assign PIDs at will. + +Since an entry level cost of 1,500 USD is too high for most small companies +and hobbyists, we provide some VID/PID pairs for free. See the file +USB-IDs-for-free.txt for details. + +Objective Development also has some license offerings which include product +IDs. See http://www.obdev.at/vusb/ for details. + + +DEVELOPMENT SYSTEM +================== +This driver has been developed and optimized for the GNU compiler version 3 +(gcc 3). It does work well with gcc 4, but with bigger code size. We recommend +that you use the GNU compiler suite because it is freely available. V-USB +has also been ported to the IAR compiler and assembler. It has been tested +with IAR 4.10B/W32 and 4.12A/W32 on an ATmega8 with the "small" and "tiny" +memory model. Not every release is tested with IAR CC and the driver may +therefore fail to compile with IAR. Please note that gcc is more efficient for +usbdrv.c because this module has been deliberately optimized for gcc. + + +USING V-USB FOR FREE +==================== +The AVR firmware driver is published under the GNU General Public License +Version 2 (GPL2) and the GNU General Public License Version 3 (GPL3). It is +your choice whether you apply the terms of version 2 or version 3. + +If you decide for the free GPL2 or GPL3, we STRONGLY ENCOURAGE you to do the +following things IN ADDITION to the obligations from the GPL: + +(1) Publish your entire project on a web site and drop us a note with the URL. +Use the form at http://www.obdev.at/vusb/feedback.html for your submission. +If you don't have a web site, you can publish the project in obdev's +documentation wiki at +http://www.obdev.at/goto.php?t=vusb-wiki&p=hosted-projects. + +(2) Adhere to minimum publication standards. Please include AT LEAST: + - a circuit diagram in PDF, PNG or GIF format + - full source code for the host software + - a Readme.txt file in ASCII format which describes the purpose of the + project and what can be found in which directories and which files + - a reference to http://www.obdev.at/vusb/ + +(3) If you improve the driver firmware itself, please give us a free license +to your modifications for our commercial license offerings. + + +COMMERCIAL LICENSES FOR V-USB +============================= +If you don't want to publish your source code under the terms of the GPL, +you can simply pay money for V-USB. As an additional benefit you get +USB PIDs for free, reserved exclusively to you. See the file +"CommercialLicense.txt" for details. + diff --git a/hardware/digistump/avr/libraries/DigiJoystick/USB-ID-FAQ.txt b/hardware/digistump/avr/libraries/DigiJoystick/USB-ID-FAQ.txt new file mode 100644 index 0000000..d1de8fb --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/USB-ID-FAQ.txt @@ -0,0 +1,149 @@ +Version 2009-08-22 + +========================== +WHY DO WE NEED THESE IDs? +========================== + +USB is more than a low level protocol for data transport. It also defines a +common set of requests which must be understood by all devices. And as part +of these common requests, the specification defines data structures, the +USB Descriptors, which are used to describe the properties of the device. + +From the perspective of an operating system, it is therefore possible to find +out basic properties of a device (such as e.g. the manufacturer and the name +of the device) without a device-specific driver. This is essential because +the operating system can choose a driver to load based on this information +(Plug-And-Play). + +Among the most important properties in the Device Descriptor are the USB +Vendor- and Product-ID. Both are 16 bit integers. The most simple form of +driver matching is based on these IDs. The driver announces the Vendor- and +Product-IDs of the devices it can handle and the operating system loads the +appropriate driver when the device is connected. + +It is obvious that this technique only works if the pair Vendor- plus +Product-ID is unique: Only devices which require the same driver can have the +same pair of IDs. + + +===================================================== +HOW DOES THE USB STANDARD ENSURE THAT IDs ARE UNIQUE? +===================================================== + +Since it is so important that USB IDs are unique, the USB Implementers Forum, +Inc. (usb.org) needs a way to enforce this legally. It is not forbidden by +law to build a device and assign it any random numbers as IDs. Usb.org +therefore needs an agreement to regulate the use of USB IDs. The agreement +binds only parties who agreed to it, of course. Everybody else is free to use +any numbers for their IDs. + +So how can usb.org ensure that every manufacturer of USB devices enters into +an agreement with them? They do it via trademark licensing. Usb.org has +registered the trademark "USB", all associated logos and related terms. If +you want to put an USB logo on your product or claim that it is USB +compliant, you must license these trademarks from usb.org. And this is where +you enter into an agreement. See the "USB-IF Trademark License Agreement and +Usage Guidelines for the USB-IF Logo" at +http://www.usb.org/developers/logo_license/. + +Licensing the USB trademarks requires that you buy a USB Vendor-ID from +usb.org (one-time fee of ca. 2,000 USD), that you become a member of usb.org +(yearly fee of ca. 4,000 USD) and that you meet all the technical +specifications from the USB spec. + +This means that most hobbyists and small companies will never be able to +become USB compliant, just because membership is so expensive. And you can't +be compliant with a driver based on V-USB anyway, because the AVR's port pins +don't meet the electrical specifications for USB. So, in principle, all +hobbyists and small companies are free to choose any random numbers for their +IDs. They have nothing to lose... + +There is one exception worth noting, though: If you use a sub-component which +implements USB, the vendor of the sub-components may guarantee USB +compliance. This might apply to some or all of FTDI's solutions. + + +======================================================================= +WHY SHOULD YOU OBTAIN USB IDs EVEN IF YOU DON'T LICENSE USB TRADEMARKS? +======================================================================= + +You have learned in the previous section that you are free to choose any +numbers for your IDs anyway. So why not do exactly this? There is still the +technical issue. If you choose IDs which are already in use by somebody else, +operating systems will load the wrong drivers and your device won't work. +Even if you choose IDs which are not currently in use, they may be in use in +the next version of the operating system or even after an automatic update. + +So what you need is a pair of Vendor- and Product-IDs for which you have the +guarantee that no USB compliant product uses them. This implies that no +operating system will ever ship with drivers responsible for these IDs. + + +============================================== +HOW DOES OBJECTIVE DEVELOPMENT HANDLE USB IDs? +============================================== + +Objective Development gives away pairs of USB-IDs with their V-USB licenses. +In order to ensure that these IDs are unique, Objective Development has an +agreement with the company/person who has bought the USB Vendor-ID from +usb.org. This agreement ensures that a range of USB Product-IDs is reserved +for assignment by Objective Development and that the owner of the Vendor-ID +won't give it to anybody else. + +This means that you have to trust three parties to ensure uniqueness of +your IDs: + + - Objective Development, that they don't give the same PID to more than + one person. + - The owner of the Vendor-ID that they don't assign PIDs from the range + assigned to Objective Development to anybody else. + - Usb.org that they don't assign the same Vendor-ID a second time. + + +================================== +WHO IS THE OWNER OF THE VENDOR-ID? +================================== + +Objective Development has obtained ranges of USB Product-IDs under two +Vendor-IDs: Under Vendor-ID 5824 from Wouter van Ooijen (Van Ooijen +Technische Informatica, www.voti.nl) and under Vendor-ID 8352 from Jason +Kotzin (Clay Logic, www.claylogic.com). Both VID owners have received their +Vendor-ID directly from usb.org. + + +========================================================================= +CAN I USE USB-IDs FROM OBJECTIVE DEVELOPMENT WITH OTHER DRIVERS/HARDWARE? +========================================================================= + +The short answer is: Yes. All you get is a guarantee that the IDs are never +assigned to anybody else. What more do you need? + + +============================ +WHAT ABOUT SHARED ID PAIRS? +============================ + +Objective Development has reserved some PID/VID pairs for shared use. You +have no guarantee of uniqueness for them, except that no USB compliant device +uses them. In order to avoid technical problems, we must ensure that all +devices with the same pair of IDs use the same driver on kernel level. For +details, see the file USB-IDs-for-free.txt. + + +====================================================== +I HAVE HEARD THAT SUB-LICENSING OF USB-IDs IS ILLEGAL? +====================================================== + +A 16 bit integer number cannot be protected by copyright laws. It is not +sufficiently complex. And since none of the parties involved entered into the +USB-IF Trademark License Agreement, we are not bound by this agreement. So +there is no reason why it should be illegal to sub-license USB-IDs. + + +============================================= +WHO IS LIABLE IF THERE ARE INCOMPATIBILITIES? +============================================= + +Objective Development disclaims all liabilities which might arise from the +assignment of IDs. If you guarantee product features to your customers +without proper disclaimer, YOU are liable for that. diff --git a/hardware/digistump/avr/libraries/DigiJoystick/USB-IDs-for-free.txt b/hardware/digistump/avr/libraries/DigiJoystick/USB-IDs-for-free.txt new file mode 100644 index 0000000..2f4d59a --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/USB-IDs-for-free.txt @@ -0,0 +1,148 @@ +Version 2009-08-22 + +=========================== +FREE USB-IDs FOR SHARED USE +=========================== + +Objective Development has reserved a set of USB Product-IDs for use according +to the guidelines outlined below. For more information about the concept of +USB IDs please see the file USB-ID-FAQ.txt. Objective Development guarantees +that the IDs listed below are not used by any USB compliant devices. + + +==================== +MECHANISM OF SHARING +==================== + +From a technical point of view, two different devices can share the same USB +Vendor- and Product-ID if they require the same driver on operating system +level. We make use of this fact by assigning separate IDs for various device +classes. On application layer, devices must be distinguished by their textual +name or serial number. We offer separate sets of IDs for discrimination by +textual name and for serial number. + +Examples for shared use of USB IDs are included with V-USB in the "examples" +subdirectory. + + +====================================== +IDs FOR DISCRIMINATION BY TEXTUAL NAME +====================================== + +If you use one of the IDs listed below, your device and host-side software +must conform to these rules: + +(1) The USB device MUST provide a textual representation of the manufacturer +and product identification. The manufacturer identification MUST be available +at least in USB language 0x0409 (English/US). + +(2) The textual manufacturer identification MUST contain either an Internet +domain name (e.g. "mycompany.com") registered and owned by you, or an e-mail +address under your control (e.g. "myname@gmx.net"). You can embed the domain +name or e-mail address in any string you like, e.g. "Objective Development +http://www.obdev.at/vusb/". + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(4) You may choose any string for the textual product identification, as long +as this string is unique within the scope of your textual manufacturer +identification. + +(5) Application side device look-up MUST be based on the textual manufacturer +and product identification in addition to VID/PID matching. The driver +matching MUST be a comparison of the entire strings, NOT a sub-string match. + +(6) For devices which implement a particular USB device class (e.g. HID), the +operating system's default class driver MUST be used. If an operating system +driver for Vendor Class devices is needed, this driver must be libusb or +libusb-win32 (see http://libusb.org/ and +http://libusb-win32.sourceforge.net/). + +Table if IDs for discrimination by textual name: + +PID dec (hex) | VID dec (hex) | Description of use +==============+===============+============================================ +1500 (0x05dc) | 5824 (0x16c0) | For Vendor Class devices with libusb +--------------+---------------+-------------------------------------------- +1503 (0x05df) | 5824 (0x16c0) | For generic HID class devices (which are + | | NOT mice, keyboards or joysticks) +--------------+---------------+-------------------------------------------- +1505 (0x05e1) | 5824 (0x16c0) | For CDC-ACM class devices (modems) +--------------+---------------+-------------------------------------------- +1508 (0x05e4) | 5824 (0x16c0) | For MIDI class devices +--------------+---------------+-------------------------------------------- + +Note that Windows caches the textual product- and vendor-description for +mice, keyboards and joysticks. Name-bsed discrimination is therefore not +recommended for these device classes. + + +======================================= +IDs FOR DISCRIMINATION BY SERIAL NUMBER +======================================= + +If you use one of the IDs listed below, your device and host-side software +must conform to these rules: + +(1) The USB device MUST provide a textual representation of the serial +number. The serial number string MUST be available at least in USB language +0x0409 (English/US). + +(2) The serial number MUST start with either an Internet domain name (e.g. +"mycompany.com") registered and owned by you, or an e-mail address under your +control (e.g. "myname@gmx.net"), both terminated with a colon (":") character. +You MAY append any string you like for further discrimination of your devices. + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(5) Application side device look-up MUST be based on the serial number string +in addition to VID/PID matching. The matching must start at the first +character of the serial number string and include the colon character +terminating your domain or e-mail address. It MAY stop anywhere after that. + +(6) For devices which implement a particular USB device class (e.g. HID), the +operating system's default class driver MUST be used. If an operating system +driver for Vendor Class devices is needed, this driver must be libusb or +libusb-win32 (see http://libusb.org/ and +http://libusb-win32.sourceforge.net/). + +Table if IDs for discrimination by serial number string: + +PID dec (hex) | VID dec (hex) | Description of use +===============+===============+=========================================== +10200 (0x27d8) | 5824 (0x16c0) | For Vendor Class devices with libusb +---------------+---------------+------------------------------------------- +10201 (0x27d9) | 5824 (0x16c0) | For generic HID class devices (which are + | | NOT mice, keyboards or joysticks) +---------------+---------------+------------------------------------------- +10202 (0x27da) | 5824 (0x16c0) | For USB Mice +---------------+---------------+------------------------------------------- +10203 (0x27db) | 5824 (0x16c0) | For USB Keyboards +---------------+---------------+------------------------------------------- +10204 (0x27db) | 5824 (0x16c0) | For USB Joysticks +---------------+---------------+------------------------------------------- +10205 (0x27dc) | 5824 (0x16c0) | For CDC-ACM class devices (modems) +---------------+---------------+------------------------------------------- +10206 (0x27dd) | 5824 (0x16c0) | For MIDI class devices +---------------+---------------+------------------------------------------- + + +================= +ORIGIN OF USB-IDs +================= + +OBJECTIVE DEVELOPMENT Software GmbH has obtained all VID/PID pairs listed +here from Wouter van Ooijen (see www.voti.nl) for exclusive disposition. +Wouter van Ooijen has obtained the VID from the USB Implementers Forum, Inc. +(see www.usb.org). The VID is registered for the company name "Van Ooijen +Technische Informatica". + + +========== +DISCLAIMER +========== + +OBJECTIVE DEVELOPMENT Software GmbH disclaims all liability for any +problems which are caused by the shared use of these VID/PID pairs. diff --git a/hardware/digistump/avr/libraries/DigiJoystick/USBID-License.txt b/hardware/digistump/avr/libraries/DigiJoystick/USBID-License.txt new file mode 100644 index 0000000..c40be92 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/USBID-License.txt @@ -0,0 +1,154 @@ +Royalty-Free Non-Exclusive Use of USB Product-IDs +================================================= + +Version 2009-04-13 + +Strictly speaking, this is not a license. You can't give a license to use +a simple number (such as e.g. 1500) for any purpose. This is a set of rules +which should make it possible to build USB devices without the requirement +for individual USB IDs. If you break one of the rules, you will run into +technical problems sooner or later, but you don't risk legal trouble. + + +OBJECTIVE DEVELOPMENT Software GmbH hereby grants you the non-exclusive +right to use four USB.org vendor-ID (VID) / product-ID (PID) pairs with +products based on Objective Development's firmware-only USB driver for +Atmel AVR microcontrollers: + + * VID = 5824 (=0x16c0) / PID = 1500 (=0x5dc) for devices implementing no + USB device class (vendor-class devices with USB class = 0xff). Devices + using this pair will be referred to as "VENDOR CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1503 (=0x5df) for HID class devices + (excluding mice and keyboards). Devices using this pair will be referred + to as "HID CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1505 (=0x5e1) for CDC class modem devices + Devices using this pair will be referred to as "CDC-ACM CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1508 (=0x5e4) for MIDI class devices + Devices using this pair will be referred to as "MIDI CLASS" devices. + +Since the granted right is non-exclusive, the same VID/PID pairs may be +used by many companies and individuals for different products. To avoid +conflicts, your device and host driver software MUST adhere to the rules +outlined below. + +OBJECTIVE DEVELOPMENT Software GmbH has obtained these VID/PID pairs from +Wouter van Ooijen (see www.voti.nl) for exclusive disposition. Wouter van +Ooijen has obtained the VID from the USB Implementers Forum, Inc. +(see www.usb.org). The VID is registered for the company name +"Van Ooijen Technische Informatica". + + +RULES AND RESTRICTIONS +====================== + +(1) The USB device MUST provide a textual representation of the +manufacturer and product identification. The manufacturer identification +MUST be available at least in USB language 0x0409 (English/US). + +(2) The textual manufacturer identification MUST contain either an Internet +domain name (e.g. "mycompany.com") registered and owned by you, or an +e-mail address under your control (e.g. "myname@gmx.net"). You can embed +the domain name or e-mail address in any string you like, e.g. "Objective +Development http://www.obdev.at/vusb/". + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(4) You may choose any string for the textual product identification, as +long as this string is unique within the scope of your textual manufacturer +identification. + +(5) Matching of device-specific drivers MUST be based on the textual +manufacturer and product identification in addition to the usual VID/PID +matching. This means that operating system features which are based on +VID/PID matching only (e.g. Windows kernel level drivers, automatic actions +when the device is plugged in etc) MUST NOT be used. The driver matching +MUST be a comparison of the entire strings, NOT a sub-string match. For +CDC-ACM CLASS and MIDI CLASS devices, a generic class driver should be used +and the matching is based on the USB device class. + +(6) The extent to which VID/PID matching is allowed for non device-specific +drivers or features depends on the operating system and particular VID/PID +pair used: + + * Mac OS X, Linux, FreeBSD and other Unixes: No VID/PID matching is + required and hence no VID/PID-only matching is allowed at all. + + * Windows: The operating system performs VID/PID matching for the kernel + level driver. You are REQUIRED to use libusb-win32 (see + http://libusb-win32.sourceforge.net/) as the kernel level driver for + VENDOR CLASS devices. HID CLASS devices all use the generic HID class + driver shipped with Windows, except mice and keyboards. You therefore + MUST NOT use any of the shared VID/PID pairs for mice or keyboards. + CDC-ACM CLASS devices require a ".inf" file which matches on the VID/PID + pair. This ".inf" file MUST load the "usbser" driver to configure the + device as modem (COM-port). + +(7) OBJECTIVE DEVELOPMENT Software GmbH disclaims all liability for any +problems which are caused by the shared use of these VID/PID pairs. You +have been warned that the sharing of VID/PID pairs may cause problems. If +you want to avoid them, get your own VID/PID pair for exclusive use. + + +HOW TO IMPLEMENT THESE RULES +============================ + +The following rules are for VENDOR CLASS and HID CLASS devices. CDC-ACM +CLASS and MIDI CLASS devices use the operating system's class driver and +don't need a custom driver. + +The host driver MUST iterate over all devices with the given VID/PID +numbers in their device descriptors and query the string representation for +the manufacturer name in USB language 0x0409 (English/US). It MUST compare +the ENTIRE string with your textual manufacturer identification chosen in +(2) above. A substring search for your domain or e-mail address is NOT +acceptable. The driver MUST NOT touch the device (other than querying the +descriptors) unless the strings match. + +For all USB devices with matching VID/PID and textual manufacturer +identification, the host driver must query the textual product +identification and string-compare it with the name of the product it can +control. It may only initialize the device if the product matches exactly. + +Objective Development provides examples for these matching rules with the +"PowerSwitch" project (using libusb) and with the "Automator" project +(using Windows calls on Windows and libusb on Unix). + + +Technical Notes: +================ + +Sharing the same VID/PID pair among devices is possible as long as ALL +drivers which match the VID/PID also perform matching on the textual +identification strings. This is easy on all operating systems except +Windows, since Windows establishes a static connection between the VID/PID +pair and a kernel level driver. All devices with the same VID/PID pair must +therefore use THE SAME kernel level driver. + +We therefore demand that you use libusb-win32 for VENDOR CLASS devices. +This is a generic kernel level driver which allows all types of USB access +for user space applications. This is only a partial solution of the +problem, though, because different device drivers may come with different +versions of libusb-win32 and they may not work with the libusb version of +the respective other driver. You are therefore encouraged to test your +driver against a broad range of libusb-win32 versions. Do not use new +features in new versions, or check for their existence before you use them. +When a new libusb-win32 becomes available, make sure that your driver is +compatible with it. + +For HID CLASS devices it is necessary that all those devices bind to the +same kernel driver: Microsoft's generic USB HID driver. This is true for +all HID devices except those with a specialized driver. Currently, the only +HIDs with specialized drivers are mice and keyboards. You therefore MUST +NOT use a shared VID/PID with mouse and keyboard devices. + +Sharing the same VID/PID among different products is unusual and probably +violates the USB specification. If you do it, you do it at your own risk. + +To avoid possible incompatibilities, we highly recommend that you get your +own VID/PID pair if you intend to sell your product. Objective +Development's commercial licenses for V-USB include a PID for +unrestricted exclusive use. diff --git a/hardware/digistump/avr/libraries/DigiJoystick/asmcommon.inc b/hardware/digistump/avr/libraries/DigiJoystick/asmcommon.inc new file mode 100644 index 0000000..07d692b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/asmcommon.inc @@ -0,0 +1,188 @@ +/* Name: asmcommon.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2007-11-05 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id$ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file contains assembler code which is shared among the USB driver +implementations for different CPU cocks. Since the code must be inserted +in the middle of the module, it's split out into this file and #included. + +Jump destinations called from outside: + sofError: Called when no start sequence was found. + se0: Called when a package has been successfully received. + overflow: Called when receive buffer overflows. + doReturn: Called after sending data. + +Outside jump destinations used by this module: + waitForJ: Called to receive an already arriving packet. + sendAckAndReti: + sendNakAndReti: + sendCntAndReti: + usbSendAndReti: + +The following macros must be defined before this file is included: + .macro POP_STANDARD + .endm + .macro POP_RETI + .endm +*/ + +#define token x1 + +overflow: + ldi x2, 1< + +void setup() { + DigiJoystick.begin(); //start or reenumerate USB - BREAKING CHANGE from old versions that didn't require this + //while(!DigiJoystick.isConnected()) {} //don't run sketch until USB is connected +} + + +void loop() { + // If not using plentiful DigiJoystick.delay() calls, make sure to + //DigiJoystick.update(); // call this at least every 50ms + // calling more often than that is fine + // this will actually only send the data every once in a while unless the data is different + + // you can set the values from a raw byte array with: + // char myBuf[8] = { + // x, y, xrot, yrot, zrot, slider, + // buttonLowByte, buttonHighByte + // }; + // DigiJoystick.setValues(myBuf); + + // Or we can also set values like this: + DigiJoystick.setX((byte) (millis() / 100)); // scroll X left to right repeatedly + DigiJoystick.setY((byte) 0x30); + DigiJoystick.setXROT((byte) 0x60); + DigiJoystick.setYROT((byte) 0x90); + DigiJoystick.setZROT((byte) 0xB0); + DigiJoystick.setSLIDER((byte) 0xF0); + + // it's best to use DigiJoystick.delay() because it knows how to talk to + // the connected computer - otherwise the USB link can crash with the + // regular arduino delay() function + DigiJoystick.delay(50); // wait 50 milliseconds + + //we can set buttons like this + //DigiJoystick.setButton(Button Number 0-15, State 1 = on, 0 = off); + //you can call this multiple times and it won't clear other buttons in between + //Turn on button 0 and 1 + DigiJoystick.setButton(0, 1); + DigiJoystick.setButton(1, 1); + //Turn off button 1 + DigiJoystick.setButton(1, 0); + //Turn on button 3 + DigiJoystick.setButton(3, 1); + + // we can also set buttons like this (lowByte, highByte) + //DigiJoystick.setButtons(0x00, 0x00); + + +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigiJoystick/keywords.txt b/hardware/digistump/avr/libraries/DigiJoystick/keywords.txt new file mode 100644 index 0000000..1fa483d --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/keywords.txt @@ -0,0 +1,3 @@ +DigiKeyboard KEYWORD1 +update KEYWORD2 +sendKeyStroke KEYWORD2 \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigiJoystick/oddebug.c b/hardware/digistump/avr/libraries/DigiJoystick/oddebug.c new file mode 100644 index 0000000..945457c --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/oddebug.c @@ -0,0 +1,50 @@ +/* Name: oddebug.c + * Project: AVR library + * Author: Christian Starkjohann + * Creation Date: 2005-01-16 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: oddebug.c 692 2008-11-07 15:07:40Z cs $ + */ + +#include "oddebug.h" + +#if DEBUG_LEVEL > 0 + +#warning "Never compile production devices with debugging enabled" + +static void uartPutc(char c) +{ + while(!(ODDBG_USR & (1 << ODDBG_UDRE))); /* wait for data register empty */ + ODDBG_UDR = c; +} + +static uchar hexAscii(uchar h) +{ + h &= 0xf; + if(h >= 10) + h += 'a' - (uchar)10 - '0'; + h += '0'; + return h; +} + +static void printHex(uchar c) +{ + uartPutc(hexAscii(c >> 4)); + uartPutc(hexAscii(c)); +} + +void odDebug(uchar prefix, uchar *data, uchar len) +{ + printHex(prefix); + uartPutc(':'); + while(len--){ + uartPutc(' '); + printHex(*data++); + } + uartPutc('\r'); + uartPutc('\n'); +} + +#endif diff --git a/hardware/digistump/avr/libraries/DigiJoystick/oddebug.h b/hardware/digistump/avr/libraries/DigiJoystick/oddebug.h new file mode 100644 index 0000000..d61309d --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/oddebug.h @@ -0,0 +1,123 @@ +/* Name: oddebug.h + * Project: AVR library + * Author: Christian Starkjohann + * Creation Date: 2005-01-16 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: oddebug.h 692 2008-11-07 15:07:40Z cs $ + */ + +#ifndef __oddebug_h_included__ +#define __oddebug_h_included__ + +/* +General Description: +This module implements a function for debug logs on the serial line of the +AVR microcontroller. Debugging can be configured with the define +'DEBUG_LEVEL'. If this macro is not defined or defined to 0, all debugging +calls are no-ops. If it is 1, DBG1 logs will appear, but not DBG2. If it is +2, DBG1 and DBG2 logs will be printed. + +A debug log consists of a label ('prefix') to indicate which debug log created +the output and a memory block to dump in hex ('data' and 'len'). +*/ + + +#ifndef F_CPU +# define F_CPU 12000000 /* 12 MHz */ +#endif + +/* make sure we have the UART defines: */ +#include "usbportability.h" + +#ifndef uchar +# define uchar unsigned char +#endif + +#if DEBUG_LEVEL > 0 && !(defined TXEN || defined TXEN0) /* no UART in device */ +# warning "Debugging disabled because device has no UART" +# undef DEBUG_LEVEL +#endif + +#ifndef DEBUG_LEVEL +# define DEBUG_LEVEL 0 +#endif + +/* ------------------------------------------------------------------------- */ + +#if DEBUG_LEVEL > 0 +# define DBG1(prefix, data, len) odDebug(prefix, data, len) +#else +# define DBG1(prefix, data, len) +#endif + +#if DEBUG_LEVEL > 1 +# define DBG2(prefix, data, len) odDebug(prefix, data, len) +#else +# define DBG2(prefix, data, len) +#endif + +/* ------------------------------------------------------------------------- */ + +#if DEBUG_LEVEL > 0 +extern void odDebug(uchar prefix, uchar *data, uchar len); + +/* Try to find our control registers; ATMEL likes to rename these */ + +#if defined UBRR +# define ODDBG_UBRR UBRR +#elif defined UBRRL +# define ODDBG_UBRR UBRRL +#elif defined UBRR0 +# define ODDBG_UBRR UBRR0 +#elif defined UBRR0L +# define ODDBG_UBRR UBRR0L +#endif + +#if defined UCR +# define ODDBG_UCR UCR +#elif defined UCSRB +# define ODDBG_UCR UCSRB +#elif defined UCSR0B +# define ODDBG_UCR UCSR0B +#endif + +#if defined TXEN +# define ODDBG_TXEN TXEN +#else +# define ODDBG_TXEN TXEN0 +#endif + +#if defined USR +# define ODDBG_USR USR +#elif defined UCSRA +# define ODDBG_USR UCSRA +#elif defined UCSR0A +# define ODDBG_USR UCSR0A +#endif + +#if defined UDRE +# define ODDBG_UDRE UDRE +#else +# define ODDBG_UDRE UDRE0 +#endif + +#if defined UDR +# define ODDBG_UDR UDR +#elif defined UDR0 +# define ODDBG_UDR UDR0 +#endif + +static inline void odDebugInit(void) +{ + ODDBG_UCR |= (1< + +#ifndef uchar +#define uchar unsigned char +#endif + +/* ------------------------------------------------------------------------- */ +/* ------------------------ Oscillator Calibration ------------------------- */ +/* ------------------------------------------------------------------------- */ + +/* Calibrate the RC oscillator. Our timing reference is the Start Of Frame + * signal (a single SE0 bit) repeating every millisecond immediately after + * a USB RESET. We first do a binary search for the OSCCAL value and then + * optimize this value with a neighboorhod search. + */ +void calibrateOscillator(void) +{ +uchar step = 128; +uchar trialValue = 0, optimumValue; +int x, optimumDev, targetValue = (unsigned)(1499 * (double)F_CPU / 10.5e6 + 0.5); + + /* do a binary search: */ + do{ + OSCCAL = trialValue + step; + x = usbMeasureFrameLength(); /* proportional to current real frequency */ + if(x < targetValue) /* frequency still too low */ + trialValue += step; + step >>= 1; + }while(step > 0); + /* We have a precision of +/- 1 for optimum OSCCAL here */ + /* now do a neighborhood search for optimum value */ + optimumValue = trialValue; + optimumDev = x; /* this is certainly far away from optimum */ + for(OSCCAL = trialValue - 1; OSCCAL <= trialValue + 1; OSCCAL++){ + x = usbMeasureFrameLength() - targetValue; + if(x < 0) + x = -x; + if(x < optimumDev){ + optimumDev = x; + optimumValue = OSCCAL; + } + } + OSCCAL = optimumValue; +} +/* +Note: This calibration algorithm may try OSCCAL values of up to 192 even if +the optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +You may replace this search algorithm with any other algorithm you like if +you have additional constraints such as a maximum CPU clock. +For version 5.x RC oscillators (those with a split range of 2x128 steps, e.g. +ATTiny25, ATTiny45, ATTiny85), it may be useful to search for the optimum in +both regions. +*/ diff --git a/hardware/digistump/avr/libraries/DigiJoystick/osccal.c.lst b/hardware/digistump/avr/libraries/DigiJoystick/osccal.c.lst new file mode 100644 index 0000000..336a049 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/osccal.c.lst @@ -0,0 +1,106 @@ +GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 1 + + + 1 .file "osccal.c" + 2 __SREG__ = 0x3f + 3 __SP_H__ = 0x3e + 4 __SP_L__ = 0x3d + 5 __CCP__ = 0x34 + 6 __tmp_reg__ = 0 + 7 __zero_reg__ = 1 + 8 .text + 9 .global calibrateOscillator + 10 .type calibrateOscillator, @function + 11 calibrateOscillator: + 12 0000 FF92 push r15 + 13 0002 0F93 push r16 + 14 0004 1F93 push r17 + 15 0006 CF93 push r28 + 16 0008 DF93 push r29 + 17 /* prologue: function */ + 18 /* frame size = 0 */ + 19 000a 80E8 ldi r24,lo8(-128) + 20 000c F82E mov r15,r24 + 21 000e 00E0 ldi r16,lo8(0) + 22 0010 C0E0 ldi r28,lo8(0) + 23 0012 D0E0 ldi r29,hi8(0) + 24 .L4: + 25 0014 102F mov r17,r16 + 26 0016 1F0D add r17,r15 + 27 0018 11BF out 81-32,r17 + 28 001a 00D0 rcall usbMeasureFrameLength + 29 001c 29E0 ldi r18,hi8(2356) + 30 001e 8433 cpi r24,lo8(2356) + 31 0020 9207 cpc r25,r18 + 32 0022 04F0 brlt .L2 + 33 0024 102F mov r17,r16 + 34 .L2: + 35 0026 F694 lsr r15 + 36 0028 2196 adiw r28,1 + 37 002a C830 cpi r28,8 + 38 002c D105 cpc r29,__zero_reg__ + 39 002e 01F0 breq .L3 + 40 0030 012F mov r16,r17 + 41 0032 00C0 rjmp .L4 + 42 .L3: + 43 0034 1150 subi r17,lo8(-(-1)) + 44 0036 11BF out 81-32,r17 + 45 0038 1F5F subi r17,lo8(-(1)) + 46 003a 012F mov r16,r17 + 47 003c EC01 movw r28,r24 + 48 003e 00C0 rjmp .L5 + 49 .L8: + 50 0040 00D0 rcall usbMeasureFrameLength + 51 0042 8453 subi r24,lo8(-(-2356)) + 52 0044 9940 sbci r25,hi8(-(-2356)) + 53 0046 97FF sbrs r25,7 + 54 0048 00C0 rjmp .L6 + 55 004a 9095 com r25 + 56 004c 8195 neg r24 + 57 004e 9F4F sbci r25,lo8(-1) + GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 2 + + + 58 .L6: + 59 0050 8C17 cp r24,r28 + 60 0052 9D07 cpc r25,r29 + 61 0054 04F4 brge .L7 + 62 0056 01B7 in r16,81-32 + 63 0058 EC01 movw r28,r24 + 64 .L7: + 65 005a 81B7 in r24,81-32 + 66 005c 8F5F subi r24,lo8(-(1)) + 67 005e 81BF out 81-32,r24 + 68 .L5: + 69 0060 21B7 in r18,81-32 + 70 0062 30E0 ldi r19,lo8(0) + 71 0064 812F mov r24,r17 + 72 0066 90E0 ldi r25,lo8(0) + 73 0068 0196 adiw r24,1 + 74 006a 8217 cp r24,r18 + 75 006c 9307 cpc r25,r19 + 76 006e 04F4 brge .L8 + 77 0070 01BF out 81-32,r16 + 78 /* epilogue start */ + 79 0072 DF91 pop r29 + 80 0074 CF91 pop r28 + 81 0076 1F91 pop r17 + 82 0078 0F91 pop r16 + 83 007a FF90 pop r15 + 84 007c 0895 ret + 85 .size calibrateOscillator, .-calibrateOscillator + GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 3 + + +DEFINED SYMBOLS + *ABS*:00000000 osccal.c +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:2 *ABS*:0000003f __SREG__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:3 *ABS*:0000003e __SP_H__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:4 *ABS*:0000003d __SP_L__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:5 *ABS*:00000034 __CCP__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:6 *ABS*:00000000 __tmp_reg__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:7 *ABS*:00000001 __zero_reg__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:11 .text:00000000 calibrateOscillator + +UNDEFINED SYMBOLS +usbMeasureFrameLength diff --git a/hardware/digistump/avr/libraries/DigiJoystick/osccal.h b/hardware/digistump/avr/libraries/DigiJoystick/osccal.h new file mode 100644 index 0000000..710ce05 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/osccal.h @@ -0,0 +1,65 @@ +/* Name: osccal.h + * Author: Christian Starkjohann + * Creation Date: 2008-04-10 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osccal.h 762 2009-08-12 17:10:30Z cs $ + */ + +/* +General Description: +This module contains a function which calibrates the AVR's internal RC +oscillator so that the CPU runs at F_CPU (F_CPU is a macro which must be +defined when the module is compiled, best passed in the compiler command +line). The time reference is the USB frame clock of 1 kHz available +immediately after a USB RESET condition. Timing is done by counting CPU +cycles, so all interrupts must be disabled while the calibration runs. For +low level timing measurements, usbMeasureFrameLength() is called. This +function must be enabled in usbconfig.h by defining +USB_CFG_HAVE_MEASURE_FRAME_LENGTH to 1. It is recommended to call +calibrateOscillator() from the reset hook in usbconfig.h: +*/ + +#ifndef __ASSEMBLER__ +#include // for sei() +extern void calibrateOscillator(void); +#endif +#define USB_RESET_HOOK(resetStarts) if(!resetStarts){cli(); calibrateOscillator(); sei();} + +/* +This routine is an alternative to the continuous synchronization described +in osctune.h. + +Algorithm used: +calibrateOscillator() first does a binary search in the OSCCAL register for +the best matching oscillator frequency. Then it does a next neighbor search +to find the value with the lowest clock rate deviation. It is guaranteed to +find the best match among neighboring values, but for version 5 oscillators +(which have a discontinuous relationship between OSCCAL and frequency) a +better match might be available in another OSCCAL region. + +Limitations: +This calibration algorithm may try OSCCAL values of up to 192 even if the +optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +Precision depends on the OSCCAL vs. frequency dependency of the oscillator. +Typical precision for an ATMega168 (derived from the OSCCAL vs. F_RC diagram +in the data sheet) should be in the range of 0.4%. Only the 12.8 MHz and +16.5 MHz versions of V-USB (with built-in receiver PLL) can tolerate this +deviation! All other frequency modules require at least 0.2% precision. +*/ + +#ifndef __OSCCAL_H_INCLUDED__ +#define __OSCCAL_H_INCLUDED__ + +//void calibrateOscillator(void); +/* This function calibrates the RC oscillator so that the CPU runs at F_CPU. + * It MUST be called immediately after the end of a USB RESET condition! + * Disable all interrupts during the call! + * It is recommended that you store the resulting value in EEPROM so that a + * good guess value is available after the next reset. + */ + + +#endif /* __OSCCAL_H_INCLUDED__ */ diff --git a/hardware/digistump/avr/libraries/DigiJoystick/osccal.o b/hardware/digistump/avr/libraries/DigiJoystick/osccal.o new file mode 100644 index 0000000..08e2187 Binary files /dev/null and b/hardware/digistump/avr/libraries/DigiJoystick/osccal.o differ diff --git a/hardware/digistump/avr/libraries/DigiJoystick/osctune.h b/hardware/digistump/avr/libraries/DigiJoystick/osctune.h new file mode 100644 index 0000000..c751648 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/osctune.h @@ -0,0 +1,88 @@ +/* Name: osctune.h + * Author: Christian Starkjohann + * Creation Date: 2008-10-18 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osctune.h 692 2008-11-07 15:07:40Z cs $ + */ + +/* +General Description: +This file is declared as C-header file although it is mostly documentation +how the RC oscillator can be kept in sync to the USB frame rate. The code +shown here must be added to usbconfig.h or this header file is included from +there. This code works only if D- is wired to the interrupt, not D+!!! + +This is an alternative to the osccal routine in osccal.c. It has the advantage +that the synchronization is done continuously and that it has more compact +code size. The disadvantages are slow synchronization (it may take a while +until the driver works), that messages immediately after the SOF pulse may be +lost (and need to be retried by the host) and that the interrupt is on D- +contrary to most examples. + +You may want to store a good calibration value in EEPROM for the next startup. +You know that the calibration value is good when the first USB message is +received. Do not store the value on every received message because the EEPROM +has a limited endurance. + +Notes: +(*) You must declare the global character variable "lastTimer0Value" in your +main code. + +(*) Timer 0 must be free running (not written by your code) and the prescaling +must be consistent with the TIMER0_PRESCALING define. + +(*) Good values for Timer 0 prescaling depend on how precise the clock must +be tuned and how far away from the default clock rate the target clock is. +For precise tuning, choose a low prescaler factor, for a broad range of tuning +choose a high one. A prescaler factor of 64 is good for the entire OSCCAL +range and allows a precision of better than +/-1%. A prescaler factor of 8 +allows tuning to slightly more than +/-6% of the default frequency and is +more precise than one step of OSCCAL. It is therefore not suitable to tune an +8 MHz oscillator to 12.5 MHz. + +Thanks to Henrik Haftmann for the idea to this routine! +*/ + +#define TIMER0_PRESCALING 64 /* must match the configuration for TIMER0 in main */ +#define TOLERATED_DEVIATION_PPT 5 /* max clock deviation before we tune in 1/10 % */ +/* derived constants: */ +#define EXPECTED_TIMER0_INCREMENT ((F_CPU / (1000 * TIMER0_PRESCALING)) & 0xff) +#define TOLERATED_DEVIATION (TOLERATED_DEVIATION_PPT * F_CPU / (1000000 * TIMER0_PRESCALING)) + +#ifdef __ASSEMBLER__ +macro tuneOsccal + push YH ;[0] + in YL, TCNT0 ;[2] + lds YH, lastTimer0Value ;[3] + sts lastTimer0Value, YL ;[5] + sub YL, YH ;[7] time passed since last frame + subi YL, EXPECTED_TIMER0_INCREMENT ;[8] +#if OSCCAL > 0x3f /* outside I/O addressable range */ + lds YH, OSCCAL ;[6] +#else + in YH, OSCCAL ;[6] assembler modle uses __SFR_OFFSET == 0 +#endif + cpi YL, TOLERATED_DEVIATION + 1 ;[10] + brmi notTooHigh ;[11] + subi YH, 1 ;[12] clock rate was too high +; brcs tuningOverflow ; optionally check for overflow + rjmp osctuneDone ;[13] +notTooHigh: + cpi YL, -TOLERATED_DEVIATION ;[13] + brpl osctuneDone ;[14] not too low + inc YH ;[15] clock rate was too low +; breq tuningOverflow ; optionally check for overflow +osctuneDone: +#if OSCCAL > 0x3f /* outside I/O addressable range */ + sts OSCCAL, YH ;[12-13] store tuned value +#else + out OSCCAL, YH ;[12-13] store tuned value +#endif +tuningOverflow: + pop YH ;[17] + endm ;[19] max number of cycles +#endif + +#define USB_SOF_HOOK tuneOsccal diff --git a/hardware/digistump/avr/libraries/DigiJoystick/usbconfig-prototype.h b/hardware/digistump/avr/libraries/DigiJoystick/usbconfig-prototype.h new file mode 100644 index 0000000..a0fd1bf --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/usbconfig-prototype.h @@ -0,0 +1,369 @@ +/* Name: usbconfig.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2005-04-01 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbconfig-prototype.h 767 2009-08-22 11:39:22Z cs $ + */ + +#ifndef __usbconfig_h_included__ +#define __usbconfig_h_included__ + +/* +General Description: +This file is an example configuration (with inline documentation) for the USB +driver. It configures V-USB for USB D+ connected to Port D bit 2 (which is +also hardware interrupt 0 on many devices) and USB D- to Port D bit 4. You may +wire the lines to any other port, as long as D+ is also wired to INT0 (or any +other hardware interrupt, as long as it is the highest level interrupt, see +section at the end of this file). ++ To create your own usbconfig.h file, copy this file to your project's ++ firmware source directory) and rename it to "usbconfig.h". ++ Then edit it accordingly. +*/ + +/* ---------------------------- Hardware Config ---------------------------- */ + +#define USB_CFG_IOPORTNAME D +/* This is the port where the USB bus is connected. When you configure it to + * "B", the registers PORTB, PINB and DDRB will be used. + */ +#define USB_CFG_DMINUS_BIT 4 +/* This is the bit number in USB_CFG_IOPORT where the USB D- line is connected. + * This may be any bit in the port. + */ +#define USB_CFG_DPLUS_BIT 2 +/* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected. + * This may be any bit in the port. Please note that D+ must also be connected + * to interrupt pin INT0! [You can also use other interrupts, see section + * "Optional MCU Description" below, or you can connect D- to the interrupt, as + * it is required if you use the USB_COUNT_SOF feature. If you use D- for the + * interrupt, the USB interrupt will also be triggered at Start-Of-Frame + * markers every millisecond.] + */ +#define USB_CFG_CLOCK_KHZ (F_CPU/1000) +/* Clock rate of the AVR in kHz. Legal values are 12000, 12800, 15000, 16000, + * 16500 and 20000. The 12.8 MHz and 16.5 MHz versions of the code require no + * crystal, they tolerate +/- 1% deviation from the nominal frequency. All + * other rates require a precision of 2000 ppm and thus a crystal! + * Default if not specified: 12 MHz + */ +#define USB_CFG_CHECK_CRC 0 +/* Define this to 1 if you want that the driver checks integrity of incoming + * data packets (CRC checks). CRC checks cost quite a bit of code size and are + * currently only available for 18 MHz crystal clock. You must choose + * USB_CFG_CLOCK_KHZ = 18000 if you enable this option. + */ + +/* ----------------------- Optional Hardware Config ------------------------ */ + +/* #define USB_CFG_PULLUP_IOPORTNAME D */ +/* If you connect the 1.5k pullup resistor from D- to a port pin instead of + * V+, you can connect and disconnect the device from firmware by calling + * the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h). + * This constant defines the port on which the pullup resistor is connected. + */ +/* #define USB_CFG_PULLUP_BIT 4 */ +/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined + * above) where the 1.5k pullup resistor is connected. See description + * above for details. + */ + +/* --------------------------- Functional Range ---------------------------- */ + +#define USB_CFG_HAVE_INTRIN_ENDPOINT 0 +/* Define this to 1 if you want to compile a version with two endpoints: The + * default control endpoint 0 and an interrupt-in endpoint (any other endpoint + * number). + */ +#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0 +/* Define this to 1 if you want to compile a version with three endpoints: The + * default control endpoint 0, an interrupt-in endpoint 3 (or the number + * configured below) and a catch-all default interrupt-in endpoint as above. + * You must also define USB_CFG_HAVE_INTRIN_ENDPOINT to 1 for this feature. + */ +#define USB_CFG_EP3_NUMBER 3 +/* If the so-called endpoint 3 is used, it can now be configured to any other + * endpoint number (except 0) with this macro. Default if undefined is 3. + */ +/* #define USB_INITIAL_DATATOKEN USBPID_DATA1 */ +/* The above macro defines the startup condition for data toggling on the + * interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA1. + * Since the token is toggled BEFORE sending any data, the first packet is + * sent with the oposite value of this configuration! + */ +#define USB_CFG_IMPLEMENT_HALT 0 +/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature + * for endpoint 1 (interrupt endpoint). Although you may not need this feature, + * it is required by the standard. We have made it a config option because it + * bloats the code considerably. + */ +#define USB_CFG_SUPPRESS_INTR_CODE 0 +/* Define this to 1 if you want to declare interrupt-in endpoints, but don't + * want to send any data over them. If this macro is defined to 1, functions + * usbSetInterrupt() and usbSetInterrupt3() are omitted. This is useful if + * you need the interrupt-in endpoints in order to comply to an interface + * (e.g. HID), but never want to send any data. This option saves a couple + * of bytes in flash memory and the transmit buffers in RAM. + */ +#define USB_CFG_INTR_POLL_INTERVAL 10 +/* If you compile a version with endpoint 1 (interrupt-in), this is the poll + * interval. The value is in milliseconds and must not be less than 10 ms for + * low speed devices. + */ +#define USB_CFG_IS_SELF_POWERED 0 +/* Define this to 1 if the device has its own power supply. Set it to 0 if the + * device is powered from the USB bus. + */ +#define USB_CFG_MAX_BUS_POWER 100 +/* Set this variable to the maximum USB bus power consumption of your device. + * The value is in milliamperes. [It will be divided by two since USB + * communicates power requirements in units of 2 mA.] + */ +#define USB_CFG_IMPLEMENT_FN_WRITE 0 +/* Set this to 1 if you want usbFunctionWrite() to be called for control-out + * transfers. Set it to 0 if you don't need it and want to save a couple of + * bytes. + */ +#define USB_CFG_IMPLEMENT_FN_READ 0 +/* Set this to 1 if you need to send control replies which are generated + * "on the fly" when usbFunctionRead() is called. If you only want to send + * data from a static buffer, set it to 0 and return the data from + * usbFunctionSetup(). This saves a couple of bytes. + */ +#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0 +/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints. + * You must implement the function usbFunctionWriteOut() which receives all + * interrupt/bulk data sent to any endpoint other than 0. The endpoint number + * can be found in 'usbRxToken'. + */ +#define USB_CFG_HAVE_FLOWCONTROL 0 +/* Define this to 1 if you want flowcontrol over USB data. See the definition + * of the macros usbDisableAllRequests() and usbEnableAllRequests() in + * usbdrv.h. + */ +#define USB_CFG_LONG_TRANSFERS 0 +/* Define this to 1 if you want to send/receive blocks of more than 254 bytes + * in a single control-in or control-out transfer. Note that the capability + * for long transfers increases the driver size. + */ +/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */ +/* This macro is a hook if you want to do unconventional things. If it is + * defined, it's inserted at the beginning of received message processing. + * If you eat the received message and don't want default processing to + * proceed, do a return after doing your things. One possible application + * (besides debugging) is to flash a status LED on each packet. + */ +/* #define USB_RESET_HOOK(resetStarts) if(!resetStarts){hadUsbReset();} */ +/* This macro is a hook if you need to know when an USB RESET occurs. It has + * one parameter which distinguishes between the start of RESET state and its + * end. + */ +/* #define USB_SET_ADDRESS_HOOK() hadAddressAssigned(); */ +/* This macro (if defined) is executed when a USB SET_ADDRESS request was + * received. + */ +#define USB_COUNT_SOF 0 +/* define this macro to 1 if you need the global variable "usbSofCount" which + * counts SOF packets. This feature requires that the hardware interrupt is + * connected to D- instead of D+. + */ +/* #ifdef __ASSEMBLER__ + * macro myAssemblerMacro + * in YL, TCNT0 + * sts timer0Snapshot, YL + * endm + * #endif + * #define USB_SOF_HOOK myAssemblerMacro + * This macro (if defined) is executed in the assembler module when a + * Start Of Frame condition is detected. It is recommended to define it to + * the name of an assembler macro which is defined here as well so that more + * than one assembler instruction can be used. The macro may use the register + * YL and modify SREG. If it lasts longer than a couple of cycles, USB messages + * immediately after an SOF pulse may be lost and must be retried by the host. + * What can you do with this hook? Since the SOF signal occurs exactly every + * 1 ms (unless the host is in sleep mode), you can use it to tune OSCCAL in + * designs running on the internal RC oscillator. + * Please note that Start Of Frame detection works only if D- is wired to the + * interrupt, not D+. THIS IS DIFFERENT THAN MOST EXAMPLES! + */ +#define USB_CFG_CHECK_DATA_TOGGLING 0 +/* define this macro to 1 if you want to filter out duplicate data packets + * sent by the host. Duplicates occur only as a consequence of communication + * errors, when the host does not receive an ACK. Please note that you need to + * implement the filtering yourself in usbFunctionWriteOut() and + * usbFunctionWrite(). Use the global usbCurrentDataToken and a static variable + * for each control- and out-endpoint to check for duplicate packets. + */ +#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 0 +/* define this macro to 1 if you want the function usbMeasureFrameLength() + * compiled in. This function can be used to calibrate the AVR's RC oscillator. + */ +#define USB_USE_FAST_CRC 0 +/* The assembler module has two implementations for the CRC algorithm. One is + * faster, the other is smaller. This CRC routine is only used for transmitted + * messages where timing is not critical. The faster routine needs 31 cycles + * per byte while the smaller one needs 61 to 69 cycles. The faster routine + * may be worth the 32 bytes bigger code size if you transmit lots of data and + * run the AVR close to its limit. + */ + +/* -------------------------- Device Description --------------------------- */ + +#define USB_CFG_VENDOR_ID 0xc0, 0x16 /* = 0x16c0 = 5824 = voti.nl */ +/* USB vendor ID for the device, low byte first. If you have registered your + * own Vendor ID, define it here. Otherwise you may use one of obdev's free + * shared VID/PID pairs. Be sure to read USB-IDs-for-free.txt for rules! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_ID 0xdc, 0x05 /* = 0x05dc = 1500 */ +/* This is the ID of the product, low byte first. It is interpreted in the + * scope of the vendor ID. If you have registered your own VID with usb.org + * or if you have licensed a PID from somebody else, define it here. Otherwise + * you may use one of obdev's free shared VID/PID pairs. See the file + * USB-IDs-for-free.txt for details! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_VERSION 0x00, 0x01 +/* Version number of the device: Minor number first, then major number. + */ +#define USB_CFG_VENDOR_NAME 'o', 'b', 'd', 'e', 'v', '.', 'a', 't' +#define USB_CFG_VENDOR_NAME_LEN 8 +/* These two values define the vendor name returned by the USB device. The name + * must be given as a list of characters under single quotes. The characters + * are interpreted as Unicode (UTF-16) entities. + * If you don't want a vendor name string, undefine these macros. + * ALWAYS define a vendor name containing your Internet domain name if you use + * obdev's free shared VID/PID pair. See the file USB-IDs-for-free.txt for + * details. + */ +#define USB_CFG_DEVICE_NAME 'T', 'e', 'm', 'p', 'l', 'a', 't', 'e' +#define USB_CFG_DEVICE_NAME_LEN 8 +/* Same as above for the device name. If you don't want a device name, undefine + * the macros. See the file USB-IDs-for-free.txt before you assign a name if + * you use a shared VID/PID. + */ +/*#define USB_CFG_SERIAL_NUMBER 'N', 'o', 'n', 'e' */ +/*#define USB_CFG_SERIAL_NUMBER_LEN 0 */ +/* Same as above for the serial number. If you don't want a serial number, + * undefine the macros. + * It may be useful to provide the serial number through other means than at + * compile time. See the section about descriptor properties below for how + * to fine tune control over USB descriptors such as the string descriptor + * for the serial number. + */ +#define USB_CFG_DEVICE_CLASS 0xff /* set to 0 if deferred to interface */ +#define USB_CFG_DEVICE_SUBCLASS 0 +/* See USB specification if you want to conform to an existing device class. + * Class 0xff is "vendor specific". + */ +#define USB_CFG_INTERFACE_CLASS 0 /* define class here if not at device level */ +#define USB_CFG_INTERFACE_SUBCLASS 0 +#define USB_CFG_INTERFACE_PROTOCOL 0 +/* See USB specification if you want to conform to an existing device class or + * protocol. The following classes must be set at interface level: + * HID class is 3, no subclass and protocol required (but may be useful!) + * CDC class is 2, use subclass 2 and protocol 1 for ACM + */ +/* #define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 42 */ +/* Define this to the length of the HID report descriptor, if you implement + * an HID device. Otherwise don't define it or define it to 0. + * If you use this define, you must add a PROGMEM character array named + * "usbHidReportDescriptor" to your code which contains the report descriptor. + * Don't forget to keep the array and this define in sync! + */ + +/* #define USB_PUBLIC static */ +/* Use the define above if you #include usbdrv.c instead of linking against it. + * This technique saves a couple of bytes in flash memory. + */ + +/* ------------------- Fine Control over USB Descriptors ------------------- */ +/* If you don't want to use the driver's default USB descriptors, you can + * provide our own. These can be provided as (1) fixed length static data in + * flash memory, (2) fixed length static data in RAM or (3) dynamically at + * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more + * information about this function. + * Descriptor handling is configured through the descriptor's properties. If + * no properties are defined or if they are 0, the default descriptor is used. + * Possible properties are: + * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched + * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is + * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if + * you want RAM pointers. + * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found + * in static memory is in RAM, not in flash memory. + * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash), + * the driver must know the descriptor's length. The descriptor itself is + * found at the address of a well known identifier (see below). + * List of static descriptor names (must be declared PROGMEM if in flash): + * char usbDescriptorDevice[]; + * char usbDescriptorConfiguration[]; + * char usbDescriptorHidReport[]; + * char usbDescriptorString0[]; + * int usbDescriptorStringVendor[]; + * int usbDescriptorStringDevice[]; + * int usbDescriptorStringSerialNumber[]; + * Other descriptors can't be provided statically, they must be provided + * dynamically at runtime. + * + * Descriptor properties are or-ed or added together, e.g.: + * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18)) + * + * The following descriptors are defined: + * USB_CFG_DESCR_PROPS_DEVICE + * USB_CFG_DESCR_PROPS_CONFIGURATION + * USB_CFG_DESCR_PROPS_STRINGS + * USB_CFG_DESCR_PROPS_STRING_0 + * USB_CFG_DESCR_PROPS_STRING_VENDOR + * USB_CFG_DESCR_PROPS_STRING_PRODUCT + * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER + * USB_CFG_DESCR_PROPS_HID + * USB_CFG_DESCR_PROPS_HID_REPORT + * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver) + * + * Note about string descriptors: String descriptors are not just strings, they + * are Unicode strings prefixed with a 2 byte header. Example: + * int serialNumberDescriptor[] = { + * USB_STRING_DESCRIPTOR_HEADER(6), + * 'S', 'e', 'r', 'i', 'a', 'l' + * }; + */ + +#define USB_CFG_DESCR_PROPS_DEVICE 0 +#define USB_CFG_DESCR_PROPS_CONFIGURATION 0 +#define USB_CFG_DESCR_PROPS_STRINGS 0 +#define USB_CFG_DESCR_PROPS_STRING_0 0 +#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0 +#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0 +#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0 +#define USB_CFG_DESCR_PROPS_HID 0 +#define USB_CFG_DESCR_PROPS_HID_REPORT 0 +#define USB_CFG_DESCR_PROPS_UNKNOWN 0 + +/* ----------------------- Optional MCU Description ------------------------ */ + +/* The following configurations have working defaults in usbdrv.h. You + * usually don't need to set them explicitly. Only if you want to run + * the driver on a device which is not yet supported or with a compiler + * which is not fully supported (such as IAR C) or if you use a differnt + * interrupt than INT0, you may have to define some of these. + */ +/* #define USB_INTR_CFG MCUCR */ +/* #define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) */ +/* #define USB_INTR_CFG_CLR 0 */ +/* #define USB_INTR_ENABLE GIMSK */ +/* #define USB_INTR_ENABLE_BIT INT0 */ +/* #define USB_INTR_PENDING GIFR */ +/* #define USB_INTR_PENDING_BIT INTF0 */ +/* #define USB_INTR_VECTOR SIG_INTERRUPT0 */ + +#endif /* __usbconfig_h_included__ */ diff --git a/hardware/digistump/avr/libraries/DigiJoystick/usbconfig.h b/hardware/digistump/avr/libraries/DigiJoystick/usbconfig.h new file mode 100644 index 0000000..dd5b32a --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/usbconfig.h @@ -0,0 +1,398 @@ +/* Name: usbconfig.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2005-04-01 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbconfig-prototype.h 767 2009-08-22 11:39:22Z cs $ + */ + +#ifndef __usbconfig_h_included__ +#define __usbconfig_h_included__ + +/* +General Description: +This file is an example configuration (with inline documentation) for the USB +driver. It configures V-USB for USB D+ connected to Port D bit 2 (which is +also hardware interrupt 0 on many devices) and USB D- to Port D bit 4. You may +wire the lines to any other port, as long as D+ is also wired to INT0 (or any +other hardware interrupt, as long as it is the highest level interrupt, see +section at the end of this file). ++ To create your own usbconfig.h file, copy this file to your project's ++ firmware source directory) and rename it to "usbconfig.h". ++ Then edit it accordingly. +*/ + +/* ---------------------------- Hardware Config ---------------------------- */ + +#if defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 1 +#define USB_CFG_DPLUS_BIT 2 + +#elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 4 + +#elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 6 + +#elif defined (__AVR_ATtiny461__) || defined (__AVR_ATtiny861__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 5 +#define USB_CFG_DPLUS_BIT 6 +#else +/* ATtiny2313, ATmega8/48/88/168 */ +#define USB_CFG_IOPORTNAME D +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 2 +#endif +#define USB_CFG_CLOCK_KHZ (F_CPU/1000) +/* Clock rate of the AVR in kHz. Legal values are 12000, 12800, 15000, 16000, + * 16500 and 20000. The 12.8 MHz and 16.5 MHz versions of the code require no + * crystal, they tolerate +/- 1% deviation from the nominal frequency. All + * other rates require a precision of 2000 ppm and thus a crystal! + * Default if not specified: 12 MHz + */ +#define USB_CFG_CHECK_CRC 0 +/* Define this to 1 if you want that the driver checks integrity of incoming + * data packets (CRC checks). CRC checks cost quite a bit of code size and are + * currently only available for 18 MHz crystal clock. You must choose + * USB_CFG_CLOCK_KHZ = 18000 if you enable this option. + */ + +/* ----------------------- Optional Hardware Config ------------------------ */ + +//#define USB_CFG_PULLUP_IOPORTNAME D +/* If you connect the 1.5k pullup resistor from D- to a port pin instead of + * V+, you can connect and disconnect the device from firmware by calling + * the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h). + * This constant defines the port on which the pullup resistor is connected. + */ +//#define USB_CFG_PULLUP_BIT 5 +/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined + * above) where the 1.5k pullup resistor is connected. See description + * above for details. + */ + +/* --------------------------- Functional Range ---------------------------- */ + +#define USB_CFG_HAVE_INTRIN_ENDPOINT 1 +/* Define this to 1 if you want to compile a version with two endpoints: The + * default control endpoint 0 and an interrupt-in endpoint (any other endpoint + * number). + */ +#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0 +/* Define this to 1 if you want to compile a version with three endpoints: The + * default control endpoint 0, an interrupt-in endpoint 3 (or the number + * configured below) and a catch-all default interrupt-in endpoint as above. + * You must also define USB_CFG_HAVE_INTRIN_ENDPOINT to 1 for this feature. + */ +#define USB_CFG_EP3_NUMBER 3 +/* If the so-called endpoint 3 is used, it can now be configured to any other + * endpoint number (except 0) with this macro. Default if undefined is 3. + */ +/* #define USB_INITIAL_DATATOKEN USBPID_DATA1 */ +/* The above macro defines the startup condition for data toggling on the + * interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA1. + * Since the token is toggled BEFORE sending any data, the first packet is + * sent with the oposite value of this configuration! + */ +#define USB_CFG_IMPLEMENT_HALT 0 +/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature + * for endpoint 1 (interrupt endpoint). Although you may not need this feature, + * it is required by the standard. We have made it a config option because it + * bloats the code considerably. + */ +#define USB_CFG_SUPPRESS_INTR_CODE 0 +/* Define this to 1 if you want to declare interrupt-in endpoints, but don't + * want to send any data over them. If this macro is defined to 1, functions + * usbSetInterrupt() and usbSetInterrupt3() are omitted. This is useful if + * you need the interrupt-in endpoints in order to comply to an interface + * (e.g. HID), but never want to send any data. This option saves a couple + * of bytes in flash memory and the transmit buffers in RAM. + */ +#define USB_CFG_INTR_POLL_INTERVAL 10 +/* If you compile a version with endpoint 1 (interrupt-in), this is the poll + * interval. The value is in milliseconds and must not be less than 10 ms for + * low speed devices. + */ +#define USB_CFG_IS_SELF_POWERED 0 +/* Define this to 1 if the device has its own power supply. Set it to 0 if the + * device is powered from the USB bus. + */ +#define USB_CFG_MAX_BUS_POWER 100 +/* Set this variable to the maximum USB bus power consumption of your device. + * The value is in milliamperes. [It will be divided by two since USB + * communicates power requirements in units of 2 mA.] + */ +#define USB_CFG_IMPLEMENT_FN_WRITE 0 +/* Set this to 1 if you want usbFunctionWrite() to be called for control-out + * transfers. Set it to 0 if you don't need it and want to save a couple of + * bytes. + */ +#define USB_CFG_IMPLEMENT_FN_READ 0 +/* Set this to 1 if you need to send control replies which are generated + * "on the fly" when usbFunctionRead() is called. If you only want to send + * data from a static buffer, set it to 0 and return the data from + * usbFunctionSetup(). This saves a couple of bytes. + */ +#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0 +/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints. + * You must implement the function usbFunctionWriteOut() which receives all + * interrupt/bulk data sent to any endpoint other than 0. The endpoint number + * can be found in 'usbRxToken'. + */ +#define USB_CFG_HAVE_FLOWCONTROL 0 +/* Define this to 1 if you want flowcontrol over USB data. See the definition + * of the macros usbDisableAllRequests() and usbEnableAllRequests() in + * usbdrv.h. + */ +#define USB_CFG_LONG_TRANSFERS 0 +/* Define this to 1 if you want to send/receive blocks of more than 254 bytes + * in a single control-in or control-out transfer. Note that the capability + * for long transfers increases the driver size. + */ +/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */ +/* This macro is a hook if you want to do unconventional things. If it is + * defined, it's inserted at the beginning of received message processing. + * If you eat the received message and don't want default processing to + * proceed, do a return after doing your things. One possible application + * (besides debugging) is to flash a status LED on each packet. + */ +/* #define USB_RESET_HOOK(resetStarts) if(!resetStarts){hadUsbReset();} */ +/* This macro is a hook if you need to know when an USB RESET occurs. It has + * one parameter which distinguishes between the start of RESET state and its + * end. + */ +/* #define USB_SET_ADDRESS_HOOK() hadAddressAssigned(); */ +/* This macro (if defined) is executed when a USB SET_ADDRESS request was + * received. + */ +#define USB_COUNT_SOF 0 +/* define this macro to 1 if you need the global variable "usbSofCount" which + * counts SOF packets. This feature requires that the hardware interrupt is + * connected to D- instead of D+. + */ +/* #ifdef __ASSEMBLER__ + * macro myAssemblerMacro + * in YL, TCNT0 + * sts timer0Snapshot, YL + * endm + * #endif + * #define USB_SOF_HOOK myAssemblerMacro + * This macro (if defined) is executed in the assembler module when a + * Start Of Frame condition is detected. It is recommended to define it to + * the name of an assembler macro which is defined here as well so that more + * than one assembler instruction can be used. The macro may use the register + * YL and modify SREG. If it lasts longer than a couple of cycles, USB messages + * immediately after an SOF pulse may be lost and must be retried by the host. + * What can you do with this hook? Since the SOF signal occurs exactly every + * 1 ms (unless the host is in sleep mode), you can use it to tune OSCCAL in + * designs running on the internal RC oscillator. + * Please note that Start Of Frame detection works only if D- is wired to the + * interrupt, not D+. THIS IS DIFFERENT THAN MOST EXAMPLES! + */ +#define USB_CFG_CHECK_DATA_TOGGLING 0 +/* define this macro to 1 if you want to filter out duplicate data packets + * sent by the host. Duplicates occur only as a consequence of communication + * errors, when the host does not receive an ACK. Please note that you need to + * implement the filtering yourself in usbFunctionWriteOut() and + * usbFunctionWrite(). Use the global usbCurrentDataToken and a static variable + * for each control- and out-endpoint to check for duplicate packets. + */ +#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 1 +#include "osccal.h" +/* define this macro to 1 if you want the function usbMeasureFrameLength() + * compiled in. This function can be used to calibrate the AVR's RC oscillator. + */ +#define USB_USE_FAST_CRC 0 +/* The assembler module has two implementations for the CRC algorithm. One is + * faster, the other is smaller. This CRC routine is only used for transmitted + * messages where timing is not critical. The faster routine needs 31 cycles + * per byte while the smaller one needs 61 to 69 cycles. The faster routine + * may be worth the 32 bytes bigger code size if you transmit lots of data and + * run the AVR close to its limit. + */ + +/* -------------------------- Device Description --------------------------- */ + +#define USB_CFG_VENDOR_ID 0xc0, 0x16 +/* USB vendor ID for the device, low byte first. If you have registered your + * own Vendor ID, define it here. Otherwise you may use one of obdev's free + * shared VID/PID pairs. Be sure to read USB-IDs-for-free.txt for rules! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_ID 0xdc, 0x27 +/* This is the ID of the product, low byte first. It is interpreted in the + * scope of the vendor ID. If you have registered your own VID with usb.org + * or if you have licensed a PID from somebody else, define it here. Otherwise + * you may use one of obdev's free shared VID/PID pairs. See the file + * USB-IDs-for-free.txt for details! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_VERSION 0x00, 0x01 +/* Version number of the device: Minor number first, then major number. + */ +#define USB_CFG_VENDOR_NAME 'd','i','g','i','s','t','u','m','p','.','c','o','m' +#define USB_CFG_VENDOR_NAME_LEN 13 +/* These two values define the vendor name returned by the USB device. The name + * must be given as a list of characters under single quotes. The characters + * are interpreted as Unicode (UTF-16) entities. + * If you don't want a vendor name string, undefine these macros. + * ALWAYS define a vendor name containing your Internet domain name if you use + * obdev's free shared VID/PID pair. See the file USB-IDs-for-free.txt for + * details. + */ +#define USB_CFG_DEVICE_NAME 'D','i','g','i','K','e','y' +#define USB_CFG_DEVICE_NAME_LEN 7 +/* Same as above for the device name. If you don't want a device name, undefine + * the macros. See the file USB-IDs-for-free.txt before you assign a name if + * you use a shared VID/PID. + */ +#define USB_CFG_SERIAL_NUMBER 'd','i','g','i','s','t','u','m','p','.','c','o','m',':','J','o','y' +#define USB_CFG_SERIAL_NUMBER_LEN 17 +/* Same as above for the serial number. If you don't want a serial number, + * undefine the macros. + * It may be useful to provide the serial number through other means than at + * compile time. See the section about descriptor properties below for how + * to fine tune control over USB descriptors such as the string descriptor + * for the serial number. + */ +#define USB_CFG_DEVICE_CLASS 0 /* set to 0 if deferred to interface */ +#define USB_CFG_DEVICE_SUBCLASS 0 +/* See USB specification if you want to conform to an existing device class. + * Class 0xff is "vendor specific". + */ +#define USB_CFG_INTERFACE_CLASS 0x03 /* HID */ /* define class here if not at device level */ +#define USB_CFG_INTERFACE_SUBCLASS 0x0 +#define USB_CFG_INTERFACE_PROTOCOL 0x0 +/* See USB specification if you want to conform to an existing device class or + * protocol. The following classes must be set at interface level: + * HID class is 3, no subclass and protocol required (but may be useful!) + * CDC class is 2, use subclass 2 and protocol 1 for ACM + */ +#define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 53 +/* Define this to the length of the HID report descriptor, if you implement + * an HID device. Otherwise don't define it or define it to 0. + * If you use this define, you must add a PROGMEM character array named + * "usbHidReportDescriptor" to your code which contains the report descriptor. + * Don't forget to keep the array and this define in sync! + */ + +/* #define USB_PUBLIC static */ +/* Use the define above if you #include usbdrv.c instead of linking against it. + * This technique saves a couple of bytes in flash memory. + */ + +/* ------------------- Fine Control over USB Descriptors ------------------- */ +/* If you don't want to use the driver's default USB descriptors, you can + * provide our own. These can be provided as (1) fixed length static data in + * flash memory, (2) fixed length static data in RAM or (3) dynamically at + * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more + * information about this function. + * Descriptor handling is configured through the descriptor's properties. If + * no properties are defined or if they are 0, the default descriptor is used. + * Possible properties are: + * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched + * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is + * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if + * you want RAM pointers. + * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found + * in static memory is in RAM, not in flash memory. + * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash), + * the driver must know the descriptor's length. The descriptor itself is + * found at the address of a well known identifier (see below). + * List of static descriptor names (must be declared PROGMEM if in flash): + * char usbDescriptorDevice[]; + * char usbDescriptorConfiguration[]; + * char usbDescriptorHidReport[]; + * char usbDescriptorString0[]; + * int usbDescriptorStringVendor[]; + * int usbDescriptorStringDevice[]; + * int usbDescriptorStringSerialNumber[]; + * Other descriptors can't be provided statically, they must be provided + * dynamically at runtime. + * + * Descriptor properties are or-ed or added together, e.g.: + * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18)) + * + * The following descriptors are defined: + * USB_CFG_DESCR_PROPS_DEVICE + * USB_CFG_DESCR_PROPS_CONFIGURATION + * USB_CFG_DESCR_PROPS_STRINGS + * USB_CFG_DESCR_PROPS_STRING_0 + * USB_CFG_DESCR_PROPS_STRING_VENDOR + * USB_CFG_DESCR_PROPS_STRING_PRODUCT + * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER + * USB_CFG_DESCR_PROPS_HID + * USB_CFG_DESCR_PROPS_HID_REPORT + * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver) + * + * Note about string descriptors: String descriptors are not just strings, they + * are Unicode strings prefixed with a 2 byte header. Example: + * int serialNumberDescriptor[] = { + * USB_STRING_DESCRIPTOR_HEADER(6), + * 'S', 'e', 'r', 'i', 'a', 'l' + * }; + */ + +#define USB_CFG_DESCR_PROPS_DEVICE 0 +#define USB_CFG_DESCR_PROPS_CONFIGURATION 0 +#define USB_CFG_DESCR_PROPS_STRINGS 0 +#define USB_CFG_DESCR_PROPS_STRING_0 0 +#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0 +#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0 +#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0 +#define USB_CFG_DESCR_PROPS_HID 0 +#define USB_CFG_DESCR_PROPS_HID_REPORT USB_PROP_IS_DYNAMIC +#define USB_CFG_DESCR_PROPS_UNKNOWN 0 + +/* ----------------------- Optional MCU Description ------------------------ */ + +/* The following configurations have working defaults in usbdrv.h. You + * usually don't need to set them explicitly. Only if you want to run + * the driver on a device which is not yet supported or with a compiler + * which is not fully supported (such as IAR C) or if you use a differnt + * interrupt than INT0, you may have to define some of these. + */ +/* #define USB_INTR_CFG MCUCR */ +/* #define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) */ +/* #define USB_INTR_CFG_CLR 0 */ +/* #define USB_INTR_ENABLE GIMSK */ +/* #define USB_INTR_ENABLE_BIT INT0 */ +/* #define USB_INTR_PENDING GIFR */ +/* #define USB_INTR_PENDING_BIT INTF0 */ +/* #define USB_INTR_VECTOR SIG_INTERRUPT0 */ + + #if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define USB_INTR_CFG PCMSK +#define USB_INTR_CFG_SET (1<len & 0x10){ /* packet buffer was empty */ + txStatus->buffer[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */ + }else{ + txStatus->len = USBPID_NAK; /* avoid sending outdated (overwritten) interrupt data */ + } + p = txStatus->buffer + 1; + i = len; + do{ /* if len == 0, we still copy 1 byte, but that's no problem */ + *p++ = *data++; + }while(--i > 0); /* loop control at the end is 2 bytes shorter than at beginning */ + usbCrc16Append(&txStatus->buffer[1], len); + txStatus->len = len + 4; /* len must be given including sync byte */ + DBG2(0x21 + (((int)txStatus >> 3) & 3), txStatus->buffer, len + 3); +} + +USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len) +{ + usbGenericSetInterrupt(data, len, &usbTxStatus1); +} +#endif + +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 +USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len) +{ + usbGenericSetInterrupt(data, len, &usbTxStatus3); +} +#endif +#endif /* USB_CFG_SUPPRESS_INTR_CODE */ + +/* ------------------ utilities for code following below ------------------- */ + +/* Use defines for the switch statement so that we can choose between an + * if()else if() and a switch/case based implementation. switch() is more + * efficient for a LARGE set of sequential choices, if() is better in all other + * cases. + */ +#if USB_CFG_USE_SWITCH_STATEMENT +# define SWITCH_START(cmd) switch(cmd){{ +# define SWITCH_CASE(value) }break; case (value):{ +# define SWITCH_CASE2(v1,v2) }break; case (v1): case(v2):{ +# define SWITCH_CASE3(v1,v2,v3) }break; case (v1): case(v2): case(v3):{ +# define SWITCH_DEFAULT }break; default:{ +# define SWITCH_END }} +#else +# define SWITCH_START(cmd) {uchar _cmd = cmd; if(0){ +# define SWITCH_CASE(value) }else if(_cmd == (value)){ +# define SWITCH_CASE2(v1,v2) }else if(_cmd == (v1) || _cmd == (v2)){ +# define SWITCH_CASE3(v1,v2,v3) }else if(_cmd == (v1) || _cmd == (v2) || (_cmd == v3)){ +# define SWITCH_DEFAULT }else{ +# define SWITCH_END }} +#endif + +#ifndef USB_RX_USER_HOOK +#define USB_RX_USER_HOOK(data, len) +#endif +#ifndef USB_SET_ADDRESS_HOOK +#define USB_SET_ADDRESS_HOOK() +#endif + +/* ------------------------------------------------------------------------- */ + +/* We use if() instead of #if in the macro below because #if can't be used + * in macros and the compiler optimizes constant conditions anyway. + * This may cause problems with undefined symbols if compiled without + * optimizing! + */ +#define GET_DESCRIPTOR(cfgProp, staticName) \ + if(cfgProp){ \ + if((cfgProp) & USB_PROP_IS_RAM) \ + flags = 0; \ + if((cfgProp) & USB_PROP_IS_DYNAMIC){ \ + len = usbFunctionDescriptor(rq); \ + }else{ \ + len = USB_PROP_LENGTH(cfgProp); \ + usbMsgPtr = (uchar *)(staticName); \ + } \ + } + +/* usbDriverDescriptor() is similar to usbFunctionDescriptor(), but used + * internally for all types of descriptors. + */ +static inline usbMsgLen_t usbDriverDescriptor(usbRequest_t *rq) +{ +usbMsgLen_t len = 0; +uchar flags = USB_FLG_MSGPTR_IS_ROM; + + SWITCH_START(rq->wValue.bytes[1]) + SWITCH_CASE(USBDESCR_DEVICE) /* 1 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_DEVICE, usbDescriptorDevice) + SWITCH_CASE(USBDESCR_CONFIG) /* 2 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_CONFIGURATION, usbDescriptorConfiguration) + SWITCH_CASE(USBDESCR_STRING) /* 3 */ +#if USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC + if(USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_RAM) + flags = 0; + len = usbFunctionDescriptor(rq); +#else /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */ + SWITCH_START(rq->wValue.bytes[0]) + SWITCH_CASE(0) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_0, usbDescriptorString0) + SWITCH_CASE(1) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_VENDOR, usbDescriptorStringVendor) + SWITCH_CASE(2) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_PRODUCT, usbDescriptorStringDevice) + SWITCH_CASE(3) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER, usbDescriptorStringSerialNumber) + SWITCH_DEFAULT + if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){ + len = usbFunctionDescriptor(rq); + } + SWITCH_END +#endif /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */ +#if USB_CFG_DESCR_PROPS_HID_REPORT /* only support HID descriptors if enabled */ + SWITCH_CASE(USBDESCR_HID) /* 0x21 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID, usbDescriptorConfiguration + 18) + SWITCH_CASE(USBDESCR_HID_REPORT)/* 0x22 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID_REPORT, usbDescriptorHidReport) +#endif + SWITCH_DEFAULT + if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){ + len = usbFunctionDescriptor(rq); + } + SWITCH_END + usbMsgFlags = flags; + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbDriverSetup() is similar to usbFunctionSetup(), but it's used for + * standard requests instead of class and custom requests. + */ +static inline usbMsgLen_t usbDriverSetup(usbRequest_t *rq) +{ +uchar len = 0, *dataPtr = usbTxBuf + 9; /* there are 2 bytes free space at the end of the buffer */ +uchar value = rq->wValue.bytes[0]; +#if USB_CFG_IMPLEMENT_HALT +uchar index = rq->wIndex.bytes[0]; +#endif + + dataPtr[0] = 0; /* default reply common to USBRQ_GET_STATUS and USBRQ_GET_INTERFACE */ + SWITCH_START(rq->bRequest) + SWITCH_CASE(USBRQ_GET_STATUS) /* 0 */ + uchar recipient = rq->bmRequestType & USBRQ_RCPT_MASK; /* assign arith ops to variables to enforce byte size */ + if(USB_CFG_IS_SELF_POWERED && recipient == USBRQ_RCPT_DEVICE) + dataPtr[0] = USB_CFG_IS_SELF_POWERED; +#if USB_CFG_IMPLEMENT_HALT + if(recipient == USBRQ_RCPT_ENDPOINT && index == 0x81) /* request status for endpoint 1 */ + dataPtr[0] = usbTxLen1 == USBPID_STALL; +#endif + dataPtr[1] = 0; + len = 2; +#if USB_CFG_IMPLEMENT_HALT + SWITCH_CASE2(USBRQ_CLEAR_FEATURE, USBRQ_SET_FEATURE) /* 1, 3 */ + if(value == 0 && index == 0x81){ /* feature 0 == HALT for endpoint == 1 */ + usbTxLen1 = rq->bRequest == USBRQ_CLEAR_FEATURE ? USBPID_NAK : USBPID_STALL; + usbResetDataToggling(); + } +#endif + SWITCH_CASE(USBRQ_SET_ADDRESS) /* 5 */ + usbNewDeviceAddr = value; + USB_SET_ADDRESS_HOOK(); + SWITCH_CASE(USBRQ_GET_DESCRIPTOR) /* 6 */ + len = usbDriverDescriptor(rq); + goto skipMsgPtrAssignment; + SWITCH_CASE(USBRQ_GET_CONFIGURATION) /* 8 */ + dataPtr = &usbConfiguration; /* send current configuration value */ + len = 1; + SWITCH_CASE(USBRQ_SET_CONFIGURATION) /* 9 */ + usbConfiguration = value; + usbResetStall(); + SWITCH_CASE(USBRQ_GET_INTERFACE) /* 10 */ + len = 1; +#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE + SWITCH_CASE(USBRQ_SET_INTERFACE) /* 11 */ + usbResetDataToggling(); + usbResetStall(); +#endif + SWITCH_DEFAULT /* 7=SET_DESCRIPTOR, 12=SYNC_FRAME */ + /* Should we add an optional hook here? */ + SWITCH_END + usbMsgPtr = dataPtr; +skipMsgPtrAssignment: + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbProcessRx() is called for every message received by the interrupt + * routine. It distinguishes between SETUP and DATA packets and processes + * them accordingly. + */ +static inline void usbProcessRx(uchar *data, uchar len) +{ + usbRequest_t *rq = (usbRequest_t *)((void *)data); + +/* usbRxToken can be: + * 0x2d 00101101 (USBPID_SETUP for setup data) + * 0xe1 11100001 (USBPID_OUT: data phase of setup transfer) + * 0...0x0f for OUT on endpoint X + */ + DBG2(0x10 + (usbRxToken & 0xf), data, len + 2); /* SETUP=1d, SETUP-DATA=11, OUTx=1x */ + USB_RX_USER_HOOK(data, len) +#if USB_CFG_IMPLEMENT_FN_WRITEOUT + if(usbRxToken < 0x10){ /* OUT to endpoint != 0: endpoint number in usbRxToken */ + usbFunctionWriteOut(data, len); + return; + } +#endif + if(usbRxToken == (uchar)USBPID_SETUP){ + if(len != 8) /* Setup size must be always 8 bytes. Ignore otherwise. */ + return; + usbMsgLen_t replyLen; + usbTxBuf[0] = USBPID_DATA0; /* initialize data toggling */ + usbTxLen = USBPID_NAK; /* abort pending transmit */ + usbMsgFlags = 0; + uchar type = rq->bmRequestType & USBRQ_TYPE_MASK; + if(type != USBRQ_TYPE_STANDARD){ /* standard requests are handled by driver */ + replyLen = usbFunctionSetup(data); + }else{ + replyLen = usbDriverSetup(rq); + } +#if USB_CFG_IMPLEMENT_FN_READ || USB_CFG_IMPLEMENT_FN_WRITE + if(replyLen == USB_NO_MSG){ /* use user-supplied read/write function */ + /* do some conditioning on replyLen, but on IN transfers only */ + if((rq->bmRequestType & USBRQ_DIR_MASK) != USBRQ_DIR_HOST_TO_DEVICE){ + if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */ + replyLen = rq->wLength.bytes[0]; + }else{ + replyLen = rq->wLength.word; + } + } + usbMsgFlags = USB_FLG_USE_USER_RW; + }else /* The 'else' prevents that we limit a replyLen of USB_NO_MSG to the maximum transfer len. */ +#endif + if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */ + if(!rq->wLength.bytes[1] && replyLen > rq->wLength.bytes[0]) /* limit length to max */ + replyLen = rq->wLength.bytes[0]; + }else{ + if(replyLen > rq->wLength.word) /* limit length to max */ + replyLen = rq->wLength.word; + } + usbMsgLen = replyLen; + }else{ /* usbRxToken must be USBPID_OUT, which means data phase of setup (control-out) */ +#if USB_CFG_IMPLEMENT_FN_WRITE + if(usbMsgFlags & USB_FLG_USE_USER_RW){ + uchar rval = usbFunctionWrite(data, len); + if(rval == 0xff){ /* an error occurred */ + usbTxLen = USBPID_STALL; + }else if(rval != 0){ /* This was the final package */ + usbMsgLen = 0; /* answer with a zero-sized data packet */ + } + } +#endif + } +} + +/* ------------------------------------------------------------------------- */ + +/* This function is similar to usbFunctionRead(), but it's also called for + * data handled automatically by the driver (e.g. descriptor reads). + */ +static uchar usbDeviceRead(uchar *data, uchar len) +{ + if(len > 0){ /* don't bother app with 0 sized reads */ +#if USB_CFG_IMPLEMENT_FN_READ + if(usbMsgFlags & USB_FLG_USE_USER_RW){ + len = usbFunctionRead(data, len); + }else +#endif + { + uchar i = len, *r = usbMsgPtr; + if(usbMsgFlags & USB_FLG_MSGPTR_IS_ROM){ /* ROM data */ + do{ + uchar c = USB_READ_FLASH(r); /* assign to char size variable to enforce byte ops */ + *data++ = c; + r++; + }while(--i); + }else{ /* RAM data */ + do{ + *data++ = *r++; + }while(--i); + } + usbMsgPtr = r; + } + } + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbBuildTxBlock() is called when we have data to transmit and the + * interrupt routine's transmit buffer is empty. + */ +static inline void usbBuildTxBlock(void) +{ +usbMsgLen_t wantLen; +uchar len; + + wantLen = usbMsgLen; + if(wantLen > 8) + wantLen = 8; + usbMsgLen -= wantLen; + usbTxBuf[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* DATA toggling */ + len = usbDeviceRead(usbTxBuf + 1, wantLen); + if(len <= 8){ /* valid data packet */ + usbCrc16Append(&usbTxBuf[1], len); + len += 4; /* length including sync byte */ + if(len < 12) /* a partial package identifies end of message */ + usbMsgLen = USB_NO_MSG; + }else{ + len = USBPID_STALL; /* stall the endpoint */ + usbMsgLen = USB_NO_MSG; + } + usbTxLen = len; + DBG2(0x20, usbTxBuf, len-1); +} + +/* ------------------------------------------------------------------------- */ + +static inline void usbHandleResetHook(uchar notResetState) +{ +#ifdef USB_RESET_HOOK +static uchar wasReset; +uchar isReset = !notResetState; + + if(wasReset != isReset){ + USB_RESET_HOOK(isReset); + wasReset = isReset; + } +#endif +} + +/* ------------------------------------------------------------------------- */ + +USB_PUBLIC void usbPoll(void) +{ +schar len; +uchar i; + + len = usbRxLen - 3; + if(len >= 0){ +/* We could check CRC16 here -- but ACK has already been sent anyway. If you + * need data integrity checks with this driver, check the CRC in your app + * code and report errors back to the host. Since the ACK was already sent, + * retries must be handled on application level. + * unsigned crc = usbCrc16(buffer + 1, usbRxLen - 3); + */ + usbProcessRx(usbRxBuf + USB_BUFSIZE + 1 - usbInputBufOffset, len); +#if USB_CFG_HAVE_FLOWCONTROL + if(usbRxLen > 0) /* only mark as available if not inactivated */ + usbRxLen = 0; +#else + usbRxLen = 0; /* mark rx buffer as available */ +#endif + } + if(usbTxLen & 0x10){ /* transmit system idle */ + if(usbMsgLen != USB_NO_MSG){ /* transmit data pending? */ + usbBuildTxBlock(); + } + } + for(i = 20; i > 0; i--){ + uchar usbLineStatus = USBIN & USBMASK; + if(usbLineStatus != 0) /* SE0 has ended */ + goto isNotReset; + } + /* RESET condition, called multiple times during reset */ + usbNewDeviceAddr = 0; + usbDeviceAddr = 0; + usbResetStall(); + DBG1(0xff, 0, 0); +isNotReset: + usbHandleResetHook(i); +} + +/* ------------------------------------------------------------------------- */ + +USB_PUBLIC void usbInit(void) +{ +#if USB_INTR_CFG_SET != 0 + USB_INTR_CFG |= USB_INTR_CFG_SET; +#endif +#if USB_INTR_CFG_CLR != 0 + USB_INTR_CFG &= ~(USB_INTR_CFG_CLR); +#endif + USB_INTR_ENABLE |= (1 << USB_INTR_ENABLE_BIT); + usbResetDataToggling(); +#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE + usbTxLen1 = USBPID_NAK; +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 + usbTxLen3 = USBPID_NAK; +#endif +#endif +} + +/* ------------------------------------------------------------------------- */ diff --git a/hardware/digistump/avr/libraries/DigiJoystick/usbdrv.h b/hardware/digistump/avr/libraries/DigiJoystick/usbdrv.h new file mode 100644 index 0000000..898a091 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/usbdrv.h @@ -0,0 +1,766 @@ +/* Name: usbdrv.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2004-12-29 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbdrv.h 769 2009-08-22 11:49:05Z cs $ + */ + +#ifndef __usbdrv_h_included__ +#define __usbdrv_h_included__ + +#include "usbconfig.h" +#include "usbportability.h" + +/* +Hardware Prerequisites: +======================= +USB lines D+ and D- MUST be wired to the same I/O port. We recommend that D+ +triggers the interrupt (best achieved by using INT0 for D+), but it is also +possible to trigger the interrupt from D-. If D- is used, interrupts are also +triggered by SOF packets. D- requires a pull-up of 1.5k to +3.5V (and the +device must be powered at 3.5V) to identify as low-speed USB device. A +pull-down or pull-up of 1M SHOULD be connected from D+ to +3.5V to prevent +interference when no USB master is connected. If you use Zener diodes to limit +the voltage on D+ and D-, you MUST use a pull-down resistor, not a pull-up. +We use D+ as interrupt source and not D- because it does not trigger on +keep-alive and RESET states. If you want to count keep-alive events with +USB_COUNT_SOF, you MUST use D- as an interrupt source. + +As a compile time option, the 1.5k pull-up resistor on D- can be made +switchable to allow the device to disconnect at will. See the definition of +usbDeviceConnect() and usbDeviceDisconnect() further down in this file. + +Please adapt the values in usbconfig.h according to your hardware! + +The device MUST be clocked at exactly 12 MHz, 15 MHz, 16 MHz or 20 MHz +or at 12.8 MHz resp. 16.5 MHz +/- 1%. See usbconfig-prototype.h for details. + + +Limitations: +============ +Robustness with respect to communication errors: +The driver assumes error-free communication. It DOES check for errors in +the PID, but does NOT check bit stuffing errors, SE0 in middle of a byte, +token CRC (5 bit) and data CRC (16 bit). CRC checks can not be performed due +to timing constraints: We must start sending a reply within 7 bit times. +Bit stuffing and misplaced SE0 would have to be checked in real-time, but CPU +performance does not permit that. The driver does not check Data0/Data1 +toggling, but application software can implement the check. + +Input characteristics: +Since no differential receiver circuit is used, electrical interference +robustness may suffer. The driver samples only one of the data lines with +an ordinary I/O pin's input characteristics. However, since this is only a +low speed USB implementation and the specification allows for 8 times the +bit rate over the same hardware, we should be on the safe side. Even the spec +requires detection of asymmetric states at high bit rate for SE0 detection. + +Number of endpoints: +The driver supports the following endpoints: + +- Endpoint 0, the default control endpoint. +- Any number of interrupt- or bulk-out endpoints. The data is sent to + usbFunctionWriteOut() and USB_CFG_IMPLEMENT_FN_WRITEOUT must be defined + to 1 to activate this feature. The endpoint number can be found in the + global variable 'usbRxToken'. +- One default interrupt- or bulk-in endpoint. This endpoint is used for + interrupt- or bulk-in transfers which are not handled by any other endpoint. + You must define USB_CFG_HAVE_INTRIN_ENDPOINT in order to activate this + feature and call usbSetInterrupt() to send interrupt/bulk data. +- One additional interrupt- or bulk-in endpoint. This was endpoint 3 in + previous versions of this driver but can now be configured to any endpoint + number. You must define USB_CFG_HAVE_INTRIN_ENDPOINT3 in order to activate + this feature and call usbSetInterrupt3() to send interrupt/bulk data. The + endpoint number can be set with USB_CFG_EP3_NUMBER. + +Please note that the USB standard forbids bulk endpoints for low speed devices! +Most operating systems allow them anyway, but the AVR will spend 90% of the CPU +time in the USB interrupt polling for bulk data. + +Maximum data payload: +Data payload of control in and out transfers may be up to 254 bytes. In order +to accept payload data of out transfers, you need to implement +'usbFunctionWrite()'. + +USB Suspend Mode supply current: +The USB standard limits power consumption to 500uA when the bus is in suspend +mode. This is not a problem for self-powered devices since they don't need +bus power anyway. Bus-powered devices can achieve this only by putting the +CPU in sleep mode. The driver does not implement suspend handling by itself. +However, the application may implement activity monitoring and wakeup from +sleep. The host sends regular SE0 states on the bus to keep it active. These +SE0 states can be detected by using D- as the interrupt source. Define +USB_COUNT_SOF to 1 and use the global variable usbSofCount to check for bus +activity. + +Operation without an USB master: +The driver behaves neutral without connection to an USB master if D- reads +as 1. To avoid spurious interrupts, we recommend a high impedance (e.g. 1M) +pull-down or pull-up resistor on D+ (interrupt). If Zener diodes are used, +use a pull-down. If D- becomes statically 0, the driver may block in the +interrupt routine. + +Interrupt latency: +The application must ensure that the USB interrupt is not disabled for more +than 25 cycles (this is for 12 MHz, faster clocks allow longer latency). +This implies that all interrupt routines must either be declared as "INTERRUPT" +instead of "SIGNAL" (see "avr/signal.h") or that they are written in assembler +with "sei" as the first instruction. + +Maximum interrupt duration / CPU cycle consumption: +The driver handles all USB communication during the interrupt service +routine. The routine will not return before an entire USB message is received +and the reply is sent. This may be up to ca. 1200 cycles @ 12 MHz (= 100us) if +the host conforms to the standard. The driver will consume CPU cycles for all +USB messages, even if they address another (low-speed) device on the same bus. + +*/ + +/* ------------------------------------------------------------------------- */ +/* --------------------------- Module Interface ---------------------------- */ +/* ------------------------------------------------------------------------- */ + +#define USBDRV_VERSION 20090822 +/* This define uniquely identifies a driver version. It is a decimal number + * constructed from the driver's release date in the form YYYYMMDD. If the + * driver's behavior or interface changes, you can use this constant to + * distinguish versions. If it is not defined, the driver's release date is + * older than 2006-01-25. + */ + + +#ifndef USB_PUBLIC +#define USB_PUBLIC +#endif +/* USB_PUBLIC is used as declaration attribute for all functions exported by + * the USB driver. The default is no attribute (see above). You may define it + * to static either in usbconfig.h or from the command line if you include + * usbdrv.c instead of linking against it. Including the C module of the driver + * directly in your code saves a couple of bytes in flash memory. + */ + +#ifndef __ASSEMBLER__ +#ifndef uchar +#define uchar unsigned char +#endif +#ifndef schar +#define schar signed char +#endif +/* shortcuts for well defined 8 bit integer types */ + +#if USB_CFG_LONG_TRANSFERS /* if more than 254 bytes transfer size required */ +# define usbMsgLen_t unsigned +#else +# define usbMsgLen_t uchar +#endif +/* usbMsgLen_t is the data type used for transfer lengths. By default, it is + * defined to uchar, allowing a maximum of 254 bytes (255 is reserved for + * USB_NO_MSG below). If the usbconfig.h defines USB_CFG_LONG_TRANSFERS to 1, + * a 16 bit data type is used, allowing up to 16384 bytes (the rest is used + * for flags in the descriptor configuration). + */ +#define USB_NO_MSG ((usbMsgLen_t)-1) /* constant meaning "no message" */ + +struct usbRequest; /* forward declaration */ + +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbInit(void); +/* This function must be called before interrupts are enabled and the main + * loop is entered. We exepct that the PORT and DDR bits for D+ and D- have + * not been changed from their default status (which is 0). If you have changed + * them, set both back to 0 (configure them as input with no internal pull-up). + */ +USB_PUBLIC void usbPoll(void); +/* This function must be called at regular intervals from the main loop. + * Maximum delay between calls is somewhat less than 50ms (USB timeout for + * accepting a Setup message). Otherwise the device will not be recognized. + * Please note that debug outputs through the UART take ~ 0.5ms per byte + * at 19200 bps. + */ +#ifdef __cplusplus +} // extern "C" +#endif +extern uchar *usbMsgPtr; +/* This variable may be used to pass transmit data to the driver from the + * implementation of usbFunctionWrite(). It is also used internally by the + * driver for standard control requests. + */ +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC usbMsgLen_t usbFunctionSetup(uchar data[8]); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function is called when the driver receives a SETUP transaction from + * the host which is not answered by the driver itself (in practice: class and + * vendor requests). All control transfers start with a SETUP transaction where + * the host communicates the parameters of the following (optional) data + * transfer. The SETUP data is available in the 'data' parameter which can + * (and should) be casted to 'usbRequest_t *' for a more user-friendly access + * to parameters. + * + * If the SETUP indicates a control-in transfer, you should provide the + * requested data to the driver. There are two ways to transfer this data: + * (1) Set the global pointer 'usbMsgPtr' to the base of the static RAM data + * block and return the length of the data in 'usbFunctionSetup()'. The driver + * will handle the rest. Or (2) return USB_NO_MSG in 'usbFunctionSetup()'. The + * driver will then call 'usbFunctionRead()' when data is needed. See the + * documentation for usbFunctionRead() for details. + * + * If the SETUP indicates a control-out transfer, the only way to receive the + * data from the host is through the 'usbFunctionWrite()' call. If you + * implement this function, you must return USB_NO_MSG in 'usbFunctionSetup()' + * to indicate that 'usbFunctionWrite()' should be used. See the documentation + * of this function for more information. If you just want to ignore the data + * sent by the host, return 0 in 'usbFunctionSetup()'. + * + * Note that calls to the functions usbFunctionRead() and usbFunctionWrite() + * are only done if enabled by the configuration in usbconfig.h. + */ +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC usbMsgLen_t usbFunctionDescriptor(struct usbRequest *rq); +#ifdef __cplusplus +} // extern "C" +#endif +/* You need to implement this function ONLY if you provide USB descriptors at + * runtime (which is an expert feature). It is very similar to + * usbFunctionSetup() above, but it is called only to request USB descriptor + * data. See the documentation of usbFunctionSetup() above for more info. + */ +#if USB_CFG_HAVE_INTRIN_ENDPOINT +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function sets the message which will be sent during the next interrupt + * IN transfer. The message is copied to an internal buffer and must not exceed + * a length of 8 bytes. The message may be 0 bytes long just to indicate the + * interrupt status to the host. + * If you need to transfer more bytes, use a control read after the interrupt. + */ +#define usbInterruptIsReady() (usbTxLen1 & 0x10) +/* This macro indicates whether the last interrupt message has already been + * sent. If you set a new interrupt message before the old was sent, the + * message already buffered will be lost. + */ +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 +USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len); +#define usbInterruptIsReady3() (usbTxLen3 & 0x10) +/* Same as above for endpoint 3 */ +#endif +#endif /* USB_CFG_HAVE_INTRIN_ENDPOINT */ +#if USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH /* simplified interface for backward compatibility */ +#define usbHidReportDescriptor usbDescriptorHidReport +/* should be declared as: PROGMEM char usbHidReportDescriptor[]; */ +/* If you implement an HID device, you need to provide a report descriptor. + * The HID report descriptor syntax is a bit complex. If you understand how + * report descriptors are constructed, we recommend that you use the HID + * Descriptor Tool from usb.org, see http://www.usb.org/developers/hidpage/. + * Otherwise you should probably start with a working example. + */ +#endif /* USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH */ +#if USB_CFG_IMPLEMENT_FN_WRITE +USB_PUBLIC uchar usbFunctionWrite(uchar *data, uchar len); +/* This function is called by the driver to provide a control transfer's + * payload data (control-out). It is called in chunks of up to 8 bytes. The + * total count provided in the current control transfer can be obtained from + * the 'length' property in the setup data. If an error occurred during + * processing, return 0xff (== -1). The driver will answer the entire transfer + * with a STALL token in this case. If you have received the entire payload + * successfully, return 1. If you expect more data, return 0. If you don't + * know whether the host will send more data (you should know, the total is + * provided in the usbFunctionSetup() call!), return 1. + * NOTE: If you return 0xff for STALL, 'usbFunctionWrite()' may still be called + * for the remaining data. You must continue to return 0xff for STALL in these + * calls. + * In order to get usbFunctionWrite() called, define USB_CFG_IMPLEMENT_FN_WRITE + * to 1 in usbconfig.h and return 0xff in usbFunctionSetup().. + */ +#endif /* USB_CFG_IMPLEMENT_FN_WRITE */ +#if USB_CFG_IMPLEMENT_FN_READ +USB_PUBLIC uchar usbFunctionRead(uchar *data, uchar len); +/* This function is called by the driver to ask the application for a control + * transfer's payload data (control-in). It is called in chunks of up to 8 + * bytes each. You should copy the data to the location given by 'data' and + * return the actual number of bytes copied. If you return less than requested, + * the control-in transfer is terminated. If you return 0xff, the driver aborts + * the transfer with a STALL token. + * In order to get usbFunctionRead() called, define USB_CFG_IMPLEMENT_FN_READ + * to 1 in usbconfig.h and return 0xff in usbFunctionSetup().. + */ +#endif /* USB_CFG_IMPLEMENT_FN_READ */ + +extern uchar usbRxToken; /* may be used in usbFunctionWriteOut() below */ +#if USB_CFG_IMPLEMENT_FN_WRITEOUT +USB_PUBLIC void usbFunctionWriteOut(uchar *data, uchar len); +/* This function is called by the driver when data is received on an interrupt- + * or bulk-out endpoint. The endpoint number can be found in the global + * variable usbRxToken. You must define USB_CFG_IMPLEMENT_FN_WRITEOUT to 1 in + * usbconfig.h to get this function called. + */ +#endif /* USB_CFG_IMPLEMENT_FN_WRITEOUT */ +#ifdef USB_CFG_PULLUP_IOPORTNAME +#define usbDeviceConnect() ((USB_PULLUP_DDR |= (1<device, 1=device->host + * t ..... type: 0=standard, 1=class, 2=vendor, 3=reserved + * r ..... recipient: 0=device, 1=interface, 2=endpoint, 3=other + */ + +/* USB setup recipient values */ +#define USBRQ_RCPT_MASK 0x1f +#define USBRQ_RCPT_DEVICE 0 +#define USBRQ_RCPT_INTERFACE 1 +#define USBRQ_RCPT_ENDPOINT 2 + +/* USB request type values */ +#define USBRQ_TYPE_MASK 0x60 +#define USBRQ_TYPE_STANDARD (0<<5) +#define USBRQ_TYPE_CLASS (1<<5) +#define USBRQ_TYPE_VENDOR (2<<5) + +/* USB direction values: */ +#define USBRQ_DIR_MASK 0x80 +#define USBRQ_DIR_HOST_TO_DEVICE (0<<7) +#define USBRQ_DIR_DEVICE_TO_HOST (1<<7) + +/* USB Standard Requests */ +#define USBRQ_GET_STATUS 0 +#define USBRQ_CLEAR_FEATURE 1 +#define USBRQ_SET_FEATURE 3 +#define USBRQ_SET_ADDRESS 5 +#define USBRQ_GET_DESCRIPTOR 6 +#define USBRQ_SET_DESCRIPTOR 7 +#define USBRQ_GET_CONFIGURATION 8 +#define USBRQ_SET_CONFIGURATION 9 +#define USBRQ_GET_INTERFACE 10 +#define USBRQ_SET_INTERFACE 11 +#define USBRQ_SYNCH_FRAME 12 + +/* USB descriptor constants */ +#define USBDESCR_DEVICE 1 +#define USBDESCR_CONFIG 2 +#define USBDESCR_STRING 3 +#define USBDESCR_INTERFACE 4 +#define USBDESCR_ENDPOINT 5 +#define USBDESCR_HID 0x21 +#define USBDESCR_HID_REPORT 0x22 +#define USBDESCR_HID_PHYS 0x23 + +//#define USBATTR_BUSPOWER 0x80 // USB 1.1 does not define this value any more +#define USBATTR_SELFPOWER 0x40 +#define USBATTR_REMOTEWAKE 0x20 + +/* USB HID Requests */ +#define USBRQ_HID_GET_REPORT 0x01 +#define USBRQ_HID_GET_IDLE 0x02 +#define USBRQ_HID_GET_PROTOCOL 0x03 +#define USBRQ_HID_SET_REPORT 0x09 +#define USBRQ_HID_SET_IDLE 0x0a +#define USBRQ_HID_SET_PROTOCOL 0x0b + +/* ------------------------------------------------------------------------- */ + +#endif /* __usbdrv_h_included__ */ diff --git a/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm.S b/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm.S new file mode 100644 index 0000000..bad72f0 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm.S @@ -0,0 +1,395 @@ +/* Name: usbdrvasm.S + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2007-06-13 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + */ + +/* +General Description: +This module is the assembler part of the USB driver. This file contains +general code (preprocessor acrobatics and CRC computation) and then includes +the file appropriate for the given clock rate. +*/ +#ifdef __SFR_OFFSET +#undef __SFR_OFFSET +#endif + +#define __SFR_OFFSET 0 /* used by avr-libc's register definitions */ +#include "usbportability.h" +#include "usbdrv.h" /* for common defs */ + +/* register names */ +#define x1 r16 +#define x2 r17 +#define shift r18 +#define cnt r19 +#define x3 r20 +#define x4 r21 +#define x5 r22 +#define bitcnt x5 +#define phase x4 +#define leap x4 + +/* Some assembler dependent definitions and declarations: */ + +#ifdef __IAR_SYSTEMS_ASM__ + extern usbRxBuf, usbDeviceAddr, usbNewDeviceAddr, usbInputBufOffset + extern usbCurrentTok, usbRxLen, usbRxToken, usbTxLen + extern usbTxBuf, usbTxStatus1, usbTxStatus3 +# if USB_COUNT_SOF + extern usbSofCount +# endif + public usbCrc16 + public usbCrc16Append + + COMMON INTVEC +# ifndef USB_INTR_VECTOR + ORG INT0_vect +# else /* USB_INTR_VECTOR */ + ORG USB_INTR_VECTOR +# undef USB_INTR_VECTOR +# endif /* USB_INTR_VECTOR */ +# define USB_INTR_VECTOR usbInterruptHandler + rjmp USB_INTR_VECTOR + RSEG CODE + +#else /* __IAR_SYSTEMS_ASM__ */ + +# ifndef USB_INTR_VECTOR /* default to hardware interrupt INT0 */ +# ifdef INT0_vect +# define USB_INTR_VECTOR INT0_vect // this is the "new" define for the vector +# else +# define USB_INTR_VECTOR SIG_INTERRUPT0 // this is the "old" vector +# endif +# endif + .text + .global USB_INTR_VECTOR + .type USB_INTR_VECTOR, @function + .global usbCrc16 + .global usbCrc16Append +#endif /* __IAR_SYSTEMS_ASM__ */ + + +#if USB_INTR_PENDING < 0x40 /* This is an I/O address, use in and out */ +# define USB_LOAD_PENDING(reg) in reg, USB_INTR_PENDING +# define USB_STORE_PENDING(reg) out USB_INTR_PENDING, reg +#else /* It's a memory address, use lds and sts */ +# define USB_LOAD_PENDING(reg) lds reg, USB_INTR_PENDING +# define USB_STORE_PENDING(reg) sts USB_INTR_PENDING, reg +#endif + +#define usbTxLen1 usbTxStatus1 +#define usbTxBuf1 (usbTxStatus1 + 1) +#define usbTxLen3 usbTxStatus3 +#define usbTxBuf3 (usbTxStatus3 + 1) + + +;---------------------------------------------------------------------------- +; Utility functions +;---------------------------------------------------------------------------- + +#ifdef __IAR_SYSTEMS_ASM__ +/* Register assignments for usbCrc16 on IAR cc */ +/* Calling conventions on IAR: + * First parameter passed in r16/r17, second in r18/r19 and so on. + * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer) + * Result is passed in r16/r17 + * In case of the "tiny" memory model, pointers are only 8 bit with no + * padding. We therefore pass argument 1 as "16 bit unsigned". + */ +RTMODEL "__rt_version", "3" +/* The line above will generate an error if cc calling conventions change. + * The value "3" above is valid for IAR 4.10B/W32 + */ +# define argLen r18 /* argument 2 */ +# define argPtrL r16 /* argument 1 */ +# define argPtrH r17 /* argument 1 */ + +# define resCrcL r16 /* result */ +# define resCrcH r17 /* result */ + +# define ptrL ZL +# define ptrH ZH +# define ptr Z +# define byte r22 +# define bitCnt r19 +# define polyL r20 +# define polyH r21 +# define scratch r23 + +#else /* __IAR_SYSTEMS_ASM__ */ +/* Register assignments for usbCrc16 on gcc */ +/* Calling conventions on gcc: + * First parameter passed in r24/r25, second in r22/23 and so on. + * Callee must preserve r1-r17, r28/r29 + * Result is passed in r24/r25 + */ +# define argLen r22 /* argument 2 */ +# define argPtrL r24 /* argument 1 */ +# define argPtrH r25 /* argument 1 */ + +# define resCrcL r24 /* result */ +# define resCrcH r25 /* result */ + +# define ptrL XL +# define ptrH XH +# define ptr x +# define byte r18 +# define bitCnt r19 +# define polyL r20 +# define polyH r21 +# define scratch r23 + +#endif + +#if USB_USE_FAST_CRC + +; This implementation is faster, but has bigger code size +; Thanks to Slawomir Fras (BoskiDialer) for this code! +; It implements the following C pseudo-code: +; unsigned table(unsigned char x) +; { +; unsigned value; +; +; value = (unsigned)x << 6; +; value ^= (unsigned)x << 7; +; if(parity(x)) +; value ^= 0xc001; +; return value; +; } +; unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen) +; { +; unsigned crc = 0xffff; +; +; while(argLen--) +; crc = table(lo8(crc) ^ *argPtr++) ^ hi8(crc); +; return ~crc; +; } + +; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen); +; argPtr r24+25 / r16+r17 +; argLen r22 / r18 +; temp variables: +; byte r18 / r22 +; scratch r23 +; resCrc r24+r25 / r16+r17 +; ptr X / Z +usbCrc16: + mov ptrL, argPtrL + mov ptrH, argPtrH + ldi resCrcL, 0xFF + ldi resCrcH, 0xFF + rjmp usbCrc16LoopTest +usbCrc16ByteLoop: + ld byte, ptr+ + eor resCrcL, byte ; resCrcL is now 'x' in table() + mov byte, resCrcL ; compute parity of 'x' + swap byte + eor byte, resCrcL + mov scratch, byte + lsr byte + lsr byte + eor byte, scratch + inc byte + lsr byte + andi byte, 1 ; byte is now parity(x) + mov scratch, resCrcL + mov resCrcL, resCrcH + eor resCrcL, byte ; low byte of if(parity(x)) value ^= 0xc001; + neg byte + andi byte, 0xc0 + mov resCrcH, byte ; high byte of if(parity(x)) value ^= 0xc001; + clr byte + lsr scratch + ror byte + eor resCrcH, scratch + eor resCrcL, byte + lsr scratch + ror byte + eor resCrcH, scratch + eor resCrcL, byte +usbCrc16LoopTest: + subi argLen, 1 + brsh usbCrc16ByteLoop + com resCrcL + com resCrcH + ret + +#else /* USB_USE_FAST_CRC */ + +; This implementation is slower, but has less code size +; +; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen); +; argPtr r24+25 / r16+r17 +; argLen r22 / r18 +; temp variables: +; byte r18 / r22 +; bitCnt r19 +; poly r20+r21 +; scratch r23 +; resCrc r24+r25 / r16+r17 +; ptr X / Z +usbCrc16: + mov ptrL, argPtrL + mov ptrH, argPtrH + ldi resCrcL, 0 + ldi resCrcH, 0 + ldi polyL, lo8(0xa001) + ldi polyH, hi8(0xa001) + com argLen ; argLen = -argLen - 1: modified loop to ensure that carry is set + ldi bitCnt, 0 ; loop counter with starnd condition = end condition + rjmp usbCrcLoopEntry +usbCrcByteLoop: + ld byte, ptr+ + eor resCrcL, byte +usbCrcBitLoop: + ror resCrcH ; carry is always set here (see brcs jumps to here) + ror resCrcL + brcs usbCrcNoXor + eor resCrcL, polyL + eor resCrcH, polyH +usbCrcNoXor: + subi bitCnt, 224 ; (8 * 224) % 256 = 0; this loop iterates 8 times + brcs usbCrcBitLoop +usbCrcLoopEntry: + subi argLen, -1 + brcs usbCrcByteLoop +usbCrcReady: + ret +; Thanks to Reimar Doeffinger for optimizing this CRC routine! + +#endif /* USB_USE_FAST_CRC */ + +; extern unsigned usbCrc16Append(unsigned char *data, unsigned char len); +usbCrc16Append: + rcall usbCrc16 + st ptr+, resCrcL + st ptr+, resCrcH + ret + +#undef argLen +#undef argPtrL +#undef argPtrH +#undef resCrcL +#undef resCrcH +#undef ptrL +#undef ptrH +#undef ptr +#undef byte +#undef bitCnt +#undef polyL +#undef polyH +#undef scratch + + +#if USB_CFG_HAVE_MEASURE_FRAME_LENGTH +#ifdef __IAR_SYSTEMS_ASM__ +/* Register assignments for usbMeasureFrameLength on IAR cc */ +/* Calling conventions on IAR: + * First parameter passed in r16/r17, second in r18/r19 and so on. + * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer) + * Result is passed in r16/r17 + * In case of the "tiny" memory model, pointers are only 8 bit with no + * padding. We therefore pass argument 1 as "16 bit unsigned". + */ +# define resL r16 +# define resH r17 +# define cnt16L r30 +# define cnt16H r31 +# define cntH r18 + +#else /* __IAR_SYSTEMS_ASM__ */ +/* Register assignments for usbMeasureFrameLength on gcc */ +/* Calling conventions on gcc: + * First parameter passed in r24/r25, second in r22/23 and so on. + * Callee must preserve r1-r17, r28/r29 + * Result is passed in r24/r25 + */ +# define resL r24 +# define resH r25 +# define cnt16L r24 +# define cnt16H r25 +# define cntH r26 +#endif +# define cnt16 cnt16L + +; extern unsigned usbMeasurePacketLength(void); +; returns time between two idle strobes in multiples of 7 CPU clocks +.global usbMeasureFrameLength +usbMeasureFrameLength: + ldi cntH, 6 ; wait ~ 10 ms for D- == 0 + clr cnt16L + clr cnt16H +usbMFTime16: + dec cntH + breq usbMFTimeout +usbMFWaitStrobe: ; first wait for D- == 0 (idle strobe) + sbiw cnt16, 1 ;[0] [6] + breq usbMFTime16 ;[2] + sbic USBIN, USBMINUS ;[3] + rjmp usbMFWaitStrobe ;[4] +usbMFWaitIdle: ; then wait until idle again + sbis USBIN, USBMINUS ;1 wait for D- == 1 + rjmp usbMFWaitIdle ;2 + ldi cnt16L, 1 ;1 represents cycles so far + clr cnt16H ;1 +usbMFWaitLoop: + in cntH, USBIN ;[0] [7] + adiw cnt16, 1 ;[1] + breq usbMFTimeout ;[3] + andi cntH, USBMASK ;[4] + brne usbMFWaitLoop ;[5] +usbMFTimeout: +#if resL != cnt16L + mov resL, cnt16L + mov resH, cnt16H +#endif + ret + +#undef resL +#undef resH +#undef cnt16 +#undef cnt16L +#undef cnt16H +#undef cntH + +#endif /* USB_CFG_HAVE_MEASURE_FRAME_LENGTH */ + +;---------------------------------------------------------------------------- +; Now include the clock rate specific code +;---------------------------------------------------------------------------- + +#ifndef USB_CFG_CLOCK_KHZ +# ifdef F_CPU +# define USB_CFG_CLOCK_KHZ (F_CPU/1000) +# else +# error "USB_CFG_CLOCK_KHZ not defined in usbconfig.h and no F_CPU set!" +# endif +#endif + +#if USB_CFG_CHECK_CRC /* separate dispatcher for CRC type modules */ +# if USB_CFG_CLOCK_KHZ == 18000 +# include "usbdrvasm18-crc.inc" +# else +# error "USB_CFG_CLOCK_KHZ is not one of the supported crc-rates!" +# endif +#else /* USB_CFG_CHECK_CRC */ +# if USB_CFG_CLOCK_KHZ == 12000 +# include "usbdrvasm12.inc" +# elif USB_CFG_CLOCK_KHZ == 12800 +# include "usbdrvasm128.inc" +# elif USB_CFG_CLOCK_KHZ == 15000 +# include "usbdrvasm15.inc" +# elif USB_CFG_CLOCK_KHZ == 16000 +# include "usbdrvasm16.inc" +# elif USB_CFG_CLOCK_KHZ == 16500 +# include "usbdrvasm165.inc" +# elif USB_CFG_CLOCK_KHZ == 20000 +# include "usbdrvasm20.inc" +# else +# error "USB_CFG_CLOCK_KHZ is not one of the supported non-crc-rates!" +# endif +#endif /* USB_CFG_CHECK_CRC */ diff --git a/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm.asm b/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm.asm new file mode 100644 index 0000000..9cc4e4d --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm.asm @@ -0,0 +1,21 @@ +/* Name: usbdrvasm.asm + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2006-03-01 + * Tabsize: 4 + * Copyright: (c) 2006 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id$ + */ + +/* +General Description: +The IAR compiler/assembler system prefers assembler files with file extension +".asm". We simply provide this file as an alias for usbdrvasm.S. + +Thanks to Oleg Semyonov for his help with the IAR tools port! +*/ + +#include "usbdrvasm.S" + +end diff --git a/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm12.inc b/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm12.inc new file mode 100644 index 0000000..c116758 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm12.inc @@ -0,0 +1,393 @@ +/* Name: usbdrvasm12.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2004-12-29 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbdrvasm12.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 12 MHz version of the asssembler part of the USB driver. It +requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! + + +Timing constraints according to spec (in bit times): +timing subject min max CPUcycles +--------------------------------------------------------------------------- +EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128 +EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60 +DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60 +*/ + +;Software-receiver engine. Strict timing! Don't change unless you can preserve timing! +;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled +;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable +;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes +;Numbers in brackets are maximum cycles since SOF. +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt + push YL ;2 [35] push only what is necessary to sync with edge ASAP + in YL, SREG ;1 [37] + push YL ;2 [39] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of 1/4 bit which meets the spec. + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push YH ;2 [2] + lds YL, usbInputBufOffset;2 [4] + clr YH ;1 [5] + subi YL, lo8(-(usbRxBuf));1 [6] + sbci YH, hi8(-(usbRxBuf));1 [7] + + sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early] + rjmp haveTwoBitsK ;2 [10] + pop YH ;2 [11] undo the push from before + rjmp waitForK ;2 [13] this was not the end of sync, retry +haveTwoBitsK: +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- + push shift ;2 [16] + push x1 ;2 [12] + push x2 ;2 [14] + + in x1, USBIN ;1 [17] <-- sample bit 0 + ldi shift, 0xff ;1 [18] + bst x1, USBMINUS ;1 [19] + bld shift, 0 ;1 [20] + push x3 ;2 [22] + push cnt ;2 [24] + + in x2, USBIN ;1 [25] <-- sample bit 1 + ser x3 ;1 [26] [inserted init instruction] + eor x1, x2 ;1 [27] + bst x1, USBMINUS ;1 [28] + bld shift, 1 ;1 [29] + ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction] + rjmp rxbit2 ;2 [32] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- + +unstuff0: ;1 (branch taken) + andi x3, ~0x01 ;1 [15] + mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit + in x2, USBIN ;1 [17] <-- sample bit 1 again + ori shift, 0x01 ;1 [18] + rjmp didUnstuff0 ;2 [20] + +unstuff1: ;1 (branch taken) + mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit + andi x3, ~0x02 ;1 [22] + ori shift, 0x02 ;1 [23] + nop ;1 [24] + in x1, USBIN ;1 [25] <-- sample bit 2 again + rjmp didUnstuff1 ;2 [27] + +unstuff2: ;1 (branch taken) + andi x3, ~0x04 ;1 [29] + ori shift, 0x04 ;1 [30] + mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit + nop ;1 [32] + in x2, USBIN ;1 [33] <-- sample bit 3 + rjmp didUnstuff2 ;2 [35] + +unstuff3: ;1 (branch taken) + in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late] + andi x3, ~0x08 ;1 [35] + ori shift, 0x08 ;1 [36] + rjmp didUnstuff3 ;2 [38] + +unstuff4: ;1 (branch taken) + andi x3, ~0x10 ;1 [40] + in x1, USBIN ;1 [41] <-- sample stuffed bit 4 + ori shift, 0x10 ;1 [42] + rjmp didUnstuff4 ;2 [44] + +unstuff5: ;1 (branch taken) + andi x3, ~0x20 ;1 [48] + in x2, USBIN ;1 [49] <-- sample stuffed bit 5 + ori shift, 0x20 ;1 [50] + rjmp didUnstuff5 ;2 [52] + +unstuff6: ;1 (branch taken) + andi x3, ~0x40 ;1 [56] + in x1, USBIN ;1 [57] <-- sample stuffed bit 6 + ori shift, 0x40 ;1 [58] + rjmp didUnstuff6 ;2 [60] + +; extra jobs done during bit interval: +; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs] +; bit 1: se0 check +; bit 2: overflow check +; bit 3: recovery from delay [bit 0 tasks took too long] +; bit 4: none +; bit 5: none +; bit 6: none +; bit 7: jump, eor +rxLoop: + eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others + in x1, USBIN ;1 [1] <-- sample bit 0 + st y+, x3 ;2 [3] store data + ser x3 ;1 [4] + nop ;1 [5] + eor x2, x1 ;1 [6] + bst x2, USBMINUS;1 [7] + bld shift, 0 ;1 [8] + in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed) + andi x2, USBMASK ;1 [10] + breq se0 ;1 [11] SE0 check for bit 1 + andi shift, 0xf9 ;1 [12] +didUnstuff0: + breq unstuff0 ;1 [13] + eor x1, x2 ;1 [14] + bst x1, USBMINUS;1 [15] + bld shift, 1 ;1 [16] +rxbit2: + in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed) + andi shift, 0xf3 ;1 [18] + breq unstuff1 ;1 [19] do remaining work for bit 1 +didUnstuff1: + subi cnt, 1 ;1 [20] + brcs overflow ;1 [21] loop control + eor x2, x1 ;1 [22] + bst x2, USBMINUS;1 [23] + bld shift, 2 ;1 [24] + in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed) + andi shift, 0xe7 ;1 [26] + breq unstuff2 ;1 [27] +didUnstuff2: + eor x1, x2 ;1 [28] + bst x1, USBMINUS;1 [29] + bld shift, 3 ;1 [30] +didUnstuff3: + andi shift, 0xcf ;1 [31] + breq unstuff3 ;1 [32] + in x1, USBIN ;1 [33] <-- sample bit 4 + eor x2, x1 ;1 [34] + bst x2, USBMINUS;1 [35] + bld shift, 4 ;1 [36] +didUnstuff4: + andi shift, 0x9f ;1 [37] + breq unstuff4 ;1 [38] + nop2 ;2 [40] + in x2, USBIN ;1 [41] <-- sample bit 5 + eor x1, x2 ;1 [42] + bst x1, USBMINUS;1 [43] + bld shift, 5 ;1 [44] +didUnstuff5: + andi shift, 0x3f ;1 [45] + breq unstuff5 ;1 [46] + nop2 ;2 [48] + in x1, USBIN ;1 [49] <-- sample bit 6 + eor x2, x1 ;1 [50] + bst x2, USBMINUS;1 [51] + bld shift, 6 ;1 [52] +didUnstuff6: + cpi shift, 0x02 ;1 [53] + brlo unstuff6 ;1 [54] + nop2 ;2 [56] + in x2, USBIN ;1 [57] <-- sample bit 7 + eor x1, x2 ;1 [58] + bst x1, USBMINUS;1 [59] + bld shift, 7 ;1 [60] +didUnstuff7: + cpi shift, 0x04 ;1 [61] + brsh rxLoop ;2 [63] loop control +unstuff7: + andi x3, ~0x80 ;1 [63] + ori shift, 0x80 ;1 [64] + in x2, USBIN ;1 [65] <-- sample stuffed bit 7 + nop ;1 [66] + rjmp didUnstuff7 ;2 [68] + +macro POP_STANDARD ; 12 cycles + pop cnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;---------------------------------------------------------------------------- +; Transmitting data +;---------------------------------------------------------------------------- + +txByteLoop: +txBitloop: +stuffN1Delay: ; [03] + ror shift ;[-5] [11] [59] + brcc doExorN1 ;[-4] [60] + subi x4, 1 ;[-3] + brne commonN1 ;[-2] + lsl shift ;[-1] compensate ror after rjmp stuffDelay + nop ;[00] stuffing consists of just waiting 8 cycles + rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear + +sendNakAndReti: ;0 [-19] 19 cycles until SOP + ldi x3, USBPID_NAK ;1 [-18] + rjmp usbSendX3 ;2 [-16] +sendAckAndReti: ;0 [-19] 19 cycles until SOP + ldi x3, USBPID_ACK ;1 [-18] + rjmp usbSendX3 ;2 [-16] +sendCntAndReti: ;0 [-17] 17 cycles until SOP + mov x3, cnt ;1 [-16] +usbSendX3: ;0 [-16] + ldi YL, 20 ;1 [-15] 'x3' is R20 + ldi YH, 0 ;1 [-14] + ldi cnt, 2 ;1 [-13] +; rjmp usbSendAndReti fallthrough + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) or USBOUT = 0x01 +; K = (D+ = 1), (D- = 0) or USBOUT = 0x02 +; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles) + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte +;uses: x1...x2, x4, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x4 = bitstuff cnt] +;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction) +usbSendAndReti: + in x2, USBDDR ;[-12] 12 cycles until SOP + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS ;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + out USBDDR, x2 ;[-8] <--- acquire bus + in x1, USBOUT ;[-7] port mirror for tx loop + ldi shift, 0x40 ;[-6] sync byte is first byte sent (we enter loop after ror) + ldi x2, USBMASK ;[-5] + push x4 ;[-4] +doExorN1: + eor x1, x2 ;[-2] [06] [62] + ldi x4, 6 ;[-1] [07] [63] +commonN1: +stuffN2Delay: + out USBOUT, x1 ;[00] [08] [64] <--- set bit + ror shift ;[01] + brcc doExorN2 ;[02] + subi x4, 1 ;[03] + brne commonN2 ;[04] + lsl shift ;[05] compensate ror after rjmp stuffDelay + rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear +doExorN2: + eor x1, x2 ;[04] [12] + ldi x4, 6 ;[05] [13] +commonN2: + nop ;[06] [14] + subi cnt, 171 ;[07] [15] trick: (3 * 171) & 0xff = 1 + out USBOUT, x1 ;[08] [16] <--- set bit + brcs txBitloop ;[09] [25] [41] + +stuff6Delay: + ror shift ;[42] [50] + brcc doExor6 ;[43] + subi x4, 1 ;[44] + brne common6 ;[45] + lsl shift ;[46] compensate ror after rjmp stuffDelay + nop ;[47] stuffing consists of just waiting 8 cycles + rjmp stuff6Delay ;[48] after ror, C bit is reliably clear +doExor6: + eor x1, x2 ;[45] [53] + ldi x4, 6 ;[46] +common6: +stuff7Delay: + ror shift ;[47] [55] + out USBOUT, x1 ;[48] <--- set bit + brcc doExor7 ;[49] + subi x4, 1 ;[50] + brne common7 ;[51] + lsl shift ;[52] compensate ror after rjmp stuffDelay + rjmp stuff7Delay ;[53] after ror, C bit is reliably clear +doExor7: + eor x1, x2 ;[51] [59] + ldi x4, 6 ;[52] +common7: + ld shift, y+ ;[53] + tst cnt ;[55] + out USBOUT, x1 ;[56] <--- set bit + brne txByteLoop ;[57] + +;make SE0: + cbr x1, USBMASK ;[58] prepare SE0 [spec says EOP may be 15 to 18 cycles] + lds x2, usbNewDeviceAddr;[59] + lsl x2 ;[61] we compare with left shifted address + subi YL, 2 + 20 ;[62] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[63] + out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[01] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 12.5625 MHz +max frequency: 69.286 cycles for 8 bit -> 12.99 MHz +nominal frequency: 12.77 MHz ( = sqrt(min * max)) + +sampling positions: (next even number in range [+/- 0.5]) +cycle index range: 0 ... 66 +bits: +.5, 8.875, 17.25, 25.625, 34, 42.375, 50.75, 59.125 +[0/1], [9], [17], [25/+26], [34], [+42/43], [51], [59] + +bit number: 0 1 2 3 4 5 6 7 +spare cycles 1 2 1 2 1 1 1 0 + +operations to perform: duration cycle + ---------------- + eor fix, shift 1 -> 00 + andi phase, USBMASK 1 -> 08 + breq se0 1 -> 16 (moved to 11) + st y+, data 2 -> 24, 25 + mov data, fix 1 -> 33 + ser data 1 -> 41 + subi cnt, 1 1 -> 49 + brcs overflow 1 -> 50 + +layout of samples and operations: +[##] = sample bit +<##> = sample phase +*##* = operation + +0: *00* [01] 02 03 04 <05> 06 07 +1: *08* [09] 10 11 12 <13> 14 15 *16* +2: [17] 18 19 20 <21> 22 23 +3: *24* *25* [26] 27 28 29 <30> 31 32 +4: *33* [34] 35 36 37 <38> 39 40 +5: *41* [42] 43 44 45 <46> 47 48 +6: *49* *50* [51] 52 53 54 <55> 56 57 58 +7: [59] 60 61 62 <63> 64 65 66 +*****************************************************************************/ + +/* we prefer positive expressions (do if condition) instead of negative + * (skip if condition), therefore use defines for skip instructions: + */ +#define ifioclr sbis +#define ifioset sbic +#define ifrclr sbrs +#define ifrset sbrc + +/* The registers "fix" and "data" swap their meaning during the loop. Use + * defines to keep their name constant. + */ +#define fix x2 +#define data x1 +#undef phase /* phase has a default definition to x4 */ +#define phase x3 + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt, r0 + push YL ;2 push only what is necessary to sync with edge ASAP + in YL, SREG ;1 + push YL ;2 +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of 1/4 bit which meets the spec. + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS ;[0] + rjmp foundK ;[1] +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError + +foundK: +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push YH ;[2] + lds YL, usbInputBufOffset;[4] + clr YH ;[6] + subi YL, lo8(-(usbRxBuf));[7] + sbci YH, hi8(-(usbRxBuf));[8] + + sbis USBIN, USBMINUS ;[9] we want two bits K [we want to sample at 8 + 4 - 1.5 = 10.5] + rjmp haveTwoBitsK ;[10] + pop YH ;[11] undo the push from before + rjmp waitForK ;[13] this was not the end of sync, retry +haveTwoBitsK: +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +#define fix x2 +#define data x1 + + push shift ;[12] + push x1 ;[14] + push x2 ;[16] + ldi shift, 0x80 ;[18] prevent bit-unstuffing but init low bits to 0 + ifioset USBIN, USBMINUS ;[19] [01] <--- bit 0 [10.5 + 8 = 18.5] + ori shift, 1<<0 ;[02] + push x3 ;[03] + push cnt ;[05] + push r0 ;[07] + ifioset USBIN, USBMINUS ;[09] <--- bit 1 + ori shift, 1<<1 ;[10] + ser fix ;[11] + ldi cnt, USB_BUFSIZE ;[12] + mov data, shift ;[13] + lsl shift ;[14] + nop2 ;[15] + ifioset USBIN, USBMINUS ;[17] <--- bit 2 + ori data, 3<<2 ;[18] store in bit 2 AND bit 3 + eor shift, data ;[19] do nrzi decoding + andi data, 1<<3 ;[20] + in phase, USBIN ;[21] <- phase + brne jumpToEntryAfterSet ;[22] if USBMINS at bit 3 was 1 + nop ;[23] + rjmp entryAfterClr ;[24] +jumpToEntryAfterSet: + rjmp entryAfterSet ;[24] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +#undef fix +#define fix x1 +#undef data +#define data x2 + +bit7IsSet: + ifrclr phase, USBMINUS ;[62] check phase only if D- changed + lpm ;[63] + in phase, USBIN ;[64] <- phase (one cycle too late) + ori shift, 1 << 7 ;[65] + nop ;[66] +;;;;rjmp bit0AfterSet ; -> [00] == [67] moved block up to save jump +bit0AfterSet: + eor fix, shift ;[00] +#undef fix +#define fix x2 +#undef data +#define data x1 /* we now have result in data, fix is reset to 0xff */ + ifioclr USBIN, USBMINUS ;[01] <--- sample 0 + rjmp bit0IsClr ;[02] + andi shift, ~(7 << 0) ;[03] + breq unstuff0s ;[04] + in phase, USBIN ;[05] <- phase + rjmp bit1AfterSet ;[06] +unstuff0s: + in phase, USBIN ;[06] <- phase (one cycle too late) + andi fix, ~(1 << 0) ;[07] + ifioclr USBIN, USBMINUS ;[00] + ifioset USBIN, USBPLUS ;[01] + rjmp bit0IsClr ;[02] executed if first expr false or second true +se0AndStore: ; executed only if both bits 0 + st y+, x1 ;[15/17] cycles after start of byte + rjmp se0 ;[17/19] + +bit0IsClr: + ifrset phase, USBMINUS ;[04] check phase only if D- changed + lpm ;[05] + in phase, USBIN ;[06] <- phase (one cycle too late) + ori shift, 1 << 0 ;[07] +bit1AfterClr: + andi phase, USBMASK ;[08] + ifioset USBIN, USBMINUS ;[09] <--- sample 1 + rjmp bit1IsSet ;[10] + breq se0AndStore ;[11] if D- was 0 in bits 0 AND 1 and D+ was 0 in between, we have SE0 + andi shift, ~(7 << 1) ;[12] + in phase, USBIN ;[13] <- phase + breq unstuff1c ;[14] + rjmp bit2AfterClr ;[15] +unstuff1c: + andi fix, ~(1 << 1) ;[16] + nop2 ;[08] + nop2 ;[10] +bit1IsSet: + ifrclr phase, USBMINUS ;[12] check phase only if D- changed + lpm ;[13] + in phase, USBIN ;[14] <- phase (one cycle too late) + ori shift, 1 << 1 ;[15] + nop ;[16] +bit2AfterSet: + ifioclr USBIN, USBMINUS ;[17] <--- sample 2 + rjmp bit2IsClr ;[18] + andi shift, ~(7 << 2) ;[19] + breq unstuff2s ;[20] + in phase, USBIN ;[21] <- phase + rjmp bit3AfterSet ;[22] +unstuff2s: + in phase, USBIN ;[22] <- phase (one cycle too late) + andi fix, ~(1 << 2) ;[23] + nop2 ;[16] + nop2 ;[18] +bit2IsClr: + ifrset phase, USBMINUS ;[20] check phase only if D- changed + lpm ;[21] + in phase, USBIN ;[22] <- phase (one cycle too late) + ori shift, 1 << 2 ;[23] +bit3AfterClr: + st y+, data ;[24] +entryAfterClr: + ifioset USBIN, USBMINUS ;[26] <--- sample 3 + rjmp bit3IsSet ;[27] + andi shift, ~(7 << 3) ;[28] + breq unstuff3c ;[29] + in phase, USBIN ;[30] <- phase + rjmp bit4AfterClr ;[31] +unstuff3c: + in phase, USBIN ;[31] <- phase (one cycle too late) + andi fix, ~(1 << 3) ;[32] + nop2 ;[25] + nop2 ;[27] +bit3IsSet: + ifrclr phase, USBMINUS ;[29] check phase only if D- changed + lpm ;[30] + in phase, USBIN ;[31] <- phase (one cycle too late) + ori shift, 1 << 3 ;[32] +bit4AfterSet: + mov data, fix ;[33] undo this move by swapping defines +#undef fix +#define fix x1 +#undef data +#define data x2 + ifioclr USBIN, USBMINUS ;[34] <--- sample 4 + rjmp bit4IsClr ;[35] + andi shift, ~(7 << 4) ;[36] + breq unstuff4s ;[37] + in phase, USBIN ;[38] <- phase + rjmp bit5AfterSet ;[39] +unstuff4s: + in phase, USBIN ;[39] <- phase (one cycle too late) + andi fix, ~(1 << 4) ;[40] + nop2 ;[33] + nop2 ;[35] +bit4IsClr: + ifrset phase, USBMINUS ;[37] check phase only if D- changed + lpm ;[38] + in phase, USBIN ;[39] <- phase (one cycle too late) + ori shift, 1 << 4 ;[40] +bit5AfterClr: + ser data ;[41] + ifioset USBIN, USBMINUS ;[42] <--- sample 5 + rjmp bit5IsSet ;[43] + andi shift, ~(7 << 5) ;[44] + breq unstuff5c ;[45] + in phase, USBIN ;[46] <- phase + rjmp bit6AfterClr ;[47] +unstuff5c: + in phase, USBIN ;[47] <- phase (one cycle too late) + andi fix, ~(1 << 5) ;[48] + nop2 ;[41] + nop2 ;[43] +bit5IsSet: + ifrclr phase, USBMINUS ;[45] check phase only if D- changed + lpm ;[46] + in phase, USBIN ;[47] <- phase (one cycle too late) + ori shift, 1 << 5 ;[48] +bit6AfterSet: + subi cnt, 1 ;[49] + brcs jumpToOverflow ;[50] + ifioclr USBIN, USBMINUS ;[51] <--- sample 6 + rjmp bit6IsClr ;[52] + andi shift, ~(3 << 6) ;[53] + cpi shift, 2 ;[54] + in phase, USBIN ;[55] <- phase + brlt unstuff6s ;[56] + rjmp bit7AfterSet ;[57] + +jumpToOverflow: + rjmp overflow + +unstuff6s: + andi fix, ~(1 << 6) ;[50] + lpm ;[51] +bit6IsClr: + ifrset phase, USBMINUS ;[54] check phase only if D- changed + lpm ;[55] + in phase, USBIN ;[56] <- phase (one cycle too late) + ori shift, 1 << 6 ;[57] + nop ;[58] +bit7AfterClr: + ifioset USBIN, USBMINUS ;[59] <--- sample 7 + rjmp bit7IsSet ;[60] + andi shift, ~(1 << 7) ;[61] + cpi shift, 4 ;[62] + in phase, USBIN ;[63] <- phase + brlt unstuff7c ;[64] + rjmp bit0AfterClr ;[65] -> [00] == [67] +unstuff7c: + andi fix, ~(1 << 7) ;[58] + nop ;[59] + rjmp bit7IsSet ;[60] + +bit7IsClr: + ifrset phase, USBMINUS ;[62] check phase only if D- changed + lpm ;[63] + in phase, USBIN ;[64] <- phase (one cycle too late) + ori shift, 1 << 7 ;[65] + nop ;[66] +;;;;rjmp bit0AfterClr ; -> [00] == [67] moved block up to save jump +bit0AfterClr: + eor fix, shift ;[00] +#undef fix +#define fix x2 +#undef data +#define data x1 /* we now have result in data, fix is reset to 0xff */ + ifioset USBIN, USBMINUS ;[01] <--- sample 0 + rjmp bit0IsSet ;[02] + andi shift, ~(7 << 0) ;[03] + breq unstuff0c ;[04] + in phase, USBIN ;[05] <- phase + rjmp bit1AfterClr ;[06] +unstuff0c: + in phase, USBIN ;[06] <- phase (one cycle too late) + andi fix, ~(1 << 0) ;[07] + ifioclr USBIN, USBMINUS ;[00] + ifioset USBIN, USBPLUS ;[01] + rjmp bit0IsSet ;[02] executed if first expr false or second true + rjmp se0AndStore ;[03] executed only if both bits 0 +bit0IsSet: + ifrclr phase, USBMINUS ;[04] check phase only if D- changed + lpm ;[05] + in phase, USBIN ;[06] <- phase (one cycle too late) + ori shift, 1 << 0 ;[07] +bit1AfterSet: + andi shift, ~(7 << 1) ;[08] compensated by "ori shift, 1<<1" if bit1IsClr + ifioclr USBIN, USBMINUS ;[09] <--- sample 1 + rjmp bit1IsClr ;[10] + breq unstuff1s ;[11] + nop2 ;[12] do not check for SE0 if bit 0 was 1 + in phase, USBIN ;[14] <- phase (one cycle too late) + rjmp bit2AfterSet ;[15] +unstuff1s: + in phase, USBIN ;[13] <- phase + andi fix, ~(1 << 1) ;[14] + lpm ;[07] + nop2 ;[10] +bit1IsClr: + ifrset phase, USBMINUS ;[12] check phase only if D- changed + lpm ;[13] + in phase, USBIN ;[14] <- phase (one cycle too late) + ori shift, 1 << 1 ;[15] + nop ;[16] +bit2AfterClr: + ifioset USBIN, USBMINUS ;[17] <--- sample 2 + rjmp bit2IsSet ;[18] + andi shift, ~(7 << 2) ;[19] + breq unstuff2c ;[20] + in phase, USBIN ;[21] <- phase + rjmp bit3AfterClr ;[22] +unstuff2c: + in phase, USBIN ;[22] <- phase (one cycle too late) + andi fix, ~(1 << 2) ;[23] + nop2 ;[16] + nop2 ;[18] +bit2IsSet: + ifrclr phase, USBMINUS ;[20] check phase only if D- changed + lpm ;[21] + in phase, USBIN ;[22] <- phase (one cycle too late) + ori shift, 1 << 2 ;[23] +bit3AfterSet: + st y+, data ;[24] +entryAfterSet: + ifioclr USBIN, USBMINUS ;[26] <--- sample 3 + rjmp bit3IsClr ;[27] + andi shift, ~(7 << 3) ;[28] + breq unstuff3s ;[29] + in phase, USBIN ;[30] <- phase + rjmp bit4AfterSet ;[31] +unstuff3s: + in phase, USBIN ;[31] <- phase (one cycle too late) + andi fix, ~(1 << 3) ;[32] + nop2 ;[25] + nop2 ;[27] +bit3IsClr: + ifrset phase, USBMINUS ;[29] check phase only if D- changed + lpm ;[30] + in phase, USBIN ;[31] <- phase (one cycle too late) + ori shift, 1 << 3 ;[32] +bit4AfterClr: + mov data, fix ;[33] undo this move by swapping defines +#undef fix +#define fix x1 +#undef data +#define data x2 + ifioset USBIN, USBMINUS ;[34] <--- sample 4 + rjmp bit4IsSet ;[35] + andi shift, ~(7 << 4) ;[36] + breq unstuff4c ;[37] + in phase, USBIN ;[38] <- phase + rjmp bit5AfterClr ;[39] +unstuff4c: + in phase, USBIN ;[39] <- phase (one cycle too late) + andi fix, ~(1 << 4) ;[40] + nop2 ;[33] + nop2 ;[35] +bit4IsSet: + ifrclr phase, USBMINUS ;[37] check phase only if D- changed + lpm ;[38] + in phase, USBIN ;[39] <- phase (one cycle too late) + ori shift, 1 << 4 ;[40] +bit5AfterSet: + ser data ;[41] + ifioclr USBIN, USBMINUS ;[42] <--- sample 5 + rjmp bit5IsClr ;[43] + andi shift, ~(7 << 5) ;[44] + breq unstuff5s ;[45] + in phase, USBIN ;[46] <- phase + rjmp bit6AfterSet ;[47] +unstuff5s: + in phase, USBIN ;[47] <- phase (one cycle too late) + andi fix, ~(1 << 5) ;[48] + nop2 ;[41] + nop2 ;[43] +bit5IsClr: + ifrset phase, USBMINUS ;[45] check phase only if D- changed + lpm ;[46] + in phase, USBIN ;[47] <- phase (one cycle too late) + ori shift, 1 << 5 ;[48] +bit6AfterClr: + subi cnt, 1 ;[49] + brcs overflow ;[50] + ifioset USBIN, USBMINUS ;[51] <--- sample 6 + rjmp bit6IsSet ;[52] + andi shift, ~(3 << 6) ;[53] + cpi shift, 2 ;[54] + in phase, USBIN ;[55] <- phase + brlt unstuff6c ;[56] + rjmp bit7AfterClr ;[57] +unstuff6c: + andi fix, ~(1 << 6) ;[50] + lpm ;[51] +bit6IsSet: + ifrclr phase, USBMINUS ;[54] check phase only if D- changed + lpm ;[55] + in phase, USBIN ;[56] <- phase (one cycle too late) + ori shift, 1 << 6 ;[57] +bit7AfterSet: + ifioclr USBIN, USBMINUS ;[59] <--- sample 7 + rjmp bit7IsClr ;[60] + andi shift, ~(1 << 7) ;[61] + cpi shift, 4 ;[62] + in phase, USBIN ;[63] <- phase + brlt unstuff7s ;[64] + rjmp bit0AfterSet ;[65] -> [00] == [67] +unstuff7s: + andi fix, ~(1 << 7) ;[58] + nop ;[59] + rjmp bit7IsClr ;[60] + +macro POP_STANDARD ; 14 cycles + pop r0 + pop cnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;---------------------------------------------------------------------------- +; Transmitting data +;---------------------------------------------------------------------------- + +txByteLoop: +txBitloop: +stuffN1Delay: ; [03] + ror shift ;[-5] [11] [63] + brcc doExorN1 ;[-4] [64] + subi x3, 1 ;[-3] + brne commonN1 ;[-2] + lsl shift ;[-1] compensate ror after rjmp stuffDelay + nop ;[00] stuffing consists of just waiting 8 cycles + rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear + +sendNakAndReti: + ldi cnt, USBPID_NAK ;[-19] + rjmp sendCntAndReti ;[-18] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov r0, cnt ;[-16] + ldi YL, 0 ;[-15] R0 address is 0 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) or USBOUT = 0x01 +; K = (D+ = 1), (D- = 0) or USBOUT = 0x02 +; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles) + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte +;uses: x1...x3, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x3 = bitstuff cnt] +;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction) +usbSendAndReti: + in x2, USBDDR ;[-10] 10 cycles until SOP + ori x2, USBMASK ;[-9] + sbi USBOUT, USBMINUS ;[-8] prepare idle state; D+ and D- must have been 0 (no pullups) + out USBDDR, x2 ;[-6] <--- acquire bus + in x1, USBOUT ;[-5] port mirror for tx loop + ldi shift, 0x40 ;[-4] sync byte is first byte sent (we enter loop after ror) + ldi x2, USBMASK ;[-3] +doExorN1: + eor x1, x2 ;[-2] [06] [62] + ldi x3, 6 ;[-1] [07] [63] +commonN1: +stuffN2Delay: + out USBOUT, x1 ;[00] [08] [64] <--- set bit + ror shift ;[01] + brcc doExorN2 ;[02] + subi x3, 1 ;[03] + brne commonN2 ;[04] + lsl shift ;[05] compensate ror after rjmp stuffDelay + rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear +doExorN2: + eor x1, x2 ;[04] [12] + ldi x3, 6 ;[05] [13] +commonN2: + nop2 ;[06] [14] + subi cnt, 171 ;[08] [16] trick: (3 * 171) & 0xff = 1 + out USBOUT, x1 ;[09] [17] <--- set bit + brcs txBitloop ;[10] [27] [44] + +stuff6Delay: + ror shift ;[45] [53] + brcc doExor6 ;[46] + subi x3, 1 ;[47] + brne common6 ;[48] + lsl shift ;[49] compensate ror after rjmp stuffDelay + nop ;[50] stuffing consists of just waiting 8 cycles + rjmp stuff6Delay ;[51] after ror, C bit is reliably clear +doExor6: + eor x1, x2 ;[48] [56] + ldi x3, 6 ;[49] +common6: +stuff7Delay: + ror shift ;[50] [58] + out USBOUT, x1 ;[51] <--- set bit + brcc doExor7 ;[52] + subi x3, 1 ;[53] + brne common7 ;[54] + lsl shift ;[55] compensate ror after rjmp stuffDelay + rjmp stuff7Delay ;[56] after ror, C bit is reliably clear +doExor7: + eor x1, x2 ;[54] [62] + ldi x3, 6 ;[55] +common7: + ld shift, y+ ;[56] + nop ;[58] + tst cnt ;[59] + out USBOUT, x1 ;[60] [00]<--- set bit + brne txByteLoop ;[61] [01] +;make SE0: + cbr x1, USBMASK ;[02] prepare SE0 [spec says EOP may be 15 to 18 cycles] + lds x2, usbNewDeviceAddr;[03] + lsl x2 ;[05] we compare with left shifted address + subi YL, 2 + 0 ;[06] Only assign address on data packets, not ACK/NAK in r0 + sbci YH, 0 ;[07] + out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[01] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 0) + echo "$s\n"; + } +} + +function printBit($isAfterSet, $bitNum) +{ + ob_start(); + if($isAfterSet){ +?> + ifioclr USBIN, USBMINUS ;[00] <--- sample + rjmp bit#IsClr ;[01] + andi shift, ~(7 << #) ;[02] + breq unstuff#s ;[03] + in phase, USBIN ;[04] <- phase + rjmp bit@AfterSet ;[05] +unstuff#s: + in phase, USBIN ;[05] <- phase (one cycle too late) + andi fix, ~(1 << #) ;[06] + nop2 ;[-1] + nop2 ;[01] +bit#IsClr: + ifrset phase, USBMINUS ;[03] check phase only if D- changed + lpm ;[04] + in phase, USBIN ;[05] <- phase (one cycle too late) + ori shift, 1 << # ;[06] + + ifioset USBIN, USBMINUS ;[00] <--- sample + rjmp bit#IsSet ;[01] + andi shift, ~(7 << #) ;[02] + breq unstuff#c ;[03] + in phase, USBIN ;[04] <- phase + rjmp bit@AfterClr ;[05] +unstuff#c: + in phase, USBIN ;[05] <- phase (one cycle too late) + andi fix, ~(1 << #) ;[06] + nop2 ;[-1] + nop2 ;[01] +bit#IsSet: + ifrclr phase, USBMINUS ;[03] check phase only if D- changed + lpm ;[04] + in phase, USBIN ;[05] <- phase (one cycle too late) + ori shift, 1 << # ;[06] + +*****************************************************************************/ diff --git a/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm15.inc b/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm15.inc new file mode 100644 index 0000000..401b7f8 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm15.inc @@ -0,0 +1,423 @@ +/* Name: usbdrvasm15.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: contributed by V. Bosch + * Creation Date: 2007-08-06 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm15.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 15 MHz version of the asssembler part of the USB driver. It +requires a 15 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! +*/ + +;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + +;---------------------------------------------------------------------------- +; order of registers pushed: +; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4 +;---------------------------------------------------------------------------- +USB_INTR_VECTOR: + push YL ;2 push only what is necessary to sync with edge ASAP + in YL, SREG ;1 + push YL ;2 +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +; +; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +; sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +;------------------------------------------------------------------------------- +; The following code results in a sampling window of < 1/4 bit +; which meets the spec. +;------------------------------------------------------------------------------- +waitForK: ;- + sbis USBIN, USBMINUS ;1 [00] <-- sample + rjmp foundK ;2 [01] + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +;------------------------------------------------------------------------------ +; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for +; center sampling] +; we have 1 bit time for setup purposes, then sample again. +; Numbers in brackets are cycles from center of first sync (double K) +; bit after the instruction +;------------------------------------------------------------------------------ +foundK: ;- [02] + lds YL, usbInputBufOffset;2 [03+04] tx loop + push YH ;2 [05+06] + clr YH ;1 [07] + subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init] + sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init] + push shift ;2 [10+11] + ser shift ;1 [12] + sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early) + rjmp haveTwoBitsK ;2 [00] [14] + pop shift ;2 [15+16] undo the push from before + pop YH ;2 [17+18] undo the push from before + rjmp waitForK ;2 [19+20] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 20 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: ;- [01] + push x1 ;2 [02+03] + push x2 ;2 [04+05] + push x3 ;2 [06+07] + push bitcnt ;2 [08+09] + in x1, USBIN ;1 [00] [10] <-- sample bit 0 + bst x1, USBMINUS ;1 [01] + bld shift, 0 ;1 [02] + push cnt ;2 [03+04] + ldi cnt, USB_BUFSIZE ;1 [05] + push x4 ;2 [06+07] tx loop + rjmp rxLoop ;2 [08] +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +unstuff0: ;- [07] (branch taken) + andi x3, ~0x01 ;1 [08] + mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit + in x2, USBIN ;1 [00] [10] <-- sample bit 1 again + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 1 + ori shift, 0x01 ;1 [03] 0b00000001 + nop ;1 [04] + rjmp didUnstuff0 ;2 [05] +;----------------------------------------------------- +unstuff1: ;- [05] (branch taken) + mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit + andi x3, ~0x02 ;1 [07] + ori shift, 0x02 ;1 [08] 0b00000010 + nop ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 2 again + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 2 + rjmp didUnstuff1 ;2 [03] +;----------------------------------------------------- +unstuff2: ;- [05] (branch taken) + andi x3, ~0x04 ;1 [06] + ori shift, 0x04 ;1 [07] 0b00000100 + mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit + nop ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample bit 3 + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 3 + rjmp didUnstuff2 ;2 [03] +;----------------------------------------------------- +unstuff3: ;- [00] [10] (branch taken) + in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late + andi x2, USBMASK ;1 [02] + breq se0Hop ;1 [03] SE0 check for stuffed bit 3 + andi x3, ~0x08 ;1 [04] + ori shift, 0x08 ;1 [05] 0b00001000 + rjmp didUnstuff3 ;2 [06] +;---------------------------------------------------------------------------- +; extra jobs done during bit interval: +; +; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs], +; overflow check, jump to the head of rxLoop +; bit 1: SE0 check +; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long] +; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long] +; bit 4: SE0 check, none +; bit 5: SE0 check, none +; bit 6: SE0 check, none +; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others +;---------------------------------------------------------------------------- +rxLoop: ;- [09] + in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed) + andi x2, USBMASK ;1 [01] + brne SkipSe0Hop ;1 [02] +se0Hop: ;- [02] + rjmp se0 ;2 [03] SE0 check for bit 1 +SkipSe0Hop: ;- [03] + ser x3 ;1 [04] + andi shift, 0xf9 ;1 [05] 0b11111001 + breq unstuff0 ;1 [06] +didUnstuff0: ;- [06] + eor x1, x2 ;1 [07] + bst x1, USBMINUS ;1 [08] + bld shift, 1 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed) + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 2 + andi shift, 0xf3 ;1 [03] 0b11110011 + breq unstuff1 ;1 [04] do remaining work for bit 1 +didUnstuff1: ;- [04] + eor x2, x1 ;1 [05] + bst x2, USBMINUS ;1 [06] + bld shift, 2 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed) + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 3 + andi shift, 0xe7 ;1 [03] 0b11100111 + breq unstuff2 ;1 [04] +didUnstuff2: ;- [04] + eor x1, x2 ;1 [05] + bst x1, USBMINUS ;1 [06] + bld shift, 3 ;1 [07] +didUnstuff3: ;- [07] + andi shift, 0xcf ;1 [08] 0b11001111 + breq unstuff3 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 4 + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 4 + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 4 ;1 [05] +didUnstuff4: ;- [05] + andi shift, 0x9f ;1 [06] 0b10011111 + breq unstuff4 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 5 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 5 + eor x1, x2 ;1 [03] + bst x1, USBMINUS ;1 [04] + bld shift, 5 ;1 [05] +didUnstuff5: ;- [05] + andi shift, 0x3f ;1 [06] 0b00111111 + breq unstuff5 ;1 [07] + nop2 ;2 [08+09] + in x1, USBIN ;1 [00] [10] <-- sample bit 6 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 6 + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 6 ;1 [05] +didUnstuff6: ;- [05] + cpi shift, 0x02 ;1 [06] 0b00000010 + brlo unstuff6 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 7 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 7 + eor x1, x2 ;1 [03] + bst x1, USBMINUS ;1 [04] + bld shift, 7 ;1 [05] +didUnstuff7: ;- [05] + cpi shift, 0x04 ;1 [06] 0b00000100 + brlo unstuff7 ;1 [07] + eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others + nop ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 0 + st y+, x3 ;2 [01+02] store data + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 0 ;1 [05] + subi cnt, 1 ;1 [06] + brcs overflow ;1 [07] + rjmp rxLoop ;2 [08] +;----------------------------------------------------- +unstuff4: ;- [08] + andi x3, ~0x10 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 4 + ori shift, 0x10 ;1 [03] + rjmp didUnstuff4 ;2 [04] +;----------------------------------------------------- +unstuff5: ;- [08] + ori shift, 0x20 ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 5 + andi x3, ~0x20 ;1 [03] + rjmp didUnstuff5 ;2 [04] +;----------------------------------------------------- +unstuff6: ;- [08] + andi x3, ~0x40 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 6 + ori shift, 0x40 ;1 [03] + rjmp didUnstuff6 ;2 [04] +;----------------------------------------------------- +unstuff7: ;- [08] + andi x3, ~0x80 ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 7 + ori shift, 0x80 ;1 [03] + rjmp didUnstuff7 ;2 [04] + +macro POP_STANDARD ; 16 cycles + pop x4 + pop cnt + pop bitcnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;--------------------------------------------------------------------------- +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies +;--------------------------------------------------------------------------- +bitstuffN: ;- [04] + eor x1, x4 ;1 [05] + clr x2 ;1 [06] + nop ;1 [07] + rjmp didStuffN ;1 [08] +;--------------------------------------------------------------------------- +bitstuff6: ;- [04] + eor x1, x4 ;1 [05] + clr x2 ;1 [06] + rjmp didStuff6 ;1 [07] +;--------------------------------------------------------------------------- +bitstuff7: ;- [02] + eor x1, x4 ;1 [03] + clr x2 ;1 [06] + nop ;1 [05] + rjmp didStuff7 ;1 [06] +;--------------------------------------------------------------------------- +sendNakAndReti: ;- [-19] + ldi x3, USBPID_NAK ;1 [-18] + rjmp sendX3AndReti ;1 [-17] +;--------------------------------------------------------------------------- +sendAckAndReti: ;- [-17] + ldi cnt, USBPID_ACK ;1 [-16] +sendCntAndReti: ;- [-16] + mov x3, cnt ;1 [-15] +sendX3AndReti: ;- [-15] + ldi YL, 20 ;1 [-14] x3==r20 address is 20 + ldi YH, 0 ;1 [-13] + ldi cnt, 2 ;1 [-12] +; rjmp usbSendAndReti fallthrough +;--------------------------------------------------------------------------- +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +;We need not to match the transfer rate exactly because the spec demands +;only 1.5% precision anyway. +usbSendAndReti: ;- [-13] 13 cycles until SOP + in x2, USBDDR ;1 [-12] + ori x2, USBMASK ;1 [-11] + sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;1 [-08] port mirror for tx loop + out USBDDR, x2 ;1 [-07] <- acquire bus + ; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;1 [-06] exor mask + ldi shift, 0x80 ;1 [-05] sync byte is first byte sent + ldi bitcnt, 6 ;1 [-04] +txBitLoop: ;- [-04] [06] + sbrs shift, 0 ;1 [-03] [07] + eor x1, x4 ;1 [-02] [08] + ror shift ;1 [-01] [09] +didStuffN: ;- [09] + out USBOUT, x1 ;1 [00] [10] <-- out N + ror x2 ;1 [01] + cpi x2, 0xfc ;1 [02] + brcc bitstuffN ;1 [03] + dec bitcnt ;1 [04] + brne txBitLoop ;1 [05] + sbrs shift, 0 ;1 [06] + eor x1, x4 ;1 [07] + ror shift ;1 [08] +didStuff6: ;- [08] + nop ;1 [09] + out USBOUT, x1 ;1 [00] [10] <-- out 6 + ror x2 ;1 [01] + cpi x2, 0xfc ;1 [02] + brcc bitstuff6 ;1 [03] + sbrs shift, 0 ;1 [04] + eor x1, x4 ;1 [05] + ror shift ;1 [06] + ror x2 ;1 [07] +didStuff7: ;- [07] + ldi bitcnt, 6 ;1 [08] + cpi x2, 0xfc ;1 [09] + out USBOUT, x1 ;1 [00] [10] <-- out 7 + brcc bitstuff7 ;1 [01] + ld shift, y+ ;2 [02+03] + dec cnt ;1 [04] + brne txBitLoop ;1 [05] +makeSE0: + cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles] + lds x2, usbNewDeviceAddr;2 [07+08] + lsl x2 ;1 [09] we compare with left shifted address +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle + subi YL, 20 + 2 ;1 [01] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;1 [02] + breq skipAddrAssign ;1 [03] + sts usbDeviceAddr, x2 ;2 [04+05] if not skipped: SE0 is one cycle longer +;---------------------------------------------------------------------------- +;end of usbDeviceAddress transfer +skipAddrAssign: ;- [03/04] + ldi x2, 1< 10.6666666 cycles per bit, 85.333333333 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt + push YL ;[-25] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-23] + push YL ;[-22] + push YH ;[-20] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-15] + rjmp foundK ;[-14] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-12] +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push bitcnt ;[-12] +; [---] ;[-11] + lds YL, usbInputBufOffset;[-10] +; [---] ;[-9] + clr YH ;[-8] + subi YL, lo8(-(usbRxBuf));[-7] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init] + push shift ;[-5] +; [---] ;[-4] + ldi bitcnt, 0x55 ;[-3] [rx loop init] + sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early) + rjmp haveTwoBitsK ;[-1] + pop shift ;[0] undo the push from before + pop bitcnt ;[2] undo the push from before + rjmp waitForK ;[4] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 21 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[1] + push x2 ;[3] + push x3 ;[5] + ldi shift, 0 ;[7] + ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that + push x4 ;[9] == leap + + in x1, USBIN ;[11] <-- sample bit 0 + andi x1, USBMASK ;[12] + bst x1, USBMINUS ;[13] + bld shift, 7 ;[14] + push cnt ;[15] + ldi leap, 0 ;[17] [rx loop init] + ldi cnt, USB_BUFSIZE;[18] [rx loop init] + rjmp rxbit1 ;[19] arrives at [21] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- + +; duration of unstuffing code should be 10.66666667 cycles. We adjust "leap" +; accordingly to approximate this value in the long run. + +unstuff6: + andi x2, USBMASK ;[03] + ori x3, 1<<6 ;[04] will not be shifted any more + andi shift, ~0x80;[05] + mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6 + subi leap, -1 ;[07] total duration = 11 bits -> subtract 1/3 + rjmp didUnstuff6 ;[08] + +unstuff7: + ori x3, 1<<7 ;[09] will not be shifted any more + in x2, USBIN ;[00] [10] re-sample bit 7 + andi x2, USBMASK ;[01] + andi shift, ~0x80;[02] + subi leap, 2 ;[03] total duration = 10 bits -> add 1/3 + rjmp didUnstuff7 ;[04] + +unstuffEven: + ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0 + in x1, USBIN ;[00] [10] + andi shift, ~0x80;[01] + andi x1, USBMASK ;[02] + breq se0 ;[03] + subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3 + nop2 ;[05] + rjmp didUnstuffE ;[06] + +unstuffOdd: + ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1 + in x2, USBIN ;[00] [10] + andi shift, ~0x80;[01] + andi x2, USBMASK ;[02] + breq se0 ;[03] + subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3 + nop2 ;[05] + rjmp didUnstuffO ;[06] + +rxByteLoop: + andi x1, USBMASK ;[03] + eor x2, x1 ;[04] + subi leap, 1 ;[05] + brpl skipLeap ;[06] + subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte + nop ;1 +skipLeap: + subi x2, 1 ;[08] + ror shift ;[09] +didUnstuff6: + cpi shift, 0xfc ;[10] + in x2, USBIN ;[00] [11] <-- sample bit 7 + brcc unstuff6 ;[01] + andi x2, USBMASK ;[02] + eor x1, x2 ;[03] + subi x1, 1 ;[04] + ror shift ;[05] +didUnstuff7: + cpi shift, 0xfc ;[06] + brcc unstuff7 ;[07] + eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others + st y+, x3 ;[09] store data +rxBitLoop: + in x1, USBIN ;[00] [11] <-- sample bit 0/2/4 + andi x1, USBMASK ;[01] + eor x2, x1 ;[02] + andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7 + subi x2, 1 ;[04] + ror shift ;[05] + cpi shift, 0xfc ;[06] + brcc unstuffEven ;[07] +didUnstuffE: + lsr x3 ;[08] + lsr x3 ;[09] +rxbit1: + in x2, USBIN ;[00] [10] <-- sample bit 1/3/5 + andi x2, USBMASK ;[01] + breq se0 ;[02] + eor x1, x2 ;[03] + subi x1, 1 ;[04] + ror shift ;[05] + cpi shift, 0xfc ;[06] + brcc unstuffOdd ;[07] +didUnstuffO: + subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3 + brcs rxBitLoop ;[09] + + subi cnt, 1 ;[10] + in x1, USBIN ;[00] [11] <-- sample bit 6 + brcc rxByteLoop ;[01] + rjmp overflow + +macro POP_STANDARD ; 14 cycles + pop cnt + pop x4 + pop x3 + pop x2 + pop x1 + pop shift + pop bitcnt + endm +macro POP_RETI ; 7 cycles + pop YH + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies + +bitstuffN: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] + nop2 ;[7] + nop ;[9] + out USBOUT, x1 ;[10] <-- out + rjmp didStuffN ;[0] + +bitstuff6: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] Carry is zero due to brcc + rol shift ;[7] compensate for ror shift at branch destination + rjmp didStuff6 ;[8] + +bitstuff7: + ldi x2, 0 ;[2] Carry is zero due to brcc + rjmp didStuff7 ;[3] + + +sendNakAndReti: + ldi x3, USBPID_NAK ;[-18] + rjmp sendX3AndReti ;[-17] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov x3, cnt ;[-16] +sendX3AndReti: + ldi YL, 20 ;[-15] x3==r20 address is 20 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +;We don't match the transfer rate exactly (don't insert leap cycles every third +;byte) because the spec demands only 1.5% precision anyway. +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-7] <- acquire bus +; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-6] exor mask + ldi shift, 0x80 ;[-5] sync byte is first byte sent +txByteLoop: + ldi bitcnt, 0x35 ;[-4] [6] binary 0011 0101 +txBitLoop: + sbrs shift, 0 ;[-3] [7] + eor x1, x4 ;[-2] [8] + out USBOUT, x1 ;[-1] [9] <-- out N + ror shift ;[0] [10] + ror x2 ;[1] +didStuffN: + cpi x2, 0xfc ;[2] + brcc bitstuffN ;[3] + lsr bitcnt ;[4] + brcc txBitLoop ;[5] + brne txBitLoop ;[6] + + sbrs shift, 0 ;[7] + eor x1, x4 ;[8] +didStuff6: + out USBOUT, x1 ;[-1] [9] <-- out 6 + ror shift ;[0] [10] + ror x2 ;[1] + cpi x2, 0xfc ;[2] + brcc bitstuff6 ;[3] + ror shift ;[4] +didStuff7: + ror x2 ;[5] + sbrs x2, 7 ;[6] + eor x1, x4 ;[7] + nop ;[8] + cpi x2, 0xfc ;[9] + out USBOUT, x1 ;[-1][10] <-- out 7 + brcc bitstuff7 ;[0] [11] + ld shift, y+ ;[1] + dec cnt ;[3] + brne txByteLoop ;[4] +;make SE0: + cbr x1, USBMASK ;[5] prepare SE0 [spec says EOP may be 21 to 25 cycles] + lds x2, usbNewDeviceAddr;[6] + lsl x2 ;[8] we compare with left shifted address + subi YL, 20 + 2 ;[9] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[10] + out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[0] + sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< max 52 cycles interrupt disable +;max stack usage: [ret(2), r0, SREG, YL, YH, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 16.5 MHz -> 11 cycles per bit +; 16.3125 MHz < F_CPU < 16.6875 MHz (+/- 1.1%) +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], r0, YH, shift, x1, x2, x3, x4, cnt + push YL ;[-23] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-21] + push YL ;[-20] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-15] + rjmp foundK ;[-14] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-12] +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push r0 ;[-12] +; [---] ;[-11] + push YH ;[-10] +; [---] ;[-9] + lds YL, usbInputBufOffset;[-8] +; [---] ;[-7] + clr YH ;[-6] + subi YL, lo8(-(usbRxBuf));[-5] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-4] [rx loop init] + mov r0, x2 ;[-3] [rx loop init] + sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early) + rjmp haveTwoBitsK ;[-1] + pop YH ;[0] undo the pushes from before + pop r0 ;[2] + rjmp waitForK ;[4] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 22 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: ;[1] + push shift ;[1] + push x1 ;[3] + push x2 ;[5] + push x3 ;[7] + ldi shift, 0xff ;[9] [rx loop init] + ori x3, 0xff ;[10] [rx loop init] == ser x3, clear zero flag + + in x1, USBIN ;[11] <-- sample bit 0 + bst x1, USBMINUS ;[12] + bld shift, 0 ;[13] + push x4 ;[14] == phase +; [---] ;[15] + push cnt ;[16] +; [---] ;[17] + ldi phase, 0 ;[18] [rx loop init] + ldi cnt, USB_BUFSIZE;[19] [rx loop init] + rjmp rxbit1 ;[20] +; [---] ;[21] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +/* +byte oriented operations done during loop: +bit 0: store data +bit 1: SE0 check +bit 2: overflow check +bit 3: catch up +bit 4: rjmp to achieve conditional jump range +bit 5: PLL +bit 6: catch up +bit 7: jump, fixup bitstuff +; 87 [+ 2] cycles +------------------------------------------------------------------ +*/ +continueWithBit5: + in x2, USBIN ;[055] <-- bit 5 + eor r0, x2 ;[056] + or phase, r0 ;[057] + sbrc phase, USBMINUS ;[058] + lpm ;[059] optional nop3; modifies r0 + in phase, USBIN ;[060] <-- phase + eor x1, x2 ;[061] + bst x1, USBMINUS ;[062] + bld shift, 5 ;[063] + andi shift, 0x3f ;[064] + in x1, USBIN ;[065] <-- bit 6 + breq unstuff5 ;[066] *** unstuff escape + eor phase, x1 ;[067] + eor x2, x1 ;[068] + bst x2, USBMINUS ;[069] + bld shift, 6 ;[070] +didUnstuff6: ;[ ] + in r0, USBIN ;[071] <-- phase + cpi shift, 0x02 ;[072] + brlo unstuff6 ;[073] *** unstuff escape +didUnstuff5: ;[ ] + nop2 ;[074] +; [---] ;[075] + in x2, USBIN ;[076] <-- bit 7 + eor x1, x2 ;[077] + bst x1, USBMINUS ;[078] + bld shift, 7 ;[079] +didUnstuff7: ;[ ] + eor r0, x2 ;[080] + or phase, r0 ;[081] + in r0, USBIN ;[082] <-- phase + cpi shift, 0x04 ;[083] + brsh rxLoop ;[084] +; [---] ;[085] +unstuff7: ;[ ] + andi x3, ~0x80 ;[085] + ori shift, 0x80 ;[086] + in x2, USBIN ;[087] <-- sample stuffed bit 7 + nop ;[088] + rjmp didUnstuff7 ;[089] +; [---] ;[090] + ;[080] + +unstuff5: ;[067] + eor phase, x1 ;[068] + andi x3, ~0x20 ;[069] + ori shift, 0x20 ;[070] + in r0, USBIN ;[071] <-- phase + mov x2, x1 ;[072] + nop ;[073] + nop2 ;[074] +; [---] ;[075] + in x1, USBIN ;[076] <-- bit 6 + eor r0, x1 ;[077] + or phase, r0 ;[078] + eor x2, x1 ;[079] + bst x2, USBMINUS ;[080] + bld shift, 6 ;[081] no need to check bitstuffing, we just had one + in r0, USBIN ;[082] <-- phase + rjmp didUnstuff5 ;[083] +; [---] ;[084] + ;[074] + +unstuff6: ;[074] + andi x3, ~0x40 ;[075] + in x1, USBIN ;[076] <-- bit 6 again + ori shift, 0x40 ;[077] + nop2 ;[078] +; [---] ;[079] + rjmp didUnstuff6 ;[080] +; [---] ;[081] + ;[071] + +unstuff0: ;[013] + eor r0, x2 ;[014] + or phase, r0 ;[015] + andi x2, USBMASK ;[016] check for SE0 + in r0, USBIN ;[017] <-- phase + breq didUnstuff0 ;[018] direct jump to se0 would be too long + andi x3, ~0x01 ;[019] + ori shift, 0x01 ;[020] + mov x1, x2 ;[021] mov existing sample + in x2, USBIN ;[022] <-- bit 1 again + rjmp didUnstuff0 ;[023] +; [---] ;[024] + ;[014] + +unstuff1: ;[024] + eor r0, x1 ;[025] + or phase, r0 ;[026] + andi x3, ~0x02 ;[027] + in r0, USBIN ;[028] <-- phase + ori shift, 0x02 ;[029] + mov x2, x1 ;[030] + rjmp didUnstuff1 ;[031] +; [---] ;[032] + ;[022] + +unstuff2: ;[035] + eor r0, x2 ;[036] + or phase, r0 ;[037] + andi x3, ~0x04 ;[038] + in r0, USBIN ;[039] <-- phase + ori shift, 0x04 ;[040] + mov x1, x2 ;[041] + rjmp didUnstuff2 ;[042] +; [---] ;[043] + ;[033] + +unstuff3: ;[043] + in x2, USBIN ;[044] <-- bit 3 again + eor r0, x2 ;[045] + or phase, r0 ;[046] + andi x3, ~0x08 ;[047] + ori shift, 0x08 ;[048] + nop ;[049] + in r0, USBIN ;[050] <-- phase + rjmp didUnstuff3 ;[051] +; [---] ;[052] + ;[042] + +unstuff4: ;[053] + andi x3, ~0x10 ;[054] + in x1, USBIN ;[055] <-- bit 4 again + ori shift, 0x10 ;[056] + rjmp didUnstuff4 ;[057] +; [---] ;[058] + ;[048] + +rxLoop: ;[085] + eor x3, shift ;[086] reconstruct: x3 is 0 at bit locations we changed, 1 at others + in x1, USBIN ;[000] <-- bit 0 + st y+, x3 ;[001] +; [---] ;[002] + eor r0, x1 ;[003] + or phase, r0 ;[004] + eor x2, x1 ;[005] + in r0, USBIN ;[006] <-- phase + ser x3 ;[007] + bst x2, USBMINUS ;[008] + bld shift, 0 ;[009] + andi shift, 0xf9 ;[010] +rxbit1: ;[ ] + in x2, USBIN ;[011] <-- bit 1 + breq unstuff0 ;[012] *** unstuff escape + andi x2, USBMASK ;[013] SE0 check for bit 1 +didUnstuff0: ;[ ] Z only set if we detected SE0 in bitstuff + breq se0 ;[014] + eor r0, x2 ;[015] + or phase, r0 ;[016] + in r0, USBIN ;[017] <-- phase + eor x1, x2 ;[018] + bst x1, USBMINUS ;[019] + bld shift, 1 ;[020] + andi shift, 0xf3 ;[021] +didUnstuff1: ;[ ] + in x1, USBIN ;[022] <-- bit 2 + breq unstuff1 ;[023] *** unstuff escape + eor r0, x1 ;[024] + or phase, r0 ;[025] + subi cnt, 1 ;[026] overflow check + brcs overflow ;[027] + in r0, USBIN ;[028] <-- phase + eor x2, x1 ;[029] + bst x2, USBMINUS ;[030] + bld shift, 2 ;[031] + andi shift, 0xe7 ;[032] +didUnstuff2: ;[ ] + in x2, USBIN ;[033] <-- bit 3 + breq unstuff2 ;[034] *** unstuff escape + eor r0, x2 ;[035] + or phase, r0 ;[036] + eor x1, x2 ;[037] + bst x1, USBMINUS ;[038] + in r0, USBIN ;[039] <-- phase + bld shift, 3 ;[040] + andi shift, 0xcf ;[041] +didUnstuff3: ;[ ] + breq unstuff3 ;[042] *** unstuff escape + nop ;[043] + in x1, USBIN ;[044] <-- bit 4 + eor x2, x1 ;[045] + bst x2, USBMINUS ;[046] + bld shift, 4 ;[047] +didUnstuff4: ;[ ] + eor r0, x1 ;[048] + or phase, r0 ;[049] + in r0, USBIN ;[050] <-- phase + andi shift, 0x9f ;[051] + breq unstuff4 ;[052] *** unstuff escape + rjmp continueWithBit5;[053] +; [---] ;[054] + +macro POP_STANDARD ; 16 cycles + pop cnt + pop x4 + pop x3 + pop x2 + pop x1 + pop shift + pop YH + pop r0 + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies + +bitstuff7: + eor x1, x4 ;[4] + ldi x2, 0 ;[5] + nop2 ;[6] C is zero (brcc) + rjmp didStuff7 ;[8] + +bitstuffN: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] + lpm ;[7] 3 cycle NOP, modifies r0 + out USBOUT, x1 ;[10] <-- out + rjmp didStuffN ;[0] + +#define bitStatus x3 + +sendNakAndReti: + ldi cnt, USBPID_NAK ;[-19] + rjmp sendCntAndReti ;[-18] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov r0, cnt ;[-16] + ldi YL, 0 ;[-15] R0 address is 0 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-7] <- acquire bus +; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-6] exor mask + ldi shift, 0x80 ;[-5] sync byte is first byte sent + ldi bitStatus, 0xff ;[-4] init bit loop counter, works for up to 12 bytes +byteloop: +bitloop: + sbrs shift, 0 ;[8] [-3] + eor x1, x4 ;[9] [-2] + out USBOUT, x1 ;[10] [-1] <-- out + ror shift ;[0] + ror x2 ;[1] +didStuffN: + cpi x2, 0xfc ;[2] + brcc bitstuffN ;[3] + nop ;[4] + subi bitStatus, 37 ;[5] 256 / 7 ~=~ 37 + brcc bitloop ;[6] when we leave the loop, bitStatus has almost the initial value + sbrs shift, 0 ;[7] + eor x1, x4 ;[8] + ror shift ;[9] +didStuff7: + out USBOUT, x1 ;[10] <-- out + ror x2 ;[0] + cpi x2, 0xfc ;[1] + brcc bitstuff7 ;[2] + ld shift, y+ ;[3] + dec cnt ;[5] + brne byteloop ;[6] +;make SE0: + cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles] + lds x2, usbNewDeviceAddr;[8] + lsl x2 ;[10] we compare with left shifted address + out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + subi YL, 2 ;[0] Only assign address on data packets, not ACK/NAK in r0 + sbci YH, 0 ;[1] + breq skipAddrAssign ;[2] + sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 12 cycles per bit +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts +;register use in receive loop to receive the data bytes: +; shift assembles the byte currently being received +; x1 holds the D+ and D- line state +; x2 holds the previous line state +; cnt holds the number of bytes left in the receive buffer +; x3 holds the higher crc byte (see algorithm below) +; x4 is used as temporary register for the crc algorithm +; x5 is used for unstuffing: when unstuffing the last received bit is inverted in shift (to prevent further +; unstuffing calls. In the same time the corresponding bit in x5 is cleared to mark the bit as beening iverted +; zl lower crc value and crc table index +; zh used for crc table accesses + +;-------------------------------------------------------------------------------------------------------------- +; CRC mods: +; table driven crc checker, Z points to table in prog space +; ZL is the lower crc byte, x3 is the higher crc byte +; x4 is used as temp register to store different results +; the initialization of the crc register is not 0xFFFF but 0xFE54. This is because during the receipt of the +; first data byte an virtual zero data byte is added to the crc register, this results in the correct initial +; value of 0xFFFF at beginning of the second data byte before the first data byte is added to the crc. +; The magic number 0xFE54 results form the crc table: At tabH[0x54] = 0xFF = crcH (required) and +; tabL[0x54] = 0x01 -> crcL = 0x01 xor 0xFE = 0xFF +; bitcnt is renamed to x5 and is used for unstuffing purposes, the unstuffing works like in the 12MHz version +;-------------------------------------------------------------------------------------------------------------- +; CRC algorithm: +; The crc register is formed by x3 (higher byte) and ZL (lower byte). The algorithm uses a 'reversed' form +; i.e. that it takes the least significant bit first and shifts to the right. So in fact the highest order +; bit seen from the polynomial devision point of view is the lsb of ZL. (If this sounds strange to you i +; propose a research on CRC :-) ) +; Each data byte received is xored to ZL, the lower crc byte. This byte now builds the crc +; table index. Next the new high byte is loaded from the table and stored in x4 until we have space in x3 +; (its destination). +; Afterwards the lower table is loaded from the table and stored in ZL (the old index is overwritten as +; we don't need it anymore. In fact this is a right shift by 8 bits.) Now the old crc high value is xored +; to ZL, this is the second shift of the old crc value. Now x4 (the temp reg) is moved to x3 and the crc +; calculation is done. +; Prior to the first byte the two CRC register have to be initialized to 0xFFFF (as defined in usb spec) +; however the crc engine also runs during the receipt of the first byte, therefore x3 and zl are initialized +; to a magic number which results in a crc value of 0xFFFF after the first complete byte. +; +; This algorithm is split into the extra cycles of the different bits: +; bit7: XOR the received byte to ZL +; bit5: load the new high byte to x4 +; bit6: load the lower xor byte from the table, xor zl and x3, store result in zl (=the new crc low value) +; move x4 (the new high byte) to x3, the crc value is ready +; + + +macro POP_STANDARD ; 18 cycles + pop ZH + pop ZL + pop cnt + pop x5 + pop x3 + pop x2 + pop x1 + pop shift + pop x4 + endm +macro POP_RETI ; 7 cycles + pop YH + pop YL + out SREG, YL + pop YL + endm + +macro CRC_CLEANUP_AND_CHECK + ; the last byte has already been xored with the lower crc byte, we have to do the table lookup and xor + ; x3 is the higher crc byte, zl the lower one + ldi ZH, hi8(usbCrcTableHigh);[+1] get the new high byte from the table + lpm x2, Z ;[+2][+3][+4] + ldi ZH, hi8(usbCrcTableLow);[+5] get the new low xor byte from the table + lpm ZL, Z ;[+6][+7][+8] + eor ZL, x3 ;[+7] xor the old high byte with the value from the table, x2:ZL now holds the crc value + cpi ZL, 0x01 ;[+8] if the crc is ok we have a fixed remainder value of 0xb001 in x2:ZL (see usb spec) + brne ignorePacket ;[+9] detected a crc fault -> paket is ignored and retransmitted by the host + cpi x2, 0xb0 ;[+10] + brne ignorePacket ;[+11] detected a crc fault -> paket is ignored and retransmitted by the host + endm + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG, YH, [sofError], x4, shift, x1, x2, x3, x5, cnt, ZL, ZH + push YL ;[-28] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-26] + push YL ;[-25] + push YH ;[-23] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-17] + rjmp foundK ;[-16] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-15] +;{3, 5} after falling D- edge, average delay: 4 cycles +;bit0 should be at 30 (2.5 bits) for center sampling. Currently at 4 so 26 cylces till bit 0 sample +;use 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push x4 ;[-14] +; [---] ;[-13] + lds YL, usbInputBufOffset;[-12] used to toggle the two usb receive buffers +; [---] ;[-11] + clr YH ;[-10] + subi YL, lo8(-(usbRxBuf));[-9] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-8] [rx loop init] + push shift ;[-7] +; [---] ;[-6] + ldi shift, 0x80 ;[-5] the last bit is the end of byte marker for the pid receiver loop + clc ;[-4] the carry has to be clear for receipt of pid bit 0 + sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) + rjmp haveTwoBitsK ;[-2] + pop shift ;[-1] undo the push from before + pop x4 ;[1] + rjmp waitForK ;[3] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 24 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[0] + push x2 ;[2] + push x3 ;[4] crc high byte + ldi x2, 1< jump back and store the byte + ori shift, 0x01 ;[11] invert the last received bit to prevent furhter unstuffing + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + andi x5, 0xFE ;[1] mark this bit as inverted (will be corrected before storing shift) + eor x1, x2 ;[2] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[3] mask the interesting bits + breq stuffErr ;[4] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[5] the next bit expects the last state to be in x1 + rjmp didunstuff0 ;[6] + ;[7] jump delay of rjmp didunstuffX + +unstuff1: ;[11] this is the jump delay of breq unstuffX + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + ori shift, 0x02 ;[1] invert the last received bit to prevent furhter unstuffing + andi x5, 0xFD ;[2] mark this bit as inverted (will be corrected before storing shift) + eor x2, x1 ;[3] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[4] mask the interesting bits + breq stuffErr ;[5] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[6] the next bit expects the last state to be in x2 + nop2 ;[7] + ;[8] + rjmp didunstuff1 ;[9] + ;[10] jump delay of rjmp didunstuffX + +unstuff2: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x04 ;[10] invert the last received bit to prevent furhter unstuffing + andi x5, 0xFB ;[11] mark this bit as inverted (will be corrected before storing shift) + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[4] the next bit expects the last state to be in x1 + nop2 ;[5] + ;[6] + rjmp didunstuff2 ;[7] + ;[8] jump delay of rjmp didunstuffX + +unstuff3: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x08 ;[10] invert the last received bit to prevent furhter unstuffing + andi x5, 0xF7 ;[11] mark this bit as inverted (will be corrected before storing shift) + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[4] the next bit expects the last state to be in x2 + nop2 ;[5] + ;[6] + rjmp didunstuff3 ;[7] + ;[8] jump delay of rjmp didunstuffX + + + +; the include has to be here due to branch distance restirctions +#define __USE_CRC__ +#include "asmcommon.inc" + + + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies +; 7.5 bit times is 90 cycles. ...there is plenty of time + + +sendNakAndReti: + ldi x3, USBPID_NAK ;[-18] + rjmp sendX3AndReti ;[-17] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov x3, cnt ;[-16] +sendX3AndReti: + ldi YL, 20 ;[-15] x3==r20 address is 20 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent + +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-6] <- acquire bus + ldi x2, 0 ;[-6] init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-5] exor mask + ldi shift, 0x80 ;[-4] sync byte is first byte sent +txByteLoop: + ldi bitcnt, 0x40 ;[-3]=[9] binary 01000000 +txBitLoop: ; the loop sends the first 7 bits of the byte + sbrs shift, 0 ;[-2]=[10] if we have to send a 1 don't change the line state + eor x1, x4 ;[-1]=[11] + out USBOUT, x1 ;[0] + ror shift ;[1] + ror x2 ;[2] transfers the last sent bit to the stuffing history +didStuffN: + nop ;[3] + nop ;[4] + cpi x2, 0xfc ;[5] if we sent six consecutive ones + brcc bitstuffN ;[6] + lsr bitcnt ;[7] + brne txBitLoop ;[8] restart the loop while the 1 is still in the bitcount + +; transmit bit 7 + sbrs shift, 0 ;[9] + eor x1, x4 ;[10] +didStuff7: + ror shift ;[11] + out USBOUT, x1 ;[0] transfer bit 7 to the pins + ror x2 ;[1] move the bit into the stuffing history + cpi x2, 0xfc ;[2] + brcc bitstuff7 ;[3] + ld shift, y+ ;[4] get next byte to transmit + dec cnt ;[5] decrement byte counter + brne txByteLoop ;[7] if we have more bytes start next one + ;[8] branch delay + +;make SE0: + cbr x1, USBMASK ;[8] prepare SE0 [spec says EOP may be 25 to 30 cycles] + lds x2, usbNewDeviceAddr;[9] + lsl x2 ;[11] we compare with left shifted address + out USBOUT, x1 ;[0] <-- out SE0 -- from now 2 bits = 24 cycles until bus idle + subi YL, 20 + 2 ;[1] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[2] +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[3] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< +int main (int argc, char **argv) +{ + int i, j; + for (i=0; i<512; i++){ + unsigned short crc = i & 0xff; + for(j=0; j<8; j++) crc = (crc >> 1) ^ ((crc & 1) ? 0xa001 : 0); + if((i & 7) == 0) printf("\n.byte "); + printf("0x%02x, ", (i > 0xff ? (crc >> 8) : crc) & 0xff); + if(i == 255) printf("\n"); + } + return 0; +} + +// Use the following algorithm to compute CRC values: +ushort computeCrc(uchar *msg, uchar msgLen) +{ + uchar i; + ushort crc = 0xffff; + for(i = 0; i < msgLen; i++) + crc = usbCrcTable16[lo8(crc) ^ msg[i]] ^ hi8(crc); + return crc; +} +*/ + +.balign 256 +usbCrcTableLow: +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 + +; .balign 256 +usbCrcTableHigh: +.byte 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2 +.byte 0xC6, 0x06, 0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04 +.byte 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E +.byte 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8 +.byte 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A +.byte 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC +.byte 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6 +.byte 0xD2, 0x12, 0x13, 0xD3, 0x11, 0xD1, 0xD0, 0x10 +.byte 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32 +.byte 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4 +.byte 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE +.byte 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38 +.byte 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA +.byte 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C +.byte 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26 +.byte 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0 +.byte 0xA0, 0x60, 0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62 +.byte 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4 +.byte 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE +.byte 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68 +.byte 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA +.byte 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C +.byte 0xB4, 0x74, 0x75, 0xB5, 0x77, 0xB7, 0xB6, 0x76 +.byte 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0 +.byte 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92 +.byte 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54 +.byte 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E +.byte 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98 +.byte 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A +.byte 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C +.byte 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86 +.byte 0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 0x40 + diff --git a/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm20.inc b/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm20.inc new file mode 100644 index 0000000..303abaf --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiJoystick/usbdrvasm20.inc @@ -0,0 +1,360 @@ +/* Name: usbdrvasm20.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Jeroen Benschop + * Based on usbdrvasm16.inc from Christian Starkjohann + * Creation Date: 2008-03-05 + * Tabsize: 4 + * Copyright: (c) 2008 by Jeroen Benschop and OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm20.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 20 MHz version of the asssembler part of the USB driver. It +requires a 20 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! +*/ + +#define leap2 x3 +#ifdef __IAR_SYSTEMS_ASM__ +#define nextInst $+2 +#else +#define nextInst .+0 +#endif + +;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 20 MHz -> 13.333333 cycles per bit, 106.666667 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts +;register use in receive loop: +; shift assembles the byte currently being received +; x1 holds the D+ and D- line state +; x2 holds the previous line state +; x4 (leap) is used to add a leap cycle once every three bytes received +; X3 (leap2) is used to add a leap cycle once every three stuff bits received +; bitcnt is used to determine when a stuff bit is due +; cnt holds the number of bytes left in the receive buffer + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt + push YL ;[-28] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-26] + push YL ;[-25] + push YH ;[-23] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-19] + rjmp foundK ;[-18] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-16] +;{3, 5} after falling D- edge, average delay: 4 cycles +;bit0 should be at 34 for center sampling. Currently at 4 so 30 cylces till bit 0 sample +;use 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push bitcnt ;[-16] +; [---] ;[-15] + lds YL, usbInputBufOffset;[-14] +; [---] ;[-13] + clr YH ;[-12] + subi YL, lo8(-(usbRxBuf));[-11] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-10] [rx loop init] + push shift ;[-9] +; [---] ;[-8] + ldi shift,0x40 ;[-7] set msb to "1" so processing bit7 can be detected + nop2 ;[-6] +; [---] ;[-5] + ldi bitcnt, 5 ;[-4] [rx loop init] + sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) + rjmp haveTwoBitsK ;[-2] + pop shift ;[-1] undo the push from before + pop bitcnt ;[1] + rjmp waitForK ;[3] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 27 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[0] + push x2 ;[2] + push x3 ;[4] (leap2) + ldi leap2, 0x55 ;[6] add leap cycle on 2nd,5th,8th,... stuff bit + push x4 ;[7] == leap + ldi leap, 0x55 ;[9] skip leap cycle on 2nd,5th,8th,... byte received + push cnt ;[10] + ldi cnt, USB_BUFSIZE ;[12] [rx loop init] + ldi x2, 1< +#ifndef __IAR_SYSTEMS_ASM__ +# include +#endif + +#define __attribute__(arg) /* not supported on IAR */ + +#ifdef __IAR_SYSTEMS_ASM__ +# define __ASSEMBLER__ /* IAR does not define standard macro for asm */ +#endif + +#ifdef __HAS_ELPM__ +# define PROGMEM __farflash +#else +# define PROGMEM __flash +#endif + +#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr)) + +/* The following definitions are not needed by the driver, but may be of some + * help if you port a gcc based project to IAR. + */ +#define cli() __disable_interrupt() +#define sei() __enable_interrupt() +#define wdt_reset() __watchdog_reset() +#define _BV(x) (1 << (x)) + +/* assembler compatibility macros */ +#define nop2 rjmp $+2 /* jump to next instruction */ +#define XL r26 +#define XH r27 +#define YL r28 +#define YH r29 +#define ZL r30 +#define ZH r31 +#define lo8(x) LOW(x) +#define hi8(x) (((x)>>8) & 0xff) /* not HIGH to allow XLINK to make a proper range check */ + +/* Depending on the device you use, you may get problems with the way usbdrv.h + * handles the differences between devices. Since IAR does not use #defines + * for MCU registers, we can't check for the existence of a particular + * register with an #ifdef. If the autodetection mechanism fails, include + * definitions for the required USB_INTR_* macros in your usbconfig.h. See + * usbconfig-prototype.h and usbdrv.h for details. + */ + +/* ------------------------------------------------------------------------- */ +#elif __CODEVISIONAVR__ /* check for CodeVision AVR */ +/* ------------------------------------------------------------------------- */ +/* This port is not working (yet) */ + +/* #define F_CPU _MCU_CLOCK_FREQUENCY_ seems to be defined automatically */ + +#include +#include + +#define __attribute__(arg) /* not supported on IAR */ + +#define PROGMEM __flash +#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr)) + +#ifndef __ASSEMBLER__ +static inline void cli(void) +{ + #asm("cli"); +} +static inline void sei(void) +{ + #asm("sei"); +} +#endif +#define _delay_ms(t) delay_ms(t) +#define _BV(x) (1 << (x)) +#define USB_CFG_USE_SWITCH_STATEMENT 1 /* macro for if() cascase fails for unknown reason */ + +#define macro .macro +#define endm .endmacro +#define nop2 rjmp .+0 /* jump to next instruction */ + +/* ------------------------------------------------------------------------- */ +#else /* default development environment is avr-gcc/avr-libc */ +/* ------------------------------------------------------------------------- */ + +#include +#ifdef __ASSEMBLER__ +# define _VECTOR(N) __vector_ ## N /* io.h does not define this for asm */ +#else +# include +#endif + +#define USB_READ_FLASH(addr) pgm_read_byte(addr) + +#define macro .macro +#define endm .endm +#define nop2 rjmp .+0 /* jump to next instruction */ + +#endif /* development environment */ + +/* for conveniecne, ensure that PRG_RDB exists */ +#ifndef PRG_RDB +# define PRG_RDB(addr) USB_READ_FLASH(addr) +#endif +#endif /* __usbportability_h_INCLUDED__ */ diff --git a/hardware/digistump/avr/libraries/DigiMouse/ArduinoNotes.txt b/hardware/digistump/avr/libraries/DigiMouse/ArduinoNotes.txt new file mode 100644 index 0000000..e05398b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/ArduinoNotes.txt @@ -0,0 +1,34 @@ +Notes On Integrating AVRUSB with Arduino +======================================== + +* Note the license(s) under which AVRUSB is distributed. + +* See also: http://code.rancidbacon.com/ProjectLogArduinoUSB + +* Note: The pins we use on the PCB (not protoboard) hardware shield are: + + INT0 == PD2 == IC Pin 4 == Arduino Digital Pin 2 == D+ + + ---- == PD4 == -------- == Arduino Digital Pin 4 == D- + + ---- == PD5 == -------- == Arduino Digital Pin 5 == pull-up + + (DONE: Change to not use PD3 so INT1 is left free?) + +* In order to compile a valid 'usbconfig.h' file must exit. The content of this + file will vary depending on whether the device is a generic USB device, + generic HID device or specific class of HID device for example. + + The file 'usbconfig-prototype.h' can be used as a starting point, however + it might be easier to use the 'usbconfig.h' from one of the example projects. + + TODO: Specify the settings that need to be changed to match the shield + design we use. + +* (NOTE: Initial 'usbconfig.h' used will be based on the file from + 'HIDKeys.2007-03-29'.) (Note: Have now upgraded to V-USB 2009-08-22.) + +* Versions of the Arduino IDE prior to 0018 won't compile our library + so it needs to be pre-compiled with: + + avr-g++ -Wall -Os -I. -DF_CPU=16000000 -mmcu=atmega168 -c usbdrvasm.S -c usbdrv.c diff --git a/hardware/digistump/avr/libraries/DigiMouse/Changelog.txt b/hardware/digistump/avr/libraries/DigiMouse/Changelog.txt new file mode 100644 index 0000000..655a9d4 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/Changelog.txt @@ -0,0 +1,296 @@ +This file documents changes in the firmware-only USB driver for atmel's AVR +microcontrollers. New entries are always appended to the end of the file. +Scroll down to the bottom to see the most recent changes. + +2005-04-01: + - Implemented endpoint 1 as interrupt-in endpoint. + - Moved all configuration options to usbconfig.h which is not part of the + driver. + - Changed interface for usbVendorSetup(). + - Fixed compatibility with ATMega8 device. + - Various minor optimizations. + +2005-04-11: + - Changed interface to application: Use usbFunctionSetup(), usbFunctionRead() + and usbFunctionWrite() now. Added configuration options to choose which + of these functions to compile in. + - Assembler module delivers receive data non-inverted now. + - Made register and bit names compatible with more AVR devices. + +2005-05-03: + - Allow address of usbRxBuf on any memory page as long as the buffer does + not cross 256 byte page boundaries. + - Better device compatibility: works with Mega88 now. + - Code optimization in debugging module. + - Documentation updates. + +2006-01-02: + - Added (free) default Vendor- and Product-IDs bought from voti.nl. + - Added USBID-License.txt file which defines the rules for using the free + shared VID/PID pair. + - Added Readme.txt to the usbdrv directory which clarifies administrative + issues. + +2006-01-25: + - Added "configured state" to become more standards compliant. + - Added "HALT" state for interrupt endpoint. + - Driver passes the "USB Command Verifier" test from usb.org now. + - Made "serial number" a configuration option. + - Minor optimizations, we now recommend compiler option "-Os" for best + results. + - Added a version number to usbdrv.h + +2006-02-03: + - New configuration variable USB_BUFFER_SECTION for the memory section where + the USB rx buffer will go. This defaults to ".bss" if not defined. Since + this buffer MUST NOT cross 256 byte pages (not even touch a page at the + end), the user may want to pass a linker option similar to + "-Wl,--section-start=.mybuffer=0x800060". + - Provide structure for usbRequest_t. + - New defines for USB constants. + - Prepared for HID implementations. + - Increased data size limit for interrupt transfers to 8 bytes. + - New macro usbInterruptIsReady() to query interrupt buffer state. + +2006-02-18: + - Ensure that the data token which is sent as an ack to an OUT transfer is + always zero sized. This fixes a bug where the host reports an error after + sending an out transfer to the device, although all data arrived at the + device. + - Updated docs in usbdrv.h to reflect changed API in usbFunctionWrite(). + +* Release 2006-02-20 + + - Give a compiler warning when compiling with debugging turned on. + - Added Oleg Semyonov's changes for IAR-cc compatibility. + - Added new (optional) functions usbDeviceConnect() and usbDeviceDisconnect() + (also thanks to Oleg!). + - Rearranged tests in usbPoll() to save a couple of instructions in the most + likely case that no actions are pending. + - We need a delay between the SET ADDRESS request until the new address + becomes active. This delay was handled in usbPoll() until now. Since the + spec says that the delay must not exceed 2ms, previous versions required + aggressive polling during the enumeration phase. We have now moved the + handling of the delay into the interrupt routine. + - We must not reply with NAK to a SETUP transaction. We can only achieve this + by making sure that the rx buffer is empty when SETUP tokens are expected. + We therefore don't pass zero sized data packets from the status phase of + a transfer to usbPoll(). This change MAY cause troubles if you rely on + receiving a less than 8 bytes long packet in usbFunctionWrite() to + identify the end of a transfer. usbFunctionWrite() will NEVER be called + with a zero length. + +* Release 2006-03-14 + + - Improved IAR C support: tiny memory model, more devices + - Added template usbconfig.h file under the name usbconfig-prototype.h + +* Release 2006-03-26 + + - Added provision for one more interrupt-in endpoint (endpoint 3). + - Added provision for one interrupt-out endpoint (endpoint 1). + - Added flowcontrol macros for USB. + - Added provision for custom configuration descriptor. + - Allow ANY two port bits for D+ and D-. + - Merged (optional) receive endpoint number into global usbRxToken variable. + - Use USB_CFG_IOPORTNAME instead of USB_CFG_IOPORT. We now construct the + variable name from the single port letter instead of computing the address + of related ports from the output-port address. + +* Release 2006-06-26 + + - Updated documentation in usbdrv.h and usbconfig-prototype.h to reflect the + new features. + - Removed "#warning" directives because IAR does not understand them. Use + unused static variables instead to generate a warning. + - Do not include when compiling with IAR. + - Introduced USB_CFG_DESCR_PROPS_* in usbconfig.h to configure how each + USB descriptor should be handled. It is now possible to provide descriptor + data in Flash, RAM or dynamically at runtime. + - STALL is now a status in usbTxLen* instead of a message. We can now conform + to the spec and leave the stall status pending until it is cleared. + - Made usbTxPacketCnt1 and usbTxPacketCnt3 public. This allows the + application code to reset data toggling on interrupt pipes. + +* Release 2006-07-18 + + - Added an #if !defined __ASSEMBLER__ to the warning in usbdrv.h. This fixes + an assembler error. + - usbDeviceDisconnect() takes pull-up resistor to high impedance now. + +* Release 2007-02-01 + + - Merged in some code size improvements from usbtiny (thanks to Dick + Streefland for these optimizations!) + - Special alignment requirement for usbRxBuf not required any more. Thanks + again to Dick Streefland for this hint! + - Reverted to "#warning" instead of unused static variables -- new versions + of IAR CC should handle this directive. + - Changed Open Source license to GNU GPL v2 in order to make linking against + other free libraries easier. We no longer require publication of the + circuit diagrams, but we STRONGLY encourage it. If you improve the driver + itself, PLEASE grant us a royalty free license to your changes for our + commercial license. + +* Release 2007-03-29 + + - New configuration option "USB_PUBLIC" in usbconfig.h. + - Set USB version number to 1.10 instead of 1.01. + - Code used USB_CFG_DESCR_PROPS_STRING_DEVICE and + USB_CFG_DESCR_PROPS_STRING_PRODUCT inconsistently. Changed all occurrences + to USB_CFG_DESCR_PROPS_STRING_PRODUCT. + - New assembler module for 16.5 MHz RC oscillator clock with PLL in receiver + code. + - New assembler module for 16 MHz crystal. + - usbdrvasm.S contains common code only, clock-specific parts have been moved + to usbdrvasm12.S, usbdrvasm16.S and usbdrvasm165.S respectively. + +* Release 2007-06-25 + + - 16 MHz module: Do SE0 check in stuffed bits as well. + +* Release 2007-07-07 + + - Define hi8(x) for IAR compiler to limit result to 8 bits. This is necessary + for negative values. + - Added 15 MHz module contributed by V. Bosch. + - Interrupt vector name can now be configured. This is useful if somebody + wants to use a different hardware interrupt than INT0. + +* Release 2007-08-07 + + - Moved handleIn3 routine in usbdrvasm16.S so that relative jump range is + not exceeded. + - More config options: USB_RX_USER_HOOK(), USB_INITIAL_DATATOKEN, + USB_COUNT_SOF + - USB_INTR_PENDING can now be a memory address, not just I/O + +* Release 2007-09-19 + + - Split out common parts of assembler modules into separate include file + - Made endpoint numbers configurable so that given interface definitions + can be matched. See USB_CFG_EP3_NUMBER in usbconfig-prototype.h. + - Store endpoint number for interrupt/bulk-out so that usbFunctionWriteOut() + can handle any number of endpoints. + - Define usbDeviceConnect() and usbDeviceDisconnect() even if no + USB_CFG_PULLUP_IOPORTNAME is defined. Directly set D+ and D- to 0 in this + case. + +* Release 2007-12-01 + + - Optimize usbDeviceConnect() and usbDeviceDisconnect() for less code size + when USB_CFG_PULLUP_IOPORTNAME is not defined. + +* Release 2007-12-13 + + - Renamed all include-only assembler modules from *.S to *.inc so that + people don't add them to their project sources. + - Distribute leap bits in tx loop more evenly for 16 MHz module. + - Use "macro" and "endm" instead of ".macro" and ".endm" for IAR + - Avoid compiler warnings for constant expr range by casting some values in + USB descriptors. + +* Release 2008-01-21 + + - Fixed bug in 15 and 16 MHz module where the new address set with + SET_ADDRESS was already accepted at the next NAK or ACK we send, not at + the next data packet we send. This caused problems when the host polled + too fast. Thanks to Alexander Neumann for his help and patience debugging + this issue! + +* Release 2008-02-05 + + - Fixed bug in 16.5 MHz module where a register was used in the interrupt + handler before it was pushed. This bug was introduced with version + 2007-09-19 when common parts were moved to a separate file. + - Optimized CRC routine (thanks to Reimar Doeffinger). + +* Release 2008-02-16 + + - Removed outdated IAR compatibility stuff (code sections). + - Added hook macros for USB_RESET_HOOK() and USB_SET_ADDRESS_HOOK(). + - Added optional routine usbMeasureFrameLength() for calibration of the + internal RC oscillator. + +* Release 2008-02-28 + + - USB_INITIAL_DATATOKEN defaults to USBPID_DATA1 now, which means that we + start with sending USBPID_DATA0. + - Changed defaults in usbconfig-prototype.h + - Added free USB VID/PID pair for MIDI class devices + - Restructured AVR-USB as separate package, not part of PowerSwitch any more. + +* Release 2008-04-18 + + - Restructured usbdrv.c so that it is easier to read and understand. + - Better code optimization with gcc 4. + - If a second interrupt in endpoint is enabled, also add it to config + descriptor. + - Added config option for long transfers (above 254 bytes), see + USB_CFG_LONG_TRANSFERS in usbconfig.h. + - Added 20 MHz module contributed by Jeroen Benschop. + +* Release 2008-05-13 + + - Fixed bug in libs-host/hiddata.c function usbhidGetReport(): length + was not incremented, pointer to length was incremented instead. + - Added code to command line tool(s) which claims an interface. This code + is disabled by default, but may be necessary on newer Linux kernels. + - Added usbconfig.h option "USB_CFG_CHECK_DATA_TOGGLING". + - New header "usbportability.h" prepares ports to other development + environments. + - Long transfers (above 254 bytes) did not work when usbFunctionRead() was + used to supply the data. Fixed this bug. [Thanks to Alexander Neumann!] + - In hiddata.c (example code for sending/receiving data over HID), use + USB_RECIP_DEVICE instead of USB_RECIP_INTERFACE for control transfers so + that we need not claim the interface. + - in usbPoll() loop 20 times polling for RESET state instead of 10 times. + This accounts for the higher clock rates we now support. + - Added a module for 12.8 MHz RC oscillator with PLL in receiver loop. + - Added hook to SOF code so that oscillator can be tuned to USB frame clock. + - Added timeout to waitForJ loop. Helps preventing unexpected hangs. + - Added example code for oscillator tuning to libs-device (thanks to + Henrik Haftmann for the idea to this routine). + - Implemented option USB_CFG_SUPPRESS_INTR_CODE. + +* Release 2008-10-22 + + - Fixed libs-device/osctune.h: OSCCAL is memory address on ATMega88 and + similar, not offset of 0x20 needs to be added. + - Allow distribution under GPLv3 for those who have to link against other + code distributed under GPLv3. + +* Release 2008-11-26 + + - Removed libusb-win32 dependency for hid-data example in Makefile.windows. + It was never required and confused many people. + - Added extern uchar usbRxToken to usbdrv.h. + - Integrated a module with CRC checks at 18 MHz by Lukas Schrittwieser. + +* Release 2009-03-23 + + - Hid-mouse example used settings from hid-data example, fixed that. + - Renamed project to V-USB due to a trademark issue with Atmel(r). + - Changed CommercialLicense.txt and USBID-License.txt to make the + background of USB ID registration clearer. + +* Release 2009-04-15 + + - Changed CommercialLicense.txt to reflect the new range of PIDs from + Jason Kotzin. + - Removed USBID-License.txt in favor of USB-IDs-for-free.txt and + USB-ID-FAQ.txt + - Fixed a bug in the 12.8 MHz module: End Of Packet decection was made in + the center between bit 0 and 1 of each byte. This is where the data lines + are expected to change and the sampled data may therefore be nonsense. + We therefore check EOP ONLY if bits 0 AND 1 have both been read as 0 on D-. + - Fixed a bitstuffing problem in the 16 MHz module: If bit 6 was stuffed, + the unstuffing code in the receiver routine was 1 cycle too long. If + multiple bytes had the unstuffing in bit 6, the error summed up until the + receiver was out of sync. + - Included option for faster CRC routine. + Thanks to Slawomir Fras (BoskiDialer) for this code! + - Updated bits in Configuration Descriptor's bmAttributes according to + USB 1.1 (in particular bit 7, it is a must-be-set bit now). + +* Release 2009-08-22 diff --git a/hardware/digistump/avr/libraries/DigiMouse/CommercialLicense.txt b/hardware/digistump/avr/libraries/DigiMouse/CommercialLicense.txt new file mode 100644 index 0000000..11d07d9 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/CommercialLicense.txt @@ -0,0 +1,166 @@ +V-USB Driver Software License Agreement +Version 2009-08-03 + +THIS LICENSE AGREEMENT GRANTS YOU CERTAIN RIGHTS IN A SOFTWARE. YOU CAN +ENTER INTO THIS AGREEMENT AND ACQUIRE THE RIGHTS OUTLINED BELOW BY PAYING +THE AMOUNT ACCORDING TO SECTION 4 ("PAYMENT") TO OBJECTIVE DEVELOPMENT. + + +1 DEFINITIONS + +1.1 "OBJECTIVE DEVELOPMENT" shall mean OBJECTIVE DEVELOPMENT Software GmbH, +Grosse Schiffgasse 1A/7, 1020 Wien, AUSTRIA. + +1.2 "You" shall mean the Licensee. + +1.3 "V-USB" shall mean all files included in the package distributed under +the name "vusb" by OBJECTIVE DEVELOPMENT (http://www.obdev.at/vusb/) +unless otherwise noted. This includes the firmware-only USB device +implementation for Atmel AVR microcontrollers, some simple device examples +and host side software examples and libraries. + + +2 LICENSE GRANTS + +2.1 Source Code. OBJECTIVE DEVELOPMENT shall furnish you with the source +code of V-USB. + +2.2 Distribution and Use. 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The responsible courts in Vienna/Austria will have +exclusive jurisdiction regarding all disputes in connection with this +agreement. + diff --git a/hardware/digistump/avr/libraries/DigiMouse/DigiMouse.h b/hardware/digistump/avr/libraries/DigiMouse/DigiMouse.h new file mode 100644 index 0000000..65e9845 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/DigiMouse.h @@ -0,0 +1,307 @@ +/* + * Based on Obdev's AVRUSB code and under the same license. + * + * TODO: Make a proper file header. :-) + * Modified for Digispark by Digistump + * And now modified by Sean Murphy (duckythescientist) from a keyboard device to a mouse device + * Most of the credit for the joystick code should go to Raphaël Assénat + * And now mouse credit is due to Yiyin Ma and Abby Lin of Cornell + */ +#ifndef __DigiMouse_h__ +#define __DigiMouse_h__ + +#define REPORT_SIZE 4 + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "usbdrv.h" +//#include "devdesc.h" +#include "oddebug.h" +#include "usbconfig.h" + +static const uchar *rt_usbHidReportDescriptor = NULL; +static uchar rt_usbHidReportDescriptorSize = 0; +static const uchar *rt_usbDeviceDescriptor = NULL; +static uchar rt_usbDeviceDescriptorSize = 0; + +// TODO: Work around Arduino 12 issues better. +//#include +//#undef int() + +typedef uint8_t byte; + +/* What was most recently read from the controller */ +static unsigned char last_built_report[REPORT_SIZE]; + +/* What was most recently sent to the host */ +static unsigned char last_sent_report[REPORT_SIZE]; + +uchar reportBuffer[REPORT_SIZE]; + +// report frequency set to default of 50hz +#define DIGIMOUSE_DEFAULT_REPORT_INTERVAL 20 +static unsigned char must_report = 0; +static unsigned char idle_rate = DIGIMOUSE_DEFAULT_REPORT_INTERVAL / 4; // in units of 4ms +// new minimum report frequency system: +static unsigned long last_report_time = 0; + + + +const PROGMEM unsigned char mouse_usbHidReportDescriptor[] = { /* USB report descriptor */ + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x02, // USAGE (Mouse) + 0xa1, 0x01, // COLLECTION (Application) + 0x09, 0x01, // USAGE_PAGE (Pointer) + 0xa1, 0x00, // COLLECTION (Physical) + 0x05, 0x09, // USAGE_PAGE (Button) + 0x19, 0x01, // USAGE_MINIMUM (Button 1) + 0x29, 0x03, // USAGE_MAXIMUM (Button 3) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x95, 0x03, // REPORT_COUNT (3) + 0x75, 0x01, // REPORT_SIZE (1) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x05, // REPORT_SIZE (5) + 0x81, 0x01, // Input(Cnst) + 0x05, 0x01, // USAGE_PAGE(Generic Desktop) + 0x09, 0x30, // USAGE(X) + 0x09, 0x31, // USAGE(Y) + 0x15, 0x81, // LOGICAL_MINIMUM (-127) + 0x25, 0x7f, // LOGICAL_MAXIMUM (127) + 0x75, 0x08, // REPORT_SIZE (8) + 0x95, 0x02, // REPORT_COUNT (2) + 0x81, 0x06, // INPUT (Data,Var,Rel) + 0x09, 0x38, // Usage (Wheel) + 0x95, 0x01, // Report Count (1), + 0x81, 0x06, // Input (Data, Variable, Relative) + 0xc0, // END_COLLECTION + 0xc0 // END_COLLECTION +}; + + +#define USBDESCR_DEVICE 1 + +unsigned const char usbDescrDevice[] PROGMEM = { /* USB device descriptor */ + 18, /* sizeof(usbDescrDevice): length of descriptor in bytes */ + USBDESCR_DEVICE, /* descriptor type */ + 0x01, 0x01, /* USB version supported */ + USB_CFG_DEVICE_CLASS, + USB_CFG_DEVICE_SUBCLASS, + 0, /* protocol */ + 8, /* max packet size */ + USB_CFG_VENDOR_ID, /* 2 bytes */ + USB_CFG_DEVICE_ID, /* 2 bytes */ + USB_CFG_DEVICE_VERSION, /* 2 bytes */ +#if USB_CFG_VENDOR_NAME_LEN + 1, /* manufacturer string index */ +#else + 0, /* manufacturer string index */ +#endif +#if USB_CFG_DEVICE_NAME_LEN + 2, /* product string index */ +#else + 0, /* product string index */ +#endif +#if USB_CFG_SERIAL_NUMBER_LENGTH + 3, /* serial number string index */ +#else + 0, /* serial number string index */ +#endif + 1, /* number of configurations */ +}; + + +void buildReport(unsigned char *reportBuf) { + if (reportBuf != NULL) { + memcpy(reportBuf, last_built_report, REPORT_SIZE); + } + + memcpy(last_sent_report, last_built_report, REPORT_SIZE); +} + +void clearMove() { + // because we send deltas in movement, so when we send them, we clear them + last_built_report[1] = 0; + last_built_report[2] = 0; + last_built_report[3] = 0; + last_sent_report[1] = 0; + last_sent_report[2] = 0; + last_sent_report[3] = 0; +} + + + + + + +class DigiMouseDevice { + public: + DigiMouseDevice () { + // this timer stuff doesn't even make sense - it seems like someone got some code for Timer1 + // and haphazardly changed the 1's in the register names to 0's, but the two timers don't work + // the same way, so this code doesn't do what it says at all. Is it even useful to have? + /* configure timer 0 for a rate of 16M5/(1024 * 256) = 62.94 Hz (~16ms) */ + //TCCR0A = 5; /* timer 0 prescaler: 1024 */ + + + + //TIMSK &= !(1= (idle_rate * 4 /* in units of 4ms - usb spec stuff */)) { + last_report_time += idle_rate * 4; + must_report = 1; + } + + // if the report has changed, try force an update anyway + if (memcmp(last_built_report, last_sent_report, REPORT_SIZE)) { + must_report = 1; + } + + // if we want to send a report, signal the host computer to ask us for it with a usb 'interrupt' + if (must_report) { + if (usbInterruptIsReady()) { + must_report = 0; + buildReport(reportBuffer); // put data into reportBuffer + clearMove(); // clear deltas + usbSetInterrupt(reportBuffer, REPORT_SIZE); + } + } + } + + // delay while updating until we are finished + void delay(long milli) { + unsigned long last = millis(); + while (milli > 0) { + unsigned long now = millis(); + milli -= now - last; + last = now; + update(); + } + } + + void moveX(char deltaX) { + if (deltaX == -128) deltaX = -127; + last_built_report[1] = *(reinterpret_cast(&deltaX)); + } + + void moveY(char deltaY) { + if (deltaY == -128) deltaY = -127; + last_built_report[2] = *(reinterpret_cast(&deltaY)); + } + + void scroll(char deltaS) { + if (deltaS == -128) deltaS = -127; + last_built_report[3] = *(reinterpret_cast(&deltaS)); + } + + void move(char deltaX, char deltaY, char deltaS) { + if (deltaX == -128) deltaX = -127; + if (deltaY == -128) deltaY = -127; + if (deltaS == -128) deltaS = -127; + last_built_report[1] = *(reinterpret_cast(&deltaX)); + last_built_report[2] = *(reinterpret_cast(&deltaY)); + last_built_report[3] = *(reinterpret_cast(&deltaS)); + } + + void setButtons(unsigned char buttons) { + last_built_report[0] = buttons; + } + + void setValues(unsigned char values[]) { + memcpy(last_built_report, values, REPORT_SIZE); + } + + //private: TODO: Make friend? + // what does this even mean? -- Bluebie +}; + +// create the global singleton DigiMouse +DigiMouseDevice DigiMouse = DigiMouseDevice(); + + +#ifdef __cplusplus +extern "C"{ +#endif + // USB_PUBLIC uchar usbFunctionSetup + + uchar usbFunctionSetup(uchar data[8]) { + usbRequest_t *rq = (usbRequest_t *)data; + + usbMsgPtr = reportBuffer; + + if ((rq->bmRequestType & USBRQ_TYPE_MASK) == USBRQ_TYPE_CLASS) { /* class request type */ + if (rq->bRequest == USBRQ_HID_GET_REPORT) { /* wValue: ReportType (highbyte), ReportID (lowbyte) */ + /* we only have one report type, so don't look at wValue */ + //curGamepad->buildReport(reportBuffer); + //return curGamepad->report_size; + return REPORT_SIZE; + } else if (rq->bRequest == USBRQ_HID_GET_IDLE) { + usbMsgPtr = &idle_rate; + return 1; + } else if (rq->bRequest == USBRQ_HID_SET_IDLE) { + idle_rate = rq->wValue.bytes[1]; + } + } else { + /* no vendor specific requests implemented */ + } + return 0; + } + + uchar usbFunctionDescriptor(struct usbRequest *rq) { + if ((rq->bmRequestType & USBRQ_TYPE_MASK) != USBRQ_TYPE_STANDARD) { + return 0; + } + + if (rq->bRequest == USBRQ_GET_DESCRIPTOR) { + // USB spec 9.4.3, high byte is descriptor type + switch (rq->wValue.bytes[1]) { + case USBDESCR_DEVICE: + usbMsgPtr = rt_usbDeviceDescriptor; + return rt_usbDeviceDescriptorSize; + break; + + case USBDESCR_HID_REPORT: + usbMsgPtr = rt_usbHidReportDescriptor; + return rt_usbHidReportDescriptorSize; + break; + } + } + + return 0; + } + +#ifdef __cplusplus +} // extern "C" +#endif + + +#endif // __DigiKeyboard_h__ diff --git a/hardware/digistump/avr/libraries/DigiMouse/License.txt b/hardware/digistump/avr/libraries/DigiMouse/License.txt new file mode 100644 index 0000000..4460cfb --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/License.txt @@ -0,0 +1,361 @@ +OBJECTIVE DEVELOPMENT GmbH's V-USB driver software is distributed under the +terms and conditions of the GNU GPL version 2 or the GNU GPL version 3. It is +your choice whether you apply the terms of version 2 or version 3. The full +text of GPLv2 is included below. In addition to the requirements in the GPL, +we STRONGLY ENCOURAGE you to do the following: + +(1) Publish your entire project on a web site and drop us a note with the URL. +Use the form at http://www.obdev.at/vusb/feedback.html for your submission. + +(2) Adhere to minimum publication standards. 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See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/hardware/digistump/avr/libraries/DigiMouse/MouseReadme.txt b/hardware/digistump/avr/libraries/DigiMouse/MouseReadme.txt new file mode 100644 index 0000000..4cb63c1 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/MouseReadme.txt @@ -0,0 +1,13 @@ +MouseReadme.txt + +This library is for the attiny85 running tiny core Arduino (e.g. the Digispark) + +This implements a USB HID mouse device with three buttons and scroll +The code was borrowed mostly from the Digispark Keyboard library and from Raphaël Assénat's code on using an atmega8 as a Nintendo Gamecube/N64 controller to USB bridge: http://www.raphnet.net/electronique/gc_n64_usb/index_en.php and from Yiyin Ma and Abby Lin of Cornell https://instruct1.cit.cornell.edu/courses/ee476/FinalProjects/s2007/ayl26_ym82/ayl26_ym82/index.htm +Raphaël's work is truly marvelous, and Ma and Lin did a nice job with the mouse software. + +Because most of this code is coming from other projects with GNU GPL, I am letting my modifications inherit the same protection. A copy of this license is included in the source. + +As to the use of this code in Arduino, #include "DigiMouse.h" as you would any other library. See the included sample for use of the functions. + +My name is Sean Murphy, and you can find me many places on the internet by the handle duckythescientist (including the Digispark forums). \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigiMouse/Readme.txt b/hardware/digistump/avr/libraries/DigiMouse/Readme.txt new file mode 100644 index 0000000..a010d97 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/Readme.txt @@ -0,0 +1,158 @@ +This is the Readme file to Objective Development's firmware-only USB driver +for Atmel AVR microcontrollers. For more information please visit +http://www.obdev.at/vusb/ + +This directory contains the USB firmware only. Copy it as-is to your own +project and add all .c and .S files to your project (these files are marked +with an asterisk in the list below). Then copy usbconfig-prototype.h as +usbconfig.h to your project and edit it according to your configuration. + + +TECHNICAL DOCUMENTATION +======================= +The technical documentation (API) for the firmware driver is contained in the +file "usbdrv.h". Please read all of it carefully! Configuration options are +documented in "usbconfig-prototype.h". + +The driver consists of the following files: + Readme.txt ............. The file you are currently reading. + Changelog.txt .......... Release notes for all versions of the driver. + usbdrv.h ............... Driver interface definitions and technical docs. +* usbdrv.c ............... High level language part of the driver. Link this + module to your code! +* usbdrvasm.S ............ Assembler part of the driver. This module is mostly + a stub and includes one of the usbdrvasm*.S files + depending on processor clock. Link this module to + your code! + usbdrvasm*.inc ......... Assembler routines for particular clock frequencies. + Included by usbdrvasm.S, don't link it directly! + asmcommon.inc .......... Common assembler routines. Included by + usbdrvasm*.inc, don't link it directly! + usbconfig-prototype.h .. Prototype for your own usbdrv.h file. +* oddebug.c .............. Debug functions. Only used when DEBUG_LEVEL is + defined to a value greater than 0. Link this module + to your code! + oddebug.h .............. Interface definitions of the debug module. + usbportability.h ....... Header with compiler-dependent stuff. + usbdrvasm.asm .......... Compatibility stub for IAR-C-compiler. Use this + module instead of usbdrvasm.S when you assembler + with IAR's tools. + License.txt ............ Open Source license for this driver. + CommercialLicense.txt .. Optional commercial license for this driver. + USB-ID-FAQ.txt ......... General infos about USB Product- and Vendor-IDs. + USB-IDs-for-free.txt ... List and terms of use for free shared PIDs. + +(*) ... These files should be linked to your project. + + +CPU CORE CLOCK FREQUENCY +======================== +We supply assembler modules for clock frequencies of 12 MHz, 12.8 MHz, 15 MHz, +16 MHz, 16.5 MHz 18 MHz and 20 MHz. Other clock rates are not supported. The +actual clock rate must be configured in usbdrv.h unless you use the default +12 MHz. + +12 MHz Clock +This is the traditional clock rate of V-USB because it's the lowest clock +rate where the timing constraints of the USB spec can be met. + +15 MHz Clock +Similar to 12 MHz, but some NOPs inserted. On the other hand, the higher clock +rate allows for some loops which make the resulting code size somewhat smaller +than the 12 MHz version. + +16 MHz Clock +This clock rate has been added for users of the Arduino board and other +ready-made boards which come with a fixed 16 MHz crystal. It's also an option +if you need the slightly higher clock rate for performance reasons. Since +16 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code +is somewhat tricky and has to insert a leap cycle every third byte. + +12.8 MHz and 16.5 MHz Clock +The assembler modules for these clock rates differ from the other modules +because they have been built for an RC oscillator with only 1% precision. The +receiver code inserts leap cycles to compensate for clock deviations. 1% is +also the precision which can be achieved by calibrating the internal RC +oscillator of the AVR. Please note that only AVRs with internal 64 MHz PLL +oscillator can reach 16.5 MHz with the RC oscillator. This includes the very +popular ATTiny25, ATTiny45, ATTiny85 series as well as the ATTiny26. Almost +all AVRs can reach 12.8 MHz, although this is outside the specified range. + +See the EasyLogger example at http://www.obdev.at/vusb/easylogger.html for +code which calibrates the RC oscillator based on the USB frame clock. + +18 MHz Clock +This module is closer to the USB specification because it performs an on the +fly CRC check for incoming packets. Packets with invalid checksum are +discarded as required by the spec. If you also implement checks for data +PID toggling on application level (see option USB_CFG_CHECK_DATA_TOGGLING +in usbconfig.h for more info), this ensures data integrity. Due to the CRC +tables and alignment requirements, this code is bigger than modules for other +clock rates. To activate this module, you must define USB_CFG_CHECK_CRC to 1 +and USB_CFG_CLOCK_KHZ to 18000 in usbconfig.h. + +20 MHz Clock +This module is for people who won't do it with less than the maximum. Since +20 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code +uses similar tricks as the 16 MHz module to insert leap cycles. + + +USB IDENTIFIERS +=============== +Every USB device needs a vendor- and a product-identifier (VID and PID). VIDs +are obtained from usb.org for a price of 1,500 USD. Once you have a VID, you +can assign PIDs at will. + +Since an entry level cost of 1,500 USD is too high for most small companies +and hobbyists, we provide some VID/PID pairs for free. See the file +USB-IDs-for-free.txt for details. + +Objective Development also has some license offerings which include product +IDs. See http://www.obdev.at/vusb/ for details. + + +DEVELOPMENT SYSTEM +================== +This driver has been developed and optimized for the GNU compiler version 3 +(gcc 3). It does work well with gcc 4, but with bigger code size. We recommend +that you use the GNU compiler suite because it is freely available. V-USB +has also been ported to the IAR compiler and assembler. It has been tested +with IAR 4.10B/W32 and 4.12A/W32 on an ATmega8 with the "small" and "tiny" +memory model. Not every release is tested with IAR CC and the driver may +therefore fail to compile with IAR. Please note that gcc is more efficient for +usbdrv.c because this module has been deliberately optimized for gcc. + + +USING V-USB FOR FREE +==================== +The AVR firmware driver is published under the GNU General Public License +Version 2 (GPL2) and the GNU General Public License Version 3 (GPL3). It is +your choice whether you apply the terms of version 2 or version 3. + +If you decide for the free GPL2 or GPL3, we STRONGLY ENCOURAGE you to do the +following things IN ADDITION to the obligations from the GPL: + +(1) Publish your entire project on a web site and drop us a note with the URL. +Use the form at http://www.obdev.at/vusb/feedback.html for your submission. +If you don't have a web site, you can publish the project in obdev's +documentation wiki at +http://www.obdev.at/goto.php?t=vusb-wiki&p=hosted-projects. + +(2) Adhere to minimum publication standards. Please include AT LEAST: + - a circuit diagram in PDF, PNG or GIF format + - full source code for the host software + - a Readme.txt file in ASCII format which describes the purpose of the + project and what can be found in which directories and which files + - a reference to http://www.obdev.at/vusb/ + +(3) If you improve the driver firmware itself, please give us a free license +to your modifications for our commercial license offerings. + + +COMMERCIAL LICENSES FOR V-USB +============================= +If you don't want to publish your source code under the terms of the GPL, +you can simply pay money for V-USB. As an additional benefit you get +USB PIDs for free, reserved exclusively to you. See the file +"CommercialLicense.txt" for details. + diff --git a/hardware/digistump/avr/libraries/DigiMouse/USB-ID-FAQ.txt b/hardware/digistump/avr/libraries/DigiMouse/USB-ID-FAQ.txt new file mode 100644 index 0000000..d1de8fb --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/USB-ID-FAQ.txt @@ -0,0 +1,149 @@ +Version 2009-08-22 + +========================== +WHY DO WE NEED THESE IDs? +========================== + +USB is more than a low level protocol for data transport. It also defines a +common set of requests which must be understood by all devices. And as part +of these common requests, the specification defines data structures, the +USB Descriptors, which are used to describe the properties of the device. + +From the perspective of an operating system, it is therefore possible to find +out basic properties of a device (such as e.g. the manufacturer and the name +of the device) without a device-specific driver. This is essential because +the operating system can choose a driver to load based on this information +(Plug-And-Play). + +Among the most important properties in the Device Descriptor are the USB +Vendor- and Product-ID. Both are 16 bit integers. The most simple form of +driver matching is based on these IDs. The driver announces the Vendor- and +Product-IDs of the devices it can handle and the operating system loads the +appropriate driver when the device is connected. + +It is obvious that this technique only works if the pair Vendor- plus +Product-ID is unique: Only devices which require the same driver can have the +same pair of IDs. + + +===================================================== +HOW DOES THE USB STANDARD ENSURE THAT IDs ARE UNIQUE? +===================================================== + +Since it is so important that USB IDs are unique, the USB Implementers Forum, +Inc. (usb.org) needs a way to enforce this legally. It is not forbidden by +law to build a device and assign it any random numbers as IDs. Usb.org +therefore needs an agreement to regulate the use of USB IDs. The agreement +binds only parties who agreed to it, of course. Everybody else is free to use +any numbers for their IDs. + +So how can usb.org ensure that every manufacturer of USB devices enters into +an agreement with them? They do it via trademark licensing. Usb.org has +registered the trademark "USB", all associated logos and related terms. If +you want to put an USB logo on your product or claim that it is USB +compliant, you must license these trademarks from usb.org. And this is where +you enter into an agreement. See the "USB-IF Trademark License Agreement and +Usage Guidelines for the USB-IF Logo" at +http://www.usb.org/developers/logo_license/. + +Licensing the USB trademarks requires that you buy a USB Vendor-ID from +usb.org (one-time fee of ca. 2,000 USD), that you become a member of usb.org +(yearly fee of ca. 4,000 USD) and that you meet all the technical +specifications from the USB spec. + +This means that most hobbyists and small companies will never be able to +become USB compliant, just because membership is so expensive. And you can't +be compliant with a driver based on V-USB anyway, because the AVR's port pins +don't meet the electrical specifications for USB. So, in principle, all +hobbyists and small companies are free to choose any random numbers for their +IDs. They have nothing to lose... + +There is one exception worth noting, though: If you use a sub-component which +implements USB, the vendor of the sub-components may guarantee USB +compliance. This might apply to some or all of FTDI's solutions. + + +======================================================================= +WHY SHOULD YOU OBTAIN USB IDs EVEN IF YOU DON'T LICENSE USB TRADEMARKS? +======================================================================= + +You have learned in the previous section that you are free to choose any +numbers for your IDs anyway. So why not do exactly this? There is still the +technical issue. If you choose IDs which are already in use by somebody else, +operating systems will load the wrong drivers and your device won't work. +Even if you choose IDs which are not currently in use, they may be in use in +the next version of the operating system or even after an automatic update. + +So what you need is a pair of Vendor- and Product-IDs for which you have the +guarantee that no USB compliant product uses them. This implies that no +operating system will ever ship with drivers responsible for these IDs. + + +============================================== +HOW DOES OBJECTIVE DEVELOPMENT HANDLE USB IDs? +============================================== + +Objective Development gives away pairs of USB-IDs with their V-USB licenses. +In order to ensure that these IDs are unique, Objective Development has an +agreement with the company/person who has bought the USB Vendor-ID from +usb.org. This agreement ensures that a range of USB Product-IDs is reserved +for assignment by Objective Development and that the owner of the Vendor-ID +won't give it to anybody else. + +This means that you have to trust three parties to ensure uniqueness of +your IDs: + + - Objective Development, that they don't give the same PID to more than + one person. + - The owner of the Vendor-ID that they don't assign PIDs from the range + assigned to Objective Development to anybody else. + - Usb.org that they don't assign the same Vendor-ID a second time. + + +================================== +WHO IS THE OWNER OF THE VENDOR-ID? +================================== + +Objective Development has obtained ranges of USB Product-IDs under two +Vendor-IDs: Under Vendor-ID 5824 from Wouter van Ooijen (Van Ooijen +Technische Informatica, www.voti.nl) and under Vendor-ID 8352 from Jason +Kotzin (Clay Logic, www.claylogic.com). Both VID owners have received their +Vendor-ID directly from usb.org. + + +========================================================================= +CAN I USE USB-IDs FROM OBJECTIVE DEVELOPMENT WITH OTHER DRIVERS/HARDWARE? +========================================================================= + +The short answer is: Yes. All you get is a guarantee that the IDs are never +assigned to anybody else. What more do you need? + + +============================ +WHAT ABOUT SHARED ID PAIRS? +============================ + +Objective Development has reserved some PID/VID pairs for shared use. You +have no guarantee of uniqueness for them, except that no USB compliant device +uses them. In order to avoid technical problems, we must ensure that all +devices with the same pair of IDs use the same driver on kernel level. For +details, see the file USB-IDs-for-free.txt. + + +====================================================== +I HAVE HEARD THAT SUB-LICENSING OF USB-IDs IS ILLEGAL? +====================================================== + +A 16 bit integer number cannot be protected by copyright laws. It is not +sufficiently complex. And since none of the parties involved entered into the +USB-IF Trademark License Agreement, we are not bound by this agreement. So +there is no reason why it should be illegal to sub-license USB-IDs. + + +============================================= +WHO IS LIABLE IF THERE ARE INCOMPATIBILITIES? +============================================= + +Objective Development disclaims all liabilities which might arise from the +assignment of IDs. If you guarantee product features to your customers +without proper disclaimer, YOU are liable for that. diff --git a/hardware/digistump/avr/libraries/DigiMouse/USB-IDs-for-free.txt b/hardware/digistump/avr/libraries/DigiMouse/USB-IDs-for-free.txt new file mode 100644 index 0000000..2f4d59a --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/USB-IDs-for-free.txt @@ -0,0 +1,148 @@ +Version 2009-08-22 + +=========================== +FREE USB-IDs FOR SHARED USE +=========================== + +Objective Development has reserved a set of USB Product-IDs for use according +to the guidelines outlined below. For more information about the concept of +USB IDs please see the file USB-ID-FAQ.txt. Objective Development guarantees +that the IDs listed below are not used by any USB compliant devices. + + +==================== +MECHANISM OF SHARING +==================== + +From a technical point of view, two different devices can share the same USB +Vendor- and Product-ID if they require the same driver on operating system +level. We make use of this fact by assigning separate IDs for various device +classes. On application layer, devices must be distinguished by their textual +name or serial number. We offer separate sets of IDs for discrimination by +textual name and for serial number. + +Examples for shared use of USB IDs are included with V-USB in the "examples" +subdirectory. + + +====================================== +IDs FOR DISCRIMINATION BY TEXTUAL NAME +====================================== + +If you use one of the IDs listed below, your device and host-side software +must conform to these rules: + +(1) The USB device MUST provide a textual representation of the manufacturer +and product identification. The manufacturer identification MUST be available +at least in USB language 0x0409 (English/US). + +(2) The textual manufacturer identification MUST contain either an Internet +domain name (e.g. "mycompany.com") registered and owned by you, or an e-mail +address under your control (e.g. "myname@gmx.net"). You can embed the domain +name or e-mail address in any string you like, e.g. "Objective Development +http://www.obdev.at/vusb/". + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(4) You may choose any string for the textual product identification, as long +as this string is unique within the scope of your textual manufacturer +identification. + +(5) Application side device look-up MUST be based on the textual manufacturer +and product identification in addition to VID/PID matching. The driver +matching MUST be a comparison of the entire strings, NOT a sub-string match. + +(6) For devices which implement a particular USB device class (e.g. HID), the +operating system's default class driver MUST be used. If an operating system +driver for Vendor Class devices is needed, this driver must be libusb or +libusb-win32 (see http://libusb.org/ and +http://libusb-win32.sourceforge.net/). + +Table if IDs for discrimination by textual name: + +PID dec (hex) | VID dec (hex) | Description of use +==============+===============+============================================ +1500 (0x05dc) | 5824 (0x16c0) | For Vendor Class devices with libusb +--------------+---------------+-------------------------------------------- +1503 (0x05df) | 5824 (0x16c0) | For generic HID class devices (which are + | | NOT mice, keyboards or joysticks) +--------------+---------------+-------------------------------------------- +1505 (0x05e1) | 5824 (0x16c0) | For CDC-ACM class devices (modems) +--------------+---------------+-------------------------------------------- +1508 (0x05e4) | 5824 (0x16c0) | For MIDI class devices +--------------+---------------+-------------------------------------------- + +Note that Windows caches the textual product- and vendor-description for +mice, keyboards and joysticks. Name-bsed discrimination is therefore not +recommended for these device classes. + + +======================================= +IDs FOR DISCRIMINATION BY SERIAL NUMBER +======================================= + +If you use one of the IDs listed below, your device and host-side software +must conform to these rules: + +(1) The USB device MUST provide a textual representation of the serial +number. The serial number string MUST be available at least in USB language +0x0409 (English/US). + +(2) The serial number MUST start with either an Internet domain name (e.g. +"mycompany.com") registered and owned by you, or an e-mail address under your +control (e.g. "myname@gmx.net"), both terminated with a colon (":") character. +You MAY append any string you like for further discrimination of your devices. + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(5) Application side device look-up MUST be based on the serial number string +in addition to VID/PID matching. The matching must start at the first +character of the serial number string and include the colon character +terminating your domain or e-mail address. It MAY stop anywhere after that. + +(6) For devices which implement a particular USB device class (e.g. HID), the +operating system's default class driver MUST be used. If an operating system +driver for Vendor Class devices is needed, this driver must be libusb or +libusb-win32 (see http://libusb.org/ and +http://libusb-win32.sourceforge.net/). + +Table if IDs for discrimination by serial number string: + +PID dec (hex) | VID dec (hex) | Description of use +===============+===============+=========================================== +10200 (0x27d8) | 5824 (0x16c0) | For Vendor Class devices with libusb +---------------+---------------+------------------------------------------- +10201 (0x27d9) | 5824 (0x16c0) | For generic HID class devices (which are + | | NOT mice, keyboards or joysticks) +---------------+---------------+------------------------------------------- +10202 (0x27da) | 5824 (0x16c0) | For USB Mice +---------------+---------------+------------------------------------------- +10203 (0x27db) | 5824 (0x16c0) | For USB Keyboards +---------------+---------------+------------------------------------------- +10204 (0x27db) | 5824 (0x16c0) | For USB Joysticks +---------------+---------------+------------------------------------------- +10205 (0x27dc) | 5824 (0x16c0) | For CDC-ACM class devices (modems) +---------------+---------------+------------------------------------------- +10206 (0x27dd) | 5824 (0x16c0) | For MIDI class devices +---------------+---------------+------------------------------------------- + + +================= +ORIGIN OF USB-IDs +================= + +OBJECTIVE DEVELOPMENT Software GmbH has obtained all VID/PID pairs listed +here from Wouter van Ooijen (see www.voti.nl) for exclusive disposition. +Wouter van Ooijen has obtained the VID from the USB Implementers Forum, Inc. +(see www.usb.org). The VID is registered for the company name "Van Ooijen +Technische Informatica". + + +========== +DISCLAIMER +========== + +OBJECTIVE DEVELOPMENT Software GmbH disclaims all liability for any +problems which are caused by the shared use of these VID/PID pairs. diff --git a/hardware/digistump/avr/libraries/DigiMouse/USBID-License.txt b/hardware/digistump/avr/libraries/DigiMouse/USBID-License.txt new file mode 100644 index 0000000..c40be92 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/USBID-License.txt @@ -0,0 +1,154 @@ +Royalty-Free Non-Exclusive Use of USB Product-IDs +================================================= + +Version 2009-04-13 + +Strictly speaking, this is not a license. You can't give a license to use +a simple number (such as e.g. 1500) for any purpose. This is a set of rules +which should make it possible to build USB devices without the requirement +for individual USB IDs. If you break one of the rules, you will run into +technical problems sooner or later, but you don't risk legal trouble. + + +OBJECTIVE DEVELOPMENT Software GmbH hereby grants you the non-exclusive +right to use four USB.org vendor-ID (VID) / product-ID (PID) pairs with +products based on Objective Development's firmware-only USB driver for +Atmel AVR microcontrollers: + + * VID = 5824 (=0x16c0) / PID = 1500 (=0x5dc) for devices implementing no + USB device class (vendor-class devices with USB class = 0xff). Devices + using this pair will be referred to as "VENDOR CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1503 (=0x5df) for HID class devices + (excluding mice and keyboards). Devices using this pair will be referred + to as "HID CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1505 (=0x5e1) for CDC class modem devices + Devices using this pair will be referred to as "CDC-ACM CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1508 (=0x5e4) for MIDI class devices + Devices using this pair will be referred to as "MIDI CLASS" devices. + +Since the granted right is non-exclusive, the same VID/PID pairs may be +used by many companies and individuals for different products. To avoid +conflicts, your device and host driver software MUST adhere to the rules +outlined below. + +OBJECTIVE DEVELOPMENT Software GmbH has obtained these VID/PID pairs from +Wouter van Ooijen (see www.voti.nl) for exclusive disposition. Wouter van +Ooijen has obtained the VID from the USB Implementers Forum, Inc. +(see www.usb.org). The VID is registered for the company name +"Van Ooijen Technische Informatica". + + +RULES AND RESTRICTIONS +====================== + +(1) The USB device MUST provide a textual representation of the +manufacturer and product identification. The manufacturer identification +MUST be available at least in USB language 0x0409 (English/US). + +(2) The textual manufacturer identification MUST contain either an Internet +domain name (e.g. "mycompany.com") registered and owned by you, or an +e-mail address under your control (e.g. "myname@gmx.net"). You can embed +the domain name or e-mail address in any string you like, e.g. "Objective +Development http://www.obdev.at/vusb/". + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(4) You may choose any string for the textual product identification, as +long as this string is unique within the scope of your textual manufacturer +identification. + +(5) Matching of device-specific drivers MUST be based on the textual +manufacturer and product identification in addition to the usual VID/PID +matching. This means that operating system features which are based on +VID/PID matching only (e.g. Windows kernel level drivers, automatic actions +when the device is plugged in etc) MUST NOT be used. The driver matching +MUST be a comparison of the entire strings, NOT a sub-string match. For +CDC-ACM CLASS and MIDI CLASS devices, a generic class driver should be used +and the matching is based on the USB device class. + +(6) The extent to which VID/PID matching is allowed for non device-specific +drivers or features depends on the operating system and particular VID/PID +pair used: + + * Mac OS X, Linux, FreeBSD and other Unixes: No VID/PID matching is + required and hence no VID/PID-only matching is allowed at all. + + * Windows: The operating system performs VID/PID matching for the kernel + level driver. You are REQUIRED to use libusb-win32 (see + http://libusb-win32.sourceforge.net/) as the kernel level driver for + VENDOR CLASS devices. HID CLASS devices all use the generic HID class + driver shipped with Windows, except mice and keyboards. You therefore + MUST NOT use any of the shared VID/PID pairs for mice or keyboards. + CDC-ACM CLASS devices require a ".inf" file which matches on the VID/PID + pair. This ".inf" file MUST load the "usbser" driver to configure the + device as modem (COM-port). + +(7) OBJECTIVE DEVELOPMENT Software GmbH disclaims all liability for any +problems which are caused by the shared use of these VID/PID pairs. You +have been warned that the sharing of VID/PID pairs may cause problems. If +you want to avoid them, get your own VID/PID pair for exclusive use. + + +HOW TO IMPLEMENT THESE RULES +============================ + +The following rules are for VENDOR CLASS and HID CLASS devices. CDC-ACM +CLASS and MIDI CLASS devices use the operating system's class driver and +don't need a custom driver. + +The host driver MUST iterate over all devices with the given VID/PID +numbers in their device descriptors and query the string representation for +the manufacturer name in USB language 0x0409 (English/US). It MUST compare +the ENTIRE string with your textual manufacturer identification chosen in +(2) above. A substring search for your domain or e-mail address is NOT +acceptable. The driver MUST NOT touch the device (other than querying the +descriptors) unless the strings match. + +For all USB devices with matching VID/PID and textual manufacturer +identification, the host driver must query the textual product +identification and string-compare it with the name of the product it can +control. It may only initialize the device if the product matches exactly. + +Objective Development provides examples for these matching rules with the +"PowerSwitch" project (using libusb) and with the "Automator" project +(using Windows calls on Windows and libusb on Unix). + + +Technical Notes: +================ + +Sharing the same VID/PID pair among devices is possible as long as ALL +drivers which match the VID/PID also perform matching on the textual +identification strings. This is easy on all operating systems except +Windows, since Windows establishes a static connection between the VID/PID +pair and a kernel level driver. All devices with the same VID/PID pair must +therefore use THE SAME kernel level driver. + +We therefore demand that you use libusb-win32 for VENDOR CLASS devices. +This is a generic kernel level driver which allows all types of USB access +for user space applications. This is only a partial solution of the +problem, though, because different device drivers may come with different +versions of libusb-win32 and they may not work with the libusb version of +the respective other driver. You are therefore encouraged to test your +driver against a broad range of libusb-win32 versions. Do not use new +features in new versions, or check for their existence before you use them. +When a new libusb-win32 becomes available, make sure that your driver is +compatible with it. + +For HID CLASS devices it is necessary that all those devices bind to the +same kernel driver: Microsoft's generic USB HID driver. This is true for +all HID devices except those with a specialized driver. Currently, the only +HIDs with specialized drivers are mice and keyboards. You therefore MUST +NOT use a shared VID/PID with mouse and keyboard devices. + +Sharing the same VID/PID among different products is unusual and probably +violates the USB specification. If you do it, you do it at your own risk. + +To avoid possible incompatibilities, we highly recommend that you get your +own VID/PID pair if you intend to sell your product. Objective +Development's commercial licenses for V-USB include a PID for +unrestricted exclusive use. diff --git a/hardware/digistump/avr/libraries/DigiMouse/asmcommon.inc b/hardware/digistump/avr/libraries/DigiMouse/asmcommon.inc new file mode 100644 index 0000000..07d692b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/asmcommon.inc @@ -0,0 +1,188 @@ +/* Name: asmcommon.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2007-11-05 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id$ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file contains assembler code which is shared among the USB driver +implementations for different CPU cocks. Since the code must be inserted +in the middle of the module, it's split out into this file and #included. + +Jump destinations called from outside: + sofError: Called when no start sequence was found. + se0: Called when a package has been successfully received. + overflow: Called when receive buffer overflows. + doReturn: Called after sending data. + +Outside jump destinations used by this module: + waitForJ: Called to receive an already arriving packet. + sendAckAndReti: + sendNakAndReti: + sendCntAndReti: + usbSendAndReti: + +The following macros must be defined before this file is included: + .macro POP_STANDARD + .endm + .macro POP_RETI + .endm +*/ + +#define token x1 + +overflow: + ldi x2, 1< + +void setup() { + DigiMouse.begin(); //start or reenumerate USB - BREAKING CHANGE from old versions that didn't require this + //while(!DigiMouse.isConnected()) {} //don't run sketch until USB is connected +} + +void loop() { + // If not using plentiful DigiMouse.delay(), make sure to call + // DigiMouse.update() at least every 50ms + + // move across the screen + // these are signed chars + DigiMouse.moveY(10); //down 10 + DigiMouse.delay(500); + DigiMouse.moveX(20); //right 20 + DigiMouse.delay(500); + DigiMouse.scroll(5); + DigiMouse.delay(500); + + // or DigiMouse.move(X, Y, scroll) works + + // three buttons are the three LSBs of an unsigned char + DigiMouse.setButtons(1<<0); //left click + DigiMouse.delay(500); + DigiMouse.setButtons(0); //unclick all + DigiMouse.delay(500); + + //or you can use these functions to click + DigiMouse.rightClick(); + DigiMouse.leftClick(); + DigiMouse.middleClick(); + + //for compatability with other libraries you can also use DigiMouse.move(X, Y, scroll, buttons) +} diff --git a/hardware/digistump/avr/libraries/DigiMouse/keywords.txt b/hardware/digistump/avr/libraries/DigiMouse/keywords.txt new file mode 100644 index 0000000..3144c7b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/keywords.txt @@ -0,0 +1,7 @@ +DigiMouse KEYWORD1 +update KEYWORD2 +moveX KEYWORD2 +moveY KEYWORD2 +scroll KEYWORD2 +move KEYWORD2 +setButtons KEYWORD2 \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigiMouse/oddebug.c b/hardware/digistump/avr/libraries/DigiMouse/oddebug.c new file mode 100644 index 0000000..945457c --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/oddebug.c @@ -0,0 +1,50 @@ +/* Name: oddebug.c + * Project: AVR library + * Author: Christian Starkjohann + * Creation Date: 2005-01-16 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: oddebug.c 692 2008-11-07 15:07:40Z cs $ + */ + +#include "oddebug.h" + +#if DEBUG_LEVEL > 0 + +#warning "Never compile production devices with debugging enabled" + +static void uartPutc(char c) +{ + while(!(ODDBG_USR & (1 << ODDBG_UDRE))); /* wait for data register empty */ + ODDBG_UDR = c; +} + +static uchar hexAscii(uchar h) +{ + h &= 0xf; + if(h >= 10) + h += 'a' - (uchar)10 - '0'; + h += '0'; + return h; +} + +static void printHex(uchar c) +{ + uartPutc(hexAscii(c >> 4)); + uartPutc(hexAscii(c)); +} + +void odDebug(uchar prefix, uchar *data, uchar len) +{ + printHex(prefix); + uartPutc(':'); + while(len--){ + uartPutc(' '); + printHex(*data++); + } + uartPutc('\r'); + uartPutc('\n'); +} + +#endif diff --git a/hardware/digistump/avr/libraries/DigiMouse/oddebug.h b/hardware/digistump/avr/libraries/DigiMouse/oddebug.h new file mode 100644 index 0000000..d61309d --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/oddebug.h @@ -0,0 +1,123 @@ +/* Name: oddebug.h + * Project: AVR library + * Author: Christian Starkjohann + * Creation Date: 2005-01-16 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: oddebug.h 692 2008-11-07 15:07:40Z cs $ + */ + +#ifndef __oddebug_h_included__ +#define __oddebug_h_included__ + +/* +General Description: +This module implements a function for debug logs on the serial line of the +AVR microcontroller. Debugging can be configured with the define +'DEBUG_LEVEL'. If this macro is not defined or defined to 0, all debugging +calls are no-ops. If it is 1, DBG1 logs will appear, but not DBG2. If it is +2, DBG1 and DBG2 logs will be printed. + +A debug log consists of a label ('prefix') to indicate which debug log created +the output and a memory block to dump in hex ('data' and 'len'). +*/ + + +#ifndef F_CPU +# define F_CPU 12000000 /* 12 MHz */ +#endif + +/* make sure we have the UART defines: */ +#include "usbportability.h" + +#ifndef uchar +# define uchar unsigned char +#endif + +#if DEBUG_LEVEL > 0 && !(defined TXEN || defined TXEN0) /* no UART in device */ +# warning "Debugging disabled because device has no UART" +# undef DEBUG_LEVEL +#endif + +#ifndef DEBUG_LEVEL +# define DEBUG_LEVEL 0 +#endif + +/* ------------------------------------------------------------------------- */ + +#if DEBUG_LEVEL > 0 +# define DBG1(prefix, data, len) odDebug(prefix, data, len) +#else +# define DBG1(prefix, data, len) +#endif + +#if DEBUG_LEVEL > 1 +# define DBG2(prefix, data, len) odDebug(prefix, data, len) +#else +# define DBG2(prefix, data, len) +#endif + +/* ------------------------------------------------------------------------- */ + +#if DEBUG_LEVEL > 0 +extern void odDebug(uchar prefix, uchar *data, uchar len); + +/* Try to find our control registers; ATMEL likes to rename these */ + +#if defined UBRR +# define ODDBG_UBRR UBRR +#elif defined UBRRL +# define ODDBG_UBRR UBRRL +#elif defined UBRR0 +# define ODDBG_UBRR UBRR0 +#elif defined UBRR0L +# define ODDBG_UBRR UBRR0L +#endif + +#if defined UCR +# define ODDBG_UCR UCR +#elif defined UCSRB +# define ODDBG_UCR UCSRB +#elif defined UCSR0B +# define ODDBG_UCR UCSR0B +#endif + +#if defined TXEN +# define ODDBG_TXEN TXEN +#else +# define ODDBG_TXEN TXEN0 +#endif + +#if defined USR +# define ODDBG_USR USR +#elif defined UCSRA +# define ODDBG_USR UCSRA +#elif defined UCSR0A +# define ODDBG_USR UCSR0A +#endif + +#if defined UDRE +# define ODDBG_UDRE UDRE +#else +# define ODDBG_UDRE UDRE0 +#endif + +#if defined UDR +# define ODDBG_UDR UDR +#elif defined UDR0 +# define ODDBG_UDR UDR0 +#endif + +static inline void odDebugInit(void) +{ + ODDBG_UCR |= (1< + +#ifndef uchar +#define uchar unsigned char +#endif + +/* ------------------------------------------------------------------------- */ +/* ------------------------ Oscillator Calibration ------------------------- */ +/* ------------------------------------------------------------------------- */ + +/* Calibrate the RC oscillator. Our timing reference is the Start Of Frame + * signal (a single SE0 bit) repeating every millisecond immediately after + * a USB RESET. We first do a binary search for the OSCCAL value and then + * optimize this value with a neighboorhod search. + */ +void calibrateOscillator(void) +{ +uchar step = 128; +uchar trialValue = 0, optimumValue; +int x, optimumDev, targetValue = (unsigned)(1499 * (double)F_CPU / 10.5e6 + 0.5); + + /* do a binary search: */ + do{ + OSCCAL = trialValue + step; + x = usbMeasureFrameLength(); /* proportional to current real frequency */ + if(x < targetValue) /* frequency still too low */ + trialValue += step; + step >>= 1; + }while(step > 0); + /* We have a precision of +/- 1 for optimum OSCCAL here */ + /* now do a neighborhood search for optimum value */ + optimumValue = trialValue; + optimumDev = x; /* this is certainly far away from optimum */ + for(OSCCAL = trialValue - 1; OSCCAL <= trialValue + 1; OSCCAL++){ + x = usbMeasureFrameLength() - targetValue; + if(x < 0) + x = -x; + if(x < optimumDev){ + optimumDev = x; + optimumValue = OSCCAL; + } + } + OSCCAL = optimumValue; +} +/* +Note: This calibration algorithm may try OSCCAL values of up to 192 even if +the optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +You may replace this search algorithm with any other algorithm you like if +you have additional constraints such as a maximum CPU clock. +For version 5.x RC oscillators (those with a split range of 2x128 steps, e.g. +ATTiny25, ATTiny45, ATTiny85), it may be useful to search for the optimum in +both regions. +*/ diff --git a/hardware/digistump/avr/libraries/DigiMouse/osccal.c.lst b/hardware/digistump/avr/libraries/DigiMouse/osccal.c.lst new file mode 100644 index 0000000..336a049 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/osccal.c.lst @@ -0,0 +1,106 @@ +GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 1 + + + 1 .file "osccal.c" + 2 __SREG__ = 0x3f + 3 __SP_H__ = 0x3e + 4 __SP_L__ = 0x3d + 5 __CCP__ = 0x34 + 6 __tmp_reg__ = 0 + 7 __zero_reg__ = 1 + 8 .text + 9 .global calibrateOscillator + 10 .type calibrateOscillator, @function + 11 calibrateOscillator: + 12 0000 FF92 push r15 + 13 0002 0F93 push r16 + 14 0004 1F93 push r17 + 15 0006 CF93 push r28 + 16 0008 DF93 push r29 + 17 /* prologue: function */ + 18 /* frame size = 0 */ + 19 000a 80E8 ldi r24,lo8(-128) + 20 000c F82E mov r15,r24 + 21 000e 00E0 ldi r16,lo8(0) + 22 0010 C0E0 ldi r28,lo8(0) + 23 0012 D0E0 ldi r29,hi8(0) + 24 .L4: + 25 0014 102F mov r17,r16 + 26 0016 1F0D add r17,r15 + 27 0018 11BF out 81-32,r17 + 28 001a 00D0 rcall usbMeasureFrameLength + 29 001c 29E0 ldi r18,hi8(2356) + 30 001e 8433 cpi r24,lo8(2356) + 31 0020 9207 cpc r25,r18 + 32 0022 04F0 brlt .L2 + 33 0024 102F mov r17,r16 + 34 .L2: + 35 0026 F694 lsr r15 + 36 0028 2196 adiw r28,1 + 37 002a C830 cpi r28,8 + 38 002c D105 cpc r29,__zero_reg__ + 39 002e 01F0 breq .L3 + 40 0030 012F mov r16,r17 + 41 0032 00C0 rjmp .L4 + 42 .L3: + 43 0034 1150 subi r17,lo8(-(-1)) + 44 0036 11BF out 81-32,r17 + 45 0038 1F5F subi r17,lo8(-(1)) + 46 003a 012F mov r16,r17 + 47 003c EC01 movw r28,r24 + 48 003e 00C0 rjmp .L5 + 49 .L8: + 50 0040 00D0 rcall usbMeasureFrameLength + 51 0042 8453 subi r24,lo8(-(-2356)) + 52 0044 9940 sbci r25,hi8(-(-2356)) + 53 0046 97FF sbrs r25,7 + 54 0048 00C0 rjmp .L6 + 55 004a 9095 com r25 + 56 004c 8195 neg r24 + 57 004e 9F4F sbci r25,lo8(-1) + GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 2 + + + 58 .L6: + 59 0050 8C17 cp r24,r28 + 60 0052 9D07 cpc r25,r29 + 61 0054 04F4 brge .L7 + 62 0056 01B7 in r16,81-32 + 63 0058 EC01 movw r28,r24 + 64 .L7: + 65 005a 81B7 in r24,81-32 + 66 005c 8F5F subi r24,lo8(-(1)) + 67 005e 81BF out 81-32,r24 + 68 .L5: + 69 0060 21B7 in r18,81-32 + 70 0062 30E0 ldi r19,lo8(0) + 71 0064 812F mov r24,r17 + 72 0066 90E0 ldi r25,lo8(0) + 73 0068 0196 adiw r24,1 + 74 006a 8217 cp r24,r18 + 75 006c 9307 cpc r25,r19 + 76 006e 04F4 brge .L8 + 77 0070 01BF out 81-32,r16 + 78 /* epilogue start */ + 79 0072 DF91 pop r29 + 80 0074 CF91 pop r28 + 81 0076 1F91 pop r17 + 82 0078 0F91 pop r16 + 83 007a FF90 pop r15 + 84 007c 0895 ret + 85 .size calibrateOscillator, .-calibrateOscillator + GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 3 + + +DEFINED SYMBOLS + *ABS*:00000000 osccal.c +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:2 *ABS*:0000003f __SREG__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:3 *ABS*:0000003e __SP_H__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:4 *ABS*:0000003d __SP_L__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:5 *ABS*:00000034 __CCP__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:6 *ABS*:00000000 __tmp_reg__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:7 *ABS*:00000001 __zero_reg__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:11 .text:00000000 calibrateOscillator + +UNDEFINED SYMBOLS +usbMeasureFrameLength diff --git a/hardware/digistump/avr/libraries/DigiMouse/osccal.h b/hardware/digistump/avr/libraries/DigiMouse/osccal.h new file mode 100644 index 0000000..710ce05 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/osccal.h @@ -0,0 +1,65 @@ +/* Name: osccal.h + * Author: Christian Starkjohann + * Creation Date: 2008-04-10 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osccal.h 762 2009-08-12 17:10:30Z cs $ + */ + +/* +General Description: +This module contains a function which calibrates the AVR's internal RC +oscillator so that the CPU runs at F_CPU (F_CPU is a macro which must be +defined when the module is compiled, best passed in the compiler command +line). The time reference is the USB frame clock of 1 kHz available +immediately after a USB RESET condition. Timing is done by counting CPU +cycles, so all interrupts must be disabled while the calibration runs. For +low level timing measurements, usbMeasureFrameLength() is called. This +function must be enabled in usbconfig.h by defining +USB_CFG_HAVE_MEASURE_FRAME_LENGTH to 1. It is recommended to call +calibrateOscillator() from the reset hook in usbconfig.h: +*/ + +#ifndef __ASSEMBLER__ +#include // for sei() +extern void calibrateOscillator(void); +#endif +#define USB_RESET_HOOK(resetStarts) if(!resetStarts){cli(); calibrateOscillator(); sei();} + +/* +This routine is an alternative to the continuous synchronization described +in osctune.h. + +Algorithm used: +calibrateOscillator() first does a binary search in the OSCCAL register for +the best matching oscillator frequency. Then it does a next neighbor search +to find the value with the lowest clock rate deviation. It is guaranteed to +find the best match among neighboring values, but for version 5 oscillators +(which have a discontinuous relationship between OSCCAL and frequency) a +better match might be available in another OSCCAL region. + +Limitations: +This calibration algorithm may try OSCCAL values of up to 192 even if the +optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +Precision depends on the OSCCAL vs. frequency dependency of the oscillator. +Typical precision for an ATMega168 (derived from the OSCCAL vs. F_RC diagram +in the data sheet) should be in the range of 0.4%. Only the 12.8 MHz and +16.5 MHz versions of V-USB (with built-in receiver PLL) can tolerate this +deviation! All other frequency modules require at least 0.2% precision. +*/ + +#ifndef __OSCCAL_H_INCLUDED__ +#define __OSCCAL_H_INCLUDED__ + +//void calibrateOscillator(void); +/* This function calibrates the RC oscillator so that the CPU runs at F_CPU. + * It MUST be called immediately after the end of a USB RESET condition! + * Disable all interrupts during the call! + * It is recommended that you store the resulting value in EEPROM so that a + * good guess value is available after the next reset. + */ + + +#endif /* __OSCCAL_H_INCLUDED__ */ diff --git a/hardware/digistump/avr/libraries/DigiMouse/osccal.o b/hardware/digistump/avr/libraries/DigiMouse/osccal.o new file mode 100644 index 0000000..08e2187 Binary files /dev/null and b/hardware/digistump/avr/libraries/DigiMouse/osccal.o differ diff --git a/hardware/digistump/avr/libraries/DigiMouse/osctune.h b/hardware/digistump/avr/libraries/DigiMouse/osctune.h new file mode 100644 index 0000000..c751648 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/osctune.h @@ -0,0 +1,88 @@ +/* Name: osctune.h + * Author: Christian Starkjohann + * Creation Date: 2008-10-18 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osctune.h 692 2008-11-07 15:07:40Z cs $ + */ + +/* +General Description: +This file is declared as C-header file although it is mostly documentation +how the RC oscillator can be kept in sync to the USB frame rate. The code +shown here must be added to usbconfig.h or this header file is included from +there. This code works only if D- is wired to the interrupt, not D+!!! + +This is an alternative to the osccal routine in osccal.c. It has the advantage +that the synchronization is done continuously and that it has more compact +code size. The disadvantages are slow synchronization (it may take a while +until the driver works), that messages immediately after the SOF pulse may be +lost (and need to be retried by the host) and that the interrupt is on D- +contrary to most examples. + +You may want to store a good calibration value in EEPROM for the next startup. +You know that the calibration value is good when the first USB message is +received. Do not store the value on every received message because the EEPROM +has a limited endurance. + +Notes: +(*) You must declare the global character variable "lastTimer0Value" in your +main code. + +(*) Timer 0 must be free running (not written by your code) and the prescaling +must be consistent with the TIMER0_PRESCALING define. + +(*) Good values for Timer 0 prescaling depend on how precise the clock must +be tuned and how far away from the default clock rate the target clock is. +For precise tuning, choose a low prescaler factor, for a broad range of tuning +choose a high one. A prescaler factor of 64 is good for the entire OSCCAL +range and allows a precision of better than +/-1%. A prescaler factor of 8 +allows tuning to slightly more than +/-6% of the default frequency and is +more precise than one step of OSCCAL. It is therefore not suitable to tune an +8 MHz oscillator to 12.5 MHz. + +Thanks to Henrik Haftmann for the idea to this routine! +*/ + +#define TIMER0_PRESCALING 64 /* must match the configuration for TIMER0 in main */ +#define TOLERATED_DEVIATION_PPT 5 /* max clock deviation before we tune in 1/10 % */ +/* derived constants: */ +#define EXPECTED_TIMER0_INCREMENT ((F_CPU / (1000 * TIMER0_PRESCALING)) & 0xff) +#define TOLERATED_DEVIATION (TOLERATED_DEVIATION_PPT * F_CPU / (1000000 * TIMER0_PRESCALING)) + +#ifdef __ASSEMBLER__ +macro tuneOsccal + push YH ;[0] + in YL, TCNT0 ;[2] + lds YH, lastTimer0Value ;[3] + sts lastTimer0Value, YL ;[5] + sub YL, YH ;[7] time passed since last frame + subi YL, EXPECTED_TIMER0_INCREMENT ;[8] +#if OSCCAL > 0x3f /* outside I/O addressable range */ + lds YH, OSCCAL ;[6] +#else + in YH, OSCCAL ;[6] assembler modle uses __SFR_OFFSET == 0 +#endif + cpi YL, TOLERATED_DEVIATION + 1 ;[10] + brmi notTooHigh ;[11] + subi YH, 1 ;[12] clock rate was too high +; brcs tuningOverflow ; optionally check for overflow + rjmp osctuneDone ;[13] +notTooHigh: + cpi YL, -TOLERATED_DEVIATION ;[13] + brpl osctuneDone ;[14] not too low + inc YH ;[15] clock rate was too low +; breq tuningOverflow ; optionally check for overflow +osctuneDone: +#if OSCCAL > 0x3f /* outside I/O addressable range */ + sts OSCCAL, YH ;[12-13] store tuned value +#else + out OSCCAL, YH ;[12-13] store tuned value +#endif +tuningOverflow: + pop YH ;[17] + endm ;[19] max number of cycles +#endif + +#define USB_SOF_HOOK tuneOsccal diff --git a/hardware/digistump/avr/libraries/DigiMouse/usbconfig-prototype.h b/hardware/digistump/avr/libraries/DigiMouse/usbconfig-prototype.h new file mode 100644 index 0000000..a0fd1bf --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/usbconfig-prototype.h @@ -0,0 +1,369 @@ +/* Name: usbconfig.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2005-04-01 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbconfig-prototype.h 767 2009-08-22 11:39:22Z cs $ + */ + +#ifndef __usbconfig_h_included__ +#define __usbconfig_h_included__ + +/* +General Description: +This file is an example configuration (with inline documentation) for the USB +driver. It configures V-USB for USB D+ connected to Port D bit 2 (which is +also hardware interrupt 0 on many devices) and USB D- to Port D bit 4. You may +wire the lines to any other port, as long as D+ is also wired to INT0 (or any +other hardware interrupt, as long as it is the highest level interrupt, see +section at the end of this file). ++ To create your own usbconfig.h file, copy this file to your project's ++ firmware source directory) and rename it to "usbconfig.h". ++ Then edit it accordingly. +*/ + +/* ---------------------------- Hardware Config ---------------------------- */ + +#define USB_CFG_IOPORTNAME D +/* This is the port where the USB bus is connected. When you configure it to + * "B", the registers PORTB, PINB and DDRB will be used. + */ +#define USB_CFG_DMINUS_BIT 4 +/* This is the bit number in USB_CFG_IOPORT where the USB D- line is connected. + * This may be any bit in the port. + */ +#define USB_CFG_DPLUS_BIT 2 +/* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected. + * This may be any bit in the port. Please note that D+ must also be connected + * to interrupt pin INT0! [You can also use other interrupts, see section + * "Optional MCU Description" below, or you can connect D- to the interrupt, as + * it is required if you use the USB_COUNT_SOF feature. If you use D- for the + * interrupt, the USB interrupt will also be triggered at Start-Of-Frame + * markers every millisecond.] + */ +#define USB_CFG_CLOCK_KHZ (F_CPU/1000) +/* Clock rate of the AVR in kHz. Legal values are 12000, 12800, 15000, 16000, + * 16500 and 20000. The 12.8 MHz and 16.5 MHz versions of the code require no + * crystal, they tolerate +/- 1% deviation from the nominal frequency. All + * other rates require a precision of 2000 ppm and thus a crystal! + * Default if not specified: 12 MHz + */ +#define USB_CFG_CHECK_CRC 0 +/* Define this to 1 if you want that the driver checks integrity of incoming + * data packets (CRC checks). CRC checks cost quite a bit of code size and are + * currently only available for 18 MHz crystal clock. You must choose + * USB_CFG_CLOCK_KHZ = 18000 if you enable this option. + */ + +/* ----------------------- Optional Hardware Config ------------------------ */ + +/* #define USB_CFG_PULLUP_IOPORTNAME D */ +/* If you connect the 1.5k pullup resistor from D- to a port pin instead of + * V+, you can connect and disconnect the device from firmware by calling + * the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h). + * This constant defines the port on which the pullup resistor is connected. + */ +/* #define USB_CFG_PULLUP_BIT 4 */ +/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined + * above) where the 1.5k pullup resistor is connected. See description + * above for details. + */ + +/* --------------------------- Functional Range ---------------------------- */ + +#define USB_CFG_HAVE_INTRIN_ENDPOINT 0 +/* Define this to 1 if you want to compile a version with two endpoints: The + * default control endpoint 0 and an interrupt-in endpoint (any other endpoint + * number). + */ +#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0 +/* Define this to 1 if you want to compile a version with three endpoints: The + * default control endpoint 0, an interrupt-in endpoint 3 (or the number + * configured below) and a catch-all default interrupt-in endpoint as above. + * You must also define USB_CFG_HAVE_INTRIN_ENDPOINT to 1 for this feature. + */ +#define USB_CFG_EP3_NUMBER 3 +/* If the so-called endpoint 3 is used, it can now be configured to any other + * endpoint number (except 0) with this macro. Default if undefined is 3. + */ +/* #define USB_INITIAL_DATATOKEN USBPID_DATA1 */ +/* The above macro defines the startup condition for data toggling on the + * interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA1. + * Since the token is toggled BEFORE sending any data, the first packet is + * sent with the oposite value of this configuration! + */ +#define USB_CFG_IMPLEMENT_HALT 0 +/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature + * for endpoint 1 (interrupt endpoint). Although you may not need this feature, + * it is required by the standard. We have made it a config option because it + * bloats the code considerably. + */ +#define USB_CFG_SUPPRESS_INTR_CODE 0 +/* Define this to 1 if you want to declare interrupt-in endpoints, but don't + * want to send any data over them. If this macro is defined to 1, functions + * usbSetInterrupt() and usbSetInterrupt3() are omitted. This is useful if + * you need the interrupt-in endpoints in order to comply to an interface + * (e.g. HID), but never want to send any data. This option saves a couple + * of bytes in flash memory and the transmit buffers in RAM. + */ +#define USB_CFG_INTR_POLL_INTERVAL 10 +/* If you compile a version with endpoint 1 (interrupt-in), this is the poll + * interval. The value is in milliseconds and must not be less than 10 ms for + * low speed devices. + */ +#define USB_CFG_IS_SELF_POWERED 0 +/* Define this to 1 if the device has its own power supply. Set it to 0 if the + * device is powered from the USB bus. + */ +#define USB_CFG_MAX_BUS_POWER 100 +/* Set this variable to the maximum USB bus power consumption of your device. + * The value is in milliamperes. [It will be divided by two since USB + * communicates power requirements in units of 2 mA.] + */ +#define USB_CFG_IMPLEMENT_FN_WRITE 0 +/* Set this to 1 if you want usbFunctionWrite() to be called for control-out + * transfers. Set it to 0 if you don't need it and want to save a couple of + * bytes. + */ +#define USB_CFG_IMPLEMENT_FN_READ 0 +/* Set this to 1 if you need to send control replies which are generated + * "on the fly" when usbFunctionRead() is called. If you only want to send + * data from a static buffer, set it to 0 and return the data from + * usbFunctionSetup(). This saves a couple of bytes. + */ +#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0 +/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints. + * You must implement the function usbFunctionWriteOut() which receives all + * interrupt/bulk data sent to any endpoint other than 0. The endpoint number + * can be found in 'usbRxToken'. + */ +#define USB_CFG_HAVE_FLOWCONTROL 0 +/* Define this to 1 if you want flowcontrol over USB data. See the definition + * of the macros usbDisableAllRequests() and usbEnableAllRequests() in + * usbdrv.h. + */ +#define USB_CFG_LONG_TRANSFERS 0 +/* Define this to 1 if you want to send/receive blocks of more than 254 bytes + * in a single control-in or control-out transfer. Note that the capability + * for long transfers increases the driver size. + */ +/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */ +/* This macro is a hook if you want to do unconventional things. If it is + * defined, it's inserted at the beginning of received message processing. + * If you eat the received message and don't want default processing to + * proceed, do a return after doing your things. One possible application + * (besides debugging) is to flash a status LED on each packet. + */ +/* #define USB_RESET_HOOK(resetStarts) if(!resetStarts){hadUsbReset();} */ +/* This macro is a hook if you need to know when an USB RESET occurs. It has + * one parameter which distinguishes between the start of RESET state and its + * end. + */ +/* #define USB_SET_ADDRESS_HOOK() hadAddressAssigned(); */ +/* This macro (if defined) is executed when a USB SET_ADDRESS request was + * received. + */ +#define USB_COUNT_SOF 0 +/* define this macro to 1 if you need the global variable "usbSofCount" which + * counts SOF packets. This feature requires that the hardware interrupt is + * connected to D- instead of D+. + */ +/* #ifdef __ASSEMBLER__ + * macro myAssemblerMacro + * in YL, TCNT0 + * sts timer0Snapshot, YL + * endm + * #endif + * #define USB_SOF_HOOK myAssemblerMacro + * This macro (if defined) is executed in the assembler module when a + * Start Of Frame condition is detected. It is recommended to define it to + * the name of an assembler macro which is defined here as well so that more + * than one assembler instruction can be used. The macro may use the register + * YL and modify SREG. If it lasts longer than a couple of cycles, USB messages + * immediately after an SOF pulse may be lost and must be retried by the host. + * What can you do with this hook? Since the SOF signal occurs exactly every + * 1 ms (unless the host is in sleep mode), you can use it to tune OSCCAL in + * designs running on the internal RC oscillator. + * Please note that Start Of Frame detection works only if D- is wired to the + * interrupt, not D+. THIS IS DIFFERENT THAN MOST EXAMPLES! + */ +#define USB_CFG_CHECK_DATA_TOGGLING 0 +/* define this macro to 1 if you want to filter out duplicate data packets + * sent by the host. Duplicates occur only as a consequence of communication + * errors, when the host does not receive an ACK. Please note that you need to + * implement the filtering yourself in usbFunctionWriteOut() and + * usbFunctionWrite(). Use the global usbCurrentDataToken and a static variable + * for each control- and out-endpoint to check for duplicate packets. + */ +#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 0 +/* define this macro to 1 if you want the function usbMeasureFrameLength() + * compiled in. This function can be used to calibrate the AVR's RC oscillator. + */ +#define USB_USE_FAST_CRC 0 +/* The assembler module has two implementations for the CRC algorithm. One is + * faster, the other is smaller. This CRC routine is only used for transmitted + * messages where timing is not critical. The faster routine needs 31 cycles + * per byte while the smaller one needs 61 to 69 cycles. The faster routine + * may be worth the 32 bytes bigger code size if you transmit lots of data and + * run the AVR close to its limit. + */ + +/* -------------------------- Device Description --------------------------- */ + +#define USB_CFG_VENDOR_ID 0xc0, 0x16 /* = 0x16c0 = 5824 = voti.nl */ +/* USB vendor ID for the device, low byte first. If you have registered your + * own Vendor ID, define it here. Otherwise you may use one of obdev's free + * shared VID/PID pairs. Be sure to read USB-IDs-for-free.txt for rules! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_ID 0xdc, 0x05 /* = 0x05dc = 1500 */ +/* This is the ID of the product, low byte first. It is interpreted in the + * scope of the vendor ID. If you have registered your own VID with usb.org + * or if you have licensed a PID from somebody else, define it here. Otherwise + * you may use one of obdev's free shared VID/PID pairs. See the file + * USB-IDs-for-free.txt for details! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_VERSION 0x00, 0x01 +/* Version number of the device: Minor number first, then major number. + */ +#define USB_CFG_VENDOR_NAME 'o', 'b', 'd', 'e', 'v', '.', 'a', 't' +#define USB_CFG_VENDOR_NAME_LEN 8 +/* These two values define the vendor name returned by the USB device. The name + * must be given as a list of characters under single quotes. The characters + * are interpreted as Unicode (UTF-16) entities. + * If you don't want a vendor name string, undefine these macros. + * ALWAYS define a vendor name containing your Internet domain name if you use + * obdev's free shared VID/PID pair. See the file USB-IDs-for-free.txt for + * details. + */ +#define USB_CFG_DEVICE_NAME 'T', 'e', 'm', 'p', 'l', 'a', 't', 'e' +#define USB_CFG_DEVICE_NAME_LEN 8 +/* Same as above for the device name. If you don't want a device name, undefine + * the macros. See the file USB-IDs-for-free.txt before you assign a name if + * you use a shared VID/PID. + */ +/*#define USB_CFG_SERIAL_NUMBER 'N', 'o', 'n', 'e' */ +/*#define USB_CFG_SERIAL_NUMBER_LEN 0 */ +/* Same as above for the serial number. If you don't want a serial number, + * undefine the macros. + * It may be useful to provide the serial number through other means than at + * compile time. See the section about descriptor properties below for how + * to fine tune control over USB descriptors such as the string descriptor + * for the serial number. + */ +#define USB_CFG_DEVICE_CLASS 0xff /* set to 0 if deferred to interface */ +#define USB_CFG_DEVICE_SUBCLASS 0 +/* See USB specification if you want to conform to an existing device class. + * Class 0xff is "vendor specific". + */ +#define USB_CFG_INTERFACE_CLASS 0 /* define class here if not at device level */ +#define USB_CFG_INTERFACE_SUBCLASS 0 +#define USB_CFG_INTERFACE_PROTOCOL 0 +/* See USB specification if you want to conform to an existing device class or + * protocol. The following classes must be set at interface level: + * HID class is 3, no subclass and protocol required (but may be useful!) + * CDC class is 2, use subclass 2 and protocol 1 for ACM + */ +/* #define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 42 */ +/* Define this to the length of the HID report descriptor, if you implement + * an HID device. Otherwise don't define it or define it to 0. + * If you use this define, you must add a PROGMEM character array named + * "usbHidReportDescriptor" to your code which contains the report descriptor. + * Don't forget to keep the array and this define in sync! + */ + +/* #define USB_PUBLIC static */ +/* Use the define above if you #include usbdrv.c instead of linking against it. + * This technique saves a couple of bytes in flash memory. + */ + +/* ------------------- Fine Control over USB Descriptors ------------------- */ +/* If you don't want to use the driver's default USB descriptors, you can + * provide our own. These can be provided as (1) fixed length static data in + * flash memory, (2) fixed length static data in RAM or (3) dynamically at + * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more + * information about this function. + * Descriptor handling is configured through the descriptor's properties. If + * no properties are defined or if they are 0, the default descriptor is used. + * Possible properties are: + * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched + * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is + * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if + * you want RAM pointers. + * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found + * in static memory is in RAM, not in flash memory. + * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash), + * the driver must know the descriptor's length. The descriptor itself is + * found at the address of a well known identifier (see below). + * List of static descriptor names (must be declared PROGMEM if in flash): + * char usbDescriptorDevice[]; + * char usbDescriptorConfiguration[]; + * char usbDescriptorHidReport[]; + * char usbDescriptorString0[]; + * int usbDescriptorStringVendor[]; + * int usbDescriptorStringDevice[]; + * int usbDescriptorStringSerialNumber[]; + * Other descriptors can't be provided statically, they must be provided + * dynamically at runtime. + * + * Descriptor properties are or-ed or added together, e.g.: + * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18)) + * + * The following descriptors are defined: + * USB_CFG_DESCR_PROPS_DEVICE + * USB_CFG_DESCR_PROPS_CONFIGURATION + * USB_CFG_DESCR_PROPS_STRINGS + * USB_CFG_DESCR_PROPS_STRING_0 + * USB_CFG_DESCR_PROPS_STRING_VENDOR + * USB_CFG_DESCR_PROPS_STRING_PRODUCT + * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER + * USB_CFG_DESCR_PROPS_HID + * USB_CFG_DESCR_PROPS_HID_REPORT + * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver) + * + * Note about string descriptors: String descriptors are not just strings, they + * are Unicode strings prefixed with a 2 byte header. Example: + * int serialNumberDescriptor[] = { + * USB_STRING_DESCRIPTOR_HEADER(6), + * 'S', 'e', 'r', 'i', 'a', 'l' + * }; + */ + +#define USB_CFG_DESCR_PROPS_DEVICE 0 +#define USB_CFG_DESCR_PROPS_CONFIGURATION 0 +#define USB_CFG_DESCR_PROPS_STRINGS 0 +#define USB_CFG_DESCR_PROPS_STRING_0 0 +#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0 +#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0 +#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0 +#define USB_CFG_DESCR_PROPS_HID 0 +#define USB_CFG_DESCR_PROPS_HID_REPORT 0 +#define USB_CFG_DESCR_PROPS_UNKNOWN 0 + +/* ----------------------- Optional MCU Description ------------------------ */ + +/* The following configurations have working defaults in usbdrv.h. You + * usually don't need to set them explicitly. Only if you want to run + * the driver on a device which is not yet supported or with a compiler + * which is not fully supported (such as IAR C) or if you use a differnt + * interrupt than INT0, you may have to define some of these. + */ +/* #define USB_INTR_CFG MCUCR */ +/* #define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) */ +/* #define USB_INTR_CFG_CLR 0 */ +/* #define USB_INTR_ENABLE GIMSK */ +/* #define USB_INTR_ENABLE_BIT INT0 */ +/* #define USB_INTR_PENDING GIFR */ +/* #define USB_INTR_PENDING_BIT INTF0 */ +/* #define USB_INTR_VECTOR SIG_INTERRUPT0 */ + +#endif /* __usbconfig_h_included__ */ diff --git a/hardware/digistump/avr/libraries/DigiMouse/usbconfig.h b/hardware/digistump/avr/libraries/DigiMouse/usbconfig.h new file mode 100644 index 0000000..509cdc3 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/usbconfig.h @@ -0,0 +1,398 @@ +/* Name: usbconfig.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2005-04-01 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbconfig-prototype.h 767 2009-08-22 11:39:22Z cs $ + */ + +#ifndef __usbconfig_h_included__ +#define __usbconfig_h_included__ + +/* +General Description: +This file is an example configuration (with inline documentation) for the USB +driver. It configures V-USB for USB D+ connected to Port D bit 2 (which is +also hardware interrupt 0 on many devices) and USB D- to Port D bit 4. You may +wire the lines to any other port, as long as D+ is also wired to INT0 (or any +other hardware interrupt, as long as it is the highest level interrupt, see +section at the end of this file). ++ To create your own usbconfig.h file, copy this file to your project's ++ firmware source directory) and rename it to "usbconfig.h". ++ Then edit it accordingly. +*/ + +/* ---------------------------- Hardware Config ---------------------------- */ + +#if defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 1 +#define USB_CFG_DPLUS_BIT 2 + +#elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 4 + +#elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 6 + +#elif defined (__AVR_ATtiny461__) || defined (__AVR_ATtiny861__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 5 +#define USB_CFG_DPLUS_BIT 6 +#else +/* ATtiny2313, ATmega8/48/88/168 */ +#define USB_CFG_IOPORTNAME D +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 2 +#endif +#define USB_CFG_CLOCK_KHZ (F_CPU/1000) +/* Clock rate of the AVR in kHz. Legal values are 12000, 12800, 15000, 16000, + * 16500 and 20000. The 12.8 MHz and 16.5 MHz versions of the code require no + * crystal, they tolerate +/- 1% deviation from the nominal frequency. All + * other rates require a precision of 2000 ppm and thus a crystal! + * Default if not specified: 12 MHz + */ +#define USB_CFG_CHECK_CRC 0 +/* Define this to 1 if you want that the driver checks integrity of incoming + * data packets (CRC checks). CRC checks cost quite a bit of code size and are + * currently only available for 18 MHz crystal clock. You must choose + * USB_CFG_CLOCK_KHZ = 18000 if you enable this option. + */ + +/* ----------------------- Optional Hardware Config ------------------------ */ + +//#define USB_CFG_PULLUP_IOPORTNAME D +/* If you connect the 1.5k pullup resistor from D- to a port pin instead of + * V+, you can connect and disconnect the device from firmware by calling + * the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h). + * This constant defines the port on which the pullup resistor is connected. + */ +//#define USB_CFG_PULLUP_BIT 5 +/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined + * above) where the 1.5k pullup resistor is connected. See description + * above for details. + */ + +/* --------------------------- Functional Range ---------------------------- */ + +#define USB_CFG_HAVE_INTRIN_ENDPOINT 1 +/* Define this to 1 if you want to compile a version with two endpoints: The + * default control endpoint 0 and an interrupt-in endpoint (any other endpoint + * number). + */ +#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0 +/* Define this to 1 if you want to compile a version with three endpoints: The + * default control endpoint 0, an interrupt-in endpoint 3 (or the number + * configured below) and a catch-all default interrupt-in endpoint as above. + * You must also define USB_CFG_HAVE_INTRIN_ENDPOINT to 1 for this feature. + */ +#define USB_CFG_EP3_NUMBER 3 +/* If the so-called endpoint 3 is used, it can now be configured to any other + * endpoint number (except 0) with this macro. Default if undefined is 3. + */ +/* #define USB_INITIAL_DATATOKEN USBPID_DATA1 */ +/* The above macro defines the startup condition for data toggling on the + * interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA1. + * Since the token is toggled BEFORE sending any data, the first packet is + * sent with the oposite value of this configuration! + */ +#define USB_CFG_IMPLEMENT_HALT 0 +/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature + * for endpoint 1 (interrupt endpoint). Although you may not need this feature, + * it is required by the standard. We have made it a config option because it + * bloats the code considerably. + */ +#define USB_CFG_SUPPRESS_INTR_CODE 0 +/* Define this to 1 if you want to declare interrupt-in endpoints, but don't + * want to send any data over them. If this macro is defined to 1, functions + * usbSetInterrupt() and usbSetInterrupt3() are omitted. This is useful if + * you need the interrupt-in endpoints in order to comply to an interface + * (e.g. HID), but never want to send any data. This option saves a couple + * of bytes in flash memory and the transmit buffers in RAM. + */ +#define USB_CFG_INTR_POLL_INTERVAL 10 +/* If you compile a version with endpoint 1 (interrupt-in), this is the poll + * interval. The value is in milliseconds and must not be less than 10 ms for + * low speed devices. + */ +#define USB_CFG_IS_SELF_POWERED 0 +/* Define this to 1 if the device has its own power supply. Set it to 0 if the + * device is powered from the USB bus. + */ +#define USB_CFG_MAX_BUS_POWER 100 +/* Set this variable to the maximum USB bus power consumption of your device. + * The value is in milliamperes. [It will be divided by two since USB + * communicates power requirements in units of 2 mA.] + */ +#define USB_CFG_IMPLEMENT_FN_WRITE 0 +/* Set this to 1 if you want usbFunctionWrite() to be called for control-out + * transfers. Set it to 0 if you don't need it and want to save a couple of + * bytes. + */ +#define USB_CFG_IMPLEMENT_FN_READ 0 +/* Set this to 1 if you need to send control replies which are generated + * "on the fly" when usbFunctionRead() is called. If you only want to send + * data from a static buffer, set it to 0 and return the data from + * usbFunctionSetup(). This saves a couple of bytes. + */ +#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0 +/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints. + * You must implement the function usbFunctionWriteOut() which receives all + * interrupt/bulk data sent to any endpoint other than 0. The endpoint number + * can be found in 'usbRxToken'. + */ +#define USB_CFG_HAVE_FLOWCONTROL 0 +/* Define this to 1 if you want flowcontrol over USB data. See the definition + * of the macros usbDisableAllRequests() and usbEnableAllRequests() in + * usbdrv.h. + */ +#define USB_CFG_LONG_TRANSFERS 0 +/* Define this to 1 if you want to send/receive blocks of more than 254 bytes + * in a single control-in or control-out transfer. Note that the capability + * for long transfers increases the driver size. + */ +/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */ +/* This macro is a hook if you want to do unconventional things. If it is + * defined, it's inserted at the beginning of received message processing. + * If you eat the received message and don't want default processing to + * proceed, do a return after doing your things. One possible application + * (besides debugging) is to flash a status LED on each packet. + */ +/* #define USB_RESET_HOOK(resetStarts) if(!resetStarts){hadUsbReset();} */ +/* This macro is a hook if you need to know when an USB RESET occurs. It has + * one parameter which distinguishes between the start of RESET state and its + * end. + */ +/* #define USB_SET_ADDRESS_HOOK() hadAddressAssigned(); */ +/* This macro (if defined) is executed when a USB SET_ADDRESS request was + * received. + */ +#define USB_COUNT_SOF 0 +/* define this macro to 1 if you need the global variable "usbSofCount" which + * counts SOF packets. This feature requires that the hardware interrupt is + * connected to D- instead of D+. + */ +/* #ifdef __ASSEMBLER__ + * macro myAssemblerMacro + * in YL, TCNT0 + * sts timer0Snapshot, YL + * endm + * #endif + * #define USB_SOF_HOOK myAssemblerMacro + * This macro (if defined) is executed in the assembler module when a + * Start Of Frame condition is detected. It is recommended to define it to + * the name of an assembler macro which is defined here as well so that more + * than one assembler instruction can be used. The macro may use the register + * YL and modify SREG. If it lasts longer than a couple of cycles, USB messages + * immediately after an SOF pulse may be lost and must be retried by the host. + * What can you do with this hook? Since the SOF signal occurs exactly every + * 1 ms (unless the host is in sleep mode), you can use it to tune OSCCAL in + * designs running on the internal RC oscillator. + * Please note that Start Of Frame detection works only if D- is wired to the + * interrupt, not D+. THIS IS DIFFERENT THAN MOST EXAMPLES! + */ +#define USB_CFG_CHECK_DATA_TOGGLING 0 +/* define this macro to 1 if you want to filter out duplicate data packets + * sent by the host. Duplicates occur only as a consequence of communication + * errors, when the host does not receive an ACK. Please note that you need to + * implement the filtering yourself in usbFunctionWriteOut() and + * usbFunctionWrite(). Use the global usbCurrentDataToken and a static variable + * for each control- and out-endpoint to check for duplicate packets. + */ +#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 1 +#include "osccal.h" +/* define this macro to 1 if you want the function usbMeasureFrameLength() + * compiled in. This function can be used to calibrate the AVR's RC oscillator. + */ +#define USB_USE_FAST_CRC 0 +/* The assembler module has two implementations for the CRC algorithm. One is + * faster, the other is smaller. This CRC routine is only used for transmitted + * messages where timing is not critical. The faster routine needs 31 cycles + * per byte while the smaller one needs 61 to 69 cycles. The faster routine + * may be worth the 32 bytes bigger code size if you transmit lots of data and + * run the AVR close to its limit. + */ + +/* -------------------------- Device Description --------------------------- */ + +#define USB_CFG_VENDOR_ID 0xc0, 0x16 +/* USB vendor ID for the device, low byte first. If you have registered your + * own Vendor ID, define it here. Otherwise you may use one of obdev's free + * shared VID/PID pairs. Be sure to read USB-IDs-for-free.txt for rules! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_ID 0xda, 0x27 +/* This is the ID of the product, low byte first. It is interpreted in the + * scope of the vendor ID. If you have registered your own VID with usb.org + * or if you have licensed a PID from somebody else, define it here. Otherwise + * you may use one of obdev's free shared VID/PID pairs. See the file + * USB-IDs-for-free.txt for details! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_VERSION 0x00, 0x01 +/* Version number of the device: Minor number first, then major number. + */ +#define USB_CFG_VENDOR_NAME 'd','i','g','i','s','t','u','m','p','.','c','o','m' +#define USB_CFG_VENDOR_NAME_LEN 13 +/* These two values define the vendor name returned by the USB device. The name + * must be given as a list of characters under single quotes. The characters + * are interpreted as Unicode (UTF-16) entities. + * If you don't want a vendor name string, undefine these macros. + * ALWAYS define a vendor name containing your Internet domain name if you use + * obdev's free shared VID/PID pair. See the file USB-IDs-for-free.txt for + * details. + */ +#define USB_CFG_DEVICE_NAME 'D','i','g','i','K','e','y' +#define USB_CFG_DEVICE_NAME_LEN 7 +/* Same as above for the device name. If you don't want a device name, undefine + * the macros. See the file USB-IDs-for-free.txt before you assign a name if + * you use a shared VID/PID. + */ +#define USB_CFG_SERIAL_NUMBER 'd','i','g','i','s','t','u','m','p','.','c','o','m',':','M','o','u','s','e' +#define USB_CFG_SERIAL_NUMBER_LEN 19 +/* Same as above for the serial number. If you don't want a serial number, + * undefine the macros. + * It may be useful to provide the serial number through other means than at + * compile time. See the section about descriptor properties below for how + * to fine tune control over USB descriptors such as the string descriptor + * for the serial number. + */ +#define USB_CFG_DEVICE_CLASS 0 /* set to 0 if deferred to interface */ +#define USB_CFG_DEVICE_SUBCLASS 0 +/* See USB specification if you want to conform to an existing device class. + * Class 0xff is "vendor specific". + */ +#define USB_CFG_INTERFACE_CLASS 0x03 /* HID */ /* define class here if not at device level */ +#define USB_CFG_INTERFACE_SUBCLASS 0x0 +#define USB_CFG_INTERFACE_PROTOCOL 0x0 +/* See USB specification if you want to conform to an existing device class or + * protocol. The following classes must be set at interface level: + * HID class is 3, no subclass and protocol required (but may be useful!) + * CDC class is 2, use subclass 2 and protocol 1 for ACM + */ +#define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 56 +/* Define this to the length of the HID report descriptor, if you implement + * an HID device. Otherwise don't define it or define it to 0. + * If you use this define, you must add a PROGMEM character array named + * "usbHidReportDescriptor" to your code which contains the report descriptor. + * Don't forget to keep the array and this define in sync! + */ + +/* #define USB_PUBLIC static */ +/* Use the define above if you #include usbdrv.c instead of linking against it. + * This technique saves a couple of bytes in flash memory. + */ + +/* ------------------- Fine Control over USB Descriptors ------------------- */ +/* If you don't want to use the driver's default USB descriptors, you can + * provide our own. These can be provided as (1) fixed length static data in + * flash memory, (2) fixed length static data in RAM or (3) dynamically at + * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more + * information about this function. + * Descriptor handling is configured through the descriptor's properties. If + * no properties are defined or if they are 0, the default descriptor is used. + * Possible properties are: + * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched + * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is + * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if + * you want RAM pointers. + * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found + * in static memory is in RAM, not in flash memory. + * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash), + * the driver must know the descriptor's length. The descriptor itself is + * found at the address of a well known identifier (see below). + * List of static descriptor names (must be declared PROGMEM if in flash): + * char usbDescriptorDevice[]; + * char usbDescriptorConfiguration[]; + * char usbDescriptorHidReport[]; + * char usbDescriptorString0[]; + * int usbDescriptorStringVendor[]; + * int usbDescriptorStringDevice[]; + * int usbDescriptorStringSerialNumber[]; + * Other descriptors can't be provided statically, they must be provided + * dynamically at runtime. + * + * Descriptor properties are or-ed or added together, e.g.: + * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18)) + * + * The following descriptors are defined: + * USB_CFG_DESCR_PROPS_DEVICE + * USB_CFG_DESCR_PROPS_CONFIGURATION + * USB_CFG_DESCR_PROPS_STRINGS + * USB_CFG_DESCR_PROPS_STRING_0 + * USB_CFG_DESCR_PROPS_STRING_VENDOR + * USB_CFG_DESCR_PROPS_STRING_PRODUCT + * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER + * USB_CFG_DESCR_PROPS_HID + * USB_CFG_DESCR_PROPS_HID_REPORT + * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver) + * + * Note about string descriptors: String descriptors are not just strings, they + * are Unicode strings prefixed with a 2 byte header. Example: + * int serialNumberDescriptor[] = { + * USB_STRING_DESCRIPTOR_HEADER(6), + * 'S', 'e', 'r', 'i', 'a', 'l' + * }; + */ + +#define USB_CFG_DESCR_PROPS_DEVICE 0 +#define USB_CFG_DESCR_PROPS_CONFIGURATION 0 +#define USB_CFG_DESCR_PROPS_STRINGS 0 +#define USB_CFG_DESCR_PROPS_STRING_0 0 +#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0 +#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0 +#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0 +#define USB_CFG_DESCR_PROPS_HID 0 +#define USB_CFG_DESCR_PROPS_HID_REPORT USB_PROP_IS_DYNAMIC +#define USB_CFG_DESCR_PROPS_UNKNOWN 0 + +/* ----------------------- Optional MCU Description ------------------------ */ + +/* The following configurations have working defaults in usbdrv.h. You + * usually don't need to set them explicitly. Only if you want to run + * the driver on a device which is not yet supported or with a compiler + * which is not fully supported (such as IAR C) or if you use a differnt + * interrupt than INT0, you may have to define some of these. + */ +/* #define USB_INTR_CFG MCUCR */ +/* #define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) */ +/* #define USB_INTR_CFG_CLR 0 */ +/* #define USB_INTR_ENABLE GIMSK */ +/* #define USB_INTR_ENABLE_BIT INT0 */ +/* #define USB_INTR_PENDING GIFR */ +/* #define USB_INTR_PENDING_BIT INTF0 */ +/* #define USB_INTR_VECTOR SIG_INTERRUPT0 */ + + #if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define USB_INTR_CFG PCMSK +#define USB_INTR_CFG_SET (1<len & 0x10){ /* packet buffer was empty */ + txStatus->buffer[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */ + }else{ + txStatus->len = USBPID_NAK; /* avoid sending outdated (overwritten) interrupt data */ + } + p = txStatus->buffer + 1; + i = len; + do{ /* if len == 0, we still copy 1 byte, but that's no problem */ + *p++ = *data++; + }while(--i > 0); /* loop control at the end is 2 bytes shorter than at beginning */ + usbCrc16Append(&txStatus->buffer[1], len); + txStatus->len = len + 4; /* len must be given including sync byte */ + DBG2(0x21 + (((int)txStatus >> 3) & 3), txStatus->buffer, len + 3); +} + +USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len) +{ + usbGenericSetInterrupt(data, len, &usbTxStatus1); +} +#endif + +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 +USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len) +{ + usbGenericSetInterrupt(data, len, &usbTxStatus3); +} +#endif +#endif /* USB_CFG_SUPPRESS_INTR_CODE */ + +/* ------------------ utilities for code following below ------------------- */ + +/* Use defines for the switch statement so that we can choose between an + * if()else if() and a switch/case based implementation. switch() is more + * efficient for a LARGE set of sequential choices, if() is better in all other + * cases. + */ +#if USB_CFG_USE_SWITCH_STATEMENT +# define SWITCH_START(cmd) switch(cmd){{ +# define SWITCH_CASE(value) }break; case (value):{ +# define SWITCH_CASE2(v1,v2) }break; case (v1): case(v2):{ +# define SWITCH_CASE3(v1,v2,v3) }break; case (v1): case(v2): case(v3):{ +# define SWITCH_DEFAULT }break; default:{ +# define SWITCH_END }} +#else +# define SWITCH_START(cmd) {uchar _cmd = cmd; if(0){ +# define SWITCH_CASE(value) }else if(_cmd == (value)){ +# define SWITCH_CASE2(v1,v2) }else if(_cmd == (v1) || _cmd == (v2)){ +# define SWITCH_CASE3(v1,v2,v3) }else if(_cmd == (v1) || _cmd == (v2) || (_cmd == v3)){ +# define SWITCH_DEFAULT }else{ +# define SWITCH_END }} +#endif + +#ifndef USB_RX_USER_HOOK +#define USB_RX_USER_HOOK(data, len) +#endif +#ifndef USB_SET_ADDRESS_HOOK +#define USB_SET_ADDRESS_HOOK() +#endif + +/* ------------------------------------------------------------------------- */ + +/* We use if() instead of #if in the macro below because #if can't be used + * in macros and the compiler optimizes constant conditions anyway. + * This may cause problems with undefined symbols if compiled without + * optimizing! + */ +#define GET_DESCRIPTOR(cfgProp, staticName) \ + if(cfgProp){ \ + if((cfgProp) & USB_PROP_IS_RAM) \ + flags = 0; \ + if((cfgProp) & USB_PROP_IS_DYNAMIC){ \ + len = usbFunctionDescriptor(rq); \ + }else{ \ + len = USB_PROP_LENGTH(cfgProp); \ + usbMsgPtr = (uchar *)(staticName); \ + } \ + } + +/* usbDriverDescriptor() is similar to usbFunctionDescriptor(), but used + * internally for all types of descriptors. + */ +static inline usbMsgLen_t usbDriverDescriptor(usbRequest_t *rq) +{ +usbMsgLen_t len = 0; +uchar flags = USB_FLG_MSGPTR_IS_ROM; + + SWITCH_START(rq->wValue.bytes[1]) + SWITCH_CASE(USBDESCR_DEVICE) /* 1 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_DEVICE, usbDescriptorDevice) + SWITCH_CASE(USBDESCR_CONFIG) /* 2 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_CONFIGURATION, usbDescriptorConfiguration) + SWITCH_CASE(USBDESCR_STRING) /* 3 */ +#if USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC + if(USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_RAM) + flags = 0; + len = usbFunctionDescriptor(rq); +#else /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */ + SWITCH_START(rq->wValue.bytes[0]) + SWITCH_CASE(0) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_0, usbDescriptorString0) + SWITCH_CASE(1) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_VENDOR, usbDescriptorStringVendor) + SWITCH_CASE(2) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_PRODUCT, usbDescriptorStringDevice) + SWITCH_CASE(3) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER, usbDescriptorStringSerialNumber) + SWITCH_DEFAULT + if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){ + len = usbFunctionDescriptor(rq); + } + SWITCH_END +#endif /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */ +#if USB_CFG_DESCR_PROPS_HID_REPORT /* only support HID descriptors if enabled */ + SWITCH_CASE(USBDESCR_HID) /* 0x21 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID, usbDescriptorConfiguration + 18) + SWITCH_CASE(USBDESCR_HID_REPORT)/* 0x22 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID_REPORT, usbDescriptorHidReport) +#endif + SWITCH_DEFAULT + if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){ + len = usbFunctionDescriptor(rq); + } + SWITCH_END + usbMsgFlags = flags; + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbDriverSetup() is similar to usbFunctionSetup(), but it's used for + * standard requests instead of class and custom requests. + */ +static inline usbMsgLen_t usbDriverSetup(usbRequest_t *rq) +{ +uchar len = 0, *dataPtr = usbTxBuf + 9; /* there are 2 bytes free space at the end of the buffer */ +uchar value = rq->wValue.bytes[0]; +#if USB_CFG_IMPLEMENT_HALT +uchar index = rq->wIndex.bytes[0]; +#endif + + dataPtr[0] = 0; /* default reply common to USBRQ_GET_STATUS and USBRQ_GET_INTERFACE */ + SWITCH_START(rq->bRequest) + SWITCH_CASE(USBRQ_GET_STATUS) /* 0 */ + uchar recipient = rq->bmRequestType & USBRQ_RCPT_MASK; /* assign arith ops to variables to enforce byte size */ + if(USB_CFG_IS_SELF_POWERED && recipient == USBRQ_RCPT_DEVICE) + dataPtr[0] = USB_CFG_IS_SELF_POWERED; +#if USB_CFG_IMPLEMENT_HALT + if(recipient == USBRQ_RCPT_ENDPOINT && index == 0x81) /* request status for endpoint 1 */ + dataPtr[0] = usbTxLen1 == USBPID_STALL; +#endif + dataPtr[1] = 0; + len = 2; +#if USB_CFG_IMPLEMENT_HALT + SWITCH_CASE2(USBRQ_CLEAR_FEATURE, USBRQ_SET_FEATURE) /* 1, 3 */ + if(value == 0 && index == 0x81){ /* feature 0 == HALT for endpoint == 1 */ + usbTxLen1 = rq->bRequest == USBRQ_CLEAR_FEATURE ? USBPID_NAK : USBPID_STALL; + usbResetDataToggling(); + } +#endif + SWITCH_CASE(USBRQ_SET_ADDRESS) /* 5 */ + usbNewDeviceAddr = value; + USB_SET_ADDRESS_HOOK(); + SWITCH_CASE(USBRQ_GET_DESCRIPTOR) /* 6 */ + len = usbDriverDescriptor(rq); + goto skipMsgPtrAssignment; + SWITCH_CASE(USBRQ_GET_CONFIGURATION) /* 8 */ + dataPtr = &usbConfiguration; /* send current configuration value */ + len = 1; + SWITCH_CASE(USBRQ_SET_CONFIGURATION) /* 9 */ + usbConfiguration = value; + usbResetStall(); + SWITCH_CASE(USBRQ_GET_INTERFACE) /* 10 */ + len = 1; +#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE + SWITCH_CASE(USBRQ_SET_INTERFACE) /* 11 */ + usbResetDataToggling(); + usbResetStall(); +#endif + SWITCH_DEFAULT /* 7=SET_DESCRIPTOR, 12=SYNC_FRAME */ + /* Should we add an optional hook here? */ + SWITCH_END + usbMsgPtr = dataPtr; +skipMsgPtrAssignment: + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbProcessRx() is called for every message received by the interrupt + * routine. It distinguishes between SETUP and DATA packets and processes + * them accordingly. + */ +static inline void usbProcessRx(uchar *data, uchar len) +{ + usbRequest_t *rq = (usbRequest_t *)((void *)data); + +/* usbRxToken can be: + * 0x2d 00101101 (USBPID_SETUP for setup data) + * 0xe1 11100001 (USBPID_OUT: data phase of setup transfer) + * 0...0x0f for OUT on endpoint X + */ + DBG2(0x10 + (usbRxToken & 0xf), data, len + 2); /* SETUP=1d, SETUP-DATA=11, OUTx=1x */ + USB_RX_USER_HOOK(data, len) +#if USB_CFG_IMPLEMENT_FN_WRITEOUT + if(usbRxToken < 0x10){ /* OUT to endpoint != 0: endpoint number in usbRxToken */ + usbFunctionWriteOut(data, len); + return; + } +#endif + if(usbRxToken == (uchar)USBPID_SETUP){ + if(len != 8) /* Setup size must be always 8 bytes. Ignore otherwise. */ + return; + usbMsgLen_t replyLen; + usbTxBuf[0] = USBPID_DATA0; /* initialize data toggling */ + usbTxLen = USBPID_NAK; /* abort pending transmit */ + usbMsgFlags = 0; + uchar type = rq->bmRequestType & USBRQ_TYPE_MASK; + if(type != USBRQ_TYPE_STANDARD){ /* standard requests are handled by driver */ + replyLen = usbFunctionSetup(data); + }else{ + replyLen = usbDriverSetup(rq); + } +#if USB_CFG_IMPLEMENT_FN_READ || USB_CFG_IMPLEMENT_FN_WRITE + if(replyLen == USB_NO_MSG){ /* use user-supplied read/write function */ + /* do some conditioning on replyLen, but on IN transfers only */ + if((rq->bmRequestType & USBRQ_DIR_MASK) != USBRQ_DIR_HOST_TO_DEVICE){ + if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */ + replyLen = rq->wLength.bytes[0]; + }else{ + replyLen = rq->wLength.word; + } + } + usbMsgFlags = USB_FLG_USE_USER_RW; + }else /* The 'else' prevents that we limit a replyLen of USB_NO_MSG to the maximum transfer len. */ +#endif + if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */ + if(!rq->wLength.bytes[1] && replyLen > rq->wLength.bytes[0]) /* limit length to max */ + replyLen = rq->wLength.bytes[0]; + }else{ + if(replyLen > rq->wLength.word) /* limit length to max */ + replyLen = rq->wLength.word; + } + usbMsgLen = replyLen; + }else{ /* usbRxToken must be USBPID_OUT, which means data phase of setup (control-out) */ +#if USB_CFG_IMPLEMENT_FN_WRITE + if(usbMsgFlags & USB_FLG_USE_USER_RW){ + uchar rval = usbFunctionWrite(data, len); + if(rval == 0xff){ /* an error occurred */ + usbTxLen = USBPID_STALL; + }else if(rval != 0){ /* This was the final package */ + usbMsgLen = 0; /* answer with a zero-sized data packet */ + } + } +#endif + } +} + +/* ------------------------------------------------------------------------- */ + +/* This function is similar to usbFunctionRead(), but it's also called for + * data handled automatically by the driver (e.g. descriptor reads). + */ +static uchar usbDeviceRead(uchar *data, uchar len) +{ + if(len > 0){ /* don't bother app with 0 sized reads */ +#if USB_CFG_IMPLEMENT_FN_READ + if(usbMsgFlags & USB_FLG_USE_USER_RW){ + len = usbFunctionRead(data, len); + }else +#endif + { + uchar i = len, *r = usbMsgPtr; + if(usbMsgFlags & USB_FLG_MSGPTR_IS_ROM){ /* ROM data */ + do{ + uchar c = USB_READ_FLASH(r); /* assign to char size variable to enforce byte ops */ + *data++ = c; + r++; + }while(--i); + }else{ /* RAM data */ + do{ + *data++ = *r++; + }while(--i); + } + usbMsgPtr = r; + } + } + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbBuildTxBlock() is called when we have data to transmit and the + * interrupt routine's transmit buffer is empty. + */ +static inline void usbBuildTxBlock(void) +{ +usbMsgLen_t wantLen; +uchar len; + + wantLen = usbMsgLen; + if(wantLen > 8) + wantLen = 8; + usbMsgLen -= wantLen; + usbTxBuf[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* DATA toggling */ + len = usbDeviceRead(usbTxBuf + 1, wantLen); + if(len <= 8){ /* valid data packet */ + usbCrc16Append(&usbTxBuf[1], len); + len += 4; /* length including sync byte */ + if(len < 12) /* a partial package identifies end of message */ + usbMsgLen = USB_NO_MSG; + }else{ + len = USBPID_STALL; /* stall the endpoint */ + usbMsgLen = USB_NO_MSG; + } + usbTxLen = len; + DBG2(0x20, usbTxBuf, len-1); +} + +/* ------------------------------------------------------------------------- */ + +static inline void usbHandleResetHook(uchar notResetState) +{ +#ifdef USB_RESET_HOOK +static uchar wasReset; +uchar isReset = !notResetState; + + if(wasReset != isReset){ + USB_RESET_HOOK(isReset); + wasReset = isReset; + } +#endif +} + +/* ------------------------------------------------------------------------- */ + +USB_PUBLIC void usbPoll(void) +{ +schar len; +uchar i; + + len = usbRxLen - 3; + if(len >= 0){ +/* We could check CRC16 here -- but ACK has already been sent anyway. If you + * need data integrity checks with this driver, check the CRC in your app + * code and report errors back to the host. Since the ACK was already sent, + * retries must be handled on application level. + * unsigned crc = usbCrc16(buffer + 1, usbRxLen - 3); + */ + usbProcessRx(usbRxBuf + USB_BUFSIZE + 1 - usbInputBufOffset, len); +#if USB_CFG_HAVE_FLOWCONTROL + if(usbRxLen > 0) /* only mark as available if not inactivated */ + usbRxLen = 0; +#else + usbRxLen = 0; /* mark rx buffer as available */ +#endif + } + if(usbTxLen & 0x10){ /* transmit system idle */ + if(usbMsgLen != USB_NO_MSG){ /* transmit data pending? */ + usbBuildTxBlock(); + } + } + for(i = 20; i > 0; i--){ + uchar usbLineStatus = USBIN & USBMASK; + if(usbLineStatus != 0) /* SE0 has ended */ + goto isNotReset; + } + /* RESET condition, called multiple times during reset */ + usbNewDeviceAddr = 0; + usbDeviceAddr = 0; + usbResetStall(); + DBG1(0xff, 0, 0); +isNotReset: + usbHandleResetHook(i); +} + +/* ------------------------------------------------------------------------- */ + +USB_PUBLIC void usbInit(void) +{ +#if USB_INTR_CFG_SET != 0 + USB_INTR_CFG |= USB_INTR_CFG_SET; +#endif +#if USB_INTR_CFG_CLR != 0 + USB_INTR_CFG &= ~(USB_INTR_CFG_CLR); +#endif + USB_INTR_ENABLE |= (1 << USB_INTR_ENABLE_BIT); + usbResetDataToggling(); +#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE + usbTxLen1 = USBPID_NAK; +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 + usbTxLen3 = USBPID_NAK; +#endif +#endif +} + +/* ------------------------------------------------------------------------- */ diff --git a/hardware/digistump/avr/libraries/DigiMouse/usbdrv.h b/hardware/digistump/avr/libraries/DigiMouse/usbdrv.h new file mode 100644 index 0000000..e766173 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/usbdrv.h @@ -0,0 +1,766 @@ +/* Name: usbdrv.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2004-12-29 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbdrv.h 769 2009-08-22 11:49:05Z cs $ + */ + +#ifndef __usbdrv_h_included__ +#define __usbdrv_h_included__ + +#include "usbconfig.h" +#include "usbportability.h" + +/* +Hardware Prerequisites: +======================= +USB lines D+ and D- MUST be wired to the same I/O port. We recommend that D+ +triggers the interrupt (best achieved by using INT0 for D+), but it is also +possible to trigger the interrupt from D-. If D- is used, interrupts are also +triggered by SOF packets. D- requires a pull-up of 1.5k to +3.5V (and the +device must be powered at 3.5V) to identify as low-speed USB device. A +pull-down or pull-up of 1M SHOULD be connected from D+ to +3.5V to prevent +interference when no USB master is connected. If you use Zener diodes to limit +the voltage on D+ and D-, you MUST use a pull-down resistor, not a pull-up. +We use D+ as interrupt source and not D- because it does not trigger on +keep-alive and RESET states. If you want to count keep-alive events with +USB_COUNT_SOF, you MUST use D- as an interrupt source. + +As a compile time option, the 1.5k pull-up resistor on D- can be made +switchable to allow the device to disconnect at will. See the definition of +usbDeviceConnect() and usbDeviceDisconnect() further down in this file. + +Please adapt the values in usbconfig.h according to your hardware! + +The device MUST be clocked at exactly 12 MHz, 15 MHz, 16 MHz or 20 MHz +or at 12.8 MHz resp. 16.5 MHz +/- 1%. See usbconfig-prototype.h for details. + + +Limitations: +============ +Robustness with respect to communication errors: +The driver assumes error-free communication. It DOES check for errors in +the PID, but does NOT check bit stuffing errors, SE0 in middle of a byte, +token CRC (5 bit) and data CRC (16 bit). CRC checks can not be performed due +to timing constraints: We must start sending a reply within 7 bit times. +Bit stuffing and misplaced SE0 would have to be checked in real-time, but CPU +performance does not permit that. The driver does not check Data0/Data1 +toggling, but application software can implement the check. + +Input characteristics: +Since no differential receiver circuit is used, electrical interference +robustness may suffer. The driver samples only one of the data lines with +an ordinary I/O pin's input characteristics. However, since this is only a +low speed USB implementation and the specification allows for 8 times the +bit rate over the same hardware, we should be on the safe side. Even the spec +requires detection of asymmetric states at high bit rate for SE0 detection. + +Number of endpoints: +The driver supports the following endpoints: + +- Endpoint 0, the default control endpoint. +- Any number of interrupt- or bulk-out endpoints. The data is sent to + usbFunctionWriteOut() and USB_CFG_IMPLEMENT_FN_WRITEOUT must be defined + to 1 to activate this feature. The endpoint number can be found in the + global variable 'usbRxToken'. +- One default interrupt- or bulk-in endpoint. This endpoint is used for + interrupt- or bulk-in transfers which are not handled by any other endpoint. + You must define USB_CFG_HAVE_INTRIN_ENDPOINT in order to activate this + feature and call usbSetInterrupt() to send interrupt/bulk data. +- One additional interrupt- or bulk-in endpoint. This was endpoint 3 in + previous versions of this driver but can now be configured to any endpoint + number. You must define USB_CFG_HAVE_INTRIN_ENDPOINT3 in order to activate + this feature and call usbSetInterrupt3() to send interrupt/bulk data. The + endpoint number can be set with USB_CFG_EP3_NUMBER. + +Please note that the USB standard forbids bulk endpoints for low speed devices! +Most operating systems allow them anyway, but the AVR will spend 90% of the CPU +time in the USB interrupt polling for bulk data. + +Maximum data payload: +Data payload of control in and out transfers may be up to 254 bytes. In order +to accept payload data of out transfers, you need to implement +'usbFunctionWrite()'. + +USB Suspend Mode supply current: +The USB standard limits power consumption to 500uA when the bus is in suspend +mode. This is not a problem for self-powered devices since they don't need +bus power anyway. Bus-powered devices can achieve this only by putting the +CPU in sleep mode. The driver does not implement suspend handling by itself. +However, the application may implement activity monitoring and wakeup from +sleep. The host sends regular SE0 states on the bus to keep it active. These +SE0 states can be detected by using D- as the interrupt source. Define +USB_COUNT_SOF to 1 and use the global variable usbSofCount to check for bus +activity. + +Operation without an USB master: +The driver behaves neutral without connection to an USB master if D- reads +as 1. To avoid spurious interrupts, we recommend a high impedance (e.g. 1M) +pull-down or pull-up resistor on D+ (interrupt). If Zener diodes are used, +use a pull-down. If D- becomes statically 0, the driver may block in the +interrupt routine. + +Interrupt latency: +The application must ensure that the USB interrupt is not disabled for more +than 25 cycles (this is for 12 MHz, faster clocks allow longer latency). +This implies that all interrupt routines must either be declared as "INTERRUPT" +instead of "SIGNAL" (see "avr/signal.h") or that they are written in assembler +with "sei" as the first instruction. + +Maximum interrupt duration / CPU cycle consumption: +The driver handles all USB communication during the interrupt service +routine. The routine will not return before an entire USB message is received +and the reply is sent. This may be up to ca. 1200 cycles @ 12 MHz (= 100us) if +the host conforms to the standard. The driver will consume CPU cycles for all +USB messages, even if they address another (low-speed) device on the same bus. + +*/ + +/* ------------------------------------------------------------------------- */ +/* --------------------------- Module Interface ---------------------------- */ +/* ------------------------------------------------------------------------- */ + +#define USBDRV_VERSION 20090822 +/* This define uniquely identifies a driver version. It is a decimal number + * constructed from the driver's release date in the form YYYYMMDD. If the + * driver's behavior or interface changes, you can use this constant to + * distinguish versions. If it is not defined, the driver's release date is + * older than 2006-01-25. + */ + + +#ifndef USB_PUBLIC +#define USB_PUBLIC +#endif +/* USB_PUBLIC is used as declaration attribute for all functions exported by + * the USB driver. The default is no attribute (see above). You may define it + * to static either in usbconfig.h or from the command line if you include + * usbdrv.c instead of linking against it. Including the C module of the driver + * directly in your code saves a couple of bytes in flash memory. + */ + +#ifndef __ASSEMBLER__ +#ifndef uchar +#define uchar unsigned char +#endif +#ifndef schar +#define schar signed char +#endif +/* shortcuts for well defined 8 bit integer types */ + +#if USB_CFG_LONG_TRANSFERS /* if more than 254 bytes transfer size required */ +# define usbMsgLen_t unsigned +#else +# define usbMsgLen_t uchar +#endif +/* usbMsgLen_t is the data type used for transfer lengths. By default, it is + * defined to uchar, allowing a maximum of 254 bytes (255 is reserved for + * USB_NO_MSG below). If the usbconfig.h defines USB_CFG_LONG_TRANSFERS to 1, + * a 16 bit data type is used, allowing up to 16384 bytes (the rest is used + * for flags in the descriptor configuration). + */ +#define USB_NO_MSG ((usbMsgLen_t)-1) /* constant meaning "no message" */ + +struct usbRequest; /* forward declaration */ + +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbInit(void); +/* This function must be called before interrupts are enabled and the main + * loop is entered. We exepct that the PORT and DDR bits for D+ and D- have + * not been changed from their default status (which is 0). If you have changed + * them, set both back to 0 (configure them as input with no internal pull-up). + */ +USB_PUBLIC void usbPoll(void); +/* This function must be called at regular intervals from the main loop. + * Maximum delay between calls is somewhat less than 50ms (USB timeout for + * accepting a Setup message). Otherwise the device will not be recognized. + * Please note that debug outputs through the UART take ~ 0.5ms per byte + * at 19200 bps. + */ +#ifdef __cplusplus +} // extern "C" +#endif +extern const uchar *usbMsgPtr; +/* This variable may be used to pass transmit data to the driver from the + * implementation of usbFunctionWrite(). It is also used internally by the + * driver for standard control requests. + */ +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC usbMsgLen_t usbFunctionSetup(uchar data[8]); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function is called when the driver receives a SETUP transaction from + * the host which is not answered by the driver itself (in practice: class and + * vendor requests). All control transfers start with a SETUP transaction where + * the host communicates the parameters of the following (optional) data + * transfer. The SETUP data is available in the 'data' parameter which can + * (and should) be casted to 'usbRequest_t *' for a more user-friendly access + * to parameters. + * + * If the SETUP indicates a control-in transfer, you should provide the + * requested data to the driver. There are two ways to transfer this data: + * (1) Set the global pointer 'usbMsgPtr' to the base of the static RAM data + * block and return the length of the data in 'usbFunctionSetup()'. The driver + * will handle the rest. Or (2) return USB_NO_MSG in 'usbFunctionSetup()'. The + * driver will then call 'usbFunctionRead()' when data is needed. See the + * documentation for usbFunctionRead() for details. + * + * If the SETUP indicates a control-out transfer, the only way to receive the + * data from the host is through the 'usbFunctionWrite()' call. If you + * implement this function, you must return USB_NO_MSG in 'usbFunctionSetup()' + * to indicate that 'usbFunctionWrite()' should be used. See the documentation + * of this function for more information. If you just want to ignore the data + * sent by the host, return 0 in 'usbFunctionSetup()'. + * + * Note that calls to the functions usbFunctionRead() and usbFunctionWrite() + * are only done if enabled by the configuration in usbconfig.h. + */ +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC usbMsgLen_t usbFunctionDescriptor(struct usbRequest *rq); +#ifdef __cplusplus +} // extern "C" +#endif +/* You need to implement this function ONLY if you provide USB descriptors at + * runtime (which is an expert feature). It is very similar to + * usbFunctionSetup() above, but it is called only to request USB descriptor + * data. See the documentation of usbFunctionSetup() above for more info. + */ +#if USB_CFG_HAVE_INTRIN_ENDPOINT +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function sets the message which will be sent during the next interrupt + * IN transfer. The message is copied to an internal buffer and must not exceed + * a length of 8 bytes. The message may be 0 bytes long just to indicate the + * interrupt status to the host. + * If you need to transfer more bytes, use a control read after the interrupt. + */ +#define usbInterruptIsReady() (usbTxLen1 & 0x10) +/* This macro indicates whether the last interrupt message has already been + * sent. If you set a new interrupt message before the old was sent, the + * message already buffered will be lost. + */ +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 +USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len); +#define usbInterruptIsReady3() (usbTxLen3 & 0x10) +/* Same as above for endpoint 3 */ +#endif +#endif /* USB_CFG_HAVE_INTRIN_ENDPOINT */ +#if USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH /* simplified interface for backward compatibility */ +#define usbHidReportDescriptor usbDescriptorHidReport +/* should be declared as: PROGMEM char usbHidReportDescriptor[]; */ +/* If you implement an HID device, you need to provide a report descriptor. + * The HID report descriptor syntax is a bit complex. If you understand how + * report descriptors are constructed, we recommend that you use the HID + * Descriptor Tool from usb.org, see http://www.usb.org/developers/hidpage/. + * Otherwise you should probably start with a working example. + */ +#endif /* USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH */ +#if USB_CFG_IMPLEMENT_FN_WRITE +USB_PUBLIC uchar usbFunctionWrite(uchar *data, uchar len); +/* This function is called by the driver to provide a control transfer's + * payload data (control-out). It is called in chunks of up to 8 bytes. The + * total count provided in the current control transfer can be obtained from + * the 'length' property in the setup data. If an error occurred during + * processing, return 0xff (== -1). The driver will answer the entire transfer + * with a STALL token in this case. If you have received the entire payload + * successfully, return 1. If you expect more data, return 0. If you don't + * know whether the host will send more data (you should know, the total is + * provided in the usbFunctionSetup() call!), return 1. + * NOTE: If you return 0xff for STALL, 'usbFunctionWrite()' may still be called + * for the remaining data. You must continue to return 0xff for STALL in these + * calls. + * In order to get usbFunctionWrite() called, define USB_CFG_IMPLEMENT_FN_WRITE + * to 1 in usbconfig.h and return 0xff in usbFunctionSetup().. + */ +#endif /* USB_CFG_IMPLEMENT_FN_WRITE */ +#if USB_CFG_IMPLEMENT_FN_READ +USB_PUBLIC uchar usbFunctionRead(uchar *data, uchar len); +/* This function is called by the driver to ask the application for a control + * transfer's payload data (control-in). It is called in chunks of up to 8 + * bytes each. You should copy the data to the location given by 'data' and + * return the actual number of bytes copied. If you return less than requested, + * the control-in transfer is terminated. If you return 0xff, the driver aborts + * the transfer with a STALL token. + * In order to get usbFunctionRead() called, define USB_CFG_IMPLEMENT_FN_READ + * to 1 in usbconfig.h and return 0xff in usbFunctionSetup().. + */ +#endif /* USB_CFG_IMPLEMENT_FN_READ */ + +extern uchar usbRxToken; /* may be used in usbFunctionWriteOut() below */ +#if USB_CFG_IMPLEMENT_FN_WRITEOUT +USB_PUBLIC void usbFunctionWriteOut(uchar *data, uchar len); +/* This function is called by the driver when data is received on an interrupt- + * or bulk-out endpoint. The endpoint number can be found in the global + * variable usbRxToken. You must define USB_CFG_IMPLEMENT_FN_WRITEOUT to 1 in + * usbconfig.h to get this function called. + */ +#endif /* USB_CFG_IMPLEMENT_FN_WRITEOUT */ +#ifdef USB_CFG_PULLUP_IOPORTNAME +#define usbDeviceConnect() ((USB_PULLUP_DDR |= (1<device, 1=device->host + * t ..... type: 0=standard, 1=class, 2=vendor, 3=reserved + * r ..... recipient: 0=device, 1=interface, 2=endpoint, 3=other + */ + +/* USB setup recipient values */ +#define USBRQ_RCPT_MASK 0x1f +#define USBRQ_RCPT_DEVICE 0 +#define USBRQ_RCPT_INTERFACE 1 +#define USBRQ_RCPT_ENDPOINT 2 + +/* USB request type values */ +#define USBRQ_TYPE_MASK 0x60 +#define USBRQ_TYPE_STANDARD (0<<5) +#define USBRQ_TYPE_CLASS (1<<5) +#define USBRQ_TYPE_VENDOR (2<<5) + +/* USB direction values: */ +#define USBRQ_DIR_MASK 0x80 +#define USBRQ_DIR_HOST_TO_DEVICE (0<<7) +#define USBRQ_DIR_DEVICE_TO_HOST (1<<7) + +/* USB Standard Requests */ +#define USBRQ_GET_STATUS 0 +#define USBRQ_CLEAR_FEATURE 1 +#define USBRQ_SET_FEATURE 3 +#define USBRQ_SET_ADDRESS 5 +#define USBRQ_GET_DESCRIPTOR 6 +#define USBRQ_SET_DESCRIPTOR 7 +#define USBRQ_GET_CONFIGURATION 8 +#define USBRQ_SET_CONFIGURATION 9 +#define USBRQ_GET_INTERFACE 10 +#define USBRQ_SET_INTERFACE 11 +#define USBRQ_SYNCH_FRAME 12 + +/* USB descriptor constants */ +#define USBDESCR_DEVICE 1 +#define USBDESCR_CONFIG 2 +#define USBDESCR_STRING 3 +#define USBDESCR_INTERFACE 4 +#define USBDESCR_ENDPOINT 5 +#define USBDESCR_HID 0x21 +#define USBDESCR_HID_REPORT 0x22 +#define USBDESCR_HID_PHYS 0x23 + +//#define USBATTR_BUSPOWER 0x80 // USB 1.1 does not define this value any more +#define USBATTR_SELFPOWER 0x40 +#define USBATTR_REMOTEWAKE 0x20 + +/* USB HID Requests */ +#define USBRQ_HID_GET_REPORT 0x01 +#define USBRQ_HID_GET_IDLE 0x02 +#define USBRQ_HID_GET_PROTOCOL 0x03 +#define USBRQ_HID_SET_REPORT 0x09 +#define USBRQ_HID_SET_IDLE 0x0a +#define USBRQ_HID_SET_PROTOCOL 0x0b + +/* ------------------------------------------------------------------------- */ + +#endif /* __usbdrv_h_included__ */ diff --git a/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm.S b/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm.S new file mode 100644 index 0000000..80877e4 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm.S @@ -0,0 +1,385 @@ +/* Name: usbdrvasm.S + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2007-06-13 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm.S 761 2009-08-12 16:30:23Z cs $ + */ + +/* +General Description: +This module is the assembler part of the USB driver. This file contains +general code (preprocessor acrobatics and CRC computation) and then includes +the file appropriate for the given clock rate. +*/ + +#define __SFR_OFFSET 0 /* used by avr-libc's register definitions */ +#include "usbportability.h" +#include "usbdrv.h" /* for common defs */ + +/* register names */ +#define x1 r16 +#define x2 r17 +#define shift r18 +#define cnt r19 +#define x3 r20 +#define x4 r21 +#define x5 r22 +#define bitcnt x5 +#define phase x4 +#define leap x4 + +/* Some assembler dependent definitions and declarations: */ + +#ifdef __IAR_SYSTEMS_ASM__ + extern usbRxBuf, usbDeviceAddr, usbNewDeviceAddr, usbInputBufOffset + extern usbCurrentTok, usbRxLen, usbRxToken, usbTxLen + extern usbTxBuf, usbTxStatus1, usbTxStatus3 +# if USB_COUNT_SOF + extern usbSofCount +# endif + public usbCrc16 + public usbCrc16Append + + COMMON INTVEC +# ifndef USB_INTR_VECTOR + ORG INT0_vect +# else /* USB_INTR_VECTOR */ + ORG USB_INTR_VECTOR +# undef USB_INTR_VECTOR +# endif /* USB_INTR_VECTOR */ +# define USB_INTR_VECTOR usbInterruptHandler + rjmp USB_INTR_VECTOR + RSEG CODE + +#else /* __IAR_SYSTEMS_ASM__ */ + +# ifndef USB_INTR_VECTOR /* default to hardware interrupt INT0 */ +# define USB_INTR_VECTOR SIG_INTERRUPT0 +# endif + .text + .global USB_INTR_VECTOR + .type USB_INTR_VECTOR, @function + .global usbCrc16 + .global usbCrc16Append +#endif /* __IAR_SYSTEMS_ASM__ */ + + +#if USB_INTR_PENDING < 0x40 /* This is an I/O address, use in and out */ +# define USB_LOAD_PENDING(reg) in reg, USB_INTR_PENDING +# define USB_STORE_PENDING(reg) out USB_INTR_PENDING, reg +#else /* It's a memory address, use lds and sts */ +# define USB_LOAD_PENDING(reg) lds reg, USB_INTR_PENDING +# define USB_STORE_PENDING(reg) sts USB_INTR_PENDING, reg +#endif + +#define usbTxLen1 usbTxStatus1 +#define usbTxBuf1 (usbTxStatus1 + 1) +#define usbTxLen3 usbTxStatus3 +#define usbTxBuf3 (usbTxStatus3 + 1) + + +;---------------------------------------------------------------------------- +; Utility functions +;---------------------------------------------------------------------------- + +#ifdef __IAR_SYSTEMS_ASM__ +/* Register assignments for usbCrc16 on IAR cc */ +/* Calling conventions on IAR: + * First parameter passed in r16/r17, second in r18/r19 and so on. + * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer) + * Result is passed in r16/r17 + * In case of the "tiny" memory model, pointers are only 8 bit with no + * padding. We therefore pass argument 1 as "16 bit unsigned". + */ +RTMODEL "__rt_version", "3" +/* The line above will generate an error if cc calling conventions change. + * The value "3" above is valid for IAR 4.10B/W32 + */ +# define argLen r18 /* argument 2 */ +# define argPtrL r16 /* argument 1 */ +# define argPtrH r17 /* argument 1 */ + +# define resCrcL r16 /* result */ +# define resCrcH r17 /* result */ + +# define ptrL ZL +# define ptrH ZH +# define ptr Z +# define byte r22 +# define bitCnt r19 +# define polyL r20 +# define polyH r21 +# define scratch r23 + +#else /* __IAR_SYSTEMS_ASM__ */ +/* Register assignments for usbCrc16 on gcc */ +/* Calling conventions on gcc: + * First parameter passed in r24/r25, second in r22/23 and so on. + * Callee must preserve r1-r17, r28/r29 + * Result is passed in r24/r25 + */ +# define argLen r22 /* argument 2 */ +# define argPtrL r24 /* argument 1 */ +# define argPtrH r25 /* argument 1 */ + +# define resCrcL r24 /* result */ +# define resCrcH r25 /* result */ + +# define ptrL XL +# define ptrH XH +# define ptr x +# define byte r18 +# define bitCnt r19 +# define polyL r20 +# define polyH r21 +# define scratch r23 + +#endif + +#if USB_USE_FAST_CRC + +; This implementation is faster, but has bigger code size +; Thanks to Slawomir Fras (BoskiDialer) for this code! +; It implements the following C pseudo-code: +; unsigned table(unsigned char x) +; { +; unsigned value; +; +; value = (unsigned)x << 6; +; value ^= (unsigned)x << 7; +; if(parity(x)) +; value ^= 0xc001; +; return value; +; } +; unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen) +; { +; unsigned crc = 0xffff; +; +; while(argLen--) +; crc = table(lo8(crc) ^ *argPtr++) ^ hi8(crc); +; return ~crc; +; } + +; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen); +; argPtr r24+25 / r16+r17 +; argLen r22 / r18 +; temp variables: +; byte r18 / r22 +; scratch r23 +; resCrc r24+r25 / r16+r17 +; ptr X / Z +usbCrc16: + mov ptrL, argPtrL + mov ptrH, argPtrH + ldi resCrcL, 0xFF + ldi resCrcH, 0xFF + rjmp usbCrc16LoopTest +usbCrc16ByteLoop: + ld byte, ptr+ + eor resCrcL, byte ; resCrcL is now 'x' in table() + mov byte, resCrcL ; compute parity of 'x' + swap byte + eor byte, resCrcL + mov scratch, byte + lsr byte + lsr byte + eor byte, scratch + inc byte + lsr byte + andi byte, 1 ; byte is now parity(x) + mov scratch, resCrcL + mov resCrcL, resCrcH + eor resCrcL, byte ; low byte of if(parity(x)) value ^= 0xc001; + neg byte + andi byte, 0xc0 + mov resCrcH, byte ; high byte of if(parity(x)) value ^= 0xc001; + clr byte + lsr scratch + ror byte + eor resCrcH, scratch + eor resCrcL, byte + lsr scratch + ror byte + eor resCrcH, scratch + eor resCrcL, byte +usbCrc16LoopTest: + subi argLen, 1 + brsh usbCrc16ByteLoop + com resCrcL + com resCrcH + ret + +#else /* USB_USE_FAST_CRC */ + +; This implementation is slower, but has less code size +; +; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen); +; argPtr r24+25 / r16+r17 +; argLen r22 / r18 +; temp variables: +; byte r18 / r22 +; bitCnt r19 +; poly r20+r21 +; scratch r23 +; resCrc r24+r25 / r16+r17 +; ptr X / Z +usbCrc16: + mov ptrL, argPtrL + mov ptrH, argPtrH + ldi resCrcL, 0 + ldi resCrcH, 0 + ldi polyL, lo8(0xa001) + ldi polyH, hi8(0xa001) + com argLen ; argLen = -argLen - 1: modified loop to ensure that carry is set + ldi bitCnt, 0 ; loop counter with starnd condition = end condition + rjmp usbCrcLoopEntry +usbCrcByteLoop: + ld byte, ptr+ + eor resCrcL, byte +usbCrcBitLoop: + ror resCrcH ; carry is always set here (see brcs jumps to here) + ror resCrcL + brcs usbCrcNoXor + eor resCrcL, polyL + eor resCrcH, polyH +usbCrcNoXor: + subi bitCnt, 224 ; (8 * 224) % 256 = 0; this loop iterates 8 times + brcs usbCrcBitLoop +usbCrcLoopEntry: + subi argLen, -1 + brcs usbCrcByteLoop +usbCrcReady: + ret +; Thanks to Reimar Doeffinger for optimizing this CRC routine! + +#endif /* USB_USE_FAST_CRC */ + +; extern unsigned usbCrc16Append(unsigned char *data, unsigned char len); +usbCrc16Append: + rcall usbCrc16 + st ptr+, resCrcL + st ptr+, resCrcH + ret + +#undef argLen +#undef argPtrL +#undef argPtrH +#undef resCrcL +#undef resCrcH +#undef ptrL +#undef ptrH +#undef ptr +#undef byte +#undef bitCnt +#undef polyL +#undef polyH +#undef scratch + + +#if USB_CFG_HAVE_MEASURE_FRAME_LENGTH +#ifdef __IAR_SYSTEMS_ASM__ +/* Register assignments for usbMeasureFrameLength on IAR cc */ +/* Calling conventions on IAR: + * First parameter passed in r16/r17, second in r18/r19 and so on. + * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer) + * Result is passed in r16/r17 + * In case of the "tiny" memory model, pointers are only 8 bit with no + * padding. We therefore pass argument 1 as "16 bit unsigned". + */ +# define resL r16 +# define resH r17 +# define cnt16L r30 +# define cnt16H r31 +# define cntH r18 + +#else /* __IAR_SYSTEMS_ASM__ */ +/* Register assignments for usbMeasureFrameLength on gcc */ +/* Calling conventions on gcc: + * First parameter passed in r24/r25, second in r22/23 and so on. + * Callee must preserve r1-r17, r28/r29 + * Result is passed in r24/r25 + */ +# define resL r24 +# define resH r25 +# define cnt16L r24 +# define cnt16H r25 +# define cntH r26 +#endif +# define cnt16 cnt16L + +; extern unsigned usbMeasurePacketLength(void); +; returns time between two idle strobes in multiples of 7 CPU clocks +.global usbMeasureFrameLength +usbMeasureFrameLength: + ldi cntH, 6 ; wait ~ 10 ms for D- == 0 + clr cnt16L + clr cnt16H +usbMFTime16: + dec cntH + breq usbMFTimeout +usbMFWaitStrobe: ; first wait for D- == 0 (idle strobe) + sbiw cnt16, 1 ;[0] [6] + breq usbMFTime16 ;[2] + sbic USBIN, USBMINUS ;[3] + rjmp usbMFWaitStrobe ;[4] +usbMFWaitIdle: ; then wait until idle again + sbis USBIN, USBMINUS ;1 wait for D- == 1 + rjmp usbMFWaitIdle ;2 + ldi cnt16L, 1 ;1 represents cycles so far + clr cnt16H ;1 +usbMFWaitLoop: + in cntH, USBIN ;[0] [7] + adiw cnt16, 1 ;[1] + breq usbMFTimeout ;[3] + andi cntH, USBMASK ;[4] + brne usbMFWaitLoop ;[5] +usbMFTimeout: +#if resL != cnt16L + mov resL, cnt16L + mov resH, cnt16H +#endif + ret + +#undef resL +#undef resH +#undef cnt16 +#undef cnt16L +#undef cnt16H +#undef cntH + +#endif /* USB_CFG_HAVE_MEASURE_FRAME_LENGTH */ + +;---------------------------------------------------------------------------- +; Now include the clock rate specific code +;---------------------------------------------------------------------------- + +#ifndef USB_CFG_CLOCK_KHZ +# define USB_CFG_CLOCK_KHZ 12000 +#endif + +#if USB_CFG_CHECK_CRC /* separate dispatcher for CRC type modules */ +# if USB_CFG_CLOCK_KHZ == 18000 +# include "usbdrvasm18-crc.inc" +# else +# error "USB_CFG_CLOCK_KHZ is not one of the supported crc-rates!" +# endif +#else /* USB_CFG_CHECK_CRC */ +# if USB_CFG_CLOCK_KHZ == 12000 +# include "usbdrvasm12.inc" +# elif USB_CFG_CLOCK_KHZ == 12800 +# include "usbdrvasm128.inc" +# elif USB_CFG_CLOCK_KHZ == 15000 +# include "usbdrvasm15.inc" +# elif USB_CFG_CLOCK_KHZ == 16000 +# include "usbdrvasm16.inc" +# elif USB_CFG_CLOCK_KHZ == 16500 +# include "usbdrvasm165.inc" +# elif USB_CFG_CLOCK_KHZ == 20000 +# include "usbdrvasm20.inc" +# else +# error "USB_CFG_CLOCK_KHZ is not one of the supported non-crc-rates!" +# endif +#endif /* USB_CFG_CHECK_CRC */ diff --git a/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm.asm b/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm.asm new file mode 100644 index 0000000..9cc4e4d --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm.asm @@ -0,0 +1,21 @@ +/* Name: usbdrvasm.asm + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2006-03-01 + * Tabsize: 4 + * Copyright: (c) 2006 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id$ + */ + +/* +General Description: +The IAR compiler/assembler system prefers assembler files with file extension +".asm". We simply provide this file as an alias for usbdrvasm.S. + +Thanks to Oleg Semyonov for his help with the IAR tools port! +*/ + +#include "usbdrvasm.S" + +end diff --git a/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm12.inc b/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm12.inc new file mode 100644 index 0000000..c116758 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm12.inc @@ -0,0 +1,393 @@ +/* Name: usbdrvasm12.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2004-12-29 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbdrvasm12.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 12 MHz version of the asssembler part of the USB driver. It +requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! + + +Timing constraints according to spec (in bit times): +timing subject min max CPUcycles +--------------------------------------------------------------------------- +EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128 +EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60 +DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60 +*/ + +;Software-receiver engine. Strict timing! Don't change unless you can preserve timing! +;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled +;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable +;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes +;Numbers in brackets are maximum cycles since SOF. +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt + push YL ;2 [35] push only what is necessary to sync with edge ASAP + in YL, SREG ;1 [37] + push YL ;2 [39] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of 1/4 bit which meets the spec. + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push YH ;2 [2] + lds YL, usbInputBufOffset;2 [4] + clr YH ;1 [5] + subi YL, lo8(-(usbRxBuf));1 [6] + sbci YH, hi8(-(usbRxBuf));1 [7] + + sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early] + rjmp haveTwoBitsK ;2 [10] + pop YH ;2 [11] undo the push from before + rjmp waitForK ;2 [13] this was not the end of sync, retry +haveTwoBitsK: +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- + push shift ;2 [16] + push x1 ;2 [12] + push x2 ;2 [14] + + in x1, USBIN ;1 [17] <-- sample bit 0 + ldi shift, 0xff ;1 [18] + bst x1, USBMINUS ;1 [19] + bld shift, 0 ;1 [20] + push x3 ;2 [22] + push cnt ;2 [24] + + in x2, USBIN ;1 [25] <-- sample bit 1 + ser x3 ;1 [26] [inserted init instruction] + eor x1, x2 ;1 [27] + bst x1, USBMINUS ;1 [28] + bld shift, 1 ;1 [29] + ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction] + rjmp rxbit2 ;2 [32] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- + +unstuff0: ;1 (branch taken) + andi x3, ~0x01 ;1 [15] + mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit + in x2, USBIN ;1 [17] <-- sample bit 1 again + ori shift, 0x01 ;1 [18] + rjmp didUnstuff0 ;2 [20] + +unstuff1: ;1 (branch taken) + mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit + andi x3, ~0x02 ;1 [22] + ori shift, 0x02 ;1 [23] + nop ;1 [24] + in x1, USBIN ;1 [25] <-- sample bit 2 again + rjmp didUnstuff1 ;2 [27] + +unstuff2: ;1 (branch taken) + andi x3, ~0x04 ;1 [29] + ori shift, 0x04 ;1 [30] + mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit + nop ;1 [32] + in x2, USBIN ;1 [33] <-- sample bit 3 + rjmp didUnstuff2 ;2 [35] + +unstuff3: ;1 (branch taken) + in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late] + andi x3, ~0x08 ;1 [35] + ori shift, 0x08 ;1 [36] + rjmp didUnstuff3 ;2 [38] + +unstuff4: ;1 (branch taken) + andi x3, ~0x10 ;1 [40] + in x1, USBIN ;1 [41] <-- sample stuffed bit 4 + ori shift, 0x10 ;1 [42] + rjmp didUnstuff4 ;2 [44] + +unstuff5: ;1 (branch taken) + andi x3, ~0x20 ;1 [48] + in x2, USBIN ;1 [49] <-- sample stuffed bit 5 + ori shift, 0x20 ;1 [50] + rjmp didUnstuff5 ;2 [52] + +unstuff6: ;1 (branch taken) + andi x3, ~0x40 ;1 [56] + in x1, USBIN ;1 [57] <-- sample stuffed bit 6 + ori shift, 0x40 ;1 [58] + rjmp didUnstuff6 ;2 [60] + +; extra jobs done during bit interval: +; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs] +; bit 1: se0 check +; bit 2: overflow check +; bit 3: recovery from delay [bit 0 tasks took too long] +; bit 4: none +; bit 5: none +; bit 6: none +; bit 7: jump, eor +rxLoop: + eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others + in x1, USBIN ;1 [1] <-- sample bit 0 + st y+, x3 ;2 [3] store data + ser x3 ;1 [4] + nop ;1 [5] + eor x2, x1 ;1 [6] + bst x2, USBMINUS;1 [7] + bld shift, 0 ;1 [8] + in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed) + andi x2, USBMASK ;1 [10] + breq se0 ;1 [11] SE0 check for bit 1 + andi shift, 0xf9 ;1 [12] +didUnstuff0: + breq unstuff0 ;1 [13] + eor x1, x2 ;1 [14] + bst x1, USBMINUS;1 [15] + bld shift, 1 ;1 [16] +rxbit2: + in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed) + andi shift, 0xf3 ;1 [18] + breq unstuff1 ;1 [19] do remaining work for bit 1 +didUnstuff1: + subi cnt, 1 ;1 [20] + brcs overflow ;1 [21] loop control + eor x2, x1 ;1 [22] + bst x2, USBMINUS;1 [23] + bld shift, 2 ;1 [24] + in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed) + andi shift, 0xe7 ;1 [26] + breq unstuff2 ;1 [27] +didUnstuff2: + eor x1, x2 ;1 [28] + bst x1, USBMINUS;1 [29] + bld shift, 3 ;1 [30] +didUnstuff3: + andi shift, 0xcf ;1 [31] + breq unstuff3 ;1 [32] + in x1, USBIN ;1 [33] <-- sample bit 4 + eor x2, x1 ;1 [34] + bst x2, USBMINUS;1 [35] + bld shift, 4 ;1 [36] +didUnstuff4: + andi shift, 0x9f ;1 [37] + breq unstuff4 ;1 [38] + nop2 ;2 [40] + in x2, USBIN ;1 [41] <-- sample bit 5 + eor x1, x2 ;1 [42] + bst x1, USBMINUS;1 [43] + bld shift, 5 ;1 [44] +didUnstuff5: + andi shift, 0x3f ;1 [45] + breq unstuff5 ;1 [46] + nop2 ;2 [48] + in x1, USBIN ;1 [49] <-- sample bit 6 + eor x2, x1 ;1 [50] + bst x2, USBMINUS;1 [51] + bld shift, 6 ;1 [52] +didUnstuff6: + cpi shift, 0x02 ;1 [53] + brlo unstuff6 ;1 [54] + nop2 ;2 [56] + in x2, USBIN ;1 [57] <-- sample bit 7 + eor x1, x2 ;1 [58] + bst x1, USBMINUS;1 [59] + bld shift, 7 ;1 [60] +didUnstuff7: + cpi shift, 0x04 ;1 [61] + brsh rxLoop ;2 [63] loop control +unstuff7: + andi x3, ~0x80 ;1 [63] + ori shift, 0x80 ;1 [64] + in x2, USBIN ;1 [65] <-- sample stuffed bit 7 + nop ;1 [66] + rjmp didUnstuff7 ;2 [68] + +macro POP_STANDARD ; 12 cycles + pop cnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;---------------------------------------------------------------------------- +; Transmitting data +;---------------------------------------------------------------------------- + +txByteLoop: +txBitloop: +stuffN1Delay: ; [03] + ror shift ;[-5] [11] [59] + brcc doExorN1 ;[-4] [60] + subi x4, 1 ;[-3] + brne commonN1 ;[-2] + lsl shift ;[-1] compensate ror after rjmp stuffDelay + nop ;[00] stuffing consists of just waiting 8 cycles + rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear + +sendNakAndReti: ;0 [-19] 19 cycles until SOP + ldi x3, USBPID_NAK ;1 [-18] + rjmp usbSendX3 ;2 [-16] +sendAckAndReti: ;0 [-19] 19 cycles until SOP + ldi x3, USBPID_ACK ;1 [-18] + rjmp usbSendX3 ;2 [-16] +sendCntAndReti: ;0 [-17] 17 cycles until SOP + mov x3, cnt ;1 [-16] +usbSendX3: ;0 [-16] + ldi YL, 20 ;1 [-15] 'x3' is R20 + ldi YH, 0 ;1 [-14] + ldi cnt, 2 ;1 [-13] +; rjmp usbSendAndReti fallthrough + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) or USBOUT = 0x01 +; K = (D+ = 1), (D- = 0) or USBOUT = 0x02 +; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles) + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte +;uses: x1...x2, x4, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x4 = bitstuff cnt] +;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction) +usbSendAndReti: + in x2, USBDDR ;[-12] 12 cycles until SOP + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS ;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + out USBDDR, x2 ;[-8] <--- acquire bus + in x1, USBOUT ;[-7] port mirror for tx loop + ldi shift, 0x40 ;[-6] sync byte is first byte sent (we enter loop after ror) + ldi x2, USBMASK ;[-5] + push x4 ;[-4] +doExorN1: + eor x1, x2 ;[-2] [06] [62] + ldi x4, 6 ;[-1] [07] [63] +commonN1: +stuffN2Delay: + out USBOUT, x1 ;[00] [08] [64] <--- set bit + ror shift ;[01] + brcc doExorN2 ;[02] + subi x4, 1 ;[03] + brne commonN2 ;[04] + lsl shift ;[05] compensate ror after rjmp stuffDelay + rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear +doExorN2: + eor x1, x2 ;[04] [12] + ldi x4, 6 ;[05] [13] +commonN2: + nop ;[06] [14] + subi cnt, 171 ;[07] [15] trick: (3 * 171) & 0xff = 1 + out USBOUT, x1 ;[08] [16] <--- set bit + brcs txBitloop ;[09] [25] [41] + +stuff6Delay: + ror shift ;[42] [50] + brcc doExor6 ;[43] + subi x4, 1 ;[44] + brne common6 ;[45] + lsl shift ;[46] compensate ror after rjmp stuffDelay + nop ;[47] stuffing consists of just waiting 8 cycles + rjmp stuff6Delay ;[48] after ror, C bit is reliably clear +doExor6: + eor x1, x2 ;[45] [53] + ldi x4, 6 ;[46] +common6: +stuff7Delay: + ror shift ;[47] [55] + out USBOUT, x1 ;[48] <--- set bit + brcc doExor7 ;[49] + subi x4, 1 ;[50] + brne common7 ;[51] + lsl shift ;[52] compensate ror after rjmp stuffDelay + rjmp stuff7Delay ;[53] after ror, C bit is reliably clear +doExor7: + eor x1, x2 ;[51] [59] + ldi x4, 6 ;[52] +common7: + ld shift, y+ ;[53] + tst cnt ;[55] + out USBOUT, x1 ;[56] <--- set bit + brne txByteLoop ;[57] + +;make SE0: + cbr x1, USBMASK ;[58] prepare SE0 [spec says EOP may be 15 to 18 cycles] + lds x2, usbNewDeviceAddr;[59] + lsl x2 ;[61] we compare with left shifted address + subi YL, 2 + 20 ;[62] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[63] + out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[01] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 12.5625 MHz +max frequency: 69.286 cycles for 8 bit -> 12.99 MHz +nominal frequency: 12.77 MHz ( = sqrt(min * max)) + +sampling positions: (next even number in range [+/- 0.5]) +cycle index range: 0 ... 66 +bits: +.5, 8.875, 17.25, 25.625, 34, 42.375, 50.75, 59.125 +[0/1], [9], [17], [25/+26], [34], [+42/43], [51], [59] + +bit number: 0 1 2 3 4 5 6 7 +spare cycles 1 2 1 2 1 1 1 0 + +operations to perform: duration cycle + ---------------- + eor fix, shift 1 -> 00 + andi phase, USBMASK 1 -> 08 + breq se0 1 -> 16 (moved to 11) + st y+, data 2 -> 24, 25 + mov data, fix 1 -> 33 + ser data 1 -> 41 + subi cnt, 1 1 -> 49 + brcs overflow 1 -> 50 + +layout of samples and operations: +[##] = sample bit +<##> = sample phase +*##* = operation + +0: *00* [01] 02 03 04 <05> 06 07 +1: *08* [09] 10 11 12 <13> 14 15 *16* +2: [17] 18 19 20 <21> 22 23 +3: *24* *25* [26] 27 28 29 <30> 31 32 +4: *33* [34] 35 36 37 <38> 39 40 +5: *41* [42] 43 44 45 <46> 47 48 +6: *49* *50* [51] 52 53 54 <55> 56 57 58 +7: [59] 60 61 62 <63> 64 65 66 +*****************************************************************************/ + +/* we prefer positive expressions (do if condition) instead of negative + * (skip if condition), therefore use defines for skip instructions: + */ +#define ifioclr sbis +#define ifioset sbic +#define ifrclr sbrs +#define ifrset sbrc + +/* The registers "fix" and "data" swap their meaning during the loop. Use + * defines to keep their name constant. + */ +#define fix x2 +#define data x1 +#undef phase /* phase has a default definition to x4 */ +#define phase x3 + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt, r0 + push YL ;2 push only what is necessary to sync with edge ASAP + in YL, SREG ;1 + push YL ;2 +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of 1/4 bit which meets the spec. + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS ;[0] + rjmp foundK ;[1] +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError + +foundK: +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push YH ;[2] + lds YL, usbInputBufOffset;[4] + clr YH ;[6] + subi YL, lo8(-(usbRxBuf));[7] + sbci YH, hi8(-(usbRxBuf));[8] + + sbis USBIN, USBMINUS ;[9] we want two bits K [we want to sample at 8 + 4 - 1.5 = 10.5] + rjmp haveTwoBitsK ;[10] + pop YH ;[11] undo the push from before + rjmp waitForK ;[13] this was not the end of sync, retry +haveTwoBitsK: +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +#define fix x2 +#define data x1 + + push shift ;[12] + push x1 ;[14] + push x2 ;[16] + ldi shift, 0x80 ;[18] prevent bit-unstuffing but init low bits to 0 + ifioset USBIN, USBMINUS ;[19] [01] <--- bit 0 [10.5 + 8 = 18.5] + ori shift, 1<<0 ;[02] + push x3 ;[03] + push cnt ;[05] + push r0 ;[07] + ifioset USBIN, USBMINUS ;[09] <--- bit 1 + ori shift, 1<<1 ;[10] + ser fix ;[11] + ldi cnt, USB_BUFSIZE ;[12] + mov data, shift ;[13] + lsl shift ;[14] + nop2 ;[15] + ifioset USBIN, USBMINUS ;[17] <--- bit 2 + ori data, 3<<2 ;[18] store in bit 2 AND bit 3 + eor shift, data ;[19] do nrzi decoding + andi data, 1<<3 ;[20] + in phase, USBIN ;[21] <- phase + brne jumpToEntryAfterSet ;[22] if USBMINS at bit 3 was 1 + nop ;[23] + rjmp entryAfterClr ;[24] +jumpToEntryAfterSet: + rjmp entryAfterSet ;[24] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +#undef fix +#define fix x1 +#undef data +#define data x2 + +bit7IsSet: + ifrclr phase, USBMINUS ;[62] check phase only if D- changed + lpm ;[63] + in phase, USBIN ;[64] <- phase (one cycle too late) + ori shift, 1 << 7 ;[65] + nop ;[66] +;;;;rjmp bit0AfterSet ; -> [00] == [67] moved block up to save jump +bit0AfterSet: + eor fix, shift ;[00] +#undef fix +#define fix x2 +#undef data +#define data x1 /* we now have result in data, fix is reset to 0xff */ + ifioclr USBIN, USBMINUS ;[01] <--- sample 0 + rjmp bit0IsClr ;[02] + andi shift, ~(7 << 0) ;[03] + breq unstuff0s ;[04] + in phase, USBIN ;[05] <- phase + rjmp bit1AfterSet ;[06] +unstuff0s: + in phase, USBIN ;[06] <- phase (one cycle too late) + andi fix, ~(1 << 0) ;[07] + ifioclr USBIN, USBMINUS ;[00] + ifioset USBIN, USBPLUS ;[01] + rjmp bit0IsClr ;[02] executed if first expr false or second true +se0AndStore: ; executed only if both bits 0 + st y+, x1 ;[15/17] cycles after start of byte + rjmp se0 ;[17/19] + +bit0IsClr: + ifrset phase, USBMINUS ;[04] check phase only if D- changed + lpm ;[05] + in phase, USBIN ;[06] <- phase (one cycle too late) + ori shift, 1 << 0 ;[07] +bit1AfterClr: + andi phase, USBMASK ;[08] + ifioset USBIN, USBMINUS ;[09] <--- sample 1 + rjmp bit1IsSet ;[10] + breq se0AndStore ;[11] if D- was 0 in bits 0 AND 1 and D+ was 0 in between, we have SE0 + andi shift, ~(7 << 1) ;[12] + in phase, USBIN ;[13] <- phase + breq unstuff1c ;[14] + rjmp bit2AfterClr ;[15] +unstuff1c: + andi fix, ~(1 << 1) ;[16] + nop2 ;[08] + nop2 ;[10] +bit1IsSet: + ifrclr phase, USBMINUS ;[12] check phase only if D- changed + lpm ;[13] + in phase, USBIN ;[14] <- phase (one cycle too late) + ori shift, 1 << 1 ;[15] + nop ;[16] +bit2AfterSet: + ifioclr USBIN, USBMINUS ;[17] <--- sample 2 + rjmp bit2IsClr ;[18] + andi shift, ~(7 << 2) ;[19] + breq unstuff2s ;[20] + in phase, USBIN ;[21] <- phase + rjmp bit3AfterSet ;[22] +unstuff2s: + in phase, USBIN ;[22] <- phase (one cycle too late) + andi fix, ~(1 << 2) ;[23] + nop2 ;[16] + nop2 ;[18] +bit2IsClr: + ifrset phase, USBMINUS ;[20] check phase only if D- changed + lpm ;[21] + in phase, USBIN ;[22] <- phase (one cycle too late) + ori shift, 1 << 2 ;[23] +bit3AfterClr: + st y+, data ;[24] +entryAfterClr: + ifioset USBIN, USBMINUS ;[26] <--- sample 3 + rjmp bit3IsSet ;[27] + andi shift, ~(7 << 3) ;[28] + breq unstuff3c ;[29] + in phase, USBIN ;[30] <- phase + rjmp bit4AfterClr ;[31] +unstuff3c: + in phase, USBIN ;[31] <- phase (one cycle too late) + andi fix, ~(1 << 3) ;[32] + nop2 ;[25] + nop2 ;[27] +bit3IsSet: + ifrclr phase, USBMINUS ;[29] check phase only if D- changed + lpm ;[30] + in phase, USBIN ;[31] <- phase (one cycle too late) + ori shift, 1 << 3 ;[32] +bit4AfterSet: + mov data, fix ;[33] undo this move by swapping defines +#undef fix +#define fix x1 +#undef data +#define data x2 + ifioclr USBIN, USBMINUS ;[34] <--- sample 4 + rjmp bit4IsClr ;[35] + andi shift, ~(7 << 4) ;[36] + breq unstuff4s ;[37] + in phase, USBIN ;[38] <- phase + rjmp bit5AfterSet ;[39] +unstuff4s: + in phase, USBIN ;[39] <- phase (one cycle too late) + andi fix, ~(1 << 4) ;[40] + nop2 ;[33] + nop2 ;[35] +bit4IsClr: + ifrset phase, USBMINUS ;[37] check phase only if D- changed + lpm ;[38] + in phase, USBIN ;[39] <- phase (one cycle too late) + ori shift, 1 << 4 ;[40] +bit5AfterClr: + ser data ;[41] + ifioset USBIN, USBMINUS ;[42] <--- sample 5 + rjmp bit5IsSet ;[43] + andi shift, ~(7 << 5) ;[44] + breq unstuff5c ;[45] + in phase, USBIN ;[46] <- phase + rjmp bit6AfterClr ;[47] +unstuff5c: + in phase, USBIN ;[47] <- phase (one cycle too late) + andi fix, ~(1 << 5) ;[48] + nop2 ;[41] + nop2 ;[43] +bit5IsSet: + ifrclr phase, USBMINUS ;[45] check phase only if D- changed + lpm ;[46] + in phase, USBIN ;[47] <- phase (one cycle too late) + ori shift, 1 << 5 ;[48] +bit6AfterSet: + subi cnt, 1 ;[49] + brcs jumpToOverflow ;[50] + ifioclr USBIN, USBMINUS ;[51] <--- sample 6 + rjmp bit6IsClr ;[52] + andi shift, ~(3 << 6) ;[53] + cpi shift, 2 ;[54] + in phase, USBIN ;[55] <- phase + brlt unstuff6s ;[56] + rjmp bit7AfterSet ;[57] + +jumpToOverflow: + rjmp overflow + +unstuff6s: + andi fix, ~(1 << 6) ;[50] + lpm ;[51] +bit6IsClr: + ifrset phase, USBMINUS ;[54] check phase only if D- changed + lpm ;[55] + in phase, USBIN ;[56] <- phase (one cycle too late) + ori shift, 1 << 6 ;[57] + nop ;[58] +bit7AfterClr: + ifioset USBIN, USBMINUS ;[59] <--- sample 7 + rjmp bit7IsSet ;[60] + andi shift, ~(1 << 7) ;[61] + cpi shift, 4 ;[62] + in phase, USBIN ;[63] <- phase + brlt unstuff7c ;[64] + rjmp bit0AfterClr ;[65] -> [00] == [67] +unstuff7c: + andi fix, ~(1 << 7) ;[58] + nop ;[59] + rjmp bit7IsSet ;[60] + +bit7IsClr: + ifrset phase, USBMINUS ;[62] check phase only if D- changed + lpm ;[63] + in phase, USBIN ;[64] <- phase (one cycle too late) + ori shift, 1 << 7 ;[65] + nop ;[66] +;;;;rjmp bit0AfterClr ; -> [00] == [67] moved block up to save jump +bit0AfterClr: + eor fix, shift ;[00] +#undef fix +#define fix x2 +#undef data +#define data x1 /* we now have result in data, fix is reset to 0xff */ + ifioset USBIN, USBMINUS ;[01] <--- sample 0 + rjmp bit0IsSet ;[02] + andi shift, ~(7 << 0) ;[03] + breq unstuff0c ;[04] + in phase, USBIN ;[05] <- phase + rjmp bit1AfterClr ;[06] +unstuff0c: + in phase, USBIN ;[06] <- phase (one cycle too late) + andi fix, ~(1 << 0) ;[07] + ifioclr USBIN, USBMINUS ;[00] + ifioset USBIN, USBPLUS ;[01] + rjmp bit0IsSet ;[02] executed if first expr false or second true + rjmp se0AndStore ;[03] executed only if both bits 0 +bit0IsSet: + ifrclr phase, USBMINUS ;[04] check phase only if D- changed + lpm ;[05] + in phase, USBIN ;[06] <- phase (one cycle too late) + ori shift, 1 << 0 ;[07] +bit1AfterSet: + andi shift, ~(7 << 1) ;[08] compensated by "ori shift, 1<<1" if bit1IsClr + ifioclr USBIN, USBMINUS ;[09] <--- sample 1 + rjmp bit1IsClr ;[10] + breq unstuff1s ;[11] + nop2 ;[12] do not check for SE0 if bit 0 was 1 + in phase, USBIN ;[14] <- phase (one cycle too late) + rjmp bit2AfterSet ;[15] +unstuff1s: + in phase, USBIN ;[13] <- phase + andi fix, ~(1 << 1) ;[14] + lpm ;[07] + nop2 ;[10] +bit1IsClr: + ifrset phase, USBMINUS ;[12] check phase only if D- changed + lpm ;[13] + in phase, USBIN ;[14] <- phase (one cycle too late) + ori shift, 1 << 1 ;[15] + nop ;[16] +bit2AfterClr: + ifioset USBIN, USBMINUS ;[17] <--- sample 2 + rjmp bit2IsSet ;[18] + andi shift, ~(7 << 2) ;[19] + breq unstuff2c ;[20] + in phase, USBIN ;[21] <- phase + rjmp bit3AfterClr ;[22] +unstuff2c: + in phase, USBIN ;[22] <- phase (one cycle too late) + andi fix, ~(1 << 2) ;[23] + nop2 ;[16] + nop2 ;[18] +bit2IsSet: + ifrclr phase, USBMINUS ;[20] check phase only if D- changed + lpm ;[21] + in phase, USBIN ;[22] <- phase (one cycle too late) + ori shift, 1 << 2 ;[23] +bit3AfterSet: + st y+, data ;[24] +entryAfterSet: + ifioclr USBIN, USBMINUS ;[26] <--- sample 3 + rjmp bit3IsClr ;[27] + andi shift, ~(7 << 3) ;[28] + breq unstuff3s ;[29] + in phase, USBIN ;[30] <- phase + rjmp bit4AfterSet ;[31] +unstuff3s: + in phase, USBIN ;[31] <- phase (one cycle too late) + andi fix, ~(1 << 3) ;[32] + nop2 ;[25] + nop2 ;[27] +bit3IsClr: + ifrset phase, USBMINUS ;[29] check phase only if D- changed + lpm ;[30] + in phase, USBIN ;[31] <- phase (one cycle too late) + ori shift, 1 << 3 ;[32] +bit4AfterClr: + mov data, fix ;[33] undo this move by swapping defines +#undef fix +#define fix x1 +#undef data +#define data x2 + ifioset USBIN, USBMINUS ;[34] <--- sample 4 + rjmp bit4IsSet ;[35] + andi shift, ~(7 << 4) ;[36] + breq unstuff4c ;[37] + in phase, USBIN ;[38] <- phase + rjmp bit5AfterClr ;[39] +unstuff4c: + in phase, USBIN ;[39] <- phase (one cycle too late) + andi fix, ~(1 << 4) ;[40] + nop2 ;[33] + nop2 ;[35] +bit4IsSet: + ifrclr phase, USBMINUS ;[37] check phase only if D- changed + lpm ;[38] + in phase, USBIN ;[39] <- phase (one cycle too late) + ori shift, 1 << 4 ;[40] +bit5AfterSet: + ser data ;[41] + ifioclr USBIN, USBMINUS ;[42] <--- sample 5 + rjmp bit5IsClr ;[43] + andi shift, ~(7 << 5) ;[44] + breq unstuff5s ;[45] + in phase, USBIN ;[46] <- phase + rjmp bit6AfterSet ;[47] +unstuff5s: + in phase, USBIN ;[47] <- phase (one cycle too late) + andi fix, ~(1 << 5) ;[48] + nop2 ;[41] + nop2 ;[43] +bit5IsClr: + ifrset phase, USBMINUS ;[45] check phase only if D- changed + lpm ;[46] + in phase, USBIN ;[47] <- phase (one cycle too late) + ori shift, 1 << 5 ;[48] +bit6AfterClr: + subi cnt, 1 ;[49] + brcs overflow ;[50] + ifioset USBIN, USBMINUS ;[51] <--- sample 6 + rjmp bit6IsSet ;[52] + andi shift, ~(3 << 6) ;[53] + cpi shift, 2 ;[54] + in phase, USBIN ;[55] <- phase + brlt unstuff6c ;[56] + rjmp bit7AfterClr ;[57] +unstuff6c: + andi fix, ~(1 << 6) ;[50] + lpm ;[51] +bit6IsSet: + ifrclr phase, USBMINUS ;[54] check phase only if D- changed + lpm ;[55] + in phase, USBIN ;[56] <- phase (one cycle too late) + ori shift, 1 << 6 ;[57] +bit7AfterSet: + ifioclr USBIN, USBMINUS ;[59] <--- sample 7 + rjmp bit7IsClr ;[60] + andi shift, ~(1 << 7) ;[61] + cpi shift, 4 ;[62] + in phase, USBIN ;[63] <- phase + brlt unstuff7s ;[64] + rjmp bit0AfterSet ;[65] -> [00] == [67] +unstuff7s: + andi fix, ~(1 << 7) ;[58] + nop ;[59] + rjmp bit7IsClr ;[60] + +macro POP_STANDARD ; 14 cycles + pop r0 + pop cnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;---------------------------------------------------------------------------- +; Transmitting data +;---------------------------------------------------------------------------- + +txByteLoop: +txBitloop: +stuffN1Delay: ; [03] + ror shift ;[-5] [11] [63] + brcc doExorN1 ;[-4] [64] + subi x3, 1 ;[-3] + brne commonN1 ;[-2] + lsl shift ;[-1] compensate ror after rjmp stuffDelay + nop ;[00] stuffing consists of just waiting 8 cycles + rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear + +sendNakAndReti: + ldi cnt, USBPID_NAK ;[-19] + rjmp sendCntAndReti ;[-18] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov r0, cnt ;[-16] + ldi YL, 0 ;[-15] R0 address is 0 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) or USBOUT = 0x01 +; K = (D+ = 1), (D- = 0) or USBOUT = 0x02 +; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles) + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte +;uses: x1...x3, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x3 = bitstuff cnt] +;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction) +usbSendAndReti: + in x2, USBDDR ;[-10] 10 cycles until SOP + ori x2, USBMASK ;[-9] + sbi USBOUT, USBMINUS ;[-8] prepare idle state; D+ and D- must have been 0 (no pullups) + out USBDDR, x2 ;[-6] <--- acquire bus + in x1, USBOUT ;[-5] port mirror for tx loop + ldi shift, 0x40 ;[-4] sync byte is first byte sent (we enter loop after ror) + ldi x2, USBMASK ;[-3] +doExorN1: + eor x1, x2 ;[-2] [06] [62] + ldi x3, 6 ;[-1] [07] [63] +commonN1: +stuffN2Delay: + out USBOUT, x1 ;[00] [08] [64] <--- set bit + ror shift ;[01] + brcc doExorN2 ;[02] + subi x3, 1 ;[03] + brne commonN2 ;[04] + lsl shift ;[05] compensate ror after rjmp stuffDelay + rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear +doExorN2: + eor x1, x2 ;[04] [12] + ldi x3, 6 ;[05] [13] +commonN2: + nop2 ;[06] [14] + subi cnt, 171 ;[08] [16] trick: (3 * 171) & 0xff = 1 + out USBOUT, x1 ;[09] [17] <--- set bit + brcs txBitloop ;[10] [27] [44] + +stuff6Delay: + ror shift ;[45] [53] + brcc doExor6 ;[46] + subi x3, 1 ;[47] + brne common6 ;[48] + lsl shift ;[49] compensate ror after rjmp stuffDelay + nop ;[50] stuffing consists of just waiting 8 cycles + rjmp stuff6Delay ;[51] after ror, C bit is reliably clear +doExor6: + eor x1, x2 ;[48] [56] + ldi x3, 6 ;[49] +common6: +stuff7Delay: + ror shift ;[50] [58] + out USBOUT, x1 ;[51] <--- set bit + brcc doExor7 ;[52] + subi x3, 1 ;[53] + brne common7 ;[54] + lsl shift ;[55] compensate ror after rjmp stuffDelay + rjmp stuff7Delay ;[56] after ror, C bit is reliably clear +doExor7: + eor x1, x2 ;[54] [62] + ldi x3, 6 ;[55] +common7: + ld shift, y+ ;[56] + nop ;[58] + tst cnt ;[59] + out USBOUT, x1 ;[60] [00]<--- set bit + brne txByteLoop ;[61] [01] +;make SE0: + cbr x1, USBMASK ;[02] prepare SE0 [spec says EOP may be 15 to 18 cycles] + lds x2, usbNewDeviceAddr;[03] + lsl x2 ;[05] we compare with left shifted address + subi YL, 2 + 0 ;[06] Only assign address on data packets, not ACK/NAK in r0 + sbci YH, 0 ;[07] + out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[01] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 0) + echo "$s\n"; + } +} + +function printBit($isAfterSet, $bitNum) +{ + ob_start(); + if($isAfterSet){ +?> + ifioclr USBIN, USBMINUS ;[00] <--- sample + rjmp bit#IsClr ;[01] + andi shift, ~(7 << #) ;[02] + breq unstuff#s ;[03] + in phase, USBIN ;[04] <- phase + rjmp bit@AfterSet ;[05] +unstuff#s: + in phase, USBIN ;[05] <- phase (one cycle too late) + andi fix, ~(1 << #) ;[06] + nop2 ;[-1] + nop2 ;[01] +bit#IsClr: + ifrset phase, USBMINUS ;[03] check phase only if D- changed + lpm ;[04] + in phase, USBIN ;[05] <- phase (one cycle too late) + ori shift, 1 << # ;[06] + + ifioset USBIN, USBMINUS ;[00] <--- sample + rjmp bit#IsSet ;[01] + andi shift, ~(7 << #) ;[02] + breq unstuff#c ;[03] + in phase, USBIN ;[04] <- phase + rjmp bit@AfterClr ;[05] +unstuff#c: + in phase, USBIN ;[05] <- phase (one cycle too late) + andi fix, ~(1 << #) ;[06] + nop2 ;[-1] + nop2 ;[01] +bit#IsSet: + ifrclr phase, USBMINUS ;[03] check phase only if D- changed + lpm ;[04] + in phase, USBIN ;[05] <- phase (one cycle too late) + ori shift, 1 << # ;[06] + +*****************************************************************************/ diff --git a/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm15.inc b/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm15.inc new file mode 100644 index 0000000..401b7f8 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm15.inc @@ -0,0 +1,423 @@ +/* Name: usbdrvasm15.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: contributed by V. Bosch + * Creation Date: 2007-08-06 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm15.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 15 MHz version of the asssembler part of the USB driver. It +requires a 15 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! +*/ + +;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + +;---------------------------------------------------------------------------- +; order of registers pushed: +; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4 +;---------------------------------------------------------------------------- +USB_INTR_VECTOR: + push YL ;2 push only what is necessary to sync with edge ASAP + in YL, SREG ;1 + push YL ;2 +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +; +; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +; sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +;------------------------------------------------------------------------------- +; The following code results in a sampling window of < 1/4 bit +; which meets the spec. +;------------------------------------------------------------------------------- +waitForK: ;- + sbis USBIN, USBMINUS ;1 [00] <-- sample + rjmp foundK ;2 [01] + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +;------------------------------------------------------------------------------ +; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for +; center sampling] +; we have 1 bit time for setup purposes, then sample again. +; Numbers in brackets are cycles from center of first sync (double K) +; bit after the instruction +;------------------------------------------------------------------------------ +foundK: ;- [02] + lds YL, usbInputBufOffset;2 [03+04] tx loop + push YH ;2 [05+06] + clr YH ;1 [07] + subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init] + sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init] + push shift ;2 [10+11] + ser shift ;1 [12] + sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early) + rjmp haveTwoBitsK ;2 [00] [14] + pop shift ;2 [15+16] undo the push from before + pop YH ;2 [17+18] undo the push from before + rjmp waitForK ;2 [19+20] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 20 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: ;- [01] + push x1 ;2 [02+03] + push x2 ;2 [04+05] + push x3 ;2 [06+07] + push bitcnt ;2 [08+09] + in x1, USBIN ;1 [00] [10] <-- sample bit 0 + bst x1, USBMINUS ;1 [01] + bld shift, 0 ;1 [02] + push cnt ;2 [03+04] + ldi cnt, USB_BUFSIZE ;1 [05] + push x4 ;2 [06+07] tx loop + rjmp rxLoop ;2 [08] +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +unstuff0: ;- [07] (branch taken) + andi x3, ~0x01 ;1 [08] + mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit + in x2, USBIN ;1 [00] [10] <-- sample bit 1 again + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 1 + ori shift, 0x01 ;1 [03] 0b00000001 + nop ;1 [04] + rjmp didUnstuff0 ;2 [05] +;----------------------------------------------------- +unstuff1: ;- [05] (branch taken) + mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit + andi x3, ~0x02 ;1 [07] + ori shift, 0x02 ;1 [08] 0b00000010 + nop ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 2 again + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 2 + rjmp didUnstuff1 ;2 [03] +;----------------------------------------------------- +unstuff2: ;- [05] (branch taken) + andi x3, ~0x04 ;1 [06] + ori shift, 0x04 ;1 [07] 0b00000100 + mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit + nop ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample bit 3 + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 3 + rjmp didUnstuff2 ;2 [03] +;----------------------------------------------------- +unstuff3: ;- [00] [10] (branch taken) + in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late + andi x2, USBMASK ;1 [02] + breq se0Hop ;1 [03] SE0 check for stuffed bit 3 + andi x3, ~0x08 ;1 [04] + ori shift, 0x08 ;1 [05] 0b00001000 + rjmp didUnstuff3 ;2 [06] +;---------------------------------------------------------------------------- +; extra jobs done during bit interval: +; +; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs], +; overflow check, jump to the head of rxLoop +; bit 1: SE0 check +; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long] +; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long] +; bit 4: SE0 check, none +; bit 5: SE0 check, none +; bit 6: SE0 check, none +; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others +;---------------------------------------------------------------------------- +rxLoop: ;- [09] + in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed) + andi x2, USBMASK ;1 [01] + brne SkipSe0Hop ;1 [02] +se0Hop: ;- [02] + rjmp se0 ;2 [03] SE0 check for bit 1 +SkipSe0Hop: ;- [03] + ser x3 ;1 [04] + andi shift, 0xf9 ;1 [05] 0b11111001 + breq unstuff0 ;1 [06] +didUnstuff0: ;- [06] + eor x1, x2 ;1 [07] + bst x1, USBMINUS ;1 [08] + bld shift, 1 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed) + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 2 + andi shift, 0xf3 ;1 [03] 0b11110011 + breq unstuff1 ;1 [04] do remaining work for bit 1 +didUnstuff1: ;- [04] + eor x2, x1 ;1 [05] + bst x2, USBMINUS ;1 [06] + bld shift, 2 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed) + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 3 + andi shift, 0xe7 ;1 [03] 0b11100111 + breq unstuff2 ;1 [04] +didUnstuff2: ;- [04] + eor x1, x2 ;1 [05] + bst x1, USBMINUS ;1 [06] + bld shift, 3 ;1 [07] +didUnstuff3: ;- [07] + andi shift, 0xcf ;1 [08] 0b11001111 + breq unstuff3 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 4 + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 4 + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 4 ;1 [05] +didUnstuff4: ;- [05] + andi shift, 0x9f ;1 [06] 0b10011111 + breq unstuff4 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 5 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 5 + eor x1, x2 ;1 [03] + bst x1, USBMINUS ;1 [04] + bld shift, 5 ;1 [05] +didUnstuff5: ;- [05] + andi shift, 0x3f ;1 [06] 0b00111111 + breq unstuff5 ;1 [07] + nop2 ;2 [08+09] + in x1, USBIN ;1 [00] [10] <-- sample bit 6 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 6 + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 6 ;1 [05] +didUnstuff6: ;- [05] + cpi shift, 0x02 ;1 [06] 0b00000010 + brlo unstuff6 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 7 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 7 + eor x1, x2 ;1 [03] + bst x1, USBMINUS ;1 [04] + bld shift, 7 ;1 [05] +didUnstuff7: ;- [05] + cpi shift, 0x04 ;1 [06] 0b00000100 + brlo unstuff7 ;1 [07] + eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others + nop ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 0 + st y+, x3 ;2 [01+02] store data + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 0 ;1 [05] + subi cnt, 1 ;1 [06] + brcs overflow ;1 [07] + rjmp rxLoop ;2 [08] +;----------------------------------------------------- +unstuff4: ;- [08] + andi x3, ~0x10 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 4 + ori shift, 0x10 ;1 [03] + rjmp didUnstuff4 ;2 [04] +;----------------------------------------------------- +unstuff5: ;- [08] + ori shift, 0x20 ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 5 + andi x3, ~0x20 ;1 [03] + rjmp didUnstuff5 ;2 [04] +;----------------------------------------------------- +unstuff6: ;- [08] + andi x3, ~0x40 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 6 + ori shift, 0x40 ;1 [03] + rjmp didUnstuff6 ;2 [04] +;----------------------------------------------------- +unstuff7: ;- [08] + andi x3, ~0x80 ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 7 + ori shift, 0x80 ;1 [03] + rjmp didUnstuff7 ;2 [04] + +macro POP_STANDARD ; 16 cycles + pop x4 + pop cnt + pop bitcnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;--------------------------------------------------------------------------- +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies +;--------------------------------------------------------------------------- +bitstuffN: ;- [04] + eor x1, x4 ;1 [05] + clr x2 ;1 [06] + nop ;1 [07] + rjmp didStuffN ;1 [08] +;--------------------------------------------------------------------------- +bitstuff6: ;- [04] + eor x1, x4 ;1 [05] + clr x2 ;1 [06] + rjmp didStuff6 ;1 [07] +;--------------------------------------------------------------------------- +bitstuff7: ;- [02] + eor x1, x4 ;1 [03] + clr x2 ;1 [06] + nop ;1 [05] + rjmp didStuff7 ;1 [06] +;--------------------------------------------------------------------------- +sendNakAndReti: ;- [-19] + ldi x3, USBPID_NAK ;1 [-18] + rjmp sendX3AndReti ;1 [-17] +;--------------------------------------------------------------------------- +sendAckAndReti: ;- [-17] + ldi cnt, USBPID_ACK ;1 [-16] +sendCntAndReti: ;- [-16] + mov x3, cnt ;1 [-15] +sendX3AndReti: ;- [-15] + ldi YL, 20 ;1 [-14] x3==r20 address is 20 + ldi YH, 0 ;1 [-13] + ldi cnt, 2 ;1 [-12] +; rjmp usbSendAndReti fallthrough +;--------------------------------------------------------------------------- +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +;We need not to match the transfer rate exactly because the spec demands +;only 1.5% precision anyway. +usbSendAndReti: ;- [-13] 13 cycles until SOP + in x2, USBDDR ;1 [-12] + ori x2, USBMASK ;1 [-11] + sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;1 [-08] port mirror for tx loop + out USBDDR, x2 ;1 [-07] <- acquire bus + ; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;1 [-06] exor mask + ldi shift, 0x80 ;1 [-05] sync byte is first byte sent + ldi bitcnt, 6 ;1 [-04] +txBitLoop: ;- [-04] [06] + sbrs shift, 0 ;1 [-03] [07] + eor x1, x4 ;1 [-02] [08] + ror shift ;1 [-01] [09] +didStuffN: ;- [09] + out USBOUT, x1 ;1 [00] [10] <-- out N + ror x2 ;1 [01] + cpi x2, 0xfc ;1 [02] + brcc bitstuffN ;1 [03] + dec bitcnt ;1 [04] + brne txBitLoop ;1 [05] + sbrs shift, 0 ;1 [06] + eor x1, x4 ;1 [07] + ror shift ;1 [08] +didStuff6: ;- [08] + nop ;1 [09] + out USBOUT, x1 ;1 [00] [10] <-- out 6 + ror x2 ;1 [01] + cpi x2, 0xfc ;1 [02] + brcc bitstuff6 ;1 [03] + sbrs shift, 0 ;1 [04] + eor x1, x4 ;1 [05] + ror shift ;1 [06] + ror x2 ;1 [07] +didStuff7: ;- [07] + ldi bitcnt, 6 ;1 [08] + cpi x2, 0xfc ;1 [09] + out USBOUT, x1 ;1 [00] [10] <-- out 7 + brcc bitstuff7 ;1 [01] + ld shift, y+ ;2 [02+03] + dec cnt ;1 [04] + brne txBitLoop ;1 [05] +makeSE0: + cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles] + lds x2, usbNewDeviceAddr;2 [07+08] + lsl x2 ;1 [09] we compare with left shifted address +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle + subi YL, 20 + 2 ;1 [01] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;1 [02] + breq skipAddrAssign ;1 [03] + sts usbDeviceAddr, x2 ;2 [04+05] if not skipped: SE0 is one cycle longer +;---------------------------------------------------------------------------- +;end of usbDeviceAddress transfer +skipAddrAssign: ;- [03/04] + ldi x2, 1< 10.6666666 cycles per bit, 85.333333333 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt + push YL ;[-25] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-23] + push YL ;[-22] + push YH ;[-20] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-15] + rjmp foundK ;[-14] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-12] +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push bitcnt ;[-12] +; [---] ;[-11] + lds YL, usbInputBufOffset;[-10] +; [---] ;[-9] + clr YH ;[-8] + subi YL, lo8(-(usbRxBuf));[-7] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init] + push shift ;[-5] +; [---] ;[-4] + ldi bitcnt, 0x55 ;[-3] [rx loop init] + sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early) + rjmp haveTwoBitsK ;[-1] + pop shift ;[0] undo the push from before + pop bitcnt ;[2] undo the push from before + rjmp waitForK ;[4] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 21 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[1] + push x2 ;[3] + push x3 ;[5] + ldi shift, 0 ;[7] + ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that + push x4 ;[9] == leap + + in x1, USBIN ;[11] <-- sample bit 0 + andi x1, USBMASK ;[12] + bst x1, USBMINUS ;[13] + bld shift, 7 ;[14] + push cnt ;[15] + ldi leap, 0 ;[17] [rx loop init] + ldi cnt, USB_BUFSIZE;[18] [rx loop init] + rjmp rxbit1 ;[19] arrives at [21] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- + +; duration of unstuffing code should be 10.66666667 cycles. We adjust "leap" +; accordingly to approximate this value in the long run. + +unstuff6: + andi x2, USBMASK ;[03] + ori x3, 1<<6 ;[04] will not be shifted any more + andi shift, ~0x80;[05] + mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6 + subi leap, -1 ;[07] total duration = 11 bits -> subtract 1/3 + rjmp didUnstuff6 ;[08] + +unstuff7: + ori x3, 1<<7 ;[09] will not be shifted any more + in x2, USBIN ;[00] [10] re-sample bit 7 + andi x2, USBMASK ;[01] + andi shift, ~0x80;[02] + subi leap, 2 ;[03] total duration = 10 bits -> add 1/3 + rjmp didUnstuff7 ;[04] + +unstuffEven: + ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0 + in x1, USBIN ;[00] [10] + andi shift, ~0x80;[01] + andi x1, USBMASK ;[02] + breq se0 ;[03] + subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3 + nop2 ;[05] + rjmp didUnstuffE ;[06] + +unstuffOdd: + ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1 + in x2, USBIN ;[00] [10] + andi shift, ~0x80;[01] + andi x2, USBMASK ;[02] + breq se0 ;[03] + subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3 + nop2 ;[05] + rjmp didUnstuffO ;[06] + +rxByteLoop: + andi x1, USBMASK ;[03] + eor x2, x1 ;[04] + subi leap, 1 ;[05] + brpl skipLeap ;[06] + subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte + nop ;1 +skipLeap: + subi x2, 1 ;[08] + ror shift ;[09] +didUnstuff6: + cpi shift, 0xfc ;[10] + in x2, USBIN ;[00] [11] <-- sample bit 7 + brcc unstuff6 ;[01] + andi x2, USBMASK ;[02] + eor x1, x2 ;[03] + subi x1, 1 ;[04] + ror shift ;[05] +didUnstuff7: + cpi shift, 0xfc ;[06] + brcc unstuff7 ;[07] + eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others + st y+, x3 ;[09] store data +rxBitLoop: + in x1, USBIN ;[00] [11] <-- sample bit 0/2/4 + andi x1, USBMASK ;[01] + eor x2, x1 ;[02] + andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7 + subi x2, 1 ;[04] + ror shift ;[05] + cpi shift, 0xfc ;[06] + brcc unstuffEven ;[07] +didUnstuffE: + lsr x3 ;[08] + lsr x3 ;[09] +rxbit1: + in x2, USBIN ;[00] [10] <-- sample bit 1/3/5 + andi x2, USBMASK ;[01] + breq se0 ;[02] + eor x1, x2 ;[03] + subi x1, 1 ;[04] + ror shift ;[05] + cpi shift, 0xfc ;[06] + brcc unstuffOdd ;[07] +didUnstuffO: + subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3 + brcs rxBitLoop ;[09] + + subi cnt, 1 ;[10] + in x1, USBIN ;[00] [11] <-- sample bit 6 + brcc rxByteLoop ;[01] + rjmp overflow + +macro POP_STANDARD ; 14 cycles + pop cnt + pop x4 + pop x3 + pop x2 + pop x1 + pop shift + pop bitcnt + endm +macro POP_RETI ; 7 cycles + pop YH + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies + +bitstuffN: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] + nop2 ;[7] + nop ;[9] + out USBOUT, x1 ;[10] <-- out + rjmp didStuffN ;[0] + +bitstuff6: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] Carry is zero due to brcc + rol shift ;[7] compensate for ror shift at branch destination + rjmp didStuff6 ;[8] + +bitstuff7: + ldi x2, 0 ;[2] Carry is zero due to brcc + rjmp didStuff7 ;[3] + + +sendNakAndReti: + ldi x3, USBPID_NAK ;[-18] + rjmp sendX3AndReti ;[-17] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov x3, cnt ;[-16] +sendX3AndReti: + ldi YL, 20 ;[-15] x3==r20 address is 20 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +;We don't match the transfer rate exactly (don't insert leap cycles every third +;byte) because the spec demands only 1.5% precision anyway. +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-7] <- acquire bus +; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-6] exor mask + ldi shift, 0x80 ;[-5] sync byte is first byte sent +txByteLoop: + ldi bitcnt, 0x35 ;[-4] [6] binary 0011 0101 +txBitLoop: + sbrs shift, 0 ;[-3] [7] + eor x1, x4 ;[-2] [8] + out USBOUT, x1 ;[-1] [9] <-- out N + ror shift ;[0] [10] + ror x2 ;[1] +didStuffN: + cpi x2, 0xfc ;[2] + brcc bitstuffN ;[3] + lsr bitcnt ;[4] + brcc txBitLoop ;[5] + brne txBitLoop ;[6] + + sbrs shift, 0 ;[7] + eor x1, x4 ;[8] +didStuff6: + out USBOUT, x1 ;[-1] [9] <-- out 6 + ror shift ;[0] [10] + ror x2 ;[1] + cpi x2, 0xfc ;[2] + brcc bitstuff6 ;[3] + ror shift ;[4] +didStuff7: + ror x2 ;[5] + sbrs x2, 7 ;[6] + eor x1, x4 ;[7] + nop ;[8] + cpi x2, 0xfc ;[9] + out USBOUT, x1 ;[-1][10] <-- out 7 + brcc bitstuff7 ;[0] [11] + ld shift, y+ ;[1] + dec cnt ;[3] + brne txByteLoop ;[4] +;make SE0: + cbr x1, USBMASK ;[5] prepare SE0 [spec says EOP may be 21 to 25 cycles] + lds x2, usbNewDeviceAddr;[6] + lsl x2 ;[8] we compare with left shifted address + subi YL, 20 + 2 ;[9] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[10] + out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[0] + sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< max 52 cycles interrupt disable +;max stack usage: [ret(2), r0, SREG, YL, YH, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 16.5 MHz -> 11 cycles per bit +; 16.3125 MHz < F_CPU < 16.6875 MHz (+/- 1.1%) +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], r0, YH, shift, x1, x2, x3, x4, cnt + push YL ;[-23] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-21] + push YL ;[-20] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-15] + rjmp foundK ;[-14] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-12] +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push r0 ;[-12] +; [---] ;[-11] + push YH ;[-10] +; [---] ;[-9] + lds YL, usbInputBufOffset;[-8] +; [---] ;[-7] + clr YH ;[-6] + subi YL, lo8(-(usbRxBuf));[-5] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-4] [rx loop init] + mov r0, x2 ;[-3] [rx loop init] + sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early) + rjmp haveTwoBitsK ;[-1] + pop YH ;[0] undo the pushes from before + pop r0 ;[2] + rjmp waitForK ;[4] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 22 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: ;[1] + push shift ;[1] + push x1 ;[3] + push x2 ;[5] + push x3 ;[7] + ldi shift, 0xff ;[9] [rx loop init] + ori x3, 0xff ;[10] [rx loop init] == ser x3, clear zero flag + + in x1, USBIN ;[11] <-- sample bit 0 + bst x1, USBMINUS ;[12] + bld shift, 0 ;[13] + push x4 ;[14] == phase +; [---] ;[15] + push cnt ;[16] +; [---] ;[17] + ldi phase, 0 ;[18] [rx loop init] + ldi cnt, USB_BUFSIZE;[19] [rx loop init] + rjmp rxbit1 ;[20] +; [---] ;[21] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +/* +byte oriented operations done during loop: +bit 0: store data +bit 1: SE0 check +bit 2: overflow check +bit 3: catch up +bit 4: rjmp to achieve conditional jump range +bit 5: PLL +bit 6: catch up +bit 7: jump, fixup bitstuff +; 87 [+ 2] cycles +------------------------------------------------------------------ +*/ +continueWithBit5: + in x2, USBIN ;[055] <-- bit 5 + eor r0, x2 ;[056] + or phase, r0 ;[057] + sbrc phase, USBMINUS ;[058] + lpm ;[059] optional nop3; modifies r0 + in phase, USBIN ;[060] <-- phase + eor x1, x2 ;[061] + bst x1, USBMINUS ;[062] + bld shift, 5 ;[063] + andi shift, 0x3f ;[064] + in x1, USBIN ;[065] <-- bit 6 + breq unstuff5 ;[066] *** unstuff escape + eor phase, x1 ;[067] + eor x2, x1 ;[068] + bst x2, USBMINUS ;[069] + bld shift, 6 ;[070] +didUnstuff6: ;[ ] + in r0, USBIN ;[071] <-- phase + cpi shift, 0x02 ;[072] + brlo unstuff6 ;[073] *** unstuff escape +didUnstuff5: ;[ ] + nop2 ;[074] +; [---] ;[075] + in x2, USBIN ;[076] <-- bit 7 + eor x1, x2 ;[077] + bst x1, USBMINUS ;[078] + bld shift, 7 ;[079] +didUnstuff7: ;[ ] + eor r0, x2 ;[080] + or phase, r0 ;[081] + in r0, USBIN ;[082] <-- phase + cpi shift, 0x04 ;[083] + brsh rxLoop ;[084] +; [---] ;[085] +unstuff7: ;[ ] + andi x3, ~0x80 ;[085] + ori shift, 0x80 ;[086] + in x2, USBIN ;[087] <-- sample stuffed bit 7 + nop ;[088] + rjmp didUnstuff7 ;[089] +; [---] ;[090] + ;[080] + +unstuff5: ;[067] + eor phase, x1 ;[068] + andi x3, ~0x20 ;[069] + ori shift, 0x20 ;[070] + in r0, USBIN ;[071] <-- phase + mov x2, x1 ;[072] + nop ;[073] + nop2 ;[074] +; [---] ;[075] + in x1, USBIN ;[076] <-- bit 6 + eor r0, x1 ;[077] + or phase, r0 ;[078] + eor x2, x1 ;[079] + bst x2, USBMINUS ;[080] + bld shift, 6 ;[081] no need to check bitstuffing, we just had one + in r0, USBIN ;[082] <-- phase + rjmp didUnstuff5 ;[083] +; [---] ;[084] + ;[074] + +unstuff6: ;[074] + andi x3, ~0x40 ;[075] + in x1, USBIN ;[076] <-- bit 6 again + ori shift, 0x40 ;[077] + nop2 ;[078] +; [---] ;[079] + rjmp didUnstuff6 ;[080] +; [---] ;[081] + ;[071] + +unstuff0: ;[013] + eor r0, x2 ;[014] + or phase, r0 ;[015] + andi x2, USBMASK ;[016] check for SE0 + in r0, USBIN ;[017] <-- phase + breq didUnstuff0 ;[018] direct jump to se0 would be too long + andi x3, ~0x01 ;[019] + ori shift, 0x01 ;[020] + mov x1, x2 ;[021] mov existing sample + in x2, USBIN ;[022] <-- bit 1 again + rjmp didUnstuff0 ;[023] +; [---] ;[024] + ;[014] + +unstuff1: ;[024] + eor r0, x1 ;[025] + or phase, r0 ;[026] + andi x3, ~0x02 ;[027] + in r0, USBIN ;[028] <-- phase + ori shift, 0x02 ;[029] + mov x2, x1 ;[030] + rjmp didUnstuff1 ;[031] +; [---] ;[032] + ;[022] + +unstuff2: ;[035] + eor r0, x2 ;[036] + or phase, r0 ;[037] + andi x3, ~0x04 ;[038] + in r0, USBIN ;[039] <-- phase + ori shift, 0x04 ;[040] + mov x1, x2 ;[041] + rjmp didUnstuff2 ;[042] +; [---] ;[043] + ;[033] + +unstuff3: ;[043] + in x2, USBIN ;[044] <-- bit 3 again + eor r0, x2 ;[045] + or phase, r0 ;[046] + andi x3, ~0x08 ;[047] + ori shift, 0x08 ;[048] + nop ;[049] + in r0, USBIN ;[050] <-- phase + rjmp didUnstuff3 ;[051] +; [---] ;[052] + ;[042] + +unstuff4: ;[053] + andi x3, ~0x10 ;[054] + in x1, USBIN ;[055] <-- bit 4 again + ori shift, 0x10 ;[056] + rjmp didUnstuff4 ;[057] +; [---] ;[058] + ;[048] + +rxLoop: ;[085] + eor x3, shift ;[086] reconstruct: x3 is 0 at bit locations we changed, 1 at others + in x1, USBIN ;[000] <-- bit 0 + st y+, x3 ;[001] +; [---] ;[002] + eor r0, x1 ;[003] + or phase, r0 ;[004] + eor x2, x1 ;[005] + in r0, USBIN ;[006] <-- phase + ser x3 ;[007] + bst x2, USBMINUS ;[008] + bld shift, 0 ;[009] + andi shift, 0xf9 ;[010] +rxbit1: ;[ ] + in x2, USBIN ;[011] <-- bit 1 + breq unstuff0 ;[012] *** unstuff escape + andi x2, USBMASK ;[013] SE0 check for bit 1 +didUnstuff0: ;[ ] Z only set if we detected SE0 in bitstuff + breq se0 ;[014] + eor r0, x2 ;[015] + or phase, r0 ;[016] + in r0, USBIN ;[017] <-- phase + eor x1, x2 ;[018] + bst x1, USBMINUS ;[019] + bld shift, 1 ;[020] + andi shift, 0xf3 ;[021] +didUnstuff1: ;[ ] + in x1, USBIN ;[022] <-- bit 2 + breq unstuff1 ;[023] *** unstuff escape + eor r0, x1 ;[024] + or phase, r0 ;[025] + subi cnt, 1 ;[026] overflow check + brcs overflow ;[027] + in r0, USBIN ;[028] <-- phase + eor x2, x1 ;[029] + bst x2, USBMINUS ;[030] + bld shift, 2 ;[031] + andi shift, 0xe7 ;[032] +didUnstuff2: ;[ ] + in x2, USBIN ;[033] <-- bit 3 + breq unstuff2 ;[034] *** unstuff escape + eor r0, x2 ;[035] + or phase, r0 ;[036] + eor x1, x2 ;[037] + bst x1, USBMINUS ;[038] + in r0, USBIN ;[039] <-- phase + bld shift, 3 ;[040] + andi shift, 0xcf ;[041] +didUnstuff3: ;[ ] + breq unstuff3 ;[042] *** unstuff escape + nop ;[043] + in x1, USBIN ;[044] <-- bit 4 + eor x2, x1 ;[045] + bst x2, USBMINUS ;[046] + bld shift, 4 ;[047] +didUnstuff4: ;[ ] + eor r0, x1 ;[048] + or phase, r0 ;[049] + in r0, USBIN ;[050] <-- phase + andi shift, 0x9f ;[051] + breq unstuff4 ;[052] *** unstuff escape + rjmp continueWithBit5;[053] +; [---] ;[054] + +macro POP_STANDARD ; 16 cycles + pop cnt + pop x4 + pop x3 + pop x2 + pop x1 + pop shift + pop YH + pop r0 + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies + +bitstuff7: + eor x1, x4 ;[4] + ldi x2, 0 ;[5] + nop2 ;[6] C is zero (brcc) + rjmp didStuff7 ;[8] + +bitstuffN: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] + lpm ;[7] 3 cycle NOP, modifies r0 + out USBOUT, x1 ;[10] <-- out + rjmp didStuffN ;[0] + +#define bitStatus x3 + +sendNakAndReti: + ldi cnt, USBPID_NAK ;[-19] + rjmp sendCntAndReti ;[-18] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov r0, cnt ;[-16] + ldi YL, 0 ;[-15] R0 address is 0 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-7] <- acquire bus +; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-6] exor mask + ldi shift, 0x80 ;[-5] sync byte is first byte sent + ldi bitStatus, 0xff ;[-4] init bit loop counter, works for up to 12 bytes +byteloop: +bitloop: + sbrs shift, 0 ;[8] [-3] + eor x1, x4 ;[9] [-2] + out USBOUT, x1 ;[10] [-1] <-- out + ror shift ;[0] + ror x2 ;[1] +didStuffN: + cpi x2, 0xfc ;[2] + brcc bitstuffN ;[3] + nop ;[4] + subi bitStatus, 37 ;[5] 256 / 7 ~=~ 37 + brcc bitloop ;[6] when we leave the loop, bitStatus has almost the initial value + sbrs shift, 0 ;[7] + eor x1, x4 ;[8] + ror shift ;[9] +didStuff7: + out USBOUT, x1 ;[10] <-- out + ror x2 ;[0] + cpi x2, 0xfc ;[1] + brcc bitstuff7 ;[2] + ld shift, y+ ;[3] + dec cnt ;[5] + brne byteloop ;[6] +;make SE0: + cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles] + lds x2, usbNewDeviceAddr;[8] + lsl x2 ;[10] we compare with left shifted address + out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + subi YL, 2 ;[0] Only assign address on data packets, not ACK/NAK in r0 + sbci YH, 0 ;[1] + breq skipAddrAssign ;[2] + sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 12 cycles per bit +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts +;register use in receive loop to receive the data bytes: +; shift assembles the byte currently being received +; x1 holds the D+ and D- line state +; x2 holds the previous line state +; cnt holds the number of bytes left in the receive buffer +; x3 holds the higher crc byte (see algorithm below) +; x4 is used as temporary register for the crc algorithm +; x5 is used for unstuffing: when unstuffing the last received bit is inverted in shift (to prevent further +; unstuffing calls. In the same time the corresponding bit in x5 is cleared to mark the bit as beening iverted +; zl lower crc value and crc table index +; zh used for crc table accesses + +;-------------------------------------------------------------------------------------------------------------- +; CRC mods: +; table driven crc checker, Z points to table in prog space +; ZL is the lower crc byte, x3 is the higher crc byte +; x4 is used as temp register to store different results +; the initialization of the crc register is not 0xFFFF but 0xFE54. This is because during the receipt of the +; first data byte an virtual zero data byte is added to the crc register, this results in the correct initial +; value of 0xFFFF at beginning of the second data byte before the first data byte is added to the crc. +; The magic number 0xFE54 results form the crc table: At tabH[0x54] = 0xFF = crcH (required) and +; tabL[0x54] = 0x01 -> crcL = 0x01 xor 0xFE = 0xFF +; bitcnt is renamed to x5 and is used for unstuffing purposes, the unstuffing works like in the 12MHz version +;-------------------------------------------------------------------------------------------------------------- +; CRC algorithm: +; The crc register is formed by x3 (higher byte) and ZL (lower byte). The algorithm uses a 'reversed' form +; i.e. that it takes the least significant bit first and shifts to the right. So in fact the highest order +; bit seen from the polynomial devision point of view is the lsb of ZL. (If this sounds strange to you i +; propose a research on CRC :-) ) +; Each data byte received is xored to ZL, the lower crc byte. This byte now builds the crc +; table index. Next the new high byte is loaded from the table and stored in x4 until we have space in x3 +; (its destination). +; Afterwards the lower table is loaded from the table and stored in ZL (the old index is overwritten as +; we don't need it anymore. In fact this is a right shift by 8 bits.) Now the old crc high value is xored +; to ZL, this is the second shift of the old crc value. Now x4 (the temp reg) is moved to x3 and the crc +; calculation is done. +; Prior to the first byte the two CRC register have to be initialized to 0xFFFF (as defined in usb spec) +; however the crc engine also runs during the receipt of the first byte, therefore x3 and zl are initialized +; to a magic number which results in a crc value of 0xFFFF after the first complete byte. +; +; This algorithm is split into the extra cycles of the different bits: +; bit7: XOR the received byte to ZL +; bit5: load the new high byte to x4 +; bit6: load the lower xor byte from the table, xor zl and x3, store result in zl (=the new crc low value) +; move x4 (the new high byte) to x3, the crc value is ready +; + + +macro POP_STANDARD ; 18 cycles + pop ZH + pop ZL + pop cnt + pop x5 + pop x3 + pop x2 + pop x1 + pop shift + pop x4 + endm +macro POP_RETI ; 7 cycles + pop YH + pop YL + out SREG, YL + pop YL + endm + +macro CRC_CLEANUP_AND_CHECK + ; the last byte has already been xored with the lower crc byte, we have to do the table lookup and xor + ; x3 is the higher crc byte, zl the lower one + ldi ZH, hi8(usbCrcTableHigh);[+1] get the new high byte from the table + lpm x2, Z ;[+2][+3][+4] + ldi ZH, hi8(usbCrcTableLow);[+5] get the new low xor byte from the table + lpm ZL, Z ;[+6][+7][+8] + eor ZL, x3 ;[+7] xor the old high byte with the value from the table, x2:ZL now holds the crc value + cpi ZL, 0x01 ;[+8] if the crc is ok we have a fixed remainder value of 0xb001 in x2:ZL (see usb spec) + brne ignorePacket ;[+9] detected a crc fault -> paket is ignored and retransmitted by the host + cpi x2, 0xb0 ;[+10] + brne ignorePacket ;[+11] detected a crc fault -> paket is ignored and retransmitted by the host + endm + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG, YH, [sofError], x4, shift, x1, x2, x3, x5, cnt, ZL, ZH + push YL ;[-28] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-26] + push YL ;[-25] + push YH ;[-23] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-17] + rjmp foundK ;[-16] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-15] +;{3, 5} after falling D- edge, average delay: 4 cycles +;bit0 should be at 30 (2.5 bits) for center sampling. Currently at 4 so 26 cylces till bit 0 sample +;use 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push x4 ;[-14] +; [---] ;[-13] + lds YL, usbInputBufOffset;[-12] used to toggle the two usb receive buffers +; [---] ;[-11] + clr YH ;[-10] + subi YL, lo8(-(usbRxBuf));[-9] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-8] [rx loop init] + push shift ;[-7] +; [---] ;[-6] + ldi shift, 0x80 ;[-5] the last bit is the end of byte marker for the pid receiver loop + clc ;[-4] the carry has to be clear for receipt of pid bit 0 + sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) + rjmp haveTwoBitsK ;[-2] + pop shift ;[-1] undo the push from before + pop x4 ;[1] + rjmp waitForK ;[3] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 24 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[0] + push x2 ;[2] + push x3 ;[4] crc high byte + ldi x2, 1< jump back and store the byte + ori shift, 0x01 ;[11] invert the last received bit to prevent furhter unstuffing + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + andi x5, 0xFE ;[1] mark this bit as inverted (will be corrected before storing shift) + eor x1, x2 ;[2] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[3] mask the interesting bits + breq stuffErr ;[4] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[5] the next bit expects the last state to be in x1 + rjmp didunstuff0 ;[6] + ;[7] jump delay of rjmp didunstuffX + +unstuff1: ;[11] this is the jump delay of breq unstuffX + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + ori shift, 0x02 ;[1] invert the last received bit to prevent furhter unstuffing + andi x5, 0xFD ;[2] mark this bit as inverted (will be corrected before storing shift) + eor x2, x1 ;[3] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[4] mask the interesting bits + breq stuffErr ;[5] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[6] the next bit expects the last state to be in x2 + nop2 ;[7] + ;[8] + rjmp didunstuff1 ;[9] + ;[10] jump delay of rjmp didunstuffX + +unstuff2: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x04 ;[10] invert the last received bit to prevent furhter unstuffing + andi x5, 0xFB ;[11] mark this bit as inverted (will be corrected before storing shift) + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[4] the next bit expects the last state to be in x1 + nop2 ;[5] + ;[6] + rjmp didunstuff2 ;[7] + ;[8] jump delay of rjmp didunstuffX + +unstuff3: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x08 ;[10] invert the last received bit to prevent furhter unstuffing + andi x5, 0xF7 ;[11] mark this bit as inverted (will be corrected before storing shift) + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[4] the next bit expects the last state to be in x2 + nop2 ;[5] + ;[6] + rjmp didunstuff3 ;[7] + ;[8] jump delay of rjmp didunstuffX + + + +; the include has to be here due to branch distance restirctions +#define __USE_CRC__ +#include "asmcommon.inc" + + + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies +; 7.5 bit times is 90 cycles. ...there is plenty of time + + +sendNakAndReti: + ldi x3, USBPID_NAK ;[-18] + rjmp sendX3AndReti ;[-17] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov x3, cnt ;[-16] +sendX3AndReti: + ldi YL, 20 ;[-15] x3==r20 address is 20 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent + +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-6] <- acquire bus + ldi x2, 0 ;[-6] init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-5] exor mask + ldi shift, 0x80 ;[-4] sync byte is first byte sent +txByteLoop: + ldi bitcnt, 0x40 ;[-3]=[9] binary 01000000 +txBitLoop: ; the loop sends the first 7 bits of the byte + sbrs shift, 0 ;[-2]=[10] if we have to send a 1 don't change the line state + eor x1, x4 ;[-1]=[11] + out USBOUT, x1 ;[0] + ror shift ;[1] + ror x2 ;[2] transfers the last sent bit to the stuffing history +didStuffN: + nop ;[3] + nop ;[4] + cpi x2, 0xfc ;[5] if we sent six consecutive ones + brcc bitstuffN ;[6] + lsr bitcnt ;[7] + brne txBitLoop ;[8] restart the loop while the 1 is still in the bitcount + +; transmit bit 7 + sbrs shift, 0 ;[9] + eor x1, x4 ;[10] +didStuff7: + ror shift ;[11] + out USBOUT, x1 ;[0] transfer bit 7 to the pins + ror x2 ;[1] move the bit into the stuffing history + cpi x2, 0xfc ;[2] + brcc bitstuff7 ;[3] + ld shift, y+ ;[4] get next byte to transmit + dec cnt ;[5] decrement byte counter + brne txByteLoop ;[7] if we have more bytes start next one + ;[8] branch delay + +;make SE0: + cbr x1, USBMASK ;[8] prepare SE0 [spec says EOP may be 25 to 30 cycles] + lds x2, usbNewDeviceAddr;[9] + lsl x2 ;[11] we compare with left shifted address + out USBOUT, x1 ;[0] <-- out SE0 -- from now 2 bits = 24 cycles until bus idle + subi YL, 20 + 2 ;[1] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[2] +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[3] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< +int main (int argc, char **argv) +{ + int i, j; + for (i=0; i<512; i++){ + unsigned short crc = i & 0xff; + for(j=0; j<8; j++) crc = (crc >> 1) ^ ((crc & 1) ? 0xa001 : 0); + if((i & 7) == 0) printf("\n.byte "); + printf("0x%02x, ", (i > 0xff ? (crc >> 8) : crc) & 0xff); + if(i == 255) printf("\n"); + } + return 0; +} + +// Use the following algorithm to compute CRC values: +ushort computeCrc(uchar *msg, uchar msgLen) +{ + uchar i; + ushort crc = 0xffff; + for(i = 0; i < msgLen; i++) + crc = usbCrcTable16[lo8(crc) ^ msg[i]] ^ hi8(crc); + return crc; +} +*/ + +.balign 256 +usbCrcTableLow: +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 + +; .balign 256 +usbCrcTableHigh: +.byte 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2 +.byte 0xC6, 0x06, 0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04 +.byte 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E +.byte 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8 +.byte 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A +.byte 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC +.byte 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6 +.byte 0xD2, 0x12, 0x13, 0xD3, 0x11, 0xD1, 0xD0, 0x10 +.byte 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32 +.byte 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4 +.byte 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE +.byte 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38 +.byte 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA +.byte 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C +.byte 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26 +.byte 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0 +.byte 0xA0, 0x60, 0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62 +.byte 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4 +.byte 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE +.byte 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68 +.byte 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA +.byte 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C +.byte 0xB4, 0x74, 0x75, 0xB5, 0x77, 0xB7, 0xB6, 0x76 +.byte 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0 +.byte 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92 +.byte 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54 +.byte 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E +.byte 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98 +.byte 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A +.byte 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C +.byte 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86 +.byte 0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 0x40 + diff --git a/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm20.inc b/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm20.inc new file mode 100644 index 0000000..303abaf --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiMouse/usbdrvasm20.inc @@ -0,0 +1,360 @@ +/* Name: usbdrvasm20.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Jeroen Benschop + * Based on usbdrvasm16.inc from Christian Starkjohann + * Creation Date: 2008-03-05 + * Tabsize: 4 + * Copyright: (c) 2008 by Jeroen Benschop and OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm20.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 20 MHz version of the asssembler part of the USB driver. It +requires a 20 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! +*/ + +#define leap2 x3 +#ifdef __IAR_SYSTEMS_ASM__ +#define nextInst $+2 +#else +#define nextInst .+0 +#endif + +;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 20 MHz -> 13.333333 cycles per bit, 106.666667 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts +;register use in receive loop: +; shift assembles the byte currently being received +; x1 holds the D+ and D- line state +; x2 holds the previous line state +; x4 (leap) is used to add a leap cycle once every three bytes received +; X3 (leap2) is used to add a leap cycle once every three stuff bits received +; bitcnt is used to determine when a stuff bit is due +; cnt holds the number of bytes left in the receive buffer + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt + push YL ;[-28] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-26] + push YL ;[-25] + push YH ;[-23] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-19] + rjmp foundK ;[-18] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-16] +;{3, 5} after falling D- edge, average delay: 4 cycles +;bit0 should be at 34 for center sampling. Currently at 4 so 30 cylces till bit 0 sample +;use 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push bitcnt ;[-16] +; [---] ;[-15] + lds YL, usbInputBufOffset;[-14] +; [---] ;[-13] + clr YH ;[-12] + subi YL, lo8(-(usbRxBuf));[-11] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-10] [rx loop init] + push shift ;[-9] +; [---] ;[-8] + ldi shift,0x40 ;[-7] set msb to "1" so processing bit7 can be detected + nop2 ;[-6] +; [---] ;[-5] + ldi bitcnt, 5 ;[-4] [rx loop init] + sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) + rjmp haveTwoBitsK ;[-2] + pop shift ;[-1] undo the push from before + pop bitcnt ;[1] + rjmp waitForK ;[3] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 27 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[0] + push x2 ;[2] + push x3 ;[4] (leap2) + ldi leap2, 0x55 ;[6] add leap cycle on 2nd,5th,8th,... stuff bit + push x4 ;[7] == leap + ldi leap, 0x55 ;[9] skip leap cycle on 2nd,5th,8th,... byte received + push cnt ;[10] + ldi cnt, USB_BUFSIZE ;[12] [rx loop init] + ldi x2, 1< +#ifndef __IAR_SYSTEMS_ASM__ +# include +#endif + +#define __attribute__(arg) /* not supported on IAR */ + +#ifdef __IAR_SYSTEMS_ASM__ +# define __ASSEMBLER__ /* IAR does not define standard macro for asm */ +#endif + +#ifdef __HAS_ELPM__ +# define PROGMEM __farflash +#else +# define PROGMEM __flash +#endif + +#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr)) + +/* The following definitions are not needed by the driver, but may be of some + * help if you port a gcc based project to IAR. + */ +#define cli() __disable_interrupt() +#define sei() __enable_interrupt() +#define wdt_reset() __watchdog_reset() +#define _BV(x) (1 << (x)) + +/* assembler compatibility macros */ +#define nop2 rjmp $+2 /* jump to next instruction */ +#define XL r26 +#define XH r27 +#define YL r28 +#define YH r29 +#define ZL r30 +#define ZH r31 +#define lo8(x) LOW(x) +#define hi8(x) (((x)>>8) & 0xff) /* not HIGH to allow XLINK to make a proper range check */ + +/* Depending on the device you use, you may get problems with the way usbdrv.h + * handles the differences between devices. Since IAR does not use #defines + * for MCU registers, we can't check for the existence of a particular + * register with an #ifdef. If the autodetection mechanism fails, include + * definitions for the required USB_INTR_* macros in your usbconfig.h. See + * usbconfig-prototype.h and usbdrv.h for details. + */ + +/* ------------------------------------------------------------------------- */ +#elif __CODEVISIONAVR__ /* check for CodeVision AVR */ +/* ------------------------------------------------------------------------- */ +/* This port is not working (yet) */ + +/* #define F_CPU _MCU_CLOCK_FREQUENCY_ seems to be defined automatically */ + +#include +#include + +#define __attribute__(arg) /* not supported on IAR */ + +#define PROGMEM __flash +#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr)) + +#ifndef __ASSEMBLER__ +static inline void cli(void) +{ + #asm("cli"); +} +static inline void sei(void) +{ + #asm("sei"); +} +#endif +#define _delay_ms(t) delay_ms(t) +#define _BV(x) (1 << (x)) +#define USB_CFG_USE_SWITCH_STATEMENT 1 /* macro for if() cascase fails for unknown reason */ + +#define macro .macro +#define endm .endmacro +#define nop2 rjmp .+0 /* jump to next instruction */ + +/* ------------------------------------------------------------------------- */ +#else /* default development environment is avr-gcc/avr-libc */ +/* ------------------------------------------------------------------------- */ + +#include +#ifdef __ASSEMBLER__ +# define _VECTOR(N) __vector_ ## N /* io.h does not define this for asm */ +#else +# include +#endif + +#define USB_READ_FLASH(addr) pgm_read_byte(addr) + +#define macro .macro +#define endm .endm +#define nop2 rjmp .+0 /* jump to next instruction */ + +#endif /* development environment */ + +/* for conveniecne, ensure that PRG_RDB exists */ +#ifndef PRG_RDB +# define PRG_RDB(addr) USB_READ_FLASH(addr) +#endif +#endif /* __usbportability_h_INCLUDED__ */ diff --git a/hardware/digistump/avr/libraries/DigiUSB/ArduinoNotes.txt b/hardware/digistump/avr/libraries/DigiUSB/ArduinoNotes.txt new file mode 100644 index 0000000..b1461d5 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/ArduinoNotes.txt @@ -0,0 +1,34 @@ +Notes On Integrating AVRUSB with Arduino +======================================== + +* Note the license(s) under which AVRUSB is distributed. + +* See also: http://code.rancidbacon.com/ProjectLogArduinoUSB + +* Note: The pins we use on the PCB (not protoboard) hardware shield are: + + INT0 == PD2 == IC Pin 4 == Arduino Digital Pin 2 == D+ + + ---- == PD4 == -------- == Arduino Digital Pin 4 == D- + + ---- == PD5 == -------- == Arduino Digital Pin 5 == pull-up + + (DONE: Change to not use PD3 so INT1 is left free?) + +* In order to compile a valid 'usbconfig.h' file must exit. The content of this + file will vary depending on whether the device is a generic USB device, + generic HID device or specific class of HID device for example. + + The file 'usbconfig-prototype.h' can be used as a starting point, however + it might be easier to use the 'usbconfig.h' from one of the example projects. + + TODO: Specify the settings that need to be changed to match the shield + design we use. + +* (NOTE: Initial 'usbconfig.h' used will be based on the file from + 'HIDKeys.2007-03-29'.) (Note: Have now upgraded to V-USB 2009-08-22.) + +* At present the IDE won't compile our library so it needs to be pre-compiled + with: + + avr-g++ -Wall -Os -I. -DF_CPU=16000000 -mmcu=atmega168 -c usbdrvasm.S -c usbdrv.c diff --git a/hardware/digistump/avr/libraries/DigiUSB/Changelog.txt b/hardware/digistump/avr/libraries/DigiUSB/Changelog.txt new file mode 100644 index 0000000..655a9d4 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/Changelog.txt @@ -0,0 +1,296 @@ +This file documents changes in the firmware-only USB driver for atmel's AVR +microcontrollers. New entries are always appended to the end of the file. +Scroll down to the bottom to see the most recent changes. + +2005-04-01: + - Implemented endpoint 1 as interrupt-in endpoint. + - Moved all configuration options to usbconfig.h which is not part of the + driver. + - Changed interface for usbVendorSetup(). + - Fixed compatibility with ATMega8 device. + - Various minor optimizations. + +2005-04-11: + - Changed interface to application: Use usbFunctionSetup(), usbFunctionRead() + and usbFunctionWrite() now. Added configuration options to choose which + of these functions to compile in. + - Assembler module delivers receive data non-inverted now. + - Made register and bit names compatible with more AVR devices. + +2005-05-03: + - Allow address of usbRxBuf on any memory page as long as the buffer does + not cross 256 byte page boundaries. + - Better device compatibility: works with Mega88 now. + - Code optimization in debugging module. + - Documentation updates. + +2006-01-02: + - Added (free) default Vendor- and Product-IDs bought from voti.nl. + - Added USBID-License.txt file which defines the rules for using the free + shared VID/PID pair. + - Added Readme.txt to the usbdrv directory which clarifies administrative + issues. + +2006-01-25: + - Added "configured state" to become more standards compliant. + - Added "HALT" state for interrupt endpoint. + - Driver passes the "USB Command Verifier" test from usb.org now. + - Made "serial number" a configuration option. + - Minor optimizations, we now recommend compiler option "-Os" for best + results. + - Added a version number to usbdrv.h + +2006-02-03: + - New configuration variable USB_BUFFER_SECTION for the memory section where + the USB rx buffer will go. This defaults to ".bss" if not defined. Since + this buffer MUST NOT cross 256 byte pages (not even touch a page at the + end), the user may want to pass a linker option similar to + "-Wl,--section-start=.mybuffer=0x800060". + - Provide structure for usbRequest_t. + - New defines for USB constants. + - Prepared for HID implementations. + - Increased data size limit for interrupt transfers to 8 bytes. + - New macro usbInterruptIsReady() to query interrupt buffer state. + +2006-02-18: + - Ensure that the data token which is sent as an ack to an OUT transfer is + always zero sized. This fixes a bug where the host reports an error after + sending an out transfer to the device, although all data arrived at the + device. + - Updated docs in usbdrv.h to reflect changed API in usbFunctionWrite(). + +* Release 2006-02-20 + + - Give a compiler warning when compiling with debugging turned on. + - Added Oleg Semyonov's changes for IAR-cc compatibility. + - Added new (optional) functions usbDeviceConnect() and usbDeviceDisconnect() + (also thanks to Oleg!). + - Rearranged tests in usbPoll() to save a couple of instructions in the most + likely case that no actions are pending. + - We need a delay between the SET ADDRESS request until the new address + becomes active. This delay was handled in usbPoll() until now. Since the + spec says that the delay must not exceed 2ms, previous versions required + aggressive polling during the enumeration phase. We have now moved the + handling of the delay into the interrupt routine. + - We must not reply with NAK to a SETUP transaction. We can only achieve this + by making sure that the rx buffer is empty when SETUP tokens are expected. + We therefore don't pass zero sized data packets from the status phase of + a transfer to usbPoll(). This change MAY cause troubles if you rely on + receiving a less than 8 bytes long packet in usbFunctionWrite() to + identify the end of a transfer. usbFunctionWrite() will NEVER be called + with a zero length. + +* Release 2006-03-14 + + - Improved IAR C support: tiny memory model, more devices + - Added template usbconfig.h file under the name usbconfig-prototype.h + +* Release 2006-03-26 + + - Added provision for one more interrupt-in endpoint (endpoint 3). + - Added provision for one interrupt-out endpoint (endpoint 1). + - Added flowcontrol macros for USB. + - Added provision for custom configuration descriptor. + - Allow ANY two port bits for D+ and D-. + - Merged (optional) receive endpoint number into global usbRxToken variable. + - Use USB_CFG_IOPORTNAME instead of USB_CFG_IOPORT. We now construct the + variable name from the single port letter instead of computing the address + of related ports from the output-port address. + +* Release 2006-06-26 + + - Updated documentation in usbdrv.h and usbconfig-prototype.h to reflect the + new features. + - Removed "#warning" directives because IAR does not understand them. Use + unused static variables instead to generate a warning. + - Do not include when compiling with IAR. + - Introduced USB_CFG_DESCR_PROPS_* in usbconfig.h to configure how each + USB descriptor should be handled. It is now possible to provide descriptor + data in Flash, RAM or dynamically at runtime. + - STALL is now a status in usbTxLen* instead of a message. We can now conform + to the spec and leave the stall status pending until it is cleared. + - Made usbTxPacketCnt1 and usbTxPacketCnt3 public. This allows the + application code to reset data toggling on interrupt pipes. + +* Release 2006-07-18 + + - Added an #if !defined __ASSEMBLER__ to the warning in usbdrv.h. This fixes + an assembler error. + - usbDeviceDisconnect() takes pull-up resistor to high impedance now. + +* Release 2007-02-01 + + - Merged in some code size improvements from usbtiny (thanks to Dick + Streefland for these optimizations!) + - Special alignment requirement for usbRxBuf not required any more. Thanks + again to Dick Streefland for this hint! + - Reverted to "#warning" instead of unused static variables -- new versions + of IAR CC should handle this directive. + - Changed Open Source license to GNU GPL v2 in order to make linking against + other free libraries easier. We no longer require publication of the + circuit diagrams, but we STRONGLY encourage it. If you improve the driver + itself, PLEASE grant us a royalty free license to your changes for our + commercial license. + +* Release 2007-03-29 + + - New configuration option "USB_PUBLIC" in usbconfig.h. + - Set USB version number to 1.10 instead of 1.01. + - Code used USB_CFG_DESCR_PROPS_STRING_DEVICE and + USB_CFG_DESCR_PROPS_STRING_PRODUCT inconsistently. Changed all occurrences + to USB_CFG_DESCR_PROPS_STRING_PRODUCT. + - New assembler module for 16.5 MHz RC oscillator clock with PLL in receiver + code. + - New assembler module for 16 MHz crystal. + - usbdrvasm.S contains common code only, clock-specific parts have been moved + to usbdrvasm12.S, usbdrvasm16.S and usbdrvasm165.S respectively. + +* Release 2007-06-25 + + - 16 MHz module: Do SE0 check in stuffed bits as well. + +* Release 2007-07-07 + + - Define hi8(x) for IAR compiler to limit result to 8 bits. This is necessary + for negative values. + - Added 15 MHz module contributed by V. Bosch. + - Interrupt vector name can now be configured. This is useful if somebody + wants to use a different hardware interrupt than INT0. + +* Release 2007-08-07 + + - Moved handleIn3 routine in usbdrvasm16.S so that relative jump range is + not exceeded. + - More config options: USB_RX_USER_HOOK(), USB_INITIAL_DATATOKEN, + USB_COUNT_SOF + - USB_INTR_PENDING can now be a memory address, not just I/O + +* Release 2007-09-19 + + - Split out common parts of assembler modules into separate include file + - Made endpoint numbers configurable so that given interface definitions + can be matched. See USB_CFG_EP3_NUMBER in usbconfig-prototype.h. + - Store endpoint number for interrupt/bulk-out so that usbFunctionWriteOut() + can handle any number of endpoints. + - Define usbDeviceConnect() and usbDeviceDisconnect() even if no + USB_CFG_PULLUP_IOPORTNAME is defined. Directly set D+ and D- to 0 in this + case. + +* Release 2007-12-01 + + - Optimize usbDeviceConnect() and usbDeviceDisconnect() for less code size + when USB_CFG_PULLUP_IOPORTNAME is not defined. + +* Release 2007-12-13 + + - Renamed all include-only assembler modules from *.S to *.inc so that + people don't add them to their project sources. + - Distribute leap bits in tx loop more evenly for 16 MHz module. + - Use "macro" and "endm" instead of ".macro" and ".endm" for IAR + - Avoid compiler warnings for constant expr range by casting some values in + USB descriptors. + +* Release 2008-01-21 + + - Fixed bug in 15 and 16 MHz module where the new address set with + SET_ADDRESS was already accepted at the next NAK or ACK we send, not at + the next data packet we send. This caused problems when the host polled + too fast. Thanks to Alexander Neumann for his help and patience debugging + this issue! + +* Release 2008-02-05 + + - Fixed bug in 16.5 MHz module where a register was used in the interrupt + handler before it was pushed. This bug was introduced with version + 2007-09-19 when common parts were moved to a separate file. + - Optimized CRC routine (thanks to Reimar Doeffinger). + +* Release 2008-02-16 + + - Removed outdated IAR compatibility stuff (code sections). + - Added hook macros for USB_RESET_HOOK() and USB_SET_ADDRESS_HOOK(). + - Added optional routine usbMeasureFrameLength() for calibration of the + internal RC oscillator. + +* Release 2008-02-28 + + - USB_INITIAL_DATATOKEN defaults to USBPID_DATA1 now, which means that we + start with sending USBPID_DATA0. + - Changed defaults in usbconfig-prototype.h + - Added free USB VID/PID pair for MIDI class devices + - Restructured AVR-USB as separate package, not part of PowerSwitch any more. + +* Release 2008-04-18 + + - Restructured usbdrv.c so that it is easier to read and understand. + - Better code optimization with gcc 4. + - If a second interrupt in endpoint is enabled, also add it to config + descriptor. + - Added config option for long transfers (above 254 bytes), see + USB_CFG_LONG_TRANSFERS in usbconfig.h. + - Added 20 MHz module contributed by Jeroen Benschop. + +* Release 2008-05-13 + + - Fixed bug in libs-host/hiddata.c function usbhidGetReport(): length + was not incremented, pointer to length was incremented instead. + - Added code to command line tool(s) which claims an interface. This code + is disabled by default, but may be necessary on newer Linux kernels. + - Added usbconfig.h option "USB_CFG_CHECK_DATA_TOGGLING". + - New header "usbportability.h" prepares ports to other development + environments. + - Long transfers (above 254 bytes) did not work when usbFunctionRead() was + used to supply the data. Fixed this bug. [Thanks to Alexander Neumann!] + - In hiddata.c (example code for sending/receiving data over HID), use + USB_RECIP_DEVICE instead of USB_RECIP_INTERFACE for control transfers so + that we need not claim the interface. + - in usbPoll() loop 20 times polling for RESET state instead of 10 times. + This accounts for the higher clock rates we now support. + - Added a module for 12.8 MHz RC oscillator with PLL in receiver loop. + - Added hook to SOF code so that oscillator can be tuned to USB frame clock. + - Added timeout to waitForJ loop. Helps preventing unexpected hangs. + - Added example code for oscillator tuning to libs-device (thanks to + Henrik Haftmann for the idea to this routine). + - Implemented option USB_CFG_SUPPRESS_INTR_CODE. + +* Release 2008-10-22 + + - Fixed libs-device/osctune.h: OSCCAL is memory address on ATMega88 and + similar, not offset of 0x20 needs to be added. + - Allow distribution under GPLv3 for those who have to link against other + code distributed under GPLv3. + +* Release 2008-11-26 + + - Removed libusb-win32 dependency for hid-data example in Makefile.windows. + It was never required and confused many people. + - Added extern uchar usbRxToken to usbdrv.h. + - Integrated a module with CRC checks at 18 MHz by Lukas Schrittwieser. + +* Release 2009-03-23 + + - Hid-mouse example used settings from hid-data example, fixed that. + - Renamed project to V-USB due to a trademark issue with Atmel(r). + - Changed CommercialLicense.txt and USBID-License.txt to make the + background of USB ID registration clearer. + +* Release 2009-04-15 + + - Changed CommercialLicense.txt to reflect the new range of PIDs from + Jason Kotzin. + - Removed USBID-License.txt in favor of USB-IDs-for-free.txt and + USB-ID-FAQ.txt + - Fixed a bug in the 12.8 MHz module: End Of Packet decection was made in + the center between bit 0 and 1 of each byte. This is where the data lines + are expected to change and the sampled data may therefore be nonsense. + We therefore check EOP ONLY if bits 0 AND 1 have both been read as 0 on D-. + - Fixed a bitstuffing problem in the 16 MHz module: If bit 6 was stuffed, + the unstuffing code in the receiver routine was 1 cycle too long. If + multiple bytes had the unstuffing in bit 6, the error summed up until the + receiver was out of sync. + - Included option for faster CRC routine. + Thanks to Slawomir Fras (BoskiDialer) for this code! + - Updated bits in Configuration Descriptor's bmAttributes according to + USB 1.1 (in particular bit 7, it is a must-be-set bit now). + +* Release 2009-08-22 diff --git a/hardware/digistump/avr/libraries/DigiUSB/CommercialLicense.txt b/hardware/digistump/avr/libraries/DigiUSB/CommercialLicense.txt new file mode 100644 index 0000000..11d07d9 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/CommercialLicense.txt @@ -0,0 +1,166 @@ +V-USB Driver Software License Agreement +Version 2009-08-03 + +THIS LICENSE AGREEMENT GRANTS YOU CERTAIN RIGHTS IN A SOFTWARE. YOU CAN +ENTER INTO THIS AGREEMENT AND ACQUIRE THE RIGHTS OUTLINED BELOW BY PAYING +THE AMOUNT ACCORDING TO SECTION 4 ("PAYMENT") TO OBJECTIVE DEVELOPMENT. + + +1 DEFINITIONS + +1.1 "OBJECTIVE DEVELOPMENT" shall mean OBJECTIVE DEVELOPMENT Software GmbH, +Grosse Schiffgasse 1A/7, 1020 Wien, AUSTRIA. + +1.2 "You" shall mean the Licensee. + +1.3 "V-USB" shall mean all files included in the package distributed under +the name "vusb" by OBJECTIVE DEVELOPMENT (http://www.obdev.at/vusb/) +unless otherwise noted. This includes the firmware-only USB device +implementation for Atmel AVR microcontrollers, some simple device examples +and host side software examples and libraries. + + +2 LICENSE GRANTS + +2.1 Source Code. OBJECTIVE DEVELOPMENT shall furnish you with the source +code of V-USB. + +2.2 Distribution and Use. OBJECTIVE DEVELOPMENT grants you the +non-exclusive right to use, copy and distribute V-USB with your hardware +product(s), restricted by the limitations in section 3 below. + +2.3 Modifications. OBJECTIVE DEVELOPMENT grants you the right to modify +the source code and your copy of V-USB according to your needs. + +2.4 USB IDs. OBJECTIVE DEVELOPMENT furnishes you with one or two USB +Product ID(s), sent to you in e-mail. These Product IDs are reserved +exclusively for you. OBJECTIVE DEVELOPMENT has obtained USB Product ID +ranges under the Vendor ID 5824 from Wouter van Ooijen (Van Ooijen +Technische Informatica, www.voti.nl) and under the Vendor ID 8352 from +Jason Kotzin (Clay Logic, www.claylogic.com). Both owners of the Vendor IDs +have obtained these IDs from the USB Implementers Forum, Inc. +(www.usb.org). OBJECTIVE DEVELOPMENT disclaims all liability which might +arise from the assignment of USB IDs. + +2.5 USB Certification. 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This document represents the entire agreement between +OBJECTIVE DEVELOPMENT and you. It may only be modified in writing signed by +an authorized representative of both, OBJECTIVE DEVELOPMENT and you. + +8.3 Severability. In case a provision of these terms and conditions should +be or become partly or entirely invalid, ineffective, or not executable, +the validity of all other provisions shall not be affected. + +8.4 Applicable Law. This agreement is governed by the laws of the Republic +of Austria. + +8.5 Responsible Courts. The responsible courts in Vienna/Austria will have +exclusive jurisdiction regarding all disputes in connection with this +agreement. + diff --git a/hardware/digistump/avr/libraries/DigiUSB/DigiUSB.cpp b/hardware/digistump/avr/libraries/DigiUSB/DigiUSB.cpp new file mode 100644 index 0000000..30311f6 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/DigiUSB.cpp @@ -0,0 +1,218 @@ +/* Name: DigiUSB.c + * Based on V-USB Arduino Examples by Philip J. Lindsay + * Modification for the Digispark by Erik Kettenburg, Digistump LLC + * VID/PID changed to pair owned by Digistump LLC, code modified to use pinchange int for attiny85 + * Original notice below: + * Based on project: hid-data, example how to use HID for data transfer + * (Uses modified descriptor and usbFunctionSetup from it.) + * Original author: Christian Starkjohann + * Arduino modifications by: Philip J. Lindsay + * Creation Date: 2008-04-11 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: main.c 692 2008-11-07 15:07:40Z cs $ + */ + +/* +This example should run on most AVRs with only little changes. No special +hardware resources except INT0 are used. You may have to change usbconfig.h for +different I/O pins for USB. Please note that USB D+ must be the INT0 pin, or +at least be connected to INT0 as well. +*/ + +#include +#include +#include +#include /* for sei() */ +#include /* for _delay_ms() */ +#include +#include /* required by usbdrv.h */ +#include "usbdrv.h" +#include "oddebug.h" /* This is also an example for using debug macros */ + +#include "DigiUSB.h" + +#if F_CPU != 16500000L + #error "You must use Digispark (Tiny Core) board to use USB libraries" +#endif + +// Ring buffer implementation nicked from HardwareSerial.cpp +// TODO: Don't nick it. :) +ring_buffer rx_buffer = { { 0 }, 0, 0 }; +ring_buffer tx_buffer = { { 0 }, 0, 0 }; + + +inline int store_char(unsigned char c, ring_buffer *the_buffer) +{ + int i = (the_buffer->head + 1) % RING_BUFFER_SIZE; + + // if we should be storing the received character into the location + // just before the tail (meaning that the head would advance to the + // current location of the tail), we're about to overflow the buffer + // and so we don't write the character or advance the head. + if (i != the_buffer->tail) { + the_buffer->buffer[the_buffer->head] = c; + the_buffer->head = i; + return 1; + } + return 0; + +} + +DigiUSBDevice::DigiUSBDevice(ring_buffer *rx_buffer, + ring_buffer *tx_buffer) { + _rx_buffer = rx_buffer; + _tx_buffer = tx_buffer; +} + +void DigiUSBDevice::begin() { + cli(); + + usbInit(); + + usbDeviceDisconnect(); + uchar i; + i = 0; + while(--i){ /* fake USB disconnect for > 250 ms */ + _delay_ms(10); + } + usbDeviceConnect(); + + sei(); + } + +// TODO: Deprecate update +void DigiUSBDevice::update() { + refresh(); +} + + +void DigiUSBDevice::refresh() { + usbPoll(); +} + +// wait a specified number of milliseconds (roughly), refreshing in the background +void DigiUSBDevice::delay(long milli) { + unsigned long last = millis(); + while (milli > 0) { + unsigned long now = millis(); + milli -= now - last; + last = now; + refresh(); + } +} + +int DigiUSBDevice::available() { + /* + */ + return (RING_BUFFER_SIZE + _rx_buffer->head - _rx_buffer->tail) % RING_BUFFER_SIZE; +} + +int DigiUSBDevice::tx_remaining() { + return RING_BUFFER_SIZE - (RING_BUFFER_SIZE + _tx_buffer->head - _tx_buffer->tail) % RING_BUFFER_SIZE; +} + +int DigiUSBDevice::read() { + /* + */ + // if the head isn't ahead of the tail, we don't have any characters + if (_rx_buffer->head == _rx_buffer->tail) { + return -1; + } else { + unsigned char c = _rx_buffer->buffer[_rx_buffer->tail]; + _rx_buffer->tail = (_rx_buffer->tail + 1) % RING_BUFFER_SIZE; + return c; + } +} + +size_t DigiUSBDevice::write(byte c) { + /* + */ + return store_char(c, _tx_buffer); +} + + +// TODO: Handle this better? +int tx_available() { + /* + */ + return (RING_BUFFER_SIZE + tx_buffer.head - tx_buffer.tail) % RING_BUFFER_SIZE; +} + +int tx_read() { + /* + */ + // if the head isn't ahead of the tail, we don't have any characters + if (tx_buffer.head == tx_buffer.tail) { + return -1; + } else { + unsigned char c = tx_buffer.buffer[tx_buffer.tail]; + tx_buffer.tail = (tx_buffer.tail + 1) % RING_BUFFER_SIZE; + return c; + } +} + + + + +/* ------------------------------------------------------------------------- */ +/* ----------------------------- USB interface ----------------------------- */ +/* ------------------------------------------------------------------------- */ + +#ifdef __cplusplus +extern "C"{ +#endif +PROGMEM char usbHidReportDescriptor[22] = { /* USB report descriptor */ + 0x06, 0x00, 0xff, // USAGE_PAGE (Generic Desktop) + 0x09, 0x01, // USAGE (Vendor Usage 1) + 0xa1, 0x01, // COLLECTION (Application) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x26, 0xff, 0x00, // LOGICAL_MAXIMUM (255) + 0x75, 0x08, // REPORT_SIZE (8) + 0x95, 0x01, // REPORT_COUNT (1) + 0x09, 0x00, // USAGE (Undefined) + 0xb2, 0x02, 0x01, // FEATURE (Data,Var,Abs,Buf) + 0xc0 // END_COLLECTION +}; +/* Since we define only one feature report, we don't use report-IDs (which + * would be the first byte of the report). The entire report consists of 1 + * opaque data bytes. + */ + +/* ------------------------------------------------------------------------- */ + +usbMsgLen_t usbFunctionSetup(uchar data[8]) +{ + usbRequest_t *rq = (usbRequest_t*)((void *)data); + + if((rq->bmRequestType & USBRQ_TYPE_MASK) == USBRQ_TYPE_CLASS){ /* HID class request */ + if(rq->bRequest == USBRQ_HID_GET_REPORT){ /* wValue: ReportType (highbyte), ReportID (lowbyte) */ + /* since we have only one report type, we can ignore the report-ID */ + static uchar dataBuffer[1]; /* buffer must stay valid when usbFunctionSetup returns */ + if (tx_available()) { + dataBuffer[0] = tx_read(); + usbMsgPtr = dataBuffer; /* tell the driver which data to return */ + return 1; /* tell the driver to send 1 byte */ + } else { + // Drop through to return 0 (which will stall the request?) + } + }else if(rq->bRequest == USBRQ_HID_SET_REPORT){ + /* since we have only one report type, we can ignore the report-ID */ + + // TODO: Check race issues? + store_char(rq->wIndex.bytes[0], &rx_buffer); + + } + }else{ + /* ignore vendor type requests, we don't use any */ + } + return 0; +} +#ifdef __cplusplus +} // extern "C" +#endif + +DigiUSBDevice DigiUSB = DigiUSBDevice(&rx_buffer, &tx_buffer); + + diff --git a/hardware/digistump/avr/libraries/DigiUSB/DigiUSB.h b/hardware/digistump/avr/libraries/DigiUSB/DigiUSB.h new file mode 100644 index 0000000..dc0773b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/DigiUSB.h @@ -0,0 +1,60 @@ +/* + * Based on Obdev's AVRUSB code and under the same license. + * + * TODO: Make a proper file header. :-) + */ +#ifndef __DigiUSB_h__ +#define __DigiUSB_h__ + +#include +#include +#include +#include "usbdrv.h" +#include "Print.h" + + +typedef uint8_t byte; + +#include /* for _delay_ms() */ + +#define RING_BUFFER_SIZE 128 + + +struct ring_buffer { + unsigned char buffer[RING_BUFFER_SIZE]; + int head; + int tail; +}; + + + + + +class DigiUSBDevice : public Print { + private: + ring_buffer *_rx_buffer; + ring_buffer *_tx_buffer; + + public: + DigiUSBDevice (ring_buffer *rx_buffer, ring_buffer *tx_buffer); + + void begin(); + + // TODO: Deprecate update + void update(); + + void refresh(); + void delay(long milliseconds); + + int available(); + int tx_remaining(); + + int read(); + virtual size_t write(byte c); + using Print::write; + +}; + +extern DigiUSBDevice DigiUSB; + +#endif // __DigiUSB_h__ diff --git a/hardware/digistump/avr/libraries/DigiUSB/DigisparkReadme.txt b/hardware/digistump/avr/libraries/DigiUSB/DigisparkReadme.txt new file mode 100644 index 0000000..15e71f6 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/DigisparkReadme.txt @@ -0,0 +1 @@ +Modified for use with an Attiny85 running at 16.5Mhz by Digistump for the Digispark MCU \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigiUSB/License.txt b/hardware/digistump/avr/libraries/DigiUSB/License.txt new file mode 100644 index 0000000..4460cfb --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/License.txt @@ -0,0 +1,361 @@ +OBJECTIVE DEVELOPMENT GmbH's V-USB driver software is distributed under the +terms and conditions of the GNU GPL version 2 or the GNU GPL version 3. It is +your choice whether you apply the terms of version 2 or version 3. The full +text of GPLv2 is included below. In addition to the requirements in the GPL, +we STRONGLY ENCOURAGE you to do the following: + +(1) Publish your entire project on a web site and drop us a note with the URL. +Use the form at http://www.obdev.at/vusb/feedback.html for your submission. + +(2) Adhere to minimum publication standards. Please include AT LEAST: + - a circuit diagram in PDF, PNG or GIF format + - full source code for the host software + - a Readme.txt file in ASCII format which describes the purpose of the + project and what can be found in which directories and which files + - a reference to http://www.obdev.at/vusb/ + +(3) If you improve the driver firmware itself, please give us a free license +to your modifications for our commercial license offerings. + + + + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/hardware/digistump/avr/libraries/DigiUSB/Readme.txt b/hardware/digistump/avr/libraries/DigiUSB/Readme.txt new file mode 100644 index 0000000..a010d97 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/Readme.txt @@ -0,0 +1,158 @@ +This is the Readme file to Objective Development's firmware-only USB driver +for Atmel AVR microcontrollers. For more information please visit +http://www.obdev.at/vusb/ + +This directory contains the USB firmware only. Copy it as-is to your own +project and add all .c and .S files to your project (these files are marked +with an asterisk in the list below). Then copy usbconfig-prototype.h as +usbconfig.h to your project and edit it according to your configuration. + + +TECHNICAL DOCUMENTATION +======================= +The technical documentation (API) for the firmware driver is contained in the +file "usbdrv.h". Please read all of it carefully! Configuration options are +documented in "usbconfig-prototype.h". + +The driver consists of the following files: + Readme.txt ............. The file you are currently reading. + Changelog.txt .......... Release notes for all versions of the driver. + usbdrv.h ............... Driver interface definitions and technical docs. +* usbdrv.c ............... High level language part of the driver. Link this + module to your code! +* usbdrvasm.S ............ Assembler part of the driver. This module is mostly + a stub and includes one of the usbdrvasm*.S files + depending on processor clock. Link this module to + your code! + usbdrvasm*.inc ......... Assembler routines for particular clock frequencies. + Included by usbdrvasm.S, don't link it directly! + asmcommon.inc .......... Common assembler routines. Included by + usbdrvasm*.inc, don't link it directly! + usbconfig-prototype.h .. Prototype for your own usbdrv.h file. +* oddebug.c .............. Debug functions. Only used when DEBUG_LEVEL is + defined to a value greater than 0. Link this module + to your code! + oddebug.h .............. Interface definitions of the debug module. + usbportability.h ....... Header with compiler-dependent stuff. + usbdrvasm.asm .......... Compatibility stub for IAR-C-compiler. Use this + module instead of usbdrvasm.S when you assembler + with IAR's tools. + License.txt ............ Open Source license for this driver. + CommercialLicense.txt .. Optional commercial license for this driver. + USB-ID-FAQ.txt ......... General infos about USB Product- and Vendor-IDs. + USB-IDs-for-free.txt ... List and terms of use for free shared PIDs. + +(*) ... These files should be linked to your project. + + +CPU CORE CLOCK FREQUENCY +======================== +We supply assembler modules for clock frequencies of 12 MHz, 12.8 MHz, 15 MHz, +16 MHz, 16.5 MHz 18 MHz and 20 MHz. Other clock rates are not supported. The +actual clock rate must be configured in usbdrv.h unless you use the default +12 MHz. + +12 MHz Clock +This is the traditional clock rate of V-USB because it's the lowest clock +rate where the timing constraints of the USB spec can be met. + +15 MHz Clock +Similar to 12 MHz, but some NOPs inserted. On the other hand, the higher clock +rate allows for some loops which make the resulting code size somewhat smaller +than the 12 MHz version. + +16 MHz Clock +This clock rate has been added for users of the Arduino board and other +ready-made boards which come with a fixed 16 MHz crystal. It's also an option +if you need the slightly higher clock rate for performance reasons. Since +16 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code +is somewhat tricky and has to insert a leap cycle every third byte. + +12.8 MHz and 16.5 MHz Clock +The assembler modules for these clock rates differ from the other modules +because they have been built for an RC oscillator with only 1% precision. The +receiver code inserts leap cycles to compensate for clock deviations. 1% is +also the precision which can be achieved by calibrating the internal RC +oscillator of the AVR. Please note that only AVRs with internal 64 MHz PLL +oscillator can reach 16.5 MHz with the RC oscillator. This includes the very +popular ATTiny25, ATTiny45, ATTiny85 series as well as the ATTiny26. Almost +all AVRs can reach 12.8 MHz, although this is outside the specified range. + +See the EasyLogger example at http://www.obdev.at/vusb/easylogger.html for +code which calibrates the RC oscillator based on the USB frame clock. + +18 MHz Clock +This module is closer to the USB specification because it performs an on the +fly CRC check for incoming packets. Packets with invalid checksum are +discarded as required by the spec. If you also implement checks for data +PID toggling on application level (see option USB_CFG_CHECK_DATA_TOGGLING +in usbconfig.h for more info), this ensures data integrity. Due to the CRC +tables and alignment requirements, this code is bigger than modules for other +clock rates. To activate this module, you must define USB_CFG_CHECK_CRC to 1 +and USB_CFG_CLOCK_KHZ to 18000 in usbconfig.h. + +20 MHz Clock +This module is for people who won't do it with less than the maximum. Since +20 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code +uses similar tricks as the 16 MHz module to insert leap cycles. + + +USB IDENTIFIERS +=============== +Every USB device needs a vendor- and a product-identifier (VID and PID). VIDs +are obtained from usb.org for a price of 1,500 USD. Once you have a VID, you +can assign PIDs at will. + +Since an entry level cost of 1,500 USD is too high for most small companies +and hobbyists, we provide some VID/PID pairs for free. See the file +USB-IDs-for-free.txt for details. + +Objective Development also has some license offerings which include product +IDs. See http://www.obdev.at/vusb/ for details. + + +DEVELOPMENT SYSTEM +================== +This driver has been developed and optimized for the GNU compiler version 3 +(gcc 3). It does work well with gcc 4, but with bigger code size. We recommend +that you use the GNU compiler suite because it is freely available. V-USB +has also been ported to the IAR compiler and assembler. It has been tested +with IAR 4.10B/W32 and 4.12A/W32 on an ATmega8 with the "small" and "tiny" +memory model. Not every release is tested with IAR CC and the driver may +therefore fail to compile with IAR. Please note that gcc is more efficient for +usbdrv.c because this module has been deliberately optimized for gcc. + + +USING V-USB FOR FREE +==================== +The AVR firmware driver is published under the GNU General Public License +Version 2 (GPL2) and the GNU General Public License Version 3 (GPL3). It is +your choice whether you apply the terms of version 2 or version 3. + +If you decide for the free GPL2 or GPL3, we STRONGLY ENCOURAGE you to do the +following things IN ADDITION to the obligations from the GPL: + +(1) Publish your entire project on a web site and drop us a note with the URL. +Use the form at http://www.obdev.at/vusb/feedback.html for your submission. +If you don't have a web site, you can publish the project in obdev's +documentation wiki at +http://www.obdev.at/goto.php?t=vusb-wiki&p=hosted-projects. + +(2) Adhere to minimum publication standards. Please include AT LEAST: + - a circuit diagram in PDF, PNG or GIF format + - full source code for the host software + - a Readme.txt file in ASCII format which describes the purpose of the + project and what can be found in which directories and which files + - a reference to http://www.obdev.at/vusb/ + +(3) If you improve the driver firmware itself, please give us a free license +to your modifications for our commercial license offerings. + + +COMMERCIAL LICENSES FOR V-USB +============================= +If you don't want to publish your source code under the terms of the GPL, +you can simply pay money for V-USB. As an additional benefit you get +USB PIDs for free, reserved exclusively to you. See the file +"CommercialLicense.txt" for details. + diff --git a/hardware/digistump/avr/libraries/DigiUSB/USB-ID-FAQ.txt b/hardware/digistump/avr/libraries/DigiUSB/USB-ID-FAQ.txt new file mode 100644 index 0000000..d1de8fb --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/USB-ID-FAQ.txt @@ -0,0 +1,149 @@ +Version 2009-08-22 + +========================== +WHY DO WE NEED THESE IDs? +========================== + +USB is more than a low level protocol for data transport. It also defines a +common set of requests which must be understood by all devices. And as part +of these common requests, the specification defines data structures, the +USB Descriptors, which are used to describe the properties of the device. + +From the perspective of an operating system, it is therefore possible to find +out basic properties of a device (such as e.g. the manufacturer and the name +of the device) without a device-specific driver. This is essential because +the operating system can choose a driver to load based on this information +(Plug-And-Play). + +Among the most important properties in the Device Descriptor are the USB +Vendor- and Product-ID. Both are 16 bit integers. The most simple form of +driver matching is based on these IDs. The driver announces the Vendor- and +Product-IDs of the devices it can handle and the operating system loads the +appropriate driver when the device is connected. + +It is obvious that this technique only works if the pair Vendor- plus +Product-ID is unique: Only devices which require the same driver can have the +same pair of IDs. + + +===================================================== +HOW DOES THE USB STANDARD ENSURE THAT IDs ARE UNIQUE? +===================================================== + +Since it is so important that USB IDs are unique, the USB Implementers Forum, +Inc. (usb.org) needs a way to enforce this legally. It is not forbidden by +law to build a device and assign it any random numbers as IDs. Usb.org +therefore needs an agreement to regulate the use of USB IDs. The agreement +binds only parties who agreed to it, of course. Everybody else is free to use +any numbers for their IDs. + +So how can usb.org ensure that every manufacturer of USB devices enters into +an agreement with them? They do it via trademark licensing. Usb.org has +registered the trademark "USB", all associated logos and related terms. If +you want to put an USB logo on your product or claim that it is USB +compliant, you must license these trademarks from usb.org. And this is where +you enter into an agreement. See the "USB-IF Trademark License Agreement and +Usage Guidelines for the USB-IF Logo" at +http://www.usb.org/developers/logo_license/. + +Licensing the USB trademarks requires that you buy a USB Vendor-ID from +usb.org (one-time fee of ca. 2,000 USD), that you become a member of usb.org +(yearly fee of ca. 4,000 USD) and that you meet all the technical +specifications from the USB spec. + +This means that most hobbyists and small companies will never be able to +become USB compliant, just because membership is so expensive. And you can't +be compliant with a driver based on V-USB anyway, because the AVR's port pins +don't meet the electrical specifications for USB. So, in principle, all +hobbyists and small companies are free to choose any random numbers for their +IDs. They have nothing to lose... + +There is one exception worth noting, though: If you use a sub-component which +implements USB, the vendor of the sub-components may guarantee USB +compliance. This might apply to some or all of FTDI's solutions. + + +======================================================================= +WHY SHOULD YOU OBTAIN USB IDs EVEN IF YOU DON'T LICENSE USB TRADEMARKS? +======================================================================= + +You have learned in the previous section that you are free to choose any +numbers for your IDs anyway. So why not do exactly this? There is still the +technical issue. If you choose IDs which are already in use by somebody else, +operating systems will load the wrong drivers and your device won't work. +Even if you choose IDs which are not currently in use, they may be in use in +the next version of the operating system or even after an automatic update. + +So what you need is a pair of Vendor- and Product-IDs for which you have the +guarantee that no USB compliant product uses them. This implies that no +operating system will ever ship with drivers responsible for these IDs. + + +============================================== +HOW DOES OBJECTIVE DEVELOPMENT HANDLE USB IDs? +============================================== + +Objective Development gives away pairs of USB-IDs with their V-USB licenses. +In order to ensure that these IDs are unique, Objective Development has an +agreement with the company/person who has bought the USB Vendor-ID from +usb.org. This agreement ensures that a range of USB Product-IDs is reserved +for assignment by Objective Development and that the owner of the Vendor-ID +won't give it to anybody else. + +This means that you have to trust three parties to ensure uniqueness of +your IDs: + + - Objective Development, that they don't give the same PID to more than + one person. + - The owner of the Vendor-ID that they don't assign PIDs from the range + assigned to Objective Development to anybody else. + - Usb.org that they don't assign the same Vendor-ID a second time. + + +================================== +WHO IS THE OWNER OF THE VENDOR-ID? +================================== + +Objective Development has obtained ranges of USB Product-IDs under two +Vendor-IDs: Under Vendor-ID 5824 from Wouter van Ooijen (Van Ooijen +Technische Informatica, www.voti.nl) and under Vendor-ID 8352 from Jason +Kotzin (Clay Logic, www.claylogic.com). Both VID owners have received their +Vendor-ID directly from usb.org. + + +========================================================================= +CAN I USE USB-IDs FROM OBJECTIVE DEVELOPMENT WITH OTHER DRIVERS/HARDWARE? +========================================================================= + +The short answer is: Yes. All you get is a guarantee that the IDs are never +assigned to anybody else. What more do you need? + + +============================ +WHAT ABOUT SHARED ID PAIRS? +============================ + +Objective Development has reserved some PID/VID pairs for shared use. You +have no guarantee of uniqueness for them, except that no USB compliant device +uses them. In order to avoid technical problems, we must ensure that all +devices with the same pair of IDs use the same driver on kernel level. For +details, see the file USB-IDs-for-free.txt. + + +====================================================== +I HAVE HEARD THAT SUB-LICENSING OF USB-IDs IS ILLEGAL? +====================================================== + +A 16 bit integer number cannot be protected by copyright laws. It is not +sufficiently complex. And since none of the parties involved entered into the +USB-IF Trademark License Agreement, we are not bound by this agreement. So +there is no reason why it should be illegal to sub-license USB-IDs. + + +============================================= +WHO IS LIABLE IF THERE ARE INCOMPATIBILITIES? +============================================= + +Objective Development disclaims all liabilities which might arise from the +assignment of IDs. If you guarantee product features to your customers +without proper disclaimer, YOU are liable for that. diff --git a/hardware/digistump/avr/libraries/DigiUSB/USB-IDs-for-free.txt b/hardware/digistump/avr/libraries/DigiUSB/USB-IDs-for-free.txt new file mode 100644 index 0000000..2f4d59a --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/USB-IDs-for-free.txt @@ -0,0 +1,148 @@ +Version 2009-08-22 + +=========================== +FREE USB-IDs FOR SHARED USE +=========================== + +Objective Development has reserved a set of USB Product-IDs for use according +to the guidelines outlined below. For more information about the concept of +USB IDs please see the file USB-ID-FAQ.txt. Objective Development guarantees +that the IDs listed below are not used by any USB compliant devices. + + +==================== +MECHANISM OF SHARING +==================== + +From a technical point of view, two different devices can share the same USB +Vendor- and Product-ID if they require the same driver on operating system +level. We make use of this fact by assigning separate IDs for various device +classes. On application layer, devices must be distinguished by their textual +name or serial number. We offer separate sets of IDs for discrimination by +textual name and for serial number. + +Examples for shared use of USB IDs are included with V-USB in the "examples" +subdirectory. + + +====================================== +IDs FOR DISCRIMINATION BY TEXTUAL NAME +====================================== + +If you use one of the IDs listed below, your device and host-side software +must conform to these rules: + +(1) The USB device MUST provide a textual representation of the manufacturer +and product identification. The manufacturer identification MUST be available +at least in USB language 0x0409 (English/US). + +(2) The textual manufacturer identification MUST contain either an Internet +domain name (e.g. "mycompany.com") registered and owned by you, or an e-mail +address under your control (e.g. "myname@gmx.net"). You can embed the domain +name or e-mail address in any string you like, e.g. "Objective Development +http://www.obdev.at/vusb/". + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(4) You may choose any string for the textual product identification, as long +as this string is unique within the scope of your textual manufacturer +identification. + +(5) Application side device look-up MUST be based on the textual manufacturer +and product identification in addition to VID/PID matching. The driver +matching MUST be a comparison of the entire strings, NOT a sub-string match. + +(6) For devices which implement a particular USB device class (e.g. HID), the +operating system's default class driver MUST be used. If an operating system +driver for Vendor Class devices is needed, this driver must be libusb or +libusb-win32 (see http://libusb.org/ and +http://libusb-win32.sourceforge.net/). + +Table if IDs for discrimination by textual name: + +PID dec (hex) | VID dec (hex) | Description of use +==============+===============+============================================ +1500 (0x05dc) | 5824 (0x16c0) | For Vendor Class devices with libusb +--------------+---------------+-------------------------------------------- +1503 (0x05df) | 5824 (0x16c0) | For generic HID class devices (which are + | | NOT mice, keyboards or joysticks) +--------------+---------------+-------------------------------------------- +1505 (0x05e1) | 5824 (0x16c0) | For CDC-ACM class devices (modems) +--------------+---------------+-------------------------------------------- +1508 (0x05e4) | 5824 (0x16c0) | For MIDI class devices +--------------+---------------+-------------------------------------------- + +Note that Windows caches the textual product- and vendor-description for +mice, keyboards and joysticks. Name-bsed discrimination is therefore not +recommended for these device classes. + + +======================================= +IDs FOR DISCRIMINATION BY SERIAL NUMBER +======================================= + +If you use one of the IDs listed below, your device and host-side software +must conform to these rules: + +(1) The USB device MUST provide a textual representation of the serial +number. The serial number string MUST be available at least in USB language +0x0409 (English/US). + +(2) The serial number MUST start with either an Internet domain name (e.g. +"mycompany.com") registered and owned by you, or an e-mail address under your +control (e.g. "myname@gmx.net"), both terminated with a colon (":") character. +You MAY append any string you like for further discrimination of your devices. + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(5) Application side device look-up MUST be based on the serial number string +in addition to VID/PID matching. The matching must start at the first +character of the serial number string and include the colon character +terminating your domain or e-mail address. It MAY stop anywhere after that. + +(6) For devices which implement a particular USB device class (e.g. HID), the +operating system's default class driver MUST be used. If an operating system +driver for Vendor Class devices is needed, this driver must be libusb or +libusb-win32 (see http://libusb.org/ and +http://libusb-win32.sourceforge.net/). + +Table if IDs for discrimination by serial number string: + +PID dec (hex) | VID dec (hex) | Description of use +===============+===============+=========================================== +10200 (0x27d8) | 5824 (0x16c0) | For Vendor Class devices with libusb +---------------+---------------+------------------------------------------- +10201 (0x27d9) | 5824 (0x16c0) | For generic HID class devices (which are + | | NOT mice, keyboards or joysticks) +---------------+---------------+------------------------------------------- +10202 (0x27da) | 5824 (0x16c0) | For USB Mice +---------------+---------------+------------------------------------------- +10203 (0x27db) | 5824 (0x16c0) | For USB Keyboards +---------------+---------------+------------------------------------------- +10204 (0x27db) | 5824 (0x16c0) | For USB Joysticks +---------------+---------------+------------------------------------------- +10205 (0x27dc) | 5824 (0x16c0) | For CDC-ACM class devices (modems) +---------------+---------------+------------------------------------------- +10206 (0x27dd) | 5824 (0x16c0) | For MIDI class devices +---------------+---------------+------------------------------------------- + + +================= +ORIGIN OF USB-IDs +================= + +OBJECTIVE DEVELOPMENT Software GmbH has obtained all VID/PID pairs listed +here from Wouter van Ooijen (see www.voti.nl) for exclusive disposition. +Wouter van Ooijen has obtained the VID from the USB Implementers Forum, Inc. +(see www.usb.org). The VID is registered for the company name "Van Ooijen +Technische Informatica". + + +========== +DISCLAIMER +========== + +OBJECTIVE DEVELOPMENT Software GmbH disclaims all liability for any +problems which are caused by the shared use of these VID/PID pairs. diff --git a/hardware/digistump/avr/libraries/DigiUSB/USBID-License.txt b/hardware/digistump/avr/libraries/DigiUSB/USBID-License.txt new file mode 100644 index 0000000..c40be92 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/USBID-License.txt @@ -0,0 +1,154 @@ +Royalty-Free Non-Exclusive Use of USB Product-IDs +================================================= + +Version 2009-04-13 + +Strictly speaking, this is not a license. You can't give a license to use +a simple number (such as e.g. 1500) for any purpose. This is a set of rules +which should make it possible to build USB devices without the requirement +for individual USB IDs. If you break one of the rules, you will run into +technical problems sooner or later, but you don't risk legal trouble. + + +OBJECTIVE DEVELOPMENT Software GmbH hereby grants you the non-exclusive +right to use four USB.org vendor-ID (VID) / product-ID (PID) pairs with +products based on Objective Development's firmware-only USB driver for +Atmel AVR microcontrollers: + + * VID = 5824 (=0x16c0) / PID = 1500 (=0x5dc) for devices implementing no + USB device class (vendor-class devices with USB class = 0xff). Devices + using this pair will be referred to as "VENDOR CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1503 (=0x5df) for HID class devices + (excluding mice and keyboards). Devices using this pair will be referred + to as "HID CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1505 (=0x5e1) for CDC class modem devices + Devices using this pair will be referred to as "CDC-ACM CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1508 (=0x5e4) for MIDI class devices + Devices using this pair will be referred to as "MIDI CLASS" devices. + +Since the granted right is non-exclusive, the same VID/PID pairs may be +used by many companies and individuals for different products. To avoid +conflicts, your device and host driver software MUST adhere to the rules +outlined below. + +OBJECTIVE DEVELOPMENT Software GmbH has obtained these VID/PID pairs from +Wouter van Ooijen (see www.voti.nl) for exclusive disposition. Wouter van +Ooijen has obtained the VID from the USB Implementers Forum, Inc. +(see www.usb.org). The VID is registered for the company name +"Van Ooijen Technische Informatica". + + +RULES AND RESTRICTIONS +====================== + +(1) The USB device MUST provide a textual representation of the +manufacturer and product identification. The manufacturer identification +MUST be available at least in USB language 0x0409 (English/US). + +(2) The textual manufacturer identification MUST contain either an Internet +domain name (e.g. "mycompany.com") registered and owned by you, or an +e-mail address under your control (e.g. "myname@gmx.net"). You can embed +the domain name or e-mail address in any string you like, e.g. "Objective +Development http://www.obdev.at/vusb/". + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(4) You may choose any string for the textual product identification, as +long as this string is unique within the scope of your textual manufacturer +identification. + +(5) Matching of device-specific drivers MUST be based on the textual +manufacturer and product identification in addition to the usual VID/PID +matching. This means that operating system features which are based on +VID/PID matching only (e.g. Windows kernel level drivers, automatic actions +when the device is plugged in etc) MUST NOT be used. The driver matching +MUST be a comparison of the entire strings, NOT a sub-string match. For +CDC-ACM CLASS and MIDI CLASS devices, a generic class driver should be used +and the matching is based on the USB device class. + +(6) The extent to which VID/PID matching is allowed for non device-specific +drivers or features depends on the operating system and particular VID/PID +pair used: + + * Mac OS X, Linux, FreeBSD and other Unixes: No VID/PID matching is + required and hence no VID/PID-only matching is allowed at all. + + * Windows: The operating system performs VID/PID matching for the kernel + level driver. You are REQUIRED to use libusb-win32 (see + http://libusb-win32.sourceforge.net/) as the kernel level driver for + VENDOR CLASS devices. HID CLASS devices all use the generic HID class + driver shipped with Windows, except mice and keyboards. You therefore + MUST NOT use any of the shared VID/PID pairs for mice or keyboards. + CDC-ACM CLASS devices require a ".inf" file which matches on the VID/PID + pair. This ".inf" file MUST load the "usbser" driver to configure the + device as modem (COM-port). + +(7) OBJECTIVE DEVELOPMENT Software GmbH disclaims all liability for any +problems which are caused by the shared use of these VID/PID pairs. You +have been warned that the sharing of VID/PID pairs may cause problems. If +you want to avoid them, get your own VID/PID pair for exclusive use. + + +HOW TO IMPLEMENT THESE RULES +============================ + +The following rules are for VENDOR CLASS and HID CLASS devices. CDC-ACM +CLASS and MIDI CLASS devices use the operating system's class driver and +don't need a custom driver. + +The host driver MUST iterate over all devices with the given VID/PID +numbers in their device descriptors and query the string representation for +the manufacturer name in USB language 0x0409 (English/US). It MUST compare +the ENTIRE string with your textual manufacturer identification chosen in +(2) above. A substring search for your domain or e-mail address is NOT +acceptable. The driver MUST NOT touch the device (other than querying the +descriptors) unless the strings match. + +For all USB devices with matching VID/PID and textual manufacturer +identification, the host driver must query the textual product +identification and string-compare it with the name of the product it can +control. It may only initialize the device if the product matches exactly. + +Objective Development provides examples for these matching rules with the +"PowerSwitch" project (using libusb) and with the "Automator" project +(using Windows calls on Windows and libusb on Unix). + + +Technical Notes: +================ + +Sharing the same VID/PID pair among devices is possible as long as ALL +drivers which match the VID/PID also perform matching on the textual +identification strings. This is easy on all operating systems except +Windows, since Windows establishes a static connection between the VID/PID +pair and a kernel level driver. All devices with the same VID/PID pair must +therefore use THE SAME kernel level driver. + +We therefore demand that you use libusb-win32 for VENDOR CLASS devices. +This is a generic kernel level driver which allows all types of USB access +for user space applications. This is only a partial solution of the +problem, though, because different device drivers may come with different +versions of libusb-win32 and they may not work with the libusb version of +the respective other driver. You are therefore encouraged to test your +driver against a broad range of libusb-win32 versions. Do not use new +features in new versions, or check for their existence before you use them. +When a new libusb-win32 becomes available, make sure that your driver is +compatible with it. + +For HID CLASS devices it is necessary that all those devices bind to the +same kernel driver: Microsoft's generic USB HID driver. This is true for +all HID devices except those with a specialized driver. Currently, the only +HIDs with specialized drivers are mice and keyboards. You therefore MUST +NOT use a shared VID/PID with mouse and keyboard devices. + +Sharing the same VID/PID among different products is unusual and probably +violates the USB specification. If you do it, you do it at your own risk. + +To avoid possible incompatibilities, we highly recommend that you get your +own VID/PID pair if you intend to sell your product. Objective +Development's commercial licenses for V-USB include a PID for +unrestricted exclusive use. diff --git a/hardware/digistump/avr/libraries/DigiUSB/asmcommon.inc b/hardware/digistump/avr/libraries/DigiUSB/asmcommon.inc new file mode 100644 index 0000000..07d692b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/asmcommon.inc @@ -0,0 +1,188 @@ +/* Name: asmcommon.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2007-11-05 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id$ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file contains assembler code which is shared among the USB driver +implementations for different CPU cocks. Since the code must be inserted +in the middle of the module, it's split out into this file and #included. + +Jump destinations called from outside: + sofError: Called when no start sequence was found. + se0: Called when a package has been successfully received. + overflow: Called when receive buffer overflows. + doReturn: Called after sending data. + +Outside jump destinations used by this module: + waitForJ: Called to receive an already arriving packet. + sendAckAndReti: + sendNakAndReti: + sendCntAndReti: + usbSendAndReti: + +The following macros must be defined before this file is included: + .macro POP_STANDARD + .endm + .macro POP_RETI + .endm +*/ + +#define token x1 + +overflow: + ldi x2, 1< +byte in = 0; +int Blue = 0; +int Red = 0; +int Green = 0; + +int next = 0; + +void setup() { + DigiUSB.begin(); + pinMode(0,OUTPUT); + pinMode(1,OUTPUT); + pinMode(2,OUTPUT); +} + + +void loop() { + setBlue(); + DigiUSB.refresh(); + setBlue(); + if (DigiUSB.available() > 0) { + in = 0; + + in = DigiUSB.read(); + if (next == 0){ + if(in == 115){ + next = 1; + DigiUSB.println("Start"); + } + } + else if (next == 1){ + Red = in; + DigiUSB.print("Red "); + DigiUSB.println(in,DEC); + next = 2; + } + else if (next == 2){ + Green = in; + DigiUSB.print("Green "); + DigiUSB.println(in,DEC); + next = 3; + } + else if (next == 3){ + Blue = in; + DigiUSB.print("Blue "); + DigiUSB.println(in,DEC); + next = 0; + } + + + + + } + + + analogWrite(0,Red); + analogWrite(1,Green); + setBlue(); + + + +} + +void setBlue(){ + if(Blue == 0){ + digitalWrite(2,LOW); + return; + } + else if(Blue == 255){ + digitalWrite(2,HIGH); + return; + } + // On period + for (int x=0;x + +void setup() { + DigiUSB.begin(); +} + +void get_input() { + // when there are no characters to read + while (1==1) { + if(DigiUSB.available()){ + //something to read + DigiUSB.read(); + break; + } + // refresh the usb port + DigiUSB.refresh(); + delay(10); + + } + +} + + +void loop() { + DigiUSB.refresh(); + //print output + float value = analogRead(1); //This is Pin3 + if(value>1020) + value = 255; + else if(value<2) + value = 0; + else + value = value/4; + //send value + + value = round(byte(value)); + DigiUSB.write(value); + + //wait for response + get_input(); + +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigiUSB/examples/DigiUSB2LCD/DigiUSB2LCD.ino b/hardware/digistump/avr/libraries/DigiUSB/examples/DigiUSB2LCD/DigiUSB2LCD.ino new file mode 100644 index 0000000..657f46a --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/examples/DigiUSB2LCD/DigiUSB2LCD.ino @@ -0,0 +1,81 @@ +/* USB LCD */ + +//#define DEBUG +#include // I2C Master lib for ATTinys which use USI - comment this out to use with standard arduinos +#include // for LCD w/ GPIO MODIFIED for the ATtiny85 +#include + +#define GPIO_ADDR 0x27 // (PCA8574A A0-A2 @5V) typ. A0-A3 Gnd 0x20 / 0x38 for A - 0x27 is the address of the Digispark LCD modules. +int currentLine = 0; +boolean clearOnNext = 0; +boolean backlight = 1; + +LiquidCrystal_I2C lcd(GPIO_ADDR,16,2); // set address & 16 chars / 2 lines + + +void setup(){ + DigiUSB.begin(); + TinyWireM.begin(); // initialize I2C lib - comment this out to use with standard arduinos + lcd.init(); // initialize the lcd + lcd.backlight(); // Print a message to the LCD. + lcd.setCursor(0, currentLine); +} + + +void get_input() { + + int lastRead; + // when there are no characters to read, or the character isn't a newline + while (1==1) { + if(DigiUSB.available()){ + //something to read + lastRead = DigiUSB.read(); + if(lastRead == '\n'){ + + + if(currentLine > 0) + currentLine = 0; + else + currentLine = 1; + + clearOnNext = 1; + + lcd.setCursor(0, currentLine); + + } + else if(lastRead == 172){ //not sign "¬" send it with the send program to toggle the backlight + if(backlight){ + lcd.noBacklight(); + backlight = 0; + } + else{ + lcd.backlight(); + backlight = 1; + } + DigiUSB.read(); //read to nothing to get rid of newline that should come after it + + } + else{ + if(clearOnNext){ + lcd.print(" "); //clear a single line + lcd.setCursor(0, currentLine); + clearOnNext=0; + } + lcd.print(char(lastRead)); + } + + + + } + // refresh the usb port + DigiUSB.refresh(); + delay(10); + + } + +} + + +void loop(){ + get_input(); +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigiUSB/examples/Echo/Echo.ino b/hardware/digistump/avr/libraries/DigiUSB/examples/Echo/Echo.ino new file mode 100644 index 0000000..39f8726 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/examples/Echo/Echo.ino @@ -0,0 +1,31 @@ +#include + +void setup() { + DigiUSB.begin(); +} + +void get_input() { + int lastRead; + // when there are no characters to read, or the character isn't a newline + while (true) { // loop forever + if (DigiUSB.available()) { + // something to read + lastRead = DigiUSB.read(); + DigiUSB.write(lastRead); + + if (lastRead == '\n') { + break; // when we get a newline, break out of loop + } + } + + // refresh the usb port for 10 milliseconds + DigiUSB.delay(10); + } +} + +void loop() { + // print output + DigiUSB.println("Waiting for input..."); + // get input + get_input(); +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigiUSB/keywords.txt b/hardware/digistump/avr/libraries/DigiUSB/keywords.txt new file mode 100644 index 0000000..1f5e42b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/keywords.txt @@ -0,0 +1,2 @@ +DigiUSB KEYWORD1 +refresh KEYWORD2 \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigiUSB/libs-device/Readme.txt b/hardware/digistump/avr/libraries/DigiUSB/libs-device/Readme.txt new file mode 100644 index 0000000..76518dc --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/libs-device/Readme.txt @@ -0,0 +1,22 @@ +This is the Readme file for the libs-device directory. This directory contains +code snippets which may be useful for USB device firmware. + + +WHAT IS INCLUDED IN THIS DIRECTORY? +=================================== + +osccal.c and osccal.h + This module contains a function which calibrates the AVR's built-in RC + oscillator based on the USB frame clock. See osccal.h for a documentation + of the API. + +osctune.h + This header file contains a code snippet for usbconfig.h. With this code, + you can keep the AVR's internal RC oscillator in sync with the USB frame + clock. This is a continuous synchronization, not a single calibration at + USB reset as with osccal.c above. Please note that this code works only + if D- is wired to the interrupt, not D+. + +---------------------------------------------------------------------------- +(c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH. +http://www.obdev.at/ diff --git a/hardware/digistump/avr/libraries/DigiUSB/libs-device/osccal.c b/hardware/digistump/avr/libraries/DigiUSB/libs-device/osccal.c new file mode 100644 index 0000000..939d5c3 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/libs-device/osccal.c @@ -0,0 +1,63 @@ +/* Name: osccal.c + * Author: Christian Starkjohann + * Creation Date: 2008-04-10 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osccal.c 762 2009-08-12 17:10:30Z cs $ + */ + +#include + +#ifndef uchar +#define uchar unsigned char +#endif + +/* ------------------------------------------------------------------------- */ +/* ------------------------ Oscillator Calibration ------------------------- */ +/* ------------------------------------------------------------------------- */ + +/* Calibrate the RC oscillator. Our timing reference is the Start Of Frame + * signal (a single SE0 bit) repeating every millisecond immediately after + * a USB RESET. We first do a binary search for the OSCCAL value and then + * optimize this value with a neighboorhod search. + */ +void calibrateOscillator(void) +{ +uchar step = 128; +uchar trialValue = 0, optimumValue; +int x, optimumDev, targetValue = (unsigned)(1499 * (double)F_CPU / 10.5e6 + 0.5); + + /* do a binary search: */ + do{ + OSCCAL = trialValue + step; + x = usbMeasureFrameLength(); /* proportional to current real frequency */ + if(x < targetValue) /* frequency still too low */ + trialValue += step; + step >>= 1; + }while(step > 0); + /* We have a precision of +/- 1 for optimum OSCCAL here */ + /* now do a neighborhood search for optimum value */ + optimumValue = trialValue; + optimumDev = x; /* this is certainly far away from optimum */ + for(OSCCAL = trialValue - 1; OSCCAL <= trialValue + 1; OSCCAL++){ + x = usbMeasureFrameLength() - targetValue; + if(x < 0) + x = -x; + if(x < optimumDev){ + optimumDev = x; + optimumValue = OSCCAL; + } + } + OSCCAL = optimumValue; +} +/* +Note: This calibration algorithm may try OSCCAL values of up to 192 even if +the optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +You may replace this search algorithm with any other algorithm you like if +you have additional constraints such as a maximum CPU clock. +For version 5.x RC oscillators (those with a split range of 2x128 steps, e.g. +ATTiny25, ATTiny45, ATTiny85), it may be useful to search for the optimum in +both regions. +*/ diff --git a/hardware/digistump/avr/libraries/DigiUSB/libs-device/osccal.c.lst b/hardware/digistump/avr/libraries/DigiUSB/libs-device/osccal.c.lst new file mode 100644 index 0000000..336a049 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/libs-device/osccal.c.lst @@ -0,0 +1,106 @@ +GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 1 + + + 1 .file "osccal.c" + 2 __SREG__ = 0x3f + 3 __SP_H__ = 0x3e + 4 __SP_L__ = 0x3d + 5 __CCP__ = 0x34 + 6 __tmp_reg__ = 0 + 7 __zero_reg__ = 1 + 8 .text + 9 .global calibrateOscillator + 10 .type calibrateOscillator, @function + 11 calibrateOscillator: + 12 0000 FF92 push r15 + 13 0002 0F93 push r16 + 14 0004 1F93 push r17 + 15 0006 CF93 push r28 + 16 0008 DF93 push r29 + 17 /* prologue: function */ + 18 /* frame size = 0 */ + 19 000a 80E8 ldi r24,lo8(-128) + 20 000c F82E mov r15,r24 + 21 000e 00E0 ldi r16,lo8(0) + 22 0010 C0E0 ldi r28,lo8(0) + 23 0012 D0E0 ldi r29,hi8(0) + 24 .L4: + 25 0014 102F mov r17,r16 + 26 0016 1F0D add r17,r15 + 27 0018 11BF out 81-32,r17 + 28 001a 00D0 rcall usbMeasureFrameLength + 29 001c 29E0 ldi r18,hi8(2356) + 30 001e 8433 cpi r24,lo8(2356) + 31 0020 9207 cpc r25,r18 + 32 0022 04F0 brlt .L2 + 33 0024 102F mov r17,r16 + 34 .L2: + 35 0026 F694 lsr r15 + 36 0028 2196 adiw r28,1 + 37 002a C830 cpi r28,8 + 38 002c D105 cpc r29,__zero_reg__ + 39 002e 01F0 breq .L3 + 40 0030 012F mov r16,r17 + 41 0032 00C0 rjmp .L4 + 42 .L3: + 43 0034 1150 subi r17,lo8(-(-1)) + 44 0036 11BF out 81-32,r17 + 45 0038 1F5F subi r17,lo8(-(1)) + 46 003a 012F mov r16,r17 + 47 003c EC01 movw r28,r24 + 48 003e 00C0 rjmp .L5 + 49 .L8: + 50 0040 00D0 rcall usbMeasureFrameLength + 51 0042 8453 subi r24,lo8(-(-2356)) + 52 0044 9940 sbci r25,hi8(-(-2356)) + 53 0046 97FF sbrs r25,7 + 54 0048 00C0 rjmp .L6 + 55 004a 9095 com r25 + 56 004c 8195 neg r24 + 57 004e 9F4F sbci r25,lo8(-1) + GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 2 + + + 58 .L6: + 59 0050 8C17 cp r24,r28 + 60 0052 9D07 cpc r25,r29 + 61 0054 04F4 brge .L7 + 62 0056 01B7 in r16,81-32 + 63 0058 EC01 movw r28,r24 + 64 .L7: + 65 005a 81B7 in r24,81-32 + 66 005c 8F5F subi r24,lo8(-(1)) + 67 005e 81BF out 81-32,r24 + 68 .L5: + 69 0060 21B7 in r18,81-32 + 70 0062 30E0 ldi r19,lo8(0) + 71 0064 812F mov r24,r17 + 72 0066 90E0 ldi r25,lo8(0) + 73 0068 0196 adiw r24,1 + 74 006a 8217 cp r24,r18 + 75 006c 9307 cpc r25,r19 + 76 006e 04F4 brge .L8 + 77 0070 01BF out 81-32,r16 + 78 /* epilogue start */ + 79 0072 DF91 pop r29 + 80 0074 CF91 pop r28 + 81 0076 1F91 pop r17 + 82 0078 0F91 pop r16 + 83 007a FF90 pop r15 + 84 007c 0895 ret + 85 .size calibrateOscillator, .-calibrateOscillator + GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 3 + + +DEFINED SYMBOLS + *ABS*:00000000 osccal.c +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:2 *ABS*:0000003f __SREG__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:3 *ABS*:0000003e __SP_H__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:4 *ABS*:0000003d __SP_L__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:5 *ABS*:00000034 __CCP__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:6 *ABS*:00000000 __tmp_reg__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:7 *ABS*:00000001 __zero_reg__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:11 .text:00000000 calibrateOscillator + +UNDEFINED SYMBOLS +usbMeasureFrameLength diff --git a/hardware/digistump/avr/libraries/DigiUSB/libs-device/osccal.h b/hardware/digistump/avr/libraries/DigiUSB/libs-device/osccal.h new file mode 100644 index 0000000..710ce05 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/libs-device/osccal.h @@ -0,0 +1,65 @@ +/* Name: osccal.h + * Author: Christian Starkjohann + * Creation Date: 2008-04-10 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osccal.h 762 2009-08-12 17:10:30Z cs $ + */ + +/* +General Description: +This module contains a function which calibrates the AVR's internal RC +oscillator so that the CPU runs at F_CPU (F_CPU is a macro which must be +defined when the module is compiled, best passed in the compiler command +line). The time reference is the USB frame clock of 1 kHz available +immediately after a USB RESET condition. Timing is done by counting CPU +cycles, so all interrupts must be disabled while the calibration runs. For +low level timing measurements, usbMeasureFrameLength() is called. This +function must be enabled in usbconfig.h by defining +USB_CFG_HAVE_MEASURE_FRAME_LENGTH to 1. It is recommended to call +calibrateOscillator() from the reset hook in usbconfig.h: +*/ + +#ifndef __ASSEMBLER__ +#include // for sei() +extern void calibrateOscillator(void); +#endif +#define USB_RESET_HOOK(resetStarts) if(!resetStarts){cli(); calibrateOscillator(); sei();} + +/* +This routine is an alternative to the continuous synchronization described +in osctune.h. + +Algorithm used: +calibrateOscillator() first does a binary search in the OSCCAL register for +the best matching oscillator frequency. Then it does a next neighbor search +to find the value with the lowest clock rate deviation. It is guaranteed to +find the best match among neighboring values, but for version 5 oscillators +(which have a discontinuous relationship between OSCCAL and frequency) a +better match might be available in another OSCCAL region. + +Limitations: +This calibration algorithm may try OSCCAL values of up to 192 even if the +optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +Precision depends on the OSCCAL vs. frequency dependency of the oscillator. +Typical precision for an ATMega168 (derived from the OSCCAL vs. F_RC diagram +in the data sheet) should be in the range of 0.4%. Only the 12.8 MHz and +16.5 MHz versions of V-USB (with built-in receiver PLL) can tolerate this +deviation! All other frequency modules require at least 0.2% precision. +*/ + +#ifndef __OSCCAL_H_INCLUDED__ +#define __OSCCAL_H_INCLUDED__ + +//void calibrateOscillator(void); +/* This function calibrates the RC oscillator so that the CPU runs at F_CPU. + * It MUST be called immediately after the end of a USB RESET condition! + * Disable all interrupts during the call! + * It is recommended that you store the resulting value in EEPROM so that a + * good guess value is available after the next reset. + */ + + +#endif /* __OSCCAL_H_INCLUDED__ */ diff --git a/hardware/digistump/avr/libraries/DigiUSB/libs-device/osccal.o b/hardware/digistump/avr/libraries/DigiUSB/libs-device/osccal.o new file mode 100644 index 0000000..08e2187 Binary files /dev/null and b/hardware/digistump/avr/libraries/DigiUSB/libs-device/osccal.o differ diff --git a/hardware/digistump/avr/libraries/DigiUSB/libs-device/osctune.h b/hardware/digistump/avr/libraries/DigiUSB/libs-device/osctune.h new file mode 100644 index 0000000..c751648 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/libs-device/osctune.h @@ -0,0 +1,88 @@ +/* Name: osctune.h + * Author: Christian Starkjohann + * Creation Date: 2008-10-18 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osctune.h 692 2008-11-07 15:07:40Z cs $ + */ + +/* +General Description: +This file is declared as C-header file although it is mostly documentation +how the RC oscillator can be kept in sync to the USB frame rate. The code +shown here must be added to usbconfig.h or this header file is included from +there. This code works only if D- is wired to the interrupt, not D+!!! + +This is an alternative to the osccal routine in osccal.c. It has the advantage +that the synchronization is done continuously and that it has more compact +code size. The disadvantages are slow synchronization (it may take a while +until the driver works), that messages immediately after the SOF pulse may be +lost (and need to be retried by the host) and that the interrupt is on D- +contrary to most examples. + +You may want to store a good calibration value in EEPROM for the next startup. +You know that the calibration value is good when the first USB message is +received. Do not store the value on every received message because the EEPROM +has a limited endurance. + +Notes: +(*) You must declare the global character variable "lastTimer0Value" in your +main code. + +(*) Timer 0 must be free running (not written by your code) and the prescaling +must be consistent with the TIMER0_PRESCALING define. + +(*) Good values for Timer 0 prescaling depend on how precise the clock must +be tuned and how far away from the default clock rate the target clock is. +For precise tuning, choose a low prescaler factor, for a broad range of tuning +choose a high one. A prescaler factor of 64 is good for the entire OSCCAL +range and allows a precision of better than +/-1%. A prescaler factor of 8 +allows tuning to slightly more than +/-6% of the default frequency and is +more precise than one step of OSCCAL. It is therefore not suitable to tune an +8 MHz oscillator to 12.5 MHz. + +Thanks to Henrik Haftmann for the idea to this routine! +*/ + +#define TIMER0_PRESCALING 64 /* must match the configuration for TIMER0 in main */ +#define TOLERATED_DEVIATION_PPT 5 /* max clock deviation before we tune in 1/10 % */ +/* derived constants: */ +#define EXPECTED_TIMER0_INCREMENT ((F_CPU / (1000 * TIMER0_PRESCALING)) & 0xff) +#define TOLERATED_DEVIATION (TOLERATED_DEVIATION_PPT * F_CPU / (1000000 * TIMER0_PRESCALING)) + +#ifdef __ASSEMBLER__ +macro tuneOsccal + push YH ;[0] + in YL, TCNT0 ;[2] + lds YH, lastTimer0Value ;[3] + sts lastTimer0Value, YL ;[5] + sub YL, YH ;[7] time passed since last frame + subi YL, EXPECTED_TIMER0_INCREMENT ;[8] +#if OSCCAL > 0x3f /* outside I/O addressable range */ + lds YH, OSCCAL ;[6] +#else + in YH, OSCCAL ;[6] assembler modle uses __SFR_OFFSET == 0 +#endif + cpi YL, TOLERATED_DEVIATION + 1 ;[10] + brmi notTooHigh ;[11] + subi YH, 1 ;[12] clock rate was too high +; brcs tuningOverflow ; optionally check for overflow + rjmp osctuneDone ;[13] +notTooHigh: + cpi YL, -TOLERATED_DEVIATION ;[13] + brpl osctuneDone ;[14] not too low + inc YH ;[15] clock rate was too low +; breq tuningOverflow ; optionally check for overflow +osctuneDone: +#if OSCCAL > 0x3f /* outside I/O addressable range */ + sts OSCCAL, YH ;[12-13] store tuned value +#else + out OSCCAL, YH ;[12-13] store tuned value +#endif +tuningOverflow: + pop YH ;[17] + endm ;[19] max number of cycles +#endif + +#define USB_SOF_HOOK tuneOsccal diff --git a/hardware/digistump/avr/libraries/DigiUSB/oddebug.c b/hardware/digistump/avr/libraries/DigiUSB/oddebug.c new file mode 100644 index 0000000..945457c --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/oddebug.c @@ -0,0 +1,50 @@ +/* Name: oddebug.c + * Project: AVR library + * Author: Christian Starkjohann + * Creation Date: 2005-01-16 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: oddebug.c 692 2008-11-07 15:07:40Z cs $ + */ + +#include "oddebug.h" + +#if DEBUG_LEVEL > 0 + +#warning "Never compile production devices with debugging enabled" + +static void uartPutc(char c) +{ + while(!(ODDBG_USR & (1 << ODDBG_UDRE))); /* wait for data register empty */ + ODDBG_UDR = c; +} + +static uchar hexAscii(uchar h) +{ + h &= 0xf; + if(h >= 10) + h += 'a' - (uchar)10 - '0'; + h += '0'; + return h; +} + +static void printHex(uchar c) +{ + uartPutc(hexAscii(c >> 4)); + uartPutc(hexAscii(c)); +} + +void odDebug(uchar prefix, uchar *data, uchar len) +{ + printHex(prefix); + uartPutc(':'); + while(len--){ + uartPutc(' '); + printHex(*data++); + } + uartPutc('\r'); + uartPutc('\n'); +} + +#endif diff --git a/hardware/digistump/avr/libraries/DigiUSB/oddebug.h b/hardware/digistump/avr/libraries/DigiUSB/oddebug.h new file mode 100644 index 0000000..d61309d --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/oddebug.h @@ -0,0 +1,123 @@ +/* Name: oddebug.h + * Project: AVR library + * Author: Christian Starkjohann + * Creation Date: 2005-01-16 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: oddebug.h 692 2008-11-07 15:07:40Z cs $ + */ + +#ifndef __oddebug_h_included__ +#define __oddebug_h_included__ + +/* +General Description: +This module implements a function for debug logs on the serial line of the +AVR microcontroller. Debugging can be configured with the define +'DEBUG_LEVEL'. If this macro is not defined or defined to 0, all debugging +calls are no-ops. If it is 1, DBG1 logs will appear, but not DBG2. If it is +2, DBG1 and DBG2 logs will be printed. + +A debug log consists of a label ('prefix') to indicate which debug log created +the output and a memory block to dump in hex ('data' and 'len'). +*/ + + +#ifndef F_CPU +# define F_CPU 12000000 /* 12 MHz */ +#endif + +/* make sure we have the UART defines: */ +#include "usbportability.h" + +#ifndef uchar +# define uchar unsigned char +#endif + +#if DEBUG_LEVEL > 0 && !(defined TXEN || defined TXEN0) /* no UART in device */ +# warning "Debugging disabled because device has no UART" +# undef DEBUG_LEVEL +#endif + +#ifndef DEBUG_LEVEL +# define DEBUG_LEVEL 0 +#endif + +/* ------------------------------------------------------------------------- */ + +#if DEBUG_LEVEL > 0 +# define DBG1(prefix, data, len) odDebug(prefix, data, len) +#else +# define DBG1(prefix, data, len) +#endif + +#if DEBUG_LEVEL > 1 +# define DBG2(prefix, data, len) odDebug(prefix, data, len) +#else +# define DBG2(prefix, data, len) +#endif + +/* ------------------------------------------------------------------------- */ + +#if DEBUG_LEVEL > 0 +extern void odDebug(uchar prefix, uchar *data, uchar len); + +/* Try to find our control registers; ATMEL likes to rename these */ + +#if defined UBRR +# define ODDBG_UBRR UBRR +#elif defined UBRRL +# define ODDBG_UBRR UBRRL +#elif defined UBRR0 +# define ODDBG_UBRR UBRR0 +#elif defined UBRR0L +# define ODDBG_UBRR UBRR0L +#endif + +#if defined UCR +# define ODDBG_UCR UCR +#elif defined UCSRB +# define ODDBG_UCR UCSRB +#elif defined UCSR0B +# define ODDBG_UCR UCSR0B +#endif + +#if defined TXEN +# define ODDBG_TXEN TXEN +#else +# define ODDBG_TXEN TXEN0 +#endif + +#if defined USR +# define ODDBG_USR USR +#elif defined UCSRA +# define ODDBG_USR UCSRA +#elif defined UCSR0A +# define ODDBG_USR UCSR0A +#endif + +#if defined UDRE +# define ODDBG_UDRE UDRE +#else +# define ODDBG_UDRE UDRE0 +#endif + +#if defined UDR +# define ODDBG_UDR UDR +#elif defined UDR0 +# define ODDBG_UDR UDR0 +#endif + +static inline void odDebugInit(void) +{ + ODDBG_UCR |= (1< + +#ifndef uchar +#define uchar unsigned char +#endif + +/* ------------------------------------------------------------------------- */ +/* ------------------------ Oscillator Calibration ------------------------- */ +/* ------------------------------------------------------------------------- */ + +/* Calibrate the RC oscillator. Our timing reference is the Start Of Frame + * signal (a single SE0 bit) repeating every millisecond immediately after + * a USB RESET. We first do a binary search for the OSCCAL value and then + * optimize this value with a neighboorhod search. + */ +void calibrateOscillator(void) +{ +uchar step = 128; +uchar trialValue = 0, optimumValue; +int x, optimumDev, targetValue = (unsigned)(1499 * (double)F_CPU / 10.5e6 + 0.5); + + /* do a binary search: */ + do{ + OSCCAL = trialValue + step; + x = usbMeasureFrameLength(); /* proportional to current real frequency */ + if(x < targetValue) /* frequency still too low */ + trialValue += step; + step >>= 1; + }while(step > 0); + /* We have a precision of +/- 1 for optimum OSCCAL here */ + /* now do a neighborhood search for optimum value */ + optimumValue = trialValue; + optimumDev = x; /* this is certainly far away from optimum */ + for(OSCCAL = trialValue - 1; OSCCAL <= trialValue + 1; OSCCAL++){ + x = usbMeasureFrameLength() - targetValue; + if(x < 0) + x = -x; + if(x < optimumDev){ + optimumDev = x; + optimumValue = OSCCAL; + } + } + OSCCAL = optimumValue; +} +/* +Note: This calibration algorithm may try OSCCAL values of up to 192 even if +the optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +You may replace this search algorithm with any other algorithm you like if +you have additional constraints such as a maximum CPU clock. +For version 5.x RC oscillators (those with a split range of 2x128 steps, e.g. +ATTiny25, ATTiny45, ATTiny85), it may be useful to search for the optimum in +both regions. +*/ diff --git a/hardware/digistump/avr/libraries/DigiUSB/osccal.c.lst b/hardware/digistump/avr/libraries/DigiUSB/osccal.c.lst new file mode 100644 index 0000000..336a049 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/osccal.c.lst @@ -0,0 +1,106 @@ +GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 1 + + + 1 .file "osccal.c" + 2 __SREG__ = 0x3f + 3 __SP_H__ = 0x3e + 4 __SP_L__ = 0x3d + 5 __CCP__ = 0x34 + 6 __tmp_reg__ = 0 + 7 __zero_reg__ = 1 + 8 .text + 9 .global calibrateOscillator + 10 .type calibrateOscillator, @function + 11 calibrateOscillator: + 12 0000 FF92 push r15 + 13 0002 0F93 push r16 + 14 0004 1F93 push r17 + 15 0006 CF93 push r28 + 16 0008 DF93 push r29 + 17 /* prologue: function */ + 18 /* frame size = 0 */ + 19 000a 80E8 ldi r24,lo8(-128) + 20 000c F82E mov r15,r24 + 21 000e 00E0 ldi r16,lo8(0) + 22 0010 C0E0 ldi r28,lo8(0) + 23 0012 D0E0 ldi r29,hi8(0) + 24 .L4: + 25 0014 102F mov r17,r16 + 26 0016 1F0D add r17,r15 + 27 0018 11BF out 81-32,r17 + 28 001a 00D0 rcall usbMeasureFrameLength + 29 001c 29E0 ldi r18,hi8(2356) + 30 001e 8433 cpi r24,lo8(2356) + 31 0020 9207 cpc r25,r18 + 32 0022 04F0 brlt .L2 + 33 0024 102F mov r17,r16 + 34 .L2: + 35 0026 F694 lsr r15 + 36 0028 2196 adiw r28,1 + 37 002a C830 cpi r28,8 + 38 002c D105 cpc r29,__zero_reg__ + 39 002e 01F0 breq .L3 + 40 0030 012F mov r16,r17 + 41 0032 00C0 rjmp .L4 + 42 .L3: + 43 0034 1150 subi r17,lo8(-(-1)) + 44 0036 11BF out 81-32,r17 + 45 0038 1F5F subi r17,lo8(-(1)) + 46 003a 012F mov r16,r17 + 47 003c EC01 movw r28,r24 + 48 003e 00C0 rjmp .L5 + 49 .L8: + 50 0040 00D0 rcall usbMeasureFrameLength + 51 0042 8453 subi r24,lo8(-(-2356)) + 52 0044 9940 sbci r25,hi8(-(-2356)) + 53 0046 97FF sbrs r25,7 + 54 0048 00C0 rjmp .L6 + 55 004a 9095 com r25 + 56 004c 8195 neg r24 + 57 004e 9F4F sbci r25,lo8(-1) + GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 2 + + + 58 .L6: + 59 0050 8C17 cp r24,r28 + 60 0052 9D07 cpc r25,r29 + 61 0054 04F4 brge .L7 + 62 0056 01B7 in r16,81-32 + 63 0058 EC01 movw r28,r24 + 64 .L7: + 65 005a 81B7 in r24,81-32 + 66 005c 8F5F subi r24,lo8(-(1)) + 67 005e 81BF out 81-32,r24 + 68 .L5: + 69 0060 21B7 in r18,81-32 + 70 0062 30E0 ldi r19,lo8(0) + 71 0064 812F mov r24,r17 + 72 0066 90E0 ldi r25,lo8(0) + 73 0068 0196 adiw r24,1 + 74 006a 8217 cp r24,r18 + 75 006c 9307 cpc r25,r19 + 76 006e 04F4 brge .L8 + 77 0070 01BF out 81-32,r16 + 78 /* epilogue start */ + 79 0072 DF91 pop r29 + 80 0074 CF91 pop r28 + 81 0076 1F91 pop r17 + 82 0078 0F91 pop r16 + 83 007a FF90 pop r15 + 84 007c 0895 ret + 85 .size calibrateOscillator, .-calibrateOscillator + GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 3 + + +DEFINED SYMBOLS + *ABS*:00000000 osccal.c +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:2 *ABS*:0000003f __SREG__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:3 *ABS*:0000003e __SP_H__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:4 *ABS*:0000003d __SP_L__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:5 *ABS*:00000034 __CCP__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:6 *ABS*:00000000 __tmp_reg__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:7 *ABS*:00000001 __zero_reg__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:11 .text:00000000 calibrateOscillator + +UNDEFINED SYMBOLS +usbMeasureFrameLength diff --git a/hardware/digistump/avr/libraries/DigiUSB/osccal.h b/hardware/digistump/avr/libraries/DigiUSB/osccal.h new file mode 100644 index 0000000..710ce05 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/osccal.h @@ -0,0 +1,65 @@ +/* Name: osccal.h + * Author: Christian Starkjohann + * Creation Date: 2008-04-10 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osccal.h 762 2009-08-12 17:10:30Z cs $ + */ + +/* +General Description: +This module contains a function which calibrates the AVR's internal RC +oscillator so that the CPU runs at F_CPU (F_CPU is a macro which must be +defined when the module is compiled, best passed in the compiler command +line). The time reference is the USB frame clock of 1 kHz available +immediately after a USB RESET condition. Timing is done by counting CPU +cycles, so all interrupts must be disabled while the calibration runs. For +low level timing measurements, usbMeasureFrameLength() is called. This +function must be enabled in usbconfig.h by defining +USB_CFG_HAVE_MEASURE_FRAME_LENGTH to 1. It is recommended to call +calibrateOscillator() from the reset hook in usbconfig.h: +*/ + +#ifndef __ASSEMBLER__ +#include // for sei() +extern void calibrateOscillator(void); +#endif +#define USB_RESET_HOOK(resetStarts) if(!resetStarts){cli(); calibrateOscillator(); sei();} + +/* +This routine is an alternative to the continuous synchronization described +in osctune.h. + +Algorithm used: +calibrateOscillator() first does a binary search in the OSCCAL register for +the best matching oscillator frequency. Then it does a next neighbor search +to find the value with the lowest clock rate deviation. It is guaranteed to +find the best match among neighboring values, but for version 5 oscillators +(which have a discontinuous relationship between OSCCAL and frequency) a +better match might be available in another OSCCAL region. + +Limitations: +This calibration algorithm may try OSCCAL values of up to 192 even if the +optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +Precision depends on the OSCCAL vs. frequency dependency of the oscillator. +Typical precision for an ATMega168 (derived from the OSCCAL vs. F_RC diagram +in the data sheet) should be in the range of 0.4%. Only the 12.8 MHz and +16.5 MHz versions of V-USB (with built-in receiver PLL) can tolerate this +deviation! All other frequency modules require at least 0.2% precision. +*/ + +#ifndef __OSCCAL_H_INCLUDED__ +#define __OSCCAL_H_INCLUDED__ + +//void calibrateOscillator(void); +/* This function calibrates the RC oscillator so that the CPU runs at F_CPU. + * It MUST be called immediately after the end of a USB RESET condition! + * Disable all interrupts during the call! + * It is recommended that you store the resulting value in EEPROM so that a + * good guess value is available after the next reset. + */ + + +#endif /* __OSCCAL_H_INCLUDED__ */ diff --git a/hardware/digistump/avr/libraries/DigiUSB/osccal.o b/hardware/digistump/avr/libraries/DigiUSB/osccal.o new file mode 100644 index 0000000..08e2187 Binary files /dev/null and b/hardware/digistump/avr/libraries/DigiUSB/osccal.o differ diff --git a/hardware/digistump/avr/libraries/DigiUSB/osctune.h b/hardware/digistump/avr/libraries/DigiUSB/osctune.h new file mode 100644 index 0000000..c751648 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/osctune.h @@ -0,0 +1,88 @@ +/* Name: osctune.h + * Author: Christian Starkjohann + * Creation Date: 2008-10-18 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osctune.h 692 2008-11-07 15:07:40Z cs $ + */ + +/* +General Description: +This file is declared as C-header file although it is mostly documentation +how the RC oscillator can be kept in sync to the USB frame rate. The code +shown here must be added to usbconfig.h or this header file is included from +there. This code works only if D- is wired to the interrupt, not D+!!! + +This is an alternative to the osccal routine in osccal.c. It has the advantage +that the synchronization is done continuously and that it has more compact +code size. The disadvantages are slow synchronization (it may take a while +until the driver works), that messages immediately after the SOF pulse may be +lost (and need to be retried by the host) and that the interrupt is on D- +contrary to most examples. + +You may want to store a good calibration value in EEPROM for the next startup. +You know that the calibration value is good when the first USB message is +received. Do not store the value on every received message because the EEPROM +has a limited endurance. + +Notes: +(*) You must declare the global character variable "lastTimer0Value" in your +main code. + +(*) Timer 0 must be free running (not written by your code) and the prescaling +must be consistent with the TIMER0_PRESCALING define. + +(*) Good values for Timer 0 prescaling depend on how precise the clock must +be tuned and how far away from the default clock rate the target clock is. +For precise tuning, choose a low prescaler factor, for a broad range of tuning +choose a high one. A prescaler factor of 64 is good for the entire OSCCAL +range and allows a precision of better than +/-1%. A prescaler factor of 8 +allows tuning to slightly more than +/-6% of the default frequency and is +more precise than one step of OSCCAL. It is therefore not suitable to tune an +8 MHz oscillator to 12.5 MHz. + +Thanks to Henrik Haftmann for the idea to this routine! +*/ + +#define TIMER0_PRESCALING 64 /* must match the configuration for TIMER0 in main */ +#define TOLERATED_DEVIATION_PPT 5 /* max clock deviation before we tune in 1/10 % */ +/* derived constants: */ +#define EXPECTED_TIMER0_INCREMENT ((F_CPU / (1000 * TIMER0_PRESCALING)) & 0xff) +#define TOLERATED_DEVIATION (TOLERATED_DEVIATION_PPT * F_CPU / (1000000 * TIMER0_PRESCALING)) + +#ifdef __ASSEMBLER__ +macro tuneOsccal + push YH ;[0] + in YL, TCNT0 ;[2] + lds YH, lastTimer0Value ;[3] + sts lastTimer0Value, YL ;[5] + sub YL, YH ;[7] time passed since last frame + subi YL, EXPECTED_TIMER0_INCREMENT ;[8] +#if OSCCAL > 0x3f /* outside I/O addressable range */ + lds YH, OSCCAL ;[6] +#else + in YH, OSCCAL ;[6] assembler modle uses __SFR_OFFSET == 0 +#endif + cpi YL, TOLERATED_DEVIATION + 1 ;[10] + brmi notTooHigh ;[11] + subi YH, 1 ;[12] clock rate was too high +; brcs tuningOverflow ; optionally check for overflow + rjmp osctuneDone ;[13] +notTooHigh: + cpi YL, -TOLERATED_DEVIATION ;[13] + brpl osctuneDone ;[14] not too low + inc YH ;[15] clock rate was too low +; breq tuningOverflow ; optionally check for overflow +osctuneDone: +#if OSCCAL > 0x3f /* outside I/O addressable range */ + sts OSCCAL, YH ;[12-13] store tuned value +#else + out OSCCAL, YH ;[12-13] store tuned value +#endif +tuningOverflow: + pop YH ;[17] + endm ;[19] max number of cycles +#endif + +#define USB_SOF_HOOK tuneOsccal diff --git a/hardware/digistump/avr/libraries/DigiUSB/rx_buffer.h b/hardware/digistump/avr/libraries/DigiUSB/rx_buffer.h new file mode 100644 index 0000000..274793c --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/rx_buffer.h @@ -0,0 +1,14 @@ +#ifndef __rx_buffer_h__ +#define __rx_buffer_h__ + +#ifdef __cplusplus +extern "C"{ +#endif + uchar rx_buffer[8]; // Buffer 8 bytes + extern int rx_read_offset; // = -1; + extern int rx_write_offset; // = 0; +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // __rx_buffer_h__ diff --git a/hardware/digistump/avr/libraries/DigiUSB/usbconfig-prototype.h b/hardware/digistump/avr/libraries/DigiUSB/usbconfig-prototype.h new file mode 100644 index 0000000..a0fd1bf --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/usbconfig-prototype.h @@ -0,0 +1,369 @@ +/* Name: usbconfig.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2005-04-01 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbconfig-prototype.h 767 2009-08-22 11:39:22Z cs $ + */ + +#ifndef __usbconfig_h_included__ +#define __usbconfig_h_included__ + +/* +General Description: +This file is an example configuration (with inline documentation) for the USB +driver. It configures V-USB for USB D+ connected to Port D bit 2 (which is +also hardware interrupt 0 on many devices) and USB D- to Port D bit 4. You may +wire the lines to any other port, as long as D+ is also wired to INT0 (or any +other hardware interrupt, as long as it is the highest level interrupt, see +section at the end of this file). ++ To create your own usbconfig.h file, copy this file to your project's ++ firmware source directory) and rename it to "usbconfig.h". ++ Then edit it accordingly. +*/ + +/* ---------------------------- Hardware Config ---------------------------- */ + +#define USB_CFG_IOPORTNAME D +/* This is the port where the USB bus is connected. When you configure it to + * "B", the registers PORTB, PINB and DDRB will be used. + */ +#define USB_CFG_DMINUS_BIT 4 +/* This is the bit number in USB_CFG_IOPORT where the USB D- line is connected. + * This may be any bit in the port. + */ +#define USB_CFG_DPLUS_BIT 2 +/* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected. + * This may be any bit in the port. Please note that D+ must also be connected + * to interrupt pin INT0! [You can also use other interrupts, see section + * "Optional MCU Description" below, or you can connect D- to the interrupt, as + * it is required if you use the USB_COUNT_SOF feature. If you use D- for the + * interrupt, the USB interrupt will also be triggered at Start-Of-Frame + * markers every millisecond.] + */ +#define USB_CFG_CLOCK_KHZ (F_CPU/1000) +/* Clock rate of the AVR in kHz. Legal values are 12000, 12800, 15000, 16000, + * 16500 and 20000. The 12.8 MHz and 16.5 MHz versions of the code require no + * crystal, they tolerate +/- 1% deviation from the nominal frequency. All + * other rates require a precision of 2000 ppm and thus a crystal! + * Default if not specified: 12 MHz + */ +#define USB_CFG_CHECK_CRC 0 +/* Define this to 1 if you want that the driver checks integrity of incoming + * data packets (CRC checks). CRC checks cost quite a bit of code size and are + * currently only available for 18 MHz crystal clock. You must choose + * USB_CFG_CLOCK_KHZ = 18000 if you enable this option. + */ + +/* ----------------------- Optional Hardware Config ------------------------ */ + +/* #define USB_CFG_PULLUP_IOPORTNAME D */ +/* If you connect the 1.5k pullup resistor from D- to a port pin instead of + * V+, you can connect and disconnect the device from firmware by calling + * the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h). + * This constant defines the port on which the pullup resistor is connected. + */ +/* #define USB_CFG_PULLUP_BIT 4 */ +/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined + * above) where the 1.5k pullup resistor is connected. See description + * above for details. + */ + +/* --------------------------- Functional Range ---------------------------- */ + +#define USB_CFG_HAVE_INTRIN_ENDPOINT 0 +/* Define this to 1 if you want to compile a version with two endpoints: The + * default control endpoint 0 and an interrupt-in endpoint (any other endpoint + * number). + */ +#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0 +/* Define this to 1 if you want to compile a version with three endpoints: The + * default control endpoint 0, an interrupt-in endpoint 3 (or the number + * configured below) and a catch-all default interrupt-in endpoint as above. + * You must also define USB_CFG_HAVE_INTRIN_ENDPOINT to 1 for this feature. + */ +#define USB_CFG_EP3_NUMBER 3 +/* If the so-called endpoint 3 is used, it can now be configured to any other + * endpoint number (except 0) with this macro. Default if undefined is 3. + */ +/* #define USB_INITIAL_DATATOKEN USBPID_DATA1 */ +/* The above macro defines the startup condition for data toggling on the + * interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA1. + * Since the token is toggled BEFORE sending any data, the first packet is + * sent with the oposite value of this configuration! + */ +#define USB_CFG_IMPLEMENT_HALT 0 +/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature + * for endpoint 1 (interrupt endpoint). Although you may not need this feature, + * it is required by the standard. We have made it a config option because it + * bloats the code considerably. + */ +#define USB_CFG_SUPPRESS_INTR_CODE 0 +/* Define this to 1 if you want to declare interrupt-in endpoints, but don't + * want to send any data over them. If this macro is defined to 1, functions + * usbSetInterrupt() and usbSetInterrupt3() are omitted. This is useful if + * you need the interrupt-in endpoints in order to comply to an interface + * (e.g. HID), but never want to send any data. This option saves a couple + * of bytes in flash memory and the transmit buffers in RAM. + */ +#define USB_CFG_INTR_POLL_INTERVAL 10 +/* If you compile a version with endpoint 1 (interrupt-in), this is the poll + * interval. The value is in milliseconds and must not be less than 10 ms for + * low speed devices. + */ +#define USB_CFG_IS_SELF_POWERED 0 +/* Define this to 1 if the device has its own power supply. Set it to 0 if the + * device is powered from the USB bus. + */ +#define USB_CFG_MAX_BUS_POWER 100 +/* Set this variable to the maximum USB bus power consumption of your device. + * The value is in milliamperes. [It will be divided by two since USB + * communicates power requirements in units of 2 mA.] + */ +#define USB_CFG_IMPLEMENT_FN_WRITE 0 +/* Set this to 1 if you want usbFunctionWrite() to be called for control-out + * transfers. Set it to 0 if you don't need it and want to save a couple of + * bytes. + */ +#define USB_CFG_IMPLEMENT_FN_READ 0 +/* Set this to 1 if you need to send control replies which are generated + * "on the fly" when usbFunctionRead() is called. If you only want to send + * data from a static buffer, set it to 0 and return the data from + * usbFunctionSetup(). This saves a couple of bytes. + */ +#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0 +/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints. + * You must implement the function usbFunctionWriteOut() which receives all + * interrupt/bulk data sent to any endpoint other than 0. The endpoint number + * can be found in 'usbRxToken'. + */ +#define USB_CFG_HAVE_FLOWCONTROL 0 +/* Define this to 1 if you want flowcontrol over USB data. See the definition + * of the macros usbDisableAllRequests() and usbEnableAllRequests() in + * usbdrv.h. + */ +#define USB_CFG_LONG_TRANSFERS 0 +/* Define this to 1 if you want to send/receive blocks of more than 254 bytes + * in a single control-in or control-out transfer. Note that the capability + * for long transfers increases the driver size. + */ +/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */ +/* This macro is a hook if you want to do unconventional things. If it is + * defined, it's inserted at the beginning of received message processing. + * If you eat the received message and don't want default processing to + * proceed, do a return after doing your things. One possible application + * (besides debugging) is to flash a status LED on each packet. + */ +/* #define USB_RESET_HOOK(resetStarts) if(!resetStarts){hadUsbReset();} */ +/* This macro is a hook if you need to know when an USB RESET occurs. It has + * one parameter which distinguishes between the start of RESET state and its + * end. + */ +/* #define USB_SET_ADDRESS_HOOK() hadAddressAssigned(); */ +/* This macro (if defined) is executed when a USB SET_ADDRESS request was + * received. + */ +#define USB_COUNT_SOF 0 +/* define this macro to 1 if you need the global variable "usbSofCount" which + * counts SOF packets. This feature requires that the hardware interrupt is + * connected to D- instead of D+. + */ +/* #ifdef __ASSEMBLER__ + * macro myAssemblerMacro + * in YL, TCNT0 + * sts timer0Snapshot, YL + * endm + * #endif + * #define USB_SOF_HOOK myAssemblerMacro + * This macro (if defined) is executed in the assembler module when a + * Start Of Frame condition is detected. It is recommended to define it to + * the name of an assembler macro which is defined here as well so that more + * than one assembler instruction can be used. The macro may use the register + * YL and modify SREG. If it lasts longer than a couple of cycles, USB messages + * immediately after an SOF pulse may be lost and must be retried by the host. + * What can you do with this hook? Since the SOF signal occurs exactly every + * 1 ms (unless the host is in sleep mode), you can use it to tune OSCCAL in + * designs running on the internal RC oscillator. + * Please note that Start Of Frame detection works only if D- is wired to the + * interrupt, not D+. THIS IS DIFFERENT THAN MOST EXAMPLES! + */ +#define USB_CFG_CHECK_DATA_TOGGLING 0 +/* define this macro to 1 if you want to filter out duplicate data packets + * sent by the host. Duplicates occur only as a consequence of communication + * errors, when the host does not receive an ACK. Please note that you need to + * implement the filtering yourself in usbFunctionWriteOut() and + * usbFunctionWrite(). Use the global usbCurrentDataToken and a static variable + * for each control- and out-endpoint to check for duplicate packets. + */ +#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 0 +/* define this macro to 1 if you want the function usbMeasureFrameLength() + * compiled in. This function can be used to calibrate the AVR's RC oscillator. + */ +#define USB_USE_FAST_CRC 0 +/* The assembler module has two implementations for the CRC algorithm. One is + * faster, the other is smaller. This CRC routine is only used for transmitted + * messages where timing is not critical. The faster routine needs 31 cycles + * per byte while the smaller one needs 61 to 69 cycles. The faster routine + * may be worth the 32 bytes bigger code size if you transmit lots of data and + * run the AVR close to its limit. + */ + +/* -------------------------- Device Description --------------------------- */ + +#define USB_CFG_VENDOR_ID 0xc0, 0x16 /* = 0x16c0 = 5824 = voti.nl */ +/* USB vendor ID for the device, low byte first. If you have registered your + * own Vendor ID, define it here. Otherwise you may use one of obdev's free + * shared VID/PID pairs. Be sure to read USB-IDs-for-free.txt for rules! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_ID 0xdc, 0x05 /* = 0x05dc = 1500 */ +/* This is the ID of the product, low byte first. It is interpreted in the + * scope of the vendor ID. If you have registered your own VID with usb.org + * or if you have licensed a PID from somebody else, define it here. Otherwise + * you may use one of obdev's free shared VID/PID pairs. See the file + * USB-IDs-for-free.txt for details! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_VERSION 0x00, 0x01 +/* Version number of the device: Minor number first, then major number. + */ +#define USB_CFG_VENDOR_NAME 'o', 'b', 'd', 'e', 'v', '.', 'a', 't' +#define USB_CFG_VENDOR_NAME_LEN 8 +/* These two values define the vendor name returned by the USB device. The name + * must be given as a list of characters under single quotes. The characters + * are interpreted as Unicode (UTF-16) entities. + * If you don't want a vendor name string, undefine these macros. + * ALWAYS define a vendor name containing your Internet domain name if you use + * obdev's free shared VID/PID pair. See the file USB-IDs-for-free.txt for + * details. + */ +#define USB_CFG_DEVICE_NAME 'T', 'e', 'm', 'p', 'l', 'a', 't', 'e' +#define USB_CFG_DEVICE_NAME_LEN 8 +/* Same as above for the device name. If you don't want a device name, undefine + * the macros. See the file USB-IDs-for-free.txt before you assign a name if + * you use a shared VID/PID. + */ +/*#define USB_CFG_SERIAL_NUMBER 'N', 'o', 'n', 'e' */ +/*#define USB_CFG_SERIAL_NUMBER_LEN 0 */ +/* Same as above for the serial number. If you don't want a serial number, + * undefine the macros. + * It may be useful to provide the serial number through other means than at + * compile time. See the section about descriptor properties below for how + * to fine tune control over USB descriptors such as the string descriptor + * for the serial number. + */ +#define USB_CFG_DEVICE_CLASS 0xff /* set to 0 if deferred to interface */ +#define USB_CFG_DEVICE_SUBCLASS 0 +/* See USB specification if you want to conform to an existing device class. + * Class 0xff is "vendor specific". + */ +#define USB_CFG_INTERFACE_CLASS 0 /* define class here if not at device level */ +#define USB_CFG_INTERFACE_SUBCLASS 0 +#define USB_CFG_INTERFACE_PROTOCOL 0 +/* See USB specification if you want to conform to an existing device class or + * protocol. The following classes must be set at interface level: + * HID class is 3, no subclass and protocol required (but may be useful!) + * CDC class is 2, use subclass 2 and protocol 1 for ACM + */ +/* #define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 42 */ +/* Define this to the length of the HID report descriptor, if you implement + * an HID device. Otherwise don't define it or define it to 0. + * If you use this define, you must add a PROGMEM character array named + * "usbHidReportDescriptor" to your code which contains the report descriptor. + * Don't forget to keep the array and this define in sync! + */ + +/* #define USB_PUBLIC static */ +/* Use the define above if you #include usbdrv.c instead of linking against it. + * This technique saves a couple of bytes in flash memory. + */ + +/* ------------------- Fine Control over USB Descriptors ------------------- */ +/* If you don't want to use the driver's default USB descriptors, you can + * provide our own. These can be provided as (1) fixed length static data in + * flash memory, (2) fixed length static data in RAM or (3) dynamically at + * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more + * information about this function. + * Descriptor handling is configured through the descriptor's properties. If + * no properties are defined or if they are 0, the default descriptor is used. + * Possible properties are: + * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched + * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is + * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if + * you want RAM pointers. + * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found + * in static memory is in RAM, not in flash memory. + * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash), + * the driver must know the descriptor's length. The descriptor itself is + * found at the address of a well known identifier (see below). + * List of static descriptor names (must be declared PROGMEM if in flash): + * char usbDescriptorDevice[]; + * char usbDescriptorConfiguration[]; + * char usbDescriptorHidReport[]; + * char usbDescriptorString0[]; + * int usbDescriptorStringVendor[]; + * int usbDescriptorStringDevice[]; + * int usbDescriptorStringSerialNumber[]; + * Other descriptors can't be provided statically, they must be provided + * dynamically at runtime. + * + * Descriptor properties are or-ed or added together, e.g.: + * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18)) + * + * The following descriptors are defined: + * USB_CFG_DESCR_PROPS_DEVICE + * USB_CFG_DESCR_PROPS_CONFIGURATION + * USB_CFG_DESCR_PROPS_STRINGS + * USB_CFG_DESCR_PROPS_STRING_0 + * USB_CFG_DESCR_PROPS_STRING_VENDOR + * USB_CFG_DESCR_PROPS_STRING_PRODUCT + * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER + * USB_CFG_DESCR_PROPS_HID + * USB_CFG_DESCR_PROPS_HID_REPORT + * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver) + * + * Note about string descriptors: String descriptors are not just strings, they + * are Unicode strings prefixed with a 2 byte header. Example: + * int serialNumberDescriptor[] = { + * USB_STRING_DESCRIPTOR_HEADER(6), + * 'S', 'e', 'r', 'i', 'a', 'l' + * }; + */ + +#define USB_CFG_DESCR_PROPS_DEVICE 0 +#define USB_CFG_DESCR_PROPS_CONFIGURATION 0 +#define USB_CFG_DESCR_PROPS_STRINGS 0 +#define USB_CFG_DESCR_PROPS_STRING_0 0 +#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0 +#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0 +#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0 +#define USB_CFG_DESCR_PROPS_HID 0 +#define USB_CFG_DESCR_PROPS_HID_REPORT 0 +#define USB_CFG_DESCR_PROPS_UNKNOWN 0 + +/* ----------------------- Optional MCU Description ------------------------ */ + +/* The following configurations have working defaults in usbdrv.h. You + * usually don't need to set them explicitly. Only if you want to run + * the driver on a device which is not yet supported or with a compiler + * which is not fully supported (such as IAR C) or if you use a differnt + * interrupt than INT0, you may have to define some of these. + */ +/* #define USB_INTR_CFG MCUCR */ +/* #define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) */ +/* #define USB_INTR_CFG_CLR 0 */ +/* #define USB_INTR_ENABLE GIMSK */ +/* #define USB_INTR_ENABLE_BIT INT0 */ +/* #define USB_INTR_PENDING GIFR */ +/* #define USB_INTR_PENDING_BIT INTF0 */ +/* #define USB_INTR_VECTOR SIG_INTERRUPT0 */ + +#endif /* __usbconfig_h_included__ */ diff --git a/hardware/digistump/avr/libraries/DigiUSB/usbconfig.h b/hardware/digistump/avr/libraries/DigiUSB/usbconfig.h new file mode 100644 index 0000000..d11b5ad --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/usbconfig.h @@ -0,0 +1,393 @@ +/* Name: usbconfig.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2005-04-01 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbconfig-prototype.h 767 2009-08-22 11:39:22Z cs $ + */ + +#ifndef __usbconfig_h_included__ +#define __usbconfig_h_included__ + +/* +General Description: +This file is an example configuration (with inline documentation) for the USB +driver. It configures V-USB for USB D+ connected to Port D bit 2 (which is +also hardware interrupt 0 on many devices) and USB D- to Port D bit 4. You may +wire the lines to any other port, as long as D+ is also wired to INT0 (or any +other hardware interrupt, as long as it is the highest level interrupt, see +section at the end of this file). ++ To create your own usbconfig.h file, copy this file to your project's ++ firmware source directory) and rename it to "usbconfig.h". ++ Then edit it accordingly. +*/ + +/* ---------------------------- Hardware Config ---------------------------- */ + +#if defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 1 +#define USB_CFG_DPLUS_BIT 2 + +#elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 4 + +#elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 6 + +#elif defined (__AVR_ATtiny461__) || defined (__AVR_ATtiny861__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 5 +#define USB_CFG_DPLUS_BIT 6 +#else +/* ATtiny2313, ATmega8/48/88/168 */ +#define USB_CFG_IOPORTNAME D +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 2 +#endif +#define USB_CFG_CLOCK_KHZ (F_CPU/1000) +/* Clock rate of the AVR in kHz. Legal values are 12000, 12800, 15000, 16000, + * 16500 and 20000. The 12.8 MHz and 16.5 MHz versions of the code require no + * crystal, they tolerate +/- 1% deviation from the nominal frequency. All + * other rates require a precision of 2000 ppm and thus a crystal! + * Default if not specified: 12 MHz + */ +#define USB_CFG_CHECK_CRC 0 +/* Define this to 1 if you want that the driver checks integrity of incoming + * data packets (CRC checks). CRC checks cost quite a bit of code size and are + * currently only available for 18 MHz crystal clock. You must choose + * USB_CFG_CLOCK_KHZ = 18000 if you enable this option. + */ + +/* ----------------------- Optional Hardware Config ------------------------ */ + +//#define USB_CFG_PULLUP_IOPORTNAME D +/* If you connect the 1.5k pullup resistor from D- to a port pin instead of + * V+, you can connect and disconnect the device from firmware by calling + * the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h). + * This constant defines the port on which the pullup resistor is connected. + */ +//#define USB_CFG_PULLUP_BIT 5 +/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined + * above) where the 1.5k pullup resistor is connected. See description + * above for details. + */ + +/* --------------------------- Functional Range ---------------------------- */ + +#define USB_CFG_HAVE_INTRIN_ENDPOINT 1 +/* Define this to 1 if you want to compile a version with two endpoints: The + * default control endpoint 0 and an interrupt-in endpoint (any other endpoint + * number). + */ +#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0 +/* Define this to 1 if you want to compile a version with three endpoints: The + * default control endpoint 0, an interrupt-in endpoint 3 (or the number + * configured below) and a catch-all default interrupt-in endpoint as above. + * You must also define USB_CFG_HAVE_INTRIN_ENDPOINT to 1 for this feature. + */ +#define USB_CFG_EP3_NUMBER 3 +/* If the so-called endpoint 3 is used, it can now be configured to any other + * endpoint number (except 0) with this macro. Default if undefined is 3. + */ +/* #define USB_INITIAL_DATATOKEN USBPID_DATA1 */ +/* The above macro defines the startup condition for data toggling on the + * interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA1. + * Since the token is toggled BEFORE sending any data, the first packet is + * sent with the oposite value of this configuration! + */ +#define USB_CFG_IMPLEMENT_HALT 0 +/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature + * for endpoint 1 (interrupt endpoint). Although you may not need this feature, + * it is required by the standard. We have made it a config option because it + * bloats the code considerably. + */ +#define USB_CFG_SUPPRESS_INTR_CODE 0 +/* Define this to 1 if you want to declare interrupt-in endpoints, but don't + * want to send any data over them. If this macro is defined to 1, functions + * usbSetInterrupt() and usbSetInterrupt3() are omitted. This is useful if + * you need the interrupt-in endpoints in order to comply to an interface + * (e.g. HID), but never want to send any data. This option saves a couple + * of bytes in flash memory and the transmit buffers in RAM. + */ +#define USB_CFG_INTR_POLL_INTERVAL 10 +/* If you compile a version with endpoint 1 (interrupt-in), this is the poll + * interval. The value is in milliseconds and must not be less than 10 ms for + * low speed devices. + */ +#define USB_CFG_IS_SELF_POWERED 0 +/* Define this to 1 if the device has its own power supply. Set it to 0 if the + * device is powered from the USB bus. + */ +#define USB_CFG_MAX_BUS_POWER 100 +/* Set this variable to the maximum USB bus power consumption of your device. + * The value is in milliamperes. [It will be divided by two since USB + * communicates power requirements in units of 2 mA.] + */ +#define USB_CFG_IMPLEMENT_FN_WRITE 0 +/* Set this to 1 if you want usbFunctionWrite() to be called for control-out + * transfers. Set it to 0 if you don't need it and want to save a couple of + * bytes. + */ +#define USB_CFG_IMPLEMENT_FN_READ 0 +/* Set this to 1 if you need to send control replies which are generated + * "on the fly" when usbFunctionRead() is called. If you only want to send + * data from a static buffer, set it to 0 and return the data from + * usbFunctionSetup(). This saves a couple of bytes. + */ +#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0 +/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints. + * You must implement the function usbFunctionWriteOut() which receives all + * interrupt/bulk data sent to any endpoint other than 0. The endpoint number + * can be found in 'usbRxToken'. + */ +#define USB_CFG_HAVE_FLOWCONTROL 0 +/* Define this to 1 if you want flowcontrol over USB data. See the definition + * of the macros usbDisableAllRequests() and usbEnableAllRequests() in + * usbdrv.h. + */ +#define USB_CFG_LONG_TRANSFERS 0 +/* Define this to 1 if you want to send/receive blocks of more than 254 bytes + * in a single control-in or control-out transfer. Note that the capability + * for long transfers increases the driver size. + */ +/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */ +/* This macro is a hook if you want to do unconventional things. If it is + * defined, it's inserted at the beginning of received message processing. + * If you eat the received message and don't want default processing to + * proceed, do a return after doing your things. One possible application + * (besides debugging) is to flash a status LED on each packet. + */ +/* #define USB_RESET_HOOK(resetStarts) if(!resetStarts){hadUsbReset();} */ +/* This macro is a hook if you need to know when an USB RESET occurs. It has + * one parameter which distinguishes between the start of RESET state and its + * end. + */ +/* #define USB_SET_ADDRESS_HOOK() hadAddressAssigned(); */ +/* This macro (if defined) is executed when a USB SET_ADDRESS request was + * received. + */ +#define USB_COUNT_SOF 1 +/* define this macro to 1 if you need the global variable "usbSofCount" which + * counts SOF packets. This feature requires that the hardware interrupt is + * connected to D- instead of D+. + */ +/* #ifdef __ASSEMBLER__ + * macro myAssemblerMacro + * in YL, TCNT0 + * sts timer0Snapshot, YL + * endm + * #endif + * #define USB_SOF_HOOK myAssemblerMacro + * This macro (if defined) is executed in the assembler module when a + * Start Of Frame condition is detected. It is recommended to define it to + * the name of an assembler macro which is defined here as well so that more + * than one assembler instruction can be used. The macro may use the register + * YL and modify SREG. If it lasts longer than a couple of cycles, USB messages + * immediately after an SOF pulse may be lost and must be retried by the host. + * What can you do with this hook? Since the SOF signal occurs exactly every + * 1 ms (unless the host is in sleep mode), you can use it to tune OSCCAL in + * designs running on the internal RC oscillator. + * Please note that Start Of Frame detection works only if D- is wired to the + * interrupt, not D+. THIS IS DIFFERENT THAN MOST EXAMPLES! + */ +#define USB_CFG_CHECK_DATA_TOGGLING 0 +/* define this macro to 1 if you want to filter out duplicate data packets + * sent by the host. Duplicates occur only as a consequence of communication + * errors, when the host does not receive an ACK. Please note that you need to + * implement the filtering yourself in usbFunctionWriteOut() and + * usbFunctionWrite(). Use the global usbCurrentDataToken and a static variable + * for each control- and out-endpoint to check for duplicate packets. + */ +#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 1 +#include "osccal.h" +/* define this macro to 1 if you want the function usbMeasureFrameLength() + * compiled in. This function can be used to calibrate the AVR's RC oscillator. + */ +#define USB_USE_FAST_CRC 0 +/* The assembler module has two implementations for the CRC algorithm. One is + * faster, the other is smaller. This CRC routine is only used for transmitted + * messages where timing is not critical. The faster routine needs 31 cycles + * per byte while the smaller one needs 61 to 69 cycles. The faster routine + * may be worth the 32 bytes bigger code size if you transmit lots of data and + * run the AVR close to its limit. + */ + +/* -------------------------- Device Description --------------------------- */ + +#define USB_CFG_VENDOR_ID 0xc0, 0x16 /* = 0x16c0 = 5824 = voti.nl */ +/* USB vendor ID for the device, low byte first. If you have registered your + * own Vendor ID, define it here. Otherwise you may use one of obdev's free + * shared VID/PID pairs. Be sure to read USB-IDs-for-free.txt for rules! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_ID 0xdf, 0x05 /* obdev's shared PID for HIDs */ +/* This is the ID of the product, low byte first. It is interpreted in the + * scope of the vendor ID. If you have registered your own VID with usb.org + * or if you have licensed a PID from somebody else, define it here. Otherwise + * you may use one of obdev's free shared VID/PID pairs. See the file + * USB-IDs-for-free.txt for details! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_VERSION 0x00, 0x01 +/* Version number of the device: Minor number first, then major number. + */ +#define USB_CFG_VENDOR_NAME 'd','i','g','i','s','t','u','m','p','.','c','o','m' +#define USB_CFG_VENDOR_NAME_LEN 13 +/* These two values define the vendor name returned by the USB device. The name + * must be given as a list of characters under single quotes. The characters + * are interpreted as Unicode (UTF-16) entities. + * If you don't want a vendor name string, undefine these macros. + * ALWAYS define a vendor name containing your Internet domain name if you use + * obdev's free shared VID/PID pair. See the file USB-IDs-for-free.txt for + * details. + */ +#ifndef USB_CFG_DEVICE_NAME + +#define USB_CFG_DEVICE_NAME 'D','i','g','i','U','S','B' +#define USB_CFG_DEVICE_NAME_LEN 7 + + #endif +/* Same as above for the device name. If you don't want a device name, undefine + * the macros. See the file USB-IDs-for-free.txt before you assign a name if + * you use a shared VID/PID. + */ +/*#define USB_CFG_SERIAL_NUMBER 'N', 'o', 'n', 'e' */ +/*#define USB_CFG_SERIAL_NUMBER_LEN 0 */ +/* Same as above for the serial number. If you don't want a serial number, + * undefine the macros. + * It may be useful to provide the serial number through other means than at + * compile time. See the section about descriptor properties below for how + * to fine tune control over USB descriptors such as the string descriptor + * for the serial number. + */ +#define USB_CFG_DEVICE_CLASS 0 /* set to 0 if deferred to interface */ +#define USB_CFG_DEVICE_SUBCLASS 0 +/* See USB specification if you want to conform to an existing device class. + * Class 0xff is "vendor specific". + */ +#define USB_CFG_INTERFACE_CLASS 0x03 /* HID */ /* define class here if not at device level */ +#define USB_CFG_INTERFACE_SUBCLASS 0 +#define USB_CFG_INTERFACE_PROTOCOL 0 +/* See USB specification if you want to conform to an existing device class or + * protocol. The following classes must be set at interface level: + * HID class is 3, no subclass and protocol required (but may be useful!) + * CDC class is 2, use subclass 2 and protocol 1 for ACM + */ +#define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 22 +/* Define this to the length of the HID report descriptor, if you implement + * an HID device. Otherwise don't define it or define it to 0. + * If you use this define, you must add a PROGMEM character array named + * "usbHidReportDescriptor" to your code which contains the report descriptor. + * Don't forget to keep the array and this define in sync! + */ + +/* #define USB_PUBLIC static */ +/* Use the define above if you #include usbdrv.c instead of linking against it. + * This technique saves a couple of bytes in flash memory. + */ + +/* ------------------- Fine Control over USB Descriptors ------------------- */ +/* If you don't want to use the driver's default USB descriptors, you can + * provide our own. These can be provided as (1) fixed length static data in + * flash memory, (2) fixed length static data in RAM or (3) dynamically at + * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more + * information about this function. + * Descriptor handling is configured through the descriptor's properties. If + * no properties are defined or if they are 0, the default descriptor is used. + * Possible properties are: + * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched + * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is + * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if + * you want RAM pointers. + * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found + * in static memory is in RAM, not in flash memory. + * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash), + * the driver must know the descriptor's length. The descriptor itself is + * found at the address of a well known identifier (see below). + * List of static descriptor names (must be declared PROGMEM if in flash): + * char usbDescriptorDevice[]; + * char usbDescriptorConfiguration[]; + * char usbDescriptorHidReport[]; + * char usbDescriptorString0[]; + * int usbDescriptorStringVendor[]; + * int usbDescriptorStringDevice[]; + * int usbDescriptorStringSerialNumber[]; + * Other descriptors can't be provided statically, they must be provided + * dynamically at runtime. + * + * Descriptor properties are or-ed or added together, e.g.: + * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18)) + * + * The following descriptors are defined: + * USB_CFG_DESCR_PROPS_DEVICE + * USB_CFG_DESCR_PROPS_CONFIGURATION + * USB_CFG_DESCR_PROPS_STRINGS + * USB_CFG_DESCR_PROPS_STRING_0 + * USB_CFG_DESCR_PROPS_STRING_VENDOR + * USB_CFG_DESCR_PROPS_STRING_PRODUCT + * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER + * USB_CFG_DESCR_PROPS_HID + * USB_CFG_DESCR_PROPS_HID_REPORT + * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver) + * + * Note about string descriptors: String descriptors are not just strings, they + * are Unicode strings prefixed with a 2 byte header. Example: + * int serialNumberDescriptor[] = { + * USB_STRING_DESCRIPTOR_HEADER(6), + * 'S', 'e', 'r', 'i', 'a', 'l' + * }; + */ + +#define USB_CFG_DESCR_PROPS_DEVICE 0 +#define USB_CFG_DESCR_PROPS_CONFIGURATION 0 +#define USB_CFG_DESCR_PROPS_STRINGS 0 +#define USB_CFG_DESCR_PROPS_STRING_0 0 +#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0 +#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0 +#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0 +#define USB_CFG_DESCR_PROPS_HID 0 +#define USB_CFG_DESCR_PROPS_HID_REPORT 0 +#define USB_CFG_DESCR_PROPS_UNKNOWN 0 + +/* ----------------------- Optional MCU Description ------------------------ */ + +/* The following configurations have working defaults in usbdrv.h. You + * usually don't need to set them explicitly. Only if you want to run + * the driver on a device which is not yet supported or with a compiler + * which is not fully supported (such as IAR C) or if you use a differnt + * interrupt than INT0, you may have to define some of these. + */ + #if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define USB_INTR_CFG PCMSK +#define USB_INTR_CFG_SET (1<len & 0x10){ /* packet buffer was empty */ + txStatus->buffer[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */ + }else{ + txStatus->len = USBPID_NAK; /* avoid sending outdated (overwritten) interrupt data */ + } + p = txStatus->buffer + 1; + i = len; + do{ /* if len == 0, we still copy 1 byte, but that's no problem */ + *p++ = *data++; + }while(--i > 0); /* loop control at the end is 2 bytes shorter than at beginning */ + usbCrc16Append(&txStatus->buffer[1], len); + txStatus->len = len + 4; /* len must be given including sync byte */ + DBG2(0x21 + (((int)txStatus >> 3) & 3), txStatus->buffer, len + 3); +} + +USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len) +{ + usbGenericSetInterrupt(data, len, &usbTxStatus1); +} +#endif + +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 +USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len) +{ + usbGenericSetInterrupt(data, len, &usbTxStatus3); +} +#endif +#endif /* USB_CFG_SUPPRESS_INTR_CODE */ + +/* ------------------ utilities for code following below ------------------- */ + +/* Use defines for the switch statement so that we can choose between an + * if()else if() and a switch/case based implementation. switch() is more + * efficient for a LARGE set of sequential choices, if() is better in all other + * cases. + */ +#if USB_CFG_USE_SWITCH_STATEMENT +# define SWITCH_START(cmd) switch(cmd){{ +# define SWITCH_CASE(value) }break; case (value):{ +# define SWITCH_CASE2(v1,v2) }break; case (v1): case(v2):{ +# define SWITCH_CASE3(v1,v2,v3) }break; case (v1): case(v2): case(v3):{ +# define SWITCH_DEFAULT }break; default:{ +# define SWITCH_END }} +#else +# define SWITCH_START(cmd) {uchar _cmd = cmd; if(0){ +# define SWITCH_CASE(value) }else if(_cmd == (value)){ +# define SWITCH_CASE2(v1,v2) }else if(_cmd == (v1) || _cmd == (v2)){ +# define SWITCH_CASE3(v1,v2,v3) }else if(_cmd == (v1) || _cmd == (v2) || (_cmd == v3)){ +# define SWITCH_DEFAULT }else{ +# define SWITCH_END }} +#endif + +#ifndef USB_RX_USER_HOOK +#define USB_RX_USER_HOOK(data, len) +#endif +#ifndef USB_SET_ADDRESS_HOOK +#define USB_SET_ADDRESS_HOOK() +#endif + +/* ------------------------------------------------------------------------- */ + +/* We use if() instead of #if in the macro below because #if can't be used + * in macros and the compiler optimizes constant conditions anyway. + * This may cause problems with undefined symbols if compiled without + * optimizing! + */ +#define GET_DESCRIPTOR(cfgProp, staticName) \ + if(cfgProp){ \ + if((cfgProp) & USB_PROP_IS_RAM) \ + flags = 0; \ + if((cfgProp) & USB_PROP_IS_DYNAMIC){ \ + len = usbFunctionDescriptor(rq); \ + }else{ \ + len = USB_PROP_LENGTH(cfgProp); \ + usbMsgPtr = (uchar *)(staticName); \ + } \ + } + +/* usbDriverDescriptor() is similar to usbFunctionDescriptor(), but used + * internally for all types of descriptors. + */ +static inline usbMsgLen_t usbDriverDescriptor(usbRequest_t *rq) +{ +usbMsgLen_t len = 0; +uchar flags = USB_FLG_MSGPTR_IS_ROM; + + SWITCH_START(rq->wValue.bytes[1]) + SWITCH_CASE(USBDESCR_DEVICE) /* 1 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_DEVICE, usbDescriptorDevice) + SWITCH_CASE(USBDESCR_CONFIG) /* 2 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_CONFIGURATION, usbDescriptorConfiguration) + SWITCH_CASE(USBDESCR_STRING) /* 3 */ +#if USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC + if(USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_RAM) + flags = 0; + len = usbFunctionDescriptor(rq); +#else /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */ + SWITCH_START(rq->wValue.bytes[0]) + SWITCH_CASE(0) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_0, usbDescriptorString0) + SWITCH_CASE(1) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_VENDOR, usbDescriptorStringVendor) + SWITCH_CASE(2) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_PRODUCT, usbDescriptorStringDevice) + SWITCH_CASE(3) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER, usbDescriptorStringSerialNumber) + SWITCH_DEFAULT + if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){ + len = usbFunctionDescriptor(rq); + } + SWITCH_END +#endif /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */ +#if USB_CFG_DESCR_PROPS_HID_REPORT /* only support HID descriptors if enabled */ + SWITCH_CASE(USBDESCR_HID) /* 0x21 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID, usbDescriptorConfiguration + 18) + SWITCH_CASE(USBDESCR_HID_REPORT)/* 0x22 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID_REPORT, usbDescriptorHidReport) +#endif + SWITCH_DEFAULT + if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){ + len = usbFunctionDescriptor(rq); + } + SWITCH_END + usbMsgFlags = flags; + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbDriverSetup() is similar to usbFunctionSetup(), but it's used for + * standard requests instead of class and custom requests. + */ +static inline usbMsgLen_t usbDriverSetup(usbRequest_t *rq) +{ +uchar len = 0, *dataPtr = usbTxBuf + 9; /* there are 2 bytes free space at the end of the buffer */ +uchar value = rq->wValue.bytes[0]; +#if USB_CFG_IMPLEMENT_HALT +uchar index = rq->wIndex.bytes[0]; +#endif + + dataPtr[0] = 0; /* default reply common to USBRQ_GET_STATUS and USBRQ_GET_INTERFACE */ + SWITCH_START(rq->bRequest) + SWITCH_CASE(USBRQ_GET_STATUS) /* 0 */ + uchar recipient = rq->bmRequestType & USBRQ_RCPT_MASK; /* assign arith ops to variables to enforce byte size */ + if(USB_CFG_IS_SELF_POWERED && recipient == USBRQ_RCPT_DEVICE) + dataPtr[0] = USB_CFG_IS_SELF_POWERED; +#if USB_CFG_IMPLEMENT_HALT + if(recipient == USBRQ_RCPT_ENDPOINT && index == 0x81) /* request status for endpoint 1 */ + dataPtr[0] = usbTxLen1 == USBPID_STALL; +#endif + dataPtr[1] = 0; + len = 2; +#if USB_CFG_IMPLEMENT_HALT + SWITCH_CASE2(USBRQ_CLEAR_FEATURE, USBRQ_SET_FEATURE) /* 1, 3 */ + if(value == 0 && index == 0x81){ /* feature 0 == HALT for endpoint == 1 */ + usbTxLen1 = rq->bRequest == USBRQ_CLEAR_FEATURE ? USBPID_NAK : USBPID_STALL; + usbResetDataToggling(); + } +#endif + SWITCH_CASE(USBRQ_SET_ADDRESS) /* 5 */ + usbNewDeviceAddr = value; + USB_SET_ADDRESS_HOOK(); + SWITCH_CASE(USBRQ_GET_DESCRIPTOR) /* 6 */ + len = usbDriverDescriptor(rq); + goto skipMsgPtrAssignment; + SWITCH_CASE(USBRQ_GET_CONFIGURATION) /* 8 */ + dataPtr = &usbConfiguration; /* send current configuration value */ + len = 1; + SWITCH_CASE(USBRQ_SET_CONFIGURATION) /* 9 */ + usbConfiguration = value; + usbResetStall(); + SWITCH_CASE(USBRQ_GET_INTERFACE) /* 10 */ + len = 1; +#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE + SWITCH_CASE(USBRQ_SET_INTERFACE) /* 11 */ + usbResetDataToggling(); + usbResetStall(); +#endif + SWITCH_DEFAULT /* 7=SET_DESCRIPTOR, 12=SYNC_FRAME */ + /* Should we add an optional hook here? */ + SWITCH_END + usbMsgPtr = dataPtr; +skipMsgPtrAssignment: + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbProcessRx() is called for every message received by the interrupt + * routine. It distinguishes between SETUP and DATA packets and processes + * them accordingly. + */ +static inline void usbProcessRx(uchar *data, uchar len) +{ + usbRequest_t *rq = (usbRequest_t *)((void *)data); + +/* usbRxToken can be: + * 0x2d 00101101 (USBPID_SETUP for setup data) + * 0xe1 11100001 (USBPID_OUT: data phase of setup transfer) + * 0...0x0f for OUT on endpoint X + */ + DBG2(0x10 + (usbRxToken & 0xf), data, len + 2); /* SETUP=1d, SETUP-DATA=11, OUTx=1x */ + USB_RX_USER_HOOK(data, len) +#if USB_CFG_IMPLEMENT_FN_WRITEOUT + if(usbRxToken < 0x10){ /* OUT to endpoint != 0: endpoint number in usbRxToken */ + usbFunctionWriteOut(data, len); + return; + } +#endif + if(usbRxToken == (uchar)USBPID_SETUP){ + if(len != 8) /* Setup size must be always 8 bytes. Ignore otherwise. */ + return; + usbMsgLen_t replyLen; + usbTxBuf[0] = USBPID_DATA0; /* initialize data toggling */ + usbTxLen = USBPID_NAK; /* abort pending transmit */ + usbMsgFlags = 0; + uchar type = rq->bmRequestType & USBRQ_TYPE_MASK; + if(type != USBRQ_TYPE_STANDARD){ /* standard requests are handled by driver */ + replyLen = usbFunctionSetup(data); + }else{ + replyLen = usbDriverSetup(rq); + } +#if USB_CFG_IMPLEMENT_FN_READ || USB_CFG_IMPLEMENT_FN_WRITE + if(replyLen == USB_NO_MSG){ /* use user-supplied read/write function */ + /* do some conditioning on replyLen, but on IN transfers only */ + if((rq->bmRequestType & USBRQ_DIR_MASK) != USBRQ_DIR_HOST_TO_DEVICE){ + if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */ + replyLen = rq->wLength.bytes[0]; + }else{ + replyLen = rq->wLength.word; + } + } + usbMsgFlags = USB_FLG_USE_USER_RW; + }else /* The 'else' prevents that we limit a replyLen of USB_NO_MSG to the maximum transfer len. */ +#endif + if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */ + if(!rq->wLength.bytes[1] && replyLen > rq->wLength.bytes[0]) /* limit length to max */ + replyLen = rq->wLength.bytes[0]; + }else{ + if(replyLen > rq->wLength.word) /* limit length to max */ + replyLen = rq->wLength.word; + } + usbMsgLen = replyLen; + }else{ /* usbRxToken must be USBPID_OUT, which means data phase of setup (control-out) */ +#if USB_CFG_IMPLEMENT_FN_WRITE + if(usbMsgFlags & USB_FLG_USE_USER_RW){ + uchar rval = usbFunctionWrite(data, len); + if(rval == 0xff){ /* an error occurred */ + usbTxLen = USBPID_STALL; + }else if(rval != 0){ /* This was the final package */ + usbMsgLen = 0; /* answer with a zero-sized data packet */ + } + } +#endif + } +} + +/* ------------------------------------------------------------------------- */ + +/* This function is similar to usbFunctionRead(), but it's also called for + * data handled automatically by the driver (e.g. descriptor reads). + */ +static uchar usbDeviceRead(uchar *data, uchar len) +{ + if(len > 0){ /* don't bother app with 0 sized reads */ +#if USB_CFG_IMPLEMENT_FN_READ + if(usbMsgFlags & USB_FLG_USE_USER_RW){ + len = usbFunctionRead(data, len); + }else +#endif + { + uchar i = len, *r = usbMsgPtr; + if(usbMsgFlags & USB_FLG_MSGPTR_IS_ROM){ /* ROM data */ + do{ + uchar c = USB_READ_FLASH(r); /* assign to char size variable to enforce byte ops */ + *data++ = c; + r++; + }while(--i); + }else{ /* RAM data */ + do{ + *data++ = *r++; + }while(--i); + } + usbMsgPtr = r; + } + } + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbBuildTxBlock() is called when we have data to transmit and the + * interrupt routine's transmit buffer is empty. + */ +static inline void usbBuildTxBlock(void) +{ +usbMsgLen_t wantLen; +uchar len; + + wantLen = usbMsgLen; + if(wantLen > 8) + wantLen = 8; + usbMsgLen -= wantLen; + usbTxBuf[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* DATA toggling */ + len = usbDeviceRead(usbTxBuf + 1, wantLen); + if(len <= 8){ /* valid data packet */ + usbCrc16Append(&usbTxBuf[1], len); + len += 4; /* length including sync byte */ + if(len < 12) /* a partial package identifies end of message */ + usbMsgLen = USB_NO_MSG; + }else{ + len = USBPID_STALL; /* stall the endpoint */ + usbMsgLen = USB_NO_MSG; + } + usbTxLen = len; + DBG2(0x20, usbTxBuf, len-1); +} + +/* ------------------------------------------------------------------------- */ + +static inline void usbHandleResetHook(uchar notResetState) +{ +#ifdef USB_RESET_HOOK +static uchar wasReset; +uchar isReset = !notResetState; + + if(wasReset != isReset){ + USB_RESET_HOOK(isReset); + wasReset = isReset; + } +#endif +} + +/* ------------------------------------------------------------------------- */ + +USB_PUBLIC void usbPoll(void) +{ +schar len; +uchar i; + + len = usbRxLen - 3; + if(len >= 0){ +/* We could check CRC16 here -- but ACK has already been sent anyway. If you + * need data integrity checks with this driver, check the CRC in your app + * code and report errors back to the host. Since the ACK was already sent, + * retries must be handled on application level. + * unsigned crc = usbCrc16(buffer + 1, usbRxLen - 3); + */ + usbProcessRx(usbRxBuf + USB_BUFSIZE + 1 - usbInputBufOffset, len); +#if USB_CFG_HAVE_FLOWCONTROL + if(usbRxLen > 0) /* only mark as available if not inactivated */ + usbRxLen = 0; +#else + usbRxLen = 0; /* mark rx buffer as available */ +#endif + } + if(usbTxLen & 0x10){ /* transmit system idle */ + if(usbMsgLen != USB_NO_MSG){ /* transmit data pending? */ + usbBuildTxBlock(); + } + } + for(i = 20; i > 0; i--){ + uchar usbLineStatus = USBIN & USBMASK; + if(usbLineStatus != 0) /* SE0 has ended */ + goto isNotReset; + } + /* RESET condition, called multiple times during reset */ + usbNewDeviceAddr = 0; + usbDeviceAddr = 0; + usbResetStall(); + DBG1(0xff, 0, 0); +isNotReset: + usbHandleResetHook(i); +} + +/* ------------------------------------------------------------------------- */ + +USB_PUBLIC void usbInit(void) +{ +#if USB_INTR_CFG_SET != 0 + USB_INTR_CFG |= USB_INTR_CFG_SET; +#endif +#if USB_INTR_CFG_CLR != 0 + USB_INTR_CFG &= ~(USB_INTR_CFG_CLR); +#endif + USB_INTR_ENABLE |= (1 << USB_INTR_ENABLE_BIT); + usbResetDataToggling(); +#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE + usbTxLen1 = USBPID_NAK; +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 + usbTxLen3 = USBPID_NAK; +#endif +#endif +} + +/* ------------------------------------------------------------------------- */ diff --git a/hardware/digistump/avr/libraries/DigiUSB/usbdrv.h b/hardware/digistump/avr/libraries/DigiUSB/usbdrv.h new file mode 100644 index 0000000..8a61692 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/usbdrv.h @@ -0,0 +1,777 @@ +/* Name: usbdrv.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2004-12-29 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbdrv.h 769 2009-08-22 11:49:05Z cs $ + */ + +#ifndef __usbdrv_h_included__ +#define __usbdrv_h_included__ +#include "usbconfig.h" +#include "usbportability.h" + +/* +Hardware Prerequisites: +======================= +USB lines D+ and D- MUST be wired to the same I/O port. We recommend that D+ +triggers the interrupt (best achieved by using INT0 for D+), but it is also +possible to trigger the interrupt from D-. If D- is used, interrupts are also +triggered by SOF packets. D- requires a pull-up of 1.5k to +3.5V (and the +device must be powered at 3.5V) to identify as low-speed USB device. A +pull-down or pull-up of 1M SHOULD be connected from D+ to +3.5V to prevent +interference when no USB master is connected. If you use Zener diodes to limit +the voltage on D+ and D-, you MUST use a pull-down resistor, not a pull-up. +We use D+ as interrupt source and not D- because it does not trigger on +keep-alive and RESET states. If you want to count keep-alive events with +USB_COUNT_SOF, you MUST use D- as an interrupt source. + +As a compile time option, the 1.5k pull-up resistor on D- can be made +switchable to allow the device to disconnect at will. See the definition of +usbDeviceConnect() and usbDeviceDisconnect() further down in this file. + +Please adapt the values in usbconfig.h according to your hardware! + +The device MUST be clocked at exactly 12 MHz, 15 MHz, 16 MHz or 20 MHz +or at 12.8 MHz resp. 16.5 MHz +/- 1%. See usbconfig-prototype.h for details. + + +Limitations: +============ +Robustness with respect to communication errors: +The driver assumes error-free communication. It DOES check for errors in +the PID, but does NOT check bit stuffing errors, SE0 in middle of a byte, +token CRC (5 bit) and data CRC (16 bit). CRC checks can not be performed due +to timing constraints: We must start sending a reply within 7 bit times. +Bit stuffing and misplaced SE0 would have to be checked in real-time, but CPU +performance does not permit that. The driver does not check Data0/Data1 +toggling, but application software can implement the check. + +Input characteristics: +Since no differential receiver circuit is used, electrical interference +robustness may suffer. The driver samples only one of the data lines with +an ordinary I/O pin's input characteristics. However, since this is only a +low speed USB implementation and the specification allows for 8 times the +bit rate over the same hardware, we should be on the safe side. Even the spec +requires detection of asymmetric states at high bit rate for SE0 detection. + +Number of endpoints: +The driver supports the following endpoints: + +- Endpoint 0, the default control endpoint. +- Any number of interrupt- or bulk-out endpoints. The data is sent to + usbFunctionWriteOut() and USB_CFG_IMPLEMENT_FN_WRITEOUT must be defined + to 1 to activate this feature. The endpoint number can be found in the + global variable 'usbRxToken'. +- One default interrupt- or bulk-in endpoint. This endpoint is used for + interrupt- or bulk-in transfers which are not handled by any other endpoint. + You must define USB_CFG_HAVE_INTRIN_ENDPOINT in order to activate this + feature and call usbSetInterrupt() to send interrupt/bulk data. +- One additional interrupt- or bulk-in endpoint. This was endpoint 3 in + previous versions of this driver but can now be configured to any endpoint + number. You must define USB_CFG_HAVE_INTRIN_ENDPOINT3 in order to activate + this feature and call usbSetInterrupt3() to send interrupt/bulk data. The + endpoint number can be set with USB_CFG_EP3_NUMBER. + +Please note that the USB standard forbids bulk endpoints for low speed devices! +Most operating systems allow them anyway, but the AVR will spend 90% of the CPU +time in the USB interrupt polling for bulk data. + +Maximum data payload: +Data payload of control in and out transfers may be up to 254 bytes. In order +to accept payload data of out transfers, you need to implement +'usbFunctionWrite()'. + +USB Suspend Mode supply current: +The USB standard limits power consumption to 500uA when the bus is in suspend +mode. This is not a problem for self-powered devices since they don't need +bus power anyway. Bus-powered devices can achieve this only by putting the +CPU in sleep mode. The driver does not implement suspend handling by itself. +However, the application may implement activity monitoring and wakeup from +sleep. The host sends regular SE0 states on the bus to keep it active. These +SE0 states can be detected by using D- as the interrupt source. Define +USB_COUNT_SOF to 1 and use the global variable usbSofCount to check for bus +activity. + +Operation without an USB master: +The driver behaves neutral without connection to an USB master if D- reads +as 1. To avoid spurious interrupts, we recommend a high impedance (e.g. 1M) +pull-down or pull-up resistor on D+ (interrupt). If Zener diodes are used, +use a pull-down. If D- becomes statically 0, the driver may block in the +interrupt routine. + +Interrupt latency: +The application must ensure that the USB interrupt is not disabled for more +than 25 cycles (this is for 12 MHz, faster clocks allow longer latency). +This implies that all interrupt routines must either be declared as "INTERRUPT" +instead of "SIGNAL" (see "avr/signal.h") or that they are written in assembler +with "sei" as the first instruction. + +Maximum interrupt duration / CPU cycle consumption: +The driver handles all USB communication during the interrupt service +routine. The routine will not return before an entire USB message is received +and the reply is sent. This may be up to ca. 1200 cycles @ 12 MHz (= 100us) if +the host conforms to the standard. The driver will consume CPU cycles for all +USB messages, even if they address another (low-speed) device on the same bus. + +*/ + +/* ------------------------------------------------------------------------- */ +/* --------------------------- Module Interface ---------------------------- */ +/* ------------------------------------------------------------------------- */ + +#define USBDRV_VERSION 20090822 +/* This define uniquely identifies a driver version. It is a decimal number + * constructed from the driver's release date in the form YYYYMMDD. If the + * driver's behavior or interface changes, you can use this constant to + * distinguish versions. If it is not defined, the driver's release date is + * older than 2006-01-25. + */ + + +#ifndef USB_PUBLIC +#define USB_PUBLIC +#endif +/* USB_PUBLIC is used as declaration attribute for all functions exported by + * the USB driver. The default is no attribute (see above). You may define it + * to static either in usbconfig.h or from the command line if you include + * usbdrv.c instead of linking against it. Including the C module of the driver + * directly in your code saves a couple of bytes in flash memory. + */ + +#ifndef __ASSEMBLER__ +#ifndef uchar +#define uchar unsigned char +#endif +#ifndef schar +#define schar signed char +#endif +/* shortcuts for well defined 8 bit integer types */ + +#if USB_CFG_LONG_TRANSFERS /* if more than 254 bytes transfer size required */ +# define usbMsgLen_t unsigned +#else +# define usbMsgLen_t uchar +#endif +/* usbMsgLen_t is the data type used for transfer lengths. By default, it is + * defined to uchar, allowing a maximum of 254 bytes (255 is reserved for + * USB_NO_MSG below). If the usbconfig.h defines USB_CFG_LONG_TRANSFERS to 1, + * a 16 bit data type is used, allowing up to 16384 bytes (the rest is used + * for flags in the descriptor configuration). + */ +#define USB_NO_MSG ((usbMsgLen_t)-1) /* constant meaning "no message" */ + +struct usbRequest; /* forward declaration */ + +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbInit(void); +/* This function must be called before interrupts are enabled and the main + * loop is entered. We exepct that the PORT and DDR bits for D+ and D- have + * not been changed from their default status (which is 0). If you have changed + * them, set both back to 0 (configure them as input with no internal pull-up). + */ +USB_PUBLIC void usbPoll(void); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function must be called at regular intervals from the main loop. + * Maximum delay between calls is somewhat less than 50ms (USB timeout for + * accepting a Setup message). Otherwise the device will not be recognized. + * Please note that debug outputs through the UART take ~ 0.5ms per byte + * at 19200 bps. + */ +extern uchar *usbMsgPtr; +/* This variable may be used to pass transmit data to the driver from the + * implementation of usbFunctionWrite(). It is also used internally by the + * driver for standard control requests. + */ +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC usbMsgLen_t usbFunctionSetup(uchar data[8]); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function is called when the driver receives a SETUP transaction from + * the host which is not answered by the driver itself (in practice: class and + * vendor requests). All control transfers start with a SETUP transaction where + * the host communicates the parameters of the following (optional) data + * transfer. The SETUP data is available in the 'data' parameter which can + * (and should) be casted to 'usbRequest_t *' for a more user-friendly access + * to parameters. + * + * If the SETUP indicates a control-in transfer, you should provide the + * requested data to the driver. There are two ways to transfer this data: + * (1) Set the global pointer 'usbMsgPtr' to the base of the static RAM data + * block and return the length of the data in 'usbFunctionSetup()'. The driver + * will handle the rest. Or (2) return USB_NO_MSG in 'usbFunctionSetup()'. The + * driver will then call 'usbFunctionRead()' when data is needed. See the + * documentation for usbFunctionRead() for details. + * + * If the SETUP indicates a control-out transfer, the only way to receive the + * data from the host is through the 'usbFunctionWrite()' call. If you + * implement this function, you must return USB_NO_MSG in 'usbFunctionSetup()' + * to indicate that 'usbFunctionWrite()' should be used. See the documentation + * of this function for more information. If you just want to ignore the data + * sent by the host, return 0 in 'usbFunctionSetup()'. + * + * Note that calls to the functions usbFunctionRead() and usbFunctionWrite() + * are only done if enabled by the configuration in usbconfig.h. + */ +USB_PUBLIC usbMsgLen_t usbFunctionDescriptor(struct usbRequest *rq); +/* You need to implement this function ONLY if you provide USB descriptors at + * runtime (which is an expert feature). It is very similar to + * usbFunctionSetup() above, but it is called only to request USB descriptor + * data. See the documentation of usbFunctionSetup() above for more info. + */ +#if USB_CFG_HAVE_INTRIN_ENDPOINT +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function sets the message which will be sent during the next interrupt + * IN transfer. The message is copied to an internal buffer and must not exceed + * a length of 8 bytes. The message may be 0 bytes long just to indicate the + * interrupt status to the host. + * If you need to transfer more bytes, use a control read after the interrupt. + */ +#define usbInterruptIsReady() (usbTxLen1 & 0x10) +/* This macro indicates whether the last interrupt message has already been + * sent. If you set a new interrupt message before the old was sent, the + * message already buffered will be lost. + */ +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 +USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len); +#define usbInterruptIsReady3() (usbTxLen3 & 0x10) +/* Same as above for endpoint 3 */ +#endif +#endif /* USB_CFG_HAVE_INTRIN_ENDPOINT */ +#if USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH /* simplified interface for backward compatibility */ +#define usbHidReportDescriptor usbDescriptorHidReport +/* should be declared as: PROGMEM char usbHidReportDescriptor[]; */ +/* If you implement an HID device, you need to provide a report descriptor. + * The HID report descriptor syntax is a bit complex. If you understand how + * report descriptors are constructed, we recommend that you use the HID + * Descriptor Tool from usb.org, see http://www.usb.org/developers/hidpage/. + * Otherwise you should probably start with a working example. + */ +#endif /* USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH */ +#if USB_CFG_IMPLEMENT_FN_WRITE +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC uchar usbFunctionWrite(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function is called by the driver to provide a control transfer's + * payload data (control-out). It is called in chunks of up to 8 bytes. The + * total count provided in the current control transfer can be obtained from + * the 'length' property in the setup data. If an error occurred during + * processing, return 0xff (== -1). The driver will answer the entire transfer + * with a STALL token in this case. If you have received the entire payload + * successfully, return 1. If you expect more data, return 0. If you don't + * know whether the host will send more data (you should know, the total is + * provided in the usbFunctionSetup() call!), return 1. + * NOTE: If you return 0xff for STALL, 'usbFunctionWrite()' may still be called + * for the remaining data. You must continue to return 0xff for STALL in these + * calls. + * In order to get usbFunctionWrite() called, define USB_CFG_IMPLEMENT_FN_WRITE + * to 1 in usbconfig.h and return 0xff in usbFunctionSetup().. + */ +#endif /* USB_CFG_IMPLEMENT_FN_WRITE */ +#if USB_CFG_IMPLEMENT_FN_READ +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC uchar usbFunctionRead(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function is called by the driver to ask the application for a control + * transfer's payload data (control-in). It is called in chunks of up to 8 + * bytes each. You should copy the data to the location given by 'data' and + * return the actual number of bytes copied. If you return less than requested, + * the control-in transfer is terminated. If you return 0xff, the driver aborts + * the transfer with a STALL token. + * In order to get usbFunctionRead() called, define USB_CFG_IMPLEMENT_FN_READ + * to 1 in usbconfig.h and return 0xff in usbFunctionSetup().. + */ +#endif /* USB_CFG_IMPLEMENT_FN_READ */ + +extern uchar usbRxToken; /* may be used in usbFunctionWriteOut() below */ +#if USB_CFG_IMPLEMENT_FN_WRITEOUT +USB_PUBLIC void usbFunctionWriteOut(uchar *data, uchar len); +/* This function is called by the driver when data is received on an interrupt- + * or bulk-out endpoint. The endpoint number can be found in the global + * variable usbRxToken. You must define USB_CFG_IMPLEMENT_FN_WRITEOUT to 1 in + * usbconfig.h to get this function called. + */ +#endif /* USB_CFG_IMPLEMENT_FN_WRITEOUT */ +#ifdef USB_CFG_PULLUP_IOPORTNAME +#define usbDeviceConnect() ((USB_PULLUP_DDR |= (1<device, 1=device->host + * t ..... type: 0=standard, 1=class, 2=vendor, 3=reserved + * r ..... recipient: 0=device, 1=interface, 2=endpoint, 3=other + */ + +/* USB setup recipient values */ +#define USBRQ_RCPT_MASK 0x1f +#define USBRQ_RCPT_DEVICE 0 +#define USBRQ_RCPT_INTERFACE 1 +#define USBRQ_RCPT_ENDPOINT 2 + +/* USB request type values */ +#define USBRQ_TYPE_MASK 0x60 +#define USBRQ_TYPE_STANDARD (0<<5) +#define USBRQ_TYPE_CLASS (1<<5) +#define USBRQ_TYPE_VENDOR (2<<5) + +/* USB direction values: */ +#define USBRQ_DIR_MASK 0x80 +#define USBRQ_DIR_HOST_TO_DEVICE (0<<7) +#define USBRQ_DIR_DEVICE_TO_HOST (1<<7) + +/* USB Standard Requests */ +#define USBRQ_GET_STATUS 0 +#define USBRQ_CLEAR_FEATURE 1 +#define USBRQ_SET_FEATURE 3 +#define USBRQ_SET_ADDRESS 5 +#define USBRQ_GET_DESCRIPTOR 6 +#define USBRQ_SET_DESCRIPTOR 7 +#define USBRQ_GET_CONFIGURATION 8 +#define USBRQ_SET_CONFIGURATION 9 +#define USBRQ_GET_INTERFACE 10 +#define USBRQ_SET_INTERFACE 11 +#define USBRQ_SYNCH_FRAME 12 + +/* USB descriptor constants */ +#define USBDESCR_DEVICE 1 +#define USBDESCR_CONFIG 2 +#define USBDESCR_STRING 3 +#define USBDESCR_INTERFACE 4 +#define USBDESCR_ENDPOINT 5 +#define USBDESCR_HID 0x21 +#define USBDESCR_HID_REPORT 0x22 +#define USBDESCR_HID_PHYS 0x23 + +//#define USBATTR_BUSPOWER 0x80 // USB 1.1 does not define this value any more +#define USBATTR_SELFPOWER 0x40 +#define USBATTR_REMOTEWAKE 0x20 + +/* USB HID Requests */ +#define USBRQ_HID_GET_REPORT 0x01 +#define USBRQ_HID_GET_IDLE 0x02 +#define USBRQ_HID_GET_PROTOCOL 0x03 +#define USBRQ_HID_SET_REPORT 0x09 +#define USBRQ_HID_SET_IDLE 0x0a +#define USBRQ_HID_SET_PROTOCOL 0x0b + +/* ------------------------------------------------------------------------- */ + +#endif /* __usbdrv_h_included__ */ diff --git a/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm.S b/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm.S new file mode 100644 index 0000000..bad72f0 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm.S @@ -0,0 +1,395 @@ +/* Name: usbdrvasm.S + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2007-06-13 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + */ + +/* +General Description: +This module is the assembler part of the USB driver. This file contains +general code (preprocessor acrobatics and CRC computation) and then includes +the file appropriate for the given clock rate. +*/ +#ifdef __SFR_OFFSET +#undef __SFR_OFFSET +#endif + +#define __SFR_OFFSET 0 /* used by avr-libc's register definitions */ +#include "usbportability.h" +#include "usbdrv.h" /* for common defs */ + +/* register names */ +#define x1 r16 +#define x2 r17 +#define shift r18 +#define cnt r19 +#define x3 r20 +#define x4 r21 +#define x5 r22 +#define bitcnt x5 +#define phase x4 +#define leap x4 + +/* Some assembler dependent definitions and declarations: */ + +#ifdef __IAR_SYSTEMS_ASM__ + extern usbRxBuf, usbDeviceAddr, usbNewDeviceAddr, usbInputBufOffset + extern usbCurrentTok, usbRxLen, usbRxToken, usbTxLen + extern usbTxBuf, usbTxStatus1, usbTxStatus3 +# if USB_COUNT_SOF + extern usbSofCount +# endif + public usbCrc16 + public usbCrc16Append + + COMMON INTVEC +# ifndef USB_INTR_VECTOR + ORG INT0_vect +# else /* USB_INTR_VECTOR */ + ORG USB_INTR_VECTOR +# undef USB_INTR_VECTOR +# endif /* USB_INTR_VECTOR */ +# define USB_INTR_VECTOR usbInterruptHandler + rjmp USB_INTR_VECTOR + RSEG CODE + +#else /* __IAR_SYSTEMS_ASM__ */ + +# ifndef USB_INTR_VECTOR /* default to hardware interrupt INT0 */ +# ifdef INT0_vect +# define USB_INTR_VECTOR INT0_vect // this is the "new" define for the vector +# else +# define USB_INTR_VECTOR SIG_INTERRUPT0 // this is the "old" vector +# endif +# endif + .text + .global USB_INTR_VECTOR + .type USB_INTR_VECTOR, @function + .global usbCrc16 + .global usbCrc16Append +#endif /* __IAR_SYSTEMS_ASM__ */ + + +#if USB_INTR_PENDING < 0x40 /* This is an I/O address, use in and out */ +# define USB_LOAD_PENDING(reg) in reg, USB_INTR_PENDING +# define USB_STORE_PENDING(reg) out USB_INTR_PENDING, reg +#else /* It's a memory address, use lds and sts */ +# define USB_LOAD_PENDING(reg) lds reg, USB_INTR_PENDING +# define USB_STORE_PENDING(reg) sts USB_INTR_PENDING, reg +#endif + +#define usbTxLen1 usbTxStatus1 +#define usbTxBuf1 (usbTxStatus1 + 1) +#define usbTxLen3 usbTxStatus3 +#define usbTxBuf3 (usbTxStatus3 + 1) + + +;---------------------------------------------------------------------------- +; Utility functions +;---------------------------------------------------------------------------- + +#ifdef __IAR_SYSTEMS_ASM__ +/* Register assignments for usbCrc16 on IAR cc */ +/* Calling conventions on IAR: + * First parameter passed in r16/r17, second in r18/r19 and so on. + * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer) + * Result is passed in r16/r17 + * In case of the "tiny" memory model, pointers are only 8 bit with no + * padding. We therefore pass argument 1 as "16 bit unsigned". + */ +RTMODEL "__rt_version", "3" +/* The line above will generate an error if cc calling conventions change. + * The value "3" above is valid for IAR 4.10B/W32 + */ +# define argLen r18 /* argument 2 */ +# define argPtrL r16 /* argument 1 */ +# define argPtrH r17 /* argument 1 */ + +# define resCrcL r16 /* result */ +# define resCrcH r17 /* result */ + +# define ptrL ZL +# define ptrH ZH +# define ptr Z +# define byte r22 +# define bitCnt r19 +# define polyL r20 +# define polyH r21 +# define scratch r23 + +#else /* __IAR_SYSTEMS_ASM__ */ +/* Register assignments for usbCrc16 on gcc */ +/* Calling conventions on gcc: + * First parameter passed in r24/r25, second in r22/23 and so on. + * Callee must preserve r1-r17, r28/r29 + * Result is passed in r24/r25 + */ +# define argLen r22 /* argument 2 */ +# define argPtrL r24 /* argument 1 */ +# define argPtrH r25 /* argument 1 */ + +# define resCrcL r24 /* result */ +# define resCrcH r25 /* result */ + +# define ptrL XL +# define ptrH XH +# define ptr x +# define byte r18 +# define bitCnt r19 +# define polyL r20 +# define polyH r21 +# define scratch r23 + +#endif + +#if USB_USE_FAST_CRC + +; This implementation is faster, but has bigger code size +; Thanks to Slawomir Fras (BoskiDialer) for this code! +; It implements the following C pseudo-code: +; unsigned table(unsigned char x) +; { +; unsigned value; +; +; value = (unsigned)x << 6; +; value ^= (unsigned)x << 7; +; if(parity(x)) +; value ^= 0xc001; +; return value; +; } +; unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen) +; { +; unsigned crc = 0xffff; +; +; while(argLen--) +; crc = table(lo8(crc) ^ *argPtr++) ^ hi8(crc); +; return ~crc; +; } + +; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen); +; argPtr r24+25 / r16+r17 +; argLen r22 / r18 +; temp variables: +; byte r18 / r22 +; scratch r23 +; resCrc r24+r25 / r16+r17 +; ptr X / Z +usbCrc16: + mov ptrL, argPtrL + mov ptrH, argPtrH + ldi resCrcL, 0xFF + ldi resCrcH, 0xFF + rjmp usbCrc16LoopTest +usbCrc16ByteLoop: + ld byte, ptr+ + eor resCrcL, byte ; resCrcL is now 'x' in table() + mov byte, resCrcL ; compute parity of 'x' + swap byte + eor byte, resCrcL + mov scratch, byte + lsr byte + lsr byte + eor byte, scratch + inc byte + lsr byte + andi byte, 1 ; byte is now parity(x) + mov scratch, resCrcL + mov resCrcL, resCrcH + eor resCrcL, byte ; low byte of if(parity(x)) value ^= 0xc001; + neg byte + andi byte, 0xc0 + mov resCrcH, byte ; high byte of if(parity(x)) value ^= 0xc001; + clr byte + lsr scratch + ror byte + eor resCrcH, scratch + eor resCrcL, byte + lsr scratch + ror byte + eor resCrcH, scratch + eor resCrcL, byte +usbCrc16LoopTest: + subi argLen, 1 + brsh usbCrc16ByteLoop + com resCrcL + com resCrcH + ret + +#else /* USB_USE_FAST_CRC */ + +; This implementation is slower, but has less code size +; +; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen); +; argPtr r24+25 / r16+r17 +; argLen r22 / r18 +; temp variables: +; byte r18 / r22 +; bitCnt r19 +; poly r20+r21 +; scratch r23 +; resCrc r24+r25 / r16+r17 +; ptr X / Z +usbCrc16: + mov ptrL, argPtrL + mov ptrH, argPtrH + ldi resCrcL, 0 + ldi resCrcH, 0 + ldi polyL, lo8(0xa001) + ldi polyH, hi8(0xa001) + com argLen ; argLen = -argLen - 1: modified loop to ensure that carry is set + ldi bitCnt, 0 ; loop counter with starnd condition = end condition + rjmp usbCrcLoopEntry +usbCrcByteLoop: + ld byte, ptr+ + eor resCrcL, byte +usbCrcBitLoop: + ror resCrcH ; carry is always set here (see brcs jumps to here) + ror resCrcL + brcs usbCrcNoXor + eor resCrcL, polyL + eor resCrcH, polyH +usbCrcNoXor: + subi bitCnt, 224 ; (8 * 224) % 256 = 0; this loop iterates 8 times + brcs usbCrcBitLoop +usbCrcLoopEntry: + subi argLen, -1 + brcs usbCrcByteLoop +usbCrcReady: + ret +; Thanks to Reimar Doeffinger for optimizing this CRC routine! + +#endif /* USB_USE_FAST_CRC */ + +; extern unsigned usbCrc16Append(unsigned char *data, unsigned char len); +usbCrc16Append: + rcall usbCrc16 + st ptr+, resCrcL + st ptr+, resCrcH + ret + +#undef argLen +#undef argPtrL +#undef argPtrH +#undef resCrcL +#undef resCrcH +#undef ptrL +#undef ptrH +#undef ptr +#undef byte +#undef bitCnt +#undef polyL +#undef polyH +#undef scratch + + +#if USB_CFG_HAVE_MEASURE_FRAME_LENGTH +#ifdef __IAR_SYSTEMS_ASM__ +/* Register assignments for usbMeasureFrameLength on IAR cc */ +/* Calling conventions on IAR: + * First parameter passed in r16/r17, second in r18/r19 and so on. + * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer) + * Result is passed in r16/r17 + * In case of the "tiny" memory model, pointers are only 8 bit with no + * padding. We therefore pass argument 1 as "16 bit unsigned". + */ +# define resL r16 +# define resH r17 +# define cnt16L r30 +# define cnt16H r31 +# define cntH r18 + +#else /* __IAR_SYSTEMS_ASM__ */ +/* Register assignments for usbMeasureFrameLength on gcc */ +/* Calling conventions on gcc: + * First parameter passed in r24/r25, second in r22/23 and so on. + * Callee must preserve r1-r17, r28/r29 + * Result is passed in r24/r25 + */ +# define resL r24 +# define resH r25 +# define cnt16L r24 +# define cnt16H r25 +# define cntH r26 +#endif +# define cnt16 cnt16L + +; extern unsigned usbMeasurePacketLength(void); +; returns time between two idle strobes in multiples of 7 CPU clocks +.global usbMeasureFrameLength +usbMeasureFrameLength: + ldi cntH, 6 ; wait ~ 10 ms for D- == 0 + clr cnt16L + clr cnt16H +usbMFTime16: + dec cntH + breq usbMFTimeout +usbMFWaitStrobe: ; first wait for D- == 0 (idle strobe) + sbiw cnt16, 1 ;[0] [6] + breq usbMFTime16 ;[2] + sbic USBIN, USBMINUS ;[3] + rjmp usbMFWaitStrobe ;[4] +usbMFWaitIdle: ; then wait until idle again + sbis USBIN, USBMINUS ;1 wait for D- == 1 + rjmp usbMFWaitIdle ;2 + ldi cnt16L, 1 ;1 represents cycles so far + clr cnt16H ;1 +usbMFWaitLoop: + in cntH, USBIN ;[0] [7] + adiw cnt16, 1 ;[1] + breq usbMFTimeout ;[3] + andi cntH, USBMASK ;[4] + brne usbMFWaitLoop ;[5] +usbMFTimeout: +#if resL != cnt16L + mov resL, cnt16L + mov resH, cnt16H +#endif + ret + +#undef resL +#undef resH +#undef cnt16 +#undef cnt16L +#undef cnt16H +#undef cntH + +#endif /* USB_CFG_HAVE_MEASURE_FRAME_LENGTH */ + +;---------------------------------------------------------------------------- +; Now include the clock rate specific code +;---------------------------------------------------------------------------- + +#ifndef USB_CFG_CLOCK_KHZ +# ifdef F_CPU +# define USB_CFG_CLOCK_KHZ (F_CPU/1000) +# else +# error "USB_CFG_CLOCK_KHZ not defined in usbconfig.h and no F_CPU set!" +# endif +#endif + +#if USB_CFG_CHECK_CRC /* separate dispatcher for CRC type modules */ +# if USB_CFG_CLOCK_KHZ == 18000 +# include "usbdrvasm18-crc.inc" +# else +# error "USB_CFG_CLOCK_KHZ is not one of the supported crc-rates!" +# endif +#else /* USB_CFG_CHECK_CRC */ +# if USB_CFG_CLOCK_KHZ == 12000 +# include "usbdrvasm12.inc" +# elif USB_CFG_CLOCK_KHZ == 12800 +# include "usbdrvasm128.inc" +# elif USB_CFG_CLOCK_KHZ == 15000 +# include "usbdrvasm15.inc" +# elif USB_CFG_CLOCK_KHZ == 16000 +# include "usbdrvasm16.inc" +# elif USB_CFG_CLOCK_KHZ == 16500 +# include "usbdrvasm165.inc" +# elif USB_CFG_CLOCK_KHZ == 20000 +# include "usbdrvasm20.inc" +# else +# error "USB_CFG_CLOCK_KHZ is not one of the supported non-crc-rates!" +# endif +#endif /* USB_CFG_CHECK_CRC */ diff --git a/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm.asm b/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm.asm new file mode 100644 index 0000000..9cc4e4d --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm.asm @@ -0,0 +1,21 @@ +/* Name: usbdrvasm.asm + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2006-03-01 + * Tabsize: 4 + * Copyright: (c) 2006 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id$ + */ + +/* +General Description: +The IAR compiler/assembler system prefers assembler files with file extension +".asm". We simply provide this file as an alias for usbdrvasm.S. + +Thanks to Oleg Semyonov for his help with the IAR tools port! +*/ + +#include "usbdrvasm.S" + +end diff --git a/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm12.inc b/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm12.inc new file mode 100644 index 0000000..c116758 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm12.inc @@ -0,0 +1,393 @@ +/* Name: usbdrvasm12.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2004-12-29 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbdrvasm12.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 12 MHz version of the asssembler part of the USB driver. It +requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! + + +Timing constraints according to spec (in bit times): +timing subject min max CPUcycles +--------------------------------------------------------------------------- +EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128 +EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60 +DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60 +*/ + +;Software-receiver engine. Strict timing! Don't change unless you can preserve timing! +;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled +;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable +;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes +;Numbers in brackets are maximum cycles since SOF. +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt + push YL ;2 [35] push only what is necessary to sync with edge ASAP + in YL, SREG ;1 [37] + push YL ;2 [39] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of 1/4 bit which meets the spec. + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push YH ;2 [2] + lds YL, usbInputBufOffset;2 [4] + clr YH ;1 [5] + subi YL, lo8(-(usbRxBuf));1 [6] + sbci YH, hi8(-(usbRxBuf));1 [7] + + sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early] + rjmp haveTwoBitsK ;2 [10] + pop YH ;2 [11] undo the push from before + rjmp waitForK ;2 [13] this was not the end of sync, retry +haveTwoBitsK: +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- + push shift ;2 [16] + push x1 ;2 [12] + push x2 ;2 [14] + + in x1, USBIN ;1 [17] <-- sample bit 0 + ldi shift, 0xff ;1 [18] + bst x1, USBMINUS ;1 [19] + bld shift, 0 ;1 [20] + push x3 ;2 [22] + push cnt ;2 [24] + + in x2, USBIN ;1 [25] <-- sample bit 1 + ser x3 ;1 [26] [inserted init instruction] + eor x1, x2 ;1 [27] + bst x1, USBMINUS ;1 [28] + bld shift, 1 ;1 [29] + ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction] + rjmp rxbit2 ;2 [32] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- + +unstuff0: ;1 (branch taken) + andi x3, ~0x01 ;1 [15] + mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit + in x2, USBIN ;1 [17] <-- sample bit 1 again + ori shift, 0x01 ;1 [18] + rjmp didUnstuff0 ;2 [20] + +unstuff1: ;1 (branch taken) + mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit + andi x3, ~0x02 ;1 [22] + ori shift, 0x02 ;1 [23] + nop ;1 [24] + in x1, USBIN ;1 [25] <-- sample bit 2 again + rjmp didUnstuff1 ;2 [27] + +unstuff2: ;1 (branch taken) + andi x3, ~0x04 ;1 [29] + ori shift, 0x04 ;1 [30] + mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit + nop ;1 [32] + in x2, USBIN ;1 [33] <-- sample bit 3 + rjmp didUnstuff2 ;2 [35] + +unstuff3: ;1 (branch taken) + in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late] + andi x3, ~0x08 ;1 [35] + ori shift, 0x08 ;1 [36] + rjmp didUnstuff3 ;2 [38] + +unstuff4: ;1 (branch taken) + andi x3, ~0x10 ;1 [40] + in x1, USBIN ;1 [41] <-- sample stuffed bit 4 + ori shift, 0x10 ;1 [42] + rjmp didUnstuff4 ;2 [44] + +unstuff5: ;1 (branch taken) + andi x3, ~0x20 ;1 [48] + in x2, USBIN ;1 [49] <-- sample stuffed bit 5 + ori shift, 0x20 ;1 [50] + rjmp didUnstuff5 ;2 [52] + +unstuff6: ;1 (branch taken) + andi x3, ~0x40 ;1 [56] + in x1, USBIN ;1 [57] <-- sample stuffed bit 6 + ori shift, 0x40 ;1 [58] + rjmp didUnstuff6 ;2 [60] + +; extra jobs done during bit interval: +; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs] +; bit 1: se0 check +; bit 2: overflow check +; bit 3: recovery from delay [bit 0 tasks took too long] +; bit 4: none +; bit 5: none +; bit 6: none +; bit 7: jump, eor +rxLoop: + eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others + in x1, USBIN ;1 [1] <-- sample bit 0 + st y+, x3 ;2 [3] store data + ser x3 ;1 [4] + nop ;1 [5] + eor x2, x1 ;1 [6] + bst x2, USBMINUS;1 [7] + bld shift, 0 ;1 [8] + in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed) + andi x2, USBMASK ;1 [10] + breq se0 ;1 [11] SE0 check for bit 1 + andi shift, 0xf9 ;1 [12] +didUnstuff0: + breq unstuff0 ;1 [13] + eor x1, x2 ;1 [14] + bst x1, USBMINUS;1 [15] + bld shift, 1 ;1 [16] +rxbit2: + in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed) + andi shift, 0xf3 ;1 [18] + breq unstuff1 ;1 [19] do remaining work for bit 1 +didUnstuff1: + subi cnt, 1 ;1 [20] + brcs overflow ;1 [21] loop control + eor x2, x1 ;1 [22] + bst x2, USBMINUS;1 [23] + bld shift, 2 ;1 [24] + in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed) + andi shift, 0xe7 ;1 [26] + breq unstuff2 ;1 [27] +didUnstuff2: + eor x1, x2 ;1 [28] + bst x1, USBMINUS;1 [29] + bld shift, 3 ;1 [30] +didUnstuff3: + andi shift, 0xcf ;1 [31] + breq unstuff3 ;1 [32] + in x1, USBIN ;1 [33] <-- sample bit 4 + eor x2, x1 ;1 [34] + bst x2, USBMINUS;1 [35] + bld shift, 4 ;1 [36] +didUnstuff4: + andi shift, 0x9f ;1 [37] + breq unstuff4 ;1 [38] + nop2 ;2 [40] + in x2, USBIN ;1 [41] <-- sample bit 5 + eor x1, x2 ;1 [42] + bst x1, USBMINUS;1 [43] + bld shift, 5 ;1 [44] +didUnstuff5: + andi shift, 0x3f ;1 [45] + breq unstuff5 ;1 [46] + nop2 ;2 [48] + in x1, USBIN ;1 [49] <-- sample bit 6 + eor x2, x1 ;1 [50] + bst x2, USBMINUS;1 [51] + bld shift, 6 ;1 [52] +didUnstuff6: + cpi shift, 0x02 ;1 [53] + brlo unstuff6 ;1 [54] + nop2 ;2 [56] + in x2, USBIN ;1 [57] <-- sample bit 7 + eor x1, x2 ;1 [58] + bst x1, USBMINUS;1 [59] + bld shift, 7 ;1 [60] +didUnstuff7: + cpi shift, 0x04 ;1 [61] + brsh rxLoop ;2 [63] loop control +unstuff7: + andi x3, ~0x80 ;1 [63] + ori shift, 0x80 ;1 [64] + in x2, USBIN ;1 [65] <-- sample stuffed bit 7 + nop ;1 [66] + rjmp didUnstuff7 ;2 [68] + +macro POP_STANDARD ; 12 cycles + pop cnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;---------------------------------------------------------------------------- +; Transmitting data +;---------------------------------------------------------------------------- + +txByteLoop: +txBitloop: +stuffN1Delay: ; [03] + ror shift ;[-5] [11] [59] + brcc doExorN1 ;[-4] [60] + subi x4, 1 ;[-3] + brne commonN1 ;[-2] + lsl shift ;[-1] compensate ror after rjmp stuffDelay + nop ;[00] stuffing consists of just waiting 8 cycles + rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear + +sendNakAndReti: ;0 [-19] 19 cycles until SOP + ldi x3, USBPID_NAK ;1 [-18] + rjmp usbSendX3 ;2 [-16] +sendAckAndReti: ;0 [-19] 19 cycles until SOP + ldi x3, USBPID_ACK ;1 [-18] + rjmp usbSendX3 ;2 [-16] +sendCntAndReti: ;0 [-17] 17 cycles until SOP + mov x3, cnt ;1 [-16] +usbSendX3: ;0 [-16] + ldi YL, 20 ;1 [-15] 'x3' is R20 + ldi YH, 0 ;1 [-14] + ldi cnt, 2 ;1 [-13] +; rjmp usbSendAndReti fallthrough + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) or USBOUT = 0x01 +; K = (D+ = 1), (D- = 0) or USBOUT = 0x02 +; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles) + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte +;uses: x1...x2, x4, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x4 = bitstuff cnt] +;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction) +usbSendAndReti: + in x2, USBDDR ;[-12] 12 cycles until SOP + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS ;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + out USBDDR, x2 ;[-8] <--- acquire bus + in x1, USBOUT ;[-7] port mirror for tx loop + ldi shift, 0x40 ;[-6] sync byte is first byte sent (we enter loop after ror) + ldi x2, USBMASK ;[-5] + push x4 ;[-4] +doExorN1: + eor x1, x2 ;[-2] [06] [62] + ldi x4, 6 ;[-1] [07] [63] +commonN1: +stuffN2Delay: + out USBOUT, x1 ;[00] [08] [64] <--- set bit + ror shift ;[01] + brcc doExorN2 ;[02] + subi x4, 1 ;[03] + brne commonN2 ;[04] + lsl shift ;[05] compensate ror after rjmp stuffDelay + rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear +doExorN2: + eor x1, x2 ;[04] [12] + ldi x4, 6 ;[05] [13] +commonN2: + nop ;[06] [14] + subi cnt, 171 ;[07] [15] trick: (3 * 171) & 0xff = 1 + out USBOUT, x1 ;[08] [16] <--- set bit + brcs txBitloop ;[09] [25] [41] + +stuff6Delay: + ror shift ;[42] [50] + brcc doExor6 ;[43] + subi x4, 1 ;[44] + brne common6 ;[45] + lsl shift ;[46] compensate ror after rjmp stuffDelay + nop ;[47] stuffing consists of just waiting 8 cycles + rjmp stuff6Delay ;[48] after ror, C bit is reliably clear +doExor6: + eor x1, x2 ;[45] [53] + ldi x4, 6 ;[46] +common6: +stuff7Delay: + ror shift ;[47] [55] + out USBOUT, x1 ;[48] <--- set bit + brcc doExor7 ;[49] + subi x4, 1 ;[50] + brne common7 ;[51] + lsl shift ;[52] compensate ror after rjmp stuffDelay + rjmp stuff7Delay ;[53] after ror, C bit is reliably clear +doExor7: + eor x1, x2 ;[51] [59] + ldi x4, 6 ;[52] +common7: + ld shift, y+ ;[53] + tst cnt ;[55] + out USBOUT, x1 ;[56] <--- set bit + brne txByteLoop ;[57] + +;make SE0: + cbr x1, USBMASK ;[58] prepare SE0 [spec says EOP may be 15 to 18 cycles] + lds x2, usbNewDeviceAddr;[59] + lsl x2 ;[61] we compare with left shifted address + subi YL, 2 + 20 ;[62] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[63] + out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[01] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 12.5625 MHz +max frequency: 69.286 cycles for 8 bit -> 12.99 MHz +nominal frequency: 12.77 MHz ( = sqrt(min * max)) + +sampling positions: (next even number in range [+/- 0.5]) +cycle index range: 0 ... 66 +bits: +.5, 8.875, 17.25, 25.625, 34, 42.375, 50.75, 59.125 +[0/1], [9], [17], [25/+26], [34], [+42/43], [51], [59] + +bit number: 0 1 2 3 4 5 6 7 +spare cycles 1 2 1 2 1 1 1 0 + +operations to perform: duration cycle + ---------------- + eor fix, shift 1 -> 00 + andi phase, USBMASK 1 -> 08 + breq se0 1 -> 16 (moved to 11) + st y+, data 2 -> 24, 25 + mov data, fix 1 -> 33 + ser data 1 -> 41 + subi cnt, 1 1 -> 49 + brcs overflow 1 -> 50 + +layout of samples and operations: +[##] = sample bit +<##> = sample phase +*##* = operation + +0: *00* [01] 02 03 04 <05> 06 07 +1: *08* [09] 10 11 12 <13> 14 15 *16* +2: [17] 18 19 20 <21> 22 23 +3: *24* *25* [26] 27 28 29 <30> 31 32 +4: *33* [34] 35 36 37 <38> 39 40 +5: *41* [42] 43 44 45 <46> 47 48 +6: *49* *50* [51] 52 53 54 <55> 56 57 58 +7: [59] 60 61 62 <63> 64 65 66 +*****************************************************************************/ + +/* we prefer positive expressions (do if condition) instead of negative + * (skip if condition), therefore use defines for skip instructions: + */ +#define ifioclr sbis +#define ifioset sbic +#define ifrclr sbrs +#define ifrset sbrc + +/* The registers "fix" and "data" swap their meaning during the loop. Use + * defines to keep their name constant. + */ +#define fix x2 +#define data x1 +#undef phase /* phase has a default definition to x4 */ +#define phase x3 + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt, r0 + push YL ;2 push only what is necessary to sync with edge ASAP + in YL, SREG ;1 + push YL ;2 +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of 1/4 bit which meets the spec. + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS ;[0] + rjmp foundK ;[1] +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError + +foundK: +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push YH ;[2] + lds YL, usbInputBufOffset;[4] + clr YH ;[6] + subi YL, lo8(-(usbRxBuf));[7] + sbci YH, hi8(-(usbRxBuf));[8] + + sbis USBIN, USBMINUS ;[9] we want two bits K [we want to sample at 8 + 4 - 1.5 = 10.5] + rjmp haveTwoBitsK ;[10] + pop YH ;[11] undo the push from before + rjmp waitForK ;[13] this was not the end of sync, retry +haveTwoBitsK: +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +#define fix x2 +#define data x1 + + push shift ;[12] + push x1 ;[14] + push x2 ;[16] + ldi shift, 0x80 ;[18] prevent bit-unstuffing but init low bits to 0 + ifioset USBIN, USBMINUS ;[19] [01] <--- bit 0 [10.5 + 8 = 18.5] + ori shift, 1<<0 ;[02] + push x3 ;[03] + push cnt ;[05] + push r0 ;[07] + ifioset USBIN, USBMINUS ;[09] <--- bit 1 + ori shift, 1<<1 ;[10] + ser fix ;[11] + ldi cnt, USB_BUFSIZE ;[12] + mov data, shift ;[13] + lsl shift ;[14] + nop2 ;[15] + ifioset USBIN, USBMINUS ;[17] <--- bit 2 + ori data, 3<<2 ;[18] store in bit 2 AND bit 3 + eor shift, data ;[19] do nrzi decoding + andi data, 1<<3 ;[20] + in phase, USBIN ;[21] <- phase + brne jumpToEntryAfterSet ;[22] if USBMINS at bit 3 was 1 + nop ;[23] + rjmp entryAfterClr ;[24] +jumpToEntryAfterSet: + rjmp entryAfterSet ;[24] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +#undef fix +#define fix x1 +#undef data +#define data x2 + +bit7IsSet: + ifrclr phase, USBMINUS ;[62] check phase only if D- changed + lpm ;[63] + in phase, USBIN ;[64] <- phase (one cycle too late) + ori shift, 1 << 7 ;[65] + nop ;[66] +;;;;rjmp bit0AfterSet ; -> [00] == [67] moved block up to save jump +bit0AfterSet: + eor fix, shift ;[00] +#undef fix +#define fix x2 +#undef data +#define data x1 /* we now have result in data, fix is reset to 0xff */ + ifioclr USBIN, USBMINUS ;[01] <--- sample 0 + rjmp bit0IsClr ;[02] + andi shift, ~(7 << 0) ;[03] + breq unstuff0s ;[04] + in phase, USBIN ;[05] <- phase + rjmp bit1AfterSet ;[06] +unstuff0s: + in phase, USBIN ;[06] <- phase (one cycle too late) + andi fix, ~(1 << 0) ;[07] + ifioclr USBIN, USBMINUS ;[00] + ifioset USBIN, USBPLUS ;[01] + rjmp bit0IsClr ;[02] executed if first expr false or second true +se0AndStore: ; executed only if both bits 0 + st y+, x1 ;[15/17] cycles after start of byte + rjmp se0 ;[17/19] + +bit0IsClr: + ifrset phase, USBMINUS ;[04] check phase only if D- changed + lpm ;[05] + in phase, USBIN ;[06] <- phase (one cycle too late) + ori shift, 1 << 0 ;[07] +bit1AfterClr: + andi phase, USBMASK ;[08] + ifioset USBIN, USBMINUS ;[09] <--- sample 1 + rjmp bit1IsSet ;[10] + breq se0AndStore ;[11] if D- was 0 in bits 0 AND 1 and D+ was 0 in between, we have SE0 + andi shift, ~(7 << 1) ;[12] + in phase, USBIN ;[13] <- phase + breq unstuff1c ;[14] + rjmp bit2AfterClr ;[15] +unstuff1c: + andi fix, ~(1 << 1) ;[16] + nop2 ;[08] + nop2 ;[10] +bit1IsSet: + ifrclr phase, USBMINUS ;[12] check phase only if D- changed + lpm ;[13] + in phase, USBIN ;[14] <- phase (one cycle too late) + ori shift, 1 << 1 ;[15] + nop ;[16] +bit2AfterSet: + ifioclr USBIN, USBMINUS ;[17] <--- sample 2 + rjmp bit2IsClr ;[18] + andi shift, ~(7 << 2) ;[19] + breq unstuff2s ;[20] + in phase, USBIN ;[21] <- phase + rjmp bit3AfterSet ;[22] +unstuff2s: + in phase, USBIN ;[22] <- phase (one cycle too late) + andi fix, ~(1 << 2) ;[23] + nop2 ;[16] + nop2 ;[18] +bit2IsClr: + ifrset phase, USBMINUS ;[20] check phase only if D- changed + lpm ;[21] + in phase, USBIN ;[22] <- phase (one cycle too late) + ori shift, 1 << 2 ;[23] +bit3AfterClr: + st y+, data ;[24] +entryAfterClr: + ifioset USBIN, USBMINUS ;[26] <--- sample 3 + rjmp bit3IsSet ;[27] + andi shift, ~(7 << 3) ;[28] + breq unstuff3c ;[29] + in phase, USBIN ;[30] <- phase + rjmp bit4AfterClr ;[31] +unstuff3c: + in phase, USBIN ;[31] <- phase (one cycle too late) + andi fix, ~(1 << 3) ;[32] + nop2 ;[25] + nop2 ;[27] +bit3IsSet: + ifrclr phase, USBMINUS ;[29] check phase only if D- changed + lpm ;[30] + in phase, USBIN ;[31] <- phase (one cycle too late) + ori shift, 1 << 3 ;[32] +bit4AfterSet: + mov data, fix ;[33] undo this move by swapping defines +#undef fix +#define fix x1 +#undef data +#define data x2 + ifioclr USBIN, USBMINUS ;[34] <--- sample 4 + rjmp bit4IsClr ;[35] + andi shift, ~(7 << 4) ;[36] + breq unstuff4s ;[37] + in phase, USBIN ;[38] <- phase + rjmp bit5AfterSet ;[39] +unstuff4s: + in phase, USBIN ;[39] <- phase (one cycle too late) + andi fix, ~(1 << 4) ;[40] + nop2 ;[33] + nop2 ;[35] +bit4IsClr: + ifrset phase, USBMINUS ;[37] check phase only if D- changed + lpm ;[38] + in phase, USBIN ;[39] <- phase (one cycle too late) + ori shift, 1 << 4 ;[40] +bit5AfterClr: + ser data ;[41] + ifioset USBIN, USBMINUS ;[42] <--- sample 5 + rjmp bit5IsSet ;[43] + andi shift, ~(7 << 5) ;[44] + breq unstuff5c ;[45] + in phase, USBIN ;[46] <- phase + rjmp bit6AfterClr ;[47] +unstuff5c: + in phase, USBIN ;[47] <- phase (one cycle too late) + andi fix, ~(1 << 5) ;[48] + nop2 ;[41] + nop2 ;[43] +bit5IsSet: + ifrclr phase, USBMINUS ;[45] check phase only if D- changed + lpm ;[46] + in phase, USBIN ;[47] <- phase (one cycle too late) + ori shift, 1 << 5 ;[48] +bit6AfterSet: + subi cnt, 1 ;[49] + brcs jumpToOverflow ;[50] + ifioclr USBIN, USBMINUS ;[51] <--- sample 6 + rjmp bit6IsClr ;[52] + andi shift, ~(3 << 6) ;[53] + cpi shift, 2 ;[54] + in phase, USBIN ;[55] <- phase + brlt unstuff6s ;[56] + rjmp bit7AfterSet ;[57] + +jumpToOverflow: + rjmp overflow + +unstuff6s: + andi fix, ~(1 << 6) ;[50] + lpm ;[51] +bit6IsClr: + ifrset phase, USBMINUS ;[54] check phase only if D- changed + lpm ;[55] + in phase, USBIN ;[56] <- phase (one cycle too late) + ori shift, 1 << 6 ;[57] + nop ;[58] +bit7AfterClr: + ifioset USBIN, USBMINUS ;[59] <--- sample 7 + rjmp bit7IsSet ;[60] + andi shift, ~(1 << 7) ;[61] + cpi shift, 4 ;[62] + in phase, USBIN ;[63] <- phase + brlt unstuff7c ;[64] + rjmp bit0AfterClr ;[65] -> [00] == [67] +unstuff7c: + andi fix, ~(1 << 7) ;[58] + nop ;[59] + rjmp bit7IsSet ;[60] + +bit7IsClr: + ifrset phase, USBMINUS ;[62] check phase only if D- changed + lpm ;[63] + in phase, USBIN ;[64] <- phase (one cycle too late) + ori shift, 1 << 7 ;[65] + nop ;[66] +;;;;rjmp bit0AfterClr ; -> [00] == [67] moved block up to save jump +bit0AfterClr: + eor fix, shift ;[00] +#undef fix +#define fix x2 +#undef data +#define data x1 /* we now have result in data, fix is reset to 0xff */ + ifioset USBIN, USBMINUS ;[01] <--- sample 0 + rjmp bit0IsSet ;[02] + andi shift, ~(7 << 0) ;[03] + breq unstuff0c ;[04] + in phase, USBIN ;[05] <- phase + rjmp bit1AfterClr ;[06] +unstuff0c: + in phase, USBIN ;[06] <- phase (one cycle too late) + andi fix, ~(1 << 0) ;[07] + ifioclr USBIN, USBMINUS ;[00] + ifioset USBIN, USBPLUS ;[01] + rjmp bit0IsSet ;[02] executed if first expr false or second true + rjmp se0AndStore ;[03] executed only if both bits 0 +bit0IsSet: + ifrclr phase, USBMINUS ;[04] check phase only if D- changed + lpm ;[05] + in phase, USBIN ;[06] <- phase (one cycle too late) + ori shift, 1 << 0 ;[07] +bit1AfterSet: + andi shift, ~(7 << 1) ;[08] compensated by "ori shift, 1<<1" if bit1IsClr + ifioclr USBIN, USBMINUS ;[09] <--- sample 1 + rjmp bit1IsClr ;[10] + breq unstuff1s ;[11] + nop2 ;[12] do not check for SE0 if bit 0 was 1 + in phase, USBIN ;[14] <- phase (one cycle too late) + rjmp bit2AfterSet ;[15] +unstuff1s: + in phase, USBIN ;[13] <- phase + andi fix, ~(1 << 1) ;[14] + lpm ;[07] + nop2 ;[10] +bit1IsClr: + ifrset phase, USBMINUS ;[12] check phase only if D- changed + lpm ;[13] + in phase, USBIN ;[14] <- phase (one cycle too late) + ori shift, 1 << 1 ;[15] + nop ;[16] +bit2AfterClr: + ifioset USBIN, USBMINUS ;[17] <--- sample 2 + rjmp bit2IsSet ;[18] + andi shift, ~(7 << 2) ;[19] + breq unstuff2c ;[20] + in phase, USBIN ;[21] <- phase + rjmp bit3AfterClr ;[22] +unstuff2c: + in phase, USBIN ;[22] <- phase (one cycle too late) + andi fix, ~(1 << 2) ;[23] + nop2 ;[16] + nop2 ;[18] +bit2IsSet: + ifrclr phase, USBMINUS ;[20] check phase only if D- changed + lpm ;[21] + in phase, USBIN ;[22] <- phase (one cycle too late) + ori shift, 1 << 2 ;[23] +bit3AfterSet: + st y+, data ;[24] +entryAfterSet: + ifioclr USBIN, USBMINUS ;[26] <--- sample 3 + rjmp bit3IsClr ;[27] + andi shift, ~(7 << 3) ;[28] + breq unstuff3s ;[29] + in phase, USBIN ;[30] <- phase + rjmp bit4AfterSet ;[31] +unstuff3s: + in phase, USBIN ;[31] <- phase (one cycle too late) + andi fix, ~(1 << 3) ;[32] + nop2 ;[25] + nop2 ;[27] +bit3IsClr: + ifrset phase, USBMINUS ;[29] check phase only if D- changed + lpm ;[30] + in phase, USBIN ;[31] <- phase (one cycle too late) + ori shift, 1 << 3 ;[32] +bit4AfterClr: + mov data, fix ;[33] undo this move by swapping defines +#undef fix +#define fix x1 +#undef data +#define data x2 + ifioset USBIN, USBMINUS ;[34] <--- sample 4 + rjmp bit4IsSet ;[35] + andi shift, ~(7 << 4) ;[36] + breq unstuff4c ;[37] + in phase, USBIN ;[38] <- phase + rjmp bit5AfterClr ;[39] +unstuff4c: + in phase, USBIN ;[39] <- phase (one cycle too late) + andi fix, ~(1 << 4) ;[40] + nop2 ;[33] + nop2 ;[35] +bit4IsSet: + ifrclr phase, USBMINUS ;[37] check phase only if D- changed + lpm ;[38] + in phase, USBIN ;[39] <- phase (one cycle too late) + ori shift, 1 << 4 ;[40] +bit5AfterSet: + ser data ;[41] + ifioclr USBIN, USBMINUS ;[42] <--- sample 5 + rjmp bit5IsClr ;[43] + andi shift, ~(7 << 5) ;[44] + breq unstuff5s ;[45] + in phase, USBIN ;[46] <- phase + rjmp bit6AfterSet ;[47] +unstuff5s: + in phase, USBIN ;[47] <- phase (one cycle too late) + andi fix, ~(1 << 5) ;[48] + nop2 ;[41] + nop2 ;[43] +bit5IsClr: + ifrset phase, USBMINUS ;[45] check phase only if D- changed + lpm ;[46] + in phase, USBIN ;[47] <- phase (one cycle too late) + ori shift, 1 << 5 ;[48] +bit6AfterClr: + subi cnt, 1 ;[49] + brcs overflow ;[50] + ifioset USBIN, USBMINUS ;[51] <--- sample 6 + rjmp bit6IsSet ;[52] + andi shift, ~(3 << 6) ;[53] + cpi shift, 2 ;[54] + in phase, USBIN ;[55] <- phase + brlt unstuff6c ;[56] + rjmp bit7AfterClr ;[57] +unstuff6c: + andi fix, ~(1 << 6) ;[50] + lpm ;[51] +bit6IsSet: + ifrclr phase, USBMINUS ;[54] check phase only if D- changed + lpm ;[55] + in phase, USBIN ;[56] <- phase (one cycle too late) + ori shift, 1 << 6 ;[57] +bit7AfterSet: + ifioclr USBIN, USBMINUS ;[59] <--- sample 7 + rjmp bit7IsClr ;[60] + andi shift, ~(1 << 7) ;[61] + cpi shift, 4 ;[62] + in phase, USBIN ;[63] <- phase + brlt unstuff7s ;[64] + rjmp bit0AfterSet ;[65] -> [00] == [67] +unstuff7s: + andi fix, ~(1 << 7) ;[58] + nop ;[59] + rjmp bit7IsClr ;[60] + +macro POP_STANDARD ; 14 cycles + pop r0 + pop cnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;---------------------------------------------------------------------------- +; Transmitting data +;---------------------------------------------------------------------------- + +txByteLoop: +txBitloop: +stuffN1Delay: ; [03] + ror shift ;[-5] [11] [63] + brcc doExorN1 ;[-4] [64] + subi x3, 1 ;[-3] + brne commonN1 ;[-2] + lsl shift ;[-1] compensate ror after rjmp stuffDelay + nop ;[00] stuffing consists of just waiting 8 cycles + rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear + +sendNakAndReti: + ldi cnt, USBPID_NAK ;[-19] + rjmp sendCntAndReti ;[-18] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov r0, cnt ;[-16] + ldi YL, 0 ;[-15] R0 address is 0 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) or USBOUT = 0x01 +; K = (D+ = 1), (D- = 0) or USBOUT = 0x02 +; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles) + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte +;uses: x1...x3, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x3 = bitstuff cnt] +;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction) +usbSendAndReti: + in x2, USBDDR ;[-10] 10 cycles until SOP + ori x2, USBMASK ;[-9] + sbi USBOUT, USBMINUS ;[-8] prepare idle state; D+ and D- must have been 0 (no pullups) + out USBDDR, x2 ;[-6] <--- acquire bus + in x1, USBOUT ;[-5] port mirror for tx loop + ldi shift, 0x40 ;[-4] sync byte is first byte sent (we enter loop after ror) + ldi x2, USBMASK ;[-3] +doExorN1: + eor x1, x2 ;[-2] [06] [62] + ldi x3, 6 ;[-1] [07] [63] +commonN1: +stuffN2Delay: + out USBOUT, x1 ;[00] [08] [64] <--- set bit + ror shift ;[01] + brcc doExorN2 ;[02] + subi x3, 1 ;[03] + brne commonN2 ;[04] + lsl shift ;[05] compensate ror after rjmp stuffDelay + rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear +doExorN2: + eor x1, x2 ;[04] [12] + ldi x3, 6 ;[05] [13] +commonN2: + nop2 ;[06] [14] + subi cnt, 171 ;[08] [16] trick: (3 * 171) & 0xff = 1 + out USBOUT, x1 ;[09] [17] <--- set bit + brcs txBitloop ;[10] [27] [44] + +stuff6Delay: + ror shift ;[45] [53] + brcc doExor6 ;[46] + subi x3, 1 ;[47] + brne common6 ;[48] + lsl shift ;[49] compensate ror after rjmp stuffDelay + nop ;[50] stuffing consists of just waiting 8 cycles + rjmp stuff6Delay ;[51] after ror, C bit is reliably clear +doExor6: + eor x1, x2 ;[48] [56] + ldi x3, 6 ;[49] +common6: +stuff7Delay: + ror shift ;[50] [58] + out USBOUT, x1 ;[51] <--- set bit + brcc doExor7 ;[52] + subi x3, 1 ;[53] + brne common7 ;[54] + lsl shift ;[55] compensate ror after rjmp stuffDelay + rjmp stuff7Delay ;[56] after ror, C bit is reliably clear +doExor7: + eor x1, x2 ;[54] [62] + ldi x3, 6 ;[55] +common7: + ld shift, y+ ;[56] + nop ;[58] + tst cnt ;[59] + out USBOUT, x1 ;[60] [00]<--- set bit + brne txByteLoop ;[61] [01] +;make SE0: + cbr x1, USBMASK ;[02] prepare SE0 [spec says EOP may be 15 to 18 cycles] + lds x2, usbNewDeviceAddr;[03] + lsl x2 ;[05] we compare with left shifted address + subi YL, 2 + 0 ;[06] Only assign address on data packets, not ACK/NAK in r0 + sbci YH, 0 ;[07] + out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[01] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 0) + echo "$s\n"; + } +} + +function printBit($isAfterSet, $bitNum) +{ + ob_start(); + if($isAfterSet){ +?> + ifioclr USBIN, USBMINUS ;[00] <--- sample + rjmp bit#IsClr ;[01] + andi shift, ~(7 << #) ;[02] + breq unstuff#s ;[03] + in phase, USBIN ;[04] <- phase + rjmp bit@AfterSet ;[05] +unstuff#s: + in phase, USBIN ;[05] <- phase (one cycle too late) + andi fix, ~(1 << #) ;[06] + nop2 ;[-1] + nop2 ;[01] +bit#IsClr: + ifrset phase, USBMINUS ;[03] check phase only if D- changed + lpm ;[04] + in phase, USBIN ;[05] <- phase (one cycle too late) + ori shift, 1 << # ;[06] + + ifioset USBIN, USBMINUS ;[00] <--- sample + rjmp bit#IsSet ;[01] + andi shift, ~(7 << #) ;[02] + breq unstuff#c ;[03] + in phase, USBIN ;[04] <- phase + rjmp bit@AfterClr ;[05] +unstuff#c: + in phase, USBIN ;[05] <- phase (one cycle too late) + andi fix, ~(1 << #) ;[06] + nop2 ;[-1] + nop2 ;[01] +bit#IsSet: + ifrclr phase, USBMINUS ;[03] check phase only if D- changed + lpm ;[04] + in phase, USBIN ;[05] <- phase (one cycle too late) + ori shift, 1 << # ;[06] + +*****************************************************************************/ diff --git a/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm15.inc b/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm15.inc new file mode 100644 index 0000000..401b7f8 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm15.inc @@ -0,0 +1,423 @@ +/* Name: usbdrvasm15.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: contributed by V. Bosch + * Creation Date: 2007-08-06 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm15.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 15 MHz version of the asssembler part of the USB driver. It +requires a 15 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! +*/ + +;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + +;---------------------------------------------------------------------------- +; order of registers pushed: +; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4 +;---------------------------------------------------------------------------- +USB_INTR_VECTOR: + push YL ;2 push only what is necessary to sync with edge ASAP + in YL, SREG ;1 + push YL ;2 +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +; +; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +; sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +;------------------------------------------------------------------------------- +; The following code results in a sampling window of < 1/4 bit +; which meets the spec. +;------------------------------------------------------------------------------- +waitForK: ;- + sbis USBIN, USBMINUS ;1 [00] <-- sample + rjmp foundK ;2 [01] + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +;------------------------------------------------------------------------------ +; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for +; center sampling] +; we have 1 bit time for setup purposes, then sample again. +; Numbers in brackets are cycles from center of first sync (double K) +; bit after the instruction +;------------------------------------------------------------------------------ +foundK: ;- [02] + lds YL, usbInputBufOffset;2 [03+04] tx loop + push YH ;2 [05+06] + clr YH ;1 [07] + subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init] + sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init] + push shift ;2 [10+11] + ser shift ;1 [12] + sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early) + rjmp haveTwoBitsK ;2 [00] [14] + pop shift ;2 [15+16] undo the push from before + pop YH ;2 [17+18] undo the push from before + rjmp waitForK ;2 [19+20] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 20 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: ;- [01] + push x1 ;2 [02+03] + push x2 ;2 [04+05] + push x3 ;2 [06+07] + push bitcnt ;2 [08+09] + in x1, USBIN ;1 [00] [10] <-- sample bit 0 + bst x1, USBMINUS ;1 [01] + bld shift, 0 ;1 [02] + push cnt ;2 [03+04] + ldi cnt, USB_BUFSIZE ;1 [05] + push x4 ;2 [06+07] tx loop + rjmp rxLoop ;2 [08] +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +unstuff0: ;- [07] (branch taken) + andi x3, ~0x01 ;1 [08] + mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit + in x2, USBIN ;1 [00] [10] <-- sample bit 1 again + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 1 + ori shift, 0x01 ;1 [03] 0b00000001 + nop ;1 [04] + rjmp didUnstuff0 ;2 [05] +;----------------------------------------------------- +unstuff1: ;- [05] (branch taken) + mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit + andi x3, ~0x02 ;1 [07] + ori shift, 0x02 ;1 [08] 0b00000010 + nop ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 2 again + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 2 + rjmp didUnstuff1 ;2 [03] +;----------------------------------------------------- +unstuff2: ;- [05] (branch taken) + andi x3, ~0x04 ;1 [06] + ori shift, 0x04 ;1 [07] 0b00000100 + mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit + nop ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample bit 3 + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 3 + rjmp didUnstuff2 ;2 [03] +;----------------------------------------------------- +unstuff3: ;- [00] [10] (branch taken) + in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late + andi x2, USBMASK ;1 [02] + breq se0Hop ;1 [03] SE0 check for stuffed bit 3 + andi x3, ~0x08 ;1 [04] + ori shift, 0x08 ;1 [05] 0b00001000 + rjmp didUnstuff3 ;2 [06] +;---------------------------------------------------------------------------- +; extra jobs done during bit interval: +; +; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs], +; overflow check, jump to the head of rxLoop +; bit 1: SE0 check +; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long] +; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long] +; bit 4: SE0 check, none +; bit 5: SE0 check, none +; bit 6: SE0 check, none +; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others +;---------------------------------------------------------------------------- +rxLoop: ;- [09] + in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed) + andi x2, USBMASK ;1 [01] + brne SkipSe0Hop ;1 [02] +se0Hop: ;- [02] + rjmp se0 ;2 [03] SE0 check for bit 1 +SkipSe0Hop: ;- [03] + ser x3 ;1 [04] + andi shift, 0xf9 ;1 [05] 0b11111001 + breq unstuff0 ;1 [06] +didUnstuff0: ;- [06] + eor x1, x2 ;1 [07] + bst x1, USBMINUS ;1 [08] + bld shift, 1 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed) + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 2 + andi shift, 0xf3 ;1 [03] 0b11110011 + breq unstuff1 ;1 [04] do remaining work for bit 1 +didUnstuff1: ;- [04] + eor x2, x1 ;1 [05] + bst x2, USBMINUS ;1 [06] + bld shift, 2 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed) + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 3 + andi shift, 0xe7 ;1 [03] 0b11100111 + breq unstuff2 ;1 [04] +didUnstuff2: ;- [04] + eor x1, x2 ;1 [05] + bst x1, USBMINUS ;1 [06] + bld shift, 3 ;1 [07] +didUnstuff3: ;- [07] + andi shift, 0xcf ;1 [08] 0b11001111 + breq unstuff3 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 4 + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 4 + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 4 ;1 [05] +didUnstuff4: ;- [05] + andi shift, 0x9f ;1 [06] 0b10011111 + breq unstuff4 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 5 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 5 + eor x1, x2 ;1 [03] + bst x1, USBMINUS ;1 [04] + bld shift, 5 ;1 [05] +didUnstuff5: ;- [05] + andi shift, 0x3f ;1 [06] 0b00111111 + breq unstuff5 ;1 [07] + nop2 ;2 [08+09] + in x1, USBIN ;1 [00] [10] <-- sample bit 6 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 6 + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 6 ;1 [05] +didUnstuff6: ;- [05] + cpi shift, 0x02 ;1 [06] 0b00000010 + brlo unstuff6 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 7 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 7 + eor x1, x2 ;1 [03] + bst x1, USBMINUS ;1 [04] + bld shift, 7 ;1 [05] +didUnstuff7: ;- [05] + cpi shift, 0x04 ;1 [06] 0b00000100 + brlo unstuff7 ;1 [07] + eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others + nop ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 0 + st y+, x3 ;2 [01+02] store data + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 0 ;1 [05] + subi cnt, 1 ;1 [06] + brcs overflow ;1 [07] + rjmp rxLoop ;2 [08] +;----------------------------------------------------- +unstuff4: ;- [08] + andi x3, ~0x10 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 4 + ori shift, 0x10 ;1 [03] + rjmp didUnstuff4 ;2 [04] +;----------------------------------------------------- +unstuff5: ;- [08] + ori shift, 0x20 ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 5 + andi x3, ~0x20 ;1 [03] + rjmp didUnstuff5 ;2 [04] +;----------------------------------------------------- +unstuff6: ;- [08] + andi x3, ~0x40 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 6 + ori shift, 0x40 ;1 [03] + rjmp didUnstuff6 ;2 [04] +;----------------------------------------------------- +unstuff7: ;- [08] + andi x3, ~0x80 ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 7 + ori shift, 0x80 ;1 [03] + rjmp didUnstuff7 ;2 [04] + +macro POP_STANDARD ; 16 cycles + pop x4 + pop cnt + pop bitcnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;--------------------------------------------------------------------------- +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies +;--------------------------------------------------------------------------- +bitstuffN: ;- [04] + eor x1, x4 ;1 [05] + clr x2 ;1 [06] + nop ;1 [07] + rjmp didStuffN ;1 [08] +;--------------------------------------------------------------------------- +bitstuff6: ;- [04] + eor x1, x4 ;1 [05] + clr x2 ;1 [06] + rjmp didStuff6 ;1 [07] +;--------------------------------------------------------------------------- +bitstuff7: ;- [02] + eor x1, x4 ;1 [03] + clr x2 ;1 [06] + nop ;1 [05] + rjmp didStuff7 ;1 [06] +;--------------------------------------------------------------------------- +sendNakAndReti: ;- [-19] + ldi x3, USBPID_NAK ;1 [-18] + rjmp sendX3AndReti ;1 [-17] +;--------------------------------------------------------------------------- +sendAckAndReti: ;- [-17] + ldi cnt, USBPID_ACK ;1 [-16] +sendCntAndReti: ;- [-16] + mov x3, cnt ;1 [-15] +sendX3AndReti: ;- [-15] + ldi YL, 20 ;1 [-14] x3==r20 address is 20 + ldi YH, 0 ;1 [-13] + ldi cnt, 2 ;1 [-12] +; rjmp usbSendAndReti fallthrough +;--------------------------------------------------------------------------- +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +;We need not to match the transfer rate exactly because the spec demands +;only 1.5% precision anyway. +usbSendAndReti: ;- [-13] 13 cycles until SOP + in x2, USBDDR ;1 [-12] + ori x2, USBMASK ;1 [-11] + sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;1 [-08] port mirror for tx loop + out USBDDR, x2 ;1 [-07] <- acquire bus + ; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;1 [-06] exor mask + ldi shift, 0x80 ;1 [-05] sync byte is first byte sent + ldi bitcnt, 6 ;1 [-04] +txBitLoop: ;- [-04] [06] + sbrs shift, 0 ;1 [-03] [07] + eor x1, x4 ;1 [-02] [08] + ror shift ;1 [-01] [09] +didStuffN: ;- [09] + out USBOUT, x1 ;1 [00] [10] <-- out N + ror x2 ;1 [01] + cpi x2, 0xfc ;1 [02] + brcc bitstuffN ;1 [03] + dec bitcnt ;1 [04] + brne txBitLoop ;1 [05] + sbrs shift, 0 ;1 [06] + eor x1, x4 ;1 [07] + ror shift ;1 [08] +didStuff6: ;- [08] + nop ;1 [09] + out USBOUT, x1 ;1 [00] [10] <-- out 6 + ror x2 ;1 [01] + cpi x2, 0xfc ;1 [02] + brcc bitstuff6 ;1 [03] + sbrs shift, 0 ;1 [04] + eor x1, x4 ;1 [05] + ror shift ;1 [06] + ror x2 ;1 [07] +didStuff7: ;- [07] + ldi bitcnt, 6 ;1 [08] + cpi x2, 0xfc ;1 [09] + out USBOUT, x1 ;1 [00] [10] <-- out 7 + brcc bitstuff7 ;1 [01] + ld shift, y+ ;2 [02+03] + dec cnt ;1 [04] + brne txBitLoop ;1 [05] +makeSE0: + cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles] + lds x2, usbNewDeviceAddr;2 [07+08] + lsl x2 ;1 [09] we compare with left shifted address +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle + subi YL, 20 + 2 ;1 [01] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;1 [02] + breq skipAddrAssign ;1 [03] + sts usbDeviceAddr, x2 ;2 [04+05] if not skipped: SE0 is one cycle longer +;---------------------------------------------------------------------------- +;end of usbDeviceAddress transfer +skipAddrAssign: ;- [03/04] + ldi x2, 1< 10.6666666 cycles per bit, 85.333333333 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt + push YL ;[-25] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-23] + push YL ;[-22] + push YH ;[-20] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-15] + rjmp foundK ;[-14] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-12] +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push bitcnt ;[-12] +; [---] ;[-11] + lds YL, usbInputBufOffset;[-10] +; [---] ;[-9] + clr YH ;[-8] + subi YL, lo8(-(usbRxBuf));[-7] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init] + push shift ;[-5] +; [---] ;[-4] + ldi bitcnt, 0x55 ;[-3] [rx loop init] + sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early) + rjmp haveTwoBitsK ;[-1] + pop shift ;[0] undo the push from before + pop bitcnt ;[2] undo the push from before + rjmp waitForK ;[4] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 21 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[1] + push x2 ;[3] + push x3 ;[5] + ldi shift, 0 ;[7] + ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that + push x4 ;[9] == leap + + in x1, USBIN ;[11] <-- sample bit 0 + andi x1, USBMASK ;[12] + bst x1, USBMINUS ;[13] + bld shift, 7 ;[14] + push cnt ;[15] + ldi leap, 0 ;[17] [rx loop init] + ldi cnt, USB_BUFSIZE;[18] [rx loop init] + rjmp rxbit1 ;[19] arrives at [21] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- + +; duration of unstuffing code should be 10.66666667 cycles. We adjust "leap" +; accordingly to approximate this value in the long run. + +unstuff6: + andi x2, USBMASK ;[03] + ori x3, 1<<6 ;[04] will not be shifted any more + andi shift, ~0x80;[05] + mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6 + subi leap, -1 ;[07] total duration = 11 bits -> subtract 1/3 + rjmp didUnstuff6 ;[08] + +unstuff7: + ori x3, 1<<7 ;[09] will not be shifted any more + in x2, USBIN ;[00] [10] re-sample bit 7 + andi x2, USBMASK ;[01] + andi shift, ~0x80;[02] + subi leap, 2 ;[03] total duration = 10 bits -> add 1/3 + rjmp didUnstuff7 ;[04] + +unstuffEven: + ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0 + in x1, USBIN ;[00] [10] + andi shift, ~0x80;[01] + andi x1, USBMASK ;[02] + breq se0 ;[03] + subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3 + nop2 ;[05] + rjmp didUnstuffE ;[06] + +unstuffOdd: + ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1 + in x2, USBIN ;[00] [10] + andi shift, ~0x80;[01] + andi x2, USBMASK ;[02] + breq se0 ;[03] + subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3 + nop2 ;[05] + rjmp didUnstuffO ;[06] + +rxByteLoop: + andi x1, USBMASK ;[03] + eor x2, x1 ;[04] + subi leap, 1 ;[05] + brpl skipLeap ;[06] + subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte + nop ;1 +skipLeap: + subi x2, 1 ;[08] + ror shift ;[09] +didUnstuff6: + cpi shift, 0xfc ;[10] + in x2, USBIN ;[00] [11] <-- sample bit 7 + brcc unstuff6 ;[01] + andi x2, USBMASK ;[02] + eor x1, x2 ;[03] + subi x1, 1 ;[04] + ror shift ;[05] +didUnstuff7: + cpi shift, 0xfc ;[06] + brcc unstuff7 ;[07] + eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others + st y+, x3 ;[09] store data +rxBitLoop: + in x1, USBIN ;[00] [11] <-- sample bit 0/2/4 + andi x1, USBMASK ;[01] + eor x2, x1 ;[02] + andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7 + subi x2, 1 ;[04] + ror shift ;[05] + cpi shift, 0xfc ;[06] + brcc unstuffEven ;[07] +didUnstuffE: + lsr x3 ;[08] + lsr x3 ;[09] +rxbit1: + in x2, USBIN ;[00] [10] <-- sample bit 1/3/5 + andi x2, USBMASK ;[01] + breq se0 ;[02] + eor x1, x2 ;[03] + subi x1, 1 ;[04] + ror shift ;[05] + cpi shift, 0xfc ;[06] + brcc unstuffOdd ;[07] +didUnstuffO: + subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3 + brcs rxBitLoop ;[09] + + subi cnt, 1 ;[10] + in x1, USBIN ;[00] [11] <-- sample bit 6 + brcc rxByteLoop ;[01] + rjmp overflow + +macro POP_STANDARD ; 14 cycles + pop cnt + pop x4 + pop x3 + pop x2 + pop x1 + pop shift + pop bitcnt + endm +macro POP_RETI ; 7 cycles + pop YH + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies + +bitstuffN: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] + nop2 ;[7] + nop ;[9] + out USBOUT, x1 ;[10] <-- out + rjmp didStuffN ;[0] + +bitstuff6: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] Carry is zero due to brcc + rol shift ;[7] compensate for ror shift at branch destination + rjmp didStuff6 ;[8] + +bitstuff7: + ldi x2, 0 ;[2] Carry is zero due to brcc + rjmp didStuff7 ;[3] + + +sendNakAndReti: + ldi x3, USBPID_NAK ;[-18] + rjmp sendX3AndReti ;[-17] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov x3, cnt ;[-16] +sendX3AndReti: + ldi YL, 20 ;[-15] x3==r20 address is 20 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +;We don't match the transfer rate exactly (don't insert leap cycles every third +;byte) because the spec demands only 1.5% precision anyway. +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-7] <- acquire bus +; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-6] exor mask + ldi shift, 0x80 ;[-5] sync byte is first byte sent +txByteLoop: + ldi bitcnt, 0x35 ;[-4] [6] binary 0011 0101 +txBitLoop: + sbrs shift, 0 ;[-3] [7] + eor x1, x4 ;[-2] [8] + out USBOUT, x1 ;[-1] [9] <-- out N + ror shift ;[0] [10] + ror x2 ;[1] +didStuffN: + cpi x2, 0xfc ;[2] + brcc bitstuffN ;[3] + lsr bitcnt ;[4] + brcc txBitLoop ;[5] + brne txBitLoop ;[6] + + sbrs shift, 0 ;[7] + eor x1, x4 ;[8] +didStuff6: + out USBOUT, x1 ;[-1] [9] <-- out 6 + ror shift ;[0] [10] + ror x2 ;[1] + cpi x2, 0xfc ;[2] + brcc bitstuff6 ;[3] + ror shift ;[4] +didStuff7: + ror x2 ;[5] + sbrs x2, 7 ;[6] + eor x1, x4 ;[7] + nop ;[8] + cpi x2, 0xfc ;[9] + out USBOUT, x1 ;[-1][10] <-- out 7 + brcc bitstuff7 ;[0] [11] + ld shift, y+ ;[1] + dec cnt ;[3] + brne txByteLoop ;[4] +;make SE0: + cbr x1, USBMASK ;[5] prepare SE0 [spec says EOP may be 21 to 25 cycles] + lds x2, usbNewDeviceAddr;[6] + lsl x2 ;[8] we compare with left shifted address + subi YL, 20 + 2 ;[9] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[10] + out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[0] + sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< max 52 cycles interrupt disable +;max stack usage: [ret(2), r0, SREG, YL, YH, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 16.5 MHz -> 11 cycles per bit +; 16.3125 MHz < F_CPU < 16.6875 MHz (+/- 1.1%) +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], r0, YH, shift, x1, x2, x3, x4, cnt + push YL ;[-23] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-21] + push YL ;[-20] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-15] + rjmp foundK ;[-14] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-12] +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push r0 ;[-12] +; [---] ;[-11] + push YH ;[-10] +; [---] ;[-9] + lds YL, usbInputBufOffset;[-8] +; [---] ;[-7] + clr YH ;[-6] + subi YL, lo8(-(usbRxBuf));[-5] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-4] [rx loop init] + mov r0, x2 ;[-3] [rx loop init] + sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early) + rjmp haveTwoBitsK ;[-1] + pop YH ;[0] undo the pushes from before + pop r0 ;[2] + rjmp waitForK ;[4] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 22 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: ;[1] + push shift ;[1] + push x1 ;[3] + push x2 ;[5] + push x3 ;[7] + ldi shift, 0xff ;[9] [rx loop init] + ori x3, 0xff ;[10] [rx loop init] == ser x3, clear zero flag + + in x1, USBIN ;[11] <-- sample bit 0 + bst x1, USBMINUS ;[12] + bld shift, 0 ;[13] + push x4 ;[14] == phase +; [---] ;[15] + push cnt ;[16] +; [---] ;[17] + ldi phase, 0 ;[18] [rx loop init] + ldi cnt, USB_BUFSIZE;[19] [rx loop init] + rjmp rxbit1 ;[20] +; [---] ;[21] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +/* +byte oriented operations done during loop: +bit 0: store data +bit 1: SE0 check +bit 2: overflow check +bit 3: catch up +bit 4: rjmp to achieve conditional jump range +bit 5: PLL +bit 6: catch up +bit 7: jump, fixup bitstuff +; 87 [+ 2] cycles +------------------------------------------------------------------ +*/ +continueWithBit5: + in x2, USBIN ;[055] <-- bit 5 + eor r0, x2 ;[056] + or phase, r0 ;[057] + sbrc phase, USBMINUS ;[058] + lpm ;[059] optional nop3; modifies r0 + in phase, USBIN ;[060] <-- phase + eor x1, x2 ;[061] + bst x1, USBMINUS ;[062] + bld shift, 5 ;[063] + andi shift, 0x3f ;[064] + in x1, USBIN ;[065] <-- bit 6 + breq unstuff5 ;[066] *** unstuff escape + eor phase, x1 ;[067] + eor x2, x1 ;[068] + bst x2, USBMINUS ;[069] + bld shift, 6 ;[070] +didUnstuff6: ;[ ] + in r0, USBIN ;[071] <-- phase + cpi shift, 0x02 ;[072] + brlo unstuff6 ;[073] *** unstuff escape +didUnstuff5: ;[ ] + nop2 ;[074] +; [---] ;[075] + in x2, USBIN ;[076] <-- bit 7 + eor x1, x2 ;[077] + bst x1, USBMINUS ;[078] + bld shift, 7 ;[079] +didUnstuff7: ;[ ] + eor r0, x2 ;[080] + or phase, r0 ;[081] + in r0, USBIN ;[082] <-- phase + cpi shift, 0x04 ;[083] + brsh rxLoop ;[084] +; [---] ;[085] +unstuff7: ;[ ] + andi x3, ~0x80 ;[085] + ori shift, 0x80 ;[086] + in x2, USBIN ;[087] <-- sample stuffed bit 7 + nop ;[088] + rjmp didUnstuff7 ;[089] +; [---] ;[090] + ;[080] + +unstuff5: ;[067] + eor phase, x1 ;[068] + andi x3, ~0x20 ;[069] + ori shift, 0x20 ;[070] + in r0, USBIN ;[071] <-- phase + mov x2, x1 ;[072] + nop ;[073] + nop2 ;[074] +; [---] ;[075] + in x1, USBIN ;[076] <-- bit 6 + eor r0, x1 ;[077] + or phase, r0 ;[078] + eor x2, x1 ;[079] + bst x2, USBMINUS ;[080] + bld shift, 6 ;[081] no need to check bitstuffing, we just had one + in r0, USBIN ;[082] <-- phase + rjmp didUnstuff5 ;[083] +; [---] ;[084] + ;[074] + +unstuff6: ;[074] + andi x3, ~0x40 ;[075] + in x1, USBIN ;[076] <-- bit 6 again + ori shift, 0x40 ;[077] + nop2 ;[078] +; [---] ;[079] + rjmp didUnstuff6 ;[080] +; [---] ;[081] + ;[071] + +unstuff0: ;[013] + eor r0, x2 ;[014] + or phase, r0 ;[015] + andi x2, USBMASK ;[016] check for SE0 + in r0, USBIN ;[017] <-- phase + breq didUnstuff0 ;[018] direct jump to se0 would be too long + andi x3, ~0x01 ;[019] + ori shift, 0x01 ;[020] + mov x1, x2 ;[021] mov existing sample + in x2, USBIN ;[022] <-- bit 1 again + rjmp didUnstuff0 ;[023] +; [---] ;[024] + ;[014] + +unstuff1: ;[024] + eor r0, x1 ;[025] + or phase, r0 ;[026] + andi x3, ~0x02 ;[027] + in r0, USBIN ;[028] <-- phase + ori shift, 0x02 ;[029] + mov x2, x1 ;[030] + rjmp didUnstuff1 ;[031] +; [---] ;[032] + ;[022] + +unstuff2: ;[035] + eor r0, x2 ;[036] + or phase, r0 ;[037] + andi x3, ~0x04 ;[038] + in r0, USBIN ;[039] <-- phase + ori shift, 0x04 ;[040] + mov x1, x2 ;[041] + rjmp didUnstuff2 ;[042] +; [---] ;[043] + ;[033] + +unstuff3: ;[043] + in x2, USBIN ;[044] <-- bit 3 again + eor r0, x2 ;[045] + or phase, r0 ;[046] + andi x3, ~0x08 ;[047] + ori shift, 0x08 ;[048] + nop ;[049] + in r0, USBIN ;[050] <-- phase + rjmp didUnstuff3 ;[051] +; [---] ;[052] + ;[042] + +unstuff4: ;[053] + andi x3, ~0x10 ;[054] + in x1, USBIN ;[055] <-- bit 4 again + ori shift, 0x10 ;[056] + rjmp didUnstuff4 ;[057] +; [---] ;[058] + ;[048] + +rxLoop: ;[085] + eor x3, shift ;[086] reconstruct: x3 is 0 at bit locations we changed, 1 at others + in x1, USBIN ;[000] <-- bit 0 + st y+, x3 ;[001] +; [---] ;[002] + eor r0, x1 ;[003] + or phase, r0 ;[004] + eor x2, x1 ;[005] + in r0, USBIN ;[006] <-- phase + ser x3 ;[007] + bst x2, USBMINUS ;[008] + bld shift, 0 ;[009] + andi shift, 0xf9 ;[010] +rxbit1: ;[ ] + in x2, USBIN ;[011] <-- bit 1 + breq unstuff0 ;[012] *** unstuff escape + andi x2, USBMASK ;[013] SE0 check for bit 1 +didUnstuff0: ;[ ] Z only set if we detected SE0 in bitstuff + breq se0 ;[014] + eor r0, x2 ;[015] + or phase, r0 ;[016] + in r0, USBIN ;[017] <-- phase + eor x1, x2 ;[018] + bst x1, USBMINUS ;[019] + bld shift, 1 ;[020] + andi shift, 0xf3 ;[021] +didUnstuff1: ;[ ] + in x1, USBIN ;[022] <-- bit 2 + breq unstuff1 ;[023] *** unstuff escape + eor r0, x1 ;[024] + or phase, r0 ;[025] + subi cnt, 1 ;[026] overflow check + brcs overflow ;[027] + in r0, USBIN ;[028] <-- phase + eor x2, x1 ;[029] + bst x2, USBMINUS ;[030] + bld shift, 2 ;[031] + andi shift, 0xe7 ;[032] +didUnstuff2: ;[ ] + in x2, USBIN ;[033] <-- bit 3 + breq unstuff2 ;[034] *** unstuff escape + eor r0, x2 ;[035] + or phase, r0 ;[036] + eor x1, x2 ;[037] + bst x1, USBMINUS ;[038] + in r0, USBIN ;[039] <-- phase + bld shift, 3 ;[040] + andi shift, 0xcf ;[041] +didUnstuff3: ;[ ] + breq unstuff3 ;[042] *** unstuff escape + nop ;[043] + in x1, USBIN ;[044] <-- bit 4 + eor x2, x1 ;[045] + bst x2, USBMINUS ;[046] + bld shift, 4 ;[047] +didUnstuff4: ;[ ] + eor r0, x1 ;[048] + or phase, r0 ;[049] + in r0, USBIN ;[050] <-- phase + andi shift, 0x9f ;[051] + breq unstuff4 ;[052] *** unstuff escape + rjmp continueWithBit5;[053] +; [---] ;[054] + +macro POP_STANDARD ; 16 cycles + pop cnt + pop x4 + pop x3 + pop x2 + pop x1 + pop shift + pop YH + pop r0 + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies + +bitstuff7: + eor x1, x4 ;[4] + ldi x2, 0 ;[5] + nop2 ;[6] C is zero (brcc) + rjmp didStuff7 ;[8] + +bitstuffN: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] + lpm ;[7] 3 cycle NOP, modifies r0 + out USBOUT, x1 ;[10] <-- out + rjmp didStuffN ;[0] + +#define bitStatus x3 + +sendNakAndReti: + ldi cnt, USBPID_NAK ;[-19] + rjmp sendCntAndReti ;[-18] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov r0, cnt ;[-16] + ldi YL, 0 ;[-15] R0 address is 0 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-7] <- acquire bus +; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-6] exor mask + ldi shift, 0x80 ;[-5] sync byte is first byte sent + ldi bitStatus, 0xff ;[-4] init bit loop counter, works for up to 12 bytes +byteloop: +bitloop: + sbrs shift, 0 ;[8] [-3] + eor x1, x4 ;[9] [-2] + out USBOUT, x1 ;[10] [-1] <-- out + ror shift ;[0] + ror x2 ;[1] +didStuffN: + cpi x2, 0xfc ;[2] + brcc bitstuffN ;[3] + nop ;[4] + subi bitStatus, 37 ;[5] 256 / 7 ~=~ 37 + brcc bitloop ;[6] when we leave the loop, bitStatus has almost the initial value + sbrs shift, 0 ;[7] + eor x1, x4 ;[8] + ror shift ;[9] +didStuff7: + out USBOUT, x1 ;[10] <-- out + ror x2 ;[0] + cpi x2, 0xfc ;[1] + brcc bitstuff7 ;[2] + ld shift, y+ ;[3] + dec cnt ;[5] + brne byteloop ;[6] +;make SE0: + cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles] + lds x2, usbNewDeviceAddr;[8] + lsl x2 ;[10] we compare with left shifted address + out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + subi YL, 2 ;[0] Only assign address on data packets, not ACK/NAK in r0 + sbci YH, 0 ;[1] + breq skipAddrAssign ;[2] + sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 12 cycles per bit +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts +;register use in receive loop to receive the data bytes: +; shift assembles the byte currently being received +; x1 holds the D+ and D- line state +; x2 holds the previous line state +; cnt holds the number of bytes left in the receive buffer +; x3 holds the higher crc byte (see algorithm below) +; x4 is used as temporary register for the crc algorithm +; x5 is used for unstuffing: when unstuffing the last received bit is inverted in shift (to prevent further +; unstuffing calls. In the same time the corresponding bit in x5 is cleared to mark the bit as beening iverted +; zl lower crc value and crc table index +; zh used for crc table accesses + +;-------------------------------------------------------------------------------------------------------------- +; CRC mods: +; table driven crc checker, Z points to table in prog space +; ZL is the lower crc byte, x3 is the higher crc byte +; x4 is used as temp register to store different results +; the initialization of the crc register is not 0xFFFF but 0xFE54. This is because during the receipt of the +; first data byte an virtual zero data byte is added to the crc register, this results in the correct initial +; value of 0xFFFF at beginning of the second data byte before the first data byte is added to the crc. +; The magic number 0xFE54 results form the crc table: At tabH[0x54] = 0xFF = crcH (required) and +; tabL[0x54] = 0x01 -> crcL = 0x01 xor 0xFE = 0xFF +; bitcnt is renamed to x5 and is used for unstuffing purposes, the unstuffing works like in the 12MHz version +;-------------------------------------------------------------------------------------------------------------- +; CRC algorithm: +; The crc register is formed by x3 (higher byte) and ZL (lower byte). The algorithm uses a 'reversed' form +; i.e. that it takes the least significant bit first and shifts to the right. So in fact the highest order +; bit seen from the polynomial devision point of view is the lsb of ZL. (If this sounds strange to you i +; propose a research on CRC :-) ) +; Each data byte received is xored to ZL, the lower crc byte. This byte now builds the crc +; table index. Next the new high byte is loaded from the table and stored in x4 until we have space in x3 +; (its destination). +; Afterwards the lower table is loaded from the table and stored in ZL (the old index is overwritten as +; we don't need it anymore. In fact this is a right shift by 8 bits.) Now the old crc high value is xored +; to ZL, this is the second shift of the old crc value. Now x4 (the temp reg) is moved to x3 and the crc +; calculation is done. +; Prior to the first byte the two CRC register have to be initialized to 0xFFFF (as defined in usb spec) +; however the crc engine also runs during the receipt of the first byte, therefore x3 and zl are initialized +; to a magic number which results in a crc value of 0xFFFF after the first complete byte. +; +; This algorithm is split into the extra cycles of the different bits: +; bit7: XOR the received byte to ZL +; bit5: load the new high byte to x4 +; bit6: load the lower xor byte from the table, xor zl and x3, store result in zl (=the new crc low value) +; move x4 (the new high byte) to x3, the crc value is ready +; + + +macro POP_STANDARD ; 18 cycles + pop ZH + pop ZL + pop cnt + pop x5 + pop x3 + pop x2 + pop x1 + pop shift + pop x4 + endm +macro POP_RETI ; 7 cycles + pop YH + pop YL + out SREG, YL + pop YL + endm + +macro CRC_CLEANUP_AND_CHECK + ; the last byte has already been xored with the lower crc byte, we have to do the table lookup and xor + ; x3 is the higher crc byte, zl the lower one + ldi ZH, hi8(usbCrcTableHigh);[+1] get the new high byte from the table + lpm x2, Z ;[+2][+3][+4] + ldi ZH, hi8(usbCrcTableLow);[+5] get the new low xor byte from the table + lpm ZL, Z ;[+6][+7][+8] + eor ZL, x3 ;[+7] xor the old high byte with the value from the table, x2:ZL now holds the crc value + cpi ZL, 0x01 ;[+8] if the crc is ok we have a fixed remainder value of 0xb001 in x2:ZL (see usb spec) + brne ignorePacket ;[+9] detected a crc fault -> paket is ignored and retransmitted by the host + cpi x2, 0xb0 ;[+10] + brne ignorePacket ;[+11] detected a crc fault -> paket is ignored and retransmitted by the host + endm + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG, YH, [sofError], x4, shift, x1, x2, x3, x5, cnt, ZL, ZH + push YL ;[-28] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-26] + push YL ;[-25] + push YH ;[-23] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-17] + rjmp foundK ;[-16] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-15] +;{3, 5} after falling D- edge, average delay: 4 cycles +;bit0 should be at 30 (2.5 bits) for center sampling. Currently at 4 so 26 cylces till bit 0 sample +;use 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push x4 ;[-14] +; [---] ;[-13] + lds YL, usbInputBufOffset;[-12] used to toggle the two usb receive buffers +; [---] ;[-11] + clr YH ;[-10] + subi YL, lo8(-(usbRxBuf));[-9] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-8] [rx loop init] + push shift ;[-7] +; [---] ;[-6] + ldi shift, 0x80 ;[-5] the last bit is the end of byte marker for the pid receiver loop + clc ;[-4] the carry has to be clear for receipt of pid bit 0 + sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) + rjmp haveTwoBitsK ;[-2] + pop shift ;[-1] undo the push from before + pop x4 ;[1] + rjmp waitForK ;[3] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 24 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[0] + push x2 ;[2] + push x3 ;[4] crc high byte + ldi x2, 1< jump back and store the byte + ori shift, 0x01 ;[11] invert the last received bit to prevent furhter unstuffing + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + andi x5, 0xFE ;[1] mark this bit as inverted (will be corrected before storing shift) + eor x1, x2 ;[2] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[3] mask the interesting bits + breq stuffErr ;[4] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[5] the next bit expects the last state to be in x1 + rjmp didunstuff0 ;[6] + ;[7] jump delay of rjmp didunstuffX + +unstuff1: ;[11] this is the jump delay of breq unstuffX + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + ori shift, 0x02 ;[1] invert the last received bit to prevent furhter unstuffing + andi x5, 0xFD ;[2] mark this bit as inverted (will be corrected before storing shift) + eor x2, x1 ;[3] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[4] mask the interesting bits + breq stuffErr ;[5] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[6] the next bit expects the last state to be in x2 + nop2 ;[7] + ;[8] + rjmp didunstuff1 ;[9] + ;[10] jump delay of rjmp didunstuffX + +unstuff2: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x04 ;[10] invert the last received bit to prevent furhter unstuffing + andi x5, 0xFB ;[11] mark this bit as inverted (will be corrected before storing shift) + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[4] the next bit expects the last state to be in x1 + nop2 ;[5] + ;[6] + rjmp didunstuff2 ;[7] + ;[8] jump delay of rjmp didunstuffX + +unstuff3: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x08 ;[10] invert the last received bit to prevent furhter unstuffing + andi x5, 0xF7 ;[11] mark this bit as inverted (will be corrected before storing shift) + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[4] the next bit expects the last state to be in x2 + nop2 ;[5] + ;[6] + rjmp didunstuff3 ;[7] + ;[8] jump delay of rjmp didunstuffX + + + +; the include has to be here due to branch distance restirctions +#define __USE_CRC__ +#include "asmcommon.inc" + + + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies +; 7.5 bit times is 90 cycles. ...there is plenty of time + + +sendNakAndReti: + ldi x3, USBPID_NAK ;[-18] + rjmp sendX3AndReti ;[-17] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov x3, cnt ;[-16] +sendX3AndReti: + ldi YL, 20 ;[-15] x3==r20 address is 20 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent + +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-6] <- acquire bus + ldi x2, 0 ;[-6] init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-5] exor mask + ldi shift, 0x80 ;[-4] sync byte is first byte sent +txByteLoop: + ldi bitcnt, 0x40 ;[-3]=[9] binary 01000000 +txBitLoop: ; the loop sends the first 7 bits of the byte + sbrs shift, 0 ;[-2]=[10] if we have to send a 1 don't change the line state + eor x1, x4 ;[-1]=[11] + out USBOUT, x1 ;[0] + ror shift ;[1] + ror x2 ;[2] transfers the last sent bit to the stuffing history +didStuffN: + nop ;[3] + nop ;[4] + cpi x2, 0xfc ;[5] if we sent six consecutive ones + brcc bitstuffN ;[6] + lsr bitcnt ;[7] + brne txBitLoop ;[8] restart the loop while the 1 is still in the bitcount + +; transmit bit 7 + sbrs shift, 0 ;[9] + eor x1, x4 ;[10] +didStuff7: + ror shift ;[11] + out USBOUT, x1 ;[0] transfer bit 7 to the pins + ror x2 ;[1] move the bit into the stuffing history + cpi x2, 0xfc ;[2] + brcc bitstuff7 ;[3] + ld shift, y+ ;[4] get next byte to transmit + dec cnt ;[5] decrement byte counter + brne txByteLoop ;[7] if we have more bytes start next one + ;[8] branch delay + +;make SE0: + cbr x1, USBMASK ;[8] prepare SE0 [spec says EOP may be 25 to 30 cycles] + lds x2, usbNewDeviceAddr;[9] + lsl x2 ;[11] we compare with left shifted address + out USBOUT, x1 ;[0] <-- out SE0 -- from now 2 bits = 24 cycles until bus idle + subi YL, 20 + 2 ;[1] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[2] +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[3] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< +int main (int argc, char **argv) +{ + int i, j; + for (i=0; i<512; i++){ + unsigned short crc = i & 0xff; + for(j=0; j<8; j++) crc = (crc >> 1) ^ ((crc & 1) ? 0xa001 : 0); + if((i & 7) == 0) printf("\n.byte "); + printf("0x%02x, ", (i > 0xff ? (crc >> 8) : crc) & 0xff); + if(i == 255) printf("\n"); + } + return 0; +} + +// Use the following algorithm to compute CRC values: +ushort computeCrc(uchar *msg, uchar msgLen) +{ + uchar i; + ushort crc = 0xffff; + for(i = 0; i < msgLen; i++) + crc = usbCrcTable16[lo8(crc) ^ msg[i]] ^ hi8(crc); + return crc; +} +*/ + +.balign 256 +usbCrcTableLow: +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 + +; .balign 256 +usbCrcTableHigh: +.byte 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2 +.byte 0xC6, 0x06, 0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04 +.byte 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E +.byte 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8 +.byte 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A +.byte 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC +.byte 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6 +.byte 0xD2, 0x12, 0x13, 0xD3, 0x11, 0xD1, 0xD0, 0x10 +.byte 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32 +.byte 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4 +.byte 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE +.byte 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38 +.byte 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA +.byte 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C +.byte 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26 +.byte 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0 +.byte 0xA0, 0x60, 0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62 +.byte 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4 +.byte 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE +.byte 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68 +.byte 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA +.byte 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C +.byte 0xB4, 0x74, 0x75, 0xB5, 0x77, 0xB7, 0xB6, 0x76 +.byte 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0 +.byte 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92 +.byte 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54 +.byte 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E +.byte 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98 +.byte 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A +.byte 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C +.byte 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86 +.byte 0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 0x40 + diff --git a/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm20.inc b/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm20.inc new file mode 100644 index 0000000..303abaf --- /dev/null +++ b/hardware/digistump/avr/libraries/DigiUSB/usbdrvasm20.inc @@ -0,0 +1,360 @@ +/* Name: usbdrvasm20.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Jeroen Benschop + * Based on usbdrvasm16.inc from Christian Starkjohann + * Creation Date: 2008-03-05 + * Tabsize: 4 + * Copyright: (c) 2008 by Jeroen Benschop and OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm20.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 20 MHz version of the asssembler part of the USB driver. It +requires a 20 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! +*/ + +#define leap2 x3 +#ifdef __IAR_SYSTEMS_ASM__ +#define nextInst $+2 +#else +#define nextInst .+0 +#endif + +;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 20 MHz -> 13.333333 cycles per bit, 106.666667 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts +;register use in receive loop: +; shift assembles the byte currently being received +; x1 holds the D+ and D- line state +; x2 holds the previous line state +; x4 (leap) is used to add a leap cycle once every three bytes received +; X3 (leap2) is used to add a leap cycle once every three stuff bits received +; bitcnt is used to determine when a stuff bit is due +; cnt holds the number of bytes left in the receive buffer + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt + push YL ;[-28] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-26] + push YL ;[-25] + push YH ;[-23] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-19] + rjmp foundK ;[-18] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-16] +;{3, 5} after falling D- edge, average delay: 4 cycles +;bit0 should be at 34 for center sampling. Currently at 4 so 30 cylces till bit 0 sample +;use 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push bitcnt ;[-16] +; [---] ;[-15] + lds YL, usbInputBufOffset;[-14] +; [---] ;[-13] + clr YH ;[-12] + subi YL, lo8(-(usbRxBuf));[-11] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-10] [rx loop init] + push shift ;[-9] +; [---] ;[-8] + ldi shift,0x40 ;[-7] set msb to "1" so processing bit7 can be detected + nop2 ;[-6] +; [---] ;[-5] + ldi bitcnt, 5 ;[-4] [rx loop init] + sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) + rjmp haveTwoBitsK ;[-2] + pop shift ;[-1] undo the push from before + pop bitcnt ;[1] + rjmp waitForK ;[3] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 27 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[0] + push x2 ;[2] + push x3 ;[4] (leap2) + ldi leap2, 0x55 ;[6] add leap cycle on 2nd,5th,8th,... stuff bit + push x4 ;[7] == leap + ldi leap, 0x55 ;[9] skip leap cycle on 2nd,5th,8th,... byte received + push cnt ;[10] + ldi cnt, USB_BUFSIZE ;[12] [rx loop init] + ldi x2, 1< +#ifndef __IAR_SYSTEMS_ASM__ +# include +#endif + +#define __attribute__(arg) /* not supported on IAR */ + +#ifdef __IAR_SYSTEMS_ASM__ +# define __ASSEMBLER__ /* IAR does not define standard macro for asm */ +#endif + +#ifdef __HAS_ELPM__ +# define PROGMEM __farflash +#else +# define PROGMEM __flash +#endif + +#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr)) + +/* The following definitions are not needed by the driver, but may be of some + * help if you port a gcc based project to IAR. + */ +#define cli() __disable_interrupt() +#define sei() __enable_interrupt() +#define wdt_reset() __watchdog_reset() +#define _BV(x) (1 << (x)) + +/* assembler compatibility macros */ +#define nop2 rjmp $+2 /* jump to next instruction */ +#define XL r26 +#define XH r27 +#define YL r28 +#define YH r29 +#define ZL r30 +#define ZH r31 +#define lo8(x) LOW(x) +#define hi8(x) (((x)>>8) & 0xff) /* not HIGH to allow XLINK to make a proper range check */ + +/* Depending on the device you use, you may get problems with the way usbdrv.h + * handles the differences between devices. Since IAR does not use #defines + * for MCU registers, we can't check for the existence of a particular + * register with an #ifdef. If the autodetection mechanism fails, include + * definitions for the required USB_INTR_* macros in your usbconfig.h. See + * usbconfig-prototype.h and usbdrv.h for details. + */ + +/* ------------------------------------------------------------------------- */ +#elif __CODEVISIONAVR__ /* check for CodeVision AVR */ +/* ------------------------------------------------------------------------- */ +/* This port is not working (yet) */ + +/* #define F_CPU _MCU_CLOCK_FREQUENCY_ seems to be defined automatically */ + +#include +#include + +#define __attribute__(arg) /* not supported on IAR */ + +#define PROGMEM __flash +#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr)) + +#ifndef __ASSEMBLER__ +static inline void cli(void) +{ + #asm("cli"); +} +static inline void sei(void) +{ + #asm("sei"); +} +#endif +#define _delay_ms(t) delay_ms(t) +#define _BV(x) (1 << (x)) +#define USB_CFG_USE_SWITCH_STATEMENT 1 /* macro for if() cascase fails for unknown reason */ + +#define macro .macro +#define endm .endmacro +#define nop2 rjmp .+0 /* jump to next instruction */ + +/* ------------------------------------------------------------------------- */ +#else /* default development environment is avr-gcc/avr-libc */ +/* ------------------------------------------------------------------------- */ + +#include +#ifdef __ASSEMBLER__ +# define _VECTOR(N) __vector_ ## N /* io.h does not define this for asm */ +#else +# include +#endif + +#define USB_READ_FLASH(addr) pgm_read_byte(addr) + +#define macro .macro +#define endm .endm +#define nop2 rjmp .+0 /* jump to next instruction */ + +#endif /* development environment */ + +/* for conveniecne, ensure that PRG_RDB exists */ +#ifndef PRG_RDB +# define PRG_RDB(addr) USB_READ_FLASH(addr) +#endif +#endif /* __usbportability_h_INCLUDED__ */ diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/ArduinoNotes.txt b/hardware/digistump/avr/libraries/DigisparkJoystick/ArduinoNotes.txt new file mode 100644 index 0000000..e05398b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/ArduinoNotes.txt @@ -0,0 +1,34 @@ +Notes On Integrating AVRUSB with Arduino +======================================== + +* Note the license(s) under which AVRUSB is distributed. + +* See also: http://code.rancidbacon.com/ProjectLogArduinoUSB + +* Note: The pins we use on the PCB (not protoboard) hardware shield are: + + INT0 == PD2 == IC Pin 4 == Arduino Digital Pin 2 == D+ + + ---- == PD4 == -------- == Arduino Digital Pin 4 == D- + + ---- == PD5 == -------- == Arduino Digital Pin 5 == pull-up + + (DONE: Change to not use PD3 so INT1 is left free?) + +* In order to compile a valid 'usbconfig.h' file must exit. The content of this + file will vary depending on whether the device is a generic USB device, + generic HID device or specific class of HID device for example. + + The file 'usbconfig-prototype.h' can be used as a starting point, however + it might be easier to use the 'usbconfig.h' from one of the example projects. + + TODO: Specify the settings that need to be changed to match the shield + design we use. + +* (NOTE: Initial 'usbconfig.h' used will be based on the file from + 'HIDKeys.2007-03-29'.) (Note: Have now upgraded to V-USB 2009-08-22.) + +* Versions of the Arduino IDE prior to 0018 won't compile our library + so it needs to be pre-compiled with: + + avr-g++ -Wall -Os -I. -DF_CPU=16000000 -mmcu=atmega168 -c usbdrvasm.S -c usbdrv.c diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/Changelog.txt b/hardware/digistump/avr/libraries/DigisparkJoystick/Changelog.txt new file mode 100644 index 0000000..655a9d4 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/Changelog.txt @@ -0,0 +1,296 @@ +This file documents changes in the firmware-only USB driver for atmel's AVR +microcontrollers. New entries are always appended to the end of the file. +Scroll down to the bottom to see the most recent changes. + +2005-04-01: + - Implemented endpoint 1 as interrupt-in endpoint. + - Moved all configuration options to usbconfig.h which is not part of the + driver. + - Changed interface for usbVendorSetup(). + - Fixed compatibility with ATMega8 device. + - Various minor optimizations. + +2005-04-11: + - Changed interface to application: Use usbFunctionSetup(), usbFunctionRead() + and usbFunctionWrite() now. Added configuration options to choose which + of these functions to compile in. + - Assembler module delivers receive data non-inverted now. + - Made register and bit names compatible with more AVR devices. + +2005-05-03: + - Allow address of usbRxBuf on any memory page as long as the buffer does + not cross 256 byte page boundaries. + - Better device compatibility: works with Mega88 now. + - Code optimization in debugging module. + - Documentation updates. + +2006-01-02: + - Added (free) default Vendor- and Product-IDs bought from voti.nl. + - Added USBID-License.txt file which defines the rules for using the free + shared VID/PID pair. + - Added Readme.txt to the usbdrv directory which clarifies administrative + issues. + +2006-01-25: + - Added "configured state" to become more standards compliant. + - Added "HALT" state for interrupt endpoint. + - Driver passes the "USB Command Verifier" test from usb.org now. + - Made "serial number" a configuration option. + - Minor optimizations, we now recommend compiler option "-Os" for best + results. + - Added a version number to usbdrv.h + +2006-02-03: + - New configuration variable USB_BUFFER_SECTION for the memory section where + the USB rx buffer will go. This defaults to ".bss" if not defined. Since + this buffer MUST NOT cross 256 byte pages (not even touch a page at the + end), the user may want to pass a linker option similar to + "-Wl,--section-start=.mybuffer=0x800060". + - Provide structure for usbRequest_t. + - New defines for USB constants. + - Prepared for HID implementations. + - Increased data size limit for interrupt transfers to 8 bytes. + - New macro usbInterruptIsReady() to query interrupt buffer state. + +2006-02-18: + - Ensure that the data token which is sent as an ack to an OUT transfer is + always zero sized. This fixes a bug where the host reports an error after + sending an out transfer to the device, although all data arrived at the + device. + - Updated docs in usbdrv.h to reflect changed API in usbFunctionWrite(). + +* Release 2006-02-20 + + - Give a compiler warning when compiling with debugging turned on. + - Added Oleg Semyonov's changes for IAR-cc compatibility. + - Added new (optional) functions usbDeviceConnect() and usbDeviceDisconnect() + (also thanks to Oleg!). + - Rearranged tests in usbPoll() to save a couple of instructions in the most + likely case that no actions are pending. + - We need a delay between the SET ADDRESS request until the new address + becomes active. This delay was handled in usbPoll() until now. Since the + spec says that the delay must not exceed 2ms, previous versions required + aggressive polling during the enumeration phase. We have now moved the + handling of the delay into the interrupt routine. + - We must not reply with NAK to a SETUP transaction. We can only achieve this + by making sure that the rx buffer is empty when SETUP tokens are expected. + We therefore don't pass zero sized data packets from the status phase of + a transfer to usbPoll(). This change MAY cause troubles if you rely on + receiving a less than 8 bytes long packet in usbFunctionWrite() to + identify the end of a transfer. usbFunctionWrite() will NEVER be called + with a zero length. + +* Release 2006-03-14 + + - Improved IAR C support: tiny memory model, more devices + - Added template usbconfig.h file under the name usbconfig-prototype.h + +* Release 2006-03-26 + + - Added provision for one more interrupt-in endpoint (endpoint 3). + - Added provision for one interrupt-out endpoint (endpoint 1). + - Added flowcontrol macros for USB. + - Added provision for custom configuration descriptor. + - Allow ANY two port bits for D+ and D-. + - Merged (optional) receive endpoint number into global usbRxToken variable. + - Use USB_CFG_IOPORTNAME instead of USB_CFG_IOPORT. We now construct the + variable name from the single port letter instead of computing the address + of related ports from the output-port address. + +* Release 2006-06-26 + + - Updated documentation in usbdrv.h and usbconfig-prototype.h to reflect the + new features. + - Removed "#warning" directives because IAR does not understand them. Use + unused static variables instead to generate a warning. + - Do not include when compiling with IAR. + - Introduced USB_CFG_DESCR_PROPS_* in usbconfig.h to configure how each + USB descriptor should be handled. It is now possible to provide descriptor + data in Flash, RAM or dynamically at runtime. + - STALL is now a status in usbTxLen* instead of a message. We can now conform + to the spec and leave the stall status pending until it is cleared. + - Made usbTxPacketCnt1 and usbTxPacketCnt3 public. This allows the + application code to reset data toggling on interrupt pipes. + +* Release 2006-07-18 + + - Added an #if !defined __ASSEMBLER__ to the warning in usbdrv.h. This fixes + an assembler error. + - usbDeviceDisconnect() takes pull-up resistor to high impedance now. + +* Release 2007-02-01 + + - Merged in some code size improvements from usbtiny (thanks to Dick + Streefland for these optimizations!) + - Special alignment requirement for usbRxBuf not required any more. Thanks + again to Dick Streefland for this hint! + - Reverted to "#warning" instead of unused static variables -- new versions + of IAR CC should handle this directive. + - Changed Open Source license to GNU GPL v2 in order to make linking against + other free libraries easier. We no longer require publication of the + circuit diagrams, but we STRONGLY encourage it. If you improve the driver + itself, PLEASE grant us a royalty free license to your changes for our + commercial license. + +* Release 2007-03-29 + + - New configuration option "USB_PUBLIC" in usbconfig.h. + - Set USB version number to 1.10 instead of 1.01. + - Code used USB_CFG_DESCR_PROPS_STRING_DEVICE and + USB_CFG_DESCR_PROPS_STRING_PRODUCT inconsistently. Changed all occurrences + to USB_CFG_DESCR_PROPS_STRING_PRODUCT. + - New assembler module for 16.5 MHz RC oscillator clock with PLL in receiver + code. + - New assembler module for 16 MHz crystal. + - usbdrvasm.S contains common code only, clock-specific parts have been moved + to usbdrvasm12.S, usbdrvasm16.S and usbdrvasm165.S respectively. + +* Release 2007-06-25 + + - 16 MHz module: Do SE0 check in stuffed bits as well. + +* Release 2007-07-07 + + - Define hi8(x) for IAR compiler to limit result to 8 bits. This is necessary + for negative values. + - Added 15 MHz module contributed by V. Bosch. + - Interrupt vector name can now be configured. This is useful if somebody + wants to use a different hardware interrupt than INT0. + +* Release 2007-08-07 + + - Moved handleIn3 routine in usbdrvasm16.S so that relative jump range is + not exceeded. + - More config options: USB_RX_USER_HOOK(), USB_INITIAL_DATATOKEN, + USB_COUNT_SOF + - USB_INTR_PENDING can now be a memory address, not just I/O + +* Release 2007-09-19 + + - Split out common parts of assembler modules into separate include file + - Made endpoint numbers configurable so that given interface definitions + can be matched. See USB_CFG_EP3_NUMBER in usbconfig-prototype.h. + - Store endpoint number for interrupt/bulk-out so that usbFunctionWriteOut() + can handle any number of endpoints. + - Define usbDeviceConnect() and usbDeviceDisconnect() even if no + USB_CFG_PULLUP_IOPORTNAME is defined. Directly set D+ and D- to 0 in this + case. + +* Release 2007-12-01 + + - Optimize usbDeviceConnect() and usbDeviceDisconnect() for less code size + when USB_CFG_PULLUP_IOPORTNAME is not defined. + +* Release 2007-12-13 + + - Renamed all include-only assembler modules from *.S to *.inc so that + people don't add them to their project sources. + - Distribute leap bits in tx loop more evenly for 16 MHz module. + - Use "macro" and "endm" instead of ".macro" and ".endm" for IAR + - Avoid compiler warnings for constant expr range by casting some values in + USB descriptors. + +* Release 2008-01-21 + + - Fixed bug in 15 and 16 MHz module where the new address set with + SET_ADDRESS was already accepted at the next NAK or ACK we send, not at + the next data packet we send. This caused problems when the host polled + too fast. Thanks to Alexander Neumann for his help and patience debugging + this issue! + +* Release 2008-02-05 + + - Fixed bug in 16.5 MHz module where a register was used in the interrupt + handler before it was pushed. This bug was introduced with version + 2007-09-19 when common parts were moved to a separate file. + - Optimized CRC routine (thanks to Reimar Doeffinger). + +* Release 2008-02-16 + + - Removed outdated IAR compatibility stuff (code sections). + - Added hook macros for USB_RESET_HOOK() and USB_SET_ADDRESS_HOOK(). + - Added optional routine usbMeasureFrameLength() for calibration of the + internal RC oscillator. + +* Release 2008-02-28 + + - USB_INITIAL_DATATOKEN defaults to USBPID_DATA1 now, which means that we + start with sending USBPID_DATA0. + - Changed defaults in usbconfig-prototype.h + - Added free USB VID/PID pair for MIDI class devices + - Restructured AVR-USB as separate package, not part of PowerSwitch any more. + +* Release 2008-04-18 + + - Restructured usbdrv.c so that it is easier to read and understand. + - Better code optimization with gcc 4. + - If a second interrupt in endpoint is enabled, also add it to config + descriptor. + - Added config option for long transfers (above 254 bytes), see + USB_CFG_LONG_TRANSFERS in usbconfig.h. + - Added 20 MHz module contributed by Jeroen Benschop. + +* Release 2008-05-13 + + - Fixed bug in libs-host/hiddata.c function usbhidGetReport(): length + was not incremented, pointer to length was incremented instead. + - Added code to command line tool(s) which claims an interface. This code + is disabled by default, but may be necessary on newer Linux kernels. + - Added usbconfig.h option "USB_CFG_CHECK_DATA_TOGGLING". + - New header "usbportability.h" prepares ports to other development + environments. + - Long transfers (above 254 bytes) did not work when usbFunctionRead() was + used to supply the data. Fixed this bug. [Thanks to Alexander Neumann!] + - In hiddata.c (example code for sending/receiving data over HID), use + USB_RECIP_DEVICE instead of USB_RECIP_INTERFACE for control transfers so + that we need not claim the interface. + - in usbPoll() loop 20 times polling for RESET state instead of 10 times. + This accounts for the higher clock rates we now support. + - Added a module for 12.8 MHz RC oscillator with PLL in receiver loop. + - Added hook to SOF code so that oscillator can be tuned to USB frame clock. + - Added timeout to waitForJ loop. Helps preventing unexpected hangs. + - Added example code for oscillator tuning to libs-device (thanks to + Henrik Haftmann for the idea to this routine). + - Implemented option USB_CFG_SUPPRESS_INTR_CODE. + +* Release 2008-10-22 + + - Fixed libs-device/osctune.h: OSCCAL is memory address on ATMega88 and + similar, not offset of 0x20 needs to be added. + - Allow distribution under GPLv3 for those who have to link against other + code distributed under GPLv3. + +* Release 2008-11-26 + + - Removed libusb-win32 dependency for hid-data example in Makefile.windows. + It was never required and confused many people. + - Added extern uchar usbRxToken to usbdrv.h. + - Integrated a module with CRC checks at 18 MHz by Lukas Schrittwieser. + +* Release 2009-03-23 + + - Hid-mouse example used settings from hid-data example, fixed that. + - Renamed project to V-USB due to a trademark issue with Atmel(r). + - Changed CommercialLicense.txt and USBID-License.txt to make the + background of USB ID registration clearer. + +* Release 2009-04-15 + + - Changed CommercialLicense.txt to reflect the new range of PIDs from + Jason Kotzin. + - Removed USBID-License.txt in favor of USB-IDs-for-free.txt and + USB-ID-FAQ.txt + - Fixed a bug in the 12.8 MHz module: End Of Packet decection was made in + the center between bit 0 and 1 of each byte. This is where the data lines + are expected to change and the sampled data may therefore be nonsense. + We therefore check EOP ONLY if bits 0 AND 1 have both been read as 0 on D-. + - Fixed a bitstuffing problem in the 16 MHz module: If bit 6 was stuffed, + the unstuffing code in the receiver routine was 1 cycle too long. If + multiple bytes had the unstuffing in bit 6, the error summed up until the + receiver was out of sync. + - Included option for faster CRC routine. + Thanks to Slawomir Fras (BoskiDialer) for this code! + - Updated bits in Configuration Descriptor's bmAttributes according to + USB 1.1 (in particular bit 7, it is a must-be-set bit now). + +* Release 2009-08-22 diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/CommercialLicense.txt b/hardware/digistump/avr/libraries/DigisparkJoystick/CommercialLicense.txt new file mode 100644 index 0000000..11d07d9 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/CommercialLicense.txt @@ -0,0 +1,166 @@ +V-USB Driver Software License Agreement +Version 2009-08-03 + +THIS LICENSE AGREEMENT GRANTS YOU CERTAIN RIGHTS IN A SOFTWARE. YOU CAN +ENTER INTO THIS AGREEMENT AND ACQUIRE THE RIGHTS OUTLINED BELOW BY PAYING +THE AMOUNT ACCORDING TO SECTION 4 ("PAYMENT") TO OBJECTIVE DEVELOPMENT. + + +1 DEFINITIONS + +1.1 "OBJECTIVE DEVELOPMENT" shall mean OBJECTIVE DEVELOPMENT Software GmbH, +Grosse Schiffgasse 1A/7, 1020 Wien, AUSTRIA. + +1.2 "You" shall mean the Licensee. + +1.3 "V-USB" shall mean all files included in the package distributed under +the name "vusb" by OBJECTIVE DEVELOPMENT (http://www.obdev.at/vusb/) +unless otherwise noted. This includes the firmware-only USB device +implementation for Atmel AVR microcontrollers, some simple device examples +and host side software examples and libraries. + + +2 LICENSE GRANTS + +2.1 Source Code. OBJECTIVE DEVELOPMENT shall furnish you with the source +code of V-USB. + +2.2 Distribution and Use. OBJECTIVE DEVELOPMENT grants you the +non-exclusive right to use, copy and distribute V-USB with your hardware +product(s), restricted by the limitations in section 3 below. + +2.3 Modifications. OBJECTIVE DEVELOPMENT grants you the right to modify +the source code and your copy of V-USB according to your needs. + +2.4 USB IDs. OBJECTIVE DEVELOPMENT furnishes you with one or two USB +Product ID(s), sent to you in e-mail. These Product IDs are reserved +exclusively for you. OBJECTIVE DEVELOPMENT has obtained USB Product ID +ranges under the Vendor ID 5824 from Wouter van Ooijen (Van Ooijen +Technische Informatica, www.voti.nl) and under the Vendor ID 8352 from +Jason Kotzin (Clay Logic, www.claylogic.com). Both owners of the Vendor IDs +have obtained these IDs from the USB Implementers Forum, Inc. +(www.usb.org). OBJECTIVE DEVELOPMENT disclaims all liability which might +arise from the assignment of USB IDs. + +2.5 USB Certification. Although not part of this agreement, we want to make +it clear that you cannot become USB certified when you use V-USB or a USB +Product ID assigned by OBJECTIVE DEVELOPMENT. AVR microcontrollers don't +meet the electrical specifications required by the USB specification and +the USB Implementers Forum certifies only members who bought a Vendor ID of +their own. + + +3 LICENSE RESTRICTIONS + +3.1 Number of Units. Only one of the following three definitions is +applicable. Which one is determined by the amount you pay to OBJECTIVE +DEVELOPMENT, see section 4 ("Payment") below. + +Hobby License: You may use V-USB according to section 2 above in no more +than 5 hardware units. These units must not be sold for profit. + +Entry Level License: You may use V-USB according to section 2 above in no +more than 150 hardware units. + +Professional License: You may use V-USB according to section 2 above in +any number of hardware units, except for large scale production ("unlimited +fair use"). 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This document represents the entire agreement between +OBJECTIVE DEVELOPMENT and you. It may only be modified in writing signed by +an authorized representative of both, OBJECTIVE DEVELOPMENT and you. + +8.3 Severability. In case a provision of these terms and conditions should +be or become partly or entirely invalid, ineffective, or not executable, +the validity of all other provisions shall not be affected. + +8.4 Applicable Law. This agreement is governed by the laws of the Republic +of Austria. + +8.5 Responsible Courts. The responsible courts in Vienna/Austria will have +exclusive jurisdiction regarding all disputes in connection with this +agreement. + diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/DigiJoystick.h b/hardware/digistump/avr/libraries/DigisparkJoystick/DigiJoystick.h new file mode 100644 index 0000000..11c8a5c --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/DigiJoystick.h @@ -0,0 +1,325 @@ +/* + * Based on Obdev's AVRUSB code and under the same license. + * + * TODO: Make a proper file header. :-) + * Modified for Digispark by Digistump + * And now modified by Sean Murphy (duckythescientist) from a keyboard device to a joystick device + * And now modified by Bluebie to have better code style, not ruin system timers, and have delay() function + * Most of the credit for the joystick code should go to Raphaël Assénat + */ +#ifndef __DigiJoystick_h__ +#define __DigiJoystick_h__ + +#define GCN64_REPORT_SIZE 8 + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "usbdrv.h" +//#include "devdesc.h" +#include "oddebug.h" +#include "usbconfig.h" + +const static uchar *rt_usbHidReportDescriptor=NULL; +static uchar rt_usbHidReportDescriptorSize=0; +const static uchar *rt_usbDeviceDescriptor=NULL; +static uchar rt_usbDeviceDescriptorSize=0; + +// TODO: Work around Arduino 12 issues better. +//#include +//#undef int() + +//typedef uint8_t byte; + +/* What was most recently read from the controller */ +unsigned char last_built_report[GCN64_REPORT_SIZE]; + +/* What was most recently sent to the host */ +unsigned char last_sent_report[GCN64_REPORT_SIZE]; + +uchar reportBuffer[8]; + +// report frequency set to default of 50hz +#define DIGIJOYSTICK_DEFAULT_REPORT_INTERVAL 20 +static unsigned char must_report = 0; +static unsigned char idle_rate = DIGIJOYSTICK_DEFAULT_REPORT_INTERVAL / 4; // in units of 4ms +// new minimum report frequency system: +static unsigned long last_report_time = 0; + + +const unsigned char gcn64_usbHidReportDescriptor[] PROGMEM = { + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x05, // USAGE (Gamepad) + 0xa1, 0x01, // COLLECTION (Application) + + 0x09, 0x01, // USAGE (Pointer) + 0xa1, 0x00, // COLLECTION (Physical) + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x30, // USAGE (X) + 0x09, 0x31, // USAGE (Y) + + 0x09, 0x33, // USAGE (Rx) + 0x09, 0x34, // USAGE (Ry) + + 0x09, 0x35, // USAGE (Rz) + 0x09, 0x36, // USAGE (Slider) + + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x26, 0xFF, 0x00, // LOGICAL_MAXIMUM (255) + 0x75, 0x08, // REPORT_SIZE (8) + 0x95, 0x06, // REPORT_COUNT (6) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0xc0, // END_COLLECTION (Physical) + + 0x05, 0x09, // USAGE_PAGE (Button) + 0x19, 0x01, // USAGE_MINIMUM (Button 1) + 0x29, 0x10, // USAGE_MAXIMUM (Button 14) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x75, 0x01, // REPORT_SIZE (1) + 0x95, 0x10, // REPORT_COUNT (16) + 0x81, 0x02, // INPUT (Data,Var,Abs) + + 0xc0 // END_COLLECTION (Application) +}; + +#define USBDESCR_DEVICE 1 + +const unsigned char usbDescrDevice[] PROGMEM = { /* USB device descriptor */ + 18, /* sizeof(usbDescrDevice): length of descriptor in bytes */ + USBDESCR_DEVICE, /* descriptor type */ + 0x01, 0x01, /* USB version supported */ + USB_CFG_DEVICE_CLASS, + USB_CFG_DEVICE_SUBCLASS, + 0, /* protocol */ + 8, /* max packet size */ + USB_CFG_VENDOR_ID, /* 2 bytes */ + USB_CFG_DEVICE_ID, /* 2 bytes */ + USB_CFG_DEVICE_VERSION, /* 2 bytes */ +#if USB_CFG_VENDOR_NAME_LEN + 1, /* manufacturer string index */ +#else + 0, /* manufacturer string index */ +#endif +#if USB_CFG_DEVICE_NAME_LEN + 2, /* product string index */ +#else + 0, /* product string index */ +#endif +#if USB_CFG_SERIAL_NUMBER_LENGTH + 3, /* serial number string index */ +#else + 0, /* serial number string index */ +#endif + 1, /* number of configurations */ +}; + + + +void gamecubeBuildReport(unsigned char *reportBuf) { + if (reportBuf != NULL) { + memcpy(reportBuf, last_built_report, GCN64_REPORT_SIZE); + } + + memcpy(last_sent_report, last_built_report, GCN64_REPORT_SIZE); +} + +int getGamepadReport(unsigned char *dstbuf) { + gamecubeBuildReport(dstbuf); + return GCN64_REPORT_SIZE; +} + + +class DigiJoystickDevice { + public: + DigiJoystickDevice () { + cli(); + usbDeviceDisconnect(); + _delay_ms(250); + usbDeviceConnect(); + + rt_usbHidReportDescriptor = gcn64_usbHidReportDescriptor; + rt_usbHidReportDescriptorSize = sizeof(gcn64_usbHidReportDescriptor); + rt_usbDeviceDescriptor = usbDescrDevice; + rt_usbDeviceDescriptorSize = sizeof(usbDescrDevice); + + usbInit(); + + sei(); + + last_report_time = millis(); + } + + void update() { + usbPoll(); + + // instead of above code, use millis arduino system to enforce minimum reporting frequency + unsigned long time_since_last_report = millis() - last_report_time; + if (time_since_last_report >= (idle_rate * 4 /* in units of 4ms - usb spec stuff */)) { + last_report_time += idle_rate * 4; + must_report = 1; + } + + // if the report has changed, try force an update anyway + if (memcmp(last_built_report, last_sent_report, GCN64_REPORT_SIZE)) { + must_report = 1; + } + + // if we want to send a report, signal the host computer to ask us for it with a usb 'interrupt' + if (must_report) { + if (usbInterruptIsReady()) { + must_report = 0; + + gamecubeBuildReport(reportBuffer); + usbSetInterrupt(reportBuffer, GCN64_REPORT_SIZE); + } + } + } + + // delay while updating until we are finished delaying + void delay(long milli) { + unsigned long last = millis(); + while (milli > 0) { + unsigned long now = millis(); + milli -= now - last; + last = now; + update(); + } + } + + void setX(byte value) { + last_built_report[0] = value; + } + + void setY(byte value) { + last_built_report[1] = value; + } + + void setXROT(byte value) { + last_built_report[2] = value; + } + + void setYROT(byte value) { + last_built_report[3] = value; + } + + void setZROT(byte value) { + last_built_report[4] = value; + } + + void setSLIDER(byte value) { + last_built_report[5] = value; + } + + void setX(char value) { + setX(*(reinterpret_cast(&value))); + } + + void setY(char value) { + setY(*(reinterpret_cast(&value))); + } + + void setXROT(char value) { + setXROT(*(reinterpret_cast(&value))); + } + + void setYROT(char value) { + setYROT(*(reinterpret_cast(&value))); + } + + void setZROT(char value) { + setZROT(*(reinterpret_cast(&value))); + } + void setSLIDER(char value) { + setSLIDER(*(reinterpret_cast(&value))); + } + + void setButtons(unsigned char low, unsigned char high) { + last_built_report[6] = low; + last_built_report[7] = high; + } + + void setButtons(char low,char high) { + setButtons(*reinterpret_cast(&low),*reinterpret_cast(&high)); + } + + void setValues(unsigned char values[]) { + memcpy(last_built_report, values, GCN64_REPORT_SIZE); + } + + void setValues(char values[]) { + unsigned char *foo = reinterpret_cast(values);//preserves bit values in cast + memcpy(last_built_report, foo, GCN64_REPORT_SIZE); + } +}; + +// Create global singleton object for users to make use of +DigiJoystickDevice DigiJoystick = DigiJoystickDevice(); + + + + + +#ifdef __cplusplus +extern "C"{ +#endif + // USB_PUBLIC uchar usbFunctionSetup + + uchar usbFunctionSetup(uchar data[8]) { + usbRequest_t *rq = (usbRequest_t *)data; + + usbMsgPtr = reportBuffer; + if ((rq->bmRequestType & USBRQ_TYPE_MASK) == USBRQ_TYPE_CLASS) { // class request type + if (rq->bRequest == USBRQ_HID_GET_REPORT){ // wValue: ReportType (highbyte), ReportID (lowbyte) + // we only have one report type, so don't look at wValue + //curGamepad->buildReport(reportBuffer); + //return curGamepad->report_size; + return GCN64_REPORT_SIZE; + } else if (rq->bRequest == USBRQ_HID_GET_IDLE) { + usbMsgPtr = &idle_rate; + return 1; + } else if (rq->bRequest == USBRQ_HID_SET_IDLE) { + idle_rate = rq->wValue.bytes[1]; + } + } else { + /* no vendor specific requests implemented */ + } + return 0; + } + + uchar usbFunctionDescriptor(struct usbRequest *rq) { + if ((rq->bmRequestType & USBRQ_TYPE_MASK) != USBRQ_TYPE_STANDARD) { + return 0; + } + + if (rq->bRequest == USBRQ_GET_DESCRIPTOR) { + // USB spec 9.4.3, high byte is descriptor type + switch (rq->wValue.bytes[1]) { + case USBDESCR_DEVICE: + usbMsgPtr = rt_usbDeviceDescriptor; + return rt_usbDeviceDescriptorSize; + break; + + case USBDESCR_HID_REPORT: + usbMsgPtr = rt_usbHidReportDescriptor; + return rt_usbHidReportDescriptorSize; + break; + + } + } + + return 0; + } + +#ifdef __cplusplus +} // extern "C" +#endif + + +#endif // __DigiKeyboard_h__ diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/DigiKeyboard.h.old b/hardware/digistump/avr/libraries/DigisparkJoystick/DigiKeyboard.h.old new file mode 100644 index 0000000..3ff0df5 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/DigiKeyboard.h.old @@ -0,0 +1,230 @@ +/* + * Based on Obdev's AVRUSB code and under the same license. + * + * TODO: Make a proper file header. :-) + * Modified for Digispark by Digistump + */ +#ifndef __DigiKeyboard_h__ +#define __DigiKeyboard_h__ + +#include +#include +#include +#include + +#include "usbdrv.h" + +// TODO: Work around Arduino 12 issues better. +//#include +//#undef int() + +typedef uint8_t byte; + + +#define BUFFER_SIZE 2 // Minimum of 2: 1 for modifiers + 1 for keystroke + + +static uchar idleRate; // in 4 ms units + + +/* We use a simplifed keyboard report descriptor which does not support the + * boot protocol. We don't allow setting status LEDs and but we do allow + * simultaneous key presses. + * The report descriptor has been created with usb.org's "HID Descriptor Tool" + * which can be downloaded from http://www.usb.org/developers/hidpage/. + * Redundant entries (such as LOGICAL_MINIMUM and USAGE_PAGE) have been omitted + * for the second INPUT item. + */ +PROGMEM char usbHidReportDescriptor[USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH] = { /* USB report descriptor */ + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x06, // USAGE (Keyboard) + 0xa1, 0x01, // COLLECTION (Application) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + 0x19, 0xe0, // USAGE_MINIMUM (Keyboard LeftControl) + 0x29, 0xe7, // USAGE_MAXIMUM (Keyboard Right GUI) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x75, 0x01, // REPORT_SIZE (1) + 0x95, 0x08, // REPORT_COUNT (8) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (simultaneous keystrokes) + 0x75, 0x08, // REPORT_SIZE (8) + 0x25, 0x65, // LOGICAL_MAXIMUM (101) + 0x19, 0x00, // USAGE_MINIMUM (Reserved (no event indicated)) + 0x29, 0x65, // USAGE_MAXIMUM (Keyboard Application) + 0x81, 0x00, // INPUT (Data,Ary,Abs) + 0xc0 // END_COLLECTION +}; + + + +/* Keyboard usage values, see usb.org's HID-usage-tables document, chapter + * 10 Keyboard/Keypad Page for more codes. + */ +#define MOD_CONTROL_LEFT (1<<0) +#define MOD_SHIFT_LEFT (1<<1) +#define MOD_ALT_LEFT (1<<2) +#define MOD_GUI_LEFT (1<<3) +#define MOD_CONTROL_RIGHT (1<<4) +#define MOD_SHIFT_RIGHT (1<<5) +#define MOD_ALT_RIGHT (1<<6) +#define MOD_GUI_RIGHT (1<<7) + +#define KEY_A 4 +#define KEY_B 5 +#define KEY_C 6 +#define KEY_D 7 +#define KEY_E 8 +#define KEY_F 9 +#define KEY_G 10 +#define KEY_H 11 +#define KEY_I 12 +#define KEY_J 13 +#define KEY_K 14 +#define KEY_L 15 +#define KEY_M 16 +#define KEY_N 17 +#define KEY_O 18 +#define KEY_P 19 +#define KEY_Q 20 +#define KEY_R 21 +#define KEY_S 22 +#define KEY_T 23 +#define KEY_U 24 +#define KEY_V 25 +#define KEY_W 26 +#define KEY_X 27 +#define KEY_Y 28 +#define KEY_Z 29 +#define KEY_1 30 +#define KEY_2 31 +#define KEY_3 32 +#define KEY_4 33 +#define KEY_5 34 +#define KEY_6 35 +#define KEY_7 36 +#define KEY_8 37 +#define KEY_9 38 +#define KEY_0 39 + +#define KEY_ENTER 40 + +#define KEY_SPACE 44 + +#define KEY_F1 58 +#define KEY_F2 59 +#define KEY_F3 60 +#define KEY_F4 61 +#define KEY_F5 62 +#define KEY_F6 63 +#define KEY_F7 64 +#define KEY_F8 65 +#define KEY_F9 66 +#define KEY_F10 67 +#define KEY_F11 68 +#define KEY_F12 69 + +#define KEY_ARROW_LEFT 0x50 + + +class DigiKeyboardDevice { + public: + DigiKeyboardDevice () { + TIMSK &= !(1bmRequestType & USBRQ_TYPE_MASK) == USBRQ_TYPE_CLASS){ + /* class request type */ + + if(rq->bRequest == USBRQ_HID_GET_REPORT){ + /* wValue: ReportType (highbyte), ReportID (lowbyte) */ + + /* we only have one report type, so don't look at wValue */ + // TODO: Ensure it's okay not to return anything here? + return 0; + + }else if(rq->bRequest == USBRQ_HID_GET_IDLE){ + // usbMsgPtr = &idleRate; + // return 1; + return 0; + }else if(rq->bRequest == USBRQ_HID_SET_IDLE){ + idleRate = rq->wValue.bytes[1]; + } + }else{ + /* no vendor specific requests implemented */ + } + return 0; + } +#ifdef __cplusplus +} // extern "C" +#endif + + +#endif // __DigiKeyboard_h__ diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/JoystickReadme.txt b/hardware/digistump/avr/libraries/DigisparkJoystick/JoystickReadme.txt new file mode 100644 index 0000000..64ce3d9 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/JoystickReadme.txt @@ -0,0 +1,11 @@ +JoystickReadme.txt + +This library is for the attiny85 running tiny core Arduino (e.g. the Digispark) + +This implements a USB HID joystick device (currently 6 analog and 16 digital) +The code was borrowed mostly from the Digispark Keyboard library and from Raphaël Assénat's code on using an atmega8 as a Nintendo Gamecube/N64 controller to USB bridge: http://www.raphnet.net/electronique/gc_n64_usb/index_en.php +Raphaël's work is truly marvelous. + +Because most of this code is coming from other projects with GNU GPL, I am letting my modifications inherit the same protection. A copy of this license is included in the source. + +As to the use of this code in Arduino, include DigiJoystick.h as you would any other library. See the included sample for use of the functions. diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/License.txt b/hardware/digistump/avr/libraries/DigisparkJoystick/License.txt new file mode 100644 index 0000000..4460cfb --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/License.txt @@ -0,0 +1,361 @@ +OBJECTIVE DEVELOPMENT GmbH's V-USB driver software is distributed under the +terms and conditions of the GNU GPL version 2 or the GNU GPL version 3. It is +your choice whether you apply the terms of version 2 or version 3. The full +text of GPLv2 is included below. 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The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and "any +later version", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + + 10. If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/Readme.txt b/hardware/digistump/avr/libraries/DigisparkJoystick/Readme.txt new file mode 100644 index 0000000..a010d97 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/Readme.txt @@ -0,0 +1,158 @@ +This is the Readme file to Objective Development's firmware-only USB driver +for Atmel AVR microcontrollers. For more information please visit +http://www.obdev.at/vusb/ + +This directory contains the USB firmware only. Copy it as-is to your own +project and add all .c and .S files to your project (these files are marked +with an asterisk in the list below). Then copy usbconfig-prototype.h as +usbconfig.h to your project and edit it according to your configuration. + + +TECHNICAL DOCUMENTATION +======================= +The technical documentation (API) for the firmware driver is contained in the +file "usbdrv.h". Please read all of it carefully! Configuration options are +documented in "usbconfig-prototype.h". + +The driver consists of the following files: + Readme.txt ............. The file you are currently reading. + Changelog.txt .......... Release notes for all versions of the driver. + usbdrv.h ............... Driver interface definitions and technical docs. +* usbdrv.c ............... High level language part of the driver. Link this + module to your code! +* usbdrvasm.S ............ Assembler part of the driver. This module is mostly + a stub and includes one of the usbdrvasm*.S files + depending on processor clock. Link this module to + your code! + usbdrvasm*.inc ......... Assembler routines for particular clock frequencies. + Included by usbdrvasm.S, don't link it directly! + asmcommon.inc .......... Common assembler routines. Included by + usbdrvasm*.inc, don't link it directly! + usbconfig-prototype.h .. Prototype for your own usbdrv.h file. +* oddebug.c .............. Debug functions. Only used when DEBUG_LEVEL is + defined to a value greater than 0. Link this module + to your code! + oddebug.h .............. Interface definitions of the debug module. + usbportability.h ....... Header with compiler-dependent stuff. + usbdrvasm.asm .......... Compatibility stub for IAR-C-compiler. Use this + module instead of usbdrvasm.S when you assembler + with IAR's tools. + License.txt ............ Open Source license for this driver. + CommercialLicense.txt .. Optional commercial license for this driver. + USB-ID-FAQ.txt ......... General infos about USB Product- and Vendor-IDs. + USB-IDs-for-free.txt ... List and terms of use for free shared PIDs. + +(*) ... These files should be linked to your project. + + +CPU CORE CLOCK FREQUENCY +======================== +We supply assembler modules for clock frequencies of 12 MHz, 12.8 MHz, 15 MHz, +16 MHz, 16.5 MHz 18 MHz and 20 MHz. Other clock rates are not supported. The +actual clock rate must be configured in usbdrv.h unless you use the default +12 MHz. + +12 MHz Clock +This is the traditional clock rate of V-USB because it's the lowest clock +rate where the timing constraints of the USB spec can be met. + +15 MHz Clock +Similar to 12 MHz, but some NOPs inserted. On the other hand, the higher clock +rate allows for some loops which make the resulting code size somewhat smaller +than the 12 MHz version. + +16 MHz Clock +This clock rate has been added for users of the Arduino board and other +ready-made boards which come with a fixed 16 MHz crystal. It's also an option +if you need the slightly higher clock rate for performance reasons. Since +16 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code +is somewhat tricky and has to insert a leap cycle every third byte. + +12.8 MHz and 16.5 MHz Clock +The assembler modules for these clock rates differ from the other modules +because they have been built for an RC oscillator with only 1% precision. The +receiver code inserts leap cycles to compensate for clock deviations. 1% is +also the precision which can be achieved by calibrating the internal RC +oscillator of the AVR. Please note that only AVRs with internal 64 MHz PLL +oscillator can reach 16.5 MHz with the RC oscillator. This includes the very +popular ATTiny25, ATTiny45, ATTiny85 series as well as the ATTiny26. Almost +all AVRs can reach 12.8 MHz, although this is outside the specified range. + +See the EasyLogger example at http://www.obdev.at/vusb/easylogger.html for +code which calibrates the RC oscillator based on the USB frame clock. + +18 MHz Clock +This module is closer to the USB specification because it performs an on the +fly CRC check for incoming packets. Packets with invalid checksum are +discarded as required by the spec. If you also implement checks for data +PID toggling on application level (see option USB_CFG_CHECK_DATA_TOGGLING +in usbconfig.h for more info), this ensures data integrity. Due to the CRC +tables and alignment requirements, this code is bigger than modules for other +clock rates. To activate this module, you must define USB_CFG_CHECK_CRC to 1 +and USB_CFG_CLOCK_KHZ to 18000 in usbconfig.h. + +20 MHz Clock +This module is for people who won't do it with less than the maximum. Since +20 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code +uses similar tricks as the 16 MHz module to insert leap cycles. + + +USB IDENTIFIERS +=============== +Every USB device needs a vendor- and a product-identifier (VID and PID). VIDs +are obtained from usb.org for a price of 1,500 USD. Once you have a VID, you +can assign PIDs at will. + +Since an entry level cost of 1,500 USD is too high for most small companies +and hobbyists, we provide some VID/PID pairs for free. See the file +USB-IDs-for-free.txt for details. + +Objective Development also has some license offerings which include product +IDs. See http://www.obdev.at/vusb/ for details. + + +DEVELOPMENT SYSTEM +================== +This driver has been developed and optimized for the GNU compiler version 3 +(gcc 3). It does work well with gcc 4, but with bigger code size. We recommend +that you use the GNU compiler suite because it is freely available. V-USB +has also been ported to the IAR compiler and assembler. It has been tested +with IAR 4.10B/W32 and 4.12A/W32 on an ATmega8 with the "small" and "tiny" +memory model. Not every release is tested with IAR CC and the driver may +therefore fail to compile with IAR. Please note that gcc is more efficient for +usbdrv.c because this module has been deliberately optimized for gcc. + + +USING V-USB FOR FREE +==================== +The AVR firmware driver is published under the GNU General Public License +Version 2 (GPL2) and the GNU General Public License Version 3 (GPL3). It is +your choice whether you apply the terms of version 2 or version 3. + +If you decide for the free GPL2 or GPL3, we STRONGLY ENCOURAGE you to do the +following things IN ADDITION to the obligations from the GPL: + +(1) Publish your entire project on a web site and drop us a note with the URL. +Use the form at http://www.obdev.at/vusb/feedback.html for your submission. +If you don't have a web site, you can publish the project in obdev's +documentation wiki at +http://www.obdev.at/goto.php?t=vusb-wiki&p=hosted-projects. + +(2) Adhere to minimum publication standards. Please include AT LEAST: + - a circuit diagram in PDF, PNG or GIF format + - full source code for the host software + - a Readme.txt file in ASCII format which describes the purpose of the + project and what can be found in which directories and which files + - a reference to http://www.obdev.at/vusb/ + +(3) If you improve the driver firmware itself, please give us a free license +to your modifications for our commercial license offerings. + + +COMMERCIAL LICENSES FOR V-USB +============================= +If you don't want to publish your source code under the terms of the GPL, +you can simply pay money for V-USB. As an additional benefit you get +USB PIDs for free, reserved exclusively to you. See the file +"CommercialLicense.txt" for details. + diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/USB-ID-FAQ.txt b/hardware/digistump/avr/libraries/DigisparkJoystick/USB-ID-FAQ.txt new file mode 100644 index 0000000..d1de8fb --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/USB-ID-FAQ.txt @@ -0,0 +1,149 @@ +Version 2009-08-22 + +========================== +WHY DO WE NEED THESE IDs? +========================== + +USB is more than a low level protocol for data transport. It also defines a +common set of requests which must be understood by all devices. And as part +of these common requests, the specification defines data structures, the +USB Descriptors, which are used to describe the properties of the device. + +From the perspective of an operating system, it is therefore possible to find +out basic properties of a device (such as e.g. the manufacturer and the name +of the device) without a device-specific driver. This is essential because +the operating system can choose a driver to load based on this information +(Plug-And-Play). + +Among the most important properties in the Device Descriptor are the USB +Vendor- and Product-ID. Both are 16 bit integers. The most simple form of +driver matching is based on these IDs. The driver announces the Vendor- and +Product-IDs of the devices it can handle and the operating system loads the +appropriate driver when the device is connected. + +It is obvious that this technique only works if the pair Vendor- plus +Product-ID is unique: Only devices which require the same driver can have the +same pair of IDs. + + +===================================================== +HOW DOES THE USB STANDARD ENSURE THAT IDs ARE UNIQUE? +===================================================== + +Since it is so important that USB IDs are unique, the USB Implementers Forum, +Inc. (usb.org) needs a way to enforce this legally. It is not forbidden by +law to build a device and assign it any random numbers as IDs. Usb.org +therefore needs an agreement to regulate the use of USB IDs. The agreement +binds only parties who agreed to it, of course. Everybody else is free to use +any numbers for their IDs. + +So how can usb.org ensure that every manufacturer of USB devices enters into +an agreement with them? They do it via trademark licensing. Usb.org has +registered the trademark "USB", all associated logos and related terms. If +you want to put an USB logo on your product or claim that it is USB +compliant, you must license these trademarks from usb.org. And this is where +you enter into an agreement. See the "USB-IF Trademark License Agreement and +Usage Guidelines for the USB-IF Logo" at +http://www.usb.org/developers/logo_license/. + +Licensing the USB trademarks requires that you buy a USB Vendor-ID from +usb.org (one-time fee of ca. 2,000 USD), that you become a member of usb.org +(yearly fee of ca. 4,000 USD) and that you meet all the technical +specifications from the USB spec. + +This means that most hobbyists and small companies will never be able to +become USB compliant, just because membership is so expensive. And you can't +be compliant with a driver based on V-USB anyway, because the AVR's port pins +don't meet the electrical specifications for USB. So, in principle, all +hobbyists and small companies are free to choose any random numbers for their +IDs. They have nothing to lose... + +There is one exception worth noting, though: If you use a sub-component which +implements USB, the vendor of the sub-components may guarantee USB +compliance. This might apply to some or all of FTDI's solutions. + + +======================================================================= +WHY SHOULD YOU OBTAIN USB IDs EVEN IF YOU DON'T LICENSE USB TRADEMARKS? +======================================================================= + +You have learned in the previous section that you are free to choose any +numbers for your IDs anyway. So why not do exactly this? There is still the +technical issue. If you choose IDs which are already in use by somebody else, +operating systems will load the wrong drivers and your device won't work. +Even if you choose IDs which are not currently in use, they may be in use in +the next version of the operating system or even after an automatic update. + +So what you need is a pair of Vendor- and Product-IDs for which you have the +guarantee that no USB compliant product uses them. This implies that no +operating system will ever ship with drivers responsible for these IDs. + + +============================================== +HOW DOES OBJECTIVE DEVELOPMENT HANDLE USB IDs? +============================================== + +Objective Development gives away pairs of USB-IDs with their V-USB licenses. +In order to ensure that these IDs are unique, Objective Development has an +agreement with the company/person who has bought the USB Vendor-ID from +usb.org. This agreement ensures that a range of USB Product-IDs is reserved +for assignment by Objective Development and that the owner of the Vendor-ID +won't give it to anybody else. + +This means that you have to trust three parties to ensure uniqueness of +your IDs: + + - Objective Development, that they don't give the same PID to more than + one person. + - The owner of the Vendor-ID that they don't assign PIDs from the range + assigned to Objective Development to anybody else. + - Usb.org that they don't assign the same Vendor-ID a second time. + + +================================== +WHO IS THE OWNER OF THE VENDOR-ID? +================================== + +Objective Development has obtained ranges of USB Product-IDs under two +Vendor-IDs: Under Vendor-ID 5824 from Wouter van Ooijen (Van Ooijen +Technische Informatica, www.voti.nl) and under Vendor-ID 8352 from Jason +Kotzin (Clay Logic, www.claylogic.com). Both VID owners have received their +Vendor-ID directly from usb.org. + + +========================================================================= +CAN I USE USB-IDs FROM OBJECTIVE DEVELOPMENT WITH OTHER DRIVERS/HARDWARE? +========================================================================= + +The short answer is: Yes. All you get is a guarantee that the IDs are never +assigned to anybody else. What more do you need? + + +============================ +WHAT ABOUT SHARED ID PAIRS? +============================ + +Objective Development has reserved some PID/VID pairs for shared use. You +have no guarantee of uniqueness for them, except that no USB compliant device +uses them. In order to avoid technical problems, we must ensure that all +devices with the same pair of IDs use the same driver on kernel level. For +details, see the file USB-IDs-for-free.txt. + + +====================================================== +I HAVE HEARD THAT SUB-LICENSING OF USB-IDs IS ILLEGAL? +====================================================== + +A 16 bit integer number cannot be protected by copyright laws. It is not +sufficiently complex. And since none of the parties involved entered into the +USB-IF Trademark License Agreement, we are not bound by this agreement. So +there is no reason why it should be illegal to sub-license USB-IDs. + + +============================================= +WHO IS LIABLE IF THERE ARE INCOMPATIBILITIES? +============================================= + +Objective Development disclaims all liabilities which might arise from the +assignment of IDs. If you guarantee product features to your customers +without proper disclaimer, YOU are liable for that. diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/USB-IDs-for-free.txt b/hardware/digistump/avr/libraries/DigisparkJoystick/USB-IDs-for-free.txt new file mode 100644 index 0000000..2f4d59a --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/USB-IDs-for-free.txt @@ -0,0 +1,148 @@ +Version 2009-08-22 + +=========================== +FREE USB-IDs FOR SHARED USE +=========================== + +Objective Development has reserved a set of USB Product-IDs for use according +to the guidelines outlined below. For more information about the concept of +USB IDs please see the file USB-ID-FAQ.txt. Objective Development guarantees +that the IDs listed below are not used by any USB compliant devices. + + +==================== +MECHANISM OF SHARING +==================== + +From a technical point of view, two different devices can share the same USB +Vendor- and Product-ID if they require the same driver on operating system +level. We make use of this fact by assigning separate IDs for various device +classes. On application layer, devices must be distinguished by their textual +name or serial number. We offer separate sets of IDs for discrimination by +textual name and for serial number. + +Examples for shared use of USB IDs are included with V-USB in the "examples" +subdirectory. + + +====================================== +IDs FOR DISCRIMINATION BY TEXTUAL NAME +====================================== + +If you use one of the IDs listed below, your device and host-side software +must conform to these rules: + +(1) The USB device MUST provide a textual representation of the manufacturer +and product identification. The manufacturer identification MUST be available +at least in USB language 0x0409 (English/US). + +(2) The textual manufacturer identification MUST contain either an Internet +domain name (e.g. "mycompany.com") registered and owned by you, or an e-mail +address under your control (e.g. "myname@gmx.net"). You can embed the domain +name or e-mail address in any string you like, e.g. "Objective Development +http://www.obdev.at/vusb/". + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(4) You may choose any string for the textual product identification, as long +as this string is unique within the scope of your textual manufacturer +identification. + +(5) Application side device look-up MUST be based on the textual manufacturer +and product identification in addition to VID/PID matching. The driver +matching MUST be a comparison of the entire strings, NOT a sub-string match. + +(6) For devices which implement a particular USB device class (e.g. HID), the +operating system's default class driver MUST be used. If an operating system +driver for Vendor Class devices is needed, this driver must be libusb or +libusb-win32 (see http://libusb.org/ and +http://libusb-win32.sourceforge.net/). + +Table if IDs for discrimination by textual name: + +PID dec (hex) | VID dec (hex) | Description of use +==============+===============+============================================ +1500 (0x05dc) | 5824 (0x16c0) | For Vendor Class devices with libusb +--------------+---------------+-------------------------------------------- +1503 (0x05df) | 5824 (0x16c0) | For generic HID class devices (which are + | | NOT mice, keyboards or joysticks) +--------------+---------------+-------------------------------------------- +1505 (0x05e1) | 5824 (0x16c0) | For CDC-ACM class devices (modems) +--------------+---------------+-------------------------------------------- +1508 (0x05e4) | 5824 (0x16c0) | For MIDI class devices +--------------+---------------+-------------------------------------------- + +Note that Windows caches the textual product- and vendor-description for +mice, keyboards and joysticks. Name-bsed discrimination is therefore not +recommended for these device classes. + + +======================================= +IDs FOR DISCRIMINATION BY SERIAL NUMBER +======================================= + +If you use one of the IDs listed below, your device and host-side software +must conform to these rules: + +(1) The USB device MUST provide a textual representation of the serial +number. The serial number string MUST be available at least in USB language +0x0409 (English/US). + +(2) The serial number MUST start with either an Internet domain name (e.g. +"mycompany.com") registered and owned by you, or an e-mail address under your +control (e.g. "myname@gmx.net"), both terminated with a colon (":") character. +You MAY append any string you like for further discrimination of your devices. + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(5) Application side device look-up MUST be based on the serial number string +in addition to VID/PID matching. The matching must start at the first +character of the serial number string and include the colon character +terminating your domain or e-mail address. It MAY stop anywhere after that. + +(6) For devices which implement a particular USB device class (e.g. HID), the +operating system's default class driver MUST be used. If an operating system +driver for Vendor Class devices is needed, this driver must be libusb or +libusb-win32 (see http://libusb.org/ and +http://libusb-win32.sourceforge.net/). + +Table if IDs for discrimination by serial number string: + +PID dec (hex) | VID dec (hex) | Description of use +===============+===============+=========================================== +10200 (0x27d8) | 5824 (0x16c0) | For Vendor Class devices with libusb +---------------+---------------+------------------------------------------- +10201 (0x27d9) | 5824 (0x16c0) | For generic HID class devices (which are + | | NOT mice, keyboards or joysticks) +---------------+---------------+------------------------------------------- +10202 (0x27da) | 5824 (0x16c0) | For USB Mice +---------------+---------------+------------------------------------------- +10203 (0x27db) | 5824 (0x16c0) | For USB Keyboards +---------------+---------------+------------------------------------------- +10204 (0x27db) | 5824 (0x16c0) | For USB Joysticks +---------------+---------------+------------------------------------------- +10205 (0x27dc) | 5824 (0x16c0) | For CDC-ACM class devices (modems) +---------------+---------------+------------------------------------------- +10206 (0x27dd) | 5824 (0x16c0) | For MIDI class devices +---------------+---------------+------------------------------------------- + + +================= +ORIGIN OF USB-IDs +================= + +OBJECTIVE DEVELOPMENT Software GmbH has obtained all VID/PID pairs listed +here from Wouter van Ooijen (see www.voti.nl) for exclusive disposition. +Wouter van Ooijen has obtained the VID from the USB Implementers Forum, Inc. +(see www.usb.org). The VID is registered for the company name "Van Ooijen +Technische Informatica". + + +========== +DISCLAIMER +========== + +OBJECTIVE DEVELOPMENT Software GmbH disclaims all liability for any +problems which are caused by the shared use of these VID/PID pairs. diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/USBID-License.txt b/hardware/digistump/avr/libraries/DigisparkJoystick/USBID-License.txt new file mode 100644 index 0000000..c40be92 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/USBID-License.txt @@ -0,0 +1,154 @@ +Royalty-Free Non-Exclusive Use of USB Product-IDs +================================================= + +Version 2009-04-13 + +Strictly speaking, this is not a license. You can't give a license to use +a simple number (such as e.g. 1500) for any purpose. This is a set of rules +which should make it possible to build USB devices without the requirement +for individual USB IDs. If you break one of the rules, you will run into +technical problems sooner or later, but you don't risk legal trouble. + + +OBJECTIVE DEVELOPMENT Software GmbH hereby grants you the non-exclusive +right to use four USB.org vendor-ID (VID) / product-ID (PID) pairs with +products based on Objective Development's firmware-only USB driver for +Atmel AVR microcontrollers: + + * VID = 5824 (=0x16c0) / PID = 1500 (=0x5dc) for devices implementing no + USB device class (vendor-class devices with USB class = 0xff). Devices + using this pair will be referred to as "VENDOR CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1503 (=0x5df) for HID class devices + (excluding mice and keyboards). Devices using this pair will be referred + to as "HID CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1505 (=0x5e1) for CDC class modem devices + Devices using this pair will be referred to as "CDC-ACM CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1508 (=0x5e4) for MIDI class devices + Devices using this pair will be referred to as "MIDI CLASS" devices. + +Since the granted right is non-exclusive, the same VID/PID pairs may be +used by many companies and individuals for different products. To avoid +conflicts, your device and host driver software MUST adhere to the rules +outlined below. + +OBJECTIVE DEVELOPMENT Software GmbH has obtained these VID/PID pairs from +Wouter van Ooijen (see www.voti.nl) for exclusive disposition. Wouter van +Ooijen has obtained the VID from the USB Implementers Forum, Inc. +(see www.usb.org). The VID is registered for the company name +"Van Ooijen Technische Informatica". + + +RULES AND RESTRICTIONS +====================== + +(1) The USB device MUST provide a textual representation of the +manufacturer and product identification. The manufacturer identification +MUST be available at least in USB language 0x0409 (English/US). + +(2) The textual manufacturer identification MUST contain either an Internet +domain name (e.g. "mycompany.com") registered and owned by you, or an +e-mail address under your control (e.g. "myname@gmx.net"). You can embed +the domain name or e-mail address in any string you like, e.g. "Objective +Development http://www.obdev.at/vusb/". + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(4) You may choose any string for the textual product identification, as +long as this string is unique within the scope of your textual manufacturer +identification. + +(5) Matching of device-specific drivers MUST be based on the textual +manufacturer and product identification in addition to the usual VID/PID +matching. This means that operating system features which are based on +VID/PID matching only (e.g. Windows kernel level drivers, automatic actions +when the device is plugged in etc) MUST NOT be used. The driver matching +MUST be a comparison of the entire strings, NOT a sub-string match. For +CDC-ACM CLASS and MIDI CLASS devices, a generic class driver should be used +and the matching is based on the USB device class. + +(6) The extent to which VID/PID matching is allowed for non device-specific +drivers or features depends on the operating system and particular VID/PID +pair used: + + * Mac OS X, Linux, FreeBSD and other Unixes: No VID/PID matching is + required and hence no VID/PID-only matching is allowed at all. + + * Windows: The operating system performs VID/PID matching for the kernel + level driver. You are REQUIRED to use libusb-win32 (see + http://libusb-win32.sourceforge.net/) as the kernel level driver for + VENDOR CLASS devices. HID CLASS devices all use the generic HID class + driver shipped with Windows, except mice and keyboards. You therefore + MUST NOT use any of the shared VID/PID pairs for mice or keyboards. + CDC-ACM CLASS devices require a ".inf" file which matches on the VID/PID + pair. This ".inf" file MUST load the "usbser" driver to configure the + device as modem (COM-port). + +(7) OBJECTIVE DEVELOPMENT Software GmbH disclaims all liability for any +problems which are caused by the shared use of these VID/PID pairs. You +have been warned that the sharing of VID/PID pairs may cause problems. If +you want to avoid them, get your own VID/PID pair for exclusive use. + + +HOW TO IMPLEMENT THESE RULES +============================ + +The following rules are for VENDOR CLASS and HID CLASS devices. CDC-ACM +CLASS and MIDI CLASS devices use the operating system's class driver and +don't need a custom driver. + +The host driver MUST iterate over all devices with the given VID/PID +numbers in their device descriptors and query the string representation for +the manufacturer name in USB language 0x0409 (English/US). It MUST compare +the ENTIRE string with your textual manufacturer identification chosen in +(2) above. A substring search for your domain or e-mail address is NOT +acceptable. The driver MUST NOT touch the device (other than querying the +descriptors) unless the strings match. + +For all USB devices with matching VID/PID and textual manufacturer +identification, the host driver must query the textual product +identification and string-compare it with the name of the product it can +control. It may only initialize the device if the product matches exactly. + +Objective Development provides examples for these matching rules with the +"PowerSwitch" project (using libusb) and with the "Automator" project +(using Windows calls on Windows and libusb on Unix). + + +Technical Notes: +================ + +Sharing the same VID/PID pair among devices is possible as long as ALL +drivers which match the VID/PID also perform matching on the textual +identification strings. This is easy on all operating systems except +Windows, since Windows establishes a static connection between the VID/PID +pair and a kernel level driver. All devices with the same VID/PID pair must +therefore use THE SAME kernel level driver. + +We therefore demand that you use libusb-win32 for VENDOR CLASS devices. +This is a generic kernel level driver which allows all types of USB access +for user space applications. This is only a partial solution of the +problem, though, because different device drivers may come with different +versions of libusb-win32 and they may not work with the libusb version of +the respective other driver. You are therefore encouraged to test your +driver against a broad range of libusb-win32 versions. Do not use new +features in new versions, or check for their existence before you use them. +When a new libusb-win32 becomes available, make sure that your driver is +compatible with it. + +For HID CLASS devices it is necessary that all those devices bind to the +same kernel driver: Microsoft's generic USB HID driver. This is true for +all HID devices except those with a specialized driver. Currently, the only +HIDs with specialized drivers are mice and keyboards. You therefore MUST +NOT use a shared VID/PID with mouse and keyboard devices. + +Sharing the same VID/PID among different products is unusual and probably +violates the USB specification. If you do it, you do it at your own risk. + +To avoid possible incompatibilities, we highly recommend that you get your +own VID/PID pair if you intend to sell your product. Objective +Development's commercial licenses for V-USB include a PID for +unrestricted exclusive use. diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/asmcommon.inc b/hardware/digistump/avr/libraries/DigisparkJoystick/asmcommon.inc new file mode 100644 index 0000000..07d692b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/asmcommon.inc @@ -0,0 +1,188 @@ +/* Name: asmcommon.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2007-11-05 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id$ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file contains assembler code which is shared among the USB driver +implementations for different CPU cocks. Since the code must be inserted +in the middle of the module, it's split out into this file and #included. + +Jump destinations called from outside: + sofError: Called when no start sequence was found. + se0: Called when a package has been successfully received. + overflow: Called when receive buffer overflows. + doReturn: Called after sending data. + +Outside jump destinations used by this module: + waitForJ: Called to receive an already arriving packet. + sendAckAndReti: + sendNakAndReti: + sendCntAndReti: + usbSendAndReti: + +The following macros must be defined before this file is included: + .macro POP_STANDARD + .endm + .macro POP_RETI + .endm +*/ + +#define token x1 + +overflow: + ldi x2, 1< 0 + +#warning "Never compile production devices with debugging enabled" + +static void uartPutc(char c) +{ + while(!(ODDBG_USR & (1 << ODDBG_UDRE))); /* wait for data register empty */ + ODDBG_UDR = c; +} + +static uchar hexAscii(uchar h) +{ + h &= 0xf; + if(h >= 10) + h += 'a' - (uchar)10 - '0'; + h += '0'; + return h; +} + +static void printHex(uchar c) +{ + uartPutc(hexAscii(c >> 4)); + uartPutc(hexAscii(c)); +} + +void odDebug(uchar prefix, uchar *data, uchar len) +{ + printHex(prefix); + uartPutc(':'); + while(len--){ + uartPutc(' '); + printHex(*data++); + } + uartPutc('\r'); + uartPutc('\n'); +} + +#endif diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/oddebug.h b/hardware/digistump/avr/libraries/DigisparkJoystick/oddebug.h new file mode 100644 index 0000000..d61309d --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/oddebug.h @@ -0,0 +1,123 @@ +/* Name: oddebug.h + * Project: AVR library + * Author: Christian Starkjohann + * Creation Date: 2005-01-16 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: oddebug.h 692 2008-11-07 15:07:40Z cs $ + */ + +#ifndef __oddebug_h_included__ +#define __oddebug_h_included__ + +/* +General Description: +This module implements a function for debug logs on the serial line of the +AVR microcontroller. Debugging can be configured with the define +'DEBUG_LEVEL'. If this macro is not defined or defined to 0, all debugging +calls are no-ops. If it is 1, DBG1 logs will appear, but not DBG2. If it is +2, DBG1 and DBG2 logs will be printed. + +A debug log consists of a label ('prefix') to indicate which debug log created +the output and a memory block to dump in hex ('data' and 'len'). +*/ + + +#ifndef F_CPU +# define F_CPU 12000000 /* 12 MHz */ +#endif + +/* make sure we have the UART defines: */ +#include "usbportability.h" + +#ifndef uchar +# define uchar unsigned char +#endif + +#if DEBUG_LEVEL > 0 && !(defined TXEN || defined TXEN0) /* no UART in device */ +# warning "Debugging disabled because device has no UART" +# undef DEBUG_LEVEL +#endif + +#ifndef DEBUG_LEVEL +# define DEBUG_LEVEL 0 +#endif + +/* ------------------------------------------------------------------------- */ + +#if DEBUG_LEVEL > 0 +# define DBG1(prefix, data, len) odDebug(prefix, data, len) +#else +# define DBG1(prefix, data, len) +#endif + +#if DEBUG_LEVEL > 1 +# define DBG2(prefix, data, len) odDebug(prefix, data, len) +#else +# define DBG2(prefix, data, len) +#endif + +/* ------------------------------------------------------------------------- */ + +#if DEBUG_LEVEL > 0 +extern void odDebug(uchar prefix, uchar *data, uchar len); + +/* Try to find our control registers; ATMEL likes to rename these */ + +#if defined UBRR +# define ODDBG_UBRR UBRR +#elif defined UBRRL +# define ODDBG_UBRR UBRRL +#elif defined UBRR0 +# define ODDBG_UBRR UBRR0 +#elif defined UBRR0L +# define ODDBG_UBRR UBRR0L +#endif + +#if defined UCR +# define ODDBG_UCR UCR +#elif defined UCSRB +# define ODDBG_UCR UCSRB +#elif defined UCSR0B +# define ODDBG_UCR UCSR0B +#endif + +#if defined TXEN +# define ODDBG_TXEN TXEN +#else +# define ODDBG_TXEN TXEN0 +#endif + +#if defined USR +# define ODDBG_USR USR +#elif defined UCSRA +# define ODDBG_USR UCSRA +#elif defined UCSR0A +# define ODDBG_USR UCSR0A +#endif + +#if defined UDRE +# define ODDBG_UDRE UDRE +#else +# define ODDBG_UDRE UDRE0 +#endif + +#if defined UDR +# define ODDBG_UDR UDR +#elif defined UDR0 +# define ODDBG_UDR UDR0 +#endif + +static inline void odDebugInit(void) +{ + ODDBG_UCR |= (1< + +#ifndef uchar +#define uchar unsigned char +#endif + +/* ------------------------------------------------------------------------- */ +/* ------------------------ Oscillator Calibration ------------------------- */ +/* ------------------------------------------------------------------------- */ + +/* Calibrate the RC oscillator. Our timing reference is the Start Of Frame + * signal (a single SE0 bit) repeating every millisecond immediately after + * a USB RESET. We first do a binary search for the OSCCAL value and then + * optimize this value with a neighboorhod search. + */ +void calibrateOscillator(void) +{ +uchar step = 128; +uchar trialValue = 0, optimumValue; +int x, optimumDev, targetValue = (unsigned)(1499 * (double)F_CPU / 10.5e6 + 0.5); + + /* do a binary search: */ + do{ + OSCCAL = trialValue + step; + x = usbMeasureFrameLength(); /* proportional to current real frequency */ + if(x < targetValue) /* frequency still too low */ + trialValue += step; + step >>= 1; + }while(step > 0); + /* We have a precision of +/- 1 for optimum OSCCAL here */ + /* now do a neighborhood search for optimum value */ + optimumValue = trialValue; + optimumDev = x; /* this is certainly far away from optimum */ + for(OSCCAL = trialValue - 1; OSCCAL <= trialValue + 1; OSCCAL++){ + x = usbMeasureFrameLength() - targetValue; + if(x < 0) + x = -x; + if(x < optimumDev){ + optimumDev = x; + optimumValue = OSCCAL; + } + } + OSCCAL = optimumValue; +} +/* +Note: This calibration algorithm may try OSCCAL values of up to 192 even if +the optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +You may replace this search algorithm with any other algorithm you like if +you have additional constraints such as a maximum CPU clock. +For version 5.x RC oscillators (those with a split range of 2x128 steps, e.g. +ATTiny25, ATTiny45, ATTiny85), it may be useful to search for the optimum in +both regions. +*/ diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/osccal.c.lst b/hardware/digistump/avr/libraries/DigisparkJoystick/osccal.c.lst new file mode 100644 index 0000000..336a049 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/osccal.c.lst @@ -0,0 +1,106 @@ +GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 1 + + + 1 .file "osccal.c" + 2 __SREG__ = 0x3f + 3 __SP_H__ = 0x3e + 4 __SP_L__ = 0x3d + 5 __CCP__ = 0x34 + 6 __tmp_reg__ = 0 + 7 __zero_reg__ = 1 + 8 .text + 9 .global calibrateOscillator + 10 .type calibrateOscillator, @function + 11 calibrateOscillator: + 12 0000 FF92 push r15 + 13 0002 0F93 push r16 + 14 0004 1F93 push r17 + 15 0006 CF93 push r28 + 16 0008 DF93 push r29 + 17 /* prologue: function */ + 18 /* frame size = 0 */ + 19 000a 80E8 ldi r24,lo8(-128) + 20 000c F82E mov r15,r24 + 21 000e 00E0 ldi r16,lo8(0) + 22 0010 C0E0 ldi r28,lo8(0) + 23 0012 D0E0 ldi r29,hi8(0) + 24 .L4: + 25 0014 102F mov r17,r16 + 26 0016 1F0D add r17,r15 + 27 0018 11BF out 81-32,r17 + 28 001a 00D0 rcall usbMeasureFrameLength + 29 001c 29E0 ldi r18,hi8(2356) + 30 001e 8433 cpi r24,lo8(2356) + 31 0020 9207 cpc r25,r18 + 32 0022 04F0 brlt .L2 + 33 0024 102F mov r17,r16 + 34 .L2: + 35 0026 F694 lsr r15 + 36 0028 2196 adiw r28,1 + 37 002a C830 cpi r28,8 + 38 002c D105 cpc r29,__zero_reg__ + 39 002e 01F0 breq .L3 + 40 0030 012F mov r16,r17 + 41 0032 00C0 rjmp .L4 + 42 .L3: + 43 0034 1150 subi r17,lo8(-(-1)) + 44 0036 11BF out 81-32,r17 + 45 0038 1F5F subi r17,lo8(-(1)) + 46 003a 012F mov r16,r17 + 47 003c EC01 movw r28,r24 + 48 003e 00C0 rjmp .L5 + 49 .L8: + 50 0040 00D0 rcall usbMeasureFrameLength + 51 0042 8453 subi r24,lo8(-(-2356)) + 52 0044 9940 sbci r25,hi8(-(-2356)) + 53 0046 97FF sbrs r25,7 + 54 0048 00C0 rjmp .L6 + 55 004a 9095 com r25 + 56 004c 8195 neg r24 + 57 004e 9F4F sbci r25,lo8(-1) + GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 2 + + + 58 .L6: + 59 0050 8C17 cp r24,r28 + 60 0052 9D07 cpc r25,r29 + 61 0054 04F4 brge .L7 + 62 0056 01B7 in r16,81-32 + 63 0058 EC01 movw r28,r24 + 64 .L7: + 65 005a 81B7 in r24,81-32 + 66 005c 8F5F subi r24,lo8(-(1)) + 67 005e 81BF out 81-32,r24 + 68 .L5: + 69 0060 21B7 in r18,81-32 + 70 0062 30E0 ldi r19,lo8(0) + 71 0064 812F mov r24,r17 + 72 0066 90E0 ldi r25,lo8(0) + 73 0068 0196 adiw r24,1 + 74 006a 8217 cp r24,r18 + 75 006c 9307 cpc r25,r19 + 76 006e 04F4 brge .L8 + 77 0070 01BF out 81-32,r16 + 78 /* epilogue start */ + 79 0072 DF91 pop r29 + 80 0074 CF91 pop r28 + 81 0076 1F91 pop r17 + 82 0078 0F91 pop r16 + 83 007a FF90 pop r15 + 84 007c 0895 ret + 85 .size calibrateOscillator, .-calibrateOscillator + GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 3 + + +DEFINED SYMBOLS + *ABS*:00000000 osccal.c +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:2 *ABS*:0000003f __SREG__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:3 *ABS*:0000003e __SP_H__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:4 *ABS*:0000003d __SP_L__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:5 *ABS*:00000034 __CCP__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:6 *ABS*:00000000 __tmp_reg__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:7 *ABS*:00000001 __zero_reg__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:11 .text:00000000 calibrateOscillator + +UNDEFINED SYMBOLS +usbMeasureFrameLength diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/osccal.h b/hardware/digistump/avr/libraries/DigisparkJoystick/osccal.h new file mode 100644 index 0000000..710ce05 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/osccal.h @@ -0,0 +1,65 @@ +/* Name: osccal.h + * Author: Christian Starkjohann + * Creation Date: 2008-04-10 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osccal.h 762 2009-08-12 17:10:30Z cs $ + */ + +/* +General Description: +This module contains a function which calibrates the AVR's internal RC +oscillator so that the CPU runs at F_CPU (F_CPU is a macro which must be +defined when the module is compiled, best passed in the compiler command +line). The time reference is the USB frame clock of 1 kHz available +immediately after a USB RESET condition. Timing is done by counting CPU +cycles, so all interrupts must be disabled while the calibration runs. For +low level timing measurements, usbMeasureFrameLength() is called. This +function must be enabled in usbconfig.h by defining +USB_CFG_HAVE_MEASURE_FRAME_LENGTH to 1. It is recommended to call +calibrateOscillator() from the reset hook in usbconfig.h: +*/ + +#ifndef __ASSEMBLER__ +#include // for sei() +extern void calibrateOscillator(void); +#endif +#define USB_RESET_HOOK(resetStarts) if(!resetStarts){cli(); calibrateOscillator(); sei();} + +/* +This routine is an alternative to the continuous synchronization described +in osctune.h. + +Algorithm used: +calibrateOscillator() first does a binary search in the OSCCAL register for +the best matching oscillator frequency. Then it does a next neighbor search +to find the value with the lowest clock rate deviation. It is guaranteed to +find the best match among neighboring values, but for version 5 oscillators +(which have a discontinuous relationship between OSCCAL and frequency) a +better match might be available in another OSCCAL region. + +Limitations: +This calibration algorithm may try OSCCAL values of up to 192 even if the +optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +Precision depends on the OSCCAL vs. frequency dependency of the oscillator. +Typical precision for an ATMega168 (derived from the OSCCAL vs. F_RC diagram +in the data sheet) should be in the range of 0.4%. Only the 12.8 MHz and +16.5 MHz versions of V-USB (with built-in receiver PLL) can tolerate this +deviation! All other frequency modules require at least 0.2% precision. +*/ + +#ifndef __OSCCAL_H_INCLUDED__ +#define __OSCCAL_H_INCLUDED__ + +//void calibrateOscillator(void); +/* This function calibrates the RC oscillator so that the CPU runs at F_CPU. + * It MUST be called immediately after the end of a USB RESET condition! + * Disable all interrupts during the call! + * It is recommended that you store the resulting value in EEPROM so that a + * good guess value is available after the next reset. + */ + + +#endif /* __OSCCAL_H_INCLUDED__ */ diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/osccal.o b/hardware/digistump/avr/libraries/DigisparkJoystick/osccal.o new file mode 100644 index 0000000..08e2187 Binary files /dev/null and b/hardware/digistump/avr/libraries/DigisparkJoystick/osccal.o differ diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/osctune.h b/hardware/digistump/avr/libraries/DigisparkJoystick/osctune.h new file mode 100644 index 0000000..c751648 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/osctune.h @@ -0,0 +1,88 @@ +/* Name: osctune.h + * Author: Christian Starkjohann + * Creation Date: 2008-10-18 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osctune.h 692 2008-11-07 15:07:40Z cs $ + */ + +/* +General Description: +This file is declared as C-header file although it is mostly documentation +how the RC oscillator can be kept in sync to the USB frame rate. The code +shown here must be added to usbconfig.h or this header file is included from +there. This code works only if D- is wired to the interrupt, not D+!!! + +This is an alternative to the osccal routine in osccal.c. It has the advantage +that the synchronization is done continuously and that it has more compact +code size. The disadvantages are slow synchronization (it may take a while +until the driver works), that messages immediately after the SOF pulse may be +lost (and need to be retried by the host) and that the interrupt is on D- +contrary to most examples. + +You may want to store a good calibration value in EEPROM for the next startup. +You know that the calibration value is good when the first USB message is +received. Do not store the value on every received message because the EEPROM +has a limited endurance. + +Notes: +(*) You must declare the global character variable "lastTimer0Value" in your +main code. + +(*) Timer 0 must be free running (not written by your code) and the prescaling +must be consistent with the TIMER0_PRESCALING define. + +(*) Good values for Timer 0 prescaling depend on how precise the clock must +be tuned and how far away from the default clock rate the target clock is. +For precise tuning, choose a low prescaler factor, for a broad range of tuning +choose a high one. A prescaler factor of 64 is good for the entire OSCCAL +range and allows a precision of better than +/-1%. A prescaler factor of 8 +allows tuning to slightly more than +/-6% of the default frequency and is +more precise than one step of OSCCAL. It is therefore not suitable to tune an +8 MHz oscillator to 12.5 MHz. + +Thanks to Henrik Haftmann for the idea to this routine! +*/ + +#define TIMER0_PRESCALING 64 /* must match the configuration for TIMER0 in main */ +#define TOLERATED_DEVIATION_PPT 5 /* max clock deviation before we tune in 1/10 % */ +/* derived constants: */ +#define EXPECTED_TIMER0_INCREMENT ((F_CPU / (1000 * TIMER0_PRESCALING)) & 0xff) +#define TOLERATED_DEVIATION (TOLERATED_DEVIATION_PPT * F_CPU / (1000000 * TIMER0_PRESCALING)) + +#ifdef __ASSEMBLER__ +macro tuneOsccal + push YH ;[0] + in YL, TCNT0 ;[2] + lds YH, lastTimer0Value ;[3] + sts lastTimer0Value, YL ;[5] + sub YL, YH ;[7] time passed since last frame + subi YL, EXPECTED_TIMER0_INCREMENT ;[8] +#if OSCCAL > 0x3f /* outside I/O addressable range */ + lds YH, OSCCAL ;[6] +#else + in YH, OSCCAL ;[6] assembler modle uses __SFR_OFFSET == 0 +#endif + cpi YL, TOLERATED_DEVIATION + 1 ;[10] + brmi notTooHigh ;[11] + subi YH, 1 ;[12] clock rate was too high +; brcs tuningOverflow ; optionally check for overflow + rjmp osctuneDone ;[13] +notTooHigh: + cpi YL, -TOLERATED_DEVIATION ;[13] + brpl osctuneDone ;[14] not too low + inc YH ;[15] clock rate was too low +; breq tuningOverflow ; optionally check for overflow +osctuneDone: +#if OSCCAL > 0x3f /* outside I/O addressable range */ + sts OSCCAL, YH ;[12-13] store tuned value +#else + out OSCCAL, YH ;[12-13] store tuned value +#endif +tuningOverflow: + pop YH ;[17] + endm ;[19] max number of cycles +#endif + +#define USB_SOF_HOOK tuneOsccal diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/usbconfig-prototype.h b/hardware/digistump/avr/libraries/DigisparkJoystick/usbconfig-prototype.h new file mode 100644 index 0000000..a0fd1bf --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/usbconfig-prototype.h @@ -0,0 +1,369 @@ +/* Name: usbconfig.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2005-04-01 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbconfig-prototype.h 767 2009-08-22 11:39:22Z cs $ + */ + +#ifndef __usbconfig_h_included__ +#define __usbconfig_h_included__ + +/* +General Description: +This file is an example configuration (with inline documentation) for the USB +driver. It configures V-USB for USB D+ connected to Port D bit 2 (which is +also hardware interrupt 0 on many devices) and USB D- to Port D bit 4. You may +wire the lines to any other port, as long as D+ is also wired to INT0 (or any +other hardware interrupt, as long as it is the highest level interrupt, see +section at the end of this file). ++ To create your own usbconfig.h file, copy this file to your project's ++ firmware source directory) and rename it to "usbconfig.h". ++ Then edit it accordingly. +*/ + +/* ---------------------------- Hardware Config ---------------------------- */ + +#define USB_CFG_IOPORTNAME D +/* This is the port where the USB bus is connected. When you configure it to + * "B", the registers PORTB, PINB and DDRB will be used. + */ +#define USB_CFG_DMINUS_BIT 4 +/* This is the bit number in USB_CFG_IOPORT where the USB D- line is connected. + * This may be any bit in the port. + */ +#define USB_CFG_DPLUS_BIT 2 +/* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected. + * This may be any bit in the port. Please note that D+ must also be connected + * to interrupt pin INT0! [You can also use other interrupts, see section + * "Optional MCU Description" below, or you can connect D- to the interrupt, as + * it is required if you use the USB_COUNT_SOF feature. If you use D- for the + * interrupt, the USB interrupt will also be triggered at Start-Of-Frame + * markers every millisecond.] + */ +#define USB_CFG_CLOCK_KHZ (F_CPU/1000) +/* Clock rate of the AVR in kHz. Legal values are 12000, 12800, 15000, 16000, + * 16500 and 20000. The 12.8 MHz and 16.5 MHz versions of the code require no + * crystal, they tolerate +/- 1% deviation from the nominal frequency. All + * other rates require a precision of 2000 ppm and thus a crystal! + * Default if not specified: 12 MHz + */ +#define USB_CFG_CHECK_CRC 0 +/* Define this to 1 if you want that the driver checks integrity of incoming + * data packets (CRC checks). CRC checks cost quite a bit of code size and are + * currently only available for 18 MHz crystal clock. You must choose + * USB_CFG_CLOCK_KHZ = 18000 if you enable this option. + */ + +/* ----------------------- Optional Hardware Config ------------------------ */ + +/* #define USB_CFG_PULLUP_IOPORTNAME D */ +/* If you connect the 1.5k pullup resistor from D- to a port pin instead of + * V+, you can connect and disconnect the device from firmware by calling + * the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h). + * This constant defines the port on which the pullup resistor is connected. + */ +/* #define USB_CFG_PULLUP_BIT 4 */ +/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined + * above) where the 1.5k pullup resistor is connected. See description + * above for details. + */ + +/* --------------------------- Functional Range ---------------------------- */ + +#define USB_CFG_HAVE_INTRIN_ENDPOINT 0 +/* Define this to 1 if you want to compile a version with two endpoints: The + * default control endpoint 0 and an interrupt-in endpoint (any other endpoint + * number). + */ +#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0 +/* Define this to 1 if you want to compile a version with three endpoints: The + * default control endpoint 0, an interrupt-in endpoint 3 (or the number + * configured below) and a catch-all default interrupt-in endpoint as above. + * You must also define USB_CFG_HAVE_INTRIN_ENDPOINT to 1 for this feature. + */ +#define USB_CFG_EP3_NUMBER 3 +/* If the so-called endpoint 3 is used, it can now be configured to any other + * endpoint number (except 0) with this macro. Default if undefined is 3. + */ +/* #define USB_INITIAL_DATATOKEN USBPID_DATA1 */ +/* The above macro defines the startup condition for data toggling on the + * interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA1. + * Since the token is toggled BEFORE sending any data, the first packet is + * sent with the oposite value of this configuration! + */ +#define USB_CFG_IMPLEMENT_HALT 0 +/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature + * for endpoint 1 (interrupt endpoint). Although you may not need this feature, + * it is required by the standard. We have made it a config option because it + * bloats the code considerably. + */ +#define USB_CFG_SUPPRESS_INTR_CODE 0 +/* Define this to 1 if you want to declare interrupt-in endpoints, but don't + * want to send any data over them. If this macro is defined to 1, functions + * usbSetInterrupt() and usbSetInterrupt3() are omitted. This is useful if + * you need the interrupt-in endpoints in order to comply to an interface + * (e.g. HID), but never want to send any data. This option saves a couple + * of bytes in flash memory and the transmit buffers in RAM. + */ +#define USB_CFG_INTR_POLL_INTERVAL 10 +/* If you compile a version with endpoint 1 (interrupt-in), this is the poll + * interval. The value is in milliseconds and must not be less than 10 ms for + * low speed devices. + */ +#define USB_CFG_IS_SELF_POWERED 0 +/* Define this to 1 if the device has its own power supply. Set it to 0 if the + * device is powered from the USB bus. + */ +#define USB_CFG_MAX_BUS_POWER 100 +/* Set this variable to the maximum USB bus power consumption of your device. + * The value is in milliamperes. [It will be divided by two since USB + * communicates power requirements in units of 2 mA.] + */ +#define USB_CFG_IMPLEMENT_FN_WRITE 0 +/* Set this to 1 if you want usbFunctionWrite() to be called for control-out + * transfers. Set it to 0 if you don't need it and want to save a couple of + * bytes. + */ +#define USB_CFG_IMPLEMENT_FN_READ 0 +/* Set this to 1 if you need to send control replies which are generated + * "on the fly" when usbFunctionRead() is called. If you only want to send + * data from a static buffer, set it to 0 and return the data from + * usbFunctionSetup(). This saves a couple of bytes. + */ +#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0 +/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints. + * You must implement the function usbFunctionWriteOut() which receives all + * interrupt/bulk data sent to any endpoint other than 0. The endpoint number + * can be found in 'usbRxToken'. + */ +#define USB_CFG_HAVE_FLOWCONTROL 0 +/* Define this to 1 if you want flowcontrol over USB data. See the definition + * of the macros usbDisableAllRequests() and usbEnableAllRequests() in + * usbdrv.h. + */ +#define USB_CFG_LONG_TRANSFERS 0 +/* Define this to 1 if you want to send/receive blocks of more than 254 bytes + * in a single control-in or control-out transfer. Note that the capability + * for long transfers increases the driver size. + */ +/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */ +/* This macro is a hook if you want to do unconventional things. If it is + * defined, it's inserted at the beginning of received message processing. + * If you eat the received message and don't want default processing to + * proceed, do a return after doing your things. One possible application + * (besides debugging) is to flash a status LED on each packet. + */ +/* #define USB_RESET_HOOK(resetStarts) if(!resetStarts){hadUsbReset();} */ +/* This macro is a hook if you need to know when an USB RESET occurs. It has + * one parameter which distinguishes between the start of RESET state and its + * end. + */ +/* #define USB_SET_ADDRESS_HOOK() hadAddressAssigned(); */ +/* This macro (if defined) is executed when a USB SET_ADDRESS request was + * received. + */ +#define USB_COUNT_SOF 0 +/* define this macro to 1 if you need the global variable "usbSofCount" which + * counts SOF packets. This feature requires that the hardware interrupt is + * connected to D- instead of D+. + */ +/* #ifdef __ASSEMBLER__ + * macro myAssemblerMacro + * in YL, TCNT0 + * sts timer0Snapshot, YL + * endm + * #endif + * #define USB_SOF_HOOK myAssemblerMacro + * This macro (if defined) is executed in the assembler module when a + * Start Of Frame condition is detected. It is recommended to define it to + * the name of an assembler macro which is defined here as well so that more + * than one assembler instruction can be used. The macro may use the register + * YL and modify SREG. If it lasts longer than a couple of cycles, USB messages + * immediately after an SOF pulse may be lost and must be retried by the host. + * What can you do with this hook? Since the SOF signal occurs exactly every + * 1 ms (unless the host is in sleep mode), you can use it to tune OSCCAL in + * designs running on the internal RC oscillator. + * Please note that Start Of Frame detection works only if D- is wired to the + * interrupt, not D+. THIS IS DIFFERENT THAN MOST EXAMPLES! + */ +#define USB_CFG_CHECK_DATA_TOGGLING 0 +/* define this macro to 1 if you want to filter out duplicate data packets + * sent by the host. Duplicates occur only as a consequence of communication + * errors, when the host does not receive an ACK. Please note that you need to + * implement the filtering yourself in usbFunctionWriteOut() and + * usbFunctionWrite(). Use the global usbCurrentDataToken and a static variable + * for each control- and out-endpoint to check for duplicate packets. + */ +#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 0 +/* define this macro to 1 if you want the function usbMeasureFrameLength() + * compiled in. This function can be used to calibrate the AVR's RC oscillator. + */ +#define USB_USE_FAST_CRC 0 +/* The assembler module has two implementations for the CRC algorithm. One is + * faster, the other is smaller. This CRC routine is only used for transmitted + * messages where timing is not critical. The faster routine needs 31 cycles + * per byte while the smaller one needs 61 to 69 cycles. The faster routine + * may be worth the 32 bytes bigger code size if you transmit lots of data and + * run the AVR close to its limit. + */ + +/* -------------------------- Device Description --------------------------- */ + +#define USB_CFG_VENDOR_ID 0xc0, 0x16 /* = 0x16c0 = 5824 = voti.nl */ +/* USB vendor ID for the device, low byte first. If you have registered your + * own Vendor ID, define it here. Otherwise you may use one of obdev's free + * shared VID/PID pairs. Be sure to read USB-IDs-for-free.txt for rules! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_ID 0xdc, 0x05 /* = 0x05dc = 1500 */ +/* This is the ID of the product, low byte first. It is interpreted in the + * scope of the vendor ID. If you have registered your own VID with usb.org + * or if you have licensed a PID from somebody else, define it here. Otherwise + * you may use one of obdev's free shared VID/PID pairs. See the file + * USB-IDs-for-free.txt for details! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_VERSION 0x00, 0x01 +/* Version number of the device: Minor number first, then major number. + */ +#define USB_CFG_VENDOR_NAME 'o', 'b', 'd', 'e', 'v', '.', 'a', 't' +#define USB_CFG_VENDOR_NAME_LEN 8 +/* These two values define the vendor name returned by the USB device. The name + * must be given as a list of characters under single quotes. The characters + * are interpreted as Unicode (UTF-16) entities. + * If you don't want a vendor name string, undefine these macros. + * ALWAYS define a vendor name containing your Internet domain name if you use + * obdev's free shared VID/PID pair. See the file USB-IDs-for-free.txt for + * details. + */ +#define USB_CFG_DEVICE_NAME 'T', 'e', 'm', 'p', 'l', 'a', 't', 'e' +#define USB_CFG_DEVICE_NAME_LEN 8 +/* Same as above for the device name. If you don't want a device name, undefine + * the macros. See the file USB-IDs-for-free.txt before you assign a name if + * you use a shared VID/PID. + */ +/*#define USB_CFG_SERIAL_NUMBER 'N', 'o', 'n', 'e' */ +/*#define USB_CFG_SERIAL_NUMBER_LEN 0 */ +/* Same as above for the serial number. If you don't want a serial number, + * undefine the macros. + * It may be useful to provide the serial number through other means than at + * compile time. See the section about descriptor properties below for how + * to fine tune control over USB descriptors such as the string descriptor + * for the serial number. + */ +#define USB_CFG_DEVICE_CLASS 0xff /* set to 0 if deferred to interface */ +#define USB_CFG_DEVICE_SUBCLASS 0 +/* See USB specification if you want to conform to an existing device class. + * Class 0xff is "vendor specific". + */ +#define USB_CFG_INTERFACE_CLASS 0 /* define class here if not at device level */ +#define USB_CFG_INTERFACE_SUBCLASS 0 +#define USB_CFG_INTERFACE_PROTOCOL 0 +/* See USB specification if you want to conform to an existing device class or + * protocol. The following classes must be set at interface level: + * HID class is 3, no subclass and protocol required (but may be useful!) + * CDC class is 2, use subclass 2 and protocol 1 for ACM + */ +/* #define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 42 */ +/* Define this to the length of the HID report descriptor, if you implement + * an HID device. Otherwise don't define it or define it to 0. + * If you use this define, you must add a PROGMEM character array named + * "usbHidReportDescriptor" to your code which contains the report descriptor. + * Don't forget to keep the array and this define in sync! + */ + +/* #define USB_PUBLIC static */ +/* Use the define above if you #include usbdrv.c instead of linking against it. + * This technique saves a couple of bytes in flash memory. + */ + +/* ------------------- Fine Control over USB Descriptors ------------------- */ +/* If you don't want to use the driver's default USB descriptors, you can + * provide our own. These can be provided as (1) fixed length static data in + * flash memory, (2) fixed length static data in RAM or (3) dynamically at + * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more + * information about this function. + * Descriptor handling is configured through the descriptor's properties. If + * no properties are defined or if they are 0, the default descriptor is used. + * Possible properties are: + * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched + * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is + * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if + * you want RAM pointers. + * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found + * in static memory is in RAM, not in flash memory. + * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash), + * the driver must know the descriptor's length. The descriptor itself is + * found at the address of a well known identifier (see below). + * List of static descriptor names (must be declared PROGMEM if in flash): + * char usbDescriptorDevice[]; + * char usbDescriptorConfiguration[]; + * char usbDescriptorHidReport[]; + * char usbDescriptorString0[]; + * int usbDescriptorStringVendor[]; + * int usbDescriptorStringDevice[]; + * int usbDescriptorStringSerialNumber[]; + * Other descriptors can't be provided statically, they must be provided + * dynamically at runtime. + * + * Descriptor properties are or-ed or added together, e.g.: + * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18)) + * + * The following descriptors are defined: + * USB_CFG_DESCR_PROPS_DEVICE + * USB_CFG_DESCR_PROPS_CONFIGURATION + * USB_CFG_DESCR_PROPS_STRINGS + * USB_CFG_DESCR_PROPS_STRING_0 + * USB_CFG_DESCR_PROPS_STRING_VENDOR + * USB_CFG_DESCR_PROPS_STRING_PRODUCT + * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER + * USB_CFG_DESCR_PROPS_HID + * USB_CFG_DESCR_PROPS_HID_REPORT + * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver) + * + * Note about string descriptors: String descriptors are not just strings, they + * are Unicode strings prefixed with a 2 byte header. Example: + * int serialNumberDescriptor[] = { + * USB_STRING_DESCRIPTOR_HEADER(6), + * 'S', 'e', 'r', 'i', 'a', 'l' + * }; + */ + +#define USB_CFG_DESCR_PROPS_DEVICE 0 +#define USB_CFG_DESCR_PROPS_CONFIGURATION 0 +#define USB_CFG_DESCR_PROPS_STRINGS 0 +#define USB_CFG_DESCR_PROPS_STRING_0 0 +#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0 +#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0 +#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0 +#define USB_CFG_DESCR_PROPS_HID 0 +#define USB_CFG_DESCR_PROPS_HID_REPORT 0 +#define USB_CFG_DESCR_PROPS_UNKNOWN 0 + +/* ----------------------- Optional MCU Description ------------------------ */ + +/* The following configurations have working defaults in usbdrv.h. You + * usually don't need to set them explicitly. Only if you want to run + * the driver on a device which is not yet supported or with a compiler + * which is not fully supported (such as IAR C) or if you use a differnt + * interrupt than INT0, you may have to define some of these. + */ +/* #define USB_INTR_CFG MCUCR */ +/* #define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) */ +/* #define USB_INTR_CFG_CLR 0 */ +/* #define USB_INTR_ENABLE GIMSK */ +/* #define USB_INTR_ENABLE_BIT INT0 */ +/* #define USB_INTR_PENDING GIFR */ +/* #define USB_INTR_PENDING_BIT INTF0 */ +/* #define USB_INTR_VECTOR SIG_INTERRUPT0 */ + +#endif /* __usbconfig_h_included__ */ diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/usbconfig.h b/hardware/digistump/avr/libraries/DigisparkJoystick/usbconfig.h new file mode 100644 index 0000000..dd5b32a --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/usbconfig.h @@ -0,0 +1,398 @@ +/* Name: usbconfig.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2005-04-01 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbconfig-prototype.h 767 2009-08-22 11:39:22Z cs $ + */ + +#ifndef __usbconfig_h_included__ +#define __usbconfig_h_included__ + +/* +General Description: +This file is an example configuration (with inline documentation) for the USB +driver. It configures V-USB for USB D+ connected to Port D bit 2 (which is +also hardware interrupt 0 on many devices) and USB D- to Port D bit 4. You may +wire the lines to any other port, as long as D+ is also wired to INT0 (or any +other hardware interrupt, as long as it is the highest level interrupt, see +section at the end of this file). ++ To create your own usbconfig.h file, copy this file to your project's ++ firmware source directory) and rename it to "usbconfig.h". ++ Then edit it accordingly. +*/ + +/* ---------------------------- Hardware Config ---------------------------- */ + +#if defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 1 +#define USB_CFG_DPLUS_BIT 2 + +#elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 4 + +#elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 6 + +#elif defined (__AVR_ATtiny461__) || defined (__AVR_ATtiny861__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 5 +#define USB_CFG_DPLUS_BIT 6 +#else +/* ATtiny2313, ATmega8/48/88/168 */ +#define USB_CFG_IOPORTNAME D +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 2 +#endif +#define USB_CFG_CLOCK_KHZ (F_CPU/1000) +/* Clock rate of the AVR in kHz. Legal values are 12000, 12800, 15000, 16000, + * 16500 and 20000. The 12.8 MHz and 16.5 MHz versions of the code require no + * crystal, they tolerate +/- 1% deviation from the nominal frequency. All + * other rates require a precision of 2000 ppm and thus a crystal! + * Default if not specified: 12 MHz + */ +#define USB_CFG_CHECK_CRC 0 +/* Define this to 1 if you want that the driver checks integrity of incoming + * data packets (CRC checks). CRC checks cost quite a bit of code size and are + * currently only available for 18 MHz crystal clock. You must choose + * USB_CFG_CLOCK_KHZ = 18000 if you enable this option. + */ + +/* ----------------------- Optional Hardware Config ------------------------ */ + +//#define USB_CFG_PULLUP_IOPORTNAME D +/* If you connect the 1.5k pullup resistor from D- to a port pin instead of + * V+, you can connect and disconnect the device from firmware by calling + * the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h). + * This constant defines the port on which the pullup resistor is connected. + */ +//#define USB_CFG_PULLUP_BIT 5 +/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined + * above) where the 1.5k pullup resistor is connected. See description + * above for details. + */ + +/* --------------------------- Functional Range ---------------------------- */ + +#define USB_CFG_HAVE_INTRIN_ENDPOINT 1 +/* Define this to 1 if you want to compile a version with two endpoints: The + * default control endpoint 0 and an interrupt-in endpoint (any other endpoint + * number). + */ +#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0 +/* Define this to 1 if you want to compile a version with three endpoints: The + * default control endpoint 0, an interrupt-in endpoint 3 (or the number + * configured below) and a catch-all default interrupt-in endpoint as above. + * You must also define USB_CFG_HAVE_INTRIN_ENDPOINT to 1 for this feature. + */ +#define USB_CFG_EP3_NUMBER 3 +/* If the so-called endpoint 3 is used, it can now be configured to any other + * endpoint number (except 0) with this macro. Default if undefined is 3. + */ +/* #define USB_INITIAL_DATATOKEN USBPID_DATA1 */ +/* The above macro defines the startup condition for data toggling on the + * interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA1. + * Since the token is toggled BEFORE sending any data, the first packet is + * sent with the oposite value of this configuration! + */ +#define USB_CFG_IMPLEMENT_HALT 0 +/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature + * for endpoint 1 (interrupt endpoint). Although you may not need this feature, + * it is required by the standard. We have made it a config option because it + * bloats the code considerably. + */ +#define USB_CFG_SUPPRESS_INTR_CODE 0 +/* Define this to 1 if you want to declare interrupt-in endpoints, but don't + * want to send any data over them. If this macro is defined to 1, functions + * usbSetInterrupt() and usbSetInterrupt3() are omitted. This is useful if + * you need the interrupt-in endpoints in order to comply to an interface + * (e.g. HID), but never want to send any data. This option saves a couple + * of bytes in flash memory and the transmit buffers in RAM. + */ +#define USB_CFG_INTR_POLL_INTERVAL 10 +/* If you compile a version with endpoint 1 (interrupt-in), this is the poll + * interval. The value is in milliseconds and must not be less than 10 ms for + * low speed devices. + */ +#define USB_CFG_IS_SELF_POWERED 0 +/* Define this to 1 if the device has its own power supply. Set it to 0 if the + * device is powered from the USB bus. + */ +#define USB_CFG_MAX_BUS_POWER 100 +/* Set this variable to the maximum USB bus power consumption of your device. + * The value is in milliamperes. [It will be divided by two since USB + * communicates power requirements in units of 2 mA.] + */ +#define USB_CFG_IMPLEMENT_FN_WRITE 0 +/* Set this to 1 if you want usbFunctionWrite() to be called for control-out + * transfers. Set it to 0 if you don't need it and want to save a couple of + * bytes. + */ +#define USB_CFG_IMPLEMENT_FN_READ 0 +/* Set this to 1 if you need to send control replies which are generated + * "on the fly" when usbFunctionRead() is called. If you only want to send + * data from a static buffer, set it to 0 and return the data from + * usbFunctionSetup(). This saves a couple of bytes. + */ +#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0 +/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints. + * You must implement the function usbFunctionWriteOut() which receives all + * interrupt/bulk data sent to any endpoint other than 0. The endpoint number + * can be found in 'usbRxToken'. + */ +#define USB_CFG_HAVE_FLOWCONTROL 0 +/* Define this to 1 if you want flowcontrol over USB data. See the definition + * of the macros usbDisableAllRequests() and usbEnableAllRequests() in + * usbdrv.h. + */ +#define USB_CFG_LONG_TRANSFERS 0 +/* Define this to 1 if you want to send/receive blocks of more than 254 bytes + * in a single control-in or control-out transfer. Note that the capability + * for long transfers increases the driver size. + */ +/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */ +/* This macro is a hook if you want to do unconventional things. If it is + * defined, it's inserted at the beginning of received message processing. + * If you eat the received message and don't want default processing to + * proceed, do a return after doing your things. One possible application + * (besides debugging) is to flash a status LED on each packet. + */ +/* #define USB_RESET_HOOK(resetStarts) if(!resetStarts){hadUsbReset();} */ +/* This macro is a hook if you need to know when an USB RESET occurs. It has + * one parameter which distinguishes between the start of RESET state and its + * end. + */ +/* #define USB_SET_ADDRESS_HOOK() hadAddressAssigned(); */ +/* This macro (if defined) is executed when a USB SET_ADDRESS request was + * received. + */ +#define USB_COUNT_SOF 0 +/* define this macro to 1 if you need the global variable "usbSofCount" which + * counts SOF packets. This feature requires that the hardware interrupt is + * connected to D- instead of D+. + */ +/* #ifdef __ASSEMBLER__ + * macro myAssemblerMacro + * in YL, TCNT0 + * sts timer0Snapshot, YL + * endm + * #endif + * #define USB_SOF_HOOK myAssemblerMacro + * This macro (if defined) is executed in the assembler module when a + * Start Of Frame condition is detected. It is recommended to define it to + * the name of an assembler macro which is defined here as well so that more + * than one assembler instruction can be used. The macro may use the register + * YL and modify SREG. If it lasts longer than a couple of cycles, USB messages + * immediately after an SOF pulse may be lost and must be retried by the host. + * What can you do with this hook? Since the SOF signal occurs exactly every + * 1 ms (unless the host is in sleep mode), you can use it to tune OSCCAL in + * designs running on the internal RC oscillator. + * Please note that Start Of Frame detection works only if D- is wired to the + * interrupt, not D+. THIS IS DIFFERENT THAN MOST EXAMPLES! + */ +#define USB_CFG_CHECK_DATA_TOGGLING 0 +/* define this macro to 1 if you want to filter out duplicate data packets + * sent by the host. Duplicates occur only as a consequence of communication + * errors, when the host does not receive an ACK. Please note that you need to + * implement the filtering yourself in usbFunctionWriteOut() and + * usbFunctionWrite(). Use the global usbCurrentDataToken and a static variable + * for each control- and out-endpoint to check for duplicate packets. + */ +#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 1 +#include "osccal.h" +/* define this macro to 1 if you want the function usbMeasureFrameLength() + * compiled in. This function can be used to calibrate the AVR's RC oscillator. + */ +#define USB_USE_FAST_CRC 0 +/* The assembler module has two implementations for the CRC algorithm. One is + * faster, the other is smaller. This CRC routine is only used for transmitted + * messages where timing is not critical. The faster routine needs 31 cycles + * per byte while the smaller one needs 61 to 69 cycles. The faster routine + * may be worth the 32 bytes bigger code size if you transmit lots of data and + * run the AVR close to its limit. + */ + +/* -------------------------- Device Description --------------------------- */ + +#define USB_CFG_VENDOR_ID 0xc0, 0x16 +/* USB vendor ID for the device, low byte first. If you have registered your + * own Vendor ID, define it here. Otherwise you may use one of obdev's free + * shared VID/PID pairs. Be sure to read USB-IDs-for-free.txt for rules! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_ID 0xdc, 0x27 +/* This is the ID of the product, low byte first. It is interpreted in the + * scope of the vendor ID. If you have registered your own VID with usb.org + * or if you have licensed a PID from somebody else, define it here. Otherwise + * you may use one of obdev's free shared VID/PID pairs. See the file + * USB-IDs-for-free.txt for details! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_VERSION 0x00, 0x01 +/* Version number of the device: Minor number first, then major number. + */ +#define USB_CFG_VENDOR_NAME 'd','i','g','i','s','t','u','m','p','.','c','o','m' +#define USB_CFG_VENDOR_NAME_LEN 13 +/* These two values define the vendor name returned by the USB device. The name + * must be given as a list of characters under single quotes. The characters + * are interpreted as Unicode (UTF-16) entities. + * If you don't want a vendor name string, undefine these macros. + * ALWAYS define a vendor name containing your Internet domain name if you use + * obdev's free shared VID/PID pair. See the file USB-IDs-for-free.txt for + * details. + */ +#define USB_CFG_DEVICE_NAME 'D','i','g','i','K','e','y' +#define USB_CFG_DEVICE_NAME_LEN 7 +/* Same as above for the device name. If you don't want a device name, undefine + * the macros. See the file USB-IDs-for-free.txt before you assign a name if + * you use a shared VID/PID. + */ +#define USB_CFG_SERIAL_NUMBER 'd','i','g','i','s','t','u','m','p','.','c','o','m',':','J','o','y' +#define USB_CFG_SERIAL_NUMBER_LEN 17 +/* Same as above for the serial number. If you don't want a serial number, + * undefine the macros. + * It may be useful to provide the serial number through other means than at + * compile time. See the section about descriptor properties below for how + * to fine tune control over USB descriptors such as the string descriptor + * for the serial number. + */ +#define USB_CFG_DEVICE_CLASS 0 /* set to 0 if deferred to interface */ +#define USB_CFG_DEVICE_SUBCLASS 0 +/* See USB specification if you want to conform to an existing device class. + * Class 0xff is "vendor specific". + */ +#define USB_CFG_INTERFACE_CLASS 0x03 /* HID */ /* define class here if not at device level */ +#define USB_CFG_INTERFACE_SUBCLASS 0x0 +#define USB_CFG_INTERFACE_PROTOCOL 0x0 +/* See USB specification if you want to conform to an existing device class or + * protocol. The following classes must be set at interface level: + * HID class is 3, no subclass and protocol required (but may be useful!) + * CDC class is 2, use subclass 2 and protocol 1 for ACM + */ +#define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 53 +/* Define this to the length of the HID report descriptor, if you implement + * an HID device. Otherwise don't define it or define it to 0. + * If you use this define, you must add a PROGMEM character array named + * "usbHidReportDescriptor" to your code which contains the report descriptor. + * Don't forget to keep the array and this define in sync! + */ + +/* #define USB_PUBLIC static */ +/* Use the define above if you #include usbdrv.c instead of linking against it. + * This technique saves a couple of bytes in flash memory. + */ + +/* ------------------- Fine Control over USB Descriptors ------------------- */ +/* If you don't want to use the driver's default USB descriptors, you can + * provide our own. These can be provided as (1) fixed length static data in + * flash memory, (2) fixed length static data in RAM or (3) dynamically at + * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more + * information about this function. + * Descriptor handling is configured through the descriptor's properties. If + * no properties are defined or if they are 0, the default descriptor is used. + * Possible properties are: + * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched + * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is + * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if + * you want RAM pointers. + * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found + * in static memory is in RAM, not in flash memory. + * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash), + * the driver must know the descriptor's length. The descriptor itself is + * found at the address of a well known identifier (see below). + * List of static descriptor names (must be declared PROGMEM if in flash): + * char usbDescriptorDevice[]; + * char usbDescriptorConfiguration[]; + * char usbDescriptorHidReport[]; + * char usbDescriptorString0[]; + * int usbDescriptorStringVendor[]; + * int usbDescriptorStringDevice[]; + * int usbDescriptorStringSerialNumber[]; + * Other descriptors can't be provided statically, they must be provided + * dynamically at runtime. + * + * Descriptor properties are or-ed or added together, e.g.: + * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18)) + * + * The following descriptors are defined: + * USB_CFG_DESCR_PROPS_DEVICE + * USB_CFG_DESCR_PROPS_CONFIGURATION + * USB_CFG_DESCR_PROPS_STRINGS + * USB_CFG_DESCR_PROPS_STRING_0 + * USB_CFG_DESCR_PROPS_STRING_VENDOR + * USB_CFG_DESCR_PROPS_STRING_PRODUCT + * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER + * USB_CFG_DESCR_PROPS_HID + * USB_CFG_DESCR_PROPS_HID_REPORT + * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver) + * + * Note about string descriptors: String descriptors are not just strings, they + * are Unicode strings prefixed with a 2 byte header. Example: + * int serialNumberDescriptor[] = { + * USB_STRING_DESCRIPTOR_HEADER(6), + * 'S', 'e', 'r', 'i', 'a', 'l' + * }; + */ + +#define USB_CFG_DESCR_PROPS_DEVICE 0 +#define USB_CFG_DESCR_PROPS_CONFIGURATION 0 +#define USB_CFG_DESCR_PROPS_STRINGS 0 +#define USB_CFG_DESCR_PROPS_STRING_0 0 +#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0 +#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0 +#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0 +#define USB_CFG_DESCR_PROPS_HID 0 +#define USB_CFG_DESCR_PROPS_HID_REPORT USB_PROP_IS_DYNAMIC +#define USB_CFG_DESCR_PROPS_UNKNOWN 0 + +/* ----------------------- Optional MCU Description ------------------------ */ + +/* The following configurations have working defaults in usbdrv.h. You + * usually don't need to set them explicitly. Only if you want to run + * the driver on a device which is not yet supported or with a compiler + * which is not fully supported (such as IAR C) or if you use a differnt + * interrupt than INT0, you may have to define some of these. + */ +/* #define USB_INTR_CFG MCUCR */ +/* #define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) */ +/* #define USB_INTR_CFG_CLR 0 */ +/* #define USB_INTR_ENABLE GIMSK */ +/* #define USB_INTR_ENABLE_BIT INT0 */ +/* #define USB_INTR_PENDING GIFR */ +/* #define USB_INTR_PENDING_BIT INTF0 */ +/* #define USB_INTR_VECTOR SIG_INTERRUPT0 */ + + #if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define USB_INTR_CFG PCMSK +#define USB_INTR_CFG_SET (1<len & 0x10){ /* packet buffer was empty */ + txStatus->buffer[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */ + }else{ + txStatus->len = USBPID_NAK; /* avoid sending outdated (overwritten) interrupt data */ + } + p = txStatus->buffer + 1; + i = len; + do{ /* if len == 0, we still copy 1 byte, but that's no problem */ + *p++ = *data++; + }while(--i > 0); /* loop control at the end is 2 bytes shorter than at beginning */ + usbCrc16Append(&txStatus->buffer[1], len); + txStatus->len = len + 4; /* len must be given including sync byte */ + DBG2(0x21 + (((int)txStatus >> 3) & 3), txStatus->buffer, len + 3); +} + +USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len) +{ + usbGenericSetInterrupt(data, len, &usbTxStatus1); +} +#endif + +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 +USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len) +{ + usbGenericSetInterrupt(data, len, &usbTxStatus3); +} +#endif +#endif /* USB_CFG_SUPPRESS_INTR_CODE */ + +/* ------------------ utilities for code following below ------------------- */ + +/* Use defines for the switch statement so that we can choose between an + * if()else if() and a switch/case based implementation. switch() is more + * efficient for a LARGE set of sequential choices, if() is better in all other + * cases. + */ +#if USB_CFG_USE_SWITCH_STATEMENT +# define SWITCH_START(cmd) switch(cmd){{ +# define SWITCH_CASE(value) }break; case (value):{ +# define SWITCH_CASE2(v1,v2) }break; case (v1): case(v2):{ +# define SWITCH_CASE3(v1,v2,v3) }break; case (v1): case(v2): case(v3):{ +# define SWITCH_DEFAULT }break; default:{ +# define SWITCH_END }} +#else +# define SWITCH_START(cmd) {uchar _cmd = cmd; if(0){ +# define SWITCH_CASE(value) }else if(_cmd == (value)){ +# define SWITCH_CASE2(v1,v2) }else if(_cmd == (v1) || _cmd == (v2)){ +# define SWITCH_CASE3(v1,v2,v3) }else if(_cmd == (v1) || _cmd == (v2) || (_cmd == v3)){ +# define SWITCH_DEFAULT }else{ +# define SWITCH_END }} +#endif + +#ifndef USB_RX_USER_HOOK +#define USB_RX_USER_HOOK(data, len) +#endif +#ifndef USB_SET_ADDRESS_HOOK +#define USB_SET_ADDRESS_HOOK() +#endif + +/* ------------------------------------------------------------------------- */ + +/* We use if() instead of #if in the macro below because #if can't be used + * in macros and the compiler optimizes constant conditions anyway. + * This may cause problems with undefined symbols if compiled without + * optimizing! + */ +#define GET_DESCRIPTOR(cfgProp, staticName) \ + if(cfgProp){ \ + if((cfgProp) & USB_PROP_IS_RAM) \ + flags = 0; \ + if((cfgProp) & USB_PROP_IS_DYNAMIC){ \ + len = usbFunctionDescriptor(rq); \ + }else{ \ + len = USB_PROP_LENGTH(cfgProp); \ + usbMsgPtr = (uchar *)(staticName); \ + } \ + } + +/* usbDriverDescriptor() is similar to usbFunctionDescriptor(), but used + * internally for all types of descriptors. + */ +static inline usbMsgLen_t usbDriverDescriptor(usbRequest_t *rq) +{ +usbMsgLen_t len = 0; +uchar flags = USB_FLG_MSGPTR_IS_ROM; + + SWITCH_START(rq->wValue.bytes[1]) + SWITCH_CASE(USBDESCR_DEVICE) /* 1 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_DEVICE, usbDescriptorDevice) + SWITCH_CASE(USBDESCR_CONFIG) /* 2 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_CONFIGURATION, usbDescriptorConfiguration) + SWITCH_CASE(USBDESCR_STRING) /* 3 */ +#if USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC + if(USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_RAM) + flags = 0; + len = usbFunctionDescriptor(rq); +#else /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */ + SWITCH_START(rq->wValue.bytes[0]) + SWITCH_CASE(0) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_0, usbDescriptorString0) + SWITCH_CASE(1) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_VENDOR, usbDescriptorStringVendor) + SWITCH_CASE(2) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_PRODUCT, usbDescriptorStringDevice) + SWITCH_CASE(3) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER, usbDescriptorStringSerialNumber) + SWITCH_DEFAULT + if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){ + len = usbFunctionDescriptor(rq); + } + SWITCH_END +#endif /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */ +#if USB_CFG_DESCR_PROPS_HID_REPORT /* only support HID descriptors if enabled */ + SWITCH_CASE(USBDESCR_HID) /* 0x21 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID, usbDescriptorConfiguration + 18) + SWITCH_CASE(USBDESCR_HID_REPORT)/* 0x22 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID_REPORT, usbDescriptorHidReport) +#endif + SWITCH_DEFAULT + if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){ + len = usbFunctionDescriptor(rq); + } + SWITCH_END + usbMsgFlags = flags; + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbDriverSetup() is similar to usbFunctionSetup(), but it's used for + * standard requests instead of class and custom requests. + */ +static inline usbMsgLen_t usbDriverSetup(usbRequest_t *rq) +{ +uchar len = 0, *dataPtr = usbTxBuf + 9; /* there are 2 bytes free space at the end of the buffer */ +uchar value = rq->wValue.bytes[0]; +#if USB_CFG_IMPLEMENT_HALT +uchar index = rq->wIndex.bytes[0]; +#endif + + dataPtr[0] = 0; /* default reply common to USBRQ_GET_STATUS and USBRQ_GET_INTERFACE */ + SWITCH_START(rq->bRequest) + SWITCH_CASE(USBRQ_GET_STATUS) /* 0 */ + uchar recipient = rq->bmRequestType & USBRQ_RCPT_MASK; /* assign arith ops to variables to enforce byte size */ + if(USB_CFG_IS_SELF_POWERED && recipient == USBRQ_RCPT_DEVICE) + dataPtr[0] = USB_CFG_IS_SELF_POWERED; +#if USB_CFG_IMPLEMENT_HALT + if(recipient == USBRQ_RCPT_ENDPOINT && index == 0x81) /* request status for endpoint 1 */ + dataPtr[0] = usbTxLen1 == USBPID_STALL; +#endif + dataPtr[1] = 0; + len = 2; +#if USB_CFG_IMPLEMENT_HALT + SWITCH_CASE2(USBRQ_CLEAR_FEATURE, USBRQ_SET_FEATURE) /* 1, 3 */ + if(value == 0 && index == 0x81){ /* feature 0 == HALT for endpoint == 1 */ + usbTxLen1 = rq->bRequest == USBRQ_CLEAR_FEATURE ? USBPID_NAK : USBPID_STALL; + usbResetDataToggling(); + } +#endif + SWITCH_CASE(USBRQ_SET_ADDRESS) /* 5 */ + usbNewDeviceAddr = value; + USB_SET_ADDRESS_HOOK(); + SWITCH_CASE(USBRQ_GET_DESCRIPTOR) /* 6 */ + len = usbDriverDescriptor(rq); + goto skipMsgPtrAssignment; + SWITCH_CASE(USBRQ_GET_CONFIGURATION) /* 8 */ + dataPtr = &usbConfiguration; /* send current configuration value */ + len = 1; + SWITCH_CASE(USBRQ_SET_CONFIGURATION) /* 9 */ + usbConfiguration = value; + usbResetStall(); + SWITCH_CASE(USBRQ_GET_INTERFACE) /* 10 */ + len = 1; +#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE + SWITCH_CASE(USBRQ_SET_INTERFACE) /* 11 */ + usbResetDataToggling(); + usbResetStall(); +#endif + SWITCH_DEFAULT /* 7=SET_DESCRIPTOR, 12=SYNC_FRAME */ + /* Should we add an optional hook here? */ + SWITCH_END + usbMsgPtr = dataPtr; +skipMsgPtrAssignment: + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbProcessRx() is called for every message received by the interrupt + * routine. It distinguishes between SETUP and DATA packets and processes + * them accordingly. + */ +static inline void usbProcessRx(uchar *data, uchar len) +{ + usbRequest_t *rq = (usbRequest_t *)((void *)data); + +/* usbRxToken can be: + * 0x2d 00101101 (USBPID_SETUP for setup data) + * 0xe1 11100001 (USBPID_OUT: data phase of setup transfer) + * 0...0x0f for OUT on endpoint X + */ + DBG2(0x10 + (usbRxToken & 0xf), data, len + 2); /* SETUP=1d, SETUP-DATA=11, OUTx=1x */ + USB_RX_USER_HOOK(data, len) +#if USB_CFG_IMPLEMENT_FN_WRITEOUT + if(usbRxToken < 0x10){ /* OUT to endpoint != 0: endpoint number in usbRxToken */ + usbFunctionWriteOut(data, len); + return; + } +#endif + if(usbRxToken == (uchar)USBPID_SETUP){ + if(len != 8) /* Setup size must be always 8 bytes. Ignore otherwise. */ + return; + usbMsgLen_t replyLen; + usbTxBuf[0] = USBPID_DATA0; /* initialize data toggling */ + usbTxLen = USBPID_NAK; /* abort pending transmit */ + usbMsgFlags = 0; + uchar type = rq->bmRequestType & USBRQ_TYPE_MASK; + if(type != USBRQ_TYPE_STANDARD){ /* standard requests are handled by driver */ + replyLen = usbFunctionSetup(data); + }else{ + replyLen = usbDriverSetup(rq); + } +#if USB_CFG_IMPLEMENT_FN_READ || USB_CFG_IMPLEMENT_FN_WRITE + if(replyLen == USB_NO_MSG){ /* use user-supplied read/write function */ + /* do some conditioning on replyLen, but on IN transfers only */ + if((rq->bmRequestType & USBRQ_DIR_MASK) != USBRQ_DIR_HOST_TO_DEVICE){ + if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */ + replyLen = rq->wLength.bytes[0]; + }else{ + replyLen = rq->wLength.word; + } + } + usbMsgFlags = USB_FLG_USE_USER_RW; + }else /* The 'else' prevents that we limit a replyLen of USB_NO_MSG to the maximum transfer len. */ +#endif + if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */ + if(!rq->wLength.bytes[1] && replyLen > rq->wLength.bytes[0]) /* limit length to max */ + replyLen = rq->wLength.bytes[0]; + }else{ + if(replyLen > rq->wLength.word) /* limit length to max */ + replyLen = rq->wLength.word; + } + usbMsgLen = replyLen; + }else{ /* usbRxToken must be USBPID_OUT, which means data phase of setup (control-out) */ +#if USB_CFG_IMPLEMENT_FN_WRITE + if(usbMsgFlags & USB_FLG_USE_USER_RW){ + uchar rval = usbFunctionWrite(data, len); + if(rval == 0xff){ /* an error occurred */ + usbTxLen = USBPID_STALL; + }else if(rval != 0){ /* This was the final package */ + usbMsgLen = 0; /* answer with a zero-sized data packet */ + } + } +#endif + } +} + +/* ------------------------------------------------------------------------- */ + +/* This function is similar to usbFunctionRead(), but it's also called for + * data handled automatically by the driver (e.g. descriptor reads). + */ +static uchar usbDeviceRead(uchar *data, uchar len) +{ + if(len > 0){ /* don't bother app with 0 sized reads */ +#if USB_CFG_IMPLEMENT_FN_READ + if(usbMsgFlags & USB_FLG_USE_USER_RW){ + len = usbFunctionRead(data, len); + }else +#endif + { + uchar i = len, *r = usbMsgPtr; + if(usbMsgFlags & USB_FLG_MSGPTR_IS_ROM){ /* ROM data */ + do{ + uchar c = USB_READ_FLASH(r); /* assign to char size variable to enforce byte ops */ + *data++ = c; + r++; + }while(--i); + }else{ /* RAM data */ + do{ + *data++ = *r++; + }while(--i); + } + usbMsgPtr = r; + } + } + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbBuildTxBlock() is called when we have data to transmit and the + * interrupt routine's transmit buffer is empty. + */ +static inline void usbBuildTxBlock(void) +{ +usbMsgLen_t wantLen; +uchar len; + + wantLen = usbMsgLen; + if(wantLen > 8) + wantLen = 8; + usbMsgLen -= wantLen; + usbTxBuf[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* DATA toggling */ + len = usbDeviceRead(usbTxBuf + 1, wantLen); + if(len <= 8){ /* valid data packet */ + usbCrc16Append(&usbTxBuf[1], len); + len += 4; /* length including sync byte */ + if(len < 12) /* a partial package identifies end of message */ + usbMsgLen = USB_NO_MSG; + }else{ + len = USBPID_STALL; /* stall the endpoint */ + usbMsgLen = USB_NO_MSG; + } + usbTxLen = len; + DBG2(0x20, usbTxBuf, len-1); +} + +/* ------------------------------------------------------------------------- */ + +static inline void usbHandleResetHook(uchar notResetState) +{ +#ifdef USB_RESET_HOOK +static uchar wasReset; +uchar isReset = !notResetState; + + if(wasReset != isReset){ + USB_RESET_HOOK(isReset); + wasReset = isReset; + } +#endif +} + +/* ------------------------------------------------------------------------- */ + +USB_PUBLIC void usbPoll(void) +{ +schar len; +uchar i; + + len = usbRxLen - 3; + if(len >= 0){ +/* We could check CRC16 here -- but ACK has already been sent anyway. If you + * need data integrity checks with this driver, check the CRC in your app + * code and report errors back to the host. Since the ACK was already sent, + * retries must be handled on application level. + * unsigned crc = usbCrc16(buffer + 1, usbRxLen - 3); + */ + usbProcessRx(usbRxBuf + USB_BUFSIZE + 1 - usbInputBufOffset, len); +#if USB_CFG_HAVE_FLOWCONTROL + if(usbRxLen > 0) /* only mark as available if not inactivated */ + usbRxLen = 0; +#else + usbRxLen = 0; /* mark rx buffer as available */ +#endif + } + if(usbTxLen & 0x10){ /* transmit system idle */ + if(usbMsgLen != USB_NO_MSG){ /* transmit data pending? */ + usbBuildTxBlock(); + } + } + for(i = 20; i > 0; i--){ + uchar usbLineStatus = USBIN & USBMASK; + if(usbLineStatus != 0) /* SE0 has ended */ + goto isNotReset; + } + /* RESET condition, called multiple times during reset */ + usbNewDeviceAddr = 0; + usbDeviceAddr = 0; + usbResetStall(); + DBG1(0xff, 0, 0); +isNotReset: + usbHandleResetHook(i); +} + +/* ------------------------------------------------------------------------- */ + +USB_PUBLIC void usbInit(void) +{ +#if USB_INTR_CFG_SET != 0 + USB_INTR_CFG |= USB_INTR_CFG_SET; +#endif +#if USB_INTR_CFG_CLR != 0 + USB_INTR_CFG &= ~(USB_INTR_CFG_CLR); +#endif + USB_INTR_ENABLE |= (1 << USB_INTR_ENABLE_BIT); + usbResetDataToggling(); +#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE + usbTxLen1 = USBPID_NAK; +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 + usbTxLen3 = USBPID_NAK; +#endif +#endif +} + +/* ------------------------------------------------------------------------- */ diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrv.h b/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrv.h new file mode 100644 index 0000000..e766173 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrv.h @@ -0,0 +1,766 @@ +/* Name: usbdrv.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2004-12-29 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbdrv.h 769 2009-08-22 11:49:05Z cs $ + */ + +#ifndef __usbdrv_h_included__ +#define __usbdrv_h_included__ + +#include "usbconfig.h" +#include "usbportability.h" + +/* +Hardware Prerequisites: +======================= +USB lines D+ and D- MUST be wired to the same I/O port. We recommend that D+ +triggers the interrupt (best achieved by using INT0 for D+), but it is also +possible to trigger the interrupt from D-. If D- is used, interrupts are also +triggered by SOF packets. D- requires a pull-up of 1.5k to +3.5V (and the +device must be powered at 3.5V) to identify as low-speed USB device. A +pull-down or pull-up of 1M SHOULD be connected from D+ to +3.5V to prevent +interference when no USB master is connected. If you use Zener diodes to limit +the voltage on D+ and D-, you MUST use a pull-down resistor, not a pull-up. +We use D+ as interrupt source and not D- because it does not trigger on +keep-alive and RESET states. If you want to count keep-alive events with +USB_COUNT_SOF, you MUST use D- as an interrupt source. + +As a compile time option, the 1.5k pull-up resistor on D- can be made +switchable to allow the device to disconnect at will. See the definition of +usbDeviceConnect() and usbDeviceDisconnect() further down in this file. + +Please adapt the values in usbconfig.h according to your hardware! + +The device MUST be clocked at exactly 12 MHz, 15 MHz, 16 MHz or 20 MHz +or at 12.8 MHz resp. 16.5 MHz +/- 1%. See usbconfig-prototype.h for details. + + +Limitations: +============ +Robustness with respect to communication errors: +The driver assumes error-free communication. It DOES check for errors in +the PID, but does NOT check bit stuffing errors, SE0 in middle of a byte, +token CRC (5 bit) and data CRC (16 bit). CRC checks can not be performed due +to timing constraints: We must start sending a reply within 7 bit times. +Bit stuffing and misplaced SE0 would have to be checked in real-time, but CPU +performance does not permit that. The driver does not check Data0/Data1 +toggling, but application software can implement the check. + +Input characteristics: +Since no differential receiver circuit is used, electrical interference +robustness may suffer. The driver samples only one of the data lines with +an ordinary I/O pin's input characteristics. However, since this is only a +low speed USB implementation and the specification allows for 8 times the +bit rate over the same hardware, we should be on the safe side. Even the spec +requires detection of asymmetric states at high bit rate for SE0 detection. + +Number of endpoints: +The driver supports the following endpoints: + +- Endpoint 0, the default control endpoint. +- Any number of interrupt- or bulk-out endpoints. The data is sent to + usbFunctionWriteOut() and USB_CFG_IMPLEMENT_FN_WRITEOUT must be defined + to 1 to activate this feature. The endpoint number can be found in the + global variable 'usbRxToken'. +- One default interrupt- or bulk-in endpoint. This endpoint is used for + interrupt- or bulk-in transfers which are not handled by any other endpoint. + You must define USB_CFG_HAVE_INTRIN_ENDPOINT in order to activate this + feature and call usbSetInterrupt() to send interrupt/bulk data. +- One additional interrupt- or bulk-in endpoint. This was endpoint 3 in + previous versions of this driver but can now be configured to any endpoint + number. You must define USB_CFG_HAVE_INTRIN_ENDPOINT3 in order to activate + this feature and call usbSetInterrupt3() to send interrupt/bulk data. The + endpoint number can be set with USB_CFG_EP3_NUMBER. + +Please note that the USB standard forbids bulk endpoints for low speed devices! +Most operating systems allow them anyway, but the AVR will spend 90% of the CPU +time in the USB interrupt polling for bulk data. + +Maximum data payload: +Data payload of control in and out transfers may be up to 254 bytes. In order +to accept payload data of out transfers, you need to implement +'usbFunctionWrite()'. + +USB Suspend Mode supply current: +The USB standard limits power consumption to 500uA when the bus is in suspend +mode. This is not a problem for self-powered devices since they don't need +bus power anyway. Bus-powered devices can achieve this only by putting the +CPU in sleep mode. The driver does not implement suspend handling by itself. +However, the application may implement activity monitoring and wakeup from +sleep. The host sends regular SE0 states on the bus to keep it active. These +SE0 states can be detected by using D- as the interrupt source. Define +USB_COUNT_SOF to 1 and use the global variable usbSofCount to check for bus +activity. + +Operation without an USB master: +The driver behaves neutral without connection to an USB master if D- reads +as 1. To avoid spurious interrupts, we recommend a high impedance (e.g. 1M) +pull-down or pull-up resistor on D+ (interrupt). If Zener diodes are used, +use a pull-down. If D- becomes statically 0, the driver may block in the +interrupt routine. + +Interrupt latency: +The application must ensure that the USB interrupt is not disabled for more +than 25 cycles (this is for 12 MHz, faster clocks allow longer latency). +This implies that all interrupt routines must either be declared as "INTERRUPT" +instead of "SIGNAL" (see "avr/signal.h") or that they are written in assembler +with "sei" as the first instruction. + +Maximum interrupt duration / CPU cycle consumption: +The driver handles all USB communication during the interrupt service +routine. The routine will not return before an entire USB message is received +and the reply is sent. This may be up to ca. 1200 cycles @ 12 MHz (= 100us) if +the host conforms to the standard. The driver will consume CPU cycles for all +USB messages, even if they address another (low-speed) device on the same bus. + +*/ + +/* ------------------------------------------------------------------------- */ +/* --------------------------- Module Interface ---------------------------- */ +/* ------------------------------------------------------------------------- */ + +#define USBDRV_VERSION 20090822 +/* This define uniquely identifies a driver version. It is a decimal number + * constructed from the driver's release date in the form YYYYMMDD. If the + * driver's behavior or interface changes, you can use this constant to + * distinguish versions. If it is not defined, the driver's release date is + * older than 2006-01-25. + */ + + +#ifndef USB_PUBLIC +#define USB_PUBLIC +#endif +/* USB_PUBLIC is used as declaration attribute for all functions exported by + * the USB driver. The default is no attribute (see above). You may define it + * to static either in usbconfig.h or from the command line if you include + * usbdrv.c instead of linking against it. Including the C module of the driver + * directly in your code saves a couple of bytes in flash memory. + */ + +#ifndef __ASSEMBLER__ +#ifndef uchar +#define uchar unsigned char +#endif +#ifndef schar +#define schar signed char +#endif +/* shortcuts for well defined 8 bit integer types */ + +#if USB_CFG_LONG_TRANSFERS /* if more than 254 bytes transfer size required */ +# define usbMsgLen_t unsigned +#else +# define usbMsgLen_t uchar +#endif +/* usbMsgLen_t is the data type used for transfer lengths. By default, it is + * defined to uchar, allowing a maximum of 254 bytes (255 is reserved for + * USB_NO_MSG below). If the usbconfig.h defines USB_CFG_LONG_TRANSFERS to 1, + * a 16 bit data type is used, allowing up to 16384 bytes (the rest is used + * for flags in the descriptor configuration). + */ +#define USB_NO_MSG ((usbMsgLen_t)-1) /* constant meaning "no message" */ + +struct usbRequest; /* forward declaration */ + +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbInit(void); +/* This function must be called before interrupts are enabled and the main + * loop is entered. We exepct that the PORT and DDR bits for D+ and D- have + * not been changed from their default status (which is 0). If you have changed + * them, set both back to 0 (configure them as input with no internal pull-up). + */ +USB_PUBLIC void usbPoll(void); +/* This function must be called at regular intervals from the main loop. + * Maximum delay between calls is somewhat less than 50ms (USB timeout for + * accepting a Setup message). Otherwise the device will not be recognized. + * Please note that debug outputs through the UART take ~ 0.5ms per byte + * at 19200 bps. + */ +#ifdef __cplusplus +} // extern "C" +#endif +extern const uchar *usbMsgPtr; +/* This variable may be used to pass transmit data to the driver from the + * implementation of usbFunctionWrite(). It is also used internally by the + * driver for standard control requests. + */ +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC usbMsgLen_t usbFunctionSetup(uchar data[8]); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function is called when the driver receives a SETUP transaction from + * the host which is not answered by the driver itself (in practice: class and + * vendor requests). All control transfers start with a SETUP transaction where + * the host communicates the parameters of the following (optional) data + * transfer. The SETUP data is available in the 'data' parameter which can + * (and should) be casted to 'usbRequest_t *' for a more user-friendly access + * to parameters. + * + * If the SETUP indicates a control-in transfer, you should provide the + * requested data to the driver. There are two ways to transfer this data: + * (1) Set the global pointer 'usbMsgPtr' to the base of the static RAM data + * block and return the length of the data in 'usbFunctionSetup()'. The driver + * will handle the rest. Or (2) return USB_NO_MSG in 'usbFunctionSetup()'. The + * driver will then call 'usbFunctionRead()' when data is needed. See the + * documentation for usbFunctionRead() for details. + * + * If the SETUP indicates a control-out transfer, the only way to receive the + * data from the host is through the 'usbFunctionWrite()' call. If you + * implement this function, you must return USB_NO_MSG in 'usbFunctionSetup()' + * to indicate that 'usbFunctionWrite()' should be used. See the documentation + * of this function for more information. If you just want to ignore the data + * sent by the host, return 0 in 'usbFunctionSetup()'. + * + * Note that calls to the functions usbFunctionRead() and usbFunctionWrite() + * are only done if enabled by the configuration in usbconfig.h. + */ +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC usbMsgLen_t usbFunctionDescriptor(struct usbRequest *rq); +#ifdef __cplusplus +} // extern "C" +#endif +/* You need to implement this function ONLY if you provide USB descriptors at + * runtime (which is an expert feature). It is very similar to + * usbFunctionSetup() above, but it is called only to request USB descriptor + * data. See the documentation of usbFunctionSetup() above for more info. + */ +#if USB_CFG_HAVE_INTRIN_ENDPOINT +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function sets the message which will be sent during the next interrupt + * IN transfer. The message is copied to an internal buffer and must not exceed + * a length of 8 bytes. The message may be 0 bytes long just to indicate the + * interrupt status to the host. + * If you need to transfer more bytes, use a control read after the interrupt. + */ +#define usbInterruptIsReady() (usbTxLen1 & 0x10) +/* This macro indicates whether the last interrupt message has already been + * sent. If you set a new interrupt message before the old was sent, the + * message already buffered will be lost. + */ +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 +USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len); +#define usbInterruptIsReady3() (usbTxLen3 & 0x10) +/* Same as above for endpoint 3 */ +#endif +#endif /* USB_CFG_HAVE_INTRIN_ENDPOINT */ +#if USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH /* simplified interface for backward compatibility */ +#define usbHidReportDescriptor usbDescriptorHidReport +/* should be declared as: PROGMEM char usbHidReportDescriptor[]; */ +/* If you implement an HID device, you need to provide a report descriptor. + * The HID report descriptor syntax is a bit complex. If you understand how + * report descriptors are constructed, we recommend that you use the HID + * Descriptor Tool from usb.org, see http://www.usb.org/developers/hidpage/. + * Otherwise you should probably start with a working example. + */ +#endif /* USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH */ +#if USB_CFG_IMPLEMENT_FN_WRITE +USB_PUBLIC uchar usbFunctionWrite(uchar *data, uchar len); +/* This function is called by the driver to provide a control transfer's + * payload data (control-out). It is called in chunks of up to 8 bytes. The + * total count provided in the current control transfer can be obtained from + * the 'length' property in the setup data. If an error occurred during + * processing, return 0xff (== -1). The driver will answer the entire transfer + * with a STALL token in this case. If you have received the entire payload + * successfully, return 1. If you expect more data, return 0. If you don't + * know whether the host will send more data (you should know, the total is + * provided in the usbFunctionSetup() call!), return 1. + * NOTE: If you return 0xff for STALL, 'usbFunctionWrite()' may still be called + * for the remaining data. You must continue to return 0xff for STALL in these + * calls. + * In order to get usbFunctionWrite() called, define USB_CFG_IMPLEMENT_FN_WRITE + * to 1 in usbconfig.h and return 0xff in usbFunctionSetup().. + */ +#endif /* USB_CFG_IMPLEMENT_FN_WRITE */ +#if USB_CFG_IMPLEMENT_FN_READ +USB_PUBLIC uchar usbFunctionRead(uchar *data, uchar len); +/* This function is called by the driver to ask the application for a control + * transfer's payload data (control-in). It is called in chunks of up to 8 + * bytes each. You should copy the data to the location given by 'data' and + * return the actual number of bytes copied. If you return less than requested, + * the control-in transfer is terminated. If you return 0xff, the driver aborts + * the transfer with a STALL token. + * In order to get usbFunctionRead() called, define USB_CFG_IMPLEMENT_FN_READ + * to 1 in usbconfig.h and return 0xff in usbFunctionSetup().. + */ +#endif /* USB_CFG_IMPLEMENT_FN_READ */ + +extern uchar usbRxToken; /* may be used in usbFunctionWriteOut() below */ +#if USB_CFG_IMPLEMENT_FN_WRITEOUT +USB_PUBLIC void usbFunctionWriteOut(uchar *data, uchar len); +/* This function is called by the driver when data is received on an interrupt- + * or bulk-out endpoint. The endpoint number can be found in the global + * variable usbRxToken. You must define USB_CFG_IMPLEMENT_FN_WRITEOUT to 1 in + * usbconfig.h to get this function called. + */ +#endif /* USB_CFG_IMPLEMENT_FN_WRITEOUT */ +#ifdef USB_CFG_PULLUP_IOPORTNAME +#define usbDeviceConnect() ((USB_PULLUP_DDR |= (1<device, 1=device->host + * t ..... type: 0=standard, 1=class, 2=vendor, 3=reserved + * r ..... recipient: 0=device, 1=interface, 2=endpoint, 3=other + */ + +/* USB setup recipient values */ +#define USBRQ_RCPT_MASK 0x1f +#define USBRQ_RCPT_DEVICE 0 +#define USBRQ_RCPT_INTERFACE 1 +#define USBRQ_RCPT_ENDPOINT 2 + +/* USB request type values */ +#define USBRQ_TYPE_MASK 0x60 +#define USBRQ_TYPE_STANDARD (0<<5) +#define USBRQ_TYPE_CLASS (1<<5) +#define USBRQ_TYPE_VENDOR (2<<5) + +/* USB direction values: */ +#define USBRQ_DIR_MASK 0x80 +#define USBRQ_DIR_HOST_TO_DEVICE (0<<7) +#define USBRQ_DIR_DEVICE_TO_HOST (1<<7) + +/* USB Standard Requests */ +#define USBRQ_GET_STATUS 0 +#define USBRQ_CLEAR_FEATURE 1 +#define USBRQ_SET_FEATURE 3 +#define USBRQ_SET_ADDRESS 5 +#define USBRQ_GET_DESCRIPTOR 6 +#define USBRQ_SET_DESCRIPTOR 7 +#define USBRQ_GET_CONFIGURATION 8 +#define USBRQ_SET_CONFIGURATION 9 +#define USBRQ_GET_INTERFACE 10 +#define USBRQ_SET_INTERFACE 11 +#define USBRQ_SYNCH_FRAME 12 + +/* USB descriptor constants */ +#define USBDESCR_DEVICE 1 +#define USBDESCR_CONFIG 2 +#define USBDESCR_STRING 3 +#define USBDESCR_INTERFACE 4 +#define USBDESCR_ENDPOINT 5 +#define USBDESCR_HID 0x21 +#define USBDESCR_HID_REPORT 0x22 +#define USBDESCR_HID_PHYS 0x23 + +//#define USBATTR_BUSPOWER 0x80 // USB 1.1 does not define this value any more +#define USBATTR_SELFPOWER 0x40 +#define USBATTR_REMOTEWAKE 0x20 + +/* USB HID Requests */ +#define USBRQ_HID_GET_REPORT 0x01 +#define USBRQ_HID_GET_IDLE 0x02 +#define USBRQ_HID_GET_PROTOCOL 0x03 +#define USBRQ_HID_SET_REPORT 0x09 +#define USBRQ_HID_SET_IDLE 0x0a +#define USBRQ_HID_SET_PROTOCOL 0x0b + +/* ------------------------------------------------------------------------- */ + +#endif /* __usbdrv_h_included__ */ diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm.S b/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm.S new file mode 100644 index 0000000..80877e4 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm.S @@ -0,0 +1,385 @@ +/* Name: usbdrvasm.S + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2007-06-13 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm.S 761 2009-08-12 16:30:23Z cs $ + */ + +/* +General Description: +This module is the assembler part of the USB driver. This file contains +general code (preprocessor acrobatics and CRC computation) and then includes +the file appropriate for the given clock rate. +*/ + +#define __SFR_OFFSET 0 /* used by avr-libc's register definitions */ +#include "usbportability.h" +#include "usbdrv.h" /* for common defs */ + +/* register names */ +#define x1 r16 +#define x2 r17 +#define shift r18 +#define cnt r19 +#define x3 r20 +#define x4 r21 +#define x5 r22 +#define bitcnt x5 +#define phase x4 +#define leap x4 + +/* Some assembler dependent definitions and declarations: */ + +#ifdef __IAR_SYSTEMS_ASM__ + extern usbRxBuf, usbDeviceAddr, usbNewDeviceAddr, usbInputBufOffset + extern usbCurrentTok, usbRxLen, usbRxToken, usbTxLen + extern usbTxBuf, usbTxStatus1, usbTxStatus3 +# if USB_COUNT_SOF + extern usbSofCount +# endif + public usbCrc16 + public usbCrc16Append + + COMMON INTVEC +# ifndef USB_INTR_VECTOR + ORG INT0_vect +# else /* USB_INTR_VECTOR */ + ORG USB_INTR_VECTOR +# undef USB_INTR_VECTOR +# endif /* USB_INTR_VECTOR */ +# define USB_INTR_VECTOR usbInterruptHandler + rjmp USB_INTR_VECTOR + RSEG CODE + +#else /* __IAR_SYSTEMS_ASM__ */ + +# ifndef USB_INTR_VECTOR /* default to hardware interrupt INT0 */ +# define USB_INTR_VECTOR SIG_INTERRUPT0 +# endif + .text + .global USB_INTR_VECTOR + .type USB_INTR_VECTOR, @function + .global usbCrc16 + .global usbCrc16Append +#endif /* __IAR_SYSTEMS_ASM__ */ + + +#if USB_INTR_PENDING < 0x40 /* This is an I/O address, use in and out */ +# define USB_LOAD_PENDING(reg) in reg, USB_INTR_PENDING +# define USB_STORE_PENDING(reg) out USB_INTR_PENDING, reg +#else /* It's a memory address, use lds and sts */ +# define USB_LOAD_PENDING(reg) lds reg, USB_INTR_PENDING +# define USB_STORE_PENDING(reg) sts USB_INTR_PENDING, reg +#endif + +#define usbTxLen1 usbTxStatus1 +#define usbTxBuf1 (usbTxStatus1 + 1) +#define usbTxLen3 usbTxStatus3 +#define usbTxBuf3 (usbTxStatus3 + 1) + + +;---------------------------------------------------------------------------- +; Utility functions +;---------------------------------------------------------------------------- + +#ifdef __IAR_SYSTEMS_ASM__ +/* Register assignments for usbCrc16 on IAR cc */ +/* Calling conventions on IAR: + * First parameter passed in r16/r17, second in r18/r19 and so on. + * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer) + * Result is passed in r16/r17 + * In case of the "tiny" memory model, pointers are only 8 bit with no + * padding. We therefore pass argument 1 as "16 bit unsigned". + */ +RTMODEL "__rt_version", "3" +/* The line above will generate an error if cc calling conventions change. + * The value "3" above is valid for IAR 4.10B/W32 + */ +# define argLen r18 /* argument 2 */ +# define argPtrL r16 /* argument 1 */ +# define argPtrH r17 /* argument 1 */ + +# define resCrcL r16 /* result */ +# define resCrcH r17 /* result */ + +# define ptrL ZL +# define ptrH ZH +# define ptr Z +# define byte r22 +# define bitCnt r19 +# define polyL r20 +# define polyH r21 +# define scratch r23 + +#else /* __IAR_SYSTEMS_ASM__ */ +/* Register assignments for usbCrc16 on gcc */ +/* Calling conventions on gcc: + * First parameter passed in r24/r25, second in r22/23 and so on. + * Callee must preserve r1-r17, r28/r29 + * Result is passed in r24/r25 + */ +# define argLen r22 /* argument 2 */ +# define argPtrL r24 /* argument 1 */ +# define argPtrH r25 /* argument 1 */ + +# define resCrcL r24 /* result */ +# define resCrcH r25 /* result */ + +# define ptrL XL +# define ptrH XH +# define ptr x +# define byte r18 +# define bitCnt r19 +# define polyL r20 +# define polyH r21 +# define scratch r23 + +#endif + +#if USB_USE_FAST_CRC + +; This implementation is faster, but has bigger code size +; Thanks to Slawomir Fras (BoskiDialer) for this code! +; It implements the following C pseudo-code: +; unsigned table(unsigned char x) +; { +; unsigned value; +; +; value = (unsigned)x << 6; +; value ^= (unsigned)x << 7; +; if(parity(x)) +; value ^= 0xc001; +; return value; +; } +; unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen) +; { +; unsigned crc = 0xffff; +; +; while(argLen--) +; crc = table(lo8(crc) ^ *argPtr++) ^ hi8(crc); +; return ~crc; +; } + +; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen); +; argPtr r24+25 / r16+r17 +; argLen r22 / r18 +; temp variables: +; byte r18 / r22 +; scratch r23 +; resCrc r24+r25 / r16+r17 +; ptr X / Z +usbCrc16: + mov ptrL, argPtrL + mov ptrH, argPtrH + ldi resCrcL, 0xFF + ldi resCrcH, 0xFF + rjmp usbCrc16LoopTest +usbCrc16ByteLoop: + ld byte, ptr+ + eor resCrcL, byte ; resCrcL is now 'x' in table() + mov byte, resCrcL ; compute parity of 'x' + swap byte + eor byte, resCrcL + mov scratch, byte + lsr byte + lsr byte + eor byte, scratch + inc byte + lsr byte + andi byte, 1 ; byte is now parity(x) + mov scratch, resCrcL + mov resCrcL, resCrcH + eor resCrcL, byte ; low byte of if(parity(x)) value ^= 0xc001; + neg byte + andi byte, 0xc0 + mov resCrcH, byte ; high byte of if(parity(x)) value ^= 0xc001; + clr byte + lsr scratch + ror byte + eor resCrcH, scratch + eor resCrcL, byte + lsr scratch + ror byte + eor resCrcH, scratch + eor resCrcL, byte +usbCrc16LoopTest: + subi argLen, 1 + brsh usbCrc16ByteLoop + com resCrcL + com resCrcH + ret + +#else /* USB_USE_FAST_CRC */ + +; This implementation is slower, but has less code size +; +; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen); +; argPtr r24+25 / r16+r17 +; argLen r22 / r18 +; temp variables: +; byte r18 / r22 +; bitCnt r19 +; poly r20+r21 +; scratch r23 +; resCrc r24+r25 / r16+r17 +; ptr X / Z +usbCrc16: + mov ptrL, argPtrL + mov ptrH, argPtrH + ldi resCrcL, 0 + ldi resCrcH, 0 + ldi polyL, lo8(0xa001) + ldi polyH, hi8(0xa001) + com argLen ; argLen = -argLen - 1: modified loop to ensure that carry is set + ldi bitCnt, 0 ; loop counter with starnd condition = end condition + rjmp usbCrcLoopEntry +usbCrcByteLoop: + ld byte, ptr+ + eor resCrcL, byte +usbCrcBitLoop: + ror resCrcH ; carry is always set here (see brcs jumps to here) + ror resCrcL + brcs usbCrcNoXor + eor resCrcL, polyL + eor resCrcH, polyH +usbCrcNoXor: + subi bitCnt, 224 ; (8 * 224) % 256 = 0; this loop iterates 8 times + brcs usbCrcBitLoop +usbCrcLoopEntry: + subi argLen, -1 + brcs usbCrcByteLoop +usbCrcReady: + ret +; Thanks to Reimar Doeffinger for optimizing this CRC routine! + +#endif /* USB_USE_FAST_CRC */ + +; extern unsigned usbCrc16Append(unsigned char *data, unsigned char len); +usbCrc16Append: + rcall usbCrc16 + st ptr+, resCrcL + st ptr+, resCrcH + ret + +#undef argLen +#undef argPtrL +#undef argPtrH +#undef resCrcL +#undef resCrcH +#undef ptrL +#undef ptrH +#undef ptr +#undef byte +#undef bitCnt +#undef polyL +#undef polyH +#undef scratch + + +#if USB_CFG_HAVE_MEASURE_FRAME_LENGTH +#ifdef __IAR_SYSTEMS_ASM__ +/* Register assignments for usbMeasureFrameLength on IAR cc */ +/* Calling conventions on IAR: + * First parameter passed in r16/r17, second in r18/r19 and so on. + * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer) + * Result is passed in r16/r17 + * In case of the "tiny" memory model, pointers are only 8 bit with no + * padding. We therefore pass argument 1 as "16 bit unsigned". + */ +# define resL r16 +# define resH r17 +# define cnt16L r30 +# define cnt16H r31 +# define cntH r18 + +#else /* __IAR_SYSTEMS_ASM__ */ +/* Register assignments for usbMeasureFrameLength on gcc */ +/* Calling conventions on gcc: + * First parameter passed in r24/r25, second in r22/23 and so on. + * Callee must preserve r1-r17, r28/r29 + * Result is passed in r24/r25 + */ +# define resL r24 +# define resH r25 +# define cnt16L r24 +# define cnt16H r25 +# define cntH r26 +#endif +# define cnt16 cnt16L + +; extern unsigned usbMeasurePacketLength(void); +; returns time between two idle strobes in multiples of 7 CPU clocks +.global usbMeasureFrameLength +usbMeasureFrameLength: + ldi cntH, 6 ; wait ~ 10 ms for D- == 0 + clr cnt16L + clr cnt16H +usbMFTime16: + dec cntH + breq usbMFTimeout +usbMFWaitStrobe: ; first wait for D- == 0 (idle strobe) + sbiw cnt16, 1 ;[0] [6] + breq usbMFTime16 ;[2] + sbic USBIN, USBMINUS ;[3] + rjmp usbMFWaitStrobe ;[4] +usbMFWaitIdle: ; then wait until idle again + sbis USBIN, USBMINUS ;1 wait for D- == 1 + rjmp usbMFWaitIdle ;2 + ldi cnt16L, 1 ;1 represents cycles so far + clr cnt16H ;1 +usbMFWaitLoop: + in cntH, USBIN ;[0] [7] + adiw cnt16, 1 ;[1] + breq usbMFTimeout ;[3] + andi cntH, USBMASK ;[4] + brne usbMFWaitLoop ;[5] +usbMFTimeout: +#if resL != cnt16L + mov resL, cnt16L + mov resH, cnt16H +#endif + ret + +#undef resL +#undef resH +#undef cnt16 +#undef cnt16L +#undef cnt16H +#undef cntH + +#endif /* USB_CFG_HAVE_MEASURE_FRAME_LENGTH */ + +;---------------------------------------------------------------------------- +; Now include the clock rate specific code +;---------------------------------------------------------------------------- + +#ifndef USB_CFG_CLOCK_KHZ +# define USB_CFG_CLOCK_KHZ 12000 +#endif + +#if USB_CFG_CHECK_CRC /* separate dispatcher for CRC type modules */ +# if USB_CFG_CLOCK_KHZ == 18000 +# include "usbdrvasm18-crc.inc" +# else +# error "USB_CFG_CLOCK_KHZ is not one of the supported crc-rates!" +# endif +#else /* USB_CFG_CHECK_CRC */ +# if USB_CFG_CLOCK_KHZ == 12000 +# include "usbdrvasm12.inc" +# elif USB_CFG_CLOCK_KHZ == 12800 +# include "usbdrvasm128.inc" +# elif USB_CFG_CLOCK_KHZ == 15000 +# include "usbdrvasm15.inc" +# elif USB_CFG_CLOCK_KHZ == 16000 +# include "usbdrvasm16.inc" +# elif USB_CFG_CLOCK_KHZ == 16500 +# include "usbdrvasm165.inc" +# elif USB_CFG_CLOCK_KHZ == 20000 +# include "usbdrvasm20.inc" +# else +# error "USB_CFG_CLOCK_KHZ is not one of the supported non-crc-rates!" +# endif +#endif /* USB_CFG_CHECK_CRC */ diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm.asm b/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm.asm new file mode 100644 index 0000000..9cc4e4d --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm.asm @@ -0,0 +1,21 @@ +/* Name: usbdrvasm.asm + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2006-03-01 + * Tabsize: 4 + * Copyright: (c) 2006 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id$ + */ + +/* +General Description: +The IAR compiler/assembler system prefers assembler files with file extension +".asm". We simply provide this file as an alias for usbdrvasm.S. + +Thanks to Oleg Semyonov for his help with the IAR tools port! +*/ + +#include "usbdrvasm.S" + +end diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm12.inc b/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm12.inc new file mode 100644 index 0000000..c116758 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm12.inc @@ -0,0 +1,393 @@ +/* Name: usbdrvasm12.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2004-12-29 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbdrvasm12.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 12 MHz version of the asssembler part of the USB driver. It +requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! + + +Timing constraints according to spec (in bit times): +timing subject min max CPUcycles +--------------------------------------------------------------------------- +EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128 +EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60 +DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60 +*/ + +;Software-receiver engine. Strict timing! Don't change unless you can preserve timing! +;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled +;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable +;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes +;Numbers in brackets are maximum cycles since SOF. +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt + push YL ;2 [35] push only what is necessary to sync with edge ASAP + in YL, SREG ;1 [37] + push YL ;2 [39] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of 1/4 bit which meets the spec. + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push YH ;2 [2] + lds YL, usbInputBufOffset;2 [4] + clr YH ;1 [5] + subi YL, lo8(-(usbRxBuf));1 [6] + sbci YH, hi8(-(usbRxBuf));1 [7] + + sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early] + rjmp haveTwoBitsK ;2 [10] + pop YH ;2 [11] undo the push from before + rjmp waitForK ;2 [13] this was not the end of sync, retry +haveTwoBitsK: +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- + push shift ;2 [16] + push x1 ;2 [12] + push x2 ;2 [14] + + in x1, USBIN ;1 [17] <-- sample bit 0 + ldi shift, 0xff ;1 [18] + bst x1, USBMINUS ;1 [19] + bld shift, 0 ;1 [20] + push x3 ;2 [22] + push cnt ;2 [24] + + in x2, USBIN ;1 [25] <-- sample bit 1 + ser x3 ;1 [26] [inserted init instruction] + eor x1, x2 ;1 [27] + bst x1, USBMINUS ;1 [28] + bld shift, 1 ;1 [29] + ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction] + rjmp rxbit2 ;2 [32] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- + +unstuff0: ;1 (branch taken) + andi x3, ~0x01 ;1 [15] + mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit + in x2, USBIN ;1 [17] <-- sample bit 1 again + ori shift, 0x01 ;1 [18] + rjmp didUnstuff0 ;2 [20] + +unstuff1: ;1 (branch taken) + mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit + andi x3, ~0x02 ;1 [22] + ori shift, 0x02 ;1 [23] + nop ;1 [24] + in x1, USBIN ;1 [25] <-- sample bit 2 again + rjmp didUnstuff1 ;2 [27] + +unstuff2: ;1 (branch taken) + andi x3, ~0x04 ;1 [29] + ori shift, 0x04 ;1 [30] + mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit + nop ;1 [32] + in x2, USBIN ;1 [33] <-- sample bit 3 + rjmp didUnstuff2 ;2 [35] + +unstuff3: ;1 (branch taken) + in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late] + andi x3, ~0x08 ;1 [35] + ori shift, 0x08 ;1 [36] + rjmp didUnstuff3 ;2 [38] + +unstuff4: ;1 (branch taken) + andi x3, ~0x10 ;1 [40] + in x1, USBIN ;1 [41] <-- sample stuffed bit 4 + ori shift, 0x10 ;1 [42] + rjmp didUnstuff4 ;2 [44] + +unstuff5: ;1 (branch taken) + andi x3, ~0x20 ;1 [48] + in x2, USBIN ;1 [49] <-- sample stuffed bit 5 + ori shift, 0x20 ;1 [50] + rjmp didUnstuff5 ;2 [52] + +unstuff6: ;1 (branch taken) + andi x3, ~0x40 ;1 [56] + in x1, USBIN ;1 [57] <-- sample stuffed bit 6 + ori shift, 0x40 ;1 [58] + rjmp didUnstuff6 ;2 [60] + +; extra jobs done during bit interval: +; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs] +; bit 1: se0 check +; bit 2: overflow check +; bit 3: recovery from delay [bit 0 tasks took too long] +; bit 4: none +; bit 5: none +; bit 6: none +; bit 7: jump, eor +rxLoop: + eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others + in x1, USBIN ;1 [1] <-- sample bit 0 + st y+, x3 ;2 [3] store data + ser x3 ;1 [4] + nop ;1 [5] + eor x2, x1 ;1 [6] + bst x2, USBMINUS;1 [7] + bld shift, 0 ;1 [8] + in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed) + andi x2, USBMASK ;1 [10] + breq se0 ;1 [11] SE0 check for bit 1 + andi shift, 0xf9 ;1 [12] +didUnstuff0: + breq unstuff0 ;1 [13] + eor x1, x2 ;1 [14] + bst x1, USBMINUS;1 [15] + bld shift, 1 ;1 [16] +rxbit2: + in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed) + andi shift, 0xf3 ;1 [18] + breq unstuff1 ;1 [19] do remaining work for bit 1 +didUnstuff1: + subi cnt, 1 ;1 [20] + brcs overflow ;1 [21] loop control + eor x2, x1 ;1 [22] + bst x2, USBMINUS;1 [23] + bld shift, 2 ;1 [24] + in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed) + andi shift, 0xe7 ;1 [26] + breq unstuff2 ;1 [27] +didUnstuff2: + eor x1, x2 ;1 [28] + bst x1, USBMINUS;1 [29] + bld shift, 3 ;1 [30] +didUnstuff3: + andi shift, 0xcf ;1 [31] + breq unstuff3 ;1 [32] + in x1, USBIN ;1 [33] <-- sample bit 4 + eor x2, x1 ;1 [34] + bst x2, USBMINUS;1 [35] + bld shift, 4 ;1 [36] +didUnstuff4: + andi shift, 0x9f ;1 [37] + breq unstuff4 ;1 [38] + nop2 ;2 [40] + in x2, USBIN ;1 [41] <-- sample bit 5 + eor x1, x2 ;1 [42] + bst x1, USBMINUS;1 [43] + bld shift, 5 ;1 [44] +didUnstuff5: + andi shift, 0x3f ;1 [45] + breq unstuff5 ;1 [46] + nop2 ;2 [48] + in x1, USBIN ;1 [49] <-- sample bit 6 + eor x2, x1 ;1 [50] + bst x2, USBMINUS;1 [51] + bld shift, 6 ;1 [52] +didUnstuff6: + cpi shift, 0x02 ;1 [53] + brlo unstuff6 ;1 [54] + nop2 ;2 [56] + in x2, USBIN ;1 [57] <-- sample bit 7 + eor x1, x2 ;1 [58] + bst x1, USBMINUS;1 [59] + bld shift, 7 ;1 [60] +didUnstuff7: + cpi shift, 0x04 ;1 [61] + brsh rxLoop ;2 [63] loop control +unstuff7: + andi x3, ~0x80 ;1 [63] + ori shift, 0x80 ;1 [64] + in x2, USBIN ;1 [65] <-- sample stuffed bit 7 + nop ;1 [66] + rjmp didUnstuff7 ;2 [68] + +macro POP_STANDARD ; 12 cycles + pop cnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;---------------------------------------------------------------------------- +; Transmitting data +;---------------------------------------------------------------------------- + +txByteLoop: +txBitloop: +stuffN1Delay: ; [03] + ror shift ;[-5] [11] [59] + brcc doExorN1 ;[-4] [60] + subi x4, 1 ;[-3] + brne commonN1 ;[-2] + lsl shift ;[-1] compensate ror after rjmp stuffDelay + nop ;[00] stuffing consists of just waiting 8 cycles + rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear + +sendNakAndReti: ;0 [-19] 19 cycles until SOP + ldi x3, USBPID_NAK ;1 [-18] + rjmp usbSendX3 ;2 [-16] +sendAckAndReti: ;0 [-19] 19 cycles until SOP + ldi x3, USBPID_ACK ;1 [-18] + rjmp usbSendX3 ;2 [-16] +sendCntAndReti: ;0 [-17] 17 cycles until SOP + mov x3, cnt ;1 [-16] +usbSendX3: ;0 [-16] + ldi YL, 20 ;1 [-15] 'x3' is R20 + ldi YH, 0 ;1 [-14] + ldi cnt, 2 ;1 [-13] +; rjmp usbSendAndReti fallthrough + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) or USBOUT = 0x01 +; K = (D+ = 1), (D- = 0) or USBOUT = 0x02 +; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles) + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte +;uses: x1...x2, x4, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x4 = bitstuff cnt] +;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction) +usbSendAndReti: + in x2, USBDDR ;[-12] 12 cycles until SOP + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS ;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + out USBDDR, x2 ;[-8] <--- acquire bus + in x1, USBOUT ;[-7] port mirror for tx loop + ldi shift, 0x40 ;[-6] sync byte is first byte sent (we enter loop after ror) + ldi x2, USBMASK ;[-5] + push x4 ;[-4] +doExorN1: + eor x1, x2 ;[-2] [06] [62] + ldi x4, 6 ;[-1] [07] [63] +commonN1: +stuffN2Delay: + out USBOUT, x1 ;[00] [08] [64] <--- set bit + ror shift ;[01] + brcc doExorN2 ;[02] + subi x4, 1 ;[03] + brne commonN2 ;[04] + lsl shift ;[05] compensate ror after rjmp stuffDelay + rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear +doExorN2: + eor x1, x2 ;[04] [12] + ldi x4, 6 ;[05] [13] +commonN2: + nop ;[06] [14] + subi cnt, 171 ;[07] [15] trick: (3 * 171) & 0xff = 1 + out USBOUT, x1 ;[08] [16] <--- set bit + brcs txBitloop ;[09] [25] [41] + +stuff6Delay: + ror shift ;[42] [50] + brcc doExor6 ;[43] + subi x4, 1 ;[44] + brne common6 ;[45] + lsl shift ;[46] compensate ror after rjmp stuffDelay + nop ;[47] stuffing consists of just waiting 8 cycles + rjmp stuff6Delay ;[48] after ror, C bit is reliably clear +doExor6: + eor x1, x2 ;[45] [53] + ldi x4, 6 ;[46] +common6: +stuff7Delay: + ror shift ;[47] [55] + out USBOUT, x1 ;[48] <--- set bit + brcc doExor7 ;[49] + subi x4, 1 ;[50] + brne common7 ;[51] + lsl shift ;[52] compensate ror after rjmp stuffDelay + rjmp stuff7Delay ;[53] after ror, C bit is reliably clear +doExor7: + eor x1, x2 ;[51] [59] + ldi x4, 6 ;[52] +common7: + ld shift, y+ ;[53] + tst cnt ;[55] + out USBOUT, x1 ;[56] <--- set bit + brne txByteLoop ;[57] + +;make SE0: + cbr x1, USBMASK ;[58] prepare SE0 [spec says EOP may be 15 to 18 cycles] + lds x2, usbNewDeviceAddr;[59] + lsl x2 ;[61] we compare with left shifted address + subi YL, 2 + 20 ;[62] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[63] + out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[01] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 12.5625 MHz +max frequency: 69.286 cycles for 8 bit -> 12.99 MHz +nominal frequency: 12.77 MHz ( = sqrt(min * max)) + +sampling positions: (next even number in range [+/- 0.5]) +cycle index range: 0 ... 66 +bits: +.5, 8.875, 17.25, 25.625, 34, 42.375, 50.75, 59.125 +[0/1], [9], [17], [25/+26], [34], [+42/43], [51], [59] + +bit number: 0 1 2 3 4 5 6 7 +spare cycles 1 2 1 2 1 1 1 0 + +operations to perform: duration cycle + ---------------- + eor fix, shift 1 -> 00 + andi phase, USBMASK 1 -> 08 + breq se0 1 -> 16 (moved to 11) + st y+, data 2 -> 24, 25 + mov data, fix 1 -> 33 + ser data 1 -> 41 + subi cnt, 1 1 -> 49 + brcs overflow 1 -> 50 + +layout of samples and operations: +[##] = sample bit +<##> = sample phase +*##* = operation + +0: *00* [01] 02 03 04 <05> 06 07 +1: *08* [09] 10 11 12 <13> 14 15 *16* +2: [17] 18 19 20 <21> 22 23 +3: *24* *25* [26] 27 28 29 <30> 31 32 +4: *33* [34] 35 36 37 <38> 39 40 +5: *41* [42] 43 44 45 <46> 47 48 +6: *49* *50* [51] 52 53 54 <55> 56 57 58 +7: [59] 60 61 62 <63> 64 65 66 +*****************************************************************************/ + +/* we prefer positive expressions (do if condition) instead of negative + * (skip if condition), therefore use defines for skip instructions: + */ +#define ifioclr sbis +#define ifioset sbic +#define ifrclr sbrs +#define ifrset sbrc + +/* The registers "fix" and "data" swap their meaning during the loop. Use + * defines to keep their name constant. + */ +#define fix x2 +#define data x1 +#undef phase /* phase has a default definition to x4 */ +#define phase x3 + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt, r0 + push YL ;2 push only what is necessary to sync with edge ASAP + in YL, SREG ;1 + push YL ;2 +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of 1/4 bit which meets the spec. + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS ;[0] + rjmp foundK ;[1] +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError + +foundK: +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push YH ;[2] + lds YL, usbInputBufOffset;[4] + clr YH ;[6] + subi YL, lo8(-(usbRxBuf));[7] + sbci YH, hi8(-(usbRxBuf));[8] + + sbis USBIN, USBMINUS ;[9] we want two bits K [we want to sample at 8 + 4 - 1.5 = 10.5] + rjmp haveTwoBitsK ;[10] + pop YH ;[11] undo the push from before + rjmp waitForK ;[13] this was not the end of sync, retry +haveTwoBitsK: +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +#define fix x2 +#define data x1 + + push shift ;[12] + push x1 ;[14] + push x2 ;[16] + ldi shift, 0x80 ;[18] prevent bit-unstuffing but init low bits to 0 + ifioset USBIN, USBMINUS ;[19] [01] <--- bit 0 [10.5 + 8 = 18.5] + ori shift, 1<<0 ;[02] + push x3 ;[03] + push cnt ;[05] + push r0 ;[07] + ifioset USBIN, USBMINUS ;[09] <--- bit 1 + ori shift, 1<<1 ;[10] + ser fix ;[11] + ldi cnt, USB_BUFSIZE ;[12] + mov data, shift ;[13] + lsl shift ;[14] + nop2 ;[15] + ifioset USBIN, USBMINUS ;[17] <--- bit 2 + ori data, 3<<2 ;[18] store in bit 2 AND bit 3 + eor shift, data ;[19] do nrzi decoding + andi data, 1<<3 ;[20] + in phase, USBIN ;[21] <- phase + brne jumpToEntryAfterSet ;[22] if USBMINS at bit 3 was 1 + nop ;[23] + rjmp entryAfterClr ;[24] +jumpToEntryAfterSet: + rjmp entryAfterSet ;[24] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +#undef fix +#define fix x1 +#undef data +#define data x2 + +bit7IsSet: + ifrclr phase, USBMINUS ;[62] check phase only if D- changed + lpm ;[63] + in phase, USBIN ;[64] <- phase (one cycle too late) + ori shift, 1 << 7 ;[65] + nop ;[66] +;;;;rjmp bit0AfterSet ; -> [00] == [67] moved block up to save jump +bit0AfterSet: + eor fix, shift ;[00] +#undef fix +#define fix x2 +#undef data +#define data x1 /* we now have result in data, fix is reset to 0xff */ + ifioclr USBIN, USBMINUS ;[01] <--- sample 0 + rjmp bit0IsClr ;[02] + andi shift, ~(7 << 0) ;[03] + breq unstuff0s ;[04] + in phase, USBIN ;[05] <- phase + rjmp bit1AfterSet ;[06] +unstuff0s: + in phase, USBIN ;[06] <- phase (one cycle too late) + andi fix, ~(1 << 0) ;[07] + ifioclr USBIN, USBMINUS ;[00] + ifioset USBIN, USBPLUS ;[01] + rjmp bit0IsClr ;[02] executed if first expr false or second true +se0AndStore: ; executed only if both bits 0 + st y+, x1 ;[15/17] cycles after start of byte + rjmp se0 ;[17/19] + +bit0IsClr: + ifrset phase, USBMINUS ;[04] check phase only if D- changed + lpm ;[05] + in phase, USBIN ;[06] <- phase (one cycle too late) + ori shift, 1 << 0 ;[07] +bit1AfterClr: + andi phase, USBMASK ;[08] + ifioset USBIN, USBMINUS ;[09] <--- sample 1 + rjmp bit1IsSet ;[10] + breq se0AndStore ;[11] if D- was 0 in bits 0 AND 1 and D+ was 0 in between, we have SE0 + andi shift, ~(7 << 1) ;[12] + in phase, USBIN ;[13] <- phase + breq unstuff1c ;[14] + rjmp bit2AfterClr ;[15] +unstuff1c: + andi fix, ~(1 << 1) ;[16] + nop2 ;[08] + nop2 ;[10] +bit1IsSet: + ifrclr phase, USBMINUS ;[12] check phase only if D- changed + lpm ;[13] + in phase, USBIN ;[14] <- phase (one cycle too late) + ori shift, 1 << 1 ;[15] + nop ;[16] +bit2AfterSet: + ifioclr USBIN, USBMINUS ;[17] <--- sample 2 + rjmp bit2IsClr ;[18] + andi shift, ~(7 << 2) ;[19] + breq unstuff2s ;[20] + in phase, USBIN ;[21] <- phase + rjmp bit3AfterSet ;[22] +unstuff2s: + in phase, USBIN ;[22] <- phase (one cycle too late) + andi fix, ~(1 << 2) ;[23] + nop2 ;[16] + nop2 ;[18] +bit2IsClr: + ifrset phase, USBMINUS ;[20] check phase only if D- changed + lpm ;[21] + in phase, USBIN ;[22] <- phase (one cycle too late) + ori shift, 1 << 2 ;[23] +bit3AfterClr: + st y+, data ;[24] +entryAfterClr: + ifioset USBIN, USBMINUS ;[26] <--- sample 3 + rjmp bit3IsSet ;[27] + andi shift, ~(7 << 3) ;[28] + breq unstuff3c ;[29] + in phase, USBIN ;[30] <- phase + rjmp bit4AfterClr ;[31] +unstuff3c: + in phase, USBIN ;[31] <- phase (one cycle too late) + andi fix, ~(1 << 3) ;[32] + nop2 ;[25] + nop2 ;[27] +bit3IsSet: + ifrclr phase, USBMINUS ;[29] check phase only if D- changed + lpm ;[30] + in phase, USBIN ;[31] <- phase (one cycle too late) + ori shift, 1 << 3 ;[32] +bit4AfterSet: + mov data, fix ;[33] undo this move by swapping defines +#undef fix +#define fix x1 +#undef data +#define data x2 + ifioclr USBIN, USBMINUS ;[34] <--- sample 4 + rjmp bit4IsClr ;[35] + andi shift, ~(7 << 4) ;[36] + breq unstuff4s ;[37] + in phase, USBIN ;[38] <- phase + rjmp bit5AfterSet ;[39] +unstuff4s: + in phase, USBIN ;[39] <- phase (one cycle too late) + andi fix, ~(1 << 4) ;[40] + nop2 ;[33] + nop2 ;[35] +bit4IsClr: + ifrset phase, USBMINUS ;[37] check phase only if D- changed + lpm ;[38] + in phase, USBIN ;[39] <- phase (one cycle too late) + ori shift, 1 << 4 ;[40] +bit5AfterClr: + ser data ;[41] + ifioset USBIN, USBMINUS ;[42] <--- sample 5 + rjmp bit5IsSet ;[43] + andi shift, ~(7 << 5) ;[44] + breq unstuff5c ;[45] + in phase, USBIN ;[46] <- phase + rjmp bit6AfterClr ;[47] +unstuff5c: + in phase, USBIN ;[47] <- phase (one cycle too late) + andi fix, ~(1 << 5) ;[48] + nop2 ;[41] + nop2 ;[43] +bit5IsSet: + ifrclr phase, USBMINUS ;[45] check phase only if D- changed + lpm ;[46] + in phase, USBIN ;[47] <- phase (one cycle too late) + ori shift, 1 << 5 ;[48] +bit6AfterSet: + subi cnt, 1 ;[49] + brcs jumpToOverflow ;[50] + ifioclr USBIN, USBMINUS ;[51] <--- sample 6 + rjmp bit6IsClr ;[52] + andi shift, ~(3 << 6) ;[53] + cpi shift, 2 ;[54] + in phase, USBIN ;[55] <- phase + brlt unstuff6s ;[56] + rjmp bit7AfterSet ;[57] + +jumpToOverflow: + rjmp overflow + +unstuff6s: + andi fix, ~(1 << 6) ;[50] + lpm ;[51] +bit6IsClr: + ifrset phase, USBMINUS ;[54] check phase only if D- changed + lpm ;[55] + in phase, USBIN ;[56] <- phase (one cycle too late) + ori shift, 1 << 6 ;[57] + nop ;[58] +bit7AfterClr: + ifioset USBIN, USBMINUS ;[59] <--- sample 7 + rjmp bit7IsSet ;[60] + andi shift, ~(1 << 7) ;[61] + cpi shift, 4 ;[62] + in phase, USBIN ;[63] <- phase + brlt unstuff7c ;[64] + rjmp bit0AfterClr ;[65] -> [00] == [67] +unstuff7c: + andi fix, ~(1 << 7) ;[58] + nop ;[59] + rjmp bit7IsSet ;[60] + +bit7IsClr: + ifrset phase, USBMINUS ;[62] check phase only if D- changed + lpm ;[63] + in phase, USBIN ;[64] <- phase (one cycle too late) + ori shift, 1 << 7 ;[65] + nop ;[66] +;;;;rjmp bit0AfterClr ; -> [00] == [67] moved block up to save jump +bit0AfterClr: + eor fix, shift ;[00] +#undef fix +#define fix x2 +#undef data +#define data x1 /* we now have result in data, fix is reset to 0xff */ + ifioset USBIN, USBMINUS ;[01] <--- sample 0 + rjmp bit0IsSet ;[02] + andi shift, ~(7 << 0) ;[03] + breq unstuff0c ;[04] + in phase, USBIN ;[05] <- phase + rjmp bit1AfterClr ;[06] +unstuff0c: + in phase, USBIN ;[06] <- phase (one cycle too late) + andi fix, ~(1 << 0) ;[07] + ifioclr USBIN, USBMINUS ;[00] + ifioset USBIN, USBPLUS ;[01] + rjmp bit0IsSet ;[02] executed if first expr false or second true + rjmp se0AndStore ;[03] executed only if both bits 0 +bit0IsSet: + ifrclr phase, USBMINUS ;[04] check phase only if D- changed + lpm ;[05] + in phase, USBIN ;[06] <- phase (one cycle too late) + ori shift, 1 << 0 ;[07] +bit1AfterSet: + andi shift, ~(7 << 1) ;[08] compensated by "ori shift, 1<<1" if bit1IsClr + ifioclr USBIN, USBMINUS ;[09] <--- sample 1 + rjmp bit1IsClr ;[10] + breq unstuff1s ;[11] + nop2 ;[12] do not check for SE0 if bit 0 was 1 + in phase, USBIN ;[14] <- phase (one cycle too late) + rjmp bit2AfterSet ;[15] +unstuff1s: + in phase, USBIN ;[13] <- phase + andi fix, ~(1 << 1) ;[14] + lpm ;[07] + nop2 ;[10] +bit1IsClr: + ifrset phase, USBMINUS ;[12] check phase only if D- changed + lpm ;[13] + in phase, USBIN ;[14] <- phase (one cycle too late) + ori shift, 1 << 1 ;[15] + nop ;[16] +bit2AfterClr: + ifioset USBIN, USBMINUS ;[17] <--- sample 2 + rjmp bit2IsSet ;[18] + andi shift, ~(7 << 2) ;[19] + breq unstuff2c ;[20] + in phase, USBIN ;[21] <- phase + rjmp bit3AfterClr ;[22] +unstuff2c: + in phase, USBIN ;[22] <- phase (one cycle too late) + andi fix, ~(1 << 2) ;[23] + nop2 ;[16] + nop2 ;[18] +bit2IsSet: + ifrclr phase, USBMINUS ;[20] check phase only if D- changed + lpm ;[21] + in phase, USBIN ;[22] <- phase (one cycle too late) + ori shift, 1 << 2 ;[23] +bit3AfterSet: + st y+, data ;[24] +entryAfterSet: + ifioclr USBIN, USBMINUS ;[26] <--- sample 3 + rjmp bit3IsClr ;[27] + andi shift, ~(7 << 3) ;[28] + breq unstuff3s ;[29] + in phase, USBIN ;[30] <- phase + rjmp bit4AfterSet ;[31] +unstuff3s: + in phase, USBIN ;[31] <- phase (one cycle too late) + andi fix, ~(1 << 3) ;[32] + nop2 ;[25] + nop2 ;[27] +bit3IsClr: + ifrset phase, USBMINUS ;[29] check phase only if D- changed + lpm ;[30] + in phase, USBIN ;[31] <- phase (one cycle too late) + ori shift, 1 << 3 ;[32] +bit4AfterClr: + mov data, fix ;[33] undo this move by swapping defines +#undef fix +#define fix x1 +#undef data +#define data x2 + ifioset USBIN, USBMINUS ;[34] <--- sample 4 + rjmp bit4IsSet ;[35] + andi shift, ~(7 << 4) ;[36] + breq unstuff4c ;[37] + in phase, USBIN ;[38] <- phase + rjmp bit5AfterClr ;[39] +unstuff4c: + in phase, USBIN ;[39] <- phase (one cycle too late) + andi fix, ~(1 << 4) ;[40] + nop2 ;[33] + nop2 ;[35] +bit4IsSet: + ifrclr phase, USBMINUS ;[37] check phase only if D- changed + lpm ;[38] + in phase, USBIN ;[39] <- phase (one cycle too late) + ori shift, 1 << 4 ;[40] +bit5AfterSet: + ser data ;[41] + ifioclr USBIN, USBMINUS ;[42] <--- sample 5 + rjmp bit5IsClr ;[43] + andi shift, ~(7 << 5) ;[44] + breq unstuff5s ;[45] + in phase, USBIN ;[46] <- phase + rjmp bit6AfterSet ;[47] +unstuff5s: + in phase, USBIN ;[47] <- phase (one cycle too late) + andi fix, ~(1 << 5) ;[48] + nop2 ;[41] + nop2 ;[43] +bit5IsClr: + ifrset phase, USBMINUS ;[45] check phase only if D- changed + lpm ;[46] + in phase, USBIN ;[47] <- phase (one cycle too late) + ori shift, 1 << 5 ;[48] +bit6AfterClr: + subi cnt, 1 ;[49] + brcs overflow ;[50] + ifioset USBIN, USBMINUS ;[51] <--- sample 6 + rjmp bit6IsSet ;[52] + andi shift, ~(3 << 6) ;[53] + cpi shift, 2 ;[54] + in phase, USBIN ;[55] <- phase + brlt unstuff6c ;[56] + rjmp bit7AfterClr ;[57] +unstuff6c: + andi fix, ~(1 << 6) ;[50] + lpm ;[51] +bit6IsSet: + ifrclr phase, USBMINUS ;[54] check phase only if D- changed + lpm ;[55] + in phase, USBIN ;[56] <- phase (one cycle too late) + ori shift, 1 << 6 ;[57] +bit7AfterSet: + ifioclr USBIN, USBMINUS ;[59] <--- sample 7 + rjmp bit7IsClr ;[60] + andi shift, ~(1 << 7) ;[61] + cpi shift, 4 ;[62] + in phase, USBIN ;[63] <- phase + brlt unstuff7s ;[64] + rjmp bit0AfterSet ;[65] -> [00] == [67] +unstuff7s: + andi fix, ~(1 << 7) ;[58] + nop ;[59] + rjmp bit7IsClr ;[60] + +macro POP_STANDARD ; 14 cycles + pop r0 + pop cnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;---------------------------------------------------------------------------- +; Transmitting data +;---------------------------------------------------------------------------- + +txByteLoop: +txBitloop: +stuffN1Delay: ; [03] + ror shift ;[-5] [11] [63] + brcc doExorN1 ;[-4] [64] + subi x3, 1 ;[-3] + brne commonN1 ;[-2] + lsl shift ;[-1] compensate ror after rjmp stuffDelay + nop ;[00] stuffing consists of just waiting 8 cycles + rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear + +sendNakAndReti: + ldi cnt, USBPID_NAK ;[-19] + rjmp sendCntAndReti ;[-18] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov r0, cnt ;[-16] + ldi YL, 0 ;[-15] R0 address is 0 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) or USBOUT = 0x01 +; K = (D+ = 1), (D- = 0) or USBOUT = 0x02 +; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles) + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte +;uses: x1...x3, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x3 = bitstuff cnt] +;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction) +usbSendAndReti: + in x2, USBDDR ;[-10] 10 cycles until SOP + ori x2, USBMASK ;[-9] + sbi USBOUT, USBMINUS ;[-8] prepare idle state; D+ and D- must have been 0 (no pullups) + out USBDDR, x2 ;[-6] <--- acquire bus + in x1, USBOUT ;[-5] port mirror for tx loop + ldi shift, 0x40 ;[-4] sync byte is first byte sent (we enter loop after ror) + ldi x2, USBMASK ;[-3] +doExorN1: + eor x1, x2 ;[-2] [06] [62] + ldi x3, 6 ;[-1] [07] [63] +commonN1: +stuffN2Delay: + out USBOUT, x1 ;[00] [08] [64] <--- set bit + ror shift ;[01] + brcc doExorN2 ;[02] + subi x3, 1 ;[03] + brne commonN2 ;[04] + lsl shift ;[05] compensate ror after rjmp stuffDelay + rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear +doExorN2: + eor x1, x2 ;[04] [12] + ldi x3, 6 ;[05] [13] +commonN2: + nop2 ;[06] [14] + subi cnt, 171 ;[08] [16] trick: (3 * 171) & 0xff = 1 + out USBOUT, x1 ;[09] [17] <--- set bit + brcs txBitloop ;[10] [27] [44] + +stuff6Delay: + ror shift ;[45] [53] + brcc doExor6 ;[46] + subi x3, 1 ;[47] + brne common6 ;[48] + lsl shift ;[49] compensate ror after rjmp stuffDelay + nop ;[50] stuffing consists of just waiting 8 cycles + rjmp stuff6Delay ;[51] after ror, C bit is reliably clear +doExor6: + eor x1, x2 ;[48] [56] + ldi x3, 6 ;[49] +common6: +stuff7Delay: + ror shift ;[50] [58] + out USBOUT, x1 ;[51] <--- set bit + brcc doExor7 ;[52] + subi x3, 1 ;[53] + brne common7 ;[54] + lsl shift ;[55] compensate ror after rjmp stuffDelay + rjmp stuff7Delay ;[56] after ror, C bit is reliably clear +doExor7: + eor x1, x2 ;[54] [62] + ldi x3, 6 ;[55] +common7: + ld shift, y+ ;[56] + nop ;[58] + tst cnt ;[59] + out USBOUT, x1 ;[60] [00]<--- set bit + brne txByteLoop ;[61] [01] +;make SE0: + cbr x1, USBMASK ;[02] prepare SE0 [spec says EOP may be 15 to 18 cycles] + lds x2, usbNewDeviceAddr;[03] + lsl x2 ;[05] we compare with left shifted address + subi YL, 2 + 0 ;[06] Only assign address on data packets, not ACK/NAK in r0 + sbci YH, 0 ;[07] + out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[01] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 0) + echo "$s\n"; + } +} + +function printBit($isAfterSet, $bitNum) +{ + ob_start(); + if($isAfterSet){ +?> + ifioclr USBIN, USBMINUS ;[00] <--- sample + rjmp bit#IsClr ;[01] + andi shift, ~(7 << #) ;[02] + breq unstuff#s ;[03] + in phase, USBIN ;[04] <- phase + rjmp bit@AfterSet ;[05] +unstuff#s: + in phase, USBIN ;[05] <- phase (one cycle too late) + andi fix, ~(1 << #) ;[06] + nop2 ;[-1] + nop2 ;[01] +bit#IsClr: + ifrset phase, USBMINUS ;[03] check phase only if D- changed + lpm ;[04] + in phase, USBIN ;[05] <- phase (one cycle too late) + ori shift, 1 << # ;[06] + + ifioset USBIN, USBMINUS ;[00] <--- sample + rjmp bit#IsSet ;[01] + andi shift, ~(7 << #) ;[02] + breq unstuff#c ;[03] + in phase, USBIN ;[04] <- phase + rjmp bit@AfterClr ;[05] +unstuff#c: + in phase, USBIN ;[05] <- phase (one cycle too late) + andi fix, ~(1 << #) ;[06] + nop2 ;[-1] + nop2 ;[01] +bit#IsSet: + ifrclr phase, USBMINUS ;[03] check phase only if D- changed + lpm ;[04] + in phase, USBIN ;[05] <- phase (one cycle too late) + ori shift, 1 << # ;[06] + +*****************************************************************************/ diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm15.inc b/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm15.inc new file mode 100644 index 0000000..401b7f8 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm15.inc @@ -0,0 +1,423 @@ +/* Name: usbdrvasm15.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: contributed by V. Bosch + * Creation Date: 2007-08-06 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm15.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 15 MHz version of the asssembler part of the USB driver. It +requires a 15 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! +*/ + +;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + +;---------------------------------------------------------------------------- +; order of registers pushed: +; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4 +;---------------------------------------------------------------------------- +USB_INTR_VECTOR: + push YL ;2 push only what is necessary to sync with edge ASAP + in YL, SREG ;1 + push YL ;2 +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +; +; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +; sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +;------------------------------------------------------------------------------- +; The following code results in a sampling window of < 1/4 bit +; which meets the spec. +;------------------------------------------------------------------------------- +waitForK: ;- + sbis USBIN, USBMINUS ;1 [00] <-- sample + rjmp foundK ;2 [01] + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +;------------------------------------------------------------------------------ +; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for +; center sampling] +; we have 1 bit time for setup purposes, then sample again. +; Numbers in brackets are cycles from center of first sync (double K) +; bit after the instruction +;------------------------------------------------------------------------------ +foundK: ;- [02] + lds YL, usbInputBufOffset;2 [03+04] tx loop + push YH ;2 [05+06] + clr YH ;1 [07] + subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init] + sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init] + push shift ;2 [10+11] + ser shift ;1 [12] + sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early) + rjmp haveTwoBitsK ;2 [00] [14] + pop shift ;2 [15+16] undo the push from before + pop YH ;2 [17+18] undo the push from before + rjmp waitForK ;2 [19+20] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 20 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: ;- [01] + push x1 ;2 [02+03] + push x2 ;2 [04+05] + push x3 ;2 [06+07] + push bitcnt ;2 [08+09] + in x1, USBIN ;1 [00] [10] <-- sample bit 0 + bst x1, USBMINUS ;1 [01] + bld shift, 0 ;1 [02] + push cnt ;2 [03+04] + ldi cnt, USB_BUFSIZE ;1 [05] + push x4 ;2 [06+07] tx loop + rjmp rxLoop ;2 [08] +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +unstuff0: ;- [07] (branch taken) + andi x3, ~0x01 ;1 [08] + mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit + in x2, USBIN ;1 [00] [10] <-- sample bit 1 again + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 1 + ori shift, 0x01 ;1 [03] 0b00000001 + nop ;1 [04] + rjmp didUnstuff0 ;2 [05] +;----------------------------------------------------- +unstuff1: ;- [05] (branch taken) + mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit + andi x3, ~0x02 ;1 [07] + ori shift, 0x02 ;1 [08] 0b00000010 + nop ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 2 again + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 2 + rjmp didUnstuff1 ;2 [03] +;----------------------------------------------------- +unstuff2: ;- [05] (branch taken) + andi x3, ~0x04 ;1 [06] + ori shift, 0x04 ;1 [07] 0b00000100 + mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit + nop ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample bit 3 + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 3 + rjmp didUnstuff2 ;2 [03] +;----------------------------------------------------- +unstuff3: ;- [00] [10] (branch taken) + in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late + andi x2, USBMASK ;1 [02] + breq se0Hop ;1 [03] SE0 check for stuffed bit 3 + andi x3, ~0x08 ;1 [04] + ori shift, 0x08 ;1 [05] 0b00001000 + rjmp didUnstuff3 ;2 [06] +;---------------------------------------------------------------------------- +; extra jobs done during bit interval: +; +; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs], +; overflow check, jump to the head of rxLoop +; bit 1: SE0 check +; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long] +; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long] +; bit 4: SE0 check, none +; bit 5: SE0 check, none +; bit 6: SE0 check, none +; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others +;---------------------------------------------------------------------------- +rxLoop: ;- [09] + in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed) + andi x2, USBMASK ;1 [01] + brne SkipSe0Hop ;1 [02] +se0Hop: ;- [02] + rjmp se0 ;2 [03] SE0 check for bit 1 +SkipSe0Hop: ;- [03] + ser x3 ;1 [04] + andi shift, 0xf9 ;1 [05] 0b11111001 + breq unstuff0 ;1 [06] +didUnstuff0: ;- [06] + eor x1, x2 ;1 [07] + bst x1, USBMINUS ;1 [08] + bld shift, 1 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed) + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 2 + andi shift, 0xf3 ;1 [03] 0b11110011 + breq unstuff1 ;1 [04] do remaining work for bit 1 +didUnstuff1: ;- [04] + eor x2, x1 ;1 [05] + bst x2, USBMINUS ;1 [06] + bld shift, 2 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed) + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 3 + andi shift, 0xe7 ;1 [03] 0b11100111 + breq unstuff2 ;1 [04] +didUnstuff2: ;- [04] + eor x1, x2 ;1 [05] + bst x1, USBMINUS ;1 [06] + bld shift, 3 ;1 [07] +didUnstuff3: ;- [07] + andi shift, 0xcf ;1 [08] 0b11001111 + breq unstuff3 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 4 + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 4 + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 4 ;1 [05] +didUnstuff4: ;- [05] + andi shift, 0x9f ;1 [06] 0b10011111 + breq unstuff4 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 5 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 5 + eor x1, x2 ;1 [03] + bst x1, USBMINUS ;1 [04] + bld shift, 5 ;1 [05] +didUnstuff5: ;- [05] + andi shift, 0x3f ;1 [06] 0b00111111 + breq unstuff5 ;1 [07] + nop2 ;2 [08+09] + in x1, USBIN ;1 [00] [10] <-- sample bit 6 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 6 + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 6 ;1 [05] +didUnstuff6: ;- [05] + cpi shift, 0x02 ;1 [06] 0b00000010 + brlo unstuff6 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 7 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 7 + eor x1, x2 ;1 [03] + bst x1, USBMINUS ;1 [04] + bld shift, 7 ;1 [05] +didUnstuff7: ;- [05] + cpi shift, 0x04 ;1 [06] 0b00000100 + brlo unstuff7 ;1 [07] + eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others + nop ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 0 + st y+, x3 ;2 [01+02] store data + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 0 ;1 [05] + subi cnt, 1 ;1 [06] + brcs overflow ;1 [07] + rjmp rxLoop ;2 [08] +;----------------------------------------------------- +unstuff4: ;- [08] + andi x3, ~0x10 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 4 + ori shift, 0x10 ;1 [03] + rjmp didUnstuff4 ;2 [04] +;----------------------------------------------------- +unstuff5: ;- [08] + ori shift, 0x20 ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 5 + andi x3, ~0x20 ;1 [03] + rjmp didUnstuff5 ;2 [04] +;----------------------------------------------------- +unstuff6: ;- [08] + andi x3, ~0x40 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 6 + ori shift, 0x40 ;1 [03] + rjmp didUnstuff6 ;2 [04] +;----------------------------------------------------- +unstuff7: ;- [08] + andi x3, ~0x80 ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 7 + ori shift, 0x80 ;1 [03] + rjmp didUnstuff7 ;2 [04] + +macro POP_STANDARD ; 16 cycles + pop x4 + pop cnt + pop bitcnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;--------------------------------------------------------------------------- +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies +;--------------------------------------------------------------------------- +bitstuffN: ;- [04] + eor x1, x4 ;1 [05] + clr x2 ;1 [06] + nop ;1 [07] + rjmp didStuffN ;1 [08] +;--------------------------------------------------------------------------- +bitstuff6: ;- [04] + eor x1, x4 ;1 [05] + clr x2 ;1 [06] + rjmp didStuff6 ;1 [07] +;--------------------------------------------------------------------------- +bitstuff7: ;- [02] + eor x1, x4 ;1 [03] + clr x2 ;1 [06] + nop ;1 [05] + rjmp didStuff7 ;1 [06] +;--------------------------------------------------------------------------- +sendNakAndReti: ;- [-19] + ldi x3, USBPID_NAK ;1 [-18] + rjmp sendX3AndReti ;1 [-17] +;--------------------------------------------------------------------------- +sendAckAndReti: ;- [-17] + ldi cnt, USBPID_ACK ;1 [-16] +sendCntAndReti: ;- [-16] + mov x3, cnt ;1 [-15] +sendX3AndReti: ;- [-15] + ldi YL, 20 ;1 [-14] x3==r20 address is 20 + ldi YH, 0 ;1 [-13] + ldi cnt, 2 ;1 [-12] +; rjmp usbSendAndReti fallthrough +;--------------------------------------------------------------------------- +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +;We need not to match the transfer rate exactly because the spec demands +;only 1.5% precision anyway. +usbSendAndReti: ;- [-13] 13 cycles until SOP + in x2, USBDDR ;1 [-12] + ori x2, USBMASK ;1 [-11] + sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;1 [-08] port mirror for tx loop + out USBDDR, x2 ;1 [-07] <- acquire bus + ; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;1 [-06] exor mask + ldi shift, 0x80 ;1 [-05] sync byte is first byte sent + ldi bitcnt, 6 ;1 [-04] +txBitLoop: ;- [-04] [06] + sbrs shift, 0 ;1 [-03] [07] + eor x1, x4 ;1 [-02] [08] + ror shift ;1 [-01] [09] +didStuffN: ;- [09] + out USBOUT, x1 ;1 [00] [10] <-- out N + ror x2 ;1 [01] + cpi x2, 0xfc ;1 [02] + brcc bitstuffN ;1 [03] + dec bitcnt ;1 [04] + brne txBitLoop ;1 [05] + sbrs shift, 0 ;1 [06] + eor x1, x4 ;1 [07] + ror shift ;1 [08] +didStuff6: ;- [08] + nop ;1 [09] + out USBOUT, x1 ;1 [00] [10] <-- out 6 + ror x2 ;1 [01] + cpi x2, 0xfc ;1 [02] + brcc bitstuff6 ;1 [03] + sbrs shift, 0 ;1 [04] + eor x1, x4 ;1 [05] + ror shift ;1 [06] + ror x2 ;1 [07] +didStuff7: ;- [07] + ldi bitcnt, 6 ;1 [08] + cpi x2, 0xfc ;1 [09] + out USBOUT, x1 ;1 [00] [10] <-- out 7 + brcc bitstuff7 ;1 [01] + ld shift, y+ ;2 [02+03] + dec cnt ;1 [04] + brne txBitLoop ;1 [05] +makeSE0: + cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles] + lds x2, usbNewDeviceAddr;2 [07+08] + lsl x2 ;1 [09] we compare with left shifted address +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle + subi YL, 20 + 2 ;1 [01] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;1 [02] + breq skipAddrAssign ;1 [03] + sts usbDeviceAddr, x2 ;2 [04+05] if not skipped: SE0 is one cycle longer +;---------------------------------------------------------------------------- +;end of usbDeviceAddress transfer +skipAddrAssign: ;- [03/04] + ldi x2, 1< 10.6666666 cycles per bit, 85.333333333 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt + push YL ;[-25] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-23] + push YL ;[-22] + push YH ;[-20] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-15] + rjmp foundK ;[-14] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-12] +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push bitcnt ;[-12] +; [---] ;[-11] + lds YL, usbInputBufOffset;[-10] +; [---] ;[-9] + clr YH ;[-8] + subi YL, lo8(-(usbRxBuf));[-7] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init] + push shift ;[-5] +; [---] ;[-4] + ldi bitcnt, 0x55 ;[-3] [rx loop init] + sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early) + rjmp haveTwoBitsK ;[-1] + pop shift ;[0] undo the push from before + pop bitcnt ;[2] undo the push from before + rjmp waitForK ;[4] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 21 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[1] + push x2 ;[3] + push x3 ;[5] + ldi shift, 0 ;[7] + ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that + push x4 ;[9] == leap + + in x1, USBIN ;[11] <-- sample bit 0 + andi x1, USBMASK ;[12] + bst x1, USBMINUS ;[13] + bld shift, 7 ;[14] + push cnt ;[15] + ldi leap, 0 ;[17] [rx loop init] + ldi cnt, USB_BUFSIZE;[18] [rx loop init] + rjmp rxbit1 ;[19] arrives at [21] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- + +; duration of unstuffing code should be 10.66666667 cycles. We adjust "leap" +; accordingly to approximate this value in the long run. + +unstuff6: + andi x2, USBMASK ;[03] + ori x3, 1<<6 ;[04] will not be shifted any more + andi shift, ~0x80;[05] + mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6 + subi leap, -1 ;[07] total duration = 11 bits -> subtract 1/3 + rjmp didUnstuff6 ;[08] + +unstuff7: + ori x3, 1<<7 ;[09] will not be shifted any more + in x2, USBIN ;[00] [10] re-sample bit 7 + andi x2, USBMASK ;[01] + andi shift, ~0x80;[02] + subi leap, 2 ;[03] total duration = 10 bits -> add 1/3 + rjmp didUnstuff7 ;[04] + +unstuffEven: + ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0 + in x1, USBIN ;[00] [10] + andi shift, ~0x80;[01] + andi x1, USBMASK ;[02] + breq se0 ;[03] + subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3 + nop2 ;[05] + rjmp didUnstuffE ;[06] + +unstuffOdd: + ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1 + in x2, USBIN ;[00] [10] + andi shift, ~0x80;[01] + andi x2, USBMASK ;[02] + breq se0 ;[03] + subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3 + nop2 ;[05] + rjmp didUnstuffO ;[06] + +rxByteLoop: + andi x1, USBMASK ;[03] + eor x2, x1 ;[04] + subi leap, 1 ;[05] + brpl skipLeap ;[06] + subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte + nop ;1 +skipLeap: + subi x2, 1 ;[08] + ror shift ;[09] +didUnstuff6: + cpi shift, 0xfc ;[10] + in x2, USBIN ;[00] [11] <-- sample bit 7 + brcc unstuff6 ;[01] + andi x2, USBMASK ;[02] + eor x1, x2 ;[03] + subi x1, 1 ;[04] + ror shift ;[05] +didUnstuff7: + cpi shift, 0xfc ;[06] + brcc unstuff7 ;[07] + eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others + st y+, x3 ;[09] store data +rxBitLoop: + in x1, USBIN ;[00] [11] <-- sample bit 0/2/4 + andi x1, USBMASK ;[01] + eor x2, x1 ;[02] + andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7 + subi x2, 1 ;[04] + ror shift ;[05] + cpi shift, 0xfc ;[06] + brcc unstuffEven ;[07] +didUnstuffE: + lsr x3 ;[08] + lsr x3 ;[09] +rxbit1: + in x2, USBIN ;[00] [10] <-- sample bit 1/3/5 + andi x2, USBMASK ;[01] + breq se0 ;[02] + eor x1, x2 ;[03] + subi x1, 1 ;[04] + ror shift ;[05] + cpi shift, 0xfc ;[06] + brcc unstuffOdd ;[07] +didUnstuffO: + subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3 + brcs rxBitLoop ;[09] + + subi cnt, 1 ;[10] + in x1, USBIN ;[00] [11] <-- sample bit 6 + brcc rxByteLoop ;[01] + rjmp overflow + +macro POP_STANDARD ; 14 cycles + pop cnt + pop x4 + pop x3 + pop x2 + pop x1 + pop shift + pop bitcnt + endm +macro POP_RETI ; 7 cycles + pop YH + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies + +bitstuffN: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] + nop2 ;[7] + nop ;[9] + out USBOUT, x1 ;[10] <-- out + rjmp didStuffN ;[0] + +bitstuff6: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] Carry is zero due to brcc + rol shift ;[7] compensate for ror shift at branch destination + rjmp didStuff6 ;[8] + +bitstuff7: + ldi x2, 0 ;[2] Carry is zero due to brcc + rjmp didStuff7 ;[3] + + +sendNakAndReti: + ldi x3, USBPID_NAK ;[-18] + rjmp sendX3AndReti ;[-17] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov x3, cnt ;[-16] +sendX3AndReti: + ldi YL, 20 ;[-15] x3==r20 address is 20 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +;We don't match the transfer rate exactly (don't insert leap cycles every third +;byte) because the spec demands only 1.5% precision anyway. +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-7] <- acquire bus +; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-6] exor mask + ldi shift, 0x80 ;[-5] sync byte is first byte sent +txByteLoop: + ldi bitcnt, 0x35 ;[-4] [6] binary 0011 0101 +txBitLoop: + sbrs shift, 0 ;[-3] [7] + eor x1, x4 ;[-2] [8] + out USBOUT, x1 ;[-1] [9] <-- out N + ror shift ;[0] [10] + ror x2 ;[1] +didStuffN: + cpi x2, 0xfc ;[2] + brcc bitstuffN ;[3] + lsr bitcnt ;[4] + brcc txBitLoop ;[5] + brne txBitLoop ;[6] + + sbrs shift, 0 ;[7] + eor x1, x4 ;[8] +didStuff6: + out USBOUT, x1 ;[-1] [9] <-- out 6 + ror shift ;[0] [10] + ror x2 ;[1] + cpi x2, 0xfc ;[2] + brcc bitstuff6 ;[3] + ror shift ;[4] +didStuff7: + ror x2 ;[5] + sbrs x2, 7 ;[6] + eor x1, x4 ;[7] + nop ;[8] + cpi x2, 0xfc ;[9] + out USBOUT, x1 ;[-1][10] <-- out 7 + brcc bitstuff7 ;[0] [11] + ld shift, y+ ;[1] + dec cnt ;[3] + brne txByteLoop ;[4] +;make SE0: + cbr x1, USBMASK ;[5] prepare SE0 [spec says EOP may be 21 to 25 cycles] + lds x2, usbNewDeviceAddr;[6] + lsl x2 ;[8] we compare with left shifted address + subi YL, 20 + 2 ;[9] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[10] + out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[0] + sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< max 52 cycles interrupt disable +;max stack usage: [ret(2), r0, SREG, YL, YH, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 16.5 MHz -> 11 cycles per bit +; 16.3125 MHz < F_CPU < 16.6875 MHz (+/- 1.1%) +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], r0, YH, shift, x1, x2, x3, x4, cnt + push YL ;[-23] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-21] + push YL ;[-20] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-15] + rjmp foundK ;[-14] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-12] +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push r0 ;[-12] +; [---] ;[-11] + push YH ;[-10] +; [---] ;[-9] + lds YL, usbInputBufOffset;[-8] +; [---] ;[-7] + clr YH ;[-6] + subi YL, lo8(-(usbRxBuf));[-5] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-4] [rx loop init] + mov r0, x2 ;[-3] [rx loop init] + sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early) + rjmp haveTwoBitsK ;[-1] + pop YH ;[0] undo the pushes from before + pop r0 ;[2] + rjmp waitForK ;[4] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 22 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: ;[1] + push shift ;[1] + push x1 ;[3] + push x2 ;[5] + push x3 ;[7] + ldi shift, 0xff ;[9] [rx loop init] + ori x3, 0xff ;[10] [rx loop init] == ser x3, clear zero flag + + in x1, USBIN ;[11] <-- sample bit 0 + bst x1, USBMINUS ;[12] + bld shift, 0 ;[13] + push x4 ;[14] == phase +; [---] ;[15] + push cnt ;[16] +; [---] ;[17] + ldi phase, 0 ;[18] [rx loop init] + ldi cnt, USB_BUFSIZE;[19] [rx loop init] + rjmp rxbit1 ;[20] +; [---] ;[21] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +/* +byte oriented operations done during loop: +bit 0: store data +bit 1: SE0 check +bit 2: overflow check +bit 3: catch up +bit 4: rjmp to achieve conditional jump range +bit 5: PLL +bit 6: catch up +bit 7: jump, fixup bitstuff +; 87 [+ 2] cycles +------------------------------------------------------------------ +*/ +continueWithBit5: + in x2, USBIN ;[055] <-- bit 5 + eor r0, x2 ;[056] + or phase, r0 ;[057] + sbrc phase, USBMINUS ;[058] + lpm ;[059] optional nop3; modifies r0 + in phase, USBIN ;[060] <-- phase + eor x1, x2 ;[061] + bst x1, USBMINUS ;[062] + bld shift, 5 ;[063] + andi shift, 0x3f ;[064] + in x1, USBIN ;[065] <-- bit 6 + breq unstuff5 ;[066] *** unstuff escape + eor phase, x1 ;[067] + eor x2, x1 ;[068] + bst x2, USBMINUS ;[069] + bld shift, 6 ;[070] +didUnstuff6: ;[ ] + in r0, USBIN ;[071] <-- phase + cpi shift, 0x02 ;[072] + brlo unstuff6 ;[073] *** unstuff escape +didUnstuff5: ;[ ] + nop2 ;[074] +; [---] ;[075] + in x2, USBIN ;[076] <-- bit 7 + eor x1, x2 ;[077] + bst x1, USBMINUS ;[078] + bld shift, 7 ;[079] +didUnstuff7: ;[ ] + eor r0, x2 ;[080] + or phase, r0 ;[081] + in r0, USBIN ;[082] <-- phase + cpi shift, 0x04 ;[083] + brsh rxLoop ;[084] +; [---] ;[085] +unstuff7: ;[ ] + andi x3, ~0x80 ;[085] + ori shift, 0x80 ;[086] + in x2, USBIN ;[087] <-- sample stuffed bit 7 + nop ;[088] + rjmp didUnstuff7 ;[089] +; [---] ;[090] + ;[080] + +unstuff5: ;[067] + eor phase, x1 ;[068] + andi x3, ~0x20 ;[069] + ori shift, 0x20 ;[070] + in r0, USBIN ;[071] <-- phase + mov x2, x1 ;[072] + nop ;[073] + nop2 ;[074] +; [---] ;[075] + in x1, USBIN ;[076] <-- bit 6 + eor r0, x1 ;[077] + or phase, r0 ;[078] + eor x2, x1 ;[079] + bst x2, USBMINUS ;[080] + bld shift, 6 ;[081] no need to check bitstuffing, we just had one + in r0, USBIN ;[082] <-- phase + rjmp didUnstuff5 ;[083] +; [---] ;[084] + ;[074] + +unstuff6: ;[074] + andi x3, ~0x40 ;[075] + in x1, USBIN ;[076] <-- bit 6 again + ori shift, 0x40 ;[077] + nop2 ;[078] +; [---] ;[079] + rjmp didUnstuff6 ;[080] +; [---] ;[081] + ;[071] + +unstuff0: ;[013] + eor r0, x2 ;[014] + or phase, r0 ;[015] + andi x2, USBMASK ;[016] check for SE0 + in r0, USBIN ;[017] <-- phase + breq didUnstuff0 ;[018] direct jump to se0 would be too long + andi x3, ~0x01 ;[019] + ori shift, 0x01 ;[020] + mov x1, x2 ;[021] mov existing sample + in x2, USBIN ;[022] <-- bit 1 again + rjmp didUnstuff0 ;[023] +; [---] ;[024] + ;[014] + +unstuff1: ;[024] + eor r0, x1 ;[025] + or phase, r0 ;[026] + andi x3, ~0x02 ;[027] + in r0, USBIN ;[028] <-- phase + ori shift, 0x02 ;[029] + mov x2, x1 ;[030] + rjmp didUnstuff1 ;[031] +; [---] ;[032] + ;[022] + +unstuff2: ;[035] + eor r0, x2 ;[036] + or phase, r0 ;[037] + andi x3, ~0x04 ;[038] + in r0, USBIN ;[039] <-- phase + ori shift, 0x04 ;[040] + mov x1, x2 ;[041] + rjmp didUnstuff2 ;[042] +; [---] ;[043] + ;[033] + +unstuff3: ;[043] + in x2, USBIN ;[044] <-- bit 3 again + eor r0, x2 ;[045] + or phase, r0 ;[046] + andi x3, ~0x08 ;[047] + ori shift, 0x08 ;[048] + nop ;[049] + in r0, USBIN ;[050] <-- phase + rjmp didUnstuff3 ;[051] +; [---] ;[052] + ;[042] + +unstuff4: ;[053] + andi x3, ~0x10 ;[054] + in x1, USBIN ;[055] <-- bit 4 again + ori shift, 0x10 ;[056] + rjmp didUnstuff4 ;[057] +; [---] ;[058] + ;[048] + +rxLoop: ;[085] + eor x3, shift ;[086] reconstruct: x3 is 0 at bit locations we changed, 1 at others + in x1, USBIN ;[000] <-- bit 0 + st y+, x3 ;[001] +; [---] ;[002] + eor r0, x1 ;[003] + or phase, r0 ;[004] + eor x2, x1 ;[005] + in r0, USBIN ;[006] <-- phase + ser x3 ;[007] + bst x2, USBMINUS ;[008] + bld shift, 0 ;[009] + andi shift, 0xf9 ;[010] +rxbit1: ;[ ] + in x2, USBIN ;[011] <-- bit 1 + breq unstuff0 ;[012] *** unstuff escape + andi x2, USBMASK ;[013] SE0 check for bit 1 +didUnstuff0: ;[ ] Z only set if we detected SE0 in bitstuff + breq se0 ;[014] + eor r0, x2 ;[015] + or phase, r0 ;[016] + in r0, USBIN ;[017] <-- phase + eor x1, x2 ;[018] + bst x1, USBMINUS ;[019] + bld shift, 1 ;[020] + andi shift, 0xf3 ;[021] +didUnstuff1: ;[ ] + in x1, USBIN ;[022] <-- bit 2 + breq unstuff1 ;[023] *** unstuff escape + eor r0, x1 ;[024] + or phase, r0 ;[025] + subi cnt, 1 ;[026] overflow check + brcs overflow ;[027] + in r0, USBIN ;[028] <-- phase + eor x2, x1 ;[029] + bst x2, USBMINUS ;[030] + bld shift, 2 ;[031] + andi shift, 0xe7 ;[032] +didUnstuff2: ;[ ] + in x2, USBIN ;[033] <-- bit 3 + breq unstuff2 ;[034] *** unstuff escape + eor r0, x2 ;[035] + or phase, r0 ;[036] + eor x1, x2 ;[037] + bst x1, USBMINUS ;[038] + in r0, USBIN ;[039] <-- phase + bld shift, 3 ;[040] + andi shift, 0xcf ;[041] +didUnstuff3: ;[ ] + breq unstuff3 ;[042] *** unstuff escape + nop ;[043] + in x1, USBIN ;[044] <-- bit 4 + eor x2, x1 ;[045] + bst x2, USBMINUS ;[046] + bld shift, 4 ;[047] +didUnstuff4: ;[ ] + eor r0, x1 ;[048] + or phase, r0 ;[049] + in r0, USBIN ;[050] <-- phase + andi shift, 0x9f ;[051] + breq unstuff4 ;[052] *** unstuff escape + rjmp continueWithBit5;[053] +; [---] ;[054] + +macro POP_STANDARD ; 16 cycles + pop cnt + pop x4 + pop x3 + pop x2 + pop x1 + pop shift + pop YH + pop r0 + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies + +bitstuff7: + eor x1, x4 ;[4] + ldi x2, 0 ;[5] + nop2 ;[6] C is zero (brcc) + rjmp didStuff7 ;[8] + +bitstuffN: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] + lpm ;[7] 3 cycle NOP, modifies r0 + out USBOUT, x1 ;[10] <-- out + rjmp didStuffN ;[0] + +#define bitStatus x3 + +sendNakAndReti: + ldi cnt, USBPID_NAK ;[-19] + rjmp sendCntAndReti ;[-18] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov r0, cnt ;[-16] + ldi YL, 0 ;[-15] R0 address is 0 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-7] <- acquire bus +; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-6] exor mask + ldi shift, 0x80 ;[-5] sync byte is first byte sent + ldi bitStatus, 0xff ;[-4] init bit loop counter, works for up to 12 bytes +byteloop: +bitloop: + sbrs shift, 0 ;[8] [-3] + eor x1, x4 ;[9] [-2] + out USBOUT, x1 ;[10] [-1] <-- out + ror shift ;[0] + ror x2 ;[1] +didStuffN: + cpi x2, 0xfc ;[2] + brcc bitstuffN ;[3] + nop ;[4] + subi bitStatus, 37 ;[5] 256 / 7 ~=~ 37 + brcc bitloop ;[6] when we leave the loop, bitStatus has almost the initial value + sbrs shift, 0 ;[7] + eor x1, x4 ;[8] + ror shift ;[9] +didStuff7: + out USBOUT, x1 ;[10] <-- out + ror x2 ;[0] + cpi x2, 0xfc ;[1] + brcc bitstuff7 ;[2] + ld shift, y+ ;[3] + dec cnt ;[5] + brne byteloop ;[6] +;make SE0: + cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles] + lds x2, usbNewDeviceAddr;[8] + lsl x2 ;[10] we compare with left shifted address + out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + subi YL, 2 ;[0] Only assign address on data packets, not ACK/NAK in r0 + sbci YH, 0 ;[1] + breq skipAddrAssign ;[2] + sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 12 cycles per bit +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts +;register use in receive loop to receive the data bytes: +; shift assembles the byte currently being received +; x1 holds the D+ and D- line state +; x2 holds the previous line state +; cnt holds the number of bytes left in the receive buffer +; x3 holds the higher crc byte (see algorithm below) +; x4 is used as temporary register for the crc algorithm +; x5 is used for unstuffing: when unstuffing the last received bit is inverted in shift (to prevent further +; unstuffing calls. In the same time the corresponding bit in x5 is cleared to mark the bit as beening iverted +; zl lower crc value and crc table index +; zh used for crc table accesses + +;-------------------------------------------------------------------------------------------------------------- +; CRC mods: +; table driven crc checker, Z points to table in prog space +; ZL is the lower crc byte, x3 is the higher crc byte +; x4 is used as temp register to store different results +; the initialization of the crc register is not 0xFFFF but 0xFE54. This is because during the receipt of the +; first data byte an virtual zero data byte is added to the crc register, this results in the correct initial +; value of 0xFFFF at beginning of the second data byte before the first data byte is added to the crc. +; The magic number 0xFE54 results form the crc table: At tabH[0x54] = 0xFF = crcH (required) and +; tabL[0x54] = 0x01 -> crcL = 0x01 xor 0xFE = 0xFF +; bitcnt is renamed to x5 and is used for unstuffing purposes, the unstuffing works like in the 12MHz version +;-------------------------------------------------------------------------------------------------------------- +; CRC algorithm: +; The crc register is formed by x3 (higher byte) and ZL (lower byte). The algorithm uses a 'reversed' form +; i.e. that it takes the least significant bit first and shifts to the right. So in fact the highest order +; bit seen from the polynomial devision point of view is the lsb of ZL. (If this sounds strange to you i +; propose a research on CRC :-) ) +; Each data byte received is xored to ZL, the lower crc byte. This byte now builds the crc +; table index. Next the new high byte is loaded from the table and stored in x4 until we have space in x3 +; (its destination). +; Afterwards the lower table is loaded from the table and stored in ZL (the old index is overwritten as +; we don't need it anymore. In fact this is a right shift by 8 bits.) Now the old crc high value is xored +; to ZL, this is the second shift of the old crc value. Now x4 (the temp reg) is moved to x3 and the crc +; calculation is done. +; Prior to the first byte the two CRC register have to be initialized to 0xFFFF (as defined in usb spec) +; however the crc engine also runs during the receipt of the first byte, therefore x3 and zl are initialized +; to a magic number which results in a crc value of 0xFFFF after the first complete byte. +; +; This algorithm is split into the extra cycles of the different bits: +; bit7: XOR the received byte to ZL +; bit5: load the new high byte to x4 +; bit6: load the lower xor byte from the table, xor zl and x3, store result in zl (=the new crc low value) +; move x4 (the new high byte) to x3, the crc value is ready +; + + +macro POP_STANDARD ; 18 cycles + pop ZH + pop ZL + pop cnt + pop x5 + pop x3 + pop x2 + pop x1 + pop shift + pop x4 + endm +macro POP_RETI ; 7 cycles + pop YH + pop YL + out SREG, YL + pop YL + endm + +macro CRC_CLEANUP_AND_CHECK + ; the last byte has already been xored with the lower crc byte, we have to do the table lookup and xor + ; x3 is the higher crc byte, zl the lower one + ldi ZH, hi8(usbCrcTableHigh);[+1] get the new high byte from the table + lpm x2, Z ;[+2][+3][+4] + ldi ZH, hi8(usbCrcTableLow);[+5] get the new low xor byte from the table + lpm ZL, Z ;[+6][+7][+8] + eor ZL, x3 ;[+7] xor the old high byte with the value from the table, x2:ZL now holds the crc value + cpi ZL, 0x01 ;[+8] if the crc is ok we have a fixed remainder value of 0xb001 in x2:ZL (see usb spec) + brne ignorePacket ;[+9] detected a crc fault -> paket is ignored and retransmitted by the host + cpi x2, 0xb0 ;[+10] + brne ignorePacket ;[+11] detected a crc fault -> paket is ignored and retransmitted by the host + endm + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG, YH, [sofError], x4, shift, x1, x2, x3, x5, cnt, ZL, ZH + push YL ;[-28] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-26] + push YL ;[-25] + push YH ;[-23] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-17] + rjmp foundK ;[-16] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-15] +;{3, 5} after falling D- edge, average delay: 4 cycles +;bit0 should be at 30 (2.5 bits) for center sampling. Currently at 4 so 26 cylces till bit 0 sample +;use 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push x4 ;[-14] +; [---] ;[-13] + lds YL, usbInputBufOffset;[-12] used to toggle the two usb receive buffers +; [---] ;[-11] + clr YH ;[-10] + subi YL, lo8(-(usbRxBuf));[-9] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-8] [rx loop init] + push shift ;[-7] +; [---] ;[-6] + ldi shift, 0x80 ;[-5] the last bit is the end of byte marker for the pid receiver loop + clc ;[-4] the carry has to be clear for receipt of pid bit 0 + sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) + rjmp haveTwoBitsK ;[-2] + pop shift ;[-1] undo the push from before + pop x4 ;[1] + rjmp waitForK ;[3] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 24 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[0] + push x2 ;[2] + push x3 ;[4] crc high byte + ldi x2, 1< jump back and store the byte + ori shift, 0x01 ;[11] invert the last received bit to prevent furhter unstuffing + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + andi x5, 0xFE ;[1] mark this bit as inverted (will be corrected before storing shift) + eor x1, x2 ;[2] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[3] mask the interesting bits + breq stuffErr ;[4] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[5] the next bit expects the last state to be in x1 + rjmp didunstuff0 ;[6] + ;[7] jump delay of rjmp didunstuffX + +unstuff1: ;[11] this is the jump delay of breq unstuffX + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + ori shift, 0x02 ;[1] invert the last received bit to prevent furhter unstuffing + andi x5, 0xFD ;[2] mark this bit as inverted (will be corrected before storing shift) + eor x2, x1 ;[3] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[4] mask the interesting bits + breq stuffErr ;[5] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[6] the next bit expects the last state to be in x2 + nop2 ;[7] + ;[8] + rjmp didunstuff1 ;[9] + ;[10] jump delay of rjmp didunstuffX + +unstuff2: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x04 ;[10] invert the last received bit to prevent furhter unstuffing + andi x5, 0xFB ;[11] mark this bit as inverted (will be corrected before storing shift) + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[4] the next bit expects the last state to be in x1 + nop2 ;[5] + ;[6] + rjmp didunstuff2 ;[7] + ;[8] jump delay of rjmp didunstuffX + +unstuff3: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x08 ;[10] invert the last received bit to prevent furhter unstuffing + andi x5, 0xF7 ;[11] mark this bit as inverted (will be corrected before storing shift) + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[4] the next bit expects the last state to be in x2 + nop2 ;[5] + ;[6] + rjmp didunstuff3 ;[7] + ;[8] jump delay of rjmp didunstuffX + + + +; the include has to be here due to branch distance restirctions +#define __USE_CRC__ +#include "asmcommon.inc" + + + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies +; 7.5 bit times is 90 cycles. ...there is plenty of time + + +sendNakAndReti: + ldi x3, USBPID_NAK ;[-18] + rjmp sendX3AndReti ;[-17] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov x3, cnt ;[-16] +sendX3AndReti: + ldi YL, 20 ;[-15] x3==r20 address is 20 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent + +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-6] <- acquire bus + ldi x2, 0 ;[-6] init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-5] exor mask + ldi shift, 0x80 ;[-4] sync byte is first byte sent +txByteLoop: + ldi bitcnt, 0x40 ;[-3]=[9] binary 01000000 +txBitLoop: ; the loop sends the first 7 bits of the byte + sbrs shift, 0 ;[-2]=[10] if we have to send a 1 don't change the line state + eor x1, x4 ;[-1]=[11] + out USBOUT, x1 ;[0] + ror shift ;[1] + ror x2 ;[2] transfers the last sent bit to the stuffing history +didStuffN: + nop ;[3] + nop ;[4] + cpi x2, 0xfc ;[5] if we sent six consecutive ones + brcc bitstuffN ;[6] + lsr bitcnt ;[7] + brne txBitLoop ;[8] restart the loop while the 1 is still in the bitcount + +; transmit bit 7 + sbrs shift, 0 ;[9] + eor x1, x4 ;[10] +didStuff7: + ror shift ;[11] + out USBOUT, x1 ;[0] transfer bit 7 to the pins + ror x2 ;[1] move the bit into the stuffing history + cpi x2, 0xfc ;[2] + brcc bitstuff7 ;[3] + ld shift, y+ ;[4] get next byte to transmit + dec cnt ;[5] decrement byte counter + brne txByteLoop ;[7] if we have more bytes start next one + ;[8] branch delay + +;make SE0: + cbr x1, USBMASK ;[8] prepare SE0 [spec says EOP may be 25 to 30 cycles] + lds x2, usbNewDeviceAddr;[9] + lsl x2 ;[11] we compare with left shifted address + out USBOUT, x1 ;[0] <-- out SE0 -- from now 2 bits = 24 cycles until bus idle + subi YL, 20 + 2 ;[1] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[2] +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[3] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< +int main (int argc, char **argv) +{ + int i, j; + for (i=0; i<512; i++){ + unsigned short crc = i & 0xff; + for(j=0; j<8; j++) crc = (crc >> 1) ^ ((crc & 1) ? 0xa001 : 0); + if((i & 7) == 0) printf("\n.byte "); + printf("0x%02x, ", (i > 0xff ? (crc >> 8) : crc) & 0xff); + if(i == 255) printf("\n"); + } + return 0; +} + +// Use the following algorithm to compute CRC values: +ushort computeCrc(uchar *msg, uchar msgLen) +{ + uchar i; + ushort crc = 0xffff; + for(i = 0; i < msgLen; i++) + crc = usbCrcTable16[lo8(crc) ^ msg[i]] ^ hi8(crc); + return crc; +} +*/ + +.balign 256 +usbCrcTableLow: +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 + +; .balign 256 +usbCrcTableHigh: +.byte 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2 +.byte 0xC6, 0x06, 0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04 +.byte 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E +.byte 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8 +.byte 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A +.byte 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC +.byte 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6 +.byte 0xD2, 0x12, 0x13, 0xD3, 0x11, 0xD1, 0xD0, 0x10 +.byte 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32 +.byte 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4 +.byte 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE +.byte 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38 +.byte 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA +.byte 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C +.byte 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26 +.byte 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0 +.byte 0xA0, 0x60, 0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62 +.byte 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4 +.byte 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE +.byte 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68 +.byte 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA +.byte 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C +.byte 0xB4, 0x74, 0x75, 0xB5, 0x77, 0xB7, 0xB6, 0x76 +.byte 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0 +.byte 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92 +.byte 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54 +.byte 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E +.byte 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98 +.byte 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A +.byte 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C +.byte 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86 +.byte 0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 0x40 + diff --git a/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm20.inc b/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm20.inc new file mode 100644 index 0000000..303abaf --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkJoystick/usbdrvasm20.inc @@ -0,0 +1,360 @@ +/* Name: usbdrvasm20.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Jeroen Benschop + * Based on usbdrvasm16.inc from Christian Starkjohann + * Creation Date: 2008-03-05 + * Tabsize: 4 + * Copyright: (c) 2008 by Jeroen Benschop and OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm20.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 20 MHz version of the asssembler part of the USB driver. It +requires a 20 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! +*/ + +#define leap2 x3 +#ifdef __IAR_SYSTEMS_ASM__ +#define nextInst $+2 +#else +#define nextInst .+0 +#endif + +;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 20 MHz -> 13.333333 cycles per bit, 106.666667 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts +;register use in receive loop: +; shift assembles the byte currently being received +; x1 holds the D+ and D- line state +; x2 holds the previous line state +; x4 (leap) is used to add a leap cycle once every three bytes received +; X3 (leap2) is used to add a leap cycle once every three stuff bits received +; bitcnt is used to determine when a stuff bit is due +; cnt holds the number of bytes left in the receive buffer + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt + push YL ;[-28] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-26] + push YL ;[-25] + push YH ;[-23] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-19] + rjmp foundK ;[-18] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-16] +;{3, 5} after falling D- edge, average delay: 4 cycles +;bit0 should be at 34 for center sampling. Currently at 4 so 30 cylces till bit 0 sample +;use 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push bitcnt ;[-16] +; [---] ;[-15] + lds YL, usbInputBufOffset;[-14] +; [---] ;[-13] + clr YH ;[-12] + subi YL, lo8(-(usbRxBuf));[-11] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-10] [rx loop init] + push shift ;[-9] +; [---] ;[-8] + ldi shift,0x40 ;[-7] set msb to "1" so processing bit7 can be detected + nop2 ;[-6] +; [---] ;[-5] + ldi bitcnt, 5 ;[-4] [rx loop init] + sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) + rjmp haveTwoBitsK ;[-2] + pop shift ;[-1] undo the push from before + pop bitcnt ;[1] + rjmp waitForK ;[3] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 27 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[0] + push x2 ;[2] + push x3 ;[4] (leap2) + ldi leap2, 0x55 ;[6] add leap cycle on 2nd,5th,8th,... stuff bit + push x4 ;[7] == leap + ldi leap, 0x55 ;[9] skip leap cycle on 2nd,5th,8th,... byte received + push cnt ;[10] + ldi cnt, USB_BUFSIZE ;[12] [rx loop init] + ldi x2, 1< +#ifndef __IAR_SYSTEMS_ASM__ +# include +#endif + +#define __attribute__(arg) /* not supported on IAR */ + +#ifdef __IAR_SYSTEMS_ASM__ +# define __ASSEMBLER__ /* IAR does not define standard macro for asm */ +#endif + +#ifdef __HAS_ELPM__ +# define PROGMEM __farflash +#else +# define PROGMEM __flash +#endif + +#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr)) + +/* The following definitions are not needed by the driver, but may be of some + * help if you port a gcc based project to IAR. + */ +#define cli() __disable_interrupt() +#define sei() __enable_interrupt() +#define wdt_reset() __watchdog_reset() +#define _BV(x) (1 << (x)) + +/* assembler compatibility macros */ +#define nop2 rjmp $+2 /* jump to next instruction */ +#define XL r26 +#define XH r27 +#define YL r28 +#define YH r29 +#define ZL r30 +#define ZH r31 +#define lo8(x) LOW(x) +#define hi8(x) (((x)>>8) & 0xff) /* not HIGH to allow XLINK to make a proper range check */ + +/* Depending on the device you use, you may get problems with the way usbdrv.h + * handles the differences between devices. Since IAR does not use #defines + * for MCU registers, we can't check for the existence of a particular + * register with an #ifdef. If the autodetection mechanism fails, include + * definitions for the required USB_INTR_* macros in your usbconfig.h. See + * usbconfig-prototype.h and usbdrv.h for details. + */ + +/* ------------------------------------------------------------------------- */ +#elif __CODEVISIONAVR__ /* check for CodeVision AVR */ +/* ------------------------------------------------------------------------- */ +/* This port is not working (yet) */ + +/* #define F_CPU _MCU_CLOCK_FREQUENCY_ seems to be defined automatically */ + +#include +#include + +#define __attribute__(arg) /* not supported on IAR */ + +#define PROGMEM __flash +#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr)) + +#ifndef __ASSEMBLER__ +static inline void cli(void) +{ + #asm("cli"); +} +static inline void sei(void) +{ + #asm("sei"); +} +#endif +#define _delay_ms(t) delay_ms(t) +#define _BV(x) (1 << (x)) +#define USB_CFG_USE_SWITCH_STATEMENT 1 /* macro for if() cascase fails for unknown reason */ + +#define macro .macro +#define endm .endmacro +#define nop2 rjmp .+0 /* jump to next instruction */ + +/* ------------------------------------------------------------------------- */ +#else /* default development environment is avr-gcc/avr-libc */ +/* ------------------------------------------------------------------------- */ + +#include +#ifdef __ASSEMBLER__ +# define _VECTOR(N) __vector_ ## N /* io.h does not define this for asm */ +#else +# include +#endif + +#define USB_READ_FLASH(addr) pgm_read_byte(addr) + +#define macro .macro +#define endm .endm +#define nop2 rjmp .+0 /* jump to next instruction */ + +#endif /* development environment */ + +/* for conveniecne, ensure that PRG_RDB exists */ +#ifndef PRG_RDB +# define PRG_RDB(addr) USB_READ_FLASH(addr) +#endif +#endif /* __usbportability_h_INCLUDED__ */ diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/ArduinoNotes.txt b/hardware/digistump/avr/libraries/DigisparkKeyboard/ArduinoNotes.txt new file mode 100644 index 0000000..e05398b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/ArduinoNotes.txt @@ -0,0 +1,34 @@ +Notes On Integrating AVRUSB with Arduino +======================================== + +* Note the license(s) under which AVRUSB is distributed. + +* See also: http://code.rancidbacon.com/ProjectLogArduinoUSB + +* Note: The pins we use on the PCB (not protoboard) hardware shield are: + + INT0 == PD2 == IC Pin 4 == Arduino Digital Pin 2 == D+ + + ---- == PD4 == -------- == Arduino Digital Pin 4 == D- + + ---- == PD5 == -------- == Arduino Digital Pin 5 == pull-up + + (DONE: Change to not use PD3 so INT1 is left free?) + +* In order to compile a valid 'usbconfig.h' file must exit. The content of this + file will vary depending on whether the device is a generic USB device, + generic HID device or specific class of HID device for example. + + The file 'usbconfig-prototype.h' can be used as a starting point, however + it might be easier to use the 'usbconfig.h' from one of the example projects. + + TODO: Specify the settings that need to be changed to match the shield + design we use. + +* (NOTE: Initial 'usbconfig.h' used will be based on the file from + 'HIDKeys.2007-03-29'.) (Note: Have now upgraded to V-USB 2009-08-22.) + +* Versions of the Arduino IDE prior to 0018 won't compile our library + so it needs to be pre-compiled with: + + avr-g++ -Wall -Os -I. -DF_CPU=16000000 -mmcu=atmega168 -c usbdrvasm.S -c usbdrv.c diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/Changelog.txt b/hardware/digistump/avr/libraries/DigisparkKeyboard/Changelog.txt new file mode 100644 index 0000000..655a9d4 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/Changelog.txt @@ -0,0 +1,296 @@ +This file documents changes in the firmware-only USB driver for atmel's AVR +microcontrollers. New entries are always appended to the end of the file. +Scroll down to the bottom to see the most recent changes. + +2005-04-01: + - Implemented endpoint 1 as interrupt-in endpoint. + - Moved all configuration options to usbconfig.h which is not part of the + driver. + - Changed interface for usbVendorSetup(). + - Fixed compatibility with ATMega8 device. + - Various minor optimizations. + +2005-04-11: + - Changed interface to application: Use usbFunctionSetup(), usbFunctionRead() + and usbFunctionWrite() now. Added configuration options to choose which + of these functions to compile in. + - Assembler module delivers receive data non-inverted now. + - Made register and bit names compatible with more AVR devices. + +2005-05-03: + - Allow address of usbRxBuf on any memory page as long as the buffer does + not cross 256 byte page boundaries. + - Better device compatibility: works with Mega88 now. + - Code optimization in debugging module. + - Documentation updates. + +2006-01-02: + - Added (free) default Vendor- and Product-IDs bought from voti.nl. + - Added USBID-License.txt file which defines the rules for using the free + shared VID/PID pair. + - Added Readme.txt to the usbdrv directory which clarifies administrative + issues. + +2006-01-25: + - Added "configured state" to become more standards compliant. + - Added "HALT" state for interrupt endpoint. + - Driver passes the "USB Command Verifier" test from usb.org now. + - Made "serial number" a configuration option. + - Minor optimizations, we now recommend compiler option "-Os" for best + results. + - Added a version number to usbdrv.h + +2006-02-03: + - New configuration variable USB_BUFFER_SECTION for the memory section where + the USB rx buffer will go. This defaults to ".bss" if not defined. Since + this buffer MUST NOT cross 256 byte pages (not even touch a page at the + end), the user may want to pass a linker option similar to + "-Wl,--section-start=.mybuffer=0x800060". + - Provide structure for usbRequest_t. + - New defines for USB constants. + - Prepared for HID implementations. + - Increased data size limit for interrupt transfers to 8 bytes. + - New macro usbInterruptIsReady() to query interrupt buffer state. + +2006-02-18: + - Ensure that the data token which is sent as an ack to an OUT transfer is + always zero sized. This fixes a bug where the host reports an error after + sending an out transfer to the device, although all data arrived at the + device. + - Updated docs in usbdrv.h to reflect changed API in usbFunctionWrite(). + +* Release 2006-02-20 + + - Give a compiler warning when compiling with debugging turned on. + - Added Oleg Semyonov's changes for IAR-cc compatibility. + - Added new (optional) functions usbDeviceConnect() and usbDeviceDisconnect() + (also thanks to Oleg!). + - Rearranged tests in usbPoll() to save a couple of instructions in the most + likely case that no actions are pending. + - We need a delay between the SET ADDRESS request until the new address + becomes active. This delay was handled in usbPoll() until now. Since the + spec says that the delay must not exceed 2ms, previous versions required + aggressive polling during the enumeration phase. We have now moved the + handling of the delay into the interrupt routine. + - We must not reply with NAK to a SETUP transaction. We can only achieve this + by making sure that the rx buffer is empty when SETUP tokens are expected. + We therefore don't pass zero sized data packets from the status phase of + a transfer to usbPoll(). This change MAY cause troubles if you rely on + receiving a less than 8 bytes long packet in usbFunctionWrite() to + identify the end of a transfer. usbFunctionWrite() will NEVER be called + with a zero length. + +* Release 2006-03-14 + + - Improved IAR C support: tiny memory model, more devices + - Added template usbconfig.h file under the name usbconfig-prototype.h + +* Release 2006-03-26 + + - Added provision for one more interrupt-in endpoint (endpoint 3). + - Added provision for one interrupt-out endpoint (endpoint 1). + - Added flowcontrol macros for USB. + - Added provision for custom configuration descriptor. + - Allow ANY two port bits for D+ and D-. + - Merged (optional) receive endpoint number into global usbRxToken variable. + - Use USB_CFG_IOPORTNAME instead of USB_CFG_IOPORT. We now construct the + variable name from the single port letter instead of computing the address + of related ports from the output-port address. + +* Release 2006-06-26 + + - Updated documentation in usbdrv.h and usbconfig-prototype.h to reflect the + new features. + - Removed "#warning" directives because IAR does not understand them. Use + unused static variables instead to generate a warning. + - Do not include when compiling with IAR. + - Introduced USB_CFG_DESCR_PROPS_* in usbconfig.h to configure how each + USB descriptor should be handled. It is now possible to provide descriptor + data in Flash, RAM or dynamically at runtime. + - STALL is now a status in usbTxLen* instead of a message. We can now conform + to the spec and leave the stall status pending until it is cleared. + - Made usbTxPacketCnt1 and usbTxPacketCnt3 public. This allows the + application code to reset data toggling on interrupt pipes. + +* Release 2006-07-18 + + - Added an #if !defined __ASSEMBLER__ to the warning in usbdrv.h. This fixes + an assembler error. + - usbDeviceDisconnect() takes pull-up resistor to high impedance now. + +* Release 2007-02-01 + + - Merged in some code size improvements from usbtiny (thanks to Dick + Streefland for these optimizations!) + - Special alignment requirement for usbRxBuf not required any more. Thanks + again to Dick Streefland for this hint! + - Reverted to "#warning" instead of unused static variables -- new versions + of IAR CC should handle this directive. + - Changed Open Source license to GNU GPL v2 in order to make linking against + other free libraries easier. We no longer require publication of the + circuit diagrams, but we STRONGLY encourage it. If you improve the driver + itself, PLEASE grant us a royalty free license to your changes for our + commercial license. + +* Release 2007-03-29 + + - New configuration option "USB_PUBLIC" in usbconfig.h. + - Set USB version number to 1.10 instead of 1.01. + - Code used USB_CFG_DESCR_PROPS_STRING_DEVICE and + USB_CFG_DESCR_PROPS_STRING_PRODUCT inconsistently. Changed all occurrences + to USB_CFG_DESCR_PROPS_STRING_PRODUCT. + - New assembler module for 16.5 MHz RC oscillator clock with PLL in receiver + code. + - New assembler module for 16 MHz crystal. + - usbdrvasm.S contains common code only, clock-specific parts have been moved + to usbdrvasm12.S, usbdrvasm16.S and usbdrvasm165.S respectively. + +* Release 2007-06-25 + + - 16 MHz module: Do SE0 check in stuffed bits as well. + +* Release 2007-07-07 + + - Define hi8(x) for IAR compiler to limit result to 8 bits. This is necessary + for negative values. + - Added 15 MHz module contributed by V. Bosch. + - Interrupt vector name can now be configured. This is useful if somebody + wants to use a different hardware interrupt than INT0. + +* Release 2007-08-07 + + - Moved handleIn3 routine in usbdrvasm16.S so that relative jump range is + not exceeded. + - More config options: USB_RX_USER_HOOK(), USB_INITIAL_DATATOKEN, + USB_COUNT_SOF + - USB_INTR_PENDING can now be a memory address, not just I/O + +* Release 2007-09-19 + + - Split out common parts of assembler modules into separate include file + - Made endpoint numbers configurable so that given interface definitions + can be matched. See USB_CFG_EP3_NUMBER in usbconfig-prototype.h. + - Store endpoint number for interrupt/bulk-out so that usbFunctionWriteOut() + can handle any number of endpoints. + - Define usbDeviceConnect() and usbDeviceDisconnect() even if no + USB_CFG_PULLUP_IOPORTNAME is defined. Directly set D+ and D- to 0 in this + case. + +* Release 2007-12-01 + + - Optimize usbDeviceConnect() and usbDeviceDisconnect() for less code size + when USB_CFG_PULLUP_IOPORTNAME is not defined. + +* Release 2007-12-13 + + - Renamed all include-only assembler modules from *.S to *.inc so that + people don't add them to their project sources. + - Distribute leap bits in tx loop more evenly for 16 MHz module. + - Use "macro" and "endm" instead of ".macro" and ".endm" for IAR + - Avoid compiler warnings for constant expr range by casting some values in + USB descriptors. + +* Release 2008-01-21 + + - Fixed bug in 15 and 16 MHz module where the new address set with + SET_ADDRESS was already accepted at the next NAK or ACK we send, not at + the next data packet we send. This caused problems when the host polled + too fast. Thanks to Alexander Neumann for his help and patience debugging + this issue! + +* Release 2008-02-05 + + - Fixed bug in 16.5 MHz module where a register was used in the interrupt + handler before it was pushed. This bug was introduced with version + 2007-09-19 when common parts were moved to a separate file. + - Optimized CRC routine (thanks to Reimar Doeffinger). + +* Release 2008-02-16 + + - Removed outdated IAR compatibility stuff (code sections). + - Added hook macros for USB_RESET_HOOK() and USB_SET_ADDRESS_HOOK(). + - Added optional routine usbMeasureFrameLength() for calibration of the + internal RC oscillator. + +* Release 2008-02-28 + + - USB_INITIAL_DATATOKEN defaults to USBPID_DATA1 now, which means that we + start with sending USBPID_DATA0. + - Changed defaults in usbconfig-prototype.h + - Added free USB VID/PID pair for MIDI class devices + - Restructured AVR-USB as separate package, not part of PowerSwitch any more. + +* Release 2008-04-18 + + - Restructured usbdrv.c so that it is easier to read and understand. + - Better code optimization with gcc 4. + - If a second interrupt in endpoint is enabled, also add it to config + descriptor. + - Added config option for long transfers (above 254 bytes), see + USB_CFG_LONG_TRANSFERS in usbconfig.h. + - Added 20 MHz module contributed by Jeroen Benschop. + +* Release 2008-05-13 + + - Fixed bug in libs-host/hiddata.c function usbhidGetReport(): length + was not incremented, pointer to length was incremented instead. + - Added code to command line tool(s) which claims an interface. This code + is disabled by default, but may be necessary on newer Linux kernels. + - Added usbconfig.h option "USB_CFG_CHECK_DATA_TOGGLING". + - New header "usbportability.h" prepares ports to other development + environments. + - Long transfers (above 254 bytes) did not work when usbFunctionRead() was + used to supply the data. Fixed this bug. [Thanks to Alexander Neumann!] + - In hiddata.c (example code for sending/receiving data over HID), use + USB_RECIP_DEVICE instead of USB_RECIP_INTERFACE for control transfers so + that we need not claim the interface. + - in usbPoll() loop 20 times polling for RESET state instead of 10 times. + This accounts for the higher clock rates we now support. + - Added a module for 12.8 MHz RC oscillator with PLL in receiver loop. + - Added hook to SOF code so that oscillator can be tuned to USB frame clock. + - Added timeout to waitForJ loop. Helps preventing unexpected hangs. + - Added example code for oscillator tuning to libs-device (thanks to + Henrik Haftmann for the idea to this routine). + - Implemented option USB_CFG_SUPPRESS_INTR_CODE. + +* Release 2008-10-22 + + - Fixed libs-device/osctune.h: OSCCAL is memory address on ATMega88 and + similar, not offset of 0x20 needs to be added. + - Allow distribution under GPLv3 for those who have to link against other + code distributed under GPLv3. + +* Release 2008-11-26 + + - Removed libusb-win32 dependency for hid-data example in Makefile.windows. + It was never required and confused many people. + - Added extern uchar usbRxToken to usbdrv.h. + - Integrated a module with CRC checks at 18 MHz by Lukas Schrittwieser. + +* Release 2009-03-23 + + - Hid-mouse example used settings from hid-data example, fixed that. + - Renamed project to V-USB due to a trademark issue with Atmel(r). + - Changed CommercialLicense.txt and USBID-License.txt to make the + background of USB ID registration clearer. + +* Release 2009-04-15 + + - Changed CommercialLicense.txt to reflect the new range of PIDs from + Jason Kotzin. + - Removed USBID-License.txt in favor of USB-IDs-for-free.txt and + USB-ID-FAQ.txt + - Fixed a bug in the 12.8 MHz module: End Of Packet decection was made in + the center between bit 0 and 1 of each byte. This is where the data lines + are expected to change and the sampled data may therefore be nonsense. + We therefore check EOP ONLY if bits 0 AND 1 have both been read as 0 on D-. + - Fixed a bitstuffing problem in the 16 MHz module: If bit 6 was stuffed, + the unstuffing code in the receiver routine was 1 cycle too long. If + multiple bytes had the unstuffing in bit 6, the error summed up until the + receiver was out of sync. + - Included option for faster CRC routine. + Thanks to Slawomir Fras (BoskiDialer) for this code! + - Updated bits in Configuration Descriptor's bmAttributes according to + USB 1.1 (in particular bit 7, it is a must-be-set bit now). + +* Release 2009-08-22 diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/CommercialLicense.txt b/hardware/digistump/avr/libraries/DigisparkKeyboard/CommercialLicense.txt new file mode 100644 index 0000000..11d07d9 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/CommercialLicense.txt @@ -0,0 +1,166 @@ +V-USB Driver Software License Agreement +Version 2009-08-03 + +THIS LICENSE AGREEMENT GRANTS YOU CERTAIN RIGHTS IN A SOFTWARE. YOU CAN +ENTER INTO THIS AGREEMENT AND ACQUIRE THE RIGHTS OUTLINED BELOW BY PAYING +THE AMOUNT ACCORDING TO SECTION 4 ("PAYMENT") TO OBJECTIVE DEVELOPMENT. + + +1 DEFINITIONS + +1.1 "OBJECTIVE DEVELOPMENT" shall mean OBJECTIVE DEVELOPMENT Software GmbH, +Grosse Schiffgasse 1A/7, 1020 Wien, AUSTRIA. + +1.2 "You" shall mean the Licensee. + +1.3 "V-USB" shall mean all files included in the package distributed under +the name "vusb" by OBJECTIVE DEVELOPMENT (http://www.obdev.at/vusb/) +unless otherwise noted. This includes the firmware-only USB device +implementation for Atmel AVR microcontrollers, some simple device examples +and host side software examples and libraries. + + +2 LICENSE GRANTS + +2.1 Source Code. OBJECTIVE DEVELOPMENT shall furnish you with the source +code of V-USB. + +2.2 Distribution and Use. OBJECTIVE DEVELOPMENT grants you the +non-exclusive right to use, copy and distribute V-USB with your hardware +product(s), restricted by the limitations in section 3 below. + +2.3 Modifications. OBJECTIVE DEVELOPMENT grants you the right to modify +the source code and your copy of V-USB according to your needs. + +2.4 USB IDs. OBJECTIVE DEVELOPMENT furnishes you with one or two USB +Product ID(s), sent to you in e-mail. These Product IDs are reserved +exclusively for you. OBJECTIVE DEVELOPMENT has obtained USB Product ID +ranges under the Vendor ID 5824 from Wouter van Ooijen (Van Ooijen +Technische Informatica, www.voti.nl) and under the Vendor ID 8352 from +Jason Kotzin (Clay Logic, www.claylogic.com). Both owners of the Vendor IDs +have obtained these IDs from the USB Implementers Forum, Inc. +(www.usb.org). OBJECTIVE DEVELOPMENT disclaims all liability which might +arise from the assignment of USB IDs. + +2.5 USB Certification. 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This Agreement shall continue indefinitely. However, OBJECTIVE +DEVELOPMENT may terminate this Agreement and revoke the granted license and +USB-IDs if you fail to comply with any of its terms and conditions. + +6.2 Survival of Terms. All provisions regarding secrecy, confidentiality +and limitation of liability shall survive termination of this agreement. + + +7 DISCLAIMER OF WARRANTY AND LIABILITY + +LIMITED WARRANTY. V-USB IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY +KIND. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, OBJECTIVE +DEVELOPMENT AND ITS SUPPLIERS HEREBY DISCLAIM ALL WARRANTIES, EITHER +EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND +NON-INFRINGEMENT, WITH REGARD TO V-USB, AND THE PROVISION OF OR FAILURE +TO PROVIDE SUPPORT SERVICES. THIS LIMITED WARRANTY GIVES YOU SPECIFIC LEGAL +RIGHTS. YOU MAY HAVE OTHERS, WHICH VARY FROM STATE/JURISDICTION TO +STATE/JURISDICTION. + +LIMITATION OF LIABILITY. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, +IN NO EVENT SHALL OBJECTIVE DEVELOPMENT OR ITS SUPPLIERS BE LIABLE FOR ANY +SPECIAL, INCIDENTAL, INDIRECT, OR CONSEQUENTIAL DAMAGES WHATSOEVER +(INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, +BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR ANY OTHER PECUNIARY +LOSS) ARISING OUT OF THE USE OF OR INABILITY TO USE V-USB OR THE +PROVISION OF OR FAILURE TO PROVIDE SUPPORT SERVICES, EVEN IF OBJECTIVE +DEVELOPMENT HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN ANY +CASE, OBJECTIVE DEVELOPMENT'S ENTIRE LIABILITY UNDER ANY PROVISION OF THIS +AGREEMENT SHALL BE LIMITED TO THE AMOUNT ACTUALLY PAID BY YOU FOR V-USB. + + +8 MISCELLANEOUS TERMS + +8.1 Marketing. OBJECTIVE DEVELOPMENT has the right to mention for marketing +purposes that you entered into this agreement. + +8.2 Entire Agreement. This document represents the entire agreement between +OBJECTIVE DEVELOPMENT and you. It may only be modified in writing signed by +an authorized representative of both, OBJECTIVE DEVELOPMENT and you. + +8.3 Severability. In case a provision of these terms and conditions should +be or become partly or entirely invalid, ineffective, or not executable, +the validity of all other provisions shall not be affected. + +8.4 Applicable Law. This agreement is governed by the laws of the Republic +of Austria. + +8.5 Responsible Courts. The responsible courts in Vienna/Austria will have +exclusive jurisdiction regarding all disputes in connection with this +agreement. + diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/DigiKeyboard.h b/hardware/digistump/avr/libraries/DigisparkKeyboard/DigiKeyboard.h new file mode 100644 index 0000000..e9cff46 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/DigiKeyboard.h @@ -0,0 +1,250 @@ +/* + * Based on Obdev's AVRUSB code and under the same license. + * + * TODO: Make a proper file header. :-) + * Modified for Digispark by Digistump + */ +#ifndef __DigiKeyboard_h__ +#define __DigiKeyboard_h__ + +#include +#include +#include +#include +#include + +#include "usbdrv.h" +#include "scancode-ascii-table.h" + +// TODO: Work around Arduino 12 issues better. +//#include +//#undef int() + +typedef uint8_t byte; + + +#define BUFFER_SIZE 2 // Minimum of 2: 1 for modifiers + 1 for keystroke + + +static uchar idleRate; // in 4 ms units + + +/* We use a simplifed keyboard report descriptor which does not support the + * boot protocol. We don't allow setting status LEDs and but we do allow + * simultaneous key presses. + * The report descriptor has been created with usb.org's "HID Descriptor Tool" + * which can be downloaded from http://www.usb.org/developers/hidpage/. + * Redundant entries (such as LOGICAL_MINIMUM and USAGE_PAGE) have been omitted + * for the second INPUT item. + */ +const PROGMEM char usbHidReportDescriptor[USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH] = { /* USB report descriptor */ + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x06, // USAGE (Keyboard) + 0xa1, 0x01, // COLLECTION (Application) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + 0x19, 0xe0, // USAGE_MINIMUM (Keyboard LeftControl) + 0x29, 0xe7, // USAGE_MAXIMUM (Keyboard Right GUI) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x75, 0x01, // REPORT_SIZE (1) + 0x95, 0x08, // REPORT_COUNT (8) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (simultaneous keystrokes) + 0x75, 0x08, // REPORT_SIZE (8) + 0x25, 0x65, // LOGICAL_MAXIMUM (101) + 0x19, 0x00, // USAGE_MINIMUM (Reserved (no event indicated)) + 0x29, 0x65, // USAGE_MAXIMUM (Keyboard Application) + 0x81, 0x00, // INPUT (Data,Ary,Abs) + 0xc0 // END_COLLECTION +}; + + + +/* Keyboard usage values, see usb.org's HID-usage-tables document, chapter + * 10 Keyboard/Keypad Page for more codes. + */ +#define MOD_CONTROL_LEFT (1<<0) +#define MOD_SHIFT_LEFT (1<<1) +#define MOD_ALT_LEFT (1<<2) +#define MOD_GUI_LEFT (1<<3) +#define MOD_CONTROL_RIGHT (1<<4) +#define MOD_SHIFT_RIGHT (1<<5) +#define MOD_ALT_RIGHT (1<<6) +#define MOD_GUI_RIGHT (1<<7) + +#define KEY_A 4 +#define KEY_B 5 +#define KEY_C 6 +#define KEY_D 7 +#define KEY_E 8 +#define KEY_F 9 +#define KEY_G 10 +#define KEY_H 11 +#define KEY_I 12 +#define KEY_J 13 +#define KEY_K 14 +#define KEY_L 15 +#define KEY_M 16 +#define KEY_N 17 +#define KEY_O 18 +#define KEY_P 19 +#define KEY_Q 20 +#define KEY_R 21 +#define KEY_S 22 +#define KEY_T 23 +#define KEY_U 24 +#define KEY_V 25 +#define KEY_W 26 +#define KEY_X 27 +#define KEY_Y 28 +#define KEY_Z 29 +#define KEY_1 30 +#define KEY_2 31 +#define KEY_3 32 +#define KEY_4 33 +#define KEY_5 34 +#define KEY_6 35 +#define KEY_7 36 +#define KEY_8 37 +#define KEY_9 38 +#define KEY_0 39 + +#define KEY_ENTER 40 + +#define KEY_SPACE 44 + +#define KEY_F1 58 +#define KEY_F2 59 +#define KEY_F3 60 +#define KEY_F4 61 +#define KEY_F5 62 +#define KEY_F6 63 +#define KEY_F7 64 +#define KEY_F8 65 +#define KEY_F9 66 +#define KEY_F10 67 +#define KEY_F11 68 +#define KEY_F12 69 + +#define KEY_ARROW_LEFT 0x50 + + +class DigiKeyboardDevice : public Print { + public: + DigiKeyboardDevice () { + cli(); + usbDeviceDisconnect(); + _delay_ms(250); + usbDeviceConnect(); + + + usbInit(); + + sei(); + + // TODO: Remove the next two lines once we fix + // missing first keystroke bug properly. + memset(reportBuffer, 0, sizeof(reportBuffer)); + usbSetInterrupt(reportBuffer, sizeof(reportBuffer)); + } + + void update() { + usbPoll(); + } + + // delay while updating until we are finished delaying + void delay(long milli) { + unsigned long last = millis(); + while (milli > 0) { + unsigned long now = millis(); + milli -= now - last; + last = now; + update(); + } + } + + void sendKeyStroke(byte keyStroke) { + sendKeyStroke(keyStroke, 0); + } + + void sendKeyStroke(byte keyStroke, byte modifiers) { + while (!usbInterruptIsReady()) { + // Note: We wait until we can send keystroke + // so we know the previous keystroke was + // sent. + usbPoll(); + _delay_ms(5); + } + + memset(reportBuffer, 0, sizeof(reportBuffer)); + + reportBuffer[0] = modifiers; + reportBuffer[1] = keyStroke; + + usbSetInterrupt(reportBuffer, sizeof(reportBuffer)); + + while (!usbInterruptIsReady()) { + // Note: We wait until we can send keystroke + // so we know the previous keystroke was + // sent. + usbPoll(); + _delay_ms(5); + } + + // This stops endlessly repeating keystrokes: + memset(reportBuffer, 0, sizeof(reportBuffer)); + usbSetInterrupt(reportBuffer, sizeof(reportBuffer)); + } + + size_t write(uint8_t chr) { + uint8_t data = pgm_read_byte_near(ascii_to_scan_code_table + (chr - 8)); + sendKeyStroke(data & 0b01111111, data >> 7 ? MOD_SHIFT_RIGHT : 0); + return 1; + } + + //private: TODO: Make friend? + uchar reportBuffer[2]; // buffer for HID reports [ 1 modifier byte + (len-1) key strokes] + using Print::write; +}; + +DigiKeyboardDevice DigiKeyboard = DigiKeyboardDevice(); + +#ifdef __cplusplus +extern "C"{ +#endif + // USB_PUBLIC uchar usbFunctionSetup + uchar usbFunctionSetup(uchar data[8]) { + usbRequest_t *rq = (usbRequest_t *)((void *)data); + + usbMsgPtr = DigiKeyboard.reportBuffer; // + if ((rq->bmRequestType & USBRQ_TYPE_MASK) == USBRQ_TYPE_CLASS) { + /* class request type */ + + if (rq->bRequest == USBRQ_HID_GET_REPORT) { + /* wValue: ReportType (highbyte), ReportID (lowbyte) */ + + /* we only have one report type, so don't look at wValue */ + // TODO: Ensure it's okay not to return anything here? + return 0; + + } else if (rq->bRequest == USBRQ_HID_GET_IDLE) { + //usbMsgPtr = &idleRate; + //return 1; + return 0; + + } else if (rq->bRequest == USBRQ_HID_SET_IDLE) { + idleRate = rq->wValue.bytes[1]; + + } + } else { + /* no vendor specific requests implemented */ + } + + return 0; + } +#ifdef __cplusplus +} // extern "C" +#endif + + +#endif // __DigiKeyboard_h__ diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/License.txt b/hardware/digistump/avr/libraries/DigisparkKeyboard/License.txt new file mode 100644 index 0000000..4460cfb --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/License.txt @@ -0,0 +1,361 @@ +OBJECTIVE DEVELOPMENT GmbH's V-USB driver software is distributed under the +terms and conditions of the GNU GPL version 2 or the GNU GPL version 3. It is +your choice whether you apply the terms of version 2 or version 3. The full +text of GPLv2 is included below. In addition to the requirements in the GPL, +we STRONGLY ENCOURAGE you to do the following: + +(1) Publish your entire project on a web site and drop us a note with the URL. +Use the form at http://www.obdev.at/vusb/feedback.html for your submission. + +(2) Adhere to minimum publication standards. Please include AT LEAST: + - a circuit diagram in PDF, PNG or GIF format + - full source code for the host software + - a Readme.txt file in ASCII format which describes the purpose of the + project and what can be found in which directories and which files + - a reference to http://www.obdev.at/vusb/ + +(3) If you improve the driver firmware itself, please give us a free license +to your modifications for our commercial license offerings. + + + + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/Readme.txt b/hardware/digistump/avr/libraries/DigisparkKeyboard/Readme.txt new file mode 100644 index 0000000..a010d97 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/Readme.txt @@ -0,0 +1,158 @@ +This is the Readme file to Objective Development's firmware-only USB driver +for Atmel AVR microcontrollers. For more information please visit +http://www.obdev.at/vusb/ + +This directory contains the USB firmware only. Copy it as-is to your own +project and add all .c and .S files to your project (these files are marked +with an asterisk in the list below). Then copy usbconfig-prototype.h as +usbconfig.h to your project and edit it according to your configuration. + + +TECHNICAL DOCUMENTATION +======================= +The technical documentation (API) for the firmware driver is contained in the +file "usbdrv.h". Please read all of it carefully! Configuration options are +documented in "usbconfig-prototype.h". + +The driver consists of the following files: + Readme.txt ............. The file you are currently reading. + Changelog.txt .......... Release notes for all versions of the driver. + usbdrv.h ............... Driver interface definitions and technical docs. +* usbdrv.c ............... High level language part of the driver. Link this + module to your code! +* usbdrvasm.S ............ Assembler part of the driver. This module is mostly + a stub and includes one of the usbdrvasm*.S files + depending on processor clock. Link this module to + your code! + usbdrvasm*.inc ......... Assembler routines for particular clock frequencies. + Included by usbdrvasm.S, don't link it directly! + asmcommon.inc .......... Common assembler routines. Included by + usbdrvasm*.inc, don't link it directly! + usbconfig-prototype.h .. Prototype for your own usbdrv.h file. +* oddebug.c .............. Debug functions. Only used when DEBUG_LEVEL is + defined to a value greater than 0. Link this module + to your code! + oddebug.h .............. Interface definitions of the debug module. + usbportability.h ....... Header with compiler-dependent stuff. + usbdrvasm.asm .......... Compatibility stub for IAR-C-compiler. Use this + module instead of usbdrvasm.S when you assembler + with IAR's tools. + License.txt ............ Open Source license for this driver. + CommercialLicense.txt .. Optional commercial license for this driver. + USB-ID-FAQ.txt ......... General infos about USB Product- and Vendor-IDs. + USB-IDs-for-free.txt ... List and terms of use for free shared PIDs. + +(*) ... These files should be linked to your project. + + +CPU CORE CLOCK FREQUENCY +======================== +We supply assembler modules for clock frequencies of 12 MHz, 12.8 MHz, 15 MHz, +16 MHz, 16.5 MHz 18 MHz and 20 MHz. Other clock rates are not supported. The +actual clock rate must be configured in usbdrv.h unless you use the default +12 MHz. + +12 MHz Clock +This is the traditional clock rate of V-USB because it's the lowest clock +rate where the timing constraints of the USB spec can be met. + +15 MHz Clock +Similar to 12 MHz, but some NOPs inserted. On the other hand, the higher clock +rate allows for some loops which make the resulting code size somewhat smaller +than the 12 MHz version. + +16 MHz Clock +This clock rate has been added for users of the Arduino board and other +ready-made boards which come with a fixed 16 MHz crystal. It's also an option +if you need the slightly higher clock rate for performance reasons. Since +16 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code +is somewhat tricky and has to insert a leap cycle every third byte. + +12.8 MHz and 16.5 MHz Clock +The assembler modules for these clock rates differ from the other modules +because they have been built for an RC oscillator with only 1% precision. The +receiver code inserts leap cycles to compensate for clock deviations. 1% is +also the precision which can be achieved by calibrating the internal RC +oscillator of the AVR. Please note that only AVRs with internal 64 MHz PLL +oscillator can reach 16.5 MHz with the RC oscillator. This includes the very +popular ATTiny25, ATTiny45, ATTiny85 series as well as the ATTiny26. Almost +all AVRs can reach 12.8 MHz, although this is outside the specified range. + +See the EasyLogger example at http://www.obdev.at/vusb/easylogger.html for +code which calibrates the RC oscillator based on the USB frame clock. + +18 MHz Clock +This module is closer to the USB specification because it performs an on the +fly CRC check for incoming packets. Packets with invalid checksum are +discarded as required by the spec. If you also implement checks for data +PID toggling on application level (see option USB_CFG_CHECK_DATA_TOGGLING +in usbconfig.h for more info), this ensures data integrity. Due to the CRC +tables and alignment requirements, this code is bigger than modules for other +clock rates. To activate this module, you must define USB_CFG_CHECK_CRC to 1 +and USB_CFG_CLOCK_KHZ to 18000 in usbconfig.h. + +20 MHz Clock +This module is for people who won't do it with less than the maximum. Since +20 MHz is not divisible by the USB low speed bit clock of 1.5 MHz, the code +uses similar tricks as the 16 MHz module to insert leap cycles. + + +USB IDENTIFIERS +=============== +Every USB device needs a vendor- and a product-identifier (VID and PID). VIDs +are obtained from usb.org for a price of 1,500 USD. Once you have a VID, you +can assign PIDs at will. + +Since an entry level cost of 1,500 USD is too high for most small companies +and hobbyists, we provide some VID/PID pairs for free. See the file +USB-IDs-for-free.txt for details. + +Objective Development also has some license offerings which include product +IDs. See http://www.obdev.at/vusb/ for details. + + +DEVELOPMENT SYSTEM +================== +This driver has been developed and optimized for the GNU compiler version 3 +(gcc 3). It does work well with gcc 4, but with bigger code size. We recommend +that you use the GNU compiler suite because it is freely available. V-USB +has also been ported to the IAR compiler and assembler. It has been tested +with IAR 4.10B/W32 and 4.12A/W32 on an ATmega8 with the "small" and "tiny" +memory model. Not every release is tested with IAR CC and the driver may +therefore fail to compile with IAR. Please note that gcc is more efficient for +usbdrv.c because this module has been deliberately optimized for gcc. + + +USING V-USB FOR FREE +==================== +The AVR firmware driver is published under the GNU General Public License +Version 2 (GPL2) and the GNU General Public License Version 3 (GPL3). It is +your choice whether you apply the terms of version 2 or version 3. + +If you decide for the free GPL2 or GPL3, we STRONGLY ENCOURAGE you to do the +following things IN ADDITION to the obligations from the GPL: + +(1) Publish your entire project on a web site and drop us a note with the URL. +Use the form at http://www.obdev.at/vusb/feedback.html for your submission. +If you don't have a web site, you can publish the project in obdev's +documentation wiki at +http://www.obdev.at/goto.php?t=vusb-wiki&p=hosted-projects. + +(2) Adhere to minimum publication standards. Please include AT LEAST: + - a circuit diagram in PDF, PNG or GIF format + - full source code for the host software + - a Readme.txt file in ASCII format which describes the purpose of the + project and what can be found in which directories and which files + - a reference to http://www.obdev.at/vusb/ + +(3) If you improve the driver firmware itself, please give us a free license +to your modifications for our commercial license offerings. + + +COMMERCIAL LICENSES FOR V-USB +============================= +If you don't want to publish your source code under the terms of the GPL, +you can simply pay money for V-USB. As an additional benefit you get +USB PIDs for free, reserved exclusively to you. See the file +"CommercialLicense.txt" for details. + diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/USB-ID-FAQ.txt b/hardware/digistump/avr/libraries/DigisparkKeyboard/USB-ID-FAQ.txt new file mode 100644 index 0000000..d1de8fb --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/USB-ID-FAQ.txt @@ -0,0 +1,149 @@ +Version 2009-08-22 + +========================== +WHY DO WE NEED THESE IDs? +========================== + +USB is more than a low level protocol for data transport. It also defines a +common set of requests which must be understood by all devices. And as part +of these common requests, the specification defines data structures, the +USB Descriptors, which are used to describe the properties of the device. + +From the perspective of an operating system, it is therefore possible to find +out basic properties of a device (such as e.g. the manufacturer and the name +of the device) without a device-specific driver. This is essential because +the operating system can choose a driver to load based on this information +(Plug-And-Play). + +Among the most important properties in the Device Descriptor are the USB +Vendor- and Product-ID. Both are 16 bit integers. The most simple form of +driver matching is based on these IDs. The driver announces the Vendor- and +Product-IDs of the devices it can handle and the operating system loads the +appropriate driver when the device is connected. + +It is obvious that this technique only works if the pair Vendor- plus +Product-ID is unique: Only devices which require the same driver can have the +same pair of IDs. + + +===================================================== +HOW DOES THE USB STANDARD ENSURE THAT IDs ARE UNIQUE? +===================================================== + +Since it is so important that USB IDs are unique, the USB Implementers Forum, +Inc. (usb.org) needs a way to enforce this legally. It is not forbidden by +law to build a device and assign it any random numbers as IDs. Usb.org +therefore needs an agreement to regulate the use of USB IDs. The agreement +binds only parties who agreed to it, of course. Everybody else is free to use +any numbers for their IDs. + +So how can usb.org ensure that every manufacturer of USB devices enters into +an agreement with them? They do it via trademark licensing. Usb.org has +registered the trademark "USB", all associated logos and related terms. If +you want to put an USB logo on your product or claim that it is USB +compliant, you must license these trademarks from usb.org. And this is where +you enter into an agreement. See the "USB-IF Trademark License Agreement and +Usage Guidelines for the USB-IF Logo" at +http://www.usb.org/developers/logo_license/. + +Licensing the USB trademarks requires that you buy a USB Vendor-ID from +usb.org (one-time fee of ca. 2,000 USD), that you become a member of usb.org +(yearly fee of ca. 4,000 USD) and that you meet all the technical +specifications from the USB spec. + +This means that most hobbyists and small companies will never be able to +become USB compliant, just because membership is so expensive. And you can't +be compliant with a driver based on V-USB anyway, because the AVR's port pins +don't meet the electrical specifications for USB. So, in principle, all +hobbyists and small companies are free to choose any random numbers for their +IDs. They have nothing to lose... + +There is one exception worth noting, though: If you use a sub-component which +implements USB, the vendor of the sub-components may guarantee USB +compliance. This might apply to some or all of FTDI's solutions. + + +======================================================================= +WHY SHOULD YOU OBTAIN USB IDs EVEN IF YOU DON'T LICENSE USB TRADEMARKS? +======================================================================= + +You have learned in the previous section that you are free to choose any +numbers for your IDs anyway. So why not do exactly this? There is still the +technical issue. If you choose IDs which are already in use by somebody else, +operating systems will load the wrong drivers and your device won't work. +Even if you choose IDs which are not currently in use, they may be in use in +the next version of the operating system or even after an automatic update. + +So what you need is a pair of Vendor- and Product-IDs for which you have the +guarantee that no USB compliant product uses them. This implies that no +operating system will ever ship with drivers responsible for these IDs. + + +============================================== +HOW DOES OBJECTIVE DEVELOPMENT HANDLE USB IDs? +============================================== + +Objective Development gives away pairs of USB-IDs with their V-USB licenses. +In order to ensure that these IDs are unique, Objective Development has an +agreement with the company/person who has bought the USB Vendor-ID from +usb.org. This agreement ensures that a range of USB Product-IDs is reserved +for assignment by Objective Development and that the owner of the Vendor-ID +won't give it to anybody else. + +This means that you have to trust three parties to ensure uniqueness of +your IDs: + + - Objective Development, that they don't give the same PID to more than + one person. + - The owner of the Vendor-ID that they don't assign PIDs from the range + assigned to Objective Development to anybody else. + - Usb.org that they don't assign the same Vendor-ID a second time. + + +================================== +WHO IS THE OWNER OF THE VENDOR-ID? +================================== + +Objective Development has obtained ranges of USB Product-IDs under two +Vendor-IDs: Under Vendor-ID 5824 from Wouter van Ooijen (Van Ooijen +Technische Informatica, www.voti.nl) and under Vendor-ID 8352 from Jason +Kotzin (Clay Logic, www.claylogic.com). Both VID owners have received their +Vendor-ID directly from usb.org. + + +========================================================================= +CAN I USE USB-IDs FROM OBJECTIVE DEVELOPMENT WITH OTHER DRIVERS/HARDWARE? +========================================================================= + +The short answer is: Yes. All you get is a guarantee that the IDs are never +assigned to anybody else. What more do you need? + + +============================ +WHAT ABOUT SHARED ID PAIRS? +============================ + +Objective Development has reserved some PID/VID pairs for shared use. You +have no guarantee of uniqueness for them, except that no USB compliant device +uses them. In order to avoid technical problems, we must ensure that all +devices with the same pair of IDs use the same driver on kernel level. For +details, see the file USB-IDs-for-free.txt. + + +====================================================== +I HAVE HEARD THAT SUB-LICENSING OF USB-IDs IS ILLEGAL? +====================================================== + +A 16 bit integer number cannot be protected by copyright laws. It is not +sufficiently complex. And since none of the parties involved entered into the +USB-IF Trademark License Agreement, we are not bound by this agreement. So +there is no reason why it should be illegal to sub-license USB-IDs. + + +============================================= +WHO IS LIABLE IF THERE ARE INCOMPATIBILITIES? +============================================= + +Objective Development disclaims all liabilities which might arise from the +assignment of IDs. If you guarantee product features to your customers +without proper disclaimer, YOU are liable for that. diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/USB-IDs-for-free.txt b/hardware/digistump/avr/libraries/DigisparkKeyboard/USB-IDs-for-free.txt new file mode 100644 index 0000000..2f4d59a --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/USB-IDs-for-free.txt @@ -0,0 +1,148 @@ +Version 2009-08-22 + +=========================== +FREE USB-IDs FOR SHARED USE +=========================== + +Objective Development has reserved a set of USB Product-IDs for use according +to the guidelines outlined below. For more information about the concept of +USB IDs please see the file USB-ID-FAQ.txt. Objective Development guarantees +that the IDs listed below are not used by any USB compliant devices. + + +==================== +MECHANISM OF SHARING +==================== + +From a technical point of view, two different devices can share the same USB +Vendor- and Product-ID if they require the same driver on operating system +level. We make use of this fact by assigning separate IDs for various device +classes. On application layer, devices must be distinguished by their textual +name or serial number. We offer separate sets of IDs for discrimination by +textual name and for serial number. + +Examples for shared use of USB IDs are included with V-USB in the "examples" +subdirectory. + + +====================================== +IDs FOR DISCRIMINATION BY TEXTUAL NAME +====================================== + +If you use one of the IDs listed below, your device and host-side software +must conform to these rules: + +(1) The USB device MUST provide a textual representation of the manufacturer +and product identification. The manufacturer identification MUST be available +at least in USB language 0x0409 (English/US). + +(2) The textual manufacturer identification MUST contain either an Internet +domain name (e.g. "mycompany.com") registered and owned by you, or an e-mail +address under your control (e.g. "myname@gmx.net"). You can embed the domain +name or e-mail address in any string you like, e.g. "Objective Development +http://www.obdev.at/vusb/". + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(4) You may choose any string for the textual product identification, as long +as this string is unique within the scope of your textual manufacturer +identification. + +(5) Application side device look-up MUST be based on the textual manufacturer +and product identification in addition to VID/PID matching. The driver +matching MUST be a comparison of the entire strings, NOT a sub-string match. + +(6) For devices which implement a particular USB device class (e.g. HID), the +operating system's default class driver MUST be used. If an operating system +driver for Vendor Class devices is needed, this driver must be libusb or +libusb-win32 (see http://libusb.org/ and +http://libusb-win32.sourceforge.net/). + +Table if IDs for discrimination by textual name: + +PID dec (hex) | VID dec (hex) | Description of use +==============+===============+============================================ +1500 (0x05dc) | 5824 (0x16c0) | For Vendor Class devices with libusb +--------------+---------------+-------------------------------------------- +1503 (0x05df) | 5824 (0x16c0) | For generic HID class devices (which are + | | NOT mice, keyboards or joysticks) +--------------+---------------+-------------------------------------------- +1505 (0x05e1) | 5824 (0x16c0) | For CDC-ACM class devices (modems) +--------------+---------------+-------------------------------------------- +1508 (0x05e4) | 5824 (0x16c0) | For MIDI class devices +--------------+---------------+-------------------------------------------- + +Note that Windows caches the textual product- and vendor-description for +mice, keyboards and joysticks. Name-bsed discrimination is therefore not +recommended for these device classes. + + +======================================= +IDs FOR DISCRIMINATION BY SERIAL NUMBER +======================================= + +If you use one of the IDs listed below, your device and host-side software +must conform to these rules: + +(1) The USB device MUST provide a textual representation of the serial +number. The serial number string MUST be available at least in USB language +0x0409 (English/US). + +(2) The serial number MUST start with either an Internet domain name (e.g. +"mycompany.com") registered and owned by you, or an e-mail address under your +control (e.g. "myname@gmx.net"), both terminated with a colon (":") character. +You MAY append any string you like for further discrimination of your devices. + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(5) Application side device look-up MUST be based on the serial number string +in addition to VID/PID matching. The matching must start at the first +character of the serial number string and include the colon character +terminating your domain or e-mail address. It MAY stop anywhere after that. + +(6) For devices which implement a particular USB device class (e.g. HID), the +operating system's default class driver MUST be used. If an operating system +driver for Vendor Class devices is needed, this driver must be libusb or +libusb-win32 (see http://libusb.org/ and +http://libusb-win32.sourceforge.net/). + +Table if IDs for discrimination by serial number string: + +PID dec (hex) | VID dec (hex) | Description of use +===============+===============+=========================================== +10200 (0x27d8) | 5824 (0x16c0) | For Vendor Class devices with libusb +---------------+---------------+------------------------------------------- +10201 (0x27d9) | 5824 (0x16c0) | For generic HID class devices (which are + | | NOT mice, keyboards or joysticks) +---------------+---------------+------------------------------------------- +10202 (0x27da) | 5824 (0x16c0) | For USB Mice +---------------+---------------+------------------------------------------- +10203 (0x27db) | 5824 (0x16c0) | For USB Keyboards +---------------+---------------+------------------------------------------- +10204 (0x27db) | 5824 (0x16c0) | For USB Joysticks +---------------+---------------+------------------------------------------- +10205 (0x27dc) | 5824 (0x16c0) | For CDC-ACM class devices (modems) +---------------+---------------+------------------------------------------- +10206 (0x27dd) | 5824 (0x16c0) | For MIDI class devices +---------------+---------------+------------------------------------------- + + +================= +ORIGIN OF USB-IDs +================= + +OBJECTIVE DEVELOPMENT Software GmbH has obtained all VID/PID pairs listed +here from Wouter van Ooijen (see www.voti.nl) for exclusive disposition. +Wouter van Ooijen has obtained the VID from the USB Implementers Forum, Inc. +(see www.usb.org). The VID is registered for the company name "Van Ooijen +Technische Informatica". + + +========== +DISCLAIMER +========== + +OBJECTIVE DEVELOPMENT Software GmbH disclaims all liability for any +problems which are caused by the shared use of these VID/PID pairs. diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/USBID-License.txt b/hardware/digistump/avr/libraries/DigisparkKeyboard/USBID-License.txt new file mode 100644 index 0000000..c40be92 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/USBID-License.txt @@ -0,0 +1,154 @@ +Royalty-Free Non-Exclusive Use of USB Product-IDs +================================================= + +Version 2009-04-13 + +Strictly speaking, this is not a license. You can't give a license to use +a simple number (such as e.g. 1500) for any purpose. This is a set of rules +which should make it possible to build USB devices without the requirement +for individual USB IDs. If you break one of the rules, you will run into +technical problems sooner or later, but you don't risk legal trouble. + + +OBJECTIVE DEVELOPMENT Software GmbH hereby grants you the non-exclusive +right to use four USB.org vendor-ID (VID) / product-ID (PID) pairs with +products based on Objective Development's firmware-only USB driver for +Atmel AVR microcontrollers: + + * VID = 5824 (=0x16c0) / PID = 1500 (=0x5dc) for devices implementing no + USB device class (vendor-class devices with USB class = 0xff). Devices + using this pair will be referred to as "VENDOR CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1503 (=0x5df) for HID class devices + (excluding mice and keyboards). Devices using this pair will be referred + to as "HID CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1505 (=0x5e1) for CDC class modem devices + Devices using this pair will be referred to as "CDC-ACM CLASS" devices. + + * VID = 5824 (=0x16c0) / PID = 1508 (=0x5e4) for MIDI class devices + Devices using this pair will be referred to as "MIDI CLASS" devices. + +Since the granted right is non-exclusive, the same VID/PID pairs may be +used by many companies and individuals for different products. To avoid +conflicts, your device and host driver software MUST adhere to the rules +outlined below. + +OBJECTIVE DEVELOPMENT Software GmbH has obtained these VID/PID pairs from +Wouter van Ooijen (see www.voti.nl) for exclusive disposition. Wouter van +Ooijen has obtained the VID from the USB Implementers Forum, Inc. +(see www.usb.org). The VID is registered for the company name +"Van Ooijen Technische Informatica". + + +RULES AND RESTRICTIONS +====================== + +(1) The USB device MUST provide a textual representation of the +manufacturer and product identification. The manufacturer identification +MUST be available at least in USB language 0x0409 (English/US). + +(2) The textual manufacturer identification MUST contain either an Internet +domain name (e.g. "mycompany.com") registered and owned by you, or an +e-mail address under your control (e.g. "myname@gmx.net"). You can embed +the domain name or e-mail address in any string you like, e.g. "Objective +Development http://www.obdev.at/vusb/". + +(3) You are responsible for retaining ownership of the domain or e-mail +address for as long as any of your products are in use. + +(4) You may choose any string for the textual product identification, as +long as this string is unique within the scope of your textual manufacturer +identification. + +(5) Matching of device-specific drivers MUST be based on the textual +manufacturer and product identification in addition to the usual VID/PID +matching. This means that operating system features which are based on +VID/PID matching only (e.g. Windows kernel level drivers, automatic actions +when the device is plugged in etc) MUST NOT be used. The driver matching +MUST be a comparison of the entire strings, NOT a sub-string match. For +CDC-ACM CLASS and MIDI CLASS devices, a generic class driver should be used +and the matching is based on the USB device class. + +(6) The extent to which VID/PID matching is allowed for non device-specific +drivers or features depends on the operating system and particular VID/PID +pair used: + + * Mac OS X, Linux, FreeBSD and other Unixes: No VID/PID matching is + required and hence no VID/PID-only matching is allowed at all. + + * Windows: The operating system performs VID/PID matching for the kernel + level driver. You are REQUIRED to use libusb-win32 (see + http://libusb-win32.sourceforge.net/) as the kernel level driver for + VENDOR CLASS devices. HID CLASS devices all use the generic HID class + driver shipped with Windows, except mice and keyboards. You therefore + MUST NOT use any of the shared VID/PID pairs for mice or keyboards. + CDC-ACM CLASS devices require a ".inf" file which matches on the VID/PID + pair. This ".inf" file MUST load the "usbser" driver to configure the + device as modem (COM-port). + +(7) OBJECTIVE DEVELOPMENT Software GmbH disclaims all liability for any +problems which are caused by the shared use of these VID/PID pairs. You +have been warned that the sharing of VID/PID pairs may cause problems. If +you want to avoid them, get your own VID/PID pair for exclusive use. + + +HOW TO IMPLEMENT THESE RULES +============================ + +The following rules are for VENDOR CLASS and HID CLASS devices. CDC-ACM +CLASS and MIDI CLASS devices use the operating system's class driver and +don't need a custom driver. + +The host driver MUST iterate over all devices with the given VID/PID +numbers in their device descriptors and query the string representation for +the manufacturer name in USB language 0x0409 (English/US). It MUST compare +the ENTIRE string with your textual manufacturer identification chosen in +(2) above. A substring search for your domain or e-mail address is NOT +acceptable. The driver MUST NOT touch the device (other than querying the +descriptors) unless the strings match. + +For all USB devices with matching VID/PID and textual manufacturer +identification, the host driver must query the textual product +identification and string-compare it with the name of the product it can +control. It may only initialize the device if the product matches exactly. + +Objective Development provides examples for these matching rules with the +"PowerSwitch" project (using libusb) and with the "Automator" project +(using Windows calls on Windows and libusb on Unix). + + +Technical Notes: +================ + +Sharing the same VID/PID pair among devices is possible as long as ALL +drivers which match the VID/PID also perform matching on the textual +identification strings. This is easy on all operating systems except +Windows, since Windows establishes a static connection between the VID/PID +pair and a kernel level driver. All devices with the same VID/PID pair must +therefore use THE SAME kernel level driver. + +We therefore demand that you use libusb-win32 for VENDOR CLASS devices. +This is a generic kernel level driver which allows all types of USB access +for user space applications. This is only a partial solution of the +problem, though, because different device drivers may come with different +versions of libusb-win32 and they may not work with the libusb version of +the respective other driver. You are therefore encouraged to test your +driver against a broad range of libusb-win32 versions. Do not use new +features in new versions, or check for their existence before you use them. +When a new libusb-win32 becomes available, make sure that your driver is +compatible with it. + +For HID CLASS devices it is necessary that all those devices bind to the +same kernel driver: Microsoft's generic USB HID driver. This is true for +all HID devices except those with a specialized driver. Currently, the only +HIDs with specialized drivers are mice and keyboards. You therefore MUST +NOT use a shared VID/PID with mouse and keyboard devices. + +Sharing the same VID/PID among different products is unusual and probably +violates the USB specification. If you do it, you do it at your own risk. + +To avoid possible incompatibilities, we highly recommend that you get your +own VID/PID pair if you intend to sell your product. Objective +Development's commercial licenses for V-USB include a PID for +unrestricted exclusive use. diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/asmcommon.inc b/hardware/digistump/avr/libraries/DigisparkKeyboard/asmcommon.inc new file mode 100644 index 0000000..07d692b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/asmcommon.inc @@ -0,0 +1,188 @@ +/* Name: asmcommon.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2007-11-05 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id$ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file contains assembler code which is shared among the USB driver +implementations for different CPU cocks. Since the code must be inserted +in the middle of the module, it's split out into this file and #included. + +Jump destinations called from outside: + sofError: Called when no start sequence was found. + se0: Called when a package has been successfully received. + overflow: Called when receive buffer overflows. + doReturn: Called after sending data. + +Outside jump destinations used by this module: + waitForJ: Called to receive an already arriving packet. + sendAckAndReti: + sendNakAndReti: + sendCntAndReti: + usbSendAndReti: + +The following macros must be defined before this file is included: + .macro POP_STANDARD + .endm + .macro POP_RETI + .endm +*/ + +#define token x1 + +overflow: + ldi x2, 1< 0 + +#warning "Never compile production devices with debugging enabled" + +static void uartPutc(char c) +{ + while(!(ODDBG_USR & (1 << ODDBG_UDRE))); /* wait for data register empty */ + ODDBG_UDR = c; +} + +static uchar hexAscii(uchar h) +{ + h &= 0xf; + if(h >= 10) + h += 'a' - (uchar)10 - '0'; + h += '0'; + return h; +} + +static void printHex(uchar c) +{ + uartPutc(hexAscii(c >> 4)); + uartPutc(hexAscii(c)); +} + +void odDebug(uchar prefix, uchar *data, uchar len) +{ + printHex(prefix); + uartPutc(':'); + while(len--){ + uartPutc(' '); + printHex(*data++); + } + uartPutc('\r'); + uartPutc('\n'); +} + +#endif diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/oddebug.h b/hardware/digistump/avr/libraries/DigisparkKeyboard/oddebug.h new file mode 100644 index 0000000..d61309d --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/oddebug.h @@ -0,0 +1,123 @@ +/* Name: oddebug.h + * Project: AVR library + * Author: Christian Starkjohann + * Creation Date: 2005-01-16 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: oddebug.h 692 2008-11-07 15:07:40Z cs $ + */ + +#ifndef __oddebug_h_included__ +#define __oddebug_h_included__ + +/* +General Description: +This module implements a function for debug logs on the serial line of the +AVR microcontroller. Debugging can be configured with the define +'DEBUG_LEVEL'. If this macro is not defined or defined to 0, all debugging +calls are no-ops. If it is 1, DBG1 logs will appear, but not DBG2. If it is +2, DBG1 and DBG2 logs will be printed. + +A debug log consists of a label ('prefix') to indicate which debug log created +the output and a memory block to dump in hex ('data' and 'len'). +*/ + + +#ifndef F_CPU +# define F_CPU 12000000 /* 12 MHz */ +#endif + +/* make sure we have the UART defines: */ +#include "usbportability.h" + +#ifndef uchar +# define uchar unsigned char +#endif + +#if DEBUG_LEVEL > 0 && !(defined TXEN || defined TXEN0) /* no UART in device */ +# warning "Debugging disabled because device has no UART" +# undef DEBUG_LEVEL +#endif + +#ifndef DEBUG_LEVEL +# define DEBUG_LEVEL 0 +#endif + +/* ------------------------------------------------------------------------- */ + +#if DEBUG_LEVEL > 0 +# define DBG1(prefix, data, len) odDebug(prefix, data, len) +#else +# define DBG1(prefix, data, len) +#endif + +#if DEBUG_LEVEL > 1 +# define DBG2(prefix, data, len) odDebug(prefix, data, len) +#else +# define DBG2(prefix, data, len) +#endif + +/* ------------------------------------------------------------------------- */ + +#if DEBUG_LEVEL > 0 +extern void odDebug(uchar prefix, uchar *data, uchar len); + +/* Try to find our control registers; ATMEL likes to rename these */ + +#if defined UBRR +# define ODDBG_UBRR UBRR +#elif defined UBRRL +# define ODDBG_UBRR UBRRL +#elif defined UBRR0 +# define ODDBG_UBRR UBRR0 +#elif defined UBRR0L +# define ODDBG_UBRR UBRR0L +#endif + +#if defined UCR +# define ODDBG_UCR UCR +#elif defined UCSRB +# define ODDBG_UCR UCSRB +#elif defined UCSR0B +# define ODDBG_UCR UCSR0B +#endif + +#if defined TXEN +# define ODDBG_TXEN TXEN +#else +# define ODDBG_TXEN TXEN0 +#endif + +#if defined USR +# define ODDBG_USR USR +#elif defined UCSRA +# define ODDBG_USR UCSRA +#elif defined UCSR0A +# define ODDBG_USR UCSR0A +#endif + +#if defined UDRE +# define ODDBG_UDRE UDRE +#else +# define ODDBG_UDRE UDRE0 +#endif + +#if defined UDR +# define ODDBG_UDR UDR +#elif defined UDR0 +# define ODDBG_UDR UDR0 +#endif + +static inline void odDebugInit(void) +{ + ODDBG_UCR |= (1< + +#ifndef uchar +#define uchar unsigned char +#endif + +/* ------------------------------------------------------------------------- */ +/* ------------------------ Oscillator Calibration ------------------------- */ +/* ------------------------------------------------------------------------- */ + +/* Calibrate the RC oscillator. Our timing reference is the Start Of Frame + * signal (a single SE0 bit) repeating every millisecond immediately after + * a USB RESET. We first do a binary search for the OSCCAL value and then + * optimize this value with a neighboorhod search. + */ +void calibrateOscillator(void) +{ +uchar step = 128; +uchar trialValue = 0, optimumValue; +int x, optimumDev, targetValue = (unsigned)(1499 * (double)F_CPU / 10.5e6 + 0.5); + + /* do a binary search: */ + do{ + OSCCAL = trialValue + step; + x = usbMeasureFrameLength(); /* proportional to current real frequency */ + if(x < targetValue) /* frequency still too low */ + trialValue += step; + step >>= 1; + }while(step > 0); + /* We have a precision of +/- 1 for optimum OSCCAL here */ + /* now do a neighborhood search for optimum value */ + optimumValue = trialValue; + optimumDev = x; /* this is certainly far away from optimum */ + for(OSCCAL = trialValue - 1; OSCCAL <= trialValue + 1; OSCCAL++){ + x = usbMeasureFrameLength() - targetValue; + if(x < 0) + x = -x; + if(x < optimumDev){ + optimumDev = x; + optimumValue = OSCCAL; + } + } + OSCCAL = optimumValue; +} +/* +Note: This calibration algorithm may try OSCCAL values of up to 192 even if +the optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +You may replace this search algorithm with any other algorithm you like if +you have additional constraints such as a maximum CPU clock. +For version 5.x RC oscillators (those with a split range of 2x128 steps, e.g. +ATTiny25, ATTiny45, ATTiny85), it may be useful to search for the optimum in +both regions. +*/ diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/osccal.c.lst b/hardware/digistump/avr/libraries/DigisparkKeyboard/osccal.c.lst new file mode 100644 index 0000000..336a049 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/osccal.c.lst @@ -0,0 +1,106 @@ +GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 1 + + + 1 .file "osccal.c" + 2 __SREG__ = 0x3f + 3 __SP_H__ = 0x3e + 4 __SP_L__ = 0x3d + 5 __CCP__ = 0x34 + 6 __tmp_reg__ = 0 + 7 __zero_reg__ = 1 + 8 .text + 9 .global calibrateOscillator + 10 .type calibrateOscillator, @function + 11 calibrateOscillator: + 12 0000 FF92 push r15 + 13 0002 0F93 push r16 + 14 0004 1F93 push r17 + 15 0006 CF93 push r28 + 16 0008 DF93 push r29 + 17 /* prologue: function */ + 18 /* frame size = 0 */ + 19 000a 80E8 ldi r24,lo8(-128) + 20 000c F82E mov r15,r24 + 21 000e 00E0 ldi r16,lo8(0) + 22 0010 C0E0 ldi r28,lo8(0) + 23 0012 D0E0 ldi r29,hi8(0) + 24 .L4: + 25 0014 102F mov r17,r16 + 26 0016 1F0D add r17,r15 + 27 0018 11BF out 81-32,r17 + 28 001a 00D0 rcall usbMeasureFrameLength + 29 001c 29E0 ldi r18,hi8(2356) + 30 001e 8433 cpi r24,lo8(2356) + 31 0020 9207 cpc r25,r18 + 32 0022 04F0 brlt .L2 + 33 0024 102F mov r17,r16 + 34 .L2: + 35 0026 F694 lsr r15 + 36 0028 2196 adiw r28,1 + 37 002a C830 cpi r28,8 + 38 002c D105 cpc r29,__zero_reg__ + 39 002e 01F0 breq .L3 + 40 0030 012F mov r16,r17 + 41 0032 00C0 rjmp .L4 + 42 .L3: + 43 0034 1150 subi r17,lo8(-(-1)) + 44 0036 11BF out 81-32,r17 + 45 0038 1F5F subi r17,lo8(-(1)) + 46 003a 012F mov r16,r17 + 47 003c EC01 movw r28,r24 + 48 003e 00C0 rjmp .L5 + 49 .L8: + 50 0040 00D0 rcall usbMeasureFrameLength + 51 0042 8453 subi r24,lo8(-(-2356)) + 52 0044 9940 sbci r25,hi8(-(-2356)) + 53 0046 97FF sbrs r25,7 + 54 0048 00C0 rjmp .L6 + 55 004a 9095 com r25 + 56 004c 8195 neg r24 + 57 004e 9F4F sbci r25,lo8(-1) + GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 2 + + + 58 .L6: + 59 0050 8C17 cp r24,r28 + 60 0052 9D07 cpc r25,r29 + 61 0054 04F4 brge .L7 + 62 0056 01B7 in r16,81-32 + 63 0058 EC01 movw r28,r24 + 64 .L7: + 65 005a 81B7 in r24,81-32 + 66 005c 8F5F subi r24,lo8(-(1)) + 67 005e 81BF out 81-32,r24 + 68 .L5: + 69 0060 21B7 in r18,81-32 + 70 0062 30E0 ldi r19,lo8(0) + 71 0064 812F mov r24,r17 + 72 0066 90E0 ldi r25,lo8(0) + 73 0068 0196 adiw r24,1 + 74 006a 8217 cp r24,r18 + 75 006c 9307 cpc r25,r19 + 76 006e 04F4 brge .L8 + 77 0070 01BF out 81-32,r16 + 78 /* epilogue start */ + 79 0072 DF91 pop r29 + 80 0074 CF91 pop r28 + 81 0076 1F91 pop r17 + 82 0078 0F91 pop r16 + 83 007a FF90 pop r15 + 84 007c 0895 ret + 85 .size calibrateOscillator, .-calibrateOscillator + GAS LISTING C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s page 3 + + +DEFINED SYMBOLS + *ABS*:00000000 osccal.c +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:2 *ABS*:0000003f __SREG__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:3 *ABS*:0000003e __SP_H__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:4 *ABS*:0000003d __SP_L__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:5 *ABS*:00000034 __CCP__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:6 *ABS*:00000000 __tmp_reg__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:7 *ABS*:00000001 __zero_reg__ +C:\Users\Erik\AppData\Local\Temp/ccabieCZ.s:11 .text:00000000 calibrateOscillator + +UNDEFINED SYMBOLS +usbMeasureFrameLength diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/osccal.h b/hardware/digistump/avr/libraries/DigisparkKeyboard/osccal.h new file mode 100644 index 0000000..710ce05 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/osccal.h @@ -0,0 +1,65 @@ +/* Name: osccal.h + * Author: Christian Starkjohann + * Creation Date: 2008-04-10 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osccal.h 762 2009-08-12 17:10:30Z cs $ + */ + +/* +General Description: +This module contains a function which calibrates the AVR's internal RC +oscillator so that the CPU runs at F_CPU (F_CPU is a macro which must be +defined when the module is compiled, best passed in the compiler command +line). The time reference is the USB frame clock of 1 kHz available +immediately after a USB RESET condition. Timing is done by counting CPU +cycles, so all interrupts must be disabled while the calibration runs. For +low level timing measurements, usbMeasureFrameLength() is called. This +function must be enabled in usbconfig.h by defining +USB_CFG_HAVE_MEASURE_FRAME_LENGTH to 1. It is recommended to call +calibrateOscillator() from the reset hook in usbconfig.h: +*/ + +#ifndef __ASSEMBLER__ +#include // for sei() +extern void calibrateOscillator(void); +#endif +#define USB_RESET_HOOK(resetStarts) if(!resetStarts){cli(); calibrateOscillator(); sei();} + +/* +This routine is an alternative to the continuous synchronization described +in osctune.h. + +Algorithm used: +calibrateOscillator() first does a binary search in the OSCCAL register for +the best matching oscillator frequency. Then it does a next neighbor search +to find the value with the lowest clock rate deviation. It is guaranteed to +find the best match among neighboring values, but for version 5 oscillators +(which have a discontinuous relationship between OSCCAL and frequency) a +better match might be available in another OSCCAL region. + +Limitations: +This calibration algorithm may try OSCCAL values of up to 192 even if the +optimum value is far below 192. It may therefore exceed the allowed clock +frequency of the CPU in low voltage designs! +Precision depends on the OSCCAL vs. frequency dependency of the oscillator. +Typical precision for an ATMega168 (derived from the OSCCAL vs. F_RC diagram +in the data sheet) should be in the range of 0.4%. Only the 12.8 MHz and +16.5 MHz versions of V-USB (with built-in receiver PLL) can tolerate this +deviation! All other frequency modules require at least 0.2% precision. +*/ + +#ifndef __OSCCAL_H_INCLUDED__ +#define __OSCCAL_H_INCLUDED__ + +//void calibrateOscillator(void); +/* This function calibrates the RC oscillator so that the CPU runs at F_CPU. + * It MUST be called immediately after the end of a USB RESET condition! + * Disable all interrupts during the call! + * It is recommended that you store the resulting value in EEPROM so that a + * good guess value is available after the next reset. + */ + + +#endif /* __OSCCAL_H_INCLUDED__ */ diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/osccal.o b/hardware/digistump/avr/libraries/DigisparkKeyboard/osccal.o new file mode 100644 index 0000000..08e2187 Binary files /dev/null and b/hardware/digistump/avr/libraries/DigisparkKeyboard/osccal.o differ diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/osctune.h b/hardware/digistump/avr/libraries/DigisparkKeyboard/osctune.h new file mode 100644 index 0000000..c751648 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/osctune.h @@ -0,0 +1,88 @@ +/* Name: osctune.h + * Author: Christian Starkjohann + * Creation Date: 2008-10-18 + * Tabsize: 4 + * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: osctune.h 692 2008-11-07 15:07:40Z cs $ + */ + +/* +General Description: +This file is declared as C-header file although it is mostly documentation +how the RC oscillator can be kept in sync to the USB frame rate. The code +shown here must be added to usbconfig.h or this header file is included from +there. This code works only if D- is wired to the interrupt, not D+!!! + +This is an alternative to the osccal routine in osccal.c. It has the advantage +that the synchronization is done continuously and that it has more compact +code size. The disadvantages are slow synchronization (it may take a while +until the driver works), that messages immediately after the SOF pulse may be +lost (and need to be retried by the host) and that the interrupt is on D- +contrary to most examples. + +You may want to store a good calibration value in EEPROM for the next startup. +You know that the calibration value is good when the first USB message is +received. Do not store the value on every received message because the EEPROM +has a limited endurance. + +Notes: +(*) You must declare the global character variable "lastTimer0Value" in your +main code. + +(*) Timer 0 must be free running (not written by your code) and the prescaling +must be consistent with the TIMER0_PRESCALING define. + +(*) Good values for Timer 0 prescaling depend on how precise the clock must +be tuned and how far away from the default clock rate the target clock is. +For precise tuning, choose a low prescaler factor, for a broad range of tuning +choose a high one. A prescaler factor of 64 is good for the entire OSCCAL +range and allows a precision of better than +/-1%. A prescaler factor of 8 +allows tuning to slightly more than +/-6% of the default frequency and is +more precise than one step of OSCCAL. It is therefore not suitable to tune an +8 MHz oscillator to 12.5 MHz. + +Thanks to Henrik Haftmann for the idea to this routine! +*/ + +#define TIMER0_PRESCALING 64 /* must match the configuration for TIMER0 in main */ +#define TOLERATED_DEVIATION_PPT 5 /* max clock deviation before we tune in 1/10 % */ +/* derived constants: */ +#define EXPECTED_TIMER0_INCREMENT ((F_CPU / (1000 * TIMER0_PRESCALING)) & 0xff) +#define TOLERATED_DEVIATION (TOLERATED_DEVIATION_PPT * F_CPU / (1000000 * TIMER0_PRESCALING)) + +#ifdef __ASSEMBLER__ +macro tuneOsccal + push YH ;[0] + in YL, TCNT0 ;[2] + lds YH, lastTimer0Value ;[3] + sts lastTimer0Value, YL ;[5] + sub YL, YH ;[7] time passed since last frame + subi YL, EXPECTED_TIMER0_INCREMENT ;[8] +#if OSCCAL > 0x3f /* outside I/O addressable range */ + lds YH, OSCCAL ;[6] +#else + in YH, OSCCAL ;[6] assembler modle uses __SFR_OFFSET == 0 +#endif + cpi YL, TOLERATED_DEVIATION + 1 ;[10] + brmi notTooHigh ;[11] + subi YH, 1 ;[12] clock rate was too high +; brcs tuningOverflow ; optionally check for overflow + rjmp osctuneDone ;[13] +notTooHigh: + cpi YL, -TOLERATED_DEVIATION ;[13] + brpl osctuneDone ;[14] not too low + inc YH ;[15] clock rate was too low +; breq tuningOverflow ; optionally check for overflow +osctuneDone: +#if OSCCAL > 0x3f /* outside I/O addressable range */ + sts OSCCAL, YH ;[12-13] store tuned value +#else + out OSCCAL, YH ;[12-13] store tuned value +#endif +tuningOverflow: + pop YH ;[17] + endm ;[19] max number of cycles +#endif + +#define USB_SOF_HOOK tuneOsccal diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/scancode-ascii-table.h b/hardware/digistump/avr/libraries/DigisparkKeyboard/scancode-ascii-table.h new file mode 100644 index 0000000..0b0f613 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/scancode-ascii-table.h @@ -0,0 +1,134 @@ +#include +// Lookup table to convert ascii characters in to keyboard scan codes +// Format: most signifficant bit indicates if scan code should be sent with shift modifier +// remaining 7 bits are to be used as scan code number. + +const unsigned char ascii_to_scan_code_table[] PROGMEM = { + // /* ASCII: 0 */ 0, + // /* ASCII: 1 */ 0, + // /* ASCII: 2 */ 0, + // /* ASCII: 3 */ 0, + // /* ASCII: 4 */ 0, + // /* ASCII: 5 */ 0, + // /* ASCII: 6 */ 0, + // /* ASCII: 7 */ 0, + /* ASCII: 8 */ 42, + /* ASCII: 9 */ 43, + /* ASCII: 10 */ 40, + /* ASCII: 11 */ 0, + /* ASCII: 12 */ 0, + /* ASCII: 13 */ 0, + /* ASCII: 14 */ 0, + /* ASCII: 15 */ 0, + /* ASCII: 16 */ 0, + /* ASCII: 17 */ 0, + /* ASCII: 18 */ 0, + /* ASCII: 19 */ 0, + /* ASCII: 20 */ 0, + /* ASCII: 21 */ 0, + /* ASCII: 22 */ 0, + /* ASCII: 23 */ 0, + /* ASCII: 24 */ 0, + /* ASCII: 25 */ 0, + /* ASCII: 26 */ 0, + /* ASCII: 27 */ 41, + /* ASCII: 28 */ 0, + /* ASCII: 29 */ 0, + /* ASCII: 30 */ 0, + /* ASCII: 31 */ 0, + /* ASCII: 32 */ 44, + /* ASCII: 33 */ 158, + /* ASCII: 34 */ 180, + /* ASCII: 35 */ 160, + /* ASCII: 36 */ 161, + /* ASCII: 37 */ 162, + /* ASCII: 38 */ 164, + /* ASCII: 39 */ 52, + /* ASCII: 40 */ 166, + /* ASCII: 41 */ 167, + /* ASCII: 42 */ 165, + /* ASCII: 43 */ 174, + /* ASCII: 44 */ 54, + /* ASCII: 45 */ 45, + /* ASCII: 46 */ 55, + /* ASCII: 47 */ 56, + /* ASCII: 48 */ 39, + /* ASCII: 49 */ 30, + /* ASCII: 50 */ 31, + /* ASCII: 51 */ 32, + /* ASCII: 52 */ 33, + /* ASCII: 53 */ 34, + /* ASCII: 54 */ 35, + /* ASCII: 55 */ 36, + /* ASCII: 56 */ 37, + /* ASCII: 57 */ 38, + /* ASCII: 58 */ 179, + /* ASCII: 59 */ 51, + /* ASCII: 60 */ 182, + /* ASCII: 61 */ 46, + /* ASCII: 62 */ 183, + /* ASCII: 63 */ 184, + /* ASCII: 64 */ 159, + /* ASCII: 65 */ 132, + /* ASCII: 66 */ 133, + /* ASCII: 67 */ 134, + /* ASCII: 68 */ 135, + /* ASCII: 69 */ 136, + /* ASCII: 70 */ 137, + /* ASCII: 71 */ 138, + /* ASCII: 72 */ 139, + /* ASCII: 73 */ 140, + /* ASCII: 74 */ 141, + /* ASCII: 75 */ 142, + /* ASCII: 76 */ 143, + /* ASCII: 77 */ 144, + /* ASCII: 78 */ 145, + /* ASCII: 79 */ 146, + /* ASCII: 80 */ 147, + /* ASCII: 81 */ 148, + /* ASCII: 82 */ 149, + /* ASCII: 83 */ 150, + /* ASCII: 84 */ 151, + /* ASCII: 85 */ 152, + /* ASCII: 86 */ 153, + /* ASCII: 87 */ 154, + /* ASCII: 88 */ 155, + /* ASCII: 89 */ 156, + /* ASCII: 90 */ 157, + /* ASCII: 91 */ 47, + /* ASCII: 92 */ 49, + /* ASCII: 93 */ 48, + /* ASCII: 94 */ 163, + /* ASCII: 95 */ 173, + /* ASCII: 96 */ 53, + /* ASCII: 97 */ 4, + /* ASCII: 98 */ 5, + /* ASCII: 99 */ 6, + /* ASCII: 100 */ 7, + /* ASCII: 101 */ 8, + /* ASCII: 102 */ 9, + /* ASCII: 103 */ 10, + /* ASCII: 104 */ 11, + /* ASCII: 105 */ 12, + /* ASCII: 106 */ 13, + /* ASCII: 107 */ 14, + /* ASCII: 108 */ 15, + /* ASCII: 109 */ 16, + /* ASCII: 110 */ 17, + /* ASCII: 111 */ 18, + /* ASCII: 112 */ 19, + /* ASCII: 113 */ 20, + /* ASCII: 114 */ 21, + /* ASCII: 115 */ 22, + /* ASCII: 116 */ 23, + /* ASCII: 117 */ 24, + /* ASCII: 118 */ 25, + /* ASCII: 119 */ 26, + /* ASCII: 120 */ 27, + /* ASCII: 121 */ 28, + /* ASCII: 122 */ 29, + /* ASCII: 123 */ 175, + /* ASCII: 124 */ 177, + /* ASCII: 125 */ 176, + /* ASCII: 126 */ 181 +}; \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/usbconfig-prototype.h b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbconfig-prototype.h new file mode 100644 index 0000000..a0fd1bf --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbconfig-prototype.h @@ -0,0 +1,369 @@ +/* Name: usbconfig.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2005-04-01 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbconfig-prototype.h 767 2009-08-22 11:39:22Z cs $ + */ + +#ifndef __usbconfig_h_included__ +#define __usbconfig_h_included__ + +/* +General Description: +This file is an example configuration (with inline documentation) for the USB +driver. It configures V-USB for USB D+ connected to Port D bit 2 (which is +also hardware interrupt 0 on many devices) and USB D- to Port D bit 4. You may +wire the lines to any other port, as long as D+ is also wired to INT0 (or any +other hardware interrupt, as long as it is the highest level interrupt, see +section at the end of this file). ++ To create your own usbconfig.h file, copy this file to your project's ++ firmware source directory) and rename it to "usbconfig.h". ++ Then edit it accordingly. +*/ + +/* ---------------------------- Hardware Config ---------------------------- */ + +#define USB_CFG_IOPORTNAME D +/* This is the port where the USB bus is connected. When you configure it to + * "B", the registers PORTB, PINB and DDRB will be used. + */ +#define USB_CFG_DMINUS_BIT 4 +/* This is the bit number in USB_CFG_IOPORT where the USB D- line is connected. + * This may be any bit in the port. + */ +#define USB_CFG_DPLUS_BIT 2 +/* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected. + * This may be any bit in the port. Please note that D+ must also be connected + * to interrupt pin INT0! [You can also use other interrupts, see section + * "Optional MCU Description" below, or you can connect D- to the interrupt, as + * it is required if you use the USB_COUNT_SOF feature. If you use D- for the + * interrupt, the USB interrupt will also be triggered at Start-Of-Frame + * markers every millisecond.] + */ +#define USB_CFG_CLOCK_KHZ (F_CPU/1000) +/* Clock rate of the AVR in kHz. Legal values are 12000, 12800, 15000, 16000, + * 16500 and 20000. The 12.8 MHz and 16.5 MHz versions of the code require no + * crystal, they tolerate +/- 1% deviation from the nominal frequency. All + * other rates require a precision of 2000 ppm and thus a crystal! + * Default if not specified: 12 MHz + */ +#define USB_CFG_CHECK_CRC 0 +/* Define this to 1 if you want that the driver checks integrity of incoming + * data packets (CRC checks). CRC checks cost quite a bit of code size and are + * currently only available for 18 MHz crystal clock. You must choose + * USB_CFG_CLOCK_KHZ = 18000 if you enable this option. + */ + +/* ----------------------- Optional Hardware Config ------------------------ */ + +/* #define USB_CFG_PULLUP_IOPORTNAME D */ +/* If you connect the 1.5k pullup resistor from D- to a port pin instead of + * V+, you can connect and disconnect the device from firmware by calling + * the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h). + * This constant defines the port on which the pullup resistor is connected. + */ +/* #define USB_CFG_PULLUP_BIT 4 */ +/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined + * above) where the 1.5k pullup resistor is connected. See description + * above for details. + */ + +/* --------------------------- Functional Range ---------------------------- */ + +#define USB_CFG_HAVE_INTRIN_ENDPOINT 0 +/* Define this to 1 if you want to compile a version with two endpoints: The + * default control endpoint 0 and an interrupt-in endpoint (any other endpoint + * number). + */ +#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0 +/* Define this to 1 if you want to compile a version with three endpoints: The + * default control endpoint 0, an interrupt-in endpoint 3 (or the number + * configured below) and a catch-all default interrupt-in endpoint as above. + * You must also define USB_CFG_HAVE_INTRIN_ENDPOINT to 1 for this feature. + */ +#define USB_CFG_EP3_NUMBER 3 +/* If the so-called endpoint 3 is used, it can now be configured to any other + * endpoint number (except 0) with this macro. Default if undefined is 3. + */ +/* #define USB_INITIAL_DATATOKEN USBPID_DATA1 */ +/* The above macro defines the startup condition for data toggling on the + * interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA1. + * Since the token is toggled BEFORE sending any data, the first packet is + * sent with the oposite value of this configuration! + */ +#define USB_CFG_IMPLEMENT_HALT 0 +/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature + * for endpoint 1 (interrupt endpoint). Although you may not need this feature, + * it is required by the standard. We have made it a config option because it + * bloats the code considerably. + */ +#define USB_CFG_SUPPRESS_INTR_CODE 0 +/* Define this to 1 if you want to declare interrupt-in endpoints, but don't + * want to send any data over them. If this macro is defined to 1, functions + * usbSetInterrupt() and usbSetInterrupt3() are omitted. This is useful if + * you need the interrupt-in endpoints in order to comply to an interface + * (e.g. HID), but never want to send any data. This option saves a couple + * of bytes in flash memory and the transmit buffers in RAM. + */ +#define USB_CFG_INTR_POLL_INTERVAL 10 +/* If you compile a version with endpoint 1 (interrupt-in), this is the poll + * interval. The value is in milliseconds and must not be less than 10 ms for + * low speed devices. + */ +#define USB_CFG_IS_SELF_POWERED 0 +/* Define this to 1 if the device has its own power supply. Set it to 0 if the + * device is powered from the USB bus. + */ +#define USB_CFG_MAX_BUS_POWER 100 +/* Set this variable to the maximum USB bus power consumption of your device. + * The value is in milliamperes. [It will be divided by two since USB + * communicates power requirements in units of 2 mA.] + */ +#define USB_CFG_IMPLEMENT_FN_WRITE 0 +/* Set this to 1 if you want usbFunctionWrite() to be called for control-out + * transfers. Set it to 0 if you don't need it and want to save a couple of + * bytes. + */ +#define USB_CFG_IMPLEMENT_FN_READ 0 +/* Set this to 1 if you need to send control replies which are generated + * "on the fly" when usbFunctionRead() is called. If you only want to send + * data from a static buffer, set it to 0 and return the data from + * usbFunctionSetup(). This saves a couple of bytes. + */ +#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0 +/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints. + * You must implement the function usbFunctionWriteOut() which receives all + * interrupt/bulk data sent to any endpoint other than 0. The endpoint number + * can be found in 'usbRxToken'. + */ +#define USB_CFG_HAVE_FLOWCONTROL 0 +/* Define this to 1 if you want flowcontrol over USB data. See the definition + * of the macros usbDisableAllRequests() and usbEnableAllRequests() in + * usbdrv.h. + */ +#define USB_CFG_LONG_TRANSFERS 0 +/* Define this to 1 if you want to send/receive blocks of more than 254 bytes + * in a single control-in or control-out transfer. Note that the capability + * for long transfers increases the driver size. + */ +/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */ +/* This macro is a hook if you want to do unconventional things. If it is + * defined, it's inserted at the beginning of received message processing. + * If you eat the received message and don't want default processing to + * proceed, do a return after doing your things. One possible application + * (besides debugging) is to flash a status LED on each packet. + */ +/* #define USB_RESET_HOOK(resetStarts) if(!resetStarts){hadUsbReset();} */ +/* This macro is a hook if you need to know when an USB RESET occurs. It has + * one parameter which distinguishes between the start of RESET state and its + * end. + */ +/* #define USB_SET_ADDRESS_HOOK() hadAddressAssigned(); */ +/* This macro (if defined) is executed when a USB SET_ADDRESS request was + * received. + */ +#define USB_COUNT_SOF 0 +/* define this macro to 1 if you need the global variable "usbSofCount" which + * counts SOF packets. This feature requires that the hardware interrupt is + * connected to D- instead of D+. + */ +/* #ifdef __ASSEMBLER__ + * macro myAssemblerMacro + * in YL, TCNT0 + * sts timer0Snapshot, YL + * endm + * #endif + * #define USB_SOF_HOOK myAssemblerMacro + * This macro (if defined) is executed in the assembler module when a + * Start Of Frame condition is detected. It is recommended to define it to + * the name of an assembler macro which is defined here as well so that more + * than one assembler instruction can be used. The macro may use the register + * YL and modify SREG. If it lasts longer than a couple of cycles, USB messages + * immediately after an SOF pulse may be lost and must be retried by the host. + * What can you do with this hook? Since the SOF signal occurs exactly every + * 1 ms (unless the host is in sleep mode), you can use it to tune OSCCAL in + * designs running on the internal RC oscillator. + * Please note that Start Of Frame detection works only if D- is wired to the + * interrupt, not D+. THIS IS DIFFERENT THAN MOST EXAMPLES! + */ +#define USB_CFG_CHECK_DATA_TOGGLING 0 +/* define this macro to 1 if you want to filter out duplicate data packets + * sent by the host. Duplicates occur only as a consequence of communication + * errors, when the host does not receive an ACK. Please note that you need to + * implement the filtering yourself in usbFunctionWriteOut() and + * usbFunctionWrite(). Use the global usbCurrentDataToken and a static variable + * for each control- and out-endpoint to check for duplicate packets. + */ +#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 0 +/* define this macro to 1 if you want the function usbMeasureFrameLength() + * compiled in. This function can be used to calibrate the AVR's RC oscillator. + */ +#define USB_USE_FAST_CRC 0 +/* The assembler module has two implementations for the CRC algorithm. One is + * faster, the other is smaller. This CRC routine is only used for transmitted + * messages where timing is not critical. The faster routine needs 31 cycles + * per byte while the smaller one needs 61 to 69 cycles. The faster routine + * may be worth the 32 bytes bigger code size if you transmit lots of data and + * run the AVR close to its limit. + */ + +/* -------------------------- Device Description --------------------------- */ + +#define USB_CFG_VENDOR_ID 0xc0, 0x16 /* = 0x16c0 = 5824 = voti.nl */ +/* USB vendor ID for the device, low byte first. If you have registered your + * own Vendor ID, define it here. Otherwise you may use one of obdev's free + * shared VID/PID pairs. Be sure to read USB-IDs-for-free.txt for rules! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_ID 0xdc, 0x05 /* = 0x05dc = 1500 */ +/* This is the ID of the product, low byte first. It is interpreted in the + * scope of the vendor ID. If you have registered your own VID with usb.org + * or if you have licensed a PID from somebody else, define it here. Otherwise + * you may use one of obdev's free shared VID/PID pairs. See the file + * USB-IDs-for-free.txt for details! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_VERSION 0x00, 0x01 +/* Version number of the device: Minor number first, then major number. + */ +#define USB_CFG_VENDOR_NAME 'o', 'b', 'd', 'e', 'v', '.', 'a', 't' +#define USB_CFG_VENDOR_NAME_LEN 8 +/* These two values define the vendor name returned by the USB device. The name + * must be given as a list of characters under single quotes. The characters + * are interpreted as Unicode (UTF-16) entities. + * If you don't want a vendor name string, undefine these macros. + * ALWAYS define a vendor name containing your Internet domain name if you use + * obdev's free shared VID/PID pair. See the file USB-IDs-for-free.txt for + * details. + */ +#define USB_CFG_DEVICE_NAME 'T', 'e', 'm', 'p', 'l', 'a', 't', 'e' +#define USB_CFG_DEVICE_NAME_LEN 8 +/* Same as above for the device name. If you don't want a device name, undefine + * the macros. See the file USB-IDs-for-free.txt before you assign a name if + * you use a shared VID/PID. + */ +/*#define USB_CFG_SERIAL_NUMBER 'N', 'o', 'n', 'e' */ +/*#define USB_CFG_SERIAL_NUMBER_LEN 0 */ +/* Same as above for the serial number. If you don't want a serial number, + * undefine the macros. + * It may be useful to provide the serial number through other means than at + * compile time. See the section about descriptor properties below for how + * to fine tune control over USB descriptors such as the string descriptor + * for the serial number. + */ +#define USB_CFG_DEVICE_CLASS 0xff /* set to 0 if deferred to interface */ +#define USB_CFG_DEVICE_SUBCLASS 0 +/* See USB specification if you want to conform to an existing device class. + * Class 0xff is "vendor specific". + */ +#define USB_CFG_INTERFACE_CLASS 0 /* define class here if not at device level */ +#define USB_CFG_INTERFACE_SUBCLASS 0 +#define USB_CFG_INTERFACE_PROTOCOL 0 +/* See USB specification if you want to conform to an existing device class or + * protocol. The following classes must be set at interface level: + * HID class is 3, no subclass and protocol required (but may be useful!) + * CDC class is 2, use subclass 2 and protocol 1 for ACM + */ +/* #define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 42 */ +/* Define this to the length of the HID report descriptor, if you implement + * an HID device. Otherwise don't define it or define it to 0. + * If you use this define, you must add a PROGMEM character array named + * "usbHidReportDescriptor" to your code which contains the report descriptor. + * Don't forget to keep the array and this define in sync! + */ + +/* #define USB_PUBLIC static */ +/* Use the define above if you #include usbdrv.c instead of linking against it. + * This technique saves a couple of bytes in flash memory. + */ + +/* ------------------- Fine Control over USB Descriptors ------------------- */ +/* If you don't want to use the driver's default USB descriptors, you can + * provide our own. These can be provided as (1) fixed length static data in + * flash memory, (2) fixed length static data in RAM or (3) dynamically at + * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more + * information about this function. + * Descriptor handling is configured through the descriptor's properties. If + * no properties are defined or if they are 0, the default descriptor is used. + * Possible properties are: + * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched + * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is + * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if + * you want RAM pointers. + * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found + * in static memory is in RAM, not in flash memory. + * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash), + * the driver must know the descriptor's length. The descriptor itself is + * found at the address of a well known identifier (see below). + * List of static descriptor names (must be declared PROGMEM if in flash): + * char usbDescriptorDevice[]; + * char usbDescriptorConfiguration[]; + * char usbDescriptorHidReport[]; + * char usbDescriptorString0[]; + * int usbDescriptorStringVendor[]; + * int usbDescriptorStringDevice[]; + * int usbDescriptorStringSerialNumber[]; + * Other descriptors can't be provided statically, they must be provided + * dynamically at runtime. + * + * Descriptor properties are or-ed or added together, e.g.: + * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18)) + * + * The following descriptors are defined: + * USB_CFG_DESCR_PROPS_DEVICE + * USB_CFG_DESCR_PROPS_CONFIGURATION + * USB_CFG_DESCR_PROPS_STRINGS + * USB_CFG_DESCR_PROPS_STRING_0 + * USB_CFG_DESCR_PROPS_STRING_VENDOR + * USB_CFG_DESCR_PROPS_STRING_PRODUCT + * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER + * USB_CFG_DESCR_PROPS_HID + * USB_CFG_DESCR_PROPS_HID_REPORT + * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver) + * + * Note about string descriptors: String descriptors are not just strings, they + * are Unicode strings prefixed with a 2 byte header. Example: + * int serialNumberDescriptor[] = { + * USB_STRING_DESCRIPTOR_HEADER(6), + * 'S', 'e', 'r', 'i', 'a', 'l' + * }; + */ + +#define USB_CFG_DESCR_PROPS_DEVICE 0 +#define USB_CFG_DESCR_PROPS_CONFIGURATION 0 +#define USB_CFG_DESCR_PROPS_STRINGS 0 +#define USB_CFG_DESCR_PROPS_STRING_0 0 +#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0 +#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0 +#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0 +#define USB_CFG_DESCR_PROPS_HID 0 +#define USB_CFG_DESCR_PROPS_HID_REPORT 0 +#define USB_CFG_DESCR_PROPS_UNKNOWN 0 + +/* ----------------------- Optional MCU Description ------------------------ */ + +/* The following configurations have working defaults in usbdrv.h. You + * usually don't need to set them explicitly. Only if you want to run + * the driver on a device which is not yet supported or with a compiler + * which is not fully supported (such as IAR C) or if you use a differnt + * interrupt than INT0, you may have to define some of these. + */ +/* #define USB_INTR_CFG MCUCR */ +/* #define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) */ +/* #define USB_INTR_CFG_CLR 0 */ +/* #define USB_INTR_ENABLE GIMSK */ +/* #define USB_INTR_ENABLE_BIT INT0 */ +/* #define USB_INTR_PENDING GIFR */ +/* #define USB_INTR_PENDING_BIT INTF0 */ +/* #define USB_INTR_VECTOR SIG_INTERRUPT0 */ + +#endif /* __usbconfig_h_included__ */ diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/usbconfig.h b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbconfig.h new file mode 100644 index 0000000..9e99405 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbconfig.h @@ -0,0 +1,411 @@ +/* Name: usbconfig.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2005-04-01 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbconfig-prototype.h 767 2009-08-22 11:39:22Z cs $ + */ + +#ifndef __usbconfig_h_included__ +#define __usbconfig_h_included__ + +/* +General Description: +This file is an example configuration (with inline documentation) for the USB +driver. It configures V-USB for USB D+ connected to Port D bit 2 (which is +also hardware interrupt 0 on many devices) and USB D- to Port D bit 4. You may +wire the lines to any other port, as long as D+ is also wired to INT0 (or any +other hardware interrupt, as long as it is the highest level interrupt, see +section at the end of this file). ++ To create your own usbconfig.h file, copy this file to your project's ++ firmware source directory) and rename it to "usbconfig.h". ++ Then edit it accordingly. +*/ + +/* ---------------------------- Hardware Config ---------------------------- */ + +#if defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 1 +#define USB_CFG_DPLUS_BIT 2 + +#elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 4 + +#elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 6 + +#elif defined (__AVR_ATtiny461__) || defined (__AVR_ATtiny861__) +#define USB_CFG_IOPORTNAME B +#define USB_CFG_DMINUS_BIT 5 +#define USB_CFG_DPLUS_BIT 6 +#else +/* ATtiny2313, ATmega8/48/88/168 */ +#define USB_CFG_IOPORTNAME D +#define USB_CFG_DMINUS_BIT 3 +#define USB_CFG_DPLUS_BIT 2 +#endif +/* This is the bit number in USB_CFG_IOPORT where the USB D+ line is connected. + * This may be any bit in the port. Please note that D+ must also be connected + * to interrupt pin INT0! [You can also use other interrupts, see section + * "Optional MCU Description" below, or you can connect D- to the interrupt, as + * it is required if you use the USB_COUNT_SOF feature. If you use D- for the + * interrupt, the USB interrupt will also be triggered at Start-Of-Frame + * markers every millisecond.] + */ +#define USB_CFG_CLOCK_KHZ (F_CPU/1000) +/* Clock rate of the AVR in kHz. Legal values are 12000, 12800, 15000, 16000, + * 16500 and 20000. The 12.8 MHz and 16.5 MHz versions of the code require no + * crystal, they tolerate +/- 1% deviation from the nominal frequency. All + * other rates require a precision of 2000 ppm and thus a crystal! + * Default if not specified: 12 MHz + */ +#define USB_CFG_CHECK_CRC 0 +/* Define this to 1 if you want that the driver checks integrity of incoming + * data packets (CRC checks). CRC checks cost quite a bit of code size and are + * currently only available for 18 MHz crystal clock. You must choose + * USB_CFG_CLOCK_KHZ = 18000 if you enable this option. + */ + +/* ----------------------- Optional Hardware Config ------------------------ */ + +//#define USB_CFG_PULLUP_IOPORTNAME D +/* If you connect the 1.5k pullup resistor from D- to a port pin instead of + * V+, you can connect and disconnect the device from firmware by calling + * the macros usbDeviceConnect() and usbDeviceDisconnect() (see usbdrv.h). + * This constant defines the port on which the pullup resistor is connected. + */ +//#define USB_CFG_PULLUP_BIT 5 +/* This constant defines the bit number in USB_CFG_PULLUP_IOPORT (defined + * above) where the 1.5k pullup resistor is connected. See description + * above for details. + */ + +/* --------------------------- Functional Range ---------------------------- */ + +#define USB_CFG_HAVE_INTRIN_ENDPOINT 1 +/* Define this to 1 if you want to compile a version with two endpoints: The + * default control endpoint 0 and an interrupt-in endpoint (any other endpoint + * number). + */ +#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0 +/* Define this to 1 if you want to compile a version with three endpoints: The + * default control endpoint 0, an interrupt-in endpoint 3 (or the number + * configured below) and a catch-all default interrupt-in endpoint as above. + * You must also define USB_CFG_HAVE_INTRIN_ENDPOINT to 1 for this feature. + */ +#define USB_CFG_EP3_NUMBER 3 +/* If the so-called endpoint 3 is used, it can now be configured to any other + * endpoint number (except 0) with this macro. Default if undefined is 3. + */ +/* #define USB_INITIAL_DATATOKEN USBPID_DATA1 */ +/* The above macro defines the startup condition for data toggling on the + * interrupt/bulk endpoints 1 and 3. Defaults to USBPID_DATA1. + * Since the token is toggled BEFORE sending any data, the first packet is + * sent with the oposite value of this configuration! + */ +#define USB_CFG_IMPLEMENT_HALT 0 +/* Define this to 1 if you also want to implement the ENDPOINT_HALT feature + * for endpoint 1 (interrupt endpoint). Although you may not need this feature, + * it is required by the standard. We have made it a config option because it + * bloats the code considerably. + */ +#define USB_CFG_SUPPRESS_INTR_CODE 0 +/* Define this to 1 if you want to declare interrupt-in endpoints, but don't + * want to send any data over them. If this macro is defined to 1, functions + * usbSetInterrupt() and usbSetInterrupt3() are omitted. This is useful if + * you need the interrupt-in endpoints in order to comply to an interface + * (e.g. HID), but never want to send any data. This option saves a couple + * of bytes in flash memory and the transmit buffers in RAM. + */ +#define USB_CFG_INTR_POLL_INTERVAL 10 +/* If you compile a version with endpoint 1 (interrupt-in), this is the poll + * interval. The value is in milliseconds and must not be less than 10 ms for + * low speed devices. + */ +#define USB_CFG_IS_SELF_POWERED 0 +/* Define this to 1 if the device has its own power supply. Set it to 0 if the + * device is powered from the USB bus. + */ +#define USB_CFG_MAX_BUS_POWER 100 +/* Set this variable to the maximum USB bus power consumption of your device. + * The value is in milliamperes. [It will be divided by two since USB + * communicates power requirements in units of 2 mA.] + */ +#define USB_CFG_IMPLEMENT_FN_WRITE 0 +/* Set this to 1 if you want usbFunctionWrite() to be called for control-out + * transfers. Set it to 0 if you don't need it and want to save a couple of + * bytes. + */ +#define USB_CFG_IMPLEMENT_FN_READ 0 +/* Set this to 1 if you need to send control replies which are generated + * "on the fly" when usbFunctionRead() is called. If you only want to send + * data from a static buffer, set it to 0 and return the data from + * usbFunctionSetup(). This saves a couple of bytes. + */ +#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0 +/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints. + * You must implement the function usbFunctionWriteOut() which receives all + * interrupt/bulk data sent to any endpoint other than 0. The endpoint number + * can be found in 'usbRxToken'. + */ +#define USB_CFG_HAVE_FLOWCONTROL 0 +/* Define this to 1 if you want flowcontrol over USB data. See the definition + * of the macros usbDisableAllRequests() and usbEnableAllRequests() in + * usbdrv.h. + */ +#define USB_CFG_LONG_TRANSFERS 0 +/* Define this to 1 if you want to send/receive blocks of more than 254 bytes + * in a single control-in or control-out transfer. Note that the capability + * for long transfers increases the driver size. + */ +/* #define USB_RX_USER_HOOK(data, len) if(usbRxToken == (uchar)USBPID_SETUP) blinkLED(); */ +/* This macro is a hook if you want to do unconventional things. If it is + * defined, it's inserted at the beginning of received message processing. + * If you eat the received message and don't want default processing to + * proceed, do a return after doing your things. One possible application + * (besides debugging) is to flash a status LED on each packet. + */ +/* #define USB_RESET_HOOK(resetStarts) if(!resetStarts){hadUsbReset();} */ +/* This macro is a hook if you need to know when an USB RESET occurs. It has + * one parameter which distinguishes between the start of RESET state and its + * end. + */ +/* #define USB_SET_ADDRESS_HOOK() hadAddressAssigned(); */ +/* This macro (if defined) is executed when a USB SET_ADDRESS request was + * received. + */ +#define USB_COUNT_SOF 0 +/* define this macro to 1 if you need the global variable "usbSofCount" which + * counts SOF packets. This feature requires that the hardware interrupt is + * connected to D- instead of D+. + */ +/* #ifdef __ASSEMBLER__ + * macro myAssemblerMacro + * in YL, TCNT0 + * sts timer0Snapshot, YL + * endm + * #endif + * #define USB_SOF_HOOK myAssemblerMacro + * This macro (if defined) is executed in the assembler module when a + * Start Of Frame condition is detected. It is recommended to define it to + * the name of an assembler macro which is defined here as well so that more + * than one assembler instruction can be used. The macro may use the register + * YL and modify SREG. If it lasts longer than a couple of cycles, USB messages + * immediately after an SOF pulse may be lost and must be retried by the host. + * What can you do with this hook? Since the SOF signal occurs exactly every + * 1 ms (unless the host is in sleep mode), you can use it to tune OSCCAL in + * designs running on the internal RC oscillator. + * Please note that Start Of Frame detection works only if D- is wired to the + * interrupt, not D+. THIS IS DIFFERENT THAN MOST EXAMPLES! + */ +#define USB_CFG_CHECK_DATA_TOGGLING 0 +/* define this macro to 1 if you want to filter out duplicate data packets + * sent by the host. Duplicates occur only as a consequence of communication + * errors, when the host does not receive an ACK. Please note that you need to + * implement the filtering yourself in usbFunctionWriteOut() and + * usbFunctionWrite(). Use the global usbCurrentDataToken and a static variable + * for each control- and out-endpoint to check for duplicate packets. + */ +#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 1 +#include "osccal.h" +/* define this macro to 1 if you want the function usbMeasureFrameLength() + * compiled in. This function can be used to calibrate the AVR's RC oscillator. + */ +#define USB_USE_FAST_CRC 0 +/* The assembler module has two implementations for the CRC algorithm. One is + * faster, the other is smaller. This CRC routine is only used for transmitted + * messages where timing is not critical. The faster routine needs 31 cycles + * per byte while the smaller one needs 61 to 69 cycles. The faster routine + * may be worth the 32 bytes bigger code size if you transmit lots of data and + * run the AVR close to its limit. + */ + +/* -------------------------- Device Description --------------------------- */ + +#define USB_CFG_VENDOR_ID 0xc0, 0x16 +/* USB vendor ID for the device, low byte first. If you have registered your + * own Vendor ID, define it here. Otherwise you may use one of obdev's free + * shared VID/PID pairs. Be sure to read USB-IDs-for-free.txt for rules! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_ID 0xdb, 0x27 +/* This is the ID of the product, low byte first. It is interpreted in the + * scope of the vendor ID. If you have registered your own VID with usb.org + * or if you have licensed a PID from somebody else, define it here. Otherwise + * you may use one of obdev's free shared VID/PID pairs. See the file + * USB-IDs-for-free.txt for details! + * *** IMPORTANT NOTE *** + * This template uses obdev's shared VID/PID pair for Vendor Class devices + * with libusb: 0x16c0/0x5dc. Use this VID/PID pair ONLY if you understand + * the implications! + */ +#define USB_CFG_DEVICE_VERSION 0x00, 0x01 +/* Version number of the device: Minor number first, then major number. + */ +#define USB_CFG_VENDOR_NAME 'd','i','g','i','s','t','u','m','p','.','c','o','m' +#define USB_CFG_VENDOR_NAME_LEN 13 +/* These two values define the vendor name returned by the USB device. The name + * must be given as a list of characters under single quotes. The characters + * are interpreted as Unicode (UTF-16) entities. + * If you don't want a vendor name string, undefine these macros. + * ALWAYS define a vendor name containing your Internet domain name if you use + * obdev's free shared VID/PID pair. See the file USB-IDs-for-free.txt for + * details. + */ +#define USB_CFG_DEVICE_NAME 'D','i','g','i','K','e','y' +#define USB_CFG_DEVICE_NAME_LEN 7 +/* Same as above for the device name. If you don't want a device name, undefine + * the macros. See the file USB-IDs-for-free.txt before you assign a name if + * you use a shared VID/PID. + */ +/*#define USB_CFG_SERIAL_NUMBER 'N', 'o', 'n', 'e' */ +/*#define USB_CFG_SERIAL_NUMBER_LEN 0 */ +/* Same as above for the serial number. If you don't want a serial number, + * undefine the macros. + * It may be useful to provide the serial number through other means than at + * compile time. See the section about descriptor properties below for how + * to fine tune control over USB descriptors such as the string descriptor + * for the serial number. + */ +#define USB_CFG_DEVICE_CLASS 0 /* set to 0 if deferred to interface */ +#define USB_CFG_DEVICE_SUBCLASS 0 +/* See USB specification if you want to conform to an existing device class. + * Class 0xff is "vendor specific". + */ +#define USB_CFG_INTERFACE_CLASS 0x03 /* HID */ /* define class here if not at device level */ +#define USB_CFG_INTERFACE_SUBCLASS 0x01 +#define USB_CFG_INTERFACE_PROTOCOL 0x01 +/* See USB specification if you want to conform to an existing device class or + * protocol. The following classes must be set at interface level: + * HID class is 3, no subclass and protocol required (but may be useful!) + * CDC class is 2, use subclass 2 and protocol 1 for ACM + */ +#define USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH 35 +/* Define this to the length of the HID report descriptor, if you implement + * an HID device. Otherwise don't define it or define it to 0. + * If you use this define, you must add a PROGMEM character array named + * "usbHidReportDescriptor" to your code which contains the report descriptor. + * Don't forget to keep the array and this define in sync! + */ + +/* #define USB_PUBLIC static */ +/* Use the define above if you #include usbdrv.c instead of linking against it. + * This technique saves a couple of bytes in flash memory. + */ + +/* ------------------- Fine Control over USB Descriptors ------------------- */ +/* If you don't want to use the driver's default USB descriptors, you can + * provide our own. These can be provided as (1) fixed length static data in + * flash memory, (2) fixed length static data in RAM or (3) dynamically at + * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more + * information about this function. + * Descriptor handling is configured through the descriptor's properties. If + * no properties are defined or if they are 0, the default descriptor is used. + * Possible properties are: + * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched + * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is + * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if + * you want RAM pointers. + * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found + * in static memory is in RAM, not in flash memory. + * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash), + * the driver must know the descriptor's length. The descriptor itself is + * found at the address of a well known identifier (see below). + * List of static descriptor names (must be declared PROGMEM if in flash): + * char usbDescriptorDevice[]; + * char usbDescriptorConfiguration[]; + * char usbDescriptorHidReport[]; + * char usbDescriptorString0[]; + * int usbDescriptorStringVendor[]; + * int usbDescriptorStringDevice[]; + * int usbDescriptorStringSerialNumber[]; + * Other descriptors can't be provided statically, they must be provided + * dynamically at runtime. + * + * Descriptor properties are or-ed or added together, e.g.: + * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18)) + * + * The following descriptors are defined: + * USB_CFG_DESCR_PROPS_DEVICE + * USB_CFG_DESCR_PROPS_CONFIGURATION + * USB_CFG_DESCR_PROPS_STRINGS + * USB_CFG_DESCR_PROPS_STRING_0 + * USB_CFG_DESCR_PROPS_STRING_VENDOR + * USB_CFG_DESCR_PROPS_STRING_PRODUCT + * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER + * USB_CFG_DESCR_PROPS_HID + * USB_CFG_DESCR_PROPS_HID_REPORT + * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver) + * + * Note about string descriptors: String descriptors are not just strings, they + * are Unicode strings prefixed with a 2 byte header. Example: + * int serialNumberDescriptor[] = { + * USB_STRING_DESCRIPTOR_HEADER(6), + * 'S', 'e', 'r', 'i', 'a', 'l' + * }; + */ + +#define USB_CFG_DESCR_PROPS_DEVICE 0 +#define USB_CFG_DESCR_PROPS_CONFIGURATION 0 +#define USB_CFG_DESCR_PROPS_STRINGS 0 +#define USB_CFG_DESCR_PROPS_STRING_0 0 +#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0 +#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0 +#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0 +#define USB_CFG_DESCR_PROPS_HID 0 +#define USB_CFG_DESCR_PROPS_HID_REPORT 0 +#define USB_CFG_DESCR_PROPS_UNKNOWN 0 + +/* ----------------------- Optional MCU Description ------------------------ */ + +/* The following configurations have working defaults in usbdrv.h. You + * usually don't need to set them explicitly. Only if you want to run + * the driver on a device which is not yet supported or with a compiler + * which is not fully supported (such as IAR C) or if you use a differnt + * interrupt than INT0, you may have to define some of these. + */ +/* #define USB_INTR_CFG MCUCR */ +/* #define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) */ +/* #define USB_INTR_CFG_CLR 0 */ +/* #define USB_INTR_ENABLE GIMSK */ +/* #define USB_INTR_ENABLE_BIT INT0 */ +/* #define USB_INTR_PENDING GIFR */ +/* #define USB_INTR_PENDING_BIT INTF0 */ +/* #define USB_INTR_VECTOR SIG_INTERRUPT0 */ + + #ifndef SIG_INTERRUPT0 +#define SIG_INTERRUPT0 _VECTOR(1) +#endif + + + #if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define USB_INTR_CFG PCMSK +#define USB_INTR_CFG_SET (1<len & 0x10){ /* packet buffer was empty */ + txStatus->buffer[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */ + }else{ + txStatus->len = USBPID_NAK; /* avoid sending outdated (overwritten) interrupt data */ + } + p = txStatus->buffer + 1; + i = len; + do{ /* if len == 0, we still copy 1 byte, but that's no problem */ + *p++ = *data++; + }while(--i > 0); /* loop control at the end is 2 bytes shorter than at beginning */ + usbCrc16Append(&txStatus->buffer[1], len); + txStatus->len = len + 4; /* len must be given including sync byte */ + DBG2(0x21 + (((int)txStatus >> 3) & 3), txStatus->buffer, len + 3); +} + +USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len) +{ + usbGenericSetInterrupt(data, len, &usbTxStatus1); +} +#endif + +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 +USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len) +{ + usbGenericSetInterrupt(data, len, &usbTxStatus3); +} +#endif +#endif /* USB_CFG_SUPPRESS_INTR_CODE */ + +/* ------------------ utilities for code following below ------------------- */ + +/* Use defines for the switch statement so that we can choose between an + * if()else if() and a switch/case based implementation. switch() is more + * efficient for a LARGE set of sequential choices, if() is better in all other + * cases. + */ +#if USB_CFG_USE_SWITCH_STATEMENT +# define SWITCH_START(cmd) switch(cmd){{ +# define SWITCH_CASE(value) }break; case (value):{ +# define SWITCH_CASE2(v1,v2) }break; case (v1): case(v2):{ +# define SWITCH_CASE3(v1,v2,v3) }break; case (v1): case(v2): case(v3):{ +# define SWITCH_DEFAULT }break; default:{ +# define SWITCH_END }} +#else +# define SWITCH_START(cmd) {uchar _cmd = cmd; if(0){ +# define SWITCH_CASE(value) }else if(_cmd == (value)){ +# define SWITCH_CASE2(v1,v2) }else if(_cmd == (v1) || _cmd == (v2)){ +# define SWITCH_CASE3(v1,v2,v3) }else if(_cmd == (v1) || _cmd == (v2) || (_cmd == v3)){ +# define SWITCH_DEFAULT }else{ +# define SWITCH_END }} +#endif + +#ifndef USB_RX_USER_HOOK +#define USB_RX_USER_HOOK(data, len) +#endif +#ifndef USB_SET_ADDRESS_HOOK +#define USB_SET_ADDRESS_HOOK() +#endif + +/* ------------------------------------------------------------------------- */ + +/* We use if() instead of #if in the macro below because #if can't be used + * in macros and the compiler optimizes constant conditions anyway. + * This may cause problems with undefined symbols if compiled without + * optimizing! + */ +#define GET_DESCRIPTOR(cfgProp, staticName) \ + if(cfgProp){ \ + if((cfgProp) & USB_PROP_IS_RAM) \ + flags = 0; \ + if((cfgProp) & USB_PROP_IS_DYNAMIC){ \ + len = usbFunctionDescriptor(rq); \ + }else{ \ + len = USB_PROP_LENGTH(cfgProp); \ + usbMsgPtr = (uchar *)(staticName); \ + } \ + } + +/* usbDriverDescriptor() is similar to usbFunctionDescriptor(), but used + * internally for all types of descriptors. + */ +static inline usbMsgLen_t usbDriverDescriptor(usbRequest_t *rq) +{ +usbMsgLen_t len = 0; +uchar flags = USB_FLG_MSGPTR_IS_ROM; + + SWITCH_START(rq->wValue.bytes[1]) + SWITCH_CASE(USBDESCR_DEVICE) /* 1 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_DEVICE, usbDescriptorDevice) + SWITCH_CASE(USBDESCR_CONFIG) /* 2 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_CONFIGURATION, usbDescriptorConfiguration) + SWITCH_CASE(USBDESCR_STRING) /* 3 */ +#if USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC + if(USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_RAM) + flags = 0; + len = usbFunctionDescriptor(rq); +#else /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */ + SWITCH_START(rq->wValue.bytes[0]) + SWITCH_CASE(0) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_0, usbDescriptorString0) + SWITCH_CASE(1) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_VENDOR, usbDescriptorStringVendor) + SWITCH_CASE(2) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_PRODUCT, usbDescriptorStringDevice) + SWITCH_CASE(3) + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER, usbDescriptorStringSerialNumber) + SWITCH_DEFAULT + if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){ + len = usbFunctionDescriptor(rq); + } + SWITCH_END +#endif /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */ +#if USB_CFG_DESCR_PROPS_HID_REPORT /* only support HID descriptors if enabled */ + SWITCH_CASE(USBDESCR_HID) /* 0x21 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID, usbDescriptorConfiguration + 18) + SWITCH_CASE(USBDESCR_HID_REPORT)/* 0x22 */ + GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID_REPORT, usbDescriptorHidReport) +#endif + SWITCH_DEFAULT + if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){ + len = usbFunctionDescriptor(rq); + } + SWITCH_END + usbMsgFlags = flags; + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbDriverSetup() is similar to usbFunctionSetup(), but it's used for + * standard requests instead of class and custom requests. + */ +static inline usbMsgLen_t usbDriverSetup(usbRequest_t *rq) +{ +uchar len = 0, *dataPtr = usbTxBuf + 9; /* there are 2 bytes free space at the end of the buffer */ +uchar value = rq->wValue.bytes[0]; +#if USB_CFG_IMPLEMENT_HALT +uchar index = rq->wIndex.bytes[0]; +#endif + + dataPtr[0] = 0; /* default reply common to USBRQ_GET_STATUS and USBRQ_GET_INTERFACE */ + SWITCH_START(rq->bRequest) + SWITCH_CASE(USBRQ_GET_STATUS) /* 0 */ + uchar recipient = rq->bmRequestType & USBRQ_RCPT_MASK; /* assign arith ops to variables to enforce byte size */ + if(USB_CFG_IS_SELF_POWERED && recipient == USBRQ_RCPT_DEVICE) + dataPtr[0] = USB_CFG_IS_SELF_POWERED; +#if USB_CFG_IMPLEMENT_HALT + if(recipient == USBRQ_RCPT_ENDPOINT && index == 0x81) /* request status for endpoint 1 */ + dataPtr[0] = usbTxLen1 == USBPID_STALL; +#endif + dataPtr[1] = 0; + len = 2; +#if USB_CFG_IMPLEMENT_HALT + SWITCH_CASE2(USBRQ_CLEAR_FEATURE, USBRQ_SET_FEATURE) /* 1, 3 */ + if(value == 0 && index == 0x81){ /* feature 0 == HALT for endpoint == 1 */ + usbTxLen1 = rq->bRequest == USBRQ_CLEAR_FEATURE ? USBPID_NAK : USBPID_STALL; + usbResetDataToggling(); + } +#endif + SWITCH_CASE(USBRQ_SET_ADDRESS) /* 5 */ + usbNewDeviceAddr = value; + USB_SET_ADDRESS_HOOK(); + SWITCH_CASE(USBRQ_GET_DESCRIPTOR) /* 6 */ + len = usbDriverDescriptor(rq); + goto skipMsgPtrAssignment; + SWITCH_CASE(USBRQ_GET_CONFIGURATION) /* 8 */ + dataPtr = &usbConfiguration; /* send current configuration value */ + len = 1; + SWITCH_CASE(USBRQ_SET_CONFIGURATION) /* 9 */ + usbConfiguration = value; + usbResetStall(); + SWITCH_CASE(USBRQ_GET_INTERFACE) /* 10 */ + len = 1; +#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE + SWITCH_CASE(USBRQ_SET_INTERFACE) /* 11 */ + usbResetDataToggling(); + usbResetStall(); +#endif + SWITCH_DEFAULT /* 7=SET_DESCRIPTOR, 12=SYNC_FRAME */ + /* Should we add an optional hook here? */ + SWITCH_END + usbMsgPtr = dataPtr; +skipMsgPtrAssignment: + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbProcessRx() is called for every message received by the interrupt + * routine. It distinguishes between SETUP and DATA packets and processes + * them accordingly. + */ +static inline void usbProcessRx(uchar *data, uchar len) +{ +usbRequest_t *rq = (void *)data; + +/* usbRxToken can be: + * 0x2d 00101101 (USBPID_SETUP for setup data) + * 0xe1 11100001 (USBPID_OUT: data phase of setup transfer) + * 0...0x0f for OUT on endpoint X + */ + DBG2(0x10 + (usbRxToken & 0xf), data, len + 2); /* SETUP=1d, SETUP-DATA=11, OUTx=1x */ + USB_RX_USER_HOOK(data, len) +#if USB_CFG_IMPLEMENT_FN_WRITEOUT + if(usbRxToken < 0x10){ /* OUT to endpoint != 0: endpoint number in usbRxToken */ + usbFunctionWriteOut(data, len); + return; + } +#endif + if(usbRxToken == (uchar)USBPID_SETUP){ + if(len != 8) /* Setup size must be always 8 bytes. Ignore otherwise. */ + return; + usbMsgLen_t replyLen; + usbTxBuf[0] = USBPID_DATA0; /* initialize data toggling */ + usbTxLen = USBPID_NAK; /* abort pending transmit */ + usbMsgFlags = 0; + uchar type = rq->bmRequestType & USBRQ_TYPE_MASK; + if(type != USBRQ_TYPE_STANDARD){ /* standard requests are handled by driver */ + replyLen = usbFunctionSetup(data); + }else{ + replyLen = usbDriverSetup(rq); + } +#if USB_CFG_IMPLEMENT_FN_READ || USB_CFG_IMPLEMENT_FN_WRITE + if(replyLen == USB_NO_MSG){ /* use user-supplied read/write function */ + /* do some conditioning on replyLen, but on IN transfers only */ + if((rq->bmRequestType & USBRQ_DIR_MASK) != USBRQ_DIR_HOST_TO_DEVICE){ + if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */ + replyLen = rq->wLength.bytes[0]; + }else{ + replyLen = rq->wLength.word; + } + } + usbMsgFlags = USB_FLG_USE_USER_RW; + }else /* The 'else' prevents that we limit a replyLen of USB_NO_MSG to the maximum transfer len. */ +#endif + if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */ + if(!rq->wLength.bytes[1] && replyLen > rq->wLength.bytes[0]) /* limit length to max */ + replyLen = rq->wLength.bytes[0]; + }else{ + if(replyLen > rq->wLength.word) /* limit length to max */ + replyLen = rq->wLength.word; + } + usbMsgLen = replyLen; + }else{ /* usbRxToken must be USBPID_OUT, which means data phase of setup (control-out) */ +#if USB_CFG_IMPLEMENT_FN_WRITE + if(usbMsgFlags & USB_FLG_USE_USER_RW){ + uchar rval = usbFunctionWrite(data, len); + if(rval == 0xff){ /* an error occurred */ + usbTxLen = USBPID_STALL; + }else if(rval != 0){ /* This was the final package */ + usbMsgLen = 0; /* answer with a zero-sized data packet */ + } + } +#endif + } +} + +/* ------------------------------------------------------------------------- */ + +/* This function is similar to usbFunctionRead(), but it's also called for + * data handled automatically by the driver (e.g. descriptor reads). + */ +static uchar usbDeviceRead(uchar *data, uchar len) +{ + if(len > 0){ /* don't bother app with 0 sized reads */ +#if USB_CFG_IMPLEMENT_FN_READ + if(usbMsgFlags & USB_FLG_USE_USER_RW){ + len = usbFunctionRead(data, len); + }else +#endif + { + uchar i = len, *r = usbMsgPtr; + if(usbMsgFlags & USB_FLG_MSGPTR_IS_ROM){ /* ROM data */ + do{ + uchar c = USB_READ_FLASH(r); /* assign to char size variable to enforce byte ops */ + *data++ = c; + r++; + }while(--i); + }else{ /* RAM data */ + do{ + *data++ = *r++; + }while(--i); + } + usbMsgPtr = r; + } + } + return len; +} + +/* ------------------------------------------------------------------------- */ + +/* usbBuildTxBlock() is called when we have data to transmit and the + * interrupt routine's transmit buffer is empty. + */ +static inline void usbBuildTxBlock(void) +{ +usbMsgLen_t wantLen; +uchar len; + + wantLen = usbMsgLen; + if(wantLen > 8) + wantLen = 8; + usbMsgLen -= wantLen; + usbTxBuf[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* DATA toggling */ + len = usbDeviceRead(usbTxBuf + 1, wantLen); + if(len <= 8){ /* valid data packet */ + usbCrc16Append(&usbTxBuf[1], len); + len += 4; /* length including sync byte */ + if(len < 12) /* a partial package identifies end of message */ + usbMsgLen = USB_NO_MSG; + }else{ + len = USBPID_STALL; /* stall the endpoint */ + usbMsgLen = USB_NO_MSG; + } + usbTxLen = len; + DBG2(0x20, usbTxBuf, len-1); +} + +/* ------------------------------------------------------------------------- */ + +static inline void usbHandleResetHook(uchar notResetState) +{ +#ifdef USB_RESET_HOOK +static uchar wasReset; +uchar isReset = !notResetState; + + if(wasReset != isReset){ + USB_RESET_HOOK(isReset); + wasReset = isReset; + } +#endif +} + +/* ------------------------------------------------------------------------- */ + +USB_PUBLIC void usbPoll(void) +{ +schar len; +uchar i; + + len = usbRxLen - 3; + if(len >= 0){ +/* We could check CRC16 here -- but ACK has already been sent anyway. If you + * need data integrity checks with this driver, check the CRC in your app + * code and report errors back to the host. Since the ACK was already sent, + * retries must be handled on application level. + * unsigned crc = usbCrc16(buffer + 1, usbRxLen - 3); + */ + usbProcessRx(usbRxBuf + USB_BUFSIZE + 1 - usbInputBufOffset, len); +#if USB_CFG_HAVE_FLOWCONTROL + if(usbRxLen > 0) /* only mark as available if not inactivated */ + usbRxLen = 0; +#else + usbRxLen = 0; /* mark rx buffer as available */ +#endif + } + if(usbTxLen & 0x10){ /* transmit system idle */ + if(usbMsgLen != USB_NO_MSG){ /* transmit data pending? */ + usbBuildTxBlock(); + } + } + for(i = 20; i > 0; i--){ + uchar usbLineStatus = USBIN & USBMASK; + if(usbLineStatus != 0) /* SE0 has ended */ + goto isNotReset; + } + /* RESET condition, called multiple times during reset */ + usbNewDeviceAddr = 0; + usbDeviceAddr = 0; + usbResetStall(); + DBG1(0xff, 0, 0); +isNotReset: + usbHandleResetHook(i); +} + +/* ------------------------------------------------------------------------- */ + +USB_PUBLIC void usbInit(void) +{ +#if USB_INTR_CFG_SET != 0 + USB_INTR_CFG |= USB_INTR_CFG_SET; +#endif +#if USB_INTR_CFG_CLR != 0 + USB_INTR_CFG &= ~(USB_INTR_CFG_CLR); +#endif + USB_INTR_ENABLE |= (1 << USB_INTR_ENABLE_BIT); + usbResetDataToggling(); +#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE + usbTxLen1 = USBPID_NAK; +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 + usbTxLen3 = USBPID_NAK; +#endif +#endif +} + +/* ------------------------------------------------------------------------- */ diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrv.h b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrv.h new file mode 100644 index 0000000..660cb1b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrv.h @@ -0,0 +1,790 @@ +/* Name: usbdrv.h + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2004-12-29 + * Tabsize: 4 + * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbdrv.h 793 2010-07-15 15:58:11Z cs $ + */ + +#ifndef __usbdrv_h_included__ +#define __usbdrv_h_included__ +#include "usbconfig.h" +#include "usbportability.h" + +/* +Hardware Prerequisites: +======================= +USB lines D+ and D- MUST be wired to the same I/O port. We recommend that D+ +triggers the interrupt (best achieved by using INT0 for D+), but it is also +possible to trigger the interrupt from D-. If D- is used, interrupts are also +triggered by SOF packets. D- requires a pull-up of 1.5k to +3.5V (and the +device must be powered at 3.5V) to identify as low-speed USB device. A +pull-down or pull-up of 1M SHOULD be connected from D+ to +3.5V to prevent +interference when no USB master is connected. If you use Zener diodes to limit +the voltage on D+ and D-, you MUST use a pull-down resistor, not a pull-up. +We use D+ as interrupt source and not D- because it does not trigger on +keep-alive and RESET states. If you want to count keep-alive events with +USB_COUNT_SOF, you MUST use D- as an interrupt source. + +As a compile time option, the 1.5k pull-up resistor on D- can be made +switchable to allow the device to disconnect at will. See the definition of +usbDeviceConnect() and usbDeviceDisconnect() further down in this file. + +Please adapt the values in usbconfig.h according to your hardware! + +The device MUST be clocked at exactly 12 MHz, 15 MHz, 16 MHz or 20 MHz +or at 12.8 MHz resp. 16.5 MHz +/- 1%. See usbconfig-prototype.h for details. + + +Limitations: +============ +Robustness with respect to communication errors: +The driver assumes error-free communication. It DOES check for errors in +the PID, but does NOT check bit stuffing errors, SE0 in middle of a byte, +token CRC (5 bit) and data CRC (16 bit). CRC checks can not be performed due +to timing constraints: We must start sending a reply within 7 bit times. +Bit stuffing and misplaced SE0 would have to be checked in real-time, but CPU +performance does not permit that. The driver does not check Data0/Data1 +toggling, but application software can implement the check. + +Input characteristics: +Since no differential receiver circuit is used, electrical interference +robustness may suffer. The driver samples only one of the data lines with +an ordinary I/O pin's input characteristics. However, since this is only a +low speed USB implementation and the specification allows for 8 times the +bit rate over the same hardware, we should be on the safe side. Even the spec +requires detection of asymmetric states at high bit rate for SE0 detection. + +Number of endpoints: +The driver supports the following endpoints: + +- Endpoint 0, the default control endpoint. +- Any number of interrupt- or bulk-out endpoints. The data is sent to + usbFunctionWriteOut() and USB_CFG_IMPLEMENT_FN_WRITEOUT must be defined + to 1 to activate this feature. The endpoint number can be found in the + global variable 'usbRxToken'. +- One default interrupt- or bulk-in endpoint. This endpoint is used for + interrupt- or bulk-in transfers which are not handled by any other endpoint. + You must define USB_CFG_HAVE_INTRIN_ENDPOINT in order to activate this + feature and call usbSetInterrupt() to send interrupt/bulk data. +- One additional interrupt- or bulk-in endpoint. This was endpoint 3 in + previous versions of this driver but can now be configured to any endpoint + number. You must define USB_CFG_HAVE_INTRIN_ENDPOINT3 in order to activate + this feature and call usbSetInterrupt3() to send interrupt/bulk data. The + endpoint number can be set with USB_CFG_EP3_NUMBER. + +Please note that the USB standard forbids bulk endpoints for low speed devices! +Most operating systems allow them anyway, but the AVR will spend 90% of the CPU +time in the USB interrupt polling for bulk data. + +Maximum data payload: +Data payload of control in and out transfers may be up to 254 bytes. In order +to accept payload data of out transfers, you need to implement +'usbFunctionWrite()'. + +USB Suspend Mode supply current: +The USB standard limits power consumption to 500uA when the bus is in suspend +mode. This is not a problem for self-powered devices since they don't need +bus power anyway. Bus-powered devices can achieve this only by putting the +CPU in sleep mode. The driver does not implement suspend handling by itself. +However, the application may implement activity monitoring and wakeup from +sleep. The host sends regular SE0 states on the bus to keep it active. These +SE0 states can be detected by using D- as the interrupt source. Define +USB_COUNT_SOF to 1 and use the global variable usbSofCount to check for bus +activity. + +Operation without an USB master: +The driver behaves neutral without connection to an USB master if D- reads +as 1. To avoid spurious interrupts, we recommend a high impedance (e.g. 1M) +pull-down or pull-up resistor on D+ (interrupt). If Zener diodes are used, +use a pull-down. If D- becomes statically 0, the driver may block in the +interrupt routine. + +Interrupt latency: +The application must ensure that the USB interrupt is not disabled for more +than 25 cycles (this is for 12 MHz, faster clocks allow longer latency). +This implies that all interrupt routines must either have the "ISR_NOBLOCK" +attribute set (see "avr/interrupt.h") or be written in assembler with "sei" +as the first instruction. + +Maximum interrupt duration / CPU cycle consumption: +The driver handles all USB communication during the interrupt service +routine. The routine will not return before an entire USB message is received +and the reply is sent. This may be up to ca. 1200 cycles @ 12 MHz (= 100us) if +the host conforms to the standard. The driver will consume CPU cycles for all +USB messages, even if they address another (low-speed) device on the same bus. + +*/ + +/* ------------------------------------------------------------------------- */ +/* --------------------------- Module Interface ---------------------------- */ +/* ------------------------------------------------------------------------- */ + +#define USBDRV_VERSION 20100715 +/* This define uniquely identifies a driver version. It is a decimal number + * constructed from the driver's release date in the form YYYYMMDD. If the + * driver's behavior or interface changes, you can use this constant to + * distinguish versions. If it is not defined, the driver's release date is + * older than 2006-01-25. + */ + + +#ifndef USB_PUBLIC +#define USB_PUBLIC +#endif +/* USB_PUBLIC is used as declaration attribute for all functions exported by + * the USB driver. The default is no attribute (see above). You may define it + * to static either in usbconfig.h or from the command line if you include + * usbdrv.c instead of linking against it. Including the C module of the driver + * directly in your code saves a couple of bytes in flash memory. + */ + +#ifndef __ASSEMBLER__ +#ifndef uchar +#define uchar unsigned char +#endif +#ifndef schar +#define schar signed char +#endif +/* shortcuts for well defined 8 bit integer types */ + +#if USB_CFG_LONG_TRANSFERS /* if more than 254 bytes transfer size required */ +# define usbMsgLen_t unsigned +#else +# define usbMsgLen_t uchar +#endif +/* usbMsgLen_t is the data type used for transfer lengths. By default, it is + * defined to uchar, allowing a maximum of 254 bytes (255 is reserved for + * USB_NO_MSG below). If the usbconfig.h defines USB_CFG_LONG_TRANSFERS to 1, + * a 16 bit data type is used, allowing up to 16384 bytes (the rest is used + * for flags in the descriptor configuration). + */ +#define USB_NO_MSG ((usbMsgLen_t)-1) /* constant meaning "no message" */ + +struct usbRequest; /* forward declaration */ + +#ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbInit(void); +/* This function must be called before interrupts are enabled and the main + * loop is entered. We exepct that the PORT and DDR bits for D+ and D- have + * not been changed from their default status (which is 0). If you have changed + * them, set both back to 0 (configure them as input with no internal pull-up). + */ +USB_PUBLIC void usbPoll(void); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function must be called at regular intervals from the main loop. + * Maximum delay between calls is somewhat less than 50ms (USB timeout for + * accepting a Setup message). Otherwise the device will not be recognized. + * Please note that debug outputs through the UART take ~ 0.5ms per byte + * at 19200 bps. + */ +extern uchar *usbMsgPtr; +/* This variable may be used to pass transmit data to the driver from the + * implementation of usbFunctionWrite(). It is also used internally by the + * driver for standard control requests. + */ + #ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC usbMsgLen_t usbFunctionSetup(uchar data[8]); +/* This function is called when the driver receives a SETUP transaction from + * the host which is not answered by the driver itself (in practice: class and + * vendor requests). All control transfers start with a SETUP transaction where + * the host communicates the parameters of the following (optional) data + * transfer. The SETUP data is available in the 'data' parameter which can + * (and should) be casted to 'usbRequest_t *' for a more user-friendly access + * to parameters. + * + * If the SETUP indicates a control-in transfer, you should provide the + * requested data to the driver. There are two ways to transfer this data: + * (1) Set the global pointer 'usbMsgPtr' to the base of the static RAM data + * block and return the length of the data in 'usbFunctionSetup()'. The driver + * will handle the rest. Or (2) return USB_NO_MSG in 'usbFunctionSetup()'. The + * driver will then call 'usbFunctionRead()' when data is needed. See the + * documentation for usbFunctionRead() for details. + * + * If the SETUP indicates a control-out transfer, the only way to receive the + * data from the host is through the 'usbFunctionWrite()' call. If you + * implement this function, you must return USB_NO_MSG in 'usbFunctionSetup()' + * to indicate that 'usbFunctionWrite()' should be used. See the documentation + * of this function for more information. If you just want to ignore the data + * sent by the host, return 0 in 'usbFunctionSetup()'. + * + * Note that calls to the functions usbFunctionRead() and usbFunctionWrite() + * are only done if enabled by the configuration in usbconfig.h. + */ +USB_PUBLIC usbMsgLen_t usbFunctionDescriptor(struct usbRequest *rq); + +#ifdef __cplusplus +} // extern "C" +#endif +/* You need to implement this function ONLY if you provide USB descriptors at + * runtime (which is an expert feature). It is very similar to + * usbFunctionSetup() above, but it is called only to request USB descriptor + * data. See the documentation of usbFunctionSetup() above for more info. + */ +#if USB_CFG_HAVE_INTRIN_ENDPOINT + #ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function sets the message which will be sent during the next interrupt + * IN transfer. The message is copied to an internal buffer and must not exceed + * a length of 8 bytes. The message may be 0 bytes long just to indicate the + * interrupt status to the host. + * If you need to transfer more bytes, use a control read after the interrupt. + */ +#define usbInterruptIsReady() (usbTxLen1 & 0x10) +/* This macro indicates whether the last interrupt message has already been + * sent. If you set a new interrupt message before the old was sent, the + * message already buffered will be lost. + */ +#if USB_CFG_HAVE_INTRIN_ENDPOINT3 + #ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +#define usbInterruptIsReady3() (usbTxLen3 & 0x10) +/* Same as above for endpoint 3 */ +#endif +#endif /* USB_CFG_HAVE_INTRIN_ENDPOINT */ +#if USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH /* simplified interface for backward compatibility */ +#define usbHidReportDescriptor usbDescriptorHidReport +/* should be declared as: const PROGMEM char usbHidReportDescriptor[]; */ +/* If you implement an HID device, you need to provide a report descriptor. + * The HID report descriptor syntax is a bit complex. If you understand how + * report descriptors are constructed, we recommend that you use the HID + * Descriptor Tool from usb.org, see http://www.usb.org/developers/hidpage/. + * Otherwise you should probably start with a working example. + */ +#endif /* USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH */ +#if USB_CFG_IMPLEMENT_FN_WRITE + #ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC uchar usbFunctionWrite(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function is called by the driver to provide a control transfer's + * payload data (control-out). It is called in chunks of up to 8 bytes. The + * total count provided in the current control transfer can be obtained from + * the 'length' property in the setup data. If an error occurred during + * processing, return 0xff (== -1). The driver will answer the entire transfer + * with a STALL token in this case. If you have received the entire payload + * successfully, return 1. If you expect more data, return 0. If you don't + * know whether the host will send more data (you should know, the total is + * provided in the usbFunctionSetup() call!), return 1. + * NOTE: If you return 0xff for STALL, 'usbFunctionWrite()' may still be called + * for the remaining data. You must continue to return 0xff for STALL in these + * calls. + * In order to get usbFunctionWrite() called, define USB_CFG_IMPLEMENT_FN_WRITE + * to 1 in usbconfig.h and return 0xff in usbFunctionSetup().. + */ +#endif /* USB_CFG_IMPLEMENT_FN_WRITE */ +#if USB_CFG_IMPLEMENT_FN_READ + #ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC uchar usbFunctionRead(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function is called by the driver to ask the application for a control + * transfer's payload data (control-in). It is called in chunks of up to 8 + * bytes each. You should copy the data to the location given by 'data' and + * return the actual number of bytes copied. If you return less than requested, + * the control-in transfer is terminated. If you return 0xff, the driver aborts + * the transfer with a STALL token. + * In order to get usbFunctionRead() called, define USB_CFG_IMPLEMENT_FN_READ + * to 1 in usbconfig.h and return 0xff in usbFunctionSetup().. + */ +#endif /* USB_CFG_IMPLEMENT_FN_READ */ + +extern uchar usbRxToken; /* may be used in usbFunctionWriteOut() below */ +#if USB_CFG_IMPLEMENT_FN_WRITEOUT + #ifdef __cplusplus +extern "C"{ +#endif +USB_PUBLIC void usbFunctionWriteOut(uchar *data, uchar len); +#ifdef __cplusplus +} // extern "C" +#endif +/* This function is called by the driver when data is received on an interrupt- + * or bulk-out endpoint. The endpoint number can be found in the global + * variable usbRxToken. You must define USB_CFG_IMPLEMENT_FN_WRITEOUT to 1 in + * usbconfig.h to get this function called. + */ +#endif /* USB_CFG_IMPLEMENT_FN_WRITEOUT */ +#ifdef USB_CFG_PULLUP_IOPORTNAME +#define usbDeviceConnect() ((USB_PULLUP_DDR |= (1<device, 1=device->host + * t ..... type: 0=standard, 1=class, 2=vendor, 3=reserved + * r ..... recipient: 0=device, 1=interface, 2=endpoint, 3=other + */ + +/* USB setup recipient values */ +#define USBRQ_RCPT_MASK 0x1f +#define USBRQ_RCPT_DEVICE 0 +#define USBRQ_RCPT_INTERFACE 1 +#define USBRQ_RCPT_ENDPOINT 2 + +/* USB request type values */ +#define USBRQ_TYPE_MASK 0x60 +#define USBRQ_TYPE_STANDARD (0<<5) +#define USBRQ_TYPE_CLASS (1<<5) +#define USBRQ_TYPE_VENDOR (2<<5) + +/* USB direction values: */ +#define USBRQ_DIR_MASK 0x80 +#define USBRQ_DIR_HOST_TO_DEVICE (0<<7) +#define USBRQ_DIR_DEVICE_TO_HOST (1<<7) + +/* USB Standard Requests */ +#define USBRQ_GET_STATUS 0 +#define USBRQ_CLEAR_FEATURE 1 +#define USBRQ_SET_FEATURE 3 +#define USBRQ_SET_ADDRESS 5 +#define USBRQ_GET_DESCRIPTOR 6 +#define USBRQ_SET_DESCRIPTOR 7 +#define USBRQ_GET_CONFIGURATION 8 +#define USBRQ_SET_CONFIGURATION 9 +#define USBRQ_GET_INTERFACE 10 +#define USBRQ_SET_INTERFACE 11 +#define USBRQ_SYNCH_FRAME 12 + +/* USB descriptor constants */ +#define USBDESCR_DEVICE 1 +#define USBDESCR_CONFIG 2 +#define USBDESCR_STRING 3 +#define USBDESCR_INTERFACE 4 +#define USBDESCR_ENDPOINT 5 +#define USBDESCR_HID 0x21 +#define USBDESCR_HID_REPORT 0x22 +#define USBDESCR_HID_PHYS 0x23 + +//#define USBATTR_BUSPOWER 0x80 // USB 1.1 does not define this value any more +#define USBATTR_SELFPOWER 0x40 +#define USBATTR_REMOTEWAKE 0x20 + +/* USB HID Requests */ +#define USBRQ_HID_GET_REPORT 0x01 +#define USBRQ_HID_GET_IDLE 0x02 +#define USBRQ_HID_GET_PROTOCOL 0x03 +#define USBRQ_HID_SET_REPORT 0x09 +#define USBRQ_HID_SET_IDLE 0x0a +#define USBRQ_HID_SET_PROTOCOL 0x0b + +/* ------------------------------------------------------------------------- */ + +#endif /* __usbdrv_h_included__ */ diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm.S b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm.S new file mode 100644 index 0000000..45fcf18 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm.S @@ -0,0 +1,393 @@ +/* Name: usbdrvasm.S + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2007-06-13 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm.S 785 2010-05-30 17:57:07Z cs $ + */ + +/* +General Description: +This module is the assembler part of the USB driver. This file contains +general code (preprocessor acrobatics and CRC computation) and then includes +the file appropriate for the given clock rate. +*/ + +#define __SFR_OFFSET 0 /* used by avr-libc's register definitions */ +#include "usbportability.h" +#include "usbdrv.h" /* for common defs */ + +/* register names */ +#define x1 r16 +#define x2 r17 +#define shift r18 +#define cnt r19 +#define x3 r20 +#define x4 r21 +#define x5 r22 +#define bitcnt x5 +#define phase x4 +#define leap x4 + +/* Some assembler dependent definitions and declarations: */ + +#ifdef __IAR_SYSTEMS_ASM__ + extern usbRxBuf, usbDeviceAddr, usbNewDeviceAddr, usbInputBufOffset + extern usbCurrentTok, usbRxLen, usbRxToken, usbTxLen + extern usbTxBuf, usbTxStatus1, usbTxStatus3 +# if USB_COUNT_SOF + extern usbSofCount +# endif + public usbCrc16 + public usbCrc16Append + + COMMON INTVEC +# ifndef USB_INTR_VECTOR + ORG INT0_vect +# else /* USB_INTR_VECTOR */ + ORG USB_INTR_VECTOR +# undef USB_INTR_VECTOR +# endif /* USB_INTR_VECTOR */ +# define USB_INTR_VECTOR usbInterruptHandler + rjmp USB_INTR_VECTOR + RSEG CODE + +#else /* __IAR_SYSTEMS_ASM__ */ + +# ifndef USB_INTR_VECTOR /* default to hardware interrupt INT0 */ +# ifdef INT0_vect +# define USB_INTR_VECTOR INT0_vect // this is the "new" define for the vector +# else +# define USB_INTR_VECTOR SIG_INTERRUPT0 // this is the "old" vector +# endif +# endif + .text + .global USB_INTR_VECTOR + .type USB_INTR_VECTOR, @function + .global usbCrc16 + .global usbCrc16Append +#endif /* __IAR_SYSTEMS_ASM__ */ + + +#if USB_INTR_PENDING < 0x40 /* This is an I/O address, use in and out */ +# define USB_LOAD_PENDING(reg) in reg, USB_INTR_PENDING +# define USB_STORE_PENDING(reg) out USB_INTR_PENDING, reg +#else /* It's a memory address, use lds and sts */ +# define USB_LOAD_PENDING(reg) lds reg, USB_INTR_PENDING +# define USB_STORE_PENDING(reg) sts USB_INTR_PENDING, reg +#endif + +#define usbTxLen1 usbTxStatus1 +#define usbTxBuf1 (usbTxStatus1 + 1) +#define usbTxLen3 usbTxStatus3 +#define usbTxBuf3 (usbTxStatus3 + 1) + + +;---------------------------------------------------------------------------- +; Utility functions +;---------------------------------------------------------------------------- + +#ifdef __IAR_SYSTEMS_ASM__ +/* Register assignments for usbCrc16 on IAR cc */ +/* Calling conventions on IAR: + * First parameter passed in r16/r17, second in r18/r19 and so on. + * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer) + * Result is passed in r16/r17 + * In case of the "tiny" memory model, pointers are only 8 bit with no + * padding. We therefore pass argument 1 as "16 bit unsigned". + */ +RTMODEL "__rt_version", "3" +/* The line above will generate an error if cc calling conventions change. + * The value "3" above is valid for IAR 4.10B/W32 + */ +# define argLen r18 /* argument 2 */ +# define argPtrL r16 /* argument 1 */ +# define argPtrH r17 /* argument 1 */ + +# define resCrcL r16 /* result */ +# define resCrcH r17 /* result */ + +# define ptrL ZL +# define ptrH ZH +# define ptr Z +# define byte r22 +# define bitCnt r19 +# define polyL r20 +# define polyH r21 +# define scratch r23 + +#else /* __IAR_SYSTEMS_ASM__ */ +/* Register assignments for usbCrc16 on gcc */ +/* Calling conventions on gcc: + * First parameter passed in r24/r25, second in r22/23 and so on. + * Callee must preserve r1-r17, r28/r29 + * Result is passed in r24/r25 + */ +# define argLen r22 /* argument 2 */ +# define argPtrL r24 /* argument 1 */ +# define argPtrH r25 /* argument 1 */ + +# define resCrcL r24 /* result */ +# define resCrcH r25 /* result */ + +# define ptrL XL +# define ptrH XH +# define ptr x +# define byte r18 +# define bitCnt r19 +# define polyL r20 +# define polyH r21 +# define scratch r23 + +#endif + +#if USB_USE_FAST_CRC + +; This implementation is faster, but has bigger code size +; Thanks to Slawomir Fras (BoskiDialer) for this code! +; It implements the following C pseudo-code: +; unsigned table(unsigned char x) +; { +; unsigned value; +; +; value = (unsigned)x << 6; +; value ^= (unsigned)x << 7; +; if(parity(x)) +; value ^= 0xc001; +; return value; +; } +; unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen) +; { +; unsigned crc = 0xffff; +; +; while(argLen--) +; crc = table(lo8(crc) ^ *argPtr++) ^ hi8(crc); +; return ~crc; +; } + +; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen); +; argPtr r24+25 / r16+r17 +; argLen r22 / r18 +; temp variables: +; byte r18 / r22 +; scratch r23 +; resCrc r24+r25 / r16+r17 +; ptr X / Z +usbCrc16: + mov ptrL, argPtrL + mov ptrH, argPtrH + ldi resCrcL, 0xFF + ldi resCrcH, 0xFF + rjmp usbCrc16LoopTest +usbCrc16ByteLoop: + ld byte, ptr+ + eor resCrcL, byte ; resCrcL is now 'x' in table() + mov byte, resCrcL ; compute parity of 'x' + swap byte + eor byte, resCrcL + mov scratch, byte + lsr byte + lsr byte + eor byte, scratch + inc byte + lsr byte + andi byte, 1 ; byte is now parity(x) + mov scratch, resCrcL + mov resCrcL, resCrcH + eor resCrcL, byte ; low byte of if(parity(x)) value ^= 0xc001; + neg byte + andi byte, 0xc0 + mov resCrcH, byte ; high byte of if(parity(x)) value ^= 0xc001; + clr byte + lsr scratch + ror byte + eor resCrcH, scratch + eor resCrcL, byte + lsr scratch + ror byte + eor resCrcH, scratch + eor resCrcL, byte +usbCrc16LoopTest: + subi argLen, 1 + brsh usbCrc16ByteLoop + com resCrcL + com resCrcH + ret + +#else /* USB_USE_FAST_CRC */ + +; This implementation is slower, but has less code size +; +; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen); +; argPtr r24+25 / r16+r17 +; argLen r22 / r18 +; temp variables: +; byte r18 / r22 +; bitCnt r19 +; poly r20+r21 +; scratch r23 +; resCrc r24+r25 / r16+r17 +; ptr X / Z +usbCrc16: + mov ptrL, argPtrL + mov ptrH, argPtrH + ldi resCrcL, 0 + ldi resCrcH, 0 + ldi polyL, lo8(0xa001) + ldi polyH, hi8(0xa001) + com argLen ; argLen = -argLen - 1: modified loop to ensure that carry is set + ldi bitCnt, 0 ; loop counter with starnd condition = end condition + rjmp usbCrcLoopEntry +usbCrcByteLoop: + ld byte, ptr+ + eor resCrcL, byte +usbCrcBitLoop: + ror resCrcH ; carry is always set here (see brcs jumps to here) + ror resCrcL + brcs usbCrcNoXor + eor resCrcL, polyL + eor resCrcH, polyH +usbCrcNoXor: + subi bitCnt, 224 ; (8 * 224) % 256 = 0; this loop iterates 8 times + brcs usbCrcBitLoop +usbCrcLoopEntry: + subi argLen, -1 + brcs usbCrcByteLoop +usbCrcReady: + ret +; Thanks to Reimar Doeffinger for optimizing this CRC routine! + +#endif /* USB_USE_FAST_CRC */ + +; extern unsigned usbCrc16Append(unsigned char *data, unsigned char len); +usbCrc16Append: + rcall usbCrc16 + st ptr+, resCrcL + st ptr+, resCrcH + ret + +#undef argLen +#undef argPtrL +#undef argPtrH +#undef resCrcL +#undef resCrcH +#undef ptrL +#undef ptrH +#undef ptr +#undef byte +#undef bitCnt +#undef polyL +#undef polyH +#undef scratch + + +#if USB_CFG_HAVE_MEASURE_FRAME_LENGTH +#ifdef __IAR_SYSTEMS_ASM__ +/* Register assignments for usbMeasureFrameLength on IAR cc */ +/* Calling conventions on IAR: + * First parameter passed in r16/r17, second in r18/r19 and so on. + * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer) + * Result is passed in r16/r17 + * In case of the "tiny" memory model, pointers are only 8 bit with no + * padding. We therefore pass argument 1 as "16 bit unsigned". + */ +# define resL r16 +# define resH r17 +# define cnt16L r30 +# define cnt16H r31 +# define cntH r18 + +#else /* __IAR_SYSTEMS_ASM__ */ +/* Register assignments for usbMeasureFrameLength on gcc */ +/* Calling conventions on gcc: + * First parameter passed in r24/r25, second in r22/23 and so on. + * Callee must preserve r1-r17, r28/r29 + * Result is passed in r24/r25 + */ +# define resL r24 +# define resH r25 +# define cnt16L r24 +# define cnt16H r25 +# define cntH r26 +#endif +# define cnt16 cnt16L + +; extern unsigned usbMeasurePacketLength(void); +; returns time between two idle strobes in multiples of 7 CPU clocks +.global usbMeasureFrameLength +usbMeasureFrameLength: + ldi cntH, 6 ; wait ~ 10 ms for D- == 0 + clr cnt16L + clr cnt16H +usbMFTime16: + dec cntH + breq usbMFTimeout +usbMFWaitStrobe: ; first wait for D- == 0 (idle strobe) + sbiw cnt16, 1 ;[0] [6] + breq usbMFTime16 ;[2] + sbic USBIN, USBMINUS ;[3] + rjmp usbMFWaitStrobe ;[4] +usbMFWaitIdle: ; then wait until idle again + sbis USBIN, USBMINUS ;1 wait for D- == 1 + rjmp usbMFWaitIdle ;2 + ldi cnt16L, 1 ;1 represents cycles so far + clr cnt16H ;1 +usbMFWaitLoop: + in cntH, USBIN ;[0] [7] + adiw cnt16, 1 ;[1] + breq usbMFTimeout ;[3] + andi cntH, USBMASK ;[4] + brne usbMFWaitLoop ;[5] +usbMFTimeout: +#if resL != cnt16L + mov resL, cnt16L + mov resH, cnt16H +#endif + ret + +#undef resL +#undef resH +#undef cnt16 +#undef cnt16L +#undef cnt16H +#undef cntH + +#endif /* USB_CFG_HAVE_MEASURE_FRAME_LENGTH */ + +;---------------------------------------------------------------------------- +; Now include the clock rate specific code +;---------------------------------------------------------------------------- + +#ifndef USB_CFG_CLOCK_KHZ +# ifdef F_CPU +# define USB_CFG_CLOCK_KHZ (F_CPU/1000) +# else +# error "USB_CFG_CLOCK_KHZ not defined in usbconfig.h and no F_CPU set!" +# endif +#endif + +#if USB_CFG_CHECK_CRC /* separate dispatcher for CRC type modules */ +# if USB_CFG_CLOCK_KHZ == 18000 +# include "usbdrvasm18-crc.inc" +# else +# error "USB_CFG_CLOCK_KHZ is not one of the supported crc-rates!" +# endif +#else /* USB_CFG_CHECK_CRC */ +# if USB_CFG_CLOCK_KHZ == 12000 +# include "usbdrvasm12.inc" +# elif USB_CFG_CLOCK_KHZ == 12800 +# include "usbdrvasm128.inc" +# elif USB_CFG_CLOCK_KHZ == 15000 +# include "usbdrvasm15.inc" +# elif USB_CFG_CLOCK_KHZ == 16000 +# include "usbdrvasm16.inc" +# elif USB_CFG_CLOCK_KHZ == 16500 +# include "usbdrvasm165.inc" +# elif USB_CFG_CLOCK_KHZ == 20000 +# include "usbdrvasm20.inc" +# else +# error "USB_CFG_CLOCK_KHZ is not one of the supported non-crc-rates!" +# endif +#endif /* USB_CFG_CHECK_CRC */ diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm.asm b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm.asm new file mode 100644 index 0000000..9cc4e4d --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm.asm @@ -0,0 +1,21 @@ +/* Name: usbdrvasm.asm + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2006-03-01 + * Tabsize: 4 + * Copyright: (c) 2006 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id$ + */ + +/* +General Description: +The IAR compiler/assembler system prefers assembler files with file extension +".asm". We simply provide this file as an alias for usbdrvasm.S. + +Thanks to Oleg Semyonov for his help with the IAR tools port! +*/ + +#include "usbdrvasm.S" + +end diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm12.inc b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm12.inc new file mode 100644 index 0000000..c116758 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm12.inc @@ -0,0 +1,393 @@ +/* Name: usbdrvasm12.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Christian Starkjohann + * Creation Date: 2004-12-29 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * This Revision: $Id: usbdrvasm12.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 12 MHz version of the asssembler part of the USB driver. It +requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! + + +Timing constraints according to spec (in bit times): +timing subject min max CPUcycles +--------------------------------------------------------------------------- +EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128 +EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60 +DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60 +*/ + +;Software-receiver engine. Strict timing! Don't change unless you can preserve timing! +;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled +;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable +;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes +;Numbers in brackets are maximum cycles since SOF. +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt + push YL ;2 [35] push only what is necessary to sync with edge ASAP + in YL, SREG ;1 [37] + push YL ;2 [39] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of 1/4 bit which meets the spec. + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push YH ;2 [2] + lds YL, usbInputBufOffset;2 [4] + clr YH ;1 [5] + subi YL, lo8(-(usbRxBuf));1 [6] + sbci YH, hi8(-(usbRxBuf));1 [7] + + sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early] + rjmp haveTwoBitsK ;2 [10] + pop YH ;2 [11] undo the push from before + rjmp waitForK ;2 [13] this was not the end of sync, retry +haveTwoBitsK: +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- + push shift ;2 [16] + push x1 ;2 [12] + push x2 ;2 [14] + + in x1, USBIN ;1 [17] <-- sample bit 0 + ldi shift, 0xff ;1 [18] + bst x1, USBMINUS ;1 [19] + bld shift, 0 ;1 [20] + push x3 ;2 [22] + push cnt ;2 [24] + + in x2, USBIN ;1 [25] <-- sample bit 1 + ser x3 ;1 [26] [inserted init instruction] + eor x1, x2 ;1 [27] + bst x1, USBMINUS ;1 [28] + bld shift, 1 ;1 [29] + ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction] + rjmp rxbit2 ;2 [32] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- + +unstuff0: ;1 (branch taken) + andi x3, ~0x01 ;1 [15] + mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit + in x2, USBIN ;1 [17] <-- sample bit 1 again + ori shift, 0x01 ;1 [18] + rjmp didUnstuff0 ;2 [20] + +unstuff1: ;1 (branch taken) + mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit + andi x3, ~0x02 ;1 [22] + ori shift, 0x02 ;1 [23] + nop ;1 [24] + in x1, USBIN ;1 [25] <-- sample bit 2 again + rjmp didUnstuff1 ;2 [27] + +unstuff2: ;1 (branch taken) + andi x3, ~0x04 ;1 [29] + ori shift, 0x04 ;1 [30] + mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit + nop ;1 [32] + in x2, USBIN ;1 [33] <-- sample bit 3 + rjmp didUnstuff2 ;2 [35] + +unstuff3: ;1 (branch taken) + in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late] + andi x3, ~0x08 ;1 [35] + ori shift, 0x08 ;1 [36] + rjmp didUnstuff3 ;2 [38] + +unstuff4: ;1 (branch taken) + andi x3, ~0x10 ;1 [40] + in x1, USBIN ;1 [41] <-- sample stuffed bit 4 + ori shift, 0x10 ;1 [42] + rjmp didUnstuff4 ;2 [44] + +unstuff5: ;1 (branch taken) + andi x3, ~0x20 ;1 [48] + in x2, USBIN ;1 [49] <-- sample stuffed bit 5 + ori shift, 0x20 ;1 [50] + rjmp didUnstuff5 ;2 [52] + +unstuff6: ;1 (branch taken) + andi x3, ~0x40 ;1 [56] + in x1, USBIN ;1 [57] <-- sample stuffed bit 6 + ori shift, 0x40 ;1 [58] + rjmp didUnstuff6 ;2 [60] + +; extra jobs done during bit interval: +; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs] +; bit 1: se0 check +; bit 2: overflow check +; bit 3: recovery from delay [bit 0 tasks took too long] +; bit 4: none +; bit 5: none +; bit 6: none +; bit 7: jump, eor +rxLoop: + eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others + in x1, USBIN ;1 [1] <-- sample bit 0 + st y+, x3 ;2 [3] store data + ser x3 ;1 [4] + nop ;1 [5] + eor x2, x1 ;1 [6] + bst x2, USBMINUS;1 [7] + bld shift, 0 ;1 [8] + in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed) + andi x2, USBMASK ;1 [10] + breq se0 ;1 [11] SE0 check for bit 1 + andi shift, 0xf9 ;1 [12] +didUnstuff0: + breq unstuff0 ;1 [13] + eor x1, x2 ;1 [14] + bst x1, USBMINUS;1 [15] + bld shift, 1 ;1 [16] +rxbit2: + in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed) + andi shift, 0xf3 ;1 [18] + breq unstuff1 ;1 [19] do remaining work for bit 1 +didUnstuff1: + subi cnt, 1 ;1 [20] + brcs overflow ;1 [21] loop control + eor x2, x1 ;1 [22] + bst x2, USBMINUS;1 [23] + bld shift, 2 ;1 [24] + in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed) + andi shift, 0xe7 ;1 [26] + breq unstuff2 ;1 [27] +didUnstuff2: + eor x1, x2 ;1 [28] + bst x1, USBMINUS;1 [29] + bld shift, 3 ;1 [30] +didUnstuff3: + andi shift, 0xcf ;1 [31] + breq unstuff3 ;1 [32] + in x1, USBIN ;1 [33] <-- sample bit 4 + eor x2, x1 ;1 [34] + bst x2, USBMINUS;1 [35] + bld shift, 4 ;1 [36] +didUnstuff4: + andi shift, 0x9f ;1 [37] + breq unstuff4 ;1 [38] + nop2 ;2 [40] + in x2, USBIN ;1 [41] <-- sample bit 5 + eor x1, x2 ;1 [42] + bst x1, USBMINUS;1 [43] + bld shift, 5 ;1 [44] +didUnstuff5: + andi shift, 0x3f ;1 [45] + breq unstuff5 ;1 [46] + nop2 ;2 [48] + in x1, USBIN ;1 [49] <-- sample bit 6 + eor x2, x1 ;1 [50] + bst x2, USBMINUS;1 [51] + bld shift, 6 ;1 [52] +didUnstuff6: + cpi shift, 0x02 ;1 [53] + brlo unstuff6 ;1 [54] + nop2 ;2 [56] + in x2, USBIN ;1 [57] <-- sample bit 7 + eor x1, x2 ;1 [58] + bst x1, USBMINUS;1 [59] + bld shift, 7 ;1 [60] +didUnstuff7: + cpi shift, 0x04 ;1 [61] + brsh rxLoop ;2 [63] loop control +unstuff7: + andi x3, ~0x80 ;1 [63] + ori shift, 0x80 ;1 [64] + in x2, USBIN ;1 [65] <-- sample stuffed bit 7 + nop ;1 [66] + rjmp didUnstuff7 ;2 [68] + +macro POP_STANDARD ; 12 cycles + pop cnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;---------------------------------------------------------------------------- +; Transmitting data +;---------------------------------------------------------------------------- + +txByteLoop: +txBitloop: +stuffN1Delay: ; [03] + ror shift ;[-5] [11] [59] + brcc doExorN1 ;[-4] [60] + subi x4, 1 ;[-3] + brne commonN1 ;[-2] + lsl shift ;[-1] compensate ror after rjmp stuffDelay + nop ;[00] stuffing consists of just waiting 8 cycles + rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear + +sendNakAndReti: ;0 [-19] 19 cycles until SOP + ldi x3, USBPID_NAK ;1 [-18] + rjmp usbSendX3 ;2 [-16] +sendAckAndReti: ;0 [-19] 19 cycles until SOP + ldi x3, USBPID_ACK ;1 [-18] + rjmp usbSendX3 ;2 [-16] +sendCntAndReti: ;0 [-17] 17 cycles until SOP + mov x3, cnt ;1 [-16] +usbSendX3: ;0 [-16] + ldi YL, 20 ;1 [-15] 'x3' is R20 + ldi YH, 0 ;1 [-14] + ldi cnt, 2 ;1 [-13] +; rjmp usbSendAndReti fallthrough + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) or USBOUT = 0x01 +; K = (D+ = 1), (D- = 0) or USBOUT = 0x02 +; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles) + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte +;uses: x1...x2, x4, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x4 = bitstuff cnt] +;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction) +usbSendAndReti: + in x2, USBDDR ;[-12] 12 cycles until SOP + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS ;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + out USBDDR, x2 ;[-8] <--- acquire bus + in x1, USBOUT ;[-7] port mirror for tx loop + ldi shift, 0x40 ;[-6] sync byte is first byte sent (we enter loop after ror) + ldi x2, USBMASK ;[-5] + push x4 ;[-4] +doExorN1: + eor x1, x2 ;[-2] [06] [62] + ldi x4, 6 ;[-1] [07] [63] +commonN1: +stuffN2Delay: + out USBOUT, x1 ;[00] [08] [64] <--- set bit + ror shift ;[01] + brcc doExorN2 ;[02] + subi x4, 1 ;[03] + brne commonN2 ;[04] + lsl shift ;[05] compensate ror after rjmp stuffDelay + rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear +doExorN2: + eor x1, x2 ;[04] [12] + ldi x4, 6 ;[05] [13] +commonN2: + nop ;[06] [14] + subi cnt, 171 ;[07] [15] trick: (3 * 171) & 0xff = 1 + out USBOUT, x1 ;[08] [16] <--- set bit + brcs txBitloop ;[09] [25] [41] + +stuff6Delay: + ror shift ;[42] [50] + brcc doExor6 ;[43] + subi x4, 1 ;[44] + brne common6 ;[45] + lsl shift ;[46] compensate ror after rjmp stuffDelay + nop ;[47] stuffing consists of just waiting 8 cycles + rjmp stuff6Delay ;[48] after ror, C bit is reliably clear +doExor6: + eor x1, x2 ;[45] [53] + ldi x4, 6 ;[46] +common6: +stuff7Delay: + ror shift ;[47] [55] + out USBOUT, x1 ;[48] <--- set bit + brcc doExor7 ;[49] + subi x4, 1 ;[50] + brne common7 ;[51] + lsl shift ;[52] compensate ror after rjmp stuffDelay + rjmp stuff7Delay ;[53] after ror, C bit is reliably clear +doExor7: + eor x1, x2 ;[51] [59] + ldi x4, 6 ;[52] +common7: + ld shift, y+ ;[53] + tst cnt ;[55] + out USBOUT, x1 ;[56] <--- set bit + brne txByteLoop ;[57] + +;make SE0: + cbr x1, USBMASK ;[58] prepare SE0 [spec says EOP may be 15 to 18 cycles] + lds x2, usbNewDeviceAddr;[59] + lsl x2 ;[61] we compare with left shifted address + subi YL, 2 + 20 ;[62] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[63] + out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[01] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 12.5625 MHz +max frequency: 69.286 cycles for 8 bit -> 12.99 MHz +nominal frequency: 12.77 MHz ( = sqrt(min * max)) + +sampling positions: (next even number in range [+/- 0.5]) +cycle index range: 0 ... 66 +bits: +.5, 8.875, 17.25, 25.625, 34, 42.375, 50.75, 59.125 +[0/1], [9], [17], [25/+26], [34], [+42/43], [51], [59] + +bit number: 0 1 2 3 4 5 6 7 +spare cycles 1 2 1 2 1 1 1 0 + +operations to perform: duration cycle + ---------------- + eor fix, shift 1 -> 00 + andi phase, USBMASK 1 -> 08 + breq se0 1 -> 16 (moved to 11) + st y+, data 2 -> 24, 25 + mov data, fix 1 -> 33 + ser data 1 -> 41 + subi cnt, 1 1 -> 49 + brcs overflow 1 -> 50 + +layout of samples and operations: +[##] = sample bit +<##> = sample phase +*##* = operation + +0: *00* [01] 02 03 04 <05> 06 07 +1: *08* [09] 10 11 12 <13> 14 15 *16* +2: [17] 18 19 20 <21> 22 23 +3: *24* *25* [26] 27 28 29 <30> 31 32 +4: *33* [34] 35 36 37 <38> 39 40 +5: *41* [42] 43 44 45 <46> 47 48 +6: *49* *50* [51] 52 53 54 <55> 56 57 58 +7: [59] 60 61 62 <63> 64 65 66 +*****************************************************************************/ + +/* we prefer positive expressions (do if condition) instead of negative + * (skip if condition), therefore use defines for skip instructions: + */ +#define ifioclr sbis +#define ifioset sbic +#define ifrclr sbrs +#define ifrset sbrc + +/* The registers "fix" and "data" swap their meaning during the loop. Use + * defines to keep their name constant. + */ +#define fix x2 +#define data x1 +#undef phase /* phase has a default definition to x4 */ +#define phase x3 + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt, r0 + push YL ;2 push only what is necessary to sync with edge ASAP + in YL, SREG ;1 + push YL ;2 +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of 1/4 bit which meets the spec. + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS ;[0] + rjmp foundK ;[1] +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError + +foundK: +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push YH ;[2] + lds YL, usbInputBufOffset;[4] + clr YH ;[6] + subi YL, lo8(-(usbRxBuf));[7] + sbci YH, hi8(-(usbRxBuf));[8] + + sbis USBIN, USBMINUS ;[9] we want two bits K [we want to sample at 8 + 4 - 1.5 = 10.5] + rjmp haveTwoBitsK ;[10] + pop YH ;[11] undo the push from before + rjmp waitForK ;[13] this was not the end of sync, retry +haveTwoBitsK: +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +#define fix x2 +#define data x1 + + push shift ;[12] + push x1 ;[14] + push x2 ;[16] + ldi shift, 0x80 ;[18] prevent bit-unstuffing but init low bits to 0 + ifioset USBIN, USBMINUS ;[19] [01] <--- bit 0 [10.5 + 8 = 18.5] + ori shift, 1<<0 ;[02] + push x3 ;[03] + push cnt ;[05] + push r0 ;[07] + ifioset USBIN, USBMINUS ;[09] <--- bit 1 + ori shift, 1<<1 ;[10] + ser fix ;[11] + ldi cnt, USB_BUFSIZE ;[12] + mov data, shift ;[13] + lsl shift ;[14] + nop2 ;[15] + ifioset USBIN, USBMINUS ;[17] <--- bit 2 + ori data, 3<<2 ;[18] store in bit 2 AND bit 3 + eor shift, data ;[19] do nrzi decoding + andi data, 1<<3 ;[20] + in phase, USBIN ;[21] <- phase + brne jumpToEntryAfterSet ;[22] if USBMINS at bit 3 was 1 + nop ;[23] + rjmp entryAfterClr ;[24] +jumpToEntryAfterSet: + rjmp entryAfterSet ;[24] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +#undef fix +#define fix x1 +#undef data +#define data x2 + +bit7IsSet: + ifrclr phase, USBMINUS ;[62] check phase only if D- changed + lpm ;[63] + in phase, USBIN ;[64] <- phase (one cycle too late) + ori shift, 1 << 7 ;[65] + nop ;[66] +;;;;rjmp bit0AfterSet ; -> [00] == [67] moved block up to save jump +bit0AfterSet: + eor fix, shift ;[00] +#undef fix +#define fix x2 +#undef data +#define data x1 /* we now have result in data, fix is reset to 0xff */ + ifioclr USBIN, USBMINUS ;[01] <--- sample 0 + rjmp bit0IsClr ;[02] + andi shift, ~(7 << 0) ;[03] + breq unstuff0s ;[04] + in phase, USBIN ;[05] <- phase + rjmp bit1AfterSet ;[06] +unstuff0s: + in phase, USBIN ;[06] <- phase (one cycle too late) + andi fix, ~(1 << 0) ;[07] + ifioclr USBIN, USBMINUS ;[00] + ifioset USBIN, USBPLUS ;[01] + rjmp bit0IsClr ;[02] executed if first expr false or second true +se0AndStore: ; executed only if both bits 0 + st y+, x1 ;[15/17] cycles after start of byte + rjmp se0 ;[17/19] + +bit0IsClr: + ifrset phase, USBMINUS ;[04] check phase only if D- changed + lpm ;[05] + in phase, USBIN ;[06] <- phase (one cycle too late) + ori shift, 1 << 0 ;[07] +bit1AfterClr: + andi phase, USBMASK ;[08] + ifioset USBIN, USBMINUS ;[09] <--- sample 1 + rjmp bit1IsSet ;[10] + breq se0AndStore ;[11] if D- was 0 in bits 0 AND 1 and D+ was 0 in between, we have SE0 + andi shift, ~(7 << 1) ;[12] + in phase, USBIN ;[13] <- phase + breq unstuff1c ;[14] + rjmp bit2AfterClr ;[15] +unstuff1c: + andi fix, ~(1 << 1) ;[16] + nop2 ;[08] + nop2 ;[10] +bit1IsSet: + ifrclr phase, USBMINUS ;[12] check phase only if D- changed + lpm ;[13] + in phase, USBIN ;[14] <- phase (one cycle too late) + ori shift, 1 << 1 ;[15] + nop ;[16] +bit2AfterSet: + ifioclr USBIN, USBMINUS ;[17] <--- sample 2 + rjmp bit2IsClr ;[18] + andi shift, ~(7 << 2) ;[19] + breq unstuff2s ;[20] + in phase, USBIN ;[21] <- phase + rjmp bit3AfterSet ;[22] +unstuff2s: + in phase, USBIN ;[22] <- phase (one cycle too late) + andi fix, ~(1 << 2) ;[23] + nop2 ;[16] + nop2 ;[18] +bit2IsClr: + ifrset phase, USBMINUS ;[20] check phase only if D- changed + lpm ;[21] + in phase, USBIN ;[22] <- phase (one cycle too late) + ori shift, 1 << 2 ;[23] +bit3AfterClr: + st y+, data ;[24] +entryAfterClr: + ifioset USBIN, USBMINUS ;[26] <--- sample 3 + rjmp bit3IsSet ;[27] + andi shift, ~(7 << 3) ;[28] + breq unstuff3c ;[29] + in phase, USBIN ;[30] <- phase + rjmp bit4AfterClr ;[31] +unstuff3c: + in phase, USBIN ;[31] <- phase (one cycle too late) + andi fix, ~(1 << 3) ;[32] + nop2 ;[25] + nop2 ;[27] +bit3IsSet: + ifrclr phase, USBMINUS ;[29] check phase only if D- changed + lpm ;[30] + in phase, USBIN ;[31] <- phase (one cycle too late) + ori shift, 1 << 3 ;[32] +bit4AfterSet: + mov data, fix ;[33] undo this move by swapping defines +#undef fix +#define fix x1 +#undef data +#define data x2 + ifioclr USBIN, USBMINUS ;[34] <--- sample 4 + rjmp bit4IsClr ;[35] + andi shift, ~(7 << 4) ;[36] + breq unstuff4s ;[37] + in phase, USBIN ;[38] <- phase + rjmp bit5AfterSet ;[39] +unstuff4s: + in phase, USBIN ;[39] <- phase (one cycle too late) + andi fix, ~(1 << 4) ;[40] + nop2 ;[33] + nop2 ;[35] +bit4IsClr: + ifrset phase, USBMINUS ;[37] check phase only if D- changed + lpm ;[38] + in phase, USBIN ;[39] <- phase (one cycle too late) + ori shift, 1 << 4 ;[40] +bit5AfterClr: + ser data ;[41] + ifioset USBIN, USBMINUS ;[42] <--- sample 5 + rjmp bit5IsSet ;[43] + andi shift, ~(7 << 5) ;[44] + breq unstuff5c ;[45] + in phase, USBIN ;[46] <- phase + rjmp bit6AfterClr ;[47] +unstuff5c: + in phase, USBIN ;[47] <- phase (one cycle too late) + andi fix, ~(1 << 5) ;[48] + nop2 ;[41] + nop2 ;[43] +bit5IsSet: + ifrclr phase, USBMINUS ;[45] check phase only if D- changed + lpm ;[46] + in phase, USBIN ;[47] <- phase (one cycle too late) + ori shift, 1 << 5 ;[48] +bit6AfterSet: + subi cnt, 1 ;[49] + brcs jumpToOverflow ;[50] + ifioclr USBIN, USBMINUS ;[51] <--- sample 6 + rjmp bit6IsClr ;[52] + andi shift, ~(3 << 6) ;[53] + cpi shift, 2 ;[54] + in phase, USBIN ;[55] <- phase + brlt unstuff6s ;[56] + rjmp bit7AfterSet ;[57] + +jumpToOverflow: + rjmp overflow + +unstuff6s: + andi fix, ~(1 << 6) ;[50] + lpm ;[51] +bit6IsClr: + ifrset phase, USBMINUS ;[54] check phase only if D- changed + lpm ;[55] + in phase, USBIN ;[56] <- phase (one cycle too late) + ori shift, 1 << 6 ;[57] + nop ;[58] +bit7AfterClr: + ifioset USBIN, USBMINUS ;[59] <--- sample 7 + rjmp bit7IsSet ;[60] + andi shift, ~(1 << 7) ;[61] + cpi shift, 4 ;[62] + in phase, USBIN ;[63] <- phase + brlt unstuff7c ;[64] + rjmp bit0AfterClr ;[65] -> [00] == [67] +unstuff7c: + andi fix, ~(1 << 7) ;[58] + nop ;[59] + rjmp bit7IsSet ;[60] + +bit7IsClr: + ifrset phase, USBMINUS ;[62] check phase only if D- changed + lpm ;[63] + in phase, USBIN ;[64] <- phase (one cycle too late) + ori shift, 1 << 7 ;[65] + nop ;[66] +;;;;rjmp bit0AfterClr ; -> [00] == [67] moved block up to save jump +bit0AfterClr: + eor fix, shift ;[00] +#undef fix +#define fix x2 +#undef data +#define data x1 /* we now have result in data, fix is reset to 0xff */ + ifioset USBIN, USBMINUS ;[01] <--- sample 0 + rjmp bit0IsSet ;[02] + andi shift, ~(7 << 0) ;[03] + breq unstuff0c ;[04] + in phase, USBIN ;[05] <- phase + rjmp bit1AfterClr ;[06] +unstuff0c: + in phase, USBIN ;[06] <- phase (one cycle too late) + andi fix, ~(1 << 0) ;[07] + ifioclr USBIN, USBMINUS ;[00] + ifioset USBIN, USBPLUS ;[01] + rjmp bit0IsSet ;[02] executed if first expr false or second true + rjmp se0AndStore ;[03] executed only if both bits 0 +bit0IsSet: + ifrclr phase, USBMINUS ;[04] check phase only if D- changed + lpm ;[05] + in phase, USBIN ;[06] <- phase (one cycle too late) + ori shift, 1 << 0 ;[07] +bit1AfterSet: + andi shift, ~(7 << 1) ;[08] compensated by "ori shift, 1<<1" if bit1IsClr + ifioclr USBIN, USBMINUS ;[09] <--- sample 1 + rjmp bit1IsClr ;[10] + breq unstuff1s ;[11] + nop2 ;[12] do not check for SE0 if bit 0 was 1 + in phase, USBIN ;[14] <- phase (one cycle too late) + rjmp bit2AfterSet ;[15] +unstuff1s: + in phase, USBIN ;[13] <- phase + andi fix, ~(1 << 1) ;[14] + lpm ;[07] + nop2 ;[10] +bit1IsClr: + ifrset phase, USBMINUS ;[12] check phase only if D- changed + lpm ;[13] + in phase, USBIN ;[14] <- phase (one cycle too late) + ori shift, 1 << 1 ;[15] + nop ;[16] +bit2AfterClr: + ifioset USBIN, USBMINUS ;[17] <--- sample 2 + rjmp bit2IsSet ;[18] + andi shift, ~(7 << 2) ;[19] + breq unstuff2c ;[20] + in phase, USBIN ;[21] <- phase + rjmp bit3AfterClr ;[22] +unstuff2c: + in phase, USBIN ;[22] <- phase (one cycle too late) + andi fix, ~(1 << 2) ;[23] + nop2 ;[16] + nop2 ;[18] +bit2IsSet: + ifrclr phase, USBMINUS ;[20] check phase only if D- changed + lpm ;[21] + in phase, USBIN ;[22] <- phase (one cycle too late) + ori shift, 1 << 2 ;[23] +bit3AfterSet: + st y+, data ;[24] +entryAfterSet: + ifioclr USBIN, USBMINUS ;[26] <--- sample 3 + rjmp bit3IsClr ;[27] + andi shift, ~(7 << 3) ;[28] + breq unstuff3s ;[29] + in phase, USBIN ;[30] <- phase + rjmp bit4AfterSet ;[31] +unstuff3s: + in phase, USBIN ;[31] <- phase (one cycle too late) + andi fix, ~(1 << 3) ;[32] + nop2 ;[25] + nop2 ;[27] +bit3IsClr: + ifrset phase, USBMINUS ;[29] check phase only if D- changed + lpm ;[30] + in phase, USBIN ;[31] <- phase (one cycle too late) + ori shift, 1 << 3 ;[32] +bit4AfterClr: + mov data, fix ;[33] undo this move by swapping defines +#undef fix +#define fix x1 +#undef data +#define data x2 + ifioset USBIN, USBMINUS ;[34] <--- sample 4 + rjmp bit4IsSet ;[35] + andi shift, ~(7 << 4) ;[36] + breq unstuff4c ;[37] + in phase, USBIN ;[38] <- phase + rjmp bit5AfterClr ;[39] +unstuff4c: + in phase, USBIN ;[39] <- phase (one cycle too late) + andi fix, ~(1 << 4) ;[40] + nop2 ;[33] + nop2 ;[35] +bit4IsSet: + ifrclr phase, USBMINUS ;[37] check phase only if D- changed + lpm ;[38] + in phase, USBIN ;[39] <- phase (one cycle too late) + ori shift, 1 << 4 ;[40] +bit5AfterSet: + ser data ;[41] + ifioclr USBIN, USBMINUS ;[42] <--- sample 5 + rjmp bit5IsClr ;[43] + andi shift, ~(7 << 5) ;[44] + breq unstuff5s ;[45] + in phase, USBIN ;[46] <- phase + rjmp bit6AfterSet ;[47] +unstuff5s: + in phase, USBIN ;[47] <- phase (one cycle too late) + andi fix, ~(1 << 5) ;[48] + nop2 ;[41] + nop2 ;[43] +bit5IsClr: + ifrset phase, USBMINUS ;[45] check phase only if D- changed + lpm ;[46] + in phase, USBIN ;[47] <- phase (one cycle too late) + ori shift, 1 << 5 ;[48] +bit6AfterClr: + subi cnt, 1 ;[49] + brcs overflow ;[50] + ifioset USBIN, USBMINUS ;[51] <--- sample 6 + rjmp bit6IsSet ;[52] + andi shift, ~(3 << 6) ;[53] + cpi shift, 2 ;[54] + in phase, USBIN ;[55] <- phase + brlt unstuff6c ;[56] + rjmp bit7AfterClr ;[57] +unstuff6c: + andi fix, ~(1 << 6) ;[50] + lpm ;[51] +bit6IsSet: + ifrclr phase, USBMINUS ;[54] check phase only if D- changed + lpm ;[55] + in phase, USBIN ;[56] <- phase (one cycle too late) + ori shift, 1 << 6 ;[57] +bit7AfterSet: + ifioclr USBIN, USBMINUS ;[59] <--- sample 7 + rjmp bit7IsClr ;[60] + andi shift, ~(1 << 7) ;[61] + cpi shift, 4 ;[62] + in phase, USBIN ;[63] <- phase + brlt unstuff7s ;[64] + rjmp bit0AfterSet ;[65] -> [00] == [67] +unstuff7s: + andi fix, ~(1 << 7) ;[58] + nop ;[59] + rjmp bit7IsClr ;[60] + +macro POP_STANDARD ; 14 cycles + pop r0 + pop cnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;---------------------------------------------------------------------------- +; Transmitting data +;---------------------------------------------------------------------------- + +txByteLoop: +txBitloop: +stuffN1Delay: ; [03] + ror shift ;[-5] [11] [63] + brcc doExorN1 ;[-4] [64] + subi x3, 1 ;[-3] + brne commonN1 ;[-2] + lsl shift ;[-1] compensate ror after rjmp stuffDelay + nop ;[00] stuffing consists of just waiting 8 cycles + rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear + +sendNakAndReti: + ldi cnt, USBPID_NAK ;[-19] + rjmp sendCntAndReti ;[-18] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov r0, cnt ;[-16] + ldi YL, 0 ;[-15] R0 address is 0 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) or USBOUT = 0x01 +; K = (D+ = 1), (D- = 0) or USBOUT = 0x02 +; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles) + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte +;uses: x1...x3, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x3 = bitstuff cnt] +;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction) +usbSendAndReti: + in x2, USBDDR ;[-10] 10 cycles until SOP + ori x2, USBMASK ;[-9] + sbi USBOUT, USBMINUS ;[-8] prepare idle state; D+ and D- must have been 0 (no pullups) + out USBDDR, x2 ;[-6] <--- acquire bus + in x1, USBOUT ;[-5] port mirror for tx loop + ldi shift, 0x40 ;[-4] sync byte is first byte sent (we enter loop after ror) + ldi x2, USBMASK ;[-3] +doExorN1: + eor x1, x2 ;[-2] [06] [62] + ldi x3, 6 ;[-1] [07] [63] +commonN1: +stuffN2Delay: + out USBOUT, x1 ;[00] [08] [64] <--- set bit + ror shift ;[01] + brcc doExorN2 ;[02] + subi x3, 1 ;[03] + brne commonN2 ;[04] + lsl shift ;[05] compensate ror after rjmp stuffDelay + rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear +doExorN2: + eor x1, x2 ;[04] [12] + ldi x3, 6 ;[05] [13] +commonN2: + nop2 ;[06] [14] + subi cnt, 171 ;[08] [16] trick: (3 * 171) & 0xff = 1 + out USBOUT, x1 ;[09] [17] <--- set bit + brcs txBitloop ;[10] [27] [44] + +stuff6Delay: + ror shift ;[45] [53] + brcc doExor6 ;[46] + subi x3, 1 ;[47] + brne common6 ;[48] + lsl shift ;[49] compensate ror after rjmp stuffDelay + nop ;[50] stuffing consists of just waiting 8 cycles + rjmp stuff6Delay ;[51] after ror, C bit is reliably clear +doExor6: + eor x1, x2 ;[48] [56] + ldi x3, 6 ;[49] +common6: +stuff7Delay: + ror shift ;[50] [58] + out USBOUT, x1 ;[51] <--- set bit + brcc doExor7 ;[52] + subi x3, 1 ;[53] + brne common7 ;[54] + lsl shift ;[55] compensate ror after rjmp stuffDelay + rjmp stuff7Delay ;[56] after ror, C bit is reliably clear +doExor7: + eor x1, x2 ;[54] [62] + ldi x3, 6 ;[55] +common7: + ld shift, y+ ;[56] + nop ;[58] + tst cnt ;[59] + out USBOUT, x1 ;[60] [00]<--- set bit + brne txByteLoop ;[61] [01] +;make SE0: + cbr x1, USBMASK ;[02] prepare SE0 [spec says EOP may be 15 to 18 cycles] + lds x2, usbNewDeviceAddr;[03] + lsl x2 ;[05] we compare with left shifted address + subi YL, 2 + 0 ;[06] Only assign address on data packets, not ACK/NAK in r0 + sbci YH, 0 ;[07] + out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[01] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 0) + echo "$s\n"; + } +} + +function printBit($isAfterSet, $bitNum) +{ + ob_start(); + if($isAfterSet){ +?> + ifioclr USBIN, USBMINUS ;[00] <--- sample + rjmp bit#IsClr ;[01] + andi shift, ~(7 << #) ;[02] + breq unstuff#s ;[03] + in phase, USBIN ;[04] <- phase + rjmp bit@AfterSet ;[05] +unstuff#s: + in phase, USBIN ;[05] <- phase (one cycle too late) + andi fix, ~(1 << #) ;[06] + nop2 ;[-1] + nop2 ;[01] +bit#IsClr: + ifrset phase, USBMINUS ;[03] check phase only if D- changed + lpm ;[04] + in phase, USBIN ;[05] <- phase (one cycle too late) + ori shift, 1 << # ;[06] + + ifioset USBIN, USBMINUS ;[00] <--- sample + rjmp bit#IsSet ;[01] + andi shift, ~(7 << #) ;[02] + breq unstuff#c ;[03] + in phase, USBIN ;[04] <- phase + rjmp bit@AfterClr ;[05] +unstuff#c: + in phase, USBIN ;[05] <- phase (one cycle too late) + andi fix, ~(1 << #) ;[06] + nop2 ;[-1] + nop2 ;[01] +bit#IsSet: + ifrclr phase, USBMINUS ;[03] check phase only if D- changed + lpm ;[04] + in phase, USBIN ;[05] <- phase (one cycle too late) + ori shift, 1 << # ;[06] + +*****************************************************************************/ diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm15.inc b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm15.inc new file mode 100644 index 0000000..401b7f8 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm15.inc @@ -0,0 +1,423 @@ +/* Name: usbdrvasm15.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: contributed by V. Bosch + * Creation Date: 2007-08-06 + * Tabsize: 4 + * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm15.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 15 MHz version of the asssembler part of the USB driver. It +requires a 15 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! +*/ + +;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + +;---------------------------------------------------------------------------- +; order of registers pushed: +; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4 +;---------------------------------------------------------------------------- +USB_INTR_VECTOR: + push YL ;2 push only what is necessary to sync with edge ASAP + in YL, SREG ;1 + push YL ;2 +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +; +; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +; sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +;------------------------------------------------------------------------------- +; The following code results in a sampling window of < 1/4 bit +; which meets the spec. +;------------------------------------------------------------------------------- +waitForK: ;- + sbis USBIN, USBMINUS ;1 [00] <-- sample + rjmp foundK ;2 [01] + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK + sbis USBIN, USBMINUS ; <-- sample + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +;------------------------------------------------------------------------------ +; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for +; center sampling] +; we have 1 bit time for setup purposes, then sample again. +; Numbers in brackets are cycles from center of first sync (double K) +; bit after the instruction +;------------------------------------------------------------------------------ +foundK: ;- [02] + lds YL, usbInputBufOffset;2 [03+04] tx loop + push YH ;2 [05+06] + clr YH ;1 [07] + subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init] + sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init] + push shift ;2 [10+11] + ser shift ;1 [12] + sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early) + rjmp haveTwoBitsK ;2 [00] [14] + pop shift ;2 [15+16] undo the push from before + pop YH ;2 [17+18] undo the push from before + rjmp waitForK ;2 [19+20] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 20 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: ;- [01] + push x1 ;2 [02+03] + push x2 ;2 [04+05] + push x3 ;2 [06+07] + push bitcnt ;2 [08+09] + in x1, USBIN ;1 [00] [10] <-- sample bit 0 + bst x1, USBMINUS ;1 [01] + bld shift, 0 ;1 [02] + push cnt ;2 [03+04] + ldi cnt, USB_BUFSIZE ;1 [05] + push x4 ;2 [06+07] tx loop + rjmp rxLoop ;2 [08] +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +unstuff0: ;- [07] (branch taken) + andi x3, ~0x01 ;1 [08] + mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit + in x2, USBIN ;1 [00] [10] <-- sample bit 1 again + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 1 + ori shift, 0x01 ;1 [03] 0b00000001 + nop ;1 [04] + rjmp didUnstuff0 ;2 [05] +;----------------------------------------------------- +unstuff1: ;- [05] (branch taken) + mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit + andi x3, ~0x02 ;1 [07] + ori shift, 0x02 ;1 [08] 0b00000010 + nop ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 2 again + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 2 + rjmp didUnstuff1 ;2 [03] +;----------------------------------------------------- +unstuff2: ;- [05] (branch taken) + andi x3, ~0x04 ;1 [06] + ori shift, 0x04 ;1 [07] 0b00000100 + mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit + nop ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample bit 3 + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 3 + rjmp didUnstuff2 ;2 [03] +;----------------------------------------------------- +unstuff3: ;- [00] [10] (branch taken) + in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late + andi x2, USBMASK ;1 [02] + breq se0Hop ;1 [03] SE0 check for stuffed bit 3 + andi x3, ~0x08 ;1 [04] + ori shift, 0x08 ;1 [05] 0b00001000 + rjmp didUnstuff3 ;2 [06] +;---------------------------------------------------------------------------- +; extra jobs done during bit interval: +; +; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs], +; overflow check, jump to the head of rxLoop +; bit 1: SE0 check +; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long] +; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long] +; bit 4: SE0 check, none +; bit 5: SE0 check, none +; bit 6: SE0 check, none +; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others +;---------------------------------------------------------------------------- +rxLoop: ;- [09] + in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed) + andi x2, USBMASK ;1 [01] + brne SkipSe0Hop ;1 [02] +se0Hop: ;- [02] + rjmp se0 ;2 [03] SE0 check for bit 1 +SkipSe0Hop: ;- [03] + ser x3 ;1 [04] + andi shift, 0xf9 ;1 [05] 0b11111001 + breq unstuff0 ;1 [06] +didUnstuff0: ;- [06] + eor x1, x2 ;1 [07] + bst x1, USBMINUS ;1 [08] + bld shift, 1 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed) + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 2 + andi shift, 0xf3 ;1 [03] 0b11110011 + breq unstuff1 ;1 [04] do remaining work for bit 1 +didUnstuff1: ;- [04] + eor x2, x1 ;1 [05] + bst x2, USBMINUS ;1 [06] + bld shift, 2 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed) + andi x2, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 3 + andi shift, 0xe7 ;1 [03] 0b11100111 + breq unstuff2 ;1 [04] +didUnstuff2: ;- [04] + eor x1, x2 ;1 [05] + bst x1, USBMINUS ;1 [06] + bld shift, 3 ;1 [07] +didUnstuff3: ;- [07] + andi shift, 0xcf ;1 [08] 0b11001111 + breq unstuff3 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 4 + andi x1, USBMASK ;1 [01] + breq se0Hop ;1 [02] SE0 check for bit 4 + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 4 ;1 [05] +didUnstuff4: ;- [05] + andi shift, 0x9f ;1 [06] 0b10011111 + breq unstuff4 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 5 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 5 + eor x1, x2 ;1 [03] + bst x1, USBMINUS ;1 [04] + bld shift, 5 ;1 [05] +didUnstuff5: ;- [05] + andi shift, 0x3f ;1 [06] 0b00111111 + breq unstuff5 ;1 [07] + nop2 ;2 [08+09] + in x1, USBIN ;1 [00] [10] <-- sample bit 6 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 6 + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 6 ;1 [05] +didUnstuff6: ;- [05] + cpi shift, 0x02 ;1 [06] 0b00000010 + brlo unstuff6 ;1 [07] + nop2 ;2 [08+09] + in x2, USBIN ;1 [00] [10] <-- sample bit 7 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for bit 7 + eor x1, x2 ;1 [03] + bst x1, USBMINUS ;1 [04] + bld shift, 7 ;1 [05] +didUnstuff7: ;- [05] + cpi shift, 0x04 ;1 [06] 0b00000100 + brlo unstuff7 ;1 [07] + eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others + nop ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample bit 0 + st y+, x3 ;2 [01+02] store data + eor x2, x1 ;1 [03] + bst x2, USBMINUS ;1 [04] + bld shift, 0 ;1 [05] + subi cnt, 1 ;1 [06] + brcs overflow ;1 [07] + rjmp rxLoop ;2 [08] +;----------------------------------------------------- +unstuff4: ;- [08] + andi x3, ~0x10 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 4 + ori shift, 0x10 ;1 [03] + rjmp didUnstuff4 ;2 [04] +;----------------------------------------------------- +unstuff5: ;- [08] + ori shift, 0x20 ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 5 + andi x3, ~0x20 ;1 [03] + rjmp didUnstuff5 ;2 [04] +;----------------------------------------------------- +unstuff6: ;- [08] + andi x3, ~0x40 ;1 [09] + in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6 + andi x1, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 6 + ori shift, 0x40 ;1 [03] + rjmp didUnstuff6 ;2 [04] +;----------------------------------------------------- +unstuff7: ;- [08] + andi x3, ~0x80 ;1 [09] + in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7 + andi x2, USBMASK ;1 [01] + breq se0 ;1 [02] SE0 check for stuffed bit 7 + ori shift, 0x80 ;1 [03] + rjmp didUnstuff7 ;2 [04] + +macro POP_STANDARD ; 16 cycles + pop x4 + pop cnt + pop bitcnt + pop x3 + pop x2 + pop x1 + pop shift + pop YH + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +;--------------------------------------------------------------------------- +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies +;--------------------------------------------------------------------------- +bitstuffN: ;- [04] + eor x1, x4 ;1 [05] + clr x2 ;1 [06] + nop ;1 [07] + rjmp didStuffN ;1 [08] +;--------------------------------------------------------------------------- +bitstuff6: ;- [04] + eor x1, x4 ;1 [05] + clr x2 ;1 [06] + rjmp didStuff6 ;1 [07] +;--------------------------------------------------------------------------- +bitstuff7: ;- [02] + eor x1, x4 ;1 [03] + clr x2 ;1 [06] + nop ;1 [05] + rjmp didStuff7 ;1 [06] +;--------------------------------------------------------------------------- +sendNakAndReti: ;- [-19] + ldi x3, USBPID_NAK ;1 [-18] + rjmp sendX3AndReti ;1 [-17] +;--------------------------------------------------------------------------- +sendAckAndReti: ;- [-17] + ldi cnt, USBPID_ACK ;1 [-16] +sendCntAndReti: ;- [-16] + mov x3, cnt ;1 [-15] +sendX3AndReti: ;- [-15] + ldi YL, 20 ;1 [-14] x3==r20 address is 20 + ldi YH, 0 ;1 [-13] + ldi cnt, 2 ;1 [-12] +; rjmp usbSendAndReti fallthrough +;--------------------------------------------------------------------------- +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +;We need not to match the transfer rate exactly because the spec demands +;only 1.5% precision anyway. +usbSendAndReti: ;- [-13] 13 cycles until SOP + in x2, USBDDR ;1 [-12] + ori x2, USBMASK ;1 [-11] + sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;1 [-08] port mirror for tx loop + out USBDDR, x2 ;1 [-07] <- acquire bus + ; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;1 [-06] exor mask + ldi shift, 0x80 ;1 [-05] sync byte is first byte sent + ldi bitcnt, 6 ;1 [-04] +txBitLoop: ;- [-04] [06] + sbrs shift, 0 ;1 [-03] [07] + eor x1, x4 ;1 [-02] [08] + ror shift ;1 [-01] [09] +didStuffN: ;- [09] + out USBOUT, x1 ;1 [00] [10] <-- out N + ror x2 ;1 [01] + cpi x2, 0xfc ;1 [02] + brcc bitstuffN ;1 [03] + dec bitcnt ;1 [04] + brne txBitLoop ;1 [05] + sbrs shift, 0 ;1 [06] + eor x1, x4 ;1 [07] + ror shift ;1 [08] +didStuff6: ;- [08] + nop ;1 [09] + out USBOUT, x1 ;1 [00] [10] <-- out 6 + ror x2 ;1 [01] + cpi x2, 0xfc ;1 [02] + brcc bitstuff6 ;1 [03] + sbrs shift, 0 ;1 [04] + eor x1, x4 ;1 [05] + ror shift ;1 [06] + ror x2 ;1 [07] +didStuff7: ;- [07] + ldi bitcnt, 6 ;1 [08] + cpi x2, 0xfc ;1 [09] + out USBOUT, x1 ;1 [00] [10] <-- out 7 + brcc bitstuff7 ;1 [01] + ld shift, y+ ;2 [02+03] + dec cnt ;1 [04] + brne txBitLoop ;1 [05] +makeSE0: + cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles] + lds x2, usbNewDeviceAddr;2 [07+08] + lsl x2 ;1 [09] we compare with left shifted address +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle + subi YL, 20 + 2 ;1 [01] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;1 [02] + breq skipAddrAssign ;1 [03] + sts usbDeviceAddr, x2 ;2 [04+05] if not skipped: SE0 is one cycle longer +;---------------------------------------------------------------------------- +;end of usbDeviceAddress transfer +skipAddrAssign: ;- [03/04] + ldi x2, 1< 10.6666666 cycles per bit, 85.333333333 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt + push YL ;[-25] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-23] + push YL ;[-22] + push YH ;[-20] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-15] + rjmp foundK ;[-14] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-12] +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push bitcnt ;[-12] +; [---] ;[-11] + lds YL, usbInputBufOffset;[-10] +; [---] ;[-9] + clr YH ;[-8] + subi YL, lo8(-(usbRxBuf));[-7] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init] + push shift ;[-5] +; [---] ;[-4] + ldi bitcnt, 0x55 ;[-3] [rx loop init] + sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early) + rjmp haveTwoBitsK ;[-1] + pop shift ;[0] undo the push from before + pop bitcnt ;[2] undo the push from before + rjmp waitForK ;[4] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 21 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[1] + push x2 ;[3] + push x3 ;[5] + ldi shift, 0 ;[7] + ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that + push x4 ;[9] == leap + + in x1, USBIN ;[11] <-- sample bit 0 + andi x1, USBMASK ;[12] + bst x1, USBMINUS ;[13] + bld shift, 7 ;[14] + push cnt ;[15] + ldi leap, 0 ;[17] [rx loop init] + ldi cnt, USB_BUFSIZE;[18] [rx loop init] + rjmp rxbit1 ;[19] arrives at [21] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- + +; duration of unstuffing code should be 10.66666667 cycles. We adjust "leap" +; accordingly to approximate this value in the long run. + +unstuff6: + andi x2, USBMASK ;[03] + ori x3, 1<<6 ;[04] will not be shifted any more + andi shift, ~0x80;[05] + mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6 + subi leap, -1 ;[07] total duration = 11 bits -> subtract 1/3 + rjmp didUnstuff6 ;[08] + +unstuff7: + ori x3, 1<<7 ;[09] will not be shifted any more + in x2, USBIN ;[00] [10] re-sample bit 7 + andi x2, USBMASK ;[01] + andi shift, ~0x80;[02] + subi leap, 2 ;[03] total duration = 10 bits -> add 1/3 + rjmp didUnstuff7 ;[04] + +unstuffEven: + ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0 + in x1, USBIN ;[00] [10] + andi shift, ~0x80;[01] + andi x1, USBMASK ;[02] + breq se0 ;[03] + subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3 + nop2 ;[05] + rjmp didUnstuffE ;[06] + +unstuffOdd: + ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1 + in x2, USBIN ;[00] [10] + andi shift, ~0x80;[01] + andi x2, USBMASK ;[02] + breq se0 ;[03] + subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3 + nop2 ;[05] + rjmp didUnstuffO ;[06] + +rxByteLoop: + andi x1, USBMASK ;[03] + eor x2, x1 ;[04] + subi leap, 1 ;[05] + brpl skipLeap ;[06] + subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte + nop ;1 +skipLeap: + subi x2, 1 ;[08] + ror shift ;[09] +didUnstuff6: + cpi shift, 0xfc ;[10] + in x2, USBIN ;[00] [11] <-- sample bit 7 + brcc unstuff6 ;[01] + andi x2, USBMASK ;[02] + eor x1, x2 ;[03] + subi x1, 1 ;[04] + ror shift ;[05] +didUnstuff7: + cpi shift, 0xfc ;[06] + brcc unstuff7 ;[07] + eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others + st y+, x3 ;[09] store data +rxBitLoop: + in x1, USBIN ;[00] [11] <-- sample bit 0/2/4 + andi x1, USBMASK ;[01] + eor x2, x1 ;[02] + andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7 + subi x2, 1 ;[04] + ror shift ;[05] + cpi shift, 0xfc ;[06] + brcc unstuffEven ;[07] +didUnstuffE: + lsr x3 ;[08] + lsr x3 ;[09] +rxbit1: + in x2, USBIN ;[00] [10] <-- sample bit 1/3/5 + andi x2, USBMASK ;[01] + breq se0 ;[02] + eor x1, x2 ;[03] + subi x1, 1 ;[04] + ror shift ;[05] + cpi shift, 0xfc ;[06] + brcc unstuffOdd ;[07] +didUnstuffO: + subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3 + brcs rxBitLoop ;[09] + + subi cnt, 1 ;[10] + in x1, USBIN ;[00] [11] <-- sample bit 6 + brcc rxByteLoop ;[01] + rjmp overflow + +macro POP_STANDARD ; 14 cycles + pop cnt + pop x4 + pop x3 + pop x2 + pop x1 + pop shift + pop bitcnt + endm +macro POP_RETI ; 7 cycles + pop YH + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies + +bitstuffN: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] + nop2 ;[7] + nop ;[9] + out USBOUT, x1 ;[10] <-- out + rjmp didStuffN ;[0] + +bitstuff6: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] Carry is zero due to brcc + rol shift ;[7] compensate for ror shift at branch destination + rjmp didStuff6 ;[8] + +bitstuff7: + ldi x2, 0 ;[2] Carry is zero due to brcc + rjmp didStuff7 ;[3] + + +sendNakAndReti: + ldi x3, USBPID_NAK ;[-18] + rjmp sendX3AndReti ;[-17] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov x3, cnt ;[-16] +sendX3AndReti: + ldi YL, 20 ;[-15] x3==r20 address is 20 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +;We don't match the transfer rate exactly (don't insert leap cycles every third +;byte) because the spec demands only 1.5% precision anyway. +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-7] <- acquire bus +; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-6] exor mask + ldi shift, 0x80 ;[-5] sync byte is first byte sent +txByteLoop: + ldi bitcnt, 0x35 ;[-4] [6] binary 0011 0101 +txBitLoop: + sbrs shift, 0 ;[-3] [7] + eor x1, x4 ;[-2] [8] + out USBOUT, x1 ;[-1] [9] <-- out N + ror shift ;[0] [10] + ror x2 ;[1] +didStuffN: + cpi x2, 0xfc ;[2] + brcc bitstuffN ;[3] + lsr bitcnt ;[4] + brcc txBitLoop ;[5] + brne txBitLoop ;[6] + + sbrs shift, 0 ;[7] + eor x1, x4 ;[8] +didStuff6: + out USBOUT, x1 ;[-1] [9] <-- out 6 + ror shift ;[0] [10] + ror x2 ;[1] + cpi x2, 0xfc ;[2] + brcc bitstuff6 ;[3] + ror shift ;[4] +didStuff7: + ror x2 ;[5] + sbrs x2, 7 ;[6] + eor x1, x4 ;[7] + nop ;[8] + cpi x2, 0xfc ;[9] + out USBOUT, x1 ;[-1][10] <-- out 7 + brcc bitstuff7 ;[0] [11] + ld shift, y+ ;[1] + dec cnt ;[3] + brne txByteLoop ;[4] +;make SE0: + cbr x1, USBMASK ;[5] prepare SE0 [spec says EOP may be 21 to 25 cycles] + lds x2, usbNewDeviceAddr;[6] + lsl x2 ;[8] we compare with left shifted address + subi YL, 20 + 2 ;[9] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[10] + out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[0] + sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< max 52 cycles interrupt disable +;max stack usage: [ret(2), r0, SREG, YL, YH, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 16.5 MHz -> 11 cycles per bit +; 16.3125 MHz < F_CPU < 16.6875 MHz (+/- 1.1%) +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG [sofError], r0, YH, shift, x1, x2, x3, x4, cnt + push YL ;[-23] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-21] + push YL ;[-20] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-15] + rjmp foundK ;[-14] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-12] +;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling] +;we have 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push r0 ;[-12] +; [---] ;[-11] + push YH ;[-10] +; [---] ;[-9] + lds YL, usbInputBufOffset;[-8] +; [---] ;[-7] + clr YH ;[-6] + subi YL, lo8(-(usbRxBuf));[-5] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-4] [rx loop init] + mov r0, x2 ;[-3] [rx loop init] + sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early) + rjmp haveTwoBitsK ;[-1] + pop YH ;[0] undo the pushes from before + pop r0 ;[2] + rjmp waitForK ;[4] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 22 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: ;[1] + push shift ;[1] + push x1 ;[3] + push x2 ;[5] + push x3 ;[7] + ldi shift, 0xff ;[9] [rx loop init] + ori x3, 0xff ;[10] [rx loop init] == ser x3, clear zero flag + + in x1, USBIN ;[11] <-- sample bit 0 + bst x1, USBMINUS ;[12] + bld shift, 0 ;[13] + push x4 ;[14] == phase +; [---] ;[15] + push cnt ;[16] +; [---] ;[17] + ldi phase, 0 ;[18] [rx loop init] + ldi cnt, USB_BUFSIZE;[19] [rx loop init] + rjmp rxbit1 ;[20] +; [---] ;[21] + +;---------------------------------------------------------------------------- +; Receiver loop (numbers in brackets are cycles within byte after instr) +;---------------------------------------------------------------------------- +/* +byte oriented operations done during loop: +bit 0: store data +bit 1: SE0 check +bit 2: overflow check +bit 3: catch up +bit 4: rjmp to achieve conditional jump range +bit 5: PLL +bit 6: catch up +bit 7: jump, fixup bitstuff +; 87 [+ 2] cycles +------------------------------------------------------------------ +*/ +continueWithBit5: + in x2, USBIN ;[055] <-- bit 5 + eor r0, x2 ;[056] + or phase, r0 ;[057] + sbrc phase, USBMINUS ;[058] + lpm ;[059] optional nop3; modifies r0 + in phase, USBIN ;[060] <-- phase + eor x1, x2 ;[061] + bst x1, USBMINUS ;[062] + bld shift, 5 ;[063] + andi shift, 0x3f ;[064] + in x1, USBIN ;[065] <-- bit 6 + breq unstuff5 ;[066] *** unstuff escape + eor phase, x1 ;[067] + eor x2, x1 ;[068] + bst x2, USBMINUS ;[069] + bld shift, 6 ;[070] +didUnstuff6: ;[ ] + in r0, USBIN ;[071] <-- phase + cpi shift, 0x02 ;[072] + brlo unstuff6 ;[073] *** unstuff escape +didUnstuff5: ;[ ] + nop2 ;[074] +; [---] ;[075] + in x2, USBIN ;[076] <-- bit 7 + eor x1, x2 ;[077] + bst x1, USBMINUS ;[078] + bld shift, 7 ;[079] +didUnstuff7: ;[ ] + eor r0, x2 ;[080] + or phase, r0 ;[081] + in r0, USBIN ;[082] <-- phase + cpi shift, 0x04 ;[083] + brsh rxLoop ;[084] +; [---] ;[085] +unstuff7: ;[ ] + andi x3, ~0x80 ;[085] + ori shift, 0x80 ;[086] + in x2, USBIN ;[087] <-- sample stuffed bit 7 + nop ;[088] + rjmp didUnstuff7 ;[089] +; [---] ;[090] + ;[080] + +unstuff5: ;[067] + eor phase, x1 ;[068] + andi x3, ~0x20 ;[069] + ori shift, 0x20 ;[070] + in r0, USBIN ;[071] <-- phase + mov x2, x1 ;[072] + nop ;[073] + nop2 ;[074] +; [---] ;[075] + in x1, USBIN ;[076] <-- bit 6 + eor r0, x1 ;[077] + or phase, r0 ;[078] + eor x2, x1 ;[079] + bst x2, USBMINUS ;[080] + bld shift, 6 ;[081] no need to check bitstuffing, we just had one + in r0, USBIN ;[082] <-- phase + rjmp didUnstuff5 ;[083] +; [---] ;[084] + ;[074] + +unstuff6: ;[074] + andi x3, ~0x40 ;[075] + in x1, USBIN ;[076] <-- bit 6 again + ori shift, 0x40 ;[077] + nop2 ;[078] +; [---] ;[079] + rjmp didUnstuff6 ;[080] +; [---] ;[081] + ;[071] + +unstuff0: ;[013] + eor r0, x2 ;[014] + or phase, r0 ;[015] + andi x2, USBMASK ;[016] check for SE0 + in r0, USBIN ;[017] <-- phase + breq didUnstuff0 ;[018] direct jump to se0 would be too long + andi x3, ~0x01 ;[019] + ori shift, 0x01 ;[020] + mov x1, x2 ;[021] mov existing sample + in x2, USBIN ;[022] <-- bit 1 again + rjmp didUnstuff0 ;[023] +; [---] ;[024] + ;[014] + +unstuff1: ;[024] + eor r0, x1 ;[025] + or phase, r0 ;[026] + andi x3, ~0x02 ;[027] + in r0, USBIN ;[028] <-- phase + ori shift, 0x02 ;[029] + mov x2, x1 ;[030] + rjmp didUnstuff1 ;[031] +; [---] ;[032] + ;[022] + +unstuff2: ;[035] + eor r0, x2 ;[036] + or phase, r0 ;[037] + andi x3, ~0x04 ;[038] + in r0, USBIN ;[039] <-- phase + ori shift, 0x04 ;[040] + mov x1, x2 ;[041] + rjmp didUnstuff2 ;[042] +; [---] ;[043] + ;[033] + +unstuff3: ;[043] + in x2, USBIN ;[044] <-- bit 3 again + eor r0, x2 ;[045] + or phase, r0 ;[046] + andi x3, ~0x08 ;[047] + ori shift, 0x08 ;[048] + nop ;[049] + in r0, USBIN ;[050] <-- phase + rjmp didUnstuff3 ;[051] +; [---] ;[052] + ;[042] + +unstuff4: ;[053] + andi x3, ~0x10 ;[054] + in x1, USBIN ;[055] <-- bit 4 again + ori shift, 0x10 ;[056] + rjmp didUnstuff4 ;[057] +; [---] ;[058] + ;[048] + +rxLoop: ;[085] + eor x3, shift ;[086] reconstruct: x3 is 0 at bit locations we changed, 1 at others + in x1, USBIN ;[000] <-- bit 0 + st y+, x3 ;[001] +; [---] ;[002] + eor r0, x1 ;[003] + or phase, r0 ;[004] + eor x2, x1 ;[005] + in r0, USBIN ;[006] <-- phase + ser x3 ;[007] + bst x2, USBMINUS ;[008] + bld shift, 0 ;[009] + andi shift, 0xf9 ;[010] +rxbit1: ;[ ] + in x2, USBIN ;[011] <-- bit 1 + breq unstuff0 ;[012] *** unstuff escape + andi x2, USBMASK ;[013] SE0 check for bit 1 +didUnstuff0: ;[ ] Z only set if we detected SE0 in bitstuff + breq se0 ;[014] + eor r0, x2 ;[015] + or phase, r0 ;[016] + in r0, USBIN ;[017] <-- phase + eor x1, x2 ;[018] + bst x1, USBMINUS ;[019] + bld shift, 1 ;[020] + andi shift, 0xf3 ;[021] +didUnstuff1: ;[ ] + in x1, USBIN ;[022] <-- bit 2 + breq unstuff1 ;[023] *** unstuff escape + eor r0, x1 ;[024] + or phase, r0 ;[025] + subi cnt, 1 ;[026] overflow check + brcs overflow ;[027] + in r0, USBIN ;[028] <-- phase + eor x2, x1 ;[029] + bst x2, USBMINUS ;[030] + bld shift, 2 ;[031] + andi shift, 0xe7 ;[032] +didUnstuff2: ;[ ] + in x2, USBIN ;[033] <-- bit 3 + breq unstuff2 ;[034] *** unstuff escape + eor r0, x2 ;[035] + or phase, r0 ;[036] + eor x1, x2 ;[037] + bst x1, USBMINUS ;[038] + in r0, USBIN ;[039] <-- phase + bld shift, 3 ;[040] + andi shift, 0xcf ;[041] +didUnstuff3: ;[ ] + breq unstuff3 ;[042] *** unstuff escape + nop ;[043] + in x1, USBIN ;[044] <-- bit 4 + eor x2, x1 ;[045] + bst x2, USBMINUS ;[046] + bld shift, 4 ;[047] +didUnstuff4: ;[ ] + eor r0, x1 ;[048] + or phase, r0 ;[049] + in r0, USBIN ;[050] <-- phase + andi shift, 0x9f ;[051] + breq unstuff4 ;[052] *** unstuff escape + rjmp continueWithBit5;[053] +; [---] ;[054] + +macro POP_STANDARD ; 16 cycles + pop cnt + pop x4 + pop x3 + pop x2 + pop x1 + pop shift + pop YH + pop r0 + endm +macro POP_RETI ; 5 cycles + pop YL + out SREG, YL + pop YL + endm + +#include "asmcommon.inc" + + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies + +bitstuff7: + eor x1, x4 ;[4] + ldi x2, 0 ;[5] + nop2 ;[6] C is zero (brcc) + rjmp didStuff7 ;[8] + +bitstuffN: + eor x1, x4 ;[5] + ldi x2, 0 ;[6] + lpm ;[7] 3 cycle NOP, modifies r0 + out USBOUT, x1 ;[10] <-- out + rjmp didStuffN ;[0] + +#define bitStatus x3 + +sendNakAndReti: + ldi cnt, USBPID_NAK ;[-19] + rjmp sendCntAndReti ;[-18] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov r0, cnt ;[-16] + ldi YL, 0 ;[-15] R0 address is 0 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-7] <- acquire bus +; need not init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-6] exor mask + ldi shift, 0x80 ;[-5] sync byte is first byte sent + ldi bitStatus, 0xff ;[-4] init bit loop counter, works for up to 12 bytes +byteloop: +bitloop: + sbrs shift, 0 ;[8] [-3] + eor x1, x4 ;[9] [-2] + out USBOUT, x1 ;[10] [-1] <-- out + ror shift ;[0] + ror x2 ;[1] +didStuffN: + cpi x2, 0xfc ;[2] + brcc bitstuffN ;[3] + nop ;[4] + subi bitStatus, 37 ;[5] 256 / 7 ~=~ 37 + brcc bitloop ;[6] when we leave the loop, bitStatus has almost the initial value + sbrs shift, 0 ;[7] + eor x1, x4 ;[8] + ror shift ;[9] +didStuff7: + out USBOUT, x1 ;[10] <-- out + ror x2 ;[0] + cpi x2, 0xfc ;[1] + brcc bitstuff7 ;[2] + ld shift, y+ ;[3] + dec cnt ;[5] + brne byteloop ;[6] +;make SE0: + cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles] + lds x2, usbNewDeviceAddr;[8] + lsl x2 ;[10] we compare with left shifted address + out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + subi YL, 2 ;[0] Only assign address on data packets, not ACK/NAK in r0 + sbci YH, 0 ;[1] + breq skipAddrAssign ;[2] + sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< 12 cycles per bit +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts +;register use in receive loop to receive the data bytes: +; shift assembles the byte currently being received +; x1 holds the D+ and D- line state +; x2 holds the previous line state +; cnt holds the number of bytes left in the receive buffer +; x3 holds the higher crc byte (see algorithm below) +; x4 is used as temporary register for the crc algorithm +; x5 is used for unstuffing: when unstuffing the last received bit is inverted in shift (to prevent further +; unstuffing calls. In the same time the corresponding bit in x5 is cleared to mark the bit as beening iverted +; zl lower crc value and crc table index +; zh used for crc table accesses + +;-------------------------------------------------------------------------------------------------------------- +; CRC mods: +; table driven crc checker, Z points to table in prog space +; ZL is the lower crc byte, x3 is the higher crc byte +; x4 is used as temp register to store different results +; the initialization of the crc register is not 0xFFFF but 0xFE54. This is because during the receipt of the +; first data byte an virtual zero data byte is added to the crc register, this results in the correct initial +; value of 0xFFFF at beginning of the second data byte before the first data byte is added to the crc. +; The magic number 0xFE54 results form the crc table: At tabH[0x54] = 0xFF = crcH (required) and +; tabL[0x54] = 0x01 -> crcL = 0x01 xor 0xFE = 0xFF +; bitcnt is renamed to x5 and is used for unstuffing purposes, the unstuffing works like in the 12MHz version +;-------------------------------------------------------------------------------------------------------------- +; CRC algorithm: +; The crc register is formed by x3 (higher byte) and ZL (lower byte). The algorithm uses a 'reversed' form +; i.e. that it takes the least significant bit first and shifts to the right. So in fact the highest order +; bit seen from the polynomial devision point of view is the lsb of ZL. (If this sounds strange to you i +; propose a research on CRC :-) ) +; Each data byte received is xored to ZL, the lower crc byte. This byte now builds the crc +; table index. Next the new high byte is loaded from the table and stored in x4 until we have space in x3 +; (its destination). +; Afterwards the lower table is loaded from the table and stored in ZL (the old index is overwritten as +; we don't need it anymore. In fact this is a right shift by 8 bits.) Now the old crc high value is xored +; to ZL, this is the second shift of the old crc value. Now x4 (the temp reg) is moved to x3 and the crc +; calculation is done. +; Prior to the first byte the two CRC register have to be initialized to 0xFFFF (as defined in usb spec) +; however the crc engine also runs during the receipt of the first byte, therefore x3 and zl are initialized +; to a magic number which results in a crc value of 0xFFFF after the first complete byte. +; +; This algorithm is split into the extra cycles of the different bits: +; bit7: XOR the received byte to ZL +; bit5: load the new high byte to x4 +; bit6: load the lower xor byte from the table, xor zl and x3, store result in zl (=the new crc low value) +; move x4 (the new high byte) to x3, the crc value is ready +; + + +macro POP_STANDARD ; 18 cycles + pop ZH + pop ZL + pop cnt + pop x5 + pop x3 + pop x2 + pop x1 + pop shift + pop x4 + endm +macro POP_RETI ; 7 cycles + pop YH + pop YL + out SREG, YL + pop YL + endm + +macro CRC_CLEANUP_AND_CHECK + ; the last byte has already been xored with the lower crc byte, we have to do the table lookup and xor + ; x3 is the higher crc byte, zl the lower one + ldi ZH, hi8(usbCrcTableHigh);[+1] get the new high byte from the table + lpm x2, Z ;[+2][+3][+4] + ldi ZH, hi8(usbCrcTableLow);[+5] get the new low xor byte from the table + lpm ZL, Z ;[+6][+7][+8] + eor ZL, x3 ;[+7] xor the old high byte with the value from the table, x2:ZL now holds the crc value + cpi ZL, 0x01 ;[+8] if the crc is ok we have a fixed remainder value of 0xb001 in x2:ZL (see usb spec) + brne ignorePacket ;[+9] detected a crc fault -> paket is ignored and retransmitted by the host + cpi x2, 0xb0 ;[+10] + brne ignorePacket ;[+11] detected a crc fault -> paket is ignored and retransmitted by the host + endm + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG, YH, [sofError], x4, shift, x1, x2, x3, x5, cnt, ZL, ZH + push YL ;[-28] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-26] + push YL ;[-25] + push YH ;[-23] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-17] + rjmp foundK ;[-16] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-15] +;{3, 5} after falling D- edge, average delay: 4 cycles +;bit0 should be at 30 (2.5 bits) for center sampling. Currently at 4 so 26 cylces till bit 0 sample +;use 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push x4 ;[-14] +; [---] ;[-13] + lds YL, usbInputBufOffset;[-12] used to toggle the two usb receive buffers +; [---] ;[-11] + clr YH ;[-10] + subi YL, lo8(-(usbRxBuf));[-9] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-8] [rx loop init] + push shift ;[-7] +; [---] ;[-6] + ldi shift, 0x80 ;[-5] the last bit is the end of byte marker for the pid receiver loop + clc ;[-4] the carry has to be clear for receipt of pid bit 0 + sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) + rjmp haveTwoBitsK ;[-2] + pop shift ;[-1] undo the push from before + pop x4 ;[1] + rjmp waitForK ;[3] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 24 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[0] + push x2 ;[2] + push x3 ;[4] crc high byte + ldi x2, 1< jump back and store the byte + ori shift, 0x01 ;[11] invert the last received bit to prevent furhter unstuffing + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + andi x5, 0xFE ;[1] mark this bit as inverted (will be corrected before storing shift) + eor x1, x2 ;[2] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[3] mask the interesting bits + breq stuffErr ;[4] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[5] the next bit expects the last state to be in x1 + rjmp didunstuff0 ;[6] + ;[7] jump delay of rjmp didunstuffX + +unstuff1: ;[11] this is the jump delay of breq unstuffX + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + ori shift, 0x02 ;[1] invert the last received bit to prevent furhter unstuffing + andi x5, 0xFD ;[2] mark this bit as inverted (will be corrected before storing shift) + eor x2, x1 ;[3] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[4] mask the interesting bits + breq stuffErr ;[5] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[6] the next bit expects the last state to be in x2 + nop2 ;[7] + ;[8] + rjmp didunstuff1 ;[9] + ;[10] jump delay of rjmp didunstuffX + +unstuff2: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x04 ;[10] invert the last received bit to prevent furhter unstuffing + andi x5, 0xFB ;[11] mark this bit as inverted (will be corrected before storing shift) + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[4] the next bit expects the last state to be in x1 + nop2 ;[5] + ;[6] + rjmp didunstuff2 ;[7] + ;[8] jump delay of rjmp didunstuffX + +unstuff3: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x08 ;[10] invert the last received bit to prevent furhter unstuffing + andi x5, 0xF7 ;[11] mark this bit as inverted (will be corrected before storing shift) + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[4] the next bit expects the last state to be in x2 + nop2 ;[5] + ;[6] + rjmp didunstuff3 ;[7] + ;[8] jump delay of rjmp didunstuffX + + + +; the include has to be here due to branch distance restirctions +#define __USE_CRC__ +#include "asmcommon.inc" + + + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies +; 7.5 bit times is 90 cycles. ...there is plenty of time + + +sendNakAndReti: + ldi x3, USBPID_NAK ;[-18] + rjmp sendX3AndReti ;[-17] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov x3, cnt ;[-16] +sendX3AndReti: + ldi YL, 20 ;[-15] x3==r20 address is 20 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent + +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-6] <- acquire bus + ldi x2, 0 ;[-6] init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-5] exor mask + ldi shift, 0x80 ;[-4] sync byte is first byte sent +txByteLoop: + ldi bitcnt, 0x40 ;[-3]=[9] binary 01000000 +txBitLoop: ; the loop sends the first 7 bits of the byte + sbrs shift, 0 ;[-2]=[10] if we have to send a 1 don't change the line state + eor x1, x4 ;[-1]=[11] + out USBOUT, x1 ;[0] + ror shift ;[1] + ror x2 ;[2] transfers the last sent bit to the stuffing history +didStuffN: + nop ;[3] + nop ;[4] + cpi x2, 0xfc ;[5] if we sent six consecutive ones + brcc bitstuffN ;[6] + lsr bitcnt ;[7] + brne txBitLoop ;[8] restart the loop while the 1 is still in the bitcount + +; transmit bit 7 + sbrs shift, 0 ;[9] + eor x1, x4 ;[10] +didStuff7: + ror shift ;[11] + out USBOUT, x1 ;[0] transfer bit 7 to the pins + ror x2 ;[1] move the bit into the stuffing history + cpi x2, 0xfc ;[2] + brcc bitstuff7 ;[3] + ld shift, y+ ;[4] get next byte to transmit + dec cnt ;[5] decrement byte counter + brne txByteLoop ;[7] if we have more bytes start next one + ;[8] branch delay + +;make SE0: + cbr x1, USBMASK ;[8] prepare SE0 [spec says EOP may be 25 to 30 cycles] + lds x2, usbNewDeviceAddr;[9] + lsl x2 ;[11] we compare with left shifted address + out USBOUT, x1 ;[0] <-- out SE0 -- from now 2 bits = 24 cycles until bus idle + subi YL, 20 + 2 ;[1] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[2] +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[3] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1< +int main (int argc, char **argv) +{ + int i, j; + for (i=0; i<512; i++){ + unsigned short crc = i & 0xff; + for(j=0; j<8; j++) crc = (crc >> 1) ^ ((crc & 1) ? 0xa001 : 0); + if((i & 7) == 0) printf("\n.byte "); + printf("0x%02x, ", (i > 0xff ? (crc >> 8) : crc) & 0xff); + if(i == 255) printf("\n"); + } + return 0; +} + +// Use the following algorithm to compute CRC values: +ushort computeCrc(uchar *msg, uchar msgLen) +{ + uchar i; + ushort crc = 0xffff; + for(i = 0; i < msgLen; i++) + crc = usbCrcTable16[lo8(crc) ^ msg[i]] ^ hi8(crc); + return crc; +} +*/ + +.balign 256 +usbCrcTableLow: +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 +.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 + +; .balign 256 +usbCrcTableHigh: +.byte 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2 +.byte 0xC6, 0x06, 0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04 +.byte 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E +.byte 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8 +.byte 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A +.byte 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC +.byte 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6 +.byte 0xD2, 0x12, 0x13, 0xD3, 0x11, 0xD1, 0xD0, 0x10 +.byte 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32 +.byte 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4 +.byte 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE +.byte 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38 +.byte 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA +.byte 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C +.byte 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26 +.byte 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0 +.byte 0xA0, 0x60, 0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62 +.byte 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4 +.byte 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE +.byte 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68 +.byte 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA +.byte 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C +.byte 0xB4, 0x74, 0x75, 0xB5, 0x77, 0xB7, 0xB6, 0x76 +.byte 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0 +.byte 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92 +.byte 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54 +.byte 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E +.byte 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98 +.byte 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A +.byte 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C +.byte 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86 +.byte 0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 0x40 + diff --git a/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm20.inc b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm20.inc new file mode 100644 index 0000000..303abaf --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkKeyboard/usbdrvasm20.inc @@ -0,0 +1,360 @@ +/* Name: usbdrvasm20.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Jeroen Benschop + * Based on usbdrvasm16.inc from Christian Starkjohann + * Creation Date: 2008-03-05 + * Tabsize: 4 + * Copyright: (c) 2008 by Jeroen Benschop and OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + * Revision: $Id: usbdrvasm20.inc 740 2009-04-13 18:23:31Z cs $ + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 20 MHz version of the asssembler part of the USB driver. It +requires a 20 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! +*/ + +#define leap2 x3 +#ifdef __IAR_SYSTEMS_ASM__ +#define nextInst $+2 +#else +#define nextInst .+0 +#endif + +;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes +;nominal frequency: 20 MHz -> 13.333333 cycles per bit, 106.666667 cycles per byte +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts +;register use in receive loop: +; shift assembles the byte currently being received +; x1 holds the D+ and D- line state +; x2 holds the previous line state +; x4 (leap) is used to add a leap cycle once every three bytes received +; X3 (leap2) is used to add a leap cycle once every three stuff bits received +; bitcnt is used to determine when a stuff bit is due +; cnt holds the number of bytes left in the receive buffer + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt + push YL ;[-28] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-26] + push YL ;[-25] + push YH ;[-23] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-19] + rjmp foundK ;[-18] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-16] +;{3, 5} after falling D- edge, average delay: 4 cycles +;bit0 should be at 34 for center sampling. Currently at 4 so 30 cylces till bit 0 sample +;use 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push bitcnt ;[-16] +; [---] ;[-15] + lds YL, usbInputBufOffset;[-14] +; [---] ;[-13] + clr YH ;[-12] + subi YL, lo8(-(usbRxBuf));[-11] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-10] [rx loop init] + push shift ;[-9] +; [---] ;[-8] + ldi shift,0x40 ;[-7] set msb to "1" so processing bit7 can be detected + nop2 ;[-6] +; [---] ;[-5] + ldi bitcnt, 5 ;[-4] [rx loop init] + sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) + rjmp haveTwoBitsK ;[-2] + pop shift ;[-1] undo the push from before + pop bitcnt ;[1] + rjmp waitForK ;[3] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 27 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[0] + push x2 ;[2] + push x3 ;[4] (leap2) + ldi leap2, 0x55 ;[6] add leap cycle on 2nd,5th,8th,... stuff bit + push x4 ;[7] == leap + ldi leap, 0x55 ;[9] skip leap cycle on 2nd,5th,8th,... byte received + push cnt ;[10] + ldi cnt, USB_BUFSIZE ;[12] [rx loop init] + ldi x2, 1< +#ifndef __IAR_SYSTEMS_ASM__ +# include +#endif + +#define __attribute__(arg) /* not supported on IAR */ + +#ifdef __IAR_SYSTEMS_ASM__ +# define __ASSEMBLER__ /* IAR does not define standard macro for asm */ +#endif + +#ifdef __HAS_ELPM__ +# define PROGMEM __farflash +#else +# define PROGMEM __flash +#endif + +#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr)) + +/* The following definitions are not needed by the driver, but may be of some + * help if you port a gcc based project to IAR. + */ +#define cli() __disable_interrupt() +#define sei() __enable_interrupt() +#define wdt_reset() __watchdog_reset() +#define _BV(x) (1 << (x)) + +/* assembler compatibility macros */ +#define nop2 rjmp $+2 /* jump to next instruction */ +#define XL r26 +#define XH r27 +#define YL r28 +#define YH r29 +#define ZL r30 +#define ZH r31 +#define lo8(x) LOW(x) +#define hi8(x) (((x)>>8) & 0xff) /* not HIGH to allow XLINK to make a proper range check */ + +/* Depending on the device you use, you may get problems with the way usbdrv.h + * handles the differences between devices. Since IAR does not use #defines + * for MCU registers, we can't check for the existence of a particular + * register with an #ifdef. If the autodetection mechanism fails, include + * definitions for the required USB_INTR_* macros in your usbconfig.h. See + * usbconfig-prototype.h and usbdrv.h for details. + */ + +/* ------------------------------------------------------------------------- */ +#elif __CODEVISIONAVR__ /* check for CodeVision AVR */ +/* ------------------------------------------------------------------------- */ +/* This port is not working (yet) */ + +/* #define F_CPU _MCU_CLOCK_FREQUENCY_ seems to be defined automatically */ + +#include +#include + +#define __attribute__(arg) /* not supported on IAR */ + +#define PROGMEM __flash +#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr)) + +#ifndef __ASSEMBLER__ +static inline void cli(void) +{ + #asm("cli"); +} +static inline void sei(void) +{ + #asm("sei"); +} +#endif +#define _delay_ms(t) delay_ms(t) +#define _BV(x) (1 << (x)) +#define USB_CFG_USE_SWITCH_STATEMENT 1 /* macro for if() cascase fails for unknown reason */ + +#define macro .macro +#define endm .endmacro +#define nop2 rjmp .+0 /* jump to next instruction */ + +/* ------------------------------------------------------------------------- */ +#else /* default development environment is avr-gcc/avr-libc */ +/* ------------------------------------------------------------------------- */ + +#include +#ifdef __ASSEMBLER__ +# define _VECTOR(N) __vector_ ## N /* io.h does not define this for asm */ +#else +# include +#endif + +#define USB_READ_FLASH(addr) pgm_read_byte(addr) + +#define macro .macro +#define endm .endm +#define nop2 rjmp .+0 /* jump to next instruction */ + +#endif /* development environment */ + +/* for conveniecne, ensure that PRG_RDB exists */ +#ifndef PRG_RDB +# define PRG_RDB(addr) USB_READ_FLASH(addr) +#endif +#endif /* __usbportability_h_INCLUDED__ */ diff --git a/hardware/digistump/avr/libraries/DigisparkLCD/LiquidCrystal_I2C.cpp b/hardware/digistump/avr/libraries/DigisparkLCD/LiquidCrystal_I2C.cpp new file mode 100644 index 0000000..1ccf383 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkLCD/LiquidCrystal_I2C.cpp @@ -0,0 +1,321 @@ +// LiquidCrystal_I2C V2.0 + +#include "LiquidCrystal_I2C.h" +#include +#if defined(__AVR_ATtiny85__) || (__AVR_ATtiny2313__) || (__AVR_ATtiny167__) +#include "TinyWireM.h" // include this if ATtiny85 or ATtiny2313 +#else +#include // original lib include +#endif +#include "Arduino.h" + + +// When the display powers up, it is configured as follows: +// +// 1. Display clear +// 2. Function set: +// DL = 1; 8-bit interface data +// N = 0; 1-line display +// F = 0; 5x8 dot character font +// 3. Display on/off control: +// D = 0; Display off +// C = 0; Cursor off +// B = 0; Blinking off +// 4. Entry mode set: +// I/D = 1; Increment by 1 +// S = 0; No shift +// +// Note, however, that resetting the Arduino doesn't reset the LCD, so we +// can't assume that its in that state when a sketch starts (and the +// LiquidCrystal constructor is called). + +LiquidCrystal_I2C::LiquidCrystal_I2C(uint8_t lcd_Addr,uint8_t lcd_cols,uint8_t lcd_rows) +{ + _Addr = lcd_Addr; + _cols = lcd_cols; + _rows = lcd_rows; + _backlightval = LCD_NOBACKLIGHT; +} + +void LiquidCrystal_I2C::init(){ + init_priv(); +} + +void LiquidCrystal_I2C::init_priv() +{ +#if defined (__AVR_ATtiny85__) || (__AVR_ATtiny2313__) || (__AVR_ATtiny167__) + TinyWireM.begin(); // initialize I2C lib +#else // original call + Wire.begin(); +#endif + _displayfunction = LCD_4BITMODE | LCD_1LINE | LCD_5x8DOTS; + begin(_cols, _rows); +} + +void LiquidCrystal_I2C::begin(uint8_t cols, uint8_t lines, uint8_t dotsize) { + if (lines > 1) { + _displayfunction |= LCD_2LINE; + } + _numlines = lines; + + // for some 1 line displays you can select a 10 pixel high font + if ((dotsize != 0) && (lines == 1)) { + _displayfunction |= LCD_5x10DOTS; + } + + // SEE PAGE 45/46 FOR INITIALIZATION SPECIFICATION! + // according to datasheet, we need at least 40ms after power rises above 2.7V + // before sending commands. Arduino can turn on way befer 4.5V so we'll wait 50 + delay(50); + + // Now we pull both RS and R/W low to begin commands + expanderWrite(_backlightval); // reset expanderand turn backlight off (Bit 8 =1) + delay(1000); + + //put the LCD into 4 bit mode + // this is according to the hitachi HD44780 datasheet + // figure 24, pg 46 + + // we start in 8bit mode, try to set 4 bit mode + write4bits(0x03 << 4); + delayMicroseconds(4500); // wait min 4.1ms + + // second try + write4bits(0x03 << 4); + delayMicroseconds(4500); // wait min 4.1ms + + // third go! + write4bits(0x03 << 4); + delayMicroseconds(150); + + // finally, set to 4-bit interface + write4bits(0x02 << 4); + + + + // set # lines, font size, etc. + command(LCD_FUNCTIONSET | _displayfunction); + + // turn the display on with no cursor or blinking default + _displaycontrol = LCD_DISPLAYON | LCD_CURSOROFF | LCD_BLINKOFF; + display(); + + // clear it off + clear(); + + // Initialize to default text direction (for roman languages) + _displaymode = LCD_ENTRYLEFT | LCD_ENTRYSHIFTDECREMENT; + + // set the entry mode + command(LCD_ENTRYMODESET | _displaymode); + + home(); + +} + + + +/********** high level commands, for the user! */ +void LiquidCrystal_I2C::clear(){ + command(LCD_CLEARDISPLAY);// clear display, set cursor position to zero + delayMicroseconds(2000); // this command takes a long time! +} + +void LiquidCrystal_I2C::home(){ + command(LCD_RETURNHOME); // set cursor position to zero + delayMicroseconds(2000); // this command takes a long time! +} + +void LiquidCrystal_I2C::setCursor(uint8_t col, uint8_t row){ + int row_offsets[] = { 0x00, 0x40, 0x14, 0x54 }; + if ( row > _numlines ) { + row = _numlines-1; // we count rows starting w/0 + } + command(LCD_SETDDRAMADDR | (col + row_offsets[row])); +} + +// Turn the display on/off (quickly) +void LiquidCrystal_I2C::noDisplay() { + _displaycontrol &= ~LCD_DISPLAYON; + command(LCD_DISPLAYCONTROL | _displaycontrol); +} +void LiquidCrystal_I2C::display() { + _displaycontrol |= LCD_DISPLAYON; + command(LCD_DISPLAYCONTROL | _displaycontrol); +} + +// Turns the underline cursor on/off +void LiquidCrystal_I2C::noCursor() { + _displaycontrol &= ~LCD_CURSORON; + command(LCD_DISPLAYCONTROL | _displaycontrol); +} +void LiquidCrystal_I2C::cursor() { + _displaycontrol |= LCD_CURSORON; + command(LCD_DISPLAYCONTROL | _displaycontrol); +} + +// Turn on and off the blinking cursor +void LiquidCrystal_I2C::noBlink() { + _displaycontrol &= ~LCD_BLINKON; + command(LCD_DISPLAYCONTROL | _displaycontrol); +} +void LiquidCrystal_I2C::blink() { + _displaycontrol |= LCD_BLINKON; + command(LCD_DISPLAYCONTROL | _displaycontrol); +} + +// These commands scroll the display without changing the RAM +void LiquidCrystal_I2C::scrollDisplayLeft(void) { + command(LCD_CURSORSHIFT | LCD_DISPLAYMOVE | LCD_MOVELEFT); +} +void LiquidCrystal_I2C::scrollDisplayRight(void) { + command(LCD_CURSORSHIFT | LCD_DISPLAYMOVE | LCD_MOVERIGHT); +} + +// This is for text that flows Left to Right +void LiquidCrystal_I2C::leftToRight(void) { + _displaymode |= LCD_ENTRYLEFT; + command(LCD_ENTRYMODESET | _displaymode); +} + +// This is for text that flows Right to Left +void LiquidCrystal_I2C::rightToLeft(void) { + _displaymode &= ~LCD_ENTRYLEFT; + command(LCD_ENTRYMODESET | _displaymode); +} + +// This will 'right justify' text from the cursor +void LiquidCrystal_I2C::autoscroll(void) { + _displaymode |= LCD_ENTRYSHIFTINCREMENT; + command(LCD_ENTRYMODESET | _displaymode); +} + +// This will 'left justify' text from the cursor +void LiquidCrystal_I2C::noAutoscroll(void) { + _displaymode &= ~LCD_ENTRYSHIFTINCREMENT; + command(LCD_ENTRYMODESET | _displaymode); +} + +// Allows us to fill the first 8 CGRAM locations +// with custom characters +void LiquidCrystal_I2C::createChar(uint8_t location, uint8_t charmap[]) { + location &= 0x7; // we only have 8 locations 0-7 + command(LCD_SETCGRAMADDR | (location << 3)); + for (int i=0; i<8; i++) { + write(charmap[i]); + } +} + +// Turn the (optional) backlight off/on +void LiquidCrystal_I2C::noBacklight(void) { + _backlightval=LCD_NOBACKLIGHT; + expanderWrite(0); +} + +void LiquidCrystal_I2C::backlight(void) { + _backlightval=LCD_BACKLIGHT; + expanderWrite(0); +} + + + +/*********** mid level commands, for sending data/cmds */ + +inline void LiquidCrystal_I2C::command(uint8_t value) { + send(value, 0); +} + +inline size_t LiquidCrystal_I2C::write(uint8_t value) { + send(value, Rs); + return 0; +} + + + + + +/************ low level data pushing commands **********/ + +// write either command or data +void LiquidCrystal_I2C::send(uint8_t value, uint8_t mode) { + uint8_t highnib=value&0xf0; + uint8_t lownib=(value<<4)&0xf0; + write4bits((highnib)|mode); + write4bits((lownib)|mode); +} + +void LiquidCrystal_I2C::write4bits(uint8_t value) { + expanderWrite(value); + pulseEnable(value); +} + +void LiquidCrystal_I2C::expanderWrite(uint8_t _data){ +#if defined(__AVR_ATtiny85__) || (__AVR_ATtiny2313__)|| (__AVR_ATtiny167__) // Replaced Wire calls with ATtiny TWI calls + TinyWireM.beginTransmission(_Addr); + TinyWireM.send(((int)(_data) | _backlightval)); + TinyWireM.endTransmission(); +#else // original lib function + Wire.beginTransmission(_Addr); + Wire.write((int)(_data) | _backlightval); + Wire.endTransmission(); +#endif + } + +void LiquidCrystal_I2C::pulseEnable(uint8_t _data){ + expanderWrite(_data | En); // En high + delayMicroseconds(1); // enable pulse must be >450ns + + expanderWrite(_data & ~En); // En low + delayMicroseconds(50); // commands need > 37us to settle +} + + +// Alias functions + +void LiquidCrystal_I2C::cursor_on(){ + cursor(); +} + +void LiquidCrystal_I2C::cursor_off(){ + noCursor(); +} + +void LiquidCrystal_I2C::blink_on(){ + blink(); +} + +void LiquidCrystal_I2C::blink_off(){ + noBlink(); +} + +void LiquidCrystal_I2C::load_custom_character(uint8_t char_num, uint8_t *rows){ + createChar(char_num, rows); +} + +void LiquidCrystal_I2C::setBacklight(uint8_t new_val){ + if(new_val){ + backlight(); // turn backlight on + }else{ + noBacklight(); // turn backlight off + } +} + +void LiquidCrystal_I2C::printstr(const char c[]){ + //This function is not identical to the function used for "real" I2C displays + //it's here so the user sketch doesn't have to be changed + print(c); +} + + +// unsupported API functions +void LiquidCrystal_I2C::off(){} +void LiquidCrystal_I2C::on(){} +void LiquidCrystal_I2C::setDelay (int cmdDelay,int charDelay) {} +uint8_t LiquidCrystal_I2C::status(){return 0;} +uint8_t LiquidCrystal_I2C::keypad (){return 0;} +uint8_t LiquidCrystal_I2C::init_bargraph(uint8_t graphtype){return 0;} +void LiquidCrystal_I2C::draw_horizontal_graph(uint8_t row, uint8_t column, uint8_t len, uint8_t pixel_col_end){} +void LiquidCrystal_I2C::draw_vertical_graph(uint8_t row, uint8_t column, uint8_t len, uint8_t pixel_row_end){} +void LiquidCrystal_I2C::setContrast(uint8_t new_val){} + + \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigisparkLCD/LiquidCrystal_I2C.h b/hardware/digistump/avr/libraries/DigisparkLCD/LiquidCrystal_I2C.h new file mode 100644 index 0000000..82ac972 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkLCD/LiquidCrystal_I2C.h @@ -0,0 +1,135 @@ +// LiquidCrystal_I2C V2.0 +// Note: The original libe file has beem modified to support the ATtiny85 1/20/11 by "BroHogan" +// All changes can be located by searching for "__AVR_ATtiny85__". + +#ifndef LiquidCrystal_I2C_h +#define LiquidCrystal_I2C_h + +#include +#include "Print.h" + +#if defined(__AVR_ATtiny85__) || (__AVR_ATtiny2313__) +#include "TinyWireM.h" // include this if ATtiny85 or ATtiny2313 +#else +#include // original lib include +#endif + + +// commands +#define LCD_CLEARDISPLAY 0x01 +#define LCD_RETURNHOME 0x02 +#define LCD_ENTRYMODESET 0x04 +#define LCD_DISPLAYCONTROL 0x08 +#define LCD_CURSORSHIFT 0x10 +#define LCD_FUNCTIONSET 0x20 +#define LCD_SETCGRAMADDR 0x40 +#define LCD_SETDDRAMADDR 0x80 + +// flags for display entry mode +#define LCD_ENTRYRIGHT 0x00 +#define LCD_ENTRYLEFT 0x02 +#define LCD_ENTRYSHIFTINCREMENT 0x01 +#define LCD_ENTRYSHIFTDECREMENT 0x00 + +// flags for display on/off control +#define LCD_DISPLAYON 0x04 +#define LCD_DISPLAYOFF 0x00 +#define LCD_CURSORON 0x02 +#define LCD_CURSOROFF 0x00 +#define LCD_BLINKON 0x01 +#define LCD_BLINKOFF 0x00 + +// flags for display/cursor shift +#define LCD_DISPLAYMOVE 0x08 +#define LCD_CURSORMOVE 0x00 +#define LCD_MOVERIGHT 0x04 +#define LCD_MOVELEFT 0x00 + +// flags for function set +#define LCD_8BITMODE 0x10 +#define LCD_4BITMODE 0x00 +#define LCD_2LINE 0x08 +#define LCD_1LINE 0x00 +#define LCD_5x10DOTS 0x04 +#define LCD_5x8DOTS 0x00 + +// flags for backlight control +#define LCD_BACKLIGHT 0x08 +#define LCD_NOBACKLIGHT 0x00 + +#define En B00000100 // Enable bit +#define Rw B00000010 // Read/Write bit +#define Rs B00000001 // Register select bit + +class LiquidCrystal_I2C : public Print { +public: + LiquidCrystal_I2C(uint8_t lcd_Addr,uint8_t lcd_cols,uint8_t lcd_rows); + void begin(uint8_t cols, uint8_t rows, uint8_t charsize = LCD_5x8DOTS ); + void clear(); + void home(); + void noDisplay(); + void display(); + void noBlink(); + void blink(); + void noCursor(); + void cursor(); + void scrollDisplayLeft(); + void scrollDisplayRight(); + void printLeft(); + void printRight(); + void leftToRight(); + void rightToLeft(); + void shiftIncrement(); + void shiftDecrement(); + void noBacklight(); + void backlight(); + void autoscroll(); + void noAutoscroll(); + void createChar(uint8_t, uint8_t[]); + void setCursor(uint8_t, uint8_t); +#if defined(ARDUINO) && ARDUINO >= 100 + virtual size_t write(uint8_t); +#else + virtual void write(uint8_t); +#endif + void command(uint8_t); + void init(); + +////compatibility API function aliases +void blink_on(); // alias for blink() +void blink_off(); // alias for noBlink() +void cursor_on(); // alias for cursor() +void cursor_off(); // alias for noCursor() +void setBacklight(uint8_t new_val); // alias for backlight() and nobacklight() +void load_custom_character(uint8_t char_num, uint8_t *rows); // alias for createChar() +void printstr(const char[]); + +////Unsupported API functions (not implemented in this library) +uint8_t status(); +void setContrast(uint8_t new_val); +uint8_t keypad(); +void setDelay(int,int); +void on(); +void off(); +uint8_t init_bargraph(uint8_t graphtype); +void draw_horizontal_graph(uint8_t row, uint8_t column, uint8_t len, uint8_t pixel_col_end); +void draw_vertical_graph(uint8_t row, uint8_t column, uint8_t len, uint8_t pixel_col_end); + + +private: + void init_priv(); + void send(uint8_t, uint8_t); + void write4bits(uint8_t); + void expanderWrite(uint8_t); + void pulseEnable(uint8_t); + uint8_t _Addr; + uint8_t _displayfunction; + uint8_t _displaycontrol; + uint8_t _displaymode; + uint8_t _numlines; + uint8_t _cols; + uint8_t _rows; + uint8_t _backlightval; +}; + +#endif diff --git a/hardware/digistump/avr/libraries/DigisparkLCD/examples/BasicUsage/BasicUsage.ino b/hardware/digistump/avr/libraries/DigisparkLCD/examples/BasicUsage/BasicUsage.ino new file mode 100644 index 0000000..80e3576 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkLCD/examples/BasicUsage/BasicUsage.ino @@ -0,0 +1,36 @@ +/* ATtiny85 as an I2C Master Ex2 BroHogan 1/21/11 + * Modified for Digistump - Digispark LCD Shield by Erik Kettenburg 11/2012 + * SETUP: + * ATtiny Pin 1 = (RESET) N/U ATtiny Pin 2 = (D3) N/U + * ATtiny Pin 3 = (D4) to LED1 ATtiny Pin 4 = GND + * ATtiny Pin 5 = SDA on DS1621 & GPIO ATtiny Pin 6 = (D1) to LED2 + * ATtiny Pin 7 = SCK on DS1621 & GPIO ATtiny Pin 8 = VCC (2.7-5.5V) + * NOTE! - It's very important to use pullups on the SDA & SCL lines! + * PCA8574A GPIO was used wired per instructions in "info" folder in the LiquidCrystal_I2C lib. + * This ex assumes A0-A2 are set HIGH for an addeess of 0x3F + * LiquidCrystal_I2C lib was modified for ATtiny - on Playground with TinyWireM lib. + * TinyWireM USAGE & CREDITS: - see TinyWireM.h + */ + +//#define DEBUG +#include // I2C Master lib for ATTinys which use USI - comment this out to use with standard arduinos +#include // for LCD w/ GPIO MODIFIED for the ATtiny85 + +#define GPIO_ADDR 0x27 // (PCA8574A A0-A2 @5V) typ. A0-A3 Gnd 0x20 / 0x38 for A - 0x27 is the address of the Digispark LCD modules. + + +LiquidCrystal_I2C lcd(GPIO_ADDR,16,2); // set address & 16 chars / 2 lines + + +void setup(){ + TinyWireM.begin(); // initialize I2C lib - comment this out to use with standard arduinos + lcd.init(); // initialize the lcd + lcd.backlight(); // Print a message to the LCD. + lcd.print("Digispark!"); +} + + +void loop(){ + +} + diff --git a/hardware/digistump/avr/libraries/DigisparkLCD/info/BC557.pdf b/hardware/digistump/avr/libraries/DigisparkLCD/info/BC557.pdf new file mode 100644 index 0000000..05790db --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkLCD/info/BC557.pdf @@ -0,0 +1,122 @@ +BC 556 ... BC 559 General Purpose Transistors +PNP + Si-Epitaxial PlanarTransistors PNP + Standard Pinning + 1=C 2=B 3=E Power dissipation – Verlustleistung 500 mW + + Plastic case TO-92 + Kunststoffgehäuse (10D3) + + Weight approx. – Gewicht ca. 0.18 g + + Plastic material has UL classification 94V-0 + Gehäusematerial UL94V-0 klassifiziert + + Standard packaging taped in ammo pack + Standard Lieferform gegurtet in Ammo-Pack + +Maximum ratings (TA = 25/C) Grenzwerte (TA = 25/C) + + BC 556 BC 557 BC 558/559 + 65 V +Collector-Emitter-voltage B open - VCE0 80 V 45 V 30 V + - VCB0 +Collector-Base-voltage E open - VEB0 50 V 30 V + Ptot +Emitter-Base-voltage C open - IC 5V + Tj +Power dissipation – Verlustleistung TS 500 mW 1) + +Collector current – Kollektorstrom (DC) 100 mA + +Junction temp. – Sperrschichttemperatur 150/C + - 55…+ 150/C +Storage temperature – Lagerungstemperatur + +Characteristics (Tj = 25/C) Kennwerte (Tj = 25/C) + + Group A Group B Group C + +DC current gain – Kollektor-Basis-Stromverhältnis 110...220 + + - VCE = 5 V, - IC = 2 mA hFE typ. 220 200...460 420...800 + +h-Parameters at - VCE = 5V, - IC = 2 mA, f = 1 kHz 1.6...4.5 kS + 18 < 30 :S + Small signal current gain hfe typ. 330 typ. 600 + Stromverstärkung typ.1.5 *10-4 + + Input impedance – Eingangsimpedanz hie – 3.2...8.5 kS 6...15 kS + 30 < 60 :S 60 < 110 :S + Output admittance – Ausg.-Leitwert hoe + + Reverse voltage transfer ratio hre typ. 2 *10-4 typ. 3 *10-4 + Spannungsrückwirkung + +Collector saturation voltage – Kollektor-Sättigungsspg. + + - IC = 100 mA, - IB = 5 mA -VCEsat – 300 mV + +1) Valid, if leads are kept at ambient temperature at a distance of 2 mm from case + + Gültig, wenn die Anschlußdrähte in 2 mm Abstand von Gehäuse auf Umgebungstemperatur gehalten werden + +8 01.11.2003 + General Purpose Transistors BC 556 ... BC 559 + +Characteristics (Tj = 25/C) Kennwerte (Tj = 25/C) + + Min. Typ. Max. + +Base saturation voltage – Basis-Sättigungsspannung + + - IC = 100 mA, - IB = 5 mA - VBEsat – – 1V +Base-Emitter voltage – Basis-Emitter-Spannung + +- VCE = 5 V, - IC = 2 mA - VBE 580 mV 660 mV 700 mV + +Collector-Emitter cutoff current – Kollektorreststrom + +- VCE = 60 V BC 556 - ICE0 – – 0.1 :A + - ICE0 +- VCE = 40 V BC 557 - ICE0 – – 0.1 :A + - ICE0 +- VCE = 25 V BC 558 – – 0.1 :A + +- VCE = 25 V BC 559 – – 0.1 :A + +Gain-Bandwidth Product – Transitfrequenz + +- VCE = 5 V, - IC = 10 mA, f = 100 MHz fT 150 MHz – – + +Collector-Base Capacitance – Kollektor-Basis-Kapazität + +- VCB = 10 V, IE = ie = 0, f = 1 MHz CCB0 – – 6 pF + +Emitter-Base Capacitance – Emitter-Basis-Kapazität + + - VEB = 0.5 V, f = 1 MHz CEB0 – 9 pF – +Noise figure – Rauschzahl + BC 556... – 2 dB 10 dB + - VCE = 5 V, - IC = 200 :A F + RG = 2 kS f = 1 kHz, – 1 dB 4 dB + )f = 200 Hz BC 558 + BC 559 F + +Thermal resistance junction to ambient air RthA 200 K/W 1) +Wärmewiderstand Sperrschicht – umgebende Luft + +Recommended complementary PNP transistors BC 546 ... BC 549 +Empfohlene komplementäre PNP-Transistoren + +Available current gain groups per type BC 556A BC 556B BC 557C +Lieferbare Stromverstärkungsgruppen pro Typ BC 557A BC 557B BC 558C + BC 558A BC 558B BC 559C + BC 559B + +1) Valid, if leads are kept at ambient temperature at a distance of 2 mm from case + +Gültig, wenn die Anschlußdrähte in 2 mm Abstand von Gehäuse auf Umgebungstemperatur gehalten werden + +01.11.2003 9 + diff --git a/hardware/digistump/avr/libraries/DigisparkLCD/info/Image.jpg b/hardware/digistump/avr/libraries/DigisparkLCD/info/Image.jpg new file mode 100644 index 0000000..a72b23d Binary files /dev/null and b/hardware/digistump/avr/libraries/DigisparkLCD/info/Image.jpg differ diff --git a/hardware/digistump/avr/libraries/DigisparkLCD/info/PCF8574P.pdf b/hardware/digistump/avr/libraries/DigisparkLCD/info/PCF8574P.pdf new file mode 100644 index 0000000..e164e76 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkLCD/info/PCF8574P.pdf @@ -0,0 +1 @@ + diff --git a/hardware/digistump/avr/libraries/DigisparkLCD/info/Schematic_diagram.jpg b/hardware/digistump/avr/libraries/DigisparkLCD/info/Schematic_diagram.jpg new file mode 100644 index 0000000..920ea2b Binary files /dev/null and b/hardware/digistump/avr/libraries/DigisparkLCD/info/Schematic_diagram.jpg differ diff --git a/hardware/digistump/avr/libraries/DigisparkLCD/info/notes_for_pollin_interface.txt b/hardware/digistump/avr/libraries/DigisparkLCD/info/notes_for_pollin_interface.txt new file mode 100644 index 0000000..4aaa1bc --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkLCD/info/notes_for_pollin_interface.txt @@ -0,0 +1,55 @@ +Notes for users with a Pollin.de interface board +http://www.pollin.de/shop/dt/NDU4OTgxOTk-/Bausaetze_Module/Bausaetze/LCD_I2C_Modul.html + +The pollin interface board will not work with de default library. +To get it working two control lines to the LCD need to be changed. + +Open file "LiquidCrystal_I2C.h" with a text editor like Notepad (not WordPad !) + +In that file look for: +#define En B00010000 // Enable bit +#define Rw B00100000 // Read/Write bit +#define Rs B01000000 // Register select bit + +Replace these lines by: +#define En B01000000 // Enable bit +#define Rw B00100000 // Read/Write bit +#define Rs B00010000 // Register select bit + + + +People at Pollin also have misunderstood the PCF8574 Datasheet and list the wrong addresses on their PCB +For PCF8574A the addressing is: + +Jp3 Jp2 Jp1 +A2 A1 A0 Dec Hex +L L L 56 0x38 +L L H 57 0x39 +L H L 64 0x40 +L H H 74 0x4A +H L L 75 0x4B +H L H 76 0x4C +H H L 77 0x4D +H H H 78 0x4E + +They also seem to ship boards with a PCF8574 +For PCF8574 the addressing is: + +Jp3 Jp2 Jp1 +A2 A1 A0 Dec Hex +L L L 32 0x20 +L L H 33 0x21 +L H L 34 0x22 +L H H 35 0x23 +H L L 36 0x24 +H L H 37 0x25 +H H L 38 0x26 +H H H 39 0x27 + + +They have also chosen two rather high pull-up resistors (10K) for the I2C lines. Usually two 4K7 resistors should do the job. +Please note that on a I2C bus only one device should have the pull-up resistors installed! + +I hope this helps in getting your LCD working. + +Mario \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigisparkLCD/info/readme.txt b/hardware/digistump/avr/libraries/DigisparkLCD/info/readme.txt new file mode 100644 index 0000000..7a7f0a7 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkLCD/info/readme.txt @@ -0,0 +1,36 @@ +LiquidCrystal_I2C V2.0 + +The LiquidCrystal_I2C library is a modified version of the standard LiquidCrystal library as found on +the Arduino website. +This library is intended to be used when a parallel HD44780 compatible LCD is controlled over I2C using +a PCF8574 extender (see datasheet for details). +4 of the 8 outputs are used for LDC data lines 4 to 7. +3 outputs are used for the Enable, register-select and Read/Write lines. +The one output left can be used to control the backlight of the LCD (if available). +For backlight control some extra resistors and a pnp-type transistor are required (for details see +schematic diagram). + +The PCF8574 extender is available in two versions, the PCF8574 and the PCF8574A. +The only difference between the two is the I2C base address. +The base address for the PCF8574 is 0x20 and the base address for the PCF8574A is 0x38. +The examples included in this zip file assume the use of an PCF8574 set for address 0x20 +(A0, A1 and A3 grounded). + +For compatibility reasons this library contains some aliases for functions that are known under different +names in other libraries. This should make it fairly easy to implement the library in existing sketches +without changing to much code. +Functions not supported by this library will return nothing at all and in case a return value is expected +the function will return 0. + +Update 8-12-2011: +Due to the relaese of Arduino IDE 1.0 some changes were made to the library to get it working under the new IDE. +Because of these changes this version of the LiquidCrystal_I2C library can not be used for older IDE versions. +The old version of the LiquidCrystal_I2Clibrary can be downloaded form http://www.xs4all.nl/~hmario/arduino/LiquidCrystal_I2C/V1.0/LiquidCrystal_I2C_V1.0.zip + +Download the latest version from: +http://www.xs4all.nl/~hmario/arduino/LiquidCrystal_I2C/LiquidCrystal_I2C.zip +(Thanks to Ailton F. for beta testing.) + + +Mario H. +atmega@xs4all.nl \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/DigisparkLCD/keywords.txt b/hardware/digistump/avr/libraries/DigisparkLCD/keywords.txt new file mode 100644 index 0000000..198480f --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkLCD/keywords.txt @@ -0,0 +1,47 @@ +########################################### +# Syntax Coloring Map For LiquidCrystal_I2C +# Version 2.0 +########################################### + +########################################### +# Datatypes (KEYWORD1) +########################################### + +LiquidCrystal_I2C KEYWORD1 + +########################################### +# Methods and Functions (KEYWORD2) +########################################### +init KEYWORD2 +begin KEYWORD2 +clear KEYWORD2 +home KEYWORD2 +noDisplay KEYWORD2 +display KEYWORD2 +noBlink KEYWORD2 +blink KEYWORD2 +noCursor KEYWORD2 +cursor KEYWORD2 +scrollDisplayLeft KEYWORD2 +scrollDisplayRight KEYWORD2 +leftToRight KEYWORD2 +rightToLeft KEYWORD2 +shiftIncrement KEYWORD2 +shiftDecrement KEYWORD2 +noBacklight KEYWORD2 +backlight KEYWORD2 +autoscroll KEYWORD2 +noAutoscroll KEYWORD2 +createChar KEYWORD2 +setCursor KEYWORD2 +print KEYWORD2 +blink_on KEYWORD2 +blink_off KEYWORD2 +cursor_on KEYWORD2 +cursor_off KEYWORD2 +setBacklight KEYWORD2 +load_custom_character KEYWORD2 +printstr KEYWORD2 +########################################### +# Constants (LITERAL1) +########################################### diff --git a/hardware/digistump/avr/libraries/DigisparkRGB/DigisparkRGB.cpp b/hardware/digistump/avr/libraries/DigisparkRGB/DigisparkRGB.cpp new file mode 100644 index 0000000..3b2766b --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkRGB/DigisparkRGB.cpp @@ -0,0 +1,78 @@ +#include +#include +#include + +#include "DigisparkRGB.h" +#include "Arduino.h" + +#define set(x) |= (1< +/* + Digispark RGB + + This example shows how to use soft PWM to fade 3 colors. + Note: This is only necessary for PB2 (pin 2) - Blue, as Red (pin 0) and Green (pin 1) as well as pin 4 support the standard Arduino analogWrite() function. + + This example code is in the public domain. + */ +byte RED = 0; +byte BLUE = 2; +byte GREEN = 1; +byte COLORS[] = {RED, BLUE, GREEN}; + +// the setup routine runs once when you press reset: +void setup() { + DigisparkRGBBegin(); +} + + +void loop () +{ +//direction: up = true, down = false +boolean dir = true; +int i = 0; + +while(1) +{ +fade(COLORS[i%3], dir); +i++; +dir = !dir; +} +} +void fade(byte Led, boolean dir) +{ +int i; + +//if fading up +if (dir) +{ +for (i = 0; i < 256; i++) +{ +DigisparkRGB(Led, i); +DigisparkRGBDelay(25);//1); +} +} +else +{ +for (i = 255; i >= 0; i--) +{ +DigisparkRGB(Led, i); +DigisparkRGBDelay(25);//1); +} +} +} + + + diff --git a/hardware/digistump/avr/libraries/DigisparkRGB/keywords.txt b/hardware/digistump/avr/libraries/DigisparkRGB/keywords.txt new file mode 100644 index 0000000..2cd9471 --- /dev/null +++ b/hardware/digistump/avr/libraries/DigisparkRGB/keywords.txt @@ -0,0 +1,3 @@ +DigisparkRGBBegin KEYWORD2 +DigisparkRGB KEYWORD2 +DigisparkRGBDelay KEYWORD2 \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/BasicRobot/BasicRobot.ino b/hardware/digistump/avr/libraries/Digispark_Examples/BasicRobot/BasicRobot.ino new file mode 100644 index 0000000..6b05ee4 --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/BasicRobot/BasicRobot.ino @@ -0,0 +1,80 @@ +void setup() { + // put your setup code here, to run once: + botInit(); +} + + +void loop() { + // put your main code here, to run repeatedly: + botForward(255); //speed can be any value from 0 (stopped) to 255 (full) + delay(5000); + botReverse(255); + delay(5000); + botRight(255); + delay(5000); + botHardRight(255); + delay(5000); + botLeft(255); + delay(5000); + botHardLeft(255); + delay(5000); + botStop(); + delay(5000); +} + +void botForward(int botSpeed){ + digitalWrite(2,HIGH); + digitalWrite(5,HIGH); + analogWrite(0,botSpeed); + analogWrite(1,botSpeed); +} + +void botReverse(int botSpeed){ + digitalWrite(2,LOW); + digitalWrite(5,LOW); + analogWrite(0,botSpeed); + analogWrite(1,botSpeed); +} + +void botRight(int botSpeed){ + digitalWrite(2,HIGH); + digitalWrite(5,LOW); + analogWrite(0,botSpeed); + analogWrite(1,0); +} + +void botHardRight(int botSpeed){ + digitalWrite(2,HIGH); + digitalWrite(5,LOW); + analogWrite(0,botSpeed); + analogWrite(1,botSpeed); +} + +void botLeft(int botSpeed){ + digitalWrite(2,LOW); + digitalWrite(5,HIGH); + analogWrite(0,0); + analogWrite(1,botSpeed); +} + +void botHardLeft(int botSpeed){ + digitalWrite(2,LOW); + digitalWrite(5,HIGH); + analogWrite(0,botSpeed); + analogWrite(1,botSpeed); +} + +void botStop(){ + digitalWrite(2,LOW); + digitalWrite(5,LOW); + analogWrite(0,0); + analogWrite(1,0); +} + +void botInit(){ + pinMode(0,OUTPUT); + pinMode(1,OUTPUT); + pinMode(2,OUTPUT); + pinMode(5,OUTPUT); +} + diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/CharliePlexMarquee/charlieplex.ino b/hardware/digistump/avr/libraries/Digispark_Examples/CharliePlexMarquee/charlieplex.ino new file mode 100644 index 0000000..a0e6043 --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/CharliePlexMarquee/charlieplex.ino @@ -0,0 +1,138 @@ +// where does our characterMap start in the ASCII code +#define MAP_START 32 + +#define DISPLAY_WIDTH 4 +#define DISPLAY_HEIGHT 5 + +// "pixels" per second +#define SPEED 10 + +// the text to display +#define DISPLAY_STRING "HELLO WORLD!" + + +// maps characters to their 4x5 grid +unsigned long characterMap[59]; + +// set up a character in the characterMap +void Chr(char theChar, unsigned long value) { + characterMap[theChar - MAP_START] = value; +} + +// The offset of our string in the display +int offset = 0; +unsigned long lastMillis = 0; +unsigned long currentMillis = 0; +unsigned int timeout; + +char myString[] = DISPLAY_STRING; +int length = sizeof(myString); + +// render the string on the given offset +void renderString(char *theString, int offset) { + int index = 0; + while (theString[index]) { + renderCharacter(theString[index], offset - index * (DISPLAY_WIDTH + 1)); + index++; + } +} + +// render a character on the given offset +void renderCharacter(char theChar, int charOffset) { + if (charOffset <= -DISPLAY_WIDTH || charOffset > DISPLAY_WIDTH) { + // off the 'screen' nothing to do + return; + } + + unsigned long graphic = characterMap[theChar - MAP_START]; + + for (byte y = 0; y < DISPLAY_HEIGHT; y++) { + for (byte x = 0; x < DISPLAY_WIDTH; x++) { + if (graphic & 0x1) { + // 3 - x to reverse order + lightPixel(3 - x - charOffset, y); + } + graphic = graphic >> 1; + } + } +} + +// light a pixel at the given coordinates +void lightPixel(byte x, byte y) { + if (x >= 0 && x < DISPLAY_WIDTH) { + if (y <= x) { + x++; + } + LEDon(y, x); + } +} + +// turn on the pins to light a LED +void LEDon(byte vin, byte gnd) { + delay(1); + pinMode(0, INPUT); + pinMode(1, INPUT); + pinMode(2, INPUT); + pinMode(3, INPUT); + pinMode(4, INPUT); + + pinMode(vin, OUTPUT); + pinMode(gnd, OUTPUT); + digitalWrite(vin, HIGH); + digitalWrite(gnd, LOW); +} + +// runs at start +void setup() { + // set up render map + + // Rows: 1---2---3---4---5--- + Chr('A', 0b01101001111110011001); + Chr('B', 0b11101001111010011110); + Chr('C', 0b01111000100010000111); + Chr('D', 0b11101001100110011110); + Chr('E', 0b11111000111010001111); + Chr('F', 0b11111000111010001000); + Chr('G', 0b01111000101110010110); + Chr('H', 0b10011001111110011001); + Chr('I', 0b01110010001000100111); + Chr('J', 0b01110010001010100100); + Chr('K', 0b10011010110010101001); + Chr('L', 0b10001000100010001111); + Chr('M', 0b10011111111110011001); + Chr('N', 0b10011101101110011001); + Chr('O', 0b01101001100110010110); + Chr('P', 0b11101001111010001000); + Chr('Q', 0b01101001101101100001); + Chr('R', 0b11101001111010101001); + Chr('S', 0b11111000111100011111); + Chr('T', 0b01110010001000100010); + Chr('U', 0b10011001100110010110); + Chr('V', 0b10011001100110100100); + Chr('W', 0b10011001111111110110); + Chr('X', 0b10011001011010011001); + Chr('Y', 0b10011001011000101100); + Chr('Z', 0b11110001001001001111); + Chr(' ', 0b00000000000000000000); + Chr('!', 0b01000100010000000100); + + // how long to wait between shifting the display + timeout = 1000 / SPEED; +} + +// loops continuously +void loop() { + currentMillis = millis(); + + renderString(myString, offset); + + if (currentMillis - lastMillis > timeout) { + lastMillis = currentMillis; + // shift string over one "pixel" + offset++; + // if it's past the length of the string, start over from the beginning + if (offset > length * (DISPLAY_WIDTH + 1)) { + offset = -DISPLAY_WIDTH; + } + } +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/Charlieplex/Charlieplex.ino b/hardware/digistump/avr/libraries/Digispark_Examples/Charlieplex/Charlieplex.ino new file mode 100644 index 0000000..6f589ed --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/Charlieplex/Charlieplex.ino @@ -0,0 +1,63 @@ +void setup() { + // initialize the digital pin as an output. + + +} + +// the loop routine runs over and over again forever: +void loop() { + LEDon(0, 1); + delay(1000); + LEDon(0, 2); + delay(1000); + LEDon(0, 3); + delay(1000); + LEDon(0, 4); + delay(1000); + LEDon(1, 0); + delay(1000); + LEDon(1, 2); + delay(1000); + LEDon(1, 3); + delay(1000); + LEDon(1, 4); + delay(1000); + LEDon(2, 0); + delay(1000); + LEDon(2, 1); + delay(1000); + LEDon(2, 3); + delay(1000); + LEDon(2, 4); + delay(1000); + LEDon(3, 0); + delay(1000); + LEDon(3, 1); + delay(1000); + LEDon(3, 2); + delay(1000); + LEDon(3, 4); + delay(1000); + LEDon(4, 0); + delay(1000); + LEDon(4, 1); + delay(1000); + LEDon(4, 2); + delay(1000); + LEDon(4, 3); + delay(1000); +} + +void LEDon(int vin, int gnd) { + pinMode(0, INPUT); + pinMode(1, INPUT); + pinMode(2, INPUT); + pinMode(3, INPUT); + pinMode(4, INPUT); + pinMode(5, INPUT); + + pinMode(vin, OUTPUT); + pinMode(gnd, OUTPUT); + digitalWrite(vin, HIGH); + digitalWrite(gnd, LOW); +} diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/EEPROM/EEPROM.ino b/hardware/digistump/avr/libraries/Digispark_Examples/EEPROM/EEPROM.ino new file mode 100644 index 0000000..6efac43 --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/EEPROM/EEPROM.ino @@ -0,0 +1,53 @@ +#include + +#define disk1 0x50 //Address of 24LC256 eeprom chip +int returned = 0; +void setup(void) +{ + //Serial.begin(9600); + TinyWireM.begin(); + + unsigned int address = 0; + pinMode(5, OUTPUT); + + writeEEPROM(disk1, address, 5); + returned = readEEPROM(disk1, address); + + while(returned>0){ + digitalWrite(5,HIGH); + delay(500); + digitalWrite(5,LOW); + delay(500); + returned--; + } + +} + +void loop(){} + +void writeEEPROM(int deviceaddress, unsigned int eeaddress, byte data ) +{ + TinyWireM.beginTransmission(deviceaddress); + TinyWireM.send((int)(eeaddress >> 8)); // MSB + TinyWireM.send((int)(eeaddress & 0xFF)); // LSB + TinyWireM.send(data); + TinyWireM.endTransmission(); + + delay(5); +} + +byte readEEPROM(int deviceaddress, unsigned int eeaddress ) +{ + byte rdata = 0xFF; + + TinyWireM.beginTransmission(deviceaddress); + TinyWireM.send((int)(eeaddress >> 8)); // MSB + TinyWireM.send((int)(eeaddress & 0xFF)); // LSB + TinyWireM.endTransmission(); + + TinyWireM.requestFrom(deviceaddress,1); + + if (TinyWireM.available()) rdata = TinyWireM.receive(); + + return rdata; +} diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/Expander/Expander.ino b/hardware/digistump/avr/libraries/Digispark_Examples/Expander/Expander.ino new file mode 100644 index 0000000..8c31259 --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/Expander/Expander.ino @@ -0,0 +1,33 @@ +#include +#define expander 0x20 + +byte expanderStatus = B11111111; //all off + +void setup() +{ + TinyWireM.begin(); +} + +void loop() +{ + expanderWrite(0,HIGH); + delay(1000); + expanderWrite(0,LOW); + delay(1000); +} + + +void expanderWrite(byte pinNumber, boolean state){ + if(state == HIGH) + expanderStatus &= ~(1 << pinNumber); + else + expanderStatus |= (1 << pinNumber); + + expanderWrite(expanderStatus); +} + +void expanderWrite(byte _data ) { + TinyWireM.beginTransmission(expander); + TinyWireM.send(_data); + TinyWireM.endTransmission(); +} diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/GPS/GPS.ino b/hardware/digistump/avr/libraries/Digispark_Examples/GPS/GPS.ino new file mode 100644 index 0000000..e5fa1c4 --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/GPS/GPS.ino @@ -0,0 +1,289 @@ +#include "DigiKeyboard.h" + +char nmeaString[57]; +bool gpsReady = 0; +bool gpsDateTimeReady = 0; + +void setup() { + + DigiKeyboard.delay(3000);//When this sketch is used with DigiKeyboard as it is here, it tends to need a bit of a delay at the start + Serial.begin(9600); //Connect to GPS + DigiKeyboard.delay(1000);//We need a delay before we init the GPS module + initGPS(); //Send init msgs to GPS + +} + + +void loop() { + + if(updateGPS()){ //this will return true if it was able to get a valid string from the GPS + DigiKeyboard.println(nmeaString); //the whole string from the GPS unit + + + DigiKeyboard.println(getStatus()); //A means we are good to go, V means it is still getting a fix + if(gpsDateTimeReady){ //date and time are oftenr eady before the rest of the data, so if we are just looking for that we can use it much sooner + DigiKeyboard.println(getTime()); + DigiKeyboard.println(getDate()); + } + if(gpsReady){ + DigiKeyboard.println(getLat()); + DigiKeyboard.println(getLon()); + } + } + DigiKeyboard.delay(1000); + + +} + +void initGPS(){ + + Serial.println(F("$PUBX,40,RMC,1,1,1,0*46")); //turn on RMC msgs + Serial.println(F("$PUBX,40,GLL,0,0,0,0*5C")); //turn off the rest + Serial.println(F("$PUBX,40,GGA,0,0,0,0*5A")); + Serial.println(F("$PUBX,40,GSA,0,0,0,0*4E")); + Serial.println(F("$PUBX,40,GSV,0,0,0,0*59")); + Serial.println(F("$PUBX,40,VTG,0,0,0,0*5E")); + +} + + + + +bool updateGPS() { + + + while(Serial.read()!='$'); + while(Serial.read()!=','); + unsigned int i = 0; + while(i<56){nmeaString[i] = Serial.read();i++;} + nmeaString[56] = '\0'; + if(getStatus() == 'A'){ //we're good to go + gpsReady = 1; + gpsDateTimeReady = 1; + } + else if (getStatus() == 'V'){ //string is valid but gps isn't ready - check if we have date and time at least + gpsReady = 0; + gpsDateTimeReady = dateTimeReady(); + } + else + return false; //we got an invalid string + + return true; + +} + +unsigned int charIndexOf(char* array, char searchChar){ + unsigned int i = 0; + while(array[i] != '\0'){ + if(array[i] == searchChar) + return i; + i++; + } + return false; +} + +unsigned int charLastIndexOf(char* array, char searchChar){ + unsigned int i = 0; + unsigned int l = '\0'; + while(array[i] != '\0'){ + if(array[i] == searchChar) + l=i; + i++; + } + if(l=='\0') + return false; + else + return l; +} + + + +long getTime(){ + char time[7]; + memcpy(time,&nmeaString[0],6); + time[6] = '\0'; + return atol(time); +} + + +int getHour(){ + char time[3]; + memcpy(time,&nmeaString[0],2); + time[2] = '\0'; + return atoi(time); +} + +int getMin(){ + char time[3]; + memcpy(time,&nmeaString[2],2); + time[2] = '\0'; + return atoi(time); +} + +int getSec(){ + char time[3]; + memcpy(time,&nmeaString[4],2); + time[2] = '\0'; + return atoi(time); +} + +char getStatus(){ + return nmeaString[charIndexOf(nmeaString,',')+1]; //this has to work even if the other data isn't present +} + + +bool dateTimeReady(){ + if(nmeaString[0] != ',' && nmeaString[18] != ','){ + return true; + } + else + return false; +} + +float getLat(){ + char temp[11]; + memcpy( temp, &nmeaString[12], 10 ); + temp[10] = '\0'; + return atof(temp); +} + +int getLatDeg(){ + char temp[3]; + memcpy( temp, &nmeaString[12], 2 ); + temp[2] = '\0'; + return atoi(temp); +} + +float getLatMin(){ + char temp[9]; + memcpy( temp, &nmeaString[14], 8 ); + temp[8] = '\0'; + return atof(temp); +} + +float getLon(){ + char temp[12]; + memcpy( temp, &nmeaString[25], 11 ); + temp[11] = '\0'; + return atof(temp); +} + +int getLonDeg(){ + char temp[4]; + memcpy( temp, &nmeaString[25], 3 ); + temp[3] = '\0'; + return atoi(temp); +} + +float getLonMin(){ + char temp[9]; + memcpy( temp, &nmeaString[28], 8 ); + temp[8] = '\0'; + return atof(temp); +} + +float getKnots(){ + char temp[6]; + memcpy( temp, &nmeaString[39], 5 ); + temp[5] = '\0'; + return atof(temp); +} + +float getCourse(){ + char temp[7]; + memcpy( temp, &nmeaString[45], 6 ); + temp[6] = '\0'; + return atof(temp); +} +bool isCoursePresent(){ + if(nmeaString[12] == ',') + return false; + else if(charLastIndexOf(nmeaString,',')>53) + return false; + else + return true; +} + +long getDate(){ + char date[7]; + if(isCoursePresent()){ + memcpy( date, &nmeaString[52], 4 ); + date[4] = '\0'; + return atol(date)*100+14; + } + else{ + if(nmeaString[12] == ',') + memcpy( date, &nmeaString[18], 6 ); + else + memcpy( date, &nmeaString[46], 6 ); + date[6] = '\0'; + return atol(date); + } +} + + +int getDay(){ + char date[3]; + if(isCoursePresent()) + memcpy( date, &nmeaString[52], 2 ); + else{ + if(nmeaString[12] == ',') + memcpy( date, &nmeaString[18], 2 ); + else + memcpy( date, &nmeaString[46], 2 ); + } + date[2] = '\0'; + return atoi(date); +} +int getMonth(){ + char date[3]; + if(isCoursePresent()) + memcpy( date, &nmeaString[54], 2 ); + else{ + if(nmeaString[12] == ',') + memcpy( date, &nmeaString[20], 2 ); + else + memcpy( date, &nmeaString[48], 2 ); + } + date[2] = '\0'; + return atoi(date); +} +int getYear(){ + if(isCoursePresent()) + return 14; //just assume the year hasn't changed - we could also save it when we have it, but that would take more ram + else{ + char date[3]; + if(nmeaString[12] == ',') + memcpy( date, &nmeaString[22], 2 ); + else + memcpy( date, &nmeaString[50], 2 ); + date[2] = '\0'; + return atoi(date); + } + +} + +int getFullYear(){ + if(isCoursePresent()) + return 2014; //just assume the year hasn't changed - we could also save it when we have it, but that would take more ram + else{ + char date[3]; + if(nmeaString[12] == ',') + memcpy( date, &nmeaString[22], 2 ); + else + memcpy( date, &nmeaString[50], 2 ); + date[2] = '\0'; + return atoi(date)+2000; + } +} + + +char getNS(){ + return nmeaString[23]; +} + +char getEW(){ + return nmeaString[37]; +} + + diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/Infrared/Infrared.ino b/hardware/digistump/avr/libraries/Digispark_Examples/Infrared/Infrared.ino new file mode 100644 index 0000000..dce7edc --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/Infrared/Infrared.ino @@ -0,0 +1,27 @@ +int irPin=2; + +void setup() +{ + pinMode(irPin,INPUT); + pinMode(0,OUTPUT); + //Serial.begin(9600); + digitalWrite(0,HIGH); + //Serial.println("You pressed a button"); + delay(1000); + digitalWrite(0,LOW); +} + +void loop() +{ + + if(pulseIn(irPin,LOW)) + { + //button pressed + delay(100); + digitalWrite(0,HIGH); + //Serial.println("You pressed a button"); + delay(1000); + digitalWrite(0,LOW); + } + +} diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/MotorShield/MotorShield.ino b/hardware/digistump/avr/libraries/Digispark_Examples/MotorShield/MotorShield.ino new file mode 100644 index 0000000..6eeba6e --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/MotorShield/MotorShield.ino @@ -0,0 +1,50 @@ +/* + + This example code is in the public domain. + */ + +int MotorADir = 2; +int MotorASpeed = 0; +int MotorBDir = 5; +int MotorBSpeed = 1; + +// the setup routine runs once when you press reset: +void setup() { + // initialize the outputs. + pinMode(MotorADir, OUTPUT); + pinMode(MotorASpeed, OUTPUT); + pinMode(MotorBDir, OUTPUT); + pinMode(MotorBSpeed, OUTPUT); +} + +// the loop routine runs over and over again forever: +void loop() { + //both motors forward full speed + digitalWrite(MotorADir, HIGH); //forward + digitalWrite(MotorBDir, HIGH); + analogWrite(MotorASpeed, 255); //full speed + analogWrite(MotorBSpeed, 255); + delay(5000); // wait for 5 seconds + //turn in place (if using a skid steer configuration) + digitalWrite(MotorADir, HIGH); //forward + digitalWrite(MotorBDir, HIGH); + analogWrite(MotorASpeed, 255); + analogWrite(MotorBSpeed, 0); //off + delay(5000); // wait for 5 seconds + //turn gradually - the other direction (if using a skid steer configuration) + digitalWrite(MotorADir, HIGH); //forward + digitalWrite(MotorBDir, HIGH); + analogWrite(MotorASpeed, 100); + analogWrite(MotorBSpeed, 255); + delay(5000); // wait for 5 seconds + //stop + digitalWrite(MotorADir, HIGH); //forward + digitalWrite(MotorBDir, HIGH); + analogWrite(MotorASpeed, 0); + analogWrite(MotorBSpeed, 0); //off + //reverse slowly + digitalWrite(MotorADir, LOW); //reverse + digitalWrite(MotorBDir, LOW); + analogWrite(MotorASpeed, 100); + analogWrite(MotorBSpeed, 100); +} diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/Rfm12b/Rfm12b.ino b/hardware/digistump/avr/libraries/Digispark_Examples/Rfm12b/Rfm12b.ino new file mode 100644 index 0000000..d82fe29 --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/Rfm12b/Rfm12b.ino @@ -0,0 +1,297 @@ +// This sketch will send a RFM12b packet that is compatible with the Jeelib and can be picked up by a JeeNode running RFM12 demo sketch +//See http://jeelabs.org/2011/06/09/rf12-packet-format-and-design/ +//for packet design + +#define GROUP 212 +#define HEADER 17 +//433mhz = 1, 868mhz = 2, 915mhz = 3 +#define RF12_FREQ 1 + + +#define RF12_NOT_CS() PORTB |= _BV(PB3) +#define RF12_CS() PORTB &= ~_BV(PB3) +#define MOSI_LOW() PORTB &= ~_BV(PB1) +#define MISO_LEVEL() (PINB & _BV(PB0)) +#define RF12_TRANSMIT 0xB8 + +union +{ + unsigned char byte; + struct + { +char ATS_RSSI: + 1; //ATS=Antenna tuning circuit detected strong enough RF signal + //RSSI=The strength of the incoming signal is above the pre-programmed limit +char FFEM: + 1; //FIFO is empty +char LBD: + 1; //Low battery detect, the power supply voltage is below the pre-programmed limit +char EXT: + 1; //Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Read Command) +char WKUP: + 1; //Wake-up timer overflow (Cleared after Status Read Command ) +char RGUR_FFOV: + 1; //RGUR=TX register under run, register over write (Cleared after Status Read Command ) + //FFOV=RX FIFO overflow (Cleared after Status Read Command ) +char POR: + 1; //Power-on reset (Cleared after Status Read Command ) +char RGIT_FFIT: + 1; //RGIT=TX register is ready to receive the next byte + //(Can be cleared by Transmitter Register Write Command) + //FFIT=The number of data bits in the RX FIFO has reached the pre-programmed limit + //(Can be cleared by any of the FIFO read methods) + }bits; +} status_H; + +union +{ + unsigned char byte; + struct + { +char OFFS: + 4; //Offset value to be added to the value of the frequency control parameter (Four LSB bits) +char OFFS6: + 1; //MSB of the measured frequency offset (sign of the offset value) +char ATGL: + 1; //Toggling in each AFC cycle +char CRL: + 1; //Clock recovery locked +char DQD: + 1; //Data quality detector output + }bits; +} status_L; + + +void setup(){ +DDRB = _BV(PB1) | _BV(PB2) | _BV(PB3) | _BV(PB4); +// MOSI, SCK, SEL +PORTB = _BV(PB3); // deselect RFM12 +rf12_init(); +} + +//Some extremely dummy packet payload, just to show it works.. +uint8_t data[] = { "TEST" }; + +void loop(){ + + rf12_cmd(0x82,0x38); //Enable transciever + rf12_send((uint8_t *)&data, sizeof(data)); + //wait till the next-to-last byte is sent (the last is the dummy) + while (!rf12_read_status_MSB()); + rf12_cmd(0x82,0x08); //Disable transciever + delay(3000); +} + + +static void spi_run_clock () { + USICR = _BV(USIWM0) | _BV(USITC); + USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK); + USICR = _BV(USIWM0) | _BV(USITC); + USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK); + USICR = _BV(USIWM0) | _BV(USITC); + USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK); + USICR = _BV(USIWM0) | _BV(USITC); + USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK); + USICR = _BV(USIWM0) | _BV(USITC); + USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK); + USICR = _BV(USIWM0) | _BV(USITC); + USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK); + USICR = _BV(USIWM0) | _BV(USITC); + USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK); + USICR = _BV(USIWM0) | _BV(USITC); + USICR = _BV(USIWM0) | _BV(USITC) | _BV(USICLK); +} + +void rf12_cmd(uint8_t highbyte, uint8_t lowbyte) +{ + RF12_CS(); + USIDR = highbyte; + spi_run_clock(); + USIDR = lowbyte; + spi_run_clock(); + RF12_NOT_CS(); +} + +void rf12_loop_until_FFIT_RGIT(void) +{ + do + { + rf12_read_status_MSB(); + } + while (!status_H.bits.RGIT_FFIT); +} + +/* rf12_read_status_MSB + RX Mode: FFIT = The number of data bits in the RX FIFO has reached the pre-programmed limit. + Can be cleared by any of the FIFO read methods + TX Mode: RGIT = TX register is ready to receive the next byte + (Can be cleared by Transmitter Register Write Command) +*/ +uint8_t rf12_read_status_MSB(void) +{ + RF12_CS(); + MOSI_LOW(); + asm volatile("nop"); + if (MISO_LEVEL()) + status_H.bits.RGIT_FFIT=1; + else + status_H.bits.RGIT_FFIT=0; + RF12_NOT_CS(); + return status_H.bits.RGIT_FFIT; +} + +void rf12_read_status(void) +{ + RF12_CS(); + USIDR = 0x00; //Status Read Command + spi_run_clock(); + status_H.byte = USIDR; + USIDR = 0x00; //Status Read Command + spi_run_clock(); + status_L.byte = USIDR; + RF12_NOT_CS(); +} + +void rf12_TX(uint8_t aByte) +{ + //FFIT wird gepollt um zu erkennen ob das FIFO TX + //Register bereit ist. + //Alternativ ist es auch möglich(wenn verbunden) + //den Interrupt Ausgang des RF12 zu pollen: while(INT1_LEVEL()); + while (!rf12_read_status_MSB()); + rf12_cmd(RF12_TRANSMIT,aByte); +} + + +#if RF12_RECEIVE_CODE +uint8_t rf12_RX(void) +{ + rf12_loop_until_FFIT_RGIT(); + RF12_CS(); + USIDR = 0xB0; + spi_run_clock(); + USIDR = 0x00; + spi_run_clock(); + RF12_NOT_CS(); + return USIDR; +} +#endif + +static __inline__ uint16_t _crc16_update(uint16_t __crc, uint8_t __data) +{ + uint8_t __tmp; + uint16_t __ret; + + __asm__ __volatile__ ( + "eor %A0,%2" "\n\t" + "mov %1,%A0" "\n\t" + "swap %1" "\n\t" + "eor %1,%A0" "\n\t" + "mov __tmp_reg__,%1" "\n\t" + "lsr %1" "\n\t" + "lsr %1" "\n\t" + "eor %1,__tmp_reg__" "\n\t" + "mov __tmp_reg__,%1" "\n\t" + "lsr %1" "\n\t" + "eor %1,__tmp_reg__" "\n\t" + "andi %1,0x07" "\n\t" + "mov __tmp_reg__,%A0" "\n\t" + "mov %A0,%B0" "\n\t" + "lsr %1" "\n\t" + "ror __tmp_reg__" "\n\t" + "ror %1" "\n\t" + "mov %B0,__tmp_reg__" "\n\t" + "eor %A0,%1" "\n\t" + "lsr __tmp_reg__" "\n\t" + "ror %1" "\n\t" + "eor %B0,__tmp_reg__" "\n\t" + "eor %A0,%1" + : "=r" (__ret), "=d" (__tmp) + : "r" (__data), "0" (__crc) + : "r0" + ); + return __ret; +} + + +void rf12_send(const uint8_t* buf, uint8_t cnt) +{ + if (!cnt) return; + uint16_t chksum=~0; + +//See http://jeelabs.org/2011/06/09/rf12-packet-format-and-design/ +//http://jeelabs.org/2010/12/07/binary-packet-decoding/ + + rf12_TX(0xAA); //PREAMBLE + rf12_TX(0xAA); //PREAMBLE + rf12_TX(0xAA); //PREAMBLE + rf12_TX(0x2D); //SYNC HI BYTE +rf12_TX(GROUP); //SYNC LOW BYTE (group 210) +chksum = _crc16_update(chksum, GROUP); + rf12_TX(HEADER); // Header byte + chksum = _crc16_update(chksum, HEADER); + rf12_TX(cnt); + chksum = _crc16_update(chksum, cnt); + while (cnt--) + { + rf12_TX(*buf); + chksum = _crc16_update(chksum,*buf++); + } + rf12_TX(chksum); + rf12_TX(chksum>>8); + rf12_TX(0xAA); //dummy byte +} + +#if RF12_RECEIVE_CODE +//returns 0 if no data is available +//returns -1(255) if there is a CRC Error +//else, returns number of received byte +uint8_t rf12_read(uint8_t* buf, const uint8_t max) +{ + uint16_t checksum=~0; + uint16_t received_checksum; + + uint8_t hdr; + hdr=rf12_RX(); + checksum = _crc16_update(checksum,hdr); + + uint8_t len; + len=rf12_RX(); + checksum = _crc16_update(checksum,len); + + uint8_t i=len; + while (i--) + { + *buf=rf12_RX(); + checksum = _crc16_update(checksum,*buf++); + } + received_checksum=rf12_RX(); + received_checksum=received_checksum<<8; + received_checksum |= rf12_RX(); + + if (received_checksum==checksum) + return len; + else + return -1; +} +#endif + + +void rf12_init(void) +{ + USICR = _BV(USIWM0); // 3-wire, software clock strobe + rf12_cmd(0x80, 0xC7 | (RF12_868MHZ << 4)); // EL (ena TX), EF (ena RX FIFO), 12.0pF + rf12_cmd(0xA6,0x40); // 868MHz + rf12_cmd(0xC6,0x06); // approx 49.2 Kbps, i.e. 10000/29/(1+6) Kbps + rf12_cmd(0x94,0xA2); // VDI,FAST,134kHz,0dBm,-91dBm + rf12_cmd(0xC2,0xAC); // AL,!ml,DIG,DQD4 + rf12_cmd(0xCA,0x83); // FIFO8,2-SYNC,!ff,DR + rf12_cmd(0xCE,0x00 | GROUP); // SYNC=2DXXï¼› + rf12_cmd(0xC4,0x83); // @PWR,NO RSTRIC,!st,!fi,OE,EN + rf12_cmd(0x98,0x50); // !mp,90kHz,MAX OUT + rf12_cmd(0xCC,0x77); // OB1，OB0, LPX,ï¼ddy，DDIT，BW0 + rf12_cmd(0xE0,0x00); // NOT USE + rf12_cmd(0xC8,0x00); // NOT USE + rf12_cmd(0xC0,0x40); // 1.66MHz,2.2V + +} diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/Start/Start.ino b/hardware/digistump/avr/libraries/Digispark_Examples/Start/Start.ino new file mode 100644 index 0000000..e535cfa --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/Start/Start.ino @@ -0,0 +1,17 @@ + +// the setup routine runs once when you press reset: +void setup() { + // initialize the digital pin as an output. + pinMode(0, OUTPUT); //LED on Model B + pinMode(1, OUTPUT); //LED on Model A or Pro +} + +// the loop routine runs over and over again forever: +void loop() { + digitalWrite(0, HIGH); // turn the LED on (HIGH is the voltage level) + digitalWrite(1, HIGH); + delay(1000); // wait for a second + digitalWrite(0, LOW); // turn the LED off by making the voltage LOW + digitalWrite(1, LOW); + delay(1000); // wait for a second +} diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/WiFiClientGetExample/WiFiClientGetExample.ino b/hardware/digistump/avr/libraries/Digispark_Examples/WiFiClientGetExample/WiFiClientGetExample.ino new file mode 100644 index 0000000..b9cd865 --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/WiFiClientGetExample/WiFiClientGetExample.ino @@ -0,0 +1,118 @@ +#include +void setup() { + // put your setup code here, to run once: + wifiDelay(10000); //wait a good amount of time for moduel to connect to wifi - this script assumes it can connect and doesn't check + Serial.begin(9600); + + /*========================================================== + = NOTE: This assumes you have used the wifi module = + = web interface to set it up as a client and 9600 baud = + = See the wifi shield page for more info. = + = = + = NOTE YOU MAY NEED TO CHANGE THE begin STATEMENT AND = + = THE MODULED TO 4800 baud IF YOU EXPERIENCE SCRAMBLED = + = OUTPUT = + = = + = If not useing DigiKeyboard change wifiDelay as noted = + ==========================================================*/ + + if(wifiConnect(F("digistump.com"))){ //host wrapped in F() to save ram + + if(wifiSendGet(F("digistump.com"),F("/test.txt"))){ //host and path wrapped in F() to save ram + + //uncomment one of the three test methods below to try one out, only one will work at a time + + //YOU CAN READ IT OUT ONE CHAR AT A TIME AND PRINT IT + while(!Serial.available()){wifiDelay(10);} //wait for some data + while(Serial.available()){ //as long as there is data read it and do something with it + DigiKeyboard.write(Serial.read()); //in this case we just type it out + } + + + /* + //OR YOU CAN FIND SOMETHING AND THEN READ AFTER THAT + //try this with ip.jsontest.com + //See also: Serial.findUntil, Serial.readBytesUntil, Serial.readStringUntil, Serial.find, etc + Serial.find(": \""); //find the start of where the ip is shown + String ip = Serial.readStringUntil('"'); //read until the end of the ip which is the " + DigiKeyboard.print(ip); //type it out for the demo + */ + + /* + //OR YOU CAN GRAB IT ALL AT ONCE + //ASSUMING THE BODY ISN'T LARGER THAN AVAILABLE RAME + String body = Serial.readString(); //read it all to a string + DigiKeyboard.print(body.trim()); //type it out for the demo - but first trim the whitespace off the start and end + */ + } + else{ + //we didn't get a response to our GET - something failed + DigiKeyboard.write('1'); + } + + } + else{ + //we couldn't talk to the wifi module properly - see wifiConnect for possible break points + DigiKeyboard.write('2'); + } +} + + + + + +void loop() { + // put your main code here, to run repeatedly: + +} + +void wifiDelay(long time){ + /* + If you are not using DigiKeyboard in you sketch + change this by commenting out the DigiKeyboard delay and + uncommenting the regular delay + Also remove the DigiKeyboard.h include at the top + Note: This sketch will not run with DigiKeyboard in use + unless connected to a computer + */ + DigiKeyboard.delay(time); + //delay(time); +} + + +bool wifiConnect(String host){ + wifiDelay(50); + Serial.write("+++"); + if (!Serial.find("a")) return false; //error in entering AT mode - try restoring module and then setting settings again + Serial.write("a"); + if (!wifiWaitForOK()) return false; //error in entering AT mode + Serial.print(F("AT+NETP=TCP,CLIENT,80,")); + Serial.print(host); + Serial.print(F("\r")); + if (!wifiWaitForOK()) return false; //error in setting host + Serial.print(F("AT+ENTM\r")); + if (!wifiWaitForOK()) return false; //error in going back to transparent mode + wifiDelay(1000); //instead of calling TCPLK to check for a link we just wait a good amount of time for a link, because TCPLK can be buggy + while(Serial.read()!=-1); //empty the read buffer so we are ready for a clean GET OR POST + return true; +} + +bool wifiWaitForOK(){ + return Serial.find("k"); +} + +bool wifiSendGet(String host, String path){ + Serial.print(F("GET ")); + Serial.print(path); + Serial.println(F(" HTTP/1.1")); + Serial.print(F("Host: ")); + Serial.println(host); + Serial.println(F("Cache-Control: no-cache")); + Serial.println(); + Serial.setTimeout(5000); + if(!Serial.find("\r\n\r")) //skip the header - if this fail then the GET probably did too + return false; + Serial.setTimeout(1000); + return true; +} + diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/WiFiClientPostExample/WiFiClientPostExample.ino b/hardware/digistump/avr/libraries/Digispark_Examples/WiFiClientPostExample/WiFiClientPostExample.ino new file mode 100644 index 0000000..56812fc --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/WiFiClientPostExample/WiFiClientPostExample.ino @@ -0,0 +1,127 @@ +#include +void setup() { + // put your setup code here, to run once: + wifiDelay(10000); //wait a good amount of time for moduel to connect to wifi - this script assumes it can connect and doesn't check + Serial.begin(600); + + /*========================================================== + = NOTE: This assumes you have used the wifi module = + = web interface to set it up as a client and 600 baud = + = See the wifi shield page for more info. = + = = + = NOTE YOU MAY NEED TO CHANGE THE begin STATEMENT AND = + = THE MODULE TO A LOWER BAUD IF YOU EXPERIENCE SCRAMBLED= + = OUTPUT - see notes in the wiki on how to set these = + = = + = If not useing DigiKeyboard change wifiDelay as noted = + ==========================================================*/ + + if(wifiConnect(F("requestb.in"))){ //host wrapped in F() to save ram + + if(wifiSendPost(F("requestb.in"),F("/12tefnq1"),F("test=test123"))){ //host and path and parameters wrapped in F() to save ram + + //uncomment one of the three test methods below to try one out, only one will work at a time + //you could also just ignore all of this - we know we got headers back so we're probably good and out data was sent + //TODO: read the status code to be sure + + /* + //YOU CAN READ IT OUT ONE CHAR AT A TIME AND PRINT IT + while(!Serial.available()){wifiDelay(10);} //wait for some data + while(Serial.available()){ //as long as there is data read it and do something with it + DigiKeyboard.write(Serial.read()); //in this case we just type it out + } + */ + + /* + //OR YOU CAN FIND SOMETHING AND THEN READ AFTER THAT + //try this with ip.jsontest.com + //See also: Serial.findUntil, Serial.readBytesUntil, Serial.readStringUntil, Serial.find, etc + Serial.find(": \""); //find the start of where the ip is shown + String ip = Serial.readStringUntil('"'); //read until the end of the ip which is the " + DigiKeyboard.print(ip); //type it out for the demo + */ + + /* + //OR YOU CAN GRAB IT ALL AT ONCE + //ASSUMING THE BODY ISN'T LARGER THAN AVAILABLE RAME + String body = Serial.readString(); //read it all to a string + DigiKeyboard.print(body.trim()); //type it out for the demo - but first trim the whitespace off the start and end + */ + } + else{ + //we didn't get a response to our GET - something failed + DigiKeyboard.write('1'); + } + + } + else{ + //we couldn't talk to the wifi module properly - see wifiConnect for possible break points + DigiKeyboard.write('2'); + } +} + + + + + +void loop() { + // put your main code here, to run repeatedly: + +} + +void wifiDelay(long time){ + /* + If you are not using DigiKeyboard in you sketch + change this by commenting out the DigiKeyboard delay and + uncommenting the regular delay + Also remove the DigiKeyboard.h include at the top + Note: This sketch will not run with DigiKeyboard in use + unless connected to a computer + */ + DigiKeyboard.delay(time); + //delay(time); +} + + +bool wifiConnect(String host){ + wifiDelay(50); + Serial.write("+++"); + if (!Serial.find("a")) return false; //error in entering AT mode - try restoring module and then setting settings again + Serial.write("a"); + if (!wifiWaitForOK()) return false; //error in entering AT mode + Serial.print(F("AT+NETP=TCP,CLIENT,80,")); + Serial.print(host); + Serial.print(F("\r")); + if (!wifiWaitForOK()) return false; //error in setting host + Serial.print(F("AT+ENTM\r")); + if (!wifiWaitForOK()) return false; //error in going back to transparent mode + wifiDelay(1000); //instead of calling TCPLK to check for a link we just wait a good amount of time for a link, because TCPLK can be buggy + while(Serial.read()!=-1); //empty the read buffer so we are ready for a clean GET OR POST + return true; +} + +bool wifiWaitForOK(){ + return Serial.find("k"); +} + + +bool wifiSendPost(String host, String path, String data){ + Serial.print(F("POST ")); + Serial.print(path); + Serial.println(F(" HTTP/1.1")); + Serial.print(F("Host: ")); + Serial.println(host); + Serial.println(F("Content-Type: application/x-www-form-urlencoded")); + Serial.print(F("Content-Length: ")); + Serial.println(data.length()); + Serial.println(); + Serial.println(data); + Serial.println(); + Serial.setTimeout(5000); + if(!Serial.find("\r\n\r")) //skip the header - if this fail then the GET probably did too + return false; + Serial.setTimeout(1000); + return true; +} + + diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/WiFiServerExample/WiFiServerExample.ino b/hardware/digistump/avr/libraries/Digispark_Examples/WiFiServerExample/WiFiServerExample.ino new file mode 100644 index 0000000..96106d1 --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/WiFiServerExample/WiFiServerExample.ino @@ -0,0 +1,83 @@ +void setup() { + // put your setup code here, to run once: + pinMode(1,OUTPUT); //use onboard LED as output + delay(10000);//wait for wifi to connect + Serial.begin(9600); //open connection to wifi module +/*========================================================== + = NOTE: This assumes you have used the wifi module = + = web interface to set it up as a server and 9600 baud = + = See the wifi shield page for more info. = + ========================================================== + + Goto: http://[WIFI IP ADDRESS]:[WIFI SERVER PORT]/ to see the response + ie. http://192.168.0.123:8899/ + +*/ +} + + +void loop() { + + if(serverRequest()){ + //new request + //find the path requested + String path = getRequestPath(); + + //route based on path + + ///wrap responses and other strings in F() to save ram + + if(path == F("/on")){ + digitalWrite(1,HIGH); + sendResponse(F("LED ON
LED OFF")); + } + else if(path == F("/off")){ + digitalWrite(1,LOW); + sendResponse(F("LED OFF
LED ON")); + } + else{ + sendResponse(F("WELCOME
LED ON
LED OFF")); + } + } + + +} + +bool serverRequest(){ + if(Serial.available()>4){ + return Serial.find("GET "); + } + return false; +} + +String getRequestPath(){ + String path = Serial.readStringUntil(' '); + while(Serial.read() != -1); //clear read buffer + return path; +} +void sendResponse(String response){ + sendResponseStart(); + sendResponseChunk(response); + sendResponseEnd(); +} + + +void sendResponseStart(){ + //sends a chunked response + Serial.println(F("HTTP/1.1 200 OK")); + Serial.println(F("Content-Type: text/html")); + Serial.println(F("Connection: close")); + Serial.println(F("Transfer-Encoding: chunked")); + Serial.println(); +} +void sendResponseChunk(String response){ + + Serial.println(response.length()+2,HEX); + Serial.println(response); + Serial.println(); + +} +void sendResponseEnd(){ + Serial.println(F("0")); + Serial.println(); +} diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/WiFiServerRobot/WiFiServerRobot.ino b/hardware/digistump/avr/libraries/Digispark_Examples/WiFiServerRobot/WiFiServerRobot.ino new file mode 100644 index 0000000..9b70d20 --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/WiFiServerRobot/WiFiServerRobot.ino @@ -0,0 +1,166 @@ +void setup() { + // put your setup code here, to run once: + delay(10000);//wait for wifi to connect + Serial.begin(9600); //open connection to wifi module +/*========================================================== + = NOTE: This assumes you have used the wifi module = + = web interface to set it up as a server and 9600 baud = + = See the wifi shield page for more info. = + ========================================================== + + Goto: http://[WIFI IP ADDRESS]:[WIFI SERVER PORT]/forward to make the bot go forward + ie. http://192.168.0.123:8899/forward + change the forward to back, right, left, or stop to do those things instead +*/ + botInit(); //setup the pins for the bot + +} + + +void loop() { + + if(serverRequest()){ + //new request + //find the path requested + String path = getRequestPath(); + + //route based on path + + ///wrap responses and other strings in F() to save ram + + if(path == F("/forward")){ + botForward(255); + sendOK(); + } + else if(path == F("/back")){ + botReverse(255); + sendOK(); + } + else if(path == F("/right")){ + botRight(255); + sendOK(); + } + else if(path == F("/left")){ + botLeft(255); + sendOK(); + } + else if(path == F("/stop")){ + botStop(); + sendOK(); + } + else{ + //it doesn't like sending big responses as one chunk - so you can use these functions to break it up + sendResponseStart(); + sendResponseChunk(F("BOTLY - your RESTful Bot!")); + sendResponseChunk(F("
Forward")); + sendResponseChunk(F("
Back")); + sendResponseChunk(F("
Right")); + sendResponseChunk(F("
Left")); + sendResponseChunk(F("
Stop")); + sendResponseEnd(); + } + } + + +} + +void sendOK(){ + sendResponse(F("OK")); +} +void botForward(int botSpeed){ + digitalWrite(2,HIGH); + digitalWrite(5,HIGH); + analogWrite(0,botSpeed); + analogWrite(1,botSpeed); +} + +void botReverse(int botSpeed){ + digitalWrite(2,LOW); + digitalWrite(5,LOW); + analogWrite(0,botSpeed); + analogWrite(1,botSpeed); +} + +void botRight(int botSpeed){ + digitalWrite(2,HIGH); + digitalWrite(5,LOW); + analogWrite(0,botSpeed); + analogWrite(1,0); +} + +void botHardRight(int botSpeed){ + digitalWrite(2,HIGH); + digitalWrite(5,LOW); + analogWrite(0,botSpeed); + analogWrite(1,botSpeed); +} + +void botLeft(int botSpeed){ + digitalWrite(2,LOW); + digitalWrite(5,HIGH); + analogWrite(0,0); + analogWrite(1,botSpeed); +} + +void botHardLeft(int botSpeed){ + digitalWrite(2,LOW); + digitalWrite(5,HIGH); + analogWrite(0,botSpeed); + analogWrite(1,botSpeed); +} + +void botStop(){ + digitalWrite(2,LOW); + digitalWrite(5,LOW); + analogWrite(0,0); + analogWrite(1,0); +} + +void botInit(){ + pinMode(0,OUTPUT); + pinMode(1,OUTPUT); + pinMode(2,OUTPUT); + pinMode(5,OUTPUT); +} + + +bool serverRequest(){ + if(Serial.available()>4){ + return Serial.find("GET "); + } + return false; +} + +String getRequestPath(){ + String path = Serial.readStringUntil(' '); + while(Serial.read() != -1); //clear read buffer + return path; +} + +void sendResponse(String response){ + sendResponseStart(); + sendResponseChunk(response); + sendResponseEnd(); +} + + +void sendResponseStart(){ + //sends a chunked response + Serial.println(F("HTTP/1.1 200 OK")); + Serial.println(F("Content-Type: text/html")); + Serial.println(F("Connection: close")); + Serial.println(F("Transfer-Encoding: chunked")); + Serial.println(); +} +void sendResponseChunk(String response){ + + Serial.println(response.length()+2,HEX); + Serial.println(response); + Serial.println(); + +} +void sendResponseEnd(){ + Serial.println(F("0")); + Serial.println(); +} + diff --git a/hardware/digistump/avr/libraries/Digispark_Examples/i2cScanner/i2cScanner.ino b/hardware/digistump/avr/libraries/Digispark_Examples/i2cScanner/i2cScanner.ino new file mode 100644 index 0000000..5d8d918 --- /dev/null +++ b/hardware/digistump/avr/libraries/Digispark_Examples/i2cScanner/i2cScanner.ino @@ -0,0 +1,83 @@ +// -------------------------------------- +// i2c_scanner +// +// Version 1 +// This program (or code that looks like it) +// can be found in many places. +// For example on the Arduino.cc forum. +// The original author is not know. +// Version 2, Juni 2012, Using Arduino 1.0.1 +// Adapted to be as simple as possible by Arduino.cc user Krodal +// Version 3, Feb 26 2013 +// V3 by louarnold +// Version 4, March 3, 2013, Using Arduino 1.0.3 +// by Arduino.cc user Krodal. +// Changes by louarnold removed. +// Scanning addresses changed from 0...127 to 1...119, +// according to the i2c scanner by Nick Gammon +// http://www.gammon.com.au/forum/?id=10896 +// Version 5, March 28, 2013 +// As version 4, but address scans now to 127. +// A sensor seems to use address 120. +// +// +// This sketch tests the standard 7-bit addresses +// Devices with higher bit address might not be seen properly. +// + +#include +#include + +void setup() +{ + + Wire.begin(); + DigiKeyboard.delay(3000); + + DigiKeyboard.println("\nI2C Scanner"); +} + + +void loop() +{ + byte error, address; + int nDevices; + + DigiKeyboard.println("Scanning..."); + + nDevices = 0; + for (address = 1; address < 127; address++ ) + { + // The i2c_scanner uses the return value of + // the Write.endTransmisstion to see if + // a device did acknowledge to the address. + Wire.beginTransmission(address); + error = Wire.endTransmission(); + + if (error == 0) + { + DigiKeyboard.print("I2C device found at address 0x"); + if (address < 16) + DigiKeyboard.print("0"); + DigiKeyboard.print(address, HEX); + DigiKeyboard.println(" !"); + + nDevices++; + } + else if (error == 4) + { + DigiKeyboard.print("Unknow error at address 0x"); + if (address < 16) + DigiKeyboard.print("0"); + DigiKeyboard.println(address, HEX); + } + } + if (nDevices == 0) + DigiKeyboard.println("No I2C devices found\n"); + else + DigiKeyboard.println("done\n"); + + DigiKeyboard.delay(5000); // wait 5 seconds for next scan +} + + diff --git a/hardware/digistump/avr/libraries/LPD8806/LPD8806.cpp b/hardware/digistump/avr/libraries/LPD8806/LPD8806.cpp new file mode 100644 index 0000000..2588ecb --- /dev/null +++ b/hardware/digistump/avr/libraries/LPD8806/LPD8806.cpp @@ -0,0 +1,124 @@ +#include "LPD8806.h" + +// Arduino library to control LPD8806-based RGB LED Strips +// (c) Adafruit industries +// MIT license + +/*****************************************************************************/ + +// Constructor for use with arbitrary clock/data pins: +LPD8806::LPD8806(uint16_t n, uint8_t dpin, uint8_t cpin) { + pixels = NULL; + begun = false; + updateLength(n); + updatePins(dpin, cpin); +} + +// Activate hard/soft SPI as appropriate: +void LPD8806::begin(void) { + startBitbang(); + begun = true; +} + +// Change pin assignments post-constructor, using arbitrary pins: +void LPD8806::updatePins(uint8_t dpin, uint8_t cpin) { + datapin = dpin; + clkpin = cpin; + clkport = portOutputRegister(digitalPinToPort(cpin)); + clkpinmask = digitalPinToBitMask(cpin); + dataport = portOutputRegister(digitalPinToPort(dpin)); + datapinmask = digitalPinToBitMask(dpin); + + if(begun == true) { // If begin() was previously invoked... + startBitbang(); // Regardless, now enable 'soft' SPI outputs + } // Otherwise, pins are not set to outputs until begin() is called. + + // Note: any prior clock/data pin directions are left as-is and are + // NOT restored as inputs! + + hardwareSPI = false; +} + +// Enable software SPI pins and issue initial latch: +void LPD8806::startBitbang() { + pinMode(datapin, OUTPUT); + pinMode(clkpin , OUTPUT); + *dataport &= ~datapinmask; // Data is held low throughout (latch = 0) + for(uint8_t i = 8; i>0; i--) { + *clkport |= clkpinmask; + *clkport &= ~clkpinmask; + } +} + +// Change strip length (see notes with empty constructor, above): +void LPD8806::updateLength(uint16_t n) { + if(pixels != NULL) free(pixels); // Free existing data (if any) + numLEDs = n; + n *= 3; // 3 bytes per pixel + if(NULL != (pixels = (uint8_t *)malloc(n + 1))) { // Alloc new data + memset(pixels, 0x80, n); // Init to RGB 'off' state + pixels[n] = 0; // Last byte is always zero for latch + } else numLEDs = 0; // else malloc failed + // 'begun' state does not change -- pins retain prior modes +} + +uint16_t LPD8806::numPixels(void) { + return numLEDs; +} + +// This is how data is pushed to the strip. Unfortunately, the company +// that makes the chip didnt release the protocol document or you need +// to sign an NDA or something stupid like that, but we reverse engineered +// this from a strip controller and it seems to work very nicely! +void LPD8806::show(void) { + uint16_t i, n3 = numLEDs * 3 + 1; // 3 bytes per LED + 1 for latch + + // write 24 bits per pixel + + for (i=0; i>= 1) { + if(pixels[i] & bit) *dataport |= datapinmask; + else *dataport &= ~datapinmask; + *clkport |= clkpinmask; + *clkport &= ~clkpinmask; + } + } + +} + +// Convert separate R,G,B into combined 32-bit GRB color: +uint32_t LPD8806::Color(byte r, byte g, byte b) { + return 0x808080 | ((uint32_t)g << 16) | ((uint32_t)r << 8) | (uint32_t)b; +} + +// Set pixel color from separate 7-bit R, G, B components: +void LPD8806::setPixelColor(uint16_t n, uint8_t r, uint8_t g, uint8_t b) { + if(n < numLEDs) { // Arrays are 0-indexed, thus NOT '<=' + uint8_t *p = &pixels[n * 3]; + *p++ = g | 0x80; // LPD8806 color order is GRB, + *p++ = r | 0x80; // not the more common RGB, + *p++ = b | 0x80; // so the order here is intentional; don't "fix" + } +} + +// Set pixel color from 'packed' 32-bit RGB value: +void LPD8806::setPixelColor(uint16_t n, uint32_t c) { + if(n < numLEDs) { // Arrays are 0-indexed, thus NOT '<=' + uint8_t *p = &pixels[n * 3]; + *p++ = (c >> 16) | 0x80; + *p++ = (c >> 8) | 0x80; + *p++ = c | 0x80; + } +} + +// Query color from previously-set pixel (returns packed 32-bit GRB value) +uint32_t LPD8806::getPixelColor(uint16_t n) { + if(n < numLEDs) { + uint16_t ofs = n * 3; + return ((uint32_t)((uint32_t)pixels[ofs ] << 16) | + (uint32_t)((uint32_t)pixels[ofs + 1] << 8) | + (uint32_t)pixels[ofs + 2]) & 0x7f7f7f; + } + + return 0; // Pixel # is out of bounds +} diff --git a/hardware/digistump/avr/libraries/LPD8806/LPD8806.h b/hardware/digistump/avr/libraries/LPD8806/LPD8806.h new file mode 100644 index 0000000..e2ab69e --- /dev/null +++ b/hardware/digistump/avr/libraries/LPD8806/LPD8806.h @@ -0,0 +1,41 @@ +#if (ARDUINO >= 100) + #include +#else + #include + #include +#endif + +class LPD8806 { + + public: + + LPD8806(uint16_t n, uint8_t dpin, uint8_t cpin); // Configurable pins + void + begin(void), + show(void), + setPixelColor(uint16_t n, uint8_t r, uint8_t g, uint8_t b), + setPixelColor(uint16_t n, uint32_t c), + updatePins(uint8_t dpin, uint8_t cpin), // Change pins, configurable + updateLength(uint16_t n); // Change strip length + uint16_t + numPixels(void); + uint32_t + Color(byte, byte, byte), + getPixelColor(uint16_t n); + + private: + + uint16_t + numLEDs; // Number of RGB LEDs in strip + uint8_t + *pixels, // Holds LED color values (3 bytes each) + clkpin , datapin, // Clock & data pin numbers + clkpinmask, datapinmask; // Clock & data PORT bitmasks + volatile uint8_t + *clkport , *dataport; // Clock & data PORT registers + void + startBitbang(void); + boolean + hardwareSPI, // If 'true', using hardware SPI + begun; // If 'true', begin() method was previously invoked +}; diff --git a/hardware/digistump/avr/libraries/LPD8806/README.md b/hardware/digistump/avr/libraries/LPD8806/README.md new file mode 100644 index 0000000..9bcd44b --- /dev/null +++ b/hardware/digistump/avr/libraries/LPD8806/README.md @@ -0,0 +1,18 @@ +# Arduino library for LPD8806 # +This Library was written for the LPD8806 PWM LED driver chips, strips and pixels. +But the LPD8803/LPD8809 will probably work too. + +## Where to Buy? ## +Pick some up at [Adafruit Industries](http://www.adafruit.com/products/306) + +## Download ## +Click the Downloads Tab in the Tabbar above. +Or follow [this](https://github.com/adafruit/LPD8806/zipball/master) link + +## Installation ## +* Uncompress the Downloaded Library +* Rename the uncompressed folder to LPD8806 +* Check that the LPD8806 folder contains LPD8806.cpp and LPD8806.h +* Place the LPD8806 library folder your /libraries/ folder, + if the libraries folder does not exist - create it first! +* Restart the IDE \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/LPD8806/examples/LEDbeltKit/LEDbeltKit.pde b/hardware/digistump/avr/libraries/LPD8806/examples/LEDbeltKit/LEDbeltKit.pde new file mode 100644 index 0000000..3ca0c7b --- /dev/null +++ b/hardware/digistump/avr/libraries/LPD8806/examples/LEDbeltKit/LEDbeltKit.pde @@ -0,0 +1,255 @@ +#include "LPD8806.h" +#include "SPI.h" + +// Example to control LPD8806-based RGB LED Modules in a strip! +/*****************************************************************************/ + +#if defined(USB_SERIAL) || defined(USB_SERIAL_ADAFRUIT) +// this is for teensyduino support +int dataPin = 2; +int clockPin = 1; +#else +// these are the pins we use for the LED belt kit using +// the Leonardo pinouts +int dataPin = 16; +int clockPin = 15; +#endif + +// Set the first variable to the NUMBER of pixels. 32 = 32 pixels in a row +// The LED strips are 32 LEDs per meter but you can extend/cut the strip +LPD8806 strip = LPD8806(32, dataPin, clockPin); + + + +void setup() { + // Start up the LED strip + strip.begin(); + + // Update the strip, to start they are all 'off' + strip.show(); +} + +// function prototypes, do not remove these! +void colorChase(uint32_t c, uint8_t wait); +void colorWipe(uint32_t c, uint8_t wait); +void dither(uint32_t c, uint8_t wait); +void scanner(uint8_t r, uint8_t g, uint8_t b, uint8_t wait); +void wave(uint32_t c, int cycles, uint8_t wait); +void rainbowCycle(uint8_t wait); +uint32_t Wheel(uint16_t WheelPos); + +void loop() { + + // Send a simple pixel chase in... + colorChase(strip.Color(127,127,127), 20); // white + colorChase(strip.Color(127,0,0), 20); // red + colorChase(strip.Color(127,127,0), 20); // yellow + colorChase(strip.Color(0,127,0), 20); // green + colorChase(strip.Color(0,127,127), 20); // cyan + colorChase(strip.Color(0,0,127), 20); // blue + colorChase(strip.Color(127,0,127), 20); // magenta + + // Fill the entire strip with... + colorWipe(strip.Color(127,0,0), 20); // red + colorWipe(strip.Color(0, 127,0), 20); // green + colorWipe(strip.Color(0,0,127), 20); // blue + colorWipe(strip.Color(0,0,0), 20); // black + + // Color sparkles + dither(strip.Color(0,127,127), 50); // cyan, slow + dither(strip.Color(0,0,0), 15); // black, fast + dither(strip.Color(127,0,127), 50); // magenta, slow + dither(strip.Color(0,0,0), 15); // black, fast + dither(strip.Color(127,127,0), 50); // yellow, slow + dither(strip.Color(0,0,0), 15); // black, fast + + // Back-and-forth lights + scanner(127,0,0, 30); // red, slow + scanner(0,0,127, 15); // blue, fast + + // Wavy ripple effects + wave(strip.Color(127,0,0), 4, 20); // candy cane + wave(strip.Color(0,0,100), 2, 40); // icy + + // make a pretty rainbow cycle! + rainbowCycle(0); // make it go through the cycle fairly fast + + // Clear strip data before start of next effect + for (int i=0; i < strip.numPixels(); i++) { + strip.setPixelColor(i, 0); + } +} + +// Cycle through the color wheel, equally spaced around the belt +void rainbowCycle(uint8_t wait) { + uint16_t i, j; + + for (j=0; j < 384 * 5; j++) { // 5 cycles of all 384 colors in the wheel + for (i=0; i < strip.numPixels(); i++) { + // tricky math! we use each pixel as a fraction of the full 384-color + // wheel (thats the i / strip.numPixels() part) + // Then add in j which makes the colors go around per pixel + // the % 384 is to make the wheel cycle around + strip.setPixelColor(i, Wheel(((i * 384 / strip.numPixels()) + j) % 384)); + } + strip.show(); // write all the pixels out + delay(wait); + } +} + +// fill the dots one after the other with said color +// good for testing purposes +void colorWipe(uint32_t c, uint8_t wait) { + int i; + + for (i=0; i < strip.numPixels(); i++) { + strip.setPixelColor(i, c); + strip.show(); + delay(wait); + } +} + +// Chase a dot down the strip +// good for testing purposes +void colorChase(uint32_t c, uint8_t wait) { + int i; + + for (i=0; i < strip.numPixels(); i++) { + strip.setPixelColor(i, 0); // turn all pixels off + } + + for (i=0; i < strip.numPixels(); i++) { + strip.setPixelColor(i, c); // set one pixel + strip.show(); // refresh strip display + delay(wait); // hold image for a moment + strip.setPixelColor(i, 0); // erase pixel (but don't refresh yet) + } + strip.show(); // for last erased pixel +} + +// An "ordered dither" fills every pixel in a sequence that looks +// sparkly and almost random, but actually follows a specific order. +void dither(uint32_t c, uint8_t wait) { + + // Determine highest bit needed to represent pixel index + int hiBit = 0; + int n = strip.numPixels() - 1; + for(int bit=1; bit < 0x8000; bit <<= 1) { + if(n & bit) hiBit = bit; + } + + int bit, reverse; + for(int i=0; i<(hiBit << 1); i++) { + // Reverse the bits in i to create ordered dither: + reverse = 0; + for(bit=1; bit <= hiBit; bit <<= 1) { + reverse <<= 1; + if(i & bit) reverse |= 1; + } + strip.setPixelColor(reverse, c); + strip.show(); + delay(wait); + } + delay(250); // Hold image for 1/4 sec +} + +// "Larson scanner" = Cylon/KITT bouncing light effect +void scanner(uint8_t r, uint8_t g, uint8_t b, uint8_t wait) { + int i, j, pos, dir; + + pos = 0; + dir = 1; + + for(i=0; i<((strip.numPixels()-1) * 8); i++) { + // Draw 5 pixels centered on pos. setPixelColor() will clip + // any pixels off the ends of the strip, no worries there. + // we'll make the colors dimmer at the edges for a nice pulse + // look + strip.setPixelColor(pos - 2, strip.Color(r/4, g/4, b/4)); + strip.setPixelColor(pos - 1, strip.Color(r/2, g/2, b/2)); + strip.setPixelColor(pos, strip.Color(r, g, b)); + strip.setPixelColor(pos + 1, strip.Color(r/2, g/2, b/2)); + strip.setPixelColor(pos + 2, strip.Color(r/4, g/4, b/4)); + + strip.show(); + delay(wait); + // If we wanted to be sneaky we could erase just the tail end + // pixel, but it's much easier just to erase the whole thing + // and draw a new one next time. + for(j=-2; j<= 2; j++) + strip.setPixelColor(pos+j, strip.Color(0,0,0)); + // Bounce off ends of strip + pos += dir; + if(pos < 0) { + pos = 1; + dir = -dir; + } else if(pos >= strip.numPixels()) { + pos = strip.numPixels() - 2; + dir = -dir; + } + } +} + +// Sine wave effect +#define PI 3.14159265 +void wave(uint32_t c, int cycles, uint8_t wait) { + float y; + byte r, g, b, r2, g2, b2; + + // Need to decompose color into its r, g, b elements + g = (c >> 16) & 0x7f; + r = (c >> 8) & 0x7f; + b = c & 0x7f; + + for(int x=0; x<(strip.numPixels()*5); x++) + { + for(int i=0; i= 0.0) { + // Peaks of sine wave are white + y = 1.0 - y; // Translate Y to 0.0 (top) to 1.0 (center) + r2 = 127 - (byte)((float)(127 - r) * y); + g2 = 127 - (byte)((float)(127 - g) * y); + b2 = 127 - (byte)((float)(127 - b) * y); + } else { + // Troughs of sine wave are black + y += 1.0; // Translate Y to 0.0 (bottom) to 1.0 (center) + r2 = (byte)((float)r * y); + g2 = (byte)((float)g * y); + b2 = (byte)((float)b * y); + } + strip.setPixelColor(i, r2, g2, b2); + } + strip.show(); + delay(wait); + } +} + +/* Helper functions */ + +//Input a value 0 to 384 to get a color value. +//The colours are a transition r - g - b - back to r + +uint32_t Wheel(uint16_t WheelPos) +{ + byte r, g, b; + switch(WheelPos / 128) + { + case 0: + r = 127 - WheelPos % 128; // red down + g = WheelPos % 128; // green up + b = 0; // blue off + break; + case 1: + g = 127 - WheelPos % 128; // green down + b = WheelPos % 128; // blue up + r = 0; // red off + break; + case 2: + b = 127 - WheelPos % 128; // blue down + r = WheelPos % 128; // red up + g = 0; // green off + break; + } + return(strip.Color(r,g,b)); +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/LPD8806/examples/advancedLEDbeltKit/advancedLEDbeltKit.pde b/hardware/digistump/avr/libraries/LPD8806/examples/advancedLEDbeltKit/advancedLEDbeltKit.pde new file mode 100644 index 0000000..58e280a --- /dev/null +++ b/hardware/digistump/avr/libraries/LPD8806/examples/advancedLEDbeltKit/advancedLEDbeltKit.pde @@ -0,0 +1,523 @@ +// Example to control LPD8806-based RGB LED Modules in a strip; originally +// intended for the Adafruit Digital Programmable LED Belt Kit. +// REQUIRES TIMER1 LIBRARY: http://www.arduino.cc/playground/Code/Timer1 +// ALSO REQUIRES LPD8806 LIBRARY, which should be included with this code. + +// I'm generally not fond of canned animation patterns. Wanting something +// more nuanced than the usual 8-bit beep-beep-boop-boop pixelly animation, +// this program smoothly cycles through a set of procedural animated effects +// and transitions -- it's like a Video Toaster for your waist! Some of the +// coding techniques may be a bit obtuse (e.g. function arrays), so novice +// programmers may have an easier time starting out with the 'strandtest' +// program also included with the LPD8806 library. + +#include +#include "SPI.h" +#include "LPD8806.h" +#include "TimerOne.h" + + +#if defined(USB_SERIAL) || defined(USB_SERIAL_ADAFRUIT) +// this is for teensyduino support +int dataPin = 2; +int clockPin = 1; +#else +// these are the pins we use for the LED belt kit using +// the Leonardo pinouts +int dataPin = 16; +int clockPin = 15; +#endif + + +// Declare the number of pixels in strand; 32 = 32 pixels in a row. The +// LED strips have 32 LEDs per meter, but you can extend or cut the strip. +const int numPixels = 32; +// 'const' makes subsequent array declarations possible, otherwise there +// would be a pile of malloc() calls later. + +// Instantiate LED strip; arguments are the total number of pixels in strip, +// the data pin number and clock pin number: +LPD8806 strip = LPD8806(numPixels, dataPin, clockPin); + +// You can also use hardware SPI for ultra-fast writes by omitting the data +// and clock pin arguments. This is faster, but the data and clock are then +// fixed to very specific pin numbers: on Arduino 168/328, data = pin 11, +// clock = pin 13. On Mega, data = pin 51, clock = pin 52. +//LPD8806 strip = LPD8806(numPixels); + +// Principle of operation: at any given time, the LEDs depict an image or +// animation effect (referred to as the "back" image throughout this code). +// Periodically, a transition to a new image or animation effect (referred +// to as the "front" image) occurs. During this transition, a third buffer +// (the "alpha channel") determines how the front and back images are +// combined; it represents the opacity of the front image. When the +// transition completes, the "front" then becomes the "back," a new front +// is chosen, and the process repeats. +byte imgData[2][numPixels * 3], // Data for 2 strips worth of imagery + alphaMask[numPixels], // Alpha channel for compositing images + backImgIdx = 0, // Index of 'back' image (always 0 or 1) + fxIdx[3]; // Effect # for back & front images + alpha +int fxVars[3][50], // Effect instance variables (explained later) + tCounter = -1, // Countdown to next transition + transitionTime; // Duration (in frames) of current transition + +// function prototypes, leave these be :) +void renderEffect00(byte idx); +void renderEffect01(byte idx); +void renderEffect02(byte idx); +void renderEffect03(byte idx); +void renderAlpha00(void); +void renderAlpha01(void); +void renderAlpha02(void); +void renderAlpha03(void); +void callback(); +byte gamma(byte x); +long hsv2rgb(long h, byte s, byte v); +char fixSin(int angle); +char fixCos(int angle); + +// List of image effect and alpha channel rendering functions; the code for +// each of these appears later in this file. Just a few to start with... +// simply append new ones to the appropriate list here: +void (*renderEffect[])(byte) = { + renderEffect00, + renderEffect01, + renderEffect02, + renderEffect03 }, +(*renderAlpha[])(void) = { + renderAlpha00, + renderAlpha01, + renderAlpha02 }; + +// --------------------------------------------------------------------------- + +void setup() { + // Start up the LED strip. Note that strip.show() is NOT called here -- + // the callback function will be invoked immediately when attached, and + // the first thing the calback does is update the strip. + strip.begin(); + + // Initialize random number generator from a floating analog input. + randomSeed(analogRead(0)); + memset(imgData, 0, sizeof(imgData)); // Clear image data + fxVars[backImgIdx][0] = 1; // Mark back image as initialized + + // Timer1 is used so the strip will update at a known fixed frame rate. + // Each effect rendering function varies in processing complexity, so + // the timer allows smooth transitions between effects (otherwise the + // effects and transitions would jump around in speed...not attractive). + Timer1.initialize(); + Timer1.attachInterrupt(callback, 1000000 / 60); // 60 frames/second +} + +void loop() { + // Do nothing. All the work happens in the callback() function below, + // but we still need loop() here to keep the compiler happy. +} + +// Timer1 interrupt handler. Called at equal intervals; 60 Hz by default. +void callback() { + // Very first thing here is to issue the strip data generated from the + // *previous* callback. It's done this way on purpose because show() is + // roughly constant-time, so the refresh will always occur on a uniform + // beat with respect to the Timer1 interrupt. The various effects + // rendering and compositing code is not constant-time, and that + // unevenness would be apparent if show() were called at the end. + strip.show(); + + byte frontImgIdx = 1 - backImgIdx, + *backPtr = &imgData[backImgIdx][0], + r, g, b; + int i; + + // Always render back image based on current effect index: + (*renderEffect[fxIdx[backImgIdx]])(backImgIdx); + + // Front render and composite only happen during transitions... + if(tCounter > 0) { + // Transition in progress + byte *frontPtr = &imgData[frontImgIdx][0]; + int alpha, inv; + + // Render front image and alpha mask based on current effect indices... + (*renderEffect[fxIdx[frontImgIdx]])(frontImgIdx); + (*renderAlpha[fxIdx[2]])(); + + // ...then composite front over back: + for(i=0; i> 8); + g = gamma((*frontPtr++ * alpha + *backPtr++ * inv) >> 8); + b = gamma((*frontPtr++ * alpha + *backPtr++ * inv) >> 8); + strip.setPixelColor(i, r, g, b); + } + } else { + // No transition in progress; just show back image + for(i=0; i= transitionTime) { // End transition + fxIdx[backImgIdx] = fxIdx[frontImgIdx]; // Move front effect index to back + backImgIdx = 1 - backImgIdx; // Invert back index + tCounter = -120 - random(240); // Hold image 2 to 6 seconds + } +} + +// --------------------------------------------------------------------------- +// Image effect rendering functions. Each effect is generated parametrically +// (that is, from a set of numbers, usually randomly seeded). Because both +// back and front images may be rendering the same effect at the same time +// (but with different parameters), a distinct block of parameter memory is +// required for each image. The 'fxVars' array is a two-dimensional array +// of integers, where the major axis is either 0 or 1 to represent the two +// images, while the minor axis holds 50 elements -- this is working scratch +// space for the effect code to preserve its "state." The meaning of each +// element is generally unique to each rendering effect, but the first element +// is most often used as a flag indicating whether the effect parameters have +// been initialized yet. When the back/front image indexes swap at the end of +// each transition, the corresponding set of fxVars, being keyed to the same +// indexes, are automatically carried with them. + +// Simplest rendering effect: fill entire image with solid color +void renderEffect00(byte idx) { + // Only needs to be rendered once, when effect is initialized: + if(fxVars[idx][0] == 0) { + byte *ptr = &imgData[idx][0], + r = random(256), g = random(256), b = random(256); + for(int i=0; i> 16; *ptr++ = color >> 8; *ptr++ = color; + } + fxVars[idx][3] += fxVars[idx][2]; +} + +// Sine wave chase effect +void renderEffect02(byte idx) { + if(fxVars[idx][0] == 0) { // Initialize effect? + fxVars[idx][1] = random(1536); // Random hue + // Number of repetitions (complete loops around color wheel); + // any more than 4 per meter just looks too chaotic. + // Store as distance around complete belt in half-degree units: + fxVars[idx][2] = (1 + random(4 * ((numPixels + 31) / 32))) * 720; + // Frame-to-frame increment (speed) -- may be positive or negative, + // but magnitude shouldn't be so small as to be boring. It's generally + // still less than a full pixel per frame, making motion very smooth. + fxVars[idx][3] = 4 + random(fxVars[idx][1]) / numPixels; + // Reverse direction half the time. + if(random(2) == 0) fxVars[idx][3] = -fxVars[idx][3]; + fxVars[idx][4] = 0; // Current position + fxVars[idx][0] = 1; // Effect initialized + } + + byte *ptr = &imgData[idx][0]; + int foo; + long color, i; + for(long i=0; i= 0) ? + hsv2rgb(fxVars[idx][1], 254 - (foo * 2), 255) : + hsv2rgb(fxVars[idx][1], 255, 254 + foo * 2); + *ptr++ = color >> 16; *ptr++ = color >> 8; *ptr++ = color; + } + fxVars[idx][4] += fxVars[idx][3]; +} + +// Data for American-flag-like colors (20 pixels representing +// blue field, stars and stripes). This gets "stretched" as needed +// to the full LED strip length in the flag effect code, below. +// Can change this data to the colors of your own national flag, +// favorite sports team colors, etc. OK to change number of elements. +#define C_RED 160, 0, 0 +#define C_WHITE 255, 255, 255 +#define C_BLUE 0, 0, 100 +PROGMEM prog_uchar flagTable[] = { + C_BLUE , C_WHITE, C_BLUE , C_WHITE, C_BLUE , C_WHITE, C_BLUE, + C_RED , C_WHITE, C_RED , C_WHITE, C_RED , C_WHITE, C_RED , + C_WHITE, C_RED , C_WHITE, C_RED , C_WHITE, C_RED }; + +// Wavy flag effect +void renderEffect03(byte idx) { + long i, sum, s, x; + int idx1, idx2, a, b; + if(fxVars[idx][0] == 0) { // Initialize effect? + fxVars[idx][1] = 720 + random(720); // Wavyness + fxVars[idx][2] = 4 + random(10); // Wave speed + fxVars[idx][3] = 200 + random(200); // Wave 'puckeryness' + fxVars[idx][4] = 0; // Current position + fxVars[idx][0] = 1; // Effect initialized + } + for(sum=0, i=0; i> 8) * 3; + idx2 = ((x >> 8) + 1) * 3; + b = (x & 255) + 1; + a = 257 - b; + *ptr++ = ((pgm_read_byte(&flagTable[idx1 ]) * a) + + (pgm_read_byte(&flagTable[idx2 ]) * b)) >> 8; + *ptr++ = ((pgm_read_byte(&flagTable[idx1 + 1]) * a) + + (pgm_read_byte(&flagTable[idx2 + 1]) * b)) >> 8; + *ptr++ = ((pgm_read_byte(&flagTable[idx1 + 2]) * a) + + (pgm_read_byte(&flagTable[idx2 + 2]) * b)) >> 8; + s += fxVars[idx][3] + fixCos(fxVars[idx][4] + fxVars[idx][1] * + i / numPixels); + } + + fxVars[idx][4] += fxVars[idx][2]; + if(fxVars[idx][4] >= 720) fxVars[idx][4] -= 720; +} + +// TO DO: Add more effects here...Larson scanner, etc. + +// --------------------------------------------------------------------------- +// Alpha channel effect rendering functions. Like the image rendering +// effects, these are typically parametrically-generated...but unlike the +// images, there is only one alpha renderer "in flight" at any given time. +// So it would be okay to use local static variables for storing state +// information...but, given that there could end up being many more render +// functions here, and not wanting to use up all the RAM for static vars +// for each, a third row of fxVars is used for this information. + +// Simplest alpha effect: fade entire strip over duration of transition. +void renderAlpha00(void) { + byte fade = 255L * tCounter / transitionTime; + for(int i=0; i 0) ? + (255L + (numPixels * fxVars[2][2] / fxVars[2][1])) * + tCounter / transitionTime - (numPixels * fxVars[2][2] / fxVars[2][1]) : + (255L - (numPixels * fxVars[2][2] / fxVars[2][1])) * + tCounter / transitionTime; + for(x=0; x= 255) alphaMask[x] = 255; + else alphaMask[x] = (byte)y; + } +} + +// Dither reveal between images +void renderAlpha02(void) { + long fade; + int i, bit, reverse, hiWord; + + if(fxVars[2][0] == 0) { + // Determine most significant bit needed to represent pixel count. + int hiBit, n = (numPixels - 1) >> 1; + for(hiBit=1; n; n >>=1) hiBit <<= 1; + fxVars[2][1] = hiBit; + fxVars[2][0] = 1; // Transition initialized + } + + for(i=0; i> 8); + if(reverse == hiWord) alphaMask[i] = (fade & 255); // Remainder + else if(reverse < hiWord) alphaMask[i] = 255; + else alphaMask[i] = 0; + } +} + +// TO DO: Add more transitions here...triangle wave reveal, etc. + +// --------------------------------------------------------------------------- +// Assorted fixed-point utilities below this line. Not real interesting. + +// Gamma correction compensates for our eyes' nonlinear perception of +// intensity. It's the LAST step before a pixel value is stored, and +// allows intermediate rendering/processing to occur in linear space. +// The table contains 256 elements (8 bit input), though the outputs are +// only 7 bits (0 to 127). This is normal and intentional by design: it +// allows all the rendering code to operate in the more familiar unsigned +// 8-bit colorspace (used in a lot of existing graphics code), and better +// preserves accuracy where repeated color blending operations occur. +// Only the final end product is converted to 7 bits, the native format +// for the LPD8806 LED driver. Gamma correction and 7-bit decimation +// thus occur in a single operation. +PROGMEM prog_uchar gammaTable[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, + 4, 4, 4, 4, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 7, 7, + 7, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, + 11, 11, 12, 12, 12, 13, 13, 13, 13, 14, 14, 14, 15, 15, 16, 16, + 16, 17, 17, 17, 18, 18, 18, 19, 19, 20, 20, 21, 21, 21, 22, 22, + 23, 23, 24, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29, 29, 30, + 30, 31, 32, 32, 33, 33, 34, 34, 35, 35, 36, 37, 37, 38, 38, 39, + 40, 40, 41, 41, 42, 43, 43, 44, 45, 45, 46, 47, 47, 48, 49, 50, + 50, 51, 52, 52, 53, 54, 55, 55, 56, 57, 58, 58, 59, 60, 61, 62, + 62, 63, 64, 65, 66, 67, 67, 68, 69, 70, 71, 72, 73, 74, 74, 75, + 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, + 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,104,105,106,107,108, + 109,110,111,113,114,115,116,117,118,120,121,122,123,125,126,127 +}; + +// This function (which actually gets 'inlined' anywhere it's called) +// exists so that gammaTable can reside out of the way down here in the +// utility code...didn't want that huge table distracting or intimidating +// folks before even getting into the real substance of the program, and +// the compiler permits forward references to functions but not data. +inline byte gamma(byte x) { + return pgm_read_byte(&gammaTable[x]); +} + +// Fixed-point colorspace conversion: HSV (hue-saturation-value) to RGB. +// This is a bit like the 'Wheel' function from the original strandtest +// code on steroids. The angular units for the hue parameter may seem a +// bit odd: there are 1536 increments around the full color wheel here -- +// not degrees, radians, gradians or any other conventional unit I'm +// aware of. These units make the conversion code simpler/faster, because +// the wheel can be divided into six sections of 256 values each, very +// easy to handle on an 8-bit microcontroller. Math is math, and the +// rendering code elsehwere in this file was written to be aware of these +// units. Saturation and value (brightness) range from 0 to 255. +long hsv2rgb(long h, byte s, byte v) { + byte r, g, b, lo; + int s1; + long v1; + + // Hue + h %= 1536; // -1535 to +1535 + if(h < 0) h += 1536; // 0 to +1535 + lo = h & 255; // Low byte = primary/secondary color mix + switch(h >> 8) { // High byte = sextant of colorwheel + case 0 : r = 255 ; g = lo ; b = 0 ; break; // R to Y + case 1 : r = 255 - lo; g = 255 ; b = 0 ; break; // Y to G + case 2 : r = 0 ; g = 255 ; b = lo ; break; // G to C + case 3 : r = 0 ; g = 255 - lo; b = 255 ; break; // C to B + case 4 : r = lo ; g = 0 ; b = 255 ; break; // B to M + default: r = 255 ; g = 0 ; b = 255 - lo; break; // M to R + } + + // Saturation: add 1 so range is 1 to 256, allowig a quick shift operation + // on the result rather than a costly divide, while the type upgrade to int + // avoids repeated type conversions in both directions. + s1 = s + 1; + r = 255 - (((255 - r) * s1) >> 8); + g = 255 - (((255 - g) * s1) >> 8); + b = 255 - (((255 - b) * s1) >> 8); + + // Value (brightness) and 24-bit color concat merged: similar to above, add + // 1 to allow shifts, and upgrade to long makes other conversions implicit. + v1 = v + 1; + return (((r * v1) & 0xff00) << 8) | + ((g * v1) & 0xff00) | + ( (b * v1) >> 8); +} + +// The fixed-point sine and cosine functions use marginally more +// conventional units, equal to 1/2 degree (720 units around full circle), +// chosen because this gives a reasonable resolution for the given output +// range (-127 to +127). Sine table intentionally contains 181 (not 180) +// elements: 0 to 180 *inclusive*. This is normal. + +PROGMEM prog_char sineTable[181] = { + 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 17, + 18, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 32, 33, 34, + 35, 36, 37, 38, 39, 40, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, + 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, + 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 77, 78, 79, 80, 81, + 82, 83, 83, 84, 85, 86, 87, 88, 88, 89, 90, 91, 92, 92, 93, 94, + 95, 95, 96, 97, 97, 98, 99,100,100,101,102,102,103,104,104,105, + 105,106,107,107,108,108,109,110,110,111,111,112,112,113,113,114, + 114,115,115,116,116,117,117,117,118,118,119,119,120,120,120,121, + 121,121,122,122,122,123,123,123,123,124,124,124,124,125,125,125, + 125,125,126,126,126,126,126,126,126,127,127,127,127,127,127,127, + 127,127,127,127,127 +}; + +char fixSin(int angle) { + angle %= 720; // -719 to +719 + if(angle < 0) angle += 720; // 0 to +719 + return (angle <= 360) ? + pgm_read_byte(&sineTable[(angle <= 180) ? + angle : // Quadrant 1 + (360 - angle)]) : // Quadrant 2 + -pgm_read_byte(&sineTable[(angle <= 540) ? + (angle - 360) : // Quadrant 3 + (720 - angle)]) ; // Quadrant 4 +} + +char fixCos(int angle) { + angle %= 720; // -719 to +719 + if(angle < 0) angle += 720; // 0 to +719 + return (angle <= 360) ? + ((angle <= 180) ? pgm_read_byte(&sineTable[180 - angle]) : // Quad 1 + -pgm_read_byte(&sineTable[angle - 180])) : // Quad 2 + ((angle <= 540) ? -pgm_read_byte(&sineTable[540 - angle]) : // Quad 3 + pgm_read_byte(&sineTable[angle - 540])) ; // Quad 4 +} + diff --git a/hardware/digistump/avr/libraries/LPD8806/examples/longstrandtest/longstrandtest.pde b/hardware/digistump/avr/libraries/LPD8806/examples/longstrandtest/longstrandtest.pde new file mode 100644 index 0000000..42af884 --- /dev/null +++ b/hardware/digistump/avr/libraries/LPD8806/examples/longstrandtest/longstrandtest.pde @@ -0,0 +1,60 @@ +#include "LPD8806.h" +#include "SPI.h" + +// Simple test for 160 (5 meters) of LPD8806-based RGB LED strip + +/*****************************************************************************/ + +// Number of RGB LEDs in strand: +int nLEDs = 160; + +// Chose 2 pins for output; can be any valid output pins: +int dataPin = 2; +int clockPin = 3; + +// First parameter is the number of LEDs in the strand. The LED strips +// are 32 LEDs per meter but you can extend or cut the strip. Next two +// parameters are SPI data and clock pins: +LPD8806 strip = LPD8806(nLEDs, dataPin, clockPin); + +// You can optionally use hardware SPI for faster writes, just leave out +// the data and clock pin parameters. But this does limit use to very +// specific pins on the Arduino. For "classic" Arduinos (Uno, Duemilanove, +// etc.), data = pin 11, clock = pin 13. For Arduino Mega, data = pin 51, +// clock = pin 52. For 32u4 Breakout Board+ and Teensy, data = pin B2, +// clock = pin B1. For Leonardo, this can ONLY be done on the ICSP pins. +//LPD8806 strip = LPD8806(nLEDs); + +void setup() { + // Start up the LED strip + strip.begin(); + + // Update the strip, to start they are all 'off' + strip.show(); +} + +void loop() { + colorChase(strip.Color(127, 0, 0), 100); // Red + colorChase(strip.Color( 0,127, 0), 100); // Green + colorChase(strip.Color( 0, 0,127), 100); // Blue + colorChase(strip.Color(127,127,127), 100); // White +} + +// Chase one dot down the full strip. Good for testing purposes. +void colorChase(uint32_t c, uint8_t wait) { + int i; + + // Start by turning all pixels off: + for(i=0; i8 ) + numDevices=8; + maxDevices=numDevices; + pinMode(SPI_MOSI,OUTPUT); + pinMode(SPI_CLK,OUTPUT); + pinMode(SPI_CS,OUTPUT); + digitalWrite(SPI_CS,HIGH); + SPI_MOSI=dataPin; + for(int i=0;i<64;i++) + status[i]=0x00; + for(int i=0;i=maxDevices) + return; + if(b) + spiTransfer(addr, OP_SHUTDOWN,0); + else + spiTransfer(addr, OP_SHUTDOWN,1); +} + +void LedControl::setScanLimit(int addr, int limit) { + if(addr<0 || addr>=maxDevices) + return; + if(limit>=0 || limit<8) + spiTransfer(addr, OP_SCANLIMIT,limit); +} + +void LedControl::setIntensity(int addr, int intensity) { + if(addr<0 || addr>=maxDevices) + return; + if(intensity>=0 || intensity<16) + spiTransfer(addr, OP_INTENSITY,intensity); + +} + +void LedControl::clearDisplay(int addr) { + int offset; + + if(addr<0 || addr>=maxDevices) + return; + offset=addr*8; + for(int i=0;i<8;i++) { + status[offset+i]=0; + spiTransfer(addr, i+1,status[offset+i]); + } +} + +void LedControl::setLed(int addr, int row, int column, boolean state) { + int offset; + byte val=0x00; + + if(addr<0 || addr>=maxDevices) + return; + if(row<0 || row>7 || column<0 || column>7) + return; + offset=addr*8; + val=B10000000 >> column; + if(state) + status[offset+row]=status[offset+row]|val; + else { + val=~val; + status[offset+row]=status[offset+row]&val; + } + spiTransfer(addr, row+1,status[offset+row]); +} + +void LedControl::setRow(int addr, int row, byte value) { + int offset; + if(addr<0 || addr>=maxDevices) + return; + if(row<0 || row>7) + return; + offset=addr*8; + status[offset+row]=value; + spiTransfer(addr, row+1,status[offset+row]); +} + +void LedControl::setColumn(int addr, int col, byte value) { + byte val; + + if(addr<0 || addr>=maxDevices) + return; + if(col<0 || col>7) + return; + for(int row=0;row<8;row++) { + val=value >> (7-row); + val=val & 0x01; + setLed(addr,row,col,val); + } +} + +void LedControl::setDigit(int addr, int digit, byte value, boolean dp) { + int offset; + byte v; + + if(addr<0 || addr>=maxDevices) + return; + if(digit<0 || digit>7 || value>15) + return; + offset=addr*8; + v=charTable[value]; + if(dp) + v|=B10000000; + status[offset+digit]=v; + spiTransfer(addr, digit+1,v); + +} + +void LedControl::setChar(int addr, int digit, char value, boolean dp) { + int offset; + byte index,v; + + if(addr<0 || addr>=maxDevices) + return; + if(digit<0 || digit>7) + return; + offset=addr*8; + index=(byte)value; + if(index >127) { + //nothing define we use the space char + value=32; + } + v=charTable[index]; + if(dp) + v|=B10000000; + status[offset+digit]=v; + spiTransfer(addr, digit+1,v); +} + +void LedControl::spiTransfer(int addr, volatile byte opcode, volatile byte data) { + //Create an array with the data to shift out + int offset=addr*2; + int maxbytes=maxDevices*2; + + for(int i=0;i0;i--) + shiftOut(SPI_MOSI,SPI_CLK,MSBFIRST,spidata[i-1]); + //latch the data onto the display + digitalWrite(SPI_CS,HIGH); +} + + diff --git a/hardware/digistump/avr/libraries/LedControl/LedControl.h b/hardware/digistump/avr/libraries/LedControl/LedControl.h new file mode 100644 index 0000000..6f2e6c9 --- /dev/null +++ b/hardware/digistump/avr/libraries/LedControl/LedControl.h @@ -0,0 +1,188 @@ +/* + * LedControl.h - A library for controling Leds with a MAX7219/MAX7221 + * Copyright (c) 2007 Eberhard Fahle + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * This permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef LedControl_h +#define LedControl_h + +#if (ARDUINO >= 100) +#include +#else +#include +#endif + +/* + * Segments to be switched on for characters and digits on + * 7-Segment Displays + */ +const static byte charTable[128] = { + B01111110,B00110000,B01101101,B01111001,B00110011,B01011011,B01011111,B01110000, + B01111111,B01111011,B01110111,B00011111,B00001101,B00111101,B01001111,B01000111, + B00000000,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000, + B00000000,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000, + B00000000,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000, + B00000000,B00000000,B00000000,B00000000,B10000000,B00000001,B10000000,B00000000, + B01111110,B00110000,B01101101,B01111001,B00110011,B01011011,B01011111,B01110000, + B01111111,B01111011,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000, + B00000000,B01110111,B00011111,B00001101,B00111101,B01001111,B01000111,B00000000, + B00110111,B00000000,B00000000,B00000000,B00001110,B00000000,B00000000,B00000000, + B01100111,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000, + B00000000,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000,B00001000, + B00000000,B01110111,B00011111,B00001101,B00111101,B01001111,B01000111,B00000000, + B00110111,B00000000,B00000000,B00000000,B00001110,B00000000,B00000000,B00000000, + B01100111,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000, + B00000000,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000,B00000000 +}; + +class LedControl { + private : + /* The array for shifting the data to the devices */ + byte spidata[16]; + /* Send out a single command to the device */ + void spiTransfer(int addr, byte opcode, byte data); + + /* We keep track of the led-status for all 8 devices in this array */ + byte status[64]; + /* Data is shifted out of this pin*/ + int SPI_MOSI; + /* The clock is signaled on this pin */ + int SPI_CLK; + /* This one is driven LOW for chip selectzion */ + int SPI_CS; + /* The maximum number of devices we use */ + int maxDevices; + + public: + /* + * Create a new controler + * Params : + * dataPin pin on the Arduino where data gets shifted out + * clockPin pin for the clock + * csPin pin for selecting the device + * numDevices maximum number of devices that can be controled + */ + LedControl(int dataPin, int clkPin, int csPin, int numDevices=1); + + /* + * Gets the number of devices attached to this LedControl. + * Returns : + * int the number of devices on this LedControl + */ + int getDeviceCount(); + + /* + * Set the shutdown (power saving) mode for the device + * Params : + * addr The address of the display to control + * status If true the device goes into power-down mode. Set to false + * for normal operation. + */ + void shutdown(int addr, bool status); + + /* + * Set the number of digits (or rows) to be displayed. + * See datasheet for sideeffects of the scanlimit on the brightness + * of the display. + * Params : + * addr address of the display to control + * limit number of digits to be displayed (1..8) + */ + void setScanLimit(int addr, int limit); + + /* + * Set the brightness of the display. + * Params: + * addr the address of the display to control + * intensity the brightness of the display. (0..15) + */ + void setIntensity(int addr, int intensity); + + /* + * Switch all Leds on the display off. + * Params: + * addr address of the display to control + */ + void clearDisplay(int addr); + + /* + * Set the status of a single Led. + * Params : + * addr address of the display + * row the row of the Led (0..7) + * col the column of the Led (0..7) + * state If true the led is switched on, + * if false it is switched off + */ + void setLed(int addr, int row, int col, boolean state); + + /* + * Set all 8 Led's in a row to a new state + * Params: + * addr address of the display + * row row which is to be set (0..7) + * value each bit set to 1 will light up the + * corresponding Led. + */ + void setRow(int addr, int row, byte value); + + /* + * Set all 8 Led's in a column to a new state + * Params: + * addr address of the display + * col column which is to be set (0..7) + * value each bit set to 1 will light up the + * corresponding Led. + */ + void setColumn(int addr, int col, byte value); + + /* + * Display a hexadecimal digit on a 7-Segment Display + * Params: + * addr address of the display + * digit the position of the digit on the display (0..7) + * value the value to be displayed. (0x00..0x0F) + * dp sets the decimal point. + */ + void setDigit(int addr, int digit, byte value, boolean dp); + + /* + * Display a character on a 7-Segment display. + * There are only a few characters that make sense here : + * '0','1','2','3','4','5','6','7','8','9','0', + * 'A','b','c','d','E','F','H','L','P', + * '.','-','_',' ' + * Params: + * addr address of the display + * digit the position of the character on the display (0..7) + * value the character to be displayed. + * dp sets the decimal point. + */ + void setChar(int addr, int digit, char value, boolean dp); +}; + +#endif //LedControl.h + + + diff --git a/hardware/digistump/avr/libraries/LedControl/examples/LCDemo7Segment/LCDemo7Segment.pde b/hardware/digistump/avr/libraries/LedControl/examples/LCDemo7Segment/LCDemo7Segment.pde new file mode 100644 index 0000000..a75f32f --- /dev/null +++ b/hardware/digistump/avr/libraries/LedControl/examples/LCDemo7Segment/LCDemo7Segment.pde @@ -0,0 +1,73 @@ +//We always have to include the library +#include "LedControl.h" + +/* + Now we need a LedControl to work with. + ***** These pin numbers will probably not work with your hardware ***** + pin 12 is connected to the DataIn + pin 11 is connected to the CLK + pin 10 is connected to LOAD + We have only a single MAX72XX. + */ +LedControl lc=LedControl(12,11,10,1); + +/* we always wait a bit between updates of the display */ +unsigned long delaytime=250; + +void setup() { + /* + The MAX72XX is in power-saving mode on startup, + we have to do a wakeup call + */ + lc.shutdown(0,false); + /* Set the brightness to a medium values */ + lc.setIntensity(0,8); + /* and clear the display */ + lc.clearDisplay(0); +} + + +/* + This method will display the characters for the + word "Arduino" one after the other on digit 0. + */ +void writeArduinoOn7Segment() { + lc.setChar(0,0,'a',false); + delay(delaytime); + lc.setRow(0,0,0x05); + delay(delaytime); + lc.setChar(0,0,'d',false); + delay(delaytime); + lc.setRow(0,0,0x1c); + delay(delaytime); + lc.setRow(0,0,B00010000); + delay(delaytime); + lc.setRow(0,0,0x15); + delay(delaytime); + lc.setRow(0,0,0x1D); + delay(delaytime); + lc.clearDisplay(0); + delay(delaytime); +} + +/* + This method will scroll all the hexa-decimal + numbers and letters on the display. You will need at least + four 7-Segment digits. otherwise it won't really look that good. + */ +void scrollDigits() { + for(int i=0;i<13;i++) { + lc.setDigit(0,3,i,false); + lc.setDigit(0,2,i+1,false); + lc.setDigit(0,1,i+2,false); + lc.setDigit(0,0,i+3,false); + delay(delaytime); + } + lc.clearDisplay(0); + delay(delaytime); +} + +void loop() { + writeArduinoOn7Segment(); + scrollDigits(); +} diff --git a/hardware/digistump/avr/libraries/LedControl/examples/LCDemoCascadedDevices/LCDemoCascadedDevices.pde b/hardware/digistump/avr/libraries/LedControl/examples/LCDemoCascadedDevices/LCDemoCascadedDevices.pde new file mode 100644 index 0000000..090b8dd --- /dev/null +++ b/hardware/digistump/avr/libraries/LedControl/examples/LCDemoCascadedDevices/LCDemoCascadedDevices.pde @@ -0,0 +1,52 @@ +//We always have to include the library +#include "LedControl.h" + +/* + Now we need a LedControl to work with. + ***** These pin numbers will probably not work with your hardware ***** + pin 12 is connected to the DataIn + pin 11 is connected to the CLK + pin 10 is connected to LOAD + ***** Please set the number of devices you have ***** + But the maximum default of 8 MAX72XX wil also work. + */ +LedControl lc=LedControl(12,11,10,8); + +/* we always wait a bit between updates of the display */ +unsigned long delaytime=500; + +/* + This time we have more than one device. + But all of them have to be initialized + individually. + */ +void setup() { + //we have already set the number of devices when we created the LedControl + int devices=lc.getDeviceCount(); + //we have to init all devices in a loop + for(int address=0;address +* All rights reserved. +*************************************************************************/ + +//#include + #if ARDUINO >= 100 + #include "Arduino.h" + #define WIRE_WRITE Wire.write +#else + #include "WProgram.h" + #define WIRE_WRITE Wire.send +#endif +#include +#include "MicrOledPro.h" + +// fonts data +const PROGMEM unsigned char digits16x24[][48] = { +{0x00,0x00,0x00,0xF0,0xFF,0x0F,0xFC,0xFF,0x3F,0xFE,0xFF,0x7F,0xFE,0xFF,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x07,0x00,0xE0,0x07,0x00,0xE0,0x07,0x00,0xE0,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFF,0x7F,0xFE,0xFF,0x7F,0xFC,0xFF,0x3F,0xF0,0xFF,0x0F},/*"0",0*/ +{0x00,0x00,0x00,0x70,0x00,0x00,0x70,0x00,0x00,0x70,0x00,0x00,0x78,0x00,0x00,0xF8,0x00,0x00,0xFC,0xFF,0xFF,0xFE,0xFF,0xFF,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"1",0*/ +{0x00,0x00,0x00,0xF8,0x00,0xE0,0xFC,0x00,0xF8,0xFE,0x00,0xFE,0xFE,0x80,0xFF,0xFF,0xC0,0xFF,0x07,0xF0,0xFF,0x07,0xFC,0xFF,0x07,0xFF,0xEF,0xFF,0xFF,0xE3,0xFF,0xFF,0xE1,0xFE,0x7F,0xE0,0xFE,0x3F,0xE0,0xFC,0x0F,0xE0,0xF0,0x03,0x00,0x00,0x00,0x00},/*"2",2*/ +{0x00,0x00,0x00,0xF8,0x80,0x1F,0xFE,0x80,0x3F,0xFE,0x80,0x7F,0xFF,0x80,0x7F,0xFF,0x80,0xFF,0xFF,0x9C,0xFF,0xFF,0x9C,0xFF,0x07,0x1C,0xE0,0x07,0x3E,0xE0,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFF,0x7F,0xFE,0xF7,0x7F,0xFC,0xF7,0x3F,0xF0,0xE3,0x1F},/*"3",3*/ +{0x00,0xF0,0x0F,0x00,0xFE,0x0F,0x80,0xFF,0x0F,0xE0,0xFF,0x0F,0xFC,0xBF,0x0F,0xFF,0x87,0x0F,0xFF,0x81,0x0F,0x3F,0x80,0x0F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x80,0x0F,0x00,0x80,0x0F},/*"4",4*/ +{0x00,0x00,0x00,0xFF,0xC7,0x0F,0xFF,0xC7,0x3F,0xFF,0xC7,0x7F,0xFF,0xC7,0x7F,0xFF,0xC7,0xFF,0xFF,0xC7,0xFF,0x87,0x01,0xE0,0xC7,0x01,0xE0,0xC7,0x01,0xE0,0xC7,0xFF,0xFF,0xC7,0xFF,0xFF,0xC7,0xFF,0x7F,0x87,0xFF,0x7F,0x87,0xFF,0x3F,0x07,0xFE,0x1F},/*"5",5*/ +{0x00,0x00,0x00,0xF0,0xFF,0x0F,0xFC,0xFF,0x3F,0xFE,0xFF,0x7F,0xFE,0xFF,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x07,0x06,0xE0,0x07,0x07,0xE0,0x07,0x07,0xE0,0x3F,0xFF,0xFF,0x3F,0xFF,0xFF,0x3E,0xFF,0x7F,0x3E,0xFE,0x7F,0x3C,0xFE,0x3F,0x38,0xF8,0x1F},/*"6",6*/ +{0x00,0x00,0x00,0x07,0x00,0x00,0x07,0x00,0x00,0x07,0x00,0xC0,0x07,0x00,0xF8,0x07,0x00,0xFF,0x07,0xE0,0xFF,0x07,0xFE,0xFF,0xC7,0xFF,0xFF,0xFF,0xFF,0x3F,0xFF,0xFF,0x07,0xFF,0xFF,0x00,0xFF,0x0F,0x00,0xFF,0x01,0x00,0x1F,0x00,0x00,0x00,0x00,0x00},/*"7",1*/ +{0x00,0x00,0x00,0xF0,0xE3,0x1F,0xFC,0xF7,0x3F,0xFE,0xFF,0x7F,0xFE,0xFF,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x07,0x1C,0xE0,0x07,0x1C,0xE0,0x07,0x1C,0xE0,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFF,0x7F,0xFE,0xF7,0x7F,0xFC,0xF7,0x3F,0xF0,0xE3,0x1F},/*"8",8*/ +{0x00,0x00,0x00,0xF8,0x1F,0x1C,0xFC,0x7F,0x3C,0xFE,0x7F,0x7C,0xFE,0xFF,0x7C,0xFF,0xFF,0xFC,0xFF,0xFF,0xFC,0x07,0xE0,0xE0,0x07,0xE0,0xE0,0x07,0x60,0xE0,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFF,0x7F,0xFE,0xFF,0x7F,0xFC,0xFF,0x3F,0xF0,0xFF,0x0F},/*"9",9*/ +}; + +const PROGMEM unsigned char digits8x8[][8] = { +{0x3C,0x7E,0x83,0x81,0x81,0x7E,0x3C,0x00},/*0*/ +{0x84,0x84,0x82,0xFF,0xFF,0x80,0x80,0x00},/*1*/ +{0x84,0xC6,0xE1,0xA1,0xB1,0x9F,0x8E,0x00},/*2*/ +{0x42,0xC3,0x81,0x89,0x89,0xFF,0x76,0x00},/*3*/ +{0x20,0x38,0x24,0x22,0xFF,0xFF,0x20,0x00},/*4*/ +{0x5F,0xDF,0x99,0x89,0x89,0xF9,0x70,0x00},/*5*/ +{0x3C,0x7E,0x89,0x89,0x89,0xFB,0x72,0x00},/*6*/ +{0x01,0x01,0xE1,0xF9,0x1D,0x07,0x01,0x00},/*7*/ +{0x6E,0xFF,0x89,0x89,0x99,0xFF,0x76,0x00},/*8*/ +{0x4E,0xDF,0x91,0x91,0x91,0x7F,0x3E,0x00},/*9*/ +}; + +// The 7-bit ASCII character set... +const PROGMEM unsigned char font5x8[][5] = { + { 0x00, 0x00, 0x5f, 0x00, 0x00 }, // 21 ! + { 0x00, 0x07, 0x00, 0x07, 0x00 }, // 22 " + { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // 23 # + { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // 24 $ + { 0x23, 0x13, 0x08, 0x64, 0x62 }, // 25 % + { 0x36, 0x49, 0x55, 0x22, 0x50 }, // 26 & + { 0x00, 0x05, 0x03, 0x00, 0x00 }, // 27 ' + { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // 28 ( + { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // 29 ) + { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // 2a * + { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // 2b + + { 0x00, 0x50, 0x30, 0x00, 0x00 }, // 2c , + { 0x08, 0x08, 0x08, 0x08, 0x08 }, // 2d - + { 0x00, 0x60, 0x60, 0x00, 0x00 }, // 2e . + { 0x20, 0x10, 0x08, 0x04, 0x02 }, // 2f / + { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 30 0 + { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 31 1 + { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 32 2 + { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 33 3 + { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 34 4 + { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 35 5 + { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 36 6 + { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 37 7 + { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 38 8 + { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 39 9 + { 0x00, 0x36, 0x36, 0x00, 0x00 }, // 3a : + { 0x00, 0x56, 0x36, 0x00, 0x00 }, // 3b ; + { 0x08, 0x14, 0x22, 0x41, 0x00 }, // 3c < + { 0x14, 0x14, 0x14, 0x14, 0x14 }, // 3d = + { 0x00, 0x41, 0x22, 0x14, 0x08 }, // 3e > + { 0x02, 0x01, 0x51, 0x09, 0x06 }, // 3f ? + { 0x32, 0x49, 0x79, 0x41, 0x3e }, // 40 @ + { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // 41 A + { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // 42 B + { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // 43 C + { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // 44 D + { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // 45 E + { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // 46 F + { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // 47 G + { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // 48 H + { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // 49 I + { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // 4a J + { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // 4b K + { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // 4c L + { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // 4d M + { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // 4e N + { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // 4f O + { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // 50 P + { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // 51 Q + { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // 52 R + { 0x46, 0x49, 0x49, 0x49, 0x31 }, // 53 S + { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // 54 T + { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // 55 U + { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // 56 V + { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // 57 W + { 0x63, 0x14, 0x08, 0x14, 0x63 }, // 58 X + { 0x07, 0x08, 0x70, 0x08, 0x07 }, // 59 Y + { 0x61, 0x51, 0x49, 0x45, 0x43 }, // 5a Z + { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // 5b [ + { 0x02, 0x04, 0x08, 0x10, 0x20 }, // 5c backslash + { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // 5d ] + { 0x04, 0x02, 0x01, 0x02, 0x04 }, // 5e ^ + { 0x40, 0x40, 0x40, 0x40, 0x40 }, // 5f _ + { 0x00, 0x01, 0x02, 0x04, 0x00 }, // 60 ` + { 0x20, 0x54, 0x54, 0x54, 0x78 }, // 61 a + { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // 62 b + { 0x38, 0x44, 0x44, 0x44, 0x20 }, // 63 c + { 0x38, 0x44, 0x44, 0x48, 0x7f }, // 64 d + { 0x38, 0x54, 0x54, 0x54, 0x18 }, // 65 e + { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // 66 f + { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // 67 g + { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // 68 h + { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // 69 i + { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // 6a j + { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // 6b k + { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // 6c l + { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // 6d m + { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // 6e n + { 0x38, 0x44, 0x44, 0x44, 0x38 }, // 6f o + { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // 70 p + { 0x08, 0x14, 0x14, 0x18, 0x7c }, // 71 q + { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // 72 r + { 0x48, 0x54, 0x54, 0x54, 0x20 }, // 73 s + { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // 74 t + { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // 75 u + { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // 76 v + { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // 77 w + { 0x44, 0x28, 0x10, 0x28, 0x44 }, // 78 x + { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // 79 y + { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // 7a z + { 0x00, 0x08, 0x36, 0x41, 0x00 }, // 7b { + { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // 7c | + { 0x00, 0x41, 0x36, 0x08, 0x00 }, // 7d } + { 0x10, 0x08, 0x08, 0x10, 0x08 }, // 7e ~ +}; + +#ifndef MEMORY_SAVING +const PROGMEM unsigned char digits16x16[][32] = { +{0x00,0xE0,0xF8,0xFC,0xFE,0x1E,0x07,0x07,0x07,0x07,0x1E,0xFE,0xFC,0xF8,0xF0,0x00,0x00,0x07,0x0F,0x3F,0x3F,0x7C,0x70,0x70,0x70,0x70,0x7C,0x3F,0x1F,0x1F,0x07,0x00},/*0*/ +{0x00,0x00,0x00,0x06,0x07,0x07,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x7F,0x7F,0x7F,0x00,0x00,0x00,0x00,0x00,0x00},/*1*/ +{0x00,0x38,0x3C,0x3E,0x3E,0x0F,0x07,0x07,0x07,0xCF,0xFF,0xFE,0xFE,0x38,0x00,0x00,0x00,0x40,0x40,0x60,0x70,0x78,0x7C,0x7E,0x7F,0x77,0x73,0x71,0x70,0x70,0x00,0x00},/*2*/ +{0x00,0x18,0x1C,0x1E,0x1E,0x0F,0xC7,0xC7,0xE7,0xFF,0xFE,0xBE,0x9C,0x00,0x00,0x00,0x00,0x0C,0x1C,0x3C,0x3C,0x78,0x70,0x70,0x70,0x79,0x7F,0x3F,0x1F,0x0F,0x00,0x00},/*3*/ +{0x00,0x00,0x80,0xC0,0xE0,0x70,0x38,0x1C,0x1E,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x06,0x07,0x07,0x07,0x06,0x06,0x06,0x06,0x06,0x7F,0x7F,0x7F,0x7F,0x06,0x06,0x00},/*4*/ +{0x00,0x00,0x00,0x00,0xF0,0xFF,0xFF,0xFF,0xE7,0xE7,0xE7,0xE7,0xC7,0x87,0x00,0x00,0x00,0x00,0x38,0x78,0x71,0x70,0x70,0x70,0x70,0x70,0x39,0x3F,0x3F,0x1F,0x0F,0x00},/*5*/ +{0x00,0x80,0xE0,0xF0,0xF8,0xFC,0x7F,0x7F,0x6F,0x67,0xE1,0xE1,0xC0,0x80,0x00,0x00,0x00,0x0F,0x1F,0x3F,0x3F,0x78,0x70,0x70,0x70,0x70,0x78,0x3F,0x3F,0x1F,0x0F,0x00},/*6*/ +{0x00,0x07,0x07,0x07,0x07,0x07,0xC7,0xE7,0xF7,0xFF,0x7F,0x3F,0x1F,0x07,0x03,0x01,0x00,0x20,0x38,0x7C,0x7E,0x3F,0x0F,0x07,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*7*/ +{0x00,0x00,0x00,0x1C,0xBE,0xFE,0xFF,0xE7,0xC3,0xC3,0xE7,0xFF,0xFE,0xBE,0x1C,0x00,0x00,0x00,0x0E,0x3F,0x3F,0x7F,0x71,0x60,0x60,0x60,0x71,0x7F,0x3F,0x3F,0x0F,0x00},/*8*/ +{0x00,0x78,0xFC,0xFE,0xFE,0x8F,0x07,0x07,0x07,0x07,0x8F,0xFE,0xFE,0xFC,0xF8,0x00,0x00,0x00,0x00,0x01,0x43,0x43,0x73,0x7B,0x7F,0x7F,0x1F,0x0F,0x07,0x03,0x00,0x00},/*9*/ +}; + +const PROGMEM unsigned char font8x16_terminal[][16] = { +{0x00,0x00,0x00,0x00,0x7C,0x00,0xFE,0x1B,0xFE,0x1B,0x7C,0x00,0x00,0x00,0x00,0x00},/*"!",0*/ +{0x00,0x00,0x0E,0x00,0x1E,0x00,0x00,0x00,0x00,0x00,0x1E,0x00,0x0E,0x00,0x00,0x00},/*""",1*/ +{0x20,0x01,0xFC,0x0F,0xFC,0x0F,0x20,0x01,0x20,0x01,0xFC,0x0F,0xFC,0x0F,0x20,0x01},/*"#",2*/ +{0x38,0x06,0x7C,0x0C,0x44,0x08,0xFF,0x3F,0xFF,0x3F,0x84,0x08,0x8C,0x0F,0x18,0x07},/*"$",3*/ +{0x1C,0x18,0x14,0x1E,0x9C,0x07,0xE0,0x01,0x78,0x1C,0x1E,0x14,0x06,0x1C,0x00,0x00},/*"%",4*/ +{0xBC,0x1F,0xFE,0x10,0x42,0x10,0xC2,0x10,0xFE,0x1F,0x3C,0x0F,0x80,0x19,0x80,0x10},/*"&",5*/ +{0x00,0x00,0x00,0x00,0x10,0x00,0x1E,0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",6*/ +{0x00,0x00,0x00,0x00,0xF0,0x07,0xFC,0x1F,0x0E,0x38,0x02,0x20,0x00,0x00,0x00,0x00},/*"(",7*/ +{0x00,0x00,0x00,0x00,0x02,0x20,0x0E,0x38,0xFC,0x1F,0xF0,0x07,0x00,0x00,0x00,0x00},/*")",8*/ +{0x80,0x00,0xA0,0x02,0xE0,0x03,0xC0,0x01,0xC0,0x01,0xE0,0x03,0xA0,0x02,0x80,0x00},/*"*",9*/ +{0x80,0x00,0x80,0x00,0x80,0x00,0xE0,0x03,0xE0,0x03,0x80,0x00,0x80,0x00,0x80,0x00},/*"+",10*/ +{0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x78,0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00},/*",",11*/ +{0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00},/*"-",12*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00},/*".",13*/ +{0x00,0x18,0x00,0x1E,0x80,0x07,0xE0,0x01,0x78,0x00,0x1E,0x00,0x06,0x00,0x00,0x00},/*"/",14*/ +{0xF8,0x07,0xFC,0x0F,0x06,0x18,0xC2,0x10,0xC2,0x10,0x06,0x18,0xFC,0x0F,0xF8,0x07},/*"0",15*/ +{0x00,0x00,0x08,0x10,0x0C,0x10,0xFE,0x1F,0xFE,0x1F,0x00,0x10,0x00,0x10,0x00,0x00},/*"1",16*/ +{0x04,0x1C,0x06,0x1E,0x02,0x13,0x82,0x11,0xC2,0x10,0x62,0x10,0x3E,0x18,0x1C,0x18},/*"2",17*/ +{0x04,0x08,0x06,0x18,0x02,0x10,0x42,0x10,0x42,0x10,0x42,0x10,0xFE,0x1F,0xBC,0x0F},/*"3",18*/ +{0xC0,0x01,0xE0,0x01,0x30,0x01,0x18,0x01,0x0C,0x11,0xFE,0x1F,0xFE,0x1F,0x00,0x11},/*"4",19*/ +{0x7E,0x08,0x7E,0x18,0x42,0x10,0x42,0x10,0x42,0x10,0x42,0x10,0xC2,0x1F,0x82,0x0F},/*"5",20*/ +{0xF8,0x0F,0xFC,0x1F,0x46,0x10,0x42,0x10,0x42,0x10,0x42,0x10,0xC0,0x1F,0x80,0x0F},/*"6",21*/ +{0x06,0x00,0x06,0x00,0x02,0x00,0x02,0x1F,0xC2,0x1F,0xF2,0x00,0x3E,0x00,0x0E,0x00},/*"7",22*/ +{0xBC,0x0F,0xFE,0x1F,0x42,0x10,0x42,0x10,0x42,0x10,0x42,0x10,0xFE,0x1F,0xBC,0x0F},/*"8",23*/ +{0x3C,0x00,0x7E,0x10,0x42,0x10,0x42,0x10,0x42,0x10,0x42,0x18,0xFE,0x0F,0xFC,0x07},/*"9",24*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x0C,0x30,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ +{0x00,0x00,0x00,0x00,0x00,0x20,0x60,0x3C,0x60,0x1C,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ +{0x80,0x00,0xC0,0x01,0x60,0x03,0x30,0x06,0x18,0x0C,0x0C,0x18,0x04,0x10,0x00,0x00},/*"<",28*/ +{0x40,0x02,0x40,0x02,0x40,0x02,0x40,0x02,0x40,0x02,0x40,0x02,0x40,0x02,0x40,0x02},/*"=",29*/ +{0x04,0x10,0x0C,0x18,0x18,0x0C,0x30,0x06,0x60,0x03,0xC0,0x01,0x80,0x00,0x00,0x00},/*">",30*/ +{0x04,0x00,0x06,0x00,0x02,0x00,0x82,0x1B,0xC2,0x1B,0x62,0x00,0x3E,0x00,0x1C,0x00},/*"?",31*/ +{0xFC,0x0F,0xFE,0x1F,0x02,0x10,0x82,0x11,0xC2,0x13,0xE2,0x13,0xFE,0x13,0xFC,0x03},/*"@",32*/ +{0xF0,0x1F,0xF8,0x1F,0x0C,0x01,0x06,0x01,0x06,0x01,0x0C,0x01,0xF8,0x1F,0xF0,0x1F},/*"A",33*/ +{0x02,0x10,0xFE,0x1F,0xFE,0x1F,0x42,0x10,0x42,0x10,0x42,0x10,0xFE,0x1F,0xBC,0x0F},/*"B",34*/ +{0xF8,0x07,0xFC,0x0F,0x06,0x18,0x02,0x10,0x02,0x10,0x02,0x10,0x06,0x18,0x0C,0x0C},/*"C",35*/ +{0x02,0x10,0xFE,0x1F,0xFE,0x1F,0x02,0x10,0x02,0x10,0x06,0x18,0xFC,0x0F,0xF8,0x07},/*"D",36*/ +{0x02,0x10,0xFE,0x1F,0xFE,0x1F,0x42,0x10,0x42,0x10,0xE2,0x10,0x06,0x18,0x06,0x18},/*"E",37*/ +{0x02,0x10,0xFE,0x1F,0xFE,0x1F,0x42,0x10,0x42,0x00,0xE2,0x00,0x06,0x00,0x06,0x00},/*"F",38*/ +{0xF8,0x07,0xFC,0x0F,0x06,0x18,0x02,0x10,0x82,0x10,0x82,0x10,0x86,0x0F,0x8C,0x1F},/*"G",39*/ +{0xFE,0x1F,0xFE,0x1F,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0xFE,0x1F,0xFE,0x1F},/*"H",40*/ +{0x00,0x00,0x02,0x10,0x02,0x10,0xFE,0x1F,0xFE,0x1F,0x02,0x10,0x02,0x10,0x00,0x00},/*"I",41*/ +{0x00,0x0C,0x00,0x1C,0x00,0x10,0x00,0x10,0x02,0x10,0xFE,0x1F,0xFE,0x0F,0x02,0x00},/*"J",42*/ +{0x02,0x10,0xFE,0x1F,0xFE,0x1F,0xE0,0x00,0xB0,0x01,0x18,0x03,0x0E,0x1E,0x06,0x1C},/*"K",43*/ +{0x02,0x10,0xFE,0x1F,0xFE,0x1F,0x02,0x10,0x00,0x10,0x00,0x10,0x00,0x18,0x00,0x18},/*"L",44*/ +{0xFE,0x1F,0xFE,0x1F,0x18,0x00,0xF0,0x00,0xF0,0x00,0x18,0x00,0xFE,0x1F,0xFE,0x1F},/*"M",45*/ +{0xFE,0x1F,0xFE,0x1F,0x38,0x00,0x70,0x00,0xE0,0x00,0xC0,0x01,0xFE,0x1F,0xFE,0x1F},/*"N",46*/ +{0xFC,0x0F,0xFE,0x1F,0x02,0x10,0x02,0x10,0x02,0x10,0x02,0x10,0xFE,0x1F,0xFC,0x0F},/*"O",47*/ +{0x02,0x10,0xFE,0x1F,0xFE,0x1F,0x42,0x10,0x42,0x00,0x42,0x00,0x7E,0x00,0x3C,0x00},/*"P",48*/ +{0xFC,0x0F,0xFE,0x1F,0x02,0x10,0x02,0x1C,0x02,0x38,0x02,0x70,0xFE,0x5F,0xFC,0x0F},/*"Q",49*/ +{0x02,0x10,0xFE,0x1F,0xFE,0x1F,0x42,0x00,0x42,0x00,0xC2,0x00,0xFE,0x1F,0x3C,0x1F},/*"R",50*/ +{0x1C,0x0C,0x3E,0x1C,0x62,0x10,0x42,0x10,0x42,0x10,0xC2,0x10,0x8E,0x1F,0x0C,0x0F},/*"S",51*/ +{0x06,0x00,0x06,0x00,0x02,0x10,0xFE,0x1F,0xFE,0x1F,0x02,0x10,0x06,0x00,0x06,0x00},/*"T",52*/ +{0xFE,0x0F,0xFE,0x1F,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0xFE,0x1F,0xFE,0x0F},/*"U",53*/ +{0xFE,0x03,0xFE,0x07,0x00,0x0C,0x00,0x18,0x00,0x18,0x00,0x0C,0xFE,0x07,0xFE,0x03},/*"V",54*/ +{0xFE,0x07,0xFE,0x1F,0x00,0x1C,0xC0,0x07,0xC0,0x07,0x00,0x1C,0xFE,0x1F,0xFE,0x07},/*"W",55*/ +{0x0E,0x1C,0x1E,0x1E,0x30,0x03,0xE0,0x01,0xE0,0x01,0x30,0x03,0x1E,0x1E,0x0E,0x1C},/*"X",56*/ +{0x1E,0x00,0x3E,0x00,0x60,0x10,0xC0,0x1F,0xC0,0x1F,0x60,0x10,0x3E,0x00,0x1E,0x00},/*"Y",57*/ +{0x06,0x1E,0x06,0x1F,0x82,0x11,0xC2,0x10,0x62,0x10,0x32,0x10,0x1E,0x18,0x0E,0x18},/*"Z",58*/ +{0x00,0x00,0x00,0x00,0xFE,0x1F,0xFE,0x1F,0x02,0x10,0x02,0x10,0x00,0x00,0x00,0x00},/*"[",59*/ +{0x00,0x18,0x00,0x1E,0x80,0x07,0xE0,0x01,0x78,0x00,0x1E,0x00,0x06,0x00,0x00,0x00},/*"/",60*/ +{0x00,0x00,0x00,0x00,0x02,0x10,0x02,0x10,0xFE,0x1F,0xFE,0x1F,0x00,0x00,0x00,0x00},/*"]",61*/ +{0x20,0x00,0x30,0x00,0x18,0x00,0x0C,0x00,0x18,0x00,0x30,0x00,0x20,0x00,0x00,0x00},/*"^",62*/ +{0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80},/*"_",63*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x00,0x78,0x00,0x40,0x00,0x00,0x00,0x00,0x00},/*"`",64*/ +{0x00,0x0E,0x20,0x1F,0x20,0x11,0x20,0x11,0x20,0x11,0xE0,0x0F,0xC0,0x1F,0x00,0x10},/*"a",65*/ +{0x02,0x10,0xFE,0x1F,0xFE,0x0F,0x20,0x10,0x20,0x10,0x60,0x10,0xC0,0x1F,0x80,0x0F},/*"b",66*/ +{0xC0,0x0F,0xE0,0x1F,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0x60,0x18,0x40,0x08},/*"c",67*/ +{0x80,0x0F,0xC0,0x1F,0x60,0x10,0x20,0x10,0x22,0x10,0xFE,0x0F,0xFE,0x1F,0x00,0x10},/*"d",68*/ +{0xC0,0x0F,0xE0,0x1F,0x20,0x11,0x20,0x11,0x20,0x11,0x20,0x11,0xE0,0x19,0xC0,0x09},/*"e",69*/ +{0x00,0x00,0x20,0x10,0xFC,0x1F,0xFE,0x1F,0x22,0x10,0x22,0x00,0x06,0x00,0x04,0x00},/*"f",70*/ +{0xC0,0x4F,0xE0,0xDF,0x20,0x90,0x20,0x90,0x20,0x90,0xC0,0xFF,0xE0,0x7F,0x20,0x00},/*"g",71*/ +{0x02,0x10,0xFE,0x1F,0xFE,0x1F,0x40,0x00,0x20,0x00,0x20,0x00,0xE0,0x1F,0xC0,0x1F},/*"h",72*/ +{0x00,0x00,0x20,0x10,0x20,0x10,0xEC,0x1F,0xEC,0x1F,0x00,0x10,0x00,0x10,0x00,0x00},/*"i",73*/ +{0x00,0x60,0x00,0xC0,0x20,0x80,0x20,0x80,0xEC,0xFF,0xEC,0x7F,0x00,0x00,0x00,0x00},/*"j",74*/ +{0x02,0x10,0xFE,0x1F,0xFE,0x1F,0x80,0x01,0x80,0x03,0xC0,0x06,0x60,0x1C,0x20,0x18},/*"k",75*/ +{0x00,0x00,0x02,0x10,0x02,0x10,0xFE,0x1F,0xFE,0x1F,0x00,0x10,0x00,0x10,0x00,0x00},/*"l",76*/ +{0xE0,0x1F,0xE0,0x1F,0x60,0x00,0xC0,0x0F,0xC0,0x0F,0x60,0x00,0xE0,0x1F,0xC0,0x1F},/*"m",77*/ +{0x20,0x00,0xE0,0x1F,0xC0,0x1F,0x20,0x00,0x20,0x00,0x20,0x00,0xE0,0x1F,0xC0,0x1F},/*"n",78*/ +{0xC0,0x0F,0xE0,0x1F,0x20,0x10,0x20,0x10,0x20,0x10,0x20,0x10,0xE0,0x1F,0xC0,0x0F},/*"o",79*/ +{0x20,0x80,0xE0,0xFF,0xC0,0xFF,0x20,0x90,0x20,0x10,0x20,0x10,0xE0,0x1F,0xC0,0x0F},/*"p",80*/ +{0xC0,0x0F,0xE0,0x1F,0x20,0x10,0x20,0x10,0x20,0x90,0xC0,0xFF,0xE0,0xFF,0x20,0x80},/*"q",81*/ +{0x20,0x10,0xE0,0x1F,0xC0,0x1F,0x60,0x10,0x20,0x00,0x20,0x00,0x60,0x00,0x40,0x00},/*"r",82*/ +{0xC0,0x08,0xE0,0x19,0x20,0x11,0x20,0x11,0x20,0x13,0x20,0x12,0x60,0x1E,0x40,0x0C},/*"s",83*/ +{0x20,0x00,0x20,0x00,0xFC,0x0F,0xFE,0x1F,0x20,0x10,0x20,0x18,0x00,0x08,0x00,0x00},/*"t",84*/ +{0xE0,0x0F,0xE0,0x1F,0x00,0x10,0x00,0x10,0x00,0x10,0xE0,0x0F,0xE0,0x1F,0x00,0x10},/*"u",85*/ +{0xE0,0x03,0xE0,0x07,0x00,0x0C,0x00,0x18,0x00,0x18,0x00,0x0C,0xE0,0x07,0xE0,0x03},/*"v",86*/ +{0xE0,0x0F,0xE0,0x1F,0x00,0x18,0x00,0x0F,0x00,0x0F,0x00,0x18,0xE0,0x1F,0xE0,0x0F},/*"w",87*/ +{0x20,0x10,0x60,0x18,0xC0,0x0C,0x80,0x07,0x80,0x07,0xC0,0x0C,0x60,0x18,0x20,0x10},/*"x",88*/ +{0xE0,0x8F,0xE0,0x9F,0x00,0x90,0x00,0x90,0x00,0x90,0x00,0xD0,0xE0,0x7F,0xE0,0x3F},/*"y",89*/ +{0x60,0x18,0x60,0x1C,0x20,0x16,0x20,0x13,0xA0,0x11,0xE0,0x10,0x60,0x18,0x20,0x18},/*"z",90*/ +{0x00,0x00,0x00,0x00,0x80,0x00,0xFC,0x1F,0x7E,0x3F,0x02,0x20,0x02,0x20,0x00,0x00},/*"{",91*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x3E,0x7C,0x3E,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/ +{0x00,0x00,0x02,0x20,0x02,0x20,0x7E,0x3F,0xFC,0x1F,0x80,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ +}; +#endif + +void LCD_Common::printInt(uint16_t value, int8_t padding) +{ + uint16_t den = 10000; + for (int8_t i = 5; i > 0; i--) { + byte v = (byte)(value / den); + value -= v * den; + den /= 10; + if (v == 0 && padding && den) { + if (padding >= i) { + writeDigit((m_flags & FLAG_PAD_ZERO) ? 0 : -1); + } + continue; + } + padding = 0; + writeDigit(v); + } +} + +void LCD_Common::printLong(uint32_t value, int8_t padding) +{ + uint32_t den = 1000000000; + for (int8_t i = 10; i > 0; i--) { + byte v = (byte)(value / den); + value -= v * den; + den /= 10; + if (v == 0 && padding && den) { + if (padding >= i) { + writeDigit((m_flags & FLAG_PAD_ZERO) ? 0 : -1); + } + continue; + } + padding = 0; + writeDigit(v); + } +} + +void LCD_SSD1306::setCursor(byte column, byte line) +{ + m_col = column; + m_row = line; + ssd1306_command(0xB0 + m_row);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address +} + +size_t LCD_SSD1306::write(uint8_t c) +{ + if (c == '\n') { + setCursor(0, m_row + ((m_font == FONT_SIZE_SMALL) ? 1 : 2)); + return 1; + } else if (c == '\r') { + m_col = 0; + return 1; + } +#ifdef TWBR + uint8_t twbrbackup = TWBR; + TWBR = 18; // upgrade to 400KHz! +#endif +#ifndef MEMORY_SAVING + if (m_font == FONT_SIZE_SMALL) { +#endif + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + if (c > 0x20 && c < 0x7f) { + c -= 0x21; + for (byte i = 0; i < 5; i++) { + byte d = pgm_read_byte(&font5x8[c][i]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + WIRE_WRITE(0); + } else { + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 11 : 6; i > 0; i--) { + WIRE_WRITE(0); + } + } + Wire.endTransmission(); + m_col += (m_flags & FLAG_PIXEL_DOUBLE_H) ? 11 : 6; + if (m_col >= 128) { + m_col = 0; + m_row ++; + } +#ifndef MEMORY_SAVING + } else { + if (c > 0x20 && c < 0x7f) { + c -= 0x21; + + ssd1306_command(0xB0 + m_row);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (byte i = 0; i <= 14; i += 2) { + byte d = pgm_read_byte(&font8x16_terminal[c][i]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + + ssd1306_command(0xB0 + m_row + 1);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (byte i = 1; i <= 15; i += 2) { + byte d = pgm_read_byte(&font8x16_terminal[c][i]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + } else { + ssd1306_command(0xB0 + m_row);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 16 : 8; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + + ssd1306_command(0xB0 + m_row + 1);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 16 : 8; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + } + m_col += (m_flags & FLAG_PIXEL_DOUBLE_H) ? 17 : 9; + if (m_col >= 128) { + m_col = 0; + m_row += 2; + } + } +#endif +#ifdef TWBR + TWBR = twbrbackup; +#endif + return 1; +} + +void LCD_SSD1306::writeDigit(byte n) +{ +#ifdef TWBR + uint8_t twbrbackup = TWBR; + TWBR = 18; // upgrade to 400KHz! +#endif + if (m_font == FONT_SIZE_SMALL) { + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + if (n <= 9) { + n += '0' - 0x21; + for (byte i = 0; i < 5; i++) { + WIRE_WRITE(pgm_read_byte(&font5x8[n][i])); + } + WIRE_WRITE(0); + } else { + for (byte i = 0; i < 6; i++) { + WIRE_WRITE(0); + } + } + Wire.endTransmission(); + m_col += 6; + } else if (m_font == FONT_SIZE_MEDIUM) { + write(n <= 9 ? ('0' + n) : ' '); +#ifndef MEMORY_SAVING + } else if (m_font == FONT_SIZE_LARGE) { + if (n <= 9) { + byte i; + ssd1306_command(0xB0 + m_row);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (i = 0; i < 16; i ++) { + byte d = pgm_read_byte(&digits16x16[n][i]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + + ssd1306_command(0xB0 + m_row + 1);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (; i < 32; i ++) { + byte d = pgm_read_byte(&digits16x16[n][i]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + } else { + ssd1306_command(0xB0 + m_row);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 32 : 16; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + + ssd1306_command(0xB0 + m_row + 1);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 32 : 16; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + } + m_col += (m_flags & FLAG_PIXEL_DOUBLE_H) ? 30 : 16; +#endif + } else { + if (n <= 9) { + byte i; + ssd1306_command(0xB0 + m_row);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (i = 0; i < 16; i ++) { + byte d = pgm_read_byte(&digits16x24[n][i * 3]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + + ssd1306_command(0xB0 + m_row + 1);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (i = 0; i < 16; i ++) { + byte d = pgm_read_byte(&digits16x24[n][i * 3 + 1]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + + ssd1306_command(0xB0 + m_row + 2);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (i = 0; i < 16; i ++) { + byte d = pgm_read_byte(&digits16x24[n][i * 3 + 2]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + } else { + ssd1306_command(0xB0 + m_row);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 32 : 16; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + + ssd1306_command(0xB0 + m_row + 1);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 32 : 16; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + + ssd1306_command(0xB0 + m_row + 2);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 32 : 16; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + } + m_col += (m_flags & FLAG_PIXEL_DOUBLE_H) ? 30 : 16; + } +#ifdef TWBR + TWBR = twbrbackup; +#endif +} + +void LCD_SSD1306::draw(const PROGMEM byte* buffer, byte width, byte height) +{ + ssd1306_command(SSD1306_SETLOWCOLUMN | 0x0); // low col = 0 + ssd1306_command(SSD1306_SETHIGHCOLUMN | 0x0); // hi col = 0 + ssd1306_command(SSD1306_SETSTARTLINE | 0x0); // line #0 + + const PROGMEM byte *p = buffer; + height >>= 3; + width >>= 3; +#ifdef TWBR + uint8_t twbrbackup = TWBR; + TWBR = 18; // upgrade to 400KHz! +#endif + for (byte i = 0; i < height; i++) { + // send a bunch of data in one xmission + ssd1306_command(0xB0 + i + m_row);//set page address + ssd1306_command(m_col & 0xf);//set lower column address + ssd1306_command(0x10 | (m_col >> 4));//set higher column address + + for(byte j = 0; j < 8; j++){ + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (byte k = 0; k < width; k++, p++) { + WIRE_WRITE(pgm_read_byte(p)); + } + Wire.endTransmission(); + } + } + m_col += width; +#ifdef TWBR + TWBR = twbrbackup; +#endif +} + +void LCD_SSD1306::clearLine(byte line) +{ + ssd1306_command(SSD1306_SETLOWCOLUMN | 0x0); // low col = 0 + ssd1306_command(SSD1306_SETHIGHCOLUMN | 0x0); // hi col = 0 + ssd1306_command(SSD1306_SETSTARTLINE | 0x0); // line #0 + +#ifdef TWBR + uint8_t twbrbackup = TWBR; + TWBR = 18; // upgrade to 400KHz! +#endif + + // send a bunch of data in one xmission + ssd1306_command(0xB0 + line);//set page address + ssd1306_command(0);//set lower column address + ssd1306_command(0x10);//set higher column address + + for(byte j = 0; j < 8; j++){ + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (byte k = 0; k < 16; k++) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + } +#ifdef TWBR + TWBR = twbrbackup; +#endif +} + +void LCD_SSD1306::setContrast(byte Contrast) +{ +return; // BUGBUG + ssd1306_command(SSD1306_SETCONTRAST); + ssd1306_command(Contrast); +} diff --git a/hardware/digistump/avr/libraries/MicrOledPro/MicrOledPro.h b/hardware/digistump/avr/libraries/MicrOledPro/MicrOledPro.h new file mode 100644 index 0000000..30278ed --- /dev/null +++ b/hardware/digistump/avr/libraries/MicrOledPro/MicrOledPro.h @@ -0,0 +1,126 @@ +/************************************************************************* +* Arduino Text & Bitmap Display Library for multiple models of monochrome LCD display +* Distributed under GPL v2.0 +* Copyright (c) 2013-2014 Stanley Huang +* All rights reserved. +* For more information, please visit http://arduinodev.com +*************************************************************************/ + +//#include + #if ARDUINO >= 100 + #include "Arduino.h" + #define WIRE_WRITE Wire.write +#else + #include "WProgram.h" + #define WIRE_WRITE Wire.send +#endif + +// #define MEMORY_SAVING + +typedef enum { + FONT_SIZE_SMALL = 0, + FONT_SIZE_MEDIUM, + FONT_SIZE_LARGE, + FONT_SIZE_XLARGE +} FONT_SIZE; + +#define FLAG_PAD_ZERO 1 +#define FLAG_PIXEL_DOUBLE_H 2 +#define FLAG_PIXEL_DOUBLE_V 4 +#define FLAG_PIXEL_DOUBLE (FLAG_PIXEL_DOUBLE_H | FLAG_PIXEL_DOUBLE_V) + +extern const PROGMEM unsigned char font5x8[][5]; +extern const PROGMEM unsigned char digits8x8[][8] ; +extern const PROGMEM unsigned char digits16x16[][32]; +extern const PROGMEM unsigned char digits16x24[][48]; +extern const PROGMEM unsigned char font8x16_doslike[][16]; +extern const PROGMEM unsigned char font8x16_terminal[][16]; + +class LCD_Common +{ +public: + LCD_Common():m_font(FONT_SIZE_SMALL),m_flags(0) {} + void setFontSize(FONT_SIZE size) { m_font = size; } + void setFlags(byte flags) { m_flags = flags; } + virtual void backlight(bool on) {} + virtual void draw(const PROGMEM byte* buffer, byte width, byte height) {} + void printInt(uint16_t value, int8_t padding = -1); + void printLong(uint32_t value, int8_t padding = -1); +protected: + virtual void writeDigit(byte n) {} + byte m_font; + byte m_flags; +}; + +class LCD_Null : public LCD_Common, public Print +{ +public: + byte getLines() { return 0; } + byte getCols() { return 0; } + void clearLine(byte line) {} + void clear() {} + void begin() {} + void setCursor(byte column, byte line) {} + size_t write(uint8_t c) { return 0; } +}; + +#include "SSD1306.h" + +class LCD_SSD1306 : public LCD_Common, public SSD1306, public Print +{ +public: + void setCursor(byte column, byte line); + void setContrast(byte Contrast); + void draw(const PROGMEM byte* buffer, byte width, byte height); + size_t write(uint8_t c); +// void clear(byte x = 0, byte y = 0, byte width = 128, byte height = 64); + void clearLine(byte line); + byte getLines() { return 21; } + byte getCols() { return 8; } +private: + void writeDigit(byte n); + byte m_col; + byte m_row; +}; + +class LCD_SH1106 : public LCD_Common, public Print +{ +public: + void begin(); + void setCursor(byte column, byte line); + void draw(const PROGMEM byte* buffer, byte width, byte height); + size_t write(uint8_t c); + void clear(byte x = 0, byte y = 0, byte width = 128, byte height = 64); + void clearLine(byte line); + byte getLines() { return 21; } + byte getCols() { return 8; } +private: + void WriteCommand(unsigned char ins); + void WriteData(unsigned char dat); + void writeDigit(byte n); + byte m_col; + byte m_row; +}; + +#include "PCD8544.h" + +class LCD_PCD8544 : public LCD_Common, public PCD8544 +{ +public: + byte getLines() { return 6; } + byte getCols() { return 14; } + void backlight(bool on) + { + pinMode(7, OUTPUT); + digitalWrite(7, on ? HIGH : LOW); + } + void clearLine(byte line) + { + setCursor(0, line); + for (byte i = 14; i > 0; i--) write(' '); + } + void draw(const PROGMEM byte* buffer, byte width, byte height); +private: + void writeDigit(byte n); +}; + diff --git a/hardware/digistump/avr/libraries/MicrOledPro/PCD8544.cpp b/hardware/digistump/avr/libraries/MicrOledPro/PCD8544.cpp new file mode 100644 index 0000000..6b339fe --- /dev/null +++ b/hardware/digistump/avr/libraries/MicrOledPro/PCD8544.cpp @@ -0,0 +1,316 @@ +/* + * PCD8544 - Interface with Philips PCD8544 (or compatible) LCDs. + * + * Copyright (c) 2010 Carlos Rodrigues + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + +#include "PCD8544.h" + +#include +#include + +extern const PROGMEM unsigned char font5x8[][5]; + +/* + * If this was a ".h", it would get added to sketches when using + * the "Sketch -> Import Library..." menu on the Arduino IDE... + */ + +PCD8544::PCD8544(unsigned char sclk, unsigned char sdin, + unsigned char dc, unsigned char reset, + unsigned char sce): + pin_sclk(sclk), + pin_sdin(sdin), + pin_dc(dc), + pin_reset(reset), + pin_sce(sce) +{} + + +void PCD8544::begin(unsigned char model) +{ + this->column = 0; + this->line = 0; + + // Sanitize the custom glyphs... + memset(this->custom, 0, sizeof(this->custom)); + + // All pins are outputs (these displays cannot be read)... + pinMode(this->pin_sclk, OUTPUT); + pinMode(this->pin_sdin, OUTPUT); + pinMode(this->pin_dc, OUTPUT); + pinMode(this->pin_reset, OUTPUT); + pinMode(this->pin_sce, OUTPUT); + + // Reset the controller state... + digitalWrite(this->pin_reset, HIGH); + digitalWrite(this->pin_sce, HIGH); + digitalWrite(this->pin_reset, LOW); + delay(100); + digitalWrite(this->pin_reset, HIGH); + + // Set the LCD parameters... + this->send(PCD8544_CMD, 0x21); // extended instruction set control (H=1) + this->send(PCD8544_CMD, 0x13); // bias system (1:48) + + if (model == CHIP_ST7576) { + this->send(PCD8544_CMD, 0xe0); // higher Vop, too faint at default + this->send(PCD8544_CMD, 0x05); // partial display mode + } else { + this->send(PCD8544_CMD, 0xc2); // default Vop (3.06 + 66 * 0.06 = 7V) + } + + this->send(PCD8544_CMD, 0x20); // extended instruction set control (H=0) + this->send(PCD8544_CMD, 0x09); // all display segments on + + // Clear RAM contents... + this->clear(); + + // Activate LCD... + this->send(PCD8544_CMD, 0x08); // display blank + this->send(PCD8544_CMD, 0x0c); // normal mode (0x0d = inverse mode) + delay(100); + + // Place the cursor at the origin... + this->send(PCD8544_CMD, 0x80); + this->send(PCD8544_CMD, 0x40); +} + + +void PCD8544::stop() +{ + this->clear(); + this->setPower(false); +} + + +void PCD8544::clear() +{ + this->setCursor(0, 0); + + for (unsigned short i = 0; i < PCD8544_WIDTH * (PCD8544_HEIGHT/8); i++) { + this->send(PCD8544_DATA, 0x00); + } + + this->setCursor(0, 0); +} + + +void PCD8544::clearLine() +{ + this->setCursor(0, this->line); + + for (unsigned char i = 0; i < PCD8544_WIDTH; i++) { + this->send(PCD8544_DATA, 0x00); + } + + this->setCursor(0, this->line); +} + + +void PCD8544::setPower(bool on) +{ + this->send(PCD8544_CMD, on ? 0x20 : 0x24); +} + + +inline void PCD8544::display() +{ + this->setPower(true); +} + + +inline void PCD8544::noDisplay() +{ + this->setPower(false); +} + + +void PCD8544::setInverse(bool inverse) +{ + this->send(PCD8544_CMD, inverse ? 0x0d : 0x0c); +} + + +void PCD8544::home() +{ + this->setCursor(0, this->line); +} + + +void PCD8544::setCursor(unsigned char column, unsigned char line) +{ + if (column > PCD8544_WIDTH) { + column = 0; + line++; + } + if (line > PCD8544_HEIGHT / 8) + line = 0; + + this->column = column; + this->line = line; + + this->send(PCD8544_CMD, 0x80 | column); + this->send(PCD8544_CMD, 0x40 | line); +} + + +void PCD8544::createChar(unsigned char chr, const unsigned char *glyph) +{ + // ASCII 0-31 only... + if (chr >= ' ') { + return; + } + + this->custom[chr] = glyph; +} + + +size_t PCD8544::write(uint8_t chr) +{ + // ASCII 7-bit only... + if (chr >= 0x7f) { + return 0; + } + + if (chr == '\n') { + column = 0; + line = (line + 1) % (PCD8544_HEIGHT/9 + 1); + return 0; + } else if (chr == '\r') { + column = 0; + return 0; + } + + const unsigned char *glyph; + unsigned char pgm_buffer[5]; + + if (chr >= ' ') { + // Regular ASCII characters are kept in flash to save RAM... + memcpy_P(pgm_buffer, &font5x8[chr - ' '], sizeof(pgm_buffer)); + glyph = pgm_buffer; + } else { + // Custom glyphs, on the other hand, are stored in RAM... + if (custom[chr]) { + glyph = custom[chr]; + } else { + // Default to a space character if unset... + memcpy_P(pgm_buffer, &font5x8[0], sizeof(pgm_buffer)); + glyph = pgm_buffer; + } + } + + // Output one column at a time... + for (unsigned char i = 0; i < 5; i++) { + this->send(PCD8544_DATA, glyph[i]); + } + + // One column between characters... + this->send(PCD8544_DATA, 0x00); + + // Update the cursor position... + this->column = (this->column + 6) % PCD8544_WIDTH; + + if (this->column == 0) { + this->line = (this->line + 1) % (PCD8544_HEIGHT/9 + 1); + } + +#if ARDUINO >= 100 + return 1; +#endif +} + +void PCD8544::draw8x8(const unsigned char *data) +{ + // Output one column at a time... + for (unsigned char i = 0; i < 8; i++) { + this->send(PCD8544_DATA, data[i]); + } + this->setCursor(column + 8, line); +} + +void PCD8544::draw16x16(const unsigned char *data) +{ + unsigned char scolumn = this->column; + unsigned char sline = this->line; + // Output one column at a time... + for (unsigned char i = 0; i < 16; i++) { + this->send(PCD8544_DATA, data[i]); + } + this->setCursor(scolumn, sline + 1); + for (unsigned char i = 0; i < 16; i++) { + this->send(PCD8544_DATA, data[i + 16]); + } + // Update the cursor position... + this->setCursor(scolumn + 16, sline); +} + +void PCD8544::drawColumn(unsigned char lines, unsigned char value) +{ + unsigned char scolumn = this->column; + unsigned char sline = this->line; + + // Keep "value" within range... + if (value > lines*8) { + value = lines*8; + } + + // Find the line where "value" resides... + unsigned char mark = (lines*8 - 1 - value)/8; + + // Clear the lines above the mark... + for (unsigned char line = 0; line < mark; line++) { + this->setCursor(scolumn, sline + line); + this->send(PCD8544_DATA, 0x00); + } + + // Compute the byte to draw at the "mark" line... + unsigned char b = 0xff; + for (unsigned char i = 0; i < lines*8 - mark*8 - value; i++) { + b <<= 1; + } + + this->setCursor(scolumn, sline + mark); + this->send(PCD8544_DATA, b); + + // Fill the lines below the mark... + for (unsigned char line = mark + 1; line < lines; line++) { + this->setCursor(scolumn, sline + line); + this->send(PCD8544_DATA, 0xff); + } + + // Leave the cursor in a consistent position... + this->setCursor(scolumn + 1, sline); +} + + +void PCD8544::send(unsigned char type, unsigned char data) +{ + digitalWrite(this->pin_dc, type); + + digitalWrite(this->pin_sce, LOW); + shiftOut(this->pin_sdin, this->pin_sclk, MSBFIRST, data); + digitalWrite(this->pin_sce, HIGH); +} + + +/* vim: set expandtab ts=4 sw=4: */ diff --git a/hardware/digistump/avr/libraries/MicrOledPro/PCD8544.h b/hardware/digistump/avr/libraries/MicrOledPro/PCD8544.h new file mode 100644 index 0000000..c96bc7e --- /dev/null +++ b/hardware/digistump/avr/libraries/MicrOledPro/PCD8544.h @@ -0,0 +1,117 @@ +/* + * PCD8544 - Interface with Philips PCD8544 (or compatible) LCDs. + * + * Copyright (c) 2010 Carlos Rodrigues + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + +#ifndef PCD8544_H +#define PCD8544_H + + +#if ARDUINO < 100 +#include +#else +#include +#endif + +// Chip variants supported... +#define CHIP_PCD8544 0 +#define CHIP_ST7576 1 + +#define PCD8544_WIDTH 84 +#define PCD8544_HEIGHT 48 + +#define PCD8544_CMD LOW +#define PCD8544_DATA HIGH + +class PCD8544: public Print { + public: + // All the pins can be changed from the default values... + PCD8544(unsigned char sclk = 2, /* clock (display pin 2) */ + unsigned char sdin = 3, /* data-in (display pin 3) */ + unsigned char dc = 4, /* data select (display pin 4) */ + unsigned char reset = 6, /* reset (display pin 8) */ + unsigned char sce = 5); /* enable (display pin 5) */ + + // Display initialization (dimensions in pixels)... + void begin(unsigned char model=CHIP_PCD8544); + void stop(); + + // Erase everything on the display... + void clear(); + void clearLine(); // ...or just the current line + + // Control the display's power state... + void setPower(bool on); + + // For compatibility with the LiquidCrystal library... + void display(); + void noDisplay(); + + // Activate white-on-black mode (whole display)... + void setInverse(bool inverse); + + // Place the cursor at the start of the current line... + void home(); + + // Place the cursor at position (column, line)... + void setCursor(unsigned char column, unsigned char line); + + // Assign a user-defined glyph (5x8) to an ASCII character (0-31)... + void createChar(unsigned char chr, const unsigned char *glyph); + + // Write an ASCII character at the current cursor position (7-bit)... +#if ARDUINO < 100 + virtual void write(uint8_t chr); +#else + virtual size_t write(uint8_t chr); +#endif + + // Draw a chart element at the current cursor position... + void drawColumn(unsigned char lines, unsigned char value); + + void draw8x8(const unsigned char *data); + void draw16x16(const unsigned char *data); + + protected: + // Current cursor position... + unsigned char column; + unsigned char line; + // Send a command or data to the display... + void send(unsigned char type, unsigned char data); + + private: + unsigned char pin_sclk; + unsigned char pin_sdin; + unsigned char pin_dc; + unsigned char pin_reset; + unsigned char pin_sce; + + // User-defined glyphs (below the ASCII space character)... + const unsigned char *custom[' ']; +}; + + +#endif /* PCD8544_H */ + + +/* vim: set expandtab ts=4 sw=4: */ diff --git a/hardware/digistump/avr/libraries/MicrOledPro/README.md b/hardware/digistump/avr/libraries/MicrOledPro/README.md new file mode 100644 index 0000000..5a616c6 --- /dev/null +++ b/hardware/digistump/avr/libraries/MicrOledPro/README.md @@ -0,0 +1,4 @@ +MicrOledPro +=========== + +modified version of OLEDPRO, the 128x64 OLED lib (mainly aimed at digispark pro) diff --git a/hardware/digistump/avr/libraries/MicrOledPro/SH1106.cpp b/hardware/digistump/avr/libraries/MicrOledPro/SH1106.cpp new file mode 100644 index 0000000..e153ac2 --- /dev/null +++ b/hardware/digistump/avr/libraries/MicrOledPro/SH1106.cpp @@ -0,0 +1,420 @@ +//#include + #if ARDUINO >= 100 + #include "Arduino.h" + #define WIRE_WRITE Wire.write +#else + #include "WProgram.h" + #define WIRE_WRITE Wire.send +#endif +#include +#include "MicrOledPro.h" + +#define I2C_ADDR 0x78 >> 1 + +void LCD_SH1106::WriteCommand(unsigned char ins) +{ + Wire.beginTransmission(I2C_ADDR);//0x78 >> 1 + WIRE_WRITE(0x00);//0x00 + WIRE_WRITE(ins); + Wire.endTransmission(); +} + +void LCD_SH1106::WriteData(unsigned char dat) +{ + Wire.beginTransmission(I2C_ADDR);//0x78 >> 1 + WIRE_WRITE(0x40);//0x40 + WIRE_WRITE(dat); + Wire.endTransmission(); +} + +void LCD_SH1106::setCursor(unsigned char x, unsigned char y) +{ + m_col = x + 2; + m_row = y; + WriteCommand(0xb0 + m_row); + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address +} + +void LCD_SH1106::clear(byte x, byte y, byte width, byte height) +{ + WriteCommand(SSD1306_SETLOWCOLUMN | 0x0); // low col = 0 + WriteCommand(SSD1306_SETHIGHCOLUMN | 0x0); // hi col = 0 + WriteCommand(SSD1306_SETSTARTLINE | 0x0); // line #0 + + height >>= 3; + width >>= 3; + y >>= 3; +#ifdef TWBR + uint8_t twbrbackup = TWBR; + TWBR = 18; // upgrade to 400KHz! +#endif + for (byte i = 0; i < height; i++) { + // send a bunch of data in one xmission + WriteCommand(0xB0 + i + y);//set page address + WriteCommand((x + 2) & 0xf);//set lower column address + WriteCommand(0x10 | (x >> 4));//set higher column address + + for(byte j = 0; j < 8; j++){ + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (byte k = 0; k < width; k++) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + } + } +#ifdef TWBR + TWBR = twbrbackup; +#endif + setCursor(0, 0); +} + +size_t LCD_SH1106::write(uint8_t c) +{ + if (c == '\n') { + setCursor(0, m_row + ((m_font == FONT_SIZE_SMALL) ? 1 : 2)); + return 1; + } else if (c == '\r') { + m_col = 0; + return 1; + } + +#ifdef TWBR + uint8_t twbrbackup = TWBR; + TWBR = 18; // upgrade to 400KHz! +#endif +#ifndef MEMORY_SAVING + if (m_font == FONT_SIZE_SMALL) { +#endif + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + if (c > 0x20 && c < 0x7f) { + c -= 0x21; + for (byte i = 0; i < 5; i++) { + byte d = pgm_read_byte(&font5x8[c][i]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + WIRE_WRITE(0); + } else { + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 11 : 6; i > 0; i--) { + WIRE_WRITE(0); + } + } + Wire.endTransmission(); + m_col += (m_flags & FLAG_PIXEL_DOUBLE_H) ? 11 : 6; + if (m_col >= 128) { + m_col = 0; + m_row ++; + } +#ifndef MEMORY_SAVING + } else { + if (c > 0x20 && c < 0x7f) { + c -= 0x21; + + WriteCommand(0xB0 + m_row);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (byte i = 0; i <= 14; i += 2) { + byte d = pgm_read_byte(&font8x16_terminal[c][i]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + + WriteCommand(0xB0 + m_row + 1);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (byte i = 1; i <= 15; i += 2) { + byte d = pgm_read_byte(&font8x16_terminal[c][i]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + } else { + WriteCommand(0xB0 + m_row);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 16 : 8; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + + WriteCommand(0xB0 + m_row + 1);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 16 : 8; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + } + m_col += (m_flags & FLAG_PIXEL_DOUBLE_H) ? 17 : 9; + if (m_col >= 128) { + m_col = 0; + m_row += 2; + } + } +#endif +#ifdef TWBR + TWBR = twbrbackup; +#endif + return 1; +} + +void LCD_SH1106::writeDigit(byte n) +{ +#ifdef TWBR + uint8_t twbrbackup = TWBR; + TWBR = 18; // upgrade to 400KHz! +#endif + if (m_font == FONT_SIZE_SMALL) { + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + if (n <= 9) { + n += '0' - 0x21; + for (byte i = 0; i < 5; i++) { + WIRE_WRITE(pgm_read_byte(&font5x8[n][i])); + } + WIRE_WRITE(0); + } else { + for (byte i = 0; i < 6; i++) { + WIRE_WRITE(0); + } + } + Wire.endTransmission(); + m_col += 6; + } else if (m_font == FONT_SIZE_MEDIUM) { + write(n <= 9 ? ('0' + n) : ' '); +#ifndef MEMORY_SAVING + } else if (m_font == FONT_SIZE_LARGE) { + if (n <= 9) { + byte i; + WriteCommand(0xB0 + m_row);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (i = 0; i < 16; i ++) { + byte d = pgm_read_byte(&digits16x16[n][i]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + + WriteCommand(0xB0 + m_row + 1);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (; i < 32; i ++) { + byte d = pgm_read_byte(&digits16x16[n][i]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + } else { + WriteCommand(0xB0 + m_row);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 32 : 16; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + + WriteCommand(0xB0 + m_row + 1);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 32 : 16; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + } + m_col += (m_flags & FLAG_PIXEL_DOUBLE_H) ? 30 : 16; +#endif + } else { + if (n <= 9) { + byte i; + WriteCommand(0xB0 + m_row);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (i = 0; i < 16; i ++) { + byte d = pgm_read_byte(&digits16x24[n][i * 3]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + + WriteCommand(0xB0 + m_row + 1);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (i = 0; i < 16; i ++) { + byte d = pgm_read_byte(&digits16x24[n][i * 3 + 1]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + + WriteCommand(0xB0 + m_row + 2);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (i = 0; i < 16; i ++) { + byte d = pgm_read_byte(&digits16x24[n][i * 3 + 2]); + WIRE_WRITE(d); + if (m_flags & FLAG_PIXEL_DOUBLE_H) WIRE_WRITE(d); + } + Wire.endTransmission(); + } else { + WriteCommand(0xB0 + m_row);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 32 : 16; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + + WriteCommand(0xB0 + m_row + 1);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 32 : 16; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + + WriteCommand(0xB0 + m_row + 2);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (byte i = (m_flags & FLAG_PIXEL_DOUBLE_H) ? 32 : 16; i > 0; i--) { + WIRE_WRITE(0); + } + Wire.endTransmission(); + } + m_col += (m_flags & FLAG_PIXEL_DOUBLE_H) ? 30 : 16; + } +#ifdef TWBR + TWBR = twbrbackup; +#endif +} + +void LCD_SH1106::draw(const PROGMEM byte* buffer, byte width, byte height) +{ +#ifdef TWBR + uint8_t twbrbackup = TWBR; + TWBR = 18; // upgrade to 400KHz! +#endif + + WriteCommand(SSD1306_SETLOWCOLUMN | 0x0); // low col = 0 + WriteCommand(SSD1306_SETHIGHCOLUMN | 0x0); // hi col = 0 + WriteCommand(SSD1306_SETSTARTLINE | 0x0); // line #0 + + const PROGMEM byte *p = buffer; + height >>= 3; + width >>= 3; + for (byte i = 0; i < height; i++) { + // send a bunch of data in one xmission + WriteCommand(0xB0 + i + m_row);//set page address + WriteCommand(m_col & 0xf);//set lower column address + WriteCommand(0x10 | (m_col >> 4));//set higher column address + + for(byte j = 0; j < 8; j++){ + Wire.beginTransmission(I2C_ADDR); + WIRE_WRITE(0x40); + for (byte k = 0; k < width; k++, p++) { + WIRE_WRITE(pgm_read_byte(p)); + } + Wire.endTransmission(); + } + } +#ifdef TWBR + TWBR = twbrbackup; +#endif + m_col += width; +} + +void LCD_SH1106::begin() +{ + Wire.begin(); + + WriteCommand(0xAE); /*display off*/ + + WriteCommand(0x02); /*set lower column address*/ + WriteCommand(0x10); /*set higher column address*/ + + WriteCommand(0x40); /*set display start line*/ + + WriteCommand(0xB0); /*set page address*/ + + WriteCommand(0x81); /*contract control*/ + WriteCommand(0x80); /*128*/ + + WriteCommand(0xA1); /*set segment remap*/ + + WriteCommand(0xA6); /*normal / reverse*/ + + WriteCommand(0xA8); /*multiplex ratio*/ + WriteCommand(0x3F); /*duty = 1/32*/ + + WriteCommand(0xad); /*set charge pump enable*/ + WriteCommand(0x8b); /*external VCC */ + + WriteCommand(0x30); /*0X30---0X33 set VPP 9V liangdu!!!!*/ + + WriteCommand(0xC8); /*Com scan direction*/ + + WriteCommand(0xD3); /*set display offset*/ + WriteCommand(0x00); /* 0x20 */ + + WriteCommand(0xD5); /*set osc division*/ + WriteCommand(0x80); + + WriteCommand(0xD9); /*set pre-charge period*/ + WriteCommand(0x1f); /*0x22*/ + + WriteCommand(0xDA); /*set COM pins*/ + WriteCommand(0x12); + + WriteCommand(0xdb); /*set vcomh*/ + WriteCommand(0x40); + + WriteCommand(0xAF); /*display ON*/ + + clear(); +} diff --git a/hardware/digistump/avr/libraries/MicrOledPro/SSD1306.cpp b/hardware/digistump/avr/libraries/MicrOledPro/SSD1306.cpp new file mode 100644 index 0000000..a2185e4 --- /dev/null +++ b/hardware/digistump/avr/libraries/MicrOledPro/SSD1306.cpp @@ -0,0 +1,319 @@ +#include +#include +#include +#include +#include "SSD1306.h" + +SSD1306::SSD1306(int8_t SCLK, int8_t DC, int8_t RST, int8_t CS) { + cs = CS; + rst = RST; + dc = DC; + sclk = SCLK; +} + +// initializer for I2C - we only indicate the reset pin! + SSD1306::SSD1306(int8_t reset) { + sclk = dc = cs = -1; + rst = reset; +} + + +void SSD1306::begin(uint8_t vccstate, uint8_t i2caddr) { + _i2caddr = i2caddr; + + + // set pin directions + // Setup reset pin direction (used by both SPI and I2C) + pinMode(rst, OUTPUT); + + + // I2C Init + Wire.begin(); // Is this the right place for this? + + digitalWrite(rst, HIGH); + // VDD (3.3V) goes high at start, lets just chill for a ms + + delay(1); + // bring reset low + digitalWrite(rst, LOW); + // wait 10ms + delay(10); + // bring out of reset + digitalWrite(rst, HIGH); + + + // turn on VCC (9V?) + #if defined SSD1306_128_32 + // Init sequence for 128x32 OLED module + ssd1306_command(SSD1306_DISPLAYOFF); // 0xAE + ssd1306_command(SSD1306_SETDISPLAYCLOCKDIV); // 0xD5 + ssd1306_command(0x80); // the suggested ratio 0x80 + ssd1306_command(SSD1306_SETMULTIPLEX); // 0xA8 + ssd1306_command(0x1F); + ssd1306_command(SSD1306_SETDISPLAYOFFSET); // 0xD3 + ssd1306_command(0x0); // no offset + ssd1306_command(SSD1306_SETSTARTLINE | 0x0); // line #0 + ssd1306_command(SSD1306_CHARGEPUMP); // 0x8D + if (vccstate == SSD1306_EXTERNALVCC) + { ssd1306_command(0x10); } + else + { ssd1306_command(0x14); } + ssd1306_command(SSD1306_MEMORYMODE); // 0x20 + ssd1306_command(0x00); // 0x0 act like ks0108 + ssd1306_command(SSD1306_SEGREMAP | 0x1); + ssd1306_command(SSD1306_COMSCANDEC); + ssd1306_command(SSD1306_SETCOMPINS); // 0xDA + ssd1306_command(0x02); + ssd1306_command(SSD1306_SETCONTRAST); // 0x81 + ssd1306_command(0x8F); + ssd1306_command(SSD1306_SETPRECHARGE); // 0xd9 + if (vccstate == SSD1306_EXTERNALVCC) + { ssd1306_command(0x22); } + else + { ssd1306_command(0xF1); } + ssd1306_command(SSD1306_SETVCOMDETECT); // 0xDB + ssd1306_command(0x40); + ssd1306_command(SSD1306_DISPLAYALLON_RESUME); // 0xA4 + ssd1306_command(SSD1306_NORMALDISPLAY); // 0xA6 + #endif + + + #if defined SSD1306_128_64 + // Init sequence for 128x64 OLED module + ssd1306_command(SSD1306_DISPLAYOFF); // 0xAE + ssd1306_command(SSD1306_SETDISPLAYCLOCKDIV); // 0xD5 + ssd1306_command(0x80); // the suggested ratio 0x80 + ssd1306_command(SSD1306_SETMULTIPLEX); // 0xA8 + ssd1306_command(0x3F); + ssd1306_command(SSD1306_SETDISPLAYOFFSET); // 0xD3 + ssd1306_command(0x0); // no offset + ssd1306_command(SSD1306_SETSTARTLINE | 0x0); // line #0 + ssd1306_command(SSD1306_CHARGEPUMP); // 0x8D + if (vccstate == SSD1306_EXTERNALVCC) + { ssd1306_command(0x10); } + else + { ssd1306_command(0x14); } + ssd1306_command(SSD1306_MEMORYMODE); // 0x20 + ssd1306_command(0x00); // 0x0 act like ks0108 + ssd1306_command(SSD1306_SEGREMAP | 0x1); + ssd1306_command(SSD1306_COMSCANDEC); + ssd1306_command(SSD1306_SETCOMPINS); // 0xDA + ssd1306_command(0x12); + ssd1306_command(SSD1306_SETCONTRAST); // 0x81 + if (vccstate == SSD1306_EXTERNALVCC) + { ssd1306_command(0x9F); } + else + { ssd1306_command(0xCF); } + ssd1306_command(SSD1306_SETPRECHARGE); // 0xd9 + if (vccstate == SSD1306_EXTERNALVCC) + { ssd1306_command(0x22); } + else + { ssd1306_command(0xF1); } + ssd1306_command(SSD1306_SETVCOMDETECT); // 0xDB + ssd1306_command(0x40); + ssd1306_command(SSD1306_DISPLAYALLON_RESUME); // 0xA4 + ssd1306_command(SSD1306_NORMALDISPLAY); // 0xA6 + #endif + + ssd1306_command(SSD1306_DISPLAYON);//--turn on oled panel + + + // clear screen + delay(5); + + clear(); +} + + +void SSD1306::invertDisplay(uint8_t i) { + if (i) { + ssd1306_command(SSD1306_INVERTDISPLAY); + } else { + ssd1306_command(SSD1306_NORMALDISPLAY); + } +} + +void SSD1306::ssd1306_command(uint8_t c) { + // I2C + uint8_t control = 0x00; // Co = 0, D/C = 0 + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(control); + WIRE_WRITE(c); + Wire.endTransmission(); +} +void SSD1306::ssd1306_command2(uint8_t c, uint8_t d) { + // I2C + uint8_t control = 0x00; // Co = 0, D/C = 0 + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(control); + WIRE_WRITE(c); + WIRE_WRITE(d); + Wire.endTransmission(); +} +void SSD1306::ssd1306_command3(uint8_t c, uint8_t d, uint8_t e) { + // I2C + uint8_t control = 0x00; // Co = 0, D/C = 0 + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(control); + WIRE_WRITE(c); + WIRE_WRITE(d); + WIRE_WRITE(e); + Wire.endTransmission(); +} + +// startscrollright +// Activate a right handed scroll for rows start through stop +// Hint, the display is 16 rows tall. To scroll the whole display, run: +// display.scrollright(0x00, 0x0F) +void SSD1306::startscrollright(uint8_t start, uint8_t stop){ + ssd1306_command(SSD1306_RIGHT_HORIZONTAL_SCROLL); + ssd1306_command(0X00); + ssd1306_command(start); + ssd1306_command(0X00); + ssd1306_command(stop); + ssd1306_command(0X01); + ssd1306_command(0XFF); + ssd1306_command(SSD1306_ACTIVATE_SCROLL); +} + +// startscrollleft +// Activate a right handed scroll for rows start through stop +// Hint, the display is 16 rows tall. To scroll the whole display, run: +// display.scrollright(0x00, 0x0F) +void SSD1306::startscrollleft(uint8_t start, uint8_t stop){ + ssd1306_command(SSD1306_LEFT_HORIZONTAL_SCROLL); + ssd1306_command(0X00); + ssd1306_command(start); + ssd1306_command(0X00); + ssd1306_command(stop); + ssd1306_command(0X01); + ssd1306_command(0XFF); + ssd1306_command(SSD1306_ACTIVATE_SCROLL); +} + +// startscrolldiagright +// Activate a diagonal scroll for rows start through stop +// Hint, the display is 16 rows tall. To scroll the whole display, run: +// display.scrollright(0x00, 0x0F) +void SSD1306::startscrolldiagright(uint8_t start, uint8_t stop){ + ssd1306_command(SSD1306_SET_VERTICAL_SCROLL_AREA); + ssd1306_command(0X00); + ssd1306_command(SSD1306_LCDHEIGHT); + ssd1306_command(SSD1306_VERTICAL_AND_RIGHT_HORIZONTAL_SCROLL); + ssd1306_command(0X00); + ssd1306_command(start); + ssd1306_command(0X00); + ssd1306_command(stop); + ssd1306_command(0X01); + ssd1306_command(SSD1306_ACTIVATE_SCROLL); +} + +// startscrolldiagleft +// Activate a diagonal scroll for rows start through stop +// Hint, the display is 16 rows tall. To scroll the whole display, run: +// display.scrollright(0x00, 0x0F) +void SSD1306::startscrolldiagleft(uint8_t start, uint8_t stop){ + ssd1306_command(SSD1306_SET_VERTICAL_SCROLL_AREA); + ssd1306_command(0X00); + ssd1306_command(SSD1306_LCDHEIGHT); + ssd1306_command(SSD1306_VERTICAL_AND_LEFT_HORIZONTAL_SCROLL); + ssd1306_command(0X00); + ssd1306_command(start); + ssd1306_command(0X00); + ssd1306_command(stop); + ssd1306_command(0X01); + ssd1306_command(SSD1306_ACTIVATE_SCROLL); +} + +void SSD1306::stopscroll(void){ + ssd1306_command(SSD1306_DEACTIVATE_SCROLL); +} + +void SSD1306::ssd1306_data(uint8_t c) { + // I2C + uint8_t control = 0x40; // Co = 0, D/C = 1 + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(control); + WIRE_WRITE(c); + Wire.endTransmission(); +} + +void SSD1306::fill(unsigned char dat) +{ + unsigned char i,j; + + ssd1306_command(0x00);//set lower column address + ssd1306_command(0x10);//set higher column address + ssd1306_command(0xB0);//set page address + +#ifdef TWBR + uint8_t twbrbackup = TWBR; + TWBR = 18; // upgrade to 400KHz! +#endif + for (byte i=0; i<(SSD1306_LCDHEIGHT/8); i++) + { + // send a bunch of data in one xmission + ssd1306_command(0xB0 + i);//set page address + ssd1306_command(0);//set lower column address + ssd1306_command(0x10);//set higher column address + + for(byte j = 0; j < 8; j++){ + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for (byte k = 0; k < 16; k++) { + WIRE_WRITE(dat); + } + Wire.endTransmission(); + } + } +#ifdef TWBR + TWBR = twbrbackup; +#endif +} + +void SSD1306::clear(byte x, byte y, byte width, byte height) +{ + byte eline = (y + height) >> 3; + y >>= 3; + + uint16_t xfersize = width * height >> 3; + if (( y & 0x07) + (height & 0x07) > 7) { + eline++; + xfersize += width; + } + + ssd1306_command2( 0x20, 0x00); // memory addressing mode: horizontal + ssd1306_command3( 0x21, x, (x+width)-1); // column start/end + ssd1306_command3( 0x22, y, eline-1); // page address start/end + +#ifdef TWBR + uint8_t twbrbackup = TWBR; + TWBR = 18; // upgrade to 400KHz! +#endif + uint16_t i = 0; + while( i < xfersize) { + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + for( byte j = 0; j < I2C_BLT_SIZE; j++, i++){ + WIRE_WRITE(0); + } + Wire.endTransmission(); + } +#ifdef TWBR + TWBR = twbrbackup; +#endif +} + +/* void SSD1306::draw8x8(byte* buffer, uint8_t x, uint8_t y) +{ + // send a bunch of data in one xmission + ssd1306_command(0xB0 + y);//set page address + ssd1306_command(x & 0xf);//set lower column address + ssd1306_command(0x10 | (x >> 4));//set higher column address + + Wire.beginTransmission(_i2caddr); + WIRE_WRITE(0x40); + WIRE_WRITE(buffer, 8); + Wire.endTransmission(); +} +*/ diff --git a/hardware/digistump/avr/libraries/MicrOledPro/SSD1306.h b/hardware/digistump/avr/libraries/MicrOledPro/SSD1306.h new file mode 100644 index 0000000..2089ec6 --- /dev/null +++ b/hardware/digistump/avr/libraries/MicrOledPro/SSD1306.h @@ -0,0 +1,125 @@ +//#include "Arduino.h" + #if ARDUINO >= 100 + #include "Arduino.h" + #define WIRE_WRITE Wire.write +#else + #include "WProgram.h" + #define WIRE_WRITE Wire.send + <100 +#endif + +#define SSD1306_I2C_ADDRESS 0x3C // 011110+SA0+RW - 0x3C or 0x3D +// Address for 128x32 is 0x3C +// Address for 128x32 is 0x3D (default) or 0x3C (if SA0 is grounded) + +/*========================================================================= + SSD1306 Displays + ----------------------------------------------------------------------- + The driver is used in multiple displays (128x64, 128x32, etc.). + Select the appropriate display below to create an appropriately + sized framebuffer, etc. + + SSD1306_128_64 128x64 pixel display + + SSD1306_128_32 128x32 pixel display + + You also need to set the LCDWIDTH and LCDHEIGHT defines to an + appropriate size + + -----------------------------------------------------------------------*/ + #define SSD1306_128_64 +// #define SSD1306_128_32 +/*=========================================================================*/ + +#if defined SSD1306_128_64 && defined SSD1306_128_32 + #error "Only one SSD1306 display can be specified at once in SSD1306.h" +#endif +#if !defined SSD1306_128_64 && !defined SSD1306_128_32 + #error "At least one SSD1306 display must be specified in SSD1306.h" +#endif + +#if defined SSD1306_128_64 + #define SSD1306_LCDWIDTH 128 + #define SSD1306_LCDHEIGHT 64 +#endif +#if defined SSD1306_128_32 + #define SSD1306_LCDWIDTH 128 + #define SSD1306_LCDHEIGHT 32 +#endif + +#define SSD1306_SETCONTRAST 0x81 +#define SSD1306_DISPLAYALLON_RESUME 0xA4 +#define SSD1306_DISPLAYALLON 0xA5 +#define SSD1306_NORMALDISPLAY 0xA6 +#define SSD1306_INVERTDISPLAY 0xA7 +#define SSD1306_DISPLAYOFF 0xAE +#define SSD1306_DISPLAYON 0xAF + +#define SSD1306_SETDISPLAYOFFSET 0xD3 +#define SSD1306_SETCOMPINS 0xDA + +#define SSD1306_SETVCOMDETECT 0xDB + +#define SSD1306_SETDISPLAYCLOCKDIV 0xD5 +#define SSD1306_SETPRECHARGE 0xD9 + +#define SSD1306_SETMULTIPLEX 0xA8 + +#define SSD1306_SETLOWCOLUMN 0x00 +#define SSD1306_SETHIGHCOLUMN 0x10 + +#define SSD1306_SETSTARTLINE 0x40 + +#define SSD1306_MEMORYMODE 0x20 + +#define SSD1306_COMSCANINC 0xC0 +#define SSD1306_COMSCANDEC 0xC8 + +#define SSD1306_SEGREMAP 0xA0 + +#define SSD1306_CHARGEPUMP 0x8D + +#define SSD1306_EXTERNALVCC 0x1 +#define SSD1306_SWITCHCAPVCC 0x2 + +// Scrolling #defines +#define SSD1306_ACTIVATE_SCROLL 0x2F +#define SSD1306_DEACTIVATE_SCROLL 0x2E +#define SSD1306_SET_VERTICAL_SCROLL_AREA 0xA3 +#define SSD1306_RIGHT_HORIZONTAL_SCROLL 0x26 +#define SSD1306_LEFT_HORIZONTAL_SCROLL 0x27 +#define SSD1306_VERTICAL_AND_RIGHT_HORIZONTAL_SCROLL 0x29 +#define SSD1306_VERTICAL_AND_LEFT_HORIZONTAL_SCROLL 0x2A + +#define I2C_BLT_SIZE 8 + +class SSD1306 { +public: + SSD1306(int8_t SCLK, int8_t DC, int8_t RST, int8_t CS); + SSD1306(int8_t RST = 4); + + void begin(uint8_t switchvcc = SSD1306_SWITCHCAPVCC, uint8_t i2caddr = SSD1306_I2C_ADDRESS); + void ssd1306_command(uint8_t c); + void ssd1306_command2(uint8_t c,uint8_t d); + void ssd1306_command3(uint8_t c,uint8_t d,uint8_t e); + void ssd1306_data(uint8_t c); + + void invertDisplay(uint8_t i); + // void draw8x8(byte* buffer, byte x, byte y); + + void startscrollright(uint8_t start, uint8_t stop); + void startscrollleft(uint8_t start, uint8_t stop); + + void startscrolldiagright(uint8_t start, uint8_t stop); + void startscrolldiagleft(uint8_t start, uint8_t stop); + void stopscroll(void); + + void fill(unsigned char dat); + void clear(byte x=0, byte y=0, byte width=128, byte height=64); + void clearBuffer(); + +protected: + uint8_t _i2caddr; +private: + int8_t sclk, dc, rst, cs; +}; diff --git a/hardware/digistump/avr/libraries/MicrOledPro/examples/lcdhello/lcdhello.ino b/hardware/digistump/avr/libraries/MicrOledPro/examples/lcdhello/lcdhello.ino new file mode 100644 index 0000000..37d37f1 --- /dev/null +++ b/hardware/digistump/avr/libraries/MicrOledPro/examples/lcdhello/lcdhello.ino @@ -0,0 +1,116 @@ +/************************************************************************* +* Demo sketch for MicroLCD library +* Distributed under GPL v2.0 +* Copyright (c) 2013-2014 Stanley Huang +* All rights reserved. +* For more information, please visit http://arduinodev.com +*************************************************************************/ + +#include +#include +#include + +//LCD_SH1106 lcd; /* for SH1106 OLED module */ +LCD_SSD1306 lcd; /* for SSD1306 OLED module */ + + +const PROGMEM uint8_t smile[48 * 48 / 8] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xF8, 0xFC, 0xFC, 0xFE, 0xFE, 0x7E, 0x7F, 0x7F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x7F, 0x7F, 0x7E, 0xFE, 0xFE, 0xFC, 0xFC, 0xF8, 0xF8, 0xF0, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xC0, 0xF0, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, 0x3F, 0x1F, 0x0F, 0x07, 0x03, 0x01, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x01, 0x03, 0x07, 0x0F, 0x1F, 0x3F, 0xFF, 0xFF, 0xFF, 0xFE, 0xFC, 0xF0, 0xC0, 0x00, + 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x1F, 0x1F, 0x1F, 0x3F, 0x1F, 0x1F, 0x02, 0x00, 0x00, 0x00, 0x00, 0x06, 0x1F, 0x1F, 0x1F, 0x3F, 0x1F, 0x1F, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0x00, 0x00, 0x30, 0xF8, 0xF8, 0xF8, 0xF8, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0xF8, 0xF8, 0xFC, 0xF8, 0x30, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, + 0x00, 0x03, 0x0F, 0x3F, 0x7F, 0xFF, 0xFF, 0xFF, 0xFC, 0xF8, 0xF0, 0xE1, 0xC7, 0x87, 0x0F, 0x1F, 0x3F, 0x3F, 0x3E, 0x7E, 0x7C, 0x7C, 0x7C, 0x78, 0x78, 0x7C, 0x7C, 0x7C, 0x7E, 0x3E, 0x3F, 0x3F, 0x1F, 0x0F, 0x87, 0xC7, 0xE1, 0xF0, 0xF8, 0xFC, 0xFF, 0xFF, 0xFF, 0x7F, 0x3F, 0x0F, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x07, 0x0F, 0x1F, 0x1F, 0x3F, 0x3F, 0x7F, 0x7F, 0x7E, 0xFE, 0xFE, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFE, 0xFE, 0x7E, 0x7F, 0x7F, 0x3F, 0x3F, 0x1F, 0x1F, 0x0F, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + + +const PROGMEM uint8_t tick[16 * 16 / 8] = +{0x00, 0x80, 0xC0, 0xE0, 0xC0, 0x80, 0x00, 0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC, 0x78, 0x30, 0x00, 0x00, 0x01, 0x03, 0x07, 0x0F, 0x1F, 0x1F, 0x1F, 0x0F, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00}; + +const PROGMEM uint8_t cross[16 * 16 / 8] = +{0x00, 0x0C, 0x1C, 0x3C, 0x78, 0xF0, 0xE0, 0xC0, 0xE0, 0xF0, 0x78, 0x3C, 0x1C, 0x0C, 0x00, 0x00, 0x00, 0x30, 0x38, 0x3C, 0x1E, 0x0F, 0x07, 0x03, 0x07, 0x0F, 0x1E, 0x3C, 0x38, 0x30, 0x00, 0x00}; + +void setup() +{ + lcd.begin(); +} + +int wait = 500; +long lcount = 0; +void loop() +{ + lcd.clear(); + for ( int ii = 1; ii < 72; ii++) { + lcd.setCursor( ii, 1); + lcd.draw(smile, 48, 48); + delay( 25); + lcd.clear( ii, 8, 56, 48); + } +// delay(wait); + lcd.clear(); + lcd.setCursor(40, 1); + lcd.draw(smile, 48, 48); + delay(wait); + + lcd.clear(); + lcd.setFontSize(FONT_SIZE_SMALL); + lcd.println("Hello, world!"); + lcd.setFontSize(FONT_SIZE_MEDIUM); + lcd.println("Hello, world!"); + lcd.setFontSize(FONT_SIZE_MEDIUM); + lcd.println("Hello, world!"); + lcd.setFontSize(FONT_SIZE_SMALL); + lcd.println("Hello, world!123<>{}"); + delay(wait); + + lcd.clear(); + for ( int ii = 1; ii < 9; ii++) { + lcd.printInt(ii); +// delay(wait / 10); + lcd.println("_._.5._._0_._.5._._0"); +// delay(wait / 4); + } + delay(wait); + + lcd.clear(); + lcd.setCursor(40, 6); + lcd.draw(tick, 16, 16); + lcd.setCursor(72, 6); + lcd.draw(cross, 16, 16); + delay(wait); + + lcd.clear(); + lcd.setCursor(0, 0); + lcd.setFontSize(FONT_SIZE_SMALL); + lcd.printLong(12345678); + delay(wait); + + lcd.clear(); + lcd.setCursor(0, 0); + lcd.setFontSize(FONT_SIZE_MEDIUM); + lcd.printLong(12345678); + delay(wait); + + lcd.clear(); + lcd.setCursor(0, 0); + lcd.setFontSize(FONT_SIZE_LARGE); + lcd.println("Count"); + lcd.printLong(++lcount); + delay(wait); + + lcd.clear(); + lcd.setCursor(0, 0); + lcd.setFontSize(FONT_SIZE_XLARGE); + lcd.printLong(12345678); + delay(wait); + + lcd.clear(); + lcd.setCursor(0, 0); + lcd.setFontSize(FONT_SIZE_MEDIUM); + lcd.println("WAIT"); + lcd.printInt(wait); + lcd.println("Count"); + lcd.printLong(lcount); + delay(250+wait); +} + diff --git a/hardware/digistump/avr/libraries/MicrOledPro/examples/lcdhello2/lcdhello2.ino b/hardware/digistump/avr/libraries/MicrOledPro/examples/lcdhello2/lcdhello2.ino new file mode 100644 index 0000000..b777c2a --- /dev/null +++ b/hardware/digistump/avr/libraries/MicrOledPro/examples/lcdhello2/lcdhello2.ino @@ -0,0 +1,106 @@ +#include / +#include +#include + +//LCD_SH1106 lcd; /* for SH1106 OLED module */ +LCD_SSD1306 lcd; /* for SSD1306 OLED module */ + + +const PROGMEM uint8_t smile[48 * 48 / 8] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xF8, 0xFC, 0xFC, 0xFE, 0xFE, 0x7E, 0x7F, 0x7F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x7F, 0x7F, 0x7E, 0xFE, 0xFE, 0xFC, 0xFC, 0xF8, 0xF8, 0xF0, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xC0, 0xF0, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, 0x3F, 0x1F, 0x0F, 0x07, 0x03, 0x01, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x01, 0x03, 0x07, 0x0F, 0x1F, 0x3F, 0xFF, 0xFF, 0xFF, 0xFE, 0xFC, 0xF0, 0xC0, 0x00, + 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x1F, 0x1F, 0x1F, 0x3F, 0x1F, 0x1F, 0x02, 0x00, 0x00, 0x00, 0x00, 0x06, 0x1F, 0x1F, 0x1F, 0x3F, 0x1F, 0x1F, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, + 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0x00, 0x00, 0x30, 0xF8, 0xF8, 0xF8, 0xF8, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0xF8, 0xF8, 0xFC, 0xF8, 0x30, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, + 0x00, 0x03, 0x0F, 0x3F, 0x7F, 0xFF, 0xFF, 0xFF, 0xFC, 0xF8, 0xF0, 0xE1, 0xC7, 0x87, 0x0F, 0x1F, 0x3F, 0x3F, 0x3E, 0x7E, 0x7C, 0x7C, 0x7C, 0x78, 0x78, 0x7C, 0x7C, 0x7C, 0x7E, 0x3E, 0x3F, 0x3F, 0x1F, 0x0F, 0x87, 0xC7, 0xE1, 0xF0, 0xF8, 0xFC, 0xFF, 0xFF, 0xFF, 0x7F, 0x3F, 0x0F, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x07, 0x0F, 0x1F, 0x1F, 0x3F, 0x3F, 0x7F, 0x7F, 0x7E, 0xFE, 0xFE, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFE, 0xFE, 0x7E, 0x7F, 0x7F, 0x3F, 0x3F, 0x1F, 0x1F, 0x0F, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + + +const PROGMEM uint8_t tick[16 * 16 / 8] = +{0x00, 0x80, 0xC0, 0xE0, 0xC0, 0x80, 0x00, 0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC, 0x78, 0x30, 0x00, 0x00, 0x01, 0x03, 0x07, 0x0F, 0x1F, 0x1F, 0x1F, 0x0F, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00}; + +const PROGMEM uint8_t cross[16 * 16 / 8] = +{0x00, 0x0C, 0x1C, 0x3C, 0x78, 0xF0, 0xE0, 0xC0, 0xE0, 0xF0, 0x78, 0x3C, 0x1C, 0x0C, 0x00, 0x00, 0x00, 0x30, 0x38, 0x3C, 0x1E, 0x0F, 0x07, 0x03, 0x07, 0x0F, 0x1E, 0x3C, 0x38, 0x30, 0x00, 0x00}; + +void setup() +{ + lcd.begin(); +} + +int wait = 340; +long lcount = 0; +void loop() +{ + if (wait < 400) wait += 70; else wait = 20; + for ( int ii = 1; ii < 8; ii++) { + lcd.clear(); + lcd.setCursor(5 + (ii * 8), 1); + lcd.draw(smile, 48, 48); + delay(wait/3); + } + delay(wait); + lcd.clear(); + lcd.setCursor(40, 1); + lcd.draw(smile, 48, 48); + delay(wait); + + lcd.clear(); + lcd.setFontSize(FONT_SIZE_SMALL); + lcd.println("Hello, world!"); + lcd.setFontSize(FONT_SIZE_MEDIUM); + lcd.println("Hello, world!"); + lcd.setFontSize(FONT_SIZE_MEDIUM); + lcd.println("Hello, world!"); + lcd.setFontSize(FONT_SIZE_SMALL); + lcd.println("Hello, world!ABC<>{}"); + delay(wait); + lcd.clear(); + + for ( int ii = 1; ii < 9; ii++) { + lcd.printInt(ii); + delay(wait / 10); + lcd.println("_._.5._._0_._.5._._0"); + delay(wait / 4); + } + delay(wait); + + lcd.setCursor(40, 6); + lcd.draw(tick, 16, 16); + lcd.setCursor(72, 6); + lcd.draw(cross, 16, 16); + delay(wait); + + lcd.clear(); + lcd.setCursor(0, 0); + lcd.setFontSize(FONT_SIZE_SMALL); + lcd.printLong(12345678); + delay(wait); + + lcd.clear(); + lcd.setCursor(0, 0); + lcd.setFontSize(FONT_SIZE_MEDIUM); + lcd.printLong(12345678); + delay(wait); + + lcd.clear(); + lcd.setCursor(0, 0); + lcd.setFontSize(FONT_SIZE_LARGE); + lcd.println("Count"); + lcd.printLong(++lcount); + delay(wait); + + lcd.clear(); + lcd.setCursor(0, 0); + lcd.setFontSize(FONT_SIZE_XLARGE); + lcd.printLong(12345678); + delay(wait); + + lcd.clear(); + lcd.setCursor(0, 0); + lcd.setFontSize(FONT_SIZE_MEDIUM); + lcd.println("WAIT"); + lcd.printInt(wait); + lcd.println("Count"); + lcd.printLong(lcount); + delay(100+wait); +} diff --git a/hardware/digistump/avr/libraries/Nunchuk/ArduinoNunchuk.cpp b/hardware/digistump/avr/libraries/Nunchuk/ArduinoNunchuk.cpp new file mode 100644 index 0000000..eab00d3 --- /dev/null +++ b/hardware/digistump/avr/libraries/Nunchuk/ArduinoNunchuk.cpp @@ -0,0 +1,65 @@ +/* + * ArduinoNunchuk.cpp - Improved Wii Nunchuk library for Arduino + * + * Copyright 2011-2013 Gabriel Bianconi, http://www.gabrielbianconi.com/ + * + * Project URL: http://www.gabrielbianconi.com/projects/arduinonunchuk/ + * + * Based on the following resources: + * http://www.windmeadow.com/node/42 + * http://todbot.com/blog/2008/02/18/wiichuck-wii-nunchuck-adapter-available/ + * http://wiibrew.org/wiki/Wiimote/Extension_Controllers + * + */ + +#include +#include +#include "ArduinoNunchuk.h" + +#define ADDRESS 0x52 + +void ArduinoNunchuk::init() +{ + TinyWireM.begin(); + + ArduinoNunchuk::_sendByte(0x55, 0xF0); + ArduinoNunchuk::_sendByte(0x00, 0xFB); + + ArduinoNunchuk::update(); +} + +void ArduinoNunchuk::update() +{ + int count = 0; + int values[6]; + + TinyWireM.requestFrom(ADDRESS, 6); + + while(TinyWireM.available()) + { + values[count] = TinyWireM.receive(); + count++; + } + + ArduinoNunchuk::analogX = values[0]; + ArduinoNunchuk::analogY = values[1]; + ArduinoNunchuk::accelX = (values[2] << 2) | ((values[5] >> 2) & 3); + ArduinoNunchuk::accelY = (values[3] << 2) | ((values[5] >> 4) & 3); + ArduinoNunchuk::accelZ = (values[4] << 2) | ((values[5] >> 6) & 3); + ArduinoNunchuk::zButton = !((values[5] >> 0) & 1); + ArduinoNunchuk::cButton = !((values[5] >> 1) & 1); + + ArduinoNunchuk::_sendByte(0x00, 0x00); +} + +void ArduinoNunchuk::_sendByte(byte data, byte location) +{ + TinyWireM.beginTransmission(ADDRESS); + + TinyWireM.send(location); + TinyWireM.send(data); + + TinyWireM.endTransmission(); + + delay(10); +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/Nunchuk/ArduinoNunchuk.h b/hardware/digistump/avr/libraries/Nunchuk/ArduinoNunchuk.h new file mode 100644 index 0000000..0c1a9e0 --- /dev/null +++ b/hardware/digistump/avr/libraries/Nunchuk/ArduinoNunchuk.h @@ -0,0 +1,38 @@ +/* + * ArduinoNunchuk.h - Improved Wii Nunchuk library for Arduino + * + * Copyright 2011-2013 Gabriel Bianconi, http://www.gabrielbianconi.com/ + * + * Project URL: http://www.gabrielbianconi.com/projects/arduinonunchuk/ + * + * Based on the following resources: + * http://www.windmeadow.com/node/42 + * http://todbot.com/blog/2008/02/18/wiichuck-wii-nunchuck-adapter-available/ + * http://wiibrew.org/wiki/Wiimote/Extension_Controllers + * + */ + +#ifndef ArduinoNunchuk_H +#define ArduinoNunchuk_H + +#include + +class ArduinoNunchuk +{ + public: + int analogX; + int analogY; + int accelX; + int accelY; + int accelZ; + int zButton; + int cButton; + + void init(); + void update(); + + private: + void _sendByte(byte data, byte location); +}; + +#endif diff --git a/hardware/digistump/avr/libraries/Nunchuk/LICENSE.txt b/hardware/digistump/avr/libraries/Nunchuk/LICENSE.txt new file mode 100644 index 0000000..328baef --- /dev/null +++ b/hardware/digistump/avr/libraries/Nunchuk/LICENSE.txt @@ -0,0 +1,3 @@ +LICENSE + +This work is licensed under the Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License. To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-sa/3.0/ or send a letter to Creative Commons, 444 Castro Street, Suite 900, Mountain View, California, 94041, USA. \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/Nunchuk/README.txt b/hardware/digistump/avr/libraries/Nunchuk/README.txt new file mode 100644 index 0000000..ae13dcc --- /dev/null +++ b/hardware/digistump/avr/libraries/Nunchuk/README.txt @@ -0,0 +1,15 @@ +ArduinoNunchuk - Improved Wii Nunchuk library for Arduino + +Copyright 2011-2013 Gabriel Bianconi, http://www.gabrielbianconi.com/ + +Project URL: http://www.gabrielbianconi.com/projects/arduinonunchuk/ + +Based on the following resources: + - http://www.windmeadow.com/node/42 + - http://todbot.com/blog/2008/02/18/wiichuck-wii-nunchuck-adapter-available/ + - http://wiibrew.org/wiki/Wiimote/Extension_Controllers + + +INSTALLATION: + +Copy the 'ArduinoNunchuk' folder, located in the same folder as this 'README' file, to the Arduino libraries folder (Arduino/libraries). \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/Nunchuk/examples/ArduinoNunchukDemo/ArduinoNunchukDemo.ino b/hardware/digistump/avr/libraries/Nunchuk/examples/ArduinoNunchukDemo/ArduinoNunchukDemo.ino new file mode 100644 index 0000000..7085c03 --- /dev/null +++ b/hardware/digistump/avr/libraries/Nunchuk/examples/ArduinoNunchukDemo/ArduinoNunchukDemo.ino @@ -0,0 +1,40 @@ +/* + * ArduinoNunchukDemo.ino + * + * Copyright 2011-2013 Gabriel Bianconi, http://www.gabrielbianconi.com/ + * + * Project URL: http://www.gabrielbianconi.com/projects/arduinonunchuk/ + * + */ + +#include +#include + +#define BAUDRATE 19200 + +ArduinoNunchuk nunchuk = ArduinoNunchuk(); + +void setup() +{ + Serial.begin(BAUDRATE); + nunchuk.init(); +} + +void loop() +{ + nunchuk.update(); + + Serial.print(nunchuk.analogX, DEC); + Serial.print(' '); + Serial.print(nunchuk.analogY, DEC); + Serial.print(' '); + Serial.print(nunchuk.accelX, DEC); + Serial.print(' '); + Serial.print(nunchuk.accelY, DEC); + Serial.print(' '); + Serial.print(nunchuk.accelZ, DEC); + Serial.print(' '); + Serial.print(nunchuk.zButton, DEC); + Serial.print(' '); + Serial.println(nunchuk.cButton, DEC); +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/Nunchuk/examples/DigisparkJoystickDemo/DigisparkJoystickDemo.ino b/hardware/digistump/avr/libraries/Nunchuk/examples/DigisparkJoystickDemo/DigisparkJoystickDemo.ino new file mode 100644 index 0000000..1714d3f --- /dev/null +++ b/hardware/digistump/avr/libraries/Nunchuk/examples/DigisparkJoystickDemo/DigisparkJoystickDemo.ino @@ -0,0 +1,28 @@ +//DigiJoystick Nunchuck Demo + +#include +#include +#include + +ArduinoNunchuk nunchuk = ArduinoNunchuk(); + +void setup() { + nunchuk.init(); +} + + +void loop() { + nunchuk.update(); + DigiJoystick.setX((byte) nunchuk.analogX); // scroll X left to right repeatedly + DigiJoystick.setY((byte) nunchuk.analogY); + DigiJoystick.setXROT((byte) map(nunchuk.accelX,255,700,0,255)); + DigiJoystick.setYROT((byte) map(nunchuk.accelY,255,850,0,255)); + DigiJoystick.setZROT((byte) map(nunchuk.accelZ,255,750,0,255)); + int buttonByte = 0; + bitWrite(buttonByte, 0, nunchuk.zButton); + bitWrite(buttonByte, 1, nunchuk.cButton); + DigiJoystick.setButtons((byte) buttonByte, (byte) 0); + DigiJoystick.delay(10); + + +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/Nunchuk/examples/DigisparkUSBDemo/DigisparkUSBDemo.ino b/hardware/digistump/avr/libraries/Nunchuk/examples/DigisparkUSBDemo/DigisparkUSBDemo.ino new file mode 100644 index 0000000..a304cca --- /dev/null +++ b/hardware/digistump/avr/libraries/Nunchuk/examples/DigisparkUSBDemo/DigisparkUSBDemo.ino @@ -0,0 +1,40 @@ +/* + * Digispark Nunchuck shield demo + * + * Uses arduinonunchuk - Copyright 2011-2013 Gabriel Bianconi, http://www.gabrielbianconi.com/ - http://www.gabrielbianconi.com/projects/arduinonunchuk/ + * + */ + + +#include +#include +#include + +ArduinoNunchuk nunchuk = ArduinoNunchuk(); + +void setup() +{ + DigiUSB.begin(); + nunchuk.init(); +} + +void loop() +{ + nunchuk.update(); + + DigiUSB.println(nunchuk.analogX, DEC); + + DigiUSB.println(nunchuk.analogY, DEC); + + DigiUSB.println(nunchuk.accelX, DEC); + + DigiUSB.println(nunchuk.accelY, DEC); + + DigiUSB.println(nunchuk.accelZ, DEC); + + DigiUSB.println(nunchuk.zButton, DEC); + + DigiUSB.println(nunchuk.cButton, DEC); + + DigiUSB.delay(250); +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/Nunchuk/keywords.txt b/hardware/digistump/avr/libraries/Nunchuk/keywords.txt new file mode 100644 index 0000000..5c25fd6 --- /dev/null +++ b/hardware/digistump/avr/libraries/Nunchuk/keywords.txt @@ -0,0 +1,3 @@ +ArduinoNunchuk KEYWORD1 +init KEYWORD2 +update KEYWORD2 \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/OneWire/OneWire.cpp b/hardware/digistump/avr/libraries/OneWire/OneWire.cpp new file mode 100644 index 0000000..631813f --- /dev/null +++ b/hardware/digistump/avr/libraries/OneWire/OneWire.cpp @@ -0,0 +1,557 @@ +/* +Copyright (c) 2007, Jim Studt (original old version - many contributors since) + +The latest version of this library may be found at: + http://www.pjrc.com/teensy/td_libs_OneWire.html + +OneWire has been maintained by Paul Stoffregen (paul@pjrc.com) since +January 2010. At the time, it was in need of many bug fixes, but had +been abandoned the original author (Jim Studt). None of the known +contributors were interested in maintaining OneWire. Paul typically +works on OneWire every 6 to 12 months. Patches usually wait that +long. If anyone is interested in more actively maintaining OneWire, +please contact Paul. + +Version 2.2: + Teensy 3.0 compatibility, Paul Stoffregen, paul@pjrc.com + Arduino Due compatibility, http://arduino.cc/forum/index.php?topic=141030 + Fix DS18B20 example negative temperature + Fix DS18B20 example's low res modes, Ken Butcher + Improve reset timing, Mark Tillotson + Add const qualifiers, Bertrik Sikken + Add initial value input to crc16, Bertrik Sikken + Add target_search() function, Scott Roberts + +Version 2.1: + Arduino 1.0 compatibility, Paul Stoffregen + Improve temperature example, Paul Stoffregen + DS250x_PROM example, Guillermo Lovato + PIC32 (chipKit) compatibility, Jason Dangel, dangel.jason AT gmail.com + Improvements from Glenn Trewitt: + - crc16() now works + - check_crc16() does all of calculation/checking work. + - Added read_bytes() and write_bytes(), to reduce tedious loops. + - Added ds2408 example. + Delete very old, out-of-date readme file (info is here) + +Version 2.0: Modifications by Paul Stoffregen, January 2010: +http://www.pjrc.com/teensy/td_libs_OneWire.html + Search fix from Robin James + http://www.arduino.cc/cgi-bin/yabb2/YaBB.pl?num=1238032295/27#27 + Use direct optimized I/O in all cases + Disable interrupts during timing critical sections + (this solves many random communication errors) + Disable interrupts during read-modify-write I/O + Reduce RAM consumption by eliminating unnecessary + variables and trimming many to 8 bits + Optimize both crc8 - table version moved to flash + +Modified to work with larger numbers of devices - avoids loop. +Tested in Arduino 11 alpha with 12 sensors. +26 Sept 2008 -- Robin James +http://www.arduino.cc/cgi-bin/yabb2/YaBB.pl?num=1238032295/27#27 + +Updated to work with arduino-0008 and to include skip() as of +2007/07/06. --RJL20 + +Modified to calculate the 8-bit CRC directly, avoiding the need for +the 256-byte lookup table to be loaded in RAM. Tested in arduino-0010 +-- Tom Pollard, Jan 23, 2008 + +Jim Studt's original library was modified by Josh Larios. + +Tom Pollard, pollard@alum.mit.edu, contributed around May 20, 2008 + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice shall be +included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Much of the code was inspired by Derek Yerger's code, though I don't +think much of that remains. In any event that was.. + (copyleft) 2006 by Derek Yerger - Free to distribute freely. + +The CRC code was excerpted and inspired by the Dallas Semiconductor +sample code bearing this copyright. +//--------------------------------------------------------------------------- +// Copyright (C) 2000 Dallas Semiconductor Corporation, All Rights Reserved. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL DALLAS SEMICONDUCTOR BE LIABLE FOR ANY CLAIM, DAMAGES +// OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +// OTHER DEALINGS IN THE SOFTWARE. +// +// Except as contained in this notice, the name of Dallas Semiconductor +// shall not be used except as stated in the Dallas Semiconductor +// Branding Policy. +//-------------------------------------------------------------------------- +*/ + +#include "OneWire.h" + + +OneWire::OneWire(uint8_t pin) +{ + pinMode(pin, INPUT); + bitmask = PIN_TO_BITMASK(pin); + baseReg = PIN_TO_BASEREG(pin); +#if ONEWIRE_SEARCH + reset_search(); +#endif +} + + +// Perform the onewire reset function. We will wait up to 250uS for +// the bus to come high, if it doesn't then it is broken or shorted +// and we return a 0; +// +// Returns 1 if a device asserted a presence pulse, 0 otherwise. +// +uint8_t OneWire::reset(void) +{ + IO_REG_TYPE mask = bitmask; + volatile IO_REG_TYPE *reg IO_REG_ASM = baseReg; + uint8_t r; + uint8_t retries = 125; + + noInterrupts(); + DIRECT_MODE_INPUT(reg, mask); + interrupts(); + // wait until the wire is high... just in case + do { + if (--retries == 0) return 0; + delayMicroseconds(2); + } while ( !DIRECT_READ(reg, mask)); + + noInterrupts(); + DIRECT_WRITE_LOW(reg, mask); + DIRECT_MODE_OUTPUT(reg, mask); // drive output low + interrupts(); + delayMicroseconds(480); + noInterrupts(); + DIRECT_MODE_INPUT(reg, mask); // allow it to float + delayMicroseconds(70); + r = !DIRECT_READ(reg, mask); + interrupts(); + delayMicroseconds(410); + return r; +} + +// +// Write a bit. Port and bit is used to cut lookup time and provide +// more certain timing. +// +void OneWire::write_bit(uint8_t v) +{ + IO_REG_TYPE mask=bitmask; + volatile IO_REG_TYPE *reg IO_REG_ASM = baseReg; + + if (v & 1) { + noInterrupts(); + DIRECT_WRITE_LOW(reg, mask); + DIRECT_MODE_OUTPUT(reg, mask); // drive output low + delayMicroseconds(10); + DIRECT_WRITE_HIGH(reg, mask); // drive output high + interrupts(); + delayMicroseconds(55); + } else { + noInterrupts(); + DIRECT_WRITE_LOW(reg, mask); + DIRECT_MODE_OUTPUT(reg, mask); // drive output low + delayMicroseconds(65); + DIRECT_WRITE_HIGH(reg, mask); // drive output high + interrupts(); + delayMicroseconds(5); + } +} + +// +// Read a bit. Port and bit is used to cut lookup time and provide +// more certain timing. +// +uint8_t OneWire::read_bit(void) +{ + IO_REG_TYPE mask=bitmask; + volatile IO_REG_TYPE *reg IO_REG_ASM = baseReg; + uint8_t r; + + noInterrupts(); + DIRECT_MODE_OUTPUT(reg, mask); + DIRECT_WRITE_LOW(reg, mask); + delayMicroseconds(3); + DIRECT_MODE_INPUT(reg, mask); // let pin float, pull up will raise + delayMicroseconds(10); + r = DIRECT_READ(reg, mask); + interrupts(); + delayMicroseconds(53); + return r; +} + +// +// Write a byte. The writing code uses the active drivers to raise the +// pin high, if you need power after the write (e.g. DS18S20 in +// parasite power mode) then set 'power' to 1, otherwise the pin will +// go tri-state at the end of the write to avoid heating in a short or +// other mishap. +// +void OneWire::write(uint8_t v, uint8_t power /* = 0 */) { + uint8_t bitMask; + + for (bitMask = 0x01; bitMask; bitMask <<= 1) { + OneWire::write_bit( (bitMask & v)?1:0); + } + if ( !power) { + noInterrupts(); + DIRECT_MODE_INPUT(baseReg, bitmask); + DIRECT_WRITE_LOW(baseReg, bitmask); + interrupts(); + } +} + +void OneWire::write_bytes(const uint8_t *buf, uint16_t count, bool power /* = 0 */) { + for (uint16_t i = 0 ; i < count ; i++) + write(buf[i]); + if (!power) { + noInterrupts(); + DIRECT_MODE_INPUT(baseReg, bitmask); + DIRECT_WRITE_LOW(baseReg, bitmask); + interrupts(); + } +} + +// +// Read a byte +// +uint8_t OneWire::read() { + uint8_t bitMask; + uint8_t r = 0; + + for (bitMask = 0x01; bitMask; bitMask <<= 1) { + if ( OneWire::read_bit()) r |= bitMask; + } + return r; +} + +void OneWire::read_bytes(uint8_t *buf, uint16_t count) { + for (uint16_t i = 0 ; i < count ; i++) + buf[i] = read(); +} + +// +// Do a ROM select +// +void OneWire::select(const uint8_t rom[8]) +{ + uint8_t i; + + write(0x55); // Choose ROM + + for (i = 0; i < 8; i++) write(rom[i]); +} + +// +// Do a ROM skip +// +void OneWire::skip() +{ + write(0xCC); // Skip ROM +} + +void OneWire::depower() +{ + noInterrupts(); + DIRECT_MODE_INPUT(baseReg, bitmask); + interrupts(); +} + +#if ONEWIRE_SEARCH + +// +// You need to use this function to start a search again from the beginning. +// You do not need to do it for the first search, though you could. +// +void OneWire::reset_search() +{ + // reset the search state + LastDiscrepancy = 0; + LastDeviceFlag = FALSE; + LastFamilyDiscrepancy = 0; + for(int i = 7; ; i--) { + ROM_NO[i] = 0; + if ( i == 0) break; + } +} + +// Setup the search to find the device type 'family_code' on the next call +// to search(*newAddr) if it is present. +// +void OneWire::target_search(uint8_t family_code) +{ + // set the search state to find SearchFamily type devices + ROM_NO[0] = family_code; + for (uint8_t i = 1; i < 8; i++) + ROM_NO[i] = 0; + LastDiscrepancy = 64; + LastFamilyDiscrepancy = 0; + LastDeviceFlag = FALSE; +} + +// +// Perform a search. If this function returns a '1' then it has +// enumerated the next device and you may retrieve the ROM from the +// OneWire::address variable. If there are no devices, no further +// devices, or something horrible happens in the middle of the +// enumeration then a 0 is returned. If a new device is found then +// its address is copied to newAddr. Use OneWire::reset_search() to +// start over. +// +// --- Replaced by the one from the Dallas Semiconductor web site --- +//-------------------------------------------------------------------------- +// Perform the 1-Wire Search Algorithm on the 1-Wire bus using the existing +// search state. +// Return TRUE : device found, ROM number in ROM_NO buffer +// FALSE : device not found, end of search +// +uint8_t OneWire::search(uint8_t *newAddr) +{ + uint8_t id_bit_number; + uint8_t last_zero, rom_byte_number, search_result; + uint8_t id_bit, cmp_id_bit; + + unsigned char rom_byte_mask, search_direction; + + // initialize for search + id_bit_number = 1; + last_zero = 0; + rom_byte_number = 0; + rom_byte_mask = 1; + search_result = 0; + + // if the last call was not the last one + if (!LastDeviceFlag) + { + // 1-Wire reset + if (!reset()) + { + // reset the search + LastDiscrepancy = 0; + LastDeviceFlag = FALSE; + LastFamilyDiscrepancy = 0; + return FALSE; + } + + // issue the search command + write(0xF0); + + // loop to do the search + do + { + // read a bit and its complement + id_bit = read_bit(); + cmp_id_bit = read_bit(); + + // check for no devices on 1-wire + if ((id_bit == 1) && (cmp_id_bit == 1)) + break; + else + { + // all devices coupled have 0 or 1 + if (id_bit != cmp_id_bit) + search_direction = id_bit; // bit write value for search + else + { + // if this discrepancy if before the Last Discrepancy + // on a previous next then pick the same as last time + if (id_bit_number < LastDiscrepancy) + search_direction = ((ROM_NO[rom_byte_number] & rom_byte_mask) > 0); + else + // if equal to last pick 1, if not then pick 0 + search_direction = (id_bit_number == LastDiscrepancy); + + // if 0 was picked then record its position in LastZero + if (search_direction == 0) + { + last_zero = id_bit_number; + + // check for Last discrepancy in family + if (last_zero < 9) + LastFamilyDiscrepancy = last_zero; + } + } + + // set or clear the bit in the ROM byte rom_byte_number + // with mask rom_byte_mask + if (search_direction == 1) + ROM_NO[rom_byte_number] |= rom_byte_mask; + else + ROM_NO[rom_byte_number] &= ~rom_byte_mask; + + // serial number search direction write bit + write_bit(search_direction); + + // increment the byte counter id_bit_number + // and shift the mask rom_byte_mask + id_bit_number++; + rom_byte_mask <<= 1; + + // if the mask is 0 then go to new SerialNum byte rom_byte_number and reset mask + if (rom_byte_mask == 0) + { + rom_byte_number++; + rom_byte_mask = 1; + } + } + } + while(rom_byte_number < 8); // loop until through all ROM bytes 0-7 + + // if the search was successful then + if (!(id_bit_number < 65)) + { + // search successful so set LastDiscrepancy,LastDeviceFlag,search_result + LastDiscrepancy = last_zero; + + // check for last device + if (LastDiscrepancy == 0) + LastDeviceFlag = TRUE; + + search_result = TRUE; + } + } + + // if no device found then reset counters so next 'search' will be like a first + if (!search_result || !ROM_NO[0]) + { + LastDiscrepancy = 0; + LastDeviceFlag = FALSE; + LastFamilyDiscrepancy = 0; + search_result = FALSE; + } + for (int i = 0; i < 8; i++) newAddr[i] = ROM_NO[i]; + return search_result; + } + +#endif + +#if ONEWIRE_CRC +// The 1-Wire CRC scheme is described in Maxim Application Note 27: +// "Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products" +// + +#if ONEWIRE_CRC8_TABLE +// This table comes from Dallas sample code where it is freely reusable, +// though Copyright (C) 2000 Dallas Semiconductor Corporation +static const uint8_t PROGMEM dscrc_table[] = { + 0, 94,188,226, 97, 63,221,131,194,156,126, 32,163,253, 31, 65, + 157,195, 33,127,252,162, 64, 30, 95, 1,227,189, 62, 96,130,220, + 35,125,159,193, 66, 28,254,160,225,191, 93, 3,128,222, 60, 98, + 190,224, 2, 92,223,129, 99, 61,124, 34,192,158, 29, 67,161,255, + 70, 24,250,164, 39,121,155,197,132,218, 56,102,229,187, 89, 7, + 219,133,103, 57,186,228, 6, 88, 25, 71,165,251,120, 38,196,154, + 101, 59,217,135, 4, 90,184,230,167,249, 27, 69,198,152,122, 36, + 248,166, 68, 26,153,199, 37,123, 58,100,134,216, 91, 5,231,185, + 140,210, 48,110,237,179, 81, 15, 78, 16,242,172, 47,113,147,205, + 17, 79,173,243,112, 46,204,146,211,141,111, 49,178,236, 14, 80, + 175,241, 19, 77,206,144,114, 44,109, 51,209,143, 12, 82,176,238, + 50,108,142,208, 83, 13,239,177,240,174, 76, 18,145,207, 45,115, + 202,148,118, 40,171,245, 23, 73, 8, 86,180,234,105, 55,213,139, + 87, 9,235,181, 54,104,138,212,149,203, 41,119,244,170, 72, 22, + 233,183, 85, 11,136,214, 52,106, 43,117,151,201, 74, 20,246,168, + 116, 42,200,150, 21, 75,169,247,182,232, 10, 84,215,137,107, 53}; + +// +// Compute a Dallas Semiconductor 8 bit CRC. These show up in the ROM +// and the registers. (note: this might better be done without to +// table, it would probably be smaller and certainly fast enough +// compared to all those delayMicrosecond() calls. But I got +// confused, so I use this table from the examples.) +// +uint8_t OneWire::crc8(const uint8_t *addr, uint8_t len) +{ + uint8_t crc = 0; + + while (len--) { + crc = pgm_read_byte(dscrc_table + (crc ^ *addr++)); + } + return crc; +} +#else +// +// Compute a Dallas Semiconductor 8 bit CRC directly. +// this is much slower, but much smaller, than the lookup table. +// +uint8_t OneWire::crc8(const uint8_t *addr, uint8_t len) +{ + uint8_t crc = 0; + + while (len--) { + uint8_t inbyte = *addr++; + for (uint8_t i = 8; i; i--) { + uint8_t mix = (crc ^ inbyte) & 0x01; + crc >>= 1; + if (mix) crc ^= 0x8C; + inbyte >>= 1; + } + } + return crc; +} +#endif + +#if ONEWIRE_CRC16 +bool OneWire::check_crc16(const uint8_t* input, uint16_t len, const uint8_t* inverted_crc, uint16_t crc) +{ + crc = ~crc16(input, len, crc); + return (crc & 0xFF) == inverted_crc[0] && (crc >> 8) == inverted_crc[1]; +} + +uint16_t OneWire::crc16(const uint8_t* input, uint16_t len, uint16_t crc) +{ + static const uint8_t oddparity[16] = + { 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0 }; + + for (uint16_t i = 0 ; i < len ; i++) { + // Even though we're just copying a byte from the input, + // we'll be doing 16-bit computation with it. + uint16_t cdata = input[i]; + cdata = (cdata ^ crc) & 0xff; + crc >>= 8; + + if (oddparity[cdata & 0x0F] ^ oddparity[cdata >> 4]) + crc ^= 0xC001; + + cdata <<= 6; + crc ^= cdata; + cdata <<= 1; + crc ^= cdata; + } + return crc; +} +#endif + +#endif diff --git a/hardware/digistump/avr/libraries/OneWire/OneWire.h b/hardware/digistump/avr/libraries/OneWire/OneWire.h new file mode 100644 index 0000000..916c529 --- /dev/null +++ b/hardware/digistump/avr/libraries/OneWire/OneWire.h @@ -0,0 +1,229 @@ +#ifndef OneWire_h +#define OneWire_h + +#include + +#if ARDUINO >= 100 +#include "Arduino.h" // for delayMicroseconds, digitalPinToBitMask, etc +#else +#include "WProgram.h" // for delayMicroseconds +#include "pins_arduino.h" // for digitalPinToBitMask, etc +#endif + +// You can exclude certain features from OneWire. In theory, this +// might save some space. In practice, the compiler automatically +// removes unused code (technically, the linker, using -fdata-sections +// and -ffunction-sections when compiling, and Wl,--gc-sections +// when linking), so most of these will not result in any code size +// reduction. Well, unless you try to use the missing features +// and redesign your program to not need them! ONEWIRE_CRC8_TABLE +// is the exception, because it selects a fast but large algorithm +// or a small but slow algorithm. + +// you can exclude onewire_search by defining that to 0 +#ifndef ONEWIRE_SEARCH +#define ONEWIRE_SEARCH 1 +#endif + +// You can exclude CRC checks altogether by defining this to 0 +#ifndef ONEWIRE_CRC +#define ONEWIRE_CRC 1 +#endif + +// Select the table-lookup method of computing the 8-bit CRC +// by setting this to 1. The lookup table enlarges code size by +// about 250 bytes. It does NOT consume RAM (but did in very +// old versions of OneWire). If you disable this, a slower +// but very compact algorithm is used. +#ifndef ONEWIRE_CRC8_TABLE +#define ONEWIRE_CRC8_TABLE 1 +#endif + +// You can allow 16-bit CRC checks by defining this to 1 +// (Note that ONEWIRE_CRC must also be 1.) +#ifndef ONEWIRE_CRC16 +#define ONEWIRE_CRC16 1 +#endif + +#define FALSE 0 +#define TRUE 1 + +// Platform specific I/O definitions + +#if defined(__AVR__) +#define PIN_TO_BASEREG(pin) (portInputRegister(digitalPinToPort(pin))) +#define PIN_TO_BITMASK(pin) (digitalPinToBitMask(pin)) +#define IO_REG_TYPE uint8_t +#define IO_REG_ASM asm("r30") +#define DIRECT_READ(base, mask) (((*(base)) & (mask)) ? 1 : 0) +#define DIRECT_MODE_INPUT(base, mask) ((*((base)+1)) &= ~(mask)) +#define DIRECT_MODE_OUTPUT(base, mask) ((*((base)+1)) |= (mask)) +#define DIRECT_WRITE_LOW(base, mask) ((*((base)+2)) &= ~(mask)) +#define DIRECT_WRITE_HIGH(base, mask) ((*((base)+2)) |= (mask)) + +#elif defined(__MK20DX128__) +#define PIN_TO_BASEREG(pin) (portOutputRegister(pin)) +#define PIN_TO_BITMASK(pin) (1) +#define IO_REG_TYPE uint8_t +#define IO_REG_ASM +#define DIRECT_READ(base, mask) (*((base)+512)) +#define DIRECT_MODE_INPUT(base, mask) (*((base)+640) = 0) +#define DIRECT_MODE_OUTPUT(base, mask) (*((base)+640) = 1) +#define DIRECT_WRITE_LOW(base, mask) (*((base)+256) = 1) +#define DIRECT_WRITE_HIGH(base, mask) (*((base)+128) = 1) + +#elif defined(__SAM3X8E__) +// Arduino 1.5.1 may have a bug in delayMicroseconds() on Arduino Due. +// http://arduino.cc/forum/index.php/topic,141030.msg1076268.html#msg1076268 +// If you have trouble with OneWire on Arduino Due, please check the +// status of delayMicroseconds() before reporting a bug in OneWire! +#define PIN_TO_BASEREG(pin) (&(digitalPinToPort(pin)->PIO_PER)) +#define PIN_TO_BITMASK(pin) (digitalPinToBitMask(pin)) +#define IO_REG_TYPE uint32_t +#define IO_REG_ASM +#define DIRECT_READ(base, mask) (((*((base)+15)) & (mask)) ? 1 : 0) +#define DIRECT_MODE_INPUT(base, mask) ((*((base)+5)) = (mask)) +#define DIRECT_MODE_OUTPUT(base, mask) ((*((base)+4)) = (mask)) +#define DIRECT_WRITE_LOW(base, mask) ((*((base)+13)) = (mask)) +#define DIRECT_WRITE_HIGH(base, mask) ((*((base)+12)) = (mask)) +#ifndef PROGMEM +#define PROGMEM +#endif +#ifndef pgm_read_byte +#define pgm_read_byte(addr) (*(const uint8_t *)(addr)) +#endif + +#elif defined(__PIC32MX__) +#define PIN_TO_BASEREG(pin) (portModeRegister(digitalPinToPort(pin))) +#define PIN_TO_BITMASK(pin) (digitalPinToBitMask(pin)) +#define IO_REG_TYPE uint32_t +#define IO_REG_ASM +#define DIRECT_READ(base, mask) (((*(base+4)) & (mask)) ? 1 : 0) //PORTX + 0x10 +#define DIRECT_MODE_INPUT(base, mask) ((*(base+2)) = (mask)) //TRISXSET + 0x08 +#define DIRECT_MODE_OUTPUT(base, mask) ((*(base+1)) = (mask)) //TRISXCLR + 0x04 +#define DIRECT_WRITE_LOW(base, mask) ((*(base+8+1)) = (mask)) //LATXCLR + 0x24 +#define DIRECT_WRITE_HIGH(base, mask) ((*(base+8+2)) = (mask)) //LATXSET + 0x28 + +#else +#error "Please define I/O register types here" +#endif + + +class OneWire +{ + private: + IO_REG_TYPE bitmask; + volatile IO_REG_TYPE *baseReg; + +#if ONEWIRE_SEARCH + // global search state + unsigned char ROM_NO[8]; + uint8_t LastDiscrepancy; + uint8_t LastFamilyDiscrepancy; + uint8_t LastDeviceFlag; +#endif + + public: + OneWire( uint8_t pin); + + // Perform a 1-Wire reset cycle. Returns 1 if a device responds + // with a presence pulse. Returns 0 if there is no device or the + // bus is shorted or otherwise held low for more than 250uS + uint8_t reset(void); + + // Issue a 1-Wire rom select command, you do the reset first. + void select(const uint8_t rom[8]); + + // Issue a 1-Wire rom skip command, to address all on bus. + void skip(void); + + // Write a byte. If 'power' is one then the wire is held high at + // the end for parasitically powered devices. You are responsible + // for eventually depowering it by calling depower() or doing + // another read or write. + void write(uint8_t v, uint8_t power = 0); + + void write_bytes(const uint8_t *buf, uint16_t count, bool power = 0); + + // Read a byte. + uint8_t read(void); + + void read_bytes(uint8_t *buf, uint16_t count); + + // Write a bit. The bus is always left powered at the end, see + // note in write() about that. + void write_bit(uint8_t v); + + // Read a bit. + uint8_t read_bit(void); + + // Stop forcing power onto the bus. You only need to do this if + // you used the 'power' flag to write() or used a write_bit() call + // and aren't about to do another read or write. You would rather + // not leave this powered if you don't have to, just in case + // someone shorts your bus. + void depower(void); + +#if ONEWIRE_SEARCH + // Clear the search state so that if will start from the beginning again. + void reset_search(); + + // Setup the search to find the device type 'family_code' on the next call + // to search(*newAddr) if it is present. + void target_search(uint8_t family_code); + + // Look for the next device. Returns 1 if a new address has been + // returned. A zero might mean that the bus is shorted, there are + // no devices, or you have already retrieved all of them. It + // might be a good idea to check the CRC to make sure you didn't + // get garbage. The order is deterministic. You will always get + // the same devices in the same order. + uint8_t search(uint8_t *newAddr); +#endif + +#if ONEWIRE_CRC + // Compute a Dallas Semiconductor 8 bit CRC, these are used in the + // ROM and scratchpad registers. + static uint8_t crc8(const uint8_t *addr, uint8_t len); + +#if ONEWIRE_CRC16 + // Compute the 1-Wire CRC16 and compare it against the received CRC. + // Example usage (reading a DS2408): + // // Put everything in a buffer so we can compute the CRC easily. + // uint8_t buf[13]; + // buf[0] = 0xF0; // Read PIO Registers + // buf[1] = 0x88; // LSB address + // buf[2] = 0x00; // MSB address + // WriteBytes(net, buf, 3); // Write 3 cmd bytes + // ReadBytes(net, buf+3, 10); // Read 6 data bytes, 2 0xFF, 2 CRC16 + // if (!CheckCRC16(buf, 11, &buf[11])) { + // // Handle error. + // } + // + // @param input - Array of bytes to checksum. + // @param len - How many bytes to use. + // @param inverted_crc - The two CRC16 bytes in the received data. + // This should just point into the received data, + // *not* at a 16-bit integer. + // @param crc - The crc starting value (optional) + // @return True, iff the CRC matches. + static bool check_crc16(const uint8_t* input, uint16_t len, const uint8_t* inverted_crc, uint16_t crc = 0); + + // Compute a Dallas Semiconductor 16 bit CRC. This is required to check + // the integrity of data received from many 1-Wire devices. Note that the + // CRC computed here is *not* what you'll get from the 1-Wire network, + // for two reasons: + // 1) The CRC is transmitted bitwise inverted. + // 2) Depending on the endian-ness of your processor, the binary + // representation of the two-byte return value may have a different + // byte order than the two bytes you get from 1-Wire. + // @param input - Array of bytes to checksum. + // @param len - How many bytes to use. + // @param crc - The crc starting value (optional) + // @return The CRC16, as defined by Dallas Semiconductor. + static uint16_t crc16(const uint8_t* input, uint16_t len, uint16_t crc = 0); +#endif +#endif +}; + +#endif diff --git a/hardware/digistump/avr/libraries/OneWire/examples/DS18x20_Temperature/DS18x20_Temperature.pde b/hardware/digistump/avr/libraries/OneWire/examples/DS18x20_Temperature/DS18x20_Temperature.pde new file mode 100644 index 0000000..68ca194 --- /dev/null +++ b/hardware/digistump/avr/libraries/OneWire/examples/DS18x20_Temperature/DS18x20_Temperature.pde @@ -0,0 +1,112 @@ +#include + +// OneWire DS18S20, DS18B20, DS1822 Temperature Example +// +// http://www.pjrc.com/teensy/td_libs_OneWire.html +// +// The DallasTemperature library can do all this work for you! +// http://milesburton.com/Dallas_Temperature_Control_Library + +OneWire ds(10); // on pin 10 (a 4.7K resistor is necessary) + +void setup(void) { + Serial.begin(9600); +} + +void loop(void) { + byte i; + byte present = 0; + byte type_s; + byte data[12]; + byte addr[8]; + float celsius, fahrenheit; + + if ( !ds.search(addr)) { + Serial.println("No more addresses."); + Serial.println(); + ds.reset_search(); + delay(250); + return; + } + + Serial.print("ROM ="); + for( i = 0; i < 8; i++) { + Serial.write(' '); + Serial.print(addr[i], HEX); + } + + if (OneWire::crc8(addr, 7) != addr[7]) { + Serial.println("CRC is not valid!"); + return; + } + Serial.println(); + + // the first ROM byte indicates which chip + switch (addr[0]) { + case 0x10: + Serial.println(" Chip = DS18S20"); // or old DS1820 + type_s = 1; + break; + case 0x28: + Serial.println(" Chip = DS18B20"); + type_s = 0; + break; + case 0x22: + Serial.println(" Chip = DS1822"); + type_s = 0; + break; + default: + Serial.println("Device is not a DS18x20 family device."); + return; + } + + ds.reset(); + ds.select(addr); + ds.write(0x44, 1); // start conversion, with parasite power on at the end + + delay(1000); // maybe 750ms is enough, maybe not + // we might do a ds.depower() here, but the reset will take care of it. + + present = ds.reset(); + ds.select(addr); + ds.write(0xBE); // Read Scratchpad + + Serial.print(" Data = "); + Serial.print(present, HEX); + Serial.print(" "); + for ( i = 0; i < 9; i++) { // we need 9 bytes + data[i] = ds.read(); + Serial.print(data[i], HEX); + Serial.print(" "); + } + Serial.print(" CRC="); + Serial.print(OneWire::crc8(data, 8), HEX); + Serial.println(); + + // Convert the data to actual temperature + // because the result is a 16 bit signed integer, it should + // be stored to an "int16_t" type, which is always 16 bits + // even when compiled on a 32 bit processor. + int16_t raw = (data[1] << 8) | data[0]; + if (type_s) { + raw = raw << 3; // 9 bit resolution default + if (data[7] == 0x10) { + // "count remain" gives full 12 bit resolution + raw = (raw & 0xFFF0) + 12 - data[6]; + } + } else { + byte cfg = (data[4] & 0x60); + // at lower res, the low bits are undefined, so let's zero them + if (cfg == 0x00) raw = raw & ~7; // 9 bit resolution, 93.75 ms + else if (cfg == 0x20) raw = raw & ~3; // 10 bit res, 187.5 ms + else if (cfg == 0x40) raw = raw & ~1; // 11 bit res, 375 ms + //// default is 12 bit resolution, 750 ms conversion time + } + celsius = (float)raw / 16.0; + fahrenheit = celsius * 1.8 + 32.0; + Serial.print(" Temperature = "); + Serial.print(celsius); + Serial.print(" Celsius, "); + Serial.print(fahrenheit); + Serial.println(" Fahrenheit"); +} diff --git a/hardware/digistump/avr/libraries/OneWire/examples/DS2408_Switch/DS2408_Switch.pde b/hardware/digistump/avr/libraries/OneWire/examples/DS2408_Switch/DS2408_Switch.pde new file mode 100644 index 0000000..d171f9b --- /dev/null +++ b/hardware/digistump/avr/libraries/OneWire/examples/DS2408_Switch/DS2408_Switch.pde @@ -0,0 +1,77 @@ +#include + +/* + * DS2408 8-Channel Addressable Switch + * + * Writte by Glenn Trewitt, glenn at trewitt dot org + * + * Some notes about the DS2408: + * - Unlike most input/output ports, the DS2408 doesn't have mode bits to + * set whether the pins are input or output. If you issue a read command, + * they're inputs. If you write to them, they're outputs. + * - For reading from a switch, you should use 10K pull-up resisters. + */ + +void PrintBytes(uint8_t* addr, uint8_t count, bool newline=0) { + for (uint8_t i = 0; i < count; i++) { + Serial.print(addr[i]>>4, HEX); + Serial.print(addr[i]&0x0f, HEX); + } + if (newline) + Serial.println(); +} + +void ReadAndReport(OneWire* net, uint8_t* addr) { + Serial.print(" Reading DS2408 "); + PrintBytes(addr, 8); + Serial.println(); + + uint8_t buf[13]; // Put everything in the buffer so we can compute CRC easily. + buf[0] = 0xF0; // Read PIO Registers + buf[1] = 0x88; // LSB address + buf[2] = 0x00; // MSB address + net->write_bytes(buf, 3); + net->read_bytes(buf+3, 10); // 3 cmd bytes, 6 data bytes, 2 0xFF, 2 CRC16 + net->reset(); + + if (!OneWire::check_crc16(buf, 11, &buf[11])) { + Serial.print("CRC failure in DS2408 at "); + PrintBytes(addr, 8, true); + return; + } + Serial.print(" DS2408 data = "); + // First 3 bytes contain command, register address. + Serial.println(buf[3], BIN); +} + +OneWire net(10); // on pin 10 + +void setup(void) { + Serial.begin(9600); +} + +void loop(void) { + byte i; + byte present = 0; + byte addr[8]; + + if (!net.search(addr)) { + Serial.print("No more addresses.\n"); + net.reset_search(); + delay(1000); + return; + } + + if (OneWire::crc8(addr, 7) != addr[7]) { + Serial.print("CRC is not valid!\n"); + return; + } + + if (addr[0] != 0x29) { + PrintBytes(addr, 8); + Serial.print(" is not a DS2408.\n"); + return; + } + + ReadAndReport(&net, addr); +} diff --git a/hardware/digistump/avr/libraries/OneWire/examples/DS250x_PROM/DS250x_PROM.pde b/hardware/digistump/avr/libraries/OneWire/examples/DS250x_PROM/DS250x_PROM.pde new file mode 100644 index 0000000..a85b1c2 --- /dev/null +++ b/hardware/digistump/avr/libraries/OneWire/examples/DS250x_PROM/DS250x_PROM.pde @@ -0,0 +1,90 @@ +/* +DS250x add-only programmable memory reader w/SKIP ROM. + + The DS250x is a 512/1024bit add-only PROM(you can add data but cannot change the old one) that's used mainly for device identification purposes + like serial number, mfgr data, unique identifiers, etc. It uses the Maxim 1-wire bus. + + This sketch will use the SKIP ROM function that skips the 1-Wire search phase since we only have one device connected in the bus on digital pin 6. + If more than one device is connected to the bus, it will fail. + Sketch will not verify if device connected is from the DS250x family since the skip rom function effectively skips the family-id byte readout. + thus it is possible to run this sketch with any Maxim OneWire device in which case the command CRC will most likely fail. + Sketch will only read the first page of memory(32bits) starting from the lower address(0000h), if more than 1 device is present, then use the sketch with search functions. + Remember to put a 4.7K pullup resistor between pin 6 and +Vcc + + To change the range or ammount of data to read, simply change the data array size, LSB/MSB addresses and for loop iterations + + This example code is in the public domain and is provided AS-IS. + + Built with Arduino 0022 and PJRC OneWire 2.0 library http://www.pjrc.com/teensy/td_libs_OneWire.html + + created by Guillermo Lovato + march/2011 + + */ + +#include +OneWire ds(6); // OneWire bus on digital pin 6 +void setup() { + Serial.begin (9600); +} + +void loop() { + byte i; // This is for the for loops + boolean present; // device present var + byte data[32]; // container for the data from device + byte leemem[3] = { // array with the commands to initiate a read, DS250x devices expect 3 bytes to start a read: command,LSB&MSB adresses + 0xF0 , 0x00 , 0x00 }; // 0xF0 is the Read Data command, followed by 00h 00h as starting address(the beginning, 0000h) + byte ccrc; // Variable to store the command CRC + byte ccrc_calc; + + present = ds.reset(); // OneWire bus reset, always needed to start operation on the bus, returns a 1/TRUE if there's a device present. + ds.skip(); // Skip ROM search + + if (present == TRUE){ // We only try to read the data if there's a device present + Serial.println("DS250x device present"); + ds.write(leemem[0],1); // Read data command, leave ghost power on + ds.write(leemem[1],1); // LSB starting address, leave ghost power on + ds.write(leemem[2],1); // MSB starting address, leave ghost power on + + ccrc = ds.read(); // DS250x generates a CRC for the command we sent, we assign a read slot and store it's value + ccrc_calc = OneWire::crc8(leemem, 3); // We calculate the CRC of the commands we sent using the library function and store it + + if ( ccrc_calc != ccrc) { // Then we compare it to the value the ds250x calculated, if it fails, we print debug messages and abort + Serial.println("Invalid command CRC!"); + Serial.print("Calculated CRC:"); + Serial.println(ccrc_calc,HEX); // HEX makes it easier to observe and compare + Serial.print("DS250x readback CRC:"); + Serial.println(ccrc,HEX); + return; // Since CRC failed, we abort the rest of the loop and start over + } + Serial.println("Data is: "); // For the printout of the data + for ( i = 0; i < 32; i++) { // Now it's time to read the PROM data itself, each page is 32 bytes so we need 32 read commands + data[i] = ds.read(); // we store each read byte to a different position in the data array + Serial.print(data[i]); // printout in ASCII + Serial.print(" "); // blank space + } + Serial.println(); + delay(5000); // Delay so we don't saturate the serial output + } + else { // Nothing is connected in the bus + Serial.println("Nothing connected"); + delay(3000); + } +} + + + + + + + + + + + + + + + + + diff --git a/hardware/digistump/avr/libraries/OneWire/examples/Digispark_Example/Digispark_Example.ino b/hardware/digistump/avr/libraries/OneWire/examples/Digispark_Example/Digispark_Example.ino new file mode 100644 index 0000000..8963e85 --- /dev/null +++ b/hardware/digistump/avr/libraries/OneWire/examples/Digispark_Example/Digispark_Example.ino @@ -0,0 +1,76 @@ + +#include +#include +#define DS18S20_ID 0x10 +#define DS18B20_ID 0x28 +int temp; + + +OneWire ds(5); + +byte data[12]; +byte addr[8]; + +boolean readTemperature(){ + + + + //find a device + + + if (!ds.search(addr)) { + ds.reset_search(); + return false; + } + if (OneWire::crc8( addr, 7) != addr[7]) { + return false; + } + if (addr[0] != DS18S20_ID && addr[0] != DS18B20_ID) { + return false; + } + + ds.reset(); + ds.select(addr); + // Start conversion + ds.write(0x44, 1); + // Wait some time... + } + +boolean getTemperature(){ + byte i; + byte present = 0; + present = ds.reset(); + ds.select(addr); + // Issue Read scratchpad command + ds.write(0xBE); + // Receive 9 bytes + for ( i = 0; i < 9; i++) { + data[i] = ds.read(); + } + // Calculate temperature value + temp = ((( (data[1] << 8) + data[0] )*0.0625)*1.8)+32; + return true; + +} + +void setup(){ + DigiUSB.begin(); + DigiUSB.print("Start"); +} + + +void loop(){ + + + readTemperature(); + DigiUSB.delay(1000); + getTemperature(); + DigiUSB.println(temp); + + DigiUSB.delay(1000); + + + +} + + diff --git a/hardware/digistump/avr/libraries/OneWire/keywords.txt b/hardware/digistump/avr/libraries/OneWire/keywords.txt new file mode 100644 index 0000000..bee5d90 --- /dev/null +++ b/hardware/digistump/avr/libraries/OneWire/keywords.txt @@ -0,0 +1,38 @@ +####################################### +# Syntax Coloring Map For OneWire +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +OneWire KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +reset KEYWORD2 +write_bit KEYWORD2 +read_bit KEYWORD2 +write KEYWORD2 +write_bytes KEYWORD2 +read KEYWORD2 +read_bytes KEYWORD2 +select KEYWORD2 +skip KEYWORD2 +depower KEYWORD2 +reset_search KEYWORD2 +search KEYWORD2 +crc8 KEYWORD2 +crc16 KEYWORD2 +check_crc16 KEYWORD2 + +####################################### +# Instances (KEYWORD2) +####################################### + + +####################################### +# Constants (LITERAL1) +####################################### diff --git a/hardware/digistump/avr/libraries/RF24/.gitignore b/hardware/digistump/avr/libraries/RF24/.gitignore new file mode 100644 index 0000000..ac32040 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/.gitignore @@ -0,0 +1,14 @@ +*.bak +*.o +.*.swp +*.orig +.swp +docs/ +output/ +ojam/ +out/ +16000000/ +8000000/ +out_native/ +version.h +Session.vim diff --git a/hardware/digistump/avr/libraries/RF24/Doxyfile b/hardware/digistump/avr/libraries/RF24/Doxyfile new file mode 100644 index 0000000..4604afc --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/Doxyfile @@ -0,0 +1,1551 @@ +# Doxyfile 1.6.3 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project +# +# All text after a hash (#) is considered a comment and will be ignored +# The format is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" ") + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all +# text before the first occurrence of this tag. Doxygen uses libiconv (or the +# iconv built into libc) for the transcoding. See +# http://www.gnu.org/software/libiconv for the list of possible encodings. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded +# by quotes) that should identify the project. + +PROJECT_NAME = RF24 + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = v1 + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) +# base path where the generated documentation will be put. +# If a relative path is entered, it will be relative to the location +# where doxygen was started. If left blank the current directory will be used. + +OUTPUT_DIRECTORY = docs + +# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create +# 4096 sub-directories (in 2 levels) under the output directory of each output +# format and will distribute the generated files over these directories. +# Enabling this option can be useful when feeding doxygen a huge amount of +# source files, where putting all generated files in the same directory would +# otherwise cause performance problems for the file system. + +CREATE_SUBDIRS = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# The default language is English, other supported languages are: +# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, +# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, +# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English +# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, +# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, +# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. + +OUTPUT_LANGUAGE = English + +# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will +# include brief member descriptions after the members that are listed in +# the file and class documentation (similar to JavaDoc). +# Set to NO to disable this. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend +# the brief description of a member or function before the detailed description. +# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator +# that is used to form the text in various listings. Each string +# in this list, if found as the leading text of the brief description, will be +# stripped from the text and the result after processing the whole list, is +# used as the annotated text. Otherwise, the brief description is used as-is. +# If left blank, the following values are used ("$name" is automatically +# replaced with the name of the entity): "The $name class" "The $name widget" +# "The $name file" "is" "provides" "specifies" "contains" +# "represents" "a" "an" "the" + +ABBREVIATE_BRIEF = + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# Doxygen will generate a detailed section even if there is only a brief +# description. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. Constructors, destructors and assignment +# operators of the base classes will not be shown. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full +# path before files name in the file list and in the header files. If set +# to NO the shortest path that makes the file name unique will be used. + +FULL_PATH_NAMES = YES + +# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag +# can be used to strip a user-defined part of the path. Stripping is +# only done if one of the specified strings matches the left-hand part of +# the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the +# path to strip. + +STRIP_FROM_PATH = + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of +# the path mentioned in the documentation of a class, which tells +# the reader which header file to include in order to use a class. +# If left blank only the name of the header file containing the class +# definition is used. Otherwise one should specify the include paths that +# are normally passed to the compiler using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter +# (but less readable) file names. This can be useful is your file systems +# doesn't support long names like on DOS, Mac, or CD-ROM. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen +# will interpret the first line (until the first dot) of a JavaDoc-style +# comment as the brief description. If set to NO, the JavaDoc +# comments will behave just like regular Qt-style comments +# (thus requiring an explicit @brief command for a brief description.) + +JAVADOC_AUTOBRIEF = YES + +# If the QT_AUTOBRIEF tag is set to YES then Doxygen will +# interpret the first line (until the first dot) of a Qt-style +# comment as the brief description. If set to NO, the comments +# will behave just like regular Qt-style comments (thus requiring +# an explicit \brief command for a brief description.) + +QT_AUTOBRIEF = YES + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen +# treat a multi-line C++ special comment block (i.e. a block of //! or /// +# comments) as a brief description. This used to be the default behaviour. +# The new default is to treat a multi-line C++ comment block as a detailed +# description. Set this tag to YES if you prefer the old behaviour instead. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented +# member inherits the documentation from any documented member that it +# re-implements. + +INHERIT_DOCS = YES + +# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce +# a new page for each member. If set to NO, the documentation of a member will +# be part of the file/class/namespace that contains it. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. +# Doxygen uses this value to replace tabs by spaces in code fragments. + +TAB_SIZE = 8 + +# This tag can be used to specify a number of aliases that acts +# as commands in the documentation. An alias has the form "name=value". +# For example adding "sideeffect=\par Side Effects:\n" will allow you to +# put the command \sideeffect (or @sideeffect) in the documentation, which +# will result in a user-defined paragraph with heading "Side Effects:". +# You can put \n's in the value part of an alias to insert newlines. + +ALIASES = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C +# sources only. Doxygen will then generate output that is more tailored for C. +# For instance, some of the names that are used will be different. The list +# of all members will be omitted, etc. + +OPTIMIZE_OUTPUT_FOR_C = NO + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java +# sources only. Doxygen will then generate output that is more tailored for +# Java. For instance, namespaces will be presented as packages, qualified +# scopes will look different, etc. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran +# sources only. Doxygen will then generate output that is more tailored for +# Fortran. + +OPTIMIZE_FOR_FORTRAN = NO + +# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL +# sources. Doxygen will then generate output that is tailored for +# VHDL. + +OPTIMIZE_OUTPUT_VHDL = NO + +# Doxygen selects the parser to use depending on the extension of the files it parses. +# With this tag you can assign which parser to use for a given extension. +# Doxygen has a built-in mapping, but you can override or extend it using this tag. +# The format is ext=language, where ext is a file extension, and language is one of +# the parsers supported by doxygen: IDL, Java, Javascript, C#, C, C++, D, PHP, +# Objective-C, Python, Fortran, VHDL, C, C++. For instance to make doxygen treat +# .inc files as Fortran files (default is PHP), and .f files as C (default is Fortran), +# use: inc=Fortran f=C. Note that for custom extensions you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. + +EXTENSION_MAPPING = + +# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want +# to include (a tag file for) the STL sources as input, then you should +# set this tag to YES in order to let doxygen match functions declarations and +# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. +# func(std::string) {}). This also make the inheritance and collaboration +# diagrams that involve STL classes more complete and accurate. + +BUILTIN_STL_SUPPORT = NO + +# If you use Microsoft's C++/CLI language, you should set this option to YES to +# enable parsing support. + +CPP_CLI_SUPPORT = NO + +# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. +# Doxygen will parse them like normal C++ but will assume all classes use public +# instead of private inheritance when no explicit protection keyword is present. + +SIP_SUPPORT = NO + +# For Microsoft's IDL there are propget and propput attributes to indicate getter +# and setter methods for a property. Setting this option to YES (the default) +# will make doxygen to replace the get and set methods by a property in the +# documentation. This will only work if the methods are indeed getting or +# setting a simple type. If this is not the case, or you want to show the +# methods anyway, you should set this option to NO. + +IDL_PROPERTY_SUPPORT = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. + +DISTRIBUTE_GROUP_DOC = NO + +# Set the SUBGROUPING tag to YES (the default) to allow class member groups of +# the same type (for instance a group of public functions) to be put as a +# subgroup of that type (e.g. under the Public Functions section). Set it to +# NO to prevent subgrouping. Alternatively, this can be done per class using +# the \nosubgrouping command. + +SUBGROUPING = YES + +# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum +# is documented as struct, union, or enum with the name of the typedef. So +# typedef struct TypeS {} TypeT, will appear in the documentation as a struct +# with name TypeT. When disabled the typedef will appear as a member of a file, +# namespace, or class. And the struct will be named TypeS. This can typically +# be useful for C code in case the coding convention dictates that all compound +# types are typedef'ed and only the typedef is referenced, never the tag name. + +TYPEDEF_HIDES_STRUCT = NO + +# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to +# determine which symbols to keep in memory and which to flush to disk. +# When the cache is full, less often used symbols will be written to disk. +# For small to medium size projects (<1000 input files) the default value is +# probably good enough. For larger projects a too small cache size can cause +# doxygen to be busy swapping symbols to and from disk most of the time +# causing a significant performance penality. +# If the system has enough physical memory increasing the cache will improve the +# performance by keeping more symbols in memory. Note that the value works on +# a logarithmic scale so increasing the size by one will rougly double the +# memory usage. The cache size is given by this formula: +# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, +# corresponding to a cache size of 2^16 = 65536 symbols + +SYMBOL_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. +# Private class members and static file members will be hidden unless +# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES + +EXTRACT_ALL = NO + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class +# will be included in the documentation. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_STATIC tag is set to YES all static members of a file +# will be included in the documentation. + +EXTRACT_STATIC = NO + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) +# defined locally in source files will be included in the documentation. +# If set to NO only classes defined in header files are included. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. When set to YES local +# methods, which are defined in the implementation section but not in +# the interface are included in the documentation. +# If set to NO (the default) only methods in the interface are included. + +EXTRACT_LOCAL_METHODS = NO + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base +# name of the file that contains the anonymous namespace. By default +# anonymous namespace are hidden. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all +# undocumented members of documented classes, files or namespaces. +# If set to NO (the default) these members will be included in the +# various overviews, but no documentation section is generated. +# This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. +# If set to NO (the default) these classes will be included in the various +# overviews. This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation +# that is typed after a \internal command is included. If the tag is set +# to NO (the default) then the documentation will be excluded. +# Set it to YES to include the internal documentation. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate +# file names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. + +CASE_SENSE_NAMES = YES + +# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen +# will show members with their full class and namespace scopes in the +# documentation. If set to YES the scope will be hidden. + +HIDE_SCOPE_NAMES = NO + +# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen +# will put a list of the files that are included by a file in the documentation +# of that file. + +SHOW_INCLUDE_FILES = YES + +# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen +# will list include files with double quotes in the documentation +# rather than with sharp brackets. + +FORCE_LOCAL_INCLUDES = NO + +# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] +# is inserted in the documentation for inline members. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen +# will sort the (detailed) documentation of file and class members +# alphabetically by member name. If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the (brief and detailed) documentation of class members so that constructors and destructors are listed first. If set to NO (the default) the constructors will appear in the respective orders defined by SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the +# hierarchy of group names into alphabetical order. If set to NO (the default) +# the group names will appear in their defined order. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if sectionname ... \endif. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or define consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and defines in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = YES + +# If the sources in your project are distributed over multiple directories +# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy +# in the documentation. The default is NO. + +SHOW_DIRECTORIES = NO + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. +# This will remove the Files entry from the Quick Index and from the +# Folder Tree View (if specified). The default is YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the +# Namespaces page. +# This will remove the Namespaces entry from the Quick Index +# and from the Folder Tree View (if specified). The default is YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command , where is the value of +# the FILE_VERSION_FILTER tag, and is the name of an input file +# provided by doxygen. Whatever the program writes to standard output +# is used as the file version. See the manual for examples. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed by +# doxygen. The layout file controls the global structure of the generated output files +# in an output format independent way. The create the layout file that represents +# doxygen's defaults, run doxygen with the -l option. You can optionally specify a +# file name after the option, if omitted DoxygenLayout.xml will be used as the name +# of the layout file. + +LAYOUT_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = YES + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# This WARN_NO_PARAMDOC option can be abled to get warnings for +# functions that are documented, but have no documentation for their parameters +# or return value. If set to NO (the default) doxygen will only warn about +# wrong or incomplete parameter documentation, but not about the absence of +# documentation. + +WARN_NO_PARAMDOC = NO + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. Optionally the format may contain +# $version, which will be replaced by the version of the file (if it could +# be obtained via FILE_VERSION_FILTER) + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = . + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is +# also the default input encoding. Doxygen uses libiconv (or the iconv built +# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for +# the list of possible encodings. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx +# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 + +FILE_PATTERNS = *.h FAQ + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = NO + +# The EXCLUDE tag can be used to specify files and/or directories that should +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used select whether or not files or +# directories that are symbolic links (a Unix filesystem feature) are excluded +# from the input. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. Note that the wildcards are matched +# against the file with absolute path, so to exclude all test directories +# for example use the pattern */test/* + +EXCLUDE_PATTERNS = + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = examples + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = YES + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command , where +# is the value of the INPUT_FILTER tag, and is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. +# If FILTER_PATTERNS is specified, this tag will be +# ignored. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. +# Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. +# The filters are a list of the form: +# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further +# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER +# is applied to all files. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = NO + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = NO + +# If the REFERENCES_RELATION tag is set to YES +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = NO + +# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) +# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from +# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will +# link to the source code. +# Otherwise they will link to the documentation. + +REFERENCES_LINK_SOURCE = NO + +# If the USE_HTAGS tag is set to YES then the references to source code +# will point to the HTML generated by the htags(1) tool instead of doxygen +# built-in source browser. The htags tool is part of GNU's global source +# tagging system (see http://www.gnu.org/software/global/global.html). You +# will need version 4.8.6 or higher. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = YES + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = NO + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If the tag is left blank doxygen +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# stylesheet in the HTML output directory as well, or it will be erased! + +HTML_STYLESHEET = doxygen-custom.css + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting +# this to NO can help when comparing the output of multiple runs. + +HTML_TIMESTAMP = YES + +# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, +# files or namespaces will be aligned in HTML using tables. If set to +# NO a bullet list will be used. + +HTML_ALIGN_MEMBERS = YES + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. For this to work a browser that supports +# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox +# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). + +HTML_DYNAMIC_SECTIONS = NO + +# If the GENERATE_DOCSET tag is set to YES, additional index files +# will be generated that can be used as input for Apple's Xcode 3 +# integrated development environment, introduced with OSX 10.5 (Leopard). +# To create a documentation set, doxygen will generate a Makefile in the +# HTML output directory. Running make will produce the docset in that +# directory and running "make install" will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find +# it at startup. +# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html for more information. + +GENERATE_DOCSET = NO + +# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the +# feed. A documentation feed provides an umbrella under which multiple +# documentation sets from a single provider (such as a company or product suite) +# can be grouped. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that +# should uniquely identify the documentation set bundle. This should be a +# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen +# will append .docset to the name. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING +# is used to encode HtmlHelp index (hhk), content (hhc) and project file +# content. + +CHM_INDEX_ENCODING = + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and QHP_VIRTUAL_FOLDER +# are set, an additional index file will be generated that can be used as input for +# Qt's qhelpgenerator to generate a Qt Compressed Help (.qch) of the generated +# HTML documentation. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can +# be used to specify the file name of the resulting .qch file. +# The path specified is relative to the HTML output folder. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#namespace + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#virtual-folders + +QHP_VIRTUAL_FOLDER = doc + +# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to add. +# For more information please see +# http://doc.trolltech.com/qthelpproject.html#custom-filters + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the custom filter to add.For more information please see +# Qt Help Project / Custom Filters. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this project's +# filter section matches. +# Qt Help Project / Filter Attributes. + +QHP_SECT_FILTER_ATTRS = + +# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can +# be used to specify the location of Qt's qhelpgenerator. +# If non-empty doxygen will try to run qhelpgenerator on the generated +# .qhp file. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files +# will be generated, which together with the HTML files, form an Eclipse help +# plugin. To install this plugin and make it available under the help contents +# menu in Eclipse, the contents of the directory containing the HTML and XML +# files needs to be copied into the plugins directory of eclipse. The name of +# the directory within the plugins directory should be the same as +# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before the help appears. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have +# this name. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index at +# top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. + +DISABLE_INDEX = NO + +# This tag can be used to set the number of enum values (range [1..20]) +# that doxygen will group on one line in the generated HTML documentation. + +ENUM_VALUES_PER_LINE = 4 + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. +# If the tag value is set to YES, a side panel will be generated +# containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). +# Windows users are probably better off using the HTML help feature. + +GENERATE_TREEVIEW = NO + +# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, +# and Class Hierarchy pages using a tree view instead of an ordered list. + +USE_INLINE_TREES = NO + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +# Use this tag to change the font size of Latex formulas included +# as images in the HTML documentation. The default is 10. Note that +# when you change the font size after a successful doxygen run you need +# to manually remove any form_*.png images from the HTML output directory +# to force them to be regenerated. + +FORMULA_FONTSIZE = 10 + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box for the HTML output. The underlying search engine uses javascript +# and DHTML and should work on any modern browser. Note that when using HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) there is already a search function so this one should +# typically be disabled. For large projects the javascript based search engine +# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. + +SEARCHENGINE = YES + +# When the SERVER_BASED_SEARCH tag is enabled the search engine will be implemented using a PHP enabled web server instead of at the web client using Javascript. Doxygen will generate the search PHP script and index +# file to put on the web server. The advantage of the server based approach is that it scales better to large projects and allows full text search. The disadvances is that it is more difficult to setup +# and does not have live searching capabilities. + +SERVER_BASED_SEARCH = NO + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = NO + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. +# Note that when enabling USE_PDFLATEX this option is only used for +# generating bitmaps for formulas in the HTML output, but not in the +# Makefile that is written to the output directory. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, a4wide, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = a4wide + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = YES + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = YES + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = NO + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + +# If LATEX_SOURCE_CODE is set to YES then doxygen will include source code with syntax highlighting in the LaTeX output. Note that which sources are shown also depends on other settings such as SOURCE_BROWSER. + +LATEX_SOURCE_CODE = NO + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = NO + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = NO + +# Load stylesheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = NO + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = YES + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + +# The XML_SCHEMA tag can be used to specify an XML schema, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_SCHEMA = + +# The XML_DTD tag can be used to specify an XML DTD, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_DTD = + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = NO + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. +# This is useful +# if you want to understand what is going on. +# On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = NO + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_DEFINED tags. + +EXPAND_ONLY_PREDEF = NO + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# in the INCLUDE_PATH (see below) will be search if a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. To prevent a macro definition from being +# undefined via #undef or recursively expanded use the := operator +# instead of the = operator. + +PREDEFINED = + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition. + +EXPAND_AS_DEFINED = + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all function-like macros that are alone +# on a line, have an all uppercase name, and do not end with a semicolon. Such +# function macros are typically used for boiler-plate code, and will confuse +# the parser if not removed. + +SKIP_FUNCTION_MACROS = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base +# or super classes. Setting the tag to NO turns the diagrams off. Note that +# this option is superseded by the HAVE_DOT option below. This is only a +# fallback. It is recommended to install and use dot, since it yields more +# powerful graphs. + +CLASS_DIAGRAMS = YES + +# You can define message sequence charts within doxygen comments using the \msc +# command. Doxygen will then run the mscgen tool (see +# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the +# documentation. The MSCGEN_PATH tag allows you to specify the directory where +# the mscgen tool resides. If left empty the tool is assumed to be found in the +# default search path. + +MSCGEN_PATH = + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = YES + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = NO + +# By default doxygen will write a font called FreeSans.ttf to the output +# directory and reference it in all dot files that doxygen generates. This +# font does not include all possible unicode characters however, so when you need +# these (or just want a differently looking font) you can specify the font name +# using DOT_FONTNAME. You need need to make sure dot is able to find the font, +# which can be done by putting it in a standard location or by setting the +# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory +# containing the font. + +DOT_FONTNAME = FreeSans + +# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. +# The default size is 10pt. + +DOT_FONTSIZE = 10 + +# By default doxygen will tell dot to use the output directory to look for the +# FreeSans.ttf font (which doxygen will put there itself). If you specify a +# different font using DOT_FONTNAME you can set the path where dot +# can find it using this tag. + +DOT_FONTPATH = + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# the CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for groups, showing the direct groups dependencies + +GROUP_GRAPHS = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = NO + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = YES + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = YES + +# If the CALL_GRAPH and HAVE_DOT options are set to YES then +# doxygen will generate a call dependency graph for every global function +# or class method. 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This is disabled by default, because dot on Windows does not +# seem to support this out of the box. Warning: Depending on the platform used, +# enabling this option may lead to badly anti-aliased labels on the edges of +# a graph (i.e. they become hard to read). + +DOT_TRANSPARENT = NO + +# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output +# files in one run (i.e. multiple -o and -T options on the command line). This +# makes dot run faster, but since only newer versions of dot (>1.8.10) +# support this, this feature is disabled by default. + +DOT_MULTI_TARGETS = YES + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES diff --git a/hardware/digistump/avr/libraries/RF24/FAQ b/hardware/digistump/avr/libraries/RF24/FAQ new file mode 100644 index 0000000..eccd03a --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/FAQ @@ -0,0 +1,53 @@ +/** + * @page FAQ Frequently Asked Questions + * + * @ref starting + * + * @ref hardware + * + * @ref range + * + * @ref issues + * + * @ref ram + * + * @ref tests + * + * @section starting Where do I start? + * + * See my blog post: + * Getting Started with nRF24L01+ on Arduino + * + * @section hardware Where can I buy some hardware? + * + * @li iTeadStudio sells the basic 2.4G Wireless nRF24L01+ Module for $4. Such a deal! + * @li MDfly.com sells the same unit, 2.4Ghz Wireless nRF24L01+ Transceiver Module for $6.95, but it ships from the US so it gets there a lot faster. Great place to get a few units and get started quickly. + * @li MDfly.com also has the nRF24L01 2.4GHz Transceiver Module w/ Power Amplifier for $13.95, which increases range dramatically and uses a chip antenna + * @li MDfly.com also has the 2.4GHz Transceiver Module w/ Power Amplifier with an external antenna for $19.95 + * + * @section range What is the range of these units? + * + * Here are some results from measurements I have taken, using the basic $4 iTeadStudio units. + * I recommend that everyone take their own measurements in their particular circumstances. + * + * @li non-plus unit, 2MBps (worst case), 41+ ft line of sight indoors, immediate dropoff with any deviation from LOS. (41 ft is as far as I can go in my house without turning a corner) + * @li Plus unit, 250kbps (best case), 46 ft around two corners indoors, 49 ft around one corner. More importantly, at 250k, packet loss is almost negligible through almost all of that range. + * @li Both units at 1MBps, plus unit gets about 10% range improvement over non-plus in almost all situations. + * + * @section issues What should I do if I find a problem? + * + * Please open an issue on github if you find any problems using it with any version of Arduino or Maple. + * + * @section ram What is the RAM footprint of this library? + * + * 16 bytes. A single radio object consumes 16 bytes of RAM, and the library + * does not use any other RAM statically. + * + * @section tests Why are the examples in the 'tests' directory failing? + * + * The sketches in the 'tests' directory are not for general use. + * Please use the examples in the 'examples' directory instead. + * + * The 'tests' directory is only for people making changes to the library + * to ensure that their changes do not break anything. + */ diff --git a/hardware/digistump/avr/libraries/RF24/README.md b/hardware/digistump/avr/libraries/RF24/README.md new file mode 100644 index 0000000..c0e71c0 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/README.md @@ -0,0 +1,20 @@ +# Arduino driver for nRF24L01 2.4GHz Wireless Transceiver + +Design Goals: This library is designed to be... + +* Maximally compliant with the intended operation of the chip +* Easy for beginners to use +* Consumed with a public interface that's similiar to other Arduino standard libraries +* Built against the standard SPI library. + +Please refer to: + +* [Documentation Main Page](http://maniacbug.github.com/RF24) +* [RF24 Class Documentation](http://maniacbug.github.com/RF24/classRF24.html) +* [Source Code](https://github.com/maniacbug/RF24) +* [Downloads](https://github.com/maniacbug/RF24/archives/master) +* [Chip Datasheet](http://www.nordicsemi.com/files/Product/data_sheet/nRF24L01_Product_Specification_v2_0.pdf) + +This chip uses the SPI bus, plus two chip control pins. Remember that pin 10 must still remain an output, or +the SPI hardware will go into 'slave' mode. + diff --git a/hardware/digistump/avr/libraries/RF24/RF24.cpp b/hardware/digistump/avr/libraries/RF24/RF24.cpp new file mode 100644 index 0000000..9471583 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/RF24.cpp @@ -0,0 +1,985 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +#include "nRF24L01.h" +#include "RF24_config.h" +#include "RF24.h" + +/****************************************************************************/ + +void RF24::csn(int mode) +{ + // Minimum ideal SPI bus speed is 2x data rate + // If we assume 2Mbs data rate and 16Mhz clock, a + // divider of 4 is the minimum we want. + // CLK:BUS 8Mhz:2Mhz, 16Mhz:4Mhz, or 20Mhz:5Mhz +#ifdef ARDUINO + SPI.setBitOrder(MSBFIRST); + SPI.setDataMode(SPI_MODE0); + SPI.setClockDivider(SPI_CLOCK_DIV4); +#endif + digitalWrite(csn_pin,mode); +} + +/****************************************************************************/ + +void RF24::ce(int level) +{ + digitalWrite(ce_pin,level); +} + +/****************************************************************************/ + +uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len) +{ + uint8_t status; + + csn(LOW); + status = SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) ); + while ( len-- ) + *buf++ = SPI.transfer(0xff); + + csn(HIGH); + + return status; +} + +/****************************************************************************/ + +uint8_t RF24::read_register(uint8_t reg) +{ + csn(LOW); + SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) ); + uint8_t result = SPI.transfer(0xff); + + csn(HIGH); + return result; +} + +/****************************************************************************/ + +uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len) +{ + uint8_t status; + + csn(LOW); + status = SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) ); + while ( len-- ) + SPI.transfer(*buf++); + + csn(HIGH); + + return status; +} + +/****************************************************************************/ + +uint8_t RF24::write_register(uint8_t reg, uint8_t value) +{ + uint8_t status; + + IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"),reg,value)); + + csn(LOW); + status = SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) ); + SPI.transfer(value); + csn(HIGH); + + return status; +} + +/****************************************************************************/ + +uint8_t RF24::write_payload(const void* buf, uint8_t len) +{ + uint8_t status; + + const uint8_t* current = reinterpret_cast(buf); + + uint8_t data_len = min(len,payload_size); + uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len; + + //printf("[Writing %u bytes %u blanks]",data_len,blank_len); + + csn(LOW); + status = SPI.transfer( W_TX_PAYLOAD ); + while ( data_len-- ) + SPI.transfer(*current++); + while ( blank_len-- ) + SPI.transfer(0); + csn(HIGH); + + return status; +} + +/****************************************************************************/ + +uint8_t RF24::read_payload(void* buf, uint8_t len) +{ + uint8_t status; + uint8_t* current = reinterpret_cast(buf); + + uint8_t data_len = min(len,payload_size); + uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len; + + //printf("[Reading %u bytes %u blanks]",data_len,blank_len); + + csn(LOW); + status = SPI.transfer( R_RX_PAYLOAD ); + while ( data_len-- ) + *current++ = SPI.transfer(0xff); + while ( blank_len-- ) + SPI.transfer(0xff); + csn(HIGH); + + return status; +} + +/****************************************************************************/ + +uint8_t RF24::flush_rx(void) +{ + uint8_t status; + + csn(LOW); + status = SPI.transfer( FLUSH_RX ); + csn(HIGH); + + return status; +} + +/****************************************************************************/ + +uint8_t RF24::flush_tx(void) +{ + uint8_t status; + + csn(LOW); + status = SPI.transfer( FLUSH_TX ); + csn(HIGH); + + return status; +} + +/****************************************************************************/ + +uint8_t RF24::get_status(void) +{ + uint8_t status; + + csn(LOW); + status = SPI.transfer( NOP ); + csn(HIGH); + + return status; +} + +/****************************************************************************/ + +void RF24::print_status(uint8_t status) +{ + printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"), + status, + (status & _BV(RX_DR))?1:0, + (status & _BV(TX_DS))?1:0, + (status & _BV(MAX_RT))?1:0, + ((status >> RX_P_NO) & B111), + (status & _BV(TX_FULL))?1:0 + ); +} + +/****************************************************************************/ + +void RF24::print_observe_tx(uint8_t value) +{ + printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"), + value, + (value >> PLOS_CNT) & B1111, + (value >> ARC_CNT) & B1111 + ); +} + +/****************************************************************************/ + +void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty) +{ + char extra_tab = strlen_P(name) < 8 ? '\t' : 0; + printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab); + while (qty--) + printf_P(PSTR(" 0x%02x"),read_register(reg++)); + printf_P(PSTR("\r\n")); +} + +/****************************************************************************/ + +void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty) +{ + char extra_tab = strlen_P(name) < 8 ? '\t' : 0; + printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab); + + while (qty--) + { + uint8_t buffer[5]; + read_register(reg++,buffer,sizeof buffer); + + printf_P(PSTR(" 0x")); + uint8_t* bufptr = buffer + sizeof buffer; + while( --bufptr >= buffer ) + printf_P(PSTR("%02x"),*bufptr); + } + + printf_P(PSTR("\r\n")); +} + +/****************************************************************************/ + +RF24::RF24(uint8_t _cepin, uint8_t _cspin): + ce_pin(_cepin), csn_pin(_cspin), wide_band(true), p_variant(false), + payload_size(32), ack_payload_available(false), dynamic_payloads_enabled(false), + pipe0_reading_address(0) +{ +} + +/****************************************************************************/ + +void RF24::setChannel(uint8_t channel) +{ + // TODO: This method could take advantage of the 'wide_band' calculation + // done in setChannel() to require certain channel spacing. + + const uint8_t max_channel = 127; + write_register(RF_CH,min(channel,max_channel)); +} + +/****************************************************************************/ + +void RF24::setPayloadSize(uint8_t size) +{ + const uint8_t max_payload_size = 32; + payload_size = min(size,max_payload_size); +} + +/****************************************************************************/ + +uint8_t RF24::getPayloadSize(void) +{ + return payload_size; +} + +/****************************************************************************/ + +static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS"; +static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS"; +static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS"; +static const char * const rf24_datarate_e_str_P[] PROGMEM = { + rf24_datarate_e_str_0, + rf24_datarate_e_str_1, + rf24_datarate_e_str_2, +}; +static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01"; +static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+"; +static const char * const rf24_model_e_str_P[] PROGMEM = { + rf24_model_e_str_0, + rf24_model_e_str_1, +}; +static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled"; +static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits"; +static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ; +static const char * const rf24_crclength_e_str_P[] PROGMEM = { + rf24_crclength_e_str_0, + rf24_crclength_e_str_1, + rf24_crclength_e_str_2, +}; +static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN"; +static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW"; +static const char rf24_pa_dbm_e_str_2[] PROGMEM = "LA_MED"; +static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_HIGH"; +static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = { + rf24_pa_dbm_e_str_0, + rf24_pa_dbm_e_str_1, + rf24_pa_dbm_e_str_2, + rf24_pa_dbm_e_str_3, +}; + +void RF24::printDetails(void) +{ + print_status(get_status()); + + print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2); + print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4); + print_address_register(PSTR("TX_ADDR"),TX_ADDR); + + print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6); + print_byte_register(PSTR("EN_AA"),EN_AA); + print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR); + print_byte_register(PSTR("RF_CH"),RF_CH); + print_byte_register(PSTR("RF_SETUP"),RF_SETUP); + print_byte_register(PSTR("CONFIG"),CONFIG); + print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2); + + printf_P(PSTR("Data Rate\t = %S\r\n"),pgm_read_word(&rf24_datarate_e_str_P[getDataRate()])); + printf_P(PSTR("Model\t\t = %S\r\n"),pgm_read_word(&rf24_model_e_str_P[isPVariant()])); + printf_P(PSTR("CRC Length\t = %S\r\n"),pgm_read_word(&rf24_crclength_e_str_P[getCRCLength()])); + printf_P(PSTR("PA Power\t = %S\r\n"),pgm_read_word(&rf24_pa_dbm_e_str_P[getPALevel()])); +} + +/****************************************************************************/ + +void RF24::begin(void) +{ + // Initialize pins + pinMode(ce_pin,OUTPUT); + pinMode(csn_pin,OUTPUT); + + // Initialize SPI bus + SPI.begin(); + + ce(LOW); + csn(HIGH); + + // Must allow the radio time to settle else configuration bits will not necessarily stick. + // This is actually only required following power up but some settling time also appears to + // be required after resets too. For full coverage, we'll always assume the worst. + // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped. + // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure. + // WARNING: Delay is based on P-variant whereby non-P *may* require different timing. + delay( 5 ) ; + + // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier + // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet + // sizes must never be used. See documentation for a more complete explanation. + write_register(SETUP_RETR,(B0100 << ARD) | (B1111 << ARC)); + + // Restore our default PA level + setPALevel( RF24_PA_MAX ) ; + + // Determine if this is a p or non-p RF24 module and then + // reset our data rate back to default value. This works + // because a non-P variant won't allow the data rate to + // be set to 250Kbps. + if( setDataRate( RF24_250KBPS ) ) + { + p_variant = true ; + } + + // Then set the data rate to the slowest (and most reliable) speed supported by all + // hardware. + setDataRate( RF24_1MBPS ) ; + + // Initialize CRC and request 2-byte (16bit) CRC + setCRCLength( RF24_CRC_16 ) ; + + // Disable dynamic payloads, to match dynamic_payloads_enabled setting + write_register(DYNPD,0); + + // Reset current status + // Notice reset and flush is the last thing we do + write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); + + // Set up default configuration. Callers can always change it later. + // This channel should be universally safe and not bleed over into adjacent + // spectrum. + setChannel(76); + + // Flush buffers + flush_rx(); + flush_tx(); +} + +/****************************************************************************/ + +void RF24::startListening(void) +{ + write_register(CONFIG, read_register(CONFIG) | _BV(PWR_UP) | _BV(PRIM_RX)); + write_register(STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); + + // Restore the pipe0 adddress, if exists + if (pipe0_reading_address) + write_register(RX_ADDR_P0, reinterpret_cast(&pipe0_reading_address), 5); + + // Flush buffers + flush_rx(); + flush_tx(); + + // Go! + ce(HIGH); + + // wait for the radio to come up (130us actually only needed) + delayMicroseconds(130); +} + +/****************************************************************************/ + +void RF24::stopListening(void) +{ + ce(LOW); + flush_tx(); + flush_rx(); +} + +/****************************************************************************/ + +void RF24::powerDown(void) +{ + write_register(CONFIG,read_register(CONFIG) & ~_BV(PWR_UP)); +} + +/****************************************************************************/ + +void RF24::powerUp(void) +{ + write_register(CONFIG,read_register(CONFIG) | _BV(PWR_UP)); +} + +/******************************************************************/ + +bool RF24::write( const void* buf, uint8_t len ) +{ + bool result = false; + + // Begin the write + startWrite(buf,len); + + // ------------ + // At this point we could return from a non-blocking write, and then call + // the rest after an interrupt + + // Instead, we are going to block here until we get TX_DS (transmission completed and ack'd) + // or MAX_RT (maximum retries, transmission failed). Also, we'll timeout in case the radio + // is flaky and we get neither. + + // IN the end, the send should be blocking. It comes back in 60ms worst case, or much faster + // if I tighted up the retry logic. (Default settings will be 1500us. + // Monitor the send + uint8_t observe_tx; + uint8_t status; + uint32_t sent_at = millis(); + const uint32_t timeout = 500; //ms to wait for timeout + do + { + status = read_register(OBSERVE_TX,&observe_tx,1); + IF_SERIAL_DEBUG(Serial.print(observe_tx,HEX)); + } + while( ! ( status & ( _BV(TX_DS) | _BV(MAX_RT) ) ) && ( millis() - sent_at < timeout ) ); + + // The part above is what you could recreate with your own interrupt handler, + // and then call this when you got an interrupt + // ------------ + + // Call this when you get an interrupt + // The status tells us three things + // * The send was successful (TX_DS) + // * The send failed, too many retries (MAX_RT) + // * There is an ack packet waiting (RX_DR) + bool tx_ok, tx_fail; + whatHappened(tx_ok,tx_fail,ack_payload_available); + + //printf("%u%u%u\r\n",tx_ok,tx_fail,ack_payload_available); + + result = tx_ok; + IF_SERIAL_DEBUG(Serial.print(result?"...OK.":"...Failed")); + + // Handle the ack packet + if ( ack_payload_available ) + { + ack_payload_length = getDynamicPayloadSize(); + IF_SERIAL_DEBUG(Serial.print("[AckPacket]/")); + IF_SERIAL_DEBUG(Serial.println(ack_payload_length,DEC)); + } + + // Yay, we are done. + + // Power down + powerDown(); + + // Flush buffers (Is this a relic of past experimentation, and not needed anymore??) + flush_tx(); + + return result; +} +/****************************************************************************/ + +void RF24::startWrite( const void* buf, uint8_t len ) +{ + // Transmitter power-up + write_register(CONFIG, ( read_register(CONFIG) | _BV(PWR_UP) ) & ~_BV(PRIM_RX) ); + delayMicroseconds(150); + + // Send the payload + write_payload( buf, len ); + + // Allons! + ce(HIGH); + delayMicroseconds(15); + ce(LOW); +} + +/****************************************************************************/ + +uint8_t RF24::getDynamicPayloadSize(void) +{ + uint8_t result = 0; + + csn(LOW); + SPI.transfer( R_RX_PL_WID ); + result = SPI.transfer(0xff); + csn(HIGH); + + return result; +} + +/****************************************************************************/ + +bool RF24::available(void) +{ + return available(NULL); +} + +/****************************************************************************/ + +bool RF24::available(uint8_t* pipe_num) +{ + uint8_t status = get_status(); + + // Too noisy, enable if you really want lots o data!! + //IF_SERIAL_DEBUG(print_status(status)); + + bool result = ( status & _BV(RX_DR) ); + + if (result) + { + // If the caller wants the pipe number, include that + if ( pipe_num ) + *pipe_num = ( status >> RX_P_NO ) & B111; + + // Clear the status bit + + // ??? Should this REALLY be cleared now? Or wait until we + // actually READ the payload? + + write_register(STATUS,_BV(RX_DR) ); + + // Handle ack payload receipt + if ( status & _BV(TX_DS) ) + { + write_register(STATUS,_BV(TX_DS)); + } + } + + return result; +} + +/****************************************************************************/ + +bool RF24::read( void* buf, uint8_t len ) +{ + // Fetch the payload + read_payload( buf, len ); + + // was this the last of the data available? + return read_register(FIFO_STATUS) & _BV(RX_EMPTY); +} + +/****************************************************************************/ + +void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready) +{ + // Read the status & reset the status in one easy call + // Or is that such a good idea? + uint8_t status = write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); + + // Report to the user what happened + tx_ok = status & _BV(TX_DS); + tx_fail = status & _BV(MAX_RT); + rx_ready = status & _BV(RX_DR); +} + +/****************************************************************************/ + +void RF24::openWritingPipe(uint64_t value) +{ + // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+) + // expects it LSB first too, so we're good. + + write_register(RX_ADDR_P0, reinterpret_cast(&value), 5); + write_register(TX_ADDR, reinterpret_cast(&value), 5); + + const uint8_t max_payload_size = 32; + write_register(RX_PW_P0,min(payload_size,max_payload_size)); +} + +/****************************************************************************/ + +static const uint8_t child_pipe[] PROGMEM = +{ + RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5 +}; +static const uint8_t child_payload_size[] PROGMEM = +{ + RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5 +}; +static const uint8_t child_pipe_enable[] PROGMEM = +{ + ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5 +}; + +void RF24::openReadingPipe(uint8_t child, uint64_t address) +{ + // If this is pipe 0, cache the address. This is needed because + // openWritingPipe() will overwrite the pipe 0 address, so + // startListening() will have to restore it. + if (child == 0) + pipe0_reading_address = address; + + if (child <= 6) + { + // For pipes 2-5, only write the LSB + if ( child < 2 ) + write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast(&address), 5); + else + write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast(&address), 1); + + write_register(pgm_read_byte(&child_payload_size[child]),payload_size); + + // Note it would be more efficient to set all of the bits for all open + // pipes at once. However, I thought it would make the calling code + // more simple to do it this way. + write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child]))); + } +} + +/****************************************************************************/ + +void RF24::toggle_features(void) +{ + csn(LOW); + SPI.transfer( ACTIVATE ); + SPI.transfer( 0x73 ); + csn(HIGH); +} + +/****************************************************************************/ + +void RF24::enableDynamicPayloads(void) +{ + // Enable dynamic payload throughout the system + write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) ); + + // If it didn't work, the features are not enabled + if ( ! read_register(FEATURE) ) + { + // So enable them and try again + toggle_features(); + write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) ); + } + + IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE))); + + // Enable dynamic payload on all pipes + // + // Not sure the use case of only having dynamic payload on certain + // pipes, so the library does not support it. + write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0)); + + dynamic_payloads_enabled = true; +} + +/****************************************************************************/ + +void RF24::enableAckPayload(void) +{ + // + // enable ack payload and dynamic payload features + // + + write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) ); + + // If it didn't work, the features are not enabled + if ( ! read_register(FEATURE) ) + { + // So enable them and try again + toggle_features(); + write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) ); + } + + IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE))); + + // + // Enable dynamic payload on pipes 0 & 1 + // + + write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0)); +} + +/****************************************************************************/ + +void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len) +{ + const uint8_t* current = reinterpret_cast(buf); + + csn(LOW); + SPI.transfer( W_ACK_PAYLOAD | ( pipe & B111 ) ); + const uint8_t max_payload_size = 32; + uint8_t data_len = min(len,max_payload_size); + while ( data_len-- ) + SPI.transfer(*current++); + + csn(HIGH); +} + +/****************************************************************************/ + +bool RF24::isAckPayloadAvailable(void) +{ + bool result = ack_payload_available; + ack_payload_available = false; + return result; +} + +/****************************************************************************/ + +bool RF24::isPVariant(void) +{ + return p_variant ; +} + +/****************************************************************************/ + +void RF24::setAutoAck(bool enable) +{ + if ( enable ) + write_register(EN_AA, B111111); + else + write_register(EN_AA, 0); +} + +/****************************************************************************/ + +void RF24::setAutoAck( uint8_t pipe, bool enable ) +{ + if ( pipe <= 6 ) + { + uint8_t en_aa = read_register( EN_AA ) ; + if( enable ) + { + en_aa |= _BV(pipe) ; + } + else + { + en_aa &= ~_BV(pipe) ; + } + write_register( EN_AA, en_aa ) ; + } +} + +/****************************************************************************/ + +bool RF24::testCarrier(void) +{ + return ( read_register(CD) & 1 ); +} + +/****************************************************************************/ + +bool RF24::testRPD(void) +{ + return ( read_register(RPD) & 1 ) ; +} + +/****************************************************************************/ + +void RF24::setPALevel(rf24_pa_dbm_e level) +{ + uint8_t setup = read_register(RF_SETUP) ; + setup &= ~(_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ; + + // switch uses RAM (evil!) + if ( level == RF24_PA_MAX ) + { + setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ; + } + else if ( level == RF24_PA_HIGH ) + { + setup |= _BV(RF_PWR_HIGH) ; + } + else if ( level == RF24_PA_LOW ) + { + setup |= _BV(RF_PWR_LOW); + } + else if ( level == RF24_PA_MIN ) + { + // nothing + } + else if ( level == RF24_PA_ERROR ) + { + // On error, go to maximum PA + setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ; + } + + write_register( RF_SETUP, setup ) ; +} + +/****************************************************************************/ + +rf24_pa_dbm_e RF24::getPALevel(void) +{ + rf24_pa_dbm_e result = RF24_PA_ERROR ; + uint8_t power = read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ; + + // switch uses RAM (evil!) + if ( power == (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ) + { + result = RF24_PA_MAX ; + } + else if ( power == _BV(RF_PWR_HIGH) ) + { + result = RF24_PA_HIGH ; + } + else if ( power == _BV(RF_PWR_LOW) ) + { + result = RF24_PA_LOW ; + } + else + { + result = RF24_PA_MIN ; + } + + return result ; +} + +/****************************************************************************/ + +bool RF24::setDataRate(rf24_datarate_e speed) +{ + bool result = false; + uint8_t setup = read_register(RF_SETUP) ; + + // HIGH and LOW '00' is 1Mbs - our default + wide_band = false ; + setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ; + if( speed == RF24_250KBPS ) + { + // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0 + // Making it '10'. + wide_band = false ; + setup |= _BV( RF_DR_LOW ) ; + } + else + { + // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1 + // Making it '01' + if ( speed == RF24_2MBPS ) + { + wide_band = true ; + setup |= _BV(RF_DR_HIGH); + } + else + { + // 1Mbs + wide_band = false ; + } + } + write_register(RF_SETUP,setup); + + // Verify our result + if ( read_register(RF_SETUP) == setup ) + { + result = true; + } + else + { + wide_band = false; + } + + return result; +} + +/****************************************************************************/ + +rf24_datarate_e RF24::getDataRate( void ) +{ + rf24_datarate_e result ; + uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)); + + // switch uses RAM (evil!) + // Order matters in our case below + if ( dr == _BV(RF_DR_LOW) ) + { + // '10' = 250KBPS + result = RF24_250KBPS ; + } + else if ( dr == _BV(RF_DR_HIGH) ) + { + // '01' = 2MBPS + result = RF24_2MBPS ; + } + else + { + // '00' = 1MBPS + result = RF24_1MBPS ; + } + return result ; +} + +/****************************************************************************/ + +void RF24::setCRCLength(rf24_crclength_e length) +{ + uint8_t config = read_register(CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ; + + // switch uses RAM (evil!) + if ( length == RF24_CRC_DISABLED ) + { + // Do nothing, we turned it off above. + } + else if ( length == RF24_CRC_8 ) + { + config |= _BV(EN_CRC); + } + else + { + config |= _BV(EN_CRC); + config |= _BV( CRCO ); + } + write_register( CONFIG, config ) ; +} + +/****************************************************************************/ + +rf24_crclength_e RF24::getCRCLength(void) +{ + rf24_crclength_e result = RF24_CRC_DISABLED; + uint8_t config = read_register(CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ; + + if ( config & _BV(EN_CRC ) ) + { + if ( config & _BV(CRCO) ) + result = RF24_CRC_16; + else + result = RF24_CRC_8; + } + + return result; +} + +/****************************************************************************/ + +void RF24::disableCRC( void ) +{ + uint8_t disable = read_register(CONFIG) & ~_BV(EN_CRC) ; + write_register( CONFIG, disable ) ; +} + +/****************************************************************************/ +void RF24::setRetries(uint8_t delay, uint8_t count) +{ + write_register(SETUP_RETR,(delay&0xf)< + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file RF24.h + * + * Class declaration for RF24 and helper enums + */ + +#ifndef __RF24_H__ +#define __RF24_H__ + +#include + +/** + * Power Amplifier level. + * + * For use with setPALevel() + */ +typedef enum { RF24_PA_MIN = 0,RF24_PA_LOW, RF24_PA_HIGH, RF24_PA_MAX, RF24_PA_ERROR } rf24_pa_dbm_e ; + +/** + * Data rate. How fast data moves through the air. + * + * For use with setDataRate() + */ +typedef enum { RF24_1MBPS = 0, RF24_2MBPS, RF24_250KBPS } rf24_datarate_e; + +/** + * CRC Length. How big (if any) of a CRC is included. + * + * For use with setCRCLength() + */ +typedef enum { RF24_CRC_DISABLED = 0, RF24_CRC_8, RF24_CRC_16 } rf24_crclength_e; + +/** + * Driver for nRF24L01(+) 2.4GHz Wireless Transceiver + */ + +class RF24 +{ +private: + uint8_t ce_pin; /**< "Chip Enable" pin, activates the RX or TX role */ + uint8_t csn_pin; /**< SPI Chip select */ + bool wide_band; /* 2Mbs data rate in use? */ + bool p_variant; /* False for RF24L01 and true for RF24L01P */ + uint8_t payload_size; /**< Fixed size of payloads */ + bool ack_payload_available; /**< Whether there is an ack payload waiting */ + bool dynamic_payloads_enabled; /**< Whether dynamic payloads are enabled. */ + uint8_t ack_payload_length; /**< Dynamic size of pending ack payload. */ + uint64_t pipe0_reading_address; /**< Last address set on pipe 0 for reading. */ + +protected: + /** + * @name Low-level internal interface. + * + * Protected methods that address the chip directly. Regular users cannot + * ever call these. They are documented for completeness and for developers who + * may want to extend this class. + */ + /**@{*/ + + /** + * Set chip select pin + * + * Running SPI bus at PI_CLOCK_DIV2 so we don't waste time transferring data + * and best of all, we make use of the radio's FIFO buffers. A lower speed + * means we're less likely to effectively leverage our FIFOs and pay a higher + * AVR runtime cost as toll. + * + * @param mode HIGH to take this unit off the SPI bus, LOW to put it on + */ + void csn(int mode); + + /** + * Set chip enable + * + * @param level HIGH to actively begin transmission or LOW to put in standby. Please see data sheet + * for a much more detailed description of this pin. + */ + void ce(int level); + + /** + * Read a chunk of data in from a register + * + * @param reg Which register. Use constants from nRF24L01.h + * @param buf Where to put the data + * @param len How many bytes of data to transfer + * @return Current value of status register + */ + uint8_t read_register(uint8_t reg, uint8_t* buf, uint8_t len); + + /** + * Read single byte from a register + * + * @param reg Which register. Use constants from nRF24L01.h + * @return Current value of register @p reg + */ + uint8_t read_register(uint8_t reg); + + /** + * Write a chunk of data to a register + * + * @param reg Which register. Use constants from nRF24L01.h + * @param buf Where to get the data + * @param len How many bytes of data to transfer + * @return Current value of status register + */ + uint8_t write_register(uint8_t reg, const uint8_t* buf, uint8_t len); + + /** + * Write a single byte to a register + * + * @param reg Which register. Use constants from nRF24L01.h + * @param value The new value to write + * @return Current value of status register + */ + uint8_t write_register(uint8_t reg, uint8_t value); + + /** + * Write the transmit payload + * + * The size of data written is the fixed payload size, see getPayloadSize() + * + * @param buf Where to get the data + * @param len Number of bytes to be sent + * @return Current value of status register + */ + uint8_t write_payload(const void* buf, uint8_t len); + + /** + * Read the receive payload + * + * The size of data read is the fixed payload size, see getPayloadSize() + * + * @param buf Where to put the data + * @param len Maximum number of bytes to read + * @return Current value of status register + */ + uint8_t read_payload(void* buf, uint8_t len); + + /** + * Empty the receive buffer + * + * @return Current value of status register + */ + uint8_t flush_rx(void); + + /** + * Empty the transmit buffer + * + * @return Current value of status register + */ + uint8_t flush_tx(void); + + /** + * Retrieve the current status of the chip + * + * @return Current value of status register + */ + uint8_t get_status(void); + + /** + * Decode and print the given status to stdout + * + * @param status Status value to print + * + * @warning Does nothing if stdout is not defined. See fdevopen in stdio.h + */ + void print_status(uint8_t status); + + /** + * Decode and print the given 'observe_tx' value to stdout + * + * @param value The observe_tx value to print + * + * @warning Does nothing if stdout is not defined. See fdevopen in stdio.h + */ + void print_observe_tx(uint8_t value); + + /** + * Print the name and value of an 8-bit register to stdout + * + * Optionally it can print some quantity of successive + * registers on the same line. This is useful for printing a group + * of related registers on one line. + * + * @param name Name of the register + * @param reg Which register. Use constants from nRF24L01.h + * @param qty How many successive registers to print + */ + void print_byte_register(const char* name, uint8_t reg, uint8_t qty = 1); + + /** + * Print the name and value of a 40-bit address register to stdout + * + * Optionally it can print some quantity of successive + * registers on the same line. This is useful for printing a group + * of related registers on one line. + * + * @param name Name of the register + * @param reg Which register. Use constants from nRF24L01.h + * @param qty How many successive registers to print + */ + void print_address_register(const char* name, uint8_t reg, uint8_t qty = 1); + + /** + * Turn on or off the special features of the chip + * + * The chip has certain 'features' which are only available when the 'features' + * are enabled. See the datasheet for details. + */ + void toggle_features(void); + /**@}*/ + +public: + /** + * @name Primary public interface + * + * These are the main methods you need to operate the chip + */ + /**@{*/ + + /** + * Constructor + * + * Creates a new instance of this driver. Before using, you create an instance + * and send in the unique pins that this chip is connected to. + * + * @param _cepin The pin attached to Chip Enable on the RF module + * @param _cspin The pin attached to Chip Select + */ + RF24(uint8_t _cepin, uint8_t _cspin); + + /** + * Begin operation of the chip + * + * Call this in setup(), before calling any other methods. + */ + void begin(void); + + /** + * Start listening on the pipes opened for reading. + * + * Be sure to call openReadingPipe() first. Do not call write() while + * in this mode, without first calling stopListening(). Call + * isAvailable() to check for incoming traffic, and read() to get it. + */ + void startListening(void); + + /** + * Stop listening for incoming messages + * + * Do this before calling write(). + */ + void stopListening(void); + + /** + * Write to the open writing pipe + * + * Be sure to call openWritingPipe() first to set the destination + * of where to write to. + * + * This blocks until the message is successfully acknowledged by + * the receiver or the timeout/retransmit maxima are reached. In + * the current configuration, the max delay here is 60ms. + * + * The maximum size of data written is the fixed payload size, see + * getPayloadSize(). However, you can write less, and the remainder + * will just be filled with zeroes. + * + * @param buf Pointer to the data to be sent + * @param len Number of bytes to be sent + * @return True if the payload was delivered successfully false if not + */ + bool write( const void* buf, uint8_t len ); + + /** + * Test whether there are bytes available to be read + * + * @return True if there is a payload available, false if none is + */ + bool available(void); + + /** + * Read the payload + * + * Return the last payload received + * + * The size of data read is the fixed payload size, see getPayloadSize() + * + * @note I specifically chose 'void*' as a data type to make it easier + * for beginners to use. No casting needed. + * + * @param buf Pointer to a buffer where the data should be written + * @param len Maximum number of bytes to read into the buffer + * @return True if the payload was delivered successfully false if not + */ + bool read( void* buf, uint8_t len ); + + /** + * Open a pipe for writing + * + * Only one pipe can be open at once, but you can change the pipe + * you'll listen to. Do not call this while actively listening. + * Remember to stopListening() first. + * + * Addresses are 40-bit hex values, e.g.: + * + * @code + * openWritingPipe(0xF0F0F0F0F0); + * @endcode + * + * @param address The 40-bit address of the pipe to open. This can be + * any value whatsoever, as long as you are the only one writing to it + * and only one other radio is listening to it. Coordinate these pipe + * addresses amongst nodes on the network. + */ + void openWritingPipe(uint64_t address); + + /** + * Open a pipe for reading + * + * Up to 6 pipes can be open for reading at once. Open all the + * reading pipes, and then call startListening(). + * + * @see openWritingPipe + * + * @warning Pipes 1-5 should share the first 32 bits. + * Only the least significant byte should be unique, e.g. + * @code + * openReadingPipe(1,0xF0F0F0F0AA); + * openReadingPipe(2,0xF0F0F0F066); + * @endcode + * + * @warning Pipe 0 is also used by the writing pipe. So if you open + * pipe 0 for reading, and then startListening(), it will overwrite the + * writing pipe. Ergo, do an openWritingPipe() again before write(). + * + * @todo Enforce the restriction that pipes 1-5 must share the top 32 bits + * + * @param number Which pipe# to open, 0-5. + * @param address The 40-bit address of the pipe to open. + */ + void openReadingPipe(uint8_t number, uint64_t address); + + /**@}*/ + /** + * @name Optional Configurators + * + * Methods you can use to get or set the configuration of the chip. + * None are required. Calling begin() sets up a reasonable set of + * defaults. + */ + /**@{*/ + /** + * Set the number and delay of retries upon failed submit + * + * @param delay How long to wait between each retry, in multiples of 250us, + * max is 15. 0 means 250us, 15 means 4000us. + * @param count How many retries before giving up, max 15 + */ + void setRetries(uint8_t delay, uint8_t count); + + /** + * Set RF communication channel + * + * @param channel Which RF channel to communicate on, 0-127 + */ + void setChannel(uint8_t channel); + + /** + * Set Static Payload Size + * + * This implementation uses a pre-stablished fixed payload size for all + * transmissions. If this method is never called, the driver will always + * transmit the maximum payload size (32 bytes), no matter how much + * was sent to write(). + * + * @todo Implement variable-sized payloads feature + * + * @param size The number of bytes in the payload + */ + void setPayloadSize(uint8_t size); + + /** + * Get Static Payload Size + * + * @see setPayloadSize() + * + * @return The number of bytes in the payload + */ + uint8_t getPayloadSize(void); + + /** + * Get Dynamic Payload Size + * + * For dynamic payloads, this pulls the size of the payload off + * the chip + * + * @return Payload length of last-received dynamic payload + */ + uint8_t getDynamicPayloadSize(void); + + /** + * Enable custom payloads on the acknowledge packets + * + * Ack payloads are a handy way to return data back to senders without + * manually changing the radio modes on both units. + * + * @see examples/pingpair_pl/pingpair_pl.pde + */ + void enableAckPayload(void); + + /** + * Enable dynamically-sized payloads + * + * This way you don't always have to send large packets just to send them + * once in a while. This enables dynamic payloads on ALL pipes. + * + * @see examples/pingpair_pl/pingpair_dyn.pde + */ + void enableDynamicPayloads(void); + + /** + * Determine whether the hardware is an nRF24L01+ or not. + * + * @return true if the hardware is nRF24L01+ (or compatible) and false + * if its not. + */ + bool isPVariant(void) ; + + /** + * Enable or disable auto-acknowlede packets + * + * This is enabled by default, so it's only needed if you want to turn + * it off for some reason. + * + * @param enable Whether to enable (true) or disable (false) auto-acks + */ + void setAutoAck(bool enable); + + /** + * Enable or disable auto-acknowlede packets on a per pipeline basis. + * + * AA is enabled by default, so it's only needed if you want to turn + * it off/on for some reason on a per pipeline basis. + * + * @param pipe Which pipeline to modify + * @param enable Whether to enable (true) or disable (false) auto-acks + */ + void setAutoAck( uint8_t pipe, bool enable ) ; + + /** + * Set Power Amplifier (PA) level to one of four levels. + * Relative mnemonics have been used to allow for future PA level + * changes. According to 6.5 of the nRF24L01+ specification sheet, + * they translate to: RF24_PA_MIN=-18dBm, RF24_PA_LOW=-12dBm, + * RF24_PA_MED=-6dBM, and RF24_PA_HIGH=0dBm. + * + * @param level Desired PA level. + */ + void setPALevel( rf24_pa_dbm_e level ) ; + + /** + * Fetches the current PA level. + * + * @return Returns a value from the rf24_pa_dbm_e enum describing + * the current PA setting. Please remember, all values represented + * by the enum mnemonics are negative dBm. See setPALevel for + * return value descriptions. + */ + rf24_pa_dbm_e getPALevel( void ) ; + + /** + * Set the transmission data rate + * + * @warning setting RF24_250KBPS will fail for non-plus units + * + * @param speed RF24_250KBPS for 250kbs, RF24_1MBPS for 1Mbps, or RF24_2MBPS for 2Mbps + * @return true if the change was successful + */ + bool setDataRate(rf24_datarate_e speed); + + /** + * Fetches the transmission data rate + * + * @return Returns the hardware's currently configured datarate. The value + * is one of 250kbs, RF24_1MBPS for 1Mbps, or RF24_2MBPS, as defined in the + * rf24_datarate_e enum. + */ + rf24_datarate_e getDataRate( void ) ; + + /** + * Set the CRC length + * + * @param length RF24_CRC_8 for 8-bit or RF24_CRC_16 for 16-bit + */ + void setCRCLength(rf24_crclength_e length); + + /** + * Get the CRC length + * + * @return RF24_DISABLED if disabled or RF24_CRC_8 for 8-bit or RF24_CRC_16 for 16-bit + */ + rf24_crclength_e getCRCLength(void); + + /** + * Disable CRC validation + * + */ + void disableCRC( void ) ; + + /**@}*/ + /** + * @name Advanced Operation + * + * Methods you can use to drive the chip in more advanced ways + */ + /**@{*/ + + /** + * Print a giant block of debugging information to stdout + * + * @warning Does nothing if stdout is not defined. See fdevopen in stdio.h + */ + void printDetails(void); + + /** + * Enter low-power mode + * + * To return to normal power mode, either write() some data or + * startListening, or powerUp(). + */ + void powerDown(void); + + /** + * Leave low-power mode - making radio more responsive + * + * To return to low power mode, call powerDown(). + */ + void powerUp(void) ; + + /** + * Test whether there are bytes available to be read + * + * Use this version to discover on which pipe the message + * arrived. + * + * @param[out] pipe_num Which pipe has the payload available + * @return True if there is a payload available, false if none is + */ + bool available(uint8_t* pipe_num); + + /** + * Non-blocking write to the open writing pipe + * + * Just like write(), but it returns immediately. To find out what happened + * to the send, catch the IRQ and then call whatHappened(). + * + * @see write() + * @see whatHappened() + * + * @param buf Pointer to the data to be sent + * @param len Number of bytes to be sent + * @return True if the payload was delivered successfully false if not + */ + void startWrite( const void* buf, uint8_t len ); + + /** + * Write an ack payload for the specified pipe + * + * The next time a message is received on @p pipe, the data in @p buf will + * be sent back in the acknowledgement. + * + * @warning According to the data sheet, only three of these can be pending + * at any time. I have not tested this. + * + * @param pipe Which pipe# (typically 1-5) will get this response. + * @param buf Pointer to data that is sent + * @param len Length of the data to send, up to 32 bytes max. Not affected + * by the static payload set by setPayloadSize(). + */ + void writeAckPayload(uint8_t pipe, const void* buf, uint8_t len); + + /** + * Determine if an ack payload was received in the most recent call to + * write(). + * + * Call read() to retrieve the ack payload. + * + * @warning Calling this function clears the internal flag which indicates + * a payload is available. If it returns true, you must read the packet + * out as the very next interaction with the radio, or the results are + * undefined. + * + * @return True if an ack payload is available. + */ + bool isAckPayloadAvailable(void); + + /** + * Call this when you get an interrupt to find out why + * + * Tells you what caused the interrupt, and clears the state of + * interrupts. + * + * @param[out] tx_ok The send was successful (TX_DS) + * @param[out] tx_fail The send failed, too many retries (MAX_RT) + * @param[out] rx_ready There is a message waiting to be read (RX_DS) + */ + void whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready); + + /** + * Test whether there was a carrier on the line for the + * previous listening period. + * + * Useful to check for interference on the current channel. + * + * @return true if was carrier, false if not + */ + bool testCarrier(void); + + /** + * Test whether a signal (carrier or otherwise) greater than + * or equal to -64dBm is present on the channel. Valid only + * on nRF24L01P (+) hardware. On nRF24L01, use testCarrier(). + * + * Useful to check for interference on the current channel and + * channel hopping strategies. + * + * @return true if signal => -64dBm, false if not + */ + bool testRPD(void) ; + + /** + * Test whether this is a real radio, or a mock shim for + * debugging. Setting either pin to 0xff is the way to + * indicate that this is not a real radio. + * + * @return true if this is a legitimate radio + */ + bool isValid() { return ce_pin != 0xff && csn_pin != 0xff; } + + /**@}*/ +}; + +/** + * @example GettingStarted.pde + * + * This is an example which corresponds to my "Getting Started" blog post: + * Getting Started with nRF24L01+ on Arduino. + * + * It is an example of how to use the RF24 class. Write this sketch to two + * different nodes. Put one of the nodes into 'transmit' mode by connecting + * with the serial monitor and sending a 'T'. The ping node sends the current + * time to the pong node, which responds by sending the value back. The ping + * node can then see how long the whole cycle took. + */ + +/** + * @example nordic_fob.pde + * + * This is an example of how to use the RF24 class to receive signals from the + * Sparkfun Nordic FOB. See http://www.sparkfun.com/products/8602 . + * Thanks to Kirk Mower for providing test hardware. + */ + +/** + * @example led_remote.pde + * + * This is an example of how to use the RF24 class to control a remote + * bank of LED's using buttons on a remote control. + * + * Every time the buttons change on the remote, the entire state of + * buttons is send to the led board, which displays the state. + */ + +/** + * @example pingpair.pde + * + * This is an example of how to use the RF24 class. Write this sketch to two + * different nodes, connect the role_pin to ground on one. The ping node sends + * the current time to the pong node, which responds by sending the value back. + * The ping node can then see how long the whole cycle took. + */ + +/** + * @example pingpair_maple.pde + * + * This is an example of how to use the RF24 class on the Maple. For a more + * detailed explanation, see my blog post: + * nRF24L01+ Running on Maple + * + * It will communicate well to an Arduino-based unit as well, so it's not for only Maple-to-Maple communication. + * + * Write this sketch to two different nodes, + * connect the role_pin to ground on one. The ping node sends the current time to the pong node, + * which responds by sending the value back. The ping node can then see how long the whole cycle + * took. + */ + +/** + * @example starping.pde + * + * This sketch is a more complex example of using the RF24 library for Arduino. + * Deploy this on up to six nodes. Set one as the 'pong receiver' by tying the + * role_pin low, and the others will be 'ping transmit' units. The ping units + * unit will send out the value of millis() once a second. The pong unit will + * respond back with a copy of the value. Each ping unit can get that response + * back, and determine how long the whole cycle took. + * + * This example requires a bit more complexity to determine which unit is which. + * The pong receiver is identified by having its role_pin tied to ground. + * The ping senders are further differentiated by a byte in eeprom. + */ + +/** + * @example pingpair_pl.pde + * + * This is an example of how to do two-way communication without changing + * transmit/receive modes. Here, a payload is set to the transmitter within + * the Ack packet of each transmission. Note that the payload is set BEFORE + * the sender's message arrives. + */ + +/** + * @example pingpair_irq.pde + * + * This is an example of how to user interrupts to interact with the radio. + * It builds on the pingpair_pl example, and uses ack payloads. + */ + +/** + * @example pingpair_sleepy.pde + * + * This is an example of how to use the RF24 class to create a battery- + * efficient system. It is just like the pingpair.pde example, but the + * ping node powers down the radio and sleeps the MCU after every + * ping/pong cycle. + */ + +/** + * @example scanner.pde + * + * Example to detect interference on the various channels available. + * This is a good diagnostic tool to check whether you're picking a + * good channel for your application. + * + * Inspired by cpixip. + * See http://arduino.cc/forum/index.php/topic,54795.0.html + */ + +/** + * @mainpage Driver for nRF24L01(+) 2.4GHz Wireless Transceiver + * + * @section Goals Design Goals + * + * This library is designed to be... + * @li Maximally compliant with the intended operation of the chip + * @li Easy for beginners to use + * @li Consumed with a public interface that's similiar to other Arduino standard libraries + * + * @section News News + * + * NOW COMPATIBLE WITH ARDUINO 1.0 - The 'master' branch and all examples work with both Arduino 1.0 and earlier versions. + * Please open an issue if you find any problems using it with any version of Arduino. + * + * NOW COMPATIBLE WITH MAPLE - RF24 has been tested with the + * Maple Native, + * and should work with any Maple board. See the pingpair_maple example. + * Note that only the pingpair_maple example has been tested on Maple, although + * the others can certainly be adapted. + * + * @section Useful Useful References + * + * Please refer to: + * + * @li Documentation Main Page + * @li RF24 Class Documentation + * @li Source Code + * @li Downloads Page + * @li Chip Datasheet + * + * This chip uses the SPI bus, plus two chip control pins. Remember that pin 10 must still remain an output, or + * the SPI hardware will go into 'slave' mode. + * + * @section More More Information + * + * @subpage FAQ + * + * @section Projects Projects + * + * Stuff I have built with RF24 + * + * RF24 Getting Started - Finished Product + * + * Getting Started with nRF24L01+ on Arduino + * + * Nordic FOB and nRF24L01+ + * + * Using the Sparkfun Nordic FOB + * + * RF Duinode V3 (2V4) + * + * Low-Power Wireless Sensor Node + * + * nRF24L01+ connected to Leaf Labs Maple Native + * + * nRF24L01+ Running on Maple + */ + +#endif // __RF24_H__ +// vim:ai:cin:sts=2 sw=2 ft=cpp + diff --git a/hardware/digistump/avr/libraries/RF24/RF24_config.h b/hardware/digistump/avr/libraries/RF24/RF24_config.h new file mode 100644 index 0000000..fc7397f --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/RF24_config.h @@ -0,0 +1,65 @@ + +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +#ifndef __RF24_CONFIG_H__ +#define __RF24_CONFIG_H__ + +#if ARDUINO < 100 +#include +#else +#include +#endif + +#include + +// Stuff that is normally provided by Arduino +#ifdef ARDUINO +#include +#else +#include +#include +#include +extern HardwareSPI SPI; +#define _BV(x) (1<<(x)) +#endif + +#undef SERIAL_DEBUG +#ifdef SERIAL_DEBUG +#define IF_SERIAL_DEBUG(x) ({x;}) +#else +#define IF_SERIAL_DEBUG(x) +#endif + +// Avoid spurious warnings +#if 1 +#if ! defined( NATIVE ) && defined( ARDUINO ) +#undef PROGMEM +#define PROGMEM __attribute__(( section(".progmem.data") )) +#undef PSTR +#define PSTR(s) (__extension__({static const char __c[] PROGMEM = (s); &__c[0];})) +#endif +#endif + +// Progmem is Arduino-specific +#ifdef ARDUINO +#include +#define PRIPSTR "%S" +#else +typedef char const char; +typedef uint16_t prog_uint16_t; +#define PSTR(x) (x) +#define printf_P printf +#define strlen_P strlen +#define PROGMEM +#define pgm_read_word(p) (*(p)) +#define PRIPSTR "%s" +#endif + +#endif // __RF24_CONFIG_H__ +// vim:ai:cin:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/doxygen-custom.css b/hardware/digistump/avr/libraries/RF24/doxygen-custom.css new file mode 100644 index 0000000..d7d0e12 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/doxygen-custom.css @@ -0,0 +1,835 @@ +/* The standard CSS for doxygen */ + +body, table, div, p, dl { + font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif; + font-size: 12px; +} + +/* @group Heading Levels */ + +h1 { + font-size: 150%; +} + +.title { + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2 { + font-size: 120%; +} + +h3 { + font-size: 100%; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; 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+ /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 8px; + -moz-border-radius-topleft: 8px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 8px; + -webkit-border-top-left-radius: 8px; + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + +} + +.memdoc { + border-bottom: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 2px 5px; + background-color: #FBFCFD; + border-top-width: 0; + /* opera specific markup */ + border-bottom-left-radius: 8px; + border-bottom-right-radius: 8px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 8px; + -moz-border-radius-bottomright: 8px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7); + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 8px; + -webkit-border-bottom-right-radius: 8px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7)); +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} + +.params, .retval, .exception, .tparams { + border-spacing: 6px 2px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + + + + +/* @end */ + +/* @group Directory (tree) */ + +/* for the tree view */ + +.ftvtree { + font-family: sans-serif; + margin: 0px; +} + +/* these are for tree view when used as main index */ + +.directory { + font-size: 9pt; + font-weight: bold; + margin: 5px; +} + +.directory h3 { + margin: 0px; + margin-top: 1em; + font-size: 11pt; +} + +/* +The following two styles can be used to replace the root node title +with an image of your choice. Simply uncomment the next two styles, +specify the name of your image and be sure to set 'height' to the +proper pixel height of your image. +*/ + +/* +.directory h3.swap { + height: 61px; + background-repeat: no-repeat; + background-image: url("yourimage.gif"); +} +.directory h3.swap span { + display: none; +} +*/ + +.directory > h3 { + margin-top: 0; +} + +.directory p { + margin: 0px; + white-space: nowrap; +} + +.directory div { + display: none; + margin: 0px; +} + +.directory img { + vertical-align: -30%; +} + +/* these are for tree view when not used as main index */ + +.directory-alt { + font-size: 100%; + font-weight: bold; +} + +.directory-alt h3 { + margin: 0px; + margin-top: 1em; + font-size: 11pt; +} + +.directory-alt > h3 { + margin-top: 0; +} + +.directory-alt p { + margin: 0px; + white-space: nowrap; +} + +.directory-alt div { + display: none; + margin: 0px; +} + +.directory-alt img { + vertical-align: -30%; +} + +/* @end */ + +div.dynheader { + margin-top: 8px; +} + +address { + font-style: normal; + color: #2A3D61; +} + +table.doxtable { + border-collapse:collapse; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; +} + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + height:30px; + line-height:30px; + color:#8AA0CC; + border:solid 1px #C2CDE4; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#364D7C; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; +} + +.navpath li.navelem a:hover +{ + color:#6884BD; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#364D7C; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + font-size: 8pt; + padding-left: 5px; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C4CFE5; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +dl +{ + padding: 0 0 0 10px; +} + +dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug +{ + border-left:4px solid; + padding: 0 0 0 6px; +} + +dl.note +{ + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + border-color: #00D000; +} + +dl.deprecated +{ + border-color: #505050; +} + +dl.todo +{ + border-color: #00C0E0; +} + +dl.test +{ + border-color: #3030E0; +} + +dl.bug +{ + border-color: #C08050; +} + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5373B4; +} + +.image +{ + text-align: left; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + diff --git a/hardware/digistump/avr/libraries/RF24/examples/GettingStarted/GettingStarted.pde b/hardware/digistump/avr/libraries/RF24/examples/GettingStarted/GettingStarted.pde new file mode 100644 index 0000000..bf1851a --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/GettingStarted/GettingStarted.pde @@ -0,0 +1,227 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * Example for Getting Started with nRF24L01+ radios. + * + * This is an example of how to use the RF24 class. Write this sketch to two + * different nodes. Put one of the nodes into 'transmit' mode by connecting + * with the serial monitor and sending a 'T'. The ping node sends the current + * time to the pong node, which responds by sending the value back. The ping + * node can then see how long the whole cycle took. + */ + +#include +#include "nRF24L01.h" +#include "RF24.h" +#include "printf.h" + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 9 & 10 + +RF24 radio(9,10); + +// +// Topology +// + +// Radio pipe addresses for the 2 nodes to communicate. +const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL }; + +// +// Role management +// +// Set up role. This sketch uses the same software for all the nodes +// in this system. Doing so greatly simplifies testing. +// + +// The various roles supported by this sketch +typedef enum { role_ping_out = 1, role_pong_back } role_e; + +// The debug-friendly names of those roles +const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"}; + +// The role of the current running sketch +role_e role = role_pong_back; + +void setup(void) +{ + // + // Print preamble + // + + Serial.begin(57600); + printf_begin(); + printf("\n\rRF24/examples/GettingStarted/\n\r"); + printf("ROLE: %s\n\r",role_friendly_name[role]); + printf("*** PRESS 'T' to begin transmitting to the other node\n\r"); + + // + // Setup and configure rf radio + // + + radio.begin(); + + // optionally, increase the delay between retries & # of retries + radio.setRetries(15,15); + + // optionally, reduce the payload size. seems to + // improve reliability + //radio.setPayloadSize(8); + + // + // Open pipes to other nodes for communication + // + + // This simple sketch opens two pipes for these two nodes to communicate + // back and forth. + // Open 'our' pipe for writing + // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading) + + //if ( role == role_ping_out ) + { + //radio.openWritingPipe(pipes[0]); + radio.openReadingPipe(1,pipes[1]); + } + //else + { + //radio.openWritingPipe(pipes[1]); + //radio.openReadingPipe(1,pipes[0]); + } + + // + // Start listening + // + + radio.startListening(); + + // + // Dump the configuration of the rf unit for debugging + // + + radio.printDetails(); +} + +void loop(void) +{ + // + // Ping out role. Repeatedly send the current time + // + + if (role == role_ping_out) + { + // First, stop listening so we can talk. + radio.stopListening(); + + // Take the time, and send it. This will block until complete + unsigned long time = millis(); + printf("Now sending %lu...",time); + bool ok = radio.write( &time, sizeof(unsigned long) ); + + if (ok) + printf("ok..."); + else + printf("failed.\n\r"); + + // Now, continue listening + radio.startListening(); + + // Wait here until we get a response, or timeout (250ms) + unsigned long started_waiting_at = millis(); + bool timeout = false; + while ( ! radio.available() && ! timeout ) + if (millis() - started_waiting_at > 200 ) + timeout = true; + + // Describe the results + if ( timeout ) + { + printf("Failed, response timed out.\n\r"); + } + else + { + // Grab the response, compare, and send to debugging spew + unsigned long got_time; + radio.read( &got_time, sizeof(unsigned long) ); + + // Spew it + printf("Got response %lu, round-trip delay: %lu\n\r",got_time,millis()-got_time); + } + + // Try again 1s later + delay(1000); + } + + // + // Pong back role. Receive each packet, dump it out, and send it back + // + + if ( role == role_pong_back ) + { + // if there is data ready + if ( radio.available() ) + { + // Dump the payloads until we've gotten everything + unsigned long got_time; + bool done = false; + while (!done) + { + // Fetch the payload, and see if this was the last one. + done = radio.read( &got_time, sizeof(unsigned long) ); + + // Spew it + printf("Got payload %lu...",got_time); + + // Delay just a little bit to let the other unit + // make the transition to receiver + delay(20); + } + + // First, stop listening so we can talk + radio.stopListening(); + + // Send the final one back. + radio.write( &got_time, sizeof(unsigned long) ); + printf("Sent response.\n\r"); + + // Now, resume listening so we catch the next packets. + radio.startListening(); + } + } + + // + // Change roles + // + + if ( Serial.available() ) + { + char c = toupper(Serial.read()); + if ( c == 'T' && role == role_pong_back ) + { + printf("*** CHANGING TO TRANSMIT ROLE -- PRESS 'R' TO SWITCH BACK\n\r"); + + // Become the primary transmitter (ping out) + role = role_ping_out; + radio.openWritingPipe(pipes[0]); + radio.openReadingPipe(1,pipes[1]); + } + else if ( c == 'R' && role == role_ping_out ) + { + printf("*** CHANGING TO RECEIVE ROLE -- PRESS 'T' TO SWITCH BACK\n\r"); + + // Become the primary receiver (pong back) + role = role_pong_back; + radio.openWritingPipe(pipes[1]); + radio.openReadingPipe(1,pipes[0]); + } + } +} +// vim:cin:ai:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/examples/GettingStarted/Jamfile b/hardware/digistump/avr/libraries/RF24/examples/GettingStarted/Jamfile new file mode 100644 index 0000000..9a5f2c4 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/GettingStarted/Jamfile @@ -0,0 +1,210 @@ +# (1) Project Information + +PROJECT_LIBS = SPI RF24 ; + +# (2) Board Information + +UPLOAD_PROTOCOL ?= arduino ; +UPLOAD_SPEED ?= 57600 ; +MCU ?= atmega328p ; +F_CPU ?= 16000000 ; +CORE ?= arduino ; +VARIANT ?= standard ; +ARDUINO_VERSION ?= 100 ; + +# (3) USB Ports + +PORTS = p4 p6 p9 u0 u1 u2 ; +PORT_p6 = /dev/tty.usbserial-A600eHIs ; +PORT_p4 = /dev/tty.usbserial-A40081RP ; +PORT_p9 = /dev/tty.usbserial-A9007LmI ; +PORT_u0 = /dev/ttyUSB0 ; +PORT_u1 = /dev/ttyUSB1 ; +PORT_u2 = /dev/ttyUSB2 ; + +# (4) Location of AVR tools +# +# This configuration assumes using avr-tools that were obtained separate from the Arduino +# distribution. + +if $(OS) = MACOSX +{ + AVR_BIN = /usr/local/avrtools/bin ; + AVR_ETC = /usr/local/avrtools/etc ; + AVR_INCLUDE = /usr/local/avrtools/include ; +} +else +{ + AVR_BIN ?= /usr/bin ; + AVR_INCLUDE ?= /usr/lib/avr/include ; + AVR_ETC = /etc ; +} + +# (5) Directories where Arduino core and libraries are located + +ARDUINO_DIR ?= /opt/Arduino ; +ARDUINO_CORE = $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ; +ARDUINO_LIB = $(ARDUINO_DIR)/libraries ; +SKETCH_LIB = $(HOME)/Source/Arduino/libraries ; + +# +# -------------------------------------------------- +# Below this line usually never needs to be modified +# + +# Tool locations + +CC = $(AVR_BIN)/avr-gcc ; +C++ = $(AVR_BIN)/avr-g++ ; +LINK = $(AVR_BIN)/avr-gcc ; +OBJCOPY = $(AVR_BIN)/avr-objcopy ; +AVRDUDE = $(AVR_BIN)/avrdude ; + +# Flags + +DEFINES += F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ; +OPTIM = -Os ; +CCFLAGS = -Wall -Wextra -mmcu=$(MCU) -ffunction-sections -fdata-sections ; +C++FLAGS = $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ; +LINKFLAGS = $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ; +AVRDUDEFLAGS = -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ; + +# Search everywhere for headers + +HDRS = $(PWD) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ; + +# Output locations + +LOCATE_TARGET = $(F_CPU) ; +LOCATE_SOURCE = $(F_CPU) ; + +# +# Custom rules +# + +rule GitVersion +{ + Always $(<) ; + Depends all : $(<) ; +} + +actions GitVersion +{ + echo "const char program_version[] = \"\\" > $(<) + git log -1 --pretty=format:%h >> $(<) + echo "\";" >> $(<) +} + +GitVersion version.h ; + +rule Pde +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_SOURCE) ; + Clean clean : $(<) ; +} + +if ( $(ARDUINO_VERSION) < 100 ) +{ + ARDUINO_H = WProgram.h ; +} +else +{ + ARDUINO_H = Arduino.h ; +} + +actions Pde +{ + echo "#include <$(ARDUINO_H)>" > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule C++Pde +{ + local _CPP = $(>:B).cpp ; + Pde $(_CPP) : $(>) ; + C++ $(<) : $(_CPP) ; +} + +rule UserObject +{ + switch $(>:S) + { + case .ino : C++Pde $(<) : $(>) ; + case .pde : C++Pde $(<) : $(>) ; + } +} + +rule Objects +{ + local _i ; + + for _i in [ FGristFiles $(<) ] + { + local _b = $(_i:B)$(SUFOBJ) ; + local _o = $(_b:G=$(SOURCE_GRIST:E)) ; + Object $(_o) : $(_i) ; + Depends obj : $(_o) ; + } +} + +rule Main +{ + MainFromObjects $(<) : $(>:B)$(SUFOBJ) ; + Objects $(>) ; +} + +rule Hex +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_TARGET) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions Hex +{ + $(OBJCOPY) -O ihex -R .eeprom $(>) $(<) +} + +rule Upload +{ + Depends $(1) : $(2) ; + Depends $(2) : $(3) ; + NotFile $(1) ; + Always $(1) ; + Always $(2) ; + UploadAction $(2) : $(3) ; +} + +actions UploadAction +{ + $(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i +} + +# +# Targets +# + +# Grab everything from the core directory +CORE_MODULES = [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ; + +# Grab everything from libraries. To avoid this "grab everything" behaviour, you +# can specify specific modules to pick up in PROJECT_MODULES +LIB_MODULES = [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ; + +# Grab everything from the current dir +PROJECT_MODULES += [ GLOB $(PWD) : *.c *.cpp *.pde *.ino ] ; + +# Main output executable +MAIN = $(PWD:B).elf ; + +Main $(MAIN) : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ; +Hex $(MAIN:B).hex : $(MAIN) ; + +# Upload targets +for _p in $(PORTS) +{ + Upload $(_p) : $(PORT_$(_p)) : $(MAIN:B).hex ; +} diff --git a/hardware/digistump/avr/libraries/RF24/examples/GettingStarted/printf.h b/hardware/digistump/avr/libraries/RF24/examples/GettingStarted/printf.h new file mode 100644 index 0000000..b2efd56 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/GettingStarted/printf.h @@ -0,0 +1,37 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file printf.h + * + * Setup necessary to direct stdout to the Arduino Serial library, which + * enables 'printf' + */ + +#ifndef __PRINTF_H__ +#define __PRINTF_H__ + +#ifdef ARDUINO + +int serial_putc( char c, FILE * ) +{ + Serial.write( c ); + + return c; +} + +void printf_begin(void) +{ + fdevopen( &serial_putc, 0 ); +} + +#else +#error This example is only for use on Arduino. +#endif // ARDUINO + +#endif // __PRINTF_H__ diff --git a/hardware/digistump/avr/libraries/RF24/examples/digispark_receive/digispark_receive.ino b/hardware/digistump/avr/libraries/RF24/examples/digispark_receive/digispark_receive.ino new file mode 100644 index 0000000..e990b51 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/digispark_receive/digispark_receive.ino @@ -0,0 +1,41 @@ +#include +#include "nRF24L01.h" +#include "RF24.h" + +RF24 radio(9,12); +const int LED = 1; + +const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL }; + +// The various roles supported by this sketch +typedef enum { role_ping_out = 1, role_pong_back } role_e; + +// The role of the current running sketch +role_e role = role_pong_back; + +void setup() { + // put your setup code here, to run once: + pinMode(LED, OUTPUT); + + digitalWrite(LED, LOW); + radio.begin(); + radio.setRetries(15, 15); + radio.openReadingPipe(1, pipes[1]); + radio.startListening(); + digitalWrite(LED, HIGH); +} + +void loop() { + if(radio.available()) { + unsigned long value; + bool done = false; + while(!done) { + done = radio.read(&value, sizeof(unsigned long)); + delay(20); + } + + digitalWrite(LED, LOW); + delay(1000); + digitalWrite(LED, HIGH); + } +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/RF24/examples/digispark_send/digispark_send.ino b/hardware/digistump/avr/libraries/RF24/examples/digispark_send/digispark_send.ino new file mode 100644 index 0000000..062dde7 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/digispark_send/digispark_send.ino @@ -0,0 +1,36 @@ +#include +#include "nRF24L01.h" +#include "RF24.h" + +RF24 radio(9,12); +const int LED = 1; + +const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL }; + +// The various roles supported by this sketch +typedef enum { role_ping_out = 1, role_pong_back } role_e; + +// The role of the current running sketch +role_e role = role_pong_back; + +void setup() { + // put your setup code here, to run once: + pinMode(LED, OUTPUT); + + digitalWrite(LED, LOW); + radio.begin(); + radio.setRetries(15, 15); + radio.openWritingPipe(pipes[1]); + digitalWrite(LED, HIGH); +} + +void loop() { + unsigned long value = 2000; + bool ok = radio.write(&value, sizeof(unsigned long)); + + if(ok) { + digitalWrite(LED, LOW); + delay(2000); + digitalWrite(LED, HIGH); + } +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/RF24/examples/led_remote/Jamfile b/hardware/digistump/avr/libraries/RF24/examples/led_remote/Jamfile new file mode 100644 index 0000000..901f8da --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/led_remote/Jamfile @@ -0,0 +1,206 @@ +PROJECT_NAME = $(PWD:B) ; +PROJECT_DIR = . ; +PROJECT_LIBS = SPI RF24 ; + +OUT_DIR = ojam ; +F_CPU = 16000000 ; +MCU = atmega328p ; +PORTS = /dev/tty.usbserial-A600eHIs /dev/tty.usbserial-A40081RP /dev/tty.usbserial-A9007LmI ; + +UPLOAD_RATE = 57600 ; +AVRDUDE_PROTOCOL = stk500v1 ; +COM = 33 ; + +# Host-specific overrides for locations +if $(OS) = MACOSX +{ +ARDUINO_VERSION = 22 ; +OLD_DIR = /opt/arduino-0021 ; +AVR_TOOLS_PATH = $(OLD_DIR)/hardware/tools/avr/bin ; +AVRDUDECONFIG_PATH = $(OLD_DIR)/hardware/tools/avr/etc ; +ARDUINO_DIR = /opt/Arduino ; +ARDUINO_AVR = /usr/lib/avr/include ; +} + +# Where is everything? +ARDUINO_VERSION ?= 22 ; +AVR_TOOLS_PATH ?= /usr/bin ; +ARDUINO_DIR ?= /opt/arduino-00$(ARDUINO_VERSION) ; +ARDUINO_AVR ?= $(ARDUINO_DIR)/hardware/tools/avr/avr/include/avr ; +AVRDUDECONFIG_PATH ?= $(ARDUINO_DIR)/hardware/tools ; +ARDUINO_CORE = $(ARDUINO_DIR)/hardware/arduino/cores/arduino ; +ARDUINO_LIB = $(ARDUINO_DIR)/libraries ; +SKETCH_LIB = $(HOME)/Source/Arduino/libraries ; +AVR_CC = $(AVR_TOOLS_PATH)/avr-gcc ; +AVR_CXX = $(AVR_TOOLS_PATH)/avr-g++ ; +AVR_LD = $(AVR_TOOLS_PATH)/avr-gcc ; +AVR_OBJCOPY = $(AVR_TOOLS_PATH)/avr-objcopy ; +AVRDUDE = $(AVR_TOOLS_PATH)/avrdude ; + +DEFINES = F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ; +CTUNING = -ffunction-sections -fdata-sections ; +CXXTUNING = -fno-exceptions -fno-strict-aliasing ; +CFLAGS = -Os -Wall -Wextra -mmcu=$(MCU) $(CTUNING) ; +CXXFLAGS = $(CFLAGS) $(CXXTUNING) ; +LDFLAGS = -Os -lm -Wl,--gc-sections -mmcu=atmega328p ; + +# Search everywhere for headers +HDRS = $(PROJECT_DIR) $(ARDUINO_AVR) $(ARDUINO_CORE) [ GLOB $(ARDUINO_LIB) $(SKETCH_LIB) : [^.]* ] ; + +# Grab everything from the core directory +CORE_MODULES = [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ; + +# Grab everything from libraries. To avoid this "grab everything" behaviour, you +# can specify specific modules to pick up in PROJECT_MODULES +LIB_MODULES = [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp ] ; + +# In addition to explicitly-specified program modules, pick up anything from the current +# dir. +PROJECT_MODULES += [ GLOB $(PROJECT_DIR) : *.c *.cpp *.pde ] ; + +# Shortcut for the out files +OUT = $(OUT_DIR)/$(PROJECT_NAME) ; + +# AvrDude setup +AVRDUDE_FLAGS = -V -F -D -C $(AVRDUDECONFIG_PATH)/avrdude.conf -p $(MCU) -c $(AVRDUDE_PROTOCOL) -b $(UPLOAD_RATE) ; + +rule GitVersion +{ + Always $(<) ; + Depends all : $(<) ; +} + +actions GitVersion +{ + echo "const char program_version[] = \"\\" > $(<) + git log -1 --pretty=format:%h >> $(<) + echo "\";" >> $(<) +} + +GitVersion version.h ; + +rule AvrCc +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrCc +{ + $(AVR_CC) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CFLAGS) $(>) +} + +rule AvrC++ +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrC++ +{ + $(AVR_CXX) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) +} + +rule Pde +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + +} + +actions Pde +{ + echo "#include " > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule AvrPde +{ + local _CPP = $(OUT_DIR)/$(_I:B).cpp ; + Pde $(_CPP) : $(>) ; + AvrC++ $(<) : $(_CPP) ; +} + +rule AvrObject +{ + switch $(>:S) + { + case .c : AvrCc $(<) : $(>) ; + case .cpp : AvrC++ $(<) : $(>) ; + case .pde : AvrPde $(<) : $(>) ; + } +} + +rule AvrObjects +{ + for _I in $(<) + { + AvrObject $(OUT_DIR)/$(_I:B).o : $(_I) ; + } +} + +rule AvrMainFromObjects +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + MkDir $(<:D) ; + Depends all : $(<) ; + Clean clean : $(<) ; +} + +actions AvrMainFromObjects +{ + $(AVR_LD) $(LDFLAGS) -o $(<) $(>) +} + +rule AvrMain +{ + AvrMainFromObjects $(<) : $(OUT_DIR)/$(>:B).o ; + AvrObjects $(>) ; +} + +rule AvrHex +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions AvrHex +{ + $(AVR_OBJCOPY) -O ihex -R .eeprom $(>) $(<) +} + +rule AvrUpload +{ + Depends $(1) : $(2) ; + Depends $(2) : $(3) ; + NotFile $(1) ; + Always $(1) ; + Always $(2) ; + AvrUploadAction $(2) : $(3) ; +} + +actions AvrUploadAction +{ + $(AVRDUDE) $(AVRDUDE_FLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i +} + +AvrMain $(OUT).elf : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ; +AvrHex $(OUT).hex : $(OUT).elf ; + +AvrUpload p6 : /dev/tty.usbserial-A600eHIs : $(OUT).hex ; +AvrUpload p4 : /dev/tty.usbserial-A40081RP : $(OUT).hex ; +AvrUpload p9 : /dev/tty.usbserial-A9007LmI : $(OUT).hex ; + diff --git a/hardware/digistump/avr/libraries/RF24/examples/led_remote/led_remote.pde b/hardware/digistump/avr/libraries/RF24/examples/led_remote/led_remote.pde new file mode 100644 index 0000000..80e2955 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/led_remote/led_remote.pde @@ -0,0 +1,255 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * Example LED Remote + * + * This is an example of how to use the RF24 class to control a remote + * bank of LED's using buttons on a remote control. + * + * On the 'remote', connect any number of buttons or switches from + * an arduino pin to ground. Update 'button_pins' to reflect the + * pins used. + * + * On the 'led' board, connect the same number of LED's from an + * arduino pin to a resistor to ground. Update 'led_pins' to reflect + * the pins used. Also connect a separate pin to ground and change + * the 'role_pin'. This tells the sketch it's running on the LED board. + * + * Every time the buttons change on the remote, the entire state of + * buttons is send to the led board, which displays the state. + */ + +#include +#include "nRF24L01.h" +#include "RF24.h" +#include "printf.h" + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 9 & 10 + +RF24 radio(9,10); + +// sets the role of this unit in hardware. Connect to GND to be the 'led' board receiver +// Leave open to be the 'remote' transmitter +const int role_pin = A4; + +// Pins on the remote for buttons +const uint8_t button_pins[] = { 2,3,4,5,6,7 }; +const uint8_t num_button_pins = sizeof(button_pins); + +// Pins on the LED board for LED's +const uint8_t led_pins[] = { 2,3,4,5,6,7 }; +const uint8_t num_led_pins = sizeof(led_pins); + +// +// Topology +// + +// Single radio pipe address for the 2 nodes to communicate. +const uint64_t pipe = 0xE8E8F0F0E1LL; + +// +// Role management +// +// Set up role. This sketch uses the same software for all the nodes in this +// system. Doing so greatly simplifies testing. The hardware itself specifies +// which node it is. +// +// This is done through the role_pin +// + +// The various roles supported by this sketch +typedef enum { role_remote = 1, role_led } role_e; + +// The debug-friendly names of those roles +const char* role_friendly_name[] = { "invalid", "Remote", "LED Board"}; + +// The role of the current running sketch +role_e role; + +// +// Payload +// + +uint8_t button_states[num_button_pins]; +uint8_t led_states[num_led_pins]; + +// +// Setup +// + +void setup(void) +{ + // + // Role + // + + // set up the role pin + pinMode(role_pin, INPUT); + digitalWrite(role_pin,HIGH); + delay(20); // Just to get a solid reading on the role pin + + // read the address pin, establish our role + if ( digitalRead(role_pin) ) + role = role_remote; + else + role = role_led; + + // + // Print preamble + // + + Serial.begin(57600); + printf_begin(); + printf("\n\rRF24/examples/led_remote/\n\r"); + printf("ROLE: %s\n\r",role_friendly_name[role]); + + // + // Setup and configure rf radio + // + + radio.begin(); + + // + // Open pipes to other nodes for communication + // + + // This simple sketch opens a single pipes for these two nodes to communicate + // back and forth. One listens on it, the other talks to it. + + if ( role == role_remote ) + { + radio.openWritingPipe(pipe); + } + else + { + radio.openReadingPipe(1,pipe); + } + + // + // Start listening + // + + if ( role == role_led ) + radio.startListening(); + + // + // Dump the configuration of the rf unit for debugging + // + + radio.printDetails(); + + // + // Set up buttons / LED's + // + + // Set pull-up resistors for all buttons + if ( role == role_remote ) + { + int i = num_button_pins; + while(i--) + { + pinMode(button_pins[i],INPUT); + digitalWrite(button_pins[i],HIGH); + } + } + + // Turn LED's ON until we start getting keys + if ( role == role_led ) + { + int i = num_led_pins; + while(i--) + { + pinMode(led_pins[i],OUTPUT); + led_states[i] = HIGH; + digitalWrite(led_pins[i],led_states[i]); + } + } + +} + +// +// Loop +// + +void loop(void) +{ + // + // Remote role. If the state of any button has changed, send the whole state of + // all buttons. + // + + if ( role == role_remote ) + { + // Get the current state of buttons, and + // Test if the current state is different from the last state we sent + int i = num_button_pins; + bool different = false; + while(i--) + { + uint8_t state = ! digitalRead(button_pins[i]); + if ( state != button_states[i] ) + { + different = true; + button_states[i] = state; + } + } + + // Send the state of the buttons to the LED board + if ( different ) + { + printf("Now sending..."); + bool ok = radio.write( button_states, num_button_pins ); + if (ok) + printf("ok\n\r"); + else + printf("failed\n\r"); + } + + // Try again in a short while + delay(20); + } + + // + // LED role. Receive the state of all buttons, and reflect that in the LEDs + // + + if ( role == role_led ) + { + // if there is data ready + if ( radio.available() ) + { + // Dump the payloads until we've gotten everything + bool done = false; + while (!done) + { + // Fetch the payload, and see if this was the last one. + done = radio.read( button_states, num_button_pins ); + + // Spew it + printf("Got buttons\n\r"); + + // For each button, if the button now on, then toggle the LED + int i = num_led_pins; + while(i--) + { + if ( button_states[i] ) + { + led_states[i] ^= HIGH; + digitalWrite(led_pins[i],led_states[i]); + } + } + } + } + } +} +// vim:ai:cin:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/examples/led_remote/printf.h b/hardware/digistump/avr/libraries/RF24/examples/led_remote/printf.h new file mode 100644 index 0000000..b2efd56 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/led_remote/printf.h @@ -0,0 +1,37 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file printf.h + * + * Setup necessary to direct stdout to the Arduino Serial library, which + * enables 'printf' + */ + +#ifndef __PRINTF_H__ +#define __PRINTF_H__ + +#ifdef ARDUINO + +int serial_putc( char c, FILE * ) +{ + Serial.write( c ); + + return c; +} + +void printf_begin(void) +{ + fdevopen( &serial_putc, 0 ); +} + +#else +#error This example is only for use on Arduino. +#endif // ARDUINO + +#endif // __PRINTF_H__ diff --git a/hardware/digistump/avr/libraries/RF24/examples/nordic_fob/Jamfile b/hardware/digistump/avr/libraries/RF24/examples/nordic_fob/Jamfile new file mode 100644 index 0000000..ec519f7 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/nordic_fob/Jamfile @@ -0,0 +1,219 @@ +# (1) Project Information + +PROJECT_LIBS = RF24 SPI ; +PROJECT_DIRS = $(PWD) ; + +# (2) Board Information + +UPLOAD_PROTOCOL ?= stk500v1 ; +UPLOAD_SPEED ?= 115200 ; +MCU ?= atmega328p ; +F_CPU ?= 16000000 ; +CORE ?= arduino ; +VARIANT ?= standard ; +ARDUINO_VERSION ?= 100 ; + +# (3) USB Ports + +PORTS = p4 p6 p9 u0 u1 u2 ; +PORT_p6 = /dev/tty.usbserial-A600eHIs ; +PORT_p4 = /dev/tty.usbserial-A40081RP ; +PORT_p9 = /dev/tty.usbserial-A9007LmI ; +PORT_u0 = /dev/ttyUSB0 ; +PORT_u1 = /dev/ttyUSB1 ; +PORT_u2 = /dev/ttyUSB2 ; + +# (4) Location of AVR tools +# +# This configuration assumes using avr-tools that were obtained separate from the Arduino +# distribution. + +if $(OS) = MACOSX +{ + AVR_BIN = /usr/local/avrtools/bin ; + AVR_ETC = /usr/local/avrtools/etc ; + AVR_INCLUDE = /usr/local/avrtools/include ; +} +else +{ + AVR_BIN = /usr/bin ; + AVR_INCLUDE = /usr/lib/avr/include ; + AVR_ETC = /etc ; +} + +# (5) Directories where Arduino core and libraries are located + +ARDUINO_DIR ?= /opt/Arduino ; +ARDUINO_CORE = $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ; +ARDUINO_LIB = $(ARDUINO_DIR)/libraries ; +SKETCH_LIB = $(HOME)/Source/Arduino/libraries ; + +# +# -------------------------------------------------- +# Below this line usually never needs to be modified +# + +# Tool locations + +CC = $(AVR_BIN)/avr-gcc ; +C++ = $(AVR_BIN)/avr-g++ ; +LINK = $(AVR_BIN)/avr-gcc ; +AR = $(AVR_BIN)/avr-ar rcs ; +RANLIB = ; +OBJCOPY = $(AVR_BIN)/avr-objcopy ; +AVRDUDE = $(AVR_BIN)/avrdude ; + +# Flags + +DEFINES += F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ; +OPTIM = -Os ; +CCFLAGS = -Wall -Wextra -Wno-strict-aliasing -mmcu=$(MCU) -ffunction-sections -fdata-sections ; +C++FLAGS = $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ; +LINKFLAGS = $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ; +AVRDUDEFLAGS = -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ; + +# Search everywhere for headers + +HDRS = $(PROJECT_DIRS) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ; + +# Output locations + +LOCATE_TARGET = $(F_CPU) ; +LOCATE_SOURCE = $(F_CPU) ; + +# +# Custom rules +# + +rule GitVersion +{ + Always $(<) ; + Depends all : $(<) ; +} + +actions GitVersion +{ + echo "const char program_version[] = \"\\" > $(<) + git log -1 --pretty=format:%h >> $(<) + echo "\";" >> $(<) +} + +GitVersion version.h ; + +rule Pde +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_SOURCE) ; + Clean clean : $(<) ; +} + +if ( $(ARDUINO_VERSION) < 100 ) +{ + ARDUINO_H = WProgram.h ; +} +else +{ + ARDUINO_H = Arduino.h ; +} + +actions Pde +{ + echo "#include <$(ARDUINO_H)>" > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule C++Pde +{ + local _CPP = $(>:B).cpp ; + Pde $(_CPP) : $(>) ; + C++ $(<) : $(_CPP) ; +} + +rule UserObject +{ + switch $(>:S) + { + case .ino : C++Pde $(<) : $(>) ; + case .pde : C++Pde $(<) : $(>) ; + } +} + +rule Objects +{ + local _i ; + + for _i in [ FGristFiles $(<) ] + { + local _b = $(_i:B)$(SUFOBJ) ; + local _o = $(_b:G=$(SOURCE_GRIST:E)) ; + Object $(_o) : $(_i) ; + Depends obj : $(_o) ; + } +} + +rule Library +{ + LibraryFromObjects $(<) : $(>:B)$(SUFOBJ) ; + Objects $(>) ; +} + +rule Main +{ + MainFromObjects $(<) : $(>:B)$(SUFOBJ) ; + Objects $(>) ; +} + +rule Hex +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_TARGET) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions Hex +{ + $(OBJCOPY) -O ihex -R .eeprom $(>) $(<) +} + +rule Upload +{ + Depends $(1) : $(2) ; + Depends $(2) : $(3) ; + NotFile $(1) ; + Always $(1) ; + Always $(2) ; + UploadAction $(2) : $(3) ; +} + +actions UploadAction +{ + $(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i +} + +rule Arduino +{ + LINKFLAGS on $(<) = $(LINKFLAGS) -Wl,-Map=$(LOCATE_TARGET)/$(<:B).map ; + Main $(<) : $(>) ; + LinkLibraries $(<) : libs core ; + Hex $(<:B).hex : $(<) ; + for _p in $(PORTS) + { + Upload $(_p) : $(PORT_$(_p)) : $(<:B).hex ; + } +} + +# +# Targets +# + +# Grab everything from the core directory +Library core : [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ; + +# Grab everything from libraries. To avoid this "grab everything" behaviour, you +# can specify specific modules to pick up in PROJECT_MODULES +Library libs : [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ; + +# Main output executable +Arduino $(PWD:B).elf : $(PROJECT_MODULES) [ GLOB $(PROJECT_DIRS) : *.c *.cpp *.pde *.ino ] ; diff --git a/hardware/digistump/avr/libraries/RF24/examples/nordic_fob/nordic_fob.pde b/hardware/digistump/avr/libraries/RF24/examples/nordic_fob/nordic_fob.pde new file mode 100644 index 0000000..5a316a0 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/nordic_fob/nordic_fob.pde @@ -0,0 +1,142 @@ +/* + Copyright (C) 2012 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * Example Nordic FOB Receiver + * + * This is an example of how to use the RF24 class to receive signals from the + * Sparkfun Nordic FOB. Thanks to Kirk Mower for providing test hardware. + * + * See blog post at http://maniacbug.wordpress.com/2012/01/08/nordic-fob/ + */ + +#include +#include +#include "nRF24L01.h" +#include "printf.h" + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 9 & 10 + +RF24 radio(9,10); + +// +// Payload +// + +struct payload_t +{ + uint8_t buttons; + uint16_t id; + uint8_t empty; +}; + +const char* button_names[] = { "Up", "Down", "Left", "Right", "Center" }; +const int num_buttons = 5; + +// +// Forward declarations +// + +uint16_t flip_endian(uint16_t in); + +// +// Setup +// + +void setup(void) +{ + // + // Print preamble + // + + Serial.begin(57600); + printf_begin(); + printf("\r\nRF24/examples/nordic_fob/\r\n"); + + // + // Setup and configure rf radio according to the built-in parameters + // of the FOB. + // + + radio.begin(); + radio.setChannel(2); + radio.setPayloadSize(4); + radio.setAutoAck(false); + radio.setCRCLength(RF24_CRC_8); + radio.openReadingPipe(1,0xE7E7E7E7E7LL); + + // + // Start listening + // + + radio.startListening(); + + // + // Dump the configuration of the rf unit for debugging + // + + radio.printDetails(); +} + +// +// Loop +// + +void loop(void) +{ + // + // Receive each packet, dump it out + // + + // if there is data ready + if ( radio.available() ) + { + // Get the packet from the radio + payload_t payload; + radio.read( &payload, sizeof(payload) ); + + // Print the ID of this message. Note that the message + // is sent 'big-endian', so we have to flip it. + printf("#%05u Buttons ",flip_endian(payload.id)); + + // Print the name of each button + int i = num_buttons; + while (i--) + { + if ( ! ( payload.buttons & _BV(i) ) ) + { + printf("%s ",button_names[i]); + } + } + + // If no buttons, print None + if ( payload.buttons == _BV(num_buttons) - 1 ) + printf("None"); + + printf("\r\n"); + } +} + +// +// Helper functions +// + +// Change a big-endian word into a little-endian +uint16_t flip_endian(uint16_t in) +{ + uint16_t low = in >> 8; + uint16_t high = in << 8; + + return high | low; +} + +// vim:cin:ai:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/examples/nordic_fob/printf.h b/hardware/digistump/avr/libraries/RF24/examples/nordic_fob/printf.h new file mode 100644 index 0000000..b2efd56 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/nordic_fob/printf.h @@ -0,0 +1,37 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file printf.h + * + * Setup necessary to direct stdout to the Arduino Serial library, which + * enables 'printf' + */ + +#ifndef __PRINTF_H__ +#define __PRINTF_H__ + +#ifdef ARDUINO + +int serial_putc( char c, FILE * ) +{ + Serial.write( c ); + + return c; +} + +void printf_begin(void) +{ + fdevopen( &serial_putc, 0 ); +} + +#else +#error This example is only for use on Arduino. +#endif // ARDUINO + +#endif // __PRINTF_H__ diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair/Jamfile b/hardware/digistump/avr/libraries/RF24/examples/pingpair/Jamfile new file mode 100644 index 0000000..18244ec --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair/Jamfile @@ -0,0 +1,219 @@ +# (1) Project Information + +PROJECT_LIBS = SPI RF24 ; +PROJECT_DIRS = $(PWD) ; + +# (2) Board Information + +UPLOAD_PROTOCOL ?= arduino ; +UPLOAD_SPEED ?= 115200 ; +MCU ?= atmega328p ; +F_CPU ?= 16000000 ; +CORE ?= arduino ; +VARIANT ?= standard ; +ARDUINO_VERSION ?= 100 ; + +# (3) USB Ports + +PORTS = p4 p6 p9 u0 u1 u2 ; +PORT_p6 = /dev/tty.usbserial-A600eHIs ; +PORT_p4 = /dev/tty.usbserial-A40081RP ; +PORT_p9 = /dev/tty.usbserial-A9007LmI ; +PORT_u0 = /dev/ttyUSB0 ; +PORT_u1 = /dev/ttyUSB1 ; +PORT_u2 = /dev/ttyUSB2 ; + +# (4) Location of AVR tools +# +# This configuration assumes using avr-tools that were obtained separate from the Arduino +# distribution. + +if $(OS) = MACOSX +{ + AVR_BIN ?= /usr/local/avrtools/bin ; + AVR_ETC = /usr/local/avrtools/etc ; + AVR_INCLUDE = /usr/local/avrtools/include ; +} +else +{ + AVR_BIN ?= /usr/bin ; + AVR_INCLUDE = /usr/lib/avr/include ; + AVR_ETC = /etc ; +} + +# (5) Directories where Arduino core and libraries are located + +ARDUINO_DIR ?= /opt/Arduino ; +ARDUINO_CORE = $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ; +ARDUINO_LIB = $(ARDUINO_DIR)/libraries ; +SKETCH_LIB = $(HOME)/Source/Arduino/libraries ; + +# +# -------------------------------------------------- +# Below this line usually never needs to be modified +# + +# Tool locations + +CC = $(AVR_BIN)/avr-gcc ; +C++ = $(AVR_BIN)/avr-g++ ; +LINK = $(AVR_BIN)/avr-gcc ; +AR = $(AVR_BIN)/avr-ar rcs ; +RANLIB = ; +OBJCOPY = $(AVR_BIN)/avr-objcopy ; +AVRDUDE ?= $(AVR_BIN)/avrdude ; + +# Flags + +DEFINES += F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ; +OPTIM = -Os ; +CCFLAGS = -Wall -Wextra -Wno-strict-aliasing -mmcu=$(MCU) -ffunction-sections -fdata-sections ; +C++FLAGS = $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ; +LINKFLAGS = $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ; +AVRDUDEFLAGS = -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ; + +# Search everywhere for headers + +HDRS = $(PROJECT_DIRS) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ; + +# Output locations + +LOCATE_TARGET = $(F_CPU) ; +LOCATE_SOURCE = $(F_CPU) ; + +# +# Custom rules +# + +rule GitVersion +{ + Always $(<) ; + Depends all : $(<) ; +} + +actions GitVersion +{ + echo "const char program_version[] = \"\\" > $(<) + git log -1 --pretty=format:%h >> $(<) + echo "\";" >> $(<) +} + +GitVersion version.h ; + +rule Pde +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_SOURCE) ; + Clean clean : $(<) ; +} + +if ( $(ARDUINO_VERSION) < 100 ) +{ + ARDUINO_H = WProgram.h ; +} +else +{ + ARDUINO_H = Arduino.h ; +} + +actions Pde +{ + echo "#include <$(ARDUINO_H)>" > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule C++Pde +{ + local _CPP = $(>:B).cpp ; + Pde $(_CPP) : $(>) ; + C++ $(<) : $(_CPP) ; +} + +rule UserObject +{ + switch $(>:S) + { + case .ino : C++Pde $(<) : $(>) ; + case .pde : C++Pde $(<) : $(>) ; + } +} + +rule Objects +{ + local _i ; + + for _i in [ FGristFiles $(<) ] + { + local _b = $(_i:B)$(SUFOBJ) ; + local _o = $(_b:G=$(SOURCE_GRIST:E)) ; + Object $(_o) : $(_i) ; + Depends obj : $(_o) ; + } +} + +rule Library +{ + LibraryFromObjects $(<) : $(>:B)$(SUFOBJ) ; + Objects $(>) ; +} + +rule Main +{ + MainFromObjects $(<) : $(>:B)$(SUFOBJ) ; + Objects $(>) ; +} + +rule Hex +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_TARGET) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions Hex +{ + $(OBJCOPY) -O ihex -R .eeprom $(>) $(<) +} + +rule Upload +{ + Depends $(1) : $(2) ; + Depends $(2) : $(3) ; + NotFile $(1) ; + Always $(1) ; + Always $(2) ; + UploadAction $(2) : $(3) ; +} + +actions UploadAction +{ + $(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i +} + +rule Arduino +{ + LINKFLAGS on $(<) = $(LINKFLAGS) -Wl,-Map=$(LOCATE_TARGET)/$(<:B).map ; + Main $(<) : $(>) ; + LinkLibraries $(<) : core libs ; + Hex $(<:B).hex : $(<) ; + for _p in $(PORTS) + { + Upload $(_p) : $(PORT_$(_p)) : $(<:B).hex ; + } +} + +# +# Targets +# + +# Grab everything from the core directory +Library core : [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ; + +# Grab everything from libraries. To avoid this "grab everything" behaviour, you +# can specify specific modules to pick up in PROJECT_MODULES +Library libs : [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ; + +# Main output executable +Arduino $(PWD:B).elf : $(PROJECT_MODULES) [ GLOB $(PROJECT_DIRS) : *.c *.cpp *.pde *.ino ] ; diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair/pingpair.pde b/hardware/digistump/avr/libraries/RF24/examples/pingpair/pingpair.pde new file mode 100644 index 0000000..3a57a67 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair/pingpair.pde @@ -0,0 +1,220 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * Example RF Radio Ping Pair + * + * This is an example of how to use the RF24 class. Write this sketch to two different nodes, + * connect the role_pin to ground on one. The ping node sends the current time to the pong node, + * which responds by sending the value back. The ping node can then see how long the whole cycle + * took. + */ + +#include +#include "nRF24L01.h" +#include "RF24.h" +#include "printf.h" + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 9 & 10 + +RF24 radio(9,10); + +// sets the role of this unit in hardware. Connect to GND to be the 'pong' receiver +// Leave open to be the 'ping' transmitter +const int role_pin = 7; + +// +// Topology +// + +// Radio pipe addresses for the 2 nodes to communicate. +const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL }; + +// +// Role management +// +// Set up role. This sketch uses the same software for all the nodes +// in this system. Doing so greatly simplifies testing. The hardware itself specifies +// which node it is. +// +// This is done through the role_pin +// + +// The various roles supported by this sketch +typedef enum { role_ping_out = 1, role_pong_back } role_e; + +// The debug-friendly names of those roles +const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"}; + +// The role of the current running sketch +role_e role; + +void setup(void) +{ + // + // Role + // + + // set up the role pin + pinMode(role_pin, INPUT); + digitalWrite(role_pin,HIGH); + delay(20); // Just to get a solid reading on the role pin + + // read the address pin, establish our role + if ( ! digitalRead(role_pin) ) + role = role_ping_out; + else + role = role_pong_back; + + // + // Print preamble + // + + Serial.begin(57600); + printf_begin(); + printf("\n\rRF24/examples/pingpair/\n\r"); + printf("ROLE: %s\n\r",role_friendly_name[role]); + + // + // Setup and configure rf radio + // + + radio.begin(); + + // optionally, increase the delay between retries & # of retries + radio.setRetries(15,15); + + // optionally, reduce the payload size. seems to + // improve reliability + radio.setPayloadSize(8); + + // + // Open pipes to other nodes for communication + // + + // This simple sketch opens two pipes for these two nodes to communicate + // back and forth. + // Open 'our' pipe for writing + // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading) + + if ( role == role_ping_out ) + { + radio.openWritingPipe(pipes[0]); + radio.openReadingPipe(1,pipes[1]); + } + else + { + radio.openWritingPipe(pipes[1]); + radio.openReadingPipe(1,pipes[0]); + } + + // + // Start listening + // + + radio.startListening(); + + // + // Dump the configuration of the rf unit for debugging + // + + radio.printDetails(); +} + +void loop(void) +{ + // + // Ping out role. Repeatedly send the current time + // + + if (role == role_ping_out) + { + // First, stop listening so we can talk. + radio.stopListening(); + + // Take the time, and send it. This will block until complete + unsigned long time = millis(); + printf("Now sending %lu...",time); + bool ok = radio.write( &time, sizeof(unsigned long) ); + + if (ok) + printf("ok..."); + else + printf("failed.\n\r"); + + // Now, continue listening + radio.startListening(); + + // Wait here until we get a response, or timeout (250ms) + unsigned long started_waiting_at = millis(); + bool timeout = false; + while ( ! radio.available() && ! timeout ) + if (millis() - started_waiting_at > 200 ) + timeout = true; + + // Describe the results + if ( timeout ) + { + printf("Failed, response timed out.\n\r"); + } + else + { + // Grab the response, compare, and send to debugging spew + unsigned long got_time; + radio.read( &got_time, sizeof(unsigned long) ); + + // Spew it + printf("Got response %lu, round-trip delay: %lu\n\r",got_time,millis()-got_time); + } + + // Try again 1s later + delay(1000); + } + + // + // Pong back role. Receive each packet, dump it out, and send it back + // + + if ( role == role_pong_back ) + { + // if there is data ready + if ( radio.available() ) + { + // Dump the payloads until we've gotten everything + unsigned long got_time; + bool done = false; + while (!done) + { + // Fetch the payload, and see if this was the last one. + done = radio.read( &got_time, sizeof(unsigned long) ); + + // Spew it + printf("Got payload %lu...",got_time); + + // Delay just a little bit to let the other unit + // make the transition to receiver + delay(20); + } + + // First, stop listening so we can talk + radio.stopListening(); + + // Send the final one back. + radio.write( &got_time, sizeof(unsigned long) ); + printf("Sent response.\n\r"); + + // Now, resume listening so we catch the next packets. + radio.startListening(); + } + } +} +// vim:cin:ai:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair/printf.h b/hardware/digistump/avr/libraries/RF24/examples/pingpair/printf.h new file mode 100644 index 0000000..b2efd56 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair/printf.h @@ -0,0 +1,37 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file printf.h + * + * Setup necessary to direct stdout to the Arduino Serial library, which + * enables 'printf' + */ + +#ifndef __PRINTF_H__ +#define __PRINTF_H__ + +#ifdef ARDUINO + +int serial_putc( char c, FILE * ) +{ + Serial.write( c ); + + return c; +} + +void printf_begin(void) +{ + fdevopen( &serial_putc, 0 ); +} + +#else +#error This example is only for use on Arduino. +#endif // ARDUINO + +#endif // __PRINTF_H__ diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_dyn/Jamfile b/hardware/digistump/avr/libraries/RF24/examples/pingpair_dyn/Jamfile new file mode 100644 index 0000000..901f8da --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_dyn/Jamfile @@ -0,0 +1,206 @@ +PROJECT_NAME = $(PWD:B) ; +PROJECT_DIR = . ; +PROJECT_LIBS = SPI RF24 ; + +OUT_DIR = ojam ; +F_CPU = 16000000 ; +MCU = atmega328p ; +PORTS = /dev/tty.usbserial-A600eHIs /dev/tty.usbserial-A40081RP /dev/tty.usbserial-A9007LmI ; + +UPLOAD_RATE = 57600 ; +AVRDUDE_PROTOCOL = stk500v1 ; +COM = 33 ; + +# Host-specific overrides for locations +if $(OS) = MACOSX +{ +ARDUINO_VERSION = 22 ; +OLD_DIR = /opt/arduino-0021 ; +AVR_TOOLS_PATH = $(OLD_DIR)/hardware/tools/avr/bin ; +AVRDUDECONFIG_PATH = $(OLD_DIR)/hardware/tools/avr/etc ; +ARDUINO_DIR = /opt/Arduino ; +ARDUINO_AVR = /usr/lib/avr/include ; +} + +# Where is everything? +ARDUINO_VERSION ?= 22 ; +AVR_TOOLS_PATH ?= /usr/bin ; +ARDUINO_DIR ?= /opt/arduino-00$(ARDUINO_VERSION) ; +ARDUINO_AVR ?= $(ARDUINO_DIR)/hardware/tools/avr/avr/include/avr ; +AVRDUDECONFIG_PATH ?= $(ARDUINO_DIR)/hardware/tools ; +ARDUINO_CORE = $(ARDUINO_DIR)/hardware/arduino/cores/arduino ; +ARDUINO_LIB = $(ARDUINO_DIR)/libraries ; +SKETCH_LIB = $(HOME)/Source/Arduino/libraries ; +AVR_CC = $(AVR_TOOLS_PATH)/avr-gcc ; +AVR_CXX = $(AVR_TOOLS_PATH)/avr-g++ ; +AVR_LD = $(AVR_TOOLS_PATH)/avr-gcc ; +AVR_OBJCOPY = $(AVR_TOOLS_PATH)/avr-objcopy ; +AVRDUDE = $(AVR_TOOLS_PATH)/avrdude ; + +DEFINES = F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ; +CTUNING = -ffunction-sections -fdata-sections ; +CXXTUNING = -fno-exceptions -fno-strict-aliasing ; +CFLAGS = -Os -Wall -Wextra -mmcu=$(MCU) $(CTUNING) ; +CXXFLAGS = $(CFLAGS) $(CXXTUNING) ; +LDFLAGS = -Os -lm -Wl,--gc-sections -mmcu=atmega328p ; + +# Search everywhere for headers +HDRS = $(PROJECT_DIR) $(ARDUINO_AVR) $(ARDUINO_CORE) [ GLOB $(ARDUINO_LIB) $(SKETCH_LIB) : [^.]* ] ; + +# Grab everything from the core directory +CORE_MODULES = [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ; + +# Grab everything from libraries. To avoid this "grab everything" behaviour, you +# can specify specific modules to pick up in PROJECT_MODULES +LIB_MODULES = [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp ] ; + +# In addition to explicitly-specified program modules, pick up anything from the current +# dir. +PROJECT_MODULES += [ GLOB $(PROJECT_DIR) : *.c *.cpp *.pde ] ; + +# Shortcut for the out files +OUT = $(OUT_DIR)/$(PROJECT_NAME) ; + +# AvrDude setup +AVRDUDE_FLAGS = -V -F -D -C $(AVRDUDECONFIG_PATH)/avrdude.conf -p $(MCU) -c $(AVRDUDE_PROTOCOL) -b $(UPLOAD_RATE) ; + +rule GitVersion +{ + Always $(<) ; + Depends all : $(<) ; +} + +actions GitVersion +{ + echo "const char program_version[] = \"\\" > $(<) + git log -1 --pretty=format:%h >> $(<) + echo "\";" >> $(<) +} + +GitVersion version.h ; + +rule AvrCc +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrCc +{ + $(AVR_CC) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CFLAGS) $(>) +} + +rule AvrC++ +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrC++ +{ + $(AVR_CXX) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) +} + +rule Pde +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + +} + +actions Pde +{ + echo "#include " > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule AvrPde +{ + local _CPP = $(OUT_DIR)/$(_I:B).cpp ; + Pde $(_CPP) : $(>) ; + AvrC++ $(<) : $(_CPP) ; +} + +rule AvrObject +{ + switch $(>:S) + { + case .c : AvrCc $(<) : $(>) ; + case .cpp : AvrC++ $(<) : $(>) ; + case .pde : AvrPde $(<) : $(>) ; + } +} + +rule AvrObjects +{ + for _I in $(<) + { + AvrObject $(OUT_DIR)/$(_I:B).o : $(_I) ; + } +} + +rule AvrMainFromObjects +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + MkDir $(<:D) ; + Depends all : $(<) ; + Clean clean : $(<) ; +} + +actions AvrMainFromObjects +{ + $(AVR_LD) $(LDFLAGS) -o $(<) $(>) +} + +rule AvrMain +{ + AvrMainFromObjects $(<) : $(OUT_DIR)/$(>:B).o ; + AvrObjects $(>) ; +} + +rule AvrHex +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions AvrHex +{ + $(AVR_OBJCOPY) -O ihex -R .eeprom $(>) $(<) +} + +rule AvrUpload +{ + Depends $(1) : $(2) ; + Depends $(2) : $(3) ; + NotFile $(1) ; + Always $(1) ; + Always $(2) ; + AvrUploadAction $(2) : $(3) ; +} + +actions AvrUploadAction +{ + $(AVRDUDE) $(AVRDUDE_FLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i +} + +AvrMain $(OUT).elf : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ; +AvrHex $(OUT).hex : $(OUT).elf ; + +AvrUpload p6 : /dev/tty.usbserial-A600eHIs : $(OUT).hex ; +AvrUpload p4 : /dev/tty.usbserial-A40081RP : $(OUT).hex ; +AvrUpload p9 : /dev/tty.usbserial-A9007LmI : $(OUT).hex ; + diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_dyn/pingpair_dyn.pde b/hardware/digistump/avr/libraries/RF24/examples/pingpair_dyn/pingpair_dyn.pde new file mode 100644 index 0000000..7108f3b --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_dyn/pingpair_dyn.pde @@ -0,0 +1,232 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * Example using Dynamic Payloads + * + * This is an example of how to use payloads of a varying (dynamic) size. + */ + +#include +#include "nRF24L01.h" +#include "RF24.h" +#include "printf.h" + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 9 & 10 + +RF24 radio(9,10); + +// sets the role of this unit in hardware. Connect to GND to be the 'pong' receiver +// Leave open to be the 'ping' transmitter +const int role_pin = 7; + +// +// Topology +// + +// Radio pipe addresses for the 2 nodes to communicate. +const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL }; + +// +// Role management +// +// Set up role. This sketch uses the same software for all the nodes +// in this system. Doing so greatly simplifies testing. The hardware itself specifies +// which node it is. +// +// This is done through the role_pin +// + +// The various roles supported by this sketch +typedef enum { role_ping_out = 1, role_pong_back } role_e; + +// The debug-friendly names of those roles +const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"}; + +// The role of the current running sketch +role_e role; + +// +// Payload +// + +const int min_payload_size = 4; +const int max_payload_size = 32; +const int payload_size_increments_by = 2; +int next_payload_size = min_payload_size; + +char receive_payload[max_payload_size+1]; // +1 to allow room for a terminating NULL char + +void setup(void) +{ + // + // Role + // + + // set up the role pin + pinMode(role_pin, INPUT); + digitalWrite(role_pin,HIGH); + delay(20); // Just to get a solid reading on the role pin + + // read the address pin, establish our role + if ( digitalRead(role_pin) ) + role = role_ping_out; + else + role = role_pong_back; + + // + // Print preamble + // + + Serial.begin(57600); + printf_begin(); + printf("\n\rRF24/examples/pingpair_dyn/\n\r"); + printf("ROLE: %s\n\r",role_friendly_name[role]); + + // + // Setup and configure rf radio + // + + radio.begin(); + + // enable dynamic payloads + radio.enableDynamicPayloads(); + + // optionally, increase the delay between retries & # of retries + radio.setRetries(15,15); + + // + // Open pipes to other nodes for communication + // + + // This simple sketch opens two pipes for these two nodes to communicate + // back and forth. + // Open 'our' pipe for writing + // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading) + + if ( role == role_ping_out ) + { + radio.openWritingPipe(pipes[0]); + radio.openReadingPipe(1,pipes[1]); + } + else + { + radio.openWritingPipe(pipes[1]); + radio.openReadingPipe(1,pipes[0]); + } + + // + // Start listening + // + + radio.startListening(); + + // + // Dump the configuration of the rf unit for debugging + // + + radio.printDetails(); +} + +void loop(void) +{ + // + // Ping out role. Repeatedly send the current time + // + + if (role == role_ping_out) + { + // The payload will always be the same, what will change is how much of it we send. + static char send_payload[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ789012"; + + // First, stop listening so we can talk. + radio.stopListening(); + + // Take the time, and send it. This will block until complete + printf("Now sending length %i...",next_payload_size); + radio.write( send_payload, next_payload_size ); + + // Now, continue listening + radio.startListening(); + + // Wait here until we get a response, or timeout + unsigned long started_waiting_at = millis(); + bool timeout = false; + while ( ! radio.available() && ! timeout ) + if (millis() - started_waiting_at > 500 ) + timeout = true; + + // Describe the results + if ( timeout ) + { + printf("Failed, response timed out.\n\r"); + } + else + { + // Grab the response, compare, and send to debugging spew + uint8_t len = radio.getDynamicPayloadSize(); + radio.read( receive_payload, len ); + + // Put a zero at the end for easy printing + receive_payload[len] = 0; + + // Spew it + printf("Got response size=%i value=%s\n\r",len,receive_payload); + } + + // Update size for next time. + next_payload_size += payload_size_increments_by; + if ( next_payload_size > max_payload_size ) + next_payload_size = min_payload_size; + + // Try again 1s later + delay(1000); + } + + // + // Pong back role. Receive each packet, dump it out, and send it back + // + + if ( role == role_pong_back ) + { + // if there is data ready + if ( radio.available() ) + { + // Dump the payloads until we've gotten everything + uint8_t len; + bool done = false; + while (!done) + { + // Fetch the payload, and see if this was the last one. + len = radio.getDynamicPayloadSize(); + done = radio.read( receive_payload, len ); + + // Put a zero at the end for easy printing + receive_payload[len] = 0; + + // Spew it + printf("Got payload size=%i value=%s\n\r",len,receive_payload); + } + + // First, stop listening so we can talk + radio.stopListening(); + + // Send the final one back. + radio.write( receive_payload, len ); + printf("Sent response.\n\r"); + + // Now, resume listening so we catch the next packets. + radio.startListening(); + } + } +} +// vim:cin:ai:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_dyn/printf.h b/hardware/digistump/avr/libraries/RF24/examples/pingpair_dyn/printf.h new file mode 100644 index 0000000..b2efd56 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_dyn/printf.h @@ -0,0 +1,37 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file printf.h + * + * Setup necessary to direct stdout to the Arduino Serial library, which + * enables 'printf' + */ + +#ifndef __PRINTF_H__ +#define __PRINTF_H__ + +#ifdef ARDUINO + +int serial_putc( char c, FILE * ) +{ + Serial.write( c ); + + return c; +} + +void printf_begin(void) +{ + fdevopen( &serial_putc, 0 ); +} + +#else +#error This example is only for use on Arduino. +#endif // ARDUINO + +#endif // __PRINTF_H__ diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_irq/Jamfile b/hardware/digistump/avr/libraries/RF24/examples/pingpair_irq/Jamfile new file mode 100644 index 0000000..97237bc --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_irq/Jamfile @@ -0,0 +1,219 @@ +# (1) Project Information + +PROJECT_LIBS = SPI RF24 ; +PROJECT_DIRS = $(PWD) ; + +# (2) Board Information + +UPLOAD_PROTOCOL ?= arduino ; +UPLOAD_SPEED ?= 115200 ; +MCU ?= atmega328p ; +F_CPU ?= 16000000 ; +CORE ?= arduino ; +VARIANT ?= standard ; +ARDUINO_VERSION ?= 100 ; + +# (3) USB Ports + +PORTS = p4 p6 p9 u0 u1 u2 ; +PORT_p6 = /dev/tty.usbserial-A600eHIs ; +PORT_p4 = /dev/tty.usbserial-A40081RP ; +PORT_p9 = /dev/tty.usbserial-A9007LmI ; +PORT_u0 = /dev/ttyUSB0 ; +PORT_u1 = /dev/ttyUSB1 ; +PORT_u2 = /dev/ttyUSB2 ; + +# (4) Location of AVR tools +# +# This configuration assumes using avr-tools that were obtained separate from the Arduino +# distribution. + +if $(OS) = MACOSX +{ + AVR_BIN ?= /usr/local/avrtools/bin ; + AVR_ETC = /usr/local/avrtools/etc ; + AVR_INCLUDE = /usr/local/avrtools/include ; +} +else +{ + AVR_BIN ?= /usr/bin ; + AVR_INCLUDE ?= /usr/lib/avr/include ; + AVR_ETC = /etc ; +} + +# (5) Directories where Arduino core and libraries are located + +ARDUINO_DIR ?= /opt/Arduino ; +ARDUINO_CORE = $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ; +ARDUINO_LIB = $(ARDUINO_DIR)/libraries ; +SKETCH_LIB = $(HOME)/Source/Arduino/libraries ; + +# +# -------------------------------------------------- +# Below this line usually never needs to be modified +# + +# Tool locations + +CC = $(AVR_BIN)/avr-gcc ; +C++ = $(AVR_BIN)/avr-g++ ; +LINK = $(AVR_BIN)/avr-gcc ; +AR = $(AVR_BIN)/avr-ar rcs ; +RANLIB = ; +OBJCOPY = $(AVR_BIN)/avr-objcopy ; +AVRDUDE ?= $(AVR_BIN)/avrdude ; + +# Flags + +DEFINES += F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ; +OPTIM = -Os ; +CCFLAGS = -Wall -Wextra -Wno-strict-aliasing -mmcu=$(MCU) -ffunction-sections -fdata-sections ; +C++FLAGS = $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ; +LINKFLAGS = $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ; +AVRDUDEFLAGS = -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ; + +# Search everywhere for headers + +HDRS = $(PROJECT_DIRS) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ; + +# Output locations + +LOCATE_TARGET = $(F_CPU) ; +LOCATE_SOURCE = $(F_CPU) ; + +# +# Custom rules +# + +rule GitVersion +{ + Always $(<) ; + Depends all : $(<) ; +} + +actions GitVersion +{ + echo "const char program_version[] = \"\\" > $(<) + git log -1 --pretty=format:%h >> $(<) + echo "\";" >> $(<) +} + +GitVersion version.h ; + +rule Pde +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_SOURCE) ; + Clean clean : $(<) ; +} + +if ( $(ARDUINO_VERSION) < 100 ) +{ + ARDUINO_H = WProgram.h ; +} +else +{ + ARDUINO_H = Arduino.h ; +} + +actions Pde +{ + echo "#include <$(ARDUINO_H)>" > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule C++Pde +{ + local _CPP = $(>:B).cpp ; + Pde $(_CPP) : $(>) ; + C++ $(<) : $(_CPP) ; +} + +rule UserObject +{ + switch $(>:S) + { + case .ino : C++Pde $(<) : $(>) ; + case .pde : C++Pde $(<) : $(>) ; + } +} + +rule Objects +{ + local _i ; + + for _i in [ FGristFiles $(<) ] + { + local _b = $(_i:B)$(SUFOBJ) ; + local _o = $(_b:G=$(SOURCE_GRIST:E)) ; + Object $(_o) : $(_i) ; + Depends obj : $(_o) ; + } +} + +rule Library +{ + LibraryFromObjects $(<) : $(>:B)$(SUFOBJ) ; + Objects $(>) ; +} + +rule Main +{ + MainFromObjects $(<) : $(>:B)$(SUFOBJ) ; + Objects $(>) ; +} + +rule Hex +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_TARGET) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions Hex +{ + $(OBJCOPY) -O ihex -R .eeprom $(>) $(<) +} + +rule Upload +{ + Depends $(1) : $(2) ; + Depends $(2) : $(3) ; + NotFile $(1) ; + Always $(1) ; + Always $(2) ; + UploadAction $(2) : $(3) ; +} + +actions UploadAction +{ + $(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i +} + +rule Arduino +{ + LINKFLAGS on $(<) = $(LINKFLAGS) -Wl,-Map=$(LOCATE_TARGET)/$(<:B).map ; + Main $(<) : $(>) ; + LinkLibraries $(<) : core libs ; + Hex $(<:B).hex : $(<) ; + for _p in $(PORTS) + { + Upload $(_p) : $(PORT_$(_p)) : $(<:B).hex ; + } +} + +# +# Targets +# + +# Grab everything from the core directory +Library core : [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ; + +# Grab everything from libraries. To avoid this "grab everything" behaviour, you +# can specify specific modules to pick up in PROJECT_MODULES +Library libs : [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ; + +# Main output executable +Arduino $(PWD:B).elf : $(PROJECT_MODULES) [ GLOB $(PROJECT_DIRS) : *.c *.cpp *.pde *.ino ] ; diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_irq/pingpair_irq.pde b/hardware/digistump/avr/libraries/RF24/examples/pingpair_irq/pingpair_irq.pde new file mode 100644 index 0000000..47084a1 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_irq/pingpair_irq.pde @@ -0,0 +1,216 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * Example of using interrupts + * + * This is an example of how to user interrupts to interact with the radio. + * It builds on the pingpair_pl example, and uses ack payloads. + */ + +#include +#include "nRF24L01.h" +#include "RF24.h" +#include "printf.h" + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 9 & 10 + +RF24 radio(8,9); + +// sets the role of this unit in hardware. Connect to GND to be the 'pong' receiver +// Leave open to be the 'ping' transmitter +const short role_pin = 7; + +// +// Topology +// + +// Single radio pipe address for the 2 nodes to communicate. +const uint64_t pipe = 0xE8E8F0F0E1LL; + +// +// Role management +// +// Set up role. This sketch uses the same software for all the nodes in this +// system. Doing so greatly simplifies testing. The hardware itself specifies +// which node it is. +// +// This is done through the role_pin +// + +// The various roles supported by this sketch +typedef enum { role_sender = 1, role_receiver } role_e; + +// The debug-friendly names of those roles +const char* role_friendly_name[] = { "invalid", "Sender", "Receiver"}; + +// The role of the current running sketch +role_e role; + +// Interrupt handler, check the radio because we got an IRQ +void check_radio(void); + +void setup(void) +{ + // + // Role + // + + // set up the role pin + pinMode(role_pin, INPUT); + digitalWrite(role_pin,HIGH); + delay(20); // Just to get a solid reading on the role pin + + // read the address pin, establish our role + if ( digitalRead(role_pin) ) + role = role_sender; + else + role = role_receiver; + + // + // Print preamble + // + + Serial.begin(57600); + printf_begin(); + printf("\n\rRF24/examples/pingpair_irq/\n\r"); + printf("ROLE: %s\n\r",role_friendly_name[role]); + + // + // Setup and configure rf radio + // + + radio.begin(); + + // We will be using the Ack Payload feature, so please enable it + radio.enableAckPayload(); + + // + // Open pipes to other nodes for communication + // + + // This simple sketch opens a single pipe for these two nodes to communicate + // back and forth. One listens on it, the other talks to it. + + if ( role == role_sender ) + { + radio.openWritingPipe(pipe); + } + else + { + radio.openReadingPipe(1,pipe); + } + + // + // Start listening + // + + if ( role == role_receiver ) + radio.startListening(); + + // + // Dump the configuration of the rf unit for debugging + // + + radio.printDetails(); + + // + // Attach interrupt handler to interrupt #0 (using pin 2) + // on BOTH the sender and receiver + // + + attachInterrupt(0, check_radio, FALLING); +} + +static uint32_t message_count = 0; + +void loop(void) +{ + // + // Sender role. Repeatedly send the current time + // + + if (role == role_sender) + { + // Take the time, and send it. + unsigned long time = millis(); + printf("Now sending %lu\n\r",time); + radio.startWrite( &time, sizeof(unsigned long) ); + + // Try again soon + delay(2000); + } + + // + // Receiver role: Does nothing! All the work is in IRQ + // + +} + +void check_radio(void) +{ + // What happened? + bool tx,fail,rx; + radio.whatHappened(tx,fail,rx); + + // Have we successfully transmitted? + if ( tx ) + { + if ( role == role_sender ) + printf("Send:OK\n\r"); + + if ( role == role_receiver ) + printf("Ack Payload:Sent\n\r"); + } + + // Have we failed to transmit? + if ( fail ) + { + if ( role == role_sender ) + printf("Send:Failed\n\r"); + + if ( role == role_receiver ) + printf("Ack Payload:Failed\n\r"); + } + + // Transmitter can power down for now, because + // the transmission is done. + if ( ( tx || fail ) && ( role == role_sender ) ) + radio.powerDown(); + + // Did we receive a message? + if ( rx ) + { + // If we're the sender, we've received an ack payload + if ( role == role_sender ) + { + radio.read(&message_count,sizeof(message_count)); + printf("Ack:%lu\n\r",message_count); + } + + // If we're the receiver, we've received a time message + if ( role == role_receiver ) + { + // Get this payload and dump it + static unsigned long got_time; + radio.read( &got_time, sizeof(got_time) ); + printf("Got payload %lu\n\r",got_time); + + // Add an ack packet for the next time around. This is a simple + // packet counter + radio.writeAckPayload( 1, &message_count, sizeof(message_count) ); + ++message_count; + } + } +} + +// vim:ai:cin:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_irq/printf.h b/hardware/digistump/avr/libraries/RF24/examples/pingpair_irq/printf.h new file mode 100644 index 0000000..b2efd56 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_irq/printf.h @@ -0,0 +1,37 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file printf.h + * + * Setup necessary to direct stdout to the Arduino Serial library, which + * enables 'printf' + */ + +#ifndef __PRINTF_H__ +#define __PRINTF_H__ + +#ifdef ARDUINO + +int serial_putc( char c, FILE * ) +{ + Serial.write( c ); + + return c; +} + +void printf_begin(void) +{ + fdevopen( &serial_putc, 0 ); +} + +#else +#error This example is only for use on Arduino. +#endif // ARDUINO + +#endif // __PRINTF_H__ diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_maple/Jamfile b/hardware/digistump/avr/libraries/RF24/examples/pingpair_maple/Jamfile new file mode 100644 index 0000000..798096c --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_maple/Jamfile @@ -0,0 +1,182 @@ +MCU = cortex-m3 ; +CHIP = STM32F103ZE ; +BOARD = maple_native ; + +#CHIP = at91sam3u4 ; +#BOARD = sam3u-ek ; + +if ! $(TOOLSET) +{ + TOOLSET = devkit ; + Echo "Assuming TOOLSET=devkit" ; +} + +if $(TOOLSET) = yagarto +{ + TOOLS_PATH = ~/Source/yagarto-4.6.2/bin ; + TOOLS_ARCH = arm-none-eabi- ; +} +if $(TOOLSET) = yagarto-install +{ + TOOLS_PATH = ~/Source/yagarto/install/bin ; + TOOLS_ARCH = arm-none-eabi- ; +} +else if $(TOOLSET) = devkit +{ + TOOLS_PATH = /opt/devkitARM/bin ; + TOOLS_ARCH = arm-eabi- ; +} +else if $(TOOLSET) = maple +{ + TOOLS_PATH = /opt/Maple/Resources/Java/hardware/tools/arm/bin ; + TOOLS_ARCH = arm-none-eabi- ; +} +else if $(TOOLSET) = ports +{ + TOOLS_PATH = /opt/local/bin ; + TOOLS_ARCH = arm-none-eabi- ; +} + +CC = $(TOOLS_PATH)/$(TOOLS_ARCH)gcc ; +C++ = $(TOOLS_PATH)/$(TOOLS_ARCH)g++ ; +AS = $(TOOLS_PATH)/$(TOOLS_ARCH)gcc -c ; +LINK = $(TOOLS_PATH)/$(TOOLS_ARCH)g++ ; +OBJCOPY = $(TOOLS_PATH)/$(TOOLS_ARCH)objcopy ; +DFU = dfu-util ; + +DEFINES += VECT_TAB_FLASH BOARD_$(BOARD) MCU_$(CHIP) ERROR_LED_PORT=GPIOC ERROR_LED_PIN=15 STM32_HIGH_DENSITY MAPLE_IDE ; +OPTIM = -Os ; +MFLAGS = cpu=$(MCU) thumb arch=armv7-m ; +CCFLAGS = -Wall -m$(MFLAGS) -g -nostdlib -ffunction-sections -fdata-sections -Wl,--gc-sections ; +C++FLAGS = $(CCFLAGS) -fno-rtti -fno-exceptions ; +LINKFLAGS += -m$(MFLAGS) -Xlinker --gc-sections ; +DFUFLAGS = -a1 -d 0x1eaf:0x0003 -R ; + +MAPLE_DIR = $(HOME)/Source/SAM3U/libmaple ; +MAPLE_LIBS = Servo LiquidCrystal Wire FreeRTOS ; +MAPLE_SUBDIRS = wirish wirish/comm wirish/boards libmaple libmaple/usb libmaple/usb/usb_lib ; + +SKETCH_DIR = $(HOME)/Source/Arduino ; +SKETCH_LIBS = RF24 ; + +MODULE_DIRS = . $(MAPLE_DIR)/$(MAPLE_SUBDIRS) $(MAPLE_DIR)/libraries/$(MAPLE_LIBS) $(SKETCH_DIR)/libraries/$(SKETCH_LIBS) ; +HDRS = $(MODULE_DIRS) ; +LOCATE_TARGET = out/$(TOOLSET) ; +LOCATE_SOURCE = $(LOCATE_TARGET) ; + +rule Pde +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_SOURCE) ; + Clean clean : $(<) ; +} + +if ( $(ARDUINO_VERSION) < 100 ) +{ + ARDUINO_H = WProgram.h ; +} +else +{ + ARDUINO_H = Arduino.h ; +} + +actions Pde +{ + echo "#include <$(ARDUINO_H)>" > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule C++Pde +{ + local _CPP = $(>:B).cpp ; + Pde $(_CPP) : $(>) ; + C++ $(<) : $(_CPP) ; +} + +rule Hex +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_TARGET) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions Hex +{ + $(OBJCOPY) -O ihex $(>) $(<) +} + +rule Binary +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_TARGET) ; + Depends binary : $(<) ; + Clean clean : $(<) ; +} + +actions Binary +{ + $(OBJCOPY) -O binary $(>) $(<) +} + +rule UserObject +{ + switch $(>:S) + { + case .S : As $(<) : $(>) ; + case .ino : C++Pde $(<) : $(>) ; + case .pde : C++Pde $(<) : $(>) ; + } +} + +rule Upload +{ + Depends up : $(<) ; + NotFile up ; + Always $(<) ; + Always up ; +} + +actions Upload +{ + $(DFU) $(DFUFLAGS) -D $(<) +} + +# Override base objects rule, so all output can go in the output dir +rule Objects +{ + local _i ; + + for _i in [ FGristFiles $(<) ] + { + local _b = $(_i:B)$(SUFOBJ) ; + local _o = $(_b:G=$(SOURCE_GRIST:E)) ; + Object $(_o) : $(_i) ; + Depends obj : $(_o) ; + } +} + +# Override base main rule, so all output can go in the output dir +rule Main +{ + MainFromObjects $(<) : $(>:B)$(SUFOBJ) ; + Objects $(>) ; +} + +# Modules +MODULES = [ GLOB $(MODULE_DIRS) : *.pde *.c *.cpp *.S ] ; + +# Main output executable +MAIN = $(PWD:B).elf ; + +# Linker script +LINK_DIR = $(MAPLE_DIR)/support/ld ; +LINKSCRIPT = $(LINK_DIR)/$(BOARD)/flash.ld ; + +# Bring in the map and link script +LINKFLAGS += -Wl,-Map=$(LOCATE_TARGET)/$(MAIN:B).map -T$(LINKSCRIPT) -L$(LINK_DIR) ; + +Main $(MAIN) : $(MODULES) ; +Binary $(MAIN:B).bin : $(MAIN) ; +Upload $(MAIN:B).bin ; diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_maple/main.cpp b/hardware/digistump/avr/libraries/RF24/examples/pingpair_maple/main.cpp new file mode 100644 index 0000000..b4f976d --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_maple/main.cpp @@ -0,0 +1,87 @@ +#ifdef MAPLE_IDE + +#include +#include "wirish.h" + +extern void setup(void); +extern void loop(void); + +void board_start(const char* program_name) +{ + // Set up the LED to steady on + pinMode(BOARD_LED_PIN, OUTPUT); + digitalWrite(BOARD_LED_PIN, HIGH); + + // Setup the button as input + pinMode(BOARD_BUTTON_PIN, INPUT); + digitalWrite(BOARD_BUTTON_PIN, HIGH); + + SerialUSB.begin(); + SerialUSB.println("Press BUT"); + + // Wait for button press + while ( !isButtonPressed() ) + { + } + + SerialUSB.println("Welcome!"); + SerialUSB.println(program_name); + + int i = 11; + while (i--) + { + toggleLED(); + delay(50); + } +} + +/** + * Custom version of _write, which will print to the USB. + * In order to use it you MUST ADD __attribute__((weak)) + * to _write in libmaple/syscalls.c +*/ +extern "C" int _write (int file, char * ptr, int len) +{ + if ( (file != 1) && (file != 2) ) + return 0; + else + SerialUSB.write(ptr,len); + return len; +} + +/** + * Re-entrant version of _write. Yagarto and Devkit now use + * the re-entrant newlib, so these get called instead of the + * non_r versions. + */ +extern "C" int _write_r (void*, int file, char * ptr, int len) +{ + return _write( file, ptr, len); +} + +__attribute__((constructor)) __attribute__ ((weak)) void premain() +{ + init(); +} + +__attribute__((weak)) void setup(void) +{ + board_start("No program defined"); +} + +__attribute__((weak)) void loop(void) +{ +} + +__attribute__((weak)) int main(void) +{ + setup(); + + while (true) + { + loop(); + } + return 0; +} +#endif // ifdef MAPLE_IDE +// vim:cin:ai:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_maple/pingpair_maple.pde b/hardware/digistump/avr/libraries/RF24/examples/pingpair_maple/pingpair_maple.pde new file mode 100644 index 0000000..2d3925b --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_maple/pingpair_maple.pde @@ -0,0 +1,242 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * Example RF Radio Ping Pair ... for Maple + * + * This is an example of how to use the RF24 class. Write this sketch to two different nodes, + * connect the role_pin to ground on one. The ping node sends the current time to the pong node, + * which responds by sending the value back. The ping node can then see how long the whole cycle + * took. + */ + +#include "WProgram.h" +#include +#include "nRF24L01.h" +#include "RF24.h" + +// +// Maple specific setup. Other than this section, the sketch is the same on Maple as on +// Arduino +// + +#ifdef MAPLE_IDE + +// External startup function +extern void board_start(const char* program_name); + +// Use SPI #2. +HardwareSPI SPI(2); + +#else +#define board_startup printf +#define toggleLED(x) (x) +#endif + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 7 & 6 +// (This works for the Getting Started board plugged into the +// Maple Native backwards.) + +RF24 radio(7,6); + +// sets the role of this unit in hardware. Connect to GND to be the 'pong' receiver +// Leave open to be the 'ping' transmitter +const int role_pin = 10; + +// +// Topology +// + +// Radio pipe addresses for the 2 nodes to communicate. +const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL }; + +// +// Role management +// +// Set up role. This sketch uses the same software for all the nodes +// in this system. Doing so greatly simplifies testing. The hardware itself specifies +// which node it is. +// +// This is done through the role_pin +// + +// The various roles supported by this sketch +typedef enum { role_ping_out = 1, role_pong_back } role_e; + +// The debug-friendly names of those roles +const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"}; + +// The role of the current running sketch +role_e role; + +void setup(void) +{ + // + // Role + // + + // set up the role pin + pinMode(role_pin, INPUT); + digitalWrite(role_pin,HIGH); + delay(20); // Just to get a solid reading on the role pin + + // read the address pin, establish our role + if ( digitalRead(role_pin) ) + role = role_ping_out; + else + role = role_pong_back; + + // + // Print preamble + // + + board_start("\n\rRF24/examples/pingpair/\n\r"); + printf("ROLE: %s\n\r",role_friendly_name[role]); + + // + // Setup and configure rf radio + // + + radio.begin(); + + // optionally, increase the delay between retries & # of retries + radio.setRetries(15,15); + + // optionally, reduce the payload size. seems to + // improve reliability + radio.setPayloadSize(8); + + // + // Open pipes to other nodes for communication + // + + // This simple sketch opens two pipes for these two nodes to communicate + // back and forth. + // Open 'our' pipe for writing + // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading) + + if ( role == role_ping_out ) + { + radio.openWritingPipe(pipes[0]); + radio.openReadingPipe(1,pipes[1]); + } + else + { + radio.openWritingPipe(pipes[1]); + radio.openReadingPipe(1,pipes[0]); + } + + // + // Start listening + // + + radio.startListening(); + + // + // Dump the configuration of the rf unit for debugging + // + + radio.printDetails(); +} + +void loop(void) +{ + // + // Ping out role. Repeatedly send the current time + // + + if (role == role_ping_out) + { + toggleLED(); + + // First, stop listening so we can talk. + radio.stopListening(); + + // Take the time, and send it. This will block until complete + unsigned long time = millis(); + printf("Now sending %lu...",time); + bool ok = radio.write( &time, sizeof(unsigned long) ); + + if (ok) + printf("ok...\r\n"); + else + printf("failed.\r\n"); + + // Now, continue listening + radio.startListening(); + + // Wait here until we get a response, or timeout (250ms) + unsigned long started_waiting_at = millis(); + bool timeout = false; + while ( ! radio.available() && ! timeout ) + if (millis() - started_waiting_at > 200 ) + timeout = true; + + // Describe the results + if ( timeout ) + { + printf("Failed, response timed out.\r\n"); + } + else + { + // Grab the response, compare, and send to debugging spew + unsigned long got_time; + radio.read( &got_time, sizeof(unsigned long) ); + + // Spew it + printf("Got response %lu, round-trip delay: %lu\r\n",got_time,millis()-got_time); + } + + toggleLED(); + + // Try again 1s later + delay(1000); + } + + // + // Pong back role. Receive each packet, dump it out, and send it back + // + + if ( role == role_pong_back ) + { + // if there is data ready + if ( radio.available() ) + { + // Dump the payloads until we've gotten everything + unsigned long got_time; + bool done = false; + while (!done) + { + // Fetch the payload, and see if this was the last one. + done = radio.read( &got_time, sizeof(unsigned long) ); + + // Spew it + printf("Got payload %lu...",got_time); + + // Delay just a little bit to let the other unit + // make the transition to receiver + delay(20); + } + + // First, stop listening so we can talk + radio.stopListening(); + + // Send the final one back. + radio.write( &got_time, sizeof(unsigned long) ); + printf("Sent response.\r\n"); + + // Now, resume listening so we catch the next packets. + radio.startListening(); + } + } +} +// vim:cin:ai:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_pl/Jamfile b/hardware/digistump/avr/libraries/RF24/examples/pingpair_pl/Jamfile new file mode 100644 index 0000000..901f8da --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_pl/Jamfile @@ -0,0 +1,206 @@ +PROJECT_NAME = $(PWD:B) ; +PROJECT_DIR = . ; +PROJECT_LIBS = SPI RF24 ; + +OUT_DIR = ojam ; +F_CPU = 16000000 ; +MCU = atmega328p ; +PORTS = /dev/tty.usbserial-A600eHIs /dev/tty.usbserial-A40081RP /dev/tty.usbserial-A9007LmI ; + +UPLOAD_RATE = 57600 ; +AVRDUDE_PROTOCOL = stk500v1 ; +COM = 33 ; + +# Host-specific overrides for locations +if $(OS) = MACOSX +{ +ARDUINO_VERSION = 22 ; +OLD_DIR = /opt/arduino-0021 ; +AVR_TOOLS_PATH = $(OLD_DIR)/hardware/tools/avr/bin ; +AVRDUDECONFIG_PATH = $(OLD_DIR)/hardware/tools/avr/etc ; +ARDUINO_DIR = /opt/Arduino ; +ARDUINO_AVR = /usr/lib/avr/include ; +} + +# Where is everything? +ARDUINO_VERSION ?= 22 ; +AVR_TOOLS_PATH ?= /usr/bin ; +ARDUINO_DIR ?= /opt/arduino-00$(ARDUINO_VERSION) ; +ARDUINO_AVR ?= $(ARDUINO_DIR)/hardware/tools/avr/avr/include/avr ; +AVRDUDECONFIG_PATH ?= $(ARDUINO_DIR)/hardware/tools ; +ARDUINO_CORE = $(ARDUINO_DIR)/hardware/arduino/cores/arduino ; +ARDUINO_LIB = $(ARDUINO_DIR)/libraries ; +SKETCH_LIB = $(HOME)/Source/Arduino/libraries ; +AVR_CC = $(AVR_TOOLS_PATH)/avr-gcc ; +AVR_CXX = $(AVR_TOOLS_PATH)/avr-g++ ; +AVR_LD = $(AVR_TOOLS_PATH)/avr-gcc ; +AVR_OBJCOPY = $(AVR_TOOLS_PATH)/avr-objcopy ; +AVRDUDE = $(AVR_TOOLS_PATH)/avrdude ; + +DEFINES = F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ; +CTUNING = -ffunction-sections -fdata-sections ; +CXXTUNING = -fno-exceptions -fno-strict-aliasing ; +CFLAGS = -Os -Wall -Wextra -mmcu=$(MCU) $(CTUNING) ; +CXXFLAGS = $(CFLAGS) $(CXXTUNING) ; +LDFLAGS = -Os -lm -Wl,--gc-sections -mmcu=atmega328p ; + +# Search everywhere for headers +HDRS = $(PROJECT_DIR) $(ARDUINO_AVR) $(ARDUINO_CORE) [ GLOB $(ARDUINO_LIB) $(SKETCH_LIB) : [^.]* ] ; + +# Grab everything from the core directory +CORE_MODULES = [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ; + +# Grab everything from libraries. To avoid this "grab everything" behaviour, you +# can specify specific modules to pick up in PROJECT_MODULES +LIB_MODULES = [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp ] ; + +# In addition to explicitly-specified program modules, pick up anything from the current +# dir. +PROJECT_MODULES += [ GLOB $(PROJECT_DIR) : *.c *.cpp *.pde ] ; + +# Shortcut for the out files +OUT = $(OUT_DIR)/$(PROJECT_NAME) ; + +# AvrDude setup +AVRDUDE_FLAGS = -V -F -D -C $(AVRDUDECONFIG_PATH)/avrdude.conf -p $(MCU) -c $(AVRDUDE_PROTOCOL) -b $(UPLOAD_RATE) ; + +rule GitVersion +{ + Always $(<) ; + Depends all : $(<) ; +} + +actions GitVersion +{ + echo "const char program_version[] = \"\\" > $(<) + git log -1 --pretty=format:%h >> $(<) + echo "\";" >> $(<) +} + +GitVersion version.h ; + +rule AvrCc +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrCc +{ + $(AVR_CC) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CFLAGS) $(>) +} + +rule AvrC++ +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrC++ +{ + $(AVR_CXX) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) +} + +rule Pde +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + +} + +actions Pde +{ + echo "#include " > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule AvrPde +{ + local _CPP = $(OUT_DIR)/$(_I:B).cpp ; + Pde $(_CPP) : $(>) ; + AvrC++ $(<) : $(_CPP) ; +} + +rule AvrObject +{ + switch $(>:S) + { + case .c : AvrCc $(<) : $(>) ; + case .cpp : AvrC++ $(<) : $(>) ; + case .pde : AvrPde $(<) : $(>) ; + } +} + +rule AvrObjects +{ + for _I in $(<) + { + AvrObject $(OUT_DIR)/$(_I:B).o : $(_I) ; + } +} + +rule AvrMainFromObjects +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + MkDir $(<:D) ; + Depends all : $(<) ; + Clean clean : $(<) ; +} + +actions AvrMainFromObjects +{ + $(AVR_LD) $(LDFLAGS) -o $(<) $(>) +} + +rule AvrMain +{ + AvrMainFromObjects $(<) : $(OUT_DIR)/$(>:B).o ; + AvrObjects $(>) ; +} + +rule AvrHex +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions AvrHex +{ + $(AVR_OBJCOPY) -O ihex -R .eeprom $(>) $(<) +} + +rule AvrUpload +{ + Depends $(1) : $(2) ; + Depends $(2) : $(3) ; + NotFile $(1) ; + Always $(1) ; + Always $(2) ; + AvrUploadAction $(2) : $(3) ; +} + +actions AvrUploadAction +{ + $(AVRDUDE) $(AVRDUDE_FLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i +} + +AvrMain $(OUT).elf : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ; +AvrHex $(OUT).hex : $(OUT).elf ; + +AvrUpload p6 : /dev/tty.usbserial-A600eHIs : $(OUT).hex ; +AvrUpload p4 : /dev/tty.usbserial-A40081RP : $(OUT).hex ; +AvrUpload p9 : /dev/tty.usbserial-A9007LmI : $(OUT).hex ; + diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_pl/pingpair_pl.pde b/hardware/digistump/avr/libraries/RF24/examples/pingpair_pl/pingpair_pl.pde new file mode 100644 index 0000000..70aed6e --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_pl/pingpair_pl.pde @@ -0,0 +1,180 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * Example of using Ack Payloads + * + * This is an example of how to do two-way communication without changing + * transmit/receive modes. Here, a payload is set to the transmitter within + * the Ack packet of each transmission. Note that the payload is set BEFORE + * the sender's message arrives. + */ + +#include +#include "nRF24L01.h" +#include "RF24.h" +#include "printf.h" + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 9 & 10 + +RF24 radio(9,10); + +// sets the role of this unit in hardware. Connect to GND to be the 'pong' receiver +// Leave open to be the 'ping' transmitter +const short role_pin = 7; + +// +// Topology +// + +// Single radio pipe address for the 2 nodes to communicate. +const uint64_t pipe = 0xE8E8F0F0E1LL; + +// +// Role management +// +// Set up role. This sketch uses the same software for all the nodes in this +// system. Doing so greatly simplifies testing. The hardware itself specifies +// which node it is. +// +// This is done through the role_pin +// + +// The various roles supported by this sketch +typedef enum { role_sender = 1, role_receiver } role_e; + +// The debug-friendly names of those roles +const char* role_friendly_name[] = { "invalid", "Sender", "Receiver"}; + +// The role of the current running sketch +role_e role; + +void setup(void) +{ + // + // Role + // + + // set up the role pin + pinMode(role_pin, INPUT); + digitalWrite(role_pin,HIGH); + delay(20); // Just to get a solid reading on the role pin + + // read the address pin, establish our role + if ( digitalRead(role_pin) ) + role = role_sender; + else + role = role_receiver; + + // + // Print preamble + // + + Serial.begin(57600); + printf_begin(); + printf("\n\rRF24/examples/pingpair_pl/\n\r"); + printf("ROLE: %s\n\r",role_friendly_name[role]); + + // + // Setup and configure rf radio + // + + radio.begin(); + + // We will be using the Ack Payload feature, so please enable it + radio.enableAckPayload(); + + // + // Open pipes to other nodes for communication + // + + // This simple sketch opens a single pipes for these two nodes to communicate + // back and forth. One listens on it, the other talks to it. + + if ( role == role_sender ) + { + radio.openWritingPipe(pipe); + } + else + { + radio.openReadingPipe(1,pipe); + } + + // + // Start listening + // + + if ( role == role_receiver ) + radio.startListening(); + + // + // Dump the configuration of the rf unit for debugging + // + + radio.printDetails(); +} + +void loop(void) +{ + static uint32_t message_count = 0; + + // + // Sender role. Repeatedly send the current time + // + + if (role == role_sender) + { + // Take the time, and send it. This will block until complete + unsigned long time = millis(); + printf("Now sending %lu...",time); + radio.write( &time, sizeof(unsigned long) ); + + if ( radio.isAckPayloadAvailable() ) + { + radio.read(&message_count,sizeof(message_count)); + printf("Ack: [%lu] ",message_count); + } + printf("OK\n\r"); + + // Try again soon + delay(2000); + } + + // + // Receiver role. Receive each packet, dump it out, add ack payload for next time + // + + if ( role == role_receiver ) + { + // if there is data ready + if ( radio.available() ) + { + // Dump the payloads until we've gotten everything + static unsigned long got_time; + bool done = false; + while (!done) + { + // Fetch the payload, and see if this was the last one. + done = radio.read( &got_time, sizeof(unsigned long) ); + + // Spew it + printf("Got payload %lu\n",got_time); + } + + // Add an ack packet for the next time around. This is a simple + // packet counter + radio.writeAckPayload( 1, &message_count, sizeof(message_count) ); + ++message_count; + } + } +} +// vim:ai:cin:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_pl/printf.h b/hardware/digistump/avr/libraries/RF24/examples/pingpair_pl/printf.h new file mode 100644 index 0000000..b2efd56 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_pl/printf.h @@ -0,0 +1,37 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file printf.h + * + * Setup necessary to direct stdout to the Arduino Serial library, which + * enables 'printf' + */ + +#ifndef __PRINTF_H__ +#define __PRINTF_H__ + +#ifdef ARDUINO + +int serial_putc( char c, FILE * ) +{ + Serial.write( c ); + + return c; +} + +void printf_begin(void) +{ + fdevopen( &serial_putc, 0 ); +} + +#else +#error This example is only for use on Arduino. +#endif // ARDUINO + +#endif // __PRINTF_H__ diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_sleepy/Jamfile b/hardware/digistump/avr/libraries/RF24/examples/pingpair_sleepy/Jamfile new file mode 100644 index 0000000..901f8da --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_sleepy/Jamfile @@ -0,0 +1,206 @@ +PROJECT_NAME = $(PWD:B) ; +PROJECT_DIR = . ; +PROJECT_LIBS = SPI RF24 ; + +OUT_DIR = ojam ; +F_CPU = 16000000 ; +MCU = atmega328p ; +PORTS = /dev/tty.usbserial-A600eHIs /dev/tty.usbserial-A40081RP /dev/tty.usbserial-A9007LmI ; + +UPLOAD_RATE = 57600 ; +AVRDUDE_PROTOCOL = stk500v1 ; +COM = 33 ; + +# Host-specific overrides for locations +if $(OS) = MACOSX +{ +ARDUINO_VERSION = 22 ; +OLD_DIR = /opt/arduino-0021 ; +AVR_TOOLS_PATH = $(OLD_DIR)/hardware/tools/avr/bin ; +AVRDUDECONFIG_PATH = $(OLD_DIR)/hardware/tools/avr/etc ; +ARDUINO_DIR = /opt/Arduino ; +ARDUINO_AVR = /usr/lib/avr/include ; +} + +# Where is everything? +ARDUINO_VERSION ?= 22 ; +AVR_TOOLS_PATH ?= /usr/bin ; +ARDUINO_DIR ?= /opt/arduino-00$(ARDUINO_VERSION) ; +ARDUINO_AVR ?= $(ARDUINO_DIR)/hardware/tools/avr/avr/include/avr ; +AVRDUDECONFIG_PATH ?= $(ARDUINO_DIR)/hardware/tools ; +ARDUINO_CORE = $(ARDUINO_DIR)/hardware/arduino/cores/arduino ; +ARDUINO_LIB = $(ARDUINO_DIR)/libraries ; +SKETCH_LIB = $(HOME)/Source/Arduino/libraries ; +AVR_CC = $(AVR_TOOLS_PATH)/avr-gcc ; +AVR_CXX = $(AVR_TOOLS_PATH)/avr-g++ ; +AVR_LD = $(AVR_TOOLS_PATH)/avr-gcc ; +AVR_OBJCOPY = $(AVR_TOOLS_PATH)/avr-objcopy ; +AVRDUDE = $(AVR_TOOLS_PATH)/avrdude ; + +DEFINES = F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ; +CTUNING = -ffunction-sections -fdata-sections ; +CXXTUNING = -fno-exceptions -fno-strict-aliasing ; +CFLAGS = -Os -Wall -Wextra -mmcu=$(MCU) $(CTUNING) ; +CXXFLAGS = $(CFLAGS) $(CXXTUNING) ; +LDFLAGS = -Os -lm -Wl,--gc-sections -mmcu=atmega328p ; + +# Search everywhere for headers +HDRS = $(PROJECT_DIR) $(ARDUINO_AVR) $(ARDUINO_CORE) [ GLOB $(ARDUINO_LIB) $(SKETCH_LIB) : [^.]* ] ; + +# Grab everything from the core directory +CORE_MODULES = [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ; + +# Grab everything from libraries. To avoid this "grab everything" behaviour, you +# can specify specific modules to pick up in PROJECT_MODULES +LIB_MODULES = [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp ] ; + +# In addition to explicitly-specified program modules, pick up anything from the current +# dir. +PROJECT_MODULES += [ GLOB $(PROJECT_DIR) : *.c *.cpp *.pde ] ; + +# Shortcut for the out files +OUT = $(OUT_DIR)/$(PROJECT_NAME) ; + +# AvrDude setup +AVRDUDE_FLAGS = -V -F -D -C $(AVRDUDECONFIG_PATH)/avrdude.conf -p $(MCU) -c $(AVRDUDE_PROTOCOL) -b $(UPLOAD_RATE) ; + +rule GitVersion +{ + Always $(<) ; + Depends all : $(<) ; +} + +actions GitVersion +{ + echo "const char program_version[] = \"\\" > $(<) + git log -1 --pretty=format:%h >> $(<) + echo "\";" >> $(<) +} + +GitVersion version.h ; + +rule AvrCc +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrCc +{ + $(AVR_CC) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CFLAGS) $(>) +} + +rule AvrC++ +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrC++ +{ + $(AVR_CXX) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) +} + +rule Pde +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + +} + +actions Pde +{ + echo "#include " > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule AvrPde +{ + local _CPP = $(OUT_DIR)/$(_I:B).cpp ; + Pde $(_CPP) : $(>) ; + AvrC++ $(<) : $(_CPP) ; +} + +rule AvrObject +{ + switch $(>:S) + { + case .c : AvrCc $(<) : $(>) ; + case .cpp : AvrC++ $(<) : $(>) ; + case .pde : AvrPde $(<) : $(>) ; + } +} + +rule AvrObjects +{ + for _I in $(<) + { + AvrObject $(OUT_DIR)/$(_I:B).o : $(_I) ; + } +} + +rule AvrMainFromObjects +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + MkDir $(<:D) ; + Depends all : $(<) ; + Clean clean : $(<) ; +} + +actions AvrMainFromObjects +{ + $(AVR_LD) $(LDFLAGS) -o $(<) $(>) +} + +rule AvrMain +{ + AvrMainFromObjects $(<) : $(OUT_DIR)/$(>:B).o ; + AvrObjects $(>) ; +} + +rule AvrHex +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions AvrHex +{ + $(AVR_OBJCOPY) -O ihex -R .eeprom $(>) $(<) +} + +rule AvrUpload +{ + Depends $(1) : $(2) ; + Depends $(2) : $(3) ; + NotFile $(1) ; + Always $(1) ; + Always $(2) ; + AvrUploadAction $(2) : $(3) ; +} + +actions AvrUploadAction +{ + $(AVRDUDE) $(AVRDUDE_FLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i +} + +AvrMain $(OUT).elf : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ; +AvrHex $(OUT).hex : $(OUT).elf ; + +AvrUpload p6 : /dev/tty.usbserial-A600eHIs : $(OUT).hex ; +AvrUpload p4 : /dev/tty.usbserial-A40081RP : $(OUT).hex ; +AvrUpload p9 : /dev/tty.usbserial-A9007LmI : $(OUT).hex ; + diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_sleepy/pingpair_sleepy.pde b/hardware/digistump/avr/libraries/RF24/examples/pingpair_sleepy/pingpair_sleepy.pde new file mode 100644 index 0000000..49daa69 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_sleepy/pingpair_sleepy.pde @@ -0,0 +1,288 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * Example RF Radio Ping Pair which Sleeps between Sends + * + * This is an example of how to use the RF24 class to create a battery- + * efficient system. It is just like the pingpair.pde example, but the + * ping node powers down the radio and sleeps the MCU after every + * ping/pong cycle. + * + * As with the pingpair.pde example, write this sketch to two different nodes, + * connect the role_pin to ground on one. The ping node sends the current + * time to the pong node, which responds by sending the value back. The ping + * node can then see how long the whole cycle took. + */ + +#include +#include +#include +#include "nRF24L01.h" +#include "RF24.h" +#include "printf.h" + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 9 & 10 + +RF24 radio(9,10); + +// sets the role of this unit in hardware. Connect to GND to be the 'pong' receiver +// Leave open to be the 'ping' transmitter +const int role_pin = 7; + +// +// Topology +// + +// Radio pipe addresses for the 2 nodes to communicate. +const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL }; + +// +// Role management +// +// Set up role. This sketch uses the same software for all the nodes +// in this system. Doing so greatly simplifies testing. The hardware itself specifies +// which node it is. +// +// This is done through the role_pin +// + +// The various roles supported by this sketch +typedef enum { role_ping_out = 1, role_pong_back } role_e; + +// The debug-friendly names of those roles +const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"}; + +// The role of the current running sketch +role_e role; + +// +// Sleep declarations +// + +typedef enum { wdt_16ms = 0, wdt_32ms, wdt_64ms, wdt_128ms, wdt_250ms, wdt_500ms, wdt_1s, wdt_2s, wdt_4s, wdt_8s } wdt_prescalar_e; + +void setup_watchdog(uint8_t prescalar); +void do_sleep(void); + +const short sleep_cycles_per_transmission = 4; +volatile short sleep_cycles_remaining = sleep_cycles_per_transmission; + +// +// Normal operation +// + +void setup(void) +{ + // + // Role + // + + // set up the role pin + pinMode(role_pin, INPUT); + digitalWrite(role_pin,HIGH); + delay(20); // Just to get a solid reading on the role pin + + // read the address pin, establish our role + if ( digitalRead(role_pin) ) + role = role_ping_out; + else + role = role_pong_back; + + // + // Print preamble + // + + Serial.begin(57600); + printf_begin(); + printf("\n\rRF24/examples/pingpair_sleepy/\n\r"); + printf("ROLE: %s\n\r",role_friendly_name[role]); + + // + // Prepare sleep parameters + // + + // Only the ping out role sleeps. Wake up every 4s to send a ping + if ( role == role_ping_out ) + setup_watchdog(wdt_1s); + + // + // Setup and configure rf radio + // + + radio.begin(); + + // + // Open pipes to other nodes for communication + // + + // This simple sketch opens two pipes for these two nodes to communicate + // back and forth. + // Open 'our' pipe for writing + // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading) + + if ( role == role_ping_out ) + { + radio.openWritingPipe(pipes[0]); + radio.openReadingPipe(1,pipes[1]); + } + else + { + radio.openWritingPipe(pipes[1]); + radio.openReadingPipe(1,pipes[0]); + } + + // + // Start listening + // + + radio.startListening(); + + // + // Dump the configuration of the rf unit for debugging + // + + radio.printDetails(); +} + +void loop(void) +{ + // + // Ping out role. Repeatedly send the current time + // + + if (role == role_ping_out) + { + // First, stop listening so we can talk. + radio.stopListening(); + + // Take the time, and send it. This will block until complete + unsigned long time = millis(); + printf("Now sending %lu...",time); + radio.write( &time, sizeof(unsigned long) ); + + // Now, continue listening + radio.startListening(); + + // Wait here until we get a response, or timeout (250ms) + unsigned long started_waiting_at = millis(); + bool timeout = false; + while ( ! radio.available() && ! timeout ) + if (millis() - started_waiting_at > 250 ) + timeout = true; + + // Describe the results + if ( timeout ) + { + printf("Failed, response timed out.\n\r"); + } + else + { + // Grab the response, compare, and send to debugging spew + unsigned long got_time; + radio.read( &got_time, sizeof(unsigned long) ); + + // Spew it + printf("Got response %lu, round-trip delay: %lu\n\r",got_time,millis()-got_time); + } + + // + // Shut down the system + // + + // Experiment with some delay here to see if it has an effect + delay(500); + + // Power down the radio. Note that the radio will get powered back up + // on the next write() call. + radio.powerDown(); + + // Sleep the MCU. The watchdog timer will awaken in a short while, and + // continue execution here. + while( sleep_cycles_remaining ) + do_sleep(); + + sleep_cycles_remaining = sleep_cycles_per_transmission; + } + + // + // Pong back role. Receive each packet, dump it out, and send it back + // + // This is untouched from the pingpair example. + // + + if ( role == role_pong_back ) + { + // if there is data ready + if ( radio.available() ) + { + // Dump the payloads until we've gotten everything + unsigned long got_time; + bool done = false; + while (!done) + { + // Fetch the payload, and see if this was the last one. + done = radio.read( &got_time, sizeof(unsigned long) ); + + // Spew it. Include our time, because the ping_out millis counter is unreliable + // due to it sleeping + printf("Got payload %lu @ %lu...",got_time,millis()); + } + + // First, stop listening so we can talk + radio.stopListening(); + + // Send the final one back. + radio.write( &got_time, sizeof(unsigned long) ); + printf("Sent response.\n\r"); + + // Now, resume listening so we catch the next packets. + radio.startListening(); + } + } +} + +// +// Sleep helpers +// + +// 0=16ms, 1=32ms,2=64ms,3=125ms,4=250ms,5=500ms +// 6=1 sec,7=2 sec, 8=4 sec, 9= 8sec + +void setup_watchdog(uint8_t prescalar) +{ + prescalar = min(9,prescalar); + uint8_t wdtcsr = prescalar & 7; + if ( prescalar & 8 ) + wdtcsr |= _BV(WDP3); + + MCUSR &= ~_BV(WDRF); + WDTCSR = _BV(WDCE) | _BV(WDE); + WDTCSR = _BV(WDCE) | wdtcsr | _BV(WDIE); +} + +ISR(WDT_vect) +{ + --sleep_cycles_remaining; +} + +void do_sleep(void) +{ + set_sleep_mode(SLEEP_MODE_PWR_DOWN); // sleep mode is set here + sleep_enable(); + + sleep_mode(); // System sleeps here + + sleep_disable(); // System continues execution here when watchdog timed out +} + +// vim:ai:cin:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/examples/pingpair_sleepy/printf.h b/hardware/digistump/avr/libraries/RF24/examples/pingpair_sleepy/printf.h new file mode 100644 index 0000000..b2efd56 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/pingpair_sleepy/printf.h @@ -0,0 +1,37 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file printf.h + * + * Setup necessary to direct stdout to the Arduino Serial library, which + * enables 'printf' + */ + +#ifndef __PRINTF_H__ +#define __PRINTF_H__ + +#ifdef ARDUINO + +int serial_putc( char c, FILE * ) +{ + Serial.write( c ); + + return c; +} + +void printf_begin(void) +{ + fdevopen( &serial_putc, 0 ); +} + +#else +#error This example is only for use on Arduino. +#endif // ARDUINO + +#endif // __PRINTF_H__ diff --git a/hardware/digistump/avr/libraries/RF24/examples/scanner/Jamfile b/hardware/digistump/avr/libraries/RF24/examples/scanner/Jamfile new file mode 100644 index 0000000..1bf541e --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/scanner/Jamfile @@ -0,0 +1,210 @@ +# (1) Project Information + +PROJECT_LIBS = SPI RF24 ; + +# (2) Board Information + +UPLOAD_PROTOCOL ?= stk500v1 ; +UPLOAD_SPEED ?= 57600 ; +MCU ?= atmega328p ; +F_CPU ?= 16000000 ; +CORE ?= arduino ; +VARIANT ?= standard ; +ARDUINO_VERSION ?= 100 ; + +# (3) USB Ports + +PORTS = p4 p6 p9 u0 u1 u2 ; +PORT_p6 = /dev/tty.usbserial-A600eHIs ; +PORT_p4 = /dev/tty.usbserial-A40081RP ; +PORT_p9 = /dev/tty.usbserial-A9007LmI ; +PORT_u0 = /dev/ttyUSB0 ; +PORT_u1 = /dev/ttyUSB1 ; +PORT_u2 = /dev/ttyUSB2 ; + +# (4) Location of AVR tools +# +# This configuration assumes using avr-tools that were obtained separate from the Arduino +# distribution. + +if $(OS) = MACOSX +{ + AVR_BIN = /usr/local/avrtools/bin ; + AVR_ETC = /usr/local/avrtools/etc ; + AVR_INCLUDE = /usr/local/avrtools/include ; +} +else +{ + AVR_BIN = /usr/bin ; + AVR_INCLUDE = /usr/lib/avr/include ; + AVR_ETC = /etc ; +} + +# (5) Directories where Arduino core and libraries are located + +ARDUINO_DIR ?= /opt/Arduino ; +ARDUINO_CORE = $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ; +ARDUINO_LIB = $(ARDUINO_DIR)/libraries ; +SKETCH_LIB = $(HOME)/Source/Arduino/libraries ; + +# +# -------------------------------------------------- +# Below this line usually never needs to be modified +# + +# Tool locations + +CC = $(AVR_BIN)/avr-gcc ; +C++ = $(AVR_BIN)/avr-g++ ; +LINK = $(AVR_BIN)/avr-gcc ; +OBJCOPY = $(AVR_BIN)/avr-objcopy ; +AVRDUDE = $(AVR_BIN)/avrdude ; + +# Flags + +DEFINES += F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ; +OPTIM = -Os ; +CCFLAGS = -Wall -Wextra -mmcu=$(MCU) -ffunction-sections -fdata-sections ; +C++FLAGS = $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ; +LINKFLAGS = $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ; +AVRDUDEFLAGS = -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ; + +# Search everywhere for headers + +HDRS = $(PWD) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ; + +# Output locations + +LOCATE_TARGET = $(F_CPU) ; +LOCATE_SOURCE = $(F_CPU) ; + +# +# Custom rules +# + +rule GitVersion +{ + Always $(<) ; + Depends all : $(<) ; +} + +actions GitVersion +{ + echo "const char program_version[] = \"\\" > $(<) + git log -1 --pretty=format:%h >> $(<) + echo "\";" >> $(<) +} + +GitVersion version.h ; + +rule Pde +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_SOURCE) ; + Clean clean : $(<) ; +} + +if ( $(ARDUINO_VERSION) < 100 ) +{ + ARDUINO_H = WProgram.h ; +} +else +{ + ARDUINO_H = Arduino.h ; +} + +actions Pde +{ + echo "#include <$(ARDUINO_H)>" > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule C++Pde +{ + local _CPP = $(>:B).cpp ; + Pde $(_CPP) : $(>) ; + C++ $(<) : $(_CPP) ; +} + +rule UserObject +{ + switch $(>:S) + { + case .ino : C++Pde $(<) : $(>) ; + case .pde : C++Pde $(<) : $(>) ; + } +} + +rule Objects +{ + local _i ; + + for _i in [ FGristFiles $(<) ] + { + local _b = $(_i:B)$(SUFOBJ) ; + local _o = $(_b:G=$(SOURCE_GRIST:E)) ; + Object $(_o) : $(_i) ; + Depends obj : $(_o) ; + } +} + +rule Main +{ + MainFromObjects $(<) : $(>:B)$(SUFOBJ) ; + Objects $(>) ; +} + +rule Hex +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_TARGET) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions Hex +{ + $(OBJCOPY) -O ihex -R .eeprom $(>) $(<) +} + +rule Upload +{ + Depends $(1) : $(2) ; + Depends $(2) : $(3) ; + NotFile $(1) ; + Always $(1) ; + Always $(2) ; + UploadAction $(2) : $(3) ; +} + +actions UploadAction +{ + $(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i +} + +# +# Targets +# + +# Grab everything from the core directory +CORE_MODULES = [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ; + +# Grab everything from libraries. To avoid this "grab everything" behaviour, you +# can specify specific modules to pick up in PROJECT_MODULES +LIB_MODULES = [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ; + +# Grab everything from the current dir +PROJECT_MODULES += [ GLOB $(PWD) : *.c *.cpp *.pde *.ino ] ; + +# Main output executable +MAIN = $(PWD:B).elf ; + +Main $(MAIN) : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ; +Hex $(MAIN:B).hex : $(MAIN) ; + +# Upload targets +for _p in $(PORTS) +{ + Upload $(_p) : $(PORT_$(_p)) : $(MAIN:B).hex ; +} diff --git a/hardware/digistump/avr/libraries/RF24/examples/scanner/printf.h b/hardware/digistump/avr/libraries/RF24/examples/scanner/printf.h new file mode 100644 index 0000000..66f6438 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/scanner/printf.h @@ -0,0 +1,31 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file printf.h + * + * Setup necessary to direct stdout to the Arduino Serial library, which + * enables 'printf' + */ + +#ifndef __PRINTF_H__ +#define __PRINTF_H__ + +int serial_putc( char c, FILE * ) +{ + Serial.write( c ); + + return c; +} + +void printf_begin(void) +{ + fdevopen( &serial_putc, 0 ); +} + +#endif // __PRINTF_H__ diff --git a/hardware/digistump/avr/libraries/RF24/examples/scanner/scanner.pde b/hardware/digistump/avr/libraries/RF24/examples/scanner/scanner.pde new file mode 100644 index 0000000..1a43d72 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/scanner/scanner.pde @@ -0,0 +1,124 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * Channel scanner + * + * Example to detect interference on the various channels available. + * This is a good diagnostic tool to check whether you're picking a + * good channel for your application. + * + * Inspired by cpixip. + * See http://arduino.cc/forum/index.php/topic,54795.0.html + */ + +#include +#include "nRF24L01.h" +#include "RF24.h" +#include "printf.h" + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 9 & 10 + +RF24 radio(9,10); + +// +// Channel info +// + +const uint8_t num_channels = 128; +uint8_t values[num_channels]; + +// +// Setup +// + +void setup(void) +{ + // + // Print preamble + // + + Serial.begin(57600); + printf_begin(); + printf("\n\rRF24/examples/scanner/\n\r"); + + // + // Setup and configure rf radio + // + + radio.begin(); + radio.setAutoAck(false); + + // Get into standby mode + radio.startListening(); + radio.stopListening(); + + // Print out header, high then low digit + int i = 0; + while ( i < num_channels ) + { + printf("%x",i>>4); + ++i; + } + printf("\n\r"); + i = 0; + while ( i < num_channels ) + { + printf("%x",i&0xf); + ++i; + } + printf("\n\r"); +} + +// +// Loop +// + +const int num_reps = 100; + +void loop(void) +{ + // Clear measurement values + memset(values,0,sizeof(values)); + + // Scan all channels num_reps times + int rep_counter = num_reps; + while (rep_counter--) + { + int i = num_channels; + while (i--) + { + // Select this channel + radio.setChannel(i); + + // Listen for a little + radio.startListening(); + delayMicroseconds(128); + radio.stopListening(); + + // Did we get a carrier? + if ( radio.testCarrier() ) + ++values[i]; + } + } + + // Print out channel measurements, clamped to a single hex digit + int i = 0; + while ( i < num_channels ) + { + printf("%x",min(0xf,values[i]&0xf)); + ++i; + } + printf("\n\r"); +} + +// vim:ai:cin:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/examples/starping/Jamfile b/hardware/digistump/avr/libraries/RF24/examples/starping/Jamfile new file mode 100644 index 0000000..de9b1f6 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/starping/Jamfile @@ -0,0 +1,206 @@ +PROJECT_NAME = $(PWD:B) ; +PROJECT_DIR = . ; +PROJECT_LIBS = EEPROM SPI RF24 ; + +OUT_DIR = ojam ; +F_CPU = 16000000 ; +MCU = atmega328p ; +PORTS = /dev/tty.usbserial-A600eHIs /dev/tty.usbserial-A40081RP /dev/tty.usbserial-A9007LmI ; + +UPLOAD_RATE = 57600 ; +AVRDUDE_PROTOCOL = stk500v1 ; +COM = 33 ; + +# Host-specific overrides for locations +if $(OS) = MACOSX +{ +ARDUINO_VERSION = 22 ; +OLD_DIR = /opt/arduino-0021 ; +AVR_TOOLS_PATH = $(OLD_DIR)/hardware/tools/avr/bin ; +AVRDUDECONFIG_PATH = $(OLD_DIR)/hardware/tools/avr/etc ; +ARDUINO_DIR = /opt/Arduino ; +ARDUINO_AVR = /usr/lib/avr/include ; +} + +# Where is everything? +ARDUINO_VERSION ?= 22 ; +AVR_TOOLS_PATH ?= /usr/bin ; +ARDUINO_DIR ?= /opt/arduino-00$(ARDUINO_VERSION) ; +ARDUINO_AVR ?= $(ARDUINO_DIR)/hardware/tools/avr/avr/include/avr ; +AVRDUDECONFIG_PATH ?= $(ARDUINO_DIR)/hardware/tools ; +ARDUINO_CORE = $(ARDUINO_DIR)/hardware/arduino/cores/arduino ; +ARDUINO_LIB = $(ARDUINO_DIR)/libraries ; +SKETCH_LIB = $(HOME)/Source/Arduino/libraries ; +AVR_CC = $(AVR_TOOLS_PATH)/avr-gcc ; +AVR_CXX = $(AVR_TOOLS_PATH)/avr-g++ ; +AVR_LD = $(AVR_TOOLS_PATH)/avr-gcc ; +AVR_OBJCOPY = $(AVR_TOOLS_PATH)/avr-objcopy ; +AVRDUDE = $(AVR_TOOLS_PATH)/avrdude ; + +DEFINES = F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ; +CTUNING = -ffunction-sections -fdata-sections ; +CXXTUNING = -fno-exceptions -fno-strict-aliasing ; +CFLAGS = -Os -Wall -Wextra -mmcu=$(MCU) $(CTUNING) ; +CXXFLAGS = $(CFLAGS) $(CXXTUNING) ; +LDFLAGS = -Os -lm -Wl,--gc-sections -mmcu=atmega328p ; + +# Search everywhere for headers +HDRS = $(PROJECT_DIR) $(ARDUINO_AVR) $(ARDUINO_CORE) [ GLOB $(ARDUINO_LIB) $(SKETCH_LIB) : [^.]* ] ; + +# Grab everything from the core directory +CORE_MODULES = [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ; + +# Grab everything from libraries. To avoid this "grab everything" behaviour, you +# can specify specific modules to pick up in PROJECT_MODULES +LIB_MODULES = [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp ] ; + +# In addition to explicitly-specified program modules, pick up anything from the current +# dir. +PROJECT_MODULES += [ GLOB $(PROJECT_DIR) : *.c *.cpp *.pde ] ; + +# Shortcut for the out files +OUT = $(OUT_DIR)/$(PROJECT_NAME) ; + +# AvrDude setup +AVRDUDE_FLAGS = -V -F -D -C $(AVRDUDECONFIG_PATH)/avrdude.conf -p $(MCU) -c $(AVRDUDE_PROTOCOL) -b $(UPLOAD_RATE) ; + +rule GitVersion +{ + Always $(<) ; + Depends all : $(<) ; +} + +actions GitVersion +{ + echo "const char program_version[] = \"\\" > $(<) + git log -1 --pretty=format:%h >> $(<) + echo "\";" >> $(<) +} + +GitVersion version.h ; + +rule AvrCc +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrCc +{ + $(AVR_CC) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CFLAGS) $(>) +} + +rule AvrC++ +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrC++ +{ + $(AVR_CXX) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) +} + +rule Pde +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + +} + +actions Pde +{ + echo "#include " > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule AvrPde +{ + local _CPP = $(OUT_DIR)/$(_I:B).cpp ; + Pde $(_CPP) : $(>) ; + AvrC++ $(<) : $(_CPP) ; +} + +rule AvrObject +{ + switch $(>:S) + { + case .c : AvrCc $(<) : $(>) ; + case .cpp : AvrC++ $(<) : $(>) ; + case .pde : AvrPde $(<) : $(>) ; + } +} + +rule AvrObjects +{ + for _I in $(<) + { + AvrObject $(OUT_DIR)/$(_I:B).o : $(_I) ; + } +} + +rule AvrMainFromObjects +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + MkDir $(<:D) ; + Depends all : $(<) ; + Clean clean : $(<) ; +} + +actions AvrMainFromObjects +{ + $(AVR_LD) $(LDFLAGS) -o $(<) $(>) +} + +rule AvrMain +{ + AvrMainFromObjects $(<) : $(OUT_DIR)/$(>:B).o ; + AvrObjects $(>) ; +} + +rule AvrHex +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions AvrHex +{ + $(AVR_OBJCOPY) -O ihex -R .eeprom $(>) $(<) +} + +rule AvrUpload +{ + Depends $(1) : $(2) ; + Depends $(2) : $(3) ; + NotFile $(1) ; + Always $(1) ; + Always $(2) ; + AvrUploadAction $(2) : $(3) ; +} + +actions AvrUploadAction +{ + $(AVRDUDE) $(AVRDUDE_FLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i +} + +AvrMain $(OUT).elf : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ; +AvrHex $(OUT).hex : $(OUT).elf ; + +AvrUpload p6 : /dev/tty.usbserial-A600eHIs : $(OUT).hex ; +AvrUpload p4 : /dev/tty.usbserial-A40081RP : $(OUT).hex ; +AvrUpload p9 : /dev/tty.usbserial-A9007LmI : $(OUT).hex ; + diff --git a/hardware/digistump/avr/libraries/RF24/examples/starping/printf.h b/hardware/digistump/avr/libraries/RF24/examples/starping/printf.h new file mode 100644 index 0000000..b2efd56 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/starping/printf.h @@ -0,0 +1,37 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file printf.h + * + * Setup necessary to direct stdout to the Arduino Serial library, which + * enables 'printf' + */ + +#ifndef __PRINTF_H__ +#define __PRINTF_H__ + +#ifdef ARDUINO + +int serial_putc( char c, FILE * ) +{ + Serial.write( c ); + + return c; +} + +void printf_begin(void) +{ + fdevopen( &serial_putc, 0 ); +} + +#else +#error This example is only for use on Arduino. +#endif // ARDUINO + +#endif // __PRINTF_H__ diff --git a/hardware/digistump/avr/libraries/RF24/examples/starping/starping.pde b/hardware/digistump/avr/libraries/RF24/examples/starping/starping.pde new file mode 100644 index 0000000..4813a77 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/examples/starping/starping.pde @@ -0,0 +1,293 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * Example RF Radio Ping Star Group + * + * This sketch is a more complex example of using the RF24 library for Arduino. + * Deploy this on up to six nodes. Set one as the 'pong receiver' by tying the + * role_pin low, and the others will be 'ping transmit' units. The ping units + * unit will send out the value of millis() once a second. The pong unit will + * respond back with a copy of the value. Each ping unit can get that response + * back, and determine how long the whole cycle took. + * + * This example requires a bit more complexity to determine which unit is which. + * The pong receiver is identified by having its role_pin tied to ground. + * The ping senders are further differentiated by a byte in eeprom. + */ + +#include +#include +#include "nRF24L01.h" +#include "RF24.h" +#include "printf.h" + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 9 & 10 + +RF24 radio(9,10); + +// sets the role of this unit in hardware. Connect to GND to be the 'pong' receiver +// Leave open to be the 'pong' receiver. +const int role_pin = 7; + +// +// Topology +// + +// Radio pipe addresses for the nodes to communicate. Only ping nodes need +// dedicated pipes in this topology. Each ping node has a talking pipe +// that it will ping into, and a listening pipe that it will listen for +// the pong. The pong node listens on all the ping node talking pipes +// and sends the pong back on the sending node's specific listening pipe. + +const uint64_t talking_pipes[5] = { 0xF0F0F0F0D2LL, 0xF0F0F0F0C3LL, 0xF0F0F0F0B4LL, 0xF0F0F0F0A5LL, 0xF0F0F0F096LL }; +const uint64_t listening_pipes[5] = { 0x3A3A3A3AD2LL, 0x3A3A3A3AC3LL, 0x3A3A3A3AB4LL, 0x3A3A3A3AA5LL, 0x3A3A3A3A96LL }; + +// +// Role management +// +// Set up role. This sketch uses the same software for all the nodes +// in this system. Doing so greatly simplifies testing. The hardware itself specifies +// which node it is. +// +// This is done through the role_pin +// + +// The various roles supported by this sketch +typedef enum { role_invalid = 0, role_ping_out, role_pong_back } role_e; + +// The debug-friendly names of those roles +const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"}; + +// The role of the current running sketch +role_e role; + +// +// Address management +// + +// Where in EEPROM is the address stored? +const uint8_t address_at_eeprom_location = 0; + +// What is our address (SRAM cache of the address from EEPROM) +// Note that zero is an INVALID address. The pong back unit takes address +// 1, and the rest are 2-6 +uint8_t node_address; + +void setup(void) +{ + // + // Role + // + + // set up the role pin + pinMode(role_pin, INPUT); + digitalWrite(role_pin,HIGH); + delay(20); // Just to get a solid reading on the role pin + + // read the address pin, establish our role + if ( digitalRead(role_pin) ) + role = role_ping_out; + else + role = role_pong_back; + + // + // Address + // + + if ( role == role_pong_back ) + node_address = 1; + else + { + // Read the address from EEPROM + uint8_t reading = EEPROM.read(address_at_eeprom_location); + + // If it is in a valid range for node addresses, it is our + // address. + if ( reading >= 2 && reading <= 6 ) + node_address = reading; + + // Otherwise, it is invalid, so set our address AND ROLE to 'invalid' + else + { + node_address = 0; + role = role_invalid; + } + } + + // + // Print preamble + // + + Serial.begin(57600); + printf_begin(); + printf("\n\rRF24/examples/starping/\n\r"); + printf("ROLE: %s\n\r",role_friendly_name[role]); + printf("ADDRESS: %i\n\r",node_address); + + // + // Setup and configure rf radio + // + + radio.begin(); + + // + // Open pipes to other nodes for communication + // + + // The pong node listens on all the ping node talking pipes + // and sends the pong back on the sending node's specific listening pipe. + if ( role == role_pong_back ) + { + radio.openReadingPipe(1,talking_pipes[0]); + radio.openReadingPipe(2,talking_pipes[1]); + radio.openReadingPipe(3,talking_pipes[2]); + radio.openReadingPipe(4,talking_pipes[3]); + radio.openReadingPipe(5,talking_pipes[4]); + } + + // Each ping node has a talking pipe that it will ping into, and a listening + // pipe that it will listen for the pong. + if ( role == role_ping_out ) + { + // Write on our talking pipe + radio.openWritingPipe(talking_pipes[node_address-2]); + // Listen on our listening pipe + radio.openReadingPipe(1,listening_pipes[node_address-2]); + } + + // + // Start listening + // + + radio.startListening(); + + // + // Dump the configuration of the rf unit for debugging + // + + radio.printDetails(); + + // + // Prompt the user to assign a node address if we don't have one + // + + if ( role == role_invalid ) + { + printf("\n\r*** NO NODE ADDRESS ASSIGNED *** Send 1 through 6 to assign an address\n\r"); + } +} + +void loop(void) +{ + // + // Ping out role. Repeatedly send the current time + // + + if (role == role_ping_out) + { + // First, stop listening so we can talk. + radio.stopListening(); + + // Take the time, and send it. This will block until complete + unsigned long time = millis(); + printf("Now sending %lu...",time); + radio.write( &time, sizeof(unsigned long) ); + + // Now, continue listening + radio.startListening(); + + // Wait here until we get a response, or timeout (250ms) + unsigned long started_waiting_at = millis(); + bool timeout = false; + while ( ! radio.available() && ! timeout ) + if (millis() - started_waiting_at > 250 ) + timeout = true; + + // Describe the results + if ( timeout ) + { + printf("Failed, response timed out.\n\r"); + } + else + { + // Grab the response, compare, and send to debugging spew + unsigned long got_time; + radio.read( &got_time, sizeof(unsigned long) ); + + // Spew it + printf("Got response %lu, round-trip delay: %lu\n\r",got_time,millis()-got_time); + } + + // Try again 1s later + delay(1000); + } + + // + // Pong back role. Receive each packet, dump it out, and send it back + // + + if ( role == role_pong_back ) + { + // if there is data ready + uint8_t pipe_num; + if ( radio.available(&pipe_num) ) + { + // Dump the payloads until we've gotten everything + unsigned long got_time; + bool done = false; + while (!done) + { + // Fetch the payload, and see if this was the last one. + done = radio.read( &got_time, sizeof(unsigned long) ); + + // Spew it + printf("Got payload %lu from node %i...",got_time,pipe_num+1); + } + + // First, stop listening so we can talk + radio.stopListening(); + + // Open the correct pipe for writing + radio.openWritingPipe(listening_pipes[pipe_num-1]); + + // Retain the low 2 bytes to identify the pipe for the spew + uint16_t pipe_id = listening_pipes[pipe_num-1] & 0xffff; + + // Send the final one back. + radio.write( &got_time, sizeof(unsigned long) ); + printf("Sent response to %04x.\n\r",pipe_id); + + // Now, resume listening so we catch the next packets. + radio.startListening(); + } + } + + // + // Listen for serial input, which is how we set the address + // + if (Serial.available()) + { + // If the character on serial input is in a valid range... + char c = Serial.read(); + if ( c >= '1' && c <= '6' ) + { + // It is our address + EEPROM.write(address_at_eeprom_location,c-'0'); + + // And we are done right now (no easy way to soft reset) + printf("\n\rManually reset address to: %c\n\rPress RESET to continue!",c); + while(1) ; + } + } +} +// vim:ai:ci sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/keywords.txt b/hardware/digistump/avr/libraries/RF24/keywords.txt new file mode 100644 index 0000000..d0bd557 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/keywords.txt @@ -0,0 +1,13 @@ + RF24 KEYWORD1 + begin KEYWORD2 + setChannel KEYWORD2 + setPayloadSize KEYWORD2 + getPayloadSize KEYWORD2 + print_details KEYWORD2 + startListening KEYWORD2 + stopListening KEYWORD2 + write KEYWORD2 + available KEYWORD2 + read KEYWORD2 + openWritingPipe KEYWORD2 + openReadingPipe KEYWORD2 \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/RF24/nRF24L01.h b/hardware/digistump/avr/libraries/RF24/nRF24L01.h new file mode 100644 index 0000000..2012ce6 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/nRF24L01.h @@ -0,0 +1,125 @@ +/* + Copyright (c) 2007 Stefan Engelke + + Permission is hereby granted, free of charge, to any person + obtaining a copy of this software and associated documentation + files (the "Software"), to deal in the Software without + restriction, including without limitation the rights to use, copy, + modify, merge, publish, distribute, sublicense, and/or sell copies + of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*/ + +/* Memory Map */ +#define CONFIG 0x00 +#define EN_AA 0x01 +#define EN_RXADDR 0x02 +#define SETUP_AW 0x03 +#define SETUP_RETR 0x04 +#define RF_CH 0x05 +#define RF_SETUP 0x06 +#define STATUS 0x07 +#define OBSERVE_TX 0x08 +#define CD 0x09 +#define RX_ADDR_P0 0x0A +#define RX_ADDR_P1 0x0B +#define RX_ADDR_P2 0x0C +#define RX_ADDR_P3 0x0D +#define RX_ADDR_P4 0x0E +#define RX_ADDR_P5 0x0F +#define TX_ADDR 0x10 +#define RX_PW_P0 0x11 +#define RX_PW_P1 0x12 +#define RX_PW_P2 0x13 +#define RX_PW_P3 0x14 +#define RX_PW_P4 0x15 +#define RX_PW_P5 0x16 +#define FIFO_STATUS 0x17 +#define DYNPD 0x1C +#define FEATURE 0x1D + +/* Bit Mnemonics */ +#define MASK_RX_DR 6 +#define MASK_TX_DS 5 +#define MASK_MAX_RT 4 +#define EN_CRC 3 +#define CRCO 2 +#define PWR_UP 1 +#define PRIM_RX 0 +#define ENAA_P5 5 +#define ENAA_P4 4 +#define ENAA_P3 3 +#define ENAA_P2 2 +#define ENAA_P1 1 +#define ENAA_P0 0 +#define ERX_P5 5 +#define ERX_P4 4 +#define ERX_P3 3 +#define ERX_P2 2 +#define ERX_P1 1 +#define ERX_P0 0 +#define AW 0 +#define ARD 4 +#define ARC 0 +#define PLL_LOCK 4 +#define RF_DR 3 +#define RF_PWR 6 +#define RX_DR 6 +#define TX_DS 5 +#define MAX_RT 4 +#define RX_P_NO 1 +#define TX_FULL 0 +#define PLOS_CNT 4 +#define ARC_CNT 0 +#define TX_REUSE 6 +#define FIFO_FULL 5 +#define TX_EMPTY 4 +#define RX_FULL 1 +#define RX_EMPTY 0 +#define DPL_P5 5 +#define DPL_P4 4 +#define DPL_P3 3 +#define DPL_P2 2 +#define DPL_P1 1 +#define DPL_P0 0 +#define EN_DPL 2 +#define EN_ACK_PAY 1 +#define EN_DYN_ACK 0 + +/* Instruction Mnemonics */ +#define R_REGISTER 0x00 +#define W_REGISTER 0x20 +#define REGISTER_MASK 0x1F +#define ACTIVATE 0x50 +#define R_RX_PL_WID 0x60 +#define R_RX_PAYLOAD 0x61 +#define W_TX_PAYLOAD 0xA0 +#define W_ACK_PAYLOAD 0xA8 +#define FLUSH_TX 0xE1 +#define FLUSH_RX 0xE2 +#define REUSE_TX_PL 0xE3 +#define NOP 0xFF + +/* Non-P omissions */ +#define LNA_HCURR 0 + +/* P model memory Map */ +#define RPD 0x09 + +/* P model bit Mnemonics */ +#define RF_DR_LOW 5 +#define RF_DR_HIGH 3 +#define RF_PWR_LOW 1 +#define RF_PWR_HIGH 2 diff --git a/hardware/digistump/avr/libraries/RF24/tests/README b/hardware/digistump/avr/libraries/RF24/tests/README new file mode 100644 index 0000000..43ceaf5 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/README @@ -0,0 +1,7 @@ +The sketches in this directory are intended to be checkin tests. +No code should be pushed to github without these tests passing. + +See "runtests.sh" script inside each sketch dir. This script is fully compatible with +git bisest. + +Note that this requires python and py-serial diff --git a/hardware/digistump/avr/libraries/RF24/tests/native/Jamfile b/hardware/digistump/avr/libraries/RF24/tests/native/Jamfile new file mode 100644 index 0000000..10d0336 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/native/Jamfile @@ -0,0 +1,300 @@ +PROJECT_NAME = $(PWD:B) ; +PROJECT_DIR = . ; +PROJECT_LIBS = RF24 ; + +OUT_DIR = ojam ; +F_CPU = 16000000 ; +MCU = atmega328p ; +PORTS = /dev/tty.usbserial-A600eHIs /dev/tty.usbserial-A40081RP /dev/tty.usbserial-A9007LmI ; + +UPLOAD_RATE = 57600 ; +AVRDUDE_PROTOCOL = stk500v1 ; +COM = 33 ; + +# Host-specific overrides for locations +if $(OS) = MACOSX +{ +ARDUINO_VERSION = 22 ; +OLD_DIR = /opt/arduino-0021 ; +AVR_TOOLS_PATH = $(OLD_DIR)/hardware/tools/avr/bin ; +AVRDUDECONFIG_PATH = $(OLD_DIR)/hardware/tools/avr/etc ; +ARDUINO_DIR = /opt/Arduino ; +ARDUINO_AVR = /usr/lib/avr/include ; +} + +# Where is everything? +ARDUINO_VERSION ?= 22 ; +SKETCH_DIR = $(HOME)/Source/Arduino ; +AVR_TOOLS_PATH ?= /usr/bin ; +ARDUINO_DIR ?= /opt/arduino-00$(ARDUINO_VERSION) ; +ARDUINO_AVR ?= $(ARDUINO_DIR)/hardware/tools/avr/avr/include/avr ; +AVRDUDECONFIG_PATH ?= $(ARDUINO_DIR)/hardware/tools ; +ARDUINO_CORE = $(ARDUINO_DIR)/hardware/arduino/cores/arduino ; +ARDUINO_LIB = $(ARDUINO_DIR)/libraries ; +SKETCH_LIB = $(SKETCH_DIR)/libraries ; +AVR_AS = $(AVR_TOOLS_PATH)/avr-as ; +AVR_CC = $(AVR_TOOLS_PATH)/avr-gcc ; +AVR_CXX = $(AVR_TOOLS_PATH)/avr-g++ ; +AVR_LD = $(AVR_TOOLS_PATH)/avr-gcc ; +AVR_OBJCOPY = $(AVR_TOOLS_PATH)/avr-objcopy ; +AVRDUDE = $(AVR_TOOLS_PATH)/avrdude ; + +DEFINES = F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H HAL=1 ; +CTUNING = -ffunction-sections -fdata-sections ; +CXXTUNING = -fno-exceptions -fno-strict-aliasing ; +ASFLAGS = -mmcu=$(MCU) ; +CFLAGS = -Os -Wall -Wextra $(ASFLAGS) $(CTUNING) ; +CXXFLAGS = $(CFLAGS) $(CXXTUNING) ; +LDFLAGS = -Os -lm -Wl,--gc-sections -mmcu=atmega328p ; + +# Search everywhere for headers +HDRS = $(PROJECT_DIR) $(ARDUINO_AVR) $(ARDUINO_CORE) [ GLOB $(ARDUINO_LIB) $(SKETCH_LIB) : [^.]* ] ; +HDRS += [ GLOB $(HDRS) : utility ] ; + +# Grab everything from the core directory +CORE_MODULES = [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ; + +# Grab everything from libraries. To avoid this "grab everything" behaviour, you +# can specify specific modules to pick up in PROJECT_MODULES +LIB_MODULES = [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ; + +# In addition to explicitly-specified program modules, pick up anything from the current +# dir. +PROJECT_MODULES += [ GLOB $(PROJECT_DIR) : *.c *.cpp *.pde ] ; + +# Shortcut for the out files +OUT = $(OUT_DIR)/$(PROJECT_NAME) ; + +# AvrDude setup +AVRDUDE_FLAGS = -V -F -D -C $(AVRDUDECONFIG_PATH)/avrdude.conf -p $(MCU) -c $(AVRDUDE_PROTOCOL) -b $(UPLOAD_RATE) ; + +rule GitVersion +{ + Always $(<) ; + Depends all : $(<) ; +} + +actions GitVersion +{ + echo "const char program_version[] = \"\\" > $(<) + git log -1 --pretty=format:%h >> $(<) + echo "\";" >> $(<) +} + +# GitVersion version.h ; + +rule AvrAsm +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrAsm +{ + $(AVR_AS) $(ASFLAGS) -o $(<) $(>) +} + +rule AvrCc +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrCc +{ + $(AVR_CC) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CFLAGS) $(>) +} + +rule AvrC++ +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrC++ +{ + $(AVR_CXX) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) +} + +rule AvrAsmFromC++ +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; + + CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ; + CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ; +} + +actions AvrAsmFromC++ +{ + $(AVR_CXX) -S -fverbose-asm -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) +} + +rule Pde +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Clean clean : $(<) ; +} + +actions Pde +{ + echo "#include " > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule AvrPde +{ + local _CPP = $(OUT_DIR)/$(_I:B).cpp ; + Pde $(_CPP) : $(>) ; + AvrC++ $(<) : $(_CPP) ; +} + +rule AvrObject +{ + switch $(>:S) + { + case .S : AvrAsm $(<) : $(>) ; + case .c : AvrCc $(<) : $(>) ; + case .cpp : AvrC++ $(<) : $(>) ; + case .pde : AvrPde $(<) : $(>) ; + } +} + +rule AvrObjects +{ + for _I in $(<) + { + AvrObject $(OUT_DIR)/$(_I:B).o : $(_I) ; + } +} + +rule AvrMainFromObjects +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + MkDir $(<:D) ; + Depends all : $(<) ; + Clean clean : $(<) ; +} + +actions AvrMainFromObjects +{ + $(AVR_LD) $(LDFLAGS) -o $(<) $(>) +} + +rule AvrMain +{ + AvrMainFromObjects $(<) : $(OUT_DIR)/$(>:B).o ; + AvrObjects $(>) ; +} + +rule AvrHex +{ + Depends $(<) : $(>) ; + Depends $(<) : $(<:D) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions AvrHex +{ + $(AVR_OBJCOPY) -O ihex -R .eeprom $(>) $(<) +} + +rule AvrUpload +{ + Depends $(1) : $(2) ; + Depends $(2) : $(3) ; + NotFile $(1) ; + Always $(1) ; + Always $(2) ; + AvrUploadAction $(2) : $(3) ; +} + +actions AvrUploadAction +{ + $(AVRDUDE) $(AVRDUDE_FLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i +} + +AvrMain $(OUT).elf : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) +AvrHex $(OUT).hex : $(OUT).elf ; + +AvrUpload p6 : /dev/tty.usbserial-A600eHIs : $(OUT).hex ; +AvrUpload p4 : /dev/tty.usbserial-A40081RP : $(OUT).hex ; +AvrUpload p9 : /dev/tty.usbserial-A9007LmI : $(OUT).hex ; + +# +# Native +# + +OUT_DIR_NATIVE = out_native ; +OUT_NATIVE = $(OUT_DIR_NATIVE)/$(PROJECT_NAME) ; +NATIVE_CORE = $(SKETCH_DIR)/hardware/native ; +HDRS = $(NATIVE_CORE) $(HDRS) ; +NATIVE_CORE_MODULES = [ GLOB $(NATIVE_CORE) : *.c *.cpp ] ; +NATIVE_MODULES = ; +DEFINES += NATIVE ; + +rule NativePde +{ + local _CPP = $(OUT_DIR_NATIVE)/$(_I:B).cpp ; + Pde $(_CPP) : $(>) ; + C++ $(<) : $(_CPP) ; +} + +rule UserObject +{ + switch $(>) + { + case *.pde : NativePde $(<) : $(>) ; + } +} + +rule Objects +{ + for _I in $(<) + { + local _O = $(OUT_DIR_NATIVE)/$(_I:B).o ; + Object $(_O) : $(_I) ; + } +} + +rule Main +{ + MainFromObjects $(<) : $(OUT_DIR_NATIVE)/$(>:B).o ; + Objects $(>) ; +} + +actions C++ +{ + c++ -c -o $(<) $(CCHDRS) $(CCDEFS) $(>) +} + +actions Link +{ + c++ -o $(<) $(>) +} + + + +MkDir $(OUT_DIR_NATIVE) ; +Depends $(OUT_NATIVE) : $(OUT_DIR_NATIVE) ; +Main $(OUT_NATIVE) : $(NATIVE_CORE_MODULES) $(NATIVE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ; + +Depends native : $(OUT_NATIVE) ; + diff --git a/hardware/digistump/avr/libraries/RF24/tests/native/pingpair_irq.pde b/hardware/digistump/avr/libraries/RF24/tests/native/pingpair_irq.pde new file mode 100644 index 0000000..99c2cdf --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/native/pingpair_irq.pde @@ -0,0 +1,223 @@ +/* + Copyright (C) 2011 James Coliz, Jr. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * Interrupt-driven test for native target + * + * This example is the friendliest for the native target because it doesn't do + * any polling. Made a slight change to call done() at the end of setup. + */ + +#include +#include "nRF24L01.h" +#include "RF24.h" +#include "printf.h" + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 8 & 9 + +RF24 radio(8,9); + +// sets the role of this unit in hardware. Connect to GND to be the 'pong' receiver +// Leave open to be the 'ping' transmitter +const short role_pin = 7; + +// +// Topology +// + +// Single radio pipe address for the 2 nodes to communicate. +const uint64_t pipe = 0xE8E8F0F0E1LL; + +// +// Role management +// +// Set up role. This sketch uses the same software for all the nodes in this +// system. Doing so greatly simplifies testing. The hardware itself specifies +// which node it is. +// +// This is done through the role_pin +// + +// The various roles supported by this sketch +typedef enum { role_sender = 1, role_receiver } role_e; + +// The debug-friendly names of those roles +const char* role_friendly_name[] = { "invalid", "Sender", "Receiver"}; + +// The role of the current running sketch +role_e role; + +// Interrupt handler, check the radio because we got an IRQ +void check_radio(void); + +void setup(void) +{ + // + // Role + // + + // set up the role pin + pinMode(role_pin, INPUT); + digitalWrite(role_pin,HIGH); + delay(20); // Just to get a solid reading on the role pin + + // read the address pin, establish our role + if ( digitalRead(role_pin) ) + role = role_sender; + else + role = role_receiver; + + // + // Print preamble + // + + Serial.begin(57600); + printf_begin(); + printf("\n\rRF24/examples/pingpair_irq/\n\r"); + printf("ROLE: %s\n\r",role_friendly_name[role]); + + // + // Setup and configure rf radio + // + + radio.begin(); + + // We will be using the Ack Payload feature, so please enable it + radio.enableAckPayload(); + + // + // Open pipes to other nodes for communication + // + + // This simple sketch opens a single pipe for these two nodes to communicate + // back and forth. One listens on it, the other talks to it. + + if ( role == role_sender ) + { + radio.openWritingPipe(pipe); + } + else + { + radio.openReadingPipe(1,pipe); + } + + // + // Start listening + // + + if ( role == role_receiver ) + radio.startListening(); + + // + // Dump the configuration of the rf unit for debugging + // + + radio.printDetails(); + + // + // Attach interrupt handler to interrupt #0 (using pin 2) + // on BOTH the sender and receiver + // + + attachInterrupt(0, check_radio, FALLING); + + // + // On the native target, this is as far as we get + // +#if NATIVE + done(); +#endif +} + +static uint32_t message_count = 0; + +void loop(void) +{ + // + // Sender role. Repeatedly send the current time + // + + if (role == role_sender) + { + // Take the time, and send it. + unsigned long time = millis(); + printf("Now sending %lu\n\r",time); + radio.startWrite( &time, sizeof(unsigned long) ); + + // Try again soon + delay(2000); + } + + // + // Receiver role: Does nothing! All the work is in IRQ + // + +} + +void check_radio(void) +{ + // What happened? + bool tx,fail,rx; + radio.whatHappened(tx,fail,rx); + + // Have we successfully transmitted? + if ( tx ) + { + if ( role == role_sender ) + printf("Send:OK\n\r"); + + if ( role == role_receiver ) + printf("Ack Payload:Sent\n\r"); + } + + // Have we failed to transmit? + if ( fail ) + { + if ( role == role_sender ) + printf("Send:Failed\n\r"); + + if ( role == role_receiver ) + printf("Ack Payload:Failed\n\r"); + } + + // Transmitter can power down for now, because + // the transmission is done. + if ( ( tx || fail ) && ( role == role_sender ) ) + radio.powerDown(); + + // Did we receive a message? + if ( rx ) + { + // If we're the sender, we've received an ack payload + if ( role == role_sender ) + { + radio.read(&message_count,sizeof(message_count)); + printf("Ack:%lu\n\r",(unsigned long)message_count); + } + + // If we're the receiver, we've received a time message + if ( role == role_receiver ) + { + // Get this payload and dump it + static unsigned long got_time; + radio.read( &got_time, sizeof(got_time) ); + printf("Got payload %lu\n\r",got_time); + + // Add an ack packet for the next time around. This is a simple + // packet counter + radio.writeAckPayload( 1, &message_count, sizeof(message_count) ); + ++message_count; + } + } +} + +// vim:ai:cin:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/tests/native/printf.h b/hardware/digistump/avr/libraries/RF24/tests/native/printf.h new file mode 100644 index 0000000..df6c46a --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/native/printf.h @@ -0,0 +1,33 @@ +/* + Copyright (C) 2011 James Coliz, Jr. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file printf.h + * + * Setup necessary to direct stdout to the Arduino Serial library, which + * enables 'printf' + */ + +#ifndef __PRINTF_H__ +#define __PRINTF_H__ + +#include "WProgram.h" + +int serial_putc( char c, FILE * ) +{ + Serial.write( c ); + + return c; +} + +void printf_begin(void) +{ + fdevopen( &serial_putc, 0 ); +} + +#endif // __PRINTF_H__ diff --git a/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/Jamfile b/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/Jamfile new file mode 100644 index 0000000..18244ec --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/Jamfile @@ -0,0 +1,219 @@ +# (1) Project Information + +PROJECT_LIBS = SPI RF24 ; +PROJECT_DIRS = $(PWD) ; + +# (2) Board Information + +UPLOAD_PROTOCOL ?= arduino ; +UPLOAD_SPEED ?= 115200 ; +MCU ?= atmega328p ; +F_CPU ?= 16000000 ; +CORE ?= arduino ; +VARIANT ?= standard ; +ARDUINO_VERSION ?= 100 ; + +# (3) USB Ports + +PORTS = p4 p6 p9 u0 u1 u2 ; +PORT_p6 = /dev/tty.usbserial-A600eHIs ; +PORT_p4 = /dev/tty.usbserial-A40081RP ; +PORT_p9 = /dev/tty.usbserial-A9007LmI ; +PORT_u0 = /dev/ttyUSB0 ; +PORT_u1 = /dev/ttyUSB1 ; +PORT_u2 = /dev/ttyUSB2 ; + +# (4) Location of AVR tools +# +# This configuration assumes using avr-tools that were obtained separate from the Arduino +# distribution. + +if $(OS) = MACOSX +{ + AVR_BIN ?= /usr/local/avrtools/bin ; + AVR_ETC = /usr/local/avrtools/etc ; + AVR_INCLUDE = /usr/local/avrtools/include ; +} +else +{ + AVR_BIN ?= /usr/bin ; + AVR_INCLUDE = /usr/lib/avr/include ; + AVR_ETC = /etc ; +} + +# (5) Directories where Arduino core and libraries are located + +ARDUINO_DIR ?= /opt/Arduino ; +ARDUINO_CORE = $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ; +ARDUINO_LIB = $(ARDUINO_DIR)/libraries ; +SKETCH_LIB = $(HOME)/Source/Arduino/libraries ; + +# +# -------------------------------------------------- +# Below this line usually never needs to be modified +# + +# Tool locations + +CC = $(AVR_BIN)/avr-gcc ; +C++ = $(AVR_BIN)/avr-g++ ; +LINK = $(AVR_BIN)/avr-gcc ; +AR = $(AVR_BIN)/avr-ar rcs ; +RANLIB = ; +OBJCOPY = $(AVR_BIN)/avr-objcopy ; +AVRDUDE ?= $(AVR_BIN)/avrdude ; + +# Flags + +DEFINES += F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ; +OPTIM = -Os ; +CCFLAGS = -Wall -Wextra -Wno-strict-aliasing -mmcu=$(MCU) -ffunction-sections -fdata-sections ; +C++FLAGS = $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ; +LINKFLAGS = $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ; +AVRDUDEFLAGS = -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ; + +# Search everywhere for headers + +HDRS = $(PROJECT_DIRS) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ; + +# Output locations + +LOCATE_TARGET = $(F_CPU) ; +LOCATE_SOURCE = $(F_CPU) ; + +# +# Custom rules +# + +rule GitVersion +{ + Always $(<) ; + Depends all : $(<) ; +} + +actions GitVersion +{ + echo "const char program_version[] = \"\\" > $(<) + git log -1 --pretty=format:%h >> $(<) + echo "\";" >> $(<) +} + +GitVersion version.h ; + +rule Pde +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_SOURCE) ; + Clean clean : $(<) ; +} + +if ( $(ARDUINO_VERSION) < 100 ) +{ + ARDUINO_H = WProgram.h ; +} +else +{ + ARDUINO_H = Arduino.h ; +} + +actions Pde +{ + echo "#include <$(ARDUINO_H)>" > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule C++Pde +{ + local _CPP = $(>:B).cpp ; + Pde $(_CPP) : $(>) ; + C++ $(<) : $(_CPP) ; +} + +rule UserObject +{ + switch $(>:S) + { + case .ino : C++Pde $(<) : $(>) ; + case .pde : C++Pde $(<) : $(>) ; + } +} + +rule Objects +{ + local _i ; + + for _i in [ FGristFiles $(<) ] + { + local _b = $(_i:B)$(SUFOBJ) ; + local _o = $(_b:G=$(SOURCE_GRIST:E)) ; + Object $(_o) : $(_i) ; + Depends obj : $(_o) ; + } +} + +rule Library +{ + LibraryFromObjects $(<) : $(>:B)$(SUFOBJ) ; + Objects $(>) ; +} + +rule Main +{ + MainFromObjects $(<) : $(>:B)$(SUFOBJ) ; + Objects $(>) ; +} + +rule Hex +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_TARGET) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions Hex +{ + $(OBJCOPY) -O ihex -R .eeprom $(>) $(<) +} + +rule Upload +{ + Depends $(1) : $(2) ; + Depends $(2) : $(3) ; + NotFile $(1) ; + Always $(1) ; + Always $(2) ; + UploadAction $(2) : $(3) ; +} + +actions UploadAction +{ + $(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i +} + +rule Arduino +{ + LINKFLAGS on $(<) = $(LINKFLAGS) -Wl,-Map=$(LOCATE_TARGET)/$(<:B).map ; + Main $(<) : $(>) ; + LinkLibraries $(<) : core libs ; + Hex $(<:B).hex : $(<) ; + for _p in $(PORTS) + { + Upload $(_p) : $(PORT_$(_p)) : $(<:B).hex ; + } +} + +# +# Targets +# + +# Grab everything from the core directory +Library core : [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ; + +# Grab everything from libraries. To avoid this "grab everything" behaviour, you +# can specify specific modules to pick up in PROJECT_MODULES +Library libs : [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ; + +# Main output executable +Arduino $(PWD:B).elf : $(PROJECT_MODULES) [ GLOB $(PROJECT_DIRS) : *.c *.cpp *.pde *.ino ] ; diff --git a/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/pingpair_blocking.pde b/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/pingpair_blocking.pde new file mode 100644 index 0000000..1501d37 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/pingpair_blocking.pde @@ -0,0 +1,273 @@ +/* + Copyright (C) 2011 James Coliz, Jr. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +#include +#include "nRF24L01.h" +#include "RF24.h" +#include "printf.h" + +// +// Test version of RF24, exposes some protected interface +// + +class RF24Test: public RF24 +{ +public: RF24Test(int a, int b): RF24(a,b) {} +}; + + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 8 & 9 + +RF24Test radio(8,9); + +// sets the role of this unit in hardware. Connect to GND to be the 'pong' receiver +// Leave open to be the 'ping' transmitter +const int role_pin = 7; + +// +// Topology +// + +// Radio pipe addresses for the 2 nodes to communicate. +const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL }; + +// +// Role management +// +// Set up role. This sketch uses the same software for all the nodes +// in this system. Doing so greatly simplifies testing. The hardware itself specifies +// which node it is. +// +// This is done through the role_pin +// + +// The various roles supported by this sketch +typedef enum { role_ping_out = 1, role_pong_back } role_e; + +// The debug-friendly names of those roles +const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"}; + +// The role of the current running sketch +role_e role; + +// +// Test state +// + +bool done; //*< Are we done with the test? */ +bool passed; //*< Have we passed the test? */ +bool notified; //*< Have we notified the user we're done? */ +const int num_needed = 10; //*< How many success/failures until we're done? */ +int receives_remaining = num_needed; //*< How many ack packets until we declare victory? */ +int failures_remaining = num_needed; //*< How many more failed sends until we declare failure? */ +const int interval = 100; //*< ms to wait between sends */ + +char configuration = '1'; //*< Configuration key, one char sent in by the test framework to tell us how to configure, this is the default */ + +void one_ok(void) +{ + // Have we received enough yet? + if ( ! --receives_remaining ) + { + done = true; + passed = true; + } +} + +void one_failed(void) +{ + // Have we failed enough yet? + if ( ! --failures_remaining ) + { + done = true; + passed = false; + } +} + +void setup(void) +{ + // + // Role + // + + // set up the role pin + pinMode(role_pin, INPUT); + digitalWrite(role_pin,HIGH); + delay(20); // Just to get a solid reading on the role pin + + // read the address pin, establish our role + if ( digitalRead(role_pin) ) + role = role_ping_out; + else + role = role_pong_back; + + // + // Print preamble + // + + Serial.begin(57600); + printf_begin(); + printf("\n\rRF24/tests/pingpair_blocking/\n\r"); + printf("ROLE: %s\n\r",role_friendly_name[role]); + + // + // get test config + // + + printf("+READY press any key to start\n\r\n\r"); + + while (! Serial.available() ) {} + configuration = Serial.read(); + printf("Configuration\t = %c\n\r",configuration); + + // + // Setup and configure rf radio + // + + radio.begin(); + + // + // Open pipes to other nodes for communication + // + + // This simple sketch opens two pipes for these two nodes to communicate + // back and forth. + // Open 'our' pipe for writing + // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading) + + if ( role == role_ping_out ) + { + radio.openWritingPipe(pipes[0]); + radio.openReadingPipe(1,pipes[1]); + } + else + { + radio.openWritingPipe(pipes[1]); + radio.openReadingPipe(1,pipes[0]); + } + + // + // Start listening + // + + radio.startListening(); + + // + // Dump the configuration of the rf unit for debugging + // + + radio.printDetails(); + + if ( role == role_pong_back ) + printf("\n\r+OK "); +} + +void loop(void) +{ + // + // Ping out role. Repeatedly send the current time + // + + if (role == role_ping_out) + { + // First, stop listening so we can talk. + radio.stopListening(); + + // Take the time, and send it. This will block until complete + unsigned long time = millis(); + printf("Now sending %lu...",time); + radio.write( &time, sizeof(unsigned long) ); + + // Now, continue listening + radio.startListening(); + + // Wait here until we get a response, or timeout (250ms) + unsigned long started_waiting_at = millis(); + bool timeout = false; + while ( ! radio.available() && ! timeout ) + if (millis() - started_waiting_at > 200 ) + timeout = true; + + // Describe the results + if ( timeout ) + { + printf("Failed, response timed out.\n\r"); + one_failed(); + } + else + { + // Grab the response, compare, and send to debugging spew + unsigned long got_time; + radio.read( &got_time, sizeof(unsigned long) ); + + // Spew it + printf("Got response %lu, round-trip delay: %lu\n\r",got_time,millis()-got_time); + one_ok(); + } + + // Try again later + delay(250); + } + + // + // Pong back role. Receive each packet, dump it out, and send it back + // + + if ( role == role_pong_back ) + { + // if there is data ready + if ( radio.available() ) + { + // Dump the payloads until we've gotten everything + unsigned long got_time; + bool done = false; + while (!done) + { + // Fetch the payload, and see if this was the last one. + done = radio.read( &got_time, sizeof(unsigned long) ); + + // Spew it + printf("Got payload %lu...",got_time); + + // Delay just a little bit to let the other unit + // make the transition to receiver + delay(20); + } + + // First, stop listening so we can talk + radio.stopListening(); + + // Send the final one back. + radio.write( &got_time, sizeof(unsigned long) ); + printf("Sent response.\n\r"); + + // Now, resume listening so we catch the next packets. + radio.startListening(); + + } + } + + // + // Stop the test if we're done and report results + // + if ( done && ! notified ) + { + notified = true; + + printf("\n\r+OK "); + if ( passed ) + printf("PASS\n\r\n\r"); + else + printf("FAIL\n\r\n\r"); + } +} +// vim:cin:ai:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/printf.h b/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/printf.h new file mode 100644 index 0000000..b2efd56 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/printf.h @@ -0,0 +1,37 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file printf.h + * + * Setup necessary to direct stdout to the Arduino Serial library, which + * enables 'printf' + */ + +#ifndef __PRINTF_H__ +#define __PRINTF_H__ + +#ifdef ARDUINO + +int serial_putc( char c, FILE * ) +{ + Serial.write( c ); + + return c; +} + +void printf_begin(void) +{ + fdevopen( &serial_putc, 0 ); +} + +#else +#error This example is only for use on Arduino. +#endif // ARDUINO + +#endif // __PRINTF_H__ diff --git a/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/runtest.py b/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/runtest.py new file mode 100644 index 0000000..0772f95 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/runtest.py @@ -0,0 +1,25 @@ +#!/usr/bin/python + +import sys,serial + +def read_until(token): + while 1: + line = ser.readline(None) + sys.stdout.write(line) + + if (line.startswith(token)): + break + return line + + +ser = serial.Serial(sys.argv[1], 57600, timeout=5, dsrdtr=False, rtscts=False) + +read_until("+READY") +ser.write(sys.argv[2]) + +line = read_until("+OK") +ser.close() +if (line.find("PASS") != -1): + sys.exit(0) +else: + sys.exit(1) diff --git a/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/runtests.sh b/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/runtests.sh new file mode 100644 index 0000000..e106448 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/runtests.sh @@ -0,0 +1,5 @@ +#!/bin/sh + +# Connect u0 to receiver, u1 to sender + +jam u0 u1 && expect test.ex diff --git a/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/test.ex b/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/test.ex new file mode 100644 index 0000000..ea992ad --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/pingpair_blocking/test.ex @@ -0,0 +1,11 @@ +#/usr/bin/expect + +set timeout 100 +spawn picocom -b 57600 /dev/ttyUSB0 +expect "+READY" +send "1" +expect "+OK" +spawn picocom -b 57600 /dev/ttyUSB1 +expect "+READY" +send "1" +expect "+OK" diff --git a/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/Jamfile b/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/Jamfile new file mode 100644 index 0000000..18244ec --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/Jamfile @@ -0,0 +1,219 @@ +# (1) Project Information + +PROJECT_LIBS = SPI RF24 ; +PROJECT_DIRS = $(PWD) ; + +# (2) Board Information + +UPLOAD_PROTOCOL ?= arduino ; +UPLOAD_SPEED ?= 115200 ; +MCU ?= atmega328p ; +F_CPU ?= 16000000 ; +CORE ?= arduino ; +VARIANT ?= standard ; +ARDUINO_VERSION ?= 100 ; + +# (3) USB Ports + +PORTS = p4 p6 p9 u0 u1 u2 ; +PORT_p6 = /dev/tty.usbserial-A600eHIs ; +PORT_p4 = /dev/tty.usbserial-A40081RP ; +PORT_p9 = /dev/tty.usbserial-A9007LmI ; +PORT_u0 = /dev/ttyUSB0 ; +PORT_u1 = /dev/ttyUSB1 ; +PORT_u2 = /dev/ttyUSB2 ; + +# (4) Location of AVR tools +# +# This configuration assumes using avr-tools that were obtained separate from the Arduino +# distribution. + +if $(OS) = MACOSX +{ + AVR_BIN ?= /usr/local/avrtools/bin ; + AVR_ETC = /usr/local/avrtools/etc ; + AVR_INCLUDE = /usr/local/avrtools/include ; +} +else +{ + AVR_BIN ?= /usr/bin ; + AVR_INCLUDE = /usr/lib/avr/include ; + AVR_ETC = /etc ; +} + +# (5) Directories where Arduino core and libraries are located + +ARDUINO_DIR ?= /opt/Arduino ; +ARDUINO_CORE = $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ; +ARDUINO_LIB = $(ARDUINO_DIR)/libraries ; +SKETCH_LIB = $(HOME)/Source/Arduino/libraries ; + +# +# -------------------------------------------------- +# Below this line usually never needs to be modified +# + +# Tool locations + +CC = $(AVR_BIN)/avr-gcc ; +C++ = $(AVR_BIN)/avr-g++ ; +LINK = $(AVR_BIN)/avr-gcc ; +AR = $(AVR_BIN)/avr-ar rcs ; +RANLIB = ; +OBJCOPY = $(AVR_BIN)/avr-objcopy ; +AVRDUDE ?= $(AVR_BIN)/avrdude ; + +# Flags + +DEFINES += F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ; +OPTIM = -Os ; +CCFLAGS = -Wall -Wextra -Wno-strict-aliasing -mmcu=$(MCU) -ffunction-sections -fdata-sections ; +C++FLAGS = $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ; +LINKFLAGS = $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ; +AVRDUDEFLAGS = -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ; + +# Search everywhere for headers + +HDRS = $(PROJECT_DIRS) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ; + +# Output locations + +LOCATE_TARGET = $(F_CPU) ; +LOCATE_SOURCE = $(F_CPU) ; + +# +# Custom rules +# + +rule GitVersion +{ + Always $(<) ; + Depends all : $(<) ; +} + +actions GitVersion +{ + echo "const char program_version[] = \"\\" > $(<) + git log -1 --pretty=format:%h >> $(<) + echo "\";" >> $(<) +} + +GitVersion version.h ; + +rule Pde +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_SOURCE) ; + Clean clean : $(<) ; +} + +if ( $(ARDUINO_VERSION) < 100 ) +{ + ARDUINO_H = WProgram.h ; +} +else +{ + ARDUINO_H = Arduino.h ; +} + +actions Pde +{ + echo "#include <$(ARDUINO_H)>" > $(<) + echo "#line 1 \"$(>)\"" >> $(<) + cat $(>) >> $(<) +} + +rule C++Pde +{ + local _CPP = $(>:B).cpp ; + Pde $(_CPP) : $(>) ; + C++ $(<) : $(_CPP) ; +} + +rule UserObject +{ + switch $(>:S) + { + case .ino : C++Pde $(<) : $(>) ; + case .pde : C++Pde $(<) : $(>) ; + } +} + +rule Objects +{ + local _i ; + + for _i in [ FGristFiles $(<) ] + { + local _b = $(_i:B)$(SUFOBJ) ; + local _o = $(_b:G=$(SOURCE_GRIST:E)) ; + Object $(_o) : $(_i) ; + Depends obj : $(_o) ; + } +} + +rule Library +{ + LibraryFromObjects $(<) : $(>:B)$(SUFOBJ) ; + Objects $(>) ; +} + +rule Main +{ + MainFromObjects $(<) : $(>:B)$(SUFOBJ) ; + Objects $(>) ; +} + +rule Hex +{ + Depends $(<) : $(>) ; + MakeLocate $(<) : $(LOCATE_TARGET) ; + Depends hex : $(<) ; + Clean clean : $(<) ; +} + +actions Hex +{ + $(OBJCOPY) -O ihex -R .eeprom $(>) $(<) +} + +rule Upload +{ + Depends $(1) : $(2) ; + Depends $(2) : $(3) ; + NotFile $(1) ; + Always $(1) ; + Always $(2) ; + UploadAction $(2) : $(3) ; +} + +actions UploadAction +{ + $(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i +} + +rule Arduino +{ + LINKFLAGS on $(<) = $(LINKFLAGS) -Wl,-Map=$(LOCATE_TARGET)/$(<:B).map ; + Main $(<) : $(>) ; + LinkLibraries $(<) : core libs ; + Hex $(<:B).hex : $(<) ; + for _p in $(PORTS) + { + Upload $(_p) : $(PORT_$(_p)) : $(<:B).hex ; + } +} + +# +# Targets +# + +# Grab everything from the core directory +Library core : [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ; + +# Grab everything from libraries. To avoid this "grab everything" behaviour, you +# can specify specific modules to pick up in PROJECT_MODULES +Library libs : [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ; + +# Main output executable +Arduino $(PWD:B).elf : $(PROJECT_MODULES) [ GLOB $(PROJECT_DIRS) : *.c *.cpp *.pde *.ino ] ; diff --git a/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/pingpair_test.pde b/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/pingpair_test.pde new file mode 100644 index 0000000..6acbf51 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/pingpair_test.pde @@ -0,0 +1,435 @@ +/* + Copyright (C) 2011 James Coliz, Jr. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * Full test on single RF pair + * + * This sketches uses as many RF24 methods as possible in a single test. + * + * To operate: + * Upload this sketch on two nodes, each with IRQ -> pin 2 + * One node needs pin 7 -> GND, the other NC. That's the receiving node + * Monitor the sending node's serial output + * Look for "+OK PASS" or "+OK FAIL" + */ + +#include +#include "nRF24L01.h" +#include "RF24.h" +#include "printf.h" + +// +// Hardware configuration +// + +// Set up nRF24L01 radio on SPI bus plus pins 8 & 9 + +RF24 radio(8,9); + +// sets the role of this unit in hardware. Connect to GND to be the 'pong' receiver +// Leave open to be the 'ping' transmitter +const short role_pin = 7; + +// +// Topology +// + +// Single radio pipe address for the 2 nodes to communicate. +const uint64_t pipe = 0xE8E8F0F0E1LL; + +// +// Role management +// +// Set up role. This sketch uses the same software for all the nodes in this +// system. Doing so greatly simplifies testing. The hardware itself specifies +// which node it is. +// +// This is done through the role_pin +// + +// The various roles supported by this sketch +typedef enum { role_sender = 1, role_receiver } role_e; + +// The debug-friendly names of those roles +const char* role_friendly_name[] = { "invalid", "Sender", "Receiver"}; + +// The role of the current running sketch +role_e role; + +// Interrupt handler, check the radio because we got an IRQ +void check_radio(void); + +// +// Payload +// + +const int min_payload_size = 4; +const int max_payload_size = 32; +int payload_size_increments_by = 2; +int next_payload_size = min_payload_size; + +char receive_payload[max_payload_size+1]; // +1 to allow room for a terminating NULL char + +// +// Test state +// + +bool done; //*< Are we done with the test? */ +bool passed; //*< Have we passed the test? */ +bool notified; //*< Have we notified the user we're done? */ +const int num_needed = 10; //*< How many success/failures until we're done? */ +int receives_remaining = num_needed; //*< How many ack packets until we declare victory? */ +int failures_remaining = num_needed; //*< How many more failed sends until we declare failure? */ +const int interval = 100; //*< ms to wait between sends */ + +char configuration = '1'; //*< Configuration key, one char sent in by the test framework to tell us how to configure, this is the default */ + +uint8_t pipe_number = 1; // Which pipe to send on. + +void one_ok(void) +{ + // Have we received enough yet? + if ( ! --receives_remaining ) + { + done = true; + passed = true; + } +} + +void one_failed(void) +{ + // Have we failed enough yet? + if ( ! --failures_remaining ) + { + done = true; + passed = false; + } +} + +// +// Setup +// + +void setup(void) +{ + // + // Role + // + + // set up the role pin + pinMode(role_pin, INPUT); + digitalWrite(role_pin,HIGH); + delay(20); // Just to get a solid reading on the role pin + + // read the address pin, establish our role + if ( digitalRead(role_pin) ) + role = role_sender; + else + role = role_receiver; + + // + // Print preamble + // + + Serial.begin(57600); + printf_begin(); + printf("\n\rRF24/tests/pingpair_test/\n\r"); + printf("ROLE: %s\n\r",role_friendly_name[role]); + + // + // Read configuration from serial + // + // It would be a much better test if this program could accept configuration + // from the serial port. Then it would be possible to run the same test under + // lots of different circumstances. + // + // The idea is that we will print "+READY" at this point. The python script + // will wait for it, and then send down a configuration script that we + // execute here and then run with. + // + // The test controller will need to configure the receiver first, then go run + // the test on the sender. + // + + printf("+READY press any key to start\n\r\n\r"); + + while (! Serial.available() ) {} + configuration = Serial.read(); + printf("Configuration\t = %c\n\r",configuration); + + // + // Setup and configure rf radio + // + + radio.begin(); + + // We will be using the Ack Payload feature, so please enable it + radio.enableAckPayload(); + + // Config 2 is special radio config + if (configuration=='2') + { + radio.setCRCLength(RF24_CRC_8); + radio.setDataRate(RF24_250KBPS); + radio.setChannel(10); + } + else + { + //Otherwise, default radio config + + // Optional: Increase CRC length for improved reliability + radio.setCRCLength(RF24_CRC_16); + + // Optional: Decrease data rate for improved reliability + radio.setDataRate(RF24_1MBPS); + + // Optional: Pick a high channel + radio.setChannel(90); + } + + // Config 3 is static payloads only + if (configuration == '3') + { + next_payload_size = 16; + payload_size_increments_by = 0; + radio.setPayloadSize(next_payload_size); + } + else + { + // enable dynamic payloads + radio.enableDynamicPayloads(); + } + + // Config 4 tests out a higher pipe ## + if (configuration == '4' && role == role_sender) + { + // Set top 4 bytes of the address in pipe 1 + radio.openReadingPipe(1,pipe & 0xFFFFFFFF00ULL); + + // indicate the pipe to use + pipe_number = 5; + } + else if ( role == role_sender ) + { + radio.openReadingPipe(5,0); + } + + // + // Open pipes to other nodes for communication + // + + // This simple sketch opens a single pipe for these two nodes to communicate + // back and forth. One listens on it, the other talks to it. + + if ( role == role_sender ) + { + radio.openWritingPipe(pipe); + } + else + { + radio.openReadingPipe(pipe_number,pipe); + } + + // + // Start listening + // + + if ( role == role_receiver ) + radio.startListening(); + + // + // Dump the configuration of the rf unit for debugging + // + + radio.printDetails(); + + // + // Attach interrupt handler to interrupt #0 (using pin 2) + // on BOTH the sender and receiver + // + + attachInterrupt(0, check_radio, FALLING); + + if ( role == role_receiver ) + printf("\n\r+OK "); +} + +// +// Print buffer +// +// Printing from the interrupt handler is a bad idea, so we print from there +// to this intermediate buffer +// + +char prbuf[1000]; +char *prbuf_end = prbuf + sizeof(prbuf); +char *prbuf_in = prbuf; +char *prbuf_out = prbuf; + +// +// Loop +// + +static uint32_t message_count = 0; +static uint32_t last_message_count = 0; + +void loop(void) +{ + // + // Sender role. Repeatedly send the current time + // + + if (role == role_sender && !done) + { + // The payload will always be the same, what will change is how much of it we send. + static char send_payload[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ789012"; + + // First, stop listening so we can talk. + radio.stopListening(); + + // Send it. This will block until complete + printf("\n\rNow sending length %i...",next_payload_size); + radio.startWrite( send_payload, next_payload_size ); + + // Update size for next time. + next_payload_size += payload_size_increments_by; + if ( next_payload_size > max_payload_size ) + next_payload_size = min_payload_size; + + // Try again soon + delay(interval); + + // Timeout if we have not received anything back ever + if ( ! last_message_count && millis() > interval * 100 ) + { + printf("No responses received. Are interrupts connected??\n\r"); + done = true; + } + } + + // + // Receiver role: Does nothing! All the work is in IRQ + // + + // + // Spew print buffer + // + + size_t write_length = prbuf_in - prbuf_out; + if ( write_length ) + { + Serial.write(reinterpret_cast(prbuf_out),write_length); + prbuf_out += write_length; + } + + // + // Stop the test if we're done and report results + // + if ( done && ! notified ) + { + notified = true; + + printf("\n\r+OK "); + if ( passed ) + printf("PASS\n\r\n\r"); + else + printf("FAIL\n\r\n\r"); + } + +} + +void check_radio(void) +{ + // What happened? + bool tx,fail,rx; + radio.whatHappened(tx,fail,rx); + + // Have we successfully transmitted? + if ( tx ) + { + if ( role == role_sender ) + prbuf_in += sprintf(prbuf_in,"Send:OK "); + + if ( role == role_receiver ) + prbuf_in += sprintf(prbuf_in,"Ack Payload:Sent\n\r"); + } + + // Have we failed to transmit? + if ( fail ) + { + if ( role == role_sender ) + { + prbuf_in += sprintf(prbuf_in,"Send:Failed "); + + // log status of this line + one_failed(); + } + + if ( role == role_receiver ) + prbuf_in += sprintf(prbuf_in,"Ack Payload:Failed\n\r"); + } + + // Transmitter can power down for now, because + // the transmission is done. + if ( ( tx || fail ) && ( role == role_sender ) ) + radio.powerDown(); + + // Did we receive a message? + if ( rx ) + { + // If we're the sender, we've received an ack payload + if ( role == role_sender ) + { + radio.read(&message_count,sizeof(message_count)); + prbuf_in += sprintf(prbuf_in,"Ack:%lu ",message_count); + + // is this ack what we were expecting? to account + // for failures, we simply want to make sure we get a + // DIFFERENT ack every time. + if ( ( message_count != last_message_count ) || ( configuration=='3' && message_count == 16 ) ) + { + prbuf_in += sprintf(prbuf_in,"OK "); + one_ok(); + } + else + { + prbuf_in += sprintf(prbuf_in,"FAILED "); + one_failed(); + } + last_message_count = message_count; + } + + // If we're the receiver, we've received a time message + if ( role == role_receiver ) + { + // Get this payload and dump it + size_t len = max_payload_size; + memset(receive_payload,0,max_payload_size); + + if ( configuration == '3' ) + len = next_payload_size; + else + len = radio.getDynamicPayloadSize(); + + radio.read( receive_payload, len ); + + // Put a zero at the end for easy printing + receive_payload[len] = 0; + + // Spew it + prbuf_in += sprintf(prbuf_in,"Recv size=%i val=%s len=%u\n\r",len,receive_payload,strlen(receive_payload)); + + // Add an ack packet for the next time around. + // Here we will report back how many bytes we got this time. + radio.writeAckPayload( pipe_number, &len, sizeof(len) ); + ++message_count; + } + } +} + +// vim:ai:cin:sts=2 sw=2 ft=cpp diff --git a/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/printf.h b/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/printf.h new file mode 100644 index 0000000..b2efd56 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/printf.h @@ -0,0 +1,37 @@ +/* + Copyright (C) 2011 J. Coliz + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + */ + +/** + * @file printf.h + * + * Setup necessary to direct stdout to the Arduino Serial library, which + * enables 'printf' + */ + +#ifndef __PRINTF_H__ +#define __PRINTF_H__ + +#ifdef ARDUINO + +int serial_putc( char c, FILE * ) +{ + Serial.write( c ); + + return c; +} + +void printf_begin(void) +{ + fdevopen( &serial_putc, 0 ); +} + +#else +#error This example is only for use on Arduino. +#endif // ARDUINO + +#endif // __PRINTF_H__ diff --git a/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/runtest.py b/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/runtest.py new file mode 100644 index 0000000..45fb65c --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/runtest.py @@ -0,0 +1,25 @@ +#!/opt/local/bin/python + +import sys,serial + +def read_until(token): + while 1: + line = ser.readline(None,"\r") + sys.stdout.write(line) + + if (line.startswith(token)): + break + return line + + +ser = serial.Serial(sys.argv[1], 57600, timeout=5, dsrdtr=False, rtscts=False) + +read_until("+READY") +ser.write(sys.argv[2]) + +line = read_until("+OK") +ser.close() +if (line.find("PASS") != -1): + sys.exit(0) +else: + sys.exit(1) diff --git a/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/runtests.sh b/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/runtests.sh new file mode 100644 index 0000000..4d02310 --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/runtests.sh @@ -0,0 +1,21 @@ +#!/bin/sh + +# Connect u0 to receiver, u0 to sender +# WARNING: Test config 2 only works with PLUS units. + +jam u0 u1 && expect test.ex 1 +sleep 1 +stty 57600 raw ignbrk hup < /dev/ttyUSB0 +sleep 1 +stty 57600 raw ignbrk hup < /dev/ttyUSB1 +expect test.ex 2 +sleep 1 +stty 57600 raw ignbrk hup < /dev/ttyUSB0 +sleep 1 +stty 57600 raw ignbrk hup < /dev/ttyUSB1 +expect test.ex 3 +sleep 1 +stty 57600 raw ignbrk hup < /dev/ttyUSB0 +sleep 1 +stty 57600 raw ignbrk hup < /dev/ttyUSB1 +expect test.ex 4 diff --git a/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/test.ex b/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/test.ex new file mode 100644 index 0000000..a14ffef --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/tests/pingpair_test/test.ex @@ -0,0 +1,11 @@ +#/usr/bin/expect + +set timeout 100 +spawn picocom -b 57600 /dev/ttyUSB0 +expect "+READY" +send [lindex $argv 0] +expect "+OK" +spawn picocom -b 57600 /dev/ttyUSB1 +expect "+READY" +send [lindex $argv 0] +expect "+OK" diff --git a/hardware/digistump/avr/libraries/RF24/wikidoc.xslt b/hardware/digistump/avr/libraries/RF24/wikidoc.xslt new file mode 100644 index 0000000..b94d3ef --- /dev/null +++ b/hardware/digistump/avr/libraries/RF24/wikidoc.xslt @@ -0,0 +1,41 @@ + + + + + + + + === === + + + + + '''' + +Parameters: + + + + * '''': + + + + + +Returns: + +* + + +Warning: + + + + <pre> </pre> + + + + + + + diff --git a/hardware/digistump/avr/libraries/RcSeq/Examples/DigiRcSeqZodiac/DigiRcSeqZodiac.ino b/hardware/digistump/avr/libraries/RcSeq/Examples/DigiRcSeqZodiac/DigiRcSeqZodiac.ino new file mode 100644 index 0000000..333fd77 --- /dev/null +++ b/hardware/digistump/avr/libraries/RcSeq/Examples/DigiRcSeqZodiac/DigiRcSeqZodiac.ino @@ -0,0 +1,192 @@ +/* +Sketch using library, for automatically dropping a pneumatic Zodiac at sea and returning for it back to the deck of a supply vessel. +The sequence is launched after sending the 'g' (Go) character at the USB interface. + +In this example, the declared sequence is: +1) The crane lifts the pneumatic Zodiac from the deck to the air and stops +2) The crane rotates (90°) to locate the pneumatic Zodiac above the sea +3) The crane drops down the pneumatic Zodiac at sea level +4) The crane stops during 6 seconds +5) The crane lifts up the pneumatic Zodiac from sea level to the air and stops +6) The crane rotates (90°) to locate the pneumatic Zodiac above the deck +7) The crane drops down the pneumatic Zodiac on the deck and stops. The sequence ends. +This sequence uses: +- 2 commands from USB interface ('g' and 't' characters from Digiterm or Digi Monitor) +- 2 servos (a "ROTATION" servo for the crane rotation and an "UP/DOWN" servo to drop and lift the pneumatic Zodiac) + +IMPORTANT: +========= +For this sketch, which is using library: +1) Comment "#define RC_SEQ_WITH_SOFT_RC_PULSE_IN_SUPPORT" in "arduino-1.xx\libraries\RcSeq.h". + This will disable the code to manage incoming RC pulses and save some flash memory. +2) Replace #define RING_BUFFER_SIZE 128 with #define RING_BUFFER_SIZE 32 in "arduino-1.xx\libraries\DigisparkUSB\DigiUSB.h". +3) The sequence will be launch by sending "g" character through USB link (using Digiterm or Digi Monitor). + To check all the sequence is performed asynchronously, you can send 't' to toggle the LED during servo motion! +If step 1) and 2) are not done, this sketch won't compile because won't fit in programm memory of the DigiSpark! + +RC Navy 2013 +http://p.loussouarn.free.fr +*/ + +static void ToggleLed(void); /* Declare Short Action: Toggle a LED */ + +/*************************************************/ +/* STEP #1: Include the needed libraries */ +/*************************************************/ +#include /* The Servo Sequence will be launched by sending "g" character (Go) at the USB interface */ +#include +#include + +#define LED_PIN 1 + +/*****************************************************************/ +/* STEP #2: Enumeration of the servos used in the sequence */ +/*****************************************************************/ +enum {ROTATION_SERVO=0, UP_DOWN_SERVO , SERVO_NB}; + +/*****************************************************************/ +/* STEP #3: Servos Digital Pins assignment */ +/*****************************************************************/ +#define UP_DOWN_SERVO_PIN 2 +/* /!\ Do not use Pin 3 (used by USB) /!\ */ +/* /!\ Do not use Pin 4 (used by USB) /!\ */ +#define ROTATION_SERVO_PIN 5 + +/**************************************************************************************/ +/* STEP #4: Declaration of the angles of the servos for the different motions (in °) */ +/**************************************************************************************/ +#define UP_DOWN_ON_DECK_POS 120 /* Zodiac on the deck */ +#define UP_DOWN_ON_AIR_POS 180 /* Zodiac in the air */ +#define UP_DOWN_ON_SEA_POS 0 /* Zodiac at sea level */ + +#define ROTATION_ABOVE_DECK_POS 90 /* crane at deck side */ +#define ROTATION_ABOVE_SEA_POS 0 /* crane at sea side */ + + +/***************************************************************************************************************************************/ +/* STEP #5: Do a temporal diagram showing the start up and the duration of each motions of each servo */ +/***************************************************************************************************************************************/ +/* +All the start up values (time stamp) have as reference the moment of the sequence startup order (t=0). + + UP_DOWN_SERVO MOTION ROTATION_SERVO MOTION UP_DOWN_SERVO MOTION NO MOTION MOUVEMENT(WAITING) UP_DOWN_SERVO MOTION ROTATION_SERVO MOTION UP_DOWN_SERVO MOTION +Order <--DECK_TO_AIR_DURATION_MS--> <--DECK_TO_SEA_ROTATION_DURATION_MS--> <--AIR_TO_SEA_FALLING_DURATION_MS--> <--DELAY_BEFORE_RISING_UP_MS--> <--SEA_TO_AIR_RISING_DURATION_MS--> <--SEA_TO_DECK_ROTATION_DURATION_MS--> <--AIR_TO_DECK_FALLING_DURATION_MS--> + |-------------------|-----------------------------|--------------------------------------|------------------------------------|-------------------------------|-----------------------------------|--------------------------------------|-------------------------------------|-->Time Axis + 0 START_UP_DECK_TO_AIR_MS START_UP_DECK_TO_SEA_ROTATION_MS START_UP_AIR_TO_SEA_FALLING_MS START_UP_SEA_TO_AIR_RISING_MS START_UP_SEA_TO_DECK_ROTATION_MS START_UP_AIR_TO_DECK_FALLING_MS +*/ + +/**************************************************************************************************************************************************/ +/* STEP #6: With the help of the temporal diagram, declare start up time, the motion duration of servo and optional delay */ +/**************************************************************************************************************************************************/ +/* Tune below all the motion duration. Do not forget to add a trailer 'UL' for each value to force them in Unsigned Long type */ +#define START_UP_DECK_TO_AIR_MS 0UL /* 0 for immediate start up, but you can put a delay here. Ex: 2000UL, will delay the startup of the whole sequence after 2 seconds */ +#define DECK_TO_AIR_DURATION_MS 3000UL + +#define START_UP_DECK_TO_SEA_ROTATION_MS (START_UP_DECK_TO_AIR_MS + DECK_TO_AIR_DURATION_MS) +#define DECK_TO_SEA_ROTATION_DURATION_MS 3000UL + +#define START_UP_AIR_TO_SEA_FALLING_MS (START_UP_DECK_TO_SEA_ROTATION_MS + DECK_TO_SEA_ROTATION_DURATION_MS) +#define AIR_TO_SEA_FALLING_DURATION_MS 9000UL + +#define DELAY_BEFORE_RISING_UP_MS 6000UL + +#define START_UP_SEA_TO_AIR_RISING_MS (START_UP_AIR_TO_SEA_FALLING_MS + AIR_TO_SEA_FALLING_DURATION_MS + DELAY_BEFORE_RISING_UP_MS) +#define SEA_TO_AIR_RISING_DURATION_MS 9000UL + +#define START_UP_SEA_TO_DECK_ROTATION_MS (START_UP_SEA_TO_AIR_RISING_MS + SEA_TO_AIR_RISING_DURATION_MS) +#define SEA_TO_DECK_ROTATION_DURATION_MS 3000UL + + +#define START_UP_AIR_TO_DECK_FALLING_MS (START_UP_SEA_TO_DECK_ROTATION_MS + SEA_TO_DECK_ROTATION_DURATION_MS) +#define AIR_TO_DECK_FALLING_DURATION_MS 3000UL + +/********************************************************************************************************************/ +/* STEP #7: Declare here the percentage of motion to be performed at half speed for servo start up and stop */ +/********************************************************************************************************************/ +#define START_STOP_PER_CENT 5L /* Percentage of motion performed at half speed for servo start and servo stop (Soft start and Soft stop) */ +/* Note: due to the lack of programm memory on the DigiSpark, this feature is not used */ + +/************************************************************************************************************/ +/* STEP #11: Use a "SequenceSt_t" structure table to declare the servo sequence */ +/* For each table entry, arguments are: */ +/* - Servo Index */ +/* - Initial Servo Position in ° */ +/* - Final Servo Position in ° */ +/* - Motion Start Time Stamp in ms */ +/* - Motion duration in ms between initial and final position */ +/* - Percentage of motion performed at half speed for servo start and servo stop (Soft start and Soft stop) */ +/* Note: START_STOP_PER_CENT not used (MOTION_WITHOUT_SOFT_START_AND_STOP() macro used) */ +/************************************************************************************************************/ +SequenceSt_t ZodiacSequence[] PROGMEM = { + SHORT_ACTION_TO_PERFORM(ToggleLed, START_UP_DECK_TO_AIR_MS) /* Switch ON the Led at the beginning of the sequence */ + SHORT_ACTION_TO_PERFORM(ToggleLed, START_UP_AIR_TO_DECK_FALLING_MS+AIR_TO_DECK_FALLING_DURATION_MS) /* Switch OFF the Led at the beginning of the sequence: You are not obliged to put this line at the end of the table */ + /* 1) The crane lifts the pneumatic Zodiac from the deck to the air and stops */ + MOTION_WITHOUT_SOFT_START_AND_STOP(UP_DOWN_SERVO, UP_DOWN_ON_DECK_POS, UP_DOWN_ON_AIR_POS, START_UP_DECK_TO_AIR_MS, DECK_TO_AIR_DURATION_MS) + /* 2) The crane rotates (90°) to locate the pneumatic Zodiac above the sea */ + MOTION_WITHOUT_SOFT_START_AND_STOP(ROTATION_SERVO, ROTATION_ABOVE_DECK_POS, ROTATION_ABOVE_SEA_POS, START_UP_DECK_TO_SEA_ROTATION_MS, DECK_TO_SEA_ROTATION_DURATION_MS) + /* 3) The crane drops down the pneumatic Zodiac at sea level */ + MOTION_WITHOUT_SOFT_START_AND_STOP(UP_DOWN_SERVO, UP_DOWN_ON_AIR_POS, UP_DOWN_ON_SEA_POS, START_UP_AIR_TO_SEA_FALLING_MS, AIR_TO_SEA_FALLING_DURATION_MS) + /* 4) The crane stops during 6 seconds and 5) The crane lifts up the pneumatic Zodiac from sea level to the air and stops */ + MOTION_WITHOUT_SOFT_START_AND_STOP(UP_DOWN_SERVO, UP_DOWN_ON_SEA_POS, UP_DOWN_ON_AIR_POS, START_UP_SEA_TO_AIR_RISING_MS, SEA_TO_AIR_RISING_DURATION_MS) + /* 6) The crane rotates (90°) to locate the pneumatic Zodiac above the deck */ + MOTION_WITHOUT_SOFT_START_AND_STOP(ROTATION_SERVO, ROTATION_ABOVE_SEA_POS, ROTATION_ABOVE_DECK_POS, START_UP_SEA_TO_DECK_ROTATION_MS, SEA_TO_DECK_ROTATION_DURATION_MS) + /* 7) The crane drops down the pneumatic Zodiac on the deck and stops. The sequence ends. */ + MOTION_WITHOUT_SOFT_START_AND_STOP(UP_DOWN_SERVO, UP_DOWN_ON_AIR_POS, UP_DOWN_ON_DECK_POS, START_UP_AIR_TO_DECK_FALLING_MS, AIR_TO_DECK_FALLING_DURATION_MS) + }; + +void setup() +{ + pinMode(LED_PIN, OUTPUT); + + DigiUSB.begin(); + +/***************************************************************************/ +/* STEP #9: Init library */ +/***************************************************************************/ + RcSeq_Init(); + +/****************************************************************************************/ +/* STEP #10: declare the servo command signals with their digital pin number */ +/****************************************************************************************/ + RcSeq_DeclareServo(UP_DOWN_SERVO, UP_DOWN_SERVO_PIN); + RcSeq_DeclareServo(ROTATION_SERVO, ROTATION_SERVO_PIN); + +/**************************************************************************************************************************/ +/* STEP #11: declare the sequence command signal (0), the stick level (0), and the sequence to call */ +/**************************************************************************************************************************/ + RcSeq_DeclareCommandAndSequence(0, 0, RC_SEQUENCE(ZodiacSequence)); /* 0,0 since there's no RC command */ +} + +void loop() +{ +char RxChar; + +/***********************************************************************************************************************************/ +/* STEP #12: call the refresh function inside the loop() to catch RC commands and to manage the servo positions */ +/***********************************************************************************************************************************/ + RcSeq_Refresh(); + +/****************************************************************************************************************/ +/* STEP #13: the sequence can be launched directly by calling the RcSeq_LaunchSequence() function */ +/****************************************************************************************************************/ + if(DigiUSB.available()) + { + RxChar=DigiUSB.read(); + if(RxChar=='g') /* Go ! */ + { + RcSeq_LaunchSequence(ZodiacSequence); + } + if(RxChar=='t') /* Toggle LED ! */ + { + RcSeq_LaunchShortAction(ToggleLed); /* You can toggle LED during Servo Motion! */ + } + } + DigiUSB.refresh(); +} + +static void ToggleLed(void) +{ +static boolean Status=LOW; + Status=!Status; /* Toggle Status */ + digitalWrite(LED_PIN, Status); +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/RcSeq/Examples/OnePropTo5/OnePropTo5.ino b/hardware/digistump/avr/libraries/RcSeq/Examples/OnePropTo5/OnePropTo5.ino new file mode 100644 index 0000000..648d30c --- /dev/null +++ b/hardware/digistump/avr/libraries/RcSeq/Examples/OnePropTo5/OnePropTo5.ino @@ -0,0 +1,123 @@ +#include +#include +#include +#include + +/* +This sketch demonstrates how to easily transform a proportionnal RC channel into 5 digital commands with an ATtiny85. +RC Navy (2013) +http://P.loussouarn.free.fr + +COMMMAND OF 5 digital outputs from 5 push button replacing a potentiometer in the RC transmitter: +================================================================================================ + Output pins: #1, #2, #3, #4, #5 of an ATtiny85 or a Digispark + The receiver output channel is connected to pin#0 of an ATtiny85 or a Digispark + A furtive pressure on the push button on the transmitter toggles the corresponding output on the ATtiny85 or a Digispark + connected to the receiver output channel. + Version with RcSeq library inspired by: http://bateaux.trucs.free.fr/huit_sorties.html + +Modification at RC Transmitter side: +=================================== + Custom keyboard with push buttons + ================================= + Stick Potentiometer 1K 1K 1K 1K 1K 1K + =================== .--###---+---###---+---###---+---###---+---###---+---###---. + .-. .--. .-. | _.| _.| _.| _.| _.| | + |O|--' | |O|-' PB1 |_| PB2 |_| PB3 |_| PB4 |_| PB5 |_| | PB# = Push Button # + | | # Replaced with | | '| '| '| '| '| | + |O|----># ============> |O|----------+---------+---------+---------+---------+---###---+ + | | # | | 100K | + |O|-- | |O|------------------------------------------------------------' + '-' '--' '-' + + +At RC Receiver side: (The following sketch is related to this ATtiny85 or Digispark) +=================== + + .---------------. + | | + | ,------+------. + | | VDD |1 + | | +-- LED, Relay, etc... + | | | + | | |2 + | | +-- LED, Relay, etc... + | | | + | | ATtiny85 |3 + | | or +-- LED, Relay, etc... + .------------. | | Digispark | + | |-----' 0| |4 + | Channel#1|--------------+ +-- LED, Relay, etc... + | |-----. | | + | RC | | | |5 + | RECEIVER | | | +-- LED, Relay, etc... + | | | | GND | + | |- | '------+------' + | Channel#2|- | | + | |- '---------------' + '------------' + +Note: +==== +- Decoupling capacitors are not drawn. +- This sketch can easily be extended to 8 outputs by using an ATtiny84 which has more pins. +- This sketch cannot work if you are using DigiUSB library as this one monopolizes the "pin change interrupt vector" (which is very time sensitive). +- On the other side, its possible to communicate with exterior world by using , a library mainly derived from , but which + allow to share the pin change interrupt vector through the library. + +================================================================================================*/ + +/* Channel Declaration */ +enum {RC_CHANNEL, RC_CHANNEL_NB}; /* Here, as there is a single channel, we could used a simple "#define RC_CHANNEL 0" rather an enumeration */ + +//============================================================================================== +/* Channel Signal of the Receiver */ +#define RX_CHANNEL_SIGNAL_PIN 0 + +//============================================================================================== +/* Declaration of the custom keyboard": the pulse width of the push buttons do not need to be equidistant */ +enum {PUSH_BUTTON1, PUSH_BUTTON2, PUSH_BUTTON3, PUSH_BUTTON4, PUSH_BUTTON5, PUSH_BUTTON_NBR}; +#define TOLERANCE 40 /* Tolerance +/- (in microseconds): CAUTION, no overlap allowed between 2 adjacent active areas . active area width = 2 x TOLERANCE (us) */ +KeyMap_t CustomKeyboard[] PROGMEM ={ {CENTER_VALUE_US(1100,TOLERANCE)}, /* PUSH_BUTTON1: +/-40 us */ + {CENTER_VALUE_US(1300,TOLERANCE)}, /* PUSH_BUTTON2: +/-40 us */ + {CENTER_VALUE_US(1500,TOLERANCE)}, /* PUSH_BUTTON3: +/-40 us */ + {CENTER_VALUE_US(1700,TOLERANCE)}, /* PUSH_BUTTON4: +/-40 us */ + {CENTER_VALUE_US(1900,TOLERANCE)}, /* PUSH_BUTTON5: +/-40 us */ + }; + +//============================================================================================== +/* Trick: a macro to write a single time the ToggleAction#() function */ +#define DECLARE_TOGGLE_ACTION(Idx) \ +void ToggleAction##Idx(void) \ +{ \ +static boolean Etat=HIGH; \ + digitalWrite(Idx, Etat); \ + Etat=!Etat; \ +} + +/* Declaration of the actions using the DECLARE_TOGGLE_ACTION(Idx) macro with Idx = The number of the action and the pin number (The ##Idx will be automatically replaced with the Idx value */ +DECLARE_TOGGLE_ACTION(1) +DECLARE_TOGGLE_ACTION(2) +DECLARE_TOGGLE_ACTION(3) +DECLARE_TOGGLE_ACTION(4) +DECLARE_TOGGLE_ACTION(5) + +//============================================================================================== +void setup() +{ + RcSeq_Init(); + RcSeq_DeclareSignal(RC_CHANNEL, RX_CHANNEL_SIGNAL_PIN); /* RC_CHANNEL Channel is assigned to RX_CHANNEL_SIGNAL_PIN pin */ + RcSeq_DeclareCustomKeyboard(RC_CHANNEL, RC_CUSTOM_KEYBOARD(CustomKeyboard)); /* The CustomKeyboard map is assigned to the RC_CHANNEL Channel */ + RcSeq_DeclareCommandAndShortAction(RC_CHANNEL, PUSH_BUTTON1, ToggleAction1);pinMode(1,OUTPUT); /* The ToggleAction1 is assigned to the PUSH_BUTTON1 push button #1 */ + RcSeq_DeclareCommandAndShortAction(RC_CHANNEL, PUSH_BUTTON2, ToggleAction2);pinMode(2,OUTPUT); /* The ToggleAction2 is assigned to the PUSH_BUTTON1 push button #2 */ + RcSeq_DeclareCommandAndShortAction(RC_CHANNEL, PUSH_BUTTON3, ToggleAction3);pinMode(3,OUTPUT); /* The ToggleAction3 is assigned to the PUSH_BUTTON1 push button #3 */ + RcSeq_DeclareCommandAndShortAction(RC_CHANNEL, PUSH_BUTTON4, ToggleAction4);pinMode(4,OUTPUT); /* The ToggleAction4 is assigned to the PUSH_BUTTON1 push button #4 */ + RcSeq_DeclareCommandAndShortAction(RC_CHANNEL, PUSH_BUTTON5, ToggleAction5);pinMode(5,OUTPUT); /* The ToggleAction5 is assigned to the PUSH_BUTTON1 push button #5 */ +} +//============================================================================================== +void loop() +{ + RcSeq_Refresh(); /* This function performs all the needed job asynchronously (non blocking) */ +} +//============================ END OF SKETCH ================================================= + diff --git a/hardware/digistump/avr/libraries/RcSeq/Examples/RcSeqDemo/RcSeqDemo.ino b/hardware/digistump/avr/libraries/RcSeq/Examples/RcSeqDemo/RcSeqDemo.ino new file mode 100644 index 0000000..534e79b --- /dev/null +++ b/hardware/digistump/avr/libraries/RcSeq/Examples/RcSeqDemo/RcSeqDemo.ino @@ -0,0 +1,140 @@ +/* +Ce sketch de demo de la librairie RcSeq montre comment configurer tres facilement la commande d'actions ou de sequences de servo predefinies. +La commande peut etre: +- un manche de l'emetteur RC avec possibilité de definir jusqu'a 8 positions "actives" (le nombre de position doit etre pair: neutre au milieu) +- un clavier: un montage resistances/boutons-poussoirs remplacant le potentiometre du manche d'un emetteur RC + (les resistances doivent etre d'egales valeurs avec une 2 resistances identiques "au centre/neutre" pour la zone inactive) +- un clavier "maison": un montage resistances/boutons-poussoirs remplacant le potentiometre du manche d'un emetteur RC avec des resistances pas forcement identiques + (la largeur d'impulsion pour chaque bouton-poussoir est define dans une table, une tolerance est egalement prevue) +Les 3 exemples sont traites dans ce sketch de demo. +*/ +#include +#include /* Ne pas oublier d'inclure la librairie qui est utilisee par la librairie */ +#include /* Ne pas oublier d'inclure la librairie qui est utilisee par la librairie */ +#include /* Ne pas oublier d'inclure la librairie qui est utilisee par la librairie */ + +enum {RC_VOIE1, RC_VOIE2, RC_VOIE3, NBR_VOIES_RC}; /* Declaration des voies */ + +enum {BP1, BP2, NBR_BP}; /* Declaration des Boutons-Poussoirs (On peut aller jusqu'à BP8) */ + +enum {POS_MINUS1, POS_PLUS1,NBR_POS}; /* Declaration des positions du Manche on peut aller de POS_MOINS2 à POS_PLUS2 (4 Positions actives Max)*/ + + +/* Declaration d'un clavier "Maison": les impulsions des Boutons-Poussoirs n'ont pas besoin d'etre equidistantes */ +enum {BP_MAISON1, BP_MAISON2, BP_MAISON3, NBR_BP_MAISON}; +#define TOLERANCE 40 /* Tolerance en + ou en - (en micro-seconde) */ +KeyMap_t ClavierMaison[] PROGMEM ={ {VALEUR_CENTRALE_US(1100,TOLERANCE)}, /* BP_MAISON1: 1100 +/-40 us */ + {VALEUR_CENTRALE_US(1300,TOLERANCE)}, /* BP_MAISON2: 1300 +/-40 us */ + {VALEUR_CENTRALE_US(1700,TOLERANCE)}, /* BP_MAISON3: 1700 +/-40 us */ + }; + +enum {AZIMUT=0, ELEVATION , NBR_SERVO}; /* Delaration de tous les servos, 2 dans cet exemple (On peut déclaer jusqu'à 8 servos) */ + +/* Declaration des broches reliees aux sorties du recepteur RC */ +#define BROCHE_SIGNAL_RECEPTEUR_VOIE1 8 +#define BROCHE_SIGNAL_RECEPTEUR_VOIE2 2 +#define BROCHE_SIGNAL_RECEPTEUR_VOIE3 9 + +/* Declaration des broches de commande des servos */ +#define BROCHE_SIGNAL_SERVO_EL 3 +#define BROCHE_SIGNAL_SERVO_AZ 4 + +/* Declaration des differents angles des servos */ +#define ELEVATION_POS_PONT 120 /* position zodiac sur pont (Pos A) */ +#define ELEVATION_POS_HAUT 180 /* position zodiac en haut (Pos B) */ +#define ELEVATION_POS_MER 0 /* position zodiac dans l'eau (pos C) */ + +#define AZIMUT_POS_PONT 90 /* position rotation sur pont */ +#define AZIMUT_POS_MER 0 /* position rotation sur mer */ + +/* Declaration des moments de demarrage ainsi que la duree des mouvement de servo */ +#define DEMARRAGE_MONTEE_PONT_HAUT_MS 0L /* 0 pour demarrage immediat, mais on peut mettre une tempo ici. Ex 2000L, va differer la sequence complete de 2 secondes */ +#define DUREE_MONTEE_PONT_HAUT_MS 3000L + +#define DEMARRAGE_ROTATION_PONT_MER_MS (DEMARRAGE_MONTEE_PONT_HAUT_MS+DUREE_MONTEE_PONT_HAUT_MS) +#define DUREE_ROTATION_PONT_MER_MS 3000L + +#define DEMARRAGE_DESCENTE_HAUT_MER_MS (DEMARRAGE_ROTATION_PONT_MER_MS+DUREE_ROTATION_PONT_MER_MS) +#define DUREE_DESCENTE_HAUT_MER_MS 9000L + +#define ATTENTE_AVANT_REMONTEE_MS 6000L /* Exemple d'utilisation d'une temporisation */ + +#define DEMARRAGE_MONTEE_MER_HAUT_MS (DEMARRAGE_DESCENTE_HAUT_MER_MS+DUREE_DESCENTE_HAUT_MER_MS+ATTENTE_AVANT_REMONTEE_MS) +#define DUREE_MONTEE_MER_HAUT_MS 9000L + +#define DEMARRAGE_ROTATION_MER_PONT_MS (DEMARRAGE_MONTEE_MER_HAUT_MS+DUREE_MONTEE_MER_HAUT_MS) +#define DUREE_ROTATION_MER_PONT_MS 3000L + + +#define DEMARRAGE_DESCENTE_HAUT_PONT_MS (DEMARRAGE_ROTATION_MER_PONT_MS+DUREE_ROTATION_MER_PONT_MS) +#define DUREE_DESCENTE_HAUT_PONT_MS 3000L + +#define DEM_ARRET_POUR_CENT 5 /* Pourcentage du mouvement devant etre effectue a mi-vitesse pour demarrage servo et arret servo (Soft start et Soft stop) */ + +/* Declaration de la table de sequence des mouvements des servo et des actions courtes */ +SequenceSt_t SequenceServoEtActionCourte[] PROGMEM = { + ACTION_COURTE_A_EFFECTUER(InverseLed,DEMARRAGE_MONTEE_PONT_HAUT_MS) + /* Montee du Zodiac du pont vers la position haute */ + MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS(ELEVATION,ELEVATION_POS_PONT,ELEVATION_POS_HAUT,DEMARRAGE_MONTEE_PONT_HAUT_MS,DUREE_MONTEE_PONT_HAUT_MS,DEM_ARRET_POUR_CENT) + /* Rotation Grue du pont vers la mer */ + MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS(AZIMUT,AZIMUT_POS_PONT,AZIMUT_POS_MER,DEMARRAGE_ROTATION_PONT_MER_MS,DUREE_ROTATION_PONT_MER_MS,DEM_ARRET_POUR_CENT) + /* Descente du Zodiac depuis la position haute vers la la mer */ + MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS(ELEVATION,ELEVATION_POS_HAUT,ELEVATION_POS_MER,DEMARRAGE_DESCENTE_HAUT_MER_MS,DUREE_DESCENTE_HAUT_MER_MS,DEM_ARRET_POUR_CENT) + ACTION_COURTE_A_EFFECTUER(InverseLed,DEMARRAGE_DESCENTE_HAUT_MER_MS+DUREE_DESCENTE_HAUT_MER_MS) + ACTION_COURTE_A_EFFECTUER(InverseLed,DEMARRAGE_MONTEE_MER_HAUT_MS) + /* Montee du Zodiac de la mer vers la position haute */ + MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS(ELEVATION,ELEVATION_POS_MER,ELEVATION_POS_HAUT,DEMARRAGE_MONTEE_MER_HAUT_MS,DUREE_MONTEE_MER_HAUT_MS,DEM_ARRET_POUR_CENT) + /* Rotation Grue de la mer vers le pont */ + MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS(AZIMUT,AZIMUT_POS_MER,AZIMUT_POS_PONT,DEMARRAGE_ROTATION_MER_PONT_MS,DUREE_ROTATION_MER_PONT_MS,DEM_ARRET_POUR_CENT) + /* Descente du Zodiac de la position haute vers le pont */ + MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS(ELEVATION,ELEVATION_POS_HAUT,ELEVATION_POS_PONT,DEMARRAGE_DESCENTE_HAUT_PONT_MS,DUREE_DESCENTE_HAUT_PONT_MS,DEM_ARRET_POUR_CENT) + ACTION_COURTE_A_EFFECTUER(InverseLed,DEMARRAGE_DESCENTE_HAUT_PONT_MS+DUREE_DESCENTE_HAUT_PONT_MS) + }; + +#define LED 13 + +void setup() +{ +#if !defined(__AVR_ATtiny24__) && !defined(__AVR_ATtiny44__) && !defined(__AVR_ATtiny84__) && !defined(__AVR_ATtiny25__) && !defined(__AVR_ATtiny45__) && !defined(__AVR_ATtiny85__) + Serial.begin(9600); + Serial.print("RcSeq library V");Serial.print(RcSeq_LibTextVersionRevision());Serial.print(" demo: RcSeqDemo"); +#endif + RcSeq_Init(); + + /* Declaration des Servos */ + RcSeq_DeclareServo(ELEVATION, BROCHE_SIGNAL_SERVO_EL); + RcSeq_DeclareServo(AZIMUT, BROCHE_SIGNAL_SERVO_AZ); + + /* Commande d'une action courte et d'une sequence de servos avec 2 BP du clavier de la VOIE1 */ + RcSeq_DeclareSignal(RC_VOIE1,BROCHE_SIGNAL_RECEPTEUR_VOIE1); + RcSeq_DeclareClavier(RC_VOIE1, 1000, 2000, NBR_BP); + RcSeq_DeclareCommandeEtActionCourte(RC_VOIE1, BP1, InverseLed); + RcSeq_DeclareCommandeEtSequence(RC_VOIE1, BP2, RC_SEQUENCE(SequenceServoEtActionCourte)); + + /* Commande d'une action courte et d'une sequence de servos avec le manche de la VOIE2 */ + RcSeq_DeclareSignal(RC_VOIE2,BROCHE_SIGNAL_RECEPTEUR_VOIE2); + RcSeq_DeclareManche(RC_VOIE2, 1000, 2000, NBR_POS); + RcSeq_DeclareCommandeEtActionCourte(RC_VOIE2, POS_MINUS1, InverseLed); + RcSeq_DeclareCommandeEtSequence(RC_VOIE2, POS_PLUS1, RC_SEQUENCE(SequenceServoEtActionCourte)); + + /* Commande d'une action courte et d'une sequence de servos avec le clavier "maison" de la VOIE3 */ + RcSeq_DeclareSignal(RC_VOIE3,BROCHE_SIGNAL_RECEPTEUR_VOIE3); + RcSeq_DeclareClavierMaison(RC_VOIE3, RC_CLAVIER_MAISON(ClavierMaison)); + RcSeq_DeclareCommandeEtActionCourte(RC_VOIE3, BP_MAISON1, InverseLed); + RcSeq_DeclareCommandeEtSequence(RC_VOIE3, BP_MAISON3, RC_SEQUENCE(SequenceServoEtActionCourte)); + + pinMode(LED, OUTPUT); +} + +void loop() +{ + RcSeq_Rafraichit(); +} + +/* Action associee au BP1 de la VOIE1 ou au manche position basse de la VOIE2 ou au BP_MAISON1 de la VOIE3 */ +void InverseLed(void) +{ +static boolean Etat=HIGH; /* static, pour conserver l'etat entre 2 appels de la fonction */ + digitalWrite(LED, Etat); + Etat=!Etat; /* AU prochain appel de InverseLed(), l'etat de la LED sera inverse */ +} diff --git a/hardware/digistump/avr/libraries/RcSeq/Examples/RcSeqZodiac/RcSeqZodiac.ino b/hardware/digistump/avr/libraries/RcSeq/Examples/RcSeqZodiac/RcSeqZodiac.ino new file mode 100644 index 0000000..cd6dec5 --- /dev/null +++ b/hardware/digistump/avr/libraries/RcSeq/Examples/RcSeqZodiac/RcSeqZodiac.ino @@ -0,0 +1,218 @@ +/* +IMPORTANT: +========= +La librairie "RcSeq" utilise la technique de programmation dite "asynchrone", c'est-a-dire qu'aucun appel a des fonctions bloquantes telles que la fonction delay() +ou la fonction pulseIn() n'est effectue. +Ceci se traduit par un temps de boucle principale inferieur a 70 micro-secondes bien que les servos soient rafraichis toutes les 20ms a l'aide de la methode +Rafraichit() qui doit etre appelee dans la fonction loop(). Cela laisse donc enormement de temps au micro-controleur pour faire "en meme temps" d'autres taches. +Par exemple dans ce sketch, il est possible d'envoyer la commande 'i' via la serial console pour inverser l'etat de la LED connectee a la pin digitale 13 pendant +que les servos sont en mouvement. + +Ce sketch illustre l'utilisation de la librairie "RcSeq" qui permet de sequencer tres facilement des servos et des actions courtes a l'aide de la librairie "SoftwareServo". +Les actions courtes doivent durer moins de 20ms pour ne pas perturber la commande des servos. +Si ce sketch est charge dans une carte UNO, il est possible de lancer la sequence en tapant 'g' puis Entree dans la serial console de l'EDI Arduino. +En tapant 'i' puis Entree, l'action InverseLed() est executee. Comme "RcSeq" est asynchrone, il est possible de le faire pendant que les servos tournent. +La possibilite de lancer les sequence et action courte via la serial console evite de sortir et cabler l'ensemble RC pour lancer la sequence et l'action. + +Dans cet exemple, la sequence declaree est la mise a l'eau d'un Zodiac avec une grue depuis un bateau de service type baliseur: +1) La grue souleve le Zodiac en position haute puis s'arrete +2) La grue fait une rotation de 90° pour positionner le Zodiac au dessus de l'eau +3) La grue descend le Zodiac au niveau de l'eau +4) La grue reste sans action pendant 6 secondes +5) La grue remonte le Zodiac en position haute puis s'arrete +6) La grue fait une rotation de 90° pour positionner le Zodiac au dessus du pont +7) La grue descend le Zodiac en position basse puis s'arrete. La sequence est terminee. +Cette sequence utilise: +- 2 commande RC sur le meme manche (Impulsion d'au moins 1/4 de seconde en position mi-course pour l'action courte et extreme pour la sequnce avec le manche de l'emetteur RC) + ou la commande 'i' ou 'g' depuis la serial console de l'EDI Arduino +- 2 servos (un servo "Azimut" pour les rotations et un servo "Elevation" pour la montee/descente) +*/ + +/***************************************************/ +/* ETAPE N°1: Inclure les 4 librairies necessaires */ +/***************************************************/ +#include +#include /* Ne pas oublier d'inclure la librairie qui est utilisee par la librairie */ +#include /* Ne pas oublier d'inclure la librairie qui est utilisee par la librairie */ +#include /* Ne pas oublier d'inclure la librairie qui est utilisee par la librairie */ + +/*****************************************************/ +/* ETAPE N°2: Enumeration des signaux de commande RC */ +/*****************************************************/ +enum {SIGNAL_RC=0, NBR_SIGNAL}; /* Delaration de tous les signaux de commande (sortie voie du recepteur), un seul dans cet exemple */ + +/****************************************************************/ +/* ETAPE N°3: Enumeration des differentes position du manche RC */ +/****************************************************************/ +enum {RC_IMPULSION_NIVEAU_MOINS_2, RC_IMPULSION_NIVEAU_MOINS_1, RC_IMPULSION_NIVEAU_PLUS_1, RC_IMPULSION_NIVEAU_PLUS_2, NBR_RC_IMPULSIONS}; + +/*****************************************************************/ +/* ETAPE N°4: Enumeration des servos utilisés pour les sequences */ +/*****************************************************************/ +enum {AZIMUT=0, ELEVATION , NBR_SERVO}; /* Delaration de tous les servos, 2 dans cet exemple */ + +/*********************************************************************************/ +/* ETAPE N°5: Affectation des broches Digitales (PIN) des signaux de commande RC */ +/*********************************************************************************/ +#define BROCHE_SIGNAL_RECEPTEUR 2 + +/*****************************************************************************************/ +/* ETAPE N°6: Affectation des broches Digitales (PIN) des signaux de commande des servos */ +/*****************************************************************************************/ +#define BROCHE_SIGNAL_SERVO_EL 3 +#define BROCHE_SIGNAL_SERVO_AZ 4 + +/**************************************************************************************/ +/* ETAPE N°7: Declaration des angles des servos pour les differents mouvements (en °) */ +/**************************************************************************************/ +#define ELEVATION_POS_PONT 120 /* position zodiac sur pont (Pos A) */ +#define ELEVATION_POS_HAUT 180 /* position zodiac en haut (Pos B) */ +#define ELEVATION_POS_MER 0 /* position zodiac dans l'eau (pos C) */ + +#define AZIMUT_POS_PONT 90 /* position rotation sur pont */ +#define AZIMUT_POS_MER 0 /* position rotation sur mer */ + + +/***************************************************************************************************************************************/ +/* ETAPE N°8: Faire un croquis temporel faisant apparaitre les moments de demarrages et les duree des mouvements des differents servos */ +/***************************************************************************************************************************************/ +/* +Toutes les valeurs de demarrage ont comme reference le moment de l'ordre de demarrage de sequence (t=0). + + MOUVEMENT SERVO ELEVATION MOUVEMENT SERVO AZIMUT MOUVEMENT SERVO ELEVATION AUCUN MOUVEMENT(ATTENTE) MOUVEMENT SERVO ELEVATION MOUVEMENT SERVO AZIMUT MOUVEMENT SERVO ELEVATION +Ordre <---DUREE_MONTEE_PONT_HAUT_MS--> <--DUREE_ROTATION_PONT_MER_MS----> <--DUREE_DESCENTE_HAUT_MER_MS--><--ATTENTE_AVANT_REMONTEE_MS--><---DUREE_MONTEE_MER_HAUT_MS---><----DUREE_ROTATION_MER_PONT_MS-----><--DUREE_DESCENTE_HAUT_PONT_MS--> + |-------------------|--------------------------------|----------------------------------|--------------------------------|------------------------------|-------------------------------|------------------------------------|--------------------------------|-->Axe du Temps + 0 DEMARRAGE_MONTEE_PONT_HAUT_MS DEMARRAGE_ROTATION_PONT_MER_MS DEMARRAGE_DESCENTE_HAUT_MER_MS DEMARRAGE_MONTEE_MER_HAUT_MS DEMARRAGE_ROTATION_MER_PONT_MS DEMARRAGE_DESCENTE_HAUT_PONT_MS +*/ + +/**************************************************************************************************************************************************/ +/* ETAPE N°9: A l'aide du croquis temporel, declarer les moments de demarrage, les durees des movement de servo et les eventuelles temporisations */ +/**************************************************************************************************************************************************/ +/* Regler ci-dessous les temps de mouvement en ms. Ne pas oulier de d'ajouter un 'L' a la fin de la valeur pour forcer les valeurs en type Long */ +#define DEMARRAGE_MONTEE_PONT_HAUT_MS 0L /* 0 pour demarrage immediat, mais on peut mettre une tempo ici. Ex 2000L, va differer la sequence complete de 2 secondes */ +#define DUREE_MONTEE_PONT_HAUT_MS 3000L + +#define DEMARRAGE_ROTATION_PONT_MER_MS (DEMARRAGE_MONTEE_PONT_HAUT_MS+DUREE_MONTEE_PONT_HAUT_MS) +#define DUREE_ROTATION_PONT_MER_MS 3000L + +#define DEMARRAGE_DESCENTE_HAUT_MER_MS (DEMARRAGE_ROTATION_PONT_MER_MS+DUREE_ROTATION_PONT_MER_MS) +#define DUREE_DESCENTE_HAUT_MER_MS 9000L + +#define ATTENTE_AVANT_REMONTEE_MS 6000L /* Exemple d'utilisation d'une temporisation */ + +#define DEMARRAGE_MONTEE_MER_HAUT_MS (DEMARRAGE_DESCENTE_HAUT_MER_MS+DUREE_DESCENTE_HAUT_MER_MS+ATTENTE_AVANT_REMONTEE_MS) +#define DUREE_MONTEE_MER_HAUT_MS 9000L + +#define DEMARRAGE_ROTATION_MER_PONT_MS (DEMARRAGE_MONTEE_MER_HAUT_MS+DUREE_MONTEE_MER_HAUT_MS) +#define DUREE_ROTATION_MER_PONT_MS 3000L + + +#define DEMARRAGE_DESCENTE_HAUT_PONT_MS (DEMARRAGE_ROTATION_MER_PONT_MS+DUREE_ROTATION_MER_PONT_MS) +#define DUREE_DESCENTE_HAUT_PONT_MS 3000L + +/********************************************************************************************************************/ +/* ETAPE N°10: Declarer le pourcentage de mouvement devant etre a mi-vitesse pour les demarrage et arret des servos */ +/********************************************************************************************************************/ +#define DEM_ARRET_POUR_CENT 5 /* Pourcentage du mouvement devant etre effectue a mi-vitesse pour demarrage servo et arret servo (Soft start et Soft stop) */ + +/***************************************************************************************************************************************************************/ +/* ETAPE N°11: Dans une structure de type "SequenceSt_t", a l'aide de la macro MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS(), declarer le N° de servo, l'angle initial, */ +/* l'angle final, le moment de demarrage, la duree du mouvement et le pourcentage de mouvement devant etre a mi-vitesse pour les demarrage et arret des servos */ +/* Il est possible d'inclure des actions courtes. Il suffit d'utiliser la macro ACTION_COURTE_A_EFFECTUER() en donnant le nom de la fonction a appeler et le */ +/* moment ou l'action doit avoir lieu. Dans cet exemple, la LED s'allume pendant que les servos tournent et s'eteint pendant la pause de 6 secondes. */ +/***************************************************************************************************************************************************************/ +SequenceSt_t SequencePlus2[] PROGMEM = { + ACTION_COURTE_A_EFFECTUER(InverseLed,DEMARRAGE_MONTEE_PONT_HAUT_MS) + /* Montee du Zodiac du pont vers la position haute */ + MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS(ELEVATION,ELEVATION_POS_PONT,ELEVATION_POS_HAUT,DEMARRAGE_MONTEE_PONT_HAUT_MS,DUREE_MONTEE_PONT_HAUT_MS,DEM_ARRET_POUR_CENT) + /* Rotation Grue du pont vers la mer */ + MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS(AZIMUT,AZIMUT_POS_PONT,AZIMUT_POS_MER,DEMARRAGE_ROTATION_PONT_MER_MS,DUREE_ROTATION_PONT_MER_MS,DEM_ARRET_POUR_CENT) + /* Descente du Zodiac depuis la position haute vers la la mer */ + MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS(ELEVATION,ELEVATION_POS_HAUT,ELEVATION_POS_MER,DEMARRAGE_DESCENTE_HAUT_MER_MS,DUREE_DESCENTE_HAUT_MER_MS,DEM_ARRET_POUR_CENT) + ACTION_COURTE_A_EFFECTUER(InverseLed,DEMARRAGE_DESCENTE_HAUT_MER_MS+DUREE_DESCENTE_HAUT_MER_MS) + ACTION_COURTE_A_EFFECTUER(InverseLed,DEMARRAGE_MONTEE_MER_HAUT_MS) + /* Montee du Zodiac de la mer vers la position haute */ + MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS(ELEVATION,ELEVATION_POS_MER,ELEVATION_POS_HAUT,DEMARRAGE_MONTEE_MER_HAUT_MS,DUREE_MONTEE_MER_HAUT_MS,DEM_ARRET_POUR_CENT) + /* Rotation Grue de la mer vers le pont */ + MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS(AZIMUT,AZIMUT_POS_MER,AZIMUT_POS_PONT,DEMARRAGE_ROTATION_MER_PONT_MS,DUREE_ROTATION_MER_PONT_MS,DEM_ARRET_POUR_CENT) + /* Descente du Zodiac de la position haute vers le pont */ + MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS(ELEVATION,ELEVATION_POS_HAUT,ELEVATION_POS_PONT,DEMARRAGE_DESCENTE_HAUT_PONT_MS,DUREE_DESCENTE_HAUT_PONT_MS,DEM_ARRET_POUR_CENT) + ACTION_COURTE_A_EFFECTUER(InverseLed,DEMARRAGE_DESCENTE_HAUT_PONT_MS+DUREE_DESCENTE_HAUT_PONT_MS) + }; + +#define LED 13 + +void setup() +{ + +#if !defined(__AVR_ATtiny24__) && !defined(__AVR_ATtiny44__) && !defined(__AVR_ATtiny84__) && !defined(__AVR_ATtiny25__) && !defined(__AVR_ATtiny45__) && !defined(__AVR_ATtiny85__) + Serial.begin(9600); + Serial.print("RcSeq library V");Serial.print(RcSeq_LibTextVersionRevision());Serial.print(" demo: RcSeqZodiac"); +#endif + +/***************************************************************************/ +/* ETAPE N°12: Appeler la fonction d'initialisation de la libraire "RcSeq" */ +/***************************************************************************/ + RcSeq_Init(); + +/**************************************************************************************/ +/* ETAPE N°13: declarer le(s) signal(aux) de commande RC avec leur N° de pin digitale */ +/**************************************************************************************/ + RcSeq_DeclareSignal(SIGNAL_RC,BROCHE_SIGNAL_RECEPTEUR); + +/******************************************************************************************/ +/* ETAPE N°14: que le signal RC est associe a un manche qui a NBR_RC_IMPULSIONS positions */ +/*****************************************************************************************/ + RcSeq_DeclareManche(SIGNAL_RC, 1000, 2000, NBR_RC_IMPULSIONS); + +/********************************************************************************************/ +/* ETAPE N°15: declarer le(s) signal(aux) ce commande de servo avec leur N° de pin digitale */ +/********************************************************************************************/ + RcSeq_DeclareServo(ELEVATION, BROCHE_SIGNAL_SERVO_EL); + RcSeq_DeclareServo(AZIMUT, BROCHE_SIGNAL_SERVO_AZ); + +/**************************************************************************************************************************/ +/* ETAPE N°16: declarer le signal de commande de sequence, le niveau du manche, et la sequence ou action courte a appeler */ +/**************************************************************************************************************************/ + RcSeq_DeclareCommandeEtSequence(SIGNAL_RC, RC_IMPULSION_NIVEAU_PLUS_2, RC_SEQUENCE(SequencePlus2)); // Voici comment declarer une sequence actionnee par une impulsion Niveau Plus 2 (manche en position extreme pendant au moins 250 ms) + + pinMode(LED, OUTPUT); + RcSeq_DeclareCommandeEtActionCourte(SIGNAL_RC, RC_IMPULSION_NIVEAU_MOINS_1, InverseLed); // Voici comment declarer une action actionnee par une impulsion Niveau Moins 1 (manche en position mi-course pendant au moins 250 ms) +} + +void loop() +{ + +/***********************************************************************************************************************************/ +/* ETAPE N°17: appeler la fonction Rafraichit dans la fonction loop() pour capter les commandes RC et gerer la position des servos */ +/***********************************************************************************************************************************/ + RcSeq_Rafraichit(); + +/******************************************************************************************************/ +/* ETAPE N°18: optionnellement, autoriser le lancement des Sequences ou Actions via la serial console */ +/******************************************************************************************************/ +#if !defined(__AVR_ATtiny24__) && !defined(__AVR_ATtiny44__) && !defined(__AVR_ATtiny84__) && !defined(__AVR_ATtiny25__) && !defined(__AVR_ATtiny45__) && !defined(__AVR_ATtiny85__) +int RxChar; + /* Lance la sequence en envoyant le caractere 'g' dans la serial console: cela permet de tester la sequence de servo avec une carte UNO sans utiliser d'ensemble RC */ + if(Serial.available() > 0) + { + RxChar=Serial.read(); + if(tolower(RxChar)=='g') /* Go ! */ + { + RcSeq_LanceSequence(SequencePlus2); + } + if(tolower(RxChar)=='i') /* inverse led ! */ + { + RcSeq_LanceActionCourte(InverseLed); + } + } +#endif +} + +/* Action associee au manche a mi-course */ +void InverseLed(void) +{ +static boolean Etat=HIGH; /* static, pour conserver l'etat entre 2 appels de la fonction */ + digitalWrite(LED, Etat); + Etat=!Etat; /* AU prochain appel de InverseLed(), l'etat de la LED sera inverse */ +} diff --git a/hardware/digistump/avr/libraries/RcSeq/Examples/UneVoieVers8/UneVoieVers8.ino b/hardware/digistump/avr/libraries/RcSeq/Examples/UneVoieVers8/UneVoieVers8.ino new file mode 100644 index 0000000..0a93a0a --- /dev/null +++ b/hardware/digistump/avr/libraries/RcSeq/Examples/UneVoieVers8/UneVoieVers8.ino @@ -0,0 +1,76 @@ +#include +#include /* Ne pas oublier d'inclure la librairie qui est utilisee par la librairie */ +#include /* Ne pas oublier d'inclure la librairie qui est utilisee par la librairie */ +#include /* Ne pas oublier d'inclure la librairie qui est utilisee par la librairie */ + +/*================= COMMMANDE DE 8 SORTIES ON/OFF PAR 8 INTERS POUSSOIR ======================== + Les 8 relais ou sont connectés aux prise n°1,2,3,4,5,6,7,8 d'un ATtiny84 + La voie du récepteur est connecté à la prise n°0 de l'ATtiny84 + Un appui furtif sur un bouton fait actionne le relais correspondant qui reste collé. + Un deuxième appui furtif sur le même bouton fait décoller le relais correspondant. + Version avec librairie RcSeq d'apres l'exemple de http://bateaux.trucs.free.fr/huit_sorties.html +================================================================================================*/ + +/* Declaration des voies */ +enum {RC_VOIE, NBR_VOIES_RC}; /* Ici, comme il n'y a qu'une voie, on aurait pu faire un simple "#define RC_VOIE 0" a la place de l'enumeration */ + +//============================================================================================== +/* Declaration du signal du recepteur */ +#define BROCHE_SIGNAL_RECEPTEUR_VOIE 0 + +//============================================================================================== +/* Declaration d'un clavier "Maison": les impulsions des Boutons-Poussoirs n'ont pas besoin d'etre equidistantes */ +enum {BP1, BP2, BP3, BP4, BP5, BP6, BP7, BP8, NBR_BP}; +#define TOLERANCE 40 /* Tolerance en + ou en - (en micro-seconde): ATTENTION, il ne doit pas y avoir recouvrement entre 2 zones actives adjascentes. Zone active = 2 x TOLERANCE (us) */ +KeyMap_t ClavierMaison[] PROGMEM ={ {VALEUR_CENTRALE_US(1100,TOLERANCE)}, /* BP1: +/-40 us */ + {VALEUR_CENTRALE_US(1200,TOLERANCE)}, /* BP2: +/-40 us */ + {VALEUR_CENTRALE_US(1300,TOLERANCE)}, /* BP3: +/-40 us */ + {VALEUR_CENTRALE_US(1400,TOLERANCE)}, /* BP4: +/-40 us */ + {VALEUR_CENTRALE_US(1600,TOLERANCE)}, /* BP5: +/-40 us */ + {VALEUR_CENTRALE_US(1700,TOLERANCE)}, /* BP6: +/-40 us */ + {VALEUR_CENTRALE_US(1800,TOLERANCE)}, /* BP7: +/-40 us */ + {VALEUR_CENTRALE_US(1900,TOLERANCE)}, /* BP8: +/-40 us */ + }; + +//============================================================================================== +/* Astuce: une macro pour n'ecrire qu'une seule fois la fonction ActionX() */ +#define DECLARE_ACTION(Idx) \ +void Action##Idx(void) \ +{ \ +static boolean Etat=HIGH; \ + digitalWrite(Idx, Etat); \ + Etat=!Etat; \ +} + +/* Declaration des actions en utilisant la macro DECLARE_ACTION(Idx) avec Idx = le numero de l'action et de la pin (le ##Idx sera remplace automatiquement par la valeur de Idx */ +DECLARE_ACTION(1) +DECLARE_ACTION(2) +DECLARE_ACTION(3) +DECLARE_ACTION(4) +DECLARE_ACTION(5) +DECLARE_ACTION(6) +DECLARE_ACTION(7) +DECLARE_ACTION(8) + +//============================================================================================== +void setup() +{ + RcSeq_Init(); + RcSeq_DeclareSignal(RC_VOIE, BROCHE_SIGNAL_RECEPTEUR_VOIE); + RcSeq_DeclareClavierMaison(RC_VOIE, RC_CLAVIER_MAISON(ClavierMaison)); + RcSeq_DeclareCommandeEtActionCourte(RC_VOIE, BP1, Action1);pinMode(1,OUTPUT); + RcSeq_DeclareCommandeEtActionCourte(RC_VOIE, BP2, Action2);pinMode(2,OUTPUT); + RcSeq_DeclareCommandeEtActionCourte(RC_VOIE, BP3, Action3);pinMode(3,OUTPUT); + RcSeq_DeclareCommandeEtActionCourte(RC_VOIE, BP4, Action4);pinMode(4,OUTPUT); + RcSeq_DeclareCommandeEtActionCourte(RC_VOIE, BP5, Action5);pinMode(5,OUTPUT); + RcSeq_DeclareCommandeEtActionCourte(RC_VOIE, BP6, Action6);pinMode(6,OUTPUT); + RcSeq_DeclareCommandeEtActionCourte(RC_VOIE, BP7, Action7);pinMode(7,OUTPUT); + RcSeq_DeclareCommandeEtActionCourte(RC_VOIE, BP8, Action8);pinMode(8,OUTPUT); +} +//============================================================================================== +void loop() +{ + RcSeq_Rafraichit(); +} +//============================ FIN DU PROGRAMME ================================================= + diff --git a/hardware/digistump/avr/libraries/RcSeq/RcSeq.cpp b/hardware/digistump/avr/libraries/RcSeq/RcSeq.cpp new file mode 100644 index 0000000..596ad18 --- /dev/null +++ b/hardware/digistump/avr/libraries/RcSeq/RcSeq.cpp @@ -0,0 +1,566 @@ +#include "RcSeq.h" +/* + English: by RC Navy (2012/2013) + ======= + is an asynchronous library for ATmega328P (UNO), ATtiny84 and ATtiny85 to easily create servo's sequences and/or to execute short actions from RC commands. + It can also be used to trig some short "actions" (the duration must be less than 20ms to not disturb the servo commands) + The Application Programming Interface (API) makes library very easy to use. + needs 3 other libraries written by the same author: + 1) : a library to catch asynchronously the input change using Pin Change Interruption capability of the AVR + 2) : a library to catch asynchronously the input pulses using library + 3) : a library mainly based on the library, but with a better pulse generation to limit jitter + RC Signals (receiver outputs) can be assigned to a control type: + -Stick Positions (up to 8, but in practice, 4 is the maximum to manually discriminate each stick position) + -Keyboard ( assumes Push-Buttons associated Pulse duration are equidistant) + -Custom Keyboard (The pulse durations can be defined independently for each Push-Button) + Some definitions: + -Sequence: is used to sequence one or several servos (sequence is defined in a structure in the user's sketch to be performed when the RC command rises) + The Sequence table (structure) may contain some servo motions and some short actions to call. + -Short Action: is used to perform a quick action (action is a short function defined in the user's sketch to be called when the RC command rises) + CAUTION: the end user shall also use asynchronous programmation method in the loop() function (no blocking functions such as delay() or pulseIn()). + http://p.loussouarn.free.fr + + Francais: par RC Navy (2012) + ======== + est une librairie asynchrone pour ATmega328P (UNO), ATtiny84 et ATtiny85 pour creer facilement des sequences de servos et/ou executer des actions depuis des commandes RC. + Elle peut egalement etre utilisee pour lancer des "actions courtes" (la duree doit etre inferieure a 20ms pour ne pas perturber la commande des servos) + L'Interface de Programmation d'Application (API) fait que la librairie est tres facile a utiliser. + necessite 3 autres librairies ecrites par le meme auteur: + 1) : une librarie pour capter de maniere asynchrone les changements d'etat des broches utilisant les interruptions sur changement des pins des AVR + 2) : une librarie pour capter de maniere asynchrone les impulsions entrantes en utilisant la librairie + 3) : une librairie majoritairement basee sur la librairie , mais avec une meilleur generation des impulsions pour limiter la gigue + Les signaux RC (sorties du recepteur) peuvent etre associes a un type de controle: + -Positions de Manche (jusqu'a 8, mais en pratique, 4 est le maximum pour discriminer manuellement les positions du manche) + -Clavier ( suppose que les durees d'impulsion des Bouton-Poussoirs sont equidistantes) + -Clavier "Maison" (Les durees d'impulsion peuvent etre definies de manière independante pour chaque Bouton-Poussoir) + Quelques definitions: + -Sequence: est utilisee pour sequencer un ou plusieurs servos (sequence est definie dans une structure dans le sketch utilisateur: est lancee quand la commande RC est recue) + La table de sequence (structure) peut contenir des mouvements de servo et des actions courtes a appeler. + -Action courte: est utilisee pour une action rapide (action est une fonction courte definie dans le sketch utilsateur: est appelee quand la commande RC est recue) + ATTENTION: l'utilisateur final doit egalement utiliser la methode de programmation asynchrone dans la fonction loop() (pas de fonctions bloquantes comme delay() ou pulseIn()). + http://p.loussouarn.free.fr + + ASTUCE: + ====== + + Il est possible de declarer 8 sequences par manche (4 avec la voie du potentiometre vertical et 4 avec la voie du potentiometre horizontal). + Il est possible de lancer 2 sequences en meme temps en utilisant les diagonales (la ou il y a des X dans la figure ci-dessous). + + POSITION MANCHE SUR EMETTEUR + ,---------------------. \ + | X O X | --> RC_IMPULSION_NIVEAU_PLUS_2 | + | | | | + | X O X | --> RC_IMPULSION_NIVEAU_PLUS_1 | + | | | / + | O---O---O---O---O | --> Neutre (Aucune action) > 4 sequences possibles avec le manche vertical + | | | \ + | X O X | --> RC_IMPULSION_NIVEAU_MOINS_1 | + | | | | + | X O X | --> RC_IMPULSION_NIVEAU_MOINS_2 | + '---------------------' / + | | | | | + | | | | | \ + | | | | '------> RC_IMPULSION_NIVEAU_PLUS_2 | + | | | | | + | | | '----------> RC_IMPULSION_NIVEAU_PLUS_1 | + | | | / + | | '--------------> Neutre (Aucune action) > 4 sequences possibles avec le manche horizontal + | | \ + | '------------------> RC_IMPULSION_NIVEAU_MOINS_1 | + | | + '----------------------> RC_IMPULSION_NIVEAU_MOINS_2 | + / +*/ +/************************************************************************* + MACROS +*************************************************************************/ +/* For an easy Library Version Management */ +#define LIB_VERSION 1 +#define LIB_REVISION 0 + +#define STR(s) #s +#define MAKE_TEXT_VER_REV(Ver,Rev) (char*)(STR(Ver)"."STR(Rev)) + +#define LIB_TEXT_VERSION_REVISION MAKE_TEXT_VER_REV(LIB_VERSION,LIB_REVISION) /* Make Full version as a string "Ver.Rev" */ + +/* A Set of Macros for bit manipulation */ +#define SET_BIT(Value,BitIdx) (Value)|= (1<<(BitIdx)) +#define CLR_BIT(Value,BitIdx) (Value)&=~(1<<(BitIdx)) +#define TST_BIT(Value,BitIdx) ((Value)&(1<<(BitIdx))) + +/* Servo refresh interval in ms (do not change this value, this one allows "round" values) */ +#define REFRESH_INTERVAL_MS 20L + +/* A pulse shall be valid during XXXX_PULSE_CHECK_MS before being taken into account */ +#define STICK_PULSE_CHECK_MS 100L +#define KBD_PULSE_CHECK_MS 10L + +/* Duration between 2 consecutive commands */ +#define INTER_CMD_DURATION_MS 1000L + +/* Free servo Indicator */ +#define NO_SEQ_LINE 255 + +/* Free Position Indicator */ +#define NO_POS 255 + +/* The macro below computes how many refresh to perform while a duration in ms */ +#define REFRESH_NB(DurationMs) ((DurationMs)/REFRESH_INTERVAL_MS) + +/* The motion goes from StartInDegrees to EndInDegrees and will take MotionDurationMs in ms */ +#define STEP_IN_DEGREES_PER_REFRESH(StartInDegrees,EndInDegrees,MotionDurationMs) (EndInDegrees-StartInDegrees)/REFRESH_NB(MotionDurationMs) +/* A set of Macros to read an (u)int8_t (Byte), an (u)int16_t (Word) in program memory (Flash memory) */ +#define PGM_READ_8(FlashAddr) pgm_read_byte(&(FlashAddr)) +#define PGM_READ_16(FlashAddr) pgm_read_word(&(FlashAddr)) +#define PGM_READ_32(FlashAddr) pgm_read_dword(&(FlashAddr)) + +/* +STICK TYPE: +========== +Pos 0 1 2 3 + |---|-|---|--|---|-|---| +1000us 2000us (Typical Pulse Width values) +*/ +#define ACTIVE_AREA_STEP_NBR 3 +#define INACTIVE_AREA_STEP_NBR 1 +#define TOTAL_STEP_NBR(KeyNb,Type) ((Type==RC_CMD_STICK)?((KeyNb)*(ACTIVE_AREA_STEP_NBR+INACTIVE_AREA_STEP_NBR)):(((KeyNb)*(ACTIVE_AREA_STEP_NBR+INACTIVE_AREA_STEP_NBR))-1)) +#define STEP(MinUs, MaxUs,KeyNb,Type) ((MaxUs-MinUs)/TOTAL_STEP_NBR(KeyNb,Type)) +#define KEY_MIN_VAL(Idx,Step) ((ACTIVE_AREA_STEP_NBR+INACTIVE_AREA_STEP_NBR)*(Step)*(Idx)) +#define KEY_MAX_VAL(Idx,Step) (KEY_MIN_VAL(Idx,Step)+(ACTIVE_AREA_STEP_NBR*(Step))) + +typedef struct { + int8_t InProgress; + int8_t CmdIdx; + int8_t Pos; + uint32_t StartChronoMs; + void *TableOrShortAction; + uint8_t SequenceLength; + uint8_t ShortActionMap; +}CmdSequenceSt_t; + +#ifdef RC_SEQ_WITH_SOFT_RC_PULSE_IN_SUPPORT +typedef struct { + int8_t Idx; + uint32_t StartChronoMs; +}PosST_t; + +typedef struct { + SoftRcPulseIn Pulse; + PosST_t Pos; + uint8_t Type; /* RC_CMD_STICK or RC_CMD_KEYBOARD or RC_CMD_CUSTOM */ + uint8_t PosNb; + uint16_t PulseMinUs; + uint16_t PulseMaxUs; + uint16_t StepUs; + KeyMap_t *KeyMap; +}RcCmdSt_t; +#endif + +typedef struct { + SoftRcPulseOut Motor; + uint16_t RefreshNb; /* Used to store the number of refresh to perform during a servo motion (if not 0 -> Motion in progress) */ + uint8_t SeqLineInProgress; +}ServoSt_t; +/************************************************************************* + GLOBAL VARIABLES +*************************************************************************/ +static uint8_t SeqNb; +static uint8_t ServoNb; +#ifdef RC_SEQ_WITH_SOFT_RC_PULSE_IN_SUPPORT +static uint8_t CmdSignalNb; +static RcCmdSt_t RcChannel[RC_CMD_MAX_NB]; +#endif +#ifdef RC_SEQ_WITH_STATIC_MEM_ALLOC_SUPPORT +#define AsMember . +static ServoSt_t Servo[SERVO_MAX_NB]; +static CmdSequenceSt_t CmdSequence[SEQUENCE_MAX_NB]; +#else +#define AsMember -> +static ServoSt_t **Servo=NULL; +static CmdSequenceSt_t **CmdSequence=NULL; +#endif +/************************************************************************* + PRIVATE FUNCTION PROTOTYPES +*************************************************************************/ +static void ExecuteSequence(uint8_t CmdIdx, uint8_t Pos); +#ifndef RC_SEQ_WITH_STATIC_MEM_ALLOC_SUPPORT +static void LoadSequenceOrShortAction(uint8_t CmdIdx,uint8_t Pos,void *SequenceOrShortAction, uint8_t SequenceLength); +#endif +#ifdef RC_SEQ_WITH_SOFT_RC_PULSE_IN_SUPPORT +static int8_t GetPos(uint8_t ChIdx,uint16_t PulseWidthUs); +#endif + +//======================================================================================================================== +void RcSeq_Init(void) +{ + SeqNb=0; + ServoNb=0; +#ifdef RC_SEQ_WITH_SOFT_RC_PULSE_IN_SUPPORT + for(uint8_t ChIdx=0;ChIdx=0) + { + if(RcChannel[ChIdx].Pos.Idx!=CmdPos) + { + if((millis()-RcChannel[ChIdx].Pos.StartChronoMs)>=INTER_CMD_DURATION_MS) /* Check the last command was received for at least 1 second */ + { + RcChannel[ChIdx].Pos.Idx=CmdPos; + RcChannel[ChIdx].Pos.StartChronoMs=millis(); + } + } + else + { + if((millis()-RcChannel[ChIdx].Pos.StartChronoMs)>=((RcChannel[ChIdx].Type==RC_CMD_STICK)?STICK_PULSE_CHECK_MS:KBD_PULSE_CHECK_MS)) /* Check the Pulse is valid at least for 100 ms or 50 ms */ + { + ExecuteSequence(ChIdx,CmdPos); + RcChannel[ChIdx].Pos.Idx=NO_POS; + } + } + } + else + { + RcChannel[ChIdx].Pos.Idx=NO_POS; + } + } +#endif + NowMs=millis(); + if((NowMs - StartChronoInterPulseMs) >= 20L) + { + /* We arrive here every 20 ms */ + /* Asynchronous Servo Sequence management */ + for(int8_t Idx=0;Idx=StartOfSeqMs) && !TST_BIT(CmdSequence[Idx] AsMember ShortActionMap,ShortActionCnt) ) + { + ShortAction=(void(*)(void))PGM_READ_16(SequenceTable[SeqLine].ShortAction); + ShortAction(); + SET_BIT(CmdSequence[Idx] AsMember ShortActionMap,ShortActionCnt); /* Mark short Action as performed */ + /* If the last line contains an Action AsMember End of Sequence */ + if(SeqLine==(CmdSequence[Idx] AsMember SequenceLength-1)) + { + CmdSequence[Idx] AsMember InProgress=0; + CmdSequence[Idx] AsMember ShortActionMap=0; /* Mark all Short Action as not performed */ + } + } + continue; + } +#endif + if(Servo[ServoIdx] AsMember RefreshNb && SeqLine!=Servo[ServoIdx] AsMember SeqLineInProgress) + { + continue; + } + StartOfSeqMs = CmdSequence[Idx] AsMember StartChronoMs + (int32_t)PGM_READ_32(SequenceTable[SeqLine].StartMotionOffsetMs); + MotionDurationMs = (int32_t)PGM_READ_32(SequenceTable[SeqLine].MotionDurationMs); + EndOfSeqMs = StartOfSeqMs + MotionDurationMs; + if(!Servo[ServoIdx] AsMember RefreshNb && Servo[ServoIdx] AsMember SeqLineInProgress==NO_SEQ_LINE) + { + if( (NowMs>=StartOfSeqMs) && (NowMs<=EndOfSeqMs) ) + { + Servo[ServoIdx] AsMember SeqLineInProgress=SeqLine; + StartInDegrees=(uint16_t)PGM_READ_8(SequenceTable[SeqLine].StartInDegrees); + Servo[ServoIdx] AsMember RefreshNb=REFRESH_NB(MotionDurationMs); + Servo[ServoIdx] AsMember Motor.write(StartInDegrees); + } + } + else + { + /* A sequence line is in progress: update the next position */ + if(Servo[ServoIdx] AsMember RefreshNb) Servo[ServoIdx] AsMember RefreshNb--; + StartInDegrees=(uint16_t)PGM_READ_8(SequenceTable[SeqLine].StartInDegrees); + EndInDegrees=(uint16_t)PGM_READ_8(SequenceTable[SeqLine].EndInDegrees); + Pos=(int32_t)EndInDegrees-((int32_t)Servo[ServoIdx] AsMember RefreshNb*STEP_IN_DEGREES_PER_REFRESH((int32_t)StartInDegrees,(int32_t)EndInDegrees,(int32_t)MotionDurationMs)); //For refresh max nb, Pos = StartInDegrees + Servo[ServoIdx] AsMember Motor.write(Pos); + if( !Servo[ServoIdx] AsMember RefreshNb ) + { + Servo[ServoIdx] AsMember SeqLineInProgress=NO_SEQ_LINE; + /* Last servo motion and refresh = 0 -> End of Sequence */ + if(SeqLine==(CmdSequence[Idx] AsMember SequenceLength-1)) + { + CmdSequence[Idx] AsMember InProgress=0; + CmdSequence[Idx] AsMember ShortActionMap=0; /* Mark all Short Action as not performed */ + } + } + } + } + } + SoftRcPulseOut::refresh(1); /* Force Refresh */ + StartChronoInterPulseMs=millis(); + } +} + +//======================================================================================================================== +// PRIVATE FUNCTIONS +//======================================================================================================================== +static void ExecuteSequence(uint8_t CmdIdx, uint8_t Pos) +{ +void(*ShortAction)(void); +uint8_t Idx; + + for(Idx=0;Idx=PulseMinUs) && (PulseWidthUs<=PulseMaxUs)) + { + Ret=Idx; + break; + } + } + return(Ret); +} +#endif +//======================================================================================================================== diff --git a/hardware/digistump/avr/libraries/RcSeq/RcSeq.h b/hardware/digistump/avr/libraries/RcSeq/RcSeq.h new file mode 100644 index 0000000..93dbe8d --- /dev/null +++ b/hardware/digistump/avr/libraries/RcSeq/RcSeq.h @@ -0,0 +1,171 @@ +#ifndef RC_SEQ_H +#define RC_SEQ_H + +/* + English: by RC Navy (2012) + ======= + is an asynchronous library for ATmega328P (UNO), ATtiny84 and ATtiny85 to easily create servo's sequences and/or to execute short actions from RC commands. + It can also be used to trig some short "actions" (the duration must be less than 20ms to not disturb the servo commands) + The Application Programming Interface (API) makes library very easy to use. + needs 3 other libraries written by the same author: + 1) : a library to catch asynchronously the input change using Pin Change Interruption capability of the AVR + 2) : a library to catch asynchronously the input pulses using library + 3) : a library mainly based on the library, but with a better pulse generation to limit jitter + RC Signals (receiver outputs) can be assigned to a control type: + -Stick Positions (up to 8, but in practice, 4 is the maximum to manually discriminate each stick position) + -Keyboard ( assumes Push-Buttons associated Pulse duration are equidistant) + -Custom Keyboard (The pulse durations can be defined independently for each Push-Button) + Some definitions: + -Sequence: is used to sequence one or several servos (sequence is defined in a structure in the user's sketch to be performed when the RC command rises) + The Sequence table (structure) may contain some servo motions and some short actions to call. + -Short Action: is used to perform a quick action (action is a short function defined in the user's sketch to be called when the RC command rises) + CAUTION: the end user shall also use asynchronous programmation method in the loop() function (no blocking functions such as delay() or pulseIn()). + http://p.loussouarn.free.fr + + Francais: par RC Navy (2012) + ======== + est une librairie asynchrone pour ATmega328P (UNO), ATtiny84 et ATtiny85 pour creer facilement des sequences de servos et/ou executer des actions depuis des commandes RC. + Elle peut egalement etre utilisee pour lancer des "actions courtes" (la duree doit etre inferieure a 20ms pour ne pas perturber la commande des servos) + L'Interface de Programmation d'Application (API) fait que la librairie est tres facile a utiliser. + necessite 3 autres librairies ecrites par le meme auteur: + 1) : une librarie pour capter de maniere asynchrone les changements d'etat des broches utilisant les interruptions sur changement des pins des AVR + 2) : une librarie pour capter de maniere asynchrone les impulsions entrantes en utilisant la librairie + 3) : une librairie majoritairement basee sur la librairie , mais avec une meilleur generation des impulsions pour limiter la gigue + Les signaux RC (sorties du recepteur) peuvent etre associes a un type de controle: + -Positions de Manche (jusqu'a 8, mais en pratique, 4 est le maximum pour discriminer manuellement les positions du manche) + -Clavier ( suppose que les durees d'impulsion des Bouton-Poussoirs sont equidistantes) + -Clavier "Maison" (Les durees d'impulsion peuvent etre definies de manière independante pour chaque Bouton-Poussoir) + Quelques definitions: + -Sequence: est utilisee pour sequencer un ou plusieurs servos (sequence est definie dans une structure dans le sketch utilisateur: est lancee quand la commande RC est recue) + La table de sequence (structure) peut contenir des mouvements de servo et des actions courtes a appeler. + -Action courte: est utilisee pour une action rapide (action est une fonction courte definie dans le sketch utilsateur: est appelee quand la commande RC est recue) + ATTENTION: l'utilisateur final doit egalement utiliser la methode de programmation asynchrone dans la fonction loop() (pas de fonctions bloquantes comme delay() ou pulseIn()). + http://p.loussouarn.free.fr +*/ +/**********************************************/ +/* RCSEQ LIBRARY CONFIGURATION */ +/**********************************************/ +//#define RC_SEQ_WITH_SOFT_RC_PULSE_IN_SUPPORT /* Comment this line if you use library in your sketch */ +#define RC_SEQ_WITH_SHORT_ACTION_SUPPORT /* This allows to put call to short action in sequence table */ + + + +/**********************************************/ +/* /!\ Do not touch below /!\ */ +/**********************************************/ +#define RC_SEQ_WITH_STATIC_MEM_ALLOC_SUPPORT /* Do NOT comment this line for DigiSpark */ + +#ifdef RC_SEQ_WITH_SOFT_RC_PULSE_IN_SUPPORT +#include +#include +#else +#warning RC_SEQ_WITH_SOFT_RC_PULSE_IN_SUPPORT disabled: no RC command possible!!! +#endif +#ifndef RC_SEQ_WITH_SHORT_ACTION_SUPPORT +#warning RC_SEQ_WITH_SHORT_ACTION_SUPPORT disabled: no short action possible!!! +#endif +#include + +#if defined(ARDUINO) && ARDUINO >= 100 +#include "Arduino.h" +#else +#include "WProgram.h" +#endif + +#include +#include + +#ifdef RC_SEQ_WITH_SOFT_RC_PULSE_IN_SUPPORT +#define SERVO_MAX_NB 10 +#define SEQUENCE_MAX_NB 8 +#define RC_CMD_MAX_NB 4 +#else +#define SERVO_MAX_NB 3 /* 3 is the maximum for DigiSpark if DigiUSB is used in the skecth */ +#define SEQUENCE_MAX_NB 1 /* 1 is the maximum for DigiSpark if DigiUSB is used in the skecth */ +#define RC_CMD_MAX_NB 0 +#endif + +typedef struct { + uint8_t ServoIndex; + uint8_t StartInDegrees; + uint8_t EndInDegrees; + uint32_t StartMotionOffsetMs; + uint32_t MotionDurationMs; + void (*ShortAction)(void); +}SequenceSt_t; + +typedef struct { + uint16_t Min; + uint16_t Max; +} KeyMap_t; + +#define TABLE_ITEM_NBR(Tbl) (sizeof(Tbl)/sizeof(Tbl[0])) + +/* Macro to declare a motion WITH soft start and soft stop (to use in "Sequence[]" structure table) */ +#define MOTION_WITH_SOFT_START_AND_STOP(ServoIndex,StartInDegrees,EndInDegrees,StartMvtOffsetMs,MvtDurationMs,PourCent) \ + {(ServoIndex), (StartInDegrees), (StartInDegrees+((EndInDegrees-StartInDegrees)*PourCent)/100L), (StartMvtOffsetMs), ((MvtDurationMs*2L*PourCent)/100L), NULL }, \ + {(ServoIndex), (StartInDegrees+((EndInDegrees-StartInDegrees)*PourCent)/100L), (EndInDegrees-((EndInDegrees-StartInDegrees)*PourCent)/100L), (StartMvtOffsetMs+(MvtDurationMs*2L*PourCent)/100L), ((MvtDurationMs*(100L-4L*PourCent))/100L), NULL }, \ + {(ServoIndex), (EndInDegrees-((EndInDegrees-StartInDegrees)*PourCent)/100L), (EndInDegrees), ((StartMvtOffsetMs+(MvtDurationMs*2L*PourCent)/100L)+(MvtDurationMs*(100L-4L*PourCent))/100L), ((MvtDurationMs*2L*PourCent)/100L), NULL }, + +/* Macro to declare a motion WITHOUT soft start and soft stop (to use in "Sequence[]" structure table) */ +#define MOTION_WITHOUT_SOFT_START_AND_STOP(ServoIndex,StartInDegrees,EndInDegrees,StartMvtOffsetMs,MvtDurationMs) \ + {ServoIndex, StartInDegrees, EndInDegrees, StartMvtOffsetMs, MvtDurationMs, NULL}, + +/* Macro to declare a short action (to use in "Sequence[]" structure table) */ +#define SHORT_ACTION_TO_PERFORM(ShortAction, StartActionOffsetMs) {255, 0, 0, (StartActionOffsetMs), 0L, (ShortAction)}, + +enum {RC_CMD_STICK=0, RC_CMD_KEYBOARD, RC_CMD_CUSTOM}; + +#define RC_SEQUENCE(Sequence) Sequence, TABLE_ITEM_NBR(Sequence) +#define RC_CUSTOM_KEYBOARD(KeyMap) KeyMap, TABLE_ITEM_NBR(KeyMap) + +#define CENTER_VALUE_US(CenterVal,Tol) ((CenterVal)-(Tol)),((CenterVal)+(Tol)) + +void RcSeq_Init(void); +uint8_t RcSeq_LibVersion(void); +uint8_t RcSeq_LibRevision(void); +char *RcSeq_LibTextVersionRevision(void); +void RcSeq_DeclareServo(uint8_t Idx, uint8_t DigitalPin); +#ifdef RC_SEQ_WITH_SOFT_RC_PULSE_IN_SUPPORT +void RcSeq_DeclareSignal(uint8_t Idx, uint8_t DigitalPin); +void RcSeq_DeclareKeyboardOrStickOrCustom(uint8_t ChIdx, uint8_t Type, uint16_t PulseMinUs, uint16_t PulseMaxUs, KeyMap_t *KeyMapTbl, uint8_t PosNb); +void RcSeq_DeclareCustomKeyboard(uint8_t ChIdx, KeyMap_t *KeyMapTbl, uint8_t PosNb); +#define RcSeq_DeclareStick(ChIdx, PulseMinUs, PulseMaxUs, PosNb) RcSeq_DeclareKeyboardOrStickOrCustom(ChIdx, RC_CMD_STICK, PulseMinUs, PulseMaxUs, NULL, PosNb) +#define RcSeq_DeclareKeyboard(ChIdx, PulseMinUs, PulseMaxUs, KeyNb) RcSeq_DeclareKeyboardOrStickOrCustom(ChIdx, RC_CMD_KEYBOARD, PulseMinUs, PulseMaxUs, NULL, KeyNb) +#ifdef RC_SEQ_WITH_SHORT_ACTION_SUPPORT +void RcSeq_DeclareCommandAndShortAction(uint8_t CmdIdx,uint8_t TypeCmd,void(*ShortAction)(void)); +#endif +#endif +void RcSeq_DeclareCommandAndSequence(uint8_t CmdIdx,uint8_t TypeCmd,SequenceSt_t *Table, uint8_t SequenceLength); +uint8_t RcSeq_LaunchSequence(SequenceSt_t *Table); +#ifdef RC_SEQ_WITH_SHORT_ACTION_SUPPORT +#define RcSeq_LaunchShortAction(ShortAction) if(ShortAction) ShortAction() +#endif +void RcSeq_Refresh(void); + +/*******************************************************/ +/* Application Programming Interface (API) en Francais */ +/*******************************************************/ + +/* Macro en Francais de declaration mouvement English native Macro to declare a motion */ +#define MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS MOTION_WITH_SOFT_START_AND_STOP +#define MVT_SANS_DEBUT_ET_FIN_MVT_LENTS MOTION_WITHOUT_SOFT_START_AND_STOP +#define ACTION_COURTE_A_EFFECTUER SHORT_ACTION_TO_PERFORM +#ifdef RC_SEQ_WITH_SOFT_RC_PULSE_IN_SUPPORT +#define RC_CLAVIER_MAISON RC_CUSTOM_KEYBOARD +#define VALEUR_CENTRALE_US CENTER_VALUE_US +#endif + +/* Methodes en Francais English native methods */ +#ifdef RC_SEQ_WITH_SOFT_RC_PULSE_IN_SUPPORT +#define RcSeq_DeclareManche RcSeq_DeclareStick +#define RcSeq_DeclareClavier RcSeq_DeclareKeyboard +#define RcSeq_DeclareClavierMaison RcSeq_DeclareCustomKeyboard +#define RcSeq_DeclareCommandeEtActionCourte RcSeq_DeclareCommandAndShortAction +#endif +#define RcSeq_DeclareCommandeEtSequence RcSeq_DeclareCommandAndSequence +#define RcSeq_LanceSequence RcSeq_LaunchSequence +#define RcSeq_LanceActionCourte RcSeq_LaunchShortAction +#define RcSeq_Rafraichit RcSeq_Refresh + +#endif diff --git a/hardware/digistump/avr/libraries/RcSeq/keywords.txt b/hardware/digistump/avr/libraries/RcSeq/keywords.txt new file mode 100644 index 0000000..2a3b465 --- /dev/null +++ b/hardware/digistump/avr/libraries/RcSeq/keywords.txt @@ -0,0 +1,51 @@ +############################################ +# Syntax Coloring Map RcSeq +############################################ + +############################################ +# Datatypes (KEYWORD1) +############################################ +RcSeq KEYWORD1 + +############################################ +# Methods and Functions (KEYWORD2) +############################################ +RcSeq_LibVersion KEYWORD2 +RcSeq_LibRevision KEYWORD2 +RcSeq_LibTextVersionRevision KEYWORD2 +RcSeq_Init KEYWORD2 +RcSeq_DeclareSignal KEYWORD2 +RcSeq_DeclareKeyboard KEYWORD2 +RcSeq_DeclareClavier KEYWORD2 +RcSeq_DeclareStick KEYWORD2 +RcSeq_DeclareManche KEYWORD2 +RcSeq_DeclareServo KEYWORD2 +RcSeq_DeclareCustomKeyboard KEYWORD2 +RcSeq_DeclareClavierMaison KEYWORD2 +RcSeq_DeclareCommandAndSequence KEYWORD2 +RcSeq_DeclareCommandeEtSequence KEYWORD2 +RcSeq_DeclareCommandAndShortAction KEYWORD2 +RcSeq_DeclareCommandeEtActionCourte KEYWORD2 +RcSeq_LaunchSequence KEYWORD2 +RcSeq_LanceSequence KEYWORD2 +RcSeq_LaunchShortAction KEYWORD2 +RcSeq_LanceActionCourte KEYWORD2 +RcSeq_Refresh KEYWORD2 +RcSeq_Rafraichit KEYWORD2 + +############################################ +# Constants (LITERAL1) +############################################ +SequenceSt_t LITERAL1 +KeyMap_t LITERAL1 +SHORT_ACTION_TO_PERFORM LITERAL1 +ACTION_COURTE_A_EFFECTUER LITERAL1 +MOTION_WITH_SOFT_START_AND_STOP LITERAL1 +MOTION_WITHOUT_SOFT_START_AND_STOP LITERAL1 +MVT_AVEC_DEBUT_ET_FIN_MVT_LENTS LITERAL1 +MVT_SANS_DEBUT_ET_FIN_MVT_LENTS LITERAL1 +RC_CUSTOM_KEYBOARD LITERAL1 +RC_CLAVIER_MAISON LITERAL1 +RC_SEQUENCE LITERAL1 +CENTER_VALUE_US LITERAL1 +VALEUR_CENTRALE_US LITERAL1 diff --git a/hardware/digistump/avr/libraries/SPI/SPI.cpp b/hardware/digistump/avr/libraries/SPI/SPI.cpp new file mode 100644 index 0000000..5e48073 --- /dev/null +++ b/hardware/digistump/avr/libraries/SPI/SPI.cpp @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2010 by Cristian Maglie + * SPI Master library for arduino. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of either the GNU General Public License version 2 + * or the GNU Lesser General Public License version 2.1, both as + * published by the Free Software Foundation. + */ + +#include "pins_arduino.h" +#include "SPI.h" + +SPIClass SPI; + +void SPIClass::begin() { + + // Set SS to high so a connected chip will be "deselected" by default + digitalWrite(SS, HIGH); + + // When the SS pin is set as OUTPUT, it can be used as + // a general purpose output port (it doesn't influence + // SPI operations). + pinMode(SS, OUTPUT); + + // Warning: if the SS pin ever becomes a LOW INPUT then SPI + // automatically switches to Slave, so the data direction of + // the SS pin MUST be kept as OUTPUT. + SPCR |= _BV(MSTR); + SPCR |= _BV(SPE); + + // Set direction register for SCK and MOSI pin. + // MISO pin automatically overrides to INPUT. + // By doing this AFTER enabling SPI, we avoid accidentally + // clocking in a single bit since the lines go directly + // from "input" to SPI control. + // http://code.google.com/p/arduino/issues/detail?id=888 + pinMode(SCK, OUTPUT); + pinMode(MOSI, OUTPUT); +} + + +void SPIClass::end() { + SPCR &= ~_BV(SPE); +} + +void SPIClass::setBitOrder(uint8_t bitOrder) +{ + if(bitOrder == LSBFIRST) { + SPCR |= _BV(DORD); + } else { + SPCR &= ~(_BV(DORD)); + } +} + +void SPIClass::setDataMode(uint8_t mode) +{ + SPCR = (SPCR & ~SPI_MODE_MASK) | mode; +} + +void SPIClass::setClockDivider(uint8_t rate) +{ + SPCR = (SPCR & ~SPI_CLOCK_MASK) | (rate & SPI_CLOCK_MASK); + SPSR = (SPSR & ~SPI_2XCLOCK_MASK) | ((rate >> 2) & SPI_2XCLOCK_MASK); +} + diff --git a/hardware/digistump/avr/libraries/SPI/SPI.h b/hardware/digistump/avr/libraries/SPI/SPI.h new file mode 100644 index 0000000..f647d5c --- /dev/null +++ b/hardware/digistump/avr/libraries/SPI/SPI.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2010 by Cristian Maglie + * SPI Master library for arduino. + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of either the GNU General Public License version 2 + * or the GNU Lesser General Public License version 2.1, both as + * published by the Free Software Foundation. + */ + +#ifndef _SPI_H_INCLUDED +#define _SPI_H_INCLUDED + +#include +#include +#include + +#define SPI_CLOCK_DIV4 0x00 +#define SPI_CLOCK_DIV16 0x01 +#define SPI_CLOCK_DIV64 0x02 +#define SPI_CLOCK_DIV128 0x03 +#define SPI_CLOCK_DIV2 0x04 +#define SPI_CLOCK_DIV8 0x05 +#define SPI_CLOCK_DIV32 0x06 +//#define SPI_CLOCK_DIV64 0x07 + +#define SPI_MODE0 0x00 +#define SPI_MODE1 0x04 +#define SPI_MODE2 0x08 +#define SPI_MODE3 0x0C + +#define SPI_MODE_MASK 0x0C // CPOL = bit 3, CPHA = bit 2 on SPCR +#define SPI_CLOCK_MASK 0x03 // SPR1 = bit 1, SPR0 = bit 0 on SPCR +#define SPI_2XCLOCK_MASK 0x01 // SPI2X = bit 0 on SPSR + +class SPIClass { +public: + inline static byte transfer(byte _data); + + // SPI Configuration methods + + inline static void attachInterrupt(); + inline static void detachInterrupt(); // Default + + static void begin(); // Default + static void end(); + + static void setBitOrder(uint8_t); + static void setDataMode(uint8_t); + static void setClockDivider(uint8_t); +}; + +extern SPIClass SPI; + +byte SPIClass::transfer(byte _data) { + SPDR = _data; + while (!(SPSR & _BV(SPIF))) + ; + return SPDR; +} + +void SPIClass::attachInterrupt() { + SPCR |= _BV(SPIE); +} + +void SPIClass::detachInterrupt() { + SPCR &= ~_BV(SPIE); +} + +#endif diff --git a/hardware/digistump/avr/libraries/SPI/examples/BarometricPressureSensor/BarometricPressureSensor.ino b/hardware/digistump/avr/libraries/SPI/examples/BarometricPressureSensor/BarometricPressureSensor.ino new file mode 100644 index 0000000..8104fcb --- /dev/null +++ b/hardware/digistump/avr/libraries/SPI/examples/BarometricPressureSensor/BarometricPressureSensor.ino @@ -0,0 +1,143 @@ +/* + SCP1000 Barometric Pressure Sensor Display + + Shows the output of a Barometric Pressure Sensor on a + Uses the SPI library. For details on the sensor, see: + http://www.sparkfun.com/commerce/product_info.php?products_id=8161 + http://www.vti.fi/en/support/obsolete_products/pressure_sensors/ + + This sketch adapted from Nathan Seidle's SCP1000 example for PIC: + http://www.sparkfun.com/datasheets/Sensors/SCP1000-Testing.zip + + Circuit: + SCP1000 sensor attached to pins 6, 7, 10 - 13: + DRDY: pin 6 + CSB: pin 7 + MOSI: pin 11 + MISO: pin 12 + SCK: pin 13 + + created 31 July 2010 + modified 14 August 2010 + by Tom Igoe + */ + +// the sensor communicates using SPI, so include the library: +#include + +//Sensor's memory register addresses: +const int PRESSURE = 0x1F; //3 most significant bits of pressure +const int PRESSURE_LSB = 0x20; //16 least significant bits of pressure +const int TEMPERATURE = 0x21; //16 bit temperature reading +const byte READ = 0b11111100; // SCP1000's read command +const byte WRITE = 0b00000010; // SCP1000's write command + +// pins used for the connection with the sensor +// the other you need are controlled by the SPI library): +const int dataReadyPin = 6; +const int chipSelectPin = 7; + +void setup() { + Serial.begin(9600); + + // start the SPI library: + SPI.begin(); + + // initalize the data ready and chip select pins: + pinMode(dataReadyPin, INPUT); + pinMode(chipSelectPin, OUTPUT); + + //Configure SCP1000 for low noise configuration: + writeRegister(0x02, 0x2D); + writeRegister(0x01, 0x03); + writeRegister(0x03, 0x02); + // give the sensor time to set up: + delay(100); +} + +void loop() { + //Select High Resolution Mode + writeRegister(0x03, 0x0A); + + // don't do anything until the data ready pin is high: + if (digitalRead(dataReadyPin) == HIGH) { + //Read the temperature data + int tempData = readRegister(0x21, 2); + + // convert the temperature to celsius and display it: + float realTemp = (float)tempData / 20.0; + Serial.print("Temp[C]="); + Serial.print(realTemp); + + + //Read the pressure data highest 3 bits: + byte pressure_data_high = readRegister(0x1F, 1); + pressure_data_high &= 0b00000111; //you only needs bits 2 to 0 + + //Read the pressure data lower 16 bits: + unsigned int pressure_data_low = readRegister(0x20, 2); + //combine the two parts into one 19-bit number: + long pressure = ((pressure_data_high << 16) | pressure_data_low) / 4; + + // display the temperature: + Serial.println("\tPressure [Pa]=" + String(pressure)); + } +} + +//Read from or write to register from the SCP1000: +unsigned int readRegister(byte thisRegister, int bytesToRead ) { + byte inByte = 0; // incoming byte from the SPI + unsigned int result = 0; // result to return + Serial.print(thisRegister, BIN); + Serial.print("\t"); + // SCP1000 expects the register name in the upper 6 bits + // of the byte. So shift the bits left by two bits: + thisRegister = thisRegister << 2; + // now combine the address and the command into one byte + byte dataToSend = thisRegister & READ; + Serial.println(thisRegister, BIN); + // take the chip select low to select the device: + digitalWrite(chipSelectPin, LOW); + // send the device the register you want to read: + SPI.transfer(dataToSend); + // send a value of 0 to read the first byte returned: + result = SPI.transfer(0x00); + // decrement the number of bytes left to read: + bytesToRead--; + // if you still have another byte to read: + if (bytesToRead > 0) { + // shift the first byte left, then get the second byte: + result = result << 8; + inByte = SPI.transfer(0x00); + // combine the byte you just got with the previous one: + result = result | inByte; + // decrement the number of bytes left to read: + bytesToRead--; + } + // take the chip select high to de-select: + digitalWrite(chipSelectPin, HIGH); + // return the result: + return(result); +} + + +//Sends a write command to SCP1000 + +void writeRegister(byte thisRegister, byte thisValue) { + + // SCP1000 expects the register address in the upper 6 bits + // of the byte. So shift the bits left by two bits: + thisRegister = thisRegister << 2; + // now combine the register address and the command into one byte: + byte dataToSend = thisRegister | WRITE; + + // take the chip select low to select the device: + digitalWrite(chipSelectPin, LOW); + + SPI.transfer(dataToSend); //Send register location + SPI.transfer(thisValue); //Send value to record into register + + // take the chip select high to de-select: + digitalWrite(chipSelectPin, HIGH); +} + diff --git a/hardware/digistump/avr/libraries/SPI/examples/DigitalPotControl/DigitalPotControl.ino b/hardware/digistump/avr/libraries/SPI/examples/DigitalPotControl/DigitalPotControl.ino new file mode 100644 index 0000000..b135a74 --- /dev/null +++ b/hardware/digistump/avr/libraries/SPI/examples/DigitalPotControl/DigitalPotControl.ino @@ -0,0 +1,71 @@ +/* + Digital Pot Control + + This example controls an Analog Devices AD5206 digital potentiometer. + The AD5206 has 6 potentiometer channels. Each channel's pins are labeled + A - connect this to voltage + W - this is the pot's wiper, which changes when you set it + B - connect this to ground. + + The AD5206 is SPI-compatible,and to command it, you send two bytes, + one with the channel number (0 - 5) and one with the resistance value for the + channel (0 - 255). + + The circuit: + * All A pins of AD5206 connected to +5V + * All B pins of AD5206 connected to ground + * An LED and a 220-ohm resisor in series connected from each W pin to ground + * CS - to digital pin 10 (SS pin) + * SDI - to digital pin 11 (MOSI pin) + * CLK - to digital pin 13 (SCK pin) + + created 10 Aug 2010 + by Tom Igoe + + Thanks to Heather Dewey-Hagborg for the original tutorial, 2005 + +*/ + + +// inslude the SPI library: +#include + + +// set pin 10 as the slave select for the digital pot: +const int slaveSelectPin = 10; + +void setup() { + // set the slaveSelectPin as an output: + pinMode (slaveSelectPin, OUTPUT); + // initialize SPI: + SPI.begin(); +} + +void loop() { + // go through the six channels of the digital pot: + for (int channel = 0; channel < 6; channel++) { + // change the resistance on this channel from min to max: + for (int level = 0; level < 255; level++) { + digitalPotWrite(channel, level); + delay(10); + } + // wait a second at the top: + delay(100); + // change the resistance on this channel from max to min: + for (int level = 0; level < 255; level++) { + digitalPotWrite(channel, 255 - level); + delay(10); + } + } + +} + +void digitalPotWrite(int address, int value) { + // take the SS pin low to select the chip: + digitalWrite(slaveSelectPin, LOW); + // send in the address and value via SPI: + SPI.transfer(address); + SPI.transfer(value); + // take the SS pin high to de-select the chip: + digitalWrite(slaveSelectPin, HIGH); +} diff --git a/hardware/digistump/avr/libraries/SPI/keywords.txt b/hardware/digistump/avr/libraries/SPI/keywords.txt new file mode 100644 index 0000000..fa76165 --- /dev/null +++ b/hardware/digistump/avr/libraries/SPI/keywords.txt @@ -0,0 +1,36 @@ +####################################### +# Syntax Coloring Map SPI +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +SPI KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### +begin KEYWORD2 +end KEYWORD2 +transfer KEYWORD2 +setBitOrder KEYWORD2 +setDataMode KEYWORD2 +setClockDivider KEYWORD2 + + +####################################### +# Constants (LITERAL1) +####################################### +SPI_CLOCK_DIV4 LITERAL1 +SPI_CLOCK_DIV16 LITERAL1 +SPI_CLOCK_DIV64 LITERAL1 +SPI_CLOCK_DIV128 LITERAL1 +SPI_CLOCK_DIV2 LITERAL1 +SPI_CLOCK_DIV8 LITERAL1 +SPI_CLOCK_DIV32 LITERAL1 +SPI_CLOCK_DIV64 LITERAL1 +SPI_MODE0 LITERAL1 +SPI_MODE1 LITERAL1 +SPI_MODE2 LITERAL1 +SPI_MODE3 LITERAL1 \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/SimpleServo/.DS_Store b/hardware/digistump/avr/libraries/SimpleServo/.DS_Store new file mode 100644 index 0000000..037ef29 Binary files /dev/null and b/hardware/digistump/avr/libraries/SimpleServo/.DS_Store differ diff --git a/hardware/digistump/avr/libraries/SimpleServo/README.txt b/hardware/digistump/avr/libraries/SimpleServo/README.txt new file mode 100644 index 0000000..0446a00 --- /dev/null +++ b/hardware/digistump/avr/libraries/SimpleServo/README.txt @@ -0,0 +1,42 @@ +================== +SimpleServo - v0.8 +================== + +"Shh, ya hear that? Me neither… It's simple… Maybe *too* simple…" + +This is a simplistic library to bundle up and generalize bit-banging servo PWM. It has some good points and trade-offs and is primarily being developed for the Digispark. + +First the good: + - Can control any number of servos + - All software, no fancy hardware required + - Produces a relatively clean signal + - Allows (or will) tuning pulse parameters to suit the widely varied tastes of different servos + - A single instance can be used with multiple similar servos + +Now some limitations: + - It can only control one servo at a time + - The program can't do anything else while the servo is being signaled + - Documentation is incomplete (at the moment) + +When typical servos stop receiving a control signal, they stay where they are; while they won't actively hold their position, most require some force to backdrive. So if that's enough for your project, you can move each servo in turn, and sample inputs, set LEDs and such in between. + +======= +Methods +======= + +See comments in SimpleServo.h (and SimpleServo.m) for now. + +*(( TODO: Document the additional methods in detail, add an example ))* + +======= +License +======= + +The MIT License (MIT) +Copyright (c) 2013 Benjamin Holt + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/hardware/digistump/avr/libraries/SimpleServo/SimpleServo.cpp b/hardware/digistump/avr/libraries/SimpleServo/SimpleServo.cpp new file mode 100644 index 0000000..af2145f --- /dev/null +++ b/hardware/digistump/avr/libraries/SimpleServo/SimpleServo.cpp @@ -0,0 +1,151 @@ +/* + Copyright (c) 2013 Benjamin Holt + + The MIT License (MIT) - See README for complete license + */ + + +#include + + +///// Setup ///// +SimpleServo::SimpleServo() : +_pin(0xff), +_degrees(0xff), +_microseconds(0), +_maxDegrees(180), +_millisPer60degrees(230), // default from http://www.servodatabase.com/servo/futaba/s3003 +_minWriteMillis(0), +_maxWriteMillis(0xffff), +_minPulse(700), +_maxPulse(2300), +_pulseMillis(16) +{} + + +uint8_t SimpleServo::attach(uint8_t p) { + _pin = p; + _degrees = 0xff; + _microseconds = 0; + // Deliberately not (re)initializing servo parameters + pinMode(_pin, OUTPUT); + digitalWrite(_pin, LOW); + return 1; +} + + +void SimpleServo::detach() { + _pin = 0xff; +} + + +uint8_t SimpleServo::attached() { + return _pin != 0xff; +} +///// + + +///// Movement ///// +void SimpleServo::_pulse(uint16_t ms) { + // This actually moves the servo + uint16_t elapsedMillis = 0; + while (elapsedMillis < ms) { + digitalWrite(_pin,HIGH); + delayMicroseconds(_microseconds); + digitalWrite(_pin,LOW); + if (ms > 0) { // 0ms: do the pulse, but that's it (probably a bad idea but, hey, if it works with your project, cool) + delay(_pulseMillis); // ENHANCEME: A hook to allow the client to make use (at their own risk of adding jitter) of these millis would be really nice + } + elapsedMillis += _pulseMillis + _microseconds / 1000 + 1; + } +} + + +void SimpleServo::writeMicrosecondsMillis(uint16_t us, uint16_t ms) { + _microseconds = us; // Allow unconstrained us + if (_minPulse <= us && us <= _maxPulse) { + _degrees = map(us, _minPulse, _maxPulse, 0, _maxDegrees); + } else { + _degrees = 0xff; // Out-of-range us do not convert sensibly to degrees + } + _pulse(ms); // And unconstrained ms, don't point this method at your foot. +} + + +void SimpleServo::writeMillis(uint8_t deg, uint16_t ms) { + _degrees = constrain(deg, 0, _maxDegrees); + _microseconds = constrain(map(_degrees, 0, _maxDegrees, _minPulse, _maxPulse), _minPulse, _maxPulse); + _pulse(ms); // Allow unconstrained millis +} + + +uint32_t SimpleServo::millisToTarget(uint8_t deg) { + uint8_t delta = abs(_degrees - deg); // if degrees is 0xff, this will over-estimate, so don't do anything special in that case + return ((uint32_t)_millisPer60degrees * delta) / 60; +} + + +void SimpleServo::writeMicroseconds(uint16_t us) { + // Simplest to do the us -> deg conversion here, so just finish the job + _microseconds = constrain(us, 0, _maxPulse); // keep degrees sane as much as possible, you have writeMicrosecondsMillis if you need to bend the rules + uint8_t target = map(us, _minPulse, _maxPulse, 0, _maxDegrees); + uint32_t millis = millisToTarget(target); + millis = constrain(millis, _minWriteMillis, _maxWriteMillis); + _degrees = target; + _pulse((uint16_t)millis); +} + + +void SimpleServo::write(uint8_t deg) { + uint32_t millis = millisToTarget(deg); + millis = constrain(millis, _minWriteMillis, _maxWriteMillis); + writeMillis(deg, (uint16_t)millis); +} + + +uint8_t SimpleServo::read() { + return _degrees; +} + + +uint16_t SimpleServo::readMicroseconds() { + return _microseconds; +} +///// + + +///// Servo Parameters ///// +void SimpleServo::setMaximumDegrees(uint8_t deg) { + _maxDegrees = deg; +} + + +void SimpleServo::setMillisPer60Degrees(uint16_t ms) { + _millisPer60degrees = ms; +} + + +void SimpleServo::setMinimumMillis(uint16_t ms) { + _minWriteMillis = ms; +} + + +void SimpleServo::setMaximumMillis(uint16_t ms) { + _maxWriteMillis = ms; +} + + +void SimpleServo::setMinimumPulse(uint16_t us) { + _minPulse = us; +} + + +void SimpleServo::setMaximumPulse(uint16_t us) { + _maxPulse = us; +} + + +void SimpleServo::setPulseMillis(uint8_t ms) { + _pulseMillis = ms; +} +///// diff --git a/hardware/digistump/avr/libraries/SimpleServo/SimpleServo.h b/hardware/digistump/avr/libraries/SimpleServo/SimpleServo.h new file mode 100644 index 0000000..275abc9 --- /dev/null +++ b/hardware/digistump/avr/libraries/SimpleServo/SimpleServo.h @@ -0,0 +1,59 @@ +/* + Copyright (c) 2013 Benjamin Holt + + The MIT License (MIT) - See README for complete license +*/ + +#ifndef _SimpleServo_h_ +#define _SimpleServo_h_ + +#include +#include + +class SimpleServo { + private: + // Movement + uint8_t _pin; + uint8_t _degrees; + uint16_t _microseconds; + + // Servo Parameters + // REM: nasty bit about when to constrain vs. not... more below... + uint8_t _maxDegrees; + uint16_t _millisPer60degrees; + uint16_t _minWriteMillis; + uint16_t _maxWriteMillis; + uint16_t _minPulse; + uint16_t _maxPulse; + uint8_t _pulseMillis; + + void _pulse(uint16_t); + + public: + // TODO: update keywords file + // Setup + SimpleServo(); + uint8_t attach(uint8_t); // Note: resets position, but not servo parameters, doesn't signal servo + void detach(); + uint8_t attached(); + + // Movement + void write(uint8_t); + void writeMicroseconds(uint16_t); + uint32_t millisToTarget(uint8_t); // Estimates time from current (expected) position to a target; if millisPer60Degrees is too small, this will come up short and the servo may not reach the target, too large and the write methods may signal longer than needed + void writeMillis(uint8_t, uint16_t); // Allows unconstrained millis + void writeMicrosecondsMillis(uint16_t, uint16_t); // Allows unconstrained microseconds and millis, full manual control + uint8_t read(); + uint16_t readMicroseconds(); + + + // Servo Parameters + void setMaximumDegrees(uint8_t); // A lot of servos move a bit more than 180 + void setMillisPer60Degrees(uint16_t); // For estimating time from last set position to newly requested position; different for every servo, http://www.servodatabase.com has many specs, default is 230 from Futaba S3003 + void setMinimumMillis(uint16_t); // The smallest time to signal the servo; some write methods do not enforce this + void setMaximumMillis(uint16_t); // This longest time to signal the servo, even if it probably has not yet reached the requested position; some write methods do not enforce this + void setMinimumPulse(uint16_t); // The shortest pulse (in microseconds) to send to the servo, maps to 0deg; only writeMicrosecondsMillis does not enforce this + void setMaximumPulse(uint16_t); // The shortest pulse (in microseconds) to send to the servo, maps to 0deg; only writeMicrosecondsMillis does not enforce this + void setPulseMillis(uint8_t); // Delay between pulses; defaults to 16 which is a bit quicker than spec. Experiment, different servos may react differently +}; +#endif // _SimpleServo_h_ diff --git a/hardware/digistump/avr/libraries/SimpleServo/examples/.DS_Store b/hardware/digistump/avr/libraries/SimpleServo/examples/.DS_Store new file mode 100644 index 0000000..5008ddf Binary files /dev/null and b/hardware/digistump/avr/libraries/SimpleServo/examples/.DS_Store differ diff --git a/hardware/digistump/avr/libraries/SimpleServo/keywords.txt b/hardware/digistump/avr/libraries/SimpleServo/keywords.txt new file mode 100644 index 0000000..382783c --- /dev/null +++ b/hardware/digistump/avr/libraries/SimpleServo/keywords.txt @@ -0,0 +1,27 @@ +####################################### +# Syntax Coloring Map SimpleServo +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +SimpleServo KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +attach KEYWORD2 +attached KEYWORD2 +detach KEYWORD2 +read KEYWORD2 +setMaximumPulse KEYWORD2 +setMinimumPulse KEYWORD2 +write KEYWORD2 +writeMillis KEYWORD2 +writeMicrosecondsMillis KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### diff --git a/hardware/digistump/avr/libraries/SoftRcPulseIn/SoftRcPulseIn.cpp b/hardware/digistump/avr/libraries/SoftRcPulseIn/SoftRcPulseIn.cpp new file mode 100644 index 0000000..70a4d12 --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseIn/SoftRcPulseIn.cpp @@ -0,0 +1,110 @@ +/* + English: by RC Navy (2012) + ======= + : an asynchronous library to read Input Pulse Width from standard Hobby Radio-Control. This library is a non-blocking version of pulseIn(). + http://p.loussouarn.free.fr + + Francais: par RC Navy (2012) + ======== + : une librairie asynchrone pour lire les largeur d'impulsions des Radio-Commandes standards. Cette librairie est une version non bloquante de pulsIn(). + http://p.loussouarn.free.fr +*/ + +#include "SoftRcPulseIn.h" + +#define LIB_VERSION 1 +#define LIB_REVISION 0 + +#define STR(s) #s +#define MAKE_TEXT_VER_REV(Ver,Rev) STR(Ver)"."STR(Rev) + +#define LIB_TEXT_VERSION_REVISION MAKE_TEXT_VER_REV(LIB_VERSION,LIB_REVISION) /* Make Full version as a string "Ver.Rev" */ + +SoftRcPulseIn *SoftRcPulseIn::first; + +SoftRcPulseIn::SoftRcPulseIn(void) +{ +} + +uint8_t SoftRcPulseIn::attach(uint8_t Pin, uint16_t PulseMin_us/*=600*/, uint16_t PulseMax_us/*=2400*/) +{ +uint8_t Ret=0; + + _Pin=Pin; + _PinMask=TinyPinChange_PinToMsk(Pin); + _Min_us=PulseMin_us; + _Max_us=PulseMax_us; + next = first; + first = this; + pinMode(_Pin,INPUT); + _VirtualPortIdx=TinyPinChange_RegisterIsr(_Pin,SoftRcPulseIn::SoftRcPulseInInterrupt); + if(_VirtualPortIdx>=0) + { + TinyPinChange_EnablePin(_Pin); + Ret=1; + } + return(Ret); +} + +int SoftRcPulseIn::LibVersion(void) +{ + return(LIB_VERSION); +} + +int SoftRcPulseIn::LibRevision(void) +{ + return(LIB_REVISION); +} + +char *SoftRcPulseIn::LibTextVersionRevision(void) +{ + return(LIB_TEXT_VERSION_REVISION); +} + +uint8_t SoftRcPulseIn::available(void) +{ +boolean Ret=0; +uint16_t PulseWidth_us; + + if(_Available) + { + noInterrupts(); + PulseWidth_us=_Width_us; + interrupts(); + Ret=_Available && (PulseWidth_us>=_Min_us) && (PulseWidth_us<=_Max_us); + _Available=0; + } + return(Ret); +} + +uint16_t SoftRcPulseIn::width_us(void) +{ +uint16_t PulseWidth_us; + noInterrupts(); + PulseWidth_us=_Width_us; + interrupts(); + return(PulseWidth_us); +} + +void SoftRcPulseIn::SoftRcPulseInInterrupt(void) +{ +SoftRcPulseIn *RcPulseIn; + + for ( RcPulseIn = first; RcPulseIn != 0; RcPulseIn = RcPulseIn->next ) + { + if(TinyPinChange_GetPinEvent(RcPulseIn->_VirtualPortIdx)&RcPulseIn->_PinMask) + { + if(digitalRead(RcPulseIn->_Pin)) + { + /* High level, rising edge: start chrono */ + RcPulseIn->_Start_us=micros(); + } + else + { + /* Low level, falling edge: stop chrono */ + RcPulseIn->_Width_us=micros()-RcPulseIn->_Start_us; + RcPulseIn->_Available=1; + } + } + } +} diff --git a/hardware/digistump/avr/libraries/SoftRcPulseIn/SoftRcPulseIn.h b/hardware/digistump/avr/libraries/SoftRcPulseIn/SoftRcPulseIn.h new file mode 100644 index 0000000..1d53eaf --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseIn/SoftRcPulseIn.h @@ -0,0 +1,58 @@ +/* + English: by RC Navy (2012) + ======= + : an asynchronous library to read Input Pulse Width from standard Hobby Radio-Control. This library is a non-blocking version of pulseIn(). + http://p.loussouarn.free.fr + + Francais: par RC Navy (2012) + ======== + : une librairie asynchrone pour lire les largeur d'impulsions des Radio-Commandes standards. Cette librairie est une version non bloquante de pulsIn(). + http://p.loussouarn.free.fr +*/ + +#ifndef SOFT_RC_PULSE_IN_H +#define SOFT_RC_PULSE_IN_H + +#if defined(ARDUINO) && ARDUINO >= 100 +#include "Arduino.h" +#else +#include "WProgram.h" +#endif + +#include + +#include + +class SoftRcPulseIn +{ + public: + SoftRcPulseIn(); + static int LibVersion(void); + static int LibRevision(void); + static char *LibTextVersionRevision(void); + static void SoftRcPulseInInterrupt(void); + uint8_t attach(uint8_t Pin, uint16_t PulseMin_us=600, uint16_t PulseMax_us=2400); + boolean available(); + uint16_t width_us(); + private: + class SoftRcPulseIn *next; + static SoftRcPulseIn *first; + uint8_t _Pin; + uint8_t _PinMask; + uint8_t _VirtualPortIdx; + uint16_t _Min_us; + uint16_t _Max_us; + uint32_t _Start_us; + uint32_t _Width_us; + boolean _Available; +}; +/*******************************************************/ +/* Application Programming Interface (API) en Francais */ +/*******************************************************/ + +/* Methodes en Francais English native methods */ +#define attache attach +#define disponible available +#define largeur_us width_us + +#endif diff --git a/hardware/digistump/avr/libraries/SoftRcPulseIn/examples/SoftRcPulseInDemo/SoftRcPulseInDemo.ino b/hardware/digistump/avr/libraries/SoftRcPulseIn/examples/SoftRcPulseInDemo/SoftRcPulseInDemo.ino new file mode 100644 index 0000000..a749a06 --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseIn/examples/SoftRcPulseInDemo/SoftRcPulseInDemo.ino @@ -0,0 +1,28 @@ +#include +#include + +#define BROCHE_VOIE1 2 + +SoftRcPulseIn ImpulsionVoie1; + + +void setup() +{ +#if !defined(__AVR_ATtiny24__) && !defined(__AVR_ATtiny44__) && !defined(__AVR_ATtiny84__) && !defined(__AVR_ATtiny25__) && !defined(__AVR_ATtiny45__) && !defined(__AVR_ATtiny85__) + Serial.begin(9600); + Serial.print("SoftRcPulseIn library V");Serial.print(SoftRcPulseIn::LibTextVersionRevision());Serial.print(" demo"); +#endif + ImpulsionVoie1.attache(BROCHE_VOIE1); +} + +void loop() +{ + if(ImpulsionVoie1.disponible()) + { +#if !defined(__AVR_ATtiny24__) && !defined(__AVR_ATtiny44__) && !defined(__AVR_ATtiny84__) && !defined(__AVR_ATtiny25__) && !defined(__AVR_ATtiny45__) && !defined(__AVR_ATtiny85__) + Serial.print("Pulse=");Serial.println(ImpulsionVoie1.largeur_us()); +#endif + } +} + + diff --git a/hardware/digistump/avr/libraries/SoftRcPulseIn/examples/SoftRcPulseInOutDemo/SoftRcPulseInOutDemo.ino b/hardware/digistump/avr/libraries/SoftRcPulseIn/examples/SoftRcPulseInOutDemo/SoftRcPulseInOutDemo.ino new file mode 100644 index 0000000..c6c09bb --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseIn/examples/SoftRcPulseInOutDemo/SoftRcPulseInOutDemo.ino @@ -0,0 +1,100 @@ +/* +This sketch demonstrates how to use library to get RC pulses from a receiver and to use library to drive 2 servos. +The first servo will follow the order, and the second one will have a reverted motion. +Please notice this sketch is fully asynchronous: no blocking functions such as delay() or pulseIn() are used. +Tested on arduino UNO, ATtiny84, ATtiny85 and Digispark rev2 (Model A). +RC Navy 2013 +http://p.loussouarn.free.fr +*/ + +#include +#include +#include /* Needed for library */ + +#define RX_CHANNEL_PIN 2 + +#define SERVO1_PIN 3 +#define SERVO2_PIN 4 + +#define LED_PIN 1//1 on Digispark rev2 (Model A), change to pin 0 for Digispark rev1 (Model B), change to 13 for UNO + +#define LED_HALF_PERIOD_MS 250 + +#define PULSE_MAX_PERIOD_MS 30 /* To refresh the servo in case of pulse extinction */ + +#define NOW 1 + +#define NEUTRAL_US 1500 /* Default position in case of no pulse at startup */ + +enum {NORMAL=0, INVERTED, SERVO_NB}; /* Trick: use an enumeration to declare the index of the servos AND the amount of servos */ + + +SoftRcPulseIn RxChannelPulse; /* RxChannelPulse is an objet of SoftRcPulseIn type */ +SoftRcPulseOut ServoMotor[SERVO_NB]; /* Table Creation for 2 objets of SoftRcPulseOut type */ + +/* Possible values to compute a shifting average fin order to smooth the recieved pulse witdh */ +#define AVG_WITH_1_VALUE 0 +#define AVG_WITH_2_VALUES 1 +#define AVG_WITH_4_VALUES 2 +#define AVG_WITH_8_VALUES 3 +#define AVG_WITH_16_VALUES 4 + +#define AVERAGE_LEVEL AVG_WITH_4_VALUES /* Choose here the average level among the above listed values */ + /* Higher is the average level, more the system is stable (jitter suppression), but lesser is the reaction */ + +/* Macro for average */ +#define AVERAGE(ValueToAverage,LastReceivedValue,AverageLevelInPowerOf2) ValueToAverage=(((ValueToAverage)*((1<<(AverageLevelInPowerOf2))-1)+(LastReceivedValue))/(1<<(AverageLevelInPowerOf2))) + +/* Variables */ +uint32_t LedStartMs=millis(); +uint32_t RxPulseStartMs=millis(); +boolean LedState=HIGH; + +void setup() +{ +#if !defined(__AVR_ATtiny24__) && !defined(__AVR_ATtiny44__) && !defined(__AVR_ATtiny84__) && !defined(__AVR_ATtiny25__) && !defined(__AVR_ATtiny45__) && !defined(__AVR_ATtiny85__) + Serial.begin(9600); + Serial.print("SoftRcPulseIn library V");Serial.print(SoftRcPulseIn::LibTextVersionRevision());Serial.print(" demo"); /* For arduino UNO which has an hardware UART, display the library version in the console */ +#endif + RxChannelPulse.attach(RX_CHANNEL_PIN); + ServoMotor[NORMAL].attach(SERVO1_PIN); /* enumeration is used a index for the ServoMotor[] table */ + ServoMotor[INVERTED].attach(SERVO2_PIN); /* enumeration is used a index for the ServoMotor[]table */ + pinMode(LED_PIN, OUTPUT); +} + +void loop() +{ +static uint16_t Width_us=NEUTRAL_US; /* Static to keep the value at the next loop */ + + /* Receiver pulse acquisition and command of 2 servos, one in the direct direction, one in the inverted direction */ + if(RxChannelPulse.available()) + { + AVERAGE(Width_us,RxChannelPulse.width_us(),AVERAGE_LEVEL); + ServoMotor[NORMAL].write_us(Width_us); /* Direct Signal */ + ServoMotor[INVERTED].write_us((NEUTRAL_US*2)-Width_us); /* Inverted Signal */ + SoftRcPulseOut::refresh(NOW); /* NOW argument (=1) allows to synchronize outgoing pulses with incoming pulses */ + RxPulseStartMs=millis(); /* Restart the Chrono for Pulse */ +#if !defined(__AVR_ATtiny24__) && !defined(__AVR_ATtiny44__) && !defined(__AVR_ATtiny84__) && !defined(__AVR_ATtiny25__) && !defined(__AVR_ATtiny45__) && !defined(__AVR_ATtiny85__) + Serial.print("Pulse=");Serial.println(Largeur_us); /* For arduino UNO which has an hardware UART, display the library version in the console */ +#endif + } + else + { + /* Check for pulse extinction */ + if(millis()-RxPulseStartMs>=PULSE_MAX_PERIOD_MS) + { + /* Refresh the servos with the last known position in order to avoid "flabby" servos */ + SoftRcPulseOut::refresh(NOW); /* Immediate refresh of outgoing pulses */ + RxPulseStartMs=millis(); /* Restart the Chrono for Pulse */ + } + } + + /* Blink LED Management */ + if(millis()-LedStartMs>=LED_HALF_PERIOD_MS) + { + digitalWrite(LED_PIN, LedState); + LedState=!LedState; /* At the next loop, if the half period is elapsed, the LED state will be inverted */ + LedStartMs=millis(); /* Restart the Chrono for the LED */ + } + +} diff --git a/hardware/digistump/avr/libraries/SoftRcPulseIn/keywords.txt b/hardware/digistump/avr/libraries/SoftRcPulseIn/keywords.txt new file mode 100644 index 0000000..5a6a77a --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseIn/keywords.txt @@ -0,0 +1,26 @@ +####################################### +# Syntax Coloring Map SoftRcPulseIn +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +SoftRcPulseIn KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### +LibVersion KEYWORD2 +LibRevision KEYWORD2 +LibTextVersionRevision KEYWORD2 +attach KEYWORD2 +attache KEYWORD2 +available KEYWORD2 +disponible KEYWORD2 +width_us KEYWORD2 +largeur_us KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### diff --git a/hardware/digistump/avr/libraries/SoftRcPulseOut/SoftRcPulseOut.cpp b/hardware/digistump/avr/libraries/SoftRcPulseOut/SoftRcPulseOut.cpp new file mode 100644 index 0000000..1c9aaba --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseOut/SoftRcPulseOut.cpp @@ -0,0 +1,208 @@ +#include "SoftRcPulseOut.h" +/* + Update 01/03/2013: add support for DigiSpark (http://digistump.com): automatic Timer selection (RC Navy: p.loussouarn.free.fr) + + English: by RC Navy (2012) + ======= + : a library mainly based on the library, but with a better pulse generation to limit jitter. + It supports the same methods as . + It also support Pulse Width order given in microseconds. The current Pulse Width can also be read in microseconds. + The refresh method can admit an optionnal argument (force). If SoftRcPulseOut::refresh(1) is called, the refresh is forced even if 20 ms are not elapsed. + http://p.loussouarn.free.fr + + Francais: par RC Navy (2012) + ======== + : une librairie majoritairement basee sur la librairie , mais avec une meilleure generation des impulsions pour limiter la gigue. + Elle supporte les memes methodes que . + Elle supporte egalement une consigne de largeur d'impulsion passee en microseconde. La largeur de l'impulsion courante peut egalement etre lue en microseconde. + La methode refresh peut admettre un parametre optionnel (force). Si SoftRcPulseOut::resfresh(1) est appelee, le refresh est force meme si 20 ms ne se sont pas ecoulee. + http://p.loussouarn.free.fr +*/ + +/* Automatic Timer selection (at compilation time) */ +#ifndef TIMER_TO_USE_FOR_MILLIS //This symbol is not defined arduino standard core and is defined in core_build_options.h in DigiStump version +#define SOFT_RC_PULSE_OUT_TCNT TCNT0 //For arduino standard core of UNO/MEGA, etc +#else +#if (TIMER_TO_USE_FOR_MILLIS==1) +#define SOFT_RC_PULSE_OUT_TCNT TCNT1 //For example for ATtiny85 +#else +#define SOFT_RC_PULSE_OUT_TCNT TCNT0 //For example for ATtiny84 +#endif +#endif + +SoftRcPulseOut *SoftRcPulseOut::first; + +#define NO_ANGLE (0xff) + +SoftRcPulseOut::SoftRcPulseOut() : pin(0),angle(NO_ANGLE),pulse0(0),min16(34),max16(150),next(0) +{} + +void SoftRcPulseOut::setMinimumPulse(uint16_t t) +{ + min16 = t/16; +} + +void SoftRcPulseOut::setMaximumPulse(uint16_t t) +{ + max16 = t/16; +} + +uint8_t SoftRcPulseOut::attach(int pinArg) +{ + pin = pinArg; + angle = NO_ANGLE; + pulse0 = 0; + next = first; + first = this; + digitalWrite(pin,0); + pinMode(pin,OUTPUT); + return 1; +} + +void SoftRcPulseOut::detach() +{ + for ( SoftRcPulseOut **p = &first; *p != 0; p = &((*p)->next) ) { + if ( *p == this) { + *p = this->next; + this->next = 0; + return; + } + } +} + +void SoftRcPulseOut::write(int angleArg) +{ + if ( angleArg < 0) angleArg = 0; + if ( angleArg > 180) angleArg = 180; + angle = angleArg; + // bleh, have to use longs to prevent overflow, could be tricky if always a 16MHz clock, but not true + // That 64L on the end is the TCNT0 prescaler, it will need to change if the clock's prescaler changes, + // but then there will likely be an overflow problem, so it will have to be handled by a human. +#ifdef TIMER0_TICK_EVERY_X_CYCLES + pulse0 = (min16*16L*clockCyclesPerMicrosecond() + (max16-min16)*(16L*clockCyclesPerMicrosecond())*angle/180L)/TIMER0_TICK_EVERY_X_CYCLES; +#else + pulse0 = (min16*16L*clockCyclesPerMicrosecond() + (max16-min16)*(16L*clockCyclesPerMicrosecond())*angle/180L)/64L; +#endif +} + +void SoftRcPulseOut::write_us(int PulseWidth_us) +{ + SoftRcPulseOut::write(map(PulseWidth_us,min16*16,max16*16,0,180)); +} + +uint8_t SoftRcPulseOut::read() +{ + return angle; +} + +uint8_t SoftRcPulseOut::read_us() +{ + return map(angle,0,180,min16*16,max16*16); +} + +uint8_t SoftRcPulseOut::attached() +{ + for ( SoftRcPulseOut *p = first; p != 0; p = p->next ) { + if ( p == this) return 1; + } + return 0; +} + +uint8_t SoftRcPulseOut::refresh(bool force /* = false */) +{ + uint8_t RefreshDone=0; + uint8_t count = 0, i = 0; + uint16_t base = 0; + SoftRcPulseOut *p; + static unsigned long lastRefresh = 0; + unsigned long m = millis(); + if(!force) + { + // if we haven't wrapped millis, and 20ms have not passed, then don't do anything + if ( m >= lastRefresh && m < lastRefresh + 20) return(RefreshDone); + } + RefreshDone=1; //Ok: Refresh will be performed + lastRefresh = m; + + for ( p = first; p != 0; p = p->next ) if ( p->pulse0) count++; + if ( count == 0) return(RefreshDone); + + // gather all the SoftRcPulseOuts in an array + SoftRcPulseOut *s[count]; + for ( p = first; p != 0; p = p->next ) if ( p->pulse0) s[i++] = p; + + // bubblesort the SoftRcPulseOuts by pulse time, ascending order + s[0]->ItMasked=0; + for(;;) + { + uint8_t moved = 0; + for ( i = 1; i < count; i++) + { + s[i]->ItMasked=0; + if ( s[i]->pulse0 < s[i-1]->pulse0) + { + SoftRcPulseOut *t = s[i]; + s[i] = s[i-1]; + s[i-1] = t; + moved = 1; + } + } + if ( !moved) break; + } + for ( i = 1; i < count; i++) + { + if ( abs(s[i]->pulse0 - s[i-1]->pulse0)<=5) + { + s[i]->ItMasked=1; /* 2 consecutive Pulses are close each other, so do not unmask interrupts between Pulses */ + } + } + // turn on all the pins + // Note the timing error here... when you have many SoftwareServos going, the + // ones at the front will get a pulse that is a few microseconds too long. + // Figure about 4uS/SoftRcPulseOut after them. This could be compensated, but I feel + // it is within the margin of error of software SoftRcPulseOuts that could catch + // an extra interrupt handler at any time. + noInterrupts(); + for ( i = 0; i < count; i++) digitalWrite( s[i]->pin, 1); + interrupts(); + + uint8_t start = SOFT_RC_PULSE_OUT_TCNT; + uint8_t now = start; + uint8_t last = now; + + // Now wait for each pin's time in turn.. + for ( i = 0; i < count; i++) + { + uint16_t go = start + s[i]->pulse0; + uint16_t it = go - 4; /* 4 Ticks is OK for UNO @ 16MHz */ /* Mask Interruptions just before setting down the pin */ + + // loop until we reach or pass 'go' time + for (;;) + { + now = SOFT_RC_PULSE_OUT_TCNT; + if ( now < last) base += 256; + last = now; + if(!s[i]->ItMasked) + { + if( base + now > it) + { + noInterrupts(); + s[i]->ItMasked=1; + } + } + if ( base + now > go) + { + digitalWrite( s[i]->pin,0); + if((i+1)ItMasked) + { + interrupts(); + } + }else interrupts(); + break; + } + } + } + return(RefreshDone); +} diff --git a/hardware/digistump/avr/libraries/SoftRcPulseOut/SoftRcPulseOut.h b/hardware/digistump/avr/libraries/SoftRcPulseOut/SoftRcPulseOut.h new file mode 100644 index 0000000..38fe050 --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseOut/SoftRcPulseOut.h @@ -0,0 +1,59 @@ +#ifndef SoftRcPulseOut_h +#define SoftRcPulseOut_h + +/* + Update 01/03/2013: add support for DigiSpark (http://digistump.com): automatic Timer selection (RC Navy: p.loussouarn.free.fr) + + English: by RC Navy (2012) + ======= + : a library mainly based on the library, but with a better pulse generation to limit jitter. + It supports the same methods as . + It also support Pulse Width order given in microseconds. The current Pulse Width can also be read in microseconds. + The refresh method can admit an optionnal argument (force). If SoftRcPulseOut::refresh(1) is called, the refresh is forced even if 20 ms are not elapsed. + http://p.loussouarn.free.fr + + Francais: par RC Navy (2012) + ======== + : une librairie majoritairement basee sur la librairie , mais avec une meilleure generation des impulsions pour limiter la gigue. + Elle supporte les memes methodes que . + Elle supporte egalement une consigne de largeur d'impulsion passee en microseconde. La largeur de l'impulsion courante peut egalement etre lue en microseconde. + La methode refresh peut admettre un parametre optionnel (force). Si SoftRcPulseOut::resfresh(1) est appelee, le refresh est force meme si 20 ms ne se sont pas ecoulee. + http://p.loussouarn.free.fr +*/ + +#if defined(ARDUINO) && ARDUINO >= 100 +#include "Arduino.h" +#else +#include "WProgram.h" +#endif + +#include + +class SoftRcPulseOut +{ + private: + boolean ItMasked; + uint8_t pin; + uint8_t angle; // in degrees + uint16_t pulse0; // pulse width in TCNT0 counts + uint8_t min16; // minimum pulse, 16uS units (default is 34) + uint8_t max16; // maximum pulse, 16uS units, 0-4ms range (default is 150) + class SoftRcPulseOut *next; + static SoftRcPulseOut* first; + public: + SoftRcPulseOut(); + uint8_t attach(int); // attach to a pin, sets pinMode, returns 0 on failure, won't + // position the servo until a subsequent write() happens + void detach(); + void write(int); // specify the angle in degrees, 0 to 180 + void write_us(int); // specify the angle in microseconds, 500 to 2500 + uint8_t read(); // return the current angle + uint8_t read_us(); // return the current pulse with in microseconds + uint8_t attached(); + void setMinimumPulse(uint16_t); // pulse length for 0 degrees in microseconds, 540uS default + void setMaximumPulse(uint16_t); // pulse length for 180 degrees in microseconds, 2400uS default + static uint8_t refresh(bool force = false); // must be called at least every 50ms or so to keep servo alive + // you can call more often, it won't happen more than once every 20ms +}; + +#endif diff --git a/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/Knob/Knob.ino b/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/Knob/Knob.ino new file mode 100644 index 0000000..b0daf50 --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/Knob/Knob.ino @@ -0,0 +1,37 @@ +// Controlling a servo position using a potentiometer (variable resistor) +// by Michal Rinott +// Adapted to SoftRcPulseOut library by RC Navy (http://p.loussouarn.free.fr) +// This sketch can work with ATtiny and Arduino UNO, MEGA, etc... + +#include + +SoftRcPulseOut myservo; // create servo object to control a servo + +#if defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny25__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__) +//Here is the POT_PIN definition for ATtiny, they do NOT need a 'A' prefix for Analogic definition +#define POT_PIN 2 // --analog pin-- (not digital) used to connect the potentiometer +#else +//Here is the POT_PIN definition for Arduino UNO, MEGA, they do need a 'A' prefix for Analogic definition +#define POT_PIN A2 // --analog pin-- (not digital) used to connect the potentiometer +#endif + +#define SERVO_PIN 3 // --digital pin-- (not analog) used to connect the servo + +#define REFRESH_PERIOD_MS 20 + +int val; // variable to read the value from the analog pin + +void setup() +{ + myservo.attach(SERVO_PIN); // attaches the servo on pin defined by SERVO_PIN to the servo object +} + +void loop() +{ + val = analogRead(POT_PIN); // reads the value of the potentiometer (value between 0 and 1023) + val = map(val, 0, 1023, 0, 179); // scale it to use it with the servo (value between 0 and 180) + myservo.write(val); // sets the servo position according to the scaled value + delay(REFRESH_PERIOD_MS); // waits for the servo to get there + SoftRcPulseOut::refresh(); // generates the servo pulse +} + diff --git a/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/SerialServo/SerialServo.ino b/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/SerialServo/SerialServo.ino new file mode 100644 index 0000000..25ef81d --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/SerialServo/SerialServo.ino @@ -0,0 +1,60 @@ +// This SoftwareServo library example sketch was initially delivered without any comments. +// Below my own comments for SoftRcPulseOut library: by RC Navy (http://p.loussouarn.free.fr) +// Controlling the position of 2 servos using the Arduino built-in hardware UART (Arduino Serial object). +// This sketch do NOT work with an ATtinyX4 and ATtinyX5 since they do not have a built-in harware UART (no Arduino Serial object). + +// The command (issued in the Arduino Serial Console or in a Terminal) is: +// S=P with: +// S=A for Servo1 and S=B for Servo2 +// P=Position number x 20° (Possible positions are from 0 to 9 which correspond to from 0° to 180°) +// Ex: +// A=7 sets Servo1 at 7 x 20 =140° +// B=3 sets Servo2 at 3 x 20 =60° + +#include + +SoftRcPulseOut servo1; +SoftRcPulseOut servo2; + +void setup() +{ + pinMode(13,OUTPUT); + servo1.attach(2); + servo1.setMaximumPulse(2200); + servo2.attach(4); + servo2.setMaximumPulse(2200); + Serial.begin(9600); + Serial.print("Ready"); +} + +void loop() +{ + static int value = 0; + static char CurrentServo = 0; + + if ( Serial.available()) { + char ch = Serial.read(); + switch(ch) { + case 'A': + CurrentServo='A'; + digitalWrite(13,LOW); + break; + case 'B': + CurrentServo='B'; + digitalWrite(13,HIGH); + break; + case '0' ... '9': + value=(ch-'0')*20; + if (CurrentServo=='A') + { + servo1.write(value); + } + else if (CurrentServo=='B') + { + servo2.write(value); + } + break; + } + } + SoftRcPulseOut::refresh(); +} diff --git a/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/SoftRcPulseInOutDemo/SoftRcPulseInOutDemo.ino b/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/SoftRcPulseInOutDemo/SoftRcPulseInOutDemo.ino new file mode 100644 index 0000000..c6c09bb --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/SoftRcPulseInOutDemo/SoftRcPulseInOutDemo.ino @@ -0,0 +1,100 @@ +/* +This sketch demonstrates how to use library to get RC pulses from a receiver and to use library to drive 2 servos. +The first servo will follow the order, and the second one will have a reverted motion. +Please notice this sketch is fully asynchronous: no blocking functions such as delay() or pulseIn() are used. +Tested on arduino UNO, ATtiny84, ATtiny85 and Digispark rev2 (Model A). +RC Navy 2013 +http://p.loussouarn.free.fr +*/ + +#include +#include +#include /* Needed for library */ + +#define RX_CHANNEL_PIN 2 + +#define SERVO1_PIN 3 +#define SERVO2_PIN 4 + +#define LED_PIN 1//1 on Digispark rev2 (Model A), change to pin 0 for Digispark rev1 (Model B), change to 13 for UNO + +#define LED_HALF_PERIOD_MS 250 + +#define PULSE_MAX_PERIOD_MS 30 /* To refresh the servo in case of pulse extinction */ + +#define NOW 1 + +#define NEUTRAL_US 1500 /* Default position in case of no pulse at startup */ + +enum {NORMAL=0, INVERTED, SERVO_NB}; /* Trick: use an enumeration to declare the index of the servos AND the amount of servos */ + + +SoftRcPulseIn RxChannelPulse; /* RxChannelPulse is an objet of SoftRcPulseIn type */ +SoftRcPulseOut ServoMotor[SERVO_NB]; /* Table Creation for 2 objets of SoftRcPulseOut type */ + +/* Possible values to compute a shifting average fin order to smooth the recieved pulse witdh */ +#define AVG_WITH_1_VALUE 0 +#define AVG_WITH_2_VALUES 1 +#define AVG_WITH_4_VALUES 2 +#define AVG_WITH_8_VALUES 3 +#define AVG_WITH_16_VALUES 4 + +#define AVERAGE_LEVEL AVG_WITH_4_VALUES /* Choose here the average level among the above listed values */ + /* Higher is the average level, more the system is stable (jitter suppression), but lesser is the reaction */ + +/* Macro for average */ +#define AVERAGE(ValueToAverage,LastReceivedValue,AverageLevelInPowerOf2) ValueToAverage=(((ValueToAverage)*((1<<(AverageLevelInPowerOf2))-1)+(LastReceivedValue))/(1<<(AverageLevelInPowerOf2))) + +/* Variables */ +uint32_t LedStartMs=millis(); +uint32_t RxPulseStartMs=millis(); +boolean LedState=HIGH; + +void setup() +{ +#if !defined(__AVR_ATtiny24__) && !defined(__AVR_ATtiny44__) && !defined(__AVR_ATtiny84__) && !defined(__AVR_ATtiny25__) && !defined(__AVR_ATtiny45__) && !defined(__AVR_ATtiny85__) + Serial.begin(9600); + Serial.print("SoftRcPulseIn library V");Serial.print(SoftRcPulseIn::LibTextVersionRevision());Serial.print(" demo"); /* For arduino UNO which has an hardware UART, display the library version in the console */ +#endif + RxChannelPulse.attach(RX_CHANNEL_PIN); + ServoMotor[NORMAL].attach(SERVO1_PIN); /* enumeration is used a index for the ServoMotor[] table */ + ServoMotor[INVERTED].attach(SERVO2_PIN); /* enumeration is used a index for the ServoMotor[]table */ + pinMode(LED_PIN, OUTPUT); +} + +void loop() +{ +static uint16_t Width_us=NEUTRAL_US; /* Static to keep the value at the next loop */ + + /* Receiver pulse acquisition and command of 2 servos, one in the direct direction, one in the inverted direction */ + if(RxChannelPulse.available()) + { + AVERAGE(Width_us,RxChannelPulse.width_us(),AVERAGE_LEVEL); + ServoMotor[NORMAL].write_us(Width_us); /* Direct Signal */ + ServoMotor[INVERTED].write_us((NEUTRAL_US*2)-Width_us); /* Inverted Signal */ + SoftRcPulseOut::refresh(NOW); /* NOW argument (=1) allows to synchronize outgoing pulses with incoming pulses */ + RxPulseStartMs=millis(); /* Restart the Chrono for Pulse */ +#if !defined(__AVR_ATtiny24__) && !defined(__AVR_ATtiny44__) && !defined(__AVR_ATtiny84__) && !defined(__AVR_ATtiny25__) && !defined(__AVR_ATtiny45__) && !defined(__AVR_ATtiny85__) + Serial.print("Pulse=");Serial.println(Largeur_us); /* For arduino UNO which has an hardware UART, display the library version in the console */ +#endif + } + else + { + /* Check for pulse extinction */ + if(millis()-RxPulseStartMs>=PULSE_MAX_PERIOD_MS) + { + /* Refresh the servos with the last known position in order to avoid "flabby" servos */ + SoftRcPulseOut::refresh(NOW); /* Immediate refresh of outgoing pulses */ + RxPulseStartMs=millis(); /* Restart the Chrono for Pulse */ + } + } + + /* Blink LED Management */ + if(millis()-LedStartMs>=LED_HALF_PERIOD_MS) + { + digitalWrite(LED_PIN, LedState); + LedState=!LedState; /* At the next loop, if the half period is elapsed, the LED state will be inverted */ + LedStartMs=millis(); /* Restart the Chrono for the LED */ + } + +} diff --git a/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/Sweep/Sweep.ino b/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/Sweep/Sweep.ino new file mode 100644 index 0000000..6261356 --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/Sweep/Sweep.ino @@ -0,0 +1,37 @@ +// Sweep +// by BARRAGAN +// Adapted to SoftRcPulseOut library by RC Navy (http://p.loussouarn.free.fr) +// This sketch can work with ATtiny and Arduino UNO, MEGA, etc... +// This example code is in the public domain. + +#include + +SoftRcPulseOut myservo; // create servo object to control a servo + // a maximum of eight servo objects can be created +#define SERVO_PIN 3 + +#define REFRESH_PERIOD_MS 20 + +int pos = 0; // variable to store the servo position + +void setup() +{ + myservo.attach(SERVO_PIN); // attaches the servo on pin defined by SERVO_PIN to the servo object +} + + +void loop() +{ + for(pos = 0; pos < 180; pos += 1) // goes from 0 degrees to 180 degrees + { // in steps of 1 degree + myservo.write(pos); // tell servo to go to position in variable 'pos' + delay(REFRESH_PERIOD_MS); // waits 20ms for refresh period + SoftRcPulseOut::refresh(1); // generates the servo pulse + } + for(pos = 180; pos>=1; pos-=1) // goes from 180 degrees to 0 degrees + { + myservo.write(pos); // tell servo to go to position in variable 'pos' + delay(REFRESH_PERIOD_MS); // waits 20ms for for refresh period + SoftRcPulseOut::refresh(1); // generates the servo pulse + } +} diff --git a/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/Usb2Servos/Usb2Servos.ino b/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/Usb2Servos/Usb2Servos.ino new file mode 100644 index 0000000..a3ceaab --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/Usb2Servos/Usb2Servos.ino @@ -0,0 +1,73 @@ +// This sketch demonstrates how to command 2 servos through the USB of the Digispark. +// It uses: +// - library to easily generates the RC pulses for the servos. +// - library to communicate with the PC +// By RC Navy (http://p.loussouarn.free.fr) + +// The command (issued in the DigiUSB Monitor or the digiterm) is: +// S=P with: +// S=A for ServoA and S=B for ServoB +// P=Position number x 20° (Possible positions are from 0 to 9 which correspond to from 0° to 180°) +// Ex: +// A=7 sets Servo1 at 7 x 20 =140° +// B=3 sets Servo2 at 3 x 20 =60° +// Once the servo selected, just type the value between 0 and 9 +// Please, note this sketch is derived from the SerialServo example of library. + +#include +#include + +#define LED_PIN 1 /* Builtin Led on Rev2 ModelA Digispark */ +#define SERVO_A_PIN 2 +/* /!\ Do not use Pin 3 (used by USB) /!\ */ +/* /!\ Do not use Pin 4 (used by USB) /!\ */ +#define SERVO_B_PIN 5 + +SoftRcPulseOut ServoA; +SoftRcPulseOut ServoB; + + +void setup() +{ + pinMode(LED_PIN,OUTPUT); + ServoA.attach(SERVO_A_PIN); + ServoB.attach(SERVO_B_PIN); + DigiUSB.begin(); + DigiUSB.println(" Ready"); +} + +void loop() +{ + static int value = 0; + static char CurrentServo = 0; + + if ( DigiUSB.available()) { + char ch = DigiUSB.read(); + switch(ch) { + case 'A': + CurrentServo='A'; + digitalWrite(LED_PIN,LOW); + break; + case 'B': + CurrentServo='B'; + digitalWrite(LED_PIN,HIGH); + break; + case '0' ... '9': + value=(ch-'0')*20; + if (CurrentServo=='A') + { + ServoA.write(value); + } + else if (CurrentServo=='B') + { + ServoB.write(value); + } + break; + } + } + DigiUSB.refresh(); + SoftRcPulseOut::refresh(); + /* + Put here your non-blocking code + */ +} diff --git a/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/knob_moyennee/knob_moyennee.ino b/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/knob_moyennee/knob_moyennee.ino new file mode 100644 index 0000000..7f7a436 --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseOut/examples/knob_moyennee/knob_moyennee.ino @@ -0,0 +1,53 @@ +// Controlling a servo position using a potentiometer (variable resistor) +// by Michal Rinott +// Adapted to SoftRcPulseOut library by RC Navy (http://p.loussouarn.free.fr) +// This sketch can work with ATtiny and Arduino UNO, MEGA, etc... + +#include + +SoftRcPulseOut myservo; // create servo object to control a servo + +#if defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) || defined(__AVR_ATtiny25__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__) +//Here is the POT_PIN definition for ATtiny, they do NOT need a 'A' prefix for Analogic definition +#define POT_PIN 2 // --analog pin-- (not digital) used to connect the potentiometer +#else +//Here is the POT_PIN definition for Arduino UNO, MEGA, they do need a 'A' prefix for Analogic definition +#define POT_PIN A2 // --analog pin-- (not digital) used to connect the potentiometer +#endif + +#define SERVO_PIN 3 // --digital pin-- (not analog) used to connect the servo + +#define REFRESH_PERIOD_MS 20 + + +#define MOY_SUR_1_VALEUR 0 +#define MOY_SUR_2_VALEURS 1 +#define MOY_SUR_4_VALEURS 2 +#define MOY_SUR_8_VALEURS 3 +#define MOY_SUR_16_VALEURS 4 +#define MOY_SUR_32_VALEURS 5 + +#define TAUX_DE_MOYENNAGE MOY_SUR_4_VALEURS /* Choisir ici le taux de moyennage parmi les valeurs precedentes possibles listees ci-dessus */ + /* Plus le taux est élevé, plus le système est stable (diminution de la gigue), mais moins il est réactif */ + +#define MOYENNE(Valeur_A_Moyenner,DerniereValeurRecue,TauxDeMoyEnPuissanceDeDeux) Valeur_A_Moyenner=((((Valeur_A_Moyenner)*((1<<(TauxDeMoyEnPuissanceDeDeux))-1)+(DerniereValeurRecue))/(1<<(TauxDeMoyEnPuissanceDeDeux)))+(TauxDeMoyEnPuissanceDeDeux-1)) + +int val; // variable to read the value from the analog pin + +void setup() +{ + + myservo.attach(SERVO_PIN); // attaches the servo on pin defined by SERVO_PIN to the servo object +} + +void loop() +{ +static int ValMoyennee; + val = analogRead(POT_PIN); // reads the value of the potentiometer (value between 0 and 1023) + val = map(val, 0, 1023, 0, 179); // scale it to use it with the servo (value between 0 and 180) + MOYENNE(ValMoyennee,val,TAUX_DE_MOYENNAGE);//If there is lots of noise: average with TAUX_DE_MOYENNAGE + myservo.write(ValMoyennee); // sets the servo position according to the scaled value + delay(REFRESH_PERIOD_MS); // waits for the servo to get there + SoftRcPulseOut::refresh(); // generates the servo pulse +} + diff --git a/hardware/digistump/avr/libraries/SoftRcPulseOut/keywords.txt b/hardware/digistump/avr/libraries/SoftRcPulseOut/keywords.txt new file mode 100644 index 0000000..55c3f40 --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftRcPulseOut/keywords.txt @@ -0,0 +1,27 @@ +####################################### +# Syntax Coloring Map SoftRcPulseOut +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +SoftRcPulseOut KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### +attach KEYWORD2 +detach KEYWORD2 +write KEYWORD2 +write_us KEYWORD2 +read KEYWORD2 +read_us KEYWORD2 +attached KEYWORD2 +setMinimumPulse KEYWORD2 +setMaximumPulse KEYWORD2 +refresh KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### diff --git a/hardware/digistump/avr/libraries/SoftSerial/SoftSerial.cpp b/hardware/digistump/avr/libraries/SoftSerial/SoftSerial.cpp new file mode 100644 index 0000000..be2db54 --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftSerial/SoftSerial.cpp @@ -0,0 +1,573 @@ +/* + library is exactly the same as the library but used with the library which allows to share +the Pin Change Interrupt Vector. + monopolizes the Pin Change Interrupt Vector and don't allow sharing. +With , it's possible. Don't forget to #include in your sketch! +Additionally, for small devices such as ATtiny85 (Digispark), it's possible to declare the same pin for TX and RX. +Data direction is set by using the new txMode() and rxMode methods. +RC Navy (2012-2013): http://p.loussouarn.free.fr + +SoftwareSerial.cpp (formerly NewSoftSerial.cpp) - +Multi-instance software serial library for Arduino/Wiring +-- Interrupt-driven receive and other improvements by ladyada + (http://ladyada.net) +-- Tuning, circular buffer, derivation from class Print/Stream, + multi-instance support, porting to 8MHz processors, + various optimizations, PROGMEM delay tables, inverse logic and + direct port writing by Mikal Hart (http://www.arduiniana.org) +-- Pin change interrupt macros by Paul Stoffregen (http://www.pjrc.com) +-- 20MHz processor support by Garrett Mace (http://www.macetech.com) +-- ATmega1280/2560 support by Brett Hagman (http://www.roguerobotics.com/) + +This library is free software; you can redistribute it and/or +modify it under the terms of the GNU Lesser General Public +License as published by the Free Software Foundation; either +version 2.1 of the License, or (at your option) any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Lesser General Public License for more details. + +You should have received a copy of the GNU Lesser General Public +License along with this library; if not, write to the Free Software +Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +The latest version of this library can always be found at +http://arduiniana.org. +*/ + +// When set, _DEBUG co-opts pins 11 and 13 for debugging with an +// oscilloscope or logic analyzer. Beware: it also slightly modifies +// the bit times, so don't rely on it too much at high baud rates +#define _DEBUG 0 +#define _DEBUG_PIN1 11 +#define _DEBUG_PIN2 13 +// +// Includes +// +#include +#include +#include "Arduino.h" +#include "SoftSerial.h" +// +// Lookup table +// +typedef struct _DELAY_TABLE +{ + long baud; + unsigned short rx_delay_centering; + unsigned short rx_delay_intrabit; + unsigned short rx_delay_stopbit; + unsigned short tx_delay; +} DELAY_TABLE; + +#if F_CPU == 16000000 + +static const DELAY_TABLE PROGMEM table[] = +{ + // baud rxcenter rxintra rxstop tx + { 115200, 1, 17, 17, 12, }, + { 57600, 10, 37, 37, 33, }, + { 38400, 25, 57, 57, 54, }, + { 31250, 31, 70, 70, 68, }, + { 28800, 34, 77, 77, 74, }, + { 19200, 54, 117, 117, 114, }, + { 14400, 74, 156, 156, 153, }, + { 9600, 114, 236, 236, 233, }, + { 4800, 233, 474, 474, 471, }, + { 2400, 471, 950, 950, 947, }, + { 1200, 947, 1902, 1902, 1899, }, + { 300, 3804, 7617, 7617, 7614, }, +}; + +const int XMIT_START_ADJUSTMENT = 5; +//PL{ table from http://digistump.com/board/index.php/topic,212.msg1214/topicseen.html#msg1214 +#elif F_CPU == 16500000 + + +static const DELAY_TABLE PROGMEM table[] = +{ + // baud rxcenter rxintra rxstop tx + { 115200, 1, 18, 18, 12, }, + { 57600, 10, 38, 38, 34, }, + { 38400, 26, 59, 59, 56, }, + { 31250, 32, 72, 72, 70, }, + { 28800, 35, 79, 79, 76, }, + { 19200, 56, 121, 121, 118, }, + { 14400, 76, 161, 161, 158, }, + { 9600, 118, 243, 243, 240, }, + { 4800, 240, 489, 489, 486, }, + { 2400, 486, 980, 980, 977, }, + { 1200, 977, 1961, 1961, 1958, }, + { 600, 1961, 3923, 3923, 3919, }, + { 300, 3923, 7855, 7855, 7852, }, +}; + + +const int XMIT_START_ADJUSTMENT = 5; +//PL} +#elif F_CPU == 8000000 + +static const DELAY_TABLE table[] PROGMEM = +{ + // baud rxcenter rxintra rxstop tx + { 115200, 1, 5, 5, 3, }, + { 57600, 1, 15, 15, 13, }, + { 38400, 2, 25, 26, 23, }, + { 31250, 7, 32, 33, 29, }, + { 28800, 11, 35, 35, 32, }, + { 19200, 20, 55, 55, 52, }, + { 14400, 30, 75, 75, 72, }, + { 9600, 50, 114, 114, 112, }, + { 4800, 110, 233, 233, 230, }, + { 2400, 229, 472, 472, 469, }, + { 1200, 467, 948, 948, 945, }, + { 300, 1895, 3805, 3805, 3802, }, +}; + +const int XMIT_START_ADJUSTMENT = 4; + +#elif F_CPU == 20000000 + +// 20MHz support courtesy of the good people at macegr.com. +// Thanks, Garrett! + +static const DELAY_TABLE PROGMEM table[] = +{ + // baud rxcenter rxintra rxstop tx + { 115200, 3, 21, 21, 18, }, + { 57600, 20, 43, 43, 41, }, + { 38400, 37, 73, 73, 70, }, + { 31250, 45, 89, 89, 88, }, + { 28800, 46, 98, 98, 95, }, + { 19200, 71, 148, 148, 145, }, + { 14400, 96, 197, 197, 194, }, + { 9600, 146, 297, 297, 294, }, + { 4800, 296, 595, 595, 592, }, + { 2400, 592, 1189, 1189, 1186, }, + { 1200, 1187, 2379, 2379, 2376, }, + { 300, 4759, 9523, 9523, 9520, }, +}; + +const int XMIT_START_ADJUSTMENT = 6; + +#else + +#error This version of SoftSerial supports only 20, 16 and 8MHz processors + +#endif + +// +// Statics +// +SoftSerial *SoftSerial::active_object = 0; +char SoftSerial::_receive_buffer[_SS_MAX_RX_BUFF]; +volatile uint8_t SoftSerial::_receive_buffer_tail = 0; +volatile uint8_t SoftSerial::_receive_buffer_head = 0; + +// +// Debugging +// +// This function generates a brief pulse +// for debugging or measuring on an oscilloscope. +inline void DebugPulse(uint8_t pin, uint8_t count) +{ +#if _DEBUG + volatile uint8_t *pport = portOutputRegister(digitalPinToPort(pin)); + + uint8_t val = *pport; + while (count--) + { + *pport = val | digitalPinToBitMask(pin); + *pport = val; + } +#endif +} + +// +// Private methods +// + +/* static */ +inline void SoftSerial::tunedDelay(uint16_t delay) { + uint8_t tmp=0; + + asm volatile("sbiw %0, 0x01 \n\t" + "ldi %1, 0xFF \n\t" + "cpi %A0, 0xFF \n\t" + "cpc %B0, %1 \n\t" + "brne .-10 \n\t" + : "+r" (delay), "+a" (tmp) + : "0" (delay) + ); +} + +// This function sets the current object as the "listening" +// one and returns true if it replaces another +bool SoftSerial::listen() +{ + if (active_object != this) + { + _buffer_overflow = false; + uint8_t oldSREG = SREG; + cli(); + _receive_buffer_head = _receive_buffer_tail = 0; + active_object = this; + SREG = oldSREG; + return true; + } + + return false; +} + +// +// The receive routine called by the interrupt handler +// +void SoftSerial::recv() +{ + +#if GCC_VERSION < 40302 +// Work-around for avr-gcc 4.3.0 OSX version bug +// Preserve the registers that the compiler misses +// (courtesy of Arduino forum user *etracer*) + asm volatile( + "push r18 \n\t" + "push r19 \n\t" + "push r20 \n\t" + "push r21 \n\t" + "push r22 \n\t" + "push r23 \n\t" + "push r26 \n\t" + "push r27 \n\t" + ::); +#endif + + uint8_t d = 0; + + // If RX line is high, then we don't see any start bit + // so interrupt is probably not for us + if (_inverse_logic ? rx_pin_read() : !rx_pin_read()) + { + // Wait approximately 1/2 of a bit width to "center" the sample + tunedDelay(_rx_delay_centering); + DebugPulse(_DEBUG_PIN2, 1); + + // Read each of the 8 bits + for (uint8_t i=0x1; i; i <<= 1) + { + tunedDelay(_rx_delay_intrabit); + DebugPulse(_DEBUG_PIN2, 1); + uint8_t noti = ~i; + if (rx_pin_read()) + d |= i; + else // else clause added to ensure function timing is ~balanced + d &= noti; + } + + // skip the stop bit + tunedDelay(_rx_delay_stopbit); + DebugPulse(_DEBUG_PIN2, 1); + + if (_inverse_logic) + d = ~d; + + // if buffer full, set the overflow flag and return + if ((_receive_buffer_tail + 1) % _SS_MAX_RX_BUFF != _receive_buffer_head) + { + // save new data in buffer: tail points to where byte goes + _receive_buffer[_receive_buffer_tail] = d; // save new byte + _receive_buffer_tail = (_receive_buffer_tail + 1) % _SS_MAX_RX_BUFF; + } + else + { +#if _DEBUG // for scope: pulse pin as overflow indictator + DebugPulse(_DEBUG_PIN1, 1); +#endif + _buffer_overflow = true; + } + } + +#if GCC_VERSION < 40302 +// Work-around for avr-gcc 4.3.0 OSX version bug +// Restore the registers that the compiler misses + asm volatile( + "pop r27 \n\t" + "pop r26 \n\t" + "pop r23 \n\t" + "pop r22 \n\t" + "pop r21 \n\t" + "pop r20 \n\t" + "pop r19 \n\t" + "pop r18 \n\t" + ::); +#endif +} + +void SoftSerial::tx_pin_write(uint8_t pin_state) +{ + if (pin_state == LOW) + *_transmitPortRegister &= ~_transmitBitMask; + else + *_transmitPortRegister |= _transmitBitMask; +} + +uint8_t SoftSerial::rx_pin_read() +{ + return *_receivePortRegister & _receiveBitMask; +} + +// +// Interrupt handling +// + +/* static */ +inline void SoftSerial::handle_interrupt() +{ + if (active_object) + { + active_object->recv(); + } +} +#if 0 /* Do not use Interrupt Vector here: Interrupt Vector is shared through TinyPinChange library */ +#if defined(PCINT0_vect) +ISR(PCINT0_vect) +{ + SoftSerial::handle_interrupt(); +} +#endif + +#if defined(PCINT1_vect) +ISR(PCINT1_vect) +{ + SoftSerial::handle_interrupt(); +} +#endif + +#if defined(PCINT2_vect) +ISR(PCINT2_vect) +{ + SoftSerial::handle_interrupt(); +} +#endif + +#if defined(PCINT3_vect) +ISR(PCINT3_vect) +{ + SoftSerial::handle_interrupt(); +} +#endif +#endif +// +// Constructor +// +SoftSerial::SoftSerial(uint8_t receivePin, uint8_t transmitPin, bool inverse_logic /* = false */) : + _rx_delay_centering(0), + _rx_delay_intrabit(0), + _rx_delay_stopbit(0), + _tx_delay(0), + _buffer_overflow(false), + _inverse_logic(inverse_logic) +{ +// setTX(transmitPin); + setRX(receivePin); + setTX(transmitPin); + TinyPinChange_RegisterIsr(receivePin, SoftSerial::handle_interrupt); +} + +// +// Destructor +// +SoftSerial::~SoftSerial() +{ + end(); +} + +void SoftSerial::setTX(uint8_t tx) +{ + _transmitBitMask = digitalPinToBitMask(tx); + if(_transmitBitMask!=_receiveBitMask) + { + pinMode(tx, OUTPUT); + digitalWrite(tx, HIGH); + } +// _transmitBitMask = digitalPinToBitMask(tx); + uint8_t port = digitalPinToPort(tx); + _transmitPortRegister = portOutputRegister(port); +} + +void SoftSerial::setRX(uint8_t rx) +{ + pinMode(rx, INPUT); + if (!_inverse_logic) + digitalWrite(rx, HIGH); // pullup for normal logic! + _receivePin = rx; + _receiveBitMask = digitalPinToBitMask(rx); + uint8_t port = digitalPinToPort(rx); + _receivePortRegister = portInputRegister(port); +} + +// +// Public methods +// + +void SoftSerial::begin(long speed) +{ + _rx_delay_centering = _rx_delay_intrabit = _rx_delay_stopbit = _tx_delay = 0; + + for (unsigned i=0; i library is exactly the same as the library but used with the library which allows to share +the Pin Change Interrupt Vector. + monopolizes the Pin Change Interrupt Vector and don't allow sharing. +With , it's possible. Don't forget to #include in your sketch! +RC Navy (2012): http://p.loussouarn.free.fr + +SoftwareSerial.h (formerly NewSoftSerial.h) - +Multi-instance software serial library for Arduino/Wiring +-- Interrupt-driven receive and other improvements by ladyada + (http://ladyada.net) +-- Tuning, circular buffer, derivation from class Print/Stream, + multi-instance support, porting to 8MHz processors, + various optimizations, PROGMEM delay tables, inverse logic and + direct port writing by Mikal Hart (http://www.arduiniana.org) +-- Pin change interrupt macros by Paul Stoffregen (http://www.pjrc.com) +-- 20MHz processor support by Garrett Mace (http://www.macetech.com) +-- ATmega1280/2560 support by Brett Hagman (http://www.roguerobotics.com/) + +This library is free software; you can redistribute it and/or +modify it under the terms of the GNU Lesser General Public +License as published by the Free Software Foundation; either +version 2.1 of the License, or (at your option) any later version. + +This library is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Lesser General Public License for more details. + +You should have received a copy of the GNU Lesser General Public +License along with this library; if not, write to the Free Software +Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +The latest version of this library can always be found at +http://arduiniana.org. +*/ + +#ifndef SoftSerial_h +#define SoftSerial_h + +#include +#include + +#include + +/****************************************************************************** +* Definitions +******************************************************************************/ + +#define _SS_MAX_RX_BUFF 64 // RX buffer size +#ifndef GCC_VERSION +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) +#endif + +class SoftSerial : public Stream +{ +private: + // per object data + uint8_t _receivePin; + uint8_t _receiveBitMask; + volatile uint8_t *_receivePortRegister; + uint8_t _transmitBitMask; + volatile uint8_t *_transmitPortRegister; + + uint16_t _rx_delay_centering; + uint16_t _rx_delay_intrabit; + uint16_t _rx_delay_stopbit; + uint16_t _tx_delay; + + uint16_t _buffer_overflow:1; + uint16_t _inverse_logic:1; + + // static data + static char _receive_buffer[_SS_MAX_RX_BUFF]; + static volatile uint8_t _receive_buffer_tail; + static volatile uint8_t _receive_buffer_head; + static SoftSerial *active_object; + + // private methods + void recv(); + uint8_t rx_pin_read(); + void tx_pin_write(uint8_t pin_state); + void setTX(uint8_t transmitPin); + void setRX(uint8_t receivePin); + + // private static method for timing + static inline void tunedDelay(uint16_t delay); + +public: + // public methods + SoftSerial(uint8_t receivePin, uint8_t transmitPin, bool inverse_logic = false); + ~SoftSerial(); + void begin(long speed); + bool listen(); + void end(); + bool isListening() { return this == active_object; } + bool overflow() { bool ret = _buffer_overflow; _buffer_overflow = false; return ret; } + int peek(); + void txMode(); + void rxMode(); + virtual size_t write(uint8_t byte); + virtual int read(); + virtual int available(); + virtual void flush(); + + using Print::write; + + // public only for easy access by interrupt handlers + static inline void handle_interrupt(); +}; + +// Arduino 0012 workaround +#undef int +#undef char +#undef long +#undef byte +#undef float +#undef abs +#undef round + +#endif diff --git a/hardware/digistump/avr/libraries/SoftSerial/examples/Digi_1io_SerialDbg/Digi_1io_SerialDbg.ino b/hardware/digistump/avr/libraries/SoftSerial/examples/Digi_1io_SerialDbg/Digi_1io_SerialDbg.ino new file mode 100644 index 0000000..cbd0350 --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftSerial/examples/Digi_1io_SerialDbg/Digi_1io_SerialDbg.ino @@ -0,0 +1,64 @@ +/* + _____ ____ __ _ ____ _ _ _ _ + | __ \ / __ \ | \ | | / __ \ | | | | | | | | + | |__| | | / \_| | . \ | | / / \ \ | | | | \ \ / / + | _ / | | _ | |\ \| | | |__| | | | | | \ ' / + | | \ \ | \__/ | | | \ ' | | __ | \ \/ / | | + |_| |_| \____/ |_| \__| |_| |_| \__/ |_| 2013 + + http://p.loussouarn.free.fr + + **************************************** + * Digispark Debug Demo with 1 I/O * + **************************************** + + This sketch demonstrates how to debug a Digispark using a bi-directional serial port using a single I/O. + This approach allows to use the built-in Serial Console of the arduino IDE. + Please, note this solution requires a native RS232 port (rare today) or a RS232/USB adapter on the development PC. + + Hardware Wiring: + =============== + SERIAL SINGLE I/O + DEBUGGING CABLE + ___________________/\__________________ + / \ + ____ + .--------. | \ + | GND |--------------------------------+---o5 \ + | | 47K | | 9o | + | | .--###--' | o4 | + | DEBUG | 4.7K | | 8o | + | TX_RX |-------------------###--+--|<|------o3 | ---> To regular RS232 SubD 9 pins Male of PC + | PIN | ^ | 1N4148 | 7o | or to RS232/USB adapter + | | | '-----------o2 | + '--------' | | 6o | + ATtiny85 Single | o1 / + (Digispark) I/O |____/ + SubD 9 pins + Female +*/ +#include +#include + +#define DEBUG_TX_RX_PIN 2 //Adjust here your Tx/Rx debug pin + +SoftSerial MyDbgSerial(DEBUG_TX_RX_PIN, DEBUG_TX_RX_PIN, true); //true allows to connect to a regular RS232 without RS232 line driver + +void setup() +{ + MyDbgSerial.begin(38400); //After MyDbgSerial.begin(), the serial port is in rxMode by default + MyDbgSerial.txMode(); //Before sending a message, switch to txMode + MyDbgSerial.println(F("\nDebug enabled")); + MyDbgSerial.rxMode(); //switch to rxMode to be ready to receive some commands +} + +void loop() +{ + if(MyDbgSerial.available()) + { + MyDbgSerial.txMode(); + MyDbgSerial.print(F("\nReceived: "));MyDbgSerial.write(MyDbgSerial.read());MyDbgSerial.print(F("\n")); + MyDbgSerial.rxMode(); + } +} + diff --git a/hardware/digistump/avr/libraries/SoftSerial/examples/SoftSerialExample/SoftSerialExample.ino b/hardware/digistump/avr/libraries/SoftSerial/examples/SoftSerialExample/SoftSerialExample.ino new file mode 100644 index 0000000..00406fa --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftSerial/examples/SoftSerialExample/SoftSerialExample.ino @@ -0,0 +1,50 @@ +/* + Software serial multiple serial test + + Receives from the hardware serial, sends to software serial. + Receives from software serial, sends to hardware serial. + + The circuit: + * RX is digital pin 2 (connect to TX of other device) + * TX is digital pin 3 (connect to RX of other device) + + created back in the mists of time + modified 9 Apr 2012 + by Tom Igoe + based on Mikal Hart's example + + This example code is in the public domain. + + adapted from for library which allows sharing the Pin Change Interrupt Vector. + Single difference with : add #include at the top of your sketch. + RC Navy (2012): http://p.loussouarn.free.fr + + */ +#include /* Allows Pin Change Interrupt Vector Sharing */ +#include /* Ne pas oublier d'inclure la librairie qui est utilisee par la librairie */ + +SoftSerial mySerial(2, 3); // RX, TX + +void setup() +{ + // Open serial communications and wait for port to open: + Serial.begin(57600); + while (!Serial) { + ; // wait for serial port to connect. Needed for Leonardo only + } + + + Serial.println("Goodnight moon!"); + + // set the data rate for the SoftwareSerial port + mySerial.begin(4800); + mySerial.println("Hello, world?"); +} + +void loop() // run over and over +{ + if (mySerial.available()) + Serial.write(mySerial.read()); + if (Serial.available()) + mySerial.write(Serial.read()); +} diff --git a/hardware/digistump/avr/libraries/SoftSerial/examples/TwoPortReceive/TwoPortReceive.ino b/hardware/digistump/avr/libraries/SoftSerial/examples/TwoPortReceive/TwoPortReceive.ino new file mode 100644 index 0000000..a1ca89d --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftSerial/examples/TwoPortReceive/TwoPortReceive.ino @@ -0,0 +1,85 @@ +/* + Software serial multple serial test + + Receives from the two software serial ports, + sends to the hardware serial port. + + In order to listen on a software port, you call port.listen(). + When using two software serial ports, you have to switch ports + by listen()ing on each one in turn. Pick a logical time to switch + ports, like the end of an expected transmission, or when the + buffer is empty. This example switches ports when there is nothing + more to read from a port + + The circuit: + Two devices which communicate serially are needed. + * First serial device's TX attached to digital pin 2, RX to pin 3 + * Second serial device's TX attached to digital pin 4, RX to pin 5 + + created 18 Apr. 2011 + modified 9 Apr 2012 + by Tom Igoe + based on Mikal Hart's twoPortRXExample + + This example code is in the public domain. + + */ + +#include +#include /* Ne pas oublier d'inclure la librairie qui est utilisee par la librairie */ + +// software serial #1: TX = digital pin 2, RX = digital pin 3 +SoftSerial portOne(2, 3); + +// software serial #2: TX = digital pin 4, RX = digital pin 5 +SoftSerial portTwo(4, 5); + +void setup() +{ + // Open serial communications and wait for port to open: + Serial.begin(9600); + while (!Serial) { + ; // wait for serial port to connect. Needed for Leonardo only + } + + + // Start each software serial port + portOne.begin(9600); + portTwo.begin(9600); +} + +void loop() +{ + // By default, the last intialized port is listening. + // when you want to listen on a port, explicitly select it: + portOne.listen(); + Serial.println("Data from port one:"); + // while there is data coming in, read it + // and send to the hardware serial port: + while (portOne.available() > 0) { + char inByte = portOne.read(); + Serial.write(inByte); + } + + // blank line to separate data from the two ports: + Serial.println(); + + // Now listen on the second port + portTwo.listen(); + // while there is data coming in, read it + // and send to the hardware serial port: + Serial.println("Data from port two:"); + while (portTwo.available() > 0) { + char inByte = portTwo.read(); + Serial.write(inByte); + } + + // blank line to separate data from the two ports: + Serial.println(); +} + + + + + + diff --git a/hardware/digistump/avr/libraries/SoftSerial/keywords.txt b/hardware/digistump/avr/libraries/SoftSerial/keywords.txt new file mode 100644 index 0000000..e86541f --- /dev/null +++ b/hardware/digistump/avr/libraries/SoftSerial/keywords.txt @@ -0,0 +1,29 @@ +####################################### +# Syntax Coloring Map for SoftSerial +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +SoftSerial KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +end KEYWORD2 +read KEYWORD2 +available KEYWORD2 +isListening KEYWORD2 +overflow KEYWORD2 +flush KEYWORD2 +listen KEYWORD2 +txMode KEYWORD2 +rxMode KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + diff --git a/hardware/digistump/avr/libraries/TinyPinChange/TinyPinChange.cpp b/hardware/digistump/avr/libraries/TinyPinChange/TinyPinChange.cpp new file mode 100644 index 0000000..43b2cd9 --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyPinChange/TinyPinChange.cpp @@ -0,0 +1,178 @@ +/****************************************************************************/ +/* PROJECT: All based on ATtinyX5, ATtinyX4, ATmega328P */ +/* MODULE: PinChange */ +/* VERSION: 1.0 */ +/* DATE: 30/01/2011 */ +/* TARGET: ATtinyX5, ATtinyX4, ATmega328P */ +/* COMPILER: WinAvr (avr-gcc) */ +/* IDE: AVR Studio 4 */ +/* PROGRAMER: AVR-JTAG-ICE MKII */ +/* AUTHOR: P.LOUSSOUARN (P.Loussouarn: http://p.loussouarn.free.fr) */ +/****************************************************************************/ +#include +#include + +/************************************************************************* + MACROS +*************************************************************************/ + +#define PIN_CHANGE_HANDLER_MAX_NB 3 /* ISR max number Pin Change ISR can handle */ + + +/************************************************************************* + GLOBAL VARIABLES +*************************************************************************/ +struct PinChangeStruct +{ + void (*Isr[PIN_CHANGE_HANDLER_MAX_NB])(void); + uint8_t LoadedIsrNb; + uint8_t Event; + uint8_t PinPrev; + uint8_t PinCur; +}; + +struct PinChangePortStruct +{ + PinChangeStruct Port[PIN_CHG_PORT_NB]; +}; + +static volatile struct PinChangePortStruct PinChange; + +/************************************************************************* + INTERRUPT SUB-ROUTINE +*************************************************************************/ +#define DECLARE_PIN_CHANGE_ISR(VirtualPortIdx) \ +ISR(PCINT##VirtualPortIdx##_vect) \ +{ \ +uint8_t Idx; \ + PinChange.Port[VirtualPortIdx].PinCur=(PC_PIN##VirtualPortIdx)&(PC_PCMSK##VirtualPortIdx); \ + PinChange.Port[VirtualPortIdx].Event=PinChange.Port[VirtualPortIdx].PinPrev^PinChange.Port[VirtualPortIdx].PinCur; \ + PinChange.Port[VirtualPortIdx].PinPrev=PinChange.Port[VirtualPortIdx].PinCur; \ + for(Idx=0;Idx, a library for Pin Change Interrupt by RC Navy (2012) +* Supported device ATmega238P (UNO), ATtiny84, ATtiny85 +* +* http://p.loussouarn.free.fr +*/ + +#if defined(ARDUINO) && ARDUINO >= 100 +#include "Arduino.h" +#else +#include "WProgram.h" +#endif + +#include + +#if defined(__AVR_ATtiny25__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__) +/* ATtinyX5 */ +#define PIN_CHG_PORT_NB 1 +#define DigitalPinToPortIdx(p) 0 +#define PC_PIN0 PINB +#define PC_PCMSK0 PCMSK +#else +#if defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__) +/* ATtinyX4 */ +#define PIN_CHG_PORT_NB 2 +#define DigitalPinToPortIdx(p) (((p) <= 7) ? (0) : (((p) <= 10) ? (1) : (0))) +#define PC_PIN0 PINA +#define PC_PCMSK0 PCMSK0 +#define PC_PIN1 PINB +#define PC_PCMSK1 PCMSK1 +#else +/* UNO */ +#define PIN_CHG_PORT_NB 3 +#define DigitalPinToPortIdx(p) (((p) <= 7) ? (2) : (((p) <= 13) ? (0) : (((p) <= 21) ? (1) : (0)))) +#define PC_PIN0 PINB +#define PC_PCMSK0 PCMSK0 +#define PC_PIN1 PINC +#define PC_PCMSK1 PCMSK1 +#define PC_PIN2 PIND +#define PC_PCMSK2 PCMSK2 +#endif +#endif + +void TinyPinChange_Init(void); +int8_t TinyPinChange_RegisterIsr(uint8_t Pin, void(*Isr)(void)); +void TinyPinChange_EnablePin(uint8_t Pin); +void TinyPinChange_DisablePin(uint8_t Pin); +uint8_t TinyPinChange_GetPinEvent(uint8_t VirtualPortIdx); +uint8_t TinyPinChange_GetPinCurSt(uint8_t VirtualPortIdx); +#define TinyPinChange_PinToMsk(Pin) _BV(digitalPinToPCMSKbit(Pin)) + +/*******************************************************/ +/* Application Programming Interface (API) en Francais */ +/*******************************************************/ + +/* Methodes en Francais English native methods */ +#define TinyPinChange_EnregistreFonctionInterruption TinyPinChange_RegisterIsr +#define TinyPinChange_ActiveBroche TinyPinChange_EnablePin +#define TinyPinChange_DesactiveBroche TinyPinChange_DisablePin +#define TinyPinChange_RetourneEvenemenPort TinyPinChange_GetPinEvent +#define TinyPinChange_RetourneEtatCourantPort TinyPinChange_GetPinCurSt +#define TinyPinChange_MasqueDeBroche TinyPinChange_PinToMsk + +#endif diff --git a/hardware/digistump/avr/libraries/TinyPinChange/examples/TinyPinChangeDemo/TinyPinChangeDemo.ino b/hardware/digistump/avr/libraries/TinyPinChange/examples/TinyPinChangeDemo/TinyPinChangeDemo.ino new file mode 100644 index 0000000..ee55a59 --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyPinChange/examples/TinyPinChangeDemo/TinyPinChangeDemo.ino @@ -0,0 +1,159 @@ +/* + _____ ____ __ _ ____ _ _ _ _ + | __ \ / __ \ | \ | | / __ \ | | | | | | | | + | |__| | | / \_| | . \ | | / / \ \ | | | | \ \ / / + | _ / | | _ | |\ \| | | |__| | | | | | \ ' / + | | \ \ | \__/ | | | \ ' | | __ | \ \/ / | | + |_| \_\ \____/ |_| \__| |_| |_| \__/ |_| 2013 + + http://p.loussouarn.free.fr + + ******************************************************* + * library Demo * + * with debugging capabilities using * + * object as single wire serial interface * + ******************************************************* + +This sketch demonstrates how to use library. +It counts all the transitions on 2 different pins. +/!\CAUTION/!\: as library can be shared (and it is with SoftSerial in this sketch) , the user shall test if the changes are related to the declared pins. + +Trick: By connecting Pin#1 to Pin#0 or to Pin#5 through a 1K resistor, you can generate transitions for testing purpose. +Output results are sent to a software serial. + +And the great thing is: using a object as a bi-directionnal software serial port (half-duplex) on a single pin to communicate with the outside world! + +To display the sketch results on a PC (in a Terminal): +1) Build the "Serial One Wire Debug Cable" and plug it to the regular RS232 port as depicted below, +2) Open your favorite Terminal at 38400,n,8,1: HyperTerminal, Teraterm (Windows) or Minicom, GtkTerm (Linux) and CoolTerm (MAC) does the trick. +3) You can also use the Serial Monitor of the arduino IDE: Tools->Serial Port and select your RS232 port (may be an USB virtual port), Rate=38400. +4) To enable the display, type 1, to disable, type 0 in the Terminal/Monitor. + + SERIAL ONE WIRE + DEBUGGING CABLE + _______________ ________________ + / \___/\___/ \ + ____ + .--------. | \ + | GND |--------------------------------+---o5 \ + | | 47K | | 9o | + | | .--###--' | o4 | + | DEBUG | 4.7K | | 8o | + | TX_RX |-------------------###--+--|<|------o3 | ---> To regular RS232 SubD 9 pins Male of PC or Serial/USB adapter + | PIN | ^ | 1N4148 | 7o | + | | | '-----------o2 | + '--------' | | 6o | + ATtiny85 Single | o1 / + (Digispark) I/O |____/ + SubD 9 pins + Female +*/ +#include +#include + +#define LED_PIN 1 + +#define DEBUG_TX_RX_PIN 2 + +#define FIRST_INPUT 0 +#define SECOND_INPUT 5 + +volatile uint16_t FirstInputChangeCount=0; /* Volatile since the variable will be updated in interruption */ +volatile uint16_t SecondInputChangeCount=0; /* Volatile since the variable will be updated in interruption */ + +SoftSerial MySerial(DEBUG_TX_RX_PIN, DEBUG_TX_RX_PIN, true); /* Tx/Rx on a single Pin !!! (Pin#2) */ + +uint8_t VirtualPortNb; +uint8_t VirtualPortNb_; + +void setup() +{ + TinyPinChange_Init(); + + MySerial.begin(38400); /* Trick: use a "high" data rate (less time wasted in ISR and for transmitting each character) */ + + VirtualPortNb=TinyPinChange_RegisterIsr(FIRST_INPUT, InterruptFunctionToCall); + VirtualPortNb_=TinyPinChange_RegisterIsr(SECOND_INPUT, InterruptFunctionToCall); + + /* Enable Pin Change for each pin */ + TinyPinChange_EnablePin(FIRST_INPUT); + TinyPinChange_EnablePin(SECOND_INPUT); + + MySerial.txMode(); + MySerial.println(F("\n*** Tiny PinChange Demo ***")); + MySerial.print(F("Pin "));MySerial.print((int)FIRST_INPUT); + MySerial.print(F(" is part of virtual port "));MySerial.println((int)VirtualPortNb); + + MySerial.print(F("Pin "));MySerial.print((int)SECOND_INPUT); + MySerial.print(F(" is part of virtual port "));MySerial.println((int)VirtualPortNb_); + + MySerial.println(F("As you can see, virtual port is always port 0 for ATtiny85")); + MySerial.println(F("Remember is also designed for UNO, MEGA and ATtiny84 ;-)")); + + pinMode(LED_PIN, OUTPUT); + + MySerial.rxMode(); /* Switch to Rx Mode */ +} + +/* Function called in interruption in case of change on pins */ +void InterruptFunctionToCall(void) +{ +uint8_t PortChange; + + PortChange = TinyPinChange_GetPinEvent(VirtualPortNb); + if(PortChange & TinyPinChange_PinToMsk(FIRST_INPUT)) /* Check FIRST_INPUT has changed */ + { + FirstInputChangeCount++; /* Rising AND Falling edges are counted */ + } + if(PortChange & TinyPinChange_PinToMsk(SECOND_INPUT)) /* Check SECOND_INPUT has changed */ + { + SecondInputChangeCount++; /* Rising AND Falling edges are counted */ + } +} + +void loop() +{ +static boolean State=HIGH, DisplayEnabled=false; +static uint32_t LedStartMs=millis(), DisplayStartMs=millis(); +uint16_t LocalFirstInputChangeCount; +uint16_t LocalSecondInputChangeCount; + + /* Blink the built-in LED */ + if(millis()-LedStartMs >= 500) + { + LedStartMs=millis(); + digitalWrite(LED_PIN, State); + State=!State; /* State will be inverted at the next digitalWrite() */ + } + + /* Get command from single wire SoftSerial */ + if(MySerial.available()) + { + switch(MySerial.read()) + { + case '0': + DisplayEnabled=false; + break; + + case '1': + DisplayEnabled=true; + break; + } + } + + /* Diplay Transition numbers every second */ + if((millis()-DisplayStartMs >= 1000) && DisplayEnabled) + { + DisplayStartMs=millis(); + noInterrupts(); /* Mandatory since counters are 16 bits */ + LocalFirstInputChangeCount = FirstInputChangeCount; + LocalSecondInputChangeCount = SecondInputChangeCount; + interrupts(); + MySerial.txMode(); + MySerial.print(F("FirstInputChangeCount="));MySerial.println(LocalFirstInputChangeCount); + MySerial.print(F("SecondInputChangeCount="));MySerial.println(LocalSecondInputChangeCount); + MySerial.rxMode(); + } + +} + diff --git a/hardware/digistump/avr/libraries/TinyPinChange/keywords.txt b/hardware/digistump/avr/libraries/TinyPinChange/keywords.txt new file mode 100644 index 0000000..0f006bc --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyPinChange/keywords.txt @@ -0,0 +1,29 @@ +####################################### +# Syntax Coloring Map TinyPinChange +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### +TinyPinChange KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### +TinyPinChange_Init KEYWORD2 +TinyPinChange_RegisterIsr KEYWORD2 +TinyPinChange_EnregistreFonctionInterruption KEYWORD2 +TinyPinChange_EnablePin KEYWORD2 +TinyPinChange_ActiveBroche KEYWORD2 +TinyPinChange_DisablePin KEYWORD2 +TinyPinChange_DesactiveBroche KEYWORD2 +TinyPinChange_GetPinEvent KEYWORD2 +TinyPinChange_RetourneEvenemenPort KEYWORD2 +TinyPinChange_GetPinCurSt KEYWORD2 +TinyPinChange_RetourneEtatCourantPort KEYWORD2 +TinyPinChange_PinToMsk KEYWORD2 +TinyPinChange_MasqueDeBroche KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### diff --git a/hardware/digistump/avr/libraries/TinyRTClib/README.md b/hardware/digistump/avr/libraries/TinyRTClib/README.md new file mode 100644 index 0000000..ccfdfc1 --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyRTClib/README.md @@ -0,0 +1,11 @@ +TinyRTClib +========== + +DS1307's Arduino Adafruit library modified to run on Digispark's attiny85. + +I've searched everywhere for a DS1307 library that could work on my Digispark but found none. + +This is the Adafruit version (https://github.com/adafruit/RTClib) with their examples modified to work on Digispark's attiny85. + +**I'm unable to push the files into the right folders by now. That's why I've them renamed to the folders name and slashs... +**Will try to add to the right place later. diff --git a/hardware/digistump/avr/libraries/TinyRTClib/TinyRTClib.cpp b/hardware/digistump/avr/libraries/TinyRTClib/TinyRTClib.cpp new file mode 100644 index 0000000..c386814 --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyRTClib/TinyRTClib.cpp @@ -0,0 +1,243 @@ +// Code by JeeLabs http://news.jeelabs.org/code/ +// Released to the public domain! Enjoy! + +// --Refactored by nGoline http://arduino.ngoline.com +// --to fit Digispark and the attiny85 + +#include +#include +#include "TinyRTClib.h" + +#define DS1307_ADDRESS 0x68 +#define SECONDS_PER_DAY 86400L + +#define SECONDS_FROM_1970_TO_2000 946684800 + +#if (ARDUINO >= 100) + #include // capital A so it is error prone on case-sensitive filesystems +#else + #include +#endif + +int i = 0; //The new wire library needs to take an int when you are sending for the zero register +//////////////////////////////////////////////////////////////////////////////// +// utility code, some of this could be exposed in the DateTime API if needed + +const uint8_t daysInMonth [] PROGMEM = { 31,28,31,30,31,30,31,31,30,31,30,31 }; //has to be const or compiler compaints + +// number of days since 2000/01/01, valid for 2001..2099 +static uint16_t date2days(uint16_t y, uint8_t m, uint8_t d) { + if (y >= 2000) + y -= 2000; + uint16_t days = d; + for (uint8_t i = 1; i < m; ++i) + days += pgm_read_byte(daysInMonth + i - 1); + if (m > 2 && y % 4 == 0) + ++days; + return days + 365 * y + (y + 3) / 4 - 1; +} + +static long time2long(uint16_t days, uint8_t h, uint8_t m, uint8_t s) { + return ((days * 24L + h) * 60 + m) * 60 + s; +} + +//////////////////////////////////////////////////////////////////////////////// +// DateTime implementation - ignores time zones and DST changes +// NOTE: also ignores leap seconds, see http://en.wikipedia.org/wiki/Leap_second + +DateTime::DateTime (uint32_t t) { + t -= SECONDS_FROM_1970_TO_2000; // bring to 2000 timestamp from 1970 + + ss = t % 60; + t /= 60; + mm = t % 60; + t /= 60; + hh = t % 24; + uint16_t days = t / 24; + uint8_t leap; + for (yOff = 0; ; ++yOff) { + leap = yOff % 4 == 0; + if (days < 365 + leap) + break; + days -= 365 + leap; + } + for (m = 1; ; ++m) { + uint8_t daysPerMonth = pgm_read_byte(daysInMonth + m - 1); + if (leap && m == 2) + ++daysPerMonth; + if (days < daysPerMonth) + break; + days -= daysPerMonth; + } + d = days + 1; +} + +DateTime::DateTime (uint16_t year, uint8_t month, uint8_t day, uint8_t hour, uint8_t min, uint8_t sec) { + if (year >= 2000) + year -= 2000; + yOff = year; + m = month; + d = day; + hh = hour; + mm = min; + ss = sec; +} + +static uint8_t conv2d(const char* p) { + uint8_t v = 0; + if ('0' <= *p && *p <= '9') + v = *p - '0'; + return 10 * v + *++p - '0'; +} + +// A convenient constructor for using "the compiler's time": +// DateTime now (__DATE__, __TIME__); +// NOTE: using PSTR would further reduce the RAM footprint +DateTime::DateTime (const char* date, const char* time) { + // sample input: date = "Dec 26 2009", time = "12:34:56" + yOff = conv2d(date + 9); + // Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec + switch (date[0]) { + case 'J': m = date[1] == 'a' ? 1 : m = date[2] == 'n' ? 6 : 7; break; + case 'F': m = 2; break; + case 'A': m = date[2] == 'r' ? 4 : 8; break; + case 'M': m = date[2] == 'r' ? 3 : 5; break; + case 'S': m = 9; break; + case 'O': m = 10; break; + case 'N': m = 11; break; + case 'D': m = 12; break; + } + d = conv2d(date + 4); + hh = conv2d(time); + mm = conv2d(time + 3); + ss = conv2d(time + 6); +} + +uint8_t DateTime::dayOfWeek() const { + uint16_t day = date2days(yOff, m, d); + return (day + 6) % 7; // Jan 1, 2000 is a Saturday, i.e. returns 6 +} + +uint32_t DateTime::unixtime(void) const { + uint32_t t; + uint16_t days = date2days(yOff, m, d); + t = time2long(days, hh, mm, ss); + t += SECONDS_FROM_1970_TO_2000; // seconds from 1970 to 2000 + + return t; +} + +//////////////////////////////////////////////////////////////////////////////// +// RTC_DS1307 implementation + +static uint8_t bcd2bin (uint8_t val) { return val - 6 * (val >> 4); } +static uint8_t bin2bcd (uint8_t val) { return val + 6 * (val / 10); } + +uint8_t RTC_DS1307::begin(void) { + return 1; +} + + +#if (ARDUINO >= 100) + +uint8_t RTC_DS1307::isrunning(void) { + TinyWireM.beginTransmission(DS1307_ADDRESS); + TinyWireM.send(i); + TinyWireM.endTransmission(); + + TinyWireM.requestFrom(DS1307_ADDRESS, 1); + uint8_t ss = TinyWireM.receive(); + return !(ss>>7); +} + +void RTC_DS1307::adjust(const DateTime& dt) { + TinyWireM.beginTransmission(DS1307_ADDRESS); + TinyWireM.send(i); + TinyWireM.send(bin2bcd(dt.second())); + TinyWireM.send(bin2bcd(dt.minute())); + TinyWireM.send(bin2bcd(dt.hour())); + TinyWireM.send(bin2bcd(0)); + TinyWireM.send(bin2bcd(dt.day())); + TinyWireM.send(bin2bcd(dt.month())); + TinyWireM.send(bin2bcd(dt.year() - 2000)); + TinyWireM.send(i); + TinyWireM.endTransmission(); +} + +DateTime RTC_DS1307::now() { + TinyWireM.beginTransmission(DS1307_ADDRESS); + TinyWireM.send(i); + TinyWireM.endTransmission(); + + TinyWireM.requestFrom(DS1307_ADDRESS, 7); + uint8_t ss = bcd2bin(TinyWireM.receive() & 0x7F); + uint8_t mm = bcd2bin(TinyWireM.receive()); + uint8_t hh = bcd2bin(TinyWireM.receive()); + TinyWireM.receive(); + uint8_t d = bcd2bin(TinyWireM.receive()); + uint8_t m = bcd2bin(TinyWireM.receive()); + uint16_t y = bcd2bin(TinyWireM.receive()) + 2000; + + return DateTime (y, m, d, hh, mm, ss); +} + +#else + +uint8_t RTC_DS1307::isrunning(void) { + TinyWireM.beginTransmission(DS1307_ADDRESS); + TinyWireM.send(i); + TinyWireM.endTransmission(); + + TinyWireM.requestFrom(DS1307_ADDRESS, 1); + uint8_t ss = TinyWireM.receive(); + return !(ss>>7); +} + +void RTC_DS1307::adjust(const DateTime& dt) { + TinyWireM.beginTransmission(DS1307_ADDRESS); + TinyWireM.send(i); + TinyWireM.send(bin2bcd(dt.second())); + TinyWireM.send(bin2bcd(dt.minute())); + TinyWireM.send(bin2bcd(dt.hour())); + TinyWireM.send(bin2bcd(0)); + TinyWireM.send(bin2bcd(dt.day())); + TinyWireM.send(bin2bcd(dt.month())); + TinyWireM.send(bin2bcd(dt.year() - 2000)); + TinyWireM.send(i); + TinyWireM.endTransmission(); +} + +DateTime RTC_DS1307::now() { + TinyWireM.beginTransmission(DS1307_ADDRESS); + TinyWireM.send(i); + TinyWireM.endTransmission(); + + TinyWireM.requestFrom(DS1307_ADDRESS, 7); + uint8_t ss = bcd2bin(TinyWireM.receive() & 0x7F); + uint8_t mm = bcd2bin(TinyWireM.receive()); + uint8_t hh = bcd2bin(TinyWireM.receive()); + TinyWireM.receive(); + uint8_t d = bcd2bin(TinyWireM.receive()); + uint8_t m = bcd2bin(TinyWireM.receive()); + uint16_t y = bcd2bin(TinyWireM.receive()) + 2000; + + return DateTime (y, m, d, hh, mm, ss); +} + +#endif + + +//////////////////////////////////////////////////////////////////////////////// +// RTC_Millis implementation + +long RTC_Millis::offset = 0; + +void RTC_Millis::adjust(const DateTime& dt) { + offset = dt.unixtime() - millis() / 1000; +} + +DateTime RTC_Millis::now() { + return (uint32_t)(offset + millis() / 1000); +} + +//////////////////////////////////////////////////////////////////////////////// diff --git a/hardware/digistump/avr/libraries/TinyRTClib/TinyRTClib.h b/hardware/digistump/avr/libraries/TinyRTClib/TinyRTClib.h new file mode 100644 index 0000000..aeeaaef --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyRTClib/TinyRTClib.h @@ -0,0 +1,51 @@ +// Code by JeeLabs http://news.jeelabs.org/code/ +// Released to the public domain! Enjoy! + +// --Refactored by nGoline http://arduino.ngoline.com +// --to fit Digispark and the attiny85 + +// Simple general-purpose date/time class (no TZ / DST / leap second handling!) +class DateTime { +public: + DateTime (uint32_t t =0); + DateTime (uint16_t year, uint8_t month, uint8_t day, + uint8_t hour =0, uint8_t min =0, uint8_t sec =0); + DateTime (const char* date, const char* time); + uint16_t year() const { return 2000 + yOff; } + uint8_t month() const { return m; } + uint8_t day() const { return d; } + uint8_t hour() const { return hh; } + uint8_t minute() const { return mm; } + uint8_t second() const { return ss; } + uint8_t dayOfWeek() const; + + // 32-bit times as seconds since 1/1/2000 + long secondstime() const; + // 32-bit times as seconds since 1/1/1970 + uint32_t unixtime(void) const; + +protected: + uint8_t yOff, m, d, hh, mm, ss; +}; + +// RTC based on the DS1307 chip connected via I2C and the Wire library +// -- Now using the TinyWireM library +class RTC_DS1307 { +public: + static uint8_t begin(void); + static void adjust(const DateTime& dt); + uint8_t isrunning(void); + static DateTime now(); +}; + +// RTC using the internal millis() clock, has to be initialized before use +// NOTE: this clock won't be correct once the millis() timer rolls over (>49d?) +class RTC_Millis { +public: + static void begin(const DateTime& dt) { adjust(dt); } + static void adjust(const DateTime& dt); + static DateTime now(); + +protected: + static long offset; +}; diff --git a/hardware/digistump/avr/libraries/TinyRTClib/examples/datecalc/datecalc.pde b/hardware/digistump/avr/libraries/TinyRTClib/examples/datecalc/datecalc.pde new file mode 100644 index 0000000..b55dfe6 --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyRTClib/examples/datecalc/datecalc.pde @@ -0,0 +1,65 @@ +// Simple date conversions and calculations + +#include +#include "TinyRTClib.h" + +void showDate(const char* txt, const DateTime& dt) { + Serial.print(txt); + Serial.print(' '); + Serial.print(dt.year(), DEC); + Serial.print('/'); + Serial.print(dt.month(), DEC); + Serial.print('/'); + Serial.print(dt.day(), DEC); + Serial.print(' '); + Serial.print(dt.hour(), DEC); + Serial.print(':'); + Serial.print(dt.minute(), DEC); + Serial.print(':'); + Serial.print(dt.second(), DEC); + + Serial.print(" = "); + Serial.print(dt.unixtime()); + Serial.print("s / "); + Serial.print(dt.unixtime() / 86400L); + Serial.print("d since 1970"); + + Serial.println(); +} + +void setup () { + Serial.begin(115200); + + DateTime dt0 (0, 1, 1, 0, 0, 0); + showDate("dt0", dt0); + + DateTime dt1 (1, 1, 1, 0, 0, 0); + showDate("dt1", dt1); + + DateTime dt2 (2009, 1, 1, 0, 0, 0); + showDate("dt2", dt2); + + DateTime dt3 (2009, 1, 2, 0, 0, 0); + showDate("dt3", dt3); + + DateTime dt4 (2009, 1, 27, 0, 0, 0); + showDate("dt4", dt4); + + DateTime dt5 (2009, 2, 27, 0, 0, 0); + showDate("dt5", dt5); + + DateTime dt6 (2009, 12, 27, 0, 0, 0); + showDate("dt6", dt6); + + DateTime dt7 (dt6.unixtime() + 3600); // one hour later + showDate("dt7", dt7); + + DateTime dt8 (dt6.unixtime() + 86400L); // one day later + showDate("dt8", dt8); + + DateTime dt9 (dt6.unixtime() + 7 * 86400L); // one week later + showDate("dt9", dt9); +} + +void loop () { +} diff --git a/hardware/digistump/avr/libraries/TinyRTClib/examples/ds1307/ds1307.pde b/hardware/digistump/avr/libraries/TinyRTClib/examples/ds1307/ds1307.pde new file mode 100644 index 0000000..80a1f0c --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyRTClib/examples/ds1307/ds1307.pde @@ -0,0 +1,61 @@ +// Date and time functions using a DS1307 RTC connected via I2C and Wire lib + +#include +#include "TinyRTClib.h" + +RTC_DS1307 RTC; + +void setup () { + Serial.begin(115200); + TinyWireM.begin(); + RTC.begin(); + + if (! RTC.isrunning()) { + Serial.println("RTC is NOT running!"); + // following line sets the RTC to the date & time this sketch was compiled + RTC.adjust(DateTime(__DATE__, __TIME__)); + } +} + +void loop () { + DateTime now = RTC.now(); + + Serial.print(now.year(), DEC); + Serial.print('/'); + Serial.print(now.month(), DEC); + Serial.print('/'); + Serial.print(now.day(), DEC); + Serial.print(' '); + Serial.print(now.hour(), DEC); + Serial.print(':'); + Serial.print(now.minute(), DEC); + Serial.print(':'); + Serial.print(now.second(), DEC); + Serial.println(); + + Serial.print(" since midnight 1/1/1970 = "); + Serial.print(now.unixtime()); + Serial.print("s = "); + Serial.print(now.unixtime() / 86400L); + Serial.println("d"); + + // calculate a date which is 7 days and 30 seconds into the future + DateTime future (now.unixtime() + 7 * 86400L + 30); + + Serial.print(" now + 7d + 30s: "); + Serial.print(future.year(), DEC); + Serial.print('/'); + Serial.print(future.month(), DEC); + Serial.print('/'); + Serial.print(future.day(), DEC); + Serial.print(' '); + Serial.print(future.hour(), DEC); + Serial.print(':'); + Serial.print(future.minute(), DEC); + Serial.print(':'); + Serial.print(future.second(), DEC); + Serial.println(); + + Serial.println(); + delay(3000); +} diff --git a/hardware/digistump/avr/libraries/TinyRTClib/examples/softrtc/softrtc.pde b/hardware/digistump/avr/libraries/TinyRTClib/examples/softrtc/softrtc.pde new file mode 100644 index 0000000..1aa4974 --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyRTClib/examples/softrtc/softrtc.pde @@ -0,0 +1,52 @@ +// Date and time functions using just software, based on millis() & timer + +#include +#include "TinyRTClib.h" + +RTC_Millis RTC; + +void setup () { + Serial.begin(115200); + // following line sets the RTC to the date & time this sketch was compiled + RTC.begin(DateTime(__DATE__, __TIME__)); +} + +void loop () { + DateTime now = RTC.now(); + + Serial.print(now.year(), DEC); + Serial.print('/'); + Serial.print(now.month(), DEC); + Serial.print('/'); + Serial.print(now.day(), DEC); + Serial.print(' '); + Serial.print(now.hour(), DEC); + Serial.print(':'); + Serial.print(now.minute(), DEC); + Serial.print(':'); + Serial.print(now.second(), DEC); + Serial.println(); + + Serial.print(" seconds since 1970: "); + Serial.println(now.unixtime()); + + // calculate a date which is 7 days and 30 seconds into the future + DateTime future (now.unixtime() + 7 * 86400L + 30); + + Serial.print(" now + 7d + 30s: "); + Serial.print(future.year(), DEC); + Serial.print('/'); + Serial.print(future.month(), DEC); + Serial.print('/'); + Serial.print(future.day(), DEC); + Serial.print(' '); + Serial.print(future.hour(), DEC); + Serial.print(':'); + Serial.print(future.minute(), DEC); + Serial.print(':'); + Serial.print(future.second(), DEC); + Serial.println(); + + Serial.println(); + delay(3000); +} diff --git a/hardware/digistump/avr/libraries/TinyRTClib/keywords.txt b/hardware/digistump/avr/libraries/TinyRTClib/keywords.txt new file mode 100644 index 0000000..88bd02c --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyRTClib/keywords.txt @@ -0,0 +1,34 @@ +####################################### +# Syntax Coloring Map For RTC +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +DateTime KEYWORD1 +RTC_DS1307 KEYWORD1 +RTC_Millis KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +year KEYWORD2 +month KEYWORD2 +day KEYWORD2 +hour KEYWORD2 +minute KEYWORD2 +second KEYWORD2 +dayOfWeek KEYWORD2 +secondstime KEYWORD2 +unixtime KEYWORD2 +begin KEYWORD2 +adjust KEYWORD2 +isrunning KEYWORD2 +now KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + diff --git a/hardware/digistump/avr/libraries/TinySoftPwm/TinySoftPwm.cpp b/hardware/digistump/avr/libraries/TinySoftPwm/TinySoftPwm.cpp new file mode 100644 index 0000000..94b27df --- /dev/null +++ b/hardware/digistump/avr/libraries/TinySoftPwm/TinySoftPwm.cpp @@ -0,0 +1,151 @@ +// a Tiny optimized Software PWM Manager (all pins must be part of the same port) +// Only resources RAM/Program Memory of used pins are declared in the code at compilation time. +// based largely on Atmel's AVR136: Low-Jitter Multi-Channel Software PWM Application Note: +// http://www.atmel.com/dyn/resources/prod_documents/doc8020.pdf +// RC Navy 2013 +// http://p.loussouarn.free.fr + +#include + +#define TINY_SOFT_PWM_PORT PORTB +#define TINY_SOFT_PWM_DDR DDRB + +#define TINY_SOFT_PWM_CLEAR_PIN(RamIdx) (PortPwmTo1 &= GET_INV_PIN_MSK(RamIdx)) + +#define TINY_SOFT_PWM_DECLARE_PIN(Px) TINY_SOFT_PWM_DDR |= (1<<(Px)); PortPwmMask |= (1<<(Px)) + +#define GET_INV_PIN_MSK(RamIdx) ((uint8_t)pgm_read_byte(&RamIdxToInvPinMsk[(RamIdx)])) + +uint8_t RamIdxToInvPinMsk[] PROGMEM ={ +#if (TINY_SOFT_PWM_USES_P0 == 1) + ~(1<<0), +#endif +#if (TINY_SOFT_PWM_USES_P1 == 1) + ~(1<<1), +#endif +#if (TINY_SOFT_PWM_USES_P2 == 1) + ~(1<<2), +#endif +#if (TINY_SOFT_PWM_USES_P3 == 1) + ~(1<<3), +#endif +#if (TINY_SOFT_PWM_USES_P4 == 1) + ~(1<<4), +#endif +#if (TINY_SOFT_PWM_USES_P5 == 1) + ~(1<<5), +#endif + }; +static uint8_t Compare[TINY_SOFT_PWM_CH_MAX]; +volatile uint8_t PwmOrder[TINY_SOFT_PWM_CH_MAX]; +static uint8_t PortPwmMask=0; +volatile uint8_t PortPwmTo1=0x00; +volatile uint8_t PortPwmTo0=0xFF; +static uint8_t _TickMax=255; + +static uint8_t PwmToPwmMax(uint8_t Pwm); + +void TinySoftPwm_begin(uint8_t TickMax, uint8_t PwmInit) +{ +uint8_t oldSREG = SREG; + cli(); + // set the direction of the used ports and update PortPwmMask +#if (TINY_SOFT_PWM_USES_P0 == 1) + TINY_SOFT_PWM_DECLARE_PIN(PB0); +#endif +#if (TINY_SOFT_PWM_USES_P1 == 1) + TINY_SOFT_PWM_DECLARE_PIN(PB1); +#endif +#if (TINY_SOFT_PWM_USES_P2 == 1) + TINY_SOFT_PWM_DECLARE_PIN(PB2); +#endif +#if (TINY_SOFT_PWM_USES_P3 == 1) + TINY_SOFT_PWM_DECLARE_PIN(PB3); +#endif +#if (TINY_SOFT_PWM_USES_P4 == 1) + TINY_SOFT_PWM_DECLARE_PIN(PB4); +#endif +#if (TINY_SOFT_PWM_USES_P5 == 1) + TINY_SOFT_PWM_DECLARE_PIN(PB5); +#endif + _TickMax=TickMax; + PortPwmTo1=PortPwmMask; + // initialise all channels + for(uint8_t i=0 ; i= 1) + Compare[0] = PwmOrder[0]; // verbose code for speed +#endif +#if (TINY_SOFT_PWM_CH_MAX >= 2) + Compare[1] = PwmOrder[1]; +#endif +#if (TINY_SOFT_PWM_CH_MAX >= 3) + Compare[2] = PwmOrder[2]; +#endif +#if (TINY_SOFT_PWM_CH_MAX >= 4) + Compare[3] = PwmOrder[3]; +#endif +#if (TINY_SOFT_PWM_CH_MAX >= 5) + Compare[4] = PwmOrder[4]; +#endif +#if (TINY_SOFT_PWM_CH_MAX >= 6) + Compare[5] = PwmOrder[5]; +#endif + PortPwmTo1 = PortPwmMask; // set all port used pins high + } + // clear port pin on compare match (executed on next interrupt) +#if (TINY_SOFT_PWM_CH_MAX >= 1) + if(Compare[0] == OvfCount) TINY_SOFT_PWM_CLEAR_PIN(0); +#endif +#if (TINY_SOFT_PWM_CH_MAX >= 2) + if(Compare[1] == OvfCount) TINY_SOFT_PWM_CLEAR_PIN(1); +#endif +#if (TINY_SOFT_PWM_CH_MAX >= 3) + if(Compare[2] == OvfCount) TINY_SOFT_PWM_CLEAR_PIN(2); +#endif +#if (TINY_SOFT_PWM_CH_MAX >= 4) + if(Compare[3] == OvfCount) TINY_SOFT_PWM_CLEAR_PIN(3); +#endif +#if (TINY_SOFT_PWM_CH_MAX >= 5) + if(Compare[4] == OvfCount) TINY_SOFT_PWM_CLEAR_PIN(4); +#endif +#if (TINY_SOFT_PWM_CH_MAX >= 6) + if(Compare[5] == OvfCount) TINY_SOFT_PWM_CLEAR_PIN(5); +#endif +} diff --git a/hardware/digistump/avr/libraries/TinySoftPwm/TinySoftPwm.h b/hardware/digistump/avr/libraries/TinySoftPwm/TinySoftPwm.h new file mode 100644 index 0000000..c163146 --- /dev/null +++ b/hardware/digistump/avr/libraries/TinySoftPwm/TinySoftPwm.h @@ -0,0 +1,86 @@ +#ifndef TinySoftPwm_h +#define TinySoftPwm_h + +// a Tiny optimized Software PWM Manager (all pins must be part of the same port) +// Only resources RAM/Program Memory of used pins are declared in the code at compilation time. +// based largely on Atmel's AVR136: Low-Jitter Multi-Channel Software PWM Application Note: +// http://www.atmel.com/dyn/resources/prod_documents/doc8020.pdf +// RC Navy 2013 +// http://p.loussouarn.free.fr + +#if defined(ARDUINO) && ARDUINO >= 100 +#include "Arduino.h" +#else +#include "WProgram.h" +#endif + +#include + +/*************************************************/ +/* Define here the PIN to use with Tiny Soft PWM */ +/* Unused Pin(s) SHALL be commented */ +/*************************************************/ +//#define TINY_SOFT_PWM_USES_P0 +#define TINY_SOFT_PWM_USES_P1 +#define TINY_SOFT_PWM_USES_P2 +//#define TINY_SOFT_PWM_USES_P3 /* /!\ used for USB on DigiSpark: do not use it for PWM if DigiUSB is also used /!\ */ +//#define TINY_SOFT_PWM_USES_P4 /* /!\ used for USB on DigiSpark: do not use it for PWM if DigiUSB is also used /!\ */ +#define TINY_SOFT_PWM_USES_P5 + + + + + +/*******************************************************************/ +/* Do NOT modify below: it's used to optimize RAM and Program size */ +/*******************************************************************/ +#ifdef TINY_SOFT_PWM_USES_P0 +#undef TINY_SOFT_PWM_USES_P0 +#define TINY_SOFT_PWM_USES_P0 1 +#else +#define TINY_SOFT_PWM_USES_P0 0 +#endif + +#ifdef TINY_SOFT_PWM_USES_P1 +#undef TINY_SOFT_PWM_USES_P1 +#define TINY_SOFT_PWM_USES_P1 1 +#else +#define TINY_SOFT_PWM_USES_P1 0 +#endif + +#ifdef TINY_SOFT_PWM_USES_P2 +#undef TINY_SOFT_PWM_USES_P2 +#define TINY_SOFT_PWM_USES_P2 1 +#else +#define TINY_SOFT_PWM_USES_P2 0 +#endif + +#ifdef TINY_SOFT_PWM_USES_P3 +#undef TINY_SOFT_PWM_USES_P3 +#define TINY_SOFT_PWM_USES_P3 1 +#else +#define TINY_SOFT_PWM_USES_P3 0 +#endif + +#ifdef TINY_SOFT_PWM_USES_P4 +#undef TINY_SOFT_PWM_USES_P4 +#define TINY_SOFT_PWM_USES_P4 1 +#else +#define TINY_SOFT_PWM_USES_P4 0 +#endif + +#ifdef TINY_SOFT_PWM_USES_P5 +#undef TINY_SOFT_PWM_USES_P5 +#define TINY_SOFT_PWM_USES_P5 1 +#else +#define TINY_SOFT_PWM_USES_P5 0 +#endif + +#define TINY_SOFT_PWM_CH_MAX (TINY_SOFT_PWM_USES_P0 + TINY_SOFT_PWM_USES_P1 + TINY_SOFT_PWM_USES_P2 + TINY_SOFT_PWM_USES_P3 + TINY_SOFT_PWM_USES_P4 + TINY_SOFT_PWM_USES_P5) + + +void TinySoftPwm_begin(uint8_t TickMax, uint8_t PwmInit); +void TinySoftPwm_analogWrite(uint8_t PinIdx, uint8_t Pwm); +void TinySoftPwm_process(void); + +#endif diff --git a/hardware/digistump/avr/libraries/TinySoftPwm/examples/TinySoftPwmDemo/TinySoftPwmDemo.ino b/hardware/digistump/avr/libraries/TinySoftPwm/examples/TinySoftPwmDemo/TinySoftPwmDemo.ino new file mode 100644 index 0000000..4ef17a9 --- /dev/null +++ b/hardware/digistump/avr/libraries/TinySoftPwm/examples/TinySoftPwmDemo/TinySoftPwmDemo.ino @@ -0,0 +1,71 @@ +#include + +/* + _____ ____ __ _ ____ _ _ _ _ + | __ \ / __ \ | \ | | / __ \ | | | | | | | | + | |__| | | / \_| | . \ | | / / \ \ | | | | \ \ / / + | _ / | | _ | |\ \| | | |__| | | | | | \ ' / + | | \ \ | \__/ | | | \ ' | | __ | \ \/ / | | + |_| \_\ \____/ |_| \__| |_| |_| \__/ |_| 2013 + + http://p.loussouarn.free.fr + + **************************************** + * library Demo * + **************************************** + +This sketch increases the luminosity of the built-in LED of the Digispark. +When the luminosity reaches its maximum, the luminosity decreases. +When the luminosity reaches its minimum, the luminosity increases, and so on... + +Note: +==== +Declare the Pin(s) used in "librarie/TinySoftPwm/TinySoftPwm.h" +In this sketch, #define TINY_SOFT_PWM_USES_P1 must be enabled (not commented) since it uses the DigiSpark built-in LED wired on P1. + +In this basic example, TinySoftPwm_process() is called periodically using micros(), but it is recommanded to call it from a timer ISR +to ensure a better periodicity. + +*/ + +#define BUILT_IN_LED_PIN 1 /* Digispark Model A (Rev2) built-in LED pin number (Change it to 2 for Model B) */ + +void setup() +{ + TinySoftPwm_begin(128, 0); /* 128 x TinySoftPwm_process() calls before overlap (Frequency tuning), 0 = PWM init for all declared pins */ +} + +void loop() +{ +static uint32_t StartUs=micros(); +static uint32_t StartMs=millis(); +static uint8_t Pwm=0; +static int8_t Dir=1; + + /***********************************************************/ + /* Call TinySoftPwm_process() with a period of 60 us */ + /* The PWM frequency = 128 x 60 # 7.7 ms -> F # 130Hz */ + /* 128 is the first argument passed to TinySoftPwm_begin() */ + /***********************************************************/ + if((micros() - StartUs) >= 60) + { + /* We arrived here every 60 microseconds */ + StartUs=micros(); + TinySoftPwm_process(); /* This function shall be called periodically (like here, based on micros(), or in a timer ISR) */ + } + + /*************************************************************/ + /* Increment/decrement PWM on LED Pin with a period of 10 ms */ + /*************************************************************/ + if((millis()-StartMs) >= 10) + { + /* We arrived here every 10 milliseconds */ + StartMs=millis(); + Pwm+=Dir; /* increment or decrement PWM depending of sign of Dir */ + TinySoftPwm_analogWrite(BUILT_IN_LED_PIN, Pwm); /* Update built-in LED for Digispark */ + if(Pwm==255) Dir=-1; /* if PWM reaches the maximum: change direction */ + if(Pwm==0) Dir=+1; /* if PWM reaches the minimum: change direction */ + } +} + + diff --git a/hardware/digistump/avr/libraries/TinySoftPwm/keywords.txt b/hardware/digistump/avr/libraries/TinySoftPwm/keywords.txt new file mode 100644 index 0000000..2377b95 --- /dev/null +++ b/hardware/digistump/avr/libraries/TinySoftPwm/keywords.txt @@ -0,0 +1,19 @@ +####################################### +# Syntax Coloring Map TinySoftPwm +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### +TinySoftPwm KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### +TinySoftPwm_begin KEYWORD2 +TinySoftPwm_analogWrite KEYWORD2 +TinySoftPwm_process KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### diff --git a/hardware/digistump/avr/libraries/TinyWireM/TinyWireM.cpp b/hardware/digistump/avr/libraries/TinyWireM/TinyWireM.cpp new file mode 100644 index 0000000..24ae065 --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyWireM/TinyWireM.cpp @@ -0,0 +1,96 @@ +/* + TinyWireM.cpp - a wrapper class for TWI/I2C Master library for the ATtiny on Arduino + 1/21/2011 BroHogan - brohoganx10 at gmail dot com + + **** See TinyWireM.h for Credits and Usage information **** + + This library is free software; you can redistribute it and/or modify it under the + terms of the GNU General Public License as published by the Free Software + Foundation; either version 2.1 of the License, or any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A + PARTICULAR PURPOSE. See the GNU General Public License for more details. +*/ + +extern "C" { + //#include "USI_TWI_Master.h" + //#include + //#include + //#include +} + +#include "USI_TWI_Master.h" +#include "TinyWireM.h" + + +// Initialize Class Variables ////////////////////////////////////////////////// + uint8_t USI_TWI::USI_Buf[USI_BUF_SIZE]; // holds I2C send and receive data + uint8_t USI_TWI::USI_BufIdx = 0; // current number of bytes in the send buff + uint8_t USI_TWI::USI_LastRead = 0; // number of bytes read so far + uint8_t USI_TWI::USI_BytesAvail = 0; // number of bytes requested but not read + +// Constructors //////////////////////////////////////////////////////////////// + +USI_TWI::USI_TWI(){ +} + +// Public Methods ////////////////////////////////////////////////////////////// + +void USI_TWI::begin(){ // initialize I2C lib + USI_TWI_Master_Initialise(); +} + +void USI_TWI::beginTransmission(uint8_t slaveAddr){ // setup address & write bit + USI_BufIdx = 0; + USI_Buf[USI_BufIdx] = (slaveAddr<= USI_BUF_SIZE) return; // dont blow out the buffer + USI_BufIdx++; // inc for next byte in buffer + USI_Buf[USI_BufIdx] = data; +} + +uint8_t USI_TWI::endTransmission(){ // actually sends the buffer + bool xferOK = false; + uint8_t errorCode = 0; + xferOK = USI_TWI_Start_Read_Write(USI_Buf,USI_BufIdx+1); // core func that does the work + USI_BufIdx = 0; + if (xferOK) return 0; + else { // there was an error + errorCode = USI_TWI_Get_State_Info(); // this function returns the error number + return errorCode; + } +} + +uint8_t USI_TWI::requestFrom(uint8_t slaveAddr, uint8_t numBytes){ // setup for receiving from slave + bool xferOK = false; + uint8_t errorCode = 0; + USI_LastRead = 0; + USI_BytesAvail = numBytes; // save this off in a global + numBytes++; // add extra byte to transmit header + USI_Buf[0] = (slaveAddr< +#define USI_SEND 0 // indicates sending to TWI +#define USI_RCVE 1 // indicates receiving from TWI +#define USI_BUF_SIZE 16 // bytes in message buffer + +class USI_TWI +{ + private: + static uint8_t USI_Buf[]; // holds I2C send and receive data + static uint8_t USI_BufIdx; // current number of bytes in the send buff + static uint8_t USI_LastRead; // number of bytes read so far + static uint8_t USI_BytesAvail; // number of bytes requested but not read + + public: + USI_TWI(); + void begin(); + void beginTransmission(uint8_t); + void send(uint8_t); + uint8_t endTransmission(); + uint8_t requestFrom(uint8_t, uint8_t); + uint8_t receive(); + uint8_t available(); +}; + +extern USI_TWI TinyWireM; + +#endif + diff --git a/hardware/digistump/avr/libraries/TinyWireM/USI_TWI_Master.cpp b/hardware/digistump/avr/libraries/TinyWireM/USI_TWI_Master.cpp new file mode 100644 index 0000000..eea99cb --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyWireM/USI_TWI_Master.cpp @@ -0,0 +1,343 @@ +/***************************************************************************** +* +* +* File USI_TWI_Master.c compiled with gcc +* Date Friday, 10/31/08 Boo! +* Updated by jkl +* + +* AppNote : AVR310 - Using the USI module as a TWI Master +* +* Extensively modified to provide complete I2C driver. +* +*Notes: +* - T4_TWI and T2_TWI delays are modified to work with 1MHz default clock +* and now use hard code values. They would need to change +* for other clock rates. Refer to the Apps Note. +* +* 12/17/08 Added USI_TWI_Start_Memory_Read Routine -jkl +* Note msg buffer will have slave adrs ( with write bit set) and memory adrs; +* length should be these two bytes plus the number of bytes to read. +****************************************************************************/ +#include +#if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define F_CPU 16500000UL + +#elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) +#define F_CPU 16000000UL // Sets up the default speed for delay.h +#endif + +#include +#include +#include "USI_TWI_Master.h" + +unsigned char USI_TWI_Start_Transceiver_With_Data( unsigned char * , unsigned char ); +unsigned char USI_TWI_Master_Transfer( unsigned char ); +unsigned char USI_TWI_Master_Stop( void ); +unsigned char USI_TWI_Master_Start( void ); + +union USI_TWI_state +{ + unsigned char errorState; // Can reuse the TWI_state for error states since it will not be needed if there is an error. + struct + { + unsigned char addressMode : 1; + unsigned char masterWriteDataMode : 1; + unsigned char memReadMode : 1; + unsigned char unused : 5; + }; +} USI_TWI_state; + +/*--------------------------------------------------------------- + USI TWI single master initialization function +---------------------------------------------------------------*/ +void USI_TWI_Master_Initialise( void ) +{ + PORT_USI |= (1< (unsigned char*)RAMEND) // Test if address is outside SRAM space + { + USI_TWI_state.errorState = USI_TWI_DATA_OUT_OF_BOUND; + return (FALSE); + } + if(msgSize <= 1) // Test if the transmission buffer is empty + { + USI_TWI_state.errorState = USI_TWI_NO_DATA; + return (FALSE); + } +#endif + +#ifdef NOISE_TESTING // Test if any unexpected conditions have arrived prior to this execution. + if( USISR & (1<4,7us +#define T4_TWI 4 // >4,0us + +// Defines error code generating +//#define PARAM_VERIFICATION +//#define NOISE_TESTING +#define SIGNAL_VERIFY // This should probably be on always. + +/**************************************************************************** + Bit and byte definitions +****************************************************************************/ +#define TWI_READ_BIT 0 // Bit position for R/W bit in "address byte". +#define TWI_ADR_BITS 1 // Bit position for LSB of the slave address bits in the init byte. +#define TWI_NACK_BIT 0 // Bit position for (N)ACK bit. + +// Note these have been renumbered from the Atmel Apps Note. Most likely errors are now +// lowest numbers so they're easily recognized as LED flashes. +#define USI_TWI_NO_DATA 0x08 // Transmission buffer is empty +#define USI_TWI_DATA_OUT_OF_BOUND 0x09 // Transmission buffer is outside SRAM space +#define USI_TWI_UE_START_CON 0x07 // Unexpected Start Condition +#define USI_TWI_UE_STOP_CON 0x06 // Unexpected Stop Condition +#define USI_TWI_UE_DATA_COL 0x05 // Unexpected Data Collision (arbitration) +#define USI_TWI_NO_ACK_ON_DATA 0x02 // The slave did not acknowledge all data +#define USI_TWI_NO_ACK_ON_ADDRESS 0x01 // The slave did not acknowledge the address +#define USI_TWI_MISSING_START_CON 0x03 // Generated Start Condition not detected on bus +#define USI_TWI_MISSING_STOP_CON 0x04 // Generated Stop Condition not detected on bus +#define USI_TWI_BAD_MEM_READ 0x0A // Error during external memory read + +// Device dependant defines ADDED BACK IN FROM ORIGINAL ATMEL .H + +#if defined(__AVR_AT90Mega169__) | defined(__AVR_ATmega169__) | \ + defined(__AVR_AT90Mega165__) | defined(__AVR_ATmega165__) | \ + defined(__AVR_ATmega325__) | defined(__AVR_ATmega3250__) | \ + defined(__AVR_ATmega645__) | defined(__AVR_ATmega6450__) | \ + defined(__AVR_ATmega329__) | defined(__AVR_ATmega3290__) | \ + defined(__AVR_ATmega649__) | defined(__AVR_ATmega6490__) + #define DDR_USI DDRE + #define PORT_USI PORTE + #define PIN_USI PINE + #define PORT_USI_SDA PORTE5 + #define PORT_USI_SCL PORTE4 + #define PIN_USI_SDA PINE5 + #define PIN_USI_SCL PINE4 +#endif + +#if defined(__AVR_ATtiny25__) | defined(__AVR_ATtiny45__) | defined(__AVR_ATtiny85__) | \ + defined(__AVR_AT90Tiny26__) | defined(__AVR_ATtiny26__) | defined(__AVR_ATtiny167__) | \ + defined(__AVR_ATtiny87__) + #define DDR_USI DDRB + #define PORT_USI PORTB + #define PIN_USI PINB + #define PORT_USI_SDA PORTB0 + #define PORT_USI_SCL PORTB2 + #define PIN_USI_SDA PINB0 + #define PIN_USI_SCL PINB2 +#endif + +#if defined(__AVR_AT90Tiny2313__) | defined(__AVR_ATtiny2313__) + #define DDR_USI DDRB + #define PORT_USI PORTB + #define PIN_USI PINB + #define PORT_USI_SDA PORTB5 + #define PORT_USI_SCL PORTB7 + #define PIN_USI_SDA PINB5 + #define PIN_USI_SCL PINB7 +#endif + +/* From the original .h +// Device dependant defines - These for ATtiny2313. // CHANGED FOR ATtiny85 + + #define DDR_USI DDRB + #define PORT_USI PORTB + #define PIN_USI PINB + #define PORT_USI_SDA PORTB0 // was PORTB5 - N/U + #define PORT_USI_SCL PORTB2 // was PORTB7 - N/U + #define PIN_USI_SDA PINB0 // was PINB5 + #define PIN_USI_SCL PINB2 // was PINB7 +*/ + +// General defines +#define TRUE 1 +#define FALSE 0 + +//********** Prototypes **********// + +void USI_TWI_Master_Initialise( void ); +unsigned char USI_TWI_Start_Random_Read( unsigned char * , unsigned char ); +unsigned char USI_TWI_Start_Read_Write( unsigned char * , unsigned char ); +unsigned char USI_TWI_Get_State_Info( void ); diff --git a/hardware/digistump/avr/libraries/TinyWireM/examples/Tiny85_Temp/Tiny85_Temp.pde b/hardware/digistump/avr/libraries/TinyWireM/examples/Tiny85_Temp/Tiny85_Temp.pde new file mode 100644 index 0000000..552aebb --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyWireM/examples/Tiny85_Temp/Tiny85_Temp.pde @@ -0,0 +1,78 @@ +/* ATtiny85 as an I2C Master Ex1 BroHogan 1/21/11 + * I2C master reading DS1621 temperature sensor. (display with leds) + * SETUP: + * ATtiny Pin 1 = (RESET) N/U ATtiny Pin 2 = (D3) LED3 + * ATtiny Pin 3 = (D4) to LED1 ATtiny Pin 4 = GND + * ATtiny Pin 5 = SDA on DS1621 ATtiny Pin 6 = (D1) to LED2 + * ATtiny Pin 7 = SCK on DS1621 ATtiny Pin 8 = VCC (2.7-5.5V) + * NOTE! - It's very important to use pullups on the SDA & SCL lines! + * DS1621 wired per data sheet. This ex assumes A0-A2 are set LOW for an addeess of 0x48 + * TinyWireM USAGE & CREDITS: - see TinyWireM.h + * NOTES: + * The ATtiny85 + DS1621 draws 1.7mA @5V when leds are not on and not reading temp. + * Using sleep mode, they draw .2 @5V @ idle - see http://brownsofa.org/blog/archives/261 + */ + +#include // I2C Master lib for ATTinys which use USI + +#define DS1621_ADDR 0x48 // 7 bit I2C address for DS1621 temperature sensor +#define LED1_PIN 4 // ATtiny Pin 3 +#define LED2_PIN 1 // ATtiny Pin 6 +#define LED3_PIN 3 // ATtiny Pin 2 + +int tempC = 0; // holds temp in C +int tempF = 0; // holds temp in F + + +void setup(){ + pinMode(LED1_PIN,OUTPUT); + pinMode(LED2_PIN,OUTPUT); + pinMode(LED3_PIN,OUTPUT); + Blink(LED1_PIN,2); // show it's alive + TinyWireM.begin(); // initialize I2C lib + Init_Temp(); // Setup DS1621 + delay (3000); +} + + +void loop(){ + Get_Temp(); + Blink(LED1_PIN,tempC/10); // blink 10's of temperature on LED 1 + delay (1000); + Blink(LED2_PIN,tempC%10); // blink 1's of temperature on LED 2 + delay (4000); // wait a few sec before next reading +} + + +void Init_Temp(){ // Setup the DS1621 for one-shot mode + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xAC); // Access Command Register + TinyWireM.send(B00000001); // Using one-shot mode for battery savings + //TinyWireM.send(B00000000); // if setting continious mode for fast reads + TinyWireM.endTransmission(); // Send to the slave +} + + +void Get_Temp(){ // Get the temperature from a DS1621 + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xEE); // if one-shot, start conversions now + TinyWireM.endTransmission(); // Send 1 byte to the slave + delay(750); // if one-shot, must wait ~750 ms for conversion + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xAA); // read temperature (for either mode) + TinyWireM.endTransmission(); // Send 1 byte to the slave + TinyWireM.requestFrom(DS1621_ADDR,1); // Request 1 byte from slave + tempC = TinyWireM.receive(); // get the temperature + tempF = tempC * 9 / 5 + 32; // convert to Fahrenheit +} + + +void Blink(byte led, byte times){ // poor man's GUI + for (byte i=0; i< times; i++){ + digitalWrite(led,HIGH); + delay (400); + digitalWrite(led,LOW); + delay (175); + } +} + diff --git a/hardware/digistump/avr/libraries/TinyWireM/examples/Tiny85_Temp_LCD/Tiny85_Temp_LCD.pde b/hardware/digistump/avr/libraries/TinyWireM/examples/Tiny85_Temp_LCD/Tiny85_Temp_LCD.pde new file mode 100644 index 0000000..5efed12 --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyWireM/examples/Tiny85_Temp_LCD/Tiny85_Temp_LCD.pde @@ -0,0 +1,96 @@ +/* ATtiny85 as an I2C Master Ex2 BroHogan 1/21/11 + * I2C master reading DS1621 temperature sensor. Display to I2C GPIO LED. + * SETUP: + * ATtiny Pin 1 = (RESET) N/U ATtiny Pin 2 = (D3) N/U + * ATtiny Pin 3 = (D4) to LED1 ATtiny Pin 4 = GND + * ATtiny Pin 5 = SDA on DS1621 & GPIO ATtiny Pin 6 = (D1) to LED2 + * ATtiny Pin 7 = SCK on DS1621 & GPIO ATtiny Pin 8 = VCC (2.7-5.5V) + * NOTE! - It's very important to use pullups on the SDA & SCL lines! + * DS1621 wired per data sheet. This ex assumes A0-A2 are set LOW for an addeess of 0x48 + * PCA8574A GPIO was used wired per instructions in "info" folder in the LiquidCrystal_I2C lib. + * This ex assumes A0-A2 are set HIGH for an addeess of 0x3F + * LiquidCrystal_I2C lib was modified for ATtiny - on Playground with TinyWireM lib. + * TinyWireM USAGE & CREDITS: - see TinyWireM.h + */ + +//#define DEBUG +#include // I2C Master lib for ATTinys which use USI +#include // for LCD w/ GPIO MODIFIED for the ATtiny85 + +#define GPIO_ADDR 0x3F // (PCA8574A A0-A2 @5V) typ. A0-A3 Gnd 0x20 / 0x38 for A +#define DS1621_ADDR 0x48 // 7 bit I2C address for DS1621 temperature sensor +#define LED1_PIN 4 // ATtiny Pin 3 +#define LED2_PIN 1 // ATtiny Pin 6 + +int tempC = 0; // holds temp in C +int tempF = 0; // holds temp in F + +LiquidCrystal_I2C lcd(GPIO_ADDR,16,2); // set address & 16 chars / 2 lines + + +void setup(){ +#ifdef DEBUG + pinMode(LED1_PIN,OUTPUT); + pinMode(LED2_PIN,OUTPUT); + Blink(LED1_PIN,2); // show it's alive +#endif + TinyWireM.begin(); // initialize I2C lib + Init_Temp(); // Setup DS1621 + lcd.init(); // initialize the lcd + lcd.backlight(); // Print a message to the LCD. + lcd.print("Hello, Temp!"); + delay (2000); +} + + +void loop(){ + Get_Temp(); // read current temperature + lcd.clear(); // display it + lcd.print("C: "); + lcd.print(tempC,DEC); + lcd.setCursor(7,0); + lcd.print("F: "); + lcd.print(tempF,DEC); +#ifdef DEBUG + Blink(LED1_PIN,tempC/10); // blink 10's of temperature on LED 1 + delay (1000); + Blink(LED2_PIN,tempC%10); // blink 1's of temperature on LED 2 +#endif + delay (4000); // wait a few sec before next reading +} + + +void Init_Temp(){ // Setup the DS1621 for one-shot mode + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xAC); // Access Command Register + TinyWireM.send(B00000001); // Using one-shot mode for battery savings + //TinyWireM.send(B00000000); // if setting continious mode for fast reads + TinyWireM.endTransmission(); // Send to the slave +} + + +void Get_Temp(){ // Get the temperature from a DS1621 + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xEE); // if one-shot, start conversions now + TinyWireM.endTransmission(); // Send 1 byte to the slave + delay(750); // if one-shot, must wait ~750 ms for conversion + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xAA); // read temperature (for either mode) + TinyWireM.endTransmission(); // Send 1 byte to the slave + TinyWireM.requestFrom(DS1621_ADDR,1); // Request 1 byte from slave + tempC = TinyWireM.receive(); // get the temperature + tempF = tempC * 9 / 5 + 32; // convert to Fahrenheit +} + + +#ifdef DEBUG +void Blink(byte led, byte times){ // poor man's GUI + for (byte i=0; i< times; i++){ + digitalWrite(led,HIGH); + delay (400); + digitalWrite(led,LOW); + delay (175); + } +} +#endif + diff --git a/hardware/digistump/avr/libraries/TinyWireM/examples/Tiny85_Temp_LCD_RTC/Tiny85_Temp_LCD_RTC.pde b/hardware/digistump/avr/libraries/TinyWireM/examples/Tiny85_Temp_LCD_RTC/Tiny85_Temp_LCD_RTC.pde new file mode 100644 index 0000000..42674cc --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyWireM/examples/Tiny85_Temp_LCD_RTC/Tiny85_Temp_LCD_RTC.pde @@ -0,0 +1,199 @@ +/* ATtiny85 as an I2C Master Ex3 BroHogan 1/22/11 + * I2C master reading DS1621 temperature sensor & DS1307 RTC. Display to I2C GPIO LED. + * SETUP: + * ATtiny Pin 1 = (RESET) N/U ATtiny Pin 2 = (D3) N/U + * ATtiny Pin 3 = (D4) to LED1 ATtiny Pin 4 = GND + * ATtiny Pin 5 = SDA on all devices ATtiny Pin 6 = (D1) to LED2 + * ATtiny Pin 7 = SCK on all devices ATtiny Pin 8 = VCC (2.7-5.5V) + * NOTE! - It's very important to use pullups on the SDA & SCL lines! + * DS1621 wired per data sheet. This ex assumes A0-A2 are set LOW for an addeess of 0x48 + * DS1307 wired per data sheet. This ex assumes A0-A2 are set LOW for an addeess of 0x68 + * PCA8574A GPIO was used wired per instructions in "info" folder in the LiquidCrystal_I2C lib. + * This ex assumes A0-A2 are set HIGH for an addeess of 0x3F + * LiquidCrystal_I2C lib was modified for ATtiny - on Playground with TinyWireM lib. + * TinyWireM USAGE & CREDITS: - see TinyWireM.h + */ + +//#define DEBUG +#include // I2C Master lib for ATTinys which use USI +#include // for LCD w/ GPIO MODIFIED for the ATtiny85 + +#define GPIO_ADDR 0x3F // (PCA8574A A0-A2 @5V) typ. A0-A3 Gnd 0x20 / 0x38 for A +#define DS1307_ADDR 0x68 // I2C real time clock +#define DS1621_ADDR 0x48 // 7 bit I2C address for DS1621 temperature sensor +#define LED1_PIN 4 // ATtiny Pin 3 +#define LED2_PIN 1 // ATtiny Pin 6 +//#define HR24 true + +int tempC = 0; // holds temp in C +int tempF = 0; // holds temp in F +byte seconds,minutes,hours,day_of_week,days,months,years,PM,hour12,DST; +char timeString[10]; // HH:MM 12 Hr. no AM/PM or 24 Hr (based on param) +char dateString[10]; // MM/DD or DD/MM (based on param)- no year +bool HR24; // 12/24 Hr Time and date + +LiquidCrystal_I2C lcd(GPIO_ADDR,16,2); // set address & 16 chars / 2 lines + + +void setup(){ +#ifdef DEBUG + pinMode(LED1_PIN,OUTPUT); + pinMode(LED2_PIN,OUTPUT); + Blink(LED1_PIN,3); // show it's alive +#endif + TinyWireM.begin(); // initialize I2C lib + Init_Temp(); // Setup DS1621 + lcd.init(); // initialize the lcd + lcd.backlight(); // Print a message to the LCD. + lcd.print("Hello, Temp!"); + delay (2000); +} + + +void loop(){ + Get_Temp(); // read current temperature + Get_Time(); // read current time + lcd.clear(); // display it + lcd.print("C"); + lcd.print((char)223); + lcd.print(": "); + lcd.print(tempC,DEC); + lcd.setCursor(9,0); + lcd.print("F"); + lcd.print((char)223); + lcd.print(": "); + lcd.print(tempF,DEC); + lcd.setCursor(0,1); + lcd.print(timeString); + lcd.setCursor(9,1); + lcd.print(dateString); +#ifdef DEBUG + Blink(LED1_PIN,tempC/10); // blink 10's of temperature on LED 1 + delay (1000); + Blink(LED2_PIN,tempC%10); // blink 1's of temperature on LED 2 +#endif + HR24 = ! HR24; // flip the format + delay (4000); // wait a few sec before next reading +} + + +void Init_Temp(){ // Setup the DS1621 for one-shot mode + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xAC); // Access Command Register + TinyWireM.send(B00000001); // Using one-shot mode for battery savings + //TinyWireM.send(B00000000); // if setting continious mode for fast reads + TinyWireM.endTransmission(); // Send to the slave +} + + +void Get_Temp(){ // Get the temperature from a DS1621 + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xEE); // if one-shot, start conversions now + TinyWireM.endTransmission(); // Send 1 byte to the slave + delay(750); // if one-shot, must wait ~750 ms for conversion + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xAA); // read temperature (for either mode) + TinyWireM.endTransmission(); // Send 1 byte to the slave + TinyWireM.requestFrom(DS1621_ADDR,1); // Request 1 byte from slave + tempC = TinyWireM.receive(); // get the temperature + tempF = tempC * 9 / 5 + 32; // convert to Fahrenheit +} + + +void Get_Time(){ // get the time and date from the DS1307 chip + byte wireRet = 0; + memset(timeString,0,sizeof(timeString)); // initialize the strings + memset(dateString,0,sizeof(dateString)); + + TinyWireM.beginTransmission(DS1307_ADDR); // reset DS1307 register pointer + TinyWireM.send(0); + wireRet = TinyWireM.endTransmission(); + if (wireRet) { // report any send esrrors + lcd.clear(); + lcd.print("SendError: "); + lcd.print(wireRet,DEC); + delay(1500); + } + wireRet = TinyWireM.requestFrom(DS1307_ADDR, 7); // request 7 bytes from DS1307 + if (wireRet) { // report any receive esrrors + lcd.clear(); + lcd.print("RcveError: "); + lcd.print(wireRet,DEC); + delay(1500); + } +#ifdef DEBUG + lcd.clear(); + lcd.print("Before Reads: "); + lcd.print(TinyWireM.available(),DEC); // testing TinyWireM.available() + delay(1500); +#endif + seconds = bcdToDec(TinyWireM.receive()); // handle the 7 bytes received + minutes = bcdToDec(TinyWireM.receive()); + hours = bcdToDec(TinyWireM.receive()); + day_of_week = TinyWireM.receive(); + days = bcdToDec(TinyWireM.receive()); + months = bcdToDec(TinyWireM.receive()); + years = bcdToDec(TinyWireM.receive()); +#ifdef DEBUG + lcd.clear(); + lcd.print("After Reads: "); + lcd.print(TinyWireM.available(),DEC); // testing TinyWireM.available() + delay(1500); +#endif + // deal with AM/PM global and 12 hour clock + if (hours >= 12) PM = true; + else PM = false; + if (hours > 12)hour12 = hours - 12; + else hour12 = hours; + if (hours == 0) hour12 = 12; + + // make time string + if (HR24) AppendToString (hours,timeString); // add 24 hour time to string + else AppendToString (hour12,timeString); // add 12 hour time to string + strcat(timeString,":"); + if (minutes < 10) strcat(timeString,"0"); + AppendToString (minutes,timeString); // add MINUTES to string + if (!HR24){ + if (hours >= 12) strcat(timeString," PM"); // deal with AM/PM + else strcat(timeString," AM"); + } + // make date string + if (HR24)AppendToString (days,dateString); // add DAY to string + else AppendToString (months,dateString); // add MONTH to string + strcat(dateString,"/"); + if (HR24)AppendToString (months,dateString); // add MONTH to string + else AppendToString (days,dateString); // add DAY to string + strcat(dateString,"/"); + if (years < 10) strcat(dateString,"0"); + AppendToString (years,dateString); // add YEAR to string +} + + +void AppendToString (byte bValue, char *pString){ // appends a byte to string passed + char tempStr[6]; + memset(tempStr,'\0',sizeof(tempStr)); + itoa(bValue,tempStr,10); + strcat(pString,tempStr); +} + + +byte bcdToDec(byte val) { // Convert binary coded decimal to normal decimal numbers + return ((val / 16 * 10) + (val % 16)); +} + + +#ifdef DEBUG +void Blink(byte led, byte times){ // poor man's GUI + for (byte i=0; i< times; i++){ + digitalWrite(led,HIGH); + delay (400); + digitalWrite(led,LOW); + delay (175); + } +} +#endif + + + + + diff --git a/hardware/digistump/avr/libraries/TinyWireM/keywords.txt b/hardware/digistump/avr/libraries/TinyWireM/keywords.txt new file mode 100644 index 0000000..b6b61c3 --- /dev/null +++ b/hardware/digistump/avr/libraries/TinyWireM/keywords.txt @@ -0,0 +1,29 @@ +####################################### +# Syntax Coloring Map For TinyWireM +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +beginTransmission KEYWORD2 +endTransmission KEYWORD2 +requestFrom KEYWORD2 +send KEYWORD2 +receive KEYWORD2 + +####################################### +# Instances (KEYWORD2) +####################################### + +TinyWireM KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + diff --git a/hardware/digistump/avr/libraries/VirtualWire/CHANGES b/hardware/digistump/avr/libraries/VirtualWire/CHANGES new file mode 100644 index 0000000..592d0e0 --- /dev/null +++ b/hardware/digistump/avr/libraries/VirtualWire/CHANGES @@ -0,0 +1 @@ +See VirtulWire.h for latest change log diff --git a/hardware/digistump/avr/libraries/VirtualWire/LICENSE b/hardware/digistump/avr/libraries/VirtualWire/LICENSE new file mode 100644 index 0000000..da124e1 --- /dev/null +++ b/hardware/digistump/avr/libraries/VirtualWire/LICENSE @@ -0,0 +1,17 @@ +This software is Copyright (C) 2008 Mike McCauley. Use is subject to license +conditions. The main licensing options available are GPL V2 or Commercial: + +Open Source Licensing GPL V2 + +This is the appropriate option if you want to share the source code of your +application with everyone you distribute it to, and you also want to give them +the right to share who uses it. If you wish to use this software under Open +Source Licensing, you must contribute all your source code to the open source +community in accordance with the GPL Version 2 when your application is +distributed. See http://www.gnu.org/copyleft/gpl.html + +Commercial Licensing + +This is the appropriate option if you are creating proprietary applications +and you are not prepared to distribute and share the source code of your +application. Contact info@open.com.au for details. diff --git a/hardware/digistump/avr/libraries/VirtualWire/MANIFEST b/hardware/digistump/avr/libraries/VirtualWire/MANIFEST new file mode 100644 index 0000000..805a14e --- /dev/null +++ b/hardware/digistump/avr/libraries/VirtualWire/MANIFEST @@ -0,0 +1,14 @@ +VirtualWire/doc +VirtualWire/LICENSE +VirtualWire/README +VirtualWire/Makefile +VirtualWire/VirtualWire.cpp +VirtualWire/VirtualWire.h +VirtualWire/CHANGES +VirtualWire/MANIFEST +VirtualWire/keywords.txt +VirtualWire/util/crc16.h +VirtualWire/examples/client/client.pde +VirtualWire/examples/transmitter/transmitter.pde +VirtualWire/examples/receiver/receiver.pde +VirtualWire/examples/server/server.pde diff --git a/hardware/digistump/avr/libraries/VirtualWire/Makefile b/hardware/digistump/avr/libraries/VirtualWire/Makefile new file mode 100644 index 0000000..fb53d5c --- /dev/null +++ b/hardware/digistump/avr/libraries/VirtualWire/Makefile @@ -0,0 +1,26 @@ +# Makefile +# +# Makefile for the Arduino VirtualWire project +# +# Author: Mike McCauley (mikem@airspayce.com) +# Copyright (C) 2011 Mike McCauley +# $Id: Makefile,v 1.1 2013/01/14 06:49:29 mikem Exp mikem $ + +PROJNAME = VirtualWire +# Dont forget to also change the version at the top of RF22.h: +DISTFILE = $(PROJNAME)-1.15.zip + +all: doxygen dist upload + +doxygen: + doxygen project.cfg + +ci: + (cd ..;ci -l `cat $(PROJNAME)/MANIFEST`) + +dist: + (cd ..; zip $(PROJNAME)/$(DISTFILE) `cat $(PROJNAME)/MANIFEST`) + +upload: + rsync -avz $(DISTFILE) doc/ www.airspayce.com:public_html/mikem/arduino/$(PROJNAME) + rsync -avz ../../doc/VirtualWire.pdf doc/ www.airspayce.com:public_html/mikem/arduino/ diff --git a/hardware/digistump/avr/libraries/VirtualWire/README b/hardware/digistump/avr/libraries/VirtualWire/README new file mode 100644 index 0000000..1ea8627 --- /dev/null +++ b/hardware/digistump/avr/libraries/VirtualWire/README @@ -0,0 +1,8 @@ +Virtual Wire + +This is the VirtualWire library for Arduino +It provides a simple message passing protocol for a range of inexpensive +transmitter and receiver modules. + +See http://www.open.com.au/mikem/arduino/VirtualWire.pdf for full documentation. + diff --git a/hardware/digistump/avr/libraries/VirtualWire/VirtualWire.cpp b/hardware/digistump/avr/libraries/VirtualWire/VirtualWire.cpp new file mode 100644 index 0000000..8ef3378 --- /dev/null +++ b/hardware/digistump/avr/libraries/VirtualWire/VirtualWire.cpp @@ -0,0 +1,662 @@ +// VirtualWire.cpp +// +// Virtual Wire implementation for Arduino +// See the README file in this directory fdor documentation +// See also +// ASH Transceiver Software Designer's Guide of 2002.08.07 +// http://www.rfm.com/products/apnotes/tr_swg05.pdf +// +// Changes: +// 1.5 2008-05-25: fixed a bug that could prevent messages with certain +// bytes sequences being received (false message start detected) +// 1.6 2011-09-10: Patch from David Bath to prevent unconditional reenabling of the receiver +// at end of transmission. +// +// Author: Mike McCauley (mikem@airspayce.com) +// Copyright (C) 2008 Mike McCauley +// $Id: VirtualWire.cpp,v 1.9 2013/02/14 22:02:11 mikem Exp mikem $ + + +#if defined(ARDUINO) + #if (ARDUINO < 100) + #include "WProgram.h" + #endif +#elif defined(__MSP430G2452__) || defined(__MSP430G2553__) // LaunchPad specific + #include "legacymsp430.h" + #include "Energia.h" +#else // error + #error Platform not defined +#endif + +#include "VirtualWire.h" +#include + + +static uint8_t vw_tx_buf[(VW_MAX_MESSAGE_LEN * 2) + VW_HEADER_LEN] + = {0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x2a, 0x38, 0x2c}; + +// Number of symbols in vw_tx_buf to be sent; +static uint8_t vw_tx_len = 0; + +// Index of the next symbol to send. Ranges from 0 to vw_tx_len +static uint8_t vw_tx_index = 0; + +// Bit number of next bit to send +static uint8_t vw_tx_bit = 0; + +// Sample number for the transmitter. Runs 0 to 7 during one bit interval +static uint8_t vw_tx_sample = 0; + +// Flag to indicated the transmitter is active +static volatile uint8_t vw_tx_enabled = 0; + +// Total number of messages sent +static uint16_t vw_tx_msg_count = 0; + +// The digital IO pin number of the press to talk, enables the transmitter hardware +static uint8_t vw_ptt_pin = 10; +static uint8_t vw_ptt_inverted = 0; + +// The digital IO pin number of the receiver data +static uint8_t vw_rx_pin = 11; + +// The digital IO pin number of the transmitter data +static uint8_t vw_tx_pin = 12; + +// Current receiver sample +static uint8_t vw_rx_sample = 0; + +// Last receiver sample +static uint8_t vw_rx_last_sample = 0; + +// PLL ramp, varies between 0 and VW_RX_RAMP_LEN-1 (159) over +// VW_RX_SAMPLES_PER_BIT (8) samples per nominal bit time. +// When the PLL is synchronised, bit transitions happen at about the +// 0 mark. +static uint8_t vw_rx_pll_ramp = 0; + +// This is the integrate and dump integral. If there are <5 0 samples in the PLL cycle +// the bit is declared a 0, else a 1 +static uint8_t vw_rx_integrator = 0; + +// Flag indictate if we have seen the start symbol of a new message and are +// in the processes of reading and decoding it +static uint8_t vw_rx_active = 0; + +// Flag to indicate that a new message is available +static volatile uint8_t vw_rx_done = 0; + +// Flag to indicate the receiver PLL is to run +static uint8_t vw_rx_enabled = 0; + +// Last 12 bits received, so we can look for the start symbol +static uint16_t vw_rx_bits = 0; + +// How many bits of message we have received. Ranges from 0 to 12 +static uint8_t vw_rx_bit_count = 0; + +// The incoming message buffer +static uint8_t vw_rx_buf[VW_MAX_MESSAGE_LEN]; + +// The incoming message expected length +static uint8_t vw_rx_count = 0; + +// The incoming message buffer length received so far +static volatile uint8_t vw_rx_len = 0; + +// Number of bad messages received and dropped due to bad lengths +static uint8_t vw_rx_bad = 0; + +// Number of good messages received +static uint8_t vw_rx_good = 0; + +// 4 bit to 6 bit symbol converter table +// Used to convert the high and low nybbles of the transmitted data +// into 6 bit symbols for transmission. Each 6-bit symbol has 3 1s and 3 0s +// with at most 3 consecutive identical bits +static uint8_t symbols[] = +{ + 0xd, 0xe, 0x13, 0x15, 0x16, 0x19, 0x1a, 0x1c, + 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c, 0x32, 0x34 +}; + +// This new feature allows to call an external function from the timer interrupt (interesting for small microcontroller without many timers) +static void (*_Funct)(void)=NULL; + +// Cant really do this as a real C++ class, since we need to have +// an ISR +extern "C" +{ + +// Compute CRC over count bytes. +// This should only be ever called at user level, not interrupt level +uint16_t vw_crc(uint8_t *ptr, uint8_t count) +{ + uint16_t crc = 0xffff; + + while (count-- > 0) + crc = _crc_ccitt_update(crc, *ptr++); + return crc; +} + +// Convert a 6 bit encoded symbol into its 4 bit decoded equivalent +uint8_t vw_symbol_6to4(uint8_t symbol) +{ + uint8_t i; + + // Linear search :-( Could have a 64 byte reverse lookup table? + for (i = 0; i < 16; i++) + if (symbol == symbols[i]) return i; + return 0; // Not found +} + +// Set the output pin number for transmitter data +void vw_set_tx_pin(uint8_t pin) +{ + vw_tx_pin = pin; +} + +// Set the pin number for input receiver data +void vw_set_rx_pin(uint8_t pin) +{ + vw_rx_pin = pin; +} + +// Set the output pin number for transmitter PTT enable +void vw_set_ptt_pin(uint8_t pin) +{ + vw_ptt_pin = pin; +} + +// Set the ptt pin inverted (low to transmit) +void vw_set_ptt_inverted(uint8_t inverted) +{ + vw_ptt_inverted = inverted; +} + +// Called 8 times per bit period +// Phase locked loop tries to synchronise with the transmitter so that bit +// transitions occur at about the time vw_rx_pll_ramp is 0; +// Then the average is computed over each bit period to deduce the bit value +void vw_pll() +{ + // Integrate each sample + if (vw_rx_sample) + vw_rx_integrator++; + + if (vw_rx_sample != vw_rx_last_sample) + { + // Transition, advance if ramp > 80, retard if < 80 + vw_rx_pll_ramp += ((vw_rx_pll_ramp < VW_RAMP_TRANSITION) + ? VW_RAMP_INC_RETARD + : VW_RAMP_INC_ADVANCE); + vw_rx_last_sample = vw_rx_sample; + } + else + { + // No transition + // Advance ramp by standard 20 (== 160/8 samples) + vw_rx_pll_ramp += VW_RAMP_INC; + } + if (vw_rx_pll_ramp >= VW_RX_RAMP_LEN) + { + // Add this to the 12th bit of vw_rx_bits, LSB first + // The last 12 bits are kept + vw_rx_bits >>= 1; + + // Check the integrator to see how many samples in this cycle were high. + // If < 5 out of 8, then its declared a 0 bit, else a 1; + if (vw_rx_integrator >= 5) + vw_rx_bits |= 0x800; + + vw_rx_pll_ramp -= VW_RX_RAMP_LEN; + vw_rx_integrator = 0; // Clear the integral for the next cycle + + if (vw_rx_active) + { + // We have the start symbol and now we are collecting message bits, + // 6 per symbol, each which has to be decoded to 4 bits + if (++vw_rx_bit_count >= 12) + { + // Have 12 bits of encoded message == 1 byte encoded + // Decode as 2 lots of 6 bits into 2 lots of 4 bits + // The 6 lsbits are the high nybble + uint8_t this_byte = + (vw_symbol_6to4(vw_rx_bits & 0x3f)) << 4 + | vw_symbol_6to4(vw_rx_bits >> 6); + + // The first decoded byte is the byte count of the following message + // the count includes the byte count and the 2 trailing FCS bytes + // REVISIT: may also include the ACK flag at 0x40 + if (vw_rx_len == 0) + { + // The first byte is the byte count + // Check it for sensibility. It cant be less than 4, since it + // includes the bytes count itself and the 2 byte FCS + vw_rx_count = this_byte; + if (vw_rx_count < 4 || vw_rx_count > VW_MAX_MESSAGE_LEN) + { + // Stupid message length, drop the whole thing + vw_rx_active = false; + vw_rx_bad++; + return; + } + } + vw_rx_buf[vw_rx_len++] = this_byte; + + if (vw_rx_len >= vw_rx_count) + { + // Got all the bytes now + vw_rx_active = false; + vw_rx_good++; + vw_rx_done = true; // Better come get it before the next one starts + } + vw_rx_bit_count = 0; + } + } + // Not in a message, see if we have a start symbol + else if (vw_rx_bits == 0xb38) + { + // Have start symbol, start collecting message + vw_rx_active = true; + vw_rx_bit_count = 0; + vw_rx_len = 0; + vw_rx_done = false; // Too bad if you missed the last message + } + } +} + +// Common function for setting timer ticks @ prescaler values for speed +// Returns prescaler index into {0, 0, 3, 6, 8, 10, 12} array +// and sets nticks to compare-match value if lower than max_ticks +// returns 0 & nticks = 0 on fault +uint8_t prescalers[] PROGMEM = {0, 0, 3, 6, 8, 10, 12}; /* Must be outside the function */ +uint8_t _timer_calc(uint16_t speed, uint16_t max_ticks, uint16_t *nticks) +{ + // Clock divider (prescaler) values - 0/4096: error flag + /* Trick: use power of 2 rather than divisor values: only uint8_t table needed */ + uint8_t prescaler=0; // index into array & return bit value + uint32_t ulticks; // calculate by ntick overflow + + // Div-by-zero protection + if (speed == 0) + { + // signal fault + *nticks = 0; + return 0; + } + // test increasing prescaler (divisor), decreasing ulticks until no overflow + for (prescaler=1; prescaler < 7; prescaler += 1) + { + /* Trick: compute in frequency domain rather than in time domain: no need of floats */ + // Amount of time per CPU clock tick (in seconds) + uint32_t clock_freq = F_CPU >> (uint8_t)pgm_read_byte(&prescalers[prescaler]); + // Fraction of second needed to xmit one bit + uint32_t bit_freq = (uint32_t)speed << 3;/* 8 samples */ + // number of prescaled ticks needed to handle bit time @ speed + ulticks = clock_freq / bit_freq; + // Test if ulticks fits in nticks bitwidth (with 1-tick safety margin) + if ((ulticks > 1) && (ulticks < max_ticks)) + { + break; // found prescaler + } + // Won't fit, check with next prescaler value + } + + // Check for error + if ((prescaler >= 6) || (ulticks < 2UL) || (ulticks > (uint32_t)max_ticks)) + { + // signal fault + *nticks = 0; + return 0; + } + + *nticks = (uint16_t)ulticks; + return prescaler; +} + +// Speed is in bits per sec RF rate +#if defined(__MSP430G2452__) || defined(__MSP430G2553__) // LaunchPad specific +void vw_setup(uint16_t speed) +{ + // Calculate the counter overflow count based on the required bit speed + // and CPU clock rate + uint16_t ocr1a = (F_CPU / 8UL) / speed; + + // This code is for Energia/MSP430 + TA0CCR0 = ocr1a; // Ticks for 62,5 us + TA0CTL = TASSEL_2 + MC_1; // SMCLK, up mode + TA0CCTL0 |= CCIE; // CCR0 interrupt enabled + + // Set up digital IO pins + pinMode(vw_tx_pin, OUTPUT); + pinMode(vw_rx_pin, INPUT); + pinMode(vw_ptt_pin, OUTPUT); + digitalWrite(vw_ptt_pin, vw_ptt_inverted); +} + +#elif defined (ARDUINO) // Arduino specific +void vw_setup(uint16_t speed) +{ + uint16_t nticks; // number of prescaled ticks needed + uint8_t prescaler; // Bit values for CS0[2:0] + +#ifdef __AVR_ATtiny85__ + // figure out prescaler value and counter match value + prescaler = _timer_calc(speed, (uint8_t)-1, &nticks); + if (!prescaler) + { + return; // fault + } + + TCCR0A = 0; + TCCR0A = _BV(WGM01); // Turn on CTC mode / Output Compare pins disconnected + + // convert prescaler index to TCCRnB prescaler bits CS00, CS01, CS02 + TCCR0B = 0; + TCCR0B = prescaler; // set CS00, CS01, CS02 (other bits not needed) + + // Number of ticks to count before firing interrupt + OCR0A = uint8_t(nticks); + + // Set mask to fire interrupt when OCF0A bit is set in TIFR0 + TIMSK |= _BV(OCIE0A); +#else // ARDUINO + // This is the path for most Arduinos + // figure out prescaler value and counter match value + prescaler = _timer_calc(speed, (uint16_t)-1, &nticks); + if (!prescaler) + { + return; // fault + } + + TCCR1A = 0; // Output Compare pins disconnected + TCCR1B = _BV(WGM12); // Turn on CTC mode + + // convert prescaler index to TCCRnB prescaler bits CS10, CS11, CS12 + TCCR1B |= prescaler; + + // Caution: special procedures for setting 16 bit regs + // is handled by the compiler + OCR1A = nticks; + // Enable interrupt +#ifdef TIMSK1 + // atmega168 + TIMSK1 |= _BV(OCIE1A); +#else + // others + TIMSK |= _BV(OCIE1A); +#endif // TIMSK1 + +#endif // __AVR_ATtiny85__ + + // Set up digital IO pins + pinMode(vw_tx_pin, OUTPUT); + pinMode(vw_rx_pin, INPUT); + pinMode(vw_ptt_pin, OUTPUT); + digitalWrite(vw_ptt_pin, vw_ptt_inverted); +} +#endif // ARDUINO + +// Declare an external function to call in the timer interruption +void vw_declare_timer_Ovf_funct(void (*Funct)(void)) +{ +uint8_t oldSREG = SREG; + cli(); + _Funct=Funct; + SREG = oldSREG; +} + +// Start the transmitter, call when the tx buffer is ready to go and vw_tx_len is +// set to the total number of symbols to send +void vw_tx_start() +{ + vw_tx_index = 0; + vw_tx_bit = 0; + vw_tx_sample = 0; + + // Enable the transmitter hardware + digitalWrite(vw_ptt_pin, true ^ vw_ptt_inverted); + + // Next tick interrupt will send the first bit + vw_tx_enabled = true; +} + +// Stop the transmitter, call when all bits are sent +void vw_tx_stop() +{ + // Disable the transmitter hardware + digitalWrite(vw_ptt_pin, false ^ vw_ptt_inverted); + digitalWrite(vw_tx_pin, false); + + // No more ticks for the transmitter + vw_tx_enabled = false; +} + +// Enable the receiver. When a message becomes available, vw_rx_done flag +// is set, and vw_wait_rx() will return. +void vw_rx_start() +{ + if (!vw_rx_enabled) + { + vw_rx_enabled = true; + vw_rx_active = false; // Never restart a partial message + } +} + +// Disable the receiver +void vw_rx_stop() +{ + vw_rx_enabled = false; +} + +// Return true if the transmitter is active +uint8_t vx_tx_active() +{ + return vw_tx_enabled; +} + +// Wait for the transmitter to become available +// Busy-wait loop until the ISR says the message has been sent +void vw_wait_tx() +{ + while (vw_tx_enabled) + ; +} + +// Wait for the receiver to get a message +// Busy-wait loop until the ISR says a message is available +// can then call vw_get_message() +void vw_wait_rx() +{ + while (!vw_rx_done) + ; +} + +// Wait at most max milliseconds for the receiver to receive a message +// Return the truth of whether there is a message +uint8_t vw_wait_rx_max(unsigned long milliseconds) +{ + unsigned long start = millis(); + + while (!vw_rx_done && ((millis() - start) < milliseconds)) + ; + return vw_rx_done; +} + +// Wait until transmitter is available and encode and queue the message +// into vw_tx_buf +// The message is raw bytes, with no packet structure imposed +// It is transmitted preceded a byte count and followed by 2 FCS bytes +uint8_t vw_send(uint8_t* buf, uint8_t len) +{ + uint8_t i; + uint8_t index = 0; + uint16_t crc = 0xffff; + uint8_t *p = vw_tx_buf + VW_HEADER_LEN; // start of the message area + uint8_t count = len + 3; // Added byte count and FCS to get total number of bytes + + if (len > VW_MAX_PAYLOAD) + return false; + + // Wait for transmitter to become available + vw_wait_tx(); + + // Encode the message length + crc = _crc_ccitt_update(crc, count); + p[index++] = symbols[count >> 4]; + p[index++] = symbols[count & 0xf]; + + // Encode the message into 6 bit symbols. Each byte is converted into + // 2 6-bit symbols, high nybble first, low nybble second + for (i = 0; i < len; i++) + { + crc = _crc_ccitt_update(crc, buf[i]); + p[index++] = symbols[buf[i] >> 4]; + p[index++] = symbols[buf[i] & 0xf]; + } + + // Append the fcs, 16 bits before encoding (4 6-bit symbols after encoding) + // Caution: VW expects the _ones_complement_ of the CCITT CRC-16 as the FCS + // VW sends FCS as low byte then hi byte + crc = ~crc; + p[index++] = symbols[(crc >> 4) & 0xf]; + p[index++] = symbols[crc & 0xf]; + p[index++] = symbols[(crc >> 12) & 0xf]; + p[index++] = symbols[(crc >> 8) & 0xf]; + + // Total number of 6-bit symbols to send + vw_tx_len = index + VW_HEADER_LEN; + + // Start the low level interrupt handler sending symbols + vw_tx_start(); + + return true; +} + +// Return true if there is a message available +uint8_t vw_have_message() +{ + return vw_rx_done; +} + +// Get the last message received (without byte count or FCS) +// Copy at most *len bytes, set *len to the actual number copied +// Return true if there is a message and the FCS is OK +uint8_t vw_get_message(uint8_t* buf, uint8_t* len) +{ + uint8_t rxlen; + + // Message available? + if (!vw_rx_done) + return false; + + // Wait until vw_rx_done is set before reading vw_rx_len + // then remove bytecount and FCS + rxlen = vw_rx_len - 3; + + // Copy message (good or bad) + if (*len > rxlen) + *len = rxlen; + memcpy(buf, vw_rx_buf + 1, *len); + + vw_rx_done = false; // OK, got that message thanks + + // Check the FCS, return goodness + return (vw_crc(vw_rx_buf, vw_rx_len) == 0xf0b8); // FCS OK? +} + +// This is the interrupt service routine called when timer1 overflows +// Its job is to output the next bit from the transmitter (every 8 calls) +// and to call the PLL code if the receiver is enabled +//ISR(SIG_OUTPUT_COMPARE1A) +#if defined (ARDUINO) // Arduino specific + +#ifdef __AVR_ATtiny85__ +ISR(TIM0_COMPA_vect, ISR_NOBLOCK) +#else // Assume Arduino Uno (328p or similar) + +SIGNAL(TIMER1_COMPA_vect) +#endif // __AVR_ATtiny85__ + +{ + if (vw_rx_enabled && !vw_tx_enabled) + vw_rx_sample = digitalRead(vw_rx_pin); + + // Do transmitter stuff first to reduce transmitter bit jitter due + // to variable receiver processing + if (vw_tx_enabled && vw_tx_sample++ == 0) + { + // Send next bit + // Symbols are sent LSB first + // Finished sending the whole message? (after waiting one bit period + // since the last bit) + if (vw_tx_index >= vw_tx_len) + { + vw_tx_stop(); + vw_tx_msg_count++; + } + else + { + digitalWrite(vw_tx_pin, vw_tx_buf[vw_tx_index] & (1 << vw_tx_bit++)); + if (vw_tx_bit >= 6) + { + vw_tx_bit = 0; + vw_tx_index++; + } + } + } + if (vw_tx_sample > 7) + vw_tx_sample = 0; + + if (vw_rx_enabled && !vw_tx_enabled) + vw_pll(); +//PL{ + if(_Funct) _Funct(); +//PL} +} +#elif defined(__MSP430G2452__) || defined(__MSP430G2553__) // LaunchPad specific +void vw_Int_Handler() +{ + if (vw_rx_enabled && !vw_tx_enabled) + vw_rx_sample = digitalRead(vw_rx_pin); + + // Do transmitter stuff first to reduce transmitter bit jitter due + // to variable receiver processing + if (vw_tx_enabled && vw_tx_sample++ == 0) + { + // Send next bit + // Symbols are sent LSB first + // Finished sending the whole message? (after waiting one bit period + // since the last bit) + if (vw_tx_index >= vw_tx_len) + { + vw_tx_stop(); + vw_tx_msg_count++; + } + else + { + digitalWrite(vw_tx_pin, vw_tx_buf[vw_tx_index] & (1 << vw_tx_bit++)); + if (vw_tx_bit >= 6) + { + vw_tx_bit = 0; + vw_tx_index++; + } + } + } + if (vw_tx_sample > 7) + vw_tx_sample = 0; + + if (vw_rx_enabled && !vw_tx_enabled) + vw_pll(); +} + +interrupt(TIMER0_A0_VECTOR) Timer_A_int(void) +{ + vw_Int_Handler(); +}; + +#endif + + +} diff --git a/hardware/digistump/avr/libraries/VirtualWire/VirtualWire.h b/hardware/digistump/avr/libraries/VirtualWire/VirtualWire.h new file mode 100644 index 0000000..c9ca4bb --- /dev/null +++ b/hardware/digistump/avr/libraries/VirtualWire/VirtualWire.h @@ -0,0 +1,297 @@ +// VirtualWire.h +// +// Virtual Wire implementation for Arduino +// See the README file in this directory fdor documentation +// +// Author: Mike McCauley (mikem@airspayce.com) DO NOT CONTACT THE AUTHOR DIRECTLY: USE THE LISTS +// Copyright (C) 2008 Mike McCauley +// $Id: VirtualWire.h,v 1.6 2013/02/14 22:02:11 mikem Exp mikem $ + +/// \mainpage VirtualWire library for Arduino +/// +/// This is the Arduino VirtualWire library. +/// +/// VirtualWire is an Arduino library that provides features to send short +/// messages, without addressing, retransmit or acknowledgment, a bit like UDP +/// over wireless, using ASK (amplitude shift keying). Supports a number of +/// inexpensive radio transmitters and receivers. All that is required is +/// transmit data, receive data and (for transmitters, optionally) a PTT +/// transmitter enable. +/// +/// It is intended to be compatible with the RF Monolithics (www.rfm.com) +/// Virtual Wire protocol, but this has not been tested. +/// +/// Does not use the Arduino UART. Messages are sent with a training preamble, +/// message length and checksum. Messages are sent with 4-to-6 bit encoding +/// for good DC balance, and a CRC checksum for message integrity. +/// +/// Why not just use the Arduino UART connected directly to the +/// transmitter/receiver? As discussed in the RFM documentation, ASK receivers +/// require a burst of training pulses to synchronize the transmitter and +/// receiver, and also requires good balance between 0s and 1s in the message +/// stream in order to maintain the DC balance of the message. UARTs do not +/// provide these. They work a bit with ASK wireless, but not as well as this +/// code. +/// +/// This library provides classes for +/// - VirtualWire: unaddressed, unreliable messages +/// +/// Example Arduino programs are included to show the main modes of use. +/// +/// The version of the package that this documentation refers to can be downloaded +/// from http://www.airspayce.com/mikem/arduino/VirtualWire/VirtualWire-1.15.zip +/// You can find the latest version at http://www.airspayce.com/mikem/arduino/VirtualWire +/// +/// You can also find online help and disussion at http://groups.google.com/group/virtualwire +/// Please use that group for all questions and discussions on this topic. +/// Do not contact the author directly, unless it is to discuss commercial licensing. +/// +/// \par Supported Hardware +/// A range of communications hardware is supported. The ones listed blow are +/// available in common retail outlets in Australian and other countries for +/// under $10 per unit. Many other modules may also work with this software. +/// Runs on ATmega8/168 (Arduino Diecimila, Uno etc) and ATmega328 and possibly +/// others. Also runs on on Energia with MSP430G2553 / G2452 and Arduino with +/// ATMega328 (courtesy Yannick DEVOS - XV4Y). +/// Also compiles and runs on ATtiny85 in Arduino environment, courtesy r4z0r7o3. +/// +/// - Receivers +/// - RX-B1 (433.92MHz) (also known as ST-RX04-ASK) +/// - Transmitters: +/// - TX-C1 (433.92MHz) +/// - Transceivers +/// - DR3100 (433.92MHz) +/// +/// \par Installation +/// To install, unzip the library into the libraries sub-directory of your +/// Arduino application directory. Then launch the Arduino environment; you +/// should see the library in the Sketch->Import Library menu, and example +/// code in +/// File->Sketchbook->Examples->VirtualWire menu. +/// +/// \par Open Source Licensing GPL V2 +/// +/// This is the appropriate option if you want to share the source code of your +/// application with everyone you distribute it to, and you also want to give them +/// the right to share who uses it. If you wish to use this software under Open +/// Source Licensing, you must contribute all your source code to the open source +/// community in accordance with the GPL Version 2 when your application is +/// distributed. See http://www.gnu.org/copyleft/gpl.html +/// +/// \par Commercial Licensing +/// +/// This is the appropriate option if you are creating proprietary applications +/// and you are not prepared to distribute and share the source code of your +/// application. Contact info@airspayce.com for details. +/// +/// \par Revision History +/// \version 1.0 Original release +/// +/// \version 1.1 2008-06-24 +/// Now can compile for atmega8 +/// Reported by creatrope +/// \version 1.2 2009-03-30 +/// Fixed a problem that prevented compiling with arduino-0015 +/// Reported by Jaime Castro +/// \version 1.3 2009-04-01 +/// Fixed a compatibility problem with ATMEGA328 of the new arduino +/// Now use SIGNAL(TIMER1_COMPA_vect) instead of ISR(SIG_OUTPUT_COMPARE1A) +/// as discussed in +/// http://www.arduino.cc/cgi-bin/yabb2/YaBB.pl?num=1237714550/11 +/// and reported by Jaime Castro. +/// \version 1.4 2010-01-29 +/// Added vx_tx_active(), suggested by Alan Burlison. +/// \version 1.5 2011-09-09 +/// Added vx_tx_active() function. +/// \version 1.6 2012-01-10 +/// Fixed a problem where the receiver was always reenabled after +/// transmission. Reported by David Bath +/// \version 1.9 2012-02-07 Documentation updates +/// Documentation updates +/// \version 1.10 Updated CHANGES file with changes since 1.4. +/// \version 1.11 Converted documentation to Doxygen. Moved CHANGES log to this version history. +/// Ensure vw_rx_pin is not accessed unless receiver is enabled +/// \version 1.12 Compiles and runs on on Energia with MSP430G2553 / G2452 and Arduino with ATMega328. +/// Patches contributed by Yannick DEVOS - XV4Y +/// \version 1.13 util/crc16.h needed for compiling on Energia with MSP430G2553 / G2452 was accidentally +/// left out of the distribution +/// \version 1.14 Added support ATtiny85 on Arduino, patch provided by r4z0r7o3. +/// \version 1.15 Updated author and distribution location details to airspayce.com +/// +/// \par Implementation Details +/// See: http://www.airspayce.com/mikem/arduino/VirtualWire.pdf +/// +/// \par Performance +/// See: http://www.airspayce.com/mikem/arduino/VirtualWire.pdf +/// +/// \par Connections +/// See: http://www.airspayce.com/mikem/arduino/VirtualWire.pdf +/// +/// \file VirtualWire.h +/// \brief VirtualWire API +/// +/// To use the VirtualWire library, you must have +/// \code +/// #include +/// \endcode +/// At the top of your sketch. +/// + +#ifndef VirtualWire_h +#define VirtualWire_h + +#include +#if defined(ARDUINO) + #if ARDUINO >= 100 + #include + #else + #include + #endif +#elif defined(__MSP430G2452__) || defined(__MSP430G2553__) // LaunchPad specific + #include "legacymsp430.h" + #include "Energia.h" +#else // error + #error Platform not defined +#endif + +// These defs cause trouble on some versions of Arduino +#undef abs +#undef double +#undef round + +/// Maximum number of bytes in a message, counting the byte count and FCS +#define VW_MAX_MESSAGE_LEN 30 + +/// The maximum payload length +#define VW_MAX_PAYLOAD VW_MAX_MESSAGE_LEN-3 + +/// The size of the receiver ramp. Ramp wraps modulu this number +#define VW_RX_RAMP_LEN 160 + +/// Number of samples per bit +#define VW_RX_SAMPLES_PER_BIT 8 + +// Ramp adjustment parameters +// Standard is if a transition occurs before VW_RAMP_TRANSITION (80) in the ramp, +// the ramp is retarded by adding VW_RAMP_INC_RETARD (11) +// else by adding VW_RAMP_INC_ADVANCE (29) +// If there is no transition it is adjusted by VW_RAMP_INC (20) +/// Internal ramp adjustment parameter +#define VW_RAMP_INC (VW_RX_RAMP_LEN/VW_RX_SAMPLES_PER_BIT) +/// Internal ramp adjustment parameter +#define VW_RAMP_TRANSITION VW_RX_RAMP_LEN/2 +/// Internal ramp adjustment parameter +#define VW_RAMP_ADJUST 9 +/// Internal ramp adjustment parameter +#define VW_RAMP_INC_RETARD (VW_RAMP_INC-VW_RAMP_ADJUST) +/// Internal ramp adjustment parameter +#define VW_RAMP_INC_ADVANCE (VW_RAMP_INC+VW_RAMP_ADJUST) + +/// Outgoing message bits grouped as 6-bit words +/// 36 alternating 1/0 bits, followed by 12 bits of start symbol +/// Followed immediately by the 4-6 bit encoded byte count, +/// message buffer and 2 byte FCS +/// Each byte from the byte count on is translated into 2x6-bit words +/// Caution, each symbol is transmitted LSBit first, +/// but each byte is transmitted high nybble first +#define VW_HEADER_LEN 8 + +// Cant really do this as a real C++ class, since we need to have +// an ISR +extern "C" +{ + /// Set the digital IO pin to be for transmit data. + /// This pin will only be accessed if + /// the transmitter is enabled + /// \param[in] pin The Arduino pin number for transmitting data. Defaults to 12. + extern void vw_set_tx_pin(uint8_t pin); + + /// Set the digital IO pin to be for receive data. + /// This pin will only be accessed if + /// the receiver is enabled + /// \param[in] pin The Arduino pin number for receiving data. Defaults to 11. + extern void vw_set_rx_pin(uint8_t pin); + + // Set the digital IO pin to enable the transmitter (press to talk, PTT)' + /// This pin will only be accessed if + /// the transmitter is enabled + /// \param[in] pin The Arduino pin number to enable the transmitter. Defaults to 10. + extern void vw_set_ptt_pin(uint8_t pin); + + /// By default the PTT pin goes high when the transmitter is enabled. + /// This flag forces it low when the transmitter is enabled. + /// \param[in] inverted True to invert PTT + extern void vw_set_ptt_inverted(uint8_t inverted); + + /// Initialise the VirtualWire software, to operate at speed bits per second + /// Call this one in your setup() after any vw_set_* calls + /// Must call vw_rx_start() before you will get any messages + /// \param[in] speed Desired speed in bits per second + extern void vw_setup(uint16_t speed); + + /// Start the Phase Locked Loop listening to the receiver + /// Must do this before you can receive any messages + /// When a message is available (good checksum or not), vw_have_message(); + /// will return true. + extern void vw_rx_start(); + + /// Stop the Phase Locked Loop listening to the receiver + /// No messages will be received until vw_rx_start() is called again + /// Saves interrupt processing cycles + extern void vw_rx_stop(); + + /// Returns the state of the + /// transmitter + /// \return true if the transmitter is active else false + extern uint8_t vx_tx_active(); + + /// Block until the transmitter is idle + /// then returns + extern void vw_wait_tx(); + + /// Block until a message is available + /// then returns + extern void vw_wait_rx(); + + /// Block until a message is available or for a max time + /// \param[in] milliseconds Maximum time to wait in milliseconds. + /// \return true if a message is available, false if the wait timed out. + extern uint8_t vw_wait_rx_max(unsigned long milliseconds); + + /// Send a message with the given length. Returns almost immediately, + /// and message will be sent at the right timing by interrupts + /// \param[in] buf Pointer to the data to transmit + /// \param[in] len Number of octetes to transmit + /// \return true if the message was accepted for transmission, false if the message is too long (>VW_MAX_MESSAGE_LEN - 3) + extern uint8_t vw_send(uint8_t* buf, uint8_t len); + + // Returns true if an unread message is available + /// \return true if a message is available to read + extern uint8_t vw_have_message(); + + // If a message is available (good checksum or not), copies + // up to *len octets to buf. + /// \param[in] buf Pointer to location to save the read data (must be at least *len bytes. + /// \param[in,out] len Available space in buf. Will be set to the actual number of octets read + /// \return true if there was a message and the checksum was good + extern uint8_t vw_get_message(uint8_t* buf, uint8_t* len); + + /// Declare an external function to call when the timer overflows. + /// \param[in] Funct Pointer to the function to call when timer overflows (eg: Software PWM management function) + extern void vw_declare_timer_Ovf_funct(void (*Funct)(void)); + +} + +/// @example client.pde +/// Client side of simple client/server pair using VirtualWire + +/// @example server.pde +/// Server side of simple client/server pair using VirtualWire + +/// @example transmitter.pde +/// Transmitter side of simple one-way transmitter->receiver pair using VirtualWire + +/// @example receiver.pde +/// Transmitter side of simple one-way transmitter->receiver pair using VirtualWire + +#endif diff --git a/hardware/digistump/avr/libraries/VirtualWire/examples/client/client.pde b/hardware/digistump/avr/libraries/VirtualWire/examples/client/client.pde new file mode 100644 index 0000000..018cb01 --- /dev/null +++ b/hardware/digistump/avr/libraries/VirtualWire/examples/client/client.pde @@ -0,0 +1,59 @@ +// client.pde +// +// Simple example of how to use VirtualWire to send and receive messages +// with a DR3100 module. +// Send a message to another arduino running the 'server' example, which +// should send a reply, which we will check +// +// See VirtualWire.h for detailed API docs +// Author: Mike McCauley (mikem@airspayce.com) +// Copyright (C) 2008 Mike McCauley +// $Id: client.pde,v 1.1 2008/04/20 09:24:17 mikem Exp $ + +#include + +void setup() +{ + Serial.begin(9600); // Debugging only + Serial.println("setup"); + + // Initialise the IO and ISR + vw_set_ptt_inverted(true); // Required for DR3100 + vw_setup(2000); // Bits per sec + vw_rx_start(); // Start the receiver PLL running +} + +void loop() +{ + const char *msg = "hello"; + uint8_t buf[VW_MAX_MESSAGE_LEN]; + uint8_t buflen = VW_MAX_MESSAGE_LEN; + + digitalWrite(13, true); // Flash a light to show transmitting + vw_send((uint8_t *)msg, strlen(msg)); + vw_wait_tx(); // Wait until the whole message is gone + Serial.println("Sent"); + digitalWrite(13, false); + + // Wait at most 200ms for a reply + if (vw_wait_rx_max(200)) + { + if (vw_get_message(buf, &buflen)) // Non-blocking + { + int i; + + // Message with a good checksum received, dump it. + Serial.print("Got: "); + + for (i = 0; i < buflen; i++) + { + Serial.print(buf[i], HEX); + Serial.print(" "); + } + Serial.println(""); + } + } + else + Serial.println("Timout"); + +} diff --git a/hardware/digistump/avr/libraries/VirtualWire/examples/receiver/receiver.pde b/hardware/digistump/avr/libraries/VirtualWire/examples/receiver/receiver.pde new file mode 100644 index 0000000..a5cb420 --- /dev/null +++ b/hardware/digistump/avr/libraries/VirtualWire/examples/receiver/receiver.pde @@ -0,0 +1,46 @@ +// receiver.pde +// +// Simple example of how to use VirtualWire to receive messages +// Implements a simplex (one-way) receiver with an Rx-B1 module +// +// See VirtualWire.h for detailed API docs +// Author: Mike McCauley (mikem@airspayce.com) +// Copyright (C) 2008 Mike McCauley +// $Id: receiver.pde,v 1.3 2009/03/30 00:07:24 mikem Exp $ + +#include + +void setup() +{ + Serial.begin(9600); // Debugging only + Serial.println("setup"); + + // Initialise the IO and ISR + vw_set_ptt_inverted(true); // Required for DR3100 + vw_setup(2000); // Bits per sec + + vw_rx_start(); // Start the receiver PLL running +} + +void loop() +{ + uint8_t buf[VW_MAX_MESSAGE_LEN]; + uint8_t buflen = VW_MAX_MESSAGE_LEN; + + if (vw_get_message(buf, &buflen)) // Non-blocking + { + int i; + + digitalWrite(13, true); // Flash a light to show received good message + // Message with a good checksum received, dump it. + Serial.print("Got: "); + + for (i = 0; i < buflen; i++) + { + Serial.print(buf[i], HEX); + Serial.print(" "); + } + Serial.println(""); + digitalWrite(13, false); + } +} diff --git a/hardware/digistump/avr/libraries/VirtualWire/examples/server/server.pde b/hardware/digistump/avr/libraries/VirtualWire/examples/server/server.pde new file mode 100644 index 0000000..ead67f0 --- /dev/null +++ b/hardware/digistump/avr/libraries/VirtualWire/examples/server/server.pde @@ -0,0 +1,55 @@ +// server.pde +// +// Simple example of how to use VirtualWire to send and receive messages +// with a DR3100 module. +// Wait for a message from another arduino running the 'client' example, +// and send a reply. +// You can use this as the basis of a remote control/remote sensing system +// +// See VirtualWire.h for detailed API docs +// Author: Mike McCauley (mikem@airspayce.com) +// Copyright (C) 2008 Mike McCauley +// $Id: server.pde,v 1.1 2008/04/20 09:24:17 mikem Exp $ + +#include + +void setup() +{ + Serial.begin(9600); // Debugging only + Serial.println("setup"); + + // Initialise the IO and ISR + vw_set_ptt_inverted(true); // Required for DR3100 + vw_setup(2000); // Bits per sec + vw_rx_start(); // Start the receiver PLL running +} + +void loop() +{ + const char *msg = "hello"; + uint8_t buf[VW_MAX_MESSAGE_LEN]; + uint8_t buflen = VW_MAX_MESSAGE_LEN; + + // Wait for a message + vw_wait_rx(); + if (vw_get_message(buf, &buflen)) // Non-blocking + { + int i; + const char *msg = "goodbye"; + + digitalWrite(13, true); // Flash a light to show received good message + // Message with a good checksum received, dump it. + Serial.print("Got: "); + + for (i = 0; i < buflen; i++) + { + Serial.print(buf[i], HEX); + Serial.print(" "); + } + Serial.println(""); + + // Send a reply + vw_send((uint8_t *)msg, strlen(msg)); + digitalWrite(13, false); + } +} diff --git a/hardware/digistump/avr/libraries/VirtualWire/examples/transmitter/transmitter.pde b/hardware/digistump/avr/libraries/VirtualWire/examples/transmitter/transmitter.pde new file mode 100644 index 0000000..dd8d4d2 --- /dev/null +++ b/hardware/digistump/avr/libraries/VirtualWire/examples/transmitter/transmitter.pde @@ -0,0 +1,32 @@ +// transmitter.pde +// +// Simple example of how to use VirtualWire to transmit messages +// Implements a simplex (one-way) transmitter with an TX-C1 module +// +// See VirtualWire.h for detailed API docs +// Author: Mike McCauley (mikem@airspayce.com) +// Copyright (C) 2008 Mike McCauley +// $Id: transmitter.pde,v 1.3 2009/03/30 00:07:24 mikem Exp $ + +#include + +void setup() +{ + Serial.begin(9600); // Debugging only + Serial.println("setup"); + + // Initialise the IO and ISR + vw_set_ptt_inverted(true); // Required for DR3100 + vw_setup(2000); // Bits per sec +} + +void loop() +{ + const char *msg = "hello"; + + digitalWrite(13, true); // Flash a light to show transmitting + vw_send((uint8_t *)msg, strlen(msg)); + vw_wait_tx(); // Wait until the whole message is gone + digitalWrite(13, false); + delay(200); +} diff --git a/hardware/digistump/avr/libraries/VirtualWire/keywords.txt b/hardware/digistump/avr/libraries/VirtualWire/keywords.txt new file mode 100644 index 0000000..1d8a5bf --- /dev/null +++ b/hardware/digistump/avr/libraries/VirtualWire/keywords.txt @@ -0,0 +1,2 @@ +VirtualWire KEYWORD1 + diff --git a/hardware/digistump/avr/libraries/VirtualWire/util/crc16.h b/hardware/digistump/avr/libraries/VirtualWire/util/crc16.h new file mode 100644 index 0000000..18c173c --- /dev/null +++ b/hardware/digistump/avr/libraries/VirtualWire/util/crc16.h @@ -0,0 +1,103 @@ +/* Copyright (c) 2002, 2003, 2004 Marek Michalkiewicz + Copyright (c) 2005, 2007 Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +// Port to Energia / MPS430 by Yannick DEVOS XV4Y - (c) 2013 +// http://xv4y.radioclub.asia/ +// + +/* $Id: crc16.h 2136 2010-06-08 12:03:38Z joerg_wunsch $ */ + +#ifndef _UTIL_CRC16_H_ +#define _UTIL_CRC16_H_ + +#include + +#define lo8(x) ((x)&0xff) +#define hi8(x) ((x)>>8) + + uint16_t crc16_update(uint16_t crc, uint8_t a) + { + int i; + + crc ^= a; + for (i = 0; i < 8; ++i) + { + if (crc & 1) + crc = (crc >> 1) ^ 0xA001; + else + crc = (crc >> 1); + } + + return crc; + } + + uint16_t crc_xmodem_update (uint16_t crc, uint8_t data) + { + int i; + + crc = crc ^ ((uint16_t)data << 8); + for (i=0; i<8; i++) + { + if (crc & 0x8000) + crc = (crc << 1) ^ 0x1021; + else + crc <<= 1; + } + + return crc; + } + uint16_t _crc_ccitt_update (uint16_t crc, uint8_t data) + { + data ^= lo8 (crc); + data ^= data << 4; + + return ((((uint16_t)data << 8) | hi8 (crc)) ^ (uint8_t)(data >> 4) + ^ ((uint16_t)data << 3)); + } + + uint8_t _crc_ibutton_update(uint8_t crc, uint8_t data) + { + uint8_t i; + + crc = crc ^ data; + for (i = 0; i < 8; i++) + { + if (crc & 0x01) + crc = (crc >> 1) ^ 0x8C; + else + crc >>= 1; + } + + return crc; + } + + +#endif /* _UTIL_CRC16_H_ */ diff --git a/hardware/digistump/avr/libraries/WS2811/WS2811.h b/hardware/digistump/avr/libraries/WS2811/WS2811.h new file mode 100644 index 0000000..d742b90 --- /dev/null +++ b/hardware/digistump/avr/libraries/WS2811/WS2811.h @@ -0,0 +1,154 @@ +/* + * Copyright 2012 Alan Burlison, alan@bleaklow.com. All rights reserved. + * Use is subject to license terms. + */ + +/* + * WS2811 RGB LED driver. + */ + + #include + +#ifndef WS2811_h +#define WS2811_h + +// RGB value structure. +typedef struct __attribute__ ((__packed__)) { + uint8_t r; + uint8_t g; + uint8_t b; +} RGB_t; + +#ifndef ARRAYLEN +#define ARRAYLEN(A) (sizeof(A) / sizeof(A[0])) +#endif + +/* + * Inline asm macro to output 24-bit RGB value in (G,R,B) order, MSBit first. + * 0 bits are 250ns hi, 1000ns lo, 1 bits are 1000ns hi, 250ns lo. + * r18 = red byte to be output + * r19 = green byte to be output + * r20 = blue byte to be output + * r26 = saved SREG + * r27 = inner loop counter + */ +#define WS2811(PORT, PIN, RGB, LEN) \ +asm volatile( \ +/* initialise */ \ +" cp %A[len], r1 ; check len > 0, return immediately if it is\n" \ +" cpc %B[len], r1\n" \ +" brne 1f\n" \ +" rjmp 16f\n" \ +"1: ld r18, Z+ ; load in first red byte to be output\n" \ +" ld r19, Z+ ; load in first green byte to be output\n" \ +" ld r20, Z+ ; load in first blue byte to be output\n" \ +" ldi r27, 8 ; load inner loop counter\n" \ +" in r26, __SREG__ ; timing-critical, so no interrupts\n" \ +" cli\n" \ +/* green - loop over 8 bits */ \ +"2: sbi %[port], %[pin] ; pin lo -> hi\n" \ +" sbrc r19, 7 ; test hi bit clear\n" \ +" rjmp 3f ; true, skip pin hi -> lo\n" \ +" cbi %[port], %[pin] ; false, pin hi -> lo\n" \ +"3: sbrc r19, 7 ; equalise delay of both code paths\n" \ +" rjmp 4f\n" \ +"4: nop ; pulse timing delay\n" \ +" nop\n" \ +" nop\n" \ +" nop\n" \ +" nop\n" \ +" nop\n" \ +" lsl r19 ; shift to next bit\n" \ +" dec r27 ; decrement loop counter\n" \ +" cbi %[port], %[pin] ; pin hi -> lo\n" \ +" brne 2b\n ; loop if required\n" \ +" ldi r27, 7 ; reload inner loop counter\n" \ +/* red - loop over first 7 bits */ \ +"5: sbi %[port], %[pin] ; pin lo -> hi\n" \ +" sbrc r18, 7 ; test hi bit clear\n" \ +" rjmp 6f ; true, skip pin hi -> lo\n" \ +" cbi %[port], %[pin] ; false, pin hi -> lo\n" \ +"6: sbrc r18, 7 ; equalise delay of both code paths\n" \ +" rjmp 7f\n" \ +"7: nop ; pulse timing delay\n" \ +" nop\n" \ +" nop\n" \ +" nop\n" \ +" nop\n" \ +" nop\n" \ +" lsl r18 ; shift to next bit\n" \ +" dec r27 ; decrement inner loop counter\n" \ +" cbi %[port], %[pin] ; pin hi -> lo\n" \ +" brne 5b ; inner loop, if required\n" \ +" nop ; equalise delay of both code paths\n" \ +/* red, 8th bit - output & fetch next values */ \ +" sbi %[port], %[pin] ; pin lo -> hi\n" \ +" sbrc r18, 7 ; test hi bit clear\n" \ +" rjmp 8f ; true, skip pin hi -> lo\n" \ +" cbi %[port], %[pin] ; false, pin hi -> lo\n" \ +"8: sbrc r18, 7 ; equalise delay of both code paths\n" \ +" rjmp 9f\n" \ +"9: nop ; pulse timing delay\n" \ +" nop\n" \ +" nop\n" \ +" ld r18, Z+ ; load next red byte\n" \ +" ld r19, Z+ ; load next green byte\n" \ +" ldi r27, 7 ; reload inner loop counter\n" \ +" cbi %[port], %[pin] ; pin hi -> lo\n" \ +" nop ; pulse timing delay\n" \ +" nop\n" \ +/* blue - loop over first 7 bits */ \ +"10: sbi %[port], %[pin] ; pin lo -> hi\n" \ +" sbrc r20, 7 ; test hi bit clear\n" \ +" rjmp 11f ; true, skip pin hi -> lo\n" \ +" cbi %[port], %[pin] ; false, pin hi -> lo\n" \ +"11: sbrc r20, 7 ; equalise delay of both code paths\n" \ +" rjmp 12f\n" \ +"12: nop ; pulse timing delay\n" \ +" nop\n" \ +" nop\n" \ +" nop\n" \ +" nop\n" \ +" nop\n" \ +" lsl r20 ; shift to next bit\n" \ +" dec r27 ; decrement inner loop counter\n" \ +" cbi %[port], %[pin] ; pin hi -> lo\n" \ +" brne 10b ; inner loop, if required\n" \ +" nop ; equalise delay of both code paths\n" \ +/* blue, 8th bit - output & handle outer loop */ \ +" sbi %[port], %[pin] ; pin lo -> hi\n" \ +" sbrc r20, 7 ; test hi bit clear\n" \ +" rjmp 13f ; true, skip pin hi -> lo\n" \ +" cbi %[port], %[pin] ; false, pin hi -> lo\n" \ +"13: sbrc r20, 7 ; equalise delay of both code paths\n" \ +" rjmp 14f\n" \ +"14: nop ; pulse timing delay\n" \ +" nop\n" \ +" ldi r27, 8 ; reload inner loop counter\n" \ +" sbiw %A[len], 1 ; decrement outer loop counter\n" \ +" breq 15f ; exit outer loop if zero\n" \ +" ld r20, Z+ ; load in next blue byte\n" \ +" cbi %[port], %[pin] ; pin hi -> lo\n" \ +" rjmp 2b ; outer loop, if required\n" \ +"15: nop ; pulse timing delay\n" \ +" cbi %[port], %[pin] ; pin hi -> lo\n" \ +" nop ; pulse timing delay\n" \ +" nop\n" \ +" out __SREG__, r26 ; reenable interrupts\n" \ +"16:\n" \ +: \ +: [rgb] "z" (RGB), \ + [len] "w" (LEN), \ + [port] "I" (_SFR_IO_ADDR(PORT)), \ + [pin] "I" (PIN) \ +: "r18", "r19", "r20", "r26", "r27", "cc", "memory" \ +) + +/* + * Define a C function to wrap the inline WS2811 macro for a given port and pin. + */ +#define DEFINE_WS2811_FN(NAME, PORT, PIN) \ +extern void NAME(const RGB_t *rgb, uint16_t len) __attribute__((noinline)); \ +void NAME(const RGB_t *rgb, uint16_t len) { WS2811(PORT, PIN, rgb, len); } + +#endif /* WS2811_h */ diff --git a/hardware/digistump/avr/libraries/WS2811/examples/digispark/digispark.ino b/hardware/digistump/avr/libraries/WS2811/examples/digispark/digispark.ino new file mode 100644 index 0000000..ff922a4 --- /dev/null +++ b/hardware/digistump/avr/libraries/WS2811/examples/digispark/digispark.ino @@ -0,0 +1,24 @@ +#include +DEFINE_WS2811_FN(WS2811RGB, PORTB, 1) +RGB_t rgb[1]; //1 for 1 pixel + +void setup() { + + pinMode(1,OUTPUT); + +} + +void loop() { + setPixel(0,255,0,0); //set first pixel (zero indexed) to red + updatePixels(); //show the change +} + +void setPixel(i,r,g,b){ + rgb[r].r=r; + rgb[g].g=g; + rgb[b].b=b; +} + +void updatePixels(){ + WS2811RGB(rgb, ARRAYLEN(rgb)); +} \ No newline at end of file diff --git a/hardware/digistump/avr/libraries/Wire/USI_TWI_Master.cpp b/hardware/digistump/avr/libraries/Wire/USI_TWI_Master.cpp new file mode 100644 index 0000000..89f50d2 --- /dev/null +++ b/hardware/digistump/avr/libraries/Wire/USI_TWI_Master.cpp @@ -0,0 +1,344 @@ +/***************************************************************************** +* +* +* File USI_TWI_Master.c compiled with gcc +* Date Friday, 10/31/08 Boo! +* Updated by jkl +* + +* AppNote : AVR310 - Using the USI module as a TWI Master +* +* Extensively modified to provide complete I2C driver. +* +*Notes: +* - T4_TWI and T2_TWI delays are modified to work with 1MHz default clock +* and now use hard code values. They would need to change +* for other clock rates. Refer to the Apps Note. +* +* 12/17/08 Added USI_TWI_Start_Memory_Read Routine -jkl +* Note msg buffer will have slave adrs ( with write bit set) and memory adrs; +* length should be these two bytes plus the number of bytes to read. +****************************************************************************/ +#include + +#if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) +#define F_CPU 16500000UL + +#elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) +#define F_CPU 16000000UL // Sets up the default speed for delay.h +#endif + +#include +#include +#include "USI_TWI_Master.h" + +unsigned char USI_TWI_Start_Transceiver_With_Data( unsigned char * , unsigned char ); +unsigned char USI_TWI_Master_Transfer( unsigned char ); +unsigned char USI_TWI_Master_Stop( void ); +unsigned char USI_TWI_Master_Start( void ); + +union USI_TWI_state +{ + unsigned char errorState; // Can reuse the TWI_state for error states since it will not be needed if there is an error. + struct + { + unsigned char addressMode : 1; + unsigned char masterWriteDataMode : 1; + unsigned char memReadMode : 1; + unsigned char unused : 5; + }; +} USI_TWI_state; + +/*--------------------------------------------------------------- + USI TWI single master initialization function +---------------------------------------------------------------*/ +void USI_TWI_Master_Initialise( void ) +{ + PORT_USI |= (1< (unsigned char*)RAMEND) // Test if address is outside SRAM space + { + USI_TWI_state.errorState = USI_TWI_DATA_OUT_OF_BOUND; + return (FALSE); + } + if(msgSize <= 1) // Test if the transmission buffer is empty + { + USI_TWI_state.errorState = USI_TWI_NO_DATA; + return (FALSE); + } +#endif + +#ifdef NOISE_TESTING // Test if any unexpected conditions have arrived prior to this execution. + if( USISR & (1<4,7us +#define T4_TWI 4 // >4,0us + +// Defines error code generating +//#define PARAM_VERIFICATION +//#define NOISE_TESTING +#define SIGNAL_VERIFY // This should probably be on always. + +/**************************************************************************** + Bit and byte definitions +****************************************************************************/ +#define TWI_READ_BIT 0 // Bit position for R/W bit in "address byte". +#define TWI_ADR_BITS 1 // Bit position for LSB of the slave address bits in the init byte. +#define TWI_NACK_BIT 0 // Bit position for (N)ACK bit. + +// Note these have been renumbered from the Atmel Apps Note. Most likely errors are now +// lowest numbers so they're easily recognized as LED flashes. +#define USI_TWI_NO_DATA 0x08 // Transmission buffer is empty +#define USI_TWI_DATA_OUT_OF_BOUND 0x09 // Transmission buffer is outside SRAM space +#define USI_TWI_UE_START_CON 0x07 // Unexpected Start Condition +#define USI_TWI_UE_STOP_CON 0x06 // Unexpected Stop Condition +#define USI_TWI_UE_DATA_COL 0x05 // Unexpected Data Collision (arbitration) +#define USI_TWI_NO_ACK_ON_DATA 0x02 // The slave did not acknowledge all data +#define USI_TWI_NO_ACK_ON_ADDRESS 0x01 // The slave did not acknowledge the address +#define USI_TWI_MISSING_START_CON 0x03 // Generated Start Condition not detected on bus +#define USI_TWI_MISSING_STOP_CON 0x04 // Generated Stop Condition not detected on bus +#define USI_TWI_BAD_MEM_READ 0x0A // Error during external memory read + +// Device dependant defines ADDED BACK IN FROM ORIGINAL ATMEL .H + +#if defined(__AVR_AT90Mega169__) | defined(__AVR_ATmega169__) | \ + defined(__AVR_AT90Mega165__) | defined(__AVR_ATmega165__) | \ + defined(__AVR_ATmega325__) | defined(__AVR_ATmega3250__) | \ + defined(__AVR_ATmega645__) | defined(__AVR_ATmega6450__) | \ + defined(__AVR_ATmega329__) | defined(__AVR_ATmega3290__) | \ + defined(__AVR_ATmega649__) | defined(__AVR_ATmega6490__) + #define DDR_USI DDRE + #define PORT_USI PORTE + #define PIN_USI PINE + #define PORT_USI_SDA PORTE5 + #define PORT_USI_SCL PORTE4 + #define PIN_USI_SDA PINE5 + #define PIN_USI_SCL PINE4 +#endif + +#if defined(__AVR_ATtiny25__) | defined(__AVR_ATtiny45__) | defined(__AVR_ATtiny85__) | \ + defined(__AVR_AT90Tiny26__) | defined(__AVR_ATtiny26__) | defined(__AVR_ATtiny167__) | \ + defined(__AVR_ATtiny87__) + #define DDR_USI DDRB + #define PORT_USI PORTB + #define PIN_USI PINB + #define PORT_USI_SDA PORTB0 + #define PORT_USI_SCL PORTB2 + #define PIN_USI_SDA PINB0 + #define PIN_USI_SCL PINB2 +#endif + +#if defined(__AVR_AT90Tiny2313__) | defined(__AVR_ATtiny2313__) + #define DDR_USI DDRB + #define PORT_USI PORTB + #define PIN_USI PINB + #define PORT_USI_SDA PORTB5 + #define PORT_USI_SCL PORTB7 + #define PIN_USI_SDA PINB5 + #define PIN_USI_SCL PINB7 +#endif + +/* From the original .h +// Device dependant defines - These for ATtiny2313. // CHANGED FOR ATtiny85 + + #define DDR_USI DDRB + #define PORT_USI PORTB + #define PIN_USI PINB + #define PORT_USI_SDA PORTB0 // was PORTB5 - N/U + #define PORT_USI_SCL PORTB2 // was PORTB7 - N/U + #define PIN_USI_SDA PINB0 // was PINB5 + #define PIN_USI_SCL PINB2 // was PINB7 +*/ + +// General defines +#define TRUE 1 +#define FALSE 0 + +//********** Prototypes **********// + +void USI_TWI_Master_Initialise( void ); +unsigned char USI_TWI_Start_Random_Read( unsigned char * , unsigned char ); +unsigned char USI_TWI_Start_Read_Write( unsigned char * , unsigned char ); +unsigned char USI_TWI_Get_State_Info( void ); diff --git a/hardware/digistump/avr/libraries/Wire/Wire.cpp b/hardware/digistump/avr/libraries/Wire/Wire.cpp new file mode 100644 index 0000000..93ec48a --- /dev/null +++ b/hardware/digistump/avr/libraries/Wire/Wire.cpp @@ -0,0 +1,108 @@ +/* + +This version has been modified by Digistump to be a drop in replacement for Wire + + TinyWireM.cpp - a wrapper class for TWI/I2C Master library for the ATtiny on Arduino + 1/21/2011 BroHogan - brohoganx10 at gmail dot com + + **** See TinyWireM.h for Credits and Usage information **** + + This library is free software; you can redistribute it and/or modify it under the + terms of the GNU General Public License as published by the Free Software + Foundation; either version 2.1 of the License, or any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A + PARTICULAR PURPOSE. See the GNU General Public License for more details. +*/ + +extern "C" { + //#include "USI_TWI_Master.h" + //#include + //#include + //#include +} + +#include "USI_TWI_Master.h" +#include "Wire.h" + + +// Initialize Class Variables ////////////////////////////////////////////////// + uint8_t USI_TWI::USI_Buf[USI_BUF_SIZE]; // holds I2C send and receive data + uint8_t USI_TWI::USI_BufIdx = 0; // current number of bytes in the send buff + uint8_t USI_TWI::USI_LastRead = 0; // number of bytes read so far + uint8_t USI_TWI::USI_BytesAvail = 0; // number of bytes requested but not read + +// Constructors //////////////////////////////////////////////////////////////// + +USI_TWI::USI_TWI(){ +} + +// Public Methods ////////////////////////////////////////////////////////////// + +void USI_TWI::begin(){ // initialize I2C lib + USI_TWI_Master_Initialise(); +} + +void USI_TWI::beginTransmission(uint8_t slaveAddr){ // setup address & write bit + USI_BufIdx = 0; + USI_Buf[USI_BufIdx] = (slaveAddr<= USI_BUF_SIZE) return; // dont blow out the buffer + USI_BufIdx++; // inc for next byte in buffer + USI_Buf[USI_BufIdx] = data; +} + +void USI_TWI::write(uint8_t data){ // buffers up data to send + send(data); +} + + +uint8_t USI_TWI::endTransmission(){ // actually sends the buffer + bool xferOK = false; + uint8_t errorCode = 0; + xferOK = USI_TWI_Start_Read_Write(USI_Buf,USI_BufIdx+1); // core func that does the work + USI_BufIdx = 0; + if (xferOK) return 0; + else { // there was an error + errorCode = USI_TWI_Get_State_Info(); // this function returns the error number + return errorCode; + } +} + +uint8_t USI_TWI::requestFrom(uint8_t slaveAddr, uint8_t numBytes){ // setup for receiving from slave + bool xferOK = false; + uint8_t errorCode = 0; + USI_LastRead = 0; + USI_BytesAvail = numBytes; // save this off in a global + numBytes++; // add extra byte to transmit header + USI_Buf[0] = (slaveAddr< +#define USI_SEND 0 // indicates sending to TWI +#define USI_RCVE 1 // indicates receiving from TWI +#define USI_BUF_SIZE 16 // bytes in message buffer + +class USI_TWI +{ + private: + static uint8_t USI_Buf[]; // holds I2C send and receive data + static uint8_t USI_BufIdx; // current number of bytes in the send buff + static uint8_t USI_LastRead; // number of bytes read so far + static uint8_t USI_BytesAvail; // number of bytes requested but not read + + public: + USI_TWI(); + void begin(); + void beginTransmission(uint8_t); + void send(uint8_t); + void write(uint8_t); + uint8_t endTransmission(); + uint8_t requestFrom(uint8_t, uint8_t); + uint8_t receive(); + uint8_t read(); + uint8_t available(); +}; + +extern USI_TWI Wire; + +#endif + diff --git a/hardware/digistump/avr/libraries/Wire/examples/Tiny85_Temp/Tiny85_Temp.pde b/hardware/digistump/avr/libraries/Wire/examples/Tiny85_Temp/Tiny85_Temp.pde new file mode 100644 index 0000000..552aebb --- /dev/null +++ b/hardware/digistump/avr/libraries/Wire/examples/Tiny85_Temp/Tiny85_Temp.pde @@ -0,0 +1,78 @@ +/* ATtiny85 as an I2C Master Ex1 BroHogan 1/21/11 + * I2C master reading DS1621 temperature sensor. (display with leds) + * SETUP: + * ATtiny Pin 1 = (RESET) N/U ATtiny Pin 2 = (D3) LED3 + * ATtiny Pin 3 = (D4) to LED1 ATtiny Pin 4 = GND + * ATtiny Pin 5 = SDA on DS1621 ATtiny Pin 6 = (D1) to LED2 + * ATtiny Pin 7 = SCK on DS1621 ATtiny Pin 8 = VCC (2.7-5.5V) + * NOTE! - It's very important to use pullups on the SDA & SCL lines! + * DS1621 wired per data sheet. This ex assumes A0-A2 are set LOW for an addeess of 0x48 + * TinyWireM USAGE & CREDITS: - see TinyWireM.h + * NOTES: + * The ATtiny85 + DS1621 draws 1.7mA @5V when leds are not on and not reading temp. + * Using sleep mode, they draw .2 @5V @ idle - see http://brownsofa.org/blog/archives/261 + */ + +#include // I2C Master lib for ATTinys which use USI + +#define DS1621_ADDR 0x48 // 7 bit I2C address for DS1621 temperature sensor +#define LED1_PIN 4 // ATtiny Pin 3 +#define LED2_PIN 1 // ATtiny Pin 6 +#define LED3_PIN 3 // ATtiny Pin 2 + +int tempC = 0; // holds temp in C +int tempF = 0; // holds temp in F + + +void setup(){ + pinMode(LED1_PIN,OUTPUT); + pinMode(LED2_PIN,OUTPUT); + pinMode(LED3_PIN,OUTPUT); + Blink(LED1_PIN,2); // show it's alive + TinyWireM.begin(); // initialize I2C lib + Init_Temp(); // Setup DS1621 + delay (3000); +} + + +void loop(){ + Get_Temp(); + Blink(LED1_PIN,tempC/10); // blink 10's of temperature on LED 1 + delay (1000); + Blink(LED2_PIN,tempC%10); // blink 1's of temperature on LED 2 + delay (4000); // wait a few sec before next reading +} + + +void Init_Temp(){ // Setup the DS1621 for one-shot mode + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xAC); // Access Command Register + TinyWireM.send(B00000001); // Using one-shot mode for battery savings + //TinyWireM.send(B00000000); // if setting continious mode for fast reads + TinyWireM.endTransmission(); // Send to the slave +} + + +void Get_Temp(){ // Get the temperature from a DS1621 + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xEE); // if one-shot, start conversions now + TinyWireM.endTransmission(); // Send 1 byte to the slave + delay(750); // if one-shot, must wait ~750 ms for conversion + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xAA); // read temperature (for either mode) + TinyWireM.endTransmission(); // Send 1 byte to the slave + TinyWireM.requestFrom(DS1621_ADDR,1); // Request 1 byte from slave + tempC = TinyWireM.receive(); // get the temperature + tempF = tempC * 9 / 5 + 32; // convert to Fahrenheit +} + + +void Blink(byte led, byte times){ // poor man's GUI + for (byte i=0; i< times; i++){ + digitalWrite(led,HIGH); + delay (400); + digitalWrite(led,LOW); + delay (175); + } +} + diff --git a/hardware/digistump/avr/libraries/Wire/examples/Tiny85_Temp_LCD/Tiny85_Temp_LCD.pde b/hardware/digistump/avr/libraries/Wire/examples/Tiny85_Temp_LCD/Tiny85_Temp_LCD.pde new file mode 100644 index 0000000..5efed12 --- /dev/null +++ b/hardware/digistump/avr/libraries/Wire/examples/Tiny85_Temp_LCD/Tiny85_Temp_LCD.pde @@ -0,0 +1,96 @@ +/* ATtiny85 as an I2C Master Ex2 BroHogan 1/21/11 + * I2C master reading DS1621 temperature sensor. Display to I2C GPIO LED. + * SETUP: + * ATtiny Pin 1 = (RESET) N/U ATtiny Pin 2 = (D3) N/U + * ATtiny Pin 3 = (D4) to LED1 ATtiny Pin 4 = GND + * ATtiny Pin 5 = SDA on DS1621 & GPIO ATtiny Pin 6 = (D1) to LED2 + * ATtiny Pin 7 = SCK on DS1621 & GPIO ATtiny Pin 8 = VCC (2.7-5.5V) + * NOTE! - It's very important to use pullups on the SDA & SCL lines! + * DS1621 wired per data sheet. This ex assumes A0-A2 are set LOW for an addeess of 0x48 + * PCA8574A GPIO was used wired per instructions in "info" folder in the LiquidCrystal_I2C lib. + * This ex assumes A0-A2 are set HIGH for an addeess of 0x3F + * LiquidCrystal_I2C lib was modified for ATtiny - on Playground with TinyWireM lib. + * TinyWireM USAGE & CREDITS: - see TinyWireM.h + */ + +//#define DEBUG +#include // I2C Master lib for ATTinys which use USI +#include // for LCD w/ GPIO MODIFIED for the ATtiny85 + +#define GPIO_ADDR 0x3F // (PCA8574A A0-A2 @5V) typ. A0-A3 Gnd 0x20 / 0x38 for A +#define DS1621_ADDR 0x48 // 7 bit I2C address for DS1621 temperature sensor +#define LED1_PIN 4 // ATtiny Pin 3 +#define LED2_PIN 1 // ATtiny Pin 6 + +int tempC = 0; // holds temp in C +int tempF = 0; // holds temp in F + +LiquidCrystal_I2C lcd(GPIO_ADDR,16,2); // set address & 16 chars / 2 lines + + +void setup(){ +#ifdef DEBUG + pinMode(LED1_PIN,OUTPUT); + pinMode(LED2_PIN,OUTPUT); + Blink(LED1_PIN,2); // show it's alive +#endif + TinyWireM.begin(); // initialize I2C lib + Init_Temp(); // Setup DS1621 + lcd.init(); // initialize the lcd + lcd.backlight(); // Print a message to the LCD. + lcd.print("Hello, Temp!"); + delay (2000); +} + + +void loop(){ + Get_Temp(); // read current temperature + lcd.clear(); // display it + lcd.print("C: "); + lcd.print(tempC,DEC); + lcd.setCursor(7,0); + lcd.print("F: "); + lcd.print(tempF,DEC); +#ifdef DEBUG + Blink(LED1_PIN,tempC/10); // blink 10's of temperature on LED 1 + delay (1000); + Blink(LED2_PIN,tempC%10); // blink 1's of temperature on LED 2 +#endif + delay (4000); // wait a few sec before next reading +} + + +void Init_Temp(){ // Setup the DS1621 for one-shot mode + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xAC); // Access Command Register + TinyWireM.send(B00000001); // Using one-shot mode for battery savings + //TinyWireM.send(B00000000); // if setting continious mode for fast reads + TinyWireM.endTransmission(); // Send to the slave +} + + +void Get_Temp(){ // Get the temperature from a DS1621 + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xEE); // if one-shot, start conversions now + TinyWireM.endTransmission(); // Send 1 byte to the slave + delay(750); // if one-shot, must wait ~750 ms for conversion + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xAA); // read temperature (for either mode) + TinyWireM.endTransmission(); // Send 1 byte to the slave + TinyWireM.requestFrom(DS1621_ADDR,1); // Request 1 byte from slave + tempC = TinyWireM.receive(); // get the temperature + tempF = tempC * 9 / 5 + 32; // convert to Fahrenheit +} + + +#ifdef DEBUG +void Blink(byte led, byte times){ // poor man's GUI + for (byte i=0; i< times; i++){ + digitalWrite(led,HIGH); + delay (400); + digitalWrite(led,LOW); + delay (175); + } +} +#endif + diff --git a/hardware/digistump/avr/libraries/Wire/examples/Tiny85_Temp_LCD_RTC/Tiny85_Temp_LCD_RTC.pde b/hardware/digistump/avr/libraries/Wire/examples/Tiny85_Temp_LCD_RTC/Tiny85_Temp_LCD_RTC.pde new file mode 100644 index 0000000..42674cc --- /dev/null +++ b/hardware/digistump/avr/libraries/Wire/examples/Tiny85_Temp_LCD_RTC/Tiny85_Temp_LCD_RTC.pde @@ -0,0 +1,199 @@ +/* ATtiny85 as an I2C Master Ex3 BroHogan 1/22/11 + * I2C master reading DS1621 temperature sensor & DS1307 RTC. Display to I2C GPIO LED. + * SETUP: + * ATtiny Pin 1 = (RESET) N/U ATtiny Pin 2 = (D3) N/U + * ATtiny Pin 3 = (D4) to LED1 ATtiny Pin 4 = GND + * ATtiny Pin 5 = SDA on all devices ATtiny Pin 6 = (D1) to LED2 + * ATtiny Pin 7 = SCK on all devices ATtiny Pin 8 = VCC (2.7-5.5V) + * NOTE! - It's very important to use pullups on the SDA & SCL lines! + * DS1621 wired per data sheet. This ex assumes A0-A2 are set LOW for an addeess of 0x48 + * DS1307 wired per data sheet. This ex assumes A0-A2 are set LOW for an addeess of 0x68 + * PCA8574A GPIO was used wired per instructions in "info" folder in the LiquidCrystal_I2C lib. + * This ex assumes A0-A2 are set HIGH for an addeess of 0x3F + * LiquidCrystal_I2C lib was modified for ATtiny - on Playground with TinyWireM lib. + * TinyWireM USAGE & CREDITS: - see TinyWireM.h + */ + +//#define DEBUG +#include // I2C Master lib for ATTinys which use USI +#include // for LCD w/ GPIO MODIFIED for the ATtiny85 + +#define GPIO_ADDR 0x3F // (PCA8574A A0-A2 @5V) typ. A0-A3 Gnd 0x20 / 0x38 for A +#define DS1307_ADDR 0x68 // I2C real time clock +#define DS1621_ADDR 0x48 // 7 bit I2C address for DS1621 temperature sensor +#define LED1_PIN 4 // ATtiny Pin 3 +#define LED2_PIN 1 // ATtiny Pin 6 +//#define HR24 true + +int tempC = 0; // holds temp in C +int tempF = 0; // holds temp in F +byte seconds,minutes,hours,day_of_week,days,months,years,PM,hour12,DST; +char timeString[10]; // HH:MM 12 Hr. no AM/PM or 24 Hr (based on param) +char dateString[10]; // MM/DD or DD/MM (based on param)- no year +bool HR24; // 12/24 Hr Time and date + +LiquidCrystal_I2C lcd(GPIO_ADDR,16,2); // set address & 16 chars / 2 lines + + +void setup(){ +#ifdef DEBUG + pinMode(LED1_PIN,OUTPUT); + pinMode(LED2_PIN,OUTPUT); + Blink(LED1_PIN,3); // show it's alive +#endif + TinyWireM.begin(); // initialize I2C lib + Init_Temp(); // Setup DS1621 + lcd.init(); // initialize the lcd + lcd.backlight(); // Print a message to the LCD. + lcd.print("Hello, Temp!"); + delay (2000); +} + + +void loop(){ + Get_Temp(); // read current temperature + Get_Time(); // read current time + lcd.clear(); // display it + lcd.print("C"); + lcd.print((char)223); + lcd.print(": "); + lcd.print(tempC,DEC); + lcd.setCursor(9,0); + lcd.print("F"); + lcd.print((char)223); + lcd.print(": "); + lcd.print(tempF,DEC); + lcd.setCursor(0,1); + lcd.print(timeString); + lcd.setCursor(9,1); + lcd.print(dateString); +#ifdef DEBUG + Blink(LED1_PIN,tempC/10); // blink 10's of temperature on LED 1 + delay (1000); + Blink(LED2_PIN,tempC%10); // blink 1's of temperature on LED 2 +#endif + HR24 = ! HR24; // flip the format + delay (4000); // wait a few sec before next reading +} + + +void Init_Temp(){ // Setup the DS1621 for one-shot mode + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xAC); // Access Command Register + TinyWireM.send(B00000001); // Using one-shot mode for battery savings + //TinyWireM.send(B00000000); // if setting continious mode for fast reads + TinyWireM.endTransmission(); // Send to the slave +} + + +void Get_Temp(){ // Get the temperature from a DS1621 + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xEE); // if one-shot, start conversions now + TinyWireM.endTransmission(); // Send 1 byte to the slave + delay(750); // if one-shot, must wait ~750 ms for conversion + TinyWireM.beginTransmission(DS1621_ADDR); + TinyWireM.send(0xAA); // read temperature (for either mode) + TinyWireM.endTransmission(); // Send 1 byte to the slave + TinyWireM.requestFrom(DS1621_ADDR,1); // Request 1 byte from slave + tempC = TinyWireM.receive(); // get the temperature + tempF = tempC * 9 / 5 + 32; // convert to Fahrenheit +} + + +void Get_Time(){ // get the time and date from the DS1307 chip + byte wireRet = 0; + memset(timeString,0,sizeof(timeString)); // initialize the strings + memset(dateString,0,sizeof(dateString)); + + TinyWireM.beginTransmission(DS1307_ADDR); // reset DS1307 register pointer + TinyWireM.send(0); + wireRet = TinyWireM.endTransmission(); + if (wireRet) { // report any send esrrors + lcd.clear(); + lcd.print("SendError: "); + lcd.print(wireRet,DEC); + delay(1500); + } + wireRet = TinyWireM.requestFrom(DS1307_ADDR, 7); // request 7 bytes from DS1307 + if (wireRet) { // report any receive esrrors + lcd.clear(); + lcd.print("RcveError: "); + lcd.print(wireRet,DEC); + delay(1500); + } +#ifdef DEBUG + lcd.clear(); + lcd.print("Before Reads: "); + lcd.print(TinyWireM.available(),DEC); // testing TinyWireM.available() + delay(1500); +#endif + seconds = bcdToDec(TinyWireM.receive()); // handle the 7 bytes received + minutes = bcdToDec(TinyWireM.receive()); + hours = bcdToDec(TinyWireM.receive()); + day_of_week = TinyWireM.receive(); + days = bcdToDec(TinyWireM.receive()); + months = bcdToDec(TinyWireM.receive()); + years = bcdToDec(TinyWireM.receive()); +#ifdef DEBUG + lcd.clear(); + lcd.print("After Reads: "); + lcd.print(TinyWireM.available(),DEC); // testing TinyWireM.available() + delay(1500); +#endif + // deal with AM/PM global and 12 hour clock + if (hours >= 12) PM = true; + else PM = false; + if (hours > 12)hour12 = hours - 12; + else hour12 = hours; + if (hours == 0) hour12 = 12; + + // make time string + if (HR24) AppendToString (hours,timeString); // add 24 hour time to string + else AppendToString (hour12,timeString); // add 12 hour time to string + strcat(timeString,":"); + if (minutes < 10) strcat(timeString,"0"); + AppendToString (minutes,timeString); // add MINUTES to string + if (!HR24){ + if (hours >= 12) strcat(timeString," PM"); // deal with AM/PM + else strcat(timeString," AM"); + } + // make date string + if (HR24)AppendToString (days,dateString); // add DAY to string + else AppendToString (months,dateString); // add MONTH to string + strcat(dateString,"/"); + if (HR24)AppendToString (months,dateString); // add MONTH to string + else AppendToString (days,dateString); // add DAY to string + strcat(dateString,"/"); + if (years < 10) strcat(dateString,"0"); + AppendToString (years,dateString); // add YEAR to string +} + + +void AppendToString (byte bValue, char *pString){ // appends a byte to string passed + char tempStr[6]; + memset(tempStr,'\0',sizeof(tempStr)); + itoa(bValue,tempStr,10); + strcat(pString,tempStr); +} + + +byte bcdToDec(byte val) { // Convert binary coded decimal to normal decimal numbers + return ((val / 16 * 10) + (val % 16)); +} + + +#ifdef DEBUG +void Blink(byte led, byte times){ // poor man's GUI + for (byte i=0; i< times; i++){ + digitalWrite(led,HIGH); + delay (400); + digitalWrite(led,LOW); + delay (175); + } +} +#endif + + + + + diff --git a/hardware/digistump/avr/libraries/Wire/keywords.txt b/hardware/digistump/avr/libraries/Wire/keywords.txt new file mode 100644 index 0000000..e185f3c --- /dev/null +++ b/hardware/digistump/avr/libraries/Wire/keywords.txt @@ -0,0 +1,31 @@ +####################################### +# Syntax Coloring Map For TinyWireM +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +begin KEYWORD2 +beginTransmission KEYWORD2 +endTransmission KEYWORD2 +requestFrom KEYWORD2 +send KEYWORD2 +read KEYWORD2 +receive KEYWORD2 +write KEYWORD2 + +####################################### +# Instances (KEYWORD2) +####################################### + +Wire KEYWORD2 + +####################################### +# Constants (LITERAL1) +####################################### + diff --git a/hardware/digistump/avr/platform.txt b/hardware/digistump/avr/platform.txt new file mode 100644 index 0000000..dd1b1e6 --- /dev/null +++ b/hardware/digistump/avr/platform.txt @@ -0,0 +1,80 @@ + +# Arduino AVR Core and platform. +# ------------------------------ + +# For more info: +# https://github.com/arduino/Arduino/wiki/Arduino-IDE-1.5---3rd-party-Hardware-specification + +name=Digistump AVR Boards +version=1.5.4 + +# AVR compile variables +# --------------------- + +# Default "compiler.path" is correct, change only if you want to overidde the initial value +compiler.path={runtime.ide.path}/hardware/tools/avr/bin/ +compiler.c.cmd=avr-gcc +compiler.c.flags=-c -g -Os -w -ffunction-sections -fdata-sections -MMD +compiler.c.elf.flags=-Os -Wl,--gc-sections +compiler.c.elf.cmd=avr-gcc +compiler.S.flags=-c -g -x assembler-with-cpp +compiler.cpp.cmd=avr-g++ +compiler.cpp.flags=-c -g -Os -w -fno-exceptions -ffunction-sections -fdata-sections -MMD +compiler.ar.cmd=avr-ar +compiler.ar.flags=rcs +compiler.objcopy.cmd=avr-objcopy +compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0 +compiler.elf2hex.flags=-O ihex -R .eeprom +compiler.elf2hex.cmd=avr-objcopy +compiler.ldflags= +compiler.size.cmd=avr-size +# this can be overriden in boards.txt +build.extra_flags= + +# AVR compile patterns +# -------------------- + +## Compile c files +recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" + +## Compile c++ files +recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" + +## Compile S files +recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.flags} -mmcu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {build.extra_flags} {includes} "{source_file}" -o "{object_file}" + +## Create archives +recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} "{build.path}/{archive_file}" "{object_file}" + +## Combine gc-sections, archives, and objects +recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mmcu={build.mcu} -o "{build.path}/{build.project_name}.elf" {object_files} "{build.path}/{archive_file}" "-L{build.path}" -lm + +## Create eeprom +recipe.objcopy.eep.pattern="{compiler.path}{compiler.objcopy.cmd}" {compiler.objcopy.eep.flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.eep" + +## Create hex +recipe.objcopy.hex.pattern="{compiler.path}{compiler.elf2hex.cmd}" {compiler.elf2hex.flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.hex" + +## Compute size +recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf" +recipe.size.regex=^(?:\.text|\.data|\.bootloader)\s+([0-9]+).* +recipe.size.regex.data=^(?:\.data|\.bss|\.noinit)\s+([0-9]+).* +recipe.size.regex.eeprom=^(?:\.eeprom)\s+([0-9]+).* + + +# AVR Uploader/Programmers tools +# ------------------------------ + +tools.micronucleus.cmd.path={sketchbook.path}/hardware/digistump/avr/tools/avrdude +tools.micronucleus.cmd.path.linux={sketchbook.path}/hardware/digistump/avr/tools/avrdude + +tools.micronucleus.upload.params.verbose=-v +tools.micronucleus.upload.params.quiet=-q +#tools.micronucleus.upload.pattern="{cmd.path}" --run --timeout 60 "{build.path}/{build.project_name}.hex" +tools.micronucleus.upload.pattern="{cmd.path}" -cdigispark --timeout 60 -Uflash:w:{build.path}/{build.project_name}.hex:i + +# USB Default Flags +# Default blank usb manufacturer will be filled it at compile time +# - from numeric vendor ID, set to Unknown otherwise +build.usb_manufacturer= +build.usb_flags= \ No newline at end of file diff --git a/hardware/digistump/avr/programmers.txt b/hardware/digistump/avr/programmers.txt new file mode 100644 index 0000000..537865a --- /dev/null +++ b/hardware/digistump/avr/programmers.txt @@ -0,0 +1,5 @@ +micronucleusprog.name=Micronucleus +micronucleusprog.communication=usb +micronucleusprog.protocol=micronucleus +micronucleusprog.program.tool=micronucleus +micronucleusprog.program.extra_params=-Pusb \ No newline at end of file diff --git a/hardware/digistump/avr/tools/avrdude.exe b/hardware/digistump/avr/tools/avrdude.exe new file mode 100644 index 0000000..718593a Binary files /dev/null and b/hardware/digistump/avr/tools/avrdude.exe differ diff --git a/hardware/digistump/avr/tools/ld.exe b/hardware/digistump/avr/tools/ld.exe new file mode 100644 index 0000000..70c34b0 Binary files /dev/null and b/hardware/digistump/avr/tools/ld.exe differ diff --git a/hardware/digistump/avr/tools/libusb-0.1.4.dylib b/hardware/digistump/avr/tools/libusb-0.1.4.dylib new file mode 100644 index 0000000..02b0c60 Binary files /dev/null and b/hardware/digistump/avr/tools/libusb-0.1.4.dylib differ diff --git a/hardware/digistump/avr/tools/libusb-1.0.0.dylib b/hardware/digistump/avr/tools/libusb-1.0.0.dylib new file mode 100644 index 0000000..91a7b6c Binary files /dev/null and b/hardware/digistump/avr/tools/libusb-1.0.0.dylib differ diff --git a/hardware/digistump/avr/tools/micronucleus b/hardware/digistump/avr/tools/micronucleus new file mode 100644 index 0000000..97e67c9 Binary files /dev/null and b/hardware/digistump/avr/tools/micronucleus differ diff --git a/hardware/digistump/avr/tools/micronucleus.exe b/hardware/digistump/avr/tools/micronucleus.exe new file mode 100644 index 0000000..5816159 Binary files /dev/null and b/hardware/digistump/avr/tools/micronucleus.exe differ diff --git a/hardware/digistump/avr/variants/digispark/pins_arduino.c b/hardware/digistump/avr/variants/digispark/pins_arduino.c new file mode 100644 index 0000000..ea70922 --- /dev/null +++ b/hardware/digistump/avr/variants/digispark/pins_arduino.c @@ -0,0 +1,321 @@ +/* + pins_arduino.c - pin definitions for the Arduino board + Part of Arduino / Wiring Lite + + Copyright (c) 2005 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: pins_arduino.c 565 2009-03-25 10:50:00Z dmellis $ + + Modified 28-08-2009 for attiny84 R.Wiersma + Modified 09-10-2009 for attiny45 A.Saporetti + Modified for Atmel ATTiny2313 mcu by René Bohne + + Corrected 17-05-2010 for ATtiny84 B.Cook ... + + The default analog_reference leaves chip pin 13 (digital pin 10; PA0) + unconnected. So the pin can be set to a non-floating state and so the + pin can be used as another digital pin, support for digital pin 10 was + added. +*/ + +#include +#include "pins_arduino.h" +#include "wiring_private.h" + + +#if defined( __AVR_ATtinyX313__ ) + +// On the Arduino board, digital pins are also used +// for the analog output (software PWM). Analog input +// pins are a separate set. + +// ATMEL ATTINY2313 +// +// +-\/-+ +// (D 17) PA2 1| |29 VCC +// RX (D 0) PD0 2| |19 PB7 (D 16) +// TX (D 1) PD1 3| |18 PB6 (D 15) +// (D 2) PA1 4| |17 PB5 (D 14) +// (D 3) PA0 5| |16 PB4 (D 13)* +// INT0 (D 4) PD2 6| |15 PB3 (D 12)* +// INT1 (D 5) PD3 7| |14 PB2 (D 11)* +// (D 6) PD4 8| |13 PB1 (D 10) +// *(D 7) PD5 9| |12 PB0 (D 9) +// GND 10| |11 PD6 (D 8) +// +----+ +// +// * indicates PWM port + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) +const uint8_t PROGMEM port_to_mode_PGM[] = +{ + NOT_A_PORT, + &DDRA, + &DDRB, + NOT_A_PORT, + &DDRD, +}; + +const uint8_t PROGMEM port_to_output_PGM[] = +{ + NOT_A_PORT, + &PORTA, + &PORTB, + NOT_A_PORT, + &PORTD, +}; + +const uint8_t PROGMEM port_to_input_PGM[] = +{ + NOT_A_PORT, + &PINA, + &PINB, + NOT_A_PORT, + &PIND, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = +{ + PORT_D_ID, /* 0 */ + PORT_D_ID, + PORT_A_ID, + PORT_A_ID, + PORT_D_ID, + PORT_D_ID, + PORT_D_ID, + PORT_D_ID, + PORT_D_ID, /* 8 */ + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, /* 14 */ + PORT_B_ID, + PORT_B_ID, + PORT_A_ID, +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = +{ + _BV(0), /* 0 */ + _BV(1), + _BV(1), + _BV(0), + _BV(2), + _BV(3), + _BV(4), + _BV(5), + _BV(6), /* 8 */ + _BV(0), + _BV(1), + _BV(2), + _BV(3), + _BV(4), + _BV(5), /* 14 */ + _BV(6), + _BV(7), + _BV(2), +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = +{ + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + TIMER0B, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + TIMER0A, + TIMER1A, + TIMER1B, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +#endif + + +#if defined( __AVR_ATtinyX4__ ) + +// ATMEL ATTINY84 / ARDUINO +// +// +-\/-+ +// VCC 1| |14 GND +// (D 0) PB0 2| |13 AREF (D 10) +// (D 1) PB1 3| |12 PA1 (D 9) +// PB3 4| |11 PA2 (D 8) +// PWM INT0 (D 2) PB2 5| |10 PA3 (D 7) +// PWM (D 3) PA7 6| |9 PA4 (D 6) +// PWM (D 4) PA6 7| |8 PA5 (D 5) PWM +// +----+ + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) +const uint8_t PROGMEM port_to_mode_PGM[] = +{ + NOT_A_PORT, + &DDRA, + &DDRB, +}; + +const uint8_t PROGMEM port_to_output_PGM[] = +{ + NOT_A_PORT, + &PORTA, + &PORTB, +}; + +const uint8_t PROGMEM port_to_input_PGM[] = +{ + NOT_A_PORT, + &PINA, + &PINB, +}; + +const uint8_t PROGMEM port_to_pcmask_PGM[] = +{ + NOT_A_PORT, + &PCMSK0, + &PCMSK1, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = +{ + PORT_B_ID, /* 0 */ + PORT_B_ID, + PORT_B_ID, + PORT_A_ID, + PORT_A_ID, + PORT_A_ID, + PORT_A_ID, + PORT_A_ID, + PORT_A_ID, /* 8 */ + PORT_A_ID, + PORT_A_ID, +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = +{ + _BV(0), /* 0, port B */ + _BV(1), + _BV(2), + _BV(7), /* 3 port B */ + _BV(6), + _BV(5), + _BV(4), + _BV(3), + _BV(2), + _BV(1), + _BV(0), +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = +{ + NOT_ON_TIMER, + NOT_ON_TIMER, + TIMER0A, /* OC0A */ + TIMER0B, /* OC0B */ + TIMER1A, /* OC1A */ + TIMER1B, /* OC1B */ + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +#endif + + +#if defined( __AVR_ATtinyX5__ ) + +// ATMEL ATTINY45 / ARDUINO +// +// +-\/-+ +// Ain0 (D 5) PB5 1| |8 VCC +// Ain3 (D 3) PB3 2| |7 PB2 (D 2) INT0 Ain1 +// Ain2 (D 4) PB4 3| |6 PB1 (D 1) pwm1 +// GND 4| |5 PB0 (D 0) pwm0 +// +----+ + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) tiny45 only port B +const uint8_t PROGMEM port_to_mode_PGM[] = +{ + NOT_A_PORT, + &DDRB, +}; + +const uint8_t PROGMEM port_to_output_PGM[] = +{ + NOT_A_PORT, + &PORTB, +}; + +const uint8_t PROGMEM port_to_input_PGM[] = +{ + NOT_A_PIN, + &PINB, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = +{ + PORT_B_ID, /* 0 */ + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, + PORT_B_ID, /* 5 */ + +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = +{ + _BV(0), /* 0, port B */ + _BV(1), + _BV(2), + _BV(3), /* 3 port B */ + _BV(4), + _BV(5), + +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = +{ + TIMER0A, /* OC0A */ + TIMER1A, /* OC1A? */ + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +#endif diff --git a/hardware/digistump/avr/variants/digispark/pins_arduino.h b/hardware/digistump/avr/variants/digispark/pins_arduino.h new file mode 100644 index 0000000..b49b33c --- /dev/null +++ b/hardware/digistump/avr/variants/digispark/pins_arduino.h @@ -0,0 +1,115 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.h 249 2007-02-03 16:52:51Z mellis $ + + Modified 28-08-2009 for attiny84 R.Wiersma + Modified 14-10-2009 for attiny45 Saposoft +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include + +#include "core_build_options.h" + +#if defined( __AVR_ATtinyX313__ ) +#define PORT_A_ID 1 +#define PORT_B_ID 2 +#define PORT_D_ID 4 +#endif + +#if defined( __AVR_ATtinyX4__ ) +#define PORT_A_ID 1 +#define PORT_B_ID 2 +#endif + +#if defined( __AVR_ATtinyX5__ ) +#define PORT_B_ID 1 +#endif + +#define NOT_A_PIN 0 +#define NOT_A_PORT 0 + +#define NOT_ON_TIMER 0 +#define TIMER0A 1 +#define TIMER0B 2 +#define TIMER1A 3 +#define TIMER1B 4 + +//changed it to uint16_t to uint8_t +extern const uint8_t PROGMEM port_to_mode_PGM[]; +extern const uint8_t PROGMEM port_to_input_PGM[]; +extern const uint8_t PROGMEM port_to_output_PGM[]; +extern const uint8_t PROGMEM port_to_pcmask_PGM[]; + +extern const uint8_t PROGMEM digital_pin_to_port_PGM[]; +// extern const uint8_t PROGMEM digital_pin_to_bit_PGM[]; +extern const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[]; +extern const uint8_t PROGMEM digital_pin_to_timer_PGM[]; + +// Get the bit location within the hardware port of the given virtual pin. +// This comes from the pins_*.c file for the active board configuration. +// +// These perform slightly better as macros compared to inline functions +// +#define digitalPinToPort(P) ( pgm_read_byte( digital_pin_to_port_PGM + (P) ) ) +#define digitalPinToBitMask(P) ( pgm_read_byte( digital_pin_to_bit_mask_PGM + (P) ) ) +#define digitalPinToTimer(P) ( pgm_read_byte( digital_pin_to_timer_PGM + (P) ) ) +#define analogInPinToBit(P) (P) +// in the following lines modified pgm_read_word in pgm_read_byte, word doesn't work on attiny45 +#define portOutputRegister(P) ( (volatile uint8_t *)( pgm_read_byte( port_to_output_PGM + (P))) ) +#define portInputRegister(P) ( (volatile uint8_t *)( pgm_read_byte( port_to_input_PGM + (P))) ) +#define portModeRegister(P) ( (volatile uint8_t *)( pgm_read_byte( port_to_mode_PGM + (P))) ) +#define portPcMaskRegister(P) ( (volatile uint8_t *)( pgm_read_byte( port_to_pcmask_PGM + (P))) ) + +#if defined(__AVR_ATtinyX5__) +#define digitalPinToPCICR(p) (((p) >= 0 && (p) <= 5) ? (&GIMSK) : ((uint8_t *)NULL)) +#define digitalPinToPCICRbit(p) (PCIE) +#define digitalPinToPCMSK(p) (((p) >= 0 && (p) <= 5) ? (&PCMSK) : ((uint8_t *)NULL)) +#define digitalPinToPCMSKbit(p) (p) +#endif + +#if defined(__AVR_ATtinyX4__) +#define digitalPinToPCICR(p) (((p) >= 0 && (p) <= 10) ? (&GIMSK) : ((uint8_t *)NULL)) +#define digitalPinToPCICRbit(p) (((p) <= 2) ? PCIE1 : PCIE0) +#define digitalPinToPCMSK(p) (((p) <= 2) ? (&PCMSK1) : (((p) <= 10) ? (&PCMSK0) : ((uint8_t *)NULL))) +#define digitalPinToPCMSKbit(p) (((p) <= 2) ? (p) : (10 - (p))) +#endif + +#if defined(__AVR_ATtiny4313__) +#define digitalPinToPCX(p,s1,s2,s3,s4,s5) \ + (((p) >= 0) \ + ? (((p) <= 1) ? (s1) /* 0 - 1 ==> D0 - D1 */ \ + : (((p) <= 3) ? (s2) /* 2 - 3 ==> A1 - A0 */ \ + : (((p) <= 8) ? (s3) /* 4 - 8 ==> D2 - D6 */ \ + : (((p) <= 16) ? (s4) /* 9 - 16 ==> B0 - B7 */ \ + : (s5))))) \ + : (s5)) +// s1 D s2 A s3 D s4 B +#define digitalPinToPCICR(p) digitalPinToPCX( p, &GIMSK, &GIMSK, &GIMSK, &GIMSK, NULL ) +#define digitalPinToPCICRbit(p) digitalPinToPCX( p, PCIE2, PCIE1, PCIE2, PCIE0, 0 ) +#define digitalPinToPCMSK(p) digitalPinToPCX( p, &PCMSK2, &PCMSK1, &PCMSK2, &PCMSK0, NULL ) +#define digitalPinToPCMSKbit(p) digitalPinToPCX( p, p, 3-p, p-2, p-9, 0 ) +#endif + +#endif diff --git a/hardware/digistump/avr/variants/pro/pins_arduino.h b/hardware/digistump/avr/variants/pro/pins_arduino.h new file mode 100644 index 0000000..720d469 --- /dev/null +++ b/hardware/digistump/avr/variants/pro/pins_arduino.h @@ -0,0 +1,233 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.h 249 2007-02-03 16:52:51Z mellis $ +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#define ATTINYX7 1 + +#define SERIAL_BUFFER_SIZE 16 + +#include + +#define NUM_DIGITAL_PINS 14 +#define NUM_ANALOG_INPUTS 10 +#define analogInputToDigitalPin(p) ((p < 7) ? p+6 : (p ==7) ? 5 : (p==9) ? 4 : (p==10) ? 13 : -1) + +#define digitalPinHasPWM(p) ((p) == 0 || (p) == 1) + +#define SS 12 +#define MOSI 10 +#define MISO 8 +#define SCK 11 + +static const uint8_t SDA = 0; +static const uint8_t SCL = 2; + +//Ax constants cannot be used for digitalRead/digitalWrite/analogWrite functions, only analogRead(). +static const uint8_t A4 = NUM_DIGITAL_PINS+9; +static const uint8_t A5 = NUM_DIGITAL_PINS+7; +static const uint8_t A6 = NUM_DIGITAL_PINS+0; +static const uint8_t A7 = NUM_DIGITAL_PINS+1; +static const uint8_t A8 = NUM_DIGITAL_PINS+2; +static const uint8_t A9 = NUM_DIGITAL_PINS+3; +static const uint8_t A10 = NUM_DIGITAL_PINS+4; +static const uint8_t A11 = NUM_DIGITAL_PINS+5; +static const uint8_t A12 = NUM_DIGITAL_PINS+6; +static const uint8_t A13 = NUM_DIGITAL_PINS+10; + + + +//---------------------------------------------------------- +//---------------------------------------------------------- +//Core Configuration (used to be in core_build_options.h) + +//If Software Serial communications doesn't work, run the TinyTuner sketch provided with the core to give you a calibrated OSCCAL value. +//Change the value here with the tuned value. By default this option uses the default value which the compiler will optimise out. +#define TUNED_OSCCAL_VALUE OSCCAL +//e.g +//#define TUNED_OSCCAL_VALUE 0x57 + +//Choosing not to initialise saves power and flash. 1 = initialise. +#define INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER 1 +#define INITIALIZE_SECONDARY_TIMERS 0 + +#define TIMER_TO_USE_FOR_MILLIS 0 + +#define HAVE_BOOTLOADER 1 + +/* + Where to put the software serial? (Arduino Digital pin numbers) +*/ +//WARNING, if using software, TX is on AIN0, RX is on AIN1. Comparator is favoured to use its interrupt for the RX pin. +#define USE_SOFTWARE_SERIAL 0 +//Please define the port on which the analog comparator is found. +#define ANALOG_COMP_DDR DDRA +#define ANALOG_COMP_PORT PORTA +#define ANALOG_COMP_PIN PINA +#define ANALOG_COMP_AIN0_BIT 6 +#define ANALOG_COMP_AIN1_BIT 7 + +/* + Analog reference bit masks. +*/ +// VCC used as analog reference, disconnected from PA0 (AREF) +#define DEFAULT (0) +// External voltage reference at PA0 (AREF) pin, internal reference turned off +#define EXTERNAL (1) +// Internal 1.1V voltage reference +#define INTERNAL (2) + + +//---------------------------------------------------------- +//---------------------------------------------------------- +//---------------------------------------------------------- +//---------------------------------------------------------- + + + +#define digitalPinToPCICR(p) (&PCIFR) +#define digitalPinToPCICRbit(p) (((p) >= 3 && (p) <= 10) ? 4 : 5) +#define digitalPinToPCMSK(p) (((p) >= 3 && (p) <= 10) ? (&PCMSK0) : (((p) >= 0 && (p) <= 2) ? (&PCMSK1) : ((uint8_t *)NULL))) +#define digitalPinToPCMSKbit(p) (((p) >= 3 && (p) <= 10) ? (10 - (p)) : (p)) + +#ifdef ARDUINO_MAIN + +// On the Arduino board, digital pins are also used +// for the analog output (software PWM). Analog input +// pins are a separate set. + +// ATMEL ATTINY167 +// +// +-\/-+ +// RX (D 0) PA0 1| |20 PB0 (D 4) +// TX (D 1) PA1 2| |19 PB1 (D 5) +// *(D 12) PA2 3| |18 PB2 (D 6) +// (D 3) PA3 4| |17 PB3 (D 7)* +// AVCC 5| |16 GND +// AGND 6| |15 VCC +// INT1 (D 11) PA4 7| |14 PB4 (D 8) +// (D 13) PA5 8| |13 PB5 (D 9) +// (D 10) PA6 9| |12 PB6 (D 2)* INT0 +// (D 14) PA7 10| |11 PB7 (D 15) +// +----+ +// +// * indicates PWM pin. + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) +const uint16_t PROGMEM port_to_mode_PGM[] = +{ + NOT_A_PORT, + (uint16_t)&DDRA, + (uint16_t)&DDRB, +}; + +const uint16_t PROGMEM port_to_output_PGM[] = +{ + NOT_A_PORT, + (uint16_t)&PORTA, + (uint16_t)&PORTB, +}; + +const uint16_t PROGMEM port_to_input_PGM[] = +{ + NOT_A_PORT, + (uint16_t)&PINA, + (uint16_t)&PINB, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = +{ + PB, /* 0 */ + PB, + PB, /* 2 */ + PB, /* 3 */ + PB, /* 4 */ + PA, + PA, + PA, + PA, + PA, + PA, /* 10 */ + PA, + PA, + PB, /* 15 */ +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = +{ + _BV(0), /* 0 */ + _BV(1), + _BV(2), /* 2 */ + _BV(3), /* 3 */ + _BV(6), /* 4 */ + _BV(7), + _BV(0), + _BV(1), + _BV(2), + _BV(3), + _BV(4), /* 10 */ + _BV(5), + _BV(6), + _BV(7), +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = +{ + TIMER1A, + TIMER1B, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +#endif + +#endif + + + + +//Old code, just here for temporary backup until I decide it is not needed. +//WARNING, if using software, RX must be on a pin which has a Pin change interrupt <= 7 (e.g. PCINT6, or PCINT1, but not PCINT8) +/*#define USE_SOFTWARE_SERIAL 1 +//These are set to match Optiboot pins. + +#define SOFTWARE_SERIAL_PORT PORTB +#define SOFTWARE_SERIAL_TX 0 +#define SOFTWARE_SERIAL_PIN PINB +#define SOFTWARE_SERIAL_RX 1*/ \ No newline at end of file diff --git a/hardware/digistump/avr/variants/pro32buffer/pins_arduino.h b/hardware/digistump/avr/variants/pro32buffer/pins_arduino.h new file mode 100644 index 0000000..daa7beb --- /dev/null +++ b/hardware/digistump/avr/variants/pro32buffer/pins_arduino.h @@ -0,0 +1,233 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.h 249 2007-02-03 16:52:51Z mellis $ +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#define ATTINYX7 1 + +#define SERIAL_BUFFER_SIZE 32 + +#include + +#define NUM_DIGITAL_PINS 14 +#define NUM_ANALOG_INPUTS 10 +#define analogInputToDigitalPin(p) ((p < 7) ? p+6 : (p ==7) ? 5 : (p==9) ? 4 : (p==10) ? 13 : -1) + +#define digitalPinHasPWM(p) ((p) == 0 || (p) == 1) + +#define SS 12 +#define MOSI 10 +#define MISO 8 +#define SCK 11 + +static const uint8_t SDA = 0; +static const uint8_t SCL = 2; + +//Ax constants cannot be used for digitalRead/digitalWrite/analogWrite functions, only analogRead(). +static const uint8_t A4 = NUM_DIGITAL_PINS+9; +static const uint8_t A5 = NUM_DIGITAL_PINS+7; +static const uint8_t A6 = NUM_DIGITAL_PINS+0; +static const uint8_t A7 = NUM_DIGITAL_PINS+1; +static const uint8_t A8 = NUM_DIGITAL_PINS+2; +static const uint8_t A9 = NUM_DIGITAL_PINS+3; +static const uint8_t A10 = NUM_DIGITAL_PINS+4; +static const uint8_t A11 = NUM_DIGITAL_PINS+5; +static const uint8_t A12 = NUM_DIGITAL_PINS+6; +static const uint8_t A13 = NUM_DIGITAL_PINS+10; + + + +//---------------------------------------------------------- +//---------------------------------------------------------- +//Core Configuration (used to be in core_build_options.h) + +//If Software Serial communications doesn't work, run the TinyTuner sketch provided with the core to give you a calibrated OSCCAL value. +//Change the value here with the tuned value. By default this option uses the default value which the compiler will optimise out. +#define TUNED_OSCCAL_VALUE OSCCAL +//e.g +//#define TUNED_OSCCAL_VALUE 0x57 + +//Choosing not to initialise saves power and flash. 1 = initialise. +#define INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER 1 +#define INITIALIZE_SECONDARY_TIMERS 0 + +#define TIMER_TO_USE_FOR_MILLIS 0 + +#define HAVE_BOOTLOADER 1 + +/* + Where to put the software serial? (Arduino Digital pin numbers) +*/ +//WARNING, if using software, TX is on AIN0, RX is on AIN1. Comparator is favoured to use its interrupt for the RX pin. +#define USE_SOFTWARE_SERIAL 0 +//Please define the port on which the analog comparator is found. +#define ANALOG_COMP_DDR DDRA +#define ANALOG_COMP_PORT PORTA +#define ANALOG_COMP_PIN PINA +#define ANALOG_COMP_AIN0_BIT 6 +#define ANALOG_COMP_AIN1_BIT 7 + +/* + Analog reference bit masks. +*/ +// VCC used as analog reference, disconnected from PA0 (AREF) +#define DEFAULT (0) +// External voltage reference at PA0 (AREF) pin, internal reference turned off +#define EXTERNAL (1) +// Internal 1.1V voltage reference +#define INTERNAL (2) + + +//---------------------------------------------------------- +//---------------------------------------------------------- +//---------------------------------------------------------- +//---------------------------------------------------------- + + + +#define digitalPinToPCICR(p) (&PCIFR) +#define digitalPinToPCICRbit(p) (((p) >= 3 && (p) <= 10) ? 4 : 5) +#define digitalPinToPCMSK(p) (((p) >= 3 && (p) <= 10) ? (&PCMSK0) : (((p) >= 0 && (p) <= 2) ? (&PCMSK1) : ((uint8_t *)NULL))) +#define digitalPinToPCMSKbit(p) (((p) >= 3 && (p) <= 10) ? (10 - (p)) : (p)) + +#ifdef ARDUINO_MAIN + +// On the Arduino board, digital pins are also used +// for the analog output (software PWM). Analog input +// pins are a separate set. + +// ATMEL ATTINY167 +// +// +-\/-+ +// RX (D 0) PA0 1| |20 PB0 (D 4) +// TX (D 1) PA1 2| |19 PB1 (D 5) +// *(D 12) PA2 3| |18 PB2 (D 6) +// (D 3) PA3 4| |17 PB3 (D 7)* +// AVCC 5| |16 GND +// AGND 6| |15 VCC +// INT1 (D 11) PA4 7| |14 PB4 (D 8) +// (D 13) PA5 8| |13 PB5 (D 9) +// (D 10) PA6 9| |12 PB6 (D 2)* INT0 +// (D 14) PA7 10| |11 PB7 (D 15) +// +----+ +// +// * indicates PWM pin. + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) +const uint16_t PROGMEM port_to_mode_PGM[] = +{ + NOT_A_PORT, + (uint16_t)&DDRA, + (uint16_t)&DDRB, +}; + +const uint16_t PROGMEM port_to_output_PGM[] = +{ + NOT_A_PORT, + (uint16_t)&PORTA, + (uint16_t)&PORTB, +}; + +const uint16_t PROGMEM port_to_input_PGM[] = +{ + NOT_A_PORT, + (uint16_t)&PINA, + (uint16_t)&PINB, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = +{ + PB, /* 0 */ + PB, + PB, /* 2 */ + PB, /* 3 */ + PB, /* 4 */ + PA, + PA, + PA, + PA, + PA, + PA, /* 10 */ + PA, + PA, + PB, /* 15 */ +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = +{ + _BV(0), /* 0 */ + _BV(1), + _BV(2), /* 2 */ + _BV(3), /* 3 */ + _BV(6), /* 4 */ + _BV(7), + _BV(0), + _BV(1), + _BV(2), + _BV(3), + _BV(4), /* 10 */ + _BV(5), + _BV(6), + _BV(7), +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = +{ + TIMER1A, + TIMER1B, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +#endif + +#endif + + + + +//Old code, just here for temporary backup until I decide it is not needed. +//WARNING, if using software, RX must be on a pin which has a Pin change interrupt <= 7 (e.g. PCINT6, or PCINT1, but not PCINT8) +/*#define USE_SOFTWARE_SERIAL 1 +//These are set to match Optiboot pins. + +#define SOFTWARE_SERIAL_PORT PORTB +#define SOFTWARE_SERIAL_TX 0 +#define SOFTWARE_SERIAL_PIN PINB +#define SOFTWARE_SERIAL_RX 1*/ \ No newline at end of file diff --git a/hardware/digistump/avr/variants/pro64buffer/pins_arduino.h b/hardware/digistump/avr/variants/pro64buffer/pins_arduino.h new file mode 100644 index 0000000..686f4ba --- /dev/null +++ b/hardware/digistump/avr/variants/pro64buffer/pins_arduino.h @@ -0,0 +1,233 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + $Id: wiring.h 249 2007-02-03 16:52:51Z mellis $ +*/ + +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#define ATTINYX7 1 + +#define SERIAL_BUFFER_SIZE 64 + +#include + +#define NUM_DIGITAL_PINS 14 +#define NUM_ANALOG_INPUTS 10 +#define analogInputToDigitalPin(p) ((p < 7) ? p+6 : (p ==7) ? 5 : (p==9) ? 4 : (p==10) ? 13 : -1) + +#define digitalPinHasPWM(p) ((p) == 0 || (p) == 1) + +#define SS 12 +#define MOSI 10 +#define MISO 8 +#define SCK 11 + +static const uint8_t SDA = 0; +static const uint8_t SCL = 2; + +//Ax constants cannot be used for digitalRead/digitalWrite/analogWrite functions, only analogRead(). +static const uint8_t A4 = NUM_DIGITAL_PINS+9; +static const uint8_t A5 = NUM_DIGITAL_PINS+7; +static const uint8_t A6 = NUM_DIGITAL_PINS+0; +static const uint8_t A7 = NUM_DIGITAL_PINS+1; +static const uint8_t A8 = NUM_DIGITAL_PINS+2; +static const uint8_t A9 = NUM_DIGITAL_PINS+3; +static const uint8_t A10 = NUM_DIGITAL_PINS+4; +static const uint8_t A11 = NUM_DIGITAL_PINS+5; +static const uint8_t A12 = NUM_DIGITAL_PINS+6; +static const uint8_t A13 = NUM_DIGITAL_PINS+10; + + + +//---------------------------------------------------------- +//---------------------------------------------------------- +//Core Configuration (used to be in core_build_options.h) + +//If Software Serial communications doesn't work, run the TinyTuner sketch provided with the core to give you a calibrated OSCCAL value. +//Change the value here with the tuned value. By default this option uses the default value which the compiler will optimise out. +#define TUNED_OSCCAL_VALUE OSCCAL +//e.g +//#define TUNED_OSCCAL_VALUE 0x57 + +//Choosing not to initialise saves power and flash. 1 = initialise. +#define INITIALIZE_ANALOG_TO_DIGITAL_CONVERTER 1 +#define INITIALIZE_SECONDARY_TIMERS 0 + +#define TIMER_TO_USE_FOR_MILLIS 0 + +#define HAVE_BOOTLOADER 1 + +/* + Where to put the software serial? (Arduino Digital pin numbers) +*/ +//WARNING, if using software, TX is on AIN0, RX is on AIN1. Comparator is favoured to use its interrupt for the RX pin. +#define USE_SOFTWARE_SERIAL 0 +//Please define the port on which the analog comparator is found. +#define ANALOG_COMP_DDR DDRA +#define ANALOG_COMP_PORT PORTA +#define ANALOG_COMP_PIN PINA +#define ANALOG_COMP_AIN0_BIT 6 +#define ANALOG_COMP_AIN1_BIT 7 + +/* + Analog reference bit masks. +*/ +// VCC used as analog reference, disconnected from PA0 (AREF) +#define DEFAULT (0) +// External voltage reference at PA0 (AREF) pin, internal reference turned off +#define EXTERNAL (1) +// Internal 1.1V voltage reference +#define INTERNAL (2) + + +//---------------------------------------------------------- +//---------------------------------------------------------- +//---------------------------------------------------------- +//---------------------------------------------------------- + + + +#define digitalPinToPCICR(p) (&PCIFR) +#define digitalPinToPCICRbit(p) (((p) >= 3 && (p) <= 10) ? 4 : 5) +#define digitalPinToPCMSK(p) (((p) >= 3 && (p) <= 10) ? (&PCMSK0) : (((p) >= 0 && (p) <= 2) ? (&PCMSK1) : ((uint8_t *)NULL))) +#define digitalPinToPCMSKbit(p) (((p) >= 3 && (p) <= 10) ? (10 - (p)) : (p)) + +#ifdef ARDUINO_MAIN + +// On the Arduino board, digital pins are also used +// for the analog output (software PWM). Analog input +// pins are a separate set. + +// ATMEL ATTINY167 +// +// +-\/-+ +// RX (D 0) PA0 1| |20 PB0 (D 4) +// TX (D 1) PA1 2| |19 PB1 (D 5) +// *(D 12) PA2 3| |18 PB2 (D 6) +// (D 3) PA3 4| |17 PB3 (D 7)* +// AVCC 5| |16 GND +// AGND 6| |15 VCC +// INT1 (D 11) PA4 7| |14 PB4 (D 8) +// (D 13) PA5 8| |13 PB5 (D 9) +// (D 10) PA6 9| |12 PB6 (D 2)* INT0 +// (D 14) PA7 10| |11 PB7 (D 15) +// +----+ +// +// * indicates PWM pin. + +// these arrays map port names (e.g. port B) to the +// appropriate addresses for various functions (e.g. reading +// and writing) +const uint16_t PROGMEM port_to_mode_PGM[] = +{ + NOT_A_PORT, + (uint16_t)&DDRA, + (uint16_t)&DDRB, +}; + +const uint16_t PROGMEM port_to_output_PGM[] = +{ + NOT_A_PORT, + (uint16_t)&PORTA, + (uint16_t)&PORTB, +}; + +const uint16_t PROGMEM port_to_input_PGM[] = +{ + NOT_A_PORT, + (uint16_t)&PINA, + (uint16_t)&PINB, +}; + +const uint8_t PROGMEM digital_pin_to_port_PGM[] = +{ + PB, /* 0 */ + PB, + PB, /* 2 */ + PB, /* 3 */ + PB, /* 4 */ + PA, + PA, + PA, + PA, + PA, + PA, /* 10 */ + PA, + PA, + PB, /* 15 */ +}; + +const uint8_t PROGMEM digital_pin_to_bit_mask_PGM[] = +{ + _BV(0), /* 0 */ + _BV(1), + _BV(2), /* 2 */ + _BV(3), /* 3 */ + _BV(6), /* 4 */ + _BV(7), + _BV(0), + _BV(1), + _BV(2), + _BV(3), + _BV(4), /* 10 */ + _BV(5), + _BV(6), + _BV(7), +}; + +const uint8_t PROGMEM digital_pin_to_timer_PGM[] = +{ + TIMER1A, + TIMER1B, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, + NOT_ON_TIMER, +}; + +#endif + +#endif + + + + +//Old code, just here for temporary backup until I decide it is not needed. +//WARNING, if using software, RX must be on a pin which has a Pin change interrupt <= 7 (e.g. PCINT6, or PCINT1, but not PCINT8) +/*#define USE_SOFTWARE_SERIAL 1 +//These are set to match Optiboot pins. + +#define SOFTWARE_SERIAL_PORT PORTB +#define SOFTWARE_SERIAL_TX 0 +#define SOFTWARE_SERIAL_PIN PINB +#define SOFTWARE_SERIAL_RX 1*/ \ No newline at end of file diff --git a/hardware/digistump/sam/boards.txt b/hardware/digistump/sam/boards.txt new file mode 100644 index 0000000..15e0418 --- /dev/null +++ b/hardware/digistump/sam/boards.txt @@ -0,0 +1,16 @@ +digix.name=Digistump DigiX +digix.upload.tool=bossac +digix.upload.protocol=sam-ba +digix.upload.maximum_size=524288 +digix.upload.use_1200bps_touch=true +digix.upload.wait_for_upload_port=true +digix.upload.native_usb=true +digix.build.mcu=cortex-m3 +digix.build.f_cpu=84000000L +digix.build.core=digix +digix.build.extra_flags=-D__SAM3X8E__ -mthumb -DUSB_PID={build.pid} -DUSB_VID={build.vid} -DUSBCON +digix.build.ldscript=linker_scripts/gcc/flash.ld +digix.build.variant=digix +digix.build.variant_system_lib=libsam_sam3x8e_gcc_rel.a +digix.build.vid=0x16D0 +digix.build.pid=0x078A diff --git a/hardware/digistump/sam/cores/digix/Arduino.h b/hardware/digistump/sam/cores/digix/Arduino.h new file mode 100644 index 0000000..48894d4 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/Arduino.h @@ -0,0 +1,217 @@ +/* + Copyright (c) 2012 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef Arduino_h +#define Arduino_h + +#include +#include +#include +#include + +// some libraries and sketches depend on this +// AVR stuff, assuming Arduino.h or WProgram.h +// automatically includes it... +#include +#include + +#include "binary.h" + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +// Includes Atmel CMSIS +#include + +#include "wiring_constants.h" + +#define clockCyclesPerMicrosecond() ( SystemCoreClock / 1000000L ) +#define clockCyclesToMicroseconds(a) ( ((a) * 1000L) / (SystemCoreClock / 1000L) ) +#define microsecondsToClockCycles(a) ( (a) * (SystemCoreClock / 1000000L) ) + +void yield(void); + +/* sketch */ +extern void setup( void ) ; +extern void loop( void ) ; + +// Get the bit location within the hardware port of the given virtual pin. +// This comes from the pins_*.c file for the active board configuration. +// +#define digitalPinToPort(P) ( g_APinDescription[P].pPort ) +#define digitalPinToBitMask(P) ( g_APinDescription[P].ulPin ) +#define digitalPinToTimer(P) ( ) +//#define analogInPinToBit(P) ( ) +#define portOutputRegister(port) ( &(port->PIO_ODSR) ) +#define portInputRegister(port) ( &(port->PIO_PDSR) ) +//#define portModeRegister(P) ( ) + +//#define NOT_A_PIN 0 // defined in pio.h/EPioType +#define NOT_A_PORT 0 + +#define NOT_AN_INTERRUPT -1 + +typedef enum _EExt_Interrupts +{ + EXTERNAL_INT_0=0, + EXTERNAL_INT_1=1, + EXTERNAL_INT_2=2, + EXTERNAL_INT_3=3, + EXTERNAL_INT_4=4, + EXTERNAL_INT_5=5, + EXTERNAL_INT_6=6, + EXTERNAL_INT_7=7, + EXTERNAL_NUM_INTERRUPTS +} EExt_Interrupts ; + +typedef void (*voidFuncPtr)( void ) ; + +/* Define attribute */ +#if defined ( __CC_ARM ) /* Keil uVision 4 */ + #define WEAK (__attribute__ ((weak))) +#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ + #define WEAK __weak +#elif defined ( __GNUC__ ) /* GCC CS */ + #define WEAK __attribute__ ((weak)) +#endif + +/* Definitions and types for pins */ +typedef enum _EAnalogChannel +{ + NO_ADC=-1, + ADC0=0, + ADC1, + ADC2, + ADC3, + ADC4, + ADC5, + ADC6, + ADC7, + ADC8, + ADC9, + ADC10, + ADC11, + ADC12, + ADC13, + ADC14, + ADC15, + DA0, + DA1 +} EAnalogChannel ; + +#define ADC_CHANNEL_NUMBER_NONE 0xffffffff + +// Definitions for PWM channels +typedef enum _EPWMChannel +{ + NOT_ON_PWM=-1, + PWM_CH0=0, + PWM_CH1, + PWM_CH2, + PWM_CH3, + PWM_CH4, + PWM_CH5, + PWM_CH6, + PWM_CH7 +} EPWMChannel ; + +// Definitions for TC channels +typedef enum _ETCChannel +{ + NOT_ON_TIMER=-1, + TC0_CHA0=0, + TC0_CHB0, + TC0_CHA1, + TC0_CHB1, + TC0_CHA2, + TC0_CHB2, + TC1_CHA3, + TC1_CHB3, + TC1_CHA4, + TC1_CHB4, + TC1_CHA5, + TC1_CHB5, + TC2_CHA6, + TC2_CHB6, + TC2_CHA7, + TC2_CHB7, + TC2_CHA8, + TC2_CHB8 +} ETCChannel ; + +/** + * Pin Attributes to be OR-ed + */ +#define PIN_ATTR_COMBO (1UL<<0) +#define PIN_ATTR_ANALOG (1UL<<1) +#define PIN_ATTR_DIGITAL (1UL<<2) +#define PIN_ATTR_PWM (1UL<<3) +#define PIN_ATTR_TIMER (1UL<<4) + +/* Types used for the tables below */ +typedef struct _PinDescription +{ + Pio* pPort ; + uint32_t ulPin ; + uint32_t ulPeripheralId ; + EPioType ulPinType ; + uint32_t ulPinConfiguration ; + uint32_t ulPinAttribute ; + EAnalogChannel ulAnalogChannel ; /* Analog pin in the Arduino context (label on the board) */ + EAnalogChannel ulADCChannelNumber ; /* ADC Channel number in the SAM device */ + EPWMChannel ulPWMChannel ; + ETCChannel ulTCChannel ; +} PinDescription ; + +/* Pins table to be instanciated into variant.cpp */ +extern const PinDescription g_APinDescription[] ; + +#ifdef __cplusplus +} // extern "C" + +#include "WCharacter.h" +#include "WString.h" +#include "Tone.h" +#include "WMath.h" +#include "HardwareSerial.h" +#include "wiring_pulse.h" + +#endif // __cplusplus + +// Include board variant +#include "variant.h" + +#include "wiring.h" +#include "wiring_digital.h" +#include "wiring_analog.h" +#include "wiring_shift.h" +#include "WInterrupts.h" + +// USB Device +#define USB_VID 0x2341 // arduino LLC vid +#define USB_VID_DIGIX 0x16D0 // Digistump LLC vid +#define USB_PID_LEONARDO 0x0034 +#define USB_PID_MICRO 0x0035 +#define USB_PID_DUE 0x003E +#define USB_PID_DIGIX 0x078A +#include "USB/USBDesc.h" +#include "USB/USBCore.h" +#include "USB/USBAPI.h" + +#endif // Arduino_h diff --git a/hardware/digistump/sam/cores/digix/Client.h b/hardware/digistump/sam/cores/digix/Client.h new file mode 100644 index 0000000..cfe9667 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/Client.h @@ -0,0 +1,26 @@ +#ifndef client_h +#define client_h +#include "Print.h" +#include "Stream.h" +#include "IPAddress.h" + +class Client : public Stream { + +public: + virtual int connect(IPAddress ip, uint16_t port = 80) =0; + virtual int connect(const char *host, uint16_t port = 80) =0; + virtual size_t write(uint8_t) =0; + virtual size_t write(const uint8_t *buf, size_t size) =0; + virtual int available() = 0; + virtual int read() = 0; + virtual int read(uint8_t *buf, size_t size) = 0; + virtual int peek() = 0; + virtual void flush() = 0; + virtual void stop() = 0; + virtual uint8_t connected() = 0; + virtual operator bool() = 0; +protected: + uint8_t* rawIPAddress(IPAddress& addr) { return addr.raw_address(); }; +}; + +#endif diff --git a/hardware/digistump/sam/cores/digix/HardwareSerial.h b/hardware/digistump/sam/cores/digix/HardwareSerial.h new file mode 100644 index 0000000..17cc3cf --- /dev/null +++ b/hardware/digistump/sam/cores/digix/HardwareSerial.h @@ -0,0 +1,42 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef HardwareSerial_h +#define HardwareSerial_h + +#include + +#include "Stream.h" + +class HardwareSerial : public Stream +{ + public: + void begin(unsigned long); + void end(); + virtual int available(void) = 0; + virtual int peek(void) = 0; + virtual int read(void) = 0; + virtual void flush(void) = 0; + virtual size_t write(uint8_t) = 0; + using Print::write; // pull in write(str) and write(buf, size) from Print + virtual operator bool() = 0; +}; + +extern void serialEventRun(void) __attribute__((weak)); + +#endif diff --git a/hardware/digistump/sam/cores/digix/IPAddress.cpp b/hardware/digistump/sam/cores/digix/IPAddress.cpp new file mode 100644 index 0000000..fe3deb7 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/IPAddress.cpp @@ -0,0 +1,56 @@ + +#include +#include + +IPAddress::IPAddress() +{ + memset(_address, 0, sizeof(_address)); +} + +IPAddress::IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet) +{ + _address[0] = first_octet; + _address[1] = second_octet; + _address[2] = third_octet; + _address[3] = fourth_octet; +} + +IPAddress::IPAddress(uint32_t address) +{ + memcpy(_address, &address, sizeof(_address)); +} + +IPAddress::IPAddress(const uint8_t *address) +{ + memcpy(_address, address, sizeof(_address)); +} + +IPAddress& IPAddress::operator=(const uint8_t *address) +{ + memcpy(_address, address, sizeof(_address)); + return *this; +} + +IPAddress& IPAddress::operator=(uint32_t address) +{ + memcpy(_address, (const uint8_t *)&address, sizeof(_address)); + return *this; +} + +bool IPAddress::operator==(const uint8_t* addr) +{ + return memcmp(addr, _address, sizeof(_address)) == 0; +} + +size_t IPAddress::printTo(Print& p) const +{ + size_t n = 0; + for (int i =0; i < 3; i++) + { + n += p.print(_address[i], DEC); + n += p.print('.'); + } + n += p.print(_address[3], DEC); + return n; +} + diff --git a/hardware/digistump/sam/cores/digix/IPAddress.h b/hardware/digistump/sam/cores/digix/IPAddress.h new file mode 100644 index 0000000..2585aec --- /dev/null +++ b/hardware/digistump/sam/cores/digix/IPAddress.h @@ -0,0 +1,76 @@ +/* + * + * MIT License: + * Copyright (c) 2011 Adrian McEwen + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * adrianm@mcqn.com 1/1/2011 + */ + +#ifndef IPAddress_h +#define IPAddress_h + +#include + +// A class to make it easier to handle and pass around IP addresses + +class IPAddress : public Printable { +private: + uint8_t _address[4]; // IPv4 address + // Access the raw byte array containing the address. Because this returns a pointer + // to the internal structure rather than a copy of the address this function should only + // be used when you know that the usage of the returned uint8_t* will be transient and not + // stored. + uint8_t* raw_address() { return _address; }; + +public: + // Constructors + IPAddress(); + IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet); + IPAddress(uint32_t address); + IPAddress(const uint8_t *address); + + // Overloaded cast operator to allow IPAddress objects to be used where a pointer + // to a four-byte uint8_t array is expected + operator uint32_t() { return *((uint32_t*)_address); }; + bool operator==(const IPAddress& addr) { return (*((uint32_t*)_address)) == (*((uint32_t*)addr._address)); }; + bool operator==(const uint8_t* addr); + + // Overloaded index operator to allow getting and setting individual octets of the address + uint8_t operator[](int index) const { return _address[index]; }; + uint8_t& operator[](int index) { return _address[index]; }; + + // Overloaded copy operators to allow initialisation of IPAddress objects from other types + IPAddress& operator=(const uint8_t *address); + IPAddress& operator=(uint32_t address); + + virtual size_t printTo(Print& p) const; + + friend class EthernetClass; + friend class UDP; + friend class Client; + friend class Server; + friend class DhcpClass; + friend class DNSClient; +}; + +const IPAddress INADDR_NONE(0,0,0,0); + + +#endif diff --git a/hardware/digistump/sam/cores/digix/Print.cpp b/hardware/digistump/sam/cores/digix/Print.cpp new file mode 100644 index 0000000..78c5e36 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/Print.cpp @@ -0,0 +1,261 @@ +/* + Print.cpp - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Modified 23 November 2006 by David A. Mellis + */ + +#include +#include +#include +#include +#include "Arduino.h" + +#include "Print.h" + +// Public Methods ////////////////////////////////////////////////////////////// + +/* default implementation: may be overridden */ +size_t Print::write(const uint8_t *buffer, size_t size) +{ + size_t n = 0; + while (size--) { + n += write(*buffer++); + } + return n; +} + +size_t Print::print(const __FlashStringHelper *ifsh) +{ + return print(reinterpret_cast(ifsh)); +} + +size_t Print::print(const String &s) +{ + size_t n = 0; + for (uint16_t i = 0; i < s.length(); i++) { + n += write(s[i]); + } + return n; +} + +size_t Print::print(const char str[]) +{ + return write(str); +} + +size_t Print::print(char c) +{ + return write(c); +} + +size_t Print::print(unsigned char b, int base) +{ + return print((unsigned long) b, base); +} + +size_t Print::print(int n, int base) +{ + return print((long) n, base); +} + +size_t Print::print(unsigned int n, int base) +{ + return print((unsigned long) n, base); +} + +size_t Print::print(long n, int base) +{ + if (base == 0) { + return write(n); + } else if (base == 10) { + if (n < 0) { + int t = print('-'); + n = -n; + return printNumber(n, 10) + t; + } + return printNumber(n, 10); + } else { + return printNumber(n, base); + } +} + +size_t Print::print(unsigned long n, int base) +{ + if (base == 0) return write(n); + else return printNumber(n, base); +} + +size_t Print::print(double n, int digits) +{ + return printFloat(n, digits); +} + +size_t Print::println(const __FlashStringHelper *ifsh) +{ + size_t n = print(ifsh); + n += println(); + return n; +} + +size_t Print::print(const Printable& x) +{ + return x.printTo(*this); +} + +size_t Print::println(void) +{ + size_t n = print('\r'); + n += print('\n'); + return n; +} + +size_t Print::println(const String &s) +{ + size_t n = print(s); + n += println(); + return n; +} + +size_t Print::println(const char c[]) +{ + size_t n = print(c); + n += println(); + return n; +} + +size_t Print::println(char c) +{ + size_t n = print(c); + n += println(); + return n; +} + +size_t Print::println(unsigned char b, int base) +{ + size_t n = print(b, base); + n += println(); + return n; +} + +size_t Print::println(int num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(unsigned int num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(long num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(unsigned long num, int base) +{ + size_t n = print(num, base); + n += println(); + return n; +} + +size_t Print::println(double num, int digits) +{ + size_t n = print(num, digits); + n += println(); + return n; +} + +size_t Print::println(const Printable& x) +{ + size_t n = print(x); + n += println(); + return n; +} + +// Private Methods ///////////////////////////////////////////////////////////// + +size_t Print::printNumber(unsigned long n, uint8_t base) { + char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte. + char *str = &buf[sizeof(buf) - 1]; + + *str = '\0'; + + // prevent crash if called with base == 1 + if (base < 2) base = 10; + + do { + unsigned long m = n; + n /= base; + char c = m - base * n; + *--str = c < 10 ? c + '0' : c + 'A' - 10; + } while(n); + + return write(str); +} + +size_t Print::printFloat(double number, uint8_t digits) +{ + size_t n = 0; + + if (isnan(number)) return print("nan"); + if (isinf(number)) return print("inf"); + if (number > 4294967040.0) return print ("ovf"); // constant determined empirically + if (number <-4294967040.0) return print ("ovf"); // constant determined empirically + + // Handle negative numbers + if (number < 0.0) + { + n += print('-'); + number = -number; + } + + // Round correctly so that print(1.999, 2) prints as "2.00" + double rounding = 0.5; + for (uint8_t i=0; i 0) { + n += print("."); + } + + // Extract digits from the remainder one at a time + while (digits-- > 0) + { + remainder *= 10.0; + int toPrint = int(remainder); + n += print(toPrint); + remainder -= toPrint; + } + + return n; +} diff --git a/hardware/digistump/sam/cores/digix/Print.h b/hardware/digistump/sam/cores/digix/Print.h new file mode 100644 index 0000000..dc76150 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/Print.h @@ -0,0 +1,81 @@ +/* + Print.h - Base class that provides print() and println() + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef Print_h +#define Print_h + +#include +#include // for size_t + +#include "WString.h" +#include "Printable.h" + +#define DEC 10 +#define HEX 16 +#define OCT 8 +#define BIN 2 + +class Print +{ + private: + int write_error; + size_t printNumber(unsigned long, uint8_t); + size_t printFloat(double, uint8_t); + protected: + void setWriteError(int err = 1) { write_error = err; } + public: + Print() : write_error(0) {} + + int getWriteError() { return write_error; } + void clearWriteError() { setWriteError(0); } + + virtual size_t write(uint8_t) = 0; + size_t write(const char *str) { + if (str == NULL) return 0; + return write((const uint8_t *)str, strlen(str)); + } + virtual size_t write(const uint8_t *buffer, size_t size); + + size_t print(const __FlashStringHelper *); + size_t print(const String &); + size_t print(const char[]); + size_t print(char); + size_t print(unsigned char, int = DEC); + size_t print(int, int = DEC); + size_t print(unsigned int, int = DEC); + size_t print(long, int = DEC); + size_t print(unsigned long, int = DEC); + size_t print(double, int = 2); + size_t print(const Printable&); + + size_t println(const __FlashStringHelper *); + size_t println(const String &s); + size_t println(const char[]); + size_t println(char); + size_t println(unsigned char, int = DEC); + size_t println(int, int = DEC); + size_t println(unsigned int, int = DEC); + size_t println(long, int = DEC); + size_t println(unsigned long, int = DEC); + size_t println(double, int = 2); + size_t println(const Printable&); + size_t println(void); +}; + +#endif diff --git a/hardware/digistump/sam/cores/digix/Printable.h b/hardware/digistump/sam/cores/digix/Printable.h new file mode 100644 index 0000000..2a1b2e9 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/Printable.h @@ -0,0 +1,40 @@ +/* + Printable.h - Interface class that allows printing of complex types + Copyright (c) 2011 Adrian McEwen. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef Printable_h +#define Printable_h + +#include + +class Print; + +/** The Printable class provides a way for new classes to allow themselves to be printed. + By deriving from Printable and implementing the printTo method, it will then be possible + for users to print out instances of this class by passing them into the usual + Print::print and Print::println methods. +*/ + +class Printable +{ + public: + virtual size_t printTo(Print& p) const = 0; +}; + +#endif + diff --git a/hardware/digistump/sam/cores/digix/Reset.cpp b/hardware/digistump/sam/cores/digix/Reset.cpp new file mode 100644 index 0000000..6336427 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/Reset.cpp @@ -0,0 +1,78 @@ +/* + Copyright (c) 2012 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include +#include "Reset.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__ ((long_call, section (".ramfunc"))) +void banzai() { + // Disable all interrupts + __disable_irq(); + + // Set bootflag to run SAM-BA bootloader at restart + const int EEFC_FCMD_CGPB = 0x0C; + const int EEFC_KEY = 0x5A; + while (EFC0->EEFC_FSR & EEFC_FSR_FRDY == 0); + EFC0->EEFC_FCR = + EEFC_FCR_FCMD(EEFC_FCMD_CGPB) | + EEFC_FCR_FARG(1) | + EEFC_FCR_FKEY(EEFC_KEY); + while (EFC0->EEFC_FSR & EEFC_FSR_FRDY == 0); + + // From here flash memory is no more available. + + // Memory swap needs some time to stabilize + for (uint32_t i=0; i<1000000; i++) + // force compiler to not optimize this + __asm__ __volatile__(""); + + // BANZAIIIIIII!!! + const int RSTC_KEY = 0xA5; + RSTC->RSTC_CR = + RSTC_CR_KEY(RSTC_KEY) | + RSTC_CR_PROCRST | + RSTC_CR_PERRST; + + while (true); +} + +static int ticks = -1; + +void initiateReset(int _ticks) { + ticks = _ticks; +} + +void cancelReset() { + ticks = -1; +} + +void tickReset() { + if (ticks == -1) + return; + ticks--; + if (ticks == 0) + banzai(); +} + +#ifdef __cplusplus +} +#endif diff --git a/hardware/digistump/sam/cores/digix/Reset.h b/hardware/digistump/sam/cores/digix/Reset.h new file mode 100644 index 0000000..373f6d1 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/Reset.h @@ -0,0 +1,34 @@ +/* + Copyright (c) 2012 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef RESET_H +#define RESET_H + +#ifdef __cplusplus +extern "C" { +#endif + +void initiateReset(int ms); +void tickReset(); +void cancelReset(); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hardware/digistump/sam/cores/digix/RingBuffer.cpp b/hardware/digistump/sam/cores/digix/RingBuffer.cpp new file mode 100644 index 0000000..f0b3ed1 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/RingBuffer.cpp @@ -0,0 +1,43 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "RingBuffer.h" +#include + +RingBuffer::RingBuffer( void ) +{ + memset( _aucBuffer, 0, SERIAL_BUFFER_SIZE ) ; + _iHead=0 ; + _iTail=0 ; +} + +void RingBuffer::store_char( uint8_t c ) +{ + int i = (uint32_t)(_iHead + 1) % SERIAL_BUFFER_SIZE ; + + // if we should be storing the received character into the location + // just before the tail (meaning that the head would advance to the + // current location of the tail), we're about to overflow the buffer + // and so we don't write the character or advance the head. + if ( i != _iTail ) + { + _aucBuffer[_iHead] = c ; + _iHead = i ; + } +} + diff --git a/hardware/digistump/sam/cores/digix/RingBuffer.h b/hardware/digistump/sam/cores/digix/RingBuffer.h new file mode 100644 index 0000000..28309df --- /dev/null +++ b/hardware/digistump/sam/cores/digix/RingBuffer.h @@ -0,0 +1,42 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _RING_BUFFER_ +#define _RING_BUFFER_ + +#include + +// Define constants and variables for buffering incoming serial data. We're +// using a ring buffer (I think), in which head is the index of the location +// to which to write the next incoming character and tail is the index of the +// location from which to read. +#define SERIAL_BUFFER_SIZE 64 + +class RingBuffer +{ + public: + uint8_t _aucBuffer[SERIAL_BUFFER_SIZE] ; + int _iHead ; + int _iTail ; + + public: + RingBuffer( void ) ; + void store_char( uint8_t c ) ; +} ; + +#endif /* _RING_BUFFER_ */ diff --git a/hardware/digistump/sam/cores/digix/Server.h b/hardware/digistump/sam/cores/digix/Server.h new file mode 100644 index 0000000..9674c76 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/Server.h @@ -0,0 +1,9 @@ +#ifndef server_h +#define server_h + +class Server : public Print { +public: + virtual void begin() =0; +}; + +#endif diff --git a/hardware/digistump/sam/cores/digix/Stream.cpp b/hardware/digistump/sam/cores/digix/Stream.cpp new file mode 100644 index 0000000..aafb7fc --- /dev/null +++ b/hardware/digistump/sam/cores/digix/Stream.cpp @@ -0,0 +1,270 @@ +/* + Stream.cpp - adds parsing methods to Stream class + Copyright (c) 2008 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Created July 2011 + parsing functions based on TextFinder library by Michael Margolis + */ + +#include "Arduino.h" +#include "Stream.h" + +#define PARSE_TIMEOUT 1000 // default number of milli-seconds to wait +#define NO_SKIP_CHAR 1 // a magic char not found in a valid ASCII numeric field + +// private method to read stream with timeout +int Stream::timedRead() +{ + int c; + _startMillis = millis(); + do { + c = read(); + if (c >= 0) return c; + } while(millis() - _startMillis < _timeout); + return -1; // -1 indicates timeout +} + +// private method to peek stream with timeout +int Stream::timedPeek() +{ + int c; + _startMillis = millis(); + do { + c = peek(); + if (c >= 0) return c; + } while(millis() - _startMillis < _timeout); + return -1; // -1 indicates timeout +} + +// returns peek of the next digit in the stream or -1 if timeout +// discards non-numeric characters +int Stream::peekNextDigit() +{ + int c; + while (1) { + c = timedPeek(); + if (c < 0) return c; // timeout + if (c == '-') return c; + if (c >= '0' && c <= '9') return c; + read(); // discard non-numeric + } +} + +// Public Methods +////////////////////////////////////////////////////////////// + +void Stream::setTimeout(unsigned long timeout) // sets the maximum number of milliseconds to wait +{ + _timeout = timeout; +} + + // find returns true if the target string is found +bool Stream::find(char *target) +{ + return findUntil(target, NULL); +} + +// reads data from the stream until the target string of given length is found +// returns true if target string is found, false if timed out +bool Stream::find(char *target, size_t length) +{ + return findUntil(target, length, NULL, 0); +} + +// as find but search ends if the terminator string is found +bool Stream::findUntil(char *target, char *terminator) +{ + return findUntil(target, strlen(target), terminator, strlen(terminator)); +} + +// reads data from the stream until the target string of the given length is found +// search terminated if the terminator string is found +// returns true if target string is found, false if terminated or timed out +bool Stream::findUntil(char *target, size_t targetLen, char *terminator, size_t termLen) +{ + size_t index = 0; // maximum target string length is 64k bytes! + size_t termIndex = 0; + int c; + + if( *target == 0) + return true; // return true if target is a null string + while( (c = timedRead()) > 0){ + + if(c != target[index]) + index = 0; // reset index if any char does not match + + if( c == target[index]){ + //////Serial.print("found "); Serial.write(c); Serial.print("index now"); Serial.println(index+1); + if(++index >= targetLen){ // return true if all chars in the target match + return true; + } + } + + if(termLen > 0 && c == terminator[termIndex]){ + if(++termIndex >= termLen) + return false; // return false if terminate string found before target string + } + else + termIndex = 0; + } + return false; +} + + +// returns the first valid (long) integer value from the current position. +// initial characters that are not digits (or the minus sign) are skipped +// function is terminated by the first character that is not a digit. +long Stream::parseInt() +{ + return parseInt(NO_SKIP_CHAR); // terminate on first non-digit character (or timeout) +} + +// as above but a given skipChar is ignored +// this allows format characters (typically commas) in values to be ignored +long Stream::parseInt(char skipChar) +{ + boolean isNegative = false; + long value = 0; + int c; + + c = peekNextDigit(); + // ignore non numeric leading characters + if(c < 0) + return 0; // zero returned if timeout + + do{ + if(c == skipChar) + ; // ignore this charactor + else if(c == '-') + isNegative = true; + else if(c >= '0' && c <= '9') // is c a digit? + value = value * 10 + c - '0'; + read(); // consume the character we got with peek + c = timedPeek(); + } + while( (c >= '0' && c <= '9') || c == skipChar ); + + if(isNegative) + value = -value; + return value; +} + + +// as parseInt but returns a floating point value +float Stream::parseFloat() +{ + return parseFloat(NO_SKIP_CHAR); +} + +// as above but the given skipChar is ignored +// this allows format characters (typically commas) in values to be ignored +float Stream::parseFloat(char skipChar){ + boolean isNegative = false; + boolean isFraction = false; + long value = 0; + char c; + float fraction = 1.0; + + c = peekNextDigit(); + // ignore non numeric leading characters + if(c < 0) + return 0; // zero returned if timeout + + do{ + if(c == skipChar) + ; // ignore + else if(c == '-') + isNegative = true; + else if (c == '.') + isFraction = true; + else if(c >= '0' && c <= '9') { // is c a digit? + value = value * 10 + c - '0'; + if(isFraction) + fraction *= 0.1; + } + read(); // consume the character we got with peek + c = timedPeek(); + } + while( (c >= '0' && c <= '9') || c == '.' || c == skipChar ); + + if(isNegative) + value = -value; + if(isFraction) + return value * fraction; + else + return value; +} + +// read characters from stream into buffer +// terminates if length characters have been read, or timeout (see setTimeout) +// returns the number of characters placed in the buffer +// the buffer is NOT null terminated. +// +size_t Stream::readBytes(char *buffer, size_t length) +{ + size_t count = 0; + while (count < length) { + int c = timedRead(); + if (c < 0) break; + *buffer++ = (char)c; + count++; + } + return count; +} + + +// as readBytes with terminator character +// terminates if length characters have been read, timeout, or if the terminator character detected +// returns the number of characters placed in the buffer (0 means no valid data found) + +size_t Stream::readBytesUntil(char terminator, char *buffer, size_t length) +{ + if (length < 1) return 0; + size_t index = 0; + while (index < length) { + int c = timedRead(); + if (c < 0 || c == terminator) break; + *buffer++ = (char)c; + index++; + } + return index; // return number of characters, not including null terminator +} + +String Stream::readString() +{ + String ret; + int c = timedRead(); + while (c >= 0) + { + ret += (char)c; + c = timedRead(); + } + return ret; +} + +String Stream::readStringUntil(char terminator) +{ + String ret; + int c = timedRead(); + while (c >= 0 && c != terminator) + { + ret += (char)c; + c = timedRead(); + } + return ret; +} + diff --git a/hardware/digistump/sam/cores/digix/Stream.h b/hardware/digistump/sam/cores/digix/Stream.h new file mode 100644 index 0000000..007b4bc --- /dev/null +++ b/hardware/digistump/sam/cores/digix/Stream.h @@ -0,0 +1,96 @@ +/* + Stream.h - base class for character-based streams. + Copyright (c) 2010 David A. Mellis. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + parsing functions based on TextFinder library by Michael Margolis +*/ + +#ifndef Stream_h +#define Stream_h + +#include +#include "Print.h" + +// compatability macros for testing +/* +#define getInt() parseInt() +#define getInt(skipChar) parseInt(skipchar) +#define getFloat() parseFloat() +#define getFloat(skipChar) parseFloat(skipChar) +#define getString( pre_string, post_string, buffer, length) +readBytesBetween( pre_string, terminator, buffer, length) +*/ + +class Stream : public Print +{ + protected: + unsigned long _timeout; // number of milliseconds to wait for the next char before aborting timed read + unsigned long _startMillis; // used for timeout measurement + int timedRead(); // private method to read stream with timeout + int timedPeek(); // private method to peek stream with timeout + int peekNextDigit(); // returns the next numeric digit in the stream or -1 if timeout + + public: + virtual int available() = 0; + virtual int read() = 0; + virtual int peek() = 0; + virtual void flush() = 0; + + Stream() {_timeout=1000;} + +// parsing methods + + void setTimeout(unsigned long timeout); // sets maximum milliseconds to wait for stream data, default is 1 second + + bool find(char *target); // reads data from the stream until the target string is found + // returns true if target string is found, false if timed out (see setTimeout) + + bool find(char *target, size_t length); // reads data from the stream until the target string of given length is found + // returns true if target string is found, false if timed out + + bool findUntil(char *target, char *terminator); // as find but search ends if the terminator string is found + + bool findUntil(char *target, size_t targetLen, char *terminate, size_t termLen); // as above but search ends if the terminate string is found + + + long parseInt(); // returns the first valid (long) integer value from the current position. + // initial characters that are not digits (or the minus sign) are skipped + // integer is terminated by the first character that is not a digit. + + float parseFloat(); // float version of parseInt + + size_t readBytes( char *buffer, size_t length); // read chars from stream into buffer + // terminates if length characters have been read or timeout (see setTimeout) + // returns the number of characters placed in the buffer (0 means no valid data found) + + size_t readBytesUntil( char terminator, char *buffer, size_t length); // as readBytes with terminator character + // terminates if length characters have been read, timeout, or if the terminator character detected + // returns the number of characters placed in the buffer (0 means no valid data found) + + // Arduino String functions to be added here + String readString(); + String readStringUntil(char terminator); + + protected: + long parseInt(char skipChar); // as above but the given skipChar is ignored + // as above but the given skipChar is ignored + // this allows format characters (typically commas) in values to be ignored + + float parseFloat(char skipChar); // as above but the given skipChar is ignored +}; + +#endif diff --git a/hardware/digistump/sam/cores/digix/Tone.cpp.disabled b/hardware/digistump/sam/cores/digix/Tone.cpp.disabled new file mode 100644 index 0000000..9bb6fe7 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/Tone.cpp.disabled @@ -0,0 +1,616 @@ +/* Tone.cpp + + A Tone Generator Library + + Written by Brett Hagman + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +Version Modified By Date Comments +------- ----------- -------- -------- +0001 B Hagman 09/08/02 Initial coding +0002 B Hagman 09/08/18 Multiple pins +0003 B Hagman 09/08/18 Moved initialization from constructor to begin() +0004 B Hagman 09/09/26 Fixed problems with ATmega8 +0005 B Hagman 09/11/23 Scanned prescalars for best fit on 8 bit timers + 09/11/25 Changed pin toggle method to XOR + 09/11/25 Fixed timer0 from being excluded +0006 D Mellis 09/12/29 Replaced objects with functions +0007 M Sproul 10/08/29 Changed #ifdefs from cpu to register +0008 S Kanemoto 12/06/22 Fixed for Leonardo by @maris_HY +*************************************************/ + +#include +#include +#include "Arduino.h" +#include "pins_arduino.h" + +#if defined(__AVR_ATmega8__) || defined(__AVR_ATmega128__) +#define TCCR2A TCCR2 +#define TCCR2B TCCR2 +#define COM2A1 COM21 +#define COM2A0 COM20 +#define OCR2A OCR2 +#define TIMSK2 TIMSK +#define OCIE2A OCIE2 +#define TIMER2_COMPA_vect TIMER2_COMP_vect +#define TIMSK1 TIMSK +#endif + +// timerx_toggle_count: +// > 0 - duration specified +// = 0 - stopped +// < 0 - infinitely (until stop() method called, or new play() called) + +#if !defined(__AVR_ATmega8__) +volatile long timer0_toggle_count; +volatile uint8_t *timer0_pin_port; +volatile uint8_t timer0_pin_mask; +#endif + +volatile long timer1_toggle_count; +volatile uint8_t *timer1_pin_port; +volatile uint8_t timer1_pin_mask; +volatile long timer2_toggle_count; +volatile uint8_t *timer2_pin_port; +volatile uint8_t timer2_pin_mask; + +#if defined(TIMSK3) +volatile long timer3_toggle_count; +volatile uint8_t *timer3_pin_port; +volatile uint8_t timer3_pin_mask; +#endif + +#if defined(TIMSK4) +volatile long timer4_toggle_count; +volatile uint8_t *timer4_pin_port; +volatile uint8_t timer4_pin_mask; +#endif + +#if defined(TIMSK5) +volatile long timer5_toggle_count; +volatile uint8_t *timer5_pin_port; +volatile uint8_t timer5_pin_mask; +#endif + + +#if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) + +#define AVAILABLE_TONE_PINS 1 +#define USE_TIMER2 + +const uint8_t PROGMEM tone_pin_to_timer_PGM[] = { 2 /*, 3, 4, 5, 1, 0 */ }; +static uint8_t tone_pins[AVAILABLE_TONE_PINS] = { 255 /*, 255, 255, 255, 255, 255 */ }; + +#elif defined(__AVR_ATmega8__) + +#define AVAILABLE_TONE_PINS 1 +#define USE_TIMER2 + +const uint8_t PROGMEM tone_pin_to_timer_PGM[] = { 2 /*, 1 */ }; +static uint8_t tone_pins[AVAILABLE_TONE_PINS] = { 255 /*, 255 */ }; + +#elif defined(__AVR_ATmega32U4__) + +#define AVAILABLE_TONE_PINS 1 +#define USE_TIMER3 + +const uint8_t PROGMEM tone_pin_to_timer_PGM[] = { 3 /*, 1 */ }; +static uint8_t tone_pins[AVAILABLE_TONE_PINS] = { 255 /*, 255 */ }; + +#else + +#define AVAILABLE_TONE_PINS 1 +#define USE_TIMER2 + +// Leave timer 0 to last. +const uint8_t PROGMEM tone_pin_to_timer_PGM[] = { 2 /*, 1, 0 */ }; +static uint8_t tone_pins[AVAILABLE_TONE_PINS] = { 255 /*, 255, 255 */ }; + +#endif + + + +static int8_t toneBegin(uint8_t _pin) +{ + int8_t _timer = -1; + + // if we're already using the pin, the timer should be configured. + for (int i = 0; i < AVAILABLE_TONE_PINS; i++) { + if (tone_pins[i] == _pin) { + return pgm_read_byte(tone_pin_to_timer_PGM + i); + } + } + + // search for an unused timer. + for (int i = 0; i < AVAILABLE_TONE_PINS; i++) { + if (tone_pins[i] == 255) { + tone_pins[i] = _pin; + _timer = pgm_read_byte(tone_pin_to_timer_PGM + i); + break; + } + } + + if (_timer != -1) + { + // Set timer specific stuff + // All timers in CTC mode + // 8 bit timers will require changing prescalar values, + // whereas 16 bit timers are set to either ck/1 or ck/64 prescalar + switch (_timer) + { + #if defined(TCCR0A) && defined(TCCR0B) + case 0: + // 8 bit timer + TCCR0A = 0; + TCCR0B = 0; + bitWrite(TCCR0A, WGM01, 1); + bitWrite(TCCR0B, CS00, 1); + timer0_pin_port = portOutputRegister(digitalPinToPort(_pin)); + timer0_pin_mask = digitalPinToBitMask(_pin); + break; + #endif + + #if defined(TCCR1A) && defined(TCCR1B) && defined(WGM12) + case 1: + // 16 bit timer + TCCR1A = 0; + TCCR1B = 0; + bitWrite(TCCR1B, WGM12, 1); + bitWrite(TCCR1B, CS10, 1); + timer1_pin_port = portOutputRegister(digitalPinToPort(_pin)); + timer1_pin_mask = digitalPinToBitMask(_pin); + break; + #endif + + #if defined(TCCR2A) && defined(TCCR2B) + case 2: + // 8 bit timer + TCCR2A = 0; + TCCR2B = 0; + bitWrite(TCCR2A, WGM21, 1); + bitWrite(TCCR2B, CS20, 1); + timer2_pin_port = portOutputRegister(digitalPinToPort(_pin)); + timer2_pin_mask = digitalPinToBitMask(_pin); + break; + #endif + + #if defined(TCCR3A) && defined(TCCR3B) && defined(TIMSK3) + case 3: + // 16 bit timer + TCCR3A = 0; + TCCR3B = 0; + bitWrite(TCCR3B, WGM32, 1); + bitWrite(TCCR3B, CS30, 1); + timer3_pin_port = portOutputRegister(digitalPinToPort(_pin)); + timer3_pin_mask = digitalPinToBitMask(_pin); + break; + #endif + + #if defined(TCCR4A) && defined(TCCR4B) && defined(TIMSK4) + case 4: + // 16 bit timer + TCCR4A = 0; + TCCR4B = 0; + #if defined(WGM42) + bitWrite(TCCR4B, WGM42, 1); + #elif defined(CS43) + #warning this may not be correct + // atmega32u4 + bitWrite(TCCR4B, CS43, 1); + #endif + bitWrite(TCCR4B, CS40, 1); + timer4_pin_port = portOutputRegister(digitalPinToPort(_pin)); + timer4_pin_mask = digitalPinToBitMask(_pin); + break; + #endif + + #if defined(TCCR5A) && defined(TCCR5B) && defined(TIMSK5) + case 5: + // 16 bit timer + TCCR5A = 0; + TCCR5B = 0; + bitWrite(TCCR5B, WGM52, 1); + bitWrite(TCCR5B, CS50, 1); + timer5_pin_port = portOutputRegister(digitalPinToPort(_pin)); + timer5_pin_mask = digitalPinToBitMask(_pin); + break; + #endif + } + } + + return _timer; +} + + + +// frequency (in hertz) and duration (in milliseconds). + +void tone(uint8_t _pin, unsigned int frequency, unsigned long duration) +{ + uint8_t prescalarbits = 0b001; + long toggle_count = 0; + uint32_t ocr = 0; + int8_t _timer; + + _timer = toneBegin(_pin); + + if (_timer >= 0) + { + // Set the pinMode as OUTPUT + pinMode(_pin, OUTPUT); + + // if we are using an 8 bit timer, scan through prescalars to find the best fit + if (_timer == 0 || _timer == 2) + { + ocr = F_CPU / frequency / 2 - 1; + prescalarbits = 0b001; // ck/1: same for both timers + if (ocr > 255) + { + ocr = F_CPU / frequency / 2 / 8 - 1; + prescalarbits = 0b010; // ck/8: same for both timers + + if (_timer == 2 && ocr > 255) + { + ocr = F_CPU / frequency / 2 / 32 - 1; + prescalarbits = 0b011; + } + + if (ocr > 255) + { + ocr = F_CPU / frequency / 2 / 64 - 1; + prescalarbits = _timer == 0 ? 0b011 : 0b100; + + if (_timer == 2 && ocr > 255) + { + ocr = F_CPU / frequency / 2 / 128 - 1; + prescalarbits = 0b101; + } + + if (ocr > 255) + { + ocr = F_CPU / frequency / 2 / 256 - 1; + prescalarbits = _timer == 0 ? 0b100 : 0b110; + if (ocr > 255) + { + // can't do any better than /1024 + ocr = F_CPU / frequency / 2 / 1024 - 1; + prescalarbits = _timer == 0 ? 0b101 : 0b111; + } + } + } + } + +#if defined(TCCR0B) + if (_timer == 0) + { + TCCR0B = prescalarbits; + } + else +#endif +#if defined(TCCR2B) + { + TCCR2B = prescalarbits; + } +#else + { + // dummy place holder to make the above ifdefs work + } +#endif + } + else + { + // two choices for the 16 bit timers: ck/1 or ck/64 + ocr = F_CPU / frequency / 2 - 1; + + prescalarbits = 0b001; + if (ocr > 0xffff) + { + ocr = F_CPU / frequency / 2 / 64 - 1; + prescalarbits = 0b011; + } + + if (_timer == 1) + { +#if defined(TCCR1B) + TCCR1B = (TCCR1B & 0b11111000) | prescalarbits; +#endif + } +#if defined(TCCR3B) + else if (_timer == 3) + TCCR3B = (TCCR3B & 0b11111000) | prescalarbits; +#endif +#if defined(TCCR4B) + else if (_timer == 4) + TCCR4B = (TCCR4B & 0b11111000) | prescalarbits; +#endif +#if defined(TCCR5B) + else if (_timer == 5) + TCCR5B = (TCCR5B & 0b11111000) | prescalarbits; +#endif + + } + + + // Calculate the toggle count + if (duration > 0) + { + toggle_count = 2 * frequency * duration / 1000; + } + else + { + toggle_count = -1; + } + + // Set the OCR for the given timer, + // set the toggle count, + // then turn on the interrupts + switch (_timer) + { + +#if defined(OCR0A) && defined(TIMSK0) && defined(OCIE0A) + case 0: + OCR0A = ocr; + timer0_toggle_count = toggle_count; + bitWrite(TIMSK0, OCIE0A, 1); + break; +#endif + + case 1: +#if defined(OCR1A) && defined(TIMSK1) && defined(OCIE1A) + OCR1A = ocr; + timer1_toggle_count = toggle_count; + bitWrite(TIMSK1, OCIE1A, 1); +#elif defined(OCR1A) && defined(TIMSK) && defined(OCIE1A) + // this combination is for at least the ATmega32 + OCR1A = ocr; + timer1_toggle_count = toggle_count; + bitWrite(TIMSK, OCIE1A, 1); +#endif + break; + +#if defined(OCR2A) && defined(TIMSK2) && defined(OCIE2A) + case 2: + OCR2A = ocr; + timer2_toggle_count = toggle_count; + bitWrite(TIMSK2, OCIE2A, 1); + break; +#endif + +#if defined(TIMSK3) + case 3: + OCR3A = ocr; + timer3_toggle_count = toggle_count; + bitWrite(TIMSK3, OCIE3A, 1); + break; +#endif + +#if defined(TIMSK4) + case 4: + OCR4A = ocr; + timer4_toggle_count = toggle_count; + bitWrite(TIMSK4, OCIE4A, 1); + break; +#endif + +#if defined(OCR5A) && defined(TIMSK5) && defined(OCIE5A) + case 5: + OCR5A = ocr; + timer5_toggle_count = toggle_count; + bitWrite(TIMSK5, OCIE5A, 1); + break; +#endif + + } + } +} + + +// XXX: this function only works properly for timer 2 (the only one we use +// currently). for the others, it should end the tone, but won't restore +// proper PWM functionality for the timer. +void disableTimer(uint8_t _timer) +{ + switch (_timer) + { + case 0: + #if defined(TIMSK0) + TIMSK0 = 0; + #elif defined(TIMSK) + TIMSK = 0; // atmega32 + #endif + break; + +#if defined(TIMSK1) && defined(OCIE1A) + case 1: + bitWrite(TIMSK1, OCIE1A, 0); + break; +#endif + + case 2: + #if defined(TIMSK2) && defined(OCIE2A) + bitWrite(TIMSK2, OCIE2A, 0); // disable interrupt + #endif + #if defined(TCCR2A) && defined(WGM20) + TCCR2A = (1 << WGM20); + #endif + #if defined(TCCR2B) && defined(CS22) + TCCR2B = (TCCR2B & 0b11111000) | (1 << CS22); + #endif + #if defined(OCR2A) + OCR2A = 0; + #endif + break; + +#if defined(TIMSK3) + case 3: + TIMSK3 = 0; + break; +#endif + +#if defined(TIMSK4) + case 4: + TIMSK4 = 0; + break; +#endif + +#if defined(TIMSK5) + case 5: + TIMSK5 = 0; + break; +#endif + } +} + + +void noTone(uint8_t _pin) +{ + int8_t _timer = -1; + + for (int i = 0; i < AVAILABLE_TONE_PINS; i++) { + if (tone_pins[i] == _pin) { + _timer = pgm_read_byte(tone_pin_to_timer_PGM + i); + tone_pins[i] = 255; + } + } + + disableTimer(_timer); + + digitalWrite(_pin, 0); +} + +#ifdef USE_TIMER0 +ISR(TIMER0_COMPA_vect) +{ + if (timer0_toggle_count != 0) + { + // toggle the pin + *timer0_pin_port ^= timer0_pin_mask; + + if (timer0_toggle_count > 0) + timer0_toggle_count--; + } + else + { + disableTimer(0); + *timer0_pin_port &= ~(timer0_pin_mask); // keep pin low after stop + } +} +#endif + + +#ifdef USE_TIMER1 +ISR(TIMER1_COMPA_vect) +{ + if (timer1_toggle_count != 0) + { + // toggle the pin + *timer1_pin_port ^= timer1_pin_mask; + + if (timer1_toggle_count > 0) + timer1_toggle_count--; + } + else + { + disableTimer(1); + *timer1_pin_port &= ~(timer1_pin_mask); // keep pin low after stop + } +} +#endif + + +#ifdef USE_TIMER2 +ISR(TIMER2_COMPA_vect) +{ + + if (timer2_toggle_count != 0) + { + // toggle the pin + *timer2_pin_port ^= timer2_pin_mask; + + if (timer2_toggle_count > 0) + timer2_toggle_count--; + } + else + { + // need to call noTone() so that the tone_pins[] entry is reset, so the + // timer gets initialized next time we call tone(). + // XXX: this assumes timer 2 is always the first one used. + noTone(tone_pins[0]); +// disableTimer(2); +// *timer2_pin_port &= ~(timer2_pin_mask); // keep pin low after stop + } +} +#endif + + +#ifdef USE_TIMER3 +ISR(TIMER3_COMPA_vect) +{ + if (timer3_toggle_count != 0) + { + // toggle the pin + *timer3_pin_port ^= timer3_pin_mask; + + if (timer3_toggle_count > 0) + timer3_toggle_count--; + } + else + { + disableTimer(3); + *timer3_pin_port &= ~(timer3_pin_mask); // keep pin low after stop + } +} +#endif + + +#ifdef USE_TIMER4 +ISR(TIMER4_COMPA_vect) +{ + if (timer4_toggle_count != 0) + { + // toggle the pin + *timer4_pin_port ^= timer4_pin_mask; + + if (timer4_toggle_count > 0) + timer4_toggle_count--; + } + else + { + disableTimer(4); + *timer4_pin_port &= ~(timer4_pin_mask); // keep pin low after stop + } +} +#endif + + +#ifdef USE_TIMER5 +ISR(TIMER5_COMPA_vect) +{ + if (timer5_toggle_count != 0) + { + // toggle the pin + *timer5_pin_port ^= timer5_pin_mask; + + if (timer5_toggle_count > 0) + timer5_toggle_count--; + } + else + { + disableTimer(5); + *timer5_pin_port &= ~(timer5_pin_mask); // keep pin low after stop + } +} +#endif diff --git a/hardware/digistump/sam/cores/digix/Tone.h b/hardware/digistump/sam/cores/digix/Tone.h new file mode 100644 index 0000000..5789b08 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/Tone.h @@ -0,0 +1,23 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_TONE_ +#define _WIRING_TONE_ + + +#endif /* _WIRING_TONE_ */ diff --git a/hardware/digistump/sam/cores/digix/UARTClass.cpp b/hardware/digistump/sam/cores/digix/UARTClass.cpp new file mode 100644 index 0000000..16188b1 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/UARTClass.cpp @@ -0,0 +1,137 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include +#include +#include +#include "UARTClass.h" + +// Constructors //////////////////////////////////////////////////////////////// + +UARTClass::UARTClass( Uart* pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer ) +{ + _rx_buffer = pRx_buffer ; + + _pUart=pUart ; + _dwIrq=dwIrq ; + _dwId=dwId ; +} + +// Public Methods ////////////////////////////////////////////////////////////// + +void UARTClass::begin( const uint32_t dwBaudRate ) +{ + // Configure PMC + pmc_enable_periph_clk( _dwId ) ; + + // Disable PDC channel + _pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS ; + + // Reset and disable receiver and transmitter + _pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS ; + + // Configure mode + _pUart->UART_MR = UART_MR_PAR_NO | UART_MR_CHMODE_NORMAL ; + + // Configure baudrate (asynchronous, no oversampling) + _pUart->UART_BRGR = (SystemCoreClock / dwBaudRate) >> 4 ; + + // Configure interrupts + _pUart->UART_IDR = 0xFFFFFFFF; + _pUart->UART_IER = UART_IER_RXRDY | UART_IER_OVRE | UART_IER_FRAME; + + // Enable UART interrupt in NVIC + NVIC_EnableIRQ(_dwIrq); + + // Enable receiver and transmitter + _pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN ; +} + +void UARTClass::end( void ) +{ + // clear any received data + _rx_buffer->_iHead = _rx_buffer->_iTail ; + + // Disable UART interrupt in NVIC + NVIC_DisableIRQ( _dwIrq ) ; + + // Wait for any outstanding data to be sent + flush(); + + pmc_disable_periph_clk( _dwId ) ; +} + +int UARTClass::available( void ) +{ + return (uint32_t)(SERIAL_BUFFER_SIZE + _rx_buffer->_iHead - _rx_buffer->_iTail) % SERIAL_BUFFER_SIZE ; +} + +int UARTClass::peek( void ) +{ + if ( _rx_buffer->_iHead == _rx_buffer->_iTail ) + return -1 ; + + return _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ; +} + +int UARTClass::read( void ) +{ + // if the head isn't ahead of the tail, we don't have any characters + if ( _rx_buffer->_iHead == _rx_buffer->_iTail ) + return -1 ; + + uint8_t uc = _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ; + _rx_buffer->_iTail = (unsigned int)(_rx_buffer->_iTail + 1) % SERIAL_BUFFER_SIZE ; + return uc ; +} + +void UARTClass::flush( void ) +{ + // Wait for transmission to complete + while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY) + ; +} + +size_t UARTClass::write( const uint8_t uc_data ) +{ + // Check if the transmitter is ready + while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY) + ; + + // Send character + _pUart->UART_THR = uc_data; + return 1; +} + +void UARTClass::IrqHandler( void ) +{ + uint32_t status = _pUart->UART_SR; + + // Did we receive data ? + if ((status & UART_SR_RXRDY) == UART_SR_RXRDY) + _rx_buffer->store_char(_pUart->UART_RHR); + + // Acknowledge errors + if ((status & UART_SR_OVRE) == UART_SR_OVRE || + (status & UART_SR_FRAME) == UART_SR_FRAME) + { + // TODO: error reporting outside ISR + _pUart->UART_CR |= UART_CR_RSTSTA; + } +} + diff --git a/hardware/digistump/sam/cores/digix/UARTClass.h b/hardware/digistump/sam/cores/digix/UARTClass.h new file mode 100644 index 0000000..5836f2e --- /dev/null +++ b/hardware/digistump/sam/cores/digix/UARTClass.h @@ -0,0 +1,61 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _UART_CLASS_ +#define _UART_CLASS_ + +#include "HardwareSerial.h" +#include "RingBuffer.h" + +// Includes Atmel CMSIS +#include + +class UARTClass : public HardwareSerial +{ + protected: + RingBuffer *_rx_buffer ; + + protected: + Uart* _pUart ; + IRQn_Type _dwIrq ; + uint32_t _dwId ; + + public: + UARTClass( Uart* pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer ) ; + + void begin( const uint32_t dwBaudRate ) ; + void end( void ) ; + int available( void ) ; + int peek( void ) ; + int read( void ) ; + void flush( void ) ; + size_t write( const uint8_t c ) ; + + void IrqHandler( void ) ; + +#if defined __GNUC__ /* GCC CS3 */ + using Print::write ; // pull in write(str) and write(buf, size) from Print +#elif defined __ICCARM__ /* IAR Ewarm 5.41+ */ +// virtual void write( const char *str ) ; +// virtual void write( const uint8_t *buffer, size_t size ) ; +#endif + + operator bool() { return true; }; // UART always active +}; + +#endif // _UART_CLASS_ diff --git a/hardware/digistump/sam/cores/digix/USARTClass.cpp b/hardware/digistump/sam/cores/digix/USARTClass.cpp new file mode 100644 index 0000000..3cc13ac --- /dev/null +++ b/hardware/digistump/sam/cores/digix/USARTClass.cpp @@ -0,0 +1,183 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include +#include +#include +#include +#include +#include +#include "USARTClass.h" + +// Constructors //////////////////////////////////////////////////////////////// + +USARTClass::USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer ) +{ + _rx_buffer = pRx_buffer ; + + _pUsart=pUsart ; + _dwIrq=dwIrq ; + _dwId=dwId ; + ctsEn=false; +} + +// Public Methods ////////////////////////////////////////////////////////////// + +void USARTClass::begin( const uint32_t dwBaudRate ) +{ + if(ctsEn) + { + pinMode(ctsPin, OUTPUT); + digitalWrite(ctsPin, HIGH); + cts=HIGH; + } + + // Configure PMC + pmc_enable_periph_clk( _dwId ) ; + + // Disable PDC channel + _pUsart->US_PTCR = US_PTCR_RXTDIS | US_PTCR_TXTDIS ; + + // Reset and disable receiver and transmitter + _pUsart->US_CR = US_CR_RSTRX | US_CR_RSTTX | US_CR_RXDIS | US_CR_TXDIS ; + + // Configure mode + _pUsart->US_MR = US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_NO | + US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL; + + // Configure baudrate, asynchronous no oversampling + _pUsart->US_BRGR = (SystemCoreClock / dwBaudRate) / 16 ; + + // Configure interrupts + _pUsart->US_IDR = 0xFFFFFFFF; + _pUsart->US_IER = US_IER_RXRDY | US_IER_OVRE | US_IER_FRAME; + + // Enable UART interrupt in NVIC + NVIC_EnableIRQ( _dwIrq ) ; + + // Enable receiver and transmitter + _pUsart->US_CR = US_CR_RXEN | US_CR_TXEN ; + + if(ctsEn) + ctsCheck(); +} + +void USARTClass::enableCTS(boolean enabled) +{ + ctsEn=enabled; + if(ctsEn) + ctsCheck(); +} + +void USARTClass::setCTSPin(int pin) +{ + ctsPin=pin; +} + +void USARTClass::end( void ) +{ + // clear any received data + _rx_buffer->_iHead = _rx_buffer->_iTail ; + + // Disable UART interrupt in NVIC + NVIC_DisableIRQ( _dwIrq ) ; + + // Wait for any outstanding data to be sent + flush(); + + pmc_disable_periph_clk( _dwId ) ; +} + +int USARTClass::available( void ) +{ + return (uint32_t)(SERIAL_BUFFER_SIZE + _rx_buffer->_iHead - _rx_buffer->_iTail) % SERIAL_BUFFER_SIZE ; +} + +int USARTClass::peek( void ) +{ + if ( _rx_buffer->_iHead == _rx_buffer->_iTail ) + return -1 ; + + return _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ; +} + +int USARTClass::read( void ) +{ + // if the head isn't ahead of the tail, we don't have any characters + if ( _rx_buffer->_iHead == _rx_buffer->_iTail ) + return -1 ; + + uint8_t uc = _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ; + _rx_buffer->_iTail = (unsigned int)(_rx_buffer->_iTail + 1) % SERIAL_BUFFER_SIZE ; + if(ctsEn) + ctsCheck(); + return uc ; +} + +void USARTClass::flush( void ) +{ + // Wait for transmission to complete + while ((_pUsart->US_CSR & US_CSR_TXRDY) != US_CSR_TXRDY) + ; +} + +size_t USARTClass::write( const uint8_t uc_data ) +{ + // Check if the transmitter is ready + while ((_pUsart->US_CSR & US_CSR_TXRDY) != US_CSR_TXRDY) + ; + + // Send character + _pUsart->US_THR = uc_data ; + return 1; +} + +void USARTClass::ctsCheck() +{ + avail=available(); + if(avail > SERIAL_BUFFER_SIZE - 8 && cts==LOW) + { + digitalWrite(ctsPin, HIGH); + cts=HIGH; + } + else if(avail < SERIAL_BUFFER_SIZE - 8 && cts==HIGH) + { + digitalWrite(ctsPin, LOW); + cts=LOW; + } +} + +void USARTClass::IrqHandler( void ) +{ + uint32_t status = _pUsart->US_CSR; + + // Did we receive data ? + if ((status & US_CSR_RXRDY) == US_CSR_RXRDY) + _rx_buffer->store_char( _pUsart->US_RHR ) ; + + // Acknowledge errors + if ((status & US_CSR_OVRE) == US_CSR_OVRE || + (status & US_CSR_FRAME) == US_CSR_FRAME) + { + // TODO: error reporting outside ISR + _pUsart->US_CR |= US_CR_RSTSTA; + } + if(ctsEn) + ctsCheck(); +} + diff --git a/hardware/digistump/sam/cores/digix/USARTClass.h b/hardware/digistump/sam/cores/digix/USARTClass.h new file mode 100644 index 0000000..babc54b --- /dev/null +++ b/hardware/digistump/sam/cores/digix/USARTClass.h @@ -0,0 +1,71 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _USART_CLASS_ +#define _USART_CLASS_ + +#include +#include +#include +#include +#include +// Includes Atmel CMSIS +#include + +class USARTClass : public HardwareSerial +{ + protected: + RingBuffer *_rx_buffer ; + + protected: + Usart* _pUsart ; + IRQn_Type _dwIrq ; + uint32_t _dwId ; + int cts; + int ctsEn; + int ctsPin; + int avail; + + public: + USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer ) ; + + void begin( const uint32_t dwBaudRate ) ; + void end( void ) ; + void enableCTS( boolean ); + void setCTSPin( int ) ; + int available( void ) ; + int peek( void ) ; + int read( void ) ; + void flush( void ) ; + size_t write( const uint8_t c ) ; + + void ctsCheck(); + + void IrqHandler( void ) ; + +#if defined __GNUC__ /* GCC CS3 */ + using Print::write ; // pull in write(str) and write(buf, size) from Print +#elif defined __ICCARM__ /* IAR Ewarm 5.41+ */ +// virtual void write( const char *str ) ; +// virtual void write( const uint8_t *buffer, size_t size ) ; +#endif + + operator bool() { return true; }; // USART always active +}; + +#endif // _USART_CLASS_ diff --git a/hardware/digistump/sam/cores/digix/USB/CDC.cpp b/hardware/digistump/sam/cores/digix/USB/CDC.cpp new file mode 100644 index 0000000..292d7e7 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/USB/CDC.cpp @@ -0,0 +1,301 @@ +/* Copyright (c) 2011, Peter Barrett +** +** Permission to use, copy, modify, and/or distribute this software for +** any purpose with or without fee is hereby granted, provided that the +** above copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL +** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR +** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES +** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +** SOFTWARE. +*/ + +#include "Arduino.h" +#include "USBAPI.h" +#include "Reset.h" + +#ifdef CDC_ENABLED + +#define CDC_SERIAL_BUFFER_SIZE 512 + +/* For information purpose only since RTS is not always handled by the terminal application */ +#define CDC_LINESTATE_DTR 0x01 // Data Terminal Ready +#define CDC_LINESTATE_RTS 0x02 // Ready to Send + +#define CDC_LINESTATE_READY (CDC_LINESTATE_RTS | CDC_LINESTATE_DTR) + +struct ring_buffer +{ + uint8_t buffer[CDC_SERIAL_BUFFER_SIZE]; + volatile uint32_t head; + volatile uint32_t tail; +}; + +ring_buffer cdc_rx_buffer = { { 0 }, 0, 0}; + +typedef struct +{ + uint32_t dwDTERate; + uint8_t bCharFormat; + uint8_t bParityType; + uint8_t bDataBits; + uint8_t lineState; +} LineInfo; + +static volatile LineInfo _usbLineInfo = { + 57600, // dWDTERate + 0x00, // bCharFormat + 0x00, // bParityType + 0x08, // bDataBits + 0x00 // lineState +}; + +_Pragma("pack(1)") +static const CDCDescriptor _cdcInterface = +{ + D_IAD(0,2,CDC_COMMUNICATION_INTERFACE_CLASS,CDC_ABSTRACT_CONTROL_MODEL,1), + + // CDC communication interface + D_INTERFACE(CDC_ACM_INTERFACE,1,CDC_COMMUNICATION_INTERFACE_CLASS,CDC_ABSTRACT_CONTROL_MODEL,0), + D_CDCCS(CDC_HEADER,0x10,0x01), // Header (1.10 bcd) + D_CDCCS(CDC_CALL_MANAGEMENT,1,1), // Device handles call management (not) + D_CDCCS4(CDC_ABSTRACT_CONTROL_MANAGEMENT,6), // SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported + D_CDCCS(CDC_UNION,CDC_ACM_INTERFACE,CDC_DATA_INTERFACE), // Communication interface is master, data interface is slave 0 + D_ENDPOINT(USB_ENDPOINT_IN (CDC_ENDPOINT_ACM),USB_ENDPOINT_TYPE_INTERRUPT,0x10, 0x10), + + // CDC data interface + D_INTERFACE(CDC_DATA_INTERFACE,2,CDC_DATA_INTERFACE_CLASS,0,0), + D_ENDPOINT(USB_ENDPOINT_OUT(CDC_ENDPOINT_OUT),USB_ENDPOINT_TYPE_BULK,512,0), + D_ENDPOINT(USB_ENDPOINT_IN (CDC_ENDPOINT_IN ),USB_ENDPOINT_TYPE_BULK,512,0) +}; +static const CDCDescriptor _cdcOtherInterface = +{ + D_IAD(0,2,CDC_COMMUNICATION_INTERFACE_CLASS,CDC_ABSTRACT_CONTROL_MODEL,1), + + // CDC communication interface + D_INTERFACE(CDC_ACM_INTERFACE,1,CDC_COMMUNICATION_INTERFACE_CLASS,CDC_ABSTRACT_CONTROL_MODEL,0), + D_CDCCS(CDC_HEADER,0x10,0x01), // Header (1.10 bcd) + D_CDCCS(CDC_CALL_MANAGEMENT,1,1), // Device handles call management (not) + D_CDCCS4(CDC_ABSTRACT_CONTROL_MANAGEMENT,6), // SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported + D_CDCCS(CDC_UNION,CDC_ACM_INTERFACE,CDC_DATA_INTERFACE), // Communication interface is master, data interface is slave 0 + D_ENDPOINT(USB_ENDPOINT_IN (CDC_ENDPOINT_ACM),USB_ENDPOINT_TYPE_INTERRUPT,0x10, 0x10), + + // CDC data interface + D_INTERFACE(CDC_DATA_INTERFACE,2,CDC_DATA_INTERFACE_CLASS,0,0), + D_ENDPOINT(USB_ENDPOINT_OUT(CDC_ENDPOINT_OUT),USB_ENDPOINT_TYPE_BULK,64,0), + D_ENDPOINT(USB_ENDPOINT_IN (CDC_ENDPOINT_IN ),USB_ENDPOINT_TYPE_BULK,64,0) +}; +_Pragma("pack()") + +int WEAK CDC_GetInterface(uint8_t* interfaceNum) +{ + interfaceNum[0] += 2; // uses 2 + return USBD_SendControl(0,&_cdcInterface,sizeof(_cdcInterface)); +} + +int WEAK CDC_GetOtherInterface(uint8_t* interfaceNum) +{ + interfaceNum[0] += 2; // uses 2 + return USBD_SendControl(0,&_cdcOtherInterface,sizeof(_cdcOtherInterface)); +} + +bool WEAK CDC_Setup(Setup& setup) +{ + uint8_t r = setup.bRequest; + uint8_t requestType = setup.bmRequestType; + + if (REQUEST_DEVICETOHOST_CLASS_INTERFACE == requestType) + { + if (CDC_GET_LINE_CODING == r) + { + USBD_SendControl(0,(void*)&_usbLineInfo,7); + return true; + } + } + + if (REQUEST_HOSTTODEVICE_CLASS_INTERFACE == requestType) + { + if (CDC_SET_LINE_CODING == r) + { + USBD_RecvControl((void*)&_usbLineInfo,7); + return true; + } + + if (CDC_SET_CONTROL_LINE_STATE == r) + { + _usbLineInfo.lineState = setup.wValueL; + // auto-reset into the bootloader is triggered when the port, already + // open at 1200 bps, is closed. + if (1200 == _usbLineInfo.dwDTERate) + { + // We check DTR state to determine if host port is open (bit 0 of lineState). + if ((_usbLineInfo.lineState & 0x01) == 0) + initiateReset(250); + else + cancelReset(); + } + return true; + } + } + return false; +} + +int _serialPeek = -1; +void Serial_::begin(uint32_t baud_count) +{ +} + +void Serial_::begin(uint32_t baud_count, uint8_t config) +{ +} + +void Serial_::end(void) +{ +} + +void Serial_::accept(void) +{ + static uint32_t guard = 0; + + // synchronized access to guard + do { + if (__LDREXW(&guard) != 0) { + __CLREX(); + return; // busy + } + } while (__STREXW(1, &guard) != 0); // retry until write succeed + + ring_buffer *buffer = &cdc_rx_buffer; + uint32_t i = (uint32_t)(buffer->head+1) % CDC_SERIAL_BUFFER_SIZE; + + // if we should be storing the received character into the location + // just before the tail (meaning that the head would advance to the + // current location of the tail), we're about to overflow the buffer + // and so we don't write the character or advance the head. + while (i != buffer->tail) { + uint32_t c; + if (!USBD_Available(CDC_RX)) { + udd_ack_fifocon(CDC_RX); + break; + } + c = USBD_Recv(CDC_RX); + // c = UDD_Recv8(CDC_RX & 0xF); + buffer->buffer[buffer->head] = c; + buffer->head = i; + + i = (i + 1) % CDC_SERIAL_BUFFER_SIZE; + } + + // release the guard + guard = 0; +} + +int Serial_::available(void) +{ + ring_buffer *buffer = &cdc_rx_buffer; + return (unsigned int)(CDC_SERIAL_BUFFER_SIZE + buffer->head - buffer->tail) % CDC_SERIAL_BUFFER_SIZE; +} + +int Serial_::peek(void) +{ + ring_buffer *buffer = &cdc_rx_buffer; + + if (buffer->head == buffer->tail) + { + return -1; + } + else + { + return buffer->buffer[buffer->tail]; + } +} + +int Serial_::read(void) +{ + ring_buffer *buffer = &cdc_rx_buffer; + + // if the head isn't ahead of the tail, we don't have any characters + if (buffer->head == buffer->tail) + { + return -1; + } + else + { + unsigned char c = buffer->buffer[buffer->tail]; + buffer->tail = (unsigned int)(buffer->tail + 1) % CDC_SERIAL_BUFFER_SIZE; + if (USBD_Available(CDC_RX)) + accept(); + return c; + } +} + +void Serial_::flush(void) +{ + USBD_Flush(CDC_TX); +} + +size_t Serial_::write(const uint8_t *buffer, size_t size) +{ + /* only try to send bytes if the high-level CDC connection itself + is open (not just the pipe) - the OS should set lineState when the port + is opened and clear lineState when the port is closed. + bytes sent before the user opens the connection or after + the connection is closed are lost - just like with a UART. */ + + // TODO - ZE - check behavior on different OSes and test what happens if an + // open connection isn't broken cleanly (cable is yanked out, host dies + // or locks up, or host virtual serial port hangs) + if (_usbLineInfo.lineState > 0) + { + int r = USBD_Send(CDC_TX, buffer, size); + + if (r > 0) + { + return r; + } else + { + setWriteError(); + return 0; + } + } + setWriteError(); + return 0; +} + +size_t Serial_::write(uint8_t c) { + return write(&c, 1); +} + +// This operator is a convenient way for a sketch to check whether the +// port has actually been configured and opened by the host (as opposed +// to just being connected to the host). It can be used, for example, in +// setup() before printing to ensure that an application on the host is +// actually ready to receive and display the data. +// We add a short delay before returning to fix a bug observed by Federico +// where the port is configured (lineState != 0) but not quite opened. +Serial_::operator bool() +{ + // this is here to avoid spurious opening after upload + if (millis() < 500) + return false; + + bool result = false; + + if (_usbLineInfo.lineState > 0) + { + result = true; + } + + delay(10); + return result; +} + +Serial_ SerialUSB; +Serial_ Serial; + + +#endif diff --git a/hardware/digistump/sam/cores/digix/USB/HID.cpp b/hardware/digistump/sam/cores/digix/USB/HID.cpp new file mode 100644 index 0000000..c243f49 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/USB/HID.cpp @@ -0,0 +1,518 @@ +/* Copyright (c) 2011, Peter Barrett +** +** Permission to use, copy, modify, and/or distribute this software for +** any purpose with or without fee is hereby granted, provided that the +** above copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL +** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR +** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES +** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +** SOFTWARE. +*/ + +#include "Arduino.h" + +#ifdef HID_ENABLED + +//#define RAWHID_ENABLED + +// Singletons for mouse and keyboard + +Mouse_ Mouse; +Keyboard_ Keyboard; + +//================================================================================ +//================================================================================ + +// HID report descriptor + +#define LSB(_x) ((_x) & 0xFF) +#define MSB(_x) ((_x) >> 8) + +#define RAWHID_USAGE_PAGE 0xFFC0 +#define RAWHID_USAGE 0x0C00 +#define RAWHID_TX_SIZE 64 +#define RAWHID_RX_SIZE 64 + +extern const uint8_t _hidReportDescriptor[] = { + // Mouse + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) // 54 + 0x09, 0x02, // USAGE (Mouse) + 0xa1, 0x01, // COLLECTION (Application) + 0x09, 0x01, // USAGE (Pointer) + 0xa1, 0x00, // COLLECTION (Physical) + 0x85, 0x01, // REPORT_ID (1) + 0x05, 0x09, // USAGE_PAGE (Button) + 0x19, 0x01, // USAGE_MINIMUM (Button 1) + 0x29, 0x03, // USAGE_MAXIMUM (Button 3) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x95, 0x03, // REPORT_COUNT (3) + 0x75, 0x01, // REPORT_SIZE (1) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x05, // REPORT_SIZE (5) + 0x81, 0x03, // INPUT (Cnst,Var,Abs) + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x30, // USAGE (X) + 0x09, 0x31, // USAGE (Y) + 0x09, 0x38, // USAGE (Wheel) + 0x15, 0x81, // LOGICAL_MINIMUM (-127) + 0x25, 0x7f, // LOGICAL_MAXIMUM (127) + 0x75, 0x08, // REPORT_SIZE (8) + 0x95, 0x03, // REPORT_COUNT (3) + 0x81, 0x06, // INPUT (Data,Var,Rel) + 0xc0, // END_COLLECTION + 0xc0, // END_COLLECTION + + // Keyboard + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) // 47 + 0x09, 0x06, // USAGE (Keyboard) + 0xa1, 0x01, // COLLECTION (Application) + 0x85, 0x02, // REPORT_ID (2) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + + 0x19, 0xe0, // USAGE_MINIMUM (Keyboard LeftControl) + 0x29, 0xe7, // USAGE_MAXIMUM (Keyboard Right GUI) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x75, 0x01, // REPORT_SIZE (1) + + 0x95, 0x08, // REPORT_COUNT (8) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x08, // REPORT_SIZE (8) + 0x81, 0x03, // INPUT (Cnst,Var,Abs) + + 0x95, 0x06, // REPORT_COUNT (6) + 0x75, 0x08, // REPORT_SIZE (8) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x65, // LOGICAL_MAXIMUM (101) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + + 0x19, 0x00, // USAGE_MINIMUM (Reserved (no event indicated)) + 0x29, 0x65, // USAGE_MAXIMUM (Keyboard Application) + 0x81, 0x00, // INPUT (Data,Ary,Abs) + 0xc0, // END_COLLECTION + +#ifdef RAWHID_ENABLED + // RAW HID + 0x06, LSB(RAWHID_USAGE_PAGE), MSB(RAWHID_USAGE_PAGE), // 30 + 0x0A, LSB(RAWHID_USAGE), MSB(RAWHID_USAGE), + + 0xA1, 0x01, // Collection 0x01 + 0x85, 0x03, // REPORT_ID (3) + 0x75, 0x08, // report size = 8 bits + 0x15, 0x00, // logical minimum = 0 + 0x26, 0xFF, 0x00, // logical maximum = 255 + + 0x95, 64, // report count TX + 0x09, 0x01, // usage + 0x81, 0x02, // Input (array) + + 0x95, 64, // report count RX + 0x09, 0x02, // usage + 0x91, 0x02, // Output (array) + 0xC0 // end collection +#endif +}; + +_Pragma("pack(1)") +extern const HIDDescriptor _hidInterface = +{ + D_INTERFACE(HID_INTERFACE,1,3,0,0), + D_HIDREPORT(sizeof(_hidReportDescriptor)), + D_ENDPOINT(USB_ENDPOINT_IN(HID_ENDPOINT_INT),USB_ENDPOINT_TYPE_INTERRUPT,0x40,0x01) +}; +_Pragma("pack()") + +//================================================================================ +//================================================================================ +// Driver + +uint8_t _hid_protocol = 1; +uint8_t _hid_idle = 1; + +#define WEAK __attribute__ ((weak)) + +int WEAK HID_GetInterface(uint8_t* interfaceNum) +{ + interfaceNum[0] += 1; // uses 1 + return USBD_SendControl(0,&_hidInterface,sizeof(_hidInterface)); +} + +int WEAK HID_GetDescriptor(int i) +{ + return USBD_SendControl(0,_hidReportDescriptor,sizeof(_hidReportDescriptor)); +} + +void WEAK HID_SendReport(uint8_t id, const void* data, uint32_t len) +{ + uint8_t p[64]; + const uint8_t *d = reinterpret_cast(data); + + p[0] = id; + for (uint32_t i=0; i 0) + return true; + return false; +} + +//================================================================================ +//================================================================================ +// Keyboard + +Keyboard_::Keyboard_(void) +{ +} + +void Keyboard_::begin(void) +{ +} + +void Keyboard_::end(void) +{ +} + +void Keyboard_::sendReport(KeyReport* keys) +{ + HID_SendReport(2,keys,sizeof(KeyReport)); +} + +#define SHIFT 0x80 +extern const uint8_t _asciimap[128] = +{ + 0x00, // NUL + 0x00, // SOH + 0x00, // STX + 0x00, // ETX + 0x00, // EOT + 0x00, // ENQ + 0x00, // ACK + 0x00, // BEL + 0x2a, // BS Backspace + 0x2b, // TAB Tab + 0x28, // LF Enter + 0x00, // VT + 0x00, // FF + 0x00, // CR + 0x00, // SO + 0x00, // SI + 0x00, // DEL + 0x00, // DC1 + 0x00, // DC2 + 0x00, // DC3 + 0x00, // DC4 + 0x00, // NAK + 0x00, // SYN + 0x00, // ETB + 0x00, // CAN + 0x00, // EM + 0x00, // SUB + 0x00, // ESC + 0x00, // FS + 0x00, // GS + 0x00, // RS + 0x00, // US + + 0x2c, // ' ' + 0x1e|SHIFT, // ! + 0x34|SHIFT, // " + 0x20|SHIFT, // # + 0x21|SHIFT, // $ + 0x22|SHIFT, // % + 0x24|SHIFT, // & + 0x34, // ' + 0x26|SHIFT, // ( + 0x27|SHIFT, // ) + 0x25|SHIFT, // * + 0x2e|SHIFT, // + + 0x36, // , + 0x2d, // - + 0x37, // . + 0x38, // / + 0x27, // 0 + 0x1e, // 1 + 0x1f, // 2 + 0x20, // 3 + 0x21, // 4 + 0x22, // 5 + 0x23, // 6 + 0x24, // 7 + 0x25, // 8 + 0x26, // 9 + 0x33|SHIFT, // : + 0x33, // ; + 0x36|SHIFT, // < + 0x2e, // = + 0x37|SHIFT, // > + 0x38|SHIFT, // ? + 0x1f|SHIFT, // @ + 0x04|SHIFT, // A + 0x05|SHIFT, // B + 0x06|SHIFT, // C + 0x07|SHIFT, // D + 0x08|SHIFT, // E + 0x09|SHIFT, // F + 0x0a|SHIFT, // G + 0x0b|SHIFT, // H + 0x0c|SHIFT, // I + 0x0d|SHIFT, // J + 0x0e|SHIFT, // K + 0x0f|SHIFT, // L + 0x10|SHIFT, // M + 0x11|SHIFT, // N + 0x12|SHIFT, // O + 0x13|SHIFT, // P + 0x14|SHIFT, // Q + 0x15|SHIFT, // R + 0x16|SHIFT, // S + 0x17|SHIFT, // T + 0x18|SHIFT, // U + 0x19|SHIFT, // V + 0x1a|SHIFT, // W + 0x1b|SHIFT, // X + 0x1c|SHIFT, // Y + 0x1d|SHIFT, // Z + 0x2f, // [ + 0x31, // bslash + 0x30, // ] + 0x23|SHIFT, // ^ + 0x2d|SHIFT, // _ + 0x35, // ` + 0x04, // a + 0x05, // b + 0x06, // c + 0x07, // d + 0x08, // e + 0x09, // f + 0x0a, // g + 0x0b, // h + 0x0c, // i + 0x0d, // j + 0x0e, // k + 0x0f, // l + 0x10, // m + 0x11, // n + 0x12, // o + 0x13, // p + 0x14, // q + 0x15, // r + 0x16, // s + 0x17, // t + 0x18, // u + 0x19, // v + 0x1a, // w + 0x1b, // x + 0x1c, // y + 0x1d, // z + 0x2f|SHIFT, // + 0x31|SHIFT, // | + 0x30|SHIFT, // } + 0x35|SHIFT, // ~ + 0 // DEL +}; + +uint8_t USBPutChar(uint8_t c); + +// press() adds the specified key (printing, non-printing, or modifier) +// to the persistent key report and sends the report. Because of the way +// USB HID works, the host acts like the key remains pressed until we +// call release(), releaseAll(), or otherwise clear the report and resend. +size_t Keyboard_::press(uint8_t k) +{ + uint8_t i; + if (k >= 136) { // it's a non-printing key (not a modifier) + k = k - 136; + } else if (k >= 128) { // it's a modifier key + _keyReport.modifiers |= (1<<(k-128)); + k = 0; + } else { // it's a printing key + k = _asciimap[k]; + if (!k) { + setWriteError(); + return 0; + } + if (k & 0x80) { // it's a capital letter or other character reached with shift + _keyReport.modifiers |= 0x02; // the left shift modifier + k &= 0x7F; + } + } + + // Add k to the key report only if it's not already present + // and if there is an empty slot. + if (_keyReport.keys[0] != k && _keyReport.keys[1] != k && + _keyReport.keys[2] != k && _keyReport.keys[3] != k && + _keyReport.keys[4] != k && _keyReport.keys[5] != k) { + + for (i=0; i<6; i++) { + if (_keyReport.keys[i] == 0x00) { + _keyReport.keys[i] = k; + break; + } + } + if (i == 6) { + setWriteError(); + return 0; + } + } + sendReport(&_keyReport); + return 1; +} + +// release() takes the specified key out of the persistent key report and +// sends the report. This tells the OS the key is no longer pressed and that +// it shouldn't be repeated any more. +size_t Keyboard_::release(uint8_t k) +{ + uint8_t i; + if (k >= 136) { // it's a non-printing key (not a modifier) + k = k - 136; + } else if (k >= 128) { // it's a modifier key + _keyReport.modifiers &= ~(1<<(k-128)); + k = 0; + } else { // it's a printing key + k = _asciimap[k]; + if (!k) { + return 0; + } + if (k & 0x80) { // it's a capital letter or other character reached with shift + _keyReport.modifiers &= ~(0x02); // the left shift modifier + k &= 0x7F; + } + } + + // Test the key report to see if k is present. Clear it if it exists. + // Check all positions in case the key is present more than once (which it shouldn't be) + for (i=0; i<6; i++) { + if (0 != k && _keyReport.keys[i] == k) { + _keyReport.keys[i] = 0x00; + } + } + + sendReport(&_keyReport); + return 1; +} + +void Keyboard_::releaseAll(void) +{ + _keyReport.keys[0] = 0; + _keyReport.keys[1] = 0; + _keyReport.keys[2] = 0; + _keyReport.keys[3] = 0; + _keyReport.keys[4] = 0; + _keyReport.keys[5] = 0; + _keyReport.modifiers = 0; + sendReport(&_keyReport); +} + +size_t Keyboard_::write(uint8_t c) +{ + uint8_t p = 0; + + p = press(c); // Keydown + release(c); // Keyup + + return (p); // Just return the result of press() since release() almost always returns 1 +} + +#endif diff --git a/hardware/digistump/sam/cores/digix/USB/USBAPI.h b/hardware/digistump/sam/cores/digix/USB/USBAPI.h new file mode 100644 index 0000000..e024ec5 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/USB/USBAPI.h @@ -0,0 +1,222 @@ +/* + Copyright (c) 2012 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef __USBAPI__ +#define __USBAPI__ + +#if defined __cplusplus + +#include "RingBuffer.h" + +//================================================================================ +//================================================================================ +// USB + +class USBDevice_ +{ +public: + USBDevice_(); + bool configured(); + + bool attach(); + bool detach(); // Serial port goes down too... + void poll(); +}; +extern USBDevice_ USBDevice; + +//================================================================================ +//================================================================================ +// Serial over CDC (Serial1 is the physical port) + +class Serial_ : public Stream +{ +private: + RingBuffer *_cdc_rx_buffer; +public: + void begin(uint32_t baud_count); + void begin(uint32_t baud_count, uint8_t config); + void end(void); + + virtual int available(void); + virtual void accept(void); + virtual int peek(void); + virtual int read(void); + virtual void flush(void); + virtual size_t write(uint8_t); + virtual size_t write(const uint8_t *buffer, size_t size); + using Print::write; // pull in write(str) from Print + operator bool(); +}; +extern Serial_ SerialUSB; +extern Serial_ Serial; + +//================================================================================ +//================================================================================ +// Mouse + +#define MOUSE_LEFT 1 +#define MOUSE_RIGHT 2 +#define MOUSE_MIDDLE 4 +#define MOUSE_ALL (MOUSE_LEFT | MOUSE_RIGHT | MOUSE_MIDDLE) + +class Mouse_ +{ +private: + uint8_t _buttons; + void buttons(uint8_t b); +public: + Mouse_(void); + void begin(void); + void end(void); + void click(uint8_t b = MOUSE_LEFT); + void move(signed char x, signed char y, signed char wheel = 0); + void press(uint8_t b = MOUSE_LEFT); // press LEFT by default + void release(uint8_t b = MOUSE_LEFT); // release LEFT by default + bool isPressed(uint8_t b = MOUSE_ALL); // check all buttons by default +}; +extern Mouse_ Mouse; + +//================================================================================ +//================================================================================ +// Keyboard + +#define KEY_LEFT_CTRL 0x80 +#define KEY_LEFT_SHIFT 0x81 +#define KEY_LEFT_ALT 0x82 +#define KEY_LEFT_GUI 0x83 +#define KEY_RIGHT_CTRL 0x84 +#define KEY_RIGHT_SHIFT 0x85 +#define KEY_RIGHT_ALT 0x86 +#define KEY_RIGHT_GUI 0x87 + +#define KEY_UP_ARROW 0xDA +#define KEY_DOWN_ARROW 0xD9 +#define KEY_LEFT_ARROW 0xD8 +#define KEY_RIGHT_ARROW 0xD7 +#define KEY_BACKSPACE 0xB2 +#define KEY_TAB 0xB3 +#define KEY_RETURN 0xB0 +#define KEY_ESC 0xB1 +#define KEY_INSERT 0xD1 +#define KEY_DELETE 0xD4 +#define KEY_PAGE_UP 0xD3 +#define KEY_PAGE_DOWN 0xD6 +#define KEY_HOME 0xD2 +#define KEY_END 0xD5 +#define KEY_CAPS_LOCK 0xC1 +#define KEY_F1 0xC2 +#define KEY_F2 0xC3 +#define KEY_F3 0xC4 +#define KEY_F4 0xC5 +#define KEY_F5 0xC6 +#define KEY_F6 0xC7 +#define KEY_F7 0xC8 +#define KEY_F8 0xC9 +#define KEY_F9 0xCA +#define KEY_F10 0xCB +#define KEY_F11 0xCC +#define KEY_F12 0xCD + +// Low level key report: up to 6 keys and shift, ctrl etc at once +typedef struct +{ + uint8_t modifiers; + uint8_t reserved; + uint8_t keys[6]; +} KeyReport; + +class Keyboard_ : public Print +{ +private: + KeyReport _keyReport; + void sendReport(KeyReport* keys); +public: + Keyboard_(void); + void begin(void); + void end(void); + virtual size_t write(uint8_t k); + virtual size_t press(uint8_t k); + virtual size_t release(uint8_t k); + virtual void releaseAll(void); +}; +extern Keyboard_ Keyboard; + +//================================================================================ +//================================================================================ +// Low level API + +typedef struct +{ + uint8_t bmRequestType; + uint8_t bRequest; + uint8_t wValueL; + uint8_t wValueH; + uint16_t wIndex; + uint16_t wLength; +} Setup; + +//================================================================================ +//================================================================================ +// HID 'Driver' + +int HID_GetInterface(uint8_t* interfaceNum); +int HID_GetDescriptor(int i); +bool HID_Setup(Setup& setup); +void HID_SendReport(uint8_t id, const void* data, uint32_t len); + +//================================================================================ +//================================================================================ +// MSC 'Driver' + +int MSC_GetInterface(uint8_t* interfaceNum); +int MSC_GetDescriptor(int i); +bool MSC_Setup(Setup& setup); +bool MSC_Data(uint8_t rx,uint8_t tx); + +//================================================================================ +//================================================================================ +// CSC 'Driver' + +int CDC_GetInterface(uint8_t* interfaceNum); +int CDC_GetOtherInterface(uint8_t* interfaceNum); +int CDC_GetDescriptor(int i); +bool CDC_Setup(Setup& setup); + +//================================================================================ +//================================================================================ + +#define TRANSFER_RELEASE 0x40 +#define TRANSFER_ZERO 0x20 + +void USBD_InitControl(int end); +int USBD_SendControl(uint8_t flags, const void* d, uint32_t len); +int USBD_RecvControl(void* d, uint32_t len); +int USBD_SendInterfaces(void); +bool USBD_ClassInterfaceRequest(Setup& setup); + + +uint32_t USBD_Available(uint32_t ep); +uint32_t USBD_SendSpace(uint32_t ep); +uint32_t USBD_Send(uint32_t ep, const void* d, uint32_t len); +uint32_t USBD_Recv(uint32_t ep, void* data, uint32_t len); // non-blocking +uint32_t USBD_Recv(uint32_t ep); // non-blocking +void USBD_Flush(uint32_t ep); +uint32_t USBD_Connected(void); + +#endif +#endif diff --git a/hardware/digistump/sam/cores/digix/USB/USBCore.cpp b/hardware/digistump/sam/cores/digix/USB/USBCore.cpp new file mode 100644 index 0000000..e881169 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/USB/USBCore.cpp @@ -0,0 +1,882 @@ +// Copyright (c) 2010, Peter Barrett +/* +** Permission to use, copy, modify, and/or distribute this software for +** any purpose with or without fee is hereby granted, provided that the +** above copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL +** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR +** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES +** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +** SOFTWARE. +*/ + +#include "Arduino.h" +#include "USBAPI.h" +#include "Reset.h" +#include + +//#define TRACE_CORE(x) x +#define TRACE_CORE(x) + +static const uint32_t EndPoints[] = +{ + EP_TYPE_CONTROL, + +#ifdef CDC_ENABLED + EP_TYPE_INTERRUPT_IN, // CDC_ENDPOINT_ACM + EP_TYPE_BULK_OUT, // CDC_ENDPOINT_OUT + EP_TYPE_BULK_IN, // CDC_ENDPOINT_IN +#endif + +#ifdef HID_ENABLED + EP_TYPE_INTERRUPT_IN_HID // HID_ENDPOINT_INT +#endif +}; + +/** Pulse generation counters to keep track of the number of milliseconds remaining for each pulse type */ +#define TX_RX_LED_PULSE_MS 100 +volatile uint8_t TxLEDPulse; /**< Milliseconds remaining for data Tx LED pulse */ +volatile uint8_t RxLEDPulse; /**< Milliseconds remaining for data Rx LED pulse */ +static char isRemoteWakeUpEnabled = 0; +static char isEndpointHalt = 0; +//================================================================== +//================================================================== + +extern const uint16_t STRING_LANGUAGE[]; +extern const uint8_t STRING_PRODUCT[]; +extern const uint8_t STRING_MANUFACTURER[]; +extern const DeviceDescriptor USB_DeviceDescriptor; +extern const DeviceDescriptor USB_DeviceDescriptorA; + +const uint16_t STRING_LANGUAGE[2] = { + (3<<8) | (2+2), + 0x0409 // English +}; + +#ifndef USB_PRODUCT +// Use a hardcoded product name if none is provided +#if USB_PID == USB_PID_DUE +#define USB_PRODUCT "Arduino Due" +#elif USB_PID == USB_PID_DIGIX +#define USB_PRODUCT "Digistump DigiX" +#else +#define USB_PRODUCT "USB IO Board" +#endif +#endif + +const uint8_t STRING_PRODUCT[] = USB_PRODUCT; + + +#define USB_MANUFACTURER "Digistump" + + +const uint8_t STRING_MANUFACTURER[12] = USB_MANUFACTURER; + +#ifdef CDC_ENABLED +#define DEVICE_CLASS 0x02 +#else +#define DEVICE_CLASS 0x00 +#endif + +// DEVICE DESCRIPTOR +const DeviceDescriptor USB_DeviceDescriptor = + D_DEVICE(0x00,0x00,0x00,64,USB_VID_DIGIX,USB_PID,0x100,IMANUFACTURER,IPRODUCT,0,1); + +const DeviceDescriptor USB_DeviceDescriptorA = + D_DEVICE(DEVICE_CLASS,0x00,0x00,64,USB_VID_DIGIX,USB_PID,0x100,IMANUFACTURER,IPRODUCT,0,1); + +const DeviceDescriptor USB_DeviceQualifier = + D_QUALIFIER(0x00,0x00,0x00,64,1); + +//! 7.1.20 Test Mode Support +static const unsigned char test_packet_buffer[] = { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // JKJKJKJK * 9 + 0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, // JJKKJJKK * 8 + 0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, // JJJJKKKK * 8 + 0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, // JJJJJJJKKKKKKK * 8 + 0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD, // JJJJJJJK * 8 + 0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E // {JKKKKKKK * 10}, JK +}; + +//================================================================== +//================================================================== + +volatile uint32_t _usbConfiguration = 0; +volatile uint32_t _usbInitialized = 0; +uint32_t _usbSetInterface = 0; +uint32_t _cdcComposite = 0; + +//================================================================== +//================================================================== + +#define USB_RECV_TIMEOUT +class LockEP +{ + irqflags_t flags; +public: + LockEP(uint32_t ep) : flags(cpu_irq_save()) + { + } + ~LockEP() + { + cpu_irq_restore(flags); + } +}; + +// Number of bytes, assumes a rx endpoint +uint32_t USBD_Available(uint32_t ep) +{ + LockEP lock(ep); + return UDD_FifoByteCount(ep & 0xF); +} + +// Non Blocking receive +// Return number of bytes read +uint32_t USBD_Recv(uint32_t ep, void* d, uint32_t len) +{ + if (!_usbConfiguration || len < 0) + return -1; + + LockEP lock(ep); + uint32_t n = UDD_FifoByteCount(ep & 0xF); + len = min(n,len); + n = len; + uint8_t* dst = (uint8_t*)d; + while (n--) + *dst++ = UDD_Recv8(ep & 0xF); + if (len && !UDD_FifoByteCount(ep & 0xF)) // release empty buffer + UDD_ReleaseRX(ep & 0xF); + + return len; +} + +// Recv 1 byte if ready +uint32_t USBD_Recv(uint32_t ep) +{ + uint8_t c; + if (USBD_Recv(ep & 0xF, &c, 1) != 1) + return -1; + else + return c; +} + +// Space in send EP +//uint32_t USBD_SendSpace(uint32_t ep) +//{ + //LockEP lock(ep); +//// if (!UDD_ReadWriteAllowed(ep & 0xF)) + ////{ + ////printf("pb "); // UOTGHS->UOTGHS_DEVEPTISR[%d]=0x%X\n\r", ep, UOTGHS->UOTGHS_DEVEPTISR[ep]); + ////return 0; + ////} + + //if(ep==0) return 64 - UDD_FifoByteCount(ep & 0xF); // EP0_SIZE jcb + //else return 512 - UDD_FifoByteCount(ep & 0xF); // EPX_SIZE jcb +//} + +// Blocking Send of data to an endpoint +uint32_t USBD_Send(uint32_t ep, const void* d, uint32_t len) +{ + uint32_t n; + int r = len; + const uint8_t* data = (const uint8_t*)d; + + if (!_usbConfiguration) + { + TRACE_CORE(printf("pb conf\n\r");) + return -1; + } + + while (len) + { + if(ep==0) n = EP0_SIZE; + else n = EPX_SIZE; + if (n > len) + n = len; + len -= n; + + UDD_Send(ep & 0xF, data, n); + data += n; + } + //TXLED1; // light the TX LED + //TxLEDPulse = TX_RX_LED_PULSE_MS; + return r; +} + +int _cmark; +int _cend; + +void USBD_InitControl(int end) +{ + _cmark = 0; + _cend = end; +} + +// Clipped by _cmark/_cend +int USBD_SendControl(uint8_t flags, const void* d, uint32_t len) +{ + const uint8_t* data = (const uint8_t*)d; + uint32_t length = len; + uint32_t sent = 0; + uint32_t pos = 0; + + TRACE_CORE(printf("=> USBD_SendControl TOTAL len=%lu\r\n", len);) + + if (_cmark < _cend) + { + while (len > 0) + { + sent = UDD_Send(EP0, data + pos, len); + TRACE_CORE(printf("=> USBD_SendControl sent=%lu\r\n", sent);) + pos += sent; + len -= sent; + } + } + + _cmark += length; + + return length; +} + +// Send a USB descriptor string. The string is stored as a +// plain ASCII string but is sent out as UTF-16 with the +// correct 2-byte prefix +static bool USB_SendStringDescriptor(const uint8_t *string, int wLength) { + uint16_t buff[64]; + int l = 1; + wLength-=2; + while (*string && wLength>0) { + buff[l++] = (uint8_t)(*string++); + wLength-=2; + } + buff[0] = (3<<8) | (l*2); + return USBD_SendControl(0, (uint8_t*)buff, l*2); +} + +// Does not timeout or cross fifo boundaries +// Will only work for transfers <= 64 bytes +// TODO +int USBD_RecvControl(void* d, uint32_t len) +{ + UDD_WaitOUT(); + UDD_Recv(EP0, (uint8_t*)d, len); + UDD_ClearOUT(); + + return len; +} + +// Handle CLASS_INTERFACE requests +bool USBD_ClassInterfaceRequest(Setup& setup) +{ + uint8_t i = setup.wIndex; + + TRACE_CORE(printf("=> USBD_ClassInterfaceRequest\r\n");) + +#ifdef CDC_ENABLED + if (CDC_ACM_INTERFACE == i) + { + return CDC_Setup(setup); + } +#endif + +#ifdef HID_ENABLED + if (HID_INTERFACE == i) + { + return HID_Setup(setup); + } +#endif + + return false; +} + +int USBD_SendInterfaces(void) +{ + int total = 0; + uint8_t interfaces = 0; + +#ifdef CDC_ENABLED + total = CDC_GetInterface(&interfaces); +#endif + +#ifdef HID_ENABLED + total += HID_GetInterface(&interfaces); +#endif + + total = total; // Get rid of compiler warning + TRACE_CORE(printf("=> USBD_SendInterfaces, total=%d interfaces=%d\r\n", total, interfaces);) + return interfaces; +} + +int USBD_SendOtherInterfaces(void) +{ + int total = 0; + uint8_t interfaces = 0; + +#ifdef CDC_ENABLED + total = CDC_GetOtherInterface(&interfaces); +#endif + +#ifdef HID_ENABLED + total += HID_GetInterface(&interfaces); +#endif + + total = total; // Get rid of compiler warning + TRACE_CORE(printf("=> USBD_SendInterfaces, total=%d interfaces=%d\r\n", total, interfaces);) + return interfaces; +} + +// Construct a dynamic configuration descriptor +// This really needs dynamic endpoint allocation etc +// TODO +static bool USBD_SendConfiguration(int maxlen) +{ + // Count and measure interfaces + USBD_InitControl(0); + //TRACE_CORE(printf("=> USBD_SendConfiguration _cmark1=%d\r\n", _cmark);) + int interfaces = USBD_SendInterfaces(); + //TRACE_CORE(printf("=> USBD_SendConfiguration _cmark2=%d\r\n", _cmark);) + //TRACE_CORE(printf("=> USBD_SendConfiguration sizeof=%d\r\n", sizeof(ConfigDescriptor));) + +_Pragma("pack(1)") + ConfigDescriptor config = D_CONFIG(_cmark + sizeof(ConfigDescriptor),interfaces); +_Pragma("pack()") + //TRACE_CORE(printf("=> USBD_SendConfiguration clen=%d\r\n", config.clen);) + + //TRACE_CORE(printf("=> USBD_SendConfiguration maxlen=%d\r\n", maxlen);) + + // Now send them + USBD_InitControl(maxlen); + USBD_SendControl(0,&config,sizeof(ConfigDescriptor)); + USBD_SendInterfaces(); + return true; +} + +static bool USBD_SendOtherConfiguration(int maxlen) +{ + // Count and measure interfaces + USBD_InitControl(0); + //TRACE_CORE(printf("=> USBD_SendConfiguration _cmark1=%d\r\n", _cmark);) + int interfaces = USBD_SendOtherInterfaces(); + //TRACE_CORE(printf("=> USBD_SendConfiguration _cmark2=%d\r\n", _cmark);) + //TRACE_CORE(printf("=> USBD_SendConfiguration sizeof=%d\r\n", sizeof(ConfigDescriptor));) + +_Pragma("pack(1)") + ConfigDescriptor config = D_OTHERCONFIG(_cmark + sizeof(ConfigDescriptor),interfaces); +_Pragma("pack()") + //TRACE_CORE(printf("=> USBD_SendConfiguration clen=%d\r\n", config.clen);) + + //TRACE_CORE(printf("=> USBD_SendConfiguration maxlen=%d\r\n", maxlen);) + + // Now send them + USBD_InitControl(maxlen); + USBD_SendControl(0,&config,sizeof(ConfigDescriptor)); + USBD_SendOtherInterfaces(); + return true; +} + +static bool USBD_SendDescriptor(Setup& setup) +{ + uint8_t t = setup.wValueH; + uint8_t desc_length = 0; + const uint8_t* desc_addr = 0; + + if (USB_CONFIGURATION_DESCRIPTOR_TYPE == t) + { + TRACE_CORE(printf("=> USBD_SendDescriptor : USB_CONFIGURATION_DESCRIPTOR_TYPE length=%d\r\n", setup.wLength);) + return USBD_SendConfiguration(setup.wLength); + } + + USBD_InitControl(setup.wLength); +#ifdef HID_ENABLED + if (HID_REPORT_DESCRIPTOR_TYPE == t) + { + TRACE_CORE(puts("=> USBD_SendDescriptor : HID_REPORT_DESCRIPTOR_TYPE\r\n");) + return HID_GetDescriptor(t); + } +#endif + + if (USB_DEVICE_DESCRIPTOR_TYPE == t) + { + TRACE_CORE(puts("=> USBD_SendDescriptor : USB_DEVICE_DESCRIPTOR_TYPE\r\n");) + if (setup.wLength == 8) + { + _cdcComposite = 1; + } + desc_addr = _cdcComposite ? (const uint8_t*)&USB_DeviceDescriptorA : (const uint8_t*)&USB_DeviceDescriptor; + if( *desc_addr > setup.wLength ) { + desc_length = setup.wLength; + } + } + else if (USB_STRING_DESCRIPTOR_TYPE == t) + { + TRACE_CORE(puts("=> USBD_SendDescriptor : USB_STRING_DESCRIPTOR_TYPE\r\n");) + if (setup.wValueL == 0) { + desc_addr = (const uint8_t*)&STRING_LANGUAGE; + } + else if (setup.wValueL == IPRODUCT) { + return USB_SendStringDescriptor(STRING_PRODUCT, setup.wLength); + } + else if (setup.wValueL == IMANUFACTURER) { + return USB_SendStringDescriptor(STRING_MANUFACTURER, setup.wLength); + } + else { + return false; + } + if( *desc_addr > setup.wLength ) { + desc_length = setup.wLength; + } + } + else if (USB_DEVICE_QUALIFIER == t) + { + // Device qualifier descriptor requested + desc_addr = (const uint8_t*)&USB_DeviceQualifier; + if( *desc_addr > setup.wLength ) { + desc_length = setup.wLength; + } + } + else if (USB_OTHER_SPEED_CONFIGURATION == t) + { + // Other configuration descriptor requested + return USBD_SendOtherConfiguration(setup.wLength); + } + else + { + //printf("Device ERROR"); + } + + if (desc_addr == 0) + { + return false; + } + + if (desc_length == 0) + { + desc_length = *desc_addr; + } + + TRACE_CORE(printf("=> USBD_SendDescriptor : desc_addr=%p desc_length=%d\r\n", desc_addr, desc_length);) + USBD_SendControl(0, desc_addr, desc_length); + + return true; +} + + +static void USB_SendZlp( void ) +{ + while( UOTGHS_DEVEPTISR_TXINI != (UOTGHS->UOTGHS_DEVEPTISR[0] & UOTGHS_DEVEPTISR_TXINI ) ) + { + if((UOTGHS->UOTGHS_DEVISR & UOTGHS_DEVISR_SUSP) == UOTGHS_DEVISR_SUSP) + { + return; + } + } + UOTGHS->UOTGHS_DEVEPTICR[0] = UOTGHS_DEVEPTICR_TXINIC; +} + + +static void Test_Mode_Support( uint8_t wIndex ) +{ + uint8_t i; + uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(2); + + switch( wIndex ) + { + case 4: + //Test mode Test_Packet: + //Upon command, a port must repetitively transmit the following test packet until + //the exit action is taken. This enables the testing of rise and fall times, eye + //patterns, jitter, and any other dynamic waveform specifications. + //The test packet is made up by concatenating the following strings. + //(Note: For J/K NRZI data, and for NRZ data, the bit on the left is the first one + //transmitted. "S" indicates that a bit stuff occurs, which inserts an "extra" NRZI data bit. + //"* N" is used to indicate N occurrences of a string of bits or symbols.) + //A port in Test_Packet mode must send this packet repetitively. The inter-packet timing + //must be no less than the minimum allowable inter-packet gap as defined in Section 7.1.18 and + //no greater than 125 us. + + // Send ZLP + USB_SendZlp(); + + UOTGHS->UOTGHS_DEVDMA[0].UOTGHS_DEVDMACONTROL = 0; // raz + UOTGHS->UOTGHS_DEVDMA[1].UOTGHS_DEVDMACONTROL = 0; // raz + + // Configure endpoint 2, 64 bytes, direction IN, type BULK, 1 bank + UOTGHS->UOTGHS_DEVEPTCFG[2] = UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE + | UOTGHS_DEVEPTCFG_EPDIR_IN + | UOTGHS_DEVEPTCFG_EPTYPE_BLK + | UOTGHS_DEVEPTCFG_EPBK_1_BANK; + // Check if the configuration is ok + UOTGHS->UOTGHS_DEVEPTCFG[2] |= UOTGHS_DEVEPTCFG_ALLOC; + while((UOTGHS->UOTGHS_DEVEPTISR[2]&UOTGHS_DEVEPTISR_CFGOK)==0) {} + UOTGHS->UOTGHS_DEVEPT |= UOTGHS_DEVEPT_EPEN2; + // Write FIFO + for( i=0; iUOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_TSTPCKT; + // Send packet + UOTGHS->UOTGHS_DEVEPTICR[2] = UOTGHS_DEVEPTICR_TXINIC; + UOTGHS->UOTGHS_DEVEPTIDR[2] = UOTGHS_DEVEPTIDR_FIFOCONC; + for(;;); +// break; + + case 1: + //Test mode Test_J: + //Upon command, a port's transceiver must enter the high-speed J state and remain in that + //state until the exit action is taken. This enables the testing of the high output drive + //level on the D+ line. + // Send a ZLP + USB_SendZlp(); + UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_TSTJ; + for(;;); +// break; + + case 2: + //Test mode Test_K: + //Upon command, a port's transceiver must enter the high-speed K state and remain in + //that state until the exit action is taken. This enables the testing of the high output drive + //level on the D- line. + // Send a ZLP + USB_SendZlp(); + UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_TSTK; + for(;;); +// break; + + case 3: + //Test mode Test_SE0_NAK: + //Upon command, a port's transceiver must enter the high-speed receive mode + //and remain in that mode until the exit action is taken. This enables the testing + //of output impedance, low level output voltage, and loading characteristics. + //In addition, while in this mode, upstream facing ports (and only upstream facing ports) + //must respond to any IN token packet with a NAK handshake (only if the packet CRC is + //determined to be correct) within the normal allowed device response time. This enables testing of + //the device squelch level circuitry and, additionally, provides a general purpose stimulus/response + //test for basic functional testing. + + // Send a ZLP + USB_SendZlp(); + UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_SUSPEC + | UOTGHS_DEVIDR_MSOFEC + | UOTGHS_DEVIDR_SOFEC + | UOTGHS_DEVIDR_EORSTEC + | UOTGHS_DEVIDR_WAKEUPEC + | UOTGHS_DEVIDR_EORSMEC + | UOTGHS_DEVIDR_UPRSMEC + | UOTGHS_DEVIDR_PEP_0 + | UOTGHS_DEVIDR_PEP_1 + | UOTGHS_DEVIDR_PEP_2 + | UOTGHS_DEVIDR_PEP_3 + | UOTGHS_DEVIDR_PEP_4 + | UOTGHS_DEVIDR_PEP_5 + | UOTGHS_DEVIDR_PEP_6 + | UOTGHS_DEVIDR_DMA_1 + | UOTGHS_DEVIDR_DMA_2 + | UOTGHS_DEVIDR_DMA_3 + | UOTGHS_DEVIDR_DMA_4 + | UOTGHS_DEVIDR_DMA_5 + | UOTGHS_DEVIDR_DMA_6; + for(;;); +// break; + } +} + + +//unsigned int iii=0; +// Endpoint 0 interrupt +static void USB_ISR(void) +{ +// printf("ISR=0x%X\n\r", UOTGHS->UOTGHS_DEVISR); // jcb +// if( iii++ > 1500 ) while(1); // jcb + // End of bus reset + if (Is_udd_reset()) + { + TRACE_CORE(printf(">>> End of Reset\r\n");) + + // Reset USB address to 0 + udd_configure_address(0); + udd_enable_address(); + + // Configure EP 0 + UDD_InitEP(0, EP_TYPE_CONTROL); + udd_enable_setup_received_interrupt(0); + udd_enable_endpoint_interrupt(0); + + _usbConfiguration = 0; + udd_ack_reset(); + } + +#ifdef CDC_ENABLED + if (Is_udd_endpoint_interrupt(CDC_RX)) + { + udd_ack_out_received(CDC_RX); + + // Handle received bytes + if (USBD_Available(CDC_RX)) + SerialUSB.accept(); + } + + if (Is_udd_sof()) + { + udd_ack_sof(); + // USBD_Flush(CDC_TX); // jcb + } +#endif + + // EP 0 Interrupt + if (Is_udd_endpoint_interrupt(0) ) + { + if (!UDD_ReceivedSetupInt()) + { + return; + } + + Setup setup; + UDD_Recv(EP0, (uint8_t*)&setup, 8); + UDD_ClearSetupInt(); + + uint8_t requestType = setup.bmRequestType; + if (requestType & REQUEST_DEVICETOHOST) + { + TRACE_CORE(puts(">>> EP0 Int: IN Request\r\n");) + UDD_WaitIN(); + } + else + { + TRACE_CORE(puts(">>> EP0 Int: OUT Request\r\n");) + UDD_ClearIN(); + } + + bool ok = true; + if (REQUEST_STANDARD == (requestType & REQUEST_TYPE)) + { + // Standard Requests + uint8_t r = setup.bRequest; + if (GET_STATUS == r) + { + if( setup.bmRequestType == 0 ) // device + { + // Send the device status + TRACE_CORE(puts(">>> EP0 Int: GET_STATUS\r\n");) + // Check current configuration for power mode (if device is configured) + // TODO + // Check if remote wake-up is enabled + // TODO + UDD_Send8(EP0, 0); // TODO + UDD_Send8(EP0, 0); + } + // if( setup.bmRequestType == 2 ) // Endpoint: + else + { + // Send the endpoint status + // Check if the endpoint if currently halted + if( isEndpointHalt == 1 ) + UDD_Send8(EP0, 1); // TODO + else + UDD_Send8(EP0, 0); // TODO + UDD_Send8(EP0, 0); + } + } + else if (CLEAR_FEATURE == r) + { + // Check which is the selected feature + if( setup.wValueL == 1) // DEVICEREMOTEWAKEUP + { + // Enable remote wake-up and send a ZLP + if( isRemoteWakeUpEnabled == 1 ) + UDD_Send8(EP0, 1); + else + UDD_Send8(EP0, 0); + UDD_Send8(EP0, 0); + } + else // if( setup.wValueL == 0) // ENDPOINTHALT + { + isEndpointHalt = 0; // TODO + UDD_Send8(EP0, 0); + UDD_Send8(EP0, 0); + } + + } + else if (SET_FEATURE == r) + { + // Check which is the selected feature + if( setup.wValueL == 1) // DEVICEREMOTEWAKEUP + { + // Enable remote wake-up and send a ZLP + isRemoteWakeUpEnabled = 1; + UDD_Send8(EP0, 0); + } + if( setup.wValueL == 0) // ENDPOINTHALT + { + // Halt endpoint + isEndpointHalt = 1; + //USBD_Halt(USBGenericRequest_GetEndpointNumber(pRequest)); + UDD_Send8(EP0, 0); + } + if( setup.wValueL == 2) // TEST_MODE + { + // 7.1.20 Test Mode Support, 9.4.9 SetFeature + if( (setup.bmRequestType == 0 /*USBGenericRequest_DEVICE*/) && + ((setup.wIndex & 0x000F) == 0) ) + { + // the lower byte of wIndex must be zero + // the most significant byte of wIndex is used to specify the specific test mode + + UOTGHS->UOTGHS_DEVIDR &= ~UOTGHS_DEVIDR_SUSPEC; + UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED; // remove suspend ? + + Test_Mode_Support( (setup.wIndex & 0xFF00)>>8 ); + } + } + } + else if (SET_ADDRESS == r) + { + TRACE_CORE(puts(">>> EP0 Int: SET_ADDRESS\r\n");) + UDD_WaitIN(); + UDD_SetAddress(setup.wValueL); + } + else if (GET_DESCRIPTOR == r) + { + TRACE_CORE(puts(">>> EP0 Int: GET_DESCRIPTOR\r\n");) + ok = USBD_SendDescriptor(setup); + } + else if (SET_DESCRIPTOR == r) + { + TRACE_CORE(puts(">>> EP0 Int: SET_DESCRIPTOR\r\n");) + ok = false; + } + else if (GET_CONFIGURATION == r) + { + TRACE_CORE(puts(">>> EP0 Int: GET_CONFIGURATION\r\n");) + UDD_Send8(EP0, _usbConfiguration); + } + else if (SET_CONFIGURATION == r) + { + if (REQUEST_DEVICE == (requestType & REQUEST_RECIPIENT)) + { + TRACE_CORE(printf(">>> EP0 Int: SET_CONFIGURATION REQUEST_DEVICE %d\r\n", setup.wValueL);) + + UDD_InitEndpoints(EndPoints, (sizeof(EndPoints) / sizeof(EndPoints[0]))); + _usbConfiguration = setup.wValueL; + +#ifdef CDC_ENABLED + // Enable interrupt for CDC reception from host (OUT packet) + udd_enable_out_received_interrupt(CDC_RX); + udd_enable_endpoint_interrupt(CDC_RX); +#endif + } + else + { + TRACE_CORE(puts(">>> EP0 Int: SET_CONFIGURATION failed!\r\n");) + ok = false; + } + } + else if (GET_INTERFACE == r) + { + TRACE_CORE(puts(">>> EP0 Int: GET_INTERFACE\r\n");) + UDD_Send8(EP0, _usbSetInterface); + } + else if (SET_INTERFACE == r) + { + _usbSetInterface = setup.wValueL; + TRACE_CORE(puts(">>> EP0 Int: SET_INTERFACE\r\n");) + } + } + else + { + TRACE_CORE(puts(">>> EP0 Int: ClassInterfaceRequest\r\n");) + + UDD_WaitIN(); // Workaround: need tempo here, else CDC serial won't open correctly + + USBD_InitControl(setup.wLength); // Max length of transfer + ok = USBD_ClassInterfaceRequest(setup); + } + + if (ok) + { + TRACE_CORE(puts(">>> EP0 Int: Send packet\r\n");) + UDD_ClearIN(); + } + else + { + TRACE_CORE(puts(">>> EP0 Int: Stall\r\n");) + UDD_Stall(); + } + } +} + +void USBD_Flush(uint32_t ep) +{ + if (UDD_FifoByteCount(ep)) + UDD_ReleaseTX(ep); +} + +// VBUS or counting frames +// Any frame counting? +uint32_t USBD_Connected(void) +{ + uint8_t f = UDD_GetFrameNumber(); + + delay(3); + + return f != UDD_GetFrameNumber(); +} + + +//======================================================================= +//======================================================================= + +USBDevice_ USBDevice; + +USBDevice_::USBDevice_() +{ + UDD_SetStack(&USB_ISR); + + if (UDD_Init() == 0UL) + { + _usbInitialized=1UL; + } +} + +bool USBDevice_::attach(void) +{ + if (_usbInitialized != 0UL) + { + UDD_Attach(); + _usbConfiguration = 0; + return true; + } + else + { + return false; + } +} + +bool USBDevice_::detach(void) +{ + if (_usbInitialized != 0UL) + { + UDD_Detach(); + return true; + } + else + { + return false; + } +} + +// Check for interrupts +// TODO: VBUS detection +bool USBDevice_::configured() +{ + return _usbConfiguration; +} + +void USBDevice_::poll() +{ +} diff --git a/hardware/digistump/sam/cores/digix/USB/USBCore.h b/hardware/digistump/sam/cores/digix/USB/USBCore.h new file mode 100644 index 0000000..b01d757 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/USB/USBCore.h @@ -0,0 +1,311 @@ +// Copyright (c) 2010, Peter Barrett +/* +** Permission to use, copy, modify, and/or distribute this software for +** any purpose with or without fee is hereby granted, provided that the +** above copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL +** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR +** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES +** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +** SOFTWARE. +*/ + +#ifndef __USBCORE_H__ +#define __USBCORE_H__ + +// Standard requests +#define GET_STATUS 0 +#define CLEAR_FEATURE 1 +#define SET_FEATURE 3 +#define SET_ADDRESS 5 +#define GET_DESCRIPTOR 6 +#define SET_DESCRIPTOR 7 +#define GET_CONFIGURATION 8 +#define SET_CONFIGURATION 9 +#define GET_INTERFACE 10 +#define SET_INTERFACE 11 + + +// bmRequestType +#define REQUEST_HOSTTODEVICE 0x00 +#define REQUEST_DEVICETOHOST 0x80 +#define REQUEST_DIRECTION 0x80 + +#define REQUEST_STANDARD 0x00 +#define REQUEST_CLASS 0x20 +#define REQUEST_VENDOR 0x40 +#define REQUEST_TYPE 0x60 + +#define REQUEST_DEVICE 0x00 +#define REQUEST_INTERFACE 0x01 +#define REQUEST_ENDPOINT 0x02 +#define REQUEST_OTHER 0x03 +#define REQUEST_RECIPIENT 0x1F + +#define REQUEST_DEVICETOHOST_CLASS_INTERFACE (REQUEST_DEVICETOHOST + REQUEST_CLASS + REQUEST_INTERFACE) +#define REQUEST_HOSTTODEVICE_CLASS_INTERFACE (REQUEST_HOSTTODEVICE + REQUEST_CLASS + REQUEST_INTERFACE) + +// Class requests + +#define CDC_SET_LINE_CODING 0x20 +#define CDC_GET_LINE_CODING 0x21 +#define CDC_SET_CONTROL_LINE_STATE 0x22 + +#define MSC_RESET 0xFF +#define MSC_GET_MAX_LUN 0xFE + +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B + +// Descriptors + +#define USB_DEVICE_DESC_SIZE 18 +#define USB_CONFIGUARTION_DESC_SIZE 9 +#define USB_INTERFACE_DESC_SIZE 9 +#define USB_ENDPOINT_DESC_SIZE 7 + +#define USB_DEVICE_DESCRIPTOR_TYPE 1 +#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2 +#define USB_STRING_DESCRIPTOR_TYPE 3 +#define USB_INTERFACE_DESCRIPTOR_TYPE 4 +#define USB_ENDPOINT_DESCRIPTOR_TYPE 5 +#define USB_DEVICE_QUALIFIER 6 +#define USB_OTHER_SPEED_CONFIGURATION 7 + +#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02 +#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03 +#define USB_DEVICE_CLASS_STORAGE 0x08 +#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF + +#define USB_CONFIG_POWERED_MASK 0x40 +#define USB_CONFIG_BUS_POWERED 0x80 +#define USB_CONFIG_SELF_POWERED 0xC0 +#define USB_CONFIG_REMOTE_WAKEUP 0x20 + +// bMaxPower in Configuration Descriptor +#define USB_CONFIG_POWER_MA(mA) ((mA)/2) + +// bEndpointAddress in Endpoint Descriptor +#define USB_ENDPOINT_DIRECTION_MASK 0x80 +#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00) +#define USB_ENDPOINT_IN(addr) ((addr) | 0x80) + +#define USB_ENDPOINT_TYPE_MASK 0x03 +#define USB_ENDPOINT_TYPE_CONTROL 0x00 +#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 +#define USB_ENDPOINT_TYPE_BULK 0x02 +#define USB_ENDPOINT_TYPE_INTERRUPT 0x03 + +#define TOBYTES(x) ((x) & 0xFF),(((x) >> 8) & 0xFF) + +#define CDC_V1_10 0x0110 +#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02 + +#define CDC_CALL_MANAGEMENT 0x01 +#define CDC_ABSTRACT_CONTROL_MODEL 0x02 +#define CDC_HEADER 0x00 +#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02 +#define CDC_UNION 0x06 +#define CDC_CS_INTERFACE 0x24 +#define CDC_CS_ENDPOINT 0x25 +#define CDC_DATA_INTERFACE_CLASS 0x0A + +#define MSC_SUBCLASS_SCSI 0x06 +#define MSC_PROTOCOL_BULK_ONLY 0x50 + +#define HID_HID_DESCRIPTOR_TYPE 0x21 +#define HID_REPORT_DESCRIPTOR_TYPE 0x22 +#define HID_PHYSICAL_DESCRIPTOR_TYPE 0x23 + +_Pragma("pack(1)") + +// Device +typedef struct { + uint8_t len; // 18 + uint8_t dtype; // 1 USB_DEVICE_DESCRIPTOR_TYPE + uint16_t usbVersion; // 0x200 + uint8_t deviceClass; + uint8_t deviceSubClass; + uint8_t deviceProtocol; + uint8_t packetSize0; // Packet 0 + uint16_t idVendor; + uint16_t idProduct; + uint16_t deviceVersion; // 0x100 + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} DeviceDescriptor; + +// Config +typedef struct { + uint8_t len; // 9 + uint8_t dtype; // 2 + uint16_t clen; // total length + uint8_t numInterfaces; + uint8_t config; + uint8_t iconfig; + uint8_t attributes; + uint8_t maxPower; +} ConfigDescriptor; + +// String + +// Interface +typedef struct +{ + uint8_t len; // 9 + uint8_t dtype; // 4 + uint8_t number; + uint8_t alternate; + uint8_t numEndpoints; + uint8_t interfaceClass; + uint8_t interfaceSubClass; + uint8_t protocol; + uint8_t iInterface; +} InterfaceDescriptor; + +// Endpoint +typedef struct +{ + uint8_t len; // 7 + uint8_t dtype; // 5 + uint8_t addr; + uint8_t attr; + uint16_t packetSize; + uint8_t interval; +} EndpointDescriptor; + +// Interface Association Descriptor +// Used to bind 2 interfaces together in CDC compostite device +typedef struct +{ + uint8_t len; // 8 + uint8_t dtype; // 11 + uint8_t firstInterface; + uint8_t interfaceCount; + uint8_t functionClass; + uint8_t funtionSubClass; + uint8_t functionProtocol; + uint8_t iInterface; +} IADDescriptor; + +// CDC CS interface descriptor +typedef struct +{ + uint8_t len; // 5 + uint8_t dtype; // 0x24 + uint8_t subtype; + uint8_t d0; + uint8_t d1; +} CDCCSInterfaceDescriptor; + +typedef struct +{ + uint8_t len; // 4 + uint8_t dtype; // 0x24 + uint8_t subtype; + uint8_t d0; +} CDCCSInterfaceDescriptor4; + +typedef struct +{ + uint8_t len; + uint8_t dtype; // 0x24 + uint8_t subtype; // 1 + uint8_t bmCapabilities; + uint8_t bDataInterface; +} CMFunctionalDescriptor; + +typedef struct +{ + uint8_t len; + uint8_t dtype; // 0x24 + uint8_t subtype; // 1 + uint8_t bmCapabilities; +} ACMFunctionalDescriptor; + +typedef struct +{ + // IAD + IADDescriptor iad; // Only needed on compound device + + // Control + InterfaceDescriptor cif; + CDCCSInterfaceDescriptor header; + CMFunctionalDescriptor callManagement; // Call Management + ACMFunctionalDescriptor controlManagement; // ACM + CDCCSInterfaceDescriptor functionalDescriptor; // CDC_UNION + EndpointDescriptor cifin; + + // Data + InterfaceDescriptor dif; + EndpointDescriptor in; + EndpointDescriptor out; +} CDCDescriptor; + +typedef struct +{ + InterfaceDescriptor msc; + EndpointDescriptor in; + EndpointDescriptor out; +} MSCDescriptor; + +typedef struct +{ + uint8_t len; // 9 + uint8_t dtype; // 0x21 + uint8_t addr; + uint8_t versionL; // 0x101 + uint8_t versionH; // 0x101 + uint8_t country; + uint8_t desctype; // 0x22 report + uint8_t descLenL; + uint8_t descLenH; +} HIDDescDescriptor; + +typedef struct +{ + InterfaceDescriptor hid; + HIDDescDescriptor desc; + EndpointDescriptor in; +} HIDDescriptor; + +_Pragma("pack()") + +#define D_DEVICE(_class,_subClass,_proto,_packetSize0,_vid,_pid,_version,_im,_ip,_is,_configs) \ + { 18, 1, 0x200, _class,_subClass,_proto,_packetSize0,_vid,_pid,_version,_im,_ip,_is,_configs } + +#define D_CONFIG(_totalLength,_interfaces) \ + { 9, 2, _totalLength,_interfaces, 1, 0, USB_CONFIG_SELF_POWERED, USB_CONFIG_POWER_MA(500) } + +#define D_OTHERCONFIG(_totalLength,_interfaces) \ + { 9, 7, _totalLength,_interfaces, 1, 0, USB_CONFIG_SELF_POWERED, USB_CONFIG_POWER_MA(500) } + +#define D_INTERFACE(_n,_numEndpoints,_class,_subClass,_protocol) \ + { 9, 4, _n, 0, _numEndpoints, _class,_subClass, _protocol, 0 } + +#define D_ENDPOINT(_addr,_attr,_packetSize, _interval) \ + { 7, 5, _addr,_attr,_packetSize, _interval } + +#define D_QUALIFIER(_class,_subClass,_proto,_packetSize0,_configs) \ + { 10, 6, 0x200, _class,_subClass,_proto,_packetSize0,_configs } + +#define D_IAD(_firstInterface, _count, _class, _subClass, _protocol) \ + { 8, 11, _firstInterface, _count, _class, _subClass, _protocol, 0 } + +#define D_HIDREPORT(_descriptorLength) \ + { 9, 0x21, 0x1, 0x1, 0, 1, 0x22, _descriptorLength, 0 } + +#define D_CDCCS(_subtype,_d0,_d1) { 5, 0x24, _subtype, _d0, _d1 } +#define D_CDCCS4(_subtype,_d0) { 4, 0x24, _subtype, _d0 } + +#endif diff --git a/hardware/digistump/sam/cores/digix/USB/USBDesc.h b/hardware/digistump/sam/cores/digix/USB/USBDesc.h new file mode 100644 index 0000000..878095e --- /dev/null +++ b/hardware/digistump/sam/cores/digix/USB/USBDesc.h @@ -0,0 +1,64 @@ +// Copyright (c) 2010, Peter Barrett +/* +** Permission to use, copy, modify, and/or distribute this software for +** any purpose with or without fee is hereby granted, provided that the +** above copyright notice and this permission notice appear in all copies. +** +** THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL +** WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR +** BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES +** OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +** WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +** ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +** SOFTWARE. +*/ + +#ifndef __USBDESC_H__ +#define __USBDESC_H__ + +#define CDC_ENABLED +#define HID_ENABLED + +#ifdef CDC_ENABLED +#define CDC_INTERFACE_COUNT 2 +#define CDC_ENPOINT_COUNT 3 +#else +#define CDC_INTERFACE_COUNT 0 +#define CDC_ENPOINT_COUNT 0 +#endif + +#ifdef HID_ENABLED +#define HID_INTERFACE_COUNT 1 +#define HID_ENPOINT_COUNT 1 +#else +#define HID_INTERFACE_COUNT 0 +#define HID_ENPOINT_COUNT 0 +#endif + +#define CDC_ACM_INTERFACE 0 // CDC ACM +#define CDC_DATA_INTERFACE 1 // CDC Data +#define CDC_FIRST_ENDPOINT 1 +#define CDC_ENDPOINT_ACM (CDC_FIRST_ENDPOINT) // CDC First +#define CDC_ENDPOINT_OUT (CDC_FIRST_ENDPOINT+1) +#define CDC_ENDPOINT_IN (CDC_FIRST_ENDPOINT+2) + +#define HID_INTERFACE (CDC_ACM_INTERFACE + CDC_INTERFACE_COUNT) // HID Interface +#define HID_FIRST_ENDPOINT (CDC_FIRST_ENDPOINT + CDC_ENPOINT_COUNT) +#define HID_ENDPOINT_INT (HID_FIRST_ENDPOINT) + +#define INTERFACE_COUNT (MSC_INTERFACE + MSC_INTERFACE_COUNT) + +#ifdef CDC_ENABLED +#define CDC_RX CDC_ENDPOINT_OUT +#define CDC_TX CDC_ENDPOINT_IN +#endif + +#ifdef HID_ENABLED +#define HID_TX HID_ENDPOINT_INT +#endif + +#define IMANUFACTURER 1 +#define IPRODUCT 2 + +#endif /* __USBDESC_H__ */ diff --git a/hardware/digistump/sam/cores/digix/Udp.h b/hardware/digistump/sam/cores/digix/Udp.h new file mode 100644 index 0000000..dc5644b --- /dev/null +++ b/hardware/digistump/sam/cores/digix/Udp.h @@ -0,0 +1,88 @@ +/* + * Udp.cpp: Library to send/receive UDP packets. + * + * NOTE: UDP is fast, but has some important limitations (thanks to Warren Gray for mentioning these) + * 1) UDP does not guarantee the order in which assembled UDP packets are received. This + * might not happen often in practice, but in larger network topologies, a UDP + * packet can be received out of sequence. + * 2) UDP does not guard against lost packets - so packets *can* disappear without the sender being + * aware of it. Again, this may not be a concern in practice on small local networks. + * For more information, see http://www.cafeaulait.org/course/week12/35.html + * + * MIT License: + * Copyright (c) 2008 Bjoern Hartmann + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * bjoern@cs.stanford.edu 12/30/2008 + */ + +#ifndef udp_h +#define udp_h + +#include +#include + +class UDP : public Stream { + +public: + virtual uint8_t begin(uint16_t) =0; // initialize, start listening on specified port. Returns 1 if successful, 0 if there are no sockets available to use + virtual void stop() =0; // Finish with the UDP socket + + // Sending UDP packets + + // Start building up a packet to send to the remote host specific in ip and port + // Returns 1 if successful, 0 if there was a problem with the supplied IP address or port + virtual int beginPacket(IPAddress ip, uint16_t port) =0; + // Start building up a packet to send to the remote host specific in host and port + // Returns 1 if successful, 0 if there was a problem resolving the hostname or port + virtual int beginPacket(const char *host, uint16_t port) =0; + // Finish off this packet and send it + // Returns 1 if the packet was sent successfully, 0 if there was an error + virtual int endPacket() =0; + // Write a single byte into the packet + virtual size_t write(uint8_t) =0; + // Write size bytes from buffer into the packet + virtual size_t write(const uint8_t *buffer, size_t size) =0; + + // Start processing the next available incoming packet + // Returns the size of the packet in bytes, or 0 if no packets are available + virtual int parsePacket() =0; + // Number of bytes remaining in the current packet + virtual int available() =0; + // Read a single byte from the current packet + virtual int read() =0; + // Read up to len bytes from the current packet and place them into buffer + // Returns the number of bytes read, or 0 if none are available + virtual int read(unsigned char* buffer, size_t len) =0; + // Read up to len characters from the current packet and place them into buffer + // Returns the number of characters read, or 0 if none are available + virtual int read(char* buffer, size_t len) =0; + // Return the next byte from the current packet without moving on to the next byte + virtual int peek() =0; + virtual void flush() =0; // Finish reading the current packet + + // Return the IP address of the host who sent the current incoming packet + virtual IPAddress remoteIP() =0; + // Return the port of the host who sent the current incoming packet + virtual uint16_t remotePort() =0; +protected: + uint8_t* rawIPAddress(IPAddress& addr) { return addr.raw_address(); }; +}; + +#endif diff --git a/hardware/digistump/sam/cores/digix/WCharacter.h b/hardware/digistump/sam/cores/digix/WCharacter.h new file mode 100644 index 0000000..e84b348 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/WCharacter.h @@ -0,0 +1,180 @@ +/* + WCharacter.h - Character utility functions for Wiring & Arduino + Copyright (c) 2010 Hernando Barragan. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef Character_h +#define Character_h + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// WCharacter.h prototypes +#if defined ( __GNUC__ ) +inline boolean isAlphaNumeric(int c) __attribute__((always_inline)); +inline boolean isAlpha(int c) __attribute__((always_inline)); +inline boolean isAscii(int c) __attribute__((always_inline)); +inline boolean isWhitespace(int c) __attribute__((always_inline)); +inline boolean isControl(int c) __attribute__((always_inline)); +inline boolean isDigit(int c) __attribute__((always_inline)); +inline boolean isGraph(int c) __attribute__((always_inline)); +inline boolean isLowerCase(int c) __attribute__((always_inline)); +inline boolean isPrintable(int c) __attribute__((always_inline)); +inline boolean isPunct(int c) __attribute__((always_inline)); +inline boolean isSpace(int c) __attribute__((always_inline)); +inline boolean isUpperCase(int c) __attribute__((always_inline)); +inline boolean isHexadecimalDigit(int c) __attribute__((always_inline)); +inline int toAscii(int c) __attribute__((always_inline)); +inline int toLowerCase(int c) __attribute__((always_inline)); +inline int toUpperCase(int c)__attribute__((always_inline)); +#elif defined ( __ICCARM__ ) +#endif + +// Checks for an alphanumeric character. +// It is equivalent to (isalpha(c) || isdigit(c)). +inline boolean isAlphaNumeric(int c) +{ + return ( isalnum(c) == 0 ? false : true); +} + + +// Checks for an alphabetic character. +// It is equivalent to (isupper(c) || islower(c)). +inline boolean isAlpha(int c) +{ + return ( isalpha(c) == 0 ? false : true); +} + + +// Checks whether c is a 7-bit unsigned char value +// that fits into the ASCII character set. +inline boolean isAscii(int c) +{ +/* return ( isascii(c) == 0 ? false : true); */ + return ( (c & ~0x7f) != 0 ? false : true); +} + + +// Checks for a blank character, that is, a space or a tab. +inline boolean isWhitespace(int c) +{ + return ( isblank (c) == 0 ? false : true); +} + + +// Checks for a control character. +inline boolean isControl(int c) +{ + return ( iscntrl (c) == 0 ? false : true); +} + + +// Checks for a digit (0 through 9). +inline boolean isDigit(int c) +{ + return ( isdigit (c) == 0 ? false : true); +} + + +// Checks for any printable character except space. +inline boolean isGraph(int c) +{ + return ( isgraph (c) == 0 ? false : true); +} + + +// Checks for a lower-case character. +inline boolean isLowerCase(int c) +{ + return (islower (c) == 0 ? false : true); +} + + +// Checks for any printable character including space. +inline boolean isPrintable(int c) +{ + return ( isprint (c) == 0 ? false : true); +} + + +// Checks for any printable character which is not a space +// or an alphanumeric character. +inline boolean isPunct(int c) +{ + return ( ispunct (c) == 0 ? false : true); +} + + +// Checks for white-space characters. For the avr-libc library, +// these are: space, formfeed ('\f'), newline ('\n'), carriage +// return ('\r'), horizontal tab ('\t'), and vertical tab ('\v'). +inline boolean isSpace(int c) +{ + return ( isspace (c) == 0 ? false : true); +} + + +// Checks for an uppercase letter. +inline boolean isUpperCase(int c) +{ + return ( isupper (c) == 0 ? false : true); +} + + +// Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7 +// 8 9 a b c d e f A B C D E F. +inline boolean isHexadecimalDigit(int c) +{ + return ( isxdigit (c) == 0 ? false : true); +} + + +// Converts c to a 7-bit unsigned char value that fits into the +// ASCII character set, by clearing the high-order bits. +inline int toAscii(int c) +{ +/* return toascii (c); */ + return (c & 0x7f); +} + + +// Warning: +// Many people will be unhappy if you use this function. +// This function will convert accented letters into random +// characters. + +// Converts the letter c to lower case, if possible. +inline int toLowerCase(int c) +{ + return tolower (c); +} + + +// Converts the letter c to upper case, if possible. +inline int toUpperCase(int c) +{ + return toupper (c); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hardware/digistump/sam/cores/digix/WInterrupts.c b/hardware/digistump/sam/cores/digix/WInterrupts.c new file mode 100644 index 0000000..87b83e4 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/WInterrupts.c @@ -0,0 +1,182 @@ +/* + Copyright (c) 2011-2012 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "WInterrupts.h" + +typedef void (*interruptCB)(void); + +static interruptCB callbacksPioA[32]; +static interruptCB callbacksPioB[32]; +static interruptCB callbacksPioC[32]; +static interruptCB callbacksPioD[32]; + +/* Configure PIO interrupt sources */ +static void __initialize() { + int i; + for (i=0; i<32; i++) { + callbacksPioA[i] = NULL; + callbacksPioB[i] = NULL; + callbacksPioC[i] = NULL; + callbacksPioD[i] = NULL; + } + + pmc_enable_periph_clk(ID_PIOA); + NVIC_DisableIRQ(PIOA_IRQn); + NVIC_ClearPendingIRQ(PIOA_IRQn); + NVIC_SetPriority(PIOA_IRQn, 0); + NVIC_EnableIRQ(PIOA_IRQn); + + pmc_enable_periph_clk(ID_PIOB); + NVIC_DisableIRQ(PIOB_IRQn); + NVIC_ClearPendingIRQ(PIOB_IRQn); + NVIC_SetPriority(PIOB_IRQn, 0); + NVIC_EnableIRQ(PIOB_IRQn); + + pmc_enable_periph_clk(ID_PIOC); + NVIC_DisableIRQ(PIOC_IRQn); + NVIC_ClearPendingIRQ(PIOC_IRQn); + NVIC_SetPriority(PIOC_IRQn, 0); + NVIC_EnableIRQ(PIOC_IRQn); + + pmc_enable_periph_clk(ID_PIOD); + NVIC_DisableIRQ(PIOD_IRQn); + NVIC_ClearPendingIRQ(PIOD_IRQn); + NVIC_SetPriority(PIOD_IRQn, 0); + NVIC_EnableIRQ(PIOD_IRQn); +} + + +void attachInterrupt(uint32_t pin, void (*callback)(void), uint32_t mode) +{ + static int enabled = 0; + if (!enabled) { + __initialize(); + enabled = 1; + } + + // Retrieve pin information + Pio *pio = g_APinDescription[pin].pPort; + uint32_t mask = g_APinDescription[pin].ulPin; + uint32_t pos = 0; + + uint32_t t; + for (t = mask; t>1; t>>=1, pos++) + ; + + // Set callback function + if (pio == PIOA) + callbacksPioA[pos] = callback; + if (pio == PIOB) + callbacksPioB[pos] = callback; + if (pio == PIOC) + callbacksPioC[pos] = callback; + if (pio == PIOD) + callbacksPioD[pos] = callback; + + // Configure the interrupt mode + if (mode == CHANGE) { + // Disable additional interrupt mode (detects both rising and falling edges) + pio->PIO_AIMDR = mask; + } else { + // Enable additional interrupt mode + pio->PIO_AIMER = mask; + + // Select mode of operation + if (mode == LOW) { + pio->PIO_LSR = mask; // "Level" Select Register + pio->PIO_FELLSR = mask; // "Falling Edge / Low Level" Select Register + } + if (mode == HIGH) { + pio->PIO_LSR = mask; // "Level" Select Register + pio->PIO_REHLSR = mask; // "Rising Edge / High Level" Select Register + } + if (mode == FALLING) { + pio->PIO_ESR = mask; // "Edge" Select Register + pio->PIO_FELLSR = mask; // "Falling Edge / Low Level" Select Register + } + if (mode == RISING) { + pio->PIO_ESR = mask; // "Edge" Select Register + pio->PIO_REHLSR = mask; // "Rising Edge / High Level" Select Register + } + } + + // Enable interrupt + pio->PIO_IER = mask; +} + +void detachInterrupt(uint32_t pin) +{ + // Retrieve pin information + Pio *pio = g_APinDescription[pin].pPort; + uint32_t mask = g_APinDescription[pin].ulPin; + + // Disable interrupt + pio->PIO_IDR = mask; +} + +#ifdef __cplusplus +extern "C" { +#endif + +void PIOA_Handler(void) { + uint32_t isr = PIOA->PIO_ISR; + uint32_t i; + for (i=0; i<32; i++, isr>>=1) { + if ((isr & 0x1) == 0) + continue; + if (callbacksPioA[i]) + callbacksPioA[i](); + } +} + +void PIOB_Handler(void) { + uint32_t isr = PIOB->PIO_ISR; + uint32_t i; + for (i=0; i<32; i++, isr>>=1) { + if ((isr & 0x1) == 0) + continue; + if (callbacksPioB[i]) + callbacksPioB[i](); + } +} + +void PIOC_Handler(void) { + uint32_t isr = PIOC->PIO_ISR; + uint32_t i; + for (i=0; i<32; i++, isr>>=1) { + if ((isr & 0x1) == 0) + continue; + if (callbacksPioC[i]) + callbacksPioC[i](); + } +} + +void PIOD_Handler(void) { + uint32_t isr = PIOD->PIO_ISR; + uint32_t i; + for (i=0; i<32; i++, isr>>=1) { + if ((isr & 0x1) == 0) + continue; + if (callbacksPioD[i]) + callbacksPioD[i](); + } +} + +#ifdef __cplusplus +} +#endif diff --git a/hardware/digistump/sam/cores/digix/WInterrupts.h b/hardware/digistump/sam/cores/digix/WInterrupts.h new file mode 100644 index 0000000..bb698cd --- /dev/null +++ b/hardware/digistump/sam/cores/digix/WInterrupts.h @@ -0,0 +1,36 @@ +/* + Copyright (c) 2011-2012 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_INTERRUPTS_ +#define _WIRING_INTERRUPTS_ + +#include "Arduino.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void attachInterrupt(uint32_t pin, void (*callback)(void), uint32_t mode); + +void detachInterrupt(uint32_t pin); + +#ifdef __cplusplus +} +#endif + +#endif /* _WIRING_INTERRUPTS_ */ diff --git a/hardware/digistump/sam/cores/digix/WMath.cpp b/hardware/digistump/sam/cores/digix/WMath.cpp new file mode 100644 index 0000000..ec2e29b --- /dev/null +++ b/hardware/digistump/sam/cores/digix/WMath.cpp @@ -0,0 +1,68 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +extern "C" { + #include "stdlib.h" + #include "stdint.h" +} +#include "WMath.h" + +extern void randomSeed( uint32_t dwSeed ) +{ + if ( dwSeed != 0 ) + { + srand( dwSeed ) ; + } +} + +extern long random( long howbig ) +{ + if ( howbig == 0 ) + { + return 0 ; + } + + return rand() % howbig; +} + +extern long random( long howsmall, long howbig ) +{ + if (howsmall >= howbig) + { + return howsmall; + } + + long diff = howbig - howsmall; + + return random(diff) + howsmall; +} + +extern long map(long x, long in_min, long in_max, long out_min, long out_max) +{ + return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min; +} + +extern uint16_t makeWord( uint16_t w ) +{ + return w ; +} + +extern uint16_t makeWord( uint8_t h, uint8_t l ) +{ + return (h << 8) | l ; +} diff --git a/hardware/digistump/sam/cores/digix/WMath.h b/hardware/digistump/sam/cores/digix/WMath.h new file mode 100644 index 0000000..05779ea --- /dev/null +++ b/hardware/digistump/sam/cores/digix/WMath.h @@ -0,0 +1,33 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_MATH_ +#define _WIRING_MATH_ + +extern long random( long ) ; +extern long random( long, long ) ; +extern void randomSeed( uint32_t dwSeed ) ; +extern long map( long, long, long, long, long ) ; + +extern uint16_t makeWord( uint16_t w ) ; +extern uint16_t makeWord( uint8_t h, uint8_t l ) ; + +#define word(...) makeWord(__VA_ARGS__) + + +#endif /* _WIRING_MATH_ */ diff --git a/hardware/digistump/sam/cores/digix/WString.cpp b/hardware/digistump/sam/cores/digix/WString.cpp new file mode 100644 index 0000000..265d856 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/WString.cpp @@ -0,0 +1,746 @@ +/* + WString.cpp - String library for Wiring & Arduino + ...mostly rewritten by Paul Stoffregen... + Copyright (c) 2009-10 Hernando Barragan. All rights reserved. + Copyright 2011, Paul Stoffregen, paul@pjrc.com + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "WString.h" +#include "itoa.h" +#include "avr/dtostrf.h" + +/*********************************************/ +/* Constructors */ +/*********************************************/ + +String::String(const char *cstr) +{ + init(); + if (cstr) copy(cstr, strlen(cstr)); +} + +String::String(const String &value) +{ + init(); + *this = value; +} + +String::String(const __FlashStringHelper *pstr) +{ + init(); + *this = pstr; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +String::String(String &&rval) +{ + init(); + move(rval); +} +String::String(StringSumHelper &&rval) +{ + init(); + move(rval); +} +#endif + +String::String(char c) +{ + init(); + char buf[2]; + buf[0] = c; + buf[1] = 0; + *this = buf; +} + +String::String(unsigned char value, unsigned char base) +{ + init(); + char buf[9]; + utoa(value, buf, base); + *this = buf; +} + +String::String(int value, unsigned char base) +{ + init(); + char buf[18]; + itoa(value, buf, base); + *this = buf; +} + +String::String(unsigned int value, unsigned char base) +{ + init(); + char buf[17]; + utoa(value, buf, base); + *this = buf; +} + +String::String(long value, unsigned char base) +{ + init(); + char buf[34]; + ltoa(value, buf, base); + *this = buf; +} + +String::String(unsigned long value, unsigned char base) +{ + init(); + char buf[33]; + ultoa(value, buf, base); + *this = buf; +} + +String::String(float value, unsigned char decimalPlaces) +{ + init(); + char buf[33]; + *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf); +} + +String::String(double value, unsigned char decimalPlaces) +{ + init(); + char buf[33]; + *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf); +} + +String::~String() +{ + free(buffer); +} + +/*********************************************/ +/* Memory Management */ +/*********************************************/ + +inline void String::init(void) +{ + buffer = NULL; + capacity = 0; + len = 0; +} + +void String::invalidate(void) +{ + if (buffer) free(buffer); + buffer = NULL; + capacity = len = 0; +} + +unsigned char String::reserve(unsigned int size) +{ + if (buffer && capacity >= size) return 1; + if (changeBuffer(size)) { + if (len == 0) buffer[0] = 0; + return 1; + } + return 0; +} + +unsigned char String::changeBuffer(unsigned int maxStrLen) +{ + char *newbuffer = (char *)realloc(buffer, maxStrLen + 1); + if (newbuffer) { + buffer = newbuffer; + capacity = maxStrLen; + return 1; + } + return 0; +} + +/*********************************************/ +/* Copy and Move */ +/*********************************************/ + +String & String::copy(const char *cstr, unsigned int length) +{ + if (!reserve(length)) { + invalidate(); + return *this; + } + len = length; + strcpy(buffer, cstr); + return *this; +} + +String & String::copy(const __FlashStringHelper *pstr, unsigned int length) +{ + if (!reserve(length)) { + invalidate(); + return *this; + } + len = length; + strcpy_P(buffer, (const prog_char *)pstr); + return *this; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +void String::move(String &rhs) +{ + if (buffer) { + if (capacity >= rhs.len) { + strcpy(buffer, rhs.buffer); + len = rhs.len; + rhs.len = 0; + return; + } else { + free(buffer); + } + } + buffer = rhs.buffer; + capacity = rhs.capacity; + len = rhs.len; + rhs.buffer = NULL; + rhs.capacity = 0; + rhs.len = 0; +} +#endif + +String & String::operator = (const String &rhs) +{ + if (this == &rhs) return *this; + + if (rhs.buffer) copy(rhs.buffer, rhs.len); + else invalidate(); + + return *this; +} + +#ifdef __GXX_EXPERIMENTAL_CXX0X__ +String & String::operator = (String &&rval) +{ + if (this != &rval) move(rval); + return *this; +} + +String & String::operator = (StringSumHelper &&rval) +{ + if (this != &rval) move(rval); + return *this; +} +#endif + +String & String::operator = (const char *cstr) +{ + if (cstr) copy(cstr, strlen(cstr)); + else invalidate(); + + return *this; +} + +String & String::operator = (const __FlashStringHelper *pstr) +{ + if (pstr) copy(pstr, strlen_P((const prog_char *)pstr)); + else invalidate(); + + return *this; +} + +/*********************************************/ +/* concat */ +/*********************************************/ + +unsigned char String::concat(const String &s) +{ + return concat(s.buffer, s.len); +} + +unsigned char String::concat(const char *cstr, unsigned int length) +{ + unsigned int newlen = len + length; + if (!cstr) return 0; + if (length == 0) return 1; + if (!reserve(newlen)) return 0; + strcpy(buffer + len, cstr); + len = newlen; + return 1; +} + +unsigned char String::concat(const char *cstr) +{ + if (!cstr) return 0; + return concat(cstr, strlen(cstr)); +} + +unsigned char String::concat(char c) +{ + char buf[2]; + buf[0] = c; + buf[1] = 0; + return concat(buf, 1); +} + +unsigned char String::concat(unsigned char num) +{ + char buf[4]; + itoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(int num) +{ + char buf[12]; + itoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(unsigned int num) +{ + char buf[11]; + utoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(long num) +{ + char buf[12]; + ltoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(unsigned long num) +{ + char buf[11]; + ultoa(num, buf, 10); + return concat(buf, strlen(buf)); +} + +unsigned char String::concat(float num) +{ + char buf[20]; + char* string = dtostrf(num, 4, 2, buf); + return concat(string, strlen(string)); +} + +unsigned char String::concat(double num) +{ + char buf[20]; + char* string = dtostrf(num, 4, 2, buf); + return concat(string, strlen(string)); +} + +unsigned char String::concat(const __FlashStringHelper * str) +{ + if (!str) return 0; + int length = strlen_P((const char *) str); + if (length == 0) return 1; + unsigned int newlen = len + length; + if (!reserve(newlen)) return 0; + strcpy_P(buffer + len, (const char *) str); + len = newlen; + return 1; +} + +/*********************************************/ +/* Concatenate */ +/*********************************************/ + +StringSumHelper & operator + (const StringSumHelper &lhs, const String &rhs) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(rhs.buffer, rhs.len)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, const char *cstr) +{ + StringSumHelper &a = const_cast(lhs); + if (!cstr || !a.concat(cstr, strlen(cstr))) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, char c) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(c)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, unsigned char num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, int num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, unsigned int num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, long num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, unsigned long num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, float num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, double num) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(num)) a.invalidate(); + return a; +} + +StringSumHelper & operator + (const StringSumHelper &lhs, const __FlashStringHelper *rhs) +{ + StringSumHelper &a = const_cast(lhs); + if (!a.concat(rhs)) a.invalidate(); + return a; +} + +/*********************************************/ +/* Comparison */ +/*********************************************/ + +int String::compareTo(const String &s) const +{ + if (!buffer || !s.buffer) { + if (s.buffer && s.len > 0) return 0 - *(unsigned char *)s.buffer; + if (buffer && len > 0) return *(unsigned char *)buffer; + return 0; + } + return strcmp(buffer, s.buffer); +} + +unsigned char String::equals(const String &s2) const +{ + return (len == s2.len && compareTo(s2) == 0); +} + +unsigned char String::equals(const char *cstr) const +{ + if (len == 0) return (cstr == NULL || *cstr == 0); + if (cstr == NULL) return buffer[0] == 0; + return strcmp(buffer, cstr) == 0; +} + +unsigned char String::operator<(const String &rhs) const +{ + return compareTo(rhs) < 0; +} + +unsigned char String::operator>(const String &rhs) const +{ + return compareTo(rhs) > 0; +} + +unsigned char String::operator<=(const String &rhs) const +{ + return compareTo(rhs) <= 0; +} + +unsigned char String::operator>=(const String &rhs) const +{ + return compareTo(rhs) >= 0; +} + +unsigned char String::equalsIgnoreCase( const String &s2 ) const +{ + if (this == &s2) return 1; + if (len != s2.len) return 0; + if (len == 0) return 1; + const char *p1 = buffer; + const char *p2 = s2.buffer; + while (*p1) { + if (tolower(*p1++) != tolower(*p2++)) return 0; + } + return 1; +} + +unsigned char String::startsWith( const String &s2 ) const +{ + if (len < s2.len) return 0; + return startsWith(s2, 0); +} + +unsigned char String::startsWith( const String &s2, unsigned int offset ) const +{ + if (offset > len - s2.len || !buffer || !s2.buffer) return 0; + return strncmp( &buffer[offset], s2.buffer, s2.len ) == 0; +} + +unsigned char String::endsWith( const String &s2 ) const +{ + if ( len < s2.len || !buffer || !s2.buffer) return 0; + return strcmp(&buffer[len - s2.len], s2.buffer) == 0; +} + +/*********************************************/ +/* Character Access */ +/*********************************************/ + +char String::charAt(unsigned int loc) const +{ + return operator[](loc); +} + +void String::setCharAt(unsigned int loc, char c) +{ + if (loc < len) buffer[loc] = c; +} + +char & String::operator[](unsigned int index) +{ + static char dummy_writable_char; + if (index >= len || !buffer) { + dummy_writable_char = 0; + return dummy_writable_char; + } + return buffer[index]; +} + +char String::operator[]( unsigned int index ) const +{ + if (index >= len || !buffer) return 0; + return buffer[index]; +} + +void String::getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index) const +{ + if (!bufsize || !buf) return; + if (index >= len) { + buf[0] = 0; + return; + } + unsigned int n = bufsize - 1; + if (n > len - index) n = len - index; + strncpy((char *)buf, buffer + index, n); + buf[n] = 0; +} + +/*********************************************/ +/* Search */ +/*********************************************/ + +int String::indexOf(char c) const +{ + return indexOf(c, 0); +} + +int String::indexOf( char ch, unsigned int fromIndex ) const +{ + if (fromIndex >= len) return -1; + const char* temp = strchr(buffer + fromIndex, ch); + if (temp == NULL) return -1; + return temp - buffer; +} + +int String::indexOf(const String &s2) const +{ + return indexOf(s2, 0); +} + +int String::indexOf(const String &s2, unsigned int fromIndex) const +{ + if (fromIndex >= len) return -1; + const char *found = strstr(buffer + fromIndex, s2.buffer); + if (found == NULL) return -1; + return found - buffer; +} + +int String::lastIndexOf( char theChar ) const +{ + return lastIndexOf(theChar, len - 1); +} + +int String::lastIndexOf(char ch, unsigned int fromIndex) const +{ + if (fromIndex >= len) return -1; + char tempchar = buffer[fromIndex + 1]; + buffer[fromIndex + 1] = '\0'; + char* temp = strrchr( buffer, ch ); + buffer[fromIndex + 1] = tempchar; + if (temp == NULL) return -1; + return temp - buffer; +} + +int String::lastIndexOf(const String &s2) const +{ + return lastIndexOf(s2, len - s2.len); +} + +int String::lastIndexOf(const String &s2, unsigned int fromIndex) const +{ + if (s2.len == 0 || len == 0 || s2.len > len) return -1; + if (fromIndex >= len) fromIndex = len - 1; + int found = -1; + for (char *p = buffer; p <= buffer + fromIndex; p++) { + p = strstr(p, s2.buffer); + if (!p) break; + if ((unsigned int)(p - buffer) <= fromIndex) found = p - buffer; + } + return found; +} + +String String::substring(unsigned int left, unsigned int right) const +{ + if (left > right) { + unsigned int temp = right; + right = left; + left = temp; + } + String out; + if (left > len) return out; + if (right > len) right = len; + char temp = buffer[right]; // save the replaced character + buffer[right] = '\0'; + out = buffer + left; // pointer arithmetic + buffer[right] = temp; //restore character + return out; +} + +/*********************************************/ +/* Modification */ +/*********************************************/ + +void String::replace(char find, char replace) +{ + if (!buffer) return; + for (char *p = buffer; *p; p++) { + if (*p == find) *p = replace; + } +} + +void String::replace(const String& find, const String& replace) +{ + if (len == 0 || find.len == 0) return; + int diff = replace.len - find.len; + char *readFrom = buffer; + char *foundAt; + if (diff == 0) { + while ((foundAt = strstr(readFrom, find.buffer)) != NULL) { + memcpy(foundAt, replace.buffer, replace.len); + readFrom = foundAt + replace.len; + } + } else if (diff < 0) { + char *writeTo = buffer; + while ((foundAt = strstr(readFrom, find.buffer)) != NULL) { + unsigned int n = foundAt - readFrom; + memcpy(writeTo, readFrom, n); + writeTo += n; + memcpy(writeTo, replace.buffer, replace.len); + writeTo += replace.len; + readFrom = foundAt + find.len; + len += diff; + } + strcpy(writeTo, readFrom); + } else { + unsigned int size = len; // compute size needed for result + while ((foundAt = strstr(readFrom, find.buffer)) != NULL) { + readFrom = foundAt + find.len; + size += diff; + } + if (size == len) return; + if (size > capacity && !changeBuffer(size)) return; // XXX: tell user! + int index = len - 1; + while (index >= 0 && (index = lastIndexOf(find, index)) >= 0) { + readFrom = buffer + index + find.len; + memmove(readFrom + diff, readFrom, len - (readFrom - buffer)); + len += diff; + buffer[len] = 0; + memcpy(buffer + index, replace.buffer, replace.len); + index--; + } + } +} + +void String::remove(unsigned int index){ + if (index >= len) { return; } + int count = len - index; + remove(index, count); +} + +void String::remove(unsigned int index, unsigned int count){ + if (index >= len) { return; } + if (count <= 0) { return; } + if (index + count > len) { count = len - index; } + char *writeTo = buffer + index; + len = len - count; + strncpy(writeTo, buffer + index + count,len - index); + buffer[len] = 0; +} + +void String::toLowerCase(void) +{ + if (!buffer) return; + for (char *p = buffer; *p; p++) { + *p = tolower(*p); + } +} + +void String::toUpperCase(void) +{ + if (!buffer) return; + for (char *p = buffer; *p; p++) { + *p = toupper(*p); + } +} + +void String::trim(void) +{ + if (!buffer || len == 0) return; + char *begin = buffer; + while (isspace(*begin)) begin++; + char *end = buffer + len - 1; + while (isspace(*end) && end >= begin) end--; + len = end + 1 - begin; + if (begin > buffer) memcpy(buffer, begin, len); + buffer[len] = 0; +} + +/*********************************************/ +/* Parsing / Conversion */ +/*********************************************/ + +long String::toInt(void) const +{ + if (buffer) return atol(buffer); + return 0; +} + +float String::toFloat(void) const +{ + if (buffer) return float(atof(buffer)); + return 0; +} \ No newline at end of file diff --git a/hardware/digistump/sam/cores/digix/WString.h b/hardware/digistump/sam/cores/digix/WString.h new file mode 100644 index 0000000..72efa23 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/WString.h @@ -0,0 +1,224 @@ +/* + WString.h - String library for Wiring & Arduino + ...mostly rewritten by Paul Stoffregen... + Copyright (c) 2009-10 Hernando Barragan. All right reserved. + Copyright 2011, Paul Stoffregen, paul@pjrc.com + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef String_class_h +#define String_class_h +#ifdef __cplusplus + +#include +#include +#include +#include + +// When compiling programs with this class, the following gcc parameters +// dramatically increase performance and memory (RAM) efficiency, typically +// with little or no increase in code size. +// -felide-constructors +// -std=c++0x + +class __FlashStringHelper; +#define F(string_literal) (reinterpret_cast(PSTR(string_literal))) + +// An inherited class for holding the result of a concatenation. These +// result objects are assumed to be writable by subsequent concatenations. +class StringSumHelper; + +// The string class +class String +{ + // use a function pointer to allow for "if (s)" without the + // complications of an operator bool(). for more information, see: + // http://www.artima.com/cppsource/safebool.html + typedef void (String::*StringIfHelperType)() const; + void StringIfHelper() const {} + +public: + // constructors + // creates a copy of the initial value. + // if the initial value is null or invalid, or if memory allocation + // fails, the string will be marked as invalid (i.e. "if (s)" will + // be false). + String(const char *cstr = ""); + String(const String &str); + String(const __FlashStringHelper *str); + #ifdef __GXX_EXPERIMENTAL_CXX0X__ + String(String &&rval); + String(StringSumHelper &&rval); + #endif + explicit String(char c); + explicit String(unsigned char, unsigned char base=10); + explicit String(int, unsigned char base=10); + explicit String(unsigned int, unsigned char base=10); + explicit String(long, unsigned char base=10); + explicit String(unsigned long, unsigned char base=10); + explicit String(float, unsigned char decimalPlaces=2); + explicit String(double, unsigned char decimalPlaces=2); + ~String(void); + + // memory management + // return true on success, false on failure (in which case, the string + // is left unchanged). reserve(0), if successful, will validate an + // invalid string (i.e., "if (s)" will be true afterwards) + unsigned char reserve(unsigned int size); + inline unsigned int length(void) const {return len;} + + // creates a copy of the assigned value. if the value is null or + // invalid, or if the memory allocation fails, the string will be + // marked as invalid ("if (s)" will be false). + String & operator = (const String &rhs); + String & operator = (const char *cstr); + String & operator = (const __FlashStringHelper *str); + #ifdef __GXX_EXPERIMENTAL_CXX0X__ + String & operator = (String &&rval); + String & operator = (StringSumHelper &&rval); + #endif + + // concatenate (works w/ built-in types) + + // returns true on success, false on failure (in which case, the string + // is left unchanged). if the argument is null or invalid, the + // concatenation is considered unsucessful. + unsigned char concat(const String &str); + unsigned char concat(const char *cstr); + unsigned char concat(char c); + unsigned char concat(unsigned char c); + unsigned char concat(int num); + unsigned char concat(unsigned int num); + unsigned char concat(long num); + unsigned char concat(unsigned long num); + unsigned char concat(float num); + unsigned char concat(double num); + unsigned char concat(const __FlashStringHelper * str); + + // if there's not enough memory for the concatenated value, the string + // will be left unchanged (but this isn't signalled in any way) + String & operator += (const String &rhs) {concat(rhs); return (*this);} + String & operator += (const char *cstr) {concat(cstr); return (*this);} + String & operator += (char c) {concat(c); return (*this);} + String & operator += (unsigned char num) {concat(num); return (*this);} + String & operator += (int num) {concat(num); return (*this);} + String & operator += (unsigned int num) {concat(num); return (*this);} + String & operator += (long num) {concat(num); return (*this);} + String & operator += (unsigned long num) {concat(num); return (*this);} + String & operator += (float num) {concat(num); return (*this);} + String & operator += (double num) {concat(num); return (*this);} + String & operator += (const __FlashStringHelper *str){concat(str); return (*this);} + + friend StringSumHelper & operator + (const StringSumHelper &lhs, const String &rhs); + friend StringSumHelper & operator + (const StringSumHelper &lhs, const char *cstr); + friend StringSumHelper & operator + (const StringSumHelper &lhs, char c); + friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned char num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, int num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned int num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, long num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned long num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, float num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, double num); + friend StringSumHelper & operator + (const StringSumHelper &lhs, const __FlashStringHelper *rhs); + + // comparison (only works w/ Strings and "strings") + operator StringIfHelperType() const { return buffer ? &String::StringIfHelper : 0; } + int compareTo(const String &s) const; + unsigned char equals(const String &s) const; + unsigned char equals(const char *cstr) const; + unsigned char operator == (const String &rhs) const {return equals(rhs);} + unsigned char operator == (const char *cstr) const {return equals(cstr);} + unsigned char operator != (const String &rhs) const {return !equals(rhs);} + unsigned char operator != (const char *cstr) const {return !equals(cstr);} + unsigned char operator < (const String &rhs) const; + unsigned char operator > (const String &rhs) const; + unsigned char operator <= (const String &rhs) const; + unsigned char operator >= (const String &rhs) const; + unsigned char equalsIgnoreCase(const String &s) const; + unsigned char startsWith( const String &prefix) const; + unsigned char startsWith(const String &prefix, unsigned int offset) const; + unsigned char endsWith(const String &suffix) const; + + // character acccess + char charAt(unsigned int index) const; + void setCharAt(unsigned int index, char c); + char operator [] (unsigned int index) const; + char& operator [] (unsigned int index); + void getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index=0) const; + void toCharArray(char *buf, unsigned int bufsize, unsigned int index=0) const + {getBytes((unsigned char *)buf, bufsize, index);} + const char * c_str() const { return buffer; } + + // search + int indexOf( char ch ) const; + int indexOf( char ch, unsigned int fromIndex ) const; + int indexOf( const String &str ) const; + int indexOf( const String &str, unsigned int fromIndex ) const; + int lastIndexOf( char ch ) const; + int lastIndexOf( char ch, unsigned int fromIndex ) const; + int lastIndexOf( const String &str ) const; + int lastIndexOf( const String &str, unsigned int fromIndex ) const; + String substring( unsigned int beginIndex ) const { return substring(beginIndex, len); }; + String substring( unsigned int beginIndex, unsigned int endIndex ) const; + + // modification + void replace(char find, char replace); + void replace(const String& find, const String& replace); + void remove(unsigned int index); + void remove(unsigned int index, unsigned int count); + void toLowerCase(void); + void toUpperCase(void); + void trim(void); + + // parsing/conversion + long toInt(void) const; + float toFloat(void) const; + +protected: + char *buffer; // the actual char array + unsigned int capacity; // the array length minus one (for the '\0') + unsigned int len; // the String length (not counting the '\0') +protected: + void init(void); + void invalidate(void); + unsigned char changeBuffer(unsigned int maxStrLen); + unsigned char concat(const char *cstr, unsigned int length); + + // copy and move + String & copy(const char *cstr, unsigned int length); + String & copy(const __FlashStringHelper *pstr, unsigned int length); + #ifdef __GXX_EXPERIMENTAL_CXX0X__ + void move(String &rhs); + #endif +}; + +class StringSumHelper : public String +{ +public: + StringSumHelper(const String &s) : String(s) {} + StringSumHelper(const char *p) : String(p) {} + StringSumHelper(char c) : String(c) {} + StringSumHelper(unsigned char num) : String(num) {} + StringSumHelper(int num) : String(num) {} + StringSumHelper(unsigned int num) : String(num) {} + StringSumHelper(long num) : String(num) {} + StringSumHelper(unsigned long num) : String(num) {} + StringSumHelper(float num) : String(num) {} + StringSumHelper(double num) : String(num) {} +}; + +#endif // __cplusplus +#endif // String_class_h \ No newline at end of file diff --git a/hardware/digistump/sam/cores/digix/avr/dtostrf.c b/hardware/digistump/sam/cores/digix/avr/dtostrf.c new file mode 100644 index 0000000..5154173 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/avr/dtostrf.c @@ -0,0 +1,27 @@ +/* + dtostrf - Emulation for dtostrf function from avr-libc + Copyright (c) 2013 Arduino. All rights reserved. + Written by Cristian Maglie + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +char *dtostrf (double val, signed char width, unsigned char prec, char *sout) { + char fmt[20]; + sprintf(fmt, "%%%d.%df", width, prec); + sprintf(sout, fmt, val); + return sout; +} + diff --git a/hardware/digistump/sam/cores/digix/avr/dtostrf.h b/hardware/digistump/sam/cores/digix/avr/dtostrf.h new file mode 100644 index 0000000..0bf9f57 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/avr/dtostrf.h @@ -0,0 +1,29 @@ +/* + dtostrf - Emulation for dtostrf function from avr-libc + Copyright (c) 2013 Arduino. All rights reserved. + Written by Cristian Maglie + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +char *dtostrf (double val, signed char width, unsigned char prec, char *sout); + +#ifdef __cplusplus +} +#endif diff --git a/hardware/digistump/sam/cores/digix/avr/interrupt.h b/hardware/digistump/sam/cores/digix/avr/interrupt.h new file mode 100644 index 0000000..e69de29 diff --git a/hardware/digistump/sam/cores/digix/avr/pgmspace.h b/hardware/digistump/sam/cores/digix/avr/pgmspace.h new file mode 100644 index 0000000..9b344c9 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/avr/pgmspace.h @@ -0,0 +1,44 @@ +#ifndef __PGMSPACE_H_ +#define __PGMSPACE_H_ 1 + +#include + +#define PROGMEM +#define PGM_P const char * +#define PSTR(str) (str) + +#define _SFR_BYTE(n) (n) + +typedef void prog_void; +typedef char prog_char; +typedef unsigned char prog_uchar; +typedef int8_t prog_int8_t; +typedef uint8_t prog_uint8_t; +typedef int16_t prog_int16_t; +typedef uint16_t prog_uint16_t; +typedef int32_t prog_int32_t; +typedef uint32_t prog_uint32_t; + +#define memcpy_P(dest, src, num) memcpy((dest), (src), (num)) +#define strcpy_P(dest, src) strcpy((dest), (src)) +#define strcat_P(dest, src) strcat((dest), (src)) +#define strcmp_P(a, b) strcmp((a), (b)) +#define strstr_P(a, b) strstr((a), (b)) +#define strlen_P(a) strlen((a)) +#define sprintf_P(s, f, ...) sprintf((s), (f), __VA_ARGS__) + +#define pgm_read_byte(addr) (*(const unsigned char *)(addr)) +#define pgm_read_word(addr) (*(const unsigned short *)(addr)) +#define pgm_read_dword(addr) (*(const unsigned long *)(addr)) +#define pgm_read_float(addr) (*(const float *)(addr)) + +#define pgm_read_byte_near(addr) pgm_read_byte(addr) +#define pgm_read_word_near(addr) pgm_read_word(addr) +#define pgm_read_dword_near(addr) pgm_read_dword(addr) +#define pgm_read_float_near(addr) pgm_read_float(addr) +#define pgm_read_byte_far(addr) pgm_read_byte(addr) +#define pgm_read_word_far(addr) pgm_read_word(addr) +#define pgm_read_dword_far(addr) pgm_read_dword(addr) +#define pgm_read_float_far(addr) pgm_read_float(addr) + +#endif diff --git a/hardware/digistump/sam/cores/digix/binary.h b/hardware/digistump/sam/cores/digix/binary.h new file mode 100644 index 0000000..af14980 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/binary.h @@ -0,0 +1,515 @@ +#ifndef Binary_h +#define Binary_h + +#define B0 0 +#define B00 0 +#define B000 0 +#define B0000 0 +#define B00000 0 +#define B000000 0 +#define B0000000 0 +#define B00000000 0 +#define B1 1 +#define B01 1 +#define B001 1 +#define B0001 1 +#define B00001 1 +#define B000001 1 +#define B0000001 1 +#define B00000001 1 +#define B10 2 +#define B010 2 +#define B0010 2 +#define B00010 2 +#define B000010 2 +#define B0000010 2 +#define B00000010 2 +#define B11 3 +#define B011 3 +#define B0011 3 +#define B00011 3 +#define B000011 3 +#define B0000011 3 +#define B00000011 3 +#define B100 4 +#define B0100 4 +#define B00100 4 +#define B000100 4 +#define B0000100 4 +#define B00000100 4 +#define B101 5 +#define B0101 5 +#define B00101 5 +#define B000101 5 +#define B0000101 5 +#define B00000101 5 +#define B110 6 +#define B0110 6 +#define B00110 6 +#define B000110 6 +#define B0000110 6 +#define B00000110 6 +#define B111 7 +#define B0111 7 +#define B00111 7 +#define B000111 7 +#define B0000111 7 +#define B00000111 7 +#define B1000 8 +#define B01000 8 +#define B001000 8 +#define B0001000 8 +#define B00001000 8 +#define B1001 9 +#define B01001 9 +#define B001001 9 +#define B0001001 9 +#define B00001001 9 +#define B1010 10 +#define B01010 10 +#define B001010 10 +#define B0001010 10 +#define B00001010 10 +#define B1011 11 +#define B01011 11 +#define B001011 11 +#define B0001011 11 +#define B00001011 11 +#define B1100 12 +#define B01100 12 +#define B001100 12 +#define B0001100 12 +#define B00001100 12 +#define B1101 13 +#define B01101 13 +#define B001101 13 +#define B0001101 13 +#define B00001101 13 +#define B1110 14 +#define B01110 14 +#define B001110 14 +#define B0001110 14 +#define B00001110 14 +#define B1111 15 +#define B01111 15 +#define B001111 15 +#define B0001111 15 +#define B00001111 15 +#define B10000 16 +#define B010000 16 +#define B0010000 16 +#define B00010000 16 +#define B10001 17 +#define B010001 17 +#define B0010001 17 +#define B00010001 17 +#define B10010 18 +#define B010010 18 +#define B0010010 18 +#define B00010010 18 +#define B10011 19 +#define B010011 19 +#define B0010011 19 +#define B00010011 19 +#define B10100 20 +#define B010100 20 +#define B0010100 20 +#define B00010100 20 +#define B10101 21 +#define B010101 21 +#define B0010101 21 +#define B00010101 21 +#define B10110 22 +#define B010110 22 +#define B0010110 22 +#define B00010110 22 +#define B10111 23 +#define B010111 23 +#define B0010111 23 +#define B00010111 23 +#define B11000 24 +#define B011000 24 +#define B0011000 24 +#define B00011000 24 +#define B11001 25 +#define B011001 25 +#define B0011001 25 +#define B00011001 25 +#define B11010 26 +#define B011010 26 +#define B0011010 26 +#define B00011010 26 +#define B11011 27 +#define B011011 27 +#define B0011011 27 +#define B00011011 27 +#define B11100 28 +#define B011100 28 +#define B0011100 28 +#define B00011100 28 +#define B11101 29 +#define B011101 29 +#define B0011101 29 +#define B00011101 29 +#define B11110 30 +#define B011110 30 +#define B0011110 30 +#define B00011110 30 +#define B11111 31 +#define B011111 31 +#define B0011111 31 +#define B00011111 31 +#define B100000 32 +#define B0100000 32 +#define B00100000 32 +#define B100001 33 +#define B0100001 33 +#define B00100001 33 +#define B100010 34 +#define B0100010 34 +#define B00100010 34 +#define B100011 35 +#define B0100011 35 +#define B00100011 35 +#define B100100 36 +#define B0100100 36 +#define B00100100 36 +#define B100101 37 +#define B0100101 37 +#define B00100101 37 +#define B100110 38 +#define B0100110 38 +#define B00100110 38 +#define B100111 39 +#define B0100111 39 +#define B00100111 39 +#define B101000 40 +#define B0101000 40 +#define B00101000 40 +#define B101001 41 +#define B0101001 41 +#define B00101001 41 +#define B101010 42 +#define B0101010 42 +#define B00101010 42 +#define B101011 43 +#define B0101011 43 +#define B00101011 43 +#define B101100 44 +#define B0101100 44 +#define B00101100 44 +#define B101101 45 +#define B0101101 45 +#define B00101101 45 +#define B101110 46 +#define B0101110 46 +#define B00101110 46 +#define B101111 47 +#define B0101111 47 +#define B00101111 47 +#define B110000 48 +#define B0110000 48 +#define B00110000 48 +#define B110001 49 +#define B0110001 49 +#define B00110001 49 +#define B110010 50 +#define B0110010 50 +#define B00110010 50 +#define B110011 51 +#define B0110011 51 +#define B00110011 51 +#define B110100 52 +#define B0110100 52 +#define B00110100 52 +#define B110101 53 +#define B0110101 53 +#define B00110101 53 +#define B110110 54 +#define B0110110 54 +#define B00110110 54 +#define B110111 55 +#define B0110111 55 +#define B00110111 55 +#define B111000 56 +#define B0111000 56 +#define B00111000 56 +#define B111001 57 +#define B0111001 57 +#define B00111001 57 +#define B111010 58 +#define B0111010 58 +#define B00111010 58 +#define B111011 59 +#define B0111011 59 +#define B00111011 59 +#define B111100 60 +#define B0111100 60 +#define B00111100 60 +#define B111101 61 +#define B0111101 61 +#define B00111101 61 +#define B111110 62 +#define B0111110 62 +#define B00111110 62 +#define B111111 63 +#define B0111111 63 +#define B00111111 63 +#define B1000000 64 +#define B01000000 64 +#define B1000001 65 +#define B01000001 65 +#define B1000010 66 +#define B01000010 66 +#define B1000011 67 +#define B01000011 67 +#define B1000100 68 +#define B01000100 68 +#define B1000101 69 +#define B01000101 69 +#define B1000110 70 +#define B01000110 70 +#define B1000111 71 +#define B01000111 71 +#define B1001000 72 +#define B01001000 72 +#define B1001001 73 +#define B01001001 73 +#define B1001010 74 +#define B01001010 74 +#define B1001011 75 +#define B01001011 75 +#define B1001100 76 +#define B01001100 76 +#define B1001101 77 +#define B01001101 77 +#define B1001110 78 +#define B01001110 78 +#define B1001111 79 +#define B01001111 79 +#define B1010000 80 +#define B01010000 80 +#define B1010001 81 +#define B01010001 81 +#define B1010010 82 +#define B01010010 82 +#define B1010011 83 +#define B01010011 83 +#define B1010100 84 +#define B01010100 84 +#define B1010101 85 +#define B01010101 85 +#define B1010110 86 +#define B01010110 86 +#define B1010111 87 +#define B01010111 87 +#define B1011000 88 +#define B01011000 88 +#define B1011001 89 +#define B01011001 89 +#define B1011010 90 +#define B01011010 90 +#define B1011011 91 +#define B01011011 91 +#define B1011100 92 +#define B01011100 92 +#define B1011101 93 +#define B01011101 93 +#define B1011110 94 +#define B01011110 94 +#define B1011111 95 +#define B01011111 95 +#define B1100000 96 +#define B01100000 96 +#define B1100001 97 +#define B01100001 97 +#define B1100010 98 +#define B01100010 98 +#define B1100011 99 +#define B01100011 99 +#define B1100100 100 +#define B01100100 100 +#define B1100101 101 +#define B01100101 101 +#define B1100110 102 +#define B01100110 102 +#define B1100111 103 +#define B01100111 103 +#define B1101000 104 +#define B01101000 104 +#define B1101001 105 +#define B01101001 105 +#define B1101010 106 +#define B01101010 106 +#define B1101011 107 +#define B01101011 107 +#define B1101100 108 +#define B01101100 108 +#define B1101101 109 +#define B01101101 109 +#define B1101110 110 +#define B01101110 110 +#define B1101111 111 +#define B01101111 111 +#define B1110000 112 +#define B01110000 112 +#define B1110001 113 +#define B01110001 113 +#define B1110010 114 +#define B01110010 114 +#define B1110011 115 +#define B01110011 115 +#define B1110100 116 +#define B01110100 116 +#define B1110101 117 +#define B01110101 117 +#define B1110110 118 +#define B01110110 118 +#define B1110111 119 +#define B01110111 119 +#define B1111000 120 +#define B01111000 120 +#define B1111001 121 +#define B01111001 121 +#define B1111010 122 +#define B01111010 122 +#define B1111011 123 +#define B01111011 123 +#define B1111100 124 +#define B01111100 124 +#define B1111101 125 +#define B01111101 125 +#define B1111110 126 +#define B01111110 126 +#define B1111111 127 +#define B01111111 127 +#define B10000000 128 +#define B10000001 129 +#define B10000010 130 +#define B10000011 131 +#define B10000100 132 +#define B10000101 133 +#define B10000110 134 +#define B10000111 135 +#define B10001000 136 +#define B10001001 137 +#define B10001010 138 +#define B10001011 139 +#define B10001100 140 +#define B10001101 141 +#define B10001110 142 +#define B10001111 143 +#define B10010000 144 +#define B10010001 145 +#define B10010010 146 +#define B10010011 147 +#define B10010100 148 +#define B10010101 149 +#define B10010110 150 +#define B10010111 151 +#define B10011000 152 +#define B10011001 153 +#define B10011010 154 +#define B10011011 155 +#define B10011100 156 +#define B10011101 157 +#define B10011110 158 +#define B10011111 159 +#define B10100000 160 +#define B10100001 161 +#define B10100010 162 +#define B10100011 163 +#define B10100100 164 +#define B10100101 165 +#define B10100110 166 +#define B10100111 167 +#define B10101000 168 +#define B10101001 169 +#define B10101010 170 +#define B10101011 171 +#define B10101100 172 +#define B10101101 173 +#define B10101110 174 +#define B10101111 175 +#define B10110000 176 +#define B10110001 177 +#define B10110010 178 +#define B10110011 179 +#define B10110100 180 +#define B10110101 181 +#define B10110110 182 +#define B10110111 183 +#define B10111000 184 +#define B10111001 185 +#define B10111010 186 +#define B10111011 187 +#define B10111100 188 +#define B10111101 189 +#define B10111110 190 +#define B10111111 191 +#define B11000000 192 +#define B11000001 193 +#define B11000010 194 +#define B11000011 195 +#define B11000100 196 +#define B11000101 197 +#define B11000110 198 +#define B11000111 199 +#define B11001000 200 +#define B11001001 201 +#define B11001010 202 +#define B11001011 203 +#define B11001100 204 +#define B11001101 205 +#define B11001110 206 +#define B11001111 207 +#define B11010000 208 +#define B11010001 209 +#define B11010010 210 +#define B11010011 211 +#define B11010100 212 +#define B11010101 213 +#define B11010110 214 +#define B11010111 215 +#define B11011000 216 +#define B11011001 217 +#define B11011010 218 +#define B11011011 219 +#define B11011100 220 +#define B11011101 221 +#define B11011110 222 +#define B11011111 223 +#define B11100000 224 +#define B11100001 225 +#define B11100010 226 +#define B11100011 227 +#define B11100100 228 +#define B11100101 229 +#define B11100110 230 +#define B11100111 231 +#define B11101000 232 +#define B11101001 233 +#define B11101010 234 +#define B11101011 235 +#define B11101100 236 +#define B11101101 237 +#define B11101110 238 +#define B11101111 239 +#define B11110000 240 +#define B11110001 241 +#define B11110010 242 +#define B11110011 243 +#define B11110100 244 +#define B11110101 245 +#define B11110110 246 +#define B11110111 247 +#define B11111000 248 +#define B11111001 249 +#define B11111010 250 +#define B11111011 251 +#define B11111100 252 +#define B11111101 253 +#define B11111110 254 +#define B11111111 255 + +#endif diff --git a/hardware/digistump/sam/cores/digix/cortex_handlers.c b/hardware/digistump/sam/cores/digix/cortex_handlers.c new file mode 100644 index 0000000..bf0a69c --- /dev/null +++ b/hardware/digistump/sam/cores/digix/cortex_handlers.c @@ -0,0 +1,127 @@ +/* + Copyright (c) 2012 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "Arduino.h" +#include "Reset.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static void __halt() { + // Halts + while (1) + ; +} + +extern void svcHook(void); +extern void pendSVHook(void); +extern int sysTickHook(void); + +/* Cortex-M3 core handlers */ +void NMI_Handler (void) __attribute__ ((weak, alias("__halt"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("__halt"))); +void MemManage_Handler (void) __attribute__ ((weak, alias("__halt"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("__halt"))); +void UsageFault_Handler(void) __attribute__ ((weak, alias("__halt"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("__halt"))); +void SVC_Handler (void) { svcHook(); } +void PendSV_Handler (void) { pendSVHook(); } + +void SysTick_Handler(void) +{ + if (sysTickHook()) + return; + + tickReset(); + + // Increment tick count each ms + TimeTick_Increment(); +} + +/* Peripherals handlers */ +void SUPC_Handler (void) __attribute__ ((weak, alias("__halt"))); +void RSTC_Handler (void) __attribute__ ((weak, alias("__halt"))); +void RTC_Handler (void) __attribute__ ((weak, alias("__halt"))); +void RTT_Handler (void) __attribute__ ((weak, alias("__halt"))); +void WDT_Handler (void) __attribute__ ((weak, alias("__halt"))); +void PMC_Handler (void) __attribute__ ((weak, alias("__halt"))); +void EFC0_Handler (void) __attribute__ ((weak, alias("__halt"))); +void EFC1_Handler (void) __attribute__ ((weak, alias("__halt"))); +void UART_Handler (void) __attribute__ ((weak, alias("__halt"))); +#ifdef _SAM3XA_SMC_INSTANCE_ +void SMC_Handler (void) __attribute__ ((weak, alias("__halt"))); +#endif +#ifdef _SAM3XA_SDRAMC_INSTANCE_ +void SDRAMC_Handler (void) __attribute__ ((weak, alias("__halt"))); +#endif +void PIOA_Handler (void) __attribute__ ((weak, alias("__halt"))); +void PIOB_Handler (void) __attribute__ ((weak, alias("__halt"))); +#ifdef _SAM3XA_PIOC_INSTANCE_ +void PIOC_Handler (void) __attribute__ ((weak, alias("__halt"))); +#endif +#ifdef _SAM3XA_PIOD_INSTANCE_ +void PIOD_Handler (void) __attribute__ ((weak, alias("__halt"))); +#endif +#ifdef _SAM3XA_PIOE_INSTANCE_ +void PIOE_Handler (void) __attribute__ ((weak, alias("__halt"))); +#endif +#ifdef _SAM3XA_PIOF_INSTANCE_ +void PIOF_Handler (void) __attribute__ ((weak, alias("__halt"))); +#endif +void USART0_Handler (void) __attribute__ ((weak, alias("__halt"))); +void USART1_Handler (void) __attribute__ ((weak, alias("__halt"))); +void USART2_Handler (void) __attribute__ ((weak, alias("__halt"))); +#ifdef _SAM3XA_USART3_INSTANCE_ +void USART3_Handler (void) __attribute__ ((weak, alias("__halt"))); +#endif +void HSMCI_Handler (void) __attribute__ ((weak, alias("__halt"))); +void TWI0_Handler (void) __attribute__ ((weak, alias("__halt"))); +void TWI1_Handler (void) __attribute__ ((weak, alias("__halt"))); +void SPI0_Handler (void) __attribute__ ((weak, alias("__halt"))); +#ifdef _SAM3XA_SPI1_INSTANCE_ +void SPI1_Handler (void) __attribute__ ((weak, alias("__halt"))); +#endif +void SSC_Handler (void) __attribute__ ((weak, alias("__halt"))); +void TC0_Handler (void) __attribute__ ((weak, alias("__halt"))); +void TC1_Handler (void) __attribute__ ((weak, alias("__halt"))); +void TC2_Handler (void) __attribute__ ((weak, alias("__halt"))); +void TC3_Handler (void) __attribute__ ((weak, alias("__halt"))); +void TC4_Handler (void) __attribute__ ((weak, alias("__halt"))); +void TC5_Handler (void) __attribute__ ((weak, alias("__halt"))); +#ifdef _SAM3XA_TC2_INSTANCE_ +void TC6_Handler (void) __attribute__ ((weak, alias("__halt"))); +void TC7_Handler (void) __attribute__ ((weak, alias("__halt"))); +void TC8_Handler (void) __attribute__ ((weak, alias("__halt"))); +#endif +void PWM_Handler (void) __attribute__ ((weak, alias("__halt"))); +void ADC_Handler (void) __attribute__ ((weak, alias("__halt"))); +void DACC_Handler (void) __attribute__ ((weak, alias("__halt"))); +void DMAC_Handler (void) __attribute__ ((weak, alias("__halt"))); +void UOTGHS_Handler (void) __attribute__ ((weak, alias("__halt"))); +void TRNG_Handler (void) __attribute__ ((weak, alias("__halt"))); +#ifdef _SAM3XA_EMAC_INSTANCE_ +void EMAC_Handler (void) __attribute__ ((weak, alias("__halt"))); +#endif +void CAN0_Handler (void) __attribute__ ((weak, alias("__halt"))); +void CAN1_Handler (void) __attribute__ ((weak, alias("__halt"))); + +#ifdef __cplusplus +} +#endif + diff --git a/hardware/digistump/sam/cores/digix/cxxabi-compat.cpp b/hardware/digistump/sam/cores/digix/cxxabi-compat.cpp new file mode 100644 index 0000000..7370b0b --- /dev/null +++ b/hardware/digistump/sam/cores/digix/cxxabi-compat.cpp @@ -0,0 +1,26 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +extern "C" void __cxa_pure_virtual(void) ; + +/* We compile with nodefaultlibs, so we need to provide an error + * handler for an empty pure virtual function */ +extern "C" void __cxa_pure_virtual(void) { + while(1) + ; +} diff --git a/hardware/digistump/sam/cores/digix/hooks.c b/hardware/digistump/sam/cores/digix/hooks.c new file mode 100644 index 0000000..aa16d11 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/hooks.c @@ -0,0 +1,58 @@ +/* + Copyright (c) 2012 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/** + * Empty yield() hook. + * + * This function is intended to be used by library writers to build + * libraries or sketches that supports cooperative threads. + * + * Its defined as a weak symbol and it can be redefined to implement a + * real cooperative scheduler. + */ +static void __empty() { + // Empty +} +void yield(void) __attribute__ ((weak, alias("__empty"))); + +/** + * SysTick hook + * + * This function is called from SysTick handler, before the default + * handler provided by Arduino. + */ +static int __false() { + // Return false + return 0; +} +int sysTickHook(void) __attribute__ ((weak, alias("__false"))); + +/** + * SVC hook + * PendSV hook + * + * These functions are called from SVC handler, and PensSV handler. + * Default action is halting. + */ +static void __halt() { + // Halts + while (1) + ; +} +void svcHook(void) __attribute__ ((weak, alias("__halt"))); +void pendSVHook(void) __attribute__ ((weak, alias("__halt"))); diff --git a/hardware/digistump/sam/cores/digix/iar_calls_sam3.c b/hardware/digistump/sam/cores/digix/iar_calls_sam3.c new file mode 100644 index 0000000..253f3b0 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/iar_calls_sam3.c @@ -0,0 +1,109 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/** +* \file +* +* Implementation of low level library. +* +*/ + +#if defined __ICCARM__ /* IAR Ewarm 5.41+ */ + +#include "board.h" + +#include +#include +#include +#include +#include + +extern __weak size_t __write( int handle, const unsigned char *buf, size_t bufSize ) +{ + size_t nChars = 0 ; + + /* Check for the command to flush all handles */ + if ( handle == -1 ) + { + return 0 ; + } + + /* Check for stdout and stderr (only necessary if FILE descriptors are enabled.) */ + if ( handle != 1 && handle != 2 ) + { + /* remove warnings */ + return 0xfffffff ; + } + + for ( /* Empty */ ; bufSize > 0 ; --bufSize ) + { + while ( !uart_is_tx_ready(CONSOLE_UART) ) + ; + uart_write( CONSOLE_UART, *buf ) ; + ++buf ; + ++nChars ; + } + + return nChars ; +} + + +extern __weak size_t __read( int handle, unsigned char *buf, size_t bufSize ) +{ + size_t nChars = 0 ; + + /* Check for stdin (only necessary if FILE descriptors are enabled) */ + if ( handle != 0 ) + { + /* remove warnings */ + return 0xfffffff ; + } + + for ( /*Empty*/; bufSize > 0 ; --bufSize ) + { + uint8_t c; + while (uart_read( CONSOLE_UART, &c )) + ; + + if ( c == 0 ) + { + break ; + } + *buf++ = c ; + ++nChars ; + } + + return nChars ; +} + +/** + * \brief Outputs a character on the UART. + * + * \param c Character to output. + * + * \return The character that was output. + */ +extern __weak signed int putchar( signed int c ) +{ + while ( !uart_is_tx_ready(CONSOLE_UART) ) + ; + uart_write( CONSOLE_UART, c ) ; + + return c ; +} +#endif // defined __ICCARM__ diff --git a/hardware/digistump/sam/cores/digix/itoa.c b/hardware/digistump/sam/cores/digix/itoa.c new file mode 100644 index 0000000..fc35766 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/itoa.c @@ -0,0 +1,170 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "itoa.h" +#include + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +#if 0 +/* reverse: reverse string s in place */ +static void reverse( char s[] ) +{ + int i, j ; + char c ; + + for ( i = 0, j = strlen(s)-1 ; i < j ; i++, j-- ) + { + c = s[i] ; + s[i] = s[j] ; + s[j] = c ; + } +} + +/* itoa: convert n to characters in s */ +extern void itoa( int n, char s[] ) +{ + int i, sign ; + + if ( (sign = n) < 0 ) /* record sign */ + { + n = -n; /* make n positive */ + } + + i = 0; + do + { /* generate digits in reverse order */ + s[i++] = n % 10 + '0'; /* get next digit */ + } while ((n /= 10) > 0) ; /* delete it */ + + if (sign < 0 ) + { + s[i++] = '-'; + } + + s[i] = '\0'; + + reverse( s ) ; +} + +#else + +extern char* itoa( int value, char *string, int radix ) +{ + return ltoa( value, string, radix ) ; +} + +extern char* ltoa( long value, char *string, int radix ) +{ + char tmp[33]; + char *tp = tmp; + long i; + unsigned long v; + int sign; + char *sp; + + if ( string == NULL ) + { + return 0 ; + } + + if (radix > 36 || radix <= 1) + { + return 0 ; + } + + sign = (radix == 10 && value < 0); + if (sign) + { + v = -value; + } + else + { + v = (unsigned long)value; + } + + while (v || tp == tmp) + { + i = v % radix; + v = v / radix; + if (i < 10) + *tp++ = i+'0'; + else + *tp++ = i + 'a' - 10; + } + + sp = string; + + if (sign) + *sp++ = '-'; + while (tp > tmp) + *sp++ = *--tp; + *sp = 0; + + return string; +} + +extern char* utoa( unsigned long value, char *string, int radix ) +{ + return ultoa( value, string, radix ) ; +} + +extern char* ultoa( unsigned long value, char *string, int radix ) +{ + char tmp[33]; + char *tp = tmp; + long i; + unsigned long v = value; + char *sp; + + if ( string == NULL ) + { + return 0; + } + + if (radix > 36 || radix <= 1) + { + return 0; + } + + while (v || tp == tmp) + { + i = v % radix; + v = v / radix; + if (i < 10) + *tp++ = i+'0'; + else + *tp++ = i + 'a' - 10; + } + + sp = string; + + + while (tp > tmp) + *sp++ = *--tp; + *sp = 0; + + return string; +} +#endif /* 0 */ + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus diff --git a/hardware/digistump/sam/cores/digix/itoa.h b/hardware/digistump/sam/cores/digix/itoa.h new file mode 100644 index 0000000..59af109 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/itoa.h @@ -0,0 +1,42 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _ITOA_ +#define _ITOA_ + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +#if 0 + +extern void itoa( int n, char s[] ) ; + +#else + +extern char* itoa( int value, char *string, int radix ) ; +extern char* ltoa( long value, char *string, int radix ) ; +extern char* utoa( unsigned long value, char *string, int radix ) ; +extern char* ultoa( unsigned long value, char *string, int radix ) ; +#endif /* 0 */ + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // _ITOA_ diff --git a/hardware/digistump/sam/cores/digix/main.cpp b/hardware/digistump/sam/cores/digix/main.cpp new file mode 100644 index 0000000..f28b6fd --- /dev/null +++ b/hardware/digistump/sam/cores/digix/main.cpp @@ -0,0 +1,55 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#define ARDUINO_MAIN +#include "Arduino.h" + +/* + * Cortex-M3 Systick IT handler + */ +/* +extern void SysTick_Handler( void ) +{ + // Increment tick count each ms + TimeTick_Increment() ; +} +*/ + +/* + * \brief Main entry point of Arduino application + */ +int main( void ) +{ + init(); + + delay(1); + +#if defined(USBCON) + USBDevice.attach(); +#endif + + setup(); + + for (;;) + { + loop(); + if (serialEventRun) serialEventRun(); + } + + return 0; +} diff --git a/hardware/digistump/sam/cores/digix/syscalls.h b/hardware/digistump/sam/cores/digix/syscalls.h new file mode 100644 index 0000000..845b4b5 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/syscalls.h @@ -0,0 +1,60 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/** + * \file syscalls.h + * + * Implementation of newlib syscall. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include +#include +#include +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +#ifdef __cplusplus +extern "C" { +#endif + +extern caddr_t _sbrk( int incr ) ; + +extern int link( char *cOld, char *cNew ) ; + +extern int _close( int file ) ; + +extern int _fstat( int file, struct stat *st ) ; + +extern int _isatty( int file ) ; + +extern int _lseek( int file, int ptr, int dir ) ; + +extern int _read(int file, char *ptr, int len) ; + +extern int _write( int file, char *ptr, int len ) ; + +#ifdef __cplusplus +} +#endif + diff --git a/hardware/digistump/sam/cores/digix/syscalls_sam3.c b/hardware/digistump/sam/cores/digix/syscalls_sam3.c new file mode 100644 index 0000000..23256db --- /dev/null +++ b/hardware/digistump/sam/cores/digix/syscalls_sam3.c @@ -0,0 +1,140 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/** + * \file syscalls_sam3.c + * + * Implementation of newlib syscall. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + + +#include "syscalls.h" + +#include +#include +#include "sam.h" +#if defined ( __GNUC__ ) /* GCC CS3 */ + #include + #include +#endif + +/*---------------------------------------------------------------------------- + * Exported variables + *----------------------------------------------------------------------------*/ + +#undef errno +extern int errno ; +extern int _end ; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void _exit( int status ) ; +extern void _kill( int pid, int sig ) ; +extern int _getpid ( void ) ; + +extern caddr_t _sbrk ( int incr ) +{ + static unsigned char *heap = NULL ; + unsigned char *prev_heap ; + + if ( heap == NULL ) + { + heap = (unsigned char *)&_end ; + } + prev_heap = heap; + + heap += incr ; + + return (caddr_t) prev_heap ; +} + +extern int link( char *cOld, char *cNew ) +{ + return -1 ; +} + +extern int _close( int file ) +{ + return -1 ; +} + +extern int _fstat( int file, struct stat *st ) +{ + st->st_mode = S_IFCHR ; + + return 0 ; +} + +extern int _isatty( int file ) +{ + return 1 ; +} + +extern int _lseek( int file, int ptr, int dir ) +{ + return 0 ; +} + +extern int _read(int file, char *ptr, int len) +{ + return 0 ; +} + +extern int _write( int file, char *ptr, int len ) +{ + int iIndex ; + + +// for ( ; *ptr != 0 ; ptr++ ) + for ( iIndex=0 ; iIndex < len ; iIndex++, ptr++ ) + { +// UART_PutChar( *ptr ) ; + + // Check if the transmitter is ready + while ((UART->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY) + ; + + // Send character + UART->UART_THR = *ptr; + } + + return iIndex ; +} + +extern void _exit( int status ) +{ + printf( "Exiting with status %d.\n", status ) ; + + for ( ; ; ) ; +} + +extern void _kill( int pid, int sig ) +{ + return ; +} + +extern int _getpid ( void ) +{ + return -1 ; +} diff --git a/hardware/digistump/sam/cores/digix/wiring.c b/hardware/digistump/sam/cores/digix/wiring.c new file mode 100644 index 0000000..02fd04a --- /dev/null +++ b/hardware/digistump/sam/cores/digix/wiring.c @@ -0,0 +1,99 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "Arduino.h" + +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t millis( void ) +{ +// todo: ensure no interrupts + return GetTickCount() ; +} + +// Interrupt-compatible version of micros +// Theory: repeatedly take readings of SysTick counter, millis counter and SysTick interrupt pending flag. +// When it appears that millis counter and pending is stable and SysTick hasn't rolled over, use these +// values to calculate micros. If there is a pending SysTick, add one to the millis counter in the calculation. +uint32_t micros( void ) +{ + uint32_t ticks, ticks2; + uint32_t pend, pend2; + uint32_t count, count2; + + ticks2 = SysTick->VAL; + pend2 = !!((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk)||((SCB->SHCSR & SCB_SHCSR_SYSTICKACT_Msk))) ; + count2 = GetTickCount(); + + do { + ticks=ticks2; + pend=pend2; + count=count2; + ticks2 = SysTick->VAL; + pend2 = !!((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk)||((SCB->SHCSR & SCB_SHCSR_SYSTICKACT_Msk))) ; + count2 = GetTickCount(); + } while ((pend != pend2) || (count != count2) || (ticks < ticks2)); + + return ((count+pend) * 1000) + (((SysTick->LOAD - ticks)*(1048576/(F_CPU/1000000)))>>20) ; + // this is an optimization to turn a runtime division into two compile-time divisions and + // a runtime multiplication and shift, saving a few cycles +} + +// original function: +// uint32_t micros( void ) +// { +// uint32_t ticks ; +// uint32_t count ; +// +// SysTick->CTRL; +// do { +// ticks = SysTick->VAL; +// count = GetTickCount(); +// } while (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk); +// +// return count * 1000 + (SysTick->LOAD + 1 - ticks) / (SystemCoreClock/1000000) ; +// } + + +void delay( uint32_t ms ) +{ + uint32_t end = GetTickCount() + ms; + while (GetTickCount() < end) + yield(); +} + +#if defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ +extern signed int putchar( signed int c ) ; +/** + * \brief + * + * \param c Character to output. + * + * \return The character that was output. + */ +extern WEAK signed int putchar( signed int c ) +{ + return c ; +} +#endif /* __ICCARM__ */ + +#ifdef __cplusplus +} +#endif diff --git a/hardware/digistump/sam/cores/digix/wiring.h b/hardware/digistump/sam/cores/digix/wiring.h new file mode 100644 index 0000000..3c58cf0 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/wiring.h @@ -0,0 +1,80 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_ +#define _WIRING_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * + */ +extern void init( void ) ; + +/** + * \brief Returns the number of milliseconds since the Arduino board began running the current program. + * + * This number will overflow (go back to zero), after approximately 50 days. + * + * \return Number of milliseconds since the program started (uint32_t) + */ +extern uint32_t millis( void ) ; + +/** + * \brief Returns the number of microseconds since the Arduino board began running the current program. + * + * This number will overflow (go back to zero), after approximately 70 minutes. On 16 MHz Arduino boards + * (e.g. Duemilanove and Nano), this function has a resolution of four microseconds (i.e. the value returned is + * always a multiple of four). On 8 MHz Arduino boards (e.g. the LilyPad), this function has a resolution + * of eight microseconds. + * + * \note There are 1,000 microseconds in a millisecond and 1,000,000 microseconds in a second. + */ +extern uint32_t micros( void ) ; + +/** + * \brief Pauses the program for the amount of time (in miliseconds) specified as parameter. + * (There are 1000 milliseconds in a second.) + * + * \param dwMs the number of milliseconds to pause (uint32_t) + */ +extern void delay( uint32_t dwMs ) ; + +/** + * \brief Pauses the program for the amount of time (in microseconds) specified as parameter. + * + * \param dwUs the number of microseconds to pause (uint32_t) + */ +static inline void delayMicroseconds(uint32_t) __attribute__((always_inline, unused)); +static inline void delayMicroseconds(uint32_t usec){ + uint32_t n = usec * (VARIANT_MCK / 3000000); + asm volatile( + "L_%=_delayMicroseconds:" "\n\t" + "subs %0, #1" "\n\t" + "bge L_%=_delayMicroseconds" "\n" + : "+r" (n) : + ); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _WIRING_ */ diff --git a/hardware/digistump/sam/cores/digix/wiring_analog.c b/hardware/digistump/sam/cores/digix/wiring_analog.c new file mode 100644 index 0000000..97f50e8 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/wiring_analog.c @@ -0,0 +1,353 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Arduino.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static int _readResolution = 10; +static int _writeResolution = 8; + +void analogReadResolution(int res) { + _readResolution = res; +} + +void analogWriteResolution(int res) { + _writeResolution = res; +} + +static inline uint32_t mapResolution(uint32_t value, uint32_t from, uint32_t to) { + if (from == to) + return value; + if (from > to) + return value >> (from-to); + else + return value << (to-from); +} + +eAnalogReference analog_reference = AR_DEFAULT; + +void analogReference(eAnalogReference ulMode) +{ + analog_reference = ulMode; +} + +uint32_t analogRead(uint32_t ulPin) +{ + uint32_t ulValue = 0; + uint32_t ulChannel; + + if (ulPin < A0) + ulPin += A0; + + ulChannel = g_APinDescription[ulPin].ulADCChannelNumber ; + +#if defined __SAM3U4E__ + switch ( g_APinDescription[ulPin].ulAnalogChannel ) + { + // Handling ADC 10 bits channels + case ADC0 : + case ADC1 : + case ADC2 : + case ADC3 : + case ADC4 : + case ADC5 : + case ADC6 : + case ADC7 : + // Enable the corresponding channel + adc_enable_channel( ADC, ulChannel ); + + // Start the ADC + adc_start( ADC ); + + // Wait for end of conversion + while ((adc_get_status(ADC) & ADC_SR_DRDY) != ADC_SR_DRDY) + ; + + // Read the value + ulValue = adc_get_latest_value(ADC); + ulValue = mapResolution(ulValue, 10, _readResolution); + + // Disable the corresponding channel + adc_disable_channel( ADC, ulChannel ); + + // Stop the ADC + // adc_stop( ADC ) ; // never do adc_stop() else we have to reconfigure the ADC each time + break; + + // Handling ADC 12 bits channels + case ADC8 : + case ADC9 : + case ADC10 : + case ADC11 : + case ADC12 : + case ADC13 : + case ADC14 : + case ADC15 : + // Enable the corresponding channel + adc12b_enable_channel( ADC12B, ulChannel ); + + // Start the ADC12B + adc12b_start( ADC12B ); + + // Wait for end of conversion + while ((adc12b_get_status(ADC12B) & ADC12B_SR_DRDY) != ADC12B_SR_DRDY) + ; + + // Read the value + ulValue = adc12b_get_latest_value(ADC12B) >> 2; + ulValue = mapResolution(ulValue, 12, _readResolution); + + // Stop the ADC12B + // adc12_stop( ADC12B ) ; // never do adc12_stop() else we have to reconfigure the ADC12B each time + + // Disable the corresponding channel + adc12b_disable_channel( ADC12B, ulChannel ); + break; + + // Compiler could yell because we don't handle DAC pins + default : + ulValue=0; + break; + } +#endif + +#if defined __SAM3X8E__ || defined __SAM3X8H__ + switch ( g_APinDescription[ulPin].ulAnalogChannel ) + { + // Handling ADC 12 bits channels + case ADC0 : + case ADC1 : + case ADC2 : + case ADC3 : + case ADC4 : + case ADC5 : + case ADC6 : + case ADC7 : + case ADC8 : + case ADC9 : + case ADC10 : + case ADC11 : + + // Enable the corresponding channel + adc_enable_channel( ADC, ulChannel ); + + // Start the ADC + adc_start( ADC ); + + // Wait for end of conversion + while ((adc_get_status(ADC) & ADC_ISR_DRDY) != ADC_ISR_DRDY) + ; + + // Read the value + ulValue = adc_get_latest_value(ADC); + ulValue = mapResolution(ulValue, ADC_RESOLUTION, _readResolution); + + // Disable the corresponding channel + adc_disable_channel(ADC, ulChannel); + + break; + + // Compiler could yell because we don't handle DAC pins + default : + ulValue=0; + break; + } +#endif + + return ulValue; +} + +static void TC_SetCMR_ChannelA(Tc *tc, uint32_t chan, uint32_t v) +{ + tc->TC_CHANNEL[chan].TC_CMR = (tc->TC_CHANNEL[chan].TC_CMR & 0xFFF0FFFF) | v; +} + +static void TC_SetCMR_ChannelB(Tc *tc, uint32_t chan, uint32_t v) +{ + tc->TC_CHANNEL[chan].TC_CMR = (tc->TC_CHANNEL[chan].TC_CMR & 0xF0FFFFFF) | v; +} + +static uint8_t PWMEnabled = 0; +static uint8_t pinEnabled[PINS_COUNT]; +static uint8_t TCChanEnabled[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; + +void analogOutputInit(void) { + uint8_t i; + for (i=0; i 0..TC + ulValue = mapResolution(ulValue, _writeResolution, TC_RESOLUTION); + ulValue = ulValue * TC; + ulValue = ulValue / TC_MAX_DUTY_CYCLE; + + // Setup Timer for this pin + ETCChannel channel = g_APinDescription[ulPin].ulTCChannel; + static const uint32_t channelToChNo[] = { 0, 0, 1, 1, 2, 2, 0, 0, 1, 1, 2, 2, 0, 0, 1, 1, 2, 2 }; + static const uint32_t channelToAB[] = { 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0 }; + static const Tc *channelToTC[] = { + TC0, TC0, TC0, TC0, TC0, TC0, + TC1, TC1, TC1, TC1, TC1, TC1, + TC2, TC2, TC2, TC2, TC2, TC2 }; + static const uint32_t channelToId[] = { 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8 }; + uint32_t chNo = channelToChNo[channel]; + uint32_t chA = channelToAB[channel]; + Tc *chTC = channelToTC[channel]; + uint32_t interfaceID = channelToId[channel]; + + if (!TCChanEnabled[interfaceID]) { + pmc_enable_periph_clk(TC_INTERFACE_ID + interfaceID); + TC_Configure(chTC, chNo, + TC_CMR_TCCLKS_TIMER_CLOCK1 | + TC_CMR_WAVE | // Waveform mode + TC_CMR_WAVSEL_UP_RC | // Counter running up and reset when equals to RC + TC_CMR_EEVT_XC0 | // Set external events from XC0 (this setup TIOB as output) + TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_CLEAR | + TC_CMR_BCPB_CLEAR | TC_CMR_BCPC_CLEAR); + TC_SetRC(chTC, chNo, TC); + } + if (ulValue == 0) { + if (chA) + TC_SetCMR_ChannelA(chTC, chNo, TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_CLEAR); + else + TC_SetCMR_ChannelB(chTC, chNo, TC_CMR_BCPB_CLEAR | TC_CMR_BCPC_CLEAR); + } else { + if (chA) { + TC_SetRA(chTC, chNo, ulValue); + TC_SetCMR_ChannelA(chTC, chNo, TC_CMR_ACPA_CLEAR | TC_CMR_ACPC_SET); + } else { + TC_SetRB(chTC, chNo, ulValue); + TC_SetCMR_ChannelB(chTC, chNo, TC_CMR_BCPB_CLEAR | TC_CMR_BCPC_SET); + } + } + if (!pinEnabled[ulPin]) { + PIO_Configure(g_APinDescription[ulPin].pPort, + g_APinDescription[ulPin].ulPinType, + g_APinDescription[ulPin].ulPin, + g_APinDescription[ulPin].ulPinConfiguration); + pinEnabled[ulPin] = 1; + } + if (!TCChanEnabled[interfaceID]) { + TC_Start(chTC, chNo); + TCChanEnabled[interfaceID] = 1; + } + return; + } + + // Defaults to digital write + pinMode(ulPin, OUTPUT); + ulValue = mapResolution(ulValue, _writeResolution, 8); + if (ulValue < 128) + digitalWrite(ulPin, LOW); + else + digitalWrite(ulPin, HIGH); +} + +#ifdef __cplusplus +} +#endif diff --git a/hardware/digistump/sam/cores/digix/wiring_analog.h b/hardware/digistump/sam/cores/digix/wiring_analog.h new file mode 100644 index 0000000..ce732b2 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/wiring_analog.h @@ -0,0 +1,79 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_ANALOG_ +#define _WIRING_ANALOG_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief SAM3 products have only one reference for ADC + */ +typedef enum _eAnalogReference +{ + AR_DEFAULT, +} eAnalogReference ; + +/* + * \brief Configures the reference voltage used for analog input (i.e. the value used as the top of the input range). + * This function is kept only for compatibility with existing AVR based API. + * + * \param ulMmode Should be set to AR_DEFAULT. + */ +extern void analogReference( eAnalogReference ulMode ) ; + +/* + * \brief Writes an analog value (PWM wave) to a pin. + * + * \param ulPin + * \param ulValue + */ +extern void analogWrite( uint32_t ulPin, uint32_t ulValue ) ; + +/* + * \brief Reads the value from the specified analog pin. + * + * \param ulPin + * + * \return Read value from selected pin, if no error. + */ +extern uint32_t analogRead( uint32_t ulPin ) ; + +/* + * \brief Set the resolution of analogRead return values. Default is 10 bits (range from 0 to 1023). + * + * \param res + */ +extern void analogReadResolution(int res); + +/* + * \brief Set the resolution of analogWrite parameters. Default is 8 bits (range from 0 to 255). + * + * \param res + */ +extern void analogWriteResolution(int res); + +extern void analogOutputInit( void ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* _WIRING_ANALOG_ */ diff --git a/hardware/digistump/sam/cores/digix/wiring_constants.h b/hardware/digistump/sam/cores/digix/wiring_constants.h new file mode 100644 index 0000000..80f015d --- /dev/null +++ b/hardware/digistump/sam/cores/digix/wiring_constants.h @@ -0,0 +1,103 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_CONSTANTS_ +#define _WIRING_CONSTANTS_ + +#ifdef __cplusplus +extern "C"{ +#endif // __cplusplus + +#define HIGH 0x1 +#define LOW 0x0 + +#define INPUT 0x0 +#define OUTPUT 0x1 +#define INPUT_PULLUP 0x2 + +#define true 0x1 +#define false 0x0 + +#define PI 3.1415926535897932384626433832795 +#define HALF_PI 1.5707963267948966192313216916398 +#define TWO_PI 6.283185307179586476925286766559 +#define DEG_TO_RAD 0.017453292519943295769236907684886 +#define RAD_TO_DEG 57.295779513082320876798154814105 + +#define SERIAL 0x0 +#define DISPLAY 0x1 + +enum BitOrder { + LSBFIRST = 0, + MSBFIRST = 1 +}; + +// LOW 0 +// HIGH 1 +#define CHANGE 2 +#define FALLING 3 +#define RISING 4 + +#define DEFAULT 1 +#define EXTERNAL 0 + +// undefine stdlib's abs if encountered +#ifdef abs +#undef abs +#endif // abs + +#ifndef min +#define min(a,b) ((a)<(b)?(a):(b)) +#endif // min + +#ifndef max +#define max(a,b) ((a)>(b)?(a):(b)) +#endif // max + +#define abs(x) ((x)>0?(x):-(x)) +#define constrain(amt,low,high) ((amt)<(low)?(low):((amt)>(high)?(high):(amt))) +#define round(x) ((x)>=0?(long)((x)+0.5):(long)((x)-0.5)) +#define radians(deg) ((deg)*DEG_TO_RAD) +#define degrees(rad) ((rad)*RAD_TO_DEG) +#define sq(x) ((x)*(x)) + +#define interrupts() __enable_irq() +#define noInterrupts() __disable_irq() + +#define lowByte(w) ((uint8_t) ((w) & 0xff)) +#define highByte(w) ((uint8_t) ((w) >> 8)) + +#define bitRead(value, bit) (((value) >> (bit)) & 0x01) +#define bitSet(value, bit) ((value) |= (1UL << (bit))) +#define bitClear(value, bit) ((value) &= ~(1UL << (bit))) +#define bitWrite(value, bit, bitvalue) (bitvalue ? bitSet(value, bit) : bitClear(value, bit)) + +typedef unsigned int word; + +#define bit(b) (1UL << (b)) + +// TODO: to be checked +typedef uint8_t boolean ; +typedef uint8_t byte ; + + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif /* _WIRING_CONSTANTS_ */ diff --git a/hardware/digistump/sam/cores/digix/wiring_digital.c b/hardware/digistump/sam/cores/digix/wiring_digital.c new file mode 100644 index 0000000..7c958de --- /dev/null +++ b/hardware/digistump/sam/cores/digix/wiring_digital.c @@ -0,0 +1,109 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "Arduino.h" + +#ifdef __cplusplus + extern "C" { +#endif + +extern void pinMode( uint32_t ulPin, uint32_t ulMode ) +{ + if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN ) + { + return ; + } + + switch ( ulMode ) + { + case INPUT: + /* Enable peripheral for clocking input */ + pmc_enable_periph_clk( g_APinDescription[ulPin].ulPeripheralId ) ; + PIO_Configure( + g_APinDescription[ulPin].pPort, + PIO_INPUT, + g_APinDescription[ulPin].ulPin, + 0 ) ; + break ; + + case INPUT_PULLUP: + /* Enable peripheral for clocking input */ + pmc_enable_periph_clk( g_APinDescription[ulPin].ulPeripheralId ) ; + PIO_Configure( + g_APinDescription[ulPin].pPort, + PIO_INPUT, + g_APinDescription[ulPin].ulPin, + PIO_PULLUP ) ; + break ; + + case OUTPUT: + PIO_Configure( + g_APinDescription[ulPin].pPort, + PIO_OUTPUT_1, + g_APinDescription[ulPin].ulPin, + g_APinDescription[ulPin].ulPinConfiguration ) ; + + /* if all pins are output, disable PIO Controller clocking, reduce power consumption */ + if ( g_APinDescription[ulPin].pPort->PIO_OSR == 0xffffffff ) + { + pmc_disable_periph_clk( g_APinDescription[ulPin].ulPeripheralId ) ; + } + break ; + + default: + break ; + } +} + +extern void digitalWrite( uint32_t ulPin, uint32_t ulVal ) +{ + /* Handle */ + if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN ) + { + return ; + } + + if ( PIO_GetOutputDataStatus( g_APinDescription[ulPin].pPort, g_APinDescription[ulPin].ulPin ) == 0 ) + { + PIO_PullUp( g_APinDescription[ulPin].pPort, g_APinDescription[ulPin].ulPin, ulVal ) ; + } + else + { + PIO_SetOutput( g_APinDescription[ulPin].pPort, g_APinDescription[ulPin].ulPin, ulVal, 0, PIO_PULLUP ) ; + } +} + +extern int digitalRead( uint32_t ulPin ) +{ + if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN ) + { + return LOW ; + } + + if ( PIO_Get( g_APinDescription[ulPin].pPort, PIO_INPUT, g_APinDescription[ulPin].ulPin ) == 1 ) + { + return HIGH ; + } + + return LOW ; +} + +#ifdef __cplusplus +} +#endif + diff --git a/hardware/digistump/sam/cores/digix/wiring_digital.h b/hardware/digistump/sam/cores/digix/wiring_digital.h new file mode 100644 index 0000000..4499024 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/wiring_digital.h @@ -0,0 +1,69 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_DIGITAL_ +#define _WIRING_DIGITAL_ + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * \brief Configures the specified pin to behave either as an input or an output. See the description of digital pins for details. + * + * \param ulPin The number of the pin whose mode you wish to set + * \param ulMode Either INPUT or OUTPUT + */ +extern void pinMode( uint32_t dwPin, uint32_t dwMode ) ; + +/** + * \brief Write a HIGH or a LOW value to a digital pin. + * + * If the pin has been configured as an OUTPUT with pinMode(), its voltage will be set to the + * corresponding value: 5V (or 3.3V on 3.3V boards) for HIGH, 0V (ground) for LOW. + * + * If the pin is configured as an INPUT, writing a HIGH value with digitalWrite() will enable an internal + * 20K pullup resistor (see the tutorial on digital pins). Writing LOW will disable the pullup. The pullup + * resistor is enough to light an LED dimly, so if LEDs appear to work, but very dimly, this is a likely + * cause. The remedy is to set the pin to an output with the pinMode() function. + * + * \note Digital pin PIN_LED is harder to use as a digital input than the other digital pins because it has an LED + * and resistor attached to it that's soldered to the board on most boards. If you enable its internal 20k pull-up + * resistor, it will hang at around 1.7 V instead of the expected 5V because the onboard LED and series resistor + * pull the voltage level down, meaning it always returns LOW. If you must use pin PIN_LED as a digital input, use an + * external pull down resistor. + * + * \param dwPin the pin number + * \param dwVal HIGH or LOW + */ +extern void digitalWrite( uint32_t dwPin, uint32_t dwVal ) ; + +/** + * \brief Reads the value from a specified digital pin, either HIGH or LOW. + * + * \param ulPin The number of the digital pin you want to read (int) + * + * \return HIGH or LOW + */ +extern int digitalRead( uint32_t ulPin ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* _WIRING_DIGITAL_ */ diff --git a/hardware/digistump/sam/cores/digix/wiring_private.h b/hardware/digistump/sam/cores/digix/wiring_private.h new file mode 100644 index 0000000..573da03 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/wiring_private.h @@ -0,0 +1,42 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef WiringPrivate_h +#define WiringPrivate_h + +#include +#include +#include + +#ifdef __cplusplus +extern "C"{ +#endif + +// Includes Atmel CMSIS +#include + +#include "wiring_constants.h" + +#ifdef __cplusplus +} // extern "C" + +#include "HardwareSerial.h" + +#endif + +#endif diff --git a/hardware/digistump/sam/cores/digix/wiring_pulse.cpp b/hardware/digistump/sam/cores/digix/wiring_pulse.cpp new file mode 100644 index 0000000..bf250ff --- /dev/null +++ b/hardware/digistump/sam/cores/digix/wiring_pulse.cpp @@ -0,0 +1,61 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "Arduino.h" +#include "wiring_private.h" + +/* Measures the length (in microseconds) of a pulse on the pin; state is HIGH + * or LOW, the type of pulse to measure. Works on pulses from 2-3 microseconds + * to 3 minutes in length, but must be called at least a few dozen microseconds + * before the start of the pulse. */ +extern uint32_t pulseIn( uint32_t pin, uint32_t state, uint32_t timeout ) +{ + // cache the port and bit of the pin in order to speed up the + // pulse width measuring loop and achieve finer resolution. calling + // digitalRead() instead yields much coarser resolution. + PinDescription p = g_APinDescription[pin]; + uint32_t width = 0; // keep initialization out of time critical area + + // convert the timeout from microseconds to a number of times through + // the initial loop; it takes 22 clock cycles per iteration. + uint32_t numloops = 0; + uint32_t maxloops = microsecondsToClockCycles(timeout) / 22; + + // wait for any previous pulse to end + while (PIO_Get(p.pPort, PIO_INPUT, p.ulPin) == state) + if (numloops++ == maxloops) + return 0; + + // wait for the pulse to start + while (PIO_Get(p.pPort, PIO_INPUT, p.ulPin) != state) + if (numloops++ == maxloops) + return 0; + + // wait for the pulse to stop + while (PIO_Get(p.pPort, PIO_INPUT, p.ulPin) == state) { + if (numloops++ == maxloops) + return 0; + width++; + } + + // convert the reading to microseconds. The loop has been determined + // to be 52 clock cycles long and have about 16 clocks between the edge + // and the start of the loop. There will be some error introduced by + // the interrupt handlers. + return clockCyclesToMicroseconds(width * 52 + 16); +} diff --git a/hardware/digistump/sam/cores/digix/wiring_pulse.h b/hardware/digistump/sam/cores/digix/wiring_pulse.h new file mode 100644 index 0000000..f328969 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/wiring_pulse.h @@ -0,0 +1,39 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_PULSE_ +#define _WIRING_PULSE_ + +#ifdef __cplusplus + extern "C" { +#endif + +/* + * \brief Measures the length (in microseconds) of a pulse on the pin; state is HIGH + * or LOW, the type of pulse to measure. Works on pulses from 2-3 microseconds + * to 3 minutes in length, but must be called at least a few dozen microseconds + * before the start of the pulse. + */ +extern uint32_t pulseIn( uint32_t ulPin, uint32_t ulState, uint32_t ulTimeout = 1000000L ) ; + + +#ifdef __cplusplus +} +#endif + +#endif /* _WIRING_PULSE_ */ diff --git a/hardware/digistump/sam/cores/digix/wiring_shift.c b/hardware/digistump/sam/cores/digix/wiring_shift.c new file mode 100644 index 0000000..302f0b5 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/wiring_shift.c @@ -0,0 +1,71 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "Arduino.h" + +#ifdef __cplusplus +extern "C"{ +#endif + +uint32_t shiftIn( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder ) +{ + uint8_t value = 0 ; + uint8_t i ; + + for ( i=0 ; i < 8 ; ++i ) + { + digitalWrite( ulClockPin, HIGH ) ; + + if ( ulBitOrder == LSBFIRST ) + { + value |= digitalRead( ulDataPin ) << i ; + } + else + { + value |= digitalRead( ulDataPin ) << (7 - i) ; + } + + digitalWrite( ulClockPin, LOW ) ; + } + + return value ; +} + +void shiftOut( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder, uint32_t ulVal ) +{ + uint8_t i ; + + for ( i=0 ; i < 8 ; i++ ) + { + if ( ulBitOrder == LSBFIRST ) + { + digitalWrite( ulDataPin, !!(ulVal & (1 << i)) ) ; + } + else + { + digitalWrite( ulDataPin, !!(ulVal & (1 << (7 - i))) ) ; + } + + digitalWrite( ulClockPin, HIGH ) ; + digitalWrite( ulClockPin, LOW ) ; + } +} + +#ifdef __cplusplus +} // extern "C" +#endif diff --git a/hardware/digistump/sam/cores/digix/wiring_shift.h b/hardware/digistump/sam/cores/digix/wiring_shift.h new file mode 100644 index 0000000..f33d848 --- /dev/null +++ b/hardware/digistump/sam/cores/digix/wiring_shift.h @@ -0,0 +1,42 @@ +/* + Copyright (c) 2011 Arduino. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef _WIRING_SHIFT_ +#define _WIRING_SHIFT_ + +#ifdef __cplusplus + extern "C" { +#endif + +/* + * \brief + */ +extern uint32_t shiftIn( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder ) ; + + +/* + * \brief + */ +extern void shiftOut( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder, uint32_t ulVal ) ; + + +#ifdef __cplusplus +} +#endif + +#endif /* _WIRING_SHIFT_ */ diff --git a/hardware/digistump/sam/libraries/DigiFi/DigiFi.cpp b/hardware/digistump/sam/libraries/DigiFi/DigiFi.cpp new file mode 100644 index 0000000..c94b99c --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/DigiFi.cpp @@ -0,0 +1,1216 @@ +// DigiX WiFi module example - released by Digistump LLC/Erik Kettenburg under CC-BY-SA 3.0 + +#include "DigiFi.h" + +#define DEBUG + + bool digiFiDebugState = false; + uint8_t digiFiMode = TCP; + bool digiFiServer = false; + uint32_t digiFiActivityTimeout = 0; + +DigiFi::DigiFi() +{ + +} + +/* Stream Implementation */ +int DigiFi::available( void ) +{ + uint8_t available = Serial1.available(); + if(available>0) + digiFiActivityTimeout = millis() +1000; + return available; +} +int DigiFi::peek( void ) +{ + return Serial1.peek(); +} +int DigiFi::read( void ) +{ + return Serial1.read(); +} +int DigiFi::read(uint8_t *buf, size_t size) +{ + return Serial1.readBytes((char*)buf,size); +} +void DigiFi::flush( void ) +{ + return Serial1.flush(); +} +void DigiFi::stop( void ) +{ + startATMode(); + setTCPConn("off"); + endATMode(); +} +void DigiFi::setFlowControl( boolean en ) +{ + Serial1.setCTSPin(DIGIFI_CTS); + Serial1.enableCTS(en); +} +size_t DigiFi::write( const uint8_t c ) +{ + + digiFiActivityTimeout = millis() + (requestTimeout*1000); + return Serial1.write(c); +} +size_t DigiFi::write(const uint8_t *buf, size_t size) +{ + digiFiActivityTimeout = millis() + (requestTimeout*1000); + return Serial1.write(buf,size); +} +void DigiFi::closeChunk() +{ + Serial1.println('0'); + Serial1.println(); +} + +void DigiFi::printChunk(int str) +{ + printChunk(String(str)); +} +void DigiFi::printChunk(long str) +{ + printChunk(String(str)); +} +void DigiFi::printChunk(const char *str) +{ + printChunk(String(str)); +} +void DigiFi::printChunk(String str) +{ + Serial1.println(str.length()+2,HEX); + Serial1.println(str); + Serial1.println(); +} + + + + +DigiFi::operator bool() { + return Serial1; +} + +void DigiFi::begin(int aBaud, bool en) +{ + setFlowControl(en); + Serial1.begin(aBaud); + + /** / + //Enable USART HW Flow Control + USART0->US_MR |= US_MR_USART_MODE_HW_HANDSHAKING; + + //Disable PIO Control of URTS pin + PIOB->PIO_ABSR |= (0u << 25); + PIOB->PIO_PDR |= PIO_PB25A_RTS0; + + //Disable PIO Control of UCTS pin + PIOB->PIO_ABSR |= (0u << 26); + PIOB->PIO_PDR |= PIO_PB26A_CTS0; + + //Disable PIO Control of WRTS pin + PIOC->PIO_ABSR |= (0u << 27); + PIOC->PIO_PDR |= (1u << 27); + + //Disable PIO Control of WCTS pin + PIOC->PIO_ABSR |= (0u << 20); + PIOC->PIO_PDR |= (1u << 20); + /**/ + while(Serial1.available()){Serial1.read();} +} +void DigiFi::startATMode() +{ + bool ATsuccess = false; + // ensure the module properly acknowledges + // our request for AT mode. Otherwise retry. + int retries = 0; // TODO: make constant + do { + if (retries > 5) { + debug("Retried 5 times, bailing"); + // need to change return-types perhaps to + // trigger some kind of reset higher up. + return; + } + ATsuccess = startATSequence(); + retries += 1; + } while (!ATsuccess); + debug("Send client acknowledge AT mode"); + Serial1.print("a"); + debug(readResponse(0)); + debug("echo off"); + Serial1.print("AT+E\r"); + debug(readResponse(0)); +} +bool DigiFi::startATSequence(){ + //silly init sequence for wifi module + delay(50); // changed from 100 + // clear the incoming buffer + while(Serial1.available()){Serial1.read();} + debug("start at mode"); + debug("next"); + Serial1.write("+++"); + debug("wait for a"); + // there's a ~4s (see datasheet for newer G2 module) + // time within which the handshake must complete + // if time is longer than that, it's failed. + // TODO: turn the timeout into a constant + unsigned long timeout = millis() + (4*1000); + while(!Serial1.available()){ + delay(1); + if (millis() > timeout) { + debug("FAILED: AT handshake timeout"); + return false; + } + } + debug("check for a"); + char resp = Serial1.read(); + if (resp == 'a') { + debug("OK: module acknowledge AT mode"); + return true; + } + // otherwise it's failed. + debug("FAILED: module acknowledge AT mode"); + return false; +} +void DigiFi::endATMode() +{ + //back to transparent mode + Serial1.print("AT+E\r"); + debug(readResponse(0)); + Serial1.print("AT+ENTM\r"); + debug(readResponse(0)); + debug("exit at mode"); +} + bool DigiFi::ready(){ + startATMode(); + //debug("send cmd"); + //+ok=< LF >< LF > + //â€Disconnectedâ€, if no WiFi connection; + //â€AP’ SSID（AP’s MAC†）, if WiFi connection available; + //â€RF Offâ€, if WiFi OFF; + debug("Check Link"); + String ret = STALinkStatus(); + debug("OUT"); + debug(ret); + endATMode(); + debug(ret); + //change this to report the AP it is connected to + if(ret.substring(0,10) == "+ok=RF Off" || ret.substring(0,16) == "+ok=Disconnected") + return 0; + else + return 1; +} + +uint8_t DigiFi::maintain() {return 0;} + + +IPAddress DigiFi::localIP(){ + + startATMode(); + String response = getSTANetwork(); + endATMode(); + response = response.substring(response.indexOf(",")+1); + response = response.substring(0,response.indexOf(",")); + String ip1 = response.substring(0,response.indexOf(".")); + String ip2 = response.substring(response.indexOf(".")+1); + String ip3 = ip2.substring(ip2.indexOf(".")+1); + String ip4 = ip3.substring(ip3.indexOf(".")+1); + ip2 = ip2.substring(0,ip2.indexOf(".")); + ip3 = ip3.substring(0,ip3.indexOf(".")); + IPAddress ip(ip1.toInt(),ip2.toInt(),ip3.toInt(),ip4.toInt()); + return ip; +} + +IPAddress DigiFi::subnetMask(){ + + startATMode(); + String response = getSTANetwork(); + endATMode(); + response = response.substring(response.indexOf(",")+1); + response = response.substring(response.indexOf(",")+1); + response = response.substring(0,response.indexOf(",")); + String ip1 = response.substring(0,response.indexOf(".")); + String ip2 = response.substring(response.indexOf(".")+1); + String ip3 = ip2.substring(ip2.indexOf(".")+1); + String ip4 = ip3.substring(ip3.indexOf(".")+1); + ip2 = ip2.substring(0,ip2.indexOf(".")); + ip3 = ip3.substring(0,ip3.indexOf(".")); + IPAddress ip(ip1.toInt(),ip2.toInt(),ip3.toInt(),ip4.toInt()); + return ip; +} + +IPAddress DigiFi::gatewayIP(){ + + startATMode(); + String response = getSTANetwork(); + endATMode(); + response = response.substring(response.indexOf(",")+1); + response = response.substring(response.indexOf(",")+1); + response = response.substring(response.indexOf(",")+1); + response = response.substring(0,response.indexOf("\r")); + String ip1 = response.substring(0,response.indexOf(".")); + String ip2 = response.substring(response.indexOf(".")+1); + String ip3 = ip2.substring(ip2.indexOf(".")+1); + String ip4 = ip3.substring(ip3.indexOf(".")+1); + ip2 = ip2.substring(0,ip2.indexOf(".")); + ip3 = ip3.substring(0,ip3.indexOf(".")); + IPAddress ip(ip1.toInt(),ip2.toInt(),ip3.toInt(),ip4.toInt()); + return ip; +} + +IPAddress DigiFi::dnsServerIP(){ + + startATMode(); + String response = getSTADNS(); + endATMode(); + response = response.substring(4,response.indexOf("\r")); + String ip1 = response.substring(0,response.indexOf(".")); + String ip2 = response.substring(response.indexOf(".")+1); + String ip3 = ip2.substring(ip2.indexOf(".")+1); + String ip4 = ip3.substring(ip3.indexOf(".")+1); + ip2 = ip2.substring(0,ip2.indexOf(".")); + ip3 = ip3.substring(0,ip3.indexOf(".")); + IPAddress ip(ip1.toInt(),ip2.toInt(),ip3.toInt(),ip4.toInt()); + return ip; +} + +//server functions + +String DigiFi::server(uint16_t port){ + startATMode(); + + while(Serial1.available()){Serial1.read();} + String conn=getNetParams(); + + String isServer = conn.substring(conn.indexOf("+ok"),conn.length()); + + isServer = isServer.substring(8,14); + + setNetParams("TCP","SERVER",port,"127.0.0.1"); + //setTCPConn("On"); //is this needed? + + if(isServer != "Server"){ + + debug("restart for switch to server mode"); + reset(); + delay(3000); + + + uint32_t startTime = millis(); + while(!ready() && millis()-startTime < 30000){ + delay(1000); + } + startATMode(); + + } + String response = getSTANetwork(); + response = response.substring(response.indexOf(",")+1); + response = response.substring(0,response.indexOf(",")); + endATMode(); + return response; +} + +bool DigiFi::serverRequest(){ + if(Serial1.available()){ + String response = readResponse(0); + response = response.substring(4); + response = response.substring(0,response.indexOf("\n")); + response = response.substring(0,response.lastIndexOf("HTTP/")-1); + debug(response); + serverRequestPathString = response; + return true; + } + else + return false; +} + +String DigiFi::serverRequestPath(){ + return serverRequestPathString; + +} +void DigiFi::serverResponse(String response, int code) //defaults to code = 200 +{ + Serial1.print("HTTP/1.1 "); + Serial1.print(code); + if(code==200) + Serial1.print(" OK"); + else if(code==404) + Serial1.print(" Not Found"); + else + Serial1.print(" OK"); //left as OK to not mess anything up + Serial1.print(" \r\n"); + Serial1.print("Content-Type: text/html;\r\n"); + Serial1.print("Content-Length: "); + Serial1.print(response.length()); + Serial1.print("\r\n"); + Serial1.print("Connection: close\r\n\r\n"); + Serial1.print(response); + Serial1.print("\r\n\r\n"); + + return; +} + +void DigiFi::setTCPTimeout(uint16_t timeout){ + startATMode(); + Serial1.print("AT+TCPTO="); + Serial1.print(timeout); + Serial1.print("\r"); + endATMode(); + +} + +uint8_t DigiFi::connected(){ + + uint8_t ret = 0; + + + if(Serial1.available() > 0) + return 1; + + if(millis() < digiFiActivityTimeout) + return 1; + + + startATMode(); + + debug("Checking for link build up"); + String status=getTCPLnk(); + + if (status.substring(0,6)=="+ok=on") + ret = 1; + + endATMode(); + + + + return ret; + +} + + +//client functions + +int DigiFi::connect(IPAddress ip, uint16_t port = 80){ + //uint8_t* server = rawIPAddress(ip); + String server = String(ip[0]) + "." + String(ip[1])+ "." + String(ip[2])+ "." + String(ip[3]); + return connect(server.c_str(),port); +} +int DigiFi::connect(const char *host, uint16_t port = 80){ + debug("::connect(*char host, uint port)"); + uint8_t lastMode = TCP; + debug("Connect"); + startATMode(); + debug("send client settings"); + setTCPConn("off"); + //assuming port 80 for now + String conn=getNetParams(); + String isServer = conn.substring(8,14); + + if(conn.substring(4,7)=="UDP") + lastMode = UDP; + + debug(conn.substring(4,7)); + conn=conn.substring(conn.lastIndexOf(',')+1,conn.length()-1); + debug(conn); + debug(host); + + debug(isServer); + if(conn != host || isServer == "Server" || lastMode != digiFiMode){ + if(digiFiMode == TCP) + setNetParams("TCP","CLIENT",port,host); + else + setNetParams("UDP","CLIENT",port,host); + + debug("setting net params"); + } + else{ + debug("skipping net params"); + } + + //lastHost = conn; + + if(isServer == "Server" || lastMode != digiFiMode){ + debug("restart for switch to client mode"); + reset(); + delay(3000); + startATMode(); + setTCPConn("off"); + } + + setTCPConn("On"); + uint32_t linkStart = millis(); + if(digiFiMode == TCP){ + + getNetParams(); + + debug("Checking for link build up"); + String status=getTCPLnk(); + while(status.substring(0,6)!="+ok=on"){ + debug("Status:"); + debug(status); + debug("Re-checking for link build up"); + status=getTCPLnk(); + debug(status); + if(millis()-linkStart > (requestTimeout*1000)){ + endATMode(); + return 0; + } + } + } + else{ + debug("Checking for host ready"); + String status = ping((char*)host); + if(status.substring(0,11)!="+ok=Success"){ + while(status.substring(0,11)!="+ok=Success"){ + debug("Re-checking for host ready"); + status=ping((char*)host); + debug(status); + if(millis()-linkStart > (requestTimeout*1000)){ + endATMode(); + return 0; + } + } + debug("Wait for UDP to be ready to receive as well"); + delay(2000); + } + + } + + endATMode(); + + return 1; +} + +int DigiFi::disconnect() { + debug("::disconnect(*char host, uint port)"); + startATMode(); + setTCPConn("off"); + endATMode(); + return 1; +} +String DigiFi::body(){ + return aBody; +} +String DigiFi::header(){ + return aHeader; +} +void DigiFi::setDebug(bool debugStateVar){ + digiFiDebugState = debugStateVar; +} +void DigiFi::setMode(uint8_t protocol){ + digiFiMode = protocol; +} +void DigiFi::debug(String output){ + if(digiFiDebugState == true) + Serial.println(output); + +} +void DigiFi::debugWrite(char output){ + if(digiFiDebugState == true) + Serial.write(output); + +} +/* +Return value should be the HTTP return code (i.e. 100 and above). +If something else fails, the non-HTTP error codes are negative numbers. +-1 - connect failure +-2 - connect successful, but request failed +-3 - invalid HTTP return-code returned +*/ +int DigiFi::get(char *aHost, char *aPath){ + if(connect(aHost) == 1){ + //delay(500); + Serial1.print("GET "); + Serial1.print(aPath); + Serial1.print(" HTTP/1.1\r\nHost: "); + Serial1.print(aHost); + Serial1.print("\r\nCache-Control: no-cache\r\nConnection: close\r\n\r\n"); + Serial1.flush(); + + //don't block while awating reply + debug("wait for response..."); + bool success = true; + int i=0; + int st = millis(); + while(!Serial1.available()){ + if(millis() - st > requestTimeout * 1000) { + success = false; + break; + } + if(((millis() - st) % 1000) == 1) + debugWrite('.'); + i++; + } + debug("get header"); + if(success == false) + return -2; + aHeader = readResponse(0); + debug(aHeader); + + String contentLength = aHeader.substring(aHeader.lastIndexOf("Content-Length: ")); + contentLength = contentLength.substring(16,contentLength.indexOf("\r")); + debug("Length:"+contentLength+";"); + + if(contentLength.toInt() != 0) { + debug("get body for later"); + aBody = readResponse(contentLength.toInt()); + } + else + { + debug("Skip body"); + } + debug("return from get"); + + // work out the returncode + int iRetCode = aHeader.substring(9,12).toInt(); + if (iRetCode == 0) { + debug("Invalid return code"); + return -3; + } + return iRetCode; + } + else + return -1; + + //To do: + /* + User agent! + Better handle timeouts/other errors + Efficiency! + */ +} +String DigiFi::URLEncode(String smsg) +{ + const char *msg = smsg.c_str(); + const char *hex = "0123456789abcdef"; + String encodedMsg = ""; + + while (*msg!='\0'){ + if( ('a' <= *msg && *msg <= 'z') + || ('A' <= *msg && *msg <= 'Z') + || ('0' <= *msg && *msg <= '9') ) { + encodedMsg += *msg; + } else { + encodedMsg += '%'; + encodedMsg += hex[*msg >> 4]; + encodedMsg += hex[*msg & 15]; + } + msg++; + } + return encodedMsg; +} +/* +Return value should be the HTTP return code (i.e. 100 and above). +If something else fails, the non-HTTP error codes are negative numbers. +-1 - connect failure +-2 - connect successful, but request failed +-3 - invalid HTTP return-code returned +*/ +int DigiFi::post(char *aHost, char *aPath, String postData) { + if(connect(aHost) == 1){ + Serial1.print("POST "); + Serial1.print(aPath); + Serial1.print(" HTTP/1.1\r\nHost: "); + Serial1.print(aHost); + Serial1.print("\r\nCache-Control: no-cache\r\nContent-Type: application/x-www-form-urlencoded\r\nConnection: close\r\n"); + Serial1.print("Content-Length: "); + Serial1.print(postData.length()); + Serial1.print("\r\n\r\n"); + Serial1.print(postData); + Serial1.print("\r\n\r\n"); + Serial1.flush(); + + debug("wait for response..."); + bool success = true; + int i=0; + int st = millis(); + while(!Serial1.available()){ + if(millis() - st > requestTimeout * 1000) { + success = false; + break; + } + if(((millis() - st) % 1000) == 1) + debugWrite('.'); + i++; + } + + if(success == false) + return -2; + + debug("Get header"); + aHeader = readResponse(0); + + debug(aHeader); + + String contentLength = aHeader.substring(aHeader.lastIndexOf("Content-Length: ")); + contentLength = contentLength.substring(16,contentLength.indexOf("\n")); + debug(contentLength); + + if(contentLength.toInt() != 0) { + debug("Get body"); + aBody = readResponse(contentLength.toInt()); + } + else + { + debug("Skip body"); + } + + // connection: close hard-coded, so disconnect here. + disconnect(); + // TODO: + // + make connection: close header optional + // and run disconnect dependent on that option + // + remove the disconnect command (TCPDIS=off) + // from the start of the connect command. + // but need to have connection checking upfront + // first. + + // work out the returncode + int iRetCode = aHeader.substring(9,12).toInt(); + if (iRetCode == 0) { + debug("Invalid return code"); + return -3; + } + return iRetCode; + } + else + return -1; + + //To do: + /* + User agent! + accept post data as array or array or string, etc + Better handle timeouts/other errors + Efficiency! + */ + +} +void DigiFi::close() +{ + //clear buffer + while(Serial1.available()){Serial1.read();} + Serial1.end(); +} +String DigiFi::readResponse(int contentLength) //0 = cmd, 1 = header, 2=body +{ + String stringBuffer; + char inByte; + int rCount = 0; + int nCount = 0; + int curLength = 0; + bool end = false; + Serial1.flush(); + bool timeout = false; + int st = millis(); + + while (!end) + { + //look for this to be four bytes in a row + if (Serial1.available()) + { + inByte = Serial1.read(); + curLength++; + //debugWrite(inByte);// disabled, leads to lots of duplicate debug logging + + if(contentLength == 0){ + if (inByte == '\n' && rCount == 2 && nCount == 1) + { + end = true; + int strLength = stringBuffer.length()-3; + stringBuffer = stringBuffer.substring(0,strLength); + } + else if (inByte == '\r') + rCount++; + else if (inByte == '\n') + nCount++; + else{ + rCount = 0; + nCount = 0; + } + } + else if(curLength>=contentLength) + end = true; + + stringBuffer += inByte; + } + else + { + // need a timeout otherwise we can get stuck in + // here if the server drops out for some reason + // does though imply that 15s is sufficient to + // retrieve whatever it is your after + // seems OK though as DigiX doesn't have a large + // amount of memory + if(millis() - st > requestTimeout * 1000) { + timeout = true; + break; + } + } + } + + if(stringBuffer.substring(0,4) == "+ERR") { + lastErr = stringBuffer.substring(5,2).toInt(); + } else if (timeout) { + lastErr = -1; + } else { + lastErr = 0; + } + return stringBuffer; +} +int DigiFi::lastError() +{ + return lastErr; +} +String DigiFi::AT(char *cmd, char *params) +{ + Serial1.print("AT+"); + Serial1.print(cmd); + if(sizeof(*params) > 0) + { + Serial1.print("="); + Serial1.print(params); + } + Serial1.print("\r"); + return readResponse(0); +} +void DigiFi::toggleEcho() //E +{ + Serial1.print("AT+E\r"); + readResponse(0); +} +String DigiFi::getWifiMode() //WMODE AP STA APSTA +{ + Serial1.print("AT+WMODE\r"); + return readResponse(0); +} +void DigiFi::setWifiMode(char *mode) +{ + Serial1.print("AT+WMODE="); + Serial1.print(mode); + Serial1.print("\r"); + readResponse(0); +} +void DigiFi::setTransparent() //ENTM +{ + Serial1.print("AT+ENTM\r"); + readResponse(0); +} +String DigiFi::getTMode() //TMODE throughput cmd +{ + Serial1.print("AT+TMODE\r"); + return readResponse(0); +} +void DigiFi::setTMode(char *mode) +{ + Serial1.print("AT+TMODE="); + Serial1.print(mode); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getModId() //MID +{ + Serial1.print("AT+MID\r"); + return readResponse(0); +} +String DigiFi::version() //VER +{ + Serial1.print("AT+VER\r"); + return readResponse(0); +} +void DigiFi::factoryRestore() //RELD rebooting... +{ + Serial1.print("AT+RELD\r"); + readResponse(0); +} +void DigiFi::reset() //Z (No return) +{ + Serial1.print("AT+Z\r"); + //readResponse(0); + lastErr=0; //This command doesnt return anything. +} +String DigiFi::help()//H +{ + Serial1.print("AT+H\r"); + return readResponse(0); +} +int DigiFi::readConfig(byte* buffer)//CFGRD +{ + Serial1.print("AT+CFGRD\r"); + Serial1.readBytes((char*)buffer,4); + if((char*)buffer=="+ERR") + return -1; //TODO Set lastErr here (Technically it shouldn't ever error here) + Serial1.readBytes((char*)buffer,2); + int len=(int)word(buffer[1],buffer[0]); + Serial1.readBytes((char*)buffer,len); + return len; +} +void DigiFi::writeConfig(byte* config, int len)//CFGWR +{ + Serial1.print("AT+CFGWR="); + Serial1.write(highByte(len)); + Serial1.write(lowByte(len)); + Serial1.write(config,len); + Serial1.print("\r"); + readResponse(0); +} +int DigiFi::readFactoryDef(byte* buffer)//CFGFR +{ + Serial1.print("AT+CFGFR\r"); + Serial1.readBytes((char*)buffer,4); + if((char*)buffer=="+ERR") + return -1; //TODO Set lastErr here (Technically it shouldn't ever error here) + Serial1.readBytes((char*)buffer,2); + int len=(int)word(buffer[1],buffer[0]); + Serial1.readBytes((char*)buffer,len); + return len; +} +void DigiFi::makeFactory() //CFGTF +{ + Serial1.print("AT+CFGTF\r"); + readResponse(0); +} +String DigiFi::getUart()//UART baudrate,data_bits,stop_bit,parity +{ + Serial1.print("AT+UART\r"); + return readResponse(0); +} +void DigiFi::setUart(int baudrate,int data_bits,int stop_bit,char *parity) +{ + Serial1.print("AT+UART="); + Serial1.print(baudrate); + Serial1.print(","); + Serial1.print(data_bits); + Serial1.print(","); + Serial1.print(stop_bit); + Serial1.print(","); + Serial1.print(parity); + Serial1.print("\r"); + readResponse(0); +} +/* +String getAutoFrame(); //UARTF +void setAutoFrame(char *para); +int getAutoFrmTrigTime(); //UARTFT +void setAutoFrmTrigTime(int ms); +int getAutoFrmTrigLength(); //UARTFL +void setAutoFrmTrigLength(int v); +*/ +void DigiFi::sendData(int len, char *data)//SEND +{ + Serial1.print("AT+SEND="); + Serial1.print(len); + Serial1.print(","); + Serial1.print(data); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::recvData(int len)//RECV len,data (+ok=0 if timeout (3sec)) +{ + Serial1.print("AT+RECV="); + Serial1.print(len); + Serial1.print("\r"); + return readResponse(0); +} +String DigiFi::ping(char *ip)//PING Success Timeout Unknown host +{ + Serial1.print("AT+PING="); + Serial1.print(ip); + Serial1.print("\r"); + return readResponse(0); +} +String DigiFi::getNetParams()//NETP (TCP|UDP),(SERVER|CLIENT),port,IP +{ + Serial1.print("AT+NETP\r"); + return readResponse(0); +} +void DigiFi::setNetParams(char *proto, char *cs, int port, const char *ip) +{ + if(cs == "SERVER") + digiFiServer = true; + else + digiFiServer = false; + + Serial1.print("AT+NETP="); + Serial1.print(proto); + Serial1.print(","); + Serial1.print(cs); + Serial1.print(","); + Serial1.print(port); + Serial1.print(","); + Serial1.print(ip); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getTCPLnk()//TCPLK on|off +{ + Serial1.print("AT+TCPLK\r"); + return readResponse(0); +} +String DigiFi::getTCPTimeout()//TCPTO 0 <= int <= 600 (Def 300) +{ + Serial1.print("AT+TCPTO\r"); + return readResponse(0); +} +String DigiFi::getTCPConn()//TCPDIS On|off +{ + Serial1.print("AT+TCPDIS\r"); + return readResponse(0); +} +void DigiFi::setTCPConn(char *sta) +{ + Serial1.print("AT+TCPDIS="); + Serial1.print(sta); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getWSSSID()//WSSSID +{ + Serial1.print("AT+WSSSID\r"); + return readResponse(0); +} +void DigiFi::setWSSSID(char *ssid) +{ + Serial1.print("AT+WSSSID="); + Serial1.print(ssid); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getSTAKey()//WSKEY (OPEN|SHARED|WPAPSK|WPA2PSK),(NONE|WEP|TKIP|AES),key +{ + Serial1.print("AT+WSKEY\r"); + return readResponse(0); +} +void DigiFi::setSTAKey(char* auth,char *encry,char *key) +{ + Serial1.print("AT+WSKEY="); + Serial1.print(auth); + Serial1.print(","); + Serial1.print(encry); + Serial1.print(","); + Serial1.print(key); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getSTANetwork()//WANN (static|DHCP),ip,subnet,gateway +{ + Serial1.print("AT+WANN\r"); + return readResponse(0); +} +void DigiFi::setSTANetwork(char *mode, char *ip, char *subnet, char *gateway) +{ + Serial1.print("AT+WANN="); + Serial1.print(mode); + Serial1.print(","); + Serial1.print(ip); + Serial1.print(","); + Serial1.print(subnet); + Serial1.print(","); + Serial1.print(gateway); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getSTAMac()//WSMAC returns MAC +{ + Serial1.print("AT+WSMAC\r"); + return readResponse(0); +} +void DigiFi::setSTAMac(int code, char *mac)//Code default is 8888, no idea what its for +{ + Serial1.print("AT+WSSSID="); + Serial1.print(code); + Serial1.print(","); + Serial1.print(mac); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::STALinkStatus()//WSLK (Disconnected|AP SSID (AP MAC)|RF Off) +{ + Serial1.print("AT+WSLK\r"); + return readResponse(0); +} +String DigiFi::STASignalStrength()//WSLQ (Disconnected|Value) +{ + Serial1.print("AT+WSLQ\r"); + return readResponse(0); +} +String DigiFi::scan()//WSCAN returns list +{ + Serial1.print("AT+WSCAN\r"); + return readResponse(0); +} +String DigiFi::getSTADNS()//WSDNS address +{ + Serial1.print("AT+WSDNS\r"); + return readResponse(0); +} +void DigiFi::setSTADNS(char *dns) +{ + Serial1.print("AT+WSDNS="); + Serial1.print(dns); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getAPNetwork()//LANN ip,subnet +{ + Serial1.print("AT+LANN\r"); + return readResponse(0); +} +void DigiFi::setAPNetwork(char *ip, char *subnet) +{ + Serial1.print("AT+LANN="); + Serial1.print(ip); + Serial1.print(","); + Serial1.print(subnet); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getAPParams()//WAP (11B|11BG|11BGN),SSID,(AUTO|C1...C11) +{ + Serial1.print("AT+WAP\r"); + return readResponse(0); +} +void DigiFi::setAPParams(char *mode, char *ssid, char *channel) +{ + Serial1.print("AT+WAP="); + Serial1.print(mode); + Serial1.print(","); + Serial1.print(ssid); + Serial1.print(","); + Serial1.print(channel); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getAPKey()//WAKEY (OPEN|WPA2PSK),(NONE|AES),key +{ + Serial1.print("AT+WAKEY\r"); + return readResponse(0); +} +void DigiFi::setAPKey(char* auth,char *encry,char *key) +{ + Serial1.print("AT+WAKEY="); + Serial1.print(auth); + Serial1.print(","); + Serial1.print(encry); + Serial1.print(","); + Serial1.print(key); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getAPMac()//WAMAC returns MAC +{ + Serial1.print("AT+WAMAC\r"); + return readResponse(0); +} +String DigiFi::getAPDHCP()//WADHCP (on|off) +{ + Serial1.print("AT+WADHCP\r"); + return readResponse(0); +} +void DigiFi::setAPDHCP(char *status) +{ + Serial1.print("AT+WADHCP="); + Serial1.print(status); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getAPPageDomain()//WADMN domain +{ + Serial1.print("AT+WADM\r"); + return readResponse(0); +} +void DigiFi::setAPPageDomain(char *domain) +{ + Serial1.print("AT+WADMN="); + Serial1.print(domain); + Serial1.print("\r"); + readResponse(0); +} +void DigiFi::setPageDisplayMode(char *mode)//WEBSWITCH (iw|ew) +{ + Serial1.print("AT+WEBSWITCH="); + Serial1.print(mode); + Serial1.print("\r"); + readResponse(0); +} +void DigiFi::setPageLanguage(char *lang)//PLANG CN|EN +{ + Serial1.print("AT+PLANG="); + Serial1.print(lang); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getUpgradeUrl()//UPURL url !!!DANGEROUS!!! +{ + Serial1.print("AT+UPURL\r"); + return readResponse(0); +} +void DigiFi::setUpgradeUrl(char *url)//url,filename (filename is optional, if provided upgrade is auto started) +{ + Serial1.print("AT+UPURL="); + Serial1.print(url); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getUpgradeFile()//UPFILE filename !!!DANGEROUS!!! +{ + Serial1.print("AT+UPFILE\r"); + return readResponse(0); +} +void DigiFi::setUpgradeFile(char *filename) +{ + Serial1.print("AT+UPFILE="); + Serial1.print(filename); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::startUpgrade()//UPST !!!DANGEROUS!!! +{ + Serial1.print("AT+UPST\r"); + return readResponse(0); +} +String DigiFi::getWebAuth()//WEBU user,pass +{ + Serial1.print("AT+WEBU\r"); + return readResponse(0); +} +void DigiFi::setWebAuth(char *user, char *pass) +{ + Serial1.print("AT+WEBU="); + Serial1.print(user); + Serial1.print(","); + Serial1.print(pass); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getSleepMode()//MSLP normal|standby +{ + Serial1.print("AT+MSLP\r"); + return readResponse(0); +} +void DigiFi::setSleepMode(char *mode) +{ + Serial1.print("AT+MSLP="); + Serial1.print(mode); + Serial1.print("\r"); + readResponse(0); +} +void DigiFi::setModId(char *modid)//WRMID +{ + Serial1.print("AT+WRMID="); + Serial1.print(modid); + Serial1.print("\r"); + readResponse(0); +} +String DigiFi::getWifiCfgPassword()//ASWD aswd +{ + Serial1.print("AT+ASWD\r"); + return readResponse(0); +} +void DigiFi::setWifiCfgPassword(char *aswd) +{ + Serial1.print("AT+ASWD="); + Serial1.print(aswd); + Serial1.print("\r"); + readResponse(0); +} diff --git a/hardware/digistump/sam/libraries/DigiFi/DigiFi.h b/hardware/digistump/sam/libraries/DigiFi/DigiFi.h new file mode 100644 index 0000000..1da3aed --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/DigiFi.h @@ -0,0 +1,162 @@ +// DigiX WiFi module example - released by Digistump LLC/Erik Kettenburg under CC-BY-SA 3.0 + + +#ifndef DigiFi_h +#define DigiFi_h + +#include "Arduino.h" +#include "Print.h" +#include +#include "Client.h" +#include "IPAddress.h" + +#define DIGIFI_RTS 105 +#define DIGIFI_CTS 104 +#define TCP 1 +#define UDP 0 + +class DigiFi : public Client +{ + public: + static const int requestTimeout = 15; + String serverRequestPathString; + DigiFi(); + + void begin(int aBaud = 9600, bool en = false); + bool ready(); + void setDebug(bool debugStateVar); + void setTCPTimeout(uint16_t timeout); + bool serverRequest(); + void serverResponse(String response, int code = 200); + String server(uint16_t port); + String serverRequestPath(); + virtual int connect(IPAddress ip, uint16_t port); + virtual int connect(const char *host, uint16_t port); + virtual int disconnect(); + int get(char *aHost, char *aPath); + int post(char *aHost, char *aPath, String postData); + void startATMode(); + void endATMode(); + void close(); + void closeChunk(); + void printChunk(const char *str); + void printChunk(int str); + void printChunk(long str); + void printChunk(String str); + void setMode(uint8_t protocol = TCP); + String header(); + String body(); + int lastError(); + void debug(String output); + void debugWrite(char output); + String URLEncode(String smsg); + void setFlowControl(boolean); + + //Ethernet implimentation + IPAddress localIP(); + IPAddress subnetMask(); + IPAddress gatewayIP(); + IPAddress dnsServerIP(); + uint8_t maintain(); + + /* Client Implementation */ + virtual uint8_t connected(); + //uint8_t status(); + virtual operator bool(); + + virtual int available( void ) ; + virtual int peek( void ) ; + virtual int read( void ) ; + virtual int read(uint8_t *buf, size_t size); + virtual void flush( void ) ; + virtual void stop( void ) ; + virtual size_t write( const uint8_t c ) ; + virtual size_t write(const uint8_t *buf, size_t size); + using Print::write ; // pull in write(str) and write(buf, size) from Print + + /* AT Wrappers */ + String AT(char *cmd, char *params); + void toggleEcho(); //E + String getWifiMode(); //WMODE AP STA APSTA + void setWifiMode(char *mode); + void setTransparent(); //ENTM + String getTMode(); //TMODE throughput cmd + void setTMode(char *mode); + String getModId(); //MID + String version(); //VER + void factoryRestore(); //RELD rebooting... + void reset(); //Z (No return) + String help();//H + int readConfig(byte* buffer);//CFGRD + void writeConfig(byte* config, int len);//CFGWR + int readFactoryDef(byte* buffer);//CFGFR + void makeFactory(); //CFGTF + String getUart();//UART baudrate,data_bits,stop_bit,parity + void setUart(int baudrate,int data_bits,int stop_bit,char *parity); + /* These are commented out as I'm unsure how they should be named + String getAutoFrame(); //UARTF + void setAutoFrame(char *para); + int getAutoFrmTrigTime(); //UARTFT + void setAutoFrmTrigTime(int ms); + int getAutoFrmTrigLength(); //UARTFL + void setAutoFrmTrigLength(int v); + */ + void sendData(int len, char *data);//SEND + String recvData(int len);//RECV len,data (+ok=0 if timeout (3sec)) + String ping(char *ip);//PING Success Timeout Unknown host + String getNetParams();//NETP (TCP|UDP),(SERVER|CLIENT),port,IP + void setNetParams(char *proto, char *cs, int port, const char *ip); + String getTCPLnk();//TCPLK on|off + String getTCPTimeout();//TCPTO 0 <= int <= 600 (Def 300) + String getTCPConn();//TCPDIS On|off + void setTCPConn(char *sta); + String getWSSSID();//WSSSID + void setWSSSID(char *ssid); + String getSTAKey();//WSKEY (OPEN|SHARED|WPAPSK|WPA2PSK),(NONE|WEP|TKIP|AES),key + void setSTAKey(char* auth,char *encry,char *key); + String getSTANetwork();//WANN (static|DHCP),ip,subnet,gateway + void setSTANetwork(char *mode, char *ip, char *subnet, char *gateway); + String getSTAMac();//WSMAC returns MAC + void setSTAMac(int code, char *mac);//Code default is 8888, no idea what its for + String STALinkStatus();//WSLK (Disconnected|AP SSID (AP MAC)|RF Off) + String STASignalStrength();//WSLQ (Disconnected|Value) + String scan();//WSCAN returns list + String getSTADNS();//WSDNS address + void setSTADNS(char *dns); + String getAPNetwork();//LANN ip,subnet + void setAPNetwork(char *ip, char *subnet); + String getAPParams();//WAP (11B|11BG|11BGN),SSID,(AUTO|C1...C11) + void setAPParams(char *mode, char *ssid, char *channel); + String getAPKey();//WAKEY (OPEN|WPA2PSK),(NONE|AES),key + void setAPKey(char* auth,char *encry,char *key); + String getAPMac();//WAMAC returns MAC + String getAPDHCP();//WADHCP (on|off) + void setAPDHCP(char *status); + String getAPPageDomain();//WADMN domain + void setAPPageDomain(char *domain); + void setPageDisplayMode(char *mode);//WEBSWITCH (iw|ew) + void setPageLanguage(char *lang);//PLANG CN|EN + String getUpgradeUrl();//UPURL url !!!DANGEROUS!!! + void setUpgradeUrl(char *url);//url,filename (filename is optional, if provided upgrade is auto started) + String getUpgradeFile();//UPFILE filename !!!DANGEROUS!!! + void setUpgradeFile(char *filename); + String startUpgrade();//UPST !!!DANGEROUS!!! + String getWebAuth();//WEBU user,pass + void setWebAuth(char *user, char *pass); + String getSleepMode();//MSLP normal|standby + void setSleepMode(char *mode); + void setModId(char *modid);//WRMID + String getWifiCfgPassword();//ASWD aswd + void setWifiCfgPassword(char *aswd); + private: + String readResponse(int contentLength); + bool startATSequence(); + String aHeader; + String aBody; + //String lastHost; + int lastErr; + bool debugState; + +}; + +#endif \ No newline at end of file diff --git a/hardware/digistump/sam/libraries/DigiFi/README.md b/hardware/digistump/sam/libraries/DigiFi/README.md new file mode 100644 index 0000000..ea1414c --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/README.md @@ -0,0 +1,4 @@ +DigiFi +====== + +DigiX WiFi Library for the WIFI232-G Module diff --git a/hardware/digistump/sam/libraries/DigiFi/examples/BasicClient/BasicClient.ino b/hardware/digistump/sam/libraries/DigiFi/examples/BasicClient/BasicClient.ino new file mode 100644 index 0000000..89a032d --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/examples/BasicClient/BasicClient.ino @@ -0,0 +1,61 @@ +// DigiX WiFi module example - released by Digistump LLC/Erik Kettenburg under CC-BY-SA 3.0 +// Inspired by HttpClient library by MCQN Ltd. + +#include + +DigiFi wifi; + +void setup() +{ + // initialize serial communications at 9600 bps: + Serial.begin(9600); + wifi.begin(9600); + + //DigiX trick - since we are on serial over USB wait for character to be entered in serial terminal + while(!Serial.available()){ + Serial.println("Enter any key to begin"); + delay(1000); + } + + Serial.println("Starting"); + + while (wifi.ready() != 1) + { + Serial.println("Error connecting to network"); + delay(15000); + } + + Serial.println("Connected to wifi!"); + +//GET request example + + if(wifi.get("digistump.com","/test.txt")){ + String body = wifi.body(); + Serial.println(body); + } + else{ + Serial.println("error"); + + } + + //POST request example +Serial.println("Sending tweet!"); + //To use thingspeak for sending tweets see: http://community.thingspeak.com/documentation/apps/thingtweet/ + if(wifi.post("api.thingspeak.com","/apps/thingtweet/1/statuses/update","api_key=[YOURTHINGTWEETAPIKEY]&status="+wifi.URLEncode("Tweet from my new DigiX! #digix #digistump http://digistump.com"))){ + String body = wifi.body(); + Serial.println(body); + } + else{ + Serial.println("error"); + + } + + + wifi.close(); +} + +void loop() +{ + + +} \ No newline at end of file diff --git a/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/ChatServer/ChatServer.ino b/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/ChatServer/ChatServer.ino new file mode 100644 index 0000000..bb5b36e --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/ChatServer/ChatServer.ino @@ -0,0 +1,77 @@ +/* + Chat Server + + A simple server that distributes any incoming messages to all + connected clients. To use telnet to your device's IP address and type. + You can see the client's input in the serial monitor as well. + Using a DigiX. + + Circuit: + + * Analog inputs attached to pins A0 through A5 (optional) + + created 18 Dec 2009 + by David A. Mellis + modified 9 Apr 2012 + by Tom Igoe + modified Dec 22, 2013 for use with DigiX by Erik Kettenburg + + */ + +#include + + +DigiFi server; +boolean alreadyConnected = false; // whether or not the client was connected previously + +void setup() { + + + // Open serial communications and wait for port to open: + Serial.begin(9600); + //DigiX trick - since we are on serial over USB wait for character to be entered in serial terminal + while(!Serial.available()){ + Serial.println("Enter any key to begin"); + delay(1000); + } + + // start listening for clients + server.begin(); + server.server(8080); //connect to it on port 8080 + + while (server.ready() != 1) + { + Serial.println("Connecting to network..."); + delay(1000); + } + + Serial.print("Chat server address:"); + Serial.println(server.localIP()); +} + +void loop() { + // wait for a new client: + + // when the client sends the first byte, say hello: + if (server.available() > 0) { + if (!alreadyConnected) { + // clead out the input buffer: + server.flush(); + Serial.println("We have a new client"); + server.println("Hello, client!"); + alreadyConnected = true; + } + + + // read the bytes incoming from the client: + char thisChar = server.read(); + // echo the bytes back to the client: + server.write(thisChar); + // echo the bytes to the server as well: + Serial.write(thisChar); + } + +} + + + diff --git a/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/TelnetClient/TelnetClient.ino b/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/TelnetClient/TelnetClient.ino new file mode 100644 index 0000000..24f217d --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/TelnetClient/TelnetClient.ino @@ -0,0 +1,89 @@ +/* + Telnet client + + This sketch connects to a a telnet server (http://www.google.com) + using a DigiX. You'll need a telnet server + to test this with. + Processing's ChatServer example (part of the network library) works well, + running on port 10002. It can be found as part of the examples + in the Processing application, available at + http://processing.org/ + + + created 14 Sep 2010 + modified 9 Apr 2012 + by Tom Igoe + modified Dec 22, 2013 for use with DigiX by Erik Kettenburg + + + */ + +#include + + +// Enter the IP address of the server you're connecting to: +IPAddress server(1, 1, 1, 1); + +// Initialize the Ethernet client library +// with the IP address and port of the server +// that you want to connect to (port 23 is default for telnet; +// if you're using Processing's ChatServer, use port 10002): +DigiFi client; + +void setup() { + // Open serial communications and wait for port to open: + Serial.begin(9600); + +//DigiX trick - since we are on serial over USB wait for character to be entered in serial terminal + while(!Serial.available()){ + Serial.println("Enter any key to begin"); + delay(1000); + } + + + + Serial.println("Connecting..."); + // start the connection: + client.begin(9600); + client.connect(server,23); + Serial.println("Connected."); + //client.setDebug(true); + //wait for module to be ready + while (client.ready() != 1) + { + Serial.println("Connecting to network..."); + delay(1000); + } +} + +void loop() +{ + // if there are incoming bytes available + // from the server, read them and print them: + if (client.available()) { + char c = client.read(); + Serial.print(c); + } + + // as long as there are bytes in the serial queue, + // read them and send them out the socket if it's open: + while (Serial.available() > 0) { + char inChar = Serial.read(); + if (client.connected()) { + client.print(inChar); + } + } + + // if the server's disconnected, stop the client: + if (!client.connected()) { + Serial.println(); + Serial.println("disconnecting."); + client.stop(); + // do nothing: + while (true); + } +} + + + + diff --git a/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/UdpNtpClient/UdpNtpClient.ino b/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/UdpNtpClient/UdpNtpClient.ino new file mode 100644 index 0000000..0cc9bc7 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/UdpNtpClient/UdpNtpClient.ino @@ -0,0 +1,127 @@ +/* + + Udp NTP Client + + Get the time from a Network Time Protocol (NTP) time server + Demonstrates use of UDP sendPacket and ReceivePacket + For more on NTP time servers and the messages needed to communicate with them, + see http://en.wikipedia.org/wiki/Network_Time_Protocol + + created 4 Sep 2010 + by Michael Margolis + modified 9 Apr 2012 + by Tom Igoe + modified Dec 22, 2013 for use with DigiX by Erik Kettenburg + + This code is in the public domain. + + */ + +#include + +char timeServer[] = "time.nist.gov"; // time.nist.gov NTP server + +const int NTP_PACKET_SIZE = 48; // NTP time stamp is in the first 48 bytes of the message + +uint8_t packetBuffer[NTP_PACKET_SIZE]; //buffer to hold incoming and outgoing packets + +DigiFi client; + +void setup() +{ + // Open serial communications and wait for port to open: + Serial.begin(9600); + +//DigiX trick - since we are on serial over USB wait for character to be entered in serial terminal + while(!Serial.available()){ + Serial.println("Enter any key to begin"); + delay(1000); + } + + // start the connection: + client.begin(9600); + //client.setDebug(true); + //wait for module to be ready + while (client.ready() != 1) + { + Serial.println("Connecting to network..."); + delay(1000); + } + client.setMode(UDP); //must come before connect + Serial.println("Setting up UDP connection"); + client.connect(timeServer,123); +} + +void loop() +{ + sendNTPpacket(); // send an NTP packet to a time server + + // wait to see if a reply is available + delay(1000); + if ( client.available() ) { + // We've received a packet, read the data from it + client.read(packetBuffer, NTP_PACKET_SIZE); // read the packet into the buffer + + //the timestamp starts at byte 40 of the received packet and is four bytes, + // or two words, long. First, esxtract the two words: + + unsigned long highWord = word(packetBuffer[40], packetBuffer[41]); + unsigned long lowWord = word(packetBuffer[42], packetBuffer[43]); + // combine the four bytes (two words) into a long integer + // this is NTP time (seconds since Jan 1 1900): + unsigned long secsSince1900 = highWord << 16 | lowWord; + Serial.print("Seconds since Jan 1 1900 = " ); + Serial.println(secsSince1900); + + // now convert NTP time into everyday time: + Serial.print("Unix time = "); + // Unix time starts on Jan 1 1970. In seconds, that's 2208988800: + const unsigned long seventyYears = 2208988800UL; + // subtract seventy years: + unsigned long epoch = secsSince1900 - seventyYears; + // print Unix time: + Serial.println(epoch); + + + // print the hour, minute and second: + Serial.print("The UTC time is "); // UTC is the time at Greenwich Meridian (GMT) + Serial.print((epoch % 86400L) / 3600); // print the hour (86400 equals secs per day) + Serial.print(':'); + if ( ((epoch % 3600) / 60) < 10 ) { + // In the first 10 minutes of each hour, we'll want a leading '0' + Serial.print('0'); + } + Serial.print((epoch % 3600) / 60); // print the minute (3600 equals secs per minute) + Serial.print(':'); + if ( (epoch % 60) < 10 ) { + // In the first 10 seconds of each minute, we'll want a leading '0' + Serial.print('0'); + } + Serial.println(epoch % 60); // print the second + } + // wait ten seconds before asking for the time again + delay(10000); +} + +// send an NTP request to the time server at the given address +unsigned long sendNTPpacket() +{ + // set all bytes in the buffer to 0 + memset(packetBuffer, 0, NTP_PACKET_SIZE); + // Initialize values needed to form NTP request + // (see URL above for details on the packets) + packetBuffer[0] = 0b11100011; // LI, Version, Mode + packetBuffer[1] = 0; // Stratum, or type of clock + packetBuffer[2] = 6; // Polling Interval + packetBuffer[3] = 0xEC; // Peer Clock Precision + // 8 bytes of zero for Root Delay & Root Dispersion + packetBuffer[12] = 49; + packetBuffer[13] = 0x4E; + packetBuffer[14] = 49; + packetBuffer[15] = 52; + + // all NTP fields have been given values, now + // you can send a packet requesting a timestamp: + client.write(packetBuffer, NTP_PACKET_SIZE); + +} diff --git a/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/WebClient/WebClient.ino b/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/WebClient/WebClient.ino new file mode 100644 index 0000000..248dcf0 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/WebClient/WebClient.ino @@ -0,0 +1,86 @@ +/* + Web client + + This sketch connects to a website (http://www.google.com) + using an DigiX. + + Based on example by David A. Mellis, Tom Igoe, and Adrian McEwen + + */ + +#include + + +// if you don't want to use DNS - though it is handeled by the WiFI module +//so there is no size penalty for using it - +// use the numeric IP instead of the name for the server: +//IPAddress server(74,125,232,128); // numeric IP for Google (no DNS) +char server[] = "digistump.com"; // name address for Google (using DNS) + +// Initialize the Wifi library (client/server/and main all in one) +// with the IP address and port of the server +// that you want to connect to (port 80 is default for HTTP): +DigiFi client; + +void setup() { + // Open serial communications and wait for port to open: + Serial.begin(9600); + + +//DigiX trick - since we are on serial over USB wait for character to be entered in serial terminal + while(!Serial.available()){ + Serial.println("Enter any key to begin"); + delay(1000); + } + + + // start the connection: + client.begin(9600); + //client.setDebug(true); + //wait for module to be ready + while (client.ready() != 1) + { + Serial.println("Connecting to network..."); + delay(1000); + } + + + Serial.println("connecting..."); + + // if you get a connection, report back via serial: + if (client.connect(server, 80)) { + Serial.println("connected"); + // Make a HTTP request: + client.println("GET /test.txt HTTP/1.1"); + client.println("Host: www.digistump.com"); + client.println("Connection: close"); + client.println(); + } + else { + // kf you didn't get a connection to the server: + Serial.println("connection failed"); + } + +} + +void loop() +{ + // if there are incoming bytes available + // from the server, read them and print them: + //while(!Serial1.available()){} + if (client.available()) { + char c = client.read(); + Serial.print(c); + } + + // if the server's disconnected, stop the client: + if (!client.connected()) { + Serial.println(); + Serial.println("disconnecting."); + client.stop(); + + // do nothing forevermore: + while(true); + } +} + diff --git a/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/WebServer/WebServer.ino b/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/WebServer/WebServer.ino new file mode 100644 index 0000000..5435b5f --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/WebServer/WebServer.ino @@ -0,0 +1,100 @@ +/* + Web Server + + A simple web server that shows the value of the analog input pins. + Using a DigiX. + + Circuit: + * Analog inputs attached to pins A0 through A5 (optional) + + created 18 Dec 2009 + by David A. Mellis + modified 9 Apr 2012 + by Tom Igoe + modified Dec 22, 2013 for use with DigiX by Erik Kettenburg + + */ + +#include + +// Initialize the DigiFi library +// with the IP address and port you want to use +// (port 80 is default for HTTP): +DigiFi server; + +void setup() { + // Open serial communications and wait for port to open: + Serial.begin(9600); + //DigiX trick - since we are on serial over USB wait for character to be entered in serial terminal + while(!Serial.available()){ + Serial.println("Enter any key to begin"); + delay(1000); + } + + + // start the server: + server.begin(); + server.server(8080); //start server on port 8080 + server.setTCPTimeout(1); //force wifi to close connection after idle for 1 second + //fix for not being able to close client connections + //see WebServerChunked for a better approach + while (server.ready() != 1) + { + Serial.println("Connecting to network..."); + delay(1000); + } + Serial.print("server is at "); + Serial.println(server.localIP()); +} + + boolean currentLineIsBlank = false; +void loop() { + // listen for incoming + // an http request ends with a blank line + + + if (server.available()) { + char c = server.read(); + Serial.write(c); + // if you've gotten to the end of the line (received a newline + // character) and the line is blank, the http request has ended, + // so you can send a reply + if (c == '\n' && currentLineIsBlank) { + // send a standard http response header + server.println("HTTP/1.1 200 OK"); + server.println("Content-Type: text/html"); + server.println("Connection: close"); // the connection will be closed after completion of the response + server.println("Refresh: 5"); // refresh the page automatically every 5 sec + server.println(); + server.println(""); + server.println(""); + // output the value of each analog input pin + for (int analogChannel = 0; analogChannel < 6; analogChannel++) { + int sensorReading = analogRead(analogChannel); + server.print("analog input "); + server.print(analogChannel); + server.print(" is "); + server.print(sensorReading); + server.println("
"); + } + server.println(""); + server.println(""); + server.println(""); + currentLineIsBlank = false; + + } + else if (c == '\n') { + // you're starting a new line + currentLineIsBlank = true; + } + else if (c != '\r') { + // you've gotten a character on the current line + currentLineIsBlank = false; + } + } + +// give the web browser time to receive the data +delay(1); + + +} diff --git a/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/WebServerChunked/WebServerChunked.ino b/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/WebServerChunked/WebServerChunked.ino new file mode 100644 index 0000000..7237d10 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/examples/EthernetCompatible/WebServerChunked/WebServerChunked.ino @@ -0,0 +1,98 @@ +/* + Web Server + + A simple web server that shows the value of the analog input pins. + Using a DigiX. + + Circuit: + * Analog inputs attached to pins A0 through A5 (optional) + + created 18 Dec 2009 + by David A. Mellis + modified 9 Apr 2012 + by Tom Igoe + modified Dec 22, 2013 for use with DigiX by Erik Kettenburg + + */ + +#include + +// Initialize the DigiFi library +// with the IP address and port you want to use +// (port 80 is default for HTTP): +DigiFi server; + +void setup() { + // Open serial communications and wait for port to open: + Serial.begin(9600); + //DigiX trick - since we are on serial over USB wait for character to be entered in serial terminal + while(!Serial.available()){ + Serial.println("Enter any key to begin"); + delay(1000); + } + + + // start the server: + server.begin(); + server.server(8080); //start server on port 8080 + while (server.ready() != 1) + { + Serial.println("Connecting to network..."); + delay(1000); + } + Serial.print("server is at "); + Serial.println(server.localIP()); +} + + boolean currentLineIsBlank = false; +void loop() { + // listen for incoming + // an http request ends with a blank line + + + if (server.available()) { + char c = server.read(); + Serial.write(c); + // if you've gotten to the end of the line (received a newline + // character) and the line is blank, the http request has ended, + // so you can send a reply + if (c == '\n' && currentLineIsBlank) { + // send a standard http response header + server.println("HTTP/1.1 200 OK"); + server.println("Content-Type: text/html"); + server.println("Connection: close"); // the connection will be closed after completion of the response + //server.println("Refresh: 5"); // refresh the page automatically every 5 sec + server.println("Transfer-Encoding: chunked"); + server.println(); + server.printChunk(""); + server.printChunk(""); + // output the value of each analog input pin + for (int analogChannel = 0; analogChannel < 6; analogChannel++) { + int sensorReading = analogRead(analogChannel); + server.printChunk("analog input "); + server.printChunk(analogChannel); + server.printChunk(" is "); + server.printChunk(sensorReading); + server.printChunk("
"); + } + server.printChunk(""); + server.closeChunk(); + + currentLineIsBlank = false; + + } + else if (c == '\n') { + // you're starting a new line + currentLineIsBlank = true; + } + else if (c != '\r') { + // you've gotten a character on the current line + currentLineIsBlank = false; + } + } + +// give the web browser time to receive the data +delay(1); + + +} diff --git a/hardware/digistump/sam/libraries/DigiFi/examples/KeyboardTweetLCD/KeyboardTweetLCD.ino b/hardware/digistump/sam/libraries/DigiFi/examples/KeyboardTweetLCD/KeyboardTweetLCD.ino new file mode 100644 index 0000000..cb8fe08 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/examples/KeyboardTweetLCD/KeyboardTweetLCD.ino @@ -0,0 +1,118 @@ +bool start = true; +String message = ""; + + +#include + +DigiFi wifi; + +//#define DEBUG +#include // I2C Master lib for ATTinys which use USI - comment this out to use with standard arduinos +#include // for LCD w/ GPIO MODIFIED for the ATtiny85 + +#define GPIO_ADDR 0x27 // (PCA8574A A0-A2 @5V) typ. A0-A3 Gnd 0x20 / 0x38 for A - 0x27 is the address of the Digispark LCD modules. + + +LiquidCrystal_I2C lcd(GPIO_ADDR,16,2); // set address & 16 chars / 2 lines + + + +// Require keyboard control library +#include + +// Initialize USB Controller +USBHost usb; + +// Attach keyboard controller to USB +KeyboardController keyboard(usb); + +// This function intercepts key press +void keyPressed() { + +} + +// This function intercepts key release +void keyReleased() { + + printKey(); +} + +void printKey() { + + if(start){ + lcd.clear(); + lcd.home(); + start = false; + } + + if(keyboard.getOemKey()==40){//enter pressed + lcd.noAutoscroll(); + lcd.clear(); + lcd.home(); + lcd.print("Sending tweet..."); + if(wifi.post("api.thingspeak.com","/apps/thingtweet/1/statuses/update","api_key=[YOURTHINGTWEETAPIKEY]&status="+wifi.URLEncode(message))){ + lcd.clear(); + lcd.home(); + lcd.print("Tweet sent!"); + } + else{ + lcd.clear(); + lcd.home(); + lcd.print("Error sending!"); + } + delay(3000); + lcd.clear(); + lcd.home(); + lcd.print("DigiX - Ready!"); + message =""; + start=true; + lcd.noAutoscroll(); + } + else{ + // getKey() returns the ASCII translation of OEM key + // combined with modifiers. + + char nextChar = keyboard.getKey(); + lcd.print(nextChar); + message += nextChar; + if(message.length()==16) + lcd.autoscroll(); + } + + +} + + + +void setup() +{ + Wire1.begin(); // initialize I2C lib - comment this out to use with standard arduinos + lcd.init(); // initialize the lcd + lcd.backlight(); // Print a message to the LCD. + lcd.print("Starting...."); + delay(5000); //give wifi some time to warm up + lcd.clear(); + lcd.print("WiFi Starting..."); + wifi.begin(9600); + + delay(200); + + while (wifi.ready() != 1) + { + lcd.home(); + lcd.print("WiFi not ready"); + delay(15000); + } + lcd.clear(); + lcd.home(); + lcd.print("DigiX - Ready!"); + + + +} + +void loop() +{ + // Process USB tasks + usb.Task(); +} diff --git a/hardware/digistump/sam/libraries/DigiFi/examples/ServerExample/ServerExample.ino b/hardware/digistump/sam/libraries/DigiFi/examples/ServerExample/ServerExample.ino new file mode 100644 index 0000000..7acbc2f --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/examples/ServerExample/ServerExample.ino @@ -0,0 +1,44 @@ +#include +DigiFi wifi; + +void setup() +{ + Serial.begin(9600); + wifi.begin(9600); + + //DigiX trick - since we are on serial over USB wait for character to be entered in serial terminal + while(!Serial.available()){ + Serial.println("Enter any key to begin"); + delay(1000); + } + + Serial.println("Starting"); + + while (wifi.ready() != 1) + { + Serial.println("Error connecting to network"); + delay(15000); + } + + Serial.println("Connected to wifi!"); + Serial.print("Server running at: "); + String address = wifi.server(8080);//sets up server and returns IP + Serial.println(address); + +// wifi.close(); +} + +void loop() +{ + + if ( wifi.serverRequest()){ + Serial.print("Request for: "); + Serial.println(wifi.serverRequestPath()); + if(wifi.serverRequestPath()!="/") + wifi.serverResponse("404 Not Found",404); + else + wifi.serverResponse("

This is a test

"); //defaults to 200 + } + + delay(10); +} \ No newline at end of file diff --git a/hardware/digistump/sam/libraries/DigiFi/examples/SetRTCbyNTP/SetRTCbyNTP.ino b/hardware/digistump/sam/libraries/DigiFi/examples/SetRTCbyNTP/SetRTCbyNTP.ino new file mode 100644 index 0000000..d2f299c --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/examples/SetRTCbyNTP/SetRTCbyNTP.ino @@ -0,0 +1,155 @@ +/* + + Udp NTP Client + + Uses both Due_RTC library and DigiFi to connect to NTP server + get current time and set RTC to that time. + + This code is in the public domain. + + */ + #include +#include + +RTC_clock rtc_clock(XTAL); + +char* daynames[]={"Mon", "Tue", "Wed", "Thu", "Fri", "Sat", "Sun"}; +int hh,mm,ss,dow,dd,mon,yyyy; + +char timeServer[] = "time.nist.gov"; // time.nist.gov NTP server + +const int NTP_PACKET_SIZE = 48; // NTP time stamp is in the first 48 bytes of the message + +uint8_t packetBuffer[NTP_PACKET_SIZE]; //buffer to hold incoming and outgoing packets + +DigiFi client; + +void setup() +{ + // Open serial communications and wait for port to open: + Serial.begin(9600); + +//DigiX trick - since we are on serial over USB wait for character to be entered in serial terminal + while(!Serial.available()){ + Serial.println("Enter any key to begin"); + delay(1000); + } + rtc_clock.init(); + // start the connection: + client.begin(9600); + //client.setDebug(true); + //wait for module to be ready + while (client.ready() != 1) + { + Serial.println("Connecting to network..."); + delay(1000); + } + client.setMode(UDP); //must come before connect + rtc_clock.set_time(__TIME__); + Serial.println("Setting up UDP connection"); + client.connect(timeServer,123); + unsigned long ntpUnixTime = 0; + while(ntpUnixTime == 0){ + sendNTPpacket(); // send an NTP packet to a time server + delay(1000); + ntpUnixTime = getNTPpacket(); + } + Serial.print("Got NTP Timestamp: "); + Serial.println(ntpUnixTime); + Serial.println("Setting RTC Clock"); + rtc_clock.set_timestamp(ntpUnixTime); + + +} + +void loop() +{ + Serial.print("Time: "); + rtc_clock.get_time(&hh,&mm,&ss); + rtc_clock.get_date(&dow,&dd,&mon,&yyyy); + digitprint(hh, 2); + Serial.print(":"); + digitprint(mm, 2); + Serial.print(":"); + digitprint(ss, 2); + Serial.println(""); + Serial.print("Date: "); + Serial.print(daynames[dow-1]); + Serial.print(" "); + digitprint(dd, 2); + Serial.print("."); + digitprint(mon, 2); + Serial.print("."); + Serial.println(yyyy); + Serial.println(""); + delay(1000); +} + +// send an NTP request to the time server at the given address +unsigned long sendNTPpacket() +{ + // set all bytes in the buffer to 0 + memset(packetBuffer, 0, NTP_PACKET_SIZE); + // Initialize values needed to form NTP request + // (see URL above for details on the packets) + packetBuffer[0] = 0b11100011; // LI, Version, Mode + packetBuffer[1] = 0; // Stratum, or type of clock + packetBuffer[2] = 6; // Polling Interval + packetBuffer[3] = 0xEC; // Peer Clock Precision + // 8 bytes of zero for Root Delay & Root Dispersion + packetBuffer[12] = 49; + packetBuffer[13] = 0x4E; + packetBuffer[14] = 49; + packetBuffer[15] = 52; + + // all NTP fields have been given values, now + // you can send a packet requesting a timestamp: + client.write(packetBuffer, NTP_PACKET_SIZE); + +} + +unsigned long getNTPpacket(){ + if ( client.available() ) { + // We've received a packet, read the data from it + client.read(packetBuffer, NTP_PACKET_SIZE); // read the packet into the buffer + + //the timestamp starts at byte 40 of the received packet and is four bytes, + // or two words, long. First, esxtract the two words: + + unsigned long highWord = word(packetBuffer[40], packetBuffer[41]); + unsigned long lowWord = word(packetBuffer[42], packetBuffer[43]); + // combine the four bytes (two words) into a long integer + // this is NTP time (seconds since Jan 1 1900): + unsigned long secsSince1900 = highWord << 16 | lowWord; + //Serial.print("Seconds since Jan 1 1900 = " ); + //Serial.println(secsSince1900); + + // now convert NTP time into everyday time: + //Serial.print("Unix time = "); + // Unix time starts on Jan 1 1970. In seconds, that's 2208988800: + const unsigned long seventyYears = 2208988800UL; + // subtract seventy years: + unsigned long epoch = secsSince1900 - seventyYears; + // print Unix time: + return epoch; + } + else{ + return 0; + } +} + +void digitprint(int value, int lenght){ + for (int i = 0; i < (lenght - numdigits(value)); i++){ + Serial.print("0"); + } + Serial.print(value); +} + +int numdigits(int i){ + int digits; + if (i < 10) + digits = 1; + else + digits = (int)(log10((double)i)) + 1; + return digits; +} diff --git a/hardware/digistump/sam/libraries/DigiFi/examples/ThingSpeak/Arduino_to_ThingSpeak/Arduino_to_ThingSpeak.ino b/hardware/digistump/sam/libraries/DigiFi/examples/ThingSpeak/Arduino_to_ThingSpeak/Arduino_to_ThingSpeak.ino new file mode 100644 index 0000000..e5189d6 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/examples/ThingSpeak/Arduino_to_ThingSpeak/Arduino_to_ThingSpeak.ino @@ -0,0 +1,99 @@ + +#include + +// ThingSpeak Settings +char thingSpeakAddress[] = "api.thingspeak.com"; +String writeAPIKey = "XXXMX2WYYR0EV68M"; +const int updateThingSpeakInterval = 16 * 1000; // Time interval in milliseconds to update ThingSpeak (number of seconds * 1000 = interval) + +// Variable Setup +long lastConnectionTime = 0; +int failedCounter = 0; + +// Initialize DigiFi +DigiFi client; + +void setup() +{ + // Start Serial for debugging on the Serial Monitor + Serial.begin(9600); + //DigiX trick - since we are on serial over USB wait for character to be entered in serial terminal + while(!Serial.available()){ + Serial.println("Enter any key to begin"); + delay(1000); + } + // Start DigiFi + startDigiFi(); +} + +void loop() +{ + // Read value from Analog Input Pin 0 + String analogPin0 = String(analogRead(A0), DEC); + + + // Update ThingSpeak + if(millis() - lastConnectionTime > updateThingSpeakInterval) + { + updateThingSpeak("field1="+analogPin0); + } + + // Check if Arduino Ethernet needs to be restarted + if (failedCounter > 3 ) {startDigiFi();} + +} + +void updateThingSpeak(String tsData) +{ + if (client.connect(thingSpeakAddress, 80)) + { + + lastConnectionTime = millis(); + if(wifi.post("api.thingspeak.com","/update","api_key="++writeAPIKey++"&status="+wifi.URLEncode(tsData))) + { + Serial.println("Sent to ThingSpeak"); + Serial.println(); + failedCounter = 0; + Serial.println(wifi.body()); + } + else + { + failedCounter++; + + Serial.println("Connection to ThingSpeak failed ("+String(failedCounter, DEC)+")"); + Serial.println(); + } + + } + else + { + failedCounter++; + + Serial.println("Connection to ThingSpeak Failed ("+String(failedCounter, DEC)+")"); + Serial.println(); + + lastConnectionTime = millis(); + } +} + +void startDigiFi() +{ + + + + Serial.println("Connecting Arduino to network..."); + Serial.println(); + + delay(1000); + + // Connect to network amd obtain an IP address using DHCP + client.begin(); + client.setDebug(true); + while (client.ready() != 1) + { + Serial.println("Connecting to network..."); + delay(1000); + } + + delay(1000); +} \ No newline at end of file diff --git a/hardware/digistump/sam/libraries/DigiFi/examples/basic/basic.ino b/hardware/digistump/sam/libraries/DigiFi/examples/basic/basic.ino new file mode 100644 index 0000000..89a032d --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/examples/basic/basic.ino @@ -0,0 +1,61 @@ +// DigiX WiFi module example - released by Digistump LLC/Erik Kettenburg under CC-BY-SA 3.0 +// Inspired by HttpClient library by MCQN Ltd. + +#include + +DigiFi wifi; + +void setup() +{ + // initialize serial communications at 9600 bps: + Serial.begin(9600); + wifi.begin(9600); + + //DigiX trick - since we are on serial over USB wait for character to be entered in serial terminal + while(!Serial.available()){ + Serial.println("Enter any key to begin"); + delay(1000); + } + + Serial.println("Starting"); + + while (wifi.ready() != 1) + { + Serial.println("Error connecting to network"); + delay(15000); + } + + Serial.println("Connected to wifi!"); + +//GET request example + + if(wifi.get("digistump.com","/test.txt")){ + String body = wifi.body(); + Serial.println(body); + } + else{ + Serial.println("error"); + + } + + //POST request example +Serial.println("Sending tweet!"); + //To use thingspeak for sending tweets see: http://community.thingspeak.com/documentation/apps/thingtweet/ + if(wifi.post("api.thingspeak.com","/apps/thingtweet/1/statuses/update","api_key=[YOURTHINGTWEETAPIKEY]&status="+wifi.URLEncode("Tweet from my new DigiX! #digix #digistump http://digistump.com"))){ + String body = wifi.body(); + Serial.println(body); + } + else{ + Serial.println("error"); + + } + + + wifi.close(); +} + +void loop() +{ + + +} \ No newline at end of file diff --git a/hardware/digistump/sam/libraries/DigiFi/examples/ping/ping.ino b/hardware/digistump/sam/libraries/DigiFi/examples/ping/ping.ino new file mode 100644 index 0000000..a5d3595 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiFi/examples/ping/ping.ino @@ -0,0 +1,33 @@ +#include +DigiFi wifi; + +void setup() +{ + Serial.begin(9600); + wifi.begin(9600); + + //DigiX trick - since we are on serial over USB wait for character to be entered in serial terminal + while(!Serial.available()){ + Serial.println("Enter any key to begin"); + delay(1000); + } + + Serial.println("Starting"); + + while (wifi.ready() != 1) + { + Serial.println("Error connecting to network"); + delay(15000); + } + + Serial.println("Connected to wifi!"); + wifi.startATMode(); + Serial.println(wifi.ping("192.168.2.1")); + wifi.endATMode(); + wifi.close(); +} + +void loop() +{ + +} diff --git a/hardware/digistump/sam/libraries/DigiXBetaBonus/Bonus_Encoder_Working/Bonus_Encoder_Working.ino b/hardware/digistump/sam/libraries/DigiXBetaBonus/Bonus_Encoder_Working/Bonus_Encoder_Working.ino new file mode 100644 index 0000000..5f2ba78 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiXBetaBonus/Bonus_Encoder_Working/Bonus_Encoder_Working.ino @@ -0,0 +1,70 @@ +/* Software Debouncing - Mechanical Rotary Encoder */ + +#define encoder0PinA 9 +#define encoder0PinB 10 +const int buttonPin = 12; +volatile unsigned int encoder0Pos = 0; +static boolean rotating=false; +int buttonState; // the current reading from the input pin +int lastButtonState = LOW; // the previous reading from the input pin +long lastDebounceTime = 0; // the last time the output pin was toggled +long debounceDelay = 50; // the debounce time; increase if the output flickers + +void setup() { + pinMode(buttonPin, INPUT); + digitalWrite(buttonPin, HIGH); + pinMode(encoder0PinA, INPUT); + digitalWrite(encoder0PinA, HIGH); + pinMode(encoder0PinB, INPUT); + digitalWrite(encoder0PinB, HIGH); + + attachInterrupt(encoder0PinA, rotEncoder, CHANGE); + SerialUSB.begin (9600); +} + +void rotEncoder(){ + rotating=true; + // If a signal change (noise or otherwise) is detected + // in the rotary encoder, the flag is set to true +} + +void loop() { + while(rotating) { + delay(2); + // When signal changes we wait 2 milliseconds for it to + // stabilise before reading (increase this value if there + // still bounce issues) + if (digitalRead(encoder0PinA) == digitalRead(encoder0PinB)) { + encoder0Pos++; + } + else { + encoder0Pos--; + } + rotating=false; // Reset the flag back to false + SerialUSB.println(encoder0Pos); + } + int reading = digitalRead(buttonPin); + + // check to see if you just pressed the button + // (i.e. the input went from LOW to HIGH), and you've waited + // long enough since the last press to ignore any noise: + + // If the switch changed, due to noise or pressing: + if (reading != lastButtonState) { + // reset the debouncing timer + lastDebounceTime = millis(); + SerialUSB.print("Button: "); + SerialUSB.println(reading); + } + + if ((millis() - lastDebounceTime) > debounceDelay) { + // whatever the reading is at, it's been there for longer + // than the debounce delay, so take it as the actual current state: + buttonState = reading; + } + + + // save the reading. Next time through the loop, + // it'll be the lastButtonState: + lastButtonState = reading; +} diff --git a/hardware/digistump/sam/libraries/DigiXBetaBonus/Bonus_IR_rec/Bonus_IR_rec.ino b/hardware/digistump/sam/libraries/DigiXBetaBonus/Bonus_IR_rec/Bonus_IR_rec.ino new file mode 100644 index 0000000..313f8ce --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiXBetaBonus/Bonus_IR_rec/Bonus_IR_rec.ino @@ -0,0 +1,27 @@ +int irPin=11; + +void setup() +{ + pinMode(irPin,INPUT); + pinMode(13,OUTPUT); + Serial.begin(9600); + digitalWrite(13,HIGH); + Serial.println("You pressed a button"); + delay(1000); + digitalWrite(13,LOW); +} + +void loop() +{ + + if(pulseIn(irPin,LOW)) + { + //button pressed + delay(100); + digitalWrite(13,HIGH); + Serial.println("You pressed a button"); + delay(1000); + digitalWrite(13,LOW); + } + +} \ No newline at end of file diff --git a/hardware/digistump/sam/libraries/DigiXBetaBonus/Bonus_RGB/Bonus_RGB.ino b/hardware/digistump/sam/libraries/DigiXBetaBonus/Bonus_RGB/Bonus_RGB.ino new file mode 100644 index 0000000..fb8a2b4 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiXBetaBonus/Bonus_RGB/Bonus_RGB.ino @@ -0,0 +1,20 @@ +int RedPin = 5; +int GreenPin = 6; +int BluePin = 7; + +void setup() { + // put your setup code here, to run once: + pinMode(RedPin, OUTPUT); + pinMode(GreenPin, OUTPUT); + pinMode(BluePin, OUTPUT); +} + +void loop() { + randomSeed(analogRead(0)); + // put your main code here, to run repeatedly: + analogWrite(RedPin,random(255)); + analogWrite(GreenPin,random(255)); + analogWrite(BluePin,random(255)); + + delay(500); +} diff --git a/hardware/digistump/sam/libraries/DigiXBetaBonus/Bonus_Temp/Bonus_Temp.ino b/hardware/digistump/sam/libraries/DigiXBetaBonus/Bonus_Temp/Bonus_Temp.ino new file mode 100644 index 0000000..1e97b45 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiXBetaBonus/Bonus_Temp/Bonus_Temp.ino @@ -0,0 +1,112 @@ +#include +//DigiX Bonus Shield Temp example - modfied by Erik Kettenburg, Digistump LLC from: +// OneWire DS18S20, DS18B20, DS1822 Temperature Example +// +// http://www.pjrc.com/teensy/td_libs_OneWire.html +// +// The DallasTemperature library can do all this work for you! +// http://milesburton.com/Dallas_Temperature_Control_Library + +OneWire ds(8); // on pin 10 (a 4.7K resistor is necessary) + +void setup(void) { + SerialUSB.begin(9600); +} + +void loop(void) { + byte i; + byte present = 0; + byte type_s; + byte data[12]; + byte addr[8]; + float celsius, fahrenheit; + + if ( !ds.search(addr)) { + SerialUSB.println("No more addresses."); + SerialUSB.println(); + ds.reset_search(); + delay(250); + return; + } + + SerialUSB.print("ROM ="); + for( i = 0; i < 8; i++) { + SerialUSB.write(' '); + SerialUSB.print(addr[i], HEX); + } + + if (OneWire::crc8(addr, 7) != addr[7]) { + SerialUSB.println("CRC is not valid!"); + return; + } + SerialUSB.println(); + + // the first ROM byte indicates which chip + switch (addr[0]) { + case 0x10: + SerialUSB.println(" Chip = DS18S20"); // or old DS1820 + type_s = 1; + break; + case 0x28: + SerialUSB.println(" Chip = DS18B20"); + type_s = 0; + break; + case 0x22: + SerialUSB.println(" Chip = DS1822"); + type_s = 0; + break; + default: + SerialUSB.println("Device is not a DS18x20 family device."); + return; + } + + ds.reset(); + ds.select(addr); + ds.write(0x44, 1); // start conversion, with parasite power on at the end + + delay(1000); // maybe 750ms is enough, maybe not + // we might do a ds.depower() here, but the reset will take care of it. + + present = ds.reset(); + ds.select(addr); + ds.write(0xBE); // Read Scratchpad + + SerialUSB.print(" Data = "); + SerialUSB.print(present, HEX); + SerialUSB.print(" "); + for ( i = 0; i < 9; i++) { // we need 9 bytes + data[i] = ds.read(); + SerialUSB.print(data[i], HEX); + SerialUSB.print(" "); + } + SerialUSB.print(" CRC="); + SerialUSB.print(OneWire::crc8(data, 8), HEX); + SerialUSB.println(); + + // Convert the data to actual temperature + // because the result is a 16 bit signed integer, it should + // be stored to an "int16_t" type, which is always 16 bits + // even when compiled on a 32 bit processor. + int16_t raw = (data[1] << 8) | data[0]; + if (type_s) { + raw = raw << 3; // 9 bit resolution default + if (data[7] == 0x10) { + // "count remain" gives full 12 bit resolution + raw = (raw & 0xFFF0) + 12 - data[6]; + } + } else { + byte cfg = (data[4] & 0x60); + // at lower res, the low bits are undefined, so let's zero them + if (cfg == 0x00) raw = raw & ~7; // 9 bit resolution, 93.75 ms + else if (cfg == 0x20) raw = raw & ~3; // 10 bit res, 187.5 ms + else if (cfg == 0x40) raw = raw & ~1; // 11 bit res, 375 ms + //// default is 12 bit resolution, 750 ms conversion time + } + celsius = (float)raw / 16.0; + fahrenheit = celsius * 1.8 + 32.0; + SerialUSB.print(" Temperature = "); + SerialUSB.print(celsius); + SerialUSB.print(" Celsius, "); + SerialUSB.print(fahrenheit); + SerialUSB.println(" Fahrenheit"); +} diff --git a/hardware/digistump/sam/libraries/DigiXEEPROM/Extensive_EEPROM.h b/hardware/digistump/sam/libraries/DigiXEEPROM/Extensive_EEPROM.h new file mode 100644 index 0000000..aa31509 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiXEEPROM/Extensive_EEPROM.h @@ -0,0 +1,179 @@ +/* +Extensive TWI/I2C EEPROM Library - for 24LCxxx devices +version: 0.4.1 +target device: Microchip 24LC256 or similar +compatibility: designed with Arduino Due +-> Ver. 0.4.1: Successfully tested with Arduino Uno R3 and Arduino Micro! +author: Dennis Schweer (Inglorious Engineer) +license: CC BY-SA 3.0 (http://creativecommons.org/licenses/by-sa/3.0/deed.en) + +Overview: + -bytewise reading/writing + void extEEPROMwrite(int chip_address, int address, byte value); + byte extEEPROMread(int chip_address, int address); + -pagewise reading/writing + void extEEPROMwritePage(int chip_address, int startaddress, byte* data_origin_array, int amount_of_transfered_bytes) + (!!!ATTENTION!!!: Limited to 30 Bytes only!) + void extEEPROMreadPage(int chip_address, int startaddress, byte* data_target_array, int amount_of_transfered_bytes) + (!!!ATTENTION!!!: Limited to 32 Bytes only) + Do not care about their size, just save them! + -read/write complete 32bit integers [Requires four bytes of your EEPROM.] + void extEEPROMwriteInt(int chip_address, int address, int data_to_be_stored) + int extEEPROMreadInt(int chip_address, int address) + -read/write your 10/12 bit sensor values (e.g., ADC values) [Requires two bytes of your EEPROM.] + void extEEPROMwriteSensor(int chip_address, int addresse, int data_to_be_stored) + int extEEPROMreadSensor(int chip_address, int addresse) + +NEW IN VERSION 0.4: +Now all functions include a device address parameter, allowing you to use two +or more external EEPROM chips simultaneously on a single bus. Just choose the +right device addresses and feet them into the library functions! + +NEW IN VERSION 0.4.1: +My library is designed with an Arduino Due, but now everything is successfully +tested to work on Arduino Uno R3 and Arduino Micro as well! Since all current +Arduinos are based on either ATmega328 (e.g., Uno), ATmega32U4 (e.g., Micro/ +Leonardo/Esplora) or ATSAM3X8E (Due), my library should work with ALL official +or 1:1-compatible boards. +!!! Unfortunately, Arduino Due appears to be the only device with the ability +to handle 32 bit integers. Hence none of my "writeInt" / "readInt" functions +run on 8-bit Arduinos !!! + + +Planned for future releases: + -erase byte + -erase page + -erase complete EEPROM + -read/write with autocorrection of "startaddress"-value +*/ + +#include "Arduino.h" +//========FUNCTIONS========================= + +///////////////// WRITE ///////////////////// + +void extEEPROMwrite(int EEPROM_addr, int addr, byte data) +{ + Wire.beginTransmission(EEPROM_addr); //Start transmission to EEPROM + Wire.write(highByte(addr)); // send high byte of address + Wire.write(lowByte(addr)); // send low byte of address + Wire.write((byte) data); // send data + Wire.endTransmission(true); // stop transmitting + delay(6); // wait for a successful write +} + +void extEEPROMwritePage(int EEPROM_addr, int addr, byte* data_origin, int amount) +{ + Wire.beginTransmission(EEPROM_addr); //Start transmission to EEPROM + Wire.write(highByte(addr)); // send high byte of address + Wire.write(lowByte(addr)); // send low byte of address + for(int i = 0; i> 8; + Wire.write(lowByte(data)); // send 2nd lowest byte of 32 bit integer + data = data >> 8; + Wire.write(lowByte(data)); // send 2nd highest byte of 32 bit integer + data = data >> 8; + Wire.write(lowByte(data)); // send highest byte of 32 bit integer + Wire.endTransmission(true); // stop transmitting + delay(6); // wait for a successful write +} + +void extEEPROMwriteSensor(int EEPROM_addr, int addr, int data) +{ + Wire.beginTransmission(EEPROM_addr); //Start transmission to EEPROM + Wire.write(highByte(addr)); // send high byte of address + Wire.write(lowByte(addr)); // send low byte of address + Wire.write(lowByte(data)); // send low byte of 12 bit integer + data = data >> 8; + Wire.write(lowByte(data)); // send high byte of 12 bit integer + Wire.endTransmission(true); // stop transmitting + delay(6); // wait for a successful write +} + +///////////////// READ ///////////////////// + +byte extEEPROMread(int EEPROM_addr, int addr) +{ + Wire.beginTransmission(EEPROM_addr); //Start transmission to EEPROM + Wire.write(highByte(addr)); // send high byte of address + Wire.write(lowByte(addr)); // send low byte of address + Wire.endTransmission(true); // stop transmitting + Wire.requestFrom(EEPROM_addr, 0x01, true); // request 1 byte form the device attached to EEPROM_addr + byte data_out = 64; + // read that byte + while(Wire.available() == 0) {} // wait for data + data_out = Wire.read(); //read single byte + return data_out; +} + +void extEEPROMreadPage(int EEPROM_addr, int addr, byte* data_target, int amount) +{ + Wire.beginTransmission(EEPROM_addr); //Start transmission to EEPROM + Wire.write(highByte(addr)); // send high byte of address + Wire.write(lowByte(addr)); // send low byte of address + Wire.endTransmission(true); // stop transmitting + Wire.requestFrom(EEPROM_addr, amount, true); // request 1 byte form the device attached to EEPROM_addr + // read that byte + while(Wire.available() == 0) {} // wait for data + for(int i = 0; i Ver. 0.4.1: Successfully tested with Arduino Uno R3 and Arduino Micro! +author: Dennis Schweer (Inglorious Engineer) +license: CC BY-SA 3.0 (http://creativecommons.org/licenses/by-sa/3.0/deed.en) + +Overview: + -bytewise reading/writing + void extEEPROMwrite(int chip_address, int address, byte value); + byte extEEPROMread(int chip_address, int address); + -pagewise reading/writing + void extEEPROMwritePage(int chip_address, int startaddress, byte* data_origin_array, int amount_of_transfered_bytes) + (!!!ATTENTION!!!: Limited to 30 Bytes only!) + void extEEPROMreadPage(int chip_address, int startaddress, byte* data_target_array, int amount_of_transfered_bytes) + (!!!ATTENTION!!!: Limited to 32 Bytes only) + Do not care about their size, just save them! + -read/write complete 32bit integers [Requires four bytes of your EEPROM.] + void extEEPROMwriteInt(int chip_address, int address, int data_to_be_stored) + int extEEPROMreadInt(int chip_address, int address) + -read/write your 10/12 bit sensor values (e.g., ADC values) [Requires two bytes of your EEPROM.] + void extEEPROMwriteSensor(int chip_address, int addresse, int data_to_be_stored) + int extEEPROMreadSensor(int chip_address, int addresse) + +NEW IN VERSION 0.4: +Now all functions include a device address parameter, allowing you to use two +or more external EEPROM chips simultaneously on a single bus. Just choose the +right device addresses and feet them into the library functions! + +NEW IN VERSION 0.4.1: +My library is designed with an Arduino Due, but now everything is successfully +tested to work on Arduino Uno R3 and Arduino Micro as well! Since all current +Arduinos are based on either ATmega328 (e.g., Uno), ATmega32U4 (e.g., Micro/ +Leonardo/Esplora) or ATSAM3X8E (Due), my library should work with ALL official +or 1:1-compatible boards. +!!! Unfortunately, Arduino Due appears to be the only device with the ability +to handle 32 bit integers. Hence none of my "writeInt" / "readInt" functions +run on 8-bit Arduinos !!! + + +Planned for future releases: + -erase byte + -erase page + -erase complete EEPROM + -read/write with autocorrection of "startaddress"-value +*/ +#include +#include + +const int EEPROM_addr = 0x50; + +// Testbed variables +int test = 1; + +void setup() +{ + Wire.begin(); // join i2c bus (address optional for master) + Serial.begin(9600); + test = 1; +} + +void loop() +{ + //Testbed + if(test == 1) //only run it once + { + //byte-wise writing/reading + Serial.println("//byte-wise writing/reading"); + for(int i = 0; i < 32; i++) + { + extEEPROMwrite(EEPROM_addr, i, i); //void extEEPROMwrite(int chip_address, int address, byte value); + } + int data_back; + for(int i = 0; i < 32; i++) + { + data_back = extEEPROMread(EEPROM_addr, i); //byte extEEPROMread(int chip_address, int address); + Serial.print("original data= "); + Serial.print(i); + Serial.print(" read_back= "); + Serial.println(data_back); + } + + + //page-wise writing/reading + Serial.println("//page-wise writing/reading"); + byte data_to_be_written[30]; + for(int i=0; i<30; i++) + { + data_to_be_written[i] = (29-i); //writes the numbers 29 downto 0 into cells 0-29 + Serial.print("Original Data = "); + Serial.println((29-i)); + } + //store array in EEPROM (max. 30 Bytes) + extEEPROMwritePage(EEPROM_addr, 32, data_to_be_written, 30); //void extEEPROMwritePage(int chip_address, int startaddress, byte* data_origin_array, int amount_of_transfered_bytes) + //read page into an array (max. 32 Bytes) + byte data_output[30]; + extEEPROMreadPage(EEPROM_addr, 32, data_output, 30); // void extEEPROMreadPage(int chip_address, int startaddress, byte* data_target_array, int amountof_transfered_bytes) + for(int j=0; j<30; j++) + { + Serial.print("Read Page= "); + Serial.println(data_output[j]); // Print array + } + + //write/read 32 bit integer + Serial.println("//write/read 32 bit integer"); + int original_int = 0x7FFFFFFF; + extEEPROMwriteInt(EEPROM_addr, 70, original_int); + int original_int_output; + original_int_output = extEEPROMreadInt(EEPROM_addr, 70); + Serial.print("Integer: in = "); + Serial.print(original_int); + Serial.print(" / out = "); + Serial.println(original_int_output); + + //write/read 10/12 bit sensor data + Serial.println("//write/read 10/12 bit sensor data"); + int original_sensor = 0x7FFF; + extEEPROMwriteInt(EEPROM_addr, 75, original_sensor); + int original_sensor_output; + original_sensor_output = extEEPROMreadInt(EEPROM_addr, 75); + Serial.print("Sensordata: in = "); + Serial.print(original_sensor); + Serial.print(" / out = "); + Serial.println(original_sensor_output); + + } + test = 2; // only perform this procedure once +} diff --git a/hardware/digistump/sam/libraries/DigiXLCD/LiquidCrystal_I2C.cpp b/hardware/digistump/sam/libraries/DigiXLCD/LiquidCrystal_I2C.cpp new file mode 100644 index 0000000..eeaebb3 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiXLCD/LiquidCrystal_I2C.cpp @@ -0,0 +1,321 @@ +// LiquidCrystal_I2C V2.0 + +#include "LiquidCrystal_I2C.h" +#include +#if defined(__AVR_ATtiny85__) || (__AVR_ATtiny2313__) +#include "TinyWireM.h" // include this if ATtiny85 or ATtiny2313 +#else +#include // original lib include +#endif +#include "Arduino.h" + + +// When the display powers up, it is configured as follows: +// +// 1. Display clear +// 2. Function set: +// DL = 1; 8-bit interface data +// N = 0; 1-line display +// F = 0; 5x8 dot character font +// 3. Display on/off control: +// D = 0; Display off +// C = 0; Cursor off +// B = 0; Blinking off +// 4. Entry mode set: +// I/D = 1; Increment by 1 +// S = 0; No shift +// +// Note, however, that resetting the Arduino doesn't reset the LCD, so we +// can't assume that its in that state when a sketch starts (and the +// LiquidCrystal constructor is called). + +LiquidCrystal_I2C::LiquidCrystal_I2C(uint8_t lcd_Addr,uint8_t lcd_cols,uint8_t lcd_rows) +{ + _Addr = lcd_Addr; + _cols = lcd_cols; + _rows = lcd_rows; + _backlightval = LCD_NOBACKLIGHT; +} + +void LiquidCrystal_I2C::init(){ + init_priv(); +} + +void LiquidCrystal_I2C::init_priv() +{ +#if defined (__AVR_ATtiny85__) || (__AVR_ATtiny2313__) + TinyWireM.begin(); // initialize I2C lib +#else // original call + Wire1.begin(); +#endif + _displayfunction = LCD_4BITMODE | LCD_1LINE | LCD_5x8DOTS; + begin(_cols, _rows); +} + +void LiquidCrystal_I2C::begin(uint8_t cols, uint8_t lines, uint8_t dotsize) { + if (lines > 1) { + _displayfunction |= LCD_2LINE; + } + _numlines = lines; + + // for some 1 line displays you can select a 10 pixel high font + if ((dotsize != 0) && (lines == 1)) { + _displayfunction |= LCD_5x10DOTS; + } + + // SEE PAGE 45/46 FOR INITIALIZATION SPECIFICATION! + // according to datasheet, we need at least 40ms after power rises above 2.7V + // before sending commands. Arduino can turn on way befer 4.5V so we'll wait 50 + delay(50); + + // Now we pull both RS and R/W low to begin commands + expanderWrite(_backlightval); // reset expanderand turn backlight off (Bit 8 =1) + delay(1000); + + //put the LCD into 4 bit mode + // this is according to the hitachi HD44780 datasheet + // figure 24, pg 46 + + // we start in 8bit mode, try to set 4 bit mode + write4bits(0x03 << 4); + delayMicroseconds(4500); // wait min 4.1ms + + // second try + write4bits(0x03 << 4); + delayMicroseconds(4500); // wait min 4.1ms + + // third go! + write4bits(0x03 << 4); + delayMicroseconds(150); + + // finally, set to 4-bit interface + write4bits(0x02 << 4); + + + + // set # lines, font size, etc. + command(LCD_FUNCTIONSET | _displayfunction); + + // turn the display on with no cursor or blinking default + _displaycontrol = LCD_DISPLAYON | LCD_CURSOROFF | LCD_BLINKOFF; + display(); + + // clear it off + clear(); + + // Initialize to default text direction (for roman languages) + _displaymode = LCD_ENTRYLEFT | LCD_ENTRYSHIFTDECREMENT; + + // set the entry mode + command(LCD_ENTRYMODESET | _displaymode); + + home(); + +} + + + +/********** high level commands, for the user! */ +void LiquidCrystal_I2C::clear(){ + command(LCD_CLEARDISPLAY);// clear display, set cursor position to zero + delayMicroseconds(2000); // this command takes a long time! +} + +void LiquidCrystal_I2C::home(){ + command(LCD_RETURNHOME); // set cursor position to zero + delayMicroseconds(2000); // this command takes a long time! +} + +void LiquidCrystal_I2C::setCursor(uint8_t col, uint8_t row){ + int row_offsets[] = { 0x00, 0x40, 0x14, 0x54 }; + if ( row > _numlines ) { + row = _numlines-1; // we count rows starting w/0 + } + command(LCD_SETDDRAMADDR | (col + row_offsets[row])); +} + +// Turn the display on/off (quickly) +void LiquidCrystal_I2C::noDisplay() { + _displaycontrol &= ~LCD_DISPLAYON; + command(LCD_DISPLAYCONTROL | _displaycontrol); +} +void LiquidCrystal_I2C::display() { + _displaycontrol |= LCD_DISPLAYON; + command(LCD_DISPLAYCONTROL | _displaycontrol); +} + +// Turns the underline cursor on/off +void LiquidCrystal_I2C::noCursor() { + _displaycontrol &= ~LCD_CURSORON; + command(LCD_DISPLAYCONTROL | _displaycontrol); +} +void LiquidCrystal_I2C::cursor() { + _displaycontrol |= LCD_CURSORON; + command(LCD_DISPLAYCONTROL | _displaycontrol); +} + +// Turn on and off the blinking cursor +void LiquidCrystal_I2C::noBlink() { + _displaycontrol &= ~LCD_BLINKON; + command(LCD_DISPLAYCONTROL | _displaycontrol); +} +void LiquidCrystal_I2C::blink() { + _displaycontrol |= LCD_BLINKON; + command(LCD_DISPLAYCONTROL | _displaycontrol); +} + +// These commands scroll the display without changing the RAM +void LiquidCrystal_I2C::scrollDisplayLeft(void) { + command(LCD_CURSORSHIFT | LCD_DISPLAYMOVE | LCD_MOVELEFT); +} +void LiquidCrystal_I2C::scrollDisplayRight(void) { + command(LCD_CURSORSHIFT | LCD_DISPLAYMOVE | LCD_MOVERIGHT); +} + +// This is for text that flows Left to Right +void LiquidCrystal_I2C::leftToRight(void) { + _displaymode |= LCD_ENTRYLEFT; + command(LCD_ENTRYMODESET | _displaymode); +} + +// This is for text that flows Right to Left +void LiquidCrystal_I2C::rightToLeft(void) { + _displaymode &= ~LCD_ENTRYLEFT; + command(LCD_ENTRYMODESET | _displaymode); +} + +// This will 'right justify' text from the cursor +void LiquidCrystal_I2C::autoscroll(void) { + _displaymode |= LCD_ENTRYSHIFTINCREMENT; + command(LCD_ENTRYMODESET | _displaymode); +} + +// This will 'left justify' text from the cursor +void LiquidCrystal_I2C::noAutoscroll(void) { + _displaymode &= ~LCD_ENTRYSHIFTINCREMENT; + command(LCD_ENTRYMODESET | _displaymode); +} + +// Allows us to fill the first 8 CGRAM locations +// with custom characters +void LiquidCrystal_I2C::createChar(uint8_t location, uint8_t charmap[]) { + location &= 0x7; // we only have 8 locations 0-7 + command(LCD_SETCGRAMADDR | (location << 3)); + for (int i=0; i<8; i++) { + write(charmap[i]); + } +} + +// Turn the (optional) backlight off/on +void LiquidCrystal_I2C::noBacklight(void) { + _backlightval=LCD_NOBACKLIGHT; + expanderWrite(0); +} + +void LiquidCrystal_I2C::backlight(void) { + _backlightval=LCD_BACKLIGHT; + expanderWrite(0); +} + + + +/*********** mid level commands, for sending data/cmds */ + +inline void LiquidCrystal_I2C::command(uint8_t value) { + send(value, 0); +} + +inline size_t LiquidCrystal_I2C::write(uint8_t value) { + send(value, Rs); + return 0; +} + + + + + +/************ low level data pushing commands **********/ + +// write either command or data +void LiquidCrystal_I2C::send(uint8_t value, uint8_t mode) { + uint8_t highnib=value&0xf0; + uint8_t lownib=(value<<4)&0xf0; + write4bits((highnib)|mode); + write4bits((lownib)|mode); +} + +void LiquidCrystal_I2C::write4bits(uint8_t value) { + expanderWrite(value); + pulseEnable(value); +} + +void LiquidCrystal_I2C::expanderWrite(uint8_t _data){ +#if defined(__AVR_ATtiny85__) || (__AVR_ATtiny2313__) // Replaced Wire calls with ATtiny TWI calls + TinyWireM.beginTransmission(_Addr); + TinyWireM.send(((int)(_data) | _backlightval)); + TinyWireM.endTransmission(); +#else // original lib function + Wire1.beginTransmission(_Addr); + Wire1.write((int)(_data) | _backlightval); + Wire1.endTransmission(); +#endif + } + +void LiquidCrystal_I2C::pulseEnable(uint8_t _data){ + expanderWrite(_data | En); // En high + delayMicroseconds(1); // enable pulse must be >450ns + + expanderWrite(_data & ~En); // En low + delayMicroseconds(50); // commands need > 37us to settle +} + + +// Alias functions + +void LiquidCrystal_I2C::cursor_on(){ + cursor(); +} + +void LiquidCrystal_I2C::cursor_off(){ + noCursor(); +} + +void LiquidCrystal_I2C::blink_on(){ + blink(); +} + +void LiquidCrystal_I2C::blink_off(){ + noBlink(); +} + +void LiquidCrystal_I2C::load_custom_character(uint8_t char_num, uint8_t *rows){ + createChar(char_num, rows); +} + +void LiquidCrystal_I2C::setBacklight(uint8_t new_val){ + if(new_val){ + backlight(); // turn backlight on + }else{ + noBacklight(); // turn backlight off + } +} + +void LiquidCrystal_I2C::printstr(const char c[]){ + //This function is not identical to the function used for "real" I2C displays + //it's here so the user sketch doesn't have to be changed + print(c); +} + + +// unsupported API functions +void LiquidCrystal_I2C::off(){} +void LiquidCrystal_I2C::on(){} +void LiquidCrystal_I2C::setDelay (int cmdDelay,int charDelay) {} +uint8_t LiquidCrystal_I2C::status(){return 0;} +uint8_t LiquidCrystal_I2C::keypad (){return 0;} +uint8_t LiquidCrystal_I2C::init_bargraph(uint8_t graphtype){return 0;} +void LiquidCrystal_I2C::draw_horizontal_graph(uint8_t row, uint8_t column, uint8_t len, uint8_t pixel_col_end){} +void LiquidCrystal_I2C::draw_vertical_graph(uint8_t row, uint8_t column, uint8_t len, uint8_t pixel_row_end){} +void LiquidCrystal_I2C::setContrast(uint8_t new_val){} + + \ No newline at end of file diff --git a/hardware/digistump/sam/libraries/DigiXLCD/LiquidCrystal_I2C.h b/hardware/digistump/sam/libraries/DigiXLCD/LiquidCrystal_I2C.h new file mode 100644 index 0000000..82ac972 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiXLCD/LiquidCrystal_I2C.h @@ -0,0 +1,135 @@ +// LiquidCrystal_I2C V2.0 +// Note: The original libe file has beem modified to support the ATtiny85 1/20/11 by "BroHogan" +// All changes can be located by searching for "__AVR_ATtiny85__". + +#ifndef LiquidCrystal_I2C_h +#define LiquidCrystal_I2C_h + +#include +#include "Print.h" + +#if defined(__AVR_ATtiny85__) || (__AVR_ATtiny2313__) +#include "TinyWireM.h" // include this if ATtiny85 or ATtiny2313 +#else +#include // original lib include +#endif + + +// commands +#define LCD_CLEARDISPLAY 0x01 +#define LCD_RETURNHOME 0x02 +#define LCD_ENTRYMODESET 0x04 +#define LCD_DISPLAYCONTROL 0x08 +#define LCD_CURSORSHIFT 0x10 +#define LCD_FUNCTIONSET 0x20 +#define LCD_SETCGRAMADDR 0x40 +#define LCD_SETDDRAMADDR 0x80 + +// flags for display entry mode +#define LCD_ENTRYRIGHT 0x00 +#define LCD_ENTRYLEFT 0x02 +#define LCD_ENTRYSHIFTINCREMENT 0x01 +#define LCD_ENTRYSHIFTDECREMENT 0x00 + +// flags for display on/off control +#define LCD_DISPLAYON 0x04 +#define LCD_DISPLAYOFF 0x00 +#define LCD_CURSORON 0x02 +#define LCD_CURSOROFF 0x00 +#define LCD_BLINKON 0x01 +#define LCD_BLINKOFF 0x00 + +// flags for display/cursor shift +#define LCD_DISPLAYMOVE 0x08 +#define LCD_CURSORMOVE 0x00 +#define LCD_MOVERIGHT 0x04 +#define LCD_MOVELEFT 0x00 + +// flags for function set +#define LCD_8BITMODE 0x10 +#define LCD_4BITMODE 0x00 +#define LCD_2LINE 0x08 +#define LCD_1LINE 0x00 +#define LCD_5x10DOTS 0x04 +#define LCD_5x8DOTS 0x00 + +// flags for backlight control +#define LCD_BACKLIGHT 0x08 +#define LCD_NOBACKLIGHT 0x00 + +#define En B00000100 // Enable bit +#define Rw B00000010 // Read/Write bit +#define Rs B00000001 // Register select bit + +class LiquidCrystal_I2C : public Print { +public: + LiquidCrystal_I2C(uint8_t lcd_Addr,uint8_t lcd_cols,uint8_t lcd_rows); + void begin(uint8_t cols, uint8_t rows, uint8_t charsize = LCD_5x8DOTS ); + void clear(); + void home(); + void noDisplay(); + void display(); + void noBlink(); + void blink(); + void noCursor(); + void cursor(); + void scrollDisplayLeft(); + void scrollDisplayRight(); + void printLeft(); + void printRight(); + void leftToRight(); + void rightToLeft(); + void shiftIncrement(); + void shiftDecrement(); + void noBacklight(); + void backlight(); + void autoscroll(); + void noAutoscroll(); + void createChar(uint8_t, uint8_t[]); + void setCursor(uint8_t, uint8_t); +#if defined(ARDUINO) && ARDUINO >= 100 + virtual size_t write(uint8_t); +#else + virtual void write(uint8_t); +#endif + void command(uint8_t); + void init(); + +////compatibility API function aliases +void blink_on(); // alias for blink() +void blink_off(); // alias for noBlink() +void cursor_on(); // alias for cursor() +void cursor_off(); // alias for noCursor() +void setBacklight(uint8_t new_val); // alias for backlight() and nobacklight() +void load_custom_character(uint8_t char_num, uint8_t *rows); // alias for createChar() +void printstr(const char[]); + +////Unsupported API functions (not implemented in this library) +uint8_t status(); +void setContrast(uint8_t new_val); +uint8_t keypad(); +void setDelay(int,int); +void on(); +void off(); +uint8_t init_bargraph(uint8_t graphtype); +void draw_horizontal_graph(uint8_t row, uint8_t column, uint8_t len, uint8_t pixel_col_end); +void draw_vertical_graph(uint8_t row, uint8_t column, uint8_t len, uint8_t pixel_col_end); + + +private: + void init_priv(); + void send(uint8_t, uint8_t); + void write4bits(uint8_t); + void expanderWrite(uint8_t); + void pulseEnable(uint8_t); + uint8_t _Addr; + uint8_t _displayfunction; + uint8_t _displaycontrol; + uint8_t _displaymode; + uint8_t _numlines; + uint8_t _cols; + uint8_t _rows; + uint8_t _backlightval; +}; + +#endif diff --git a/hardware/digistump/sam/libraries/DigiXLCD/examples/BasicUsage/BasicUsage.ino b/hardware/digistump/sam/libraries/DigiXLCD/examples/BasicUsage/BasicUsage.ino new file mode 100644 index 0000000..9f648ee --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiXLCD/examples/BasicUsage/BasicUsage.ino @@ -0,0 +1,26 @@ +/* ATtiny85 as an I2C Master Ex2 BroHogan 1/21/11 + * Modified for Digistump/DigiX - Digispark LCD Shield by Erik Kettenburg 11/2012 + */ + +//#define DEBUG +#include // I2C Master lib for ATTinys which use USI - comment this out to use with standard arduinos +#include // for LCD w/ GPIO MODIFIED for the ATtiny85 + +#define GPIO_ADDR 0x27 // (PCA8574A A0-A2 @5V) typ. A0-A3 Gnd 0x20 / 0x38 for A - 0x27 is the address of the Digispark LCD modules. + + +LiquidCrystal_I2C lcd(GPIO_ADDR,16,2); // set address & 16 chars / 2 lines + + +void setup(){ + Wire1.begin(); // initialize I2C lib - comment this out to use with standard arduinos + lcd.init(); // initialize the lcd + lcd.backlight(); + lcd.print("DigiX!"); // Print a message to the LCD. +} + + +void loop(){ + +} + diff --git a/hardware/digistump/sam/libraries/DigiXLCD/info/BC557.pdf b/hardware/digistump/sam/libraries/DigiXLCD/info/BC557.pdf new file mode 100644 index 0000000..05790db --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiXLCD/info/BC557.pdf @@ -0,0 +1,122 @@ +BC 556 ... BC 559 General Purpose Transistors +PNP + Si-Epitaxial PlanarTransistors PNP + Standard Pinning + 1=C 2=B 3=E Power dissipation – Verlustleistung 500 mW + + Plastic case TO-92 + Kunststoffgehäuse (10D3) + + Weight approx. – Gewicht ca. 0.18 g + + Plastic material has UL classification 94V-0 + Gehäusematerial UL94V-0 klassifiziert + + Standard packaging taped in ammo pack + Standard Lieferform gegurtet in Ammo-Pack + +Maximum ratings (TA = 25/C) Grenzwerte (TA = 25/C) + + BC 556 BC 557 BC 558/559 + 65 V +Collector-Emitter-voltage B open - VCE0 80 V 45 V 30 V + - VCB0 +Collector-Base-voltage E open - VEB0 50 V 30 V + Ptot +Emitter-Base-voltage C open - IC 5V + Tj +Power dissipation – Verlustleistung TS 500 mW 1) + +Collector current – Kollektorstrom (DC) 100 mA + +Junction temp. – Sperrschichttemperatur 150/C + - 55…+ 150/C +Storage temperature – Lagerungstemperatur + +Characteristics (Tj = 25/C) Kennwerte (Tj = 25/C) + + Group A Group B Group C + +DC current gain – Kollektor-Basis-Stromverhältnis 110...220 + + - VCE = 5 V, - IC = 2 mA hFE typ. 220 200...460 420...800 + +h-Parameters at - VCE = 5V, - IC = 2 mA, f = 1 kHz 1.6...4.5 kS + 18 < 30 :S + Small signal current gain hfe typ. 330 typ. 600 + Stromverstärkung typ.1.5 *10-4 + + Input impedance – Eingangsimpedanz hie – 3.2...8.5 kS 6...15 kS + 30 < 60 :S 60 < 110 :S + Output admittance – Ausg.-Leitwert hoe + + Reverse voltage transfer ratio hre typ. 2 *10-4 typ. 3 *10-4 + Spannungsrückwirkung + +Collector saturation voltage – Kollektor-Sättigungsspg. + + - IC = 100 mA, - IB = 5 mA -VCEsat – 300 mV + +1) Valid, if leads are kept at ambient temperature at a distance of 2 mm from case + + Gültig, wenn die Anschlußdrähte in 2 mm Abstand von Gehäuse auf Umgebungstemperatur gehalten werden + +8 01.11.2003 + General Purpose Transistors BC 556 ... BC 559 + +Characteristics (Tj = 25/C) Kennwerte (Tj = 25/C) + + Min. Typ. Max. + +Base saturation voltage – Basis-Sättigungsspannung + + - IC = 100 mA, - IB = 5 mA - VBEsat – – 1V +Base-Emitter voltage – Basis-Emitter-Spannung + +- VCE = 5 V, - IC = 2 mA - VBE 580 mV 660 mV 700 mV + +Collector-Emitter cutoff current – Kollektorreststrom + +- VCE = 60 V BC 556 - ICE0 – – 0.1 :A + - ICE0 +- VCE = 40 V BC 557 - ICE0 – – 0.1 :A + - ICE0 +- VCE = 25 V BC 558 – – 0.1 :A + +- VCE = 25 V BC 559 – – 0.1 :A + +Gain-Bandwidth Product – Transitfrequenz + +- VCE = 5 V, - IC = 10 mA, f = 100 MHz fT 150 MHz – – + +Collector-Base Capacitance – Kollektor-Basis-Kapazität + +- VCB = 10 V, IE = ie = 0, f = 1 MHz CCB0 – – 6 pF + +Emitter-Base Capacitance – Emitter-Basis-Kapazität + + - VEB = 0.5 V, f = 1 MHz CEB0 – 9 pF – +Noise figure – Rauschzahl + BC 556... – 2 dB 10 dB + - VCE = 5 V, - IC = 200 :A F + RG = 2 kS f = 1 kHz, – 1 dB 4 dB + )f = 200 Hz BC 558 + BC 559 F + +Thermal resistance junction to ambient air RthA 200 K/W 1) +Wärmewiderstand Sperrschicht – umgebende Luft + +Recommended complementary PNP transistors BC 546 ... BC 549 +Empfohlene komplementäre PNP-Transistoren + +Available current gain groups per type BC 556A BC 556B BC 557C +Lieferbare Stromverstärkungsgruppen pro Typ BC 557A BC 557B BC 558C + BC 558A BC 558B BC 559C + BC 559B + +1) Valid, if leads are kept at ambient temperature at a distance of 2 mm from case + +Gültig, wenn die Anschlußdrähte in 2 mm Abstand von Gehäuse auf Umgebungstemperatur gehalten werden + +01.11.2003 9 + diff --git a/hardware/digistump/sam/libraries/DigiXLCD/info/Image.jpg b/hardware/digistump/sam/libraries/DigiXLCD/info/Image.jpg new file mode 100644 index 0000000..a72b23d Binary files /dev/null and b/hardware/digistump/sam/libraries/DigiXLCD/info/Image.jpg differ diff --git a/hardware/digistump/sam/libraries/DigiXLCD/info/PCF8574P.pdf b/hardware/digistump/sam/libraries/DigiXLCD/info/PCF8574P.pdf new file mode 100644 index 0000000..e164e76 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiXLCD/info/PCF8574P.pdf @@ -0,0 +1 @@ + diff --git a/hardware/digistump/sam/libraries/DigiXLCD/info/Schematic_diagram.jpg b/hardware/digistump/sam/libraries/DigiXLCD/info/Schematic_diagram.jpg new file mode 100644 index 0000000..920ea2b Binary files /dev/null and b/hardware/digistump/sam/libraries/DigiXLCD/info/Schematic_diagram.jpg differ diff --git a/hardware/digistump/sam/libraries/DigiXLCD/info/notes_for_pollin_interface.txt b/hardware/digistump/sam/libraries/DigiXLCD/info/notes_for_pollin_interface.txt new file mode 100644 index 0000000..4aaa1bc --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiXLCD/info/notes_for_pollin_interface.txt @@ -0,0 +1,55 @@ +Notes for users with a Pollin.de interface board +http://www.pollin.de/shop/dt/NDU4OTgxOTk-/Bausaetze_Module/Bausaetze/LCD_I2C_Modul.html + +The pollin interface board will not work with de default library. +To get it working two control lines to the LCD need to be changed. + +Open file "LiquidCrystal_I2C.h" with a text editor like Notepad (not WordPad !) + +In that file look for: +#define En B00010000 // Enable bit +#define Rw B00100000 // Read/Write bit +#define Rs B01000000 // Register select bit + +Replace these lines by: +#define En B01000000 // Enable bit +#define Rw B00100000 // Read/Write bit +#define Rs B00010000 // Register select bit + + + +People at Pollin also have misunderstood the PCF8574 Datasheet and list the wrong addresses on their PCB +For PCF8574A the addressing is: + +Jp3 Jp2 Jp1 +A2 A1 A0 Dec Hex +L L L 56 0x38 +L L H 57 0x39 +L H L 64 0x40 +L H H 74 0x4A +H L L 75 0x4B +H L H 76 0x4C +H H L 77 0x4D +H H H 78 0x4E + +They also seem to ship boards with a PCF8574 +For PCF8574 the addressing is: + +Jp3 Jp2 Jp1 +A2 A1 A0 Dec Hex +L L L 32 0x20 +L L H 33 0x21 +L H L 34 0x22 +L H H 35 0x23 +H L L 36 0x24 +H L H 37 0x25 +H H L 38 0x26 +H H H 39 0x27 + + +They have also chosen two rather high pull-up resistors (10K) for the I2C lines. Usually two 4K7 resistors should do the job. +Please note that on a I2C bus only one device should have the pull-up resistors installed! + +I hope this helps in getting your LCD working. + +Mario \ No newline at end of file diff --git a/hardware/digistump/sam/libraries/DigiXLCD/info/readme.txt b/hardware/digistump/sam/libraries/DigiXLCD/info/readme.txt new file mode 100644 index 0000000..7a7f0a7 --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiXLCD/info/readme.txt @@ -0,0 +1,36 @@ +LiquidCrystal_I2C V2.0 + +The LiquidCrystal_I2C library is a modified version of the standard LiquidCrystal library as found on +the Arduino website. +This library is intended to be used when a parallel HD44780 compatible LCD is controlled over I2C using +a PCF8574 extender (see datasheet for details). +4 of the 8 outputs are used for LDC data lines 4 to 7. +3 outputs are used for the Enable, register-select and Read/Write lines. +The one output left can be used to control the backlight of the LCD (if available). +For backlight control some extra resistors and a pnp-type transistor are required (for details see +schematic diagram). + +The PCF8574 extender is available in two versions, the PCF8574 and the PCF8574A. +The only difference between the two is the I2C base address. +The base address for the PCF8574 is 0x20 and the base address for the PCF8574A is 0x38. +The examples included in this zip file assume the use of an PCF8574 set for address 0x20 +(A0, A1 and A3 grounded). + +For compatibility reasons this library contains some aliases for functions that are known under different +names in other libraries. This should make it fairly easy to implement the library in existing sketches +without changing to much code. +Functions not supported by this library will return nothing at all and in case a return value is expected +the function will return 0. + +Update 8-12-2011: +Due to the relaese of Arduino IDE 1.0 some changes were made to the library to get it working under the new IDE. +Because of these changes this version of the LiquidCrystal_I2C library can not be used for older IDE versions. +The old version of the LiquidCrystal_I2Clibrary can be downloaded form http://www.xs4all.nl/~hmario/arduino/LiquidCrystal_I2C/V1.0/LiquidCrystal_I2C_V1.0.zip + +Download the latest version from: +http://www.xs4all.nl/~hmario/arduino/LiquidCrystal_I2C/LiquidCrystal_I2C.zip +(Thanks to Ailton F. for beta testing.) + + +Mario H. +atmega@xs4all.nl \ No newline at end of file diff --git a/hardware/digistump/sam/libraries/DigiXLCD/keywords.txt b/hardware/digistump/sam/libraries/DigiXLCD/keywords.txt new file mode 100644 index 0000000..198480f --- /dev/null +++ b/hardware/digistump/sam/libraries/DigiXLCD/keywords.txt @@ -0,0 +1,47 @@ +########################################### +# Syntax Coloring Map For LiquidCrystal_I2C +# Version 2.0 +########################################### + +########################################### +# Datatypes (KEYWORD1) +########################################### + +LiquidCrystal_I2C KEYWORD1 + +########################################### +# Methods and Functions (KEYWORD2) +########################################### +init KEYWORD2 +begin KEYWORD2 +clear KEYWORD2 +home KEYWORD2 +noDisplay KEYWORD2 +display KEYWORD2 +noBlink KEYWORD2 +blink KEYWORD2 +noCursor KEYWORD2 +cursor KEYWORD2 +scrollDisplayLeft KEYWORD2 +scrollDisplayRight KEYWORD2 +leftToRight KEYWORD2 +rightToLeft KEYWORD2 +shiftIncrement KEYWORD2 +shiftDecrement KEYWORD2 +noBacklight KEYWORD2 +backlight KEYWORD2 +autoscroll KEYWORD2 +noAutoscroll KEYWORD2 +createChar KEYWORD2 +setCursor KEYWORD2 +print KEYWORD2 +blink_on KEYWORD2 +blink_off KEYWORD2 +cursor_on KEYWORD2 +cursor_off KEYWORD2 +setBacklight KEYWORD2 +load_custom_character KEYWORD2 +printstr KEYWORD2 +########################################### +# Constants (LITERAL1) +########################################### diff --git a/hardware/digistump/sam/libraries/I2Cdev/I2Cdev.cpp b/hardware/digistump/sam/libraries/I2Cdev/I2Cdev.cpp new file mode 100644 index 0000000..0d81a9b --- /dev/null +++ b/hardware/digistump/sam/libraries/I2Cdev/I2Cdev.cpp @@ -0,0 +1,1405 @@ +// I2Cdev library collection - Main I2C device class +// Abstracts bit and byte I2C R/W functions into a convenient class +// 6/9/2012 by Jeff Rowberg +// +// Changelog: +// 2013-05-05 - fix issue with writing bit values to words (Sasquatch/Farzanegan) +// 2012-06-09 - fix major issue with reading > 32 bytes at a time with Arduino Wire +// - add compiler warnings when using outdated or IDE or limited I2Cdev implementation +// 2011-11-01 - fix write*Bits mask calculation (thanks sasquatch @ Arduino forums) +// 2011-10-03 - added automatic Arduino version detection for ease of use +// 2011-10-02 - added Gene Knight's NBWire TwoWire class implementation with small modifications +// 2011-08-31 - added support for Arduino 1.0 Wire library (methods are different from 0.x) +// 2011-08-03 - added optional timeout parameter to read* methods to easily change from default +// 2011-08-02 - added support for 16-bit registers +// - fixed incorrect Doxygen comments on some methods +// - added timeout value for read operations (thanks mem @ Arduino forums) +// 2011-07-30 - changed read/write function structures to return success or byte counts +// - made all methods static for multi-device memory savings +// 2011-07-28 - initial release + + +/* ============================================ +I2Cdev device library code is placed under the MIT license +Copyright (c) 2012 Jeff Rowberg + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +=============================================== +*/ + +#include "I2Cdev.h" + +#if I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE + + #ifdef I2CDEV_IMPLEMENTATION_WARNINGS + #if ARDUINO < 100 + #warning Using outdated Arduino IDE with Wire library is functionally limiting. + #warning Arduino IDE v1.0.1+ with I2Cdev Fastwire implementation is recommended. + #warning This I2Cdev implementation does not support: + #warning - Repeated starts conditions + #warning - Timeout detection (some Wire requests block forever) + #elif ARDUINO == 100 + #warning Using outdated Arduino IDE with Wire library is functionally limiting. + #warning Arduino IDE v1.0.1+ with I2Cdev Fastwire implementation is recommended. + #warning This I2Cdev implementation does not support: + #warning - Repeated starts conditions + #warning - Timeout detection (some Wire requests block forever) + #elif ARDUINO > 100 + /* + #warning Using current Arduino IDE with Wire library is functionally limiting. + #warning Arduino IDE v1.0.1+ with I2CDEV_BUILTIN_FASTWIRE implementation is recommended. + #warning This I2Cdev implementation does not support: + #warning - Timeout detection (some Wire requests block forever) + */ + #endif + #endif + +#elif I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_FASTWIRE + + #error The I2CDEV_BUILTIN_FASTWIRE implementation is known to be broken right now. Patience, Iago! + +#elif I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_NBWIRE + + #ifdef I2CDEV_IMPLEMENTATION_WARNINGS + #warning Using I2CDEV_BUILTIN_NBWIRE implementation may adversely affect interrupt detection. + #warning This I2Cdev implementation does not support: + #warning - Repeated starts conditions + #endif + + // NBWire implementation based heavily on code by Gene Knight + // Originally posted on the Arduino forum at http://arduino.cc/forum/index.php/topic,70705.0.html + // Originally offered to the i2cdevlib project at http://arduino.cc/forum/index.php/topic,68210.30.html + TwoWire Wire; + +#elif I2CDEV_IMPLEMENTATION == I2CDEV_I2CMASTER_LIBRARY + + #warning Dunno, just don't want it to feel left out ^_^' + +#endif + +/** Default constructor. + */ +I2Cdev::I2Cdev() { +} + +/** Read a single bit from an 8-bit device register. + * @param devAddr I2C slave device address + * @param regAddr Register regAddr to read from + * @param bitNum Bit position to read (0-7) + * @param data Container for single bit value + * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout) + * @return Status of read operation (true = success) + */ +int8_t I2Cdev::readBit(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint8_t *data, uint16_t timeout) { + uint8_t b; + uint8_t count = readByte(devAddr, regAddr, &b, timeout); + *data = b & (1 << bitNum); + return count; +} + +/** Read a single bit from a 16-bit device register. + * @param devAddr I2C slave device address + * @param regAddr Register regAddr to read from + * @param bitNum Bit position to read (0-15) + * @param data Container for single bit value + * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout) + * @return Status of read operation (true = success) + */ +int8_t I2Cdev::readBitW(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint16_t *data, uint16_t timeout) { + uint16_t b; + uint8_t count = readWord(devAddr, regAddr, &b, timeout); + *data = b & (1 << bitNum); + return count; +} + +/** Read multiple bits from an 8-bit device register. + * @param devAddr I2C slave device address + * @param regAddr Register regAddr to read from + * @param bitStart First bit position to read (0-7) + * @param length Number of bits to read (not more than 8) + * @param data Container for right-aligned value (i.e. '101' read from any bitStart position will equal 0x05) + * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout) + * @return Status of read operation (true = success) + */ +int8_t I2Cdev::readBits(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint8_t *data, uint16_t timeout) { + // 01101001 read byte + // 76543210 bit numbers + // xxx args: bitStart=4, length=3 + // 010 masked + // -> 010 shifted + uint8_t count, b; + if ((count = readByte(devAddr, regAddr, &b, timeout)) != 0) { + uint8_t mask = ((1 << length) - 1) << (bitStart - length + 1); + b &= mask; + b >>= (bitStart - length + 1); + *data = b; + } + return count; +} + +/** Read multiple bits from a 16-bit device register. + * @param devAddr I2C slave device address + * @param regAddr Register regAddr to read from + * @param bitStart First bit position to read (0-15) + * @param length Number of bits to read (not more than 16) + * @param data Container for right-aligned value (i.e. '101' read from any bitStart position will equal 0x05) + * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout) + * @return Status of read operation (1 = success, 0 = failure, -1 = timeout) + */ +int8_t I2Cdev::readBitsW(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint16_t *data, uint16_t timeout) { + // 1101011001101001 read byte + // fedcba9876543210 bit numbers + // xxx args: bitStart=12, length=3 + // 010 masked + // -> 010 shifted + uint8_t count; + uint16_t w; + if ((count = readWord(devAddr, regAddr, &w, timeout)) != 0) { + uint16_t mask = ((1 << length) - 1) << (bitStart - length + 1); + w &= mask; + w >>= (bitStart - length + 1); + *data = w; + } + return count; +} + +/** Read single byte from an 8-bit device register. + * @param devAddr I2C slave device address + * @param regAddr Register regAddr to read from + * @param data Container for byte value read from device + * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout) + * @return Status of read operation (true = success) + */ +int8_t I2Cdev::readByte(uint8_t devAddr, uint8_t regAddr, uint8_t *data, uint16_t timeout) { + return readBytes(devAddr, regAddr, 1, data, timeout); +} + +/** Read single word from a 16-bit device register. + * @param devAddr I2C slave device address + * @param regAddr Register regAddr to read from + * @param data Container for word value read from device + * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout) + * @return Status of read operation (true = success) + */ +int8_t I2Cdev::readWord(uint8_t devAddr, uint8_t regAddr, uint16_t *data, uint16_t timeout) { + return readWords(devAddr, regAddr, 1, data, timeout); +} + +/** Read multiple bytes from an 8-bit device register. + * @param devAddr I2C slave device address + * @param regAddr First register regAddr to read from + * @param length Number of bytes to read + * @param data Buffer to store read data in + * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout) + * @return Number of bytes read (-1 indicates failure) + */ +int8_t I2Cdev::readBytes(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint8_t *data, uint16_t timeout) { + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print("I2C (0x"); + Serial.print(devAddr, HEX); + Serial.print(") reading "); + Serial.print(length, DEC); + Serial.print(" bytes from 0x"); + Serial.print(regAddr, HEX); + Serial.print("..."); + #endif + + int8_t count = 0; + uint32_t t1 = millis(); + + #if (I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE) + + #if (ARDUINO < 100) + // Arduino v00xx (before v1.0), Wire library + + // I2C/TWI subsystem uses internal buffer that breaks with large data requests + // so if user requests more than BUFFER_LENGTH bytes, we have to do it in + // smaller chunks instead of all at once + for (uint8_t k = 0; k < length; k += min(length, BUFFER_LENGTH)) { + Wire1.beginTransmission(devAddr); + Wire1.send(regAddr); + Wire1.endTransmission(); + Wire1.beginTransmission(devAddr); + Wire1.requestFrom(devAddr, (uint8_t)min(length - k, BUFFER_LENGTH)); + + for (; Wire1.available() && (timeout == 0 || millis() - t1 < timeout); count++) { + data[count] = Wire1.receive(); + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print(data[count], HEX); + if (count + 1 < length) Serial.print(" "); + #endif + } + + Wire1.endTransmission(); + } + #elif (ARDUINO == 100) + // Arduino v1.0.0, Wire library + // Adds standardized write() and read() stream methods instead of send() and receive() + + // I2C/TWI subsystem uses internal buffer that breaks with large data requests + // so if user requests more than BUFFER_LENGTH bytes, we have to do it in + // smaller chunks instead of all at once + for (uint8_t k = 0; k < length; k += min(length, BUFFER_LENGTH)) { + Wire1.beginTransmission(devAddr); + Wire1.write(regAddr); + Wire1.endTransmission(); + Wire1.beginTransmission(devAddr); + Wire1.requestFrom(devAddr, (uint8_t)min(length - k, BUFFER_LENGTH)); + + for (; Wire1.available() && (timeout == 0 || millis() - t1 < timeout); count++) { + data[count] = Wire1.read(); + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print(data[count], HEX); + if (count + 1 < length) Serial.print(" "); + #endif + } + + Wire1.endTransmission(); + } + #elif (ARDUINO > 100) + // Arduino v1.0.1+, Wire library + // Adds official support for repeated start condition, yay! + + // I2C/TWI subsystem uses internal buffer that breaks with large data requests + // so if user requests more than BUFFER_LENGTH bytes, we have to do it in + // smaller chunks instead of all at once + for (uint8_t k = 0; k < length; k += min(length, BUFFER_LENGTH)) { + Wire1.beginTransmission(devAddr); + Wire1.write(regAddr); + Wire1.endTransmission(); + Wire1.beginTransmission(devAddr); + Wire1.requestFrom(devAddr, (uint8_t)min(length - k, BUFFER_LENGTH)); + + for (; Wire1.available() && (timeout == 0 || millis() - t1 < timeout); count++) { + data[count] = Wire1.read(); + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print(data[count], HEX); + if (count + 1 < length) Serial.print(" "); + #endif + } + + Wire1.endTransmission(); + } + #endif + + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_FASTWIRE) + // Fastwire library (STILL UNDER DEVELOPMENT, NON-FUNCTIONAL!) + + // no loop required for fastwire + uint8_t status = Fastwire::readBuf(devAddr, regAddr, data, length); + if (status == 0) { + count = length; // success + } else { + count = -1; // error + } + + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_I2CMASTER_LIBRARY) + + uint8_t status = I2c.read(devAddr, regAddr, length, data); + if(status == 0) { + count = length; + } else { + count = -1 * status; + } + + #endif + + // check for timeout + if (timeout > 0 && millis() - t1 >= timeout && count < length) count = -1; // timeout + + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print(". Done ("); + Serial.print(count, DEC); + Serial.println(" read)."); + #endif + + return count; +} + +/** Read multiple words from a 16-bit device register. + * @param devAddr I2C slave device address + * @param regAddr First register regAddr to read from + * @param length Number of words to read + * @param data Buffer to store read data in + * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev::readTimeout) + * @return Number of words read (0 indicates failure) + */ +int8_t I2Cdev::readWords(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint16_t *data, uint16_t timeout) { + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print("I2C (0x"); + Serial.print(devAddr, HEX); + Serial.print(") reading "); + Serial.print(length, DEC); + Serial.print(" words from 0x"); + Serial.print(regAddr, HEX); + Serial.print("..."); + #endif + + int8_t count = 0; + uint32_t t1 = millis(); + + #if (I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE) + + #if (ARDUINO < 100) + // Arduino v00xx (before v1.0), Wire library + + // I2C/TWI subsystem uses internal buffer that breaks with large data requests + // so if user requests more than BUFFER_LENGTH bytes, we have to do it in + // smaller chunks instead of all at once + for (uint8_t k = 0; k < length * 2; k += min(length * 2, BUFFER_LENGTH)) { + Wire1.beginTransmission(devAddr); + Wire1.send(regAddr); + Wire1.endTransmission(); + Wire1.beginTransmission(devAddr); + Wire1.requestFrom(devAddr, (uint8_t)(length * 2)); // length=words, this wants bytes + + bool msb = true; // starts with MSB, then LSB + for (; Wire1.available() && count < length && (timeout == 0 || millis() - t1 < timeout);) { + if (msb) { + // first byte is bits 15-8 (MSb=15) + data[count] = Wire1.receive() << 8; + } else { + // second byte is bits 7-0 (LSb=0) + data[count] |= Wire1.receive(); + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print(data[count], HEX); + if (count + 1 < length) Serial.print(" "); + #endif + count++; + } + msb = !msb; + } + + Wire1.endTransmission(); + } + #elif (ARDUINO == 100) + // Arduino v1.0.0, Wire library + // Adds standardized write() and read() stream methods instead of send() and receive() + + // I2C/TWI subsystem uses internal buffer that breaks with large data requests + // so if user requests more than BUFFER_LENGTH bytes, we have to do it in + // smaller chunks instead of all at once + for (uint8_t k = 0; k < length * 2; k += min(length * 2, BUFFER_LENGTH)) { + Wire1.beginTransmission(devAddr); + Wire1.write(regAddr); + Wire1.endTransmission(); + Wire1.beginTransmission(devAddr); + Wire1.requestFrom(devAddr, (uint8_t)(length * 2)); // length=words, this wants bytes + + bool msb = true; // starts with MSB, then LSB + for (; Wire1.available() && count < length && (timeout == 0 || millis() - t1 < timeout);) { + if (msb) { + // first byte is bits 15-8 (MSb=15) + data[count] = Wire1.read() << 8; + } else { + // second byte is bits 7-0 (LSb=0) + data[count] |= Wire1.read(); + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print(data[count], HEX); + if (count + 1 < length) Serial.print(" "); + #endif + count++; + } + msb = !msb; + } + + Wire1.endTransmission(); + } + #elif (ARDUINO > 100) + // Arduino v1.0.1+, Wire library + // Adds official support for repeated start condition, yay! + + // I2C/TWI subsystem uses internal buffer that breaks with large data requests + // so if user requests more than BUFFER_LENGTH bytes, we have to do it in + // smaller chunks instead of all at once + for (uint8_t k = 0; k < length * 2; k += min(length * 2, BUFFER_LENGTH)) { + Wire1.beginTransmission(devAddr); + Wire1.write(regAddr); + Wire1.endTransmission(); + Wire1.beginTransmission(devAddr); + Wire1.requestFrom(devAddr, (uint8_t)(length * 2)); // length=words, this wants bytes + + bool msb = true; // starts with MSB, then LSB + for (; Wire1.available() && count < length && (timeout == 0 || millis() - t1 < timeout);) { + if (msb) { + // first byte is bits 15-8 (MSb=15) + data[count] = Wire1.read() << 8; + } else { + // second byte is bits 7-0 (LSb=0) + data[count] |= Wire1.read(); + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print(data[count], HEX); + if (count + 1 < length) Serial.print(" "); + #endif + count++; + } + msb = !msb; + } + + Wire1.endTransmission(); + } + #endif + + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_FASTWIRE) + // Fastwire library (STILL UNDER DEVELOPMENT, NON-FUNCTIONAL!) + + // no loop required for fastwire + uint16_t intermediate[(uint8_t)length]; + uint8_t status = Fastwire::readBuf(devAddr, regAddr, (uint8_t *)intermediate, (uint8_t)(length * 2)); + if (status == 0) { + count = length; // success + for (uint8_t i = 0; i < length; i++) { + data[i] = (intermediate[2*i] << 8) | intermediate[2*i + 1]; + } + } else { + count = -1; // error + } + + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_I2CMASTER_LIBRARY) + + uint16_t intermediate[(uint8_t)length]; + uint8_t status = I2c.read(devAddr, regAddr, length*2, (uint8_t *)intermediate); + if(status == 0) { + count = length; + for(uint8_t i = 0; i < length; i++) { + data[i] = (intermediate[2*i] << 8) | intermediate[2*i + i]; + } + } else { + count = -1 * status; + } + #endif + + if (timeout > 0 && millis() - t1 >= timeout && count < length) count = -1; // timeout + + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print(". Done ("); + Serial.print(count, DEC); + Serial.println(" read)."); + #endif + + return count; +} + +/** write a single bit in an 8-bit device register. + * @param devAddr I2C slave device address + * @param regAddr Register regAddr to write to + * @param bitNum Bit position to write (0-7) + * @param value New bit value to write + * @return Status of operation (true = success) + */ +bool I2Cdev::writeBit(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint8_t data) { + uint8_t b; + readByte(devAddr, regAddr, &b); + b = (data != 0) ? (b | (1 << bitNum)) : (b & ~(1 << bitNum)); + return writeByte(devAddr, regAddr, b); +} + +/** write a single bit in a 16-bit device register. + * @param devAddr I2C slave device address + * @param regAddr Register regAddr to write to + * @param bitNum Bit position to write (0-15) + * @param value New bit value to write + * @return Status of operation (true = success) + */ +bool I2Cdev::writeBitW(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint16_t data) { + uint16_t w; + readWord(devAddr, regAddr, &w); + w = (data != 0) ? (w | (1 << bitNum)) : (w & ~(1 << bitNum)); + return writeWord(devAddr, regAddr, w); +} + +/** Write multiple bits in an 8-bit device register. + * @param devAddr I2C slave device address + * @param regAddr Register regAddr to write to + * @param bitStart First bit position to write (0-7) + * @param length Number of bits to write (not more than 8) + * @param data Right-aligned value to write + * @return Status of operation (true = success) + */ +bool I2Cdev::writeBits(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint8_t data) { + // 010 value to write + // 76543210 bit numbers + // xxx args: bitStart=4, length=3 + // 00011100 mask byte + // 10101111 original value (sample) + // 10100011 original & ~mask + // 10101011 masked | value + uint8_t b; + if (readByte(devAddr, regAddr, &b) != 0) { + uint8_t mask = ((1 << length) - 1) << (bitStart - length + 1); + data <<= (bitStart - length + 1); // shift data into correct position + data &= mask; // zero all non-important bits in data + b &= ~(mask); // zero all important bits in existing byte + b |= data; // combine data with existing byte + return writeByte(devAddr, regAddr, b); + } else { + return false; + } +} + +/** Write multiple bits in a 16-bit device register. + * @param devAddr I2C slave device address + * @param regAddr Register regAddr to write to + * @param bitStart First bit position to write (0-15) + * @param length Number of bits to write (not more than 16) + * @param data Right-aligned value to write + * @return Status of operation (true = success) + */ +bool I2Cdev::writeBitsW(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint16_t data) { + // 010 value to write + // fedcba9876543210 bit numbers + // xxx args: bitStart=12, length=3 + // 0001110000000000 mask word + // 1010111110010110 original value (sample) + // 1010001110010110 original & ~mask + // 1010101110010110 masked | value + uint16_t w; + if (readWord(devAddr, regAddr, &w) != 0) { + uint16_t mask = ((1 << length) - 1) << (bitStart - length + 1); + data <<= (bitStart - length + 1); // shift data into correct position + data &= mask; // zero all non-important bits in data + w &= ~(mask); // zero all important bits in existing word + w |= data; // combine data with existing word + return writeWord(devAddr, regAddr, w); + } else { + return false; + } +} + +/** Write single byte to an 8-bit device register. + * @param devAddr I2C slave device address + * @param regAddr Register address to write to + * @param data New byte value to write + * @return Status of operation (true = success) + */ +bool I2Cdev::writeByte(uint8_t devAddr, uint8_t regAddr, uint8_t data) { + return writeBytes(devAddr, regAddr, 1, &data); +} + +/** Write single word to a 16-bit device register. + * @param devAddr I2C slave device address + * @param regAddr Register address to write to + * @param data New word value to write + * @return Status of operation (true = success) + */ +bool I2Cdev::writeWord(uint8_t devAddr, uint8_t regAddr, uint16_t data) { + return writeWords(devAddr, regAddr, 1, &data); +} + +/** Write multiple bytes to an 8-bit device register. + * @param devAddr I2C slave device address + * @param regAddr First register address to write to + * @param length Number of bytes to write + * @param data Buffer to copy new data from + * @return Status of operation (true = success) + */ +bool I2Cdev::writeBytes(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint8_t* data) { + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print("I2C (0x"); + Serial.print(devAddr, HEX); + Serial.print(") writing "); + Serial.print(length, DEC); + Serial.print(" bytes to 0x"); + Serial.print(regAddr, HEX); + Serial.print("..."); + #endif + uint8_t status = 0; + #if ((I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE && ARDUINO < 100) || I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_NBWIRE) + Wire1.beginTransmission(devAddr); + Wire1.send((uint8_t) regAddr); // send address + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE && ARDUINO >= 100) + Wire1.beginTransmission(devAddr); + Wire1.write((uint8_t) regAddr); // send address + #endif + for (uint8_t i = 0; i < length; i++) { + #if ((I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE && ARDUINO < 100) || I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_NBWIRE) + Wire1.send((uint8_t) data[i]); + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE && ARDUINO >= 100) + Wire1.write((uint8_t) data[i]); + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_FASTWIRE) + status = Fastwire::write(devAddr, regAddr, data[i]); + Serial.println(status); + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_I2CMASTER_LIBRARY) + status = I2c.write(devAddr, regAddr, data[i]); + #endif + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print(data[i], HEX); + if (i + 1 < length) Serial.print(" "); + #endif + } + #if ((I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE && ARDUINO < 100) || I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_NBWIRE) + Wire1.endTransmission(); + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE && ARDUINO >= 100) + status = Wire1.endTransmission(); + #endif + #ifdef I2CDEV_SERIAL_DEBUG + Serial.println(". Done."); + #endif + return status == 0; +} + +/** Write multiple words to a 16-bit device register. + * @param devAddr I2C slave device address + * @param regAddr First register address to write to + * @param length Number of words to write + * @param data Buffer to copy new data from + * @return Status of operation (true = success) + */ +bool I2Cdev::writeWords(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint16_t* data) { + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print("I2C (0x"); + Serial.print(devAddr, HEX); + Serial.print(") writing "); + Serial.print(length, DEC); + Serial.print(" words to 0x"); + Serial.print(regAddr, HEX); + Serial.print("..."); + #endif + uint8_t status = 0; + #if ((I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE && ARDUINO < 100) || I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_NBWIRE) + Wire1.beginTransmission(devAddr); + Wire1.send(regAddr); // send address + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE && ARDUINO >= 100) + Wire1.beginTransmission(devAddr); + Wire1.write(regAddr); // send address + #endif + for (uint8_t i = 0; i < length * 2; i++) { + #if ((I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE && ARDUINO < 100) || I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_NBWIRE) + Wire1.send((uint8_t)(data[i++] >> 8)); // send MSB + Wire1.send((uint8_t)data[i]); // send LSB + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE && ARDUINO >= 100) + Wire1.write((uint8_t)(data[i++] >> 8)); // send MSB + Wire1.write((uint8_t)data[i]); // send LSB + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_FASTWIRE) + status = Fastwire::write(devAddr, regAddr, (uint8_t)(data[i++] >> 8)); + status = Fastwire::write(devAddr, regAddr + 1, (uint8_t)data[i]); + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_I2CMASTER_LIBRARY) + status = I2c.write((uint8_t)devAddr, (uint8_t)regAddr, (uint8_t)(data[i++] >> 8)); + status = I2c.write((uint8_t)devAddr, (uint8_t)regAddr + 1, (uint8_t)data[i]); + #endif + #ifdef I2CDEV_SERIAL_DEBUG + Serial.print(data[i], HEX); + if (i + 1 < length) Serial.print(" "); + #endif + } + #if ((I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE && ARDUINO < 100) || I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_NBWIRE) + Wire1.endTransmission(); + #elif (I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE && ARDUINO >= 100) + status = Wire1.endTransmission(); + #endif + #ifdef I2CDEV_SERIAL_DEBUG + Serial.println(". Done."); + #endif + return status == 0; +} + +/** Default timeout value for read operations. + * Set this to 0 to disable timeout detection. + */ +uint16_t I2Cdev::readTimeout = I2CDEV_DEFAULT_READ_TIMEOUT; + +#if I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_FASTWIRE + /* + FastWire 0.2 + This is a library to help faster programs to read I2C devices. + Copyright(C) 2011 Francesco Ferrara + occhiobello at gmail dot com + */ + + boolean Fastwire::waitInt() { + int l = 250; + while (!(TWCR & (1 << TWINT)) && l-- > 0); + return l > 0; + } + + void Fastwire::setup(int khz, boolean pullup) { + TWCR = 0; + #if defined(__AVR_ATmega168__) || defined(__AVR_ATmega8__) || defined(__AVR_ATmega328P__) + // activate internal pull-ups for twi (PORTC bits 4 & 5) + // as per note from atmega8 manual pg167 + if (pullup) PORTC |= ((1 << 4) | (1 << 5)); + else PORTC &= ~((1 << 4) | (1 << 5)); + #elif defined(__AVR_ATmega644P__) || defined(__AVR_ATmega644__) + // activate internal pull-ups for twi (PORTC bits 0 & 1) + if (pullup) PORTC |= ((1 << 0) | (1 << 1)); + else PORTC &= ~((1 << 0) | (1 << 1)); + #else + // activate internal pull-ups for twi (PORTD bits 0 & 1) + // as per note from atmega128 manual pg204 + if (pullup) PORTD |= ((1 << 0) | (1 << 1)); + else PORTD &= ~((1 << 0) | (1 << 1)); + #endif + + TWSR = 0; // no prescaler => prescaler = 1 + TWBR = ((16000L / khz) - 16) / 2; // change the I2C clock rate + TWCR = 1 << TWEN; // enable twi module, no interrupt + } + + byte Fastwire::write(byte device, byte address, byte value) { + byte twst, retry; + + retry = 2; + do { + TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO) | (1 << TWSTA); + if (!waitInt()) return 1; + twst = TWSR & 0xF8; + if (twst != TW_START && twst != TW_REP_START) return 2; + + TWDR = device & 0xFE; // send device address without read bit (1) + TWCR = (1 << TWINT) | (1 << TWEN); + if (!waitInt()) return 3; + twst = TWSR & 0xF8; + } while (twst == TW_MT_SLA_NACK && retry-- > 0); + if (twst != TW_MT_SLA_ACK) return 4; + + TWDR = address; // send data to the previously addressed device + TWCR = (1 << TWINT) | (1 << TWEN); + if (!waitInt()) return 5; + twst = TWSR & 0xF8; + if (twst != TW_MT_DATA_ACK) return 6; + + TWDR = value; // send data to the previously addressed device + TWCR = (1 << TWINT) | (1 << TWEN); + if (!waitInt()) return 7; + twst = TWSR & 0xF8; + if (twst != TW_MT_DATA_ACK) return 8; + + return 0; + } + + byte Fastwire::readBuf(byte device, byte address, byte *data, byte num) { + byte twst, retry; + + retry = 2; + do { + TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO) | (1 << TWSTA); + if (!waitInt()) return 16; + twst = TWSR & 0xF8; + if (twst != TW_START && twst != TW_REP_START) return 17; + + TWDR = device & 0xfe; // send device address to write + TWCR = (1 << TWINT) | (1 << TWEN); + if (!waitInt()) return 18; + twst = TWSR & 0xF8; + } while (twst == TW_MT_SLA_NACK && retry-- > 0); + if (twst != TW_MT_SLA_ACK) return 19; + + TWDR = address; // send data to the previously addressed device + TWCR = (1 << TWINT) | (1 << TWEN); + if (!waitInt()) return 20; + twst = TWSR & 0xF8; + if (twst != TW_MT_DATA_ACK) return 21; + + /***/ + + retry = 2; + do { + TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO) | (1 << TWSTA); + if (!waitInt()) return 22; + twst = TWSR & 0xF8; + if (twst != TW_START && twst != TW_REP_START) return 23; + + TWDR = device | 0x01; // send device address with the read bit (1) + TWCR = (1 << TWINT) | (1 << TWEN); + if (!waitInt()) return 24; + twst = TWSR & 0xF8; + } while (twst == TW_MR_SLA_NACK && retry-- > 0); + if (twst != TW_MR_SLA_ACK) return 25; + + for(uint8_t i = 0; i < num; i++) { + if (i == num - 1) + TWCR = (1 << TWINT) | (1 << TWEN); + else + TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWEA); + if (!waitInt()) return 26; + twst = TWSR & 0xF8; + if (twst != TW_MR_DATA_ACK && twst != TW_MR_DATA_NACK) return twst; + data[i] = TWDR; + } + + return 0; + } +#endif + +#if I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_NBWIRE + // NBWire implementation based heavily on code by Gene Knight + // Originally posted on the Arduino forum at http://arduino.cc/forum/index.php/topic,70705.0.html + // Originally offered to the i2cdevlib project at http://arduino.cc/forum/index.php/topic,68210.30.html + + /* + call this version 1.0 + + Offhand, the only funky part that I can think of is in nbrequestFrom, where the buffer + length and index are set *before* the data is actually read. The problem is that these + are variables local to the TwoWire object, and by the time we actually have read the + data, and know what the length actually is, we have no simple access to the object's + variables. The actual bytes read *is* given to the callback function, though. + + The ISR code for a slave receiver is commented out. I don't have that setup, and can't + verify it at this time. Save it for 2.0! + + The handling of the read and write processes here is much like in the demo sketch code: + the process is broken down into sequential functions, where each registers the next as a + callback, essentially. + + For example, for the Read process, twi_read00 just returns if TWI is not yet in a + ready state. When there's another interrupt, and the interface *is* ready, then it + sets up the read, starts it, and registers twi_read01 as the function to call after + the *next* interrupt. twi_read01, then, just returns if the interface is still in a + "reading" state. When the reading is done, it copies the information to the buffer, + cleans up, and calls the user-requested callback function with the actual number of + bytes read. + + The writing is similar. + + Questions, comments and problems can go to Gene@Telobot.com. + + Thumbs Up! + Gene Knight + + */ + + uint8_t TwoWire::rxBuffer[NBWIRE_BUFFER_LENGTH]; + uint8_t TwoWire::rxBufferIndex = 0; + uint8_t TwoWire::rxBufferLength = 0; + + uint8_t TwoWire::txAddress = 0; + uint8_t TwoWire::txBuffer[NBWIRE_BUFFER_LENGTH]; + uint8_t TwoWire::txBufferIndex = 0; + uint8_t TwoWire::txBufferLength = 0; + + //uint8_t TwoWire::transmitting = 0; + void (*TwoWire::user_onRequest)(void); + void (*TwoWire::user_onReceive)(int); + + static volatile uint8_t twi_transmitting; + static volatile uint8_t twi_state; + static uint8_t twi_slarw; + static volatile uint8_t twi_error; + static uint8_t twi_masterBuffer[TWI_BUFFER_LENGTH]; + static volatile uint8_t twi_masterBufferIndex; + static uint8_t twi_masterBufferLength; + static uint8_t twi_rxBuffer[TWI_BUFFER_LENGTH]; + static volatile uint8_t twi_rxBufferIndex; + //static volatile uint8_t twi_Interrupt_Continue_Command; + static volatile uint8_t twi_Return_Value; + static volatile uint8_t twi_Done; + void (*twi_cbendTransmissionDone)(int); + void (*twi_cbreadFromDone)(int); + + void twi_init() { + // initialize state + twi_state = TWI_READY; + + // activate internal pull-ups for twi + // as per note from atmega8 manual pg167 + sbi(PORTC, 4); + sbi(PORTC, 5); + + // initialize twi prescaler and bit rate + cbi(TWSR, TWPS0); // TWI Status Register - Prescaler bits + cbi(TWSR, TWPS1); + + /* twi bit rate formula from atmega128 manual pg 204 + SCL Frequency = CPU Clock Frequency / (16 + (2 * TWBR)) + note: TWBR should be 10 or higher for master mode + It is 72 for a 16mhz Wiring board with 100kHz TWI */ + + TWBR = ((CPU_FREQ / TWI_FREQ) - 16) / 2; // bitrate register + // enable twi module, acks, and twi interrupt + + TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWEA); + + /* TWEN - TWI Enable Bit + TWIE - TWI Interrupt Enable + TWEA - TWI Enable Acknowledge Bit + TWINT - TWI Interrupt Flag + TWSTA - TWI Start Condition + */ + } + + typedef struct { + uint8_t address; + uint8_t* data; + uint8_t length; + uint8_t wait; + uint8_t i; + } twi_Write_Vars; + + twi_Write_Vars *ptwv = 0; + static void (*fNextInterruptFunction)(void) = 0; + + void twi_Finish(byte bRetVal) { + if (ptwv) { + free(ptwv); + ptwv = 0; + } + twi_Done = 0xFF; + twi_Return_Value = bRetVal; + fNextInterruptFunction = 0; + } + + uint8_t twii_WaitForDone(uint16_t timeout) { + uint32_t endMillis = millis() + timeout; + while (!twi_Done && (timeout == 0 || millis() < endMillis)) continue; + return twi_Return_Value; + } + + void twii_SetState(uint8_t ucState) { + twi_state = ucState; + } + + void twii_SetError(uint8_t ucError) { + twi_error = ucError ; + } + + void twii_InitBuffer(uint8_t ucPos, uint8_t ucLength) { + twi_masterBufferIndex = 0; + twi_masterBufferLength = ucLength; + } + + void twii_CopyToBuf(uint8_t* pData, uint8_t ucLength) { + uint8_t i; + for (i = 0; i < ucLength; ++i) { + twi_masterBuffer[i] = pData[i]; + } + } + + void twii_CopyFromBuf(uint8_t *pData, uint8_t ucLength) { + uint8_t i; + for (i = 0; i < ucLength; ++i) { + pData[i] = twi_masterBuffer[i]; + } + } + + void twii_SetSlaRW(uint8_t ucSlaRW) { + twi_slarw = ucSlaRW; + } + + void twii_SetStart() { + TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWEA) | _BV(TWINT) | _BV(TWSTA); + } + + void twi_write01() { + if (TWI_MTX == twi_state) return; // blocking test + twi_transmitting = 0 ; + if (twi_error == 0xFF) + twi_Finish (0); // success + else if (twi_error == TW_MT_SLA_NACK) + twi_Finish (2); // error: address send, nack received + else if (twi_error == TW_MT_DATA_NACK) + twi_Finish (3); // error: data send, nack received + else + twi_Finish (4); // other twi error + if (twi_cbendTransmissionDone) return twi_cbendTransmissionDone(twi_Return_Value); + return; + } + + + void twi_write00() { + if (TWI_READY != twi_state) return; // blocking test + if (TWI_BUFFER_LENGTH < ptwv -> length) { + twi_Finish(1); // end write with error 1 + return; + } + twi_Done = 0x00; // show as working + twii_SetState(TWI_MTX); // to transmitting + twii_SetError(0xFF); // to No Error + twii_InitBuffer(0, ptwv -> length); // pointer and length + twii_CopyToBuf(ptwv -> data, ptwv -> length); // get the data + twii_SetSlaRW((ptwv -> address << 1) | TW_WRITE); // write command + twii_SetStart(); // start the cycle + fNextInterruptFunction = twi_write01; // next routine + return twi_write01(); + } + + void twi_writeTo(uint8_t address, uint8_t* data, uint8_t length, uint8_t wait) { + uint8_t i; + ptwv = (twi_Write_Vars *)malloc(sizeof(twi_Write_Vars)); + ptwv -> address = address; + ptwv -> data = data; + ptwv -> length = length; + ptwv -> wait = wait; + fNextInterruptFunction = twi_write00; + return twi_write00(); + } + + void twi_read01() { + if (TWI_MRX == twi_state) return; // blocking test + if (twi_masterBufferIndex < ptwv -> length) ptwv -> length = twi_masterBufferIndex; + twii_CopyFromBuf(ptwv -> data, ptwv -> length); + twi_Finish(ptwv -> length); + if (twi_cbreadFromDone) return twi_cbreadFromDone(twi_Return_Value); + return; + } + + void twi_read00() { + if (TWI_READY != twi_state) return; // blocking test + if (TWI_BUFFER_LENGTH < ptwv -> length) twi_Finish(0); // error return + twi_Done = 0x00; // show as working + twii_SetState(TWI_MRX); // reading + twii_SetError(0xFF); // reset error + twii_InitBuffer(0, ptwv -> length - 1); // init to one less than length + twii_SetSlaRW((ptwv -> address << 1) | TW_READ); // read command + twii_SetStart(); // start cycle + fNextInterruptFunction = twi_read01; + return twi_read01(); + } + + void twi_readFrom(uint8_t address, uint8_t* data, uint8_t length) { + uint8_t i; + + ptwv = (twi_Write_Vars *)malloc(sizeof(twi_Write_Vars)); + ptwv -> address = address; + ptwv -> data = data; + ptwv -> length = length; + fNextInterruptFunction = twi_read00; + return twi_read00(); + } + + void twi_reply(uint8_t ack) { + // transmit master read ready signal, with or without ack + if (ack){ + TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWINT) | _BV(TWEA); + } else { + TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWINT); + } + } + + void twi_stop(void) { + // send stop condition + TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWEA) | _BV(TWINT) | _BV(TWSTO); + + // wait for stop condition to be exectued on bus + // TWINT is not set after a stop condition! + while (TWCR & _BV(TWSTO)) { + continue; + } + + // update twi state + twi_state = TWI_READY; + } + + void twi_releaseBus(void) { + // release bus + TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWEA) | _BV(TWINT); + + // update twi state + twi_state = TWI_READY; + } + + SIGNAL(TWI_vect) { + switch (TW_STATUS) { + // All Master + case TW_START: // sent start condition + case TW_REP_START: // sent repeated start condition + // copy device address and r/w bit to output register and ack + TWDR = twi_slarw; + twi_reply(1); + break; + + // Master Transmitter + case TW_MT_SLA_ACK: // slave receiver acked address + case TW_MT_DATA_ACK: // slave receiver acked data + // if there is data to send, send it, otherwise stop + if (twi_masterBufferIndex < twi_masterBufferLength) { + // copy data to output register and ack + TWDR = twi_masterBuffer[twi_masterBufferIndex++]; + twi_reply(1); + } else { + twi_stop(); + } + break; + + case TW_MT_SLA_NACK: // address sent, nack received + twi_error = TW_MT_SLA_NACK; + twi_stop(); + break; + + case TW_MT_DATA_NACK: // data sent, nack received + twi_error = TW_MT_DATA_NACK; + twi_stop(); + break; + + case TW_MT_ARB_LOST: // lost bus arbitration + twi_error = TW_MT_ARB_LOST; + twi_releaseBus(); + break; + + // Master Receiver + case TW_MR_DATA_ACK: // data received, ack sent + // put byte into buffer + twi_masterBuffer[twi_masterBufferIndex++] = TWDR; + + case TW_MR_SLA_ACK: // address sent, ack received + // ack if more bytes are expected, otherwise nack + if (twi_masterBufferIndex < twi_masterBufferLength) { + twi_reply(1); + } else { + twi_reply(0); + } + break; + + case TW_MR_DATA_NACK: // data received, nack sent + // put final byte into buffer + twi_masterBuffer[twi_masterBufferIndex++] = TWDR; + + case TW_MR_SLA_NACK: // address sent, nack received + twi_stop(); + break; + + // TW_MR_ARB_LOST handled by TW_MT_ARB_LOST case + + // Slave Receiver (NOT IMPLEMENTED YET) + /* + case TW_SR_SLA_ACK: // addressed, returned ack + case TW_SR_GCALL_ACK: // addressed generally, returned ack + case TW_SR_ARB_LOST_SLA_ACK: // lost arbitration, returned ack + case TW_SR_ARB_LOST_GCALL_ACK: // lost arbitration, returned ack + // enter slave receiver mode + twi_state = TWI_SRX; + + // indicate that rx buffer can be overwritten and ack + twi_rxBufferIndex = 0; + twi_reply(1); + break; + + case TW_SR_DATA_ACK: // data received, returned ack + case TW_SR_GCALL_DATA_ACK: // data received generally, returned ack + // if there is still room in the rx buffer + if (twi_rxBufferIndex < TWI_BUFFER_LENGTH) { + // put byte in buffer and ack + twi_rxBuffer[twi_rxBufferIndex++] = TWDR; + twi_reply(1); + } else { + // otherwise nack + twi_reply(0); + } + break; + + case TW_SR_STOP: // stop or repeated start condition received + // put a null char after data if there's room + if (twi_rxBufferIndex < TWI_BUFFER_LENGTH) { + twi_rxBuffer[twi_rxBufferIndex] = 0; + } + + // sends ack and stops interface for clock stretching + twi_stop(); + + // callback to user defined callback + twi_onSlaveReceive(twi_rxBuffer, twi_rxBufferIndex); + + // since we submit rx buffer to "wire" library, we can reset it + twi_rxBufferIndex = 0; + + // ack future responses and leave slave receiver state + twi_releaseBus(); + break; + + case TW_SR_DATA_NACK: // data received, returned nack + case TW_SR_GCALL_DATA_NACK: // data received generally, returned nack + // nack back at master + twi_reply(0); + break; + + // Slave Transmitter + case TW_ST_SLA_ACK: // addressed, returned ack + case TW_ST_ARB_LOST_SLA_ACK: // arbitration lost, returned ack + // enter slave transmitter mode + twi_state = TWI_STX; + + // ready the tx buffer index for iteration + twi_txBufferIndex = 0; + + // set tx buffer length to be zero, to verify if user changes it + twi_txBufferLength = 0; + + // request for txBuffer to be filled and length to be set + // note: user must call twi_transmit(bytes, length) to do this + twi_onSlaveTransmit(); + + // if they didn't change buffer & length, initialize it + if (0 == twi_txBufferLength) { + twi_txBufferLength = 1; + twi_txBuffer[0] = 0x00; + } + + // transmit first byte from buffer, fall through + + case TW_ST_DATA_ACK: // byte sent, ack returned + // copy data to output register + TWDR = twi_txBuffer[twi_txBufferIndex++]; + + // if there is more to send, ack, otherwise nack + if (twi_txBufferIndex < twi_txBufferLength) { + twi_reply(1); + } else { + twi_reply(0); + } + break; + + case TW_ST_DATA_NACK: // received nack, we are done + case TW_ST_LAST_DATA: // received ack, but we are done already! + // ack future responses + twi_reply(1); + // leave slave receiver state + twi_state = TWI_READY; + break; + */ + + // all + case TW_NO_INFO: // no state information + break; + + case TW_BUS_ERROR: // bus error, illegal stop/start + twi_error = TW_BUS_ERROR; + twi_stop(); + break; + } + + if (fNextInterruptFunction) return fNextInterruptFunction(); + } + + TwoWire::TwoWire() { } + + void TwoWire::begin(void) { + rxBufferIndex = 0; + rxBufferLength = 0; + + txBufferIndex = 0; + txBufferLength = 0; + + twi_init(); + } + + void TwoWire::beginTransmission(uint8_t address) { + //beginTransmission((uint8_t)address); + + // indicate that we are transmitting + twi_transmitting = 1; + + // set address of targeted slave + txAddress = address; + + // reset tx buffer iterator vars + txBufferIndex = 0; + txBufferLength = 0; + } + + uint8_t TwoWire::endTransmission(uint16_t timeout) { + // transmit buffer (blocking) + //int8_t ret = + twi_cbendTransmissionDone = NULL; + twi_writeTo(txAddress, txBuffer, txBufferLength, 1); + int8_t ret = twii_WaitForDone(timeout); + + // reset tx buffer iterator vars + txBufferIndex = 0; + txBufferLength = 0; + + // indicate that we are done transmitting + // twi_transmitting = 0; + return ret; + } + + void TwoWire::nbendTransmission(void (*function)(int)) { + twi_cbendTransmissionDone = function; + twi_writeTo(txAddress, txBuffer, txBufferLength, 1); + return; + } + + void TwoWire::send(uint8_t data) { + if (twi_transmitting) { + // in master transmitter mode + // don't bother if buffer is full + if (txBufferLength >= NBWIRE_BUFFER_LENGTH) { + return; + } + + // put byte in tx buffer + txBuffer[txBufferIndex] = data; + ++txBufferIndex; + + // update amount in buffer + txBufferLength = txBufferIndex; + } else { + // in slave send mode + // reply to master + //twi_transmit(&data, 1); + } + } + + uint8_t TwoWire::receive(void) { + // default to returning null char + // for people using with char strings + uint8_t value = 0; + + // get each successive byte on each call + if (rxBufferIndex < rxBufferLength) { + value = rxBuffer[rxBufferIndex]; + ++rxBufferIndex; + } + + return value; + } + + uint8_t TwoWire::requestFrom(uint8_t address, int quantity, uint16_t timeout) { + // clamp to buffer length + if (quantity > NBWIRE_BUFFER_LENGTH) { + quantity = NBWIRE_BUFFER_LENGTH; + } + + // perform blocking read into buffer + twi_cbreadFromDone = NULL; + twi_readFrom(address, rxBuffer, quantity); + uint8_t read = twii_WaitForDone(timeout); + + // set rx buffer iterator vars + rxBufferIndex = 0; + rxBufferLength = read; + + return read; + } + + void TwoWire::nbrequestFrom(uint8_t address, int quantity, void (*function)(int)) { + // clamp to buffer length + if (quantity > NBWIRE_BUFFER_LENGTH) { + quantity = NBWIRE_BUFFER_LENGTH; + } + + // perform blocking read into buffer + twi_cbreadFromDone = function; + twi_readFrom(address, rxBuffer, quantity); + //uint8_t read = twii_WaitForDone(); + + // set rx buffer iterator vars + //rxBufferIndex = 0; + //rxBufferLength = read; + + rxBufferIndex = 0; + rxBufferLength = quantity; // this is a hack + + return; //read; + } + + uint8_t TwoWire::available(void) { + return rxBufferLength - rxBufferIndex; + } + +#endif diff --git a/hardware/digistump/sam/libraries/I2Cdev/I2Cdev.h b/hardware/digistump/sam/libraries/I2Cdev/I2Cdev.h new file mode 100644 index 0000000..60af68e --- /dev/null +++ b/hardware/digistump/sam/libraries/I2Cdev/I2Cdev.h @@ -0,0 +1,268 @@ +// I2Cdev library collection - Main I2C device class header file +// Abstracts bit and byte I2C R/W functions into a convenient class +// 6/9/2012 by Jeff Rowberg +// +// Changelog: +// 2013-05-05 - fix issue with writing bit values to words (Sasquatch/Farzanegan) +// 2012-06-09 - fix major issue with reading > 32 bytes at a time with Arduino Wire +// - add compiler warnings when using outdated or IDE or limited I2Cdev implementation +// 2011-11-01 - fix write*Bits mask calculation (thanks sasquatch @ Arduino forums) +// 2011-10-03 - added automatic Arduino version detection for ease of use +// 2011-10-02 - added Gene Knight's NBWire TwoWire class implementation with small modifications +// 2011-08-31 - added support for Arduino 1.0 Wire library (methods are different from 0.x) +// 2011-08-03 - added optional timeout parameter to read* methods to easily change from default +// 2011-08-02 - added support for 16-bit registers +// - fixed incorrect Doxygen comments on some methods +// - added timeout value for read operations (thanks mem @ Arduino forums) +// 2011-07-30 - changed read/write function structures to return success or byte counts +// - made all methods static for multi-device memory savings +// 2011-07-28 - initial release + +/* ============================================ +I2Cdev device library code is placed under the MIT license +Copyright (c) 2012 Jeff Rowberg + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +=============================================== +*/ + +#ifndef _I2CDEV_H_ +#define _I2CDEV_H_ + +// comment this out if you are using a non-optimal IDE/implementation setting +// but want the compiler to shut up about it +#define I2CDEV_IMPLEMENTATION_WARNINGS + +// ----------------------------------------------------------------------------- +// I2C interface implementation options +// ----------------------------------------------------------------------------- +#define I2CDEV_ARDUINO_WIRE 1 // Wire object from Arduino +#define I2CDEV_BUILTIN_NBWIRE 2 // Tweaked Wire object from Gene Knight's NBWire project + // ^^^ NBWire implementation is still buggy w/some interrupts! +#define I2CDEV_BUILTIN_FASTWIRE 3 // FastWire object from Francesco Ferrara's project + // ^^^ FastWire implementation in I2Cdev is INCOMPLETE! +#define I2CDEV_I2CMASTER_LIBRARY 4 // I2C object from DSSCircuits I2C-Master Library at + // https://github.com/DSSCircuits/I2C-Master-Library + +// ----------------------------------------------------------------------------- +// I2C interface implementation setting +// ----------------------------------------------------------------------------- +#define I2CDEV_IMPLEMENTATION I2CDEV_ARDUINO_WIRE + +// ----------------------------------------------------------------------------- +// Arduino-style "Serial.print" debug constant (uncomment to enable) +// ----------------------------------------------------------------------------- +//#define I2CDEV_SERIAL_DEBUG + +#ifdef ARDUINO + #if ARDUINO < 100 + #include "WProgram.h" + #else + #include "Arduino.h" + #endif + #if I2CDEV_IMPLEMENTATION == I2CDEV_ARDUINO_WIRE + #include + #else + #if I2CDEV_IMPLEMENTATION == I2CDEV_I2CMASTER_LIBRARY + #include + #endif + #endif +#else + #include "ArduinoWrapper.h" +#endif + +// 1000ms default read timeout (modify with "I2Cdev::readTimeout = [ms];") +#define I2CDEV_DEFAULT_READ_TIMEOUT 1000 + +class I2Cdev { + public: + I2Cdev(); + + static int8_t readBit(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint8_t *data, uint16_t timeout=I2Cdev::readTimeout); + static int8_t readBitW(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint16_t *data, uint16_t timeout=I2Cdev::readTimeout); + static int8_t readBits(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint8_t *data, uint16_t timeout=I2Cdev::readTimeout); + static int8_t readBitsW(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint16_t *data, uint16_t timeout=I2Cdev::readTimeout); + static int8_t readByte(uint8_t devAddr, uint8_t regAddr, uint8_t *data, uint16_t timeout=I2Cdev::readTimeout); + static int8_t readWord(uint8_t devAddr, uint8_t regAddr, uint16_t *data, uint16_t timeout=I2Cdev::readTimeout); + static int8_t readBytes(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint8_t *data, uint16_t timeout=I2Cdev::readTimeout); + static int8_t readWords(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint16_t *data, uint16_t timeout=I2Cdev::readTimeout); + + static bool writeBit(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint8_t data); + static bool writeBitW(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint16_t data); + static bool writeBits(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint8_t data); + static bool writeBitsW(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint16_t data); + static bool writeByte(uint8_t devAddr, uint8_t regAddr, uint8_t data); + static bool writeWord(uint8_t devAddr, uint8_t regAddr, uint16_t data); + static bool writeBytes(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint8_t *data); + static bool writeWords(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint16_t *data); + + static uint16_t readTimeout; +}; + +#if I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_FASTWIRE + ////////////////////// + // FastWire 0.2 + // This is a library to help faster programs to read I2C devices. + // Copyright(C) 2011 + // Francesco Ferrara + ////////////////////// + + /* Master */ + #define TW_START 0x08 + #define TW_REP_START 0x10 + + /* Master Transmitter */ + #define TW_MT_SLA_ACK 0x18 + #define TW_MT_SLA_NACK 0x20 + #define TW_MT_DATA_ACK 0x28 + #define TW_MT_DATA_NACK 0x30 + #define TW_MT_ARB_LOST 0x38 + + /* Master Receiver */ + #define TW_MR_ARB_LOST 0x38 + #define TW_MR_SLA_ACK 0x40 + #define TW_MR_SLA_NACK 0x48 + #define TW_MR_DATA_ACK 0x50 + #define TW_MR_DATA_NACK 0x58 + + #define TW_OK 0 + #define TW_ERROR 1 + + class Fastwire { + private: + static boolean waitInt(); + + public: + static void setup(int khz, boolean pullup); + static byte write(byte device, byte address, byte value); + static byte readBuf(byte device, byte address, byte *data, byte num); + }; +#endif + +#if I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_NBWIRE + // NBWire implementation based heavily on code by Gene Knight + // Originally posted on the Arduino forum at http://arduino.cc/forum/index.php/topic,70705.0.html + // Originally offered to the i2cdevlib project at http://arduino.cc/forum/index.php/topic,68210.30.html + + #define NBWIRE_BUFFER_LENGTH 32 + + class TwoWire { + private: + static uint8_t rxBuffer[]; + static uint8_t rxBufferIndex; + static uint8_t rxBufferLength; + + static uint8_t txAddress; + static uint8_t txBuffer[]; + static uint8_t txBufferIndex; + static uint8_t txBufferLength; + + // static uint8_t transmitting; + static void (*user_onRequest)(void); + static void (*user_onReceive)(int); + static void onRequestService(void); + static void onReceiveService(uint8_t*, int); + + public: + TwoWire(); + void begin(); + void begin(uint8_t); + void begin(int); + void beginTransmission(uint8_t); + //void beginTransmission(int); + uint8_t endTransmission(uint16_t timeout=0); + void nbendTransmission(void (*function)(int)) ; + uint8_t requestFrom(uint8_t, int, uint16_t timeout=0); + //uint8_t requestFrom(int, int); + void nbrequestFrom(uint8_t, int, void (*function)(int)); + void send(uint8_t); + void send(uint8_t*, uint8_t); + //void send(int); + void send(char*); + uint8_t available(void); + uint8_t receive(void); + void onReceive(void (*)(int)); + void onRequest(void (*)(void)); + }; + + #define TWI_READY 0 + #define TWI_MRX 1 + #define TWI_MTX 2 + #define TWI_SRX 3 + #define TWI_STX 4 + + #define TW_WRITE 0 + #define TW_READ 1 + + #define TW_MT_SLA_NACK 0x20 + #define TW_MT_DATA_NACK 0x30 + + #define CPU_FREQ 16000000L + #define TWI_FREQ 100000L + #define TWI_BUFFER_LENGTH 32 + + /* TWI Status is in TWSR, in the top 5 bits: TWS7 - TWS3 */ + + #define TW_STATUS_MASK (_BV(TWS7)|_BV(TWS6)|_BV(TWS5)|_BV(TWS4)|_BV(TWS3)) + #define TW_STATUS (TWSR & TW_STATUS_MASK) + #define TW_START 0x08 + #define TW_REP_START 0x10 + #define TW_MT_SLA_ACK 0x18 + #define TW_MT_SLA_NACK 0x20 + #define TW_MT_DATA_ACK 0x28 + #define TW_MT_DATA_NACK 0x30 + #define TW_MT_ARB_LOST 0x38 + #define TW_MR_ARB_LOST 0x38 + #define TW_MR_SLA_ACK 0x40 + #define TW_MR_SLA_NACK 0x48 + #define TW_MR_DATA_ACK 0x50 + #define TW_MR_DATA_NACK 0x58 + #define TW_ST_SLA_ACK 0xA8 + #define TW_ST_ARB_LOST_SLA_ACK 0xB0 + #define TW_ST_DATA_ACK 0xB8 + #define TW_ST_DATA_NACK 0xC0 + #define TW_ST_LAST_DATA 0xC8 + #define TW_SR_SLA_ACK 0x60 + #define TW_SR_ARB_LOST_SLA_ACK 0x68 + #define TW_SR_GCALL_ACK 0x70 + #define TW_SR_ARB_LOST_GCALL_ACK 0x78 + #define TW_SR_DATA_ACK 0x80 + #define TW_SR_DATA_NACK 0x88 + #define TW_SR_GCALL_DATA_ACK 0x90 + #define TW_SR_GCALL_DATA_NACK 0x98 + #define TW_SR_STOP 0xA0 + #define TW_NO_INFO 0xF8 + #define TW_BUS_ERROR 0x00 + + //#define _MMIO_BYTE(mem_addr) (*(volatile uint8_t *)(mem_addr)) + //#define _SFR_BYTE(sfr) _MMIO_BYTE(_SFR_ADDR(sfr)) + + #ifndef sbi // set bit + #define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit)) + #endif // sbi + + #ifndef cbi // clear bit + #define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit)) + #endif // cbi + + extern TwoWire Wire; + +#endif // I2CDEV_IMPLEMENTATION == I2CDEV_BUILTIN_NBWIRE + +#endif /* _I2CDEV_H_ */ diff --git a/hardware/digistump/sam/libraries/I2Cdev/keywords.txt b/hardware/digistump/sam/libraries/I2Cdev/keywords.txt new file mode 100644 index 0000000..4132a06 --- /dev/null +++ b/hardware/digistump/sam/libraries/I2Cdev/keywords.txt @@ -0,0 +1,38 @@ +####################################### +# Syntax Coloring Map For I2Cdev +####################################### + +####################################### +# Datatypes (KEYWORD1) +####################################### +I2Cdev KEYWORD1 + +####################################### +# Methods and Functions (KEYWORD2) +####################################### + +readBit KEYWORD2 +readBitW KEYWORD2 +readBits KEYWORD2 +readBitsW KEYWORD2 +readByte KEYWORD2 +readBytes KEYWORD2 +readWord KEYWORD2 +readWords KEYWORD2 +writeBit KEYWORD2 +writeBitW KEYWORD2 +writeBits KEYWORD2 +writeBitsW KEYWORD2 +writeByte KEYWORD2 +writeBytes KEYWORD2 +writeWord KEYWORD2 +writeWords KEYWORD2 + +####################################### +# Instances (KEYWORD2) +####################################### + +####################################### +# Constants (LITERAL1) +####################################### + diff --git a/hardware/digistump/sam/libraries/MPU6050/Examples/MPU6050_DMP6/MPU6050_DMP6.ino b/hardware/digistump/sam/libraries/MPU6050/Examples/MPU6050_DMP6/MPU6050_DMP6.ino new file mode 100644 index 0000000..752f828 --- /dev/null +++ b/hardware/digistump/sam/libraries/MPU6050/Examples/MPU6050_DMP6/MPU6050_DMP6.ino @@ -0,0 +1,356 @@ +// I2C device class (I2Cdev) demonstration Arduino sketch for MPU6050 class using DMP (MotionApps v2.0) +// 6/21/2012 by Jeff Rowberg +// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib +// +// Changelog: +// 2012-06-21 - added note about Arduino 1.0.1 + Leonardo compatibility error +// 2012-06-20 - improved FIFO overflow handling and simplified read process +// 2012-06-19 - completely rearranged DMP initialization code and simplification +// 2012-06-13 - pull gyro and accel data from FIFO packet instead of reading directly +// 2012-06-09 - fix broken FIFO read sequence and change interrupt detection to RISING +// 2012-06-05 - add gravity-compensated initial reference frame acceleration output +// - add 3D math helper file to DMP6 example sketch +// - add Euler output and Yaw/Pitch/Roll output formats +// 2012-06-04 - remove accel offset clearing for better results (thanks Sungon Lee) +// 2012-06-01 - fixed gyro sensitivity to be 2000 deg/sec instead of 250 +// 2012-05-30 - basic DMP initialization working + +/* ============================================ +I2Cdev device library code is placed under the MIT license +Copyright (c) 2012 Jeff Rowberg + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +=============================================== +*/ + +// Arduino Wire library is required if I2Cdev I2CDEV_ARDUINO_WIRE implementation +// is used in I2Cdev.h +#include "Wire.h" + +// I2Cdev and MPU6050 must be installed as libraries, or else the .cpp/.h files +// for both classes must be in the include path of your project +#include "I2Cdev.h" + +#include "MPU6050_6Axis_MotionApps20.h" +//#include "MPU6050.h" // not necessary if using MotionApps include file + +// class default I2C address is 0x68 +// specific I2C addresses may be passed as a parameter here +// AD0 low = 0x68 (default for SparkFun breakout and InvenSense evaluation board) +// AD0 high = 0x69 +MPU6050 mpu; + +/* ========================================================================= + NOTE: In addition to connection 3.3v, GND, SDA, and SCL, this sketch + depends on the MPU-6050's INT pin being connected to the Arduino's + external interrupt #0 pin. On the Arduino Uno and Mega 2560, this is + digital I/O pin 2. + * ========================================================================= */ + +/* ========================================================================= + NOTE: Arduino v1.0.1 with the Leonardo board generates a compile error + when using Serial.write(buf, len). The Teapot output uses this method. + The solution requires a modification to the Arduino USBAPI.h file, which + is fortunately simple, but annoying. This will be fixed in the next IDE + release. For more info, see these links: + + http://arduino.cc/forum/index.php/topic,109987.0.html + http://code.google.com/p/arduino/issues/detail?id=958 + * ========================================================================= */ + + + +// uncomment "OUTPUT_READABLE_QUATERNION" if you want to see the actual +// quaternion components in a [w, x, y, z] format (not best for parsing +// on a remote host such as Processing or something though) +//#define OUTPUT_READABLE_QUATERNION + +// uncomment "OUTPUT_READABLE_EULER" if you want to see Euler angles +// (in degrees) calculated from the quaternions coming from the FIFO. +// Note that Euler angles suffer from gimbal lock (for more info, see +// http://en.wikipedia.org/wiki/Gimbal_lock) +//#define OUTPUT_READABLE_EULER + +// uncomment "OUTPUT_READABLE_YAWPITCHROLL" if you want to see the yaw/ +// pitch/roll angles (in degrees) calculated from the quaternions coming +// from the FIFO. Note this also requires gravity vector calculations. +// Also note that yaw/pitch/roll angles suffer from gimbal lock (for +// more info, see: http://en.wikipedia.org/wiki/Gimbal_lock) +#define OUTPUT_READABLE_YAWPITCHROLL + +// uncomment "OUTPUT_READABLE_REALACCEL" if you want to see acceleration +// components with gravity removed. This acceleration reference frame is +// not compensated for orientation, so +X is always +X according to the +// sensor, just without the effects of gravity. If you want acceleration +// compensated for orientation, us OUTPUT_READABLE_WORLDACCEL instead. +//#define OUTPUT_READABLE_REALACCEL + +// uncomment "OUTPUT_READABLE_WORLDACCEL" if you want to see acceleration +// components with gravity removed and adjusted for the world frame of +// reference (yaw is relative to initial orientation, since no magnetometer +// is present in this case). Could be quite handy in some cases. +//#define OUTPUT_READABLE_WORLDACCEL + +// uncomment "OUTPUT_TEAPOT" if you want output that matches the +// format used for the InvenSense teapot demo +//#define OUTPUT_TEAPOT + + + +#define LED_PIN 13 // (Arduino is 13, Teensy is 11, Teensy++ is 6) +bool blinkState = false; + +// MPU control/status vars +bool dmpReady = false; // set true if DMP init was successful +uint8_t mpuIntStatus; // holds actual interrupt status byte from MPU +uint8_t devStatus; // return status after each device operation (0 = success, !0 = error) +uint16_t packetSize; // expected DMP packet size (default is 42 bytes) +uint16_t fifoCount; // count of all bytes currently in FIFO +uint8_t fifoBuffer[64]; // FIFO storage buffer + +// orientation/motion vars +Quaternion q; // [w, x, y, z] quaternion container +VectorInt16 aa; // [x, y, z] accel sensor measurements +VectorInt16 aaReal; // [x, y, z] gravity-free accel sensor measurements +VectorInt16 aaWorld; // [x, y, z] world-frame accel sensor measurements +VectorFloat gravity; // [x, y, z] gravity vector +float euler[3]; // [psi, theta, phi] Euler angle container +float ypr[3]; // [yaw, pitch, roll] yaw/pitch/roll container and gravity vector + +// packet structure for InvenSense teapot demo +uint8_t teapotPacket[14] = { '$', 0x02, 0,0, 0,0, 0,0, 0,0, 0x00, 0x00, '\r', '\n' }; + + + +// ================================================================ +// === INTERRUPT DETECTION ROUTINE === +// ================================================================ + +volatile bool mpuInterrupt = false; // indicates whether MPU interrupt pin has gone high +void dmpDataReady() { + mpuInterrupt = true; +} + + + +// ================================================================ +// === INITIAL SETUP === +// ================================================================ + +void setup() { + // join I2C bus (I2Cdev library doesn't do this automatically) + Wire1.begin(); + + // initialize serial communication + // (115200 chosen because it is required for Teapot Demo output, but it's + // really up to you depending on your project) + Serial.begin(115200); + while (!Serial); // wait for Leonardo enumeration, others continue immediately + + // NOTE: 8MHz or slower host processors, like the Teensy @ 3.3v or Ardunio + // Pro Mini running at 3.3v, cannot handle this baud rate reliably due to + // the baud timing being too misaligned with processor ticks. You must use + // 38400 or slower in these cases, or use some kind of external separate + // crystal solution for the UART timer. + + // initialize device + Serial.println(F("Initializing I2C devices...")); + mpu.initialize(); + + // verify connection + Serial.println(F("Testing device connections...")); + Serial.println(mpu.testConnection() ? F("MPU6050 connection successful") : F("MPU6050 connection failed")); + + // wait for ready + Serial.println(F("\nSend any character to begin DMP programming and demo: ")); + while (Serial.available() && Serial.read()); // empty buffer + while (!Serial.available()); // wait for data + while (Serial.available() && Serial.read()); // empty buffer again + + // load and configure the DMP + Serial.println(F("Initializing DMP...")); + devStatus = mpu.dmpInitialize(); + + // make sure it worked (returns 0 if so) + if (devStatus == 0) { + // turn on the DMP, now that it's ready + Serial.println(F("Enabling DMP...")); + mpu.setDMPEnabled(true); + + // enable Arduino interrupt detection + Serial.println(F("Enabling interrupt detection (Arduino external interrupt 2)...")); + attachInterrupt(2, dmpDataReady, RISING); + mpuIntStatus = mpu.getIntStatus(); + + // set our DMP Ready flag so the main loop() function knows it's okay to use it + Serial.println(F("DMP ready! Waiting for first interrupt...")); + dmpReady = true; + + // get expected DMP packet size for later comparison + packetSize = mpu.dmpGetFIFOPacketSize(); + } else { + // ERROR! + // 1 = initial memory load failed + // 2 = DMP configuration updates failed + // (if it's going to break, usually the code will be 1) + Serial.print(F("DMP Initialization failed (code ")); + Serial.print(devStatus); + Serial.println(F(")")); + } + + // configure LED for output + pinMode(LED_PIN, OUTPUT); +} + + + +// ================================================================ +// === MAIN PROGRAM LOOP === +// ================================================================ + +void loop() { + // if programming failed, don't try to do anything + if (!dmpReady) return; + + // wait for MPU interrupt or extra packet(s) available + while (!mpuInterrupt && fifoCount < packetSize) { + // other program behavior stuff here + // . + // . + // . + // if you are really paranoid you can frequently test in between other + // stuff to see if mpuInterrupt is true, and if so, "break;" from the + // while() loop to immediately process the MPU data + // . + // . + // . + } + + // reset interrupt flag and get INT_STATUS byte + mpuInterrupt = false; + mpuIntStatus = mpu.getIntStatus(); + + // get current FIFO count + fifoCount = mpu.getFIFOCount(); + + // check for overflow (this should never happen unless our code is too inefficient) + if ((mpuIntStatus & 0x10) || fifoCount == 1024) { + // reset so we can continue cleanly + mpu.resetFIFO(); + Serial.println(F("FIFO overflow!")); + + // otherwise, check for DMP data ready interrupt (this should happen frequently) + } else if (mpuIntStatus & 0x02) { + // wait for correct available data length, should be a VERY short wait + while (fifoCount < packetSize) fifoCount = mpu.getFIFOCount(); + + // read a packet from FIFO + mpu.getFIFOBytes(fifoBuffer, packetSize); + + // track FIFO count here in case there is > 1 packet available + // (this lets us immediately read more without waiting for an interrupt) + fifoCount -= packetSize; + + #ifdef OUTPUT_READABLE_QUATERNION + // display quaternion values in easy matrix form: w x y z + mpu.dmpGetQuaternion(&q, fifoBuffer); + Serial.print("quat\t"); + Serial.print(q.w); + Serial.print("\t"); + Serial.print(q.x); + Serial.print("\t"); + Serial.print(q.y); + Serial.print("\t"); + Serial.println(q.z); + #endif + + #ifdef OUTPUT_READABLE_EULER + // display Euler angles in degrees + mpu.dmpGetQuaternion(&q, fifoBuffer); + mpu.dmpGetEuler(euler, &q); + Serial.print("euler\t"); + Serial.print(euler[0] * 180/M_PI); + Serial.print("\t"); + Serial.print(euler[1] * 180/M_PI); + Serial.print("\t"); + Serial.println(euler[2] * 180/M_PI); + #endif + + #ifdef OUTPUT_READABLE_YAWPITCHROLL + // display Euler angles in degrees + mpu.dmpGetQuaternion(&q, fifoBuffer); + mpu.dmpGetGravity(&gravity, &q); + mpu.dmpGetYawPitchRoll(ypr, &q, &gravity); + Serial.print("ypr\t"); + Serial.print(ypr[0] * 180/M_PI); + Serial.print("\t"); + Serial.print(ypr[1] * 180/M_PI); + Serial.print("\t"); + Serial.println(ypr[2] * 180/M_PI); + #endif + + #ifdef OUTPUT_READABLE_REALACCEL + // display real acceleration, adjusted to remove gravity + mpu.dmpGetQuaternion(&q, fifoBuffer); + mpu.dmpGetAccel(&aa, fifoBuffer); + mpu.dmpGetGravity(&gravity, &q); + mpu.dmpGetLinearAccel(&aaReal, &aa, &gravity); + Serial.print("areal\t"); + Serial.print(aaReal.x); + Serial.print("\t"); + Serial.print(aaReal.y); + Serial.print("\t"); + Serial.println(aaReal.z); + #endif + + #ifdef OUTPUT_READABLE_WORLDACCEL + // display initial world-frame acceleration, adjusted to remove gravity + // and rotated based on known orientation from quaternion + mpu.dmpGetQuaternion(&q, fifoBuffer); + mpu.dmpGetAccel(&aa, fifoBuffer); + mpu.dmpGetGravity(&gravity, &q); + mpu.dmpGetLinearAccel(&aaReal, &aa, &gravity); + mpu.dmpGetLinearAccelInWorld(&aaWorld, &aaReal, &q); + Serial.print("aworld\t"); + Serial.print(aaWorld.x); + Serial.print("\t"); + Serial.print(aaWorld.y); + Serial.print("\t"); + Serial.println(aaWorld.z); + #endif + + #ifdef OUTPUT_TEAPOT + // display quaternion values in InvenSense Teapot demo format: + teapotPacket[2] = fifoBuffer[0]; + teapotPacket[3] = fifoBuffer[1]; + teapotPacket[4] = fifoBuffer[4]; + teapotPacket[5] = fifoBuffer[5]; + teapotPacket[6] = fifoBuffer[8]; + teapotPacket[7] = fifoBuffer[9]; + teapotPacket[8] = fifoBuffer[12]; + teapotPacket[9] = fifoBuffer[13]; + Serial.write(teapotPacket, 14); + teapotPacket[11]++; // packetCount, loops at 0xFF on purpose + #endif + + // blink LED to indicate activity + blinkState = !blinkState; + digitalWrite(LED_PIN, blinkState); + } +} \ No newline at end of file diff --git a/hardware/digistump/sam/libraries/MPU6050/Examples/MPU6050_DMP6/Processing/MPUTeapot.pde b/hardware/digistump/sam/libraries/MPU6050/Examples/MPU6050_DMP6/Processing/MPUTeapot.pde new file mode 100644 index 0000000..0507fc2 --- /dev/null +++ b/hardware/digistump/sam/libraries/MPU6050/Examples/MPU6050_DMP6/Processing/MPUTeapot.pde @@ -0,0 +1,246 @@ +// I2C device class (I2Cdev) demonstration Processing sketch for MPU6050 DMP output +// 6/20/2012 by Jeff Rowberg +// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib +// +// Changelog: +// 2012-06-20 - initial release + +/* ============================================ +I2Cdev device library code is placed under the MIT license +Copyright (c) 2012 Jeff Rowberg + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +=============================================== +*/ + +import processing.serial.*; +import processing.opengl.*; +import toxi.geom.*; +import toxi.processing.*; + +// NOTE: requires ToxicLibs to be installed in order to run properly. +// 1. Download from http://toxiclibs.org/downloads +// 2. Extract into [userdir]/Processing/libraries +// (location may be different on Mac/Linux) +// 3. Run and bask in awesomeness + +ToxiclibsSupport gfx; + +Serial port; // The serial port +char[] teapotPacket = new char[14]; // InvenSense Teapot packet +int serialCount = 0; // current packet byte position +int aligned = 0; +int interval = 0; + +float[] q = new float[4]; +Quaternion quat = new Quaternion(1, 0, 0, 0); + +float[] gravity = new float[3]; +float[] euler = new float[3]; +float[] ypr = new float[3]; + +void setup() { + // 300px square viewport using OpenGL rendering + size(300, 300, OPENGL); + gfx = new ToxiclibsSupport(this); + + // setup lights and antialiasing + lights(); + smooth(); + + // display serial port list for debugging/clarity + println(Serial.list()); + + // get the first available port (use EITHER this OR the specific port code below) + String portName = Serial.list()[0]; + + // get a specific serial port (use EITHER this OR the first-available code above) + //String portName = "COM4"; + + // open the serial port + port = new Serial(this, portName, 115200); + + // send single character to trigger DMP init/start + // (expected by MPU6050_DMP6 example Arduino sketch) + port.write('r'); +} + +void draw() { + if (millis() - interval > 1000) { + // resend single character to trigger DMP init/start + // in case the MPU is halted/reset while applet is running + port.write('r'); + interval = millis(); + } + + // black background + background(0); + + // translate everything to the middle of the viewport + pushMatrix(); + translate(width / 2, height / 2); + + // 3-step rotation from yaw/pitch/roll angles (gimbal lock!) + // ...and other weirdness I haven't figured out yet + //rotateY(-ypr[0]); + //rotateZ(-ypr[1]); + //rotateX(-ypr[2]); + + // toxiclibs direct angle/axis rotation from quaternion (NO gimbal lock!) + // (axis order [1, 3, 2] and inversion [-1, +1, +1] is a consequence of + // different coordinate system orientation assumptions between Processing + // and InvenSense DMP) + float[] axis = quat.toAxisAngle(); + rotate(axis[0], -axis[1], axis[3], axis[2]); + + // draw main body in red + fill(255, 0, 0, 200); + box(10, 10, 200); + + // draw front-facing tip in blue + fill(0, 0, 255, 200); + pushMatrix(); + translate(0, 0, -120); + rotateX(PI/2); + drawCylinder(0, 20, 20, 8); + popMatrix(); + + // draw wings and tail fin in green + fill(0, 255, 0, 200); + beginShape(TRIANGLES); + vertex(-100, 2, 30); vertex(0, 2, -80); vertex(100, 2, 30); // wing top layer + vertex(-100, -2, 30); vertex(0, -2, -80); vertex(100, -2, 30); // wing bottom layer + vertex(-2, 0, 98); vertex(-2, -30, 98); vertex(-2, 0, 70); // tail left layer + vertex( 2, 0, 98); vertex( 2, -30, 98); vertex( 2, 0, 70); // tail right layer + endShape(); + beginShape(QUADS); + vertex(-100, 2, 30); vertex(-100, -2, 30); vertex( 0, -2, -80); vertex( 0, 2, -80); + vertex( 100, 2, 30); vertex( 100, -2, 30); vertex( 0, -2, -80); vertex( 0, 2, -80); + vertex(-100, 2, 30); vertex(-100, -2, 30); vertex(100, -2, 30); vertex(100, 2, 30); + vertex(-2, 0, 98); vertex(2, 0, 98); vertex(2, -30, 98); vertex(-2, -30, 98); + vertex(-2, 0, 98); vertex(2, 0, 98); vertex(2, 0, 70); vertex(-2, 0, 70); + vertex(-2, -30, 98); vertex(2, -30, 98); vertex(2, 0, 70); vertex(-2, 0, 70); + endShape(); + + popMatrix(); +} + +void serialEvent(Serial port) { + interval = millis(); + while (port.available() > 0) { + int ch = port.read(); + print((char)ch); + if (aligned < 4) { + // make sure we are properly aligned on a 14-byte packet + if (serialCount == 0) { + if (ch == '$') aligned++; else aligned = 0; + } else if (serialCount == 1) { + if (ch == 2) aligned++; else aligned = 0; + } else if (serialCount == 12) { + if (ch == '\r') aligned++; else aligned = 0; + } else if (serialCount == 13) { + if (ch == '\n') aligned++; else aligned = 0; + } + //println(ch + " " + aligned + " " + serialCount); + serialCount++; + if (serialCount == 14) serialCount = 0; + } else { + if (serialCount > 0 || ch == '$') { + teapotPacket[serialCount++] = (char)ch; + if (serialCount == 14) { + serialCount = 0; // restart packet byte position + + // get quaternion from data packet + q[0] = ((teapotPacket[2] << 8) | teapotPacket[3]) / 16384.0f; + q[1] = ((teapotPacket[4] << 8) | teapotPacket[5]) / 16384.0f; + q[2] = ((teapotPacket[6] << 8) | teapotPacket[7]) / 16384.0f; + q[3] = ((teapotPacket[8] << 8) | teapotPacket[9]) / 16384.0f; + for (int i = 0; i < 4; i++) if (q[i] >= 2) q[i] = -4 + q[i]; + + // set our toxilibs quaternion to new data + quat.set(q[0], q[1], q[2], q[3]); + + /* + // below calculations unnecessary for orientation only using toxilibs + + // calculate gravity vector + gravity[0] = 2 * (q[1]*q[3] - q[0]*q[2]); + gravity[1] = 2 * (q[0]*q[1] + q[2]*q[3]); + gravity[2] = q[0]*q[0] - q[1]*q[1] - q[2]*q[2] + q[3]*q[3]; + + // calculate Euler angles + euler[0] = atan2(2*q[1]*q[2] - 2*q[0]*q[3], 2*q[0]*q[0] + 2*q[1]*q[1] - 1); + euler[1] = -asin(2*q[1]*q[3] + 2*q[0]*q[2]); + euler[2] = atan2(2*q[2]*q[3] - 2*q[0]*q[1], 2*q[0]*q[0] + 2*q[3]*q[3] - 1); + + // calculate yaw/pitch/roll angles + ypr[0] = atan2(2*q[1]*q[2] - 2*q[0]*q[3], 2*q[0]*q[0] + 2*q[1]*q[1] - 1); + ypr[1] = atan(gravity[0] / sqrt(gravity[1]*gravity[1] + gravity[2]*gravity[2])); + ypr[2] = atan(gravity[1] / sqrt(gravity[0]*gravity[0] + gravity[2]*gravity[2])); + + // output various components for debugging + //println("q:\t" + round(q[0]*100.0f)/100.0f + "\t" + round(q[1]*100.0f)/100.0f + "\t" + round(q[2]*100.0f)/100.0f + "\t" + round(q[3]*100.0f)/100.0f); + //println("euler:\t" + euler[0]*180.0f/PI + "\t" + euler[1]*180.0f/PI + "\t" + euler[2]*180.0f/PI); + //println("ypr:\t" + ypr[0]*180.0f/PI + "\t" + ypr[1]*180.0f/PI + "\t" + ypr[2]*180.0f/PI); + */ + } + } + } + } +} + +void drawCylinder(float topRadius, float bottomRadius, float tall, int sides) { + float angle = 0; + float angleIncrement = TWO_PI / sides; + beginShape(QUAD_STRIP); + for (int i = 0; i < sides + 1; ++i) { + vertex(topRadius*cos(angle), 0, topRadius*sin(angle)); + vertex(bottomRadius*cos(angle), tall, bottomRadius*sin(angle)); + angle += angleIncrement; + } + endShape(); + + // If it is not a cone, draw the circular top cap + if (topRadius != 0) { + angle = 0; + beginShape(TRIANGLE_FAN); + + // Center point + vertex(0, 0, 0); + for (int i = 0; i < sides + 1; i++) { + vertex(topRadius * cos(angle), 0, topRadius * sin(angle)); + angle += angleIncrement; + } + endShape(); + } + + // If it is not a cone, draw the circular bottom cap + if (bottomRadius != 0) { + angle = 0; + beginShape(TRIANGLE_FAN); + + // Center point + vertex(0, tall, 0); + for (int i = 0; i < sides + 1; i++) { + vertex(bottomRadius * cos(angle), tall, bottomRadius * sin(angle)); + angle += angleIncrement; + } + endShape(); + } +} diff --git a/hardware/digistump/sam/libraries/MPU6050/Examples/MPU6050_raw/MPU6050_raw.ino b/hardware/digistump/sam/libraries/MPU6050/Examples/MPU6050_raw/MPU6050_raw.ino new file mode 100644 index 0000000..867aea3 --- /dev/null +++ b/hardware/digistump/sam/libraries/MPU6050/Examples/MPU6050_raw/MPU6050_raw.ino @@ -0,0 +1,95 @@ +// I2C device class (I2Cdev) demonstration Arduino sketch for MPU6050 class +// 10/7/2011 by Jeff Rowberg +// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib +// +// Changelog: +// 2011-10-07 - initial release + +/* ============================================ +I2Cdev device library code is placed under the MIT license +Copyright (c) 2011 Jeff Rowberg + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +=============================================== +*/ + +// Arduino Wire library is required if I2Cdev I2CDEV_ARDUINO_WIRE implementation +// is used in I2Cdev.h +#include "Wire.h" + +// I2Cdev and MPU6050 must be installed as libraries, or else the .cpp/.h files +// for both classes must be in the include path of your project +#include "I2Cdev.h" +#include "MPU6050.h" + +// class default I2C address is 0x68 +// specific I2C addresses may be passed as a parameter here +// AD0 low = 0x68 (default for InvenSense evaluation board) +// AD0 high = 0x69 +MPU6050 accelgyro; + +int16_t ax, ay, az; +int16_t gx, gy, gz; + +#define LED_PIN 13 +bool blinkState = false; + +void setup() { + // join I2C bus (I2Cdev library doesn't do this automatically) + Wire1.begin(); + + // initialize serial communication + // (38400 chosen because it works as well at 8MHz as it does at 16MHz, but + // it's really up to you depending on your project) + SerialUSB.begin(9600); + + // initialize device + SerialUSB.println("Initializing I2C devices..."); + accelgyro.initialize(); + + // verify connection + SerialUSB.println("Testing device connections..."); + SerialUSB.println(accelgyro.testConnection() ? "MPU6050 connection successful" : "MPU6050 connection failed"); + + // configure Arduino LED for + pinMode(LED_PIN, OUTPUT); +} + +void loop() { + // read raw accel/gyro measurements from device + accelgyro.getMotion6(&ax, &ay, &az, &gx, &gy, &gz); + + // these methods (and a few others) are also available + //accelgyro.getAcceleration(&ax, &ay, &az); + //accelgyro.getRotation(&gx, &gy, &gz); + + // display tab-separated accel/gyro x/y/z values + SerialUSB.print("a/g:\t"); + SerialUSB.print(ax); SerialUSB.print("\t"); + SerialUSB.print(ay); SerialUSB.print("\t"); + SerialUSB.print(az); SerialUSB.print("\t"); + SerialUSB.print(gx); SerialUSB.print("\t"); + SerialUSB.print(gy); SerialUSB.print("\t"); + SerialUSB.println(gz); + + // blink LED to indicate activity + blinkState = !blinkState; + digitalWrite(LED_PIN, blinkState); + delay(500); +} diff --git a/hardware/digistump/sam/libraries/MPU6050/MPU6050.cpp b/hardware/digistump/sam/libraries/MPU6050/MPU6050.cpp new file mode 100644 index 0000000..3f531ef --- /dev/null +++ b/hardware/digistump/sam/libraries/MPU6050/MPU6050.cpp @@ -0,0 +1,3142 @@ +// I2Cdev library collection - MPU6050 I2C device class +// Based on InvenSense MPU-6050 register map document rev. 2.0, 5/19/2011 (RM-MPU-6000A-00) +// 8/24/2011 by Jeff Rowberg +// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib +// +// Changelog: +// ... - ongoing debug release + +// NOTE: THIS IS ONLY A PARIAL RELEASE. THIS DEVICE CLASS IS CURRENTLY UNDERGOING ACTIVE +// DEVELOPMENT AND IS STILL MISSING SOME IMPORTANT FEATURES. PLEASE KEEP THIS IN MIND IF +// YOU DECIDE TO USE THIS PARTICULAR CODE FOR ANYTHING. + +/* ============================================ +I2Cdev device library code is placed under the MIT license +Copyright (c) 2012 Jeff Rowberg + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +=============================================== +*/ + +#include "MPU6050.h" + +/** Default constructor, uses default I2C address. + * @see MPU6050_DEFAULT_ADDRESS + */ +MPU6050::MPU6050() { + devAddr = MPU6050_DEFAULT_ADDRESS; +} + +/** Specific address constructor. + * @param address I2C address + * @see MPU6050_DEFAULT_ADDRESS + * @see MPU6050_ADDRESS_AD0_LOW + * @see MPU6050_ADDRESS_AD0_HIGH + */ +MPU6050::MPU6050(uint8_t address) { + devAddr = address; +} + +/** Power on and prepare for general usage. + * This will activate the device and take it out of sleep mode (which must be done + * after start-up). This function also sets both the accelerometer and the gyroscope + * to their most sensitive settings, namely +/- 2g and +/- 250 degrees/sec, and sets + * the clock source to use the X Gyro for reference, which is slightly better than + * the default internal clock source. + */ +void MPU6050::initialize() { + setClockSource(MPU6050_CLOCK_PLL_XGYRO); + setFullScaleGyroRange(MPU6050_GYRO_FS_250); + setFullScaleAccelRange(MPU6050_ACCEL_FS_2); + setSleepEnabled(false); // thanks to Jack Elston for pointing this one out! +} + +/** Verify the I2C connection. + * Make sure the device is connected and responds as expected. + * @return True if connection is valid, false otherwise + */ +bool MPU6050::testConnection() { + return getDeviceID() == 0x34; +} + +// AUX_VDDIO register (InvenSense demo code calls this RA_*G_OFFS_TC) + +/** Get the auxiliary I2C supply voltage level. + * When set to 1, the auxiliary I2C bus high logic level is VDD. When cleared to + * 0, the auxiliary I2C bus high logic level is VLOGIC. This does not apply to + * the MPU-6000, which does not have a VLOGIC pin. + * @return I2C supply voltage level (0=VLOGIC, 1=VDD) + */ +uint8_t MPU6050::getAuxVDDIOLevel() { + I2Cdev::readBit(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_PWR_MODE_BIT, buffer); + return buffer[0]; +} +/** Set the auxiliary I2C supply voltage level. + * When set to 1, the auxiliary I2C bus high logic level is VDD. When cleared to + * 0, the auxiliary I2C bus high logic level is VLOGIC. This does not apply to + * the MPU-6000, which does not have a VLOGIC pin. + * @param level I2C supply voltage level (0=VLOGIC, 1=VDD) + */ +void MPU6050::setAuxVDDIOLevel(uint8_t level) { + I2Cdev::writeBit(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_PWR_MODE_BIT, level); +} + +// SMPLRT_DIV register + +/** Get gyroscope output rate divider. + * The sensor register output, FIFO output, DMP sampling, Motion detection, Zero + * Motion detection, and Free Fall detection are all based on the Sample Rate. + * The Sample Rate is generated by dividing the gyroscope output rate by + * SMPLRT_DIV: + * + * Sample Rate = Gyroscope Output Rate / (1 + SMPLRT_DIV) + * + * where Gyroscope Output Rate = 8kHz when the DLPF is disabled (DLPF_CFG = 0 or + * 7), and 1kHz when the DLPF is enabled (see Register 26). + * + * Note: The accelerometer output rate is 1kHz. This means that for a Sample + * Rate greater than 1kHz, the same accelerometer sample may be output to the + * FIFO, DMP, and sensor registers more than once. + * + * For a diagram of the gyroscope and accelerometer signal paths, see Section 8 + * of the MPU-6000/MPU-6050 Product Specification document. + * + * @return Current sample rate + * @see MPU6050_RA_SMPLRT_DIV + */ +uint8_t MPU6050::getRate() { + I2Cdev::readByte(devAddr, MPU6050_RA_SMPLRT_DIV, buffer); + return buffer[0]; +} +/** Set gyroscope sample rate divider. + * @param rate New sample rate divider + * @see getRate() + * @see MPU6050_RA_SMPLRT_DIV + */ +void MPU6050::setRate(uint8_t rate) { + I2Cdev::writeByte(devAddr, MPU6050_RA_SMPLRT_DIV, rate); +} + +// CONFIG register + +/** Get external FSYNC configuration. + * Configures the external Frame Synchronization (FSYNC) pin sampling. An + * external signal connected to the FSYNC pin can be sampled by configuring + * EXT_SYNC_SET. Signal changes to the FSYNC pin are latched so that short + * strobes may be captured. The latched FSYNC signal will be sampled at the + * Sampling Rate, as defined in register 25. After sampling, the latch will + * reset to the current FSYNC signal state. + * + * The sampled value will be reported in place of the least significant bit in + * a sensor data register determined by the value of EXT_SYNC_SET according to + * the following table. + * + * 
+ * EXT_SYNC_SET | FSYNC Bit Location
+ * -------------+-------------------
+ * 0            | Input disabled
+ * 1            | TEMP_OUT_L[0]
+ * 2            | GYRO_XOUT_L[0]
+ * 3            | GYRO_YOUT_L[0]
+ * 4            | GYRO_ZOUT_L[0]
+ * 5            | ACCEL_XOUT_L[0]
+ * 6            | ACCEL_YOUT_L[0]
+ * 7            | ACCEL_ZOUT_L[0]
+ *
+ * + * @return FSYNC configuration value + */ +uint8_t MPU6050::getExternalFrameSync() { + I2Cdev::readBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_EXT_SYNC_SET_BIT, MPU6050_CFG_EXT_SYNC_SET_LENGTH, buffer); + return buffer[0]; +} +/** Set external FSYNC configuration. + * @see getExternalFrameSync() + * @see MPU6050_RA_CONFIG + * @param sync New FSYNC configuration value + */ +void MPU6050::setExternalFrameSync(uint8_t sync) { + I2Cdev::writeBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_EXT_SYNC_SET_BIT, MPU6050_CFG_EXT_SYNC_SET_LENGTH, sync); +} +/** Get digital low-pass filter configuration. + * The DLPF_CFG parameter sets the digital low pass filter configuration. It + * also determines the internal sampling rate used by the device as shown in + * the table below. + * + * Note: The accelerometer output rate is 1kHz. This means that for a Sample + * Rate greater than 1kHz, the same accelerometer sample may be output to the + * FIFO, DMP, and sensor registers more than once. + * + * 
+ *          |   ACCELEROMETER    |           GYROSCOPE
+ * DLPF_CFG | Bandwidth | Delay  | Bandwidth | Delay  | Sample Rate
+ * ---------+-----------+--------+-----------+--------+-------------
+ * 0        | 260Hz     | 0ms    | 256Hz     | 0.98ms | 8kHz
+ * 1        | 184Hz     | 2.0ms  | 188Hz     | 1.9ms  | 1kHz
+ * 2        | 94Hz      | 3.0ms  | 98Hz      | 2.8ms  | 1kHz
+ * 3        | 44Hz      | 4.9ms  | 42Hz      | 4.8ms  | 1kHz
+ * 4        | 21Hz      | 8.5ms  | 20Hz      | 8.3ms  | 1kHz
+ * 5        | 10Hz      | 13.8ms | 10Hz      | 13.4ms | 1kHz
+ * 6        | 5Hz       | 19.0ms | 5Hz       | 18.6ms | 1kHz
+ * 7        |   -- Reserved --   |   -- Reserved --   | Reserved
+ *
+ * + * @return DLFP configuration + * @see MPU6050_RA_CONFIG + * @see MPU6050_CFG_DLPF_CFG_BIT + * @see MPU6050_CFG_DLPF_CFG_LENGTH + */ +uint8_t MPU6050::getDLPFMode() { + I2Cdev::readBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_DLPF_CFG_BIT, MPU6050_CFG_DLPF_CFG_LENGTH, buffer); + return buffer[0]; +} +/** Set digital low-pass filter configuration. + * @param mode New DLFP configuration setting + * @see getDLPFBandwidth() + * @see MPU6050_DLPF_BW_256 + * @see MPU6050_RA_CONFIG + * @see MPU6050_CFG_DLPF_CFG_BIT + * @see MPU6050_CFG_DLPF_CFG_LENGTH + */ +void MPU6050::setDLPFMode(uint8_t mode) { + I2Cdev::writeBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_DLPF_CFG_BIT, MPU6050_CFG_DLPF_CFG_LENGTH, mode); +} + +// GYRO_CONFIG register + +/** Get full-scale gyroscope range. + * The FS_SEL parameter allows setting the full-scale range of the gyro sensors, + * as described in the table below. + * + * 
+ * 0 = +/- 250 degrees/sec
+ * 1 = +/- 500 degrees/sec
+ * 2 = +/- 1000 degrees/sec
+ * 3 = +/- 2000 degrees/sec
+ *
+ * + * @return Current full-scale gyroscope range setting + * @see MPU6050_GYRO_FS_250 + * @see MPU6050_RA_GYRO_CONFIG + * @see MPU6050_GCONFIG_FS_SEL_BIT + * @see MPU6050_GCONFIG_FS_SEL_LENGTH + */ +uint8_t MPU6050::getFullScaleGyroRange() { + I2Cdev::readBits(devAddr, MPU6050_RA_GYRO_CONFIG, MPU6050_GCONFIG_FS_SEL_BIT, MPU6050_GCONFIG_FS_SEL_LENGTH, buffer); + return buffer[0]; +} +/** Set full-scale gyroscope range. + * @param range New full-scale gyroscope range value + * @see getFullScaleRange() + * @see MPU6050_GYRO_FS_250 + * @see MPU6050_RA_GYRO_CONFIG + * @see MPU6050_GCONFIG_FS_SEL_BIT + * @see MPU6050_GCONFIG_FS_SEL_LENGTH + */ +void MPU6050::setFullScaleGyroRange(uint8_t range) { + I2Cdev::writeBits(devAddr, MPU6050_RA_GYRO_CONFIG, MPU6050_GCONFIG_FS_SEL_BIT, MPU6050_GCONFIG_FS_SEL_LENGTH, range); +} + +// ACCEL_CONFIG register + +/** Get self-test enabled setting for accelerometer X axis. + * @return Self-test enabled value + * @see MPU6050_RA_ACCEL_CONFIG + */ +bool MPU6050::getAccelXSelfTest() { + I2Cdev::readBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_XA_ST_BIT, buffer); + return buffer[0]; +} +/** Get self-test enabled setting for accelerometer X axis. + * @param enabled Self-test enabled value + * @see MPU6050_RA_ACCEL_CONFIG + */ +void MPU6050::setAccelXSelfTest(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_XA_ST_BIT, enabled); +} +/** Get self-test enabled value for accelerometer Y axis. + * @return Self-test enabled value + * @see MPU6050_RA_ACCEL_CONFIG + */ +bool MPU6050::getAccelYSelfTest() { + I2Cdev::readBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_YA_ST_BIT, buffer); + return buffer[0]; +} +/** Get self-test enabled value for accelerometer Y axis. + * @param enabled Self-test enabled value + * @see MPU6050_RA_ACCEL_CONFIG + */ +void MPU6050::setAccelYSelfTest(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_YA_ST_BIT, enabled); +} +/** Get self-test enabled value for accelerometer Z axis. + * @return Self-test enabled value + * @see MPU6050_RA_ACCEL_CONFIG + */ +bool MPU6050::getAccelZSelfTest() { + I2Cdev::readBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ZA_ST_BIT, buffer); + return buffer[0]; +} +/** Set self-test enabled value for accelerometer Z axis. + * @param enabled Self-test enabled value + * @see MPU6050_RA_ACCEL_CONFIG + */ +void MPU6050::setAccelZSelfTest(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ZA_ST_BIT, enabled); +} +/** Get full-scale accelerometer range. + * The FS_SEL parameter allows setting the full-scale range of the accelerometer + * sensors, as described in the table below. + * + * 
+ * 0 = +/- 2g
+ * 1 = +/- 4g
+ * 2 = +/- 8g
+ * 3 = +/- 16g
+ *
+ * + * @return Current full-scale accelerometer range setting + * @see MPU6050_ACCEL_FS_2 + * @see MPU6050_RA_ACCEL_CONFIG + * @see MPU6050_ACONFIG_AFS_SEL_BIT + * @see MPU6050_ACONFIG_AFS_SEL_LENGTH + */ +uint8_t MPU6050::getFullScaleAccelRange() { + I2Cdev::readBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_AFS_SEL_BIT, MPU6050_ACONFIG_AFS_SEL_LENGTH, buffer); + return buffer[0]; +} +/** Set full-scale accelerometer range. + * @param range New full-scale accelerometer range setting + * @see getFullScaleAccelRange() + */ +void MPU6050::setFullScaleAccelRange(uint8_t range) { + I2Cdev::writeBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_AFS_SEL_BIT, MPU6050_ACONFIG_AFS_SEL_LENGTH, range); +} +/** Get the high-pass filter configuration. + * The DHPF is a filter module in the path leading to motion detectors (Free + * Fall, Motion threshold, and Zero Motion). The high pass filter output is not + * available to the data registers (see Figure in Section 8 of the MPU-6000/ + * MPU-6050 Product Specification document). + * + * The high pass filter has three modes: + * + * 
+ *    Reset: The filter output settles to zero within one sample. This
+ *           effectively disables the high pass filter. This mode may be toggled
+ *           to quickly settle the filter.
+ *
+ *    On:    The high pass filter will pass signals above the cut off frequency.
+ *
+ *    Hold:  When triggered, the filter holds the present sample. The filter
+ *           output will be the difference between the input sample and the held
+ *           sample.
+ *
+ * + * 
+ * ACCEL_HPF | Filter Mode | Cut-off Frequency
+ * ----------+-------------+------------------
+ * 0         | Reset       | None
+ * 1         | On          | 5Hz
+ * 2         | On          | 2.5Hz
+ * 3         | On          | 1.25Hz
+ * 4         | On          | 0.63Hz
+ * 7         | Hold        | None
+ *
+ * + * @return Current high-pass filter configuration + * @see MPU6050_DHPF_RESET + * @see MPU6050_RA_ACCEL_CONFIG + */ +uint8_t MPU6050::getDHPFMode() { + I2Cdev::readBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ACCEL_HPF_BIT, MPU6050_ACONFIG_ACCEL_HPF_LENGTH, buffer); + return buffer[0]; +} +/** Set the high-pass filter configuration. + * @param bandwidth New high-pass filter configuration + * @see setDHPFMode() + * @see MPU6050_DHPF_RESET + * @see MPU6050_RA_ACCEL_CONFIG + */ +void MPU6050::setDHPFMode(uint8_t bandwidth) { + I2Cdev::writeBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ACCEL_HPF_BIT, MPU6050_ACONFIG_ACCEL_HPF_LENGTH, bandwidth); +} + +// FF_THR register + +/** Get free-fall event acceleration threshold. + * This register configures the detection threshold for Free Fall event + * detection. The unit of FF_THR is 1LSB = 2mg. Free Fall is detected when the + * absolute value of the accelerometer measurements for the three axes are each + * less than the detection threshold. This condition increments the Free Fall + * duration counter (Register 30). The Free Fall interrupt is triggered when the + * Free Fall duration counter reaches the time specified in FF_DUR. + * + * For more details on the Free Fall detection interrupt, see Section 8.2 of the + * MPU-6000/MPU-6050 Product Specification document as well as Registers 56 and + * 58 of this document. + * + * @return Current free-fall acceleration threshold value (LSB = 2mg) + * @see MPU6050_RA_FF_THR + */ +uint8_t MPU6050::getFreefallDetectionThreshold() { + I2Cdev::readByte(devAddr, MPU6050_RA_FF_THR, buffer); + return buffer[0]; +} +/** Get free-fall event acceleration threshold. + * @param threshold New free-fall acceleration threshold value (LSB = 2mg) + * @see getFreefallDetectionThreshold() + * @see MPU6050_RA_FF_THR + */ +void MPU6050::setFreefallDetectionThreshold(uint8_t threshold) { + I2Cdev::writeByte(devAddr, MPU6050_RA_FF_THR, threshold); +} + +// FF_DUR register + +/** Get free-fall event duration threshold. + * This register configures the duration counter threshold for Free Fall event + * detection. The duration counter ticks at 1kHz, therefore FF_DUR has a unit + * of 1 LSB = 1 ms. + * + * The Free Fall duration counter increments while the absolute value of the + * accelerometer measurements are each less than the detection threshold + * (Register 29). The Free Fall interrupt is triggered when the Free Fall + * duration counter reaches the time specified in this register. + * + * For more details on the Free Fall detection interrupt, see Section 8.2 of + * the MPU-6000/MPU-6050 Product Specification document as well as Registers 56 + * and 58 of this document. + * + * @return Current free-fall duration threshold value (LSB = 1ms) + * @see MPU6050_RA_FF_DUR + */ +uint8_t MPU6050::getFreefallDetectionDuration() { + I2Cdev::readByte(devAddr, MPU6050_RA_FF_DUR, buffer); + return buffer[0]; +} +/** Get free-fall event duration threshold. + * @param duration New free-fall duration threshold value (LSB = 1ms) + * @see getFreefallDetectionDuration() + * @see MPU6050_RA_FF_DUR + */ +void MPU6050::setFreefallDetectionDuration(uint8_t duration) { + I2Cdev::writeByte(devAddr, MPU6050_RA_FF_DUR, duration); +} + +// MOT_THR register + +/** Get motion detection event acceleration threshold. + * This register configures the detection threshold for Motion interrupt + * generation. The unit of MOT_THR is 1LSB = 2mg. Motion is detected when the + * absolute value of any of the accelerometer measurements exceeds this Motion + * detection threshold. This condition increments the Motion detection duration + * counter (Register 32). The Motion detection interrupt is triggered when the + * Motion Detection counter reaches the time count specified in MOT_DUR + * (Register 32). + * + * The Motion interrupt will indicate the axis and polarity of detected motion + * in MOT_DETECT_STATUS (Register 97). + * + * For more details on the Motion detection interrupt, see Section 8.3 of the + * MPU-6000/MPU-6050 Product Specification document as well as Registers 56 and + * 58 of this document. + * + * @return Current motion detection acceleration threshold value (LSB = 2mg) + * @see MPU6050_RA_MOT_THR + */ +uint8_t MPU6050::getMotionDetectionThreshold() { + I2Cdev::readByte(devAddr, MPU6050_RA_MOT_THR, buffer); + return buffer[0]; +} +/** Set free-fall event acceleration threshold. + * @param threshold New motion detection acceleration threshold value (LSB = 2mg) + * @see getMotionDetectionThreshold() + * @see MPU6050_RA_MOT_THR + */ +void MPU6050::setMotionDetectionThreshold(uint8_t threshold) { + I2Cdev::writeByte(devAddr, MPU6050_RA_MOT_THR, threshold); +} + +// MOT_DUR register + +/** Get motion detection event duration threshold. + * This register configures the duration counter threshold for Motion interrupt + * generation. The duration counter ticks at 1 kHz, therefore MOT_DUR has a unit + * of 1LSB = 1ms. The Motion detection duration counter increments when the + * absolute value of any of the accelerometer measurements exceeds the Motion + * detection threshold (Register 31). The Motion detection interrupt is + * triggered when the Motion detection counter reaches the time count specified + * in this register. + * + * For more details on the Motion detection interrupt, see Section 8.3 of the + * MPU-6000/MPU-6050 Product Specification document. + * + * @return Current motion detection duration threshold value (LSB = 1ms) + * @see MPU6050_RA_MOT_DUR + */ +uint8_t MPU6050::getMotionDetectionDuration() { + I2Cdev::readByte(devAddr, MPU6050_RA_MOT_DUR, buffer); + return buffer[0]; +} +/** Set motion detection event duration threshold. + * @param duration New motion detection duration threshold value (LSB = 1ms) + * @see getMotionDetectionDuration() + * @see MPU6050_RA_MOT_DUR + */ +void MPU6050::setMotionDetectionDuration(uint8_t duration) { + I2Cdev::writeByte(devAddr, MPU6050_RA_MOT_DUR, duration); +} + +// ZRMOT_THR register + +/** Get zero motion detection event acceleration threshold. + * This register configures the detection threshold for Zero Motion interrupt + * generation. The unit of ZRMOT_THR is 1LSB = 2mg. Zero Motion is detected when + * the absolute value of the accelerometer measurements for the 3 axes are each + * less than the detection threshold. This condition increments the Zero Motion + * duration counter (Register 34). The Zero Motion interrupt is triggered when + * the Zero Motion duration counter reaches the time count specified in + * ZRMOT_DUR (Register 34). + * + * Unlike Free Fall or Motion detection, Zero Motion detection triggers an + * interrupt both when Zero Motion is first detected and when Zero Motion is no + * longer detected. + * + * When a zero motion event is detected, a Zero Motion Status will be indicated + * in the MOT_DETECT_STATUS register (Register 97). When a motion-to-zero-motion + * condition is detected, the status bit is set to 1. When a zero-motion-to- + * motion condition is detected, the status bit is set to 0. + * + * For more details on the Zero Motion detection interrupt, see Section 8.4 of + * the MPU-6000/MPU-6050 Product Specification document as well as Registers 56 + * and 58 of this document. + * + * @return Current zero motion detection acceleration threshold value (LSB = 2mg) + * @see MPU6050_RA_ZRMOT_THR + */ +uint8_t MPU6050::getZeroMotionDetectionThreshold() { + I2Cdev::readByte(devAddr, MPU6050_RA_ZRMOT_THR, buffer); + return buffer[0]; +} +/** Set zero motion detection event acceleration threshold. + * @param threshold New zero motion detection acceleration threshold value (LSB = 2mg) + * @see getZeroMotionDetectionThreshold() + * @see MPU6050_RA_ZRMOT_THR + */ +void MPU6050::setZeroMotionDetectionThreshold(uint8_t threshold) { + I2Cdev::writeByte(devAddr, MPU6050_RA_ZRMOT_THR, threshold); +} + +// ZRMOT_DUR register + +/** Get zero motion detection event duration threshold. + * This register configures the duration counter threshold for Zero Motion + * interrupt generation. The duration counter ticks at 16 Hz, therefore + * ZRMOT_DUR has a unit of 1 LSB = 64 ms. The Zero Motion duration counter + * increments while the absolute value of the accelerometer measurements are + * each less than the detection threshold (Register 33). The Zero Motion + * interrupt is triggered when the Zero Motion duration counter reaches the time + * count specified in this register. + * + * For more details on the Zero Motion detection interrupt, see Section 8.4 of + * the MPU-6000/MPU-6050 Product Specification document, as well as Registers 56 + * and 58 of this document. + * + * @return Current zero motion detection duration threshold value (LSB = 64ms) + * @see MPU6050_RA_ZRMOT_DUR + */ +uint8_t MPU6050::getZeroMotionDetectionDuration() { + I2Cdev::readByte(devAddr, MPU6050_RA_ZRMOT_DUR, buffer); + return buffer[0]; +} +/** Set zero motion detection event duration threshold. + * @param duration New zero motion detection duration threshold value (LSB = 1ms) + * @see getZeroMotionDetectionDuration() + * @see MPU6050_RA_ZRMOT_DUR + */ +void MPU6050::setZeroMotionDetectionDuration(uint8_t duration) { + I2Cdev::writeByte(devAddr, MPU6050_RA_ZRMOT_DUR, duration); +} + +// FIFO_EN register + +/** Get temperature FIFO enabled value. + * When set to 1, this bit enables TEMP_OUT_H and TEMP_OUT_L (Registers 65 and + * 66) to be written into the FIFO buffer. + * @return Current temperature FIFO enabled value + * @see MPU6050_RA_FIFO_EN + */ +bool MPU6050::getTempFIFOEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_TEMP_FIFO_EN_BIT, buffer); + return buffer[0]; +} +/** Set temperature FIFO enabled value. + * @param enabled New temperature FIFO enabled value + * @see getTempFIFOEnabled() + * @see MPU6050_RA_FIFO_EN + */ +void MPU6050::setTempFIFOEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_TEMP_FIFO_EN_BIT, enabled); +} +/** Get gyroscope X-axis FIFO enabled value. + * When set to 1, this bit enables GYRO_XOUT_H and GYRO_XOUT_L (Registers 67 and + * 68) to be written into the FIFO buffer. + * @return Current gyroscope X-axis FIFO enabled value + * @see MPU6050_RA_FIFO_EN + */ +bool MPU6050::getXGyroFIFOEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_XG_FIFO_EN_BIT, buffer); + return buffer[0]; +} +/** Set gyroscope X-axis FIFO enabled value. + * @param enabled New gyroscope X-axis FIFO enabled value + * @see getXGyroFIFOEnabled() + * @see MPU6050_RA_FIFO_EN + */ +void MPU6050::setXGyroFIFOEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_XG_FIFO_EN_BIT, enabled); +} +/** Get gyroscope Y-axis FIFO enabled value. + * When set to 1, this bit enables GYRO_YOUT_H and GYRO_YOUT_L (Registers 69 and + * 70) to be written into the FIFO buffer. + * @return Current gyroscope Y-axis FIFO enabled value + * @see MPU6050_RA_FIFO_EN + */ +bool MPU6050::getYGyroFIFOEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_YG_FIFO_EN_BIT, buffer); + return buffer[0]; +} +/** Set gyroscope Y-axis FIFO enabled value. + * @param enabled New gyroscope Y-axis FIFO enabled value + * @see getYGyroFIFOEnabled() + * @see MPU6050_RA_FIFO_EN + */ +void MPU6050::setYGyroFIFOEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_YG_FIFO_EN_BIT, enabled); +} +/** Get gyroscope Z-axis FIFO enabled value. + * When set to 1, this bit enables GYRO_ZOUT_H and GYRO_ZOUT_L (Registers 71 and + * 72) to be written into the FIFO buffer. + * @return Current gyroscope Z-axis FIFO enabled value + * @see MPU6050_RA_FIFO_EN + */ +bool MPU6050::getZGyroFIFOEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ZG_FIFO_EN_BIT, buffer); + return buffer[0]; +} +/** Set gyroscope Z-axis FIFO enabled value. + * @param enabled New gyroscope Z-axis FIFO enabled value + * @see getZGyroFIFOEnabled() + * @see MPU6050_RA_FIFO_EN + */ +void MPU6050::setZGyroFIFOEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ZG_FIFO_EN_BIT, enabled); +} +/** Get accelerometer FIFO enabled value. + * When set to 1, this bit enables ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, + * ACCEL_YOUT_L, ACCEL_ZOUT_H, and ACCEL_ZOUT_L (Registers 59 to 64) to be + * written into the FIFO buffer. + * @return Current accelerometer FIFO enabled value + * @see MPU6050_RA_FIFO_EN + */ +bool MPU6050::getAccelFIFOEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ACCEL_FIFO_EN_BIT, buffer); + return buffer[0]; +} +/** Set accelerometer FIFO enabled value. + * @param enabled New accelerometer FIFO enabled value + * @see getAccelFIFOEnabled() + * @see MPU6050_RA_FIFO_EN + */ +void MPU6050::setAccelFIFOEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ACCEL_FIFO_EN_BIT, enabled); +} +/** Get Slave 2 FIFO enabled value. + * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96) + * associated with Slave 2 to be written into the FIFO buffer. + * @return Current Slave 2 FIFO enabled value + * @see MPU6050_RA_FIFO_EN + */ +bool MPU6050::getSlave2FIFOEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV2_FIFO_EN_BIT, buffer); + return buffer[0]; +} +/** Set Slave 2 FIFO enabled value. + * @param enabled New Slave 2 FIFO enabled value + * @see getSlave2FIFOEnabled() + * @see MPU6050_RA_FIFO_EN + */ +void MPU6050::setSlave2FIFOEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV2_FIFO_EN_BIT, enabled); +} +/** Get Slave 1 FIFO enabled value. + * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96) + * associated with Slave 1 to be written into the FIFO buffer. + * @return Current Slave 1 FIFO enabled value + * @see MPU6050_RA_FIFO_EN + */ +bool MPU6050::getSlave1FIFOEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV1_FIFO_EN_BIT, buffer); + return buffer[0]; +} +/** Set Slave 1 FIFO enabled value. + * @param enabled New Slave 1 FIFO enabled value + * @see getSlave1FIFOEnabled() + * @see MPU6050_RA_FIFO_EN + */ +void MPU6050::setSlave1FIFOEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV1_FIFO_EN_BIT, enabled); +} +/** Get Slave 0 FIFO enabled value. + * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96) + * associated with Slave 0 to be written into the FIFO buffer. + * @return Current Slave 0 FIFO enabled value + * @see MPU6050_RA_FIFO_EN + */ +bool MPU6050::getSlave0FIFOEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV0_FIFO_EN_BIT, buffer); + return buffer[0]; +} +/** Set Slave 0 FIFO enabled value. + * @param enabled New Slave 0 FIFO enabled value + * @see getSlave0FIFOEnabled() + * @see MPU6050_RA_FIFO_EN + */ +void MPU6050::setSlave0FIFOEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV0_FIFO_EN_BIT, enabled); +} + +// I2C_MST_CTRL register + +/** Get multi-master enabled value. + * Multi-master capability allows multiple I2C masters to operate on the same + * bus. In circuits where multi-master capability is required, set MULT_MST_EN + * to 1. This will increase current drawn by approximately 30uA. + * + * In circuits where multi-master capability is required, the state of the I2C + * bus must always be monitored by each separate I2C Master. Before an I2C + * Master can assume arbitration of the bus, it must first confirm that no other + * I2C Master has arbitration of the bus. When MULT_MST_EN is set to 1, the + * MPU-60X0's bus arbitration detection logic is turned on, enabling it to + * detect when the bus is available. + * + * @return Current multi-master enabled value + * @see MPU6050_RA_I2C_MST_CTRL + */ +bool MPU6050::getMultiMasterEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_MULT_MST_EN_BIT, buffer); + return buffer[0]; +} +/** Set multi-master enabled value. + * @param enabled New multi-master enabled value + * @see getMultiMasterEnabled() + * @see MPU6050_RA_I2C_MST_CTRL + */ +void MPU6050::setMultiMasterEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_MULT_MST_EN_BIT, enabled); +} +/** Get wait-for-external-sensor-data enabled value. + * When the WAIT_FOR_ES bit is set to 1, the Data Ready interrupt will be + * delayed until External Sensor data from the Slave Devices are loaded into the + * EXT_SENS_DATA registers. This is used to ensure that both the internal sensor + * data (i.e. from gyro and accel) and external sensor data have been loaded to + * their respective data registers (i.e. the data is synced) when the Data Ready + * interrupt is triggered. + * + * @return Current wait-for-external-sensor-data enabled value + * @see MPU6050_RA_I2C_MST_CTRL + */ +bool MPU6050::getWaitForExternalSensorEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_WAIT_FOR_ES_BIT, buffer); + return buffer[0]; +} +/** Set wait-for-external-sensor-data enabled value. + * @param enabled New wait-for-external-sensor-data enabled value + * @see getWaitForExternalSensorEnabled() + * @see MPU6050_RA_I2C_MST_CTRL + */ +void MPU6050::setWaitForExternalSensorEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_WAIT_FOR_ES_BIT, enabled); +} +/** Get Slave 3 FIFO enabled value. + * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96) + * associated with Slave 3 to be written into the FIFO buffer. + * @return Current Slave 3 FIFO enabled value + * @see MPU6050_RA_MST_CTRL + */ +bool MPU6050::getSlave3FIFOEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_SLV_3_FIFO_EN_BIT, buffer); + return buffer[0]; +} +/** Set Slave 3 FIFO enabled value. + * @param enabled New Slave 3 FIFO enabled value + * @see getSlave3FIFOEnabled() + * @see MPU6050_RA_MST_CTRL + */ +void MPU6050::setSlave3FIFOEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_SLV_3_FIFO_EN_BIT, enabled); +} +/** Get slave read/write transition enabled value. + * The I2C_MST_P_NSR bit configures the I2C Master's transition from one slave + * read to the next slave read. If the bit equals 0, there will be a restart + * between reads. If the bit equals 1, there will be a stop followed by a start + * of the following read. When a write transaction follows a read transaction, + * the stop followed by a start of the successive write will be always used. + * + * @return Current slave read/write transition enabled value + * @see MPU6050_RA_I2C_MST_CTRL + */ +bool MPU6050::getSlaveReadWriteTransitionEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_P_NSR_BIT, buffer); + return buffer[0]; +} +/** Set slave read/write transition enabled value. + * @param enabled New slave read/write transition enabled value + * @see getSlaveReadWriteTransitionEnabled() + * @see MPU6050_RA_I2C_MST_CTRL + */ +void MPU6050::setSlaveReadWriteTransitionEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_P_NSR_BIT, enabled); +} +/** Get I2C master clock speed. + * I2C_MST_CLK is a 4 bit unsigned value which configures a divider on the + * MPU-60X0 internal 8MHz clock. It sets the I2C master clock speed according to + * the following table: + * + * 
+ * I2C_MST_CLK | I2C Master Clock Speed | 8MHz Clock Divider
+ * ------------+------------------------+-------------------
+ * 0           | 348kHz                 | 23
+ * 1           | 333kHz                 | 24
+ * 2           | 320kHz                 | 25
+ * 3           | 308kHz                 | 26
+ * 4           | 296kHz                 | 27
+ * 5           | 286kHz                 | 28
+ * 6           | 276kHz                 | 29
+ * 7           | 267kHz                 | 30
+ * 8           | 258kHz                 | 31
+ * 9           | 500kHz                 | 16
+ * 10          | 471kHz                 | 17
+ * 11          | 444kHz                 | 18
+ * 12          | 421kHz                 | 19
+ * 13          | 400kHz                 | 20
+ * 14          | 381kHz                 | 21
+ * 15          | 364kHz                 | 22
+ *
+ * + * @return Current I2C master clock speed + * @see MPU6050_RA_I2C_MST_CTRL + */ +uint8_t MPU6050::getMasterClockSpeed() { + I2Cdev::readBits(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_CLK_BIT, MPU6050_I2C_MST_CLK_LENGTH, buffer); + return buffer[0]; +} +/** Set I2C master clock speed. + * @reparam speed Current I2C master clock speed + * @see MPU6050_RA_I2C_MST_CTRL + */ +void MPU6050::setMasterClockSpeed(uint8_t speed) { + I2Cdev::writeBits(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_CLK_BIT, MPU6050_I2C_MST_CLK_LENGTH, speed); +} + +// I2C_SLV* registers (Slave 0-3) + +/** Get the I2C address of the specified slave (0-3). + * Note that Bit 7 (MSB) controls read/write mode. If Bit 7 is set, it's a read + * operation, and if it is cleared, then it's a write operation. The remaining + * bits (6-0) are the 7-bit device address of the slave device. + * + * In read mode, the result of the read is placed in the lowest available + * EXT_SENS_DATA register. For further information regarding the allocation of + * read results, please refer to the EXT_SENS_DATA register description + * (Registers 73 - 96). + * + * The MPU-6050 supports a total of five slaves, but Slave 4 has unique + * characteristics, and so it has its own functions (getSlave4* and setSlave4*). + * + * I2C data transactions are performed at the Sample Rate, as defined in + * Register 25. The user is responsible for ensuring that I2C data transactions + * to and from each enabled Slave can be completed within a single period of the + * Sample Rate. + * + * The I2C slave access rate can be reduced relative to the Sample Rate. This + * reduced access rate is determined by I2C_MST_DLY (Register 52). Whether a + * slave's access rate is reduced relative to the Sample Rate is determined by + * I2C_MST_DELAY_CTRL (Register 103). + * + * The processing order for the slaves is fixed. The sequence followed for + * processing the slaves is Slave 0, Slave 1, Slave 2, Slave 3 and Slave 4. If a + * particular Slave is disabled it will be skipped. + * + * Each slave can either be accessed at the sample rate or at a reduced sample + * rate. In a case where some slaves are accessed at the Sample Rate and some + * slaves are accessed at the reduced rate, the sequence of accessing the slaves + * (Slave 0 to Slave 4) is still followed. However, the reduced rate slaves will + * be skipped if their access rate dictates that they should not be accessed + * during that particular cycle. For further information regarding the reduced + * access rate, please refer to Register 52. Whether a slave is accessed at the + * Sample Rate or at the reduced rate is determined by the Delay Enable bits in + * Register 103. + * + * @param num Slave number (0-3) + * @return Current address for specified slave + * @see MPU6050_RA_I2C_SLV0_ADDR + */ +uint8_t MPU6050::getSlaveAddress(uint8_t num) { + if (num > 3) return 0; + I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV0_ADDR + num*3, buffer); + return buffer[0]; +} +/** Set the I2C address of the specified slave (0-3). + * @param num Slave number (0-3) + * @param address New address for specified slave + * @see getSlaveAddress() + * @see MPU6050_RA_I2C_SLV0_ADDR + */ +void MPU6050::setSlaveAddress(uint8_t num, uint8_t address) { + if (num > 3) return; + I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV0_ADDR + num*3, address); +} +/** Get the active internal register for the specified slave (0-3). + * Read/write operations for this slave will be done to whatever internal + * register address is stored in this MPU register. + * + * The MPU-6050 supports a total of five slaves, but Slave 4 has unique + * characteristics, and so it has its own functions. + * + * @param num Slave number (0-3) + * @return Current active register for specified slave + * @see MPU6050_RA_I2C_SLV0_REG + */ +uint8_t MPU6050::getSlaveRegister(uint8_t num) { + if (num > 3) return 0; + I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV0_REG + num*3, buffer); + return buffer[0]; +} +/** Set the active internal register for the specified slave (0-3). + * @param num Slave number (0-3) + * @param reg New active register for specified slave + * @see getSlaveRegister() + * @see MPU6050_RA_I2C_SLV0_REG + */ +void MPU6050::setSlaveRegister(uint8_t num, uint8_t reg) { + if (num > 3) return; + I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV0_REG + num*3, reg); +} +/** Get the enabled value for the specified slave (0-3). + * When set to 1, this bit enables Slave 0 for data transfer operations. When + * cleared to 0, this bit disables Slave 0 from data transfer operations. + * @param num Slave number (0-3) + * @return Current enabled value for specified slave + * @see MPU6050_RA_I2C_SLV0_CTRL + */ +bool MPU6050::getSlaveEnabled(uint8_t num) { + if (num > 3) return 0; + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_EN_BIT, buffer); + return buffer[0]; +} +/** Set the enabled value for the specified slave (0-3). + * @param num Slave number (0-3) + * @param enabled New enabled value for specified slave + * @see getSlaveEnabled() + * @see MPU6050_RA_I2C_SLV0_CTRL + */ +void MPU6050::setSlaveEnabled(uint8_t num, bool enabled) { + if (num > 3) return; + I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_EN_BIT, enabled); +} +/** Get word pair byte-swapping enabled for the specified slave (0-3). + * When set to 1, this bit enables byte swapping. When byte swapping is enabled, + * the high and low bytes of a word pair are swapped. Please refer to + * I2C_SLV0_GRP for the pairing convention of the word pairs. When cleared to 0, + * bytes transferred to and from Slave 0 will be written to EXT_SENS_DATA + * registers in the order they were transferred. + * + * @param num Slave number (0-3) + * @return Current word pair byte-swapping enabled value for specified slave + * @see MPU6050_RA_I2C_SLV0_CTRL + */ +bool MPU6050::getSlaveWordByteSwap(uint8_t num) { + if (num > 3) return 0; + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_BYTE_SW_BIT, buffer); + return buffer[0]; +} +/** Set word pair byte-swapping enabled for the specified slave (0-3). + * @param num Slave number (0-3) + * @param enabled New word pair byte-swapping enabled value for specified slave + * @see getSlaveWordByteSwap() + * @see MPU6050_RA_I2C_SLV0_CTRL + */ +void MPU6050::setSlaveWordByteSwap(uint8_t num, bool enabled) { + if (num > 3) return; + I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_BYTE_SW_BIT, enabled); +} +/** Get write mode for the specified slave (0-3). + * When set to 1, the transaction will read or write data only. When cleared to + * 0, the transaction will write a register address prior to reading or writing + * data. This should equal 0 when specifying the register address within the + * Slave device to/from which the ensuing data transaction will take place. + * + * @param num Slave number (0-3) + * @return Current write mode for specified slave (0 = register address + data, 1 = data only) + * @see MPU6050_RA_I2C_SLV0_CTRL + */ +bool MPU6050::getSlaveWriteMode(uint8_t num) { + if (num > 3) return 0; + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_REG_DIS_BIT, buffer); + return buffer[0]; +} +/** Set write mode for the specified slave (0-3). + * @param num Slave number (0-3) + * @param mode New write mode for specified slave (0 = register address + data, 1 = data only) + * @see getSlaveWriteMode() + * @see MPU6050_RA_I2C_SLV0_CTRL + */ +void MPU6050::setSlaveWriteMode(uint8_t num, bool mode) { + if (num > 3) return; + I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_REG_DIS_BIT, mode); +} +/** Get word pair grouping order offset for the specified slave (0-3). + * This sets specifies the grouping order of word pairs received from registers. + * When cleared to 0, bytes from register addresses 0 and 1, 2 and 3, etc (even, + * then odd register addresses) are paired to form a word. When set to 1, bytes + * from register addresses are paired 1 and 2, 3 and 4, etc. (odd, then even + * register addresses) are paired to form a word. + * + * @param num Slave number (0-3) + * @return Current word pair grouping order offset for specified slave + * @see MPU6050_RA_I2C_SLV0_CTRL + */ +bool MPU6050::getSlaveWordGroupOffset(uint8_t num) { + if (num > 3) return 0; + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_GRP_BIT, buffer); + return buffer[0]; +} +/** Set word pair grouping order offset for the specified slave (0-3). + * @param num Slave number (0-3) + * @param enabled New word pair grouping order offset for specified slave + * @see getSlaveWordGroupOffset() + * @see MPU6050_RA_I2C_SLV0_CTRL + */ +void MPU6050::setSlaveWordGroupOffset(uint8_t num, bool enabled) { + if (num > 3) return; + I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_GRP_BIT, enabled); +} +/** Get number of bytes to read for the specified slave (0-3). + * Specifies the number of bytes transferred to and from Slave 0. Clearing this + * bit to 0 is equivalent to disabling the register by writing 0 to I2C_SLV0_EN. + * @param num Slave number (0-3) + * @return Number of bytes to read for specified slave + * @see MPU6050_RA_I2C_SLV0_CTRL + */ +uint8_t MPU6050::getSlaveDataLength(uint8_t num) { + if (num > 3) return 0; + I2Cdev::readBits(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_LEN_BIT, MPU6050_I2C_SLV_LEN_LENGTH, buffer); + return buffer[0]; +} +/** Set number of bytes to read for the specified slave (0-3). + * @param num Slave number (0-3) + * @param length Number of bytes to read for specified slave + * @see getSlaveDataLength() + * @see MPU6050_RA_I2C_SLV0_CTRL + */ +void MPU6050::setSlaveDataLength(uint8_t num, uint8_t length) { + if (num > 3) return; + I2Cdev::writeBits(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num*3, MPU6050_I2C_SLV_LEN_BIT, MPU6050_I2C_SLV_LEN_LENGTH, length); +} + +// I2C_SLV* registers (Slave 4) + +/** Get the I2C address of Slave 4. + * Note that Bit 7 (MSB) controls read/write mode. If Bit 7 is set, it's a read + * operation, and if it is cleared, then it's a write operation. The remaining + * bits (6-0) are the 7-bit device address of the slave device. + * + * @return Current address for Slave 4 + * @see getSlaveAddress() + * @see MPU6050_RA_I2C_SLV4_ADDR + */ +uint8_t MPU6050::getSlave4Address() { + I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV4_ADDR, buffer); + return buffer[0]; +} +/** Set the I2C address of Slave 4. + * @param address New address for Slave 4 + * @see getSlave4Address() + * @see MPU6050_RA_I2C_SLV4_ADDR + */ +void MPU6050::setSlave4Address(uint8_t address) { + I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV4_ADDR, address); +} +/** Get the active internal register for the Slave 4. + * Read/write operations for this slave will be done to whatever internal + * register address is stored in this MPU register. + * + * @return Current active register for Slave 4 + * @see MPU6050_RA_I2C_SLV4_REG + */ +uint8_t MPU6050::getSlave4Register() { + I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV4_REG, buffer); + return buffer[0]; +} +/** Set the active internal register for Slave 4. + * @param reg New active register for Slave 4 + * @see getSlave4Register() + * @see MPU6050_RA_I2C_SLV4_REG + */ +void MPU6050::setSlave4Register(uint8_t reg) { + I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV4_REG, reg); +} +/** Set new byte to write to Slave 4. + * This register stores the data to be written into the Slave 4. If I2C_SLV4_RW + * is set 1 (set to read), this register has no effect. + * @param data New byte to write to Slave 4 + * @see MPU6050_RA_I2C_SLV4_DO + */ +void MPU6050::setSlave4OutputByte(uint8_t data) { + I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV4_DO, data); +} +/** Get the enabled value for the Slave 4. + * When set to 1, this bit enables Slave 4 for data transfer operations. When + * cleared to 0, this bit disables Slave 4 from data transfer operations. + * @return Current enabled value for Slave 4 + * @see MPU6050_RA_I2C_SLV4_CTRL + */ +bool MPU6050::getSlave4Enabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_EN_BIT, buffer); + return buffer[0]; +} +/** Set the enabled value for Slave 4. + * @param enabled New enabled value for Slave 4 + * @see getSlave4Enabled() + * @see MPU6050_RA_I2C_SLV4_CTRL + */ +void MPU6050::setSlave4Enabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_EN_BIT, enabled); +} +/** Get the enabled value for Slave 4 transaction interrupts. + * When set to 1, this bit enables the generation of an interrupt signal upon + * completion of a Slave 4 transaction. When cleared to 0, this bit disables the + * generation of an interrupt signal upon completion of a Slave 4 transaction. + * The interrupt status can be observed in Register 54. + * + * @return Current enabled value for Slave 4 transaction interrupts. + * @see MPU6050_RA_I2C_SLV4_CTRL + */ +bool MPU6050::getSlave4InterruptEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_INT_EN_BIT, buffer); + return buffer[0]; +} +/** Set the enabled value for Slave 4 transaction interrupts. + * @param enabled New enabled value for Slave 4 transaction interrupts. + * @see getSlave4InterruptEnabled() + * @see MPU6050_RA_I2C_SLV4_CTRL + */ +void MPU6050::setSlave4InterruptEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_INT_EN_BIT, enabled); +} +/** Get write mode for Slave 4. + * When set to 1, the transaction will read or write data only. When cleared to + * 0, the transaction will write a register address prior to reading or writing + * data. This should equal 0 when specifying the register address within the + * Slave device to/from which the ensuing data transaction will take place. + * + * @return Current write mode for Slave 4 (0 = register address + data, 1 = data only) + * @see MPU6050_RA_I2C_SLV4_CTRL + */ +bool MPU6050::getSlave4WriteMode() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_REG_DIS_BIT, buffer); + return buffer[0]; +} +/** Set write mode for the Slave 4. + * @param mode New write mode for Slave 4 (0 = register address + data, 1 = data only) + * @see getSlave4WriteMode() + * @see MPU6050_RA_I2C_SLV4_CTRL + */ +void MPU6050::setSlave4WriteMode(bool mode) { + I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_REG_DIS_BIT, mode); +} +/** Get Slave 4 master delay value. + * This configures the reduced access rate of I2C slaves relative to the Sample + * Rate. When a slave's access rate is decreased relative to the Sample Rate, + * the slave is accessed every: + * + * 1 / (1 + I2C_MST_DLY) samples + * + * This base Sample Rate in turn is determined by SMPLRT_DIV (register 25) and + * DLPF_CFG (register 26). Whether a slave's access rate is reduced relative to + * the Sample Rate is determined by I2C_MST_DELAY_CTRL (register 103). For + * further information regarding the Sample Rate, please refer to register 25. + * + * @return Current Slave 4 master delay value + * @see MPU6050_RA_I2C_SLV4_CTRL + */ +uint8_t MPU6050::getSlave4MasterDelay() { + I2Cdev::readBits(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_MST_DLY_BIT, MPU6050_I2C_SLV4_MST_DLY_LENGTH, buffer); + return buffer[0]; +} +/** Set Slave 4 master delay value. + * @param delay New Slave 4 master delay value + * @see getSlave4MasterDelay() + * @see MPU6050_RA_I2C_SLV4_CTRL + */ +void MPU6050::setSlave4MasterDelay(uint8_t delay) { + I2Cdev::writeBits(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_MST_DLY_BIT, MPU6050_I2C_SLV4_MST_DLY_LENGTH, delay); +} +/** Get last available byte read from Slave 4. + * This register stores the data read from Slave 4. This field is populated + * after a read transaction. + * @return Last available byte read from to Slave 4 + * @see MPU6050_RA_I2C_SLV4_DI + */ +uint8_t MPU6050::getSlate4InputByte() { + I2Cdev::readByte(devAddr, MPU6050_RA_I2C_SLV4_DI, buffer); + return buffer[0]; +} + +// I2C_MST_STATUS register + +/** Get FSYNC interrupt status. + * This bit reflects the status of the FSYNC interrupt from an external device + * into the MPU-60X0. This is used as a way to pass an external interrupt + * through the MPU-60X0 to the host application processor. When set to 1, this + * bit will cause an interrupt if FSYNC_INT_EN is asserted in INT_PIN_CFG + * (Register 55). + * @return FSYNC interrupt status + * @see MPU6050_RA_I2C_MST_STATUS + */ +bool MPU6050::getPassthroughStatus() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_PASS_THROUGH_BIT, buffer); + return buffer[0]; +} +/** Get Slave 4 transaction done status. + * Automatically sets to 1 when a Slave 4 transaction has completed. This + * triggers an interrupt if the I2C_MST_INT_EN bit in the INT_ENABLE register + * (Register 56) is asserted and if the SLV_4_DONE_INT bit is asserted in the + * I2C_SLV4_CTRL register (Register 52). + * @return Slave 4 transaction done status + * @see MPU6050_RA_I2C_MST_STATUS + */ +bool MPU6050::getSlave4IsDone() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV4_DONE_BIT, buffer); + return buffer[0]; +} +/** Get master arbitration lost status. + * This bit automatically sets to 1 when the I2C Master has lost arbitration of + * the auxiliary I2C bus (an error condition). This triggers an interrupt if the + * I2C_MST_INT_EN bit in the INT_ENABLE register (Register 56) is asserted. + * @return Master arbitration lost status + * @see MPU6050_RA_I2C_MST_STATUS + */ +bool MPU6050::getLostArbitration() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_LOST_ARB_BIT, buffer); + return buffer[0]; +} +/** Get Slave 4 NACK status. + * This bit automatically sets to 1 when the I2C Master receives a NACK in a + * transaction with Slave 4. This triggers an interrupt if the I2C_MST_INT_EN + * bit in the INT_ENABLE register (Register 56) is asserted. + * @return Slave 4 NACK interrupt status + * @see MPU6050_RA_I2C_MST_STATUS + */ +bool MPU6050::getSlave4Nack() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV4_NACK_BIT, buffer); + return buffer[0]; +} +/** Get Slave 3 NACK status. + * This bit automatically sets to 1 when the I2C Master receives a NACK in a + * transaction with Slave 3. This triggers an interrupt if the I2C_MST_INT_EN + * bit in the INT_ENABLE register (Register 56) is asserted. + * @return Slave 3 NACK interrupt status + * @see MPU6050_RA_I2C_MST_STATUS + */ +bool MPU6050::getSlave3Nack() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV3_NACK_BIT, buffer); + return buffer[0]; +} +/** Get Slave 2 NACK status. + * This bit automatically sets to 1 when the I2C Master receives a NACK in a + * transaction with Slave 2. This triggers an interrupt if the I2C_MST_INT_EN + * bit in the INT_ENABLE register (Register 56) is asserted. + * @return Slave 2 NACK interrupt status + * @see MPU6050_RA_I2C_MST_STATUS + */ +bool MPU6050::getSlave2Nack() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV2_NACK_BIT, buffer); + return buffer[0]; +} +/** Get Slave 1 NACK status. + * This bit automatically sets to 1 when the I2C Master receives a NACK in a + * transaction with Slave 1. This triggers an interrupt if the I2C_MST_INT_EN + * bit in the INT_ENABLE register (Register 56) is asserted. + * @return Slave 1 NACK interrupt status + * @see MPU6050_RA_I2C_MST_STATUS + */ +bool MPU6050::getSlave1Nack() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV1_NACK_BIT, buffer); + return buffer[0]; +} +/** Get Slave 0 NACK status. + * This bit automatically sets to 1 when the I2C Master receives a NACK in a + * transaction with Slave 0. This triggers an interrupt if the I2C_MST_INT_EN + * bit in the INT_ENABLE register (Register 56) is asserted. + * @return Slave 0 NACK interrupt status + * @see MPU6050_RA_I2C_MST_STATUS + */ +bool MPU6050::getSlave0Nack() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV0_NACK_BIT, buffer); + return buffer[0]; +} + +// INT_PIN_CFG register + +/** Get interrupt logic level mode. + * Will be set 0 for active-high, 1 for active-low. + * @return Current interrupt mode (0=active-high, 1=active-low) + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_INT_LEVEL_BIT + */ +bool MPU6050::getInterruptMode() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_LEVEL_BIT, buffer); + return buffer[0]; +} +/** Set interrupt logic level mode. + * @param mode New interrupt mode (0=active-high, 1=active-low) + * @see getInterruptMode() + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_INT_LEVEL_BIT + */ +void MPU6050::setInterruptMode(bool mode) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_LEVEL_BIT, mode); +} +/** Get interrupt drive mode. + * Will be set 0 for push-pull, 1 for open-drain. + * @return Current interrupt drive mode (0=push-pull, 1=open-drain) + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_INT_OPEN_BIT + */ +bool MPU6050::getInterruptDrive() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_OPEN_BIT, buffer); + return buffer[0]; +} +/** Set interrupt drive mode. + * @param drive New interrupt drive mode (0=push-pull, 1=open-drain) + * @see getInterruptDrive() + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_INT_OPEN_BIT + */ +void MPU6050::setInterruptDrive(bool drive) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_OPEN_BIT, drive); +} +/** Get interrupt latch mode. + * Will be set 0 for 50us-pulse, 1 for latch-until-int-cleared. + * @return Current latch mode (0=50us-pulse, 1=latch-until-int-cleared) + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_LATCH_INT_EN_BIT + */ +bool MPU6050::getInterruptLatch() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_LATCH_INT_EN_BIT, buffer); + return buffer[0]; +} +/** Set interrupt latch mode. + * @param latch New latch mode (0=50us-pulse, 1=latch-until-int-cleared) + * @see getInterruptLatch() + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_LATCH_INT_EN_BIT + */ +void MPU6050::setInterruptLatch(bool latch) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_LATCH_INT_EN_BIT, latch); +} +/** Get interrupt latch clear mode. + * Will be set 0 for status-read-only, 1 for any-register-read. + * @return Current latch clear mode (0=status-read-only, 1=any-register-read) + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_INT_RD_CLEAR_BIT + */ +bool MPU6050::getInterruptLatchClear() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_RD_CLEAR_BIT, buffer); + return buffer[0]; +} +/** Set interrupt latch clear mode. + * @param clear New latch clear mode (0=status-read-only, 1=any-register-read) + * @see getInterruptLatchClear() + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_INT_RD_CLEAR_BIT + */ +void MPU6050::setInterruptLatchClear(bool clear) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_RD_CLEAR_BIT, clear); +} +/** Get FSYNC interrupt logic level mode. + * @return Current FSYNC interrupt mode (0=active-high, 1=active-low) + * @see getFSyncInterruptMode() + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT + */ +bool MPU6050::getFSyncInterruptLevel() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT, buffer); + return buffer[0]; +} +/** Set FSYNC interrupt logic level mode. + * @param mode New FSYNC interrupt mode (0=active-high, 1=active-low) + * @see getFSyncInterruptMode() + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT + */ +void MPU6050::setFSyncInterruptLevel(bool level) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT, level); +} +/** Get FSYNC pin interrupt enabled setting. + * Will be set 0 for disabled, 1 for enabled. + * @return Current interrupt enabled setting + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_FSYNC_INT_EN_BIT + */ +bool MPU6050::getFSyncInterruptEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_EN_BIT, buffer); + return buffer[0]; +} +/** Set FSYNC pin interrupt enabled setting. + * @param enabled New FSYNC pin interrupt enabled setting + * @see getFSyncInterruptEnabled() + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_FSYNC_INT_EN_BIT + */ +void MPU6050::setFSyncInterruptEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_EN_BIT, enabled); +} +/** Get I2C bypass enabled status. + * When this bit is equal to 1 and I2C_MST_EN (Register 106 bit[5]) is equal to + * 0, the host application processor will be able to directly access the + * auxiliary I2C bus of the MPU-60X0. When this bit is equal to 0, the host + * application processor will not be able to directly access the auxiliary I2C + * bus of the MPU-60X0 regardless of the state of I2C_MST_EN (Register 106 + * bit[5]). + * @return Current I2C bypass enabled status + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_I2C_BYPASS_EN_BIT + */ +bool MPU6050::getI2CBypassEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_I2C_BYPASS_EN_BIT, buffer); + return buffer[0]; +} +/** Set I2C bypass enabled status. + * When this bit is equal to 1 and I2C_MST_EN (Register 106 bit[5]) is equal to + * 0, the host application processor will be able to directly access the + * auxiliary I2C bus of the MPU-60X0. When this bit is equal to 0, the host + * application processor will not be able to directly access the auxiliary I2C + * bus of the MPU-60X0 regardless of the state of I2C_MST_EN (Register 106 + * bit[5]). + * @param enabled New I2C bypass enabled status + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_I2C_BYPASS_EN_BIT + */ +void MPU6050::setI2CBypassEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_I2C_BYPASS_EN_BIT, enabled); +} +/** Get reference clock output enabled status. + * When this bit is equal to 1, a reference clock output is provided at the + * CLKOUT pin. When this bit is equal to 0, the clock output is disabled. For + * further information regarding CLKOUT, please refer to the MPU-60X0 Product + * Specification document. + * @return Current reference clock output enabled status + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_CLKOUT_EN_BIT + */ +bool MPU6050::getClockOutputEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_CLKOUT_EN_BIT, buffer); + return buffer[0]; +} +/** Set reference clock output enabled status. + * When this bit is equal to 1, a reference clock output is provided at the + * CLKOUT pin. When this bit is equal to 0, the clock output is disabled. For + * further information regarding CLKOUT, please refer to the MPU-60X0 Product + * Specification document. + * @param enabled New reference clock output enabled status + * @see MPU6050_RA_INT_PIN_CFG + * @see MPU6050_INTCFG_CLKOUT_EN_BIT + */ +void MPU6050::setClockOutputEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_CLKOUT_EN_BIT, enabled); +} + +// INT_ENABLE register + +/** Get full interrupt enabled status. + * Full register byte for all interrupts, for quick reading. Each bit will be + * set 0 for disabled, 1 for enabled. + * @return Current interrupt enabled status + * @see MPU6050_RA_INT_ENABLE + * @see MPU6050_INTERRUPT_FF_BIT + **/ +uint8_t MPU6050::getIntEnabled() { + I2Cdev::readByte(devAddr, MPU6050_RA_INT_ENABLE, buffer); + return buffer[0]; +} +/** Set full interrupt enabled status. + * Full register byte for all interrupts, for quick reading. Each bit should be + * set 0 for disabled, 1 for enabled. + * @param enabled New interrupt enabled status + * @see getIntFreefallEnabled() + * @see MPU6050_RA_INT_ENABLE + * @see MPU6050_INTERRUPT_FF_BIT + **/ +void MPU6050::setIntEnabled(uint8_t enabled) { + I2Cdev::writeByte(devAddr, MPU6050_RA_INT_ENABLE, enabled); +} +/** Get Free Fall interrupt enabled status. + * Will be set 0 for disabled, 1 for enabled. + * @return Current interrupt enabled status + * @see MPU6050_RA_INT_ENABLE + * @see MPU6050_INTERRUPT_FF_BIT + **/ +bool MPU6050::getIntFreefallEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FF_BIT, buffer); + return buffer[0]; +} +/** Set Free Fall interrupt enabled status. + * @param enabled New interrupt enabled status + * @see getIntFreefallEnabled() + * @see MPU6050_RA_INT_ENABLE + * @see MPU6050_INTERRUPT_FF_BIT + **/ +void MPU6050::setIntFreefallEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FF_BIT, enabled); +} +/** Get Motion Detection interrupt enabled status. + * Will be set 0 for disabled, 1 for enabled. + * @return Current interrupt enabled status + * @see MPU6050_RA_INT_ENABLE + * @see MPU6050_INTERRUPT_MOT_BIT + **/ +bool MPU6050::getIntMotionEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_MOT_BIT, buffer); + return buffer[0]; +} +/** Set Motion Detection interrupt enabled status. + * @param enabled New interrupt enabled status + * @see getIntMotionEnabled() + * @see MPU6050_RA_INT_ENABLE + * @see MPU6050_INTERRUPT_MOT_BIT + **/ +void MPU6050::setIntMotionEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_MOT_BIT, enabled); +} +/** Get Zero Motion Detection interrupt enabled status. + * Will be set 0 for disabled, 1 for enabled. + * @return Current interrupt enabled status + * @see MPU6050_RA_INT_ENABLE + * @see MPU6050_INTERRUPT_ZMOT_BIT + **/ +bool MPU6050::getIntZeroMotionEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_ZMOT_BIT, buffer); + return buffer[0]; +} +/** Set Zero Motion Detection interrupt enabled status. + * @param enabled New interrupt enabled status + * @see getIntZeroMotionEnabled() + * @see MPU6050_RA_INT_ENABLE + * @see MPU6050_INTERRUPT_ZMOT_BIT + **/ +void MPU6050::setIntZeroMotionEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_ZMOT_BIT, enabled); +} +/** Get FIFO Buffer Overflow interrupt enabled status. + * Will be set 0 for disabled, 1 for enabled. + * @return Current interrupt enabled status + * @see MPU6050_RA_INT_ENABLE + * @see MPU6050_INTERRUPT_FIFO_OFLOW_BIT + **/ +bool MPU6050::getIntFIFOBufferOverflowEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FIFO_OFLOW_BIT, buffer); + return buffer[0]; +} +/** Set FIFO Buffer Overflow interrupt enabled status. + * @param enabled New interrupt enabled status + * @see getIntFIFOBufferOverflowEnabled() + * @see MPU6050_RA_INT_ENABLE + * @see MPU6050_INTERRUPT_FIFO_OFLOW_BIT + **/ +void MPU6050::setIntFIFOBufferOverflowEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FIFO_OFLOW_BIT, enabled); +} +/** Get I2C Master interrupt enabled status. + * This enables any of the I2C Master interrupt sources to generate an + * interrupt. Will be set 0 for disabled, 1 for enabled. + * @return Current interrupt enabled status + * @see MPU6050_RA_INT_ENABLE + * @see MPU6050_INTERRUPT_I2C_MST_INT_BIT + **/ +bool MPU6050::getIntI2CMasterEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_I2C_MST_INT_BIT, buffer); + return buffer[0]; +} +/** Set I2C Master interrupt enabled status. + * @param enabled New interrupt enabled status + * @see getIntI2CMasterEnabled() + * @see MPU6050_RA_INT_ENABLE + * @see MPU6050_INTERRUPT_I2C_MST_INT_BIT + **/ +void MPU6050::setIntI2CMasterEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_I2C_MST_INT_BIT, enabled); +} +/** Get Data Ready interrupt enabled setting. + * This event occurs each time a write operation to all of the sensor registers + * has been completed. Will be set 0 for disabled, 1 for enabled. + * @return Current interrupt enabled status + * @see MPU6050_RA_INT_ENABLE + * @see MPU6050_INTERRUPT_DATA_RDY_BIT + */ +bool MPU6050::getIntDataReadyEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DATA_RDY_BIT, buffer); + return buffer[0]; +} +/** Set Data Ready interrupt enabled status. + * @param enabled New interrupt enabled status + * @see getIntDataReadyEnabled() + * @see MPU6050_RA_INT_CFG + * @see MPU6050_INTERRUPT_DATA_RDY_BIT + */ +void MPU6050::setIntDataReadyEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DATA_RDY_BIT, enabled); +} + +// INT_STATUS register + +/** Get full set of interrupt status bits. + * These bits clear to 0 after the register has been read. Very useful + * for getting multiple INT statuses, since each single bit read clears + * all of them because it has to read the whole byte. + * @return Current interrupt status + * @see MPU6050_RA_INT_STATUS + */ +uint8_t MPU6050::getIntStatus() { + I2Cdev::readByte(devAddr, MPU6050_RA_INT_STATUS, buffer); + return buffer[0]; +} +/** Get Free Fall interrupt status. + * This bit automatically sets to 1 when a Free Fall interrupt has been + * generated. The bit clears to 0 after the register has been read. + * @return Current interrupt status + * @see MPU6050_RA_INT_STATUS + * @see MPU6050_INTERRUPT_FF_BIT + */ +bool MPU6050::getIntFreefallStatus() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_FF_BIT, buffer); + return buffer[0]; +} +/** Get Motion Detection interrupt status. + * This bit automatically sets to 1 when a Motion Detection interrupt has been + * generated. The bit clears to 0 after the register has been read. + * @return Current interrupt status + * @see MPU6050_RA_INT_STATUS + * @see MPU6050_INTERRUPT_MOT_BIT + */ +bool MPU6050::getIntMotionStatus() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_MOT_BIT, buffer); + return buffer[0]; +} +/** Get Zero Motion Detection interrupt status. + * This bit automatically sets to 1 when a Zero Motion Detection interrupt has + * been generated. The bit clears to 0 after the register has been read. + * @return Current interrupt status + * @see MPU6050_RA_INT_STATUS + * @see MPU6050_INTERRUPT_ZMOT_BIT + */ +bool MPU6050::getIntZeroMotionStatus() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_ZMOT_BIT, buffer); + return buffer[0]; +} +/** Get FIFO Buffer Overflow interrupt status. + * This bit automatically sets to 1 when a Free Fall interrupt has been + * generated. The bit clears to 0 after the register has been read. + * @return Current interrupt status + * @see MPU6050_RA_INT_STATUS + * @see MPU6050_INTERRUPT_FIFO_OFLOW_BIT + */ +bool MPU6050::getIntFIFOBufferOverflowStatus() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_FIFO_OFLOW_BIT, buffer); + return buffer[0]; +} +/** Get I2C Master interrupt status. + * This bit automatically sets to 1 when an I2C Master interrupt has been + * generated. For a list of I2C Master interrupts, please refer to Register 54. + * The bit clears to 0 after the register has been read. + * @return Current interrupt status + * @see MPU6050_RA_INT_STATUS + * @see MPU6050_INTERRUPT_I2C_MST_INT_BIT + */ +bool MPU6050::getIntI2CMasterStatus() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_I2C_MST_INT_BIT, buffer); + return buffer[0]; +} +/** Get Data Ready interrupt status. + * This bit automatically sets to 1 when a Data Ready interrupt has been + * generated. The bit clears to 0 after the register has been read. + * @return Current interrupt status + * @see MPU6050_RA_INT_STATUS + * @see MPU6050_INTERRUPT_DATA_RDY_BIT + */ +bool MPU6050::getIntDataReadyStatus() { + I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_DATA_RDY_BIT, buffer); + return buffer[0]; +} + +// ACCEL_*OUT_* registers + +/** Get raw 9-axis motion sensor readings (accel/gyro/compass). + * FUNCTION NOT FULLY IMPLEMENTED YET. + * @param ax 16-bit signed integer container for accelerometer X-axis value + * @param ay 16-bit signed integer container for accelerometer Y-axis value + * @param az 16-bit signed integer container for accelerometer Z-axis value + * @param gx 16-bit signed integer container for gyroscope X-axis value + * @param gy 16-bit signed integer container for gyroscope Y-axis value + * @param gz 16-bit signed integer container for gyroscope Z-axis value + * @param mx 16-bit signed integer container for magnetometer X-axis value + * @param my 16-bit signed integer container for magnetometer Y-axis value + * @param mz 16-bit signed integer container for magnetometer Z-axis value + * @see getMotion6() + * @see getAcceleration() + * @see getRotation() + * @see MPU6050_RA_ACCEL_XOUT_H + */ +void MPU6050::getMotion9(int16_t* ax, int16_t* ay, int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz, int16_t* mx, int16_t* my, int16_t* mz) { + getMotion6(ax, ay, az, gx, gy, gz); + // TODO: magnetometer integration +} +/** Get raw 6-axis motion sensor readings (accel/gyro). + * Retrieves all currently available motion sensor values. + * @param ax 16-bit signed integer container for accelerometer X-axis value + * @param ay 16-bit signed integer container for accelerometer Y-axis value + * @param az 16-bit signed integer container for accelerometer Z-axis value + * @param gx 16-bit signed integer container for gyroscope X-axis value + * @param gy 16-bit signed integer container for gyroscope Y-axis value + * @param gz 16-bit signed integer container for gyroscope Z-axis value + * @see getAcceleration() + * @see getRotation() + * @see MPU6050_RA_ACCEL_XOUT_H + */ +void MPU6050::getMotion6(int16_t* ax, int16_t* ay, int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz) { + I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_XOUT_H, 14, buffer); + *ax = (((int16_t)buffer[0]) << 8) | buffer[1]; + *ay = (((int16_t)buffer[2]) << 8) | buffer[3]; + *az = (((int16_t)buffer[4]) << 8) | buffer[5]; + *gx = (((int16_t)buffer[8]) << 8) | buffer[9]; + *gy = (((int16_t)buffer[10]) << 8) | buffer[11]; + *gz = (((int16_t)buffer[12]) << 8) | buffer[13]; +} +/** Get 3-axis accelerometer readings. + * These registers store the most recent accelerometer measurements. + * Accelerometer measurements are written to these registers at the Sample Rate + * as defined in Register 25. + * + * The accelerometer measurement registers, along with the temperature + * measurement registers, gyroscope measurement registers, and external sensor + * data registers, are composed of two sets of registers: an internal register + * set and a user-facing read register set. + * + * The data within the accelerometer sensors' internal register set is always + * updated at the Sample Rate. Meanwhile, the user-facing read register set + * duplicates the internal register set's data values whenever the serial + * interface is idle. This guarantees that a burst read of sensor registers will + * read measurements from the same sampling instant. Note that if burst reads + * are not used, the user is responsible for ensuring a set of single byte reads + * correspond to a single sampling instant by checking the Data Ready interrupt. + * + * Each 16-bit accelerometer measurement has a full scale defined in ACCEL_FS + * (Register 28). For each full scale setting, the accelerometers' sensitivity + * per LSB in ACCEL_xOUT is shown in the table below: + * + * 
+ * AFS_SEL | Full Scale Range | LSB Sensitivity
+ * --------+------------------+----------------
+ * 0       | +/- 2g           | 8192 LSB/mg
+ * 1       | +/- 4g           | 4096 LSB/mg
+ * 2       | +/- 8g           | 2048 LSB/mg
+ * 3       | +/- 16g          | 1024 LSB/mg
+ *
+ * + * @param x 16-bit signed integer container for X-axis acceleration + * @param y 16-bit signed integer container for Y-axis acceleration + * @param z 16-bit signed integer container for Z-axis acceleration + * @see MPU6050_RA_GYRO_XOUT_H + */ +void MPU6050::getAcceleration(int16_t* x, int16_t* y, int16_t* z) { + I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_XOUT_H, 6, buffer); + *x = (((int16_t)buffer[0]) << 8) | buffer[1]; + *y = (((int16_t)buffer[2]) << 8) | buffer[3]; + *z = (((int16_t)buffer[4]) << 8) | buffer[5]; +} +/** Get X-axis accelerometer reading. + * @return X-axis acceleration measurement in 16-bit 2's complement format + * @see getMotion6() + * @see MPU6050_RA_ACCEL_XOUT_H + */ +int16_t MPU6050::getAccelerationX() { + I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_XOUT_H, 2, buffer); + return (((int16_t)buffer[0]) << 8) | buffer[1]; +} +/** Get Y-axis accelerometer reading. + * @return Y-axis acceleration measurement in 16-bit 2's complement format + * @see getMotion6() + * @see MPU6050_RA_ACCEL_YOUT_H + */ +int16_t MPU6050::getAccelerationY() { + I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_YOUT_H, 2, buffer); + return (((int16_t)buffer[0]) << 8) | buffer[1]; +} +/** Get Z-axis accelerometer reading. + * @return Z-axis acceleration measurement in 16-bit 2's complement format + * @see getMotion6() + * @see MPU6050_RA_ACCEL_ZOUT_H + */ +int16_t MPU6050::getAccelerationZ() { + I2Cdev::readBytes(devAddr, MPU6050_RA_ACCEL_ZOUT_H, 2, buffer); + return (((int16_t)buffer[0]) << 8) | buffer[1]; +} + +// TEMP_OUT_* registers + +/** Get current internal temperature. + * @return Temperature reading in 16-bit 2's complement format + * @see MPU6050_RA_TEMP_OUT_H + */ +int16_t MPU6050::getTemperature() { + I2Cdev::readBytes(devAddr, MPU6050_RA_TEMP_OUT_H, 2, buffer); + return (((int16_t)buffer[0]) << 8) | buffer[1]; +} + +// GYRO_*OUT_* registers + +/** Get 3-axis gyroscope readings. + * These gyroscope measurement registers, along with the accelerometer + * measurement registers, temperature measurement registers, and external sensor + * data registers, are composed of two sets of registers: an internal register + * set and a user-facing read register set. + * The data within the gyroscope sensors' internal register set is always + * updated at the Sample Rate. Meanwhile, the user-facing read register set + * duplicates the internal register set's data values whenever the serial + * interface is idle. This guarantees that a burst read of sensor registers will + * read measurements from the same sampling instant. Note that if burst reads + * are not used, the user is responsible for ensuring a set of single byte reads + * correspond to a single sampling instant by checking the Data Ready interrupt. + * + * Each 16-bit gyroscope measurement has a full scale defined in FS_SEL + * (Register 27). For each full scale setting, the gyroscopes' sensitivity per + * LSB in GYRO_xOUT is shown in the table below: + * + * 
+ * FS_SEL | Full Scale Range   | LSB Sensitivity
+ * -------+--------------------+----------------
+ * 0      | +/- 250 degrees/s  | 131 LSB/deg/s
+ * 1      | +/- 500 degrees/s  | 65.5 LSB/deg/s
+ * 2      | +/- 1000 degrees/s | 32.8 LSB/deg/s
+ * 3      | +/- 2000 degrees/s | 16.4 LSB/deg/s
+ *
+ * + * @param x 16-bit signed integer container for X-axis rotation + * @param y 16-bit signed integer container for Y-axis rotation + * @param z 16-bit signed integer container for Z-axis rotation + * @see getMotion6() + * @see MPU6050_RA_GYRO_XOUT_H + */ +void MPU6050::getRotation(int16_t* x, int16_t* y, int16_t* z) { + I2Cdev::readBytes(devAddr, MPU6050_RA_GYRO_XOUT_H, 6, buffer); + *x = (((int16_t)buffer[0]) << 8) | buffer[1]; + *y = (((int16_t)buffer[2]) << 8) | buffer[3]; + *z = (((int16_t)buffer[4]) << 8) | buffer[5]; +} +/** Get X-axis gyroscope reading. + * @return X-axis rotation measurement in 16-bit 2's complement format + * @see getMotion6() + * @see MPU6050_RA_GYRO_XOUT_H + */ +int16_t MPU6050::getRotationX() { + I2Cdev::readBytes(devAddr, MPU6050_RA_GYRO_XOUT_H, 2, buffer); + return (((int16_t)buffer[0]) << 8) | buffer[1]; +} +/** Get Y-axis gyroscope reading. + * @return Y-axis rotation measurement in 16-bit 2's complement format + * @see getMotion6() + * @see MPU6050_RA_GYRO_YOUT_H + */ +int16_t MPU6050::getRotationY() { + I2Cdev::readBytes(devAddr, MPU6050_RA_GYRO_YOUT_H, 2, buffer); + return (((int16_t)buffer[0]) << 8) | buffer[1]; +} +/** Get Z-axis gyroscope reading. + * @return Z-axis rotation measurement in 16-bit 2's complement format + * @see getMotion6() + * @see MPU6050_RA_GYRO_ZOUT_H + */ +int16_t MPU6050::getRotationZ() { + I2Cdev::readBytes(devAddr, MPU6050_RA_GYRO_ZOUT_H, 2, buffer); + return (((int16_t)buffer[0]) << 8) | buffer[1]; +} + +// EXT_SENS_DATA_* registers + +/** Read single byte from external sensor data register. + * These registers store data read from external sensors by the Slave 0, 1, 2, + * and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in + * I2C_SLV4_DI (Register 53). + * + * External sensor data is written to these registers at the Sample Rate as + * defined in Register 25. This access rate can be reduced by using the Slave + * Delay Enable registers (Register 103). + * + * External sensor data registers, along with the gyroscope measurement + * registers, accelerometer measurement registers, and temperature measurement + * registers, are composed of two sets of registers: an internal register set + * and a user-facing read register set. + * + * The data within the external sensors' internal register set is always updated + * at the Sample Rate (or the reduced access rate) whenever the serial interface + * is idle. This guarantees that a burst read of sensor registers will read + * measurements from the same sampling instant. Note that if burst reads are not + * used, the user is responsible for ensuring a set of single byte reads + * correspond to a single sampling instant by checking the Data Ready interrupt. + * + * Data is placed in these external sensor data registers according to + * I2C_SLV0_CTRL, I2C_SLV1_CTRL, I2C_SLV2_CTRL, and I2C_SLV3_CTRL (Registers 39, + * 42, 45, and 48). When more than zero bytes are read (I2C_SLVx_LEN > 0) from + * an enabled slave (I2C_SLVx_EN = 1), the slave is read at the Sample Rate (as + * defined in Register 25) or delayed rate (if specified in Register 52 and + * 103). During each Sample cycle, slave reads are performed in order of Slave + * number. If all slaves are enabled with more than zero bytes to be read, the + * order will be Slave 0, followed by Slave 1, Slave 2, and Slave 3. + * + * Each enabled slave will have EXT_SENS_DATA registers associated with it by + * number of bytes read (I2C_SLVx_LEN) in order of slave number, starting from + * EXT_SENS_DATA_00. Note that this means enabling or disabling a slave may + * change the higher numbered slaves' associated registers. Furthermore, if + * fewer total bytes are being read from the external sensors as a result of + * such a change, then the data remaining in the registers which no longer have + * an associated slave device (i.e. high numbered registers) will remain in + * these previously allocated registers unless reset. + * + * If the sum of the read lengths of all SLVx transactions exceed the number of + * available EXT_SENS_DATA registers, the excess bytes will be dropped. There + * are 24 EXT_SENS_DATA registers and hence the total read lengths between all + * the slaves cannot be greater than 24 or some bytes will be lost. + * + * Note: Slave 4's behavior is distinct from that of Slaves 0-3. For further + * information regarding the characteristics of Slave 4, please refer to + * Registers 49 to 53. + * + * EXAMPLE: + * Suppose that Slave 0 is enabled with 4 bytes to be read (I2C_SLV0_EN = 1 and + * I2C_SLV0_LEN = 4) while Slave 1 is enabled with 2 bytes to be read so that + * I2C_SLV1_EN = 1 and I2C_SLV1_LEN = 2. In such a situation, EXT_SENS_DATA _00 + * through _03 will be associated with Slave 0, while EXT_SENS_DATA _04 and 05 + * will be associated with Slave 1. If Slave 2 is enabled as well, registers + * starting from EXT_SENS_DATA_06 will be allocated to Slave 2. + * + * If Slave 2 is disabled while Slave 3 is enabled in this same situation, then + * registers starting from EXT_SENS_DATA_06 will be allocated to Slave 3 + * instead. + * + * REGISTER ALLOCATION FOR DYNAMIC DISABLE VS. NORMAL DISABLE: + * If a slave is disabled at any time, the space initially allocated to the + * slave in the EXT_SENS_DATA register, will remain associated with that slave. + * This is to avoid dynamic adjustment of the register allocation. + * + * The allocation of the EXT_SENS_DATA registers is recomputed only when (1) all + * slaves are disabled, or (2) the I2C_MST_RST bit is set (Register 106). + * + * This above is also true if one of the slaves gets NACKed and stops + * functioning. + * + * @param position Starting position (0-23) + * @return Byte read from register + */ +uint8_t MPU6050::getExternalSensorByte(int position) { + I2Cdev::readByte(devAddr, MPU6050_RA_EXT_SENS_DATA_00 + position, buffer); + return buffer[0]; +} +/** Read word (2 bytes) from external sensor data registers. + * @param position Starting position (0-21) + * @return Word read from register + * @see getExternalSensorByte() + */ +uint16_t MPU6050::getExternalSensorWord(int position) { + I2Cdev::readBytes(devAddr, MPU6050_RA_EXT_SENS_DATA_00 + position, 2, buffer); + return (((uint16_t)buffer[0]) << 8) | buffer[1]; +} +/** Read double word (4 bytes) from external sensor data registers. + * @param position Starting position (0-20) + * @return Double word read from registers + * @see getExternalSensorByte() + */ +uint32_t MPU6050::getExternalSensorDWord(int position) { + I2Cdev::readBytes(devAddr, MPU6050_RA_EXT_SENS_DATA_00 + position, 4, buffer); + return (((uint32_t)buffer[0]) << 24) | (((uint32_t)buffer[1]) << 16) | (((uint16_t)buffer[2]) << 8) | buffer[3]; +} + +// MOT_DETECT_STATUS register + +/** Get X-axis negative motion detection interrupt status. + * @return Motion detection status + * @see MPU6050_RA_MOT_DETECT_STATUS + * @see MPU6050_MOTION_MOT_XNEG_BIT + */ +bool MPU6050::getXNegMotionDetected() { + I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_XNEG_BIT, buffer); + return buffer[0]; +} +/** Get X-axis positive motion detection interrupt status. + * @return Motion detection status + * @see MPU6050_RA_MOT_DETECT_STATUS + * @see MPU6050_MOTION_MOT_XPOS_BIT + */ +bool MPU6050::getXPosMotionDetected() { + I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_XPOS_BIT, buffer); + return buffer[0]; +} +/** Get Y-axis negative motion detection interrupt status. + * @return Motion detection status + * @see MPU6050_RA_MOT_DETECT_STATUS + * @see MPU6050_MOTION_MOT_YNEG_BIT + */ +bool MPU6050::getYNegMotionDetected() { + I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_YNEG_BIT, buffer); + return buffer[0]; +} +/** Get Y-axis positive motion detection interrupt status. + * @return Motion detection status + * @see MPU6050_RA_MOT_DETECT_STATUS + * @see MPU6050_MOTION_MOT_YPOS_BIT + */ +bool MPU6050::getYPosMotionDetected() { + I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_YPOS_BIT, buffer); + return buffer[0]; +} +/** Get Z-axis negative motion detection interrupt status. + * @return Motion detection status + * @see MPU6050_RA_MOT_DETECT_STATUS + * @see MPU6050_MOTION_MOT_ZNEG_BIT + */ +bool MPU6050::getZNegMotionDetected() { + I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_ZNEG_BIT, buffer); + return buffer[0]; +} +/** Get Z-axis positive motion detection interrupt status. + * @return Motion detection status + * @see MPU6050_RA_MOT_DETECT_STATUS + * @see MPU6050_MOTION_MOT_ZPOS_BIT + */ +bool MPU6050::getZPosMotionDetected() { + I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_ZPOS_BIT, buffer); + return buffer[0]; +} +/** Get zero motion detection interrupt status. + * @return Motion detection status + * @see MPU6050_RA_MOT_DETECT_STATUS + * @see MPU6050_MOTION_MOT_ZRMOT_BIT + */ +bool MPU6050::getZeroMotionDetected() { + I2Cdev::readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_ZRMOT_BIT, buffer); + return buffer[0]; +} + +// I2C_SLV*_DO register + +/** Write byte to Data Output container for specified slave. + * This register holds the output data written into Slave when Slave is set to + * write mode. For further information regarding Slave control, please + * refer to Registers 37 to 39 and immediately following. + * @param num Slave number (0-3) + * @param data Byte to write + * @see MPU6050_RA_I2C_SLV0_DO + */ +void MPU6050::setSlaveOutputByte(uint8_t num, uint8_t data) { + if (num > 3) return; + I2Cdev::writeByte(devAddr, MPU6050_RA_I2C_SLV0_DO + num, data); +} + +// I2C_MST_DELAY_CTRL register + +/** Get external data shadow delay enabled status. + * This register is used to specify the timing of external sensor data + * shadowing. When DELAY_ES_SHADOW is set to 1, shadowing of external + * sensor data is delayed until all data has been received. + * @return Current external data shadow delay enabled status. + * @see MPU6050_RA_I2C_MST_DELAY_CTRL + * @see MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT + */ +bool MPU6050::getExternalShadowDelayEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT, buffer); + return buffer[0]; +} +/** Set external data shadow delay enabled status. + * @param enabled New external data shadow delay enabled status. + * @see getExternalShadowDelayEnabled() + * @see MPU6050_RA_I2C_MST_DELAY_CTRL + * @see MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT + */ +void MPU6050::setExternalShadowDelayEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT, enabled); +} +/** Get slave delay enabled status. + * When a particular slave delay is enabled, the rate of access for the that + * slave device is reduced. When a slave's access rate is decreased relative to + * the Sample Rate, the slave is accessed every: + * + * 1 / (1 + I2C_MST_DLY) Samples + * + * This base Sample Rate in turn is determined by SMPLRT_DIV (register * 25) + * and DLPF_CFG (register 26). + * + * For further information regarding I2C_MST_DLY, please refer to register 52. + * For further information regarding the Sample Rate, please refer to register 25. + * + * @param num Slave number (0-4) + * @return Current slave delay enabled status. + * @see MPU6050_RA_I2C_MST_DELAY_CTRL + * @see MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT + */ +bool MPU6050::getSlaveDelayEnabled(uint8_t num) { + // MPU6050_DELAYCTRL_I2C_SLV4_DLY_EN_BIT is 4, SLV3 is 3, etc. + if (num > 4) return 0; + I2Cdev::readBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, num, buffer); + return buffer[0]; +} +/** Set slave delay enabled status. + * @param num Slave number (0-4) + * @param enabled New slave delay enabled status. + * @see MPU6050_RA_I2C_MST_DELAY_CTRL + * @see MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT + */ +void MPU6050::setSlaveDelayEnabled(uint8_t num, bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, num, enabled); +} + +// SIGNAL_PATH_RESET register + +/** Reset gyroscope signal path. + * The reset will revert the signal path analog to digital converters and + * filters to their power up configurations. + * @see MPU6050_RA_SIGNAL_PATH_RESET + * @see MPU6050_PATHRESET_GYRO_RESET_BIT + */ +void MPU6050::resetGyroscopePath() { + I2Cdev::writeBit(devAddr, MPU6050_RA_SIGNAL_PATH_RESET, MPU6050_PATHRESET_GYRO_RESET_BIT, true); +} +/** Reset accelerometer signal path. + * The reset will revert the signal path analog to digital converters and + * filters to their power up configurations. + * @see MPU6050_RA_SIGNAL_PATH_RESET + * @see MPU6050_PATHRESET_ACCEL_RESET_BIT + */ +void MPU6050::resetAccelerometerPath() { + I2Cdev::writeBit(devAddr, MPU6050_RA_SIGNAL_PATH_RESET, MPU6050_PATHRESET_ACCEL_RESET_BIT, true); +} +/** Reset temperature sensor signal path. + * The reset will revert the signal path analog to digital converters and + * filters to their power up configurations. + * @see MPU6050_RA_SIGNAL_PATH_RESET + * @see MPU6050_PATHRESET_TEMP_RESET_BIT + */ +void MPU6050::resetTemperaturePath() { + I2Cdev::writeBit(devAddr, MPU6050_RA_SIGNAL_PATH_RESET, MPU6050_PATHRESET_TEMP_RESET_BIT, true); +} + +// MOT_DETECT_CTRL register + +/** Get accelerometer power-on delay. + * The accelerometer data path provides samples to the sensor registers, Motion + * detection, Zero Motion detection, and Free Fall detection modules. The + * signal path contains filters which must be flushed on wake-up with new + * samples before the detection modules begin operations. The default wake-up + * delay, of 4ms can be lengthened by up to 3ms. This additional delay is + * specified in ACCEL_ON_DELAY in units of 1 LSB = 1 ms. The user may select + * any value above zero unless instructed otherwise by InvenSense. Please refer + * to Section 8 of the MPU-6000/MPU-6050 Product Specification document for + * further information regarding the detection modules. + * @return Current accelerometer power-on delay + * @see MPU6050_RA_MOT_DETECT_CTRL + * @see MPU6050_DETECT_ACCEL_ON_DELAY_BIT + */ +uint8_t MPU6050::getAccelerometerPowerOnDelay() { + I2Cdev::readBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_ACCEL_ON_DELAY_BIT, MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH, buffer); + return buffer[0]; +} +/** Set accelerometer power-on delay. + * @param delay New accelerometer power-on delay (0-3) + * @see getAccelerometerPowerOnDelay() + * @see MPU6050_RA_MOT_DETECT_CTRL + * @see MPU6050_DETECT_ACCEL_ON_DELAY_BIT + */ +void MPU6050::setAccelerometerPowerOnDelay(uint8_t delay) { + I2Cdev::writeBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_ACCEL_ON_DELAY_BIT, MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH, delay); +} +/** Get Free Fall detection counter decrement configuration. + * Detection is registered by the Free Fall detection module after accelerometer + * measurements meet their respective threshold conditions over a specified + * number of samples. When the threshold conditions are met, the corresponding + * detection counter increments by 1. The user may control the rate at which the + * detection counter decrements when the threshold condition is not met by + * configuring FF_COUNT. The decrement rate can be set according to the + * following table: + * + * 
+ * FF_COUNT | Counter Decrement
+ * ---------+------------------
+ * 0        | Reset
+ * 1        | 1
+ * 2        | 2
+ * 3        | 4
+ *
+ * + * When FF_COUNT is configured to 0 (reset), any non-qualifying sample will + * reset the counter to 0. For further information on Free Fall detection, + * please refer to Registers 29 to 32. + * + * @return Current decrement configuration + * @see MPU6050_RA_MOT_DETECT_CTRL + * @see MPU6050_DETECT_FF_COUNT_BIT + */ +uint8_t MPU6050::getFreefallDetectionCounterDecrement() { + I2Cdev::readBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_FF_COUNT_BIT, MPU6050_DETECT_FF_COUNT_LENGTH, buffer); + return buffer[0]; +} +/** Set Free Fall detection counter decrement configuration. + * @param decrement New decrement configuration value + * @see getFreefallDetectionCounterDecrement() + * @see MPU6050_RA_MOT_DETECT_CTRL + * @see MPU6050_DETECT_FF_COUNT_BIT + */ +void MPU6050::setFreefallDetectionCounterDecrement(uint8_t decrement) { + I2Cdev::writeBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_FF_COUNT_BIT, MPU6050_DETECT_FF_COUNT_LENGTH, decrement); +} +/** Get Motion detection counter decrement configuration. + * Detection is registered by the Motion detection module after accelerometer + * measurements meet their respective threshold conditions over a specified + * number of samples. When the threshold conditions are met, the corresponding + * detection counter increments by 1. The user may control the rate at which the + * detection counter decrements when the threshold condition is not met by + * configuring MOT_COUNT. The decrement rate can be set according to the + * following table: + * + * 
+ * MOT_COUNT | Counter Decrement
+ * ----------+------------------
+ * 0         | Reset
+ * 1         | 1
+ * 2         | 2
+ * 3         | 4
+ *
+ * + * When MOT_COUNT is configured to 0 (reset), any non-qualifying sample will + * reset the counter to 0. For further information on Motion detection, + * please refer to Registers 29 to 32. + * + */ +uint8_t MPU6050::getMotionDetectionCounterDecrement() { + I2Cdev::readBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_MOT_COUNT_BIT, MPU6050_DETECT_MOT_COUNT_LENGTH, buffer); + return buffer[0]; +} +/** Set Motion detection counter decrement configuration. + * @param decrement New decrement configuration value + * @see getMotionDetectionCounterDecrement() + * @see MPU6050_RA_MOT_DETECT_CTRL + * @see MPU6050_DETECT_MOT_COUNT_BIT + */ +void MPU6050::setMotionDetectionCounterDecrement(uint8_t decrement) { + I2Cdev::writeBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_MOT_COUNT_BIT, MPU6050_DETECT_MOT_COUNT_LENGTH, decrement); +} + +// USER_CTRL register + +/** Get FIFO enabled status. + * When this bit is set to 0, the FIFO buffer is disabled. The FIFO buffer + * cannot be written to or read from while disabled. The FIFO buffer's state + * does not change unless the MPU-60X0 is power cycled. + * @return Current FIFO enabled status + * @see MPU6050_RA_USER_CTRL + * @see MPU6050_USERCTRL_FIFO_EN_BIT + */ +bool MPU6050::getFIFOEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_FIFO_EN_BIT, buffer); + return buffer[0]; +} +/** Set FIFO enabled status. + * @param enabled New FIFO enabled status + * @see getFIFOEnabled() + * @see MPU6050_RA_USER_CTRL + * @see MPU6050_USERCTRL_FIFO_EN_BIT + */ +void MPU6050::setFIFOEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_FIFO_EN_BIT, enabled); +} +/** Get I2C Master Mode enabled status. + * When this mode is enabled, the MPU-60X0 acts as the I2C Master to the + * external sensor slave devices on the auxiliary I2C bus. When this bit is + * cleared to 0, the auxiliary I2C bus lines (AUX_DA and AUX_CL) are logically + * driven by the primary I2C bus (SDA and SCL). This is a precondition to + * enabling Bypass Mode. For further information regarding Bypass Mode, please + * refer to Register 55. + * @return Current I2C Master Mode enabled status + * @see MPU6050_RA_USER_CTRL + * @see MPU6050_USERCTRL_I2C_MST_EN_BIT + */ +bool MPU6050::getI2CMasterModeEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_EN_BIT, buffer); + return buffer[0]; +} +/** Set I2C Master Mode enabled status. + * @param enabled New I2C Master Mode enabled status + * @see getI2CMasterModeEnabled() + * @see MPU6050_RA_USER_CTRL + * @see MPU6050_USERCTRL_I2C_MST_EN_BIT + */ +void MPU6050::setI2CMasterModeEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_EN_BIT, enabled); +} +/** Switch from I2C to SPI mode (MPU-6000 only) + * If this is set, the primary SPI interface will be enabled in place of the + * disabled primary I2C interface. + */ +void MPU6050::switchSPIEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_IF_DIS_BIT, enabled); +} +/** Reset the FIFO. + * This bit resets the FIFO buffer when set to 1 while FIFO_EN equals 0. This + * bit automatically clears to 0 after the reset has been triggered. + * @see MPU6050_RA_USER_CTRL + * @see MPU6050_USERCTRL_FIFO_RESET_BIT + */ +void MPU6050::resetFIFO() { + I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_FIFO_RESET_BIT, true); +} +/** Reset the I2C Master. + * This bit resets the I2C Master when set to 1 while I2C_MST_EN equals 0. + * This bit automatically clears to 0 after the reset has been triggered. + * @see MPU6050_RA_USER_CTRL + * @see MPU6050_USERCTRL_I2C_MST_RESET_BIT + */ +void MPU6050::resetI2CMaster() { + I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_RESET_BIT, true); +} +/** Reset all sensor registers and signal paths. + * When set to 1, this bit resets the signal paths for all sensors (gyroscopes, + * accelerometers, and temperature sensor). This operation will also clear the + * sensor registers. This bit automatically clears to 0 after the reset has been + * triggered. + * + * When resetting only the signal path (and not the sensor registers), please + * use Register 104, SIGNAL_PATH_RESET. + * + * @see MPU6050_RA_USER_CTRL + * @see MPU6050_USERCTRL_SIG_COND_RESET_BIT + */ +void MPU6050::resetSensors() { + I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_SIG_COND_RESET_BIT, true); +} + +// PWR_MGMT_1 register + +/** Trigger a full device reset. + * A small delay of ~50ms may be desirable after triggering a reset. + * @see MPU6050_RA_PWR_MGMT_1 + * @see MPU6050_PWR1_DEVICE_RESET_BIT + */ +void MPU6050::reset() { + I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_DEVICE_RESET_BIT, true); +} +/** Get sleep mode status. + * Setting the SLEEP bit in the register puts the device into very low power + * sleep mode. In this mode, only the serial interface and internal registers + * remain active, allowing for a very low standby current. Clearing this bit + * puts the device back into normal mode. To save power, the individual standby + * selections for each of the gyros should be used if any gyro axis is not used + * by the application. + * @return Current sleep mode enabled status + * @see MPU6050_RA_PWR_MGMT_1 + * @see MPU6050_PWR1_SLEEP_BIT + */ +bool MPU6050::getSleepEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_SLEEP_BIT, buffer); + return buffer[0]; +} +/** Set sleep mode status. + * @param enabled New sleep mode enabled status + * @see getSleepEnabled() + * @see MPU6050_RA_PWR_MGMT_1 + * @see MPU6050_PWR1_SLEEP_BIT + */ +void MPU6050::setSleepEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_SLEEP_BIT, enabled); +} +/** Get wake cycle enabled status. + * When this bit is set to 1 and SLEEP is disabled, the MPU-60X0 will cycle + * between sleep mode and waking up to take a single sample of data from active + * sensors at a rate determined by LP_WAKE_CTRL (register 108). + * @return Current sleep mode enabled status + * @see MPU6050_RA_PWR_MGMT_1 + * @see MPU6050_PWR1_CYCLE_BIT + */ +bool MPU6050::getWakeCycleEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CYCLE_BIT, buffer); + return buffer[0]; +} +/** Set wake cycle enabled status. + * @param enabled New sleep mode enabled status + * @see getWakeCycleEnabled() + * @see MPU6050_RA_PWR_MGMT_1 + * @see MPU6050_PWR1_CYCLE_BIT + */ +void MPU6050::setWakeCycleEnabled(bool enabled) { + I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CYCLE_BIT, enabled); +} +/** Get temperature sensor enabled status. + * Control the usage of the internal temperature sensor. + * + * Note: this register stores the *disabled* value, but for consistency with the + * rest of the code, the function is named and used with standard true/false + * values to indicate whether the sensor is enabled or disabled, respectively. + * + * @return Current temperature sensor enabled status + * @see MPU6050_RA_PWR_MGMT_1 + * @see MPU6050_PWR1_TEMP_DIS_BIT + */ +bool MPU6050::getTempSensorEnabled() { + I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_TEMP_DIS_BIT, buffer); + return buffer[0] == 0; // 1 is actually disabled here +} +/** Set temperature sensor enabled status. + * Note: this register stores the *disabled* value, but for consistency with the + * rest of the code, the function is named and used with standard true/false + * values to indicate whether the sensor is enabled or disabled, respectively. + * + * @param enabled New temperature sensor enabled status + * @see getTempSensorEnabled() + * @see MPU6050_RA_PWR_MGMT_1 + * @see MPU6050_PWR1_TEMP_DIS_BIT + */ +void MPU6050::setTempSensorEnabled(bool enabled) { + // 1 is actually disabled here + I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_TEMP_DIS_BIT, !enabled); +} +/** Get clock source setting. + * @return Current clock source setting + * @see MPU6050_RA_PWR_MGMT_1 + * @see MPU6050_PWR1_CLKSEL_BIT + * @see MPU6050_PWR1_CLKSEL_LENGTH + */ +uint8_t MPU6050::getClockSource() { + I2Cdev::readBits(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CLKSEL_BIT, MPU6050_PWR1_CLKSEL_LENGTH, buffer); + return buffer[0]; +} +/** Set clock source setting. + * An internal 8MHz oscillator, gyroscope based clock, or external sources can + * be selected as the MPU-60X0 clock source. When the internal 8 MHz oscillator + * or an external source is chosen as the clock source, the MPU-60X0 can operate + * in low power modes with the gyroscopes disabled. + * + * Upon power up, the MPU-60X0 clock source defaults to the internal oscillator. + * However, it is highly recommended that the device be configured to use one of + * the gyroscopes (or an external clock source) as the clock reference for + * improved stability. The clock source can be selected according to the following table: + * + * 
+ * CLK_SEL | Clock Source
+ * --------+--------------------------------------
+ * 0       | Internal oscillator
+ * 1       | PLL with X Gyro reference
+ * 2       | PLL with Y Gyro reference
+ * 3       | PLL with Z Gyro reference
+ * 4       | PLL with external 32.768kHz reference
+ * 5       | PLL with external 19.2MHz reference
+ * 6       | Reserved
+ * 7       | Stops the clock and keeps the timing generator in reset
+ *
+ * + * @param source New clock source setting + * @see getClockSource() + * @see MPU6050_RA_PWR_MGMT_1 + * @see MPU6050_PWR1_CLKSEL_BIT + * @see MPU6050_PWR1_CLKSEL_LENGTH + */ +void MPU6050::setClockSource(uint8_t source) { + I2Cdev::writeBits(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CLKSEL_BIT, MPU6050_PWR1_CLKSEL_LENGTH, source); +} + +// PWR_MGMT_2 register + +/** Get wake frequency in Accel-Only Low Power Mode. + * The MPU-60X0 can be put into Accerlerometer Only Low Power Mode by setting + * PWRSEL to 1 in the Power Management 1 register (Register 107). In this mode, + * the device will power off all devices except for the primary I2C interface, + * waking only the accelerometer at fixed intervals to take a single + * measurement. The frequency of wake-ups can be configured with LP_WAKE_CTRL + * as shown below: + * + * 
+ * LP_WAKE_CTRL | Wake-up Frequency
+ * -------------+------------------
+ * 0            | 1.25 Hz
+ * 1            | 2.5 Hz
+ * 2            | 5 Hz
+ * 3            | 10 Hz
+ * 
+ *
+ * For further information regarding the MPU-60X0's power modes, please refer to
+ * Register 107.
+ *
+ * @return Current wake frequency
+ * @see MPU6050_RA_PWR_MGMT_2
+ */
+uint8_t MPU6050::getWakeFrequency() {
+    I2Cdev::readBits(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_LP_WAKE_CTRL_BIT, MPU6050_PWR2_LP_WAKE_CTRL_LENGTH, buffer);
+    return buffer[0];
+}
+/** Set wake frequency in Accel-Only Low Power Mode.
+ * @param frequency New wake frequency
+ * @see MPU6050_RA_PWR_MGMT_2
+ */
+void MPU6050::setWakeFrequency(uint8_t frequency) {
+    I2Cdev::writeBits(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_LP_WAKE_CTRL_BIT, MPU6050_PWR2_LP_WAKE_CTRL_LENGTH, frequency);
+}
+
+/** Get X-axis accelerometer standby enabled status.
+ * If enabled, the X-axis will not gather or report data (or use power).
+ * @return Current X-axis standby enabled status
+ * @see MPU6050_RA_PWR_MGMT_2
+ * @see MPU6050_PWR2_STBY_XA_BIT
+ */
+bool MPU6050::getStandbyXAccelEnabled() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XA_BIT, buffer);
+    return buffer[0];
+}
+/** Set X-axis accelerometer standby enabled status.
+ * @param New X-axis standby enabled status
+ * @see getStandbyXAccelEnabled()
+ * @see MPU6050_RA_PWR_MGMT_2
+ * @see MPU6050_PWR2_STBY_XA_BIT
+ */
+void MPU6050::setStandbyXAccelEnabled(bool enabled) {
+    I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XA_BIT, enabled);
+}
+/** Get Y-axis accelerometer standby enabled status.
+ * If enabled, the Y-axis will not gather or report data (or use power).
+ * @return Current Y-axis standby enabled status
+ * @see MPU6050_RA_PWR_MGMT_2
+ * @see MPU6050_PWR2_STBY_YA_BIT
+ */
+bool MPU6050::getStandbyYAccelEnabled() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YA_BIT, buffer);
+    return buffer[0];
+}
+/** Set Y-axis accelerometer standby enabled status.
+ * @param New Y-axis standby enabled status
+ * @see getStandbyYAccelEnabled()
+ * @see MPU6050_RA_PWR_MGMT_2
+ * @see MPU6050_PWR2_STBY_YA_BIT
+ */
+void MPU6050::setStandbyYAccelEnabled(bool enabled) {
+    I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YA_BIT, enabled);
+}
+/** Get Z-axis accelerometer standby enabled status.
+ * If enabled, the Z-axis will not gather or report data (or use power).
+ * @return Current Z-axis standby enabled status
+ * @see MPU6050_RA_PWR_MGMT_2
+ * @see MPU6050_PWR2_STBY_ZA_BIT
+ */
+bool MPU6050::getStandbyZAccelEnabled() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZA_BIT, buffer);
+    return buffer[0];
+}
+/** Set Z-axis accelerometer standby enabled status.
+ * @param New Z-axis standby enabled status
+ * @see getStandbyZAccelEnabled()
+ * @see MPU6050_RA_PWR_MGMT_2
+ * @see MPU6050_PWR2_STBY_ZA_BIT
+ */
+void MPU6050::setStandbyZAccelEnabled(bool enabled) {
+    I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZA_BIT, enabled);
+}
+/** Get X-axis gyroscope standby enabled status.
+ * If enabled, the X-axis will not gather or report data (or use power).
+ * @return Current X-axis standby enabled status
+ * @see MPU6050_RA_PWR_MGMT_2
+ * @see MPU6050_PWR2_STBY_XG_BIT
+ */
+bool MPU6050::getStandbyXGyroEnabled() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XG_BIT, buffer);
+    return buffer[0];
+}
+/** Set X-axis gyroscope standby enabled status.
+ * @param New X-axis standby enabled status
+ * @see getStandbyXGyroEnabled()
+ * @see MPU6050_RA_PWR_MGMT_2
+ * @see MPU6050_PWR2_STBY_XG_BIT
+ */
+void MPU6050::setStandbyXGyroEnabled(bool enabled) {
+    I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XG_BIT, enabled);
+}
+/** Get Y-axis gyroscope standby enabled status.
+ * If enabled, the Y-axis will not gather or report data (or use power).
+ * @return Current Y-axis standby enabled status
+ * @see MPU6050_RA_PWR_MGMT_2
+ * @see MPU6050_PWR2_STBY_YG_BIT
+ */
+bool MPU6050::getStandbyYGyroEnabled() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YG_BIT, buffer);
+    return buffer[0];
+}
+/** Set Y-axis gyroscope standby enabled status.
+ * @param New Y-axis standby enabled status
+ * @see getStandbyYGyroEnabled()
+ * @see MPU6050_RA_PWR_MGMT_2
+ * @see MPU6050_PWR2_STBY_YG_BIT
+ */
+void MPU6050::setStandbyYGyroEnabled(bool enabled) {
+    I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YG_BIT, enabled);
+}
+/** Get Z-axis gyroscope standby enabled status.
+ * If enabled, the Z-axis will not gather or report data (or use power).
+ * @return Current Z-axis standby enabled status
+ * @see MPU6050_RA_PWR_MGMT_2
+ * @see MPU6050_PWR2_STBY_ZG_BIT
+ */
+bool MPU6050::getStandbyZGyroEnabled() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZG_BIT, buffer);
+    return buffer[0];
+}
+/** Set Z-axis gyroscope standby enabled status.
+ * @param New Z-axis standby enabled status
+ * @see getStandbyZGyroEnabled()
+ * @see MPU6050_RA_PWR_MGMT_2
+ * @see MPU6050_PWR2_STBY_ZG_BIT
+ */
+void MPU6050::setStandbyZGyroEnabled(bool enabled) {
+    I2Cdev::writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZG_BIT, enabled);
+}
+
+// FIFO_COUNT* registers
+
+/** Get current FIFO buffer size.
+ * This value indicates the number of bytes stored in the FIFO buffer. This
+ * number is in turn the number of bytes that can be read from the FIFO buffer
+ * and it is directly proportional to the number of samples available given the
+ * set of sensor data bound to be stored in the FIFO (register 35 and 36).
+ * @return Current FIFO buffer size
+ */
+uint16_t MPU6050::getFIFOCount() {
+    I2Cdev::readBytes(devAddr, MPU6050_RA_FIFO_COUNTH, 2, buffer);
+    return (((uint16_t)buffer[0]) << 8) | buffer[1];
+}
+
+// FIFO_R_W register
+
+/** Get byte from FIFO buffer.
+ * This register is used to read and write data from the FIFO buffer. Data is
+ * written to the FIFO in order of register number (from lowest to highest). If
+ * all the FIFO enable flags (see below) are enabled and all External Sensor
+ * Data registers (Registers 73 to 96) are associated with a Slave device, the
+ * contents of registers 59 through 96 will be written in order at the Sample
+ * Rate.
+ *
+ * The contents of the sensor data registers (Registers 59 to 96) are written
+ * into the FIFO buffer when their corresponding FIFO enable flags are set to 1
+ * in FIFO_EN (Register 35). An additional flag for the sensor data registers
+ * associated with I2C Slave 3 can be found in I2C_MST_CTRL (Register 36).
+ *
+ * If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is
+ * automatically set to 1. This bit is located in INT_STATUS (Register 58).
+ * When the FIFO buffer has overflowed, the oldest data will be lost and new
+ * data will be written to the FIFO.
+ *
+ * If the FIFO buffer is empty, reading this register will return the last byte
+ * that was previously read from the FIFO until new data is available. The user
+ * should check FIFO_COUNT to ensure that the FIFO buffer is not read when
+ * empty.
+ *
+ * @return Byte from FIFO buffer
+ */
+uint8_t MPU6050::getFIFOByte() {
+    I2Cdev::readByte(devAddr, MPU6050_RA_FIFO_R_W, buffer);
+    return buffer[0];
+}
+void MPU6050::getFIFOBytes(uint8_t *data, uint8_t length) {
+    I2Cdev::readBytes(devAddr, MPU6050_RA_FIFO_R_W, length, data);
+}
+/** Write byte to FIFO buffer.
+ * @see getFIFOByte()
+ * @see MPU6050_RA_FIFO_R_W
+ */
+void MPU6050::setFIFOByte(uint8_t data) {
+    I2Cdev::writeByte(devAddr, MPU6050_RA_FIFO_R_W, data);
+}
+
+// WHO_AM_I register
+
+/** Get Device ID.
+ * This register is used to verify the identity of the device (0b110100, 0x34).
+ * @return Device ID (6 bits only! should be 0x34)
+ * @see MPU6050_RA_WHO_AM_I
+ * @see MPU6050_WHO_AM_I_BIT
+ * @see MPU6050_WHO_AM_I_LENGTH
+ */
+uint8_t MPU6050::getDeviceID() {
+    I2Cdev::readBits(devAddr, MPU6050_RA_WHO_AM_I, MPU6050_WHO_AM_I_BIT, MPU6050_WHO_AM_I_LENGTH, buffer);
+    return buffer[0];
+}
+/** Set Device ID.
+ * Write a new ID into the WHO_AM_I register (no idea why this should ever be
+ * necessary though).
+ * @param id New device ID to set.
+ * @see getDeviceID()
+ * @see MPU6050_RA_WHO_AM_I
+ * @see MPU6050_WHO_AM_I_BIT
+ * @see MPU6050_WHO_AM_I_LENGTH
+ */
+void MPU6050::setDeviceID(uint8_t id) {
+    I2Cdev::writeBits(devAddr, MPU6050_RA_WHO_AM_I, MPU6050_WHO_AM_I_BIT, MPU6050_WHO_AM_I_LENGTH, id);
+}
+
+// ======== UNDOCUMENTED/DMP REGISTERS/METHODS ========
+
+// XG_OFFS_TC register
+
+uint8_t MPU6050::getOTPBankValid() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OTP_BNK_VLD_BIT, buffer);
+    return buffer[0];
+}
+void MPU6050::setOTPBankValid(bool enabled) {
+    I2Cdev::writeBit(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OTP_BNK_VLD_BIT, enabled);
+}
+int8_t MPU6050::getXGyroOffsetTC() {
+    I2Cdev::readBits(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, buffer);
+    return buffer[0];
+}
+void MPU6050::setXGyroOffsetTC(int8_t offset) {
+    I2Cdev::writeBits(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, offset);
+}
+
+// YG_OFFS_TC register
+
+int8_t MPU6050::getYGyroOffsetTC() {
+    I2Cdev::readBits(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, buffer);
+    return buffer[0];
+}
+void MPU6050::setYGyroOffsetTC(int8_t offset) {
+    I2Cdev::writeBits(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, offset);
+}
+
+// ZG_OFFS_TC register
+
+int8_t MPU6050::getZGyroOffsetTC() {
+    I2Cdev::readBits(devAddr, MPU6050_RA_ZG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, buffer);
+    return buffer[0];
+}
+void MPU6050::setZGyroOffsetTC(int8_t offset) {
+    I2Cdev::writeBits(devAddr, MPU6050_RA_ZG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, offset);
+}
+
+// X_FINE_GAIN register
+
+int8_t MPU6050::getXFineGain() {
+    I2Cdev::readByte(devAddr, MPU6050_RA_X_FINE_GAIN, buffer);
+    return buffer[0];
+}
+void MPU6050::setXFineGain(int8_t gain) {
+    I2Cdev::writeByte(devAddr, MPU6050_RA_X_FINE_GAIN, gain);
+}
+
+// Y_FINE_GAIN register
+
+int8_t MPU6050::getYFineGain() {
+    I2Cdev::readByte(devAddr, MPU6050_RA_Y_FINE_GAIN, buffer);
+    return buffer[0];
+}
+void MPU6050::setYFineGain(int8_t gain) {
+    I2Cdev::writeByte(devAddr, MPU6050_RA_Y_FINE_GAIN, gain);
+}
+
+// Z_FINE_GAIN register
+
+int8_t MPU6050::getZFineGain() {
+    I2Cdev::readByte(devAddr, MPU6050_RA_Z_FINE_GAIN, buffer);
+    return buffer[0];
+}
+void MPU6050::setZFineGain(int8_t gain) {
+    I2Cdev::writeByte(devAddr, MPU6050_RA_Z_FINE_GAIN, gain);
+}
+
+// XA_OFFS_* registers
+
+int16_t MPU6050::getXAccelOffset() {
+    I2Cdev::readBytes(devAddr, MPU6050_RA_XA_OFFS_H, 2, buffer);
+    return (((int16_t)buffer[0]) << 8) | buffer[1];
+}
+void MPU6050::setXAccelOffset(int16_t offset) {
+    I2Cdev::writeWord(devAddr, MPU6050_RA_XA_OFFS_H, offset);
+}
+
+// YA_OFFS_* register
+
+int16_t MPU6050::getYAccelOffset() {
+    I2Cdev::readBytes(devAddr, MPU6050_RA_YA_OFFS_H, 2, buffer);
+    return (((int16_t)buffer[0]) << 8) | buffer[1];
+}
+void MPU6050::setYAccelOffset(int16_t offset) {
+    I2Cdev::writeWord(devAddr, MPU6050_RA_YA_OFFS_H, offset);
+}
+
+// ZA_OFFS_* register
+
+int16_t MPU6050::getZAccelOffset() {
+    I2Cdev::readBytes(devAddr, MPU6050_RA_ZA_OFFS_H, 2, buffer);
+    return (((int16_t)buffer[0]) << 8) | buffer[1];
+}
+void MPU6050::setZAccelOffset(int16_t offset) {
+    I2Cdev::writeWord(devAddr, MPU6050_RA_ZA_OFFS_H, offset);
+}
+
+// XG_OFFS_USR* registers
+
+int16_t MPU6050::getXGyroOffset() {
+    I2Cdev::readBytes(devAddr, MPU6050_RA_XG_OFFS_USRH, 2, buffer);
+    return (((int16_t)buffer[0]) << 8) | buffer[1];
+}
+void MPU6050::setXGyroOffset(int16_t offset) {
+    I2Cdev::writeWord(devAddr, MPU6050_RA_XG_OFFS_USRH, offset);
+}
+
+// YG_OFFS_USR* register
+
+int16_t MPU6050::getYGyroOffset() {
+    I2Cdev::readBytes(devAddr, MPU6050_RA_YG_OFFS_USRH, 2, buffer);
+    return (((int16_t)buffer[0]) << 8) | buffer[1];
+}
+void MPU6050::setYGyroOffset(int16_t offset) {
+    I2Cdev::writeWord(devAddr, MPU6050_RA_YG_OFFS_USRH, offset);
+}
+
+// ZG_OFFS_USR* register
+
+int16_t MPU6050::getZGyroOffset() {
+    I2Cdev::readBytes(devAddr, MPU6050_RA_ZG_OFFS_USRH, 2, buffer);
+    return (((int16_t)buffer[0]) << 8) | buffer[1];
+}
+void MPU6050::setZGyroOffset(int16_t offset) {
+    I2Cdev::writeWord(devAddr, MPU6050_RA_ZG_OFFS_USRH, offset);
+}
+
+// INT_ENABLE register (DMP functions)
+
+bool MPU6050::getIntPLLReadyEnabled() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_PLL_RDY_INT_BIT, buffer);
+    return buffer[0];
+}
+void MPU6050::setIntPLLReadyEnabled(bool enabled) {
+    I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_PLL_RDY_INT_BIT, enabled);
+}
+bool MPU6050::getIntDMPEnabled() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DMP_INT_BIT, buffer);
+    return buffer[0];
+}
+void MPU6050::setIntDMPEnabled(bool enabled) {
+    I2Cdev::writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DMP_INT_BIT, enabled);
+}
+
+// DMP_INT_STATUS
+
+bool MPU6050::getDMPInt5Status() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_5_BIT, buffer);
+    return buffer[0];
+}
+bool MPU6050::getDMPInt4Status() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_4_BIT, buffer);
+    return buffer[0];
+}
+bool MPU6050::getDMPInt3Status() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_3_BIT, buffer);
+    return buffer[0];
+}
+bool MPU6050::getDMPInt2Status() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_2_BIT, buffer);
+    return buffer[0];
+}
+bool MPU6050::getDMPInt1Status() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_1_BIT, buffer);
+    return buffer[0];
+}
+bool MPU6050::getDMPInt0Status() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_0_BIT, buffer);
+    return buffer[0];
+}
+
+// INT_STATUS register (DMP functions)
+
+bool MPU6050::getIntPLLReadyStatus() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_PLL_RDY_INT_BIT, buffer);
+    return buffer[0];
+}
+bool MPU6050::getIntDMPStatus() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_DMP_INT_BIT, buffer);
+    return buffer[0];
+}
+
+// USER_CTRL register (DMP functions)
+
+bool MPU6050::getDMPEnabled() {
+    I2Cdev::readBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_DMP_EN_BIT, buffer);
+    return buffer[0];
+}
+void MPU6050::setDMPEnabled(bool enabled) {
+    I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_DMP_EN_BIT, enabled);
+}
+void MPU6050::resetDMP() {
+    I2Cdev::writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_DMP_RESET_BIT, true);
+}
+
+// BANK_SEL register
+
+void MPU6050::setMemoryBank(uint8_t bank, bool prefetchEnabled, bool userBank) {
+    bank &= 0x1F;
+    if (userBank) bank |= 0x20;
+    if (prefetchEnabled) bank |= 0x40;
+    I2Cdev::writeByte(devAddr, MPU6050_RA_BANK_SEL, bank);
+}
+
+// MEM_START_ADDR register
+
+void MPU6050::setMemoryStartAddress(uint8_t address) {
+    I2Cdev::writeByte(devAddr, MPU6050_RA_MEM_START_ADDR, address);
+}
+
+// MEM_R_W register
+
+uint8_t MPU6050::readMemoryByte() {
+    I2Cdev::readByte(devAddr, MPU6050_RA_MEM_R_W, buffer);
+    return buffer[0];
+}
+void MPU6050::writeMemoryByte(uint8_t data) {
+    I2Cdev::writeByte(devAddr, MPU6050_RA_MEM_R_W, data);
+}
+void MPU6050::readMemoryBlock(uint8_t *data, uint16_t dataSize, uint8_t bank, uint8_t address) {
+    setMemoryBank(bank);
+    setMemoryStartAddress(address);
+    uint8_t chunkSize;
+    for (uint16_t i = 0; i < dataSize;) {
+        // determine correct chunk size according to bank position and data size
+        chunkSize = MPU6050_DMP_MEMORY_CHUNK_SIZE;
+
+        // make sure we don't go past the data size
+        if (i + chunkSize > dataSize) chunkSize = dataSize - i;
+
+        // make sure this chunk doesn't go past the bank boundary (256 bytes)
+        if (chunkSize > 256 - address) chunkSize = 256 - address;
+
+        // read the chunk of data as specified
+        I2Cdev::readBytes(devAddr, MPU6050_RA_MEM_R_W, chunkSize, data + i);
+        
+        // increase byte index by [chunkSize]
+        i += chunkSize;
+
+        // uint8_t automatically wraps to 0 at 256
+        address += chunkSize;
+
+        // if we aren't done, update bank (if necessary) and address
+        if (i < dataSize) {
+            if (address == 0) bank++;
+            setMemoryBank(bank);
+            setMemoryStartAddress(address);
+        }
+    }
+}
+bool MPU6050::writeMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank, uint8_t address, bool verify, bool useProgMem) {
+    setMemoryBank(bank);
+    setMemoryStartAddress(address);
+    uint8_t chunkSize;
+    uint8_t *verifyBuffer;
+    uint8_t *progBuffer;
+    uint16_t i;
+    uint8_t j;
+    if (verify) verifyBuffer = (uint8_t *)malloc(MPU6050_DMP_MEMORY_CHUNK_SIZE);
+    if (useProgMem) progBuffer = (uint8_t *)malloc(MPU6050_DMP_MEMORY_CHUNK_SIZE);
+    for (i = 0; i < dataSize;) {
+        // determine correct chunk size according to bank position and data size
+        chunkSize = MPU6050_DMP_MEMORY_CHUNK_SIZE;
+
+        // make sure we don't go past the data size
+        if (i + chunkSize > dataSize) chunkSize = dataSize - i;
+
+        // make sure this chunk doesn't go past the bank boundary (256 bytes)
+        if (chunkSize > 256 - address) chunkSize = 256 - address;
+        
+        if (useProgMem) {
+            // write the chunk of data as specified
+            for (j = 0; j < chunkSize; j++) progBuffer[j] = pgm_read_byte(data + i + j);
+        } else {
+            // write the chunk of data as specified
+            progBuffer = (uint8_t *)data + i;
+        }
+
+        I2Cdev::writeBytes(devAddr, MPU6050_RA_MEM_R_W, chunkSize, progBuffer);
+
+        // verify data if needed
+        if (verify && verifyBuffer) {
+            setMemoryBank(bank);
+            setMemoryStartAddress(address);
+            I2Cdev::readBytes(devAddr, MPU6050_RA_MEM_R_W, chunkSize, verifyBuffer);
+            if (memcmp(progBuffer, verifyBuffer, chunkSize) != 0) {
+                /*Serial.print("Block write verification error, bank ");
+                Serial.print(bank, DEC);
+                Serial.print(", address ");
+                Serial.print(address, DEC);
+                Serial.print("!\nExpected:");
+                for (j = 0; j < chunkSize; j++) {
+                    Serial.print(" 0x");
+                    if (progBuffer[j] < 16) Serial.print("0");
+                    Serial.print(progBuffer[j], HEX);
+                }
+                Serial.print("\nReceived:");
+                for (uint8_t j = 0; j < chunkSize; j++) {
+                    Serial.print(" 0x");
+                    if (verifyBuffer[i + j] < 16) Serial.print("0");
+                    Serial.print(verifyBuffer[i + j], HEX);
+                }
+                Serial.print("\n");*/
+                free(verifyBuffer);
+                if (useProgMem) free(progBuffer);
+                return false; // uh oh.
+            }
+        }
+
+        // increase byte index by [chunkSize]
+        i += chunkSize;
+
+        // uint8_t automatically wraps to 0 at 256
+        address += chunkSize;
+
+        // if we aren't done, update bank (if necessary) and address
+        if (i < dataSize) {
+            if (address == 0) bank++;
+            setMemoryBank(bank);
+            setMemoryStartAddress(address);
+        }
+    }
+    if (verify) free(verifyBuffer);
+    if (useProgMem) free(progBuffer);
+    return true;
+}
+bool MPU6050::writeProgMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank, uint8_t address, bool verify) {
+    return writeMemoryBlock(data, dataSize, bank, address, verify, true);
+}
+bool MPU6050::writeDMPConfigurationSet(const uint8_t *data, uint16_t dataSize, bool useProgMem) {
+    uint8_t *progBuffer, success, special;
+    uint16_t i, j;
+    if (useProgMem) {
+        progBuffer = (uint8_t *)malloc(8); // assume 8-byte blocks, realloc later if necessary
+    }
+
+    // config set data is a long string of blocks with the following structure:
+    // [bank] [offset] [length] [byte[0], byte[1], ..., byte[length]]
+    uint8_t bank, offset, length;
+    for (i = 0; i < dataSize;) {
+        if (useProgMem) {
+            bank = pgm_read_byte(data + i++);
+            offset = pgm_read_byte(data + i++);
+            length = pgm_read_byte(data + i++);
+        } else {
+            bank = data[i++];
+            offset = data[i++];
+            length = data[i++];
+        }
+
+        // write data or perform special action
+        if (length > 0) {
+            // regular block of data to write
+            /*Serial.print("Writing config block to bank ");
+            Serial.print(bank);
+            Serial.print(", offset ");
+            Serial.print(offset);
+            Serial.print(", length=");
+            Serial.println(length);*/
+            if (useProgMem) {
+                if (sizeof(progBuffer) < length) progBuffer = (uint8_t *)realloc(progBuffer, length);
+                for (j = 0; j < length; j++) progBuffer[j] = pgm_read_byte(data + i + j);
+            } else {
+                progBuffer = (uint8_t *)data + i;
+            }
+            success = writeMemoryBlock(progBuffer, length, bank, offset, true);
+            i += length;
+        } else {
+            // special instruction
+            // NOTE: this kind of behavior (what and when to do certain things)
+            // is totally undocumented. This code is in here based on observed
+            // behavior only, and exactly why (or even whether) it has to be here
+            // is anybody's guess for now.
+            if (useProgMem) {
+                special = pgm_read_byte(data + i++);
+            } else {
+                special = data[i++];
+            }
+            /*Serial.print("Special command code ");
+            Serial.print(special, HEX);
+            Serial.println(" found...");*/
+            if (special == 0x01) {
+                // enable DMP-related interrupts
+                
+                //setIntZeroMotionEnabled(true);
+                //setIntFIFOBufferOverflowEnabled(true);
+                //setIntDMPEnabled(true);
+                I2Cdev::writeByte(devAddr, MPU6050_RA_INT_ENABLE, 0x32);  // single operation
+
+                success = true;
+            } else {
+                // unknown special command
+                success = false;
+            }
+        }
+        
+        if (!success) {
+            if (useProgMem) free(progBuffer);
+            return false; // uh oh
+        }
+    }
+    if (useProgMem) free(progBuffer);
+    return true;
+}
+bool MPU6050::writeProgDMPConfigurationSet(const uint8_t *data, uint16_t dataSize) {
+    return writeDMPConfigurationSet(data, dataSize, true);
+}
+
+// DMP_CFG_1 register
+
+uint8_t MPU6050::getDMPConfig1() {
+    I2Cdev::readByte(devAddr, MPU6050_RA_DMP_CFG_1, buffer);
+    return buffer[0];
+}
+void MPU6050::setDMPConfig1(uint8_t config) {
+    I2Cdev::writeByte(devAddr, MPU6050_RA_DMP_CFG_1, config);
+}
+
+// DMP_CFG_2 register
+
+uint8_t MPU6050::getDMPConfig2() {
+    I2Cdev::readByte(devAddr, MPU6050_RA_DMP_CFG_2, buffer);
+    return buffer[0];
+}
+void MPU6050::setDMPConfig2(uint8_t config) {
+    I2Cdev::writeByte(devAddr, MPU6050_RA_DMP_CFG_2, config);
+}
\ No newline at end of file
diff --git a/hardware/digistump/sam/libraries/MPU6050/MPU6050.h b/hardware/digistump/sam/libraries/MPU6050/MPU6050.h
new file mode 100644
index 0000000..bb00718
--- /dev/null
+++ b/hardware/digistump/sam/libraries/MPU6050/MPU6050.h
@@ -0,0 +1,1024 @@
+// I2Cdev library collection - MPU6050 I2C device class
+// Based on InvenSense MPU-6050 register map document rev. 2.0, 5/19/2011 (RM-MPU-6000A-00)
+// 10/3/2011 by Jeff Rowberg 
+// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib
+//
+// Changelog:
+//     ... - ongoing debug release
+
+// NOTE: THIS IS ONLY A PARIAL RELEASE. THIS DEVICE CLASS IS CURRENTLY UNDERGOING ACTIVE
+// DEVELOPMENT AND IS STILL MISSING SOME IMPORTANT FEATURES. PLEASE KEEP THIS IN MIND IF
+// YOU DECIDE TO USE THIS PARTICULAR CODE FOR ANYTHING.
+
+/* ============================================
+I2Cdev device library code is placed under the MIT license
+Copyright (c) 2012 Jeff Rowberg
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+===============================================
+*/
+
+#ifndef _MPU6050_H_
+#define _MPU6050_H_
+
+#include "I2Cdev.h"
+#ifndef __PGMSPACE_H_
+#define __PGMSPACE_H_ 1
+
+#include 
+
+#define PROGMEM
+#define PGM_P  const char *
+#define PSTR(str) (str)
+
+typedef void prog_void;
+typedef char prog_char;
+typedef unsigned char prog_uchar;
+typedef int8_t prog_int8_t;
+typedef uint8_t prog_uint8_t;
+typedef int16_t prog_int16_t;
+typedef uint16_t prog_uint16_t;
+typedef int32_t prog_int32_t;
+typedef uint32_t prog_uint32_t;
+
+#define strcpy_P(dest, src) strcpy((dest), (src))
+#define strcat_P(dest, src) strcat((dest), (src))
+#define strcmp_P(a, b) strcmp((a), (b))
+
+#define pgm_read_byte(addr) (*(const unsigned char *)(addr))
+#define pgm_read_word(addr) (*(const unsigned short *)(addr))
+#define pgm_read_dword(addr) (*(const unsigned long *)(addr))
+#define pgm_read_float(addr) (*(const float *)(addr))
+
+#define pgm_read_byte_near(addr) pgm_read_byte(addr)
+#define pgm_read_word_near(addr) pgm_read_word(addr)
+#define pgm_read_dword_near(addr) pgm_read_dword(addr)
+#define pgm_read_float_near(addr) pgm_read_float(addr)
+#define pgm_read_byte_far(addr) pgm_read_byte(addr)
+#define pgm_read_word_far(addr) pgm_read_word(addr)
+#define pgm_read_dword_far(addr) pgm_read_dword(addr)
+#define pgm_read_float_far(addr) pgm_read_float(addr)
+
+#endif
+
+
+
+#define MPU6050_ADDRESS_AD0_LOW     0x68 // address pin low (GND), default for InvenSense evaluation board
+#define MPU6050_ADDRESS_AD0_HIGH    0x69 // address pin high (VCC)
+#define MPU6050_DEFAULT_ADDRESS     MPU6050_ADDRESS_AD0_LOW
+
+#define MPU6050_RA_XG_OFFS_TC       0x00 //[7] PWR_MODE, [6:1] XG_OFFS_TC, [0] OTP_BNK_VLD
+#define MPU6050_RA_YG_OFFS_TC       0x01 //[7] PWR_MODE, [6:1] YG_OFFS_TC, [0] OTP_BNK_VLD
+#define MPU6050_RA_ZG_OFFS_TC       0x02 //[7] PWR_MODE, [6:1] ZG_OFFS_TC, [0] OTP_BNK_VLD
+#define MPU6050_RA_X_FINE_GAIN      0x03 //[7:0] X_FINE_GAIN
+#define MPU6050_RA_Y_FINE_GAIN      0x04 //[7:0] Y_FINE_GAIN
+#define MPU6050_RA_Z_FINE_GAIN      0x05 //[7:0] Z_FINE_GAIN
+#define MPU6050_RA_XA_OFFS_H        0x06 //[15:0] XA_OFFS
+#define MPU6050_RA_XA_OFFS_L_TC     0x07
+#define MPU6050_RA_YA_OFFS_H        0x08 //[15:0] YA_OFFS
+#define MPU6050_RA_YA_OFFS_L_TC     0x09
+#define MPU6050_RA_ZA_OFFS_H        0x0A //[15:0] ZA_OFFS
+#define MPU6050_RA_ZA_OFFS_L_TC     0x0B
+#define MPU6050_RA_XG_OFFS_USRH     0x13 //[15:0] XG_OFFS_USR
+#define MPU6050_RA_XG_OFFS_USRL     0x14
+#define MPU6050_RA_YG_OFFS_USRH     0x15 //[15:0] YG_OFFS_USR
+#define MPU6050_RA_YG_OFFS_USRL     0x16
+#define MPU6050_RA_ZG_OFFS_USRH     0x17 //[15:0] ZG_OFFS_USR
+#define MPU6050_RA_ZG_OFFS_USRL     0x18
+#define MPU6050_RA_SMPLRT_DIV       0x19
+#define MPU6050_RA_CONFIG           0x1A
+#define MPU6050_RA_GYRO_CONFIG      0x1B
+#define MPU6050_RA_ACCEL_CONFIG     0x1C
+#define MPU6050_RA_FF_THR           0x1D
+#define MPU6050_RA_FF_DUR           0x1E
+#define MPU6050_RA_MOT_THR          0x1F
+#define MPU6050_RA_MOT_DUR          0x20
+#define MPU6050_RA_ZRMOT_THR        0x21
+#define MPU6050_RA_ZRMOT_DUR        0x22
+#define MPU6050_RA_FIFO_EN          0x23
+#define MPU6050_RA_I2C_MST_CTRL     0x24
+#define MPU6050_RA_I2C_SLV0_ADDR    0x25
+#define MPU6050_RA_I2C_SLV0_REG     0x26
+#define MPU6050_RA_I2C_SLV0_CTRL    0x27
+#define MPU6050_RA_I2C_SLV1_ADDR    0x28
+#define MPU6050_RA_I2C_SLV1_REG     0x29
+#define MPU6050_RA_I2C_SLV1_CTRL    0x2A
+#define MPU6050_RA_I2C_SLV2_ADDR    0x2B
+#define MPU6050_RA_I2C_SLV2_REG     0x2C
+#define MPU6050_RA_I2C_SLV2_CTRL    0x2D
+#define MPU6050_RA_I2C_SLV3_ADDR    0x2E
+#define MPU6050_RA_I2C_SLV3_REG     0x2F
+#define MPU6050_RA_I2C_SLV3_CTRL    0x30
+#define MPU6050_RA_I2C_SLV4_ADDR    0x31
+#define MPU6050_RA_I2C_SLV4_REG     0x32
+#define MPU6050_RA_I2C_SLV4_DO      0x33
+#define MPU6050_RA_I2C_SLV4_CTRL    0x34
+#define MPU6050_RA_I2C_SLV4_DI      0x35
+#define MPU6050_RA_I2C_MST_STATUS   0x36
+#define MPU6050_RA_INT_PIN_CFG      0x37
+#define MPU6050_RA_INT_ENABLE       0x38
+#define MPU6050_RA_DMP_INT_STATUS   0x39
+#define MPU6050_RA_INT_STATUS       0x3A
+#define MPU6050_RA_ACCEL_XOUT_H     0x3B
+#define MPU6050_RA_ACCEL_XOUT_L     0x3C
+#define MPU6050_RA_ACCEL_YOUT_H     0x3D
+#define MPU6050_RA_ACCEL_YOUT_L     0x3E
+#define MPU6050_RA_ACCEL_ZOUT_H     0x3F
+#define MPU6050_RA_ACCEL_ZOUT_L     0x40
+#define MPU6050_RA_TEMP_OUT_H       0x41
+#define MPU6050_RA_TEMP_OUT_L       0x42
+#define MPU6050_RA_GYRO_XOUT_H      0x43
+#define MPU6050_RA_GYRO_XOUT_L      0x44
+#define MPU6050_RA_GYRO_YOUT_H      0x45
+#define MPU6050_RA_GYRO_YOUT_L      0x46
+#define MPU6050_RA_GYRO_ZOUT_H      0x47
+#define MPU6050_RA_GYRO_ZOUT_L      0x48
+#define MPU6050_RA_EXT_SENS_DATA_00 0x49
+#define MPU6050_RA_EXT_SENS_DATA_01 0x4A
+#define MPU6050_RA_EXT_SENS_DATA_02 0x4B
+#define MPU6050_RA_EXT_SENS_DATA_03 0x4C
+#define MPU6050_RA_EXT_SENS_DATA_04 0x4D
+#define MPU6050_RA_EXT_SENS_DATA_05 0x4E
+#define MPU6050_RA_EXT_SENS_DATA_06 0x4F
+#define MPU6050_RA_EXT_SENS_DATA_07 0x50
+#define MPU6050_RA_EXT_SENS_DATA_08 0x51
+#define MPU6050_RA_EXT_SENS_DATA_09 0x52
+#define MPU6050_RA_EXT_SENS_DATA_10 0x53
+#define MPU6050_RA_EXT_SENS_DATA_11 0x54
+#define MPU6050_RA_EXT_SENS_DATA_12 0x55
+#define MPU6050_RA_EXT_SENS_DATA_13 0x56
+#define MPU6050_RA_EXT_SENS_DATA_14 0x57
+#define MPU6050_RA_EXT_SENS_DATA_15 0x58
+#define MPU6050_RA_EXT_SENS_DATA_16 0x59
+#define MPU6050_RA_EXT_SENS_DATA_17 0x5A
+#define MPU6050_RA_EXT_SENS_DATA_18 0x5B
+#define MPU6050_RA_EXT_SENS_DATA_19 0x5C
+#define MPU6050_RA_EXT_SENS_DATA_20 0x5D
+#define MPU6050_RA_EXT_SENS_DATA_21 0x5E
+#define MPU6050_RA_EXT_SENS_DATA_22 0x5F
+#define MPU6050_RA_EXT_SENS_DATA_23 0x60
+#define MPU6050_RA_MOT_DETECT_STATUS    0x61
+#define MPU6050_RA_I2C_SLV0_DO      0x63
+#define MPU6050_RA_I2C_SLV1_DO      0x64
+#define MPU6050_RA_I2C_SLV2_DO      0x65
+#define MPU6050_RA_I2C_SLV3_DO      0x66
+#define MPU6050_RA_I2C_MST_DELAY_CTRL   0x67
+#define MPU6050_RA_SIGNAL_PATH_RESET    0x68
+#define MPU6050_RA_MOT_DETECT_CTRL      0x69
+#define MPU6050_RA_USER_CTRL        0x6A
+#define MPU6050_RA_PWR_MGMT_1       0x6B
+#define MPU6050_RA_PWR_MGMT_2       0x6C
+#define MPU6050_RA_BANK_SEL         0x6D
+#define MPU6050_RA_MEM_START_ADDR   0x6E
+#define MPU6050_RA_MEM_R_W          0x6F
+#define MPU6050_RA_DMP_CFG_1        0x70
+#define MPU6050_RA_DMP_CFG_2        0x71
+#define MPU6050_RA_FIFO_COUNTH      0x72
+#define MPU6050_RA_FIFO_COUNTL      0x73
+#define MPU6050_RA_FIFO_R_W         0x74
+#define MPU6050_RA_WHO_AM_I         0x75
+
+#define MPU6050_TC_PWR_MODE_BIT     7
+#define MPU6050_TC_OFFSET_BIT       6
+#define MPU6050_TC_OFFSET_LENGTH    6
+#define MPU6050_TC_OTP_BNK_VLD_BIT  0
+
+#define MPU6050_VDDIO_LEVEL_VLOGIC  0
+#define MPU6050_VDDIO_LEVEL_VDD     1
+
+#define MPU6050_CFG_EXT_SYNC_SET_BIT    5
+#define MPU6050_CFG_EXT_SYNC_SET_LENGTH 3
+#define MPU6050_CFG_DLPF_CFG_BIT    2
+#define MPU6050_CFG_DLPF_CFG_LENGTH 3
+
+#define MPU6050_EXT_SYNC_DISABLED       0x0
+#define MPU6050_EXT_SYNC_TEMP_OUT_L     0x1
+#define MPU6050_EXT_SYNC_GYRO_XOUT_L    0x2
+#define MPU6050_EXT_SYNC_GYRO_YOUT_L    0x3
+#define MPU6050_EXT_SYNC_GYRO_ZOUT_L    0x4
+#define MPU6050_EXT_SYNC_ACCEL_XOUT_L   0x5
+#define MPU6050_EXT_SYNC_ACCEL_YOUT_L   0x6
+#define MPU6050_EXT_SYNC_ACCEL_ZOUT_L   0x7
+
+#define MPU6050_DLPF_BW_256         0x00
+#define MPU6050_DLPF_BW_188         0x01
+#define MPU6050_DLPF_BW_98          0x02
+#define MPU6050_DLPF_BW_42          0x03
+#define MPU6050_DLPF_BW_20          0x04
+#define MPU6050_DLPF_BW_10          0x05
+#define MPU6050_DLPF_BW_5           0x06
+
+#define MPU6050_GCONFIG_FS_SEL_BIT      4
+#define MPU6050_GCONFIG_FS_SEL_LENGTH   2
+
+#define MPU6050_GYRO_FS_250         0x00
+#define MPU6050_GYRO_FS_500         0x01
+#define MPU6050_GYRO_FS_1000        0x02
+#define MPU6050_GYRO_FS_2000        0x03
+
+#define MPU6050_ACONFIG_XA_ST_BIT           7
+#define MPU6050_ACONFIG_YA_ST_BIT           6
+#define MPU6050_ACONFIG_ZA_ST_BIT           5
+#define MPU6050_ACONFIG_AFS_SEL_BIT         4
+#define MPU6050_ACONFIG_AFS_SEL_LENGTH      2
+#define MPU6050_ACONFIG_ACCEL_HPF_BIT       2
+#define MPU6050_ACONFIG_ACCEL_HPF_LENGTH    3
+
+#define MPU6050_ACCEL_FS_2          0x00
+#define MPU6050_ACCEL_FS_4          0x01
+#define MPU6050_ACCEL_FS_8          0x02
+#define MPU6050_ACCEL_FS_16         0x03
+
+#define MPU6050_DHPF_RESET          0x00
+#define MPU6050_DHPF_5              0x01
+#define MPU6050_DHPF_2P5            0x02
+#define MPU6050_DHPF_1P25           0x03
+#define MPU6050_DHPF_0P63           0x04
+#define MPU6050_DHPF_HOLD           0x07
+
+#define MPU6050_TEMP_FIFO_EN_BIT    7
+#define MPU6050_XG_FIFO_EN_BIT      6
+#define MPU6050_YG_FIFO_EN_BIT      5
+#define MPU6050_ZG_FIFO_EN_BIT      4
+#define MPU6050_ACCEL_FIFO_EN_BIT   3
+#define MPU6050_SLV2_FIFO_EN_BIT    2
+#define MPU6050_SLV1_FIFO_EN_BIT    1
+#define MPU6050_SLV0_FIFO_EN_BIT    0
+
+#define MPU6050_MULT_MST_EN_BIT     7
+#define MPU6050_WAIT_FOR_ES_BIT     6
+#define MPU6050_SLV_3_FIFO_EN_BIT   5
+#define MPU6050_I2C_MST_P_NSR_BIT   4
+#define MPU6050_I2C_MST_CLK_BIT     3
+#define MPU6050_I2C_MST_CLK_LENGTH  4
+
+#define MPU6050_CLOCK_DIV_348       0x0
+#define MPU6050_CLOCK_DIV_333       0x1
+#define MPU6050_CLOCK_DIV_320       0x2
+#define MPU6050_CLOCK_DIV_308       0x3
+#define MPU6050_CLOCK_DIV_296       0x4
+#define MPU6050_CLOCK_DIV_286       0x5
+#define MPU6050_CLOCK_DIV_276       0x6
+#define MPU6050_CLOCK_DIV_267       0x7
+#define MPU6050_CLOCK_DIV_258       0x8
+#define MPU6050_CLOCK_DIV_500       0x9
+#define MPU6050_CLOCK_DIV_471       0xA
+#define MPU6050_CLOCK_DIV_444       0xB
+#define MPU6050_CLOCK_DIV_421       0xC
+#define MPU6050_CLOCK_DIV_400       0xD
+#define MPU6050_CLOCK_DIV_381       0xE
+#define MPU6050_CLOCK_DIV_364       0xF
+
+#define MPU6050_I2C_SLV_RW_BIT      7
+#define MPU6050_I2C_SLV_ADDR_BIT    6
+#define MPU6050_I2C_SLV_ADDR_LENGTH 7
+#define MPU6050_I2C_SLV_EN_BIT      7
+#define MPU6050_I2C_SLV_BYTE_SW_BIT 6
+#define MPU6050_I2C_SLV_REG_DIS_BIT 5
+#define MPU6050_I2C_SLV_GRP_BIT     4
+#define MPU6050_I2C_SLV_LEN_BIT     3
+#define MPU6050_I2C_SLV_LEN_LENGTH  4
+
+#define MPU6050_I2C_SLV4_RW_BIT         7
+#define MPU6050_I2C_SLV4_ADDR_BIT       6
+#define MPU6050_I2C_SLV4_ADDR_LENGTH    7
+#define MPU6050_I2C_SLV4_EN_BIT         7
+#define MPU6050_I2C_SLV4_INT_EN_BIT     6
+#define MPU6050_I2C_SLV4_REG_DIS_BIT    5
+#define MPU6050_I2C_SLV4_MST_DLY_BIT    4
+#define MPU6050_I2C_SLV4_MST_DLY_LENGTH 5
+
+#define MPU6050_MST_PASS_THROUGH_BIT    7
+#define MPU6050_MST_I2C_SLV4_DONE_BIT   6
+#define MPU6050_MST_I2C_LOST_ARB_BIT    5
+#define MPU6050_MST_I2C_SLV4_NACK_BIT   4
+#define MPU6050_MST_I2C_SLV3_NACK_BIT   3
+#define MPU6050_MST_I2C_SLV2_NACK_BIT   2
+#define MPU6050_MST_I2C_SLV1_NACK_BIT   1
+#define MPU6050_MST_I2C_SLV0_NACK_BIT   0
+
+#define MPU6050_INTCFG_INT_LEVEL_BIT        7
+#define MPU6050_INTCFG_INT_OPEN_BIT         6
+#define MPU6050_INTCFG_LATCH_INT_EN_BIT     5
+#define MPU6050_INTCFG_INT_RD_CLEAR_BIT     4
+#define MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT  3
+#define MPU6050_INTCFG_FSYNC_INT_EN_BIT     2
+#define MPU6050_INTCFG_I2C_BYPASS_EN_BIT    1
+#define MPU6050_INTCFG_CLKOUT_EN_BIT        0
+
+#define MPU6050_INTMODE_ACTIVEHIGH  0x00
+#define MPU6050_INTMODE_ACTIVELOW   0x01
+
+#define MPU6050_INTDRV_PUSHPULL     0x00
+#define MPU6050_INTDRV_OPENDRAIN    0x01
+
+#define MPU6050_INTLATCH_50USPULSE  0x00
+#define MPU6050_INTLATCH_WAITCLEAR  0x01
+
+#define MPU6050_INTCLEAR_STATUSREAD 0x00
+#define MPU6050_INTCLEAR_ANYREAD    0x01
+
+#define MPU6050_INTERRUPT_FF_BIT            7
+#define MPU6050_INTERRUPT_MOT_BIT           6
+#define MPU6050_INTERRUPT_ZMOT_BIT          5
+#define MPU6050_INTERRUPT_FIFO_OFLOW_BIT    4
+#define MPU6050_INTERRUPT_I2C_MST_INT_BIT   3
+#define MPU6050_INTERRUPT_PLL_RDY_INT_BIT   2
+#define MPU6050_INTERRUPT_DMP_INT_BIT       1
+#define MPU6050_INTERRUPT_DATA_RDY_BIT      0
+
+// TODO: figure out what these actually do
+// UMPL source code is not very obivous
+#define MPU6050_DMPINT_5_BIT            5
+#define MPU6050_DMPINT_4_BIT            4
+#define MPU6050_DMPINT_3_BIT            3
+#define MPU6050_DMPINT_2_BIT            2
+#define MPU6050_DMPINT_1_BIT            1
+#define MPU6050_DMPINT_0_BIT            0
+
+#define MPU6050_MOTION_MOT_XNEG_BIT     7
+#define MPU6050_MOTION_MOT_XPOS_BIT     6
+#define MPU6050_MOTION_MOT_YNEG_BIT     5
+#define MPU6050_MOTION_MOT_YPOS_BIT     4
+#define MPU6050_MOTION_MOT_ZNEG_BIT     3
+#define MPU6050_MOTION_MOT_ZPOS_BIT     2
+#define MPU6050_MOTION_MOT_ZRMOT_BIT    0
+
+#define MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT   7
+#define MPU6050_DELAYCTRL_I2C_SLV4_DLY_EN_BIT   4
+#define MPU6050_DELAYCTRL_I2C_SLV3_DLY_EN_BIT   3
+#define MPU6050_DELAYCTRL_I2C_SLV2_DLY_EN_BIT   2
+#define MPU6050_DELAYCTRL_I2C_SLV1_DLY_EN_BIT   1
+#define MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT   0
+
+#define MPU6050_PATHRESET_GYRO_RESET_BIT    2
+#define MPU6050_PATHRESET_ACCEL_RESET_BIT   1
+#define MPU6050_PATHRESET_TEMP_RESET_BIT    0
+
+#define MPU6050_DETECT_ACCEL_ON_DELAY_BIT       5
+#define MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH    2
+#define MPU6050_DETECT_FF_COUNT_BIT             3
+#define MPU6050_DETECT_FF_COUNT_LENGTH          2
+#define MPU6050_DETECT_MOT_COUNT_BIT            1
+#define MPU6050_DETECT_MOT_COUNT_LENGTH         2
+
+#define MPU6050_DETECT_DECREMENT_RESET  0x0
+#define MPU6050_DETECT_DECREMENT_1      0x1
+#define MPU6050_DETECT_DECREMENT_2      0x2
+#define MPU6050_DETECT_DECREMENT_4      0x3
+
+#define MPU6050_USERCTRL_DMP_EN_BIT             7
+#define MPU6050_USERCTRL_FIFO_EN_BIT            6
+#define MPU6050_USERCTRL_I2C_MST_EN_BIT         5
+#define MPU6050_USERCTRL_I2C_IF_DIS_BIT         4
+#define MPU6050_USERCTRL_DMP_RESET_BIT          3
+#define MPU6050_USERCTRL_FIFO_RESET_BIT         2
+#define MPU6050_USERCTRL_I2C_MST_RESET_BIT      1
+#define MPU6050_USERCTRL_SIG_COND_RESET_BIT     0
+
+#define MPU6050_PWR1_DEVICE_RESET_BIT   7
+#define MPU6050_PWR1_SLEEP_BIT          6
+#define MPU6050_PWR1_CYCLE_BIT          5
+#define MPU6050_PWR1_TEMP_DIS_BIT       3
+#define MPU6050_PWR1_CLKSEL_BIT         2
+#define MPU6050_PWR1_CLKSEL_LENGTH      3
+
+#define MPU6050_CLOCK_INTERNAL          0x00
+#define MPU6050_CLOCK_PLL_XGYRO         0x01
+#define MPU6050_CLOCK_PLL_YGYRO         0x02
+#define MPU6050_CLOCK_PLL_ZGYRO         0x03
+#define MPU6050_CLOCK_PLL_EXT32K        0x04
+#define MPU6050_CLOCK_PLL_EXT19M        0x05
+#define MPU6050_CLOCK_KEEP_RESET        0x07
+
+#define MPU6050_PWR2_LP_WAKE_CTRL_BIT       7
+#define MPU6050_PWR2_LP_WAKE_CTRL_LENGTH    2
+#define MPU6050_PWR2_STBY_XA_BIT            5
+#define MPU6050_PWR2_STBY_YA_BIT            4
+#define MPU6050_PWR2_STBY_ZA_BIT            3
+#define MPU6050_PWR2_STBY_XG_BIT            2
+#define MPU6050_PWR2_STBY_YG_BIT            1
+#define MPU6050_PWR2_STBY_ZG_BIT            0
+
+#define MPU6050_WAKE_FREQ_1P25      0x0
+#define MPU6050_WAKE_FREQ_2P5       0x1
+#define MPU6050_WAKE_FREQ_5         0x2
+#define MPU6050_WAKE_FREQ_10        0x3
+
+#define MPU6050_BANKSEL_PRFTCH_EN_BIT       6
+#define MPU6050_BANKSEL_CFG_USER_BANK_BIT   5
+#define MPU6050_BANKSEL_MEM_SEL_BIT         4
+#define MPU6050_BANKSEL_MEM_SEL_LENGTH      5
+
+#define MPU6050_WHO_AM_I_BIT        6
+#define MPU6050_WHO_AM_I_LENGTH     6
+
+#define MPU6050_DMP_MEMORY_BANKS        8
+#define MPU6050_DMP_MEMORY_BANK_SIZE    256
+#define MPU6050_DMP_MEMORY_CHUNK_SIZE   16
+
+// note: DMP code memory blocks defined at end of header file
+
+class MPU6050 {
+    public:
+        MPU6050();
+        MPU6050(uint8_t address);
+
+        void initialize();
+        bool testConnection();
+
+        // AUX_VDDIO register
+        uint8_t getAuxVDDIOLevel();
+        void setAuxVDDIOLevel(uint8_t level);
+
+        // SMPLRT_DIV register
+        uint8_t getRate();
+        void setRate(uint8_t rate);
+
+        // CONFIG register
+        uint8_t getExternalFrameSync();
+        void setExternalFrameSync(uint8_t sync);
+        uint8_t getDLPFMode();
+        void setDLPFMode(uint8_t bandwidth);
+
+        // GYRO_CONFIG register
+        uint8_t getFullScaleGyroRange();
+        void setFullScaleGyroRange(uint8_t range);
+
+        // ACCEL_CONFIG register
+        bool getAccelXSelfTest();
+        void setAccelXSelfTest(bool enabled);
+        bool getAccelYSelfTest();
+        void setAccelYSelfTest(bool enabled);
+        bool getAccelZSelfTest();
+        void setAccelZSelfTest(bool enabled);
+        uint8_t getFullScaleAccelRange();
+        void setFullScaleAccelRange(uint8_t range);
+        uint8_t getDHPFMode();
+        void setDHPFMode(uint8_t mode);
+
+        // FF_THR register
+        uint8_t getFreefallDetectionThreshold();
+        void setFreefallDetectionThreshold(uint8_t threshold);
+
+        // FF_DUR register
+        uint8_t getFreefallDetectionDuration();
+        void setFreefallDetectionDuration(uint8_t duration);
+
+        // MOT_THR register
+        uint8_t getMotionDetectionThreshold();
+        void setMotionDetectionThreshold(uint8_t threshold);
+
+        // MOT_DUR register
+        uint8_t getMotionDetectionDuration();
+        void setMotionDetectionDuration(uint8_t duration);
+
+        // ZRMOT_THR register
+        uint8_t getZeroMotionDetectionThreshold();
+        void setZeroMotionDetectionThreshold(uint8_t threshold);
+
+        // ZRMOT_DUR register
+        uint8_t getZeroMotionDetectionDuration();
+        void setZeroMotionDetectionDuration(uint8_t duration);
+
+        // FIFO_EN register
+        bool getTempFIFOEnabled();
+        void setTempFIFOEnabled(bool enabled);
+        bool getXGyroFIFOEnabled();
+        void setXGyroFIFOEnabled(bool enabled);
+        bool getYGyroFIFOEnabled();
+        void setYGyroFIFOEnabled(bool enabled);
+        bool getZGyroFIFOEnabled();
+        void setZGyroFIFOEnabled(bool enabled);
+        bool getAccelFIFOEnabled();
+        void setAccelFIFOEnabled(bool enabled);
+        bool getSlave2FIFOEnabled();
+        void setSlave2FIFOEnabled(bool enabled);
+        bool getSlave1FIFOEnabled();
+        void setSlave1FIFOEnabled(bool enabled);
+        bool getSlave0FIFOEnabled();
+        void setSlave0FIFOEnabled(bool enabled);
+
+        // I2C_MST_CTRL register
+        bool getMultiMasterEnabled();
+        void setMultiMasterEnabled(bool enabled);
+        bool getWaitForExternalSensorEnabled();
+        void setWaitForExternalSensorEnabled(bool enabled);
+        bool getSlave3FIFOEnabled();
+        void setSlave3FIFOEnabled(bool enabled);
+        bool getSlaveReadWriteTransitionEnabled();
+        void setSlaveReadWriteTransitionEnabled(bool enabled);
+        uint8_t getMasterClockSpeed();
+        void setMasterClockSpeed(uint8_t speed);
+
+        // I2C_SLV* registers (Slave 0-3)
+        uint8_t getSlaveAddress(uint8_t num);
+        void setSlaveAddress(uint8_t num, uint8_t address);
+        uint8_t getSlaveRegister(uint8_t num);
+        void setSlaveRegister(uint8_t num, uint8_t reg);
+        bool getSlaveEnabled(uint8_t num);
+        void setSlaveEnabled(uint8_t num, bool enabled);
+        bool getSlaveWordByteSwap(uint8_t num);
+        void setSlaveWordByteSwap(uint8_t num, bool enabled);
+        bool getSlaveWriteMode(uint8_t num);
+        void setSlaveWriteMode(uint8_t num, bool mode);
+        bool getSlaveWordGroupOffset(uint8_t num);
+        void setSlaveWordGroupOffset(uint8_t num, bool enabled);
+        uint8_t getSlaveDataLength(uint8_t num);
+        void setSlaveDataLength(uint8_t num, uint8_t length);
+
+        // I2C_SLV* registers (Slave 4)
+        uint8_t getSlave4Address();
+        void setSlave4Address(uint8_t address);
+        uint8_t getSlave4Register();
+        void setSlave4Register(uint8_t reg);
+        void setSlave4OutputByte(uint8_t data);
+        bool getSlave4Enabled();
+        void setSlave4Enabled(bool enabled);
+        bool getSlave4InterruptEnabled();
+        void setSlave4InterruptEnabled(bool enabled);
+        bool getSlave4WriteMode();
+        void setSlave4WriteMode(bool mode);
+        uint8_t getSlave4MasterDelay();
+        void setSlave4MasterDelay(uint8_t delay);
+        uint8_t getSlate4InputByte();
+
+        // I2C_MST_STATUS register
+        bool getPassthroughStatus();
+        bool getSlave4IsDone();
+        bool getLostArbitration();
+        bool getSlave4Nack();
+        bool getSlave3Nack();
+        bool getSlave2Nack();
+        bool getSlave1Nack();
+        bool getSlave0Nack();
+
+        // INT_PIN_CFG register
+        bool getInterruptMode();
+        void setInterruptMode(bool mode);
+        bool getInterruptDrive();
+        void setInterruptDrive(bool drive);
+        bool getInterruptLatch();
+        void setInterruptLatch(bool latch);
+        bool getInterruptLatchClear();
+        void setInterruptLatchClear(bool clear);
+        bool getFSyncInterruptLevel();
+        void setFSyncInterruptLevel(bool level);
+        bool getFSyncInterruptEnabled();
+        void setFSyncInterruptEnabled(bool enabled);
+        bool getI2CBypassEnabled();
+        void setI2CBypassEnabled(bool enabled);
+        bool getClockOutputEnabled();
+        void setClockOutputEnabled(bool enabled);
+
+        // INT_ENABLE register
+        uint8_t getIntEnabled();
+        void setIntEnabled(uint8_t enabled);
+        bool getIntFreefallEnabled();
+        void setIntFreefallEnabled(bool enabled);
+        bool getIntMotionEnabled();
+        void setIntMotionEnabled(bool enabled);
+        bool getIntZeroMotionEnabled();
+        void setIntZeroMotionEnabled(bool enabled);
+        bool getIntFIFOBufferOverflowEnabled();
+        void setIntFIFOBufferOverflowEnabled(bool enabled);
+        bool getIntI2CMasterEnabled();
+        void setIntI2CMasterEnabled(bool enabled);
+        bool getIntDataReadyEnabled();
+        void setIntDataReadyEnabled(bool enabled);
+
+        // INT_STATUS register
+        uint8_t getIntStatus();
+        bool getIntFreefallStatus();
+        bool getIntMotionStatus();
+        bool getIntZeroMotionStatus();
+        bool getIntFIFOBufferOverflowStatus();
+        bool getIntI2CMasterStatus();
+        bool getIntDataReadyStatus();
+
+        // ACCEL_*OUT_* registers
+        void getMotion9(int16_t* ax, int16_t* ay, int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz, int16_t* mx, int16_t* my, int16_t* mz);
+        void getMotion6(int16_t* ax, int16_t* ay, int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz);
+        void getAcceleration(int16_t* x, int16_t* y, int16_t* z);
+        int16_t getAccelerationX();
+        int16_t getAccelerationY();
+        int16_t getAccelerationZ();
+
+        // TEMP_OUT_* registers
+        int16_t getTemperature();
+
+        // GYRO_*OUT_* registers
+        void getRotation(int16_t* x, int16_t* y, int16_t* z);
+        int16_t getRotationX();
+        int16_t getRotationY();
+        int16_t getRotationZ();
+
+        // EXT_SENS_DATA_* registers
+        uint8_t getExternalSensorByte(int position);
+        uint16_t getExternalSensorWord(int position);
+        uint32_t getExternalSensorDWord(int position);
+
+        // MOT_DETECT_STATUS register
+        bool getXNegMotionDetected();
+        bool getXPosMotionDetected();
+        bool getYNegMotionDetected();
+        bool getYPosMotionDetected();
+        bool getZNegMotionDetected();
+        bool getZPosMotionDetected();
+        bool getZeroMotionDetected();
+
+        // I2C_SLV*_DO register
+        void setSlaveOutputByte(uint8_t num, uint8_t data);
+
+        // I2C_MST_DELAY_CTRL register
+        bool getExternalShadowDelayEnabled();
+        void setExternalShadowDelayEnabled(bool enabled);
+        bool getSlaveDelayEnabled(uint8_t num);
+        void setSlaveDelayEnabled(uint8_t num, bool enabled);
+
+        // SIGNAL_PATH_RESET register
+        void resetGyroscopePath();
+        void resetAccelerometerPath();
+        void resetTemperaturePath();
+
+        // MOT_DETECT_CTRL register
+        uint8_t getAccelerometerPowerOnDelay();
+        void setAccelerometerPowerOnDelay(uint8_t delay);
+        uint8_t getFreefallDetectionCounterDecrement();
+        void setFreefallDetectionCounterDecrement(uint8_t decrement);
+        uint8_t getMotionDetectionCounterDecrement();
+        void setMotionDetectionCounterDecrement(uint8_t decrement);
+
+        // USER_CTRL register
+        bool getFIFOEnabled();
+        void setFIFOEnabled(bool enabled);
+        bool getI2CMasterModeEnabled();
+        void setI2CMasterModeEnabled(bool enabled);
+        void switchSPIEnabled(bool enabled);
+        void resetFIFO();
+        void resetI2CMaster();
+        void resetSensors();
+
+        // PWR_MGMT_1 register
+        void reset();
+        bool getSleepEnabled();
+        void setSleepEnabled(bool enabled);
+        bool getWakeCycleEnabled();
+        void setWakeCycleEnabled(bool enabled);
+        bool getTempSensorEnabled();
+        void setTempSensorEnabled(bool enabled);
+        uint8_t getClockSource();
+        void setClockSource(uint8_t source);
+
+        // PWR_MGMT_2 register
+        uint8_t getWakeFrequency();
+        void setWakeFrequency(uint8_t frequency);
+        bool getStandbyXAccelEnabled();
+        void setStandbyXAccelEnabled(bool enabled);
+        bool getStandbyYAccelEnabled();
+        void setStandbyYAccelEnabled(bool enabled);
+        bool getStandbyZAccelEnabled();
+        void setStandbyZAccelEnabled(bool enabled);
+        bool getStandbyXGyroEnabled();
+        void setStandbyXGyroEnabled(bool enabled);
+        bool getStandbyYGyroEnabled();
+        void setStandbyYGyroEnabled(bool enabled);
+        bool getStandbyZGyroEnabled();
+        void setStandbyZGyroEnabled(bool enabled);
+
+        // FIFO_COUNT_* registers
+        uint16_t getFIFOCount();
+
+        // FIFO_R_W register
+        uint8_t getFIFOByte();
+        void setFIFOByte(uint8_t data);
+        void getFIFOBytes(uint8_t *data, uint8_t length);
+
+        // WHO_AM_I register
+        uint8_t getDeviceID();
+        void setDeviceID(uint8_t id);
+        
+        // ======== UNDOCUMENTED/DMP REGISTERS/METHODS ========
+        
+        // XG_OFFS_TC register
+        uint8_t getOTPBankValid();
+        void setOTPBankValid(bool enabled);
+        int8_t getXGyroOffsetTC();
+        void setXGyroOffsetTC(int8_t offset);
+
+        // YG_OFFS_TC register
+        int8_t getYGyroOffsetTC();
+        void setYGyroOffsetTC(int8_t offset);
+
+        // ZG_OFFS_TC register
+        int8_t getZGyroOffsetTC();
+        void setZGyroOffsetTC(int8_t offset);
+
+        // X_FINE_GAIN register
+        int8_t getXFineGain();
+        void setXFineGain(int8_t gain);
+
+        // Y_FINE_GAIN register
+        int8_t getYFineGain();
+        void setYFineGain(int8_t gain);
+
+        // Z_FINE_GAIN register
+        int8_t getZFineGain();
+        void setZFineGain(int8_t gain);
+
+        // XA_OFFS_* registers
+        int16_t getXAccelOffset();
+        void setXAccelOffset(int16_t offset);
+
+        // YA_OFFS_* register
+        int16_t getYAccelOffset();
+        void setYAccelOffset(int16_t offset);
+
+        // ZA_OFFS_* register
+        int16_t getZAccelOffset();
+        void setZAccelOffset(int16_t offset);
+
+        // XG_OFFS_USR* registers
+        int16_t getXGyroOffset();
+        void setXGyroOffset(int16_t offset);
+
+        // YG_OFFS_USR* register
+        int16_t getYGyroOffset();
+        void setYGyroOffset(int16_t offset);
+
+        // ZG_OFFS_USR* register
+        int16_t getZGyroOffset();
+        void setZGyroOffset(int16_t offset);
+        
+        // INT_ENABLE register (DMP functions)
+        bool getIntPLLReadyEnabled();
+        void setIntPLLReadyEnabled(bool enabled);
+        bool getIntDMPEnabled();
+        void setIntDMPEnabled(bool enabled);
+        
+        // DMP_INT_STATUS
+        bool getDMPInt5Status();
+        bool getDMPInt4Status();
+        bool getDMPInt3Status();
+        bool getDMPInt2Status();
+        bool getDMPInt1Status();
+        bool getDMPInt0Status();
+
+        // INT_STATUS register (DMP functions)
+        bool getIntPLLReadyStatus();
+        bool getIntDMPStatus();
+        
+        // USER_CTRL register (DMP functions)
+        bool getDMPEnabled();
+        void setDMPEnabled(bool enabled);
+        void resetDMP();
+        
+        // BANK_SEL register
+        void setMemoryBank(uint8_t bank, bool prefetchEnabled=false, bool userBank=false);
+        
+        // MEM_START_ADDR register
+        void setMemoryStartAddress(uint8_t address);
+        
+        // MEM_R_W register
+        uint8_t readMemoryByte();
+        void writeMemoryByte(uint8_t data);
+        void readMemoryBlock(uint8_t *data, uint16_t dataSize, uint8_t bank=0, uint8_t address=0);
+        bool writeMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank=0, uint8_t address=0, bool verify=true, bool useProgMem=false);
+        bool writeProgMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank=0, uint8_t address=0, bool verify=true);
+
+        bool writeDMPConfigurationSet(const uint8_t *data, uint16_t dataSize, bool useProgMem=false);
+        bool writeProgDMPConfigurationSet(const uint8_t *data, uint16_t dataSize);
+
+        // DMP_CFG_1 register
+        uint8_t getDMPConfig1();
+        void setDMPConfig1(uint8_t config);
+
+        // DMP_CFG_2 register
+        uint8_t getDMPConfig2();
+        void setDMPConfig2(uint8_t config);
+
+        // special methods for MotionApps 2.0 implementation
+        #ifdef MPU6050_INCLUDE_DMP_MOTIONAPPS20
+            uint8_t *dmpPacketBuffer;
+            uint16_t dmpPacketSize;
+
+            uint8_t dmpInitialize();
+            bool dmpPacketAvailable();
+
+            uint8_t dmpSetFIFORate(uint8_t fifoRate);
+            uint8_t dmpGetFIFORate();
+            uint8_t dmpGetSampleStepSizeMS();
+            uint8_t dmpGetSampleFrequency();
+            int32_t dmpDecodeTemperature(int8_t tempReg);
+            
+            // Register callbacks after a packet of FIFO data is processed
+            //uint8_t dmpRegisterFIFORateProcess(inv_obj_func func, int16_t priority);
+            //uint8_t dmpUnregisterFIFORateProcess(inv_obj_func func);
+            uint8_t dmpRunFIFORateProcesses();
+            
+            // Setup FIFO for various output
+            uint8_t dmpSendQuaternion(uint_fast16_t accuracy);
+            uint8_t dmpSendGyro(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendAccel(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendLinearAccel(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendLinearAccelInWorld(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendControlData(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendSensorData(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendExternalSensorData(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendGravity(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendPacketNumber(uint_fast16_t accuracy);
+            uint8_t dmpSendQuantizedAccel(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendEIS(uint_fast16_t elements, uint_fast16_t accuracy);
+
+            // Get Fixed Point data from FIFO
+            uint8_t dmpGetAccel(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetAccel(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetAccel(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetQuaternion(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetQuaternion(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetQuaternion(Quaternion *q, const uint8_t* packet=0);
+            uint8_t dmpGet6AxisQuaternion(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGet6AxisQuaternion(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGet6AxisQuaternion(Quaternion *q, const uint8_t* packet=0);
+            uint8_t dmpGetRelativeQuaternion(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetRelativeQuaternion(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetRelativeQuaternion(Quaternion *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyro(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyro(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyro(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpSetLinearAccelFilterCoefficient(float coef);
+            uint8_t dmpGetLinearAccel(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetLinearAccel(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetLinearAccel(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetLinearAccel(VectorInt16 *v, VectorInt16 *vRaw, VectorFloat *gravity);
+            uint8_t dmpGetLinearAccelInWorld(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetLinearAccelInWorld(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetLinearAccelInWorld(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetLinearAccelInWorld(VectorInt16 *v, VectorInt16 *vReal, Quaternion *q);
+            uint8_t dmpGetGyroAndAccelSensor(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyroAndAccelSensor(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyroAndAccelSensor(VectorInt16 *g, VectorInt16 *a, const uint8_t* packet=0);
+            uint8_t dmpGetGyroSensor(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyroSensor(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyroSensor(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetControlData(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetTemperature(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGravity(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGravity(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGravity(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetGravity(VectorFloat *v, Quaternion *q);
+            uint8_t dmpGetUnquantizedAccel(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetUnquantizedAccel(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetUnquantizedAccel(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetQuantizedAccel(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetQuantizedAccel(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetQuantizedAccel(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetExternalSensorData(int32_t *data, uint16_t size, const uint8_t* packet=0);
+            uint8_t dmpGetEIS(int32_t *data, const uint8_t* packet=0);
+            
+            uint8_t dmpGetEuler(float *data, Quaternion *q);
+            uint8_t dmpGetYawPitchRoll(float *data, Quaternion *q, VectorFloat *gravity);
+
+            // Get Floating Point data from FIFO
+            uint8_t dmpGetAccelFloat(float *data, const uint8_t* packet=0);
+            uint8_t dmpGetQuaternionFloat(float *data, const uint8_t* packet=0);
+
+            uint8_t dmpProcessFIFOPacket(const unsigned char *dmpData);
+            uint8_t dmpReadAndProcessFIFOPacket(uint8_t numPackets, uint8_t *processed=NULL);
+
+            uint8_t dmpSetFIFOProcessedCallback(void (*func) (void));
+
+            uint8_t dmpInitFIFOParam();
+            uint8_t dmpCloseFIFO();
+            uint8_t dmpSetGyroDataSource(uint8_t source);
+            uint8_t dmpDecodeQuantizedAccel();
+            uint32_t dmpGetGyroSumOfSquare();
+            uint32_t dmpGetAccelSumOfSquare();
+            void dmpOverrideQuaternion(long *q);
+            uint16_t dmpGetFIFOPacketSize();
+        #endif
+
+        // special methods for MotionApps 4.1 implementation
+        #ifdef MPU6050_INCLUDE_DMP_MOTIONAPPS41
+            uint8_t *dmpPacketBuffer;
+            uint16_t dmpPacketSize;
+
+            uint8_t dmpInitialize();
+            bool dmpPacketAvailable();
+
+            uint8_t dmpSetFIFORate(uint8_t fifoRate);
+            uint8_t dmpGetFIFORate();
+            uint8_t dmpGetSampleStepSizeMS();
+            uint8_t dmpGetSampleFrequency();
+            int32_t dmpDecodeTemperature(int8_t tempReg);
+            
+            // Register callbacks after a packet of FIFO data is processed
+            //uint8_t dmpRegisterFIFORateProcess(inv_obj_func func, int16_t priority);
+            //uint8_t dmpUnregisterFIFORateProcess(inv_obj_func func);
+            uint8_t dmpRunFIFORateProcesses();
+            
+            // Setup FIFO for various output
+            uint8_t dmpSendQuaternion(uint_fast16_t accuracy);
+            uint8_t dmpSendGyro(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendAccel(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendLinearAccel(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendLinearAccelInWorld(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendControlData(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendSensorData(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendExternalSensorData(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendGravity(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendPacketNumber(uint_fast16_t accuracy);
+            uint8_t dmpSendQuantizedAccel(uint_fast16_t elements, uint_fast16_t accuracy);
+            uint8_t dmpSendEIS(uint_fast16_t elements, uint_fast16_t accuracy);
+
+            // Get Fixed Point data from FIFO
+            uint8_t dmpGetAccel(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetAccel(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetAccel(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetQuaternion(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetQuaternion(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetQuaternion(Quaternion *q, const uint8_t* packet=0);
+            uint8_t dmpGet6AxisQuaternion(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGet6AxisQuaternion(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGet6AxisQuaternion(Quaternion *q, const uint8_t* packet=0);
+            uint8_t dmpGetRelativeQuaternion(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetRelativeQuaternion(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetRelativeQuaternion(Quaternion *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyro(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyro(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyro(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetMag(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpSetLinearAccelFilterCoefficient(float coef);
+            uint8_t dmpGetLinearAccel(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetLinearAccel(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetLinearAccel(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetLinearAccel(VectorInt16 *v, VectorInt16 *vRaw, VectorFloat *gravity);
+            uint8_t dmpGetLinearAccelInWorld(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetLinearAccelInWorld(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetLinearAccelInWorld(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetLinearAccelInWorld(VectorInt16 *v, VectorInt16 *vReal, Quaternion *q);
+            uint8_t dmpGetGyroAndAccelSensor(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyroAndAccelSensor(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyroAndAccelSensor(VectorInt16 *g, VectorInt16 *a, const uint8_t* packet=0);
+            uint8_t dmpGetGyroSensor(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyroSensor(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGyroSensor(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetControlData(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetTemperature(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGravity(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGravity(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetGravity(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetGravity(VectorFloat *v, Quaternion *q);
+            uint8_t dmpGetUnquantizedAccel(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetUnquantizedAccel(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetUnquantizedAccel(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetQuantizedAccel(int32_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetQuantizedAccel(int16_t *data, const uint8_t* packet=0);
+            uint8_t dmpGetQuantizedAccel(VectorInt16 *v, const uint8_t* packet=0);
+            uint8_t dmpGetExternalSensorData(int32_t *data, uint16_t size, const uint8_t* packet=0);
+            uint8_t dmpGetEIS(int32_t *data, const uint8_t* packet=0);
+            
+            uint8_t dmpGetEuler(float *data, Quaternion *q);
+            uint8_t dmpGetYawPitchRoll(float *data, Quaternion *q, VectorFloat *gravity);
+
+            // Get Floating Point data from FIFO
+            uint8_t dmpGetAccelFloat(float *data, const uint8_t* packet=0);
+            uint8_t dmpGetQuaternionFloat(float *data, const uint8_t* packet=0);
+
+            uint8_t dmpProcessFIFOPacket(const unsigned char *dmpData);
+            uint8_t dmpReadAndProcessFIFOPacket(uint8_t numPackets, uint8_t *processed=NULL);
+
+            uint8_t dmpSetFIFOProcessedCallback(void (*func) (void));
+
+            uint8_t dmpInitFIFOParam();
+            uint8_t dmpCloseFIFO();
+            uint8_t dmpSetGyroDataSource(uint8_t source);
+            uint8_t dmpDecodeQuantizedAccel();
+            uint32_t dmpGetGyroSumOfSquare();
+            uint32_t dmpGetAccelSumOfSquare();
+            void dmpOverrideQuaternion(long *q);
+            uint16_t dmpGetFIFOPacketSize();
+        #endif
+
+    private:
+        uint8_t devAddr;
+        uint8_t buffer[14];
+};
+
+#endif /* _MPU6050_H_ */
diff --git a/hardware/digistump/sam/libraries/MPU6050/MPU6050_6Axis_MotionApps20.h b/hardware/digistump/sam/libraries/MPU6050/MPU6050_6Axis_MotionApps20.h
new file mode 100644
index 0000000..1e86cc4
--- /dev/null
+++ b/hardware/digistump/sam/libraries/MPU6050/MPU6050_6Axis_MotionApps20.h
@@ -0,0 +1,697 @@
+// I2Cdev library collection - MPU6050 I2C device class, 6-axis MotionApps 2.0 implementation
+// Based on InvenSense MPU-6050 register map document rev. 2.0, 5/19/2011 (RM-MPU-6000A-00)
+// 5/20/2013 by Jeff Rowberg 
+// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib
+//
+// Changelog:
+//     ... - ongoing debug release
+
+/* ============================================
+I2Cdev device library code is placed under the MIT license
+Copyright (c) 2012 Jeff Rowberg
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+===============================================
+*/
+
+#ifndef _MPU6050_6AXIS_MOTIONAPPS20_H_
+#define _MPU6050_6AXIS_MOTIONAPPS20_H_
+
+#include "I2Cdev.h"
+#include "helper_3dmath.h"
+
+// MotionApps 2.0 DMP implementation, built using the MPU-6050EVB evaluation board
+#define MPU6050_INCLUDE_DMP_MOTIONAPPS20
+
+#include "MPU6050.h"
+#include 
+
+/* Source is from the InvenSense MotionApps v2 demo code. Original source is
+ * unavailable, unless you happen to be amazing as decompiling binary by
+ * hand (in which case, please contact me, and I'm totally serious).
+ *
+ * Also, I'd like to offer many, many thanks to Noah Zerkin for all of the
+ * DMP reverse-engineering he did to help make this bit of wizardry
+ * possible.
+ */
+
+// NOTE! Enabling DEBUG adds about 3.3kB to the flash program size.
+// Debug output is now working even on ATMega328P MCUs (e.g. Arduino Uno)
+// after moving string constants to flash memory storage using the F()
+// compiler macro (Arduino IDE 1.0+ required).
+
+//#define DEBUG
+#ifdef DEBUG
+    #define DEBUG_PRINT(x) Serial.print(x)
+    #define DEBUG_PRINTF(x, y) Serial.print(x, y)
+    #define DEBUG_PRINTLN(x) Serial.println(x)
+    #define DEBUG_PRINTLNF(x, y) Serial.println(x, y)
+#else
+    #define DEBUG_PRINT(x)
+    #define DEBUG_PRINTF(x, y)
+    #define DEBUG_PRINTLN(x)
+    #define DEBUG_PRINTLNF(x, y)
+#endif
+
+#define MPU6050_DMP_CODE_SIZE       1929    // dmpMemory[]
+#define MPU6050_DMP_CONFIG_SIZE     192     // dmpConfig[]
+#define MPU6050_DMP_UPDATES_SIZE    47      // dmpUpdates[]
+
+/* ================================================================================================ *
+ | Default MotionApps v2.0 42-byte FIFO packet structure:                                           |
+ |                                                                                                  |
+ | [QUAT W][      ][QUAT X][      ][QUAT Y][      ][QUAT Z][      ][GYRO X][      ][GYRO Y][      ] |
+ |   0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  |
+ |                                                                                                  |
+ | [GYRO Z][      ][ACC X ][      ][ACC Y ][      ][ACC Z ][      ][      ]                         |
+ |  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41                          |
+ * ================================================================================================ */
+
+// this block of memory gets written to the MPU on start-up, and it seems
+// to be volatile memory, so it has to be done each time (it only takes ~1
+// second though)
+const unsigned char dmpMemory[MPU6050_DMP_CODE_SIZE] PROGMEM = {
+    // bank 0, 256 bytes
+    0xFB, 0x00, 0x00, 0x3E, 0x00, 0x0B, 0x00, 0x36, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x00,
+    0x00, 0x65, 0x00, 0x54, 0xFF, 0xEF, 0x00, 0x00, 0xFA, 0x80, 0x00, 0x0B, 0x12, 0x82, 0x00, 0x01,
+    0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x28, 0x00, 0x00, 0xFF, 0xFF, 0x45, 0x81, 0xFF, 0xFF, 0xFA, 0x72, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x03, 0xE8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x7F, 0xFF, 0xFF, 0xFE, 0x80, 0x01,
+    0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x3E, 0x03, 0x30, 0x40, 0x00, 0x00, 0x00, 0x02, 0xCA, 0xE3, 0x09, 0x3E, 0x80, 0x00, 0x00,
+    0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00,
+    0x41, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x2A, 0x00, 0x00, 0x16, 0x55, 0x00, 0x00, 0x21, 0x82,
+    0xFD, 0x87, 0x26, 0x50, 0xFD, 0x80, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x05, 0x80, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
+    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x6F, 0x00, 0x02, 0x65, 0x32, 0x00, 0x00, 0x5E, 0xC0,
+    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0xFB, 0x8C, 0x6F, 0x5D, 0xFD, 0x5D, 0x08, 0xD9, 0x00, 0x7C, 0x73, 0x3B, 0x00, 0x6C, 0x12, 0xCC,
+    0x32, 0x00, 0x13, 0x9D, 0x32, 0x00, 0xD0, 0xD6, 0x32, 0x00, 0x08, 0x00, 0x40, 0x00, 0x01, 0xF4,
+    0xFF, 0xE6, 0x80, 0x79, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD0, 0xD6, 0x00, 0x00, 0x27, 0x10,
+
+    // bank 1, 256 bytes
+    0xFB, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0xFA, 0x36, 0xFF, 0xBC, 0x30, 0x8E, 0x00, 0x05, 0xFB, 0xF0, 0xFF, 0xD9, 0x5B, 0xC8,
+    0xFF, 0xD0, 0x9A, 0xBE, 0x00, 0x00, 0x10, 0xA9, 0xFF, 0xF4, 0x1E, 0xB2, 0x00, 0xCE, 0xBB, 0xF7,
+    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x02, 0x00, 0x02, 0x02, 0x00, 0x00, 0x0C,
+    0xFF, 0xC2, 0x80, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0xCF, 0x80, 0x00, 0x40, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x14,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x03, 0x3F, 0x68, 0xB6, 0x79, 0x35, 0x28, 0xBC, 0xC6, 0x7E, 0xD1, 0x6C,
+    0x80, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB2, 0x6A, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xF0, 0x00, 0x00, 0x00, 0x30,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x25, 0x4D, 0x00, 0x2F, 0x70, 0x6D, 0x00, 0x00, 0x05, 0xAE, 0x00, 0x0C, 0x02, 0xD0,
+
+    // bank 2, 256 bytes
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x00, 0x54, 0xFF, 0xEF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x01, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x00, 0x00, 0x00, 0x54, 0x00, 0x00, 0xFF, 0xEF, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+    0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+    // bank 3, 256 bytes
+    0xD8, 0xDC, 0xBA, 0xA2, 0xF1, 0xDE, 0xB2, 0xB8, 0xB4, 0xA8, 0x81, 0x91, 0xF7, 0x4A, 0x90, 0x7F,
+    0x91, 0x6A, 0xF3, 0xF9, 0xDB, 0xA8, 0xF9, 0xB0, 0xBA, 0xA0, 0x80, 0xF2, 0xCE, 0x81, 0xF3, 0xC2,
+    0xF1, 0xC1, 0xF2, 0xC3, 0xF3, 0xCC, 0xA2, 0xB2, 0x80, 0xF1, 0xC6, 0xD8, 0x80, 0xBA, 0xA7, 0xDF,
+    0xDF, 0xDF, 0xF2, 0xA7, 0xC3, 0xCB, 0xC5, 0xB6, 0xF0, 0x87, 0xA2, 0x94, 0x24, 0x48, 0x70, 0x3C,
+    0x95, 0x40, 0x68, 0x34, 0x58, 0x9B, 0x78, 0xA2, 0xF1, 0x83, 0x92, 0x2D, 0x55, 0x7D, 0xD8, 0xB1,
+    0xB4, 0xB8, 0xA1, 0xD0, 0x91, 0x80, 0xF2, 0x70, 0xF3, 0x70, 0xF2, 0x7C, 0x80, 0xA8, 0xF1, 0x01,
+    0xB0, 0x98, 0x87, 0xD9, 0x43, 0xD8, 0x86, 0xC9, 0x88, 0xBA, 0xA1, 0xF2, 0x0E, 0xB8, 0x97, 0x80,
+    0xF1, 0xA9, 0xDF, 0xDF, 0xDF, 0xAA, 0xDF, 0xDF, 0xDF, 0xF2, 0xAA, 0xC5, 0xCD, 0xC7, 0xA9, 0x0C,
+    0xC9, 0x2C, 0x97, 0x97, 0x97, 0x97, 0xF1, 0xA9, 0x89, 0x26, 0x46, 0x66, 0xB0, 0xB4, 0xBA, 0x80,
+    0xAC, 0xDE, 0xF2, 0xCA, 0xF1, 0xB2, 0x8C, 0x02, 0xA9, 0xB6, 0x98, 0x00, 0x89, 0x0E, 0x16, 0x1E,
+    0xB8, 0xA9, 0xB4, 0x99, 0x2C, 0x54, 0x7C, 0xB0, 0x8A, 0xA8, 0x96, 0x36, 0x56, 0x76, 0xF1, 0xB9,
+    0xAF, 0xB4, 0xB0, 0x83, 0xC0, 0xB8, 0xA8, 0x97, 0x11, 0xB1, 0x8F, 0x98, 0xB9, 0xAF, 0xF0, 0x24,
+    0x08, 0x44, 0x10, 0x64, 0x18, 0xF1, 0xA3, 0x29, 0x55, 0x7D, 0xAF, 0x83, 0xB5, 0x93, 0xAF, 0xF0,
+    0x00, 0x28, 0x50, 0xF1, 0xA3, 0x86, 0x9F, 0x61, 0xA6, 0xDA, 0xDE, 0xDF, 0xD9, 0xFA, 0xA3, 0x86,
+    0x96, 0xDB, 0x31, 0xA6, 0xD9, 0xF8, 0xDF, 0xBA, 0xA6, 0x8F, 0xC2, 0xC5, 0xC7, 0xB2, 0x8C, 0xC1,
+    0xB8, 0xA2, 0xDF, 0xDF, 0xDF, 0xA3, 0xDF, 0xDF, 0xDF, 0xD8, 0xD8, 0xF1, 0xB8, 0xA8, 0xB2, 0x86,
+
+    // bank 4, 256 bytes
+    0xB4, 0x98, 0x0D, 0x35, 0x5D, 0xB8, 0xAA, 0x98, 0xB0, 0x87, 0x2D, 0x35, 0x3D, 0xB2, 0xB6, 0xBA,
+    0xAF, 0x8C, 0x96, 0x19, 0x8F, 0x9F, 0xA7, 0x0E, 0x16, 0x1E, 0xB4, 0x9A, 0xB8, 0xAA, 0x87, 0x2C,
+    0x54, 0x7C, 0xB9, 0xA3, 0xDE, 0xDF, 0xDF, 0xA3, 0xB1, 0x80, 0xF2, 0xC4, 0xCD, 0xC9, 0xF1, 0xB8,
+    0xA9, 0xB4, 0x99, 0x83, 0x0D, 0x35, 0x5D, 0x89, 0xB9, 0xA3, 0x2D, 0x55, 0x7D, 0xB5, 0x93, 0xA3,
+    0x0E, 0x16, 0x1E, 0xA9, 0x2C, 0x54, 0x7C, 0xB8, 0xB4, 0xB0, 0xF1, 0x97, 0x83, 0xA8, 0x11, 0x84,
+    0xA5, 0x09, 0x98, 0xA3, 0x83, 0xF0, 0xDA, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0xD8, 0xF1, 0xA5,
+    0x29, 0x55, 0x7D, 0xA5, 0x85, 0x95, 0x02, 0x1A, 0x2E, 0x3A, 0x56, 0x5A, 0x40, 0x48, 0xF9, 0xF3,
+    0xA3, 0xD9, 0xF8, 0xF0, 0x98, 0x83, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0x97, 0x82, 0xA8, 0xF1,
+    0x11, 0xF0, 0x98, 0xA2, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0xDA, 0xF3, 0xDE, 0xD8, 0x83, 0xA5,
+    0x94, 0x01, 0xD9, 0xA3, 0x02, 0xF1, 0xA2, 0xC3, 0xC5, 0xC7, 0xD8, 0xF1, 0x84, 0x92, 0xA2, 0x4D,
+    0xDA, 0x2A, 0xD8, 0x48, 0x69, 0xD9, 0x2A, 0xD8, 0x68, 0x55, 0xDA, 0x32, 0xD8, 0x50, 0x71, 0xD9,
+    0x32, 0xD8, 0x70, 0x5D, 0xDA, 0x3A, 0xD8, 0x58, 0x79, 0xD9, 0x3A, 0xD8, 0x78, 0x93, 0xA3, 0x4D,
+    0xDA, 0x2A, 0xD8, 0x48, 0x69, 0xD9, 0x2A, 0xD8, 0x68, 0x55, 0xDA, 0x32, 0xD8, 0x50, 0x71, 0xD9,
+    0x32, 0xD8, 0x70, 0x5D, 0xDA, 0x3A, 0xD8, 0x58, 0x79, 0xD9, 0x3A, 0xD8, 0x78, 0xA8, 0x8A, 0x9A,
+    0xF0, 0x28, 0x50, 0x78, 0x9E, 0xF3, 0x88, 0x18, 0xF1, 0x9F, 0x1D, 0x98, 0xA8, 0xD9, 0x08, 0xD8,
+    0xC8, 0x9F, 0x12, 0x9E, 0xF3, 0x15, 0xA8, 0xDA, 0x12, 0x10, 0xD8, 0xF1, 0xAF, 0xC8, 0x97, 0x87,
+
+    // bank 5, 256 bytes
+    0x34, 0xB5, 0xB9, 0x94, 0xA4, 0x21, 0xF3, 0xD9, 0x22, 0xD8, 0xF2, 0x2D, 0xF3, 0xD9, 0x2A, 0xD8,
+    0xF2, 0x35, 0xF3, 0xD9, 0x32, 0xD8, 0x81, 0xA4, 0x60, 0x60, 0x61, 0xD9, 0x61, 0xD8, 0x6C, 0x68,
+    0x69, 0xD9, 0x69, 0xD8, 0x74, 0x70, 0x71, 0xD9, 0x71, 0xD8, 0xB1, 0xA3, 0x84, 0x19, 0x3D, 0x5D,
+    0xA3, 0x83, 0x1A, 0x3E, 0x5E, 0x93, 0x10, 0x30, 0x81, 0x10, 0x11, 0xB8, 0xB0, 0xAF, 0x8F, 0x94,
+    0xF2, 0xDA, 0x3E, 0xD8, 0xB4, 0x9A, 0xA8, 0x87, 0x29, 0xDA, 0xF8, 0xD8, 0x87, 0x9A, 0x35, 0xDA,
+    0xF8, 0xD8, 0x87, 0x9A, 0x3D, 0xDA, 0xF8, 0xD8, 0xB1, 0xB9, 0xA4, 0x98, 0x85, 0x02, 0x2E, 0x56,
+    0xA5, 0x81, 0x00, 0x0C, 0x14, 0xA3, 0x97, 0xB0, 0x8A, 0xF1, 0x2D, 0xD9, 0x28, 0xD8, 0x4D, 0xD9,
+    0x48, 0xD8, 0x6D, 0xD9, 0x68, 0xD8, 0xB1, 0x84, 0x0D, 0xDA, 0x0E, 0xD8, 0xA3, 0x29, 0x83, 0xDA,
+    0x2C, 0x0E, 0xD8, 0xA3, 0x84, 0x49, 0x83, 0xDA, 0x2C, 0x4C, 0x0E, 0xD8, 0xB8, 0xB0, 0xA8, 0x8A,
+    0x9A, 0xF5, 0x20, 0xAA, 0xDA, 0xDF, 0xD8, 0xA8, 0x40, 0xAA, 0xD0, 0xDA, 0xDE, 0xD8, 0xA8, 0x60,
+    0xAA, 0xDA, 0xD0, 0xDF, 0xD8, 0xF1, 0x97, 0x86, 0xA8, 0x31, 0x9B, 0x06, 0x99, 0x07, 0xAB, 0x97,
+    0x28, 0x88, 0x9B, 0xF0, 0x0C, 0x20, 0x14, 0x40, 0xB8, 0xB0, 0xB4, 0xA8, 0x8C, 0x9C, 0xF0, 0x04,
+    0x28, 0x51, 0x79, 0x1D, 0x30, 0x14, 0x38, 0xB2, 0x82, 0xAB, 0xD0, 0x98, 0x2C, 0x50, 0x50, 0x78,
+    0x78, 0x9B, 0xF1, 0x1A, 0xB0, 0xF0, 0x8A, 0x9C, 0xA8, 0x29, 0x51, 0x79, 0x8B, 0x29, 0x51, 0x79,
+    0x8A, 0x24, 0x70, 0x59, 0x8B, 0x20, 0x58, 0x71, 0x8A, 0x44, 0x69, 0x38, 0x8B, 0x39, 0x40, 0x68,
+    0x8A, 0x64, 0x48, 0x31, 0x8B, 0x30, 0x49, 0x60, 0xA5, 0x88, 0x20, 0x09, 0x71, 0x58, 0x44, 0x68,
+
+    // bank 6, 256 bytes
+    0x11, 0x39, 0x64, 0x49, 0x30, 0x19, 0xF1, 0xAC, 0x00, 0x2C, 0x54, 0x7C, 0xF0, 0x8C, 0xA8, 0x04,
+    0x28, 0x50, 0x78, 0xF1, 0x88, 0x97, 0x26, 0xA8, 0x59, 0x98, 0xAC, 0x8C, 0x02, 0x26, 0x46, 0x66,
+    0xF0, 0x89, 0x9C, 0xA8, 0x29, 0x51, 0x79, 0x24, 0x70, 0x59, 0x44, 0x69, 0x38, 0x64, 0x48, 0x31,
+    0xA9, 0x88, 0x09, 0x20, 0x59, 0x70, 0xAB, 0x11, 0x38, 0x40, 0x69, 0xA8, 0x19, 0x31, 0x48, 0x60,
+    0x8C, 0xA8, 0x3C, 0x41, 0x5C, 0x20, 0x7C, 0x00, 0xF1, 0x87, 0x98, 0x19, 0x86, 0xA8, 0x6E, 0x76,
+    0x7E, 0xA9, 0x99, 0x88, 0x2D, 0x55, 0x7D, 0x9E, 0xB9, 0xA3, 0x8A, 0x22, 0x8A, 0x6E, 0x8A, 0x56,
+    0x8A, 0x5E, 0x9F, 0xB1, 0x83, 0x06, 0x26, 0x46, 0x66, 0x0E, 0x2E, 0x4E, 0x6E, 0x9D, 0xB8, 0xAD,
+    0x00, 0x2C, 0x54, 0x7C, 0xF2, 0xB1, 0x8C, 0xB4, 0x99, 0xB9, 0xA3, 0x2D, 0x55, 0x7D, 0x81, 0x91,
+    0xAC, 0x38, 0xAD, 0x3A, 0xB5, 0x83, 0x91, 0xAC, 0x2D, 0xD9, 0x28, 0xD8, 0x4D, 0xD9, 0x48, 0xD8,
+    0x6D, 0xD9, 0x68, 0xD8, 0x8C, 0x9D, 0xAE, 0x29, 0xD9, 0x04, 0xAE, 0xD8, 0x51, 0xD9, 0x04, 0xAE,
+    0xD8, 0x79, 0xD9, 0x04, 0xD8, 0x81, 0xF3, 0x9D, 0xAD, 0x00, 0x8D, 0xAE, 0x19, 0x81, 0xAD, 0xD9,
+    0x01, 0xD8, 0xF2, 0xAE, 0xDA, 0x26, 0xD8, 0x8E, 0x91, 0x29, 0x83, 0xA7, 0xD9, 0xAD, 0xAD, 0xAD,
+    0xAD, 0xF3, 0x2A, 0xD8, 0xD8, 0xF1, 0xB0, 0xAC, 0x89, 0x91, 0x3E, 0x5E, 0x76, 0xF3, 0xAC, 0x2E,
+    0x2E, 0xF1, 0xB1, 0x8C, 0x5A, 0x9C, 0xAC, 0x2C, 0x28, 0x28, 0x28, 0x9C, 0xAC, 0x30, 0x18, 0xA8,
+    0x98, 0x81, 0x28, 0x34, 0x3C, 0x97, 0x24, 0xA7, 0x28, 0x34, 0x3C, 0x9C, 0x24, 0xF2, 0xB0, 0x89,
+    0xAC, 0x91, 0x2C, 0x4C, 0x6C, 0x8A, 0x9B, 0x2D, 0xD9, 0xD8, 0xD8, 0x51, 0xD9, 0xD8, 0xD8, 0x79,
+
+    // bank 7, 138 bytes (remainder)
+    0xD9, 0xD8, 0xD8, 0xF1, 0x9E, 0x88, 0xA3, 0x31, 0xDA, 0xD8, 0xD8, 0x91, 0x2D, 0xD9, 0x28, 0xD8,
+    0x4D, 0xD9, 0x48, 0xD8, 0x6D, 0xD9, 0x68, 0xD8, 0xB1, 0x83, 0x93, 0x35, 0x3D, 0x80, 0x25, 0xDA,
+    0xD8, 0xD8, 0x85, 0x69, 0xDA, 0xD8, 0xD8, 0xB4, 0x93, 0x81, 0xA3, 0x28, 0x34, 0x3C, 0xF3, 0xAB,
+    0x8B, 0xF8, 0xA3, 0x91, 0xB6, 0x09, 0xB4, 0xD9, 0xAB, 0xDE, 0xFA, 0xB0, 0x87, 0x9C, 0xB9, 0xA3,
+    0xDD, 0xF1, 0xA3, 0xA3, 0xA3, 0xA3, 0x95, 0xF1, 0xA3, 0xA3, 0xA3, 0x9D, 0xF1, 0xA3, 0xA3, 0xA3,
+    0xA3, 0xF2, 0xA3, 0xB4, 0x90, 0x80, 0xF2, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3,
+    0xA3, 0xB2, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xB0, 0x87, 0xB5, 0x99, 0xF1, 0xA3, 0xA3, 0xA3,
+    0x98, 0xF1, 0xA3, 0xA3, 0xA3, 0xA3, 0x97, 0xA3, 0xA3, 0xA3, 0xA3, 0xF3, 0x9B, 0xA3, 0xA3, 0xDC,
+    0xB9, 0xA7, 0xF1, 0x26, 0x26, 0x26, 0xD8, 0xD8, 0xFF
+};
+
+// thanks to Noah Zerkin for piecing this stuff together!
+const unsigned char dmpConfig[MPU6050_DMP_CONFIG_SIZE] PROGMEM = {
+//  BANK    OFFSET  LENGTH  [DATA]
+    0x03,   0x7B,   0x03,   0x4C, 0xCD, 0x6C,         // FCFG_1 inv_set_gyro_calibration
+    0x03,   0xAB,   0x03,   0x36, 0x56, 0x76,         // FCFG_3 inv_set_gyro_calibration
+    0x00,   0x68,   0x04,   0x02, 0xCB, 0x47, 0xA2,   // D_0_104 inv_set_gyro_calibration
+    0x02,   0x18,   0x04,   0x00, 0x05, 0x8B, 0xC1,   // D_0_24 inv_set_gyro_calibration
+    0x01,   0x0C,   0x04,   0x00, 0x00, 0x00, 0x00,   // D_1_152 inv_set_accel_calibration
+    0x03,   0x7F,   0x06,   0x0C, 0xC9, 0x2C, 0x97, 0x97, 0x97, // FCFG_2 inv_set_accel_calibration
+    0x03,   0x89,   0x03,   0x26, 0x46, 0x66,         // FCFG_7 inv_set_accel_calibration
+    0x00,   0x6C,   0x02,   0x20, 0x00,               // D_0_108 inv_set_accel_calibration
+    0x02,   0x40,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_00 inv_set_compass_calibration
+    0x02,   0x44,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_01
+    0x02,   0x48,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_02
+    0x02,   0x4C,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_10
+    0x02,   0x50,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_11
+    0x02,   0x54,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_12
+    0x02,   0x58,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_20
+    0x02,   0x5C,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_21
+    0x02,   0xBC,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_22
+    0x01,   0xEC,   0x04,   0x00, 0x00, 0x40, 0x00,   // D_1_236 inv_apply_endian_accel
+    0x03,   0x7F,   0x06,   0x0C, 0xC9, 0x2C, 0x97, 0x97, 0x97, // FCFG_2 inv_set_mpu_sensors
+    0x04,   0x02,   0x03,   0x0D, 0x35, 0x5D,         // CFG_MOTION_BIAS inv_turn_on_bias_from_no_motion
+    0x04,   0x09,   0x04,   0x87, 0x2D, 0x35, 0x3D,   // FCFG_5 inv_set_bias_update
+    0x00,   0xA3,   0x01,   0x00,                     // D_0_163 inv_set_dead_zone
+                 // SPECIAL 0x01 = enable interrupts
+    0x00,   0x00,   0x00,   0x01, // SET INT_ENABLE at i=22, SPECIAL INSTRUCTION
+    0x07,   0x86,   0x01,   0xFE,                     // CFG_6 inv_set_fifo_interupt
+    0x07,   0x41,   0x05,   0xF1, 0x20, 0x28, 0x30, 0x38, // CFG_8 inv_send_quaternion
+    0x07,   0x7E,   0x01,   0x30,                     // CFG_16 inv_set_footer
+    0x07,   0x46,   0x01,   0x9A,                     // CFG_GYRO_SOURCE inv_send_gyro
+    0x07,   0x47,   0x04,   0xF1, 0x28, 0x30, 0x38,   // CFG_9 inv_send_gyro -> inv_construct3_fifo
+    0x07,   0x6C,   0x04,   0xF1, 0x28, 0x30, 0x38,   // CFG_12 inv_send_accel -> inv_construct3_fifo
+    0x02,   0x16,   0x02,   0x00, 0x01                // D_0_22 inv_set_fifo_rate
+
+    // This very last 0x01 WAS a 0x09, which drops the FIFO rate down to 20 Hz. 0x07 is 25 Hz,
+    // 0x01 is 100Hz. Going faster than 100Hz (0x00=200Hz) tends to result in very noisy data.
+    // DMP output frequency is calculated easily using this equation: (200Hz / (1 + value))
+
+    // It is important to make sure the host processor can keep up with reading and processing
+    // the FIFO output at the desired rate. Handling FIFO overflow cleanly is also a good idea.
+};
+
+const unsigned char dmpUpdates[MPU6050_DMP_UPDATES_SIZE] PROGMEM = {
+    0x01,   0xB2,   0x02,   0xFF, 0xFF,
+    0x01,   0x90,   0x04,   0x09, 0x23, 0xA1, 0x35,
+    0x01,   0x6A,   0x02,   0x06, 0x00,
+    0x01,   0x60,   0x08,   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00,   0x60,   0x04,   0x40, 0x00, 0x00, 0x00,
+    0x01,   0x62,   0x02,   0x00, 0x00,
+    0x00,   0x60,   0x04,   0x00, 0x40, 0x00, 0x00
+};
+
+uint8_t MPU6050::dmpInitialize() {
+    // reset device
+    DEBUG_PRINTLN(F("\n\nResetting MPU6050..."));
+    reset();
+    delay(30); // wait after reset
+
+    // enable sleep mode and wake cycle
+    /*Serial.println(F("Enabling sleep mode..."));
+    setSleepEnabled(true);
+    Serial.println(F("Enabling wake cycle..."));
+    setWakeCycleEnabled(true);*/
+
+    // disable sleep mode
+    DEBUG_PRINTLN(F("Disabling sleep mode..."));
+    setSleepEnabled(false);
+
+    // get MPU hardware revision
+    DEBUG_PRINTLN(F("Selecting user bank 16..."));
+    setMemoryBank(0x10, true, true);
+    DEBUG_PRINTLN(F("Selecting memory byte 6..."));
+    setMemoryStartAddress(0x06);
+    DEBUG_PRINTLN(F("Checking hardware revision..."));
+    uint8_t hwRevision = readMemoryByte();
+    DEBUG_PRINT(F("Revision @ user[16][6] = "));
+    DEBUG_PRINTLNF(hwRevision, HEX);
+    DEBUG_PRINTLN(F("Resetting memory bank selection to 0..."));
+    setMemoryBank(0, false, false);
+
+    // check OTP bank valid
+    DEBUG_PRINTLN(F("Reading OTP bank valid flag..."));
+    uint8_t otpValid = getOTPBankValid();
+    DEBUG_PRINT(F("OTP bank is "));
+    DEBUG_PRINTLN(otpValid ? F("valid!") : F("invalid!"));
+
+    // get X/Y/Z gyro offsets
+    DEBUG_PRINTLN(F("Reading gyro offset TC values..."));
+    int8_t xgOffsetTC = getXGyroOffsetTC();
+    int8_t ygOffsetTC = getYGyroOffsetTC();
+    int8_t zgOffsetTC = getZGyroOffsetTC();
+    DEBUG_PRINT(F("X gyro offset = "));
+    DEBUG_PRINTLN(xgOffset);
+    DEBUG_PRINT(F("Y gyro offset = "));
+    DEBUG_PRINTLN(ygOffset);
+    DEBUG_PRINT(F("Z gyro offset = "));
+    DEBUG_PRINTLN(zgOffset);
+
+    // setup weird slave stuff (?)
+    DEBUG_PRINTLN(F("Setting slave 0 address to 0x7F..."));
+    setSlaveAddress(0, 0x7F);
+    DEBUG_PRINTLN(F("Disabling I2C Master mode..."));
+    setI2CMasterModeEnabled(false);
+    DEBUG_PRINTLN(F("Setting slave 0 address to 0x68 (self)..."));
+    setSlaveAddress(0, 0x68);
+    DEBUG_PRINTLN(F("Resetting I2C Master control..."));
+    resetI2CMaster();
+    delay(20);
+
+    // load DMP code into memory banks
+    DEBUG_PRINT(F("Writing DMP code to MPU memory banks ("));
+    DEBUG_PRINT(MPU6050_DMP_CODE_SIZE);
+    DEBUG_PRINTLN(F(" bytes)"));
+    if (writeProgMemoryBlock(dmpMemory, MPU6050_DMP_CODE_SIZE)) {
+        DEBUG_PRINTLN(F("Success! DMP code written and verified."));
+
+        // write DMP configuration
+        DEBUG_PRINT(F("Writing DMP configuration to MPU memory banks ("));
+        DEBUG_PRINT(MPU6050_DMP_CONFIG_SIZE);
+        DEBUG_PRINTLN(F(" bytes in config def)"));
+        if (writeProgDMPConfigurationSet(dmpConfig, MPU6050_DMP_CONFIG_SIZE)) {
+            DEBUG_PRINTLN(F("Success! DMP configuration written and verified."));
+
+            DEBUG_PRINTLN(F("Setting clock source to Z Gyro..."));
+            setClockSource(MPU6050_CLOCK_PLL_ZGYRO);
+
+            DEBUG_PRINTLN(F("Setting DMP and FIFO_OFLOW interrupts enabled..."));
+            setIntEnabled(0x12);
+
+            DEBUG_PRINTLN(F("Setting sample rate to 200Hz..."));
+            setRate(4); // 1khz / (1 + 4) = 200 Hz
+
+            DEBUG_PRINTLN(F("Setting external frame sync to TEMP_OUT_L[0]..."));
+            setExternalFrameSync(MPU6050_EXT_SYNC_TEMP_OUT_L);
+
+            DEBUG_PRINTLN(F("Setting DLPF bandwidth to 42Hz..."));
+            setDLPFMode(MPU6050_DLPF_BW_42);
+
+            DEBUG_PRINTLN(F("Setting gyro sensitivity to +/- 2000 deg/sec..."));
+            setFullScaleGyroRange(MPU6050_GYRO_FS_2000);
+
+            DEBUG_PRINTLN(F("Setting DMP configuration bytes (function unknown)..."));
+            setDMPConfig1(0x03);
+            setDMPConfig2(0x00);
+
+            DEBUG_PRINTLN(F("Clearing OTP Bank flag..."));
+            setOTPBankValid(false);
+
+            DEBUG_PRINTLN(F("Setting X/Y/Z gyro offset TCs to previous values..."));
+            setXGyroOffsetTC(xgOffsetTC);
+            setYGyroOffsetTC(ygOffsetTC);
+            setZGyroOffsetTC(zgOffsetTC);
+
+            //DEBUG_PRINTLN(F("Setting X/Y/Z gyro user offsets to zero..."));
+            //setXGyroOffset(0);
+            //setYGyroOffset(0);
+            //setZGyroOffset(0);
+
+            DEBUG_PRINTLN(F("Writing final memory update 1/7 (function unknown)..."));
+            uint8_t dmpUpdate[16], j;
+            uint16_t pos = 0;
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("Writing final memory update 2/7 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("Resetting FIFO..."));
+            resetFIFO();
+
+            DEBUG_PRINTLN(F("Reading FIFO count..."));
+            uint16_t fifoCount = getFIFOCount();
+            uint8_t fifoBuffer[128];
+
+            DEBUG_PRINT(F("Current FIFO count="));
+            DEBUG_PRINTLN(fifoCount);
+            getFIFOBytes(fifoBuffer, fifoCount);
+
+            DEBUG_PRINTLN(F("Setting motion detection threshold to 2..."));
+            setMotionDetectionThreshold(2);
+
+            DEBUG_PRINTLN(F("Setting zero-motion detection threshold to 156..."));
+            setZeroMotionDetectionThreshold(156);
+
+            DEBUG_PRINTLN(F("Setting motion detection duration to 80..."));
+            setMotionDetectionDuration(80);
+
+            DEBUG_PRINTLN(F("Setting zero-motion detection duration to 0..."));
+            setZeroMotionDetectionDuration(0);
+
+            DEBUG_PRINTLN(F("Resetting FIFO..."));
+            resetFIFO();
+
+            DEBUG_PRINTLN(F("Enabling FIFO..."));
+            setFIFOEnabled(true);
+
+            DEBUG_PRINTLN(F("Enabling DMP..."));
+            setDMPEnabled(true);
+
+            DEBUG_PRINTLN(F("Resetting DMP..."));
+            resetDMP();
+
+            DEBUG_PRINTLN(F("Writing final memory update 3/7 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("Writing final memory update 4/7 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("Writing final memory update 5/7 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("Waiting for FIFO count > 2..."));
+            while ((fifoCount = getFIFOCount()) < 3);
+
+            DEBUG_PRINT(F("Current FIFO count="));
+            DEBUG_PRINTLN(fifoCount);
+            DEBUG_PRINTLN(F("Reading FIFO data..."));
+            getFIFOBytes(fifoBuffer, fifoCount);
+
+            DEBUG_PRINTLN(F("Reading interrupt status..."));
+            uint8_t mpuIntStatus = getIntStatus();
+
+            DEBUG_PRINT(F("Current interrupt status="));
+            DEBUG_PRINTLNF(mpuIntStatus, HEX);
+
+            DEBUG_PRINTLN(F("Reading final memory update 6/7 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            readMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("Waiting for FIFO count > 2..."));
+            while ((fifoCount = getFIFOCount()) < 3);
+
+            DEBUG_PRINT(F("Current FIFO count="));
+            DEBUG_PRINTLN(fifoCount);
+
+            DEBUG_PRINTLN(F("Reading FIFO data..."));
+            getFIFOBytes(fifoBuffer, fifoCount);
+
+            DEBUG_PRINTLN(F("Reading interrupt status..."));
+            mpuIntStatus = getIntStatus();
+
+            DEBUG_PRINT(F("Current interrupt status="));
+            DEBUG_PRINTLNF(mpuIntStatus, HEX);
+
+            DEBUG_PRINTLN(F("Writing final memory update 7/7 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("DMP is good to go! Finally."));
+
+            DEBUG_PRINTLN(F("Disabling DMP (you turn it on later)..."));
+            setDMPEnabled(false);
+
+            DEBUG_PRINTLN(F("Setting up internal 42-byte (default) DMP packet buffer..."));
+            dmpPacketSize = 42;
+            /*if ((dmpPacketBuffer = (uint8_t *)malloc(42)) == 0) {
+                return 3; // TODO: proper error code for no memory
+            }*/
+
+            DEBUG_PRINTLN(F("Resetting FIFO and clearing INT status one last time..."));
+            resetFIFO();
+            getIntStatus();
+        } else {
+            DEBUG_PRINTLN(F("ERROR! DMP configuration verification failed."));
+            return 2; // configuration block loading failed
+        }
+    } else {
+        DEBUG_PRINTLN(F("ERROR! DMP code verification failed."));
+        return 1; // main binary block loading failed
+    }
+    return 0; // success
+}
+
+bool MPU6050::dmpPacketAvailable() {
+    return getFIFOCount() >= dmpGetFIFOPacketSize();
+}
+
+// uint8_t MPU6050::dmpSetFIFORate(uint8_t fifoRate);
+// uint8_t MPU6050::dmpGetFIFORate();
+// uint8_t MPU6050::dmpGetSampleStepSizeMS();
+// uint8_t MPU6050::dmpGetSampleFrequency();
+// int32_t MPU6050::dmpDecodeTemperature(int8_t tempReg);
+
+//uint8_t MPU6050::dmpRegisterFIFORateProcess(inv_obj_func func, int16_t priority);
+//uint8_t MPU6050::dmpUnregisterFIFORateProcess(inv_obj_func func);
+//uint8_t MPU6050::dmpRunFIFORateProcesses();
+
+// uint8_t MPU6050::dmpSendQuaternion(uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendGyro(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendAccel(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendLinearAccel(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendLinearAccelInWorld(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendControlData(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendSensorData(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendExternalSensorData(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendGravity(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendPacketNumber(uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendQuantizedAccel(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendEIS(uint_fast16_t elements, uint_fast16_t accuracy);
+
+uint8_t MPU6050::dmpGetAccel(int32_t *data, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    data[0] = ((packet[28] << 24) + (packet[29] << 16) + (packet[30] << 8) + packet[31]);
+    data[1] = ((packet[32] << 24) + (packet[33] << 16) + (packet[34] << 8) + packet[35]);
+    data[2] = ((packet[36] << 24) + (packet[37] << 16) + (packet[38] << 8) + packet[39]);
+    return 0;
+}
+uint8_t MPU6050::dmpGetAccel(int16_t *data, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    data[0] = (packet[28] << 8) + packet[29];
+    data[1] = (packet[32] << 8) + packet[33];
+    data[2] = (packet[36] << 8) + packet[37];
+    return 0;
+}
+uint8_t MPU6050::dmpGetAccel(VectorInt16 *v, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    v -> x = (packet[28] << 8) + packet[29];
+    v -> y = (packet[32] << 8) + packet[33];
+    v -> z = (packet[36] << 8) + packet[37];
+    return 0;
+}
+uint8_t MPU6050::dmpGetQuaternion(int32_t *data, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    data[0] = ((packet[0] << 24) + (packet[1] << 16) + (packet[2] << 8) + packet[3]);
+    data[1] = ((packet[4] << 24) + (packet[5] << 16) + (packet[6] << 8) + packet[7]);
+    data[2] = ((packet[8] << 24) + (packet[9] << 16) + (packet[10] << 8) + packet[11]);
+    data[3] = ((packet[12] << 24) + (packet[13] << 16) + (packet[14] << 8) + packet[15]);
+    return 0;
+}
+uint8_t MPU6050::dmpGetQuaternion(int16_t *data, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    data[0] = ((packet[0] << 8) + packet[1]);
+    data[1] = ((packet[4] << 8) + packet[5]);
+    data[2] = ((packet[8] << 8) + packet[9]);
+    data[3] = ((packet[12] << 8) + packet[13]);
+    return 0;
+}
+uint8_t MPU6050::dmpGetQuaternion(Quaternion *q, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    int16_t qI[4];
+    uint8_t status = dmpGetQuaternion(qI, packet);
+    if (status == 0) {
+        q -> w = (float)qI[0] / 16384.0f;
+        q -> x = (float)qI[1] / 16384.0f;
+        q -> y = (float)qI[2] / 16384.0f;
+        q -> z = (float)qI[3] / 16384.0f;
+        return 0;
+    }
+    return status; // int16 return value, indicates error if this line is reached
+}
+// uint8_t MPU6050::dmpGet6AxisQuaternion(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetRelativeQuaternion(long *data, const uint8_t* packet);
+uint8_t MPU6050::dmpGetGyro(int32_t *data, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    data[0] = ((packet[16] << 24) + (packet[17] << 16) + (packet[18] << 8) + packet[19]);
+    data[1] = ((packet[20] << 24) + (packet[21] << 16) + (packet[22] << 8) + packet[23]);
+    data[2] = ((packet[24] << 24) + (packet[25] << 16) + (packet[26] << 8) + packet[27]);
+    return 0;
+}
+uint8_t MPU6050::dmpGetGyro(int16_t *data, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    data[0] = (packet[16] << 8) + packet[17];
+    data[1] = (packet[20] << 8) + packet[21];
+    data[2] = (packet[24] << 8) + packet[25];
+    return 0;
+}
+// uint8_t MPU6050::dmpSetLinearAccelFilterCoefficient(float coef);
+// uint8_t MPU6050::dmpGetLinearAccel(long *data, const uint8_t* packet);
+uint8_t MPU6050::dmpGetLinearAccel(VectorInt16 *v, VectorInt16 *vRaw, VectorFloat *gravity) {
+    // get rid of the gravity component (+1g = +8192 in standard DMP FIFO packet, sensitivity is 2g)
+    v -> x = vRaw -> x - gravity -> x*8192;
+    v -> y = vRaw -> y - gravity -> y*8192;
+    v -> z = vRaw -> z - gravity -> z*8192;
+    return 0;
+}
+// uint8_t MPU6050::dmpGetLinearAccelInWorld(long *data, const uint8_t* packet);
+uint8_t MPU6050::dmpGetLinearAccelInWorld(VectorInt16 *v, VectorInt16 *vReal, Quaternion *q) {
+    // rotate measured 3D acceleration vector into original state
+    // frame of reference based on orientation quaternion
+    memcpy(v, vReal, sizeof(VectorInt16));
+    v -> rotate(q);
+    return 0;
+}
+// uint8_t MPU6050::dmpGetGyroAndAccelSensor(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetGyroSensor(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetControlData(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetTemperature(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetGravity(long *data, const uint8_t* packet);
+uint8_t MPU6050::dmpGetGravity(VectorFloat *v, Quaternion *q) {
+    v -> x = 2 * (q -> x*q -> z - q -> w*q -> y);
+    v -> y = 2 * (q -> w*q -> x + q -> y*q -> z);
+    v -> z = q -> w*q -> w - q -> x*q -> x - q -> y*q -> y + q -> z*q -> z;
+    return 0;
+}
+// uint8_t MPU6050::dmpGetUnquantizedAccel(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetQuantizedAccel(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetExternalSensorData(long *data, int size, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetEIS(long *data, const uint8_t* packet);
+
+uint8_t MPU6050::dmpGetEuler(float *data, Quaternion *q) {
+    data[0] = atan2(2*q -> x*q -> y - 2*q -> w*q -> z, 2*q -> w*q -> w + 2*q -> x*q -> x - 1);   // psi
+    data[1] = -asin(2*q -> x*q -> z + 2*q -> w*q -> y);                              // theta
+    data[2] = atan2(2*q -> y*q -> z - 2*q -> w*q -> x, 2*q -> w*q -> w + 2*q -> z*q -> z - 1);   // phi
+    return 0;
+}
+uint8_t MPU6050::dmpGetYawPitchRoll(float *data, Quaternion *q, VectorFloat *gravity) {
+    // yaw: (about Z axis)
+    data[0] = atan2(2*q -> x*q -> y - 2*q -> w*q -> z, 2*q -> w*q -> w + 2*q -> x*q -> x - 1);
+    // pitch: (nose up/down, about Y axis)
+    data[1] = atan(gravity -> x / sqrt(gravity -> y*gravity -> y + gravity -> z*gravity -> z));
+    // roll: (tilt left/right, about X axis)
+    data[2] = atan(gravity -> y / sqrt(gravity -> x*gravity -> x + gravity -> z*gravity -> z));
+    return 0;
+}
+
+// uint8_t MPU6050::dmpGetAccelFloat(float *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetQuaternionFloat(float *data, const uint8_t* packet);
+
+uint8_t MPU6050::dmpProcessFIFOPacket(const unsigned char *dmpData) {
+    /*for (uint8_t k = 0; k < dmpPacketSize; k++) {
+        if (dmpData[k] < 0x10) Serial.print("0");
+        Serial.print(dmpData[k], HEX);
+        Serial.print(" ");
+    }
+    Serial.print("\n");*/
+    //Serial.println((uint16_t)dmpPacketBuffer);
+    return 0;
+}
+uint8_t MPU6050::dmpReadAndProcessFIFOPacket(uint8_t numPackets, uint8_t *processed) {
+    uint8_t status;
+    uint8_t buf[dmpPacketSize];
+    for (uint8_t i = 0; i < numPackets; i++) {
+        // read packet from FIFO
+        getFIFOBytes(buf, dmpPacketSize);
+
+        // process packet
+        if ((status = dmpProcessFIFOPacket(buf)) > 0) return status;
+        
+        // increment external process count variable, if supplied
+        if (processed != 0) *processed++;
+    }
+    return 0;
+}
+
+// uint8_t MPU6050::dmpSetFIFOProcessedCallback(void (*func) (void));
+
+// uint8_t MPU6050::dmpInitFIFOParam();
+// uint8_t MPU6050::dmpCloseFIFO();
+// uint8_t MPU6050::dmpSetGyroDataSource(uint_fast8_t source);
+// uint8_t MPU6050::dmpDecodeQuantizedAccel();
+// uint32_t MPU6050::dmpGetGyroSumOfSquare();
+// uint32_t MPU6050::dmpGetAccelSumOfSquare();
+// void MPU6050::dmpOverrideQuaternion(long *q);
+uint16_t MPU6050::dmpGetFIFOPacketSize() {
+    return dmpPacketSize;
+}
+
+#endif /* _MPU6050_6AXIS_MOTIONAPPS20_H_ */
diff --git a/hardware/digistump/sam/libraries/MPU6050/MPU6050_9Axis_MotionApps41.h b/hardware/digistump/sam/libraries/MPU6050/MPU6050_9Axis_MotionApps41.h
new file mode 100644
index 0000000..6ecb2c3
--- /dev/null
+++ b/hardware/digistump/sam/libraries/MPU6050/MPU6050_9Axis_MotionApps41.h
@@ -0,0 +1,808 @@
+// I2Cdev library collection - MPU6050 I2C device class, 9-axis MotionApps 4.1 implementation
+// Based on InvenSense MPU-6050 register map document rev. 2.0, 5/19/2011 (RM-MPU-6000A-00)
+// 6/18/2012 by Jeff Rowberg 
+// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib
+//
+// Changelog:
+//     ... - ongoing debug release
+
+/* ============================================
+I2Cdev device library code is placed under the MIT license
+Copyright (c) 2012 Jeff Rowberg
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+===============================================
+*/
+
+#ifndef _MPU6050_9AXIS_MOTIONAPPS41_H_
+#define _MPU6050_9AXIS_MOTIONAPPS41_H_
+
+#include "I2Cdev.h"
+#include "helper_3dmath.h"
+
+// MotionApps 4.1 DMP implementation, built using the MPU-9150 "MotionFit" board
+#define MPU6050_INCLUDE_DMP_MOTIONAPPS41
+
+#include "MPU6050.h"
+#include 
+
+// NOTE! Enabling DEBUG adds about 3.3kB to the flash program size.
+// Debug output is now working even on ATMega328P MCUs (e.g. Arduino Uno)
+// after moving string constants to flash memory storage using the F()
+// compiler macro (Arduino IDE 1.0+ required).
+
+//#define DEBUG
+#ifdef DEBUG
+    #define DEBUG_PRINT(x) Serial.print(x)
+    #define DEBUG_PRINTF(x, y) Serial.print(x, y)
+    #define DEBUG_PRINTLN(x) Serial.println(x)
+    #define DEBUG_PRINTLNF(x, y) Serial.println(x, y)
+#else
+    #define DEBUG_PRINT(x)
+    #define DEBUG_PRINTF(x, y)
+    #define DEBUG_PRINTLN(x)
+    #define DEBUG_PRINTLNF(x, y)
+#endif
+
+#define MPU6050_DMP_CODE_SIZE       1962    // dmpMemory[]
+#define MPU6050_DMP_CONFIG_SIZE     232     // dmpConfig[]
+#define MPU6050_DMP_UPDATES_SIZE    140     // dmpUpdates[]
+
+/* ================================================================================================ *
+ | Default MotionApps v4.1 48-byte FIFO packet structure:                                           |
+ |                                                                                                  |
+ | [QUAT W][      ][QUAT X][      ][QUAT Y][      ][QUAT Z][      ][GYRO X][      ][GYRO Y][      ] |
+ |   0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  |
+ |                                                                                                  |
+ | [GYRO Z][      ][MAG X ][MAG Y ][MAG Z ][ACC X ][      ][ACC Y ][      ][ACC Z ][      ][      ] |
+ |  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  |
+ * ================================================================================================ */
+
+// this block of memory gets written to the MPU on start-up, and it seems
+// to be volatile memory, so it has to be done each time (it only takes ~1
+// second though)
+const prog_uchar dmpMemory[MPU6050_DMP_CODE_SIZE] PROGMEM = {
+    // bank 0, 256 bytes
+    0xFB, 0x00, 0x00, 0x3E, 0x00, 0x0B, 0x00, 0x36, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x00,
+    0x00, 0x65, 0x00, 0x54, 0xFF, 0xEF, 0x00, 0x00, 0xFA, 0x80, 0x00, 0x0B, 0x12, 0x82, 0x00, 0x01,
+    0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x28, 0x00, 0x00, 0xFF, 0xFF, 0x45, 0x81, 0xFF, 0xFF, 0xFA, 0x72, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x03, 0xE8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x7F, 0xFF, 0xFF, 0xFE, 0x80, 0x01,
+    0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x3E, 0x03, 0x30, 0x40, 0x00, 0x00, 0x00, 0x02, 0xCA, 0xE3, 0x09, 0x3E, 0x80, 0x00, 0x00,
+    0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00,
+    0x41, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x2A, 0x00, 0x00, 0x16, 0x55, 0x00, 0x00, 0x21, 0x82,
+    0xFD, 0x87, 0x26, 0x50, 0xFD, 0x80, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x05, 0x80, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
+    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x6F, 0x00, 0x02, 0x65, 0x32, 0x00, 0x00, 0x5E, 0xC0,
+    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0xFB, 0x8C, 0x6F, 0x5D, 0xFD, 0x5D, 0x08, 0xD9, 0x00, 0x7C, 0x73, 0x3B, 0x00, 0x6C, 0x12, 0xCC,
+    0x32, 0x00, 0x13, 0x9D, 0x32, 0x00, 0xD0, 0xD6, 0x32, 0x00, 0x08, 0x00, 0x40, 0x00, 0x01, 0xF4,
+    0xFF, 0xE6, 0x80, 0x79, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD0, 0xD6, 0x00, 0x00, 0x27, 0x10,
+
+    // bank 1, 256 bytes
+    0xFB, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0xFA, 0x36, 0xFF, 0xBC, 0x30, 0x8E, 0x00, 0x05, 0xFB, 0xF0, 0xFF, 0xD9, 0x5B, 0xC8,
+    0xFF, 0xD0, 0x9A, 0xBE, 0x00, 0x00, 0x10, 0xA9, 0xFF, 0xF4, 0x1E, 0xB2, 0x00, 0xCE, 0xBB, 0xF7,
+    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x02, 0x00, 0x02, 0x02, 0x00, 0x00, 0x0C,
+    0xFF, 0xC2, 0x80, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0xCF, 0x80, 0x00, 0x40, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x14,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x03, 0x3F, 0x68, 0xB6, 0x79, 0x35, 0x28, 0xBC, 0xC6, 0x7E, 0xD1, 0x6C,
+    0x80, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB2, 0x6A, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xF0, 0x00, 0x00, 0x00, 0x30,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x25, 0x4D, 0x00, 0x2F, 0x70, 0x6D, 0x00, 0x00, 0x05, 0xAE, 0x00, 0x0C, 0x02, 0xD0,
+    
+    // bank 2, 256 bytes
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x00, 0x54, 0xFF, 0xEF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x01, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x00, 0x00, 0x00, 0x54, 0x00, 0x00, 0xFF, 0xEF, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+    0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x78, 0xA2,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    
+    // bank 3, 256 bytes
+    0xD8, 0xDC, 0xF4, 0xD8, 0xB9, 0xAB, 0xF3, 0xF8, 0xFA, 0xF1, 0xBA, 0xA2, 0xDE, 0xB2, 0xB8, 0xB4,
+    0xA8, 0x81, 0x98, 0xF7, 0x4A, 0x90, 0x7F, 0x91, 0x6A, 0xF3, 0xF9, 0xDB, 0xA8, 0xF9, 0xB0, 0xBA,
+    0xA0, 0x80, 0xF2, 0xCE, 0x81, 0xF3, 0xC2, 0xF1, 0xC1, 0xF2, 0xC3, 0xF3, 0xCC, 0xA2, 0xB2, 0x80,
+    0xF1, 0xC6, 0xD8, 0x80, 0xBA, 0xA7, 0xDF, 0xDF, 0xDF, 0xF2, 0xA7, 0xC3, 0xCB, 0xC5, 0xB6, 0xF0,
+    0x87, 0xA2, 0x94, 0x24, 0x48, 0x70, 0x3C, 0x95, 0x40, 0x68, 0x34, 0x58, 0x9B, 0x78, 0xA2, 0xF1,
+    0x83, 0x92, 0x2D, 0x55, 0x7D, 0xD8, 0xB1, 0xB4, 0xB8, 0xA1, 0xD0, 0x91, 0x80, 0xF2, 0x70, 0xF3,
+    0x70, 0xF2, 0x7C, 0x80, 0xA8, 0xF1, 0x01, 0xB0, 0x98, 0x87, 0xD9, 0x43, 0xD8, 0x86, 0xC9, 0x88,
+    0xBA, 0xA1, 0xF2, 0x0E, 0xB8, 0x97, 0x80, 0xF1, 0xA9, 0xDF, 0xDF, 0xDF, 0xAA, 0xDF, 0xDF, 0xDF,
+    0xF2, 0xAA, 0xC5, 0xCD, 0xC7, 0xA9, 0x0C, 0xC9, 0x2C, 0x97, 0x97, 0x97, 0x97, 0xF1, 0xA9, 0x89,
+    0x26, 0x46, 0x66, 0xB0, 0xB4, 0xBA, 0x80, 0xAC, 0xDE, 0xF2, 0xCA, 0xF1, 0xB2, 0x8C, 0x02, 0xA9,
+    0xB6, 0x98, 0x00, 0x89, 0x0E, 0x16, 0x1E, 0xB8, 0xA9, 0xB4, 0x99, 0x2C, 0x54, 0x7C, 0xB0, 0x8A,
+    0xA8, 0x96, 0x36, 0x56, 0x76, 0xF1, 0xB9, 0xAF, 0xB4, 0xB0, 0x83, 0xC0, 0xB8, 0xA8, 0x97, 0x11,
+    0xB1, 0x8F, 0x98, 0xB9, 0xAF, 0xF0, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0xF1, 0xA3, 0x29, 0x55,
+    0x7D, 0xAF, 0x83, 0xB5, 0x93, 0xF0, 0x00, 0x28, 0x50, 0xF5, 0xBA, 0xAD, 0x8F, 0x9F, 0x28, 0x54,
+    0x7C, 0xB9, 0xF1, 0xA3, 0x86, 0x9F, 0x61, 0xA6, 0xDA, 0xDE, 0xDF, 0xDB, 0xB2, 0xB6, 0x8E, 0x9D,
+    0xAE, 0xF5, 0x60, 0x68, 0x70, 0xB1, 0xB5, 0xF1, 0xDA, 0xA6, 0xDF, 0xD9, 0xA6, 0xFA, 0xA3, 0x86,
+    
+    // bank 4, 256 bytes
+    0x96, 0xDB, 0x31, 0xA6, 0xD9, 0xF8, 0xDF, 0xBA, 0xA6, 0x8F, 0xC2, 0xC5, 0xC7, 0xB2, 0x8C, 0xC1,
+    0xB8, 0xA2, 0xDF, 0xDF, 0xDF, 0xA3, 0xDF, 0xDF, 0xDF, 0xD8, 0xD8, 0xF1, 0xB8, 0xA8, 0xB2, 0x86,
+    0xB4, 0x98, 0x0D, 0x35, 0x5D, 0xB8, 0xAA, 0x98, 0xB0, 0x87, 0x2D, 0x35, 0x3D, 0xB2, 0xB6, 0xBA,
+    0xAF, 0x8C, 0x96, 0x19, 0x8F, 0x9F, 0xA7, 0x0E, 0x16, 0x1E, 0xB4, 0x9A, 0xB8, 0xAA, 0x87, 0x2C,
+    0x54, 0x7C, 0xB9, 0xA3, 0xDE, 0xDF, 0xDF, 0xA3, 0xB1, 0x80, 0xF2, 0xC4, 0xCD, 0xC9, 0xF1, 0xB8,
+    0xA9, 0xB4, 0x99, 0x83, 0x0D, 0x35, 0x5D, 0x89, 0xB9, 0xA3, 0x2D, 0x55, 0x7D, 0xB5, 0x93, 0xA3,
+    0x0E, 0x16, 0x1E, 0xA9, 0x2C, 0x54, 0x7C, 0xB8, 0xB4, 0xB0, 0xF1, 0x97, 0x83, 0xA8, 0x11, 0x84,
+    0xA5, 0x09, 0x98, 0xA3, 0x83, 0xF0, 0xDA, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0xD8, 0xF1, 0xA5,
+    0x29, 0x55, 0x7D, 0xA5, 0x85, 0x95, 0x02, 0x1A, 0x2E, 0x3A, 0x56, 0x5A, 0x40, 0x48, 0xF9, 0xF3,
+    0xA3, 0xD9, 0xF8, 0xF0, 0x98, 0x83, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0x97, 0x82, 0xA8, 0xF1,
+    0x11, 0xF0, 0x98, 0xA2, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0xDA, 0xF3, 0xDE, 0xD8, 0x83, 0xA5,
+    0x94, 0x01, 0xD9, 0xA3, 0x02, 0xF1, 0xA2, 0xC3, 0xC5, 0xC7, 0xD8, 0xF1, 0x84, 0x92, 0xA2, 0x4D,
+    0xDA, 0x2A, 0xD8, 0x48, 0x69, 0xD9, 0x2A, 0xD8, 0x68, 0x55, 0xDA, 0x32, 0xD8, 0x50, 0x71, 0xD9,
+    0x32, 0xD8, 0x70, 0x5D, 0xDA, 0x3A, 0xD8, 0x58, 0x79, 0xD9, 0x3A, 0xD8, 0x78, 0x93, 0xA3, 0x4D,
+    0xDA, 0x2A, 0xD8, 0x48, 0x69, 0xD9, 0x2A, 0xD8, 0x68, 0x55, 0xDA, 0x32, 0xD8, 0x50, 0x71, 0xD9,
+    0x32, 0xD8, 0x70, 0x5D, 0xDA, 0x3A, 0xD8, 0x58, 0x79, 0xD9, 0x3A, 0xD8, 0x78, 0xA8, 0x8A, 0x9A,
+    
+    // bank 5, 256 bytes
+    0xF0, 0x28, 0x50, 0x78, 0x9E, 0xF3, 0x88, 0x18, 0xF1, 0x9F, 0x1D, 0x98, 0xA8, 0xD9, 0x08, 0xD8,
+    0xC8, 0x9F, 0x12, 0x9E, 0xF3, 0x15, 0xA8, 0xDA, 0x12, 0x10, 0xD8, 0xF1, 0xAF, 0xC8, 0x97, 0x87,
+    0x34, 0xB5, 0xB9, 0x94, 0xA4, 0x21, 0xF3, 0xD9, 0x22, 0xD8, 0xF2, 0x2D, 0xF3, 0xD9, 0x2A, 0xD8,
+    0xF2, 0x35, 0xF3, 0xD9, 0x32, 0xD8, 0x81, 0xA4, 0x60, 0x60, 0x61, 0xD9, 0x61, 0xD8, 0x6C, 0x68,
+    0x69, 0xD9, 0x69, 0xD8, 0x74, 0x70, 0x71, 0xD9, 0x71, 0xD8, 0xB1, 0xA3, 0x84, 0x19, 0x3D, 0x5D,
+    0xA3, 0x83, 0x1A, 0x3E, 0x5E, 0x93, 0x10, 0x30, 0x81, 0x10, 0x11, 0xB8, 0xB0, 0xAF, 0x8F, 0x94,
+    0xF2, 0xDA, 0x3E, 0xD8, 0xB4, 0x9A, 0xA8, 0x87, 0x29, 0xDA, 0xF8, 0xD8, 0x87, 0x9A, 0x35, 0xDA,
+    0xF8, 0xD8, 0x87, 0x9A, 0x3D, 0xDA, 0xF8, 0xD8, 0xB1, 0xB9, 0xA4, 0x98, 0x85, 0x02, 0x2E, 0x56,
+    0xA5, 0x81, 0x00, 0x0C, 0x14, 0xA3, 0x97, 0xB0, 0x8A, 0xF1, 0x2D, 0xD9, 0x28, 0xD8, 0x4D, 0xD9,
+    0x48, 0xD8, 0x6D, 0xD9, 0x68, 0xD8, 0xB1, 0x84, 0x0D, 0xDA, 0x0E, 0xD8, 0xA3, 0x29, 0x83, 0xDA,
+    0x2C, 0x0E, 0xD8, 0xA3, 0x84, 0x49, 0x83, 0xDA, 0x2C, 0x4C, 0x0E, 0xD8, 0xB8, 0xB0, 0x97, 0x86,
+    0xA8, 0x31, 0x9B, 0x06, 0x99, 0x07, 0xAB, 0x97, 0x28, 0x88, 0x9B, 0xF0, 0x0C, 0x20, 0x14, 0x40,
+    0xB9, 0xA3, 0x8A, 0xC3, 0xC5, 0xC7, 0x9A, 0xA3, 0x28, 0x50, 0x78, 0xF1, 0xB5, 0x93, 0x01, 0xD9,
+    0xDF, 0xDF, 0xDF, 0xD8, 0xB8, 0xB4, 0xA8, 0x8C, 0x9C, 0xF0, 0x04, 0x28, 0x51, 0x79, 0x1D, 0x30,
+    0x14, 0x38, 0xB2, 0x82, 0xAB, 0xD0, 0x98, 0x2C, 0x50, 0x50, 0x78, 0x78, 0x9B, 0xF1, 0x1A, 0xB0,
+    0xF0, 0xB1, 0x83, 0x9C, 0xA8, 0x29, 0x51, 0x79, 0xB0, 0x8B, 0x29, 0x51, 0x79, 0xB1, 0x83, 0x24,
+
+    // bank 6, 256 bytes
+    0x70, 0x59, 0xB0, 0x8B, 0x20, 0x58, 0x71, 0xB1, 0x83, 0x44, 0x69, 0x38, 0xB0, 0x8B, 0x39, 0x40,
+    0x68, 0xB1, 0x83, 0x64, 0x48, 0x31, 0xB0, 0x8B, 0x30, 0x49, 0x60, 0xA5, 0x88, 0x20, 0x09, 0x71,
+    0x58, 0x44, 0x68, 0x11, 0x39, 0x64, 0x49, 0x30, 0x19, 0xF1, 0xAC, 0x00, 0x2C, 0x54, 0x7C, 0xF0,
+    0x8C, 0xA8, 0x04, 0x28, 0x50, 0x78, 0xF1, 0x88, 0x97, 0x26, 0xA8, 0x59, 0x98, 0xAC, 0x8C, 0x02,
+    0x26, 0x46, 0x66, 0xF0, 0x89, 0x9C, 0xA8, 0x29, 0x51, 0x79, 0x24, 0x70, 0x59, 0x44, 0x69, 0x38,
+    0x64, 0x48, 0x31, 0xA9, 0x88, 0x09, 0x20, 0x59, 0x70, 0xAB, 0x11, 0x38, 0x40, 0x69, 0xA8, 0x19,
+    0x31, 0x48, 0x60, 0x8C, 0xA8, 0x3C, 0x41, 0x5C, 0x20, 0x7C, 0x00, 0xF1, 0x87, 0x98, 0x19, 0x86,
+    0xA8, 0x6E, 0x76, 0x7E, 0xA9, 0x99, 0x88, 0x2D, 0x55, 0x7D, 0x9E, 0xB9, 0xA3, 0x8A, 0x22, 0x8A,
+    0x6E, 0x8A, 0x56, 0x8A, 0x5E, 0x9F, 0xB1, 0x83, 0x06, 0x26, 0x46, 0x66, 0x0E, 0x2E, 0x4E, 0x6E,
+    0x9D, 0xB8, 0xAD, 0x00, 0x2C, 0x54, 0x7C, 0xF2, 0xB1, 0x8C, 0xB4, 0x99, 0xB9, 0xA3, 0x2D, 0x55,
+    0x7D, 0x81, 0x91, 0xAC, 0x38, 0xAD, 0x3A, 0xB5, 0x83, 0x91, 0xAC, 0x2D, 0xD9, 0x28, 0xD8, 0x4D,
+    0xD9, 0x48, 0xD8, 0x6D, 0xD9, 0x68, 0xD8, 0x8C, 0x9D, 0xAE, 0x29, 0xD9, 0x04, 0xAE, 0xD8, 0x51,
+    0xD9, 0x04, 0xAE, 0xD8, 0x79, 0xD9, 0x04, 0xD8, 0x81, 0xF3, 0x9D, 0xAD, 0x00, 0x8D, 0xAE, 0x19,
+    0x81, 0xAD, 0xD9, 0x01, 0xD8, 0xF2, 0xAE, 0xDA, 0x26, 0xD8, 0x8E, 0x91, 0x29, 0x83, 0xA7, 0xD9,
+    0xAD, 0xAD, 0xAD, 0xAD, 0xF3, 0x2A, 0xD8, 0xD8, 0xF1, 0xB0, 0xAC, 0x89, 0x91, 0x3E, 0x5E, 0x76,
+    0xF3, 0xAC, 0x2E, 0x2E, 0xF1, 0xB1, 0x8C, 0x5A, 0x9C, 0xAC, 0x2C, 0x28, 0x28, 0x28, 0x9C, 0xAC,
+    
+    // bank 7, 170 bytes (remainder)
+    0x30, 0x18, 0xA8, 0x98, 0x81, 0x28, 0x34, 0x3C, 0x97, 0x24, 0xA7, 0x28, 0x34, 0x3C, 0x9C, 0x24,
+    0xF2, 0xB0, 0x89, 0xAC, 0x91, 0x2C, 0x4C, 0x6C, 0x8A, 0x9B, 0x2D, 0xD9, 0xD8, 0xD8, 0x51, 0xD9,
+    0xD8, 0xD8, 0x79, 0xD9, 0xD8, 0xD8, 0xF1, 0x9E, 0x88, 0xA3, 0x31, 0xDA, 0xD8, 0xD8, 0x91, 0x2D,
+    0xD9, 0x28, 0xD8, 0x4D, 0xD9, 0x48, 0xD8, 0x6D, 0xD9, 0x68, 0xD8, 0xB1, 0x83, 0x93, 0x35, 0x3D,
+    0x80, 0x25, 0xDA, 0xD8, 0xD8, 0x85, 0x69, 0xDA, 0xD8, 0xD8, 0xB4, 0x93, 0x81, 0xA3, 0x28, 0x34,
+    0x3C, 0xF3, 0xAB, 0x8B, 0xA3, 0x91, 0xB6, 0x09, 0xB4, 0xD9, 0xAB, 0xDE, 0xB0, 0x87, 0x9C, 0xB9,
+    0xA3, 0xDD, 0xF1, 0xA3, 0xA3, 0xA3, 0xA3, 0x95, 0xF1, 0xA3, 0xA3, 0xA3, 0x9D, 0xF1, 0xA3, 0xA3,
+    0xA3, 0xA3, 0xF2, 0xA3, 0xB4, 0x90, 0x80, 0xF2, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3,
+    0xA3, 0xA3, 0xB2, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xB0, 0x87, 0xB5, 0x99, 0xF1, 0xA3, 0xA3,
+    0xA3, 0x98, 0xF1, 0xA3, 0xA3, 0xA3, 0xA3, 0x97, 0xA3, 0xA3, 0xA3, 0xA3, 0xF3, 0x9B, 0xA3, 0xA3,
+    0xDC, 0xB9, 0xA7, 0xF1, 0x26, 0x26, 0x26, 0xD8, 0xD8, 0xFF
+};
+
+const prog_uchar dmpConfig[MPU6050_DMP_CONFIG_SIZE] PROGMEM = {
+//  BANK    OFFSET  LENGTH  [DATA]
+    0x02,   0xEC,   0x04,   0x00, 0x47, 0x7D, 0x1A,   // ?
+    0x03,   0x82,   0x03,   0x4C, 0xCD, 0x6C,         // FCFG_1 inv_set_gyro_calibration
+    0x03,   0xB2,   0x03,   0x36, 0x56, 0x76,         // FCFG_3 inv_set_gyro_calibration
+    0x00,   0x68,   0x04,   0x02, 0xCA, 0xE3, 0x09,   // D_0_104 inv_set_gyro_calibration
+    0x01,   0x0C,   0x04,   0x00, 0x00, 0x00, 0x00,   // D_1_152 inv_set_accel_calibration
+    0x03,   0x86,   0x03,   0x0C, 0xC9, 0x2C,         // FCFG_2 inv_set_accel_calibration
+    0x03,   0x90,   0x03,   0x26, 0x46, 0x66,         //   (continued)...FCFG_2 inv_set_accel_calibration
+    0x00,   0x6C,   0x02,   0x40, 0x00,               // D_0_108 inv_set_accel_calibration
+
+    0x02,   0x40,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_00 inv_set_compass_calibration
+    0x02,   0x44,   0x04,   0x40, 0x00, 0x00, 0x00,   // CPASS_MTX_01
+    0x02,   0x48,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_02
+    0x02,   0x4C,   0x04,   0x40, 0x00, 0x00, 0x00,   // CPASS_MTX_10
+    0x02,   0x50,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_11
+    0x02,   0x54,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_12
+    0x02,   0x58,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_20
+    0x02,   0x5C,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_21
+    0x02,   0xBC,   0x04,   0xC0, 0x00, 0x00, 0x00,   // CPASS_MTX_22
+
+    0x01,   0xEC,   0x04,   0x00, 0x00, 0x40, 0x00,   // D_1_236 inv_apply_endian_accel
+    0x03,   0x86,   0x06,   0x0C, 0xC9, 0x2C, 0x97, 0x97, 0x97, // FCFG_2 inv_set_mpu_sensors
+    0x04,   0x22,   0x03,   0x0D, 0x35, 0x5D,         // CFG_MOTION_BIAS inv_turn_on_bias_from_no_motion
+    0x00,   0xA3,   0x01,   0x00,                     // ?
+    0x04,   0x29,   0x04,   0x87, 0x2D, 0x35, 0x3D,   // FCFG_5 inv_set_bias_update
+    0x07,   0x62,   0x05,   0xF1, 0x20, 0x28, 0x30, 0x38, // CFG_8 inv_send_quaternion
+    0x07,   0x9F,   0x01,   0x30,                     // CFG_16 inv_set_footer
+    0x07,   0x67,   0x01,   0x9A,                     // CFG_GYRO_SOURCE inv_send_gyro
+    0x07,   0x68,   0x04,   0xF1, 0x28, 0x30, 0x38,   // CFG_9 inv_send_gyro -> inv_construct3_fifo
+    0x07,   0x62,   0x05,   0xF1, 0x20, 0x28, 0x30, 0x38, // ?
+    0x02,   0x0C,   0x04,   0x00, 0x00, 0x00, 0x00,   // ?
+    0x07,   0x83,   0x06,   0xC2, 0xCA, 0xC4, 0xA3, 0xA3, 0xA3, // ?
+                 // SPECIAL 0x01 = enable interrupts
+    0x00,   0x00,   0x00,   0x01, // SET INT_ENABLE, SPECIAL INSTRUCTION
+    0x07,   0xA7,   0x01,   0xFE,                     // ?
+    0x07,   0x62,   0x05,   0xF1, 0x20, 0x28, 0x30, 0x38, // ?
+    0x07,   0x67,   0x01,   0x9A,                     // ?
+    0x07,   0x68,   0x04,   0xF1, 0x28, 0x30, 0x38,   // CFG_12 inv_send_accel -> inv_construct3_fifo
+    0x07,   0x8D,   0x04,   0xF1, 0x28, 0x30, 0x38,   // ??? CFG_12 inv_send_mag -> inv_construct3_fifo
+    0x02,   0x16,   0x02,   0x00, 0x03                // D_0_22 inv_set_fifo_rate
+
+    // This very last 0x01 WAS a 0x09, which drops the FIFO rate down to 20 Hz. 0x07 is 25 Hz,
+    // 0x01 is 100Hz. Going faster than 100Hz (0x00=200Hz) tends to result in very noisy data.
+    // DMP output frequency is calculated easily using this equation: (200Hz / (1 + value))
+
+    // It is important to make sure the host processor can keep up with reading and processing
+    // the FIFO output at the desired rate. Handling FIFO overflow cleanly is also a good idea.
+};
+
+const prog_uchar dmpUpdates[MPU6050_DMP_UPDATES_SIZE] PROGMEM = {
+    0x01,   0xB2,   0x02,   0xFF, 0xF5,
+    0x01,   0x90,   0x04,   0x0A, 0x0D, 0x97, 0xC0,
+    0x00,   0xA3,   0x01,   0x00,
+    0x04,   0x29,   0x04,   0x87, 0x2D, 0x35, 0x3D,
+    0x01,   0x6A,   0x02,   0x06, 0x00,
+    0x01,   0x60,   0x08,   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00,   0x60,   0x04,   0x40, 0x00, 0x00, 0x00,
+    0x02,   0x60,   0x0C,   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x01,   0x08,   0x02,   0x01, 0x20,
+    0x01,   0x0A,   0x02,   0x00, 0x4E,
+    0x01,   0x02,   0x02,   0xFE, 0xB3,
+    0x02,   0x6C,   0x04,   0x00, 0x00, 0x00, 0x00, // READ
+    0x02,   0x6C,   0x04,   0xFA, 0xFE, 0x00, 0x00,
+    0x02,   0x60,   0x0C,   0xFF, 0xFF, 0xCB, 0x4D, 0x00, 0x01, 0x08, 0xC1, 0xFF, 0xFF, 0xBC, 0x2C,
+    0x02,   0xF4,   0x04,   0x00, 0x00, 0x00, 0x00,
+    0x02,   0xF8,   0x04,   0x00, 0x00, 0x00, 0x00,
+    0x02,   0xFC,   0x04,   0x00, 0x00, 0x00, 0x00,
+    0x00,   0x60,   0x04,   0x40, 0x00, 0x00, 0x00,
+    0x00,   0x60,   0x04,   0x00, 0x40, 0x00, 0x00
+};
+
+uint8_t MPU6050::dmpInitialize() {
+    // reset device
+    DEBUG_PRINTLN(F("\n\nResetting MPU6050..."));
+    reset();
+    delay(30); // wait after reset
+
+    // disable sleep mode
+    DEBUG_PRINTLN(F("Disabling sleep mode..."));
+    setSleepEnabled(false);
+
+    // get MPU product ID
+    DEBUG_PRINTLN(F("Getting product ID..."));
+    //uint8_t productID = 0; //getProductID();
+    DEBUG_PRINT(F("Product ID = "));
+    DEBUG_PRINT(productID);
+
+    // get MPU hardware revision
+    DEBUG_PRINTLN(F("Selecting user bank 16..."));
+    setMemoryBank(0x10, true, true);
+    DEBUG_PRINTLN(F("Selecting memory byte 6..."));
+    setMemoryStartAddress(0x06);
+    DEBUG_PRINTLN(F("Checking hardware revision..."));
+    uint8_t hwRevision = readMemoryByte();
+    DEBUG_PRINT(F("Revision @ user[16][6] = "));
+    DEBUG_PRINTLNF(hwRevision, HEX);
+    DEBUG_PRINTLN(F("Resetting memory bank selection to 0..."));
+    setMemoryBank(0, false, false);
+
+    // check OTP bank valid
+    DEBUG_PRINTLN(F("Reading OTP bank valid flag..."));
+    uint8_t otpValid = getOTPBankValid();
+    DEBUG_PRINT(F("OTP bank is "));
+    DEBUG_PRINTLN(otpValid ? F("valid!") : F("invalid!"));
+
+    // get X/Y/Z gyro offsets
+    DEBUG_PRINTLN(F("Reading gyro offset values..."));
+    int8_t xgOffset = getXGyroOffset();
+    int8_t ygOffset = getYGyroOffset();
+    int8_t zgOffset = getZGyroOffset();
+    DEBUG_PRINT(F("X gyro offset = "));
+    DEBUG_PRINTLN(xgOffset);
+    DEBUG_PRINT(F("Y gyro offset = "));
+    DEBUG_PRINTLN(ygOffset);
+    DEBUG_PRINT(F("Z gyro offset = "));
+    DEBUG_PRINTLN(zgOffset);
+    
+    I2Cdev::readByte(devAddr, MPU6050_RA_USER_CTRL, buffer); // ?
+    
+    DEBUG_PRINTLN(F("Enabling interrupt latch, clear on any read, AUX bypass enabled"));
+    I2Cdev::writeByte(devAddr, MPU6050_RA_INT_PIN_CFG, 0x32);
+
+    // enable MPU AUX I2C bypass mode
+    //DEBUG_PRINTLN(F("Enabling AUX I2C bypass mode..."));
+    //setI2CBypassEnabled(true);
+
+    DEBUG_PRINTLN(F("Setting magnetometer mode to power-down..."));
+    //mag -> setMode(0);
+    I2Cdev::writeByte(0x0E, 0x0A, 0x00);
+
+    DEBUG_PRINTLN(F("Setting magnetometer mode to fuse access..."));
+    //mag -> setMode(0x0F);
+    I2Cdev::writeByte(0x0E, 0x0A, 0x0F);
+
+    DEBUG_PRINTLN(F("Reading mag magnetometer factory calibration..."));
+    int8_t asax, asay, asaz;
+    //mag -> getAdjustment(&asax, &asay, &asaz);
+    I2Cdev::readBytes(0x0E, 0x10, 3, buffer);
+    asax = (int8_t)buffer[0];
+    asay = (int8_t)buffer[1];
+    asaz = (int8_t)buffer[2];
+    DEBUG_PRINT(F("Adjustment X/Y/Z = "));
+    DEBUG_PRINT(asax);
+    DEBUG_PRINT(F(" / "));
+    DEBUG_PRINT(asay);
+    DEBUG_PRINT(F(" / "));
+    DEBUG_PRINTLN(asaz);
+
+    DEBUG_PRINTLN(F("Setting magnetometer mode to power-down..."));
+    //mag -> setMode(0);
+    I2Cdev::writeByte(0x0E, 0x0A, 0x00);
+
+    // load DMP code into memory banks
+    DEBUG_PRINT(F("Writing DMP code to MPU memory banks ("));
+    DEBUG_PRINT(MPU6050_DMP_CODE_SIZE);
+    DEBUG_PRINTLN(F(" bytes)"));
+    if (writeProgMemoryBlock(dmpMemory, MPU6050_DMP_CODE_SIZE)) {
+        DEBUG_PRINTLN(F("Success! DMP code written and verified."));
+
+        DEBUG_PRINTLN(F("Configuring DMP and related settings..."));
+
+        // write DMP configuration
+        DEBUG_PRINT(F("Writing DMP configuration to MPU memory banks ("));
+        DEBUG_PRINT(MPU6050_DMP_CONFIG_SIZE);
+        DEBUG_PRINTLN(F(" bytes in config def)"));
+        if (writeProgDMPConfigurationSet(dmpConfig, MPU6050_DMP_CONFIG_SIZE)) {
+            DEBUG_PRINTLN(F("Success! DMP configuration written and verified."));
+
+            DEBUG_PRINTLN(F("Setting DMP and FIFO_OFLOW interrupts enabled..."));
+            setIntEnabled(0x12);
+
+            DEBUG_PRINTLN(F("Setting sample rate to 200Hz..."));
+            setRate(4); // 1khz / (1 + 4) = 200 Hz
+
+            DEBUG_PRINTLN(F("Setting clock source to Z Gyro..."));
+            setClockSource(MPU6050_CLOCK_PLL_ZGYRO);
+
+            DEBUG_PRINTLN(F("Setting DLPF bandwidth to 42Hz..."));
+            setDLPFMode(MPU6050_DLPF_BW_42);
+
+            DEBUG_PRINTLN(F("Setting external frame sync to TEMP_OUT_L[0]..."));
+            setExternalFrameSync(MPU6050_EXT_SYNC_TEMP_OUT_L);
+
+            DEBUG_PRINTLN(F("Setting gyro sensitivity to +/- 2000 deg/sec..."));
+            setFullScaleGyroRange(MPU6050_GYRO_FS_2000);
+
+            DEBUG_PRINTLN(F("Setting DMP configuration bytes (function unknown)..."));
+            setDMPConfig1(0x03);
+            setDMPConfig2(0x00);
+
+            DEBUG_PRINTLN(F("Clearing OTP Bank flag..."));
+            setOTPBankValid(false);
+
+            DEBUG_PRINTLN(F("Setting X/Y/Z gyro offsets to previous values..."));
+            setXGyroOffset(xgOffset);
+            setYGyroOffset(ygOffset);
+            setZGyroOffset(zgOffset);
+
+            DEBUG_PRINTLN(F("Setting X/Y/Z gyro user offsets to zero..."));
+            setXGyroOffsetUser(0);
+            setYGyroOffsetUser(0);
+            setZGyroOffsetUser(0);
+
+            DEBUG_PRINTLN(F("Writing final memory update 1/19 (function unknown)..."));
+            uint8_t dmpUpdate[16], j;
+            uint16_t pos = 0;
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("Writing final memory update 2/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("Resetting FIFO..."));
+            resetFIFO();
+
+            DEBUG_PRINTLN(F("Reading FIFO count..."));
+            uint8_t fifoCount = getFIFOCount();
+
+            DEBUG_PRINT(F("Current FIFO count="));
+            DEBUG_PRINTLN(fifoCount);
+            uint8_t fifoBuffer[128];
+            //getFIFOBytes(fifoBuffer, fifoCount);
+
+            DEBUG_PRINTLN(F("Writing final memory update 3/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("Writing final memory update 4/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("Disabling all standby flags..."));
+            I2Cdev::writeByte(0x68, MPU6050_RA_PWR_MGMT_2, 0x00);
+
+            DEBUG_PRINTLN(F("Setting accelerometer sensitivity to +/- 2g..."));
+            I2Cdev::writeByte(0x68, MPU6050_RA_ACCEL_CONFIG, 0x00);
+
+            DEBUG_PRINTLN(F("Setting motion detection threshold to 2..."));
+            setMotionDetectionThreshold(2);
+
+            DEBUG_PRINTLN(F("Setting zero-motion detection threshold to 156..."));
+            setZeroMotionDetectionThreshold(156);
+
+            DEBUG_PRINTLN(F("Setting motion detection duration to 80..."));
+            setMotionDetectionDuration(80);
+
+            DEBUG_PRINTLN(F("Setting zero-motion detection duration to 0..."));
+            setZeroMotionDetectionDuration(0);
+
+            DEBUG_PRINTLN(F("Setting AK8975 to single measurement mode..."));
+            //mag -> setMode(1);
+            I2Cdev::writeByte(0x0E, 0x0A, 0x01);
+
+            // setup AK8975 (0x0E) as Slave 0 in read mode
+            DEBUG_PRINTLN(F("Setting up AK8975 read slave 0..."));
+            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV0_ADDR, 0x8E);
+            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV0_REG,  0x01);
+            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV0_CTRL, 0xDA);
+
+            // setup AK8975 (0x0E) as Slave 2 in write mode
+            DEBUG_PRINTLN(F("Setting up AK8975 write slave 2..."));
+            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV2_ADDR, 0x0E);
+            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV2_REG,  0x0A);
+            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV2_CTRL, 0x81);
+            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV2_DO,   0x01);
+
+            // setup I2C timing/delay control
+            DEBUG_PRINTLN(F("Setting up slave access delay..."));
+            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV4_CTRL, 0x18);
+            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_MST_DELAY_CTRL, 0x05);
+
+            // enable interrupts
+            DEBUG_PRINTLN(F("Enabling default interrupt behavior/no bypass..."));
+            I2Cdev::writeByte(0x68, MPU6050_RA_INT_PIN_CFG, 0x00);
+
+            // enable I2C master mode and reset DMP/FIFO
+            DEBUG_PRINTLN(F("Enabling I2C master mode..."));
+            I2Cdev::writeByte(0x68, MPU6050_RA_USER_CTRL, 0x20);
+            DEBUG_PRINTLN(F("Resetting FIFO..."));
+            I2Cdev::writeByte(0x68, MPU6050_RA_USER_CTRL, 0x24);
+            DEBUG_PRINTLN(F("Rewriting I2C master mode enabled because...I don't know"));
+            I2Cdev::writeByte(0x68, MPU6050_RA_USER_CTRL, 0x20);
+            DEBUG_PRINTLN(F("Enabling and resetting DMP/FIFO..."));
+            I2Cdev::writeByte(0x68, MPU6050_RA_USER_CTRL, 0xE8);
+
+            DEBUG_PRINTLN(F("Writing final memory update 5/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+            DEBUG_PRINTLN(F("Writing final memory update 6/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+            DEBUG_PRINTLN(F("Writing final memory update 7/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+            DEBUG_PRINTLN(F("Writing final memory update 8/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+            DEBUG_PRINTLN(F("Writing final memory update 9/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+            DEBUG_PRINTLN(F("Writing final memory update 10/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+            DEBUG_PRINTLN(F("Writing final memory update 11/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+            
+            DEBUG_PRINTLN(F("Reading final memory update 12/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            readMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+            #ifdef DEBUG
+                DEBUG_PRINT(F("Read bytes: "));
+                for (j = 0; j < 4; j++) {
+                    DEBUG_PRINTF(dmpUpdate[3 + j], HEX);
+                    DEBUG_PRINT(" ");
+                }
+                DEBUG_PRINTLN("");
+            #endif
+
+            DEBUG_PRINTLN(F("Writing final memory update 13/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+            DEBUG_PRINTLN(F("Writing final memory update 14/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+            DEBUG_PRINTLN(F("Writing final memory update 15/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+            DEBUG_PRINTLN(F("Writing final memory update 16/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+            DEBUG_PRINTLN(F("Writing final memory update 17/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("Waiting for FIRO count >= 46..."));
+            while ((fifoCount = getFIFOCount()) < 46);
+            DEBUG_PRINTLN(F("Reading FIFO..."));
+            getFIFOBytes(fifoBuffer, min(fifoCount, 128)); // safeguard only 128 bytes
+            DEBUG_PRINTLN(F("Reading interrupt status..."));
+            getIntStatus();
+
+            DEBUG_PRINTLN(F("Writing final memory update 18/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("Waiting for FIRO count >= 48..."));
+            while ((fifoCount = getFIFOCount()) < 48);
+            DEBUG_PRINTLN(F("Reading FIFO..."));
+            getFIFOBytes(fifoBuffer, min(fifoCount, 128)); // safeguard only 128 bytes
+            DEBUG_PRINTLN(F("Reading interrupt status..."));
+            getIntStatus();
+            DEBUG_PRINTLN(F("Waiting for FIRO count >= 48..."));
+            while ((fifoCount = getFIFOCount()) < 48);
+            DEBUG_PRINTLN(F("Reading FIFO..."));
+            getFIFOBytes(fifoBuffer, min(fifoCount, 128)); // safeguard only 128 bytes
+            DEBUG_PRINTLN(F("Reading interrupt status..."));
+            getIntStatus();
+
+            DEBUG_PRINTLN(F("Writing final memory update 19/19 (function unknown)..."));
+            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);
+            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);
+
+            DEBUG_PRINTLN(F("Disabling DMP (you turn it on later)..."));
+            setDMPEnabled(false);
+
+            DEBUG_PRINTLN(F("Setting up internal 48-byte (default) DMP packet buffer..."));
+            dmpPacketSize = 48;
+            /*if ((dmpPacketBuffer = (uint8_t *)malloc(42)) == 0) {
+                return 3; // TODO: proper error code for no memory
+            }*/
+
+            DEBUG_PRINTLN(F("Resetting FIFO and clearing INT status one last time..."));
+            resetFIFO();
+            getIntStatus();
+        } else {
+            DEBUG_PRINTLN(F("ERROR! DMP configuration verification failed."));
+            return 2; // configuration block loading failed
+        }
+    } else {
+        DEBUG_PRINTLN(F("ERROR! DMP code verification failed."));
+        return 1; // main binary block loading failed
+    }
+    return 0; // success
+}
+
+bool MPU6050::dmpPacketAvailable() {
+    return getFIFOCount() >= dmpGetFIFOPacketSize();
+}
+
+// uint8_t MPU6050::dmpSetFIFORate(uint8_t fifoRate);
+// uint8_t MPU6050::dmpGetFIFORate();
+// uint8_t MPU6050::dmpGetSampleStepSizeMS();
+// uint8_t MPU6050::dmpGetSampleFrequency();
+// int32_t MPU6050::dmpDecodeTemperature(int8_t tempReg);
+
+//uint8_t MPU6050::dmpRegisterFIFORateProcess(inv_obj_func func, int16_t priority);
+//uint8_t MPU6050::dmpUnregisterFIFORateProcess(inv_obj_func func);
+//uint8_t MPU6050::dmpRunFIFORateProcesses();
+
+// uint8_t MPU6050::dmpSendQuaternion(uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendGyro(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendAccel(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendLinearAccel(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendLinearAccelInWorld(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendControlData(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendSensorData(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendExternalSensorData(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendGravity(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendPacketNumber(uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendQuantizedAccel(uint_fast16_t elements, uint_fast16_t accuracy);
+// uint8_t MPU6050::dmpSendEIS(uint_fast16_t elements, uint_fast16_t accuracy);
+
+uint8_t MPU6050::dmpGetAccel(int32_t *data, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    data[0] = ((packet[34] << 24) + (packet[35] << 16) + (packet[36] << 8) + packet[37]);
+    data[1] = ((packet[38] << 24) + (packet[39] << 16) + (packet[40] << 8) + packet[41]);
+    data[2] = ((packet[42] << 24) + (packet[43] << 16) + (packet[44] << 8) + packet[45]);
+    return 0;
+}
+uint8_t MPU6050::dmpGetAccel(int16_t *data, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    data[0] = (packet[34] << 8) + packet[35];
+    data[1] = (packet[38] << 8) + packet[39];
+    data[2] = (packet[42] << 8) + packet[43];
+    return 0;
+}
+uint8_t MPU6050::dmpGetAccel(VectorInt16 *v, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    v -> x = (packet[34] << 8) + packet[35];
+    v -> y = (packet[38] << 8) + packet[39];
+    v -> z = (packet[42] << 8) + packet[43];
+    return 0;
+}
+uint8_t MPU6050::dmpGetQuaternion(int32_t *data, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    data[0] = ((packet[0] << 24) + (packet[1] << 16) + (packet[2] << 8) + packet[3]);
+    data[1] = ((packet[4] << 24) + (packet[5] << 16) + (packet[6] << 8) + packet[7]);
+    data[2] = ((packet[8] << 24) + (packet[9] << 16) + (packet[10] << 8) + packet[11]);
+    data[3] = ((packet[12] << 24) + (packet[13] << 16) + (packet[14] << 8) + packet[15]);
+    return 0;
+}
+uint8_t MPU6050::dmpGetQuaternion(int16_t *data, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    data[0] = ((packet[0] << 8) + packet[1]);
+    data[1] = ((packet[4] << 8) + packet[5]);
+    data[2] = ((packet[8] << 8) + packet[9]);
+    data[3] = ((packet[12] << 8) + packet[13]);
+    return 0;
+}
+uint8_t MPU6050::dmpGetQuaternion(Quaternion *q, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    int16_t qI[4];
+    uint8_t status = dmpGetQuaternion(qI, packet);
+    if (status == 0) {
+        q -> w = (float)qI[0] / 16384.0f;
+        q -> x = (float)qI[1] / 16384.0f;
+        q -> y = (float)qI[2] / 16384.0f;
+        q -> z = (float)qI[3] / 16384.0f;
+        return 0;
+    }
+    return status; // int16 return value, indicates error if this line is reached
+}
+// uint8_t MPU6050::dmpGet6AxisQuaternion(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetRelativeQuaternion(long *data, const uint8_t* packet);
+uint8_t MPU6050::dmpGetGyro(int32_t *data, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    data[0] = ((packet[16] << 24) + (packet[17] << 16) + (packet[18] << 8) + packet[19]);
+    data[1] = ((packet[20] << 24) + (packet[21] << 16) + (packet[22] << 8) + packet[23]);
+    data[2] = ((packet[24] << 24) + (packet[25] << 16) + (packet[26] << 8) + packet[27]);
+    return 0;
+}
+uint8_t MPU6050::dmpGetGyro(int16_t *data, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    data[0] = (packet[16] << 8) + packet[17];
+    data[1] = (packet[20] << 8) + packet[21];
+    data[2] = (packet[24] << 8) + packet[25];
+    return 0;
+}
+uint8_t MPU6050::dmpGetMag(int16_t *data, const uint8_t* packet) {
+    // TODO: accommodate different arrangements of sent data (ONLY default supported now)
+    if (packet == 0) packet = dmpPacketBuffer;
+    data[0] = (packet[28] << 8) + packet[29];
+    data[1] = (packet[30] << 8) + packet[31];
+    data[2] = (packet[32] << 8) + packet[33];
+    return 0;
+}
+// uint8_t MPU6050::dmpSetLinearAccelFilterCoefficient(float coef);
+// uint8_t MPU6050::dmpGetLinearAccel(long *data, const uint8_t* packet);
+uint8_t MPU6050::dmpGetLinearAccel(VectorInt16 *v, VectorInt16 *vRaw, VectorFloat *gravity) {
+    // get rid of the gravity component (+1g = +4096 in standard DMP FIFO packet)
+    v -> x = vRaw -> x - gravity -> x*4096;
+    v -> y = vRaw -> y - gravity -> y*4096;
+    v -> z = vRaw -> z - gravity -> z*4096;
+    return 0;
+}
+// uint8_t MPU6050::dmpGetLinearAccelInWorld(long *data, const uint8_t* packet);
+uint8_t MPU6050::dmpGetLinearAccelInWorld(VectorInt16 *v, VectorInt16 *vReal, Quaternion *q) {
+    // rotate measured 3D acceleration vector into original state
+    // frame of reference based on orientation quaternion
+    memcpy(v, vReal, sizeof(VectorInt16));
+    v -> rotate(q);
+    return 0;
+}
+// uint8_t MPU6050::dmpGetGyroAndAccelSensor(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetGyroSensor(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetControlData(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetTemperature(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetGravity(long *data, const uint8_t* packet);
+uint8_t MPU6050::dmpGetGravity(VectorFloat *v, Quaternion *q) {
+    v -> x = 2 * (q -> x*q -> z - q -> w*q -> y);
+    v -> y = 2 * (q -> w*q -> x + q -> y*q -> z);
+    v -> z = q -> w*q -> w - q -> x*q -> x - q -> y*q -> y + q -> z*q -> z;
+    return 0;
+}
+// uint8_t MPU6050::dmpGetUnquantizedAccel(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetQuantizedAccel(long *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetExternalSensorData(long *data, int size, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetEIS(long *data, const uint8_t* packet);
+
+uint8_t MPU6050::dmpGetEuler(float *data, Quaternion *q) {
+    data[0] = atan2(2*q -> x*q -> y - 2*q -> w*q -> z, 2*q -> w*q -> w + 2*q -> x*q -> x - 1);   // psi
+    data[1] = -asin(2*q -> x*q -> z + 2*q -> w*q -> y);                              // theta
+    data[2] = atan2(2*q -> y*q -> z - 2*q -> w*q -> x, 2*q -> w*q -> w + 2*q -> z*q -> z - 1);   // phi
+    return 0;
+}
+uint8_t MPU6050::dmpGetYawPitchRoll(float *data, Quaternion *q, VectorFloat *gravity) {
+    // yaw: (about Z axis)
+    data[0] = atan2(2*q -> x*q -> y - 2*q -> w*q -> z, 2*q -> w*q -> w + 2*q -> x*q -> x - 1);
+    // pitch: (nose up/down, about Y axis)
+    data[1] = atan(gravity -> x / sqrt(gravity -> y*gravity -> y + gravity -> z*gravity -> z));
+    // roll: (tilt left/right, about X axis)
+    data[2] = atan(gravity -> y / sqrt(gravity -> x*gravity -> x + gravity -> z*gravity -> z));
+    return 0;
+}
+
+// uint8_t MPU6050::dmpGetAccelFloat(float *data, const uint8_t* packet);
+// uint8_t MPU6050::dmpGetQuaternionFloat(float *data, const uint8_t* packet);
+
+uint8_t MPU6050::dmpProcessFIFOPacket(const unsigned char *dmpData) {
+    /*for (uint8_t k = 0; k < dmpPacketSize; k++) {
+        if (dmpData[k] < 0x10) Serial.print("0");
+        Serial.print(dmpData[k], HEX);
+        Serial.print(" ");
+    }
+    Serial.print("\n");*/
+    //Serial.println((uint16_t)dmpPacketBuffer);
+    return 0;
+}
+uint8_t MPU6050::dmpReadAndProcessFIFOPacket(uint8_t numPackets, uint8_t *processed) {
+    uint8_t status;
+    uint8_t buf[dmpPacketSize];
+    for (uint8_t i = 0; i < numPackets; i++) {
+        // read packet from FIFO
+        getFIFOBytes(buf, dmpPacketSize);
+
+        // process packet
+        if ((status = dmpProcessFIFOPacket(buf)) > 0) return status;
+        
+        // increment external process count variable, if supplied
+        if (processed != 0) *processed++;
+    }
+    return 0;
+}
+
+// uint8_t MPU6050::dmpSetFIFOProcessedCallback(void (*func) (void));
+
+// uint8_t MPU6050::dmpInitFIFOParam();
+// uint8_t MPU6050::dmpCloseFIFO();
+// uint8_t MPU6050::dmpSetGyroDataSource(uint_fast8_t source);
+// uint8_t MPU6050::dmpDecodeQuantizedAccel();
+// uint32_t MPU6050::dmpGetGyroSumOfSquare();
+// uint32_t MPU6050::dmpGetAccelSumOfSquare();
+// void MPU6050::dmpOverrideQuaternion(long *q);
+uint16_t MPU6050::dmpGetFIFOPacketSize() {
+    return dmpPacketSize;
+}
+
+#endif /* _MPU6050_9AXIS_MOTIONAPPS41_H_ */
diff --git a/hardware/digistump/sam/libraries/MPU6050/helper_3dmath.h b/hardware/digistump/sam/libraries/MPU6050/helper_3dmath.h
new file mode 100644
index 0000000..9ed260e
--- /dev/null
+++ b/hardware/digistump/sam/libraries/MPU6050/helper_3dmath.h
@@ -0,0 +1,216 @@
+// I2C device class (I2Cdev) demonstration Arduino sketch for MPU6050 class, 3D math helper
+// 6/5/2012 by Jeff Rowberg 
+// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib
+//
+// Changelog:
+//     2012-06-05 - add 3D math helper file to DMP6 example sketch
+
+/* ============================================
+I2Cdev device library code is placed under the MIT license
+Copyright (c) 2012 Jeff Rowberg
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+===============================================
+*/
+
+#ifndef _HELPER_3DMATH_H_
+#define _HELPER_3DMATH_H_
+
+class Quaternion {
+    public:
+        float w;
+        float x;
+        float y;
+        float z;
+        
+        Quaternion() {
+            w = 1.0f;
+            x = 0.0f;
+            y = 0.0f;
+            z = 0.0f;
+        }
+        
+        Quaternion(float nw, float nx, float ny, float nz) {
+            w = nw;
+            x = nx;
+            y = ny;
+            z = nz;
+        }
+
+        Quaternion getProduct(Quaternion q) {
+            // Quaternion multiplication is defined by:
+            //     (Q1 * Q2).w = (w1w2 - x1x2 - y1y2 - z1z2)
+            //     (Q1 * Q2).x = (w1x2 + x1w2 + y1z2 - z1y2)
+            //     (Q1 * Q2).y = (w1y2 - x1z2 + y1w2 + z1x2)
+            //     (Q1 * Q2).z = (w1z2 + x1y2 - y1x2 + z1w2
+            return Quaternion(
+                w*q.w - x*q.x - y*q.y - z*q.z,  // new w
+                w*q.x + x*q.w + y*q.z - z*q.y,  // new x
+                w*q.y - x*q.z + y*q.w + z*q.x,  // new y
+                w*q.z + x*q.y - y*q.x + z*q.w); // new z
+        }
+
+        Quaternion getConjugate() {
+            return Quaternion(w, -x, -y, -z);
+        }
+        
+        float getMagnitude() {
+            return sqrt(w*w + x*x + y*y + z*z);
+        }
+        
+        void normalize() {
+            float m = getMagnitude();
+            w /= m;
+            x /= m;
+            y /= m;
+            z /= m;
+        }
+        
+        Quaternion getNormalized() {
+            Quaternion r(w, x, y, z);
+            r.normalize();
+            return r;
+        }
+};
+
+class VectorInt16 {
+    public:
+        int16_t x;
+        int16_t y;
+        int16_t z;
+
+        VectorInt16() {
+            x = 0;
+            y = 0;
+            z = 0;
+        }
+        
+        VectorInt16(int16_t nx, int16_t ny, int16_t nz) {
+            x = nx;
+            y = ny;
+            z = nz;
+        }
+
+        float getMagnitude() {
+            return sqrt(x*x + y*y + z*z);
+        }
+
+        void normalize() {
+            float m = getMagnitude();
+            x /= m;
+            y /= m;
+            z /= m;
+        }
+        
+        VectorInt16 getNormalized() {
+            VectorInt16 r(x, y, z);
+            r.normalize();
+            return r;
+        }
+        
+        void rotate(Quaternion *q) {
+            // http://www.cprogramming.com/tutorial/3d/quaternions.html
+            // http://www.euclideanspace.com/maths/algebra/realNormedAlgebra/quaternions/transforms/index.htm
+            // http://content.gpwiki.org/index.php/OpenGL:Tutorials:Using_Quaternions_to_represent_rotation
+            // ^ or: http://webcache.googleusercontent.com/search?q=cache:xgJAp3bDNhQJ:content.gpwiki.org/index.php/OpenGL:Tutorials:Using_Quaternions_to_represent_rotation&hl=en&gl=us&strip=1
+        
+            // P_out = q * P_in * conj(q)
+            // - P_out is the output vector
+            // - q is the orientation quaternion
+            // - P_in is the input vector (a*aReal)
+            // - conj(q) is the conjugate of the orientation quaternion (q=[w,x,y,z], q*=[w,-x,-y,-z])
+            Quaternion p(0, x, y, z);
+
+            // quaternion multiplication: q * p, stored back in p
+            p = q -> getProduct(p);
+
+            // quaternion multiplication: p * conj(q), stored back in p
+            p = p.getProduct(q -> getConjugate());
+
+            // p quaternion is now [0, x', y', z']
+            x = p.x;
+            y = p.y;
+            z = p.z;
+        }
+
+        VectorInt16 getRotated(Quaternion *q) {
+            VectorInt16 r(x, y, z);
+            r.rotate(q);
+            return r;
+        }
+};
+
+class VectorFloat {
+    public:
+        float x;
+        float y;
+        float z;
+
+        VectorFloat() {
+            x = 0;
+            y = 0;
+            z = 0;
+        }
+        
+        VectorFloat(float nx, float ny, float nz) {
+            x = nx;
+            y = ny;
+            z = nz;
+        }
+
+        float getMagnitude() {
+            return sqrt(x*x + y*y + z*z);
+        }
+
+        void normalize() {
+            float m = getMagnitude();
+            x /= m;
+            y /= m;
+            z /= m;
+        }
+        
+        VectorFloat getNormalized() {
+            VectorFloat r(x, y, z);
+            r.normalize();
+            return r;
+        }
+        
+        void rotate(Quaternion *q) {
+            Quaternion p(0, x, y, z);
+
+            // quaternion multiplication: q * p, stored back in p
+            p = q -> getProduct(p);
+
+            // quaternion multiplication: p * conj(q), stored back in p
+            p = p.getProduct(q -> getConjugate());
+
+            // p quaternion is now [0, x', y', z']
+            x = p.x;
+            y = p.y;
+            z = p.z;
+        }
+
+        VectorFloat getRotated(Quaternion *q) {
+            VectorFloat r(x, y, z);
+            r.rotate(q);
+            return r;
+        }
+};
+
+#endif /* _HELPER_3DMATH_H_ */
\ No newline at end of file
diff --git a/hardware/digistump/sam/libraries/OneWire/OneWire.cpp b/hardware/digistump/sam/libraries/OneWire/OneWire.cpp
new file mode 100644
index 0000000..631813f
--- /dev/null
+++ b/hardware/digistump/sam/libraries/OneWire/OneWire.cpp
@@ -0,0 +1,557 @@
+/*
+Copyright (c) 2007, Jim Studt  (original old version - many contributors since)
+
+The latest version of this library may be found at:
+  http://www.pjrc.com/teensy/td_libs_OneWire.html
+
+OneWire has been maintained by Paul Stoffregen (paul@pjrc.com) since
+January 2010.  At the time, it was in need of many bug fixes, but had
+been abandoned the original author (Jim Studt).  None of the known
+contributors were interested in maintaining OneWire.  Paul typically
+works on OneWire every 6 to 12 months.  Patches usually wait that
+long.  If anyone is interested in more actively maintaining OneWire,
+please contact Paul.
+
+Version 2.2:
+  Teensy 3.0 compatibility, Paul Stoffregen, paul@pjrc.com
+  Arduino Due compatibility, http://arduino.cc/forum/index.php?topic=141030
+  Fix DS18B20 example negative temperature
+  Fix DS18B20 example's low res modes, Ken Butcher
+  Improve reset timing, Mark Tillotson
+  Add const qualifiers, Bertrik Sikken
+  Add initial value input to crc16, Bertrik Sikken
+  Add target_search() function, Scott Roberts
+
+Version 2.1:
+  Arduino 1.0 compatibility, Paul Stoffregen
+  Improve temperature example, Paul Stoffregen
+  DS250x_PROM example, Guillermo Lovato
+  PIC32 (chipKit) compatibility, Jason Dangel, dangel.jason AT gmail.com
+  Improvements from Glenn Trewitt:
+  - crc16() now works
+  - check_crc16() does all of calculation/checking work.
+  - Added read_bytes() and write_bytes(), to reduce tedious loops.
+  - Added ds2408 example.
+  Delete very old, out-of-date readme file (info is here)
+
+Version 2.0: Modifications by Paul Stoffregen, January 2010:
+http://www.pjrc.com/teensy/td_libs_OneWire.html
+  Search fix from Robin James
+    http://www.arduino.cc/cgi-bin/yabb2/YaBB.pl?num=1238032295/27#27
+  Use direct optimized I/O in all cases
+  Disable interrupts during timing critical sections
+    (this solves many random communication errors)
+  Disable interrupts during read-modify-write I/O
+  Reduce RAM consumption by eliminating unnecessary
+    variables and trimming many to 8 bits
+  Optimize both crc8 - table version moved to flash
+
+Modified to work with larger numbers of devices - avoids loop.
+Tested in Arduino 11 alpha with 12 sensors.
+26 Sept 2008 -- Robin James
+http://www.arduino.cc/cgi-bin/yabb2/YaBB.pl?num=1238032295/27#27
+
+Updated to work with arduino-0008 and to include skip() as of
+2007/07/06. --RJL20
+
+Modified to calculate the 8-bit CRC directly, avoiding the need for
+the 256-byte lookup table to be loaded in RAM.  Tested in arduino-0010
+-- Tom Pollard, Jan 23, 2008
+
+Jim Studt's original library was modified by Josh Larios.
+
+Tom Pollard, pollard@alum.mit.edu, contributed around May 20, 2008
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be
+included in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+Much of the code was inspired by Derek Yerger's code, though I don't
+think much of that remains.  In any event that was..
+    (copyleft) 2006 by Derek Yerger - Free to distribute freely.
+
+The CRC code was excerpted and inspired by the Dallas Semiconductor
+sample code bearing this copyright.
+//---------------------------------------------------------------------------
+// Copyright (C) 2000 Dallas Semiconductor Corporation, All Rights Reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a
+// copy of this software and associated documentation files (the "Software"),
+// to deal in the Software without restriction, including without limitation
+// the rights to use, copy, modify, merge, publish, distribute, sublicense,
+// and/or sell copies of the Software, and to permit persons to whom the
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY,  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL DALLAS SEMICONDUCTOR BE LIABLE FOR ANY CLAIM, DAMAGES
+// OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+// OTHER DEALINGS IN THE SOFTWARE.
+//
+// Except as contained in this notice, the name of Dallas Semiconductor
+// shall not be used except as stated in the Dallas Semiconductor
+// Branding Policy.
+//--------------------------------------------------------------------------
+*/
+
+#include "OneWire.h"
+
+
+OneWire::OneWire(uint8_t pin)
+{
+	pinMode(pin, INPUT);
+	bitmask = PIN_TO_BITMASK(pin);
+	baseReg = PIN_TO_BASEREG(pin);
+#if ONEWIRE_SEARCH
+	reset_search();
+#endif
+}
+
+
+// Perform the onewire reset function.  We will wait up to 250uS for
+// the bus to come high, if it doesn't then it is broken or shorted
+// and we return a 0;
+//
+// Returns 1 if a device asserted a presence pulse, 0 otherwise.
+//
+uint8_t OneWire::reset(void)
+{
+	IO_REG_TYPE mask = bitmask;
+	volatile IO_REG_TYPE *reg IO_REG_ASM = baseReg;
+	uint8_t r;
+	uint8_t retries = 125;
+
+	noInterrupts();
+	DIRECT_MODE_INPUT(reg, mask);
+	interrupts();
+	// wait until the wire is high... just in case
+	do {
+		if (--retries == 0) return 0;
+		delayMicroseconds(2);
+	} while ( !DIRECT_READ(reg, mask));
+
+	noInterrupts();
+	DIRECT_WRITE_LOW(reg, mask);
+	DIRECT_MODE_OUTPUT(reg, mask);	// drive output low
+	interrupts();
+	delayMicroseconds(480);
+	noInterrupts();
+	DIRECT_MODE_INPUT(reg, mask);	// allow it to float
+	delayMicroseconds(70);
+	r = !DIRECT_READ(reg, mask);
+	interrupts();
+	delayMicroseconds(410);
+	return r;
+}
+
+//
+// Write a bit. Port and bit is used to cut lookup time and provide
+// more certain timing.
+//
+void OneWire::write_bit(uint8_t v)
+{
+	IO_REG_TYPE mask=bitmask;
+	volatile IO_REG_TYPE *reg IO_REG_ASM = baseReg;
+
+	if (v & 1) {
+		noInterrupts();
+		DIRECT_WRITE_LOW(reg, mask);
+		DIRECT_MODE_OUTPUT(reg, mask);	// drive output low
+		delayMicroseconds(10);
+		DIRECT_WRITE_HIGH(reg, mask);	// drive output high
+		interrupts();
+		delayMicroseconds(55);
+	} else {
+		noInterrupts();
+		DIRECT_WRITE_LOW(reg, mask);
+		DIRECT_MODE_OUTPUT(reg, mask);	// drive output low
+		delayMicroseconds(65);
+		DIRECT_WRITE_HIGH(reg, mask);	// drive output high
+		interrupts();
+		delayMicroseconds(5);
+	}
+}
+
+//
+// Read a bit. Port and bit is used to cut lookup time and provide
+// more certain timing.
+//
+uint8_t OneWire::read_bit(void)
+{
+	IO_REG_TYPE mask=bitmask;
+	volatile IO_REG_TYPE *reg IO_REG_ASM = baseReg;
+	uint8_t r;
+
+	noInterrupts();
+	DIRECT_MODE_OUTPUT(reg, mask);
+	DIRECT_WRITE_LOW(reg, mask);
+	delayMicroseconds(3);
+	DIRECT_MODE_INPUT(reg, mask);	// let pin float, pull up will raise
+	delayMicroseconds(10);
+	r = DIRECT_READ(reg, mask);
+	interrupts();
+	delayMicroseconds(53);
+	return r;
+}
+
+//
+// Write a byte. The writing code uses the active drivers to raise the
+// pin high, if you need power after the write (e.g. DS18S20 in
+// parasite power mode) then set 'power' to 1, otherwise the pin will
+// go tri-state at the end of the write to avoid heating in a short or
+// other mishap.
+//
+void OneWire::write(uint8_t v, uint8_t power /* = 0 */) {
+    uint8_t bitMask;
+
+    for (bitMask = 0x01; bitMask; bitMask <<= 1) {
+	OneWire::write_bit( (bitMask & v)?1:0);
+    }
+    if ( !power) {
+	noInterrupts();
+	DIRECT_MODE_INPUT(baseReg, bitmask);
+	DIRECT_WRITE_LOW(baseReg, bitmask);
+	interrupts();
+    }
+}
+
+void OneWire::write_bytes(const uint8_t *buf, uint16_t count, bool power /* = 0 */) {
+  for (uint16_t i = 0 ; i < count ; i++)
+    write(buf[i]);
+  if (!power) {
+    noInterrupts();
+    DIRECT_MODE_INPUT(baseReg, bitmask);
+    DIRECT_WRITE_LOW(baseReg, bitmask);
+    interrupts();
+  }
+}
+
+//
+// Read a byte
+//
+uint8_t OneWire::read() {
+    uint8_t bitMask;
+    uint8_t r = 0;
+
+    for (bitMask = 0x01; bitMask; bitMask <<= 1) {
+	if ( OneWire::read_bit()) r |= bitMask;
+    }
+    return r;
+}
+
+void OneWire::read_bytes(uint8_t *buf, uint16_t count) {
+  for (uint16_t i = 0 ; i < count ; i++)
+    buf[i] = read();
+}
+
+//
+// Do a ROM select
+//
+void OneWire::select(const uint8_t rom[8])
+{
+    uint8_t i;
+
+    write(0x55);           // Choose ROM
+
+    for (i = 0; i < 8; i++) write(rom[i]);
+}
+
+//
+// Do a ROM skip
+//
+void OneWire::skip()
+{
+    write(0xCC);           // Skip ROM
+}
+
+void OneWire::depower()
+{
+	noInterrupts();
+	DIRECT_MODE_INPUT(baseReg, bitmask);
+	interrupts();
+}
+
+#if ONEWIRE_SEARCH
+
+//
+// You need to use this function to start a search again from the beginning.
+// You do not need to do it for the first search, though you could.
+//
+void OneWire::reset_search()
+{
+  // reset the search state
+  LastDiscrepancy = 0;
+  LastDeviceFlag = FALSE;
+  LastFamilyDiscrepancy = 0;
+  for(int i = 7; ; i--) {
+    ROM_NO[i] = 0;
+    if ( i == 0) break;
+  }
+}
+
+// Setup the search to find the device type 'family_code' on the next call
+// to search(*newAddr) if it is present.
+//
+void OneWire::target_search(uint8_t family_code)
+{
+   // set the search state to find SearchFamily type devices
+   ROM_NO[0] = family_code;
+   for (uint8_t i = 1; i < 8; i++)
+      ROM_NO[i] = 0;
+   LastDiscrepancy = 64;
+   LastFamilyDiscrepancy = 0;
+   LastDeviceFlag = FALSE;
+}
+
+//
+// Perform a search. If this function returns a '1' then it has
+// enumerated the next device and you may retrieve the ROM from the
+// OneWire::address variable. If there are no devices, no further
+// devices, or something horrible happens in the middle of the
+// enumeration then a 0 is returned.  If a new device is found then
+// its address is copied to newAddr.  Use OneWire::reset_search() to
+// start over.
+//
+// --- Replaced by the one from the Dallas Semiconductor web site ---
+//--------------------------------------------------------------------------
+// Perform the 1-Wire Search Algorithm on the 1-Wire bus using the existing
+// search state.
+// Return TRUE  : device found, ROM number in ROM_NO buffer
+//        FALSE : device not found, end of search
+//
+uint8_t OneWire::search(uint8_t *newAddr)
+{
+   uint8_t id_bit_number;
+   uint8_t last_zero, rom_byte_number, search_result;
+   uint8_t id_bit, cmp_id_bit;
+
+   unsigned char rom_byte_mask, search_direction;
+
+   // initialize for search
+   id_bit_number = 1;
+   last_zero = 0;
+   rom_byte_number = 0;
+   rom_byte_mask = 1;
+   search_result = 0;
+
+   // if the last call was not the last one
+   if (!LastDeviceFlag)
+   {
+      // 1-Wire reset
+      if (!reset())
+      {
+         // reset the search
+         LastDiscrepancy = 0;
+         LastDeviceFlag = FALSE;
+         LastFamilyDiscrepancy = 0;
+         return FALSE;
+      }
+
+      // issue the search command
+      write(0xF0);
+
+      // loop to do the search
+      do
+      {
+         // read a bit and its complement
+         id_bit = read_bit();
+         cmp_id_bit = read_bit();
+
+         // check for no devices on 1-wire
+         if ((id_bit == 1) && (cmp_id_bit == 1))
+            break;
+         else
+         {
+            // all devices coupled have 0 or 1
+            if (id_bit != cmp_id_bit)
+               search_direction = id_bit;  // bit write value for search
+            else
+            {
+               // if this discrepancy if before the Last Discrepancy
+               // on a previous next then pick the same as last time
+               if (id_bit_number < LastDiscrepancy)
+                  search_direction = ((ROM_NO[rom_byte_number] & rom_byte_mask) > 0);
+               else
+                  // if equal to last pick 1, if not then pick 0
+                  search_direction = (id_bit_number == LastDiscrepancy);
+
+               // if 0 was picked then record its position in LastZero
+               if (search_direction == 0)
+               {
+                  last_zero = id_bit_number;
+
+                  // check for Last discrepancy in family
+                  if (last_zero < 9)
+                     LastFamilyDiscrepancy = last_zero;
+               }
+            }
+
+            // set or clear the bit in the ROM byte rom_byte_number
+            // with mask rom_byte_mask
+            if (search_direction == 1)
+              ROM_NO[rom_byte_number] |= rom_byte_mask;
+            else
+              ROM_NO[rom_byte_number] &= ~rom_byte_mask;
+
+            // serial number search direction write bit
+            write_bit(search_direction);
+
+            // increment the byte counter id_bit_number
+            // and shift the mask rom_byte_mask
+            id_bit_number++;
+            rom_byte_mask <<= 1;
+
+            // if the mask is 0 then go to new SerialNum byte rom_byte_number and reset mask
+            if (rom_byte_mask == 0)
+            {
+                rom_byte_number++;
+                rom_byte_mask = 1;
+            }
+         }
+      }
+      while(rom_byte_number < 8);  // loop until through all ROM bytes 0-7
+
+      // if the search was successful then
+      if (!(id_bit_number < 65))
+      {
+         // search successful so set LastDiscrepancy,LastDeviceFlag,search_result
+         LastDiscrepancy = last_zero;
+
+         // check for last device
+         if (LastDiscrepancy == 0)
+            LastDeviceFlag = TRUE;
+
+         search_result = TRUE;
+      }
+   }
+
+   // if no device found then reset counters so next 'search' will be like a first
+   if (!search_result || !ROM_NO[0])
+   {
+      LastDiscrepancy = 0;
+      LastDeviceFlag = FALSE;
+      LastFamilyDiscrepancy = 0;
+      search_result = FALSE;
+   }
+   for (int i = 0; i < 8; i++) newAddr[i] = ROM_NO[i];
+   return search_result;
+  }
+
+#endif
+
+#if ONEWIRE_CRC
+// The 1-Wire CRC scheme is described in Maxim Application Note 27:
+// "Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products"
+//
+
+#if ONEWIRE_CRC8_TABLE
+// This table comes from Dallas sample code where it is freely reusable,
+// though Copyright (C) 2000 Dallas Semiconductor Corporation
+static const uint8_t PROGMEM dscrc_table[] = {
+      0, 94,188,226, 97, 63,221,131,194,156,126, 32,163,253, 31, 65,
+    157,195, 33,127,252,162, 64, 30, 95,  1,227,189, 62, 96,130,220,
+     35,125,159,193, 66, 28,254,160,225,191, 93,  3,128,222, 60, 98,
+    190,224,  2, 92,223,129, 99, 61,124, 34,192,158, 29, 67,161,255,
+     70, 24,250,164, 39,121,155,197,132,218, 56,102,229,187, 89,  7,
+    219,133,103, 57,186,228,  6, 88, 25, 71,165,251,120, 38,196,154,
+    101, 59,217,135,  4, 90,184,230,167,249, 27, 69,198,152,122, 36,
+    248,166, 68, 26,153,199, 37,123, 58,100,134,216, 91,  5,231,185,
+    140,210, 48,110,237,179, 81, 15, 78, 16,242,172, 47,113,147,205,
+     17, 79,173,243,112, 46,204,146,211,141,111, 49,178,236, 14, 80,
+    175,241, 19, 77,206,144,114, 44,109, 51,209,143, 12, 82,176,238,
+     50,108,142,208, 83, 13,239,177,240,174, 76, 18,145,207, 45,115,
+    202,148,118, 40,171,245, 23, 73,  8, 86,180,234,105, 55,213,139,
+     87,  9,235,181, 54,104,138,212,149,203, 41,119,244,170, 72, 22,
+    233,183, 85, 11,136,214, 52,106, 43,117,151,201, 74, 20,246,168,
+    116, 42,200,150, 21, 75,169,247,182,232, 10, 84,215,137,107, 53};
+
+//
+// Compute a Dallas Semiconductor 8 bit CRC. These show up in the ROM
+// and the registers.  (note: this might better be done without to
+// table, it would probably be smaller and certainly fast enough
+// compared to all those delayMicrosecond() calls.  But I got
+// confused, so I use this table from the examples.)
+//
+uint8_t OneWire::crc8(const uint8_t *addr, uint8_t len)
+{
+	uint8_t crc = 0;
+
+	while (len--) {
+		crc = pgm_read_byte(dscrc_table + (crc ^ *addr++));
+	}
+	return crc;
+}
+#else
+//
+// Compute a Dallas Semiconductor 8 bit CRC directly.
+// this is much slower, but much smaller, than the lookup table.
+//
+uint8_t OneWire::crc8(const uint8_t *addr, uint8_t len)
+{
+	uint8_t crc = 0;
+	
+	while (len--) {
+		uint8_t inbyte = *addr++;
+		for (uint8_t i = 8; i; i--) {
+			uint8_t mix = (crc ^ inbyte) & 0x01;
+			crc >>= 1;
+			if (mix) crc ^= 0x8C;
+			inbyte >>= 1;
+		}
+	}
+	return crc;
+}
+#endif
+
+#if ONEWIRE_CRC16
+bool OneWire::check_crc16(const uint8_t* input, uint16_t len, const uint8_t* inverted_crc, uint16_t crc)
+{
+    crc = ~crc16(input, len, crc);
+    return (crc & 0xFF) == inverted_crc[0] && (crc >> 8) == inverted_crc[1];
+}
+
+uint16_t OneWire::crc16(const uint8_t* input, uint16_t len, uint16_t crc)
+{
+    static const uint8_t oddparity[16] =
+        { 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0 };
+
+    for (uint16_t i = 0 ; i < len ; i++) {
+      // Even though we're just copying a byte from the input,
+      // we'll be doing 16-bit computation with it.
+      uint16_t cdata = input[i];
+      cdata = (cdata ^ crc) & 0xff;
+      crc >>= 8;
+
+      if (oddparity[cdata & 0x0F] ^ oddparity[cdata >> 4])
+          crc ^= 0xC001;
+
+      cdata <<= 6;
+      crc ^= cdata;
+      cdata <<= 1;
+      crc ^= cdata;
+    }
+    return crc;
+}
+#endif
+
+#endif
diff --git a/hardware/digistump/sam/libraries/OneWire/OneWire.h b/hardware/digistump/sam/libraries/OneWire/OneWire.h
new file mode 100644
index 0000000..916c529
--- /dev/null
+++ b/hardware/digistump/sam/libraries/OneWire/OneWire.h
@@ -0,0 +1,229 @@
+#ifndef OneWire_h
+#define OneWire_h
+
+#include 
+
+#if ARDUINO >= 100
+#include "Arduino.h"       // for delayMicroseconds, digitalPinToBitMask, etc
+#else
+#include "WProgram.h"      // for delayMicroseconds
+#include "pins_arduino.h"  // for digitalPinToBitMask, etc
+#endif
+
+// You can exclude certain features from OneWire.  In theory, this
+// might save some space.  In practice, the compiler automatically
+// removes unused code (technically, the linker, using -fdata-sections
+// and -ffunction-sections when compiling, and Wl,--gc-sections
+// when linking), so most of these will not result in any code size
+// reduction.  Well, unless you try to use the missing features
+// and redesign your program to not need them!  ONEWIRE_CRC8_TABLE
+// is the exception, because it selects a fast but large algorithm
+// or a small but slow algorithm.
+
+// you can exclude onewire_search by defining that to 0
+#ifndef ONEWIRE_SEARCH
+#define ONEWIRE_SEARCH 1
+#endif
+
+// You can exclude CRC checks altogether by defining this to 0
+#ifndef ONEWIRE_CRC
+#define ONEWIRE_CRC 1
+#endif
+
+// Select the table-lookup method of computing the 8-bit CRC
+// by setting this to 1.  The lookup table enlarges code size by
+// about 250 bytes.  It does NOT consume RAM (but did in very
+// old versions of OneWire).  If you disable this, a slower
+// but very compact algorithm is used.
+#ifndef ONEWIRE_CRC8_TABLE
+#define ONEWIRE_CRC8_TABLE 1
+#endif
+
+// You can allow 16-bit CRC checks by defining this to 1
+// (Note that ONEWIRE_CRC must also be 1.)
+#ifndef ONEWIRE_CRC16
+#define ONEWIRE_CRC16 1
+#endif
+
+#define FALSE 0
+#define TRUE  1
+
+// Platform specific I/O definitions
+
+#if defined(__AVR__)
+#define PIN_TO_BASEREG(pin)             (portInputRegister(digitalPinToPort(pin)))
+#define PIN_TO_BITMASK(pin)             (digitalPinToBitMask(pin))
+#define IO_REG_TYPE uint8_t
+#define IO_REG_ASM asm("r30")
+#define DIRECT_READ(base, mask)         (((*(base)) & (mask)) ? 1 : 0)
+#define DIRECT_MODE_INPUT(base, mask)   ((*((base)+1)) &= ~(mask))
+#define DIRECT_MODE_OUTPUT(base, mask)  ((*((base)+1)) |= (mask))
+#define DIRECT_WRITE_LOW(base, mask)    ((*((base)+2)) &= ~(mask))
+#define DIRECT_WRITE_HIGH(base, mask)   ((*((base)+2)) |= (mask))
+
+#elif defined(__MK20DX128__)
+#define PIN_TO_BASEREG(pin)             (portOutputRegister(pin))
+#define PIN_TO_BITMASK(pin)             (1)
+#define IO_REG_TYPE uint8_t
+#define IO_REG_ASM
+#define DIRECT_READ(base, mask)         (*((base)+512))
+#define DIRECT_MODE_INPUT(base, mask)   (*((base)+640) = 0)
+#define DIRECT_MODE_OUTPUT(base, mask)  (*((base)+640) = 1)
+#define DIRECT_WRITE_LOW(base, mask)    (*((base)+256) = 1)
+#define DIRECT_WRITE_HIGH(base, mask)   (*((base)+128) = 1)
+
+#elif defined(__SAM3X8E__)
+// Arduino 1.5.1 may have a bug in delayMicroseconds() on Arduino Due.
+// http://arduino.cc/forum/index.php/topic,141030.msg1076268.html#msg1076268
+// If you have trouble with OneWire on Arduino Due, please check the
+// status of delayMicroseconds() before reporting a bug in OneWire!
+#define PIN_TO_BASEREG(pin)             (&(digitalPinToPort(pin)->PIO_PER))
+#define PIN_TO_BITMASK(pin)             (digitalPinToBitMask(pin))
+#define IO_REG_TYPE uint32_t
+#define IO_REG_ASM
+#define DIRECT_READ(base, mask)         (((*((base)+15)) & (mask)) ? 1 : 0)
+#define DIRECT_MODE_INPUT(base, mask)   ((*((base)+5)) = (mask))
+#define DIRECT_MODE_OUTPUT(base, mask)  ((*((base)+4)) = (mask))
+#define DIRECT_WRITE_LOW(base, mask)    ((*((base)+13)) = (mask))
+#define DIRECT_WRITE_HIGH(base, mask)   ((*((base)+12)) = (mask))
+#ifndef PROGMEM
+#define PROGMEM
+#endif
+#ifndef pgm_read_byte
+#define pgm_read_byte(addr) (*(const uint8_t *)(addr))
+#endif
+
+#elif defined(__PIC32MX__)
+#define PIN_TO_BASEREG(pin)             (portModeRegister(digitalPinToPort(pin)))
+#define PIN_TO_BITMASK(pin)             (digitalPinToBitMask(pin))
+#define IO_REG_TYPE uint32_t
+#define IO_REG_ASM
+#define DIRECT_READ(base, mask)         (((*(base+4)) & (mask)) ? 1 : 0)  //PORTX + 0x10
+#define DIRECT_MODE_INPUT(base, mask)   ((*(base+2)) = (mask))            //TRISXSET + 0x08
+#define DIRECT_MODE_OUTPUT(base, mask)  ((*(base+1)) = (mask))            //TRISXCLR + 0x04
+#define DIRECT_WRITE_LOW(base, mask)    ((*(base+8+1)) = (mask))          //LATXCLR  + 0x24
+#define DIRECT_WRITE_HIGH(base, mask)   ((*(base+8+2)) = (mask))          //LATXSET + 0x28
+
+#else
+#error "Please define I/O register types here"
+#endif
+
+
+class OneWire
+{
+  private:
+    IO_REG_TYPE bitmask;
+    volatile IO_REG_TYPE *baseReg;
+
+#if ONEWIRE_SEARCH
+    // global search state
+    unsigned char ROM_NO[8];
+    uint8_t LastDiscrepancy;
+    uint8_t LastFamilyDiscrepancy;
+    uint8_t LastDeviceFlag;
+#endif
+
+  public:
+    OneWire( uint8_t pin);
+
+    // Perform a 1-Wire reset cycle. Returns 1 if a device responds
+    // with a presence pulse.  Returns 0 if there is no device or the
+    // bus is shorted or otherwise held low for more than 250uS
+    uint8_t reset(void);
+
+    // Issue a 1-Wire rom select command, you do the reset first.
+    void select(const uint8_t rom[8]);
+
+    // Issue a 1-Wire rom skip command, to address all on bus.
+    void skip(void);
+
+    // Write a byte. If 'power' is one then the wire is held high at
+    // the end for parasitically powered devices. You are responsible
+    // for eventually depowering it by calling depower() or doing
+    // another read or write.
+    void write(uint8_t v, uint8_t power = 0);
+
+    void write_bytes(const uint8_t *buf, uint16_t count, bool power = 0);
+
+    // Read a byte.
+    uint8_t read(void);
+
+    void read_bytes(uint8_t *buf, uint16_t count);
+
+    // Write a bit. The bus is always left powered at the end, see
+    // note in write() about that.
+    void write_bit(uint8_t v);
+
+    // Read a bit.
+    uint8_t read_bit(void);
+
+    // Stop forcing power onto the bus. You only need to do this if
+    // you used the 'power' flag to write() or used a write_bit() call
+    // and aren't about to do another read or write. You would rather
+    // not leave this powered if you don't have to, just in case
+    // someone shorts your bus.
+    void depower(void);
+
+#if ONEWIRE_SEARCH
+    // Clear the search state so that if will start from the beginning again.
+    void reset_search();
+
+    // Setup the search to find the device type 'family_code' on the next call
+    // to search(*newAddr) if it is present.
+    void target_search(uint8_t family_code);
+
+    // Look for the next device. Returns 1 if a new address has been
+    // returned. A zero might mean that the bus is shorted, there are
+    // no devices, or you have already retrieved all of them.  It
+    // might be a good idea to check the CRC to make sure you didn't
+    // get garbage.  The order is deterministic. You will always get
+    // the same devices in the same order.
+    uint8_t search(uint8_t *newAddr);
+#endif
+
+#if ONEWIRE_CRC
+    // Compute a Dallas Semiconductor 8 bit CRC, these are used in the
+    // ROM and scratchpad registers.
+    static uint8_t crc8(const uint8_t *addr, uint8_t len);
+
+#if ONEWIRE_CRC16
+    // Compute the 1-Wire CRC16 and compare it against the received CRC.
+    // Example usage (reading a DS2408):
+    //    // Put everything in a buffer so we can compute the CRC easily.
+    //    uint8_t buf[13];
+    //    buf[0] = 0xF0;    // Read PIO Registers
+    //    buf[1] = 0x88;    // LSB address
+    //    buf[2] = 0x00;    // MSB address
+    //    WriteBytes(net, buf, 3);    // Write 3 cmd bytes
+    //    ReadBytes(net, buf+3, 10);  // Read 6 data bytes, 2 0xFF, 2 CRC16
+    //    if (!CheckCRC16(buf, 11, &buf[11])) {
+    //        // Handle error.
+    //    }     
+    //          
+    // @param input - Array of bytes to checksum.
+    // @param len - How many bytes to use.
+    // @param inverted_crc - The two CRC16 bytes in the received data.
+    //                       This should just point into the received data,
+    //                       *not* at a 16-bit integer.
+    // @param crc - The crc starting value (optional)
+    // @return True, iff the CRC matches.
+    static bool check_crc16(const uint8_t* input, uint16_t len, const uint8_t* inverted_crc, uint16_t crc = 0);
+
+    // Compute a Dallas Semiconductor 16 bit CRC.  This is required to check
+    // the integrity of data received from many 1-Wire devices.  Note that the
+    // CRC computed here is *not* what you'll get from the 1-Wire network,
+    // for two reasons:
+    //   1) The CRC is transmitted bitwise inverted.
+    //   2) Depending on the endian-ness of your processor, the binary
+    //      representation of the two-byte return value may have a different
+    //      byte order than the two bytes you get from 1-Wire.
+    // @param input - Array of bytes to checksum.
+    // @param len - How many bytes to use.
+    // @param crc - The crc starting value (optional)
+    // @return The CRC16, as defined by Dallas Semiconductor.
+    static uint16_t crc16(const uint8_t* input, uint16_t len, uint16_t crc = 0);
+#endif
+#endif
+};
+
+#endif
diff --git a/hardware/digistump/sam/libraries/OneWire/examples/DS18x20_Temperature/DS18x20_Temperature.pde b/hardware/digistump/sam/libraries/OneWire/examples/DS18x20_Temperature/DS18x20_Temperature.pde
new file mode 100644
index 0000000..68ca194
--- /dev/null
+++ b/hardware/digistump/sam/libraries/OneWire/examples/DS18x20_Temperature/DS18x20_Temperature.pde
@@ -0,0 +1,112 @@
+#include 
+
+// OneWire DS18S20, DS18B20, DS1822 Temperature Example
+//
+// http://www.pjrc.com/teensy/td_libs_OneWire.html
+//
+// The DallasTemperature library can do all this work for you!
+// http://milesburton.com/Dallas_Temperature_Control_Library
+
+OneWire  ds(10);  // on pin 10 (a 4.7K resistor is necessary)
+
+void setup(void) {
+  Serial.begin(9600);
+}
+
+void loop(void) {
+  byte i;
+  byte present = 0;
+  byte type_s;
+  byte data[12];
+  byte addr[8];
+  float celsius, fahrenheit;
+  
+  if ( !ds.search(addr)) {
+    Serial.println("No more addresses.");
+    Serial.println();
+    ds.reset_search();
+    delay(250);
+    return;
+  }
+  
+  Serial.print("ROM =");
+  for( i = 0; i < 8; i++) {
+    Serial.write(' ');
+    Serial.print(addr[i], HEX);
+  }
+
+  if (OneWire::crc8(addr, 7) != addr[7]) {
+      Serial.println("CRC is not valid!");
+      return;
+  }
+  Serial.println();
+ 
+  // the first ROM byte indicates which chip
+  switch (addr[0]) {
+    case 0x10:
+      Serial.println("  Chip = DS18S20");  // or old DS1820
+      type_s = 1;
+      break;
+    case 0x28:
+      Serial.println("  Chip = DS18B20");
+      type_s = 0;
+      break;
+    case 0x22:
+      Serial.println("  Chip = DS1822");
+      type_s = 0;
+      break;
+    default:
+      Serial.println("Device is not a DS18x20 family device.");
+      return;
+  } 
+
+  ds.reset();
+  ds.select(addr);
+  ds.write(0x44, 1);        // start conversion, with parasite power on at the end
+  
+  delay(1000);     // maybe 750ms is enough, maybe not
+  // we might do a ds.depower() here, but the reset will take care of it.
+  
+  present = ds.reset();
+  ds.select(addr);    
+  ds.write(0xBE);         // Read Scratchpad
+
+  Serial.print("  Data = ");
+  Serial.print(present, HEX);
+  Serial.print(" ");
+  for ( i = 0; i < 9; i++) {           // we need 9 bytes
+    data[i] = ds.read();
+    Serial.print(data[i], HEX);
+    Serial.print(" ");
+  }
+  Serial.print(" CRC=");
+  Serial.print(OneWire::crc8(data, 8), HEX);
+  Serial.println();
+
+  // Convert the data to actual temperature
+  // because the result is a 16 bit signed integer, it should
+  // be stored to an "int16_t" type, which is always 16 bits
+  // even when compiled on a 32 bit processor.
+  int16_t raw = (data[1] << 8) | data[0];
+  if (type_s) {
+    raw = raw << 3; // 9 bit resolution default
+    if (data[7] == 0x10) {
+      // "count remain" gives full 12 bit resolution
+      raw = (raw & 0xFFF0) + 12 - data[6];
+    }
+  } else {
+    byte cfg = (data[4] & 0x60);
+    // at lower res, the low bits are undefined, so let's zero them
+    if (cfg == 0x00) raw = raw & ~7;  // 9 bit resolution, 93.75 ms
+    else if (cfg == 0x20) raw = raw & ~3; // 10 bit res, 187.5 ms
+    else if (cfg == 0x40) raw = raw & ~1; // 11 bit res, 375 ms
+    //// default is 12 bit resolution, 750 ms conversion time
+  }
+  celsius = (float)raw / 16.0;
+  fahrenheit = celsius * 1.8 + 32.0;
+  Serial.print("  Temperature = ");
+  Serial.print(celsius);
+  Serial.print(" Celsius, ");
+  Serial.print(fahrenheit);
+  Serial.println(" Fahrenheit");
+}
diff --git a/hardware/digistump/sam/libraries/OneWire/examples/DS2408_Switch/DS2408_Switch.pde b/hardware/digistump/sam/libraries/OneWire/examples/DS2408_Switch/DS2408_Switch.pde
new file mode 100644
index 0000000..d171f9b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/OneWire/examples/DS2408_Switch/DS2408_Switch.pde
@@ -0,0 +1,77 @@
+#include 
+
+/*
+ * DS2408 8-Channel Addressable Switch
+ *
+ * Writte by Glenn Trewitt, glenn at trewitt dot org
+ *
+ * Some notes about the DS2408:
+ *   - Unlike most input/output ports, the DS2408 doesn't have mode bits to
+ *       set whether the pins are input or output.  If you issue a read command,
+ *       they're inputs.  If you write to them, they're outputs.
+ *   - For reading from a switch, you should use 10K pull-up resisters.
+ */
+
+void PrintBytes(uint8_t* addr, uint8_t count, bool newline=0) {
+  for (uint8_t i = 0; i < count; i++) {
+    Serial.print(addr[i]>>4, HEX);
+    Serial.print(addr[i]&0x0f, HEX);
+  }
+  if (newline)
+    Serial.println();
+}
+
+void ReadAndReport(OneWire* net, uint8_t* addr) {
+  Serial.print("  Reading DS2408 ");
+  PrintBytes(addr, 8);
+  Serial.println();
+	
+  uint8_t buf[13];  // Put everything in the buffer so we can compute CRC easily.
+  buf[0] = 0xF0;    // Read PIO Registers
+  buf[1] = 0x88;    // LSB address
+  buf[2] = 0x00;    // MSB address
+  net->write_bytes(buf, 3);
+  net->read_bytes(buf+3, 10);     // 3 cmd bytes, 6 data bytes, 2 0xFF, 2 CRC16
+  net->reset();
+
+  if (!OneWire::check_crc16(buf, 11, &buf[11])) {
+    Serial.print("CRC failure in DS2408 at ");
+    PrintBytes(addr, 8, true);
+    return;
+  }
+  Serial.print("  DS2408 data = ");
+  // First 3 bytes contain command, register address.
+  Serial.println(buf[3], BIN);
+}
+
+OneWire net(10);  // on pin 10
+
+void setup(void) {
+  Serial.begin(9600);
+}
+
+void loop(void) {
+  byte i;
+  byte present = 0;
+  byte addr[8];
+  
+  if (!net.search(addr)) {
+    Serial.print("No more addresses.\n");
+    net.reset_search();
+    delay(1000);
+    return;
+  }
+  
+  if (OneWire::crc8(addr, 7) != addr[7]) {
+    Serial.print("CRC is not valid!\n");
+    return;
+  }
+  
+  if (addr[0] != 0x29) {
+    PrintBytes(addr, 8);
+    Serial.print(" is not a DS2408.\n");
+    return;
+  }
+
+  ReadAndReport(&net, addr);
+}
diff --git a/hardware/digistump/sam/libraries/OneWire/examples/DS250x_PROM/DS250x_PROM.pde b/hardware/digistump/sam/libraries/OneWire/examples/DS250x_PROM/DS250x_PROM.pde
new file mode 100644
index 0000000..a85b1c2
--- /dev/null
+++ b/hardware/digistump/sam/libraries/OneWire/examples/DS250x_PROM/DS250x_PROM.pde
@@ -0,0 +1,90 @@
+/*
+DS250x add-only programmable memory reader w/SKIP ROM.
+ 
+ The DS250x is a 512/1024bit add-only PROM(you can add data but cannot change the old one) that's used mainly for device identification purposes
+ like serial number, mfgr data, unique identifiers, etc. It uses the Maxim 1-wire bus.
+ 
+ This sketch will use the SKIP ROM function that skips the 1-Wire search phase since we only have one device connected in the bus on digital pin 6.
+ If more than one device is connected to the bus, it will fail.
+ Sketch will not verify if device connected is from the DS250x family since the skip rom function effectively skips the family-id byte readout.
+ thus it is possible to run this sketch with any Maxim OneWire device in which case the command CRC will most likely fail.
+ Sketch will only read the first page of memory(32bits) starting from the lower address(0000h), if more than 1 device is present, then use the sketch with search functions.
+ Remember to put a 4.7K pullup resistor between pin 6 and +Vcc
+ 
+ To change the range or ammount of data to read, simply change the data array size, LSB/MSB addresses and for loop iterations
+ 
+ This example code is in the public domain and is provided AS-IS.
+ 
+ Built with Arduino 0022 and PJRC OneWire 2.0 library http://www.pjrc.com/teensy/td_libs_OneWire.html
+ 
+ created by Guillermo Lovato 
+ march/2011
+ 
+ */
+
+#include 
+OneWire ds(6);                    // OneWire bus on digital pin 6
+void setup() {
+  Serial.begin (9600);
+}
+
+void loop() {
+  byte i;                         // This is for the for loops
+  boolean present;                // device present var
+  byte data[32];                  // container for the data from device
+  byte leemem[3] = {              // array with the commands to initiate a read, DS250x devices expect 3 bytes to start a read: command,LSB&MSB adresses
+    0xF0 , 0x00 , 0x00   };       // 0xF0 is the Read Data command, followed by 00h 00h as starting address(the beginning, 0000h)
+  byte ccrc;                      // Variable to store the command CRC
+  byte ccrc_calc;
+
+  present = ds.reset();           // OneWire bus reset, always needed to start operation on the bus, returns a 1/TRUE if there's a device present.
+  ds.skip();                      // Skip ROM search
+
+  if (present == TRUE){           // We only try to read the data if there's a device present 
+    Serial.println("DS250x device present");
+    ds.write(leemem[0],1);        // Read data command, leave ghost power on
+    ds.write(leemem[1],1);        // LSB starting address, leave ghost power on
+    ds.write(leemem[2],1);        // MSB starting address, leave ghost power on
+
+    ccrc = ds.read();             // DS250x generates a CRC for the command we sent, we assign a read slot and store it's value
+    ccrc_calc = OneWire::crc8(leemem, 3);  // We calculate the CRC of the commands we sent using the library function and store it
+
+    if ( ccrc_calc != ccrc) {      // Then we compare it to the value the ds250x calculated, if it fails, we print debug messages and abort
+      Serial.println("Invalid command CRC!");
+      Serial.print("Calculated CRC:");
+      Serial.println(ccrc_calc,HEX);    // HEX makes it easier to observe and compare
+      Serial.print("DS250x readback CRC:");
+      Serial.println(ccrc,HEX);
+      return;                      // Since CRC failed, we abort the rest of the loop and start over
+    }
+    Serial.println("Data is: ");   // For the printout of the data 
+    for ( i = 0; i < 32; i++) {    // Now it's time to read the PROM data itself, each page is 32 bytes so we need 32 read commands
+      data[i] = ds.read();         // we store each read byte to a different position in the data array 
+      Serial.print(data[i]);       // printout in ASCII
+      Serial.print(" ");           // blank space 
+    }
+    Serial.println();
+    delay(5000);                    // Delay so we don't saturate the serial output
+  }
+  else {                           // Nothing is connected in the bus 
+    Serial.println("Nothing connected");
+    delay(3000);
+  }
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/hardware/digistump/sam/libraries/OneWire/examples/Digispark_Example/Digispark_Example.ino b/hardware/digistump/sam/libraries/OneWire/examples/Digispark_Example/Digispark_Example.ino
new file mode 100644
index 0000000..8963e85
--- /dev/null
+++ b/hardware/digistump/sam/libraries/OneWire/examples/Digispark_Example/Digispark_Example.ino
@@ -0,0 +1,76 @@
+
+#include 
+#include 
+#define DS18S20_ID 0x10
+#define DS18B20_ID 0x28
+int temp;
+
+
+OneWire ds(5);
+
+byte data[12];
+byte addr[8]; 
+
+boolean readTemperature(){
+
+
+
+  //find a device
+   
+   
+ if (!ds.search(addr)) {
+ ds.reset_search();
+ return false;
+ }
+ if (OneWire::crc8( addr, 7) != addr[7]) {
+ return false;
+ }
+ if (addr[0] != DS18S20_ID && addr[0] != DS18B20_ID) {
+ return false;
+ }
+ 
+   ds.reset();
+ ds.select(addr);
+  // Start conversion
+ ds.write(0x44, 1);
+ // Wait some time...
+  }
+  
+boolean getTemperature(){
+     byte i;  
+       byte present = 0;
+ present = ds.reset();
+ ds.select(addr);
+ // Issue Read scratchpad command
+ ds.write(0xBE);
+ // Receive 9 bytes
+ for ( i = 0; i < 9; i++) {
+ data[i] = ds.read();
+ }
+ // Calculate temperature value
+ temp = ((( (data[1] << 8) + data[0] )*0.0625)*1.8)+32;
+ return true;
+ 
+}
+
+void setup(){
+  DigiUSB.begin();
+  DigiUSB.print("Start");
+}
+
+
+void loop(){
+
+
+  readTemperature();
+  DigiUSB.delay(1000);
+  getTemperature();
+  DigiUSB.println(temp);
+
+  DigiUSB.delay(1000);
+
+        
+        
+}
+
+
diff --git a/hardware/digistump/sam/libraries/OneWire/keywords.txt b/hardware/digistump/sam/libraries/OneWire/keywords.txt
new file mode 100644
index 0000000..bee5d90
--- /dev/null
+++ b/hardware/digistump/sam/libraries/OneWire/keywords.txt
@@ -0,0 +1,38 @@
+#######################################
+# Syntax Coloring Map For OneWire
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+OneWire	KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+reset	KEYWORD2
+write_bit	KEYWORD2
+read_bit	KEYWORD2
+write	KEYWORD2
+write_bytes	KEYWORD2
+read	KEYWORD2
+read_bytes	KEYWORD2
+select	KEYWORD2
+skip	KEYWORD2
+depower	KEYWORD2
+reset_search	KEYWORD2
+search	KEYWORD2
+crc8	KEYWORD2
+crc16	KEYWORD2
+check_crc16	KEYWORD2
+
+#######################################
+# Instances (KEYWORD2)
+#######################################
+
+
+#######################################
+# Constants (LITERAL1)
+#######################################
diff --git a/hardware/digistump/sam/libraries/RF24/.gitignore b/hardware/digistump/sam/libraries/RF24/.gitignore
new file mode 100644
index 0000000..ac32040
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/.gitignore
@@ -0,0 +1,14 @@
+*.bak
+*.o
+.*.swp
+*.orig
+.swp
+docs/
+output/
+ojam/
+out/
+16000000/
+8000000/
+out_native/
+version.h
+Session.vim
diff --git a/hardware/digistump/sam/libraries/RF24/Doxyfile b/hardware/digistump/sam/libraries/RF24/Doxyfile
new file mode 100644
index 0000000..4604afc
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/Doxyfile
@@ -0,0 +1,1551 @@
+# Doxyfile 1.6.3
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project
+#
+# All text after a hash (#) is considered a comment and will be ignored
+# The format is:
+#       TAG = value [value, ...]
+# For lists items can also be appended using:
+#       TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (" ")
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the config file
+# that follow. The default is UTF-8 which is also the encoding used for all
+# text before the first occurrence of this tag. Doxygen uses libiconv (or the
+# iconv built into libc) for the transcoding. See
+# http://www.gnu.org/software/libiconv for the list of possible encodings.
+
+DOXYFILE_ENCODING      = UTF-8
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded
+# by quotes) that should identify the project.
+
+PROJECT_NAME           = RF24 
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number.
+# This could be handy for archiving the generated documentation or
+# if some version control system is used.
+
+PROJECT_NUMBER         = v1
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
+# base path where the generated documentation will be put.
+# If a relative path is entered, it will be relative to the location
+# where doxygen was started. If left blank the current directory will be used.
+
+OUTPUT_DIRECTORY       = docs
+
+# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create
+# 4096 sub-directories (in 2 levels) under the output directory of each output
+# format and will distribute the generated files over these directories.
+# Enabling this option can be useful when feeding doxygen a huge amount of
+# source files, where putting all generated files in the same directory would
+# otherwise cause performance problems for the file system.
+
+CREATE_SUBDIRS         = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# The default language is English, other supported languages are:
+# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional,
+# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,
+# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English
+# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,
+# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak,
+# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
+
+OUTPUT_LANGUAGE        = English
+
+# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will
+# include brief member descriptions after the members that are listed in
+# the file and class documentation (similar to JavaDoc).
+# Set to NO to disable this.
+
+BRIEF_MEMBER_DESC      = YES
+
+# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend
+# the brief description of a member or function before the detailed description.
+# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+
+REPEAT_BRIEF           = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator
+# that is used to form the text in various listings. Each string
+# in this list, if found as the leading text of the brief description, will be
+# stripped from the text and the result after processing the whole list, is
+# used as the annotated text. Otherwise, the brief description is used as-is.
+# If left blank, the following values are used ("$name" is automatically
+# replaced with the name of the entity): "The $name class" "The $name widget"
+# "The $name file" "is" "provides" "specifies" "contains"
+# "represents" "a" "an" "the"
+
+ABBREVIATE_BRIEF       =
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# Doxygen will generate a detailed section even if there is only a brief
+# description.
+
+ALWAYS_DETAILED_SEC    = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# inherited members of a class in the documentation of that class as if those
+# members were ordinary class members. Constructors, destructors and assignment
+# operators of the base classes will not be shown.
+
+INLINE_INHERITED_MEMB  = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full
+# path before files name in the file list and in the header files. If set
+# to NO the shortest path that makes the file name unique will be used.
+
+FULL_PATH_NAMES        = YES
+
+# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag
+# can be used to strip a user-defined part of the path. Stripping is
+# only done if one of the specified strings matches the left-hand part of
+# the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the
+# path to strip.
+
+STRIP_FROM_PATH        =
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of
+# the path mentioned in the documentation of a class, which tells
+# the reader which header file to include in order to use a class.
+# If left blank only the name of the header file containing the class
+# definition is used. Otherwise one should specify the include paths that
+# are normally passed to the compiler using the -I flag.
+
+STRIP_FROM_INC_PATH    =
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter
+# (but less readable) file names. This can be useful is your file systems
+# doesn't support long names like on DOS, Mac, or CD-ROM.
+
+SHORT_NAMES            = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen
+# will interpret the first line (until the first dot) of a JavaDoc-style
+# comment as the brief description. If set to NO, the JavaDoc
+# comments will behave just like regular Qt-style comments
+# (thus requiring an explicit @brief command for a brief description.)
+
+JAVADOC_AUTOBRIEF      = YES
+
+# If the QT_AUTOBRIEF tag is set to YES then Doxygen will
+# interpret the first line (until the first dot) of a Qt-style
+# comment as the brief description. If set to NO, the comments
+# will behave just like regular Qt-style comments (thus requiring
+# an explicit \brief command for a brief description.)
+
+QT_AUTOBRIEF           = YES
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen
+# treat a multi-line C++ special comment block (i.e. a block of //! or ///
+# comments) as a brief description. This used to be the default behaviour.
+# The new default is to treat a multi-line C++ comment block as a detailed
+# description. Set this tag to YES if you prefer the old behaviour instead.
+
+MULTILINE_CPP_IS_BRIEF = NO
+
+# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented
+# member inherits the documentation from any documented member that it
+# re-implements.
+
+INHERIT_DOCS           = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce
+# a new page for each member. If set to NO, the documentation of a member will
+# be part of the file/class/namespace that contains it.
+
+SEPARATE_MEMBER_PAGES  = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab.
+# Doxygen uses this value to replace tabs by spaces in code fragments.
+
+TAB_SIZE               = 8
+
+# This tag can be used to specify a number of aliases that acts
+# as commands in the documentation. An alias has the form "name=value".
+# For example adding "sideeffect=\par Side Effects:\n" will allow you to
+# put the command \sideeffect (or @sideeffect) in the documentation, which
+# will result in a user-defined paragraph with heading "Side Effects:".
+# You can put \n's in the value part of an alias to insert newlines.
+
+ALIASES                =
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C
+# sources only. Doxygen will then generate output that is more tailored for C.
+# For instance, some of the names that are used will be different. The list
+# of all members will be omitted, etc.
+
+OPTIMIZE_OUTPUT_FOR_C  = NO
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java
+# sources only. Doxygen will then generate output that is more tailored for
+# Java. For instance, namespaces will be presented as packages, qualified
+# scopes will look different, etc.
+
+OPTIMIZE_OUTPUT_JAVA   = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources only. Doxygen will then generate output that is more tailored for
+# Fortran.
+
+OPTIMIZE_FOR_FORTRAN   = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for
+# VHDL.
+
+OPTIMIZE_OUTPUT_VHDL   = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it parses.
+# With this tag you can assign which parser to use for a given extension.
+# Doxygen has a built-in mapping, but you can override or extend it using this tag.
+# The format is ext=language, where ext is a file extension, and language is one of
+# the parsers supported by doxygen: IDL, Java, Javascript, C#, C, C++, D, PHP,
+# Objective-C, Python, Fortran, VHDL, C, C++. For instance to make doxygen treat
+# .inc files as Fortran files (default is PHP), and .f files as C (default is Fortran),
+# use: inc=Fortran f=C. Note that for custom extensions you also need to set FILE_PATTERNS otherwise the files are not read by doxygen.
+
+EXTENSION_MAPPING      =
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should
+# set this tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string); v.s.
+# func(std::string) {}). This also make the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+
+BUILTIN_STL_SUPPORT    = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+
+CPP_CLI_SUPPORT        = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only.
+# Doxygen will parse them like normal C++ but will assume all classes use public
+# instead of private inheritance when no explicit protection keyword is present.
+
+SIP_SUPPORT            = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate getter
+# and setter methods for a property. Setting this option to YES (the default)
+# will make doxygen to replace the get and set methods by a property in the
+# documentation. This will only work if the methods are indeed getting or
+# setting a simple type. If this is not the case, or you want to show the
+# methods anyway, you should set this option to NO.
+
+IDL_PROPERTY_SUPPORT   = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES, then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+
+DISTRIBUTE_GROUP_DOC   = NO
+
+# Set the SUBGROUPING tag to YES (the default) to allow class member groups of
+# the same type (for instance a group of public functions) to be put as a
+# subgroup of that type (e.g. under the Public Functions section). Set it to
+# NO to prevent subgrouping. Alternatively, this can be done per class using
+# the \nosubgrouping command.
+
+SUBGROUPING            = YES
+
+# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum
+# is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically
+# be useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+
+TYPEDEF_HIDES_STRUCT   = NO
+
+# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to
+# determine which symbols to keep in memory and which to flush to disk.
+# When the cache is full, less often used symbols will be written to disk.
+# For small to medium size projects (<1000 input files) the default value is
+# probably good enough. For larger projects a too small cache size can cause
+# doxygen to be busy swapping symbols to and from disk most of the time
+# causing a significant performance penality.
+# If the system has enough physical memory increasing the cache will improve the
+# performance by keeping more symbols in memory. Note that the value works on
+# a logarithmic scale so increasing the size by one will rougly double the
+# memory usage. The cache size is given by this formula:
+# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,
+# corresponding to a cache size of 2^16 = 65536 symbols
+
+SYMBOL_CACHE_SIZE      = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in
+# documentation are documented, even if no documentation was available.
+# Private class members and static file members will be hidden unless
+# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
+
+EXTRACT_ALL            = NO
+
+# If the EXTRACT_PRIVATE tag is set to YES all private members of a class
+# will be included in the documentation.
+
+EXTRACT_PRIVATE        = NO
+
+# If the EXTRACT_STATIC tag is set to YES all static members of a file
+# will be included in the documentation.
+
+EXTRACT_STATIC         = NO
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)
+# defined locally in source files will be included in the documentation.
+# If set to NO only classes defined in header files are included.
+
+EXTRACT_LOCAL_CLASSES  = YES
+
+# This flag is only useful for Objective-C code. When set to YES local
+# methods, which are defined in the implementation section but not in
+# the interface are included in the documentation.
+# If set to NO (the default) only methods in the interface are included.
+
+EXTRACT_LOCAL_METHODS  = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base
+# name of the file that contains the anonymous namespace. By default
+# anonymous namespace are hidden.
+
+EXTRACT_ANON_NSPACES   = NO
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
+# undocumented members of documented classes, files or namespaces.
+# If set to NO (the default) these members will be included in the
+# various overviews, but no documentation section is generated.
+# This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_MEMBERS     = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy.
+# If set to NO (the default) these classes will be included in the various
+# overviews. This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_CLASSES     = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all
+# friend (class|struct|union) declarations.
+# If set to NO (the default) these declarations will be included in the
+# documentation.
+
+HIDE_FRIEND_COMPOUNDS  = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any
+# documentation blocks found inside the body of a function.
+# If set to NO (the default) these blocks will be appended to the
+# function's detailed documentation block.
+
+HIDE_IN_BODY_DOCS      = NO
+
+# The INTERNAL_DOCS tag determines if documentation
+# that is typed after a \internal command is included. If the tag is set
+# to NO (the default) then the documentation will be excluded.
+# Set it to YES to include the internal documentation.
+
+INTERNAL_DOCS          = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate
+# file names in lower-case letters. If set to YES upper-case letters are also
+# allowed. This is useful if you have classes or files whose names only differ
+# in case and if your file system supports case sensitive file names. Windows
+# and Mac users are advised to set this option to NO.
+
+CASE_SENSE_NAMES       = YES
+
+# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen
+# will show members with their full class and namespace scopes in the
+# documentation. If set to YES the scope will be hidden.
+
+HIDE_SCOPE_NAMES       = NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen
+# will put a list of the files that are included by a file in the documentation
+# of that file.
+
+SHOW_INCLUDE_FILES     = YES
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen
+# will list include files with double quotes in the documentation
+# rather than with sharp brackets.
+
+FORCE_LOCAL_INCLUDES   = NO
+
+# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]
+# is inserted in the documentation for inline members.
+
+INLINE_INFO            = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen
+# will sort the (detailed) documentation of file and class members
+# alphabetically by member name. If set to NO the members will appear in
+# declaration order.
+
+SORT_MEMBER_DOCS       = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the
+# brief documentation of file, namespace and class members alphabetically
+# by member name. If set to NO (the default) the members will appear in
+# declaration order.
+
+SORT_BRIEF_DOCS        = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the (brief and detailed) documentation of class members so that constructors and destructors are listed first. If set to NO (the default) the constructors will appear in the respective orders defined by SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the
+# hierarchy of group names into alphabetical order. If set to NO (the default)
+# the group names will appear in their defined order.
+
+SORT_GROUP_NAMES       = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be
+# sorted by fully-qualified names, including namespaces. If set to
+# NO (the default), the class list will be sorted only by class name,
+# not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the
+# alphabetical list.
+
+SORT_BY_SCOPE_NAME     = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or
+# disable (NO) the todo list. This list is created by putting \todo
+# commands in the documentation.
+
+GENERATE_TODOLIST      = YES
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or
+# disable (NO) the test list. This list is created by putting \test
+# commands in the documentation.
+
+GENERATE_TESTLIST      = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or
+# disable (NO) the bug list. This list is created by putting \bug
+# commands in the documentation.
+
+GENERATE_BUGLIST       = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or
+# disable (NO) the deprecated list. This list is created by putting
+# \deprecated commands in the documentation.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional
+# documentation sections, marked by \if sectionname ... \endif.
+
+ENABLED_SECTIONS       =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines
+# the initial value of a variable or define consists of for it to appear in
+# the documentation. If the initializer consists of more lines than specified
+# here it will be hidden. Use a value of 0 to hide initializers completely.
+# The appearance of the initializer of individual variables and defines in the
+# documentation can be controlled using \showinitializer or \hideinitializer
+# command in the documentation regardless of this setting.
+
+MAX_INITIALIZER_LINES  = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated
+# at the bottom of the documentation of classes and structs. If set to YES the
+# list will mention the files that were used to generate the documentation.
+
+SHOW_USED_FILES        = YES
+
+# If the sources in your project are distributed over multiple directories
+# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy
+# in the documentation. The default is NO.
+
+SHOW_DIRECTORIES       = NO
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page.
+# This will remove the Files entry from the Quick Index and from the
+# Folder Tree View (if specified). The default is YES.
+
+SHOW_FILES             = YES 
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the
+# Namespaces page.
+# This will remove the Namespaces entry from the Quick Index
+# and from the Folder Tree View (if specified). The default is YES.
+
+SHOW_NAMESPACES        = YES
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command  , where  is the value of
+# the FILE_VERSION_FILTER tag, and  is the name of an input file
+# provided by doxygen. Whatever the program writes to standard output
+# is used as the file version. See the manual for examples.
+
+FILE_VERSION_FILTER    =
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed by
+# doxygen. The layout file controls the global structure of the generated output files
+# in an output format independent way. The create the layout file that represents
+# doxygen's defaults, run doxygen with the -l option. You can optionally specify a
+# file name after the option, if omitted DoxygenLayout.xml will be used as the name
+# of the layout file.
+
+LAYOUT_FILE            =
+
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated
+# by doxygen. Possible values are YES and NO. If left blank NO is used.
+
+QUIET                  = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated by doxygen. Possible values are YES and NO. If left blank
+# NO is used.
+
+WARNINGS               = YES
+
+# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings
+# for undocumented members. If EXTRACT_ALL is set to YES then this flag will
+# automatically be disabled.
+
+WARN_IF_UNDOCUMENTED   = YES
+
+# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some
+# parameters in a documented function, or documenting parameters that
+# don't exist or using markup commands wrongly.
+
+WARN_IF_DOC_ERROR      = YES
+
+# This WARN_NO_PARAMDOC option can be abled to get warnings for
+# functions that are documented, but have no documentation for their parameters
+# or return value. If set to NO (the default) doxygen will only warn about
+# wrong or incomplete parameter documentation, but not about the absence of
+# documentation.
+
+WARN_NO_PARAMDOC       = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that
+# doxygen can produce. The string should contain the $file, $line, and $text
+# tags, which will be replaced by the file and line number from which the
+# warning originated and the warning text. Optionally the format may contain
+# $version, which will be replaced by the version of the file (if it could
+# be obtained via FILE_VERSION_FILTER)
+
+WARN_FORMAT            = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning
+# and error messages should be written. If left blank the output is written
+# to stderr.
+
+WARN_LOGFILE           =
+
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag can be used to specify the files and/or directories that contain
+# documented source files. You may enter file names like "myfile.cpp" or
+# directories like "/usr/src/myproject". Separate the files or directories
+# with spaces.
+
+INPUT                  = . 
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is
+# also the default input encoding. Doxygen uses libiconv (or the iconv built
+# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for
+# the list of possible encodings.
+
+INPUT_ENCODING         = UTF-8
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank the following patterns are tested:
+# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx
+# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90
+
+FILE_PATTERNS          = *.h FAQ
+
+# The RECURSIVE tag can be used to turn specify whether or not subdirectories
+# should be searched for input files as well. Possible values are YES and NO.
+# If left blank NO is used.
+
+RECURSIVE              = NO
+
+# The EXCLUDE tag can be used to specify files and/or directories that should
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+
+EXCLUDE                =
+
+# The EXCLUDE_SYMLINKS tag can be used select whether or not files or
+# directories that are symbolic links (a Unix filesystem feature) are excluded
+# from the input.
+
+EXCLUDE_SYMLINKS       = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories. Note that the wildcards are matched
+# against the file with absolute path, so to exclude all test directories
+# for example use the pattern */test/*
+
+EXCLUDE_PATTERNS       =
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# AClass::ANamespace, ANamespace::*Test
+
+EXCLUDE_SYMBOLS        =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or
+# directories that contain example code fragments that are included (see
+# the \include command).
+
+EXAMPLE_PATH           = examples
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank all files are included.
+
+EXAMPLE_PATTERNS       =
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude
+# commands irrespective of the value of the RECURSIVE tag.
+# Possible values are YES and NO. If left blank NO is used.
+
+EXAMPLE_RECURSIVE      = YES
+
+# The IMAGE_PATH tag can be used to specify one or more files or
+# directories that contain image that are included in the documentation (see
+# the \image command).
+
+IMAGE_PATH             =
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command  , where 
+# is the value of the INPUT_FILTER tag, and  is the name of an
+# input file. Doxygen will then use the output that the filter program writes
+# to standard output.
+# If FILTER_PATTERNS is specified, this tag will be
+# ignored.
+
+INPUT_FILTER           =
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis.
+# Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match.
+# The filters are a list of the form:
+# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
+# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER
+# is applied to all files.
+
+FILTER_PATTERNS        =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will be used to filter the input files when producing source
+# files to browse (i.e. when SOURCE_BROWSER is set to YES).
+
+FILTER_SOURCE_FILES    = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will
+# be generated. Documented entities will be cross-referenced with these sources.
+# Note: To get rid of all source code in the generated output, make sure also
+# VERBATIM_HEADERS is set to NO.
+
+SOURCE_BROWSER         = NO
+
+# Setting the INLINE_SOURCES tag to YES will include the body
+# of functions and classes directly in the documentation.
+
+INLINE_SOURCES         = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
+# doxygen to hide any special comment blocks from generated source code
+# fragments. Normal C and C++ comments will always remain visible.
+
+STRIP_CODE_COMMENTS    = YES
+
+# If the REFERENCED_BY_RELATION tag is set to YES
+# then for each documented function all documented
+# functions referencing it will be listed.
+
+REFERENCED_BY_RELATION = NO
+
+# If the REFERENCES_RELATION tag is set to YES
+# then for each documented function all documented entities
+# called/used by that function will be listed.
+
+REFERENCES_RELATION    = NO
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)
+# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from
+# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will
+# link to the source code.
+# Otherwise they will link to the documentation.
+
+REFERENCES_LINK_SOURCE = NO
+
+# If the USE_HTAGS tag is set to YES then the references to source code
+# will point to the HTML generated by the htags(1) tool instead of doxygen
+# built-in source browser. The htags tool is part of GNU's global source
+# tagging system (see http://www.gnu.org/software/global/global.html). You
+# will need version 4.8.6 or higher.
+
+USE_HTAGS              = NO
+
+# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen
+# will generate a verbatim copy of the header file for each class for
+# which an include is specified. Set to NO to disable this.
+
+VERBATIM_HEADERS       = YES 
+
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index
+# of all compounds will be generated. Enable this if the project
+# contains a lot of classes, structs, unions or interfaces.
+
+ALPHABETICAL_INDEX     = NO
+
+# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then
+# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns
+# in which this list will be split (can be a number in the range [1..20])
+
+COLS_IN_ALPHA_INDEX    = 5
+
+# In case all classes in a project start with a common prefix, all
+# classes will be put under the same header in the alphabetical index.
+# The IGNORE_PREFIX tag can be used to specify one or more prefixes that
+# should be ignored while generating the index headers.
+
+IGNORE_PREFIX          =
+
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES (the default) Doxygen will
+# generate HTML output.
+
+GENERATE_HTML          = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `html' will be used as the default path.
+
+HTML_OUTPUT            = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for
+# each generated HTML page (for example: .htm,.php,.asp). If it is left blank
+# doxygen will generate files with .html extension.
+
+HTML_FILE_EXTENSION    = .html
+
+# The HTML_HEADER tag can be used to specify a personal HTML header for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard header.
+
+HTML_HEADER            =
+
+# The HTML_FOOTER tag can be used to specify a personal HTML footer for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard footer.
+
+HTML_FOOTER            =
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
+# style sheet that is used by each HTML page. It can be used to
+# fine-tune the look of the HTML output. If the tag is left blank doxygen
+# will generate a default style sheet. Note that doxygen will try to copy
+# the style sheet file to the HTML output directory, so don't put your own
+# stylesheet in the HTML output directory as well, or it will be erased!
+
+HTML_STYLESHEET        = doxygen-custom.css
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting
+# this to NO can help when comparing the output of multiple runs.
+
+HTML_TIMESTAMP         = YES
+
+# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes,
+# files or namespaces will be aligned in HTML using tables. If set to
+# NO a bullet list will be used.
+
+HTML_ALIGN_MEMBERS     = YES
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded. For this to work a browser that supports
+# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox
+# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari).
+
+HTML_DYNAMIC_SECTIONS  = NO
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files
+# will be generated that can be used as input for Apple's Xcode 3
+# integrated development environment, introduced with OSX 10.5 (Leopard).
+# To create a documentation set, doxygen will generate a Makefile in the
+# HTML output directory. Running make will produce the docset in that
+# directory and running "make install" will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find
+# it at startup.
+# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html for more information.
+
+GENERATE_DOCSET        = NO
+
+# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the
+# feed. A documentation feed provides an umbrella under which multiple
+# documentation sets from a single provider (such as a company or product suite)
+# can be grouped.
+
+DOCSET_FEEDNAME        = "Doxygen generated docs"
+
+# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that
+# should uniquely identify the documentation set bundle. This should be a
+# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen
+# will append .docset to the name.
+
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+
+# If the GENERATE_HTMLHELP tag is set to YES, additional index files
+# will be generated that can be used as input for tools like the
+# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)
+# of the generated HTML documentation.
+
+GENERATE_HTMLHELP      = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can
+# be used to specify the file name of the resulting .chm file. You
+# can add a path in front of the file if the result should not be
+# written to the html output directory.
+
+CHM_FILE               =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can
+# be used to specify the location (absolute path including file name) of
+# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run
+# the HTML help compiler on the generated index.hhp.
+
+HHC_LOCATION           =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
+# controls if a separate .chi index file is generated (YES) or that
+# it should be included in the master .chm file (NO).
+
+GENERATE_CHI           = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING
+# is used to encode HtmlHelp index (hhk), content (hhc) and project file
+# content.
+
+CHM_INDEX_ENCODING     =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag
+# controls whether a binary table of contents is generated (YES) or a
+# normal table of contents (NO) in the .chm file.
+
+BINARY_TOC             = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members
+# to the contents of the HTML help documentation and to the tree view.
+
+TOC_EXPAND             = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and QHP_VIRTUAL_FOLDER
+# are set, an additional index file will be generated that can be used as input for
+# Qt's qhelpgenerator to generate a Qt Compressed Help (.qch) of the generated
+# HTML documentation.
+
+GENERATE_QHP           = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can
+# be used to specify the file name of the resulting .qch file.
+# The path specified is relative to the HTML output folder.
+
+QCH_FILE               =
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#namespace
+
+QHP_NAMESPACE          = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#virtual-folders
+
+QHP_VIRTUAL_FOLDER     = doc
+
+# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to add.
+# For more information please see
+# http://doc.trolltech.com/qthelpproject.html#custom-filters
+
+QHP_CUST_FILTER_NAME   =
+
+# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the custom filter to add.For more information please see
+# Qt Help Project / Custom Filters.
+
+QHP_CUST_FILTER_ATTRS  =
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this project's
+# filter section matches.
+# Qt Help Project / Filter Attributes.
+
+QHP_SECT_FILTER_ATTRS  =
+
+# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can
+# be used to specify the location of Qt's qhelpgenerator.
+# If non-empty doxygen will try to run qhelpgenerator on the generated
+# .qhp file.
+
+QHG_LOCATION           =
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files
+#  will be generated, which together with the HTML files, form an Eclipse help
+#  plugin. To install this plugin and make it available under the help contents
+# menu in Eclipse, the contents of the directory containing the HTML and XML
+# files needs to be copied into the plugins directory of eclipse. The name of
+# the directory within the plugins directory should be the same as
+# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before the help appears.
+
+GENERATE_ECLIPSEHELP   = NO
+
+# A unique identifier for the eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have
+# this name.
+
+ECLIPSE_DOC_ID         = org.doxygen.Project
+
+# The DISABLE_INDEX tag can be used to turn on/off the condensed index at
+# top of each HTML page. The value NO (the default) enables the index and
+# the value YES disables it.
+
+DISABLE_INDEX          = NO
+
+# This tag can be used to set the number of enum values (range [1..20])
+# that doxygen will group on one line in the generated HTML documentation.
+
+ENUM_VALUES_PER_LINE   = 4
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information.
+# If the tag value is set to YES, a side panel will be generated
+# containing a tree-like index structure (just like the one that
+# is generated for HTML Help). For this to work a browser that supports
+# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
+# Windows users are probably better off using the HTML help feature.
+
+GENERATE_TREEVIEW      = NO
+
+# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,
+# and Class Hierarchy pages using a tree view instead of an ordered list.
+
+USE_INLINE_TREES       = NO
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be
+# used to set the initial width (in pixels) of the frame in which the tree
+# is shown.
+
+TREEVIEW_WIDTH         = 250
+
+# Use this tag to change the font size of Latex formulas included
+# as images in the HTML documentation. The default is 10. Note that
+# when you change the font size after a successful doxygen run you need
+# to manually remove any form_*.png images from the HTML output directory
+# to force them to be regenerated.
+
+FORMULA_FONTSIZE       = 10
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box for the HTML output. The underlying search engine uses javascript
+# and DHTML and should work on any modern browser. Note that when using HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) there is already a search function so this one should
+# typically be disabled. For large projects the javascript based search engine
+# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.
+
+SEARCHENGINE           = YES
+
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be implemented using a PHP enabled web server instead of at the web client using Javascript. Doxygen will generate the search PHP script and index
+# file to put on the web server. The advantage of the server based approach is that it scales better to large projects and allows full text search. The disadvances is that it is more difficult to setup
+# and does not have live searching capabilities.
+
+SERVER_BASED_SEARCH    = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will
+# generate Latex output.
+
+GENERATE_LATEX         = NO
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `latex' will be used as the default path.
+
+LATEX_OUTPUT           = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
+# invoked. If left blank `latex' will be used as the default command name.
+# Note that when enabling USE_PDFLATEX this option is only used for
+# generating bitmaps for formulas in the HTML output, but not in the
+# Makefile that is written to the output directory.
+
+LATEX_CMD_NAME         = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to
+# generate index for LaTeX. If left blank `makeindex' will be used as the
+# default command name.
+
+MAKEINDEX_CMD_NAME     = makeindex
+
+# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact
+# LaTeX documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_LATEX          = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used
+# by the printer. Possible values are: a4, a4wide, letter, legal and
+# executive. If left blank a4wide will be used.
+
+PAPER_TYPE             = a4wide
+
+# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
+# packages that should be included in the LaTeX output.
+
+EXTRA_PACKAGES         =
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for
+# the generated latex document. The header should contain everything until
+# the first chapter. If it is left blank doxygen will generate a
+# standard header. Notice: only use this tag if you know what you are doing!
+
+LATEX_HEADER           =
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
+# is prepared for conversion to pdf (using ps2pdf). The pdf file will
+# contain links (just like the HTML output) instead of page references
+# This makes the output suitable for online browsing using a pdf viewer.
+
+PDF_HYPERLINKS         = YES
+
+# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of
+# plain latex in the generated Makefile. Set this option to YES to get a
+# higher quality PDF documentation.
+
+USE_PDFLATEX           = YES
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.
+# command to the generated LaTeX files. This will instruct LaTeX to keep
+# running if errors occur, instead of asking the user for help.
+# This option is also used when generating formulas in HTML.
+
+LATEX_BATCHMODE        = NO
+
+# If LATEX_HIDE_INDICES is set to YES then doxygen will not
+# include the index chapters (such as File Index, Compound Index, etc.)
+# in the output.
+
+LATEX_HIDE_INDICES     = NO
+
+# If LATEX_SOURCE_CODE is set to YES then doxygen will include source code with syntax highlighting in the LaTeX output. Note that which sources are shown also depends on other settings such as SOURCE_BROWSER.
+
+LATEX_SOURCE_CODE      = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output
+# The RTF output is optimized for Word 97 and may not look very pretty with
+# other RTF readers or editors.
+
+GENERATE_RTF           = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `rtf' will be used as the default path.
+
+RTF_OUTPUT             = rtf
+
+# If the COMPACT_RTF tag is set to YES Doxygen generates more compact
+# RTF documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_RTF            = NO
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated
+# will contain hyperlink fields. The RTF file will
+# contain links (just like the HTML output) instead of page references.
+# This makes the output suitable for online browsing using WORD or other
+# programs which support those fields.
+# Note: wordpad (write) and others do not support links.
+
+RTF_HYPERLINKS         = NO
+
+# Load stylesheet definitions from file. Syntax is similar to doxygen's
+# config file, i.e. a series of assignments. You only have to provide
+# replacements, missing definitions are set to their default value.
+
+RTF_STYLESHEET_FILE    =
+
+# Set optional variables used in the generation of an rtf document.
+# Syntax is similar to doxygen's config file.
+
+RTF_EXTENSIONS_FILE    =
+
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES (the default) Doxygen will
+# generate man pages
+
+GENERATE_MAN           = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `man' will be used as the default path.
+
+MAN_OUTPUT             = man
+
+# The MAN_EXTENSION tag determines the extension that is added to
+# the generated man pages (default is the subroutine's section .3)
+
+MAN_EXTENSION          = .3
+
+# If the MAN_LINKS tag is set to YES and Doxygen generates man output,
+# then it will generate one additional man file for each entity
+# documented in the real man page(s). These additional files
+# only source the real man page, but without them the man command
+# would be unable to find the correct page. The default is NO.
+
+MAN_LINKS              = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES Doxygen will
+# generate an XML file that captures the structure of
+# the code including all documentation.
+
+GENERATE_XML           = YES
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `xml' will be used as the default path.
+
+XML_OUTPUT             = xml
+
+# The XML_SCHEMA tag can be used to specify an XML schema,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_SCHEMA             =
+
+# The XML_DTD tag can be used to specify an XML DTD,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_DTD                =
+
+# If the XML_PROGRAMLISTING tag is set to YES Doxygen will
+# dump the program listings (including syntax highlighting
+# and cross-referencing information) to the XML output. Note that
+# enabling this will significantly increase the size of the XML output.
+
+XML_PROGRAMLISTING     = NO
+
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will
+# generate an AutoGen Definitions (see autogen.sf.net) file
+# that captures the structure of the code including all
+# documentation. Note that this feature is still experimental
+# and incomplete at the moment.
+
+GENERATE_AUTOGEN_DEF   = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_PERLMOD tag is set to YES Doxygen will
+# generate a Perl module file that captures the structure of
+# the code including all documentation. Note that this
+# feature is still experimental and incomplete at the
+# moment.
+
+GENERATE_PERLMOD       = NO
+
+# If the PERLMOD_LATEX tag is set to YES Doxygen will generate
+# the necessary Makefile rules, Perl scripts and LaTeX code to be able
+# to generate PDF and DVI output from the Perl module output.
+
+PERLMOD_LATEX          = NO
+
+# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be
+# nicely formatted so it can be parsed by a human reader.
+# This is useful
+# if you want to understand what is going on.
+# On the other hand, if this
+# tag is set to NO the size of the Perl module output will be much smaller
+# and Perl will parse it just the same.
+
+PERLMOD_PRETTY         = YES
+
+# The names of the make variables in the generated doxyrules.make file
+# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.
+# This is useful so different doxyrules.make files included by the same
+# Makefile don't overwrite each other's variables.
+
+PERLMOD_MAKEVAR_PREFIX =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+
+# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will
+# evaluate all C-preprocessor directives found in the sources and include
+# files.
+
+ENABLE_PREPROCESSING   = YES
+
+# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro
+# names in the source code. If set to NO (the default) only conditional
+# compilation will be performed. Macro expansion can be done in a controlled
+# way by setting EXPAND_ONLY_PREDEF to YES.
+
+MACRO_EXPANSION        = NO
+
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES
+# then the macro expansion is limited to the macros specified with the
+# PREDEFINED and EXPAND_AS_DEFINED tags.
+
+EXPAND_ONLY_PREDEF     = NO
+
+# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
+# in the INCLUDE_PATH (see below) will be search if a #include is found.
+
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diff --git a/hardware/digistump/sam/libraries/RF24/FAQ b/hardware/digistump/sam/libraries/RF24/FAQ
new file mode 100644
index 0000000..eccd03a
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/FAQ
@@ -0,0 +1,53 @@
+/**
+ * @page FAQ Frequently Asked Questions
+ *
+ * @ref starting
+ *
+ * @ref hardware
+ *
+ * @ref range
+ *
+ * @ref issues
+ *
+ * @ref ram
+ *
+ * @ref tests
+ *
+ * @section starting Where do I start?
+ *
+ * See my blog post: 
+ * Getting Started with nRF24L01+ on Arduino
+ *
+ * @section hardware Where can I buy some hardware?
+ *
+ * @li iTeadStudio sells the basic 2.4G Wireless nRF24L01+ Module for $4.  Such a deal!
+ * @li MDfly.com sells the same unit, 2.4Ghz Wireless nRF24L01+ Transceiver Module for $6.95, but it ships from the US so it gets there a lot faster.  Great place to get a few units and get started quickly.
+ * @li MDfly.com also has the nRF24L01 2.4GHz Transceiver Module w/ Power Amplifier for $13.95, which increases range dramatically and uses a chip antenna
+ * @li MDfly.com also has the 2.4GHz Transceiver Module w/ Power Amplifier with an external antenna for $19.95
+ *
+ * @section range What is the range of these units?
+ *
+ * Here are some results from measurements I have taken, using the basic $4 iTeadStudio units.  
+ * I recommend that everyone take their own measurements in their particular circumstances.
+ *
+ * @li non-plus unit, 2MBps (worst case), 41+ ft line of sight indoors, immediate dropoff with any deviation from LOS.  (41 ft is as far as I can go in my house without turning a corner)
+ * @li Plus unit, 250kbps (best case), 46 ft around two corners indoors, 49 ft around one corner.  More importantly, at 250k, packet loss is almost negligible through almost all of that range.
+ * @li Both units at 1MBps, plus unit gets about 10% range improvement over non-plus in almost all situations.
+ * 
+ * @section issues What should I do if I find a problem?
+ *
+ * Please open an issue on github if you find any problems using it with any version of Arduino or Maple.
+ *
+ * @section ram What is the RAM footprint of this library?
+ *
+ * 16 bytes.  A single radio object consumes 16 bytes of RAM, and the library 
+ * does not use any other RAM statically.
+ * 
+ * @section tests Why are the examples in the 'tests' directory failing?
+ *
+ * The sketches in the 'tests' directory are not for general use.
+ * Please use the examples in the 'examples' directory instead.  
+ *
+ * The 'tests' directory is only for people making changes to the library
+ * to ensure that their changes do not break anything.
+ */
diff --git a/hardware/digistump/sam/libraries/RF24/README.md b/hardware/digistump/sam/libraries/RF24/README.md
new file mode 100644
index 0000000..c0e71c0
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/README.md
@@ -0,0 +1,20 @@
+# Arduino driver for nRF24L01 2.4GHz Wireless Transceiver
+
+Design Goals: This library is designed to be...
+
+* Maximally compliant with the intended operation of the chip
+* Easy for beginners to use
+* Consumed with a public interface that's similiar to other Arduino standard libraries
+* Built against the standard SPI library. 
+
+Please refer to:
+
+* [Documentation Main Page](http://maniacbug.github.com/RF24)
+* [RF24 Class Documentation](http://maniacbug.github.com/RF24/classRF24.html)
+* [Source Code](https://github.com/maniacbug/RF24)
+* [Downloads](https://github.com/maniacbug/RF24/archives/master)
+* [Chip Datasheet](http://www.nordicsemi.com/files/Product/data_sheet/nRF24L01_Product_Specification_v2_0.pdf)
+
+This chip uses the SPI bus, plus two chip control pins.  Remember that pin 10 must still remain an output, or
+the SPI hardware will go into 'slave' mode.
+
diff --git a/hardware/digistump/sam/libraries/RF24/RF24.cpp b/hardware/digistump/sam/libraries/RF24/RF24.cpp
new file mode 100644
index 0000000..9471583
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/RF24.cpp
@@ -0,0 +1,985 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#include "nRF24L01.h"
+#include "RF24_config.h"
+#include "RF24.h"
+
+/****************************************************************************/
+
+void RF24::csn(int mode)
+{
+  // Minimum ideal SPI bus speed is 2x data rate
+  // If we assume 2Mbs data rate and 16Mhz clock, a
+  // divider of 4 is the minimum we want.
+  // CLK:BUS 8Mhz:2Mhz, 16Mhz:4Mhz, or 20Mhz:5Mhz
+#ifdef ARDUINO
+  SPI.setBitOrder(MSBFIRST);
+  SPI.setDataMode(SPI_MODE0);
+  SPI.setClockDivider(SPI_CLOCK_DIV4);
+#endif
+  digitalWrite(csn_pin,mode);
+}
+
+/****************************************************************************/
+
+void RF24::ce(int level)
+{
+  digitalWrite(ce_pin,level);
+}
+
+/****************************************************************************/
+
+uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
+{
+  uint8_t status;
+
+  csn(LOW);
+  status = SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
+  while ( len-- )
+    *buf++ = SPI.transfer(0xff);
+
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::read_register(uint8_t reg)
+{
+  csn(LOW);
+  SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
+  uint8_t result = SPI.transfer(0xff);
+
+  csn(HIGH);
+  return result;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
+{
+  uint8_t status;
+
+  csn(LOW);
+  status = SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
+  while ( len-- )
+    SPI.transfer(*buf++);
+
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::write_register(uint8_t reg, uint8_t value)
+{
+  uint8_t status;
+
+  IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"),reg,value));
+
+  csn(LOW);
+  status = SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
+  SPI.transfer(value);
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::write_payload(const void* buf, uint8_t len)
+{
+  uint8_t status;
+
+  const uint8_t* current = reinterpret_cast(buf);
+
+  uint8_t data_len = min(len,payload_size);
+  uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
+  
+  //printf("[Writing %u bytes %u blanks]",data_len,blank_len);
+  
+  csn(LOW);
+  status = SPI.transfer( W_TX_PAYLOAD );
+  while ( data_len-- )
+    SPI.transfer(*current++);
+  while ( blank_len-- )
+    SPI.transfer(0);
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::read_payload(void* buf, uint8_t len)
+{
+  uint8_t status;
+  uint8_t* current = reinterpret_cast(buf);
+
+  uint8_t data_len = min(len,payload_size);
+  uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
+  
+  //printf("[Reading %u bytes %u blanks]",data_len,blank_len);
+  
+  csn(LOW);
+  status = SPI.transfer( R_RX_PAYLOAD );
+  while ( data_len-- )
+    *current++ = SPI.transfer(0xff);
+  while ( blank_len-- )
+    SPI.transfer(0xff);
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::flush_rx(void)
+{
+  uint8_t status;
+
+  csn(LOW);
+  status = SPI.transfer( FLUSH_RX );
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::flush_tx(void)
+{
+  uint8_t status;
+
+  csn(LOW);
+  status = SPI.transfer( FLUSH_TX );
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::get_status(void)
+{
+  uint8_t status;
+
+  csn(LOW);
+  status = SPI.transfer( NOP );
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+void RF24::print_status(uint8_t status)
+{
+  printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"),
+           status,
+           (status & _BV(RX_DR))?1:0,
+           (status & _BV(TX_DS))?1:0,
+           (status & _BV(MAX_RT))?1:0,
+           ((status >> RX_P_NO) & B111),
+           (status & _BV(TX_FULL))?1:0
+          );
+}
+
+/****************************************************************************/
+
+void RF24::print_observe_tx(uint8_t value)
+{
+  printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"),
+           value,
+           (value >> PLOS_CNT) & B1111,
+           (value >> ARC_CNT) & B1111
+          );
+}
+
+/****************************************************************************/
+
+void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty)
+{
+  char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
+  printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
+  while (qty--)
+    printf_P(PSTR(" 0x%02x"),read_register(reg++));
+  printf_P(PSTR("\r\n"));
+}
+
+/****************************************************************************/
+
+void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
+{
+  char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
+  printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
+
+  while (qty--)
+  {
+    uint8_t buffer[5];
+    read_register(reg++,buffer,sizeof buffer);
+
+    printf_P(PSTR(" 0x"));
+    uint8_t* bufptr = buffer + sizeof buffer;
+    while( --bufptr >= buffer )
+      printf_P(PSTR("%02x"),*bufptr);
+  }
+
+  printf_P(PSTR("\r\n"));
+}
+
+/****************************************************************************/
+
+RF24::RF24(uint8_t _cepin, uint8_t _cspin):
+  ce_pin(_cepin), csn_pin(_cspin), wide_band(true), p_variant(false), 
+  payload_size(32), ack_payload_available(false), dynamic_payloads_enabled(false),
+  pipe0_reading_address(0)
+{
+}
+
+/****************************************************************************/
+
+void RF24::setChannel(uint8_t channel)
+{
+  // TODO: This method could take advantage of the 'wide_band' calculation
+  // done in setChannel() to require certain channel spacing.
+
+  const uint8_t max_channel = 127;
+  write_register(RF_CH,min(channel,max_channel));
+}
+
+/****************************************************************************/
+
+void RF24::setPayloadSize(uint8_t size)
+{
+  const uint8_t max_payload_size = 32;
+  payload_size = min(size,max_payload_size);
+}
+
+/****************************************************************************/
+
+uint8_t RF24::getPayloadSize(void)
+{
+  return payload_size;
+}
+
+/****************************************************************************/
+
+static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS";
+static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS";
+static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS";
+static const char * const rf24_datarate_e_str_P[] PROGMEM = {
+  rf24_datarate_e_str_0,
+  rf24_datarate_e_str_1,
+  rf24_datarate_e_str_2,
+};
+static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01";
+static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+";
+static const char * const rf24_model_e_str_P[] PROGMEM = {
+  rf24_model_e_str_0,
+  rf24_model_e_str_1,
+};
+static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled";
+static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits";
+static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ;
+static const char * const rf24_crclength_e_str_P[] PROGMEM = {
+  rf24_crclength_e_str_0,
+  rf24_crclength_e_str_1,
+  rf24_crclength_e_str_2,
+};
+static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN";
+static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW";
+static const char rf24_pa_dbm_e_str_2[] PROGMEM = "LA_MED";
+static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_HIGH";
+static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = { 
+  rf24_pa_dbm_e_str_0,
+  rf24_pa_dbm_e_str_1,
+  rf24_pa_dbm_e_str_2,
+  rf24_pa_dbm_e_str_3,
+};
+
+void RF24::printDetails(void)
+{
+  print_status(get_status());
+
+  print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2);
+  print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4);
+  print_address_register(PSTR("TX_ADDR"),TX_ADDR);
+
+  print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6);
+  print_byte_register(PSTR("EN_AA"),EN_AA);
+  print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR);
+  print_byte_register(PSTR("RF_CH"),RF_CH);
+  print_byte_register(PSTR("RF_SETUP"),RF_SETUP);
+  print_byte_register(PSTR("CONFIG"),CONFIG);
+  print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2);
+
+  printf_P(PSTR("Data Rate\t = %S\r\n"),pgm_read_word(&rf24_datarate_e_str_P[getDataRate()]));
+  printf_P(PSTR("Model\t\t = %S\r\n"),pgm_read_word(&rf24_model_e_str_P[isPVariant()]));
+  printf_P(PSTR("CRC Length\t = %S\r\n"),pgm_read_word(&rf24_crclength_e_str_P[getCRCLength()]));
+  printf_P(PSTR("PA Power\t = %S\r\n"),pgm_read_word(&rf24_pa_dbm_e_str_P[getPALevel()]));
+}
+
+/****************************************************************************/
+
+void RF24::begin(void)
+{
+  // Initialize pins
+  pinMode(ce_pin,OUTPUT);
+  pinMode(csn_pin,OUTPUT);
+
+  // Initialize SPI bus
+  SPI.begin();
+
+  ce(LOW);
+  csn(HIGH);
+
+  // Must allow the radio time to settle else configuration bits will not necessarily stick.
+  // This is actually only required following power up but some settling time also appears to
+  // be required after resets too. For full coverage, we'll always assume the worst.
+  // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
+  // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
+  // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
+  delay( 5 ) ;
+
+  // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
+  // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
+  // sizes must never be used. See documentation for a more complete explanation.
+  write_register(SETUP_RETR,(B0100 << ARD) | (B1111 << ARC));
+
+  // Restore our default PA level
+  setPALevel( RF24_PA_MAX ) ;
+
+  // Determine if this is a p or non-p RF24 module and then
+  // reset our data rate back to default value. This works
+  // because a non-P variant won't allow the data rate to
+  // be set to 250Kbps.
+  if( setDataRate( RF24_250KBPS ) )
+  {
+    p_variant = true ;
+  }
+  
+  // Then set the data rate to the slowest (and most reliable) speed supported by all
+  // hardware.
+  setDataRate( RF24_1MBPS ) ;
+
+  // Initialize CRC and request 2-byte (16bit) CRC
+  setCRCLength( RF24_CRC_16 ) ;
+  
+  // Disable dynamic payloads, to match dynamic_payloads_enabled setting
+  write_register(DYNPD,0);
+
+  // Reset current status
+  // Notice reset and flush is the last thing we do
+  write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
+
+  // Set up default configuration.  Callers can always change it later.
+  // This channel should be universally safe and not bleed over into adjacent
+  // spectrum.
+  setChannel(76);
+
+  // Flush buffers
+  flush_rx();
+  flush_tx();
+}
+
+/****************************************************************************/
+
+void RF24::startListening(void)
+{
+  write_register(CONFIG, read_register(CONFIG) | _BV(PWR_UP) | _BV(PRIM_RX));
+  write_register(STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
+
+  // Restore the pipe0 adddress, if exists
+  if (pipe0_reading_address)
+    write_register(RX_ADDR_P0, reinterpret_cast(&pipe0_reading_address), 5);
+
+  // Flush buffers
+  flush_rx();
+  flush_tx();
+
+  // Go!
+  ce(HIGH);
+
+  // wait for the radio to come up (130us actually only needed)
+  delayMicroseconds(130);
+}
+
+/****************************************************************************/
+
+void RF24::stopListening(void)
+{
+  ce(LOW);
+  flush_tx();
+  flush_rx();
+}
+
+/****************************************************************************/
+
+void RF24::powerDown(void)
+{
+  write_register(CONFIG,read_register(CONFIG) & ~_BV(PWR_UP));
+}
+
+/****************************************************************************/
+
+void RF24::powerUp(void)
+{
+  write_register(CONFIG,read_register(CONFIG) | _BV(PWR_UP));
+}
+
+/******************************************************************/
+
+bool RF24::write( const void* buf, uint8_t len )
+{
+  bool result = false;
+
+  // Begin the write
+  startWrite(buf,len);
+
+  // ------------
+  // At this point we could return from a non-blocking write, and then call
+  // the rest after an interrupt
+
+  // Instead, we are going to block here until we get TX_DS (transmission completed and ack'd)
+  // or MAX_RT (maximum retries, transmission failed).  Also, we'll timeout in case the radio
+  // is flaky and we get neither.
+
+  // IN the end, the send should be blocking.  It comes back in 60ms worst case, or much faster
+  // if I tighted up the retry logic.  (Default settings will be 1500us.
+  // Monitor the send
+  uint8_t observe_tx;
+  uint8_t status;
+  uint32_t sent_at = millis();
+  const uint32_t timeout = 500; //ms to wait for timeout
+  do
+  {
+    status = read_register(OBSERVE_TX,&observe_tx,1);
+    IF_SERIAL_DEBUG(Serial.print(observe_tx,HEX));
+  }
+  while( ! ( status & ( _BV(TX_DS) | _BV(MAX_RT) ) ) && ( millis() - sent_at < timeout ) );
+
+  // The part above is what you could recreate with your own interrupt handler,
+  // and then call this when you got an interrupt
+  // ------------
+
+  // Call this when you get an interrupt
+  // The status tells us three things
+  // * The send was successful (TX_DS)
+  // * The send failed, too many retries (MAX_RT)
+  // * There is an ack packet waiting (RX_DR)
+  bool tx_ok, tx_fail;
+  whatHappened(tx_ok,tx_fail,ack_payload_available);
+  
+  //printf("%u%u%u\r\n",tx_ok,tx_fail,ack_payload_available);
+
+  result = tx_ok;
+  IF_SERIAL_DEBUG(Serial.print(result?"...OK.":"...Failed"));
+
+  // Handle the ack packet
+  if ( ack_payload_available )
+  {
+    ack_payload_length = getDynamicPayloadSize();
+    IF_SERIAL_DEBUG(Serial.print("[AckPacket]/"));
+    IF_SERIAL_DEBUG(Serial.println(ack_payload_length,DEC));
+  }
+
+  // Yay, we are done.
+
+  // Power down
+  powerDown();
+
+  // Flush buffers (Is this a relic of past experimentation, and not needed anymore??)
+  flush_tx();
+
+  return result;
+}
+/****************************************************************************/
+
+void RF24::startWrite( const void* buf, uint8_t len )
+{
+  // Transmitter power-up
+  write_register(CONFIG, ( read_register(CONFIG) | _BV(PWR_UP) ) & ~_BV(PRIM_RX) );
+  delayMicroseconds(150);
+
+  // Send the payload
+  write_payload( buf, len );
+
+  // Allons!
+  ce(HIGH);
+  delayMicroseconds(15);
+  ce(LOW);
+}
+
+/****************************************************************************/
+
+uint8_t RF24::getDynamicPayloadSize(void)
+{
+  uint8_t result = 0;
+
+  csn(LOW);
+  SPI.transfer( R_RX_PL_WID );
+  result = SPI.transfer(0xff);
+  csn(HIGH);
+
+  return result;
+}
+
+/****************************************************************************/
+
+bool RF24::available(void)
+{
+  return available(NULL);
+}
+
+/****************************************************************************/
+
+bool RF24::available(uint8_t* pipe_num)
+{
+  uint8_t status = get_status();
+
+  // Too noisy, enable if you really want lots o data!!
+  //IF_SERIAL_DEBUG(print_status(status));
+
+  bool result = ( status & _BV(RX_DR) );
+
+  if (result)
+  {
+    // If the caller wants the pipe number, include that
+    if ( pipe_num )
+      *pipe_num = ( status >> RX_P_NO ) & B111;
+
+    // Clear the status bit
+
+    // ??? Should this REALLY be cleared now?  Or wait until we
+    // actually READ the payload?
+
+    write_register(STATUS,_BV(RX_DR) );
+
+    // Handle ack payload receipt
+    if ( status & _BV(TX_DS) )
+    {
+      write_register(STATUS,_BV(TX_DS));
+    }
+  }
+
+  return result;
+}
+
+/****************************************************************************/
+
+bool RF24::read( void* buf, uint8_t len )
+{
+  // Fetch the payload
+  read_payload( buf, len );
+
+  // was this the last of the data available?
+  return read_register(FIFO_STATUS) & _BV(RX_EMPTY);
+}
+
+/****************************************************************************/
+
+void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
+{
+  // Read the status & reset the status in one easy call
+  // Or is that such a good idea?
+  uint8_t status = write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
+
+  // Report to the user what happened
+  tx_ok = status & _BV(TX_DS);
+  tx_fail = status & _BV(MAX_RT);
+  rx_ready = status & _BV(RX_DR);
+}
+
+/****************************************************************************/
+
+void RF24::openWritingPipe(uint64_t value)
+{
+  // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
+  // expects it LSB first too, so we're good.
+
+  write_register(RX_ADDR_P0, reinterpret_cast(&value), 5);
+  write_register(TX_ADDR, reinterpret_cast(&value), 5);
+
+  const uint8_t max_payload_size = 32;
+  write_register(RX_PW_P0,min(payload_size,max_payload_size));
+}
+
+/****************************************************************************/
+
+static const uint8_t child_pipe[] PROGMEM =
+{
+  RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5
+};
+static const uint8_t child_payload_size[] PROGMEM =
+{
+  RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5
+};
+static const uint8_t child_pipe_enable[] PROGMEM =
+{
+  ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5
+};
+
+void RF24::openReadingPipe(uint8_t child, uint64_t address)
+{
+  // If this is pipe 0, cache the address.  This is needed because
+  // openWritingPipe() will overwrite the pipe 0 address, so
+  // startListening() will have to restore it.
+  if (child == 0)
+    pipe0_reading_address = address;
+
+  if (child <= 6)
+  {
+    // For pipes 2-5, only write the LSB
+    if ( child < 2 )
+      write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast(&address), 5);
+    else
+      write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast(&address), 1);
+
+    write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
+
+    // Note it would be more efficient to set all of the bits for all open
+    // pipes at once.  However, I thought it would make the calling code
+    // more simple to do it this way.
+    write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
+  }
+}
+
+/****************************************************************************/
+
+void RF24::toggle_features(void)
+{
+  csn(LOW);
+  SPI.transfer( ACTIVATE );
+  SPI.transfer( 0x73 );
+  csn(HIGH);
+}
+
+/****************************************************************************/
+
+void RF24::enableDynamicPayloads(void)
+{
+  // Enable dynamic payload throughout the system
+  write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
+
+  // If it didn't work, the features are not enabled
+  if ( ! read_register(FEATURE) )
+  {
+    // So enable them and try again
+    toggle_features();
+    write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
+  }
+
+  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
+
+  // Enable dynamic payload on all pipes
+  //
+  // Not sure the use case of only having dynamic payload on certain
+  // pipes, so the library does not support it.
+  write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
+
+  dynamic_payloads_enabled = true;
+}
+
+/****************************************************************************/
+
+void RF24::enableAckPayload(void)
+{
+  //
+  // enable ack payload and dynamic payload features
+  //
+
+  write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
+
+  // If it didn't work, the features are not enabled
+  if ( ! read_register(FEATURE) )
+  {
+    // So enable them and try again
+    toggle_features();
+    write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
+  }
+
+  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
+
+  //
+  // Enable dynamic payload on pipes 0 & 1
+  //
+
+  write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
+}
+
+/****************************************************************************/
+
+void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
+{
+  const uint8_t* current = reinterpret_cast(buf);
+
+  csn(LOW);
+  SPI.transfer( W_ACK_PAYLOAD | ( pipe & B111 ) );
+  const uint8_t max_payload_size = 32;
+  uint8_t data_len = min(len,max_payload_size);
+  while ( data_len-- )
+    SPI.transfer(*current++);
+
+  csn(HIGH);
+}
+
+/****************************************************************************/
+
+bool RF24::isAckPayloadAvailable(void)
+{
+  bool result = ack_payload_available;
+  ack_payload_available = false;
+  return result;
+}
+
+/****************************************************************************/
+
+bool RF24::isPVariant(void)
+{
+  return p_variant ;
+}
+
+/****************************************************************************/
+
+void RF24::setAutoAck(bool enable)
+{
+  if ( enable )
+    write_register(EN_AA, B111111);
+  else
+    write_register(EN_AA, 0);
+}
+
+/****************************************************************************/
+
+void RF24::setAutoAck( uint8_t pipe, bool enable )
+{
+  if ( pipe <= 6 )
+  {
+    uint8_t en_aa = read_register( EN_AA ) ;
+    if( enable )
+    {
+      en_aa |= _BV(pipe) ;
+    }
+    else
+    {
+      en_aa &= ~_BV(pipe) ;
+    }
+    write_register( EN_AA, en_aa ) ;
+  }
+}
+
+/****************************************************************************/
+
+bool RF24::testCarrier(void)
+{
+  return ( read_register(CD) & 1 );
+}
+
+/****************************************************************************/
+
+bool RF24::testRPD(void)
+{
+  return ( read_register(RPD) & 1 ) ;
+}
+
+/****************************************************************************/
+
+void RF24::setPALevel(rf24_pa_dbm_e level)
+{
+  uint8_t setup = read_register(RF_SETUP) ;
+  setup &= ~(_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
+
+  // switch uses RAM (evil!)
+  if ( level == RF24_PA_MAX )
+  {
+    setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
+  }
+  else if ( level == RF24_PA_HIGH )
+  {
+    setup |= _BV(RF_PWR_HIGH) ;
+  }
+  else if ( level == RF24_PA_LOW )
+  {
+    setup |= _BV(RF_PWR_LOW);
+  }
+  else if ( level == RF24_PA_MIN )
+  {
+    // nothing
+  }
+  else if ( level == RF24_PA_ERROR )
+  {
+    // On error, go to maximum PA
+    setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
+  }
+
+  write_register( RF_SETUP, setup ) ;
+}
+
+/****************************************************************************/
+
+rf24_pa_dbm_e RF24::getPALevel(void)
+{
+  rf24_pa_dbm_e result = RF24_PA_ERROR ;
+  uint8_t power = read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
+
+  // switch uses RAM (evil!)
+  if ( power == (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) )
+  {
+    result = RF24_PA_MAX ;
+  }
+  else if ( power == _BV(RF_PWR_HIGH) )
+  {
+    result = RF24_PA_HIGH ;
+  }
+  else if ( power == _BV(RF_PWR_LOW) )
+  {
+    result = RF24_PA_LOW ;
+  }
+  else
+  {
+    result = RF24_PA_MIN ;
+  }
+
+  return result ;
+}
+
+/****************************************************************************/
+
+bool RF24::setDataRate(rf24_datarate_e speed)
+{
+  bool result = false;
+  uint8_t setup = read_register(RF_SETUP) ;
+
+  // HIGH and LOW '00' is 1Mbs - our default
+  wide_band = false ;
+  setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ;
+  if( speed == RF24_250KBPS )
+  {
+    // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
+    // Making it '10'.
+    wide_band = false ;
+    setup |= _BV( RF_DR_LOW ) ;
+  }
+  else
+  {
+    // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
+    // Making it '01'
+    if ( speed == RF24_2MBPS )
+    {
+      wide_band = true ;
+      setup |= _BV(RF_DR_HIGH);
+    }
+    else
+    {
+      // 1Mbs
+      wide_band = false ;
+    }
+  }
+  write_register(RF_SETUP,setup);
+
+  // Verify our result
+  if ( read_register(RF_SETUP) == setup )
+  {
+    result = true;
+  }
+  else
+  {
+    wide_band = false;
+  }
+
+  return result;
+}
+
+/****************************************************************************/
+
+rf24_datarate_e RF24::getDataRate( void )
+{
+  rf24_datarate_e result ;
+  uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH));
+  
+  // switch uses RAM (evil!)
+  // Order matters in our case below
+  if ( dr == _BV(RF_DR_LOW) )
+  {
+    // '10' = 250KBPS
+    result = RF24_250KBPS ;
+  }
+  else if ( dr == _BV(RF_DR_HIGH) )
+  {
+    // '01' = 2MBPS
+    result = RF24_2MBPS ;
+  }
+  else
+  {
+    // '00' = 1MBPS
+    result = RF24_1MBPS ;
+  }
+  return result ;
+}
+
+/****************************************************************************/
+
+void RF24::setCRCLength(rf24_crclength_e length)
+{
+  uint8_t config = read_register(CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ;
+  
+  // switch uses RAM (evil!)
+  if ( length == RF24_CRC_DISABLED )
+  {
+    // Do nothing, we turned it off above. 
+  }
+  else if ( length == RF24_CRC_8 )
+  {
+    config |= _BV(EN_CRC);
+  }
+  else
+  {
+    config |= _BV(EN_CRC);
+    config |= _BV( CRCO );
+  }
+  write_register( CONFIG, config ) ;
+}
+
+/****************************************************************************/
+
+rf24_crclength_e RF24::getCRCLength(void)
+{
+  rf24_crclength_e result = RF24_CRC_DISABLED;
+  uint8_t config = read_register(CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ;
+
+  if ( config & _BV(EN_CRC ) )
+  {
+    if ( config & _BV(CRCO) )
+      result = RF24_CRC_16;
+    else
+      result = RF24_CRC_8;
+  }
+
+  return result;
+}
+
+/****************************************************************************/
+
+void RF24::disableCRC( void )
+{
+  uint8_t disable = read_register(CONFIG) & ~_BV(EN_CRC) ;
+  write_register( CONFIG, disable ) ;
+}
+
+/****************************************************************************/
+void RF24::setRetries(uint8_t delay, uint8_t count)
+{
+ write_register(SETUP_RETR,(delay&0xf)<
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * @file RF24.h
+ *
+ * Class declaration for RF24 and helper enums
+ */
+
+#ifndef __RF24_H__
+#define __RF24_H__
+
+#ifdef __arm__
+#define SPI_CLOCK_DIV4 21
+#define _BV(bit) (1 << (bit))
+#define printf_P printf
+#endif
+
+#include 
+
+/**
+ * Power Amplifier level.
+ *
+ * For use with setPALevel()
+ */
+typedef enum { RF24_PA_MIN = 0,RF24_PA_LOW, RF24_PA_HIGH, RF24_PA_MAX, RF24_PA_ERROR } rf24_pa_dbm_e ;
+
+/**
+ * Data rate.  How fast data moves through the air.
+ *
+ * For use with setDataRate()
+ */
+typedef enum { RF24_1MBPS = 0, RF24_2MBPS, RF24_250KBPS } rf24_datarate_e;
+
+/**
+ * CRC Length.  How big (if any) of a CRC is included.
+ *
+ * For use with setCRCLength()
+ */
+typedef enum { RF24_CRC_DISABLED = 0, RF24_CRC_8, RF24_CRC_16 } rf24_crclength_e;
+
+/**
+ * Driver for nRF24L01(+) 2.4GHz Wireless Transceiver
+ */
+
+class RF24
+{
+private:
+  uint8_t ce_pin; /**< "Chip Enable" pin, activates the RX or TX role */
+  uint8_t csn_pin; /**< SPI Chip select */
+  bool wide_band; /* 2Mbs data rate in use? */
+  bool p_variant; /* False for RF24L01 and true for RF24L01P */
+  uint8_t payload_size; /**< Fixed size of payloads */
+  bool ack_payload_available; /**< Whether there is an ack payload waiting */
+  bool dynamic_payloads_enabled; /**< Whether dynamic payloads are enabled. */ 
+  uint8_t ack_payload_length; /**< Dynamic size of pending ack payload. */
+  uint64_t pipe0_reading_address; /**< Last address set on pipe 0 for reading. */
+
+protected:
+  /**
+   * @name Low-level internal interface.
+   *
+   *  Protected methods that address the chip directly.  Regular users cannot
+   *  ever call these.  They are documented for completeness and for developers who
+   *  may want to extend this class.
+   */
+  /**@{*/
+
+  /**
+   * Set chip select pin
+   *
+   * Running SPI bus at PI_CLOCK_DIV2 so we don't waste time transferring data
+   * and best of all, we make use of the radio's FIFO buffers. A lower speed
+   * means we're less likely to effectively leverage our FIFOs and pay a higher
+   * AVR runtime cost as toll.
+   *
+   * @param mode HIGH to take this unit off the SPI bus, LOW to put it on
+   */
+  void csn(int mode);
+
+  /**
+   * Set chip enable
+   *
+   * @param level HIGH to actively begin transmission or LOW to put in standby.  Please see data sheet
+   * for a much more detailed description of this pin.
+   */
+  void ce(int level);
+
+  /**
+   * Read a chunk of data in from a register
+   *
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param buf Where to put the data
+   * @param len How many bytes of data to transfer
+   * @return Current value of status register
+   */
+  uint8_t read_register(uint8_t reg, uint8_t* buf, uint8_t len);
+
+  /**
+   * Read single byte from a register
+   *
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @return Current value of register @p reg
+   */
+  uint8_t read_register(uint8_t reg);
+
+  /**
+   * Write a chunk of data to a register
+   *
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param buf Where to get the data
+   * @param len How many bytes of data to transfer
+   * @return Current value of status register
+   */
+  uint8_t write_register(uint8_t reg, const uint8_t* buf, uint8_t len);
+
+  /**
+   * Write a single byte to a register
+   *
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param value The new value to write
+   * @return Current value of status register
+   */
+  uint8_t write_register(uint8_t reg, uint8_t value);
+
+  /**
+   * Write the transmit payload
+   *
+   * The size of data written is the fixed payload size, see getPayloadSize()
+   *
+   * @param buf Where to get the data
+   * @param len Number of bytes to be sent
+   * @return Current value of status register
+   */
+  uint8_t write_payload(const void* buf, uint8_t len);
+
+  /**
+   * Read the receive payload
+   *
+   * The size of data read is the fixed payload size, see getPayloadSize()
+   *
+   * @param buf Where to put the data
+   * @param len Maximum number of bytes to read
+   * @return Current value of status register
+   */
+  uint8_t read_payload(void* buf, uint8_t len);
+
+  /**
+   * Empty the receive buffer
+   *
+   * @return Current value of status register
+   */
+  uint8_t flush_rx(void);
+
+  /**
+   * Empty the transmit buffer
+   *
+   * @return Current value of status register
+   */
+  uint8_t flush_tx(void);
+
+  /**
+   * Retrieve the current status of the chip
+   *
+   * @return Current value of status register
+   */
+  uint8_t get_status(void);
+
+  /**
+   * Decode and print the given status to stdout
+   *
+   * @param status Status value to print
+   *
+   * @warning Does nothing if stdout is not defined.  See fdevopen in stdio.h
+   */
+  void print_status(uint8_t status);
+
+  /**
+   * Decode and print the given 'observe_tx' value to stdout
+   *
+   * @param value The observe_tx value to print
+   *
+   * @warning Does nothing if stdout is not defined.  See fdevopen in stdio.h
+   */
+  void print_observe_tx(uint8_t value);
+
+  /**
+   * Print the name and value of an 8-bit register to stdout
+   *
+   * Optionally it can print some quantity of successive
+   * registers on the same line.  This is useful for printing a group
+   * of related registers on one line.
+   *
+   * @param name Name of the register
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param qty How many successive registers to print
+   */
+  void print_byte_register(const char* name, uint8_t reg, uint8_t qty = 1);
+
+  /**
+   * Print the name and value of a 40-bit address register to stdout
+   *
+   * Optionally it can print some quantity of successive
+   * registers on the same line.  This is useful for printing a group
+   * of related registers on one line.
+   *
+   * @param name Name of the register
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param qty How many successive registers to print
+   */
+  void print_address_register(const char* name, uint8_t reg, uint8_t qty = 1);
+
+  /**
+   * Turn on or off the special features of the chip
+   *
+   * The chip has certain 'features' which are only available when the 'features'
+   * are enabled.  See the datasheet for details.
+   */
+  void toggle_features(void);
+  /**@}*/
+
+public:
+  /**
+   * @name Primary public interface
+   *
+   *  These are the main methods you need to operate the chip
+   */
+  /**@{*/
+
+  /**
+   * Constructor
+   *
+   * Creates a new instance of this driver.  Before using, you create an instance
+   * and send in the unique pins that this chip is connected to.
+   *
+   * @param _cepin The pin attached to Chip Enable on the RF module
+   * @param _cspin The pin attached to Chip Select
+   */
+  RF24(uint8_t _cepin, uint8_t _cspin);
+
+  /**
+   * Begin operation of the chip
+   *
+   * Call this in setup(), before calling any other methods.
+   */
+  void begin(void);
+
+  /**
+   * Start listening on the pipes opened for reading.
+   *
+   * Be sure to call openReadingPipe() first.  Do not call write() while
+   * in this mode, without first calling stopListening().  Call
+   * isAvailable() to check for incoming traffic, and read() to get it.
+   */
+  void startListening(void);
+
+  /**
+   * Stop listening for incoming messages
+   *
+   * Do this before calling write().
+   */
+  void stopListening(void);
+
+  /**
+   * Write to the open writing pipe
+   *
+   * Be sure to call openWritingPipe() first to set the destination
+   * of where to write to.
+   *
+   * This blocks until the message is successfully acknowledged by
+   * the receiver or the timeout/retransmit maxima are reached.  In
+   * the current configuration, the max delay here is 60ms.
+   *
+   * The maximum size of data written is the fixed payload size, see
+   * getPayloadSize().  However, you can write less, and the remainder
+   * will just be filled with zeroes.
+   *
+   * @param buf Pointer to the data to be sent
+   * @param len Number of bytes to be sent
+   * @return True if the payload was delivered successfully false if not
+   */
+  bool write( const void* buf, uint8_t len );
+
+  /**
+   * Test whether there are bytes available to be read
+   *
+   * @return True if there is a payload available, false if none is
+   */
+  bool available(void);
+
+  /**
+   * Read the payload
+   *
+   * Return the last payload received
+   *
+   * The size of data read is the fixed payload size, see getPayloadSize()
+   *
+   * @note I specifically chose 'void*' as a data type to make it easier
+   * for beginners to use.  No casting needed.
+   *
+   * @param buf Pointer to a buffer where the data should be written
+   * @param len Maximum number of bytes to read into the buffer
+   * @return True if the payload was delivered successfully false if not
+   */
+  bool read( void* buf, uint8_t len );
+
+  /**
+   * Open a pipe for writing
+   *
+   * Only one pipe can be open at once, but you can change the pipe
+   * you'll listen to.  Do not call this while actively listening.
+   * Remember to stopListening() first.
+   *
+   * Addresses are 40-bit hex values, e.g.:
+   *
+   * @code
+   *   openWritingPipe(0xF0F0F0F0F0);
+   * @endcode
+   *
+   * @param address The 40-bit address of the pipe to open.  This can be
+   * any value whatsoever, as long as you are the only one writing to it
+   * and only one other radio is listening to it.  Coordinate these pipe
+   * addresses amongst nodes on the network.
+   */
+  void openWritingPipe(uint64_t address);
+
+  /**
+   * Open a pipe for reading
+   *
+   * Up to 6 pipes can be open for reading at once.  Open all the
+   * reading pipes, and then call startListening().
+   *
+   * @see openWritingPipe
+   *
+   * @warning Pipes 1-5 should share the first 32 bits.
+   * Only the least significant byte should be unique, e.g.
+   * @code
+   *   openReadingPipe(1,0xF0F0F0F0AA);
+   *   openReadingPipe(2,0xF0F0F0F066);
+   * @endcode
+   *
+   * @warning Pipe 0 is also used by the writing pipe.  So if you open
+   * pipe 0 for reading, and then startListening(), it will overwrite the
+   * writing pipe.  Ergo, do an openWritingPipe() again before write().
+   *
+   * @todo Enforce the restriction that pipes 1-5 must share the top 32 bits
+   *
+   * @param number Which pipe# to open, 0-5.
+   * @param address The 40-bit address of the pipe to open.
+   */
+  void openReadingPipe(uint8_t number, uint64_t address);
+
+  /**@}*/
+  /**
+   * @name Optional Configurators 
+   *
+   *  Methods you can use to get or set the configuration of the chip.
+   *  None are required.  Calling begin() sets up a reasonable set of
+   *  defaults.
+   */
+  /**@{*/
+  /**
+   * Set the number and delay of retries upon failed submit
+   *
+   * @param delay How long to wait between each retry, in multiples of 250us,
+   * max is 15.  0 means 250us, 15 means 4000us.
+   * @param count How many retries before giving up, max 15
+   */
+  void setRetries(uint8_t delay, uint8_t count);
+
+  /**
+   * Set RF communication channel
+   *
+   * @param channel Which RF channel to communicate on, 0-127
+   */
+  void setChannel(uint8_t channel);
+
+  /**
+   * Set Static Payload Size
+   *
+   * This implementation uses a pre-stablished fixed payload size for all
+   * transmissions.  If this method is never called, the driver will always
+   * transmit the maximum payload size (32 bytes), no matter how much
+   * was sent to write().
+   *
+   * @todo Implement variable-sized payloads feature
+   *
+   * @param size The number of bytes in the payload
+   */
+  void setPayloadSize(uint8_t size);
+
+  /**
+   * Get Static Payload Size
+   *
+   * @see setPayloadSize()
+   *
+   * @return The number of bytes in the payload
+   */
+  uint8_t getPayloadSize(void);
+
+  /**
+   * Get Dynamic Payload Size
+   *
+   * For dynamic payloads, this pulls the size of the payload off
+   * the chip
+   *
+   * @return Payload length of last-received dynamic payload
+   */
+  uint8_t getDynamicPayloadSize(void);
+  
+  /**
+   * Enable custom payloads on the acknowledge packets
+   *
+   * Ack payloads are a handy way to return data back to senders without
+   * manually changing the radio modes on both units.
+   *
+   * @see examples/pingpair_pl/pingpair_pl.pde
+   */
+  void enableAckPayload(void);
+
+  /**
+   * Enable dynamically-sized payloads
+   *
+   * This way you don't always have to send large packets just to send them
+   * once in a while.  This enables dynamic payloads on ALL pipes.
+   *
+   * @see examples/pingpair_pl/pingpair_dyn.pde
+   */
+  void enableDynamicPayloads(void);
+
+  /**
+   * Determine whether the hardware is an nRF24L01+ or not.
+   *
+   * @return true if the hardware is nRF24L01+ (or compatible) and false
+   * if its not.
+   */
+  bool isPVariant(void) ;
+
+  /**
+   * Enable or disable auto-acknowlede packets
+   *
+   * This is enabled by default, so it's only needed if you want to turn
+   * it off for some reason.
+   *
+   * @param enable Whether to enable (true) or disable (false) auto-acks
+   */
+  void setAutoAck(bool enable);
+
+  /**
+   * Enable or disable auto-acknowlede packets on a per pipeline basis.
+   *
+   * AA is enabled by default, so it's only needed if you want to turn
+   * it off/on for some reason on a per pipeline basis.
+   *
+   * @param pipe Which pipeline to modify
+   * @param enable Whether to enable (true) or disable (false) auto-acks
+   */
+  void setAutoAck( uint8_t pipe, bool enable ) ;
+
+  /**
+   * Set Power Amplifier (PA) level to one of four levels.
+   * Relative mnemonics have been used to allow for future PA level
+   * changes. According to 6.5 of the nRF24L01+ specification sheet,
+   * they translate to: RF24_PA_MIN=-18dBm, RF24_PA_LOW=-12dBm,
+   * RF24_PA_MED=-6dBM, and RF24_PA_HIGH=0dBm.
+   *
+   * @param level Desired PA level.
+   */
+  void setPALevel( rf24_pa_dbm_e level ) ;
+
+  /**
+   * Fetches the current PA level.
+   *
+   * @return Returns a value from the rf24_pa_dbm_e enum describing
+   * the current PA setting. Please remember, all values represented
+   * by the enum mnemonics are negative dBm. See setPALevel for
+   * return value descriptions.
+   */
+  rf24_pa_dbm_e getPALevel( void ) ;
+
+  /**
+   * Set the transmission data rate
+   *
+   * @warning setting RF24_250KBPS will fail for non-plus units
+   *
+   * @param speed RF24_250KBPS for 250kbs, RF24_1MBPS for 1Mbps, or RF24_2MBPS for 2Mbps
+   * @return true if the change was successful
+   */
+  bool setDataRate(rf24_datarate_e speed);
+  
+  /**
+   * Fetches the transmission data rate
+   *
+   * @return Returns the hardware's currently configured datarate. The value
+   * is one of 250kbs, RF24_1MBPS for 1Mbps, or RF24_2MBPS, as defined in the
+   * rf24_datarate_e enum.
+   */
+  rf24_datarate_e getDataRate( void ) ;
+
+  /**
+   * Set the CRC length
+   *
+   * @param length RF24_CRC_8 for 8-bit or RF24_CRC_16 for 16-bit
+   */
+  void setCRCLength(rf24_crclength_e length);
+
+  /**
+   * Get the CRC length
+   *
+   * @return RF24_DISABLED if disabled or RF24_CRC_8 for 8-bit or RF24_CRC_16 for 16-bit
+   */
+  rf24_crclength_e getCRCLength(void);
+
+  /**
+   * Disable CRC validation
+   *
+   */
+  void disableCRC( void ) ;
+
+  /**@}*/
+  /**
+   * @name Advanced Operation 
+   *
+   *  Methods you can use to drive the chip in more advanced ways 
+   */
+  /**@{*/
+
+  /**
+   * Print a giant block of debugging information to stdout
+   *
+   * @warning Does nothing if stdout is not defined.  See fdevopen in stdio.h
+   */
+  void printDetails(void);
+
+  /**
+   * Enter low-power mode
+   *
+   * To return to normal power mode, either write() some data or
+   * startListening, or powerUp().
+   */
+  void powerDown(void);
+
+  /**
+   * Leave low-power mode - making radio more responsive
+   *
+   * To return to low power mode, call powerDown().
+   */
+  void powerUp(void) ;
+
+  /**
+   * Test whether there are bytes available to be read
+   *
+   * Use this version to discover on which pipe the message
+   * arrived.
+   *
+   * @param[out] pipe_num Which pipe has the payload available
+   * @return True if there is a payload available, false if none is
+   */
+  bool available(uint8_t* pipe_num);
+
+  /**
+   * Non-blocking write to the open writing pipe
+   *
+   * Just like write(), but it returns immediately. To find out what happened
+   * to the send, catch the IRQ and then call whatHappened().
+   *
+   * @see write()
+   * @see whatHappened()
+   *
+   * @param buf Pointer to the data to be sent
+   * @param len Number of bytes to be sent
+   * @return True if the payload was delivered successfully false if not
+   */
+  void startWrite( const void* buf, uint8_t len );
+
+  /**
+   * Write an ack payload for the specified pipe
+   *
+   * The next time a message is received on @p pipe, the data in @p buf will
+   * be sent back in the acknowledgement.
+   *
+   * @warning According to the data sheet, only three of these can be pending
+   * at any time.  I have not tested this.
+   *
+   * @param pipe Which pipe# (typically 1-5) will get this response.
+   * @param buf Pointer to data that is sent
+   * @param len Length of the data to send, up to 32 bytes max.  Not affected
+   * by the static payload set by setPayloadSize().
+   */
+  void writeAckPayload(uint8_t pipe, const void* buf, uint8_t len);
+
+  /**
+   * Determine if an ack payload was received in the most recent call to
+   * write().
+   *
+   * Call read() to retrieve the ack payload.
+   *
+   * @warning Calling this function clears the internal flag which indicates
+   * a payload is available.  If it returns true, you must read the packet
+   * out as the very next interaction with the radio, or the results are
+   * undefined.
+   *
+   * @return True if an ack payload is available.
+   */
+  bool isAckPayloadAvailable(void);
+
+  /**
+   * Call this when you get an interrupt to find out why
+   *
+   * Tells you what caused the interrupt, and clears the state of
+   * interrupts.
+   *
+   * @param[out] tx_ok The send was successful (TX_DS)
+   * @param[out] tx_fail The send failed, too many retries (MAX_RT)
+   * @param[out] rx_ready There is a message waiting to be read (RX_DS)
+   */
+  void whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready);
+
+  /**
+   * Test whether there was a carrier on the line for the
+   * previous listening period.
+   *
+   * Useful to check for interference on the current channel.
+   *
+   * @return true if was carrier, false if not
+   */
+  bool testCarrier(void);
+
+  /**
+   * Test whether a signal (carrier or otherwise) greater than
+   * or equal to -64dBm is present on the channel. Valid only
+   * on nRF24L01P (+) hardware. On nRF24L01, use testCarrier().
+   *
+   * Useful to check for interference on the current channel and
+   * channel hopping strategies.
+   *
+   * @return true if signal => -64dBm, false if not
+   */
+  bool testRPD(void) ;
+
+  /**@}*/
+};
+
+/**
+ * @example GettingStarted.pde
+ *
+ * This is an example which corresponds to my "Getting Started" blog post:
+ * Getting Started with nRF24L01+ on Arduino. 
+ *
+ * It is an example of how to use the RF24 class.  Write this sketch to two 
+ * different nodes.  Put one of the nodes into 'transmit' mode by connecting 
+ * with the serial monitor and sending a 'T'.  The ping node sends the current 
+ * time to the pong node, which responds by sending the value back.  The ping 
+ * node can then see how long the whole cycle took.
+ */
+
+/**
+ * @example nordic_fob.pde
+ *
+ * This is an example of how to use the RF24 class to receive signals from the
+ * Sparkfun Nordic FOB.  See http://www.sparkfun.com/products/8602 .
+ * Thanks to Kirk Mower for providing test hardware.
+ */
+
+/**
+ * @example led_remote.pde
+ *
+ * This is an example of how to use the RF24 class to control a remote
+ * bank of LED's using buttons on a remote control.
+ *
+ * Every time the buttons change on the remote, the entire state of
+ * buttons is send to the led board, which displays the state.
+ */
+
+/**
+ * @example pingpair.pde
+ *
+ * This is an example of how to use the RF24 class.  Write this sketch to two
+ * different nodes, connect the role_pin to ground on one.  The ping node sends
+ * the current time to the pong node, which responds by sending the value back.
+ * The ping node can then see how long the whole cycle took.
+ */
+
+/**
+ * @example pingpair_maple.pde 
+ *
+ * This is an example of how to use the RF24 class on the Maple.  For a more
+ * detailed explanation, see my blog post:
+ * nRF24L01+ Running on Maple
+ *
+ * It will communicate well to an Arduino-based unit as well, so it's not for only Maple-to-Maple communication.
+ * 
+ * Write this sketch to two different nodes,
+ * connect the role_pin to ground on one.  The ping node sends the current time to the pong node,
+ * which responds by sending the value back.  The ping node can then see how long the whole cycle
+ * took.
+ */
+
+/**
+ * @example starping.pde
+ *
+ * This sketch is a more complex example of using the RF24 library for Arduino.
+ * Deploy this on up to six nodes.  Set one as the 'pong receiver' by tying the
+ * role_pin low, and the others will be 'ping transmit' units.  The ping units
+ * unit will send out the value of millis() once a second.  The pong unit will
+ * respond back with a copy of the value.  Each ping unit can get that response
+ * back, and determine how long the whole cycle took.
+ *
+ * This example requires a bit more complexity to determine which unit is which.
+ * The pong receiver is identified by having its role_pin tied to ground.
+ * The ping senders are further differentiated by a byte in eeprom.
+ */
+
+/**
+ * @example pingpair_pl.pde
+ *
+ * This is an example of how to do two-way communication without changing
+ * transmit/receive modes.  Here, a payload is set to the transmitter within
+ * the Ack packet of each transmission.  Note that the payload is set BEFORE
+ * the sender's message arrives.
+ */
+
+/**
+ * @example pingpair_irq.pde
+ *
+ * This is an example of how to user interrupts to interact with the radio.
+ * It builds on the pingpair_pl example, and uses ack payloads.
+ */
+
+/**
+ * @example pingpair_sleepy.pde
+ *
+ * This is an example of how to use the RF24 class to create a battery-
+ * efficient system.  It is just like the pingpair.pde example, but the
+ * ping node powers down the radio and sleeps the MCU after every
+ * ping/pong cycle.
+ */
+
+/**
+ * @example scanner.pde
+ *
+ * Example to detect interference on the various channels available.
+ * This is a good diagnostic tool to check whether you're picking a
+ * good channel for your application.
+ *
+ * Inspired by cpixip.
+ * See http://arduino.cc/forum/index.php/topic,54795.0.html
+ */
+
+/**
+ * @mainpage Driver for nRF24L01(+) 2.4GHz Wireless Transceiver
+ *
+ * @section Goals Design Goals
+ * 
+ * This library is designed to be...
+ * @li Maximally compliant with the intended operation of the chip
+ * @li Easy for beginners to use
+ * @li Consumed with a public interface that's similiar to other Arduino standard libraries
+ *
+ * @section News News
+ * 
+ * NOW COMPATIBLE WITH ARDUINO 1.0 - The 'master' branch and all examples work with both Arduino 1.0 and earlier versions.  
+ * Please open an issue if you find any problems using it with any version of Arduino.
+ *
+ * NOW COMPATIBLE WITH MAPLE - RF24 has been tested with the 
+ * Maple Native, 
+ * and should work with any Maple board.  See the pingpair_maple example.
+ * Note that only the pingpair_maple example has been tested on Maple, although
+ * the others can certainly be adapted.
+ *
+ * @section Useful Useful References
+ * 
+ * Please refer to:
+ *
+ * @li Documentation Main Page
+ * @li RF24 Class Documentation
+ * @li Source Code
+ * @li Downloads Page
+ * @li Chip Datasheet
+ *
+ * This chip uses the SPI bus, plus two chip control pins.  Remember that pin 10 must still remain an output, or
+ * the SPI hardware will go into 'slave' mode.
+ *
+ * @section More More Information
+ *
+ * @subpage FAQ
+ *
+ * @section Projects Projects
+ *
+ * Stuff I have built with RF24
+ *
+ * RF24 Getting Started - Finished Product
+ *
+ * Getting Started with nRF24L01+ on Arduino 
+ *
+ * Nordic FOB and nRF24L01+
+ *
+ * Using the Sparkfun Nordic FOB 
+ *
+ * RF Duinode V3 (2V4)
+ *
+ * Low-Power Wireless Sensor Node
+ *
+ * nRF24L01+ connected to Leaf Labs Maple Native
+ *
+ * nRF24L01+ Running on Maple
+ */
+
+#endif // __RF24_H__
+// vim:ai:cin:sts=2 sw=2 ft=cpp
+
diff --git a/hardware/digistump/sam/libraries/RF24/RF24_config.h b/hardware/digistump/sam/libraries/RF24/RF24_config.h
new file mode 100644
index 0000000..fc7397f
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/RF24_config.h
@@ -0,0 +1,65 @@
+
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef __RF24_CONFIG_H__
+#define __RF24_CONFIG_H__
+
+#if ARDUINO < 100
+#include 
+#else
+#include 
+#endif
+
+#include 
+
+// Stuff that is normally provided by Arduino
+#ifdef ARDUINO
+#include 
+#else
+#include 
+#include 
+#include 
+extern HardwareSPI SPI;
+#define _BV(x) (1<<(x))
+#endif
+
+#undef SERIAL_DEBUG
+#ifdef SERIAL_DEBUG
+#define IF_SERIAL_DEBUG(x) ({x;})
+#else
+#define IF_SERIAL_DEBUG(x)
+#endif
+
+// Avoid spurious warnings
+#if 1
+#if ! defined( NATIVE ) && defined( ARDUINO )
+#undef PROGMEM
+#define PROGMEM __attribute__(( section(".progmem.data") ))
+#undef PSTR
+#define PSTR(s) (__extension__({static const char __c[] PROGMEM = (s); &__c[0];}))
+#endif
+#endif
+
+// Progmem is Arduino-specific
+#ifdef ARDUINO
+#include 
+#define PRIPSTR "%S"
+#else
+typedef char const char;
+typedef uint16_t prog_uint16_t;
+#define PSTR(x) (x)
+#define printf_P printf
+#define strlen_P strlen
+#define PROGMEM
+#define pgm_read_word(p) (*(p)) 
+#define PRIPSTR "%s"
+#endif
+
+#endif // __RF24_CONFIG_H__
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/doxygen-custom.css b/hardware/digistump/sam/libraries/RF24/doxygen-custom.css
new file mode 100644
index 0000000..d7d0e12
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/doxygen-custom.css
@@ -0,0 +1,835 @@
+/* The standard CSS for doxygen */
+
+body, table, div, p, dl {
+	font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;
+	font-size: 12px;
+}
+
+/* @group Heading Levels */
+
+h1 {
+	font-size: 150%;
+}
+
+.title {
+	font-size: 150%;
+	font-weight: bold;
+	margin: 10px 2px;
+}
+
+h2 {
+	font-size: 120%;
+}
+
+h3 {
+	font-size: 100%;
+}
+
+dt {
+	font-weight: bold;
+}
+
+div.multicol {
+	-moz-column-gap: 1em;
+	-webkit-column-gap: 1em;
+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd, p.starttd {
+	margin-top: 2px;
+}
+
+p.endli {
+	margin-bottom: 0px;
+}
+
+p.enddd {
+	margin-bottom: 4px;
+}
+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	padding: 2px;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
+}
+
+div.navtab {
+	margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+a {
+	color: #3D578C;
+	font-weight: normal;
+	text-decoration: none;
+}
+
+.contents a:visited {
+	color: #4665A2;
+}
+
+a:hover {
+	text-decoration: underline;
+}
+
+a.qindex {
+	font-weight: bold;
+}
+
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+a.el {
+	font-weight: bold;
+}
+
+a.elRef {
+}
+
+a.code {
+	color: #4665A2;
+}
+
+a.codeRef {
+	color: #4665A2;
+}
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+.fragment {
+	font-family: monospace, fixed;
+	font-size: 105%;
+}
+
+pre.fragment {
+	border: 1px solid #C4CFE5;
+	background-color: #FBFCFD;
+	padding: 4px 6px;
+	margin: 4px 8px 4px 2px;
+	overflow: auto;
+	word-wrap: break-word;
+	font-size:  9pt;
+	line-height: 125%;
+}
+
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background: white;
+	color: black;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 10px;
+	margin-right: 5px;
+}
+
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+}
+
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+	
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+span.keyword {
+	color: #008000
+}
+
+span.keywordtype {
+	color: #604020
+}
+
+span.keywordflow {
+	color: #e08000
+}
+
+span.comment {
+	color: #800000
+}
+
+span.preprocessor {
+	color: #806020
+}
+
+span.stringliteral {
+	color: #002080
+}
+
+span.charliteral {
+	color: #008080
+}
+
+span.vhdldigit { 
+	color: #ff00ff 
+}
+
+span.vhdlchar { 
+	color: #000000 
+}
+
+span.vhdlkeyword { 
+	color: #700070 
+}
+
+span.vhdllogic { 
+	color: #ff0000 
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+hr {
+	height: 0px;
+	border: none;
+	border-top: 1px solid #4A6AAA;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memItemLeft, .memItemRight, .memTemplParams {
+	border-top: 1px solid #C4CFE5;
+}
+
+.memItemLeft, .memTemplItemLeft {
+        white-space: nowrap;
+}
+
+.memItemRight {
+	width: 100%;
+}
+
+.memTemplParams {
+	color: #4665A2;
+        white-space: nowrap;
+}
+
+/* @end */
+
+/* @group Member Details */
+
+/* Styles for detailed member documentation */
+
+.memtemplate {
+	font-size: 80%;
+	color: #4665A2;
+	font-weight: normal;
+	margin-left: 9px;
+}
+
+.memnav {
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+	margin: 2px;
+	margin-right: 15px;
+	padding: 2px;
+}
+
+.mempage {
+	width: 100%;
+}
+
+.memitem {
+	padding: 0;
+	margin-bottom: 10px;
+	margin-right: 5px;
+}
+
+.memname {
+        white-space: nowrap;
+        font-weight: bold;
+        margin-left: 6px;
+}
+
+.memproto {
+        border-top: 1px solid #A8B8D9;
+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
+        color: #253555;
+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+        /* opera specific markup */
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        border-top-right-radius: 8px;
+        border-top-left-radius: 8px;
+        /* firefox specific markup */
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        -moz-border-radius-topright: 8px;
+        -moz-border-radius-topleft: 8px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 8px;
+        -webkit-border-top-left-radius: 8px;
+        background-image:url('nav_f.png');
+        background-repeat:repeat-x;
+        background-color: #E2E8F2;
+
+}
+
+.memdoc {
+        border-bottom: 1px solid #A8B8D9;      
+        border-left: 1px solid #A8B8D9;      
+        border-right: 1px solid #A8B8D9; 
+        padding: 2px 5px;
+        background-color: #FBFCFD;
+        border-top-width: 0;
+        /* opera specific markup */
+        border-bottom-left-radius: 8px;
+        border-bottom-right-radius: 8px;
+        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        /* firefox specific markup */
+        -moz-border-radius-bottomleft: 8px;
+        -moz-border-radius-bottomright: 8px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
+        background-image: -moz-linear-gradient(center top, #FFFFFF 0%, #FFFFFF 60%, #F7F8FB 95%, #EEF1F7);
+        /* webkit specific markup */
+        -webkit-border-bottom-left-radius: 8px;
+        -webkit-border-bottom-right-radius: 8px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        background-image: -webkit-gradient(linear,center top,center bottom,from(#FFFFFF), color-stop(0.6,#FFFFFF), color-stop(0.60,#FFFFFF), color-stop(0.95,#F7F8FB), to(#EEF1F7));
+}
+
+.paramkey {
+	text-align: right;
+}
+
+.paramtype {
+	white-space: nowrap;
+}
+
+.paramname {
+	color: #602020;
+	white-space: nowrap;
+}
+.paramname em {
+	font-style: normal;
+}
+
+.params, .retval, .exception, .tparams {
+        border-spacing: 6px 2px;
+}       
+
+.params .paramname, .retval .paramname {
+        font-weight: bold;
+        vertical-align: top;
+}
+        
+.params .paramtype {
+        font-style: italic;
+        vertical-align: top;
+}       
+        
+.params .paramdir {
+        font-family: "courier new",courier,monospace;
+        vertical-align: top;
+}
+
+
+
+
+/* @end */
+
+/* @group Directory (tree) */
+
+/* for the tree view */
+
+.ftvtree {
+	font-family: sans-serif;
+	margin: 0px;
+}
+
+/* these are for tree view when used as main index */
+
+.directory {
+	font-size: 9pt;
+	font-weight: bold;
+	margin: 5px;
+}
+
+.directory h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+/*
+The following two styles can be used to replace the root node title
+with an image of your choice.  Simply uncomment the next two styles,
+specify the name of your image and be sure to set 'height' to the
+proper pixel height of your image.
+*/
+
+/*
+.directory h3.swap {
+	height: 61px;
+	background-repeat: no-repeat;
+	background-image: url("yourimage.gif");
+}
+.directory h3.swap span {
+	display: none;
+}
+*/
+
+.directory > h3 {
+	margin-top: 0;
+}
+
+.directory p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory div {
+	display: none;
+	margin: 0px;
+}
+
+.directory img {
+	vertical-align: -30%;
+}
+
+/* these are for tree view when not used as main index */
+
+.directory-alt {
+	font-size: 100%;
+	font-weight: bold;
+}
+
+.directory-alt h3 {
+	margin: 0px;
+	margin-top: 1em;
+	font-size: 11pt;
+}
+
+.directory-alt > h3 {
+	margin-top: 0;
+}
+
+.directory-alt p {
+	margin: 0px;
+	white-space: nowrap;
+}
+
+.directory-alt div {
+	display: none;
+	margin: 0px;
+}
+
+.directory-alt img {
+	vertical-align: -30%;
+}
+
+/* @end */
+
+div.dynheader {
+        margin-top: 8px;
+}
+
+address {
+	font-style: normal;
+	color: #2A3D61;
+}
+
+table.doxtable {
+	border-collapse:collapse;
+}
+
+table.doxtable td, table.doxtable th {
+	border: 1px solid #2D4068;
+	padding: 3px 7px 2px;
+}
+
+table.doxtable th {
+	background-color: #374F7F;
+	color: #FFFFFF;
+	font-size: 110%;
+	padding-bottom: 4px;
+	padding-top: 5px;
+	text-align:left;
+}
+
+.tabsearch {
+	top: 0px;
+	left: 10px;
+	height: 36px;
+	background-image: url('tab_b.png');
+	z-index: 101;
+	overflow: hidden;
+	font-size: 13px;
+}
+
+.navpath ul
+{
+	font-size: 11px;
+	background-image:url('tab_b.png');
+	background-repeat:repeat-x;
+	height:30px;
+	line-height:30px;
+	color:#8AA0CC;
+	border:solid 1px #C2CDE4;
+	overflow:hidden;
+	margin:0px;
+	padding:0px;
+}
+
+.navpath li
+{
+	list-style-type:none;
+	float:left;
+	padding-left:10px;
+	padding-right:15px;
+	background-image:url('bc_s.png');
+	background-repeat:no-repeat;
+	background-position:right;
+	color:#364D7C;
+}
+
+.navpath li.navelem a
+{
+	height:32px;
+	display:block;
+	text-decoration: none;
+	outline: none;
+}
+
+.navpath li.navelem a:hover
+{
+	color:#6884BD;
+}
+
+.navpath li.footer
+{
+        list-style-type:none;
+        float:right;
+        padding-left:10px;
+        padding-right:15px;
+        background-image:none;
+        background-repeat:no-repeat;
+        background-position:right;
+        color:#364D7C;
+        font-size: 8pt;
+}
+
+
+div.summary
+{
+	float: right;
+	font-size: 8pt;
+	padding-right: 5px;
+	width: 50%;
+	text-align: right;
+}       
+
+div.summary a
+{
+	white-space: nowrap;
+}
+
+div.ingroups
+{
+	font-size: 8pt;
+	padding-left: 5px;
+	width: 50%;
+	text-align: left;
+}
+
+div.ingroups a
+{
+	white-space: nowrap;
+}
+
+div.header
+{
+        background-image:url('nav_h.png');
+        background-repeat:repeat-x;
+	background-color: #F9FAFC;
+	margin:  0px;
+	border-bottom: 1px solid #C4CFE5;
+}
+
+div.headertitle
+{
+	padding: 5px 5px 5px 10px;
+}
+
+dl
+{
+        padding: 0 0 0 10px;
+}
+
+dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug
+{
+        border-left:4px solid;
+        padding: 0 0 0 6px;
+}
+
+dl.note
+{
+        border-color: #D0C000;
+}
+
+dl.warning, dl.attention
+{
+        border-color: #FF0000;
+}
+
+dl.pre, dl.post, dl.invariant
+{
+        border-color: #00D000;
+}
+
+dl.deprecated
+{
+        border-color: #505050;
+}
+
+dl.todo
+{
+        border-color: #00C0E0;
+}
+
+dl.test
+{
+        border-color: #3030E0;
+}
+
+dl.bug
+{
+        border-color: #C08050;
+}
+
+#projectlogo
+{
+	text-align: center;
+	vertical-align: bottom;
+	border-collapse: separate;
+}
+ 
+#projectlogo img
+{ 
+	border: 0px none;
+}
+ 
+#projectname
+{
+	font: 300% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 2px 0px;
+}
+    
+#projectbrief
+{
+	font: 120% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#projectnumber
+{
+	font: 50% Tahoma, Arial,sans-serif;
+	margin: 0px;
+	padding: 0px;
+}
+
+#titlearea
+{
+	padding: 0px;
+	margin: 0px;
+	width: 100%;
+	border-bottom: 1px solid #5373B4;
+}
+
+.image
+{
+        text-align: left;
+}
+
+.dotgraph
+{
+        text-align: center;
+}
+
+.mscgraph
+{
+        text-align: center;
+}
+
+.caption
+{
+	font-weight: bold;
+}
+
diff --git a/hardware/digistump/sam/libraries/RF24/examples/GettingStarted/GettingStarted.pde b/hardware/digistump/sam/libraries/RF24/examples/GettingStarted/GettingStarted.pde
new file mode 100644
index 0000000..851b1c1
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/GettingStarted/GettingStarted.pde
@@ -0,0 +1,227 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example for Getting Started with nRF24L01+ radios. 
+ *
+ * This is an example of how to use the RF24 class.  Write this sketch to two 
+ * different nodes.  Put one of the nodes into 'transmit' mode by connecting 
+ * with the serial monitor and sending a 'T'.  The ping node sends the current 
+ * time to the pong node, which responds by sending the value back.  The ping 
+ * node can then see how long the whole cycle took.
+ */
+
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+#include "printf.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 9 & 10 
+
+RF24 radio(53,52);
+
+//
+// Topology
+//
+
+// Radio pipe addresses for the 2 nodes to communicate.
+const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL };
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes
+// in this system.  Doing so greatly simplifies testing.  
+//
+
+// The various roles supported by this sketch
+typedef enum { role_ping_out = 1, role_pong_back } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"};
+
+// The role of the current running sketch
+role_e role = role_pong_back;
+
+void setup(void)
+{
+  //
+  // Print preamble
+  //
+
+  Serial.begin(57600);
+  printf_begin();
+  printf("\n\rRF24/examples/GettingStarted/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+  printf("*** PRESS 'T' to begin transmitting to the other node\n\r");
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  // optionally, increase the delay between retries & # of retries
+  radio.setRetries(15,15);
+
+  // optionally, reduce the payload size.  seems to
+  // improve reliability
+  //radio.setPayloadSize(8);
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens two pipes for these two nodes to communicate
+  // back and forth.
+  // Open 'our' pipe for writing
+  // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading)
+
+  //if ( role == role_ping_out )
+  {
+    //radio.openWritingPipe(pipes[0]);
+    radio.openReadingPipe(1,pipes[1]);
+  }
+  //else
+  {
+    //radio.openWritingPipe(pipes[1]);
+    //radio.openReadingPipe(1,pipes[0]);
+  }
+
+  //
+  // Start listening
+  //
+
+  radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+}
+
+void loop(void)
+{
+  //
+  // Ping out role.  Repeatedly send the current time
+  //
+
+  if (role == role_ping_out)
+  {
+    // First, stop listening so we can talk.
+    radio.stopListening();
+
+    // Take the time, and send it.  This will block until complete
+    unsigned long time = millis();
+    printf("Now sending %lu...",time);
+    bool ok = radio.write( &time, sizeof(unsigned long) );
+    
+    if (ok)
+      printf("ok...");
+    else
+      printf("failed.\n\r");
+
+    // Now, continue listening
+    radio.startListening();
+
+    // Wait here until we get a response, or timeout (250ms)
+    unsigned long started_waiting_at = millis();
+    bool timeout = false;
+    while ( ! radio.available() && ! timeout )
+      if (millis() - started_waiting_at > 200 )
+        timeout = true;
+
+    // Describe the results
+    if ( timeout )
+    {
+      printf("Failed, response timed out.\n\r");
+    }
+    else
+    {
+      // Grab the response, compare, and send to debugging spew
+      unsigned long got_time;
+      radio.read( &got_time, sizeof(unsigned long) );
+
+      // Spew it
+      printf("Got response %lu, round-trip delay: %lu\n\r",got_time,millis()-got_time);
+    }
+
+    // Try again 1s later
+    delay(1000);
+  }
+
+  //
+  // Pong back role.  Receive each packet, dump it out, and send it back
+  //
+
+  if ( role == role_pong_back )
+  {
+    // if there is data ready
+    if ( radio.available() )
+    {
+      // Dump the payloads until we've gotten everything
+      unsigned long got_time;
+      bool done = false;
+      while (!done)
+      {
+        // Fetch the payload, and see if this was the last one.
+        done = radio.read( &got_time, sizeof(unsigned long) );
+
+        // Spew it
+        printf("Got payload %lu...",got_time);
+
+	// Delay just a little bit to let the other unit
+	// make the transition to receiver
+	delay(20);
+      }
+
+      // First, stop listening so we can talk
+      radio.stopListening();
+
+      // Send the final one back.
+      radio.write( &got_time, sizeof(unsigned long) );
+      printf("Sent response.\n\r");
+
+      // Now, resume listening so we catch the next packets.
+      radio.startListening();
+    }
+  }
+
+  //
+  // Change roles
+  //
+
+  if ( Serial.available() )
+  {
+    char c = toupper(Serial.read());
+    if ( c == 'T' && role == role_pong_back )
+    {
+      printf("*** CHANGING TO TRANSMIT ROLE -- PRESS 'R' TO SWITCH BACK\n\r");
+
+      // Become the primary transmitter (ping out)
+      role = role_ping_out;
+      radio.openWritingPipe(pipes[0]);
+      radio.openReadingPipe(1,pipes[1]);
+    }
+    else if ( c == 'R' && role == role_ping_out )
+    {
+      printf("*** CHANGING TO RECEIVE ROLE -- PRESS 'T' TO SWITCH BACK\n\r");
+      
+      // Become the primary receiver (pong back)
+      role = role_pong_back;
+      radio.openWritingPipe(pipes[1]);
+      radio.openReadingPipe(1,pipes[0]);
+    }
+  }
+}
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/examples/GettingStarted/Jamfile b/hardware/digistump/sam/libraries/RF24/examples/GettingStarted/Jamfile
new file mode 100644
index 0000000..9a5f2c4
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/GettingStarted/Jamfile
@@ -0,0 +1,210 @@
+# (1) Project Information
+
+PROJECT_LIBS 	= SPI RF24 ;
+
+# (2) Board Information
+
+UPLOAD_PROTOCOL ?= arduino ;
+UPLOAD_SPEED 	?= 57600 ;
+MCU		?= atmega328p ;
+F_CPU 		?= 16000000 ;
+CORE		?= arduino ;
+VARIANT 	?= standard ;
+ARDUINO_VERSION	?= 100 ;
+
+# (3) USB Ports
+
+PORTS		= p4 p6 p9 u0 u1 u2 ;
+PORT_p6 	= /dev/tty.usbserial-A600eHIs ;
+PORT_p4 	= /dev/tty.usbserial-A40081RP ;
+PORT_p9		= /dev/tty.usbserial-A9007LmI ;
+PORT_u0 	= /dev/ttyUSB0 ;
+PORT_u1 	= /dev/ttyUSB1 ;
+PORT_u2 	= /dev/ttyUSB2 ;
+
+# (4) Location of AVR tools
+#
+# This configuration assumes using avr-tools that were obtained separate from the Arduino
+# distribution. 
+
+if $(OS) = MACOSX 
+{
+	AVR_BIN 	= /usr/local/avrtools/bin ;
+	AVR_ETC 	= /usr/local/avrtools/etc ;
+	AVR_INCLUDE	= /usr/local/avrtools/include ; 
+}
+else
+{
+	AVR_BIN 	?= /usr/bin ;
+	AVR_INCLUDE 	?= /usr/lib/avr/include ;
+	AVR_ETC 	= /etc ; 
+}
+
+# (5) Directories where Arduino core and libraries are located
+
+ARDUINO_DIR 	?= /opt/Arduino ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+
+#
+# --------------------------------------------------
+# Below this line usually never needs to be modified 
+#
+
+# Tool locations
+
+CC	  	= $(AVR_BIN)/avr-gcc ;
+C++	 	= $(AVR_BIN)/avr-g++ ;
+LINK	  	= $(AVR_BIN)/avr-gcc ;
+OBJCOPY 	= $(AVR_BIN)/avr-objcopy ;
+AVRDUDE 	= $(AVR_BIN)/avrdude ;
+
+# Flags
+
+DEFINES  	+= F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+OPTIM		= -Os ;
+CCFLAGS  	= -Wall -Wextra -mmcu=$(MCU) -ffunction-sections -fdata-sections ;
+C++FLAGS  	= $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ;
+LINKFLAGS  	= $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ;
+AVRDUDEFLAGS	= -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ;
+
+# Search everywhere for headers
+
+HDRS  	 	= $(PWD) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ;
+
+# Output locations
+
+LOCATE_TARGET	= $(F_CPU) ;
+LOCATE_SOURCE	= $(F_CPU) ;
+
+#
+# Custom rules
+#
+
+rule GitVersion
+{
+	Always $(<) ;
+	Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+	echo "const char program_version[] = \"\\" > $(<)
+	git log -1 --pretty=format:%h >> $(<)
+	echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule Pde
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+if ( $(ARDUINO_VERSION) < 100 )
+{
+	ARDUINO_H = WProgram.h ;
+}
+else
+{
+	ARDUINO_H = Arduino.h ;
+}
+
+actions Pde
+{
+	echo "#include <$(ARDUINO_H)>" > $(<) 
+	echo "#line 1 \"$(>)\"" >> $(<)
+	cat $(>) >> $(<) 
+}
+
+rule C++Pde
+{
+	local _CPP = $(>:B).cpp ;
+	Pde $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule UserObject
+{
+	switch $(>:S)
+	{
+		case .ino : C++Pde $(<) : $(>) ;
+		case .pde : C++Pde $(<) : $(>) ;
+	}
+}
+
+rule Objects
+{
+        local _i ;
+
+        for _i in [ FGristFiles $(<) ]
+        {
+		local _b = $(_i:B)$(SUFOBJ) ;
+		local _o = $(_b:G=$(SOURCE_GRIST:E)) ;
+                Object $(_o) : $(_i) ;
+                Depends obj : $(_o) ;
+        }
+}
+
+rule Main
+{
+        MainFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+        Objects $(>) ;
+}
+
+rule Hex
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends hex : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Hex
+{
+	$(OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule Upload
+{
+	Depends $(1) : $(2) ;
+	Depends $(2) : $(3) ;
+	NotFile $(1) ;
+	Always $(1) ;
+	Always $(2) ;
+	UploadAction $(2) : $(3) ;
+}
+
+actions UploadAction
+{
+	$(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+#
+# Targets
+#
+
+# Grab everything from the core directory
+CORE_MODULES  	= [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+LIB_MODULES  	= [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ;
+
+# Grab everything from the current dir
+PROJECT_MODULES += [ GLOB $(PWD) : *.c *.cpp *.pde *.ino ] ;
+
+# Main output executable
+MAIN		= $(PWD:B).elf ;
+
+Main $(MAIN) : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ;
+Hex $(MAIN:B).hex : $(MAIN) ;
+
+# Upload targets
+for _p in $(PORTS)
+{
+	Upload $(_p) : $(PORT_$(_p)) : $(MAIN:B).hex ;
+}
diff --git a/hardware/digistump/sam/libraries/RF24/examples/GettingStarted/printf.h b/hardware/digistump/sam/libraries/RF24/examples/GettingStarted/printf.h
new file mode 100644
index 0000000..990d79b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/GettingStarted/printf.h
@@ -0,0 +1,39 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  #if !defined(__arm__)
+fdevopen( &serial_putc, 0 );
+#endif
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/examples/led_remote/Jamfile b/hardware/digistump/sam/libraries/RF24/examples/led_remote/Jamfile
new file mode 100644
index 0000000..901f8da
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/led_remote/Jamfile
@@ -0,0 +1,206 @@
+PROJECT_NAME 	= $(PWD:B) ;
+PROJECT_DIR 	= . ;
+PROJECT_LIBS = SPI RF24 ; 
+
+OUT_DIR = ojam ;
+F_CPU 		= 16000000 ;
+MCU             = atmega328p ;
+PORTS           = /dev/tty.usbserial-A600eHIs /dev/tty.usbserial-A40081RP /dev/tty.usbserial-A9007LmI ;
+
+UPLOAD_RATE 	= 57600 ;
+AVRDUDE_PROTOCOL = stk500v1 ;
+COM 		= 33 ;
+
+# Host-specific overrides for locations 
+if $(OS) = MACOSX 
+{
+ARDUINO_VERSION	= 22 ;
+OLD_DIR 	= /opt/arduino-0021 ;
+AVR_TOOLS_PATH 	= $(OLD_DIR)/hardware/tools/avr/bin ;
+AVRDUDECONFIG_PATH = $(OLD_DIR)/hardware/tools/avr/etc ;
+ARDUINO_DIR 	= /opt/Arduino ;
+ARDUINO_AVR 	= /usr/lib/avr/include ;
+}
+
+# Where is everything?
+ARDUINO_VERSION	?= 22 ;
+AVR_TOOLS_PATH 	?= /usr/bin ;
+ARDUINO_DIR 	?= /opt/arduino-00$(ARDUINO_VERSION) ;
+ARDUINO_AVR 	?= $(ARDUINO_DIR)/hardware/tools/avr/avr/include/avr ;
+AVRDUDECONFIG_PATH ?= $(ARDUINO_DIR)/hardware/tools ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/arduino ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+AVR_CC  	= $(AVR_TOOLS_PATH)/avr-gcc ;
+AVR_CXX  	= $(AVR_TOOLS_PATH)/avr-g++ ;
+AVR_LD  	= $(AVR_TOOLS_PATH)/avr-gcc ;
+AVR_OBJCOPY 	= $(AVR_TOOLS_PATH)/avr-objcopy ;
+AVRDUDE 	= $(AVR_TOOLS_PATH)/avrdude ;
+
+DEFINES  	= F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+CTUNING  	= -ffunction-sections -fdata-sections ;
+CXXTUNING  	= -fno-exceptions -fno-strict-aliasing ; 
+CFLAGS  	= -Os -Wall -Wextra -mmcu=$(MCU) $(CTUNING) ;
+CXXFLAGS  	= $(CFLAGS) $(CXXTUNING) ;
+LDFLAGS  	= -Os -lm -Wl,--gc-sections -mmcu=atmega328p ;
+
+# Search everywhere for headers
+HDRS  	 	= $(PROJECT_DIR) $(ARDUINO_AVR) $(ARDUINO_CORE) [ GLOB $(ARDUINO_LIB) $(SKETCH_LIB) : [^.]* ] ;
+
+# Grab everything from the core directory
+CORE_MODULES  	= [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+LIB_MODULES  	= [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp ] ;
+
+# In addition to explicitly-specified program modules, pick up anything from the current
+# dir.
+PROJECT_MODULES += [ GLOB $(PROJECT_DIR) : *.c *.cpp *.pde ] ;
+
+# Shortcut for the out files
+OUT             = $(OUT_DIR)/$(PROJECT_NAME) ;
+
+# AvrDude setup
+AVRDUDE_FLAGS = -V -F -D -C $(AVRDUDECONFIG_PATH)/avrdude.conf -p $(MCU) -c $(AVRDUDE_PROTOCOL) -b $(UPLOAD_RATE) ;
+
+rule GitVersion
+{
+  Always $(<) ;
+  Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+  echo "const char program_version[] = \"\\" > $(<)
+  git log -1 --pretty=format:%h >> $(<)
+  echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule AvrCc
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrCc
+{
+  $(AVR_CC) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CFLAGS) $(>) 
+}
+
+rule AvrC++
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrC++
+{
+  $(AVR_CXX) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) 
+}
+
+rule Pde
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+}
+
+actions Pde
+{
+  echo "#include " > $(<) 
+  echo "#line 1 \"$(>)\"" >> $(<)
+  cat $(>) >> $(<) 
+}
+
+rule AvrPde
+{
+  local _CPP = $(OUT_DIR)/$(_I:B).cpp ;
+  Pde $(_CPP) : $(>) ;
+  AvrC++ $(<) : $(_CPP) ;
+}
+
+rule AvrObject
+{
+  switch $(>:S)
+  {
+    case .c :   AvrCc $(<) : $(>) ;
+    case .cpp : AvrC++ $(<) : $(>) ;
+    case .pde : AvrPde $(<) : $(>) ;
+  }
+}
+
+rule AvrObjects
+{
+  for _I in $(<) 
+  {
+    AvrObject $(OUT_DIR)/$(_I:B).o : $(_I) ;
+  }
+}
+
+rule AvrMainFromObjects
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  MkDir $(<:D) ;
+  Depends all : $(<) ;
+  Clean clean : $(<) ;
+}
+
+actions AvrMainFromObjects
+{
+  $(AVR_LD) $(LDFLAGS) -o $(<) $(>) 
+}
+
+rule AvrMain
+{
+  AvrMainFromObjects $(<) : $(OUT_DIR)/$(>:B).o ;
+  AvrObjects $(>) ;
+}
+
+rule AvrHex
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Depends hex : $(<) ;
+  Clean clean : $(<) ;
+}
+
+actions AvrHex
+{
+  $(AVR_OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule AvrUpload
+{
+  Depends $(1) : $(2) ;
+  Depends $(2) : $(3) ;
+  NotFile $(1) ;
+  Always $(1) ;
+  Always $(2) ;
+  AvrUploadAction $(2) : $(3) ;
+}
+
+actions AvrUploadAction
+{
+  $(AVRDUDE) $(AVRDUDE_FLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+AvrMain $(OUT).elf : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ;
+AvrHex $(OUT).hex : $(OUT).elf ;
+
+AvrUpload p6 : /dev/tty.usbserial-A600eHIs : $(OUT).hex ;
+AvrUpload p4 : /dev/tty.usbserial-A40081RP : $(OUT).hex ;
+AvrUpload p9 : /dev/tty.usbserial-A9007LmI : $(OUT).hex ;
+
diff --git a/hardware/digistump/sam/libraries/RF24/examples/led_remote/led_remote.pde b/hardware/digistump/sam/libraries/RF24/examples/led_remote/led_remote.pde
new file mode 100644
index 0000000..55f93e8
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/led_remote/led_remote.pde
@@ -0,0 +1,255 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example LED Remote
+ *
+ * This is an example of how to use the RF24 class to control a remote
+ * bank of LED's using buttons on a remote control.
+ *
+ * On the 'remote', connect any number of buttons or switches from
+ * an arduino pin to ground.  Update 'button_pins' to reflect the
+ * pins used.
+ *
+ * On the 'led' board, connect the same number of LED's from an
+ * arduino pin to a resistor to ground.  Update 'led_pins' to reflect
+ * the pins used.  Also connect a separate pin to ground and change
+ * the 'role_pin'.  This tells the sketch it's running on the LED board.
+ *
+ * Every time the buttons change on the remote, the entire state of
+ * buttons is send to the led board, which displays the state.
+ */
+
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+#include "printf.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 9 & 10
+
+RF24 radio(53,52);
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'led' board receiver
+// Leave open to be the 'remote' transmitter
+const int role_pin = A4;
+
+// Pins on the remote for buttons
+const uint8_t button_pins[] = { 2,3,4,5,6,7 };
+const uint8_t num_button_pins = sizeof(button_pins);
+
+// Pins on the LED board for LED's
+const uint8_t led_pins[] = { 2,3,4,5,6,7 };
+const uint8_t num_led_pins = sizeof(led_pins);
+
+//
+// Topology
+//
+
+// Single radio pipe address for the 2 nodes to communicate.
+const uint64_t pipe = 0xE8E8F0F0E1LL;
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes in this
+// system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_remote = 1, role_led } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Remote", "LED Board"};
+
+// The role of the current running sketch
+role_e role;
+
+//
+// Payload
+//
+
+uint8_t button_states[num_button_pins];
+uint8_t led_states[num_led_pins];
+
+//
+// Setup
+//
+
+void setup(void)
+{
+  //
+  // Role
+  //
+
+  // set up the role pin
+  pinMode(role_pin, INPUT);
+  digitalWrite(role_pin,HIGH);
+  delay(20); // Just to get a solid reading on the role pin
+
+  // read the address pin, establish our role
+  if ( digitalRead(role_pin) )
+    role = role_remote;
+  else
+    role = role_led;
+
+  //
+  // Print preamble
+  //
+
+  Serial.begin(57600);
+  printf_begin();
+  printf("\n\rRF24/examples/led_remote/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens a single pipes for these two nodes to communicate
+  // back and forth.  One listens on it, the other talks to it.
+
+  if ( role == role_remote )
+  {
+    radio.openWritingPipe(pipe);
+  }
+  else
+  {
+    radio.openReadingPipe(1,pipe);
+  }
+
+  //
+  // Start listening
+  //
+
+  if ( role == role_led )
+    radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+
+  //
+  // Set up buttons / LED's
+  //
+
+  // Set pull-up resistors for all buttons
+  if ( role == role_remote )
+  {
+    int i = num_button_pins;
+    while(i--)
+    {
+      pinMode(button_pins[i],INPUT);
+      digitalWrite(button_pins[i],HIGH);
+    }
+  }
+
+  // Turn LED's ON until we start getting keys
+  if ( role == role_led )
+  {
+    int i = num_led_pins;
+    while(i--)
+    {
+      pinMode(led_pins[i],OUTPUT);
+      led_states[i] = HIGH;
+      digitalWrite(led_pins[i],led_states[i]);
+    }
+  }
+
+}
+
+//
+// Loop
+//
+
+void loop(void)
+{
+  //
+  // Remote role.  If the state of any button has changed, send the whole state of
+  // all buttons.
+  //
+
+  if ( role == role_remote )
+  {
+    // Get the current state of buttons, and
+    // Test if the current state is different from the last state we sent
+    int i = num_button_pins;
+    bool different = false;
+    while(i--)
+    {
+      uint8_t state = ! digitalRead(button_pins[i]);
+      if ( state != button_states[i] )
+      {
+        different = true;
+        button_states[i] = state;
+      }
+    }
+
+    // Send the state of the buttons to the LED board
+    if ( different )
+    {
+      printf("Now sending...");
+      bool ok = radio.write( button_states, num_button_pins );
+      if (ok)
+        printf("ok\n\r");
+      else
+        printf("failed\n\r");
+    }
+
+    // Try again in a short while
+    delay(20);
+  }
+
+  //
+  // LED role.  Receive the state of all buttons, and reflect that in the LEDs
+  //
+
+  if ( role == role_led )
+  {
+    // if there is data ready
+    if ( radio.available() )
+    {
+      // Dump the payloads until we've gotten everything
+      bool done = false;
+      while (!done)
+      {
+        // Fetch the payload, and see if this was the last one.
+        done = radio.read( button_states, num_button_pins );
+
+        // Spew it
+        printf("Got buttons\n\r");
+
+        // For each button, if the button now on, then toggle the LED
+        int i = num_led_pins;
+        while(i--)
+        {
+          if ( button_states[i] )
+          {
+            led_states[i] ^= HIGH;
+            digitalWrite(led_pins[i],led_states[i]);
+          }
+        }
+      }
+    }
+  }
+}
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/examples/led_remote/printf.h b/hardware/digistump/sam/libraries/RF24/examples/led_remote/printf.h
new file mode 100644
index 0000000..990d79b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/led_remote/printf.h
@@ -0,0 +1,39 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  #if !defined(__arm__)
+fdevopen( &serial_putc, 0 );
+#endif
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/examples/nordic_fob/Jamfile b/hardware/digistump/sam/libraries/RF24/examples/nordic_fob/Jamfile
new file mode 100644
index 0000000..ec519f7
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/nordic_fob/Jamfile
@@ -0,0 +1,219 @@
+# (1) Project Information
+
+PROJECT_LIBS 	= RF24 SPI ; 
+PROJECT_DIRS	= $(PWD) ;
+
+# (2) Board Information
+
+UPLOAD_PROTOCOL ?= stk500v1 ;
+UPLOAD_SPEED 	?= 115200 ;
+MCU		?= atmega328p ;
+F_CPU 		?= 16000000 ;
+CORE		?= arduino ;
+VARIANT 	?= standard ;
+ARDUINO_VERSION	?= 100 ;
+
+# (3) USB Ports
+
+PORTS		= p4 p6 p9 u0 u1 u2 ;
+PORT_p6 	= /dev/tty.usbserial-A600eHIs ;
+PORT_p4 	= /dev/tty.usbserial-A40081RP ;
+PORT_p9		= /dev/tty.usbserial-A9007LmI ;
+PORT_u0 	= /dev/ttyUSB0 ;
+PORT_u1 	= /dev/ttyUSB1 ;
+PORT_u2 	= /dev/ttyUSB2 ;
+
+# (4) Location of AVR tools
+#
+# This configuration assumes using avr-tools that were obtained separate from the Arduino
+# distribution. 
+
+if $(OS) = MACOSX 
+{
+	AVR_BIN 	= /usr/local/avrtools/bin ;
+	AVR_ETC 	= /usr/local/avrtools/etc ;
+	AVR_INCLUDE	= /usr/local/avrtools/include ; 
+}
+else
+{
+	AVR_BIN 	= /usr/bin ;
+	AVR_INCLUDE 	= /usr/lib/avr/include ;
+	AVR_ETC 	= /etc ; 
+}
+
+# (5) Directories where Arduino core and libraries are located
+
+ARDUINO_DIR 	?= /opt/Arduino ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+
+#
+# --------------------------------------------------
+# Below this line usually never needs to be modified 
+#
+
+# Tool locations
+
+CC	  	= $(AVR_BIN)/avr-gcc ;
+C++	 	= $(AVR_BIN)/avr-g++ ;
+LINK	  	= $(AVR_BIN)/avr-gcc ;
+AR		= $(AVR_BIN)/avr-ar rcs ;
+RANLIB		= ;
+OBJCOPY 	= $(AVR_BIN)/avr-objcopy ;
+AVRDUDE 	= $(AVR_BIN)/avrdude ;
+
+# Flags
+
+DEFINES  	+= F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+OPTIM		= -Os ;
+CCFLAGS  	= -Wall -Wextra -Wno-strict-aliasing -mmcu=$(MCU) -ffunction-sections -fdata-sections ; 
+C++FLAGS  	= $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ;
+LINKFLAGS  	= $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ;
+AVRDUDEFLAGS	= -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ;
+
+# Search everywhere for headers
+
+HDRS  	 	= $(PROJECT_DIRS) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ;
+
+# Output locations
+
+LOCATE_TARGET	= $(F_CPU) ;
+LOCATE_SOURCE	= $(F_CPU) ;
+
+#
+# Custom rules
+#
+
+rule GitVersion
+{
+	Always $(<) ;
+	Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+	echo "const char program_version[] = \"\\" > $(<)
+	git log -1 --pretty=format:%h >> $(<)
+	echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule Pde
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+if ( $(ARDUINO_VERSION) < 100 )
+{
+	ARDUINO_H = WProgram.h ;
+}
+else
+{
+	ARDUINO_H = Arduino.h ;
+}
+
+actions Pde
+{
+	echo "#include <$(ARDUINO_H)>" > $(<) 
+	echo "#line 1 \"$(>)\"" >> $(<)
+	cat $(>) >> $(<) 
+}
+
+rule C++Pde
+{
+	local _CPP = $(>:B).cpp ;
+	Pde $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule UserObject
+{
+	switch $(>:S)
+	{
+		case .ino : C++Pde $(<) : $(>) ;
+		case .pde : C++Pde $(<) : $(>) ;
+	}
+}
+
+rule Objects
+{
+        local _i ;
+
+        for _i in [ FGristFiles $(<) ]
+        {
+		local _b = $(_i:B)$(SUFOBJ) ;
+		local _o = $(_b:G=$(SOURCE_GRIST:E)) ;
+                Object $(_o) : $(_i) ;
+                Depends obj : $(_o) ;
+        }
+}
+
+rule Library
+{
+	LibraryFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+	Objects $(>) ;
+}
+
+rule Main
+{
+        MainFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+        Objects $(>) ;
+}
+
+rule Hex
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends hex : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Hex
+{
+	$(OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule Upload
+{
+	Depends $(1) : $(2) ;
+	Depends $(2) : $(3) ;
+	NotFile $(1) ;
+	Always $(1) ;
+	Always $(2) ;
+	UploadAction $(2) : $(3) ;
+}
+
+actions UploadAction
+{
+	$(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+rule Arduino
+{
+	LINKFLAGS on $(<) = $(LINKFLAGS) -Wl,-Map=$(LOCATE_TARGET)/$(<:B).map ;
+	Main $(<) : $(>) ;
+	LinkLibraries $(<) : libs core ;
+	Hex $(<:B).hex : $(<) ;
+	for _p in $(PORTS)
+	{
+		Upload $(_p) : $(PORT_$(_p)) : $(<:B).hex ;
+	}
+}
+
+#
+# Targets
+#
+
+# Grab everything from the core directory
+Library core : [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+Library libs : [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ;
+
+# Main output executable
+Arduino $(PWD:B).elf : $(PROJECT_MODULES) [ GLOB $(PROJECT_DIRS) : *.c *.cpp *.pde *.ino ] ;
diff --git a/hardware/digistump/sam/libraries/RF24/examples/nordic_fob/nordic_fob.pde b/hardware/digistump/sam/libraries/RF24/examples/nordic_fob/nordic_fob.pde
new file mode 100644
index 0000000..1b78f7a
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/nordic_fob/nordic_fob.pde
@@ -0,0 +1,142 @@
+/*
+ Copyright (C) 2012 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example Nordic FOB Receiver 
+ *
+ * This is an example of how to use the RF24 class to receive signals from the
+ * Sparkfun Nordic FOB.  Thanks to Kirk Mower for providing test hardware.
+ *
+ * See blog post at http://maniacbug.wordpress.com/2012/01/08/nordic-fob/
+ */
+
+#include 
+#include 
+#include "nRF24L01.h"
+#include "printf.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 9 & 10
+
+RF24 radio(53,52);
+
+//
+// Payload
+//
+
+struct payload_t
+{
+  uint8_t buttons;
+  uint16_t id;
+  uint8_t empty;
+};
+
+const char* button_names[] = { "Up", "Down", "Left", "Right", "Center" }; 
+const int num_buttons = 5;
+
+//
+// Forward declarations
+//
+
+uint16_t flip_endian(uint16_t in);
+
+//
+// Setup
+//
+
+void setup(void)
+{
+  //
+  // Print preamble
+  //
+
+  Serial.begin(57600);
+  printf_begin();
+  printf("\r\nRF24/examples/nordic_fob/\r\n");
+
+  //
+  // Setup and configure rf radio according to the built-in parameters
+  // of the FOB.
+  //
+
+  radio.begin();
+  radio.setChannel(2);
+  radio.setPayloadSize(4);
+  radio.setAutoAck(false);
+  radio.setCRCLength(RF24_CRC_8);
+  radio.openReadingPipe(1,0xE7E7E7E7E7LL);
+
+  //
+  // Start listening
+  //
+
+  radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+}
+
+//
+// Loop
+//
+
+void loop(void)
+{
+  //
+  // Receive each packet, dump it out
+  //
+
+    // if there is data ready
+    if ( radio.available() )
+    {
+      // Get the packet from the radio
+      payload_t payload;
+      radio.read( &payload, sizeof(payload) );
+
+      // Print the ID of this message.  Note that the message
+      // is sent 'big-endian', so we have to flip it.
+      printf("#%05u Buttons ",flip_endian(payload.id));
+
+      // Print the name of each button 
+      int i = num_buttons;
+      while (i--)
+      {
+	if ( ! ( payload.buttons & _BV(i) ) )
+	{
+	  printf("%s ",button_names[i]);
+	}
+      }
+
+      // If no buttons, print None
+      if ( payload.buttons == _BV(num_buttons) - 1 )
+	printf("None");
+
+      printf("\r\n");
+    }
+}
+
+//
+// Helper functions
+//
+
+// Change a big-endian word into a little-endian
+uint16_t flip_endian(uint16_t in)
+{
+  uint16_t low = in >> 8;
+  uint16_t high = in << 8;
+
+  return high | low;
+}
+
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/examples/nordic_fob/printf.h b/hardware/digistump/sam/libraries/RF24/examples/nordic_fob/printf.h
new file mode 100644
index 0000000..990d79b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/nordic_fob/printf.h
@@ -0,0 +1,39 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  #if !defined(__arm__)
+fdevopen( &serial_putc, 0 );
+#endif
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair/Jamfile b/hardware/digistump/sam/libraries/RF24/examples/pingpair/Jamfile
new file mode 100644
index 0000000..18244ec
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair/Jamfile
@@ -0,0 +1,219 @@
+# (1) Project Information
+
+PROJECT_LIBS 	= SPI RF24 ; 
+PROJECT_DIRS	= $(PWD) ;
+
+# (2) Board Information
+
+UPLOAD_PROTOCOL ?= arduino ;
+UPLOAD_SPEED 	?= 115200 ;
+MCU		?= atmega328p ;
+F_CPU 		?= 16000000 ;
+CORE		?= arduino ;
+VARIANT 	?= standard ;
+ARDUINO_VERSION	?= 100 ;
+
+# (3) USB Ports
+
+PORTS		= p4 p6 p9 u0 u1 u2 ;
+PORT_p6 	= /dev/tty.usbserial-A600eHIs ;
+PORT_p4 	= /dev/tty.usbserial-A40081RP ;
+PORT_p9		= /dev/tty.usbserial-A9007LmI ;
+PORT_u0 	= /dev/ttyUSB0 ;
+PORT_u1 	= /dev/ttyUSB1 ;
+PORT_u2 	= /dev/ttyUSB2 ;
+
+# (4) Location of AVR tools
+#
+# This configuration assumes using avr-tools that were obtained separate from the Arduino
+# distribution. 
+
+if $(OS) = MACOSX 
+{
+	AVR_BIN 	?= /usr/local/avrtools/bin ;
+	AVR_ETC 	= /usr/local/avrtools/etc ;
+	AVR_INCLUDE	= /usr/local/avrtools/include ; 
+}
+else
+{
+	AVR_BIN 	?= /usr/bin ;
+	AVR_INCLUDE 	= /usr/lib/avr/include ;
+	AVR_ETC 	= /etc ; 
+}
+
+# (5) Directories where Arduino core and libraries are located
+
+ARDUINO_DIR 	?= /opt/Arduino ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+
+#
+# --------------------------------------------------
+# Below this line usually never needs to be modified 
+#
+
+# Tool locations
+
+CC	  	= $(AVR_BIN)/avr-gcc ;
+C++	 	= $(AVR_BIN)/avr-g++ ;
+LINK	  	= $(AVR_BIN)/avr-gcc ;
+AR		= $(AVR_BIN)/avr-ar rcs ;
+RANLIB		= ;
+OBJCOPY 	= $(AVR_BIN)/avr-objcopy ;
+AVRDUDE 	?= $(AVR_BIN)/avrdude ;
+
+# Flags
+
+DEFINES  	+= F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+OPTIM		= -Os ;
+CCFLAGS  	= -Wall -Wextra -Wno-strict-aliasing -mmcu=$(MCU) -ffunction-sections -fdata-sections ;
+C++FLAGS  	= $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ;
+LINKFLAGS  	= $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ;
+AVRDUDEFLAGS	= -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ;
+
+# Search everywhere for headers
+
+HDRS  	 	= $(PROJECT_DIRS) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ;
+
+# Output locations
+
+LOCATE_TARGET	= $(F_CPU) ;
+LOCATE_SOURCE	= $(F_CPU) ;
+
+#
+# Custom rules
+#
+
+rule GitVersion
+{
+	Always $(<) ;
+	Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+	echo "const char program_version[] = \"\\" > $(<)
+	git log -1 --pretty=format:%h >> $(<)
+	echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule Pde
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+if ( $(ARDUINO_VERSION) < 100 )
+{
+	ARDUINO_H = WProgram.h ;
+}
+else
+{
+	ARDUINO_H = Arduino.h ;
+}
+
+actions Pde
+{
+	echo "#include <$(ARDUINO_H)>" > $(<) 
+	echo "#line 1 \"$(>)\"" >> $(<)
+	cat $(>) >> $(<) 
+}
+
+rule C++Pde
+{
+	local _CPP = $(>:B).cpp ;
+	Pde $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule UserObject
+{
+	switch $(>:S)
+	{
+		case .ino : C++Pde $(<) : $(>) ;
+		case .pde : C++Pde $(<) : $(>) ;
+	}
+}
+
+rule Objects
+{
+        local _i ;
+
+        for _i in [ FGristFiles $(<) ]
+        {
+		local _b = $(_i:B)$(SUFOBJ) ;
+		local _o = $(_b:G=$(SOURCE_GRIST:E)) ;
+                Object $(_o) : $(_i) ;
+                Depends obj : $(_o) ;
+        }
+}
+
+rule Library
+{
+	LibraryFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+	Objects $(>) ;
+}
+
+rule Main
+{
+        MainFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+        Objects $(>) ;
+}
+
+rule Hex
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends hex : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Hex
+{
+	$(OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule Upload
+{
+	Depends $(1) : $(2) ;
+	Depends $(2) : $(3) ;
+	NotFile $(1) ;
+	Always $(1) ;
+	Always $(2) ;
+	UploadAction $(2) : $(3) ;
+}
+
+actions UploadAction
+{
+	$(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+rule Arduino
+{
+	LINKFLAGS on $(<) = $(LINKFLAGS) -Wl,-Map=$(LOCATE_TARGET)/$(<:B).map ;
+	Main $(<) : $(>) ;
+	LinkLibraries $(<) : core libs ;
+	Hex $(<:B).hex : $(<) ;
+	for _p in $(PORTS)
+	{
+		Upload $(_p) : $(PORT_$(_p)) : $(<:B).hex ;
+	}
+}
+
+#
+# Targets
+#
+
+# Grab everything from the core directory
+Library core : [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+Library libs : [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ;
+
+# Main output executable
+Arduino $(PWD:B).elf : $(PROJECT_MODULES) [ GLOB $(PROJECT_DIRS) : *.c *.cpp *.pde *.ino ] ;
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair/pingpair.pde b/hardware/digistump/sam/libraries/RF24/examples/pingpair/pingpair.pde
new file mode 100644
index 0000000..d474eeb
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair/pingpair.pde
@@ -0,0 +1,220 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example RF Radio Ping Pair
+ *
+ * This is an example of how to use the RF24 class.  Write this sketch to two different nodes,
+ * connect the role_pin to ground on one.  The ping node sends the current time to the pong node,
+ * which responds by sending the value back.  The ping node can then see how long the whole cycle
+ * took.
+ */
+
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+#include "printf.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 9 & 10
+
+RF24 radio(53,52);
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'ping' transmitter
+const int role_pin = 7;
+
+//
+// Topology
+//
+
+// Radio pipe addresses for the 2 nodes to communicate.
+const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL };
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes
+// in this system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_ping_out = 1, role_pong_back } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"};
+
+// The role of the current running sketch
+role_e role;
+
+void setup(void)
+{
+  //
+  // Role
+  //
+
+  // set up the role pin
+  pinMode(role_pin, INPUT);
+  digitalWrite(role_pin,HIGH);
+  delay(20); // Just to get a solid reading on the role pin
+
+  // read the address pin, establish our role
+  if ( ! digitalRead(role_pin) )
+    role = role_ping_out;
+  else
+    role = role_pong_back;
+
+  //
+  // Print preamble
+  //
+
+  Serial.begin(57600);
+  printf_begin();
+  printf("\n\rRF24/examples/pingpair/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  // optionally, increase the delay between retries & # of retries
+  radio.setRetries(15,15);
+
+  // optionally, reduce the payload size.  seems to
+  // improve reliability
+  radio.setPayloadSize(8);
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens two pipes for these two nodes to communicate
+  // back and forth.
+  // Open 'our' pipe for writing
+  // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading)
+
+  if ( role == role_ping_out )
+  {
+    radio.openWritingPipe(pipes[0]);
+    radio.openReadingPipe(1,pipes[1]);
+  }
+  else
+  {
+    radio.openWritingPipe(pipes[1]);
+    radio.openReadingPipe(1,pipes[0]);
+  }
+
+  //
+  // Start listening
+  //
+
+  radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+}
+
+void loop(void)
+{
+  //
+  // Ping out role.  Repeatedly send the current time
+  //
+
+  if (role == role_ping_out)
+  {
+    // First, stop listening so we can talk.
+    radio.stopListening();
+
+    // Take the time, and send it.  This will block until complete
+    unsigned long time = millis();
+    printf("Now sending %lu...",time);
+    bool ok = radio.write( &time, sizeof(unsigned long) );
+    
+    if (ok)
+      printf("ok...");
+    else
+      printf("failed.\n\r");
+
+    // Now, continue listening
+    radio.startListening();
+
+    // Wait here until we get a response, or timeout (250ms)
+    unsigned long started_waiting_at = millis();
+    bool timeout = false;
+    while ( ! radio.available() && ! timeout )
+      if (millis() - started_waiting_at > 200 )
+        timeout = true;
+
+    // Describe the results
+    if ( timeout )
+    {
+      printf("Failed, response timed out.\n\r");
+    }
+    else
+    {
+      // Grab the response, compare, and send to debugging spew
+      unsigned long got_time;
+      radio.read( &got_time, sizeof(unsigned long) );
+
+      // Spew it
+      printf("Got response %lu, round-trip delay: %lu\n\r",got_time,millis()-got_time);
+    }
+
+    // Try again 1s later
+    delay(1000);
+  }
+
+  //
+  // Pong back role.  Receive each packet, dump it out, and send it back
+  //
+
+  if ( role == role_pong_back )
+  {
+    // if there is data ready
+    if ( radio.available() )
+    {
+      // Dump the payloads until we've gotten everything
+      unsigned long got_time;
+      bool done = false;
+      while (!done)
+      {
+        // Fetch the payload, and see if this was the last one.
+        done = radio.read( &got_time, sizeof(unsigned long) );
+
+        // Spew it
+        printf("Got payload %lu...",got_time);
+
+	// Delay just a little bit to let the other unit
+	// make the transition to receiver
+	delay(20);
+      }
+
+      // First, stop listening so we can talk
+      radio.stopListening();
+
+      // Send the final one back.
+      radio.write( &got_time, sizeof(unsigned long) );
+      printf("Sent response.\n\r");
+
+      // Now, resume listening so we catch the next packets.
+      radio.startListening();
+    }
+  }
+}
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair/printf.h b/hardware/digistump/sam/libraries/RF24/examples/pingpair/printf.h
new file mode 100644
index 0000000..990d79b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair/printf.h
@@ -0,0 +1,39 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  #if !defined(__arm__)
+fdevopen( &serial_putc, 0 );
+#endif
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_dyn/Jamfile b/hardware/digistump/sam/libraries/RF24/examples/pingpair_dyn/Jamfile
new file mode 100644
index 0000000..901f8da
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_dyn/Jamfile
@@ -0,0 +1,206 @@
+PROJECT_NAME 	= $(PWD:B) ;
+PROJECT_DIR 	= . ;
+PROJECT_LIBS = SPI RF24 ; 
+
+OUT_DIR = ojam ;
+F_CPU 		= 16000000 ;
+MCU             = atmega328p ;
+PORTS           = /dev/tty.usbserial-A600eHIs /dev/tty.usbserial-A40081RP /dev/tty.usbserial-A9007LmI ;
+
+UPLOAD_RATE 	= 57600 ;
+AVRDUDE_PROTOCOL = stk500v1 ;
+COM 		= 33 ;
+
+# Host-specific overrides for locations 
+if $(OS) = MACOSX 
+{
+ARDUINO_VERSION	= 22 ;
+OLD_DIR 	= /opt/arduino-0021 ;
+AVR_TOOLS_PATH 	= $(OLD_DIR)/hardware/tools/avr/bin ;
+AVRDUDECONFIG_PATH = $(OLD_DIR)/hardware/tools/avr/etc ;
+ARDUINO_DIR 	= /opt/Arduino ;
+ARDUINO_AVR 	= /usr/lib/avr/include ;
+}
+
+# Where is everything?
+ARDUINO_VERSION	?= 22 ;
+AVR_TOOLS_PATH 	?= /usr/bin ;
+ARDUINO_DIR 	?= /opt/arduino-00$(ARDUINO_VERSION) ;
+ARDUINO_AVR 	?= $(ARDUINO_DIR)/hardware/tools/avr/avr/include/avr ;
+AVRDUDECONFIG_PATH ?= $(ARDUINO_DIR)/hardware/tools ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/arduino ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+AVR_CC  	= $(AVR_TOOLS_PATH)/avr-gcc ;
+AVR_CXX  	= $(AVR_TOOLS_PATH)/avr-g++ ;
+AVR_LD  	= $(AVR_TOOLS_PATH)/avr-gcc ;
+AVR_OBJCOPY 	= $(AVR_TOOLS_PATH)/avr-objcopy ;
+AVRDUDE 	= $(AVR_TOOLS_PATH)/avrdude ;
+
+DEFINES  	= F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+CTUNING  	= -ffunction-sections -fdata-sections ;
+CXXTUNING  	= -fno-exceptions -fno-strict-aliasing ; 
+CFLAGS  	= -Os -Wall -Wextra -mmcu=$(MCU) $(CTUNING) ;
+CXXFLAGS  	= $(CFLAGS) $(CXXTUNING) ;
+LDFLAGS  	= -Os -lm -Wl,--gc-sections -mmcu=atmega328p ;
+
+# Search everywhere for headers
+HDRS  	 	= $(PROJECT_DIR) $(ARDUINO_AVR) $(ARDUINO_CORE) [ GLOB $(ARDUINO_LIB) $(SKETCH_LIB) : [^.]* ] ;
+
+# Grab everything from the core directory
+CORE_MODULES  	= [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+LIB_MODULES  	= [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp ] ;
+
+# In addition to explicitly-specified program modules, pick up anything from the current
+# dir.
+PROJECT_MODULES += [ GLOB $(PROJECT_DIR) : *.c *.cpp *.pde ] ;
+
+# Shortcut for the out files
+OUT             = $(OUT_DIR)/$(PROJECT_NAME) ;
+
+# AvrDude setup
+AVRDUDE_FLAGS = -V -F -D -C $(AVRDUDECONFIG_PATH)/avrdude.conf -p $(MCU) -c $(AVRDUDE_PROTOCOL) -b $(UPLOAD_RATE) ;
+
+rule GitVersion
+{
+  Always $(<) ;
+  Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+  echo "const char program_version[] = \"\\" > $(<)
+  git log -1 --pretty=format:%h >> $(<)
+  echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule AvrCc
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrCc
+{
+  $(AVR_CC) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CFLAGS) $(>) 
+}
+
+rule AvrC++
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrC++
+{
+  $(AVR_CXX) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) 
+}
+
+rule Pde
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+}
+
+actions Pde
+{
+  echo "#include " > $(<) 
+  echo "#line 1 \"$(>)\"" >> $(<)
+  cat $(>) >> $(<) 
+}
+
+rule AvrPde
+{
+  local _CPP = $(OUT_DIR)/$(_I:B).cpp ;
+  Pde $(_CPP) : $(>) ;
+  AvrC++ $(<) : $(_CPP) ;
+}
+
+rule AvrObject
+{
+  switch $(>:S)
+  {
+    case .c :   AvrCc $(<) : $(>) ;
+    case .cpp : AvrC++ $(<) : $(>) ;
+    case .pde : AvrPde $(<) : $(>) ;
+  }
+}
+
+rule AvrObjects
+{
+  for _I in $(<) 
+  {
+    AvrObject $(OUT_DIR)/$(_I:B).o : $(_I) ;
+  }
+}
+
+rule AvrMainFromObjects
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  MkDir $(<:D) ;
+  Depends all : $(<) ;
+  Clean clean : $(<) ;
+}
+
+actions AvrMainFromObjects
+{
+  $(AVR_LD) $(LDFLAGS) -o $(<) $(>) 
+}
+
+rule AvrMain
+{
+  AvrMainFromObjects $(<) : $(OUT_DIR)/$(>:B).o ;
+  AvrObjects $(>) ;
+}
+
+rule AvrHex
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Depends hex : $(<) ;
+  Clean clean : $(<) ;
+}
+
+actions AvrHex
+{
+  $(AVR_OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule AvrUpload
+{
+  Depends $(1) : $(2) ;
+  Depends $(2) : $(3) ;
+  NotFile $(1) ;
+  Always $(1) ;
+  Always $(2) ;
+  AvrUploadAction $(2) : $(3) ;
+}
+
+actions AvrUploadAction
+{
+  $(AVRDUDE) $(AVRDUDE_FLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+AvrMain $(OUT).elf : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ;
+AvrHex $(OUT).hex : $(OUT).elf ;
+
+AvrUpload p6 : /dev/tty.usbserial-A600eHIs : $(OUT).hex ;
+AvrUpload p4 : /dev/tty.usbserial-A40081RP : $(OUT).hex ;
+AvrUpload p9 : /dev/tty.usbserial-A9007LmI : $(OUT).hex ;
+
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_dyn/pingpair_dyn.pde b/hardware/digistump/sam/libraries/RF24/examples/pingpair_dyn/pingpair_dyn.pde
new file mode 100644
index 0000000..9e517b0
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_dyn/pingpair_dyn.pde
@@ -0,0 +1,232 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example using Dynamic Payloads 
+ *
+ * This is an example of how to use payloads of a varying (dynamic) size. 
+ */
+
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+#include "printf.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 9 & 10
+
+RF24 radio(53,52);
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'ping' transmitter
+const int role_pin = 7;
+
+//
+// Topology
+//
+
+// Radio pipe addresses for the 2 nodes to communicate.
+const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL };
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes
+// in this system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_ping_out = 1, role_pong_back } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"};
+
+// The role of the current running sketch
+role_e role;
+
+//
+// Payload
+//
+
+const int min_payload_size = 4;
+const int max_payload_size = 32;
+const int payload_size_increments_by = 2;
+int next_payload_size = min_payload_size;
+
+char receive_payload[max_payload_size+1]; // +1 to allow room for a terminating NULL char
+
+void setup(void)
+{
+  //
+  // Role
+  //
+
+  // set up the role pin
+  pinMode(role_pin, INPUT);
+  digitalWrite(role_pin,HIGH);
+  delay(20); // Just to get a solid reading on the role pin
+
+  // read the address pin, establish our role
+  if ( digitalRead(role_pin) )
+    role = role_ping_out;
+  else
+    role = role_pong_back;
+
+  //
+  // Print preamble
+  //
+
+  Serial.begin(57600);
+  printf_begin();
+  printf("\n\rRF24/examples/pingpair_dyn/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  // enable dynamic payloads
+  radio.enableDynamicPayloads();
+
+  // optionally, increase the delay between retries & # of retries
+  radio.setRetries(15,15);
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens two pipes for these two nodes to communicate
+  // back and forth.
+  // Open 'our' pipe for writing
+  // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading)
+
+  if ( role == role_ping_out )
+  {
+    radio.openWritingPipe(pipes[0]);
+    radio.openReadingPipe(1,pipes[1]);
+  }
+  else
+  {
+    radio.openWritingPipe(pipes[1]);
+    radio.openReadingPipe(1,pipes[0]);
+  }
+
+  //
+  // Start listening
+  //
+
+  radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+}
+
+void loop(void)
+{
+  //
+  // Ping out role.  Repeatedly send the current time
+  //
+
+  if (role == role_ping_out)
+  {
+    // The payload will always be the same, what will change is how much of it we send.
+    static char send_payload[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ789012";
+
+    // First, stop listening so we can talk.
+    radio.stopListening();
+
+    // Take the time, and send it.  This will block until complete
+    printf("Now sending length %i...",next_payload_size);
+    radio.write( send_payload, next_payload_size );
+
+    // Now, continue listening
+    radio.startListening();
+
+    // Wait here until we get a response, or timeout
+    unsigned long started_waiting_at = millis();
+    bool timeout = false;
+    while ( ! radio.available() && ! timeout )
+      if (millis() - started_waiting_at > 500 )
+        timeout = true;
+
+    // Describe the results
+    if ( timeout )
+    {
+      printf("Failed, response timed out.\n\r");
+    }
+    else
+    {
+      // Grab the response, compare, and send to debugging spew
+      uint8_t len = radio.getDynamicPayloadSize();
+      radio.read( receive_payload, len );
+
+      // Put a zero at the end for easy printing
+      receive_payload[len] = 0;
+
+      // Spew it
+      printf("Got response size=%i value=%s\n\r",len,receive_payload);
+    }
+    
+    // Update size for next time.
+    next_payload_size += payload_size_increments_by;
+    if ( next_payload_size > max_payload_size )
+      next_payload_size = min_payload_size;
+
+    // Try again 1s later
+    delay(1000);
+  }
+
+  //
+  // Pong back role.  Receive each packet, dump it out, and send it back
+  //
+
+  if ( role == role_pong_back )
+  {
+    // if there is data ready
+    if ( radio.available() )
+    {
+      // Dump the payloads until we've gotten everything
+      uint8_t len;
+      bool done = false;
+      while (!done)
+      {
+        // Fetch the payload, and see if this was the last one.
+	len = radio.getDynamicPayloadSize();
+	done = radio.read( receive_payload, len );
+
+	// Put a zero at the end for easy printing
+	receive_payload[len] = 0;
+
+	// Spew it
+	printf("Got payload size=%i value=%s\n\r",len,receive_payload);
+      }
+
+      // First, stop listening so we can talk
+      radio.stopListening();
+
+      // Send the final one back.
+      radio.write( receive_payload, len );
+      printf("Sent response.\n\r");
+
+      // Now, resume listening so we catch the next packets.
+      radio.startListening();
+    }
+  }
+}
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_dyn/printf.h b/hardware/digistump/sam/libraries/RF24/examples/pingpair_dyn/printf.h
new file mode 100644
index 0000000..990d79b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_dyn/printf.h
@@ -0,0 +1,39 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  #if !defined(__arm__)
+fdevopen( &serial_putc, 0 );
+#endif
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_irq/Jamfile b/hardware/digistump/sam/libraries/RF24/examples/pingpair_irq/Jamfile
new file mode 100644
index 0000000..97237bc
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_irq/Jamfile
@@ -0,0 +1,219 @@
+# (1) Project Information
+
+PROJECT_LIBS 	= SPI RF24 ; 
+PROJECT_DIRS	= $(PWD) ;
+
+# (2) Board Information
+
+UPLOAD_PROTOCOL ?= arduino ;
+UPLOAD_SPEED 	?= 115200 ;
+MCU		?= atmega328p ;
+F_CPU 		?= 16000000 ;
+CORE		?= arduino ;
+VARIANT 	?= standard ;
+ARDUINO_VERSION	?= 100 ;
+
+# (3) USB Ports
+
+PORTS		= p4 p6 p9 u0 u1 u2 ;
+PORT_p6 	= /dev/tty.usbserial-A600eHIs ;
+PORT_p4 	= /dev/tty.usbserial-A40081RP ;
+PORT_p9		= /dev/tty.usbserial-A9007LmI ;
+PORT_u0 	= /dev/ttyUSB0 ;
+PORT_u1 	= /dev/ttyUSB1 ;
+PORT_u2 	= /dev/ttyUSB2 ;
+
+# (4) Location of AVR tools
+#
+# This configuration assumes using avr-tools that were obtained separate from the Arduino
+# distribution. 
+
+if $(OS) = MACOSX 
+{
+	AVR_BIN 	?= /usr/local/avrtools/bin ;
+	AVR_ETC 	= /usr/local/avrtools/etc ;
+	AVR_INCLUDE	= /usr/local/avrtools/include ; 
+}
+else
+{
+	AVR_BIN 	?= /usr/bin ;
+	AVR_INCLUDE 	?= /usr/lib/avr/include ;
+	AVR_ETC 	= /etc ; 
+}
+
+# (5) Directories where Arduino core and libraries are located
+
+ARDUINO_DIR 	?= /opt/Arduino ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+
+#
+# --------------------------------------------------
+# Below this line usually never needs to be modified 
+#
+
+# Tool locations
+
+CC	  	= $(AVR_BIN)/avr-gcc ;
+C++	 	= $(AVR_BIN)/avr-g++ ;
+LINK	  	= $(AVR_BIN)/avr-gcc ;
+AR		= $(AVR_BIN)/avr-ar rcs ;
+RANLIB		= ;
+OBJCOPY 	= $(AVR_BIN)/avr-objcopy ;
+AVRDUDE 	?= $(AVR_BIN)/avrdude ;
+
+# Flags
+
+DEFINES  	+= F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+OPTIM		= -Os ;
+CCFLAGS  	= -Wall -Wextra -Wno-strict-aliasing -mmcu=$(MCU) -ffunction-sections -fdata-sections ;
+C++FLAGS  	= $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ;
+LINKFLAGS  	= $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ;
+AVRDUDEFLAGS	= -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ;
+
+# Search everywhere for headers
+
+HDRS  	 	= $(PROJECT_DIRS) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ;
+
+# Output locations
+
+LOCATE_TARGET	= $(F_CPU) ;
+LOCATE_SOURCE	= $(F_CPU) ;
+
+#
+# Custom rules
+#
+
+rule GitVersion
+{
+	Always $(<) ;
+	Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+	echo "const char program_version[] = \"\\" > $(<)
+	git log -1 --pretty=format:%h >> $(<)
+	echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule Pde
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+if ( $(ARDUINO_VERSION) < 100 )
+{
+	ARDUINO_H = WProgram.h ;
+}
+else
+{
+	ARDUINO_H = Arduino.h ;
+}
+
+actions Pde
+{
+	echo "#include <$(ARDUINO_H)>" > $(<) 
+	echo "#line 1 \"$(>)\"" >> $(<)
+	cat $(>) >> $(<) 
+}
+
+rule C++Pde
+{
+	local _CPP = $(>:B).cpp ;
+	Pde $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule UserObject
+{
+	switch $(>:S)
+	{
+		case .ino : C++Pde $(<) : $(>) ;
+		case .pde : C++Pde $(<) : $(>) ;
+	}
+}
+
+rule Objects
+{
+        local _i ;
+
+        for _i in [ FGristFiles $(<) ]
+        {
+		local _b = $(_i:B)$(SUFOBJ) ;
+		local _o = $(_b:G=$(SOURCE_GRIST:E)) ;
+                Object $(_o) : $(_i) ;
+                Depends obj : $(_o) ;
+        }
+}
+
+rule Library
+{
+	LibraryFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+	Objects $(>) ;
+}
+
+rule Main
+{
+        MainFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+        Objects $(>) ;
+}
+
+rule Hex
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends hex : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Hex
+{
+	$(OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule Upload
+{
+	Depends $(1) : $(2) ;
+	Depends $(2) : $(3) ;
+	NotFile $(1) ;
+	Always $(1) ;
+	Always $(2) ;
+	UploadAction $(2) : $(3) ;
+}
+
+actions UploadAction
+{
+	$(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+rule Arduino
+{
+	LINKFLAGS on $(<) = $(LINKFLAGS) -Wl,-Map=$(LOCATE_TARGET)/$(<:B).map ;
+	Main $(<) : $(>) ;
+	LinkLibraries $(<) : core libs ;
+	Hex $(<:B).hex : $(<) ;
+	for _p in $(PORTS)
+	{
+		Upload $(_p) : $(PORT_$(_p)) : $(<:B).hex ;
+	}
+}
+
+#
+# Targets
+#
+
+# Grab everything from the core directory
+Library core : [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+Library libs : [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ;
+
+# Main output executable
+Arduino $(PWD:B).elf : $(PROJECT_MODULES) [ GLOB $(PROJECT_DIRS) : *.c *.cpp *.pde *.ino ] ;
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_irq/pingpair_irq.pde b/hardware/digistump/sam/libraries/RF24/examples/pingpair_irq/pingpair_irq.pde
new file mode 100644
index 0000000..47084a1
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_irq/pingpair_irq.pde
@@ -0,0 +1,216 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example of using interrupts
+ *
+ * This is an example of how to user interrupts to interact with the radio.
+ * It builds on the pingpair_pl example, and uses ack payloads.
+ */
+
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+#include "printf.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 9 & 10
+
+RF24 radio(8,9);
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'ping' transmitter
+const short role_pin = 7;
+
+//
+// Topology
+//
+
+// Single radio pipe address for the 2 nodes to communicate.
+const uint64_t pipe = 0xE8E8F0F0E1LL;
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes in this
+// system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_sender = 1, role_receiver } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Sender", "Receiver"};
+
+// The role of the current running sketch
+role_e role;
+
+// Interrupt handler, check the radio because we got an IRQ
+void check_radio(void);
+
+void setup(void)
+{
+  //
+  // Role
+  //
+
+  // set up the role pin
+  pinMode(role_pin, INPUT);
+  digitalWrite(role_pin,HIGH);
+  delay(20); // Just to get a solid reading on the role pin
+
+  // read the address pin, establish our role
+  if ( digitalRead(role_pin) )
+    role = role_sender;
+  else
+    role = role_receiver;
+
+  //
+  // Print preamble
+  //
+
+  Serial.begin(57600);
+  printf_begin();
+  printf("\n\rRF24/examples/pingpair_irq/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  // We will be using the Ack Payload feature, so please enable it
+  radio.enableAckPayload();
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens a single pipe for these two nodes to communicate
+  // back and forth.  One listens on it, the other talks to it.
+
+  if ( role == role_sender )
+  {
+    radio.openWritingPipe(pipe);
+  }
+  else
+  {
+    radio.openReadingPipe(1,pipe);
+  }
+
+  //
+  // Start listening
+  //
+
+  if ( role == role_receiver )
+    radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+
+  //
+  // Attach interrupt handler to interrupt #0 (using pin 2)
+  // on BOTH the sender and receiver
+  //
+
+  attachInterrupt(0, check_radio, FALLING);
+}
+
+static uint32_t message_count = 0;
+
+void loop(void)
+{
+  //
+  // Sender role.  Repeatedly send the current time
+  //
+
+  if (role == role_sender)
+  {
+    // Take the time, and send it.
+    unsigned long time = millis();
+    printf("Now sending %lu\n\r",time);
+    radio.startWrite( &time, sizeof(unsigned long) );
+
+    // Try again soon
+    delay(2000);
+  }
+
+  //
+  // Receiver role: Does nothing!  All the work is in IRQ
+  //
+
+}
+
+void check_radio(void)
+{
+  // What happened?
+  bool tx,fail,rx;
+  radio.whatHappened(tx,fail,rx);
+
+  // Have we successfully transmitted?
+  if ( tx )
+  {
+    if ( role == role_sender )
+      printf("Send:OK\n\r");
+
+    if ( role == role_receiver )
+      printf("Ack Payload:Sent\n\r");
+  }
+
+  // Have we failed to transmit?
+  if ( fail )
+  {
+    if ( role == role_sender )
+      printf("Send:Failed\n\r");
+
+    if ( role == role_receiver )
+      printf("Ack Payload:Failed\n\r");
+  }
+
+  // Transmitter can power down for now, because
+  // the transmission is done.
+  if ( ( tx || fail ) && ( role == role_sender ) )
+    radio.powerDown();
+
+  // Did we receive a message?
+  if ( rx )
+  {
+    // If we're the sender, we've received an ack payload
+    if ( role == role_sender )
+    {
+      radio.read(&message_count,sizeof(message_count));
+      printf("Ack:%lu\n\r",message_count);
+    }
+
+    // If we're the receiver, we've received a time message
+    if ( role == role_receiver )
+    {
+      // Get this payload and dump it
+      static unsigned long got_time;
+      radio.read( &got_time, sizeof(got_time) );
+      printf("Got payload %lu\n\r",got_time);
+
+      // Add an ack packet for the next time around.  This is a simple
+      // packet counter
+      radio.writeAckPayload( 1, &message_count, sizeof(message_count) );
+      ++message_count;
+    }
+  }
+}
+
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_irq/printf.h b/hardware/digistump/sam/libraries/RF24/examples/pingpair_irq/printf.h
new file mode 100644
index 0000000..990d79b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_irq/printf.h
@@ -0,0 +1,39 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  #if !defined(__arm__)
+fdevopen( &serial_putc, 0 );
+#endif
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_maple/Jamfile b/hardware/digistump/sam/libraries/RF24/examples/pingpair_maple/Jamfile
new file mode 100644
index 0000000..798096c
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_maple/Jamfile
@@ -0,0 +1,182 @@
+MCU		= cortex-m3 ;
+CHIP		= STM32F103ZE ;
+BOARD		= maple_native ;
+
+#CHIP		= at91sam3u4 ;
+#BOARD		= sam3u-ek ;
+
+if ! $(TOOLSET)
+{
+	TOOLSET = devkit ;
+	Echo "Assuming TOOLSET=devkit" ;
+}
+
+if $(TOOLSET) = yagarto
+{
+	TOOLS_PATH	= ~/Source/yagarto-4.6.2/bin ;
+	TOOLS_ARCH	= arm-none-eabi- ;
+}
+if $(TOOLSET) = yagarto-install
+{
+	TOOLS_PATH	= ~/Source/yagarto/install/bin ;
+	TOOLS_ARCH	= arm-none-eabi- ;
+}
+else if $(TOOLSET) = devkit
+{
+	TOOLS_PATH	= /opt/devkitARM/bin ;
+	TOOLS_ARCH	= arm-eabi- ;
+}
+else if $(TOOLSET) = maple
+{
+	TOOLS_PATH	= /opt/Maple/Resources/Java/hardware/tools/arm/bin ; 
+	TOOLS_ARCH	= arm-none-eabi- ;
+}
+else if $(TOOLSET) = ports
+{
+	TOOLS_PATH	= /opt/local/bin ;
+	TOOLS_ARCH	= arm-none-eabi- ;
+}
+
+CC	  	= $(TOOLS_PATH)/$(TOOLS_ARCH)gcc ;
+C++	 	= $(TOOLS_PATH)/$(TOOLS_ARCH)g++ ;
+AS	  	= $(TOOLS_PATH)/$(TOOLS_ARCH)gcc -c ;
+LINK	  	= $(TOOLS_PATH)/$(TOOLS_ARCH)g++ ;
+OBJCOPY 	= $(TOOLS_PATH)/$(TOOLS_ARCH)objcopy ;
+DFU		= dfu-util ;
+
+DEFINES  	+= VECT_TAB_FLASH BOARD_$(BOARD) MCU_$(CHIP) ERROR_LED_PORT=GPIOC ERROR_LED_PIN=15 STM32_HIGH_DENSITY MAPLE_IDE ;
+OPTIM		= -Os ;
+MFLAGS		= cpu=$(MCU) thumb arch=armv7-m ;
+CCFLAGS  	= -Wall -m$(MFLAGS) -g -nostdlib -ffunction-sections -fdata-sections -Wl,--gc-sections ;
+C++FLAGS  	= $(CCFLAGS) -fno-rtti -fno-exceptions ; 
+LINKFLAGS  	+= -m$(MFLAGS) -Xlinker --gc-sections ;
+DFUFLAGS	= -a1 -d 0x1eaf:0x0003 -R ;
+
+MAPLE_DIR	= $(HOME)/Source/SAM3U/libmaple ;
+MAPLE_LIBS	= Servo LiquidCrystal Wire FreeRTOS ;
+MAPLE_SUBDIRS	= wirish wirish/comm wirish/boards libmaple libmaple/usb libmaple/usb/usb_lib ; 
+
+SKETCH_DIR	= $(HOME)/Source/Arduino ;
+SKETCH_LIBS	= RF24 ;
+
+MODULE_DIRS	= . $(MAPLE_DIR)/$(MAPLE_SUBDIRS) $(MAPLE_DIR)/libraries/$(MAPLE_LIBS) $(SKETCH_DIR)/libraries/$(SKETCH_LIBS) ;
+HDRS		= $(MODULE_DIRS) ;
+LOCATE_TARGET	= out/$(TOOLSET) ;
+LOCATE_SOURCE	= $(LOCATE_TARGET) ; 
+
+rule Pde
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+if ( $(ARDUINO_VERSION) < 100 )
+{
+	ARDUINO_H = WProgram.h ;
+}
+else
+{
+	ARDUINO_H = Arduino.h ;
+}
+
+actions Pde
+{
+	echo "#include <$(ARDUINO_H)>" > $(<) 
+	echo "#line 1 \"$(>)\"" >> $(<)
+	cat $(>) >> $(<) 
+}
+
+rule C++Pde
+{
+	local _CPP = $(>:B).cpp ;
+	Pde $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule Hex
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends hex : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Hex
+{
+	$(OBJCOPY) -O ihex $(>) $(<)
+}
+
+rule Binary
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends binary : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Binary
+{
+	$(OBJCOPY) -O binary $(>) $(<)
+}
+
+rule UserObject
+{
+	switch $(>:S)
+	{
+		case .S : As $(<) : $(>) ;
+		case .ino : C++Pde $(<) : $(>) ;
+		case .pde : C++Pde $(<) : $(>) ;
+	}
+}
+
+rule Upload
+{
+	Depends up : $(<) ;
+	NotFile up ;
+	Always $(<) ;
+	Always up ;
+}
+
+actions Upload
+{
+	$(DFU) $(DFUFLAGS)  -D $(<)
+}
+
+# Override base objects rule, so all output can go in the output dir
+rule Objects
+{
+        local _i ;
+
+        for _i in [ FGristFiles $(<) ]
+        {
+		local _b = $(_i:B)$(SUFOBJ) ;
+		local _o = $(_b:G=$(SOURCE_GRIST:E)) ;
+                Object $(_o) : $(_i) ;
+                Depends obj : $(_o) ;
+        }
+}
+
+# Override base main rule, so all output can go in the output dir
+rule Main
+{
+        MainFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+        Objects $(>) ;
+}
+
+# Modules
+MODULES	= [ GLOB $(MODULE_DIRS) : *.pde *.c *.cpp *.S ] ; 
+
+# Main output executable
+MAIN		= $(PWD:B).elf ;
+
+# Linker script
+LINK_DIR	= $(MAPLE_DIR)/support/ld ;
+LINKSCRIPT	= $(LINK_DIR)/$(BOARD)/flash.ld ; 
+
+# Bring in the map and link script
+LINKFLAGS	+= -Wl,-Map=$(LOCATE_TARGET)/$(MAIN:B).map -T$(LINKSCRIPT) -L$(LINK_DIR) ;
+
+Main $(MAIN) : $(MODULES) ;
+Binary $(MAIN:B).bin : $(MAIN) ;
+Upload $(MAIN:B).bin ;
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_maple/main.cpp b/hardware/digistump/sam/libraries/RF24/examples/pingpair_maple/main.cpp
new file mode 100644
index 0000000..b4f976d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_maple/main.cpp
@@ -0,0 +1,87 @@
+#ifdef MAPLE_IDE
+
+#include 
+#include "wirish.h"
+
+extern void setup(void);
+extern void loop(void);
+
+void board_start(const char* program_name)
+{
+  // Set up the LED to steady on
+  pinMode(BOARD_LED_PIN, OUTPUT);
+  digitalWrite(BOARD_LED_PIN, HIGH);
+
+  // Setup the button as input
+  pinMode(BOARD_BUTTON_PIN, INPUT);
+  digitalWrite(BOARD_BUTTON_PIN, HIGH);
+
+  SerialUSB.begin();
+  SerialUSB.println("Press BUT");
+
+  // Wait for button press
+  while ( !isButtonPressed() )
+  {
+  }
+
+  SerialUSB.println("Welcome!");
+  SerialUSB.println(program_name);
+
+  int i = 11;
+  while (i--)
+  {
+    toggleLED();
+    delay(50);
+  }
+}
+
+/**
+ * Custom version of _write, which will print to the USB.
+ * In order to use it you MUST ADD __attribute__((weak))
+ * to _write in libmaple/syscalls.c
+*/
+extern "C" int _write (int file, char * ptr, int len)
+{
+  if ( (file != 1) && (file != 2) )
+    return 0; 
+  else
+    SerialUSB.write(ptr,len);
+  return len;
+}
+
+/**
+ * Re-entrant version of _write.  Yagarto and Devkit now use
+ * the re-entrant newlib, so these get called instead of the
+ * non_r versions.
+ */
+extern "C" int _write_r (void*, int file, char * ptr, int len)
+{
+  return _write( file, ptr, len);
+}
+
+__attribute__((constructor)) __attribute__ ((weak)) void premain()
+{
+  init();
+}
+
+__attribute__((weak)) void setup(void)
+{
+  board_start("No program defined");
+}
+
+__attribute__((weak)) void loop(void)
+{
+}
+
+__attribute__((weak)) int main(void)
+{
+  setup();
+
+  while (true)
+  {
+    loop();
+  }
+  return 0;
+}
+#endif // ifdef MAPLE_IDE
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_maple/pingpair_maple.pde b/hardware/digistump/sam/libraries/RF24/examples/pingpair_maple/pingpair_maple.pde
new file mode 100644
index 0000000..2d3925b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_maple/pingpair_maple.pde
@@ -0,0 +1,242 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example RF Radio Ping Pair ... for Maple
+ *
+ * This is an example of how to use the RF24 class.  Write this sketch to two different nodes,
+ * connect the role_pin to ground on one.  The ping node sends the current time to the pong node,
+ * which responds by sending the value back.  The ping node can then see how long the whole cycle
+ * took.
+ */
+
+#include "WProgram.h"
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+
+//
+// Maple specific setup.  Other than this section, the sketch is the same on Maple as on
+// Arduino
+//
+
+#ifdef MAPLE_IDE
+
+// External startup function
+extern void board_start(const char* program_name);
+
+// Use SPI #2.
+HardwareSPI SPI(2);
+
+#else
+#define board_startup printf
+#define toggleLED(x) (x)
+#endif
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 7 & 6
+// (This works for the Getting Started board plugged into the
+// Maple Native backwards.)
+
+RF24 radio(7,6);
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'ping' transmitter
+const int role_pin = 10;
+
+//
+// Topology
+//
+
+// Radio pipe addresses for the 2 nodes to communicate.
+const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL };
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes
+// in this system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_ping_out = 1, role_pong_back } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"};
+
+// The role of the current running sketch
+role_e role;
+
+void setup(void)
+{
+  //
+  // Role
+  //
+
+  // set up the role pin
+  pinMode(role_pin, INPUT);
+  digitalWrite(role_pin,HIGH);
+  delay(20); // Just to get a solid reading on the role pin
+
+  // read the address pin, establish our role
+  if ( digitalRead(role_pin) )
+    role = role_ping_out;
+  else
+    role = role_pong_back;
+
+  //
+  // Print preamble
+  //
+
+  board_start("\n\rRF24/examples/pingpair/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  // optionally, increase the delay between retries & # of retries
+  radio.setRetries(15,15);
+
+  // optionally, reduce the payload size.  seems to
+  // improve reliability
+  radio.setPayloadSize(8);
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens two pipes for these two nodes to communicate
+  // back and forth.
+  // Open 'our' pipe for writing
+  // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading)
+
+  if ( role == role_ping_out )
+  {
+    radio.openWritingPipe(pipes[0]);
+    radio.openReadingPipe(1,pipes[1]);
+  }
+  else
+  {
+    radio.openWritingPipe(pipes[1]);
+    radio.openReadingPipe(1,pipes[0]);
+  }
+
+  //
+  // Start listening
+  //
+
+  radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+}
+
+void loop(void)
+{
+  //
+  // Ping out role.  Repeatedly send the current time
+  //
+
+  if (role == role_ping_out)
+  {
+    toggleLED();
+
+    // First, stop listening so we can talk.
+    radio.stopListening();
+
+    // Take the time, and send it.  This will block until complete
+    unsigned long time = millis();
+    printf("Now sending %lu...",time);
+    bool ok = radio.write( &time, sizeof(unsigned long) );
+
+    if (ok)
+      printf("ok...\r\n");
+    else
+      printf("failed.\r\n");
+
+    // Now, continue listening
+    radio.startListening();
+
+    // Wait here until we get a response, or timeout (250ms)
+    unsigned long started_waiting_at = millis();
+    bool timeout = false;
+    while ( ! radio.available() && ! timeout )
+      if (millis() - started_waiting_at > 200 )
+        timeout = true;
+
+    // Describe the results
+    if ( timeout )
+    {
+      printf("Failed, response timed out.\r\n");
+    }
+    else
+    {
+      // Grab the response, compare, and send to debugging spew
+      unsigned long got_time;
+      radio.read( &got_time, sizeof(unsigned long) );
+
+      // Spew it
+      printf("Got response %lu, round-trip delay: %lu\r\n",got_time,millis()-got_time);
+    }
+
+    toggleLED();
+
+    // Try again 1s later
+    delay(1000);
+  }
+
+  //
+  // Pong back role.  Receive each packet, dump it out, and send it back
+  //
+
+  if ( role == role_pong_back )
+  {
+    // if there is data ready
+    if ( radio.available() )
+    {
+      // Dump the payloads until we've gotten everything
+      unsigned long got_time;
+      bool done = false;
+      while (!done)
+      {
+        // Fetch the payload, and see if this was the last one.
+        done = radio.read( &got_time, sizeof(unsigned long) );
+
+        // Spew it
+        printf("Got payload %lu...",got_time);
+
+        // Delay just a little bit to let the other unit
+        // make the transition to receiver
+        delay(20);
+      }
+
+      // First, stop listening so we can talk
+      radio.stopListening();
+
+      // Send the final one back.
+      radio.write( &got_time, sizeof(unsigned long) );
+      printf("Sent response.\r\n");
+
+      // Now, resume listening so we catch the next packets.
+      radio.startListening();
+    }
+  }
+}
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_pl/Jamfile b/hardware/digistump/sam/libraries/RF24/examples/pingpair_pl/Jamfile
new file mode 100644
index 0000000..901f8da
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_pl/Jamfile
@@ -0,0 +1,206 @@
+PROJECT_NAME 	= $(PWD:B) ;
+PROJECT_DIR 	= . ;
+PROJECT_LIBS = SPI RF24 ; 
+
+OUT_DIR = ojam ;
+F_CPU 		= 16000000 ;
+MCU             = atmega328p ;
+PORTS           = /dev/tty.usbserial-A600eHIs /dev/tty.usbserial-A40081RP /dev/tty.usbserial-A9007LmI ;
+
+UPLOAD_RATE 	= 57600 ;
+AVRDUDE_PROTOCOL = stk500v1 ;
+COM 		= 33 ;
+
+# Host-specific overrides for locations 
+if $(OS) = MACOSX 
+{
+ARDUINO_VERSION	= 22 ;
+OLD_DIR 	= /opt/arduino-0021 ;
+AVR_TOOLS_PATH 	= $(OLD_DIR)/hardware/tools/avr/bin ;
+AVRDUDECONFIG_PATH = $(OLD_DIR)/hardware/tools/avr/etc ;
+ARDUINO_DIR 	= /opt/Arduino ;
+ARDUINO_AVR 	= /usr/lib/avr/include ;
+}
+
+# Where is everything?
+ARDUINO_VERSION	?= 22 ;
+AVR_TOOLS_PATH 	?= /usr/bin ;
+ARDUINO_DIR 	?= /opt/arduino-00$(ARDUINO_VERSION) ;
+ARDUINO_AVR 	?= $(ARDUINO_DIR)/hardware/tools/avr/avr/include/avr ;
+AVRDUDECONFIG_PATH ?= $(ARDUINO_DIR)/hardware/tools ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/arduino ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+AVR_CC  	= $(AVR_TOOLS_PATH)/avr-gcc ;
+AVR_CXX  	= $(AVR_TOOLS_PATH)/avr-g++ ;
+AVR_LD  	= $(AVR_TOOLS_PATH)/avr-gcc ;
+AVR_OBJCOPY 	= $(AVR_TOOLS_PATH)/avr-objcopy ;
+AVRDUDE 	= $(AVR_TOOLS_PATH)/avrdude ;
+
+DEFINES  	= F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+CTUNING  	= -ffunction-sections -fdata-sections ;
+CXXTUNING  	= -fno-exceptions -fno-strict-aliasing ; 
+CFLAGS  	= -Os -Wall -Wextra -mmcu=$(MCU) $(CTUNING) ;
+CXXFLAGS  	= $(CFLAGS) $(CXXTUNING) ;
+LDFLAGS  	= -Os -lm -Wl,--gc-sections -mmcu=atmega328p ;
+
+# Search everywhere for headers
+HDRS  	 	= $(PROJECT_DIR) $(ARDUINO_AVR) $(ARDUINO_CORE) [ GLOB $(ARDUINO_LIB) $(SKETCH_LIB) : [^.]* ] ;
+
+# Grab everything from the core directory
+CORE_MODULES  	= [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+LIB_MODULES  	= [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp ] ;
+
+# In addition to explicitly-specified program modules, pick up anything from the current
+# dir.
+PROJECT_MODULES += [ GLOB $(PROJECT_DIR) : *.c *.cpp *.pde ] ;
+
+# Shortcut for the out files
+OUT             = $(OUT_DIR)/$(PROJECT_NAME) ;
+
+# AvrDude setup
+AVRDUDE_FLAGS = -V -F -D -C $(AVRDUDECONFIG_PATH)/avrdude.conf -p $(MCU) -c $(AVRDUDE_PROTOCOL) -b $(UPLOAD_RATE) ;
+
+rule GitVersion
+{
+  Always $(<) ;
+  Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+  echo "const char program_version[] = \"\\" > $(<)
+  git log -1 --pretty=format:%h >> $(<)
+  echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule AvrCc
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrCc
+{
+  $(AVR_CC) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CFLAGS) $(>) 
+}
+
+rule AvrC++
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrC++
+{
+  $(AVR_CXX) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) 
+}
+
+rule Pde
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+}
+
+actions Pde
+{
+  echo "#include " > $(<) 
+  echo "#line 1 \"$(>)\"" >> $(<)
+  cat $(>) >> $(<) 
+}
+
+rule AvrPde
+{
+  local _CPP = $(OUT_DIR)/$(_I:B).cpp ;
+  Pde $(_CPP) : $(>) ;
+  AvrC++ $(<) : $(_CPP) ;
+}
+
+rule AvrObject
+{
+  switch $(>:S)
+  {
+    case .c :   AvrCc $(<) : $(>) ;
+    case .cpp : AvrC++ $(<) : $(>) ;
+    case .pde : AvrPde $(<) : $(>) ;
+  }
+}
+
+rule AvrObjects
+{
+  for _I in $(<) 
+  {
+    AvrObject $(OUT_DIR)/$(_I:B).o : $(_I) ;
+  }
+}
+
+rule AvrMainFromObjects
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  MkDir $(<:D) ;
+  Depends all : $(<) ;
+  Clean clean : $(<) ;
+}
+
+actions AvrMainFromObjects
+{
+  $(AVR_LD) $(LDFLAGS) -o $(<) $(>) 
+}
+
+rule AvrMain
+{
+  AvrMainFromObjects $(<) : $(OUT_DIR)/$(>:B).o ;
+  AvrObjects $(>) ;
+}
+
+rule AvrHex
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Depends hex : $(<) ;
+  Clean clean : $(<) ;
+}
+
+actions AvrHex
+{
+  $(AVR_OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule AvrUpload
+{
+  Depends $(1) : $(2) ;
+  Depends $(2) : $(3) ;
+  NotFile $(1) ;
+  Always $(1) ;
+  Always $(2) ;
+  AvrUploadAction $(2) : $(3) ;
+}
+
+actions AvrUploadAction
+{
+  $(AVRDUDE) $(AVRDUDE_FLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+AvrMain $(OUT).elf : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ;
+AvrHex $(OUT).hex : $(OUT).elf ;
+
+AvrUpload p6 : /dev/tty.usbserial-A600eHIs : $(OUT).hex ;
+AvrUpload p4 : /dev/tty.usbserial-A40081RP : $(OUT).hex ;
+AvrUpload p9 : /dev/tty.usbserial-A9007LmI : $(OUT).hex ;
+
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_pl/pingpair_pl.pde b/hardware/digistump/sam/libraries/RF24/examples/pingpair_pl/pingpair_pl.pde
new file mode 100644
index 0000000..7f9afc7
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_pl/pingpair_pl.pde
@@ -0,0 +1,180 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example of using Ack Payloads
+ *
+ * This is an example of how to do two-way communication without changing
+ * transmit/receive modes.  Here, a payload is set to the transmitter within
+ * the Ack packet of each transmission.  Note that the payload is set BEFORE
+ * the sender's message arrives.
+ */
+
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+#include "printf.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 9 & 10
+
+RF24 radio(53,52);
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'ping' transmitter
+const short role_pin = 7;
+
+//
+// Topology
+//
+
+// Single radio pipe address for the 2 nodes to communicate.
+const uint64_t pipe = 0xE8E8F0F0E1LL;
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes in this
+// system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_sender = 1, role_receiver } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Sender", "Receiver"};
+
+// The role of the current running sketch
+role_e role;
+
+void setup(void)
+{
+  //
+  // Role
+  //
+
+  // set up the role pin
+  pinMode(role_pin, INPUT);
+  digitalWrite(role_pin,HIGH);
+  delay(20); // Just to get a solid reading on the role pin
+
+  // read the address pin, establish our role
+  if ( digitalRead(role_pin) )
+    role = role_sender;
+  else
+    role = role_receiver;
+
+  //
+  // Print preamble
+  //
+
+  Serial.begin(57600);
+  printf_begin();
+  printf("\n\rRF24/examples/pingpair_pl/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  // We will be using the Ack Payload feature, so please enable it
+  radio.enableAckPayload();
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens a single pipes for these two nodes to communicate
+  // back and forth.  One listens on it, the other talks to it.
+
+  if ( role == role_sender )
+  {
+    radio.openWritingPipe(pipe);
+  }
+  else
+  {
+    radio.openReadingPipe(1,pipe);
+  }
+
+  //
+  // Start listening
+  //
+
+  if ( role == role_receiver )
+    radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+}
+
+void loop(void)
+{
+  static uint32_t message_count = 0;
+
+  //
+  // Sender role.  Repeatedly send the current time
+  //
+
+  if (role == role_sender)
+  {
+    // Take the time, and send it.  This will block until complete
+    unsigned long time = millis();
+    printf("Now sending %lu...",time);
+    radio.write( &time, sizeof(unsigned long) );
+
+    if ( radio.isAckPayloadAvailable() )
+    {
+      radio.read(&message_count,sizeof(message_count));
+      printf("Ack: [%lu] ",message_count);
+    }
+    printf("OK\n\r");
+
+    // Try again soon
+    delay(2000);
+  }
+
+  //
+  // Receiver role.  Receive each packet, dump it out, add ack payload for next time
+  //
+
+  if ( role == role_receiver )
+  {
+    // if there is data ready
+    if ( radio.available() )
+    {
+      // Dump the payloads until we've gotten everything
+      static unsigned long got_time;
+      bool done = false;
+      while (!done)
+      {
+        // Fetch the payload, and see if this was the last one.
+        done = radio.read( &got_time, sizeof(unsigned long) );
+
+        // Spew it
+        printf("Got payload %lu\n",got_time);
+      }
+
+      // Add an ack packet for the next time around.  This is a simple
+      // packet counter
+      radio.writeAckPayload( 1, &message_count, sizeof(message_count) );
+      ++message_count;
+    }
+  }
+}
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_pl/printf.h b/hardware/digistump/sam/libraries/RF24/examples/pingpair_pl/printf.h
new file mode 100644
index 0000000..990d79b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_pl/printf.h
@@ -0,0 +1,39 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  #if !defined(__arm__)
+fdevopen( &serial_putc, 0 );
+#endif
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_sleepy/Jamfile b/hardware/digistump/sam/libraries/RF24/examples/pingpair_sleepy/Jamfile
new file mode 100644
index 0000000..901f8da
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_sleepy/Jamfile
@@ -0,0 +1,206 @@
+PROJECT_NAME 	= $(PWD:B) ;
+PROJECT_DIR 	= . ;
+PROJECT_LIBS = SPI RF24 ; 
+
+OUT_DIR = ojam ;
+F_CPU 		= 16000000 ;
+MCU             = atmega328p ;
+PORTS           = /dev/tty.usbserial-A600eHIs /dev/tty.usbserial-A40081RP /dev/tty.usbserial-A9007LmI ;
+
+UPLOAD_RATE 	= 57600 ;
+AVRDUDE_PROTOCOL = stk500v1 ;
+COM 		= 33 ;
+
+# Host-specific overrides for locations 
+if $(OS) = MACOSX 
+{
+ARDUINO_VERSION	= 22 ;
+OLD_DIR 	= /opt/arduino-0021 ;
+AVR_TOOLS_PATH 	= $(OLD_DIR)/hardware/tools/avr/bin ;
+AVRDUDECONFIG_PATH = $(OLD_DIR)/hardware/tools/avr/etc ;
+ARDUINO_DIR 	= /opt/Arduino ;
+ARDUINO_AVR 	= /usr/lib/avr/include ;
+}
+
+# Where is everything?
+ARDUINO_VERSION	?= 22 ;
+AVR_TOOLS_PATH 	?= /usr/bin ;
+ARDUINO_DIR 	?= /opt/arduino-00$(ARDUINO_VERSION) ;
+ARDUINO_AVR 	?= $(ARDUINO_DIR)/hardware/tools/avr/avr/include/avr ;
+AVRDUDECONFIG_PATH ?= $(ARDUINO_DIR)/hardware/tools ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/arduino ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+AVR_CC  	= $(AVR_TOOLS_PATH)/avr-gcc ;
+AVR_CXX  	= $(AVR_TOOLS_PATH)/avr-g++ ;
+AVR_LD  	= $(AVR_TOOLS_PATH)/avr-gcc ;
+AVR_OBJCOPY 	= $(AVR_TOOLS_PATH)/avr-objcopy ;
+AVRDUDE 	= $(AVR_TOOLS_PATH)/avrdude ;
+
+DEFINES  	= F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+CTUNING  	= -ffunction-sections -fdata-sections ;
+CXXTUNING  	= -fno-exceptions -fno-strict-aliasing ; 
+CFLAGS  	= -Os -Wall -Wextra -mmcu=$(MCU) $(CTUNING) ;
+CXXFLAGS  	= $(CFLAGS) $(CXXTUNING) ;
+LDFLAGS  	= -Os -lm -Wl,--gc-sections -mmcu=atmega328p ;
+
+# Search everywhere for headers
+HDRS  	 	= $(PROJECT_DIR) $(ARDUINO_AVR) $(ARDUINO_CORE) [ GLOB $(ARDUINO_LIB) $(SKETCH_LIB) : [^.]* ] ;
+
+# Grab everything from the core directory
+CORE_MODULES  	= [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+LIB_MODULES  	= [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp ] ;
+
+# In addition to explicitly-specified program modules, pick up anything from the current
+# dir.
+PROJECT_MODULES += [ GLOB $(PROJECT_DIR) : *.c *.cpp *.pde ] ;
+
+# Shortcut for the out files
+OUT             = $(OUT_DIR)/$(PROJECT_NAME) ;
+
+# AvrDude setup
+AVRDUDE_FLAGS = -V -F -D -C $(AVRDUDECONFIG_PATH)/avrdude.conf -p $(MCU) -c $(AVRDUDE_PROTOCOL) -b $(UPLOAD_RATE) ;
+
+rule GitVersion
+{
+  Always $(<) ;
+  Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+  echo "const char program_version[] = \"\\" > $(<)
+  git log -1 --pretty=format:%h >> $(<)
+  echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule AvrCc
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrCc
+{
+  $(AVR_CC) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CFLAGS) $(>) 
+}
+
+rule AvrC++
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrC++
+{
+  $(AVR_CXX) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) 
+}
+
+rule Pde
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+}
+
+actions Pde
+{
+  echo "#include " > $(<) 
+  echo "#line 1 \"$(>)\"" >> $(<)
+  cat $(>) >> $(<) 
+}
+
+rule AvrPde
+{
+  local _CPP = $(OUT_DIR)/$(_I:B).cpp ;
+  Pde $(_CPP) : $(>) ;
+  AvrC++ $(<) : $(_CPP) ;
+}
+
+rule AvrObject
+{
+  switch $(>:S)
+  {
+    case .c :   AvrCc $(<) : $(>) ;
+    case .cpp : AvrC++ $(<) : $(>) ;
+    case .pde : AvrPde $(<) : $(>) ;
+  }
+}
+
+rule AvrObjects
+{
+  for _I in $(<) 
+  {
+    AvrObject $(OUT_DIR)/$(_I:B).o : $(_I) ;
+  }
+}
+
+rule AvrMainFromObjects
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  MkDir $(<:D) ;
+  Depends all : $(<) ;
+  Clean clean : $(<) ;
+}
+
+actions AvrMainFromObjects
+{
+  $(AVR_LD) $(LDFLAGS) -o $(<) $(>) 
+}
+
+rule AvrMain
+{
+  AvrMainFromObjects $(<) : $(OUT_DIR)/$(>:B).o ;
+  AvrObjects $(>) ;
+}
+
+rule AvrHex
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Depends hex : $(<) ;
+  Clean clean : $(<) ;
+}
+
+actions AvrHex
+{
+  $(AVR_OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule AvrUpload
+{
+  Depends $(1) : $(2) ;
+  Depends $(2) : $(3) ;
+  NotFile $(1) ;
+  Always $(1) ;
+  Always $(2) ;
+  AvrUploadAction $(2) : $(3) ;
+}
+
+actions AvrUploadAction
+{
+  $(AVRDUDE) $(AVRDUDE_FLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+AvrMain $(OUT).elf : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ;
+AvrHex $(OUT).hex : $(OUT).elf ;
+
+AvrUpload p6 : /dev/tty.usbserial-A600eHIs : $(OUT).hex ;
+AvrUpload p4 : /dev/tty.usbserial-A40081RP : $(OUT).hex ;
+AvrUpload p9 : /dev/tty.usbserial-A9007LmI : $(OUT).hex ;
+
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_sleepy/pingpair_sleepy.pde b/hardware/digistump/sam/libraries/RF24/examples/pingpair_sleepy/pingpair_sleepy.pde
new file mode 100644
index 0000000..2e0214b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_sleepy/pingpair_sleepy.pde
@@ -0,0 +1,288 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example RF Radio Ping Pair which Sleeps between Sends
+ *
+ * This is an example of how to use the RF24 class to create a battery-
+ * efficient system.  It is just like the pingpair.pde example, but the
+ * ping node powers down the radio and sleeps the MCU after every
+ * ping/pong cycle.
+ *
+ * As with the pingpair.pde example, write this sketch to two different nodes,
+ * connect the role_pin to ground on one.  The ping node sends the current
+ * time to the pong node, which responds by sending the value back.  The ping
+ * node can then see how long the whole cycle took.
+ */
+
+#include 
+#include 
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+#include "printf.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 9 & 10
+
+RF24 radio(53,52);
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'ping' transmitter
+const int role_pin = 7;
+
+//
+// Topology
+//
+
+// Radio pipe addresses for the 2 nodes to communicate.
+const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL };
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes
+// in this system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_ping_out = 1, role_pong_back } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"};
+
+// The role of the current running sketch
+role_e role;
+
+//
+// Sleep declarations
+//
+
+typedef enum { wdt_16ms = 0, wdt_32ms, wdt_64ms, wdt_128ms, wdt_250ms, wdt_500ms, wdt_1s, wdt_2s, wdt_4s, wdt_8s } wdt_prescalar_e;
+
+void setup_watchdog(uint8_t prescalar);
+void do_sleep(void);
+
+const short sleep_cycles_per_transmission = 4;
+volatile short sleep_cycles_remaining = sleep_cycles_per_transmission;
+
+//
+// Normal operation
+//
+
+void setup(void)
+{
+  //
+  // Role
+  //
+
+  // set up the role pin
+  pinMode(role_pin, INPUT);
+  digitalWrite(role_pin,HIGH);
+  delay(20); // Just to get a solid reading on the role pin
+
+  // read the address pin, establish our role
+  if ( digitalRead(role_pin) )
+    role = role_ping_out;
+  else
+    role = role_pong_back;
+
+  //
+  // Print preamble
+  //
+
+  Serial.begin(57600);
+  printf_begin();
+  printf("\n\rRF24/examples/pingpair_sleepy/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+
+  //
+  // Prepare sleep parameters
+  //
+
+  // Only the ping out role sleeps.  Wake up every 4s to send a ping
+  if ( role == role_ping_out )
+    setup_watchdog(wdt_1s);
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens two pipes for these two nodes to communicate
+  // back and forth.
+  // Open 'our' pipe for writing
+  // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading)
+
+  if ( role == role_ping_out )
+  {
+    radio.openWritingPipe(pipes[0]);
+    radio.openReadingPipe(1,pipes[1]);
+  }
+  else
+  {
+    radio.openWritingPipe(pipes[1]);
+    radio.openReadingPipe(1,pipes[0]);
+  }
+
+  //
+  // Start listening
+  //
+
+  radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+}
+
+void loop(void)
+{
+  //
+  // Ping out role.  Repeatedly send the current time
+  //
+
+  if (role == role_ping_out)
+  {
+    // First, stop listening so we can talk.
+    radio.stopListening();
+
+    // Take the time, and send it.  This will block until complete
+    unsigned long time = millis();
+    printf("Now sending %lu...",time);
+    radio.write( &time, sizeof(unsigned long) );
+
+    // Now, continue listening
+    radio.startListening();
+
+    // Wait here until we get a response, or timeout (250ms)
+    unsigned long started_waiting_at = millis();
+    bool timeout = false;
+    while ( ! radio.available() && ! timeout )
+      if (millis() - started_waiting_at > 250 )
+        timeout = true;
+
+    // Describe the results
+    if ( timeout )
+    {
+      printf("Failed, response timed out.\n\r");
+    }
+    else
+    {
+      // Grab the response, compare, and send to debugging spew
+      unsigned long got_time;
+      radio.read( &got_time, sizeof(unsigned long) );
+
+      // Spew it
+      printf("Got response %lu, round-trip delay: %lu\n\r",got_time,millis()-got_time);
+    }
+
+    //
+    // Shut down the system
+    //
+
+    // Experiment with some delay here to see if it has an effect
+    delay(500);
+
+    // Power down the radio.  Note that the radio will get powered back up
+    // on the next write() call.
+    radio.powerDown();
+
+    // Sleep the MCU.  The watchdog timer will awaken in a short while, and
+    // continue execution here.
+    while( sleep_cycles_remaining )
+      do_sleep();
+
+    sleep_cycles_remaining = sleep_cycles_per_transmission;
+  }
+
+  //
+  // Pong back role.  Receive each packet, dump it out, and send it back
+  //
+  // This is untouched from the pingpair example.
+  //
+
+  if ( role == role_pong_back )
+  {
+    // if there is data ready
+    if ( radio.available() )
+    {
+      // Dump the payloads until we've gotten everything
+      unsigned long got_time;
+      bool done = false;
+      while (!done)
+      {
+        // Fetch the payload, and see if this was the last one.
+        done = radio.read( &got_time, sizeof(unsigned long) );
+
+        // Spew it.  Include our time, because the ping_out millis counter is unreliable
+        // due to it sleeping
+        printf("Got payload %lu @ %lu...",got_time,millis());
+      }
+
+      // First, stop listening so we can talk
+      radio.stopListening();
+
+      // Send the final one back.
+      radio.write( &got_time, sizeof(unsigned long) );
+      printf("Sent response.\n\r");
+
+      // Now, resume listening so we catch the next packets.
+      radio.startListening();
+    }
+  }
+}
+
+//
+// Sleep helpers
+//
+
+// 0=16ms, 1=32ms,2=64ms,3=125ms,4=250ms,5=500ms
+// 6=1 sec,7=2 sec, 8=4 sec, 9= 8sec
+
+void setup_watchdog(uint8_t prescalar)
+{
+  prescalar = min(9,prescalar);
+  uint8_t wdtcsr = prescalar & 7;
+  if ( prescalar & 8 )
+    wdtcsr |= _BV(WDP3);
+
+  MCUSR &= ~_BV(WDRF);
+  WDTCSR = _BV(WDCE) | _BV(WDE);
+  WDTCSR = _BV(WDCE) | wdtcsr | _BV(WDIE);
+}
+
+ISR(WDT_vect)
+{
+  --sleep_cycles_remaining;
+}
+
+void do_sleep(void)
+{
+  set_sleep_mode(SLEEP_MODE_PWR_DOWN); // sleep mode is set here
+  sleep_enable();
+
+  sleep_mode();                        // System sleeps here
+
+  sleep_disable();                     // System continues execution here when watchdog timed out
+}
+
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/examples/pingpair_sleepy/printf.h b/hardware/digistump/sam/libraries/RF24/examples/pingpair_sleepy/printf.h
new file mode 100644
index 0000000..990d79b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/pingpair_sleepy/printf.h
@@ -0,0 +1,39 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  #if !defined(__arm__)
+fdevopen( &serial_putc, 0 );
+#endif
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/examples/rpi_hub_arduino/printf.h b/hardware/digistump/sam/libraries/RF24/examples/rpi_hub_arduino/printf.h
new file mode 100644
index 0000000..b2efd56
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/rpi_hub_arduino/printf.h
@@ -0,0 +1,37 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  fdevopen( &serial_putc, 0 );
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/examples/rpi_hub_arduino/rpi_hub_arduino.ino b/hardware/digistump/sam/libraries/RF24/examples/rpi_hub_arduino/rpi_hub_arduino.ino
new file mode 100644
index 0000000..12c21cf
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/rpi_hub_arduino/rpi_hub_arduino.ino
@@ -0,0 +1,222 @@
+/*
+ This program sends readings from four or more sensor readings and appends
+ addr data pipes to the beginning of the payloads. 
+
+ The receiver is a RPi accepting 6 pipes and display received payload to the screen
+
+ RPi receiver will return the receive payload for sender to calculate the rtt
+ if the string compared matched
+
+ Max payload size is 32 bytes
+
+Forked RF24 at github :-
+https://github.com/stanleyseow/RF24
+
+ Date : 5/03/2013
+
+ Written by Stanley Seow
+ stanleyseow@gmai.com
+*/
+
+#include 
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+#include "printf.h"
+
+#define RF_SETUP 0x17
+
+LiquidCrystal lcd(10, 7, 3, 4, 5, 6);
+// Make way for the SPI pins
+// 10 -> LCD 4
+// 7  -> LCD 6
+// 3  -> LCD 11
+// 4  -> LCD 12
+// 5  -> LCD 13
+// 6  -> LCD 14
+
+// Set up nRF24L01 radio on SPI pin for CE, CSN
+RF24 radio(8,9);
+
+// Radio pipe addresses for the 2 nodes to communicate.
+// const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL };
+// const uint64_t pipes[2] = { 0xF0F0F0F0E2LL, 0xF0F0F0F0D2LL };
+// const uint64_t pipes[2] = { 0xF0F0F0F0E3LL, 0xF0F0F0F0D2LL };
+ const uint64_t pipes[2] = { 0xF0F0F0F0F1LL, 0xF0F0F0F0D2LL };
+// const uint64_t pipes[2] = { 0xF0F0F0F0F2LL, 0xF0F0F0F0D2LL };
+// Pipe0 is F0F0F0F0D2 ( same as reading pipe )
+
+char receivePayload[32];
+int counter=0;
+int timeoutTimer = 500;
+int loops = 0;
+
+void setup(void)
+{
+
+  // Setup LCD
+  lcd.begin(16,2);
+  lcd.clear();
+  lcd.setCursor(0,0);
+  lcd.print("Ard Remote Node 2");
+  
+  Serial.begin(57600);
+  
+  printf_begin();
+  printf("Sending nodeID & 4 sensor data\n\r");
+
+  radio.begin();
+
+  // Enable this seems to work better
+  radio.enableDynamicPayloads();
+  radio.setAutoAck(1);
+
+  // Setup default radio settings  
+  
+  radio.setDataRate(RF24_1MBPS);
+  radio.setPALevel(RF24_PA_MAX);
+  radio.setChannel(76);
+  radio.setCRCLength(RF24_CRC_16);
+  radio.setRetries(15,15);
+
+  radio.openWritingPipe(pipes[0]); 
+  radio.openReadingPipe(1,pipes[1]); 
+
+  // Send only, ignore listening mode
+  //radio.startListening();
+
+  // Dump the configuration of the rf unit for debugging
+  radio.printDetails(); 
+  delay(1000); 
+}
+
+void loop(void)
+{
+  int Data1,Data2,Data3,Data4 = 0;
+  char temp[5];
+  char nodeID[12];
+  bool timeout=0;
+  int timeout_timer = 500;
+
+  // Use the last 2 pipes address as nodeID  
+  sprintf(nodeID,"%X",pipes[0]);
+  
+  char outBuffer[31]=""; // Clear the outBuffer before every loop
+  unsigned long send_time, rtt = 0;
+    
+    // Get readings from sensors
+    Data1 = counter++;
+    Data2 = analogRead(0);
+    Data3 = analogRead(1);
+    Data4 = random(0,1000);
+    
+    if ( counter > 999 ) counter = 0;
+
+    // Append nodeID to the beginning of the payload    
+    strcat(outBuffer,nodeID);
+    strcat(outBuffer,",");
+    
+    // Convert int to strings and append with zeros if number smaller than 3 digits
+    // 000 to 999
+    
+    sprintf(temp,"%03d",Data1);  
+    strcat(outBuffer,temp);
+    
+    strcat(outBuffer,",");
+    
+    sprintf(temp,"%04d",Data2);
+    strcat(outBuffer,temp);
+    
+    strcat(outBuffer,",");
+
+    sprintf(temp,"%04d",Data3);
+    strcat(outBuffer,temp);
+   
+    strcat(outBuffer,",");
+   
+    sprintf(temp,"%03d",Data4);
+    strcat(outBuffer,temp); 
+    
+    // End string with 0
+    // strcat(outBuffer,0);
+            
+    printf("outBuffer: %s len: %d\n\r",outBuffer, strlen(outBuffer));
+    
+    //lcd.clear();
+    //lcd.setCursor(0,0);
+
+    lcd.setCursor(2,0);
+    lcd.print(outBuffer);
+
+    send_time = millis();
+    
+    // Stop listening and write to radio 
+    radio.stopListening();
+    
+    // Send to hub
+    if ( radio.write( outBuffer, strlen(outBuffer)) ) {
+       printf("Send successful\n\r"); 
+       lcd.setCursor(0,0);
+       lcd.print("1:");
+    }
+    else {
+       printf("Send failed\n\r");
+       lcd.setCursor(0,0);
+       lcd.print("0:");  
+    }
+  
+    radio.startListening();
+    delay(20);  
+
+    lcd.setCursor(0,1);
+    lcd.print("R:              ");
+  
+  while ( radio.available() && !timeout ) {
+
+         uint8_t len = radio.getDynamicPayloadSize();
+         radio.read( receivePayload, len); 
+         // receive_payload[len] = 0;
+         Serial.print("inBuffer:  ");
+         Serial.println(receivePayload);
+         
+         lcd.setCursor(2,1);
+         lcd.print(receivePayload);
+        
+         // Compare receive payload with outBuffer        
+         if ( ! strcmp(outBuffer, receivePayload) ) {
+             rtt = millis() - send_time;
+             
+             // Send beep to Pin 2
+             digitalWrite(2,HIGH);
+           
+             lcd.setCursor(0,1);
+             lcd.print("R:              ");
+             
+             lcd.setCursor(2,1);
+             lcd.print(rtt);
+             Serial.println(rtt);       
+         }       
+    
+    // Check for timeout and exit the while loop
+    if ( millis() - send_time > timeout_timer ) {
+         lcd.setCursor(2,1);
+         lcd.print("Timeout");
+         Serial.println("Timeout!!!");
+         timeout = 1;
+         loops = 0;
+     }          
+      Serial.print(loops++);
+      delay(10);
+   } // End while  
+ 
+    
+    Serial.flush();
+    delay(250);
+    digitalWrite(2,LOW);
+    
+  }
+
+
+
+
+
diff --git a/hardware/digistump/sam/libraries/RF24/examples/scanner/Jamfile b/hardware/digistump/sam/libraries/RF24/examples/scanner/Jamfile
new file mode 100644
index 0000000..1bf541e
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/scanner/Jamfile
@@ -0,0 +1,210 @@
+# (1) Project Information
+
+PROJECT_LIBS 	= SPI RF24 ; 
+
+# (2) Board Information
+
+UPLOAD_PROTOCOL ?= stk500v1 ;
+UPLOAD_SPEED 	?= 57600 ;
+MCU		?= atmega328p ;
+F_CPU 		?= 16000000 ;
+CORE		?= arduino ;
+VARIANT 	?= standard ;
+ARDUINO_VERSION	?= 100 ;
+
+# (3) USB Ports
+
+PORTS		= p4 p6 p9 u0 u1 u2 ;
+PORT_p6 	= /dev/tty.usbserial-A600eHIs ;
+PORT_p4 	= /dev/tty.usbserial-A40081RP ;
+PORT_p9		= /dev/tty.usbserial-A9007LmI ;
+PORT_u0 	= /dev/ttyUSB0 ;
+PORT_u1 	= /dev/ttyUSB1 ;
+PORT_u2 	= /dev/ttyUSB2 ;
+
+# (4) Location of AVR tools
+#
+# This configuration assumes using avr-tools that were obtained separate from the Arduino
+# distribution. 
+
+if $(OS) = MACOSX 
+{
+	AVR_BIN 	= /usr/local/avrtools/bin ;
+	AVR_ETC 	= /usr/local/avrtools/etc ;
+	AVR_INCLUDE	= /usr/local/avrtools/include ; 
+}
+else
+{
+	AVR_BIN 	= /usr/bin ;
+	AVR_INCLUDE 	= /usr/lib/avr/include ;
+	AVR_ETC 	= /etc ; 
+}
+
+# (5) Directories where Arduino core and libraries are located
+
+ARDUINO_DIR 	?= /opt/Arduino ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+
+#
+# --------------------------------------------------
+# Below this line usually never needs to be modified 
+#
+
+# Tool locations
+
+CC	  	= $(AVR_BIN)/avr-gcc ;
+C++	 	= $(AVR_BIN)/avr-g++ ;
+LINK	  	= $(AVR_BIN)/avr-gcc ;
+OBJCOPY 	= $(AVR_BIN)/avr-objcopy ;
+AVRDUDE 	= $(AVR_BIN)/avrdude ;
+
+# Flags
+
+DEFINES  	+= F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+OPTIM		= -Os ;
+CCFLAGS  	= -Wall -Wextra -mmcu=$(MCU) -ffunction-sections -fdata-sections ;
+C++FLAGS  	= $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ;
+LINKFLAGS  	= $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ;
+AVRDUDEFLAGS	= -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ;
+
+# Search everywhere for headers
+
+HDRS  	 	= $(PWD) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ;
+
+# Output locations
+
+LOCATE_TARGET	= $(F_CPU) ;
+LOCATE_SOURCE	= $(F_CPU) ;
+
+#
+# Custom rules
+#
+
+rule GitVersion
+{
+	Always $(<) ;
+	Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+	echo "const char program_version[] = \"\\" > $(<)
+	git log -1 --pretty=format:%h >> $(<)
+	echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule Pde
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+if ( $(ARDUINO_VERSION) < 100 )
+{
+	ARDUINO_H = WProgram.h ;
+}
+else
+{
+	ARDUINO_H = Arduino.h ;
+}
+
+actions Pde
+{
+	echo "#include <$(ARDUINO_H)>" > $(<) 
+	echo "#line 1 \"$(>)\"" >> $(<)
+	cat $(>) >> $(<) 
+}
+
+rule C++Pde
+{
+	local _CPP = $(>:B).cpp ;
+	Pde $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule UserObject
+{
+	switch $(>:S)
+	{
+		case .ino : C++Pde $(<) : $(>) ;
+		case .pde : C++Pde $(<) : $(>) ;
+	}
+}
+
+rule Objects
+{
+        local _i ;
+
+        for _i in [ FGristFiles $(<) ]
+        {
+		local _b = $(_i:B)$(SUFOBJ) ;
+		local _o = $(_b:G=$(SOURCE_GRIST:E)) ;
+                Object $(_o) : $(_i) ;
+                Depends obj : $(_o) ;
+        }
+}
+
+rule Main
+{
+        MainFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+        Objects $(>) ;
+}
+
+rule Hex
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends hex : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Hex
+{
+	$(OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule Upload
+{
+	Depends $(1) : $(2) ;
+	Depends $(2) : $(3) ;
+	NotFile $(1) ;
+	Always $(1) ;
+	Always $(2) ;
+	UploadAction $(2) : $(3) ;
+}
+
+actions UploadAction
+{
+	$(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+#
+# Targets
+#
+
+# Grab everything from the core directory
+CORE_MODULES  	= [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+LIB_MODULES  	= [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ;
+
+# Grab everything from the current dir
+PROJECT_MODULES += [ GLOB $(PWD) : *.c *.cpp *.pde *.ino ] ;
+
+# Main output executable
+MAIN		= $(PWD:B).elf ;
+
+Main $(MAIN) : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ;
+Hex $(MAIN:B).hex : $(MAIN) ;
+
+# Upload targets
+for _p in $(PORTS)
+{
+	Upload $(_p) : $(PORT_$(_p)) : $(MAIN:B).hex ;
+}
diff --git a/hardware/digistump/sam/libraries/RF24/examples/scanner/printf.h b/hardware/digistump/sam/libraries/RF24/examples/scanner/printf.h
new file mode 100644
index 0000000..990d79b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/scanner/printf.h
@@ -0,0 +1,39 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  #if !defined(__arm__)
+fdevopen( &serial_putc, 0 );
+#endif
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/examples/scanner/scanner.pde b/hardware/digistump/sam/libraries/RF24/examples/scanner/scanner.pde
new file mode 100644
index 0000000..0d75f0f
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/scanner/scanner.pde
@@ -0,0 +1,124 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Channel scanner
+ *
+ * Example to detect interference on the various channels available.
+ * This is a good diagnostic tool to check whether you're picking a
+ * good channel for your application.
+ *
+ * Inspired by cpixip.
+ * See http://arduino.cc/forum/index.php/topic,54795.0.html
+ */
+
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+#include "printf.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 9 & 10
+
+RF24 radio(53,52);
+
+//
+// Channel info
+//
+
+const uint8_t num_channels = 128;
+uint8_t values[num_channels];
+
+//
+// Setup
+//
+
+void setup(void)
+{
+  //
+  // Print preamble
+  //
+
+  Serial.begin(57600);
+  printf_begin();
+  printf("\n\rRF24/examples/scanner/\n\r");
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+  radio.setAutoAck(false);
+
+  // Get into standby mode
+  radio.startListening();
+  radio.stopListening();
+
+  // Print out header, high then low digit
+  int i = 0;
+  while ( i < num_channels )
+  {
+    printf("%x",i>>4);
+    ++i;
+  }
+  printf("\n\r");
+  i = 0;
+  while ( i < num_channels )
+  {
+    printf("%x",i&0xf);
+    ++i;
+  }
+  printf("\n\r");
+}
+
+//
+// Loop
+//
+
+const int num_reps = 100;
+
+void loop(void)
+{
+  // Clear measurement values
+  memset(values,0,sizeof(values));
+
+  // Scan all channels num_reps times
+  int rep_counter = num_reps;
+  while (rep_counter--)
+  {
+    int i = num_channels;
+    while (i--)
+    {
+      // Select this channel
+      radio.setChannel(i);
+
+      // Listen for a little
+      radio.startListening();
+      delayMicroseconds(128);
+      radio.stopListening();
+
+      // Did we get a carrier?
+      if ( radio.testCarrier() )
+        ++values[i];
+    }
+  }
+
+  // Print out channel measurements, clamped to a single hex digit
+  int i = 0;
+  while ( i < num_channels )
+  {
+    printf("%x",min(0xf,values[i]&0xf));
+    ++i;
+  }
+  printf("\n\r");
+}
+
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/examples/starping/Jamfile b/hardware/digistump/sam/libraries/RF24/examples/starping/Jamfile
new file mode 100644
index 0000000..de9b1f6
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/starping/Jamfile
@@ -0,0 +1,206 @@
+PROJECT_NAME 	= $(PWD:B) ;
+PROJECT_DIR 	= . ;
+PROJECT_LIBS    = EEPROM SPI RF24 ; 
+
+OUT_DIR = ojam ;
+F_CPU 		= 16000000 ;
+MCU             = atmega328p ;
+PORTS           = /dev/tty.usbserial-A600eHIs /dev/tty.usbserial-A40081RP /dev/tty.usbserial-A9007LmI ;
+
+UPLOAD_RATE 	= 57600 ;
+AVRDUDE_PROTOCOL = stk500v1 ;
+COM 		= 33 ;
+
+# Host-specific overrides for locations 
+if $(OS) = MACOSX 
+{
+ARDUINO_VERSION	= 22 ;
+OLD_DIR 	= /opt/arduino-0021 ;
+AVR_TOOLS_PATH 	= $(OLD_DIR)/hardware/tools/avr/bin ;
+AVRDUDECONFIG_PATH = $(OLD_DIR)/hardware/tools/avr/etc ;
+ARDUINO_DIR 	= /opt/Arduino ;
+ARDUINO_AVR 	= /usr/lib/avr/include ;
+}
+
+# Where is everything?
+ARDUINO_VERSION	?= 22 ;
+AVR_TOOLS_PATH 	?= /usr/bin ;
+ARDUINO_DIR 	?= /opt/arduino-00$(ARDUINO_VERSION) ;
+ARDUINO_AVR 	?= $(ARDUINO_DIR)/hardware/tools/avr/avr/include/avr ;
+AVRDUDECONFIG_PATH ?= $(ARDUINO_DIR)/hardware/tools ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/arduino ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+AVR_CC  	= $(AVR_TOOLS_PATH)/avr-gcc ;
+AVR_CXX  	= $(AVR_TOOLS_PATH)/avr-g++ ;
+AVR_LD  	= $(AVR_TOOLS_PATH)/avr-gcc ;
+AVR_OBJCOPY 	= $(AVR_TOOLS_PATH)/avr-objcopy ;
+AVRDUDE 	= $(AVR_TOOLS_PATH)/avrdude ;
+
+DEFINES  	= F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+CTUNING  	= -ffunction-sections -fdata-sections ;
+CXXTUNING  	= -fno-exceptions -fno-strict-aliasing ; 
+CFLAGS  	= -Os -Wall -Wextra -mmcu=$(MCU) $(CTUNING) ;
+CXXFLAGS  	= $(CFLAGS) $(CXXTUNING) ;
+LDFLAGS  	= -Os -lm -Wl,--gc-sections -mmcu=atmega328p ;
+
+# Search everywhere for headers
+HDRS  	 	= $(PROJECT_DIR) $(ARDUINO_AVR) $(ARDUINO_CORE) [ GLOB $(ARDUINO_LIB) $(SKETCH_LIB) : [^.]* ] ;
+
+# Grab everything from the core directory
+CORE_MODULES  	= [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+LIB_MODULES  	= [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp ] ;
+
+# In addition to explicitly-specified program modules, pick up anything from the current
+# dir.
+PROJECT_MODULES += [ GLOB $(PROJECT_DIR) : *.c *.cpp *.pde ] ;
+
+# Shortcut for the out files
+OUT             = $(OUT_DIR)/$(PROJECT_NAME) ;
+
+# AvrDude setup
+AVRDUDE_FLAGS = -V -F -D -C $(AVRDUDECONFIG_PATH)/avrdude.conf -p $(MCU) -c $(AVRDUDE_PROTOCOL) -b $(UPLOAD_RATE) ;
+
+rule GitVersion
+{
+  Always $(<) ;
+  Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+  echo "const char program_version[] = \"\\" > $(<)
+  git log -1 --pretty=format:%h >> $(<)
+  echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule AvrCc
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrCc
+{
+  $(AVR_CC) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CFLAGS) $(>) 
+}
+
+rule AvrC++
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrC++
+{
+  $(AVR_CXX) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) 
+}
+
+rule Pde
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+}
+
+actions Pde
+{
+  echo "#include " > $(<) 
+  echo "#line 1 \"$(>)\"" >> $(<)
+  cat $(>) >> $(<) 
+}
+
+rule AvrPde
+{
+  local _CPP = $(OUT_DIR)/$(_I:B).cpp ;
+  Pde $(_CPP) : $(>) ;
+  AvrC++ $(<) : $(_CPP) ;
+}
+
+rule AvrObject
+{
+  switch $(>:S)
+  {
+    case .c :   AvrCc $(<) : $(>) ;
+    case .cpp : AvrC++ $(<) : $(>) ;
+    case .pde : AvrPde $(<) : $(>) ;
+  }
+}
+
+rule AvrObjects
+{
+  for _I in $(<) 
+  {
+    AvrObject $(OUT_DIR)/$(_I:B).o : $(_I) ;
+  }
+}
+
+rule AvrMainFromObjects
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  MkDir $(<:D) ;
+  Depends all : $(<) ;
+  Clean clean : $(<) ;
+}
+
+actions AvrMainFromObjects
+{
+  $(AVR_LD) $(LDFLAGS) -o $(<) $(>) 
+}
+
+rule AvrMain
+{
+  AvrMainFromObjects $(<) : $(OUT_DIR)/$(>:B).o ;
+  AvrObjects $(>) ;
+}
+
+rule AvrHex
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Depends hex : $(<) ;
+  Clean clean : $(<) ;
+}
+
+actions AvrHex
+{
+  $(AVR_OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule AvrUpload
+{
+  Depends $(1) : $(2) ;
+  Depends $(2) : $(3) ;
+  NotFile $(1) ;
+  Always $(1) ;
+  Always $(2) ;
+  AvrUploadAction $(2) : $(3) ;
+}
+
+actions AvrUploadAction
+{
+  $(AVRDUDE) $(AVRDUDE_FLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+AvrMain $(OUT).elf : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ;
+AvrHex $(OUT).hex : $(OUT).elf ;
+
+AvrUpload p6 : /dev/tty.usbserial-A600eHIs : $(OUT).hex ;
+AvrUpload p4 : /dev/tty.usbserial-A40081RP : $(OUT).hex ;
+AvrUpload p9 : /dev/tty.usbserial-A9007LmI : $(OUT).hex ;
+
diff --git a/hardware/digistump/sam/libraries/RF24/examples/starping/printf.h b/hardware/digistump/sam/libraries/RF24/examples/starping/printf.h
new file mode 100644
index 0000000..990d79b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/starping/printf.h
@@ -0,0 +1,39 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  #if !defined(__arm__)
+fdevopen( &serial_putc, 0 );
+#endif
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/examples/starping/starping.pde b/hardware/digistump/sam/libraries/RF24/examples/starping/starping.pde
new file mode 100644
index 0000000..dce355e
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/examples/starping/starping.pde
@@ -0,0 +1,293 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example RF Radio Ping Star Group
+ *
+ * This sketch is a more complex example of using the RF24 library for Arduino.
+ * Deploy this on up to six nodes.  Set one as the 'pong receiver' by tying the
+ * role_pin low, and the others will be 'ping transmit' units.  The ping units
+ * unit will send out the value of millis() once a second.  The pong unit will
+ * respond back with a copy of the value.  Each ping unit can get that response
+ * back, and determine how long the whole cycle took.
+ *
+ * This example requires a bit more complexity to determine which unit is which.
+ * The pong receiver is identified by having its role_pin tied to ground.
+ * The ping senders are further differentiated by a byte in eeprom.
+ */
+
+#include 
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+#include "printf.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 9 & 10
+
+RF24 radio(53,52);
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'pong' receiver.
+const int role_pin = 7;
+
+//
+// Topology
+//
+
+// Radio pipe addresses for the nodes to communicate.  Only ping nodes need
+// dedicated pipes in this topology.  Each ping node has a talking pipe
+// that it will ping into, and a listening pipe that it will listen for
+// the pong.  The pong node listens on all the ping node talking pipes
+// and sends the pong back on the sending node's specific listening pipe.
+
+const uint64_t talking_pipes[5] = { 0xF0F0F0F0D2LL, 0xF0F0F0F0C3LL, 0xF0F0F0F0B4LL, 0xF0F0F0F0A5LL, 0xF0F0F0F096LL };
+const uint64_t listening_pipes[5] = { 0x3A3A3A3AD2LL, 0x3A3A3A3AC3LL, 0x3A3A3A3AB4LL, 0x3A3A3A3AA5LL, 0x3A3A3A3A96LL };
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes
+// in this system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_invalid = 0, role_ping_out, role_pong_back } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"};
+
+// The role of the current running sketch
+role_e role;
+
+//
+// Address management
+//
+
+// Where in EEPROM is the address stored?
+const uint8_t address_at_eeprom_location = 0;
+
+// What is our address (SRAM cache of the address from EEPROM)
+// Note that zero is an INVALID address.  The pong back unit takes address
+// 1, and the rest are 2-6
+uint8_t node_address;
+
+void setup(void)
+{
+  //
+  // Role
+  //
+
+  // set up the role pin
+  pinMode(role_pin, INPUT);
+  digitalWrite(role_pin,HIGH);
+  delay(20); // Just to get a solid reading on the role pin
+
+  // read the address pin, establish our role
+  if ( digitalRead(role_pin) )
+    role = role_ping_out;
+  else
+    role = role_pong_back;
+
+  //
+  // Address
+  //
+
+  if ( role == role_pong_back )
+    node_address = 1;
+  else
+  {
+    // Read the address from EEPROM
+    uint8_t reading = EEPROM.read(address_at_eeprom_location);
+
+    // If it is in a valid range for node addresses, it is our
+    // address.
+    if ( reading >= 2 && reading <= 6 )
+      node_address = reading;
+
+    // Otherwise, it is invalid, so set our address AND ROLE to 'invalid'
+    else
+    {
+      node_address = 0;
+      role = role_invalid;
+    }
+  }
+
+  //
+  // Print preamble
+  //
+
+  Serial.begin(57600);
+  printf_begin();
+  printf("\n\rRF24/examples/starping/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+  printf("ADDRESS: %i\n\r",node_address);
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // The pong node listens on all the ping node talking pipes
+  // and sends the pong back on the sending node's specific listening pipe.
+  if ( role == role_pong_back )
+  {
+    radio.openReadingPipe(1,talking_pipes[0]);
+    radio.openReadingPipe(2,talking_pipes[1]);
+    radio.openReadingPipe(3,talking_pipes[2]);
+    radio.openReadingPipe(4,talking_pipes[3]);
+    radio.openReadingPipe(5,talking_pipes[4]);
+  }
+
+  // Each ping node has a talking pipe that it will ping into, and a listening
+  // pipe that it will listen for the pong.
+  if ( role == role_ping_out )
+  {
+    // Write on our talking pipe
+    radio.openWritingPipe(talking_pipes[node_address-2]);
+    // Listen on our listening pipe
+    radio.openReadingPipe(1,listening_pipes[node_address-2]);
+  }
+
+  //
+  // Start listening
+  //
+
+  radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+
+  //
+  // Prompt the user to assign a node address if we don't have one
+  //
+
+  if ( role == role_invalid )
+  {
+    printf("\n\r*** NO NODE ADDRESS ASSIGNED *** Send 1 through 6 to assign an address\n\r");
+  }
+}
+
+void loop(void)
+{
+  //
+  // Ping out role.  Repeatedly send the current time
+  //
+
+  if (role == role_ping_out)
+  {
+    // First, stop listening so we can talk.
+    radio.stopListening();
+
+    // Take the time, and send it.  This will block until complete
+    unsigned long time = millis();
+    printf("Now sending %lu...",time);
+    radio.write( &time, sizeof(unsigned long) );
+
+    // Now, continue listening
+    radio.startListening();
+
+    // Wait here until we get a response, or timeout (250ms)
+    unsigned long started_waiting_at = millis();
+    bool timeout = false;
+    while ( ! radio.available() && ! timeout )
+      if (millis() - started_waiting_at > 250 )
+        timeout = true;
+
+    // Describe the results
+    if ( timeout )
+    {
+      printf("Failed, response timed out.\n\r");
+    }
+    else
+    {
+      // Grab the response, compare, and send to debugging spew
+      unsigned long got_time;
+      radio.read( &got_time, sizeof(unsigned long) );
+
+      // Spew it
+      printf("Got response %lu, round-trip delay: %lu\n\r",got_time,millis()-got_time);
+    }
+
+    // Try again 1s later
+    delay(1000);
+  }
+
+  //
+  // Pong back role.  Receive each packet, dump it out, and send it back
+  //
+
+  if ( role == role_pong_back )
+  {
+    // if there is data ready
+    uint8_t pipe_num;
+    if ( radio.available(&pipe_num) )
+    {
+      // Dump the payloads until we've gotten everything
+      unsigned long got_time;
+      bool done = false;
+      while (!done)
+      {
+        // Fetch the payload, and see if this was the last one.
+        done = radio.read( &got_time, sizeof(unsigned long) );
+
+        // Spew it
+        printf("Got payload %lu from node %i...",got_time,pipe_num+1);
+      }
+
+      // First, stop listening so we can talk
+      radio.stopListening();
+
+      // Open the correct pipe for writing
+      radio.openWritingPipe(listening_pipes[pipe_num-1]);
+
+      // Retain the low 2 bytes to identify the pipe for the spew
+      uint16_t pipe_id = listening_pipes[pipe_num-1] & 0xffff;
+
+      // Send the final one back.
+      radio.write( &got_time, sizeof(unsigned long) );
+      printf("Sent response to %04x.\n\r",pipe_id);
+
+      // Now, resume listening so we catch the next packets.
+      radio.startListening();
+    }
+  }
+
+  //
+  // Listen for serial input, which is how we set the address
+  //
+  if (Serial.available())
+  {
+    // If the character on serial input is in a valid range...
+    char c = Serial.read();
+    if ( c >= '1' && c <= '6' )
+    {
+      // It is our address
+      EEPROM.write(address_at_eeprom_location,c-'0');
+
+      // And we are done right now (no easy way to soft reset)
+      printf("\n\rManually reset address to: %c\n\rPress RESET to continue!",c);
+      while(1) ;
+    }
+  }
+}
+// vim:ai:ci sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/keywords.txt b/hardware/digistump/sam/libraries/RF24/keywords.txt
new file mode 100644
index 0000000..d0bd557
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/keywords.txt
@@ -0,0 +1,13 @@
+  RF24 KEYWORD1
+  begin KEYWORD2
+  setChannel KEYWORD2
+  setPayloadSize KEYWORD2
+  getPayloadSize KEYWORD2
+  print_details KEYWORD2
+  startListening KEYWORD2
+  stopListening KEYWORD2
+  write KEYWORD2
+  available KEYWORD2
+  read KEYWORD2
+  openWritingPipe KEYWORD2
+  openReadingPipe KEYWORD2
\ No newline at end of file
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/Makefile b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/Makefile
new file mode 100644
index 0000000..c2ae37d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/Makefile
@@ -0,0 +1,55 @@
+#############################################################################
+#
+# Makefile for librf24-bcm on Raspberry Pi
+#
+# License: GPL (General Public License)
+# Author:  Charles-Henri Hallard 
+# Date:    2013/03/13 
+#
+# Description:
+# ------------
+# use make all and mak install to install the library 
+# You can change the install directory by editing the LIBDIR line
+#
+PREFIX=/usr/local
+
+# Library parameters
+# where to put the lib
+LIBDIR=$(PREFIX)/lib
+# lib name 
+LIB=librf24-bcm
+# shared library name
+LIBNAME=$(LIB).so.1.0
+
+
+# The recommended compiler flags for the Raspberry Pi
+CCFLAGS=-Ofast -mfpu=vfp -mfloat-abi=hard -march=armv6zk -mtune=arm1176jzf-s
+
+# make all
+# reinstall the library after each recompilation
+all: librf24-bcm install
+
+# Make the library
+librf24-bcm: RF24.o bcm2835.o 
+	g++ -shared -Wl,-soname,$@.so.1 ${CCFLAGS} -o ${LIBNAME} $^
+	
+# Library parts
+RF24.o: RF24.cpp
+	g++ -Wall -fPIC ${CCFLAGS} -c $^
+
+bcm2835.o: bcm2835.c
+	gcc -Wall -fPIC ${CCFLAGS} -c $^
+
+# clear build files
+clean:
+	rm -rf *.o ${LIB}.*
+
+# Install the library to LIBPATH
+install: 
+	@echo "[Install]"
+	@if ( test ! -d $(PREFIX)/lib ) ; then mkdir -p $(PREFIX)/lib ; fi
+	#@install -m 0755 ${LIB}.a ${LIBDIR}
+	@install -m 0755 ${LIBNAME} ${LIBDIR}
+	@ln -sf ${LIBDIR}/${LIBNAME} ${LIBDIR}/${LIB}.so.1
+	@ln -sf ${LIBDIR}/${LIBNAME} ${LIBDIR}/${LIB}.so
+	@ldconfig
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/RF24.cpp b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/RF24.cpp
new file mode 100644
index 0000000..63a57b5
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/RF24.cpp
@@ -0,0 +1,1088 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ 
+ 
+ 
+03/17/2013 : Charles-Henri Hallard (http://hallard.me)
+             Modified to use with Arduipi board http://hallard.me/arduipi
+						 Changed to use modified bcm2835 library 
+
+*/
+
+#include "./RF24_config.h"
+#include "./RF24.h"
+#include "./nRF24L01.h"
+
+// Used for debug with my logic analyzer
+//#include 
+//#define GPIO_CTRL_PIN   RPI_V2_GPIO_P1_07
+//#define ctrl_pin(x)	    bcm2835_gpio_write(GPIO_CTRL_PIN, x)
+
+
+/****************************************************************************/
+uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
+{
+  uint8_t status;
+	uint8_t * prx = spi_rxbuff;
+	uint8_t * ptx = spi_txbuff;
+  uint8_t size = len + 1; // Add register value to transmit buffer
+
+	*ptx++ = ( R_REGISTER | ( REGISTER_MASK & reg ) );
+	while (len--)
+		*ptx++ = NOP ; // Dummy operation, just for reading
+	
+  bcm2835_spi_transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, size);
+
+	status = *prx++; // status is 1st byte of receive buffer
+
+	// decrement before to skip status byte
+	while ( --size )
+		*buf++ = *prx++;
+
+  return status;
+}
+
+/****************************************************************************/
+uint8_t RF24::read_register(uint8_t reg)
+{
+  uint8_t result;
+	uint8_t * prx = spi_rxbuff;
+	uint8_t * ptx = spi_txbuff;
+
+	*ptx++ = ( R_REGISTER | ( REGISTER_MASK & reg ) );
+	*ptx = NOP ; // Dummy operation, just for reading
+	
+  bcm2835_spi_transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, 2);
+
+	result = *++prx;   // result is 2nd byte of receive buffer
+
+  return result;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::write_register(uint8_t reg, uint8_t value)
+{
+  uint8_t status;
+	uint8_t * prx = spi_rxbuff;
+	uint8_t * ptx = spi_txbuff;
+
+	*ptx++ = ( W_REGISTER | ( REGISTER_MASK & reg ) );
+	*ptx = value ;
+	
+  bcm2835_spi_transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, 2);
+	
+	status = *prx++; // status is 1st byte of receive buffer
+
+  if (debug) 
+		printf("write_register(%02x,%02x)\r\n",reg,value);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
+{
+  uint8_t status;
+	uint8_t * prx = spi_rxbuff;
+	uint8_t * ptx = spi_txbuff;
+  uint8_t size = len + 1; // Add register value to transmit buffer
+	
+	*ptx++ = ( W_REGISTER | ( REGISTER_MASK & reg ) );
+  while ( len-- )
+    *ptx++ = *buf++;
+
+  bcm2835_spi_transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, size);
+
+	status = *prx; // status is 1st byte of receive buffer
+	
+  return status;
+}
+
+
+/****************************************************************************/
+
+uint8_t RF24::write_payload(const void* buf, uint8_t len)
+{
+  uint8_t status;
+	uint8_t * prx = spi_rxbuff;
+	uint8_t * ptx = spi_txbuff;
+  uint8_t size ; 
+	
+  const uint8_t* current = reinterpret_cast(buf);
+
+  uint8_t data_len = min(len,payload_size);
+  uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
+	
+	size = data_len + blank_len + 1 ; // Add register value to transmit buffer
+  
+  if (debug)
+		printf("[Writing %u bytes %u blanks]",data_len,blank_len);
+
+	*ptx++ =  W_TX_PAYLOAD;
+  while ( data_len-- )
+    *ptx++ =  *current++;
+  while ( blank_len-- )
+		*ptx++ =  0; 
+
+	bcm2835_spi_transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, size);
+
+	status = *prx; // status is 1st byte of receive buffer
+
+		
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::read_payload(void* buf, uint8_t len)
+{
+  uint8_t status;
+	uint8_t * prx = spi_rxbuff;
+	uint8_t * ptx = spi_txbuff;
+  uint8_t size ; 
+	
+  uint8_t* current = reinterpret_cast(buf);
+
+  uint8_t data_len = min(len,payload_size);
+  uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
+	
+	size = data_len + blank_len + 1; // Add register value to transmit buffer
+  
+  if (debug)
+		printf("[Reading %u bytes %u blanks]",data_len,blank_len);
+  
+	*ptx++ =  R_RX_PAYLOAD;
+	while(size--)
+		*ptx++ = NOP;
+		
+	// Size has been lost during while, re affect
+	size = data_len + blank_len + 1; // Add register value to transmit buffer
+	
+	bcm2835_spi_transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, size);
+	
+	// 1st byte is status
+	status = *prx++;
+	
+	// Decrement before to skip 1st status byte
+  while ( --size )
+    *current++ = *prx++;
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::flush_rx(void)
+{
+  uint8_t status;
+
+  status = bcm2835_spi_transfer( FLUSH_RX );
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::flush_tx(void)
+{
+  uint8_t status;
+
+  status = bcm2835_spi_transfer( FLUSH_TX );
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::get_status(void)
+{
+  uint8_t status;
+
+  status = bcm2835_spi_transfer( NOP );
+
+  return status;
+}
+
+/****************************************************************************/
+
+void RF24::print_status(uint8_t status)
+{
+  printf("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n",
+           status,
+           (status & _BV(RX_DR))?1:0,
+           (status & _BV(TX_DS))?1:0,
+           (status & _BV(MAX_RT))?1:0,
+           ((status >> RX_P_NO) & 0b111),
+           (status & _BV(TX_FULL))?1:0
+          );
+}
+
+/****************************************************************************/
+
+void RF24::print_observe_tx(uint8_t value)
+{
+  printf("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n",
+           value,
+           (value >> PLOS_CNT) & 0b1111,
+           (value >> ARC_CNT) & 0b1111
+          );
+}
+
+/****************************************************************************/
+
+void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty)
+{
+  char extra_tab = strlen(name) < 8 ? '\t' : 0;
+  printf("%s\t%c =", name, extra_tab);
+  while (qty--)
+    printf(" 0x%02x",read_register(reg++));
+  printf("\n");
+}
+
+/****************************************************************************/
+
+void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
+{
+  char extra_tab = strlen(name) < 8 ? '\t' : 0;
+  printf("%s\t%c =",name,extra_tab);
+
+  while (qty--)
+  {
+    uint8_t buffer[5];
+    read_register(reg++,buffer,sizeof buffer);
+
+    printf(" 0x");
+    uint8_t* bufptr = buffer + sizeof buffer;
+    while( --bufptr >= buffer )
+      printf("%02x",*bufptr);
+  }
+
+  printf("\r\n");
+}
+
+
+/****************************************************************************/
+
+RF24::RF24(uint8_t _cepin, uint8_t _cspin, uint32_t _spi_speed):
+  ce_pin(_cepin), csn_pin(_cspin), spi_speed(_spi_speed), wide_band(true), p_variant(false), 
+  payload_size(32), ack_payload_available(false), dynamic_payloads_enabled(false),
+  pipe0_reading_address(0)
+{
+}
+
+/****************************************************************************/
+
+void RF24::setChannel(uint8_t channel)
+{
+  // TODO: This method could take advantage of the 'wide_band' calculation
+  // done in setChannel() to require certain channel spacing.
+
+  const uint8_t max_channel = 127;
+  write_register(RF_CH,min(channel,max_channel));
+}
+
+/****************************************************************************/
+
+void RF24::setPayloadSize(uint8_t size)
+{
+  const uint8_t max_payload_size = 32;
+  payload_size = min(size,max_payload_size);
+}
+
+/****************************************************************************/
+
+uint8_t RF24::getPayloadSize(void)
+{
+  return payload_size;
+}
+
+/****************************************************************************/
+
+static const char rf24_datarate_e_str_0[] = "1MBPS";
+static const char rf24_datarate_e_str_1[] = "2MBPS";
+static const char rf24_datarate_e_str_2[] = "250KBPS";
+static const char * const rf24_datarate_e_str_P[] = {
+  rf24_datarate_e_str_0,
+  rf24_datarate_e_str_1,
+  rf24_datarate_e_str_2,
+};
+static const char rf24_model_e_str_0[] = "nRF24L01";
+static const char rf24_model_e_str_1[] = "nRF24L01+";
+static const char * const rf24_model_e_str_P[] = {
+  rf24_model_e_str_0,
+  rf24_model_e_str_1,
+};
+static const char rf24_crclength_e_str_0[] = "Disabled";
+static const char rf24_crclength_e_str_1[] = "8 bits";
+static const char rf24_crclength_e_str_2[] = "16 bits" ;
+static const char * const rf24_crclength_e_str_P[]  = {
+  rf24_crclength_e_str_0,
+  rf24_crclength_e_str_1,
+  rf24_crclength_e_str_2,
+};
+static const char rf24_pa_dbm_e_str_0[] = "PA_MIN";
+static const char rf24_pa_dbm_e_str_1[] = "PA_LOW";
+static const char rf24_pa_dbm_e_str_2[] = "PA_HIGH";
+static const char rf24_pa_dbm_e_str_3[] = "PA_MAX";
+static const char * const rf24_pa_dbm_e_str_P[] = { 
+  rf24_pa_dbm_e_str_0,
+  rf24_pa_dbm_e_str_1,
+  rf24_pa_dbm_e_str_2,
+  rf24_pa_dbm_e_str_3,
+};
+
+static const char rf24_csn_e_str_0[] = "CE0 (PI Hardware Driven)";
+static const char rf24_csn_e_str_1[] = "CE1 (PI Hardware Driven)";
+static const char rf24_csn_e_str_2[] = "CE2 (PI Hardware Driven)";
+static const char rf24_csn_e_str_3[] = "Custom GPIO Software Driven";
+static const char * const rf24_csn_e_str_P[] = { 
+  rf24_csn_e_str_0,
+  rf24_csn_e_str_1,
+  rf24_csn_e_str_2,
+  rf24_csn_e_str_3,
+};
+
+// Display NRF24L01 details
+void RF24::printDetails(void)
+{
+	printf("================ SPI Configuration ================\n" );
+
+	if (csn_pin < BCM2835_SPI_CS_NONE )
+	{
+		printf("CSN Pin  \t = %s\n",rf24_csn_e_str_P[csn_pin]);
+	}
+	else
+	{	
+		printf("CSN Pin  \t = Custom GPIO%d%s\n", csn_pin, 
+			csn_pin==RPI_V2_GPIO_P1_26 ? " (CE1) Software Driven" : "" );
+	}
+	
+  printf("CE Pin  \t = Custom GPIO%d\n", ce_pin );
+	
+	// SPI Bus Speed
+	printf("Clock Speed\t = " );
+	switch (spi_speed)
+	{
+		case BCM2835_SPI_SPEED_64MHZ : printf("64 Mhz");	break ;
+		case BCM2835_SPI_SPEED_32MHZ : printf("32 Mhz");	break ;
+		case BCM2835_SPI_SPEED_16MHZ : printf("16 Mhz");	break ;
+		case BCM2835_SPI_SPEED_8MHZ  : printf("8 Mhz");	break ;
+		case BCM2835_SPI_SPEED_4MHZ  : printf("4 Mhz");	break ;
+		case BCM2835_SPI_SPEED_2MHZ  : printf("2 Mhz");	break ;
+		case BCM2835_SPI_SPEED_1MHZ  : printf("1 Mhz");	break ;
+		case BCM2835_SPI_SPEED_512KHZ: printf("512 KHz");	break ;
+		case BCM2835_SPI_SPEED_256KHZ: printf("256 KHz");	break ;
+		case BCM2835_SPI_SPEED_128KHZ: printf("128 KHz");	break ;
+		case BCM2835_SPI_SPEED_64KHZ : printf("64 KHz");	break ;
+		case BCM2835_SPI_SPEED_32KHZ : printf("32 KHz");	break ;
+		case BCM2835_SPI_SPEED_16KHZ : printf("16 KHz");	break ;
+		case BCM2835_SPI_SPEED_8KHZ  : printf("8 KHz");	break ;
+		default : printf("Probably Bad !!!");	break ;
+	}
+	printf("\n");
+
+	printf("================ NRF Configuration ================\n" );
+
+  print_status(get_status());
+
+  print_address_register("RX_ADDR_P0-1",RX_ADDR_P0,2);
+  print_byte_register("RX_ADDR_P2-5",RX_ADDR_P2,4);
+  print_address_register("TX_ADDR",TX_ADDR);
+
+  print_byte_register("RX_PW_P0-6",RX_PW_P0,6);
+  print_byte_register("EN_AA",EN_AA);
+  print_byte_register("EN_RXADDR",EN_RXADDR);
+  print_byte_register("RF_CH",RF_CH);
+  print_byte_register("RF_SETUP",RF_SETUP);
+  print_byte_register("CONFIG",CONFIG);
+  print_byte_register("DYNPD/FEATURE",DYNPD,2);
+
+  printf("Data Rate\t = %s\r\n",rf24_datarate_e_str_P[getDataRate()]);
+  printf("Model\t\t = %s\r\n",rf24_model_e_str_P[isPVariant()]);
+  printf("CRC Length\t = %s\r\n",rf24_crclength_e_str_P[getCRCLength()]);
+  printf("PA Power\t = %s\r\n",rf24_pa_dbm_e_str_P[getPALevel()]);
+}
+
+/****************************************************************************/
+
+bool RF24::begin(void)
+{
+	debug = false;
+	//debug = true;
+
+	// Init BCM2835 chipset for talking with us
+	if (!bcm2835_init())
+		return false;
+
+	// Initialise the CE pin of NRF24 (chip enable)
+	bcm2835_gpio_fsel(ce_pin, BCM2835_GPIO_FSEL_OUTP);
+  bcm2835_gpio_write(ce_pin, LOW);
+	
+	// used to drive custom I/O to trigger my logic analyser
+	// bcm2835_gpio_fsel(GPIO_CTRL_PIN , BCM2835_GPIO_FSEL_OUTP);
+
+  // start the SPI library:
+  // Note the NRF24 wants mode 0, MSB first and default to 1 Mbps
+	bcm2835_spi_setBitOrder(BCM2835_SPI_BIT_ORDER_MSBFIRST);      
+	bcm2835_spi_setDataMode(BCM2835_SPI_MODE0); 
+
+	// Set SPI bus Speed
+	bcm2835_spi_setClockSpeed(spi_speed); 
+	
+	// This initialize the SPI bus with 
+	// csn pin as chip select (custom or not)
+	bcm2835_spi_begin(csn_pin);
+
+  // wait 100ms
+	delay(100);
+
+  // Must allow the radio time to settle else configuration bits will not necessarily stick.
+  // This is actually only required following power up but some settling time also appears to
+  // be required after resets too. For full coverage, we'll always assume the worst.
+  // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
+  // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
+  // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
+  delay( 5 ) ;
+
+  // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
+  // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
+  // sizes must never be used. See documentation for a more complete explanation.
+	//printf("write_register(%02X, %02X)\n", SETUP_RETR, (0b0100 << ARD) | (0b1111 << ARC));
+  write_register(SETUP_RETR,(0b0100 << ARD) | (0b1111 << ARC));
+
+  // Restore our default PA level
+  setPALevel( RF24_PA_MAX ) ;
+
+  // Determine if this is a p or non-p RF24 module and then
+  // reset our data rate back to default value. This works
+  // because a non-P variant won't allow the data rate to
+  // be set to 250Kbps.
+  if( setDataRate( RF24_250KBPS ) )
+  {
+    p_variant = true ;
+  }
+  
+  // Then set the data rate to the slowest (and most reliable) speed supported by all
+  // hardware.
+  setDataRate( RF24_1MBPS ) ;
+
+  // Initialize CRC and request 2-byte (16bit) CRC
+  setCRCLength( RF24_CRC_16 ) ;
+  
+  // Disable dynamic payloads, to match dynamic_payloads_enabled setting
+  write_register(DYNPD,0);
+
+  // Reset current status
+  // Notice reset and flush is the last thing we do
+  write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
+
+  // Set up default configuration.  Callers can always change it later.
+  // This channel should be universally safe and not bleed over into adjacent
+  // spectrum.
+  setChannel(76);
+
+  // Flush buffers
+  flush_rx();
+  flush_tx();
+	
+	return true;
+}
+
+/****************************************************************************/
+
+void RF24::startListening(void)
+{
+  write_register(CONFIG, read_register(CONFIG) | _BV(PWR_UP) | _BV(PRIM_RX));
+  write_register(STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
+
+  // Restore the pipe0 adddress, if exists
+  if (pipe0_reading_address)
+    write_register(RX_ADDR_P0, reinterpret_cast(&pipe0_reading_address), 5);
+
+  // Flush buffers
+  flush_rx();
+  flush_tx();
+
+  // Go!
+  bcm2835_gpio_write(ce_pin, HIGH);
+
+  // wait for the radio to come up (130us actually only needed)
+  delayMicroseconds(130);
+}
+
+/****************************************************************************/
+
+void RF24::stopListening(void)
+{
+  bcm2835_gpio_write(ce_pin, LOW);
+  flush_tx();
+  flush_rx();
+}
+
+/****************************************************************************/
+
+void RF24::powerDown(void)
+{
+  write_register(CONFIG,read_register(CONFIG) & ~_BV(PWR_UP));
+}
+
+/****************************************************************************/
+
+void RF24::powerUp(void)
+{
+  write_register(CONFIG,read_register(CONFIG) | _BV(PWR_UP));
+}
+
+/******************************************************************/
+
+bool RF24::write( const void* buf, uint8_t len )
+{
+  bool result = false;
+
+  // Begin the write
+  startWrite(buf,len);
+
+  // ------------
+  // At this point we could return from a non-blocking write, and then call
+  // the rest after an interrupt
+
+  // Instead, we are going to block here until we get TX_DS (transmission completed and ack'd)
+  // or MAX_RT (maximum retries, transmission failed).  Also, we'll timeout in case the radio
+  // is flaky and we get neither.
+
+  // IN the end, the send should be blocking.  It comes back in 60ms worst case, or much faster
+  // if I tighted up the retry logic.  (Default settings will be 1500us.
+  // Monitor the send
+  uint8_t observe_tx;
+  uint8_t status;
+  uint32_t sent_at = millis();
+  const unsigned long timeout = 500; //ms to wait for timeout
+	
+  do
+  {
+    status = read_register(OBSERVE_TX,&observe_tx,1);
+		
+    if (debug)
+			printf("%02X", observe_tx);
+  }
+  while( ! ( status & ( _BV(TX_DS) | _BV(MAX_RT) ) ) && ( millis() - sent_at < timeout ) );
+
+	
+  // The part above is what you could recreate with your own interrupt handler,
+  // and then call this when you got an interrupt
+  // ------------
+
+  // Call this when you get an interrupt
+  // The status tells us three things
+  // * The send was successful (TX_DS)
+  // * The send failed, too many retries (MAX_RT)
+  // * There is an ack packet waiting (RX_DR)
+  bool tx_ok, tx_fail;
+	
+  whatHappened(tx_ok,tx_fail,ack_payload_available);
+  
+  //printf("%u%u%u\r\n",tx_ok,tx_fail,ack_payload_available);
+
+  result = tx_ok;
+  if (debug)
+		printf(result?"...OK.":"...Failed");
+
+  // Handle the ack packet
+  if ( ack_payload_available )
+  {
+    ack_payload_length = getDynamicPayloadSize();
+    if (debug )
+			printf("[AckPacket]/%d", ack_payload_length);
+  }
+
+  // Yay, we are done.
+
+  // Power down
+  powerDown();
+
+  // Flush buffers (Is this a relic of past experimentation, and not needed anymore??)
+  flush_tx();
+
+  return result;
+}
+/****************************************************************************/
+
+void RF24::startWrite( const void* buf, uint8_t len )
+{
+  // Transmitter power-up
+  write_register(CONFIG, ( read_register(CONFIG) | _BV(PWR_UP) ) & ~_BV(PRIM_RX) );
+  delayMicroseconds(150);
+
+  // Send the payload
+  write_payload( buf, len );
+
+  // Allons!
+  bcm2835_gpio_write(ce_pin, HIGH);
+  delayMicroseconds(15);
+  bcm2835_gpio_write(ce_pin, LOW);
+}
+
+/****************************************************************************/
+
+uint8_t RF24::getDynamicPayloadSize(void)
+{
+  uint8_t result = 0;
+
+  bcm2835_spi_transfer( R_RX_PL_WID );
+  result = bcm2835_spi_transfer(0xff);
+
+  return result;
+}
+
+/****************************************************************************/
+
+bool RF24::available(void)
+{
+  return available(NULL);
+}
+
+/****************************************************************************/
+
+bool RF24::available(uint8_t* pipe_num)
+{
+  uint8_t status = get_status();
+
+  // Too noisy, enable if you really want lots o data!!
+  // if (debug) print_status(status);
+
+  bool result = ( status & _BV(RX_DR) );
+
+  if (result)
+  {
+    // If the caller wants the pipe number, include that
+    if ( pipe_num )
+      *pipe_num = ( status >> RX_P_NO ) & 0b111;
+
+    // Clear the status bit
+
+    // ??? Should this REALLY be cleared now?  Or wait until we
+    // actually READ the payload?
+
+    write_register(STATUS,_BV(RX_DR) );
+
+    // Handle ack payload receipt
+    if ( status & _BV(TX_DS) )
+    {
+      write_register(STATUS,_BV(TX_DS));
+    }
+  }
+
+  return result;
+}
+
+/****************************************************************************/
+
+bool RF24::read( void* buf, uint8_t len )
+{
+  // Fetch the payload
+  read_payload( buf, len );
+
+  // was this the last of the data available?
+  return read_register(FIFO_STATUS) & _BV(RX_EMPTY);
+}
+
+/****************************************************************************/
+
+void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
+{
+  // Read the status & reset the status in one easy call
+  // Or is that such a good idea?
+  uint8_t status = write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
+
+  // Report to the user what happened
+  tx_ok = status & _BV(TX_DS);
+  tx_fail = status & _BV(MAX_RT);
+  rx_ready = status & _BV(RX_DR);
+}
+
+/****************************************************************************/
+
+void RF24::openWritingPipe(uint64_t value)
+{
+  // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
+  // expects it LSB first too, so we're good.
+
+  write_register(RX_ADDR_P0, reinterpret_cast(&value), 5);
+  write_register(TX_ADDR, reinterpret_cast(&value), 5);
+
+  const uint8_t max_payload_size = 32;
+  write_register(RX_PW_P0,min(payload_size,max_payload_size));
+}
+
+/****************************************************************************/
+
+static const uint8_t child_pipe[] =
+{
+  RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5
+};
+static const uint8_t child_payload_size[] =
+{
+  RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5
+};
+static const uint8_t child_pipe_enable[] =
+{
+  ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5
+};
+
+void RF24::openReadingPipe(uint8_t child, uint64_t address)
+{
+  // If this is pipe 0, cache the address.  This is needed because
+  // openWritingPipe() will overwrite the pipe 0 address, so
+  // startListening() will have to restore it.
+  if (child == 0)
+    pipe0_reading_address = address;
+
+  if (child <= 6)
+  {
+    // For pipes 2-5, only write the LSB
+    if ( child < 2 )
+      write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast(&address), 5);
+    else
+      write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast(&address), 1);
+
+    write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
+
+    // Note it would be more efficient to set all of the bits for all open
+    // pipes at once.  However, I thought it would make the calling code
+    // more simple to do it this way.
+    write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
+  }
+}
+
+/****************************************************************************/
+
+void RF24::toggle_features(void)
+{
+  bcm2835_spi_transfer( ACTIVATE );
+  bcm2835_spi_transfer( 0x73 );
+}
+
+/****************************************************************************/
+
+void RF24::enableDynamicPayloads(void)
+{
+  // Enable dynamic payload throughout the system
+  write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
+
+  // If it didn't work, the features are not enabled
+  if ( ! read_register(FEATURE) )
+  {
+    // So enable them and try again
+    toggle_features();
+    write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
+  }
+
+  if (debug) 
+		printf("FEATURE=%i\r\n",read_register(FEATURE));
+
+  // Enable dynamic payload on all pipes
+  //
+  // Not sure the use case of only having dynamic payload on certain
+  // pipes, so the library does not support it.
+  write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
+
+  dynamic_payloads_enabled = true;
+}
+
+/****************************************************************************/
+
+void RF24::enableAckPayload(void)
+{
+  //
+  // enable ack payload and dynamic payload features
+  //
+
+  write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
+
+  // If it didn't work, the features are not enabled
+  if ( ! read_register(FEATURE) )
+  {
+    // So enable them and try again
+    toggle_features();
+    write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
+  }
+
+  if (debug)
+		printf("FEATURE=%i\r\n",read_register(FEATURE));
+
+  //
+  // Enable dynamic payload on pipes 0 & 1
+  //
+
+  write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
+}
+
+/****************************************************************************/
+
+void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
+{
+  const uint8_t* current = reinterpret_cast(buf);
+
+  bcm2835_spi_transfer( W_ACK_PAYLOAD | ( pipe & 0b111 ) );
+  const uint8_t max_payload_size = 32;
+  uint8_t data_len = min(len,max_payload_size);
+  while ( data_len-- )
+    bcm2835_spi_transfer(*current++);
+}
+
+/****************************************************************************/
+
+bool RF24::isAckPayloadAvailable(void)
+{
+  bool result = ack_payload_available;
+  ack_payload_available = false;
+  return result;
+}
+
+/****************************************************************************/
+
+bool RF24::isPVariant(void)
+{
+  return p_variant ;
+}
+
+/****************************************************************************/
+
+void RF24::setAutoAck(bool enable)
+{
+  if ( enable )
+    write_register(EN_AA, 0b111111);
+  else
+    write_register(EN_AA, 0);
+}
+
+/****************************************************************************/
+
+void RF24::setAutoAck( uint8_t pipe, bool enable )
+{
+  if ( pipe <= 6 )
+  {
+    uint8_t en_aa = read_register( EN_AA ) ;
+    if( enable )
+    {
+      en_aa |= _BV(pipe) ;
+    }
+    else
+    {
+      en_aa &= ~_BV(pipe) ;
+    }
+    write_register( EN_AA, en_aa ) ;
+  }
+}
+
+/****************************************************************************/
+
+bool RF24::testCarrier(void)
+{
+  return ( read_register(CD) & 1 );
+}
+
+/****************************************************************************/
+
+bool RF24::testRPD(void)
+{
+  return ( read_register(RPD) & 1 ) ;
+}
+
+/****************************************************************************/
+
+void RF24::setPALevel(rf24_pa_dbm_e level)
+{
+  uint8_t setup = read_register(RF_SETUP) ;
+  setup &= ~(_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
+
+  // switch uses RAM (evil!)
+  if ( level == RF24_PA_MAX )
+  {
+    setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
+  }
+  else if ( level == RF24_PA_HIGH )
+  {
+    setup |= _BV(RF_PWR_HIGH) ;
+  }
+  else if ( level == RF24_PA_LOW )
+  {
+    setup |= _BV(RF_PWR_LOW);
+  }
+  else if ( level == RF24_PA_MIN )
+  {
+    // nothing
+  }
+  else if ( level == RF24_PA_ERROR )
+  {
+    // On error, go to maximum PA
+    setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
+  }
+
+  write_register( RF_SETUP, setup ) ;
+}
+
+/****************************************************************************/
+
+rf24_pa_dbm_e RF24::getPALevel(void)
+{
+  rf24_pa_dbm_e result = RF24_PA_ERROR ;
+  uint8_t power = read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
+
+  // switch uses RAM (evil!)
+  if ( power == (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) )
+  {
+    result = RF24_PA_MAX ;
+  }
+  else if ( power == _BV(RF_PWR_HIGH) )
+  {
+    result = RF24_PA_HIGH ;
+  }
+  else if ( power == _BV(RF_PWR_LOW) )
+  {
+    result = RF24_PA_LOW ;
+  }
+  else
+  {
+    result = RF24_PA_MIN ;
+  }
+
+  return result ;
+}
+
+/****************************************************************************/
+
+bool RF24::setDataRate(rf24_datarate_e speed)
+{
+  bool result = false;
+  uint8_t setup = read_register(RF_SETUP) ;
+
+  // HIGH and LOW '00' is 1Mbs - our default
+  wide_band = false ;
+  setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ;
+  if( speed == RF24_250KBPS )
+  {
+    // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
+    // Making it '10'.
+    wide_band = false ;
+    setup |= _BV( RF_DR_LOW ) ;
+  }
+  else
+  {
+    // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
+    // Making it '01'
+    if ( speed == RF24_2MBPS )
+    {
+      wide_band = true ;
+      setup |= _BV(RF_DR_HIGH);
+    }
+    else
+    {
+      // 1Mbs
+      wide_band = false ;
+    }
+  }
+  write_register(RF_SETUP,setup);
+
+  // Verify our result
+  if ( read_register(RF_SETUP) == setup )
+  {
+    result = true;
+  }
+  else
+  {
+    wide_band = false;
+  }
+
+  return result;
+}
+
+/****************************************************************************/
+
+rf24_datarate_e RF24::getDataRate( void )
+{
+  rf24_datarate_e result ;
+  uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH));
+  
+  // switch uses RAM (evil!)
+  // Order matters in our case below
+  if ( dr == _BV(RF_DR_LOW) )
+  {
+    // '10' = 250KBPS
+    result = RF24_250KBPS ;
+  }
+  else if ( dr == _BV(RF_DR_HIGH) )
+  {
+    // '01' = 2MBPS
+    result = RF24_2MBPS ;
+  }
+  else
+  {
+    // '00' = 1MBPS
+    result = RF24_1MBPS ;
+  }
+  return result ;
+}
+
+/****************************************************************************/
+
+void RF24::setCRCLength(rf24_crclength_e length)
+{
+  uint8_t config = read_register(CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ;
+  
+  // switch uses RAM (evil!)
+  if ( length == RF24_CRC_DISABLED )
+  {
+    // Do nothing, we turned it off above. 
+  }
+  else if ( length == RF24_CRC_8 )
+  {
+    config |= _BV(EN_CRC);
+  }
+  else
+  {
+    config |= _BV(EN_CRC);
+    config |= _BV( CRCO );
+  }
+  write_register( CONFIG, config ) ;
+}
+
+/****************************************************************************/
+
+rf24_crclength_e RF24::getCRCLength(void)
+{
+  rf24_crclength_e result = RF24_CRC_DISABLED;
+  uint8_t config = read_register(CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ;
+
+  if ( config & _BV(EN_CRC ) )
+  {
+    if ( config & _BV(CRCO) )
+      result = RF24_CRC_16;
+    else
+      result = RF24_CRC_8;
+  }
+
+  return result;
+}
+
+/****************************************************************************/
+
+void RF24::disableCRC( void )
+{
+  uint8_t disable = read_register(CONFIG) & ~_BV(EN_CRC) ;
+  write_register( CONFIG, disable ) ;
+}
+
+/****************************************************************************/
+void RF24::setRetries(uint8_t delay, uint8_t count)
+{
+ write_register(SETUP_RETR,(delay&0xf)<
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ 
+ 03/17/2013 : Charles-Henri Hallard (http://hallard.me)
+              Modified to use with Arduipi board http://hallard.me/arduipi
+              Modified to use the great bcm2835 library for I/O and SPI
+							
+ */
+
+/**
+ * @file RF24.h
+ *
+ * Class declaration for RF24 and helper enums
+ */
+
+#ifndef __RF24_H__
+#define __RF24_H__
+
+#include "RF24_config.h"
+#include "./bcm2835.h"
+
+
+/**
+ * Power Amplifier level.
+ *
+ * For use with setPALevel()
+ */
+typedef enum { RF24_PA_MIN = 0,RF24_PA_LOW, RF24_PA_HIGH, RF24_PA_MAX, RF24_PA_ERROR } rf24_pa_dbm_e ;
+
+/**
+ * Data rate.  How fast data moves through the air.
+ *
+ * For use with setDataRate()
+ */
+typedef enum { RF24_1MBPS = 0, RF24_2MBPS, RF24_250KBPS } rf24_datarate_e;
+
+/**
+ * CRC Length.  How big (if any) of a CRC is included.
+ *
+ * For use with setCRCLength()
+ */
+typedef enum { RF24_CRC_DISABLED = 0, RF24_CRC_8, RF24_CRC_16 } rf24_crclength_e;
+
+/**
+ * Driver for nRF24L01(+) 2.4GHz Wireless Transceiver
+ */
+
+class RF24
+{
+private:
+  uint8_t ce_pin; /**< "Chip Enable" pin, activates the RX or TX role */
+  uint8_t csn_pin; /**< SPI Chip select */
+	uint16_t spi_speed; /**< SPI Bus Speed */
+  bool wide_band; /* 2Mbs data rate in use? */
+  bool p_variant; /* False for RF24L01 and true for RF24L01P */
+  uint8_t payload_size; /**< Fixed size of payloads */
+  bool ack_payload_available; /**< Whether there is an ack payload waiting */
+  bool dynamic_payloads_enabled; /**< Whether dynamic payloads are enabled. */ 
+  uint8_t ack_payload_length; /**< Dynamic size of pending ack payload. */
+  uint64_t pipe0_reading_address; /**< Last address set on pipe 0 for reading. */
+	//uint32_t spispeed;
+  uint8_t debug ; /* Debug flag */
+  uint8_t spi_rxbuff[32] ; //SPI receive buffer (payload max 32 bytes)
+  uint8_t spi_txbuff[32+1] ; //SPI transmit buffer (payload max 32 bytes + 1 byte for the command)
+
+protected:
+  /**
+   * @name Low-level internal interface.
+   *
+   *  Protected methods that address the chip directly.  Regular users cannot
+   *  ever call these.  They are documented for completeness and for developers who
+   *  may want to extend this class.
+   */
+  /**@{*/
+
+
+  /**
+   * Read a chunk of data in from a register
+   *
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param buf Where to put the data
+   * @param len How many bytes of data to transfer
+   * @return Current value of status register
+   */
+  uint8_t read_register(uint8_t reg, uint8_t* buf, uint8_t len);
+
+  /**
+   * Read single byte from a register
+   *
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @return Current value of register @p reg
+   */
+  uint8_t read_register(uint8_t reg);
+
+  /**
+   * Write a chunk of data to a register
+   *
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param buf Where to get the data
+   * @param len How many bytes of data to transfer
+   * @return Current value of status register
+   */
+  uint8_t write_register(uint8_t reg, const uint8_t* buf, uint8_t len);
+
+  /**
+   * Write a single byte to a register
+   *
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param value The new value to write
+   * @return Current value of status register
+   */
+  uint8_t write_register(uint8_t reg, uint8_t value);
+
+  /**
+   * Write the transmit payload
+   *
+   * The size of data written is the fixed payload size, see getPayloadSize()
+   *
+   * @param buf Where to get the data
+   * @param len Number of bytes to be sent
+   * @return Current value of status register
+   */
+  uint8_t write_payload(const void* buf, uint8_t len);
+
+  /**
+   * Read the receive payload
+   *
+   * The size of data read is the fixed payload size, see getPayloadSize()
+   *
+   * @param buf Where to put the data
+   * @param len Maximum number of bytes to read
+   * @return Current value of status register
+   */
+  uint8_t read_payload(void* buf, uint8_t len);
+
+  /**
+   * Empty the receive buffer
+   *
+   * @return Current value of status register
+   */
+  uint8_t flush_rx(void);
+
+  /**
+   * Empty the transmit buffer
+   *
+   * @return Current value of status register
+   */
+  uint8_t flush_tx(void);
+
+  /**
+   * Retrieve the current status of the chip
+   *
+   * @return Current value of status register
+   */
+  uint8_t get_status(void);
+
+  /**
+   * Decode and print the given status to stdout
+   *
+   * @param status Status value to print
+   *
+   * @warning Does nothing if stdout is not defined.  See fdevopen in stdio.h
+   */
+  void print_status(uint8_t status);
+
+  /**
+   * Decode and print the given 'observe_tx' value to stdout
+   *
+   * @param value The observe_tx value to print
+   *
+   * @warning Does nothing if stdout is not defined.  See fdevopen in stdio.h
+   */
+  void print_observe_tx(uint8_t value);
+
+  /**
+   * Print the name and value of an 8-bit register to stdout
+   *
+   * Optionally it can print some quantity of successive
+   * registers on the same line.  This is useful for printing a group
+   * of related registers on one line.
+   *
+   * @param name Name of the register
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param qty How many successive registers to print
+   */
+  void print_byte_register(const char* name, uint8_t reg, uint8_t qty = 1);
+
+  /**
+   * Print the name and value of a 40-bit address register to stdout
+   *
+   * Optionally it can print some quantity of successive
+   * registers on the same line.  This is useful for printing a group
+   * of related registers on one line.
+   *
+   * @param name Name of the register
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param qty How many successive registers to print
+   */
+  void print_address_register(const char* name, uint8_t reg, uint8_t qty = 1);
+
+  /**
+   * Turn on or off the special features of the chip
+   *
+   * The chip has certain 'features' which are only available when the 'features'
+   * are enabled.  See the datasheet for details.
+   */
+  void toggle_features(void);
+  /**@}*/
+
+public:
+  /**
+   * @name Primary public interface
+   *
+   *  These are the main methods you need to operate the chip
+   */
+  /**@{*/
+
+  /**
+   * Constructor
+   *
+   * Creates a new instance of this driver.  Before using, you create an instance
+   * and send in the unique pins that this chip is connected to.
+   *
+   * @param _cepin The pin attached to Chip Enable on the RF module
+   * @param _cspin The pin attached to Chip Select
+   */
+  RF24(uint8_t _cepin, uint8_t _cspin);
+  RF24(uint8_t _cepin, uint8_t _cspin, uint32_t spispeed );
+
+  /**
+   * Begin operation of the chip
+   *
+   * Call this in setup(), before calling any other methods.
+   */
+  bool begin(void);
+
+  /**
+   * Start listening on the pipes opened for reading.
+   *
+   * Be sure to call openReadingPipe() first.  Do not call write() while
+   * in this mode, without first calling stopListening().  Call
+   * isAvailable() to check for incoming traffic, and read() to get it.
+   */
+  void startListening(void);
+
+  /**
+   * Stop listening for incoming messages
+   *
+   * Do this before calling write().
+   */
+  void stopListening(void);
+
+  /**
+   * Write to the open writing pipe
+   *
+   * Be sure to call openWritingPipe() first to set the destination
+   * of where to write to.
+   *
+   * This blocks until the message is successfully acknowledged by
+   * the receiver or the timeout/retransmit maxima are reached.  In
+   * the current configuration, the max delay here is 60ms.
+   *
+   * The maximum size of data written is the fixed payload size, see
+   * getPayloadSize().  However, you can write less, and the remainder
+   * will just be filled with zeroes.
+   *
+   * @param buf Pointer to the data to be sent
+   * @param len Number of bytes to be sent
+   * @return True if the payload was delivered successfully false if not
+   */
+  bool write( const void* buf, uint8_t len );
+
+  /**
+   * Test whether there are bytes available to be read
+   *
+   * @return True if there is a payload available, false if none is
+   */
+  bool available(void);
+
+  /**
+   * Read the payload
+   *
+   * Return the last payload received
+   *
+   * The size of data read is the fixed payload size, see getPayloadSize()
+   *
+   * @note I specifically chose 'void*' as a data type to make it easier
+   * for beginners to use.  No casting needed.
+   *
+   * @param buf Pointer to a buffer where the data should be written
+   * @param len Maximum number of bytes to read into the buffer
+   * @return True if the payload was delivered successfully false if not
+   */
+  bool read( void* buf, uint8_t len );
+
+  /**
+   * Open a pipe for writing
+   *
+   * Only one pipe can be open at once, but you can change the pipe
+   * you'll listen to.  Do not call this while actively listening.
+   * Remember to stopListening() first.
+   *
+   * Addresses are 40-bit hex values, e.g.:
+   *
+   * @code
+   *   openWritingPipe(0xF0F0F0F0F0);
+   * @endcode
+   *
+   * @param address The 40-bit address of the pipe to open.  This can be
+   * any value whatsoever, as long as you are the only one writing to it
+   * and only one other radio is listening to it.  Coordinate these pipe
+   * addresses amongst nodes on the network.
+   */
+  void openWritingPipe(uint64_t address);
+
+  /**
+   * Open a pipe for reading
+   *
+   * Up to 6 pipes can be open for reading at once.  Open all the
+   * reading pipes, and then call startListening().
+   *
+   * @see openWritingPipe
+   *
+   * @warning Pipes 1-5 should share the first 32 bits.
+   * Only the least significant byte should be unique, e.g.
+   * @code
+   *   openReadingPipe(1,0xF0F0F0F0AA);
+   *   openReadingPipe(2,0xF0F0F0F066);
+   * @endcode
+   *
+   * @warning Pipe 0 is also used by the writing pipe.  So if you open
+   * pipe 0 for reading, and then startListening(), it will overwrite the
+   * writing pipe.  Ergo, do an openWritingPipe() again before write().
+   *
+   * @todo Enforce the restriction that pipes 1-5 must share the top 32 bits
+   *
+   * @param number Which pipe# to open, 0-5.
+   * @param address The 40-bit address of the pipe to open.
+   */
+  void openReadingPipe(uint8_t number, uint64_t address);
+
+  /**@}*/
+  /**
+   * @name Optional Configurators 
+   *
+   *  Methods you can use to get or set the configuration of the chip.
+   *  None are required.  Calling begin() sets up a reasonable set of
+   *  defaults.
+   */
+  /**@{*/
+  /**
+   * Set the number and delay of retries upon failed submit
+   *
+   * @param delay How long to wait between each retry, in multiples of 250us,
+   * max is 15.  0 means 250us, 15 means 4000us.
+   * @param count How many retries before giving up, max 15
+   */
+  void setRetries(uint8_t delay, uint8_t count);
+
+  /**
+   * Set RF communication channel
+   *
+   * @param channel Which RF channel to communicate on, 0-127
+   */
+  void setChannel(uint8_t channel);
+
+  /**
+   * Set Static Payload Size
+   *
+   * This implementation uses a pre-stablished fixed payload size for all
+   * transmissions.  If this method is never called, the driver will always
+   * transmit the maximum payload size (32 bytes), no matter how much
+   * was sent to write().
+   *
+   * @todo Implement variable-sized payloads feature
+   *
+   * @param size The number of bytes in the payload
+   */
+  void setPayloadSize(uint8_t size);
+
+  /**
+   * Get Static Payload Size
+   *
+   * @see setPayloadSize()
+   *
+   * @return The number of bytes in the payload
+   */
+  uint8_t getPayloadSize(void);
+
+  /**
+   * Get Dynamic Payload Size
+   *
+   * For dynamic payloads, this pulls the size of the payload off
+   * the chip
+   *
+   * @return Payload length of last-received dynamic payload
+   */
+  uint8_t getDynamicPayloadSize(void);
+  
+  /**
+   * Enable custom payloads on the acknowledge packets
+   *
+   * Ack payloads are a handy way to return data back to senders without
+   * manually changing the radio modes on both units.
+   *
+   * @see examples/pingpair_pl/pingpair_pl.pde
+   */
+  void enableAckPayload(void);
+
+  /**
+   * Enable dynamically-sized payloads
+   *
+   * This way you don't always have to send large packets just to send them
+   * once in a while.  This enables dynamic payloads on ALL pipes.
+   *
+   * @see examples/pingpair_pl/pingpair_dyn.pde
+   */
+  void enableDynamicPayloads(void);
+
+  /**
+   * Determine whether the hardware is an nRF24L01+ or not.
+   *
+   * @return true if the hardware is nRF24L01+ (or compatible) and false
+   * if its not.
+   */
+  bool isPVariant(void) ;
+
+  /**
+   * Enable or disable auto-acknowlede packets
+   *
+   * This is enabled by default, so it's only needed if you want to turn
+   * it off for some reason.
+   *
+   * @param enable Whether to enable (true) or disable (false) auto-acks
+   */
+  void setAutoAck(bool enable);
+
+  /**
+   * Enable or disable auto-acknowlede packets on a per pipeline basis.
+   *
+   * AA is enabled by default, so it's only needed if you want to turn
+   * it off/on for some reason on a per pipeline basis.
+   *
+   * @param pipe Which pipeline to modify
+   * @param enable Whether to enable (true) or disable (false) auto-acks
+   */
+  void setAutoAck( uint8_t pipe, bool enable ) ;
+
+  /**
+   * Set Power Amplifier (PA) level to one of four levels.
+   * Relative mnemonics have been used to allow for future PA level
+   * changes. According to 6.5 of the nRF24L01+ specification sheet,
+   * they translate to: RF24_PA_MIN=-18dBm, RF24_PA_LOW=-12dBm,
+   * RF24_PA_MED=-6dBM, and RF24_PA_HIGH=0dBm.
+   *
+   * @param level Desired PA level.
+   */
+  void setPALevel( rf24_pa_dbm_e level ) ;
+
+  /**
+   * Fetches the current PA level.
+   *
+   * @return Returns a value from the rf24_pa_dbm_e enum describing
+   * the current PA setting. Please remember, all values represented
+   * by the enum mnemonics are negative dBm. See setPALevel for
+   * return value descriptions.
+   */
+  rf24_pa_dbm_e getPALevel( void ) ;
+
+  /**
+   * Set the transmission data rate
+   *
+   * @warning setting RF24_250KBPS will fail for non-plus units
+   *
+   * @param speed RF24_250KBPS for 250kbs, RF24_1MBPS for 1Mbps, or RF24_2MBPS for 2Mbps
+   * @return true if the change was successful
+   */
+  bool setDataRate(rf24_datarate_e speed);
+  
+  /**
+   * Fetches the transmission data rate
+   *
+   * @return Returns the hardware's currently configured datarate. The value
+   * is one of 250kbs, RF24_1MBPS for 1Mbps, or RF24_2MBPS, as defined in the
+   * rf24_datarate_e enum.
+   */
+  rf24_datarate_e getDataRate( void ) ;
+
+  /**
+   * Set the CRC length
+   *
+   * @param length RF24_CRC_8 for 8-bit or RF24_CRC_16 for 16-bit
+   */
+  void setCRCLength(rf24_crclength_e length);
+
+  /**
+   * Get the CRC length
+   *
+   * @return RF24_DISABLED if disabled or RF24_CRC_8 for 8-bit or RF24_CRC_16 for 16-bit
+   */
+  rf24_crclength_e getCRCLength(void);
+
+  /**
+   * Disable CRC validation
+   *
+   */
+  void disableCRC( void ) ;
+
+  /**@}*/
+  /**
+   * @name Advanced Operation 
+   *
+   *  Methods you can use to drive the chip in more advanced ways 
+   */
+  /**@{*/
+
+  /**
+   * Print a giant block of debugging information to stdout
+   *
+   * @warning Does nothing if stdout is not defined.  See fdevopen in stdio.h
+   */
+  void printDetails(void);
+
+  /**
+   * Enter low-power mode
+   *
+   * To return to normal power mode, either write() some data or
+   * startListening, or powerUp().
+   */
+  void powerDown(void);
+
+  /**
+   * Leave low-power mode - making radio more responsive
+   *
+   * To return to low power mode, call powerDown().
+   */
+  void powerUp(void) ;
+
+  /**
+   * Test whether there are bytes available to be read
+   *
+   * Use this version to discover on which pipe the message
+   * arrived.
+   *
+   * @param[out] pipe_num Which pipe has the payload available
+   * @return True if there is a payload available, false if none is
+   */
+  bool available(uint8_t* pipe_num);
+
+  /**
+   * Non-blocking write to the open writing pipe
+   *
+   * Just like write(), but it returns immediately. To find out what happened
+   * to the send, catch the IRQ and then call whatHappened().
+   *
+   * @see write()
+   * @see whatHappened()
+   *
+   * @param buf Pointer to the data to be sent
+   * @param len Number of bytes to be sent
+   * @return True if the payload was delivered successfully false if not
+   */
+  void startWrite( const void* buf, uint8_t len );
+
+  /**
+   * Write an ack payload for the specified pipe
+   *
+   * The next time a message is received on @p pipe, the data in @p buf will
+   * be sent back in the acknowledgement.
+   *
+   * @warning According to the data sheet, only three of these can be pending
+   * at any time.  I have not tested this.
+   *
+   * @param pipe Which pipe# (typically 1-5) will get this response.
+   * @param buf Pointer to data that is sent
+   * @param len Length of the data to send, up to 32 bytes max.  Not affected
+   * by the static payload set by setPayloadSize().
+   */
+  void writeAckPayload(uint8_t pipe, const void* buf, uint8_t len);
+
+  /**
+   * Determine if an ack payload was received in the most recent call to
+   * write().
+   *
+   * Call read() to retrieve the ack payload.
+   *
+   * @warning Calling this function clears the internal flag which indicates
+   * a payload is available.  If it returns true, you must read the packet
+   * out as the very next interaction with the radio, or the results are
+   * undefined.
+   *
+   * @return True if an ack payload is available.
+   */
+  bool isAckPayloadAvailable(void);
+
+  /**
+   * Call this when you get an interrupt to find out why
+   *
+   * Tells you what caused the interrupt, and clears the state of
+   * interrupts.
+   *
+   * @param[out] tx_ok The send was successful (TX_DS)
+   * @param[out] tx_fail The send failed, too many retries (MAX_RT)
+   * @param[out] rx_ready There is a message waiting to be read (RX_DS)
+   */
+  void whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready);
+
+  /**
+   * Test whether there was a carrier on the line for the
+   * previous listening period.
+   *
+   * Useful to check for interference on the current channel.
+   *
+   * @return true if was carrier, false if not
+   */
+  bool testCarrier(void);
+
+  /**
+   * Test whether a signal (carrier or otherwise) greater than
+   * or equal to -64dBm is present on the channel. Valid only
+   * on nRF24L01P (+) hardware. On nRF24L01, use testCarrier().
+   *
+   * Useful to check for interference on the current channel and
+   * channel hopping strategies.
+   *
+   * @return true if signal => -64dBm, false if not
+   */
+  bool testRPD(void) ;
+
+  /**@}*/
+};
+
+/**
+ * @example GettingStarted.pde
+ *
+ * This is an example which corresponds to my "Getting Started" blog post:
+ * Getting Started with nRF24L01+ on Arduino. 
+ *
+ * It is an example of how to use the RF24 class.  Write this sketch to two 
+ * different nodes.  Put one of the nodes into 'transmit' mode by connecting 
+ * with the serial monitor and sending a 'T'.  The ping node sends the current 
+ * time to the pong node, which responds by sending the value back.  The ping 
+ * node can then see how long the whole cycle took.
+ */
+
+/**
+ * @example nordic_fob.pde
+ *
+ * This is an example of how to use the RF24 class to receive signals from the
+ * Sparkfun Nordic FOB.  See http://www.sparkfun.com/products/8602 .
+ * Thanks to Kirk Mower for providing test hardware.
+ */
+
+/**
+ * @example led_remote.pde
+ *
+ * This is an example of how to use the RF24 class to control a remote
+ * bank of LED's using buttons on a remote control.
+ *
+ * Every time the buttons change on the remote, the entire state of
+ * buttons is send to the led board, which displays the state.
+ */
+
+/**
+ * @example pingpair.pde
+ *
+ * This is an example of how to use the RF24 class.  Write this sketch to two
+ * different nodes, connect the role_pin to ground on one.  The ping node sends
+ * the current time to the pong node, which responds by sending the value back.
+ * The ping node can then see how long the whole cycle took.
+ */
+
+/**
+ * @example pingpair_maple.pde 
+ *
+ * This is an example of how to use the RF24 class on the Maple.  For a more
+ * detailed explanation, see my blog post:
+ * nRF24L01+ Running on Maple
+ *
+ * It will communicate well to an Arduino-based unit as well, so it's not for only Maple-to-Maple communication.
+ * 
+ * Write this sketch to two different nodes,
+ * connect the role_pin to ground on one.  The ping node sends the current time to the pong node,
+ * which responds by sending the value back.  The ping node can then see how long the whole cycle
+ * took.
+ */
+
+/**
+ * @example starping.pde
+ *
+ * This sketch is a more complex example of using the RF24 library for Arduino.
+ * Deploy this on up to six nodes.  Set one as the 'pong receiver' by tying the
+ * role_pin low, and the others will be 'ping transmit' units.  The ping units
+ * unit will send out the value of millis() once a second.  The pong unit will
+ * respond back with a copy of the value.  Each ping unit can get that response
+ * back, and determine how long the whole cycle took.
+ *
+ * This example requires a bit more complexity to determine which unit is which.
+ * The pong receiver is identified by having its role_pin tied to ground.
+ * The ping senders are further differentiated by a byte in eeprom.
+ */
+
+/**
+ * @example pingpair_pl.pde
+ *
+ * This is an example of how to do two-way communication without changing
+ * transmit/receive modes.  Here, a payload is set to the transmitter within
+ * the Ack packet of each transmission.  Note that the payload is set BEFORE
+ * the sender's message arrives.
+ */
+
+/**
+ * @example pingpair_irq.pde
+ *
+ * This is an example of how to user interrupts to interact with the radio.
+ * It builds on the pingpair_pl example, and uses ack payloads.
+ */
+
+/**
+ * @example pingpair_sleepy.pde
+ *
+ * This is an example of how to use the RF24 class to create a battery-
+ * efficient system.  It is just like the pingpair.pde example, but the
+ * ping node powers down the radio and sleeps the MCU after every
+ * ping/pong cycle.
+ */
+
+/**
+ * @example scanner.pde
+ *
+ * Example to detect interference on the various channels available.
+ * This is a good diagnostic tool to check whether you're picking a
+ * good channel for your application.
+ *
+ * Inspired by cpixip.
+ * See http://arduino.cc/forum/index.php/topic,54795.0.html
+ */
+
+/**
+ * @mainpage Driver for nRF24L01(+) 2.4GHz Wireless Transceiver
+ *
+ * @section Goals Design Goals
+ * 
+ * This library is designed to be...
+ * @li Maximally compliant with the intended operation of the chip
+ * @li Easy for beginners to use
+ * @li Consumed with a public interface that's similiar to other Arduino standard libraries
+ *
+ * @section News News
+ * 
+ * NOW COMPATIBLE WITH ARDUINO 1.0 - The 'master' branch and all examples work with both Arduino 1.0 and earlier versions.  
+ * Please open an issue if you find any problems using it with any version of Arduino.
+ *
+ * NOW COMPATIBLE WITH MAPLE - RF24 has been tested with the 
+ * Maple Native, 
+ * and should work with any Maple board.  See the pingpair_maple example.
+ * Note that only the pingpair_maple example has been tested on Maple, although
+ * the others can certainly be adapted.
+ *
+ * @section Useful Useful References
+ * 
+ * Please refer to:
+ *
+ * @li Documentation Main Page
+ * @li RF24 Class Documentation
+ * @li Source Code
+ * @li Downloads Page
+ * @li Chip Datasheet
+ *
+ * This chip uses the SPI bus, plus two chip control pins.  Remember that pin 10 must still remain an output, or
+ * the SPI hardware will go into 'slave' mode.
+ *
+ * @section More More Information
+ *
+ * @subpage FAQ
+ *
+ * @section Projects Projects
+ *
+ * Stuff I have built with RF24
+ *
+ * RF24 Getting Started - Finished Product
+ *
+ * Getting Started with nRF24L01+ on Arduino 
+ *
+ * Nordic FOB and nRF24L01+
+ *
+ * Using the Sparkfun Nordic FOB 
+ *
+ * RF Duinode V3 (2V4)
+ *
+ * Low-Power Wireless Sensor Node
+ *
+ * nRF24L01+ connected to Leaf Labs Maple Native
+ *
+ * nRF24L01+ Running on Maple
+ */
+
+#endif // __RF24_H__
+// vim:ai:cin:sts=2 sw=2 ft=cpp
+
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/RF24_config.h b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/RF24_config.h
new file mode 100644
index 0000000..eef0704
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/RF24_config.h
@@ -0,0 +1,34 @@
+
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+  
+ 03/17/2013 : Charles-Henri Hallard (http://hallard.me)
+              Modified to use with Arduipi board http://hallard.me/arduipi
+              Modified to use the great bcm2835 library for I/O and SPI
+							
+ */
+
+#ifndef __RF24_CONFIG_H__
+#define __RF24_CONFIG_H__
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "bcm2835.h"
+
+// GCC a Arduino Missing
+#define max(a,b) (a>b?a:b)
+#define min(a,b) (a
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "./bcm2835.h"
+
+// This define enables a little test program (by default a blinking output on pin RPI_GPIO_PIN_11)
+// You can do some safe, non-destructive testing on any platform with:
+// gcc bcm2835.c -D BCM2835_TEST
+// ./a.out
+//#define BCM2835_TEST
+
+// Pointers to the hardware register bases
+volatile uint32_t *bcm2835_gpio = MAP_FAILED;
+volatile uint32_t *bcm2835_pwm  = MAP_FAILED;
+volatile uint32_t *bcm2835_clk  = MAP_FAILED;
+volatile uint32_t *bcm2835_pads = MAP_FAILED;
+volatile uint32_t *bcm2835_spi0 = MAP_FAILED;
+volatile uint32_t *bcm2835_bsc0 = MAP_FAILED;
+volatile uint32_t *bcm2835_bsc1 = MAP_FAILED;
+volatile uint32_t *bcm2835_st	= MAP_FAILED;
+
+
+// This variable allows us to test on hardware other than RPi.
+// It prevents access to the kernel memory, and does not do any peripheral access
+// Instead it prints out what it _would_ do if debug were 0
+static uint8_t debug = 0;
+
+// I2C The time needed to transmit one byte. In microseconds.
+static int i2c_byte_wait_us = 0;
+
+// SPI Custom Chip Select Pin
+static int spi_custom_cs = 0;
+
+// Time for millis function
+static unsigned long long epoch ;
+
+//
+// Low level register access functions
+//
+
+void  bcm2835_set_debug(uint8_t d)
+{
+    debug = d;
+}
+
+
+// Get raspberry PI model version
+int bcm2835_get_pi_version( void ) 
+{ 
+	int rev = 0;
+	char buff[512];
+	char * p;
+	char * pend;
+	
+	FILE * fd ;
+
+	// do some clean up
+	memset(buff,0,sizeof(buff));
+
+	fd = fopen("/proc/cpuinfo","r");
+
+	// Opened successfully
+	if( fd )
+	{
+		//printf("File opened successfully through fopen()\n");
+		
+		// parse each line until we the end or we find the good one
+		while( fgets(buff, sizeof(buff), fd) != NULL && rev ==0 ) 
+		{
+			// search 
+			if( (strstr(buff, "Revision" )) != NULL )  
+			{
+				// point to the separator ":" format is has follow
+				// Revision        : 000f
+				if ( (p = strtok( buff, ":")) != NULL )
+				{
+					// Ok get value
+					if ( (p = strtok( NULL, ":")) != NULL )
+					{
+						// Revision Version is in hex format so put 0x before the number
+						*p   = 'x';
+						*--p = '0';
+						
+						// convert to number
+						rev = strtol(p, &pend, 16);
+						
+						//printf("rev=%d 0x%04x\n", rev, rev);
+						
+						// not Okay ?
+						if ( !*pend )
+						{
+							rev= 0;
+						}
+						else
+						{
+							// Revision 1 or 2 ?
+							rev = (rev < 4 ) ? 1 : 2 ;
+						}
+					}
+				}
+			}
+		}
+
+		// Close the file.
+		if(fd) 
+		{
+			fclose(fd);
+		}
+	}
+
+	return rev;
+} 
+
+
+
+// safe read from peripheral
+uint32_t bcm2835_peri_read(volatile uint32_t* paddr)
+{
+	uint32_t ret ;
+	uint32_t dummy = 0 ;
+
+	if (debug)
+    {
+        printf("bcm2835_peri_read  paddr %08X\n", (unsigned) paddr);
+	return dummy;
+    }
+    else
+    {
+	// Make sure we dont return the _last_ read which might get lost
+	// if subsequent code changes to a different peripheral
+	ret = *paddr;
+	dummy = *paddr;
+	return ret;
+    }
+}
+
+// read from peripheral without the read barrier
+uint32_t bcm2835_peri_read_nb(volatile uint32_t* paddr)
+{
+    if (debug)
+    {
+	printf("bcm2835_peri_read_nb  paddr %08X\n", (unsigned) paddr);
+	return 0;
+    }
+    else
+    {
+	return *paddr;
+    }
+}
+
+// safe write to peripheral
+void bcm2835_peri_write(volatile uint32_t* paddr, uint32_t value)
+{
+    if (debug)
+    {
+	printf("bcm2835_peri_write paddr %08X, value %08X\n", (unsigned) paddr, value);
+    }
+    else
+    {
+	// Make sure we don't rely on the first write, which may get
+	// lost if the previous access was to a different peripheral.
+	*paddr = value;
+	*paddr = value;
+    }
+}
+
+// write to peripheral without the write barrier
+void bcm2835_peri_write_nb(volatile uint32_t* paddr, uint32_t value)
+{
+    if (debug)
+    {
+	printf("bcm2835_peri_write_nb paddr %08X, value %08X\n",
+               (unsigned) paddr, value);
+    }
+    else
+    {
+	*paddr = value;
+    }
+}
+
+// Set/clear only the bits in value covered by the mask
+void bcm2835_peri_set_bits(volatile uint32_t* paddr, uint32_t value, uint32_t mask)
+{
+    uint32_t v = bcm2835_peri_read(paddr);
+    v = (v & ~mask) | (value & mask);
+    bcm2835_peri_write(paddr, v);
+}
+
+//
+// Low level convenience functions
+//
+
+// Function select
+// pin is a BCM2835 GPIO pin number NOT RPi pin number
+//      There are 6 control registers, each control the functions of a block
+//      of 10 pins.
+//      Each control register has 10 sets of 3 bits per GPIO pin:
+//
+//      000 = GPIO Pin X is an input
+//      001 = GPIO Pin X is an output
+//      100 = GPIO Pin X takes alternate function 0
+//      101 = GPIO Pin X takes alternate function 1
+//      110 = GPIO Pin X takes alternate function 2
+//      111 = GPIO Pin X takes alternate function 3
+//      011 = GPIO Pin X takes alternate function 4
+//      010 = GPIO Pin X takes alternate function 5
+//
+// So the 3 bits for port X are:
+//      X / 10 + ((X % 10) * 3)
+void bcm2835_gpio_fsel(uint8_t pin, uint8_t mode)
+{
+    // Function selects are 10 pins per 32 bit word, 3 bits per pin
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPFSEL0/4 + (pin/10);
+    uint8_t   shift = (pin % 10) * 3;
+    uint32_t  mask = BCM2835_GPIO_FSEL_MASK << shift;
+    uint32_t  value = mode << shift;
+    bcm2835_peri_set_bits(paddr, value, mask);
+}
+
+// Set output pin
+void bcm2835_gpio_set(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPSET0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    bcm2835_peri_write(paddr, 1 << shift);
+}
+
+// Clear output pin
+void bcm2835_gpio_clr(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPCLR0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    bcm2835_peri_write(paddr, 1 << shift);
+}
+
+// Set all output pins in the mask
+void bcm2835_gpio_set_multi(uint32_t mask)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPSET0/4;
+    bcm2835_peri_write(paddr, mask);
+}
+
+// Clear all output pins in the mask
+void bcm2835_gpio_clr_multi(uint32_t mask)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPCLR0/4;
+    bcm2835_peri_write(paddr, mask);
+}
+
+// Read input pin
+uint8_t bcm2835_gpio_lev(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPLEV0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = bcm2835_peri_read(paddr);
+    return (value & (1 << shift)) ? HIGH : LOW;
+}
+
+// See if an event detection bit is set
+// Sigh cant support interrupts yet
+uint8_t bcm2835_gpio_eds(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPEDS0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = bcm2835_peri_read(paddr);
+    return (value & (1 << shift)) ? HIGH : LOW;
+}
+
+// Write a 1 to clear the bit in EDS
+void bcm2835_gpio_set_eds(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPEDS0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = 1 << shift;
+    bcm2835_peri_write(paddr, value);
+}
+
+// Rising edge detect enable
+void bcm2835_gpio_ren(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPREN0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = 1 << shift;
+    bcm2835_peri_set_bits(paddr, value, value);
+}
+void bcm2835_gpio_clr_ren(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPREN0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = 1 << shift;
+    bcm2835_peri_set_bits(paddr, 0, value);
+}
+
+// Falling edge detect enable
+void bcm2835_gpio_fen(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPFEN0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = 1 << shift;
+    bcm2835_peri_set_bits(paddr, value, value);
+}
+void bcm2835_gpio_clr_fen(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPFEN0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = 1 << shift;
+    bcm2835_peri_set_bits(paddr, 0, value);
+}
+
+// High detect enable
+void bcm2835_gpio_hen(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPHEN0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = 1 << shift;
+    bcm2835_peri_set_bits(paddr, value, value);
+}
+void bcm2835_gpio_clr_hen(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPHEN0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = 1 << shift;
+    bcm2835_peri_set_bits(paddr, 0, value);
+}
+
+// Low detect enable
+void bcm2835_gpio_len(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPLEN0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = 1 << shift;
+    bcm2835_peri_set_bits(paddr, value, value);
+}
+void bcm2835_gpio_clr_len(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPLEN0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = 1 << shift;
+    bcm2835_peri_set_bits(paddr, 0, value);
+}
+
+// Async rising edge detect enable
+void bcm2835_gpio_aren(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPAREN0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = 1 << shift;
+    bcm2835_peri_set_bits(paddr, value, value);
+}
+void bcm2835_gpio_clr_aren(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPAREN0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = 1 << shift;
+    bcm2835_peri_set_bits(paddr, 0, value);
+}
+
+// Async falling edge detect enable
+void bcm2835_gpio_afen(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPAFEN0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = 1 << shift;
+    bcm2835_peri_set_bits(paddr, value, value);
+}
+void bcm2835_gpio_clr_afen(uint8_t pin)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPAFEN0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    uint32_t value = 1 << shift;
+    bcm2835_peri_set_bits(paddr, 0, value);
+}
+
+// Set pullup/down
+void bcm2835_gpio_pud(uint8_t pud)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPPUD/4;
+    bcm2835_peri_write(paddr, pud);
+}
+
+// Pullup/down clock
+// Clocks the value of pud into the GPIO pin
+void bcm2835_gpio_pudclk(uint8_t pin, uint8_t on)
+{
+    volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPPUDCLK0/4 + pin/32;
+    uint8_t shift = pin % 32;
+    bcm2835_peri_write(paddr, (on ? 1 : 0) << shift);
+}
+
+// Read GPIO pad behaviour for groups of GPIOs
+uint32_t bcm2835_gpio_pad(uint8_t group)
+{
+    volatile uint32_t* paddr = bcm2835_pads + BCM2835_PADS_GPIO_0_27/4 + group*2;
+    return bcm2835_peri_read(paddr);
+}
+
+// Set GPIO pad behaviour for groups of GPIOs
+// powerup value for al pads is
+// BCM2835_PAD_SLEW_RATE_UNLIMITED | BCM2835_PAD_HYSTERESIS_ENABLED | BCM2835_PAD_DRIVE_8mA
+void bcm2835_gpio_set_pad(uint8_t group, uint32_t control)
+{
+    volatile uint32_t* paddr = bcm2835_pads + BCM2835_PADS_GPIO_0_27/4 + group*2;
+    bcm2835_peri_write(paddr, control);
+}
+
+// Some convenient arduino-like functions
+// milliseconds
+void bcm2835_delay(unsigned int millis)
+{
+    struct timespec sleeper;
+    
+    sleeper.tv_sec  = (time_t)(millis / 1000);
+    sleeper.tv_nsec = (long)(millis % 1000) * 1000000;
+    nanosleep(&sleeper, NULL);
+}
+
+// microseconds
+void bcm2835_delayMicroseconds(uint64_t micros)
+{
+    struct timespec t1;
+    uint64_t        start;
+	
+    // Calling nanosleep() takes at least 100-200 us, so use it for
+    // long waits and use a busy wait on the System Timer for the rest.
+    start =  bcm2835_st_read();
+    
+    if (micros > 450)
+    {
+	t1.tv_sec = 0;
+	t1.tv_nsec = 1000 * (long)(micros - 200);
+	nanosleep(&t1, NULL);
+    }    
+  
+    bcm2835_st_delay(start, micros);
+}
+
+// This function is added in order to simulate arduino millis() function
+unsigned int bcm2835_millis(void)
+{
+	struct timeval now;
+	unsigned long long ms;    
+	
+	gettimeofday(&now, NULL);
+	
+	ms = (now.tv_sec * 1000000 + now.tv_usec) / 1000 ;
+	
+	return ((uint32_t) (ms - epoch ));
+}
+
+//
+// Higher level convenience functions
+//
+
+// Set the state of an output
+void bcm2835_gpio_write(uint8_t pin, uint8_t on)
+{
+    if (on)
+	bcm2835_gpio_set(pin);
+    else
+	bcm2835_gpio_clr(pin);
+}
+
+// Set the state of a all 32 outputs in the mask to on or off
+void bcm2835_gpio_write_multi(uint32_t mask, uint8_t on)
+{
+    if (on)
+	bcm2835_gpio_set_multi(mask);
+    else
+	bcm2835_gpio_clr_multi(mask);
+}
+
+// Set the state of a all 32 outputs in the mask to the values in value
+void bcm2835_gpio_write_mask(uint32_t value, uint32_t mask)
+{
+    bcm2835_gpio_set_multi(value & mask);
+    bcm2835_gpio_clr_multi((~value) & mask);
+}
+
+// Set the pullup/down resistor for a pin
+//
+// The GPIO Pull-up/down Clock Registers control the actuation of internal pull-downs on
+// the respective GPIO pins. These registers must be used in conjunction with the GPPUD
+// register to effect GPIO Pull-up/down changes. The following sequence of events is
+// required:
+// 1. Write to GPPUD to set the required control signal (i.e. Pull-up or Pull-Down or neither
+// to remove the current Pull-up/down)
+// 2. Wait 150 cycles ? this provides the required set-up time for the control signal
+// 3. Write to GPPUDCLK0/1 to clock the control signal into the GPIO pads you wish to
+// modify ? NOTE only the pads which receive a clock will be modified, all others will
+// retain their previous state.
+// 4. Wait 150 cycles ? this provides the required hold time for the control signal
+// 5. Write to GPPUD to remove the control signal
+// 6. Write to GPPUDCLK0/1 to remove the clock
+//
+// RPi has P1-03 and P1-05 with 1k8 pullup resistor
+void bcm2835_gpio_set_pud(uint8_t pin, uint8_t pud)
+{
+    bcm2835_gpio_pud(pud);
+    delayMicroseconds(10);
+    bcm2835_gpio_pudclk(pin, 1);
+    delayMicroseconds(10);
+    bcm2835_gpio_pud(BCM2835_GPIO_PUD_OFF);
+    bcm2835_gpio_pudclk(pin, 0);
+}
+
+void bcm2835_spi_begin(uint8_t cs)
+{
+    volatile uint32_t* paddr = bcm2835_spi0 + BCM2835_SPI0_CS/4;
+
+    // Set the SPI0 pins to the Alt 0 function to enable SPI0 access on them
+		// except if we need custom Chip Select Pin 
+		// printf("bcm2835_spi_begin -> spi_custom_cs = %d \n",cs );
+		
+		// Do we need custom chip select control or 
+		// drive CE1 manually (because CE1 does not work with hardware) 
+		if ( cs > BCM2835_SPI_CS_NONE || cs == BCM2835_SPI_CS1 )
+		{
+			// indicate we will use a custom GPIO port
+			spi_custom_cs = cs ;
+
+			// ok hard CE1 not working, drive it manually
+			if (cs == BCM2835_SPI_CS1 )
+			{
+				// Dirty Hack CE1 in now custom Chip Select GPIO 26
+				// the real CE1 pin
+				spi_custom_cs = RPI_GPIO_P1_26 ; 
+				
+				bcm2835_gpio_fsel(spi_custom_cs, BCM2835_GPIO_FSEL_OUTP); 
+				bcm2835_gpio_write(spi_custom_cs, HIGH);
+			}
+
+			// Mask in we use custom CS (not sure it has a real effect)
+			bcm2835_peri_set_bits(paddr, BCM2835_SPI_CS_NONE, BCM2835_SPI0_CS_CS);
+		}
+		// Ok hardware driving of chip select
+		else
+		{
+			// Just in case
+			spi_custom_cs = 0 ;
+			
+			// Mask in the CS bits of CS
+			bcm2835_peri_set_bits(paddr, cs, BCM2835_SPI0_CS_CS);
+		}		
+		
+		// Now we can drive the I/O as asked 
+		if (spi_custom_cs == 0)
+		{
+			// Not custom CS, so hardware driven
+			bcm2835_gpio_fsel(RPI_GPIO_P1_24, BCM2835_GPIO_FSEL_ALT0); // CE0 
+			bcm2835_gpio_fsel(RPI_GPIO_P1_26, BCM2835_GPIO_FSEL_ALT0); // CE1 
+		}
+		else
+		{
+			// so set custom CS as output, High level by default
+			bcm2835_gpio_fsel(spi_custom_cs, BCM2835_GPIO_FSEL_OUTP); // Custom GPIO
+			bcm2835_gpio_write(spi_custom_cs, HIGH);
+		}
+		
+		// Classic pin, hardware driven
+    bcm2835_gpio_fsel(RPI_GPIO_P1_21, BCM2835_GPIO_FSEL_ALT0); // MISO
+    bcm2835_gpio_fsel(RPI_GPIO_P1_19, BCM2835_GPIO_FSEL_ALT0); // MOSI
+    bcm2835_gpio_fsel(RPI_GPIO_P1_23, BCM2835_GPIO_FSEL_ALT0); // CLK
+    
+    // Set the SPI CS register to the some sensible defaults
+    bcm2835_peri_write(paddr, 0); // All 0s
+    
+    // Clear TX and RX fifos
+    bcm2835_peri_write_nb(paddr, BCM2835_SPI0_CS_CLEAR);
+}
+
+void bcm2835_spi_end(void)
+{  
+    // Set all the SPI0 pins back to input
+		if (spi_custom_cs == 0)
+		{
+			bcm2835_gpio_fsel(RPI_GPIO_P1_26, BCM2835_GPIO_FSEL_INPT); // CE1
+			bcm2835_gpio_fsel(RPI_GPIO_P1_24, BCM2835_GPIO_FSEL_INPT); // CE0
+		}
+		else
+		{
+			bcm2835_gpio_fsel(spi_custom_cs, BCM2835_GPIO_FSEL_INPT); // Custom GPIO
+		}
+    bcm2835_gpio_fsel(RPI_GPIO_P1_21, BCM2835_GPIO_FSEL_INPT); // MISO
+    bcm2835_gpio_fsel(RPI_GPIO_P1_19, BCM2835_GPIO_FSEL_INPT); // MOSI
+    bcm2835_gpio_fsel(RPI_GPIO_P1_23, BCM2835_GPIO_FSEL_INPT); // CLK
+}
+
+
+// Drive Custom chip select pin
+void bcm2835_spi_setChipSelect(uint8_t level)
+{
+	// Do this only if we are using custom ChipSelect I/O
+	if ( spi_custom_cs > BCM2835_SPI_CS_NONE )
+		bcm2835_gpio_write(spi_custom_cs, level);
+}
+
+
+void bcm2835_spi_setBitOrder(uint8_t order)
+{
+    // BCM2835_SPI_BIT_ORDER_MSBFIRST is the only one suported by SPI0
+}
+
+// defaults to 0, which means a divider of 65536.
+// The divisor must be a power of 2. Odd numbers
+// rounded down. The maximum SPI clock rate is
+// of the APB clock
+void bcm2835_spi_setClockDivider(uint16_t divider)
+{
+    volatile uint32_t* paddr = bcm2835_spi0 + BCM2835_SPI0_CLK/4;
+    bcm2835_peri_write(paddr, divider);
+}
+
+void bcm2835_spi_setClockSpeed(uint16_t speed)
+{
+    bcm2835_spi_setClockDivider( speed);
+}
+
+void bcm2835_spi_setDataMode(uint8_t mode)
+{
+    volatile uint32_t* paddr = bcm2835_spi0 + BCM2835_SPI0_CS/4;
+    // Mask in the CPO and CPHA bits of CS
+    bcm2835_peri_set_bits(paddr, mode << 2, BCM2835_SPI0_CS_CPOL | BCM2835_SPI0_CS_CPHA);
+}
+
+// Writes (and reads) a single byte to SPI
+uint8_t bcm2835_spi_transfer(uint8_t value)
+{
+    volatile uint32_t* paddr = bcm2835_spi0 + BCM2835_SPI0_CS/4;
+    volatile uint32_t* fifo = bcm2835_spi0 + BCM2835_SPI0_FIFO/4;
+
+		// Custom chip select LOW
+		bcm2835_spi_setChipSelect(LOW);
+
+    // This is Polled transfer as per section 10.6.1
+    // BUG ALERT: what happens if we get interupted in this section, and someone else
+    // accesses a different peripheral? 
+    // Clear TX and RX fifos
+    bcm2835_peri_set_bits(paddr, BCM2835_SPI0_CS_CLEAR, BCM2835_SPI0_CS_CLEAR);
+
+    // Set TA = 1
+    bcm2835_peri_set_bits(paddr, BCM2835_SPI0_CS_TA, BCM2835_SPI0_CS_TA);
+
+    // Maybe wait for TXD
+    while (!(bcm2835_peri_read(paddr) & BCM2835_SPI0_CS_TXD))
+	delayMicroseconds(10);
+
+    // Write to FIFO, no barrier
+    bcm2835_peri_write_nb(fifo, value);
+
+    // Wait for DONE to be set
+    while (!(bcm2835_peri_read_nb(paddr) & BCM2835_SPI0_CS_DONE))
+	delayMicroseconds(10);
+
+    // Read any byte that was sent back by the slave while we sere sending to it
+    uint32_t ret = bcm2835_peri_read_nb(fifo);
+
+    // Set TA = 0, and also set the barrier
+    bcm2835_peri_set_bits(paddr, 0, BCM2835_SPI0_CS_TA);
+
+		// Custom chip select HIGH
+		bcm2835_spi_setChipSelect(HIGH);
+
+    return ret;
+}
+
+// Writes (and reads) an number of bytes to SPI
+void bcm2835_spi_transfernb(char* tbuf, char* rbuf, uint32_t len)
+{
+    volatile uint32_t* paddr = bcm2835_spi0 + BCM2835_SPI0_CS/4;
+    volatile uint32_t* fifo = bcm2835_spi0 + BCM2835_SPI0_FIFO/4;
+
+		// Custom chip select LOW
+		bcm2835_spi_setChipSelect(LOW);
+
+    // This is Polled transfer as per section 10.6.1
+    // BUG ALERT: what happens if we get interupted in this section, and someone else
+    // accesses a different peripheral? 
+
+    // Clear TX and RX fifos
+    bcm2835_peri_set_bits(paddr, BCM2835_SPI0_CS_CLEAR, BCM2835_SPI0_CS_CLEAR);
+
+    // Set TA = 1
+    bcm2835_peri_set_bits(paddr, BCM2835_SPI0_CS_TA, BCM2835_SPI0_CS_TA);
+
+    uint32_t i;
+    for (i = 0; i < len; i++)
+    {
+	// Maybe wait for TXD
+	while (!(bcm2835_peri_read(paddr) & BCM2835_SPI0_CS_TXD))
+	    delayMicroseconds(10);
+
+	// Write to FIFO, no barrier
+	bcm2835_peri_write_nb(fifo, tbuf[i]);
+
+	// Wait for RXD
+	while (!(bcm2835_peri_read(paddr) & BCM2835_SPI0_CS_RXD))
+	    delayMicroseconds(10);
+
+	// then read the data byte
+	rbuf[i] = bcm2835_peri_read_nb(fifo);
+    }
+    // Wait for DONE to be set
+    while (!(bcm2835_peri_read_nb(paddr) & BCM2835_SPI0_CS_DONE))
+	delayMicroseconds(10);
+
+    // Set TA = 0, and also set the barrier
+    bcm2835_peri_set_bits(paddr, 0, BCM2835_SPI0_CS_TA);
+
+		// Custom chip select HIGH
+		bcm2835_spi_setChipSelect(HIGH);
+	
+}
+
+// Writes an number of bytes to SPI
+void bcm2835_spi_writenb(char* tbuf, uint32_t len)
+{
+    volatile uint32_t* paddr = bcm2835_spi0 + BCM2835_SPI0_CS/4;
+    volatile uint32_t* fifo = bcm2835_spi0 + BCM2835_SPI0_FIFO/4;
+
+		// Custom chip select LOW
+		bcm2835_spi_setChipSelect(LOW);
+
+    // This is Polled transfer as per section 10.6.1
+    // BUG ALERT: what happens if we get interupted in this section, and someone else
+    // accesses a different peripheral?
+
+    // Clear TX and RX fifos
+    bcm2835_peri_set_bits(paddr, BCM2835_SPI0_CS_CLEAR, BCM2835_SPI0_CS_CLEAR);
+
+    // Set TA = 1
+    bcm2835_peri_set_bits(paddr, BCM2835_SPI0_CS_TA, BCM2835_SPI0_CS_TA);
+
+    uint32_t i;
+	for (i = 0; i < len; i++)
+	{
+		// Maybe wait for TXD
+		while (!(bcm2835_peri_read(paddr) & BCM2835_SPI0_CS_TXD))
+			;
+
+		// Write to FIFO, no barrier
+		bcm2835_peri_write_nb(fifo, tbuf[i]);
+	}
+
+    // Wait for DONE to be set
+    while (!(bcm2835_peri_read_nb(paddr) & BCM2835_SPI0_CS_DONE))
+    	;
+
+    // Set TA = 0, and also set the barrier
+    bcm2835_peri_set_bits(paddr, 0, BCM2835_SPI0_CS_TA);
+
+		// Custom chip select HIGH
+		bcm2835_spi_setChipSelect(HIGH);
+}
+
+// Writes (and reads) an number of bytes to SPI
+// Read bytes are copied over onto the transmit buffer
+void bcm2835_spi_transfern(char* buf, uint32_t len)
+{
+    bcm2835_spi_transfernb(buf, buf, len);
+}
+
+void bcm2835_spi_chipSelect(uint8_t cs)
+{
+	// All is done now in bcm2835_spi_begin()
+
+}
+
+void bcm2835_spi_setChipSelectPolarity(uint8_t cs, uint8_t active)
+{
+    volatile uint32_t* paddr = bcm2835_spi0 + BCM2835_SPI0_CS/4;
+
+		// only valid for no custom CS
+		if (cs <= BCM2835_SPI_CS_NONE)
+		{
+			uint8_t shift = 21 + cs;
+			
+			// Mask in the appropriate CSPOLn bit
+			bcm2835_peri_set_bits(paddr, active << shift, 1 << shift);
+		}
+}
+
+void bcm2835_i2c_begin(void)
+{
+	volatile uint32_t* paddr = bcm2835_bsc1 + BCM2835_BSC_DIV/4;
+
+    // Set the I2C/BSC1 pins to the Alt 0 function to enable I2C access on them
+    bcm2835_gpio_fsel(RPI_V2_GPIO_P1_03, BCM2835_GPIO_FSEL_ALT0); // SDA
+    bcm2835_gpio_fsel(RPI_V2_GPIO_P1_05, BCM2835_GPIO_FSEL_ALT0); // SCL
+
+    // Read the clock divider register
+    uint16_t cdiv = bcm2835_peri_read(paddr);
+    // Calculate time for transmitting one byte
+    // 1000000 = micros seconds in a second
+    // 9 = Clocks per byte : 8 bits + ACK
+    i2c_byte_wait_us = ((float)cdiv / BCM2835_CORE_CLK_HZ) * 1000000 * 9;
+}
+
+void bcm2835_i2c_end(void)
+{
+    // Set all the I2C/BSC1 pins back to input
+    bcm2835_gpio_fsel(RPI_V2_GPIO_P1_03, BCM2835_GPIO_FSEL_INPT); // SDA
+    bcm2835_gpio_fsel(RPI_V2_GPIO_P1_05, BCM2835_GPIO_FSEL_INPT); // SCL
+}
+
+void bcm2835_i2c_setSlaveAddress(uint8_t addr)
+{
+	// Set I2C Device Address
+	volatile uint32_t* paddr = bcm2835_bsc1 + BCM2835_BSC_A/4;
+	bcm2835_peri_write(paddr, addr);
+}
+
+// defaults to 0x5dc, should result in a 166.666 kHz I2C clock frequency.
+// The divisor must be a power of 2. Odd numbers
+// rounded down.
+void bcm2835_i2c_setClockDivider(uint16_t divider)
+{
+    volatile uint32_t* paddr = bcm2835_bsc1 + BCM2835_BSC_DIV/4;
+    bcm2835_peri_write(paddr, divider);
+    // Calculate time for transmitting one byte
+    // 1000000 = micros seconds in a second
+    // 9 = Clocks per byte : 8 bits + ACK
+    i2c_byte_wait_us = ((float)divider / BCM2835_CORE_CLK_HZ) * 1000000 * 9;
+}
+
+// Writes an number of bytes to I2C
+uint8_t bcm2835_i2c_write(const char * buf, uint32_t len)
+{
+    volatile uint32_t* dlen    = bcm2835_bsc1 + BCM2835_BSC_DLEN/4;
+    volatile uint32_t* fifo    = bcm2835_bsc1 + BCM2835_BSC_FIFO/4;
+    volatile uint32_t* status  = bcm2835_bsc1 + BCM2835_BSC_S/4;
+    volatile uint32_t* control = bcm2835_bsc1 + BCM2835_BSC_C/4;
+
+    uint32_t remaining = len;
+    uint32_t i = 0;
+    uint8_t reason = BCM2835_I2C_REASON_OK;
+
+    // Clear FIFO
+    bcm2835_peri_set_bits(control, BCM2835_BSC_C_CLEAR_1 , BCM2835_BSC_C_CLEAR_1 );
+    // Clear Status
+	bcm2835_peri_write_nb(status, BCM2835_BSC_S_CLKT | BCM2835_BSC_S_ERR | BCM2835_BSC_S_DONE);
+	// Set Data Length
+    bcm2835_peri_write_nb(dlen, len);
+    // Enable device and start transfer
+    bcm2835_peri_write_nb(control, BCM2835_BSC_C_I2CEN | BCM2835_BSC_C_ST);
+
+    while (!(bcm2835_peri_read(status) & BCM2835_BSC_S_DONE))
+    {
+    	while ((bcm2835_peri_read(status) & BCM2835_BSC_S_TXD) && remaining)
+    	{
+        	// Write to FIFO, no barrier
+        	bcm2835_peri_write_nb(fifo, buf[i]);
+        	i++;
+        	remaining--;
+    	}
+    	// When remaining data is to be send, then wait for an empty FIFO
+    	if (remaining >= BCM2835_BSC_FIFO_SIZE)
+    		delayMicroseconds(i2c_byte_wait_us * BCM2835_BSC_FIFO_SIZE);
+    	else
+    		delayMicroseconds(i2c_byte_wait_us * remaining);
+    }
+
+    // Received a NACK
+    if (bcm2835_peri_read(status) & BCM2835_BSC_S_ERR)
+    {
+		reason = BCM2835_I2C_REASON_ERROR_NACK;
+    }
+
+    // Received Clock Stretch Timeout
+    else if (bcm2835_peri_read(status) & BCM2835_BSC_S_CLKT)
+    {
+		reason = BCM2835_I2C_REASON_ERROR_CLKT;
+    }
+
+    // Not all data is sent
+    else if (remaining)
+    {
+		reason = BCM2835_I2C_REASON_ERROR_DATA;
+    }
+
+    bcm2835_peri_set_bits(control, BCM2835_BSC_S_DONE , BCM2835_BSC_S_DONE);
+
+    return reason;
+}
+
+// Read an number of bytes from I2C
+uint8_t bcm2835_i2c_read(char* buf, uint32_t len)
+{
+    volatile uint32_t* dlen    = bcm2835_bsc1 + BCM2835_BSC_DLEN/4;
+    volatile uint32_t* fifo    = bcm2835_bsc1 + BCM2835_BSC_FIFO/4;
+    volatile uint32_t* status  = bcm2835_bsc1 + BCM2835_BSC_S/4;
+    volatile uint32_t* control = bcm2835_bsc1 + BCM2835_BSC_C/4;
+
+    uint32_t remaining = len;
+    uint32_t i = 0;
+    uint8_t reason = BCM2835_I2C_REASON_OK;
+
+    // Clear FIFO
+    bcm2835_peri_set_bits(control, BCM2835_BSC_C_CLEAR_1 , BCM2835_BSC_C_CLEAR_1 );
+    // Clear Status
+	bcm2835_peri_write_nb(status, BCM2835_BSC_S_CLKT | BCM2835_BSC_S_ERR | BCM2835_BSC_S_DONE);
+	// Set Data Length
+    bcm2835_peri_write_nb(dlen, len);
+
+    // Start read
+    bcm2835_peri_write_nb(control, BCM2835_BSC_C_I2CEN | BCM2835_BSC_C_ST | BCM2835_BSC_C_READ);
+
+    while (!(bcm2835_peri_read(status) & BCM2835_BSC_S_DONE))
+    {
+    	while (bcm2835_peri_read(status) & BCM2835_BSC_S_RXD)
+    	{
+    		// Read from FIFO, no barrier
+    		buf[i] = bcm2835_peri_read_nb(fifo);
+        	i++;
+        	remaining--;
+    	}
+    	// When remaining data is to be received, then wait for a fully FIFO
+    	if (remaining >= BCM2835_BSC_FIFO_SIZE)
+    		delayMicroseconds(i2c_byte_wait_us * BCM2835_BSC_FIFO_SIZE);
+    	else
+    		delayMicroseconds(i2c_byte_wait_us * remaining);
+    }
+
+    // Received a NACK
+    if (bcm2835_peri_read(status) & BCM2835_BSC_S_ERR)
+    {
+		reason = BCM2835_I2C_REASON_ERROR_NACK;
+    }
+
+    // Received Clock Stretch Timeout
+    else if (bcm2835_peri_read(status) & BCM2835_BSC_S_CLKT)
+    {
+		reason = BCM2835_I2C_REASON_ERROR_CLKT;
+    }
+
+    // Not all data is received
+    else if (remaining)
+    {
+		reason = BCM2835_I2C_REASON_ERROR_DATA;
+    }
+
+    bcm2835_peri_set_bits(control, BCM2835_BSC_S_DONE , BCM2835_BSC_S_DONE);
+
+    return reason;
+}
+
+// Read the System Timer Counter (64-bits)
+uint64_t bcm2835_st_read(void)
+{
+    volatile uint32_t* paddr;
+    uint64_t st;
+    paddr = bcm2835_st + BCM2835_ST_CHI/4;
+    st = bcm2835_peri_read(paddr);
+    st <<= 32;
+    paddr = bcm2835_st + BCM2835_ST_CLO/4;
+    st += bcm2835_peri_read(paddr);
+    return st;
+}
+
+// Delays for the specified number of microseconds with offset
+void bcm2835_st_delay(uint64_t offset_micros, uint64_t micros)
+{
+    uint64_t compare = offset_micros + micros;
+
+    while(bcm2835_st_read() < compare)
+	;
+}
+
+// Allocate page-aligned memory.
+void *malloc_aligned(size_t size)
+{
+    void *mem;
+    errno = posix_memalign(&mem, BCM2835_PAGE_SIZE, size);
+    return (errno ? NULL : mem);
+}
+
+// Map 'size' bytes starting at 'off' in file 'fd' to memory.
+// Return mapped address on success, MAP_FAILED otherwise.
+// On error print message.
+static void *mapmem(const char *msg, size_t size, int fd, off_t off)
+{
+    void *map = mmap(NULL, size, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, off);
+    if (MAP_FAILED == map)
+	fprintf(stderr, "bcm2835_init: %s mmap failed: %s\n", msg, strerror(errno));
+    return map;
+}
+
+static void unmapmem(void **pmem, size_t size)
+{
+    if (*pmem == MAP_FAILED) return;
+    munmap(*pmem, size);
+    *pmem = MAP_FAILED;
+}
+
+// Initialise this library.
+int bcm2835_init(void)
+{
+	struct timeval tv ;
+	
+    if (debug) 
+    {
+	bcm2835_pads = (uint32_t*)BCM2835_GPIO_PADS;
+	bcm2835_clk = (uint32_t*)BCM2835_CLOCK_BASE;
+	bcm2835_gpio = (uint32_t*)BCM2835_GPIO_BASE;
+	bcm2835_pwm = (uint32_t*)BCM2835_GPIO_PWM;
+	bcm2835_spi0 = (uint32_t*)BCM2835_SPI0_BASE;
+	bcm2835_bsc0 = (uint32_t*)BCM2835_BSC0_BASE;
+	bcm2835_bsc1 = (uint32_t*)BCM2835_BSC1_BASE;
+	bcm2835_st   = (uint32_t*)BCM2835_ST_BASE;
+	return 1; // Success
+    }
+    int memfd = -1;
+    int ok = 0;
+    // Open the master /dev/memory device
+    if ((memfd = open("/dev/mem", O_RDWR | O_SYNC) ) < 0) 
+    {
+	fprintf(stderr, "bcm2835_init: Unable to open /dev/mem: %s\n",
+		strerror(errno)) ;
+	goto exit;
+    }
+	
+    // GPIO:
+    bcm2835_gpio = mapmem("gpio", BCM2835_BLOCK_SIZE, memfd, BCM2835_GPIO_BASE);
+    if (bcm2835_gpio == MAP_FAILED) goto exit;
+
+    // PWM
+    bcm2835_pwm = mapmem("pwm", BCM2835_BLOCK_SIZE, memfd, BCM2835_GPIO_PWM);
+    if (bcm2835_pwm == MAP_FAILED) goto exit;
+
+    // Clock control (needed for PWM)
+    bcm2835_clk = mapmem("clk", BCM2835_BLOCK_SIZE, memfd, BCM2835_CLOCK_BASE);
+    if (bcm2835_clk == MAP_FAILED) goto exit;
+    
+    bcm2835_pads = mapmem("pads", BCM2835_BLOCK_SIZE, memfd, BCM2835_GPIO_PADS);
+    if (bcm2835_pads == MAP_FAILED) goto exit;
+    
+    bcm2835_spi0 = mapmem("spi0", BCM2835_BLOCK_SIZE, memfd, BCM2835_SPI0_BASE);
+    if (bcm2835_spi0 == MAP_FAILED) goto exit;
+
+    // I2C
+    bcm2835_bsc0 = mapmem("bsc0", BCM2835_BLOCK_SIZE, memfd, BCM2835_BSC0_BASE);
+    if (bcm2835_bsc0 == MAP_FAILED) goto exit;
+
+    bcm2835_bsc1 = mapmem("bsc1", BCM2835_BLOCK_SIZE, memfd, BCM2835_BSC1_BASE);
+    if (bcm2835_bsc1 == MAP_FAILED) goto exit;
+
+    // ST
+    bcm2835_st = mapmem("st", BCM2835_BLOCK_SIZE, memfd, BCM2835_ST_BASE);
+    if (bcm2835_st == MAP_FAILED) goto exit;
+
+    ok = 1;
+
+exit:
+    if (memfd >= 0)
+        close(memfd);
+
+    if (!ok)
+	bcm2835_close();
+	
+  gettimeofday (&tv, NULL) ;
+	epoch = (tv.tv_sec * 1000000 + tv.tv_usec) / 1000 ;
+
+    return ok;
+}
+
+// Close this library and deallocate everything
+int bcm2835_close(void)
+{
+    if (debug) return 1; // Success
+    unmapmem((void**) &bcm2835_gpio, BCM2835_BLOCK_SIZE);
+    unmapmem((void**) &bcm2835_pwm,  BCM2835_BLOCK_SIZE);
+    unmapmem((void**) &bcm2835_clk,  BCM2835_BLOCK_SIZE);
+    unmapmem((void**) &bcm2835_spi0, BCM2835_BLOCK_SIZE);
+    unmapmem((void**) &bcm2835_bsc0, BCM2835_BLOCK_SIZE);
+    unmapmem((void**) &bcm2835_bsc1, BCM2835_BLOCK_SIZE);
+    unmapmem((void**) &bcm2835_st,   BCM2835_BLOCK_SIZE);
+    return 1; // Success
+}    
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/bcm2835.h b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/bcm2835.h
new file mode 100644
index 0000000..b11c001
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/bcm2835.h
@@ -0,0 +1,1169 @@
+// bcm2835.h
+//
+// C and C++ support for Broadcom BCM 2835 as used in Raspberry Pi
+//
+// Author: Mike McCauley
+// Copyright (C) 2011-2013 Mike McCauley
+// $Id: bcm2835.h,v 1.8 2013/02/15 22:06:09 mikem Exp mikem $
+//
+// 03/17/2013 : Charles-Henri Hallard (http://hallard.me)
+//              Modified Adding some fonctionnalities
+//							Added millis() function
+//              Added option to use custom Chip Select Pin PI GPIO instead of only CE0 CE1
+//              Done a hack to use CE1 by software as custom CS pin because HW does not work
+//              Added function to determine PI revision board
+//							Added function to set SPI speed (instead of divider for easier look in code)
+
+//
+/// \mainpage C library for Broadcom BCM 2835 as used in Raspberry Pi
+///
+/// This is a C library for Raspberry Pi (RPi). It provides access to 
+/// GPIO and other IO functions on the Broadcom BCM 2835 chip,
+/// allowing access to the GPIO pins on the
+/// 26 pin IDE plug on the RPi board so you can control and interface with various external devices.
+///
+/// It provides functions for reading digital inputs and setting digital outputs, using SPI and I2C,
+/// and for accessing the system timers.
+/// Pin event detection is supported by polling (interrupts are not supported).
+///
+/// It is C++ compatible, and installs as a header file and non-shared library on 
+/// any Linux-based distro (but clearly is no use except on Raspberry Pi or another board with 
+/// BCM 2835).
+///
+/// The version of the package that this documentation refers to can be downloaded 
+/// from http://www.open.com.au/mikem/bcm2835/bcm2835-1.22.tar.gz
+/// You can find the latest version at http://www.open.com.au/mikem/bcm2835
+///
+/// Several example programs are provided.
+///
+/// Based on data in http://elinux.org/RPi_Low-level_peripherals and 
+/// http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
+/// and http://www.scribd.com/doc/101830961/GPIO-Pads-Control2
+///
+/// You can also find online help and discussion at http://groups.google.com/group/bcm2835
+/// Please use that group for all questions and discussions on this topic. 
+/// Do not contact the author directly, unless it is to discuss commercial licensing.
+///
+/// Tested on debian6-19-04-2012, 2012-07-15-wheezy-raspbian and Occidentalisv01
+/// CAUTION: it has been observed that when detect enables such as bcm2835_gpio_len() 
+/// are used and the pin is pulled LOW
+/// it can cause temporary hangs on 2012-07-15-wheezy-raspbian and Occidentalisv01.
+/// Reason for this is not yet determined, but suspect that an interrupt handler is
+/// hitting a hard loop on those OSs.
+/// If you must use bcm2835_gpio_len() and friends, make sure you disable the pins with 
+/// bcm2835_gpio_cler_len() and friends after use. 
+///
+/// \par Installation
+///
+/// This library consists of a single non-shared library and header file, which will be
+/// installed in the usual places by make install
+///
+/// \code
+/// # download the latest version of the library, say bcm2835-1.xx.tar.gz, then:
+/// tar zxvf bcm2835-1.xx.tar.gz
+/// cd bcm2835-1.xx
+/// ./configure
+/// make
+/// sudo make check
+/// sudo make install
+/// \endcode
+///
+/// \par Physical Addresses
+///
+/// The functions bcm2835_peri_read(), bcm2835_peri_write() and bcm2835_peri_set_bits() 
+/// are low level peripheral register access functions. They are designed to use
+/// physical addresses as described in section 1.2.3 ARM physical addresses
+/// of the BCM2835 ARM Peripherals manual. 
+/// Physical addresses range from 0x20000000 to 0x20FFFFFF for peripherals. The bus
+/// addresses for peripherals are set up to map onto the peripheral bus address range starting at
+/// 0x7E000000. Thus a peripheral advertised in the manual at bus address 0x7Ennnnnn is available at
+/// physical address 0x20nnnnnn.
+///
+/// The base address of the various peripheral registers are available with the following
+/// externals:
+/// bcm2835_gpio
+/// bcm2835_pwm
+/// bcm2835_clk
+/// bcm2835_pads
+/// bcm2835_spio0
+/// bcm2835_st
+/// bcm2835_bsc0
+/// bcm2835_bsc1
+///
+/// \par Pin Numbering
+///
+/// The GPIO pin numbering as used by RPi is different to and inconsistent with the underlying 
+/// BCM 2835 chip pin numbering. http://elinux.org/RPi_BCM2835_GPIOs
+/// 
+/// RPi has a 26 pin IDE header that provides access to some of the GPIO pins on the BCM 2835,
+/// as well as power and ground pins. Not all GPIO pins on the BCM 2835 are available on the 
+/// IDE header.
+///
+/// RPi Version 2 also has a P5 connector with 4 GPIO pins, 5V, 3.3V and Gnd.
+///
+/// The functions in this library are designed to be passed the BCM 2835 GPIO pin number and _not_ 
+/// the RPi pin number. There are symbolic definitions for each of the available pins
+/// that you should use for convenience. See \ref RPiGPIOPin.
+///
+/// \par SPI Pins
+/// 
+/// The bcm2835_spi_* functions allow you to control the BCM 2835 SPI0 interface, 
+/// allowing you to send and received data by SPI (Serial Peripheral Interface).
+/// For more information about SPI, see http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
+///
+/// When bcm2835_spi_begin() is called it changes the bahaviour of the SPI interface pins from their 
+/// default GPIO behaviour in order to support SPI. While SPI is in use, you will not be able 
+/// to control the state of the SPI pins through the usual bcm2835_spi_gpio_write().
+/// When bcm2835_spi_end() is called, the SPI pins will all revert to inputs, and can then be
+/// configured and controled with the usual bcm2835_gpio_* calls.
+///
+/// The Raspberry Pi GPIO pins used for SPI are:
+/// 
+/// - P1-19 (MOSI)
+/// - P1-21 (MISO) 
+/// - P1-23 (CLK) 
+/// - P1-24 (CE0) 
+/// - P1-26 (CE1)
+///
+/// \par I2C Pins
+///
+/// The bcm2835_i2c_* functions allow you to control the BCM 2835 BSC interface,
+/// allowing you to send and received data by I2C ("eye-squared cee"; generically referred to as "two-wire interface") .
+/// For more information about I²C, see http://en.wikipedia.org/wiki/I%C2%B2C
+///
+/// The Raspberry Pi V2 GPIO pins used for I2C are:
+///
+/// - P1-03 (SDA)
+/// - P1-05 (SLC)
+///
+/// \par Real Time performance constraints
+///
+/// The bcm2835 is a library for user programs (i.e. they run in 'userland'). 
+/// Such programs are not part of the kernel and are usually
+/// subject to paging and swapping by the kernel while it does other things besides running your program. 
+/// This means that you should not expect to get real-time performance or 
+/// real-time timing constraints from such programs. In particular, there is no guarantee that the 
+/// bcm2835_delay() and bcm2835_delayMicroseconds() will return after exactly the time requested. 
+/// In fact, depending on other activity on the host, IO etc, you might get significantly longer delay times
+/// than the one you asked for. So please dont expect to get exactly the time delay you request.
+///
+/// Arjan reports that you can prevent swapping on Linux with the following code fragment:
+///
+/// \code
+///  struct sched_param sp;
+///  memset(&sp, 0, sizeof(sp));
+///  sp.sched_priority = sched_get_priority_max(SCHED_FIFO);
+///  sched_setscheduler(0, SCHED_FIFO, &sp);
+///  mlockall(MCL_CURRENT | MCL_FUTURE);
+/// \endcode
+///
+/// \par Open Source Licensing GPL V2
+///
+/// This is the appropriate option if you want to share the source code of your
+/// application with everyone you distribute it to, and you also want to give them
+/// the right to share who uses it. If you wish to use this software under Open
+/// Source Licensing, you must contribute all your source code to the open source
+/// community in accordance with the GPL Version 2 when your application is
+/// distributed. See http://www.gnu.org/copyleft/gpl.html and COPYING
+///
+/// \par Acknowledgements
+///
+/// Some of this code has been inspired by Dom and Gert.
+/// The I2C code has been inspired by Alan Barr.
+/// 
+/// \par Revision History
+///
+/// \version 1.0 Initial release
+/// \version 1.1 Minor bug fixes
+/// \version 1.2 Added support for SPI
+/// \version 1.3 Added bcm2835_spi_transfern()
+/// \version 1.4 Fixed a problem that prevented SPI CE1 being used. Reported by David Robinson.
+/// \version 1.5 Added bcm2835_close() to deinit the library. Suggested by C?sar Ortiz
+/// \version 1.6 Document testing on 2012-07-15-wheezy-raspbian and Occidentalisv01
+///              Functions bcm2835_gpio_ren(), bcm2835_gpio_fen(), bcm2835_gpio_hen()
+///               bcm2835_gpio_len(), bcm2835_gpio_aren() and bcm2835_gpio_afen() now 
+///               changes only the pin specified. Other pins that were already previously
+///               enabled stay enabled.
+///              Added  bcm2835_gpio_clr_ren(), bcm2835_gpio_clr_fen(), bcm2835_gpio_clr_hen()
+///                bcm2835_gpio_clr_len(), bcm2835_gpio_clr_aren(), bcm2835_gpio_clr_afen() 
+///                to clear the enable for individual pins, suggested by Andreas Sundstrom.
+/// \version 1.7 Added bcm2835_spi_transfernb to support different buffers for read and write.
+/// \version 1.8 Improvements to read barrier, as suggested by maddin.
+/// \version 1.9 Improvements contributed by mikew: 
+///              I noticed that it was mallocing memory for the mmaps on /dev/mem.
+///              It's not necessary to do that, you can just mmap the file directly,
+///              so I've removed the mallocs (and frees).
+///              I've also modified delayMicroseconds() to use nanosleep() for long waits,
+///              and a busy wait on a high resolution timer for the rest. This is because
+///              I've found that calling nanosleep() takes at least 100-200 us.
+///              You need to link using '-lrt' using this version.
+///              I've added some unsigned casts to the debug prints to silence compiler
+///              warnings I was getting, fixed some typos, and changed the value of
+///              BCM2835_PAD_HYSTERESIS_ENABLED to 0x08 as per Gert van Loo's doc at
+///              http://www.scribd.com/doc/101830961/GPIO-Pads-Control2
+///              Also added a define for the passwrd value that Gert says is needed to
+///              change pad control settings.
+/// \version 1.10 Changed the names of the delay functions to bcm2835_delay() 
+///              and bcm2835_delayMicroseconds() to prevent collisions with wiringPi.
+///              Macros to map delay()-> bcm2835_delay() and
+///              Macros to map delayMicroseconds()-> bcm2835_delayMicroseconds(), which
+///              can be disabled by defining BCM2835_NO_DELAY_COMPATIBILITY
+/// \version 1.11 Fixed incorrect link to download file
+/// \version 1.12 New GPIO pin definitions for RPi version 2 (which has a different GPIO mapping)             
+/// \version 1.13 New GPIO pin definitions for RPi version 2 plug P5
+///               Hardware base pointers are now available (after initialisation) externally as bcm2835_gpio
+///               bcm2835_pwm bcm2835_clk bcm2835_pads bcm2835_spi0.
+/// \version 1.14 Now compiles even if CLOCK_MONOTONIC_RAW is not available, uses CLOCK_MONOTONIC instead.
+///               Fixed errors in documentation of SPI divider frequencies based on 250MHz clock. 
+///               Reported by Ben Simpson.
+/// \version 1.15 Added bcm2835_close() to end of examples as suggested by Mark Wolfe.
+/// \version 1.16 Added bcm2835_gpio_set_multi, bcm2835_gpio_clr_multi and bcm2835_gpio_write_multi
+///               to allow a mask of pins to be set all at once. Requested by Sebastian Loncar.
+/// \version 1.17  Added bcm2835_gpio_write_mask. Requested by Sebastian Loncar.
+/// \version 1.18 Added bcm2835_i2c_* functions. Changes to bcm2835_delayMicroseconds: 
+///               now uses the RPi system timer counter, instead of clock_gettime, for improved accuracy. 
+///               No need to link with -lrt now. Contributed by Arjan van Vught.
+/// \version 1.19 Removed inlines added by previous patch since they don't seem to work everywhere. 
+///               Reported by olly.
+/// \version 1.20 Patch from Mark Dootson to close /dev/mem after access to the peripherals has been granted.
+/// \version 1.21 delayMicroseconds is now not susceptible to 32 bit timer overruns. 
+///               Patch courtesy Jeremy Mortis.
+/// \version 1.22 Fixed incorrect definition of BCM2835_GPFEN0 which broke the ability to set 
+///               falling edge events. Reported by MArk Dootson.
+/// \author  Mike McCauley (mikem@airspayce.com)
+
+
+
+// Defines for BCM2835
+#ifndef BCM2835_H
+#define BCM2835_H
+
+#include 
+
+/// \defgroup constants Constants for passing to and from library functions
+/// The values here are designed to be passed to various functions in the bcm2835 library.
+/// @{
+
+
+/// This means pin HIGH, true, 3.3volts on a pin.
+#define HIGH 0x1
+/// This means pin LOW, false, 0volts on a pin.
+#define LOW  0x0
+
+/// Speed of the core clock core_clk
+#define BCM2835_CORE_CLK_HZ				250000000	///< 250 MHz
+
+// Physical addresses for various peripheral register sets
+/// Base Physical Address of the BCM 2835 peripheral registers
+#define BCM2835_PERI_BASE               0x20000000
+/// Base Physical Address of the System Timer registers
+#define BCM2835_ST_BASE			(BCM2835_PERI_BASE + 0x3000)
+/// Base Physical Address of the Pads registers
+#define BCM2835_GPIO_PADS               (BCM2835_PERI_BASE + 0x100000)
+/// Base Physical Address of the Clock/timer registers
+#define BCM2835_CLOCK_BASE              (BCM2835_PERI_BASE + 0x101000)
+/// Base Physical Address of the GPIO registers
+#define BCM2835_GPIO_BASE               (BCM2835_PERI_BASE + 0x200000)
+/// Base Physical Address of the SPI0 registers
+#define BCM2835_SPI0_BASE               (BCM2835_PERI_BASE + 0x204000)
+/// Base Physical Address of the BSC0 registers
+#define BCM2835_BSC0_BASE 		(BCM2835_PERI_BASE + 0x205000)
+/// Base Physical Address of the PWM registers
+#define BCM2835_GPIO_PWM                (BCM2835_PERI_BASE + 0x20C000)
+ /// Base Physical Address of the BSC1 registers
+#define BCM2835_BSC1_BASE		(BCM2835_PERI_BASE + 0x804000)
+
+
+/// Base of the ST (System Timer) registers.
+/// Available after bcm2835_init has been called
+extern volatile uint32_t *bcm2835_st;
+
+/// Base of the GPIO registers.
+/// Available after bcm2835_init has been called
+extern volatile uint32_t *bcm2835_gpio;
+
+/// Base of the PWM registers.
+/// Available after bcm2835_init has been called
+extern volatile uint32_t *bcm2835_pwm;
+
+/// Base of the CLK registers.
+/// Available after bcm2835_init has been called
+extern volatile uint32_t *bcm2835_clk;
+
+/// Base of the PADS registers.
+/// Available after bcm2835_init has been called
+extern volatile uint32_t *bcm2835_pads;
+
+/// Base of the SPI0 registers.
+/// Available after bcm2835_init has been called
+extern volatile uint32_t *bcm2835_spi0;
+
+/// Base of the BSC0 registers.
+/// Available after bcm2835_init has been called
+extern volatile uint32_t *bcm2835_bsc0;
+
+/// Base of the BSC1 registers.
+/// Available after bcm2835_init has been called
+extern volatile uint32_t *bcm2835_bsc1;
+
+/// Size of memory page on RPi
+#define BCM2835_PAGE_SIZE               (4*1024)
+/// Size of memory block on RPi
+#define BCM2835_BLOCK_SIZE              (4*1024)
+
+
+// Defines for GPIO
+// The BCM2835 has 54 GPIO pins.
+//      BCM2835 data sheet, Page 90 onwards.
+/// GPIO register offsets from BCM2835_GPIO_BASE. Offsets into the GPIO Peripheral block in bytes per 6.1 Register View
+#define BCM2835_GPFSEL0                      0x0000 ///< GPIO Function Select 0
+#define BCM2835_GPFSEL1                      0x0004 ///< GPIO Function Select 1
+#define BCM2835_GPFSEL2                      0x0008 ///< GPIO Function Select 2
+#define BCM2835_GPFSEL3                      0x000c ///< GPIO Function Select 3
+#define BCM2835_GPFSEL4                      0x0010 ///< GPIO Function Select 4
+#define BCM2835_GPFSEL5                      0x0014 ///< GPIO Function Select 5
+#define BCM2835_GPSET0                       0x001c ///< GPIO Pin Output Set 0
+#define BCM2835_GPSET1                       0x0020 ///< GPIO Pin Output Set 1
+#define BCM2835_GPCLR0                       0x0028 ///< GPIO Pin Output Clear 0
+#define BCM2835_GPCLR1                       0x002c ///< GPIO Pin Output Clear 1
+#define BCM2835_GPLEV0                       0x0034 ///< GPIO Pin Level 0
+#define BCM2835_GPLEV1                       0x0038 ///< GPIO Pin Level 1
+#define BCM2835_GPEDS0                       0x0040 ///< GPIO Pin Event Detect Status 0
+#define BCM2835_GPEDS1                       0x0044 ///< GPIO Pin Event Detect Status 1
+#define BCM2835_GPREN0                       0x004c ///< GPIO Pin Rising Edge Detect Enable 0
+#define BCM2835_GPREN1                       0x0050 ///< GPIO Pin Rising Edge Detect Enable 1
+#define BCM2835_GPFEN0                       0x0058 ///< GPIO Pin Falling Edge Detect Enable 0
+#define BCM2835_GPFEN1                       0x005c ///< GPIO Pin Falling Edge Detect Enable 1
+#define BCM2835_GPHEN0                       0x0064 ///< GPIO Pin High Detect Enable 0
+#define BCM2835_GPHEN1                       0x0068 ///< GPIO Pin High Detect Enable 1
+#define BCM2835_GPLEN0                       0x0070 ///< GPIO Pin Low Detect Enable 0
+#define BCM2835_GPLEN1                       0x0074 ///< GPIO Pin Low Detect Enable 1
+#define BCM2835_GPAREN0                      0x007c ///< GPIO Pin Async. Rising Edge Detect 0
+#define BCM2835_GPAREN1                      0x0080 ///< GPIO Pin Async. Rising Edge Detect 1
+#define BCM2835_GPAFEN0                      0x0088 ///< GPIO Pin Async. Falling Edge Detect 0
+#define BCM2835_GPAFEN1                      0x008c ///< GPIO Pin Async. Falling Edge Detect 1
+#define BCM2835_GPPUD                        0x0094 ///< GPIO Pin Pull-up/down Enable
+#define BCM2835_GPPUDCLK0                    0x0098 ///< GPIO Pin Pull-up/down Enable Clock 0
+#define BCM2835_GPPUDCLK1                    0x009c ///< GPIO Pin Pull-up/down Enable Clock 1
+
+/// \brief bcm2835PortFunction
+/// Port function select modes for bcm2835_gpio_fsel()
+typedef enum
+{
+    BCM2835_GPIO_FSEL_INPT  = 0b000,   ///< Input
+    BCM2835_GPIO_FSEL_OUTP  = 0b001,   ///< Output
+    BCM2835_GPIO_FSEL_ALT0  = 0b100,   ///< Alternate function 0
+    BCM2835_GPIO_FSEL_ALT1  = 0b101,   ///< Alternate function 1
+    BCM2835_GPIO_FSEL_ALT2  = 0b110,   ///< Alternate function 2
+    BCM2835_GPIO_FSEL_ALT3  = 0b111,   ///< Alternate function 3
+    BCM2835_GPIO_FSEL_ALT4  = 0b011,   ///< Alternate function 4
+    BCM2835_GPIO_FSEL_ALT5  = 0b010,   ///< Alternate function 5
+    BCM2835_GPIO_FSEL_MASK  = 0b111    ///< Function select bits mask
+} bcm2835FunctionSelect;
+
+/// \brief bcm2835PUDControl
+/// Pullup/Pulldown defines for bcm2835_gpio_pud()
+typedef enum
+{
+    BCM2835_GPIO_PUD_OFF     = 0b00,   ///< Off ? disable pull-up/down
+    BCM2835_GPIO_PUD_DOWN    = 0b01,   ///< Enable Pull Down control
+    BCM2835_GPIO_PUD_UP      = 0b10    ///< Enable Pull Up control
+} bcm2835PUDControl;
+
+/// Pad control register offsets from BCM2835_GPIO_PADS
+#define BCM2835_PADS_GPIO_0_27               0x002c ///< Pad control register for pads 0 to 27
+#define BCM2835_PADS_GPIO_28_45              0x0030 ///< Pad control register for pads 28 to 45
+#define BCM2835_PADS_GPIO_46_53              0x0034 ///< Pad control register for pads 46 to 53
+
+/// Pad Control masks
+#define BCM2835_PAD_PASSWRD                  (0x5A << 24)  ///< Password to enable setting pad mask
+#define BCM2835_PAD_SLEW_RATE_UNLIMITED      0x10 ///< Slew rate unlimited
+#define BCM2835_PAD_HYSTERESIS_ENABLED       0x08 ///< Hysteresis enabled
+#define BCM2835_PAD_DRIVE_2mA                0x00 ///< 2mA drive current
+#define BCM2835_PAD_DRIVE_4mA                0x01 ///< 4mA drive current
+#define BCM2835_PAD_DRIVE_6mA                0x02 ///< 6mA drive current
+#define BCM2835_PAD_DRIVE_8mA                0x03 ///< 8mA drive current
+#define BCM2835_PAD_DRIVE_10mA               0x04 ///< 10mA drive current
+#define BCM2835_PAD_DRIVE_12mA               0x05 ///< 12mA drive current
+#define BCM2835_PAD_DRIVE_14mA               0x06 ///< 14mA drive current
+#define BCM2835_PAD_DRIVE_16mA               0x07 ///< 16mA drive current
+
+/// \brief bcm2835PadGroup
+/// Pad group specification for bcm2835_gpio_pad()
+typedef enum
+{
+    BCM2835_PAD_GROUP_GPIO_0_27         = 0, ///< Pad group for GPIO pads 0 to 27
+    BCM2835_PAD_GROUP_GPIO_28_45        = 1, ///< Pad group for GPIO pads 28 to 45
+    BCM2835_PAD_GROUP_GPIO_46_53        = 2  ///< Pad group for GPIO pads 46 to 53
+} bcm2835PadGroup;
+
+/// \brief GPIO Pin Numbers
+///
+/// Here we define Raspberry Pin GPIO pins on P1 in terms of the underlying BCM GPIO pin numbers.
+/// These can be passed as a pin number to any function requiring a pin.
+/// Not all pins on the RPi 26 bin IDE plug are connected to GPIO pins
+/// and some can adopt an alternate function.
+/// RPi version 2 has some slightly different pinouts, and these are values RPI_V2_*.
+/// At bootup, pins 8 and 10 are set to UART0_TXD, UART0_RXD (ie the alt0 function) respectively
+/// When SPI0 is in use (ie after bcm2835_spi_begin()), pins 19, 21, 23, 24, 26 are dedicated to SPI
+/// and cant be controlled independently
+typedef enum
+{
+    RPI_GPIO_P1_03        =  0,  ///< Version 1, Pin P1-03
+    RPI_GPIO_P1_05        =  1,  ///< Version 1, Pin P1-05
+    RPI_GPIO_P1_07        =  4,  ///< Version 1, Pin P1-07
+    RPI_GPIO_P1_08        = 14,  ///< Version 1, Pin P1-08, defaults to alt function 0 UART0_TXD
+    RPI_GPIO_P1_10        = 15,  ///< Version 1, Pin P1-10, defaults to alt function 0 UART0_RXD
+    RPI_GPIO_P1_11        = 17,  ///< Version 1, Pin P1-11
+    RPI_GPIO_P1_12        = 18,  ///< Version 1, Pin P1-12
+    RPI_GPIO_P1_13        = 21,  ///< Version 1, Pin P1-13
+    RPI_GPIO_P1_15        = 22,  ///< Version 1, Pin P1-15
+    RPI_GPIO_P1_16        = 23,  ///< Version 1, Pin P1-16
+    RPI_GPIO_P1_18        = 24,  ///< Version 1, Pin P1-18
+    RPI_GPIO_P1_19        = 10,  ///< Version 1, Pin P1-19, MOSI when SPI0 in use
+    RPI_GPIO_P1_21        =  9,  ///< Version 1, Pin P1-21, MISO when SPI0 in use
+    RPI_GPIO_P1_22        = 25,  ///< Version 1, Pin P1-22
+    RPI_GPIO_P1_23        = 11,  ///< Version 1, Pin P1-23, CLK when SPI0 in use
+    RPI_GPIO_P1_24        =  8,  ///< Version 1, Pin P1-24, CE0 when SPI0 in use
+    RPI_GPIO_P1_26        =  7,  ///< Version 1, Pin P1-26, CE1 when SPI0 in use
+
+    // RPi Version 2
+    RPI_V2_GPIO_P1_03     =  2,  ///< Version 2, Pin P1-03
+    RPI_V2_GPIO_P1_05     =  3,  ///< Version 2, Pin P1-05
+    RPI_V2_GPIO_P1_07     =  4,  ///< Version 2, Pin P1-07
+    RPI_V2_GPIO_P1_08     = 14,  ///< Version 2, Pin P1-08, defaults to alt function 0 UART0_TXD
+    RPI_V2_GPIO_P1_10     = 15,  ///< Version 2, Pin P1-10, defaults to alt function 0 UART0_RXD
+    RPI_V2_GPIO_P1_11     = 17,  ///< Version 2, Pin P1-11
+    RPI_V2_GPIO_P1_12     = 18,  ///< Version 2, Pin P1-12
+    RPI_V2_GPIO_P1_13     = 27,  ///< Version 2, Pin P1-13
+    RPI_V2_GPIO_P1_15     = 22,  ///< Version 2, Pin P1-15
+    RPI_V2_GPIO_P1_16     = 23,  ///< Version 2, Pin P1-16
+    RPI_V2_GPIO_P1_18     = 24,  ///< Version 2, Pin P1-18
+    RPI_V2_GPIO_P1_19     = 10,  ///< Version 2, Pin P1-19, MOSI when SPI0 in use
+    RPI_V2_GPIO_P1_21     =  9,  ///< Version 2, Pin P1-21, MISO when SPI0 in use
+    RPI_V2_GPIO_P1_22     = 25,  ///< Version 2, Pin P1-22
+    RPI_V2_GPIO_P1_23     = 11,  ///< Version 2, Pin P1-23, CLK when SPI0 in use
+    RPI_V2_GPIO_P1_24     =  8,  ///< Version 2, Pin P1-24, CE0 when SPI0 in use
+    RPI_V2_GPIO_P1_26     =  7,  ///< Version 2, Pin P1-26, CE1 when SPI0 in use
+
+    // RPi Version 2, new plug P5
+    RPI_V2_GPIO_P5_03     = 28,  ///< Version 2, Pin P5-03
+    RPI_V2_GPIO_P5_04     = 29,  ///< Version 2, Pin P5-04
+    RPI_V2_GPIO_P5_05     = 30,  ///< Version 2, Pin P5-05
+    RPI_V2_GPIO_P5_06     = 31,  ///< Version 2, Pin P5-06
+
+} RPiGPIOPin;
+
+// Defines for SPI
+// GPIO register offsets from BCM2835_SPI0_BASE. 
+// Offsets into the SPI Peripheral block in bytes per 10.5 SPI Register Map
+#define BCM2835_SPI0_CS                      0x0000 ///< SPI Master Control and Status
+#define BCM2835_SPI0_FIFO                    0x0004 ///< SPI Master TX and RX FIFOs
+#define BCM2835_SPI0_CLK                     0x0008 ///< SPI Master Clock Divider
+#define BCM2835_SPI0_DLEN                    0x000c ///< SPI Master Data Length
+#define BCM2835_SPI0_LTOH                    0x0010 ///< SPI LOSSI mode TOH
+#define BCM2835_SPI0_DC                      0x0014 ///< SPI DMA DREQ Controls
+
+// Register masks for SPI0_CS
+#define BCM2835_SPI0_CS_LEN_LONG             0x02000000 ///< Enable Long data word in Lossi mode if DMA_LEN is set
+#define BCM2835_SPI0_CS_DMA_LEN              0x01000000 ///< Enable DMA mode in Lossi mode
+#define BCM2835_SPI0_CS_CSPOL2               0x00800000 ///< Chip Select 2 Polarity
+#define BCM2835_SPI0_CS_CSPOL1               0x00400000 ///< Chip Select 1 Polarity
+#define BCM2835_SPI0_CS_CSPOL0               0x00200000 ///< Chip Select 0 Polarity
+#define BCM2835_SPI0_CS_RXF                  0x00100000 ///< RXF - RX FIFO Full
+#define BCM2835_SPI0_CS_RXR                  0x00080000 ///< RXR RX FIFO needs Reading ( full)
+#define BCM2835_SPI0_CS_TXD                  0x00040000 ///< TXD TX FIFO can accept Data
+#define BCM2835_SPI0_CS_RXD                  0x00020000 ///< RXD RX FIFO contains Data
+#define BCM2835_SPI0_CS_DONE                 0x00010000 ///< Done transfer Done
+#define BCM2835_SPI0_CS_TE_EN                0x00008000 ///< Unused
+#define BCM2835_SPI0_CS_LMONO                0x00004000 ///< Unused
+#define BCM2835_SPI0_CS_LEN                  0x00002000 ///< LEN LoSSI enable
+#define BCM2835_SPI0_CS_REN                  0x00001000 ///< REN Read Enable
+#define BCM2835_SPI0_CS_ADCS                 0x00000800 ///< ADCS Automatically Deassert Chip Select
+#define BCM2835_SPI0_CS_INTR                 0x00000400 ///< INTR Interrupt on RXR
+#define BCM2835_SPI0_CS_INTD                 0x00000200 ///< INTD Interrupt on Done
+#define BCM2835_SPI0_CS_DMAEN                0x00000100 ///< DMAEN DMA Enable
+#define BCM2835_SPI0_CS_TA                   0x00000080 ///< Transfer Active
+#define BCM2835_SPI0_CS_CSPOL                0x00000040 ///< Chip Select Polarity
+#define BCM2835_SPI0_CS_CLEAR                0x00000030 ///< Clear FIFO Clear RX and TX
+#define BCM2835_SPI0_CS_CLEAR_RX             0x00000020 ///< Clear FIFO Clear RX 
+#define BCM2835_SPI0_CS_CLEAR_TX             0x00000010 ///< Clear FIFO Clear TX 
+#define BCM2835_SPI0_CS_CPOL                 0x00000008 ///< Clock Polarity
+#define BCM2835_SPI0_CS_CPHA                 0x00000004 ///< Clock Phase
+#define BCM2835_SPI0_CS_CS                   0x00000003 ///< Chip Select
+
+/// \brief bcm2835SPIBitOrder SPI Bit order
+/// Specifies the SPI data bit ordering for bcm2835_spi_setBitOrder()
+typedef enum
+{
+    BCM2835_SPI_BIT_ORDER_LSBFIRST = 0,  ///< LSB First
+    BCM2835_SPI_BIT_ORDER_MSBFIRST = 1   ///< MSB First
+}bcm2835SPIBitOrder;
+
+/// \brief SPI Data mode
+/// Specify the SPI data mode to be passed to bcm2835_spi_setDataMode()
+typedef enum
+{
+    BCM2835_SPI_MODE0 = 0,  ///< CPOL = 0, CPHA = 0
+    BCM2835_SPI_MODE1 = 1,  ///< CPOL = 0, CPHA = 1
+    BCM2835_SPI_MODE2 = 2,  ///< CPOL = 1, CPHA = 0
+    BCM2835_SPI_MODE3 = 3,  ///< CPOL = 1, CPHA = 1
+}bcm2835SPIMode;
+
+/// \brief bcm2835SPIChipSelect
+/// Specify the SPI chip select pin(s)
+/// You can use another Chip Select pin instead of CE0 or CE1 if you want
+/// just need to indicate the GPIO line 
+typedef enum
+{
+    BCM2835_SPI_CS0 = 0,     ///< Chip Select 0
+    BCM2835_SPI_CS1 = 1,     ///< Chip Select 1
+    BCM2835_SPI_CS2 = 2,     ///< Chip Select 2 (ie pins CS1 and CS2 are asserted)
+    BCM2835_SPI_CS_NONE = 3, ///< No CS, control it yourself
+
+		// Only GPIO > 3 can be used (to not interfere with the previous value just above )
+		// Lucky we have plenty of theese pins
+		BCM2835_SPI_CS_GPIO4  = RPI_V2_GPIO_P1_07, /// BCM GPIO 4
+		BCM2835_SPI_CS_GPIO17 = RPI_V2_GPIO_P1_11, /// BCM GPIO 17
+		BCM2835_SPI_CS_GPIO18 = RPI_V2_GPIO_P1_12, /// BCM GPIO 18
+		BCM2835_SPI_CS_GPIO22 = RPI_V2_GPIO_P1_15, /// BCM GPIO 22
+		BCM2835_SPI_CS_GPIO23 = RPI_V2_GPIO_P1_16, /// BCM GPIO 23
+		BCM2835_SPI_CS_GPIO24 = RPI_V2_GPIO_P1_18, /// BCM GPIO 24
+		BCM2835_SPI_CS_GPIO25 = RPI_V2_GPIO_P1_22, /// BCM GPIO 25
+		BCM2835_SPI_CS_GPIO28 = RPI_V2_GPIO_P5_03, /// BCM GPIO 28
+		BCM2835_SPI_CS_GPIO29 = RPI_V2_GPIO_P5_04, /// BCM GPIO 29
+		BCM2835_SPI_CS_GPIO30 = RPI_V2_GPIO_P5_05, /// BCM GPIO 30
+		BCM2835_SPI_CS_GPIO31 = RPI_V2_GPIO_P5_06, /// BCM GPIO 31
+
+} bcm2835SPIChipSelect;
+
+/// \brief bcm2835SPIClockDivider
+/// Specifies the divider used to generate the SPI clock from the system clock.
+/// Figures below give the divider, clock period and clock frequency.
+/// Clock divided is based on nominal base clock rate of 250MHz
+/// It is reported that (contrary to the documentation) any even divider may used.
+/// The frequencies shown for each divider have been confirmed by measurement
+typedef enum
+{
+    BCM2835_SPI_CLOCK_DIVIDER_65536 = 0,       ///< 65536 = 262.144us = 3.814697260kHz
+    BCM2835_SPI_CLOCK_DIVIDER_32768 = 32768,   ///< 32768 = 131.072us = 7.629394531kHz
+    BCM2835_SPI_CLOCK_DIVIDER_16384 = 16384,   ///< 16384 = 65.536us = 15.25878906kHz
+    BCM2835_SPI_CLOCK_DIVIDER_8192  = 8192,    ///< 8192 = 32.768us = 30/51757813kHz
+    BCM2835_SPI_CLOCK_DIVIDER_4096  = 4096,    ///< 4096 = 16.384us = 61.03515625kHz
+    BCM2835_SPI_CLOCK_DIVIDER_2048  = 2048,    ///< 2048 = 8.192us = 122.0703125kHz
+    BCM2835_SPI_CLOCK_DIVIDER_1024  = 1024,    ///< 1024 = 4.096us = 244.140625kHz
+    BCM2835_SPI_CLOCK_DIVIDER_512   = 512,     ///< 512 = 2.048us = 488.28125kHz
+    BCM2835_SPI_CLOCK_DIVIDER_256   = 256,     ///< 256 = 1.024us = 976.5625MHz
+    BCM2835_SPI_CLOCK_DIVIDER_128   = 128,     ///< 128 = 512ns = = 1.953125MHz
+    BCM2835_SPI_CLOCK_DIVIDER_64    = 64,      ///< 64 = 256ns = 3.90625MHz
+    BCM2835_SPI_CLOCK_DIVIDER_32    = 32,      ///< 32 = 128ns = 7.8125MHz
+    BCM2835_SPI_CLOCK_DIVIDER_16    = 16,      ///< 16 = 64ns = 15.625MHz
+    BCM2835_SPI_CLOCK_DIVIDER_8     = 8,       ///< 8 = 32ns = 31.25MHz
+    BCM2835_SPI_CLOCK_DIVIDER_4     = 4,       ///< 4 = 16ns = 62.5MHz
+    BCM2835_SPI_CLOCK_DIVIDER_2     = 2,       ///< 2 = 8ns = 125MHz, fastest you can get
+    BCM2835_SPI_CLOCK_DIVIDER_1     = 1,       ///< 0 = 262.144us = 3.814697260kHz, same as 0/65536
+} bcm2835SPIClockDivider;
+
+/// \brief bcm2835SPISpeed
+/// Specifies the divider used to generate the SPI clock from the system clock.
+/// Figures below give the clock speed instead of clock divider.
+#define BCM2835_SPI_SPEED_64MHZ  BCM2835_SPI_CLOCK_DIVIDER_4
+#define BCM2835_SPI_SPEED_32MHZ  BCM2835_SPI_CLOCK_DIVIDER_8
+#define BCM2835_SPI_SPEED_16MHZ  BCM2835_SPI_CLOCK_DIVIDER_16
+#define BCM2835_SPI_SPEED_8MHZ   BCM2835_SPI_CLOCK_DIVIDER_32
+#define BCM2835_SPI_SPEED_4MHZ   BCM2835_SPI_CLOCK_DIVIDER_64
+#define BCM2835_SPI_SPEED_2MHZ   BCM2835_SPI_CLOCK_DIVIDER_128
+#define BCM2835_SPI_SPEED_1MHZ   BCM2835_SPI_CLOCK_DIVIDER_256
+#define BCM2835_SPI_SPEED_512KHZ BCM2835_SPI_CLOCK_DIVIDER_512
+#define BCM2835_SPI_SPEED_256KHZ BCM2835_SPI_CLOCK_DIVIDER_1024
+#define BCM2835_SPI_SPEED_128KHZ BCM2835_SPI_CLOCK_DIVIDER_2048
+#define BCM2835_SPI_SPEED_64KHZ  BCM2835_SPI_CLOCK_DIVIDER_4096
+#define BCM2835_SPI_SPEED_32KHZ  BCM2835_SPI_CLOCK_DIVIDER_8192
+#define BCM2835_SPI_SPEED_16KHZ  BCM2835_SPI_CLOCK_DIVIDER_16384
+#define BCM2835_SPI_SPEED_8KHZ   BCM2835_SPI_CLOCK_DIVIDER_32768
+
+
+// Defines for I2C
+// GPIO register offsets from BCM2835_BSC*_BASE.
+// Offsets into the BSC Peripheral block in bytes per 3.1 BSC Register Map
+#define BCM2835_BSC_C 							0x0000 ///< BSC Master Control
+#define BCM2835_BSC_S 							0x0004 ///< BSC Master Status
+#define BCM2835_BSC_DLEN						0x0008 ///< BSC Master Data Length
+#define BCM2835_BSC_A 							0x000c ///< BSC Master Slave Address
+#define BCM2835_BSC_FIFO						0x0010 ///< BSC Master Data FIFO
+#define BCM2835_BSC_DIV							0x0014 ///< BSC Master Clock Divider
+#define BCM2835_BSC_DEL							0x0018 ///< BSC Master Data Delay
+#define BCM2835_BSC_CLKT						0x001c ///< BSC Master Clock Stretch Timeout
+
+// Register masks for BSC_C
+#define BCM2835_BSC_C_I2CEN 					0x00008000 ///< I2C Enable, 0 = disabled, 1 = enabled
+#define BCM2835_BSC_C_INTR 						0x00000400 ///< Interrupt on RX
+#define BCM2835_BSC_C_INTT 						0x00000200 ///< Interrupt on TX
+#define BCM2835_BSC_C_INTD 						0x00000100 ///< Interrupt on DONE
+#define BCM2835_BSC_C_ST 						0x00000080 ///< Start transfer, 1 = Start a new transfer
+#define BCM2835_BSC_C_CLEAR_1 					0x00000020 ///< Clear FIFO Clear
+#define BCM2835_BSC_C_CLEAR_2 					0x00000010 ///< Clear FIFO Clear
+#define BCM2835_BSC_C_READ 						0x00000001 ///<	Read transfer
+
+// Register masks for BSC_S
+#define BCM2835_BSC_S_CLKT 						0x00000200 ///< Clock stretch timeout
+#define BCM2835_BSC_S_ERR 						0x00000100 ///< ACK error
+#define BCM2835_BSC_S_RXF 						0x00000080 ///< RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full
+#define BCM2835_BSC_S_TXE 						0x00000040 ///< TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full
+#define BCM2835_BSC_S_RXD 						0x00000020 ///< RXD FIFO contains data
+#define BCM2835_BSC_S_TXD 						0x00000010 ///< TXD FIFO can accept data
+#define BCM2835_BSC_S_RXR 						0x00000008 ///< RXR FIFO needs reading (full)
+#define BCM2835_BSC_S_TXW 						0x00000004 ///< TXW FIFO needs writing (full)
+#define BCM2835_BSC_S_DONE 						0x00000002 ///< Transfer DONE
+#define BCM2835_BSC_S_TA 						0x00000001 ///< Transfer Active
+
+#define BCM2835_BSC_FIFO_SIZE   				16 ///< BSC FIFO size
+
+/// \brief bcm2835I2CClockDivider
+/// Specifies the divider used to generate the I2C clock from the system clock.
+/// Clock divided is based on nominal base clock rate of 250MHz
+typedef enum
+{
+    BCM2835_I2C_CLOCK_DIVIDER_2500   = 2500,      ///< 2500 = 10us = 100 kHz
+    BCM2835_I2C_CLOCK_DIVIDER_626    = 626,       ///< 622 = 2.504us = 399.3610 kHz
+    BCM2835_I2C_CLOCK_DIVIDER_150    = 150,       ///< 150 = 60ns = 1.666 MHz (default at reset)
+    BCM2835_I2C_CLOCK_DIVIDER_148    = 148,       ///< 148 = 59ns = 1.689 MHz
+} bcm2835I2CClockDivider;
+
+/// \brief bcm2835I2CReasonCodes
+/// Specifies the reason codes for the bcm2835_i2c_write and bcm2835_i2c_read functions.
+typedef enum
+{
+    BCM2835_I2C_REASON_OK   		 = 0x00,      ///< Success
+    BCM2835_I2C_REASON_ERROR_NACK    = 0x01,      ///< Received a NACK
+    BCM2835_I2C_REASON_ERROR_CLKT    = 0x02,      ///< Received Clock Stretch Timeout
+    BCM2835_I2C_REASON_ERROR_DATA    = 0x04,      ///< Not all data is sent / received
+} bcm2835I2CReasonCodes;
+
+// Defines for ST
+// GPIO register offsets from BCM2835_ST_BASE.
+// Offsets into the ST Peripheral block in bytes per 12.1 System Timer Registers
+// The System Timer peripheral provides four 32-bit timer channels and a single 64-bit free running counter.
+// BCM2835_ST_CLO is the System Timer Counter Lower bits register.
+// The system timer free-running counter lower register is a read-only register that returns the current value
+// of the lower 32-bits of the free running counter.
+// BCM2835_ST_CHI is the System Timer Counter Upper bits register.
+// The system timer free-running counter upper register is a read-only register that returns the current value
+// of the upper 32-bits of the free running counter.
+#define BCM2835_ST_CS 							0x0000 ///< System Timer Control/Status
+#define BCM2835_ST_CLO 							0x0004 ///< System Timer Counter Lower 32 bits
+#define BCM2835_ST_CHI 							0x0008 ///< System Timer Counter Upper 32 bits
+
+/// @}
+
+
+// Defines for PWM
+#define BCM2835_PWM_CONTROL 0
+#define BCM2835_PWM_STATUS  1
+#define BCM2835_PWM0_RANGE  4
+#define BCM2835_PWM0_DATA   5
+#define BCM2835_PWM1_RANGE  8
+#define BCM2835_PWM1_DATA   9
+
+#define BCM2835_PWMCLK_CNTL     40
+#define BCM2835_PWMCLK_DIV      41
+
+#define BCM2835_PWM1_MS_MODE    0x8000  /// Run in MS mode
+#define BCM2835_PWM1_USEFIFO    0x2000  /// Data from FIFO
+#define BCM2835_PWM1_REVPOLAR   0x1000  /// Reverse polarity
+#define BCM2835_PWM1_OFFSTATE   0x0800  /// Ouput Off state
+#define BCM2835_PWM1_REPEATFF   0x0400  /// Repeat last value if FIFO empty
+#define BCM2835_PWM1_SERIAL     0x0200  /// Run in serial mode
+#define BCM2835_PWM1_ENABLE     0x0100  /// Channel Enable
+
+#define BCM2835_PWM0_MS_MODE    0x0080  /// Run in MS mode
+#define BCM2835_PWM0_USEFIFO    0x0020  /// Data from FIFO
+#define BCM2835_PWM0_REVPOLAR   0x0010  /// Reverse polarity
+#define BCM2835_PWM0_OFFSTATE   0x0008  /// Ouput Off state
+#define BCM2835_PWM0_REPEATFF   0x0004  /// Repeat last value if FIFO empty
+#define BCM2835_PWM0_SERIAL     0x0002  /// Run in serial mode
+#define BCM2835_PWM0_ENABLE     0x0001  /// Channel Enable
+
+// Historical name compatibility
+#ifndef BCM2835_NO_DELAY_COMPATIBILITY
+#define delay(x) bcm2835_delay(x)
+#define delayMicroseconds(x) bcm2835_delayMicroseconds(x)
+#define millis() bcm2835_millis()
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+    /// \defgroup init Library initialisation and management
+    /// These functions allow you to intialise and control the bcm2835 library
+    /// @{
+
+    /// Initialise the library by opening /dev/mem and getting pointers to the 
+    /// internal memory for BCM 2835 device registers. You must call this (successfully)
+    /// before calling any other 
+    /// functions in this library (except bcm2835_set_debug). 
+    /// If bcm2835_init() fails by returning 0, 
+    /// calling any other function may result in crashes or other failures.
+    /// Prints messages to stderr in case of errors.
+    /// \return 1 if successful else 0
+    extern int bcm2835_init(void);
+
+    /// Close the library, deallocating any allocated memory and closing /dev/mem
+    /// \return 1 if successful else 0
+    extern int bcm2835_close(void);
+		
+    /// Returns the revision of the Raspberry PI board
+    /// \return the value of revision (0 if error else 1 or 2)
+		extern int bcm2835_get_pi_version( void ) ;
+
+    /// Sets the debug level of the library.
+    /// A value of 1 prevents mapping to /dev/mem, and makes the library print out
+    /// what it would do, rather than accessing the GPIO registers.
+    /// A value of 0, the default, causes normal operation.
+    /// Call this before calling bcm2835_init();
+    /// \param[in] debug The new debug level. 1 means debug
+    extern void  bcm2835_set_debug(uint8_t debug);
+
+    /// @} // end of init
+
+    /// \defgroup lowlevel Low level register access
+    /// These functions provide low level register access, and should not generally
+    /// need to be used 
+    /// 
+    /// @{
+
+    /// Reads 32 bit value from a peripheral address
+    /// The read is done twice, and is therefore always safe in terms of 
+    /// manual section 1.3 Peripheral access precautions for correct memory ordering
+    /// \param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.
+    /// \return the value read from the 32 bit register
+    /// \sa Physical Addresses
+    extern uint32_t bcm2835_peri_read(volatile uint32_t* paddr);
+
+
+    /// Reads 32 bit value from a peripheral address without the read barrier
+    /// You should only use this when your code has previously called bcm2835_peri_read()
+    /// within the same peripheral, and no other peripheral access has occurred since.
+    /// \param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.
+    /// \return the value read from the 32 bit register
+    /// \sa Physical Addresses
+    extern uint32_t bcm2835_peri_read_nb(volatile uint32_t* paddr);
+
+
+    /// Writes 32 bit value from a peripheral address
+    /// The write is done twice, and is therefore always safe in terms of 
+    /// manual section 1.3 Peripheral access precautions for correct memory ordering
+    /// \param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.
+    /// \param[in] value The 32 bit value to write
+    /// \sa Physical Addresses
+    extern void bcm2835_peri_write(volatile uint32_t* paddr, uint32_t value);
+
+    /// Writes 32 bit value from a peripheral address without the write barrier
+    /// You should only use this when your code has previously called bcm2835_peri_write()
+    /// within the same peripheral, and no other peripheral access has occurred since.
+    /// \param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.
+    /// \param[in] value The 32 bit value to write
+    /// \sa Physical Addresses
+    extern void bcm2835_peri_write_nb(volatile uint32_t* paddr, uint32_t value);
+
+    /// Alters a number of bits in a 32 peripheral regsiter.
+    /// It reads the current valu and then alters the bits deines as 1 in mask, 
+    /// according to the bit value in value. 
+    /// All other bits that are 0 in the mask are unaffected.
+    /// Use this to alter a subset of the bits in a register.
+    /// The write is done twice, and is therefore always safe in terms of 
+    /// manual section 1.3 Peripheral access precautions for correct memory ordering
+    /// \param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.
+    /// \param[in] value The 32 bit value to write, masked in by mask.
+    /// \param[in] mask Bitmask that defines the bits that will be altered in the register.
+    /// \sa Physical Addresses
+    extern void bcm2835_peri_set_bits(volatile uint32_t* paddr, uint32_t value, uint32_t mask);
+    /// @} // end of lowlevel
+
+    /// \defgroup gpio GPIO register access
+    /// These functions allow you to control the GPIO interface. You can set the 
+    /// function of each GPIO pin, read the input state and set the output state.
+    /// @{
+
+    /// Sets the Function Select register for the given pin, which configures
+    /// the pin as Input, Output or one of the 6 alternate functions.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from RPiGPIOPin.
+    /// \param[in] mode Mode to set the pin to, one of BCM2835_GPIO_FSEL_* from \ref bcm2835FunctionSelect
+    extern void bcm2835_gpio_fsel(uint8_t pin, uint8_t mode);
+
+    /// Sets the specified pin output to 
+    /// HIGH.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    /// \sa bcm2835_gpio_write()
+    extern void bcm2835_gpio_set(uint8_t pin);
+
+    /// Sets the specified pin output to 
+    /// LOW.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    /// \sa bcm2835_gpio_write()
+    extern void bcm2835_gpio_clr(uint8_t pin);
+
+    /// Sets any of the first 32 GPIO output pins specified in the mask to 
+    /// HIGH.
+    /// \param[in] mask Mask of pins to affect. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)
+    /// \sa bcm2835_gpio_write_multi()
+    extern void bcm2835_gpio_set_multi(uint32_t mask);
+
+    /// Sets any of the first 32 GPIO output pins specified in the mask to 
+    /// LOW.
+    /// \param[in] mask Mask of pins to affect. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)
+    /// \sa bcm2835_gpio_write_multi()
+    extern void bcm2835_gpio_clr_multi(uint32_t mask);
+
+    /// Reads the current level on the specified 
+    /// pin and returns either HIGH or LOW. Works whether or not the pin
+    /// is an input or an output.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    /// \return the current level  either HIGH or LOW
+    extern uint8_t bcm2835_gpio_lev(uint8_t pin);
+
+    /// Event Detect Status.
+    /// Tests whether the specified pin has detected a level or edge
+    /// as requested by bcm2835_gpio_ren(), bcm2835_gpio_fen(), bcm2835_gpio_hen(), 
+    /// bcm2835_gpio_len(), bcm2835_gpio_aren(), bcm2835_gpio_afen().
+    /// Clear the flag for a given pin by calling bcm2835_gpio_set_eds(pin);
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    /// \return HIGH if the event detect status for th given pin is true.
+    extern uint8_t bcm2835_gpio_eds(uint8_t pin);
+
+    /// Sets the Event Detect Status register for a given pin to 1, 
+    /// which has the effect of clearing the flag. Use this afer seeing
+    /// an Event Detect Status on the pin.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    extern void bcm2835_gpio_set_eds(uint8_t pin);
+
+    /// Enable Rising Edge Detect Enable for the specified pin.
+    /// When a rising edge is detected, sets the appropriate pin in Event Detect Status.
+    /// The GPRENn registers use
+    /// synchronous edge detection. This means the input signal is sampled using the
+    /// system clock and then it is looking for a ?011? pattern on the sampled signal. This
+    /// has the effect of suppressing glitches.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    extern void bcm2835_gpio_ren(uint8_t pin);
+
+    /// Disable Rising Edge Detect Enable for the specified pin.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    extern void bcm2835_gpio_clr_ren(uint8_t pin);
+
+    /// Enable Falling Edge Detect Enable for the specified pin.
+    /// When a falling edge is detected, sets the appropriate pin in Event Detect Status.
+    /// The GPRENn registers use
+    /// synchronous edge detection. This means the input signal is sampled using the
+    /// system clock and then it is looking for a ?100? pattern on the sampled signal. This
+    /// has the effect of suppressing glitches.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    extern void bcm2835_gpio_fen(uint8_t pin);
+
+    /// Disable Falling Edge Detect Enable for the specified pin.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    extern void bcm2835_gpio_clr_fen(uint8_t pin);
+
+    /// Enable High Detect Enable for the specified pin.
+    /// When a HIGH level is detected on the pin, sets the appropriate pin in Event Detect Status.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    extern void bcm2835_gpio_hen(uint8_t pin);
+
+    /// Disable High Detect Enable for the specified pin.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    extern void bcm2835_gpio_clr_hen(uint8_t pin);
+
+    /// Enable Low Detect Enable for the specified pin.
+    /// When a LOW level is detected on the pin, sets the appropriate pin in Event Detect Status.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    extern void bcm2835_gpio_len(uint8_t pin);
+
+    /// Disable Low Detect Enable for the specified pin.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    extern void bcm2835_gpio_clr_len(uint8_t pin);
+
+    /// Enable Asynchronous Rising Edge Detect Enable for the specified pin.
+    /// When a rising edge is detected, sets the appropriate pin in Event Detect Status.
+    /// Asynchronous means the incoming signal is not sampled by the system clock. As such
+    /// rising edges of very short duration can be detected.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    extern void bcm2835_gpio_aren(uint8_t pin);
+
+    /// Disable Asynchronous Rising Edge Detect Enable for the specified pin.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    extern void bcm2835_gpio_clr_aren(uint8_t pin);
+
+    /// Enable Asynchronous Falling Edge Detect Enable for the specified pin.
+    /// When a falling edge is detected, sets the appropriate pin in Event Detect Status.
+    /// Asynchronous means the incoming signal is not sampled by the system clock. As such
+    /// falling edges of very short duration can be detected.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    extern void bcm2835_gpio_afen(uint8_t pin);
+
+    /// Disable Asynchronous Falling Edge Detect Enable for the specified pin.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    extern void bcm2835_gpio_clr_afen(uint8_t pin);
+
+    /// Sets the Pull-up/down register for the given pin. This is
+    /// used with bcm2835_gpio_pudclk() to set the  Pull-up/down resistor for the given pin.
+    /// However, it is usually more convenient to use bcm2835_gpio_set_pud().
+    /// \param[in] pud The desired Pull-up/down mode. One of BCM2835_GPIO_PUD_* from bcm2835PUDControl
+    /// \sa bcm2835_gpio_set_pud()
+    extern void bcm2835_gpio_pud(uint8_t pud);
+
+    /// Clocks the Pull-up/down value set earlier by bcm2835_gpio_pud() into the pin.
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    /// \param[in] on HIGH to clock the value from bcm2835_gpio_pud() into the pin. 
+    /// LOW to remove the clock. 
+    /// \sa bcm2835_gpio_set_pud()
+    extern void bcm2835_gpio_pudclk(uint8_t pin, uint8_t on);
+
+    /// Reads and returns the Pad Control for the given GPIO group.
+    /// \param[in] group The GPIO pad group number, one of BCM2835_PAD_GROUP_GPIO_*
+    /// \return Mask of bits from BCM2835_PAD_* from \ref bcm2835PadGroup
+    extern uint32_t bcm2835_gpio_pad(uint8_t group);
+
+    /// Sets the Pad Control for the given GPIO group.
+    /// \param[in] group The GPIO pad group number, one of BCM2835_PAD_GROUP_GPIO_*
+    /// \param[in] control Mask of bits from BCM2835_PAD_* from \ref bcm2835PadGroup
+    extern void bcm2835_gpio_set_pad(uint8_t group, uint32_t control);
+
+    /// Delays for the specified number of milliseconds.
+    /// Uses nanosleep(), and therefore does not use CPU until the time is up.
+    /// However, you are at the mercy of nanosleep(). From the manual for nanosleep():
+    /// If the interval specified in req is not an exact multiple of the granularity  
+    /// underlying  clock  (see  time(7)),  then the interval will be
+    /// rounded up to the next multiple. Furthermore, after the sleep completes, 
+    /// there may still be a delay before the CPU becomes free to once
+    /// again execute the calling thread.
+    /// \param[in] millis Delay in milliseconds
+    extern void bcm2835_delay (unsigned int millis);
+
+    /// Delays for the specified number of microseconds.
+    /// Uses a combination of nanosleep() and a busy wait loop on the BCM2835 system timers,
+    /// However, you are at the mercy of nanosleep(). From the manual for nanosleep():
+    /// If the interval specified in req is not an exact multiple of the granularity  
+    /// underlying  clock  (see  time(7)),  then the interval will be
+    /// rounded up to the next multiple. Furthermore, after the sleep completes, 
+    /// there may still be a delay before the CPU becomes free to once
+    /// again execute the calling thread.
+    /// For times less than about 450 microseconds, uses a busy wait on the System Timer.
+    /// It is reported that a delay of 0 microseconds on RaspberryPi will in fact
+    /// result in a delay of about 80 microseconds. Your mileage may vary.
+    /// \param[in] micros Delay in microseconds
+    extern void bcm2835_delayMicroseconds (uint64_t micros);
+		
+    /// Indicate the number of milliseconds since startup of PI
+		/// This function is like the Arduino millis function
+    /// \return Number of milliseconds
+		extern unsigned int bcm2835_millis(void);
+
+    /// Sets the output state of the specified pin
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    /// \param[in] on HIGH sets the output to HIGH and LOW to LOW.
+    extern void bcm2835_gpio_write(uint8_t pin, uint8_t on);
+
+    /// Sets any of the first 32 GPIO output pins specified in the mask to the state given by on
+    /// \param[in] mask Mask of pins to affect. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)
+    /// \param[in] on HIGH sets the output to HIGH and LOW to LOW.
+    extern void bcm2835_gpio_write_multi(uint32_t mask, uint8_t on);
+
+    /// Sets the first 32 GPIO output pins specified in the mask to the value given by value
+    /// \param[in] value values required for each bit masked in by mask, eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)
+    /// \param[in] mask Mask of pins to affect. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)
+    extern void bcm2835_gpio_write_mask(uint32_t value, uint32_t mask);
+
+    /// Sets the Pull-up/down mode for the specified pin. This is more convenient than
+    /// clocking the mode in with bcm2835_gpio_pud() and bcm2835_gpio_pudclk().
+    /// \param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.
+    /// \param[in] pud The desired Pull-up/down mode. One of BCM2835_GPIO_PUD_* from bcm2835PUDControl
+    extern void bcm2835_gpio_set_pud(uint8_t pin, uint8_t pud);
+
+    /// @} 
+
+    /// \defgroup spi SPI access
+    /// These functions let you use SPI0 (Serial Peripheral Interface) to 
+    /// interface with an external SPI device.
+    /// @{
+
+    /// Start SPI operations.
+    /// Forces RPi SPI0 pins P1-19 (MOSI), P1-21 (MISO), P1-23 (CLK), P1-24 (CE0) and P1-26 (CE1)
+    /// to alternate function ALT0, which enables those pins for SPI interface.
+    /// \param[in] cs Specifies the CS pins(s) that are used to activate the desired slave. 
+    ///   One of BCM2835_SPI_CS*, see \ref bcm2835SPIChipSelect
+    ///   or one of One of BCM2835_SPI_CS*, see \ref bcm2835SPIChipSelect
+		///   by default PI hardware driven using CE0
+    /// You should call bcm2835_spi_end() when all SPI funcitons are complete to return the pins to 
+    /// their default functions
+    /// \sa  bcm2835_spi_end()
+    extern void bcm2835_spi_begin(uint8_t cs);
+
+    /// End SPI operations.
+    /// SPI0 pins P1-19 (MOSI), P1-21 (MISO), P1-23 (CLK), P1-24 (CE0) and P1-26 (CE1)
+    /// are returned to their default INPUT behaviour.
+    extern void bcm2835_spi_end(void);
+		
+    /// Sets the SPI custom Chip Select pin to correct level
+    /// Defaults to 
+    /// \param[in] level The desired level, LOW or HIGH, 
+		extern void bcm2835_spi_setChipSelect(uint8_t level);
+		
+    /// Sets the SPI bit order
+    /// NOTE: has no effect. Not supported by SPI0.
+    /// Defaults to 
+    /// \param[in] order The desired bit order, one of BCM2835_SPI_BIT_ORDER_*, 
+    /// see \ref bcm2835SPIBitOrder
+    extern void bcm2835_spi_setBitOrder(uint8_t order);
+
+    /// Sets the SPI clock divider and therefore the 
+    /// SPI clock speed. 
+    /// \param[in] divider The desired SPI clock divider, one of BCM2835_SPI_CLOCK_DIVIDER_*, 
+    /// see \ref bcm2835SPIClockDivider
+    extern void bcm2835_spi_setClockDivider(uint16_t divider);
+    
+		/// Sets the SPI clock speed.
+    /// \param[in] speed The desired SPI speed, one of BCM2835_SPI_CLOCK_SPEED_*, 
+    /// see \ref bcm2835SPIClockSpeed
+    extern void bcm2835_spi_setClockSpeed(uint16_t divider);
+		
+    /// Sets the SPI data mode
+    /// Sets the clock polariy and phase
+    /// \param[in] mode The desired data mode, one of BCM2835_SPI_MODE*, 
+    /// see \ref bcm2835SPIMode
+    extern void bcm2835_spi_setDataMode(uint8_t mode);
+
+    /// Sets the chip select pin(s)
+    /// When an bcm2835_spi_transfer() is made, the selected pin(s) will be asserted during the
+    /// transfer.
+    /// \param[in] cs Specifies the CS pins(s) that are used to activate the desired slave. 
+    ///   One of BCM2835_SPI_CS*, see \ref bcm2835SPIChipSelect
+    ///   or one of One of BCM2835_SPI_CS*, see \ref bcm2835SPIChipSelect
+    extern void bcm2835_spi_chipSelect(uint8_t cs);
+
+    /// Sets the chip select pin polarity for a given pin
+    /// When an bcm2835_spi_transfer() occurs, the currently selected chip select pin(s) 
+    /// will be asserted to the 
+    /// value given by active. When transfers are not happening, the chip select pin(s) 
+    /// return to the complement (inactive) value.
+    /// \param[in] cs The chip select pin to affect
+    /// \param[in] active Whether the chip select pin is to be active HIGH
+    extern void bcm2835_spi_setChipSelectPolarity(uint8_t cs, uint8_t active);
+
+    /// Transfers one byte to and from the currently selected SPI slave.
+    /// Asserts the currently selected CS pins (as previously set by bcm2835_spi_chipSelect) 
+    /// during the transfer.
+    /// Clocks the 8 bit value out on MOSI, and simultaneously clocks in data from MISO. 
+    /// Returns the read data byte from the slave.
+    /// Uses polled transfer as per section 10.6.1 of the BCM 2835 ARM Peripherls manual
+    /// \param[in] value The 8 bit data byte to write to MOSI
+    /// \return The 8 bit byte simultaneously read from  MISO
+    /// \sa bcm2835_spi_transfern()
+    extern uint8_t bcm2835_spi_transfer(uint8_t value);
+    
+    /// Transfers any number of bytes to and from the currently selected SPI slave.
+    /// Asserts the currently selected CS pins (as previously set by bcm2835_spi_chipSelect) 
+    /// during the transfer.
+    /// Clocks the len 8 bit bytes out on MOSI, and simultaneously clocks in data from MISO. 
+    /// The data read read from the slave is placed into rbuf. rbuf must be at least len bytes long
+    /// Uses polled transfer as per section 10.6.1 of the BCM 2835 ARM Peripherls manual
+    /// \param[in] tbuf Buffer of bytes to send. 
+    /// \param[out] rbuf Received bytes will by put in this buffer
+    /// \param[in] len Number of bytes in the tbuf buffer, and the number of bytes to send/received
+    /// \sa bcm2835_spi_transfer()
+    extern void bcm2835_spi_transfernb(char* tbuf, char* rbuf, uint32_t len);
+
+    /// Transfers any number of bytes to and from the currently selected SPI slave
+    /// using bcm2835_spi_transfernb.
+    /// The returned data from the slave replaces the transmitted data in the buffer.
+    /// \param[in,out] buf Buffer of bytes to send. Received bytes will replace the contents
+    /// \param[in] len Number of bytes int eh buffer, and the number of bytes to send/received
+    /// \sa bcm2835_spi_transfer()
+    extern void bcm2835_spi_transfern(char* buf, uint32_t len);
+
+    /// Transfers any number of bytes to the currently selected SPI slave.
+    /// Asserts the currently selected CS pins (as previously set by bcm2835_spi_chipSelect)
+    /// during the transfer.
+    /// \param[in] buf Buffer of bytes to send.
+    /// \param[in] len Number of bytes in the tbuf buffer, and the number of bytes to send
+    extern void bcm2835_spi_writenb(char* buf, uint32_t len);
+
+    /// @}
+
+    /// \defgroup i2c I2C access
+    /// These functions let you use I2C (The Broadcom Serial Control bus with the Philips
+    /// I2C bus/interface version 2.1 January 2000.) to interface with an external I2C device.
+    /// @{
+
+    /// Start I2C operations.
+    /// Forces RPi I2C pins P1-03 (SDA) and P1-05 (SCL)
+    /// to alternate function ALT0, which enables those pins for I2C interface.
+    /// You should call bcm2835_i2c_end() when all I2C functions are complete to return the pins to
+    /// their default functions
+    /// \sa  bcm2835_i2c_end()
+    extern void bcm2835_i2c_begin(void);
+
+    /// End I2C operations.
+    /// I2C pins P1-03 (SDA) and P1-05 (SCL)
+    /// are returned to their default INPUT behaviour.
+    extern void bcm2835_i2c_end(void);
+
+    /// Sets the I2C slave address.
+    /// \param[in] addr The I2C slave address.
+    extern void bcm2835_i2c_setSlaveAddress(uint8_t addr);
+
+    /// Sets the I2C clock divider and therefore the I2C clock speed.
+    /// \param[in] divider The desired I2C clock divider, one of BCM2835_I2C_CLOCK_DIVIDER_*,
+    /// see \ref bcm2835I2CClockDivider
+    extern void bcm2835_i2c_setClockDivider(uint16_t divider);
+
+    /// Transfers any number of bytes to the currently selected I2C slave.
+    /// (as previously set by \sa bcm2835_i2c_setSlaveAddress)
+    /// \param[in] buf Buffer of bytes to send.
+    /// \param[in] len Number of bytes in the buf buffer, and the number of bytes to send.
+	/// \return reason see \ref bcm2835I2CReasonCodes
+    extern uint8_t bcm2835_i2c_write(const char * buf, uint32_t len);
+
+    /// Transfers any number of bytes from the currently selected I2C slave.
+    /// (as previously set by \sa bcm2835_i2c_setSlaveAddress)
+    /// \param[in] buf Buffer of bytes to receive.
+    /// \param[in] len Number of bytes in the buf buffer, and the number of bytes to received.
+	/// \return reason see \ref bcm2835I2CReasonCodes
+    extern uint8_t bcm2835_i2c_read(char* buf, uint32_t len);
+
+    /// @}
+
+    /// \defgroup st System Timer access
+    /// Allows access to and delays using the System Timer Counter.
+    /// @{
+
+    /// Read the System Timer Counter register.
+    /// \return the value read from the System Timer Counter Lower 32 bits register
+    uint64_t bcm2835_st_read(void);
+
+    /// Delays for the specified number of microseconds with offset.
+    /// \param[in] offset_micros Offset in microseconds
+    /// \param[in] micros Delay in microseconds
+    extern void bcm2835_st_delay(uint64_t offset_micros, uint64_t micros);
+
+    /// @} 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BCM2835_H
+
+/// @example blink.c
+/// Blinks RPi GPIO pin 11 on and off
+
+/// @example input.c
+/// Reads the state of an RPi input pin
+
+/// @example event.c
+/// Shows how to use event detection on an input pin
+
+/// @example spi.c
+/// Shows how to use SPI interface to transfer a byte to and from an SPI device
+
+/// @example spin.c
+/// Shows how to use SPI interface to transfer a number of bytes to and from an SPI device
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/Makefile b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/Makefile
new file mode 100644
index 0000000..96d8f5f
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/Makefile
@@ -0,0 +1,40 @@
+#############################################################################
+#
+# Makefile for librf24 examples on Raspberry Pi
+#
+# License: GPL (General Public License)
+# Author:  gnulnulf 
+# Date:    2013/02/07 (version 1.0)
+#
+# Description:
+# ------------
+# use make all and make install to install the examples
+# You can change the install directory by editing the prefix line
+#
+prefix := /usr/local
+
+# The recommended compiler flags for the Raspberry Pi
+CCFLAGS=-Ofast -mfpu=vfp -mfloat-abi=hard -march=armv6zk -mtune=arm1176jzf-s
+#CCFLAGS=
+
+# define all programs
+#PROGRAMS = scanner pingtest pongtest
+PROGRAMS = rpi-hub scanner pingtest pongtest
+SOURCES = ${PROGRAMS:=.cpp}
+
+all: ${PROGRAMS}
+
+${PROGRAMS}: ${SOURCES}
+	g++ ${CCFLAGS} -Wall -I../ -lrf24-bcm $@.cpp -o $@
+
+clean:
+	rm -rf $(PROGRAMS)
+
+install: all
+	test -d $(prefix) || mkdir $(prefix)
+	test -d $(prefix)/bin || mkdir $(prefix)/bin
+	for prog in $(PROGRAMS); do \
+	  install -m 0755 $$prog $(prefix)/bin; \
+	done
+
+.PHONY: install
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/pingtest.cpp b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/pingtest.cpp
new file mode 100644
index 0000000..380bd2e
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/pingtest.cpp
@@ -0,0 +1,230 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ 
+ 03/17/2013 : Charles-Henri Hallard (http://hallard.me)
+              Modified to use with Arduipi board http://hallard.me/arduipi
+						  Changed to use modified bcm2835 and RF24 library 
+ */
+
+/**
+ * Example RF Radio Ping Pair
+ *
+ * This is an example of how to use the RF24 class.  Write this sketch to two different nodes,
+ * connect the role_pin to ground on one.  The ping node sends the current time to the pong node,
+ * which responds by sending the value back.  The ping node can then see how long the whole cycle
+ * took.
+ */
+
+#include 
+#include 
+#include "./RF24.h"
+
+//
+// Hardware configuration
+//
+
+// CE Pin, CSN Pin, SPI Speed
+
+// Setup for GPIO 22 CE and GPIO 25 CSN with SPI Speed @ 1Mhz
+//RF24 radio(RPI_V2_GPIO_P1_22, RPI_V2_GPIO_P1_18, BCM2835_SPI_SPEED_1MHZ);
+
+// Setup for GPIO 22 CE and CE0 CSN with SPI Speed @ 4Mhz
+//RF24 radio(RPI_V2_GPIO_P1_15, BCM2835_SPI_CS0, BCM2835_SPI_SPEED_4MHZ); 
+
+// Setup for GPIO 22 CE and CE1 CSN with SPI Speed @ 8Mhz
+RF24 radio(RPI_V2_GPIO_P1_15, RPI_V2_GPIO_P1_26, BCM2835_SPI_SPEED_8MHZ);  
+
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'ping' transmitter
+const int role_pin = 7;
+
+//
+// Topology
+//
+
+// Radio pipe addresses for the 2 nodes to communicate.
+const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL };
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes
+// in this system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_ping_out = 1, role_pong_back } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"};
+
+// The role of the current running sketch
+role_e role;
+
+
+int main(int argc, char** argv)
+{
+  //
+  // Role
+  //
+
+  // set up the role 
+  role = role_ping_out;
+
+  //
+  // Print preamble:
+  //
+
+  printf("RF24/examples/pingtest/\n");
+  printf("ROLE: %s\n",role_friendly_name[role]);
+
+  //
+  // Setup and configure rf radio
+  //
+  radio.begin();
+
+  // optionally, increase the delay between retries & # of retries
+  radio.setRetries(15,15);
+
+  // optionally, reduce the payload size.  seems to
+  // improve reliability
+	//  radio.setPayloadSize(8);
+	radio.setChannel(0x4c);
+  radio.setPALevel(RF24_PA_LOW);
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens two pipes for these two nodes to communicate
+  // back and forth.
+  // Open 'our' pipe for writing
+  // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading)
+  if ( role == role_ping_out )
+  {
+    radio.openWritingPipe(pipes[0]);
+    radio.openReadingPipe(1,pipes[1]);
+  }
+  else
+  {
+    radio.openWritingPipe(pipes[1]);
+    radio.openReadingPipe(1,pipes[0]);
+  }
+
+  //
+  // Start listening
+  //
+  radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+  radio.printDetails();
+  //
+  // Ping out role.  Repeatedly send the current time
+  //
+	
+	// forever loop
+	while (1)
+	{
+		if (role == role_ping_out)
+		{
+			// First, stop listening so we can talk.
+			radio.stopListening();
+
+			// Take the time, and send it.  This will block until complete
+			unsigned long time = millis();
+			printf("Now sending %lu...",time);
+			bool ok = radio.write( &time, sizeof(unsigned long) );
+			
+			if (ok)
+				printf("ok...");
+			else
+				printf("failed.\n");
+
+			// Now, continue listening
+			radio.startListening();
+
+			// Wait here until we get a response, or timeout (250ms)
+			unsigned long started_waiting_at = millis();
+			bool timeout = false;
+			while ( ! radio.available() && ! timeout ) {
+					// by bcatalin » Thu Feb 14, 2013 11:26 am
+					delay(5); //add a small delay to let radio.available to check payload
+				if (millis() - started_waiting_at > 200 )
+					timeout = true;
+			}
+
+
+			// Describe the results
+			if ( timeout )
+			{
+				printf("Failed, response timed out.\n");
+			}
+			else
+			{
+				// Grab the response, compare, and send to debugging spew
+				unsigned long got_time;
+				radio.read( &got_time, sizeof(unsigned long) );
+
+				// Spew it
+				printf("Got response %lu, round-trip delay: %lu\n",got_time,millis()-got_time);
+			}
+
+			// Try again 1s later
+			//    delay(1000);
+			sleep(1);
+			
+		}
+
+		//
+		// Pong back role.  Receive each packet, dump it out, and send it back
+		//
+
+		if ( role == role_pong_back )
+		{
+			// if there is data ready
+			//printf("Check available...\n");
+			if ( radio.available() )
+			{
+				// Dump the payloads until we've gotten everything
+				unsigned long got_time;
+				bool done = false;
+				
+				while (!done)
+				{
+					// Fetch the payload, and see if this was the last one.
+					done = radio.read( &got_time, sizeof(unsigned long) );
+
+					// Spew it
+					printf("Got payload(%d) %lu...\n",sizeof(unsigned long), got_time);
+
+					// Delay just a little bit to let the other unit
+					// make the transition to receiver
+					delay(20);
+				}
+
+				// First, stop listening so we can talk
+				radio.stopListening();
+
+				// Send the final one back.
+				radio.write( &got_time, sizeof(unsigned long) );
+
+				// Now, resume listening so we catch the next packets.
+				radio.startListening();
+			}
+		}
+	} // forever loop
+
+  return 0;
+}
+
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/pongtest.cpp b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/pongtest.cpp
new file mode 100644
index 0000000..24e674a
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/pongtest.cpp
@@ -0,0 +1,229 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ 
+ 03/17/2013 : Charles-Henri Hallard (http://hallard.me)
+              Modified to use with Arduipi board http://hallard.me/arduipi
+						  Changed to use modified bcm2835 and RF24 library 
+
+ */
+
+/**
+ * Example RF Radio Ping Pair
+ *
+ * This is an example of how to use the RF24 class.  Write this sketch to two different nodes,
+ * connect the role_pin to ground on one.  The ping node sends the current time to the pong node,
+ * which responds by sending the value back.  The ping node can then see how long the whole cycle
+ * took.
+ */
+
+#include 
+#include 
+#include "./RF24.h"
+
+//
+// Hardware configuration
+//
+
+// CE Pin, CSN Pin, SPI Speed
+
+// Setup for GPIO 22 CE and GPIO 25 CSN with SPI Speed @ 1Mhz
+//RF24 radio(RPI_V2_GPIO_P1_22, RPI_V2_GPIO_P1_18, BCM2835_SPI_SPEED_1MHZ);
+
+// Setup for GPIO 22 CE and CE0 CSN with SPI Speed @ 4Mhz
+//RF24 radio(RPI_V2_GPIO_P1_15, BCM2835_SPI_CS0, BCM2835_SPI_SPEED_4MHZ); 
+
+// Setup for GPIO 22 CE and CE1 CSN with SPI Speed @ 8Mhz
+RF24 radio(RPI_V2_GPIO_P1_15, RPI_V2_GPIO_P1_26, BCM2835_SPI_SPEED_8MHZ);  
+
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'ping' transmitter
+const int role_pin = 7;
+
+//
+// Topology
+//
+
+// Radio pipe addresses for the 2 nodes to communicate.
+const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL };
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes
+// in this system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_ping_out = 1, role_pong_back } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"};
+
+// The role of the current running sketch
+role_e role;
+
+
+int main(int argc, char** argv)
+{
+  // Role
+  role = role_pong_back;
+
+  //
+  // Print preamble:
+  //
+
+  //Serial.begin(115200);
+  //printf_begin();
+  printf("RF24/examples/pongtest/\n");
+  printf("ROLE: %s\n",role_friendly_name[role]);
+
+  //
+  // Setup and configure rf radio
+  //
+  radio.begin();
+
+  // optionally, increase the delay between retries & # of retries
+  radio.setRetries(15,15);
+
+  // optionally, reduce the payload size.  seems to
+  // improve reliability
+	//  radio.setPayloadSize(8);
+	radio.setChannel(0x4c);
+  radio.setPALevel(RF24_PA_LOW);
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens two pipes for these two nodes to communicate
+  // back and forth.
+  // Open 'our' pipe for writing
+  // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading)
+  if ( role == role_ping_out )
+  {
+    radio.openWritingPipe(pipes[0]);
+    radio.openReadingPipe(1,pipes[1]);
+  }
+  else
+  {
+    radio.openWritingPipe(pipes[1]);
+    radio.openReadingPipe(1,pipes[0]);
+  }
+
+  //
+  // Start listening
+  //
+  radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+  radio.printDetails();
+  //
+  // Ping out role.  Repeatedly send the current time
+  //
+	
+	// forever loop
+	while (1)
+	{
+		if (role == role_ping_out)
+		{
+			// First, stop listening so we can talk.
+			radio.stopListening();
+
+			// Take the time, and send it.  This will block until complete
+			unsigned long time = millis();
+			printf("Now sending %lu...",time);
+			bool ok = radio.write( &time, sizeof(unsigned long) );
+			
+			if (ok)
+				printf("ok...");
+			else
+				printf("failed.\n");
+
+			// Now, continue listening
+			radio.startListening();
+
+			// Wait here until we get a response, or timeout (250ms)
+			unsigned long started_waiting_at = millis();
+			bool timeout = false;
+			while ( ! radio.available() && ! timeout ) {
+					// by bcatalin » Thu Feb 14, 2013 11:26 am
+					delay(5); //add a small delay to let radio.available to check payload
+				if (millis() - started_waiting_at > 200 )
+					timeout = true;
+			}
+
+
+			// Describe the results
+			if ( timeout )
+			{
+				printf("Failed, response timed out.\n");
+			}
+			else
+			{
+				// Grab the response, compare, and send to debugging spew
+				unsigned long got_time;
+				radio.read( &got_time, sizeof(unsigned long) );
+
+				// Spew it
+				printf("Got response %lu, round-trip delay: %lu\n",got_time,millis()-got_time);
+			}
+
+			// Try again 1s later
+			//    delay(1000);
+			sleep(1);
+			
+		}
+
+		//
+		// Pong back role.  Receive each packet, dump it out, and send it back
+		//
+
+		if ( role == role_pong_back )
+		{
+			// if there is data ready
+			//printf("Check available...\n");
+			if ( radio.available() )
+			{
+				// Dump the payloads until we've gotten everything
+				unsigned long got_time;
+				bool done = false;
+				
+				while (!done)
+				{
+					// Fetch the payload, and see if this was the last one.
+					done = radio.read( &got_time, sizeof(unsigned long) );
+
+					// Spew it
+					printf("Got payload(%d) %lu...\n",sizeof(unsigned long), got_time);
+
+					// Delay just a little bit to let the other unit
+					// make the transition to receiver
+					delay(20);
+				}
+
+				// First, stop listening so we can talk
+				radio.stopListening();
+
+				// Send the final one back.
+				radio.write( &got_time, sizeof(unsigned long) );
+
+				// Now, resume listening so we catch the next packets.
+				radio.startListening();
+			}
+		}
+	} // forever loop
+
+  return 0;
+}
+
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/rpi-hub.cpp b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/rpi-hub.cpp
new file mode 100644
index 0000000..6e1a1a9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/rpi-hub.cpp
@@ -0,0 +1,134 @@
+/* 
+ *
+ *  Filename : rpi-hub.cpp
+ *
+ *  This program makes the RPi as a hub listening to all six pipes from the remote sensor nodes ( usually Arduino )
+ *  and will return the packet back to the sensor on pipe0 so that the sender can calculate the round trip delays
+ *  when the payload matches.
+ *  
+ *  I encounter that at times, it also receive from pipe7 ( or pipe0 ) with content of FFFFFFFFF that I will not sent
+ *  back to the sender
+ *
+ *  Refer to RF24/examples/rpi_hub_arduino/ for the corresponding Arduino sketches to work with this code.
+ * 
+ *  
+ *  CE is not used and CSN is GPIO25 (not pinout)
+ *
+ *  Refer to RPi docs for GPIO numbers
+ *
+ *  Author : Stanley Seow
+ *  e-mail : stanleyseow@gmail.com
+ *  date   : 6th Mar 2013
+ *
+ * 03/17/2013 : Charles-Henri Hallard (http://hallard.me)
+ *              Modified to use with Arduipi board http://hallard.me/arduipi
+ *						  Changed to use modified bcm2835 and RF24 library 
+ *
+ *
+ */
+
+#include 
+#include 
+#include "./RF24.h"
+
+using namespace std;
+
+// Radio pipe addresses for the 2 nodes to communicate.
+// First pipe is for writing, 2nd, 3rd, 4th, 5th & 6th is for reading...
+const uint64_t pipes[6] = 
+					{ 0xF0F0F0F0D2LL, 0xF0F0F0F0E1LL, 
+						0xF0F0F0F0E2LL, 0xF0F0F0F0E3LL, 
+						0xF0F0F0F0F1, 0xF0F0F0F0F2 
+					};
+
+// CE Pin, CSN Pin, SPI Speed
+
+// Setup for GPIO 22 CE and GPIO 25 CSN with SPI Speed @ 1Mhz
+//RF24 radio(RPI_V2_GPIO_P1_22, RPI_V2_GPIO_P1_18, BCM2835_SPI_SPEED_1MHZ);
+
+// Setup for GPIO 22 CE and CE0 CSN with SPI Speed @ 4Mhz
+//RF24 radio(RPI_V2_GPIO_P1_15, BCM2835_SPI_CS0, BCM2835_SPI_SPEED_4MHZ); 
+
+// Setup for GPIO 22 CE and CE1 CSN with SPI Speed @ 8Mhz
+RF24 radio(RPI_V2_GPIO_P1_15, RPI_V2_GPIO_P1_26, BCM2835_SPI_SPEED_8MHZ);  
+
+
+int main(int argc, char** argv) 
+{
+	uint8_t len;
+
+	// Refer to RF24.h or nRF24L01 DS for settings
+	radio.begin();
+	radio.enableDynamicPayloads();
+	radio.setAutoAck(1);
+	radio.setRetries(15,15);
+	radio.setDataRate(RF24_1MBPS);
+	radio.setPALevel(RF24_PA_MAX);
+	radio.setChannel(76);
+	radio.setCRCLength(RF24_CRC_16);
+
+	// Open 6 pipes for readings ( 5 plus pipe0, also can be used for reading )
+	radio.openWritingPipe(pipes[0]);
+	radio.openReadingPipe(1,pipes[1]);
+	radio.openReadingPipe(2,pipes[2]);
+	radio.openReadingPipe(3,pipes[3]);
+	radio.openReadingPipe(4,pipes[4]);
+	radio.openReadingPipe(5,pipes[5]);
+
+	//
+	// Start listening
+	//
+	radio.startListening();
+
+	//
+	// Dump the configuration of the rf unit for debugging
+	//
+	radio.printDetails();
+	
+	printf("Output below : \n");
+	delay(1);
+	
+	while(1)
+	{
+		char receivePayload[32];
+		uint8_t pipe = 1;
+		
+		// Start listening
+		radio.startListening();
+					
+		while ( radio.available(&pipe) ) 
+		{
+			len = radio.getDynamicPayloadSize();
+			radio.read( receivePayload, len );
+
+			// Display it on screen
+			printf("Recv: size=%i payload=%s pipe=%i",len,receivePayload,pipe);
+
+			// Send back payload to sender
+			radio.stopListening();
+
+			// if pipe is 7, do not send it back
+			if ( pipe != 7 ) 
+			{
+				radio.write(receivePayload,len);
+				receivePayload[len]=0;
+				printf("\t Send: size=%i payload=%s pipe:%i\n",len,receivePayload,pipe);
+			}
+			else 
+			{
+				printf("\n");
+			}
+			
+			pipe++;
+			
+			// reset pipe to 0
+			if ( pipe > 6 ) 
+				pipe = 0;
+		}
+		
+		delayMicroseconds(20);
+	}
+	
+	return 0;
+}
+
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/scanner.cpp b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/scanner.cpp
new file mode 100644
index 0000000..3277e8e
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/examples/scanner.cpp
@@ -0,0 +1,146 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ 
+ 
+ 03/17/2013 : Charles-Henri Hallard (http://hallard.me)
+              Modified to use with Arduipi board http://hallard.me/arduipi
+						  Changed to use modified bcm2835 and RF24 library 
+
+ */
+
+/**
+ * Channel scanner
+ *
+ * Example to detect interference on the various channels available.
+ * This is a good diagnostic tool to check whether you're picking a
+ * good channel for your application.
+ *
+ * Inspired by cpixip.
+ * See http://arduino.cc/forum/index.php/topic,54795.0.html
+ */
+
+#include 
+#include 
+#include "./RF24.h"
+
+using namespace std;
+
+//
+// Hardware configuration
+//
+
+// CE Pin, CSN Pin, SPI Speed
+
+// Setup for GPIO 22 CE and GPIO 25 CSN with SPI Speed @ 1Mhz
+//RF24 radio(RPI_V2_GPIO_P1_22, RPI_V2_GPIO_P1_18, BCM2835_SPI_SPEED_1MHZ);
+
+// Setup for GPIO 22 CE and CE0 CSN with SPI Speed @ 4Mhz
+//RF24 radio(RPI_V2_GPIO_P1_15, BCM2835_SPI_CS0, BCM2835_SPI_SPEED_4MHZ); 
+
+// Setup for GPIO 22 CE and CE1 CSN with SPI Speed @ 8Mhz
+RF24 radio(RPI_V2_GPIO_P1_15, RPI_V2_GPIO_P1_26, BCM2835_SPI_SPEED_8MHZ);  
+
+
+//
+// Channel info
+//
+//const uint8_t num_channels = 128;
+const uint8_t num_channels = 120;
+uint8_t values[num_channels];
+
+
+const int num_reps = 100;
+int reset_array=0;
+
+
+int main(int argc, char** argv)
+{
+  //
+  // Print preamble
+  //
+
+  //Serial.begin(57600);
+  //printf_begin();
+  printf("RF24/examples/scanner/\n");
+
+  //
+  // Setup and configure rf radio
+  //
+  radio.begin();
+	
+  radio.setAutoAck(false);
+
+  // Get into standby mode
+  radio.startListening();
+  radio.stopListening();
+
+  radio.printDetails();
+
+  // Print out header, high then low digit
+  int i = 0;
+	
+  while ( i < num_channels )
+  {
+    printf("%x",i>>4);
+    ++i;
+  }
+  printf("\n");
+	
+  i = 0;
+  while ( i < num_channels )
+  {
+    printf("%x",i&0xf);
+    ++i;
+  }
+  printf("\n");       
+	
+	// forever loop
+  while(1)
+	{
+		if ( reset_array == 1 )
+		{	
+			// Clear measurement values
+			memset(values,0,sizeof(values));
+			printf("\n");
+		}
+
+		// Scan all channels num_reps times
+		int i = num_channels;
+		while (i--)
+		{
+			// Select this channel
+			radio.setChannel(i);
+
+			// Listen for a little
+			radio.startListening();
+			delayMicroseconds(128);
+			radio.stopListening();
+
+			// Did we get a carrier?
+			if ( radio.testCarrier() )
+					++values[i];
+			if ( values[i] == 0xf ) 
+			{
+				reset_array = 2;
+			}
+		}
+
+		// Print out channel measurements, clamped to a single hex digit
+		i = 0;
+		while ( i < num_channels )
+		{
+			printf("%x",min(0xf,(values[i]&0xf)));
+			++i;
+		}
+		
+		printf("\n");
+	}
+	
+  return 0;
+}
+
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/nRF24L01.h b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/nRF24L01.h
new file mode 100644
index 0000000..2012ce6
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/nRF24L01.h
@@ -0,0 +1,125 @@
+/*
+    Copyright (c) 2007 Stefan Engelke 
+
+    Permission is hereby granted, free of charge, to any person 
+    obtaining a copy of this software and associated documentation 
+    files (the "Software"), to deal in the Software without 
+    restriction, including without limitation the rights to use, copy, 
+    modify, merge, publish, distribute, sublicense, and/or sell copies 
+    of the Software, and to permit persons to whom the Software is 
+    furnished to do so, subject to the following conditions:
+
+    The above copyright notice and this permission notice shall be 
+    included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
+    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
+    NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 
+    HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 
+    WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 
+    OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
+    DEALINGS IN THE SOFTWARE.
+*/
+
+/* Memory Map */
+#define CONFIG      0x00
+#define EN_AA       0x01
+#define EN_RXADDR   0x02
+#define SETUP_AW    0x03
+#define SETUP_RETR  0x04
+#define RF_CH       0x05
+#define RF_SETUP    0x06
+#define STATUS      0x07
+#define OBSERVE_TX  0x08
+#define CD          0x09
+#define RX_ADDR_P0  0x0A
+#define RX_ADDR_P1  0x0B
+#define RX_ADDR_P2  0x0C
+#define RX_ADDR_P3  0x0D
+#define RX_ADDR_P4  0x0E
+#define RX_ADDR_P5  0x0F
+#define TX_ADDR     0x10
+#define RX_PW_P0    0x11
+#define RX_PW_P1    0x12
+#define RX_PW_P2    0x13
+#define RX_PW_P3    0x14
+#define RX_PW_P4    0x15
+#define RX_PW_P5    0x16
+#define FIFO_STATUS 0x17
+#define DYNPD	    0x1C
+#define FEATURE	    0x1D
+
+/* Bit Mnemonics */
+#define MASK_RX_DR  6
+#define MASK_TX_DS  5
+#define MASK_MAX_RT 4
+#define EN_CRC      3
+#define CRCO        2
+#define PWR_UP      1
+#define PRIM_RX     0
+#define ENAA_P5     5
+#define ENAA_P4     4
+#define ENAA_P3     3
+#define ENAA_P2     2
+#define ENAA_P1     1
+#define ENAA_P0     0
+#define ERX_P5      5
+#define ERX_P4      4
+#define ERX_P3      3
+#define ERX_P2      2
+#define ERX_P1      1
+#define ERX_P0      0
+#define AW          0
+#define ARD         4
+#define ARC         0
+#define PLL_LOCK    4
+#define RF_DR       3
+#define RF_PWR      6
+#define RX_DR       6
+#define TX_DS       5
+#define MAX_RT      4
+#define RX_P_NO     1
+#define TX_FULL     0
+#define PLOS_CNT    4
+#define ARC_CNT     0
+#define TX_REUSE    6
+#define FIFO_FULL   5
+#define TX_EMPTY    4
+#define RX_FULL     1
+#define RX_EMPTY    0
+#define DPL_P5	    5
+#define DPL_P4	    4
+#define DPL_P3	    3
+#define DPL_P2	    2
+#define DPL_P1	    1
+#define DPL_P0	    0
+#define EN_DPL	    2
+#define EN_ACK_PAY  1
+#define EN_DYN_ACK  0
+
+/* Instruction Mnemonics */
+#define R_REGISTER    0x00
+#define W_REGISTER    0x20
+#define REGISTER_MASK 0x1F
+#define ACTIVATE      0x50
+#define R_RX_PL_WID   0x60
+#define R_RX_PAYLOAD  0x61
+#define W_TX_PAYLOAD  0xA0
+#define W_ACK_PAYLOAD 0xA8
+#define FLUSH_TX      0xE1
+#define FLUSH_RX      0xE2
+#define REUSE_TX_PL   0xE3
+#define NOP           0xFF
+
+/* Non-P omissions */
+#define LNA_HCURR   0
+
+/* P model memory Map */
+#define RPD         0x09
+
+/* P model bit Mnemonics */
+#define RF_DR_LOW   5
+#define RF_DR_HIGH  3
+#define RF_PWR_LOW  1
+#define RF_PWR_HIGH 2
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/readme.md b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/readme.md
new file mode 100644
index 0000000..4161ad6
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24-bcm/readme.md
@@ -0,0 +1,49 @@
+this is library to use the nrf24l01 on the raspberry pi.
+
+it's based on the arduino lib from J. Coliz .
+the library was berryfied by Purinda Gunasekara .
+then forked from forked from github stanleyseow/RF24 by myself
+
+setup the library
+=================
+
+Clone or download this repo then go to folder
+cd RF24/librf24-rpi/librf24-bcm/
+
+then 
+
+make ; make install
+
+examples
+========
+
+go to examples subfolder then 
+make ; make install
+
+In my examples I used the NRF on ArduiPi Board 
+http://hallard.me/arduipi
+
+So on example file the instance is created as follow, change the pins according your connections
+
+// Setup for GPIO 22 CE and CE1 CSN with SPI Speed @ 8Mhz
+RF24 radio(RPI_V2_GPIO_P1_15, RPI_V2_GPIO_P1_26, BCM2835_SPI_SPEED_8MHZ);  
+
+
+Pin are
+NRF24L01    RPI       P1 Connector
+nrf-vcc  = rpi-3v3        (01)
+nrf-gnd  = rpi-gnd        (06)
+nrf-ce   = rpi-ce1        (26)
+nrf-csn  = rpi-gpio22     (15)
+nrf-sck  = rpi-sckl       (23)
+nrf-mo   = rpi-mosi       (19)
+nrf-mi   = rpi-miso       (21)
+
+known issues
+============
+none
+
+contact
+=======
+Charles-Henri Hallard http://hallard.me
+
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/Makefile b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/Makefile
new file mode 100644
index 0000000..f9b6231
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/Makefile
@@ -0,0 +1,51 @@
+#############################################################################
+#
+# Makefile for librf24 on Raspberry Pi
+#
+# License: GPL (General Public License)
+# Author:  gnulnulf 
+# Date:    2013/02/07 (version 1.0)
+#
+# Description:
+# ------------
+# use make all and mak install to install the library 
+# You can change the install directory by editing the LIBDIR line
+#
+LIBDIR=/usr/local/lib
+LIBNAME=librf24.so.1.0
+
+
+# The recommended compiler flags for the Raspberry Pi
+CCFLAGS=-Ofast -mfpu=vfp -mfloat-abi=hard -march=armv6zk -mtune=arm1176jzf-s
+
+# make all
+all: librf24
+
+# Make the library
+librf24: RF24.o gpio.o spi.o compatibility.o
+	g++ -shared -Wl,-soname,librf24.so.1 ${CCFLAGS}  -o ${LIBNAME} compatibility.o gpio.o spi.o RF24.o
+
+# Library parts
+RF24.o: RF24.cpp
+	g++ -Wall -fPIC ${CCFLAGS} -c RF24.cpp
+
+gpio.o: gpio.cpp
+	g++ -Wall -fPIC ${CCFLAGS} -c gpio.cpp
+
+spi.o: spi.cpp
+	g++ -Wall -fPIC ${CCFLAGS} -c spi.cpp
+
+compatibility.o: compatibility.c
+	gcc -Wall -fPIC  ${CCFLAGS} -c compatibility.c
+
+# clear build files
+clean:
+	rm -rf *o ${LIBNAME}
+
+# Install the library to LIBPATH
+install: 
+	cp librf24.so.1.0 ${LIBDIR}/${LIBNAME}
+	ln -sf ${LIBDIR}/${LIBNAME} ${LIBDIR}/librf24.so.1
+	ln -sf ${LIBDIR}/${LIBNAME} ${LIBDIR}/librf24.so
+	ldconfig
+
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/RF24.cpp b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/RF24.cpp
new file mode 100644
index 0000000..10a348b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/RF24.cpp
@@ -0,0 +1,1017 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#include "nRF24L01.h"
+#include "RF24_config.h"
+#include "RF24.h"
+
+/****************************************************************************/
+
+void RF24::csn(int mode)
+{
+  // Minimum ideal SPI bus speed is 2x data rate
+  // If we assume 2Mbs data rate and 16Mhz clock, a
+  // divider of 4 is the minimum we want.
+  // CLK:BUS 8Mhz:2Mhz, 16Mhz:4Mhz, or 20Mhz:5Mhz
+#ifdef ARDUINO
+//  spi->setBitOrder(MSBFIRST);
+//  spi->setDataMode(SPI_MODE0);
+//  spi->setClockDivider(SPI_CLOCK_DIV4);
+#endif
+  digitalWrite(csn_pin,mode);
+}
+
+/****************************************************************************/
+
+void RF24::ce(int level)
+{
+  digitalWrite(ce_pin,level);
+}
+
+/****************************************************************************/
+
+uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
+{
+  uint8_t status;
+
+  csn(LOW);
+  status = spi->transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
+  while ( len-- )
+    *buf++ = spi->transfer(0xff);
+
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::read_register(uint8_t reg)
+{
+  csn(LOW);
+  spi->transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
+  uint8_t result = spi->transfer(0xff);
+
+  csn(HIGH);
+  return result;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
+{
+  uint8_t status;
+
+  csn(LOW);
+  status = spi->transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
+  while ( len-- )
+    spi->transfer(*buf++);
+
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::write_register(uint8_t reg, uint8_t value)
+{
+  uint8_t status;
+
+  IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"),reg,value));
+
+  csn(LOW);
+  status = spi->transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
+  spi->transfer(value);
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::write_payload(const void* buf, uint8_t len)
+{
+  uint8_t status;
+
+  const uint8_t* current = reinterpret_cast(buf);
+
+  uint8_t data_len = min(len,payload_size);
+  uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
+  
+  //printf("[Writing %u bytes %u blanks]",data_len,blank_len);
+  
+  csn(LOW);
+  status = spi->transfer( W_TX_PAYLOAD );
+  while ( data_len-- )
+    spi->transfer(*current++);
+  while ( blank_len-- )
+    spi->transfer(0);
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::read_payload(void* buf, uint8_t len)
+{
+  uint8_t status;
+  uint8_t* current = reinterpret_cast(buf);
+
+  uint8_t data_len = min(len,payload_size);
+  uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
+  
+  //printf("[Reading %u bytes %u blanks]",data_len,blank_len);
+  
+  csn(LOW);
+  status = spi->transfer( R_RX_PAYLOAD );
+  while ( data_len-- )
+    *current++ = spi->transfer(0xff);
+  while ( blank_len-- )
+    spi->transfer(0xff);
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::flush_rx(void)
+{
+  uint8_t status;
+
+  csn(LOW);
+  status = spi->transfer( FLUSH_RX );
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::flush_tx(void)
+{
+  uint8_t status;
+
+  csn(LOW);
+  status = spi->transfer( FLUSH_TX );
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+uint8_t RF24::get_status(void)
+{
+  uint8_t status;
+
+  csn(LOW);
+  status = spi->transfer( NOP );
+  csn(HIGH);
+
+  return status;
+}
+
+/****************************************************************************/
+
+void RF24::print_status(uint8_t status)
+{
+  printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"),
+           status,
+           (status & _BV(RX_DR))?1:0,
+           (status & _BV(TX_DS))?1:0,
+           (status & _BV(MAX_RT))?1:0,
+           ((status >> RX_P_NO) & 0b111),
+           (status & _BV(TX_FULL))?1:0
+          );
+}
+
+/****************************************************************************/
+
+void RF24::print_observe_tx(uint8_t value)
+{
+  printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"),
+           value,
+           (value >> PLOS_CNT) & 0b1111,
+           (value >> ARC_CNT) & 0b1111
+          );
+}
+
+/****************************************************************************/
+
+void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty)
+{
+  char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
+  printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
+  while (qty--)
+    printf_P(PSTR(" 0x%02x"),read_register(reg++));
+  printf_P(PSTR("\r\n"));
+}
+
+/****************************************************************************/
+
+void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
+{
+  char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
+  printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
+
+  while (qty--)
+  {
+    uint8_t buffer[5];
+    read_register(reg++,buffer,sizeof buffer);
+
+    printf_P(PSTR(" 0x"));
+    uint8_t* bufptr = buffer + sizeof buffer;
+    while( --bufptr >= buffer )
+      printf_P(PSTR("%02x"),*bufptr);
+  }
+
+  printf_P(PSTR("\r\n"));
+}
+
+/****************************************************************************/
+
+RF24::RF24(string _spidevice, uint32_t _spispeed, uint8_t _cepin):
+spidevice( _spidevice) ,spispeed( _spispeed),ce_pin(_cepin), wide_band(true), p_variant(false),
+  payload_size(32), ack_payload_available(false), dynamic_payloads_enabled(false),
+  pipe0_reading_address(0)
+{
+
+}
+/****************************************************************************/
+
+RF24::RF24(uint8_t _cepin, uint8_t _cspin):
+  ce_pin(_cepin), csn_pin(_cspin), wide_band(true), p_variant(false), 
+  payload_size(32), ack_payload_available(false), dynamic_payloads_enabled(false),
+  pipe0_reading_address(0)
+{
+}
+
+/****************************************************************************/
+
+void RF24::setChannel(uint8_t channel)
+{
+  // TODO: This method could take advantage of the 'wide_band' calculation
+  // done in setChannel() to require certain channel spacing.
+
+  const uint8_t max_channel = 127;
+  write_register(RF_CH,min(channel,max_channel));
+}
+
+/****************************************************************************/
+
+void RF24::setPayloadSize(uint8_t size)
+{
+  const uint8_t max_payload_size = 32;
+  payload_size = min(size,max_payload_size);
+}
+
+/****************************************************************************/
+
+uint8_t RF24::getPayloadSize(void)
+{
+  return payload_size;
+}
+
+/****************************************************************************/
+
+static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS";
+static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS";
+static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS";
+static const char * const rf24_datarate_e_str_P[] PROGMEM = {
+  rf24_datarate_e_str_0,
+  rf24_datarate_e_str_1,
+  rf24_datarate_e_str_2,
+};
+static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01";
+static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+";
+static const char * const rf24_model_e_str_P[] PROGMEM = {
+  rf24_model_e_str_0,
+  rf24_model_e_str_1,
+};
+static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled";
+static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits";
+static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ;
+static const char * const rf24_crclength_e_str_P[] PROGMEM = {
+  rf24_crclength_e_str_0,
+  rf24_crclength_e_str_1,
+  rf24_crclength_e_str_2,
+};
+static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN";
+static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW";
+static const char rf24_pa_dbm_e_str_2[] PROGMEM = "PA_HIGH";
+static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_MAX";
+static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = { 
+  rf24_pa_dbm_e_str_0,
+  rf24_pa_dbm_e_str_1,
+  rf24_pa_dbm_e_str_2,
+  rf24_pa_dbm_e_str_3,
+};
+
+void RF24::printDetails(void)
+{
+
+  printf_P(PSTR("SPI device\t = %s\r\n"),spidevice.c_str() );
+  printf_P(PSTR("SPI speed\t = %d\r\n"),spispeed);
+  printf_P(PSTR("CE GPIO\t = %d\r\n"),ce_pin);
+	
+  print_status(get_status());
+
+  print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2);
+  print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4);
+  print_address_register(PSTR("TX_ADDR"),TX_ADDR);
+
+  print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6);
+  print_byte_register(PSTR("EN_AA"),EN_AA);
+  print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR);
+  print_byte_register(PSTR("RF_CH"),RF_CH);
+  print_byte_register(PSTR("RF_SETUP"),RF_SETUP);
+  print_byte_register(PSTR("CONFIG"),CONFIG);
+  print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2);
+
+  printf_P(PSTR("Data Rate\t = %s\r\n"),pgm_read_word(&rf24_datarate_e_str_P[getDataRate()]));
+  printf_P(PSTR("Model\t\t = %s\r\n"),pgm_read_word(&rf24_model_e_str_P[isPVariant()]));
+  printf_P(PSTR("CRC Length\t = %s\r\n"),pgm_read_word(&rf24_crclength_e_str_P[getCRCLength()]));
+  printf_P(PSTR("PA Power\t = %s\r\n"),pgm_read_word(&rf24_pa_dbm_e_str_P[getPALevel()]));
+}
+
+/****************************************************************************/
+
+void RF24::begin(void)
+{
+  // Initialize pins
+  pinMode(ce_pin,OUTPUT);
+
+if ( spidevice == "/dev/spidev0.1" ) {
+	csn_pin=9;
+} else {
+	csn_pin=8;
+}
+  pinMode(csn_pin,OUTPUT);
+
+  // Initialize SPI bus
+  //spi->begin();
+spi = new SPI();
+        spi->setdevice(spidevice);
+        spi->setspeed(spispeed);
+        spi->setbits(8);
+        spi->init();
+
+
+  ce(LOW);
+  csn(HIGH);
+
+  // Must allow the radio time to settle else configuration bits will not necessarily stick.
+  // This is actually only required following power up but some settling time also appears to
+  // be required after resets too. For full coverage, we'll always assume the worst.
+  // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
+  // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
+  // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
+  delay( 5 ) ;
+	resetcfg();
+
+  // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
+  // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
+  // sizes must never be used. See documentation for a more complete explanation.
+  write_register(SETUP_RETR,(0b0100 << ARD) | (0b1111 << ARC));
+
+  // Restore our default PA level
+  setPALevel( RF24_PA_MAX ) ;
+
+  // Determine if this is a p or non-p RF24 module and then
+  // reset our data rate back to default value. This works
+  // because a non-P variant won't allow the data rate to
+  // be set to 250Kbps.
+  if( setDataRate( RF24_250KBPS ) )
+  {
+    p_variant = true ;
+  }
+  
+  // Then set the data rate to the slowest (and most reliable) speed supported by all
+  // hardware.
+  setDataRate( RF24_1MBPS ) ;
+
+  // Initialize CRC and request 2-byte (16bit) CRC
+  setCRCLength( RF24_CRC_16 ) ;
+  
+  // Disable dynamic payloads, to match dynamic_payloads_enabled setting
+  write_register(DYNPD,0);
+
+  // Reset current status
+  // Notice reset and flush is the last thing we do
+  write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
+
+  // Set up default configuration.  Callers can always change it later.
+  // This channel should be universally safe and not bleed over into adjacent
+  // spectrum.
+  setChannel(76);
+
+  // Flush buffers
+  flush_rx();
+  flush_tx();
+}
+
+/****************************************************************************/
+
+
+void RF24::resetcfg(void){
+	write_register(0x00,0x0f);
+}
+
+void RF24::startListening(void)
+{
+  write_register(CONFIG, read_register(CONFIG) | _BV(PWR_UP) | _BV(PRIM_RX));
+  write_register(STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
+
+  // Restore the pipe0 adddress, if exists
+  if (pipe0_reading_address)
+    write_register(RX_ADDR_P0, reinterpret_cast(&pipe0_reading_address), 5);
+
+  // Flush buffers
+  flush_rx();
+  flush_tx();
+
+  // Go!
+  ce(HIGH);
+
+  // wait for the radio to come up (130us actually only needed)
+  delayMicroseconds(130);
+}
+
+/****************************************************************************/
+
+void RF24::stopListening(void)
+{
+  ce(LOW);
+  flush_tx();
+  flush_rx();
+}
+
+/****************************************************************************/
+
+void RF24::powerDown(void)
+{
+  write_register(CONFIG,read_register(CONFIG) & ~_BV(PWR_UP));
+}
+
+/****************************************************************************/
+
+void RF24::powerUp(void)
+{
+  write_register(CONFIG,read_register(CONFIG) | _BV(PWR_UP));
+}
+
+/******************************************************************/
+
+bool RF24::write( const void* buf, uint8_t len )
+{
+  bool result = false;
+
+  // Begin the write
+  startWrite(buf,len);
+
+  // ------------
+  // At this point we could return from a non-blocking write, and then call
+  // the rest after an interrupt
+
+  // Instead, we are going to block here until we get TX_DS (transmission completed and ack'd)
+  // or MAX_RT (maximum retries, transmission failed).  Also, we'll timeout in case the radio
+  // is flaky and we get neither.
+
+  // IN the end, the send should be blocking.  It comes back in 60ms worst case, or much faster
+  // if I tighted up the retry logic.  (Default settings will be 1500us.
+  // Monitor the send
+  uint8_t observe_tx;
+  uint8_t status;
+  uint32_t sent_at = __millis();
+  const uint32_t timeout = 500; //ms to wait for timeout
+  do
+  {
+    status = read_register(OBSERVE_TX,&observe_tx,1);
+    IF_SERIAL_DEBUG(printf(observe_tx,HEX));
+  }
+  while( ! ( status & ( _BV(TX_DS) | _BV(MAX_RT) ) ) && ( __millis() - sent_at < timeout ) );
+
+  // The part above is what you could recreate with your own interrupt handler,
+  // and then call this when you got an interrupt
+  // ------------
+
+  // Call this when you get an interrupt
+  // The status tells us three things
+  // * The send was successful (TX_DS)
+  // * The send failed, too many retries (MAX_RT)
+  // * There is an ack packet waiting (RX_DR)
+  bool tx_ok, tx_fail;
+  whatHappened(tx_ok,tx_fail,ack_payload_available);
+  
+  //printf("%u%u%u\r\n",tx_ok,tx_fail,ack_payload_available);
+
+  result = tx_ok;
+  IF_SERIAL_DEBUG(printf(result?"...OK.":"...Failed"));
+
+  // Handle the ack packet
+  if ( ack_payload_available )
+  {
+    ack_payload_length = getDynamicPayloadSize();
+    IF_SERIAL_DEBUG(printf("[AckPacket]/"));
+    IF_SERIAL_DEBUG(printfln(ack_payload_length,DEC));
+  }
+
+  // Yay, we are done.
+
+  // Power down
+  powerDown();
+
+  // Flush buffers (Is this a relic of past experimentation, and not needed anymore??)
+  flush_tx();
+
+  return result;
+}
+/****************************************************************************/
+
+void RF24::startWrite( const void* buf, uint8_t len )
+{
+  // Transmitter power-up
+  write_register(CONFIG, ( read_register(CONFIG) | _BV(PWR_UP) ) & ~_BV(PRIM_RX) );
+  delayMicroseconds(150);
+
+  // Send the payload
+  write_payload( buf, len );
+
+  // Allons!
+  ce(HIGH);
+  delayMicroseconds(15);
+  ce(LOW);
+}
+
+/****************************************************************************/
+
+uint8_t RF24::getDynamicPayloadSize(void)
+{
+  uint8_t result = 0;
+
+  csn(LOW);
+  spi->transfer( R_RX_PL_WID );
+  result = spi->transfer(0xff);
+  csn(HIGH);
+
+  return result;
+}
+
+/****************************************************************************/
+
+bool RF24::available(void)
+{
+  return available(NULL);
+}
+
+/****************************************************************************/
+
+bool RF24::available(uint8_t* pipe_num)
+{
+  uint8_t status = get_status();
+
+  // Too noisy, enable if you really want lots o data!!
+  //IF_SERIAL_DEBUG(print_status(status));
+
+  bool result = ( status & _BV(RX_DR) );
+
+  if (result)
+  {
+    // If the caller wants the pipe number, include that
+    if ( pipe_num )
+      *pipe_num = ( status >> RX_P_NO ) & 0b111;
+
+    // Clear the status bit
+
+    // ??? Should this REALLY be cleared now?  Or wait until we
+    // actually READ the payload?
+
+    write_register(STATUS,_BV(RX_DR) );
+
+    // Handle ack payload receipt
+    if ( status & _BV(TX_DS) )
+    {
+      write_register(STATUS,_BV(TX_DS));
+    }
+  }
+
+  return result;
+}
+
+/****************************************************************************/
+
+bool RF24::read( void* buf, uint8_t len )
+{
+  // Fetch the payload
+  read_payload( buf, len );
+
+  // was this the last of the data available?
+  return read_register(FIFO_STATUS) & _BV(RX_EMPTY);
+}
+
+/****************************************************************************/
+
+void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
+{
+  // Read the status & reset the status in one easy call
+  // Or is that such a good idea?
+  uint8_t status = write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
+
+  // Report to the user what happened
+  tx_ok = status & _BV(TX_DS);
+  tx_fail = status & _BV(MAX_RT);
+  rx_ready = status & _BV(RX_DR);
+}
+
+/****************************************************************************/
+
+void RF24::openWritingPipe(uint64_t value)
+{
+  // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
+  // expects it LSB first too, so we're good.
+
+  write_register(RX_ADDR_P0, reinterpret_cast(&value), 5);
+  write_register(TX_ADDR, reinterpret_cast(&value), 5);
+
+  const uint8_t max_payload_size = 32;
+  write_register(RX_PW_P0,min(payload_size,max_payload_size));
+}
+
+/****************************************************************************/
+
+static const uint8_t child_pipe[] PROGMEM =
+{
+  RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5
+};
+static const uint8_t child_payload_size[] PROGMEM =
+{
+  RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5
+};
+static const uint8_t child_pipe_enable[] PROGMEM =
+{
+  ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5
+};
+
+void RF24::openReadingPipe(uint8_t child, uint64_t address)
+{
+  // If this is pipe 0, cache the address.  This is needed because
+  // openWritingPipe() will overwrite the pipe 0 address, so
+  // startListening() will have to restore it.
+  if (child == 0)
+    pipe0_reading_address = address;
+
+  if (child <= 6)
+  {
+    // For pipes 2-5, only write the LSB
+    if ( child < 2 )
+      write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast(&address), 5);
+    else
+      write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast(&address), 1);
+
+    write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
+
+    // Note it would be more efficient to set all of the bits for all open
+    // pipes at once.  However, I thought it would make the calling code
+    // more simple to do it this way.
+    write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
+  }
+}
+
+/****************************************************************************/
+
+void RF24::toggle_features(void)
+{
+  csn(LOW);
+  spi->transfer( ACTIVATE );
+  spi->transfer( 0x73 );
+  csn(HIGH);
+}
+
+/****************************************************************************/
+
+void RF24::enableDynamicPayloads(void)
+{
+  // Enable dynamic payload throughout the system
+  write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
+
+  // If it didn't work, the features are not enabled
+  if ( ! read_register(FEATURE) )
+  {
+    // So enable them and try again
+    toggle_features();
+    write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
+  }
+
+  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
+
+  // Enable dynamic payload on all pipes
+  //
+  // Not sure the use case of only having dynamic payload on certain
+  // pipes, so the library does not support it.
+  write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
+
+  dynamic_payloads_enabled = true;
+}
+
+/****************************************************************************/
+
+void RF24::enableAckPayload(void)
+{
+  //
+  // enable ack payload and dynamic payload features
+  //
+
+  write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
+
+  // If it didn't work, the features are not enabled
+  if ( ! read_register(FEATURE) )
+  {
+    // So enable them and try again
+    toggle_features();
+    write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
+  }
+
+  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
+
+  //
+  // Enable dynamic payload on pipes 0 & 1
+  //
+
+  write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
+}
+
+/****************************************************************************/
+
+void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
+{
+  const uint8_t* current = reinterpret_cast(buf);
+
+  csn(LOW);
+  spi->transfer( W_ACK_PAYLOAD | ( pipe & 0b111 ) );
+  const uint8_t max_payload_size = 32;
+  uint8_t data_len = min(len,max_payload_size);
+  while ( data_len-- )
+    spi->transfer(*current++);
+
+  csn(HIGH);
+}
+
+/****************************************************************************/
+
+bool RF24::isAckPayloadAvailable(void)
+{
+  bool result = ack_payload_available;
+  ack_payload_available = false;
+  return result;
+}
+
+/****************************************************************************/
+
+bool RF24::isPVariant(void)
+{
+  return p_variant ;
+}
+
+/****************************************************************************/
+
+void RF24::setAutoAck(bool enable)
+{
+  if ( enable )
+    write_register(EN_AA, 0b111111);
+  else
+    write_register(EN_AA, 0);
+}
+
+/****************************************************************************/
+
+void RF24::setAutoAck( uint8_t pipe, bool enable )
+{
+  if ( pipe <= 6 )
+  {
+    uint8_t en_aa = read_register( EN_AA ) ;
+    if( enable )
+    {
+      en_aa |= _BV(pipe) ;
+    }
+    else
+    {
+      en_aa &= ~_BV(pipe) ;
+    }
+    write_register( EN_AA, en_aa ) ;
+  }
+}
+
+/****************************************************************************/
+
+bool RF24::testCarrier(void)
+{
+  return ( read_register(CD) & 1 );
+}
+
+/****************************************************************************/
+
+bool RF24::testRPD(void)
+{
+  return ( read_register(RPD) & 1 ) ;
+}
+
+/****************************************************************************/
+
+void RF24::setPALevel(rf24_pa_dbm_e level)
+{
+  uint8_t setup = read_register(RF_SETUP) ;
+  setup &= ~(_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
+
+  // switch uses RAM (evil!)
+  if ( level == RF24_PA_MAX )
+  {
+    setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
+  }
+  else if ( level == RF24_PA_HIGH )
+  {
+    setup |= _BV(RF_PWR_HIGH) ;
+  }
+  else if ( level == RF24_PA_LOW )
+  {
+    setup |= _BV(RF_PWR_LOW);
+  }
+  else if ( level == RF24_PA_MIN )
+  {
+    // nothing
+  }
+  else if ( level == RF24_PA_ERROR )
+  {
+    // On error, go to maximum PA
+    setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
+  }
+
+  write_register( RF_SETUP, setup ) ;
+}
+
+/****************************************************************************/
+
+rf24_pa_dbm_e RF24::getPALevel(void)
+{
+  rf24_pa_dbm_e result = RF24_PA_ERROR ;
+  uint8_t power = read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ;
+
+  // switch uses RAM (evil!)
+  if ( power == (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) )
+  {
+    result = RF24_PA_MAX ;
+  }
+  else if ( power == _BV(RF_PWR_HIGH) )
+  {
+    result = RF24_PA_HIGH ;
+  }
+  else if ( power == _BV(RF_PWR_LOW) )
+  {
+    result = RF24_PA_LOW ;
+  }
+  else
+  {
+    result = RF24_PA_MIN ;
+  }
+
+  return result ;
+}
+
+/****************************************************************************/
+
+bool RF24::setDataRate(rf24_datarate_e speed)
+{
+  bool result = false;
+  uint8_t setup = read_register(RF_SETUP) ;
+
+  // HIGH and LOW '00' is 1Mbs - our default
+  wide_band = false ;
+  setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ;
+  if( speed == RF24_250KBPS )
+  {
+    // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
+    // Making it '10'.
+    wide_band = false ;
+    setup |= _BV( RF_DR_LOW ) ;
+  }
+  else
+  {
+    // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
+    // Making it '01'
+    if ( speed == RF24_2MBPS )
+    {
+      wide_band = true ;
+      setup |= _BV(RF_DR_HIGH);
+    }
+    else
+    {
+      // 1Mbs
+      wide_band = false ;
+    }
+  }
+  write_register(RF_SETUP,setup);
+
+  // Verify our result
+  if ( read_register(RF_SETUP) == setup )
+  {
+    result = true;
+  }
+  else
+  {
+    wide_band = false;
+  }
+
+  return result;
+}
+
+/****************************************************************************/
+
+rf24_datarate_e RF24::getDataRate( void )
+{
+  rf24_datarate_e result ;
+  uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH));
+  
+  // switch uses RAM (evil!)
+  // Order matters in our case below
+  if ( dr == _BV(RF_DR_LOW) )
+  {
+    // '10' = 250KBPS
+    result = RF24_250KBPS ;
+  }
+  else if ( dr == _BV(RF_DR_HIGH) )
+  {
+    // '01' = 2MBPS
+    result = RF24_2MBPS ;
+  }
+  else
+  {
+    // '00' = 1MBPS
+    result = RF24_1MBPS ;
+  }
+  return result ;
+}
+
+/****************************************************************************/
+
+void RF24::setCRCLength(rf24_crclength_e length)
+{
+  uint8_t config = read_register(CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ;
+  
+  // switch uses RAM (evil!)
+  if ( length == RF24_CRC_DISABLED )
+  {
+    // Do nothing, we turned it off above. 
+  }
+  else if ( length == RF24_CRC_8 )
+  {
+    config |= _BV(EN_CRC);
+  }
+  else
+  {
+    config |= _BV(EN_CRC);
+    config |= _BV( CRCO );
+  }
+  write_register( CONFIG, config ) ;
+}
+
+/****************************************************************************/
+
+rf24_crclength_e RF24::getCRCLength(void)
+{
+  rf24_crclength_e result = RF24_CRC_DISABLED;
+  uint8_t config = read_register(CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ;
+
+  if ( config & _BV(EN_CRC ) )
+  {
+    if ( config & _BV(CRCO) )
+      result = RF24_CRC_16;
+    else
+      result = RF24_CRC_8;
+  }
+
+  return result;
+}
+
+/****************************************************************************/
+
+void RF24::disableCRC( void )
+{
+  uint8_t disable = read_register(CONFIG) & ~_BV(EN_CRC) ;
+  write_register( CONFIG, disable ) ;
+}
+
+/****************************************************************************/
+void RF24::setRetries(uint8_t delay, uint8_t count)
+{
+ write_register(SETUP_RETR,(delay&0xf)<
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * @file RF24.h
+ *
+ * Class declaration for RF24 and helper enums
+ */
+
+#ifndef __RF24_H__
+#define __RF24_H__
+
+#include "RF24_config.h"
+//#include "lib/RF24/compatibility.h"
+#include "compatibility.h"
+
+/**
+ * Power Amplifier level.
+ *
+ * For use with setPALevel()
+ */
+typedef enum { RF24_PA_MIN = 0,RF24_PA_LOW, RF24_PA_HIGH, RF24_PA_MAX, RF24_PA_ERROR } rf24_pa_dbm_e ;
+
+/**
+ * Data rate.  How fast data moves through the air.
+ *
+ * For use with setDataRate()
+ */
+typedef enum { RF24_1MBPS = 0, RF24_2MBPS, RF24_250KBPS } rf24_datarate_e;
+
+/**
+ * CRC Length.  How big (if any) of a CRC is included.
+ *
+ * For use with setCRCLength()
+ */
+typedef enum { RF24_CRC_DISABLED = 0, RF24_CRC_8, RF24_CRC_16 } rf24_crclength_e;
+
+/**
+ * Driver for nRF24L01(+) 2.4GHz Wireless Transceiver
+ */
+
+class RF24
+{
+private:
+  uint8_t ce_pin; /**< "Chip Enable" pin, activates the RX or TX role, unused on rpi */
+  string spidevice;
+  uint32_t spispeed;
+  uint8_t csn_pin; /**< SPI Chip select */
+  bool wide_band; /* 2Mbs data rate in use? */
+  bool p_variant; /* False for RF24L01 and true for RF24L01P */
+  uint8_t payload_size; /**< Fixed size of payloads */
+  bool ack_payload_available; /**< Whether there is an ack payload waiting */
+  bool dynamic_payloads_enabled; /**< Whether dynamic payloads are enabled. */ 
+  uint8_t ack_payload_length; /**< Dynamic size of pending ack payload. */
+  uint64_t pipe0_reading_address; /**< Last address set on pipe 0 for reading. */
+
+  SPI* spi;
+  
+protected:
+  /**
+   * @name Low-level internal interface.
+   *
+   *  Protected methods that address the chip directly.  Regular users cannot
+   *  ever call these.  They are documented for completeness and for developers who
+   *  may want to extend this class.
+   */
+  /**@{*/
+
+  /**
+   * Set chip select pin
+   *
+   * Running SPI bus at PI_CLOCK_DIV2 so we don't waste time transferring data
+   * and best of all, we make use of the radio's FIFO buffers. A lower speed
+   * means we're less likely to effectively leverage our FIFOs and pay a higher
+   * AVR runtime cost as toll.
+   *
+   * @param mode HIGH to take this unit off the SPI bus, LOW to put it on
+   */
+  void csn(int mode);
+
+  /**
+   * Set chip enable
+   *
+   * @param level HIGH to actively begin transmission or LOW to put in standby.  Please see data sheet
+   * for a much more detailed description of this pin.
+   */
+  void ce(int level);
+
+  /**
+   * Read a chunk of data in from a register
+   *
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param buf Where to put the data
+   * @param len How many bytes of data to transfer
+   * @return Current value of status register
+   */
+  uint8_t read_register(uint8_t reg, uint8_t* buf, uint8_t len);
+
+  /**
+   * Read single byte from a register
+   *
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @return Current value of register @p reg
+   */
+  uint8_t read_register(uint8_t reg);
+
+  /**
+   * Write a chunk of data to a register
+   *
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param buf Where to get the data
+   * @param len How many bytes of data to transfer
+   * @return Current value of status register
+   */
+  uint8_t write_register(uint8_t reg, const uint8_t* buf, uint8_t len);
+
+  /**
+   * Write a single byte to a register
+   *
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param value The new value to write
+   * @return Current value of status register
+   */
+  uint8_t write_register(uint8_t reg, uint8_t value);
+
+  /**
+   * Write the transmit payload
+   *
+   * The size of data written is the fixed payload size, see getPayloadSize()
+   *
+   * @param buf Where to get the data
+   * @param len Number of bytes to be sent
+   * @return Current value of status register
+   */
+  uint8_t write_payload(const void* buf, uint8_t len);
+
+  /**
+   * Read the receive payload
+   *
+   * The size of data read is the fixed payload size, see getPayloadSize()
+   *
+   * @param buf Where to put the data
+   * @param len Maximum number of bytes to read
+   * @return Current value of status register
+   */
+  uint8_t read_payload(void* buf, uint8_t len);
+
+  /**
+   * Empty the receive buffer
+   *
+   * @return Current value of status register
+   */
+  uint8_t flush_rx(void);
+
+  /**
+   * Empty the transmit buffer
+   *
+   * @return Current value of status register
+   */
+  uint8_t flush_tx(void);
+
+  /**
+   * Retrieve the current status of the chip
+   *
+   * @return Current value of status register
+   */
+  uint8_t get_status(void);
+
+  /**
+   * Decode and print the given status to stdout
+   *
+   * @param status Status value to print
+   *
+   * @warning Does nothing if stdout is not defined.  See fdevopen in stdio.h
+   */
+  void print_status(uint8_t status);
+
+  /**
+   * Decode and print the given 'observe_tx' value to stdout
+   *
+   * @param value The observe_tx value to print
+   *
+   * @warning Does nothing if stdout is not defined.  See fdevopen in stdio.h
+   */
+  void print_observe_tx(uint8_t value);
+
+  /**
+   * Print the name and value of an 8-bit register to stdout
+   *
+   * Optionally it can print some quantity of successive
+   * registers on the same line.  This is useful for printing a group
+   * of related registers on one line.
+   *
+   * @param name Name of the register
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param qty How many successive registers to print
+   */
+  void print_byte_register(const char* name, uint8_t reg, uint8_t qty = 1);
+
+  /**
+   * Print the name and value of a 40-bit address register to stdout
+   *
+   * Optionally it can print some quantity of successive
+   * registers on the same line.  This is useful for printing a group
+   * of related registers on one line.
+   *
+   * @param name Name of the register
+   * @param reg Which register. Use constants from nRF24L01.h
+   * @param qty How many successive registers to print
+   */
+  void print_address_register(const char* name, uint8_t reg, uint8_t qty = 1);
+
+  /**
+   * Turn on or off the special features of the chip
+   *
+   * The chip has certain 'features' which are only available when the 'features'
+   * are enabled.  See the datasheet for details.
+   */
+  void toggle_features(void);
+  /**@}*/
+
+public:
+  /**
+   * @name Primary public interface
+   *
+   *  These are the main methods you need to operate the chip
+   */
+  /**@{*/
+
+  /**
+   * Constructor
+   *
+   * Creates a new instance of this driver.  Before using, you create an instance
+   * and send in the unique pins that this chip is connected to.
+   *
+   * @param _cepin The pin attached to Chip Enable on the RF module
+   * @param _cspin The pin attached to Chip SPI chipSelect
+   */
+  RF24(uint8_t _cepin, uint8_t _cspin);
+  RF24(string _spidevice, uint32_t _spispeed, uint8_t _cepin);
+
+  /**
+   * Begin operation of the chip
+   *
+   * Call this in setup(), before calling any other methods.
+   */
+  void begin(void);
+
+ /**
+   * Reset confguration of the chip
+   *
+   * Call this to reset all registers
+   */
+  void resetcfg(void);
+
+  /**
+   * Start listening on the pipes opened for reading.
+   *
+   * Be sure to call openReadingPipe() first.  Do not call write() while
+   * in this mode, without first calling stopListening().  Call
+   * isAvailable() to check for incoming traffic, and read() to get it.
+   */
+  void startListening(void);
+
+  /**
+   * Stop listening for incoming messages
+   *
+   * Do this before calling write().
+   */
+  void stopListening(void);
+
+  /**
+   * Write to the open writing pipe
+   *
+   * Be sure to call openWritingPipe() first to set the destination
+   * of where to write to.
+   *
+   * This blocks until the message is successfully acknowledged by
+   * the receiver or the timeout/retransmit maxima are reached.  In
+   * the current configuration, the max delay here is 60ms.
+   *
+   * The maximum size of data written is the fixed payload size, see
+   * getPayloadSize().  However, you can write less, and the remainder
+   * will just be filled with zeroes.
+   *
+   * @param buf Pointer to the data to be sent
+   * @param len Number of bytes to be sent
+   * @return True if the payload was delivered successfully false if not
+   */
+  bool write( const void* buf, uint8_t len );
+
+  /**
+   * Test whether there are bytes available to be read
+   *
+   * @return True if there is a payload available, false if none is
+   */
+  bool available(void);
+
+  /**
+   * Read the payload
+   *
+   * Return the last payload received
+   *
+   * The size of data read is the fixed payload size, see getPayloadSize()
+   *
+   * @note I specifically chose 'void*' as a data type to make it easier
+   * for beginners to use.  No casting needed.
+   *
+   * @param buf Pointer to a buffer where the data should be written
+   * @param len Maximum number of bytes to read into the buffer
+   * @return True if the payload was delivered successfully false if not
+   */
+  bool read( void* buf, uint8_t len );
+
+  /**
+   * Open a pipe for writing
+   *
+   * Only one pipe can be open at once, but you can change the pipe
+   * you'll listen to.  Do not call this while actively listening.
+   * Remember to stopListening() first.
+   *
+   * Addresses are 40-bit hex values, e.g.:
+   *
+   * @code
+   *   openWritingPipe(0xF0F0F0F0F0);
+   * @endcode
+   *
+   * @param address The 40-bit address of the pipe to open.  This can be
+   * any value whatsoever, as long as you are the only one writing to it
+   * and only one other radio is listening to it.  Coordinate these pipe
+   * addresses amongst nodes on the network.
+   */
+  void openWritingPipe(uint64_t address);
+
+  /**
+   * Open a pipe for reading
+   *
+   * Up to 6 pipes can be open for reading at once.  Open all the
+   * reading pipes, and then call startListening().
+   *
+   * @see openWritingPipe
+   *
+   * @warning Pipes 1-5 should share the first 32 bits.
+   * Only the least significant byte should be unique, e.g.
+   * @code
+   *   openReadingPipe(1,0xF0F0F0F0AA);
+   *   openReadingPipe(2,0xF0F0F0F066);
+   * @endcode
+   *
+   * @warning Pipe 0 is also used by the writing pipe.  So if you open
+   * pipe 0 for reading, and then startListening(), it will overwrite the
+   * writing pipe.  Ergo, do an openWritingPipe() again before write().
+   *
+   * @todo Enforce the restriction that pipes 1-5 must share the top 32 bits
+   *
+   * @param number Which pipe# to open, 0-5.
+   * @param address The 40-bit address of the pipe to open.
+   */
+  void openReadingPipe(uint8_t number, uint64_t address);
+
+  /**@}*/
+  /**
+   * @name Optional Configurators 
+   *
+   *  Methods you can use to get or set the configuration of the chip.
+   *  None are required.  Calling begin() sets up a reasonable set of
+   *  defaults.
+   */
+  /**@{*/
+  /**
+   * Set the number and delay of retries upon failed submit
+   *
+   * @param delay How long to wait between each retry, in multiples of 250us,
+   * max is 15.  0 means 250us, 15 means 4000us.
+   * @param count How many retries before giving up, max 15
+   */
+  void setRetries(uint8_t delay, uint8_t count);
+
+  /**
+   * Set RF communication channel
+   *
+   * @param channel Which RF channel to communicate on, 0-127
+   */
+  void setChannel(uint8_t channel);
+
+  /**
+   * Set Static Payload Size
+   *
+   * This implementation uses a pre-stablished fixed payload size for all
+   * transmissions.  If this method is never called, the driver will always
+   * transmit the maximum payload size (32 bytes), no matter how much
+   * was sent to write().
+   *
+   * @todo Implement variable-sized payloads feature
+   *
+   * @param size The number of bytes in the payload
+   */
+  void setPayloadSize(uint8_t size);
+
+  /**
+   * Get Static Payload Size
+   *
+   * @see setPayloadSize()
+   *
+   * @return The number of bytes in the payload
+   */
+  uint8_t getPayloadSize(void);
+
+  /**
+   * Get Dynamic Payload Size
+   *
+   * For dynamic payloads, this pulls the size of the payload off
+   * the chip
+   *
+   * @return Payload length of last-received dynamic payload
+   */
+  uint8_t getDynamicPayloadSize(void);
+  
+  /**
+   * Enable custom payloads on the acknowledge packets
+   *
+   * Ack payloads are a handy way to return data back to senders without
+   * manually changing the radio modes on both units.
+   *
+   * @see examples/pingpair_pl/pingpair_pl.pde
+   */
+  void enableAckPayload(void);
+
+  /**
+   * Enable dynamically-sized payloads
+   *
+   * This way you don't always have to send large packets just to send them
+   * once in a while.  This enables dynamic payloads on ALL pipes.
+   *
+   * @see examples/pingpair_pl/pingpair_dyn.pde
+   */
+  void enableDynamicPayloads(void);
+
+  /**
+   * Determine whether the hardware is an nRF24L01+ or not.
+   *
+   * @return true if the hardware is nRF24L01+ (or compatible) and false
+   * if its not.
+   */
+  bool isPVariant(void) ;
+
+  /**
+   * Enable or disable auto-acknowlede packets
+   *
+   * This is enabled by default, so it's only needed if you want to turn
+   * it off for some reason.
+   *
+   * @param enable Whether to enable (true) or disable (false) auto-acks
+   */
+  void setAutoAck(bool enable);
+
+  /**
+   * Enable or disable auto-acknowlede packets on a per pipeline basis.
+   *
+   * AA is enabled by default, so it's only needed if you want to turn
+   * it off/on for some reason on a per pipeline basis.
+   *
+   * @param pipe Which pipeline to modify
+   * @param enable Whether to enable (true) or disable (false) auto-acks
+   */
+  void setAutoAck( uint8_t pipe, bool enable ) ;
+
+  /**
+   * Set Power Amplifier (PA) level to one of four levels.
+   * Relative mnemonics have been used to allow for future PA level
+   * changes. According to 6.5 of the nRF24L01+ specification sheet,
+   * they translate to: RF24_PA_MIN=-18dBm, RF24_PA_LOW=-12dBm,
+   * RF24_PA_MED=-6dBM, and RF24_PA_HIGH=0dBm.
+   *
+   * @param level Desired PA level.
+   */
+  void setPALevel( rf24_pa_dbm_e level ) ;
+
+  /**
+   * Fetches the current PA level.
+   *
+   * @return Returns a value from the rf24_pa_dbm_e enum describing
+   * the current PA setting. Please remember, all values represented
+   * by the enum mnemonics are negative dBm. See setPALevel for
+   * return value descriptions.
+   */
+  rf24_pa_dbm_e getPALevel( void ) ;
+
+  /**
+   * Set the transmission data rate
+   *
+   * @warning setting RF24_250KBPS will fail for non-plus units
+   *
+   * @param speed RF24_250KBPS for 250kbs, RF24_1MBPS for 1Mbps, or RF24_2MBPS for 2Mbps
+   * @return true if the change was successful
+   */
+  bool setDataRate(rf24_datarate_e speed);
+  
+  /**
+   * Fetches the transmission data rate
+   *
+   * @return Returns the hardware's currently configured datarate. The value
+   * is one of 250kbs, RF24_1MBPS for 1Mbps, or RF24_2MBPS, as defined in the
+   * rf24_datarate_e enum.
+   */
+  rf24_datarate_e getDataRate( void ) ;
+
+  /**
+   * Set the CRC length
+   *
+   * @param length RF24_CRC_8 for 8-bit or RF24_CRC_16 for 16-bit
+   */
+  void setCRCLength(rf24_crclength_e length);
+
+  /**
+   * Get the CRC length
+   *
+   * @return RF24_DISABLED if disabled or RF24_CRC_8 for 8-bit or RF24_CRC_16 for 16-bit
+   */
+  rf24_crclength_e getCRCLength(void);
+
+  /**
+   * Disable CRC validation
+   *
+   */
+  void disableCRC( void ) ;
+
+  /**@}*/
+  /**
+   * @name Advanced Operation 
+   *
+   *  Methods you can use to drive the chip in more advanced ways 
+   */
+  /**@{*/
+
+  /**
+   * Print a giant block of debugging information to stdout
+   *
+   * @warning Does nothing if stdout is not defined.  See fdevopen in stdio.h
+   */
+  void printDetails(void);
+
+  /**
+   * Enter low-power mode
+   *
+   * To return to normal power mode, either write() some data or
+   * startListening, or powerUp().
+   */
+  void powerDown(void);
+
+  /**
+   * Leave low-power mode - making radio more responsive
+   *
+   * To return to low power mode, call powerDown().
+   */
+  void powerUp(void) ;
+
+  /**
+   * Test whether there are bytes available to be read
+   *
+   * Use this version to discover on which pipe the message
+   * arrived.
+   *
+   * @param[out] pipe_num Which pipe has the payload available
+   * @return True if there is a payload available, false if none is
+   */
+  bool available(uint8_t* pipe_num);
+
+  /**
+   * Non-blocking write to the open writing pipe
+   *
+   * Just like write(), but it returns immediately. To find out what happened
+   * to the send, catch the IRQ and then call whatHappened().
+   *
+   * @see write()
+   * @see whatHappened()
+   *
+   * @param buf Pointer to the data to be sent
+   * @param len Number of bytes to be sent
+   * @return True if the payload was delivered successfully false if not
+   */
+  void startWrite( const void* buf, uint8_t len );
+
+  /**
+   * Write an ack payload for the specified pipe
+   *
+   * The next time a message is received on @p pipe, the data in @p buf will
+   * be sent back in the acknowledgement.
+   *
+   * @warning According to the data sheet, only three of these can be pending
+   * at any time.  I have not tested this.
+   *
+   * @param pipe Which pipe# (typically 1-5) will get this response.
+   * @param buf Pointer to data that is sent
+   * @param len Length of the data to send, up to 32 bytes max.  Not affected
+   * by the static payload set by setPayloadSize().
+   */
+  void writeAckPayload(uint8_t pipe, const void* buf, uint8_t len);
+
+  /**
+   * Determine if an ack payload was received in the most recent call to
+   * write().
+   *
+   * Call read() to retrieve the ack payload.
+   *
+   * @warning Calling this function clears the internal flag which indicates
+   * a payload is available.  If it returns true, you must read the packet
+   * out as the very next interaction with the radio, or the results are
+   * undefined.
+   *
+   * @return True if an ack payload is available.
+   */
+  bool isAckPayloadAvailable(void);
+
+  /**
+   * Call this when you get an interrupt to find out why
+   *
+   * Tells you what caused the interrupt, and clears the state of
+   * interrupts.
+   *
+   * @param[out] tx_ok The send was successful (TX_DS)
+   * @param[out] tx_fail The send failed, too many retries (MAX_RT)
+   * @param[out] rx_ready There is a message waiting to be read (RX_DS)
+   */
+  void whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready);
+
+  /**
+   * Test whether there was a carrier on the line for the
+   * previous listening period.
+   *
+   * Useful to check for interference on the current channel.
+   *
+   * @return true if was carrier, false if not
+   */
+  bool testCarrier(void);
+
+  /**
+   * Test whether a signal (carrier or otherwise) greater than
+   * or equal to -64dBm is present on the channel. Valid only
+   * on nRF24L01P (+) hardware. On nRF24L01, use testCarrier().
+   *
+   * Useful to check for interference on the current channel and
+   * channel hopping strategies.
+   *
+   * @return true if signal => -64dBm, false if not
+   */
+  bool testRPD(void) ;
+
+  /**@}*/
+};
+
+/**
+ * @example GettingStarted.pde
+ *
+ * This is an example which corresponds to my "Getting Started" blog post:
+ * Getting Started with nRF24L01+ on Arduino. 
+ *
+ * It is an example of how to use the RF24 class.  Write this sketch to two 
+ * different nodes.  Put one of the nodes into 'transmit' mode by connecting 
+ * with the serial monitor and sending a 'T'.  The ping node sends the current 
+ * time to the pong node, which responds by sending the value back.  The ping 
+ * node can then see how long the whole cycle took.
+ */
+
+/**
+ * @example nordic_fob.pde
+ *
+ * This is an example of how to use the RF24 class to receive signals from the
+ * Sparkfun Nordic FOB.  See http://www.sparkfun.com/products/8602 .
+ * Thanks to Kirk Mower for providing test hardware.
+ */
+
+/**
+ * @example led_remote.pde
+ *
+ * This is an example of how to use the RF24 class to control a remote
+ * bank of LED's using buttons on a remote control.
+ *
+ * Every time the buttons change on the remote, the entire state of
+ * buttons is send to the led board, which displays the state.
+ */
+
+/**
+ * @example pingpair.pde
+ *
+ * This is an example of how to use the RF24 class.  Write this sketch to two
+ * different nodes, connect the role_pin to ground on one.  The ping node sends
+ * the current time to the pong node, which responds by sending the value back.
+ * The ping node can then see how long the whole cycle took.
+ */
+
+/**
+ * @example pingpair_maple.pde 
+ *
+ * This is an example of how to use the RF24 class on the Maple.  For a more
+ * detailed explanation, see my blog post:
+ * nRF24L01+ Running on Maple
+ *
+ * It will communicate well to an Arduino-based unit as well, so it's not for only Maple-to-Maple communication.
+ * 
+ * Write this sketch to two different nodes,
+ * connect the role_pin to ground on one.  The ping node sends the current time to the pong node,
+ * which responds by sending the value back.  The ping node can then see how long the whole cycle
+ * took.
+ */
+
+/**
+ * @example starping.pde
+ *
+ * This sketch is a more complex example of using the RF24 library for Arduino.
+ * Deploy this on up to six nodes.  Set one as the 'pong receiver' by tying the
+ * role_pin low, and the others will be 'ping transmit' units.  The ping units
+ * unit will send out the value of millis() once a second.  The pong unit will
+ * respond back with a copy of the value.  Each ping unit can get that response
+ * back, and determine how long the whole cycle took.
+ *
+ * This example requires a bit more complexity to determine which unit is which.
+ * The pong receiver is identified by having its role_pin tied to ground.
+ * The ping senders are further differentiated by a byte in eeprom.
+ */
+
+/**
+ * @example pingpair_pl.pde
+ *
+ * This is an example of how to do two-way communication without changing
+ * transmit/receive modes.  Here, a payload is set to the transmitter within
+ * the Ack packet of each transmission.  Note that the payload is set BEFORE
+ * the sender's message arrives.
+ */
+
+/**
+ * @example pingpair_irq.pde
+ *
+ * This is an example of how to user interrupts to interact with the radio.
+ * It builds on the pingpair_pl example, and uses ack payloads.
+ */
+
+/**
+ * @example pingpair_sleepy.pde
+ *
+ * This is an example of how to use the RF24 class to create a battery-
+ * efficient system.  It is just like the pingpair.pde example, but the
+ * ping node powers down the radio and sleeps the MCU after every
+ * ping/pong cycle.
+ */
+
+/**
+ * @example scanner.pde
+ *
+ * Example to detect interference on the various channels available.
+ * This is a good diagnostic tool to check whether you're picking a
+ * good channel for your application.
+ *
+ * Inspired by cpixip.
+ * See http://arduino.cc/forum/index.php/topic,54795.0.html
+ */
+
+/**
+ * @mainpage Driver for nRF24L01(+) 2.4GHz Wireless Transceiver
+ *
+ * @section Goals Design Goals
+ * 
+ * This library is designed to be...
+ * @li Maximally compliant with the intended operation of the chip
+ * @li Easy for beginners to use
+ * @li Consumed with a public interface that's similiar to other Arduino standard libraries
+ *
+ * @section News News
+ * 
+ * NOW COMPATIBLE WITH ARDUINO 1.0 - The 'master' branch and all examples work with both Arduino 1.0 and earlier versions.  
+ * Please open an issue if you find any problems using it with any version of Arduino.
+ *
+ * NOW COMPATIBLE WITH MAPLE - RF24 has been tested with the 
+ * Maple Native, 
+ * and should work with any Maple board.  See the pingpair_maple example.
+ * Note that only the pingpair_maple example has been tested on Maple, although
+ * the others can certainly be adapted.
+ *
+ * @section Useful Useful References
+ * 
+ * Please refer to:
+ *
+ * @li Documentation Main Page
+ * @li RF24 Class Documentation
+ * @li Source Code
+ * @li Downloads Page
+ * @li Chip Datasheet
+ *
+ * This chip uses the SPI bus, plus two chip control pins.  Remember that pin 10 must still remain an output, or
+ * the SPI hardware will go into 'slave' mode.
+ *
+ * @section More More Information
+ *
+ * @subpage FAQ
+ *
+ * @section Projects Projects
+ *
+ * Stuff I have built with RF24
+ *
+ * RF24 Getting Started - Finished Product
+ *
+ * Getting Started with nRF24L01+ on Arduino 
+ *
+ * Nordic FOB and nRF24L01+
+ *
+ * Using the Sparkfun Nordic FOB 
+ *
+ * RF Duinode V3 (2V4)
+ *
+ * Low-Power Wireless Sensor Node
+ *
+ * nRF24L01+ connected to Leaf Labs Maple Native
+ *
+ * nRF24L01+ Running on Maple
+ */
+
+#endif // __RF24_H__
+// vim:ai:cin:sts=2 sw=2 ft=cpp
+
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/RF24_config.h b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/RF24_config.h
new file mode 100644
index 0000000..036b70c
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/RF24_config.h
@@ -0,0 +1,103 @@
+
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef __RF24_CONFIG_H__
+#define __RF24_CONFIG_H__
+
+
+#ifdef ARDUINO
+//#warning "Arduino enabled"
+#if ARDUINO < 100
+//#include 
+#else
+//#include 
+#endif
+#else 
+//#warning "Arduino disabled"
+#include "spi.h"
+#include "gpio.h"
+#include "compatibility.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define pgm_read_word(p) (*(p))
+#define pgm_read_byte(p) (*(p))
+#endif
+
+#include 
+
+// Stuff that is normally provided by Arduino
+//#ifdef ARDUINO
+//#include 
+//#else
+//#include 
+//#//include 
+//#include 
+//extern HardwareSPI SPI;
+//#define _BV(x) (1<<(x))
+
+//#else 
+//#endif
+
+//#include "../spi/spi.h"
+//#include "../gpio/gpio.h"
+
+#define _BV(x) (1<<(x))
+
+// #endif
+
+#undef SERIAL_DEBUG
+#ifdef SERIAL_DEBUG
+#define IF_SERIAL_DEBUG(x) ({x;})
+#else
+#define IF_SERIAL_DEBUG(x)
+#endif
+
+// Avoid spurious warnings
+#if 1
+#if ! defined( NATIVE ) && defined( ARDUINO )
+#undef PROGMEM
+#define PROGMEM __attribute__(( section(".progmem.data") ))
+#undef PSTR
+#define PSTR(s) (__extension__({static const char __c[] PROGMEM = (s); &__c[0];}))
+#endif
+#endif
+
+// Progmem is Arduino-specific
+//#ifdef ARDUINO
+//#include 
+//#define PRIPSTR "%S"
+//#else
+//typedef char const char;
+typedef uint16_t prog_uint16_t;
+#define PSTR(x) (x)
+#define printf_P printf
+#define strlen_P strlen
+#define PROGMEM
+#define pgm_read_word(p) (*(p)) 
+#define PRIPSTR "%s"
+
+
+// Function, constant map as a result of migrating from Arduino
+#define LOW GPIO::OUTPUT_LOW
+#define HIGH GPIO::OUTPUT_HIGH
+#define INPUT GPIO::DIRECTION_IN
+#define OUTPUT GPIO::DIRECTION_OUT
+#define digitalWrite(pin, value) GPIO::write(pin, value)
+#define pinMode(pin, direction) GPIO::open(pin, direction)
+#define delay(milisec) __msleep(milisec)
+#define delayMicroseconds(usec) __usleep(usec)
+
+//#endif
+
+#endif // __RF24_CONFIG_H__
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/compatibility.c b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/compatibility.c
new file mode 100644
index 0000000..5197fd8
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/compatibility.c
@@ -0,0 +1,40 @@
+
+#include "compatibility.h"
+/**********************************************************************/
+/**
+ * This function is added in order to simulate arduino delay() function
+ * @param milisec
+ */
+void __msleep(int milisec)
+{
+	struct timespec req = {0};
+	req.tv_sec = 0;
+	req.tv_nsec = milisec * 1000000L;
+	nanosleep(&req, (struct timespec *)NULL);	
+}
+
+void __usleep(int milisec)
+{
+	struct timespec req = {0};
+	req.tv_sec = 0;
+	req.tv_nsec = milisec * 1000L;
+	nanosleep(&req, (struct timespec *)NULL);	
+}
+
+/**
+ * This function is added in order to simulate arduino millis() function
+ */
+void __start_timer()
+{
+	gettimeofday(&start, NULL);
+}
+
+long __millis()
+{
+	gettimeofday(&end, NULL);
+    seconds  = end.tv_sec  - start.tv_sec;
+    useconds = end.tv_usec - start.tv_usec;
+
+    mtime = ((seconds) * 1000 + useconds/1000.0) + 0.5;	
+	return mtime;
+}
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/compatibility.h b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/compatibility.h
new file mode 100644
index 0000000..b6d1683
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/compatibility.h
@@ -0,0 +1,36 @@
+/* 
+ * File:   compatiblity.h
+ * Author: purinda
+ *
+ * Created on 24 June 2012, 3:08 PM
+ */
+
+#ifndef COMPATIBLITY_H
+#define	COMPATIBLITY_H
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+	
+#include 
+#include 
+#include 
+
+// added attribute unused to avoid compiler warnings
+static struct timeval start __attribute__ ((unused)) ,end __attribute__ ((unused));
+
+static long __attribute__ ((unused)) mtime;
+static long __attribute__ ((unused)) seconds;
+static long __attribute__ ((unused)) useconds;
+
+void __msleep(int milisec);
+void __usleep(int milisec);
+void __start_timer();
+long __millis();
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif	/* COMPATIBLITY_H */
+
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/Makefile b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/Makefile
new file mode 100644
index 0000000..6ccc135
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/Makefile
@@ -0,0 +1,41 @@
+#############################################################################
+#
+# Makefile for librf24 examples on Raspberry Pi
+#
+# License: GPL (General Public License)
+# Author:  gnulnulf 
+# Date:    2013/02/07 (version 1.0)
+#
+# Description:
+# ------------
+# use make all and make install to install the examples
+# You can change the install directory by editing the prefix line
+#
+prefix := /opt/librf24-examples
+
+# The recommended compiler flags for the Raspberry Pi
+CCFLAGS=-Wall -Ofast -mfpu=vfp -mfloat-abi=hard -march=armv6zk -mtune=arm1176jzf-s
+#CCFLAGS=
+
+# define all programs
+#PROGRAMS = scanner pingtest pongtest
+PROGRAMS = rpi-hub scanner pingtest pongtest
+SOURCES = ${PROGRAMS:=.cpp}
+
+all: ${PROGRAMS}
+
+${PROGRAMS}: ${SOURCES}
+#	g++ ${CCFLAGS} -Wall -L../librf24/  -lrf24 $@.cpp -o $@
+	g++ ${CCFLAGS} -L../librf24/  -lrf24 $@.cpp -o $@
+
+clean:
+	rm -rf $(PROGRAMS)
+
+install: all
+	test -d $(prefix) || mkdir $(prefix)
+	test -d $(prefix)/bin || mkdir $(prefix)/bin
+	for prog in $(PROGRAMS); do \
+	  install -m 0755 $$prog $(prefix)/bin; \
+	done
+
+.PHONY: install
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/pingtest.cpp b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/pingtest.cpp
new file mode 100644
index 0000000..22cd473
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/pingtest.cpp
@@ -0,0 +1,239 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example RF Radio Ping Pair
+ *
+ * This is an example of how to use the RF24 class.  Write this sketch to two different nodes,
+ * connect the role_pin to ground on one.  The ping node sends the current time to the pong node,
+ * which responds by sending the value back.  The ping node can then see how long the whole cycle
+ * took.
+ */
+
+#include 
+#include 
+
+#include "../RF24.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 9 & 10
+
+//RF24 radio(9,10);
+RF24 radio("/dev/spidev0.0",8000000 , 25);  //spi device, speed and CSN,only CSN is NEEDED in RPI
+
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'ping' transmitter
+const int role_pin = 7;
+
+//
+// Topology
+//
+
+// Radio pipe addresses for the 2 nodes to communicate.
+const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL };
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes
+// in this system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_ping_out = 1, role_pong_back } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"};
+
+// The role of the current running sketch
+role_e role;
+
+void setup(void)
+{
+  //
+  // Role
+  //
+
+  // set up the role pin
+ // pinMode(role_pin, INPUT);
+  //digitalWrite(role_pin,HIGH);
+ // delay(20); // Just to get a solid reading on the role pin
+
+  // read the address pin, establish our role
+  //if ( ! digitalRead(role_pin) )
+    role = role_ping_out;
+  //else
+  //  role = role_pong_back;
+
+  //
+  // Print preamble:
+  //
+
+  //Serial.begin(115200);
+  //printf_begin();
+  printf("\n\rRF24/examples/pingpair/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  // optionally, increase the delay between retries & # of retries
+  radio.setRetries(15,15);
+
+  // optionally, reduce the payload size.  seems to
+  // improve reliability
+//  radio.setPayloadSize(8);
+ radio.setChannel(0x4c);
+     radio.setPALevel(RF24_PA_MAX);
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens two pipes for these two nodes to communicate
+  // back and forth.
+  // Open 'our' pipe for writing
+  // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading)
+
+  if ( role == role_ping_out )
+  {
+    radio.openWritingPipe(pipes[0]);
+    radio.openReadingPipe(1,pipes[1]);
+  }
+  else
+  {
+    radio.openWritingPipe(pipes[1]);
+    radio.openReadingPipe(1,pipes[0]);
+  }
+
+  //
+  // Start listening
+  //
+
+  radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+}
+
+void loop(void)
+{
+  //
+  // Ping out role.  Repeatedly send the current time
+  //
+
+  if (role == role_ping_out)
+  {
+    // First, stop listening so we can talk.
+    radio.stopListening();
+
+    // Take the time, and send it.  This will block until complete
+    unsigned long time = __millis();
+    printf("Now sending %lu...",time);
+    bool ok = radio.write( &time, sizeof(unsigned long) );
+    
+    if (ok)
+      printf("ok...");
+    else
+      printf("failed.\n\r");
+
+    // Now, continue listening
+    radio.startListening();
+
+    // Wait here until we get a response, or timeout (250ms)
+    unsigned long started_waiting_at = __millis();
+    bool timeout = false;
+    while ( ! radio.available() && ! timeout ) {
+	// by bcatalin » Thu Feb 14, 2013 11:26 am 
+	__msleep(5); //add a small delay to let radio.available to check payload
+      if (__millis() - started_waiting_at > 200 )
+        timeout = true;
+    }
+
+    // Describe the results
+    if ( timeout )
+    {
+      printf("Failed, response timed out.\n\r");
+    }
+    else
+    {
+      // Grab the response, compare, and send to debugging spew
+      unsigned long got_time;
+      radio.read( &got_time, sizeof(unsigned long) );
+
+      // Spew it
+      printf("Got response %lu, round-trip delay: %lu\n\r",got_time,__millis()-got_time);
+    }
+
+    // Try again 1s later
+//    delay(1000);
+sleep(1);
+  }
+
+  //
+  // Pong back role.  Receive each packet, dump it out, and send it back
+  //
+
+  if ( role == role_pong_back )
+  {
+    // if there is data ready
+    if ( radio.available() )
+    {
+      // Dump the payloads until we've gotten everything
+      unsigned long got_time;
+      bool done = false;
+      while (!done)
+      {
+        // Fetch the payload, and see if this was the last one.
+        done = radio.read( &got_time, sizeof(unsigned long) );
+
+        // Spew it
+        printf("Got payload %lu...",got_time);
+
+	// Delay just a little bit to let the other unit
+	// make the transition to receiver
+	delay(20);
+      }
+
+      // First, stop listening so we can talk
+      radio.stopListening();
+
+      // Send the final one back.
+      printf("Sent response.\n\r");
+      radio.write( &got_time, sizeof(unsigned long) );
+
+      // Now, resume listening so we catch the next packets.
+      radio.startListening();
+    }
+  }
+}
+
+int main(int argc, char** argv)
+{
+        setup();
+        while(1)
+                loop();
+
+        return 0;
+}
+
+
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/pongtest.cpp b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/pongtest.cpp
new file mode 100644
index 0000000..ac8d5ce
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/pongtest.cpp
@@ -0,0 +1,240 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example RF Radio Ping Pair
+ *
+ * This is an example of how to use the RF24 class.  Write this sketch to two different nodes,
+ * connect the role_pin to ground on one.  The ping node sends the current time to the pong node,
+ * which responds by sending the value back.  The ping node can then see how long the whole cycle
+ * took.
+ */
+
+#include 
+#include 
+
+#include "../RF24.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 9 & 10
+
+//RF24 radio(9,10);
+RF24 radio("/dev/spidev0.0",2000000 , 25);  //spi device, speed and CE,only CE is NEEDED in RPI
+
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'ping' transmitter
+const int role_pin = 7;
+
+//
+// Topology
+//
+
+// Radio pipe addresses for the 2 nodes to communicate.
+const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL };
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes
+// in this system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_ping_out = 1, role_pong_back } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"};
+
+// The role of the current running sketch
+role_e role;
+
+void setup(void)
+{
+  //
+  // Role
+  //
+
+  // set up the role pin
+ // pinMode(role_pin, INPUT);
+  //digitalWrite(role_pin,HIGH);
+ // delay(20); // Just to get a solid reading on the role pin
+
+  // read the address pin, establish our role
+  //if ( ! digitalRead(role_pin) )
+  //  role = role_ping_out;
+  //else
+    role = role_pong_back;
+
+  //
+  // Print preamble:
+  //
+
+  //Serial.begin(115200);
+  //printf_begin();
+  printf("\n\rRF24/examples/pingpair/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  // optionally, increase the delay between retries & # of retries
+  radio.setRetries(15,15);
+
+  // optionally, reduce the payload size.  seems to
+  // improve reliability
+//  radio.setPayloadSize(8);
+ radio.setChannel(0x4c);
+     radio.setPALevel(RF24_PA_LOW);
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens two pipes for these two nodes to communicate
+  // back and forth.
+  // Open 'our' pipe for writing
+  // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading)
+
+  if ( role == role_ping_out )
+  {
+    radio.openWritingPipe(pipes[0]);
+    radio.openReadingPipe(1,pipes[1]);
+  }
+  else
+  {
+    radio.openWritingPipe(pipes[1]);
+    radio.openReadingPipe(1,pipes[0]);
+  }
+
+  //
+  // Start listening
+  //
+
+  radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+}
+
+void loop(void)
+{
+  //
+  // Ping out role.  Repeatedly send the current time
+  //
+
+  if (role == role_ping_out)
+  {
+    // First, stop listening so we can talk.
+    radio.stopListening();
+
+    // Take the time, and send it.  This will block until complete
+    unsigned long time = __millis();
+    printf("Now sending %lu...",time);
+    bool ok = radio.write( &time, sizeof(unsigned long) );
+    
+    if (ok)
+      printf("ok...");
+    else
+      printf("failed.\n\r");
+
+    // Now, continue listening
+    radio.startListening();
+
+    // Wait here until we get a response, or timeout (250ms)
+    unsigned long started_waiting_at = __millis();
+    bool timeout = false;
+    while ( ! radio.available() && ! timeout ) {
+        // by bcatalin » Thu Feb 14, 2013 11:26 am
+        __msleep(5); //add a small delay to let radio.available to check payload
+      if (__millis() - started_waiting_at > 200 )
+        timeout = true;
+    }
+
+
+    // Describe the results
+    if ( timeout )
+    {
+      printf("Failed, response timed out.\n\r");
+    }
+    else
+    {
+      // Grab the response, compare, and send to debugging spew
+      unsigned long got_time;
+      radio.read( &got_time, sizeof(unsigned long) );
+
+      // Spew it
+      printf("Got response %lu, round-trip delay: %lu\n\r",got_time,__millis()-got_time);
+    }
+
+    // Try again 1s later
+//    delay(1000);
+sleep(1);
+  }
+
+  //
+  // Pong back role.  Receive each packet, dump it out, and send it back
+  //
+
+  if ( role == role_pong_back )
+  {
+    // if there is data ready
+    if ( radio.available() )
+    {
+      // Dump the payloads until we've gotten everything
+      unsigned long got_time;
+      bool done = false;
+      while (!done)
+      {
+        // Fetch the payload, and see if this was the last one.
+        done = radio.read( &got_time, sizeof(unsigned long) );
+
+        // Spew it
+        printf("Got payload %lu...",got_time);
+
+	// Delay just a little bit to let the other unit
+	// make the transition to receiver
+	delay(20);
+      }
+
+      // First, stop listening so we can talk
+      radio.stopListening();
+
+      // Send the final one back.
+      printf("Sent response.\n\r");
+      radio.write( &got_time, sizeof(unsigned long) );
+
+      // Now, resume listening so we catch the next packets.
+      radio.startListening();
+    }
+  }
+}
+
+int main(int argc, char** argv)
+{
+        setup();
+        while(1)
+                loop();
+
+        return 0;
+}
+
+
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/rpi-hub.cpp b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/rpi-hub.cpp
new file mode 100644
index 0000000..6892b4e
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/rpi-hub.cpp
@@ -0,0 +1,119 @@
+/* 
+ *
+ *  Filename : rpi-hub.cpp
+ *
+ *  This program makes the RPi as a hub listening to all six pipes from the remote sensor nodes ( usually Arduino )
+ *  and will return the packet back to the sensor on pipe0 so that the sender can calculate the round trip delays
+ *  when the payload matches.
+ *  
+ *  I encounter that at times, it also receive from pipe7 ( or pipe0 ) with content of FFFFFFFFF that I will not sent
+ *  back to the sender
+ *
+ *  Refer to RF24/examples/rpi_hub_arduino/ for the corresponding Arduino sketches to work with this code.
+ * 
+ *  
+ *  CE is not used and CSN is GPIO25 (not pinout)
+ *
+ *  Refer to RPi docs for GPIO numbers
+ *
+ *  Author : Stanley Seow
+ *  e-mail : stanleyseow@gmail.com
+ *  date   : 6th Mar 2013
+ *
+ */
+
+#include 
+#include 
+#include "../RF24.h"
+
+using namespace std;
+
+// Radio pipe addresses for the 2 nodes to communicate.
+// First pipe is for writing, 2nd, 3rd, 4th, 5th & 6th is for reading...
+const uint64_t pipes[6] = { 0xF0F0F0F0D2LL, 0xF0F0F0F0E1LL, 0xF0F0F0F0E2LL, 0xF0F0F0F0E3LL, 0xF0F0F0F0F1, 0xF0F0F0F0F2 };
+
+// CE and CSN pins On header using GPIO numbering (not pin numbers)
+RF24 radio("/dev/spidev0.0",8000000,25);  // Setup for GPIO 25 CSN
+
+
+void setup(void)
+{
+	//
+	// Refer to RF24.h or nRF24L01 DS for settings
+	radio.begin();
+	radio.enableDynamicPayloads();
+	radio.setAutoAck(1);
+	radio.setRetries(15,15);
+	radio.setDataRate(RF24_1MBPS);
+	radio.setPALevel(RF24_PA_MAX);
+	radio.setChannel(76);
+	radio.setCRCLength(RF24_CRC_16);
+
+	// Open 6 pipes for readings ( 5 plus pipe0, also can be used for reading )
+	radio.openWritingPipe(pipes[0]);
+	radio.openReadingPipe(1,pipes[1]);
+	radio.openReadingPipe(2,pipes[2]);
+	radio.openReadingPipe(3,pipes[3]);
+	radio.openReadingPipe(4,pipes[4]);
+	radio.openReadingPipe(5,pipes[5]);
+
+	//
+	// Start listening
+	//
+
+	radio.startListening();
+
+	//
+	// Dump the configuration of the rf unit for debugging
+	//
+
+	radio.printDetails();
+	printf("\n\rOutput below : \n\r");
+	usleep(1000);
+}
+
+void loop(void)
+{
+	char receivePayload[32];
+	uint8_t pipe = 1;
+	
+	// Start listening
+	radio.startListening();
+
+        
+	 while ( radio.available(&pipe) ) {
+
+		uint8_t len = radio.getDynamicPayloadSize();
+		radio.read( receivePayload, len );
+
+		// Display it on screen
+		printf("Recv: size=%i payload=%s pipe=%i",len,receivePayload,pipe);
+
+		// Send back payload to sender
+		radio.stopListening();
+
+		// if pipe is 7, do not send it back
+		if ( pipe != 7 ) {
+			radio.write(receivePayload,len);
+			receivePayload[len]=0;
+			printf("\t Send: size=%i payload=%s pipe:%i\n\r",len,receivePayload,pipe);
+		} else {
+			printf("\n\r");
+                }
+		pipe++;
+		// reset pipe to 0
+		if ( pipe > 6 ) pipe = 0;
+	}
+	usleep(20);
+}
+
+
+int main(int argc, char** argv) 
+{
+	setup();
+	while(1)
+		loop();
+	
+	return 0;
+}
+
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/scanner.cpp b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/scanner.cpp
new file mode 100644
index 0000000..62a1010
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/examples/scanner.cpp
@@ -0,0 +1,189 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Channel scanner
+ *
+ * Example to detect interference on the various channels available.
+ * This is a good diagnostic tool to check whether you're picking a
+ * good channel for your application.
+ *
+ * Inspired by cpixip.
+ * See http://arduino.cc/forum/index.php/topic,54795.0.html
+ */
+
+#include 
+#include 
+#include "../RF24.h"
+
+using namespace std;
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 9 & 10
+
+// CE and CSN pins 
+//RF24 radio(8, 25);  //only CSN is NEEDED in RPI
+RF24 radio("/dev/spidev0.0",8000000 , 25);  //spi device, speed and CSN,only CSN is NEEDED in RPI
+
+//
+// Channel info
+//
+
+//const uint8_t num_channels = 128;
+const uint8_t num_channels = 120;
+uint8_t values[num_channels];
+
+//
+// Setup
+//
+
+void setup(void)
+{
+  //
+  // Print preamble
+  //
+
+  //Serial.begin(57600);
+  //printf_begin();
+  printf("\n\rRF24/examples/scanner/\n\r");
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+  radio.setAutoAck(false);
+
+  // Get into standby mode
+  radio.startListening();
+  radio.stopListening();
+
+  radio.printDetails();
+
+  // Print out header, high then low digit
+  int i = 0;
+  while ( i < num_channels )
+  {
+    printf("%x",i>>4);
+    ++i;
+  }
+  printf("\n\r");
+  i = 0;
+  while ( i < num_channels )
+  {
+    printf("%x",i&0xf);
+    ++i;
+  }
+  printf("\n\r");
+
+}
+
+//
+// Loop
+//
+/*
+const int num_reps = 100;
+
+void loop2(void)
+{
+  // Clear measurement values
+  memset(values,0,sizeof(values));
+
+  // Scan all channels num_reps times
+  int rep_counter = num_reps;
+  while (rep_counter--)
+  {
+    int i = num_channels;
+    while (i--)
+    {
+      // Select this channel
+      radio.setChannel(i);
+
+      // Listen for a little
+      radio.startListening();
+      delayMicroseconds(128);
+      radio.stopListening();
+
+      // Did we get a carrier?
+      if ( radio.testCarrier() )
+        ++values[i];
+    }
+  }
+
+  // Print out channel measurements, clamped to a single hex digit
+  int i = 0;
+  while ( i < num_channels )
+  {
+    printf("%x",min(0xf,values[i]&0xf));
+    ++i;
+  }
+  printf("\n\r");
+}
+*/
+//
+// Loop
+//
+
+const int num_reps = 100;
+
+int reset_array=0;
+
+void loop(void)
+{
+
+if ( reset_array == 1 ) {	
+  // Clear measurement values
+  memset(values,0,sizeof(values));
+  printf("\n\r");
+}
+
+  // Scan all channels num_reps times
+    int i = num_channels;
+    while (i--)
+    {
+      // Select this channel
+      radio.setChannel(i);
+
+      // Listen for a little
+      radio.startListening();
+      delayMicroseconds(128);
+      radio.stopListening();
+
+      // Did we get a carrier?
+      if ( radio.testCarrier() )
+        ++values[i];
+	if ( values[i] == 0xf ) {
+		reset_array = 2;
+	}
+    }
+
+  // Print out channel measurements, clamped to a single hex digit
+  i = 0;
+  while ( i < num_channels )
+  {
+    printf("%x",min(0xf,values[i]&0xf));
+    ++i;
+  }
+  printf("\n\r");
+}
+
+int main(int argc, char** argv)
+{
+        setup();
+        while(1)
+                loop();
+
+        return 0;
+}
+
+
+
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/gpio.cpp b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/gpio.cpp
new file mode 100644
index 0000000..64f33c3
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/gpio.cpp
@@ -0,0 +1,68 @@
+/* 
+ * https://github.com/mrshu/GPIOlib
+ * Copyright (c) 2011, Copyright (c) 2011 mr.Shu
+ * All rights reserved. 
+ * 
+ * Modified on 24 June 2012, 11:06 AM
+ * File:   gpio.cpp
+ * Author: purinda (purinda@gmail.com)
+ * 
+ */
+
+#include "gpio.h"
+
+GPIO::GPIO() {
+}
+
+GPIO::~GPIO() {
+}
+
+void GPIO::open(int port, int DDR)
+{
+	FILE *f;
+	f = fopen("/sys/class/gpio/export", "w");
+	fprintf(f, "%d\n", port);
+	fclose(f);
+
+	char file[128];
+	sprintf(file, "/sys/class/gpio/gpio%d/direction", port);
+	f = fopen(file, "w");
+	if (DDR == 0)	fprintf(f, "in\n");
+	else		fprintf(f, "out\n");
+	fclose(f);
+}
+
+void GPIO::close(int port)
+{
+	FILE *f;
+	f = fopen("/sys/class/gpio/unexport", "w");
+	fprintf(f, "%d\n", port);
+	fclose(f);
+}
+
+int GPIO::read(int port)
+{
+	FILE *f;
+	
+	char file[128];
+	sprintf(file, "/sys/class/gpio/gpio%d/value", port);
+	f = fopen(file, "r");
+
+	int i;
+	fscanf(f, "%d", &i);
+	fclose(f);
+	return i;
+
+}
+void GPIO::write(int port, int value){
+	FILE *f;
+
+	char file[128];
+	sprintf(file, "/sys/class/gpio/gpio%d/value", port);
+	f = fopen(file, "w");
+	
+	if (value == 0)	fprintf(f, "0\n");
+	else		fprintf(f, "1\n");
+	
+	fclose(f);
+}
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/gpio.h b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/gpio.h
new file mode 100644
index 0000000..0bee421
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/gpio.h
@@ -0,0 +1,60 @@
+/* 
+ * https://github.com/mrshu/GPIOlib
+ * Copyright (c) 2011, Copyright (c) 2011 mr.Shu
+ * All rights reserved. 
+ * 
+ * Modified on 24 June 2012, 11:06 AM
+ * File:   gpio.h
+ * Author: purinda (purinda@gmail.com)
+ * 
+ */
+
+#ifndef H
+#define	H
+
+#include 
+
+class GPIO {
+public:
+
+	/* Constants */
+	static const int DIRECTION_OUT = 1;
+	static const int DIRECTION_IN = 0;
+	
+	static const int OUTPUT_HIGH = 1;
+	static const int OUTPUT_LOW = 0;
+		
+	GPIO();
+	
+	/**
+	 * 
+     * @param port
+     * @param DDR
+     */
+	static void open(int port, int DDR);
+	/**
+	 * 
+     * @param port
+     */
+	static void close(int port);
+	/**
+	 * 
+     * @param port
+     * @param value
+     */
+	static int read(int port);
+	/**
+	* 
+	* @param port
+	* @param value
+	*/	
+	static void write(int port,int value);	
+	
+	virtual ~GPIO();
+	
+private:
+
+};
+
+#endif	/* H */
+
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/librf24.so.1.0 b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/librf24.so.1.0
new file mode 100644
index 0000000..3b4dafc
Binary files /dev/null and b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/librf24.so.1.0 differ
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/nRF24L01.h b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/nRF24L01.h
new file mode 100644
index 0000000..2012ce6
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/nRF24L01.h
@@ -0,0 +1,125 @@
+/*
+    Copyright (c) 2007 Stefan Engelke 
+
+    Permission is hereby granted, free of charge, to any person 
+    obtaining a copy of this software and associated documentation 
+    files (the "Software"), to deal in the Software without 
+    restriction, including without limitation the rights to use, copy, 
+    modify, merge, publish, distribute, sublicense, and/or sell copies 
+    of the Software, and to permit persons to whom the Software is 
+    furnished to do so, subject to the following conditions:
+
+    The above copyright notice and this permission notice shall be 
+    included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
+    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
+    NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 
+    HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 
+    WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 
+    OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
+    DEALINGS IN THE SOFTWARE.
+*/
+
+/* Memory Map */
+#define CONFIG      0x00
+#define EN_AA       0x01
+#define EN_RXADDR   0x02
+#define SETUP_AW    0x03
+#define SETUP_RETR  0x04
+#define RF_CH       0x05
+#define RF_SETUP    0x06
+#define STATUS      0x07
+#define OBSERVE_TX  0x08
+#define CD          0x09
+#define RX_ADDR_P0  0x0A
+#define RX_ADDR_P1  0x0B
+#define RX_ADDR_P2  0x0C
+#define RX_ADDR_P3  0x0D
+#define RX_ADDR_P4  0x0E
+#define RX_ADDR_P5  0x0F
+#define TX_ADDR     0x10
+#define RX_PW_P0    0x11
+#define RX_PW_P1    0x12
+#define RX_PW_P2    0x13
+#define RX_PW_P3    0x14
+#define RX_PW_P4    0x15
+#define RX_PW_P5    0x16
+#define FIFO_STATUS 0x17
+#define DYNPD	    0x1C
+#define FEATURE	    0x1D
+
+/* Bit Mnemonics */
+#define MASK_RX_DR  6
+#define MASK_TX_DS  5
+#define MASK_MAX_RT 4
+#define EN_CRC      3
+#define CRCO        2
+#define PWR_UP      1
+#define PRIM_RX     0
+#define ENAA_P5     5
+#define ENAA_P4     4
+#define ENAA_P3     3
+#define ENAA_P2     2
+#define ENAA_P1     1
+#define ENAA_P0     0
+#define ERX_P5      5
+#define ERX_P4      4
+#define ERX_P3      3
+#define ERX_P2      2
+#define ERX_P1      1
+#define ERX_P0      0
+#define AW          0
+#define ARD         4
+#define ARC         0
+#define PLL_LOCK    4
+#define RF_DR       3
+#define RF_PWR      6
+#define RX_DR       6
+#define TX_DS       5
+#define MAX_RT      4
+#define RX_P_NO     1
+#define TX_FULL     0
+#define PLOS_CNT    4
+#define ARC_CNT     0
+#define TX_REUSE    6
+#define FIFO_FULL   5
+#define TX_EMPTY    4
+#define RX_FULL     1
+#define RX_EMPTY    0
+#define DPL_P5	    5
+#define DPL_P4	    4
+#define DPL_P3	    3
+#define DPL_P2	    2
+#define DPL_P1	    1
+#define DPL_P0	    0
+#define EN_DPL	    2
+#define EN_ACK_PAY  1
+#define EN_DYN_ACK  0
+
+/* Instruction Mnemonics */
+#define R_REGISTER    0x00
+#define W_REGISTER    0x20
+#define REGISTER_MASK 0x1F
+#define ACTIVATE      0x50
+#define R_RX_PL_WID   0x60
+#define R_RX_PAYLOAD  0x61
+#define W_TX_PAYLOAD  0xA0
+#define W_ACK_PAYLOAD 0xA8
+#define FLUSH_TX      0xE1
+#define FLUSH_RX      0xE2
+#define REUSE_TX_PL   0xE3
+#define NOP           0xFF
+
+/* Non-P omissions */
+#define LNA_HCURR   0
+
+/* P model memory Map */
+#define RPD         0x09
+
+/* P model bit Mnemonics */
+#define RF_DR_LOW   5
+#define RF_DR_HIGH  3
+#define RF_PWR_LOW  1
+#define RF_PWR_HIGH 2
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/readme.txt b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/readme.txt
new file mode 100644
index 0000000..e41b725
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/readme.txt
@@ -0,0 +1,31 @@
+this is library to use the nrf24l01 on the raspberry pi.
+
+it's based on the arduino lib from J. Coliz .
+the library was berryfied by Purinda Gunasekara .
+
+examples
+========
+you need to set the library path:
+cd examples
+export LD_LIBRARY_PATH=.
+./pingtest
+
+In my examples I used /dev/spidev0.0 and GPIO25
+I have a model 1 rpi so you should check if the pins are on the same spot
+nrf-vcc = rpi-3v3 (1)
+nrf-gnd = rpi-gnd (6)
+nrf-ce =  rpi-ce0 (24)
+nrf-csn = rpi-gpio25 (22)
+nrf-sck = rpi-sckl (23)
+nrf-mo = rpi-mosi (19)
+nrf-mi = rpi-miso (21)
+
+known issues
+============
+spidev0.0 or spidev0.1 doesn't seem to work. 
+
+contact
+=======
+Arco van Geest 
+
+
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/spi.cpp b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/spi.cpp
new file mode 100644
index 0000000..a033c1e
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/spi.cpp
@@ -0,0 +1,132 @@
+/* 
+ * File:   spi.cpp
+ * Author: Purinda Gunasekara 
+ * 
+ * Created on 24 June 2012, 11:00 AM
+ * 
+ * Inspired from spidev test in linux kernel documentation
+ * www.kernel.org/doc/Documentation/spi/spidev_test.c 
+ */
+
+#include "spi.h"
+
+SPI::SPI() {
+	
+//	this->device = "/dev/spidev0.0";;
+	this->bits = 8;
+//	this->speed = 24000000; // 24Mhz - proly doesnt work
+//	this->speed = 16000000; // 16Mhz 
+//	this->speed = 8000000; // 8Mhz 
+	this->speed = 2000000; // 2Mhz 
+	this->mode = 0;
+
+//	this->init();
+}
+
+void SPI::setbits( uint8_t bits )
+{
+ this->bits = bits;
+}
+
+void SPI::setspeed( uint32_t speed )
+{
+ this->speed = speed;
+}
+
+void SPI::setdevice( string devicefile ) 
+{
+	this->device = devicefile;
+}
+
+void SPI::init()
+{
+	int ret;
+	this->fd = open(this->device.c_str(), O_RDWR);
+	if (this->fd < 0)
+	{
+		perror("can't open device");
+		abort();
+	}
+
+	/*
+	 * spi mode
+	 */
+	ret = ioctl(this->fd, SPI_IOC_WR_MODE, &this->mode);
+	if (ret == -1)
+	{
+		perror("can't set spi mode");
+		abort();		
+	}
+
+	ret = ioctl(this->fd, SPI_IOC_RD_MODE, &this->mode);
+	if (ret == -1)
+	{
+		perror("can't set spi mode");
+		abort();				
+	}
+	
+	/*
+	 * bits per word
+	 */
+	ret = ioctl(this->fd, SPI_IOC_WR_BITS_PER_WORD, &this->bits);
+	if (ret == -1)
+	{
+		perror("can't set bits per word");
+		abort();				
+	}
+
+	ret = ioctl(this->fd, SPI_IOC_RD_BITS_PER_WORD, &this->bits);
+	if (ret == -1)
+	{
+		perror("can't set bits per word");
+		abort();						
+	}
+	/*
+	 * max speed hz
+	 */
+	ret = ioctl(this->fd, SPI_IOC_WR_MAX_SPEED_HZ, &this->speed);
+	if (ret == -1)
+	{
+		perror("can't set max speed hz");
+		abort();						
+	}
+
+	ret = ioctl(this->fd, SPI_IOC_RD_MAX_SPEED_HZ, &this->speed);
+	if (ret == -1)
+	{
+		perror("can't set max speed hz");
+		abort();						
+	}
+}
+
+uint8_t SPI::transfer(uint8_t tx_)
+{
+	int ret;
+	// One byte is transfered at once
+	uint8_t tx[] = {0};
+	tx[0] = tx_;
+
+	uint8_t rx[ARRAY_SIZE(tx)] = {0};
+	struct spi_ioc_transfer tr;
+	tr.tx_buf = (unsigned long)tx;
+	tr.rx_buf = (unsigned long)rx;
+	tr.len = ARRAY_SIZE(tx);
+	tr.delay_usecs = 0;
+//	tr.cs_change = 1;
+	tr.speed_hz = this->speed;
+	tr.bits_per_word = this->bits;
+
+	ret = ioctl(this->fd, SPI_IOC_MESSAGE(1), &tr);
+	if (ret < 1)
+	{
+		perror("can't send spi message");
+		abort();		
+	}
+
+	return rx[0];
+}
+
+SPI::~SPI() {
+	close(this->fd);
+}
+
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/spi.h b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/spi.h
new file mode 100644
index 0000000..f0b83a0
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/librf24/spi.h
@@ -0,0 +1,53 @@
+/* 
+ * File:   spi.h
+ * Author: Purinda Gunasekara 
+ * 
+ * Created on 24 June 2012, 11:00 AM
+ */
+
+#ifndef SPI_H
+#define	SPI_H
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+using namespace std;
+
+class SPI {
+public:
+	
+	SPI();
+	uint8_t transfer(uint8_t tx_);
+	virtual ~SPI();
+	void init();	
+	void setdevice( string devicefile );
+	void setbits( uint8_t bits );
+	void setspeed( uint32_t speed );
+
+private:
+
+	// Default SPI device
+	string device;
+	// SPI Mode set 
+	uint8_t mode;
+	// word size
+	uint8_t bits;
+	// Set SPI speed
+	uint32_t speed;
+	int fd;
+
+};
+
+#endif	/* SPI_H */
+
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/readme.md b/hardware/digistump/sam/libraries/RF24/librf24-rpi/readme.md
new file mode 100644
index 0000000..da0d122
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/readme.md
@@ -0,0 +1,42 @@
+Raspberry Pi RF24 libraries
+===========================
+
+This is the collection of libraries for RF24 / NRF24L01 wireless modules on the raspberry pi.
+
+There are two folders with two different libraries :-
+
+- librf24 	 This library/driver are ported from Arduino to beaglebone then to RPi
+- librf24-bcm 	 This library/driver are further ported to use Broadcom bcm2835 using hardware SPI
+
+Setup
+=====
+1. Change to the selected folder
+2. Execute "make" and "sudo make install" to install the shared libraries
+3. Change to examples folder, change to the correct connected pins and execte "make"
+
+
+
+Known issues
+============
+- the current bcm2835 drivers still have some minor bugs
+
+Links 
+=====
+- Forum links : http://www.raspberrypi.org/phpBB3/viewtopic.php?f=45&t=17061
+- C library for Broadcom BCM 2835 http://www.open.com.au/mikem/bcm2835/index.html
+- Maniacbug RF24 http://maniacbug.github.com/RF24/index.html
+- RF24 Class Reference http://maniacbug.github.com/RF24/classRF24.html
+
+
+Contact
+=======
+Stanley Seow ( stanleyseow@gmail.com )
+https://github.com/stanleyseow/RF24
+
+RF24 for RPi using gpio :-
+Arco van Geest  
+https://github.com/gnulnulf/RF24
+
+RF24 for RPi using bcm2835 :-
+Charles-Henri Hallard http://hallard.me/ 
+https://github.com/hallard/RF24
diff --git a/hardware/digistump/sam/libraries/RF24/librf24-rpi/readme.txt b/hardware/digistump/sam/libraries/RF24/librf24-rpi/readme.txt
new file mode 100644
index 0000000..e41b725
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/librf24-rpi/readme.txt
@@ -0,0 +1,31 @@
+this is library to use the nrf24l01 on the raspberry pi.
+
+it's based on the arduino lib from J. Coliz .
+the library was berryfied by Purinda Gunasekara .
+
+examples
+========
+you need to set the library path:
+cd examples
+export LD_LIBRARY_PATH=.
+./pingtest
+
+In my examples I used /dev/spidev0.0 and GPIO25
+I have a model 1 rpi so you should check if the pins are on the same spot
+nrf-vcc = rpi-3v3 (1)
+nrf-gnd = rpi-gnd (6)
+nrf-ce =  rpi-ce0 (24)
+nrf-csn = rpi-gpio25 (22)
+nrf-sck = rpi-sckl (23)
+nrf-mo = rpi-mosi (19)
+nrf-mi = rpi-miso (21)
+
+known issues
+============
+spidev0.0 or spidev0.1 doesn't seem to work. 
+
+contact
+=======
+Arco van Geest 
+
+
diff --git a/hardware/digistump/sam/libraries/RF24/nRF24L01.h b/hardware/digistump/sam/libraries/RF24/nRF24L01.h
new file mode 100644
index 0000000..2012ce6
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/nRF24L01.h
@@ -0,0 +1,125 @@
+/*
+    Copyright (c) 2007 Stefan Engelke 
+
+    Permission is hereby granted, free of charge, to any person 
+    obtaining a copy of this software and associated documentation 
+    files (the "Software"), to deal in the Software without 
+    restriction, including without limitation the rights to use, copy, 
+    modify, merge, publish, distribute, sublicense, and/or sell copies 
+    of the Software, and to permit persons to whom the Software is 
+    furnished to do so, subject to the following conditions:
+
+    The above copyright notice and this permission notice shall be 
+    included in all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
+    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
+    NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 
+    HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 
+    WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 
+    OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
+    DEALINGS IN THE SOFTWARE.
+*/
+
+/* Memory Map */
+#define CONFIG      0x00
+#define EN_AA       0x01
+#define EN_RXADDR   0x02
+#define SETUP_AW    0x03
+#define SETUP_RETR  0x04
+#define RF_CH       0x05
+#define RF_SETUP    0x06
+#define STATUS      0x07
+#define OBSERVE_TX  0x08
+#define CD          0x09
+#define RX_ADDR_P0  0x0A
+#define RX_ADDR_P1  0x0B
+#define RX_ADDR_P2  0x0C
+#define RX_ADDR_P3  0x0D
+#define RX_ADDR_P4  0x0E
+#define RX_ADDR_P5  0x0F
+#define TX_ADDR     0x10
+#define RX_PW_P0    0x11
+#define RX_PW_P1    0x12
+#define RX_PW_P2    0x13
+#define RX_PW_P3    0x14
+#define RX_PW_P4    0x15
+#define RX_PW_P5    0x16
+#define FIFO_STATUS 0x17
+#define DYNPD	    0x1C
+#define FEATURE	    0x1D
+
+/* Bit Mnemonics */
+#define MASK_RX_DR  6
+#define MASK_TX_DS  5
+#define MASK_MAX_RT 4
+#define EN_CRC      3
+#define CRCO        2
+#define PWR_UP      1
+#define PRIM_RX     0
+#define ENAA_P5     5
+#define ENAA_P4     4
+#define ENAA_P3     3
+#define ENAA_P2     2
+#define ENAA_P1     1
+#define ENAA_P0     0
+#define ERX_P5      5
+#define ERX_P4      4
+#define ERX_P3      3
+#define ERX_P2      2
+#define ERX_P1      1
+#define ERX_P0      0
+#define AW          0
+#define ARD         4
+#define ARC         0
+#define PLL_LOCK    4
+#define RF_DR       3
+#define RF_PWR      6
+#define RX_DR       6
+#define TX_DS       5
+#define MAX_RT      4
+#define RX_P_NO     1
+#define TX_FULL     0
+#define PLOS_CNT    4
+#define ARC_CNT     0
+#define TX_REUSE    6
+#define FIFO_FULL   5
+#define TX_EMPTY    4
+#define RX_FULL     1
+#define RX_EMPTY    0
+#define DPL_P5	    5
+#define DPL_P4	    4
+#define DPL_P3	    3
+#define DPL_P2	    2
+#define DPL_P1	    1
+#define DPL_P0	    0
+#define EN_DPL	    2
+#define EN_ACK_PAY  1
+#define EN_DYN_ACK  0
+
+/* Instruction Mnemonics */
+#define R_REGISTER    0x00
+#define W_REGISTER    0x20
+#define REGISTER_MASK 0x1F
+#define ACTIVATE      0x50
+#define R_RX_PL_WID   0x60
+#define R_RX_PAYLOAD  0x61
+#define W_TX_PAYLOAD  0xA0
+#define W_ACK_PAYLOAD 0xA8
+#define FLUSH_TX      0xE1
+#define FLUSH_RX      0xE2
+#define REUSE_TX_PL   0xE3
+#define NOP           0xFF
+
+/* Non-P omissions */
+#define LNA_HCURR   0
+
+/* P model memory Map */
+#define RPD         0x09
+
+/* P model bit Mnemonics */
+#define RF_DR_LOW   5
+#define RF_DR_HIGH  3
+#define RF_PWR_LOW  1
+#define RF_PWR_HIGH 2
diff --git a/hardware/digistump/sam/libraries/RF24/tests/README b/hardware/digistump/sam/libraries/RF24/tests/README
new file mode 100644
index 0000000..43ceaf5
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/README
@@ -0,0 +1,7 @@
+The sketches in this directory are intended to be checkin tests.
+No code should be pushed to github without these tests passing.
+
+See "runtests.sh" script inside each sketch dir.  This script is fully compatible with
+git bisest.
+
+Note that this requires python and py-serial
diff --git a/hardware/digistump/sam/libraries/RF24/tests/native/Jamfile b/hardware/digistump/sam/libraries/RF24/tests/native/Jamfile
new file mode 100644
index 0000000..10d0336
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/native/Jamfile
@@ -0,0 +1,300 @@
+PROJECT_NAME 	= $(PWD:B) ;
+PROJECT_DIR 	= . ;
+PROJECT_LIBS 	= RF24 ;
+
+OUT_DIR 	= ojam ;
+F_CPU 		= 16000000 ;
+MCU             = atmega328p ;
+PORTS           = /dev/tty.usbserial-A600eHIs /dev/tty.usbserial-A40081RP /dev/tty.usbserial-A9007LmI ;
+
+UPLOAD_RATE 	= 57600 ;
+AVRDUDE_PROTOCOL = stk500v1 ;
+COM 		= 33 ;
+
+# Host-specific overrides for locations 
+if $(OS) = MACOSX 
+{
+ARDUINO_VERSION	= 22 ;
+OLD_DIR 	= /opt/arduino-0021 ;
+AVR_TOOLS_PATH 	= $(OLD_DIR)/hardware/tools/avr/bin ;
+AVRDUDECONFIG_PATH = $(OLD_DIR)/hardware/tools/avr/etc ;
+ARDUINO_DIR 	= /opt/Arduino ;
+ARDUINO_AVR 	= /usr/lib/avr/include ;
+}
+
+# Where is everything?
+ARDUINO_VERSION	?= 22 ;
+SKETCH_DIR      = $(HOME)/Source/Arduino ;
+AVR_TOOLS_PATH 	?= /usr/bin ;
+ARDUINO_DIR 	?= /opt/arduino-00$(ARDUINO_VERSION) ;
+ARDUINO_AVR 	?= $(ARDUINO_DIR)/hardware/tools/avr/avr/include/avr ;
+AVRDUDECONFIG_PATH ?= $(ARDUINO_DIR)/hardware/tools ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/arduino ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(SKETCH_DIR)/libraries ;
+AVR_AS  	= $(AVR_TOOLS_PATH)/avr-as ;
+AVR_CC  	= $(AVR_TOOLS_PATH)/avr-gcc ;
+AVR_CXX  	= $(AVR_TOOLS_PATH)/avr-g++ ;
+AVR_LD  	= $(AVR_TOOLS_PATH)/avr-gcc ;
+AVR_OBJCOPY 	= $(AVR_TOOLS_PATH)/avr-objcopy ;
+AVRDUDE 	= $(AVR_TOOLS_PATH)/avrdude ;
+
+DEFINES  	= F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H HAL=1 ;
+CTUNING  	= -ffunction-sections -fdata-sections ;
+CXXTUNING  	= -fno-exceptions -fno-strict-aliasing ; 
+ASFLAGS  	= -mmcu=$(MCU) ; 
+CFLAGS  	= -Os -Wall -Wextra $(ASFLAGS) $(CTUNING) ;
+CXXFLAGS  	= $(CFLAGS) $(CXXTUNING) ;
+LDFLAGS  	= -Os -lm -Wl,--gc-sections -mmcu=atmega328p ;
+
+# Search everywhere for headers
+HDRS  	 	= $(PROJECT_DIR) $(ARDUINO_AVR) $(ARDUINO_CORE) [ GLOB $(ARDUINO_LIB) $(SKETCH_LIB) : [^.]* ] ;
+HDRS  	 	+= [ GLOB $(HDRS) : utility ] ;
+
+# Grab everything from the core directory
+CORE_MODULES  	= [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+LIB_MODULES  	= [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ;
+
+# In addition to explicitly-specified program modules, pick up anything from the current
+# dir.
+PROJECT_MODULES += [ GLOB $(PROJECT_DIR) : *.c *.cpp *.pde ] ;
+
+# Shortcut for the out files
+OUT             = $(OUT_DIR)/$(PROJECT_NAME) ;
+
+# AvrDude setup
+AVRDUDE_FLAGS = -V -F -D -C $(AVRDUDECONFIG_PATH)/avrdude.conf -p $(MCU) -c $(AVRDUDE_PROTOCOL) -b $(UPLOAD_RATE) ;
+
+rule GitVersion
+{
+  Always $(<) ;
+  Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+  echo "const char program_version[] = \"\\" > $(<)
+  git log -1 --pretty=format:%h >> $(<)
+  echo "\";" >> $(<)
+}
+
+# GitVersion version.h ;
+
+rule AvrAsm
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrAsm
+{
+  $(AVR_AS) $(ASFLAGS) -o $(<) $(>) 
+}
+
+rule AvrCc
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrCc
+{
+  $(AVR_CC) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CFLAGS) $(>) 
+}
+
+rule AvrC++
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrC++
+{
+  $(AVR_CXX) -c -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) 
+}
+
+rule AvrAsmFromC++
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+
+  CCHDRS on $(<) = [ on $(<) FIncludes $(HDRS) ] ;
+  CCDEFS on $(<) = [ on $(<) FDefines $(DEFINES) ] ;
+}
+
+actions AvrAsmFromC++
+{
+  $(AVR_CXX) -S -fverbose-asm -o $(<) $(CCHDRS) $(CCDEFS) $(CXXFLAGS) $(>) 
+}
+
+rule Pde
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Clean clean : $(<) ;
+}
+
+actions Pde
+{
+  echo "#include " > $(<) 
+  echo "#line 1 \"$(>)\"" >> $(<)
+  cat $(>) >> $(<) 
+}
+
+rule AvrPde
+{
+  local _CPP = $(OUT_DIR)/$(_I:B).cpp ;
+  Pde $(_CPP) : $(>) ;
+  AvrC++ $(<) : $(_CPP) ;
+}
+
+rule AvrObject
+{
+  switch $(>:S)
+  {
+    case .S :   AvrAsm $(<) : $(>) ;
+    case .c :   AvrCc $(<) : $(>) ;
+    case .cpp : AvrC++ $(<) : $(>) ;
+    case .pde : AvrPde $(<) : $(>) ;
+  }
+}
+
+rule AvrObjects
+{
+  for _I in $(<) 
+  {
+    AvrObject $(OUT_DIR)/$(_I:B).o : $(_I) ;
+  }
+}
+
+rule AvrMainFromObjects
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  MkDir $(<:D) ;
+  Depends all : $(<) ;
+  Clean clean : $(<) ;
+}
+
+actions AvrMainFromObjects
+{
+  $(AVR_LD) $(LDFLAGS) -o $(<) $(>) 
+}
+
+rule AvrMain
+{
+  AvrMainFromObjects $(<) : $(OUT_DIR)/$(>:B).o ;
+  AvrObjects $(>) ;
+}
+
+rule AvrHex
+{
+  Depends $(<) : $(>) ;
+  Depends $(<) : $(<:D) ;
+  Depends hex : $(<) ;
+  Clean clean : $(<) ;
+}
+
+actions AvrHex
+{
+  $(AVR_OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule AvrUpload
+{
+  Depends $(1) : $(2) ;
+  Depends $(2) : $(3) ;
+  NotFile $(1) ;
+  Always $(1) ;
+  Always $(2) ;
+  AvrUploadAction $(2) : $(3) ;
+}
+
+actions AvrUploadAction
+{
+  $(AVRDUDE) $(AVRDUDE_FLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+AvrMain $(OUT).elf : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES)
+AvrHex $(OUT).hex : $(OUT).elf ;
+
+AvrUpload p6 : /dev/tty.usbserial-A600eHIs : $(OUT).hex ;
+AvrUpload p4 : /dev/tty.usbserial-A40081RP : $(OUT).hex ;
+AvrUpload p9 : /dev/tty.usbserial-A9007LmI : $(OUT).hex ;
+
+#
+# Native
+#
+
+OUT_DIR_NATIVE 	= out_native ;
+OUT_NATIVE      = $(OUT_DIR_NATIVE)/$(PROJECT_NAME) ;
+NATIVE_CORE    = $(SKETCH_DIR)/hardware/native ;
+HDRS = $(NATIVE_CORE) $(HDRS) ;
+NATIVE_CORE_MODULES = [ GLOB $(NATIVE_CORE) : *.c *.cpp ] ;
+NATIVE_MODULES  = ; 
+DEFINES += NATIVE ;
+
+rule NativePde
+{
+  local _CPP = $(OUT_DIR_NATIVE)/$(_I:B).cpp ;
+  Pde $(_CPP) : $(>) ;
+  C++ $(<) : $(_CPP) ;
+}
+
+rule UserObject
+{
+  switch $(>)
+  {
+  case *.pde : NativePde $(<) : $(>) ;
+  }
+} 
+
+rule Objects
+{
+  for _I in $(<) 
+  {
+    local _O = $(OUT_DIR_NATIVE)/$(_I:B).o ;
+    Object $(_O) : $(_I) ;
+  }
+}
+
+rule Main
+{
+  MainFromObjects $(<) : $(OUT_DIR_NATIVE)/$(>:B).o ;
+  Objects $(>) ;
+}
+
+actions C++
+{
+  c++ -c -o $(<) $(CCHDRS) $(CCDEFS) $(>) 
+}
+
+actions Link 
+{
+  c++  -o $(<) $(>) 
+}
+
+
+
+MkDir $(OUT_DIR_NATIVE) ;
+Depends $(OUT_NATIVE) : $(OUT_DIR_NATIVE) ;
+Main $(OUT_NATIVE) : $(NATIVE_CORE_MODULES) $(NATIVE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ;
+
+Depends native : $(OUT_NATIVE) ;
+
diff --git a/hardware/digistump/sam/libraries/RF24/tests/native/pingpair_irq.pde b/hardware/digistump/sam/libraries/RF24/tests/native/pingpair_irq.pde
new file mode 100644
index 0000000..99c2cdf
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/native/pingpair_irq.pde
@@ -0,0 +1,223 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Interrupt-driven test for native target
+ *
+ * This example is the friendliest for the native target because it doesn't do
+ * any polling.  Made a slight change to call done() at the end of setup.
+ */
+
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+#include "printf.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 8 & 9
+
+RF24 radio(8,9);
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'ping' transmitter
+const short role_pin = 7;
+
+//
+// Topology
+//
+
+// Single radio pipe address for the 2 nodes to communicate.
+const uint64_t pipe = 0xE8E8F0F0E1LL;
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes in this
+// system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_sender = 1, role_receiver } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Sender", "Receiver"};
+
+// The role of the current running sketch
+role_e role;
+
+// Interrupt handler, check the radio because we got an IRQ
+void check_radio(void);
+
+void setup(void)
+{
+  //
+  // Role
+  //
+
+  // set up the role pin
+  pinMode(role_pin, INPUT);
+  digitalWrite(role_pin,HIGH);
+  delay(20); // Just to get a solid reading on the role pin
+
+  // read the address pin, establish our role
+  if ( digitalRead(role_pin) )
+    role = role_sender;
+  else
+    role = role_receiver;
+
+  //
+  // Print preamble
+  //
+
+  Serial.begin(57600);
+  printf_begin();
+  printf("\n\rRF24/examples/pingpair_irq/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  // We will be using the Ack Payload feature, so please enable it
+  radio.enableAckPayload();
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens a single pipe for these two nodes to communicate
+  // back and forth.  One listens on it, the other talks to it.
+
+  if ( role == role_sender )
+  {
+    radio.openWritingPipe(pipe);
+  }
+  else
+  {
+    radio.openReadingPipe(1,pipe);
+  }
+
+  //
+  // Start listening
+  //
+
+  if ( role == role_receiver )
+    radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+
+  //
+  // Attach interrupt handler to interrupt #0 (using pin 2)
+  // on BOTH the sender and receiver
+  //
+
+  attachInterrupt(0, check_radio, FALLING);
+
+  //
+  // On the native target, this is as far as we get
+  //
+#if NATIVE
+  done();
+#endif
+}
+
+static uint32_t message_count = 0;
+
+void loop(void)
+{
+  //
+  // Sender role.  Repeatedly send the current time
+  //
+
+  if (role == role_sender)
+  {
+    // Take the time, and send it.
+    unsigned long time = millis();
+    printf("Now sending %lu\n\r",time);
+    radio.startWrite( &time, sizeof(unsigned long) );
+
+    // Try again soon
+    delay(2000);
+  }
+
+  //
+  // Receiver role: Does nothing!  All the work is in IRQ
+  //
+
+}
+
+void check_radio(void)
+{
+  // What happened?
+  bool tx,fail,rx;
+  radio.whatHappened(tx,fail,rx);
+
+  // Have we successfully transmitted?
+  if ( tx )
+  {
+    if ( role == role_sender )
+      printf("Send:OK\n\r");
+
+    if ( role == role_receiver )
+      printf("Ack Payload:Sent\n\r");
+  }
+
+  // Have we failed to transmit?
+  if ( fail )
+  {
+    if ( role == role_sender )
+      printf("Send:Failed\n\r");
+
+    if ( role == role_receiver )
+      printf("Ack Payload:Failed\n\r");
+  }
+
+  // Transmitter can power down for now, because
+  // the transmission is done.
+  if ( ( tx || fail ) && ( role == role_sender ) )
+    radio.powerDown();
+
+  // Did we receive a message?
+  if ( rx )
+  {
+    // If we're the sender, we've received an ack payload
+    if ( role == role_sender )
+    {
+      radio.read(&message_count,sizeof(message_count));
+      printf("Ack:%lu\n\r",(unsigned long)message_count);
+    }
+
+    // If we're the receiver, we've received a time message
+    if ( role == role_receiver )
+    {
+      // Get this payload and dump it
+      static unsigned long got_time;
+      radio.read( &got_time, sizeof(got_time) );
+      printf("Got payload %lu\n\r",got_time);
+
+      // Add an ack packet for the next time around.  This is a simple
+      // packet counter
+      radio.writeAckPayload( 1, &message_count, sizeof(message_count) );
+      ++message_count;
+    }
+  }
+}
+
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/tests/native/printf.h b/hardware/digistump/sam/libraries/RF24/tests/native/printf.h
new file mode 100644
index 0000000..df6c46a
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/native/printf.h
@@ -0,0 +1,33 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#include "WProgram.h"
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  fdevopen( &serial_putc, 0 );
+}
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/Jamfile b/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/Jamfile
new file mode 100644
index 0000000..18244ec
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/Jamfile
@@ -0,0 +1,219 @@
+# (1) Project Information
+
+PROJECT_LIBS 	= SPI RF24 ; 
+PROJECT_DIRS	= $(PWD) ;
+
+# (2) Board Information
+
+UPLOAD_PROTOCOL ?= arduino ;
+UPLOAD_SPEED 	?= 115200 ;
+MCU		?= atmega328p ;
+F_CPU 		?= 16000000 ;
+CORE		?= arduino ;
+VARIANT 	?= standard ;
+ARDUINO_VERSION	?= 100 ;
+
+# (3) USB Ports
+
+PORTS		= p4 p6 p9 u0 u1 u2 ;
+PORT_p6 	= /dev/tty.usbserial-A600eHIs ;
+PORT_p4 	= /dev/tty.usbserial-A40081RP ;
+PORT_p9		= /dev/tty.usbserial-A9007LmI ;
+PORT_u0 	= /dev/ttyUSB0 ;
+PORT_u1 	= /dev/ttyUSB1 ;
+PORT_u2 	= /dev/ttyUSB2 ;
+
+# (4) Location of AVR tools
+#
+# This configuration assumes using avr-tools that were obtained separate from the Arduino
+# distribution. 
+
+if $(OS) = MACOSX 
+{
+	AVR_BIN 	?= /usr/local/avrtools/bin ;
+	AVR_ETC 	= /usr/local/avrtools/etc ;
+	AVR_INCLUDE	= /usr/local/avrtools/include ; 
+}
+else
+{
+	AVR_BIN 	?= /usr/bin ;
+	AVR_INCLUDE 	= /usr/lib/avr/include ;
+	AVR_ETC 	= /etc ; 
+}
+
+# (5) Directories where Arduino core and libraries are located
+
+ARDUINO_DIR 	?= /opt/Arduino ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+
+#
+# --------------------------------------------------
+# Below this line usually never needs to be modified 
+#
+
+# Tool locations
+
+CC	  	= $(AVR_BIN)/avr-gcc ;
+C++	 	= $(AVR_BIN)/avr-g++ ;
+LINK	  	= $(AVR_BIN)/avr-gcc ;
+AR		= $(AVR_BIN)/avr-ar rcs ;
+RANLIB		= ;
+OBJCOPY 	= $(AVR_BIN)/avr-objcopy ;
+AVRDUDE 	?= $(AVR_BIN)/avrdude ;
+
+# Flags
+
+DEFINES  	+= F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+OPTIM		= -Os ;
+CCFLAGS  	= -Wall -Wextra -Wno-strict-aliasing -mmcu=$(MCU) -ffunction-sections -fdata-sections ;
+C++FLAGS  	= $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ;
+LINKFLAGS  	= $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ;
+AVRDUDEFLAGS	= -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ;
+
+# Search everywhere for headers
+
+HDRS  	 	= $(PROJECT_DIRS) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ;
+
+# Output locations
+
+LOCATE_TARGET	= $(F_CPU) ;
+LOCATE_SOURCE	= $(F_CPU) ;
+
+#
+# Custom rules
+#
+
+rule GitVersion
+{
+	Always $(<) ;
+	Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+	echo "const char program_version[] = \"\\" > $(<)
+	git log -1 --pretty=format:%h >> $(<)
+	echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule Pde
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+if ( $(ARDUINO_VERSION) < 100 )
+{
+	ARDUINO_H = WProgram.h ;
+}
+else
+{
+	ARDUINO_H = Arduino.h ;
+}
+
+actions Pde
+{
+	echo "#include <$(ARDUINO_H)>" > $(<) 
+	echo "#line 1 \"$(>)\"" >> $(<)
+	cat $(>) >> $(<) 
+}
+
+rule C++Pde
+{
+	local _CPP = $(>:B).cpp ;
+	Pde $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule UserObject
+{
+	switch $(>:S)
+	{
+		case .ino : C++Pde $(<) : $(>) ;
+		case .pde : C++Pde $(<) : $(>) ;
+	}
+}
+
+rule Objects
+{
+        local _i ;
+
+        for _i in [ FGristFiles $(<) ]
+        {
+		local _b = $(_i:B)$(SUFOBJ) ;
+		local _o = $(_b:G=$(SOURCE_GRIST:E)) ;
+                Object $(_o) : $(_i) ;
+                Depends obj : $(_o) ;
+        }
+}
+
+rule Library
+{
+	LibraryFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+	Objects $(>) ;
+}
+
+rule Main
+{
+        MainFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+        Objects $(>) ;
+}
+
+rule Hex
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends hex : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Hex
+{
+	$(OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule Upload
+{
+	Depends $(1) : $(2) ;
+	Depends $(2) : $(3) ;
+	NotFile $(1) ;
+	Always $(1) ;
+	Always $(2) ;
+	UploadAction $(2) : $(3) ;
+}
+
+actions UploadAction
+{
+	$(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+rule Arduino
+{
+	LINKFLAGS on $(<) = $(LINKFLAGS) -Wl,-Map=$(LOCATE_TARGET)/$(<:B).map ;
+	Main $(<) : $(>) ;
+	LinkLibraries $(<) : core libs ;
+	Hex $(<:B).hex : $(<) ;
+	for _p in $(PORTS)
+	{
+		Upload $(_p) : $(PORT_$(_p)) : $(<:B).hex ;
+	}
+}
+
+#
+# Targets
+#
+
+# Grab everything from the core directory
+Library core : [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+Library libs : [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ;
+
+# Main output executable
+Arduino $(PWD:B).elf : $(PROJECT_MODULES) [ GLOB $(PROJECT_DIRS) : *.c *.cpp *.pde *.ino ] ;
diff --git a/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/pingpair_blocking.pde b/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/pingpair_blocking.pde
new file mode 100644
index 0000000..1501d37
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/pingpair_blocking.pde
@@ -0,0 +1,273 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+#include "printf.h"
+
+//
+// Test version of RF24, exposes some protected interface
+//
+
+class RF24Test: public RF24
+{
+public: RF24Test(int a, int b): RF24(a,b) {}
+};
+
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 8 & 9
+
+RF24Test radio(8,9);
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'ping' transmitter
+const int role_pin = 7;
+
+//
+// Topology
+//
+
+// Radio pipe addresses for the 2 nodes to communicate.
+const uint64_t pipes[2] = { 0xF0F0F0F0E1LL, 0xF0F0F0F0D2LL };
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes
+// in this system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_ping_out = 1, role_pong_back } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Ping out", "Pong back"};
+
+// The role of the current running sketch
+role_e role;
+
+//
+// Test state
+//
+
+bool done; //*< Are we done with the test? */
+bool passed; //*< Have we passed the test? */
+bool notified; //*< Have we notified the user we're done? */
+const int num_needed = 10; //*< How many success/failures until we're done? */
+int receives_remaining = num_needed; //*< How many ack packets until we declare victory? */
+int failures_remaining = num_needed; //*< How many more failed sends until we declare failure? */
+const int interval = 100; //*< ms to wait between sends */
+
+char configuration = '1'; //*< Configuration key, one char sent in by the test framework to tell us how to configure, this is the default */
+
+void one_ok(void)
+{
+  // Have we received enough yet?
+  if ( ! --receives_remaining )
+  {
+    done = true;
+    passed = true;
+  }
+}
+
+void one_failed(void)
+{
+  // Have we failed enough yet?
+  if ( ! --failures_remaining )
+  {
+    done = true;
+    passed = false;
+  }
+}
+
+void setup(void)
+{
+  //
+  // Role
+  //
+
+  // set up the role pin
+  pinMode(role_pin, INPUT);
+  digitalWrite(role_pin,HIGH);
+  delay(20); // Just to get a solid reading on the role pin
+
+  // read the address pin, establish our role
+  if ( digitalRead(role_pin) )
+    role = role_ping_out;
+  else
+    role = role_pong_back;
+
+  //
+  // Print preamble
+  //
+
+  Serial.begin(57600);
+  printf_begin();
+  printf("\n\rRF24/tests/pingpair_blocking/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+
+  //
+  // get test config
+  //
+
+  printf("+READY press any key to start\n\r\n\r");
+
+  while (! Serial.available() ) {}
+  configuration = Serial.read();
+  printf("Configuration\t = %c\n\r",configuration);
+   
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens two pipes for these two nodes to communicate
+  // back and forth.
+  // Open 'our' pipe for writing
+  // Open the 'other' pipe for reading, in position #1 (we can have up to 5 pipes open for reading)
+
+  if ( role == role_ping_out )
+  {
+    radio.openWritingPipe(pipes[0]);
+    radio.openReadingPipe(1,pipes[1]);
+  }
+  else
+  {
+    radio.openWritingPipe(pipes[1]);
+    radio.openReadingPipe(1,pipes[0]);
+  }
+
+  //
+  // Start listening
+  //
+
+  radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+  
+  if ( role == role_pong_back )
+    printf("\n\r+OK ");
+}
+
+void loop(void)
+{
+  //
+  // Ping out role.  Repeatedly send the current time
+  //
+
+  if (role == role_ping_out)
+  {
+    // First, stop listening so we can talk.
+    radio.stopListening();
+
+    // Take the time, and send it.  This will block until complete
+    unsigned long time = millis();
+    printf("Now sending %lu...",time);
+    radio.write( &time, sizeof(unsigned long) );
+
+    // Now, continue listening
+    radio.startListening();
+
+    // Wait here until we get a response, or timeout (250ms)
+    unsigned long started_waiting_at = millis();
+    bool timeout = false;
+    while ( ! radio.available() && ! timeout )
+      if (millis() - started_waiting_at > 200 )
+        timeout = true;
+
+    // Describe the results
+    if ( timeout )
+    {
+      printf("Failed, response timed out.\n\r");
+      one_failed();
+    }
+    else
+    {
+      // Grab the response, compare, and send to debugging spew
+      unsigned long got_time;
+      radio.read( &got_time, sizeof(unsigned long) );
+
+      // Spew it
+      printf("Got response %lu, round-trip delay: %lu\n\r",got_time,millis()-got_time);
+      one_ok();
+    }
+
+    // Try again  later
+    delay(250);
+  }
+
+  //
+  // Pong back role.  Receive each packet, dump it out, and send it back
+  //
+
+  if ( role == role_pong_back )
+  {
+    // if there is data ready
+    if ( radio.available() )
+    {
+      // Dump the payloads until we've gotten everything
+      unsigned long got_time;
+      bool done = false;
+      while (!done)
+      {
+        // Fetch the payload, and see if this was the last one.
+        done = radio.read( &got_time, sizeof(unsigned long) );
+
+        // Spew it
+        printf("Got payload %lu...",got_time);
+
+	// Delay just a little bit to let the other unit
+	// make the transition to receiver
+	delay(20);
+      }
+
+      // First, stop listening so we can talk
+      radio.stopListening();
+
+      // Send the final one back.
+      radio.write( &got_time, sizeof(unsigned long) );
+      printf("Sent response.\n\r");
+
+      // Now, resume listening so we catch the next packets.
+      radio.startListening();
+
+    }
+  }
+  
+  //
+  // Stop the test if we're done and report results
+  //
+  if ( done && ! notified )
+  {
+    notified = true;
+
+    printf("\n\r+OK ");
+    if ( passed )
+      printf("PASS\n\r\n\r");
+    else
+      printf("FAIL\n\r\n\r");
+  }
+}
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/printf.h b/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/printf.h
new file mode 100644
index 0000000..b2efd56
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/printf.h
@@ -0,0 +1,37 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  fdevopen( &serial_putc, 0 );
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/runtest.py b/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/runtest.py
new file mode 100644
index 0000000..0772f95
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/runtest.py
@@ -0,0 +1,25 @@
+#!/usr/bin/python
+
+import sys,serial
+
+def read_until(token):
+	while 1: 
+		line = ser.readline(None)
+		sys.stdout.write(line)
+
+		if (line.startswith(token)):
+			break
+	return line
+
+
+ser = serial.Serial(sys.argv[1], 57600, timeout=5, dsrdtr=False, rtscts=False)
+
+read_until("+READY")
+ser.write(sys.argv[2])
+
+line = read_until("+OK")
+ser.close()
+if (line.find("PASS") != -1):
+	sys.exit(0)
+else:
+	sys.exit(1)
diff --git a/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/runtests.sh b/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/runtests.sh
new file mode 100644
index 0000000..e106448
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/runtests.sh
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+# Connect u0 to receiver, u1 to sender
+
+jam u0 u1 && expect test.ex 
diff --git a/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/test.ex b/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/test.ex
new file mode 100644
index 0000000..ea992ad
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/pingpair_blocking/test.ex
@@ -0,0 +1,11 @@
+#/usr/bin/expect
+
+set timeout 100
+spawn picocom -b 57600 /dev/ttyUSB0
+expect "+READY"
+send "1"
+expect "+OK"
+spawn picocom -b 57600 /dev/ttyUSB1
+expect "+READY"
+send "1"
+expect "+OK"
diff --git a/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/Jamfile b/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/Jamfile
new file mode 100644
index 0000000..18244ec
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/Jamfile
@@ -0,0 +1,219 @@
+# (1) Project Information
+
+PROJECT_LIBS 	= SPI RF24 ; 
+PROJECT_DIRS	= $(PWD) ;
+
+# (2) Board Information
+
+UPLOAD_PROTOCOL ?= arduino ;
+UPLOAD_SPEED 	?= 115200 ;
+MCU		?= atmega328p ;
+F_CPU 		?= 16000000 ;
+CORE		?= arduino ;
+VARIANT 	?= standard ;
+ARDUINO_VERSION	?= 100 ;
+
+# (3) USB Ports
+
+PORTS		= p4 p6 p9 u0 u1 u2 ;
+PORT_p6 	= /dev/tty.usbserial-A600eHIs ;
+PORT_p4 	= /dev/tty.usbserial-A40081RP ;
+PORT_p9		= /dev/tty.usbserial-A9007LmI ;
+PORT_u0 	= /dev/ttyUSB0 ;
+PORT_u1 	= /dev/ttyUSB1 ;
+PORT_u2 	= /dev/ttyUSB2 ;
+
+# (4) Location of AVR tools
+#
+# This configuration assumes using avr-tools that were obtained separate from the Arduino
+# distribution. 
+
+if $(OS) = MACOSX 
+{
+	AVR_BIN 	?= /usr/local/avrtools/bin ;
+	AVR_ETC 	= /usr/local/avrtools/etc ;
+	AVR_INCLUDE	= /usr/local/avrtools/include ; 
+}
+else
+{
+	AVR_BIN 	?= /usr/bin ;
+	AVR_INCLUDE 	= /usr/lib/avr/include ;
+	AVR_ETC 	= /etc ; 
+}
+
+# (5) Directories where Arduino core and libraries are located
+
+ARDUINO_DIR 	?= /opt/Arduino ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+
+#
+# --------------------------------------------------
+# Below this line usually never needs to be modified 
+#
+
+# Tool locations
+
+CC	  	= $(AVR_BIN)/avr-gcc ;
+C++	 	= $(AVR_BIN)/avr-g++ ;
+LINK	  	= $(AVR_BIN)/avr-gcc ;
+AR		= $(AVR_BIN)/avr-ar rcs ;
+RANLIB		= ;
+OBJCOPY 	= $(AVR_BIN)/avr-objcopy ;
+AVRDUDE 	?= $(AVR_BIN)/avrdude ;
+
+# Flags
+
+DEFINES  	+= F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+OPTIM		= -Os ;
+CCFLAGS  	= -Wall -Wextra -Wno-strict-aliasing -mmcu=$(MCU) -ffunction-sections -fdata-sections ;
+C++FLAGS  	= $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ;
+LINKFLAGS  	= $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ;
+AVRDUDEFLAGS	= -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ;
+
+# Search everywhere for headers
+
+HDRS  	 	= $(PROJECT_DIRS) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ;
+
+# Output locations
+
+LOCATE_TARGET	= $(F_CPU) ;
+LOCATE_SOURCE	= $(F_CPU) ;
+
+#
+# Custom rules
+#
+
+rule GitVersion
+{
+	Always $(<) ;
+	Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+	echo "const char program_version[] = \"\\" > $(<)
+	git log -1 --pretty=format:%h >> $(<)
+	echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule Pde
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+if ( $(ARDUINO_VERSION) < 100 )
+{
+	ARDUINO_H = WProgram.h ;
+}
+else
+{
+	ARDUINO_H = Arduino.h ;
+}
+
+actions Pde
+{
+	echo "#include <$(ARDUINO_H)>" > $(<) 
+	echo "#line 1 \"$(>)\"" >> $(<)
+	cat $(>) >> $(<) 
+}
+
+rule C++Pde
+{
+	local _CPP = $(>:B).cpp ;
+	Pde $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule UserObject
+{
+	switch $(>:S)
+	{
+		case .ino : C++Pde $(<) : $(>) ;
+		case .pde : C++Pde $(<) : $(>) ;
+	}
+}
+
+rule Objects
+{
+        local _i ;
+
+        for _i in [ FGristFiles $(<) ]
+        {
+		local _b = $(_i:B)$(SUFOBJ) ;
+		local _o = $(_b:G=$(SOURCE_GRIST:E)) ;
+                Object $(_o) : $(_i) ;
+                Depends obj : $(_o) ;
+        }
+}
+
+rule Library
+{
+	LibraryFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+	Objects $(>) ;
+}
+
+rule Main
+{
+        MainFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+        Objects $(>) ;
+}
+
+rule Hex
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends hex : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Hex
+{
+	$(OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule Upload
+{
+	Depends $(1) : $(2) ;
+	Depends $(2) : $(3) ;
+	NotFile $(1) ;
+	Always $(1) ;
+	Always $(2) ;
+	UploadAction $(2) : $(3) ;
+}
+
+actions UploadAction
+{
+	$(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+rule Arduino
+{
+	LINKFLAGS on $(<) = $(LINKFLAGS) -Wl,-Map=$(LOCATE_TARGET)/$(<:B).map ;
+	Main $(<) : $(>) ;
+	LinkLibraries $(<) : core libs ;
+	Hex $(<:B).hex : $(<) ;
+	for _p in $(PORTS)
+	{
+		Upload $(_p) : $(PORT_$(_p)) : $(<:B).hex ;
+	}
+}
+
+#
+# Targets
+#
+
+# Grab everything from the core directory
+Library core : [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+Library libs : [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ;
+
+# Main output executable
+Arduino $(PWD:B).elf : $(PROJECT_MODULES) [ GLOB $(PROJECT_DIRS) : *.c *.cpp *.pde *.ino ] ;
diff --git a/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/pingpair_test.pde b/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/pingpair_test.pde
new file mode 100644
index 0000000..6acbf51
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/pingpair_test.pde
@@ -0,0 +1,435 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Full test on single RF pair
+ *
+ * This sketches uses as many RF24 methods as possible in a single test.
+ *
+ * To operate:
+ *  Upload this sketch on two nodes, each with IRQ -> pin 2
+ *  One node needs pin 7 -> GND, the other NC.  That's the receiving node
+ *  Monitor the sending node's serial output
+ *  Look for "+OK PASS" or "+OK FAIL"
+ */
+
+#include 
+#include "nRF24L01.h"
+#include "RF24.h"
+#include "printf.h"
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 8 & 9
+
+RF24 radio(8,9);
+
+// sets the role of this unit in hardware.  Connect to GND to be the 'pong' receiver
+// Leave open to be the 'ping' transmitter
+const short role_pin = 7;
+
+//
+// Topology
+//
+
+// Single radio pipe address for the 2 nodes to communicate.
+const uint64_t pipe = 0xE8E8F0F0E1LL;
+
+//
+// Role management
+//
+// Set up role.  This sketch uses the same software for all the nodes in this
+// system.  Doing so greatly simplifies testing.  The hardware itself specifies
+// which node it is.
+//
+// This is done through the role_pin
+//
+
+// The various roles supported by this sketch
+typedef enum { role_sender = 1, role_receiver } role_e;
+
+// The debug-friendly names of those roles
+const char* role_friendly_name[] = { "invalid", "Sender", "Receiver"};
+
+// The role of the current running sketch
+role_e role;
+
+// Interrupt handler, check the radio because we got an IRQ
+void check_radio(void);
+
+//
+// Payload
+//
+
+const int min_payload_size = 4;
+const int max_payload_size = 32;
+int payload_size_increments_by = 2;
+int next_payload_size = min_payload_size;
+
+char receive_payload[max_payload_size+1]; // +1 to allow room for a terminating NULL char
+
+//
+// Test state
+//
+
+bool done; //*< Are we done with the test? */
+bool passed; //*< Have we passed the test? */
+bool notified; //*< Have we notified the user we're done? */
+const int num_needed = 10; //*< How many success/failures until we're done? */
+int receives_remaining = num_needed; //*< How many ack packets until we declare victory? */
+int failures_remaining = num_needed; //*< How many more failed sends until we declare failure? */
+const int interval = 100; //*< ms to wait between sends */
+
+char configuration = '1'; //*< Configuration key, one char sent in by the test framework to tell us how to configure, this is the default */
+
+uint8_t pipe_number = 1; // Which pipe to send on.
+
+void one_ok(void)
+{
+  // Have we received enough yet?
+  if ( ! --receives_remaining )
+  {
+    done = true;
+    passed = true;
+  }
+}
+
+void one_failed(void)
+{
+  // Have we failed enough yet?
+  if ( ! --failures_remaining )
+  {
+    done = true;
+    passed = false;
+  }
+}
+
+//
+// Setup 
+//
+
+void setup(void)
+{
+  //
+  // Role
+  //
+
+  // set up the role pin
+  pinMode(role_pin, INPUT);
+  digitalWrite(role_pin,HIGH);
+  delay(20); // Just to get a solid reading on the role pin
+
+  // read the address pin, establish our role
+  if ( digitalRead(role_pin) )
+    role = role_sender;
+  else
+    role = role_receiver;
+
+  //
+  // Print preamble
+  //
+
+  Serial.begin(57600);
+  printf_begin();
+  printf("\n\rRF24/tests/pingpair_test/\n\r");
+  printf("ROLE: %s\n\r",role_friendly_name[role]);
+
+  //
+  // Read configuration from serial
+  //
+  // It would be a much better test if this program could accept configuration
+  // from the serial port.  Then it would be possible to run the same test under
+  // lots of different circumstances.
+  //
+  // The idea is that we will print "+READY" at this point.  The python script
+  // will wait for it, and then send down a configuration script that we
+  // execute here and then run with.
+  //
+  // The test controller will need to configure the receiver first, then go run
+  // the test on the sender.
+  //
+
+  printf("+READY press any key to start\n\r\n\r");
+
+  while (! Serial.available() ) {}
+  configuration = Serial.read();
+  printf("Configuration\t = %c\n\r",configuration);
+
+  //
+  // Setup and configure rf radio
+  //
+
+  radio.begin();
+
+  // We will be using the Ack Payload feature, so please enable it
+  radio.enableAckPayload();
+
+  // Config 2 is special radio config
+  if (configuration=='2')
+  {
+    radio.setCRCLength(RF24_CRC_8);
+    radio.setDataRate(RF24_250KBPS);
+    radio.setChannel(10);
+  }
+  else
+  {
+    //Otherwise, default radio config
+    
+    // Optional: Increase CRC length for improved reliability
+    radio.setCRCLength(RF24_CRC_16);
+
+    // Optional: Decrease data rate for improved reliability
+    radio.setDataRate(RF24_1MBPS);
+
+    // Optional: Pick a high channel
+    radio.setChannel(90);
+  }
+
+  // Config 3 is static payloads only
+  if (configuration == '3')
+  {
+    next_payload_size = 16;
+    payload_size_increments_by = 0;
+    radio.setPayloadSize(next_payload_size);
+  }
+  else
+  {
+    // enable dynamic payloads
+    radio.enableDynamicPayloads();
+  }
+
+  // Config 4 tests out a higher pipe ##
+  if (configuration == '4' && role == role_sender)
+  {
+    // Set top 4 bytes of the address in pipe 1 
+    radio.openReadingPipe(1,pipe & 0xFFFFFFFF00ULL);
+
+    // indicate the pipe to use 
+    pipe_number = 5;
+  }
+  else if ( role == role_sender )
+  {
+    radio.openReadingPipe(5,0);
+  }
+
+  //
+  // Open pipes to other nodes for communication
+  //
+
+  // This simple sketch opens a single pipe for these two nodes to communicate
+  // back and forth.  One listens on it, the other talks to it.
+
+  if ( role == role_sender )
+  {
+    radio.openWritingPipe(pipe);
+  }
+  else
+  {
+    radio.openReadingPipe(pipe_number,pipe);
+  }
+
+  //
+  // Start listening
+  //
+
+  if ( role == role_receiver )
+    radio.startListening();
+
+  //
+  // Dump the configuration of the rf unit for debugging
+  //
+
+  radio.printDetails();
+
+  //
+  // Attach interrupt handler to interrupt #0 (using pin 2)
+  // on BOTH the sender and receiver
+  //
+
+  attachInterrupt(0, check_radio, FALLING);
+  
+  if ( role == role_receiver )
+    printf("\n\r+OK ");
+}
+
+//
+// Print buffer
+//
+// Printing from the interrupt handler is a bad idea, so we print from there
+// to this intermediate buffer
+//
+
+char prbuf[1000];
+char *prbuf_end = prbuf + sizeof(prbuf);
+char *prbuf_in = prbuf;
+char *prbuf_out = prbuf;
+
+//
+// Loop 
+//
+
+static uint32_t message_count = 0;
+static uint32_t last_message_count = 0;
+
+void loop(void)
+{
+  //
+  // Sender role.  Repeatedly send the current time
+  //
+
+  if (role == role_sender && !done)
+  {
+    // The payload will always be the same, what will change is how much of it we send.
+    static char send_payload[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ789012";
+
+    // First, stop listening so we can talk.
+    radio.stopListening();
+
+    // Send it.  This will block until complete
+    printf("\n\rNow sending length %i...",next_payload_size);
+    radio.startWrite( send_payload, next_payload_size );
+
+    // Update size for next time.
+    next_payload_size += payload_size_increments_by;
+    if ( next_payload_size > max_payload_size )
+      next_payload_size = min_payload_size;
+    
+    // Try again soon
+    delay(interval);
+    
+    // Timeout if we have not received anything back ever
+    if ( ! last_message_count && millis() > interval * 100 )
+    {
+      printf("No responses received.  Are interrupts connected??\n\r");
+      done = true;
+    }
+  }
+
+  //
+  // Receiver role: Does nothing!  All the work is in IRQ
+  //
+  
+  //
+  // Spew print buffer
+  //
+
+  size_t write_length = prbuf_in - prbuf_out;
+  if ( write_length )
+  {
+    Serial.write(reinterpret_cast(prbuf_out),write_length);
+    prbuf_out += write_length;
+  }
+  
+  //
+  // Stop the test if we're done and report results
+  //
+  if ( done && ! notified )
+  {
+    notified = true;
+
+    printf("\n\r+OK ");
+    if ( passed )
+      printf("PASS\n\r\n\r");
+    else
+      printf("FAIL\n\r\n\r");
+  }
+
+}
+
+void check_radio(void)
+{
+  // What happened?
+  bool tx,fail,rx;
+  radio.whatHappened(tx,fail,rx);
+
+  // Have we successfully transmitted?
+  if ( tx )
+  {
+    if ( role == role_sender )
+      prbuf_in += sprintf(prbuf_in,"Send:OK ");
+
+    if ( role == role_receiver )
+      prbuf_in += sprintf(prbuf_in,"Ack Payload:Sent\n\r");
+  }
+
+  // Have we failed to transmit?
+  if ( fail )
+  {
+    if ( role == role_sender )
+    {
+      prbuf_in += sprintf(prbuf_in,"Send:Failed ");
+
+      // log status of this line
+      one_failed();
+    }
+
+    if ( role == role_receiver )
+      prbuf_in += sprintf(prbuf_in,"Ack Payload:Failed\n\r");
+  }
+
+  // Transmitter can power down for now, because
+  // the transmission is done.
+  if ( ( tx || fail ) && ( role == role_sender ) )
+    radio.powerDown();
+
+  // Did we receive a message?
+  if ( rx )
+  {
+    // If we're the sender, we've received an ack payload
+    if ( role == role_sender )
+    {
+      radio.read(&message_count,sizeof(message_count));
+      prbuf_in += sprintf(prbuf_in,"Ack:%lu ",message_count);
+     
+      // is this ack what we were expecting?  to account
+      // for failures, we simply want to make sure we get a
+      // DIFFERENT ack every time.
+      if ( ( message_count != last_message_count ) || ( configuration=='3' && message_count == 16 ) )
+      {
+	prbuf_in += sprintf(prbuf_in,"OK ");
+	one_ok();
+      }
+      else
+      {
+	prbuf_in += sprintf(prbuf_in,"FAILED ");
+	one_failed();
+      }
+      last_message_count = message_count;
+    }
+
+    // If we're the receiver, we've received a time message
+    if ( role == role_receiver )
+    {
+      // Get this payload and dump it
+      size_t len = max_payload_size;
+      memset(receive_payload,0,max_payload_size);
+      
+      if ( configuration == '3' )
+	len = next_payload_size;
+      else
+	len = radio.getDynamicPayloadSize();
+      
+      radio.read( receive_payload, len );
+      
+      // Put a zero at the end for easy printing
+      receive_payload[len] = 0;
+
+      // Spew it
+      prbuf_in += sprintf(prbuf_in,"Recv size=%i val=%s len=%u\n\r",len,receive_payload,strlen(receive_payload));
+
+      // Add an ack packet for the next time around.
+      // Here we will report back how many bytes we got this time.
+      radio.writeAckPayload( pipe_number, &len, sizeof(len) );
+      ++message_count;
+    }
+  }
+}
+
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/printf.h b/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/printf.h
new file mode 100644
index 0000000..b2efd56
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/printf.h
@@ -0,0 +1,37 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  fdevopen( &serial_putc, 0 );
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/runtest.py b/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/runtest.py
new file mode 100644
index 0000000..45fb65c
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/runtest.py
@@ -0,0 +1,25 @@
+#!/opt/local/bin/python
+
+import sys,serial
+
+def read_until(token):
+	while 1: 
+		line = ser.readline(None,"\r")
+		sys.stdout.write(line)
+
+		if (line.startswith(token)):
+			break
+	return line
+
+
+ser = serial.Serial(sys.argv[1], 57600, timeout=5, dsrdtr=False, rtscts=False)
+
+read_until("+READY")
+ser.write(sys.argv[2])
+
+line = read_until("+OK")
+ser.close()
+if (line.find("PASS") != -1):
+	sys.exit(0)
+else:
+	sys.exit(1)
diff --git a/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/runtests.sh b/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/runtests.sh
new file mode 100644
index 0000000..4d02310
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/runtests.sh
@@ -0,0 +1,21 @@
+#!/bin/sh
+
+# Connect u0 to receiver, u0 to sender
+# WARNING: Test config 2 only works with PLUS units.
+
+jam u0 u1 && expect test.ex 1
+sleep 1
+stty 57600 raw ignbrk hup < /dev/ttyUSB0
+sleep 1
+stty 57600 raw ignbrk hup < /dev/ttyUSB1
+expect test.ex 2
+sleep 1
+stty 57600 raw ignbrk hup < /dev/ttyUSB0
+sleep 1
+stty 57600 raw ignbrk hup < /dev/ttyUSB1
+expect test.ex 3
+sleep 1
+stty 57600 raw ignbrk hup < /dev/ttyUSB0
+sleep 1
+stty 57600 raw ignbrk hup < /dev/ttyUSB1
+expect test.ex 4
diff --git a/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/test.ex b/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/test.ex
new file mode 100644
index 0000000..a14ffef
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/tests/pingpair_test/test.ex
@@ -0,0 +1,11 @@
+#/usr/bin/expect
+
+set timeout 100
+spawn picocom -b 57600 /dev/ttyUSB0
+expect "+READY"
+send [lindex $argv 0] 
+expect "+OK"
+spawn picocom -b 57600 /dev/ttyUSB1
+expect "+READY"
+send [lindex $argv 0]
+expect "+OK"
diff --git a/hardware/digistump/sam/libraries/RF24/wikidoc.xslt b/hardware/digistump/sam/libraries/RF24/wikidoc.xslt
new file mode 100644
index 0000000..b94d3ef
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24/wikidoc.xslt
@@ -0,0 +1,41 @@
+
+  
+  
+    	
+  
+  
+  		
+  		
===  ===


+  		
+  		

+  		
+  
+  '''' 
+  
+Parameters:
+
+
+  
+  * '''': 

+  
+  
+  	

+  
+  
+Returns:
+
+* 

+  
+  
+Warning: 

+
+  
+  
+  	
<pre>
</pre>

+  
+  
+  	

+  
+  
+
+
diff --git a/hardware/digistump/sam/libraries/RF24Network/.gitignore b/hardware/digistump/sam/libraries/RF24Network/.gitignore
new file mode 100644
index 0000000..d0d1cc9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/.gitignore
@@ -0,0 +1,4 @@
+version.h
+output/
+ojam/
+.*.swp
diff --git a/hardware/digistump/sam/libraries/RF24Network/Doxyfile b/hardware/digistump/sam/libraries/RF24Network/Doxyfile
new file mode 100644
index 0000000..0ed1867
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/Doxyfile
@@ -0,0 +1,1551 @@
+# Doxyfile 1.6.3
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project
+#
+# All text after a hash (#) is considered a comment and will be ignored
+# The format is:
+#       TAG = value [value, ...]
+# For lists items can also be appended using:
+#       TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (" ")
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the config file
+# that follow. The default is UTF-8 which is also the encoding used for all
+# text before the first occurrence of this tag. Doxygen uses libiconv (or the
+# iconv built into libc) for the transcoding. See
+# http://www.gnu.org/software/libiconv for the list of possible encodings.
+
+DOXYFILE_ENCODING      = UTF-8
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded
+# by quotes) that should identify the project.
+
+PROJECT_NAME           = RF24Network 
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number.
+# This could be handy for archiving the generated documentation or
+# if some version control system is used.
+
+PROJECT_NUMBER         = v1
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
+# base path where the generated documentation will be put.
+# If a relative path is entered, it will be relative to the location
+# where doxygen was started. If left blank the current directory will be used.
+
+OUTPUT_DIRECTORY       = docs
+
+# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create
+# 4096 sub-directories (in 2 levels) under the output directory of each output
+# format and will distribute the generated files over these directories.
+# Enabling this option can be useful when feeding doxygen a huge amount of
+# source files, where putting all generated files in the same directory would
+# otherwise cause performance problems for the file system.
+
+CREATE_SUBDIRS         = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# The default language is English, other supported languages are:
+# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional,
+# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,
+# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English
+# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,
+# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak,
+# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
+
+OUTPUT_LANGUAGE        = English
+
+# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will
+# include brief member descriptions after the members that are listed in
+# the file and class documentation (similar to JavaDoc).
+# Set to NO to disable this.
+
+BRIEF_MEMBER_DESC      = YES
+
+# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend
+# the brief description of a member or function before the detailed description.
+# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+
+REPEAT_BRIEF           = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator
+# that is used to form the text in various listings. Each string
+# in this list, if found as the leading text of the brief description, will be
+# stripped from the text and the result after processing the whole list, is
+# used as the annotated text. Otherwise, the brief description is used as-is.
+# If left blank, the following values are used ("$name" is automatically
+# replaced with the name of the entity): "The $name class" "The $name widget"
+# "The $name file" "is" "provides" "specifies" "contains"
+# "represents" "a" "an" "the"
+
+ABBREVIATE_BRIEF       =
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# Doxygen will generate a detailed section even if there is only a brief
+# description.
+
+ALWAYS_DETAILED_SEC    = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# inherited members of a class in the documentation of that class as if those
+# members were ordinary class members. Constructors, destructors and assignment
+# operators of the base classes will not be shown.
+
+INLINE_INHERITED_MEMB  = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full
+# path before files name in the file list and in the header files. If set
+# to NO the shortest path that makes the file name unique will be used.
+
+FULL_PATH_NAMES        = YES
+
+# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag
+# can be used to strip a user-defined part of the path. Stripping is
+# only done if one of the specified strings matches the left-hand part of
+# the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the
+# path to strip.
+
+STRIP_FROM_PATH        =
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of
+# the path mentioned in the documentation of a class, which tells
+# the reader which header file to include in order to use a class.
+# If left blank only the name of the header file containing the class
+# definition is used. Otherwise one should specify the include paths that
+# are normally passed to the compiler using the -I flag.
+
+STRIP_FROM_INC_PATH    =
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter
+# (but less readable) file names. This can be useful is your file systems
+# doesn't support long names like on DOS, Mac, or CD-ROM.
+
+SHORT_NAMES            = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen
+# will interpret the first line (until the first dot) of a JavaDoc-style
+# comment as the brief description. If set to NO, the JavaDoc
+# comments will behave just like regular Qt-style comments
+# (thus requiring an explicit @brief command for a brief description.)
+
+JAVADOC_AUTOBRIEF      = YES
+
+# If the QT_AUTOBRIEF tag is set to YES then Doxygen will
+# interpret the first line (until the first dot) of a Qt-style
+# comment as the brief description. If set to NO, the comments
+# will behave just like regular Qt-style comments (thus requiring
+# an explicit \brief command for a brief description.)
+
+QT_AUTOBRIEF           = YES
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen
+# treat a multi-line C++ special comment block (i.e. a block of //! or ///
+# comments) as a brief description. This used to be the default behaviour.
+# The new default is to treat a multi-line C++ comment block as a detailed
+# description. Set this tag to YES if you prefer the old behaviour instead.
+
+MULTILINE_CPP_IS_BRIEF = NO
+
+# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented
+# member inherits the documentation from any documented member that it
+# re-implements.
+
+INHERIT_DOCS           = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce
+# a new page for each member. If set to NO, the documentation of a member will
+# be part of the file/class/namespace that contains it.
+
+SEPARATE_MEMBER_PAGES  = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab.
+# Doxygen uses this value to replace tabs by spaces in code fragments.
+
+TAB_SIZE               = 8
+
+# This tag can be used to specify a number of aliases that acts
+# as commands in the documentation. An alias has the form "name=value".
+# For example adding "sideeffect=\par Side Effects:\n" will allow you to
+# put the command \sideeffect (or @sideeffect) in the documentation, which
+# will result in a user-defined paragraph with heading "Side Effects:".
+# You can put \n's in the value part of an alias to insert newlines.
+
+ALIASES                =
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C
+# sources only. Doxygen will then generate output that is more tailored for C.
+# For instance, some of the names that are used will be different. The list
+# of all members will be omitted, etc.
+
+OPTIMIZE_OUTPUT_FOR_C  = NO
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java
+# sources only. Doxygen will then generate output that is more tailored for
+# Java. For instance, namespaces will be presented as packages, qualified
+# scopes will look different, etc.
+
+OPTIMIZE_OUTPUT_JAVA   = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources only. Doxygen will then generate output that is more tailored for
+# Fortran.
+
+OPTIMIZE_FOR_FORTRAN   = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for
+# VHDL.
+
+OPTIMIZE_OUTPUT_VHDL   = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it parses.
+# With this tag you can assign which parser to use for a given extension.
+# Doxygen has a built-in mapping, but you can override or extend it using this tag.
+# The format is ext=language, where ext is a file extension, and language is one of
+# the parsers supported by doxygen: IDL, Java, Javascript, C#, C, C++, D, PHP,
+# Objective-C, Python, Fortran, VHDL, C, C++. For instance to make doxygen treat
+# .inc files as Fortran files (default is PHP), and .f files as C (default is Fortran),
+# use: inc=Fortran f=C. Note that for custom extensions you also need to set FILE_PATTERNS otherwise the files are not read by doxygen.
+
+EXTENSION_MAPPING      =
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should
+# set this tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string); v.s.
+# func(std::string) {}). This also make the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+
+BUILTIN_STL_SUPPORT    = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+
+CPP_CLI_SUPPORT        = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only.
+# Doxygen will parse them like normal C++ but will assume all classes use public
+# instead of private inheritance when no explicit protection keyword is present.
+
+SIP_SUPPORT            = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate getter
+# and setter methods for a property. Setting this option to YES (the default)
+# will make doxygen to replace the get and set methods by a property in the
+# documentation. This will only work if the methods are indeed getting or
+# setting a simple type. If this is not the case, or you want to show the
+# methods anyway, you should set this option to NO.
+
+IDL_PROPERTY_SUPPORT   = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES, then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+
+DISTRIBUTE_GROUP_DOC   = NO
+
+# Set the SUBGROUPING tag to YES (the default) to allow class member groups of
+# the same type (for instance a group of public functions) to be put as a
+# subgroup of that type (e.g. under the Public Functions section). Set it to
+# NO to prevent subgrouping. Alternatively, this can be done per class using
+# the \nosubgrouping command.
+
+SUBGROUPING            = YES
+
+# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum
+# is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically
+# be useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+
+TYPEDEF_HIDES_STRUCT   = NO 
+
+# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to
+# determine which symbols to keep in memory and which to flush to disk.
+# When the cache is full, less often used symbols will be written to disk.
+# For small to medium size projects (<1000 input files) the default value is
+# probably good enough. For larger projects a too small cache size can cause
+# doxygen to be busy swapping symbols to and from disk most of the time
+# causing a significant performance penality.
+# If the system has enough physical memory increasing the cache will improve the
+# performance by keeping more symbols in memory. Note that the value works on
+# a logarithmic scale so increasing the size by one will rougly double the
+# memory usage. The cache size is given by this formula:
+# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,
+# corresponding to a cache size of 2^16 = 65536 symbols
+
+SYMBOL_CACHE_SIZE      = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in
+# documentation are documented, even if no documentation was available.
+# Private class members and static file members will be hidden unless
+# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
+
+EXTRACT_ALL            = NO
+
+# If the EXTRACT_PRIVATE tag is set to YES all private members of a class
+# will be included in the documentation.
+
+EXTRACT_PRIVATE        = NO
+
+# If the EXTRACT_STATIC tag is set to YES all static members of a file
+# will be included in the documentation.
+
+EXTRACT_STATIC         = NO
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)
+# defined locally in source files will be included in the documentation.
+# If set to NO only classes defined in header files are included.
+
+EXTRACT_LOCAL_CLASSES  = YES
+
+# This flag is only useful for Objective-C code. When set to YES local
+# methods, which are defined in the implementation section but not in
+# the interface are included in the documentation.
+# If set to NO (the default) only methods in the interface are included.
+
+EXTRACT_LOCAL_METHODS  = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base
+# name of the file that contains the anonymous namespace. By default
+# anonymous namespace are hidden.
+
+EXTRACT_ANON_NSPACES   = NO
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
+# undocumented members of documented classes, files or namespaces.
+# If set to NO (the default) these members will be included in the
+# various overviews, but no documentation section is generated.
+# This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_MEMBERS     = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy.
+# If set to NO (the default) these classes will be included in the various
+# overviews. This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_CLASSES     = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all
+# friend (class|struct|union) declarations.
+# If set to NO (the default) these declarations will be included in the
+# documentation.
+
+HIDE_FRIEND_COMPOUNDS  = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any
+# documentation blocks found inside the body of a function.
+# If set to NO (the default) these blocks will be appended to the
+# function's detailed documentation block.
+
+HIDE_IN_BODY_DOCS      = NO
+
+# The INTERNAL_DOCS tag determines if documentation
+# that is typed after a \internal command is included. If the tag is set
+# to NO (the default) then the documentation will be excluded.
+# Set it to YES to include the internal documentation.
+
+INTERNAL_DOCS          = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate
+# file names in lower-case letters. If set to YES upper-case letters are also
+# allowed. This is useful if you have classes or files whose names only differ
+# in case and if your file system supports case sensitive file names. Windows
+# and Mac users are advised to set this option to NO.
+
+CASE_SENSE_NAMES       = YES
+
+# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen
+# will show members with their full class and namespace scopes in the
+# documentation. If set to YES the scope will be hidden.
+
+HIDE_SCOPE_NAMES       = NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen
+# will put a list of the files that are included by a file in the documentation
+# of that file.
+
+SHOW_INCLUDE_FILES     = YES
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen
+# will list include files with double quotes in the documentation
+# rather than with sharp brackets.
+
+FORCE_LOCAL_INCLUDES   = NO
+
+# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]
+# is inserted in the documentation for inline members.
+
+INLINE_INFO            = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen
+# will sort the (detailed) documentation of file and class members
+# alphabetically by member name. If set to NO the members will appear in
+# declaration order.
+
+SORT_MEMBER_DOCS       = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the
+# brief documentation of file, namespace and class members alphabetically
+# by member name. If set to NO (the default) the members will appear in
+# declaration order.
+
+SORT_BRIEF_DOCS        = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the (brief and detailed) documentation of class members so that constructors and destructors are listed first. If set to NO (the default) the constructors will appear in the respective orders defined by SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the
+# hierarchy of group names into alphabetical order. If set to NO (the default)
+# the group names will appear in their defined order.
+
+SORT_GROUP_NAMES       = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be
+# sorted by fully-qualified names, including namespaces. If set to
+# NO (the default), the class list will be sorted only by class name,
+# not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the
+# alphabetical list.
+
+SORT_BY_SCOPE_NAME     = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or
+# disable (NO) the todo list. This list is created by putting \todo
+# commands in the documentation.
+
+GENERATE_TODOLIST      = YES
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or
+# disable (NO) the test list. This list is created by putting \test
+# commands in the documentation.
+
+GENERATE_TESTLIST      = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or
+# disable (NO) the bug list. This list is created by putting \bug
+# commands in the documentation.
+
+GENERATE_BUGLIST       = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or
+# disable (NO) the deprecated list. This list is created by putting
+# \deprecated commands in the documentation.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional
+# documentation sections, marked by \if sectionname ... \endif.
+
+ENABLED_SECTIONS       =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines
+# the initial value of a variable or define consists of for it to appear in
+# the documentation. If the initializer consists of more lines than specified
+# here it will be hidden. Use a value of 0 to hide initializers completely.
+# The appearance of the initializer of individual variables and defines in the
+# documentation can be controlled using \showinitializer or \hideinitializer
+# command in the documentation regardless of this setting.
+
+MAX_INITIALIZER_LINES  = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated
+# at the bottom of the documentation of classes and structs. If set to YES the
+# list will mention the files that were used to generate the documentation.
+
+SHOW_USED_FILES        = YES
+
+# If the sources in your project are distributed over multiple directories
+# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy
+# in the documentation. The default is NO.
+
+SHOW_DIRECTORIES       = NO
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page.
+# This will remove the Files entry from the Quick Index and from the
+# Folder Tree View (if specified). The default is YES.
+
+SHOW_FILES             = YES 
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the
+# Namespaces page.
+# This will remove the Namespaces entry from the Quick Index
+# and from the Folder Tree View (if specified). The default is YES.
+
+SHOW_NAMESPACES        = YES
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command  , where  is the value of
+# the FILE_VERSION_FILTER tag, and  is the name of an input file
+# provided by doxygen. Whatever the program writes to standard output
+# is used as the file version. See the manual for examples.
+
+FILE_VERSION_FILTER    =
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed by
+# doxygen. The layout file controls the global structure of the generated output files
+# in an output format independent way. The create the layout file that represents
+# doxygen's defaults, run doxygen with the -l option. You can optionally specify a
+# file name after the option, if omitted DoxygenLayout.xml will be used as the name
+# of the layout file.
+
+LAYOUT_FILE            =
+
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated
+# by doxygen. Possible values are YES and NO. If left blank NO is used.
+
+QUIET                  = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated by doxygen. Possible values are YES and NO. If left blank
+# NO is used.
+
+WARNINGS               = YES
+
+# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings
+# for undocumented members. If EXTRACT_ALL is set to YES then this flag will
+# automatically be disabled.
+
+WARN_IF_UNDOCUMENTED   = YES
+
+# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some
+# parameters in a documented function, or documenting parameters that
+# don't exist or using markup commands wrongly.
+
+WARN_IF_DOC_ERROR      = YES
+
+# This WARN_NO_PARAMDOC option can be abled to get warnings for
+# functions that are documented, but have no documentation for their parameters
+# or return value. If set to NO (the default) doxygen will only warn about
+# wrong or incomplete parameter documentation, but not about the absence of
+# documentation.
+
+WARN_NO_PARAMDOC       = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that
+# doxygen can produce. The string should contain the $file, $line, and $text
+# tags, which will be replaced by the file and line number from which the
+# warning originated and the warning text. Optionally the format may contain
+# $version, which will be replaced by the version of the file (if it could
+# be obtained via FILE_VERSION_FILTER)
+
+WARN_FORMAT            = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning
+# and error messages should be written. If left blank the output is written
+# to stderr.
+
+WARN_LOGFILE           =
+
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag can be used to specify the files and/or directories that contain
+# documented source files. You may enter file names like "myfile.cpp" or
+# directories like "/usr/src/myproject". Separate the files or directories
+# with spaces.
+
+INPUT                  = . 
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is
+# also the default input encoding. Doxygen uses libiconv (or the iconv built
+# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for
+# the list of possible encodings.
+
+INPUT_ENCODING         = UTF-8
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank the following patterns are tested:
+# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx
+# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90
+
+FILE_PATTERNS          = *.h
+
+# The RECURSIVE tag can be used to turn specify whether or not subdirectories
+# should be searched for input files as well. Possible values are YES and NO.
+# If left blank NO is used.
+
+RECURSIVE              = NO
+
+# The EXCLUDE tag can be used to specify files and/or directories that should
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+
+EXCLUDE                =
+
+# The EXCLUDE_SYMLINKS tag can be used select whether or not files or
+# directories that are symbolic links (a Unix filesystem feature) are excluded
+# from the input.
+
+EXCLUDE_SYMLINKS       = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories. Note that the wildcards are matched
+# against the file with absolute path, so to exclude all test directories
+# for example use the pattern */test/*
+
+EXCLUDE_PATTERNS       =
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# AClass::ANamespace, ANamespace::*Test
+
+EXCLUDE_SYMBOLS        =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or
+# directories that contain example code fragments that are included (see
+# the \include command).
+
+EXAMPLE_PATH           = examples
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank all files are included.
+
+EXAMPLE_PATTERNS       =
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude
+# commands irrespective of the value of the RECURSIVE tag.
+# Possible values are YES and NO. If left blank NO is used.
+
+EXAMPLE_RECURSIVE      = YES
+
+# The IMAGE_PATH tag can be used to specify one or more files or
+# directories that contain image that are included in the documentation (see
+# the \image command).
+
+IMAGE_PATH             =
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command  , where 
+# is the value of the INPUT_FILTER tag, and  is the name of an
+# input file. Doxygen will then use the output that the filter program writes
+# to standard output.
+# If FILTER_PATTERNS is specified, this tag will be
+# ignored.
+
+INPUT_FILTER           =
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis.
+# Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match.
+# The filters are a list of the form:
+# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
+# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER
+# is applied to all files.
+
+FILTER_PATTERNS        =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will be used to filter the input files when producing source
+# files to browse (i.e. when SOURCE_BROWSER is set to YES).
+
+FILTER_SOURCE_FILES    = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will
+# be generated. Documented entities will be cross-referenced with these sources.
+# Note: To get rid of all source code in the generated output, make sure also
+# VERBATIM_HEADERS is set to NO.
+
+SOURCE_BROWSER         = NO
+
+# Setting the INLINE_SOURCES tag to YES will include the body
+# of functions and classes directly in the documentation.
+
+INLINE_SOURCES         = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
+# doxygen to hide any special comment blocks from generated source code
+# fragments. Normal C and C++ comments will always remain visible.
+
+STRIP_CODE_COMMENTS    = YES
+
+# If the REFERENCED_BY_RELATION tag is set to YES
+# then for each documented function all documented
+# functions referencing it will be listed.
+
+REFERENCED_BY_RELATION = NO
+
+# If the REFERENCES_RELATION tag is set to YES
+# then for each documented function all documented entities
+# called/used by that function will be listed.
+
+REFERENCES_RELATION    = NO
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)
+# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from
+# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will
+# link to the source code.
+# Otherwise they will link to the documentation.
+
+REFERENCES_LINK_SOURCE = NO
+
+# If the USE_HTAGS tag is set to YES then the references to source code
+# will point to the HTML generated by the htags(1) tool instead of doxygen
+# built-in source browser. The htags tool is part of GNU's global source
+# tagging system (see http://www.gnu.org/software/global/global.html). You
+# will need version 4.8.6 or higher.
+
+USE_HTAGS              = NO
+
+# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen
+# will generate a verbatim copy of the header file for each class for
+# which an include is specified. Set to NO to disable this.
+
+VERBATIM_HEADERS       = YES 
+
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index
+# of all compounds will be generated. Enable this if the project
+# contains a lot of classes, structs, unions or interfaces.
+
+ALPHABETICAL_INDEX     = NO
+
+# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then
+# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns
+# in which this list will be split (can be a number in the range [1..20])
+
+COLS_IN_ALPHA_INDEX    = 5
+
+# In case all classes in a project start with a common prefix, all
+# classes will be put under the same header in the alphabetical index.
+# The IGNORE_PREFIX tag can be used to specify one or more prefixes that
+# should be ignored while generating the index headers.
+
+IGNORE_PREFIX          =
+
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES (the default) Doxygen will
+# generate HTML output.
+
+GENERATE_HTML          = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `html' will be used as the default path.
+
+HTML_OUTPUT            = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for
+# each generated HTML page (for example: .htm,.php,.asp). If it is left blank
+# doxygen will generate files with .html extension.
+
+HTML_FILE_EXTENSION    = .html
+
+# The HTML_HEADER tag can be used to specify a personal HTML header for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard header.
+
+HTML_HEADER            =
+
+# The HTML_FOOTER tag can be used to specify a personal HTML footer for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard footer.
+
+HTML_FOOTER            =
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
+# style sheet that is used by each HTML page. It can be used to
+# fine-tune the look of the HTML output. If the tag is left blank doxygen
+# will generate a default style sheet. Note that doxygen will try to copy
+# the style sheet file to the HTML output directory, so don't put your own
+# stylesheet in the HTML output directory as well, or it will be erased!
+
+HTML_STYLESHEET        =
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting
+# this to NO can help when comparing the output of multiple runs.
+
+HTML_TIMESTAMP         = YES
+
+# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes,
+# files or namespaces will be aligned in HTML using tables. If set to
+# NO a bullet list will be used.
+
+HTML_ALIGN_MEMBERS     = YES
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded. For this to work a browser that supports
+# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox
+# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari).
+
+HTML_DYNAMIC_SECTIONS  = NO
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files
+# will be generated that can be used as input for Apple's Xcode 3
+# integrated development environment, introduced with OSX 10.5 (Leopard).
+# To create a documentation set, doxygen will generate a Makefile in the
+# HTML output directory. Running make will produce the docset in that
+# directory and running "make install" will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find
+# it at startup.
+# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html for more information.
+
+GENERATE_DOCSET        = NO
+
+# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the
+# feed. A documentation feed provides an umbrella under which multiple
+# documentation sets from a single provider (such as a company or product suite)
+# can be grouped.
+
+DOCSET_FEEDNAME        = "Doxygen generated docs"
+
+# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that
+# should uniquely identify the documentation set bundle. This should be a
+# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen
+# will append .docset to the name.
+
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+
+# If the GENERATE_HTMLHELP tag is set to YES, additional index files
+# will be generated that can be used as input for tools like the
+# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)
+# of the generated HTML documentation.
+
+GENERATE_HTMLHELP      = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can
+# be used to specify the file name of the resulting .chm file. You
+# can add a path in front of the file if the result should not be
+# written to the html output directory.
+
+CHM_FILE               =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can
+# be used to specify the location (absolute path including file name) of
+# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run
+# the HTML help compiler on the generated index.hhp.
+
+HHC_LOCATION           =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
+# controls if a separate .chi index file is generated (YES) or that
+# it should be included in the master .chm file (NO).
+
+GENERATE_CHI           = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING
+# is used to encode HtmlHelp index (hhk), content (hhc) and project file
+# content.
+
+CHM_INDEX_ENCODING     =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag
+# controls whether a binary table of contents is generated (YES) or a
+# normal table of contents (NO) in the .chm file.
+
+BINARY_TOC             = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members
+# to the contents of the HTML help documentation and to the tree view.
+
+TOC_EXPAND             = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and QHP_VIRTUAL_FOLDER
+# are set, an additional index file will be generated that can be used as input for
+# Qt's qhelpgenerator to generate a Qt Compressed Help (.qch) of the generated
+# HTML documentation.
+
+GENERATE_QHP           = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can
+# be used to specify the file name of the resulting .qch file.
+# The path specified is relative to the HTML output folder.
+
+QCH_FILE               =
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#namespace
+
+QHP_NAMESPACE          = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#virtual-folders
+
+QHP_VIRTUAL_FOLDER     = doc
+
+# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to add.
+# For more information please see
+# http://doc.trolltech.com/qthelpproject.html#custom-filters
+
+QHP_CUST_FILTER_NAME   =
+
+# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the custom filter to add.For more information please see
+# Qt Help Project / Custom Filters.
+
+QHP_CUST_FILTER_ATTRS  =
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this project's
+# filter section matches.
+# Qt Help Project / Filter Attributes.
+
+QHP_SECT_FILTER_ATTRS  =
+
+# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can
+# be used to specify the location of Qt's qhelpgenerator.
+# If non-empty doxygen will try to run qhelpgenerator on the generated
+# .qhp file.
+
+QHG_LOCATION           =
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files
+#  will be generated, which together with the HTML files, form an Eclipse help
+#  plugin. To install this plugin and make it available under the help contents
+# menu in Eclipse, the contents of the directory containing the HTML and XML
+# files needs to be copied into the plugins directory of eclipse. The name of
+# the directory within the plugins directory should be the same as
+# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before the help appears.
+
+GENERATE_ECLIPSEHELP   = NO
+
+# A unique identifier for the eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have
+# this name.
+
+ECLIPSE_DOC_ID         = org.doxygen.Project
+
+# The DISABLE_INDEX tag can be used to turn on/off the condensed index at
+# top of each HTML page. The value NO (the default) enables the index and
+# the value YES disables it.
+
+DISABLE_INDEX          = NO
+
+# This tag can be used to set the number of enum values (range [1..20])
+# that doxygen will group on one line in the generated HTML documentation.
+
+ENUM_VALUES_PER_LINE   = 4
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information.
+# If the tag value is set to YES, a side panel will be generated
+# containing a tree-like index structure (just like the one that
+# is generated for HTML Help). For this to work a browser that supports
+# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
+# Windows users are probably better off using the HTML help feature.
+
+GENERATE_TREEVIEW      = NO
+
+# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,
+# and Class Hierarchy pages using a tree view instead of an ordered list.
+
+USE_INLINE_TREES       = NO
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be
+# used to set the initial width (in pixels) of the frame in which the tree
+# is shown.
+
+TREEVIEW_WIDTH         = 250
+
+# Use this tag to change the font size of Latex formulas included
+# as images in the HTML documentation. The default is 10. Note that
+# when you change the font size after a successful doxygen run you need
+# to manually remove any form_*.png images from the HTML output directory
+# to force them to be regenerated.
+
+FORMULA_FONTSIZE       = 10
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box for the HTML output. The underlying search engine uses javascript
+# and DHTML and should work on any modern browser. Note that when using HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) there is already a search function so this one should
+# typically be disabled. For large projects the javascript based search engine
+# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.
+
+SEARCHENGINE           = YES
+
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be implemented using a PHP enabled web server instead of at the web client using Javascript. Doxygen will generate the search PHP script and index
+# file to put on the web server. The advantage of the server based approach is that it scales better to large projects and allows full text search. The disadvances is that it is more difficult to setup
+# and does not have live searching capabilities.
+
+SERVER_BASED_SEARCH    = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will
+# generate Latex output.
+
+GENERATE_LATEX         = NO
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `latex' will be used as the default path.
+
+LATEX_OUTPUT           = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
+# invoked. If left blank `latex' will be used as the default command name.
+# Note that when enabling USE_PDFLATEX this option is only used for
+# generating bitmaps for formulas in the HTML output, but not in the
+# Makefile that is written to the output directory.
+
+LATEX_CMD_NAME         = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to
+# generate index for LaTeX. If left blank `makeindex' will be used as the
+# default command name.
+
+MAKEINDEX_CMD_NAME     = makeindex
+
+# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact
+# LaTeX documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_LATEX          = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used
+# by the printer. Possible values are: a4, a4wide, letter, legal and
+# executive. If left blank a4wide will be used.
+
+PAPER_TYPE             = a4wide
+
+# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
+# packages that should be included in the LaTeX output.
+
+EXTRA_PACKAGES         =
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for
+# the generated latex document. The header should contain everything until
+# the first chapter. If it is left blank doxygen will generate a
+# standard header. Notice: only use this tag if you know what you are doing!
+
+LATEX_HEADER           =
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
+# is prepared for conversion to pdf (using ps2pdf). The pdf file will
+# contain links (just like the HTML output) instead of page references
+# This makes the output suitable for online browsing using a pdf viewer.
+
+PDF_HYPERLINKS         = YES
+
+# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of
+# plain latex in the generated Makefile. Set this option to YES to get a
+# higher quality PDF documentation.
+
+USE_PDFLATEX           = YES
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.
+# command to the generated LaTeX files. This will instruct LaTeX to keep
+# running if errors occur, instead of asking the user for help.
+# This option is also used when generating formulas in HTML.
+
+LATEX_BATCHMODE        = NO
+
+# If LATEX_HIDE_INDICES is set to YES then doxygen will not
+# include the index chapters (such as File Index, Compound Index, etc.)
+# in the output.
+
+LATEX_HIDE_INDICES     = NO
+
+# If LATEX_SOURCE_CODE is set to YES then doxygen will include source code with syntax highlighting in the LaTeX output. Note that which sources are shown also depends on other settings such as SOURCE_BROWSER.
+
+LATEX_SOURCE_CODE      = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output
+# The RTF output is optimized for Word 97 and may not look very pretty with
+# other RTF readers or editors.
+
+GENERATE_RTF           = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `rtf' will be used as the default path.
+
+RTF_OUTPUT             = rtf
+
+# If the COMPACT_RTF tag is set to YES Doxygen generates more compact
+# RTF documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_RTF            = NO
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated
+# will contain hyperlink fields. The RTF file will
+# contain links (just like the HTML output) instead of page references.
+# This makes the output suitable for online browsing using WORD or other
+# programs which support those fields.
+# Note: wordpad (write) and others do not support links.
+
+RTF_HYPERLINKS         = NO
+
+# Load stylesheet definitions from file. Syntax is similar to doxygen's
+# config file, i.e. a series of assignments. You only have to provide
+# replacements, missing definitions are set to their default value.
+
+RTF_STYLESHEET_FILE    =
+
+# Set optional variables used in the generation of an rtf document.
+# Syntax is similar to doxygen's config file.
+
+RTF_EXTENSIONS_FILE    =
+
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES (the default) Doxygen will
+# generate man pages
+
+GENERATE_MAN           = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `man' will be used as the default path.
+
+MAN_OUTPUT             = man
+
+# The MAN_EXTENSION tag determines the extension that is added to
+# the generated man pages (default is the subroutine's section .3)
+
+MAN_EXTENSION          = .3
+
+# If the MAN_LINKS tag is set to YES and Doxygen generates man output,
+# then it will generate one additional man file for each entity
+# documented in the real man page(s). These additional files
+# only source the real man page, but without them the man command
+# would be unable to find the correct page. The default is NO.
+
+MAN_LINKS              = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES Doxygen will
+# generate an XML file that captures the structure of
+# the code including all documentation.
+
+GENERATE_XML           = YES
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `xml' will be used as the default path.
+
+XML_OUTPUT             = xml
+
+# The XML_SCHEMA tag can be used to specify an XML schema,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_SCHEMA             =
+
+# The XML_DTD tag can be used to specify an XML DTD,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_DTD                =
+
+# If the XML_PROGRAMLISTING tag is set to YES Doxygen will
+# dump the program listings (including syntax highlighting
+# and cross-referencing information) to the XML output. Note that
+# enabling this will significantly increase the size of the XML output.
+
+XML_PROGRAMLISTING     = NO
+
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will
+# generate an AutoGen Definitions (see autogen.sf.net) file
+# that captures the structure of the code including all
+# documentation. Note that this feature is still experimental
+# and incomplete at the moment.
+
+GENERATE_AUTOGEN_DEF   = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_PERLMOD tag is set to YES Doxygen will
+# generate a Perl module file that captures the structure of
+# the code including all documentation. Note that this
+# feature is still experimental and incomplete at the
+# moment.
+
+GENERATE_PERLMOD       = NO
+
+# If the PERLMOD_LATEX tag is set to YES Doxygen will generate
+# the necessary Makefile rules, Perl scripts and LaTeX code to be able
+# to generate PDF and DVI output from the Perl module output.
+
+PERLMOD_LATEX          = NO
+
+# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be
+# nicely formatted so it can be parsed by a human reader.
+# This is useful
+# if you want to understand what is going on.
+# On the other hand, if this
+# tag is set to NO the size of the Perl module output will be much smaller
+# and Perl will parse it just the same.
+
+PERLMOD_PRETTY         = YES
+
+# The names of the make variables in the generated doxyrules.make file
+# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.
+# This is useful so different doxyrules.make files included by the same
+# Makefile don't overwrite each other's variables.
+
+PERLMOD_MAKEVAR_PREFIX =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+
+# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will
+# evaluate all C-preprocessor directives found in the sources and include
+# files.
+
+ENABLE_PREPROCESSING   = YES
+
+# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro
+# names in the source code. If set to NO (the default) only conditional
+# compilation will be performed. Macro expansion can be done in a controlled
+# way by setting EXPAND_ONLY_PREDEF to YES.
+
+MACRO_EXPANSION        = NO
+
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES
+# then the macro expansion is limited to the macros specified with the
+# PREDEFINED and EXPAND_AS_DEFINED tags.
+
+EXPAND_ONLY_PREDEF     = NO
+
+# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
+# in the INCLUDE_PATH (see below) will be search if a #include is found.
+
+SEARCH_INCLUDES        = YES
+
+# The INCLUDE_PATH tag can be used to specify one or more directories that
+# contain include files that are not input files but should be processed by
+# the preprocessor.
+
+INCLUDE_PATH           =
+
+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
+# patterns (like *.h and *.hpp) to filter out the header-files in the
+# directories. If left blank, the patterns specified with FILE_PATTERNS will
+# be used.
+
+INCLUDE_FILE_PATTERNS  =
+
+# The PREDEFINED tag can be used to specify one or more macro names that
+# are defined before the preprocessor is started (similar to the -D option of
+# gcc). The argument of the tag is a list of macros of the form: name
+# or name=definition (no spaces). If the definition and the = are
+# omitted =1 is assumed. To prevent a macro definition from being
+# undefined via #undef or recursively expanded use the := operator
+# instead of the = operator.
+
+PREDEFINED             =
+
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
+# this tag can be used to specify a list of macro names that should be expanded.
+# The macro definition that is found in the sources will be used.
+# Use the PREDEFINED tag if you want to use a different macro definition.
+
+EXPAND_AS_DEFINED      =
+
+# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
+# doxygen's preprocessor will remove all function-like macros that are alone
+# on a line, have an all uppercase name, and do not end with a semicolon. Such
+# function macros are typically used for boiler-plate code, and will confuse
+# the parser if not removed.
+
+SKIP_FUNCTION_MACROS   = YES
+
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+
+# The TAGFILES option can be used to specify one or more tagfiles.
+# Optionally an initial location of the external documentation
+# can be added for each tagfile. The format of a tag file without
+# this location is as follows:
+#
+# TAGFILES = file1 file2 ...
+# Adding location for the tag files is done as follows:
+#
+# TAGFILES = file1=loc1 "file2 = loc2" ...
+# where "loc1" and "loc2" can be relative or absolute paths or
+# URLs. If a location is present for each tag, the installdox tool
+# does not have to be run to correct the links.
+# Note that each tag file must have a unique name
+# (where the name does NOT include the path)
+# If a tag file is not located in the directory in which doxygen
+# is run, you must also specify the path to the tagfile here.
+
+TAGFILES               =
+
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create
+# a tag file that is based on the input files it reads.
+
+GENERATE_TAGFILE       =
+
+# If the ALLEXTERNALS tag is set to YES all external classes will be listed
+# in the class index. If set to NO only the inherited external classes
+# will be listed.
+
+ALLEXTERNALS           = NO
+
+# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed
+# in the modules index. If set to NO, only the current project's groups will
+# be listed.
+
+EXTERNAL_GROUPS        = YES
+
+# The PERL_PATH should be the absolute path and name of the perl script
+# interpreter (i.e. the result of `which perl').
+
+PERL_PATH              = /usr/bin/perl
+
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+
+# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
+# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base
+# or super classes. Setting the tag to NO turns the diagrams off. Note that
+# this option is superseded by the HAVE_DOT option below. This is only a
+# fallback. It is recommended to install and use dot, since it yields more
+# powerful graphs.
+
+CLASS_DIAGRAMS         = YES
+
+# You can define message sequence charts within doxygen comments using the \msc
+# command. Doxygen will then run the mscgen tool (see
+# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the
+# documentation. The MSCGEN_PATH tag allows you to specify the directory where
+# the mscgen tool resides. If left empty the tool is assumed to be found in the
+# default search path.
+
+MSCGEN_PATH            =
+
+# If set to YES, the inheritance and collaboration graphs will hide
+# inheritance and usage relations if the target is undocumented
+# or is not a class.
+
+HIDE_UNDOC_RELATIONS   = YES
+
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
+# available from the path. This tool is part of Graphviz, a graph visualization
+# toolkit from AT&T and Lucent Bell Labs. The other options in this section
+# have no effect if this option is set to NO (the default)
+
+HAVE_DOT               = NO
+
+# By default doxygen will write a font called FreeSans.ttf to the output
+# directory and reference it in all dot files that doxygen generates. This
+# font does not include all possible unicode characters however, so when you need
+# these (or just want a differently looking font) you can specify the font name
+# using DOT_FONTNAME. You need need to make sure dot is able to find the font,
+# which can be done by putting it in a standard location or by setting the
+# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory
+# containing the font.
+
+DOT_FONTNAME           = FreeSans
+
+# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs.
+# The default size is 10pt.
+
+DOT_FONTSIZE           = 10
+
+# By default doxygen will tell dot to use the output directory to look for the
+# FreeSans.ttf font (which doxygen will put there itself). If you specify a
+# different font using DOT_FONTNAME you can set the path where dot
+# can find it using this tag.
+
+DOT_FONTPATH           =
+
+# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect inheritance relations. Setting this tag to YES will force the
+# the CLASS_DIAGRAMS tag to NO.
+
+CLASS_GRAPH            = YES
+
+# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect implementation dependencies (inheritance, containment, and
+# class references variables) of the class with other documented classes.
+
+COLLABORATION_GRAPH    = YES
+
+# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for groups, showing the direct groups dependencies
+
+GROUP_GRAPHS           = YES
+
+# If the UML_LOOK tag is set to YES doxygen will generate inheritance and
+# collaboration diagrams in a style similar to the OMG's Unified Modeling
+# Language.
+
+UML_LOOK               = NO
+
+# If set to YES, the inheritance and collaboration graphs will show the
+# relations between templates and their instances.
+
+TEMPLATE_RELATIONS     = NO
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT
+# tags are set to YES then doxygen will generate a graph for each documented
+# file showing the direct and indirect include dependencies of the file with
+# other documented files.
+
+INCLUDE_GRAPH          = YES
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and
+# HAVE_DOT tags are set to YES then doxygen will generate a graph for each
+# documented header file showing the documented files that directly or
+# indirectly include this file.
+
+INCLUDED_BY_GRAPH      = YES
+
+# If the CALL_GRAPH and HAVE_DOT options are set to YES then
+# doxygen will generate a call dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable call graphs
+# for selected functions only using the \callgraph command.
+
+CALL_GRAPH             = NO
+
+# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then
+# doxygen will generate a caller dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable caller
+# graphs for selected functions only using the \callergraph command.
+
+CALLER_GRAPH           = NO
+
+# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
+# will graphical hierarchy of all classes instead of a textual one.
+
+GRAPHICAL_HIERARCHY    = YES
+
+# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES
+# then doxygen will show the dependencies a directory has on other directories
+# in a graphical way. The dependency relations are determined by the #include
+# relations between the files in the directories.
+
+DIRECTORY_GRAPH        = YES
+
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
+# generated by dot. Possible values are png, jpg, or gif
+# If left blank png will be used.
+
+DOT_IMAGE_FORMAT       = png
+
+# The tag DOT_PATH can be used to specify the path where the dot tool can be
+# found. If left blank, it is assumed the dot tool can be found in the path.
+
+DOT_PATH               =
+
+# The DOTFILE_DIRS tag can be used to specify one or more directories that
+# contain dot files that are included in the documentation (see the
+# \dotfile command).
+
+DOTFILE_DIRS           =
+
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of
+# nodes that will be shown in the graph. If the number of nodes in a graph
+# becomes larger than this value, doxygen will truncate the graph, which is
+# visualized by representing a node as a red box. Note that doxygen if the
+# number of direct children of the root node in a graph is already larger than
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note
+# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+
+DOT_GRAPH_MAX_NODES    = 50
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the
+# graphs generated by dot. A depth value of 3 means that only nodes reachable
+# from the root by following a path via at most 3 edges will be shown. Nodes
+# that lay further from the root node will be omitted. Note that setting this
+# option to 1 or 2 may greatly reduce the computation time needed for large
+# code bases. Also note that the size of a graph can be further restricted by
+# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
+
+MAX_DOT_GRAPH_DEPTH    = 0
+
+# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent
+# background. This is disabled by default, because dot on Windows does not
+# seem to support this out of the box. Warning: Depending on the platform used,
+# enabling this option may lead to badly anti-aliased labels on the edges of
+# a graph (i.e. they become hard to read).
+
+DOT_TRANSPARENT        = NO
+
+# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output
+# files in one run (i.e. multiple -o and -T options on the command line). This
+# makes dot run faster, but since only newer versions of dot (>1.8.10)
+# support this, this feature is disabled by default.
+
+DOT_MULTI_TARGETS      = YES
+
+# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will
+# generate a legend page explaining the meaning of the various boxes and
+# arrows in the dot generated graphs.
+
+GENERATE_LEGEND        = YES
+
+# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will
+# remove the intermediate dot files that are used to generate
+# the various graphs.
+
+DOT_CLEANUP            = YES
diff --git a/hardware/digistump/sam/libraries/RF24Network/Jamfile b/hardware/digistump/sam/libraries/RF24Network/Jamfile
new file mode 100644
index 0000000..51c1220
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/Jamfile
@@ -0,0 +1,210 @@
+# (1) Project Information
+
+PROJECT_LIBS 	= SPI RF24 RF24Network ; 
+
+# (2) Board Information
+
+UPLOAD_PROTOCOL ?= stk500v1 ;
+UPLOAD_SPEED 	?= 57600 ;
+MCU		?= atmega328p ;
+F_CPU 		?= 16000000 ;
+CORE		?= arduino ;
+VARIANT 	?= standard ;
+ARDUINO_VERSION	?= 100 ;
+
+# (3) USB Ports
+
+PORTS		= p4 p6 p9 u0 u1 u2 ;
+PORT_p6 	= /dev/tty.usbserial-A600eHIs ;
+PORT_p4 	= /dev/tty.usbserial-A40081RP ;
+PORT_p9		= /dev/tty.usbserial-A9007LmI ;
+PORT_u0 	= /dev/ttyUSB0 ;
+PORT_u1 	= /dev/ttyUSB1 ;
+PORT_u2 	= /dev/ttyUSB2 ;
+
+# (4) Location of AVR tools
+#
+# This configuration assumes using avr-tools that were obtained separate from the Arduino
+# distribution. 
+
+if $(OS) = MACOSX 
+{
+	AVR_BIN 	= /usr/local/avrtools/bin ;
+	AVR_ETC 	= /usr/local/avrtools/etc ;
+	AVR_INCLUDE	= /usr/local/avrtools/include ; 
+}
+else
+{
+	AVR_BIN 	= /usr/bin ;
+	AVR_INCLUDE 	= /usr/lib/avr/include ;
+	AVR_ETC 	= /etc ; 
+}
+
+# (5) Directories where Arduino core and libraries are located
+
+ARDUINO_DIR 	?= /opt/Arduino ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+
+#
+# --------------------------------------------------
+# Below this line usually never needs to be modified 
+#
+
+# Tool locations
+
+CC	  	= $(AVR_BIN)/avr-gcc ;
+C++	 	= $(AVR_BIN)/avr-g++ ;
+LINK	  	= $(AVR_BIN)/avr-gcc ;
+OBJCOPY 	= $(AVR_BIN)/avr-objcopy ;
+AVRDUDE 	= $(AVR_BIN)/avrdude ;
+
+# Flags
+
+DEFINES  	+= NODE=$(NODE) F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+OPTIM		= -Os ;
+CCFLAGS  	= -Wall -Wextra -mmcu=$(MCU) -ffunction-sections -fdata-sections ;
+C++FLAGS  	= $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ;
+LINKFLAGS  	= $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ;
+AVRDUDEFLAGS	= -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ;
+
+# Search everywhere for headers
+
+HDRS  	 	= $(PWD) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ;
+
+# Output locations
+
+LOCATE_TARGET	= $(F_CPU) ;
+LOCATE_SOURCE	= $(F_CPU) ;
+
+#
+# Custom rules
+#
+
+rule GitVersion
+{
+	Always $(<) ;
+	Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+	echo "const char program_version[] = \"\\" > $(<)
+	git log -1 --pretty=format:%h >> $(<)
+	echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule Pde
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+if ( $(ARDUINO_VERSION) < 100 )
+{
+	ARDUINO_H = WProgram.h ;
+}
+else
+{
+	ARDUINO_H = Arduino.h ;
+}
+
+actions Pde
+{
+	echo "#include <$(ARDUINO_H)>" > $(<) 
+	echo "#line 1 \"$(>)\"" >> $(<)
+	cat $(>) >> $(<) 
+}
+
+rule C++Pde
+{
+	local _CPP = $(>:B).cpp ;
+	Pde $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule UserObject
+{
+	switch $(>:S)
+	{
+		case .ino : C++Pde $(<) : $(>) ;
+		case .pde : C++Pde $(<) : $(>) ;
+	}
+}
+
+rule Objects
+{
+        local _i ;
+
+        for _i in [ FGristFiles $(<) ]
+        {
+		local _b = $(_i:B)$(SUFOBJ) ;
+		local _o = $(_b:G=$(SOURCE_GRIST:E)) ;
+                Object $(_o) : $(_i) ;
+                Depends obj : $(_o) ;
+        }
+}
+
+rule Main
+{
+        MainFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+        Objects $(>) ;
+}
+
+rule Hex
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends hex : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Hex
+{
+	$(OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule Upload
+{
+	Depends $(1) : $(2) ;
+	Depends $(2) : $(3) ;
+	NotFile $(1) ;
+	Always $(1) ;
+	Always $(2) ;
+	UploadAction $(2) : $(3) ;
+}
+
+actions UploadAction
+{
+	$(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+#
+# Targets
+#
+
+# Grab everything from the core directory
+CORE_MODULES  	= [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+LIB_MODULES  	= [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ;
+
+# Grab everything from the current dir
+PROJECT_MODULES += [ GLOB $(PWD) : *.c *.cpp *.pde *.ino ] ;
+
+# Main output executable
+MAIN		= $(PWD:B).elf ;
+
+Main $(MAIN) : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ;
+Hex $(MAIN:B).hex : $(MAIN) ;
+
+# Upload targets
+for _p in $(PORTS)
+{
+	Upload $(_p) : $(PORT_$(_p)) : $(MAIN:B).hex ;
+}
diff --git a/hardware/digistump/sam/libraries/RF24Network/README.md b/hardware/digistump/sam/libraries/RF24Network/README.md
new file mode 100644
index 0000000..f68418b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/README.md
@@ -0,0 +1,3 @@
+# Network Layer for nRF24L01(+) radios
+
+Please see the full documentation at http://maniacbug.github.com/RF24Network/index.html 
diff --git a/hardware/digistump/sam/libraries/RF24Network/RF24Network.cpp b/hardware/digistump/sam/libraries/RF24Network/RF24Network.cpp
new file mode 100644
index 0000000..e68fe22
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/RF24Network.cpp
@@ -0,0 +1,440 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#include "RF24Network_config.h"
+#include "RF24.h"
+#include "RF24Network.h"
+
+uint16_t RF24NetworkHeader::next_id = 1;
+
+uint64_t pipe_address( uint16_t node, uint8_t pipe );
+bool is_valid_address( uint16_t node );
+
+/******************************************************************/
+
+RF24Network::RF24Network( RF24& _radio ): radio(_radio), next_frame(frame_queue)
+{
+}
+
+/******************************************************************/
+
+void RF24Network::begin(uint8_t _channel, uint16_t _node_address )
+{
+  if (! is_valid_address(_node_address) )
+    return;
+
+  node_address = _node_address;
+
+  // Set up the radio the way we want it to look
+  radio.setChannel(_channel);
+  radio.setDataRate(RF24_1MBPS);
+  radio.setCRCLength(RF24_CRC_16);
+
+  // Setup our address helper cache
+  setup_address();
+  
+  // Open up all listening pipes
+  int i = 6;
+  while (i--)
+    radio.openReadingPipe(i,pipe_address(_node_address,i));
+  radio.startListening();
+
+  // Spew debugging state about the radio
+  radio.printDetails();
+}
+
+/******************************************************************/
+
+void RF24Network::update(void)
+{
+  // if there is data ready
+  uint8_t pipe_num;
+  while ( radio.available(&pipe_num) )
+  {
+    // Dump the payloads until we've gotten everything
+    boolean done = false;
+    while (!done)
+    {
+      // Fetch the payload, and see if this was the last one.
+      done = radio.read( frame_buffer, sizeof(frame_buffer) );
+
+      // Read the beginning of the frame as the header
+      const RF24NetworkHeader& header = * reinterpret_cast(frame_buffer);
+
+      IF_SERIAL_DEBUG(printf_P(PSTR("%lu: MAC Received on %u %s\n\r"),millis(),pipe_num,header.toString()));
+      IF_SERIAL_DEBUG(const uint16_t* i = reinterpret_cast(frame_buffer + sizeof(RF24NetworkHeader));printf_P(PSTR("%lu: NET message %04x\n\r"),millis(),*i));
+
+      // Throw it away if it's not a valid address
+      if ( !is_valid_address(header.to_node) )
+	continue;
+
+      // Is this for us?
+      if ( header.to_node == node_address )
+	// Add it to the buffer of frames for us
+	enqueue();
+      else
+	// Relay it
+	write(header.to_node);
+
+      // NOT NEEDED anymore.  Now all reading pipes are open to start.
+#if 0
+      // If this was for us, from one of our children, but on our listening
+      // pipe, it could mean that we are not listening to them.  If so, open up
+      // and listen to their talking pipe
+
+      if ( header.to_node == node_address && pipe_num == 0 && is_descendant(header.from_node) )
+      {
+	uint8_t pipe = pipe_to_descendant(header.from_node);
+	radio.openReadingPipe(pipe,pipe_address(node_address,pipe));
+
+	// Also need to open pipe 1 so the system can get the full 5-byte address of the pipe.
+	radio.openReadingPipe(1,pipe_address(node_address,1));
+      }
+#endif
+    }
+  }
+}
+
+/******************************************************************/
+
+bool RF24Network::enqueue(void)
+{
+  bool result = false;
+  
+  IF_SERIAL_DEBUG(printf_P(PSTR("%lu: NET Enqueue @%x "),millis(),next_frame-frame_queue));
+
+  // Copy the current frame into the frame queue
+  if ( next_frame < frame_queue + sizeof(frame_queue) )
+  {
+    memcpy(next_frame,frame_buffer, frame_size );
+    next_frame += frame_size; 
+
+    result = true;
+    IF_SERIAL_DEBUG(printf_P(PSTR("ok\n\r")));
+  }
+  else
+  {
+    IF_SERIAL_DEBUG(printf_P(PSTR("failed\n\r")));
+  }
+
+  return result;
+}
+
+/******************************************************************/
+
+bool RF24Network::available(void)
+{
+  // Are there frames on the queue for us?
+  return (next_frame > frame_queue);
+}
+
+/******************************************************************/
+
+uint16_t RF24Network::parent() const
+{
+  if ( node_address == 0 )
+    return -1;
+  else
+    return parent_node;
+}
+
+/******************************************************************/
+
+void RF24Network::peek(RF24NetworkHeader& header)
+{
+  if ( available() )
+  {
+    // Copy the next available frame from the queue into the provided buffer
+    memcpy(&header,next_frame-frame_size,sizeof(RF24NetworkHeader));
+  }
+}
+
+/******************************************************************/
+
+size_t RF24Network::read(RF24NetworkHeader& header,void* message, size_t maxlen)
+{
+  size_t bufsize = 0;
+
+  if ( available() )
+  {
+    // Move the pointer back one in the queue 
+    next_frame -= frame_size;
+    uint8_t* frame = next_frame;
+      
+    // How much buffer size should we actually copy?
+    bufsize = min(maxlen,frame_size-sizeof(RF24NetworkHeader));
+
+    // Copy the next available frame from the queue into the provided buffer
+    memcpy(&header,frame,sizeof(RF24NetworkHeader));
+    memcpy(message,frame+sizeof(RF24NetworkHeader),bufsize);
+    
+    IF_SERIAL_DEBUG(printf_P(PSTR("%lu: NET Received %s\n\r"),millis(),header.toString()));
+  }
+
+  return bufsize;
+}
+
+/******************************************************************/
+
+bool RF24Network::write(RF24NetworkHeader& header,const void* message, size_t len)
+{
+  // Fill out the header
+  header.from_node = node_address;
+
+  // Build the full frame to send
+  memcpy(frame_buffer,&header,sizeof(RF24NetworkHeader));
+  if (len)
+    memcpy(frame_buffer + sizeof(RF24NetworkHeader),message,min(frame_size-sizeof(RF24NetworkHeader),len));
+
+  IF_SERIAL_DEBUG(printf_P(PSTR("%lu: NET Sending %s\n\r"),millis(),header.toString()));
+  if (len)
+  {
+    IF_SERIAL_DEBUG(const uint16_t* i = reinterpret_cast(message);printf_P(PSTR("%lu: NET message %04x\n\r"),millis(),*i));
+  }
+
+
+  // If the user is trying to send it to himself
+  if ( header.to_node == node_address )
+    // Just queue it in the received queue
+    return enqueue();
+  else
+    // Otherwise send it out over the air
+    return write(header.to_node);
+}
+
+/******************************************************************/
+
+bool RF24Network::write(uint16_t to_node)
+{
+  bool ok = false;
+  
+  // Throw it away if it's not a valid address
+  if ( !is_valid_address(to_node) )
+    return false;
+
+  // First, stop listening so we can talk.
+  //radio.stopListening();
+
+  // Where do we send this?  By default, to our parent
+  uint16_t send_node = parent_node;
+  // On which pipe
+  uint8_t send_pipe = parent_pipe;
+  
+  // If the node is a direct child,
+  if ( is_direct_child(to_node) )
+  {
+    // Send directly
+    send_node = to_node;
+
+    // To its listening pipe
+    send_pipe = 0;
+  }
+  // If the node is a child of a child
+  // talk on our child's listening pipe,
+  // and let the direct child relay it.
+  else if ( is_descendant(to_node) )
+  {
+    send_node = direct_child_route_to(to_node);
+    send_pipe = 0;
+  }
+  
+  IF_SERIAL_DEBUG(printf_P(PSTR("%lu: MAC Sending to 0%o via 0%o on pipe %x\n\r"),millis(),to_node,send_node,send_pipe));
+
+  // First, stop listening so we can talk
+  radio.stopListening();
+
+  // Put the frame on the pipe
+  ok = write_to_pipe( send_node, send_pipe );
+
+      // NOT NEEDED anymore.  Now all reading pipes are open to start.
+#if 0
+  // If we are talking on our talking pipe, it's possible that no one is listening.
+  // If this fails, try sending it on our parent's listening pipe.  That will wake
+  // it up, and next time it will listen to us.
+
+  if ( !ok && send_node == parent_node )
+    ok = write_to_pipe( parent_node, 0 );
+#endif
+
+  // Now, continue listening
+  radio.startListening();
+
+  return ok;
+}
+
+/******************************************************************/
+
+bool RF24Network::write_to_pipe( uint16_t node, uint8_t pipe )
+{
+  bool ok = false;
+  
+  uint64_t out_pipe = pipe_address( node, pipe );
+ 
+  // Open the correct pipe for writing.  
+  radio.openWritingPipe(out_pipe);
+
+  // Retry a few times
+  short attempts = 5;
+  do
+  {
+    ok = radio.write( frame_buffer, frame_size );
+  }
+  while ( !ok && --attempts );
+
+  IF_SERIAL_DEBUG(printf_P(PSTR("%lu: MAC Sent on %lx %S\n\r"),millis(),(uint32_t)out_pipe,ok?PSTR("ok"):PSTR("failed")));
+
+  return ok;
+}
+
+/******************************************************************/
+
+const char* RF24NetworkHeader::toString(void) const
+{
+  static char buffer[45];
+  snprintf(buffer,sizeof(buffer),"id %04x from 0%o to 0%o type %c",id,from_node,to_node,type);
+  return buffer;
+}
+
+/******************************************************************/
+
+bool RF24Network::is_direct_child( uint16_t node )
+{
+  bool result = false;
+
+  // A direct child of ours has the same low numbers as us, and only
+  // one higher number.
+  //
+  // e.g. node 0234 is a direct child of 034, and node 01234 is a
+  // descendant but not a direct child
+
+  // First, is it even a descendant?
+  if ( is_descendant(node) )
+  {
+    // Does it only have ONE more level than us?
+    uint16_t child_node_mask = ( ~ node_mask ) << 3;
+    result = ( node & child_node_mask ) == 0 ;
+  }
+
+  return result;
+}
+
+/******************************************************************/
+
+bool RF24Network::is_descendant( uint16_t node )
+{
+  return ( node & node_mask ) == node_address;
+}
+
+/******************************************************************/
+
+void RF24Network::setup_address(void)
+{
+  // First, establish the node_mask
+  uint16_t node_mask_check = 0xFFFF;
+  while ( node_address & node_mask_check )
+    node_mask_check <<= 3;
+  
+  node_mask = ~ node_mask_check;
+
+  // parent mask is the next level down
+  uint16_t parent_mask = node_mask >> 3;
+
+  // parent node is the part IN the mask
+  parent_node = node_address & parent_mask;
+
+  // parent pipe is the part OUT of the mask
+  uint16_t i = node_address;
+  uint16_t m = parent_mask;
+  while (m)
+  {
+    i >>= 3;
+    m >>= 3;
+  }
+  parent_pipe = i;
+
+#ifdef SERIAL_DEBUG
+  printf_P(PSTR("setup_address node=0%o mask=0%o parent=0%o pipe=0%o\n\r"),node_address,node_mask,parent_node,parent_pipe);
+#endif
+}
+
+/******************************************************************/
+
+uint16_t RF24Network::direct_child_route_to( uint16_t node )
+{
+  // Presumes that this is in fact a child!!
+
+  uint16_t child_mask = ( node_mask << 3 ) | 0B111;
+  return node & child_mask ;
+}
+
+/******************************************************************/
+
+uint8_t RF24Network::pipe_to_descendant( uint16_t node )
+{
+  uint16_t i = node;
+  uint16_t m = node_mask;
+  
+  while (m)
+  {
+    i >>= 3;
+    m >>= 3;
+  }
+
+  return i & 0B111;
+}
+
+/******************************************************************/
+
+bool is_valid_address( uint16_t node )
+{
+  bool result = true;
+
+  while(node)
+  {
+    uint8_t digit = node & 0B111;
+    if (digit < 1 || digit > 5)
+    {
+      result = false;
+      printf_P(PSTR("*** WARNING *** Invalid address 0%o\n\r"),node);
+      break;
+    }
+    node >>= 3;
+  }
+
+  return result;
+}
+
+/******************************************************************/
+
+uint64_t pipe_address( uint16_t node, uint8_t pipe )
+{
+  static uint8_t pipe_segment[] = { 0x3c, 0x5a, 0x69, 0x96, 0xa5, 0xc3 };
+
+  uint64_t result;
+  uint8_t* out = reinterpret_cast(&result);
+
+  out[0] = pipe_segment[pipe];
+
+  uint8_t w; 
+  short i = 4;
+  short shift = 12;
+  while(i--)
+  {
+    w = ( node >> shift ) & 0xF ; 
+    w |= ~w << 4;
+    out[i+1] = w;
+
+    shift -= 4;
+  }
+
+  IF_SERIAL_DEBUG(uint32_t* top = reinterpret_cast(out+1);printf_P(PSTR("%lu: NET Pipe %i on node 0%o has address %lx%x\n\r"),millis(),pipe,node,*top,*out));
+
+  return result;
+}
+
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/RF24Network.h b/hardware/digistump/sam/libraries/RF24Network/RF24Network.h
new file mode 100644
index 0000000..4d599c4
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/RF24Network.h
@@ -0,0 +1,350 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef __RF24NETWORK_H__
+#define __RF24NETWORK_H__
+
+/**
+ * @file RF24Network.h
+ *
+ * Class declaration for RF24Network
+ */
+
+#include 
+#include 
+
+class RF24;
+
+/**
+ * Header which is sent with each message
+ *
+ * The frame put over the air consists of this header and a message
+ */
+struct RF24NetworkHeader
+{
+  uint16_t from_node; /**< Logical address where the message was generated */
+  uint16_t to_node; /**< Logical address where the message is going */
+  uint16_t id; /**< Sequential message ID, incremented every message */
+  unsigned char type; /**< Type of the packet.  0-127 are user-defined types, 128-255 are reserved for system */
+  unsigned char reserved; /**< Reserved for future use */
+
+  static uint16_t next_id; /**< The message ID of the next message to be sent */
+
+  /**
+   * Default constructor
+   *
+   * Simply constructs a blank header
+   */
+  RF24NetworkHeader() {}
+
+  /**
+   * Send constructor
+   *
+   * Use this constructor to create a header and then send a message
+   *
+   * @code
+   *  RF24NetworkHeader header(recipient_address,'t');
+   *  network.write(header,&message,sizeof(message));
+   * @endcode
+   *
+   * @param _to The logical node address where the message is going
+   * @param _type The type of message which follows.  Only 0-127 are allowed for
+   * user messages.
+   */
+  RF24NetworkHeader(uint16_t _to, unsigned char _type = 0): to_node(_to), id(next_id++), type(_type&0x7f) {}
+
+  /**
+   * Create debugging string
+   *
+   * Useful for debugging.  Dumps all members into a single string, using
+   * internal static memory.  This memory will get overridden next time
+   * you call the method.
+   *
+   * @return String representation of this object
+   */
+  const char* toString(void) const;
+};
+
+/**
+ * Network Layer for RF24 Radios
+ *
+ * This class implements an OSI Network Layer using nRF24L01(+) radios driven
+ * by RF24 library.
+ */
+
+class RF24Network
+{
+public:
+  /**
+   * Construct the network
+   *
+   * @param _radio The underlying radio driver instance
+   *
+   */
+  RF24Network( RF24& _radio );
+
+  /**
+   * Bring up the network
+   *
+   * @warning Be sure to 'begin' the radio first.
+   *
+   * @param _channel The RF channel to operate on
+   * @param _node_address The logical address of this node
+   */
+  void begin(uint8_t _channel, uint16_t _node_address );
+  
+  /**
+   * Main layer loop
+   *
+   * This function must be called regularly to keep the layer going.  This is where all
+   * the action happens!
+   */
+  void update(void);
+
+  /**
+   * Test whether there is a message available for this node
+   * 
+   * @return Whether there is a message available for this node
+   */
+  bool available(void);
+ 
+  /**
+   * Read the next available header
+   *
+   * Reads the next available header without advancing to the next
+   * incoming message.  Useful for doing a switch on the message type
+   *
+   * If there is no message available, the header is not touched
+   *
+   * @param[out] header The header (envelope) of the next message
+   */
+  void peek(RF24NetworkHeader& header);
+
+  /**
+   * Read a message
+   *
+   * @param[out] header The header (envelope) of this message
+   * @param[out] message Pointer to memory where the message should be placed
+   * @param maxlen The largest message size which can be held in @p message
+   * @return The total number of bytes copied into @p message
+   */
+  size_t read(RF24NetworkHeader& header, void* message, size_t maxlen);
+  
+  /**
+   * Send a message
+   *
+   * @param[in,out] header The header (envelope) of this message.  The critical
+   * thing to fill in is the @p to_node field so we know where to send the
+   * message.  It is then updated with the details of the actual header sent.
+   * @param message Pointer to memory where the message is located 
+   * @param len The size of the message 
+   * @return Whether the message was successfully received 
+   */
+  bool write(RF24NetworkHeader& header,const void* message, size_t len);
+
+  /**
+   * This node's parent address
+   * 
+   * @return This node's parent address, or -1 if this is the base 
+   */
+  uint16_t parent() const;
+ 
+protected:
+  void open_pipes(void);
+  uint16_t find_node( uint16_t current_node, uint16_t target_node );
+  bool write(uint16_t);
+  bool write_to_pipe( uint16_t node, uint8_t pipe );
+  bool enqueue(void);
+
+  bool is_direct_child( uint16_t node );
+  bool is_descendant( uint16_t node );
+  uint16_t direct_child_route_to( uint16_t node );
+  uint8_t pipe_to_descendant( uint16_t node );
+  void setup_address(void);
+
+private:
+  RF24& radio; /**< Underlying radio driver, provides link/physical layers */ 
+  uint16_t node_address; /**< Logical node address of this unit, 1 .. UINT_MAX */
+  const static int frame_size = 32; /**< How large is each frame over the air */ 
+  uint8_t frame_buffer[frame_size]; /**< Space to put the frame that will be sent/received over the air */
+  uint8_t frame_queue[5*frame_size]; /**< Space for a small set of frames that need to be delivered to the app layer */
+  uint8_t* next_frame; /**< Pointer into the @p frame_queue where we should place the next received frame */
+
+  uint16_t parent_node; /**< Our parent's node address */
+  uint8_t parent_pipe; /**< The pipe our parent uses to listen to us */
+  uint16_t node_mask; /**< The bits which contain signfificant node address information */
+};
+
+/**
+ * @example helloworld_tx.pde
+ *
+ * Simplest possible example of using RF24Network.  Put this sketch
+ * on one node, and helloworld_rx.pde on the other.  Tx will send
+ * Rx a nice message every 2 seconds which rx will print out for us.
+ */
+
+/**
+ * @example helloworld_rx.pde
+ *
+ * Simplest possible example of using RF24Network.  Put this sketch
+ * on one node, and helloworld_tx.pde on the other.  Tx will send
+ * Rx a nice message every 2 seconds which rx will print out for us.
+ */
+
+/**
+ * @example meshping.pde
+ *
+ * Example of pinging across a mesh network
+ * Using this sketch, each node will send a ping to the base every
+ * few seconds.  The RF24Network library will route the message across
+ * the mesh to the correct node.
+ */
+
+/**
+ * @example sensornet.pde
+ *
+ * Example of a sensor network.
+ * This sketch demonstrates how to use the RF24Network library to
+ * manage a set of low-power sensor nodes which mostly sleep but
+ * awake regularly to send readings to the base.
+ */
+/**
+ * @mainpage Network Layer for RF24 Radios
+ *
+ * This class implements an OSI Network Layer using nRF24L01(+) radios driven
+ * by the RF24 library.
+ *
+ * @section Purpose Purpose/Goal
+ *
+ * Create an alternative to ZigBee radios for Arduino communication.
+ *
+ * Xbees are excellent little radios, backed up by a mature and robust standard 
+ * protocol stack.  They are also expensive.
+ *
+ * For many Arduino uses, they seem like overkill.  So I am working to build
+ * an alternative using nRF24L01 radios.  Modules are available for less than 
+ * $6 from many sources.  With the RF24Network layer, I hope to cover many
+ * common communication scenarios.
+ *
+ * Please see the @ref Zigbee page for a comparison against the ZigBee protocols
+ *
+ * @section Features Features
+ *
+ * The layer provides:
+ * @li Host Addressing.  Each node has a logical address on the local network.
+ * @li Message Forwarding.  Messages can be sent from one node to any other, and
+ * this layer will get them there no matter how many hops it takes.
+ * @li Ad-hoc Joining.  A node can join a network without any changes to any
+ * existing nodes.
+ *
+ * The layer does not (yet) provide:
+ * @li Fragmentation/reassembly.  Ability to send longer messages and put them
+ * all back together before exposing them up to the app.
+ * @li Power-efficient listening.  It would be useful for nodes who are listening
+ * to sleep for extended periods of time if they could know that they would miss
+ * no traffic.
+ * @li Dynamic address assignment.
+ *
+ * @section More How to learn more
+ *
+ * @li RF24: Underlying radio driver
+ * @li RF24Network Class Documentation
+ * @li Source Code
+ * @li Downloads Page
+ * @li Examples Page.  Start with helloworld_rx and helloworld_tx.
+ *
+ * @section Topology Topology for Mesh Networks using nRF24L01(+)
+ *
+ * This network layer takes advantage of the fundamental capability of the nRF24L01(+) radio to
+ * listen actively to up to 6 other radios at once.  The network is arranged in a 
+ * Tree Topology, where
+ * one node is the base, and all other nodes are children either of that node, or of another.
+ * Unlike a true mesh network, multiple nodes are not connected together, so there is only one
+ * path to any given node.
+ *
+ * @section Octal Octal Addressing
+ *
+ * Each node must be assigned an 15-bit address by the administrator.  This address exactly
+ * describes the position of the node within the tree.  The address is an octal number.  Each
+ * digit in the address represents a position in the tree further from the base.
+ *
+ * @li Node 00 is the base node.
+ * @li Nodes 01-05 are nodes whose parent is the base.
+ * @li Node 021 is the second child of node 01.
+ * @li Node 0321 is the third child of node 021, an so on.
+ * @li The largest node address is 05555, so 3,125 nodes are allowed on a single channel.
+ *
+ * @section Routing How routing is handled
+ *
+ * When sending a message using RF24Network::write(), you fill in the header with the logical
+ * node address.  The network layer figures out the right path to find that node, and sends
+ * it through the system until it gets to the right place.  This works even if the two nodes
+ * are far separated, as it will send the message down to the base node, and then back out
+ * to the final destination.
+ *
+ * All of this work is handled by the RF24Network::update() method, so be sure to call it
+ * regularly or your network will miss packets.
+ *
+ * @section Startup Starting up a node
+ *
+ * When a node starts up, it only has to contact its parent to establish communication.
+ * No direct connection to the Base node is needed.  This is useful in situations where
+ * relay nodes are being used to bridge the distance to the base, so leaf nodes are out
+ * of range of the base.
+ *
+ * @section Directionality Directionality 
+ *
+ * By default all nodes are always listening, so messages will quickly reach
+ * their destination.  
+ * 
+ * You may choose to sleep any nodes which do not have any active children on the network
+ * (i.e. leaf nodes).  This is useful in a case where
+ * the leaf nodes are operating on batteries and need to sleep.
+ * This is useful for a sensor network.  The leaf nodes can sleep most of the time, and wake
+ * every few minutes to send in a reading.  However, messages cannot be sent to these 
+ * sleeping nodes.
+ *
+ * In the future, I plan to write a system where messages can still be passed upward from
+ * the base, and get delivered when a sleeping node is ready to receive them.  The radio
+ * and underlying driver support 'ack payloads', which will be a handy mechanism for this.
+ *
+ * @page Zigbee Comparison to ZigBee
+ *
+ * This network layer is influenced by the design of ZigBee, but does not implement it
+ * directly.  
+ *
+ * @section Advantage Which is better?
+ *
+ * ZigBee is a much more robust, feature-rich set of protocols, with many different vendors
+ * providing compatible chips.
+ *
+ * RF24Network is cheap.  While ZigBee radios are well over $20, nRF24L01 modules can be found
+ * for under $6.  My personal favorite is 
+ * MDFly RF-IS2401.
+ *
+ * @section Contrast Similiarities & Differences
+ *
+ * Here are some comparisons between RF24Network and ZigBee.
+ *
+ * @li Both networks support Star and Tree topologies.  Only Zigbee supports a true mesh.
+ * @li In both networks, only leaf nodes can sleep (see @ref NodeNames).
+ * @li ZigBee nodes are configured using AT commands, or a separate Windows application. 
+ * RF24 nodes are configured by recompiliing the firmware or writing to EEPROM.
+ *
+ * @section NodeNames Node Naming
+ *
+ * @li Leaf node: A node at the outer edge of the network with no children.  ZigBee calls it
+ * an End Device node.
+ * @li Relay node: A node which has both parents and children, and relays messages from one
+ * to the other.  ZigBee calls it a Router.
+ * @li Base node.  The top of the tree node with no parents, only children.  Typically this node
+ * will bridge to another kind of network like Ethernet.  ZigBee calls it a Co-ordinator node.
+ */
+
+#endif // __RF24NETWORK_H__
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/RF24Network_config.h b/hardware/digistump/sam/libraries/RF24Network/RF24Network_config.h
new file mode 100644
index 0000000..b86f37a
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/RF24Network_config.h
@@ -0,0 +1,72 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef __RF24_CONFIG_H__
+#define __RF24_CONFIG_H__
+
+#if ARDUINO < 100
+#include 
+#else
+#include 
+#endif
+
+#include 
+
+// Stuff that is normally provided by Arduino
+#ifndef ARDUINO
+#include 
+#include 
+#include 
+extern HardwareSPI SPI;
+#define _BV(x) (1<<(x))
+#endif
+
+// Define _BV for non-Arduino platforms and for Arduino DUE
+#if ! defined(ARDUINO) || (defined(ARDUINO) && defined(__arm__))
+	#define _BV(x) (1<<(x))
+#endif
+
+#undef SERIAL_DEBUG
+#ifdef SERIAL_DEBUG
+#define IF_SERIAL_DEBUG(x) ({x;})
+#else
+#define IF_SERIAL_DEBUG(x)
+#endif
+
+// Avoid spurious warnings
+// Arduino DUE is arm and uses traditional PROGMEM constructs
+#if ! defined( NATIVE ) && defined( ARDUINO ) && ! defined(__arm__)
+	#undef PROGMEM
+	#define PROGMEM __attribute__(( section(".progmem.data") ))
+	#undef PSTR
+	#define PSTR(s) (__extension__({static const char __c[] PROGMEM = (s); &__c[0];}))
+#endif
+
+// Progmem is Arduino-specific
+// Arduino DUE is arm and does not include avr/pgmspace
+#if defined(ARDUINO) && ! defined(__arm__)
+	#include 
+	#define PRIPSTR "%S"
+#else
+	#if ! defined(ARDUINO) // This doesn't work on Arduino DUE
+		typedef char const char;
+	#else // Fill in pgm_read_byte that is used, but missing from DUE
+		#define pgm_read_byte(addr) (*(const unsigned char *)(addr))
+	#endif
+
+	typedef uint16_t prog_uint16_t;
+	#define PSTR(x) (x)
+	#define printf_P printf
+	#define strlen_P strlen
+	#define PROGMEM
+	#define pgm_read_word(p) (*(p)) 
+	#define PRIPSTR "%s"
+#endif
+
+#endif // __RF24_CONFIG_H__
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/Sync.cpp b/hardware/digistump/sam/libraries/RF24Network/Sync.cpp
new file mode 100644
index 0000000..b31e956
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/Sync.cpp
@@ -0,0 +1,93 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+// STL headers
+// C headers
+#include 
+// Framework headers
+// Library headers
+#include 
+// Project headers
+// This component's header
+#include 
+
+/****************************************************************************/
+
+void Sync::update(void)
+{
+  // Pump the network
+  network.update();
+
+  // Look for changes to the data
+  uint8_t message[32];
+  uint8_t *mptr = message;
+  unsigned at = 0;
+  while ( at < len )
+  {
+    if ( app_data && internal_data && app_data[at] != internal_data[at] )
+    {
+      // Compose a message with the deltas
+      *mptr++ = at + 1;
+      *mptr++ = app_data[at];
+
+      // Update our internal view
+      internal_data[at] = app_data[at];
+    }
+    ++at;
+  }
+  // Zero out the remainder
+  while ( at++ < sizeof(message) )
+    *mptr++ = 0;
+
+  // If changes, send a message
+  if ( *message )
+  {
+    // TODO handle the case where this has to be broken into
+    // multiple messages
+    RF24NetworkHeader header(/*to node*/ to_node, /*type*/ 'S' /*Sync*/);
+    network.write(header,message,sizeof(message));
+  }
+
+  // Look for messages from the network
+  // Is there anything ready for us?
+  if ( network.available() )
+  {
+    // If so, take a look at it
+    RF24NetworkHeader header;
+    network.peek(header);
+
+    switch (header.type)
+    {
+    case 'S':
+      IF_SERIAL_DEBUG(printf_P(PSTR("%lu: SYN Received sync message\n\r"),millis()));
+
+      network.read(header,&message,sizeof(message));
+      // Parse the message and update the vars
+      mptr = message;
+      at = 0;
+      while ( mptr < message + sizeof(message) )
+      {
+        // A '0' in the first position means we are done
+        if ( !*mptr )
+          break;
+        uint8_t pos = (*mptr++) - 1;
+        uint8_t val = *mptr++;
+
+        IF_SERIAL_DEBUG(printf_P(PSTR("%lu: SYN Updated position %u to value %u\n\r"),millis(),pos,val));
+
+        app_data[pos] = val;
+        internal_data[pos] = val;
+      }
+      break;
+    default:
+      // Leave other messages for the app
+      break;
+    };
+  }
+}
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/Sync.h b/hardware/digistump/sam/libraries/RF24Network/Sync.h
new file mode 100644
index 0000000..701bebb
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/Sync.h
@@ -0,0 +1,85 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef __SYNC_H__
+#define __SYNC_H__
+
+// STL headers
+// C headers
+#include 
+#include 
+// Framework headers
+// Library headers
+#include 
+// Project headers
+
+class RF24Network;
+
+/**
+ * Synchronizes a shared set of variables between multiple nodes
+ */
+
+class Sync
+{
+private:
+  RF24Network& network;
+  uint8_t* app_data; /**< Application's copy of the data */
+  uint8_t* internal_data; /**< Our copy of the data */
+  size_t len; /**< Length of the data in bytes */
+  uint16_t to_node; /**< The other node we're syncing with */
+
+protected:
+public:
+  /**
+   * Constructor
+   *
+   * @param _network Which network to syncrhonize over
+   */
+  Sync(RF24Network& _network): network(_network), app_data(NULL),
+    internal_data(NULL), len(0), to_node(0)
+  {
+  }
+  /**
+   * Begin the object
+   *
+   * @param _to_node Which node we are syncing with
+   */
+  void begin(uint16_t _to_node)
+  {
+    to_node = _to_node;
+  }
+  /**
+   * Declare the shared data set
+   *
+   * @param _data Location of shared data to be syncrhonized
+   */
+  template 
+  void register_me(T& _data)
+  {
+    app_data = reinterpret_cast(&_data);
+    len = sizeof(_data);
+    internal_data = reinterpret_cast(malloc(len));
+    reset();
+  }
+
+  /**
+   * Reset the internal copy of the shared data set 
+   */
+  void reset(void)
+  {
+    memcpy(internal_data,app_data,len);
+  }
+  
+  /**
+   * Update the network and the shared data set
+   */
+  void update(void);
+};
+
+#endif // __SYNC_H__
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/Jamfile b/hardware/digistump/sam/libraries/RF24Network/examples/Jamfile
new file mode 100644
index 0000000..495a602
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/Jamfile
@@ -0,0 +1,6 @@
+SubDir TOP libraries RF24Network examples sensornet ;
+
+LOCATE_SOURCE = $(SUBDIR)/$(PINS) ;
+LOCATE_TARGET = $(SUBDIR)/$(PINS) ;
+
+ArduinoWithLibs Main : RF24Network RF24 Tictocs SPI ;
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_rx/.gitignore b/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_rx/.gitignore
new file mode 100644
index 0000000..d0d1cc9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_rx/.gitignore
@@ -0,0 +1,4 @@
+version.h
+output/
+ojam/
+.*.swp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_rx/Jamfile b/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_rx/Jamfile
new file mode 100644
index 0000000..e436fc7
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_rx/Jamfile
@@ -0,0 +1,6 @@
+SubDir TOP libraries RF24Network examples helloworld_rx ;
+
+LOCATE_SOURCE = $(SUBDIR)/$(PINS) ;
+LOCATE_TARGET = $(SUBDIR)/$(PINS) ;
+
+ArduinoWithLibs Main : RF24Network RF24 Tictocs SPI ;
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_rx/helloworld_rx.pde b/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_rx/helloworld_rx.pde
new file mode 100644
index 0000000..8097462
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_rx/helloworld_rx.pde
@@ -0,0 +1,67 @@
+/*
+ Copyright (C) 2012 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Simplest possible example of using RF24Network,
+ *
+ * RECEIVER NODE
+ * Listens for messages from the transmitter and prints them out.
+ */
+
+#include 
+#include 
+#include 
+
+// nRF24L01(+) radio attached using Getting Started board 
+RF24 radio(9,10);
+
+// Network uses that radio
+RF24Network network(radio);
+
+// Address of our node
+const uint16_t this_node = 0;
+
+// Address of the other node
+const uint16_t other_node = 1;
+
+// Structure of our payload
+struct payload_t
+{
+  unsigned long ms;
+  unsigned long counter;
+};
+
+void setup(void)
+{
+  Serial.begin(57600);
+  Serial.println("RF24Network/examples/helloworld_rx/");
+ 
+  SPI.begin();
+  radio.begin();
+  network.begin(/*channel*/ 90, /*node address*/ this_node);
+}
+
+void loop(void)
+{
+  // Pump the network regularly
+  network.update();
+
+  // Is there anything ready for us?
+  while ( network.available() )
+  {
+    // If so, grab it and print it out
+    RF24NetworkHeader header;
+    payload_t payload;
+    network.read(header,&payload,sizeof(payload));
+    Serial.print("Received packet #");
+    Serial.print(payload.counter);
+    Serial.print(" at ");
+    Serial.println(payload.ms);
+  }
+}
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_tx/.gitignore b/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_tx/.gitignore
new file mode 100644
index 0000000..d0d1cc9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_tx/.gitignore
@@ -0,0 +1,4 @@
+version.h
+output/
+ojam/
+.*.swp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_tx/Jamfile b/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_tx/Jamfile
new file mode 100644
index 0000000..6809b1b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_tx/Jamfile
@@ -0,0 +1,6 @@
+SubDir TOP libraries RF24Network examples helloworld_tx ;
+
+LOCATE_SOURCE = $(SUBDIR)/$(PINS) ;
+LOCATE_TARGET = $(SUBDIR)/$(PINS) ;
+
+ArduinoWithLibs Main : RF24Network RF24 Tictocs SPI ;
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_tx/helloworld_tx.pde b/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_tx/helloworld_tx.pde
new file mode 100644
index 0000000..34e1b9a
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/helloworld_tx/helloworld_tx.pde
@@ -0,0 +1,79 @@
+/*
+ Copyright (C) 2012 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Simplest possible example of using RF24Network 
+ *
+ * TRANSMITTER NODE
+ * Every 2 seconds, send a payload to the receiver node.
+ */
+
+#include 
+#include 
+#include 
+
+// nRF24L01(+) radio attached using Getting Started board 
+RF24 radio(9,10);
+
+// Network uses that radio
+RF24Network network(radio);
+
+// Address of our node
+const uint16_t this_node = 1;
+
+// Address of the other node
+const uint16_t other_node = 0;
+
+// How often to send 'hello world to the other unit
+const unsigned long interval = 2000; //ms
+
+// When did we last send?
+unsigned long last_sent;
+
+// How many have we sent already
+unsigned long packets_sent;
+
+// Structure of our payload
+struct payload_t
+{
+  unsigned long ms;
+  unsigned long counter;
+};
+
+void setup(void)
+{
+  Serial.begin(57600);
+  Serial.println("RF24Network/examples/helloworld_tx/");
+ 
+  SPI.begin();
+  radio.begin();
+  network.begin(/*channel*/ 90, /*node address*/ this_node);
+}
+
+void loop(void)
+{
+  // Pump the network regularly
+  network.update();
+
+  // If it's time to send a message, send it!
+  unsigned long now = millis();
+  if ( now - last_sent >= interval  )
+  {
+    last_sent = now;
+
+    Serial.print("Sending...");
+    payload_t payload = { millis(), packets_sent++ };
+    RF24NetworkHeader header(/*to node*/ other_node);
+    bool ok = network.write(header,&payload,sizeof(payload));
+    if (ok)
+      Serial.println("ok.");
+    else
+      Serial.println("failed.");
+  }
+}
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/maple/Jamfile b/hardware/digistump/sam/libraries/RF24Network/examples/maple/Jamfile
new file mode 100644
index 0000000..207c8fd
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/maple/Jamfile
@@ -0,0 +1,12 @@
+SubDir TOP ;
+
+# Set up output directories
+LOCATE_TARGET	= $(SEARCH_SOURCE)/out/$(TOOLSET) ;
+LOCATE_SOURCE	= $(LOCATE_TARGET) ;
+
+# Pull in local libraries
+SKETCH_LIBS	+= RF24Network RF24 ;
+HDRS		+= $(HOME)/Source/Arduino/libraries/$(SKETCH_LIBS) ;
+
+# Main output executable
+Maple $(SEARCH_SOURCE:B).elf : [ GLOB $(SEARCH_SOURCE) $(HOME)/Source/Arduino/libraries/$(SKETCH_LIBS) : $(MODULE_EXT) ] ;
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/maple/Jamrules b/hardware/digistump/sam/libraries/RF24Network/examples/maple/Jamrules
new file mode 100644
index 0000000..1531cfb
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/maple/Jamrules
@@ -0,0 +1,237 @@
+MCU		= cortex-m3 ;
+CHIP		= STM32F103ZE ;
+BOARD		= maple_native ;
+
+#CHIP		= at91sam3u4 ;
+#BOARD		= sam3u-ek ;
+
+if ! $(TOOLSET)
+{
+	TOOLSET = mix ;
+	Echo "Assuming TOOLSET=mix" ;
+}
+else if $(TOOLSET) = cs
+{
+	TOOLS_PATH	= /opt/cs/arm/bin ;
+	TOOLS_ARCH	= arm-none-eabi- ;
+}
+else if $(TOOLSET) = yagarto
+{
+	TOOLS_PATH	= ~/Source/yagarto-4.6.2/bin ;
+	TOOLS_ARCH	= arm-none-eabi- ;
+}
+if $(TOOLSET) = yagarto-install
+{
+	TOOLS_PATH	= ~/Source/yagarto/install/bin ;
+	TOOLS_ARCH	= arm-none-eabi- ;
+}
+else if $(TOOLSET) = devkit
+{
+	TOOLS_PATH	= /opt/devkitARM/bin ;
+	TOOLS_ARCH	= arm-eabi- ;
+}
+else if $(TOOLSET) = maple
+{
+	TOOLS_PATH	= /opt/Maple/Resources/Java/hardware/tools/arm/bin ; 
+	TOOLS_ARCH	= arm-none-eabi- ;
+	LINK_DIR	= /opt/Maple/Resources/Java/hardware/leaflabs/cores/maple ;
+	MAPLE_DIR	= /opt/Maple/Resources/Java/hardware/leaflabs/cores/maple ;
+	MAPLE_SUBDIRS	= . ;
+}
+else if $(TOOLSET) = mix
+{
+	TOOLS_PATH	= /opt/Maple/Resources/Java/hardware/tools/arm/bin ; 
+	TOOLS_ARCH	= arm-none-eabi- ;
+	LINKFLAGS	+= --print-gc-sections ;
+}
+else if $(TOOLSET) = ports
+{
+	TOOLS_PATH	= /opt/local/bin ;
+	TOOLS_ARCH	= arm-none-eabi- ;
+}
+
+# Tool locations
+
+CC	  	= $(TOOLS_PATH)/$(TOOLS_ARCH)gcc ;
+C++	 	= $(TOOLS_PATH)/$(TOOLS_ARCH)g++ ;
+AS	  	= $(TOOLS_PATH)/$(TOOLS_ARCH)gcc -c ;
+LINK	  	= $(TOOLS_PATH)/$(TOOLS_ARCH)g++ ;
+OBJCOPY 	= $(TOOLS_PATH)/$(TOOLS_ARCH)objcopy ;
+DFU		= dfu-util ;
+
+# Flags
+
+DEFINES  	+= VECT_TAB_FLASH BOARD_$(BOARD) MCU_$(CHIP) ERROR_LED_PORT=GPIOC ERROR_LED_PIN=15 STM32_HIGH_DENSITY MAPLE_IDE ;
+OPTIM		= -Os ;
+MFLAGS		= cpu=$(MCU) thumb arch=armv7-m ;
+CCFLAGS  	= -Wall -m$(MFLAGS) -g -nostdlib -ffunction-sections -fdata-sections -Wl,--gc-sections ;
+C++FLAGS  	= $(CCFLAGS) -fno-rtti -fno-exceptions ; 
+LINKFLAGS  	+= -m$(MFLAGS) -Xlinker --gc-sections ;
+DFUFLAGS	= -a1 -d 0x1eaf:0x0003 -R ;
+
+# Directories
+
+MAPLE_DIR	?= /opt/libmaple ;
+MAPLE_LIBS	= Servo LiquidCrystal Wire FreeRTOS ;
+MAPLE_SUBDIRS	?= libmaple libmaple/usb libmaple/usb/usb_lib wirish wirish/comm wirish/boards ; 
+
+SKETCH_DIR	= $(HOME)/Source/Maple ;
+
+CORE_DIRS	= $(MAPLE_DIR)/$(MAPLE_SUBDIRS) $(MAPLE_DIR)/libraries/$(MAPLE_LIBS) ;
+HDRS		= $(CORE_DIRS) ;
+
+# Modules
+MODULE_EXT	= *.c *.cpp *.S *.pde *.ino *.test ;
+CORE_MODULES	= [ GLOB $(CORE_DIRS) : $(MODULE_EXT) ] ; 
+
+# Unit test framework
+CXXTEST_DIR	= $(HOME)/Source/cxxtest ;
+#CXXTEST_GEN	= $(CXXTEST_DIR)/cxxtestgen.py ;
+CXXTEST_GEN	= $(CXXTEST_DIR)/python/scripts/cxxtestgen ;
+HDRS		+= $(CXXTEST_DIR) ;
+
+# Linker script
+LINK_DIR	?= $(MAPLE_DIR)/support/ld ;
+LINKSCRIPT	= $(LINK_DIR)/$(BOARD)/flash.ld ; 
+LINKFLAGS 	+= -T$(LINKSCRIPT) -L$(LINK_DIR) ;
+
+rule Pde
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+if ( $(ARDUINO_VERSION) < 100 )
+{
+	ARDUINO_H = WProgram.h ;
+}
+else
+{
+	ARDUINO_H = Arduino.h ;
+}
+
+actions Pde
+{
+	echo "#include <$(ARDUINO_H)>" > $(<) 
+	echo "#line 1 \"$(>)\"" >> $(<)
+	cat $(>) >> $(<) 
+}
+
+rule C++Pde
+{
+	local _CPP = $(>:B).cpp ;
+	Pde $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule TestSuite
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+actions TestSuite
+{
+	$(CXXTEST_GEN) --part $(>) > $(<)
+}
+
+rule TestRoot
+{
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+}
+
+actions TestRoot
+{
+	$(CXXTEST_GEN) --root --error-printer > $(<)
+}
+
+rule C++TestSuite
+{
+	local _CPP = $(>:B).cpp ;
+	TestSuite $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule Hex
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends hex : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Hex
+{
+	$(OBJCOPY) -O ihex $(>) $(<)
+}
+
+rule Binary
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends binary : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Binary
+{
+	$(OBJCOPY) -O binary $(>) $(<)
+}
+
+rule UserObject
+{
+	switch $(>:S)
+	{
+		case .S : As $(<) : $(>) ;
+		case .ino : C++Pde $(<) : $(>) ;
+		case .pde : C++Pde $(<) : $(>) ;
+		case .test : C++TestSuite $(<) : $(>) ;
+	}
+}
+
+rule Upload
+{
+	Depends up : $(<) ;
+	NotFile up ;
+	Always $(<) ;
+	Always up ;
+}
+
+actions Upload
+{
+	$(DFU) $(DFUFLAGS)  -D $(<)
+}
+
+# Override base objects rule, so all output can go in the output dir
+rule Objects
+{
+        local _i ;
+
+        for _i in [ FGristFiles $(<) ]
+        {
+		local _b = $(_i:B)$(SUFOBJ) ;
+		local _o = $(_b:G=$(SOURCE_GRIST:E)) ;
+                Object $(_o) : $(_i) ;
+                Depends obj : $(_o) ;
+        }
+}
+
+# Override base main rule, so all output can go in the output dir
+rule Main
+{
+	# Bring in the map
+	LINKFLAGS on $(<) = $(LINKFLAGS) -Wl,-Map=$(LOCATE_TARGET)/$(<:B).map ;
+
+	MakeLocate $(<) ;
+        MainFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+        Objects $(>) ;
+}
+
+rule Maple
+{
+	Main $(<) : $(>) $(CORE_MODULES) ; 
+	Binary $(<:B).bin : $(<) ;
+	Upload $(<:B).bin ;
+}
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/maple/helloworld_tx.pde b/hardware/digistump/sam/libraries/RF24Network/examples/maple/helloworld_tx.pde
new file mode 100644
index 0000000..bae72e4
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/maple/helloworld_tx.pde
@@ -0,0 +1,106 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Simplest possible example of using RF24Network 
+ *
+ * TRANSMITTER NODE
+ * Every 2 seconds, says hello to the receiver node.
+ */
+
+#include 
+#include 
+#include 
+
+//
+// Maple specific setup.  Other than this section, the sketch is the same on Maple as on
+// Arduino
+//
+
+#ifdef MAPLE_IDE
+
+// External startup function
+extern void board_start(const char* program_name);
+
+// Use SPI #2.
+HardwareSPI SPI(2);
+
+inline void serial_begin(int _baud)
+{
+}
+#else
+inline void serial_begin(int _baud)
+{
+  Serial.begin(_baud);
+}
+#define board_startup printf
+#define toggleLED(x) (x)
+#endif
+
+//
+// Hardware configuration
+//
+
+// Set up nRF24L01 radio on SPI bus plus pins 7 & 6
+// (This works for the Getting Started board plugged into the
+// Maple Native backwards.)
+
+RF24 radio(7,6);
+
+// Network uses that radio
+RF24Network network(radio);
+
+// Address of our node
+const uint16_t this_node = 1;
+
+// Address of the other node
+const uint16_t other_node = 0;
+
+// How often to send 'hello world to the other unit
+const unsigned long interval = 2000; //ms
+
+// When did we last send?
+unsigned long last_sent;
+
+void setup(void)
+{
+  serial_begin(57600);
+  board_start("RF24Network/examples/helloworld_tx/");
+ 
+  SPI.begin();
+  radio.begin();
+  network.begin(/*channel*/ 90, /*node address*/ this_node);
+}
+
+void loop(void)
+{
+  // Pump the network regularly
+  network.update();
+
+  // If it's time to send a message, send it!
+  unsigned long now = millis();
+  if ( now - last_sent > interval  )
+  {
+    last_sent = now;
+
+    toggleLED();
+    printf("Sending...\r\n");
+    const char* hello = "Hello, world!";
+    RF24NetworkHeader header(/*to node*/ other_node);
+    bool ok = network.write(header,hello,strlen(hello));
+    if (ok)
+      printf("\tok.\r\n");
+    else
+    {
+      printf("\tfailed.\r\n");
+      delay(250); // extra delay on fail to keep light on longer
+    }
+    toggleLED();
+  }
+}
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/maple/main.cpp b/hardware/digistump/sam/libraries/RF24Network/examples/maple/main.cpp
new file mode 100644
index 0000000..1e03125
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/maple/main.cpp
@@ -0,0 +1,77 @@
+#ifdef MAPLE_IDE
+
+#include 
+#include "wirish.h"
+
+extern void setup(void);
+extern void loop(void);
+
+void board_start(const char* program_name)
+{
+  // Set up the LED to steady on
+  pinMode(BOARD_LED_PIN, OUTPUT);
+  digitalWrite(BOARD_LED_PIN, HIGH);
+
+  // Setup the button as input
+  pinMode(BOARD_BUTTON_PIN, INPUT);
+  digitalWrite(BOARD_BUTTON_PIN, HIGH);
+
+  SerialUSB.begin();
+  SerialUSB.println("Press BUT");
+
+  // Wait for button press
+  while ( !isButtonPressed() )
+  {
+  }
+
+  SerialUSB.println("Welcome!");
+  SerialUSB.println(program_name);
+
+  int i = 11;
+  while (i--)
+  {
+    toggleLED();
+    delay(50);
+  }
+}
+
+/**
+ * Custom version of _write, which will print to the USB.
+ * In order to use it you MUST ADD __attribute__((weak))
+ * to _write in libmaple/syscalls.c
+*/
+extern "C" int _write(int file, char * ptr, int len)
+{
+  if ( (file != 1) && (file != 2) )
+    return 0; 
+  else
+    SerialUSB.write(ptr,len);
+  return len;
+}
+
+__attribute__((constructor)) __attribute__ ((weak)) void premain()
+{
+  init();
+}
+
+__attribute__((weak)) void setup(void)
+{
+  board_start("No program defined");
+}
+
+__attribute__((weak)) void loop(void)
+{
+}
+
+__attribute__((weak)) int main(void)
+{
+  setup();
+
+  while (true)
+  {
+    loop();
+  }
+  return 0;
+}
+#endif // ifdef MAPLE_IDE
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/meshping/.gitignore b/hardware/digistump/sam/libraries/RF24Network/examples/meshping/.gitignore
new file mode 100644
index 0000000..d0d1cc9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/meshping/.gitignore
@@ -0,0 +1,4 @@
+version.h
+output/
+ojam/
+.*.swp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/meshping/Jamfile b/hardware/digistump/sam/libraries/RF24Network/examples/meshping/Jamfile
new file mode 100644
index 0000000..6ded8d3
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/meshping/Jamfile
@@ -0,0 +1,6 @@
+SubDir TOP libraries RF24Network examples meshping ;
+
+LOCATE_SOURCE = $(SUBDIR)/$(PINS) ;
+LOCATE_TARGET = $(SUBDIR)/$(PINS) ;
+
+ArduinoWithLibs Main : RF24Network RF24 Tictocs SPI ;
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/meshping/meshping.pde b/hardware/digistump/sam/libraries/RF24Network/examples/meshping/meshping.pde
new file mode 100644
index 0000000..ccb543d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/meshping/meshping.pde
@@ -0,0 +1,260 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example of pinging across a mesh network
+ *
+ * Using this sketch, each node will send a ping to every other node
+ * in the network every few seconds. 
+ * The RF24Network library will route the message across
+ * the mesh to the correct node.
+ *
+ * This sketch is greatly complicated by the fact that at startup time, each
+ * node (including the base) has no clue what nodes are alive.  So,
+ * each node builds an array of nodes it has heard about.  The base
+ * periodically sends out its whole known list of nodes to everyone.
+ *
+ * To see the underlying frames being relayed, compile RF24Network with
+ * #define SERIAL_DEBUG.
+ *
+ * The logical node address of each node is set in EEPROM.  The nodeconfig
+ * module handles this by listening for a digit (0-9) on the serial port,
+ * and writing that number to EEPROM.
+ *
+ * To use the sketch, upload it to two or more units.  Run each one in
+ * turn.  Attach a serial monitor, and send a single-digit address to
+ * each.  Make the first one '0', and the following units '1', '2', etc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include "nodeconfig.h"
+#include "printf.h"
+
+// This is for git version tracking.  Safe to ignore
+#ifdef VERSION_H
+#include "version.h"
+#else
+#define __TAG__ "Unknown"
+#endif
+
+// nRF24L01(+) radio using the Getting Started board
+RF24 radio(9,10);
+RF24Network network(radio);
+
+// Our node address
+uint16_t this_node;
+
+// Delay manager to send pings regularly
+const unsigned long interval = 2000; // ms
+unsigned long last_time_sent;
+
+// Array of nodes we are aware of
+const short max_active_nodes = 10;
+uint16_t active_nodes[max_active_nodes];
+short num_active_nodes = 0;
+short next_ping_node_index = 0;
+
+// Prototypes for functions to send & handle messages
+bool send_T(uint16_t to);
+bool send_N(uint16_t to);
+void handle_T(RF24NetworkHeader& header);
+void handle_N(RF24NetworkHeader& header);
+void add_node(uint16_t node);
+
+void setup(void)
+{
+  //
+  // Print preamble
+  //
+  
+  Serial.begin(57600);
+  printf_begin();
+  printf_P(PSTR("\n\rRF24Network/examples/meshping/\n\r"));
+  printf_P(PSTR("VERSION: " __TAG__ "\n\r"));
+  
+  //
+  // Pull node address out of eeprom 
+  //
+
+  // Which node are we?
+  this_node = nodeconfig_read();
+
+  //
+  // Bring up the RF network
+  //
+
+  SPI.begin();
+  radio.begin();
+  network.begin(/*channel*/ 100, /*node address*/ this_node );
+}
+
+void loop(void)
+{
+  // Pump the network regularly
+  network.update();
+
+  // Is there anything ready for us?
+  while ( network.available() )
+  {
+    // If so, take a look at it 
+    RF24NetworkHeader header;
+    network.peek(header);
+
+    // Dispatch the message to the correct handler.
+    switch (header.type)
+    {
+    case 'T':
+      handle_T(header);
+      break;
+    case 'N':
+      handle_N(header);
+      break;
+    default:
+      printf_P(PSTR("*** WARNING *** Unknown message type %c\n\r"),header.type);
+      network.read(header,0,0);
+      break;
+    };
+  }
+
+  // Send a ping to the next node every 'interval' ms
+  unsigned long now = millis();
+  if ( now - last_time_sent >= interval )
+  {
+    last_time_sent = now;
+
+    // Who should we send to?
+    // By default, send to base
+    uint16_t to = 00;
+    
+    // Or if we have active nodes,
+    if ( num_active_nodes )
+    {
+      // Send to the next active node
+      to = active_nodes[next_ping_node_index++];
+      
+      // Have we rolled over?
+      if ( next_ping_node_index > num_active_nodes )
+      {
+	// Next time start at the beginning
+	next_ping_node_index = 0;
+
+	// This time, send to node 00.
+	to = 00;
+      }
+    }
+
+    bool ok;
+
+    // Normal nodes send a 'T' ping
+    if ( this_node > 00 || to == 00 )
+      ok = send_T(to);
+    
+    // Base node sends the current active nodes out
+    else
+      ok = send_N(to);
+
+    // Notify us of the result
+    if (ok)
+    {
+      printf_P(PSTR("%lu: APP Send ok\n\r"),millis());
+    }
+    else
+    {
+      printf_P(PSTR("%lu: APP Send failed\n\r"),millis());
+
+      // Try sending at a different time next time
+      last_time_sent -= 100;
+    }
+  }
+
+  // Listen for a new node address
+  nodeconfig_listen();
+}
+
+/**
+ * Send a 'T' message, the current time
+ */
+bool send_T(uint16_t to)
+{
+  RF24NetworkHeader header(/*to node*/ to, /*type*/ 'T' /*Time*/);
+  
+  // The 'T' message that we send is just a ulong, containing the time
+  unsigned long message = millis();
+  printf_P(PSTR("---------------------------------\n\r"));
+  printf_P(PSTR("%lu: APP Sending %lu to 0%o...\n\r"),millis(),message,to);
+  return network.write(header,&message,sizeof(unsigned long));
+}
+
+/**
+ * Send an 'N' message, the active node list
+ */
+bool send_N(uint16_t to)
+{
+  RF24NetworkHeader header(/*to node*/ to, /*type*/ 'N' /*Time*/);
+  
+  printf_P(PSTR("---------------------------------\n\r"));
+  printf_P(PSTR("%lu: APP Sending active nodes to 0%o...\n\r"),millis(),to);
+  return network.write(header,active_nodes,sizeof(active_nodes));
+}
+
+/**
+ * Handle a 'T' message
+ *
+ * Add the node to the list of active nodes
+ */
+void handle_T(RF24NetworkHeader& header)
+{
+  // The 'T' message is just a ulong, containing the time
+  unsigned long message;
+  network.read(header,&message,sizeof(unsigned long));
+  printf_P(PSTR("%lu: APP Received %lu from 0%o\n\r"),millis(),message,header.from_node);
+
+  // If this message is from ourselves or the base, don't bother adding it to the active nodes.
+  if ( header.from_node != this_node || header.from_node > 00 )
+    add_node(header.from_node);
+}
+
+/**
+ * Handle an 'N' message, the active node list
+ */
+void handle_N(RF24NetworkHeader& header)
+{
+  static uint16_t incoming_nodes[max_active_nodes];
+
+  network.read(header,&incoming_nodes,sizeof(incoming_nodes));
+  printf_P(PSTR("%lu: APP Received nodes from 0%o\n\r"),millis(),header.from_node);
+
+  int i = 0;
+  while ( i < max_active_nodes && incoming_nodes[i] > 00 )
+    add_node(incoming_nodes[i++]);
+}
+
+/**
+ * Add a particular node to the current list of active nodes
+ */
+void add_node(uint16_t node)
+{
+  // Do we already know about this node?
+  short i = num_active_nodes;
+  while (i--)
+  {
+    if ( active_nodes[i] == node )
+      break;
+  }
+  // If not, add it to the table
+  if ( i == -1 && num_active_nodes < max_active_nodes )
+  {
+    active_nodes[num_active_nodes++] = node; 
+    printf_P(PSTR("%lu: APP Added 0%o to list of active nodes.\n\r"),millis(),node);
+  }
+}
+
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/meshping/nodeconfig.cpp b/hardware/digistump/sam/libraries/RF24Network/examples/meshping/nodeconfig.cpp
new file mode 100644
index 0000000..3dfe19f
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/meshping/nodeconfig.cpp
@@ -0,0 +1,69 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#include "RF24Network_config.h"
+#include 
+#include 
+#include "nodeconfig.h"
+
+// Where in EEPROM is the address stored?
+uint8_t* address_at_eeprom_location = (uint8_t*)10;
+
+// What flag value is stored there so we know the value is valid?
+const uint8_t valid_eeprom_flag = 0xdf;
+
+// What are the actual node values that we want to use?
+// EEPROM locations are actually just indices into this array
+const uint16_t node_address_set[10] = { 00, 02, 05, 012, 015, 022, 025, 032, 035, 045 };
+
+uint8_t nodeconfig_read(void)
+{
+  uint8_t result = 0;
+
+  // Look for the token in EEPROM to indicate the following value is
+  // a validly set node address 
+  if ( eeprom_read_byte(address_at_eeprom_location) == valid_eeprom_flag )
+  {
+    // Read the address from EEPROM
+    result = node_address_set[ eeprom_read_byte(address_at_eeprom_location+1) ];
+    printf_P(PSTR("ADDRESS: %u\n\r"),result);
+  }
+  else
+  {
+    printf_P(PSTR("*** No valid address found.  Send 0-9 via serial to set node address\n\r"));
+    while(1)
+    {
+      nodeconfig_listen();
+    }
+  }
+  
+  return result;
+}
+
+void nodeconfig_listen(void)
+{
+  //
+  // Listen for serial input, which is how we set the address
+  //
+  if (Serial.available())
+  {
+    // If the character on serial input is in a valid range...
+    char c = Serial.read();
+    if ( c >= '0' && c <= '9' )
+    {
+      // It is our address
+      eeprom_write_byte(address_at_eeprom_location,valid_eeprom_flag);
+      eeprom_write_byte(address_at_eeprom_location+1,c-'0');
+
+      // And we are done right now (no easy way to soft reset)
+      printf_P(PSTR("\n\rManually reset index to: %c, address 0%o\n\rPress RESET to continue!"),c,node_address_set[c-'0']);
+      while(1);
+    }
+  }
+}
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/meshping/nodeconfig.h b/hardware/digistump/sam/libraries/RF24Network/examples/meshping/nodeconfig.h
new file mode 100644
index 0000000..4cfc602
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/meshping/nodeconfig.h
@@ -0,0 +1,15 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef __NODECONFIG_H__
+#define __NODECONFIG_H__
+
+uint8_t nodeconfig_read(void);
+void nodeconfig_listen(void);
+
+#endif // __NODECONFIG_H__
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/meshping/printf.h b/hardware/digistump/sam/libraries/RF24Network/examples/meshping/printf.h
new file mode 100644
index 0000000..b2efd56
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/meshping/printf.h
@@ -0,0 +1,37 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  fdevopen( &serial_putc, 0 );
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/.gitignore b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/.gitignore
new file mode 100644
index 0000000..d0d1cc9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/.gitignore
@@ -0,0 +1,4 @@
+version.h
+output/
+ojam/
+.*.swp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/DuinodeV1.h b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/DuinodeV1.h
new file mode 100644
index 0000000..5353d73
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/DuinodeV1.h
@@ -0,0 +1,30 @@
+#ifndef __DUINODE_V3_H__
+#define __DUINODE_V3_H__
+
+/**
+ * @file DuinodeV1.h
+ *
+ * Contains hardware definitions for RF Duinode V1 (3V3)
+ */
+
+#define PINS_DEFINED 1 
+#define __PLATFORM__ "RF Duinode V1 (3V3)"
+
+const int rf_irq = 0;
+
+const int led_red = 0;
+const int led_yellow = 0;
+const int led_green = 0;
+const int button_a = 0;
+
+const int rf_ce = 8;
+const int rf_csn = 9;
+
+const int temp_pin = 2; // analog
+const int voltage_pin = 3; // analog
+
+// 1.1V internal reference after 1M/470k divider, in 8-bit fixed point
+const unsigned voltage_reference = 0x371;
+
+#endif // __DUINODE_V3_H__
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/DuinodeV3.h b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/DuinodeV3.h
new file mode 100644
index 0000000..9e8422c
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/DuinodeV3.h
@@ -0,0 +1,30 @@
+#ifndef __DUINODE_V3_H__
+#define __DUINODE_V3_H__
+
+/**
+ * @file DuinodeV3.h
+ *
+ * Contains hardware definitions for RF Duinode V3 (2V4)
+ */
+
+#define PINS_DEFINED 1 
+#define __PLATFORM__ "RF Duinode V3/V4 (2V4)"
+
+const int rf_irq = 0;
+
+const int led_red = 3;
+const int led_yellow = 4;
+const int led_green = 5;
+const int button_a = 6;
+
+const int rf_ce = 8;
+const int rf_csn = 7;
+
+const int temp_pin = 2; // analog
+const int voltage_pin = 3; // analog
+
+// 1.1V internal reference after 1M/470k divider, in 8-bit fixed point
+const unsigned voltage_reference = 0x371;
+
+#endif // __DUINODE_V3_H__
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/DuinodeV5.h b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/DuinodeV5.h
new file mode 100644
index 0000000..6f3b236
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/DuinodeV5.h
@@ -0,0 +1,30 @@
+#ifndef __DUINODE_V5_H__
+#define __DUINODE_V5_H__
+
+/**
+ * @file DuinodeV3.h
+ *
+ * Contains hardware definitions for RF Duinode V5 (2V4)
+ */
+
+#define PINS_DEFINED 1 
+#define __PLATFORM__ "RF Duinode V5 (2V4)"
+
+const int rf_irq = 0;
+
+const int led_red = 3;
+const int led_yellow = 4;
+const int led_green = 5;
+const int button_a = 6;
+
+const int rf_ce = 14;
+const int rf_csn = 15;
+
+const int temp_pin = 2; // analog
+const int voltage_pin = 3; // analog
+
+// 1.1V internal reference after 1M/470k divider, in 8-bit fixed point
+const unsigned voltage_reference = 0x371;
+
+#endif // __DUINODE_V5_H__
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/Jamfile b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/Jamfile
new file mode 100644
index 0000000..495a602
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/Jamfile
@@ -0,0 +1,6 @@
+SubDir TOP libraries RF24Network examples sensornet ;
+
+LOCATE_SOURCE = $(SUBDIR)/$(PINS) ;
+LOCATE_TARGET = $(SUBDIR)/$(PINS) ;
+
+ArduinoWithLibs Main : RF24Network RF24 Tictocs SPI ;
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/S_message.cpp b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/S_message.cpp
new file mode 100644
index 0000000..f75bfb9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/S_message.cpp
@@ -0,0 +1,34 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+// STL headers
+// C headers
+// Framework headers
+// Library headers
+#include "RF24Network_config.h"
+// Project headers
+// This component's header
+#include "S_message.h"
+
+char S_message::buffer[32];
+
+/****************************************************************************/
+
+char* S_message::toString(void)
+{
+  snprintf(buffer,sizeof(buffer),"%2u.%02uC /%2u.%02uV",
+      temp_reading >> 8,
+      ( temp_reading & 0xFF ) * 100 / 256,
+      voltage_reading >> 8,
+      ( voltage_reading & 0xFF ) * 100 / 256
+      );
+  return buffer;
+}
+
+/****************************************************************************/
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/S_message.h b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/S_message.h
new file mode 100644
index 0000000..60a2645
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/S_message.h
@@ -0,0 +1,32 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef __S_MESSAGE_H__
+#define __S_MESSAGE_H__
+
+// STL headers
+// C headers
+// Framework headers
+// Library headers
+// Project headers
+
+/**
+ * Sensor message (type 'S') 
+ */
+
+struct S_message
+{
+  uint16_t temp_reading;
+  uint16_t voltage_reading;
+  static char buffer[];
+  S_message(void): temp_reading(0), voltage_reading(0) {}
+  char* toString(void);
+};
+
+#endif // __S_MESSAGE_H__
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/duinode1.sh b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/duinode1.sh
new file mode 100644
index 0000000..f768d97
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/duinode1.sh
@@ -0,0 +1 @@
+jam F_CPU=16000000 "CCFLAGS=-include DuinodeV1.h" -dx UPLOAD_SPEED=115200 u1 && screen /dev/ttyUSB1 57600
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/duinode3.sh b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/duinode3.sh
new file mode 100644
index 0000000..fe4194a
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/duinode3.sh
@@ -0,0 +1,3 @@
+AVR_BIN=/usr/local/avr/bin AVR_ETC=/usr/local/avr/etc jam F_CPU=8000000 sensornet.elf
+touch sensornet.pde
+AVR_BIN=/usr/local/avr/bin AVR_ETC=/usr/local/avr/etc jam F_CPU=8000000 "CCFLAGS=-include DuinodeV3.h" -dx UPLOAD_SPEED=57600 u1 && screen /dev/ttyUSB1 57600
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/duinode5.sh b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/duinode5.sh
new file mode 100644
index 0000000..f74ade5
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/duinode5.sh
@@ -0,0 +1 @@
+jam F_CPU=8000000 "CCFLAGS=-include DuinodeV5.h" -dx UPLOAD_SPEED=57600 u0 && picocom -b 57600 /dev/ttyUSB0
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/nodeconfig.cpp b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/nodeconfig.cpp
new file mode 100644
index 0000000..ff2be35
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/nodeconfig.cpp
@@ -0,0 +1,131 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#include "RF24Network_config.h"
+#include 
+#include 
+#include "nodeconfig.h"
+
+// Where in EEPROM is the address stored?
+uint8_t* address_at_eeprom_location = (uint8_t*)10;
+
+eeprom_info_t eeprom_info;
+
+const eeprom_info_t& nodeconfig_read(void)
+{
+  eeprom_read_block(&eeprom_info,address_at_eeprom_location,sizeof(eeprom_info));
+
+  // Look for the token in EEPROM to indicate the following value is
+  // a validly set node address 
+  if ( eeprom_info.isValid() ) 
+  {
+    printf_P(PSTR("ADDRESS: %o\n\r"),eeprom_info.address);
+    printf_P(PSTR("ROLE: %S\n\r"),eeprom_info.relay ? PSTR("Relay") : PSTR("Leaf") );
+    printf_P(PSTR("TEMP: %04x\n\r"),eeprom_info.temp_calibration); 
+  }
+  else
+  {
+    eeprom_info.clear();
+
+    printf_P(PSTR("*** No valid address found.  Send node address via serial of the form 011\n\r"));
+    while(1)
+    {
+      nodeconfig_listen();
+    }
+  }
+  
+  return eeprom_info;
+}
+
+char serialdata[10];
+char* nextserialat = serialdata;
+const char* maxserial = serialdata + sizeof(serialdata) - 1;
+
+void nodeconfig_listen(void)
+{
+  //
+  // Listen for serial input, which is how we set the address
+  //
+  if (Serial.available())
+  {
+    // If the character on serial input is in a valid range...
+    char c = tolower(Serial.read());
+    if ( (c >= '0' && c <= '9' ) || (c >= 'a' && c <= 'f' ) ) 
+    {
+      *nextserialat++ = c;
+      if ( nextserialat == maxserial )
+      {
+	*nextserialat = 0;
+	printf_P(PSTR("\r\n*** Unknown serial command: %s\r\n"),serialdata);
+	nextserialat = serialdata;
+      }
+    }
+    else if ( tolower(c) == 'r' )
+    {
+      eeprom_info.relay = true;
+      printf_P(PSTR("ROLE: %S\n\r"),eeprom_info.relay ? PSTR("Relay") : PSTR("Leaf") );
+      eeprom_update_block(&eeprom_info,address_at_eeprom_location,sizeof(eeprom_info));
+      printf_P(PSTR("RESET NODE before changes take effect\r\n"));
+      if ( ! eeprom_info.isValid() )
+	printf_P(PSTR("Please assign an address\r\n"));
+    }
+    else if ( tolower(c) == 'l' )
+    {
+      eeprom_info.relay = false;
+      printf_P(PSTR("ROLE: %S\n\r"),eeprom_info.relay ? PSTR("Relay") : PSTR("Leaf") );
+      eeprom_update_block(&eeprom_info,address_at_eeprom_location,sizeof(eeprom_info));
+      printf_P(PSTR("RESET NODE before changes take effect\r\n"));
+      if ( ! eeprom_info.isValid() )
+	printf_P(PSTR("Please assign an address\r\n"));
+    }
+    else if ( tolower(c) == 't' )
+    {
+      // Send temperature calibration as 2-digit 4.4-fixed decimal signed degrees
+      // celcius--followed by a 't'.  So, for -1.5 degrees, send "e8t".  Or for +2 degrees
+      // send "20t"
+
+      *nextserialat = 0;
+      int8_t val = strtol(serialdata,NULL,16);
+      nextserialat = serialdata;
+      
+      set_temp_calibration( val * 0x10 );
+      
+      printf_P(PSTR("RESET NODE before changes take effect\r\n"));
+      if ( ! eeprom_info.isValid() )
+	printf_P(PSTR("Please assign an address\r\n"));
+    }
+    else if ( c == 13 )
+    {
+      // Convert to octal
+      char *pc = serialdata;
+      uint16_t address = 0;
+      while ( pc < nextserialat )
+      {
+	address <<= 3;
+	address |= (*pc++ - '0');
+      }
+
+      // It is our address
+      eeprom_info.address = address;
+      eeprom_update_block(&eeprom_info,address_at_eeprom_location,sizeof(eeprom_info));
+
+      // And we are done right now (no easy way to soft reset)
+      printf_P(PSTR("\n\rManually set to address 0%o\n\rPress RESET to continue!"),address);
+      while(1);
+    }
+  }
+}
+
+void set_temp_calibration(int16_t val)
+{
+  eeprom_info.temp_calibration = val;
+  printf_P(PSTR("TEMP: %02x\n\r"),eeprom_info.temp_calibration);
+  eeprom_update_block(&eeprom_info,address_at_eeprom_location,sizeof(eeprom_info));
+}
+
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/nodeconfig.h b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/nodeconfig.h
new file mode 100644
index 0000000..99b26ae
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/nodeconfig.h
@@ -0,0 +1,49 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef __NODECONFIG_H__
+#define __NODECONFIG_H__
+
+// Additional info
+struct eeprom_info_t
+{
+  uint8_t flag;
+  uint16_t address;
+  int16_t temp_calibration;  // sensor adjustment in signed fixed-8.8 degrees, e.g. 0xFE80 is -1.5
+  bool relay:1;
+
+  static const uint8_t valid_flag = 0xdd;
+
+  eeprom_info_t()
+  {
+    clear();
+  }
+
+  bool isValid() const
+  {
+    return (flag == valid_flag) && (address != 0xffff);
+  }
+
+  void clear()
+  {
+    flag = valid_flag;
+    address = 0xffff;
+    relay = false;
+    temp_calibration = 0;
+  }
+
+};
+
+const eeprom_info_t& nodeconfig_read(void);
+void nodeconfig_listen(void);
+void set_temp_calibration(int16_t val);
+
+#endif // __NODECONFIG_H__
+
+// vim:ai:cin:sts=2 sw=2 ft=cpp
+
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/printf.h b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/printf.h
new file mode 100644
index 0000000..b2efd56
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/printf.h
@@ -0,0 +1,37 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+#ifdef ARDUINO
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  fdevopen( &serial_putc, 0 );
+}
+
+#else
+#error This example is only for use on Arduino.
+#endif // ARDUINO
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/sensornet.pde b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/sensornet.pde
new file mode 100644
index 0000000..1c61b02
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/sensornet.pde
@@ -0,0 +1,498 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Example of a sensor network 
+ *
+ * This sketch demonstrates how to use the RF24Network library to
+ * manage a set of low-power sensor nodes which mostly sleep but
+ * awake regularly to send readings to the base.
+ *
+ * The example uses TWO sensors, a 'temperature' sensor and a 'voltage'
+ * sensor.
+ *
+ * To see the underlying frames being relayed, compile RF24Network with
+ * #define SERIAL_DEBUG.
+ *
+ * The logical node address of each node is set in EEPROM.  The nodeconfig
+ * module handles this by listening for a digit (0-9) on the serial port,
+ * and writing that number to EEPROM.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "nodeconfig.h"
+#include "sleep.h"
+#include "S_message.h"
+#include "printf.h"
+
+// This is for git version tracking.  Safe to ignore
+#ifdef VERSION_H
+#include "version.h"
+#else
+#define __TAG__ "Unknown"
+#endif
+
+// Pin definitions
+#ifndef PINS_DEFINED
+#define __PLATFORM__ "Getting Started board"
+
+// Pins for radio
+const int rf_ce = 9;
+const int rf_csn = 10;
+
+// Pins for sensors
+const int temp_pin = A2;
+const int voltage_pin = A3;
+
+// Pins for status LED, or '0' for no LED connected
+const int led_red = 0; 
+const int led_yellow = 0; 
+const int led_green = 0; 
+
+// Button to control modes
+const int button_a = 4;
+
+// What voltage is a reading of 1023?
+const unsigned voltage_reference = 5 * 256; // 5.0V
+#endif
+
+RF24 radio(rf_ce,rf_csn);
+RF24Network network(radio);
+
+// Our node configuration 
+eeprom_info_t this_node;
+
+// Sleep constants.  In this example, the watchdog timer wakes up
+// every 4s, and every single wakeup we power up the radio and send
+// a reading.  In real use, these numbers which be much higher.
+// Try wdt_8s and 7 cycles for one reading per minute.> 1
+const wdt_prescalar_e wdt_prescalar = wdt_8s;
+const int sleep_cycles_per_transmission = 1;
+
+// Non-sleeping nodes need a timer to regulate their sending interval
+Timer send_timer(8000);
+
+// Button controls functionality of the unit
+Button ButtonA(button_a);
+
+// Long-press button
+Button ButtonLong(button_a,1000);
+
+/**
+ * Convenience class for handling LEDs.  Handles the case where the
+ * LED may not be populated on the board, so always checks whether
+ * the pin is valid before setting a value.
+ */
+
+class LED
+{
+private:
+  int pin;
+public:
+  LED(int _pin): pin(_pin)
+  {
+    if (pin > 0)
+    {
+      pinMode(pin,OUTPUT);
+      digitalWrite(pin,LOW);
+    }
+  }
+  void write(bool state) const
+  {
+    if (pin > 0)
+      digitalWrite(pin,state?HIGH:LOW);
+  }
+  void operator=(bool state)
+  {
+    write(state);
+  }
+
+};
+
+/**
+ * Startup LED sequence.  Lights up the LEDs in sequence first, then dims 
+ * them in the same sequence.
+ */
+
+class StartupLEDs: public Timer
+{
+private:
+  const LED** leds;
+  const LED** current;
+  const LED** end;
+  bool state;
+protected:
+  virtual void onFired(void)
+  {
+    (*current)->write(state);
+    ++current;
+    if ( current >= end )
+    {
+      if ( state )
+      {
+	state = false;
+	current = leds;
+      }
+      else
+	disable();
+    }
+  }
+public:
+  StartupLEDs(const LED** _leds, int _num): Timer(250), leds(_leds), current(_leds), end(_leds+_num), state(true)
+  {
+  }
+};
+
+/**
+ * Calibration LED sequence.  Flashes all 3 in unison
+ */
+class CalibrationLEDs: public Timer
+{
+  const LED** leds;
+  const LED** end;
+  bool state;
+protected:
+  void write()
+  {
+    const LED** current = end;
+    while (current-- > leds)
+      (*current)->write(state);
+  }
+  virtual void onFired() 
+  {
+    state = ! state;
+    write();
+  }
+public:
+  CalibrationLEDs(const LED** _leds, int _num, unsigned long duration = 500): Timer(duration), leds(_leds), end(_leds+_num), state(false)
+  {
+    Timer::disable();
+  }
+  void begin()
+  {
+    Updatable::begin();
+  }
+  void reset()
+  {
+    state = true;
+    write();
+    Timer::reset();
+  }
+  void disable()
+  {
+    state = false;
+    write();
+    Timer::disable();
+  }
+};
+
+LED Red(led_red), Yellow(led_yellow), Green(led_green);
+
+const LED* leds[] = { &Red, &Yellow, &Green }; 
+const int num_leds = sizeof(leds)/sizeof(leds[0]);
+StartupLEDs startup_leds(leds,num_leds);
+CalibrationLEDs calibration_leds(leds,num_leds);
+
+// Nodes in test mode do not sleep, but instead constantly try to send
+bool test_mode = false;
+
+// Nodes in calibration mode are looking for temperature calibration
+bool calibration_mode = false;
+
+// Helper functions to take readings
+
+// How many measurements to take.  64*1024 = 65536, so 64 is the max we can fit in a uint16_t.
+const int num_measurements = 64;
+
+uint32_t measure_temp()
+{
+    int i = num_measurements;
+    uint32_t reading = 0;
+    while(i--)
+      reading += analogRead(temp_pin);
+    
+    // Convert the reading to celcius*256
+    // This is the formula for MCP9700.
+    // C = reading * 1.1
+    // C = ( V - 1/2 ) * 100
+    //
+    // Then adjust for the calibation value on this sensor
+    return ( ( ( ( reading * 0x120 ) - 0x800000 ) * 0x64 ) >> 16 ) + this_node.temp_calibration;
+}
+
+uint32_t measure_voltage()
+{
+    // Take the voltage reading 
+    int i = num_measurements;
+    uint32_t reading = 0;
+    while(i--)
+      reading += analogRead(voltage_pin);
+
+    // Convert the voltage reading to volts*256
+    return ( reading * voltage_reference ) >> 16; 
+}
+
+struct CalibrationData
+{
+  uint8_t measurements_remaining;
+  static const uint8_t measurements_needed = 16;
+  int16_t accumulator;
+
+  CalibrationData()
+  {
+    measurements_remaining = measurements_needed;
+    accumulator = 0;
+  }
+  void add(int16_t reading)
+  {
+    accumulator += reading / measurements_needed;
+    if ( measurements_remaining )
+      --measurements_remaining;
+  }
+  bool done() const
+  {
+    return measurements_remaining == 0;
+  }
+  int16_t result() const
+  {
+    return accumulator;
+  }
+};
+
+CalibrationData calibration_data;
+
+void setup(void)
+{
+  //
+  // Print preamble
+  //
+  
+  Serial.begin(57600);
+  printf_begin();
+  printf_P(PSTR("\n\rRF24Network/examples/sensornet/\n\r"));
+  printf_P(PSTR("PLATFORM: " __PLATFORM__ "\n\r"));
+  printf_P(PSTR("VERSION: " __TAG__ "\n\r"));
+  
+  //
+  // Pull node address out of eeprom 
+  //
+
+  // Which node are we?
+  this_node = nodeconfig_read();
+
+  //
+  // Prepare sleep parameters
+  //
+
+  // Only the leaves sleep.  Nodes 01-05 are presumed to be relay nodes. 
+  if ( ! this_node.relay )
+    Sleep.begin(wdt_prescalar,sleep_cycles_per_transmission);
+
+  //
+  // Set up board hardware
+  //
+  ButtonA.begin();
+  ButtonLong.begin();
+
+  // Sensors use the stable internal 1.1V voltage
+#ifdef INTERNAL1V1
+  analogReference(INTERNAL1V1);
+#else
+  analogReference(INTERNAL);
+#endif
+
+  // Prepare the startup sequence
+  send_timer.begin();
+  startup_leds.begin();
+  calibration_leds.begin();
+
+  //
+  // Bring up the RF network
+  //
+
+  SPI.begin();
+  radio.begin();
+  network.begin(/*channel*/ 92, /*node address*/ this_node.address);
+}
+
+void loop(void)
+{
+  // Update objects
+  theUpdater.update();
+
+  // Pump the network regularly
+  network.update();
+
+  // Is there anything ready for us?
+  while ( network.available() )
+  {
+    // If so, grab it and print it out
+    RF24NetworkHeader header;
+    S_message message;
+    network.read(header,&message,sizeof(message));
+    printf_P(PSTR("%lu: APP Received #%u type %c %s from 0%o\n\r"),millis(),header.id,header.type,message.toString(),header.from_node);
+
+    // If we get a message, that's a little odd, because this sketch doesn't run on the
+    // base node.  Possibly it's a test message from a child node.  Possibly it's a sensor
+    // calibration message from a parent node.
+    //
+    // Either way, it only matters if we're NOT sleeping, and also only useful it we have
+    // a temp sensor
+
+    // If we have a temp sensor AND we are not sleeping
+    if ( temp_pin > -1 && ( ! Sleep || test_mode ) )
+    {
+      // if the received message is a test message, we can respond with a 'C' message in return
+      if ( header.type == 'c' )
+      {
+	// Take a reading
+	S_message response;
+	response.temp_reading = measure_temp(); 
+	response.voltage_reading = measure_voltage();
+
+	// Send it back as a calibration message
+	RF24NetworkHeader response_header(/*to node*/ header.from_node, /*type*/ 'C');
+	network.write(response_header,&response,sizeof(response));
+      }
+      else if ( header.type == 'C' )
+      {
+	// This is a calibration message.  Calculate the diff
+	uint16_t diff = message.temp_reading - measure_temp();
+	printf_P(PSTR("%lu: APP Calibration received %04x diff %04x\n\r"),millis(),message.temp_reading,diff);
+	calibration_data.add(diff);
+
+	if ( calibration_data.done() )
+	{
+	  calibration_mode = false;
+	  calibration_leds.disable();
+	  printf_P(PSTR("%lu: APP Stop calibration mode. Calibrate by %04x\n\r"),millis(),calibration_data.result());
+
+	  // Now apply the calibration
+	  this_node.temp_calibration += calibration_data.result();
+	  // And save it to eeprom...
+	  set_temp_calibration( this_node.temp_calibration );
+	}
+
+      }
+    }
+  }
+
+  // If we are the kind of node that sends readings, 
+  // AND we have a temp sensor
+  // AND it's time to send a reading 
+  // AND we're in the mode where we send readings...
+  if ( this_node.address > 0 && temp_pin > -1 && ( ( Sleep && ! test_mode ) || send_timer.wasFired() ) && ! startup_leds )
+  {
+    // Transmission beginning, TX LED ON
+    Yellow = true;
+    if ( test_mode && ! calibration_mode )
+    {
+      Green = false;
+      Red = false;
+    }
+
+    S_message message;
+    message.temp_reading = measure_temp(); 
+    message.voltage_reading = measure_voltage(); 
+
+    char message_type = 'S';
+    if ( calibration_mode )
+      message_type = 'c';
+    else if (test_mode )
+      message_type = 't';
+
+    // By default send to the base
+    uint16_t to_node = 0;
+    if ( test_mode )
+      // In test mode, sent to our parent.
+      to_node = network.parent();
+
+    printf_P(PSTR("---------------------------------\n\r"));
+    printf_P(PSTR("%lu: APP Sending type-%c %s to 0%o...\n\r"),millis(),message_type,message.toString(),to_node);
+   
+    RF24NetworkHeader header(to_node,message_type);
+    bool ok = network.write(header,&message,sizeof(message));
+    if (ok)
+    {
+      if ( test_mode && ! calibration_mode )
+	Green = true;
+      printf_P(PSTR("%lu: APP Send ok\n\r"),millis());
+    }
+    else
+    {
+      if ( test_mode && ! calibration_mode )
+	Red = true;
+      printf_P(PSTR("%lu: APP Send failed\n\r"),millis());
+    }
+
+    // Transmission complete, TX LED OFF
+    Yellow = false;
+   
+    if ( Sleep && ! test_mode ) 
+    {
+      // Power down the radio.  Note that the radio will get powered back up
+      // on the next write() call.
+      radio.powerDown();
+
+      // Be sure to flush the serial first before sleeping, so everything
+      // gets printed properly
+      Serial.flush();
+      
+      // Sleep the MCU.  The watchdog timer will awaken in a short while, and
+      // continue execution here.
+      Sleep.go();
+    }
+  }
+
+  // Button
+  unsigned a = ButtonA.wasReleased();
+  if ( a && a < 500 )
+  {
+    // Pressing the button during startup sequences engages test mode.
+    // Pressing it after turns off test mode.
+    if ( startup_leds )
+    {
+      test_mode = true;
+      send_timer.setInterval(1000);
+      printf_P(PSTR("%lu: APP Start test mode\n\r"),millis());
+    }
+    else if ( calibration_mode )
+    {
+      calibration_mode = false;
+      calibration_leds.disable();
+      printf_P(PSTR("%lu: APP Stop calibration mode\n\r"),millis());
+    }
+    else if ( test_mode )
+    {
+      test_mode = false;
+      Green = false;
+      Red = false;
+      send_timer.setInterval(8000);
+      printf_P(PSTR("%lu: APP Stop test mode\n\r"),millis());
+    }
+  }
+
+  // Long press
+  if ( ButtonLong.wasPressed() && test_mode )
+  {
+    calibration_mode = true;
+    calibration_leds.reset();
+    calibration_data = CalibrationData();
+    printf_P(PSTR("%lu: APP Start calibration mode\n\r"),millis());
+  }
+
+  // Listen for a new node address
+  nodeconfig_listen();
+}
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/sleep.cpp b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/sleep.cpp
new file mode 100644
index 0000000..e81f316
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/sleep.cpp
@@ -0,0 +1,55 @@
+
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * @file sleep.cpp 
+ *
+ * Sleep helpers, definitions
+ */
+
+#include "RF24Network_config.h"
+#include 
+#include "sleep.h" 
+
+sleep_c Sleep;
+
+/******************************************************************/
+
+void sleep_c::begin(wdt_prescalar_e prescalar_in,short cycles)
+{
+  sleep_cycles_remaining = cycles;
+  sleep_cycles_per_transmission = cycles;
+
+  uint8_t prescalar = min(9,(uint8_t)prescalar_in);
+  uint8_t wdtcsr = prescalar & 7;
+  if ( prescalar & 8 )
+      wdtcsr |= _BV(WDP3);
+
+  MCUSR &= ~_BV(WDRF);
+  WDTCSR = _BV(WDCE) | _BV(WDE);
+  WDTCSR = _BV(WDCE) | wdtcsr | _BV(WDIE);
+}
+
+/******************************************************************/
+
+void sleep_c::go(void)
+{
+  while( sleep_cycles_remaining-- )
+  {
+    set_sleep_mode(SLEEP_MODE_PWR_DOWN); 
+    sleep_mode();
+  }
+  
+  sleep_cycles_remaining = sleep_cycles_per_transmission;
+}
+
+ISR(WDT_vect) {
+}
+
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/sleep.h b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/sleep.h
new file mode 100644
index 0000000..bef5ea6
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/sleep.h
@@ -0,0 +1,84 @@
+
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * @file sleep.h 
+ *
+ * Declaration of the sleep_c class. 
+ */
+ 
+#ifndef __SLEEP_H__
+#define __SLEEP_H__
+
+/**
+ * Enums for the duration of the watchdog timer
+ */
+
+typedef enum { wdt_16ms = 0, wdt_32ms, wdt_64ms, wdt_128ms, wdt_250ms, wdt_500ms, wdt_1s, wdt_2s, wdt_4s, wdt_8s } wdt_prescalar_e;
+
+/**
+ * Simplified sleeping handler
+ */
+
+class sleep_c
+{
+public:
+  /**
+   * Enable the system to be able to sleep
+   *
+   * Does not actually do any sleeping.
+   *
+   * For example, to do something roughly evert minute, configure
+   * it like this:
+   * 
+   * @code
+   *  Sleep.begin(wdt_8s,7);
+   * @endcode
+   *
+   * @param prescalar Duration of the watchdog timer interrupt.
+   * The system will actually sleep for this long.
+   * @param cycles Number of times the system will wake up before
+   * returning from @p go().
+   */
+  void begin(wdt_prescalar_e prescalar,short cycles);
+
+  /**
+   * Go to sleep 
+   *
+   * This will return after the watchdog has awoken for the number
+   * of times specified in begin().
+   */
+  void go(void);
+
+  /**
+   * Test whether the node sleeps
+   *
+   * @retval true if the node will sleep
+   */
+  operator bool(void) const 
+  {
+    return sleep_cycles_per_transmission;
+  }
+
+private:
+  volatile short sleep_cycles_remaining;
+  short sleep_cycles_per_transmission; 
+};
+
+/**
+ * Singleton instance for general use
+ *
+ * @warning: This class is hard-coded to ONLY work with this singleton.
+ * Any other instances will fail.
+ */
+
+extern sleep_c Sleep;
+
+#endif // __SLEEP_H__
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/timer.h b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/timer.h
new file mode 100644
index 0000000..342bbec
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/examples/sensornet/timer.h
@@ -0,0 +1,38 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+// STL headers
+// C headers
+// Framework headers
+// Library headers
+// Project headers
+
+/**
+ * Simple timer 
+ */
+
+struct timer_t 
+{
+unsigned long last;
+unsigned long interval;
+timer_t(unsigned long _interval): interval(_interval) {}
+operator bool(void)
+{
+  unsigned long now = millis();
+  bool result = now - last >= interval;
+  if ( result )
+    last = now; 
+  return result;
+}
+};
+
+#endif // __TEMPLATE_H__
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/README b/hardware/digistump/sam/libraries/RF24Network/tests/README
new file mode 100644
index 0000000..fc25399
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/README
@@ -0,0 +1,19 @@
+This is the 'receiver' for the unit tests.  Run it on a node which
+is NOT under test.
+
+TODO
+
+Send finder request needs a re-think.  It needs to be re-implemented as a Tictocs::Timer, so it
+doesn't block the loop().
+
+I could also make Tictocs objects which monitor the RF24network and pull off messages that are just
+for them.  Likewise, the network can raise a signal when there is a new message.  Although I would not
+want to put that into the library for fear of adding a dependency.
+
+so the finder needs to maintain state
+- Waiting: Waiting for a finder request
+- Sending: In the midst of looping through children
+
+Needs to have some delay between each send.  So the finder has a timer component.
+
+Also...  Reset should also reset the internal copy of the sync data.  Sync may need a 'reset' method.
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit/Globals.cpp b/hardware/digistump/sam/libraries/RF24Network/tests/unit/Globals.cpp
new file mode 100644
index 0000000..43ba3d2
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit/Globals.cpp
@@ -0,0 +1,29 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+// STL headers
+// C headers
+// Framework headers
+// Library headers
+#include 
+#include 
+// Project headers
+// This component's header
+#include 
+
+#include "WProgram.h"
+
+/****************************************************************************/
+
+HardwareSPI SPI(2);
+
+// Radio on Maple Native w/ Getting Started board
+RF24 radio(7,6);
+RF24Network network(radio);
+
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit/Globals.h b/hardware/digistump/sam/libraries/RF24Network/tests/unit/Globals.h
new file mode 100644
index 0000000..c37cbc0
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit/Globals.h
@@ -0,0 +1,36 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef __GLOBALS_H__
+#define __GLOBALS_H__
+
+// STL headers
+// C headers
+// Framework headers
+// Library headers
+// Project headers
+
+class RF24;
+class RF24Network;
+
+extern RF24 radio;
+extern RF24Network network;
+
+/**
+ * Example for how classes should be declared
+ */
+
+class Template
+{
+private:
+protected:
+public:
+};
+
+#endif // __GLOBALS_H__
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit/Jamfile b/hardware/digistump/sam/libraries/RF24Network/tests/unit/Jamfile
new file mode 100644
index 0000000..207c8fd
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit/Jamfile
@@ -0,0 +1,12 @@
+SubDir TOP ;
+
+# Set up output directories
+LOCATE_TARGET	= $(SEARCH_SOURCE)/out/$(TOOLSET) ;
+LOCATE_SOURCE	= $(LOCATE_TARGET) ;
+
+# Pull in local libraries
+SKETCH_LIBS	+= RF24Network RF24 ;
+HDRS		+= $(HOME)/Source/Arduino/libraries/$(SKETCH_LIBS) ;
+
+# Main output executable
+Maple $(SEARCH_SOURCE:B).elf : [ GLOB $(SEARCH_SOURCE) $(HOME)/Source/Arduino/libraries/$(SKETCH_LIBS) : $(MODULE_EXT) ] ;
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit/Jamrules b/hardware/digistump/sam/libraries/RF24Network/tests/unit/Jamrules
new file mode 100644
index 0000000..384f28a
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit/Jamrules
@@ -0,0 +1,251 @@
+MCU		= cortex-m3 ;
+CHIP		= STM32F103ZE ;
+BOARD		= maple_native ;
+
+#CHIP		= at91sam3u4 ;
+#BOARD		= sam3u-ek ;
+
+if ! $(TOOLSET)
+{
+	TOOLSET = mix ;
+	Echo "Assuming TOOLSET=mix" ;
+}
+else if $(TOOLSET) = cs
+{
+	TOOLS_PATH	= /opt/cs/arm/bin ;
+	TOOLS_ARCH	= arm-none-eabi- ;
+}
+else if $(TOOLSET) = yagarto
+{
+	TOOLS_PATH	= ~/Source/yagarto-4.6.2/bin ;
+	TOOLS_ARCH	= arm-none-eabi- ;
+}
+if $(TOOLSET) = yagarto-install
+{
+	TOOLS_PATH	= ~/Source/yagarto/install/bin ;
+	TOOLS_ARCH	= arm-none-eabi- ;
+}
+else if $(TOOLSET) = devkit
+{
+	TOOLS_PATH	= /opt/devkitARM/bin ;
+	TOOLS_ARCH	= arm-eabi- ;
+}
+else if $(TOOLSET) = maple
+{
+	TOOLS_PATH	= /opt/Maple/Resources/Java/hardware/tools/arm/bin ; 
+	TOOLS_ARCH	= arm-none-eabi- ;
+	LINK_DIR	= /opt/Maple/Resources/Java/hardware/leaflabs/cores/maple ;
+	MAPLE_DIR	= /opt/Maple/Resources/Java/hardware/leaflabs/cores/maple ;
+	MAPLE_SUBDIRS	= . ;
+}
+else if $(TOOLSET) = mix
+{
+	TOOLS_PATH	= /opt/Maple/Resources/Java/hardware/tools/arm/bin ; 
+	TOOLS_ARCH	= arm-none-eabi- ;
+	LINKFLAGS	+= --print-gc-sections ;
+}
+else if $(TOOLSET) = ports
+{
+	TOOLS_PATH	= /opt/local/bin ;
+	TOOLS_ARCH	= arm-none-eabi- ;
+}
+
+# Tool locations
+
+CC	  	= $(TOOLS_PATH)/$(TOOLS_ARCH)gcc ;
+C++	 	= $(TOOLS_PATH)/$(TOOLS_ARCH)g++ ;
+AS	  	= $(TOOLS_PATH)/$(TOOLS_ARCH)gcc -c ;
+LINK	  	= $(TOOLS_PATH)/$(TOOLS_ARCH)g++ ;
+OBJCOPY 	= $(TOOLS_PATH)/$(TOOLS_ARCH)objcopy ;
+DFU		= dfu-util ;
+
+# Flags
+
+DEFINES  	+= VECT_TAB_FLASH BOARD_$(BOARD) MCU_$(CHIP) ERROR_LED_PORT=GPIOC ERROR_LED_PIN=15 STM32_HIGH_DENSITY MAPLE_IDE ;
+OPTIM		= -Os ;
+MFLAGS		= cpu=$(MCU) thumb arch=armv7-m ;
+CCFLAGS  	= -Wall -Wno-strict-aliasing -Wno-format -m$(MFLAGS) -g -nostdlib -ffunction-sections -fdata-sections -Wl,--gc-sections ;
+C++FLAGS  	= $(CCFLAGS) -fno-rtti -fno-exceptions ; 
+LINKFLAGS  	+= -m$(MFLAGS) -Xlinker --gc-sections ;
+DFUFLAGS	= -a1 -d 0x1eaf:0x0003 -R ;
+
+# Directories
+
+MAPLE_DIR	?= /opt/libmaple ;
+MAPLE_LIBS	= Servo LiquidCrystal Wire FreeRTOS ;
+MAPLE_SUBDIRS	?= libmaple libmaple/usb libmaple/usb/usb_lib wirish wirish/comm wirish/boards ; 
+
+SKETCH_DIR	= $(HOME)/Source/Maple ;
+
+CORE_DIRS	= $(MAPLE_DIR)/$(MAPLE_SUBDIRS) $(MAPLE_DIR)/libraries/$(MAPLE_LIBS) $(MAPLE_DIR)/libraries/$(MAPLE_LIBS)/utility ;
+HDRS		= $(CORE_DIRS) ;
+
+# Modules
+MODULE_EXT	= *.c *.cpp *.S *.pde *.ino *.test ;
+CORE_MODULES	= [ GLOB $(CORE_DIRS) : $(MODULE_EXT) ] ; 
+
+# Unit test framework
+CXXTEST_DIR	= $(HOME)/Source/cxxtest ;
+CXXTEST_GEN	= $(CXXTEST_DIR)/bin/cxxtestgen ;
+HDRS		+= $(CXXTEST_DIR) ;
+
+# Linker script
+LINK_DIR	?= $(MAPLE_DIR)/support/ld ;
+LINKSCRIPT	= $(LINK_DIR)/$(BOARD)/flash.ld ; 
+LINKFLAGS 	+= -T$(LINKSCRIPT) -L$(LINK_DIR) ;
+
+rule Pde
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+if ( $(ARDUINO_VERSION) < 100 )
+{
+	ARDUINO_H = WProgram.h ;
+}
+else
+{
+	ARDUINO_H = Arduino.h ;
+}
+
+actions Pde
+{
+	echo "#include <$(ARDUINO_H)>" > $(<) 
+	echo "#line 1 \"$(>)\"" >> $(<)
+	cat $(>) >> $(<) 
+}
+
+rule C++Pde
+{
+	local _CPP = $(>:B).cpp ;
+	Pde $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule TestSuite
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+actions TestSuite
+{
+	$(CXXTEST_GEN) --part $(>) > $(<)
+}
+
+rule TestRoot
+{
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+}
+
+actions TestRoot
+{
+	$(CXXTEST_GEN) --root --error-printer > $(<)
+}
+
+rule C++TestSuite
+{
+	local _CPP = $(>:B).cpp ;
+	TestSuite $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule Hex
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends hex : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Hex
+{
+	$(OBJCOPY) -O ihex $(>) $(<)
+}
+
+rule Binary
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends binary : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Binary
+{
+	$(OBJCOPY) -O binary $(>) $(<)
+}
+
+rule UserObject
+{
+	switch $(>:S)
+	{
+		case .S : As $(<) : $(>) ;
+		case .ino : C++Pde $(<) : $(>) ;
+		case .pde : C++Pde $(<) : $(>) ;
+		case .test : C++TestSuite $(<) : $(>) ;
+	}
+}
+
+rule Upload
+{
+	Depends up : $(<) ;
+	NotFile up ;
+	Always $(<) ;
+}
+
+actions Upload
+{
+	$(MAPLE_DIR)/support/scripts/reset.py
+	sleep 1
+	$(DFU) $(DFUFLAGS) -D $(<)
+	sleep 5
+}
+
+rule Login
+{
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Always $(<) ;
+}
+
+actions Login
+{
+	ls > $(<)
+	screen $(>) 
+}
+
+# Override base objects rule, so all output can go in the output dir
+rule Objects
+{
+        local _i ;
+
+        for _i in [ FGristFiles $(<) ]
+        {
+		local _b = $(_i:B)$(SUFOBJ) ;
+		local _o = $(_b:G=$(SOURCE_GRIST:E)) ;
+                Object $(_o) : $(_i) ;
+                Depends obj : $(_o) ;
+        }
+}
+
+# Override base main rule, so all output can go in the output dir
+rule Main
+{
+	# Bring in the map
+	LINKFLAGS on $(<) = $(LINKFLAGS) -Wl,-Map=$(LOCATE_TARGET)/$(<:B).map ;
+
+	MakeLocate $(<) ;
+        MainFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+        Objects $(>) ;
+}
+
+rule Maple
+{
+	Main $(<) : $(>) $(CORE_MODULES) ; 
+	Binary $(<:B).bin : $(<) ;
+	Upload $(<:B).bin ;
+	Login login : /dev/tty.usbmodemfa441 ;
+}
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit/PingTest.test b/hardware/digistump/sam/libraries/RF24Network/tests/unit/PingTest.test
new file mode 100644
index 0000000..f32ae89
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit/PingTest.test
@@ -0,0 +1,145 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+// STL headers
+#include 
+#include 
+#include 
+// C headers
+#include 
+// Framework headers
+// Library headers
+#include 
+// Project headers
+#include 
+#include 
+// This component's header
+#include 
+
+#include "WProgram.h"
+#include "Globals.h"
+
+using namespace std;
+
+class PingTestSuite: public CxxTest::TestSuite
+{
+
+public:
+  // 'Delay' but update the network for a bit
+  void net_delay(unsigned long amount)
+  {
+    unsigned long start = millis();
+    while ( millis() - start < amount )
+    {
+      network.update();
+#if 0
+      // Is there anything ready for us?
+      if ( network.available() )
+      {
+	// If so, take a look at it
+	RF24NetworkHeader header;
+	network.read(header,0,0);
+
+	cout << millis() << ": net_delay got " << header.type << " from " << header.from_node << "\r\n";
+      }
+#endif     
+    }
+  }
+  void setUp()
+  {
+    // Reset remote to initial state
+    RF24NetworkHeader header(/*to node*/ 1, /*type*/ 'R' /*Reset*/);
+    network.write(header,0,0);
+    
+    // Wait a bit for the message to take
+    net_delay(50);
+  }
+  
+  void tearDown()
+  {
+    net_delay(100);
+    //cout << "\r\n Complete. Press any key \r\n";
+    //SerialUSB.read();
+  }
+
+  void testNothing()
+  {
+    cout << "\r\n STARTING " << __FUNCTION__ << "\r\n";
+  }
+
+  void testPing()
+  {
+    cout << "\r\n STARTING " << __FUNCTION__ << "\r\n";
+
+    // Send an echo ping to the other unit 
+    RF24NetworkHeader header(/*to node*/ 1, /*type*/ 'E' /*Echo*/);
+    uint32_t testval = 0x12345678, gotval = 0;
+    network.write(header,&testval,sizeof(testval));
+
+    const unsigned long timeout = 1000;
+    unsigned long sent_at = millis();
+    while ( millis() - sent_at < timeout && ! gotval )
+    {
+      net_delay(100);
+
+      // Is there anything ready for us?
+      if ( network.available() )
+      {
+	// If so, take a look at it
+	RF24NetworkHeader header;
+	network.peek(header);
+
+	switch (header.type)
+	{
+	case 'E':
+	  network.read(header,&gotval,sizeof(gotval));
+	  break;
+	default:
+	  // Anything else is unexpected, and ergo a test failure
+	  network.read(header,0,0);
+	  gotval = -1;
+	  break;
+	};
+      }
+    }
+
+    TS_ASSERT_EQUALS( gotval, testval );
+  }
+
+  void testFinder()
+  {
+    cout << "\r\n STARTING " << __FUNCTION__ << "\r\n";
+    
+    // Send a child finder to the other unit 
+    RF24NetworkHeader header(/*to node*/ 1, /*type*/ 'F' /*Echo*/);
+    uint32_t testval = 0x12345678, gotval = 0;
+    network.write(header,&testval,sizeof(testval));
+
+    const unsigned long timeout = 3000;
+    unsigned long sent_at = millis();
+    while ( millis() - sent_at < timeout ) // && ! gotval )
+    {
+      network.update();
+
+      // Is there anything ready for us?
+      if ( network.available() )
+      {
+	// If so, take a look at it
+	RF24NetworkHeader header;
+	network.peek(header);
+	network.read(header,&gotval,sizeof(gotval));
+
+	cout << millis() << ": FINDER " << header.type << " from " << header.from_node << " " << hex << gotval << dec << "\r\n";
+      }
+    }
+    
+    TS_ASSERT_EQUALS( gotval, testval );
+  }
+
+};
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit/README b/hardware/digistump/sam/libraries/RF24Network/tests/unit/README
new file mode 100644
index 0000000..9547569
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit/README
@@ -0,0 +1,12 @@
+These unit tests only work on Maple.  This test runs on a Maple,
+as node #00.  One other node is expected on node #01, running the
+"unit_rx" sketch, which runs on Arduino.
+
+In the future, it would be interesting to write a test which enumerated
+the entire tree.  Each node could implement a "child finder", where it
+sends a message to each child.  Upon receiving the message, each child
+sends the message out to ITS children, AND sends a "Hello" to the base node.
+
+This requires a 'F' finder request.  For the response, we can re-use
+the 'E' echo response.  The 'E' echo system presumes that the base is
+the requestor and the RX nodes are the responder.
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit/SyncTest.test b/hardware/digistump/sam/libraries/RF24Network/tests/unit/SyncTest.test
new file mode 100644
index 0000000..d79f1b5
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit/SyncTest.test
@@ -0,0 +1,123 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+// STL headers
+#include 
+#include 
+#include 
+// C headers
+#include 
+// Framework headers
+// Library headers
+#include 
+// Project headers
+#include 
+#include 
+// This component's header
+#include 
+
+#include "WProgram.h"
+
+#include "Globals.h"
+
+using namespace std;
+
+class SyncTestSuite: public CxxTest::TestSuite
+{
+  struct sync_data_t
+  {
+    uint16_t first;
+    uint16_t second;
+
+    sync_data_t(void): first(1), second(2) {}
+  };
+
+  sync_data_t* p_sync_data;
+
+  Sync* pSync;
+
+public:
+  // 'Delay' but update the network for a bit
+  void net_delay(unsigned long amount)
+  {
+    unsigned long start = millis();
+    while ( millis() - start < amount )
+    {
+      pSync->update();
+      // Is there anything ready for us?
+      if ( network.available() )
+      {
+	// If so, take a look at it
+	RF24NetworkHeader header;
+	network.read(header,0,0);
+
+	cout << millis() << ": net_delay got " << header.type << " from " << header.from_node << "\r\n";
+      }
+    }
+  }
+  void setUp()
+  {
+    pSync = new Sync(network);
+    pSync->begin(/* other node*/ 1);
+    p_sync_data = new(sync_data_t);
+
+    // Reset remote to initial state
+    RF24NetworkHeader header(/*to node*/ 1, /*type*/ 'R' /*Reset*/);
+    network.write(header,0,0);
+    
+    // Wait a bit for the message to take
+    net_delay(200);
+  }
+  
+  void tearDown()
+  {
+    net_delay(100);
+    //cout << "\r\n Complete. Press any key \r\n";
+    //SerialUSB.read();
+    
+    delete p_sync_data;
+    delete pSync;
+  }
+
+  void testNoUpdate( void )
+  {
+    cout << "\r\n STARTING " << __FUNCTION__ << "\r\n";
+    
+    pSync->register_me(*p_sync_data);
+
+    int i = 10;
+    while (i--)
+      pSync->update();
+    
+    TS_ASSERT_EQUALS(p_sync_data->first,1);
+  }
+  void testSync( void )
+  {
+    cout << "\r\n STARTING " << __FUNCTION__ << "\r\n";
+    pSync->register_me(*p_sync_data);
+
+    int i = 10;
+    while (i--)
+      pSync->update();
+
+    const uint16_t testval = 10;
+    p_sync_data->first = testval;
+
+    // wait a little while.  During this time, the 'first' value will be propagated
+    // out to the other unit, it will set the value onto 'second', and it should get
+    // propagated back.
+
+    const unsigned long interval = 1000;
+    unsigned long sent_at = millis();
+    while ( millis() - sent_at < interval && p_sync_data->second != testval )
+      pSync->update();
+
+    TS_ASSERT_EQUALS(p_sync_data->second,testval);
+  }
+};
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit/main.cpp b/hardware/digistump/sam/libraries/RF24Network/tests/unit/main.cpp
new file mode 100644
index 0000000..1e03125
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit/main.cpp
@@ -0,0 +1,77 @@
+#ifdef MAPLE_IDE
+
+#include 
+#include "wirish.h"
+
+extern void setup(void);
+extern void loop(void);
+
+void board_start(const char* program_name)
+{
+  // Set up the LED to steady on
+  pinMode(BOARD_LED_PIN, OUTPUT);
+  digitalWrite(BOARD_LED_PIN, HIGH);
+
+  // Setup the button as input
+  pinMode(BOARD_BUTTON_PIN, INPUT);
+  digitalWrite(BOARD_BUTTON_PIN, HIGH);
+
+  SerialUSB.begin();
+  SerialUSB.println("Press BUT");
+
+  // Wait for button press
+  while ( !isButtonPressed() )
+  {
+  }
+
+  SerialUSB.println("Welcome!");
+  SerialUSB.println(program_name);
+
+  int i = 11;
+  while (i--)
+  {
+    toggleLED();
+    delay(50);
+  }
+}
+
+/**
+ * Custom version of _write, which will print to the USB.
+ * In order to use it you MUST ADD __attribute__((weak))
+ * to _write in libmaple/syscalls.c
+*/
+extern "C" int _write(int file, char * ptr, int len)
+{
+  if ( (file != 1) && (file != 2) )
+    return 0; 
+  else
+    SerialUSB.write(ptr,len);
+  return len;
+}
+
+__attribute__((constructor)) __attribute__ ((weak)) void premain()
+{
+  init();
+}
+
+__attribute__((weak)) void setup(void)
+{
+  board_start("No program defined");
+}
+
+__attribute__((weak)) void loop(void)
+{
+}
+
+__attribute__((weak)) int main(void)
+{
+  setup();
+
+  while (true)
+  {
+    loop();
+  }
+  return 0;
+}
+#endif // ifdef MAPLE_IDE
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit/runner.cpp b/hardware/digistump/sam/libraries/RF24Network/tests/unit/runner.cpp
new file mode 100644
index 0000000..5e59059
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit/runner.cpp
@@ -0,0 +1,43 @@
+#include 
+
+#ifndef CXXTEST_RUNNING
+#define CXXTEST_RUNNING
+#endif
+
+#define _CXXTEST_HAVE_STD
+#define _CXXTEST_LONGLONG long long
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+extern void board_start(const char*);
+extern RF24Network network;
+extern RF24 radio;
+
+int main( void ) 
+{
+  CxxTest::ErrorPrinter tmp;
+
+  while(1)
+  {
+    board_start(__FILE__);
+    
+    SPI.begin();
+    radio.begin();
+    network.begin(/* channel */100,/* this node */0);
+
+    CxxTest::Main( tmp, 0, NULL );
+
+    printf("Tests complete.  Restarting...\r\n");
+  }
+}
+const char* CxxTest::RealWorldDescription::_worldName = "cxxtest";
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/Finder.cpp b/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/Finder.cpp
new file mode 100644
index 0000000..32a5e0f
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/Finder.cpp
@@ -0,0 +1,129 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+// STL headers
+// C headers
+// Framework headers
+// Library headers
+#include "RF24Network.h"
+
+// Project headers
+// This component's header
+#include 
+
+extern RF24Network network;
+
+// Message buffer space
+static uint8_t message[32];
+
+/****************************************************************************/
+  
+Finder::Finder(void): this_node(0), state(state_waiting), 
+  last_sent(millis()-interval), child_increment(-1) 
+{
+}
+
+/****************************************************************************/
+
+void Finder::begin(uint16_t _this_node)
+{
+  this_node = _this_node;
+  
+  if ( ! ( this_node & 07000 ) )
+  {
+    // Figure out the address of the first child.  e.g. if our node is 045, our
+    // first child is 0145.  So we need to shift 01 up enough places to be the
+    // highest digit
+    child_increment = 01;
+    uint16_t temp = this_node;
+    while ( temp )
+    {
+      child_increment <<= 3;
+      temp >>= 3;
+    }
+  }
+
+  printf_P(PSTR("%lu: Node %o increment %o\r\n"),millis(),this_node,child_increment);
+}
+
+/****************************************************************************/
+
+void Finder::update(void)
+{
+  // Check the network for traffic
+
+  // If we got a new finder request, launch!
+  if ( network.available() )
+  {
+    RF24NetworkHeader header;
+    network.peek(header);
+    if ( header.type == 'F' )
+    {
+      network.read(header,message,sizeof(message));
+      uint16_t from = header.from_node;
+      printf_P(PSTR("%lu: APP Received FINDER request from %o\r\n"),millis(),from);
+
+      if ( state == state_sending )
+      {
+	printf_P(PSTR("%lu: APP ERROR, already sending a finder request\r\n"),millis());
+      }
+      else if ( child_increment == 0xffff )
+      {
+	printf_P(PSTR("%lu: APP This app has no children, done.\r\n"),millis());
+	last_sent = millis() - interval;
+	state = state_done;
+	goto finish;
+      }
+      else
+      {
+	last_sent = millis() - interval;
+	to_node = this_node + child_increment;
+	state = state_sending;
+	goto finish;
+      }
+    }
+  }
+
+  // If we're working but not ready, continue
+  if ( state != state_waiting && millis() - last_sent <= interval )
+    return;
+
+  // If we're working, send!
+  if ( state == state_sending )
+  {
+    RF24NetworkHeader header(to_node,'F');
+    /*bool ok = */ network.write(header,message,sizeof(message));
+    last_sent = millis();
+    
+    to_node += child_increment;
+    
+    // Done?
+    if ( to_node > this_node + 5 * child_increment )
+    {
+      state = state_done;
+      goto finish;
+    }
+  }
+  
+  // If we're now done, send the final 'E' back
+  if ( state == state_done )
+  {
+    // Send an 'E' Echo response back to the BASE
+    RF24NetworkHeader header(00,'E');
+    network.write(header,message,sizeof(message));
+    
+    state = state_waiting;
+    goto finish;
+  }
+finish:
+  return;
+}
+
+/****************************************************************************/
+
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/Finder.h b/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/Finder.h
new file mode 100644
index 0000000..07702b4
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/Finder.h
@@ -0,0 +1,42 @@
+/*
+ Copyright (C) 2011 J. Coliz 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef __FINDER_H__
+#define __FINDER_H__
+
+// STL headers
+// C headers
+// Framework headers
+#include 
+// Library headers
+// Project headers
+
+/**
+ * Manage a child-finder request 
+ */
+
+class Finder
+{
+private:
+  uint16_t this_node;
+  enum state_e { state_none = 0, state_waiting, state_sending, state_done, state_invalid };
+  state_e state;
+  static const unsigned long interval = 50;
+  unsigned long last_sent;
+  uint16_t to_node;
+  uint16_t child_increment;
+protected:
+  
+public:
+  Finder(void);
+  void begin(uint16_t);
+  void update(void);
+};
+
+#endif // __FINDER_H__
+// vim:cin:ai:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/Jamfile b/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/Jamfile
new file mode 100644
index 0000000..51c1220
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/Jamfile
@@ -0,0 +1,210 @@
+# (1) Project Information
+
+PROJECT_LIBS 	= SPI RF24 RF24Network ; 
+
+# (2) Board Information
+
+UPLOAD_PROTOCOL ?= stk500v1 ;
+UPLOAD_SPEED 	?= 57600 ;
+MCU		?= atmega328p ;
+F_CPU 		?= 16000000 ;
+CORE		?= arduino ;
+VARIANT 	?= standard ;
+ARDUINO_VERSION	?= 100 ;
+
+# (3) USB Ports
+
+PORTS		= p4 p6 p9 u0 u1 u2 ;
+PORT_p6 	= /dev/tty.usbserial-A600eHIs ;
+PORT_p4 	= /dev/tty.usbserial-A40081RP ;
+PORT_p9		= /dev/tty.usbserial-A9007LmI ;
+PORT_u0 	= /dev/ttyUSB0 ;
+PORT_u1 	= /dev/ttyUSB1 ;
+PORT_u2 	= /dev/ttyUSB2 ;
+
+# (4) Location of AVR tools
+#
+# This configuration assumes using avr-tools that were obtained separate from the Arduino
+# distribution. 
+
+if $(OS) = MACOSX 
+{
+	AVR_BIN 	= /usr/local/avrtools/bin ;
+	AVR_ETC 	= /usr/local/avrtools/etc ;
+	AVR_INCLUDE	= /usr/local/avrtools/include ; 
+}
+else
+{
+	AVR_BIN 	= /usr/bin ;
+	AVR_INCLUDE 	= /usr/lib/avr/include ;
+	AVR_ETC 	= /etc ; 
+}
+
+# (5) Directories where Arduino core and libraries are located
+
+ARDUINO_DIR 	?= /opt/Arduino ;
+ARDUINO_CORE 	= $(ARDUINO_DIR)/hardware/arduino/cores/$(CORE) $(ARDUINO_DIR)/hardware/arduino/variants/$(VARIANT) ;
+ARDUINO_LIB 	= $(ARDUINO_DIR)/libraries ;
+SKETCH_LIB      = $(HOME)/Source/Arduino/libraries ;
+
+#
+# --------------------------------------------------
+# Below this line usually never needs to be modified 
+#
+
+# Tool locations
+
+CC	  	= $(AVR_BIN)/avr-gcc ;
+C++	 	= $(AVR_BIN)/avr-g++ ;
+LINK	  	= $(AVR_BIN)/avr-gcc ;
+OBJCOPY 	= $(AVR_BIN)/avr-objcopy ;
+AVRDUDE 	= $(AVR_BIN)/avrdude ;
+
+# Flags
+
+DEFINES  	+= NODE=$(NODE) F_CPU=$(F_CPU)L ARDUINO=$(ARDUINO_VERSION) VERSION_H ;
+OPTIM		= -Os ;
+CCFLAGS  	= -Wall -Wextra -mmcu=$(MCU) -ffunction-sections -fdata-sections ;
+C++FLAGS  	= $(CCFLAGS) -fno-exceptions -fno-strict-aliasing ;
+LINKFLAGS  	= $(OPTIM) -lm -Wl,--gc-sections -mmcu=$(MCU) ;
+AVRDUDEFLAGS	= -V -F -D -C $(AVR_ETC)/avrdude.conf -p $(MCU) -c $(UPLOAD_PROTOCOL) -b $(UPLOAD_SPEED) ;
+
+# Search everywhere for headers
+
+HDRS  	 	= $(PWD) $(AVR_INCLUDE) $(ARDUINO_CORE) $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) ;
+
+# Output locations
+
+LOCATE_TARGET	= $(F_CPU) ;
+LOCATE_SOURCE	= $(F_CPU) ;
+
+#
+# Custom rules
+#
+
+rule GitVersion
+{
+	Always $(<) ;
+	Depends all : $(<) ;
+}
+
+actions GitVersion
+{
+	echo "const char program_version[] = \"\\" > $(<)
+	git log -1 --pretty=format:%h >> $(<)
+	echo "\";" >> $(<)
+}
+
+GitVersion version.h ;
+
+rule Pde
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_SOURCE) ;
+	Clean clean : $(<) ;
+}
+
+if ( $(ARDUINO_VERSION) < 100 )
+{
+	ARDUINO_H = WProgram.h ;
+}
+else
+{
+	ARDUINO_H = Arduino.h ;
+}
+
+actions Pde
+{
+	echo "#include <$(ARDUINO_H)>" > $(<) 
+	echo "#line 1 \"$(>)\"" >> $(<)
+	cat $(>) >> $(<) 
+}
+
+rule C++Pde
+{
+	local _CPP = $(>:B).cpp ;
+	Pde $(_CPP) : $(>) ;
+	C++ $(<) : $(_CPP) ;
+}
+
+rule UserObject
+{
+	switch $(>:S)
+	{
+		case .ino : C++Pde $(<) : $(>) ;
+		case .pde : C++Pde $(<) : $(>) ;
+	}
+}
+
+rule Objects
+{
+        local _i ;
+
+        for _i in [ FGristFiles $(<) ]
+        {
+		local _b = $(_i:B)$(SUFOBJ) ;
+		local _o = $(_b:G=$(SOURCE_GRIST:E)) ;
+                Object $(_o) : $(_i) ;
+                Depends obj : $(_o) ;
+        }
+}
+
+rule Main
+{
+        MainFromObjects $(<) : $(>:B)$(SUFOBJ) ;
+        Objects $(>) ;
+}
+
+rule Hex
+{
+	Depends $(<) : $(>) ;
+	MakeLocate $(<) : $(LOCATE_TARGET) ;
+	Depends hex : $(<) ;
+	Clean clean : $(<) ;
+}
+
+actions Hex
+{
+	$(OBJCOPY) -O ihex -R .eeprom $(>) $(<)
+}
+
+rule Upload
+{
+	Depends $(1) : $(2) ;
+	Depends $(2) : $(3) ;
+	NotFile $(1) ;
+	Always $(1) ;
+	Always $(2) ;
+	UploadAction $(2) : $(3) ;
+}
+
+actions UploadAction
+{
+	$(AVRDUDE) $(AVRDUDEFLAGS) -P $(<) $(AVRDUDE_WRITE_FLASH) -U flash:w:$(>):i
+}
+
+#
+# Targets
+#
+
+# Grab everything from the core directory
+CORE_MODULES  	= [ GLOB $(ARDUINO_CORE) : *.c *.cpp ] ;
+
+# Grab everything from libraries.  To avoid this "grab everything" behaviour, you
+# can specify specific modules to pick up in PROJECT_MODULES
+LIB_MODULES  	= [ GLOB $(ARDUINO_LIB)/$(PROJECT_LIBS) $(ARDUINO_LIB)/$(PROJECT_LIBS)/utility $(SKETCH_LIB)/$(PROJECT_LIBS) : *.cpp *.c ] ;
+
+# Grab everything from the current dir
+PROJECT_MODULES += [ GLOB $(PWD) : *.c *.cpp *.pde *.ino ] ;
+
+# Main output executable
+MAIN		= $(PWD:B).elf ;
+
+Main $(MAIN) : $(CORE_MODULES) $(LIB_MODULES) $(PROJECT_MODULES) ;
+Hex $(MAIN:B).hex : $(MAIN) ;
+
+# Upload targets
+for _p in $(PORTS)
+{
+	Upload $(_p) : $(PORT_$(_p)) : $(MAIN:B).hex ;
+}
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/README b/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/README
new file mode 100644
index 0000000..fc25399
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/README
@@ -0,0 +1,19 @@
+This is the 'receiver' for the unit tests.  Run it on a node which
+is NOT under test.
+
+TODO
+
+Send finder request needs a re-think.  It needs to be re-implemented as a Tictocs::Timer, so it
+doesn't block the loop().
+
+I could also make Tictocs objects which monitor the RF24network and pull off messages that are just
+for them.  Likewise, the network can raise a signal when there is a new message.  Although I would not
+want to put that into the library for fear of adding a dependency.
+
+so the finder needs to maintain state
+- Waiting: Waiting for a finder request
+- Sending: In the midst of looping through children
+
+Needs to have some delay between each send.  So the finder has a timer component.
+
+Also...  Reset should also reset the internal copy of the sync data.  Sync may need a 'reset' method.
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/printf.h b/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/printf.h
new file mode 100644
index 0000000..1b853db
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/printf.h
@@ -0,0 +1,31 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+ 
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+ 
+/**
+ * @file printf.h
+ *
+ * Setup necessary to direct stdout to the Arduino Serial library, which
+ * enables 'printf'
+ */
+
+#ifndef __PRINTF_H__
+#define __PRINTF_H__
+
+int serial_putc( char c, FILE * ) 
+{
+  Serial.write( c );
+
+  return c;
+} 
+
+void printf_begin(void)
+{
+  fdevopen( &serial_putc, 0 );
+}
+
+#endif // __PRINTF_H__
diff --git a/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/unit_rx.pde b/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/unit_rx.pde
new file mode 100644
index 0000000..3c57108
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RF24Network/tests/unit_rx/unit_rx.pde
@@ -0,0 +1,135 @@
+/*
+ Copyright (C) 2011 James Coliz, Jr. 
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License
+ version 2 as published by the Free Software Foundation.
+ */
+
+/**
+ * Receiver for unit tests.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include "Finder.h"
+#include "printf.h"
+
+// nRF24L01(+) radio attached to SPI and pins 8 & 9
+RF24 radio(8,9);
+
+// Network uses that radio
+RF24Network network(radio);
+
+// Syncronizer
+Sync sync(network);
+
+// Address of our node
+#if NODE > 0
+const uint16_t this_node = NODE;
+#else
+const uint16_t this_node = 1;
+#endif
+
+// Address of the other node
+const uint16_t other_node = 0;
+
+// Data to be synchronized
+struct sync_data_t
+{
+  uint16_t first;
+  uint16_t second;
+
+  sync_data_t(void): first(1), second(2) {}
+};
+
+sync_data_t sync_data;
+
+// Old value of 'first'
+uint16_t old_first;
+
+// Message buffer space
+uint8_t message[32];
+
+void send_finder_request(void);
+void net_delay(unsigned long amount);
+
+Finder finder;
+
+void setup(void)
+{
+  Serial.begin(57600);
+  Serial.println("RF24Network/test/unit_rx/");
+  printf_begin();
+ 
+  SPI.begin();
+  radio.begin();
+  network.begin(/*channel*/ 100, /*node address*/ this_node);
+  finder.begin(this_node);
+
+  sync.register_me(sync_data);
+  old_first = sync_data.first;
+}
+
+void loop(void)
+{
+  // Pump the network regularly
+  sync.update();
+
+  // Stay on the lookout for finder messages
+  finder.update();
+
+  // Have the values changed?
+  if ( old_first != sync_data.first )
+  {
+    printf_P(PSTR("%lu: APP Updated first to %u\n\r"),millis(),sync_data.first);
+
+      // Move the first value over to the second
+    sync_data.second = sync_data.first;
+
+    // And remember the change for next time
+    old_first = sync_data.first;
+  }
+
+  // Are there any messages for us?
+  while ( network.available() )
+  {
+    uint16_t from;
+    
+    // If so, take a look at it 
+    RF24NetworkHeader header;
+    network.peek(header);
+    
+    // Dispatch the message to the correct handler.
+    switch (header.type)
+    {
+    // Reset to initial state
+    case 'R':
+      network.read(header,0,0);
+      printf_P(PSTR("%lu: APP Reset to initial state\n\r"),millis());
+
+      sync_data = sync_data_t();
+      old_first = sync_data.first;
+      sync.reset();
+      break;
+    
+    // Echo back to the sender.
+    case 'E':
+      network.read(header,message,sizeof(message));
+      from = header.from_node;
+      printf_P(PSTR("%lu: APP Received ECHO request from %o\n\r"),millis(),from);
+      network.write(header = RF24NetworkHeader(from,'E'),message,sizeof(message));
+      break;
+    
+    // Unrecognized message type
+    default:
+      printf_P(PSTR("*** WARNING *** Unknown message type %c\n\r"),header.type);
+      network.read(header,0,0);
+      break;
+    };
+  }
+}
+
+// vim:ai:cin:sts=2 sw=2 ft=cpp
diff --git a/hardware/digistump/sam/libraries/RTC/.gitignore b/hardware/digistump/sam/libraries/RTC/.gitignore
new file mode 100644
index 0000000..620d3dc
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/.gitignore
@@ -0,0 +1,13 @@
+# Compiled Object files
+*.slo
+*.lo
+*.o
+
+# Compiled Dynamic libraries
+*.so
+*.dylib
+
+# Compiled Static libraries
+*.lai
+*.la
+*.a
diff --git a/hardware/digistump/sam/libraries/RTC/README.md b/hardware/digistump/sam/libraries/RTC/README.md
new file mode 100644
index 0000000..5c3cd35
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/README.md
@@ -0,0 +1,4 @@
+Arduino-Due-RTC-Library
+=======================
+
+RTC Library for the Arduino Due 
\ No newline at end of file
diff --git a/hardware/digistump/sam/libraries/RTC/change.log b/hardware/digistump/sam/libraries/RTC/change.log
new file mode 100644
index 0000000..1837d72
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/change.log
@@ -0,0 +1,90 @@
+2013/01/04 Due RTC Library v1.8
+added
+	- Function rtc_clock.set_clock()
+			function to set Time and Date from compliertime -/date in 1 line
+			
+fixed
+	- Bug in rtc_clock.unixtime()
+	- Bug in rtc_clock.summertime()
+
+2013/04/03 Due RTC Library v1.7
+added
+	- Function rtc_clock.date_already_set()
+			function to proof if date is already set
+	- Sketch Due_RTC_Simple_test_of_date
+			for rtc_clock.date_already_set()
+
+2013/04/03 Due RTC Library v1.6
+added
+	- Function rtc_clock.timing()
+			function to test if time and date set in summer or not musst be done in the inital
+			part when the clock is setup works in connection with rtc_clock.summertime() so
+			thats if the clock is setup in the range of summertime the function
+			rtc_clock.summertime() makes the right correct between the time changes
+			for Germany usefull
+	- Sketch Due_RTC_Simple_german_timing_summertime_sample 
+			for rtc_clock.timing() & rtc_clock.summertime()
+			
+2013/04/03 Due RTC Library v1.5
+modify
+	- Sketch Due_RTC_Simple_Germay_Summertime
+			some changes in the Sketch for an better Output on the Serialmonitor
+
+2013/04/03 Due RTC Library v1.4
+added
+	- Function rtc_clock.summertime()
+			function to show if summertime or not returns 1 for summertime (for Germany only)
+	- Sketch Due_RTC_Simple_Germay_Summertime
+			for rtc_clock.summertime()
+	- Function rtc_clock.switch_years()
+			function returns 1 if year is an switch year
+
+modify
+	- Function rtc_clock.unixtime()
+			add support for timezone Germay now summer- wintertime automatic supported
+
+2013/02/03 Due RTC Library v1.3
+modify
+	- Function rtc_clock.unixtime()
+			add support for timezones to change automatic the unixtime to the right value
+	- Sketch Due_RTC_Simple_Unixtime_timezone
+			for rtc_clock.unixtime()
+
+2013/01/03 Due RTC Library v1.2
+added
+	- Function rtc_clock.get_time()
+			to get Time in one operation
+	- Function rtc_clock.get_date()
+			to get Date in one operation
+	- Sketch Due_RTC_Simple_Sample_oneline_time_and_date
+			for rtc_clock.get_time() & rtc_clock.get_date()
+	- Changelog and versioning
+			to get some overview for me and users
+			
+modify
+	- Function rtc_clock.unixtime()
+			some changes in the codelines
+	- Sketch Due_RTC_Simple_Unixtime_Compilertime
+			some cosmetic changes in this Sketch
+		
+fixed
+	- Bug in rtc_clock.set_alarmdate function
+			wrong value name
+
+2013/28/02 Due RTC Library v1.1
+added
+	- Function rtc_clock.unixtime()
+			for unixtime support
+	- Sample Due_RTC_Simple_Unixtime_Compilertime
+			for unixtime and compilertime
+
+modify
+	- Function rtc_clock.set_time()
+			to support compilertime with the value __TIME__
+	- Function rtc_clock.set_date()
+			to support compilertime with the value __DATE__
+	- Syntax Coloring
+			set rtc_clock to KEYWORD3 now rtc_clock printed bold
+
+2012/07/12 Due RTC Library v1.0
+Initial Release
\ No newline at end of file
diff --git a/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Alarm_Sample/Due_RTC_Alarm_Sample.ino b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Alarm_Sample/Due_RTC_Alarm_Sample.ino
new file mode 100644
index 0000000..2c45924
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Alarm_Sample/Due_RTC_Alarm_Sample.ino
@@ -0,0 +1,32 @@
+#include 
+
+// Select the Slowclock source
+//RTC_clock rtc_clock(RC);
+RTC_clock rtc_clock(XTAL);
+
+char* daynames[]={"Mon", "Tue", "Wed", "Thu", "Fri", "Sat", "Sun"};
+
+void setup() {
+  Serial.begin(9600);
+  rtc_clock.init();
+  rtc_clock.set_time(10, 29, 49);
+  
+  rtc_clock.set_alarmtime(10, 30, 0);
+  
+  rtc_clock.attachalarm(announcement);
+//  rtc_clock.disable_alarm();
+}
+
+void loop() {
+  Serial.print("At the third stroke, it will be ");
+  Serial.print(rtc_clock.get_hours());
+  Serial.print(":");
+  Serial.print(rtc_clock.get_minutes());
+  Serial.print(":");
+  Serial.println(rtc_clock.get_seconds());
+}
+
+void announcement() {
+  Serial.println();
+  Serial.println("Get up and buy an Arduino Due.");
+}
diff --git a/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Germany_Summertime/Due_RTC_Simple_Germany_Summertime.ino b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Germany_Summertime/Due_RTC_Simple_Germany_Summertime.ino
new file mode 100644
index 0000000..69a402c
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Germany_Summertime/Due_RTC_Simple_Germany_Summertime.ino
@@ -0,0 +1,88 @@
+#include 
+
+// Select the Slowclock source
+//RTC_clock rtc_clock(RC);
+RTC_clock rtc_clock(XTAL);
+
+char* daynames[]={"Mon", "Tue", "Wed", "Thu", "Fri", "Sat", "Sun"};
+
+boolean toggle = false;
+int old_unixtime;
+
+void setup() {
+  Serial.begin(9600);
+  rtc_clock.init();
+  
+  //Summertimebegin Germany in 2013
+  rtc_clock.set_time(1,59,50);
+  rtc_clock.set_date(31,3,2013);
+}
+
+void loop() {
+  if ( rtc_clock.unixtime() != old_unixtime) {
+    old_unixtime = rtc_clock.unixtime();
+    output();
+  }
+  
+  if ( rtc_clock.get_seconds() == 10 ) {
+    Serial.print("Timeleap ");
+    toggle = !toggle;
+  }  
+  if ( rtc_clock.get_seconds() == 10 && toggle == false ) {
+    //Summertimebegin Germany in 2013
+    Serial.println("back to summer");
+    rtc_clock.set_time(1,59,50);
+    rtc_clock.set_date(31,3,2013);
+  } else if (rtc_clock.get_seconds() == 10 && toggle == true ) {
+    //Wintertimebegin Germany in 2013
+    Serial.println("forward to the end of summer");
+    rtc_clock.set_time(1,59,50);
+    rtc_clock.set_date(27,10,2013);
+  }
+}
+
+void output() {
+  Serial.print("Unixtime: ");
+  Serial.println(rtc_clock.unixtime(Germany));
+  
+  Serial.println("And in plain for everyone");
+  Serial.print("Time: ");
+  digitprint(rtc_clock.get_hours() + rtc_clock.summertime(), 2);
+  Serial.print(":");
+  digitprint(rtc_clock.get_minutes(), 2);
+  Serial.print(":");
+  digitprint(rtc_clock.get_seconds(), 2);
+  Serial.println("");
+  Serial.print("Date: ");
+  Serial.print(daynames[rtc_clock.get_day_of_week()-1]);
+  Serial.print(" ");
+  digitprint(rtc_clock.get_days(), 2);
+  Serial.print(".");
+  digitprint(rtc_clock.get_months(), 2);
+  Serial.print(".");
+  Serial.println(rtc_clock.get_years());
+  
+  Serial.print("Is Summertime?: ");
+  if ( rtc_clock.summertime() == 1 ) {
+    Serial.println("Yes!");
+  } else {
+    Serial.println("No!");
+  }
+  Serial.println("");
+}
+
+void digitprint(int value, int lenght){
+  for (int i = 0; i < (lenght - numdigits(value)); i++){
+    Serial.print("0");
+  }
+  Serial.print(value);
+}
+
+int numdigits(int i){
+  int digits;
+  if (i < 10)
+    digits = 1;
+  else
+    digits = (int)(log10((double)i)) + 1;
+  return digits;
+}
diff --git a/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Sample/Due_RTC_Simple_Sample.ino b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Sample/Due_RTC_Simple_Sample.ino
new file mode 100644
index 0000000..ac3bd12
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Sample/Due_RTC_Simple_Sample.ino
@@ -0,0 +1,30 @@
+#include 
+
+// Select the Slowclock source
+//RTC_clock rtc_clock(RC);
+RTC_clock rtc_clock(XTAL);
+
+char* daynames[]={"Mon", "Tue", "Wed", "Thu", "Fri", "Sat", "Sun"};
+
+void setup() {
+  Serial.begin(9600);
+  rtc_clock.init();
+  rtc_clock.set_time(10, 29, 9);
+  rtc_clock.set_date(22, 10, 2012);
+}
+
+void loop() {
+  Serial.print("At the third stroke, it will be ");
+  Serial.print(rtc_clock.get_hours());
+  Serial.print(":");
+  Serial.print(rtc_clock.get_minutes());
+  Serial.print(":");
+  Serial.println(rtc_clock.get_seconds());
+  Serial.print(daynames[rtc_clock.get_day_of_week()-1]);
+  Serial.print(": ");
+  Serial.print(rtc_clock.get_days());
+  Serial.print(".");
+  Serial.print(rtc_clock.get_months());
+  Serial.print(".");
+  Serial.println(rtc_clock.get_years());
+}
diff --git a/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Sample_oneline_time_and_date/Due_RTC_Simple_Sample_oneline_time_and_date.ino b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Sample_oneline_time_and_date/Due_RTC_Simple_Sample_oneline_time_and_date.ino
new file mode 100644
index 0000000..31b3933
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Sample_oneline_time_and_date/Due_RTC_Simple_Sample_oneline_time_and_date.ino
@@ -0,0 +1,52 @@
+#include 
+
+// Select the Slowclock source
+//RTC_clock rtc_clock(RC);
+RTC_clock rtc_clock(XTAL);
+
+char* daynames[]={"Mon", "Tue", "Wed", "Thu", "Fri", "Sat", "Sun"};
+int hh,mm,ss,dow,dd,mon,yyyy;
+
+void setup() {
+  Serial.begin(9600);
+  rtc_clock.init();
+  rtc_clock.set_time(__TIME__);
+  rtc_clock.set_date(__DATE__);
+}
+
+void loop() {
+  Serial.print("Time: ");
+  rtc_clock.get_time(&hh,&mm,&ss);
+  rtc_clock.get_date(&dow,&dd,&mon,&yyyy);
+  digitprint(hh, 2);
+  Serial.print(":");
+  digitprint(mm, 2);
+  Serial.print(":");
+  digitprint(ss, 2);
+  Serial.println("");
+  Serial.print("Date: ");
+  Serial.print(daynames[dow-1]);
+  Serial.print(" ");
+  digitprint(dd, 2);
+  Serial.print(".");
+  digitprint(mon, 2);
+  Serial.print(".");
+  Serial.println(yyyy);
+  Serial.println("");
+}
+
+void digitprint(int value, int lenght){
+  for (int i = 0; i < (lenght - numdigits(value)); i++){
+    Serial.print("0");
+  }
+  Serial.print(value);
+}
+
+int numdigits(int i){
+  int digits;
+  if (i < 10)
+    digits = 1;
+  else
+    digits = (int)(log10((double)i)) + 1;
+  return digits;
+}
diff --git a/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Unixtime_Compilertime/Due_RTC_Simple_Unixtime_Compilertime.ino b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Unixtime_Compilertime/Due_RTC_Simple_Unixtime_Compilertime.ino
new file mode 100644
index 0000000..2739c69
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Unixtime_Compilertime/Due_RTC_Simple_Unixtime_Compilertime.ino
@@ -0,0 +1,52 @@
+#include 
+
+// Select the Slowclock source
+//RTC_clock rtc_clock(RC);
+RTC_clock rtc_clock(XTAL);
+
+char* daynames[]={"Mon", "Tue", "Wed", "Thu", "Fri", "Sat", "Sun"};
+
+void setup() {
+  Serial.begin(9600);
+  rtc_clock.init();
+  rtc_clock.set_time(__TIME__);
+  rtc_clock.set_date(__DATE__);
+}
+
+void loop() {
+  Serial.print("Unixtime: ");
+  Serial.println(rtc_clock.unixtime());
+  Serial.println("And in plain for everyone");
+  Serial.print("Time: ");
+  digitprint(rtc_clock.get_hours(), 2);
+  Serial.print(":");
+  digitprint(rtc_clock.get_minutes(), 2);
+  Serial.print(":");
+  digitprint(rtc_clock.get_seconds(), 2);
+  Serial.println("");
+  Serial.print("Date: ");
+  Serial.print(daynames[rtc_clock.get_day_of_week()-1]);
+  Serial.print(" ");
+  digitprint(rtc_clock.get_days(), 2);
+  Serial.print(".");
+  digitprint(rtc_clock.get_months(), 2);
+  Serial.print(".");
+  Serial.println(rtc_clock.get_years());
+  Serial.println("");
+}
+
+void digitprint(int value, int lenght){
+  for (int i = 0; i < (lenght - numdigits(value)); i++){
+    Serial.print("0");
+  }
+  Serial.print(value);
+}
+
+int numdigits(int i){
+  int digits;
+  if (i < 10)
+    digits = 1;
+  else
+    digits = (int)(log10((double)i)) + 1;
+  return digits;
+}
diff --git a/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Unixtime_timezone/Due_RTC_Simple_Unixtime_timezone.ino b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Unixtime_timezone/Due_RTC_Simple_Unixtime_timezone.ino
new file mode 100644
index 0000000..78fbe69
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_Unixtime_timezone/Due_RTC_Simple_Unixtime_timezone.ino
@@ -0,0 +1,53 @@
+#include 
+
+// Select the Slowclock source
+//RTC_clock rtc_clock(RC);
+RTC_clock rtc_clock(XTAL);
+
+char* daynames[]={"Mon", "Tue", "Wed", "Thu", "Fri", "Sat", "Sun"};
+
+void setup() {
+  Serial.begin(9600);
+  rtc_clock.init();
+  rtc_clock.set_time(__TIME__);
+  rtc_clock.set_date(__DATE__);
+}
+
+void loop() {
+  Serial.print("Unixtime: ");
+  //All known Timezones are supported set in this style "UTC+1" or "UTC-930" without colon
+  Serial.println(rtc_clock.unixtime(UTC-5));
+  Serial.println("And in plain for everyone");
+  Serial.print("Time: ");
+  digitprint(rtc_clock.get_hours(), 2);
+  Serial.print(":");
+  digitprint(rtc_clock.get_minutes(), 2);
+  Serial.print(":");
+  digitprint(rtc_clock.get_seconds(), 2);
+  Serial.println("");
+  Serial.print("Date: ");
+  Serial.print(daynames[rtc_clock.get_day_of_week()-1]);
+  Serial.print(" ");
+  digitprint(rtc_clock.get_days(), 2);
+  Serial.print(".");
+  digitprint(rtc_clock.get_months(), 2);
+  Serial.print(".");
+  Serial.println(rtc_clock.get_years());
+  Serial.println("");
+}
+
+void digitprint(int value, int lenght){
+  for (int i = 0; i < (lenght - numdigits(value)); i++){
+    Serial.print("0");
+  }
+  Serial.print(value);
+}
+
+int numdigits(int i){
+  int digits;
+  if (i < 10)
+    digits = 1;
+  else
+    digits = (int)(log10((double)i)) + 1;
+  return digits;
+}
diff --git a/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_german_timing_summertime_sample/Due_RTC_Simple_german_timing_summertime_sample.ino b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_german_timing_summertime_sample/Due_RTC_Simple_german_timing_summertime_sample.ino
new file mode 100644
index 0000000..1dd953e
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_german_timing_summertime_sample/Due_RTC_Simple_german_timing_summertime_sample.ino
@@ -0,0 +1,88 @@
+#include 
+
+// Select the Slowclock source
+//RTC_clock rtc_clock(RC);
+RTC_clock rtc_clock(XTAL);
+
+char* daynames[]={"Mon", "Tue", "Wed", "Thu", "Fri", "Sat", "Sun"};
+
+boolean toggle = false;
+int old_unixtime;
+
+void setup() {
+  Serial.begin(9600);
+  rtc_clock.init();
+  
+  rtc_clock.set_time(1,59,50);
+  rtc_clock.set_date(15,6,2013);
+  rtc_clock.timing();
+}
+
+void loop() {
+  if ( rtc_clock.unixtime() != old_unixtime) {
+    old_unixtime = rtc_clock.unixtime();
+    output();
+  }
+  
+  if ( rtc_clock.get_seconds() == 10 ) {
+    Serial.print("Timeleap ");
+    toggle = !toggle;
+  }  
+  if ( rtc_clock.get_seconds() == 10 && toggle == false ) {
+    //Summertimebegin Germany in 2013
+    Serial.println("back to summer");
+    rtc_clock.set_time(1,59,50);
+    rtc_clock.set_date(31,3,2013);
+  } else if (rtc_clock.get_seconds() == 10 && toggle == true ) {
+    //Wintertimebegin Germany in 2013
+    Serial.println("forward to the end of summer");
+    rtc_clock.set_time(1,59,50);
+    rtc_clock.set_date(27,10,2013);
+  }
+}
+
+void output() {
+  Serial.print("Unixtime: ");
+  Serial.println(rtc_clock.unixtime(Germany));
+  
+  Serial.println("And in plain for everyone");
+  Serial.print("Time: ");
+  digitprint(rtc_clock.get_hours() + rtc_clock.summertime(), 2);
+  Serial.print(":");
+  digitprint(rtc_clock.get_minutes(), 2);
+  Serial.print(":");
+  digitprint(rtc_clock.get_seconds(), 2);
+  Serial.println("");
+  Serial.print("Date: ");
+  Serial.print(daynames[rtc_clock.get_day_of_week()-1]);
+  Serial.print(" ");
+  digitprint(rtc_clock.get_days(), 2);
+  Serial.print(".");
+  digitprint(rtc_clock.get_months(), 2);
+  Serial.print(".");
+  Serial.println(rtc_clock.get_years());
+  
+  Serial.print("Is Summertime?: ");
+  if ( rtc_clock.summertime() == 1 ) {
+    Serial.println("Yes!");
+  } else {
+    Serial.println("No!");
+  }
+  Serial.println("");
+}
+
+void digitprint(int value, int lenght){
+  for (int i = 0; i < (lenght - numdigits(value)); i++){
+    Serial.print("0");
+  }
+  Serial.print(value);
+}
+
+int numdigits(int i){
+  int digits;
+  if (i < 10)
+    digits = 1;
+  else
+    digits = (int)(log10((double)i)) + 1;
+  return digits;
+}
diff --git a/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_test_of_date/Due_RTC_Simple_test_of_date.ino b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_test_of_date/Due_RTC_Simple_test_of_date.ino
new file mode 100644
index 0000000..b86d37c
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/examples/Due_RTC_Simple_test_of_date/Due_RTC_Simple_test_of_date.ino
@@ -0,0 +1,55 @@
+#include 
+
+#define START_VALUE    "Jan 01 2007"
+
+// Select the Slowclock source
+//RTC_clock rtc_clock(RC);
+RTC_clock rtc_clock(XTAL);
+
+int counter = 0;
+
+void setup() {
+  Serial.begin(9600);
+  rtc_clock.init();
+}
+
+void loop() {
+  if (rtc_clock.date_already_set() == 0) {
+    Serial.print("no  ");
+  } else {
+    Serial.print("yes ");
+  }
+  digitprint(counter, 3, 1);
+  Serial.println();
+  delay(125);
+  if (counter == 50) {
+    rtc_clock.set_date(__DATE__);
+  }
+  if (counter == 100) {
+    counter = 0;
+    // technical all the same
+    //rtc_clock.set_date( 1,  1, 2007);
+    //rtc_clock.set_date("Jan 01 2007");
+    rtc_clock.set_date(START_VALUE);
+  }
+  counter++;
+}
+
+void digitprint(int value, int lenght, int placeholder){
+  for (int i = 0; i < (lenght - numdigits(value)); i++){
+    if (placeholder == 0)
+      Serial.print("0");
+    else
+      Serial.print(" ");
+  }
+  Serial.print(value);
+}
+
+int numdigits(int i){
+  int digits;
+  if (i < 10)
+    digits = 1;
+  else
+    digits = (int)(log10((double)i)) + 1;
+  return digits;
+}
diff --git a/hardware/digistump/sam/libraries/RTC/keywords.txt b/hardware/digistump/sam/libraries/RTC/keywords.txt
new file mode 100644
index 0000000..098764f
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/keywords.txt
@@ -0,0 +1,65 @@
+#######################################
+# Syntax Coloring Map For Due-RTC
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+RTC_clock 	KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+init 	KEYWORD2
+set_time 	KEYWORD2
+set_date 	KEYWORD2
+set_seconds 	KEYWORD2
+set_minutes 	KEYWORD2
+set_hours 	KEYWORD2
+set_days 	KEYWORD2
+set_months 	KEYWORD2
+set_years 	KEYWORD2
+set_alarmtime 	KEYWORD2
+set_alarmdate 	KEYWORD2
+get_seconds 	KEYWORD2
+get_minutes 	KEYWORD2
+get_hours 	KEYWORD2
+get_days 	KEYWORD2
+get_day_of_week 	KEYWORD2
+get_months 	KEYWORD2
+get_years 	KEYWORD2
+attachalarm 	KEYWORD2
+disable_alarm 	KEYWORD2
+unixtime 	KEYWORD2
+get_time 	KEYWORD2
+get_date 	KEYWORD2
+summertime 	KEYWORD2
+switch_years 	KEYWORD2
+timing 	KEYWORD2
+date_already_set 	KEYWORD2
+set_clock 	KEYWORD2
+
+#######################################
+# Instances (KEYWORD2)
+#######################################
+
+
+#######################################
+# Mean Instances (KEYWORD3)
+#######################################
+
+rtc_clock 	KEYWORD3
+
+#######################################
+# Constants (LITERAL1)
+#######################################
+
+RC 	LITERAL1
+XTAL 	LITERAL1
+
+__TIME__	LITERAL1
+__DATE__	LITERAL1
+
+Germany	LITERAL1
\ No newline at end of file
diff --git a/hardware/digistump/sam/libraries/RTC/rtc_clock.cpp b/hardware/digistump/sam/libraries/RTC/rtc_clock.cpp
new file mode 100644
index 0000000..1610d49
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/rtc_clock.cpp
@@ -0,0 +1,729 @@
+#include "rtc_clock.h"
+#include 
+#include 
+#include 
+#include "Arduino.h"
+
+int daysInMonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
+int meztime;
+
+RTC_clock::RTC_clock (int source)
+{
+	_source = source;
+	
+	if (_source) {
+		pmc_switch_sclk_to_32kxtal(0);
+	
+		while (!pmc_osc_is_ready_32kxtal());
+	}
+}
+
+void RTC_clock::init ()
+{
+	RTC_SetHourMode(RTC, 0);
+	
+	NVIC_DisableIRQ(RTC_IRQn);
+	NVIC_ClearPendingIRQ(RTC_IRQn);
+	NVIC_SetPriority(RTC_IRQn, 0);
+//	NVIC_EnableIRQ(RTC_IRQn);
+//	RTC_EnableIt(RTC, RTC_IER_SECEN | RTC_IER_ALREN);
+//	RTC_EnableIt(RTC, RTC_IER_SECEN);
+}
+
+void RTC_clock::set_time (int hour, int minute, int second)
+{
+	_hour = hour;
+	_minute = minute;
+	_second = second;
+	RTC_SetTime (RTC, _hour, _minute, _second);
+}
+
+int conv2d(char* p)
+{
+	int v = 0;
+  if ('0' <= *p && *p <= '9')
+  	v = *p - '0';
+  return 10 * v + *++p - '0';
+}
+
+void RTC_clock::set_time (char* time)
+{
+	_hour = conv2d(time);
+	_minute = conv2d(time + 3);
+	_second = conv2d(time + 6);
+	RTC_SetTime (RTC, _hour, _minute, _second);
+}
+
+uint32_t RTC_clock::current_time ()
+{
+	uint32_t dwTime;
+
+	/* Get current RTC time */
+	dwTime = RTC->RTC_TIMR ;
+	while ( dwTime != RTC->RTC_TIMR ) {
+		dwTime = RTC->RTC_TIMR ;
+	}
+	return (dwTime);
+}
+
+void RTC_clock::get_time (int *hour, int *minute, int *second)
+{
+	RTC_GetTime(RTC, (uint8_t*)hour, (uint8_t*)minute, (uint8_t*)second);
+}
+
+int RTC_clock::get_hours ()
+{
+	_current_time = current_time();
+	
+	return (((_current_time & 0x00300000) >> 20) * 10 + ((_current_time & 0x000F0000) >> 16));
+}
+
+int RTC_clock::get_minutes ()
+{
+	_current_time = current_time();
+	
+	return (((_current_time & 0x00007000) >> 12) * 10 + ((_current_time & 0x00000F00) >> 8));
+}
+
+int RTC_clock::get_seconds ()
+{
+	_current_time = current_time();
+	
+	return (((_current_time & 0x00000070) >> 4) * 10 + ((_current_time & 0x0000000F)));
+}
+
+/**
+ * \brief Calculate day_of_week from year, month, day.
+ */
+int RTC_clock::calculate_day_of_week (uint16_t _year, int _month, int _day)
+{
+	int _week;
+
+	if (_month == 1 || _month == 2) {
+		_month += 12;
+		--_year;
+	}
+
+	_week = (_day + 2 * _month + 3 * (_month + 1) / 5 + _year + _year / 4 - _year / 100 + _year / 400) % 7;
+
+	++_week;
+
+	return _week;
+}
+
+void RTC_clock::set_date (int day, int month, uint16_t year)
+{
+	_day = day;
+	_month = month;
+	_year = year;
+	_day_of_week = calculate_day_of_week(_year, _month, _day);
+	
+	daysInMonth[1] = 28 + switch_years (_year);
+	
+	RTC_SetDate (RTC, (uint16_t)_year, (uint8_t)_month, (uint8_t)_day, (uint8_t)_day_of_week);
+}
+
+void RTC_clock::set_date (char* date)
+{
+	_day = conv2d(date + 4);
+	
+	//Month
+	switch (date[0]) {
+    case 'J': _month = date[1] == 'a' ? 1 : _month = date[2] == 'n' ? 6 : 7; break;
+    case 'F': _month = 2; break;
+    case 'A': _month = date[2] == 'r' ? 4 : 8; break;
+    case 'M': _month = date[2] == 'r' ? 3 : 5; break;
+    case 'S': _month = 9; break;
+    case 'O': _month = 10; break;
+    case 'N': _month = 11; break;
+    case 'D': _month = 12; break;
+  }
+
+	_year = conv2d(date + 9);
+	_day_of_week = calculate_day_of_week(_year, _month, _day);
+	
+	daysInMonth[1] = 28 + switch_years (_year);
+	
+	RTC_SetDate (RTC, (uint16_t)_year, (uint8_t)_month, (uint8_t)_day, (uint8_t)_day_of_week);
+}
+
+uint32_t RTC_clock::current_date ()
+{
+	uint32_t dwTime;
+
+	/* Get current RTC date */
+	dwTime = RTC->RTC_CALR ;
+	while ( dwTime != RTC->RTC_CALR ) {
+		dwTime = RTC->RTC_CALR ;
+	}
+	return (dwTime);
+}
+
+int RTC_clock::date_already_set ()
+{
+	uint32_t dateregister;
+
+	/* Get current RTC date */
+	dateregister = current_date ();
+	
+	if ( RESET_VALUE != dateregister ) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+
+
+// set the internal clock using a timestamp using the epoch passed as argument
+uint8_t RTC_clock::set_timestamp(uint32_t timestamp, uint16_t epoch) {
+	uint32_t dayT;
+
+	if (timestamp > 951847199UL) { timestamp -= 86400UL; } //year 2000 is a special leap year, so 1 day must be added if date is greater than 29/02/2000
+	timestamp += 86400UL; //days in the calendar start from Jan., 1 not from Jan., 0
+	dayT = timestamp / (60UL * 60UL * 24UL);
+	float remaining = timestamp - dayT * (60UL * 60UL * 24UL);
+	uint16_t yearT = (dayT / 365.2422);
+	float dayRemaining = dayT - yearT * 365.2422;
+
+	if (epoch == 0) {
+		epoch = 1970;
+	} else if (epoch < 1900) {
+		epoch = 1900;
+	} else if (epoch > 1970) {
+		epoch = 1970;
+	} else if ((epoch != 1900) && (epoch != 1970)) {
+		epoch = 1970;
+	}
+
+	yearT += epoch;
+	if (dayRemaining >= 365.2422) {
+		return 1;//my math is wrong!
+    }
+	if (yearT < epoch) {
+		return 2;//year not supported!
+    }
+	uint8_t monthT = 0;
+	while (dayRemaining > daysInMonth[monthT]){
+		dayRemaining -= daysInMonth[monthT];
+		if (monthT == 1 && (((yearT % 4) == 0) && ((yearT % 100) != 0) || ((yearT % 400) == 0))) {
+			dayRemaining--;
+		}
+		monthT++;
+	}
+
+	monthT++;//because month 0 doesn't exist
+	if (monthT > 12) {
+		return 3;//my math is wrong!
+    }
+	if (dayRemaining >= (60UL*60UL*24UL)) {
+		return 4;//my math is wrong!
+    }
+	dayT = dayRemaining;
+	if (dayRemaining - dayT > 0){ //add partial day!
+		dayT++;
+	}
+	uint8_t hoursT = remaining / (60UL * 60UL);
+	remaining = remaining - hoursT * (60UL * 60UL);
+	if (remaining >= (60UL * 60UL)) {
+		return 5;//my math is wrong!
+    }
+	uint8_t minutesT = remaining / 60UL;
+	remaining = remaining - minutesT * 60UL;
+	if (remaining >= 60) {
+		return 6;//my math is wrong!
+    }
+	set_time(hoursT, minutesT, remaining);
+	set_date(dayT, monthT, yearT);
+	return 0;
+}
+
+
+void RTC_clock::get_date (int *day_of_week, int *day, int *month, int *year)
+{
+	RTC_GetDate(RTC, (uint16_t*)year, (uint8_t*)month, (uint8_t*)day, (uint8_t*)day_of_week);
+}
+
+uint16_t RTC_clock::get_years ()
+{
+	_current_date = current_date();
+	
+	return ((((_current_date >> 4) & 0x7) * 1000) + ((_current_date & 0xF) * 100)
+  						+ (((_current_date >> 12) & 0xF) * 10) + ((_current_date >> 8) & 0xF));
+}
+
+int RTC_clock::get_months ()
+{
+	_current_date = current_date();
+	
+	return ((((_current_date >> 20) & 1) * 10) + ((_current_date >> 16) & 0xF));
+}
+
+int RTC_clock::get_days ()
+{
+	_current_date = current_date();
+	
+	return ((((_current_date >> 28) & 0x3) * 10) + ((_current_date >> 24) & 0xF));
+}
+
+int RTC_clock::get_day_of_week ()
+{
+	_current_date = current_date();
+	
+	return (((_current_date >> 21) & 0x7));
+}
+
+int RTC_clock::set_hours (int hour)
+{
+	_hour = hour;
+	uint32_t _current_time = current_time();
+	uint32_t _changed;
+	
+	_changed = ((_hour%10) | ((_hour/10)<<4))<<16 ;
+	
+	_current_time = (_current_time & 0xFFC0FFFF) ^ _changed ;
+	
+	change_time(_current_time);
+}
+
+int RTC_clock::set_minutes (int minute)
+{
+	_minute = minute;
+	uint32_t _current_time = current_time();
+	uint32_t _changed;
+	
+	_changed = ((_minute%10) | ((_minute/10)<<4))<<8 ;
+	
+	_current_time = (_current_time & 0xFFFF80FF) ^ _changed ;
+	
+	change_time(_current_time);
+}
+
+int RTC_clock::set_seconds (int second)
+{
+	_second = second;
+	uint32_t _current_time = current_time();
+	uint32_t _changed;
+	
+	_changed = ((_second%10) | ((_second/10)<<4)) ;
+	
+	_current_time = (_current_time & 0xFFFFFF80) ^ _changed ;
+	
+	change_time(_current_time);
+}
+
+uint32_t RTC_clock::change_time (uint32_t now)
+{
+	_now = now;
+	
+	RTC->RTC_CR |= RTC_CR_UPDTIM ;
+	while ((RTC->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;
+	RTC->RTC_SCCR = RTC_SCCR_ACKCLR ;
+	RTC->RTC_TIMR = _now ;
+	RTC->RTC_CR &= (uint32_t)(~RTC_CR_UPDTIM) ;
+	RTC->RTC_SCCR |= RTC_SCCR_SECCLR ;
+		
+	return (int)(RTC->RTC_VER & RTC_VER_NVTIM) ;
+}
+
+int RTC_clock::set_days (int day)
+{
+	_day = day;
+	uint32_t _current_date = current_date();
+	uint32_t _changed;
+	
+	_day_of_week = calculate_day_of_week(get_years(), get_months(), _day) ;
+	_day_of_week = ((_day_of_week%10) | (_day_of_week/10)<<4)<<21 ;
+	
+	_changed = ((_day%10) | (_day/10)<<4)<<24 ;
+	
+	_current_date = (_current_date & (0xC0FFFFFF & 0xFF1FFFFF) ) ^ ( _changed | _day_of_week ) ;
+	
+	change_date(_current_date);
+}
+
+int RTC_clock::set_months (int month)
+{
+	_month = month;
+	uint32_t _current_date = current_date();
+	uint32_t _changed;
+	
+	_day_of_week = calculate_day_of_week(get_years(), _month, get_days()) ;
+	_day_of_week = ((_day_of_week%10) | (_day_of_week/10)<<4)<<21 ;
+	
+	_changed = ((_month%10) | (_month/10)<<4)<<16 ;
+	
+	_current_date = (_current_date & (0xFFE0FFFF & 0xFF1FFFFF) ) ^ ( _changed | _day_of_week ) ;
+	
+	change_date(_current_date);
+}
+
+int RTC_clock::set_years (uint16_t year)
+{
+	_year = year;
+	uint32_t _current_date = current_date();
+	uint32_t _changed;
+	
+	_day_of_week = calculate_day_of_week(_year, get_months(), get_days()) ;
+	_day_of_week = ((_day_of_week%10) | (_day_of_week/10)<<4)<<21 ;
+		
+	_changed = (((_year/100)%10) | ((_year/1000)<<4)) | ((_year%10) | (((_year/10)%10))<<4)<<8 ;
+	
+	_current_date = (_current_date & (0xFFFF0080 & 0xFF1FFFFF) ) ^ ( _changed | _day_of_week ) ;
+	
+	daysInMonth[1] = 28 + switch_years (_year);
+	
+	change_date(_current_date);
+}
+
+uint32_t RTC_clock::change_date (uint32_t now)
+{
+	_now = now;
+	
+	RTC->RTC_CR |= RTC_CR_UPDCAL ;
+	while ((RTC->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;
+	RTC->RTC_SCCR = RTC_SCCR_ACKCLR ;
+	RTC->RTC_CALR = _now ;
+	RTC->RTC_CR &= (uint32_t)(~RTC_CR_UPDCAL) ;
+	RTC->RTC_SCCR |= RTC_SCCR_SECCLR ;
+		
+	return (int)(RTC->RTC_VER & RTC_VER_NVCAL) ;
+}
+
+void RTC_clock::set_clock (char* date, char* time)
+{
+  uint32_t wDate ;
+  uint32_t dwTime=0 ;
+
+	_day = conv2d(date + 4);
+	
+	//Month
+	switch (date[0]) {
+    case 'J': _month = date[1] == 'a' ? 1 : _month = date[2] == 'n' ? 6 : 7; break;
+    case 'F': _month = 2; break;
+    case 'A': _month = date[2] == 'r' ? 4 : 8; break;
+    case 'M': _month = date[2] == 'r' ? 3 : 5; break;
+    case 'S': _month = 9; break;
+    case 'O': _month = 10; break;
+    case 'N': _month = 11; break;
+    case 'D': _month = 12; break;
+  }
+
+	_year = conv2d(date + 9);
+	_day_of_week = calculate_day_of_week(_year, _month, _day);
+	
+	daysInMonth[1] = 28 + switch_years (_year);
+  
+	_hour = conv2d(time);
+	_minute = conv2d(time + 3);
+	_second = conv2d(time + 6);
+
+  uint8_t _yearcent  = ((_year/100)%10) | ((_year/1000)<<4);
+  _year  = (_year%10)       | (((_year/10)%10)<<4);
+  _month = ((_month%10)    | (_month/10)<<4);
+  _day   = ((_day%10)      | (_day/10)<<4);
+  _day_of_week  = ((_day_of_week%10)     | (_day_of_week/10)<<4);
+    
+  _hour = (_hour%10)   | ((_hour/10)<<4) ;
+  _minute  = (_minute%10) | ((_minute/10)<<4) ;
+  _second  = (_second%10) | ((_second/10)<<4) ;
+
+  /* Convert values to register value */
+  wDate = _yearcent | (_year << 8) | (_month << 16) | (_day_of_week << 21) | (_day << 24);
+            
+  dwTime = _second | (_minute << 8) | (_hour<<16) ;
+
+	/* Update time register  */
+  RTC->RTC_CR |= RTC_CR_UPDTIM ;
+  while ((RTC->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;
+    
+  RTC->RTC_SCCR = RTC_SCCR_ACKCLR ;
+  RTC->RTC_TIMR = dwTime ;
+  // waiting for second event
+  while ((RTC->RTC_SR & RTC_SR_SEC) != RTC_SR_SEC) ;
+  RTC->RTC_CR &= (uint32_t)(~RTC_CR_UPDTIM) ;
+  RTC->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */
+   
+  /* Update calendar register  */
+  RTC->RTC_CR |= RTC_CR_UPDCAL ;
+  while ((RTC->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;
+
+  RTC->RTC_SCCR = RTC_SCCR_ACKCLR;
+  RTC->RTC_CALR = wDate ;
+  // waiting for second event
+  while ((RTC->RTC_SR & RTC_SR_SEC) != RTC_SR_SEC) ;
+  RTC->RTC_CR &= (uint32_t)(~RTC_CR_UPDCAL) ;
+  RTC->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */
+}
+
+void (*useralarmFunc)(void);
+
+void RTC_clock::attachalarm(void (*userFunction)(void))
+{
+	useralarmFunc = userFunction;
+}
+
+void RTC_Handler(void)
+{
+	uint32_t status = RTC->RTC_SR;
+	
+	/* Time or date alarm */
+	if ((status & RTC_SR_ALARM) == RTC_SR_ALARM) {
+		/* Disable RTC interrupt */
+		RTC_DisableIt(RTC, RTC_IDR_ALRDIS);
+		
+		//Bepfehl ausführen
+		useralarmFunc();
+
+		/* Clear notification */
+		RTC_ClearSCCR(RTC, RTC_SCCR_ALRCLR);
+		RTC_EnableIt(RTC, RTC_IER_ALREN);
+	}
+}
+
+void RTC_clock::set_alarmtime (int hour, int minute, int second)
+{
+	uint8_t _hour = hour;
+	uint8_t _minute = minute;
+	uint8_t _second = second;
+	
+	RTC_EnableIt(RTC, RTC_IER_ALREN);
+	RTC_SetTimeAlarm(RTC, &_hour, &_minute, &_second);
+	NVIC_EnableIRQ(RTC_IRQn);
+}
+
+void RTC_clock::set_alarmdate (int month, int day)
+{
+	uint8_t _month = month;
+	uint8_t _day = day;
+	
+	RTC_EnableIt(RTC, RTC_IER_ALREN);
+	RTC_SetDateAlarm(RTC, &_month, &_day);
+	NVIC_EnableIRQ(RTC_IRQn);
+}
+
+uint32_t RTC_clock::unixtime()
+{
+	unixtime(0);
+}
+
+uint32_t RTC_clock::unixtime(int timezone)
+{
+	uint32_t _ticks;
+	uint16_t _days;
+	float adjustment;
+	_current_date = current_date();
+	_current_time = current_time();
+	
+	_second = (((_current_time & 0x00000070) >>  4) * 10 + ((_current_time & 0x0000000F)));
+	_minute = (((_current_time & 0x00007000) >> 12) * 10 + ((_current_time & 0x00000F00) >> 8));
+	_hour   = (((_current_time & 0x00300000) >> 20) * 10 + ((_current_time & 0x000F0000) >> 16));
+	
+	_day    = ((((_current_date >> 28) & 0x3) *   10) + ((_current_date >> 24) & 0xF));
+	_day_of_week = ((_current_date >> 21) & 0x7);
+	_month  = ((((_current_date >> 20) &   1) *   10) + ((_current_date >> 16) & 0xF));
+	//_year   = ((((_current_date >>  4) & 0x7) * 1000) + ((_current_date & 0xF) * 100)
+  //						+ (((_current_date >> 12) & 0xF) * 10) + ((_current_date >> 8) & 0xF));
+  //_year = _year - 2000;
+  						
+  _year   = (((_current_date >> 12) & 0xF) * 10) + ((_current_date >> 8) & 0xF);
+  
+  _days = _day;
+	
+	for (int i = 1; i < _month; ++i)
+  	_days += daysInMonth[i - 1];
+  if (_month > 2 && _year % 4 == 0)
+    ++_days;
+  _days += 365 * _year + (_year + 3) / 4 - 1;
+
+  _ticks = ((_days * 24 + _hour) * 60 + _minute) * 60 + _second;
+  _ticks += SECONDS_FROM_1970_TO_2000;
+  
+  if (timezone == Germany) {
+  	timezone = 1 + summertime();
+  }
+  
+	switch (timezone) {
+  case -12:
+		adjustment = -12 * SECONDS_PER_HOUR;
+		break;
+  case -11:
+		adjustment = -11 * SECONDS_PER_HOUR;
+		break;
+  case -10:
+		adjustment = -10 * SECONDS_PER_HOUR;
+		break;
+  case -930:
+		adjustment = -9.5 * SECONDS_PER_HOUR;
+		break;
+  case -9:
+		adjustment = -9 * SECONDS_PER_HOUR;
+		break;
+  case -8:
+		adjustment = -8 * SECONDS_PER_HOUR;
+		break;
+  case -7:
+		adjustment = -7 * SECONDS_PER_HOUR;
+		break;
+  case -6:
+		adjustment = -6 * SECONDS_PER_HOUR;
+		break;
+  case -5:
+		adjustment = -5 * SECONDS_PER_HOUR;
+		break;
+  case -4:
+		adjustment = -4 * SECONDS_PER_HOUR;
+		break;
+  case -330:
+		adjustment = -3.5 * SECONDS_PER_HOUR;
+		break;
+  case -3:
+		adjustment = -3 * SECONDS_PER_HOUR;
+		break;
+  case -2:
+		adjustment = -2 * SECONDS_PER_HOUR;
+		break;
+  case -1:
+		adjustment = -1 * SECONDS_PER_HOUR;
+		break;
+  case 0:
+  default:
+		adjustment = 0;
+		break;
+  case 1:
+		adjustment = 1 * SECONDS_PER_HOUR;
+		break;
+  case 2:
+		adjustment = 2 * SECONDS_PER_HOUR;
+		break;
+  case 3:
+		adjustment = 3 * SECONDS_PER_HOUR;
+		break;
+  case 330:
+		adjustment = 3.5 * SECONDS_PER_HOUR;
+		break;
+  case 4:
+		adjustment = 4 * SECONDS_PER_HOUR;
+		break;
+  case 430:
+		adjustment = 4.5 * SECONDS_PER_HOUR;
+		break;
+  case 5:
+		adjustment = 5 * SECONDS_PER_HOUR;
+		break;
+  case 530:
+		adjustment = 5.5 * SECONDS_PER_HOUR;
+		break;
+  case 545:
+		adjustment = 5.75 * SECONDS_PER_HOUR;
+		break;
+  case 6:
+		adjustment = 6 * SECONDS_PER_HOUR;
+		break;
+  case 630:
+		adjustment = 6.5 * SECONDS_PER_HOUR;
+		break;
+  case 7:
+		adjustment = 7 * SECONDS_PER_HOUR;
+		break;
+  case 8:
+		adjustment = 8 * SECONDS_PER_HOUR;
+		break;
+  case 845:
+		adjustment = 8.75 * SECONDS_PER_HOUR;
+		break;
+  case 9:
+		adjustment = 9 * SECONDS_PER_HOUR;
+		break;
+  case 930:
+		adjustment = 9.5 * SECONDS_PER_HOUR;
+		break;
+  case 10:
+		adjustment = 10 * SECONDS_PER_HOUR;
+		break;	
+  case 1030:
+		adjustment = 10.5 * SECONDS_PER_HOUR;
+		break;
+  case 11:
+		adjustment = 11 * SECONDS_PER_HOUR;
+		break;
+  case 1130:
+		adjustment = 11.5 * SECONDS_PER_HOUR;
+		break;
+  case 12:
+		adjustment = 12 * SECONDS_PER_HOUR;
+		break;
+  case 1245:
+		adjustment = 12.75 * SECONDS_PER_HOUR;
+		break;
+  case 13:
+		adjustment = 13 * SECONDS_PER_HOUR;
+		break;
+  case 14:
+		adjustment = 14 * SECONDS_PER_HOUR;
+		break;
+	}
+	
+	_ticks = _ticks - (int)adjustment;
+	
+	return _ticks;
+}
+
+int RTC_clock::switch_years (uint16_t year)
+{
+	if ( ((year %4 == 0) && (year % 100 != 0)) || (year % 400 == 0) ) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int RTC_clock::summertime ()
+{
+	int sundaysommertime, sundaywintertime, today, sundaysommertimehours, sundaywintertimehours, todayhours;
+	
+	_current_date = current_date();
+	_current_time = current_time();
+	
+	_hour   = (((_current_time & 0x00300000) >> 20) * 10 + ((_current_time & 0x000F0000) >> 16));
+	_day    = ((((_current_date >> 28) & 0x3) *   10) + ((_current_date >> 24) & 0xF));
+	_month  = ((((_current_date >> 20) &   1) *   10) + ((_current_date >> 16) & 0xF));
+  _year   = (((_current_date >> 12) & 0xF) * 10) + ((_current_date >> 8) & 0xF);
+	
+  sundaysommertime = 31 - ( 5 + _year * 5 / 4 ) % 7;
+  sundaywintertime = 31 - ( 2 + _year * 5 / 4 ) % 7;
+  today = _day;
+  
+  //Summertimebegin in March
+  for (int i = 1; i < 2; ++i) {
+  	sundaysommertime += daysInMonth[i - 1];
+  }
+  
+  //Wintertimebegin in October
+  for (int i = 1; i < 9; ++i) {
+  	sundaywintertime += daysInMonth[i - 1];
+  }
+  
+  for (int i = 1; i < (_month - 1); ++i) {
+  	today += daysInMonth[i - 1];
+  }
+  
+  sundaysommertimehours = sundaysommertime * 24 + 2;
+  sundaywintertimehours = sundaywintertime * 24 + 3;
+  todayhours = today * 24 + _hour;
+  
+  if (todayhours >= sundaysommertimehours && (todayhours + 1) < sundaywintertimehours) {
+  	return (1 * meztime);
+  } else {
+  	return 0;
+  }
+}
+
+int RTC_clock::timing ()
+{
+	if ( summertime() == 1 ) {
+		meztime = MESZ;
+	} else {
+		meztime = MEZ;
+	}
+}
\ No newline at end of file
diff --git a/hardware/digistump/sam/libraries/RTC/rtc_clock.h b/hardware/digistump/sam/libraries/RTC/rtc_clock.h
new file mode 100644
index 0000000..ea414a7
--- /dev/null
+++ b/hardware/digistump/sam/libraries/RTC/rtc_clock.h
@@ -0,0 +1,83 @@
+#ifndef RTC_clock_h
+#define RTC_clock_h
+
+#include "Arduino.h"
+
+// Includes Atmel CMSIS
+#include 
+
+#define SUPC_KEY   			0xA5u
+#define RESET_VALUE			0x01210720
+
+#define RC							0
+#define	XTAL						1
+
+// Unixtimeseconds from 1. Januar 1970  00:00:00 to 1. Januar 2000   00:00:00 UTC-0
+#define SECONDS_FROM_1970_TO_2000 946684800
+#define SECONDS_PER_HOUR 3600
+
+#define UTC 0
+#define Germany 2000
+
+#define MEZ  1
+#define MESZ -1
+
+class RTC_clock
+{
+	public:
+		RTC_clock (int source);
+		void init ();
+		void set_time (int hour, int minute, int second);
+		void set_time (char* time);
+		int get_hours ();
+		int get_minutes ();
+		int get_seconds ();
+		void set_date (int day, int month, uint16_t year);
+		void set_date (char* date);
+		void set_clock (char* date, char* time);
+		uint8_t set_timestamp(uint32_t timestamp, uint16_t epoch=1970);
+		uint16_t get_years ();
+		int get_months ();
+		int date_already_set ();
+		int get_days ();
+		int get_day_of_week ();
+		int calculate_day_of_week (uint16_t _year, int _month, int _day);
+		int set_hours (int _hour);
+		int set_minutes (int minute);
+		int set_seconds (int second);
+		int set_days (int day);
+		int set_months (int month);
+		int set_years (uint16_t year);
+		void set_alarmtime (int hour, int minute, int second);
+		void set_alarmdate (int month, int day);
+		
+		void attachalarm (void (*)(void));
+		uint32_t unixtime ();
+		uint32_t unixtime (int timezone);
+		void get (int *hour, int *minute, int *second, int *day, int *month, int *year);
+		void get_time (int *hour, int *minute, int *second);
+		void get_date (int *day_of_week, int *day, int *month, int *year);
+		int switch_years (uint16_t year);
+		int summertime ();
+		int timing ();
+		
+	private:
+		int _source;
+		int _hour;
+		int _minute;
+		int _second;
+		int _day;
+		int _month;
+		uint16_t _year;
+		int _day_of_week;
+		uint32_t current_time ();
+		uint32_t current_date ();
+		uint32_t _current_time;
+		uint32_t _current_date;
+		uint32_t change_time (uint32_t _now);
+		uint32_t change_date (uint32_t _now);
+		uint32_t _now;
+		uint32_t _changed;
+};
+
+#endif
\ No newline at end of file
diff --git a/hardware/digistump/sam/libraries/SPI/SPI.cpp b/hardware/digistump/sam/libraries/SPI/SPI.cpp
new file mode 100644
index 0000000..9517e22
--- /dev/null
+++ b/hardware/digistump/sam/libraries/SPI/SPI.cpp
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2010 by Cristian Maglie 
+ * SPI Master library for arduino.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of either the GNU General Public License version 2
+ * or the GNU Lesser General Public License version 2.1, both as
+ * published by the Free Software Foundation.
+ */
+
+#include "SPI.h"
+
+SPIClass::SPIClass(Spi *_spi, uint32_t _id, void(*_initCb)(void)) :
+	spi(_spi), id(_id), initCb(_initCb), initialized(false)
+{
+	// Empty
+}
+
+void SPIClass::begin() {
+	init();
+
+	// NPCS control is left to the user
+
+	// Default speed set to 4Mhz
+	setClockDivider(BOARD_SPI_DEFAULT_SS, 21);
+	setDataMode(BOARD_SPI_DEFAULT_SS, SPI_MODE0);
+	setBitOrder(BOARD_SPI_DEFAULT_SS, MSBFIRST);
+}
+
+void SPIClass::begin(uint8_t _pin) {
+	init();
+
+	uint32_t spiPin = BOARD_PIN_TO_SPI_PIN(_pin);
+	PIO_Configure(
+		g_APinDescription[spiPin].pPort,
+		g_APinDescription[spiPin].ulPinType,
+		g_APinDescription[spiPin].ulPin,
+		g_APinDescription[spiPin].ulPinConfiguration);
+
+	// Default speed set to 4Mhz
+	setClockDivider(_pin, 21);
+	setDataMode(_pin, SPI_MODE0);
+	setBitOrder(_pin, MSBFIRST);
+}
+
+void SPIClass::init() {
+	if (initialized)
+		return;
+	initCb();
+	SPI_Configure(spi, id, SPI_MR_MSTR | SPI_MR_PS | SPI_MR_MODFDIS);
+	SPI_Enable(spi);
+	initialized = true;
+}
+
+void SPIClass::end(uint8_t _pin) {
+	uint32_t spiPin = BOARD_PIN_TO_SPI_PIN(_pin);
+	// Setting the pin as INPUT will disconnect it from SPI peripheral
+	pinMode(spiPin, INPUT);
+}
+
+void SPIClass::end() {
+	SPI_Disable(spi);
+	initialized = false;
+}
+
+void SPIClass::setBitOrder(uint8_t _pin, BitOrder _bitOrder) {
+	uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(_pin);
+	bitOrder[ch] = _bitOrder;
+}
+
+void SPIClass::setDataMode(uint8_t _pin, uint8_t _mode) {
+	uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(_pin);
+	mode[ch] = _mode | SPI_CSR_CSAAT;
+	// SPI_CSR_DLYBCT(1) keeps CS enabled for 32 MCLK after a completed
+	// transfer. Some device needs that for working properly.
+	SPI_ConfigureNPCS(spi, ch, mode[ch] | SPI_CSR_SCBR(divider[ch]) | SPI_CSR_DLYBCT(1));
+}
+
+void SPIClass::setClockDivider(uint8_t _pin, uint8_t _divider) {
+	uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(_pin);
+	divider[ch] = _divider;
+	// SPI_CSR_DLYBCT(1) keeps CS enabled for 32 MCLK after a completed
+	// transfer. Some device needs that for working properly.
+	SPI_ConfigureNPCS(spi, ch, mode[ch] | SPI_CSR_SCBR(divider[ch]) | SPI_CSR_DLYBCT(1));
+}
+
+byte SPIClass::transfer(byte _pin, uint8_t _data, SPITransferMode _mode) {
+	uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(_pin);
+	// Reverse bit order
+	if (bitOrder[ch] == LSBFIRST)
+		_data = __REV(__RBIT(_data));
+	uint32_t d = _data | SPI_PCS(ch);
+	if (_mode == SPI_LAST)
+		d |= SPI_TDR_LASTXFER;
+
+	// SPI_Write(spi, _channel, _data);
+    while ((spi->SPI_SR & SPI_SR_TDRE) == 0)
+    	;
+    spi->SPI_TDR = d;
+
+    // return SPI_Read(spi);
+    while ((spi->SPI_SR & SPI_SR_RDRF) == 0)
+    	;
+    d = spi->SPI_RDR;
+	// Reverse bit order
+	if (bitOrder[ch] == LSBFIRST)
+		d = __REV(__RBIT(d));
+    return d & 0xFF;
+}
+
+void SPIClass::attachInterrupt(void) {
+	// Should be enableInterrupt()
+}
+
+void SPIClass::detachInterrupt(void) {
+	// Should be disableInterrupt()
+}
+
+#if SPI_INTERFACES_COUNT > 0
+static void SPI_0_Init(void) {
+	PIO_Configure(
+			g_APinDescription[PIN_SPI_MOSI].pPort,
+			g_APinDescription[PIN_SPI_MOSI].ulPinType,
+			g_APinDescription[PIN_SPI_MOSI].ulPin,
+			g_APinDescription[PIN_SPI_MOSI].ulPinConfiguration);
+	PIO_Configure(
+			g_APinDescription[PIN_SPI_MISO].pPort,
+			g_APinDescription[PIN_SPI_MISO].ulPinType,
+			g_APinDescription[PIN_SPI_MISO].ulPin,
+			g_APinDescription[PIN_SPI_MISO].ulPinConfiguration);
+	PIO_Configure(
+			g_APinDescription[PIN_SPI_SCK].pPort,
+			g_APinDescription[PIN_SPI_SCK].ulPinType,
+			g_APinDescription[PIN_SPI_SCK].ulPin,
+			g_APinDescription[PIN_SPI_SCK].ulPinConfiguration);
+}
+
+SPIClass SPI(SPI_INTERFACE, SPI_INTERFACE_ID, SPI_0_Init);
+#endif
diff --git a/hardware/digistump/sam/libraries/SPI/SPI.h b/hardware/digistump/sam/libraries/SPI/SPI.h
new file mode 100644
index 0000000..735bd4b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/SPI/SPI.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2010 by Cristian Maglie 
+ * SPI Master library for arduino.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of either the GNU General Public License version 2
+ * or the GNU Lesser General Public License version 2.1, both as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _SPI_H_INCLUDED
+#define _SPI_H_INCLUDED
+
+#include "variant.h"
+#include 
+
+#define SPI_MODE0 0x02
+#define SPI_MODE1 0x00
+#define SPI_MODE2 0x03
+#define SPI_MODE3 0x01
+
+enum SPITransferMode {
+	SPI_CONTINUE,
+	SPI_LAST
+};
+
+class SPIClass {
+  public:
+	SPIClass(Spi *_spi, uint32_t _id, void(*_initCb)(void));
+
+	byte transfer(uint8_t _data, SPITransferMode _mode = SPI_LAST) { return transfer(BOARD_SPI_DEFAULT_SS, _data, _mode); }
+	byte transfer(byte _channel, uint8_t _data, SPITransferMode _mode = SPI_LAST);
+
+	// SPI Configuration methods
+
+	void attachInterrupt(void);
+	void detachInterrupt(void);
+
+	void begin(void);
+	void end(void);
+
+	// Attach/Detach pin to/from SPI controller
+	void begin(uint8_t _pin);
+	void end(uint8_t _pin);
+
+	// These methods sets a parameter on a single pin
+	void setBitOrder(uint8_t _pin, BitOrder);
+	void setDataMode(uint8_t _pin, uint8_t);
+	void setClockDivider(uint8_t _pin, uint8_t);
+
+	// These methods sets the same parameters but on default pin BOARD_SPI_DEFAULT_SS
+	void setBitOrder(BitOrder _order) { setBitOrder(BOARD_SPI_DEFAULT_SS, _order); };
+	void setDataMode(uint8_t _mode) { setDataMode(BOARD_SPI_DEFAULT_SS, _mode); };
+	void setClockDivider(uint8_t _div) { setClockDivider(BOARD_SPI_DEFAULT_SS, _div); };
+
+  private:
+	void init();
+
+	Spi *spi;
+	uint32_t id;
+	BitOrder bitOrder[SPI_CHANNELS_NUM];
+	uint32_t divider[SPI_CHANNELS_NUM];
+	uint32_t mode[SPI_CHANNELS_NUM];
+	void (*initCb)(void);
+	bool initialized;
+};
+
+#if SPI_INTERFACES_COUNT > 0
+extern SPIClass SPI;
+#endif
+
+#endif
diff --git a/hardware/digistump/sam/libraries/SPI/examples/BarometricPressureSensor/BarometricPressureSensor.ino b/hardware/digistump/sam/libraries/SPI/examples/BarometricPressureSensor/BarometricPressureSensor.ino
new file mode 100644
index 0000000..8104fcb
--- /dev/null
+++ b/hardware/digistump/sam/libraries/SPI/examples/BarometricPressureSensor/BarometricPressureSensor.ino
@@ -0,0 +1,143 @@
+/*
+ SCP1000 Barometric Pressure Sensor Display
+
+ Shows the output of a Barometric Pressure Sensor on a
+ Uses the SPI library. For details on the sensor, see:
+ http://www.sparkfun.com/commerce/product_info.php?products_id=8161
+ http://www.vti.fi/en/support/obsolete_products/pressure_sensors/
+
+ This sketch adapted from Nathan Seidle's SCP1000 example for PIC:
+ http://www.sparkfun.com/datasheets/Sensors/SCP1000-Testing.zip
+
+ Circuit:
+ SCP1000 sensor attached to pins 6, 7, 10 - 13:
+ DRDY: pin 6
+ CSB: pin 7
+ MOSI: pin 11
+ MISO: pin 12
+ SCK: pin 13
+
+ created 31 July 2010
+ modified 14 August 2010
+ by Tom Igoe
+ */
+
+// the sensor communicates using SPI, so include the library:
+#include 
+
+//Sensor's memory register addresses:
+const int PRESSURE = 0x1F;      //3 most significant bits of pressure
+const int PRESSURE_LSB = 0x20;  //16 least significant bits of pressure
+const int TEMPERATURE = 0x21;   //16 bit temperature reading
+const byte READ = 0b11111100;     // SCP1000's read command
+const byte WRITE = 0b00000010;   // SCP1000's write command
+
+// pins used for the connection with the sensor
+// the other you need are controlled by the SPI library):
+const int dataReadyPin = 6;
+const int chipSelectPin = 7;
+
+void setup() {
+  Serial.begin(9600);
+
+  // start the SPI library:
+  SPI.begin();
+
+  // initalize the  data ready and chip select pins:
+  pinMode(dataReadyPin, INPUT);
+  pinMode(chipSelectPin, OUTPUT);
+
+  //Configure SCP1000 for low noise configuration:
+  writeRegister(0x02, 0x2D);
+  writeRegister(0x01, 0x03);
+  writeRegister(0x03, 0x02);
+  // give the sensor time to set up:
+  delay(100);
+}
+
+void loop() {
+  //Select High Resolution Mode
+  writeRegister(0x03, 0x0A);
+
+  // don't do anything until the data ready pin is high:
+  if (digitalRead(dataReadyPin) == HIGH) {
+    //Read the temperature data
+    int tempData = readRegister(0x21, 2);
+
+    // convert the temperature to celsius and display it:
+    float realTemp = (float)tempData / 20.0;
+    Serial.print("Temp[C]=");
+    Serial.print(realTemp);
+
+
+    //Read the pressure data highest 3 bits:
+    byte  pressure_data_high = readRegister(0x1F, 1);
+    pressure_data_high &= 0b00000111; //you only needs bits 2 to 0
+
+    //Read the pressure data lower 16 bits:
+    unsigned int pressure_data_low = readRegister(0x20, 2);
+    //combine the two parts into one 19-bit number:
+    long pressure = ((pressure_data_high << 16) | pressure_data_low) / 4;
+
+    // display the temperature:
+    Serial.println("\tPressure [Pa]=" + String(pressure));
+  }
+}
+
+//Read from or write to register from the SCP1000:
+unsigned int readRegister(byte thisRegister, int bytesToRead ) {
+  byte inByte = 0;           // incoming byte from the SPI
+  unsigned int result = 0;   // result to return
+  Serial.print(thisRegister, BIN);
+  Serial.print("\t");
+  // SCP1000 expects the register name in the upper 6 bits
+  // of the byte. So shift the bits left by two bits:
+  thisRegister = thisRegister << 2;
+  // now combine the address and the command into one byte
+  byte dataToSend = thisRegister & READ;
+  Serial.println(thisRegister, BIN);
+  // take the chip select low to select the device:
+  digitalWrite(chipSelectPin, LOW);
+  // send the device the register you want to read:
+  SPI.transfer(dataToSend);
+  // send a value of 0 to read the first byte returned:
+  result = SPI.transfer(0x00);
+  // decrement the number of bytes left to read:
+  bytesToRead--;
+  // if you still have another byte to read:
+  if (bytesToRead > 0) {
+    // shift the first byte left, then get the second byte:
+    result = result << 8;
+    inByte = SPI.transfer(0x00);
+    // combine the byte you just got with the previous one:
+    result = result | inByte;
+    // decrement the number of bytes left to read:
+    bytesToRead--;
+  }
+  // take the chip select high to de-select:
+  digitalWrite(chipSelectPin, HIGH);
+  // return the result:
+  return(result);
+}
+
+
+//Sends a write command to SCP1000
+
+void writeRegister(byte thisRegister, byte thisValue) {
+
+  // SCP1000 expects the register address in the upper 6 bits
+  // of the byte. So shift the bits left by two bits:
+  thisRegister = thisRegister << 2;
+  // now combine the register address and the command into one byte:
+  byte dataToSend = thisRegister | WRITE;
+
+  // take the chip select low to select the device:
+  digitalWrite(chipSelectPin, LOW);
+
+  SPI.transfer(dataToSend); //Send register location
+  SPI.transfer(thisValue);  //Send value to record into register
+
+  // take the chip select high to de-select:
+  digitalWrite(chipSelectPin, HIGH);
+}
+
diff --git a/hardware/digistump/sam/libraries/SPI/examples/DigitalPotControl/DigitalPotControl.ino b/hardware/digistump/sam/libraries/SPI/examples/DigitalPotControl/DigitalPotControl.ino
new file mode 100644
index 0000000..b135a74
--- /dev/null
+++ b/hardware/digistump/sam/libraries/SPI/examples/DigitalPotControl/DigitalPotControl.ino
@@ -0,0 +1,71 @@
+/*
+  Digital Pot Control
+
+  This example controls an Analog Devices AD5206 digital potentiometer.
+  The AD5206 has 6 potentiometer channels. Each channel's pins are labeled
+  A - connect this to voltage
+  W - this is the pot's wiper, which changes when you set it
+  B - connect this to ground.
+
+ The AD5206 is SPI-compatible,and to command it, you send two bytes,
+ one with the channel number (0 - 5) and one with the resistance value for the
+ channel (0 - 255).
+
+ The circuit:
+  * All A pins  of AD5206 connected to +5V
+  * All B pins of AD5206 connected to ground
+  * An LED and a 220-ohm resisor in series connected from each W pin to ground
+  * CS - to digital pin 10  (SS pin)
+  * SDI - to digital pin 11 (MOSI pin)
+  * CLK - to digital pin 13 (SCK pin)
+
+ created 10 Aug 2010
+ by Tom Igoe
+
+ Thanks to Heather Dewey-Hagborg for the original tutorial, 2005
+
+*/
+
+
+// inslude the SPI library:
+#include 
+
+
+// set pin 10 as the slave select for the digital pot:
+const int slaveSelectPin = 10;
+
+void setup() {
+  // set the slaveSelectPin as an output:
+  pinMode (slaveSelectPin, OUTPUT);
+  // initialize SPI:
+  SPI.begin();
+}
+
+void loop() {
+  // go through the six channels of the digital pot:
+  for (int channel = 0; channel < 6; channel++) {
+    // change the resistance on this channel from min to max:
+    for (int level = 0; level < 255; level++) {
+      digitalPotWrite(channel, level);
+      delay(10);
+    }
+    // wait a second at the top:
+    delay(100);
+    // change the resistance on this channel from max to min:
+    for (int level = 0; level < 255; level++) {
+      digitalPotWrite(channel, 255 - level);
+      delay(10);
+    }
+  }
+
+}
+
+void digitalPotWrite(int address, int value) {
+  // take the SS pin low to select the chip:
+  digitalWrite(slaveSelectPin, LOW);
+  //  send in the address and value via SPI:
+  SPI.transfer(address);
+  SPI.transfer(value);
+  // take the SS pin high to de-select the chip:
+  digitalWrite(slaveSelectPin, HIGH);
+}
diff --git a/hardware/digistump/sam/libraries/SPI/keywords.txt b/hardware/digistump/sam/libraries/SPI/keywords.txt
new file mode 100644
index 0000000..47738f9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/SPI/keywords.txt
@@ -0,0 +1,31 @@
+#######################################
+# Syntax Coloring Map SPI
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+SPI	KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+begin			KEYWORD2
+end				KEYWORD2
+transfer		KEYWORD2
+#setBitOrder	KEYWORD2
+setDataMode		KEYWORD2
+setClockDivider	KEYWORD2
+
+
+#######################################
+# Constants (LITERAL1)
+#######################################
+SPI_MODE0		LITERAL1
+SPI_MODE1		LITERAL1
+SPI_MODE2		LITERAL1
+SPI_MODE3		LITERAL1
+
+SPI_CONTINUE	LITERAL1
+SPI_LAST		LITERAL1
diff --git a/hardware/digistump/sam/libraries/UTFT/DefaultFonts.c b/hardware/digistump/sam/libraries/UTFT/DefaultFonts.c
new file mode 100644
index 0000000..06cc938
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/DefaultFonts.c
@@ -0,0 +1,246 @@
+// DO NOT ADD YOUR OWN FONTS TO THIS FILE
+// If you want to use your own fonts you should just drop the font .c file into your sketch folder.
+// ------------------------------------------------------------------------------------------------
+
+#if defined(__AVR__)
+	#include 
+	#define fontdatatype uint8_t
+#elif defined(__PIC32MX__)
+	#define PROGMEM
+	#define fontdatatype const unsigned char
+#elif defined(__arm__)
+	#define PROGMEM
+	#define fontdatatype const unsigned char
+#endif
+
+// SmallFont.c 
+// Font Size	: 8x12
+// Memory usage	: 1144 bytes
+// # characters	: 95
+
+fontdatatype SmallFont[1144] PROGMEM={         
+0x08,0x0C,0x20,0x5F,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // 
+0x00,0x00,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x20,0x00,0x00, // !
+0x00,0x28,0x50,0x50,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // "
+0x00,0x00,0x28,0x28,0xFC,0x28,0x50,0xFC,0x50,0x50,0x00,0x00, // #
+0x00,0x20,0x78,0xA8,0xA0,0x60,0x30,0x28,0xA8,0xF0,0x20,0x00, // $
+0x00,0x00,0x48,0xA8,0xB0,0x50,0x28,0x34,0x54,0x48,0x00,0x00, // %
+0x00,0x00,0x20,0x50,0x50,0x78,0xA8,0xA8,0x90,0x6C,0x00,0x00, // &
+0x00,0x40,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // '
+0x00,0x04,0x08,0x10,0x10,0x10,0x10,0x10,0x10,0x08,0x04,0x00, // (
+0x00,0x40,0x20,0x10,0x10,0x10,0x10,0x10,0x10,0x20,0x40,0x00, // )
+0x00,0x00,0x00,0x20,0xA8,0x70,0x70,0xA8,0x20,0x00,0x00,0x00, // *
+0x00,0x00,0x20,0x20,0x20,0xF8,0x20,0x20,0x20,0x00,0x00,0x00, // +
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40,0x80, // ,
+0x00,0x00,0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00, // -
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00, // .
+0x00,0x08,0x10,0x10,0x10,0x20,0x20,0x40,0x40,0x40,0x80,0x00, // /
+0x00,0x00,0x70,0x88,0x88,0x88,0x88,0x88,0x88,0x70,0x00,0x00, // 0
+0x00,0x00,0x20,0x60,0x20,0x20,0x20,0x20,0x20,0x70,0x00,0x00, // 1
+0x00,0x00,0x70,0x88,0x88,0x10,0x20,0x40,0x80,0xF8,0x00,0x00, // 2
+0x00,0x00,0x70,0x88,0x08,0x30,0x08,0x08,0x88,0x70,0x00,0x00, // 3
+0x00,0x00,0x10,0x30,0x50,0x50,0x90,0x78,0x10,0x18,0x00,0x00, // 4
+0x00,0x00,0xF8,0x80,0x80,0xF0,0x08,0x08,0x88,0x70,0x00,0x00, // 5
+0x00,0x00,0x70,0x90,0x80,0xF0,0x88,0x88,0x88,0x70,0x00,0x00, // 6
+0x00,0x00,0xF8,0x90,0x10,0x20,0x20,0x20,0x20,0x20,0x00,0x00, // 7
+0x00,0x00,0x70,0x88,0x88,0x70,0x88,0x88,0x88,0x70,0x00,0x00, // 8
+0x00,0x00,0x70,0x88,0x88,0x88,0x78,0x08,0x48,0x70,0x00,0x00, // 9
+0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x20,0x00,0x00, // :
+0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x20,0x00, // ;
+0x00,0x04,0x08,0x10,0x20,0x40,0x20,0x10,0x08,0x04,0x00,0x00, // <
+0x00,0x00,0x00,0x00,0xF8,0x00,0x00,0xF8,0x00,0x00,0x00,0x00, // =
+0x00,0x40,0x20,0x10,0x08,0x04,0x08,0x10,0x20,0x40,0x00,0x00, // >
+0x00,0x00,0x70,0x88,0x88,0x10,0x20,0x20,0x00,0x20,0x00,0x00, // ?
+0x00,0x00,0x70,0x88,0x98,0xA8,0xA8,0xB8,0x80,0x78,0x00,0x00, // @
+0x00,0x00,0x20,0x20,0x30,0x50,0x50,0x78,0x48,0xCC,0x00,0x00, // A
+0x00,0x00,0xF0,0x48,0x48,0x70,0x48,0x48,0x48,0xF0,0x00,0x00, // B
+0x00,0x00,0x78,0x88,0x80,0x80,0x80,0x80,0x88,0x70,0x00,0x00, // C
+0x00,0x00,0xF0,0x48,0x48,0x48,0x48,0x48,0x48,0xF0,0x00,0x00, // D
+0x00,0x00,0xF8,0x48,0x50,0x70,0x50,0x40,0x48,0xF8,0x00,0x00, // E
+0x00,0x00,0xF8,0x48,0x50,0x70,0x50,0x40,0x40,0xE0,0x00,0x00, // F
+0x00,0x00,0x38,0x48,0x80,0x80,0x9C,0x88,0x48,0x30,0x00,0x00, // G
+0x00,0x00,0xCC,0x48,0x48,0x78,0x48,0x48,0x48,0xCC,0x00,0x00, // H
+0x00,0x00,0xF8,0x20,0x20,0x20,0x20,0x20,0x20,0xF8,0x00,0x00, // I
+0x00,0x00,0x7C,0x10,0x10,0x10,0x10,0x10,0x10,0x90,0xE0,0x00, // J
+0x00,0x00,0xEC,0x48,0x50,0x60,0x50,0x50,0x48,0xEC,0x00,0x00, // K
+0x00,0x00,0xE0,0x40,0x40,0x40,0x40,0x40,0x44,0xFC,0x00,0x00, // L
+0x00,0x00,0xD8,0xD8,0xD8,0xD8,0xA8,0xA8,0xA8,0xA8,0x00,0x00, // M
+0x00,0x00,0xDC,0x48,0x68,0x68,0x58,0x58,0x48,0xE8,0x00,0x00, // N
+0x00,0x00,0x70,0x88,0x88,0x88,0x88,0x88,0x88,0x70,0x00,0x00, // O
+0x00,0x00,0xF0,0x48,0x48,0x70,0x40,0x40,0x40,0xE0,0x00,0x00, // P
+0x00,0x00,0x70,0x88,0x88,0x88,0x88,0xE8,0x98,0x70,0x18,0x00, // Q
+0x00,0x00,0xF0,0x48,0x48,0x70,0x50,0x48,0x48,0xEC,0x00,0x00, // R
+0x00,0x00,0x78,0x88,0x80,0x60,0x10,0x08,0x88,0xF0,0x00,0x00, // S
+0x00,0x00,0xF8,0xA8,0x20,0x20,0x20,0x20,0x20,0x70,0x00,0x00, // T
+0x00,0x00,0xCC,0x48,0x48,0x48,0x48,0x48,0x48,0x30,0x00,0x00, // U
+0x00,0x00,0xCC,0x48,0x48,0x50,0x50,0x30,0x20,0x20,0x00,0x00, // V
+0x00,0x00,0xA8,0xA8,0xA8,0x70,0x50,0x50,0x50,0x50,0x00,0x00, // W
+0x00,0x00,0xD8,0x50,0x50,0x20,0x20,0x50,0x50,0xD8,0x00,0x00, // X
+0x00,0x00,0xD8,0x50,0x50,0x20,0x20,0x20,0x20,0x70,0x00,0x00, // Y
+0x00,0x00,0xF8,0x90,0x10,0x20,0x20,0x40,0x48,0xF8,0x00,0x00, // Z
+0x00,0x38,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x38,0x00, // [
+0x00,0x40,0x40,0x40,0x20,0x20,0x10,0x10,0x10,0x08,0x00,0x00, // 
+0x00,0x70,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x70,0x00, // ]
+0x00,0x20,0x50,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // ^
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFC, // _
+0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // '
+0x00,0x00,0x00,0x00,0x00,0x30,0x48,0x38,0x48,0x3C,0x00,0x00, // a
+0x00,0x00,0xC0,0x40,0x40,0x70,0x48,0x48,0x48,0x70,0x00,0x00, // b
+0x00,0x00,0x00,0x00,0x00,0x38,0x48,0x40,0x40,0x38,0x00,0x00, // c
+0x00,0x00,0x18,0x08,0x08,0x38,0x48,0x48,0x48,0x3C,0x00,0x00, // d
+0x00,0x00,0x00,0x00,0x00,0x30,0x48,0x78,0x40,0x38,0x00,0x00, // e
+0x00,0x00,0x1C,0x20,0x20,0x78,0x20,0x20,0x20,0x78,0x00,0x00, // f
+0x00,0x00,0x00,0x00,0x00,0x3C,0x48,0x30,0x40,0x78,0x44,0x38, // g
+0x00,0x00,0xC0,0x40,0x40,0x70,0x48,0x48,0x48,0xEC,0x00,0x00, // h
+0x00,0x00,0x20,0x00,0x00,0x60,0x20,0x20,0x20,0x70,0x00,0x00, // i
+0x00,0x00,0x10,0x00,0x00,0x30,0x10,0x10,0x10,0x10,0x10,0xE0, // j
+0x00,0x00,0xC0,0x40,0x40,0x5C,0x50,0x70,0x48,0xEC,0x00,0x00, // k
+0x00,0x00,0xE0,0x20,0x20,0x20,0x20,0x20,0x20,0xF8,0x00,0x00, // l
+0x00,0x00,0x00,0x00,0x00,0xF0,0xA8,0xA8,0xA8,0xA8,0x00,0x00, // m
+0x00,0x00,0x00,0x00,0x00,0xF0,0x48,0x48,0x48,0xEC,0x00,0x00, // n
+0x00,0x00,0x00,0x00,0x00,0x30,0x48,0x48,0x48,0x30,0x00,0x00, // o
+0x00,0x00,0x00,0x00,0x00,0xF0,0x48,0x48,0x48,0x70,0x40,0xE0, // p
+0x00,0x00,0x00,0x00,0x00,0x38,0x48,0x48,0x48,0x38,0x08,0x1C, // q
+0x00,0x00,0x00,0x00,0x00,0xD8,0x60,0x40,0x40,0xE0,0x00,0x00, // r
+0x00,0x00,0x00,0x00,0x00,0x78,0x40,0x30,0x08,0x78,0x00,0x00, // s
+0x00,0x00,0x00,0x20,0x20,0x70,0x20,0x20,0x20,0x18,0x00,0x00, // t
+0x00,0x00,0x00,0x00,0x00,0xD8,0x48,0x48,0x48,0x3C,0x00,0x00, // u
+0x00,0x00,0x00,0x00,0x00,0xEC,0x48,0x50,0x30,0x20,0x00,0x00, // v
+0x00,0x00,0x00,0x00,0x00,0xA8,0xA8,0x70,0x50,0x50,0x00,0x00, // w
+0x00,0x00,0x00,0x00,0x00,0xD8,0x50,0x20,0x50,0xD8,0x00,0x00, // x
+0x00,0x00,0x00,0x00,0x00,0xEC,0x48,0x50,0x30,0x20,0x20,0xC0, // y
+0x00,0x00,0x00,0x00,0x00,0x78,0x10,0x20,0x20,0x78,0x00,0x00, // z
+0x00,0x18,0x10,0x10,0x10,0x20,0x10,0x10,0x10,0x10,0x18,0x00, // {
+0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, // |
+0x00,0x60,0x20,0x20,0x20,0x10,0x20,0x20,0x20,0x20,0x60,0x00, // }
+0x40,0xA4,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // ~
+};  
+
+// BigFont.c (C)2010 by Henning Karlsen
+// Font Size	: 16x16
+// Memory usage	: 3044 bytes
+// # characters	: 95
+
+fontdatatype BigFont[3044] PROGMEM={
+0x10,0x10,0x20,0x5F,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, //  
+0x00,0x00,0x00,0x00,0x07,0x00,0x0F,0x80,0x0F,0x80,0x0F,0x80,0x0F,0x80,0x0F,0x80,0x07,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x00,0x00, // !
+0x00,0x00,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x06,0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // "
+0x00,0x00,0x0C,0x30,0x0C,0x30,0x0C,0x30,0x7F,0xFE,0x7F,0xFE,0x0C,0x30,0x0C,0x30,0x0C,0x30,0x0C,0x30,0x7F,0xFE,0x7F,0xFE,0x0C,0x30,0x0C,0x30,0x0C,0x30,0x00,0x00, // #
+0x00,0x00,0x02,0x40,0x02,0x40,0x0F,0xF8,0x1F,0xF8,0x1A,0x40,0x1A,0x40,0x1F,0xF0,0x0F,0xF8,0x02,0x58,0x02,0x58,0x1F,0xF8,0x1F,0xF0,0x02,0x40,0x02,0x40,0x00,0x00, // $
+0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x10,0x0E,0x30,0x0E,0x70,0x00,0xE0,0x01,0xC0,0x03,0x80,0x07,0x00,0x0E,0x70,0x0C,0x70,0x08,0x70,0x00,0x00,0x00,0x00,0x00,0x00, // %
+0x00,0x00,0x00,0x00,0x0F,0x00,0x19,0x80,0x19,0x80,0x19,0x80,0x0F,0x00,0x0F,0x08,0x0F,0x98,0x19,0xF8,0x18,0xF0,0x18,0xE0,0x19,0xF0,0x0F,0x98,0x00,0x00,0x00,0x00, // &
+0x00,0x00,0x00,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // '
+0x00,0x00,0x00,0x00,0x00,0xF0,0x01,0xC0,0x03,0x80,0x07,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x07,0x00,0x03,0x80,0x01,0xC0,0x00,0xF0,0x00,0x00,0x00,0x00, // (
+0x00,0x00,0x00,0x00,0x0F,0x00,0x03,0x80,0x01,0xC0,0x00,0xE0,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0xE0,0x01,0xC0,0x03,0x80,0x0F,0x00,0x00,0x00,0x00,0x00, // )
+0x00,0x00,0x00,0x00,0x01,0x80,0x11,0x88,0x09,0x90,0x07,0xE0,0x07,0xE0,0x3F,0xFC,0x3F,0xFC,0x07,0xE0,0x07,0xE0,0x09,0x90,0x11,0x88,0x01,0x80,0x00,0x00,0x00,0x00, // *
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x80,0x01,0x80,0x01,0x80,0x0F,0xF0,0x0F,0xF0,0x01,0x80,0x01,0x80,0x01,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // +
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x0E,0x00,0x00,0x00, // ,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xF8,0x1F,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // -
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x00,0x00,0x00,0x00, // ,
+0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x06,0x00,0x0E,0x00,0x1C,0x00,0x38,0x00,0x70,0x00,0xE0,0x01,0xC0,0x03,0x80,0x07,0x00,0x0E,0x00,0x1C,0x00,0x00,0x00,0x00,0x00, // /
+
+0x00,0x00,0x00,0x00,0x0F,0xF0,0x1C,0x38,0x1C,0x78,0x1C,0xF8,0x1C,0xF8,0x1D,0xB8,0x1D,0xB8,0x1F,0x38,0x1F,0x38,0x1E,0x38,0x1C,0x38,0x0F,0xF0,0x00,0x00,0x00,0x00, // 0
+0x00,0x00,0x00,0x00,0x01,0x80,0x01,0x80,0x03,0x80,0x1F,0x80,0x1F,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x1F,0xF0,0x00,0x00,0x00,0x00, // 1
+0x00,0x00,0x00,0x00,0x0F,0xE0,0x1C,0x70,0x1C,0x38,0x00,0x38,0x00,0x70,0x00,0xE0,0x01,0xC0,0x03,0x80,0x07,0x00,0x0E,0x38,0x1C,0x38,0x1F,0xF8,0x00,0x00,0x00,0x00, // 2
+0x00,0x00,0x00,0x00,0x0F,0xE0,0x1C,0x70,0x1C,0x38,0x00,0x38,0x00,0x70,0x03,0xC0,0x03,0xC0,0x00,0x70,0x00,0x38,0x1C,0x38,0x1C,0x70,0x0F,0xE0,0x00,0x00,0x00,0x00, // 3
+0x00,0x00,0x00,0x00,0x00,0xE0,0x01,0xE0,0x03,0xE0,0x06,0xE0,0x0C,0xE0,0x18,0xE0,0x1F,0xF8,0x1F,0xF8,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x03,0xF8,0x00,0x00,0x00,0x00, // 4
+0x00,0x00,0x00,0x00,0x1F,0xF8,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1F,0xE0,0x1F,0xF0,0x00,0x78,0x00,0x38,0x1C,0x38,0x1C,0x70,0x0F,0xE0,0x00,0x00,0x00,0x00, // 5
+0x00,0x00,0x00,0x00,0x03,0xE0,0x07,0x00,0x0E,0x00,0x1C,0x00,0x1C,0x00,0x1F,0xF0,0x1F,0xF8,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x0F,0xF0,0x00,0x00,0x00,0x00, // 6
+0x00,0x00,0x00,0x00,0x1F,0xFC,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x00,0x1C,0x00,0x38,0x00,0x70,0x00,0xE0,0x01,0xC0,0x03,0x80,0x03,0x80,0x03,0x80,0x00,0x00,0x00,0x00, // 7
+0x00,0x00,0x00,0x00,0x0F,0xF0,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1F,0x38,0x07,0xE0,0x07,0xE0,0x1C,0xF8,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x0F,0xF0,0x00,0x00,0x00,0x00, // 8
+0x00,0x00,0x00,0x00,0x0F,0xF0,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1F,0xF8,0x0F,0xF8,0x00,0x38,0x00,0x38,0x00,0x70,0x00,0xE0,0x07,0xC0,0x00,0x00,0x00,0x00, // 9
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,0x03,0x80,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // :
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,0x03,0x80,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,0x03,0x80,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // ;
+0x00,0x00,0x00,0x70,0x00,0xE0,0x01,0xC0,0x03,0x80,0x07,0x00,0x0E,0x00,0x1C,0x00,0x1C,0x00,0x0E,0x00,0x07,0x00,0x03,0x80,0x01,0xC0,0x00,0xE0,0x00,0x70,0x00,0x00, // <
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFC,0x3F,0xFC,0x00,0x00,0x00,0x00,0x3F,0xFC,0x3F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // =
+0x00,0x00,0x1C,0x00,0x0E,0x00,0x07,0x00,0x03,0x80,0x01,0xC0,0x00,0xE0,0x00,0x70,0x00,0x70,0x00,0xE0,0x01,0xC0,0x03,0x80,0x07,0x00,0x0E,0x00,0x1C,0x00,0x00,0x00, // >
+0x00,0x00,0x03,0xC0,0x0F,0xF0,0x1E,0x78,0x18,0x38,0x00,0x38,0x00,0x70,0x00,0xE0,0x01,0xC0,0x01,0xC0,0x00,0x00,0x00,0x00,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x00,0x00, // ?
+
+0x00,0x00,0x0F,0xF8,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0xFC,0x1C,0xFC,0x1C,0xFC,0x1C,0xFC,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1F,0xF0,0x07,0xF8,0x00,0x00, // @
+0x00,0x00,0x00,0x00,0x03,0xC0,0x07,0xE0,0x0E,0x70,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1F,0xF8,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x00,0x00,0x00,0x00, // A
+0x00,0x00,0x00,0x00,0x1F,0xF0,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0F,0xF0,0x0F,0xF0,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x1F,0xF0,0x00,0x00,0x00,0x00, // B
+0x00,0x00,0x00,0x00,0x07,0xF0,0x0E,0x38,0x1C,0x38,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x38,0x0E,0x38,0x07,0xF0,0x00,0x00,0x00,0x00, // C
+0x00,0x00,0x00,0x00,0x1F,0xE0,0x0E,0x70,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x70,0x1F,0xE0,0x00,0x00,0x00,0x00, // D
+0x00,0x00,0x00,0x00,0x1F,0xF8,0x0E,0x18,0x0E,0x08,0x0E,0x00,0x0E,0x30,0x0F,0xF0,0x0F,0xF0,0x0E,0x30,0x0E,0x00,0x0E,0x08,0x0E,0x18,0x1F,0xF8,0x00,0x00,0x00,0x00, // E
+0x00,0x00,0x00,0x00,0x1F,0xF8,0x0E,0x18,0x0E,0x08,0x0E,0x00,0x0E,0x30,0x0F,0xF0,0x0F,0xF0,0x0E,0x30,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x1F,0x00,0x00,0x00,0x00,0x00, // F
+0x00,0x00,0x00,0x00,0x07,0xF0,0x0E,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0xF8,0x1C,0x38,0x1C,0x38,0x0E,0x38,0x07,0xF8,0x00,0x00,0x00,0x00, // G
+0x00,0x00,0x00,0x00,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1F,0xF0,0x1F,0xF0,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x00,0x00,0x00,0x00, // H
+0x00,0x00,0x00,0x00,0x0F,0xE0,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x0F,0xE0,0x00,0x00,0x00,0x00, // I
+0x00,0x00,0x00,0x00,0x01,0xFC,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x38,0x70,0x38,0x70,0x38,0x70,0x38,0x70,0x0F,0xE0,0x00,0x00,0x00,0x00, // J
+0x00,0x00,0x00,0x00,0x1E,0x38,0x0E,0x38,0x0E,0x70,0x0E,0xE0,0x0F,0xC0,0x0F,0x80,0x0F,0x80,0x0F,0xC0,0x0E,0xE0,0x0E,0x70,0x0E,0x38,0x1E,0x38,0x00,0x00,0x00,0x00, // K
+0x00,0x00,0x00,0x00,0x1F,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x08,0x0E,0x18,0x0E,0x38,0x1F,0xF8,0x00,0x00,0x00,0x00, // L
+0x00,0x00,0x00,0x00,0x1C,0x1C,0x1E,0x3C,0x1F,0x7C,0x1F,0xFC,0x1F,0xFC,0x1D,0xDC,0x1C,0x9C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x00,0x00,0x00,0x00, // M
+0x00,0x00,0x00,0x00,0x1C,0x1C,0x1C,0x1C,0x1E,0x1C,0x1F,0x1C,0x1F,0x9C,0x1D,0xDC,0x1C,0xFC,0x1C,0x7C,0x1C,0x3C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x00,0x00,0x00,0x00, // N
+0x00,0x00,0x00,0x00,0x03,0xE0,0x07,0xF0,0x0E,0x38,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x0E,0x38,0x07,0xF0,0x03,0xE0,0x00,0x00,0x00,0x00, // O
+
+0x00,0x00,0x00,0x00,0x1F,0xF0,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0F,0xF0,0x0F,0xF0,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x1F,0x00,0x00,0x00,0x00,0x00, // P
+0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0x78,0x0E,0x38,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x7C,0x1C,0xFC,0x0F,0xF8,0x0F,0xF8,0x00,0x38,0x00,0xFC,0x00,0x00, // Q
+0x00,0x00,0x00,0x00,0x1F,0xF0,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0F,0xF0,0x0F,0xF0,0x0E,0x70,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x1E,0x38,0x00,0x00,0x00,0x00, // R
+0x00,0x00,0x00,0x00,0x0F,0xF0,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x00,0x0F,0xE0,0x07,0xF0,0x00,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x0F,0xF0,0x00,0x00,0x00,0x00, // S
+0x00,0x00,0x00,0x00,0x1F,0xFC,0x19,0xCC,0x11,0xC4,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x07,0xF0,0x00,0x00,0x00,0x00, // T
+0x00,0x00,0x00,0x00,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x0F,0xE0,0x00,0x00,0x00,0x00, // U
+0x00,0x00,0x00,0x00,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x0E,0xE0,0x07,0xC0,0x03,0x80,0x00,0x00,0x00,0x00, // V
+0x00,0x00,0x00,0x00,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x9C,0x1C,0x9C,0x1C,0x9C,0x0F,0xF8,0x0F,0xF8,0x07,0x70,0x07,0x70,0x00,0x00,0x00,0x00, // W
+0x00,0x00,0x00,0x00,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x0E,0xE0,0x07,0xC0,0x03,0x80,0x03,0x80,0x07,0xC0,0x0E,0xE0,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x00,0x00,0x00,0x00, // X
+0x00,0x00,0x00,0x00,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x0E,0xE0,0x07,0xC0,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x0F,0xE0,0x00,0x00,0x00,0x00, // Y
+0x00,0x00,0x00,0x00,0x1F,0xF8,0x1C,0x38,0x18,0x38,0x10,0x70,0x00,0xE0,0x01,0xC0,0x03,0x80,0x07,0x00,0x0E,0x08,0x1C,0x18,0x1C,0x38,0x1F,0xF8,0x00,0x00,0x00,0x00, // Z
+0x00,0x00,0x00,0x00,0x07,0xF0,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0xF0,0x00,0x00,0x00,0x00, // [
+0x00,0x00,0x00,0x00,0x10,0x00,0x18,0x00,0x1C,0x00,0x0E,0x00,0x07,0x00,0x03,0x80,0x01,0xC0,0x00,0xE0,0x00,0x70,0x00,0x38,0x00,0x1C,0x00,0x07,0x00,0x00,0x00,0x00, // 
+0x00,0x00,0x00,0x00,0x07,0xF0,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x07,0xF0,0x00,0x00,0x00,0x00, // ]
+0x00,0x00,0x01,0x80,0x03,0xC0,0x07,0xE0,0x0E,0x70,0x1C,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // ^
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x7F,0xFF, // _
+
+0x00,0x00,0x00,0x00,0x1C,0x00,0x1C,0x00,0x07,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // '
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xE0,0x00,0x70,0x00,0x70,0x0F,0xF0,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x0F,0xD8,0x00,0x00,0x00,0x00, // a
+0x00,0x00,0x00,0x00,0x1E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0F,0xF0,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x1B,0xF0,0x00,0x00,0x00,0x00, // b
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xE0,0x1C,0x70,0x1C,0x70,0x1C,0x00,0x1C,0x00,0x1C,0x70,0x1C,0x70,0x0F,0xE0,0x00,0x00,0x00,0x00, // c
+0x00,0x00,0x00,0x00,0x00,0xF8,0x00,0x70,0x00,0x70,0x00,0x70,0x0F,0xF0,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x0F,0xD8,0x00,0x00,0x00,0x00, // d
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xE0,0x1C,0x70,0x1C,0x70,0x1F,0xF0,0x1C,0x00,0x1C,0x70,0x1C,0x70,0x0F,0xE0,0x00,0x00,0x00,0x00, // e
+0x00,0x00,0x00,0x00,0x03,0xE0,0x07,0x70,0x07,0x70,0x07,0x00,0x07,0x00,0x1F,0xE0,0x1F,0xE0,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x1F,0xC0,0x00,0x00,0x00,0x00, // f
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xD8,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x0F,0xF0,0x07,0xF0,0x00,0x70,0x1C,0x70,0x0F,0xE0, // g
+0x00,0x00,0x00,0x00,0x1E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0xF0,0x0F,0x38,0x0F,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x1E,0x38,0x00,0x00,0x00,0x00, // h
+0x00,0x00,0x00,0x00,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x00,0x00,0x0F,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x0F,0xF8,0x00,0x00,0x00,0x00, // i
+0x00,0x00,0x00,0x00,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x00,0x03,0xF0,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0x70,0x1C,0x70,0x0C,0xF0,0x07,0xE0, // j
+0x00,0x00,0x00,0x00,0x1E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x38,0x0E,0x70,0x0E,0xE0,0x0F,0xC0,0x0E,0xE0,0x0E,0x70,0x0E,0x38,0x1E,0x38,0x00,0x00,0x00,0x00, // k
+0x00,0x00,0x00,0x00,0x0F,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x0F,0xF8,0x00,0x00,0x00,0x00, // l
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xF8,0x1C,0x9C,0x1C,0x9C,0x1C,0x9C,0x1C,0x9C,0x1C,0x9C,0x1C,0x9C,0x1C,0x9C,0x00,0x00,0x00,0x00, // m
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xE0,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x00,0x00,0x00,0x00, // n
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xE0,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x0F,0xE0,0x00,0x00,0x00,0x00, // o
+
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1B,0xF0,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0F,0xF0,0x0E,0x00,0x0E,0x00,0x1F,0x00, // p
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xB0,0x38,0xE0,0x38,0xE0,0x38,0xE0,0x38,0xE0,0x38,0xE0,0x1F,0xE0,0x00,0xE0,0x00,0xE0,0x01,0xF0, // q
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1E,0xF0,0x0F,0xF8,0x0F,0x38,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x1F,0x00,0x00,0x00,0x00,0x00, // r
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xE0,0x1C,0x30,0x1C,0x30,0x0F,0x80,0x03,0xE0,0x18,0x70,0x18,0x70,0x0F,0xE0,0x00,0x00,0x00,0x00, // s
+0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x03,0x00,0x07,0x00,0x1F,0xF0,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x70,0x07,0x70,0x03,0xE0,0x00,0x00,0x00,0x00, // t
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x0F,0xD8,0x00,0x00,0x00,0x00, // u
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x1C,0x70,0x0E,0xE0,0x07,0xC0,0x03,0x80,0x00,0x00,0x00,0x00, // v
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x9C,0x1C,0x9C,0x0F,0xF8,0x07,0x70,0x07,0x70,0x00,0x00,0x00,0x00, // w
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0xE0,0x1C,0xE0,0x0F,0xC0,0x07,0x80,0x07,0x80,0x0F,0xC0,0x1C,0xE0,0x1C,0xE0,0x00,0x00,0x00,0x00, // x
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x07,0xF0,0x03,0xE0,0x00,0xE0,0x01,0xC0,0x1F,0x80, // y
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xE0,0x18,0xE0,0x11,0xC0,0x03,0x80,0x07,0x00,0x0E,0x20,0x1C,0x60,0x1F,0xE0,0x00,0x00,0x00,0x00, // z
+0x00,0x00,0x00,0x00,0x01,0xF8,0x03,0x80,0x03,0x80,0x03,0x80,0x07,0x00,0x1C,0x00,0x1C,0x00,0x07,0x00,0x03,0x80,0x03,0x80,0x03,0x80,0x01,0xF8,0x00,0x00,0x00,0x00, // {
+0x00,0x00,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x00,0x00, // |
+0x00,0x00,0x00,0x00,0x1F,0x80,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x00,0xE0,0x00,0x38,0x00,0x38,0x00,0xE0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x1F,0x80,0x00,0x00,0x00,0x00, // }
+0x00,0x00,0x00,0x00,0x1F,0x1C,0x3B,0x9C,0x39,0xDC,0x38,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00  // ~
+}; 
+
+// SevenSegNumFont.c
+// Font Size	: 32x50
+// Memory usage	: 2004 bytes
+// # characters	: 10
+
+fontdatatype SevenSegNumFont[2004] PROGMEM={
+0x20,0x32,0x30,0x0A,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x60,0x0C,0xFF,0xFE,0xF0,0x1E,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3E,0x00,0x00,0x78,0x38,0x00,0x00,0x18,0x20,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x38,0x00,0x00,0x18,0x3E,0x00,0x00,0x78,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x1E,0x00,0x00,0xF0,0x0C,0xFF,0xFE,0x60,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  // 0
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xF0,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x00,0x78,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x78,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  // 1
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x60,0x00,0xFF,0xFE,0xF0,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x00,0x78,0x01,0xFF,0xFE,0x18,0x03,0xFF,0xFF,0x88,0x0F,0xFF,0xFF,0xE0,0x27,0xFF,0xFF,0xC0,0x39,0xFF,0xFF,0x00,0x3E,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x0C,0xFF,0xFE,0x00,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  // 2
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x60,0x00,0xFF,0xFE,0xF0,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x00,0x78,0x01,0xFF,0xFE,0x18,0x03,0xFF,0xFF,0x88,0x0F,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xC0,0x01,0xFF,0xFF,0x18,0x00,0x00,0x00,0x78,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x00,0xF0,0x00,0xFF,0xFE,0x60,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  // 3
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x0C,0x00,0x00,0xF0,0x1E,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3E,0x00,0x00,0x78,0x39,0xFF,0xFE,0x18,0x23,0xFF,0xFF,0x88,0x0F,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xC0,0x01,0xFF,0xFF,0x18,0x00,0x00,0x00,0x78,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  // 4
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x00,0x0C,0xFF,0xFE,0x00,0x1E,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x39,0xFF,0xFE,0x00,0x23,0xFF,0xFF,0x80,0x0F,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xC0,0x01,0xFF,0xFF,0x18,0x00,0x00,0x00,0x78,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x00,0xF0,0x00,0xFF,0xFE,0x60,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  // 5
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x00,0x0C,0xFF,0xFE,0x00,0x1E,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x3E,0x00,0x00,0x00,0x39,0xFF,0xFE,0x00,0x23,0xFF,0xFF,0x80,0x0F,0xFF,0xFF,0xE0,0x27,0xFF,0xFF,0xC0,0x39,0xFF,0xFF,0x18,0x3E,0x00,0x00,0x78,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x1E,0x00,0x00,0xF0,0x0C,0xFF,0xFE,0x60,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  // 6
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x60,0x00,0xFF,0xFE,0xF0,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x00,0x78,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x78,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  // 7
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x60,0x0C,0xFF,0xFE,0xF0,0x1E,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3E,0x00,0x00,0x78,0x39,0xFF,0xFE,0x18,0x23,0xFF,0xFF,0x88,0x0F,0xFF,0xFF,0xE0,0x27,0xFF,0xFF,0xC0,0x39,0xFF,0xFF,0x18,0x3E,0x00,0x00,0x78,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x1E,0x00,0x00,0xF0,0x0C,0xFF,0xFE,0x60,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  // 8
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFE,0x00,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x60,0x0C,0xFF,0xFE,0xF0,0x1E,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3F,0x00,0x01,0xF8,0x3E,0x00,0x00,0x78,0x39,0xFF,0xFE,0x18,0x23,0xFF,0xFF,0x88,0x0F,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xC0,0x01,0xFF,0xFF,0x18,0x00,0x00,0x00,0x78,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x01,0xF8,0x00,0x00,0x00,0xF0,0x00,0xFF,0xFE,0x60,0x01,0xFF,0xFF,0x00,0x03,0xFF,0xFF,0x80,0x01,0xFF,0xFF,0x00,0x00,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  // 9
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/License - CC BY-NC-SA 3.0 - Legal.pdf b/hardware/digistump/sam/libraries/UTFT/License - CC BY-NC-SA 3.0 - Legal.pdf
new file mode 100644
index 0000000..ed326c9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/License - CC BY-NC-SA 3.0 - Legal.pdf	
@@ -0,0 +1,336 @@
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+         permitted by applicable law, if You Reproduce, Distribute or Publicly Perform the
+         Work either by itself or as part of any Adaptations or Collections, You must not
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+         not assert, as appropriate, this Section, to the fullest extent permitted by the
+         applicable national law, to enable You to reasonably exercise Your right under
+         Section 3(b) of this License (right to make Adaptations) but not otherwise.
+
+5. Representations, Warranties and Disclaimer
+
+UNLESS OTHERWISE MUTUALLY AGREED TO BY THE PARTIES IN WRITING AND TO THE
+FULLEST EXTENT PERMITTED BY APPLICABLE LAW, LICENSOR OFFERS THE WORK AS-IS AND
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+
+CC BY-NC-SA 3.0 – Legal  Page 5/7
+6. Limitation on Liability. EXCEPT TO THE EXTENT REQUIRED BY APPLICABLE LAW, IN NO
+EVENT WILL LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY FOR ANY SPECIAL,
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+
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+
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+         stop distributing the Work at any time; provided, however that any such election will
+         not serve to withdraw this License (or any other license that has been, or is required
+         to be, granted under the terms of this License), and this License will continue in full
+         force and effect unless terminated as stated above.
+
+8. Miscellaneous
+
+    a. Each time You Distribute or Publicly Perform the Work or a Collection, the Licensor
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+
+    b. Each time You Distribute or Publicly Perform an Adaptation, Licensor offers to the
+         recipient a license to the original Work on the same terms and conditions as the
+         license granted to You under this License.
+
+    c. If any provision of this License is invalid or unenforceable under applicable law, it
+         shall not affect the validity or enforceability of the remainder of the terms of this
+         License, and without further action by the parties to this agreement, such provision
+         shall be reformed to the minimum extent necessary to make such provision valid and
+         enforceable.
+
+    d. No term or provision of this License shall be deemed waived and no breach
+         consented to unless such waiver or consent shall be in writing and signed by the
+         party to be charged with such waiver or consent.
+
+    e. This License constitutes the entire agreement between the parties with respect to
+         the Work licensed here. There are no understandings, agreements or representations
+         with respect to the Work not specified here. Licensor shall not be bound by any
+         additional provisions that may appear in any communication from You. This License
+         may not be modified without the mutual written agreement of the Licensor and You.
+
+    f. The rights granted under, and the subject matter referenced, in this License were
+         drafted utilizing the terminology of the Berne Convention for the Protection of
+         Literary and Artistic Works (as amended on September 28, 1979), the Rome
+         Convention of 1961, the WIPO Copyright Treaty of 1996, the WIPO Performances and
+
+CC BY-NC-SA 3.0 – Legal  Page 6/7
+       Phonograms Treaty of 1996 and the Universal Copyright Convention (as revised on
+       July 24, 1971). These rights and subject matter take effect in the relevant jurisdiction
+       in which the License terms are sought to be enforced according to the corresponding
+       provisions of the implementation of those treaty provisions in the applicable national
+       law. If the standard suite of rights granted under applicable copyright law includes
+       additional rights not granted under this License, such additional rights are deemed to
+       be included in the License; this License is not intended to restrict the license of any
+       rights under applicable law.
+
+Creative Commons Notice
+
+Creative Commons is not a party to this License, and makes no warranty whatsoever in connection with
+the Work. Creative Commons will not be liable to You or any party on any legal theory for any damages
+whatsoever, including without limitation any general, special, incidental or consequential damages
+arising in connection to this license. Notwithstanding the foregoing two (2) sentences, if Creative
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+of Licensor.
+
+Except for the limited purpose of indicating to the public that the Work is licensed under the CCPL,
+Creative Commons does not authorize the use by either party of the trademark "Creative Commons" or
+any related trademark or logo of Creative Commons without the prior written consent of Creative
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+usage guidelines, as may be published on its website or otherwise made available upon request from
+time to time. For the avoidance of doubt, this trademark restriction does not form part of this License.
+
+Creative Commons may be contacted at http://creativecommons.org/.
+
+CC BY-NC-SA 3.0 – Legal  Page 7/7
+
diff --git a/hardware/digistump/sam/libraries/UTFT/License - CC BY-NC-SA 3.0 - Summary.pdf b/hardware/digistump/sam/libraries/UTFT/License - CC BY-NC-SA 3.0 - Summary.pdf
new file mode 100644
index 0000000..b35e677
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/License - CC BY-NC-SA 3.0 - Summary.pdf	
@@ -0,0 +1,43 @@
+Attribution-NonCommercial-ShareAlike 3.0 Unported (CC BY-NC-SA 3.0)
+
+You are free:
+
+   to Share — to copy, distribute and transmit the work
+   to Remix — to adapt the work
+
+Under the following conditions:
+
+                   Attribution — You must attribute the work in the manner specified by
+                   the author or licensor (but not in any way that suggests that they
+                   endorse you or your use of the work).
+
+        Noncommercial — You may not use this work for commercial purposes.
+
+        Share Alike — If you alter, transform, or build upon this work, you may
+        distribute the resulting work only under the same or similar license to
+        this one.
+
+With the understanding that:
+
+Waiver        Any of the above conditions can be waived if you get permission
+              from the copyright holder.
+
+Public Domain Where the work or any of its elements is in the public domain under
+                     applicable law, that status is in no way affected by the license.
+
+Other Rights  In no way are any of the following rights affected by the license:
+               • Your fair dealing or fair use rights, or other applicable copyright
+
+                  exceptions and limitations;
+               • The author's moral rights;
+               • Rights other persons may have either in the work itself or in how
+
+                  the work is used, such as publicity or privacy rights.
+
+Notice        For any reuse or distribution, you must make clear to others the
+              license terms of this work. The best way to do this is with a link to
+
+              the web page:
+
+                      http://creativecommons.org/licenses/by-nc-sa/3.0/
+
diff --git a/hardware/digistump/sam/libraries/UTFT/Tools/ImageConverter565.exe b/hardware/digistump/sam/libraries/UTFT/Tools/ImageConverter565.exe
new file mode 100644
index 0000000..a8bb8e8
Binary files /dev/null and b/hardware/digistump/sam/libraries/UTFT/Tools/ImageConverter565.exe differ
diff --git a/hardware/digistump/sam/libraries/UTFT/Tools/ImgConv.exe b/hardware/digistump/sam/libraries/UTFT/Tools/ImgConv.exe
new file mode 100644
index 0000000..624139d
Binary files /dev/null and b/hardware/digistump/sam/libraries/UTFT/Tools/ImgConv.exe differ
diff --git a/hardware/digistump/sam/libraries/UTFT/Tools/Online-tool - ImageConverter 565.url b/hardware/digistump/sam/libraries/UTFT/Tools/Online-tool - ImageConverter 565.url
new file mode 100644
index 0000000..e41696b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/Tools/Online-tool - ImageConverter 565.url	
@@ -0,0 +1,7 @@
+[InternetShortcut]
+URL=http://www.henningkarlsen.com/electronics/t_imageconverter565.php
+IDList=
+IconFile=http://www.henningkarlsen.com/favicon.ico
+IconIndex=1
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
diff --git a/hardware/digistump/sam/libraries/UTFT/Tools/UTFT Image Converters.pdf b/hardware/digistump/sam/libraries/UTFT/Tools/UTFT Image Converters.pdf
new file mode 100644
index 0000000..43a8df6
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/Tools/UTFT Image Converters.pdf	
@@ -0,0 +1,141 @@
+Image Converters
+
+                                                               Part of the UTFT Tools suite
+
+                 Manual
+
+http://electronics.henningkarlsen.com  (C)2013 Henning Karlsen
+ImageConverter565.exe:
+
+Filename: When a supported image file has been opened this field will show the
+                    name of the file (without a file extenstion).
+
+Dimensions: Shows the dimensions of the currently loaded image in pixels.
+
+Converted Size: Shows the size of the converted image with the currently selected
+                               options.
+
+             If this icon is visible the resulting c array produced from the image
+             will not be able to compile. This is due to a limitation in the AVR-GCC
+             compiler.
+             These limitations is only applicable for the Arduino (AVR) target
+             platform and only when saving as a .c file.
+
+Reduce size to: Check this box to enable the image size reduction features.
+
+Lock aspect ratio When this box is checked the width to height ratio will be locked when
+                                  entering new dimensions.
+
+___ x ___ pixels Enter the desired dimensions of the image in these boxes (Width x
+                                 Height).
+
+Quick Select: Use this drop-down list to quickly select one of the pre-selected image
+                           dimensions. Using this drop-down list will de-select the Lock aspect
+                           ratio check box.
+
+Array Name:  The name of the array when saving images as .c array files.
+             The name is set to the filename of the loaded image file as a default.
+             This field is disabled when saving as .raw files as no array name is
+             needed.
+
+Save as: Select what type of file you want to save the image as.
+
+Target Board: Select what type of board the .c array file is indended for.
+                           These radio buttons will be disabled when Save as is set to .raw.
+
+             Click this button to open a new image for conversion.
+
+             Click this button to save the converted image with the current settings.
+             A progress bar will be visible at the bottom of the window during this
+             process. An Abort button will also be visible while saving.
+
+             Click this button to abort the current conversion/save process.
+             This button is only visible during conversion and saving.
+
+             Click this button to exit the program.
+
+UTFT Image Converters                                                                         Page 1
+ImgConv.exe:
+
+---------------------------------------------------------------------------
+ImgConv v1.0 - (C)2013 Henning Karlsen
+---------------------------------------------------------------------------
+This tool is licensed under a CC BY-NC-SA 3.00 (Creative Commons
+Attribution-NonCommercial-ShareAlike 3.0 Unported) license.
+For more information see: http://creativecommons.org/licenses/by-nc-sa/3.0/
+---------------------------------------------------------------------------
+
+Usage:
+          ImgConv  /c|r [/o ] [/t AVR|ARM|PIC32]
+
+:            File(s) to convert
+parameters:
+                       /c         - Create output as .c array files
+
+                       /r         - Create output as .raw files
+
+                       /o   - Set the output directory to 
+
+                       /t  - Select target platform
+
+                                  AVR : Most Arduinos
+
+                                  ARM : Arduino Due
+
+                                  PIC32: chipKit boards
+
+You must specify either /c or /r. All other parameters are optional.
+If /o is omitted the current directory will be used for output.
+If /t is omitted the target platform will be set to AVR.
+
+C:\>
+
+This command line tool can be used for batch conversions as well as for converting single
+images.
+
+ can be the name of a single image or it can contain wildcards (* or ?) for
+converting multiple images. A full path to the file(s) can be included if the image(s) are not
+in the current directory.
+The saved file will have the same filename as the image files that are being converted with
+the exception that the file extension will be changed to .c or .raw depending on what file
+type you are converting to.
+
+You must specify either /c to convert the image(s) to .c array files or /r to convert to .raw
+file(s).
+
+All output files will by default be saved to the current directory. To redirect the output to
+another directory you can specify the /o  parameter. The /o and the path must be
+separated by a space.
+
+The default target platform is AVR (Most Arduinos) if the /t parameter is not used. To select
+another target platform you must use the /t  parameter. Valid platforms are AVR
+(Most Arduinos), ARM (Arduino Due) and PIC32 (chipKit boards). The /t and the target platform
+must be separated by a space.
+This parameter has no effect when converting to .raw files.
+
+This tool does not change the size of the image(s) so you must resize them to the desired size
+before running the conversion.
+
+Examples:
+To convert all the PNG images in the C:\My Pictures directory to .raw files and save them in
+the C:\rawImages directory:
+
+             ImgConv “C:\My Pictures\*.png†/r /o C:\rawImages
+
+To convert a single image (testimage.jpg) in the current directory to a .c array file for
+chipKit boards (PIC32) and save the .c file to the current directory:
+
+             ImgConv testimage.jpg /c /t PIC32
+
+Both examples assume that the ImgConv.exe file is in the current directory or is available somewhere in the search path.
+
+The source code for the tools are available upon request for the purpose
+                           of porting them to other operating systems
+
+These tools are licensed under a CC BY-NC-SA 3.0 (Creative Commons Attribution-
+NonCommercial-ShareAlike 3.0 Unported) License.
+
+For more information see: http://creativecommons.org/licenses/by-nc-sa/3.0/
+
+UTFT Image Converters                                                            Page 2
+
diff --git a/hardware/digistump/sam/libraries/UTFT/UTFT.cpp b/hardware/digistump/sam/libraries/UTFT/UTFT.cpp
new file mode 100644
index 0000000..3199b47
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/UTFT.cpp
@@ -0,0 +1,1378 @@
+/*
+  UTFT.cpp - Arduino/chipKit library support for Color TFT LCD Boards
+  Copyright (C)2010-2013 Henning Karlsen. All right reserved
+  
+  This library is the continuation of my ITDB02_Graph, ITDB02_Graph16
+  and RGB_GLCD libraries for Arduino and chipKit. As the number of 
+  supported display modules and controllers started to increase I felt 
+  it was time to make a single, universal library as it will be much 
+  easier to maintain in the future.
+
+  Basic functionality of this library was origianlly based on the 
+  demo-code provided by ITead studio (for the ITDB02 modules) and 
+  NKC Electronics (for the RGB GLCD module/shield).
+
+  This library supports a number of 8bit, 16bit and serial graphic 
+  displays, and will work with both Arduino and chipKit boards. For a 
+  full list of tested display modules and controllers, see the 
+  document UTFT_Supported_display_modules_&_controllers.pdf.
+
+  When using 8bit and 16bit display modules there are some 
+  requirements you must adhere to. These requirements can be found 
+  in the document UTFT_Requirements.pdf.
+  There are no special requirements when using serial displays.
+
+  You can always find the latest version of the library at 
+  http://electronics.henningkarlsen.com/
+
+  If you make any modifications or improvements to the code, I would 
+  appreciate that you share the code with me so that I might include 
+  it in the next release. I can be contacted through 
+  http://electronics.henningkarlsen.com/contact.php.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the CC BY-NC-SA 3.0 license.
+  Please see the included documents for further information.
+*/
+
+#include "UTFT.h"
+#include 
+
+// Include hardware-specific functions for the correct MCU
+#if defined(__AVR__)
+	#include 
+	#include "hardware/avr/HW_AVR.h"
+	#if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__)
+		#include "hardware/avr/HW_ATmega1280.h" 
+	#elif defined(__AVR_ATmega328P__)
+		#include "hardware/avr/HW_ATmega328P.h"
+	#elif defined(__AVR_ATmega32U4__)
+		#include "hardware/avr/HW_ATmega32U4.h"
+	#elif defined(__AVR_ATmega168__)
+		#error "ATmega168 MCUs are not supported because they have too little flash memory!"
+	#else
+		#error "Unsupported AVR MCU!"
+	#endif
+#elif defined(__PIC32MX__)
+  #include "hardware/pic32/HW_PIC32.h"
+  #if defined(__32MX320F128H__)
+    #pragma message("Compiling for chipKIT UNO32 (__32MX320F128H__)")
+	#include "hardware/pic32/HW_PIC32MX320F128H.h"
+  #elif defined(__32MX340F512H__)
+    #pragma message("Compiling for chipKIT uC32 (__32MX340F512H__)")
+	#include "hardware/pic32/HW_PIC32MX340F512H.h"
+  #elif defined(__32MX795F512L__)
+    #pragma message("Compiling for chipKIT MAX32 (__32MX795F512L__)")
+	#include "hardware/pic32/HW_PIC32MX795F512L.h"
+  #else
+    #error "Unsupported PIC32 MCU!"
+  #endif  
+#elif defined(__arm__)
+	#include "hardware/arm/HW_ARM.h"
+	#if defined(__SAM3X8E__)
+		#pragma message("Compiling for Arduino Due (AT91SAM3X8E)...")
+		#include "hardware/arm/HW_SAM3X8E.h"
+	#else
+		#error "Unsupported ARM MCU!"
+	#endif
+#endif
+#include "memorysaver.h"
+
+UTFT::UTFT()
+{
+}
+
+UTFT::UTFT(byte model, int RS, int WR,int CS, int RST, int SER)
+{ 
+	switch (model)
+	{
+		case HX8347A:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=16;
+			break;
+		case ILI9327:
+			disp_x_size=239;
+			disp_y_size=399;
+			display_transfer_mode=16;
+			break;
+		case SSD1289:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=16;
+			break;
+		case ILI9325C:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=8;
+			break;
+		case ILI9325D_8:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=8;
+			break;
+		case ILI9325D_16:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=16;
+			break;
+		case ILI9325D_16ALT:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=16;
+			break;
+		case HX8340B_8:
+			disp_x_size=175;
+			disp_y_size=219;
+			display_transfer_mode=8;
+			break;
+		case HX8340B_S:
+			disp_x_size=175;
+			disp_y_size=219;
+			display_transfer_mode=1;
+			display_serial_mode=SERIAL_4PIN;
+			break;
+		case HX8352A:
+			disp_x_size=239;
+			disp_y_size=399;
+			display_transfer_mode=16;
+			break;
+		case ST7735:
+			disp_x_size=127;
+			disp_y_size=159;
+			display_transfer_mode=1;
+			display_serial_mode=SERIAL_5PIN;
+			break;
+		case ST7735S:
+			disp_x_size=127;
+			disp_y_size=159;
+			display_transfer_mode=1;
+			display_serial_mode=SERIAL_5PIN;
+			break;
+		case PCF8833:
+			disp_x_size=127;
+			disp_y_size=127;
+			display_transfer_mode=1;
+			display_serial_mode=SERIAL_5PIN;
+			break;
+		case S1D19122:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=16;
+			break;
+		case SSD1963_480:
+			disp_x_size=271;
+			disp_y_size=479;
+			display_transfer_mode=16;
+			break;
+		case SSD1963_800:
+			disp_x_size=479;
+			disp_y_size=799;
+			display_transfer_mode=16;
+			break;
+		case SSD1963_800ALT:
+			disp_x_size=479;
+			disp_y_size=799;
+			display_transfer_mode=16;
+			break;
+		case S6D1121_8:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=8;
+			break;
+		case S6D1121_16:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=16;
+			break;
+		case SSD1289LATCHED:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=LATCHED_16;
+			break;
+		case ILI9320_8:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=8;
+			break;
+		case ILI9320_16:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=16;
+			break;
+		case SSD1289_8:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=8;
+			break;
+		case ILI9481:
+			disp_x_size=319;
+			disp_y_size=479;
+			display_transfer_mode=16;
+			break;
+		case S6D0164:
+			disp_x_size=175;
+			disp_y_size=219;
+			display_transfer_mode=8;
+			break;
+		case ILI9341_S5P:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=1;
+			display_serial_mode=SERIAL_5PIN;
+			break;
+		case ILI9341_S4P:
+			disp_x_size=239;
+			disp_y_size=319;
+			display_transfer_mode=1;
+			display_serial_mode=SERIAL_4PIN;
+			break;
+	}
+	display_model=model;
+
+	if (display_transfer_mode!=1)
+	{
+		_set_direction_registers(display_transfer_mode);
+		P_RS	= portOutputRegister(digitalPinToPort(RS));
+		B_RS	= digitalPinToBitMask(RS);
+		P_WR	= portOutputRegister(digitalPinToPort(WR));
+		B_WR	= digitalPinToBitMask(WR);
+		P_CS	= portOutputRegister(digitalPinToPort(CS));
+		B_CS	= digitalPinToBitMask(CS);
+		P_RST	= portOutputRegister(digitalPinToPort(RST));
+		B_RST	= digitalPinToBitMask(RST);
+		if (display_transfer_mode==LATCHED_16)
+		{
+			P_ALE	= portOutputRegister(digitalPinToPort(SER));
+			B_ALE	= digitalPinToBitMask(SER);
+			pinMode(SER,OUTPUT);
+			cbi(P_ALE, B_ALE);
+			pinMode(8,OUTPUT);
+			digitalWrite(8, LOW);
+		}
+		pinMode(RS,OUTPUT);
+		pinMode(WR,OUTPUT);
+		pinMode(CS,OUTPUT);
+		pinMode(RST,OUTPUT);
+	}
+	else
+	{
+		P_SDA	= portOutputRegister(digitalPinToPort(RS));
+		B_SDA	= digitalPinToBitMask(RS);
+		P_SCL	= portOutputRegister(digitalPinToPort(WR));
+		B_SCL	= digitalPinToBitMask(WR);
+		P_CS	= portOutputRegister(digitalPinToPort(CS));
+		B_CS	= digitalPinToBitMask(CS);
+		P_RST	= portOutputRegister(digitalPinToPort(RST));
+		B_RST	= digitalPinToBitMask(RST);
+		if (display_serial_mode!=SERIAL_4PIN)
+		{
+			P_RS	= portOutputRegister(digitalPinToPort(SER));
+			B_RS	= digitalPinToBitMask(SER);
+			pinMode(SER,OUTPUT);
+		}
+		pinMode(RS,OUTPUT);
+		pinMode(WR,OUTPUT);
+		pinMode(CS,OUTPUT);
+		pinMode(RST,OUTPUT);
+	}
+}
+
+void UTFT::LCD_Write_COM(char VL)  
+{   
+	if (display_transfer_mode!=1)
+	{
+		cbi(P_RS, B_RS);
+		LCD_Writ_Bus(0x00,VL,display_transfer_mode);
+	}
+	else
+		LCD_Writ_Bus(0x00,VL,display_transfer_mode);
+}
+
+void UTFT::LCD_Write_DATA(char VH,char VL)
+{
+	if (display_transfer_mode!=1)
+	{
+		sbi(P_RS, B_RS);
+		LCD_Writ_Bus(VH,VL,display_transfer_mode);
+	}
+	else
+	{
+		LCD_Writ_Bus(0x01,VH,display_transfer_mode);
+		LCD_Writ_Bus(0x01,VL,display_transfer_mode);
+	}
+}
+
+void UTFT::LCD_Write_DATA(char VL)
+{
+	if (display_transfer_mode!=1)
+	{
+		sbi(P_RS, B_RS);
+		LCD_Writ_Bus(0x00,VL,display_transfer_mode);
+	}
+	else
+		LCD_Writ_Bus(0x01,VL,display_transfer_mode);
+}
+
+void UTFT::LCD_Write_COM_DATA(char com1,int dat1)
+{
+     LCD_Write_COM(com1);
+     LCD_Write_DATA(dat1>>8,dat1);
+}
+
+void UTFT::InitLCD(byte orientation)
+{
+	orient=orientation;
+	_hw_special_init();
+
+	sbi(P_RST, B_RST);
+	delay(5); 
+	cbi(P_RST, B_RST);
+	delay(15);
+	sbi(P_RST, B_RST);
+	delay(15);
+
+	cbi(P_CS, B_CS);
+
+	switch(display_model)
+	{
+#ifndef DISABLE_HX8347A
+	#include "tft_drivers/hx8347a/initlcd.h"
+#endif
+#ifndef DISABLE_ILI9327
+	#include "tft_drivers/ili9327/initlcd.h"
+#endif
+#ifndef DISABLE_SSD1289
+	#include "tft_drivers/ssd1289/initlcd.h"
+#endif
+#ifndef DISABLE_ILI9325C
+	#include "tft_drivers/ili9325c/initlcd.h"
+#endif
+#ifndef DISABLE_ILI9325D
+	#include "tft_drivers/ili9325d/default/initlcd.h"
+#endif
+#ifndef DISABLE_ILI9325D_ALT
+	#include "tft_drivers/ili9325d/alt/initlcd.h"
+#endif
+#ifndef DISABLE_HX8340B_8
+	#include "tft_drivers/hx8340b/8/initlcd.h"
+#endif
+#ifndef DISABLE_HX8340B_S
+	#include "tft_drivers/hx8340b/s/initlcd.h"
+#endif
+#ifndef DISABLE_ST7735
+	#include "tft_drivers/st7735/initlcd.h"
+#endif
+#ifndef DISABLE_PCF8833
+	#include "tft_drivers/pcf8833/initlcd.h"
+#endif
+#ifndef DISABLE_S1D19122
+	#include "tft_drivers/s1d19122/initlcd.h"
+#endif
+#ifndef DISABLE_HX8352A
+	#include "tft_drivers/hx8352a/initlcd.h"
+#endif
+#ifndef DISABLE_SSD1963_480
+	#include "tft_drivers/ssd1963/480/initlcd.h"
+#endif
+#ifndef DISABLE_SSD1963_800
+	#include "tft_drivers/ssd1963/800/initlcd.h"
+#endif
+#ifndef DISABLE_SSD1963_800_ALT
+	#include "tft_drivers/ssd1963/800alt/initlcd.h"
+#endif
+#ifndef DISABLE_S6D1121
+	#include "tft_drivers/s6d1121/initlcd.h"
+#endif
+#ifndef DISABLE_ILI9320
+	#include "tft_drivers/ili9320/initlcd.h"
+#endif
+#ifndef DISABLE_ILI9481
+	#include "tft_drivers/ili9481/initlcd.h"
+#endif
+#ifndef DISABLE_S6D0164
+	#include "tft_drivers/s6d0164/initlcd.h"
+#endif
+#ifndef DISABLE_ST7735S
+	#include "tft_drivers/st7735s/initlcd.h"
+#endif
+#ifndef DISABLE_ILI9341_S4P
+	#include "tft_drivers/ili9341/s4p/initlcd.h"
+#endif
+#ifndef DISABLE_ILI9341_S5P
+	#include "tft_drivers/ili9341/s5p/initlcd.h"
+#endif
+	}
+
+	sbi (P_CS, B_CS); 
+
+	setColor(255, 255, 255);
+	setBackColor(0, 0, 0);
+	cfont.font=0;
+	_transparent = false;
+}
+
+void UTFT::setXY(word x1, word y1, word x2, word y2)
+{
+	int tmp;
+
+	if (orient==LANDSCAPE)
+	{
+		swap(word, x1, y1);
+		swap(word, x2, y2)
+		y1=disp_y_size-y1;
+		y2=disp_y_size-y2;
+		swap(word, y1, y2)
+	}
+
+	switch(display_model)
+	{
+#ifndef DISABLE_HX8347A
+	#include "tft_drivers/hx8347a/setxy.h"
+#endif
+#ifndef DISABLE_HX8352A
+	#include "tft_drivers/hx8352a/setxy.h"
+#endif
+#ifndef DISABLE_ILI9327
+	#include "tft_drivers/ili9327/setxy.h"
+#endif
+#ifndef DISABLE_SSD1289
+	#include "tft_drivers/ssd1289/setxy.h"
+#endif
+#ifndef DISABLE_ILI9325C
+	#include "tft_drivers/ili9325c/setxy.h"
+#endif
+#ifndef DISABLE_ILI9325D
+	#include "tft_drivers/ili9325d/default/setxy.h"
+#endif
+#ifndef DISABLE_ILI9325D_ALT
+	#include "tft_drivers/ili9325d/alt/setxy.h"
+#endif
+#ifndef DISABLE_HX8340B_8
+	#include "tft_drivers/hx8340b/8/setxy.h"
+#endif
+#ifndef DISABLE_HX8340B_S
+	#include "tft_drivers/hx8340b/s/setxy.h"
+#endif
+#ifndef DISABLE_ST7735
+	#include "tft_drivers/st7735/setxy.h"
+#endif
+#ifndef DISABLE_S1D19122
+	#include "tft_drivers/s1d19122/setxy.h"
+#endif
+#ifndef DISABLE_PCF8833
+	#include "tft_drivers/pcf8833/setxy.h"
+#endif
+#ifndef DISABLE_SSD1963_480
+	#include "tft_drivers/ssd1963/480/setxy.h"
+#endif
+#ifndef DISABLE_SSD1963_800
+	#include "tft_drivers/ssd1963/800/setxy.h"
+#endif
+#ifndef DISABLE_SSD1963_800_ALT
+	#include "tft_drivers/ssd1963/800alt/setxy.h"
+#endif
+#ifndef DISABLE_S6D1121
+	#include "tft_drivers/s6d1121/setxy.h"
+#endif
+#ifndef DISABLE_ILI9320
+	#include "tft_drivers/ili9320/setxy.h"
+#endif
+#ifndef DISABLE_ILI9481
+	#include "tft_drivers/ili9481/setxy.h"
+#endif
+#ifndef DISABLE_S6D0164
+	#include "tft_drivers/s6d0164/setxy.h"
+#endif
+#ifndef DISABLE_ST7735S
+	#include "tft_drivers/st7735s/setxy.h"
+#endif
+#ifndef DISABLE_ILI9341_S4P
+	#include "tft_drivers/ili9341/s4p/setxy.h"
+#endif
+#ifndef DISABLE_ILI9341_S5P
+	#include "tft_drivers/ili9341/s5p/setxy.h"
+#endif
+	}
+}
+
+void UTFT::clrXY()
+{
+	if (orient==PORTRAIT)
+		setXY(0,0,disp_x_size,disp_y_size);
+	else
+		setXY(0,0,disp_y_size,disp_x_size);
+}
+
+void UTFT::drawRect(int x1, int y1, int x2, int y2)
+{
+	int tmp;
+
+	if (x1>x2)
+	{
+		swap(int, x1, x2);
+	}
+	if (y1>y2)
+	{
+		swap(int, y1, y2);
+	}
+
+	drawHLine(x1, y1, x2-x1);
+	drawHLine(x1, y2, x2-x1);
+	drawVLine(x1, y1, y2-y1);
+	drawVLine(x2, y1, y2-y1);
+}
+
+void UTFT::drawRoundRect(int x1, int y1, int x2, int y2)
+{
+	int tmp;
+
+	if (x1>x2)
+	{
+		swap(int, x1, x2);
+	}
+	if (y1>y2)
+	{
+		swap(int, y1, y2);
+	}
+	if ((x2-x1)>4 && (y2-y1)>4)
+	{
+		drawPixel(x1+1,y1+1);
+		drawPixel(x2-1,y1+1);
+		drawPixel(x1+1,y2-1);
+		drawPixel(x2-1,y2-1);
+		drawHLine(x1+2, y1, x2-x1-4);
+		drawHLine(x1+2, y2, x2-x1-4);
+		drawVLine(x1, y1+2, y2-y1-4);
+		drawVLine(x2, y1+2, y2-y1-4);
+	}
+}
+
+void UTFT::fillRect(int x1, int y1, int x2, int y2)
+{
+	int tmp;
+
+	if (x1>x2)
+	{
+		swap(int, x1, x2);
+	}
+	if (y1>y2)
+	{
+		swap(int, y1, y2);
+	}
+	if (display_transfer_mode==16)
+	{
+		cbi(P_CS, B_CS);
+		setXY(x1, y1, x2, y2);
+		sbi(P_RS, B_RS);
+		_fast_fill_16(fch,fcl,((long(x2-x1)+1)*(long(y2-y1)+1)));
+		sbi(P_CS, B_CS);
+	}
+	else if ((display_transfer_mode==8) and (fch==fcl))
+	{
+		cbi(P_CS, B_CS);
+		setXY(x1, y1, x2, y2);
+		sbi(P_RS, B_RS);
+		_fast_fill_8(fch,((long(x2-x1)+1)*(long(y2-y1)+1)));
+		sbi(P_CS, B_CS);
+	}
+	else
+	{
+		if (orient==PORTRAIT)
+		{
+			for (int i=0; i<((y2-y1)/2)+1; i++)
+			{
+				drawHLine(x1, y1+i, x2-x1);
+				drawHLine(x1, y2-i, x2-x1);
+			}
+		}
+		else
+		{
+			for (int i=0; i<((x2-x1)/2)+1; i++)
+			{
+				drawVLine(x1+i, y1, y2-y1);
+				drawVLine(x2-i, y1, y2-y1);
+			}
+		}
+	}
+}
+
+void UTFT::fillRoundRect(int x1, int y1, int x2, int y2)
+{
+	int tmp;
+
+	if (x1>x2)
+	{
+		swap(int, x1, x2);
+	}
+	if (y1>y2)
+	{
+		swap(int, y1, y2);
+	}
+
+	if ((x2-x1)>4 && (y2-y1)>4)
+	{
+		for (int i=0; i<((y2-y1)/2)+1; i++)
+		{
+			switch(i)
+			{
+			case 0:
+				drawHLine(x1+2, y1+i, x2-x1-4);
+				drawHLine(x1+2, y2-i, x2-x1-4);
+				break;
+			case 1:
+				drawHLine(x1+1, y1+i, x2-x1-2);
+				drawHLine(x1+1, y2-i, x2-x1-2);
+				break;
+			default:
+				drawHLine(x1, y1+i, x2-x1);
+				drawHLine(x1, y2-i, x2-x1);
+			}
+		}
+	}
+}
+
+void UTFT::drawCircle(int x, int y, int radius)
+{
+	int f = 1 - radius;
+	int ddF_x = 1;
+	int ddF_y = -2 * radius;
+	int x1 = 0;
+	int y1 = radius;
+ 
+	cbi(P_CS, B_CS);
+	setXY(x, y + radius, x, y + radius);
+	LCD_Write_DATA(fch,fcl);
+	setXY(x, y - radius, x, y - radius);
+	LCD_Write_DATA(fch,fcl);
+	setXY(x + radius, y, x + radius, y);
+	LCD_Write_DATA(fch,fcl);
+	setXY(x - radius, y, x - radius, y);
+	LCD_Write_DATA(fch,fcl);
+ 
+	while(x1 < y1)
+	{
+		if(f >= 0) 
+		{
+			y1--;
+			ddF_y += 2;
+			f += ddF_y;
+		}
+		x1++;
+		ddF_x += 2;
+		f += ddF_x;    
+		setXY(x + x1, y + y1, x + x1, y + y1);
+		LCD_Write_DATA(fch,fcl);
+		setXY(x - x1, y + y1, x - x1, y + y1);
+		LCD_Write_DATA(fch,fcl);
+		setXY(x + x1, y - y1, x + x1, y - y1);
+		LCD_Write_DATA(fch,fcl);
+		setXY(x - x1, y - y1, x - x1, y - y1);
+		LCD_Write_DATA(fch,fcl);
+		setXY(x + y1, y + x1, x + y1, y + x1);
+		LCD_Write_DATA(fch,fcl);
+		setXY(x - y1, y + x1, x - y1, y + x1);
+		LCD_Write_DATA(fch,fcl);
+		setXY(x + y1, y - x1, x + y1, y - x1);
+		LCD_Write_DATA(fch,fcl);
+		setXY(x - y1, y - x1, x - y1, y - x1);
+		LCD_Write_DATA(fch,fcl);
+	}
+	sbi(P_CS, B_CS);
+	clrXY();
+}
+
+void UTFT::fillCircle(int x, int y, int radius)
+{
+	for(int y1=-radius; y1<=0; y1++) 
+		for(int x1=-radius; x1<=0; x1++)
+			if(x1*x1+y1*y1 <= radius*radius) 
+			{
+				drawHLine(x+x1, y+y1, 2*(-x1));
+				drawHLine(x+x1, y-y1, 2*(-x1));
+				break;
+			}
+}
+
+void UTFT::clrScr()
+{
+	long i;
+	
+	cbi(P_CS, B_CS);
+	clrXY();
+	if (display_transfer_mode!=1)
+		sbi(P_RS, B_RS);
+	if (display_transfer_mode==16)
+		_fast_fill_16(0,0,((disp_x_size+1)*(disp_y_size+1)));
+	else if (display_transfer_mode==8)
+		_fast_fill_8(0,((disp_x_size+1)*(disp_y_size+1)));
+	else
+	{
+		for (i=0; i<((disp_x_size+1)*(disp_y_size+1)); i++)
+		{
+			if (display_transfer_mode!=1)
+				LCD_Writ_Bus(0,0,display_transfer_mode);
+			else
+			{
+				LCD_Writ_Bus(1,0,display_transfer_mode);
+				LCD_Writ_Bus(1,0,display_transfer_mode);
+			}
+		}
+	}
+	sbi(P_CS, B_CS);
+}
+
+void UTFT::fillScr(byte r, byte g, byte b)
+{
+	word color = ((r&248)<<8 | (g&252)<<3 | (b&248)>>3);
+	fillScr(color);
+}
+
+void UTFT::fillScr(word color)
+{
+	long i;
+	char ch, cl;
+	
+	ch=byte(color>>8);
+	cl=byte(color & 0xFF);
+
+	cbi(P_CS, B_CS);
+	clrXY();
+	if (display_transfer_mode!=1)
+		sbi(P_RS, B_RS);
+	if (display_transfer_mode==16)
+		_fast_fill_16(ch,cl,((disp_x_size+1)*(disp_y_size+1)));
+	else if ((display_transfer_mode==8) and (ch==cl))
+		_fast_fill_8(ch,((disp_x_size+1)*(disp_y_size+1)));
+	else
+	{
+		for (i=0; i<((disp_x_size+1)*(disp_y_size+1)); i++)
+		{
+			if (display_transfer_mode!=1)
+				LCD_Writ_Bus(ch,cl,display_transfer_mode);
+			else
+			{
+				LCD_Writ_Bus(1,ch,display_transfer_mode);
+				LCD_Writ_Bus(1,cl,display_transfer_mode);
+			}
+		}
+	}
+	sbi(P_CS, B_CS);
+}
+
+void UTFT::setColor(byte r, byte g, byte b)
+{
+	fch=((r&248)|g>>5);
+	fcl=((g&28)<<3|b>>3);
+}
+
+void UTFT::setColor(word color)
+{
+	fch=byte(color>>8);
+	fcl=byte(color & 0xFF);
+}
+
+word UTFT::getColor()
+{
+	return (fch<<8) | fcl;
+}
+
+void UTFT::setBackColor(byte r, byte g, byte b)
+{
+	bch=((r&248)|g>>5);
+	bcl=((g&28)<<3|b>>3);
+	_transparent=false;
+}
+
+void UTFT::setBackColor(uint32_t color)
+{
+	if (color==VGA_TRANSPARENT)
+		_transparent=true;
+	else
+	{
+		bch=byte(color>>8);
+		bcl=byte(color & 0xFF);
+		_transparent=false;
+	}
+}
+
+word UTFT::getBackColor()
+{
+	return (bch<<8) | bcl;
+}
+
+void UTFT::setPixel(word color)
+{
+	LCD_Write_DATA((color>>8),(color&0xFF));	// rrrrrggggggbbbbb
+}
+
+void UTFT::drawPixel(int x, int y)
+{
+	cbi(P_CS, B_CS);
+	setXY(x, y, x, y);
+	setPixel((fch<<8)|fcl);
+	sbi(P_CS, B_CS);
+	clrXY();
+}
+
+void UTFT::drawLine(int x1, int y1, int x2, int y2)
+{
+	if (y1==y2)
+		drawHLine(x1, y1, x2-x1);
+	else if (x1==x2)
+		drawVLine(x1, y1, y2-y1);
+	else
+	{
+		unsigned int	dx = (x2 > x1 ? x2 - x1 : x1 - x2);
+		short			xstep =  x2 > x1 ? 1 : -1;
+		unsigned int	dy = (y2 > y1 ? y2 - y1 : y1 - y2);
+		short			ystep =  y2 > y1 ? 1 : -1;
+		int				col = x1, row = y1;
+
+		cbi(P_CS, B_CS);
+		if (dx < dy)
+		{
+			int t = - (dy >> 1);
+			while (true)
+			{
+				setXY (col, row, col, row);
+				LCD_Write_DATA (fch, fcl);
+				if (row == y2)
+					return;
+				row += ystep;
+				t += dx;
+				if (t >= 0)
+				{
+					col += xstep;
+					t   -= dy;
+				}
+			} 
+		}
+		else
+		{
+			int t = - (dx >> 1);
+			while (true)
+			{
+				setXY (col, row, col, row);
+				LCD_Write_DATA (fch, fcl);
+				if (col == x2)
+					return;
+				col += xstep;
+				t += dy;
+				if (t >= 0)
+				{
+					row += ystep;
+					t   -= dx;
+				}
+			} 
+		}
+		sbi(P_CS, B_CS);
+	}
+	clrXY();
+}
+
+void UTFT::drawHLine(int x, int y, int l)
+{
+	if (l<0)
+	{
+		l = -l;
+		x -= l;
+	}
+	cbi(P_CS, B_CS);
+	setXY(x, y, x+l, y);
+	if (display_transfer_mode == 16)
+	{
+		sbi(P_RS, B_RS);
+		_fast_fill_16(fch,fcl,l);
+	}
+	else if ((display_transfer_mode==8) and (fch==fcl))
+	{
+		sbi(P_RS, B_RS);
+		_fast_fill_8(fch,l);
+	}
+	else
+	{
+		for (int i=0; i=0; zz--)
+				{
+					ch=pgm_read_byte(&cfont.font[temp+zz]);
+					for(i=0;i<8;i++)
+					{   
+						if((ch&(1<0)
+		{
+			buf[c]=48+(num % 10);
+			c++;
+			num=(num-(num % 10))/10;
+		}
+		buf[c]=0;
+	  
+		if (neg)
+		{
+			st[0]=45;
+		}
+	  
+		if (length>(c+neg))
+		{
+			for (int i=0; i<(length-c-neg); i++)
+			{
+				st[i+neg]=filler;
+				f++;
+			}
+		}
+
+		for (int i=0; i5)
+		dec=5;
+
+	if (num<0)
+		neg = true;
+
+	_convert_float(st, num, length, dec);
+
+	if (divider != '.')
+	{
+		for (int i=0; i>8,col & 0xff);
+			}
+			sbi(P_CS, B_CS);
+		}
+		else
+		{
+			cbi(P_CS, B_CS);
+			for (ty=0; ty=0; tx--)
+				{
+					col=pgm_read_word(&data[(ty*sx)+tx]);
+					LCD_Write_DATA(col>>8,col & 0xff);
+				}
+			}
+			sbi(P_CS, B_CS);
+		}
+	}
+	else
+	{
+		if (orient==PORTRAIT)
+		{
+			cbi(P_CS, B_CS);
+			for (ty=0; ty>8,col & 0xff);
+					}
+			}
+			sbi(P_CS, B_CS);
+		}
+		else
+		{
+			cbi(P_CS, B_CS);
+			for (ty=0; ty=0; tx--)
+					{
+						col=pgm_read_word(&data[(ty*sx)+tx]);
+						for (tsx=0; tsx>8,col & 0xff);
+					}
+				}
+			}
+			sbi(P_CS, B_CS);
+		}
+	}
+	clrXY();
+}
+
+void UTFT::drawBitmap(int x, int y, int sx, int sy, bitmapdatatype data, int deg, int rox, int roy)
+{
+	unsigned int col;
+	int tx, ty, newx, newy;
+	byte r, g, b;
+	double radian;
+	radian=deg*0.0175;  
+
+	if (deg==0)
+		drawBitmap(x, y, sx, sy, data);
+	else
+	{
+		cbi(P_CS, B_CS);
+		for (ty=0; ty>8,col & 0xff);
+			}
+		sbi(P_CS, B_CS);
+	}
+	clrXY();
+}
+
+void UTFT::lcdOff()
+{
+	cbi(P_CS, B_CS);
+	switch (display_model)
+	{
+	case PCF8833:
+		LCD_Write_COM(0x28);
+		break;
+	}
+	sbi(P_CS, B_CS);
+}
+
+void UTFT::lcdOn()
+{
+	cbi(P_CS, B_CS);
+	switch (display_model)
+	{
+	case PCF8833:
+		LCD_Write_COM(0x29);
+		break;
+	}
+	sbi(P_CS, B_CS);
+}
+
+void UTFT::setContrast(char c)
+{
+	cbi(P_CS, B_CS);
+	switch (display_model)
+	{
+	case PCF8833:
+		if (c>64) c=64;
+		LCD_Write_COM(0x25);
+		LCD_Write_DATA(c);
+		break;
+	}
+	sbi(P_CS, B_CS);
+}
+
+int UTFT::getDisplayXSize()
+{
+	if (orient==PORTRAIT)
+		return disp_x_size+1;
+	else
+		return disp_y_size+1;
+}
+
+int UTFT::getDisplayYSize()
+{
+	if (orient==PORTRAIT)
+		return disp_y_size+1;
+	else
+		return disp_x_size+1;
+}
diff --git a/hardware/digistump/sam/libraries/UTFT/UTFT.h b/hardware/digistump/sam/libraries/UTFT/UTFT.h
new file mode 100644
index 0000000..97db4c5
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/UTFT.h
@@ -0,0 +1,243 @@
+/*
+  UTFT.h - Arduino/chipKit library support for Color TFT LCD Boards
+  Copyright (C)2010-2013 Henning Karlsen. All right reserved
+  
+  This library is the continuation of my ITDB02_Graph, ITDB02_Graph16
+  and RGB_GLCD libraries for Arduino and chipKit. As the number of 
+  supported display modules and controllers started to increase I felt 
+  it was time to make a single, universal library as it will be much 
+  easier to maintain in the future.
+
+  Basic functionality of this library was origianlly based on the 
+  demo-code provided by ITead studio (for the ITDB02 modules) and 
+  NKC Electronics (for the RGB GLCD module/shield).
+
+  This library supports a number of 8bit, 16bit and serial graphic 
+  displays, and will work with both Arduino and chipKit boards. For a 
+  full list of tested display modules and controllers, see the 
+  document UTFT_Supported_display_modules_&_controllers.pdf.
+
+  When using 8bit and 16bit display modules there are some 
+  requirements you must adhere to. These requirements can be found 
+  in the document UTFT_Requirements.pdf.
+  There are no special requirements when using serial displays.
+
+  You can always find the latest version of the library at 
+  http://electronics.henningkarlsen.com/
+
+  If you make any modifications or improvements to the code, I would 
+  appreciate that you share the code with me so that I might include 
+  it in the next release. I can be contacted through 
+  http://electronics.henningkarlsen.com/contact.php.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the CC BY-NC-SA 3.0 license.
+  Please see the included documents for further information.
+*/
+
+#ifndef UTFT_h
+#define UTFT_h
+
+#define UTFT_VERSION	260
+
+#define LEFT 0
+#define RIGHT 9999
+#define CENTER 9998
+
+#define PORTRAIT 0
+#define LANDSCAPE 1
+
+#define HX8347A			0
+#define ILI9327			1
+#define SSD1289			2
+#define ILI9325C		3
+#define ILI9325D_8		4
+#define ILI9325D_16		5
+#define HX8340B_8		6
+#define HX8340B_S		7
+#define HX8352A			8
+#define ST7735			9
+#define PCF8833			10
+#define S1D19122		11
+#define SSD1963_480		12
+#define SSD1963_800		13
+#define S6D1121_8		14
+#define S6D1121_16		15
+#define	SSD1289LATCHED	16
+#define ILI9320_8		17
+#define ILI9320_16		18
+#define SSD1289_8		19
+#define	SSD1963_800ALT	20
+#define ILI9481			21
+#define ILI9325D_16ALT	22
+#define S6D0164			23
+#define ST7735S			24
+#define ILI9341_S5P		25
+#define ILI9341_S4P		26
+
+#define ITDB32			0	// HX8347-A (16bit)
+#define ITDB32WC		1	// ILI9327  (16bit)
+#define TFT01_32W		1	// ILI9327	(16bit)
+#define ITDB32S			2	// SSD1289  (16bit)
+#define TFT01_32		2	// SSD1289  (16bit)
+#define CTE32			2	// SSD1289  (16bit)
+#define GEEE32			2	// SSD1289  (16bit)
+#define ITDB24			3	// ILI9325C (8bit)
+#define ITDB24D			4	// ILI9325D (8bit)
+#define ITDB24DWOT		4	// ILI9325D (8bit)
+#define ITDB28			4	// ILI9325D (8bit)
+#define TFT01_24_8		4	// ILI9325D (8bit)
+#define TFT01_24_16		5	// ILI9325D (16bit)
+#define ITDB22			6	// HX8340-B (8bit)
+#define GEEE22			6	// HX8340-B (8bit)
+#define ITDB22SP		7	// HX8340-B (Serial)
+#define ITDB32WD		8	// HX8352-A (16bit)
+#define TFT01_32WD		8	// HX8352-A	(16bit)
+#define CTE32W			8	// HX8352-A	(16bit)
+#define ITDB18SP		9	// ST7735   (Serial)
+#define LPH9135			10	// PCF8833	(Serial)
+#define ITDB25H			11	// S1D19122	(16bit)
+#define ITDB43			12	// SSD1963	(16bit) 480x272
+#define ITDB50			13	// SSD1963	(16bit) 800x480
+#define TFT01_50		13	// SSD1963	(16bit) 800x480
+#define CTE50			13	// SSD1963	(16bit) 800x480
+#define ITDB24E_8		14	// S6D1121	(8bit)
+#define ITDB24E_16		15	// S6D1121	(16bit)
+#define INFINIT32		16	// SSD1289	(Latched 16bit) -- Legacy, will be removed later
+#define ELEE32_REVA		16	// SSD1289	(Latched 16bit)
+#define GEEE24			17	// ILI9320	(8bit)
+#define GEEE28			18	// ILI9320	(16bit)
+#define ELEE32_REVB		19	// SSD1289	(8bit)
+#define TFT01_70		20	// SSD1963	(16bit) 800x480 Alternative Init
+#define CTE70			20	// SSD1963	(16bit) 800x480 Alternative Init
+#define CTE32HR			21	// ILI9481	(16bit)
+#define CTE28			22	// ILI9325D (16bit) Alternative Init
+#define TFT01_28		22	// ILI9325D (16bit) Alternative Init
+#define CTE22			23	// S6D0164	(8bit)
+#define TFT01_22		23	// S6D0164	(8bit)
+#define TFT01_18SP		24	// ST7735S  (Serial)
+#define TFT01_22SP		25	// ILI9341	(Serial 5Pin)
+#define MI0283QT9		26  // ILI9341	(Serial 4Pin)
+
+#define SERIAL_4PIN		4
+#define SERIAL_5PIN		5
+#define LATCHED_16		17
+
+//*********************************
+// COLORS
+//*********************************
+// VGA color palette
+#define VGA_BLACK		0x0000
+#define VGA_WHITE		0xFFFF
+#define VGA_RED			0xF800
+#define VGA_GREEN		0x0400
+#define VGA_BLUE		0x001F
+#define VGA_SILVER		0xC618
+#define VGA_GRAY		0x8410
+#define VGA_MAROON		0x8000
+#define VGA_YELLOW		0xFFE0
+#define VGA_OLIVE		0x8400
+#define VGA_LIME		0x07E0
+#define VGA_AQUA		0x07FF
+#define VGA_TEAL		0x0410
+#define VGA_NAVY		0x0010
+#define VGA_FUCHSIA		0xF81F
+#define VGA_PURPLE		0x8010
+#define VGA_TRANSPARENT	0xFFFFFFFF
+
+#if defined(__AVR__)
+	#include "Arduino.h"
+	#include "hardware/avr/HW_AVR_defines.h"
+#elif defined(__PIC32MX__)
+	#include "WProgram.h"
+	#include "hardware/pic32/HW_PIC32_defines.h"
+#elif defined(__arm__)
+	#include "Arduino.h"
+	#include "hardware/arm/HW_ARM_defines.h"
+#endif
+
+struct _current_font
+{
+	uint8_t* font;
+	uint8_t x_size;
+	uint8_t y_size;
+	uint8_t offset;
+	uint8_t numchars;
+};
+
+class UTFT
+{
+	public:
+		UTFT();
+		UTFT(byte model, int RS, int WR,int CS, int RST, int SER=0);
+		void InitLCD(byte orientation=LANDSCAPE);
+		void clrScr();
+		void drawPixel(int x, int y);
+		void drawLine(int x1, int y1, int x2, int y2);
+		void fillScr(byte r, byte g, byte b);
+		void fillScr(word color);
+		void drawRect(int x1, int y1, int x2, int y2);
+		void drawRoundRect(int x1, int y1, int x2, int y2);
+		void fillRect(int x1, int y1, int x2, int y2);
+		void fillRoundRect(int x1, int y1, int x2, int y2);
+		void drawCircle(int x, int y, int radius);
+		void fillCircle(int x, int y, int radius);
+		void setColor(byte r, byte g, byte b);
+		void setColor(word color);
+		word getColor();
+		void setBackColor(byte r, byte g, byte b);
+		void setBackColor(uint32_t color);
+		word getBackColor();
+		void print(char *st, int x, int y, int deg=0);
+		void print(String st, int x, int y, int deg=0);
+		void printNumI(long num, int x, int y, int length=0, char filler=' ');
+		void printNumF(double num, byte dec, int x, int y, char divider='.', int length=0, char filler=' ');
+		void setFont(uint8_t* font);
+		uint8_t* getFont();
+		uint8_t getFontXsize();
+		uint8_t getFontYsize();
+		void drawBitmap(int x, int y, int sx, int sy, bitmapdatatype data, int scale=1);
+		void drawBitmap(int x, int y, int sx, int sy, bitmapdatatype data, int deg, int rox, int roy);
+		void lcdOff();
+		void lcdOn();
+		void setContrast(char c);
+		int  getDisplayXSize();
+		int	 getDisplayYSize();
+
+/*
+	The functions and variables below should not normally be used.
+	They have been left publicly available for use in add-on libraries
+	that might need access to the lower level functions of UTFT.
+
+	Please note that these functions and variables are not documented
+	and I do not provide support on how to use them.
+*/
+		byte fch, fcl, bch, bcl;
+		byte orient;
+		long disp_x_size, disp_y_size;
+		byte display_model, display_transfer_mode, display_serial_mode;
+		regtype *P_RS, *P_WR, *P_CS, *P_RST, *P_SDA, *P_SCL, *P_ALE;
+		regsize B_RS, B_WR, B_CS, B_RST, B_SDA, B_SCL, B_ALE;
+		_current_font	cfont;
+		boolean _transparent;
+
+		void LCD_Writ_Bus(char VH,char VL, byte mode);
+		void LCD_Write_COM(char VL);
+		void LCD_Write_DATA(char VH,char VL);
+		void LCD_Write_DATA(char VL);
+		void LCD_Write_COM_DATA(char com1,int dat1);
+		void _hw_special_init();
+		void setPixel(word color);
+		void drawHLine(int x, int y, int l);
+		void drawVLine(int x, int y, int l);
+		void printChar(byte c, int x, int y);
+		void setXY(word x1, word y1, word x2, word y2);
+		void clrXY();
+		void rotateChar(byte c, int x, int y, int pos, int deg);
+		void _set_direction_registers(byte mode);
+		void _fast_fill_16(int ch, int cl, long pix);
+		void _fast_fill_8(int ch, long pix);
+		void _convert_float(char *buf, double num, int width, byte prec);
+};
+
+#endif
\ No newline at end of file
diff --git a/hardware/digistump/sam/libraries/UTFT/UTFT.pdf b/hardware/digistump/sam/libraries/UTFT/UTFT.pdf
new file mode 100644
index 0000000..1e42eb9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/UTFT.pdf
@@ -0,0 +1,484 @@
+       UTFT
+
+Arduino and chipKit Universal TFT display library
+
+           Manual
+
+http://electronics.henningkarlsen.com  (C)2013 Henning Karlsen
+PREFACE:
+
+This library is the continuation of my ITDB02_Graph, ITDB02_Graph16 and RGB_GLCD libraries for
+Arduino and chipKit. As the number of supported display modules and controllers started to
+increase I felt it was time to make a single, universal library as it will be much easier to
+maintain in the future.
+
+Basic functionality of this library was origianlly based on the demo-code provided by ITead
+studio (for the ITDB02 modules) and NKC Electronics (for the RGB GLCD module/shield).
+
+This library supports a number of 8bit, 16bit and serial graphic displays, and will work with
+both Arduino and chipKit boards. For a full list of tested display modules and controllers,
+see the document UTFT_Supported_display_modules_&_controllers.pdf.
+
+You can always find the latest version of the library at
+http://electronics.henningkarlsen.com/
+
+If you make any modifications or improvements to the code, I would appreciate that you share
+the code with me so that I might include it in the next release. I can be contacted through
+http://electronics.henningkarlsen.com/contact.php.
+
+For version information, please refer to version.txt.
+
+IMPORTANT:
+
+When using 8bit and 16bit display modules there are some requirements you must adhere to.
+These requirements can be found in the document UTFT_Requirements.pdf.
+There are no special requirements when using serial displays.
+
+Since most people have only one or possibly two different display modules a lot of memory has
+been wasted to keep support for many unneeded controller chips.
+As of v1.1 you now have the option to easily remove this unneeded code from the library. By
+disabling the controllers you don't need you can reduce the memory footprint of the library by
+several Kb. For more information, please refer to memorysaver.h.
+
+If you are using the “AquaLEDSource All in One Super Screw Shield†on a chipKit Max32, please
+read the comment in hardware/pic32/HW_PIC32_defines.h
+
+If you are using the “CTE TFT LCD/SD Shield for Arduino Dueâ€, please read the comment in
+hardware/arm/HW_ARM_defines.h
+
+8 bit display shields designed for use on Arduino Uno (and similarly sized boards) can now be
+used on Arduino Megas. Please read the comment in hardware/avr/HW_AVR_defines.h
+
+The 7†display modules have not been tested on the chipKit boards due to the high current
+requirement for the LED backlight.
+
+This library is licensed under a CC BY-NC-SA 3.0 (Creative Commons Attribution-
+NonCommercial-ShareAlike 3.0 Unported) License.
+
+For more information see: http://creativecommons.org/licenses/by-nc-sa/3.0/
+
+UTFT library                                                                     Page 1
+DEFINED LITERALS:                                        Alignment
+
+For use with print(), printNumI() and printNumF()     LEFT: 0
+                                                    RIGHT: 9999
+                                                   CENTER: 9998
+
+For use with InitLCD()                                       Orientation
+
+                                                    PORTRAIT: 0
+                                                   LANDSCAPE: 1
+
+                                                                                                VGA Colors
+Predefined colors for use with setColor() and setBackColor()
+
+VGA_BLACK               VGA_SILVER                                                                          VGA_GRAY     VGA_WHITE
+VGA_MAROON                                                                                                              VGA_FUCHSIA
+VGA_GREEN               VGA_RED                                                                             VGA_PURPLE  VGA_YELLOW
+
+ VGA_NAVY               VGA_LIME                                                                            VGA_OLIVE     VGA_AQUA
+
+                        VGA_BLUE                                                                            VGA_TEAL
+
+                        VGA_TRANSPARENT (only valid for setBackColor())
+
+For use with UTFT()                                              Display model
+                        Please see UTFT_Supported_display_modules_&_controllers.pdf
+
+INCLUDED FONTS:
+
+                                                   SmallFont
+
+                                    Charactersize: 8x12 pixels
+                        Number of characters: 95
+
+                                                         BigFont
+
+                                    Charactersize: 16x16 pixels
+                        Number of characters: 95
+
+                                                SevenSegNumFont
+
+                                    Charactersize: 32x50 pixels
+                        Number of characters: 10
+
+UTFT library                                                                                                                         Page 2
+FUNCTIONS:
+
+                                                                         UTFT(Model, RS, WR, CS, RST[, ALE]);
+The main class constructor when using 8bit or 16bit display modules.
+
+Parameters:   Model:  See the separate document for the supported display modules
+Usage:        RS:     Pin for Register Select
+              WR:     Pin for Write
+              CS:     Pin for Chip Select
+              RST:    Pin for Reset
+              ALE:     Only used for latched 16bit shields
+                      Pin for Latch signal
+
+              UTFT myGLCD(ITDB32S,19,18,17,16); // Start an instance of the UTFT class
+
+                                                                        UTFT(Model, SDA, SCL, CS, RST[, RS]);
+The main class constructor when using serial display modules.
+
+Parameters:   Model:  See the separate document for the supported display modules
+              SDA:    Pin for Serial Data
+              SCL:    Pin for Serial Clock
+              CS:     Pin for Chip Select
+              RST:    Pin for Reset
+              RS:      Only used for 5pin serial modules
+                      Pin for Register Select
+
+Usage:        UTFT myGLCD(ITDB18SP,11,10,9,12,8); // Start an instance of the UTFT class
+
+                                                   InitLCD([orientation]);
+
+Initialize the LCD and set display orientation.
+
+Parameters:   Orientation: 
+                                     PORTRAIT
+Usage:                               LANDSCAPE (default)
+Notes:
+              myGLCD.initLCD(); // Initialize the display
+              This will reset color to white with black background. Selected font will be reset to none.
+
+                                                                                         getDisplayXSize();
+Get the width of the screen in the current orientation.
+
+Parameters:   None
+Returns:      Width of the screen in the current orientation in pixels
+Usage:        Xsize = myGLCD.getDisplayXSize(); // Get the width
+
+                                                                                         getDisplayYSize();
+Get the height of the screen in the current orientation.
+
+Parameters:   None
+Returns:      Height of the screen in the current orientation in pixels
+Usage:        Ysize = myGLCD.getDisplayYSize(); // Get the height
+
+                                                                                                  lcdOff();
+Turn off the LCD. No commands will be executed until a lcdOn(); is sent.
+
+Parameters:   None
+Usage:        myGLCD.lcdOff(); // Turn off the lcd
+Notes:        This function is currently only supported on PCF8833-based displays
+
+                                                   lcdOn();
+
+Turn on the LCD after issuing a lcdOff()-command.
+
+Parameters:   None
+Usage:        myGLCD.lcdOn(); // Turn on the lcd
+Notes:        This function is currently only supported on PCF8833-based displays
+
+                                                   setContrast(c);
+
+Set the contrast of the display.
+
+Parameters:   c: Contrast-level (0-64)
+Usage:        myGLCD.setContrast(64); // Set contrast to full (default)
+Notes:        This function is currently only supported on PCF8833-based displays
+
+UTFT library                                                                                                   Page 3
+                                                                                                  clrScr();
+Clear the screen. The background-color will be set to black.
+
+Parameters:   None
+Usage:        myGLCD.clrScr(); // Clear the screen
+
+                                                    fillScr(r, g, b);
+
+Fill the screen with a specified color.
+
+Parameters:   r: Red component of an RGB value (0-255)
+Usage:        g: Green component of an RGB value (0-255)
+              b: Blue component of an RGB value (0-255)
+
+              myGLCD.fillScr(255,127,0); // Fill the screen with orange
+
+                                                                                              fillScr(color);
+Fill the screen with a specified pre-calculated RGB565 color.
+
+Parameters:   color: RGB565 color value
+Usage:        myGLCD.fillScr(VGA_RED); // Fill the screen with red
+
+                                                                                           setColor(r, g, b);
+Set the color to use for all draw*, fill* and print commands.
+
+Parameters:   r: Red component of an RGB value (0-255)
+Usage:        g: Green component of an RGB value (0-255)
+              b: Blue component of an RGB value (0-255)
+
+              myGLCD.setColor(0,255,255); // Set the color to cyan
+
+                                                                                           setColor(color);
+Set the specified pre-calculated RGB565 color to use for all draw*, fill* and print commands.
+
+Parameters:   color: RGB565 color value
+Usage:        myGLCD.setColor(VGA_AQUA); // Set the color to aqua
+
+                                                    getColor();
+
+Get the currently selected color.
+
+Parameters:   None
+Returns:      Currently selected color as a RGB565 value (word)
+Usage:        Color = myGLCD.getColor(); // Get the current color
+
+                                                                                       setBackColor(r, g, b);
+Set the background color to use for all print commands.
+
+Parameters:   r: Red component of an RGB value (0-255)
+Usage:        g: Green component of an RGB value (0-255)
+              b: Blue component of an RGB value (0-255)
+
+              myGLCD.setBackColor(255,255,255); // Set the background color to white
+
+                                                                                       setBackColor(color);
+Set the specified pre-calculated RGB565 background color to use for all print commands.
+
+Parameters:   color: RGB565 color value
+Usage:        myGLCD.setBackColor(VGA_LIME); // Set the background color to lime
+
+                                              getBackColor();
+
+Get the currently selected background color.
+
+Parameters:   None
+Returns:      Currently selected background color as a RGB565 value (word)
+Usage:        BackColor = myGLCD.getBackColor(); // Get the current background color
+
+UTFT library                                                                                                   Page 4
+                                               drawPixel(x, y);
+
+Draw a single pixel.
+
+Parameters:   x: x-coordinate of the pixel
+Usage:        y: y-coordinate of the pixel
+
+              myGLCD.drawPixel(119,159); // Draw a single pixel
+
+                                               drawLine(x1, y1, x2, y2);
+
+Draw a line between two points.
+
+Parameters:   x1: x-coordinate of the start-point
+Usage:        y1: y-coordinate of the start-point
+              x2: x-coordinate of the end-point
+              y2: y-coordinate of the end-point
+
+              myGLCD.drawLine(0,0,239,319); // Draw a diagonal line
+
+                                               drawRect(x1, y1, x2, y2);
+
+Draw a rectangle between two points.
+
+Parameters:   x1: x-coordinate of the start-corner
+Usage:        y1: y-coordinate of the start-corner
+              x2: x-coordinate of the end-corner
+              y2: y-coordinate of the end-corner
+
+              myGLCD.drawRect(119,159,239,319); // Draw a rectangle
+
+                                                                              drawRoundRect(x1, y1, x2, y2);
+
+Draw a rectangle with slightly rounded corners between two points. The minimum size is 5 pixels in both directions. If a
+smaller size is requested the rectangle will not be drawn.
+
+Parameters:   x1: x-coordinate of the start-corner
+Usage:        y1: y-coordinate of the start-corner
+              x2: x-coordinate of the end-corner
+              y2: y-coordinate of the end-corner
+
+              myGLCD.drawRoundRect(0,0,119,159); // Draw a rounded rectangle
+
+                                               fillRect(x1, y1, x2, y2);
+
+Draw a filled rectangle between two points.
+
+Parameters:   x1: x-coordinate of the start-corner
+Usage:        y1: y-coordinate of the start-corner
+              x2: x-coordinate of the end-corner
+              y2: y-coordinate of the end-corner
+
+              myGLCD.fillRect(119,0,239,159); // Draw a filled rectangle
+
+                                                                                fillRoundRect(x1, y1, x2, y2);
+
+Draw a filled rectangle with slightly rounded corners between two points. The minimum size is 5 pixels in both directions. If a
+smaller size is requested the rectangle will not be drawn.
+
+Parameters:   x1: x-coordinate of the start-corner
+Usage:        y1: y-coordinate of the start-corner
+              x2: x-coordinate of the end-corner
+              y2: y-coordinate of the end-corner
+
+              myGLCD.fillRoundRect(0,159,119,319); // Draw a filled, rounded rectangle
+
+                                               drawCircle(x, y, radius);
+
+Draw a circle with a specified radius.
+
+Parameters:   x:      x-coordinate of the center of the circle
+Usage:
+              y:      y-coordinate of the center of the circle
+
+              radius: radius of the circle in pixels
+
+              myGLCD.drawCircle(119,159,20); // Draw a circle with a radius of 20 pixels
+
+                                               fillCircle(x, y, radius);
+
+Draw a filled circle with a specified radius.
+
+Parameters:   x:      x-coordinate of the center of the circle
+Usage:
+              y:      y-coordinate of the center of the circle
+
+              radius: radius of the circle in pixels
+
+              myGLCD.fillCircle(119,159,10); // Draw a filled circle with a radius of 10 pixels
+
+UTFT library                                                                                     Page 5
+                                                                                       print(st, x, y[, deg]);
+
+Print a string at the specified coordinates.
+You can use the literals LEFT, CENTER and RIGHT as the x-coordinate to align the string on the screen.
+
+Parameters:   st: the string to print
+              x: x-coordinate of the upper, left corner of the first character
+Usage:        y: y-coordinate of the upper, left corner of the first character
+Notes:        deg: 
+
+                       Degrees to rotate text (0-359). Text will be rotated around the upper left corner.
+
+              myGLCD.print(“Hello, World!â€,CENTER,0); // Print “Hello, World!â€
+
+              CENTER and RIGHT will not calculate the coordinates correctly when rotating text.
+              The string can be either a char array or a String object
+
+                                                                       printNumI(num, x, y[, length[, filler]]);
+
+Print an integer number at the specified coordinates.
+You can use the literals LEFT, CENTER and RIGHT as the x-coordinate to align the string on the screen.
+
+Parameters:   num:  the value to print (-2,147,483,648 to 2,147,483,647) INTEGERS ONLY
+Usage:        x:    x-coordinate of the upper, left corner of the first digit/sign
+              y:    y-coordinate of the upper, left corner of the first digit/sign
+
+              length: 
+                            minimum number of digits/characters (including sign) to display
+
+              filler: 
+
+                    filler character to use to get the minimum length. The character will be inserted in front
+
+                    of the number, but after the sign. Default is ' ' (space).
+
+              myGLCD.printNumI(num,CENTER,0); // Print the value of “numâ€
+
+                                                          printNumF(num, dec, x, y[, divider[, length[, filler]]]);
+
+Print a floating-point number at the specified coordinates.
+You can use the literals LEFT, CENTER and RIGHT as the x-coordinate to align the string on the screen.
+WARNING: Floating point numbers are not exact, and may yield strange results when compared. Use at your own discretion.
+
+Parameters:   num:  the value to print (See note)
+
+Usage:        dec:  digits in the fractional part (1-5) 0 is not supported. Use printNumI() instead.
+Notes:
+              x:    x-coordinate of the upper, left corner of the first digit/sign
+
+              y:    y-coordinate of the upper, left corner of the first digit/sign
+
+              divider: 
+
+                                Single character to use as decimal point. Default is '.'
+              length: 
+
+                                minimum number of digits/characters (including sign) to display
+              filler: 
+
+                    filler character to use to get the minimum length. The character will be inserted in front
+                    of the number, but after the sign. Default is ' ' (space).
+
+              myGLCD.printNumF(num, 3, CENTER,0); // Print the value of “num†with 3 fractional digits
+
+              Supported range depends on the number of fractional digits used.
+              Approx range is +/- 2*(10^(9-dec))
+
+                                                                                        setFont(fontname);
+Select font to use with print(), printNumI() and printNumF().
+
+Parameters:   fontname: Name of the array containing the font you wish to use
+Usage:        myGLCD.setFont(BigFont); // Select the font called BigFont
+Notes:        You must declare the font-array as an external or include it in your sketch.
+
+                                                getFont();
+
+Get the currently selected font.
+
+Parameters:   None
+Returns:      Currently selected font
+Usage:        CurrentFont = myGLCD.getFont(); // Get the current font
+
+                                                getFontXsize();
+
+Get the width of the currently selected font.
+
+Parameters:   None
+Returns:      Width of the currently selected font in pixels
+Usage:        Xsize = myGLCD.getFontXsize (); // Get font width
+
+                                                getFontYsize();
+
+Get the height of the currently selected font.
+
+Parameters:   None
+Returns:      Height of the currently selected font in pixels
+Usage:        Ysize = myGLCD.getFontYsize (); // Get font height
+
+UTFT library                                                                                                      Page 6
+                              drawBitmap (x, y, sx, sy, data[, scale]);
+
+Draw a bitmap on the screen.
+
+Parameters:   x:  x-coordinate of the upper, left corner of the bitmap
+
+Usage:        y:  y-coordinate of the upper, left corner of the bitmap
+Notes:
+              sx: width of the bitmap in pixels
+              sy: height of the bitmap in pixels
+              data: array containing the bitmap-data
+
+              scale: 
+                          Scaling factor. Each pixel in the bitmap will be drawn as x pixels on screen.
+
+              myGLCD.drawBitmap(0, 0, 32, 32, bitmap); // Draw a 32x32 pixel bitmap
+
+              You can use the online-tool “ImageConverter 565†or “ImageConverter565.exe†in the Tools-folder to
+              convert pictures into compatible arrays. The online-tool can be found on my website.
+
+              Requires that you #include  when using an Arduino other than Arduino Due.
+
+                                                                  drawBitmap (x, y, sx, sy, data, deg, rox, roy);
+Draw a bitmap on the screen with rotation.
+
+Parameters:   x: x-coordinate of the upper, left corner of the bitmap
+              y: y-coordinate of the upper, left corner of the bitmap
+Usage:        sx: width of the bitmap in pixels
+Notes:        sy: height of the bitmap in pixels
+              data: array containing the bitmap-data
+              deg: Degrees to rotate bitmap (0-359)
+              rox: x-coordinate of the pixel to use as rotational center relative to bitmaps upper left corner
+              roy: y-coordinate of the pixel to use as rotational center relative to bitmaps upper left corner
+
+              myGLCD.drawBitmap(50, 50, 32, 32, bitmap, 45, 16, 16); // Draw a bitmap rotated 45 degrees around
+              its center
+
+              You can use the online-tool “ImageConverter 565†or “ImageConverter565.exe†in the Tools-folder to
+              convert pictures into compatible arrays. The online-tool can be found on my website.
+              Requires that you #include  when using an Arduino other than Arduino Due.
+
+UTFT library                                                                                                       Page 7
+
diff --git a/hardware/digistump/sam/libraries/UTFT/UTFT_Requirements.pdf b/hardware/digistump/sam/libraries/UTFT/UTFT_Requirements.pdf
new file mode 100644
index 0000000..e7401c3
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/UTFT_Requirements.pdf
@@ -0,0 +1,99 @@
+       UTFT
+
+Arduino and chipKit Universal TFT display library
+
+Requirements
+
+http://electronics.henningkarlsen.com  (C)2013 Henning Karlsen
+The library require the following connections for 8 bit and 16 bit1 display modules (the
+serial display modules does not have any required pins):
+
+Signal  TFT Module pin       Arduino                     chipKit
+
+  DB05            21    2009/Uno/Leonardo Mega/Due2 Uno32/uC323   Max324
+  DB15            22
+  DB25            23    D8            D37           D3            D3
+  DB35            24
+  DB45            25    D9            D36           D5            D5
+  DB55            26
+  DB65            27    D10           D35           D6            D6
+  DB75            28
+  DB8              7    D11           D34           D9            D9
+  DB9              8
+ DB10              9    D12           D33           D10           D10
+ DB11             10
+ DB12             11    D13           D32           D34           D39
+ DB13             12
+ DB14             13    A0 (D14)      D31           D36           D47
+ DB15             14
+   RS              4    A1 (D15)      D30           D37           D77
+   WR              5
+   RD              6    D0            D22           D26           D37
+   CS             15
+ REST             17    D1            D23           D27           D36
+
+                        D2            D24           D28           D35
+
+                        D3            D25           D29           D34
+
+                        D4            D26           D30           D33
+
+                        D5            D27           D31           D32
+
+                        D6            D28           D32           D31
+
+                        D7            D29           D33           D30
+
+                                      Any free pin
+
+                                      Any free pin
+
+                                  Must be pulled high (3.3v)
+
+                                      Any free pin
+
+                                      Any free pin
+
+                                                               Common TFT module pinout
+
+1 16 bit Latched has its own requirements. See the next page.
+2 Pin-out is slightly different when using the CTE TFT LCD/SD Shield for Arduino Due. Please see the
+“hardware/arm/HW_ARM_defines.h†file.
+3 To use a 16 bit display module with a chipKit Uno32/uC32 you MUST place the JP4 jumper in the PWM/RD4 position (jumper over
+the two pins closest to the USB connector)
+4 Pin-out is slightly different when using the AquaLEDSource shield. Please see the “hardware/pic32/HW_PIC32_defines.h†file.
+5 Connect DB0 to DB7 to GND for 8bit display modules
+
+                                                                                                                                                               Page 1
+The 16 bit latched display shield has its own requirements:
+
+Signal  Shield pin                           Arduino         Due      chipKit
+                    2009/Uno/Leonardo/Mega            Unsupported   All types
+  DB0          D0                                     Unsupported  Unsupported
+  DB1          D1                     D0              Unsupported  Unsupported
+  DB2          D2                     D1              Unsupported  Unsupported
+  DB3          D3                     D2              Unsupported  Unsupported
+  DB4          D4                     D3              Unsupported  Unsupported
+  DB5          D5                     D4              Unsupported  Unsupported
+  DB6          D6                     D5              Unsupported  Unsupported
+  DB7          D7                     D6              Unsupported  Unsupported
+   CS          A0                     D7              Unsupported  Unsupported
+   RS          A1            Any free pin             Unsupported  Unsupported
+   WR          A2            Any free pin             Unsupported  Unsupported
+  RST          A3            Any free pin             Unsupported  Unsupported
+  ALE          A5            Any free pin                          Unsupported
+                             Any free pin
+
+                                                                                Page 2
+Arduino pin-mapping:
+
+         Valid for Arduino 2009/Uno/Leonardo  Valid for Arduino Mega/Due1
+chipKit pin-mapping:
+
+Valid for chipKit Uno32/uC32                  Valid for chipKit Max322
+
+1 Pin-out is slightly different when using the CTE TFT LCD/SD Shield for Arduino Due.
+2 Pin-out is slightly different when using the AquaLEDSource shield.
+
+                                                                                       Page 3
+
diff --git a/hardware/digistump/sam/libraries/UTFT/UTFT_Supported_display_modules_&_controllers.pdf b/hardware/digistump/sam/libraries/UTFT/UTFT_Supported_display_modules_&_controllers.pdf
new file mode 100644
index 0000000..a340c76
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/UTFT_Supported_display_modules_&_controllers.pdf
@@ -0,0 +1,180 @@
+          UTFT
+
+                Arduino and chipKit Universal TFT display library
+
+Supported display modules
+              & LCD Controllers
+
+http://electronics.henningkarlsen.com  (C)2013 Henning Karlsen
+These display modules have been tested, and works with the UTFT library. Other modules
+may work as long as they have one of the supported controllers.
+
+Supplier:                      ITead Studio
+
+Website:                       http://imall.iteadstudio.com/
+Module
+                               Model for UTFT()  Controller                         Notes
+ITDB02-1.8SP
+ITDB02-2.2SP                   ITDB18SP          ST7735                             5V only1
+ITDB02-2.2                                                                          Retired, 5V only1
+ITDB02-2.4                     ITDB22SP          HX8340-B(N)
+ITDB02-2.4D                                                                         Retired
+ITDB02-2.4DWOT                 ITDB22            HX8340-B(T)                        Retired
+ITDB02-2.4E                                                                         Retired
+ITDB02-2.4E                    ITDB24            ILI9325C                           8bit mode
+ITDB02-2.5H                                                                         16bit mode
+ITDB02-2.8                     ITDB24D           ILI9325D                           Retired
+ITDB02-3.2
+ITDB02-3.2WC                   ITDB24DWOT        ILI9325D                           Retired
+ITDB02-3.2S                                                                         Retired
+ITDB02-3.2WD                   ITDB24E_8         S6D1121
+ITDB02-4.3
+ITDB02-5.0                     ITDB24E_16        S6D1121
+
+                               ITDB25H           S1D19122
+
+                               ITDB28            ILI9325D
+
+                               ITDB32            HX8347-A
+
+                               ITDB32WC          ILI9327
+
+                               ITDB32S           SSD1289
+
+                               ITDB32WD          HX8352-A
+                               ITDB43            SSD1963
+
+                               ITDB50            SSD1963
+
+Supplier:                      ElecFreaks
+
+Website:                       http://www.elecfreaks.com/store/
+Module
+                               Model for UTFT()  Controller                         Notes
+TFT01-1.8SP
+TFT01-2.2                      TFT01_18SP        ST7735S                            May require external power
+TFT01-2.2SP
+TFT01-2.4                      TFT01_22          S6D0164                            May require external power
+TFT01-2.4
+TFT01-2.8                      TFT01_22SP        ILI9341                            8bit model, Retired
+TFT01-3.2                                                                           16bit model, Retired
+TFT01_3.2W                     TFT01_24_8        ILI9325D
+TFT01_3.2WD                                                                         Retired
+TFT01-5.0                      TFT01_24_16       ILI9325D
+TFT01-7.0
+                               TFT01_28          ILI9325D
+
+                               TFT01_32          SSD1289
+
+                               TFT01_32W         ILI9327
+
+                               TFT01_32WD        HX8352-A
+
+                               TFT01_50          SSD1963
+
+                               TFT01_70          SSD1963
+
+Supplier:                      NKC Electronics
+
+Website:                       http://store.nkcelectronics.com/
+Module
+                               Model for UTFT()  Controller                         Notes
+RGB LCD 65K color module
+                               LPH9135           PCF8833
+
+Supplier:                      Electronics Lee
+
+Website:                       http://stores.ebay.com/electronics-lee
+Module
+                               Model for UTFT()  Controller                         Notes
+3.2†TFT LCD Arduino Shield
+Revision A                     ELEE32_REVA2      SSD1289                            Uses 16bit latched mode3
+                                                                                    Arduino Shield not supported
+3.2†TFT LCD Arduino Shield    ELEE32_REVB       SSD1289                            on chipKit or Arduino Due
+Revision B                                                                          8bit mode4
+                                                                                    Arduino Shield not supported
+                                                                                    on chipKit or Arduino Due
+
+Supplier:                      General Electronics-Tech
+
+Website:                       http://www.geeetech.com/
+Module
+                               Model for UTFT()  Controller                         Notes
+2.2" TFT LCD
+TFT 2.4" With SD Touch Module  GEEE22            HX8340-B(T)                        5V only1
+TFT 2.8" With SD Touch Module                                                       5V only1
+TFT 3.2" With SD Touch Module  GEEE24            ILI9320
+
+                               GEEE28            ILI9320
+
+                               GEEE32            SSD1289
+
+Supplier:                      Coldtears Electronics
+
+Website:                       http://stores.ebay.com/coldtears-electronics-store
+Module
+                               Model for UTFT()  Controller                         Notes
+2.2" TFT LCD Module
+2.8" TFT LCD Module            CTE22             S6D0164                            Basic support only5
+3.2" TFT LCD Module            CTE28             ILI9325D                           Basic support only5
+3.2" (480x320) TFT LCD Module  CTE32             SSD1289                            Basic support only5
+3.2" Wide TFT LCD Module       CTE32HR           ILI9481                            Basic support only5
+5.0" TFT LCD Module            CTE32W            HX8352-A                           Basic support only5
+7.0" TFT LCD Module            CTE50             SSD1963                            Basic support only5
+                               CTE70             SSD1963                            Basic support only5
+
+Supplier:                      Watterott electronic
+
+Website:                       http://www.watterott.com/
+Module
+                               Model for UTFT()  Controller                         Notes
+MI0283QT-9A
+                               MI0283QT9         ILI9341                            Only tested on Arduino Uno
+
+1 May work on 3.3v boards (chipKit and Arduino Due) but this has not been verified
+2 Changed from INFINIT32
+3 Use UTFT myGLCD(ELEE32_REVA,A1,A2,A0,A3,A5); to initialize
+4 Use UTFT myGLCD(ELEE32_REVB,A1,A2,A0,99); to initialize
+5 UTFT does not make use of the on-board Font and Icon Flash chip.
+
+                                                                                              Page 1
+If you are unsure which module you have you can try these model codes for the
+supported controllers instead:
+
+Controller   Model for UTFT()  8bit                                                Supported mode  Serial
+HX8340-B(N)  HX8340B_S           ï                                                         16bit       ï
+HX8340-B(T)  HX8340B_8           ï
+HX8347-A     HX8347A             ï                                                 ï
+HX8352-A     HX8352A             ï                                                 ï
+ILI9320      ILI9320_8
+             ILI9320_16          ï                                                 ï
+ILI9325C     ILI9325C            ï
+ILI9325D     ILI9325D_8          ï                                                 ï
+             ILI9325D_16                                                           ï
+ILI9327      ILI9325D_16ALT6                                                       ï
+ILI9341      ILI9327
+             ILI9341_S4P7                                                                                 ï
+ILI9481      ILI9341_S5P8                                                                                 ï
+PCF8833      ILI9481                                                               ï
+S1D19122     PCF8833                                                                                      ï
+S6D0164      S1D19122                                                              ï
+S6D1121      S6D0164
+             S6D1121_8                                                                  ï
+SSD1289      S6D1121_16                                                                 ï
+             SSD1289
+SSD1963      SSD1289_8                                                             LATCHED
+             SSD1289LATCHED9                                                            ï
+ST7735       SSD1963_480                                                                ï
+ST7735S      SSD1963_800                                                                ï
+             SSD1963_800ALT10                                                                                  ï
+             ST7735                                                                                            ï
+             ST7735S
+
+6 Alternative initialization for some 2.8†display modules
+7 Use this for 4 Pin serial modules
+8 Use this for 5 Pin serial modules
+9 Currently only supported on 5v Arduino board, and not on chipKit or Arduino Due
+10 Alternative initialization for 7†displays
+
+                                                                                                   Page 2
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap/UTFT_Bitmap.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap/UTFT_Bitmap.ino
new file mode 100644
index 0000000..ccfbc2a
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap/UTFT_Bitmap.ino	
@@ -0,0 +1,58 @@
+// UTFT_Bitmap (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the drawBitmap()-function.
+//
+// This demo was made to work on the 320x240 modules.
+// Any other size displays may cause strange behaviour.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(ITDB24E_16,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+extern unsigned short info[0x400];
+extern unsigned short icon[0x400];
+extern unsigned short tux[0x400];
+
+void setup()
+{
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  myGLCD.fillScr(255, 255, 255);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.print(" *** A 10 by 7 grid of a 32x32 icon *** ", CENTER, 228);
+  for (int x=0; x<10; x++)
+    for (int y=0; y<7; y++)
+      myGLCD.drawBitmap (x*32, y*32, 32, 32, info);
+
+  delay(5000);
+  
+  myGLCD.fillScr(255, 255, 255);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.print("   Two different icons in scale 1 to 4  ", CENTER, 228);
+  int x=0;
+  for (int s=0; s<4; s++)
+  {
+    x+=(s*32);
+    myGLCD.drawBitmap (x, 0, 32, 32, tux, s+1);
+  }
+  x=0;
+  for (int s=4; s>0; s--)
+  {
+    myGLCD.drawBitmap (x, 224-(s*32), 32, 32, icon, s);
+    x+=(s*32);
+  }
+
+  delay(5000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap/icon.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap/icon.c
new file mode 100644
index 0000000..9cb97a1
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap/icon.c	
@@ -0,0 +1,71 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: taskmgr.png
+// Time generated: 11.10.2010 22:51:23
+// Size          : 2 048 Bytes
+
+const unsigned short icon[0x400] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0xCE79, 0xBDD7, 0xAD75,   // 0x0010 (16)
+0xAD55, 0xAD75, 0xBDF7, 0xD6BA, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xC638, 0x9492, 0x8C51, 0x9492, 0xA514, 0xA534,   // 0x0030 (48)
+0xA534, 0xA534, 0x9CF3, 0x8C71, 0x8430, 0x9CD3, 0xD69A, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCE59, 0x8410, 0x9492, 0xB5B6, 0xC618, 0xBDD7, 0xAD75, 0xA514,   // 0x0050 (80)
+0xA514, 0xA4F4, 0xAD55, 0xB5B6, 0xBDD7, 0xAD55, 0x8430, 0x8C71, 0xDEFB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x9CD3, 0x8430, 0xBDF7, 0xC618, 0xAD75, 0x94F2, 0x8CF1, 0x84B0, 0x8CD1,   // 0x0070 (112)
+0x9612, 0x8CB1, 0x7C6F, 0x7C8F, 0x8490, 0xA533, 0xBDF7, 0xB596, 0x7BEF, 0xB596, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x8430, 0x9CF3, 0xCE39, 0xA514, 0x94B2, 0x9E93, 0x94F2, 0x8CD1, 0x8CB1, 0x9D12,   // 0x0090 (144)
+0x9F74, 0x9D52, 0x8450, 0x7C8F, 0x73AE, 0x740E, 0x73CE, 0x9CD3, 0xC638, 0x8C51, 0x9CD3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x8430, 0xA534, 0xBDF7, 0x8CB1, 0x8C31, 0x9DB3, 0xA735, 0x9D13, 0x8CB1, 0x8C71, 0x9D13,   // 0x00B0 (176)
+0xB756, 0xA5D4, 0x8C71, 0x8490, 0x8390, 0x7C70, 0x73EE, 0x6B4D, 0x8450, 0xBDF7, 0x8C71, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x94B2, 0x9CF3, 0xBDD7, 0x8490, 0x8CF1, 0x9D72, 0xA694, 0xAE94, 0x9DD3, 0xA593, 0xA553, 0x9592,   // 0x00D0 (208)
+0x9672, 0x75CE, 0x5BAA, 0x64EB, 0x5D8C, 0x5BCA, 0x4B69, 0x634C, 0x748D, 0x7C4F, 0xBE18, 0x8430, 0xB5B6, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00E0 (224)
+0xFFFF, 0xFFFF, 0xFFFF, 0xC618, 0x8410, 0xBDF7, 0x8410, 0x83F0, 0x94F2, 0x9613, 0x9D13, 0xAE55, 0x9D12, 0x750E, 0x55CB, 0x4BC8,   // 0x00F0 (240)
+0x4447, 0x3BC6, 0x4B67, 0x44E8, 0x3CE8, 0x3325, 0x20E2, 0x2B45, 0x43E7, 0x3946, 0x732D, 0xC5F8, 0x7BCF, 0xE71C, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xF7BE, 0x7BEF, 0xBDB6, 0x9533, 0x8D71, 0x9552, 0x9E73, 0x9DD3, 0x94B2, 0x6D6D, 0x4BA8, 0x44A8, 0x55EA, 0x5D2A,   // 0x0110 (272)
+0x43E7, 0x4327, 0x46CA, 0x4B87, 0x42C6, 0x4E0A, 0x4D09, 0x4468, 0x4548, 0x3386, 0x2B25, 0x7C6F, 0xAD35, 0x9492, 0xFFFF, 0xFFFF,   // 0x0120 (288)
+0xFFDF, 0xFFFF, 0xBDD7, 0x8C71, 0xAD75, 0x8CF0, 0x8D71, 0x8D51, 0x9DF3, 0x740E, 0x21C4, 0x33E5, 0x558A, 0x554A, 0x650A, 0x566B,   // 0x0130 (304)
+0x43E7, 0x21C3, 0x3345, 0x2283, 0x1962, 0x3C87, 0x3386, 0x2163, 0x3345, 0x3346, 0x33A6, 0x32C6, 0x9CB3, 0x7BEF, 0xDEDB, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0x8430, 0xAD75, 0x8C31, 0x7C0F, 0x7BCF, 0x83F0, 0x636B, 0x0000, 0x0000, 0x4387, 0x462A, 0x4B27, 0x4B88, 0x4E8B,   // 0x0150 (336)
+0x42E6, 0x0000, 0x0020, 0x0100, 0x0000, 0x1121, 0x0040, 0x0000, 0x0941, 0x0000, 0x0020, 0x00E0, 0x5AAB, 0x94B2, 0x9CD3, 0xFFFF,   // 0x0160 (352)
+0xFFFF, 0xE71C, 0x8410, 0xB596, 0x7BEF, 0x7C6F, 0x84B0, 0x5B6B, 0x09E1, 0x0901, 0x1161, 0x3C06, 0x3D89, 0x32C5, 0x43E7, 0x470B,   // 0x0170 (368)
+0x4BC7, 0x0961, 0x11E2, 0x1282, 0x0961, 0x1262, 0x09E2, 0x0961, 0x12A2, 0x0961, 0x09C2, 0x0A01, 0x29E5, 0xA514, 0x7BEF, 0xFFDF,   // 0x0180 (384)
+0xFFFF, 0xBDD7, 0x9472, 0xA514, 0x6B4D, 0x7C6F, 0x634C, 0x0040, 0x0981, 0x0060, 0x00E0, 0x11E2, 0x10A1, 0x09C1, 0x19E3, 0x2B25,   // 0x0190 (400)
+0x22A3, 0x0060, 0x0120, 0x09E1, 0x0060, 0x09E1, 0x0120, 0x0060, 0x0A21, 0x0060, 0x0100, 0x01A0, 0x0040, 0x9CD3, 0x7BEF, 0xDEDB,   // 0x01A0 (416)
+0xFFFF, 0xA514, 0x9CF3, 0xB596, 0x73AE, 0x7C0F, 0x2945, 0x10A2, 0x2184, 0x18C3, 0x1923, 0x2184, 0x18C3, 0x21A4, 0x2964, 0x2905,   // 0x01B0 (432)
+0x2A25, 0x2104, 0x2965, 0x2A05, 0x2104, 0x2A05, 0x2985, 0x2104, 0x2A25, 0x2104, 0x2164, 0x29C4, 0x3166, 0xB5B6, 0x8410, 0xC618,   // 0x01C0 (448)
+0xFFFF, 0x9492, 0xA514, 0xDEDB, 0xC618, 0xA514, 0x8C51, 0x94B2, 0x9CB3, 0x9CF3, 0xA514, 0xA534, 0xAD75, 0xAD75, 0xB596, 0xB5D6,   // 0x01D0 (464)
+0xBDB7, 0xBDF7, 0xBDF7, 0xBDF7, 0xC618, 0xC5F8, 0xC5F8, 0xBDF7, 0xBDD7, 0xBDD7, 0xB5B6, 0xB596, 0xC638, 0xDEFB, 0x8430, 0xB596,   // 0x01E0 (480)
+0xFFFF, 0x8C51, 0x9CF3, 0xE73C, 0xDEFB, 0xD69A, 0xD6BA, 0xD6BA, 0xDEDB, 0xDEDB, 0xDEFB, 0xDF1B, 0xE71C, 0xE73C, 0xE73C, 0xE73C,   // 0x01F0 (496)
+0xEF5D, 0xEF5D, 0xEF5D, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xDEFB, 0xE71C, 0x8C51, 0xAD75,   // 0x0200 (512)
+0xFFFF, 0x8C71, 0x9CD3, 0xDEFB, 0xAD75, 0x9492, 0x9CD3, 0xA4F3, 0xA514, 0xAD55, 0xAD75, 0xB596, 0xBDB6, 0xBDD7, 0xC5F7, 0xC618,   // 0x0210 (528)
+0xC638, 0xCE59, 0xCE59, 0xCE79, 0xD679, 0xD679, 0xCE79, 0xCE59, 0xCE59, 0xC638, 0xC618, 0xBDF7, 0xCE79, 0xE71C, 0x8C51, 0xB596,   // 0x0220 (544)
+0xFFFF, 0x9CD3, 0x9492, 0xAD55, 0x2965, 0x2104, 0x2124, 0x2145, 0x1945, 0x2165, 0x2165, 0x2186, 0x2186, 0x29A6, 0x29A6, 0x31C7,   // 0x0230 (560)
+0x39C7, 0x31E7, 0x31E7, 0x31E7, 0x3208, 0x3208, 0x31E7, 0x31E7, 0x29E7, 0x31C7, 0x39C7, 0x31A6, 0x4A49, 0xBDF7, 0x8C51, 0xBDF7,   // 0x0240 (576)
+0xFFFF, 0xB5B6, 0x8430, 0x7BEF, 0x0000, 0x0000, 0x0000, 0x2000, 0x3000, 0x3000, 0x3000, 0x3000, 0x3000, 0x3000, 0x3800, 0x2000,   // 0x0250 (592)
+0x0000, 0x3000, 0x3800, 0x3000, 0x3800, 0x3800, 0x3800, 0x3000, 0x3800, 0x0800, 0x0000, 0x0000, 0x0000, 0xA514, 0x8430, 0xD6BA,   // 0x0260 (608)
+0xFFFF, 0xDEDB, 0x7BCF, 0x8430, 0x0020, 0x0000, 0x0000, 0x8000, 0xC800, 0xC000, 0xC800, 0xC820, 0xC820, 0xC820, 0xD020, 0x9800,   // 0x0270 (624)
+0x0000, 0xB820, 0xD020, 0xD020, 0xD020, 0xD020, 0xD020, 0xC820, 0xD020, 0x4800, 0x0000, 0x0000, 0x2144, 0xAD75, 0x8410, 0xF7BE,   // 0x0280 (640)
+0xFFFF, 0xFFFF, 0x7BEF, 0x8C71, 0x2945, 0x0000, 0x0000, 0x6800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xB000, 0x8000,   // 0x0290 (656)
+0x0000, 0x9800, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0x4000, 0x0000, 0x0000, 0x632C, 0xA534, 0x94B2, 0xFFFF,   // 0x02A0 (672)
+0xFFDF, 0xFFFF, 0xAD75, 0x73AE, 0x632C, 0x0000, 0x0000, 0x6920, 0xA9E0, 0xA1C0, 0xA9E0, 0xA9E0, 0xA9E0, 0xA9E0, 0xA9E0, 0x7960,   // 0x02B0 (688)
+0x0000, 0x99C0, 0xB200, 0xA9E0, 0xB200, 0xB200, 0xB1E0, 0xA9E0, 0xB200, 0x40C0, 0x0000, 0x1082, 0xAD75, 0x8410, 0xD69A, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xF79E, 0x630C, 0x8C51, 0x2965, 0x0000, 0x7400, 0xB620, 0xAE00, 0xB620, 0xB640, 0xB640, 0xB620, 0xB660, 0x84A0,   // 0x02D0 (720)
+0x0000, 0xA5A0, 0xBE60, 0xB660, 0xBE60, 0xBE60, 0xB660, 0xB640, 0xBE80, 0x4260, 0x0000, 0x6B6D, 0xAD75, 0x8430, 0xFFFF, 0xFFFF,   // 0x02E0 (736)
+0xFFFF, 0xFFDF, 0xFFFF, 0xB5B6, 0x632C, 0x8410, 0x0021, 0x7360, 0xBD40, 0xB520, 0xBD40, 0xBD60, 0xBD60, 0xBD40, 0xC580, 0x8C00,   // 0x02F0 (752)
+0x0000, 0xACE0, 0xC580, 0xC580, 0xC580, 0xC580, 0xC580, 0xBD60, 0xC5A0, 0x39C0, 0x2126, 0xBDF7, 0x73AE, 0xD6BA, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x7BEF, 0x7BEF, 0x630D, 0x4AE1, 0x6D21, 0x6D01, 0x6D21, 0x6D41, 0x6D41, 0x6D41, 0x6D61, 0x53E1,   // 0x0310 (784)
+0x0000, 0x64C1, 0x7562, 0x6D62, 0x6D62, 0x6D62, 0x6D62, 0x6D42, 0x6D41, 0x4263, 0xA515, 0x8C51, 0xA534, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0320 (800)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0x6B4D, 0x8410, 0x636E, 0x04A6, 0x05E5, 0x05C5, 0x0585, 0x0585, 0x0586, 0x05A6, 0x0424,   // 0x0330 (816)
+0x0000, 0x0505, 0x05C6, 0x05A6, 0x05A6, 0x05C7, 0x0606, 0x0606, 0x1CE9, 0xA535, 0x9492, 0x8C71, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x6B4D, 0x83EF, 0x9411, 0x3A47, 0x0403, 0x0584, 0x05A4, 0x0585, 0x0585, 0x0404,   // 0x0350 (848)
+0x0000, 0x04E5, 0x05A5, 0x05A5, 0x05C5, 0x0584, 0x1405, 0x634B, 0xBD76, 0x8C51, 0x8C51, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0360 (864)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x8410, 0x6B6D, 0x9CB3, 0x7C6F, 0x3CA9, 0x0BE4, 0x0443, 0x0504, 0x03C2,   // 0x0370 (880)
+0x0000, 0x0483, 0x0504, 0x0444, 0x1426, 0x552D, 0xA554, 0xB576, 0x73CE, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB5B6, 0x6B4D, 0x7BAF, 0x9432, 0x8BD1, 0x6BCE, 0x4C6B, 0x3C09,   // 0x0390 (912)
+0x3186, 0x3C8A, 0x5C8C, 0x8430, 0xA493, 0xACD4, 0x8410, 0x7BEF, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xAD75, 0x7BEF, 0x73AE, 0x83F0, 0x8C11, 0x9431,   // 0x03B0 (944)
+0x9492, 0x9452, 0x9432, 0x8430, 0x7BEF, 0x8450, 0xBDF7, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEFB, 0xBDD7, 0xA534, 0x94D3,   // 0x03D0 (976)
+0x94B2, 0x9CF3, 0xA554, 0xC618, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap/info.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap/info.c
new file mode 100644
index 0000000..312bee1
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap/info.c	
@@ -0,0 +1,71 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: info.png
+// Time generated: 11.10.2010 22:27:55
+// Size          : 2 048 Bytes
+
+const unsigned short info[0x400] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0010 (16)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF9F, 0xC69D, 0x95BB, 0x7D1A, 0x6CB9,   // 0x0030 (48)
+0x6499, 0x74F9, 0x8D7A, 0xB63C, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAE1C, 0x4C18, 0x2B56, 0x3397, 0x4C38, 0x64B9, 0x751A,   // 0x0050 (80)
+0x7D3A, 0x6CD9, 0x5458, 0x3BD7, 0x2B56, 0x3BB7, 0x855A, 0xE77E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xA5FB, 0x2B56, 0x2B77, 0x751A, 0xB67C, 0xD73E, 0xE75E, 0xE77E, 0xE77E,   // 0x0070 (112)
+0xE77E, 0xE77E, 0xE75E, 0xDF3E, 0xC6DD, 0x8D9B, 0x43D7, 0x1B16, 0x74D9, 0xF7BF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF9F, 0x4C18, 0x1AF6, 0x855A, 0xCEFE, 0xD71E, 0xCEFD, 0xC6DD, 0xC6BD, 0xC6BD, 0xBEBD,   // 0x0090 (144)
+0xC6BD, 0xBEBD, 0xC6BD, 0xC6DD, 0xC6DD, 0xD71E, 0xD71E, 0xA61C, 0x33B7, 0x2316, 0xBE7C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDF3E, 0x2336, 0x3BD7, 0xBE9D, 0xC6DD, 0xBE9D, 0xBE9D, 0xBE9D, 0xBEBD, 0xBE9D, 0xCEFD, 0xEF9F,   // 0x00B0 (176)
+0xEF9F, 0xD73E, 0xBE9D, 0xBEBD, 0xBE9D, 0xBE9D, 0xB69D, 0xC6BD, 0xCEDD, 0x6CFA, 0x0295, 0x9DBB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xE75E, 0x1AF6, 0x4C58, 0xBEBD, 0xB67D, 0xAE5C, 0xB67D, 0xB67D, 0xB69D, 0xB67D, 0xBEBD, 0xF7DF, 0xFFFF,   // 0x00D0 (208)
+0xFFFF, 0xFFFF, 0xCF1E, 0xB67D, 0xB67D, 0xB67D, 0xB67D, 0xAE5C, 0xAE5C, 0xC6BD, 0x857B, 0x0295, 0xA5DB, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00E0 (224)
+0xFFFF, 0xFFFF, 0xFFDF, 0x3BB7, 0x33D8, 0xB67D, 0xA63C, 0xA63C, 0xAE5C, 0xAE5D, 0xAE5D, 0xAE7D, 0xA65D, 0xC6DD, 0xFFFF, 0xFFFF,   // 0x00F0 (240)
+0xFFDF, 0xFFFF, 0xDF5E, 0xA65D, 0xAE7D, 0xAE5D, 0xAE5D, 0xAE5C, 0xA63C, 0xA61C, 0xB67D, 0x753A, 0x0295, 0xCEBC, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xF7DF, 0xFFFF, 0x957A, 0x12F6, 0x9E1C, 0x9E1C, 0x9E1C, 0x9E1C, 0xA63C, 0xA63C, 0xA63D, 0xA63D, 0xA65D, 0x9DFC, 0xDF3E, 0xFFFF,   // 0x0110 (272)
+0xFFFF, 0xFFDF, 0xA61C, 0xA65D, 0xA65D, 0xA63D, 0xA63C, 0xA63C, 0x9E1C, 0x9E1C, 0x9DFC, 0xAE3C, 0x3C18, 0x3396, 0xFFDF, 0xFFFF,   // 0x0120 (288)
+0xFFFF, 0xF79F, 0x2336, 0x64DA, 0x9DFC, 0x95DC, 0x95FC, 0x95FC, 0x9E1C, 0x9E1C, 0x9E3D, 0x9E3D, 0x9E3D, 0x9E3D, 0x7D3B, 0xA63C,   // 0x0130 (304)
+0xB6BD, 0x8DBB, 0x8DFC, 0xA65D, 0x9E3D, 0x9E3D, 0x9E1C, 0x9E1C, 0x95FC, 0x95FC, 0x95DC, 0x95DC, 0x8DBB, 0x0AF6, 0xA5DA, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xA5FB, 0x1337, 0x8DBB, 0x8DBB, 0x8DBC, 0x8DDC, 0x95FC, 0x95FC, 0x961C, 0x961D, 0x963D, 0x9E3D, 0x963D, 0xA67D, 0xB6BD,   // 0x0150 (336)
+0xB6BD, 0xAE7D, 0x9E3D, 0x9E3D, 0x961D, 0x961D, 0x961C, 0x95FC, 0x95FC, 0x8DDC, 0x8DDC, 0x859B, 0x95DC, 0x3C18, 0x4BD7, 0xFFFF,   // 0x0160 (352)
+0xFFFF, 0x6499, 0x33F8, 0x8DBB, 0x859B, 0x85BC, 0x85BC, 0x8DDC, 0x8DFC, 0x8DFD, 0x8E1D, 0x961D, 0x961D, 0x9E3D, 0xF7BF, 0xFFFF,   // 0x0170 (368)
+0xFFFF, 0xFFFF, 0xA67D, 0x8E1D, 0x961D, 0x8E1D, 0x8DFD, 0x8DFC, 0x8DDC, 0x85BC, 0x85BC, 0x859B, 0x859B, 0x5CDA, 0x2336, 0xE71C,   // 0x0180 (384)
+0xFFFF, 0x43F8, 0x4C79, 0x859B, 0x7D7B, 0x7D9C, 0x85BC, 0x85DC, 0x85DC, 0x8DFD, 0x8DFD, 0x8E1D, 0x8E1D, 0xA67E, 0xFFFF, 0xFFFF,   // 0x0190 (400)
+0xFFFF, 0xFFFF, 0xBEDE, 0x85FD, 0x8E1D, 0x8DFD, 0x8DFD, 0x85DC, 0x85DC, 0x85BC, 0x7D9C, 0x7D7B, 0x7D7B, 0x753B, 0x1B36, 0xBE5A,   // 0x01A0 (416)
+0xFFBE, 0x3BF8, 0x3419, 0x6D1B, 0x757B, 0x7D9C, 0x7D9C, 0x7DBC, 0x7DDD, 0x85FD, 0x85FD, 0x861D, 0x861D, 0x9E7E, 0xFFFF, 0xFFFF,   // 0x01B0 (432)
+0xFFFF, 0xFFFF, 0xB6DE, 0x85FD, 0x8E1D, 0x85FD, 0x85FD, 0x7DDD, 0x7DBC, 0x7D9C, 0x7D9C, 0x757B, 0x6D3B, 0x4C9A, 0x1337, 0xADD9,   // 0x01C0 (448)
+0xFFBE, 0x4418, 0x23B9, 0x3439, 0x4CBA, 0x653B, 0x759C, 0x7DBD, 0x7DDD, 0x7DFD, 0x861D, 0x861E, 0x861E, 0x9E7E, 0xFFFF, 0xFFFF,   // 0x01D0 (464)
+0xFFFF, 0xFFFF, 0xB6DE, 0x7E1E, 0x861E, 0x85FD, 0x7DFD, 0x7DDD, 0x7DBD, 0x759C, 0x653B, 0x4CDB, 0x3439, 0x2BF9, 0x1337, 0xA5B9,   // 0x01E0 (480)
+0xFF9E, 0x4C39, 0x2BF9, 0x345A, 0x3C7A, 0x3C9B, 0x4CFC, 0x5D5C, 0x659D, 0x75DD, 0x7DFE, 0x861E, 0x7E3E, 0x969F, 0xFFFF, 0xFFFF,   // 0x01F0 (496)
+0xFFFF, 0xFFFF, 0xB6FF, 0x7E1E, 0x863E, 0x7DFE, 0x75DD, 0x6D9D, 0x5D5C, 0x4CFC, 0x3C9B, 0x347A, 0x345A, 0x343A, 0x1B78, 0xA5B9,   // 0x0200 (512)
+0xF79E, 0x4418, 0x2C3A, 0x3C7A, 0x449B, 0x44DB, 0x4CFC, 0x4D3C, 0x555D, 0x5D7D, 0x65BE, 0x6DFE, 0x6DFF, 0x867F, 0xFFFF, 0xFFFF,   // 0x0210 (528)
+0xFFFF, 0xFFFF, 0xA6DF, 0x65FF, 0x6DFE, 0x65BE, 0x5D9E, 0x555D, 0x4D3C, 0x4CFC, 0x44DB, 0x44BB, 0x3C7A, 0x345A, 0x1B78, 0xA599,   // 0x0220 (544)
+0xFFDE, 0x43D8, 0x345A, 0x3C9A, 0x44DB, 0x4CFC, 0x4D3C, 0x555D, 0x5D9D, 0x5DBE, 0x65DE, 0x6DFF, 0x661F, 0x867F, 0xFFFF, 0xFFFF,   // 0x0230 (560)
+0xFFFF, 0xFFFF, 0xA6DF, 0x65FF, 0x6DFF, 0x65DE, 0x5DBE, 0x5D9D, 0x555D, 0x4D3C, 0x4CFC, 0x44DB, 0x3C7A, 0x3C9B, 0x1B57, 0xADB9,   // 0x0240 (576)
+0xFFFF, 0x4BD7, 0x2C1A, 0x44DB, 0x44DB, 0x4D1C, 0x555D, 0x5D7D, 0x5DBE, 0x65DE, 0x6E1F, 0x6E3F, 0x765F, 0x96BF, 0xFFFF, 0xFFFF,   // 0x0250 (592)
+0xFFFF, 0xFFFF, 0xAEFF, 0x6E3F, 0x763F, 0x6E1F, 0x65DE, 0x5DBE, 0x5D7D, 0x555D, 0x4D1C, 0x44DC, 0x3C9B, 0x44DC, 0x1AD5, 0xC639,   // 0x0260 (608)
+0xFFFF, 0x84D8, 0x1317, 0x5D7D, 0x44DB, 0x553C, 0x557D, 0x5D9E, 0x65DE, 0x65FF, 0x6E3F, 0x7E5F, 0x7E7F, 0x9EDF, 0xFFFF, 0xFFFF,   // 0x0270 (624)
+0xFFFF, 0xFFFF, 0xB73F, 0x7E7F, 0x7E5F, 0x6E3F, 0x65FF, 0x65DE, 0x5D9E, 0x557D, 0x553C, 0x44DC, 0x4D1C, 0x345B, 0x22B4, 0xE71B,   // 0x0280 (640)
+0xFFFF, 0xD6BC, 0x0234, 0x4CFC, 0x5D7D, 0x4D3C, 0x5D9D, 0x5DBE, 0x65FF, 0x6E3F, 0x765F, 0x867F, 0x8EBF, 0xA6DF, 0xFFFF, 0xFFFF,   // 0x0290 (656)
+0xFFFF, 0xFFFF, 0xB71F, 0x8EBF, 0x869F, 0x765F, 0x6E3F, 0x65FF, 0x5DBE, 0x5D7D, 0x553D, 0x4D1C, 0x65BE, 0x0AB7, 0x6C15, 0xFFBE,   // 0x02A0 (672)
+0xFFFF, 0xFFFF, 0x53B6, 0x0296, 0x75FE, 0x5D9D, 0x557D, 0x65DE, 0x6E1F, 0x763F, 0x7E7F, 0x8EBF, 0x9EFF, 0x96BE, 0xAE3C, 0xE77E,   // 0x02B0 (688)
+0xEF9E, 0xC69D, 0x967E, 0x9EFF, 0x8EBF, 0x7E7F, 0x763F, 0x6E1F, 0x65DE, 0x5D9E, 0x555D, 0x761E, 0x341A, 0x1294, 0xBE18, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xCE9B, 0x0A13, 0x2378, 0x7E5F, 0x6E1E, 0x5DBE, 0x6E1F, 0x7E5F, 0x869F, 0x96DF, 0x9EFF, 0xAF5F, 0x9E9E, 0x8DFC,   // 0x02D0 (720)
+0x8E1C, 0x967D, 0xAF3F, 0xA6FF, 0x96DF, 0x869F, 0x7E5F, 0x6E1F, 0x5DBE, 0x65DE, 0x7E5F, 0x4CBB, 0x0AB5, 0x7454, 0xEF5C, 0xFFFF,   // 0x02E0 (736)
+0xFFFF, 0xFFFF, 0xFFFF, 0x8D17, 0x01D3, 0x23B9, 0x7E3E, 0x8E9F, 0x763F, 0x765F, 0x8E9F, 0x9EDF, 0xA71F, 0xB75F, 0xC7BF, 0xCFDF,   // 0x02F0 (752)
+0xCFDF, 0xC7BF, 0xB75F, 0xA71F, 0x9EDF, 0x8E9F, 0x765F, 0x6E1F, 0x867F, 0x8E7F, 0x4CBB, 0x1317, 0x4BB4, 0xD679, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFBD, 0x7476, 0x0214, 0x1B78, 0x659D, 0x9EDF, 0x9EFF, 0x96DF, 0x9EFF, 0xAF1F, 0xB75F, 0xC79F, 0xD7DF,   // 0x0310 (784)
+0xD7DF, 0xC79F, 0xB75F, 0xAF1F, 0x9EDF, 0x96DF, 0x96DF, 0x9EFF, 0x7E1E, 0x3C5A, 0x1B77, 0x43B5, 0xBDD6, 0xF7BE, 0xFFFF, 0xFFFF,   // 0x0320 (800)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF77D, 0x7CB6, 0x12B4, 0x1337, 0x449B, 0x7DFD, 0xA6FF, 0xB75F, 0xBF7F, 0xC79F, 0xCFBF, 0xD7FF,   // 0x0330 (816)
+0xD7FF, 0xCFBF, 0xC79F, 0xBF7F, 0xB77F, 0xAF1F, 0x8E5E, 0x551B, 0x3419, 0x2BD7, 0x5415, 0xB5B6, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79D, 0xA577, 0x3B75, 0x1B36, 0x2BD9, 0x4CBB, 0x759D, 0x965E, 0xAEDF, 0xBF3F, 0xC77F,   // 0x0350 (848)
+0xC77F, 0xBF3F, 0xB6FF, 0x9E7F, 0x7DDD, 0x5D1C, 0x447A, 0x3C59, 0x4437, 0x7474, 0xC617, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0360 (864)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDE, 0xD699, 0x84D5, 0x43D5, 0x33B7, 0x3418, 0x4C7A, 0x5CFC, 0x753D, 0x857E,   // 0x0370 (880)
+0x859E, 0x755D, 0x653C, 0x5CFB, 0x4CDA, 0x4CB9, 0x5497, 0x6C95, 0xA555, 0xDEDA, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79D, 0xCE79, 0x9D56, 0x7495, 0x5C56, 0x4C77, 0x4C97, 0x4CB8,   // 0x0390 (912)
+0x54D8, 0x5CD8, 0x5CF8, 0x64D7, 0x74D6, 0x8CF5, 0xAD96, 0xD699, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFBE, 0xEF1B, 0xD679, 0xBDF7, 0xAD96, 0xA576,   // 0x03B0 (944)
+0xA576, 0xAD76, 0xB5B6, 0xC5F7, 0xD679, 0xEF3C, 0xFFDE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFBE,   // 0x03D0 (976)
+0xF7BE, 0xF7BE, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap/tux.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap/tux.c
new file mode 100644
index 0000000..69a04a1
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap/tux.c	
@@ -0,0 +1,71 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: tux.png
+// Time generated: 11.10.2010 22:51:32
+// Size          : 2 048 Bytes
+
+const unsigned short tux[0x400] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73C, 0x9CD3, 0x9CF3, 0xA514,   // 0x0010 (16)
+0x9CF3, 0x8C51, 0xAD75, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x5AEB, 0x7BEF, 0x9CD3, 0x94B2,   // 0x0030 (48)
+0x94B2, 0x94B2, 0x4228, 0x7BEF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x9CF3, 0x18E3, 0x630C, 0x4A49, 0x4A69,   // 0x0050 (80)
+0x4A69, 0x528A, 0x4A49, 0x0000, 0xC638, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x6B6D, 0x0000, 0x0020, 0x10A2, 0x1082,   // 0x0070 (112)
+0x0841, 0x0841, 0x0841, 0x0000, 0x630C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x528A, 0x4228, 0x8410, 0x0000, 0x0861,   // 0x0090 (144)
+0xAD55, 0xBDD7, 0x10A2, 0x0000, 0x2945, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x5ACB, 0x8C71, 0xE75D, 0x2126, 0x528B,   // 0x00B0 (176)
+0xE75D, 0xDEDB, 0x7BCF, 0x0000, 0x18E3, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x6B6D, 0x4A4A, 0x6B2A, 0x8BE7, 0xA48A,   // 0x00D0 (208)
+0x6B09, 0x4A8A, 0x8431, 0x0000, 0x2104, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00E0 (224)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x6B6E, 0x5204, 0xDE6A, 0xFFF7, 0xFFF8,   // 0x00F0 (240)
+0xD5AC, 0xBCAA, 0x5A66, 0x0000, 0x1082, 0xDEFB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8C10, 0xC540, 0xFFED, 0xFF2C, 0xFEEC,   // 0x0110 (272)
+0xFECC, 0xFE66, 0x8260, 0x0000, 0x0000, 0xB596, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0120 (288)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B3, 0x9C25, 0xFF20, 0xFE40, 0xFDA0,   // 0x0130 (304)
+0xFCC0, 0xF524, 0x836A, 0x0000, 0x0000, 0x630C, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x630C, 0x94B4, 0xFF13, 0xFD83, 0xF523,   // 0x0150 (336)
+0xE5CF, 0xF79E, 0xE71D, 0x0861, 0x0000, 0x0861, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0160 (352)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xCE59, 0x0841, 0xD69A, 0xFFFF, 0xFF7D, 0xF77D,   // 0x0170 (368)
+0xFFFF, 0xFFFF, 0xFFFF, 0x73AE, 0x0000, 0x0000, 0x4A69, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0180 (384)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0x10A2, 0x8410, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF,   // 0x0190 (400)
+0xFFFF, 0xFFDF, 0xFFFF, 0xCE59, 0x0000, 0x0000, 0x0000, 0x9492, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01A0 (416)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x52AA, 0x0020, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01B0 (432)
+0xFFDF, 0xFFDF, 0xF7BE, 0xFFDF, 0x3186, 0x0000, 0x0020, 0x0841, 0xCE79, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01C0 (448)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xC638, 0x0000, 0x52AA, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFDF,   // 0x01D0 (464)
+0xFFDF, 0xF7BE, 0xF79E, 0xFFFF, 0x9CF3, 0x0000, 0x0841, 0x0000, 0x39E7, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01E0 (480)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x5ACB, 0x0000, 0xBDF7, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFDF, 0xFFDF,   // 0x01F0 (496)
+0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0x3186, 0x0000, 0x0861, 0x0000, 0xAD55, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0200 (512)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73C, 0x0861, 0x4A49, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF,   // 0x0210 (528)
+0xF7BE, 0xF79E, 0xEF7D, 0xEF5D, 0xFFDF, 0x8410, 0x0000, 0x1082, 0x0000, 0x39E7, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0220 (544)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B2, 0x0000, 0xB596, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE,   // 0x0230 (560)
+0xF79E, 0xEF7D, 0xEF7D, 0xE73C, 0xF79E, 0xAD55, 0x0861, 0x10A2, 0x0861, 0x0841, 0xCE59, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0240 (576)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0x3185, 0x10A2, 0xE71C, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF79E,   // 0x0250 (592)
+0xEF7D, 0xEF7D, 0xEF5D, 0xE73C, 0xEF5D, 0xBDF7, 0x18C3, 0x18C3, 0x18C3, 0x0000, 0x8C71, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0260 (608)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B2, 0x0000, 0x39E7, 0xF7BE, 0xFFFF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF79E, 0xEF7D,   // 0x0270 (624)
+0xEF7D, 0xEF5D, 0xE73C, 0xE71C, 0xE71C, 0xC618, 0x18E3, 0x10A2, 0x10A2, 0x0020, 0x6B4D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0280 (640)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8C51, 0x38E0, 0x4A27, 0xFFFF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF79E, 0xEF7D, 0xEF7D,   // 0x0290 (656)
+0xEF5D, 0xE73C, 0xE71C, 0xDEFB, 0xDF1D, 0xBDF8, 0x39C7, 0x5ACB, 0x528A, 0x10A3, 0x738F, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02A0 (672)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDD6C, 0xFE2B, 0xBC45, 0xA513, 0xFFFF, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF5D,   // 0x02B0 (688)
+0xE73C, 0xE71C, 0xDEFB, 0xD6DC, 0xDD8E, 0xB3E4, 0x2124, 0x2965, 0x2945, 0x20C1, 0xB511, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF77C, 0xE5CF, 0xF60B, 0xFF9B, 0xFF54, 0x8B02, 0x7BF0, 0xFFDF, 0xF79E, 0xEF5D, 0xEF5D, 0xE73C,   // 0x02D0 (720)
+0xE71C, 0xDEFB, 0xDEDB, 0xCE7A, 0xED89, 0xDDAD, 0x0842, 0x0000, 0x0000, 0xAC69, 0xDD6B, 0xEFBF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02E0 (736)
+0xFFFF, 0xFFFF, 0xFFBE, 0xE5CB, 0xEDC9, 0xFE4B, 0xFF14, 0xFEF3, 0xFF35, 0xFE8D, 0x51C1, 0x634E, 0xE73C, 0xEF5D, 0xE73C, 0xE71C,   // 0x02F0 (752)
+0xDEFB, 0xDEDB, 0xD6DB, 0xCE59, 0xE58B, 0xFF98, 0xBD4F, 0x8B88, 0xCD90, 0xFFB7, 0xCCE8, 0xE73D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xEF3B, 0xF583, 0xFF30, 0xFF11, 0xFECF, 0xFEEF, 0xFECF, 0xFF30, 0xDD46, 0x2903, 0x6B8E, 0xEF7D, 0xE71C, 0xDEFB,   // 0x0310 (784)
+0xDEDB, 0xD6BA, 0xD69A, 0xCE59, 0xE5AA, 0xFF11, 0xFF53, 0xFF73, 0xFF33, 0xFF12, 0xFE6C, 0xDDAD, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0320 (800)
+0xFFFF, 0xFFFF, 0xF79E, 0xEDC5, 0xFECB, 0xFECC, 0xFECC, 0xFEEC, 0xFECB, 0xFECC, 0xFEEA, 0x9BE5, 0x8432, 0xE73C, 0xDEDB, 0xDEDB,   // 0x0330 (816)
+0xD6BA, 0xD69A, 0xDEDB, 0xA4F3, 0xD547, 0xFF2E, 0xFECD, 0xFECE, 0xFEEE, 0xFEEE, 0xFF10, 0xFEAB, 0xE5A8, 0xEF7D, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xF79E, 0xF603, 0xFEA2, 0xFEC7, 0xFEC7, 0xFEA4, 0xFE81, 0xFE61, 0xFEA4, 0xFE43, 0xDE33, 0xE75E, 0xE71C, 0xDEFB,   // 0x0350 (848)
+0xDEDB, 0xCE58, 0x8C72, 0x5247, 0xEDE4, 0xFF0A, 0xFECA, 0xFEC9, 0xFE84, 0xFE83, 0xFEE7, 0xFEA3, 0xB443, 0xD69B, 0xFFFF, 0xFFFF,   // 0x0360 (864)
+0xFFFF, 0xFFFF, 0xF75B, 0xFE60, 0xFF00, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEE0, 0xE5C1, 0x9492, 0xA514, 0x9CD3,   // 0x0370 (880)
+0x8410, 0x630B, 0x4229, 0x6AE8, 0xFE80, 0xFEC1, 0xFEC1, 0xFEA0, 0xFEA0, 0xFEE0, 0xDD80, 0x9BE8, 0xB597, 0xFFDF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xF79E, 0xD589, 0xE600, 0xFEA0, 0xFF00, 0xFF40, 0xFF40, 0xFF00, 0xFF00, 0xFF20, 0xFEC0, 0x5267, 0x4229, 0x4A48,   // 0x0390 (912)
+0x4A49, 0x5289, 0x424A, 0x7B46, 0xFF20, 0xFEE0, 0xFEE0, 0xFF20, 0xFEE0, 0xB4A5, 0x9C92, 0xDEFD, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xFFFF, 0xE71D, 0xBDB6, 0xB530, 0xBD0B, 0xCD65, 0xEE60, 0xFF40, 0xFFA0, 0xFF80, 0xBD03, 0x8410, 0xA514, 0xA534,   // 0x03B0 (944)
+0xAD75, 0xB596, 0xA555, 0x9C8F, 0xF6C0, 0xFFA0, 0xFFA0, 0xF6E0, 0xA449, 0xB5B8, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7F, 0xD69C, 0xBD95, 0xBD4C, 0xCDC6, 0xB4E8, 0xAD35, 0xF7BF, 0xFFFF, 0xFFFF,   // 0x03D0 (976)
+0xFFFF, 0xFFFF, 0xFFFF, 0xF7BF, 0xCDD0, 0xCDC6, 0xCDA7, 0xA48D, 0xCE7B, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDF1F, 0xB59A, 0xBDDA, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFDF, 0xFFDF, 0xFFFF, 0xEF7F, 0xB59A, 0xAD59, 0xDF1D, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap_128x128/UTFT_Bitmap_128x128.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap_128x128/UTFT_Bitmap_128x128.ino
new file mode 100644
index 0000000..3cc269e
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap_128x128/UTFT_Bitmap_128x128.ino	
@@ -0,0 +1,49 @@
+// UTFT_Bitmap_128x128 (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the drawBitmap()-function.
+//
+// This demo was made to work on the 128x128 modules.
+// Any other size displays may cause strange behaviour.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+UTFT myGLCD(LPH9135,6,5,2,3,4);   // Remember to change the model parameter to suit your display module!
+
+extern unsigned short icon1[0x400];
+extern unsigned short icon2[0x400];
+extern unsigned short tux[0x1000];
+
+void setup()
+{
+  myGLCD.InitLCD(PORTRAIT);
+}
+
+void loop()
+{
+// Draw a 4 by 4 grid of a 32x32 icon.
+  myGLCD.fillScr(255, 255, 255);
+  for (int x=0; x<4; x++)
+    for (int y=0; y<4; y++)
+      myGLCD.drawBitmap (x*32, y*32, 32, 32, icon1);
+
+  delay(5000);
+  
+// Draw a 64x64 icon in double size.
+  myGLCD.fillScr(255, 255, 255);
+  myGLCD.drawBitmap (0, 0, 64, 64, tux, 2);
+
+  delay(5000);
+
+// Draw a 2 by 2 grid of a 32x32 icon in double size.
+  myGLCD.fillScr(255, 255, 255);
+  for (int x=0; x<2; x++)
+    for (int y=0; y<2; y++)
+      myGLCD.drawBitmap (x*64, y*64, 32, 32, icon2, 2);
+
+  delay(5000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap_128x128/icon1.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap_128x128/icon1.c
new file mode 100644
index 0000000..b9c2c97
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap_128x128/icon1.c	
@@ -0,0 +1,72 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: exit.png
+// Time generated: 14.10.2010 21:53:03
+// Dimensions    : 32x32 pixels
+// Size          : 2 048 Bytes
+
+const unsigned short icon1[0x400] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF1C, 0xE618, 0xE638, 0xE638, 0xE638, 0xE659, 0xE659, 0xE659, 0xE659, 0xE659, 0xE679, 0xE679,   // 0x0010 (16)
+0xE679, 0xE679, 0xE679, 0xE679, 0xEE79, 0xEE9A, 0xEE9A, 0xEE9A, 0xEE9A, 0xEE9A, 0xE638, 0xEEBA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xD555, 0xCCD3, 0xDDB6, 0xDDD7, 0xDDF7, 0xDDF7, 0xDE18, 0xE618, 0xE638, 0xE638, 0xE659, 0xE679, 0xE679,   // 0x0030 (48)
+0xEE9A, 0xEE9A, 0xEEBA, 0xEEBA, 0xEEBA, 0xEEDB, 0xEEDB, 0xEEFB, 0xEEFB, 0xEEFB, 0xEEFB, 0xE659, 0xD575, 0xF77D, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFDF, 0xFFFF, 0xD534, 0xC471, 0xD575, 0xCCF3, 0xCCD3, 0xCCD3, 0xCCF3, 0xCCF3, 0xD4F3, 0xD514, 0xD514, 0xD514, 0xD534, 0xDD55,   // 0x0050 (80)
+0xDD55, 0xDD55, 0xDD55, 0xDD75, 0xDD75, 0xDD75, 0xDD96, 0xDD96, 0xDD96, 0xDDB6, 0xDDD7, 0xEE79, 0xEEBA, 0xD534, 0xFFBE, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xEEDB, 0xB38E, 0xC4B2, 0xBC30, 0xC451, 0xC471, 0xC471, 0xCC71, 0xCC92, 0xCC92, 0xCC92, 0xCCB2, 0xD4B2, 0xD4B2, 0xCC71,   // 0x0070 (112)
+0xCC71, 0xD4D3, 0xD4F3, 0xDCF3, 0xDCF3, 0xDD14, 0xDD14, 0xDD14, 0xDD34, 0xDD34, 0xDD34, 0xDD14, 0xE5D7, 0xDD96, 0xDDF7, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xC4F3, 0xAB2C, 0xC430, 0xC410, 0xC430, 0xC430, 0xC430, 0xCC51, 0xCC51, 0xCC51, 0xCC71, 0xCC71, 0xD471, 0xCC71, 0xD5F7,   // 0x0090 (144)
+0xD5F7, 0xCC92, 0xDCB2, 0xDCD3, 0xDCD3, 0xDCD3, 0xDCD3, 0xDCF3, 0xDCF3, 0xDD14, 0xDD14, 0xDD34, 0xDD14, 0xDD34, 0xC492, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xB3EF, 0x9A28, 0xC430, 0xBBCF, 0xC3EF, 0xC3EF, 0xC3EF, 0xC410, 0xCC10, 0xCC10, 0xCC30, 0xCC51, 0xCBEF, 0xE638, 0xFFFF,   // 0x00B0 (176)
+0xFFFF, 0xE659, 0xD430, 0xDC92, 0xDC92, 0xDC92, 0xDCB2, 0xDCB2, 0xDCB2, 0xDCD3, 0xDCD3, 0xDCD3, 0xE514, 0xD410, 0xAB0C, 0xF7FF,   // 0x00C0 (192)
+0xFFFF, 0xABCF, 0x9165, 0xC3EF, 0xBB8E, 0xBBAE, 0xC3AE, 0xC3CF, 0xC3CF, 0xCBCF, 0xCBEF, 0xCC10, 0xCC10, 0xCBAE, 0xEE9A, 0xFFFF,   // 0x00D0 (208)
+0xFFFF, 0xF6DB, 0xD410, 0xDC71, 0xDC71, 0xDC71, 0xDC71, 0xDC71, 0xDC71, 0xE492, 0xE492, 0xE492, 0xE4F3, 0xCB2C, 0xA249, 0xF7FF,   // 0x00E0 (224)
+0xFFFF, 0xABCF, 0x88C3, 0xC3AE, 0xBB4D, 0xBB6D, 0xC36D, 0xC38E, 0xC38E, 0xCBAE, 0xC36D, 0xC34D, 0xCBCF, 0xCB8E, 0xEE59, 0xFFFF,   // 0x00F0 (240)
+0xFFFF, 0xF6BA, 0xDBCF, 0xD3CF, 0xCBAE, 0xD3CF, 0xE430, 0xE430, 0xE451, 0xE451, 0xE451, 0xE451, 0xECD3, 0xCAAA, 0xA208, 0xF7FF,   // 0x0100 (256)
+0xFFFF, 0xABCF, 0x8061, 0xBB6D, 0xBB2C, 0xBB2C, 0xC34D, 0xC34D, 0xCB4D, 0xBB0C, 0xC492, 0xCD14, 0xC38E, 0xCB2C, 0xEE59, 0xFFFF,   // 0x0110 (272)
+0xFFFF, 0xF6BA, 0xD36D, 0xD575, 0xE6DB, 0xDDB6, 0xD3AE, 0xE3EF, 0xE410, 0xE410, 0xE430, 0xE410, 0xECB2, 0xC986, 0xA208, 0xF7FF,   // 0x0120 (288)
+0xFFFF, 0xB3EF, 0x8041, 0xBB0C, 0xBAEB, 0xBAEB, 0xC30C, 0xC30C, 0xBACB, 0xD5B6, 0xFFFF, 0xFFFF, 0xEE79, 0xCACB, 0xEE59, 0xFFFF,   // 0x0130 (304)
+0xFFFF, 0xF679, 0xDBEF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEEBA, 0xD3CF, 0xE3AE, 0xE3EF, 0xE3CF, 0xEC10, 0xEB6D, 0xC000, 0xA249, 0xF7FF,   // 0x0140 (320)
+0xFFFF, 0xB3EF, 0x8020, 0xBACB, 0xBAAA, 0xBAAA, 0xC2EB, 0xBA8A, 0xD596, 0xFFFF, 0xFFDF, 0xFFFF, 0xF73C, 0xCAAA, 0xEE38, 0xFFFF,   // 0x0150 (336)
+0xFFFF, 0xF679, 0xDB4D, 0xFF7D, 0xFFFF, 0xFFDF, 0xFFFF, 0xEEDB, 0xDB6D, 0xEB8E, 0xEBAE, 0xEB8E, 0xE0A2, 0xC800, 0xAA49, 0xF7FF,   // 0x0160 (352)
+0xFFFF, 0xB3EF, 0x8000, 0xB28A, 0xBA69, 0xBA8A, 0xBA49, 0xCC30, 0xFFFF, 0xFFDF, 0xFFFF, 0xFF5D, 0xDBCF, 0xCA69, 0xEE18, 0xFFFF,   // 0x0170 (368)
+0xFFFF, 0xF679, 0xDAAA, 0xE3AE, 0xF6BA, 0xFFFF, 0xFFDF, 0xFFFF, 0xE5D7, 0xE30C, 0xEB8E, 0xE0E3, 0xE000, 0xC800, 0xAA49, 0xF7FF,   // 0x0180 (384)
+0xFFFF, 0xB3EF, 0x8800, 0xB249, 0xBA49, 0xBA49, 0xBA49, 0xEF1C, 0xFFFF, 0xFFFF, 0xFF7D, 0xD32C, 0xCA69, 0xD249, 0xEDF7, 0xFFFF,   // 0x0190 (400)
+0xFFFF, 0xF659, 0xDAAA, 0xE2CB, 0xE2EB, 0xFEBA, 0xFFFF, 0xFFDF, 0xFFDF, 0xE3CF, 0xE103, 0xE000, 0xE081, 0xD000, 0xAA69, 0xF7FF,   // 0x01A0 (416)
+0xFFFF, 0xB3EF, 0x8800, 0xB228, 0xBA08, 0xB9A6, 0xCBAE, 0xFFFF, 0xFFDF, 0xFFFF, 0xDC30, 0xC9E7, 0xD28A, 0xCA08, 0xF618, 0xFFFF,   // 0x01B0 (432)
+0xFFFF, 0xF679, 0xDA49, 0xE2CB, 0xE28A, 0xEB6D, 0xFFBE, 0xFFDF, 0xFFFF, 0xEC92, 0xE000, 0xE0A2, 0xE0C2, 0xD040, 0xAA89, 0xF7FF,   // 0x01C0 (448)
+0xFFFF, 0xB3EF, 0x8800, 0xB1E7, 0xB9E7, 0xB165, 0xDD55, 0xFFFF, 0xFFFF, 0xF71C, 0xCA08, 0xCA08, 0xD228, 0xD1E7, 0xE430, 0xFFDF,   // 0x01D0 (464)
+0xFFDF, 0xEC51, 0xDA08, 0xE28A, 0xE28A, 0xE228, 0xF618, 0xFFFF, 0xFFFF, 0xF679, 0xE081, 0xE0C2, 0xE903, 0xD081, 0xAA89, 0xF7FF,   // 0x01E0 (480)
+0xFFFF, 0xBBEF, 0x9000, 0xB1A6, 0xB986, 0xB145, 0xEE38, 0xFFFF, 0xFFFF, 0xED96, 0xC165, 0xC9E7, 0xD1E7, 0xD1E7, 0xD1C7, 0xDACB,   // 0x01F0 (496)
+0xE2EB, 0xD9E7, 0xE228, 0xE228, 0xEA69, 0xE9E7, 0xF40F, 0xFFFF, 0xFFFF, 0xFF5D, 0xE144, 0xE8E2, 0xE943, 0xD8C1, 0xAA8A, 0xF7FF,   // 0x0200 (512)
+0xFFFF, 0xBC10, 0x9000, 0xB165, 0xB145, 0xB924, 0xEE9A, 0xFFFF, 0xFFFF, 0xE514, 0xC124, 0xC9A6, 0xD1A6, 0xD1A6, 0xD1C7, 0xD9A6,   // 0x0210 (528)
+0xD9A6, 0xE1E7, 0xE208, 0xE208, 0xE9A6, 0xE041, 0xEA8A, 0xFFFF, 0xFFFF, 0xFF9E, 0xE9C6, 0xE902, 0xE984, 0xD902, 0xAAAA, 0xF7FF,   // 0x0220 (544)
+0xFFFF, 0xC410, 0x9000, 0xB124, 0xB124, 0xB0C3, 0xEE18, 0xFFFF, 0xFFFF, 0xE575, 0xC0E3, 0xC986, 0xD165, 0xD165, 0xD986, 0xD9A6,   // 0x0230 (560)
+0xD9A6, 0xE1A6, 0xE165, 0xE082, 0xE020, 0xE000, 0xEB4C, 0xFFFF, 0xFFFF, 0xFF7D, 0xE9A5, 0xE943, 0xE9A5, 0xD923, 0xAAAA, 0xF7FF,   // 0x0240 (576)
+0xFFFF, 0xC410, 0x9800, 0xB0E3, 0xB0E3, 0xB061, 0xE4F3, 0xFFFF, 0xFFFF, 0xF6FB, 0xC104, 0xC924, 0xD145, 0xD145, 0xD945, 0xD945,   // 0x0250 (592)
+0xD8E3, 0xD861, 0xD800, 0xE000, 0xE061, 0xE000, 0xED34, 0xFFFF, 0xFFFF, 0xFE9A, 0xE923, 0xE984, 0xE9C5, 0xE163, 0xAAAA, 0xF7FF,   // 0x0260 (608)
+0xFFFF, 0xC410, 0xA000, 0xB0A2, 0xB0A2, 0xB041, 0xCACB, 0xFFFF, 0xFFDF, 0xFFFF, 0xD34D, 0xC841, 0xD104, 0xD0A2, 0xD061, 0xD000,   // 0x0270 (624)
+0xD800, 0xD800, 0xE000, 0xE041, 0xE000, 0xD965, 0xFF9E, 0xFFDF, 0xFFFF, 0xF4D2, 0xE8E2, 0xE9A5, 0xE9E5, 0xE183, 0xAAAA, 0xF7FF,   // 0x0280 (640)
+0xFFFF, 0xCC10, 0xA000, 0xA861, 0xB061, 0xB061, 0xB882, 0xF6DB, 0xFFFF, 0xFFDF, 0xF75D, 0xC124, 0xC800, 0xD000, 0xD000, 0xD800,   // 0x0290 (656)
+0xD800, 0xE000, 0xE020, 0xE000, 0xD861, 0xF638, 0xFFFF, 0xFFDF, 0xFFDF, 0xEA68, 0xE943, 0xE9C5, 0xEA06, 0xE1A4, 0xB2CA, 0xF7FF,   // 0x02A0 (672)
+0xFFFF, 0xCC10, 0xA000, 0xA820, 0xB000, 0xB000, 0xB000, 0xCA49, 0xFFFF, 0xFFDF, 0xFFFF, 0xF71C, 0xCA08, 0xC800, 0xD000, 0xD800,   // 0x02B0 (688)
+0xD800, 0xD800, 0xD800, 0xD944, 0xEE18, 0xFFFF, 0xFFBE, 0xFFFF, 0xF4F2, 0xE902, 0xE9A5, 0xE9C5, 0xEA06, 0xE9A4, 0xB2CA, 0xF7FF,   // 0x02C0 (704)
+0xFFFF, 0xD410, 0xA800, 0xA800, 0xB000, 0xB000, 0xB800, 0xB800, 0xDC10, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xED96, 0xDAEB, 0xD1A6,   // 0x02D0 (720)
+0xD965, 0xDA69, 0xECD3, 0xFF9E, 0xFFFF, 0xFFBE, 0xFFFF, 0xFE17, 0xE923, 0xE964, 0xE9A5, 0xE9C5, 0xEA26, 0xE9C4, 0xBACA, 0xF7FF,   // 0x02E0 (736)
+0xF7FF, 0xD410, 0xA800, 0xA800, 0xB000, 0xB000, 0xB800, 0xB800, 0xB800, 0xE3EF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02F0 (752)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF5B6, 0xE923, 0xE923, 0xE984, 0xE9A5, 0xE9E5, 0xEA26, 0xE9C5, 0xBACA, 0xF7FF,   // 0x0300 (768)
+0xF7FF, 0xDC10, 0xB000, 0xA800, 0xB000, 0xB000, 0xB800, 0xB800, 0xC000, 0xC000, 0xD228, 0xF638, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0310 (784)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFEFB, 0xF3AE, 0xE0C1, 0xE903, 0xE964, 0xE984, 0xE9A5, 0xE9E5, 0xEA26, 0xE9E5, 0xC2CA, 0xF7DF,   // 0x0320 (800)
+0xF7FF, 0xDC51, 0xB800, 0xA800, 0xB000, 0xB000, 0xB800, 0xB800, 0xC000, 0xC000, 0xC000, 0xC800, 0xD9E7, 0xEC30, 0xF5D7, 0xFE9A,   // 0x0330 (816)
+0xFEBA, 0xF618, 0xF4D3, 0xEACB, 0xE0E2, 0xE040, 0xE903, 0xE943, 0xE943, 0xE984, 0xE9A5, 0xE9E5, 0xEA26, 0xEA05, 0xC30C, 0xF7DF,   // 0x0340 (832)
+0xFFFF, 0xD575, 0xD104, 0xA820, 0xB000, 0xB800, 0xB800, 0xC000, 0xC000, 0xC000, 0xC820, 0xC800, 0xD000, 0xD000, 0xD800, 0xD800,   // 0x0350 (848)
+0xE000, 0xE000, 0xE000, 0xE000, 0xE0A1, 0xE0E3, 0xE903, 0xE943, 0xE964, 0xE984, 0xE9C5, 0xE9C5, 0xF226, 0xE227, 0xBC10, 0xF7FF,   // 0x0360 (864)
+0xFFFF, 0xDF3C, 0xCAAA, 0xD186, 0xB082, 0xB000, 0xB800, 0xB800, 0xB800, 0xC000, 0xC000, 0xC800, 0xC800, 0xD000, 0xD000, 0xD800,   // 0x0370 (880)
+0xD800, 0xE000, 0xE020, 0xE040, 0xE061, 0xE0A1, 0xE0C2, 0xE102, 0xE123, 0xE943, 0xE984, 0xEA26, 0xFB0A, 0xBA08, 0xCE38, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFDF, 0xBDD7, 0xCA69, 0xE248, 0xD207, 0xD1C6, 0xD1C6, 0xD9C7, 0xD9C7, 0xE1C7, 0xE1C7, 0xE1C7, 0xE9C7, 0xE9C7, 0xE9C7,   // 0x0390 (912)
+0xF1C6, 0xF1C7, 0xF1E7, 0xF207, 0xF228, 0xF248, 0xF269, 0xF289, 0xF2A9, 0xF2CA, 0xFB0A, 0xF2EA, 0xC207, 0xACB3, 0xF7BE, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xF7BE, 0xBDF7, 0xAB8E, 0xC2EB, 0xC2EB, 0xC30B, 0xC30B, 0xC30B, 0xC30B, 0xC30B, 0xC30B, 0xC30B, 0xCB0B, 0xCAEB,   // 0x03B0 (944)
+0xCAEB, 0xCACA, 0xCACA, 0xCAAA, 0xCAAA, 0xCA8A, 0xCA69, 0xC269, 0xC269, 0xC289, 0xBA69, 0xA2CB, 0xAD34, 0xEF7D, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xDF3C, 0xBE39, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7,   // 0x03D0 (976)
+0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xBE38, 0xD71C, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap_128x128/icon2.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap_128x128/icon2.c
new file mode 100644
index 0000000..9b843cc
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap_128x128/icon2.c	
@@ -0,0 +1,72 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: video.png
+// Time generated: 14.10.2010 21:53:17
+// Dimensions    : 32x32 pixels
+// Size          : 2 048 Bytes
+
+const unsigned short icon2[0x400] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0010 (16)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE71C, 0xB5B6, 0x94B2, 0x8C71,   // 0x0030 (48)
+0x9492, 0xA534, 0xD6BA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF5D, 0x9CF3, 0x73AE, 0x6B6D, 0x73AE, 0x7BCF,   // 0x0050 (80)
+0x7BEF, 0x7BCF, 0x7BEF, 0xA534, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xC638, 0x7BCF, 0x6B6D, 0x738E, 0x7BCF, 0x8C71, 0x9492,   // 0x0070 (112)
+0x9492, 0x9492, 0x9492, 0x8C51, 0x8C71, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB596, 0x738E, 0x738E, 0x73AE, 0x6B4D, 0x8410, 0x9CF3, 0x9CF3,   // 0x0090 (144)
+0x9CF3, 0x9CF3, 0x9CF3, 0x9CF3, 0x94B2, 0x7BEF, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB596, 0x738E, 0x7BEF, 0x8410, 0x632C, 0x4A69, 0x9492, 0xAD75, 0xAD55,   // 0x00B0 (176)
+0xAD55, 0xAD55, 0xAD55, 0xA534, 0xAD55, 0x9492, 0x8430, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xBDF7, 0x7BCF, 0x8430, 0x7BCF, 0x6B4D, 0x528A, 0x6B6D, 0xB5B6, 0xB5B6, 0xB5B6,   // 0x00D0 (208)
+0xB5B6, 0xB596, 0xB596, 0xAD75, 0xAD75, 0xAD55, 0x8410, 0xB5B6, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00E0 (224)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDB, 0x7BEF, 0x9CD3, 0xA514, 0x5AEB, 0x630C, 0x6B4D, 0x9492, 0xC638, 0xC618, 0xC618,   // 0x00F0 (240)
+0xBDF7, 0xBDF7, 0xC618, 0xB5B6, 0xB5B6, 0xB596, 0x9492, 0x8C51, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x8C71, 0x94B2, 0xAD55, 0xB5B6, 0x738E, 0x6B4D, 0x632C, 0xB596, 0xD69A, 0xCE59, 0xCE59,   // 0x0110 (272)
+0xCE79, 0xCE59, 0x6B6D, 0x9492, 0xB5B6, 0xBDF7, 0x9CF3, 0x8430, 0xD69A, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0120 (288)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB5B6, 0x8C51, 0xAD55, 0xB5B6, 0xCE79, 0x8C51, 0x630C, 0x8C51, 0xCE79, 0xD6BA, 0xD69A, 0xDEDB,   // 0x0130 (304)
+0xBDD7, 0x8C51, 0x4228, 0x2965, 0xAD55, 0xC638, 0xA534, 0x8430, 0xB5B6, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0xFFFF, 0xEF5D, 0x8C51, 0xA514, 0xB5B6, 0xC618, 0xD6BA, 0xB5B6, 0xB596, 0xE71C, 0xDEFB, 0xDEFB, 0xE71C, 0xAD55,   // 0x0150 (336)
+0x738E, 0x7BEF, 0x5AEB, 0x2945, 0xC638, 0xCE59, 0xA534, 0x9492, 0xA534, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0160 (352)
+0xFFFF, 0xFFFF, 0xFFFF, 0xB596, 0x94B2, 0xB5B6, 0xC618, 0xCE79, 0xD6BA, 0xE73C, 0xEF7D, 0xE73C, 0xEF5D, 0xE73C, 0x9CF3, 0x738E,   // 0x0170 (368)
+0x7BCF, 0x8430, 0x6B6D, 0x2965, 0xB596, 0xD69A, 0xAD55, 0x94B2, 0x9CD3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0180 (384)
+0xFFFF, 0xFFFF, 0xF79E, 0x9492, 0x9CF3, 0xB5B6, 0xD69A, 0xDEFB, 0xE71C, 0xE73C, 0x6B6D, 0x528A, 0xDEDB, 0xEF5D, 0x7BEF, 0x8430,   // 0x0190 (400)
+0x7BEF, 0x8C51, 0x7BCF, 0x2104, 0xB596, 0xD6BA, 0xAD55, 0x9CD3, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73C, 0xE6FC,   // 0x01A0 (416)
+0xFFDF, 0xFFFF, 0xCE59, 0x9492, 0x9492, 0x6B4D, 0x7BCF, 0xBDD7, 0xF7BE, 0xA514, 0x4A49, 0x528A, 0xC638, 0xEF7D, 0x7BEF, 0x7BEF,   // 0x01B0 (432)
+0x7BEF, 0x8430, 0x5AEB, 0x10A2, 0xC618, 0xD69A, 0xAD55, 0x94B2, 0xA514, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCE5A, 0x8BF2,   // 0x01C0 (448)
+0xFFFF, 0xFFFF, 0xAD55, 0x94B2, 0x8C51, 0x5AEB, 0x632C, 0xBDD7, 0xE73C, 0x630C, 0x632C, 0xBDF7, 0xFFDF, 0xEF5D, 0xBDD7, 0xB5B6,   // 0x01D0 (464)
+0xAD75, 0xAD75, 0x8C51, 0x738E, 0xD69A, 0xCE59, 0xB596, 0x8C51, 0xB5B6, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xCE39, 0x7350,   // 0x01E0 (480)
+0xFFFF, 0xF79E, 0x94B2, 0x94B2, 0x7BCF, 0x5AEB, 0x738E, 0xD6BA, 0xD69A, 0x2104, 0x6B6D, 0xF79E, 0xF79E, 0xF79E, 0xF7BE, 0xF79E,   // 0x01F0 (496)
+0xEF7D, 0xEF5D, 0xE73C, 0xE73C, 0xDEFB, 0xBDF7, 0xBDF7, 0x7BEF, 0xD69A, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAD36, 0x7350,   // 0x0200 (512)
+0xFFFF, 0xDEDB, 0x8C51, 0x94B2, 0x738E, 0x632C, 0x73AE, 0xCE79, 0xF7BE, 0x7BEF, 0xA514, 0xF7BE, 0xF79E, 0xEF7D, 0xEF7D, 0xEF5D,   // 0x0210 (528)
+0xE73C, 0xE71C, 0xDEFB, 0xDEDB, 0xDEDB, 0xBDD7, 0xBDF7, 0x73AE, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x9C75, 0x736F,   // 0x0220 (544)
+0xFFFF, 0xCE59, 0x8430, 0x94B2, 0x6B4D, 0x6B4D, 0xB596, 0xE73C, 0xEF7D, 0xFFFF, 0xFFFF, 0xF7BE, 0xF79E, 0xEF7D, 0xEF7D, 0xEF5D,   // 0x0230 (560)
+0xE73C, 0xE73C, 0xDEFB, 0xDEFB, 0xD6BA, 0xC618, 0xAD55, 0x8C71, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDB, 0x6AEF, 0x9492,   // 0x0240 (576)
+0xFFFF, 0xBDF7, 0x8430, 0x8C71, 0x6B6D, 0xB596, 0xE71C, 0xE73C, 0xEF5D, 0xE73C, 0xBDF7, 0xCE59, 0xF7BE, 0xEF7D, 0xEF7D, 0xEF5D,   // 0x0250 (592)
+0xE73C, 0xE71C, 0xDEFB, 0xDEFB, 0xC638, 0xD69A, 0x8410, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x9474, 0x6B0E, 0xCE59,   // 0x0260 (608)
+0xFFFF, 0xB5B6, 0x8410, 0x9492, 0xBDD7, 0xD6BA, 0xD6BA, 0xE71C, 0xE73C, 0x8C71, 0x6B4D, 0xA514, 0xF7BE, 0xEF5D, 0xEF5D, 0xE73C,   // 0x0270 (624)
+0xE73C, 0xE71C, 0xDEFB, 0xDEDB, 0xCE59, 0xC618, 0x7BCF, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xC5F9, 0x7B51, 0x7BEF, 0xFFFF,   // 0x0280 (640)
+0xFFFF, 0xB596, 0x8C71, 0xAD75, 0xBDF7, 0xCE59, 0xD69A, 0xE71C, 0xCE79, 0x8410, 0x8410, 0x9CD3, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C,   // 0x0290 (656)
+0xE71C, 0xDEFB, 0xDEFB, 0xCE59, 0xDEDB, 0x8C71, 0xAD75, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEBB, 0x83B2, 0x630C, 0xE73C, 0xFFFF,   // 0x02A0 (672)
+0xFFFF, 0xB5B6, 0x9492, 0xAD55, 0xBDD7, 0xC638, 0xCE79, 0xDEFB, 0xB596, 0x73AE, 0x8410, 0x8410, 0xDEDB, 0xE73C, 0xE71C, 0xE71C,   // 0x02B0 (688)
+0xDEFB, 0xDEFB, 0xD6BA, 0xCE59, 0xC618, 0x738E, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDC, 0x8C14, 0x5ACC, 0xC658, 0xFFFF, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xC638, 0x8C51, 0xA534, 0xB5B6, 0xBDF7, 0xCE59, 0xD6BA, 0x94B2, 0x738E, 0x8410, 0x8430, 0xCE59, 0xE73C, 0xDEFB, 0xDEFB,   // 0x02D0 (720)
+0xDEDB, 0xDEFB, 0xBDF7, 0xDEDB, 0x73AE, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDC, 0x8BD2, 0x5ACC, 0xBDD6, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02E0 (736)
+0xFFFF, 0xDEDB, 0x8C51, 0xA514, 0xAD75, 0xBDD7, 0xC638, 0xC618, 0x73AE, 0x7BCF, 0x8410, 0x5ACB, 0x8C51, 0xE73C, 0xDEDB, 0xD6BA,   // 0x02F0 (752)
+0xDEFB, 0xBDD7, 0xD69A, 0x8C71, 0x8C51, 0xFFFF, 0xFFFF, 0xFFDE, 0xCE5A, 0x7B71, 0x62ED, 0xBDF7, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xF7BE, 0x94B2, 0x94B2, 0xA534, 0xB596, 0xBDF7, 0xB596, 0x6B6D, 0x4208, 0x2945, 0x18C3, 0x6B6D, 0xDEFB, 0xD69A, 0xDEDB,   // 0x0310 (784)
+0xB5B6, 0xC618, 0x9CF3, 0x6B4D, 0xFFDE, 0xFFFF, 0xEF5D, 0xAD37, 0x62EE, 0x6B4D, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0320 (800)
+0xFFDF, 0xFFFF, 0xBDF7, 0x8C51, 0xA514, 0xAD55, 0xB596, 0xBDD7, 0xA514, 0x738E, 0xA514, 0xB5B6, 0xCE59, 0xD69A, 0xDEDB, 0xB596,   // 0x0330 (816)
+0xBDF7, 0xA534, 0x6B4C, 0xEF5D, 0xF79E, 0xBDB8, 0x7370, 0x5AAC, 0x8C71, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xF79E, 0x94B2, 0x94B2, 0xA534, 0xAD55, 0xB5B6, 0xA534, 0xBDD7, 0xD69A, 0xCE59, 0xCE79, 0xCE59, 0xA534, 0x8430,   // 0x0350 (848)
+0x738E, 0x3186, 0x7BB0, 0x8C33, 0x7370, 0x62ED, 0x8410, 0xCE59, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0360 (864)
+0xFFFF, 0xFFFF, 0xFFFF, 0xDEFB, 0x8C71, 0x9CD3, 0xAD55, 0xB596, 0xBDD7, 0xBDD7, 0xBDF7, 0xC618, 0xB5B6, 0xA534, 0xA534, 0x632C,   // 0x0370 (880)
+0x6B6D, 0xB5B6, 0xAD76, 0xAD76, 0xBE17, 0xE71B, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEFB, 0x94B2, 0x8C51, 0x94B2, 0xA534, 0xAD55, 0xAD55, 0x9CD3, 0x8C71, 0x73AE, 0x632C, 0xA534,   // 0x0390 (912)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xCE59, 0xA514, 0x8430, 0x7BCF, 0x738E, 0x73AE, 0x8410, 0xA534, 0xEF7D, 0xFFFF,   // 0x03B0 (944)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xE73C, 0xE71C, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03D0 (976)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap_128x128/tux.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap_128x128/tux.c
new file mode 100644
index 0000000..7fefd80
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Bitmap_128x128/tux.c	
@@ -0,0 +1,264 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: tux_64x64.png
+// Time generated: 14.10.2010 21:56:38
+// Dimensions    : 64x64 pixels
+// Size          : 8 192 Bytes
+
+const unsigned short tux[0x1000] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0010 (16)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCE79, 0x9CF3, 0x7BCF, 0x738E, 0x738E,   // 0x0020 (32)
+0x6B6D, 0x94B2, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0030 (48)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0050 (80)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCE79, 0x6B4D, 0x5ACB, 0x8410, 0x9CF3, 0x9CF3, 0x9CF3,   // 0x0060 (96)
+0x9CD3, 0x73AE, 0x4208, 0x5ACB, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0070 (112)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0090 (144)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xA514, 0x3186, 0x8C51, 0xBDF7, 0xC618, 0xBDF7, 0xBDF7, 0xBDF7,   // 0x00A0 (160)
+0xBDF7, 0xC618, 0xBDD7, 0x738E, 0x18C3, 0x8C51, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00B0 (176)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00D0 (208)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xBDD7, 0x10A2, 0x8C71, 0x9CF3, 0x8C71, 0x8C71, 0x8C71, 0x8C71, 0x8C71,   // 0x00E0 (224)
+0x8C71, 0x8C51, 0x8C51, 0x9CF3, 0x73AE, 0x0000, 0x7BEF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00F0 (240)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0110 (272)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x2945, 0x31A6, 0x7BCF, 0x6B4D, 0x6B6D, 0x6B6D, 0x6B6D, 0x6B6D, 0x6B6D,   // 0x0120 (288)
+0x6B6D, 0x6B6D, 0x6B6D, 0x6B4D, 0x73AE, 0x2124, 0x0000, 0xAD55, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0130 (304)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0150 (336)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xC638, 0x0000, 0x31A6, 0x52AA, 0x4A69, 0x4A69, 0x4A69, 0x4A69, 0x4A69, 0x4A69,   // 0x0160 (352)
+0x4A69, 0x4A69, 0x4A69, 0x4A69, 0x528A, 0x2104, 0x0000, 0x2965, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0170 (368)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0180 (384)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0190 (400)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8C71, 0x0000, 0x1082, 0x3186, 0x3186, 0x3186, 0x3186, 0x3186, 0x3186, 0x3186,   // 0x01A0 (416)
+0x3186, 0x3186, 0x3186, 0x3186, 0x2965, 0x0020, 0x0000, 0x0000, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01B0 (432)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01C0 (448)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01D0 (464)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x630C, 0x0000, 0x0000, 0x0861, 0x18C3, 0x10A2, 0x10A2, 0x10A2, 0x10A2, 0x18C3,   // 0x01E0 (480)
+0x1082, 0x0841, 0x1082, 0x10A2, 0x0020, 0x0000, 0x0000, 0x0000, 0x528A, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01F0 (496)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0200 (512)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0210 (528)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x4A49, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0220 (544)
+0x0861, 0x3186, 0x18C3, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2104, 0xD6BA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0230 (560)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0240 (576)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0250 (592)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x39C7, 0x0000, 0x3186, 0xAD75, 0x8C51, 0x0841, 0x0000, 0x0000, 0x0000, 0x4208,   // 0x0260 (608)
+0xD6BA, 0xFFDF, 0xE71C, 0x630C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0841, 0xAD75, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0270 (624)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0280 (640)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0290 (656)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x39C7, 0x0000, 0xCE59, 0xFFFF, 0xFFFF, 0x94B2, 0x0000, 0x0000, 0x10A2, 0xE73C,   // 0x02A0 (672)
+0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x2124, 0x0000, 0x0000, 0x0000, 0x0000, 0x94B2, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02B0 (688)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02D0 (720)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x2965, 0x18E3, 0xDEDB, 0x7BCF, 0xAD75, 0xEF5D, 0x2944, 0x0000, 0x5ACA, 0xFFFF,   // 0x02E0 (736)
+0xAD55, 0x94B2, 0xAD55, 0xF7BE, 0x8410, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C51, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02F0 (752)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0310 (784)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x39E7, 0x2945, 0xA514, 0x9CF3, 0x8C71, 0xD6BB, 0x39C9, 0x0000, 0x632E, 0xF7DF,   // 0x0320 (800)
+0x7BEF, 0xAD54, 0x7BEF, 0xBDF7, 0xB596, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C71, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0330 (816)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0350 (848)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x4A49, 0x18C3, 0x9492, 0x39E7, 0x3187, 0xA48F, 0x8323, 0x5A00, 0x93A6, 0xCDD5,   // 0x0360 (864)
+0x4209, 0x4249, 0x2965, 0x9CD2, 0xB575, 0x0000, 0x0000, 0x0000, 0x0000, 0x9492, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0370 (880)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0390 (912)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x5ACB, 0x0000, 0x9D14, 0x2905, 0x6A40, 0xE643, 0xFFAE, 0xFFF3, 0xFF70, 0xDD86,   // 0x03A0 (928)
+0x7240, 0x1840, 0x18C3, 0xC65A, 0x73CF, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C51, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03B0 (944)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03D0 (976)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x738E, 0x0000, 0x5A6A, 0xD566, 0xFF66, 0xFFF8, 0xFFFD, 0xFFDC, 0xFFFD, 0xFFFA,   // 0x03E0 (992)
+0xFF0E, 0xE566, 0xC464, 0xC4CC, 0x2103, 0x0000, 0x0000, 0x0000, 0x0000, 0x6B6D, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0410 (1040)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x7BEF, 0x0800, 0xB440, 0xFFC6, 0xFFF3, 0xFFB4, 0xFFB2, 0xFF92, 0xFF72, 0xFF53,   // 0x0420 (1056)
+0xFF55, 0xFF75, 0xFEF0, 0xF542, 0x8240, 0x0000, 0x0000, 0x0000, 0x0000, 0x4228, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0430 (1072)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0440 (1088)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0450 (1104)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8432, 0x4140, 0xFFE2, 0xFFEB, 0xFFAC, 0xFF8B, 0xFF4C, 0xFF2C, 0xFEEC, 0xFECB,   // 0x0460 (1120)
+0xFE6A, 0xFE08, 0xFDA7, 0xFDC3, 0xA320, 0x0000, 0x0000, 0x0000, 0x0000, 0x18E3, 0xD69A, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0470 (1136)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0480 (1152)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0490 (1168)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x9D14, 0x28A0, 0xF6E0, 0xFFE1, 0xFF43, 0xFF04, 0xFEC4, 0xFE84, 0xFE23, 0xFDE1,   // 0x04A0 (1184)
+0xFD60, 0xFD20, 0xFD20, 0xFD20, 0x7241, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x04B0 (1200)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x04C0 (1216)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x04D0 (1232)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xB5B6, 0x0000, 0xC4A9, 0xFEC0, 0xFF00, 0xFEA0, 0xFE40, 0xFE00, 0xFDA0, 0xFD60,   // 0x04E0 (1248)
+0xFD40, 0xFD20, 0xEC80, 0xDCC7, 0x8C0F, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x52AA, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x04F0 (1264)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0500 (1280)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0510 (1296)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xAD75, 0x0000, 0xD69B, 0xF631, 0xF5C0, 0xFE80, 0xFE00, 0xFDC0, 0xFD60, 0xFD40,   // 0x0520 (1312)
+0xFCC0, 0xDC86, 0xCD93, 0xE73D, 0xE71C, 0x0861, 0x0000, 0x0000, 0x0000, 0x0000, 0x0861, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0530 (1328)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0540 (1344)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0550 (1360)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x632C, 0x0000, 0xD6BA, 0xFFFF, 0xF5F1, 0xFD40, 0xFD80, 0xFD20, 0xFCE0, 0xECA3,   // 0x0560 (1376)
+0xDD6F, 0xE6FC, 0xFFFF, 0xFFFF, 0xFFFF, 0x632C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x5ACB, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0570 (1392)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0580 (1408)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0590 (1424)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xDEDB, 0x0861, 0x0000, 0xD69A, 0xFFFF, 0xFFFF, 0xFED8, 0xF631, 0xF610, 0xE5F2, 0xE6B9,   // 0x05A0 (1440)
+0xF7BF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xE71C, 0x10A2, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0xB5B6, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x05B0 (1456)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x05C0 (1472)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x05D0 (1488)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x39E7, 0x0000, 0x4228, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7FF, 0xF7DF, 0xFFFF,   // 0x05E0 (1504)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x73AE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3186, 0xEF7D, 0xFFFF, 0xFFFF,   // 0x05F0 (1520)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0600 (1536)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0610 (1552)
+0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x738E, 0x0000, 0x18C3, 0xDEFB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0620 (1568)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFFF, 0xCE59, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6B4D, 0xFFFF, 0xFFFF,   // 0x0630 (1584)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0640 (1600)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0650 (1616)
+0xFFFF, 0xFFDF, 0xFFFF, 0xA514, 0x0000, 0x0000, 0x9CD3, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0660 (1632)
+0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0x2965, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xAD55, 0xFFFF,   // 0x0670 (1648)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0680 (1664)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0690 (1680)
+0xFFDF, 0xFFFF, 0xD69A, 0x0861, 0x0000, 0x2945, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x06A0 (1696)
+0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xFFFF, 0x7BCF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x18C3, 0xD6BA,   // 0x06B0 (1712)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x06C0 (1728)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x06D0 (1744)
+0xFFFF, 0xFFDF, 0x39C7, 0x0000, 0x0000, 0x8430, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x06E0 (1760)
+0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xFFFF, 0xCE79, 0x0841, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x4228,   // 0x06F0 (1776)
+0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0700 (1792)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF,   // 0x0710 (1808)
+0xFFFF, 0x94B2, 0x0000, 0x0020, 0x0020, 0xCE79, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF,   // 0x0720 (1824)
+0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xFFDF, 0x4A69, 0x0000, 0x0841, 0x0000, 0x0000, 0x0000, 0x0020, 0x0000,   // 0x0730 (1840)
+0x8C71, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0740 (1856)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0750 (1872)
+0xEF7D, 0x2104, 0x0020, 0x0000, 0x3186, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF,   // 0x0760 (1888)
+0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xFFFF, 0xB5B6, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0000,   // 0x0770 (1904)
+0x10A2, 0xD6BA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0780 (1920)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF,   // 0x0790 (1936)
+0x8C71, 0x0000, 0x0861, 0x0000, 0x7BCF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF,   // 0x07A0 (1952)
+0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xFFDF, 0x528A, 0x0000, 0x0841, 0x0020, 0x0020, 0x0020, 0x0020,   // 0x07B0 (1968)
+0x0000, 0x630C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x07C0 (1984)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE,   // 0x07D0 (2000)
+0x3186, 0x0000, 0x0841, 0x10A2, 0xE71C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF,   // 0x07E0 (2016)
+0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xF79E, 0xEF5D, 0xF7BE, 0xBDD7, 0x0841, 0x0861, 0x0841, 0x0841, 0x0841, 0x0020,   // 0x07F0 (2032)
+0x0020, 0x1082, 0xC638, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0800 (2048)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xBDD7,   // 0x0810 (2064)
+0x0020, 0x1082, 0x0000, 0x7BEF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE,   // 0x0820 (2080)
+0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF7D, 0x4208, 0x0020, 0x0861, 0x0861, 0x0841, 0x0841,   // 0x0830 (2096)
+0x0841, 0x0000, 0x630C, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0840 (2112)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x6B4D,   // 0x0850 (2128)
+0x0000, 0x0861, 0x2104, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE,   // 0x0860 (2144)
+0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xE73C, 0xF7BE, 0x8430, 0x0000, 0x1082, 0x0861, 0x0861, 0x0861,   // 0x0870 (2160)
+0x0861, 0x0020, 0x18C3, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0880 (2176)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF5D, 0x2124,   // 0x0890 (2192)
+0x0861, 0x0020, 0x8410, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE,   // 0x08A0 (2208)
+0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xEF7D, 0xB5B6, 0x0861, 0x1082, 0x1082, 0x0861, 0x0861,   // 0x08B0 (2224)
+0x0861, 0x0861, 0x0000, 0x8430, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x08C0 (2240)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xA514, 0x0020,   // 0x08D0 (2256)
+0x10A2, 0x1082, 0xD69A, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE,   // 0x08E0 (2272)
+0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xEF5D, 0xCE79, 0x2124, 0x1082, 0x10A2, 0x1082, 0x1082,   // 0x08F0 (2288)
+0x0861, 0x1082, 0x0000, 0x4208, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0900 (2304)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x4208, 0x0861,   // 0x0910 (2320)
+0x1082, 0x31A6, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E,   // 0x0920 (2336)
+0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEDB, 0x39C7, 0x1082, 0x10A2, 0x10A2, 0x1082,   // 0x0930 (2352)
+0x1082, 0x1082, 0x0841, 0x18C3, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0940 (2368)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xA534, 0x0841, 0x18C3,   // 0x0950 (2384)
+0x0841, 0x630C, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E,   // 0x0960 (2400)
+0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xDEFB, 0xE73C, 0x4A49, 0x0861, 0x18C3, 0x10A2, 0x10A2,   // 0x0970 (2416)
+0x10A2, 0x1082, 0x1082, 0x0841, 0x9CD3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0980 (2432)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x3186, 0x1082, 0x18E3,   // 0x0990 (2448)
+0x0861, 0x94B2, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D,   // 0x09A0 (2464)
+0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEDB, 0xE73C, 0x4A69, 0x1082, 0x18E3, 0x18C3, 0x10A2,   // 0x09B0 (2480)
+0x10A2, 0x10A2, 0x10A2, 0x0020, 0x73AE, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x09C0 (2496)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B2, 0x0841, 0x18E3, 0x18E3,   // 0x09D0 (2512)
+0x0861, 0xAD75, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D,   // 0x09E0 (2528)
+0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEDB, 0xE73C, 0x52AA, 0x10A2, 0x2104, 0x18E3, 0x18C3,   // 0x09F0 (2544)
+0x18C3, 0x18C3, 0x10A2, 0x0841, 0x630C, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0A00 (2560)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x632C, 0x0861, 0x18E4, 0x18E4,   // 0x0A10 (2576)
+0x1082, 0xC638, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D,   // 0x0A20 (2592)
+0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xD6BA, 0xE71C, 0x6B4D, 0x10A2, 0x18C3, 0x18C3, 0x10A2,   // 0x0A30 (2608)
+0x10A2, 0x10A2, 0x18C3, 0x0861, 0x5AEB, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0A40 (2624)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x8410, 0x0862, 0x3143, 0x2924,   // 0x0A50 (2640)
+0x0882, 0xBDD7, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D,   // 0x0A60 (2656)
+0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB, 0xE73C, 0x630C, 0x2103, 0x4A69, 0x632C, 0x6B4D,   // 0x0A70 (2672)
+0x528A, 0x2965, 0x18C3, 0x1081, 0x738E, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0A80 (2688)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB596, 0x7A40, 0xECA0, 0xCC00,   // 0x0A90 (2704)
+0x3941, 0xA535, 0xFFFF, 0xF7BE, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D,   // 0x0AA0 (2720)
+0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEFB, 0xD6DB, 0xCE38, 0xC618, 0x4A48, 0x4A49, 0x6B6D, 0x6B4D, 0x6B4D,   // 0x0AB0 (2736)
+0x6B4D, 0x630C, 0x3186, 0x18E4, 0x9492, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0AC0 (2752)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xC488, 0xFD41, 0xFE6D, 0xFE6A,   // 0x0AD0 (2768)
+0xDC60, 0x5A25, 0xB5D8, 0xFFFF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C,   // 0x0AE0 (2784)
+0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xD6BB, 0xBCAB, 0xD462, 0xD462, 0x49E4, 0x10C3, 0x18C3, 0x18C3, 0x18C3,   // 0x0AF0 (2800)
+0x18C3, 0x18E3, 0x10A3, 0x49C4, 0xB575, 0xF7BF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0B00 (2816)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCD70, 0xECA0, 0xFF14, 0xFF9B, 0xFF7B,   // 0x0B10 (2832)
+0xFECF, 0xC3A0, 0x3143, 0x9CF3, 0xFFFF, 0xF7BE, 0xF79E, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C,   // 0x0B20 (2848)
+0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEFB, 0xC617, 0xDC60, 0xFD60, 0xFD20, 0x3120, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0B30 (2864)
+0x0000, 0x0000, 0x3900, 0xE460, 0xB46A, 0xEF9F, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0B40 (2880)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD5F4, 0xDC20, 0xFE8E, 0xFF59, 0xFF36, 0xFF36,   // 0x0B50 (2896)
+0xFF59, 0xFE6B, 0xA300, 0x18E4, 0x8410, 0xFFBE, 0xF7BE, 0xEF7D, 0xF79E, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C,   // 0x0B60 (2912)
+0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEBA, 0xDEFB, 0xC5B5, 0xE4A1, 0xFEF2, 0xF716, 0x3164, 0x18E4, 0x2103, 0x1082, 0x1082,   // 0x0B70 (2928)
+0x0021, 0x1061, 0xD5D0, 0xFE27, 0xB3E3, 0xCE9B, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0B80 (2944)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF77D, 0xE697, 0xDDAF, 0xD4C8, 0xE480, 0xFE29, 0xFF36, 0xFF15, 0xFF35, 0xFF15,   // 0x0B90 (2960)
+0xFF15, 0xFF36, 0xFDA5, 0x6A42, 0x1905, 0x6B4C, 0xE73C, 0xFFDF, 0xEF5D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C,   // 0x0BA0 (2976)
+0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB, 0xD6BA, 0xDEDB, 0xBDB5, 0xE4C3, 0xFF56, 0xFFDB, 0xAD10, 0x10A2, 0x10C3, 0x18E4, 0x1082,   // 0x0BB0 (2992)
+0x2922, 0xC5B1, 0xFFDC, 0xFED1, 0xB3A2, 0xBE19, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0BC0 (3008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE6B8, 0xD484, 0xE4C0, 0xF584, 0xFE28, 0xFECF, 0xFF14, 0xFF13, 0xFF13, 0xFF13, 0xFF13,   // 0x0BD0 (3024)
+0xFF13, 0xFF14, 0xFEF0, 0xDC80, 0x41C5, 0x2945, 0x5269, 0xCE59, 0xF7BE, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C,   // 0x0BE0 (3040)
+0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB, 0xD6BA, 0xD69A, 0xD6DB, 0xBD95, 0xE4E2, 0xFF33, 0xFF36, 0xFF97, 0xDDF1, 0x8B66, 0x7AE4, 0x9BC7,   // 0x0BF0 (3056)
+0xEEB2, 0xFF97, 0xFF37, 0xFEF0, 0xC3E0, 0xB5B7, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C00 (3072)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD52B, 0xFD60, 0xFECD, 0xFF33, 0xFF13, 0xFF12, 0xFEF1, 0xFEF1, 0xFEF1, 0xFEF1, 0xFEF1,   // 0x0C10 (3088)
+0xFEF1, 0xFEF1, 0xFF12, 0xFE69, 0x9B41, 0x31A8, 0x31A6, 0x39E7, 0xB5B6, 0xF79E, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB,   // 0x0C20 (3104)
+0xDEFB, 0xDEDB, 0xDEDB, 0xD6BA, 0xD6BA, 0xD699, 0xD6BA, 0xBD94, 0xE502, 0xFF12, 0xFF15, 0xFEF4, 0xFF55, 0xFF95, 0xFF54, 0xFF95,   // 0x0C30 (3120)
+0xFF35, 0xFEF4, 0xFF14, 0xFF14, 0xF5A4, 0xB426, 0xE75E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C40 (3136)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD54C, 0xFDA0, 0xFECE, 0xFEF0, 0xFECF, 0xFEEF, 0xFEEF, 0xFEF0, 0xFEEF, 0xFEF0, 0xFEF0,   // 0x0C50 (3152)
+0xFEF0, 0xFEEF, 0xFEF0, 0xFEEF, 0xF582, 0x6244, 0x39E8, 0x39C6, 0x528A, 0xE71C, 0xE73C, 0xE71C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB,   // 0x0C60 (3168)
+0xDEDB, 0xDEDB, 0xD6BA, 0xD6BA, 0xD69A, 0xCE79, 0xCE9A, 0xBD94, 0xE522, 0xFF10, 0xFEF2, 0xFEF2, 0xFEF2, 0xFEF2, 0xFEF2, 0xFEF2,   // 0x0C70 (3184)
+0xFEF2, 0xFF12, 0xFEF2, 0xFEF2, 0xFF12, 0xED85, 0xBC68, 0xE73D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C80 (3200)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD5B0, 0xF580, 0xFECB, 0xFEEE, 0xFECD, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE,   // 0x0C90 (3216)
+0xFEEE, 0xFEEE, 0xFECD, 0xFECE, 0xFECA, 0xCC60, 0x41C7, 0x39C7, 0x4228, 0xCE79, 0xEF5D, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB,   // 0x0CA0 (3232)
+0xDEDB, 0xD6BA, 0xD6BA, 0xD69A, 0xCE79, 0xCE59, 0xCE9A, 0xBD73, 0xED42, 0xFF0F, 0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0,   // 0x0CB0 (3248)
+0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0, 0xFF31, 0xF628, 0xC4A7, 0xDE57, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0CC0 (3264)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDE13, 0xF560, 0xFEC9, 0xFECD, 0xFECC, 0xFECC, 0xFECC, 0xFECC, 0xFECC, 0xFECC, 0xFECC,   // 0x0CD0 (3280)
+0xFEEC, 0xFEEC, 0xFECC, 0xFECC, 0xFEED, 0xFE44, 0x9323, 0x52CC, 0x73AE, 0xD69A, 0xE73C, 0xDEFB, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB,   // 0x0CE0 (3296)
+0xD6BA, 0xD6BA, 0xD69A, 0xCE79, 0xCE59, 0xD69A, 0xB5D8, 0x7B28, 0xF5A2, 0xFF0F, 0xFECE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE,   // 0x0CF0 (3312)
+0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFECD, 0xFF10, 0xFEA9, 0xCC60, 0xD615, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D00 (3328)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDE55, 0xED80, 0xFEA4, 0xFECA, 0xFECA, 0xFECA, 0xFECA, 0xFECA, 0xFECA, 0xFECA, 0xFEC9,   // 0x0D10 (3344)
+0xFEA7, 0xFEA6, 0xFEA8, 0xFEC9, 0xFECB, 0xFEEA, 0xEDA2, 0xB4F0, 0xCE9A, 0xDEFB, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB, 0xD6BA,   // 0x0D20 (3360)
+0xD6BA, 0xD69A, 0xCE79, 0xCE79, 0xD6BA, 0xB596, 0x4A8B, 0x72A4, 0xFE45, 0xFEEC, 0xFECC, 0xFEEC, 0xFEEC, 0xFEEC, 0xFEEC, 0xFEEC,   // 0x0D30 (3376)
+0xFEEC, 0xFECB, 0xFECB, 0xFEEC, 0xFEEC, 0xFEEC, 0xFECC, 0xFEA5, 0xFDE0, 0xAC8B, 0xE75E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D40 (3392)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE632, 0xF5E0, 0xFE80, 0xFE82, 0xFEC7, 0xFEC8, 0xFEC8, 0xFEC8, 0xFEC7, 0xFEA4, 0xFE61,   // 0x0D50 (3408)
+0xFE60, 0xFE60, 0xFE60, 0xFE61, 0xFE83, 0xFEA6, 0xFEA3, 0xDD22, 0xD658, 0xE75D, 0xDEDB, 0xDEDB, 0xDEDB, 0xD6BA, 0xD6BA, 0xD69A,   // 0x0D60 (3424)
+0xD69A, 0xD69A, 0xD6BA, 0xCE59, 0x9492, 0x5289, 0x39E9, 0x9B84, 0xFEA3, 0xFEEB, 0xFEEA, 0xFEEA, 0xFEEA, 0xFEEA, 0xFEEA, 0xFEC8,   // 0x0D70 (3440)
+0xFE84, 0xFE61, 0xFE61, 0xFEA5, 0xFEC9, 0xFEA7, 0xFEA2, 0xFE80, 0xBC41, 0x8C0F, 0xE71C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D80 (3456)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDDCE, 0xFE40, 0xFEA0, 0xFE80, 0xFE80, 0xFEA2, 0xFEA2, 0xFEA2, 0xFEA0, 0xFE80, 0xFE80,   // 0x0D90 (3472)
+0xFEA0, 0xFEA0, 0xFEA0, 0xFE80, 0xFE80, 0xFE80, 0xFE80, 0xFE80, 0xCCE5, 0xD69A, 0xE73C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB,   // 0x0DA0 (3488)
+0xD69A, 0xBDF7, 0x9CD3, 0x630C, 0x4228, 0x4A69, 0x422A, 0xB423, 0xFEC0, 0xFEA5, 0xFEE7, 0xFEC7, 0xFEC7, 0xFEC6, 0xFEA3, 0xFE80,   // 0x0DB0 (3504)
+0xFE80, 0xFE80, 0xFE80, 0xFE60, 0xFEA0, 0xFEC0, 0xEDC0, 0xA3A4, 0x732C, 0xAD96, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0DC0 (3520)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE5A8, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0DD0 (3536)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEE0, 0xF640, 0x93A8, 0x8C72, 0xA534, 0xAD75, 0xA534, 0x9CF3, 0x8C51,   // 0x0DE0 (3552)
+0x738E, 0x5ACB, 0x4A49, 0x4A69, 0x528A, 0x4A8A, 0x5249, 0xD502, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEC1, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0,   // 0x0DF0 (3568)
+0xFEA0, 0xFEA0, 0xFEA0, 0xFEE0, 0xFE60, 0xC482, 0x7B09, 0x7BD0, 0xB5B7, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E00 (3584)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDD8A, 0xFEC0, 0xFF20, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0,   // 0x0E10 (3600)
+0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEC0, 0xFF20, 0xAC02, 0x4209, 0x4A69, 0x4A69, 0x4A69, 0x4A69, 0x4A69,   // 0x0E20 (3616)
+0x528A, 0x528A, 0x52AA, 0x52AA, 0x528A, 0x4A8A, 0x5A69, 0xE5C1, 0xFF00, 0xFEC0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0,   // 0x0E30 (3632)
+0xFEC0, 0xFEE0, 0xFF00, 0xE561, 0x9367, 0x736E, 0x9D14, 0xD6BA, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E40 (3648)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD617, 0xCCC5, 0xF620, 0xFEE0, 0xFF40, 0xFF40, 0xFF40, 0xFF20, 0xFF00, 0xFF00, 0xFF00,   // 0x0E50 (3664)
+0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF40, 0xB483, 0x4A8B, 0x5ACA, 0x5ACB, 0x5ACB, 0x5ACB, 0x5ACB,   // 0x0E60 (3680)
+0x5ACB, 0x52AA, 0x52AA, 0x52AA, 0x52AA, 0x4A8A, 0x6289, 0xEE20, 0xFF20, 0xFEE0, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFEE0,   // 0x0E70 (3696)
+0xFF20, 0xFEC0, 0xBC64, 0x732B, 0x8C72, 0xCE58, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E80 (3712)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7E, 0xB576, 0x93EE, 0xA408, 0xC4A5, 0xDD63, 0xF641, 0xFEC0, 0xFF40, 0xFF80, 0xFF60,   // 0x0E90 (3728)
+0xFF40, 0xFF20, 0xFF20, 0xFF40, 0xFF40, 0xFF40, 0xFF20, 0xFF20, 0xFF80, 0xAC03, 0x4A6B, 0x5ACA, 0x5ACB, 0x5ACB, 0x5AEB, 0x5AEB,   // 0x0EA0 (3744)
+0x5AEB, 0x630C, 0x630C, 0x630C, 0x5AEB, 0x52CB, 0x5A69, 0xE5E1, 0xFF60, 0xFF20, 0xFF20, 0xFF20, 0xFF20, 0xFF20, 0xFF20, 0xFF60,   // 0x0EB0 (3760)
+0xF640, 0xA3A7, 0x738F, 0xAD96, 0xE71C, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0EC0 (3776)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0xD6DB, 0xB5B8, 0x9CD4, 0x9431, 0x93EE, 0x9C0A, 0xB467, 0xD544, 0xF660,   // 0x0ED0 (3792)
+0xFF60, 0xFFA0, 0xFF80, 0xFF60, 0xFF40, 0xFF40, 0xFF60, 0xFFA0, 0xD521, 0x730A, 0x73CF, 0x8C71, 0x9CD3, 0x9CF3, 0xA514, 0xA534,   // 0x0EE0 (3808)
+0xAD55, 0xB596, 0xB5B6, 0xB596, 0xAD55, 0x9CF3, 0x83F0, 0xCD04, 0xFFA0, 0xFF40, 0xFF40, 0xFF40, 0xFF40, 0xFF40, 0xFFA0, 0xF621,   // 0x0EF0 (3824)
+0x8B49, 0x8431, 0xCE58, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F00 (3840)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xF79E, 0xE73C, 0xD6BB, 0xBE19, 0xA556, 0x9472, 0x9C0D,   // 0x0F10 (3856)
+0xB447, 0xDD82, 0xFEE0, 0xFFA0, 0xFFC0, 0xFFC0, 0xFF80, 0xC4C2, 0x730C, 0x9CF4, 0xD69A, 0xEF5D, 0xEF7D, 0xF79E, 0xF79E, 0xF7BE,   // 0x0F20 (3872)
+0xF7BE, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xEF7D, 0xDF1C, 0xC530, 0xF620, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFF80, 0xE5A2, 0x834A,   // 0x0F30 (3888)
+0x8C93, 0xDEDA, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F40 (3904)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDE, 0xEF7D, 0xD6BB,   // 0x0F50 (3920)
+0xAD77, 0x9452, 0x9BEB, 0xB466, 0xC524, 0xC543, 0xA3E5, 0x734D, 0xAD76, 0xEF5C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F60 (3936)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDF1C, 0xACB0, 0xBCA6, 0xD544, 0xCD64, 0xCD05, 0xAC07, 0x7B6D, 0x9CF4,   // 0x0F70 (3952)
+0xE6FB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F80 (3968)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F90 (3984)
+0xFFDE, 0xE75D, 0xC65A, 0xA536, 0x9493, 0x8C53, 0x94B4, 0xBE18, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FA0 (4000)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xDEFC, 0xAD57, 0x9493, 0x8C73, 0x8C73, 0x94D4, 0xBE18, 0xEF5D,   // 0x0FB0 (4016)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FC0 (4032)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FD0 (4048)
+0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xEF5C, 0xE73C, 0xEF5C, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FE0 (4064)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xEF5C, 0xE73C, 0xEF5C, 0xEF7D, 0xFFDE, 0xFFFF,   // 0x0FF0 (4080)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x1000 (4096)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_128x128_Serial/UTFT_Demo_128x128_Serial.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_128x128_Serial/UTFT_Demo_128x128_Serial.ino
new file mode 100644
index 0000000..de371d9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_128x128_Serial/UTFT_Demo_128x128_Serial.ino	
@@ -0,0 +1,335 @@
+// UTFT_Demo_128x128_Serial (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made to work on the 128x128 modules.
+// Any other size displays may cause strange behaviour.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Declare an instance of the class
+UTFT myGLCD(LPH9135,6,5,2,3,4);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD(PORTRAIT);
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  byte buf[126];
+  int x, x2;
+  int y, y2;
+  int r;
+  
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+  myGLCD.setContrast(64);
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0,0,127,12);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0,117,127,127);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255,0,0);
+  myGLCD.print("Universal TFT", CENTER, 0);
+  myGLCD.setBackColor(64,64,64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("H.Karlsen", LEFT, 116);
+  myGLCD.print("(C)2013", RIGHT, 116);
+  myGLCD.setColor(0,255,0);
+  myGLCD.drawRect(0,13,127,116);
+
+// Draw crosshairs
+  myGLCD.setColor(0,0,255);
+  myGLCD.drawLine(63,14,63,115);
+  myGLCD.drawLine(1,63,126,63);
+  for (int i=3; i<128; i+=10)
+    myGLCD.drawLine(i, 61, i, 65);
+  for (int i=14; i<118; i+=10)
+    myGLCD.drawLine(61, i, 65, i);
+  
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.setBackColor(0,0,0);
+  myGLCD.print("Sin", 2, 14);
+  for (int i=1; i<126; i++)
+  {
+    myGLCD.drawPixel(i,63+(sin(((i*2.85)*3.14)/180)*45));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 2, 26);
+  for (int i=1; i<126; i++)
+  {
+    myGLCD.drawPixel(i,63+(cos(((i*2.85)*3.14)/180)*45));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 2, 38);
+  for (int i=1; i<126; i++)
+  {
+    myGLCD.drawPixel(i,63+(tan(((i*2.85)*3.14)/180)));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+  myGLCD.setColor(0,0,255);
+  myGLCD.drawLine(63,14,63,115);
+  myGLCD.drawLine(1,63,126,63);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<3654; i++)
+  {
+    x++;
+    if (x==127)
+      x=1;
+    if (i>127)
+    {
+      if ((x==63)||(buf[x-1]==63))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=63+(sin(((i*1.3)*3.14)/180)*45);
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+    delay(1);
+  }
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+  
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(10+(i*10),10+(i*10), 60+(i*10), 60+(i*10));
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+  
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(70-(i*10),10+(i*10), 120-(i*10), 60+(i*10));
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+  
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(30+(i*10),35+(i*10), 25);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+  // Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=11; i<115; i+=3)
+  {
+    myGLCD.drawLine(1, i, i-10, 115);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=112; i>14; i-=3)
+  {
+    myGLCD.drawLine(126, i, i+14, 14);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=115; i>14; i-=3)
+  {
+    myGLCD.drawLine(1, i, 116-i, 14);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=14; i<115; i+=3)
+  {
+    myGLCD.drawLine(126, i, 140-i, 115);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=22+random(85);
+    y=35+random(59);
+    r=random(20);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(124);
+    y=15+random(101);
+    x2=2+random(124);
+    y2=15+random(101);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(124);
+    y=15+random(101);
+    x2=2+random(124);
+    y2=15+random(101);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random lines
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(124);
+    y=15+random(101);
+    x2=2+random(124);
+    y2=15+random(101);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random pixels
+  for (int i=0; i<5000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(124), 15+random(101));
+  }
+  
+  delay (2000);
+  
+// Set up the "Finished"-screen
+  myGLCD.setContrast(0);
+  myGLCD.fillScr(0,0,255);
+  myGLCD.setColor(255,0,0);
+  myGLCD.fillRoundRect(2, 40, 125, 88);
+  
+  myGLCD.setColor(255,255,255);
+  myGLCD.setBackColor(255,0,0);
+  myGLCD.print("That's it!", CENTER, 46);
+  myGLCD.print("Restarting in a", CENTER, 66);
+  myGLCD.print("few seconds...", CENTER, 76);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.setBackColor(0,0,255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 108);
+  myGLCD.printNumI(millis(), CENTER, 118);
+  
+  myGLCD.setContrast(64);
+  
+  delay (10000);
+  
+// Fade screen to black
+  for (int i=64; i>0; i--)
+  {
+    myGLCD.setContrast(i);
+    delay(100);
+  }
+}
+
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_220x176/UTFT_Demo_220x176.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_220x176/UTFT_Demo_220x176.ino
new file mode 100644
index 0000000..0128930
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_220x176/UTFT_Demo_220x176.ino	
@@ -0,0 +1,322 @@
+// UTFT_Demo_220x176 (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 220x176 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(ITDB22,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[218];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 219, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 162, 219, 175);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("** Universal TFT Library **", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("> elec.henningkarlsen.com <", CENTER, 163);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 219, 161);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(109, 15, 109, 160);
+  myGLCD.drawLine(1, 88, 218, 88);
+
+  for (int i=9; i<210; i+=10)
+    myGLCD.drawLine(i, 86, i, 90);
+  for (int i=19; i<155; i+=10)
+    myGLCD.drawLine(107, i, 111, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(sin(((i*1.65)*3.14)/180)*70));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(cos(((i*1.65)*3.14)/180)*70));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(tan(((i*1.65)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(109, 15, 109, 160);
+  myGLCD.drawLine(1, 88, 218, 88);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(218*20); i++) 
+  {
+    x++;
+    if (x==219)
+      x=1;
+    if (i>219)
+    {
+      if ((x==109)||(buf[x-1]==88))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=88+(sin(((i*1.6)*3.14)/180)*(65-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(44+(i*15), 23+(i*15), 88+(i*15), 63+(i*15));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(132-(i*15), 23+(i*15), 172-(i*15), 63+(i*15));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(64+(i*15),43+(i*15), 20);
+  }
+  
+  delay(2000);
+    
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<160; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 160);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=160; i>15; i-=5)
+  {
+    myGLCD.drawLine(218, i, (i*1.44)-12, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=160; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 232-(i*1.44), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<160; i+=5)
+  {
+    myGLCD.drawLine(218, i, 231-(i*1.44), 160);
+  }
+  
+  delay(2000);
+  
+    myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=22+random(176);
+    y=35+random(105);
+    r=random(20);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(216), 16+random(143));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(40, 57, 179, 119);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 62);
+  myGLCD.print("Restarting in a", CENTER, 88);
+  myGLCD.print("few seconds...", CENTER, 101);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 146);
+  myGLCD.printNumI(millis(), CENTER, 161);
+
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_320x240/UTFT_Demo_320x240.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_320x240/UTFT_Demo_320x240.ino
new file mode 100644
index 0000000..eb6ce23
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_320x240/UTFT_Demo_320x240.ino	
@@ -0,0 +1,321 @@
+// UTFT_Demo_320x240 (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 320x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(ITDB24E_16,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[318];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 319, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 226, 319, 239);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 227);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 319, 225);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+  for (int i=9; i<310; i+=10)
+    myGLCD.drawLine(i, 117, i, 121);
+  for (int i=19; i<220; i+=10)
+    myGLCD.drawLine(157, i, 161, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(sin(((i*1.13)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(cos(((i*1.13)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(tan(((i*1.13)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(318*20); i++) 
+  {
+    x++;
+    if (x==319)
+      x=1;
+    if (i>319)
+    {
+      if ((x==159)||(buf[x-1]==119))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=119+(sin(((i*1.1)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(70+(i*20), 30+(i*20), 130+(i*20), 90+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(190-(i*20), 30+(i*20), 250-(i*20), 90+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(100+(i*20),60+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 224);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(318, i, (i*1.44)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 331-(i*1.44), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(318, i, 330-(i*1.44), 224);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(256);
+    y=45+random(146);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(207);
+    x2=2+random(316);
+    y2=16+random(207);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(207);
+    x2=2+random(316);
+    y2=16+random(207);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(209);
+    x2=2+random(316);
+    y2=16+random(209);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(316), 16+random(209));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(80, 70, 239, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 210);
+  myGLCD.printNumI(millis(), CENTER, 225);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_320x240_Serial/UTFT_Demo_320x240_Serial.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_320x240_Serial/UTFT_Demo_320x240_Serial.ino
new file mode 100644
index 0000000..6781e9b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_320x240_Serial/UTFT_Demo_320x240_Serial.ino	
@@ -0,0 +1,321 @@
+// UTFT_Demo_320x240_Serial (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 320x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(TFT01_22SP,9,8,12,11,10);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[318];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 319, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 226, 319, 239);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 227);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 319, 225);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+  for (int i=9; i<310; i+=10)
+    myGLCD.drawLine(i, 117, i, 121);
+  for (int i=19; i<220; i+=10)
+    myGLCD.drawLine(157, i, 161, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(sin(((i*1.13)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(cos(((i*1.13)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(tan(((i*1.13)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(318*20); i++) 
+  {
+    x++;
+    if (x==319)
+      x=1;
+    if (i>319)
+    {
+      if ((x==159)||(buf[x-1]==119))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=119+(sin(((i*1.1)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(70+(i*20), 30+(i*20), 130+(i*20), 90+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(190-(i*20), 30+(i*20), 250-(i*20), 90+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(100+(i*20),60+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 224);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(318, i, (i*1.44)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 331-(i*1.44), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(318, i, 330-(i*1.44), 224);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(256);
+    y=45+random(146);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(207);
+    x2=2+random(316);
+    y2=16+random(207);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(207);
+    x2=2+random(316);
+    y2=16+random(207);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(209);
+    x2=2+random(316);
+    y2=16+random(209);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(316), 16+random(209));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(80, 70, 239, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 210);
+  myGLCD.printNumI(millis(), CENTER, 225);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_400x240/UTFT_Demo_400x240.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_400x240/UTFT_Demo_400x240.ino
new file mode 100644
index 0000000..133e09e
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_400x240/UTFT_Demo_400x240.ino	
@@ -0,0 +1,323 @@
+// UTFT_Demo_400x240 (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 400x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(ITDB32WD,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[398];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 399, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 226, 399, 239);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("*** Universal Color TFT Display Library ***", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("< http://electronics.henningkarlsen.com >", CENTER, 227);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 399, 225);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(199, 15, 199, 224);
+  myGLCD.drawLine(1, 119, 398, 119);
+  for (int i=9; i<390; i+=10)
+    myGLCD.drawLine(i, 117, i, 121);
+  for (int i=19; i<220; i+=10)
+    myGLCD.drawLine(197, i, 201, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<398; i++)
+  {
+    myGLCD.drawPixel(i,119+(sin(((i*0.9)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<398; i++)
+  {
+    myGLCD.drawPixel(i,119+(cos(((i*0.9)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<398; i++)
+  {
+    y=119+(tan(((i*0.9)*3.14)/180));
+    if ((y>15) && (y<224))
+    myGLCD.drawPixel(i,y);
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(199, 15, 199, 224);
+  myGLCD.drawLine(1, 119, 398, 119);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(398*20); i++) 
+  {
+    x++;
+    if (x==399)
+      x=1;
+    if (i>399)
+    {
+      if ((x==199)||(buf[x-1]==119))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=119+(sin(((i)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(110+(i*20), 30+(i*20), 170+(i*20), 90+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(230-(i*20), 30+(i*20), 290-(i*20), 90+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(110+(i*30),60+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.77)-10, 224);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(398, i, (i*1.77)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 411-(i*1.77), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(398, i, 410-(i*1.77), 224);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(336);
+    y=45+random(146);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(396);
+    y=16+random(207);
+    x2=2+random(396);
+    y2=16+random(207);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(396);
+    y=16+random(207);
+    x2=2+random(396);
+    y2=16+random(207);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(396);
+    y=16+random(209);
+    x2=2+random(396);
+    y2=16+random(209);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(396), 16+random(209));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(120, 70, 279, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 210);
+  myGLCD.printNumI(millis(), CENTER, 225);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_480x272/UTFT_Demo_480x272.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_480x272/UTFT_Demo_480x272.ino
new file mode 100644
index 0000000..ec4c34d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_480x272/UTFT_Demo_480x272.ino	
@@ -0,0 +1,320 @@
+// UTFT_Demo_480x272 (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 480x272 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(ITDB43,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[478];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 479, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 258, 479, 271);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 259);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 479, 257);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(239, 15, 239, 256);
+  myGLCD.drawLine(1, 135, 478, 135);
+  for (int i=9; i<470; i+=10)
+    myGLCD.drawLine(i, 133, i, 138);
+  for (int i=15; i<256; i+=10)
+    myGLCD.drawLine(237, i, 241, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,135+(sin(((i*1.13)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,135+(cos(((i*1.13)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,135+(tan(((i*1.13)*3.14)/180)));
+  }
+
+  delay(2000);
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(239, 15, 239, 256);
+  myGLCD.drawLine(1, 135, 478, 135);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(478*20); i++) 
+  {
+    x++;
+    if (x==479)
+      x=1;
+    if (i>479)
+    {
+      if ((x==239)||(buf[x-1]==135))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=135+(sin(((i*1.65)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(150+(i*20), 46+(i*20), 210+(i*20), 106+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(330-(i*20), 46+(i*20), 270-(i*20), 106+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(180+(i*20),75+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<256; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.88)-10, 256);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=256; i>15; i-=5)
+  {
+    myGLCD.drawLine(478, i, (i*1.88)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=256; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 491-(i*1.88), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<256; i+=5)
+  {
+    myGLCD.drawLine(478, i, 490-(i*1.88), 256);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some random circles
+  for (int i=0; i<150; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(416);
+    y=45+random(178);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some random rectangles
+  for (int i=0; i<150; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(239);
+    x2=2+random(476);
+    y2=16+random(239);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<150; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(239);
+    x2=2+random(476);
+    y2=16+random(239);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+  for (int i=0; i<150; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(239);
+    x2=2+random(476);
+    y2=16+random(239);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(476), 16+random(239));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(160, 70, 319, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 243);
+  myGLCD.printNumI(millis(), CENTER, 258);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_480x320/UTFT_Demo_480x320.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_480x320/UTFT_Demo_480x320.ino
new file mode 100644
index 0000000..604dd06
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_480x320/UTFT_Demo_480x320.ino	
@@ -0,0 +1,321 @@
+// UTFT_Demo_480x320 (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 480x320 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(CTE32HR,25,26,27,28);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[478];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 479, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 306, 479, 319);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 307);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 479, 305);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(239, 15, 239, 304);
+  myGLCD.drawLine(1, 159, 478, 159);
+  for (int i=9; i<470; i+=10)
+    myGLCD.drawLine(i, 157, i, 161);
+  for (int i=19; i<220; i+=10)
+    myGLCD.drawLine(237, i, 241, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,159+(sin(((i*1.13)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,159+(cos(((i*1.13)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,159+(tan(((i*1.13)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(239, 15, 239, 304);
+  myGLCD.drawLine(1, 159, 478, 159);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(478*15); i++) 
+  {
+    x++;
+    if (x==479)
+      x=1;
+    if (i>479)
+    {
+      if ((x==239)||(buf[x-1]==159))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=159+(sin(((i*0.7)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(150+(i*20), 70+(i*20), 210+(i*20), 130+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(270-(i*20), 70+(i*20), 330-(i*20), 130+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(180+(i*20),100+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<304; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.6)-10, 304);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=304; i>15; i-=5)
+  {
+    myGLCD.drawLine(478, i, (i*1.6)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=304; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 491-(i*1.6), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<304; i+=5)
+  {
+    myGLCD.drawLine(478, i, 490-(i*1.6), 304);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(416);
+    y=45+random(226);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(289);
+    x2=2+random(476);
+    y2=16+random(289);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(289);
+    x2=2+random(476);
+    y2=16+random(289);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(289);
+    x2=2+random(476);
+    y2=16+random(289);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(476), 16+random(289));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(160, 70, 319, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 290);
+  myGLCD.printNumI(millis(), CENTER, 305);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_800x480/UTFT_Demo_800x480.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_800x480/UTFT_Demo_800x480.ino
new file mode 100644
index 0000000..8b743fb
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Demo_800x480/UTFT_Demo_800x480.ino	
@@ -0,0 +1,280 @@
+// UTFT_Demo_800x480 (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 800x480 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(ITDB50,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[798];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 799, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 466, 799, 479);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 467);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 799, 465);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(399, 15, 399, 464);
+  myGLCD.drawLine(1, 239, 798, 239);
+  for (int i=9; i<790; i+=10)
+    myGLCD.drawLine(i, 237, i, 242);
+  for (int i=19; i<470; i+=10)
+    myGLCD.drawLine(397, i, 402, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<798; i++)
+  {
+    myGLCD.drawPixel(i,239+(sin(((i*1.13)*3.14)/180)*200));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<798; i++)
+  {
+    myGLCD.drawPixel(i,239+(cos(((i*1.13)*3.14)/180)*200));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<798; i++)
+  {
+    myGLCD.drawPixel(i,239+(tan(((i*0.9)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(399, 15, 399, 464);
+  myGLCD.drawLine(1, 239, 798, 239);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(798*20); i++) 
+  {
+    x++;
+    if (x==799)
+      x=1;
+    if (i>799)
+    {
+      if ((x==399)||(buf[x-1]==239))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=239+(sin(((i*1.65)*3.14)/180)*(200-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random filled rectangles
+  for (int i=0; i<50; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(746);
+    y=16+random(397);
+    x2=x+50;
+    y2=y+50;
+    myGLCD.fillRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random filled, rounded rectangles
+  for (int i=0; i<50; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(746);
+    y=16+random(397);
+    x2=x+50;
+    y2=y+50;
+    myGLCD.fillRoundRect(x, y, x2, y2);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random filled circles
+  for (int i=0; i<50; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=27+random(746);
+    y=41+random(397);
+    myGLCD.fillCircle(x, y, 25);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<463; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.66)-10, 463);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=463; i>15; i-=5)
+  {
+    myGLCD.drawLine(798, i, (i*1.66)+30, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=463; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 770-(i*1.66), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<463; i+=5)
+  {
+    myGLCD.drawLine(798, i, 810-(i*1.66), 463);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random circles
+  for (int i=0; i<250; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(736);
+    y=45+random(386);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random rectangles
+  for (int i=0; i<250; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(796);
+    y=16+random(447);
+    x2=2+random(796);
+    y2=16+random(447);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<250; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(796);
+    y=16+random(447);
+    x2=2+random(796);
+    y2=16+random(447);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+  for (int i=0; i<250; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(796);
+    y=16+random(447);
+    x2=2+random(796);
+    y2=16+random(447);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(796), 16+random(447));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(320, 190, 479, 289);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 213);
+  myGLCD.print("Restarting in a", CENTER, 239);
+  myGLCD.print("few seconds...", CENTER, 252);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 450);
+  myGLCD.printNumI(millis(), CENTER, 465);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Rotate_Bitmap/UTFT_Rotate_Bitmap.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Rotate_Bitmap/UTFT_Rotate_Bitmap.ino
new file mode 100644
index 0000000..3e00580
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Rotate_Bitmap/UTFT_Rotate_Bitmap.ino	
@@ -0,0 +1,29 @@
+// UTFT_Rotate_Bitmap (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the drawBitmap()-function.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+UTFT myGLCD(ITDB24E_16,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+extern unsigned short biohazard[0x1000];
+
+void setup()
+{
+  myGLCD.InitLCD(LANDSCAPE);
+  myGLCD.fillScr(255, 255, 255);
+  myGLCD.setColor(0, 0, 0);
+}
+
+void loop()
+{
+    for (int i=0; i<360; i+=5)
+    {
+      myGLCD.drawBitmap (10, 10, 64, 64, biohazard, i, 32, 32);
+    }
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Rotate_Bitmap/biohazard.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Rotate_Bitmap/biohazard.c
new file mode 100644
index 0000000..ca1348d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Rotate_Bitmap/biohazard.c	
@@ -0,0 +1,264 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: biohazard1_L.png
+// Time generated: 12.06.2011 00:23:59
+// Dimensions    : 64x64 pixels
+// Size          : 8 192 Bytes
+
+const unsigned short biohazard[0x1000] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0010 (16)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0xC638, 0x9492, 0x6B4D, 0x4228, 0x2945, 0x2124, 0x18C3, 0x1082,   // 0x0020 (32)
+0x1082, 0x10A2, 0x18C3, 0x2124, 0x2965, 0x4A49, 0x6B6D, 0x9CD3, 0xCE79, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0030 (48)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0050 (80)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xBDD7, 0x6B6D, 0x2965, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0060 (96)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0841, 0x31A6, 0x73AE, 0xC618, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0070 (112)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0090 (144)
+0xFFFF, 0xFFFF, 0xE73C, 0x8C71, 0x3186, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0020, 0x0020, 0x0000, 0x0000,   // 0x00A0 (160)
+0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x4207, 0x9CF3, 0xF79E, 0xFFFF,   // 0x00B0 (176)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00D0 (208)
+0xEF7D, 0x8C51, 0x2104, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x00E0 (224)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x2965, 0x9CD3,   // 0x00F0 (240)
+0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAD75,   // 0x0110 (272)
+0x2965, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0000, 0x0000, 0x0000, 0x0020, 0x2901, 0x5241, 0x7B41, 0x9C02, 0xACA2, 0xBD02,   // 0x0120 (288)
+0xC521, 0xBD02, 0xACA2, 0x9C22, 0x7B41, 0x5241, 0x2901, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0130 (304)
+0x39E7, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xEF5D, 0x630C, 0x0000,   // 0x0150 (336)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x41C1, 0x93E1, 0xD5A1, 0xFEA1, 0xFF01, 0xFF20, 0xFF20, 0xFF20, 0xFF00,   // 0x0160 (352)
+0xFF00, 0xFF00, 0xFF20, 0xFF20, 0xFF20, 0xFF01, 0xFEA1, 0xD5A1, 0x93E1, 0x49E1, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0170 (368)
+0x0000, 0x0841, 0x7BEF, 0xF7BE, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0180 (384)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xC638, 0x2965, 0x0000, 0x0000,   // 0x0190 (400)
+0x0000, 0x0000, 0x0000, 0x0000, 0x18A0, 0x7B41, 0xD5A1, 0xFF01, 0xFF20, 0xFEE0, 0xFEC0, 0xFEA0, 0xF680, 0xF680, 0xFEA0, 0xFEA0,   // 0x01A0 (416)
+0xFEA0, 0xFEA0, 0xFEA0, 0xF680, 0xF680, 0xFEA0, 0xFEC0, 0xFF00, 0xFF20, 0xFF01, 0xD5A1, 0x7B41, 0x1880, 0x0000, 0x0000, 0x0000,   // 0x01B0 (432)
+0x0000, 0x0000, 0x0000, 0x4208, 0xDEDB, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01C0 (448)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAD55, 0x1082, 0x0000, 0x0000, 0x0000,   // 0x01D0 (464)
+0x0000, 0x0000, 0x0840, 0x7B62, 0xEE41, 0xFF21, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF20, 0xFF20, 0xFEA1, 0xFEC0,   // 0x01E0 (480)
+0xFEC0, 0xFEC0, 0xFEA1, 0xFF00, 0xFF20, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEE0, 0xFF21, 0xEE41, 0x7B62, 0x0840, 0x0000,   // 0x01F0 (496)
+0x0000, 0x0000, 0x0000, 0x0000, 0x18E3, 0xC618, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0200 (512)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B2, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0210 (528)
+0x0000, 0x5201, 0xDDE1, 0xFF21, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF40, 0xF6A1, 0xB4C1, 0x7322, 0xA441, 0xFEE0,   // 0x0220 (544)
+0xFEA0, 0xFEE0, 0xA461, 0x7322, 0xACA1, 0xF681, 0xFF40, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF21, 0xDDE2, 0x4A01,   // 0x0230 (560)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1082, 0xB596, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0240 (576)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x9492, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0820,   // 0x0250 (592)
+0x9402, 0xFF01, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEE0, 0xFF01, 0x9401, 0x3961, 0x7341, 0xCD81, 0xF680, 0xFEC0,   // 0x0260 (608)
+0xFEA0, 0xFEC0, 0xF681, 0xCD81, 0x7B61, 0x3961, 0x8BE1, 0xFEE1, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEE0, 0xFF01,   // 0x0270 (624)
+0x9402, 0x0820, 0x0000, 0x0000, 0x0000, 0x0000, 0x0841, 0xB596, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0280 (640)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xA534, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x20C0, 0xCD61,   // 0x0290 (656)
+0xFF40, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF01, 0xE621, 0x39A1, 0x20E1, 0xCD81, 0xFF40, 0xFEE0, 0xFEC0, 0xFEC0,   // 0x02A0 (672)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEE0, 0xFF41, 0xCDC1, 0x2901, 0x3961, 0xDE01, 0xFF00, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEA0,   // 0x02B0 (688)
+0xFF21, 0xC561, 0x18A1, 0x0000, 0x0000, 0x0000, 0x0000, 0x1082, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xC618, 0x0861, 0x0000, 0x0000, 0x0000, 0x0000, 0x3121, 0xDE01, 0xFF00,   // 0x02D0 (720)
+0xFE80, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF01, 0xD5A2, 0x18A0, 0x20E0, 0xF682, 0xFF01, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x02E0 (736)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF00, 0xF6A1, 0x2920, 0x1080, 0xCDA2, 0xFF01, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x02F0 (752)
+0xFE80, 0xFF00, 0xDE01, 0x2921, 0x0000, 0x0000, 0x0000, 0x0000, 0x18E3, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73C, 0x2124, 0x0000, 0x0000, 0x0000, 0x0000, 0x2921, 0xEE41, 0xFF00, 0xFEA0,   // 0x0310 (784)
+0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEE0, 0xDE02, 0x18A1, 0x0840, 0xDDE1, 0xFF00, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x0320 (800)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEE0, 0xE621, 0x0860, 0x1880, 0xD5E2, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0330 (816)
+0xFEA0, 0xFEA0, 0xFF00, 0xE641, 0x2921, 0x0000, 0x0000, 0x0000, 0x0000, 0x4208, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x5ACB, 0x0000, 0x0000, 0x0000, 0x0000, 0x18C0, 0xDE21, 0xFF00, 0xFEA0, 0xFEC0,   // 0x0350 (848)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC1, 0x39A1, 0x0000, 0x8382, 0xFF21, 0xFE80, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0360 (864)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFE80, 0xFF20, 0x8BC1, 0x0000, 0x3161, 0xF6A1, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0370 (880)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFF00, 0xDE01, 0x18A0, 0x0000, 0x0000, 0x0000, 0x0000, 0x7BCF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xA534, 0x0000, 0x0000, 0x0000, 0x0000, 0x0820, 0xCD61, 0xFF00, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x0390 (912)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF21, 0x93E1, 0x0000, 0x1060, 0xDE01, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x03A0 (928)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEE0, 0xE621, 0x1080, 0x0000, 0x8BA1, 0xFF20, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x03B0 (944)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF00, 0xCD61, 0x0820, 0x0000, 0x0000, 0x0000, 0x0021, 0xBDF7, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF5D, 0x2104, 0x0000, 0x0000, 0x0000, 0x0000, 0x9402, 0xFF41, 0xFE80, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x03D0 (976)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0, 0xF681, 0x20E0, 0x0000, 0x41A1, 0xFEE1, 0xFEA0, 0xFEA1, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x03E0 (992)
+0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF01, 0x49E1, 0x0000, 0x18A1, 0xEE41, 0xFEC0, 0xFEA0, 0xFEC0,   // 0x03F0 (1008)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFE80, 0xFF41, 0x9402, 0x0000, 0x0000, 0x0000, 0x0000, 0x39C7, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x7BCF, 0x0000, 0x0000, 0x0000, 0x0000, 0x4A01, 0xFF01, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0410 (1040)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFF20, 0xA461, 0x0000, 0x0000, 0x6AC1, 0xFF21, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x0420 (1056)
+0xFEE0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFE80, 0xFF20, 0x7300, 0x0000, 0x0000, 0x9C21, 0xFF20, 0xFEA0, 0xFEC0,   // 0x0430 (1072)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFF01, 0x49E1, 0x0000, 0x0000, 0x0000, 0x0000, 0x9CD3, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0440 (1088)
+0xFFFF, 0xFFFF, 0xFFFF, 0xDEFB, 0x10A2, 0x0000, 0x0000, 0x0000, 0x0840, 0xDDE1, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0450 (1104)
+0xFEA0, 0xFEA0, 0xFEA0, 0xFF20, 0x6261, 0x0000, 0x0000, 0x7300, 0xFF21, 0xF6A0, 0xFEA0, 0xFEE0, 0xFF20, 0xFF00, 0xFEA1, 0xEE42,   // 0x0460 (1120)
+0xE602, 0xEE42, 0xFEA1, 0xFF00, 0xFF20, 0xFEE0, 0xFEA0, 0xF681, 0xFF40, 0x8360, 0x0000, 0x0000, 0x5241, 0xFF01, 0xFEA0, 0xFEA0,   // 0x0470 (1136)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF00, 0xDDC1, 0x0840, 0x0000, 0x0000, 0x0000, 0x2945, 0xEF7D, 0xFFFF, 0xFFFF,   // 0x0480 (1152)
+0xFFFF, 0xFFDF, 0xFFFF, 0x7BEF, 0x0000, 0x0000, 0x0000, 0x0000, 0x7B42, 0xFF21, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0490 (1168)
+0xFEC0, 0xFEA0, 0xFEC0, 0xFEA0, 0x2900, 0x0000, 0x0000, 0x6AE0, 0xFF21, 0xFEC0, 0xFF01, 0xDE01, 0x9C01, 0x5241, 0x2921, 0x18A1,   // 0x04A0 (1184)
+0x1061, 0x1881, 0x2921, 0x5241, 0x9C02, 0xDDE1, 0xFF21, 0xFEC0, 0xFF20, 0x7321, 0x0000, 0x0000, 0x20E0, 0xF681, 0xFEC0, 0xFEA0,   // 0x04B0 (1200)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF21, 0x7B41, 0x0000, 0x0000, 0x0000, 0x0000, 0x9CD3, 0xFFFF, 0xFFDF,   // 0x04C0 (1216)
+0xFFDF, 0xFFFF, 0xEF7D, 0x2104, 0x0000, 0x0000, 0x0000, 0x1080, 0xEE41, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x04D0 (1232)
+0xFEC0, 0xFEA0, 0xFEC0, 0xEE21, 0x1060, 0x0000, 0x0000, 0x41C1, 0xFF21, 0xDDE1, 0x6AC1, 0x0860, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x04E0 (1248)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0860, 0x62C1, 0xDDC1, 0xFF41, 0x49E1, 0x0000, 0x0000, 0x0840, 0xE601, 0xFEE0, 0xFEA0,   // 0x04F0 (1264)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0, 0xEE41, 0x1080, 0x0000, 0x0000, 0x0000, 0x39C7, 0xF7BE, 0xFFFF,   // 0x0500 (1280)
+0xFFDF, 0xFFFF, 0xA534, 0x0000, 0x0000, 0x0000, 0x0000, 0x7B21, 0xFF21, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0510 (1296)
+0xFEA0, 0xFEA0, 0xFEE0, 0xE602, 0x0841, 0x0000, 0x0000, 0x1080, 0xACC2, 0x1060, 0x0000, 0x0000, 0x0000, 0x0020, 0x2920, 0x4A01,   // 0x0520 (1312)
+0x5241, 0x4A01, 0x3140, 0x0821, 0x0000, 0x0000, 0x0000, 0x0860, 0xACA2, 0x18A0, 0x0000, 0x0000, 0x0820, 0xDDE2, 0xFEE0, 0xFEA0,   // 0x0530 (1328)
+0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFE80, 0xFF21, 0x7321, 0x0000, 0x0000, 0x0000, 0x0020, 0xC618, 0xFFFF,   // 0x0540 (1344)
+0xFFFF, 0xFFFF, 0x52AA, 0x0000, 0x0020, 0x0000, 0x0820, 0xDDA1, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0550 (1360)
+0xFEC0, 0xFEA0, 0xFEE0, 0xE621, 0x1060, 0x0000, 0x0000, 0x0000, 0x6AE2, 0x20C1, 0x0000, 0x20E1, 0x8BA2, 0xD5A1, 0xFEA1, 0xFF00,   // 0x0560 (1376)
+0xFF01, 0xFF00, 0xFEC1, 0xD5C1, 0x8BC2, 0x2901, 0x0000, 0x18A1, 0x7302, 0x0000, 0x0000, 0x0000, 0x0840, 0xDE01, 0xFEE0, 0xFEA0,   // 0x0570 (1392)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEE0, 0xD5A1, 0x0020, 0x0000, 0x0000, 0x0000, 0x738E, 0xFFFF,   // 0x0580 (1408)
+0xFFFF, 0xE71C, 0x18C3, 0x0000, 0x0020, 0x0000, 0x49C1, 0xFF01, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0590 (1424)
+0xFEA0, 0xFEA0, 0xFEC0, 0xF661, 0x18A0, 0x0000, 0x0000, 0x0000, 0x2101, 0x8363, 0x7321, 0xEE81, 0xFF21, 0xFEE0, 0xFEC0, 0xFEA0,   // 0x05A0 (1440)
+0xFEA0, 0xFEA0, 0xFEC0, 0xFEE0, 0xFF20, 0xF681, 0x7B41, 0x8362, 0x2921, 0x0000, 0x0000, 0x0000, 0x1080, 0xEE41, 0xFEC0, 0xFEA0,   // 0x05B0 (1456)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFF01, 0x41C1, 0x0000, 0x0020, 0x0000, 0x3186, 0xF79E,   // 0x05C0 (1472)
+0xFFFF, 0xAD75, 0x0000, 0x0000, 0x0020, 0x0000, 0x93E1, 0xFF20, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0,   // 0x05D0 (1488)
+0xFEC0, 0xFEA0, 0xFEA0, 0xFF41, 0x5221, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0xFF01, 0xFF00, 0xF660, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x05E0 (1504)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xF660, 0xFF00, 0xFF22, 0x49E1, 0x0000, 0x0000, 0x0000, 0x0000, 0x49E1, 0xFF40, 0xFEA0, 0xFEA0,   // 0x05F0 (1520)
+0xFEA1, 0xFEC0, 0xFEA1, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF20, 0x93E1, 0x0000, 0x0020, 0x0000, 0x0020, 0xC638,   // 0x0600 (1536)
+0xFFFF, 0x73AE, 0x0000, 0x0000, 0x0000, 0x0020, 0xD5A1, 0xFF00, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA1, 0xFEA0,   // 0x0610 (1552)
+0xFEA1, 0xFF20, 0xFEC1, 0xD5C1, 0x5220, 0x0000, 0x0000, 0x0000, 0x0020, 0x0000, 0x3981, 0xE622, 0xFF20, 0xFEC0, 0xFEA0, 0xFEA0,   // 0x0620 (1568)
+0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF21, 0xE621, 0x41C1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x49E0, 0xCDA2, 0xFEA1, 0xFF20,   // 0x0630 (1584)
+0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF00, 0xD5A1, 0x0020, 0x0000, 0x0000, 0x0000, 0x9492,   // 0x0640 (1600)
+0xFFFF, 0x4A49, 0x0000, 0x0020, 0x0000, 0x2901, 0xFEA1, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEE0,   // 0x0650 (1616)
+0xFEE1, 0xA461, 0x3981, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1881, 0x93E1, 0xE622, 0xFF01, 0xFF00,   // 0x0660 (1632)
+0xFEA0, 0xFF00, 0xFF21, 0xEE41, 0x9401, 0x18A1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3141, 0x9C21,   // 0x0670 (1648)
+0xFEC1, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEA1, 0x2901, 0x0000, 0x0020, 0x0000, 0x632C,   // 0x0680 (1664)
+0xE71C, 0x2124, 0x0000, 0x0020, 0x0000, 0x5241, 0xFF01, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF00, 0xD5C1,   // 0x0690 (1680)
+0x41C1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1081, 0x4A01, 0xAC81,   // 0x06A0 (1696)
+0xFF21, 0xB4C1, 0x5221, 0x1081, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x06B0 (1712)
+0x3981, 0xCD81, 0xFF21, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF01, 0x5221, 0x0000, 0x0020, 0x0000, 0x4228,   // 0x06C0 (1728)
+0xBDF7, 0x18C3, 0x0000, 0x0020, 0x0000, 0x7B41, 0xFF20, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF20, 0xBD02, 0x1060,   // 0x06D0 (1744)
+0x0000, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x5201,   // 0x06E0 (1760)
+0xFFC0, 0x5A41, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020,   // 0x06F0 (1776)
+0x0000, 0x0840, 0xACA1, 0xFF21, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF20, 0x7B41, 0x0000, 0x0020, 0x0000, 0x2945,   // 0x0700 (1792)
+0x94B2, 0x0861, 0x0000, 0x0000, 0x0000, 0x9C02, 0xFF20, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF00, 0xBD22, 0x0820, 0x0000,   // 0x0710 (1808)
+0x0820, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1881, 0xAC81,   // 0x0720 (1824)
+0xFF20, 0xB4A1, 0x18A1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0730 (1840)
+0x0020, 0x0000, 0x0000, 0xB4C2, 0xFF00, 0xFE80, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF20, 0x9C02, 0x0000, 0x0020, 0x0000, 0x2104,   // 0x0740 (1856)
+0x73AE, 0x0841, 0x0000, 0x0000, 0x0000, 0xACA2, 0xFF20, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEE0, 0xE622, 0x18A1, 0x0000, 0x0000,   // 0x0750 (1872)
+0x0000, 0x1080, 0x5221, 0x6B03, 0x6AE2, 0x6AE3, 0x4A01, 0x1080, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1061, 0xCD82, 0xFF20,   // 0x0760 (1888)
+0xFE80, 0xFF20, 0xD5C2, 0x1881, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1080, 0x5241, 0x6AE3, 0x6AE2, 0x6AE3, 0x5A62, 0x18C0,   // 0x0770 (1904)
+0x0000, 0x0000, 0x0000, 0x1060, 0xDDE2, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF20, 0xACA2, 0x0000, 0x0000, 0x0000, 0x10A2,   // 0x0780 (1920)
+0x52AA, 0x0000, 0x0000, 0x0000, 0x0000, 0xBD02, 0xFF00, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF01, 0x5A61, 0x0000, 0x0000, 0x18A0,   // 0x0790 (1936)
+0x9401, 0xEE61, 0xFEE2, 0x49E2, 0x18A1, 0x62A1, 0xFF41, 0xE621, 0x8BC2, 0x1880, 0x0000, 0x0820, 0x0000, 0x7B21, 0xFF40, 0xFE80,   // 0x07A0 (1952)
+0xFEC0, 0xFE80, 0xFF40, 0x8381, 0x0000, 0x0820, 0x0000, 0x1080, 0x8BE2, 0xEE41, 0xFF41, 0x62A2, 0x10A1, 0x3982, 0xFEC2, 0xF6A1,   // 0x07B0 (1968)
+0xA462, 0x2101, 0x0000, 0x0000, 0x49E1, 0xFF01, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF00, 0xBD02, 0x0000, 0x0000, 0x0000, 0x1082,   // 0x07C0 (1984)
+0x528A, 0x0000, 0x0000, 0x0000, 0x0000, 0xC521, 0xFF00, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF00, 0xCD41, 0x0000, 0x0000, 0x49C1, 0xE642,   // 0x07D0 (2000)
+0xFF21, 0xFEE0, 0xEE42, 0x1081, 0x0000, 0x41A0, 0xFEE0, 0xFEC0, 0xFF40, 0xE621, 0x41A1, 0x0000, 0x0000, 0x93E1, 0xFF20, 0xFEA0,   // 0x07E0 (2016)
+0xFEA0, 0xFEA0, 0xFF20, 0x9C22, 0x0000, 0x0000, 0x3981, 0xDE01, 0xFF21, 0xFEC0, 0xFEE1, 0x49E1, 0x0000, 0x0840, 0xE602, 0xFEC0,   // 0x07F0 (2032)
+0xFF20, 0xEE81, 0x5A61, 0x0000, 0x0000, 0xBCE1, 0xFF00, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF00, 0xC521, 0x0000, 0x0000, 0x0000, 0x1082,   // 0x0800 (2048)
+0x52AA, 0x0000, 0x0000, 0x0000, 0x0000, 0xBD02, 0xFF00, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF20, 0x6AC1, 0x0000, 0x49E1, 0xFEE2, 0xFEE0,   // 0x0810 (2064)
+0xFE80, 0xFEC0, 0xF682, 0x20E1, 0x0000, 0x39A0, 0xFEE0, 0xFEA0, 0xFE80, 0xFEE0, 0xF6A2, 0x41A1, 0x3961, 0xDDC1, 0xFF00, 0xFE80,   // 0x0820 (2080)
+0xFEA0, 0xFEA0, 0xFF00, 0xE601, 0x41C1, 0x3981, 0xF682, 0xFF00, 0xFE80, 0xFEA0, 0xFF00, 0x41C1, 0x0000, 0x20C1, 0xF661, 0xFEC0,   // 0x0830 (2096)
+0xF6A0, 0xFEC0, 0xFF01, 0x6261, 0x0000, 0x5A41, 0xFF01, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF00, 0xBD02, 0x0000, 0x0000, 0x0000, 0x1082,   // 0x0840 (2112)
+0x738E, 0x0841, 0x0000, 0x0000, 0x0000, 0xACA2, 0xFF20, 0xFEA0, 0xFEA0, 0xFEC0, 0xF681, 0x18A0, 0x1080, 0xEE41, 0xFEE0, 0xFEA0,   // 0x0850 (2128)
+0xFEC0, 0xFEA0, 0xFEE1, 0x3980, 0x0000, 0x20C0, 0xF662, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEE0, 0xF681, 0xFEE1, 0xFF01, 0xDDC1, 0xFF21,   // 0x0860 (2144)
+0xFF20, 0xFF21, 0xDDC1, 0xFEC1, 0xFF01, 0xF661, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA1, 0x2900, 0x0000, 0x3140, 0xFEA1, 0xFEA0,   // 0x0870 (2160)
+0xFEA0, 0xFEA0, 0xFEC0, 0xF6A1, 0x2101, 0x0840, 0xEE41, 0xFEE0, 0xFEA0, 0xFEA0, 0xFF20, 0xAC82, 0x0000, 0x0000, 0x0000, 0x10A2,   // 0x0880 (2176)
+0x9492, 0x0861, 0x0000, 0x0000, 0x0000, 0x9C02, 0xFF20, 0xFEA0, 0xFEA0, 0xFF00, 0xD582, 0x0000, 0x93C1, 0xFF40, 0xFE80, 0xFEC0,   // 0x0890 (2192)
+0xFEC0, 0xFEA0, 0xFF21, 0x6AC1, 0x0000, 0x0000, 0xCD41, 0xFF00, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEE0, 0xDDE1, 0x41A1, 0x0860, 0x6AC1,   // 0x08A0 (2208)
+0x93E1, 0x6AE1, 0x0841, 0x3161, 0xD5C1, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF00, 0xCD61, 0x0000, 0x0000, 0x5A81, 0xFF21, 0xFEA0,   // 0x08B0 (2224)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFF20, 0xAC81, 0x0000, 0xC521, 0xFF00, 0xFEA0, 0xFEA0, 0xFF20, 0x9C02, 0x0000, 0x0020, 0x0000, 0x2104,   // 0x08C0 (2240)
+0xB5B6, 0x10A2, 0x0000, 0x0020, 0x0000, 0x7B41, 0xFF20, 0xFEA0, 0xFEA0, 0xFF20, 0xAC80, 0x0820, 0xEE41, 0xFEC0, 0xFEA0, 0xFEC0,   // 0x08D0 (2256)
+0xFEC0, 0xFEA0, 0xFF00, 0xAC81, 0x0000, 0x0000, 0x7301, 0xFF20, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEE0, 0xD5C1, 0x0000, 0x0000, 0x0000,   // 0x08E0 (2272)
+0x0000, 0x0000, 0x0000, 0x0000, 0xD561, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF41, 0x7B42, 0x0000, 0x0000, 0xA442, 0xFF21, 0xFEA0,   // 0x08F0 (2288)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA1, 0x1080, 0x9C00, 0xFF40, 0xFEA0, 0xFEA0, 0xFF20, 0x7B41, 0x0000, 0x0020, 0x0000, 0x2124,   // 0x0900 (2304)
+0xDEFB, 0x2104, 0x0000, 0x0020, 0x0000, 0x5221, 0xFF01, 0xFEA0, 0xFEA0, 0xFF40, 0x93C0, 0x3961, 0xFF21, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x0910 (2320)
+0xFEC0, 0xFEA0, 0xFEC0, 0xEE61, 0x1881, 0x0000, 0x1080, 0xEE21, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF01, 0x41C1, 0x0000, 0x0020,   // 0x0920 (2336)
+0x0000, 0x0020, 0x0000, 0x3961, 0xFEE1, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEC0, 0xEE61, 0x18A1, 0x0000, 0x1060, 0xE621, 0xFEC0, 0xFEA0,   // 0x0930 (2352)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF21, 0x4A01, 0x8361, 0xFF40, 0xFEA0, 0xFEA0, 0xFF01, 0x5221, 0x0000, 0x0020, 0x0000, 0x4208,   // 0x0940 (2368)
+0xFFDF, 0x4208, 0x0000, 0x0000, 0x0000, 0x2901, 0xFEA1, 0xFEC0, 0xFEA0, 0xFF40, 0x93C0, 0x5A60, 0xFF41, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x0950 (2384)
+0xFEA0, 0xFEC0, 0xFEA0, 0xFF21, 0x7B41, 0x0000, 0x0000, 0x6281, 0xFF21, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF21, 0x62A1, 0x0000, 0x0000,   // 0x0960 (2400)
+0x0000, 0x0000, 0x0000, 0x5A41, 0xFF01, 0xFEA0, 0xFEA0, 0xF680, 0xFF41, 0x6AC1, 0x0000, 0x0000, 0x7301, 0xFF21, 0xFEA0, 0xFEA0,   // 0x0970 (2416)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF40, 0x6AE1, 0x8361, 0xFF40, 0xFEA0, 0xFEC0, 0xFEA1, 0x2901, 0x0000, 0x0020, 0x0000, 0x630C,   // 0x0980 (2432)
+0xFFFF, 0x6B6D, 0x0000, 0x0020, 0x0000, 0x0020, 0xD5A1, 0xFF00, 0xFEA0, 0xFF20, 0xA461, 0x6AC0, 0xFF40, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x0990 (2448)
+0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xEE61, 0x18C0, 0x0000, 0x0000, 0x93E2, 0xFF41, 0xFEA0, 0xFE80, 0xFF20, 0x6AE1, 0x0000, 0x0000,   // 0x09A0 (2464)
+0x0000, 0x0000, 0x0000, 0x62A1, 0xFF21, 0xFE80, 0xFEA0, 0xFF40, 0x9C22, 0x0000, 0x0000, 0x1881, 0xE641, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x09B0 (2480)
+0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF40, 0x7B61, 0x9C00, 0xFF40, 0xFE80, 0xFF00, 0xD581, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C51,   // 0x09C0 (2496)
+0xFFFF, 0xA534, 0x0000, 0x0000, 0x0000, 0x0000, 0x93E1, 0xFF20, 0xFE80, 0xFF00, 0xC541, 0x72E1, 0xFF20, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x09D0 (2512)
+0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF00, 0xB4C1, 0x0000, 0x0020, 0x0000, 0x93E1, 0xFF21, 0xFEC0, 0xFF01, 0x5A81, 0x0000, 0x0000,   // 0x09E0 (2528)
+0x0000, 0x0000, 0x0000, 0x5222, 0xFF01, 0xFEC0, 0xFF21, 0x9C01, 0x0000, 0x0020, 0x0000, 0xAC81, 0xFF01, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x09F0 (2544)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF20, 0x7B40, 0xBD01, 0xFF20, 0xF680, 0xFF20, 0x93C1, 0x0000, 0x0020, 0x0000, 0x0000, 0xBDF7,   // 0x0A00 (2560)
+0xFFFF, 0xDEDB, 0x1082, 0x0000, 0x0000, 0x0000, 0x41C1, 0xFF01, 0xFEA0, 0xFEC0, 0xF660, 0x6AC2, 0xF6A1, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0A10 (2576)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF21, 0x8BA1, 0x0000, 0x0000, 0x0000, 0x6281, 0xDE21, 0xFF01, 0x3161, 0x0000, 0x0000,   // 0x0A20 (2592)
+0x0000, 0x0000, 0x0000, 0x2921, 0xFEE1, 0xE641, 0x62A1, 0x0000, 0x0000, 0x0000, 0x8381, 0xFF21, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0A30 (2608)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEC1, 0x6AC2, 0xE621, 0xFEE0, 0xFEA0, 0xFF01, 0x41C1, 0x0000, 0x0020, 0x0000, 0x2124, 0xEF5D,   // 0x0A40 (2624)
+0xFFFF, 0xFFFF, 0x4A49, 0x0000, 0x0000, 0x0000, 0x0020, 0xD5A1, 0xFEE0, 0xFEA0, 0xFEC0, 0xCD41, 0xF660, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0A50 (2640)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFF21, 0x8BC1, 0x0000, 0x0000, 0x0000, 0x1060, 0xA442, 0x0860, 0x0000, 0x0000,   // 0x0A60 (2656)
+0x0000, 0x0000, 0x0000, 0x0820, 0xA442, 0x18A0, 0x0000, 0x0000, 0x0000, 0x8381, 0xFF21, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0A70 (2672)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFE80, 0xCD62, 0xFEC0, 0xFEA1, 0xFEE0, 0xD5A1, 0x0020, 0x0000, 0x0000, 0x0000, 0x630C, 0xFFFF,   // 0x0A80 (2688)
+0xFFDF, 0xFFFF, 0x94B2, 0x0000, 0x0000, 0x0000, 0x0000, 0x7321, 0xFF21, 0xFEA0, 0xFEA0, 0xFEE0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x0A90 (2704)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFF21, 0xB4C1, 0x20E1, 0x0000, 0x3161, 0x62A2, 0x0000, 0x0000, 0x0000,   // 0x0AA0 (2720)
+0x0000, 0x0000, 0x0000, 0x0000, 0x5A82, 0x39A1, 0x0000, 0x20C1, 0xAC82, 0xFF21, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0AB0 (2736)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEE0, 0xFEA0, 0xFEA0, 0xFF21, 0x7321, 0x0000, 0x0000, 0x0000, 0x0000, 0xB596, 0xFFFF,   // 0x0AC0 (2752)
+0xFFDF, 0xFFFF, 0xE73C, 0x18C3, 0x0000, 0x0000, 0x0000, 0x1080, 0xEE41, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA1, 0xFF00, 0xFEE0, 0xFEA0,   // 0x0AD0 (2768)
+0xFEC0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF00, 0xEE41, 0x83C1, 0x8BA3, 0x1081, 0x0000, 0x0000, 0x0000,   // 0x0AE0 (2784)
+0x0000, 0x0000, 0x0000, 0x0000, 0x1060, 0x8383, 0x83A1, 0xEE41, 0xFF00, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0,   // 0x0AF0 (2800)
+0xFEC0, 0xFEA0, 0xFEC0, 0xFF00, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xEE21, 0x1080, 0x0000, 0x0000, 0x0000, 0x2945, 0xEF7D, 0xFFFF,   // 0x0B00 (2816)
+0xFFFF, 0xFFFF, 0xFFFF, 0x6B4D, 0x0000, 0x0000, 0x0000, 0x0000, 0x7B41, 0xFF21, 0xFEA0, 0xFEA0, 0xFF00, 0xB482, 0xD5C1, 0xFF20,   // 0x0B10 (2832)
+0xFE80, 0xFEA0, 0xFEA0, 0xFEA1, 0xFEA0, 0xFEC0, 0xFEA1, 0xFEA0, 0xF680, 0xFF20, 0xF6A2, 0x3121, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0B20 (2848)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x20E1, 0xEE62, 0xFF40, 0xF680, 0xFEA0, 0xFEA1, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0,   // 0x0B30 (2864)
+0xF681, 0xFF20, 0xE601, 0xAC62, 0xFF00, 0xFEA0, 0xFE80, 0xFF21, 0x7B41, 0x0000, 0x0000, 0x0000, 0x0000, 0x8410, 0xFFFF, 0xFFFF,   // 0x0B40 (2880)
+0xFFFF, 0xFFDF, 0xFFFF, 0xD69A, 0x0841, 0x0000, 0x0000, 0x0000, 0x0840, 0xDDC1, 0xFEE0, 0xFEA0, 0xFEE1, 0xD5A1, 0x5221, 0xBD21,   // 0x0B50 (2896)
+0xFF41, 0xFF00, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA1, 0xFEC0, 0xFF00, 0xFF21, 0xCD61, 0x20E1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020,   // 0x0B60 (2912)
+0x7322, 0x0840, 0x0000, 0x0000, 0x0000, 0x0000, 0x18A1, 0xBD22, 0xFF21, 0xFF00, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEE0,   // 0x0B70 (2928)
+0xFF40, 0xC561, 0x5221, 0xCD81, 0xFEE0, 0xFE81, 0xFEE0, 0xDDC1, 0x0840, 0x0000, 0x0000, 0x0000, 0x18E3, 0xE71C, 0xFFFF, 0xFFFF,   // 0x0B80 (2944)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x632C, 0x0000, 0x0000, 0x0000, 0x0000, 0x49E1, 0xFF01, 0xFEA0, 0xFEA0, 0xFF00, 0xDE01, 0x4181,   // 0x0B90 (2960)
+0x5A81, 0xD581, 0xFEE1, 0xFF20, 0xFF20, 0xFF01, 0xFEC1, 0xD582, 0x6AE1, 0x0020, 0x0000, 0x0020, 0x0000, 0x0000, 0x1060, 0xACA2,   // 0x0BA0 (2976)
+0xFF61, 0xBD21, 0x18A1, 0x0000, 0x0000, 0x0020, 0x0000, 0x0000, 0x62A2, 0xCD62, 0xFEA1, 0xFF01, 0xFF20, 0xFF20, 0xFEE1, 0xD5C1,   // 0x0BB0 (2992)
+0x62C1, 0x3981, 0xD5C1, 0xFF21, 0xFEA0, 0xFEA0, 0xFF01, 0x49E1, 0x0000, 0x0000, 0x0000, 0x0000, 0x7BEF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0BC0 (3008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDB, 0x1082, 0x0000, 0x0000, 0x0000, 0x0000, 0x93E2, 0xFF40, 0xFE80, 0xFE80, 0xFEE0, 0xFEC1,   // 0x0BD0 (3024)
+0x6B01, 0x1061, 0x18C1, 0x4A00, 0x5AA0, 0x5240, 0x3141, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x4A01, 0xDDC1, 0xFF20,   // 0x0BE0 (3040)
+0xFE80, 0xFF00, 0xE602, 0x5A41, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2921, 0x5220, 0x5AA0, 0x4A00, 0x20E1, 0x1060,   // 0x0BF0 (3056)
+0x6AE1, 0xF6A1, 0xFEE0, 0xFEA1, 0xFEA0, 0xFF41, 0x93E1, 0x0000, 0x0000, 0x0000, 0x0000, 0x2124, 0xE71C, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C00 (3072)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x8C71, 0x0000, 0x0000, 0x0000, 0x0000, 0x0820, 0xCD61, 0xFF00, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x0C10 (3088)
+0xFF41, 0xDDE1, 0x6B01, 0x18C1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x18A0, 0x5A61, 0xBCE2, 0xFF01, 0xFEE0, 0xFEA0,   // 0x0C20 (3104)
+0xFEC0, 0xFEA0, 0xFEE0, 0xFF01, 0xC541, 0x6281, 0x20C1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x18C1, 0x6AE1, 0xDDC1,   // 0x0C30 (3120)
+0xFF41, 0xFEC0, 0xFEA0, 0xFEA0, 0xFF01, 0xC541, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0xA514, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C40 (3136)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x4208, 0x0000, 0x0000, 0x0000, 0x0000, 0x18A1, 0xDE01, 0xFF00, 0xFE80, 0xFEC0,   // 0x0C50 (3152)
+0xFEA0, 0xFEE0, 0xFF20, 0xFEC1, 0xD5A2, 0xAC82, 0x9401, 0x93E1, 0x9C42, 0xC522, 0xEE41, 0xFF01, 0xFF00, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x0C60 (3168)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFF00, 0xFF21, 0xF661, 0xC542, 0xA462, 0x93E1, 0x9C01, 0xB4A2, 0xD5A1, 0xFEC1, 0xFF20, 0xFEE0,   // 0x0C70 (3184)
+0xFEA0, 0xFEC0, 0xFE80, 0xFF00, 0xDE01, 0x18A1, 0x0000, 0x0000, 0x0000, 0x0000, 0x52AA, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C80 (3200)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD6BA, 0x10A2, 0x0000, 0x0000, 0x0000, 0x0000, 0x2921, 0xE641, 0xFF00, 0xFE80,   // 0x0C90 (3216)
+0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF00, 0xFF20, 0xFF20, 0xFF20, 0xFF20, 0xFF00, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0CA0 (3232)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF00, 0xFF20, 0xFF20, 0xFF20, 0xFF20, 0xFF00, 0xFEC0, 0xFEA0, 0xFEA0,   // 0x0CB0 (3248)
+0xFEA0, 0xFE80, 0xFF00, 0xE641, 0x2901, 0x0000, 0x0000, 0x0000, 0x0000, 0x2124, 0xE71C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0CC0 (3264)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAD55, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2901, 0xDE01, 0xFF00,   // 0x0CD0 (3280)
+0xFE80, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0CE0 (3296)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0,   // 0x0CF0 (3312)
+0xFE80, 0xFF00, 0xDE01, 0x2900, 0x0000, 0x0000, 0x0000, 0x0000, 0x0861, 0xBDD7, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D00 (3328)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8430, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x18A1, 0xC561,   // 0x0D10 (3344)
+0xFF21, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0D20 (3360)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0,   // 0x0D30 (3376)
+0xFF41, 0xC561, 0x18A1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x9CD3, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D40 (3392)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x73AE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0820,   // 0x0D50 (3408)
+0x9402, 0xFF01, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0D60 (3424)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEE0, 0xFF01,   // 0x0D70 (3440)
+0x9402, 0x0820, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C51, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D80 (3456)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x73AE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0D90 (3472)
+0x0000, 0x4A01, 0xDDC1, 0xFF41, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0DA0 (3488)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF21, 0xD5C1, 0x4A01,   // 0x0DB0 (3504)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C51, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0DC0 (3520)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x8430, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0DD0 (3536)
+0x0000, 0x0000, 0x0840, 0x7B61, 0xE641, 0xFF21, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0DE0 (3552)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEE0, 0xFF21, 0xE621, 0x7B42, 0x0840, 0x0000,   // 0x0DF0 (3568)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0841, 0x9492, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E00 (3584)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAD55, 0x10A2, 0x0000, 0x0000,   // 0x0E10 (3600)
+0x0000, 0x0000, 0x0000, 0x0000, 0x1880, 0x7B21, 0xD5A1, 0xFF01, 0xFF20, 0xFF00, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0,   // 0x0E20 (3616)
+0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF00, 0xFF20, 0xFF01, 0xD5A1, 0x7321, 0x1880, 0x0000, 0x0000, 0x0000,   // 0x0E30 (3632)
+0x0000, 0x0000, 0x0000, 0x18E3, 0xAD75, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E40 (3648)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xD69A, 0x4228, 0x0000,   // 0x0E50 (3664)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x41C1, 0x93E1, 0xD5A1, 0xFEA1, 0xFF01, 0xFF20, 0xFF20, 0xFF20, 0xFF00,   // 0x0E60 (3680)
+0xFF00, 0xFF00, 0xFF20, 0xFF20, 0xFF20, 0xFF01, 0xFEA1, 0xD5A1, 0x93E1, 0x41C1, 0x0020, 0x0000, 0x0000, 0x0020, 0x0000, 0x0000,   // 0x0E70 (3696)
+0x0000, 0x0000, 0x528A, 0xD6BA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E80 (3712)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFDF, 0x8C71,   // 0x0E90 (3728)
+0x10A2, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2901, 0x5221, 0x7B41, 0x9402, 0xAC82, 0xBCE2,   // 0x0EA0 (3744)
+0xC521, 0xBCE2, 0xAC82, 0x9401, 0x7B41, 0x5221, 0x2901, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0EB0 (3760)
+0x18E3, 0x94B2, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0EC0 (3776)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0ED0 (3792)
+0xD6BA, 0x632C, 0x0841, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0EE0 (3808)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x10A2, 0x738E,   // 0x0EF0 (3824)
+0xDEFB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F00 (3840)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F10 (3856)
+0xFFFF, 0xFFFF, 0xCE79, 0x6B4D, 0x18C3, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0000, 0x0000,   // 0x0F20 (3872)
+0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2104, 0x738E, 0xD69A, 0xFFFF,   // 0x0F30 (3888)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F40 (3904)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F50 (3920)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE71C, 0x94B2, 0x4A49, 0x1082, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0F60 (3936)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x18C3, 0x4A69, 0x9CD3, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F70 (3952)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F80 (3968)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F90 (3984)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDB, 0xA534, 0x6B6D, 0x4208, 0x2104, 0x18C3, 0x0861, 0x0841, 0x0000,   // 0x0FA0 (4000)
+0x0000, 0x0000, 0x0841, 0x0861, 0x18C3, 0x2124, 0x4228, 0x6B6D, 0xA534, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FB0 (4016)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FC0 (4032)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FD0 (4048)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDB, 0xB5B6, 0x9492, 0x6B6D, 0x4A49,   // 0x0FE0 (4064)
+0x4228, 0x4A49, 0x6B6D, 0x8C51, 0xAD75, 0xDEDB, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FF0 (4080)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x1000 (4096)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Textrotation_Demo/UTFT_Textrotation_Demo.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Textrotation_Demo/UTFT_Textrotation_Demo.ino
new file mode 100644
index 0000000..df9e25b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_Textrotation_Demo/UTFT_Textrotation_Demo.ino	
@@ -0,0 +1,44 @@
+// UTFT_Textrotation_Demo (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the textrotation-functions.
+//
+// This demo was made for modules with a screen resolution 
+// of 320x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t BigFont[];
+extern uint8_t SevenSegNumFont[];
+
+UTFT myGLCD(ITDB24E_16,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  myGLCD.InitLCD();
+  myGLCD.clrScr();
+  myGLCD.setFont(BigFont);
+}
+
+void loop()
+{
+    myGLCD.print("Text rotation", 0, 0);
+    myGLCD.setColor(0, 0, 255);
+    myGLCD.print("0 degrees", 0, 16, 0);
+    myGLCD.print("90 degrees", 319, 0, 90);
+    myGLCD.print("180 degrees", 319, 239, 180);
+    myGLCD.print("270 degrees", 0, 239, 270);
+
+    myGLCD.setFont(SevenSegNumFont);
+    myGLCD.setColor(0, 255, 0);
+    myGLCD.print("45", 90, 100, 45);
+    myGLCD.print("90", 200, 50, 90);
+    myGLCD.print("180", 300, 200, 180);
+
+  while (true) {};
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_ViewFont/UTFT_ViewFont.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_ViewFont/UTFT_ViewFont.ino
new file mode 100644
index 0000000..32919dc
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (ARM)/UTFT_ViewFont/UTFT_ViewFont.ino	
@@ -0,0 +1,51 @@
+// UTFT_ViewFont (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the included fonts.
+//
+// This demo was made for modules with a screen resolution 
+// of 320x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+extern uint8_t BigFont[];
+extern uint8_t SevenSegNumFont[];
+
+UTFT myGLCD(ITDB24E_16,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  myGLCD.InitLCD();
+
+  myGLCD.clrScr();
+}
+
+void loop()
+{
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 0);
+
+  myGLCD.setFont(BigFont);
+  myGLCD.print(" !\"#$%&'()*+,-./", CENTER, 0);
+  myGLCD.print("0123456789:;<=>?", CENTER, 16);
+  myGLCD.print("@ABCDEFGHIJKLMNO", CENTER, 32);
+  myGLCD.print("PQRSTUVWXYZ[\\]^_", CENTER, 48);
+  myGLCD.print("`abcdefghijklmno", CENTER, 64);
+  myGLCD.print("pqrstuvwxyz{|}~ ", CENTER, 80);
+
+  myGLCD.setFont(SmallFont);
+  myGLCD.print(" !\"#$%&'()*+,-./0123456789:;<=>?", CENTER, 120);
+  myGLCD.print("@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_", CENTER, 132);
+  myGLCD.print("`abcdefghijklmnopqrstuvwxyz{|}~ ", CENTER, 144);
+
+  myGLCD.setFont(SevenSegNumFont);
+  myGLCD.print("0123456789", CENTER, 190);
+
+  while(1) {};
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap/UTFT_Bitmap.pde b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap/UTFT_Bitmap.pde
new file mode 100644
index 0000000..68b7d80
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap/UTFT_Bitmap.pde	
@@ -0,0 +1,62 @@
+// UTFT_Bitmap (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the drawBitmap()-function.
+//
+// This demo was made to work on the 320x240 modules.
+// Any other size displays may cause strange behaviour.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for Arduino 2009/Uno
+//UTFT myGLCD(ITDB32S,19,18,17,16);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for Arduino Mega
+UTFT myGLCD(ITDB32S,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+extern unsigned int info[0x400];
+extern unsigned int icon[0x400];
+extern unsigned int tux[0x400];
+
+void setup()
+{
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  myGLCD.fillScr(255, 255, 255);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.print(" *** A 10 by 7 grid of a 32x32 icon *** ", CENTER, 228);
+  for (int x=0; x<10; x++)
+    for (int y=0; y<7; y++)
+      myGLCD.drawBitmap (x*32, y*32, 32, 32, info);
+
+  delay(5000);
+  
+  myGLCD.fillScr(255, 255, 255);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.print("   Two different icons in scale 1 to 4  ", CENTER, 228);
+  int x=0;
+  for (int s=0; s<4; s++)
+  {
+    x+=(s*32);
+    myGLCD.drawBitmap (x, 0, 32, 32, tux, s+1);
+  }
+  x=0;
+  for (int s=4; s>0; s--)
+  {
+    myGLCD.drawBitmap (x, 224-(s*32), 32, 32, icon, s);
+    x+=(s*32);
+  }
+
+  delay(5000);
+}
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap/icon.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap/icon.c
new file mode 100644
index 0000000..374dd09
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap/icon.c	
@@ -0,0 +1,73 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: taskmgr.png
+// Time generated: 11.10.2010 22:51:23
+// Size          : 2 048 Bytes
+
+#include 
+
+const unsigned short icon[0x400] PROGMEM ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0xCE79, 0xBDD7, 0xAD75,   // 0x0010 (16)
+0xAD55, 0xAD75, 0xBDF7, 0xD6BA, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xC638, 0x9492, 0x8C51, 0x9492, 0xA514, 0xA534,   // 0x0030 (48)
+0xA534, 0xA534, 0x9CF3, 0x8C71, 0x8430, 0x9CD3, 0xD69A, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCE59, 0x8410, 0x9492, 0xB5B6, 0xC618, 0xBDD7, 0xAD75, 0xA514,   // 0x0050 (80)
+0xA514, 0xA4F4, 0xAD55, 0xB5B6, 0xBDD7, 0xAD55, 0x8430, 0x8C71, 0xDEFB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x9CD3, 0x8430, 0xBDF7, 0xC618, 0xAD75, 0x94F2, 0x8CF1, 0x84B0, 0x8CD1,   // 0x0070 (112)
+0x9612, 0x8CB1, 0x7C6F, 0x7C8F, 0x8490, 0xA533, 0xBDF7, 0xB596, 0x7BEF, 0xB596, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x8430, 0x9CF3, 0xCE39, 0xA514, 0x94B2, 0x9E93, 0x94F2, 0x8CD1, 0x8CB1, 0x9D12,   // 0x0090 (144)
+0x9F74, 0x9D52, 0x8450, 0x7C8F, 0x73AE, 0x740E, 0x73CE, 0x9CD3, 0xC638, 0x8C51, 0x9CD3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x8430, 0xA534, 0xBDF7, 0x8CB1, 0x8C31, 0x9DB3, 0xA735, 0x9D13, 0x8CB1, 0x8C71, 0x9D13,   // 0x00B0 (176)
+0xB756, 0xA5D4, 0x8C71, 0x8490, 0x8390, 0x7C70, 0x73EE, 0x6B4D, 0x8450, 0xBDF7, 0x8C71, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x94B2, 0x9CF3, 0xBDD7, 0x8490, 0x8CF1, 0x9D72, 0xA694, 0xAE94, 0x9DD3, 0xA593, 0xA553, 0x9592,   // 0x00D0 (208)
+0x9672, 0x75CE, 0x5BAA, 0x64EB, 0x5D8C, 0x5BCA, 0x4B69, 0x634C, 0x748D, 0x7C4F, 0xBE18, 0x8430, 0xB5B6, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00E0 (224)
+0xFFFF, 0xFFFF, 0xFFFF, 0xC618, 0x8410, 0xBDF7, 0x8410, 0x83F0, 0x94F2, 0x9613, 0x9D13, 0xAE55, 0x9D12, 0x750E, 0x55CB, 0x4BC8,   // 0x00F0 (240)
+0x4447, 0x3BC6, 0x4B67, 0x44E8, 0x3CE8, 0x3325, 0x20E2, 0x2B45, 0x43E7, 0x3946, 0x732D, 0xC5F8, 0x7BCF, 0xE71C, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xF7BE, 0x7BEF, 0xBDB6, 0x9533, 0x8D71, 0x9552, 0x9E73, 0x9DD3, 0x94B2, 0x6D6D, 0x4BA8, 0x44A8, 0x55EA, 0x5D2A,   // 0x0110 (272)
+0x43E7, 0x4327, 0x46CA, 0x4B87, 0x42C6, 0x4E0A, 0x4D09, 0x4468, 0x4548, 0x3386, 0x2B25, 0x7C6F, 0xAD35, 0x9492, 0xFFFF, 0xFFFF,   // 0x0120 (288)
+0xFFDF, 0xFFFF, 0xBDD7, 0x8C71, 0xAD75, 0x8CF0, 0x8D71, 0x8D51, 0x9DF3, 0x740E, 0x21C4, 0x33E5, 0x558A, 0x554A, 0x650A, 0x566B,   // 0x0130 (304)
+0x43E7, 0x21C3, 0x3345, 0x2283, 0x1962, 0x3C87, 0x3386, 0x2163, 0x3345, 0x3346, 0x33A6, 0x32C6, 0x9CB3, 0x7BEF, 0xDEDB, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0x8430, 0xAD75, 0x8C31, 0x7C0F, 0x7BCF, 0x83F0, 0x636B, 0x0000, 0x0000, 0x4387, 0x462A, 0x4B27, 0x4B88, 0x4E8B,   // 0x0150 (336)
+0x42E6, 0x0000, 0x0020, 0x0100, 0x0000, 0x1121, 0x0040, 0x0000, 0x0941, 0x0000, 0x0020, 0x00E0, 0x5AAB, 0x94B2, 0x9CD3, 0xFFFF,   // 0x0160 (352)
+0xFFFF, 0xE71C, 0x8410, 0xB596, 0x7BEF, 0x7C6F, 0x84B0, 0x5B6B, 0x09E1, 0x0901, 0x1161, 0x3C06, 0x3D89, 0x32C5, 0x43E7, 0x470B,   // 0x0170 (368)
+0x4BC7, 0x0961, 0x11E2, 0x1282, 0x0961, 0x1262, 0x09E2, 0x0961, 0x12A2, 0x0961, 0x09C2, 0x0A01, 0x29E5, 0xA514, 0x7BEF, 0xFFDF,   // 0x0180 (384)
+0xFFFF, 0xBDD7, 0x9472, 0xA514, 0x6B4D, 0x7C6F, 0x634C, 0x0040, 0x0981, 0x0060, 0x00E0, 0x11E2, 0x10A1, 0x09C1, 0x19E3, 0x2B25,   // 0x0190 (400)
+0x22A3, 0x0060, 0x0120, 0x09E1, 0x0060, 0x09E1, 0x0120, 0x0060, 0x0A21, 0x0060, 0x0100, 0x01A0, 0x0040, 0x9CD3, 0x7BEF, 0xDEDB,   // 0x01A0 (416)
+0xFFFF, 0xA514, 0x9CF3, 0xB596, 0x73AE, 0x7C0F, 0x2945, 0x10A2, 0x2184, 0x18C3, 0x1923, 0x2184, 0x18C3, 0x21A4, 0x2964, 0x2905,   // 0x01B0 (432)
+0x2A25, 0x2104, 0x2965, 0x2A05, 0x2104, 0x2A05, 0x2985, 0x2104, 0x2A25, 0x2104, 0x2164, 0x29C4, 0x3166, 0xB5B6, 0x8410, 0xC618,   // 0x01C0 (448)
+0xFFFF, 0x9492, 0xA514, 0xDEDB, 0xC618, 0xA514, 0x8C51, 0x94B2, 0x9CB3, 0x9CF3, 0xA514, 0xA534, 0xAD75, 0xAD75, 0xB596, 0xB5D6,   // 0x01D0 (464)
+0xBDB7, 0xBDF7, 0xBDF7, 0xBDF7, 0xC618, 0xC5F8, 0xC5F8, 0xBDF7, 0xBDD7, 0xBDD7, 0xB5B6, 0xB596, 0xC638, 0xDEFB, 0x8430, 0xB596,   // 0x01E0 (480)
+0xFFFF, 0x8C51, 0x9CF3, 0xE73C, 0xDEFB, 0xD69A, 0xD6BA, 0xD6BA, 0xDEDB, 0xDEDB, 0xDEFB, 0xDF1B, 0xE71C, 0xE73C, 0xE73C, 0xE73C,   // 0x01F0 (496)
+0xEF5D, 0xEF5D, 0xEF5D, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xDEFB, 0xE71C, 0x8C51, 0xAD75,   // 0x0200 (512)
+0xFFFF, 0x8C71, 0x9CD3, 0xDEFB, 0xAD75, 0x9492, 0x9CD3, 0xA4F3, 0xA514, 0xAD55, 0xAD75, 0xB596, 0xBDB6, 0xBDD7, 0xC5F7, 0xC618,   // 0x0210 (528)
+0xC638, 0xCE59, 0xCE59, 0xCE79, 0xD679, 0xD679, 0xCE79, 0xCE59, 0xCE59, 0xC638, 0xC618, 0xBDF7, 0xCE79, 0xE71C, 0x8C51, 0xB596,   // 0x0220 (544)
+0xFFFF, 0x9CD3, 0x9492, 0xAD55, 0x2965, 0x2104, 0x2124, 0x2145, 0x1945, 0x2165, 0x2165, 0x2186, 0x2186, 0x29A6, 0x29A6, 0x31C7,   // 0x0230 (560)
+0x39C7, 0x31E7, 0x31E7, 0x31E7, 0x3208, 0x3208, 0x31E7, 0x31E7, 0x29E7, 0x31C7, 0x39C7, 0x31A6, 0x4A49, 0xBDF7, 0x8C51, 0xBDF7,   // 0x0240 (576)
+0xFFFF, 0xB5B6, 0x8430, 0x7BEF, 0x0000, 0x0000, 0x0000, 0x2000, 0x3000, 0x3000, 0x3000, 0x3000, 0x3000, 0x3000, 0x3800, 0x2000,   // 0x0250 (592)
+0x0000, 0x3000, 0x3800, 0x3000, 0x3800, 0x3800, 0x3800, 0x3000, 0x3800, 0x0800, 0x0000, 0x0000, 0x0000, 0xA514, 0x8430, 0xD6BA,   // 0x0260 (608)
+0xFFFF, 0xDEDB, 0x7BCF, 0x8430, 0x0020, 0x0000, 0x0000, 0x8000, 0xC800, 0xC000, 0xC800, 0xC820, 0xC820, 0xC820, 0xD020, 0x9800,   // 0x0270 (624)
+0x0000, 0xB820, 0xD020, 0xD020, 0xD020, 0xD020, 0xD020, 0xC820, 0xD020, 0x4800, 0x0000, 0x0000, 0x2144, 0xAD75, 0x8410, 0xF7BE,   // 0x0280 (640)
+0xFFFF, 0xFFFF, 0x7BEF, 0x8C71, 0x2945, 0x0000, 0x0000, 0x6800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xB000, 0x8000,   // 0x0290 (656)
+0x0000, 0x9800, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0x4000, 0x0000, 0x0000, 0x632C, 0xA534, 0x94B2, 0xFFFF,   // 0x02A0 (672)
+0xFFDF, 0xFFFF, 0xAD75, 0x73AE, 0x632C, 0x0000, 0x0000, 0x6920, 0xA9E0, 0xA1C0, 0xA9E0, 0xA9E0, 0xA9E0, 0xA9E0, 0xA9E0, 0x7960,   // 0x02B0 (688)
+0x0000, 0x99C0, 0xB200, 0xA9E0, 0xB200, 0xB200, 0xB1E0, 0xA9E0, 0xB200, 0x40C0, 0x0000, 0x1082, 0xAD75, 0x8410, 0xD69A, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xF79E, 0x630C, 0x8C51, 0x2965, 0x0000, 0x7400, 0xB620, 0xAE00, 0xB620, 0xB640, 0xB640, 0xB620, 0xB660, 0x84A0,   // 0x02D0 (720)
+0x0000, 0xA5A0, 0xBE60, 0xB660, 0xBE60, 0xBE60, 0xB660, 0xB640, 0xBE80, 0x4260, 0x0000, 0x6B6D, 0xAD75, 0x8430, 0xFFFF, 0xFFFF,   // 0x02E0 (736)
+0xFFFF, 0xFFDF, 0xFFFF, 0xB5B6, 0x632C, 0x8410, 0x0021, 0x7360, 0xBD40, 0xB520, 0xBD40, 0xBD60, 0xBD60, 0xBD40, 0xC580, 0x8C00,   // 0x02F0 (752)
+0x0000, 0xACE0, 0xC580, 0xC580, 0xC580, 0xC580, 0xC580, 0xBD60, 0xC5A0, 0x39C0, 0x2126, 0xBDF7, 0x73AE, 0xD6BA, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x7BEF, 0x7BEF, 0x630D, 0x4AE1, 0x6D21, 0x6D01, 0x6D21, 0x6D41, 0x6D41, 0x6D41, 0x6D61, 0x53E1,   // 0x0310 (784)
+0x0000, 0x64C1, 0x7562, 0x6D62, 0x6D62, 0x6D62, 0x6D62, 0x6D42, 0x6D41, 0x4263, 0xA515, 0x8C51, 0xA534, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0320 (800)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0x6B4D, 0x8410, 0x636E, 0x04A6, 0x05E5, 0x05C5, 0x0585, 0x0585, 0x0586, 0x05A6, 0x0424,   // 0x0330 (816)
+0x0000, 0x0505, 0x05C6, 0x05A6, 0x05A6, 0x05C7, 0x0606, 0x0606, 0x1CE9, 0xA535, 0x9492, 0x8C71, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x6B4D, 0x83EF, 0x9411, 0x3A47, 0x0403, 0x0584, 0x05A4, 0x0585, 0x0585, 0x0404,   // 0x0350 (848)
+0x0000, 0x04E5, 0x05A5, 0x05A5, 0x05C5, 0x0584, 0x1405, 0x634B, 0xBD76, 0x8C51, 0x8C51, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0360 (864)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x8410, 0x6B6D, 0x9CB3, 0x7C6F, 0x3CA9, 0x0BE4, 0x0443, 0x0504, 0x03C2,   // 0x0370 (880)
+0x0000, 0x0483, 0x0504, 0x0444, 0x1426, 0x552D, 0xA554, 0xB576, 0x73CE, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB5B6, 0x6B4D, 0x7BAF, 0x9432, 0x8BD1, 0x6BCE, 0x4C6B, 0x3C09,   // 0x0390 (912)
+0x3186, 0x3C8A, 0x5C8C, 0x8430, 0xA493, 0xACD4, 0x8410, 0x7BEF, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xAD75, 0x7BEF, 0x73AE, 0x83F0, 0x8C11, 0x9431,   // 0x03B0 (944)
+0x9492, 0x9452, 0x9432, 0x8430, 0x7BEF, 0x8450, 0xBDF7, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEFB, 0xBDD7, 0xA534, 0x94D3,   // 0x03D0 (976)
+0x94B2, 0x9CF3, 0xA554, 0xC618, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap/info.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap/info.c
new file mode 100644
index 0000000..a0a04ee
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap/info.c	
@@ -0,0 +1,73 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: info.png
+// Time generated: 11.10.2010 22:27:55
+// Size          : 2 048 Bytes
+
+#include 
+
+const unsigned short info[0x400] PROGMEM ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0010 (16)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF9F, 0xC69D, 0x95BB, 0x7D1A, 0x6CB9,   // 0x0030 (48)
+0x6499, 0x74F9, 0x8D7A, 0xB63C, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAE1C, 0x4C18, 0x2B56, 0x3397, 0x4C38, 0x64B9, 0x751A,   // 0x0050 (80)
+0x7D3A, 0x6CD9, 0x5458, 0x3BD7, 0x2B56, 0x3BB7, 0x855A, 0xE77E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xA5FB, 0x2B56, 0x2B77, 0x751A, 0xB67C, 0xD73E, 0xE75E, 0xE77E, 0xE77E,   // 0x0070 (112)
+0xE77E, 0xE77E, 0xE75E, 0xDF3E, 0xC6DD, 0x8D9B, 0x43D7, 0x1B16, 0x74D9, 0xF7BF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF9F, 0x4C18, 0x1AF6, 0x855A, 0xCEFE, 0xD71E, 0xCEFD, 0xC6DD, 0xC6BD, 0xC6BD, 0xBEBD,   // 0x0090 (144)
+0xC6BD, 0xBEBD, 0xC6BD, 0xC6DD, 0xC6DD, 0xD71E, 0xD71E, 0xA61C, 0x33B7, 0x2316, 0xBE7C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDF3E, 0x2336, 0x3BD7, 0xBE9D, 0xC6DD, 0xBE9D, 0xBE9D, 0xBE9D, 0xBEBD, 0xBE9D, 0xCEFD, 0xEF9F,   // 0x00B0 (176)
+0xEF9F, 0xD73E, 0xBE9D, 0xBEBD, 0xBE9D, 0xBE9D, 0xB69D, 0xC6BD, 0xCEDD, 0x6CFA, 0x0295, 0x9DBB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xE75E, 0x1AF6, 0x4C58, 0xBEBD, 0xB67D, 0xAE5C, 0xB67D, 0xB67D, 0xB69D, 0xB67D, 0xBEBD, 0xF7DF, 0xFFFF,   // 0x00D0 (208)
+0xFFFF, 0xFFFF, 0xCF1E, 0xB67D, 0xB67D, 0xB67D, 0xB67D, 0xAE5C, 0xAE5C, 0xC6BD, 0x857B, 0x0295, 0xA5DB, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00E0 (224)
+0xFFFF, 0xFFFF, 0xFFDF, 0x3BB7, 0x33D8, 0xB67D, 0xA63C, 0xA63C, 0xAE5C, 0xAE5D, 0xAE5D, 0xAE7D, 0xA65D, 0xC6DD, 0xFFFF, 0xFFFF,   // 0x00F0 (240)
+0xFFDF, 0xFFFF, 0xDF5E, 0xA65D, 0xAE7D, 0xAE5D, 0xAE5D, 0xAE5C, 0xA63C, 0xA61C, 0xB67D, 0x753A, 0x0295, 0xCEBC, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xF7DF, 0xFFFF, 0x957A, 0x12F6, 0x9E1C, 0x9E1C, 0x9E1C, 0x9E1C, 0xA63C, 0xA63C, 0xA63D, 0xA63D, 0xA65D, 0x9DFC, 0xDF3E, 0xFFFF,   // 0x0110 (272)
+0xFFFF, 0xFFDF, 0xA61C, 0xA65D, 0xA65D, 0xA63D, 0xA63C, 0xA63C, 0x9E1C, 0x9E1C, 0x9DFC, 0xAE3C, 0x3C18, 0x3396, 0xFFDF, 0xFFFF,   // 0x0120 (288)
+0xFFFF, 0xF79F, 0x2336, 0x64DA, 0x9DFC, 0x95DC, 0x95FC, 0x95FC, 0x9E1C, 0x9E1C, 0x9E3D, 0x9E3D, 0x9E3D, 0x9E3D, 0x7D3B, 0xA63C,   // 0x0130 (304)
+0xB6BD, 0x8DBB, 0x8DFC, 0xA65D, 0x9E3D, 0x9E3D, 0x9E1C, 0x9E1C, 0x95FC, 0x95FC, 0x95DC, 0x95DC, 0x8DBB, 0x0AF6, 0xA5DA, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xA5FB, 0x1337, 0x8DBB, 0x8DBB, 0x8DBC, 0x8DDC, 0x95FC, 0x95FC, 0x961C, 0x961D, 0x963D, 0x9E3D, 0x963D, 0xA67D, 0xB6BD,   // 0x0150 (336)
+0xB6BD, 0xAE7D, 0x9E3D, 0x9E3D, 0x961D, 0x961D, 0x961C, 0x95FC, 0x95FC, 0x8DDC, 0x8DDC, 0x859B, 0x95DC, 0x3C18, 0x4BD7, 0xFFFF,   // 0x0160 (352)
+0xFFFF, 0x6499, 0x33F8, 0x8DBB, 0x859B, 0x85BC, 0x85BC, 0x8DDC, 0x8DFC, 0x8DFD, 0x8E1D, 0x961D, 0x961D, 0x9E3D, 0xF7BF, 0xFFFF,   // 0x0170 (368)
+0xFFFF, 0xFFFF, 0xA67D, 0x8E1D, 0x961D, 0x8E1D, 0x8DFD, 0x8DFC, 0x8DDC, 0x85BC, 0x85BC, 0x859B, 0x859B, 0x5CDA, 0x2336, 0xE71C,   // 0x0180 (384)
+0xFFFF, 0x43F8, 0x4C79, 0x859B, 0x7D7B, 0x7D9C, 0x85BC, 0x85DC, 0x85DC, 0x8DFD, 0x8DFD, 0x8E1D, 0x8E1D, 0xA67E, 0xFFFF, 0xFFFF,   // 0x0190 (400)
+0xFFFF, 0xFFFF, 0xBEDE, 0x85FD, 0x8E1D, 0x8DFD, 0x8DFD, 0x85DC, 0x85DC, 0x85BC, 0x7D9C, 0x7D7B, 0x7D7B, 0x753B, 0x1B36, 0xBE5A,   // 0x01A0 (416)
+0xFFBE, 0x3BF8, 0x3419, 0x6D1B, 0x757B, 0x7D9C, 0x7D9C, 0x7DBC, 0x7DDD, 0x85FD, 0x85FD, 0x861D, 0x861D, 0x9E7E, 0xFFFF, 0xFFFF,   // 0x01B0 (432)
+0xFFFF, 0xFFFF, 0xB6DE, 0x85FD, 0x8E1D, 0x85FD, 0x85FD, 0x7DDD, 0x7DBC, 0x7D9C, 0x7D9C, 0x757B, 0x6D3B, 0x4C9A, 0x1337, 0xADD9,   // 0x01C0 (448)
+0xFFBE, 0x4418, 0x23B9, 0x3439, 0x4CBA, 0x653B, 0x759C, 0x7DBD, 0x7DDD, 0x7DFD, 0x861D, 0x861E, 0x861E, 0x9E7E, 0xFFFF, 0xFFFF,   // 0x01D0 (464)
+0xFFFF, 0xFFFF, 0xB6DE, 0x7E1E, 0x861E, 0x85FD, 0x7DFD, 0x7DDD, 0x7DBD, 0x759C, 0x653B, 0x4CDB, 0x3439, 0x2BF9, 0x1337, 0xA5B9,   // 0x01E0 (480)
+0xFF9E, 0x4C39, 0x2BF9, 0x345A, 0x3C7A, 0x3C9B, 0x4CFC, 0x5D5C, 0x659D, 0x75DD, 0x7DFE, 0x861E, 0x7E3E, 0x969F, 0xFFFF, 0xFFFF,   // 0x01F0 (496)
+0xFFFF, 0xFFFF, 0xB6FF, 0x7E1E, 0x863E, 0x7DFE, 0x75DD, 0x6D9D, 0x5D5C, 0x4CFC, 0x3C9B, 0x347A, 0x345A, 0x343A, 0x1B78, 0xA5B9,   // 0x0200 (512)
+0xF79E, 0x4418, 0x2C3A, 0x3C7A, 0x449B, 0x44DB, 0x4CFC, 0x4D3C, 0x555D, 0x5D7D, 0x65BE, 0x6DFE, 0x6DFF, 0x867F, 0xFFFF, 0xFFFF,   // 0x0210 (528)
+0xFFFF, 0xFFFF, 0xA6DF, 0x65FF, 0x6DFE, 0x65BE, 0x5D9E, 0x555D, 0x4D3C, 0x4CFC, 0x44DB, 0x44BB, 0x3C7A, 0x345A, 0x1B78, 0xA599,   // 0x0220 (544)
+0xFFDE, 0x43D8, 0x345A, 0x3C9A, 0x44DB, 0x4CFC, 0x4D3C, 0x555D, 0x5D9D, 0x5DBE, 0x65DE, 0x6DFF, 0x661F, 0x867F, 0xFFFF, 0xFFFF,   // 0x0230 (560)
+0xFFFF, 0xFFFF, 0xA6DF, 0x65FF, 0x6DFF, 0x65DE, 0x5DBE, 0x5D9D, 0x555D, 0x4D3C, 0x4CFC, 0x44DB, 0x3C7A, 0x3C9B, 0x1B57, 0xADB9,   // 0x0240 (576)
+0xFFFF, 0x4BD7, 0x2C1A, 0x44DB, 0x44DB, 0x4D1C, 0x555D, 0x5D7D, 0x5DBE, 0x65DE, 0x6E1F, 0x6E3F, 0x765F, 0x96BF, 0xFFFF, 0xFFFF,   // 0x0250 (592)
+0xFFFF, 0xFFFF, 0xAEFF, 0x6E3F, 0x763F, 0x6E1F, 0x65DE, 0x5DBE, 0x5D7D, 0x555D, 0x4D1C, 0x44DC, 0x3C9B, 0x44DC, 0x1AD5, 0xC639,   // 0x0260 (608)
+0xFFFF, 0x84D8, 0x1317, 0x5D7D, 0x44DB, 0x553C, 0x557D, 0x5D9E, 0x65DE, 0x65FF, 0x6E3F, 0x7E5F, 0x7E7F, 0x9EDF, 0xFFFF, 0xFFFF,   // 0x0270 (624)
+0xFFFF, 0xFFFF, 0xB73F, 0x7E7F, 0x7E5F, 0x6E3F, 0x65FF, 0x65DE, 0x5D9E, 0x557D, 0x553C, 0x44DC, 0x4D1C, 0x345B, 0x22B4, 0xE71B,   // 0x0280 (640)
+0xFFFF, 0xD6BC, 0x0234, 0x4CFC, 0x5D7D, 0x4D3C, 0x5D9D, 0x5DBE, 0x65FF, 0x6E3F, 0x765F, 0x867F, 0x8EBF, 0xA6DF, 0xFFFF, 0xFFFF,   // 0x0290 (656)
+0xFFFF, 0xFFFF, 0xB71F, 0x8EBF, 0x869F, 0x765F, 0x6E3F, 0x65FF, 0x5DBE, 0x5D7D, 0x553D, 0x4D1C, 0x65BE, 0x0AB7, 0x6C15, 0xFFBE,   // 0x02A0 (672)
+0xFFFF, 0xFFFF, 0x53B6, 0x0296, 0x75FE, 0x5D9D, 0x557D, 0x65DE, 0x6E1F, 0x763F, 0x7E7F, 0x8EBF, 0x9EFF, 0x96BE, 0xAE3C, 0xE77E,   // 0x02B0 (688)
+0xEF9E, 0xC69D, 0x967E, 0x9EFF, 0x8EBF, 0x7E7F, 0x763F, 0x6E1F, 0x65DE, 0x5D9E, 0x555D, 0x761E, 0x341A, 0x1294, 0xBE18, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xCE9B, 0x0A13, 0x2378, 0x7E5F, 0x6E1E, 0x5DBE, 0x6E1F, 0x7E5F, 0x869F, 0x96DF, 0x9EFF, 0xAF5F, 0x9E9E, 0x8DFC,   // 0x02D0 (720)
+0x8E1C, 0x967D, 0xAF3F, 0xA6FF, 0x96DF, 0x869F, 0x7E5F, 0x6E1F, 0x5DBE, 0x65DE, 0x7E5F, 0x4CBB, 0x0AB5, 0x7454, 0xEF5C, 0xFFFF,   // 0x02E0 (736)
+0xFFFF, 0xFFFF, 0xFFFF, 0x8D17, 0x01D3, 0x23B9, 0x7E3E, 0x8E9F, 0x763F, 0x765F, 0x8E9F, 0x9EDF, 0xA71F, 0xB75F, 0xC7BF, 0xCFDF,   // 0x02F0 (752)
+0xCFDF, 0xC7BF, 0xB75F, 0xA71F, 0x9EDF, 0x8E9F, 0x765F, 0x6E1F, 0x867F, 0x8E7F, 0x4CBB, 0x1317, 0x4BB4, 0xD679, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFBD, 0x7476, 0x0214, 0x1B78, 0x659D, 0x9EDF, 0x9EFF, 0x96DF, 0x9EFF, 0xAF1F, 0xB75F, 0xC79F, 0xD7DF,   // 0x0310 (784)
+0xD7DF, 0xC79F, 0xB75F, 0xAF1F, 0x9EDF, 0x96DF, 0x96DF, 0x9EFF, 0x7E1E, 0x3C5A, 0x1B77, 0x43B5, 0xBDD6, 0xF7BE, 0xFFFF, 0xFFFF,   // 0x0320 (800)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF77D, 0x7CB6, 0x12B4, 0x1337, 0x449B, 0x7DFD, 0xA6FF, 0xB75F, 0xBF7F, 0xC79F, 0xCFBF, 0xD7FF,   // 0x0330 (816)
+0xD7FF, 0xCFBF, 0xC79F, 0xBF7F, 0xB77F, 0xAF1F, 0x8E5E, 0x551B, 0x3419, 0x2BD7, 0x5415, 0xB5B6, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79D, 0xA577, 0x3B75, 0x1B36, 0x2BD9, 0x4CBB, 0x759D, 0x965E, 0xAEDF, 0xBF3F, 0xC77F,   // 0x0350 (848)
+0xC77F, 0xBF3F, 0xB6FF, 0x9E7F, 0x7DDD, 0x5D1C, 0x447A, 0x3C59, 0x4437, 0x7474, 0xC617, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0360 (864)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDE, 0xD699, 0x84D5, 0x43D5, 0x33B7, 0x3418, 0x4C7A, 0x5CFC, 0x753D, 0x857E,   // 0x0370 (880)
+0x859E, 0x755D, 0x653C, 0x5CFB, 0x4CDA, 0x4CB9, 0x5497, 0x6C95, 0xA555, 0xDEDA, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79D, 0xCE79, 0x9D56, 0x7495, 0x5C56, 0x4C77, 0x4C97, 0x4CB8,   // 0x0390 (912)
+0x54D8, 0x5CD8, 0x5CF8, 0x64D7, 0x74D6, 0x8CF5, 0xAD96, 0xD699, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFBE, 0xEF1B, 0xD679, 0xBDF7, 0xAD96, 0xA576,   // 0x03B0 (944)
+0xA576, 0xAD76, 0xB5B6, 0xC5F7, 0xD679, 0xEF3C, 0xFFDE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFBE,   // 0x03D0 (976)
+0xF7BE, 0xF7BE, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap/tux.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap/tux.c
new file mode 100644
index 0000000..3b307fa
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap/tux.c	
@@ -0,0 +1,1404 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: tux.png
+// Time generated: 11.10.2010 22:51:32
+// Size          : 2 048 Bytes
+
+#include 
+
+const unsigned short tux[0x400] PROGMEM ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73C, 0x9CD3, 0x9CF3, 0xA514,   // 0x0010 (16)
+0x9CF3, 0x8C51, 0xAD75, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x5AEB, 0x7BEF, 0x9CD3, 0x94B2,   // 0x0030 (48)
+0x94B2, 0x94B2, 0x4228, 0x7BEF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x9CF3, 0x18E3, 0x630C, 0x4A49, 0x4A69,   // 0x0050 (80)
+0x4A69, 0x528A, 0x4A49, 0x0000, 0xC638, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x6B6D, 0x0000, 0x0020, 0x10A2, 0x1082,   // 0x0070 (112)
+0x0841, 0x0841, 0x0841, 0x0000, 0x630C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x528A, 0x4228, 0x8410, 0x0000, 0x0861,   // 0x0090 (144)
+0xAD55, 0xBDD7, 0x10A2, 0x0000, 0x2945, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x5ACB, 0x8C71, 0xE75D, 0x2126, 0x528B,   // 0x00B0 (176)
+0xE75D, 0xDEDB, 0x7BCF, 0x0000, 0x18E3, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x6B6D, 0x4A4A, 0x6B2A, 0x8BE7, 0xA48A,   // 0x00D0 (208)
+0x6B09, 0x4A8A, 0x8431, 0x0000, 0x2104, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00E0 (224)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x6B6E, 0x5204, 0xDE6A, 0xFFF7, 0xFFF8,   // 0x00F0 (240)
+0xD5AC, 0xBCAA, 0x5A66, 0x0000, 0x1082, 0xDEFB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8C10, 0xC540, 0xFFED, 0xFF2C, 0xFEEC,   // 0x0110 (272)
+0xFECC, 0xFE66, 0x8260, 0x0000, 0x0000, 0xB596, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0120 (288)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B3, 0x9C25, 0xFF20, 0xFE40, 0xFDA0,   // 0x0130 (304)
+0xFCC0, 0xF524, 0x836A, 0x0000, 0x0000, 0x630C, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x630C, 0x94B4, 0xFF13, 0xFD83, 0xF523,   // 0x0150 (336)
+0xE5CF, 0xF79E, 0xE71D, 0x0861, 0x0000, 0x0861, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0160 (352)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xCE59, 0x0841, 0xD69A, 0xFFFF, 0xFF7D, 0xF77D,   // 0x0170 (368)
+0xFFFF, 0xFFFF, 0xFFFF, 0x73AE, 0x0000, 0x0000, 0x4A69, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0180 (384)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0x10A2, 0x8410, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF,   // 0x0190 (400)
+0xFFFF, 0xFFDF, 0xFFFF, 0xCE59, 0x0000, 0x0000, 0x0000, 0x9492, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01A0 (416)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x52AA, 0x0020, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01B0 (432)
+0xFFDF, 0xFFDF, 0xF7BE, 0xFFDF, 0x3186, 0x0000, 0x0020, 0x0841, 0xCE79, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01C0 (448)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xC638, 0x0000, 0x52AA, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFDF,   // 0x01D0 (464)
+0xFFDF, 0xF7BE, 0xF79E, 0xFFFF, 0x9CF3, 0x0000, 0x0841, 0x0000, 0x39E7, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01E0 (480)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x5ACB, 0x0000, 0xBDF7, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFDF, 0xFFDF,   // 0x01F0 (496)
+0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0x3186, 0x0000, 0x0861, 0x0000, 0xAD55, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0200 (512)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73C, 0x0861, 0x4A49, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF,   // 0x0210 (528)
+0xF7BE, 0xF79E, 0xEF7D, 0xEF5D, 0xFFDF, 0x8410, 0x0000, 0x1082, 0x0000, 0x39E7, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0220 (544)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B2, 0x0000, 0xB596, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE,   // 0x0230 (560)
+0xF79E, 0xEF7D, 0xEF7D, 0xE73C, 0xF79E, 0xAD55, 0x0861, 0x10A2, 0x0861, 0x0841, 0xCE59, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0240 (576)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0x3185, 0x10A2, 0xE71C, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF79E,   // 0x0250 (592)
+0xEF7D, 0xEF7D, 0xEF5D, 0xE73C, 0xEF5D, 0xBDF7, 0x18C3, 0x18C3, 0x18C3, 0x0000, 0x8C71, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0260 (608)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B2, 0x0000, 0x39E7, 0xF7BE, 0xFFFF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF79E, 0xEF7D,   // 0x0270 (624)
+0xEF7D, 0xEF5D, 0xE73C, 0xE71C, 0xE71C, 0xC618, 0x18E3, 0x10A2, 0x10A2, 0x0020, 0x6B4D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0280 (640)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8C51, 0x38E0, 0x4A27, 0xFFFF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF79E, 0xEF7D, 0xEF7D,   // 0x0290 (656)
+0xEF5D, 0xE73C, 0xE71C, 0xDEFB, 0xDF1D, 0xBDF8, 0x39C7, 0x5ACB, 0x528A, 0x10A3, 0x738F, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02A0 (672)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDD6C, 0xFE2B, 0xBC45, 0xA513, 0xFFFF, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF5D,   // 0x02B0 (688)
+0xE73C, 0xE71C, 0xDEFB, 0xD6DC, 0xDD8E, 0xB3E4, 0x2124, 0x2965, 0x2945, 0x20C1, 0xB511, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF77C, 0xE5CF, 0xF60B, 0xFF9B, 0xFF54, 0x8B02, 0x7BF0, 0xFFDF, 0xF79E, 0xEF5D, 0xEF5D, 0xE73C,   // 0x02D0 (720)
+0xE71C, 0xDEFB, 0xDEDB, 0xCE7A, 0xED89, 0xDDAD, 0x0842, 0x0000, 0x0000, 0xAC69, 0xDD6B, 0xEFBF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02E0 (736)
+0xFFFF, 0xFFFF, 0xFFBE, 0xE5CB, 0xEDC9, 0xFE4B, 0xFF14, 0xFEF3, 0xFF35, 0xFE8D, 0x51C1, 0x634E, 0xE73C, 0xEF5D, 0xE73C, 0xE71C,   // 0x02F0 (752)
+0xDEFB, 0xDEDB, 0xD6DB, 0xCE59, 0xE58B, 0xFF98, 0xBD4F, 0x8B88, 0xCD90, 0xFFB7, 0xCCE8, 0xE73D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xEF3B, 0xF583, 0xFF30, 0xFF11, 0xFECF, 0xFEEF, 0xFECF, 0xFF30, 0xDD46, 0x2903, 0x6B8E, 0xEF7D, 0xE71C, 0xDEFB,   // 0x0310 (784)
+0xDEDB, 0xD6BA, 0xD69A, 0xCE59, 0xE5AA, 0xFF11, 0xFF53, 0xFF73, 0xFF33, 0xFF12, 0xFE6C, 0xDDAD, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0320 (800)
+0xFFFF, 0xFFFF, 0xF79E, 0xEDC5, 0xFECB, 0xFECC, 0xFECC, 0xFEEC, 0xFECB, 0xFECC, 0xFEEA, 0x9BE5, 0x8432, 0xE73C, 0xDEDB, 0xDEDB,   // 0x0330 (816)
+0xD6BA, 0xD69A, 0xDEDB, 0xA4F3, 0xD547, 0xFF2E, 0xFECD, 0xFECE, 0xFEEE, 0xFEEE, 0xFF10, 0xFEAB, 0xE5A8, 0xEF7D, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xF79E, 0xF603, 0xFEA2, 0xFEC7, 0xFEC7, 0xFEA4, 0xFE81, 0xFE61, 0xFEA4, 0xFE43, 0xDE33, 0xE75E, 0xE71C, 0xDEFB,   // 0x0350 (848)
+0xDEDB, 0xCE58, 0x8C72, 0x5247, 0xEDE4, 0xFF0A, 0xFECA, 0xFEC9, 0xFE84, 0xFE83, 0xFEE7, 0xFEA3, 0xB443, 0xD69B, 0xFFFF, 0xFFFF,   // 0x0360 (864)
+0xFFFF, 0xFFFF, 0xF75B, 0xFE60, 0xFF00, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEE0, 0xE5C1, 0x9492, 0xA514, 0x9CD3,   // 0x0370 (880)
+0x8410, 0x630B, 0x4229, 0x6AE8, 0xFE80, 0xFEC1, 0xFEC1, 0xFEA0, 0xFEA0, 0xFEE0, 0xDD80, 0x9BE8, 0xB597, 0xFFDF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xF79E, 0xD589, 0xE600, 0xFEA0, 0xFF00, 0xFF40, 0xFF40, 0xFF00, 0xFF00, 0xFF20, 0xFEC0, 0x5267, 0x4229, 0x4A48,   // 0x0390 (912)
+0x4A49, 0x5289, 0x424A, 0x7B46, 0xFF20, 0xFEE0, 0xFEE0, 0xFF20, 0xFEE0, 0xB4A5, 0x9C92, 0xDEFD, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xFFFF, 0xE71D, 0xBDB6, 0xB530, 0xBD0B, 0xCD65, 0xEE60, 0xFF40, 0xFFA0, 0xFF80, 0xBD03, 0x8410, 0xA514, 0xA534,   // 0x03B0 (944)
+0xAD75, 0xB596, 0xA555, 0x9C8F, 0xF6C0, 0xFFA0, 0xFFA0, 0xF6E0, 0xA449, 0xB5B8, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7F, 0xD69C, 0xBD95, 0xBD4C, 0xCDC6, 0xB4E8, 0xAD35, 0xF7BF, 0xFFFF, 0xFFFF,   // 0x03D0 (976)
+0xFFFF, 0xFFFF, 0xFFFF, 0xF7BF, 0xCDD0, 0xCDC6, 0xCDA7, 0xA48D, 0xCE7B, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDF1F, 0xB59A, 0xBDDA, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFDF, 0xFFDF, 0xFFFF, 0xEF7F, 0xB59A, 0xAD59, 0xDF1D, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
+
+// Generated by  : ImgConv v1.0
+// Generated from: HappyCat.jpg
+// Time generated: 02.07.2013 23:08:32
+// Dimensions    : 80x60 pixels
+// Size          : 9 600 Bytes
+
+prog_uint16_t HappyCatSmall[0x12C0] PROGMEM ={
+0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0820, 0x0800, 0x0000, 0x0820, 0x1062, 0x0820,   // 0x0010 (16)
+0x0800, 0x28E3, 0x3144, 0x2903, 0x20A1, 0x1040, 0x0820, 0x0820, 0x1041, 0x20C3, 0x20E3, 0x1862, 0x1882, 0x1882, 0x18C2, 0x0840,   // 0x0020 (32)
+0x1000, 0x3103, 0x3103, 0x41C6, 0x6289, 0x5A68, 0x3144, 0x2081, 0x6289, 0x944F, 0x732A, 0x8BCD, 0x8BCD, 0x940E, 0x9C4F, 0x8BAC,   // 0x0030 (48)
+0x49E5, 0x4184, 0x6AEA, 0x5A68, 0x3964, 0x2903, 0x0800, 0x0800, 0x0800, 0x1881, 0x1041, 0x1882, 0x20A2, 0x20A2, 0x20A2, 0x20C2,   // 0x0040 (64)
+0x28C1, 0x28C1, 0x28E2, 0x28C2, 0x28C2, 0x28A2, 0x2082, 0x2082, 0x28C2, 0x28C2, 0x2903, 0x2903, 0x28E2, 0x2903, 0x2923, 0x2923,   // 0x0050 (80)
+0x0820, 0x0821, 0x0820, 0x0800, 0x0800, 0x0820, 0x0800, 0x0800, 0x0800, 0x0820, 0x0820, 0x0800, 0x0820, 0x0820, 0x94B2, 0xB575,   // 0x0060 (96)
+0x734D, 0x4186, 0x41C6, 0x5248, 0x6AEA, 0x5247, 0x3984, 0x3964, 0x3103, 0x20C2, 0x3124, 0x3144, 0x20C2, 0x1881, 0x3144, 0x39A5,   // 0x0070 (112)
+0x3944, 0x49C6, 0x5227, 0x83AD, 0x9C70, 0x7B6C, 0x732B, 0x6289, 0xACF2, 0xBD53, 0x9C4F, 0x6AC9, 0x732A, 0x5A67, 0xA490, 0xA4B0,   // 0x0080 (128)
+0x5A47, 0x2080, 0x3964, 0x5227, 0x6ACA, 0x734C, 0x3144, 0x1000, 0x1020, 0x1881, 0x1020, 0x1861, 0x1840, 0x3103, 0x28E2, 0x2081,   // 0x0090 (144)
+0x28C2, 0x1880, 0x2081, 0x28C2, 0x28E2, 0x20A1, 0x1881, 0x20A2, 0x20A2, 0x20C2, 0x28E2, 0x28E2, 0x20E2, 0x2903, 0x2923, 0x2903,   // 0x00A0 (160)
+0x0821, 0x0821, 0x0800, 0x0000, 0x0800, 0x0820, 0x0800, 0x0000, 0x0820, 0x0821, 0x0800, 0x0000, 0x0000, 0x0000, 0x4A28, 0xBDB6,   // 0x00B0 (176)
+0xE6FB, 0xD638, 0xACF3, 0x7B4C, 0x4A07, 0x6288, 0x7B4B, 0x7B4B, 0x7B6C, 0x6AA9, 0x4185, 0x4185, 0x49E6, 0x49C6, 0x5A68, 0x734B,   // 0x00C0 (192)
+0x6AEA, 0x6AC9, 0x734B, 0x9C70, 0x8C0F, 0x7B6C, 0x7B6C, 0x9C90, 0xD617, 0xAD12, 0x6289, 0x6ACA, 0x732B, 0x3984, 0x9C50, 0xCDD6,   // 0x00D0 (208)
+0x5A68, 0x2902, 0x5227, 0x732B, 0x944F, 0xA491, 0x7B4C, 0x28E3, 0x4185, 0x4185, 0x28C2, 0x1840, 0x1020, 0x28C2, 0x2081, 0x2081,   // 0x00E0 (224)
+0x1881, 0x20A2, 0x1881, 0x1861, 0x20A2, 0x20A1, 0x2081, 0x20A2, 0x28E2, 0x2903, 0x28E2, 0x28E2, 0x28E3, 0x28E2, 0x2903, 0x2903,   // 0x00F0 (240)
+0x0820, 0x0820, 0x0000, 0x0000, 0x0000, 0x0820, 0x0800, 0x0000, 0x0000, 0x0820, 0x0000, 0x0820, 0x0000, 0x0820, 0x0841, 0x18A3,   // 0x0100 (256)
+0x630C, 0xBDD7, 0xDE99, 0xE6DB, 0xBDB5, 0x9C71, 0x7B4C, 0x6AA9, 0x6AEA, 0x6ACA, 0x5A68, 0x41A5, 0x5227, 0x940E, 0x9C90, 0x83CD,   // 0x0110 (272)
+0x732A, 0x838C, 0x9C70, 0xACD1, 0x8BEE, 0x7B6C, 0x940F, 0xB533, 0xE699, 0xB533, 0x5A68, 0x734C, 0x62A9, 0x49E6, 0xACF2, 0xD657,   // 0x0120 (288)
+0x83AD, 0x5248, 0x5227, 0x62A9, 0xA4D2, 0xACF2, 0x8BCE, 0x6289, 0x5207, 0x5207, 0x5A68, 0x49C6, 0x28E2, 0x1840, 0x2081, 0x2081,   // 0x0130 (304)
+0x20A2, 0x20A2, 0x20A2, 0x28E3, 0x28E2, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x3123, 0x3123, 0x3103, 0x2903, 0x20A2, 0x20E3, 0x28E3,   // 0x0140 (320)
+0x0820, 0x0000, 0x0000, 0x0000, 0x0000, 0x0820, 0x0820, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0821,   // 0x0150 (336)
+0x3186, 0x6B6E, 0x94B3, 0xC5F8, 0xDEBB, 0xEF1C, 0xDE9A, 0xC5B6, 0xA4B2, 0x9C71, 0x9C70, 0xA4B1, 0x942F, 0x9C90, 0x9C90, 0x7B6C,   // 0x0160 (352)
+0x7B6B, 0x9C6F, 0xACF1, 0xACD1, 0x7B8C, 0x734B, 0x83CD, 0xBD54, 0xCDF6, 0xCDD6, 0x734C, 0x8C0F, 0x49E6, 0x5A89, 0xBD75, 0xD658,   // 0x0170 (368)
+0x83AD, 0x734B, 0x62C9, 0x7B6C, 0xACD1, 0xACD1, 0x93EE, 0x6268, 0x51E6, 0x83AD, 0x9C4F, 0x72EA, 0x5A27, 0x49A5, 0x5207, 0x41A6,   // 0x0180 (384)
+0x3945, 0x20C3, 0x2082, 0x20A2, 0x2081, 0x28E2, 0x3144, 0x28E2, 0x3985, 0x3144, 0x28E3, 0x20C3, 0x20E3, 0x1040, 0x1040, 0x20C2,   // 0x0190 (400)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0820, 0x0000, 0x0000, 0x0000, 0x0820, 0x0800, 0x0000,   // 0x01A0 (416)
+0x18C3, 0x736E, 0x8C72, 0xAD36, 0xC619, 0xD67B, 0xD69B, 0xE6FC, 0xEF3D, 0xEEFC, 0xE71B, 0xE6B9, 0xCE37, 0xBD74, 0x940E, 0x838C,   // 0x01B0 (432)
+0x940E, 0xA4B0, 0xA4B0, 0x942E, 0x6288, 0x5A47, 0xA4B1, 0x7B6C, 0x942F, 0xCDD6, 0x8BEE, 0x9C70, 0x6AEA, 0x9C70, 0x942F, 0xA491,   // 0x01C0 (448)
+0xA4B1, 0x62A9, 0x6AC9, 0x83AD, 0xACB1, 0xACB1, 0x93EE, 0x62A8, 0x72C9, 0x8BAD, 0xA470, 0xA470, 0x942F, 0x7B6C, 0x730B, 0x5207,   // 0x01D0 (464)
+0x3124, 0x20A2, 0x1040, 0x1881, 0x3964, 0x5247, 0x62C9, 0x62A9, 0x49E7, 0x5A69, 0x8C10, 0xAD14, 0xC5D7, 0xACF4, 0x5A89, 0x20E3,   // 0x01E0 (480)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0800, 0x0841,   // 0x01F0 (496)
+0x0820, 0x6B2D, 0xA4F5, 0xB597, 0xC63A, 0xD67C, 0xD69C, 0xCE7B, 0xCE39, 0xCE79, 0xD699, 0xD678, 0xBD95, 0xA4B1, 0x8BCD, 0x7B2A,   // 0x0200 (512)
+0x9C6F, 0xACF1, 0x9C4F, 0x6AC9, 0x41A5, 0x7B6C, 0xA491, 0x5227, 0x7B4B, 0xC5B5, 0xACD2, 0x83AD, 0x9C4F, 0xC5B5, 0x5A68, 0x5A47,   // 0x0210 (528)
+0xACD2, 0x836C, 0x51E6, 0x6AA9, 0xA46F, 0xACB0, 0x9C4E, 0x7B2A, 0x836B, 0x93EE, 0xA490, 0xBD53, 0xCDD5, 0xACB1, 0x732B, 0x49E6,   // 0x0220 (544)
+0x28E2, 0x1020, 0x0800, 0x2902, 0x5247, 0x5A88, 0x62A9, 0x734D, 0xA4D3, 0xDE7A, 0xDEBB, 0xDEBB, 0xCE18, 0xAD14, 0x9CD2, 0x4207,   // 0x0230 (560)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0820, 0x0000, 0x0800, 0x0000, 0x0800,   // 0x0240 (576)
+0x0800, 0x41C7, 0xAD35, 0xB577, 0xC61A, 0xBDD9, 0xBE1A, 0xC63A, 0xC619, 0xBDF8, 0xD699, 0xD658, 0xB533, 0xA470, 0x9C0E, 0x8BAD,   // 0x0250 (592)
+0x8BAD, 0xA490, 0x9C70, 0x730A, 0x6AE9, 0xACF2, 0xACF2, 0x8BEE, 0x838C, 0xCDF6, 0x9C70, 0x9C4F, 0xC574, 0xB4F2, 0x72EA, 0x7B4C,   // 0x0260 (608)
+0xB533, 0xACF2, 0x5206, 0x7B4B, 0x9C4F, 0xB4D1, 0x9C4F, 0x940E, 0x93CD, 0x9C0E, 0xACB0, 0xB513, 0xCDF6, 0xD617, 0xC5D5, 0xBD95,   // 0x0270 (624)
+0x8BEE, 0x6289, 0x6288, 0x7B8C, 0x8C0E, 0xA4B1, 0xC5B5, 0xDE9A, 0xD65A, 0xC5B8, 0xB556, 0x9CB4, 0x7BAF, 0x630C, 0x6B4C, 0x3185,   // 0x0280 (640)
+0x0000, 0x0800, 0x0820, 0x0820, 0x0800, 0x0800, 0x0800, 0x0820, 0x0800, 0x0800, 0x0820, 0x0820, 0x0800, 0x0000, 0x0800, 0x0820,   // 0x0290 (656)
+0x1060, 0x1041, 0x8BF1, 0xCE1A, 0xB598, 0xC61A, 0xCE5B, 0xCE3A, 0xD67B, 0xCE39, 0xDE79, 0xC5B5, 0xA4B0, 0x942E, 0x7B6B, 0x838C,   // 0x02A0 (672)
+0x836C, 0x940E, 0xB513, 0x9450, 0x9430, 0xCDF7, 0xD658, 0xA4B1, 0x8BAD, 0xACB1, 0x9C2E, 0xAC90, 0xBD73, 0x7B4C, 0x944F, 0xC5D6,   // 0x02B0 (688)
+0xCDD6, 0xBD13, 0x8BAD, 0x93EE, 0xA490, 0xACB1, 0xB4D1, 0xA42E, 0x9BED, 0xA40D, 0x9BED, 0xAC6F, 0xCD94, 0xDE99, 0xDEBA, 0xE6DB,   // 0x02C0 (704)
+0xE6DB, 0xE6DB, 0xDE9A, 0xCE39, 0xDE7A, 0xE6BC, 0xCE3A, 0xC5F9, 0xBDB8, 0xA515, 0x9452, 0x734E, 0x62EC, 0x9CB3, 0x734D, 0x20C3,   // 0x02D0 (720)
+0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0820, 0x0820, 0x0800, 0x0800, 0x0820, 0x0820, 0x0800, 0x0800, 0x0820, 0x1020,   // 0x02E0 (736)
+0x1861, 0x1041, 0x522A, 0xD67C, 0xC61A, 0xCE5B, 0xD67B, 0xDEDD, 0xDEBC, 0xD67A, 0xC5D7, 0xBD74, 0xA4B0, 0x83AC, 0x6AC9, 0x5A27,   // 0x02F0 (752)
+0x6288, 0xA490, 0xAD12, 0x940F, 0x9C70, 0xCDD7, 0xE6DA, 0xB4F2, 0x93EE, 0x8BAD, 0x836C, 0x942E, 0xACD1, 0x7B6C, 0xC5B5, 0xE6DA,   // 0x0300 (768)
+0xDE37, 0xACD2, 0x8BCD, 0x9C90, 0xA4D2, 0x838D, 0x838C, 0x940E, 0x9BED, 0x93CC, 0x93AC, 0x9C2E, 0xBD53, 0xDE78, 0xDE99, 0xC5F8,   // 0x0310 (784)
+0xC5D7, 0xBDB7, 0xC5D7, 0xD65A, 0xCE3A, 0xCE19, 0xCE5A, 0xCE1A, 0xB577, 0x9CD4, 0x9CB4, 0x9CB3, 0xBD97, 0xAD35, 0x3986, 0x28E4,   // 0x0320 (800)
+0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x1040,   // 0x0330 (816)
+0x1061, 0x1061, 0x3186, 0xCE1A, 0xDEDC, 0xCE3A, 0xDEDD, 0xE6FD, 0xD65A, 0xC5B7, 0xB554, 0xB513, 0xACF1, 0x83AC, 0x51E6, 0x3102,   // 0x0340 (832)
+0x5A47, 0xB533, 0xACD2, 0x4A07, 0x8C0F, 0xD638, 0xE6DA, 0xC5B5, 0x8BEE, 0x838C, 0x9C4F, 0x9C4F, 0x9C70, 0x9C90, 0xE6D9, 0xEEFA,   // 0x0350 (848)
+0xCDF6, 0x838C, 0x732B, 0xACF2, 0xACF2, 0x6AEA, 0x49E6, 0x7B0A, 0x8BAC, 0x9C0E, 0xA42F, 0xA44F, 0xACF2, 0xCDD6, 0xC5F7, 0xB555,   // 0x0360 (864)
+0xB576, 0xC5F8, 0xCE39, 0xD67B, 0xD67B, 0xD69B, 0xD69C, 0xCE5B, 0xC5FA, 0xB598, 0xBDB8, 0xCE19, 0xD67A, 0x6B0C, 0x18A2, 0x28E3,   // 0x0370 (880)
+0x1020, 0x0820, 0x0820, 0x0820, 0x0820, 0x1020, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x1020,   // 0x0380 (896)
+0x1040, 0x1061, 0x2904, 0xB576, 0xDEDC, 0xC61A, 0xDEBC, 0xE6FD, 0xCE18, 0xB534, 0xBD74, 0xB512, 0xA4B1, 0x836C, 0x5A48, 0x5A48,   // 0x0390 (912)
+0x4164, 0xACD2, 0xBD54, 0x3985, 0x83CE, 0xE6DA, 0xFF9D, 0xD657, 0xBD53, 0xACD1, 0xB532, 0xBD53, 0xBD73, 0xD637, 0xEF3B, 0xEEFA,   // 0x03A0 (928)
+0xAD12, 0x41C5, 0x62C9, 0xC595, 0xC5B5, 0x6AC9, 0x3122, 0x51E5, 0x72C9, 0x9BED, 0xAC90, 0xA490, 0xB512, 0xCDB5, 0xC5B6, 0xBD96,   // 0x03B0 (944)
+0xC5D7, 0xCE5A, 0xD69B, 0xCE3A, 0xC63A, 0xC61A, 0xC5FA, 0xCE7B, 0xCE3A, 0xCE3A, 0xD67B, 0xEF1D, 0xB596, 0x3145, 0x3124, 0x20E3,   // 0x03C0 (960)
+0x0820, 0x0800, 0x0800, 0x0820, 0x1020, 0x1020, 0x1020, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820,   // 0x03D0 (976)
+0x1061, 0x0840, 0x20E3, 0xA4F4, 0xEF5E, 0xBDB8, 0xBD97, 0xDE9B, 0xDE79, 0xB513, 0xACF2, 0xACF2, 0xA491, 0x8BCE, 0x93EE, 0xA491,   // 0x03E0 (992)
+0x940F, 0x8BCE, 0xC5D6, 0x7B6C, 0x9450, 0xEF3C, 0xFF9D, 0xE6B9, 0xDE57, 0xD616, 0xC594, 0xD616, 0xDE78, 0xE6FA, 0xFFBD, 0xEF1A,   // 0x03F0 (1008)
+0x942F, 0x3984, 0x838C, 0xCDF6, 0x7B4B, 0x4163, 0x4163, 0x4984, 0x5205, 0x8BAC, 0xBCF1, 0xBCF1, 0xBCF2, 0xC533, 0xC574, 0xCDD6,   // 0x0400 (1024)
+0xD679, 0xD69A, 0xDEBB, 0xD69B, 0xD67B, 0xCE5B, 0xC5F9, 0xBDD9, 0xCE5B, 0xDE9C, 0xDEDC, 0xDEDC, 0x62CB, 0x18A2, 0x28E3, 0x20E2,   // 0x0410 (1040)
+0x0820, 0x0820, 0x0820, 0x1021, 0x1041, 0x1041, 0x1041, 0x1041, 0x1021, 0x1021, 0x1021, 0x1041, 0x1041, 0x1021, 0x1021, 0x1021,   // 0x0420 (1056)
+0x1040, 0x1061, 0x1061, 0x4A28, 0xE6DC, 0xE6BC, 0xD67A, 0xD619, 0xC5D6, 0xBD53, 0xB533, 0xACD1, 0xA491, 0xBD54, 0xB554, 0xB513,   // 0x0430 (1072)
+0xC5B5, 0xBD95, 0xDE99, 0xBD75, 0xC5D6, 0xFF9D, 0xF79D, 0xDEB9, 0xD637, 0xDE98, 0xDE77, 0xDE77, 0xDE98, 0xEF1B, 0xFFDE, 0xE71B,   // 0x0440 (1088)
+0x9450, 0x6AEA, 0xD616, 0x9C70, 0x6AC9, 0x838C, 0x9C4F, 0x8BAC, 0x834B, 0x9C0D, 0xBD11, 0xBD32, 0xC532, 0xC533, 0xBD12, 0xB4F2,   // 0x0450 (1104)
+0xB554, 0xDE9A, 0xEF3D, 0xF75E, 0xEF3E, 0xE6DD, 0xD65B, 0xC5D9, 0xC5F9, 0xDE9B, 0xEF3E, 0xCE39, 0x39A6, 0x2904, 0x28E3, 0x2903,   // 0x0460 (1120)
+0x1040, 0x1040, 0x1040, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041,   // 0x0470 (1136)
+0x1040, 0x1881, 0x1061, 0x2924, 0xBD96, 0xE6BC, 0xD639, 0xC5B6, 0xBD54, 0xBD53, 0xC594, 0xB512, 0xB4F3, 0xCDF7, 0xDE99, 0xE6B9,   // 0x0480 (1152)
+0xD658, 0xD658, 0xF77D, 0xFFBE, 0xEF3C, 0xFFBE, 0xF79D, 0xDEB9, 0xDE78, 0xE6B9, 0xE6D9, 0xD657, 0xDE98, 0xF75C, 0xFFDE, 0xF77D,   // 0x0490 (1168)
+0xBDD6, 0xCE37, 0xE6DA, 0xCDF6, 0xD617, 0xC594, 0xBD53, 0xB512, 0xACD1, 0xACD1, 0xBD33, 0xBD33, 0xC573, 0xC553, 0xBCF1, 0xACB1,   // 0x04A0 (1184)
+0xBD54, 0xD637, 0xDEBA, 0xEEFB, 0xE6DB, 0xC5D8, 0xB556, 0xB557, 0xCE1A, 0xDE9B, 0xDEBB, 0x8C10, 0x3145, 0x3144, 0x2903, 0x20C2,   // 0x04B0 (1200)
+0x1041, 0x1041, 0x1041, 0x1040, 0x1040, 0x1040, 0x1040, 0x1040, 0x1040, 0x1041, 0x1041, 0x1041, 0x1040, 0x1040, 0x1041, 0x1041,   // 0x04C0 (1216)
+0x1061, 0x1040, 0x18A2, 0x20C2, 0x9451, 0xE6DC, 0xC5D8, 0xA492, 0xB513, 0xCDD5, 0xBD73, 0xA490, 0xBD75, 0xCDF7, 0xD637, 0x9450,   // 0x04D0 (1232)
+0x41C6, 0x5269, 0x736D, 0xBDD6, 0xFFDE, 0xFFFF, 0xF79D, 0xCE58, 0xD678, 0xEEFA, 0xE6B9, 0xD637, 0xDE99, 0xF77C, 0xFFFF, 0xFFBE,   // 0x04E0 (1248)
+0xFFDF, 0xE6FB, 0xBDB6, 0xBD75, 0xBD95, 0xE6B9, 0xDE78, 0xD637, 0xC5D5, 0xBD54, 0xB512, 0xACD2, 0xC594, 0xCD94, 0xB511, 0xB4F1,   // 0x04F0 (1264)
+0xBD33, 0xB513, 0xD637, 0xE6BA, 0xCDF7, 0xB535, 0xB576, 0xD639, 0xD67A, 0xEF1D, 0xCE39, 0x41E8, 0x2904, 0x3144, 0x2102, 0x2943,   // 0x0500 (1280)
+0x0820, 0x1041, 0x1041, 0x1040, 0x1040, 0x1041, 0x1040, 0x0820, 0x1040, 0x1041, 0x1041, 0x1040, 0x1040, 0x1040, 0x1041, 0x1041,   // 0x0510 (1296)
+0x1061, 0x1881, 0x20C2, 0x20E2, 0x6B0B, 0xC5B5, 0x9C4F, 0x9C4F, 0xACB0, 0xB4D1, 0xC553, 0xC595, 0xBD54, 0xBD54, 0xACF2, 0x4A28,   // 0x0520 (1312)
+0x3A08, 0x2165, 0x2966, 0x39E8, 0x94B2, 0xFFFF, 0xFFBD, 0xDEB9, 0xDEB9, 0xE6F9, 0xE6FA, 0xD657, 0xE6FA, 0xFFDE, 0xFFDE, 0xFFFF,   // 0x0530 (1328)
+0x9CD3, 0x4A69, 0x41E7, 0x41E7, 0x4207, 0x5A8A, 0xBD95, 0xE6DA, 0xDE57, 0xCDD5, 0xBD52, 0xB511, 0xCDB4, 0xCDB4, 0xC594, 0xC594,   // 0x0540 (1344)
+0xC532, 0xA44F, 0xB4F2, 0xD638, 0xC5D7, 0xC5F8, 0xD69B, 0xDEFC, 0xE6FC, 0xEF5D, 0x7B8E, 0x20E3, 0x18A2, 0x2903, 0x2944, 0x2944,   // 0x0550 (1360)
+0x1040, 0x1041, 0x1061, 0x1041, 0x1041, 0x1061, 0x1061, 0x1041, 0x1041, 0x1041, 0x1041, 0x1061, 0x1041, 0x1040, 0x1041, 0x1061,   // 0x0560 (1376)
+0x1882, 0x20C2, 0x20E3, 0x2902, 0x39A5, 0x838C, 0x83AC, 0x940E, 0x93ED, 0x93CD, 0x8BAC, 0x8BAD, 0x9C50, 0xCE37, 0xB574, 0x632C,   // 0x0570 (1392)
+0x29C7, 0x0062, 0x08C3, 0x4A8B, 0x634D, 0xE71C, 0xFFFF, 0xDEDA, 0xDE99, 0xE6DA, 0xE6D9, 0xDEB9, 0xEF5C, 0xFFDE, 0xFFFF, 0xCE59,   // 0x0580 (1408)
+0x632D, 0x4A6A, 0x10C3, 0x18E4, 0x632C, 0x5AAA, 0x5269, 0xB574, 0xCDF6, 0xB533, 0xCDD5, 0xCDB5, 0xC573, 0xBD53, 0xC574, 0xB4F1,   // 0x0590 (1424)
+0xB4D0, 0x9BED, 0x7B4B, 0xA4B1, 0xC5D7, 0xC5D7, 0xCE39, 0xD67B, 0xDEBB, 0xBD97, 0x41C7, 0x1040, 0x1881, 0x20E3, 0x3144, 0x3144,   // 0x05A0 (1440)
+0x1061, 0x1061, 0x1061, 0x1061, 0x1881, 0x1881, 0x1881, 0x1881, 0x1061, 0x1061, 0x1061, 0x1881, 0x1881, 0x1061, 0x1061, 0x1881,   // 0x05B0 (1456)
+0x20C2, 0x20C2, 0x20E2, 0x3144, 0x6289, 0x83AC, 0x8BAC, 0x93CD, 0x6267, 0x2060, 0x3943, 0x6AA9, 0xCDF6, 0xFF7D, 0x840F, 0x4A69,   // 0x05C0 (1472)
+0x08A3, 0x0084, 0x4ACC, 0x73F0, 0x5B0D, 0xAD56, 0xFFFF, 0xEF3C, 0xDEDA, 0xE6FB, 0xE6DA, 0xE6DA, 0xF79D, 0xFFFF, 0xEF5D, 0x8410,   // 0x05D0 (1488)
+0x6BAF, 0x08A4, 0x29A7, 0x31E9, 0x1925, 0x8C92, 0x5269, 0x9C92, 0xBD74, 0x83AD, 0x8BEE, 0xB512, 0xCDB5, 0xCD94, 0xC574, 0xC553,   // 0x05E0 (1504)
+0xBD11, 0xB4D1, 0x8B8C, 0x836C, 0xACF3, 0xC5D7, 0xCE18, 0xD659, 0xC5D7, 0xAD34, 0x5249, 0x1881, 0x20A2, 0x3144, 0x3164, 0x41C6,   // 0x05F0 (1520)
+0x1881, 0x1881, 0x1881, 0x1882, 0x18A2, 0x1882, 0x1882, 0x18A2, 0x1882, 0x1881, 0x1881, 0x18A2, 0x18A2, 0x1882, 0x1881, 0x1881,   // 0x0600 (1536)
+0x20A2, 0x20E3, 0x2903, 0x3964, 0x6AEA, 0x838C, 0x8BAC, 0x72C9, 0x3922, 0x5A27, 0x72C9, 0x7B4C, 0xE6DA, 0xFF9D, 0x630B, 0x4A69,   // 0x0610 (1552)
+0x2166, 0x10E5, 0x2167, 0x5B2D, 0x6B8F, 0x7BF0, 0xF7BF, 0xF77D, 0xE71B, 0xE6DA, 0xE6FA, 0xEF3C, 0xFFFF, 0xFF9E, 0x7B8E, 0x4209,   // 0x0620 (1568)
+0x6B8F, 0x00A4, 0x3A2A, 0x426B, 0x2187, 0x8452, 0x528A, 0xB555, 0xF77D, 0xB533, 0x730A, 0x5A27, 0x6268, 0x7B4B, 0x940F, 0xB4D1,   // 0x0630 (1584)
+0xC553, 0xB4B0, 0xAC90, 0x8BAD, 0x940F, 0xCDD6, 0xCDF7, 0xB555, 0x9C92, 0x6AEB, 0x3165, 0x3985, 0x39A5, 0x41C6, 0x41E6, 0x3164,   // 0x0640 (1600)
+0x18A2, 0x18A1, 0x18A1, 0x18A2, 0x18A2, 0x18A1, 0x1881, 0x18A2, 0x18A2, 0x18A2, 0x18A1, 0x18A1, 0x18A2, 0x18A2, 0x1881, 0x1881,   // 0x0650 (1616)
+0x18A1, 0x20C2, 0x28E2, 0x3964, 0x5206, 0x6AC9, 0x7B4B, 0x4184, 0x4984, 0x72C9, 0x6AA9, 0x72EB, 0xC5B5, 0xFF9D, 0xC5D6, 0x4A69,   // 0x0660 (1632)
+0x3A08, 0x3A09, 0x5ACC, 0x73AF, 0x526A, 0x3986, 0xAD14, 0xE6DA, 0xDEB9, 0xCDF6, 0xEEFA, 0xEEDA, 0xEEFA, 0xA4B1, 0x4A07, 0x39A7,   // 0x0670 (1648)
+0x634E, 0x426B, 0x1105, 0x2146, 0x5B4D, 0x6B6E, 0x4A49, 0xDEDB, 0xFFBE, 0xDE58, 0x940F, 0x7B2B, 0x5A27, 0x3102, 0x28E2, 0x49C6,   // 0x0680 (1664)
+0x72E9, 0x836C, 0x93EE, 0x8BAD, 0x8BCE, 0xC574, 0xACB2, 0x6ACA, 0x4A07, 0x2904, 0x39A6, 0x5249, 0x5268, 0x5A69, 0x41C6, 0x3964,   // 0x0690 (1680)
+0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x18A1, 0x18A1, 0x18A1, 0x18A1, 0x18A1, 0x18A1, 0x1881, 0x18A1, 0x18A1, 0x18A1, 0x1881,   // 0x06A0 (1696)
+0x1881, 0x20C2, 0x2923, 0x3985, 0x49E6, 0x5227, 0x3103, 0x3964, 0x7B2B, 0x4184, 0x49C6, 0x51E6, 0x732B, 0xBD74, 0xF75C, 0xF73B,   // 0x06B0 (1712)
+0xDE99, 0xE6FB, 0xFF9D, 0xF73C, 0x732C, 0x41A5, 0x83AD, 0xC594, 0xCDB5, 0xC5B4, 0xD616, 0xC594, 0x730A, 0x3923, 0x51E6, 0x83CE,   // 0x06C0 (1728)
+0xB5B6, 0xA535, 0x8431, 0x73AF, 0x73AE, 0x6B6D, 0xCE38, 0xFFBE, 0xF73B, 0xACB1, 0x6288, 0x7B4B, 0xA491, 0x940F, 0x5207, 0x1860,   // 0x06D0 (1744)
+0x28A1, 0x4165, 0x6AA9, 0x838D, 0x730B, 0xACD2, 0xCDD6, 0x7B6D, 0x1861, 0x20C2, 0x3185, 0x5269, 0x62EA, 0x62EA, 0x41E6, 0x2902,   // 0x06E0 (1760)
+0x20E2, 0x20E2, 0x20E2, 0x20E2, 0x20E2, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x20A2, 0x20C2, 0x20C2, 0x20C2,   // 0x06F0 (1776)
+0x2903, 0x2902, 0x2903, 0x3144, 0x5228, 0x4A27, 0x1040, 0x5A89, 0xBD75, 0x838D, 0x5227, 0x836C, 0x7B6C, 0x7B4B, 0x9C4F, 0xC594,   // 0x0700 (1792)
+0xD657, 0xDE98, 0xD617, 0xB4F2, 0x6268, 0x8B8C, 0x8BAD, 0xB512, 0xB4D1, 0xB4F1, 0xBD32, 0xA44F, 0x6288, 0x3943, 0x51E6, 0xCDB5,   // 0x0710 (1808)
+0xFFFE, 0xFFFE, 0xFFDE, 0xF77D, 0xEF1B, 0xF73C, 0xEF1A, 0xDE78, 0xA490, 0x5A47, 0x6AC9, 0x836C, 0x62A8, 0x732B, 0x9450, 0x732B,   // 0x0720 (1824)
+0x3144, 0x3104, 0x4A07, 0x838D, 0x7B4B, 0x8BCE, 0xB533, 0x9C91, 0x41A6, 0x1040, 0x2924, 0x4A48, 0x5AA9, 0x62EA, 0x5247, 0x3164,   // 0x0730 (1840)
+0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x28E3, 0x2903, 0x20E2, 0x20E2, 0x20E2, 0x20E2, 0x20C2, 0x20E2, 0x2923,   // 0x0740 (1856)
+0x3123, 0x3143, 0x3964, 0x3164, 0x2923, 0x18A2, 0x1881, 0x5A8A, 0xB554, 0x8BEF, 0x41A5, 0x6268, 0x836C, 0x838C, 0x834A, 0xA46F,   // 0x0750 (1872)
+0xB512, 0xA490, 0x836C, 0x7B2B, 0xACD1, 0xC594, 0xA42E, 0xB4B0, 0xA44E, 0xACB0, 0xACAF, 0xB4F1, 0x9C2E, 0x72EA, 0x49C5, 0x7B4C,   // 0x0760 (1888)
+0xBD73, 0xDE57, 0xDE78, 0xD657, 0xD637, 0xBD74, 0xACD1, 0xA470, 0x9C4F, 0x9C4F, 0xA470, 0x7B4B, 0x7B6B, 0x7B6C, 0x9C91, 0xCE38,   // 0x0770 (1904)
+0x83EF, 0x5228, 0x5228, 0x730B, 0x7B6C, 0x838D, 0x8BEE, 0xA4B1, 0x6B2B, 0x3165, 0x3165, 0x3185, 0x3165, 0x5248, 0x5A89, 0x39A5,   // 0x0780 (1920)
+0x2903, 0x2923, 0x2923, 0x2923, 0x2903, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2903, 0x2903, 0x2903, 0x2903,   // 0x0790 (1936)
+0x3144, 0x3123, 0x3985, 0x4A08, 0x3165, 0x3144, 0x5A8A, 0xB554, 0x8C0F, 0x49C6, 0x5207, 0x5227, 0x6ACA, 0x732B, 0xAD12, 0xE6B9,   // 0x07A0 (1952)
+0xBD94, 0x5227, 0x5207, 0xB554, 0xEF1B, 0xACF2, 0x7B4C, 0x838D, 0x8BCE, 0x8BCE, 0x83CD, 0x944F, 0xCE36, 0xE697, 0xACD0, 0x6267,   // 0x07B0 (1968)
+0x6268, 0xA490, 0xC574, 0xBD53, 0xBD53, 0xB4D1, 0xA470, 0x8BCD, 0x8BAD, 0x836C, 0x6288, 0x732B, 0xBD54, 0xE6B9, 0xE6DA, 0xE6FB,   // 0x07C0 (1984)
+0xCE17, 0x6AEC, 0x3985, 0x3986, 0x41C6, 0x62A9, 0x7B6C, 0x9450, 0x7B8D, 0x5248, 0x4A07, 0x4A48, 0x4207, 0x3185, 0x3164, 0x2943,   // 0x07D0 (2000)
+0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x20E2, 0x20E2,   // 0x07E0 (2016)
+0x3123, 0x41A6, 0x4A28, 0x5269, 0x4A28, 0x5269, 0x9451, 0xB554, 0xB554, 0x838D, 0x6ACA, 0x7B6C, 0x62A9, 0x9450, 0xD658, 0xE6B9,   // 0x07F0 (2032)
+0xD678, 0xC5D6, 0xBD95, 0xD678, 0xFFDE, 0x9430, 0x4185, 0x6248, 0x72EA, 0x5A48, 0x4A06, 0x5247, 0xD657, 0xFF9C, 0xE678, 0x72EA,   // 0x0800 (2048)
+0x49A5, 0x6ACA, 0xCDF6, 0xD5F6, 0xC595, 0xB533, 0xACD1, 0xACB1, 0xA470, 0x9C2F, 0x6AEA, 0x6AEA, 0x8BEE, 0x9C50, 0xACF3, 0xDE9A,   // 0x0810 (2064)
+0xEF1C, 0xB575, 0x5A8A, 0x3985, 0x3985, 0x3124, 0x4A07, 0x734C, 0x734C, 0x5AAA, 0x6B4C, 0x62EB, 0x3185, 0x10A1, 0x20E2, 0x3185,   // 0x0820 (2080)
+0x2903, 0x2923, 0x2923, 0x2923, 0x2903, 0x2923, 0x2923, 0x2923, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x28E3, 0x28E3,   // 0x0830 (2096)
+0x2923, 0x3985, 0x4A28, 0x5A89, 0x5269, 0x5AAA, 0xA4B2, 0x9430, 0x734C, 0x9C91, 0x8BEE, 0x734C, 0x9450, 0xBD75, 0xD679, 0xE6FB,   // 0x0840 (2112)
+0xEF3C, 0xEF5C, 0xFFFE, 0xFFBE, 0xFFFE, 0xD659, 0x3965, 0x5A28, 0x5A49, 0x5228, 0x5227, 0x8C0F, 0xFF7C, 0xFF7D, 0xDE38, 0xEEBA,   // 0x0850 (2128)
+0xDE78, 0xC5B6, 0xC5B6, 0xEF1B, 0xE6B9, 0xC5B6, 0xACF2, 0x8BEE, 0x7B4C, 0x732B, 0x6AEA, 0x6AEA, 0x62CA, 0x6B0B, 0x9C70, 0xDE79,   // 0x0860 (2144)
+0xE6DB, 0xE6FC, 0xB575, 0x6AEB, 0x41C6, 0x41A6, 0x5A69, 0x83CE, 0x5AAA, 0x5269, 0x6B2C, 0x4A49, 0x2123, 0x18A2, 0x3164, 0x4A28,   // 0x0870 (2160)
+0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2923, 0x2903, 0x2903, 0x2923, 0x2923, 0x2903, 0x2903, 0x2923,   // 0x0880 (2176)
+0x3144, 0x3985, 0x5269, 0x6B2C, 0x736D, 0x7BAE, 0x83CE, 0x5A89, 0x5269, 0x734C, 0x9C71, 0x8BEF, 0x83CE, 0xB554, 0xD638, 0xD679,   // 0x0890 (2192)
+0xE6DB, 0xE71C, 0xF79D, 0xFFDE, 0xFFDE, 0xFFBE, 0x9C71, 0x49C7, 0x4186, 0x49C7, 0x9451, 0xFF9D, 0xFFFF, 0xFFDE, 0xFFFF, 0xDEBA,   // 0x08A0 (2208)
+0xDEBA, 0xF75C, 0xE6FB, 0xDEBA, 0xEF3C, 0xE6DB, 0xCDD6, 0xC5D6, 0xB534, 0x734C, 0x6AEB, 0xAD13, 0xC5D6, 0xAD13, 0x9C91, 0x9450,   // 0x08B0 (2224)
+0xC5F7, 0xDEBB, 0xE6FB, 0xD638, 0xA4D3, 0x732C, 0x7B8D, 0x8BEF, 0x6B2C, 0x5AAA, 0x6B2C, 0x6B2C, 0x5289, 0x2965, 0x2944, 0x41E6,   // 0x08C0 (2240)
+0x28E3, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2923, 0x2923,   // 0x08D0 (2256)
+0x3164, 0x3965, 0x41C6, 0x62CA, 0x736D, 0x62EB, 0x41E7, 0x41C7, 0x3145, 0x3986, 0x62CB, 0x9450, 0x9C71, 0xB535, 0xB555, 0xBDB6,   // 0x08E0 (2272)
+0xE6BB, 0xEF3D, 0xF79E, 0xF77D, 0xEF5D, 0xEEFC, 0xDE79, 0x93F0, 0x4165, 0x8BCF, 0xDEBA, 0xF77D, 0xF7DE, 0xFFFF, 0xF7DE, 0xE73C,   // 0x08F0 (2288)
+0xE6FB, 0xEF1C, 0xE6DB, 0xE6FB, 0xDEBA, 0xD679, 0xCE18, 0xBD96, 0xC5B6, 0xC5B6, 0xC5B6, 0xDE79, 0xBD74, 0x6B0B, 0x49E7, 0x41A6,   // 0x0900 (2304)
+0x734C, 0xB575, 0xDE9A, 0xCDF7, 0xACF3, 0x9410, 0x83CF, 0x6B2C, 0x5269, 0x62CB, 0x7BCF, 0x8C30, 0x7BCE, 0x5ACB, 0x5289, 0x4207,   // 0x0910 (2320)
+0x20E2, 0x20E2, 0x20E2, 0x20E2, 0x2103, 0x2103, 0x2903, 0x2903, 0x2103, 0x2903, 0x2903, 0x2903, 0x2903, 0x2103, 0x2903, 0x2923,   // 0x0920 (2336)
+0x3144, 0x4A07, 0x5289, 0x5A89, 0x52A9, 0x5269, 0x39A6, 0x20C2, 0x20E3, 0x4A28, 0x734C, 0x8BEF, 0x83CF, 0x9431, 0xB555, 0xB556,   // 0x0930 (2352)
+0xCDF8, 0xE6DB, 0xEF3C, 0xEF5D, 0xDEDA, 0xD658, 0xDE38, 0xC575, 0x51C7, 0xB4D3, 0xE679, 0xE6DA, 0xEF3C, 0xF7BD, 0xF7DE, 0xE75C,   // 0x0940 (2368)
+0xE71B, 0xF77D, 0xE6FB, 0xCE17, 0xCE38, 0xCE38, 0xCE18, 0xA4B2, 0xA4D3, 0xBD96, 0xB555, 0xAD14, 0x8C10, 0x5A8A, 0x41A6, 0x2924,   // 0x0950 (2384)
+0x3965, 0x62AA, 0x838E, 0x8C0F, 0x8C0F, 0x83AE, 0x83CE, 0x734D, 0x6B0C, 0x6B2C, 0x83EF, 0x9492, 0x8C51, 0x83EF, 0x7BCE, 0x62EB,   // 0x0960 (2400)
+0x2103, 0x2103, 0x20E2, 0x2103, 0x20E2, 0x20E2, 0x20E2, 0x20E2, 0x20E2, 0x20E2, 0x2903, 0x2103, 0x20E2, 0x20E2, 0x20E2, 0x2903,   // 0x0970 (2416)
+0x3164, 0x41C6, 0x5268, 0x5AA9, 0x5269, 0x5289, 0x5AAA, 0x4A48, 0x5AAA, 0x736D, 0x7BAE, 0xACF3, 0xCDF8, 0xCDF8, 0xC5F8, 0xBD97,   // 0x0980 (2432)
+0xA493, 0xB535, 0xCE38, 0xDE9A, 0xC5F7, 0xACD3, 0x8B8E, 0x6A29, 0x38A2, 0x59A6, 0x93AF, 0xC554, 0xDE59, 0xEEFB, 0xF75D, 0xEF3C,   // 0x0990 (2448)
+0xF73C, 0xE6DA, 0xCE18, 0xD659, 0xD659, 0xCE38, 0xCE18, 0xD679, 0xD659, 0xC5D7, 0xB575, 0xC5B7, 0xAD34, 0x8C0F, 0x62EB, 0x5249,   // 0x09A0 (2464)
+0x4A07, 0x41A5, 0x4A07, 0x49E7, 0x6ACA, 0x9410, 0x7B6D, 0x62CB, 0x62CB, 0x734D, 0x83F0, 0x8C31, 0x8C31, 0x8C51, 0x7BAE, 0x5A89,   // 0x09B0 (2480)
+0x3164, 0x3164, 0x2944, 0x2944, 0x2923, 0x2103, 0x2103, 0x2103, 0x20E2, 0x2103, 0x2103, 0x2102, 0x20E2, 0x20E2, 0x2103, 0x2923,   // 0x09C0 (2496)
+0x3164, 0x39A5, 0x4A27, 0x5248, 0x39A5, 0x3185, 0x4A48, 0x83CE, 0x736D, 0x6B0B, 0x9451, 0xAD34, 0xCE18, 0xE6BB, 0xEF5D, 0xDEBB,   // 0x09D0 (2512)
+0xB535, 0x9451, 0x83EF, 0x83EF, 0x5228, 0x28C2, 0x2841, 0x3041, 0x48E3, 0x4062, 0x3841, 0x4924, 0x7269, 0x9BEF, 0xC534, 0xC596,   // 0x09E0 (2528)
+0xAD13, 0x8C0F, 0x6B0B, 0x5269, 0xA4F3, 0xDE9A, 0xE6FB, 0xF77D, 0xFF9E, 0xF75D, 0xF75D, 0xEF1C, 0xDE7A, 0xCDF8, 0xA4F3, 0x8C0F,   // 0x09F0 (2544)
+0x734C, 0x62A9, 0x5A69, 0x730B, 0x83AD, 0x7B6D, 0x5A69, 0x5A69, 0x39A6, 0x6B0C, 0x8410, 0x9472, 0x9492, 0x8C30, 0x6AEC, 0x62AB,   // 0x0A00 (2560)
+0x3144, 0x3164, 0x3164, 0x3144, 0x3144, 0x3144, 0x3144, 0x3144, 0x3143, 0x3144, 0x2923, 0x3143, 0x3143, 0x2903, 0x2903, 0x2923,   // 0x0A10 (2576)
+0x3185, 0x41E7, 0x4A48, 0x4A48, 0x3185, 0x20C2, 0x3185, 0x4A49, 0x62EB, 0x6B2D, 0x526A, 0x8C51, 0xB556, 0xD67A, 0xF75D, 0xF73D,   // 0x0A20 (2592)
+0xDE7B, 0xB515, 0x83EE, 0x41E6, 0x1020, 0x1820, 0x38A2, 0x82AA, 0x9B2B, 0x7A07, 0x6124, 0x6104, 0x58A3, 0x6124, 0x5964, 0x61C5,   // 0x0A30 (2608)
+0x6A48, 0x59E7, 0x4186, 0x734D, 0xC5F8, 0xF7BF, 0xF7DF, 0xF7DF, 0xFFDF, 0xFFDE, 0xFF9D, 0xEEFB, 0xCE17, 0xB514, 0x9451, 0x732D,   // 0x0A40 (2624)
+0x62CB, 0x6AEB, 0x6B0B, 0x83AE, 0x83CE, 0x4A07, 0x20E2, 0x2103, 0x2944, 0x62EB, 0x7BCF, 0x8410, 0x7BAE, 0x6B4D, 0x734C, 0x62CA,   // 0x0A50 (2640)
+0x3164, 0x2944, 0x2923, 0x2923, 0x2923, 0x3144, 0x3164, 0x3164, 0x3164, 0x3164, 0x3143, 0x3164, 0x3985, 0x3144, 0x2923, 0x2903,   // 0x0A60 (2656)
+0x3164, 0x4207, 0x4A48, 0x4A48, 0x2944, 0x18A2, 0x18A2, 0x39C7, 0x6B2C, 0x8C31, 0x83D0, 0x83D0, 0x8C11, 0xB535, 0xCE39, 0xEF3D,   // 0x0A70 (2672)
+0xEF3E, 0xDEDC, 0xCE38, 0xAD13, 0x41C7, 0x1821, 0x61E7, 0xD534, 0xD554, 0xDD75, 0xC4D3, 0xABF0, 0xB3CF, 0xAB6D, 0x7248, 0x6A27,   // 0x0A80 (2688)
+0x51A5, 0x5207, 0x83AE, 0xD638, 0xFFFF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF79D, 0xEF3C, 0xD658, 0xB554, 0x9450, 0x734D, 0x7B8E, 0x9451,   // 0x0A90 (2704)
+0x9C92, 0x9C71, 0x83CF, 0x62AA, 0x4A07, 0x3964, 0x3144, 0x2923, 0x3185, 0x5269, 0x738E, 0x630C, 0x5AAA, 0x62EB, 0x5A89, 0x5268,   // 0x0AA0 (2720)
+0x5289, 0x4A28, 0x41E7, 0x39A6, 0x3185, 0x3144, 0x2924, 0x2924, 0x2923, 0x2923, 0x2924, 0x2944, 0x2944, 0x2923, 0x2944, 0x3144,   // 0x0AB0 (2736)
+0x41E7, 0x4A28, 0x5289, 0x5269, 0x4A48, 0x2924, 0x18A2, 0x3986, 0x7B8F, 0x9C93, 0xB556, 0x9452, 0x7BAF, 0x7B8F, 0xACF4, 0xCE59,   // 0x0AC0 (2752)
+0xE73D, 0xE75D, 0xEF5D, 0xFFDF, 0xC597, 0x28C3, 0x7ACB, 0xDD96, 0xD575, 0xE5F8, 0xF679, 0xEDF8, 0xD534, 0xC471, 0xD554, 0x8B2C,   // 0x0AD0 (2768)
+0x4144, 0x6289, 0xC5D6, 0xFF9D, 0xFFBE, 0xF79E, 0xF79E, 0xE71B, 0xDE99, 0xC5B6, 0x9CB1, 0x7B8D, 0x734C, 0x734C, 0x7B8D, 0x9C92,   // 0x0AE0 (2784)
+0xAD14, 0xA4D3, 0x736D, 0x5AAA, 0x5248, 0x41C6, 0x41E6, 0x3165, 0x2944, 0x5269, 0x5ACB, 0x4A28, 0x41C6, 0x4A27, 0x4A07, 0x4A07,   // 0x0AF0 (2800)
+0x7BAE, 0x736D, 0x6B2C, 0x630B, 0x5ACB, 0x5AAA, 0x52A9, 0x5AAA, 0x4A68, 0x4A28, 0x4207, 0x41E7, 0x39C6, 0x39A6, 0x39A6, 0x31A5,   // 0x0B00 (2816)
+0x39C6, 0x4A27, 0x5AA9, 0x62EA, 0x5289, 0x3165, 0x3165, 0x6B0C, 0xA4F4, 0xAD35, 0xBD97, 0xAD15, 0x9431, 0x83CF, 0x83EF, 0x8C51,   // 0x0B10 (2832)
+0xB596, 0xDEFC, 0xEF7E, 0xF79F, 0xFFBF, 0x6AAB, 0x8B6D, 0xCD34, 0xD534, 0xEE18, 0xF659, 0xE5B7, 0xD4F2, 0xCCD2, 0x934D, 0x4145,   // 0x0B20 (2848)
+0x49C7, 0xAD13, 0xF77D, 0xFFDF, 0xF79E, 0xFF9E, 0xEEFC, 0xCE18, 0x9C92, 0x7B8E, 0x6ACA, 0x730B, 0x8BEF, 0x9451, 0x8C30, 0x7B6E,   // 0x0B30 (2864)
+0x6B0C, 0x5AAA, 0x5269, 0x41E7, 0x4A07, 0x5A89, 0x5268, 0x5249, 0x5269, 0x62CB, 0x5AAA, 0x62EB, 0x5289, 0x4A27, 0x4A27, 0x41E6,   // 0x0B40 (2880)
+0x738E, 0x738E, 0x736D, 0x736D, 0x6B4D, 0x736D, 0x738E, 0x7BCF, 0x738E, 0x736D, 0x736D, 0x738D, 0x736D, 0x6B4C, 0x630B, 0x62EB,   // 0x0B50 (2896)
+0x52A9, 0x4A48, 0x5289, 0x4A48, 0x5269, 0x39C7, 0x6B4D, 0x9CD3, 0xB535, 0xA4D4, 0xACF5, 0x8C11, 0x8BF0, 0x6B2D, 0x6B0C, 0x734D,   // 0x0B60 (2912)
+0x7B8E, 0xACF4, 0xE6BB, 0xF75E, 0xFFDF, 0xC5B6, 0x8B4C, 0xC4B2, 0xC492, 0xDD35, 0xE535, 0xDCF4, 0xCC91, 0xB3EE, 0x38C2, 0x3905,   // 0x0B70 (2928)
+0x9CB2, 0xF79E, 0xFFDF, 0xFFBE, 0xF77E, 0xE6DB, 0xC5D7, 0x9431, 0x83AE, 0x838E, 0x9C72, 0xA492, 0xAD14, 0xB534, 0x8C30, 0x5269,   // 0x0B80 (2944)
+0x3986, 0x3165, 0x41C7, 0x3985, 0x3164, 0x5228, 0x4A27, 0x39A6, 0x4A48, 0x7B8E, 0x83EF, 0x6B2C, 0x5289, 0x4A07, 0x3164, 0x41C5,   // 0x0B90 (2960)
+0x738E, 0x73AE, 0x73AE, 0x738E, 0x6B6D, 0x6B6E, 0x738E, 0x7BCF, 0x73AF, 0x738E, 0x7BEF, 0x8410, 0x7BCF, 0x73AE, 0x6B6D, 0x6B4C,   // 0x0BA0 (2976)
+0x632B, 0x5ACA, 0x4A48, 0x52AA, 0x5289, 0x6B4D, 0x8C51, 0xA4F4, 0xACF5, 0xA4F4, 0x8BF1, 0x7B8F, 0x734E, 0x83CF, 0xA4D3, 0xB555,   // 0x0BB0 (2992)
+0xB515, 0xB515, 0x9CB3, 0xD659, 0xEF3D, 0xEF1C, 0x938E, 0xDD95, 0xCCD2, 0xCC92, 0xD4B2, 0xD492, 0xF5B6, 0x71E7, 0x4124, 0xA4B2,   // 0x0BC0 (3008)
+0xFFBF, 0xFFBF, 0xF77E, 0xF75D, 0xDE9A, 0xAD14, 0x9430, 0x8C10, 0xACD3, 0xACF3, 0xB555, 0xB534, 0x9451, 0x5A8A, 0x5A6A, 0x5249,   // 0x0BD0 (3024)
+0x3165, 0x3165, 0x3124, 0x4A07, 0x5248, 0x2903, 0x1061, 0x2904, 0x4A49, 0x6B4D, 0x7BCF, 0x6B2C, 0x5269, 0x3185, 0x2103, 0x5248,   // 0x0BE0 (3040)
+0x738E, 0x7BAF, 0x7BAF, 0x7B8E, 0x738E, 0x738E, 0x738F, 0x7BAF, 0x7BAF, 0x734E, 0x738E, 0x7BCF, 0x7BCF, 0x7BAF, 0x6B4D, 0x630C,   // 0x0BF0 (3056)
+0x5AEB, 0x5ACA, 0x5269, 0x4207, 0x41E7, 0x630C, 0x9492, 0xAD35, 0xBD77, 0xB536, 0xA4D4, 0xAD15, 0xACF4, 0x83CF, 0x9C92, 0xB555,   // 0x0C00 (3072)
+0xCDF8, 0xC5B7, 0x8C10, 0x83EF, 0xC5F8, 0xF73E, 0x72CB, 0x7A8A, 0xB42F, 0xBC70, 0xC471, 0xC4B2, 0xABCF, 0x5145, 0x51E7, 0xDEBA,   // 0x0C10 (3088)
+0xFFBF, 0xF77E, 0xD69A, 0xA4B3, 0x8C10, 0x83CF, 0x7B8D, 0x8C0F, 0x9C91, 0x9C91, 0x9471, 0x8C0F, 0x6B2C, 0x5248, 0x5248, 0x5A69,   // 0x0C20 (3104)
+0x41E7, 0x3985, 0x49E6, 0x41C6, 0x3123, 0x28E2, 0x28E3, 0x41E7, 0x62EB, 0x736D, 0x8C72, 0x83F0, 0x528A, 0x41E7, 0x5289, 0x6B2B,   // 0x0C30 (3120)
+0x738E, 0x7BAF, 0x7BAF, 0x738F, 0x736E, 0x738E, 0x738E, 0x736E, 0x736E, 0x6B2D, 0x736E, 0x7B8F, 0x738E, 0x736E, 0x630C, 0x5ACB,   // 0x0C40 (3136)
+0x52AA, 0x4A68, 0x4227, 0x31A6, 0x39A6, 0x6B2C, 0x9492, 0xAD15, 0xC5B8, 0xC5B8, 0xB556, 0x9452, 0xA4B3, 0x9C92, 0x6B0C, 0x734D,   // 0x0C50 (3152)
+0x9CD3, 0xC618, 0x94B2, 0x5ACB, 0x630D, 0xCDD8, 0xDE19, 0x7AAB, 0x59C5, 0x6A26, 0x830A, 0x61E6, 0x61E7, 0x7ACB, 0xBD55, 0xFF9E,   // 0x0C60 (3168)
+0xF77D, 0xDE9A, 0xA4F3, 0x7BAE, 0x736D, 0x7B8D, 0x732B, 0x5227, 0x5248, 0x5268, 0x4207, 0x5A89, 0x6B2B, 0x8C0F, 0x8BEE, 0x5AA9,   // 0x0C70 (3184)
+0x4A07, 0x5A68, 0x732B, 0x83AD, 0x732B, 0x41A5, 0x20E2, 0x5269, 0x6B4D, 0x7BAF, 0x8C52, 0x7BCF, 0x6B4D, 0x5ACA, 0x5ACA, 0x630B,   // 0x0C80 (3200)
+0x736E, 0x738F, 0x73AF, 0x738E, 0x738F, 0x7BD0, 0x7BD0, 0x738F, 0x73AF, 0x736E, 0x738F, 0x6B6E, 0x6B6D, 0x738E, 0x632C, 0x630C,   // 0x0C90 (3216)
+0x52AA, 0x4A69, 0x39C7, 0x3165, 0x3165, 0x5A8A, 0x9472, 0xBD76, 0xC5D8, 0xBD97, 0xA4B3, 0x8C10, 0x9431, 0x9C92, 0x7B6D, 0x6B0C,   // 0x0CA0 (3232)
+0xB555, 0xCE38, 0xC5F7, 0x9471, 0x5A8A, 0x7B6E, 0xE6BB, 0xEEDC, 0xC598, 0xACF5, 0xA4D3, 0xB534, 0xCE38, 0xE6FB, 0xFFBF, 0xE6DB,   // 0x0CB0 (3248)
+0xBD55, 0x940F, 0x732C, 0x7B6D, 0x732C, 0x730C, 0x6289, 0x3944, 0x3964, 0x5227, 0x62A9, 0x7B8C, 0x944F, 0x7B8D, 0x5A68, 0x5228,   // 0x0CC0 (3264)
+0x6B0C, 0x7BAE, 0x8C0F, 0x83CE, 0x62A9, 0x5227, 0x4207, 0x62CB, 0x6B2D, 0x83F0, 0x9472, 0x7B8F, 0x4A28, 0x41C6, 0x5247, 0x4A06,   // 0x0CD0 (3280)
+0x7BCF, 0x738F, 0x738E, 0x73AF, 0x7BAF, 0x7BD0, 0x83F1, 0x83F1, 0x8411, 0x7BD0, 0x83F0, 0x7BD0, 0x7BCF, 0x7BCF, 0x6B6D, 0x632C,   // 0x0CE0 (3296)
+0x5B0B, 0x52A9, 0x4207, 0x2923, 0x2923, 0x18A2, 0x62EB, 0xA4D3, 0x9C92, 0x7B8E, 0x7B8F, 0xBD76, 0xACF4, 0xB555, 0xB535, 0xA4B2,   // 0x0CF0 (3312)
+0x9C71, 0x9C71, 0xBD95, 0xC5D7, 0xA4B3, 0x732C, 0x83AF, 0xD618, 0xEEFC, 0xEEDB, 0xEF1C, 0xE6DB, 0xEEFC, 0xDE9A, 0xB534, 0x8C30,   // 0x0D00 (3328)
+0x6AEB, 0x62A9, 0x732C, 0x83CE, 0x83AE, 0x6AEB, 0x62AA, 0x62A9, 0x62A9, 0x8BCE, 0x83CE, 0x9C70, 0x83CE, 0x6AEB, 0x6AEB, 0x9430,   // 0x0D10 (3344)
+0xAD34, 0xB575, 0xA4D3, 0x8BEF, 0x83AD, 0x6B0B, 0x5A89, 0x734C, 0x738E, 0x83F0, 0x83F0, 0x630C, 0x5249, 0x41C6, 0x41C5, 0x5227,   // 0x0D20 (3360)
+0x8411, 0x7BD0, 0x73AF, 0x7BD0, 0x7BF0, 0x7BD0, 0x7BF0, 0x83F1, 0x7BF0, 0x7BD0, 0x83F0, 0x8411, 0x8410, 0x8410, 0x7BAF, 0x738E,   // 0x0D30 (3376)
+0x632C, 0x52A9, 0x4207, 0x39C6, 0x2923, 0x18A1, 0x4A27, 0x734C, 0x7B8D, 0x83AE, 0xA4B2, 0xACF4, 0xBD76, 0xC5B7, 0xC5B7, 0xBD55,   // 0x0D40 (3392)
+0xA4D2, 0x838D, 0x9430, 0xACD3, 0xACD3, 0x8BEF, 0x5A68, 0x838D, 0xAD13, 0xCDF7, 0xD659, 0xCDF8, 0xBD76, 0x83AF, 0x41C6, 0x5A89,   // 0x0D50 (3408)
+0x6AEB, 0x83AD, 0xA4B2, 0xAD13, 0xAD14, 0x9C71, 0x83EF, 0x7BAE, 0x9450, 0xB534, 0xB534, 0x9410, 0x730C, 0x838E, 0xACF4, 0xC5D7,   // 0x0D60 (3424)
+0xCE18, 0xBD96, 0x9C71, 0x8C0F, 0x9CB1, 0x734C, 0x5289, 0x734C, 0x7BAF, 0x7BCF, 0x630C, 0x526A, 0x41E7, 0x41C6, 0x5268, 0x5267,   // 0x0D70 (3440)
+0x8431, 0x8411, 0x83F1, 0x83F1, 0x83F1, 0x8411, 0x8411, 0x83F1, 0x83F1, 0x7BF0, 0x8411, 0x8411, 0x7BF0, 0x7BF0, 0x7BCF, 0x7BCF,   // 0x0D80 (3456)
+0x6B6E, 0x5AEB, 0x4208, 0x5249, 0x62EB, 0x6AEB, 0x83CE, 0x9450, 0xA4B2, 0x9C71, 0x9450, 0x9C51, 0xB535, 0xC5B8, 0xCDF8, 0xBD35,   // 0x0D90 (3472)
+0x8BEF, 0x836D, 0x6269, 0x5A48, 0x940F, 0x9C50, 0x7B8C, 0x5A68, 0x41E6, 0x6B0A, 0x6AEB, 0x6AEB, 0x6ACB, 0x5A49, 0x5228, 0x734C,   // 0x0DA0 (3488)
+0x9C92, 0xB535, 0xC5B7, 0xD639, 0xD638, 0xC5D7, 0xBD95, 0xBD75, 0xB533, 0xA4D2, 0x83CE, 0x7B6D, 0x83CE, 0x8BCF, 0xC596, 0xCDF8,   // 0x0DB0 (3504)
+0xB555, 0x8C10, 0x62CB, 0x6AEB, 0x7B8D, 0x5228, 0x41E7, 0x62CB, 0x7BAE, 0x7BCF, 0x4A29, 0x2104, 0x20C2, 0x3144, 0x5247, 0x5268,   // 0x0DC0 (3520)
+0x8411, 0x8411, 0x83F1, 0x7BF1, 0x7BF1, 0x8411, 0x8C52, 0x8C32, 0x8C52, 0x8C32, 0x8C52, 0x8C52, 0x8431, 0x8411, 0x8411, 0x7BF0,   // 0x0DD0 (3536)
+0x7BD0, 0x738F, 0x7BB0, 0x9CB4, 0xBDB8, 0xBD77, 0xA4D4, 0x9C92, 0x7B6D, 0x5248, 0x62AA, 0x7B4D, 0xACF3, 0xBD96, 0xD639, 0xC597,   // 0x0DE0 (3552)
+0xACB3, 0x8BAE, 0x6ACA, 0x5227, 0x5A47, 0x9C2F, 0x942F, 0x41A5, 0x41C6, 0x5248, 0x3984, 0x3964, 0x5A48, 0x6AEA, 0x838E, 0x9C51,   // 0x0DF0 (3568)
+0xC5B8, 0xCDF9, 0xD65A, 0xE6BC, 0xDE9A, 0xDE7A, 0xC5B7, 0xB555, 0xAD13, 0x83CE, 0x62CA, 0x7B6D, 0x9C91, 0xBD95, 0xB554, 0x9430,   // 0x0E00 (3584)
+0x7B6E, 0x62CB, 0x5A8A, 0x62AA, 0x4A07, 0x1861, 0x2924, 0x6B0C, 0x7BCF, 0x736D, 0x5AAA, 0x3165, 0x20E3, 0x2923, 0x3144, 0x3985,   // 0x0E10 (3600)
+0x8C32, 0x8411, 0x8411, 0x8411, 0x83F1, 0x8411, 0x8431, 0x8C32, 0x8C52, 0x8C32, 0x8C52, 0x9473, 0x9493, 0x9473, 0x8C52, 0x8432,   // 0x0E20 (3616)
+0x8C32, 0x9473, 0xAD57, 0xC5F9, 0xCE1A, 0xCDF9, 0x9C93, 0x62CC, 0x3145, 0x0820, 0x3124, 0x5248, 0x62CA, 0x83CF, 0xBD96, 0xDE7A,   // 0x0E30 (3632)
+0xCDF8, 0xB514, 0x942F, 0x7B6C, 0x7B6B, 0x7B6B, 0x41A6, 0x49E7, 0x6ACA, 0x5227, 0x5A47, 0x730A, 0x83AD, 0x9450, 0xACF3, 0xB535,   // 0x0E40 (3648)
+0xC5D8, 0xC5B8, 0xDE9B, 0xDE7A, 0xDE5A, 0xD659, 0xB514, 0x838E, 0x838D, 0x83AD, 0x734C, 0x8BEF, 0x9450, 0xA4B2, 0xACF3, 0x9C71,   // 0x0E50 (3664)
+0xA4D3, 0xACF3, 0xA4B2, 0x83CF, 0x4A28, 0x1861, 0x3985, 0x83CF, 0x83EF, 0x5269, 0x39A6, 0x3986, 0x2944, 0x3145, 0x39A5, 0x41E6,   // 0x0E60 (3680)
+0x8C72, 0x8C52, 0x8C52, 0x8C32, 0x8411, 0x83F1, 0x83F1, 0x7BF0, 0x83F1, 0x8411, 0x8C32, 0x8C52, 0x8C73, 0x9473, 0x9473, 0x8C52,   // 0x0E70 (3696)
+0x8C51, 0x8411, 0x7BD0, 0x736F, 0xA4D5, 0xC5D9, 0xC5F9, 0xA4F5, 0x62AB, 0x5249, 0x28E3, 0x1040, 0x2904, 0x5269, 0xBD76, 0xE6BB,   // 0x0E80 (3712)
+0xEF1C, 0xDEBA, 0xBD95, 0xA491, 0x9C71, 0x732B, 0x5A68, 0x49C6, 0x730B, 0x6AA9, 0x732B, 0x8BCE, 0x9C71, 0xAD14, 0xB535, 0xAD14,   // 0x0E90 (3728)
+0xBD76, 0xACF4, 0xB535, 0xBD76, 0xB534, 0xA492, 0x9C30, 0x732C, 0x6AEB, 0x8BEF, 0x9430, 0x8BCE, 0x9C71, 0x8C10, 0x8C11, 0x9C72,   // 0x0EA0 (3744)
+0x8C30, 0x83EF, 0x83AE, 0x7B8D, 0x732C, 0x5A69, 0x62EB, 0x83EF, 0x9CD2, 0x738D, 0x4A28, 0x5AAA, 0x6B0B, 0x62CA, 0x6B0B, 0x7B6D,   // 0x0EB0 (3760)
+0x8411, 0x8411, 0x8411, 0x8411, 0x7BF0, 0x7BF0, 0x7BD0, 0x73AF, 0x73AF, 0x7BF0, 0x8411, 0x8411, 0x8411, 0x8C52, 0x9473, 0x9492,   // 0x0EC0 (3776)
+0x94B2, 0x5AEB, 0x3186, 0x4209, 0x6B2E, 0xAD15, 0xD65A, 0xD65A, 0xD659, 0x8C30, 0x2904, 0x20E3, 0x20C3, 0x62CB, 0xB535, 0xD659,   // 0x0ED0 (3792)
+0xDEBA, 0xEF5D, 0xE6FC, 0xD639, 0xAD14, 0xA491, 0x8BCE, 0x7B4B, 0x838C, 0x836D, 0x83AE, 0x8BEF, 0x8C10, 0xACF4, 0xB575, 0xACF3,   // 0x0EE0 (3808)
+0x9C91, 0x940F, 0x838D, 0xA4B2, 0x9C50, 0x83AE, 0x9C50, 0x940F, 0x93EF, 0x838D, 0x8BEF, 0x9430, 0xA4B3, 0xACF5, 0xC5F9, 0xC5B8,   // 0x0EF0 (3824)
+0x732C, 0x3985, 0x41A6, 0x7B8D, 0x9C91, 0x7B6D, 0x6B0C, 0x7B8D, 0x8C50, 0x7BAE, 0x6B2C, 0x83EF, 0x9451, 0x9C71, 0xA4B2, 0xA4D3,   // 0x0F00 (3840)
+0x83F1, 0x83F1, 0x7BF0, 0x83F1, 0x83F1, 0x7BF0, 0x7BD0, 0x7BB0, 0x7BB0, 0x7BD0, 0x8411, 0x8C52, 0x9473, 0x8C53, 0x9474, 0x9494,   // 0x0F10 (3856)
+0x8C52, 0x738F, 0x5ACC, 0x4209, 0x41E8, 0x5AAB, 0x9452, 0xBDB7, 0xD639, 0x8BF0, 0x49E7, 0x18A2, 0x1061, 0x41C7, 0x62AA, 0xA4B2,   // 0x0F20 (3872)
+0xDEBB, 0xEEFD, 0xE6BB, 0xE6FC, 0xBD76, 0x8C10, 0x9CB2, 0xA4B2, 0xBD75, 0xC5D6, 0xB555, 0xBD76, 0xC5B7, 0xCE19, 0xD65B, 0xCE19,   // 0x0F30 (3888)
+0xC5B7, 0xC5D7, 0xAD14, 0xB555, 0xBD75, 0xB575, 0xBD96, 0xA4B2, 0x83CF, 0x83AF, 0x9CB3, 0x9472, 0xA4F4, 0xB556, 0xAD35, 0xB576,   // 0x0F40 (3904)
+0x8C11, 0x5A8B, 0x62EB, 0x9451, 0x9450, 0x7B8D, 0x62CA, 0x83CF, 0xAD13, 0x83F0, 0x83AF, 0x9451, 0x9452, 0x9472, 0x9CD3, 0x9C93,   // 0x0F50 (3920)
+0x8411, 0x8C32, 0x8C32, 0x8C32, 0x8431, 0x8411, 0x8411, 0x83F0, 0x7BF0, 0x8411, 0x8412, 0x8C32, 0x9494, 0x9473, 0xA4D5, 0xAD16,   // 0x0F60 (3936)
+0xAD56, 0xBDD8, 0xC619, 0xB5B7, 0x8C31, 0x526A, 0x5A8B, 0x7BAF, 0xB576, 0xC5F8, 0x9451, 0x49E8, 0x18A2, 0x0820, 0x3165, 0x7B8E,   // 0x0F70 (3952)
+0xACF4, 0xB555, 0xD639, 0xDEBB, 0xCDF8, 0xB555, 0xA4D4, 0xACD4, 0xBD76, 0xCE18, 0xD65A, 0xD65A, 0xD65A, 0xDE9B, 0xDEBB, 0xDE7A,   // 0x0F80 (3968)
+0xE6BB, 0xDE9B, 0xD659, 0xC5D7, 0xD639, 0xBD96, 0xAD14, 0x9451, 0x9451, 0xA4D4, 0x9CB3, 0x9C72, 0x8C11, 0x736E, 0x6B2D, 0x6B0D,   // 0x0F90 (3984)
+0x8C31, 0x9C93, 0x8C51, 0x83EF, 0x734C, 0x5A89, 0x6B0B, 0x8C30, 0xBD96, 0xA4D3, 0x8C31, 0x9472, 0x9CB3, 0x9CB3, 0x9CD3, 0x9CD3,   // 0x0FA0 (4000)
+0x83F1, 0x8431, 0x8C31, 0x8411, 0x8411, 0x8411, 0x8411, 0x7BF0, 0x8411, 0x7BD0, 0x8C32, 0x8411, 0x9473, 0x9C93, 0x9C94, 0xBD98,   // 0x0FB0 (4016)
+0xC63A, 0xD67B, 0xDEDC, 0xE71D, 0xDEDC, 0xA515, 0x4A29, 0x2946, 0x4A08, 0x7BCF, 0xA4D3, 0x9CB2, 0x528A, 0x20C3, 0x18A3, 0x2925,   // 0x0FC0 (4032)
+0x41E7, 0x7BAE, 0xA4D3, 0xA4B3, 0x9C93, 0xC5B8, 0xACF5, 0xB557, 0xBD77, 0xBD57, 0xC5D9, 0xCE19, 0xD65A, 0xD67A, 0xDEBA, 0xCE39,   // 0x0FD0 (4048)
+0xCE19, 0xC5D8, 0xB535, 0xA4B3, 0xA4B3, 0x9451, 0x9C92, 0xA4D3, 0xA4D4, 0xACD4, 0x734E, 0x6AEC, 0x7B8F, 0x9C93, 0xA4B3, 0x7B6E,   // 0x0FE0 (4064)
+0x630C, 0x736E, 0x62EC, 0x5AAB, 0x5289, 0x62EB, 0x62CA, 0x6B0B, 0x8C30, 0x8C10, 0x9C92, 0xACF4, 0x9C93, 0x9452, 0x9CB3, 0xA4B3,   // 0x0FF0 (4080)
+0x7BCF, 0x7BD0, 0x7BD0, 0x7BAF, 0x7BCF, 0x7BD0, 0x7BD0, 0x7BAF, 0x73AF, 0x7BCF, 0x7BD0, 0x8411, 0x9493, 0xA4D4, 0xAD36, 0xC5D9,   // 0x1000 (4096)
+0xD67B, 0xD69B, 0xDEDC, 0xDEDC, 0xE6FC, 0xE71D, 0x9492, 0x3186, 0x0000, 0x0821, 0x526A, 0x9472, 0x9CB3, 0x6B2D, 0x6B4D, 0x734E,   // 0x1010 (4112)
+0x6B2D, 0xA4B3, 0x8C31, 0x6B2D, 0x6B0D, 0x9C73, 0x9C73, 0xBD98, 0xC5F9, 0xBD98, 0xC5D9, 0xBDB8, 0xCE19, 0xCE3A, 0xCE39, 0xBD97,   // 0x1020 (4128)
+0xB556, 0xAD36, 0x8C11, 0x734E, 0xAD14, 0xCDF8, 0xC5B6, 0xA4D3, 0x9451, 0xB534, 0xD659, 0x9C72, 0x41C7, 0x3986, 0xA4D3, 0xCE39,   // 0x1030 (4144)
+0xB556, 0x9472, 0x5249, 0x18C3, 0x41C7, 0x62CB, 0x4A28, 0x41C7, 0x3966, 0x7B8E, 0xACF4, 0xACF4, 0x9CB3, 0x9C93, 0xA4D4, 0xAD14,   // 0x1040 (4160)
+0x7BCF, 0x73AF, 0x738E, 0x738F, 0x7BAF, 0x7BCF, 0x7BCF, 0x73AF, 0x738F, 0x7BCF, 0x7BAF, 0x8411, 0x9493, 0x8C52, 0x7BAF, 0x5A8B,   // 0x1050 (4176)
+0x62ED, 0xA515, 0xCE5A, 0xE6FD, 0xDEDC, 0xE71D, 0xEF5D, 0xCE59, 0x6B2D, 0x3166, 0x18C3, 0x4A49, 0x8C31, 0x9CD4, 0xB576, 0xA4F5,   // 0x1060 (4192)
+0xAD15, 0xDE9B, 0xCE19, 0x8C11, 0x7BAF, 0x7B8F, 0x83F0, 0x9472, 0xA4D4, 0xA4D4, 0xBDD8, 0xC5F9, 0xCE5A, 0xC61A, 0xBDB9, 0xC5F9,   // 0x1070 (4208)
+0xAD36, 0x8C31, 0x8C31, 0xB535, 0x9451, 0xA4B2, 0xCE17, 0xACF3, 0x7B6D, 0x628A, 0x8C10, 0xCE18, 0xBD75, 0x4A28, 0x39A6, 0x9CD3,   // 0x1080 (4224)
+0xC5D8, 0xCE39, 0x9451, 0x734D, 0x736D, 0x6B4D, 0x4A08, 0x62CB, 0x39A7, 0x83AF, 0xACF4, 0xAD15, 0xACF4, 0xAD15, 0xAD15, 0xAD15,   // 0x1090 (4240)
+0x83F0, 0x7BAF, 0x738E, 0x73AF, 0x7BCF, 0x7BCF, 0x73AF, 0x738E, 0x7BD0, 0x7BD0, 0x8C52, 0x8431, 0x8411, 0x62CC, 0x39A7, 0x1883,   // 0x10A0 (4256)
+0x0000, 0x1082, 0x4A29, 0x9CF4, 0xCE7A, 0xDEDC, 0xEF3D, 0xE71D, 0xD6BB, 0xA514, 0x39E8, 0x0842, 0x18A3, 0x4A29, 0x630C, 0x8C31,   // 0x10B0 (4272)
+0xC619, 0xDE7C, 0xDEDC, 0xC5D9, 0xAD56, 0x9473, 0x8C52, 0x8C52, 0xA4F4, 0xAD15, 0xBDB8, 0xD65B, 0xC61A, 0xBDB9, 0xCE1A, 0xBD78,   // 0x10C0 (4288)
+0x9472, 0x7B8F, 0xBD96, 0x9451, 0x83CE, 0xBD75, 0xBD54, 0x942F, 0x9C71, 0xACF3, 0x62EB, 0x62AA, 0xBD95, 0xB575, 0x5269, 0x5ACB,   // 0x10D0 (4304)
+0x9CB3, 0xBDF8, 0xC618, 0x7BAF, 0x4A08, 0x62EC, 0x8C31, 0xA4F4, 0xAD15, 0xAD15, 0xB536, 0xB536, 0xACF5, 0xA4D4, 0xAD15, 0xB535,   // 0x10E0 (4320)
+0x83F0, 0x83F0, 0x7BCF, 0x7BAF, 0x73AF, 0x73AF, 0x738E, 0x736E, 0x7BB0, 0x8C32, 0x9473, 0x9452, 0x8410, 0x6B0D, 0x7B8F, 0x83F0,   // 0x10F0 (4336)
+0x3185, 0x0000, 0x0000, 0x0841, 0x31A6, 0x62EC, 0x7BD0, 0xBDD8, 0xD69B, 0xD67B, 0x7BF0, 0x0842, 0x0000, 0x0000, 0x0861, 0x62EC,   // 0x1100 (4352)
+0x8C31, 0xAD36, 0xD69B, 0xD69C, 0xBDB9, 0xA516, 0x9494, 0x9CB5, 0xA4F6, 0xB578, 0xC5D9, 0xD69C, 0xC5D9, 0xC5D9, 0xBDB8, 0x7B90,   // 0x1110 (4368)
+0x6AED, 0xA4F4, 0xBD96, 0x9C92, 0x83AE, 0x8BEE, 0x9C50, 0x9C91, 0x9C71, 0x9C51, 0xC5D7, 0x9C72, 0x5269, 0x6B0C, 0x8C51, 0x528A,   // 0x1120 (4384)
+0x6B4D, 0x8411, 0xAD35, 0x8C31, 0x526A, 0x83F0, 0xA4D4, 0xAD15, 0xB535, 0xB557, 0xB536, 0xAD16, 0xB537, 0xB536, 0xAD36, 0xB536,   // 0x1130 (4400)
+0x83CF, 0x83F0, 0x83F0, 0x7BAF, 0x738E, 0x736E, 0x738F, 0x738F, 0x7BD0, 0x8C31, 0x9473, 0x9472, 0x9CB3, 0xB556, 0xB576, 0xCE39,   // 0x1140 (4416)
+0xAD33, 0x4207, 0x20C2, 0x0000, 0x0000, 0x0000, 0x0001, 0x39A8, 0xAD56, 0xD6BC, 0xA515, 0x3187, 0x1062, 0x0820, 0x0020, 0x10A2,   // 0x1150 (4432)
+0x2925, 0x4A6A, 0x9493, 0xB5B8, 0xB578, 0x8C33, 0x7BD2, 0x9CB6, 0xB579, 0xB579, 0xBDB9, 0xCE1A, 0xBD98, 0xBD97, 0x8C11, 0x6B0C,   // 0x1160 (4448)
+0x6B2D, 0xACF4, 0xBD76, 0xB534, 0x9C71, 0x9C71, 0xA4D2, 0xACF3, 0x9C71, 0x83AE, 0xA4B2, 0xD639, 0xC5D7, 0x7B8F, 0x62EC, 0x8C51,   // 0x1170 (4464)
+0x528B, 0x6B2D, 0x6B0D, 0x7B8F, 0x9472, 0xACF4, 0xACF4, 0xAD15, 0xB556, 0xAD16, 0xB536, 0xB557, 0xAD16, 0xACF6, 0xB557, 0xB536,   // 0x1180 (4480)
+0x8410, 0x83F0, 0x8410, 0x7BF0, 0x7BAF, 0x7BAF, 0x738F, 0x738F, 0x83D0, 0x83F1, 0x83D0, 0x9CD3, 0xAD35, 0xB576, 0xB576, 0xC5F8,   // 0x1190 (4496)
+0xBDD6, 0x8C50, 0x2945, 0x0841, 0x0000, 0x0000, 0x0000, 0x0000, 0x738F, 0xDEFC, 0xB597, 0x7BD0, 0x41E9, 0x0000, 0x0000, 0x0000,   // 0x11A0 (4512)
+0x0821, 0x20E4, 0x4209, 0x9492, 0x94B3, 0x4A6A, 0x31C8, 0x6B4E, 0x8C73, 0x9CF5, 0x9CD4, 0xA515, 0xAD36, 0x83D0, 0x62EC, 0x9451,   // 0x11B0 (4528)
+0xAD13, 0xA4D2, 0x9C71, 0xA4B1, 0xB513, 0xC595, 0xBD74, 0xACD2, 0x8C0F, 0x9450, 0xA4F3, 0xACF3, 0xD67A, 0xE6BC, 0x9C93, 0x9CB4,   // 0x11C0 (4544)
+0x9C72, 0x5AAB, 0x62AB, 0x83F0, 0xA4D4, 0xB556, 0xB556, 0xB556, 0xB535, 0xB535, 0xAD15, 0xB536, 0xAD15, 0xAD15, 0xAD15, 0xAD16,   // 0x11D0 (4560)
+0x8431, 0x83F0, 0x7BF0, 0x7BF0, 0x83F0, 0x8410, 0x7BD0, 0x73AF, 0x8C11, 0x8C11, 0x630C, 0x6B2D, 0x8411, 0x8C11, 0x734E, 0x8C51,   // 0x11E0 (4576)
+0xBD96, 0xBDB6, 0x8C51, 0x5AAB, 0x3186, 0x0841, 0x0000, 0x0000, 0x528A, 0xCE5A, 0xB5B8, 0xAD57, 0x738F, 0x1062, 0x0820, 0x0000,   // 0x11F0 (4592)
+0x0841, 0x2924, 0x3186, 0x5ACB, 0x5ACB, 0x1062, 0x2966, 0x3187, 0x4209, 0x5AEC, 0x630D, 0x83F1, 0x7BAF, 0x4A08, 0x83F0, 0xAD14,   // 0x1200 (4608)
+0xB533, 0xB554, 0xB554, 0xB533, 0xA491, 0x9C50, 0x942F, 0xB533, 0xBD33, 0xB513, 0xACF3, 0xBD75, 0xC5D7, 0xCE19, 0xC5F9, 0x9473,   // 0x1210 (4624)
+0x9452, 0x6B2D, 0x734E, 0x9452, 0xACF4, 0xB556, 0xBD77, 0xBD77, 0xBD77, 0xBD56, 0xB556, 0xB556, 0xAD16, 0xB536, 0xB536, 0xB556,   // 0x1220 (4640)
+0x8410, 0x7BF0, 0x7BF0, 0x83F0, 0x83F0, 0x83F0, 0x7BD0, 0x7BD0, 0x9452, 0x9CB4, 0x9493, 0x6B4E, 0x39A7, 0x39A7, 0x41E8, 0x4A49,   // 0x1230 (4656)
+0x734D, 0x83EF, 0xA4F3, 0xBD96, 0xB555, 0x5AAB, 0x0020, 0x0000, 0x39C7, 0xC5F9, 0xC61A, 0xCE5B, 0x9494, 0x2925, 0x1082, 0x1061,   // 0x1240 (4672)
+0x1061, 0x18C2, 0x2944, 0x2103, 0x39A6, 0x526A, 0x632D, 0x6B6E, 0x736E, 0x62EC, 0x6B2D, 0x736E, 0x736E, 0x736D, 0x9C92, 0xA4B2,   // 0x1250 (4688)
+0x9C70, 0x83AC, 0x942F, 0x9C4F, 0x838C, 0x942F, 0x8BCD, 0x8BCD, 0x9C2F, 0x8BCE, 0x83CD, 0xA4B1, 0xB555, 0xB555, 0xCDF8, 0xA4F4,   // 0x1260 (4704)
+0x8C31, 0x8BF1, 0x9452, 0xA4D4, 0xA4D4, 0xAD15, 0xBD77, 0xBD97, 0xBD77, 0xBD77, 0xB556, 0xB536, 0xACF5, 0xAD16, 0xB536, 0xB556,   // 0x1270 (4720)
+0x8411, 0x8411, 0x8411, 0x8411, 0x83F1, 0x7BD0, 0x7BD0, 0x8C31, 0x9473, 0xB576, 0xB576, 0xB576, 0x62EC, 0x39A7, 0x7BAF, 0x9C92,   // 0x1280 (4736)
+0x83CF, 0x83CF, 0x9CB3, 0xB556, 0xC619, 0xA4D4, 0x10A3, 0x0000, 0x39C8, 0xC5F9, 0xD67C, 0xCE7B, 0x9CB4, 0x31A7, 0x20E3, 0x18C2,   // 0x1290 (4752)
+0x1061, 0x2103, 0x0840, 0x18C2, 0x5269, 0x8430, 0xA514, 0xAD35, 0xA515, 0xA4F4, 0xA515, 0x9472, 0x8C10, 0xA4D3, 0xAD34, 0xAD13,   // 0x12A0 (4768)
+0x9C70, 0x9C4F, 0x940E, 0x836C, 0x93EE, 0xB4F2, 0x836C, 0x6AC9, 0x730A, 0x940E, 0x940F, 0x838D, 0xACD3, 0xBD75, 0xBD76, 0xA4B3,   // 0x12B0 (4784)
+0x9432, 0xA4B4, 0xAD16, 0xB557, 0xAD15, 0xAD15, 0xBD97, 0xC5B8, 0xC5D8, 0xC5D8, 0xBD98, 0xB557, 0xAD15, 0xB556, 0xBD77, 0xBD77,   // 0x12C0 (4800)
+};
+
+// Generated by  : ImageConverter 565 v2.0
+// Generated from: HappyCat.jpg
+// Time generated: 02.07.2013 22:57:23
+// Dimensions    : 147x110 pixels
+// Size          : 32 340 Bytes
+
+#include 
+
+prog_uint16_t HappyCat[0x3F2A] PROGMEM ={
+0x0000, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0000, 0x0000, 0x0800, 0x0800, 0x0800, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0010 (16)
+0x0800, 0x0800, 0x0000, 0x0800, 0x0000, 0x0841, 0x0820, 0x0000, 0x0800, 0x0800, 0x0820, 0x0840, 0x1021, 0x0800, 0x0800, 0x0800,   // 0x0020 (32)
+0x0800, 0x0800, 0x1020, 0x1020, 0x0820, 0x1020, 0x1040, 0x1040, 0x1040, 0x1020, 0x1041, 0x1020, 0x20A2, 0x5289, 0x10A2, 0x0800,   // 0x0030 (48)
+0x1820, 0x20C3, 0x1882, 0x1020, 0x1862, 0x2082, 0x1020, 0x1040, 0x1041, 0x1041, 0x1041, 0x0800, 0x1041, 0x18A2, 0x0800, 0x0821,   // 0x0040 (64)
+0x0000, 0x1081, 0x18A1, 0x1881, 0x18C3, 0x0820, 0x28E3, 0x18C2, 0x0800, 0x3965, 0x7B2A, 0x7B09, 0x6268, 0x3123, 0x5A06, 0x8B8C,   // 0x0050 (80)
+0x93ED, 0x8BAC, 0x7B4A, 0x93ED, 0x9C2E, 0x8B8B, 0x8B8B, 0x6247, 0x3923, 0x1820, 0x2061, 0x72E9, 0x832A, 0x8B8B, 0x6246, 0x3923,   // 0x0060 (96)
+0x1041, 0x1081, 0x0000, 0x0000, 0x0020, 0x1820, 0x1820, 0x1821, 0x1840, 0x20C2, 0x20C2, 0x2081, 0x2081, 0x1881, 0x2081, 0x20A2,   // 0x0070 (112)
+0x20A2, 0x20A2, 0x2081, 0x1881, 0x20A1, 0x28C2, 0x30E2, 0x30E2, 0x30E2, 0x30E2, 0x30E2, 0x28C2, 0x28C2, 0x28C2, 0x2081, 0x1881,   // 0x0080 (128)
+0x1881, 0x20A1, 0x20A1, 0x20A1, 0x20A2, 0x20A2, 0x20C2, 0x2103, 0x3103, 0x30E3, 0x28E3, 0x28E3, 0x2903, 0x2903, 0x2903, 0x2903,   // 0x0090 (144)
+0x2903, 0x2903, 0x3144, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0820, 0x0820, 0x0800, 0x0800, 0x0820, 0x0800, 0x0000,   // 0x00A0 (160)
+0x0000, 0x0000, 0x0800, 0x0820, 0x0821, 0x0820, 0x0800, 0x0800, 0x0841, 0x0821, 0x0000, 0x0800, 0x0800, 0x0000, 0x0000, 0x1041,   // 0x00B0 (176)
+0x1021, 0x1061, 0x1861, 0x1882, 0x1881, 0x0800, 0x0800, 0x1041, 0x1861, 0x1041, 0x1041, 0x1041, 0x1041, 0x1061, 0x1041, 0x1841,   // 0x00C0 (192)
+0x2903, 0x39C6, 0x20C3, 0x1020, 0x1861, 0x28C3, 0x1882, 0x1861, 0x20A2, 0x1861, 0x1061, 0x1861, 0x1061, 0x1040, 0x0800, 0x1061,   // 0x00D0 (208)
+0x3985, 0x1041, 0x20C2, 0x1881, 0x3123, 0x4184, 0x4A06, 0x3984, 0x3144, 0x20A2, 0x1061, 0x1881, 0x3964, 0x7B0A, 0x9C2D, 0x836B,   // 0x00E0 (224)
+0x5206, 0x72C9, 0xA46E, 0xACB0, 0x93ED, 0x93ED, 0xB4F1, 0xAC8F, 0xA44E, 0x9C0D, 0x7AE9, 0x5A26, 0x2082, 0x4984, 0x93CC, 0x9BCC,   // 0x00F0 (240)
+0x8B6A, 0x72C8, 0x6227, 0x20A2, 0x20C2, 0x0000, 0x0000, 0x0000, 0x0800, 0x0820, 0x1020, 0x1040, 0x28E3, 0x1881, 0x20A2, 0x2081,   // 0x0100 (256)
+0x2081, 0x2081, 0x28C2, 0x28C2, 0x20A2, 0x20A1, 0x20A2, 0x28C2, 0x28C2, 0x28E2, 0x30E2, 0x30E2, 0x3103, 0x3103, 0x30E2, 0x28C2,   // 0x0110 (272)
+0x30C2, 0x28C2, 0x20A1, 0x20A1, 0x20A1, 0x20A2, 0x20A2, 0x28C2, 0x28E2, 0x30E3, 0x3103, 0x3123, 0x3103, 0x3103, 0x3103, 0x2923,   // 0x0120 (288)
+0x2923, 0x3123, 0x2923, 0x2923, 0x3123, 0x3164, 0x0000, 0x0800, 0x0821, 0x0800, 0x0800, 0x0820, 0x0820, 0x0820, 0x0800, 0x0800,   // 0x0130 (304)
+0x0820, 0x0800, 0x0000, 0x0000, 0x0800, 0x0820, 0x0820, 0x0821, 0x0821, 0x0820, 0x0800, 0x0800, 0x0800, 0x0000, 0x0800, 0x0820,   // 0x0140 (320)
+0x1061, 0x0040, 0x0000, 0x0820, 0x20C3, 0x3985, 0x41A5, 0x4A06, 0x3144, 0x2924, 0x1881, 0x1861, 0x1040, 0x1840, 0x1041, 0x1061,   // 0x0150 (336)
+0x1041, 0x1061, 0x1881, 0x1840, 0x1881, 0x3986, 0x2924, 0x1020, 0x1861, 0x20C2, 0x20C2, 0x18A1, 0x18A1, 0x20C2, 0x1061, 0x1041,   // 0x0160 (352)
+0x1020, 0x0800, 0x1061, 0x5207, 0x3124, 0x3123, 0x4A06, 0x6AE9, 0x732A, 0x732A, 0x5247, 0x62A9, 0x3123, 0x18A2, 0x2104, 0x41A5,   // 0x0170 (368)
+0x7B4B, 0xB532, 0x942E, 0x7B6B, 0x83AC, 0x8BED, 0x9C2E, 0x836B, 0x8BAC, 0xA48F, 0x9C2E, 0xB4D1, 0x8BAC, 0x836B, 0x72E9, 0x28C2,   // 0x0180 (384)
+0x49C5, 0x6A88, 0x72C8, 0x5A26, 0x6A88, 0x4144, 0x3944, 0x5227, 0x1881, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1061, 0x18A2,   // 0x0190 (400)
+0x1041, 0x1861, 0x1861, 0x2081, 0x2081, 0x20A2, 0x28A1, 0x28E2, 0x20A2, 0x2082, 0x28C2, 0x20C2, 0x28C2, 0x20A2, 0x20C2, 0x28C2,   // 0x01A0 (416)
+0x28C2, 0x30E2, 0x28E3, 0x28C2, 0x28C2, 0x20A2, 0x20A1, 0x20A1, 0x20A2, 0x20A2, 0x28C2, 0x28E2, 0x28E3, 0x28E3, 0x2903, 0x2903,   // 0x01B0 (432)
+0x28E3, 0x28E3, 0x28E3, 0x2903, 0x2903, 0x2903, 0x2923, 0x2923, 0x3144, 0x0000, 0x0820, 0x0821, 0x0820, 0x0820, 0x0820, 0x0820,   // 0x01C0 (448)
+0x0820, 0x0820, 0x0821, 0x0821, 0x0820, 0x0800, 0x0800, 0x0800, 0x0800, 0x0821, 0x0821, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820,   // 0x01D0 (464)
+0x0800, 0x0000, 0x4207, 0x9CD3, 0x8C10, 0x5269, 0x28C2, 0x1000, 0x20A2, 0x3103, 0x5227, 0x5267, 0x6AE9, 0x730A, 0x62CA, 0x3965,   // 0x01E0 (480)
+0x20C2, 0x1881, 0x1861, 0x1061, 0x1861, 0x1881, 0x1881, 0x20A2, 0x20C2, 0x3985, 0x3965, 0x1861, 0x1041, 0x20C3, 0x2923, 0x1060,   // 0x01F0 (496)
+0x3985, 0x2903, 0x18A2, 0x20A2, 0x20C2, 0x20C2, 0x49E6, 0x5227, 0x41A5, 0x7B2B, 0x942E, 0x9C4F, 0x838C, 0x6B0A, 0x7B6C, 0x6AEA,   // 0x0200 (512)
+0x3964, 0x49E7, 0x8BCE, 0xA491, 0xBD74, 0xACF2, 0xA4D1, 0x8BAD, 0x6288, 0x8BCD, 0x836B, 0x62A9, 0x6B0A, 0x9C2F, 0xB512, 0x9C2E,   // 0x0210 (528)
+0x93ED, 0x6AC9, 0x3124, 0x1881, 0x2903, 0x49C6, 0x41A5, 0x5A48, 0x28E2, 0x62A9, 0x72E9, 0x5206, 0x1061, 0x1061, 0x0000, 0x0000,   // 0x0220 (544)
+0x0000, 0x20C2, 0x0820, 0x0800, 0x1020, 0x1841, 0x28C2, 0x20A2, 0x1861, 0x28E2, 0x3144, 0x20A2, 0x20A1, 0x20A2, 0x20C2, 0x20A2,   // 0x0230 (560)
+0x20A2, 0x20A2, 0x20A1, 0x20A2, 0x28C2, 0x28E2, 0x28C2, 0x28C2, 0x20A2, 0x20A1, 0x20A1, 0x20A1, 0x20A2, 0x20C2, 0x28C2, 0x28E2,   // 0x0240 (576)
+0x28E2, 0x2903, 0x28E3, 0x2903, 0x2903, 0x2903, 0x2903, 0x2923, 0x2923, 0x2923, 0x2923, 0x3144, 0x0820, 0x1081, 0x1041, 0x0821,   // 0x0250 (592)
+0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x0821, 0x0820, 0x0800, 0x0800, 0x0800, 0x0800, 0x0820, 0x0820, 0x0820, 0x0820,   // 0x0260 (608)
+0x0820, 0x0820, 0x0820, 0x0000, 0x0000, 0x630C, 0xD67C, 0xE71E, 0xDEDD, 0xC5F8, 0x9430, 0x5A68, 0x3922, 0x4184, 0x51E6, 0x5206,   // 0x0270 (624)
+0x6AC9, 0x83AC, 0x734B, 0x6AEA, 0x5247, 0x5A68, 0x4A47, 0x3964, 0x3985, 0x3144, 0x28E3, 0x3144, 0x2903, 0x39A6, 0x4A08, 0x20C2,   // 0x0280 (640)
+0x1041, 0x2903, 0x20C2, 0x2903, 0x5248, 0x4A07, 0x5A67, 0x4A27, 0x39A5, 0x5247, 0x5A68, 0x62A9, 0x838C, 0xA470, 0xA4B0, 0x83CD,   // 0x0290 (656)
+0x7B8C, 0x8BEE, 0x83CD, 0x4A06, 0x8BCE, 0xB553, 0xBD54, 0xCDD6, 0xACF2, 0xA4D2, 0x6B0B, 0x4A07, 0x836C, 0x838C, 0x41C6, 0x41C6,   // 0x02A0 (672)
+0x9C4F, 0xB4F1, 0xBD33, 0x9C4F, 0x62A8, 0x18A2, 0x1061, 0x28E3, 0x3985, 0x5227, 0x62A9, 0x6ACA, 0x836C, 0x940E, 0x836B, 0x5A27,   // 0x02B0 (688)
+0x30E3, 0x0800, 0x0000, 0x18A2, 0x3123, 0x1861, 0x1040, 0x1020, 0x1041, 0x1861, 0x1861, 0x1841, 0x3124, 0x3944, 0x20A1, 0x20A1,   // 0x02C0 (704)
+0x20A2, 0x20A1, 0x20A1, 0x20A2, 0x20A1, 0x20A2, 0x20A2, 0x20A2, 0x28C2, 0x28C2, 0x28C2, 0x20A2, 0x20A1, 0x20A1, 0x20A1, 0x20A2,   // 0x02D0 (720)
+0x20A2, 0x28C2, 0x28C2, 0x28E2, 0x28E3, 0x2903, 0x28E3, 0x20E3, 0x28E3, 0x2903, 0x2903, 0x2923, 0x2923, 0x3124, 0x3144, 0x0800,   // 0x02E0 (736)
+0x0841, 0x0841, 0x0820, 0x0820, 0x0820, 0x0820, 0x0800, 0x0800, 0x0820, 0x0820, 0x0820, 0x0000, 0x0800, 0x0800, 0x0820, 0x0820,   // 0x02F0 (752)
+0x0820, 0x0820, 0x0800, 0x0800, 0x0800, 0x0820, 0x0800, 0x0000, 0x2104, 0x8C52, 0xB5B8, 0xDEDC, 0xEF5E, 0xEF3D, 0xDE9A, 0xB534,   // 0x0300 (768)
+0x8BAD, 0x6AA8, 0x5206, 0x4184, 0x49C5, 0x6AC9, 0x732A, 0x838C, 0x836C, 0x838C, 0x836C, 0x7B6C, 0x7B4C, 0x5A48, 0x3964, 0x2923,   // 0x0310 (784)
+0x28E3, 0x41E7, 0x5269, 0x2104, 0x2923, 0x3144, 0x4185, 0x6289, 0x7B6C, 0x6AE9, 0x6AEA, 0x5A68, 0x62C9, 0x6AA9, 0x7B4B, 0x940E,   // 0x0320 (800)
+0xA46F, 0xA490, 0x83AC, 0x732B, 0x7B6C, 0x7B8C, 0x730B, 0xAD13, 0xC595, 0xC5B6, 0xD618, 0x942F, 0x732B, 0x5A68, 0x4A07, 0x838C,   // 0x0330 (816)
+0x836B, 0x41C6, 0x41C6, 0x838C, 0xBD53, 0xC5D6, 0xB4F2, 0x6AEA, 0x18A2, 0x20C2, 0x4A27, 0x5207, 0x62A9, 0x72EA, 0xA44F, 0x9C2E,   // 0x0340 (832)
+0xA4D1, 0x9C2E, 0x838C, 0x49C5, 0x28A2, 0x1061, 0x3185, 0x3985, 0x4185, 0x3944, 0x2062, 0x1000, 0x0820, 0x1020, 0x1020, 0x3103,   // 0x0350 (848)
+0x28E2, 0x20A1, 0x1861, 0x20A2, 0x20A2, 0x20A2, 0x2081, 0x1881, 0x1881, 0x20A2, 0x20A2, 0x20C2, 0x28E3, 0x20A2, 0x20A1, 0x2081,   // 0x0360 (864)
+0x2081, 0x20A2, 0x20C2, 0x20A2, 0x28C2, 0x28E3, 0x28E3, 0x3103, 0x2903, 0x28E3, 0x20E2, 0x28E3, 0x2903, 0x2903, 0x2903, 0x2923,   // 0x0370 (880)
+0x2923, 0x3144, 0x0800, 0x0820, 0x0820, 0x0820, 0x0800, 0x0800, 0x0800, 0x0800, 0x0820, 0x0800, 0x0820, 0x0820, 0x0000, 0x0000,   // 0x0380 (896)
+0x0800, 0x0820, 0x0821, 0x0820, 0x0800, 0x0800, 0x0800, 0x0820, 0x0820, 0x0820, 0x0820, 0x0000, 0x2123, 0x632C, 0x9CF4, 0xBDD8,   // 0x0390 (912)
+0xDE9C, 0xDEDC, 0xDEFC, 0xDEDB, 0xD679, 0xAD33, 0x7B2A, 0x49A4, 0x51E6, 0x6247, 0x6AC9, 0x72E9, 0x7B2A, 0x8B8C, 0x8BAC, 0x836C,   // 0x03A0 (928)
+0x836B, 0x5A47, 0x49C6, 0x3104, 0x3144, 0x4207, 0x6B4D, 0x62EB, 0x62C9, 0x730A, 0x7B6C, 0x93EE, 0x732A, 0x62A9, 0x730B, 0x730A,   // 0x03B0 (944)
+0x7B4B, 0x942F, 0xA4B1, 0x9C2F, 0x9C70, 0x7B8C, 0x6B0A, 0x83AC, 0x8C0F, 0x940F, 0xB554, 0xCDD6, 0xD658, 0xD638, 0x6AEA, 0x49C6,   // 0x03C0 (960)
+0x62EA, 0x5A68, 0x93ED, 0x7B6C, 0x41C6, 0x39A5, 0x730B, 0xC594, 0xD637, 0xCDF6, 0x7B4B, 0x20C2, 0x3985, 0x5AA9, 0x3965, 0x6268,   // 0x03D0 (976)
+0x730A, 0xA46F, 0xA4B0, 0xB4F2, 0xA490, 0x940F, 0x5A47, 0x4185, 0x5207, 0x41C5, 0x41A5, 0x49C6, 0x28E3, 0x30E3, 0x28A2, 0x1861,   // 0x03E0 (992)
+0x1841, 0x2081, 0x2903, 0x1040, 0x1841, 0x1861, 0x20C2, 0x20A2, 0x2061, 0x20A1, 0x2081, 0x2081, 0x2081, 0x2081, 0x28C2, 0x28C2,   // 0x03F0 (1008)
+0x20A2, 0x20A2, 0x20C2, 0x20A2, 0x20A2, 0x20C2, 0x28C2, 0x28E3, 0x3103, 0x3123, 0x2903, 0x28E3, 0x28E3, 0x2903, 0x2903, 0x2903,   // 0x0400 (1024)
+0x2903, 0x2903, 0x2903, 0x20E2, 0x2923, 0x0820, 0x0821, 0x0820, 0x0820, 0x0800, 0x0800, 0x0800, 0x0800, 0x0820, 0x0820, 0x0820,   // 0x0410 (1040)
+0x0820, 0x0820, 0x0800, 0x0800, 0x0820, 0x0820, 0x0820, 0x0800, 0x0800, 0x0000, 0x0000, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820,   // 0x0420 (1056)
+0x1881, 0x2924, 0x4A48, 0x8C51, 0xC5F9, 0xCE7B, 0xD6BC, 0xDEDC, 0xE71D, 0xDE9A, 0xC5B5, 0x9C70, 0x7B2A, 0x730A, 0x6287, 0x6267,   // 0x0430 (1072)
+0x6AC9, 0x7B2A, 0x7B4B, 0x730A, 0x6AA9, 0x72A9, 0x5A48, 0x3985, 0x49E7, 0x5A69, 0x9451, 0x9C90, 0x9C4E, 0x940F, 0x83AD, 0x838C,   // 0x0440 (1088)
+0x6288, 0x836C, 0x8BCD, 0x83AC, 0xACD1, 0xAD12, 0x9C6F, 0x942F, 0x7B8D, 0x7B8C, 0x942F, 0x8C0E, 0xA491, 0xC5B6, 0xD658, 0xE6DA,   // 0x0450 (1104)
+0xCDF7, 0x732B, 0x5A68, 0x732B, 0x6ACA, 0x836C, 0x5A68, 0x3985, 0x41E6, 0x83AE, 0xC5B5, 0xCE17, 0xCE17, 0x9C4F, 0x49E6, 0x5268,   // 0x0460 (1120)
+0x5228, 0x49C6, 0x6289, 0x730A, 0x9C4F, 0xACB1, 0xB512, 0xACF1, 0x942F, 0x5A88, 0x5A68, 0x62A9, 0x5206, 0x49C5, 0x49E5, 0x51E6,   // 0x0470 (1136)
+0x5A27, 0x49A5, 0x4164, 0x2061, 0x2903, 0x18A2, 0x0800, 0x1841, 0x2081, 0x20A1, 0x1881, 0x1881, 0x20A2, 0x20A2, 0x20A2, 0x20A2,   // 0x0480 (1152)
+0x28C2, 0x28E2, 0x20C2, 0x28C2, 0x28C2, 0x28C2, 0x20C2, 0x20C2, 0x28E2, 0x3103, 0x3103, 0x3124, 0x3124, 0x3103, 0x2903, 0x2923,   // 0x0490 (1168)
+0x3144, 0x2903, 0x20E2, 0x20E2, 0x20E2, 0x20E2, 0x20E2, 0x2903, 0x0800, 0x0821, 0x0820, 0x0800, 0x0000, 0x0000, 0x0000, 0x0820,   // 0x04A0 (1184)
+0x0820, 0x0820, 0x0821, 0x0820, 0x0820, 0x0800, 0x0000, 0x0820, 0x0820, 0x0821, 0x0820, 0x0000, 0x0000, 0x0000, 0x0000, 0x0800,   // 0x04B0 (1200)
+0x0820, 0x0821, 0x0821, 0x0800, 0x0800, 0x3144, 0x6B2C, 0x9452, 0xA515, 0xBDB8, 0xCE7B, 0xD69B, 0xDEDC, 0xE71C, 0xE6DB, 0xD638,   // 0x04C0 (1216)
+0xB554, 0x944E, 0x7B2B, 0x6AC9, 0x5206, 0x6288, 0x72EA, 0x6268, 0x6288, 0x6AEA, 0x49C6, 0x5A68, 0x6289, 0x7B8C, 0xBD55, 0xACF2,   // 0x04D0 (1232)
+0x9C8F, 0x836C, 0x836C, 0x7B6C, 0x8B8C, 0x9C4F, 0xA4B0, 0xB532, 0xACD1, 0xA4B0, 0x8C0E, 0x7B6B, 0x7B6C, 0x940E, 0x83AC, 0xA491,   // 0x04E0 (1248)
+0xCDF8, 0xD658, 0xDE9A, 0xD659, 0xACD2, 0x72E9, 0x6AC9, 0x7B6B, 0x7B4B, 0x5227, 0x3165, 0x5A89, 0xACD2, 0xCDD6, 0xCE17, 0xCE17,   // 0x04F0 (1264)
+0x9C50, 0x5248, 0x736C, 0x732B, 0x62A9, 0x51E6, 0x6AC9, 0xA470, 0xACD1, 0xACF2, 0xACF2, 0x8BCD, 0x732B, 0x6AEA, 0x49E6, 0x5A68,   // 0x0500 (1280)
+0x5A27, 0x730A, 0x8BCD, 0x7B4B, 0x72E9, 0x51C5, 0x30E3, 0x3124, 0x1861, 0x1861, 0x3944, 0x3124, 0x1860, 0x2903, 0x3103, 0x20C2,   // 0x0510 (1296)
+0x20C2, 0x28C2, 0x2903, 0x3123, 0x20C2, 0x20A1, 0x28E2, 0x2903, 0x28C2, 0x28C2, 0x20E2, 0x20E2, 0x2903, 0x3103, 0x3123, 0x3124,   // 0x0520 (1312)
+0x3124, 0x3103, 0x3123, 0x2903, 0x28E3, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x20E2, 0x2903, 0x0800, 0x0820, 0x0820, 0x0820, 0x0000,   // 0x0530 (1328)
+0x0000, 0x0000, 0x0000, 0x0800, 0x0820, 0x0821, 0x0820, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0820, 0x0800, 0x0000, 0x0000,   // 0x0540 (1344)
+0x0000, 0x0000, 0x0800, 0x0800, 0x0820, 0x0820, 0x0820, 0x0820, 0x2924, 0x62EB, 0x734C, 0x7BAF, 0x9472, 0xAD36, 0xC619, 0xC63A,   // 0x0550 (1360)
+0xD67B, 0xDEFC, 0xE73C, 0xE6FC, 0xDEBA, 0xCE58, 0xCE17, 0xACF2, 0x8BED, 0x9C4F, 0x940E, 0x944F, 0x9C91, 0x9C71, 0x8BEE, 0x8BED,   // 0x0560 (1376)
+0x7B6B, 0xACD2, 0xACD2, 0x944F, 0x7B4B, 0x7B4B, 0x8BCD, 0xA470, 0x9C0E, 0xACB0, 0xB533, 0xACF1, 0xA490, 0x7B8C, 0x732B, 0x732B,   // 0x0570 (1392)
+0x8C0F, 0x7B6C, 0xACD2, 0xC5B6, 0xC5B6, 0xCDF7, 0xDE99, 0xBD74, 0x6AE9, 0x6AE9, 0x9C4F, 0x838C, 0x41A5, 0x3964, 0x6AEA, 0xBD74,   // 0x0580 (1408)
+0xCE17, 0xD658, 0xD638, 0x9C70, 0x49E6, 0x83AE, 0x7B6C, 0x6AEA, 0x6AC9, 0x732A, 0xACD1, 0xACF2, 0xACD1, 0xACF2, 0x940E, 0x8BCD,   // 0x0590 (1424)
+0x6AEA, 0x4185, 0x49E6, 0x730A, 0x93EE, 0x93EE, 0x940E, 0x834B, 0x6247, 0x6AA9, 0x4185, 0x3943, 0x5206, 0x6288, 0x41A5, 0x41A6,   // 0x05A0 (1440)
+0x4A07, 0x3124, 0x20C2, 0x20C3, 0x20E3, 0x20E3, 0x2103, 0x18A2, 0x20C2, 0x28E3, 0x2903, 0x2923, 0x2903, 0x20E2, 0x20C2, 0x28E2,   // 0x05B0 (1456)
+0x3123, 0x3144, 0x3123, 0x3144, 0x3123, 0x20C2, 0x1861, 0x0820, 0x0820, 0x0840, 0x18A2, 0x20C2, 0x20E2, 0x2903, 0x0000, 0x0820,   // 0x05C0 (1472)
+0x0820, 0x0820, 0x0000, 0x0000, 0x0000, 0x0000, 0x0800, 0x0800, 0x0820, 0x0820, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0800,   // 0x05D0 (1488)
+0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0820, 0x0820, 0x0821, 0x0820, 0x1881, 0x39C5, 0x6B2C, 0x8411, 0xA516,   // 0x05E0 (1504)
+0xB598, 0xBDD9, 0xBDF9, 0xCE3A, 0xD6BC, 0xD6BB, 0xDEBC, 0xE6FC, 0xE71C, 0xDEFB, 0xE71C, 0xEF1C, 0xDEDB, 0xDEDA, 0xE6FB, 0xDE99,   // 0x05F0 (1520)
+0xDEDB, 0xD699, 0xC5D6, 0xB533, 0xB4F2, 0x93CD, 0x940E, 0x8BAC, 0x7B2A, 0x838B, 0xA4B0, 0xA46F, 0x9C4F, 0xB533, 0xACF1, 0x9C70,   // 0x0600 (1536)
+0x7B8C, 0x5A48, 0x5A68, 0x8BEE, 0x944F, 0xA4B2, 0xACF3, 0x9C50, 0xBD95, 0xDE99, 0xBD74, 0x730A, 0x8BED, 0xACD1, 0x8BCD, 0x3964,   // 0x0610 (1552)
+0x5A47, 0x9C6F, 0xAD12, 0xB533, 0xC5D6, 0xCDD6, 0xA4B1, 0x5A47, 0x83AE, 0x5247, 0x62A9, 0x8BAD, 0x942F, 0xB512, 0xB513, 0xA490,   // 0x0620 (1568)
+0xACB0, 0x9C4F, 0x8BCE, 0x5A27, 0x4184, 0x5A27, 0x8BCD, 0x8BCD, 0xACD1, 0xACD1, 0x836B, 0x8BAC, 0x93CC, 0x59E5, 0x730A, 0x7B4B,   // 0x0630 (1584)
+0x6288, 0x5A68, 0x5207, 0x3103, 0x28E2, 0x20C2, 0x2924, 0x1082, 0x0800, 0x1082, 0x2103, 0x20C3, 0x20C3, 0x2965, 0x3185, 0x41E6,   // 0x0640 (1600)
+0x41C6, 0x41C6, 0x5247, 0x5A88, 0x4A06, 0x4185, 0x3964, 0x3123, 0x49C6, 0x6ACA, 0x6B0B, 0x4A07, 0x18C2, 0x0000, 0x1881, 0x20E2,   // 0x0650 (1616)
+0x2903, 0x0000, 0x0800, 0x0800, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0820, 0x0800, 0x0000, 0x0000, 0x0000,   // 0x0660 (1632)
+0x0000, 0x0800, 0x0800, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0800, 0x0820, 0x0820, 0x0820, 0x3985,   // 0x0670 (1648)
+0x7B8E, 0x83D0, 0x83D0, 0x9473, 0xAD57, 0xC61A, 0xCE3B, 0xCE5A, 0xCE7A, 0xD6BB, 0xD6BC, 0xDEDC, 0xDEDC, 0xDEDC, 0xE6FC, 0xE6DB,   // 0x0680 (1664)
+0xE6FB, 0xDEDB, 0xDE9B, 0xD679, 0xDE79, 0xC5B6, 0xCDD7, 0xB533, 0x9C4E, 0x8329, 0x93EE, 0x93CE, 0x93CC, 0xACD1, 0xA4B1, 0xB513,   // 0x0690 (1680)
+0xACD1, 0x9C2F, 0x83AD, 0x732A, 0x3143, 0x4A07, 0x942F, 0xACD2, 0x942F, 0x6AEA, 0x72EA, 0xBD74, 0xD659, 0xACD2, 0x836C, 0xACB1,   // 0x06A0 (1696)
+0x9C4F, 0x9C2F, 0x51E6, 0x93EE, 0xC574, 0x9C2F, 0x7B4B, 0xA491, 0xACF2, 0xB533, 0x83CD, 0x83CD, 0x3964, 0x72EA, 0x8BCE, 0x7B2B,   // 0x06B0 (1712)
+0xA470, 0xB4F2, 0xA490, 0xA4B0, 0x9C6F, 0x838C, 0x6288, 0x6247, 0x836C, 0x836C, 0x836C, 0xA46F, 0xA4B1, 0x9C2E, 0xACF1, 0x940E,   // 0x06C0 (1728)
+0x8BCC, 0x9C0E, 0x7B0B, 0x6289, 0x6288, 0x5206, 0x3964, 0x3124, 0x20A2, 0x1861, 0x0000, 0x0820, 0x18C2, 0x20E2, 0x3103, 0x49E6,   // 0x06D0 (1744)
+0x62C9, 0x6B0A, 0x7B8C, 0x7B4B, 0x730A, 0x6288, 0x3964, 0x49E6, 0x6AEA, 0x940F, 0xB534, 0xD679, 0xE71D, 0xE6DC, 0xD69A, 0xBD97,   // 0x06E0 (1760)
+0x736E, 0x3164, 0x20A1, 0x2903, 0x0000, 0x0000, 0x0800, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0800, 0x0800,   // 0x06F0 (1776)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0800, 0x0800, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0800, 0x0800, 0x0820,   // 0x0700 (1792)
+0x0820, 0x0800, 0x20A2, 0x736E, 0x8C31, 0x8C52, 0xA4F6, 0xB578, 0xBDD9, 0xC61A, 0xD67B, 0xD69B, 0xD6BC, 0xD69B, 0xD6BB, 0xDEBC,   // 0x0710 (1808)
+0xD69B, 0xDE9B, 0xD69A, 0xDE9B, 0xDE9B, 0xD67A, 0xD659, 0xD617, 0xC574, 0xB4F2, 0xAC90, 0x9C2E, 0x7B09, 0x834A, 0xA491, 0x9C4F,   // 0x0720 (1824)
+0xB4F2, 0xACD2, 0xACB2, 0xA490, 0x83AC, 0x5A68, 0x5227, 0x3984, 0x6288, 0xA4B0, 0xA4D2, 0x7B8C, 0x3964, 0x5227, 0xA490, 0xCE18,   // 0x0730 (1840)
+0xB4F3, 0xACB1, 0xACD1, 0x8BAC, 0x93ED, 0x834B, 0xB513, 0xC595, 0x836B, 0x4A06, 0x5227, 0x8BED, 0xB512, 0xA4B0, 0x6AC9, 0x5206,   // 0x0740 (1856)
+0x732B, 0x72EA, 0x5A68, 0xACD2, 0xA490, 0xA490, 0xA4B0, 0x93ED, 0x8B8B, 0x7B2B, 0x72E9, 0x7B2A, 0x838C, 0x93CD, 0x9C0E, 0xACD0,   // 0x0750 (1872)
+0xB4D1, 0xB534, 0xB554, 0xBD74, 0x9C0E, 0x836C, 0x6AE9, 0x62A9, 0x49C6, 0x4185, 0x3103, 0x1861, 0x0800, 0x0000, 0x0840, 0x28A2,   // 0x0760 (1888)
+0x4984, 0x6A88, 0x72E9, 0x72E9, 0x7B2A, 0x6AC9, 0x6A88, 0x51E5, 0x49C5, 0x7B6D, 0xBD96, 0xDEBB, 0xE6FD, 0xE71D, 0xDEDC, 0xD6BC,   // 0x0770 (1904)
+0xD69C, 0xCE3A, 0xC5FA, 0xC5DA, 0x8C73, 0x2923, 0x28E3, 0x0000, 0x0800, 0x0800, 0x0800, 0x0820, 0x0800, 0x0000, 0x0000, 0x0000,   // 0x0780 (1920)
+0x0000, 0x0000, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0800, 0x0020, 0x0000, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0790 (1936)
+0x0800, 0x0800, 0x0820, 0x0821, 0x1021, 0x1020, 0x5248, 0xA4F5, 0xA516, 0xAD57, 0xB5B8, 0xC63A, 0xCE5B, 0xCE7B, 0xDEBC, 0xDEBC,   // 0x07A0 (1952)
+0xD69C, 0xD67B, 0xCE5A, 0xCE3A, 0xD67B, 0xD67B, 0xD65A, 0xE6DC, 0xE6DB, 0xD659, 0xC5B6, 0xC574, 0xB512, 0xA42E, 0x93CC, 0x7B2A,   // 0x07B0 (1968)
+0x72C8, 0x8BCD, 0xA4B1, 0xACD2, 0xACD2, 0x9C70, 0x836C, 0x7B4B, 0x49C6, 0x4185, 0x5A68, 0x83AC, 0xA490, 0xA4B1, 0x83AD, 0x49E6,   // 0x07C0 (1984)
+0x5A47, 0x9C4F, 0xCE17, 0xC575, 0xBD54, 0x8BCD, 0x8B8C, 0x9C0E, 0xA46F, 0xC5D6, 0xC5D6, 0x8BAC, 0x3943, 0x3984, 0x83AD, 0xA4B0,   // 0x07D0 (2000)
+0xB4F2, 0x7B2A, 0x6AEA, 0x4185, 0x49A5, 0x7B4C, 0xA490, 0x9C4F, 0xACF2, 0xACF2, 0xA490, 0x9C0D, 0x834A, 0x7B2A, 0x8BAC, 0x93CD,   // 0x07E0 (2016)
+0x93ED, 0xA490, 0xB511, 0xBD33, 0xCDD6, 0xD638, 0xC575, 0xA490, 0x8BCD, 0x732A, 0x5A68, 0x3944, 0x3924, 0x28A2, 0x1020, 0x1041,   // 0x07F0 (2032)
+0x1861, 0x2081, 0x4124, 0x51E6, 0x6267, 0x5A47, 0x6247, 0x5206, 0x5206, 0x7309, 0x944F, 0xC5B5, 0xE6FC, 0xE6DC, 0xD69B, 0xD69B,   // 0x0800 (2048)
+0xD67B, 0xCE5B, 0xC5FA, 0xB577, 0xA4B4, 0x8BF0, 0x8C51, 0x94B4, 0x4A07, 0x2903, 0x0000, 0x0800, 0x0800, 0x0800, 0x0820, 0x0000,   // 0x0810 (2064)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0800, 0x0800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0800, 0x0800, 0x0800, 0x0800, 0x0000,   // 0x0820 (2080)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0800, 0x0820, 0x0821, 0x1021, 0x1020, 0x3986, 0x9CD5, 0xB577, 0xB577, 0xB577, 0xBDF9, 0xCE5B,   // 0x0830 (2096)
+0xCE7B, 0xC63A, 0xC63A, 0xC63A, 0xC5F9, 0xC5F9, 0xC619, 0xC5F9, 0xC5F9, 0xD65A, 0xDE9B, 0xE6BB, 0xD679, 0xC5B5, 0xB4F1, 0xAC90,   // 0x0840 (2112)
+0xACB1, 0x9C2F, 0x8BAC, 0x834B, 0x8B8B, 0x8B8B, 0xACF2, 0xA491, 0xACD1, 0x8BAD, 0x732A, 0x5206, 0x49C5, 0x7B4B, 0xACB1, 0xB4F1,   // 0x0850 (2128)
+0x942F, 0x8BCD, 0x7B8C, 0x6AEA, 0x9C50, 0xD658, 0xCDF7, 0xBD54, 0x7B0A, 0x9C4F, 0xB4D1, 0xB531, 0xCDF6, 0xBD74, 0x836C, 0x51C6,   // 0x0860 (2144)
+0x62A9, 0x8BAD, 0xACD1, 0xC574, 0xACD1, 0x7B4B, 0x3944, 0x51E6, 0x9C2F, 0x93ED, 0x9C4F, 0xA4B1, 0xACF2, 0xA46F, 0x93AC, 0x836B,   // 0x0870 (2160)
+0x93ED, 0x93AC, 0x9BED, 0x9C0E, 0xACB0, 0xACB0, 0xBD73, 0xCDF6, 0xCDF7, 0xCDD6, 0xC5F7, 0xBD75, 0xB534, 0x942F, 0x838D, 0x730B,   // 0x0880 (2176)
+0x4184, 0x28A1, 0x28A2, 0x28C2, 0x3923, 0x51C5, 0x6267, 0x6247, 0x6267, 0x834B, 0x940E, 0xACF1, 0xD658, 0xE6FC, 0xDEDC, 0xD67B,   // 0x0890 (2192)
+0xCE19, 0xC5F9, 0xC61A, 0xCE3A, 0xBDB9, 0xA4D4, 0x8BF0, 0x734D, 0x6AEB, 0x734C, 0x6B6D, 0x41A5, 0x2903, 0x0000, 0x0000, 0x0800,   // 0x08A0 (2208)
+0x0820, 0x0820, 0x0800, 0x0000, 0x0800, 0x0000, 0x0000, 0x0800, 0x0800, 0x0820, 0x0000, 0x0000, 0x0000, 0x0800, 0x0800, 0x0800,   // 0x08B0 (2224)
+0x0800, 0x0820, 0x0820, 0x0800, 0x0000, 0x0000, 0x0000, 0x0800, 0x0820, 0x0821, 0x1061, 0x1040, 0x1861, 0x734D, 0xAD77, 0xAD37,   // 0x08C0 (2240)
+0xBD98, 0xC5D9, 0xBDB8, 0xC5F9, 0xBDB8, 0xB577, 0xBDD9, 0xD67C, 0xCE5B, 0xCE1A, 0xBDB9, 0xBDB8, 0xCE19, 0xD69A, 0xDE9A, 0xD618,   // 0x08D0 (2256)
+0xBD95, 0xAC90, 0xA46F, 0x9C4F, 0x942E, 0x9C70, 0x8BAC, 0x93CD, 0x8BAC, 0x93EE, 0xACD2, 0xA4D1, 0x9C90, 0x838C, 0x7B2B, 0x72E9,   // 0x08E0 (2272)
+0xA490, 0xBD53, 0xC5B5, 0xB554, 0xA4B2, 0x9C90, 0x62CA, 0x93ED, 0xCDD7, 0xC595, 0xACD2, 0x8BAD, 0xACD1, 0xBD53, 0xC594, 0xC574,   // 0x08F0 (2288)
+0x93EE, 0x7B2B, 0x7B4C, 0x942F, 0x942E, 0xBD73, 0xCDD6, 0xC573, 0x8B8B, 0x5206, 0x72EA, 0x93CD, 0x93ED, 0xA4D1, 0xACD1, 0xACD1,   // 0x0900 (2304)
+0x9C0E, 0xA490, 0xA490, 0x9C0D, 0x8B8B, 0x9BED, 0xA42E, 0xA42E, 0xAC8F, 0xACF1, 0xB553, 0xC595, 0xD617, 0xE6BA, 0xDEBA, 0xDE79,   // 0x0910 (2320)
+0xEEFC, 0xE6DB, 0xCE38, 0xB533, 0x942E, 0x838C, 0x838C, 0x8BAD, 0x9C4F, 0xB4F2, 0xBD73, 0xCDF6, 0xCE37, 0xD679, 0xE6DB, 0xE71C,   // 0x0920 (2336)
+0xD69B, 0xBDB8, 0xBD98, 0xBD98, 0xAD16, 0xA4D5, 0x9473, 0x83EF, 0x7BAE, 0x734D, 0x6B2B, 0x7BAE, 0x8C30, 0x5AAA, 0x3144, 0x3123,   // 0x0930 (2352)
+0x0000, 0x0020, 0x0800, 0x0800, 0x0800, 0x0820, 0x0820, 0x0800, 0x0800, 0x0800, 0x0800, 0x0820, 0x0820, 0x0800, 0x0820, 0x0800,   // 0x0940 (2368)
+0x0800, 0x0800, 0x0820, 0x0800, 0x0821, 0x0820, 0x0800, 0x0800, 0x0800, 0x0800, 0x0800, 0x0820, 0x1040, 0x1041, 0x1061, 0x1020,   // 0x0950 (2384)
+0x3165, 0x9CD5, 0xBDB8, 0xC5D9, 0xB578, 0xBDB8, 0xBDD9, 0xBDB8, 0xCE5B, 0xD6BC, 0xC63A, 0xCE3A, 0xCE5B, 0xCE1A, 0xD65A, 0xD65A,   // 0x0960 (2400)
+0xCE59, 0xD659, 0xBD75, 0xB533, 0xACB0, 0x9C0D, 0x9BED, 0x832A, 0x7B6B, 0x9430, 0x8BCE, 0x7B2B, 0x93EE, 0x942F, 0xAD13, 0xACF2,   // 0x0970 (2416)
+0xA490, 0x8BCD, 0x8BEE, 0xBD54, 0xCE17, 0xD658, 0xCDF7, 0xC5B6, 0xA490, 0x62A9, 0x9C4F, 0xBD53, 0xA470, 0x9C70, 0x9C70, 0xA46F,   // 0x0980 (2432)
+0xC574, 0xC595, 0xA490, 0x72EA, 0x836B, 0xA490, 0xB574, 0xBD94, 0xCDF6, 0xC5B5, 0xBD53, 0x9C2E, 0x7B2A, 0x93ED, 0x93AD, 0x9C2E,   // 0x0990 (2448)
+0xACF2, 0xA4D1, 0xB513, 0xACB0, 0xACB1, 0x9C2E, 0x93AC, 0x9C2D, 0xA44E, 0xA42E, 0x9C2D, 0xA40D, 0xA42E, 0xB512, 0xC574, 0xD638,   // 0x09A0 (2464)
+0xDE9A, 0xD659, 0xDE9A, 0xE6DB, 0xE6FB, 0xE6FB, 0xE6FB, 0xE6FB, 0xE6FB, 0xE6DA, 0xE6DA, 0xE6DB, 0xDE9A, 0xDE9A, 0xDEDB, 0xD67A,   // 0x09B0 (2480)
+0xCE3A, 0xCE39, 0xC5F9, 0xB597, 0xC61A, 0xC5D9, 0xA516, 0x9C93, 0x8C31, 0x83AF, 0x6B0B, 0x62C9, 0x62CA, 0x734D, 0x9473, 0x8411,   // 0x09C0 (2496)
+0x41C6, 0x2903, 0x3123, 0x0800, 0x0800, 0x0820, 0x0820, 0x0800, 0x0820, 0x0820, 0x0820, 0x0800, 0x0820, 0x0800, 0x0820, 0x1021,   // 0x09D0 (2512)
+0x0820, 0x0820, 0x0820, 0x0800, 0x0820, 0x0821, 0x0800, 0x1021, 0x0821, 0x0820, 0x0820, 0x0800, 0x0800, 0x0820, 0x0840, 0x1040,   // 0x09E0 (2528)
+0x1061, 0x1061, 0x1861, 0x1881, 0x736D, 0xCE3B, 0xC5FA, 0xBDB8, 0xC5D9, 0xCE5B, 0xD69C, 0xCE3A, 0xC5F9, 0xCE3A, 0xD67B, 0xD69C,   // 0x09F0 (2544)
+0xD69C, 0xD67B, 0xD67B, 0xD67A, 0xBD95, 0xBD74, 0xA490, 0xA46F, 0x9C0D, 0x93CC, 0x7B4B, 0x6A88, 0x7B0B, 0x8BCF, 0x6AEA, 0x838C,   // 0x0A00 (2560)
+0xA470, 0xACF3, 0xB534, 0xA4D2, 0x83CD, 0x940E, 0xB554, 0xCE17, 0xDE99, 0xDE9A, 0xCDF7, 0xA470, 0x730B, 0xA4B1, 0xA490, 0x93EE,   // 0x0A10 (2576)
+0x942F, 0x9C90, 0x940E, 0xBD33, 0xCDD6, 0x942E, 0x6268, 0x8BCC, 0xBD74, 0xD679, 0xD638, 0xD678, 0xC5B5, 0xBD34, 0x9C4F, 0x93ED,   // 0x0A20 (2592)
+0x93CD, 0x9C4F, 0xACB1, 0xA490, 0xA46F, 0xA4D2, 0xACF1, 0xA490, 0x9C2E, 0x9C2E, 0x9C2D, 0x9BED, 0x9BED, 0x9C0D, 0x8B8B, 0xA44E,   // 0x0A30 (2608)
+0xB4F1, 0xBD53, 0xDE79, 0xD679, 0xDE79, 0xDE9A, 0xDE9A, 0xD639, 0xD658, 0xDE9A, 0xE6DB, 0xE6BB, 0xDEBA, 0xCE18, 0xC5D7, 0xC5F9,   // 0x0A40 (2624)
+0xD67A, 0xD67B, 0xD65A, 0xCE1A, 0xCE3A, 0xCDFA, 0xC5FA, 0xBDB9, 0xB5B9, 0xB557, 0xA4F5, 0xA4F5, 0x8C11, 0x7BAE, 0x7B8E, 0x83AF,   // 0x0A50 (2640)
+0xA4D5, 0xBDBA, 0x83D0, 0x39A5, 0x2923, 0x3123, 0x0000, 0x0820, 0x0820, 0x0820, 0x1020, 0x0820, 0x0820, 0x0820, 0x0820, 0x0820,   // 0x0A60 (2656)
+0x0820, 0x0821, 0x1020, 0x1020, 0x1021, 0x0840, 0x0820, 0x0821, 0x1020, 0x1020, 0x1020, 0x0821, 0x1021, 0x0801, 0x0820, 0x0820,   // 0x0A70 (2672)
+0x0820, 0x1040, 0x1041, 0x1061, 0x1861, 0x1882, 0x1061, 0x3145, 0xB577, 0xD67C, 0xCE5B, 0xCE3B, 0xCE3B, 0xCE3A, 0xCE7B, 0xDEBC,   // 0x0A80 (2688)
+0xE6FD, 0xE6FD, 0xD69C, 0xCE7B, 0xD67A, 0xD659, 0xCE18, 0xBD75, 0xB512, 0xB512, 0xA46E, 0x9BED, 0x836C, 0x7B2B, 0x6AC9, 0x49E6,   // 0x0A90 (2704)
+0x4A06, 0x6AEA, 0x8BCD, 0xACD1, 0xACF2, 0xACF2, 0xACD2, 0x940E, 0x940E, 0xAD13, 0xCDF7, 0xDEBA, 0xDEBB, 0xD638, 0xA491, 0x83AD,   // 0x0AA0 (2720)
+0xACF2, 0x8BAC, 0x93CD, 0x732B, 0x8BCD, 0x942E, 0x9C6F, 0xC595, 0x8BCD, 0x6AA9, 0xACF2, 0xDE78, 0xE6DB, 0xDE79, 0xD679, 0xCDF6,   // 0x0AB0 (2736)
+0xB512, 0x940E, 0x9C4F, 0x940E, 0xACB1, 0xACD1, 0xA470, 0x93EE, 0x8BAD, 0x9C4F, 0x9C2F, 0xA470, 0x9C4E, 0x93AC, 0x9BED, 0x9BCC,   // 0x0AC0 (2752)
+0x8B4A, 0x93AC, 0xA44E, 0xAC6F, 0xB511, 0xCE16, 0xDE7A, 0xE6DB, 0xDE9A, 0xCDF8, 0xC5D7, 0xCDF8, 0xCE18, 0xC5D8, 0xBD77, 0xB556,   // 0x0AD0 (2768)
+0xC5B8, 0xCE3A, 0xCE3A, 0xCE1A, 0xCE19, 0xCE19, 0xCE5B, 0xD67B, 0xCE5B, 0xC5F9, 0xB578, 0xA4D5, 0x9CB4, 0x9C92, 0x9452, 0x9C73,   // 0x0AE0 (2784)
+0x9C73, 0x9CB5, 0xB578, 0xC61B, 0xA4F6, 0x5249, 0x2923, 0x2903, 0x2923, 0x0821, 0x0820, 0x0821, 0x1020, 0x1020, 0x1020, 0x0820,   // 0x0AF0 (2800)
+0x0820, 0x0820, 0x0820, 0x0820, 0x0820, 0x1020, 0x1020, 0x1020, 0x0820, 0x0820, 0x1021, 0x1020, 0x1020, 0x1020, 0x1020, 0x1020,   // 0x0B00 (2816)
+0x0820, 0x0820, 0x0820, 0x0821, 0x1041, 0x1061, 0x1061, 0x1882, 0x1881, 0x1061, 0x2903, 0xAD35, 0xDEBD, 0xCE7B, 0xCE3B, 0xC61A,   // 0x0B10 (2832)
+0xCE7B, 0xDEBC, 0xE6FD, 0xE6FD, 0xDEFD, 0xDEDC, 0xD69B, 0xD65B, 0xC5D7, 0xBD74, 0xC594, 0xB4F1, 0xB4D0, 0xAC8F, 0x93AC, 0x6AA9,   // 0x0B20 (2848)
+0x51E6, 0x5A69, 0x4A07, 0x4A07, 0x6AEA, 0x838D, 0xC5B6, 0xC5D6, 0x940E, 0x7B6B, 0x83AD, 0x93EE, 0xB553, 0xCE18, 0xDE9A, 0xE6FC,   // 0x0B30 (2864)
+0xD658, 0xB4F2, 0x93CE, 0x9C4F, 0x7B4A, 0x93CD, 0x7B0A, 0x9C2E, 0x9C2E, 0x9C4F, 0xB4F2, 0x8BCD, 0x836B, 0xCDF6, 0xEEFB, 0xEF1C,   // 0x0B40 (2880)
+0xDEBA, 0xD678, 0xCDD6, 0x9C2F, 0x838C, 0x838C, 0x8BEE, 0xACF2, 0xB513, 0xA46F, 0x8B8C, 0x7B0A, 0x6288, 0x6268, 0x83AC, 0x9C2E,   // 0x0B50 (2896)
+0x9BCC, 0x9BED, 0x9BED, 0x93AC, 0xA40D, 0x9BCC, 0xA42D, 0xACB0, 0xC5D6, 0xD659, 0xDE9A, 0xD639, 0xCE18, 0xCDF8, 0xBD96, 0xBD76,   // 0x0B60 (2912)
+0xBD97, 0xCE19, 0xD65A, 0xDE9B, 0xD6BB, 0xD69B, 0xD69B, 0xD69B, 0xCE5A, 0xC5F9, 0xCE5B, 0xCE5B, 0xCE5B, 0xBD98, 0xAD37, 0xAD16,   // 0x0B70 (2928)
+0xAD15, 0xACF5, 0xACF5, 0xB578, 0xBDB9, 0xCE3B, 0xC61A, 0x5ACA, 0x20C1, 0x20E3, 0x2903, 0x2923, 0x1021, 0x1021, 0x1021, 0x1020,   // 0x0B80 (2944)
+0x1020, 0x1021, 0x1020, 0x1020, 0x1021, 0x1020, 0x0820, 0x0840, 0x0820, 0x1020, 0x1020, 0x1020, 0x1020, 0x1021, 0x1020, 0x1020,   // 0x0B90 (2960)
+0x1020, 0x1020, 0x1020, 0x1020, 0x1020, 0x1020, 0x1021, 0x1020, 0x1041, 0x1061, 0x1061, 0x1061, 0x1881, 0x2103, 0xA4F5, 0xE71E,   // 0x0BA0 (2976)
+0xDEBC, 0xD6BC, 0xD69B, 0xCE7B, 0xDEDD, 0xDEFD, 0xE6FD, 0xE71D, 0xD69B, 0xCE1A, 0xC5D8, 0xC5B7, 0xBD13, 0xBD53, 0xBD32, 0xB4F1,   // 0x0BB0 (2992)
+0xACB0, 0x9BED, 0x836B, 0x51E6, 0x3144, 0x3944, 0x3165, 0x6B0B, 0xA491, 0xB513, 0xD638, 0x8BCE, 0x49C6, 0x5A68, 0x93EE, 0xBD74,   // 0x0BC0 (3008)
+0xD638, 0xDEBA, 0xEF3C, 0xDEBA, 0xBD33, 0x8BAD, 0x93ED, 0x834B, 0x9C0E, 0x93CD, 0xB513, 0xA46F, 0x93CD, 0xB4D1, 0x9C0E, 0xA44E,   // 0x0BD0 (3024)
+0xE6BA, 0xEF1C, 0xEF3C, 0xDEBA, 0xCE17, 0xBD95, 0x7B4B, 0x732A, 0x730A, 0xA470, 0xBD54, 0xBD33, 0xAC90, 0x7B4B, 0x5206, 0x41A5,   // 0x0BE0 (3040)
+0x5227, 0x732B, 0x838C, 0x8B4A, 0x9BCD, 0xA40D, 0xA44E, 0xAC4E, 0xA40D, 0xB4AF, 0xB4F1, 0xC574, 0xC574, 0xCE38, 0xD639, 0xC5B7,   // 0x0BF0 (3056)
+0xB555, 0xB555, 0xB576, 0xC5D8, 0xC5B7, 0xC5F8, 0xCE3A, 0xD65A, 0xCE7A, 0xD69B, 0xDEFC, 0xDEDC, 0xE6FD, 0xD69C, 0xCE5B, 0xCE3B,   // 0x0C00 (3072)
+0xCE5B, 0xBDB9, 0xBDB9, 0xC5B9, 0xC5D8, 0xC5F9, 0xCE1B, 0xD67C, 0xDEBD, 0x9CD4, 0x3964, 0x20E2, 0x28E2, 0x28E3, 0x2903, 0x1021,   // 0x0C10 (3088)
+0x1021, 0x1021, 0x1020, 0x1040, 0x1021, 0x1020, 0x1020, 0x1020, 0x1020, 0x1020, 0x1040, 0x1020, 0x1020, 0x1020, 0x1021, 0x1021,   // 0x0C20 (3104)
+0x1020, 0x1020, 0x1021, 0x1021, 0x1020, 0x1020, 0x1021, 0x1021, 0x1020, 0x1020, 0x1021, 0x1041, 0x1041, 0x1041, 0x1061, 0x1882,   // 0x0C30 (3120)
+0x20C2, 0x5AAA, 0xC63A, 0xE6FD, 0xDEDC, 0xD69B, 0xCE1A, 0xD65B, 0xE71D, 0xE73D, 0xDEDC, 0xCE5A, 0xBD76, 0xBD95, 0xBD54, 0xBD33,   // 0x0C40 (3136)
+0xBD33, 0xB4F1, 0xACB0, 0xAC90, 0x93CD, 0x72EA, 0x5A27, 0x3103, 0x3124, 0x20E2, 0x3144, 0x940F, 0xC5B6, 0xC5B6, 0x940F, 0x3964,   // 0x0C50 (3152)
+0x41A5, 0x83AD, 0xBD95, 0xDEBB, 0xEF1C, 0xEF5D, 0xE6DA, 0xC5B5, 0xA46F, 0xA44F, 0x93ED, 0x9C0E, 0xACB1, 0xBD33, 0xB4F1, 0xA470,   // 0x0C60 (3168)
+0xC553, 0xB4D1, 0xBD32, 0xE71A, 0xEF5C, 0xE71B, 0xDEB9, 0xD638, 0x942F, 0x5A67, 0x5A67, 0x730A, 0xA4B1, 0xBD54, 0xCDF6, 0xB512,   // 0x0C70 (3184)
+0x838C, 0x5207, 0x41A5, 0x5A48, 0x6AA9, 0x7B2B, 0x8B8C, 0x93AC, 0xA44E, 0xB4D0, 0xA44E, 0xA42D, 0xA44E, 0xB4D1, 0xC553, 0xCDB5,   // 0x0C80 (3200)
+0xC595, 0xBD75, 0xB535, 0xAD14, 0xB535, 0xBDB7, 0xCE39, 0xCE1A, 0xCE19, 0xCE5A, 0xC63A, 0xC5F9, 0xCE3A, 0xCE5B, 0xCE3A, 0xCE5B,   // 0x0C90 (3216)
+0xD67B, 0xDEDD, 0xD67B, 0xC5F9, 0xCE1A, 0xCDF9, 0xC5B9, 0xCE1A, 0xD65B, 0xD67C, 0xDEBD, 0xC61A, 0x5A8A, 0x20E2, 0x2902, 0x20E2,   // 0x0CA0 (3232)
+0x2102, 0x2923, 0x1021, 0x1021, 0x1021, 0x1021, 0x1021, 0x1021, 0x1020, 0x1020, 0x1020, 0x1020, 0x1020, 0x0820, 0x0820, 0x1020,   // 0x0CB0 (3248)
+0x1020, 0x1021, 0x0821, 0x0820, 0x0820, 0x0820, 0x0821, 0x1021, 0x0821, 0x0821, 0x1021, 0x0821, 0x0820, 0x1021, 0x1020, 0x1041,   // 0x0CC0 (3264)
+0x1061, 0x1061, 0x1061, 0x20E2, 0x5ACA, 0xB598, 0xD6DC, 0xD69B, 0xCE3A, 0xCE5A, 0xDE9B, 0xE71D, 0xE6FC, 0xDEBC, 0xCE5A, 0xB554,   // 0x0CD0 (3280)
+0xACF1, 0xC575, 0xBD53, 0xBD53, 0xB4D1, 0xB4F2, 0xA46F, 0x834B, 0x6248, 0x5A68, 0x6268, 0x5247, 0x5268, 0x41A5, 0x6AA8, 0xC5B6,   // 0x0CE0 (3296)
+0xCE18, 0x9C91, 0x41A5, 0x3964, 0x83AD, 0xBD95, 0xE71C, 0xF77D, 0xF79D, 0xE71B, 0xD637, 0xBD53, 0xBD94, 0xBD53, 0xB4D1, 0xC594,   // 0x0CF0 (3312)
+0xB4D1, 0xC574, 0xBD32, 0xC594, 0xD636, 0xD616, 0xEF1B, 0xF79D, 0xEF3C, 0xDEB9, 0xC5D6, 0x730A, 0x5206, 0x3944, 0x6ACA, 0xA4B1,   // 0x0D00 (3328)
+0xCE17, 0xCE38, 0xB4F3, 0x838C, 0x5227, 0x3985, 0x28E2, 0x4164, 0x6AC9, 0x7B0A, 0x832A, 0xA42E, 0xAC6F, 0xB4AF, 0xAC4D, 0xB4AF,   // 0x0D10 (3344)
+0xBD32, 0xC553, 0xC5B5, 0xCDF7, 0xC5B6, 0xC5D7, 0xC5D7, 0xCDF8, 0xC5F8, 0xC5D8, 0xD69B, 0xDEDC, 0xDEDC, 0xD67B, 0xD67B, 0xCE7B,   // 0x0D20 (3360)
+0xC61A, 0xC5FA, 0xC5D9, 0xC5FA, 0xC61A, 0xDE9C, 0xD67B, 0xC5FA, 0xCE3B, 0xD65B, 0xD67C, 0xDEBC, 0xE6FD, 0xE73E, 0xA4D5, 0x3965,   // 0x0D30 (3376)
+0x3144, 0x41C6, 0x20E2, 0x20E2, 0x2903, 0x1021, 0x1021, 0x0821, 0x0821, 0x1021, 0x1021, 0x1020, 0x1020, 0x0821, 0x0821, 0x1021,   // 0x0D40 (3392)
+0x1021, 0x1021, 0x1021, 0x1020, 0x1021, 0x0820, 0x0820, 0x0821, 0x0821, 0x0821, 0x1021, 0x0821, 0x0820, 0x0821, 0x0821, 0x0821,   // 0x0D50 (3408)
+0x0821, 0x1020, 0x1040, 0x1061, 0x1041, 0x1061, 0x1081, 0x6B4D, 0xD6BD, 0xE73E, 0xDEDC, 0xC5D8, 0xBD76, 0xC5D8, 0xDE9A, 0xE71D,   // 0x0D60 (3424)
+0xDEBB, 0xD67A, 0xC5B7, 0xACB1, 0xB532, 0xB532, 0xB513, 0xB512, 0xACF3, 0xACD1, 0x8BAC, 0x7B0A, 0x838C, 0xA491, 0x9C2F, 0x8B8C,   // 0x0D70 (3440)
+0x730A, 0x6267, 0xACB1, 0xD658, 0xACF2, 0x5A88, 0x5A47, 0x8BCE, 0xC5D6, 0xEF5C, 0xF79D, 0xF79D, 0xEF5C, 0xE699, 0xD5F6, 0xDE78,   // 0x0D80 (3456)
+0xCE17, 0xBD53, 0xCD94, 0xB4F1, 0xD657, 0xCDF5, 0xD616, 0xE6DA, 0xE6D9, 0xF75C, 0xFFBE, 0xF77D, 0xD679, 0x9C70, 0x6AA9, 0x3984,   // 0x0D90 (3472)
+0x3103, 0x730B, 0xB533, 0xCDF7, 0xC5D6, 0x940F, 0x5A67, 0x3964, 0x20A2, 0x20A2, 0x4164, 0x5206, 0x49E6, 0x6AA8, 0xA46F, 0xBCF1,   // 0x0DA0 (3488)
+0xB4B0, 0xBD11, 0xBCF1, 0xB4B0, 0xBD53, 0xC594, 0xC574, 0xC595, 0xC5D7, 0xCE18, 0xD639, 0xDE9B, 0xDE9B, 0xCE3A, 0xD67B, 0xDEDC,   // 0x0DB0 (3504)
+0xCE5A, 0xC619, 0xD67B, 0xD67C, 0xC5F9, 0xB557, 0xB577, 0xC5FA, 0xC5D9, 0xCE3B, 0xD63B, 0xD65C, 0xDE9D, 0xE6DD, 0xE6DC, 0xE71D,   // 0x0DC0 (3520)
+0xCE5A, 0x5269, 0x2903, 0x2903, 0x2903, 0x20E2, 0x20E2, 0x2903, 0x1021, 0x1021, 0x0820, 0x0821, 0x0821, 0x0821, 0x0821, 0x1021,   // 0x0DD0 (3536)
+0x1020, 0x1020, 0x1040, 0x1040, 0x1040, 0x1020, 0x1021, 0x0821, 0x0821, 0x0821, 0x1020, 0x1041, 0x0821, 0x0821, 0x1021, 0x1021,   // 0x0DE0 (3552)
+0x1021, 0x0821, 0x0820, 0x1021, 0x1021, 0x1041, 0x1041, 0x1041, 0x1061, 0x1881, 0x3164, 0xA535, 0xF7BF, 0xE75E, 0xCE1A, 0xBD77,   // 0x0DF0 (3568)
+0xBD97, 0xB556, 0xD67A, 0xE6FC, 0xDEBB, 0xCDF8, 0xB533, 0xACF1, 0xACD1, 0xACD1, 0xBD34, 0xACD2, 0x9C50, 0x9C2F, 0x942E, 0x8BCD,   // 0x0E00 (3584)
+0x9C4F, 0xACF2, 0xB512, 0xA4B0, 0x838C, 0x93ED, 0xD658, 0xCE18, 0x836C, 0x7309, 0x9C2F, 0xCE58, 0xF79D, 0xF7BE, 0xF79D, 0xF79C,   // 0x0E10 (3600)
+0xDE58, 0xD637, 0xDE98, 0xDE58, 0xC574, 0xD616, 0xC573, 0xDE78, 0xDE98, 0xDE37, 0xE73B, 0xEF5B, 0xF79D, 0xFFDE, 0xF79D, 0xCDF7,   // 0x0E20 (3616)
+0xA4B1, 0x72E9, 0x3964, 0x49E5, 0x9C90, 0xD659, 0xCE18, 0x942F, 0x5206, 0x30E2, 0x3944, 0x4184, 0x41A5, 0x51E6, 0x49A5, 0x5206,   // 0x0E30 (3632)
+0x72C9, 0xA44F, 0xACB0, 0xB4D1, 0xB511, 0xB4B0, 0xB4D1, 0xC533, 0xC553, 0xC553, 0xC595, 0xCDD7, 0xC5B7, 0xCE39, 0xDE9B, 0xDEBC,   // 0x0E40 (3648)
+0xD6BC, 0xD6BB, 0xDEDC, 0xDEDC, 0xDEDC, 0xD67B, 0xC61A, 0xD67B, 0xD67B, 0xCE19, 0xC5FA, 0xCE1A, 0xCE1A, 0xD65C, 0xD67C, 0xE6DD,   // 0x0E50 (3664)
+0xE6FD, 0xE71D, 0xE6FD, 0x83CF, 0x3143, 0x2903, 0x28E3, 0x28E3, 0x28E3, 0x28E3, 0x2903, 0x0821, 0x0821, 0x0821, 0x0820, 0x1021,   // 0x0E60 (3680)
+0x0821, 0x1021, 0x1021, 0x1040, 0x1040, 0x1040, 0x1040, 0x1040, 0x1040, 0x0820, 0x0820, 0x1020, 0x1020, 0x1020, 0x1041, 0x1041,   // 0x0E70 (3696)
+0x1021, 0x1041, 0x1041, 0x1021, 0x0820, 0x0821, 0x1020, 0x1041, 0x1040, 0x1041, 0x1041, 0x1861, 0x20E3, 0x18A1, 0x5248, 0xDF1D,   // 0x0E80 (3712)
+0xEF7E, 0xE6FD, 0xD67B, 0xC5F9, 0xCE19, 0xC5F8, 0xD659, 0xCE39, 0xC596, 0xC553, 0xC574, 0xB533, 0xACD1, 0xA490, 0xA470, 0x9C50,   // 0x0E90 (3728)
+0x9C70, 0xB512, 0xB4F1, 0xACD1, 0x9C0E, 0xACB0, 0xC573, 0xBD33, 0xACD1, 0xCE17, 0xE6DB, 0xB4F2, 0x940E, 0xBD54, 0xD679, 0xF7BE,   // 0x0EA0 (3744)
+0xF79E, 0xF79D, 0xF77C, 0xDE78, 0xD616, 0xD657, 0xE6BA, 0xCDD5, 0xDE77, 0xD636, 0xD657, 0xE6D9, 0xD636, 0xE6FA, 0xEF5C, 0xFFBE,   // 0x0EB0 (3760)
+0xFFDE, 0xF79D, 0xD679, 0xB512, 0x730A, 0x49C6, 0x83AD, 0xCDF7, 0xD658, 0x940E, 0x51C5, 0x4985, 0x5A47, 0x6AA9, 0x836B, 0x93AC,   // 0x0EC0 (3776)
+0x834A, 0x72E9, 0x72E9, 0x832B, 0x9C0E, 0xAC90, 0xB512, 0xC553, 0xC553, 0xBD11, 0xBD11, 0xC553, 0xC533, 0xC573, 0xBD12, 0xBD13,   // 0x0ED0 (3792)
+0xBD96, 0xCDF8, 0xD67A, 0xE6FC, 0xE71D, 0xEF3D, 0xEF5E, 0xE73D, 0xE73D, 0xEF3D, 0xE71E, 0xDEFD, 0xD69C, 0xC5D9, 0xC5D9, 0xCE3A,   // 0x0EE0 (3808)
+0xD65B, 0xDEBC, 0xE6FD, 0xE6FD, 0xEF5E, 0xD6BC, 0x734D, 0x3144, 0x2903, 0x2903, 0x2903, 0x2903, 0x28E3, 0x2903, 0x0821, 0x0821,   // 0x0EF0 (3824)
+0x1021, 0x1041, 0x1040, 0x0841, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1040, 0x1040, 0x1041, 0x1040,   // 0x0F00 (3840)
+0x1040, 0x1041, 0x1041, 0x1041, 0x1041, 0x1061, 0x1041, 0x1041, 0x1021, 0x1020, 0x1041, 0x1041, 0x1041, 0x1041, 0x1861, 0x18A2,   // 0x0F10 (3856)
+0x1881, 0x3123, 0xB596, 0xE71D, 0xDEFD, 0xDEFC, 0xD69B, 0xDEBC, 0xD67B, 0xC5D7, 0xC5B6, 0xBD13, 0xBD12, 0xBD53, 0xBD74, 0xB533,   // 0x0F20 (3872)
+0xACB1, 0xA470, 0xB4F2, 0xC596, 0xC5D6, 0xC5B5, 0xC5B6, 0xCDD6, 0xB533, 0xCDB6, 0xD637, 0xCDD5, 0xD657, 0xEF7D, 0xD658, 0xB533,   // 0x0F30 (3888)
+0xD679, 0xE73C, 0xFFDF, 0xFFBE, 0xF79D, 0xE6FB, 0xE6B8, 0xD657, 0xD637, 0xE6DA, 0xDE77, 0xEEF9, 0xDE77, 0xDE57, 0xE6D9, 0xD637,   // 0x0F40 (3904)
+0xE6FA, 0xF77C, 0xFFBE, 0xFFFF, 0xF79D, 0xDE99, 0xACD2, 0x72E9, 0x7B4B, 0xCDF7, 0xDEBA, 0xACD1, 0x8B8B, 0x836B, 0xA46F, 0xACD0,   // 0x0F50 (3920)
+0xB4F1, 0xBD12, 0xACB0, 0x8B6B, 0x8BCD, 0x8B8C, 0x8B8C, 0xA46F, 0xB4F1, 0xBD53, 0xC574, 0xC553, 0xC553, 0xC573, 0xBD12, 0xB4D0,   // 0x0F60 (3936)
+0xBD11, 0xBCF1, 0xB4D1, 0xACB1, 0xBD75, 0xCE59, 0xDE9B, 0xE6FC, 0xF77E, 0xF7BF, 0xF77E, 0xEF5D, 0xE6FC, 0xD69B, 0xCE1A, 0xC5D9,   // 0x0F70 (3952)
+0xC5D9, 0xBD97, 0xC5D8, 0xD63A, 0xE6DC, 0xDEDC, 0xE71D, 0xEF7E, 0xBDD8, 0x5269, 0x3124, 0x2923, 0x3124, 0x2903, 0x28E3, 0x20E2,   // 0x0F80 (3968)
+0x2903, 0x1040, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1061, 0x1041, 0x1041, 0x1041,   // 0x0F90 (3984)
+0x1041, 0x1061, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1040, 0x1041, 0x1041, 0x1041,   // 0x0FA0 (4000)
+0x1041, 0x1041, 0x1881, 0x20A2, 0x2903, 0x9451, 0xDEDC, 0xD6BB, 0xD6BC, 0xD69B, 0xCE39, 0xCE19, 0xCDF8, 0xC575, 0xBD53, 0xC553,   // 0x0FB0 (4016)
+0xBD33, 0xC594, 0xBD54, 0xACD2, 0xB513, 0xBD75, 0xC5D7, 0xCE18, 0xD679, 0xD679, 0xDEBA, 0xE6FB, 0xD679, 0xDEBA, 0xDE9A, 0xE6FB,   // 0x0FC0 (4032)
+0xEF5D, 0xF77D, 0xE6DB, 0xE71B, 0xF79E, 0xFFDF, 0xFFDE, 0xF79D, 0xE6FA, 0xE6B9, 0xDE77, 0xDE77, 0xDED8, 0xE6D9, 0xEEF9, 0xDE77,   // 0x0FD0 (4048)
+0xD657, 0xDE99, 0xDE98, 0xE71A, 0xF79D, 0xFFBE, 0xFFFF, 0xF77D, 0xDEBA, 0xBD74, 0x8BCD, 0xBD95, 0xDEBA, 0xD658, 0xCDB5, 0xC574,   // 0x0FE0 (4064)
+0xCDB4, 0xC5B4, 0xBD32, 0xBD11, 0xBD32, 0xACB0, 0xACB0, 0xB532, 0xA490, 0xA46F, 0xACB1, 0xBD33, 0xBD53, 0xC553, 0xBD53, 0xBD73,   // 0x0FF0 (4080)
+0xC594, 0xBD12, 0xBCF1, 0xBD11, 0xBD11, 0xB48F, 0xB4D0, 0xC5B5, 0xD659, 0xDE9B, 0xEF1D, 0xEF3D, 0xE71C, 0xE6FC, 0xE71D, 0xDEFD,   // 0x1000 (4096)
+0xCE1A, 0xC5FA, 0xBD98, 0xB536, 0xC597, 0xCDD7, 0xCE19, 0xDE9C, 0xDEBC, 0xE71D, 0xDEBC, 0x9473, 0x41E6, 0x3123, 0x3144, 0x3144,   // 0x1010 (4112)
+0x2903, 0x28E3, 0x28E3, 0x2903, 0x1041, 0x1861, 0x1041, 0x1040, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041,   // 0x1020 (4128)
+0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1061, 0x1041, 0x1041, 0x1061, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041,   // 0x1030 (4144)
+0x1041, 0x1041, 0x1041, 0x1041, 0x1061, 0x1882, 0x20A2, 0x20A1, 0x6B0C, 0xCE39, 0xDE9B, 0xD69B, 0xCE3A, 0xCDF9, 0xB535, 0xB4F3,   // 0x1040 (4160)
+0xBD13, 0xC553, 0xCDB4, 0xCDB5, 0xCDB5, 0xBD33, 0xA490, 0xACF1, 0xBD54, 0xCDF6, 0xD679, 0xDE9A, 0xDE99, 0xDEBA, 0xCE18, 0xCDF7,   // 0x1050 (4176)
+0xD618, 0xD659, 0xEF1C, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF79E, 0xFFFF, 0xFFDF, 0xF79D, 0xE6B9, 0xD657, 0xD657, 0xE6B8, 0xE6F9,   // 0x1060 (4192)
+0xEEF9, 0xE6D9, 0xE6D8, 0xDE77, 0xD616, 0xE6D9, 0xE6FA, 0xF79D, 0xFFFE, 0xFFFF, 0xF7BE, 0xEF5D, 0xDEBA, 0xE6FB, 0xEF5D, 0xE6DA,   // 0x1070 (4208)
+0xDEDA, 0xE6FB, 0xD658, 0xD658, 0xD637, 0xCDD6, 0xCDD6, 0xCDB4, 0xC594, 0xC594, 0xBD53, 0xC574, 0xACD1, 0xB4D1, 0xBD12, 0xBD33,   // 0x1080 (4224)
+0xBD12, 0xBD53, 0xC573, 0xC594, 0xC573, 0xCD74, 0xC533, 0xBCF0, 0xB4AF, 0xBD11, 0xC553, 0xCDF7, 0xD659, 0xDE9A, 0xDE9B, 0xE6DC,   // 0x1090 (4240)
+0xE6FC, 0xDEBB, 0xBDB8, 0xAD16, 0xB535, 0xACF3, 0xBD34, 0xD5F8, 0xD639, 0xDE9B, 0xDEBC, 0xE71D, 0xDEBC, 0x9C93, 0x5A89, 0x39A5,   // 0x10A0 (4256)
+0x3164, 0x3144, 0x2923, 0x2903, 0x2903, 0x2903, 0x2923, 0x1040, 0x1061, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1040, 0x1040,   // 0x10B0 (4272)
+0x1041, 0x1041, 0x1061, 0x1041, 0x1061, 0x1041, 0x1040, 0x1041, 0x1041, 0x1041, 0x1041, 0x1061, 0x1041, 0x1040, 0x1040, 0x1041,   // 0x10C0 (4288)
+0x1041, 0x1041, 0x1061, 0x1041, 0x1041, 0x1041, 0x1041, 0x1061, 0x1881, 0x18A1, 0x18A1, 0x5248, 0xBDB7, 0xDEDC, 0xE6DC, 0xCE3A,   // 0x10D0 (4304)
+0xBDB7, 0xACF2, 0xAC8F, 0xBD12, 0xCD94, 0xCDF6, 0xCDF6, 0xC595, 0xB4F3, 0xA470, 0xACF2, 0xCDF6, 0xCE17, 0xCE18, 0xD659, 0xD638,   // 0x10E0 (4320)
+0xBD95, 0x730A, 0x41A5, 0x49E6, 0x5A68, 0x7B6D, 0xAD34, 0xEF3C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79D, 0xE6B9, 0xD616,   // 0x10F0 (4336)
+0xCE16, 0xEEF9, 0xE6B9, 0xEEF9, 0xDE98, 0xDEB8, 0xDE57, 0xCDD5, 0xE6D9, 0xEF1A, 0xF7BD, 0xFFDE, 0xFFFF, 0xFFFF, 0xFFBF, 0xFFDE,   // 0x1100 (4352)
+0xFFFF, 0xFFBF, 0xF79E, 0xE71C, 0xEF1C, 0xE6DB, 0xE6DB, 0xE6DB, 0xDEBA, 0xDE99, 0xDE99, 0xDEB9, 0xD678, 0xCDF6, 0xCDD6, 0xC595,   // 0x1110 (4368)
+0xC553, 0xBD33, 0xB4F1, 0xACD0, 0xB4F2, 0xC574, 0xCDD5, 0xCDD5, 0xC553, 0xB4D1, 0xA46E, 0xB4D0, 0xC552, 0xBD31, 0xACF1, 0xBD54,   // 0x1120 (4384)
+0xCE38, 0xDEBB, 0xE6DC, 0xDE9B, 0xC5F8, 0xBD56, 0xB514, 0xACD3, 0xC574, 0xD639, 0xD639, 0xDE5A, 0xDE9B, 0xE6DC, 0xE71D, 0xD6BC,   // 0x1130 (4400)
+0x8C31, 0x4207, 0x3124, 0x3144, 0x3144, 0x2923, 0x2903, 0x2903, 0x2903, 0x3144, 0x1040, 0x1041, 0x1061, 0x1061, 0x1041, 0x1041,   // 0x1140 (4416)
+0x1041, 0x1040, 0x0840, 0x1041, 0x1041, 0x1041, 0x0840, 0x0840, 0x1041, 0x1041, 0x1020, 0x1041, 0x1041, 0x1041, 0x1041, 0x0840,   // 0x1150 (4432)
+0x0840, 0x1020, 0x1041, 0x1041, 0x1041, 0x1061, 0x1041, 0x1041, 0x1041, 0x1861, 0x1881, 0x18A1, 0x20C2, 0x2903, 0x4A07, 0x9CB2,   // 0x1160 (4448)
+0xD67A, 0xE6DC, 0xC5F9, 0xA4B2, 0x9C4F, 0xACAF, 0xC532, 0xC553, 0xC553, 0xBD33, 0xBD12, 0xBD33, 0xACD1, 0xACF1, 0xC5B5, 0xCDF7,   // 0x1170 (4464)
+0xCE18, 0xC5B7, 0xAC90, 0x5A27, 0x1840, 0x1082, 0x2103, 0x2103, 0x2103, 0x2103, 0x4206, 0x9491, 0xF79D, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x1180 (4480)
+0xF7BE, 0xEF1B, 0xD5F5, 0xDE78, 0xE6FA, 0xE6FA, 0xE6FA, 0xE698, 0xEF1A, 0xDE57, 0xC594, 0xEF3A, 0xEF5B, 0xFFFE, 0xFFFF, 0xFFFF,   // 0x1190 (4496)
+0xFFFF, 0xFFFF, 0xFFFF, 0xE6FB, 0xB554, 0x8C0F, 0x62AA, 0x6AEA, 0x6B0B, 0x732B, 0x942F, 0xC5F6, 0xE6DA, 0xDEBA, 0xDE99, 0xD678,   // 0x11A0 (4512)
+0xCE17, 0xC5B5, 0xCDB5, 0xC574, 0xBD33, 0xBD32, 0xACB0, 0xBD53, 0xCDD6, 0xCDD6, 0xCD94, 0xBD32, 0xBD12, 0xBD32, 0xC553, 0xC552,   // 0x11B0 (4528)
+0xC531, 0xACB0, 0xACF3, 0xCDF6, 0xCE18, 0xDE7A, 0xDE9B, 0xCE39, 0xBD77, 0xBD55, 0xBD97, 0xD63A, 0xDE7B, 0xDE9B, 0xDE9B, 0xE6FD,   // 0x11C0 (4544)
+0xEF5E, 0xEF7F, 0xB5B7, 0x5AAA, 0x20E2, 0x2923, 0x2923, 0x2903, 0x2903, 0x2903, 0x3124, 0x3144, 0x3144, 0x1021, 0x1021, 0x1041,   // 0x11D0 (4560)
+0x1061, 0x1041, 0x1041, 0x1040, 0x1041, 0x1041, 0x1061, 0x1040, 0x1040, 0x0841, 0x0820, 0x1040, 0x1040, 0x1040, 0x1041, 0x1061,   // 0x11E0 (4576)
+0x1061, 0x1041, 0x0840, 0x0840, 0x1061, 0x1061, 0x1040, 0x1041, 0x1041, 0x1041, 0x1041, 0x1041, 0x1881, 0x18A1, 0x20A2, 0x2903,   // 0x11F0 (4592)
+0x3144, 0x39C5, 0x6B2B, 0xBD77, 0xCDF9, 0xA4D3, 0x8BAD, 0x9C0D, 0xAC6F, 0xB4AF, 0xB48F, 0xB4D0, 0xB4F1, 0xBD32, 0xC595, 0xBD54,   // 0x1200 (4608)
+0xB532, 0xC574, 0xC595, 0xCDD7, 0xB513, 0x93CD, 0x3944, 0x3A07, 0x5B0B, 0x52AA, 0x4228, 0x39E8, 0x52CB, 0x4A6A, 0x2944, 0x83CF,   // 0x1210 (4624)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF5C, 0xD616, 0xE6B9, 0xE6FA, 0xEF1A, 0xEF1A, 0xEF3B, 0xEEFA, 0xE698, 0xCDF6, 0xEF1B, 0xF7BD,   // 0x1220 (4640)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xC5F6, 0x5228, 0x2964, 0x3185, 0x31C7, 0x31A6, 0x2985, 0x2965, 0x18C2, 0x3123, 0x834B,   // 0x1230 (4656)
+0xCDF7, 0xE6FB, 0xDE9A, 0xDE99, 0xDE78, 0xD657, 0xCDF6, 0xC573, 0xBD32, 0xACD1, 0xB512, 0xC5B5, 0xCDB5, 0xC574, 0xCDB5, 0xCDD5,   // 0x1240 (4672)
+0xC594, 0xCD94, 0xCD94, 0xC552, 0xB4AF, 0xAC8F, 0xB512, 0xC5D6, 0xD659, 0xD638, 0xBD96, 0xBD76, 0xD63A, 0xD67B, 0xDEBC, 0xE71D,   // 0x1250 (4688)
+0xE73D, 0xE73D, 0xEF5E, 0xF79F, 0xDE9C, 0x732C, 0x39A6, 0x2103, 0x18C2, 0x20E2, 0x20E2, 0x2903, 0x3144, 0x3164, 0x3144, 0x3144,   // 0x1260 (4704)
+0x1021, 0x1021, 0x1041, 0x1061, 0x1061, 0x1041, 0x1041, 0x1061, 0x1041, 0x1061, 0x1061, 0x1041, 0x0841, 0x0841, 0x0840, 0x1040,   // 0x1270 (4720)
+0x1041, 0x1041, 0x1061, 0x1061, 0x1041, 0x1061, 0x1041, 0x1041, 0x1061, 0x1061, 0x1061, 0x1061, 0x1061, 0x1061, 0x1861, 0x1881,   // 0x1280 (4736)
+0x18A1, 0x20C2, 0x20C2, 0x20E3, 0x39A5, 0x5A89, 0x9451, 0x9C91, 0x838D, 0x93AC, 0xAC6F, 0xAC8F, 0xA44E, 0xAC4E, 0xB4B0, 0xBD12,   // 0x1290 (4752)
+0xC553, 0xCDB5, 0xC595, 0xBD75, 0xACB1, 0xB513, 0xBD54, 0xACF2, 0x836D, 0x5269, 0x7BEF, 0x4A89, 0x10C3, 0x0861, 0x0041, 0x1904,   // 0x12A0 (4768)
+0x5B0C, 0x6B8F, 0x31E8, 0xB5B6, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79D, 0xD616, 0xDE78, 0xE6FA, 0xE6DA, 0xE6FA, 0xEF1B, 0xDE78, 0xDE78,   // 0x12B0 (4784)
+0xE6B9, 0xEF3B, 0xFFDE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD679, 0x5289, 0x4A6A, 0x634E, 0x5AEB, 0x39E7, 0x31C7, 0x52CB, 0x73AE,   // 0x12C0 (4800)
+0x7410, 0x4249, 0x20C1, 0x7B0A, 0xC5B5, 0xE6DA, 0xE6FA, 0xDE99, 0xD617, 0xC573, 0xBD53, 0xC594, 0xC594, 0xC594, 0xCDD5, 0xD617,   // 0x12D0 (4816)
+0xCDF5, 0xCDB5, 0xCDD5, 0xCD94, 0xC552, 0xBD31, 0xBCD0, 0xAC6F, 0x93EC, 0x8B6B, 0xA490, 0xC595, 0xCDD7, 0xCDD7, 0xCDF8, 0xCE5A,   // 0x12E0 (4832)
+0xCE3A, 0xDE9B, 0xDEFC, 0xDEBB, 0xDEBB, 0xE71D, 0xE71D, 0xA4D3, 0x49E6, 0x2103, 0x1061, 0x1041, 0x1881, 0x28E3, 0x2923, 0x3144,   // 0x12F0 (4848)
+0x3144, 0x2923, 0x3144, 0x1020, 0x1061, 0x1041, 0x1041, 0x1061, 0x1061, 0x1061, 0x1061, 0x1061, 0x1061, 0x1081, 0x1861, 0x1061,   // 0x1300 (4864)
+0x1061, 0x0841, 0x1061, 0x1061, 0x1061, 0x1061, 0x1061, 0x1081, 0x1061, 0x1061, 0x1061, 0x1061, 0x1061, 0x1061, 0x1041, 0x1861,   // 0x1310 (4880)
+0x1882, 0x18A1, 0x20C2, 0x20E2, 0x20E2, 0x28E3, 0x2903, 0x2903, 0x41E6, 0x6B0B, 0x8BEF, 0x836C, 0x8B8C, 0x9BED, 0x9BCC, 0x938B,   // 0x1320 (4896)
+0x938B, 0x93CC, 0x93AC, 0x9BED, 0x940F, 0x8BEE, 0x8C0E, 0xA491, 0xBD74, 0xE6DB, 0xD65A, 0x7BAF, 0x6B6D, 0x528A, 0x10A2, 0x0021,   // 0x1330 (4912)
+0x0063, 0x0084, 0x0021, 0x29A6, 0x73D1, 0x5B6F, 0x7BAF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BD, 0xE6B9, 0xDE98, 0xE6D9, 0xE6D9, 0xE6D9,   // 0x1340 (4928)
+0xE6FA, 0xE6B9, 0xDE97, 0xE6FA, 0xF79D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF3C, 0x9C71, 0x6B8F, 0x73D0, 0x52AB, 0x10C3, 0x0862,   // 0x1350 (4944)
+0x0041, 0x10A3, 0x4228, 0x738E, 0x8472, 0x4A8A, 0x28E3, 0x836B, 0xBD54, 0xC5D5, 0xCDD5, 0xC573, 0xC553, 0xBD53, 0xCDD6, 0xD5F6,   // 0x1360 (4960)
+0xCDB5, 0xCDB5, 0xC594, 0xBD53, 0xBD32, 0xC553, 0xC532, 0xB4D0, 0xACAF, 0xB48F, 0xAC8F, 0x93CC, 0x832A, 0x834B, 0xACB1, 0xC5B6,   // 0x1370 (4976)
+0xC5B7, 0xC5B7, 0xC596, 0xC597, 0xDE7A, 0xDE9B, 0xCE19, 0xDE7A, 0xDE9C, 0xC5F8, 0x83CE, 0x41E6, 0x18A2, 0x1061, 0x0820, 0x1081,   // 0x1380 (4992)
+0x2103, 0x2923, 0x3144, 0x3144, 0x3144, 0x3985, 0x1040, 0x1061, 0x1061, 0x1061, 0x1861, 0x1861, 0x1861, 0x1881, 0x1861, 0x1061,   // 0x1390 (5008)
+0x1881, 0x1881, 0x1061, 0x1041, 0x1061, 0x1061, 0x1061, 0x1061, 0x1861, 0x1881, 0x1061, 0x1061, 0x1881, 0x1861, 0x1061, 0x1061,   // 0x13A0 (5024)
+0x1061, 0x1061, 0x1881, 0x20A2, 0x20C2, 0x20C2, 0x2903, 0x2903, 0x20E2, 0x2923, 0x3985, 0x5247, 0x732B, 0x7B6C, 0x8B8C, 0x93CD,   // 0x13B0 (5040)
+0x9BEC, 0xA42E, 0x938B, 0x6A87, 0x4184, 0x30E2, 0x3944, 0x3964, 0x49E5, 0x8BCD, 0xCE38, 0xEF5D, 0xF79F, 0xAD14, 0x5AEB, 0x634D,   // 0x13C0 (5056)
+0x3185, 0x0021, 0x0083, 0x00A5, 0x1168, 0x4AEE, 0x2A09, 0x636F, 0x6C34, 0x52EC, 0xE6FC, 0xFFFF, 0xFFFF, 0xF7BD, 0xE6DA, 0xDEB9,   // 0x13D0 (5072)
+0xE6DA, 0xEF1B, 0xE6DA, 0xE699, 0xDE99, 0xEF1A, 0xEF1A, 0xFFBE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xC5D7, 0x73D1, 0x73D1, 0x632D,   // 0x13E0 (5088)
+0x10C3, 0x0083, 0x08C4, 0x0063, 0x0083, 0x10C3, 0x52AA, 0x8451, 0x8473, 0x4209, 0x4A28, 0xA4B2, 0xB4F1, 0xACD0, 0xB4D2, 0xAC90,   // 0x13F0 (5104)
+0xB4F1, 0xC574, 0xCD94, 0xC594, 0xC5B4, 0xBD52, 0xBD52, 0xBD32, 0xBD52, 0xC532, 0xBD32, 0xBD32, 0xBD11, 0xAC6F, 0x9BED, 0x834A,   // 0x1400 (5120)
+0x6A87, 0x7B0A, 0xB4D2, 0xBD96, 0xC596, 0xC5B7, 0xD65A, 0xD65A, 0xD67A, 0xD65A, 0xD65A, 0xCE3A, 0xAD14, 0x83EF, 0x4A07, 0x18C2,   // 0x1410 (5136)
+0x1081, 0x18A2, 0x20A2, 0x28E3, 0x3164, 0x3985, 0x3144, 0x3164, 0x4A06, 0x1041, 0x1061, 0x1061, 0x1881, 0x1881, 0x1881, 0x1881,   // 0x1420 (5152)
+0x1882, 0x1881, 0x1882, 0x1882, 0x1881, 0x1881, 0x1861, 0x1881, 0x1882, 0x1861, 0x1061, 0x1881, 0x1882, 0x1882, 0x1881, 0x1882,   // 0x1430 (5168)
+0x1882, 0x1061, 0x1061, 0x1061, 0x1861, 0x18A2, 0x20C2, 0x20C2, 0x20E2, 0x20E2, 0x2903, 0x2923, 0x3144, 0x49E6, 0x734C, 0x9C4F,   // 0x1440 (5184)
+0x836C, 0x8BAC, 0x9BED, 0x93CC, 0x8B8B, 0x72A8, 0x28A2, 0x0820, 0x20A2, 0x41A5, 0x6288, 0x8BAD, 0xCE17, 0xEF3C, 0xFFFF, 0xEF1C,   // 0x1450 (5200)
+0x7B2B, 0x4A48, 0x5B0B, 0x2964, 0x0042, 0x00C5, 0x00E7, 0x19CB, 0xBE5B, 0x73F2, 0x6390, 0x7476, 0x3A2B, 0xB595, 0xFFFF, 0xFFFF,   // 0x1460 (5216)
+0xF7BD, 0xEEFA, 0xDED9, 0xE6FA, 0xE6FA, 0xE6FA, 0xEEFB, 0xE6B9, 0xDEB9, 0xEF5B, 0xFFDE, 0xFFFF, 0xFFFF, 0xFFDF, 0xDEBB, 0x736D,   // 0x1470 (5232)
+0x7454, 0x73F1, 0x4229, 0x0062, 0x00A4, 0x21E9, 0x7432, 0x1988, 0x0062, 0x3A28, 0x7C10, 0x8473, 0x5B0D, 0x4A28, 0xB514, 0xDEBA,   // 0x1480 (5248)
+0xBD74, 0x8BAC, 0x836B, 0x838C, 0x9C2E, 0xBD12, 0xC594, 0xCDB5, 0xC594, 0xCDB4, 0xCD94, 0xC573, 0xC553, 0xBD32, 0xC553, 0xBD12,   // 0x1490 (5264)
+0xBD11, 0xB4D0, 0xA44E, 0x93AC, 0x830A, 0x8BAC, 0xB4F2, 0xC596, 0xCDF8, 0xD659, 0xD67A, 0xD65A, 0xCE19, 0xCDF8, 0xBD77, 0xA4B4,   // 0x14A0 (5280)
+0x9C72, 0x5AA9, 0x18A2, 0x18A2, 0x20E3, 0x20A2, 0x3144, 0x3985, 0x3164, 0x3985, 0x41C6, 0x4A06, 0x1881, 0x1881, 0x1861, 0x1881,   // 0x14B0 (5296)
+0x18A1, 0x1882, 0x1882, 0x18A2, 0x1882, 0x1882, 0x1881, 0x18A1, 0x18A1, 0x18A1, 0x1882, 0x1882, 0x1882, 0x1881, 0x1882, 0x1882,   // 0x14C0 (5312)
+0x1882, 0x18A1, 0x18A2, 0x1882, 0x1882, 0x1881, 0x1081, 0x1861, 0x18A2, 0x20C2, 0x20C2, 0x2903, 0x20E2, 0x20E2, 0x3144, 0x3985,   // 0x14D0 (5328)
+0x39A5, 0x732B, 0x8BCD, 0x8BAD, 0x836B, 0x93AB, 0x8B6A, 0x6A87, 0x3123, 0x0820, 0x28E3, 0x72C9, 0x6AA9, 0x6AA9, 0x93ED, 0xD679,   // 0x14E0 (5344)
+0xF75D, 0xFFDF, 0xDE9A, 0x6AA9, 0x39C7, 0x5B0C, 0x3185, 0x0862, 0x00C5, 0x09AB, 0x0108, 0x1147, 0x4AAC, 0x6BB1, 0x84B8, 0x52AB,   // 0x14F0 (5360)
+0x83AD, 0xFFBF, 0xFFFF, 0xFFDE, 0xEF1B, 0xEF3B, 0xE6FA, 0xDEB9, 0xE6DA, 0xEF1B, 0xEF1B, 0xEEFA, 0xFFBD, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x1500 (5376)
+0xE6FB, 0x836C, 0x2903, 0x6370, 0x7C12, 0x39E7, 0x0083, 0x00A4, 0x3A8C, 0xD6FD, 0x42AD, 0x0083, 0x4229, 0x7C11, 0x8452, 0x634F,   // 0x1510 (5392)
+0x3985, 0xBD54, 0xF79E, 0xE6DA, 0xBD33, 0x940E, 0x6268, 0x4185, 0x5A48, 0x730A, 0x93CD, 0xAC90, 0xB4F2, 0xB4D1, 0xBCF1, 0xBD52,   // 0x1520 (5408)
+0xC573, 0xC533, 0xC573, 0xBD12, 0xB4B0, 0xAC90, 0xAC90, 0x93CD, 0x8B8C, 0xA470, 0xBD55, 0xCDF8, 0xCE18, 0xCDF8, 0xD639, 0xC5F8,   // 0x1530 (5424)
+0xB535, 0xA4D4, 0xA4B4, 0x7BAF, 0x3164, 0x20C2, 0x3965, 0x3985, 0x3144, 0x3965, 0x3985, 0x41C6, 0x41E6, 0x41A6, 0x41C5, 0x18A1,   // 0x1540 (5440)
+0x18A1, 0x1882, 0x1882, 0x18A2, 0x18A2, 0x18A2, 0x20A2, 0x20A2, 0x18A2, 0x1882, 0x1882, 0x20A2, 0x18A1, 0x18A1, 0x20A2, 0x18A2,   // 0x1550 (5456)
+0x1882, 0x1882, 0x18A2, 0x1881, 0x18A1, 0x20C2, 0x18A2, 0x18A1, 0x1882, 0x1882, 0x1882, 0x1882, 0x20C2, 0x20E2, 0x20C2, 0x20E2,   // 0x1560 (5472)
+0x3144, 0x3144, 0x41C6, 0x5A68, 0x732B, 0x732B, 0x836C, 0x93CD, 0x8BAC, 0x72E9, 0x49A5, 0x28E2, 0x5247, 0x7B2A, 0x93AC, 0x6AA8,   // 0x1570 (5488)
+0x5A06, 0x9C2F, 0xD679, 0xEF5C, 0xFFBE, 0xE6FB, 0x7B6C, 0x4A28, 0x5B2C, 0x4268, 0x1904, 0x00C5, 0x0928, 0x1106, 0x29A7, 0x530E,   // 0x1580 (5504)
+0x6C14, 0x530F, 0x8C31, 0x6289, 0xDE99, 0xFFFF, 0xFFBD, 0xEF5C, 0xEF1B, 0xE6FA, 0xE6FA, 0xDEB9, 0xEF1B, 0xF73B, 0xEF3B, 0xFFDE,   // 0x1590 (5520)
+0xFFFF, 0xFFFF, 0xEF3C, 0x93EF, 0x4184, 0x2945, 0x4A8B, 0x8474, 0x4A69, 0x0883, 0x08C5, 0x0906, 0x1189, 0x0906, 0x1925, 0x52AB,   // 0x15A0 (5536)
+0x73CF, 0x8473, 0x52CD, 0x41C6, 0xCDF7, 0xFFBE, 0xF7BE, 0xDE9A, 0xC594, 0xACB0, 0x8BAC, 0x5A68, 0x3985, 0x28E2, 0x49C6, 0x5A47,   // 0x15B0 (5552)
+0x6AA8, 0x93AC, 0x9C4F, 0xAC90, 0xBCF1, 0xC573, 0xB4B0, 0xA42E, 0x9C2E, 0xA42F, 0x93CD, 0x8B8C, 0x93ED, 0xB554, 0xC5D7, 0xBD76,   // 0x15C0 (5568)
+0xC597, 0xBD96, 0x9C91, 0x8C10, 0x7BAE, 0x5227, 0x2923, 0x2923, 0x39A5, 0x4A07, 0x41C6, 0x41C6, 0x4A07, 0x4A27, 0x4A07, 0x39A5,   // 0x15D0 (5584)
+0x3985, 0x39A5, 0x20C1, 0x20A2, 0x18A2, 0x18A2, 0x1882, 0x18A2, 0x20A2, 0x20A2, 0x18A1, 0x18A2, 0x1882, 0x18A2, 0x20C2, 0x20A2,   // 0x15E0 (5600)
+0x20A2, 0x20C2, 0x20A2, 0x18A2, 0x1882, 0x1881, 0x18A1, 0x18A1, 0x18A1, 0x18A1, 0x20C2, 0x18A2, 0x1881, 0x1882, 0x1861, 0x1881,   // 0x15F0 (5616)
+0x18A2, 0x20E2, 0x2903, 0x2903, 0x18A1, 0x3964, 0x62C9, 0x6AA9, 0x6268, 0x834B, 0x93ED, 0x8BCD, 0x5A27, 0x28A1, 0x3143, 0x838C,   // 0x1600 (5632)
+0x72E9, 0x7B0A, 0x72E9, 0x6268, 0x8BAC, 0xBD73, 0xDEDA, 0xF79E, 0xF79D, 0xB553, 0x49C5, 0x31C6, 0x52CB, 0x4A8A, 0x29A6, 0x2186,   // 0x1610 (5648)
+0x3A49, 0x4ACC, 0x5B2E, 0x530E, 0x39C7, 0x3986, 0x3965, 0x83AE, 0xE6BA, 0xEF1B, 0xEF1B, 0xE6FA, 0xE6DA, 0xD637, 0xE6B9, 0xEF1B,   // 0x1620 (5664)
+0xEF3B, 0xEEFB, 0xF77D, 0xFFFF, 0xEF5C, 0xB534, 0x6248, 0x4985, 0x4AAD, 0x31C7, 0x7412, 0x6B6F, 0x31C7, 0x1104, 0x10E5, 0x08C5,   // 0x1630 (5680)
+0x08C4, 0x31E7, 0x632D, 0x8473, 0x7412, 0x3166, 0x7B2B, 0xEF1B, 0xFFFF, 0xFFDE, 0xEF3C, 0xD637, 0xBCF1, 0x93ED, 0x93CC, 0x72C9,   // 0x1640 (5696)
+0x49C6, 0x20A2, 0x20C2, 0x3124, 0x3965, 0x49A5, 0x6AA8, 0x8B8C, 0x93AC, 0x9C2F, 0x9C4F, 0x9BED, 0x9BED, 0x93CD, 0x93AC, 0x93ED,   // 0x1650 (5712)
+0xB554, 0xC5D7, 0xB535, 0x9430, 0x730A, 0x6AC9, 0x62AA, 0x5269, 0x2903, 0x20E2, 0x41C6, 0x5248, 0x5248, 0x5248, 0x5A89, 0x5268,   // 0x1660 (5728)
+0x5268, 0x4A06, 0x39A5, 0x3164, 0x3965, 0x18A1, 0x20A2, 0x20A1, 0x18A2, 0x18A2, 0x20A1, 0x20C2, 0x20C2, 0x18A1, 0x18A1, 0x18A1,   // 0x1670 (5744)
+0x20A2, 0x20C2, 0x18A1, 0x20A2, 0x20C2, 0x18A1, 0x18A1, 0x1882, 0x18A2, 0x20C2, 0x20C2, 0x20A2, 0x18A1, 0x20A2, 0x20A1, 0x18A1,   // 0x1680 (5760)
+0x1882, 0x1861, 0x1881, 0x1882, 0x20C2, 0x28E3, 0x3124, 0x3944, 0x3123, 0x3965, 0x49A5, 0x5A26, 0x72C9, 0x72C9, 0x5A48, 0x4164,   // 0x1690 (5776)
+0x3123, 0x49E6, 0x51E6, 0x51E6, 0x6AA8, 0x5A46, 0x5A06, 0x832A, 0xA42E, 0xCE16, 0xEF3C, 0xF7BE, 0xF79E, 0xBD75, 0x5A88, 0x39C6,   // 0x16A0 (5792)
+0x4208, 0x52AA, 0x634D, 0x736D, 0x7BCE, 0x8C50, 0x9470, 0x730A, 0x4A06, 0x2903, 0x49C5, 0xA46F, 0xD637, 0xE6B9, 0xDEB9, 0xD638,   // 0x16B0 (5808)
+0xC574, 0xD617, 0xDEBA, 0xE6FA, 0xE6B9, 0xDE57, 0xC5D5, 0xA470, 0x5A68, 0x5207, 0x5A47, 0x41E7, 0x3166, 0x73AF, 0x7412, 0x52EC,   // 0x16C0 (5824)
+0x4249, 0x31E8, 0x3A09, 0x52CB, 0x636E, 0x7410, 0x7C52, 0x4229, 0x49A5, 0xB534, 0xF77D, 0xFFFE, 0xFFBE, 0xE6FB, 0xC5B6, 0xA450,   // 0x16D0 (5840)
+0x6AA9, 0x6AA8, 0x93ED, 0x93ED, 0x72EA, 0x5206, 0x28E3, 0x1861, 0x20A2, 0x3103, 0x4185, 0x51E6, 0x6267, 0x7B09, 0x93CD, 0x9BEE,   // 0x16E0 (5856)
+0x8B8C, 0x834B, 0x8B8C, 0xA4D2, 0xC5D7, 0xC5F9, 0x9C71, 0x734C, 0x5228, 0x3985, 0x2923, 0x2903, 0x3985, 0x4A27, 0x5268, 0x5268,   // 0x16F0 (5872)
+0x5A69, 0x5AA9, 0x5AA9, 0x5A89, 0x4A27, 0x3984, 0x3124, 0x3144, 0x20C2, 0x20A2, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x20C2,   // 0x1700 (5888)
+0x20A2, 0x18A1, 0x20C2, 0x20C2, 0x20A2, 0x18A1, 0x20A2, 0x20C2, 0x18A1, 0x18A1, 0x18C2, 0x18C2, 0x18A1, 0x20C2, 0x18A1, 0x20A2,   // 0x1710 (5904)
+0x20A2, 0x18A1, 0x18A2, 0x1882, 0x1861, 0x1882, 0x20C2, 0x28E3, 0x28E3, 0x2903, 0x39A5, 0x41C6, 0x3985, 0x4184, 0x5206, 0x5206,   // 0x1720 (5920)
+0x3944, 0x18A1, 0x1040, 0x49E6, 0x7B4C, 0x5227, 0x3123, 0x49E6, 0x5A47, 0x6246, 0x5A26, 0x7B09, 0x9C0D, 0xCDD6, 0xE6FC, 0xF7BE,   // 0x1730 (5936)
+0xFFFF, 0xFFBE, 0xD6BA, 0xCE38, 0xDEDB, 0xF77D, 0xFFBE, 0xFFDF, 0xFFBE, 0xE6FB, 0x940F, 0x41C6, 0x3124, 0x6268, 0x9C2E, 0xC553,   // 0x1740 (5952)
+0xC595, 0xCDD6, 0xCDD5, 0xCDB5, 0xCDD6, 0xD658, 0xDE78, 0xCDD6, 0xAC90, 0x6267, 0x3944, 0x3944, 0x41A6, 0x6A88, 0x6A88, 0x836B,   // 0x1750 (5968)
+0xA491, 0xAD56, 0x7BD0, 0x6B6E, 0x5AEC, 0x634D, 0x6B6E, 0x6B90, 0x6BD0, 0x3A07, 0x4A07, 0xACD2, 0xF75D, 0xFFDF, 0xF79E, 0xEF5C,   // 0x1760 (5984)
+0xDE99, 0xACB1, 0x72EB, 0x5A47, 0x72E9, 0x93CD, 0xA42E, 0xAC70, 0x8B8C, 0x6AA8, 0x3124, 0x1081, 0x1082, 0x20C3, 0x20E3, 0x3944,   // 0x1770 (6000)
+0x51E6, 0x6A88, 0x7B2A, 0x8B8C, 0x8BAD, 0x72C9, 0x83AD, 0xBD96, 0xCE19, 0xBD76, 0x8C30, 0x5227, 0x2903, 0x1882, 0x20A2, 0x2903,   // 0x1780 (6016)
+0x3985, 0x4A27, 0x5248, 0x5A89, 0x62EA, 0x62CA, 0x5A89, 0x4A07, 0x3984, 0x3124, 0x3144, 0x20E2, 0x20E2, 0x20C2, 0x20E2, 0x20E2,   // 0x1790 (6032)
+0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x18A1, 0x18A1, 0x20C2, 0x20C2, 0x20C2, 0x18C2, 0x20C2, 0x18A1,   // 0x17A0 (6048)
+0x18A2, 0x18A2, 0x20A1, 0x20C2, 0x18A1, 0x18A1, 0x20C2, 0x18A2, 0x18A2, 0x20A2, 0x20C2, 0x2923, 0x2903, 0x2903, 0x41A5, 0x4A06,   // 0x17B0 (6064)
+0x5A67, 0x6AE9, 0x5206, 0x20A2, 0x20C2, 0x39A5, 0x83AE, 0xAD14, 0x732B, 0x4185, 0x4164, 0x5226, 0x4164, 0x51C5, 0x5A27, 0x6A67,   // 0x17C0 (6080)
+0x8BAC, 0xA490, 0xCDF6, 0xEF3C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDE, 0xFFDE, 0xFFFF, 0xFFBE, 0xCE17, 0x5A68, 0x3124, 0x730A,   // 0x17D0 (6096)
+0x7B2A, 0x93ED, 0xACB0, 0xBD33, 0xCDF6, 0xC573, 0xBD53, 0xD5F6, 0xCDB5, 0xBD53, 0xB4F1, 0x93CD, 0x6247, 0x3123, 0x3144, 0x3944,   // 0x17E0 (6112)
+0x6247, 0xACD1, 0xEF3A, 0xF77C, 0xFF9E, 0xF79D, 0xDEFB, 0xC5F7, 0xB596, 0x8C72, 0x8C10, 0x8C0F, 0xACF2, 0xE6DB, 0xFFFF, 0xFFFF,   // 0x17F0 (6128)
+0xFFBE, 0xF77D, 0xDEB9, 0xACF2, 0x730B, 0x5A27, 0x6AA9, 0x8BAC, 0x93CD, 0x9BED, 0x9C2F, 0xACD1, 0xBD32, 0x8BED, 0x3985, 0x28E3,   // 0x1800 (6144)
+0x20C3, 0x18A2, 0x20C2, 0x3144, 0x5206, 0x7B0A, 0x836C, 0x836C, 0x6AC9, 0x730A, 0xACD3, 0xC5B7, 0xC5B7, 0xACF4, 0x6B0B, 0x1881,   // 0x1810 (6160)
+0x0800, 0x1061, 0x20C2, 0x3144, 0x41C6, 0x5A89, 0x6B0B, 0x734C, 0x6B2B, 0x6B2B, 0x5AA9, 0x3964, 0x28E3, 0x2923, 0x2903, 0x2903,   // 0x1820 (6176)
+0x20E2, 0x20E2, 0x28E3, 0x2903, 0x20E2, 0x20E2, 0x20E2, 0x20C2, 0x20E2, 0x20E2, 0x20C2, 0x20C2, 0x20C2, 0x20C2, 0x20E2, 0x20C2,   // 0x1830 (6192)
+0x20C2, 0x20C2, 0x20C2, 0x20A2, 0x18A2, 0x18A1, 0x20C2, 0x20C2, 0x20C2, 0x20E2, 0x2923, 0x2903, 0x20E2, 0x2903, 0x2903, 0x2903,   // 0x1840 (6208)
+0x2923, 0x3144, 0x4185, 0x5206, 0x6288, 0x49E5, 0x28C2, 0x20C2, 0x5A69, 0xA4B2, 0xC5D8, 0xA4B1, 0x7B4C, 0x51E6, 0x5206, 0x7B2B,   // 0x1850 (6224)
+0x834B, 0x7B09, 0x7AE9, 0x834B, 0x834A, 0x9BEE, 0xACD1, 0xC574, 0xCDD6, 0xCE17, 0xD657, 0xD636, 0xD616, 0xD617, 0xCDB6, 0x8BCE,   // 0x1860 (6240)
+0x41A5, 0x6AEA, 0x93EE, 0x6AEA, 0x93ED, 0xAC4F, 0xCD94, 0xCDB4, 0xAC4E, 0xAC90, 0xCDB5, 0xC573, 0xAC6F, 0xA44E, 0x8B8C, 0x6AC8,   // 0x1870 (6256)
+0x49C6, 0x3964, 0x3965, 0x6267, 0xB4F2, 0xF79D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x1880 (6272)
+0xFFFF, 0xF77D, 0xF75C, 0xE6B9, 0xC5B4, 0xA490, 0x6AC9, 0x5A28, 0x5A68, 0x730A, 0x8B8C, 0x8BCD, 0x730A, 0x72CA, 0x836C, 0x940E,   // 0x1890 (6288)
+0x9C6F, 0x9C50, 0x6AEA, 0x3144, 0x2945, 0x2924, 0x2903, 0x3985, 0x6AC9, 0x836B, 0x8B8C, 0x8BAC, 0x836B, 0x940F, 0xAD14, 0xB555,   // 0x18A0 (6304)
+0xACF5, 0x8C10, 0x41E7, 0x18A2, 0x1061, 0x20C2, 0x3144, 0x39A5, 0x5268, 0x62EA, 0x62EA, 0x6B0B, 0x6B0B, 0x5288, 0x41C6, 0x3164,   // 0x18B0 (6320)
+0x2943, 0x2903, 0x2923, 0x2903, 0x2903, 0x2903, 0x2923, 0x28E3, 0x28E3, 0x2903, 0x28E3, 0x20E2, 0x20E2, 0x20E2, 0x28E3, 0x20E2,   // 0x18C0 (6336)
+0x20E2, 0x28E3, 0x20E2, 0x20C2, 0x20C2, 0x20E2, 0x20E2, 0x20C2, 0x20C2, 0x20E2, 0x20E2, 0x20E2, 0x20E2, 0x2903, 0x3144, 0x3164,   // 0x18D0 (6352)
+0x3144, 0x3144, 0x2923, 0x28E3, 0x3124, 0x41A6, 0x5227, 0x5A27, 0x3924, 0x1061, 0x0000, 0x1882, 0x736C, 0xBD96, 0xC5D7, 0xACF3,   // 0x18E0 (6368)
+0x62A9, 0x5A47, 0x8C0E, 0xA4B1, 0xACB1, 0xA44F, 0xA44F, 0x8B8C, 0x7B0A, 0x8B8B, 0x93CC, 0xA44F, 0xB4F2, 0xBD33, 0xC553, 0xACB0,   // 0x18F0 (6384)
+0x93CE, 0x8BAD, 0x6AC9, 0x6AA8, 0xA491, 0xACF3, 0x9C4F, 0xA42E, 0xA44E, 0xBD31, 0xAC8F, 0x9BCC, 0xA42E, 0xB4F1, 0xB4D0, 0xAC6F,   // 0x1900 (6400)
+0xBD12, 0x836C, 0x6AC9, 0x5A47, 0x41A5, 0x41A5, 0x5A27, 0x9C0E, 0xC553, 0xE6D9, 0xF77C, 0xF7BD, 0xF7BD, 0xF77C, 0xF77C, 0xF77C,   // 0x1910 (6416)
+0xEF3B, 0xEEFA, 0xE699, 0xCDD6, 0xBD13, 0xB4F2, 0xBD12, 0xACB0, 0x7B2A, 0x6247, 0x6268, 0x83AC, 0x93ED, 0x832A, 0x5A48, 0x49C6,   // 0x1920 (6432)
+0x49C6, 0x4185, 0x49C6, 0x8BAC, 0xBD75, 0xB514, 0x6B0B, 0x4A07, 0x41E7, 0x41C7, 0x5228, 0x730B, 0x8BAC, 0x8B8C, 0x834B, 0x732A,   // 0x1930 (6448)
+0x8BCD, 0xA4B2, 0xA4D3, 0xA4F4, 0xA4B4, 0x7B8E, 0x41C7, 0x18C2, 0x18C2, 0x2103, 0x39C6, 0x4A48, 0x4207, 0x3985, 0x5228, 0x5AA9,   // 0x1940 (6464)
+0x5AC9, 0x5289, 0x39A5, 0x3144, 0x2903, 0x3123, 0x2923, 0x2923, 0x2923, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903,   // 0x1950 (6480)
+0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x28E3, 0x28E3, 0x2903, 0x20E2, 0x20E2, 0x20E2, 0x28E3, 0x2903,   // 0x1960 (6496)
+0x2923, 0x2923, 0x3144, 0x3164, 0x3985, 0x3985, 0x3985, 0x3965, 0x3124, 0x20C2, 0x1861, 0x0800, 0x0820, 0x18C2, 0x5249, 0x9C92,   // 0x1970 (6512)
+0xBD96, 0xB534, 0x9C50, 0x5207, 0x3965, 0x49E6, 0x6AEA, 0x732A, 0x732B, 0x834B, 0x8BAC, 0x838C, 0x8B8B, 0xB4D0, 0xBD53, 0xC553,   // 0x1980 (6528)
+0xC574, 0xAC90, 0x836C, 0x836C, 0x834C, 0x834B, 0xB512, 0xD658, 0xC5B5, 0xB4F1, 0x9C0E, 0xAC8F, 0xB4D0, 0xAC6F, 0xAC4E, 0xB4D0,   // 0x1990 (6544)
+0xBD11, 0xACAF, 0xB490, 0xC553, 0xB512, 0x93ED, 0x836C, 0x6247, 0x51C6, 0x51E6, 0x6A88, 0x8B4A, 0xBD11, 0xCDB4, 0xD637, 0xDE78,   // 0x19A0 (6560)
+0xDE77, 0xD5F5, 0xCDB4, 0xD5F5, 0xC552, 0xBD11, 0xB4D1, 0xAC90, 0xA44F, 0xACD1, 0xB4D2, 0xACB1, 0xA470, 0xACB1, 0xACF2, 0xA46F,   // 0x19B0 (6576)
+0x834B, 0x7B2B, 0x7B4B, 0x9C2F, 0x8BCD, 0x838C, 0xACD2, 0xCDF7, 0xD618, 0xACF3, 0x7B8D, 0x6AEB, 0x5248, 0x5248, 0x5227, 0x72C9,   // 0x19C0 (6592)
+0x8B4B, 0x8B8C, 0x7B4B, 0x7B2B, 0x8BAD, 0x93EE, 0x9C71, 0x9C91, 0x734C, 0x41E7, 0x3985, 0x3165, 0x3185, 0x41E6, 0x39A6, 0x2102,   // 0x19D0 (6608)
+0x2923, 0x4A27, 0x62CA, 0x62EA, 0x5268, 0x41E6, 0x39C6, 0x2903, 0x2923, 0x2923, 0x2923, 0x2923, 0x2903, 0x2923, 0x2923, 0x2903,   // 0x19E0 (6624)
+0x2923, 0x2923, 0x2923, 0x2923, 0x2903, 0x2923, 0x2923, 0x2903, 0x2923, 0x2923, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903,   // 0x19F0 (6640)
+0x28E3, 0x2903, 0x3124, 0x2923, 0x3144, 0x3124, 0x2923, 0x3144, 0x3984, 0x3985, 0x3965, 0x3164, 0x20C3, 0x1881, 0x18C2, 0x39A6,   // 0x1A00 (6656)
+0x5268, 0x9451, 0xB576, 0x9C4F, 0x6268, 0x5206, 0x49C5, 0x2903, 0x2081, 0x1861, 0x41C6, 0x6288, 0x6AC9, 0x72EA, 0x940E, 0xBD33,   // 0x1A10 (6672)
+0xCE37, 0xD658, 0xC594, 0x8BED, 0x62A9, 0x5A68, 0x6ACA, 0x93ED, 0xBD53, 0xE698, 0xDE99, 0xBD33, 0x9BED, 0xA42E, 0x9C4F, 0x9C2F,   // 0x1A20 (6688)
+0xA42F, 0x9C2E, 0xA46F, 0xACB0, 0xAC4F, 0x9C0E, 0xACB0, 0xC553, 0xCDD5, 0xD5F6, 0xACB0, 0x832A, 0x7AC8, 0x72C9, 0x834A, 0x93AC,   // 0x1A30 (6704)
+0xAC6F, 0xBD11, 0xBCF1, 0xBD33, 0xD616, 0xD637, 0xCD94, 0xC573, 0xC594, 0xC594, 0xC553, 0xACB0, 0x93CC, 0x8B8C, 0xACB1, 0xBD33,   // 0x1A40 (6720)
+0xB533, 0xA490, 0x8BAD, 0x8BAD, 0x9C2F, 0xB512, 0xCE17, 0xDE9A, 0xDE9A, 0xDE9A, 0xDE9A, 0xDEBB, 0xD639, 0x9CB2, 0x62EB, 0x39A5,   // 0x1A50 (6736)
+0x39A6, 0x4A27, 0x5227, 0x6288, 0x72EA, 0x834B, 0x836C, 0x836C, 0x93CD, 0x940F, 0x9471, 0x8C0F, 0x62EA, 0x4A07, 0x4A08, 0x4A48,   // 0x1A60 (6752)
+0x39A6, 0x3165, 0x3185, 0x4207, 0x4A27, 0x4A27, 0x41E6, 0x39A5, 0x3185, 0x3164, 0x2903, 0x2923, 0x2903, 0x2923, 0x2923, 0x2923,   // 0x1A70 (6768)
+0x2923, 0x2903, 0x2903, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2903, 0x2903,   // 0x1A80 (6784)
+0x2923, 0x2903, 0x2923, 0x2903, 0x2903, 0x2903, 0x2923, 0x3144, 0x2923, 0x3144, 0x3985, 0x39A5, 0x41E6, 0x5248, 0x5A89, 0x41E7,   // 0x1A90 (6800)
+0x41C7, 0x39C6, 0x41E7, 0x6B0C, 0xAD15, 0xC5B7, 0x942F, 0x5206, 0x49C5, 0x62A9, 0x5AA9, 0x6B0B, 0x736C, 0x942F, 0x83AD, 0x7B4C,   // 0x1AA0 (6816)
+0x940F, 0xBD75, 0xDE79, 0xEEFB, 0xEF1B, 0xB534, 0x49C6, 0x2903, 0x3944, 0x62A9, 0xB4F2, 0xEF3B, 0xEF1A, 0xE6B9, 0xB4D1, 0x7AEA,   // 0x1AB0 (6832)
+0x734B, 0x736C, 0x7B8D, 0x83AD, 0x8BCE, 0x83AD, 0x8BCE, 0x93EF, 0x834B, 0x8B8C, 0xBD32, 0xDE57, 0xF79B, 0xF79B, 0xCDB4, 0xB4CF,   // 0x1AC0 (6848)
+0x832A, 0x51E6, 0x51E6, 0x834B, 0xB4B0, 0xC533, 0xC574, 0xB4D2, 0xBD74, 0xCDD6, 0xB4F2, 0xA470, 0xA42E, 0x93CD, 0x8BCD, 0x8BAC,   // 0x1AD0 (6864)
+0x7B6B, 0x730A, 0x62A9, 0x5A68, 0x5207, 0x49C5, 0x6AC9, 0x7B4B, 0x9C4F, 0xD618, 0xDE9A, 0xDEBB, 0xE6FC, 0xEF1C, 0xE71C, 0xDEDB,   // 0x1AE0 (6880)
+0xCDF8, 0x8BF0, 0x41E7, 0x2103, 0x20E3, 0x3124, 0x2903, 0x3123, 0x5227, 0x6AA9, 0x6288, 0x836C, 0x9430, 0x9C51, 0x83CF, 0x62EA,   // 0x1AF0 (6896)
+0x4A28, 0x4A28, 0x4207, 0x39E7, 0x4A68, 0x5289, 0x4227, 0x31A5, 0x2923, 0x2123, 0x2923, 0x2924, 0x3123, 0x2903, 0x2923, 0x2903,   // 0x1B00 (6912)
+0x2903, 0x2903, 0x2903, 0x2903, 0x2923, 0x2923, 0x2923, 0x2923, 0x2903, 0x2903, 0x2923, 0x2923, 0x2903, 0x2923, 0x2903, 0x2923,   // 0x1B10 (6928)
+0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2903, 0x2903, 0x2903, 0x20E2, 0x2903, 0x3144, 0x3965, 0x3164, 0x3164, 0x41C6, 0x5268,   // 0x1B20 (6944)
+0x5A89, 0x5268, 0x3985, 0x2904, 0x62CA, 0x9492, 0xBDB8, 0xC5D8, 0xC5B7, 0xB535, 0x9430, 0x6B0B, 0x5227, 0x6AC9, 0x8B8C, 0x7B4B,   // 0x1B30 (6960)
+0x6288, 0x6247, 0x8BAC, 0xACB1, 0xCDF6, 0xDE79, 0xE6BA, 0xDE79, 0xCE18, 0xB575, 0x9C71, 0x83AE, 0x8BCE, 0xCDB5, 0xEF5B, 0xFFBD,   // 0x1B40 (6976)
+0xEF3B, 0x8BAD, 0x62A9, 0x5249, 0x5249, 0x5A8A, 0x6AEB, 0x7B8E, 0x5A8A, 0x41C6, 0x5248, 0x5A68, 0x6268, 0xACB0, 0xEEF9, 0xF79B,   // 0x1B50 (6992)
+0xFF9C, 0xFF9C, 0xDE36, 0x6AA8, 0x28E2, 0x20C2, 0x3123, 0x72EA, 0xC574, 0xDE78, 0xCDF5, 0xB4D1, 0xB512, 0xCDB5, 0xBD34, 0xB4F2,   // 0x1B60 (7008)
+0xB4F2, 0xA491, 0xA4B1, 0x9430, 0x8C10, 0x8BCF, 0x6AEB, 0x5A48, 0x5206, 0x5A47, 0x8BED, 0x9C4F, 0xB554, 0xBD75, 0xBD75, 0xCDF7,   // 0x1B70 (7024)
+0xDE9A, 0xE6FB, 0xE71C, 0xE6DC, 0xC5D8, 0x8BF0, 0x630C, 0x4A49, 0x41E7, 0x39A6, 0x2924, 0x20C3, 0x3944, 0x51E6, 0x6AA9, 0x7B6C,   // 0x1B80 (7040)
+0x8BCE, 0x93EF, 0x6B2B, 0x62EA, 0x630B, 0x6B2D, 0x6B4D, 0x6B6D, 0x52CA, 0x31A6, 0x18E3, 0x18C2, 0x2103, 0x2924, 0x3144, 0x3164,   // 0x1B90 (7056)
+0x2903, 0x3123, 0x2923, 0x2923, 0x2903, 0x2903, 0x2903, 0x2923, 0x2923, 0x2903, 0x2923, 0x2923, 0x2923, 0x2923, 0x2903, 0x2903,   // 0x1BA0 (7072)
+0x2923, 0x2923, 0x2923, 0x2903, 0x2903, 0x2923, 0x2923, 0x2923, 0x2903, 0x20E2, 0x2903, 0x2903, 0x20E2, 0x28E3, 0x3164, 0x41C6,   // 0x1BB0 (7088)
+0x4A27, 0x5288, 0x4A27, 0x5248, 0x62C9, 0x5A89, 0x41E6, 0x62C9, 0x8C30, 0x9C93, 0xA4B3, 0xACF4, 0xB556, 0xAD35, 0x944F, 0x6AEA,   // 0x1BC0 (7104)
+0x6A88, 0x836B, 0x7B2A, 0x5A47, 0x6A68, 0x940E, 0xBD95, 0xD679, 0xE6FB, 0xE6FB, 0xD659, 0xE6FC, 0xF75D, 0xF75C, 0xF77D, 0xE6FB,   // 0x1BD0 (7120)
+0xDE78, 0xE6FA, 0xFFFE, 0xF77C, 0x8B8D, 0x3965, 0x41C7, 0x5A8A, 0x5A89, 0x62AA, 0x6B2C, 0x5248, 0x5248, 0x5268, 0x5268, 0x5A69,   // 0x1BE0 (7136)
+0x834B, 0xEEFA, 0xFFBD, 0xF77C, 0xEF3A, 0xD5F5, 0x7B4A, 0x62CA, 0x6AEA, 0x5247, 0x5A27, 0x9C2F, 0xCE17, 0xE6FA, 0xDEB9, 0xD616,   // 0x1BF0 (7152)
+0xC574, 0xC575, 0xC575, 0xBD54, 0xACF2, 0xBD34, 0xBD95, 0xB535, 0xBD54, 0xAD13, 0x940E, 0x7B6B, 0x7B2B, 0x7B4B, 0x8BCD, 0x8C0F,   // 0x1C00 (7168)
+0x8BCD, 0x83AD, 0xA491, 0xC5B6, 0xDEDB, 0xE71C, 0xEF1C, 0xD67A, 0xA4F3, 0x6AEA, 0x49E7, 0x41C7, 0x39A6, 0x4A08, 0x41E7, 0x3165,   // 0x1C10 (7184)
+0x3965, 0x5227, 0x730A, 0x7B4B, 0x72EA, 0x62AA, 0x5ACA, 0x630B, 0x738E, 0x7BAE, 0x62EB, 0x3A07, 0x18C2, 0x0840, 0x1081, 0x20E3,   // 0x1C20 (7200)
+0x3144, 0x39A5, 0x41A5, 0x2903, 0x3123, 0x2923, 0x2923, 0x2923, 0x2923, 0x3124, 0x2923, 0x2903, 0x2923, 0x2923, 0x2923, 0x2923,   // 0x1C30 (7216)
+0x2903, 0x2903, 0x2923, 0x2923, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2923, 0x2923, 0x2903, 0x20E2, 0x20E2, 0x2903, 0x2903,   // 0x1C40 (7232)
+0x20E2, 0x2923, 0x41C6, 0x5228, 0x5A69, 0x5A68, 0x5A89, 0x62CA, 0x5268, 0x49E6, 0x62A8, 0x8BF0, 0xA4B4, 0xA4B2, 0x9450, 0x8BEF,   // 0x1C50 (7248)
+0x9430, 0x9CB1, 0x9450, 0x7B8C, 0x6ACA, 0x7B8D, 0x942F, 0xA4D2, 0xBD95, 0xCE18, 0xD699, 0xE6FB, 0xE71C, 0xE71C, 0xE71C, 0xE71C,   // 0x1C60 (7264)
+0xF77D, 0xFFDE, 0xFFFE, 0xF79C, 0xF79D, 0xFFFF, 0xFFDF, 0xDE9A, 0x5A49, 0x1840, 0x49C6, 0x6AAA, 0x5A48, 0x62AA, 0x5A89, 0x51E7,   // 0x1C70 (7280)
+0x4965, 0x4165, 0x62A9, 0xC5D6, 0xF79D, 0xFFDE, 0xF77C, 0xCD94, 0xD616, 0xDE58, 0xDE79, 0xCE18, 0xC5B7, 0xB514, 0xA471, 0xCDD6,   // 0x1C80 (7296)
+0xE6B9, 0xE6FB, 0xEEFB, 0xDE99, 0xC574, 0xBD13, 0xB513, 0x9C50, 0x838D, 0x838D, 0x7B6C, 0x838D, 0x944F, 0x838C, 0x7B2B, 0x7B4B,   // 0x1C90 (7312)
+0x62A8, 0x5227, 0x5207, 0x5A47, 0x62A8, 0x93EE, 0xC595, 0xDEDB, 0xE71C, 0xE6FB, 0xDEDB, 0xDE9C, 0xB556, 0x732B, 0x41C6, 0x3164,   // 0x1CA0 (7328)
+0x3165, 0x3965, 0x41E7, 0x41C6, 0x5228, 0x732C, 0x7B6C, 0x6B0A, 0x5A89, 0x5269, 0x62EB, 0x736E, 0x630B, 0x39C6, 0x2123, 0x10C2,   // 0x1CB0 (7344)
+0x10A1, 0x10A1, 0x2944, 0x41E6, 0x4207, 0x5268, 0x2903, 0x3123, 0x2923, 0x2923, 0x2923, 0x2923, 0x3124, 0x3124, 0x2923, 0x2903,   // 0x1CC0 (7360)
+0x2923, 0x2923, 0x2903, 0x2923, 0x2923, 0x2903, 0x2923, 0x2923, 0x2903, 0x2923, 0x2903, 0x2903, 0x2903, 0x2923, 0x2903, 0x28E3,   // 0x1CD0 (7376)
+0x20E2, 0x28E3, 0x2923, 0x3124, 0x3144, 0x2923, 0x3985, 0x4A27, 0x5268, 0x5268, 0x5A89, 0x5AA9, 0x5249, 0x734E, 0xA4F5, 0xBD77,   // 0x1CE0 (7392)
+0xA4B2, 0x6B0A, 0x49E6, 0x732B, 0x9CB2, 0xA4D3, 0x9C92, 0x8BEF, 0x83CE, 0x9430, 0xA4B1, 0xACD3, 0xC5D7, 0xCE38, 0xD658, 0xE6FC,   // 0x1CF0 (7408)
+0xEF3C, 0xE6FC, 0xE6FB, 0xDEBA, 0xEF5C, 0xFFDE, 0xFFFE, 0xFFDE, 0xFFFF, 0xFFFF, 0xFFDF, 0xBD55, 0x4964, 0x3904, 0x730B, 0x4A07,   // 0x1D00 (7424)
+0x49E7, 0x41A5, 0x6208, 0x72AB, 0x6A68, 0xCDF7, 0xF7BF, 0xFFFF, 0xFFFF, 0xFFDD, 0xEF5B, 0xF75C, 0xFFBE, 0xF79D, 0xE71C, 0xEF5D,   // 0x1D10 (7440)
+0xEF5D, 0xD658, 0xCDD6, 0xDE9A, 0xEF1C, 0xEF1C, 0xEF3C, 0xDE99, 0xBD74, 0xAD13, 0xACD2, 0x838D, 0x72EA, 0x6ACA, 0x5227, 0x5207,   // 0x1D20 (7456)
+0x49C6, 0x5A27, 0x6AC9, 0x7B2A, 0x7B4B, 0x838D, 0x8BCE, 0xA491, 0xBD55, 0xCDF7, 0xD659, 0xDE9A, 0xE6FB, 0xE6FC, 0xE6FD, 0xE6FC,   // 0x1D30 (7472)
+0xD639, 0xA4D2, 0x7B4C, 0x5A68, 0x3984, 0x41A5, 0x5207, 0x7B6C, 0x940F, 0x83AE, 0x62CB, 0x4A27, 0x4A27, 0x62CA, 0x62EB, 0x5269,   // 0x1D40 (7488)
+0x4A28, 0x39E6, 0x3185, 0x2924, 0x20E3, 0x3165, 0x4207, 0x4A48, 0x62EA, 0x2903, 0x3123, 0x2923, 0x2923, 0x2923, 0x2903, 0x2903,   // 0x1D50 (7504)
+0x2923, 0x2923, 0x2903, 0x2923, 0x2923, 0x2903, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x3124, 0x2923, 0x2923, 0x2923,   // 0x1D60 (7520)
+0x2923, 0x3144, 0x2923, 0x2903, 0x2923, 0x3144, 0x3144, 0x3144, 0x3964, 0x41E6, 0x5268, 0x5AEB, 0x6B6D, 0x738E, 0x7BAF, 0x8C12,   // 0x1D70 (7536)
+0x9CB5, 0x9C93, 0x7B8D, 0x49E6, 0x41C6, 0x62EB, 0x7BD0, 0x7BAF, 0x83EE, 0x9430, 0x83CE, 0x83AD, 0x7B8C, 0x83AC, 0xB513, 0xCE17,   // 0x1D80 (7552)
+0xD679, 0xDE79, 0xDE7A, 0xE6FB, 0xEF5D, 0xEF5D, 0xEF5C, 0xEF5C, 0xF79D, 0xFFBE, 0xFFDE, 0xFFFF, 0xFFDF, 0xF77E, 0xDE7A, 0x7B2B,   // 0x1D90 (7568)
+0x5A27, 0x5A69, 0x41A5, 0x49E7, 0x49E6, 0x72CA, 0x836D, 0xCDF7, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFBD, 0xEF3B,   // 0x1DA0 (7584)
+0xD638, 0xD638, 0xEF3C, 0xE6FB, 0xE71C, 0xE6FB, 0xE6DB, 0xE6DB, 0xF73C, 0xF75C, 0xEF1B, 0xDE99, 0xC5B5, 0xC5B6, 0xD659, 0xC5B6,   // 0x1DB0 (7600)
+0xA4D2, 0x940F, 0x6288, 0x5A48, 0x730A, 0xA46F, 0xBD54, 0xC5B6, 0xC5B7, 0xB535, 0xB535, 0xA491, 0x9430, 0xA4D2, 0xC5F8, 0xD67A,   // 0x1DC0 (7616)
+0xD69A, 0xDEBB, 0xDEBB, 0xDE9B, 0xD639, 0xBD76, 0xA4B2, 0x838D, 0x62CA, 0x6AC9, 0x8BEE, 0xA493, 0x9C51, 0x7B8E, 0x6B0B, 0x5A89,   // 0x1DD0 (7632)
+0x5AAA, 0x630B, 0x6B4D, 0x6B2C, 0x5ACA, 0x5289, 0x39A6, 0x18C2, 0x20E3, 0x2944, 0x39C6, 0x4A27, 0x2903, 0x3123, 0x2903, 0x2903,   // 0x1DE0 (7648)
+0x2903, 0x2903, 0x2903, 0x2923, 0x2923, 0x2903, 0x2923, 0x2923, 0x2903, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923,   // 0x1DF0 (7664)
+0x2923, 0x2903, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x3144, 0x3144, 0x3164, 0x3164, 0x3965, 0x41E6, 0x5268, 0x5ACA, 0x736D,   // 0x1E00 (7680)
+0x7BAF, 0x7B8E, 0x736D, 0x6AEB, 0x4A06, 0x41A5, 0x5A6A, 0x62EC, 0x5269, 0x39C6, 0x4A27, 0x7B8D, 0x9471, 0x9CB2, 0x8C0E, 0x7B6B,   // 0x1E10 (7696)
+0xA4B2, 0xBD96, 0xC5D7, 0xD659, 0xCE17, 0xC5D6, 0xD67A, 0xE6FC, 0xEF3C, 0xF77D, 0xFFBE, 0xFFBE, 0xFFDE, 0xFFBE, 0xF7BE, 0xF7BE,   // 0x1E20 (7712)
+0xF77D, 0xE6FC, 0xAD13, 0x5A68, 0x49E7, 0x3964, 0x3124, 0x49C6, 0x5A48, 0xBD55, 0xEF3D, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x1E30 (7728)
+0xFFFF, 0xF75C, 0xE6B9, 0xCE17, 0xDE99, 0xEF3C, 0xE6FB, 0xEF3C, 0xEF3D, 0xEF3C, 0xDEBA, 0xDE9A, 0xEEFB, 0xEF1B, 0xE6DA, 0xD658,   // 0x1E40 (7744)
+0xC5F7, 0xDE9A, 0xE6FC, 0xDE9A, 0xBD75, 0x9C70, 0x8BCE, 0xA4B2, 0xC5D7, 0xD679, 0xD659, 0xBD97, 0x9C93, 0x8BD0, 0x7B6D, 0x6AEB,   // 0x1E50 (7760)
+0x732B, 0xA470, 0xBDB6, 0xD679, 0xDEDB, 0xDEDB, 0xDEBB, 0xD65A, 0xCE1A, 0xBD97, 0xB577, 0x9CB2, 0x838D, 0x732C, 0x7B4C, 0x6AEA,   // 0x1E60 (7776)
+0x732B, 0x6AEB, 0x62EC, 0x736E, 0x83F0, 0x83F0, 0x7BAE, 0x736D, 0x5ACA, 0x39E7, 0x2965, 0x3165, 0x41E6, 0x4226, 0x41E6, 0x2903,   // 0x1E70 (7792)
+0x2923, 0x28E3, 0x2903, 0x2903, 0x28E3, 0x2903, 0x2923, 0x2923, 0x2903, 0x2903, 0x2923, 0x2903, 0x2903, 0x2923, 0x2923, 0x2923,   // 0x1E80 (7808)
+0x2923, 0x2903, 0x2903, 0x2923, 0x2903, 0x2903, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x3144, 0x3985, 0x3965, 0x3164,   // 0x1E90 (7824)
+0x39C6, 0x4A07, 0x5AA9, 0x630C, 0x6B4D, 0x62EA, 0x49E6, 0x5A6A, 0x62EC, 0x5AAA, 0x3164, 0x2924, 0x3986, 0x5249, 0x5249, 0x5AA9,   // 0x1EA0 (7840)
+0x83AD, 0x8C0F, 0xACF4, 0xAD35, 0xA4F3, 0xAD14, 0xBD75, 0xB575, 0xBD96, 0xDEBB, 0xDEBA, 0xE6FB, 0xEF5D, 0xFF9E, 0xFFBE, 0xFFBE,   // 0x1EB0 (7856)
+0xF79E, 0xF77D, 0xF77D, 0xEF7D, 0xE71C, 0xEF5D, 0xBDB6, 0x8B8D, 0x4145, 0x30E3, 0x7B4C, 0xB534, 0xE6DB, 0xF77E, 0xFFBE, 0xFFDF,   // 0x1EC0 (7872)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFBE, 0xEF5C, 0xF75D, 0xEF5D, 0xF77D, 0xEF5D, 0xE71C, 0xE6FC, 0xE6FB, 0xE6DB, 0xE6BA, 0xD659,   // 0x1ED0 (7888)
+0xD679, 0xE6DA, 0xDE99, 0xC5D6, 0xBD75, 0xBD96, 0xC5B6, 0xCE18, 0xC5D7, 0xBDB6, 0xC5F7, 0xD67A, 0xD67A, 0xBDB6, 0x8C0F, 0x62EA,   // 0x1EE0 (7904)
+0x41E6, 0x39A5, 0x3165, 0x4185, 0x5A27, 0x8BAD, 0xB534, 0xD659, 0xDEDB, 0xDEBB, 0xCE19, 0xBD97, 0xACF4, 0x83AF, 0x83CF, 0x8C10,   // 0x1EF0 (7920)
+0x8C11, 0x7B8E, 0x6B0C, 0x5A8A, 0x4A07, 0x41E7, 0x62EB, 0x7BCF, 0x8410, 0x8C30, 0x8410, 0x736D, 0x630B, 0x62EB, 0x5AAA, 0x5289,   // 0x1F00 (7936)
+0x41E6, 0x39A5, 0x2903, 0x2903, 0x20E3, 0x2103, 0x2103, 0x2103, 0x2903, 0x2903, 0x2923, 0x2903, 0x2903, 0x2903, 0x2923, 0x2903,   // 0x1F10 (7952)
+0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2923, 0x2923, 0x2903, 0x2903, 0x2923, 0x2923, 0x2923, 0x2903, 0x2903, 0x3124, 0x3144,   // 0x1F20 (7968)
+0x3164, 0x41A6, 0x41C6, 0x4A07, 0x5289, 0x62EB, 0x736D, 0x6B4D, 0x6B2B, 0x6B6E, 0x62CB, 0x3124, 0x1881, 0x20C2, 0x28E3, 0x3145,   // 0x1F30 (7984)
+0x41A6, 0x2923, 0x734D, 0xA4D4, 0x9472, 0x8BF0, 0x7BAD, 0x9C70, 0xB556, 0xAD14, 0xB534, 0xB575, 0xD639, 0xE6DC, 0xEF5D, 0xEF3D,   // 0x1F40 (8000)
+0xF77E, 0xF77D, 0xF75D, 0xEF3C, 0xEF1C, 0xDEBB, 0xDE9A, 0xD639, 0xD639, 0xCDD7, 0xB4F3, 0x5A28, 0x4185, 0xC595, 0xD639, 0xD639,   // 0x1F50 (8016)
+0xDE9A, 0xEF3C, 0xF79D, 0xFFBE, 0xFFDF, 0xFFFF, 0xFFFF, 0xF7BE, 0xF79D, 0xEF5C, 0xEF3C, 0xDEDA, 0xE6FB, 0xEF3C, 0xE6DB, 0xDEDB,   // 0x1F60 (8032)
+0xE6FC, 0xE6DC, 0xDEBA, 0xCE38, 0xCDF7, 0xCE38, 0xC5B6, 0xA470, 0x8BEF, 0xA4B3, 0xBD75, 0xC5D7, 0xCE38, 0xCE19, 0xCE19, 0xCE18,   // 0x1F70 (8048)
+0xBD75, 0x83AE, 0x6B0B, 0x5A69, 0x4A07, 0x41A6, 0x3164, 0x41E6, 0x6269, 0x732B, 0x9C50, 0xC596, 0xC5D7, 0xC5B7, 0xACF4, 0x9451,   // 0x1F80 (8064)
+0x83AF, 0x7BAE, 0x8BF0, 0x7B8D, 0x6B0C, 0x6B2C, 0x62CB, 0x62CA, 0x7BAF, 0x83CF, 0x83EF, 0x9493, 0x9C94, 0x9473, 0x8C12, 0x7BAF,   // 0x1F90 (8080)
+0x736D, 0x6B4C, 0x62EA, 0x5288, 0x5268, 0x2103, 0x2102, 0x18C2, 0x20E2, 0x2103, 0x2123, 0x2903, 0x28E3, 0x2903, 0x2903, 0x28E3,   // 0x1FA0 (8096)
+0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x2903, 0x28E3, 0x2903, 0x2903, 0x2923, 0x2923, 0x2903, 0x20E2, 0x2903, 0x2903, 0x28E3,   // 0x1FB0 (8112)
+0x2903, 0x3124, 0x3144, 0x3965, 0x41E6, 0x5289, 0x5ACB, 0x5ACA, 0x5269, 0x5289, 0x52AA, 0x5ACB, 0x39C6, 0x3103, 0x28E3, 0x20E3,   // 0x1FC0 (8128)
+0x20E3, 0x1882, 0x3124, 0x3965, 0x7BAF, 0x8C31, 0x7B6C, 0x838C, 0x7B6C, 0x7BAE, 0x9C51, 0x9430, 0xAD14, 0xBD97, 0xB556, 0xAD14,   // 0x1FD0 (8144)
+0xD65A, 0xDEDC, 0xEF3C, 0xEF5C, 0xEF5C, 0xF75D, 0xE6FC, 0xE71C, 0xD67A, 0xCDF8, 0xCDF8, 0xCDF8, 0xCDB7, 0xBD35, 0x6289, 0x3964,   // 0x1FE0 (8160)
+0xA4B2, 0xCDD7, 0xCDF7, 0xCE18, 0xDEBB, 0xEF1C, 0xEF1C, 0xF77D, 0xF79D, 0xF7BE, 0xF79D, 0xF77D, 0xDEDA, 0xEF3C, 0xEF3C, 0xEF3D,   // 0x1FF0 (8176)
+0xF77D, 0xE71C, 0xD659, 0xC596, 0xCDD6, 0xD638, 0xDE79, 0xD659, 0xCE18, 0xC596, 0xB512, 0x940E, 0xA4B2, 0xBD96, 0xC5F8, 0xBD96,   // 0x2000 (8192)
+0xB534, 0xACD3, 0xA4D2, 0x8C0F, 0x734C, 0x5268, 0x4A27, 0x3985, 0x20E2, 0x20C2, 0x2923, 0x49E6, 0x5A68, 0x732B, 0x836C, 0x7B4B,   // 0x2010 (8208)
+0x8BEF, 0x9C71, 0x9430, 0x7BAE, 0x83CF, 0x83CF, 0x83EF, 0x83CE, 0x732C, 0x62AA, 0x62EB, 0x734D, 0x736D, 0x8410, 0x9473, 0x9473,   // 0x2020 (8224)
+0x9452, 0x8C31, 0x8C31, 0x8411, 0x83CF, 0x7BAE, 0x6B4C, 0x6B2B, 0x2903, 0x2103, 0x18C2, 0x20E2, 0x2102, 0x2103, 0x2103, 0x2103,   // 0x2030 (8240)
+0x2103, 0x2103, 0x20E2, 0x2103, 0x2903, 0x28E3, 0x28E3, 0x28E3, 0x2103, 0x2102, 0x2903, 0x28E3, 0x2903, 0x2903, 0x20C2, 0x20C2,   // 0x2040 (8256)
+0x20E2, 0x2903, 0x20E2, 0x2903, 0x2923, 0x3124, 0x3985, 0x41E6, 0x4207, 0x5268, 0x5289, 0x5ACB, 0x5ACA, 0x4228, 0x39A5, 0x4A07,   // 0x2050 (8272)
+0x6AEB, 0x62AA, 0x3984, 0x28E3, 0x3985, 0x5A89, 0x8C11, 0x83CF, 0x62C9, 0x7B6C, 0xA4D3, 0xBD97, 0xB556, 0x9C91, 0xB576, 0xCE3A,   // 0x2060 (8288)
+0xBD76, 0xACF4, 0xB555, 0xB515, 0xBD96, 0xD659, 0xD69A, 0xE6DC, 0xDE9B, 0xE6DC, 0xDE9A, 0xD659, 0xCDF8, 0xC5D7, 0xCDD7, 0xC5B7,   // 0x2070 (8304)
+0x8BAE, 0x4903, 0x38C3, 0x5A06, 0xBD34, 0xD619, 0xD639, 0xD639, 0xDE7A, 0xE6BB, 0xEF1C, 0xEF5C, 0xF7BE, 0xF7BE, 0xFF9E, 0xEF3C,   // 0x2080 (8320)
+0xEF3C, 0xF77D, 0xEF5D, 0xE6FC, 0xDEBB, 0xDE9A, 0xCE18, 0xCDF7, 0xCDF7, 0xCDF7, 0xC5F7, 0xCE18, 0xCE18, 0xC596, 0xCDF8, 0xCDF8,   // 0x2090 (8336)
+0xC596, 0xB4F3, 0xA491, 0xA4B2, 0xACF3, 0xACD2, 0x9C50, 0x83AD, 0x62A9, 0x5A89, 0x5269, 0x5248, 0x49C6, 0x41C6, 0x3965, 0x3985,   // 0x20A0 (8352)
+0x3164, 0x41A5, 0x5227, 0x5207, 0x6289, 0x7B8C, 0x9471, 0x9472, 0x8C10, 0x738D, 0x734C, 0x6B2C, 0x6B0C, 0x6B4C, 0x734C, 0x734D,   // 0x20B0 (8368)
+0x83CF, 0x8C31, 0x9472, 0x9452, 0x8C10, 0x8C10, 0x83F0, 0x83AE, 0x734C, 0x62EA, 0x5AC9, 0x2923, 0x2923, 0x2103, 0x2103, 0x2903,   // 0x20C0 (8384)
+0x2923, 0x2102, 0x2102, 0x20E2, 0x20E2, 0x20E2, 0x2102, 0x2903, 0x20E2, 0x20C2, 0x20E2, 0x2102, 0x2103, 0x2903, 0x20E3, 0x2903,   // 0x20D0 (8400)
+0x20E2, 0x20C2, 0x20C2, 0x20E2, 0x2903, 0x2903, 0x2903, 0x3144, 0x3144, 0x3144, 0x39C6, 0x4A27, 0x5268, 0x4A68, 0x630C, 0x62EB,   // 0x20E0 (8416)
+0x528A, 0x5ACB, 0x630C, 0x630B, 0x5AA9, 0x5227, 0x5A48, 0x736E, 0x83F0, 0x732B, 0x732A, 0x83CE, 0xA514, 0xC5FA, 0xC5F9, 0xCDF8,   // 0x20F0 (8432)
+0xDEBB, 0xDEBC, 0xCE19, 0xC5D8, 0xC5F8, 0xBD76, 0x942F, 0x9C71, 0xAD14, 0xCE19, 0xD65A, 0xD65A, 0xDE9B, 0xC5B8, 0xB4F3, 0xACF3,   // 0x2100 (8448)
+0x93EF, 0x6249, 0x59E6, 0x48C2, 0x4882, 0x4082, 0x3881, 0x5185, 0x72CA, 0xA492, 0xBD75, 0xCDD8, 0xDE9B, 0xDEDB, 0xE6FB, 0xEF5C,   // 0x2110 (8464)
+0xEF3C, 0xE6FC, 0xE6FC, 0xE71C, 0xEF3C, 0xE6FC, 0xDE9A, 0xC576, 0xD639, 0xE71D, 0xE71C, 0xDE9B, 0xD65A, 0xD639, 0xCDF7, 0xD679,   // 0x2120 (8480)
+0xDEBB, 0xDE9A, 0xDEBB, 0xDE9A, 0xCE18, 0xB534, 0xC5B7, 0xDE7A, 0xD638, 0xBD75, 0xACD2, 0xA4D3, 0x9410, 0x6289, 0x4A07, 0x4A07,   // 0x2130 (8496)
+0x5207, 0x49E6, 0x41A6, 0x5207, 0x5A48, 0x5227, 0x49C6, 0x49C6, 0x5A67, 0x838C, 0x940F, 0x734B, 0x62C9, 0x62EA, 0x5AA9, 0x5AA9,   // 0x2140 (8512)
+0x6B2B, 0x734D, 0x7BAE, 0x83F0, 0x8C51, 0x8C31, 0x8C31, 0x8C31, 0x9472, 0x9472, 0x83EF, 0x6B0B, 0x5268, 0x4A27, 0x3144, 0x3144,   // 0x2150 (8528)
+0x3123, 0x3123, 0x3144, 0x2943, 0x2923, 0x2923, 0x2103, 0x2103, 0x2102, 0x2102, 0x2923, 0x2103, 0x20E2, 0x20E2, 0x2102, 0x2103,   // 0x2160 (8544)
+0x2103, 0x2103, 0x2903, 0x20E2, 0x18C2, 0x18C2, 0x20E2, 0x2103, 0x2103, 0x2123, 0x2944, 0x3985, 0x3985, 0x39C6, 0x4206, 0x4A27,   // 0x2170 (8560)
+0x52AA, 0x52AA, 0x39A6, 0x3185, 0x3185, 0x41E7, 0x39E6, 0x5AA9, 0x83EF, 0x9CB4, 0x83F0, 0x5A88, 0x62CA, 0x838D, 0xAD14, 0xBD97,   // 0x2180 (8576)
+0xAD15, 0xC5D8, 0xDE9B, 0xDE9B, 0xDEBB, 0xDEBB, 0xE6FD, 0xDE9B, 0xB555, 0xA4B2, 0x9C70, 0x9C71, 0x9430, 0x9C71, 0xAD14, 0xC5B8,   // 0x2190 (8592)
+0x8C10, 0x41A5, 0x49A5, 0x49A5, 0x1800, 0x2041, 0x50A3, 0x58A3, 0x50A2, 0x48A2, 0x3882, 0x2840, 0x38E2, 0x59C6, 0x832C, 0x9C2F,   // 0x21A0 (8608)
+0xBD34, 0xCDF8, 0xD659, 0xDE9A, 0xDE7A, 0xDE9B, 0xCE18, 0xCE18, 0xBD55, 0xA491, 0x942F, 0x6B2B, 0x9430, 0xAD13, 0xD67A, 0xCE39,   // 0x21B0 (8624)
+0xD63A, 0xDEDB, 0xDEDB, 0xEF3C, 0xEF7D, 0xEF5D, 0xEF3C, 0xEF3C, 0xEF3D, 0xEF3C, 0xE71C, 0xE71C, 0xE6FB, 0xD659, 0xC5B6, 0xB555,   // 0x21C0 (8640)
+0xAD15, 0xA4F4, 0x9451, 0x83AE, 0x6ACA, 0x5A68, 0x5A68, 0x5207, 0x5A48, 0x730B, 0x7B6C, 0x7B6C, 0x7B8C, 0x8BEF, 0x8C0F, 0x6B2B,   // 0x21D0 (8656)
+0x5AA9, 0x62EA, 0x5268, 0x4A27, 0x732C, 0x8C11, 0x9452, 0x9472, 0x9452, 0x9472, 0x9472, 0x9493, 0x8C52, 0x7B8E, 0x630A, 0x62EA,   // 0x21E0 (8672)
+0x62EA, 0x3164, 0x3985, 0x3164, 0x3164, 0x3164, 0x3144, 0x2924, 0x2923, 0x3144, 0x3124, 0x2903, 0x2923, 0x2923, 0x2923, 0x2903,   // 0x21F0 (8688)
+0x2103, 0x2123, 0x2923, 0x2103, 0x2103, 0x2903, 0x2103, 0x2103, 0x20E2, 0x20E2, 0x2102, 0x2103, 0x2103, 0x2923, 0x3164, 0x39A5,   // 0x2200 (8704)
+0x41C6, 0x39C5, 0x4206, 0x5268, 0x4A27, 0x41E6, 0x39A6, 0x39C6, 0x31A6, 0x31C6, 0x62EB, 0x7B8F, 0x734D, 0x6AEA, 0x732B, 0x7B4B,   // 0x2210 (8720)
+0x9430, 0x9471, 0x8BEF, 0xBD77, 0xC5F9, 0xCE3A, 0xDE9B, 0xEF1D, 0xF77E, 0xEF7E, 0xE6FC, 0xCE3A, 0xBD76, 0xA4D2, 0x9C51, 0x838D,   // 0x2220 (8736)
+0x732B, 0x6289, 0x62AA, 0x2925, 0x0800, 0x1041, 0x28C2, 0x1841, 0x3061, 0x60C3, 0x60C3, 0x58C3, 0x50A3, 0x50C3, 0x40A2, 0x3881,   // 0x2230 (8752)
+0x4082, 0x4923, 0x48E3, 0x61A5, 0x8B2C, 0xA450, 0xACB2, 0xB534, 0xB514, 0x9C10, 0x9C30, 0x730B, 0x51C6, 0x6B2B, 0x39A5, 0x28C2,   // 0x2240 (8768)
+0x6288, 0xB555, 0xDEBC, 0xE6DC, 0xE75D, 0xF79E, 0xF79E, 0xFFDF, 0xFFDF, 0xFFDF, 0xF79E, 0xF79E, 0xF77D, 0xE71C, 0xE6BB, 0xDE7A,   // 0x2250 (8784)
+0xD65A, 0xCE3A, 0xB576, 0x9C71, 0x9430, 0x9430, 0x83CE, 0x7B8D, 0x732C, 0x6B0B, 0x5A69, 0x62A9, 0x7B4C, 0x7B8C, 0x83CE, 0x8BEF,   // 0x2260 (8800)
+0x62EA, 0x41C6, 0x4A28, 0x5AAA, 0x4207, 0x2923, 0x3985, 0x6B0B, 0x7BAE, 0x7BAF, 0x8C52, 0x9C93, 0x9C93, 0x9473, 0x8C11, 0x734D,   // 0x2270 (8816)
+0x6B0B, 0x630B, 0x62EB, 0x62EA, 0x3164, 0x3985, 0x3164, 0x3164, 0x3164, 0x3164, 0x3144, 0x3144, 0x3164, 0x3164, 0x3144, 0x3144,   // 0x2280 (8832)
+0x3144, 0x3144, 0x3144, 0x2923, 0x3144, 0x2944, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2923, 0x2903, 0x2923, 0x2923, 0x2923,   // 0x2290 (8848)
+0x2923, 0x3965, 0x39A5, 0x39A5, 0x4227, 0x4A48, 0x4A48, 0x4A27, 0x4207, 0x39A5, 0x2103, 0x1882, 0x2965, 0x4A28, 0x4A48, 0x62CA,   // 0x22A0 (8864)
+0x6B0B, 0x62C9, 0x734C, 0x734D, 0x3984, 0x7BAF, 0xAD15, 0xA4F5, 0xC5D9, 0xDE9B, 0xE6FD, 0xEF7E, 0xF79E, 0xEF5E, 0xE6FD, 0xCDF9,   // 0x22B0 (8880)
+0xBD76, 0x9C92, 0x942F, 0x838C, 0x49C5, 0x2081, 0x1062, 0x1041, 0x1021, 0x2882, 0x30A2, 0x5103, 0x9A47, 0x8A47, 0x7985, 0x6924,   // 0x22C0 (8896)
+0x6103, 0x50A2, 0x50A2, 0x50C3, 0x58E3, 0x58C3, 0x58A2, 0x6985, 0x7165, 0x5985, 0x5A27, 0x72A9, 0x6A68, 0x6227, 0x6A89, 0x4144,   // 0x22D0 (8912)
+0x3144, 0x6B0C, 0x6AA8, 0x9C71, 0xD65A, 0xEF3D, 0xF79E, 0xF7BE, 0xFFDF, 0xFFDE, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFDF, 0xF7BE, 0xF7BE,   // 0x22E0 (8928)
+0xEF5D, 0xE6DB, 0xD659, 0xC5D7, 0xB555, 0xB556, 0x8BF0, 0x6AEA, 0x62C9, 0x4A06, 0x5227, 0x6268, 0x6AC9, 0x6B0A, 0x83AD, 0x9410,   // 0x22F0 (8944)
+0x9451, 0x9430, 0x7B8E, 0x5268, 0x3144, 0x20E3, 0x28E3, 0x3144, 0x2903, 0x3985, 0x62CA, 0x734D, 0x7BCF, 0x9453, 0x8C32, 0x83D0,   // 0x2300 (8960)
+0x83D0, 0x7B8F, 0x6B4D, 0x6B2C, 0x630C, 0x5AAA, 0x62CA, 0x3164, 0x3964, 0x3144, 0x3144, 0x3144, 0x3144, 0x3164, 0x3144, 0x3144,   // 0x2310 (8976)
+0x3164, 0x3164, 0x3985, 0x3164, 0x3164, 0x3164, 0x3164, 0x3164, 0x3164, 0x3144, 0x3124, 0x3144, 0x3164, 0x3164, 0x3144, 0x3144,   // 0x2320 (8992)
+0x3144, 0x2923, 0x2923, 0x2923, 0x3144, 0x39A5, 0x4A27, 0x5268, 0x5268, 0x5AA9, 0x5268, 0x41E6, 0x2944, 0x20E3, 0x20E3, 0x31A6,   // 0x2330 (9008)
+0x18C3, 0x39A6, 0x5ACA, 0x62CB, 0x6B2C, 0x83D0, 0x41E6, 0x5A69, 0x9CB4, 0x9431, 0xACD4, 0xB536, 0xCE19, 0xE6DC, 0xEF5D, 0xEF5D,   // 0x2340 (9024)
+0xEF5D, 0xE73D, 0xDEBC, 0xCE19, 0xB535, 0xA4B2, 0x940F, 0x7B4B, 0x3944, 0x1041, 0x1062, 0x1041, 0x2862, 0x40E3, 0x8A88, 0xCC70,   // 0x2350 (9040)
+0xC450, 0xBC2F, 0xA38C, 0x92EA, 0x7A06, 0x6964, 0x7164, 0x71A5, 0x7164, 0x7944, 0x7965, 0x7965, 0x40A2, 0x4124, 0x6A47, 0x6A68,   // 0x2360 (9056)
+0x5185, 0x5A28, 0x5A69, 0x3964, 0x836D, 0xBD34, 0xDEBB, 0xF7DF, 0xFFDF, 0xF7BE, 0xFFDF, 0xFFFF, 0xFFDE, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x2370 (9072)
+0xFFDF, 0xF7BE, 0xF79E, 0xEF3C, 0xD67A, 0xCE18, 0xB554, 0xA4B1, 0x9C50, 0x9C92, 0x9430, 0x83AE, 0x7B4B, 0x7B6C, 0x7B8D, 0x734C,   // 0x2380 (9088)
+0x7B6C, 0x732B, 0x730B, 0x734D, 0x83CE, 0x5A89, 0x3124, 0x20E3, 0x2103, 0x20E2, 0x18A2, 0x3145, 0x4A27, 0x62EB, 0x7B6E, 0x7BD0,   // 0x2390 (9104)
+0x7BAF, 0x6B4D, 0x6B4D, 0x6B2D, 0x630C, 0x6B4D, 0x736E, 0x736D, 0x630B, 0x62EA, 0x3144, 0x3144, 0x2923, 0x2923, 0x3144, 0x3144,   // 0x23A0 (9120)
+0x3144, 0x3144, 0x3144, 0x3144, 0x3144, 0x3164, 0x3164, 0x3164, 0x3164, 0x3164, 0x3164, 0x3164, 0x3144, 0x3144, 0x3164, 0x3985,   // 0x23B0 (9136)
+0x3965, 0x3164, 0x3144, 0x3124, 0x2903, 0x2903, 0x2903, 0x2923, 0x3985, 0x4A48, 0x4A68, 0x4A47, 0x5268, 0x5289, 0x4206, 0x2924,   // 0x23C0 (9152)
+0x1081, 0x2145, 0x1082, 0x2924, 0x4A28, 0x4A48, 0x62EB, 0x9474, 0x83AF, 0x736D, 0xA4D4, 0x838E, 0x83AE, 0x8BF0, 0x9452, 0xBD97,   // 0x23D0 (9168)
+0xC5D9, 0xDE7B, 0xE6DC, 0xE71C, 0xEF5D, 0xEF3E, 0xDEDC, 0xD67B, 0xC5D8, 0xB556, 0xA4F4, 0x83AE, 0x3103, 0x1062, 0x1862, 0x2882,   // 0x23E0 (9184)
+0x61E6, 0xC450, 0xDD14, 0xDD55, 0xD576, 0xD576, 0xCD55, 0xBCB2, 0xAC0F, 0xABCE, 0xAB8D, 0xA36C, 0xAB2A, 0xAB0A, 0x9288, 0x3881,   // 0x23F0 (9200)
+0x61E6, 0x6A47, 0x59E6, 0x49A5, 0x3944, 0x7B6D, 0x836D, 0xA471, 0xDEBB, 0xF7BF, 0xFFFF, 0xFFFF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE,   // 0x2400 (9216)
+0xF7BE, 0xF79D, 0xF79D, 0xE71C, 0xD69A, 0xD659, 0xCDF8, 0xBD55, 0x9C70, 0x9450, 0x838D, 0x7B8C, 0x83CE, 0x83CF, 0x9430, 0x8C30,   // 0x2410 (9232)
+0x9451, 0x9CB2, 0x8C30, 0x83CE, 0x83AE, 0x62CA, 0x4185, 0x49C6, 0x4A07, 0x3144, 0x2903, 0x3144, 0x3965, 0x3144, 0x3144, 0x39A5,   // 0x2420 (9248)
+0x5AA9, 0x736E, 0x83D0, 0x7BAF, 0x738E, 0x736E, 0x6B4D, 0x6B2C, 0x630B, 0x62CA, 0x5A89, 0x5A88, 0x5AA9, 0x39A5, 0x39A5, 0x3144,   // 0x2430 (9264)
+0x2943, 0x3144, 0x2944, 0x2923, 0x2923, 0x2923, 0x3144, 0x3144, 0x3164, 0x3164, 0x3144, 0x3144, 0x3144, 0x3144, 0x2944, 0x3144,   // 0x2440 (9280)
+0x3164, 0x3965, 0x3985, 0x3164, 0x3144, 0x3144, 0x3144, 0x2903, 0x2923, 0x3144, 0x3164, 0x39C6, 0x41E6, 0x4206, 0x4A27, 0x4A28,   // 0x2450 (9296)
+0x4207, 0x39C6, 0x2903, 0x2103, 0x0841, 0x0840, 0x20E3, 0x39A6, 0x3184, 0x62EC, 0x9453, 0x9C73, 0xAD16, 0x9472, 0x83AE, 0x8BF0,   // 0x2460 (9312)
+0x736D, 0x8C11, 0x9C94, 0x9452, 0xB556, 0xDE9B, 0xEF3D, 0xEF5E, 0xF79F, 0xF79F, 0xEF5E, 0xE73D, 0xDEFD, 0xDEBC, 0xDEBC, 0x8BCE,   // 0x2470 (9328)
+0x20C1, 0x18A2, 0x30C3, 0x7AA9, 0xDD75, 0xDD34, 0xE596, 0xDD76, 0xDDF8, 0xDE19, 0xE63A, 0xD5D8, 0xD5D8, 0xCD35, 0xCD14, 0xCC70,   // 0x2480 (9344)
+0xCC70, 0xB3CD, 0x9BEF, 0x8B4C, 0x6A48, 0x4985, 0x41A6, 0x5249, 0x836D, 0xAC91, 0xCDF8, 0xEF7E, 0xF7BE, 0xFFDF, 0xFFFF, 0xFFDF,   // 0x2490 (9360)
+0xF7BE, 0xF7BE, 0xF79E, 0xEF9D, 0xF77D, 0xEF1C, 0xE6FB, 0xCDF7, 0xB514, 0xACB2, 0x9430, 0x8BCF, 0x6ACA, 0x62C9, 0x6ACA, 0x7B4C,   // 0x24A0 (9376)
+0x8BEF, 0xA4D4, 0xAD15, 0xACF5, 0xA4F4, 0xA4D4, 0x9C93, 0x7B8E, 0x732C, 0x6B0C, 0x41A6, 0x3124, 0x41C5, 0x41E6, 0x20E2, 0x20C2,   // 0x24B0 (9392)
+0x39A5, 0x3985, 0x3144, 0x4A27, 0x5A8A, 0x62EB, 0x630C, 0x5ACA, 0x41E7, 0x4207, 0x5268, 0x5268, 0x5247, 0x5247, 0x4A27, 0x5A68,   // 0x24C0 (9408)
+0x5289, 0x5AA9, 0x4A27, 0x41E6, 0x39C6, 0x31A5, 0x3164, 0x2944, 0x2944, 0x2944, 0x2923, 0x3144, 0x3144, 0x2923, 0x2923, 0x2903,   // 0x24D0 (9424)
+0x2923, 0x2944, 0x3144, 0x3144, 0x3144, 0x3144, 0x3144, 0x3124, 0x3144, 0x3144, 0x2923, 0x2943, 0x3164, 0x41C6, 0x41E6, 0x4206,   // 0x24E0 (9440)
+0x5268, 0x5289, 0x5A89, 0x5A8A, 0x5AAA, 0x4A48, 0x39A6, 0x18A2, 0x20E3, 0x3165, 0x39C6, 0x4A48, 0x8C31, 0x8C32, 0xA4F5, 0xB537,   // 0x24F0 (9456)
+0x9CB4, 0xA4F5, 0x83CF, 0x734C, 0x9C94, 0x7B8E, 0x734D, 0xA4D4, 0xC5D8, 0xDEBB, 0xE6FC, 0xE73D, 0xEF7E, 0xF79E, 0xEF7E, 0xEF7E,   // 0x2500 (9472)
+0xEF7E, 0xF7BF, 0xDE9B, 0x5A68, 0x3124, 0x28C2, 0x932B, 0xE575, 0xDD55, 0xDD55, 0xDD76, 0xDDD8, 0xE639, 0xE69B, 0xE63A, 0xE619,   // 0x2510 (9488)
+0xDD96, 0xD534, 0xCCB1, 0xD470, 0xCCD2, 0xDE3A, 0xA430, 0x6A28, 0x49A5, 0x3965, 0x5228, 0x93CE, 0xCDD7, 0xEF3D, 0xFFDF, 0xFFDE,   // 0x2520 (9504)
+0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF79E, 0xE71C, 0xDE9A, 0xDEBA, 0xD679, 0xCDF7, 0xB555, 0x9CB2, 0x734C, 0x7B4D, 0x838E, 0x83AD,   // 0x2530 (9520)
+0x6AEA, 0x7B4C, 0x8BEF, 0x9431, 0xA4B4, 0xB557, 0xBD97, 0xAD15, 0x9452, 0x732D, 0x62AA, 0x62CA, 0x5AAA, 0x5AAA, 0x528A, 0x5A69,   // 0x2540 (9536)
+0x41E6, 0x41A6, 0x3164, 0x3164, 0x20E2, 0x3985, 0x5289, 0x62EA, 0x630B, 0x5AAA, 0x39A5, 0x3144, 0x39A5, 0x4A07, 0x4A27, 0x4A27,   // 0x2550 (9552)
+0x4A27, 0x4A06, 0x5227, 0x6B6D, 0x738E, 0x5AEB, 0x5ACA, 0x52AA, 0x5289, 0x4A48, 0x4A28, 0x4207, 0x39C6, 0x3184, 0x3185, 0x39A5,   // 0x2560 (9568)
+0x39A5, 0x3184, 0x2944, 0x2944, 0x3164, 0x2923, 0x2923, 0x2943, 0x3144, 0x2923, 0x2923, 0x2923, 0x2923, 0x2944, 0x2964, 0x39C5,   // 0x2570 (9584)
+0x4207, 0x4A27, 0x5268, 0x5AA9, 0x5ACA, 0x630B, 0x6B4D, 0x6B2C, 0x6B2C, 0x4A28, 0x2103, 0x1081, 0x20A2, 0x3144, 0x6B0C, 0x9473,   // 0x2580 (9600)
+0x83EF, 0xA4B4, 0xAD36, 0xBD98, 0xB557, 0x9CB4, 0x9C72, 0x8BF0, 0x6B0C, 0x8BF0, 0xA4D3, 0xB534, 0xB535, 0xBDB7, 0xDE9B, 0xE71D,   // 0x2590 (9616)
+0xEF5E, 0xEF5E, 0xF77E, 0xF7BF, 0xFFDF, 0xFFFF, 0xA4B3, 0x3103, 0x3103, 0xB42F, 0xDD34, 0xDD13, 0xDD34, 0xDD34, 0xE5F8, 0xEE7B,   // 0x25A0 (9632)
+0xF6DC, 0xE63A, 0xE5F8, 0xDDB7, 0xD514, 0xCC91, 0xCC6F, 0xCCD1, 0xAC72, 0x72AA, 0x59E6, 0x3944, 0x5A69, 0x72C9, 0xBD55, 0xF75D,   // 0x25B0 (9648)
+0xFFFF, 0xFFDF, 0xFFDF, 0xF7BE, 0xFFDE, 0xF7BE, 0xEF7D, 0xEF7D, 0xE71C, 0xCDF7, 0xB514, 0xA491, 0x93EE, 0x7B6C, 0x83AD, 0x7B6D,   // 0x25C0 (9664)
+0x7B4C, 0x7B6D, 0x7B8D, 0x9430, 0x7B8D, 0x8BCF, 0x9451, 0x9C73, 0x9472, 0x9C93, 0x9451, 0x8410, 0x6B2B, 0x5248, 0x5248, 0x5268,   // 0x25D0 (9680)
+0x4A07, 0x3124, 0x3165, 0x5228, 0x5A8A, 0x4A48, 0x4206, 0x41E7, 0x5269, 0x5ACA, 0x62EB, 0x5ACA, 0x4A69, 0x5289, 0x5ACA, 0x5A89,   // 0x25E0 (9696)
+0x5268, 0x4A06, 0x4A06, 0x4A06, 0x41E6, 0x4A06, 0x7BCF, 0x83F0, 0x6B8E, 0x736D, 0x736D, 0x6B4D, 0x6B2C, 0x630C, 0x630B, 0x630B,   // 0x25F0 (9712)
+0x5AEB, 0x52AA, 0x5ACA, 0x5ACA, 0x52A9, 0x5289, 0x4A68, 0x4A48, 0x4227, 0x41E6, 0x41E6, 0x41E6, 0x41E6, 0x39A5, 0x3185, 0x3185,   // 0x2600 (9728)
+0x3185, 0x39A5, 0x39C6, 0x39C6, 0x41C6, 0x41E6, 0x4A28, 0x5AA9, 0x5ACA, 0x5ACA, 0x5269, 0x4A28, 0x3165, 0x3185, 0x39A6, 0x41E6,   // 0x2610 (9744)
+0x5A88, 0x9473, 0xA4D6, 0xB557, 0xBDFA, 0xB598, 0xCDFA, 0xC5FB, 0xACF5, 0x9C93, 0x83EF, 0x838E, 0x8BEF, 0x8BEF, 0x8BEF, 0x942F,   // 0x2620 (9760)
+0xA4B3, 0xB576, 0xD65A, 0xEF3E, 0xEF5E, 0xEF7E, 0xF7BF, 0xFFBF, 0xFFFF, 0xE6DC, 0x5A48, 0x3943, 0xCCB2, 0xDD14, 0xCC71, 0xDD14,   // 0x2630 (9776)
+0xE576, 0xE619, 0xEE7A, 0xEE7B, 0xE619, 0xDDD8, 0xDD97, 0xD4F3, 0xCC2F, 0xD490, 0xC42F, 0x61C6, 0x5185, 0x4164, 0x3903, 0x72C9,   // 0x2640 (9792)
+0xB4F3, 0xEF1C, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF79E, 0xEF5D, 0xE73C, 0xDE9A, 0xD659, 0xBD55, 0x9C50, 0x940F, 0x8BCE,   // 0x2650 (9808)
+0x5227, 0x5A68, 0x6288, 0x732C, 0x8C0F, 0x9C71, 0x9492, 0x9C92, 0x8BEF, 0x7B6D, 0x736D, 0x62CA, 0x5269, 0x4A28, 0x5AAA, 0x5AA9,   // 0x2660 (9824)
+0x5248, 0x4A27, 0x4A07, 0x5248, 0x630B, 0x5A89, 0x5248, 0x5248, 0x4207, 0x4A27, 0x4A28, 0x5289, 0x5ACB, 0x5ACB, 0x5ACA, 0x5ACA,   // 0x2670 (9840)
+0x5ACB, 0x62EB, 0x5AA9, 0x5248, 0x4A27, 0x4A27, 0x4A06, 0x41E6, 0x4A06, 0x7BAE, 0x8C10, 0x7BCF, 0x7BAE, 0x738E, 0x736E, 0x736D,   // 0x2680 (9856)
+0x736D, 0x736D, 0x738E, 0x738E, 0x738E, 0x7BAF, 0x73AF, 0x738E, 0x6B6D, 0x6B4C, 0x6B4C, 0x6B4C, 0x632C, 0x630B, 0x5AEB, 0x62EB,   // 0x2690 (9872)
+0x62EB, 0x5ACA, 0x52AA, 0x5289, 0x5268, 0x4A48, 0x4A27, 0x4A07, 0x49E7, 0x4A27, 0x5289, 0x4A69, 0x4A48, 0x5268, 0x4A28, 0x3986,   // 0x26A0 (9888)
+0x2924, 0x4A28, 0x736D, 0x8BEF, 0xAD16, 0xAD15, 0xB577, 0x9C72, 0x9473, 0xC5DA, 0x9CB4, 0x83D0, 0xA4D5, 0x9432, 0x7B8D, 0x6AEA,   // 0x26B0 (9904)
+0x6AEB, 0x7B6D, 0x6AEA, 0x838E, 0xA4B3, 0xC5B8, 0xD65B, 0xE71D, 0xF77F, 0xFFBF, 0xF7BF, 0xFFDF, 0xFFDF, 0xA4B3, 0x4985, 0xB42F,   // 0x26C0 (9920)
+0xDCF3, 0xCC50, 0xD4D3, 0xDD35, 0xE597, 0xE5F9, 0xE5D9, 0xE5D8, 0xDD97, 0xD4F4, 0xCC71, 0xCC70, 0xDCD1, 0x8ACA, 0x28C2, 0x28C3,   // 0x26D0 (9936)
+0x30E2, 0x6A88, 0xB4D3, 0xEF1D, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xF7BE, 0xF79E, 0xEF7E, 0xEF3D, 0xDEBB, 0xC5D7, 0xACF3, 0xAD13,   // 0x26E0 (9952)
+0x836C, 0x7B6C, 0x7B6C, 0x8BEE, 0x8BEE, 0x83AD, 0x8C30, 0x9CB3, 0xACF4, 0xAD15, 0x9CB4, 0x9493, 0x7B8E, 0x62AA, 0x5248, 0x4A07,   // 0x26F0 (9968)
+0x39A6, 0x3965, 0x5228, 0x39A6, 0x28E2, 0x3144, 0x41C6, 0x5227, 0x734D, 0x734C, 0x5269, 0x4A49, 0x5ACB, 0x5AAA, 0x62EB, 0x6B2C,   // 0x2700 (9984)
+0x736D, 0x736E, 0x738F, 0x736F, 0x630C, 0x5289, 0x5248, 0x4A27, 0x41E6, 0x41C6, 0x41E6, 0x4A27, 0x734D, 0x83CF, 0x7B8E, 0x736E,   // 0x2710 (10000)
+0x6B4D, 0x6B4D, 0x6B2D, 0x6B4D, 0x736D, 0x736D, 0x738E, 0x738E, 0x7BAF, 0x83EF, 0x7BAF, 0x7B8E, 0x7B8E, 0x7BAE, 0x73AE, 0x73AE,   // 0x2720 (10016)
+0x7BCF, 0x7BAF, 0x7BAF, 0x73AE, 0x738E, 0x736E, 0x6B4D, 0x6B2C, 0x630B, 0x5AEB, 0x5ACA, 0x5AAA, 0x5AAA, 0x5289, 0x5289, 0x52A9,   // 0x2730 (10032)
+0x5AEA, 0x5289, 0x4207, 0x4A28, 0x6B0B, 0x9451, 0xB536, 0xB557, 0xB577, 0xAD36, 0xA4D4, 0xA4F5, 0xA4F6, 0x8C32, 0x8C52, 0x9452,   // 0x2740 (10048)
+0x7B6E, 0x6B0B, 0x6B0B, 0x6AEB, 0x732C, 0x7B4C, 0x8C0F, 0x7B6D, 0x8BCF, 0xB556, 0xCE1A, 0xE6FD, 0xE73D, 0xF79F, 0xFFBF, 0xF7BF,   // 0x2750 (10064)
+0xE6FD, 0x72AB, 0x932B, 0xCC50, 0xCC2F, 0xCC50, 0xD491, 0xD4F3, 0xDD35, 0xDD56, 0xDD55, 0xD4F4, 0xCC71, 0xCC0E, 0xD4D2, 0xABAD,   // 0x2760 (10080)
+0x30A2, 0x18A2, 0x28E2, 0x6A88, 0xACD2, 0xEF1C, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFDF, 0xFFDE, 0xF79E, 0xEF7E, 0xE6FC, 0xD69B, 0xC5B7,   // 0x2770 (10096)
+0xA4F3, 0x732B, 0x9430, 0x83EE, 0x734B, 0x9C51, 0xA4D3, 0xB555, 0xB536, 0xACF4, 0xAD16, 0xB577, 0xB597, 0xA4D5, 0x7BCF, 0x6B4D,   // 0x2780 (10112)
+0x41E7, 0x3165, 0x41E6, 0x3985, 0x3985, 0x41C6, 0x4A28, 0x39A6, 0x20A3, 0x30E3, 0x3124, 0x3965, 0x49E7, 0x41C6, 0x31A5, 0x3985,   // 0x2790 (10128)
+0x41C6, 0x62CA, 0x7B8E, 0x8C52, 0x8C53, 0x73AF, 0x5AEB, 0x4A48, 0x41E6, 0x4207, 0x39C5, 0x3965, 0x3164, 0x41C6, 0x5A88, 0x738E,   // 0x27A0 (10144)
+0x7BEF, 0x738E, 0x738E, 0x736D, 0x736D, 0x734D, 0x6B4D, 0x6B4C, 0x736D, 0x736E, 0x738E, 0x7B8F, 0x7BAF, 0x7B8F, 0x736E, 0x736D,   // 0x27B0 (10160)
+0x738E, 0x738E, 0x7BAF, 0x8411, 0x8411, 0x7BCF, 0x7BAE, 0x738E, 0x7B8E, 0x738D, 0x736D, 0x6B4C, 0x6B4C, 0x6B2B, 0x62EB, 0x5AAA,   // 0x27C0 (10176)
+0x4A48, 0x4227, 0x528A, 0x630C, 0x6B2D, 0x630C, 0x6B2B, 0x7B6D, 0x8BEF, 0x9C93, 0xACD4, 0xB536, 0xA4F5, 0xAD16, 0xA4F5, 0x8BF0,   // 0x27D0 (10192)
+0x838E, 0x734C, 0x734C, 0x62CA, 0x7BAF, 0x9452, 0x9431, 0x9C93, 0xA4D4, 0x9471, 0x7B6D, 0x8BEF, 0x9C72, 0xACF4, 0xAD35, 0xDEDC,   // 0x27E0 (10208)
+0xEF7F, 0xEF7E, 0xEF5E, 0xF7BF, 0xA4B3, 0x7B0B, 0xE5F7, 0xD4B1, 0xD450, 0xCC30, 0xD470, 0xD491, 0xD4B2, 0xD4B2, 0xCC71, 0xD4B1,   // 0x27F0 (10224)
+0xE5B5, 0xBC2F, 0x5123, 0x28A2, 0x4185, 0x6A88, 0xB4D3, 0xE71D, 0xFFFF, 0xFFFF, 0xF7BE, 0xF7BE, 0xF7BF, 0xF77E, 0xEF7E, 0xDEDB,   // 0x2800 (10240)
+0xCE39, 0xBD97, 0xACF3, 0x9C51, 0x83AE, 0x83AD, 0xACF3, 0x940F, 0x9451, 0x9CB2, 0xA4D3, 0xACF4, 0xB535, 0xA4D4, 0x8C31, 0x734D,   // 0x2810 (10256)
+0x7B6E, 0x7BAF, 0x6B0C, 0x524A, 0x20A2, 0x2903, 0x3144, 0x3144, 0x3144, 0x41C6, 0x5ACA, 0x6B2C, 0x6B2B, 0x5A89, 0x3185, 0x1041,   // 0x2820 (10272)
+0x1881, 0x2923, 0x2923, 0x41E6, 0x62CA, 0x734D, 0x7B8E, 0x7BAF, 0x630C, 0x5ACA, 0x5ACB, 0x5ACB, 0x5289, 0x3185, 0x18C2, 0x20C2,   // 0x2830 (10288)
+0x41E6, 0x6B0A, 0x7BCF, 0x8410, 0x73AE, 0x7BCF, 0x7BCF, 0x7BAF, 0x7BAE, 0x738E, 0x736D, 0x734D, 0x736E, 0x7BCF, 0x7BAF, 0x83D0,   // 0x2840 (10304)
+0x7BD0, 0x7B8E, 0x736D, 0x6B8E, 0x7BAF, 0x83D0, 0x83F0, 0x8410, 0x7BCF, 0x7B8E, 0x736E, 0x736D, 0x734C, 0x6B4C, 0x6B2C, 0x6B2C,   // 0x2850 (10320)
+0x630B, 0x5ACA, 0x5AAA, 0x4A88, 0x4248, 0x4A89, 0x4A69, 0x4248, 0x5ACA, 0x83CF, 0x9C92, 0xACF4, 0xB536, 0xACF5, 0xAD15, 0xA4D5,   // 0x2860 (10336)
+0x9CB4, 0x8C10, 0x83EF, 0x736C, 0x83CE, 0x8C0F, 0x83AE, 0x9431, 0x9472, 0xACF6, 0xAD16, 0xB577, 0xBDB8, 0xC5F8, 0xC619, 0xB556,   // 0x2870 (10352)
+0xA4D3, 0x9431, 0xBDB8, 0xD69C, 0xDEDC, 0xE71D, 0xFFDF, 0xBD96, 0x5A07, 0xDDD7, 0xE5F8, 0xD4D2, 0xD470, 0xD4B1, 0xD491, 0xD471,   // 0x2880 (10368)
+0xD4B2, 0xD491, 0xD4D1, 0xF71C, 0x8B0B, 0x4081, 0x59C6, 0x72A9, 0x9C30, 0xE71D, 0xFFDF, 0xFFDF, 0xF7BF, 0xF79E, 0xEF7D, 0xEF3D,   // 0x2890 (10384)
+0xE71D, 0xDEDC, 0xBDB8, 0xA4B3, 0x8BCE, 0x83AD, 0x9430, 0x9C71, 0x9C92, 0xB556, 0xBD97, 0xBD76, 0xBD76, 0xB535, 0xA4B3, 0xA4B3,   // 0x28A0 (10400)
+0x9C93, 0x7BAE, 0x5227, 0x28E2, 0x41C6, 0x62AA, 0x5A89, 0x5AAA, 0x4185, 0x41A6, 0x2903, 0x3144, 0x3144, 0x3164, 0x5228, 0x41E7,   // 0x28B0 (10416)
+0x2924, 0x1882, 0x20E3, 0x2904, 0x2903, 0x3965, 0x5A89, 0x6AEB, 0x62EB, 0x6B2C, 0x8C32, 0x8C11, 0x6B4D, 0x5AEB, 0x4A69, 0x39E7,   // 0x28C0 (10432)
+0x2144, 0x20E3, 0x3185, 0x5268, 0x734B, 0x7BAF, 0x83F0, 0x7BAE, 0x7BCF, 0x7BAF, 0x7B8F, 0x7BAF, 0x7BAF, 0x7BAE, 0x738E, 0x73AF,   // 0x28D0 (10448)
+0x7BD0, 0x7BAF, 0x7BD0, 0x83D0, 0x83D0, 0x738E, 0x73AE, 0x7BD0, 0x83F0, 0x83F0, 0x7BF0, 0x83F0, 0x83D0, 0x7BAE, 0x736E, 0x6B2D,   // 0x28E0 (10464)
+0x6B2C, 0x630B, 0x62EB, 0x62EB, 0x5AEA, 0x52AA, 0x5289, 0x52A9, 0x5289, 0x4228, 0x31C6, 0x4227, 0x7B6D, 0x9452, 0x9C72, 0xA4D4,   // 0x28F0 (10480)
+0xB536, 0xB557, 0xB577, 0xB536, 0xA4F5, 0xA4F4, 0x9C93, 0xA4D4, 0xA4D4, 0x838D, 0x6B0B, 0x83CF, 0xA4B3, 0xAD15, 0xC5F9, 0xDEBC,   // 0x2900 (10496)
+0xEF3E, 0xDEDC, 0xC5D9, 0x9451, 0x83AE, 0x9C72, 0xB556, 0xBDB8, 0xE6FD, 0xF7BF, 0xC618, 0x3103, 0x8289, 0xDD74, 0xE555, 0xD490,   // 0x2910 (10512)
+0xDCF2, 0xDCB2, 0xD470, 0xD4F3, 0xDD34, 0xD4F2, 0xDD96, 0x8ACA, 0x5144, 0x4944, 0x6227, 0xCDB7, 0xFFDF, 0xFFFF, 0xFFDF, 0xF79F,   // 0x2920 (10528)
+0xEF3D, 0xD67A, 0xCDF8, 0xA4B3, 0xA4B3, 0xA4B3, 0x9C51, 0x8BEF, 0x7B4C, 0x7B8D, 0x9472, 0x9C93, 0xA4D4, 0xA4D4, 0xAD14, 0xB556,   // 0x2930 (10544)
+0xB556, 0xA515, 0x8C11, 0x734D, 0x62AA, 0x5228, 0x41C6, 0x3964, 0x49E6, 0x5228, 0x3164, 0x4A07, 0x2903, 0x39A5, 0x3985, 0x3124,   // 0x2940 (10560)
+0x20A2, 0x18A1, 0x1881, 0x20C3, 0x3124, 0x1041, 0x1061, 0x3164, 0x5268, 0x62EB, 0x6B0C, 0x6B2C, 0x7BAF, 0x8C32, 0x8C52, 0x7BD0,   // 0x2950 (10576)
+0x52AA, 0x31A5, 0x2124, 0x39A6, 0x5289, 0x5AA9, 0x62C9, 0x736C, 0x738E, 0x83EF, 0x7B8E, 0x7B8F, 0x7B8F, 0x736E, 0x736E, 0x738E,   // 0x2960 (10592)
+0x738E, 0x6B6E, 0x738E, 0x738F, 0x736E, 0x736E, 0x73AF, 0x738F, 0x6B4D, 0x6B6D, 0x738F, 0x7BD0, 0x7BD0, 0x7BCF, 0x7BD0, 0x83D0,   // 0x2970 (10608)
+0x7BCF, 0x736E, 0x6B2D, 0x632C, 0x630B, 0x5ACA, 0x5ACA, 0x5AAA, 0x5289, 0x4A68, 0x4248, 0x39E7, 0x39E7, 0x4A48, 0x5AC9, 0x734D,   // 0x2980 (10624)
+0x9C93, 0xACF5, 0xB536, 0xBD77, 0xC5B8, 0xBDD8, 0xBD97, 0xB577, 0xB577, 0xB557, 0xC5B9, 0xC5D8, 0xA4D4, 0x9432, 0x9431, 0x9CB3,   // 0x2990 (10640)
+0xAD36, 0x9C92, 0xA492, 0xACF4, 0xB536, 0xAD15, 0x9C93, 0x7BAE, 0x5A88, 0x83CE, 0xB556, 0xCE3B, 0xE73E, 0xDEBB, 0x5A07, 0x2881,   // 0x29A0 (10656)
+0x69C6, 0x92EB, 0x9B2C, 0xBC51, 0xB3AE, 0xC42F, 0xCC92, 0xBC2F, 0xAB8C, 0x8AA9, 0x6144, 0x4924, 0x38E2, 0x830B, 0xE6DC, 0xFFFF,   // 0x29B0 (10672)
+0xFFDF, 0xF79E, 0xF77E, 0xEF5E, 0xCE5A, 0xA4D4, 0x8C10, 0x730B, 0x7B6C, 0x838D, 0x838E, 0x7B6D, 0x7B6D, 0x838E, 0x8BEF, 0x8BEF,   // 0x29C0 (10688)
+0x9431, 0x7B4D, 0x7B6D, 0x7BAE, 0x7B8E, 0x7BAE, 0x7B6D, 0x62A9, 0x62AA, 0x6ACA, 0x732B, 0x62AA, 0x62CA, 0x5268, 0x41C6, 0x41C7,   // 0x29D0 (10704)
+0x3985, 0x5A89, 0x6AEB, 0x732C, 0x62CA, 0x49E6, 0x3123, 0x3144, 0x2903, 0x3124, 0x49E7, 0x5A89, 0x6B0B, 0x6B0B, 0x734D, 0x8C52,   // 0x29E0 (10720)
+0x9CB5, 0x9473, 0x8432, 0x7BF1, 0x6B4D, 0x52AA, 0x5269, 0x5ACA, 0x6B2B, 0x736C, 0x7BAD, 0x6B6D, 0x83F0, 0x7BCF, 0x7BAF, 0x7BCF,   // 0x29F0 (10736)
+0x7BAF, 0x738E, 0x736E, 0x6B6E, 0x738E, 0x738F, 0x736E, 0x736E, 0x738E, 0x738E, 0x6B6E, 0x6B4D, 0x632D, 0x6B6E, 0x738E, 0x738F,   // 0x2A00 (10752)
+0x738F, 0x738F, 0x738F, 0x736E, 0x6B2D, 0x630C, 0x630C, 0x5AEB, 0x5ACA, 0x52CA, 0x5289, 0x5268, 0x4247, 0x39C6, 0x3185, 0x2964,   // 0x2A10 (10768)
+0x31A5, 0x5AA9, 0x83CF, 0x9C93, 0xA4D4, 0xBD77, 0xBD77, 0xC5D9, 0xBDB8, 0xBD97, 0xB577, 0xAD36, 0xA4B4, 0x9CB4, 0xB556, 0xBD98,   // 0x2A20 (10784)
+0xB515, 0x838D, 0x732C, 0x6AEB, 0x838D, 0x9C51, 0x9C72, 0xC5B8, 0xC5D8, 0xB556, 0x7B8C, 0x5A68, 0x62EA, 0x83CF, 0x9452, 0xC619,   // 0x2A30 (10800)
+0xF79F, 0xBD75, 0x7B0B, 0x51A6, 0x38E3, 0x3061, 0x4904, 0x61E7, 0x7AAA, 0x61C6, 0x48C2, 0x40A2, 0x40E3, 0x5185, 0x6228, 0x8B6D,   // 0x2A40 (10816)
+0xCDD8, 0xF7BF, 0xF7BF, 0xF77E, 0xEF5E, 0xE6FC, 0xD65A, 0xAD15, 0x9471, 0x7B6D, 0x7B4C, 0x7BAD, 0x7B8D, 0x838E, 0x734C, 0x6AEA,   // 0x2A50 (10832)
+0x5A48, 0x5A88, 0x5AA9, 0x5A89, 0x6AEB, 0x49C6, 0x4185, 0x51E6, 0x5A68, 0x6AE9, 0x7B4B, 0x8C30, 0xA4D4, 0x9451, 0x7B8D, 0x5A89,   // 0x2A60 (10848)
+0x5A89, 0x4A07, 0x5248, 0x6B0B, 0x62EA, 0x732B, 0x83AE, 0x83CE, 0x732B, 0x5A88, 0x3985, 0x20C2, 0x3144, 0x4A07, 0x62CA, 0x6B2C,   // 0x2A70 (10864)
+0x6B2C, 0x7BAE, 0x8C32, 0x8C73, 0x8411, 0x73AF, 0x6B4D, 0x632C, 0x630B, 0x62EB, 0x630B, 0x736C, 0x736C, 0x6B2B, 0x738E, 0x8C10,   // 0x2A80 (10880)
+0x7BD0, 0x7BAF, 0x83D0, 0x83D0, 0x7BAF, 0x736E, 0x738F, 0x83D0, 0x83D0, 0x738F, 0x738E, 0x73AF, 0x736E, 0x736E, 0x736E, 0x6B6E,   // 0x2A90 (10896)
+0x736E, 0x738E, 0x73AF, 0x738F, 0x738E, 0x736E, 0x6B6E, 0x6B4D, 0x630C, 0x5AEB, 0x5AEB, 0x5ACB, 0x5289, 0x4A48, 0x4247, 0x4227,   // 0x2AA0 (10912)
+0x39C6, 0x3185, 0x2965, 0x39C6, 0x5249, 0x7B8E, 0x8BF0, 0x9431, 0x9C93, 0xB536, 0xC5B8, 0xC5D9, 0xC5D9, 0xB577, 0xB536, 0xA4B4,   // 0x2AB0 (10928)
+0x6B0A, 0x734C, 0x9C31, 0x9C71, 0x83CD, 0x6AEA, 0x51E6, 0x6ACA, 0x9C70, 0xBD77, 0xD67B, 0xD67B, 0xC5F8, 0x9C91, 0x838D, 0x62C9,   // 0x2AC0 (10944)
+0x49E6, 0x5A48, 0xA514, 0xEF1E, 0xEF3E, 0xDE7B, 0xBD15, 0xA451, 0x832C, 0x7247, 0x93CF, 0xAC71, 0x82EA, 0x8289, 0x936C, 0xA40F,   // 0x2AD0 (10960)
+0xB4B2, 0xCDB6, 0xDE7B, 0xFFBF, 0xFFDF, 0xEF5D, 0xE6FC, 0xDEBC, 0xBD97, 0xA493, 0x83AE, 0x730B, 0x9410, 0x732C, 0x7BAE, 0x7B8D,   // 0x2AE0 (10976)
+0x83AE, 0x734C, 0x62AA, 0x3103, 0x28E3, 0x49E7, 0x3965, 0x4A07, 0x5207, 0x5206, 0x5A68, 0x734C, 0x7B8D, 0x7BAD, 0x7B8D, 0x83EF,   // 0x2AF0 (10992)
+0x732C, 0x5A89, 0x5228, 0x5207, 0x5227, 0x5A68, 0x732B, 0x7BAE, 0x83AE, 0x7B6D, 0x7B4C, 0x62CA, 0x5AA9, 0x39A6, 0x18A1, 0x3124,   // 0x2B00 (11008)
+0x5268, 0x6AEB, 0x734D, 0x7B8F, 0x83D0, 0x8411, 0x8C52, 0x8C52, 0x7BD0, 0x6B4C, 0x62EA, 0x5AA9, 0x5268, 0x5268, 0x5268, 0x5268,   // 0x2B10 (11024)
+0x5A88, 0x736E, 0x7BF0, 0x738F, 0x738E, 0x7BAF, 0x73AF, 0x738F, 0x736E, 0x738F, 0x7BD0, 0x83F0, 0x73AF, 0x738E, 0x73AF, 0x738F,   // 0x2B20 (11040)
+0x738F, 0x738F, 0x73AF, 0x738F, 0x738E, 0x738E, 0x6B6E, 0x6B6E, 0x738E, 0x736E, 0x6B6D, 0x632C, 0x630C, 0x630B, 0x5ACA, 0x528A,   // 0x2B30 (11056)
+0x4A68, 0x4248, 0x4227, 0x31C6, 0x2985, 0x3186, 0x39E7, 0x4A48, 0x6B0B, 0x9451, 0xACF5, 0xBDB8, 0xC5B8, 0xC5D9, 0xCE1B, 0xCE1A,   // 0x2B40 (11072)
+0xBD97, 0xACF5, 0xA4B3, 0x7B8E, 0x83EF, 0x9451, 0x9451, 0x940F, 0x83CD, 0x62A9, 0x72EA, 0x8BEE, 0xC5D8, 0xDE9C, 0xCE39, 0xCE19,   // 0x2B50 (11088)
+0xC5B8, 0xA4B2, 0x7B8D, 0x62A9, 0x5A68, 0x7B6C, 0xBDD8, 0xE6DD, 0xEF3E, 0xDEBC, 0xCDD8, 0xC576, 0xC535, 0xB471, 0xAC50, 0xB491,   // 0x2B60 (11104)
+0xC4F4, 0xCDD8, 0xDE5A, 0xE69B, 0xEF1D, 0xF79F, 0xF79E, 0xEF5D, 0xDE9B, 0xBD98, 0xB557, 0x9452, 0x734B, 0x7B8D, 0x62EA, 0x7B8E,   // 0x2B70 (11120)
+0x7B6D, 0x732C, 0x7B8D, 0x5A89, 0x5A68, 0x5A89, 0x3965, 0x28A1, 0x4185, 0x5A89, 0x5248, 0x62AA, 0x732C, 0x7B4C, 0x8BEF, 0xA493,   // 0x2B80 (11136)
+0x9471, 0x83CE, 0x6AEA, 0x62CA, 0x5207, 0x5A48, 0x62A9, 0x732B, 0x83CE, 0x8BCE, 0x9430, 0x9C72, 0x8C10, 0x7B4C, 0x5A68, 0x5268,   // 0x2B90 (11152)
+0x5268, 0x41C6, 0x4A07, 0x5ACA, 0x6B0B, 0x630B, 0x6B2C, 0x83F0, 0x9453, 0x8C53, 0x8411, 0x738E, 0x630B, 0x4A27, 0x39A5, 0x4207,   // 0x2BA0 (11168)
+0x4A07, 0x4A06, 0x4A27, 0x5268, 0x73AF, 0x7BF0, 0x736E, 0x736E, 0x738E, 0x738E, 0x738E, 0x738E, 0x73AF, 0x7BD0, 0x8411, 0x7BF0,   // 0x2BB0 (11184)
+0x7BCF, 0x7BCF, 0x7BCF, 0x7BAF, 0x7BCF, 0x7BAF, 0x73AF, 0x73AF, 0x738F, 0x6B6E, 0x6B6E, 0x738F, 0x738E, 0x6B6E, 0x6B4D, 0x632C,   // 0x2BC0 (11200)
+0x632C, 0x62EB, 0x5ACA, 0x5ACA, 0x4A48, 0x39C6, 0x2144, 0x2103, 0x2944, 0x18E3, 0x2103, 0x5248, 0x83CE, 0xAD14, 0xBD97, 0xBD97,   // 0x2BD0 (11216)
+0xBD77, 0xBD56, 0xACD3, 0x9430, 0x83AE, 0x9C72, 0xBD98, 0xB536, 0xAD16, 0xB536, 0xB535, 0xACF3, 0x8BEF, 0x93EF, 0xA493, 0xB535,   // 0x2BE0 (11232)
+0xAD13, 0xB534, 0xCDF8, 0xCDF9, 0xC5B7, 0xA4D3, 0x9430, 0x732B, 0x6AC9, 0x8C0F, 0xC5F9, 0xDE9B, 0xDEDC, 0xE6BB, 0xDE7B, 0xD63A,   // 0x2BF0 (11248)
+0xD619, 0xDE5A, 0xD619, 0xDE3A, 0xDE9C, 0xEF5E, 0xEF5D, 0xEF1D, 0xEF3D, 0xE6FD, 0xCDF9, 0xB515, 0x9431, 0x6B0B, 0x6B0A, 0x6B0A,   // 0x2C00 (11264)
+0x734C, 0x7B8D, 0x736C, 0x83EF, 0x5A69, 0x6AEB, 0x730B, 0x5A48, 0x5A47, 0x4A06, 0x4185, 0x49C6, 0x5A68, 0x62C9, 0x6288, 0x732B,   // 0x2C10 (11280)
+0x9430, 0x9430, 0x9430, 0x8BEF, 0x732B, 0x5A47, 0x5A47, 0x5A48, 0x730B, 0x8BEE, 0x9C71, 0x9C71, 0x9C51, 0x9430, 0x9430, 0x8BEE,   // 0x2C20 (11296)
+0x730A, 0x62C9, 0x62EA, 0x62C9, 0x5A68, 0x62CA, 0x6B2C, 0x6B2C, 0x6B2C, 0x738E, 0x8C31, 0x9494, 0x9473, 0x7BF0, 0x6B4D, 0x5A89,   // 0x2C30 (11312)
+0x39C5, 0x3164, 0x41C6, 0x5247, 0x5247, 0x5A88, 0x5268, 0x83F0, 0x8C11, 0x736E, 0x738F, 0x73AF, 0x7B8F, 0x7BAF, 0x7BCF, 0x7BF0,   // 0x2C40 (11328)
+0x7BF0, 0x8411, 0x8411, 0x8411, 0x8411, 0x8411, 0x8411, 0x8411, 0x7BF0, 0x83F1, 0x8411, 0x83F1, 0x7BAF, 0x7BD0, 0x7BF1, 0x7BD0,   // 0x2C50 (11344)
+0x738F, 0x6B4E, 0x632C, 0x632C, 0x630C, 0x62EB, 0x5AEB, 0x52A9, 0x4228, 0x39C6, 0x2985, 0x2964, 0x2924, 0x1061, 0x1861, 0x41A6,   // 0x2C60 (11360)
+0x732C, 0x942F, 0xACF3, 0xA4B2, 0x83AD, 0x7B2B, 0x730A, 0x7B4B, 0x9C92, 0xCDF9, 0xA4D4, 0x9C93, 0xAD35, 0xB556, 0xB576, 0xBD56,   // 0x2C70 (11376)
+0xA4B3, 0xA493, 0x940F, 0x8BCE, 0x9C91, 0xB514, 0xC5B8, 0xC5D8, 0xC597, 0xACD4, 0x9C70, 0x734B, 0x62A9, 0x83AF, 0xB535, 0xDE7B,   // 0x2C80 (11392)
+0xE6FD, 0xEF3D, 0xEF1D, 0xE6FD, 0xE71D, 0xEF3D, 0xEEFC, 0xDE9B, 0xE6DC, 0xE6FC, 0xDE9B, 0xB535, 0xAD14, 0x9C72, 0x7B6D, 0x6AEB,   // 0x2C90 (11408)
+0x62A8, 0x5A68, 0x6B0A, 0x732B, 0x7B6C, 0x8C0F, 0x8C0F, 0x7B8C, 0x72EA, 0x730A, 0x6AEA, 0x6AEA, 0x6ACA, 0x6289, 0x6AEA, 0x7B8C,   // 0x2CA0 (11424)
+0x8BEE, 0x8BEE, 0x83CE, 0x9CB2, 0xA4B2, 0x8BEF, 0x836C, 0x7B4C, 0x72EA, 0x6ACA, 0x83CE, 0xA4B2, 0xAD15, 0xB556, 0xB556, 0xB556,   // 0x2CB0 (11440)
+0xB535, 0xA4B2, 0x8C0F, 0x83EE, 0x8C30, 0x83CD, 0x6B0A, 0x5247, 0x5A89, 0x6B2C, 0x7B6E, 0x7B8E, 0x7BD0, 0x8411, 0x8C52, 0x8411,   // 0x2CC0 (11456)
+0x736E, 0x632D, 0x5ACA, 0x4A47, 0x39C6, 0x41E6, 0x4A06, 0x41C5, 0x4A06, 0x5A88, 0x83F0, 0x8431, 0x738E, 0x738E, 0x73AF, 0x7BAF,   // 0x2CD0 (11472)
+0x7BD0, 0x7BF0, 0x7BD0, 0x7BF0, 0x8411, 0x8411, 0x83F1, 0x8411, 0x8411, 0x8411, 0x7BF0, 0x83F0, 0x8411, 0x8431, 0x8411, 0x8C11,   // 0x2CE0 (11488)
+0x8C11, 0x8C12, 0x8411, 0x83F0, 0x7B8F, 0x734D, 0x6B2C, 0x630C, 0x5AEB, 0x5ACA, 0x5289, 0x4A27, 0x31C6, 0x2965, 0x2944, 0x20E3,   // 0x2CF0 (11504)
+0x1882, 0x20A2, 0x41E6, 0x6B0B, 0x7B8E, 0x8BF0, 0x8BEF, 0x732B, 0x732B, 0x9430, 0xACF4, 0xB535, 0xB557, 0xB557, 0xAD16, 0xAD15,   // 0x2D00 (11520)
+0xC5B8, 0xBD98, 0xACF4, 0xAD14, 0xACD3, 0xA491, 0x9C50, 0x8BCE, 0xA491, 0xB535, 0xC5D7, 0xB556, 0xAD15, 0xACF4, 0x8BEE, 0x62A8,   // 0x2D10 (11536)
+0x5A47, 0x9430, 0xB576, 0xD63A, 0xE6DC, 0xE6DC, 0xE6DC, 0xEEFD, 0xE6DC, 0xEEFC, 0xDE9B, 0xDE7B, 0xC5B7, 0xACD3, 0x732B, 0x5A88,   // 0x2D20 (11552)
+0x62A9, 0x62A9, 0x5A88, 0x6B0A, 0x732B, 0x838C, 0x940F, 0x8BEF, 0x9C71, 0xA4B2, 0x9C50, 0x8BEF, 0x8BEE, 0x7B6C, 0x7B6C, 0x732B,   // 0x2D30 (11568)
+0x836C, 0x8BEF, 0xA4D3, 0xACF4, 0xB555, 0xACF4, 0x9450, 0x8BAD, 0x7B2B, 0x6AC9, 0x7B4B, 0x83AD, 0x9450, 0xAD15, 0xBD97, 0xC5D9,   // 0x2D40 (11584)
+0xCE19, 0xCDF9, 0xBD97, 0xACF4, 0x9450, 0x9450, 0x9C91, 0x9CB3, 0x8C30, 0x732B, 0x5AA9, 0x5AAA, 0x6B2C, 0x7B8E, 0x736E, 0x738F,   // 0x2D50 (11600)
+0x7BAF, 0x7BAF, 0x6B4E, 0x5AEC, 0x52AA, 0x4A69, 0x4207, 0x39C6, 0x41C5, 0x4A07, 0x4A27, 0x4A06, 0x5247, 0x8411, 0x8C72, 0x7BF0,   // 0x2D60 (11616)
+0x7BAF, 0x7BCF, 0x7BD0, 0x7BD0, 0x7BD0, 0x7BD0, 0x7BD0, 0x83F1, 0x83F1, 0x7BD0, 0x83F1, 0x8411, 0x7BF0, 0x7BAF, 0x7BD0, 0x8411,   // 0x2D70 (11632)
+0x8411, 0x7BF1, 0x83F0, 0x8C31, 0x8411, 0x7BF0, 0x7BD0, 0x83D0, 0x7BCF, 0x738E, 0x6B4C, 0x62EB, 0x52AA, 0x4A68, 0x4207, 0x39C6,   // 0x2D80 (11648)
+0x39E7, 0x41C6, 0x28E3, 0x18A2, 0x2904, 0x4A07, 0x62EA, 0x734C, 0x734D, 0x83AE, 0x8BCE, 0x8BEE, 0x9C71, 0x9CB3, 0xA4D3, 0xAD15,   // 0x2D90 (11664)
+0xC5B7, 0xCE19, 0xCE3A, 0xCE19, 0xC5B7, 0xB555, 0xBD96, 0xBD96, 0xB514, 0x83AD, 0x7B4C, 0x93CE, 0xACD3, 0xA4D3, 0x9451, 0xA4B2,   // 0x2DA0 (11680)
+0xACF4, 0x8BEF, 0x6AC9, 0x5A47, 0x72EA, 0x732B, 0x9430, 0xB514, 0xBD76, 0xD639, 0xD63A, 0xCDF8, 0xCDD8, 0xB556, 0xB535, 0xA4B3,   // 0x2DB0 (11696)
+0x5A68, 0x41C6, 0x4185, 0x5A68, 0x62A8, 0x6B0A, 0x732B, 0x8BEF, 0xA492, 0xAD34, 0xB555, 0xB514, 0xBD55, 0xBD75, 0xACD3, 0x942F,   // 0x2DC0 (11712)
+0x940E, 0x942F, 0x8BCE, 0x8BAD, 0x9C91, 0xAD35, 0xAD15, 0xACF4, 0xB535, 0xA4B2, 0x838D, 0x730B, 0x730A, 0x8BEE, 0x9C92, 0xAD14,   // 0x2DD0 (11728)
+0xC5B7, 0xCDF9, 0xCE1A, 0xCE1A, 0xBD77, 0xA4B4, 0x9451, 0x83AD, 0x83AD, 0x9C71, 0x9C93, 0x8C30, 0x62EA, 0x5268, 0x62CA, 0x6B0B,   // 0x2DE0 (11744)
+0x734D, 0x736E, 0x8410, 0x8411, 0x736E, 0x5AEC, 0x5ACB, 0x4A69, 0x4A48, 0x4227, 0x39A5, 0x4A07, 0x5AA8, 0x62C9, 0x5AA9, 0x62A9,   // 0x2DF0 (11760)
+0x8411, 0x9493, 0x8432, 0x83F1, 0x8411, 0x8411, 0x83F1, 0x7BF1, 0x83F1, 0x8411, 0x83F1, 0x83F1, 0x7BF1, 0x83F1, 0x8411, 0x83F0,   // 0x2E00 (11776)
+0x7BCF, 0x7BCF, 0x83F1, 0x8411, 0x7BF1, 0x7BB0, 0x7BF1, 0x8411, 0x7BD0, 0x7BAF, 0x7BAF, 0x83F0, 0x83EF, 0x7BAE, 0x6B2C, 0x5ACA,   // 0x2E10 (11792)
+0x5289, 0x4247, 0x4248, 0x4A48, 0x41E6, 0x39A5, 0x41E6, 0x5268, 0x6ACA, 0x62AA, 0x7B4C, 0x838E, 0x9430, 0x9451, 0x9C72, 0xA4B3,   // 0x2E20 (11808)
+0x9C71, 0x9C71, 0xA4B2, 0xACF3, 0xB535, 0xC5B8, 0xC619, 0xCE19, 0xCE3A, 0xC596, 0xAC91, 0x8BAC, 0x7B6C, 0x838D, 0x6AEA, 0x6268,   // 0x2E30 (11824)
+0x6268, 0x732B, 0x9C72, 0xA4F4, 0x9C72, 0x730B, 0x72EA, 0x72EA, 0x6267, 0x51E5, 0x6288, 0x6AEA, 0x9CB2, 0x838D, 0x940F, 0x9430,   // 0x2E40 (11840)
+0x83CE, 0x7B4C, 0x7B4B, 0x5227, 0x4185, 0x5A67, 0x62A9, 0x732B, 0x9430, 0x9430, 0xA4B2, 0xACF4, 0xC5D7, 0xD67A, 0xC5F8, 0xC596,   // 0x2E50 (11856)
+0xD659, 0xCDD8, 0xB535, 0xACF3, 0xA4B2, 0xACD3, 0xA4B3, 0xA4D3, 0xB556, 0xB536, 0xA4B3, 0x8BEF, 0x8BEE, 0x8BEE, 0x7B6C, 0x730A,   // 0x2E60 (11872)
+0x83AD, 0xACD3, 0xC5D8, 0xCE39, 0xCE5A, 0xCE1A, 0xBDB7, 0xAD14, 0x9C72, 0x9430, 0x83CE, 0x7BAD, 0x8C30, 0x9430, 0x730B, 0x5248,   // 0x2E70 (11888)
+0x5268, 0x5A89, 0x62CA, 0x630C, 0x736E, 0x7B8F, 0x83F1, 0x6B6E, 0x52AA, 0x4207, 0x2944, 0x2904, 0x3164, 0x3164, 0x39A5, 0x4A06,   // 0x2E80 (11904)
+0x5A68, 0x62A9, 0x6AEA, 0x8411, 0x8C73, 0x8411, 0x7BF1, 0x8411, 0x8411, 0x83F1, 0x83F1, 0x8411, 0x8431, 0x8411, 0x8411, 0x8411,   // 0x2E90 (11920)
+0x8411, 0x8411, 0x8411, 0x83F1, 0x7BF1, 0x8411, 0x8431, 0x8431, 0x83F1, 0x83F1, 0x8411, 0x7BF0, 0x7BAF, 0x7BAF, 0x7BAF, 0x7BAF,   // 0x2EA0 (11936)
+0x7B8E, 0x736D, 0x5ACA, 0x5289, 0x4A68, 0x4227, 0x52AA, 0x734D, 0x7BAE, 0x83CF, 0x7B8E, 0x83AE, 0x9430, 0xA4B3, 0xACF5, 0xACF5,   // 0x2EB0 (11952)
+0x9C72, 0x9431, 0x8C30, 0x9430, 0x9C72, 0xA4B3, 0xAD35, 0xC5B8, 0xC5B8, 0xC5D9, 0xCDD9, 0xBDB8, 0xACD3, 0x93AE, 0x8BCD, 0x940E,   // 0x2EC0 (11968)
+0x7B2B, 0x6247, 0x49A5, 0x5A27, 0x6B0A, 0x7B8D, 0xA4B2, 0x9C51, 0x838D, 0x8BEE, 0x730A, 0x49E5, 0x49C5, 0x49C5, 0x6288, 0x6AEA,   // 0x2ED0 (11984)
+0x49E6, 0x5227, 0x5A68, 0x5207, 0x5A68, 0x5A67, 0x5A88, 0x5A89, 0x62C9, 0x7B6C, 0x8C0F, 0xAD35, 0xB576, 0xBD76, 0xBD76, 0xC5D7,   // 0x2EE0 (12000)
+0xDEBB, 0xDE9B, 0xC5D7, 0xD69A, 0xD67A, 0xC5D8, 0xCDF8, 0xCDF8, 0xC5B7, 0xBD76, 0xAD35, 0xACF4, 0x8BEF, 0x8C10, 0x7B6D, 0x6ACA,   // 0x2EF0 (12016)
+0x838C, 0x9430, 0x8C0F, 0x8BEE, 0xA4D2, 0xBD76, 0xC5D8, 0xC5B8, 0xB557, 0xA4D4, 0x83CF, 0x62EA, 0x5A88, 0x5227, 0x5227, 0x62AA,   // 0x2F00 (12032)
+0x734C, 0x6B0C, 0x3144, 0x20C2, 0x41E6, 0x62EA, 0x734D, 0x7B8E, 0x7BF0, 0x7BD0, 0x632D, 0x39E6, 0x18C2, 0x1061, 0x0840, 0x1041,   // 0x2F10 (12048)
+0x20A2, 0x3965, 0x4A27, 0x4A27, 0x4A27, 0x5227, 0x8411, 0x8C52, 0x83F1, 0x7BF0, 0x8411, 0x8411, 0x7BF0, 0x7BF0, 0x8411, 0x8432,   // 0x2F20 (12064)
+0x8C32, 0x8C32, 0x8C52, 0x8C52, 0x8431, 0x8C52, 0x8C52, 0x8C32, 0x8432, 0x8C52, 0x8C53, 0x8C32, 0x8432, 0x8412, 0x8411, 0x8411,   // 0x2F30 (12080)
+0x83F1, 0x7BF0, 0x7BD0, 0x7BCF, 0x7BAE, 0x736D, 0x6B4D, 0x6B6E, 0x73AF, 0x9474, 0xAD37, 0xB578, 0xB537, 0xB536, 0xB577, 0xBD97,   // 0x2F40 (12096)
+0xBD37, 0xB515, 0xA493, 0x7B8E, 0x6B0B, 0x62CA, 0x730B, 0x6AC9, 0x732B, 0x8C0F, 0x9C92, 0xB556, 0xCDF8, 0xD65B, 0xD65B, 0xC5B8,   // 0x2F50 (12112)
+0xB514, 0xACB2, 0x93EE, 0x836C, 0x7B0A, 0x6AA9, 0x6AA9, 0x51E6, 0x5A46, 0x838C, 0x8BCE, 0xA4F4, 0xB534, 0x5206, 0x49C5, 0x4184,   // 0x2F60 (12128)
+0x49E5, 0x5A68, 0x5206, 0x4185, 0x3964, 0x3944, 0x49A5, 0x5A27, 0x6288, 0x730B, 0x730B, 0x7B6C, 0x9430, 0xA4B3, 0xBD77, 0xC5D8,   // 0x2F70 (12144)
+0xC5B8, 0xCE19, 0xD67A, 0xE6FC, 0xE6FC, 0xD67A, 0xD67A, 0xE6BB, 0xCE19, 0xC5B8, 0xC5D8, 0xCDF8, 0xC5B7, 0xAD14, 0xAD14, 0x838D,   // 0x2F80 (12160)
+0x5206, 0x72EA, 0x732B, 0x7B6C, 0xA491, 0xB534, 0xB555, 0xACF3, 0xB555, 0xAD15, 0x9431, 0x8BF0, 0x83CF, 0x734D, 0x5A69, 0x5227,   // 0x2F90 (12176)
+0x5A48, 0x62A9, 0x5A89, 0x49E7, 0x3165, 0x2903, 0x20C2, 0x39A5, 0x6AEB, 0x7B8E, 0x83D0, 0x8C52, 0x8432, 0x738F, 0x5AEB, 0x39C7,   // 0x2FA0 (12192)
+0x2904, 0x2903, 0x2904, 0x2903, 0x3144, 0x41E6, 0x41E6, 0x41E6, 0x4A27, 0x8411, 0x8C52, 0x83F1, 0x83F1, 0x83F1, 0x8411, 0x7BF0,   // 0x2FB0 (12208)
+0x7BF0, 0x8411, 0x8411, 0x8C32, 0x8C52, 0x8C53, 0x8C53, 0x8C52, 0x8C73, 0x8C52, 0x8C52, 0x8C53, 0x9473, 0x9473, 0x8C73, 0x8C73,   // 0x2FC0 (12224)
+0x8C53, 0x8C73, 0x8C72, 0x8432, 0x8431, 0x8411, 0x7BF0, 0x83D0, 0x83F1, 0x8432, 0x8C53, 0x9CD6, 0xBDD9, 0xC61A, 0xCE3A, 0xCE1A,   // 0x2FD0 (12240)
+0xBD98, 0xACF5, 0x9C72, 0x83AE, 0x732C, 0x5207, 0x3103, 0x28E3, 0x4185, 0x5A27, 0x6289, 0x8BCE, 0xACD4, 0xBD77, 0xC5D8, 0xCDF9,   // 0x2FE0 (12256)
+0xCE19, 0xCE1A, 0xCDF8, 0xB535, 0xA4D2, 0x9C71, 0x838D, 0x7B2A, 0x7B2A, 0x6268, 0x51C5, 0x51E5, 0x6AC9, 0x8C10, 0xB576, 0x730B,   // 0x2FF0 (12272)
+0x3923, 0x49E6, 0x41C5, 0x5226, 0x5A27, 0x49C6, 0x41A5, 0x49C6, 0x41A5, 0x6268, 0x6AC9, 0x730A, 0x7B6C, 0x838D, 0x9430, 0x9C93,   // 0x3000 (12288)
+0xAD15, 0xC5B8, 0xCE1A, 0xCDF9, 0xD67A, 0xDEBB, 0xE6FC, 0xE6FC, 0xDEDC, 0xDEBB, 0xD67A, 0xDE7A, 0xC5B7, 0xACF3, 0xA4D3, 0xB534,   // 0x3010 (12304)
+0xA4B2, 0x8BEF, 0x8BEF, 0x7B6D, 0x734C, 0x83AD, 0x8BEE, 0x940F, 0xB513, 0xD639, 0xCDF8, 0xB556, 0x9C72, 0x734C, 0x6B0A, 0x730B,   // 0x3020 (12320)
+0x732B, 0x7B6C, 0x734C, 0x6AEA, 0x734B, 0x736C, 0x5248, 0x20C2, 0x0020, 0x1881, 0x3985, 0x62CA, 0x7BAE, 0x7BAE, 0x630C, 0x52AA,   // 0x3030 (12336)
+0x52AA, 0x5AEB, 0x5289, 0x3985, 0x3124, 0x3964, 0x39A5, 0x2903, 0x20A2, 0x2903, 0x3164, 0x3985, 0x8C52, 0x9493, 0x8411, 0x8411,   // 0x3040 (12352)
+0x8411, 0x8411, 0x8411, 0x83F1, 0x83F1, 0x8411, 0x8432, 0x8C32, 0x8C32, 0x8C32, 0x8C52, 0x8C52, 0x8C32, 0x8C32, 0x8C52, 0x8C73,   // 0x3050 (12368)
+0x9473, 0x9493, 0x9473, 0x8C73, 0x9493, 0x8C72, 0x8C32, 0x8431, 0x8431, 0x8C31, 0x9452, 0x9473, 0x9CB5, 0xA517, 0xBDD9, 0xC61B,   // 0x3060 (12384)
+0xCE5B, 0xCE5B, 0xCE3B, 0xC5FA, 0xA4D4, 0x6B0B, 0x5A48, 0x49E6, 0x3944, 0x20C2, 0x20A2, 0x3123, 0x5226, 0x6ACA, 0x734C, 0x7B8D,   // 0x3070 (12400)
+0x734C, 0x736C, 0x9C72, 0xBD97, 0xD63A, 0xDE7B, 0xD63A, 0xC5B7, 0xB535, 0x9C70, 0x93ED, 0x8B8D, 0x8BAD, 0x72E9, 0x6A88, 0x8BF0,   // 0x3080 (12416)
+0x8C11, 0x6ACB, 0x3103, 0x30E3, 0x62A9, 0x62A9, 0x6288, 0x6288, 0x5226, 0x51E6, 0x5A67, 0x62A8, 0x7B6C, 0x838C, 0x83CE, 0x9430,   // 0x3090 (12432)
+0xA4B3, 0xACF4, 0xA4D3, 0xB556, 0xCDF9, 0xCE1A, 0xC5B8, 0xDE7B, 0xDE7A, 0xDE9B, 0xDEBB, 0xDE7B, 0xDE7A, 0xD65A, 0xDE9B, 0xCE18,   // 0x30A0 (12448)
+0x8BEF, 0x8BCE, 0x83AD, 0x83AE, 0x83AD, 0x7B6B, 0x6288, 0x6ACA, 0x838D, 0x9C71, 0x9C50, 0x8BEF, 0x9C92, 0xBD77, 0xBD77, 0xB557,   // 0x30B0 (12464)
+0xACF5, 0xA4D4, 0xAD14, 0x9CB2, 0x9C92, 0xA4B2, 0x9C91, 0x83EF, 0x6AEB, 0x3986, 0x1040, 0x0000, 0x1040, 0x4A07, 0x734C, 0x7BCE,   // 0x30C0 (12480)
+0x8410, 0x6B4D, 0x5268, 0x39C6, 0x3186, 0x41E6, 0x3164, 0x20C2, 0x2903, 0x41C6, 0x39A5, 0x3964, 0x3985, 0x41C6, 0x5227, 0x9493,   // 0x30D0 (12496)
+0x9CB4, 0x8C52, 0x8C53, 0x8C32, 0x8432, 0x8C32, 0x8411, 0x8411, 0x83F1, 0x8411, 0x8431, 0x8C11, 0x8C11, 0x8C32, 0x8C32, 0x8C32,   // 0x30E0 (12512)
+0x8C32, 0x9473, 0x9473, 0x8C73, 0x8C73, 0x9493, 0x9493, 0x9473, 0x8C52, 0x8C72, 0x9472, 0x8C31, 0x8C31, 0x9452, 0x9473, 0x9CD5,   // 0x30F0 (12528)
+0xAD37, 0xB577, 0xB578, 0xBD99, 0xC5D9, 0xC5FA, 0xC5FA, 0xB578, 0xACF5, 0x9C72, 0x7B6D, 0x49E6, 0x20C2, 0x1861, 0x1021, 0x1041,   // 0x3100 (12544)
+0x1881, 0x1881, 0x20A1, 0x3985, 0x6AEB, 0x8BEF, 0xB535, 0xD65A, 0xE6BB, 0xE6DC, 0xE6BB, 0xD67A, 0xCE18, 0xB555, 0xB513, 0x93EE,   // 0x3110 (12560)
+0x7B4B, 0x9C71, 0x8C0F, 0x5A47, 0x4184, 0x41A5, 0x4165, 0x5A68, 0x732B, 0x732B, 0x6288, 0x5227, 0x62A9, 0x732B, 0x7B8C, 0x9430,   // 0x3120 (12576)
+0x9450, 0x9C92, 0xACF4, 0xB535, 0xBD76, 0xB514, 0xBD76, 0xD61A, 0xBD76, 0xBD76, 0xCE19, 0xD639, 0xCDF9, 0xCE19, 0xCDF8, 0xCE19,   // 0x3130 (12592)
+0xC5B7, 0xCDD8, 0xB555, 0x8BCE, 0x6AC9, 0x6AA9, 0x6AC9, 0x838C, 0x940F, 0x93EE, 0x838D, 0x7B6C, 0x9C31, 0xA4B3, 0x9472, 0x9452,   // 0x3140 (12608)
+0x9451, 0x7BAE, 0x83AE, 0x9C72, 0xAD15, 0xBD77, 0xC5D9, 0xBD77, 0x9CB2, 0x9C71, 0x8C30, 0x7B8D, 0x62AA, 0x41E7, 0x2903, 0x3964,   // 0x3150 (12624)
+0x6B0B, 0x83F0, 0x9472, 0x9CB3, 0x8C51, 0x630C, 0x3185, 0x2923, 0x39A5, 0x4206, 0x39A5, 0x3144, 0x3144, 0x39A5, 0x5247, 0x5A88,   // 0x3160 (12640)
+0x5246, 0x5A87, 0x9493, 0x9CD4, 0x8C52, 0x8C53, 0x8C53, 0x8C53, 0x8C52, 0x8C32, 0x8411, 0x8411, 0x8411, 0x8411, 0x83F0, 0x83D0,   // 0x3170 (12656)
+0x83F1, 0x83F1, 0x8411, 0x8431, 0x8C52, 0x9473, 0x9473, 0x8C72, 0x9493, 0x9493, 0x94B3, 0x9493, 0x9473, 0x9473, 0x9452, 0x8C31,   // 0x3180 (12672)
+0x8411, 0x83F0, 0x8411, 0x8411, 0x6B4D, 0x736E, 0x9473, 0xAD36, 0xBDB9, 0xC63B, 0xCE3B, 0xCDFA, 0xAD16, 0x7B8D, 0x5227, 0x3965,   // 0x3190 (12688)
+0x3985, 0x3965, 0x20C2, 0x1882, 0x20E3, 0x2923, 0x41E6, 0x5227, 0x730B, 0xB534, 0xDE9B, 0xE71D, 0xEF3D, 0xEF3D, 0xE6FC, 0xE6BC,   // 0x31A0 (12704)
+0xCDD8, 0xACD2, 0x9C30, 0xACD2, 0xACF3, 0x8B8C, 0x72C9, 0x72EA, 0x6AC9, 0x4164, 0x49C6, 0x6B0A, 0x6B0A, 0x62C9, 0x6AEA, 0x732A,   // 0x31B0 (12720)
+0x8C0F, 0x8BCE, 0x9C71, 0x9471, 0xACF4, 0xB514, 0xB515, 0xBD55, 0xB535, 0xB535, 0xCDFA, 0xACF3, 0xACF3, 0xBD55, 0xBD96, 0xC5B8,   // 0x31C0 (12736)
+0xBD97, 0xB4F4, 0xB514, 0xACD3, 0xA491, 0xA492, 0x8BCE, 0x7B6C, 0x7B2B, 0x6A88, 0x730A, 0xA4B2, 0x9C91, 0xA492, 0x8C0F, 0x83CF,   // 0x31D0 (12752)
+0x8C10, 0x9431, 0x8C10, 0x83CF, 0x9431, 0x9472, 0x9451, 0x9431, 0x8BF0, 0x8C10, 0x9C72, 0x9431, 0x7B8D, 0x6B2B, 0x6B2B, 0x6B0B,   // 0x31E0 (12768)
+0x62EA, 0x62CA, 0x5A89, 0x62CA, 0x7BAE, 0x9472, 0x9C93, 0x9CB3, 0x8C31, 0x5288, 0x4A27, 0x5288, 0x5AA9, 0x630B, 0x6B0B, 0x62CA,   // 0x31F0 (12784)
+0x5AA9, 0x62EA, 0x6B2B, 0x736C, 0x83CD, 0x9452, 0x9CB4, 0x8C32, 0x8432, 0x8432, 0x8C32, 0x8432, 0x8411, 0x83F0, 0x83F1, 0x83F1,   // 0x3200 (12800)
+0x7BD0, 0x7BD0, 0x73AF, 0x7BAF, 0x7BD0, 0x83F0, 0x8411, 0x8411, 0x8411, 0x8C52, 0x8C32, 0x8C52, 0x8C72, 0x9473, 0x9473, 0x8C72,   // 0x3210 (12816)
+0x8C52, 0x8C52, 0x9473, 0x8C52, 0x7BF1, 0x630C, 0x52AA, 0x4227, 0x4A48, 0x6B2C, 0x9453, 0xAD17, 0xBD98, 0xC5F9, 0xC5F9, 0xC5D9,   // 0x3220 (12832)
+0xB556, 0xAD15, 0xACF4, 0x9C71, 0x62CA, 0x3144, 0x18A2, 0x1882, 0x2904, 0x20A2, 0x41A5, 0x8BCD, 0xCDD7, 0xD65A, 0xDE9B, 0xDEBC,   // 0x3230 (12848)
+0xDEBB, 0xE6FC, 0xE6DC, 0xD67A, 0xCDF8, 0xC596, 0xC596, 0xACB2, 0x8BED, 0x9C50, 0x9C70, 0x6AC9, 0x6288, 0x5A67, 0x6AE9, 0x7B6C,   // 0x3240 (12864)
+0x6ACA, 0x62C9, 0x7B6C, 0x8C30, 0x838D, 0x83AD, 0x942F, 0xAD14, 0xACD3, 0xB535, 0xACF2, 0xACF3, 0xACF4, 0xBD56, 0xA491, 0x9C71,   // 0x3250 (12880)
+0x940F, 0x9C50, 0xACF2, 0xBD76, 0xACD3, 0x9C51, 0x8BEE, 0x836C, 0x9430, 0x83CE, 0x7B6C, 0x940F, 0x9C50, 0x83AE, 0x942F, 0x8BCE,   // 0x3260 (12896)
+0x838D, 0x9471, 0x9431, 0x9452, 0xA4D4, 0x9CB3, 0x9471, 0xAD15, 0xBDD8, 0xAD36, 0x83AE, 0x5AA9, 0x41A5, 0x3985, 0x5227, 0x6AEA,   // 0x3270 (12912)
+0x838D, 0x8C0F, 0x83EF, 0x6B0C, 0x5AA9, 0x6B2B, 0x736D, 0x7B6D, 0x8C10, 0x9471, 0x8C50, 0x8C30, 0x630C, 0x5AC9, 0x6B2B, 0x7BAE,   // 0x3280 (12928)
+0x8C0F, 0x9471, 0x9471, 0x8C30, 0x8C30, 0x9451, 0x9C92, 0xAD15, 0x8411, 0x9473, 0x8411, 0x8411, 0x8411, 0x8432, 0x8431, 0x7BF0,   // 0x3290 (12944)
+0x83D0, 0x83F1, 0x7BF0, 0x7BAF, 0x73AF, 0x73AF, 0x738F, 0x7BAF, 0x7BD0, 0x7BF1, 0x83F1, 0x83F1, 0x8411, 0x8411, 0x8C32, 0x8C32,   // 0x32A0 (12960)
+0x8C32, 0x9473, 0x9493, 0x9493, 0x9CB5, 0x9CB5, 0x8C52, 0x632C, 0x39C6, 0x2944, 0x39C6, 0x52AA, 0x62EB, 0x736E, 0x9C94, 0xBDB9,   // 0x32B0 (12976)
+0xD67C, 0xDE9C, 0xDEBC, 0xDEDD, 0xD69C, 0xC5B8, 0x9431, 0x49E6, 0x1060, 0x1881, 0x3144, 0x20C2, 0x28E3, 0x6289, 0x940F, 0xA4D3,   // 0x32C0 (12992)
+0xBD97, 0xD65A, 0xDE9B, 0xE6DC, 0xEF3D, 0xF77E, 0xEF3D, 0xDEDB, 0xDEBB, 0xCDF8, 0xACF4, 0xACB3, 0xACF3, 0x9430, 0x83CD, 0x83AD,   // 0x32D0 (13008)
+0x7B4B, 0x83AC, 0x8BEE, 0x83AD, 0x7B4C, 0x83AE, 0x83CE, 0x8BCE, 0x8BCE, 0x9410, 0xA4B3, 0xAD14, 0xC5B7, 0xB534, 0xACF3, 0xA4B2,   // 0x32E0 (13024)
+0x9C70, 0x942F, 0x940F, 0x838D, 0x7B4C, 0x93EE, 0xACF3, 0xA4B2, 0x93EF, 0x8BCE, 0x83AD, 0xA492, 0x9C70, 0x8BCD, 0x93EE, 0x940F,   // 0x32F0 (13040)
+0x83AD, 0x83AE, 0x9C31, 0x838E, 0x838D, 0x9C92, 0xA4D3, 0xA4D4, 0xB557, 0xC5D9, 0xD63A, 0xCE3A, 0xBDB8, 0x9451, 0x6B0A, 0x5248,   // 0x3300 (13056)
+0x3165, 0x28E3, 0x4A07, 0x7B8D, 0x9C72, 0xA4F4, 0x9C93, 0x738D, 0x6B0B, 0x734C, 0x734C, 0x7BAE, 0x8C30, 0x8C30, 0x7BAE, 0x736D,   // 0x3310 (13072)
+0x734C, 0x7B6C, 0x83EF, 0x8C10, 0x8C51, 0x9472, 0x9473, 0x9CB3, 0xA4F4, 0xA4D4, 0xB535, 0x83F1, 0x8C52, 0x83F1, 0x7BF1, 0x7BF1,   // 0x3320 (13088)
+0x83F1, 0x8411, 0x7BD0, 0x7BD0, 0x7BF0, 0x7BF0, 0x7BCF, 0x73AF, 0x73AF, 0x7BCF, 0x7BCF, 0x7BD0, 0x83F1, 0x8411, 0x8411, 0x8411,   // 0x3330 (13104)
+0x8431, 0x8C52, 0x9452, 0x8C52, 0x8C52, 0x9493, 0x8C73, 0x8C73, 0x9CD5, 0x9452, 0x6B2C, 0x41E7, 0x39C6, 0x39C6, 0x39C6, 0x41E7,   // 0x3340 (13120)
+0x41E7, 0x5AAA, 0x83D0, 0xAD15, 0xC5D9, 0xCE7B, 0xD67B, 0xD69B, 0xBDB8, 0x838E, 0x3985, 0x3164, 0x3145, 0x20A2, 0x1040, 0x2903,   // 0x3350 (13136)
+0x5247, 0x734B, 0x8BEF, 0xB556, 0xBD97, 0xCDF8, 0xE6DC, 0xEF3D, 0xF77E, 0xEF1D, 0xDEBB, 0xE6FC, 0xD67B, 0xC5D8, 0xA4B1, 0x8BCD,   // 0x3360 (13152)
+0x9C70, 0xA4B2, 0x9C91, 0x9450, 0x9C71, 0xB535, 0xB514, 0xACD3, 0x9C72, 0xA493, 0xA4B3, 0xA4D3, 0xACF4, 0xB535, 0xCE18, 0xD65A,   // 0x3370 (13168)
+0xCDD7, 0xC596, 0xB4F4, 0xACD2, 0xACD3, 0xACF3, 0xA4D2, 0x93EE, 0x940F, 0xB534, 0xB514, 0x9C30, 0x9C51, 0xAD14, 0xBD75, 0xB534,   // 0x3380 (13184)
+0xA492, 0x93EF, 0x7B6C, 0x6AEA, 0x7B2B, 0x83AD, 0xA492, 0xA4B4, 0x9CB2, 0xA4F4, 0xAD15, 0xAD15, 0xB536, 0xBDB8, 0xCE19, 0xBDD8,   // 0x3390 (13200)
+0x83CF, 0x734D, 0x5A8A, 0x5269, 0x5A8A, 0x62EB, 0x7B8D, 0x9472, 0x9451, 0x8BF0, 0x738D, 0x6B2C, 0x5268, 0x62EA, 0x9471, 0xA4D3,   // 0x33A0 (13216)
+0x9452, 0x7BAE, 0x736D, 0x7BAE, 0x8BEF, 0x8C31, 0x8C51, 0x9471, 0x9452, 0x9493, 0xA4D4, 0xA515, 0x9CD4, 0xACF4, 0x8411, 0x8C52,   // 0x33B0 (13232)
+0x83F1, 0x83F1, 0x83F1, 0x83F1, 0x83F1, 0x83F1, 0x7BF1, 0x7BF0, 0x83F0, 0x7BF0, 0x7BD0, 0x7BB0, 0x7BD0, 0x7BCF, 0x7BD0, 0x8411,   // 0x33C0 (13248)
+0x8431, 0x8C32, 0x9473, 0x9493, 0x9494, 0x9474, 0x9494, 0x9494, 0x9494, 0x9494, 0x9493, 0x9493, 0x8C32, 0x8C32, 0x83F1, 0x630C,   // 0x33D0 (13264)
+0x5289, 0x4A69, 0x4228, 0x4A49, 0x4A49, 0x5249, 0x6B2C, 0x9453, 0xB536, 0xC5F9, 0xCE3A, 0xB556, 0x83AE, 0x62EA, 0x5A68, 0x2903,   // 0x33E0 (13280)
+0x1041, 0x1081, 0x18C2, 0x3144, 0x5227, 0x5268, 0x732C, 0x8BEF, 0xC5D8, 0xE6DC, 0xE71D, 0xEEFD, 0xDE9B, 0xE6BC, 0xEF1E, 0xE6DC,   // 0x33F0 (13296)
+0xBD96, 0x9C4F, 0x9C50, 0x9C71, 0xA4B2, 0xA4D3, 0xA4B2, 0xBD76, 0xCDF9, 0xCE19, 0xCDF9, 0xBD98, 0xC5B8, 0xCDF8, 0xC5D8, 0xCE19,   // 0x3400 (13312)
+0xCDF8, 0xD65A, 0xDE9B, 0xD65A, 0xDE7B, 0xD659, 0xD659, 0xD659, 0xD67A, 0xCDF7, 0xBD75, 0xB534, 0xC596, 0xCE39, 0xC5D7, 0xBD96,   // 0x3410 (13328)
+0xC5B7, 0xCDD8, 0xB514, 0xA4B2, 0xA492, 0x838D, 0x732B, 0x9451, 0xA4F4, 0x9452, 0x9452, 0xA4B4, 0xA4F5, 0xBDB8, 0xBDD8, 0xB536,   // 0x3420 (13344)
+0xA4B4, 0xA4F5, 0xC5F9, 0xC5D8, 0x62EC, 0x5289, 0x5248, 0x62CB, 0x83EF, 0xA4D4, 0xA4D4, 0x8C31, 0x83EF, 0x83CF, 0x736D, 0x62CB,   // 0x3430 (13360)
+0x734C, 0xA4D2, 0xB534, 0xA4D4, 0x8C31, 0x7BAE, 0x83CF, 0x8C10, 0x8C51, 0x9452, 0x9472, 0x9472, 0x9C93, 0x9C93, 0x9CB3, 0x9C93,   // 0x3440 (13376)
+0xA515, 0x8411, 0x9493, 0x8411, 0x8432, 0x8C32, 0x8411, 0x8411, 0x8C32, 0x8432, 0x8411, 0x8411, 0x8411, 0x83F1, 0x7BD0, 0x7BD0,   // 0x3450 (13392)
+0x7BD0, 0x7BD0, 0x7BF1, 0x8411, 0x8431, 0x8C52, 0x9493, 0x9C93, 0x9493, 0x9473, 0x9493, 0xA4F5, 0xA516, 0x9CF6, 0x9494, 0x9452,   // 0x3460 (13408)
+0x9CB4, 0xAD57, 0xB578, 0xA515, 0x8C31, 0x734D, 0x62EC, 0x5269, 0x5A8A, 0x62EC, 0x6B0C, 0x83CF, 0xACF6, 0xBD98, 0xC5D9, 0xBDB9,   // 0x3470 (13424)
+0xACF5, 0x736D, 0x3164, 0x18A2, 0x1882, 0x1041, 0x0820, 0x0821, 0x1061, 0x41C7, 0x9C72, 0xCDF9, 0xCE39, 0xCE18, 0xC5D8, 0xCDF8,   // 0x3480 (13440)
+0xE6FC, 0xE71D, 0xDE9B, 0xCDF8, 0xB555, 0xB514, 0x9C71, 0xACF4, 0xACD3, 0xB4F4, 0xBD56, 0xCDF8, 0xCE3A, 0xD63A, 0xD65A, 0xD65A,   // 0x3490 (13456)
+0xD65A, 0xD63A, 0xD67B, 0xD67B, 0xDE7B, 0xDEBC, 0xDEBC, 0xDE9B, 0xE6BC, 0xE6DC, 0xE6FC, 0xE6DC, 0xDE9B, 0xD65A, 0xCDF9, 0xC5D7,   // 0x34A0 (13472)
+0xCE38, 0xDE9B, 0xD639, 0xB555, 0xC597, 0xB515, 0x940F, 0xA492, 0xA4B3, 0xA4D4, 0xAD36, 0xB557, 0xA516, 0x83F0, 0x7BAF, 0x8C11,   // 0x34B0 (13488)
+0x83D0, 0x7BAF, 0x8C31, 0x9473, 0x736D, 0x5AAA, 0x9452, 0xB557, 0x8411, 0x83F0, 0x83CF, 0x83EF, 0x8BF0, 0x8C31, 0x7BAE, 0x5AAA,   // 0x34C0 (13504)
+0x5268, 0x62CA, 0x6B2B, 0x83AD, 0xACF3, 0xBD76, 0xB556, 0xA4F4, 0x8C31, 0x8C31, 0x9472, 0x9472, 0x9C93, 0x9CB3, 0xA4D4, 0x9CD4,   // 0x34D0 (13520)
+0x9C93, 0x9CB3, 0x9CB3, 0xB535, 0x8411, 0x9493, 0x8C52, 0x8C52, 0x8C52, 0x8C32, 0x8C52, 0x8C52, 0x8C32, 0x8432, 0x8432, 0x8C32,   // 0x34E0 (13536)
+0x8432, 0x8411, 0x8411, 0x8411, 0x8411, 0x8411, 0x8411, 0x8411, 0x8411, 0x8C32, 0x9473, 0x9C93, 0x9C93, 0x9C93, 0x9CB4, 0xAD37,   // 0x34F0 (13552)
+0xBDB9, 0xC5FA, 0xC61B, 0xCE5B, 0xDEBD, 0xDEDE, 0xDEBD, 0xD67B, 0xC5FA, 0xA4D4, 0x732C, 0x5248, 0x5269, 0x5268, 0x6B0B, 0x9452,   // 0x3500 (13568)
+0xB577, 0xC5FA, 0xCE3A, 0xBD98, 0x8C10, 0x6B0B, 0x5268, 0x28E3, 0x0820, 0x1082, 0x20E3, 0x39A6, 0x6B2C, 0x7B8F, 0x83F0, 0x9431,   // 0x3510 (13584)
+0x9C92, 0xA4B3, 0xCE19, 0xD67A, 0xDE9B, 0xCE5A, 0xCE1A, 0xC5D9, 0xBD56, 0xBD77, 0xACF5, 0xA492, 0xB514, 0xB535, 0xBD97, 0xC5D8,   // 0x3520 (13600)
+0xCE19, 0xD65A, 0xD67B, 0xCE3A, 0xD65A, 0xD65A, 0xDE9C, 0xDE9C, 0xDE9C, 0xE6DC, 0xDE7B, 0xD65A, 0xDE9B, 0xDEBB, 0xDE7A, 0xE6BB,   // 0x3530 (13616)
+0xDE7A, 0xC5B7, 0xBD97, 0xCE19, 0xC5D8, 0xC5B8, 0xB556, 0x9C71, 0xB556, 0x9CB3, 0x8BF0, 0x9C93, 0xACF5, 0xA4D5, 0x9432, 0x9CB4,   // 0x3540 (13632)
+0xB537, 0xA4F5, 0x83F1, 0x62CC, 0x62EB, 0x5A8A, 0x5ACA, 0x736E, 0x736E, 0x6AEC, 0x9472, 0xB577, 0xA4F5, 0x9472, 0x9452, 0x83CF,   // 0x3550 (13648)
+0x62EB, 0x5AAA, 0x62CB, 0x62AA, 0x62AA, 0x6AEA, 0x7B6C, 0xA4B3, 0xBD97, 0xB556, 0xA4F4, 0x9452, 0x9452, 0x9CB3, 0x9CB3, 0x9C93,   // 0x3560 (13664)
+0xA4B3, 0xA4D4, 0x9CD3, 0xA4B4, 0xA4D4, 0xA4F4, 0xB556, 0x83F1, 0x9473, 0x8C52, 0x8C52, 0x8C32, 0x8C32, 0x8432, 0x8411, 0x83F1,   // 0x3570 (13680)
+0x83F1, 0x8411, 0x8411, 0x8411, 0x83F1, 0x83F0, 0x8C11, 0x8411, 0x8411, 0x8431, 0x8C32, 0x8411, 0x8C32, 0x9473, 0x9C93, 0x9473,   // 0x3580 (13696)
+0x9C94, 0xA4D5, 0xA4F6, 0xB577, 0xC5F9, 0xC63B, 0xD67C, 0xDEDD, 0xDEDD, 0xDEFD, 0xDEFD, 0xDEDD, 0xD67C, 0xBD98, 0x83D0, 0x62EB,   // 0x3590 (13712)
+0x5AAA, 0x5269, 0x5AA9, 0x630B, 0x83EF, 0xA4D4, 0xAD37, 0xAD37, 0xAD36, 0x9CB4, 0x736D, 0x3145, 0x20C3, 0x18A2, 0x18A2, 0x1881,   // 0x35A0 (13728)
+0x2903, 0x3985, 0x4A07, 0x732B, 0xACD3, 0xA4D3, 0xBD76, 0xBD77, 0xAD15, 0xB556, 0xAD15, 0xD65B, 0xBD98, 0x9CB3, 0xA4F4, 0xBD56,   // 0x35B0 (13744)
+0xB536, 0xB556, 0xB556, 0xBD97, 0xD63A, 0xCE3A, 0xCE3A, 0xD63A, 0xD65A, 0xDE9B, 0xDEBC, 0xD67B, 0xE6BC, 0xD63A, 0xCDF9, 0xD639,   // 0x35C0 (13760)
+0xD65A, 0xD65A, 0xCE3A, 0xB536, 0xBD77, 0xB556, 0xC5B9, 0xACF5, 0x9431, 0x9451, 0x9C72, 0x8BEF, 0x9C72, 0x83CF, 0x83CF, 0x9C72,   // 0x35D0 (13776)
+0x9CB3, 0x7B6D, 0x5A89, 0x62EC, 0x8C11, 0xA4D5, 0xB557, 0xB557, 0x9CB4, 0x736E, 0x5ACB, 0x5AAA, 0x62CB, 0x6B2D, 0x736E, 0x83F0,   // 0x35E0 (13792)
+0x7BAF, 0x7BCF, 0x83F0, 0x7B8E, 0x5AAA, 0x62EB, 0x6B2C, 0x6B0B, 0x62CA, 0x62CA, 0x83CE, 0xA4D4, 0xA4F4, 0x8C30, 0x9C72, 0xA4B4,   // 0x35F0 (13808)
+0xA4B3, 0xA4B4, 0x9C93, 0x9451, 0x9C72, 0x9CB3, 0xA4B3, 0xA4D4, 0xA4D4, 0xB535, 0x83D0, 0x8C52, 0x8C31, 0x8C31, 0x8411, 0x8411,   // 0x3600 (13824)
+0x8411, 0x7BF0, 0x7BD0, 0x7BD0, 0x7BF1, 0x7BF0, 0x7BF0, 0x7BD0, 0x7BD0, 0x83F0, 0x83F0, 0x7BF0, 0x83F1, 0x8C32, 0x8C32, 0x8C32,   // 0x3610 (13840)
+0x9473, 0x9CB4, 0x9CB4, 0x9C94, 0xA516, 0xBD98, 0xC61A, 0xCE5B, 0xCE7B, 0xCE5B, 0xD69B, 0xD6BB, 0xDEDC, 0xE71D, 0xE71D, 0xE71D,   // 0x3620 (13856)
+0xDEBC, 0xAD36, 0x62CA, 0x2903, 0x1881, 0x10A2, 0x0861, 0x2944, 0x5269, 0x6B2C, 0x9432, 0xAD38, 0xA4B4, 0x732C, 0x5AA9, 0x41E6,   // 0x3630 (13872)
+0x1061, 0x18A1, 0x3985, 0x3164, 0x2923, 0x39A5, 0x7B8C, 0x9450, 0x83CE, 0x9430, 0x83AE, 0x9410, 0x83AE, 0x9451, 0xCE3B, 0xA4D4,   // 0x3640 (13888)
+0x9C93, 0xBD97, 0xBDB7, 0xC5B7, 0xBD97, 0xBD77, 0xBD77, 0xCE3A, 0xC5B8, 0xCDF9, 0xCE19, 0xD65A, 0xD69B, 0xD65B, 0xD67B, 0xD65A,   // 0x3650 (13904)
+0xCE3A, 0xBD77, 0xBD97, 0xC5D9, 0xC5D8, 0xB556, 0x9472, 0x9451, 0x9430, 0x9432, 0x9C93, 0x9C92, 0x8C10, 0x9C93, 0xAD15, 0xBD97,   // 0x3660 (13920)
+0xC5D8, 0xBDB8, 0xBD76, 0xA4D4, 0xA4D3, 0x6B2C, 0x4A07, 0x41E6, 0x4A48, 0x62CB, 0x8BF0, 0xBD98, 0xC61A, 0xBD98, 0x9472, 0x6B0C,   // 0x3670 (13936)
+0x62EB, 0x736E, 0x5269, 0x39C7, 0x39A6, 0x3165, 0x4207, 0x5AAA, 0x62EB, 0x5AAA, 0x62EB, 0x62EA, 0x5AA9, 0x5AA9, 0x734C, 0x7BAE,   // 0x3680 (13952)
+0x6B2C, 0x9451, 0xAD15, 0xAD15, 0xACF4, 0xA4D4, 0x9C71, 0x8C30, 0x9451, 0x9C93, 0xA4D4, 0xA4D4, 0xB555, 0x83D0, 0x8C31, 0x83F0,   // 0x3690 (13968)
+0x83F0, 0x83D0, 0x7BF0, 0x7BD0, 0x7BCF, 0x7BCF, 0x7BD0, 0x7BF0, 0x7BD0, 0x7BD0, 0x7BAF, 0x7BAF, 0x7BCF, 0x7BCF, 0x73AF, 0x73B0,   // 0x36A0 (13984)
+0x7BF1, 0x8431, 0x9452, 0x9C93, 0xA4D4, 0xA4D4, 0xA4F5, 0xAD37, 0xBDD9, 0xCE3B, 0xCE5B, 0xCE5B, 0xD69C, 0xDEBC, 0xDEFC, 0xE6FD,   // 0x36B0 (14000)
+0xE71D, 0xE73D, 0xE73E, 0xE71D, 0xDEBC, 0xACF5, 0x5228, 0x1041, 0x0000, 0x0000, 0x0020, 0x0000, 0x2944, 0x5ACB, 0x8C52, 0x9C93,   // 0x36C0 (14016)
+0xA4F5, 0x9472, 0x5A88, 0x5A68, 0x6B0B, 0x62CA, 0x62EB, 0x6B0B, 0x6B2B, 0x9452, 0x9C92, 0x9451, 0x7B8E, 0x7B6D, 0x730B, 0x62C9,   // 0x36D0 (14032)
+0x9472, 0xACF6, 0x9432, 0x9C94, 0xBD98, 0xC5F9, 0xCE5A, 0xBDB8, 0xC5F9, 0xBD97, 0xCE19, 0xBD98, 0xBD98, 0xCE19, 0xD65B, 0xD65A,   // 0x36E0 (14048)
+0xCE1A, 0xD67B, 0xCE19, 0xC5D8, 0xBD97, 0xB576, 0xB536, 0xB536, 0xA4D4, 0x83F0, 0x734C, 0x5AAA, 0x8C11, 0xB536, 0xCE19, 0xCE19,   // 0x36F0 (14064)
+0xCE19, 0xC5B6, 0xAD13, 0xACF3, 0xACF4, 0xB555, 0xCDF8, 0xDE7A, 0xD65A, 0xB535, 0x734D, 0x3165, 0x20E3, 0x3164, 0x6AEB, 0xBD76,   // 0x3700 (14080)
+0xD67B, 0xD67B, 0xC5F9, 0xAD16, 0x9C94, 0x8C32, 0x5AAA, 0x2103, 0x1061, 0x0800, 0x2944, 0x5AAA, 0x5AAA, 0x5269, 0x4A28, 0x5268,   // 0x3710 (14096)
+0x41E6, 0x2923, 0x6B0B, 0x83CF, 0x9451, 0xA4D3, 0xACF4, 0xACF4, 0xA4D3, 0xA4B2, 0x9C92, 0xA4D3, 0xA4D4, 0xA4D4, 0xACF4, 0xB555,   // 0x3720 (14112)
+0x83D0, 0x83F0, 0x7BAF, 0x7BAF, 0x73AF, 0x73AF, 0x7BAF, 0x7BF0, 0x7BF0, 0x7BD0, 0x7BCF, 0x7BD0, 0x7BCF, 0x7BAF, 0x7BCF, 0x73AF,   // 0x3730 (14128)
+0x738F, 0x73AF, 0x7BB0, 0x7BD0, 0x8411, 0x8C32, 0x9473, 0x9CB4, 0xA4D4, 0x9CD5, 0xA4F5, 0xA4F6, 0xB537, 0xC5D9, 0xC5FA, 0xCE5B,   // 0x3740 (14144)
+0xD69B, 0xDEDC, 0xDEFC, 0xDEDC, 0xDEDC, 0xDEFC, 0xE71D, 0xEF5E, 0xE73E, 0xD67B, 0x9CB4, 0x5AAA, 0x2923, 0x0000, 0x0841, 0x2965,   // 0x3750 (14160)
+0x5289, 0x6B6E, 0x9494, 0xA4D6, 0x9473, 0x9431, 0x9C93, 0x9CB4, 0xAD15, 0xAD15, 0x83EF, 0x8C10, 0xA4B4, 0xBDB8, 0xBD98, 0x9C71,   // 0x3760 (14176)
+0x8C10, 0x5A89, 0x62C9, 0x7B8E, 0x83F0, 0x83AF, 0x8C11, 0xAD16, 0xB577, 0xBDB8, 0xB577, 0xB556, 0xBD97, 0xC5F9, 0xC5B8, 0xBD98,   // 0x3770 (14192)
+0xC5F9, 0xCE3A, 0xD65A, 0xC5F9, 0xCE19, 0xC5F9, 0xBDB8, 0xBDB8, 0xBD97, 0xAD16, 0xA4D5, 0x9473, 0x7BCE, 0x7B6D, 0x9C73, 0xBDB7,   // 0x3780 (14208)
+0xC5F8, 0xC5D7, 0xCE18, 0xD618, 0xB534, 0x9410, 0x730A, 0x730B, 0x6B0A, 0x9C70, 0xCE18, 0xD65A, 0xD65A, 0xBDB7, 0x83F0, 0x3986,   // 0x3790 (14224)
+0x3965, 0x41A5, 0x62A9, 0xAD14, 0xC5D9, 0xCE1A, 0xCE3B, 0xC5D9, 0xA4D5, 0x83F1, 0x5ACB, 0x41E7, 0x4A08, 0x5AAA, 0x630B, 0x6B2C,   // 0x37A0 (14240)
+0x4207, 0x18A2, 0x5269, 0x4A28, 0x0841, 0x39A6, 0x7B8E, 0x9451, 0xACF4, 0xAD15, 0xAD15, 0xA4D4, 0xA4F4, 0xA4D4, 0xACF4, 0xAD15,   // 0x37B0 (14256)
+0xAD15, 0xACF5, 0xB536, 0x7BD0, 0x7BF0, 0x736E, 0x738E, 0x738E, 0x738E, 0x7BAF, 0x7BAF, 0x7BD0, 0x7BD0, 0x7BD0, 0x7BCF, 0x7BCF,   // 0x37C0 (14272)
+0x7BAF, 0x73AF, 0x7B8F, 0x738F, 0x7BD0, 0x83F1, 0x83F1, 0x83F1, 0x8C32, 0x9452, 0x9473, 0x9C93, 0x9493, 0x8C31, 0x6B2C, 0x5289,   // 0x37D0 (14288)
+0x62CB, 0x9451, 0xBDB7, 0xC63A, 0xD67B, 0xDEBC, 0xDEDC, 0xDEDC, 0xDEDC, 0xDEFD, 0xE71D, 0xEF3E, 0xEF5E, 0xDEBD, 0xA4F5, 0x5AEA,   // 0x37E0 (14304)
+0x3165, 0x2124, 0x2103, 0x18C2, 0x10A2, 0x5AEB, 0x9473, 0xA4D5, 0xAD36, 0xAD58, 0xAD58, 0xBDDA, 0x9CD4, 0x9C73, 0xAD57, 0xCE3B,   // 0x37F0 (14320)
+0xDEDD, 0xD65A, 0xB556, 0xA4B3, 0x734C, 0x83CF, 0x7B8D, 0x7B8D, 0x7B8D, 0x9431, 0x9C73, 0x9C73, 0xA4B4, 0xB556, 0xA4D4, 0xA4F5,   // 0x3800 (14336)
+0xBDB8, 0xC5F9, 0xC5F9, 0xCE19, 0xD65A, 0xCE3A, 0xBDB8, 0xC5D9, 0xC5F9, 0xC5F9, 0xBD98, 0xB578, 0xA4D4, 0x8C52, 0x9493, 0x83F0,   // 0x3810 (14352)
+0xACF4, 0xCDD8, 0x9C71, 0x8BAD, 0x942F, 0xB554, 0xD638, 0xCE18, 0xA4B2, 0x940F, 0x734C, 0x4A06, 0x6AA9, 0x8BEE, 0xB514, 0xC5B7,   // 0x3820 (14368)
+0xCDF8, 0xC5B8, 0x9451, 0x4A07, 0x3144, 0x41A5, 0x8BEE, 0xA4B3, 0xB577, 0xCE3A, 0xCE3A, 0xB598, 0x9474, 0x738E, 0x6B2D, 0x6B2C,   // 0x3830 (14384)
+0x7BAE, 0x7BAF, 0x6B4D, 0x630C, 0x2944, 0x7B8E, 0x5249, 0x18A1, 0x4A28, 0x7B8E, 0x9C93, 0xAD35, 0xAD15, 0xACF5, 0xAD16, 0xAD15,   // 0x3840 (14400)
+0xA4D4, 0xAD15, 0xB536, 0xAD15, 0xAD15, 0xBD56, 0x8410, 0x8431, 0x738E, 0x738E, 0x736E, 0x738E, 0x7BAF, 0x7BAF, 0x7BAF, 0x7BAF,   // 0x3850 (14416)
+0x7BAF, 0x7B8F, 0x7BAF, 0x73AF, 0x73AF, 0x7BAF, 0x7BAF, 0x83F0, 0x8411, 0x8C31, 0x8411, 0x8C32, 0x9452, 0x9452, 0x83F0, 0x5269,   // 0x3860 (14432)
+0x4228, 0x31A6, 0x0861, 0x0000, 0x18C2, 0x4A27, 0x7B6D, 0xA4D4, 0xCE5A, 0xDEDC, 0xDEDC, 0xE71D, 0xE71D, 0xE71D, 0xE71D, 0xE71D,   // 0x3870 (14448)
+0xE6FD, 0xD69C, 0xB598, 0xA4D5, 0x632C, 0x2944, 0x18C3, 0x2124, 0x2965, 0x4228, 0x5AAA, 0x8C33, 0x8C33, 0xA4F6, 0x9473, 0x9473,   // 0x3880 (14464)
+0xB558, 0xCE5B, 0xD69C, 0xE71E, 0xDEBC, 0xD65B, 0xB537, 0xA4B3, 0xA4B4, 0x9C73, 0x7B8E, 0x83EF, 0x9432, 0x8C12, 0x83EF, 0xA4D4,   // 0x3890 (14480)
+0xA4D5, 0xACF5, 0xA4F5, 0xBD98, 0xCE1A, 0xD65B, 0xD65A, 0xCE3A, 0xCE19, 0xBDB8, 0xC5F9, 0xCE19, 0xC5F9, 0xB578, 0xB557, 0x9452,   // 0x38A0 (14496)
+0x8C11, 0x8C31, 0xAD16, 0xBDB8, 0xA4B2, 0x83AD, 0x7B4C, 0xA491, 0xBD54, 0xCDF8, 0xD618, 0xC596, 0xBD75, 0xA4B2, 0x8BCE, 0x6ACA,   // 0x38B0 (14512)
+0x5207, 0x62A9, 0x9C70, 0xBD76, 0xD63A, 0xC5D9, 0x8C31, 0x4A28, 0x2923, 0x6B0B, 0xA4D3, 0xA4B4, 0xAD36, 0xCE3A, 0xCE3A, 0xB577,   // 0x38C0 (14528)
+0xA4F5, 0x9452, 0x7BAF, 0x6B4D, 0x62CB, 0x6B2C, 0x83F0, 0x5269, 0x9452, 0x9452, 0x736D, 0x8C10, 0x9C93, 0xACF5, 0xB535, 0xAD15,   // 0x38D0 (14544)
+0xAD15, 0xACF5, 0xACF5, 0xACF5, 0xACF4, 0xAD15, 0xB536, 0xB535, 0xC5B8, 0x8410, 0x8C31, 0x7BAE, 0x7BAE, 0x736E, 0x73AE, 0x7BCF,   // 0x38E0 (14560)
+0x7BD0, 0x7BD0, 0x7BD0, 0x7BAF, 0x736E, 0x738F, 0x738F, 0x7BAF, 0x83F0, 0x83D0, 0x83F1, 0x8C11, 0x8C31, 0x8C11, 0x83F1, 0x8C11,   // 0x38F0 (14576)
+0x7BCF, 0x6B4D, 0x39E7, 0x18C3, 0x2945, 0x0861, 0x0020, 0x0000, 0x0000, 0x0840, 0x3164, 0x734D, 0xB556, 0xD65A, 0xDE9C, 0xDEDD,   // 0x3900 (14592)
+0xDEDD, 0xE71E, 0xEF3E, 0xE71D, 0xDEFD, 0xE6FD, 0xD67C, 0xAD57, 0x7BAF, 0x4207, 0x0861, 0x0020, 0x0020, 0x18C3, 0x2104, 0x5ACB,   // 0x3910 (14608)
+0x630C, 0x5289, 0x9473, 0xB599, 0xCE3B, 0xCE5B, 0xD6BC, 0xDEDD, 0xDEFD, 0xCDFA, 0xBD98, 0xB578, 0xAD36, 0x9472, 0x8C10, 0x9C94,   // 0x3920 (14624)
+0x8C32, 0x8C32, 0x9CB4, 0xA4D5, 0xAD36, 0xB557, 0xBDB8, 0xD63B, 0xD67B, 0xD65B, 0xCE1A, 0xBDB9, 0xC5F9, 0xC5F9, 0xCE3A, 0xB578,   // 0x3930 (14640)
+0xB557, 0x9CB4, 0x7BAF, 0x62CA, 0xA4B3, 0xCE3A, 0xAD34, 0x8C0E, 0x8BCE, 0x9C50, 0xB555, 0xC596, 0xB514, 0x940E, 0x836C, 0x8BCE,   // 0x3940 (14656)
+0xACD2, 0xC5B7, 0xBD75, 0x83EF, 0x41E6, 0x4185, 0x8C0F, 0xB554, 0xBD97, 0xC5B9, 0x9CD4, 0x4A48, 0x20C2, 0x6B2B, 0x9C92, 0xA4B3,   // 0x3950 (14672)
+0xBD77, 0xD65B, 0xCE1A, 0xAD16, 0x7B8E, 0x4A48, 0x4A48, 0x41E7, 0x5269, 0x8C31, 0x9472, 0xAD16, 0xBD77, 0xB557, 0xB556, 0xBD77,   // 0x3960 (14688)
+0xB536, 0xB536, 0xB557, 0xB556, 0xACF5, 0xACF5, 0xACF5, 0xACF5, 0xACF5, 0xAD15, 0xB535, 0xC598, 0x83EF, 0x8C30, 0x7BCF, 0x7BF0,   // 0x3970 (14704)
+0x7BD0, 0x7BAF, 0x7BAF, 0x7BAF, 0x7BCF, 0x7BD0, 0x7BCF, 0x738F, 0x738E, 0x6B6E, 0x73AF, 0x7BF0, 0x8411, 0x8C32, 0x9452, 0x9453,   // 0x3980 (14720)
+0x8C32, 0x8C12, 0x83F1, 0x630C, 0x41E7, 0x5289, 0x4A48, 0x528A, 0x3185, 0x0820, 0x0000, 0x0021, 0x0861, 0x0000, 0x0820, 0x2904,   // 0x3990 (14736)
+0x6B0C, 0x9472, 0xAD35, 0xBDB8, 0xCE3A, 0xD69C, 0xDEDD, 0xDEDD, 0xDEDD, 0xD69C, 0xBDFA, 0x9CB5, 0x5AAA, 0x18C2, 0x0020, 0x0020,   // 0x39A0 (14752)
+0x0020, 0x0000, 0x2945, 0x18C3, 0x3185, 0x9C93, 0x9C94, 0xAD37, 0xB599, 0xBDD9, 0xE6FD, 0xE6FD, 0xDEBD, 0xC61A, 0xBDB9, 0xB598,   // 0x39B0 (14768)
+0xAD37, 0x8C52, 0x9CB4, 0x9494, 0x9CB4, 0x9CB4, 0xA4F6, 0xAD17, 0xB558, 0xBDB9, 0xCE3A, 0xD69C, 0xD65B, 0xC5F9, 0xB577, 0xC5F9,   // 0x39C0 (14784)
+0xC5D9, 0xC5FA, 0xAD16, 0x9432, 0x7BAF, 0x6B2C, 0x8BF0, 0xC5D8, 0xBD96, 0x9CB2, 0x83CE, 0x8BCE, 0x942F, 0xACF3, 0xBD75, 0xB535,   // 0x39D0 (14800)
+0xA491, 0x8C0F, 0x83EF, 0x7B8E, 0x9410, 0xC596, 0xBD97, 0xA4D4, 0x6AEB, 0x41E6, 0x734C, 0x9C92, 0xACF4, 0xAD36, 0x9CB3, 0x4A49,   // 0x39E0 (14816)
+0x4206, 0x83EF, 0x8C31, 0x9C93, 0xBD78, 0xCE1A, 0xCE1A, 0x8C30, 0x3164, 0x3165, 0x62AA, 0x83AF, 0x9C93, 0xACF5, 0xAD15, 0xB536,   // 0x39F0 (14832)
+0xB556, 0xAD15, 0xB556, 0xB536, 0xAD15, 0xAD16, 0xB536, 0xB536, 0xAD16, 0xACF5, 0xAD16, 0xB536, 0xB536, 0xB536, 0xC598, 0x83EF,   // 0x3A00 (14848)
+0x8C31, 0x83F0, 0x83F0, 0x83F0, 0x7BD0, 0x73AF, 0x738E, 0x738F, 0x7BAF, 0x7BAF, 0x73AF, 0x73AF, 0x738F, 0x738F, 0x7BF0, 0x8411,   // 0x3A10 (14864)
+0x8C32, 0x9C93, 0x9C93, 0x9453, 0x8C52, 0x9453, 0x7BAF, 0x62EB, 0x83D0, 0x9C93, 0x9CB3, 0xA4F4, 0x630B, 0x1081, 0x0000, 0x0000,   // 0x3A20 (14880)
+0x0000, 0x0000, 0x0000, 0x0000, 0x10A2, 0x2944, 0x4207, 0x5A89, 0x83CF, 0xB577, 0xCE3A, 0xDEBC, 0xDEBC, 0xD67C, 0xBDB9, 0x7BAF,   // 0x3A30 (14896)
+0x2924, 0x0000, 0x0000, 0x0000, 0x0020, 0x10A3, 0x0000, 0x18C3, 0x7BAF, 0x736E, 0x8411, 0x9494, 0xA516, 0xD67B, 0xDEBD, 0xD67C,   // 0x3A40 (14912)
+0xCE3B, 0xBDD9, 0xAD78, 0xAD57, 0x9CB5, 0x9474, 0xA517, 0x8C74, 0xA516, 0xB558, 0xAD37, 0xBDB9, 0xBD98, 0xC61A, 0xD67B, 0xCE5B,   // 0x3A50 (14928)
+0xC5D9, 0xBD98, 0xCDFA, 0xC5D9, 0xAD16, 0x738E, 0x5ACA, 0x734D, 0x83CF, 0xBD76, 0xC5B7, 0xB555, 0xBD56, 0xB534, 0x8BCE, 0x6B0A,   // 0x3A60 (14944)
+0x83AD, 0x838C, 0x942F, 0x9C91, 0xACF3, 0xB534, 0xA4B2, 0x8BEF, 0x838D, 0xB534, 0xD67A, 0xCDF9, 0x9C92, 0x5228, 0x20C2, 0x4A07,   // 0x3A70 (14960)
+0x736D, 0x9472, 0x8C31, 0x4227, 0x5269, 0x7BCF, 0x7B8E, 0x83D0, 0x9CB3, 0xAD16, 0xA4D5, 0x7BAF, 0x62EB, 0x7B8E, 0x9C72, 0xA4D4,   // 0x3A80 (14976)
+0xA4D4, 0xACF4, 0xB536, 0xB536, 0xB536, 0xB535, 0xB556, 0xB557, 0xB556, 0xB536, 0xB557, 0xB557, 0xAD16, 0xAD16, 0xB536, 0xB556,   // 0x3A90 (14992)
+0xB556, 0xC5B8, 0x83EF, 0x8C51, 0x83D0, 0x83D0, 0x83D0, 0x7BD0, 0x7BCF, 0x73AF, 0x738E, 0x738F, 0x738F, 0x73AF, 0x73AF, 0x73AF,   // 0x3AA0 (15008)
+0x73AF, 0x83F1, 0x8C11, 0x8C32, 0x9453, 0x9CB4, 0x9473, 0x9452, 0x9452, 0x9CB4, 0xA4F5, 0xAD36, 0xB577, 0xC5D8, 0xC5F9, 0xBD96,   // 0x3AB0 (15024)
+0x732C, 0x2924, 0x18C2, 0x0861, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0000, 0x0000, 0x1061, 0x5289, 0x8C51, 0xBDB8, 0xD6BC,   // 0x3AC0 (15040)
+0xD67C, 0xC61B, 0x9CD4, 0x4207, 0x0841, 0x0841, 0x0000, 0x0841, 0x0020, 0x0000, 0x0861, 0x2965, 0x2944, 0x5269, 0x630C, 0x83F1,   // 0x3AD0 (15056)
+0xAD36, 0xC5FA, 0xBDD9, 0xC61A, 0xC5FA, 0xA516, 0x8C54, 0x8C33, 0x8412, 0xA517, 0x9CD6, 0xA517, 0xBDB9, 0xB598, 0xC5FA, 0xC5D9,   // 0x3AE0 (15072)
+0xC61A, 0xD67B, 0xCE3A, 0xBD98, 0xBDB9, 0xC5D9, 0xB558, 0x8C31, 0x5ACA, 0x6B2C, 0x4A28, 0x7B8E, 0xB556, 0xBD56, 0xBD76, 0xBD75,   // 0x3AF0 (15088)
+0xACF3, 0x9C71, 0x83AE, 0x83AD, 0x83CD, 0x9C50, 0x9C71, 0xACD3, 0xB514, 0xAD14, 0xA4B2, 0x9430, 0xA4B2, 0xCE19, 0xD63A, 0xCE19,   // 0x3B00 (15104)
+0xB556, 0x734C, 0x5AA9, 0x4A06, 0x5248, 0x9471, 0x8411, 0x3186, 0x4A48, 0x83D0, 0x732D, 0x6B2B, 0x734C, 0x83D0, 0x8C32, 0x9452,   // 0x3B10 (15120)
+0x9C93, 0xA4B3, 0xAD14, 0xA4F4, 0xA4B4, 0xAD15, 0xB556, 0xBD77, 0xBD77, 0xB557, 0xB557, 0xBD77, 0xB557, 0xB536, 0xAD16, 0xAD16,   // 0x3B20 (15136)
+0xB536, 0xB556, 0xB557, 0xB556, 0xC5B8, 0x8410, 0x8C52, 0x83F0, 0x83F0, 0x83F0, 0x7BF0, 0x7BCF, 0x73AF, 0x73AF, 0x738F, 0x738F,   // 0x3B30 (15152)
+0x738F, 0x7BAF, 0x7BAE, 0x7BAE, 0x7BCF, 0x8C11, 0x8C31, 0x8C32, 0x9C93, 0x9C93, 0x9473, 0x9CB4, 0xB578, 0xBDB9, 0xBD98, 0xBDB8,   // 0x3B40 (15168)
+0xC5D8, 0xCDF9, 0xC5D7, 0xACF3, 0x734B, 0x5247, 0x3165, 0x0841, 0x0000, 0x0020, 0x1082, 0x0020, 0x0000, 0x0000, 0x0000, 0x10A1,   // 0x3B50 (15184)
+0x4207, 0xA4F5, 0xDEBD, 0xD67C, 0xCE5C, 0xA515, 0x5ACA, 0x3164, 0x3165, 0x0861, 0x0020, 0x0000, 0x0020, 0x1082, 0x0841, 0x0020,   // 0x3B60 (15200)
+0x1061, 0x39A6, 0x39C6, 0x5ACB, 0x9CD5, 0xB598, 0xAD58, 0xB578, 0x9CF6, 0x7BB1, 0x738F, 0x7390, 0x7BD0, 0xA4F7, 0xB578, 0xAD58,   // 0x3B70 (15216)
+0xB578, 0xBDB9, 0xBDD9, 0xBDB9, 0xC61A, 0xBDFA, 0xAD78, 0xBD99, 0xAD16, 0x9453, 0x738E, 0x7BAE, 0x734E, 0x62CB, 0x9451, 0xB555,   // 0x3B80 (15232)
+0xBD96, 0xBD56, 0xBD75, 0xB514, 0xB535, 0xB514, 0xBD54, 0xBD95, 0xB535, 0xB535, 0xAD14, 0x942F, 0x7B6C, 0x838D, 0x7B6C, 0x8BEF,   // 0x3B90 (15248)
+0xA4B2, 0xC5D8, 0xD65A, 0xDE9B, 0xD65B, 0xBDB7, 0x83CF, 0x5AA9, 0x7BCE, 0xA4F5, 0x7BB0, 0x4A49, 0x6B2C, 0x7BAF, 0x6B0C, 0x5ACA,   // 0x3BA0 (15264)
+0x630C, 0x7BD0, 0x9452, 0xA4D4, 0xAD16, 0xB536, 0xB536, 0xB556, 0xBD77, 0xB556, 0xAD15, 0xB536, 0xBD77, 0xAD15, 0xB536, 0xB536,   // 0x3BB0 (15280)
+0xAD15, 0xAD15, 0xAD16, 0xAD16, 0xB536, 0xB556, 0xB536, 0xC5B8, 0x8410, 0x9472, 0x8411, 0x8411, 0x8411, 0x83F0, 0x7BD0, 0x738F,   // 0x3BC0 (15296)
+0x73AF, 0x7BAF, 0x738F, 0x738F, 0x738E, 0x738E, 0x738E, 0x7BD0, 0x8C31, 0x8C31, 0x8C11, 0x9452, 0x9C93, 0x9CD4, 0xA516, 0xB577,   // 0x3BD0 (15312)
+0xB557, 0xB557, 0xBD97, 0xBDB8, 0xC5D9, 0xBDB7, 0xA4D3, 0x8BEF, 0x5268, 0x20E3, 0x10A2, 0x0841, 0x0861, 0x0841, 0x0000, 0x0000,   // 0x3BE0 (15328)
+0x0000, 0x0000, 0x0000, 0x0841, 0x7BAF, 0xD69C, 0xD69C, 0xD67C, 0xAD57, 0x83F0, 0x5ACA, 0x5289, 0x18A2, 0x0000, 0x0000, 0x0000,   // 0x3BF0 (15344)
+0x0020, 0x0020, 0x0000, 0x0000, 0x2904, 0x2103, 0x39C6, 0x6B2C, 0xA4F6, 0xAD58, 0x9CB5, 0x8412, 0x630D, 0x4A69, 0x52AB, 0x632E,   // 0x3C00 (15360)
+0x83F2, 0xA517, 0x9CD6, 0xAD58, 0xAD57, 0xAD38, 0xA517, 0xAD37, 0xB578, 0xA517, 0xAD17, 0x83F1, 0x6B2D, 0x5AAA, 0x83CF, 0x9C72,   // 0x3C10 (15376)
+0xACD3, 0xA4B3, 0x9C70, 0x9C70, 0x9C50, 0xA4B2, 0x9C51, 0x9C50, 0xACF2, 0xBD75, 0xC575, 0xB534, 0xB535, 0xB514, 0xB514, 0x9C51,   // 0x3C20 (15392)
+0x83CE, 0x8BEF, 0x9C71, 0x8C0F, 0xA4D3, 0xC5D8, 0xD67A, 0xE6FD, 0xDE9C, 0xB577, 0x83F0, 0x9472, 0xAD36, 0xAD15, 0x7BD0, 0x5289,   // 0x3C30 (15408)
+0x5289, 0x62EA, 0x736E, 0x736E, 0x8C31, 0xAD15, 0xB556, 0xB556, 0xB556, 0xB556, 0xB556, 0xB556, 0xB536, 0xAD15, 0xACF5, 0xB536,   // 0x3C40 (15424)
+0xB556, 0xB556, 0xB536, 0xAD15, 0xACF5, 0xACF5, 0xAD15, 0xAD15, 0xAD15, 0xAD15, 0xBD98, 0x8431, 0x8C52, 0x7BF0, 0x8410, 0x8411,   // 0x3C50 (15440)
+0x8410, 0x7BF0, 0x7BCF, 0x7BCF, 0x7BCF, 0x7BCF, 0x7BCF, 0x738E, 0x73AE, 0x7BD0, 0x83F1, 0x8C11, 0x83D0, 0x7B8F, 0x83F0, 0x9472,   // 0x3C60 (15456)
+0xA4F5, 0xAD36, 0xB557, 0xAD16, 0xAD15, 0xB556, 0xBDB8, 0xBDD8, 0xC5F9, 0xC5B8, 0xB535, 0x8BEE, 0x39A5, 0x1061, 0x18A2, 0x0020,   // 0x3C70 (15472)
+0x0000, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x630C, 0xCE1B, 0xDEBC, 0xCE5B, 0xB578, 0x9C95, 0x8C32, 0x736E, 0x3165,   // 0x3C80 (15488)
+0x0020, 0x0000, 0x0000, 0x0020, 0x0000, 0x0000, 0x0840, 0x20E3, 0x2944, 0x4207, 0x39A6, 0x738E, 0xA4F6, 0x8C74, 0x4A6A, 0x31C7,   // 0x3C90 (15504)
+0x2965, 0x2985, 0x39E7, 0x5AEC, 0x7390, 0x5AEC, 0xA517, 0x9474, 0x8432, 0x8C33, 0xA4B6, 0xA4F6, 0x9CB4, 0x8411, 0x6B2C, 0x5AAA,   // 0x3CA0 (15520)
+0x736E, 0x9C92, 0xB534, 0xBD55, 0xC5B6, 0xB534, 0x944F, 0x9C90, 0xA4B1, 0xACF3, 0xB533, 0xB534, 0xBD54, 0xBD33, 0xBD13, 0xBD33,   // 0x3CB0 (15536)
+0xACB2, 0x8BCD, 0x942F, 0x9C50, 0xACF4, 0xC596, 0xBD55, 0xAD14, 0xA4D3, 0xBD97, 0xD65B, 0xDEBC, 0xD67B, 0xB557, 0x8C11, 0x9CB3,   // 0x3CC0 (15552)
+0xAD36, 0x83F0, 0x6B4D, 0x5ACA, 0x5288, 0x6B4C, 0x8C51, 0x9C93, 0xAD15, 0xB557, 0xBD77, 0xB557, 0xB536, 0xB557, 0xBD77, 0xB557,   // 0x3CD0 (15568)
+0xB557, 0xB556, 0xB536, 0xBD77, 0xB557, 0xB536, 0xAD16, 0xAD16, 0xAD15, 0xAD15, 0xB536, 0xB556, 0xB536, 0xC5B8, 0x8C32, 0x8C72,   // 0x3CE0 (15584)
+0x8410, 0x8411, 0x8411, 0x7BF1, 0x7BF0, 0x8411, 0x8411, 0x8431, 0x8411, 0x7BF0, 0x7BAF, 0x7BCF, 0x8410, 0x8C32, 0x9453, 0x83D0,   // 0x3CF0 (15600)
+0x526A, 0x630C, 0x7BAF, 0x83D0, 0x8C32, 0x9C94, 0x9CB4, 0x9452, 0x9472, 0x9CD3, 0xBDB8, 0xCE1A, 0xCE19, 0xCE1A, 0xBDB8, 0x9430,   // 0x3D00 (15616)
+0x5A89, 0x41E6, 0x2924, 0x1081, 0x0881, 0x0041, 0x0000, 0x0000, 0x0000, 0x0000, 0x4208, 0xB578, 0xD69C, 0xC61B, 0xB578, 0xAD57,   // 0x3D10 (15632)
+0xA516, 0x9494, 0x4A49, 0x1081, 0x0000, 0x0020, 0x0020, 0x0000, 0x0020, 0x0840, 0x20E3, 0x2924, 0x41E7, 0x39A6, 0x5A89, 0x8411,   // 0x3D20 (15648)
+0x73B1, 0x2966, 0x0841, 0x1082, 0x31C6, 0x2123, 0x2945, 0x4A69, 0x2966, 0x73B0, 0x6B4E, 0x632D, 0x738F, 0x8C73, 0x9474, 0x7BD0,   // 0x3D30 (15664)
+0x5289, 0x41E7, 0x630C, 0x9C93, 0xB534, 0xB512, 0xACD2, 0xBD34, 0xC596, 0xC575, 0xBD74, 0xB534, 0xB533, 0xBD53, 0xB512, 0xACB1,   // 0x3D40 (15680)
+0xA470, 0xAC90, 0xBD32, 0xB512, 0xB513, 0xC575, 0xC575, 0xC575, 0xC575, 0xBD54, 0xBD76, 0xC5B7, 0xC5F8, 0xCE19, 0xD63A, 0xDE7B,   // 0x3D50 (15696)
+0xCE1A, 0x9CB4, 0x8C31, 0xA4D5, 0x9C94, 0x6B2D, 0x6B2C, 0x62EB, 0x736D, 0x9451, 0x9C73, 0xA4D4, 0xB536, 0xBD77, 0xB557, 0xB557,   // 0x3D60 (15712)
+0xBD97, 0xC5B7, 0xBD97, 0xB557, 0xB557, 0xBD77, 0xB557, 0xB556, 0xB536, 0xB536, 0xB536, 0xB536, 0xB536, 0xB556, 0xB557, 0xB557,   // 0x3D70 (15728)
+0xC5B8, 0x8411, 0x8C73, 0x8431, 0x7BF1, 0x7BF1, 0x8411, 0x8411, 0x7BF1, 0x8411, 0x8411, 0x7BF0, 0x7BCF, 0x7B8F, 0x7BCF, 0x8411,   // 0x3D80 (15744)
+0x9452, 0x9473, 0x8C11, 0x738E, 0x6B4D, 0x62EC, 0x5ACC, 0x6B0D, 0x6B2D, 0x6B4D, 0x5269, 0x2923, 0x41E7, 0x732C, 0xA4B3, 0xAD35,   // 0x3D90 (15760)
+0xAD15, 0xB556, 0xC5B8, 0xB556, 0x9472, 0x8C10, 0x734D, 0x41E7, 0x0000, 0x0000, 0x0020, 0x0000, 0x0000, 0x2944, 0xAD16, 0xCE3B,   // 0x3DA0 (15776)
+0xC61A, 0xBDB9, 0xBDD9, 0xBDB9, 0xB578, 0x630C, 0x18C2, 0x0841, 0x0841, 0x0841, 0x0020, 0x0841, 0x1041, 0x20C3, 0x20C2, 0x3185,   // 0x3DB0 (15792)
+0x4A49, 0x3986, 0x5269, 0x4A49, 0x2985, 0x18E3, 0x2103, 0x4A48, 0x4228, 0x41E7, 0x4A28, 0x5269, 0x5269, 0x41E7, 0x52AB, 0x630C,   // 0x3DC0 (15808)
+0x738F, 0x83F1, 0x6B2D, 0x4227, 0x5289, 0x83F0, 0xAD34, 0xACF2, 0x9C71, 0xBD33, 0xBD33, 0xB4F2, 0xB4F2, 0xBD54, 0xB512, 0xB511,   // 0x3DD0 (15824)
+0x940D, 0x836B, 0x8BAD, 0x8BCE, 0x834B, 0x9C0E, 0xB512, 0xBD33, 0xBD33, 0xB4F2, 0x942E, 0x93EE, 0xA470, 0xB534, 0xC5B7, 0xCDF8,   // 0x3DE0 (15840)
+0xC5D7, 0xCDF8, 0xCDF9, 0xCE1A, 0xAD36, 0x9452, 0x9C73, 0x83D0, 0x7B8E, 0x6B2C, 0x83F0, 0x9472, 0x9C93, 0x9C73, 0xA4D4, 0xB536,   // 0x3DF0 (15856)
+0xB556, 0xBD77, 0xC5B8, 0xC5B7, 0xBD77, 0xBD97, 0xBD77, 0xBD77, 0xB556, 0xB515, 0xBD77, 0xB556, 0xAD16, 0xAD16, 0xB536, 0xB556,   // 0x3E00 (15872)
+0xB557, 0xBD77, 0xB557, 0xBD98, 0x8411, 0x8C52, 0x7BF0, 0x7BD0, 0x7BF1, 0x8411, 0x83F1, 0x7BD0, 0x83F1, 0x83F1, 0x7BD0, 0x7BAF,   // 0x3E10 (15888)
+0x7BAF, 0x83F0, 0x8C31, 0x9473, 0x9453, 0x9453, 0xA4F5, 0x9473, 0x630C, 0x39A6, 0x18C3, 0x2945, 0x3165, 0x3165, 0x39A6, 0x4207,   // 0x3E20 (15904)
+0x41C6, 0x5A48, 0x732C, 0x734C, 0x83CE, 0x9C71, 0xB556, 0xC5D8, 0xBD97, 0xB557, 0x9493, 0x2924, 0x0000, 0x0020, 0x0020, 0x0000,   // 0x3E30 (15920)
+0x18C3, 0xA4D5, 0xCE3B, 0xC63B, 0xC61A, 0xCE5C, 0xC61B, 0xBDDA, 0x6B4E, 0x31A5, 0x2103, 0x0821, 0x18A3, 0x1061, 0x0841, 0x1882,   // 0x3E40 (15936)
+0x20C3, 0x20A2, 0x20E3, 0x3185, 0x20E3, 0x1081, 0x31A5, 0x4A69, 0x4A28, 0x5ACA, 0x736D, 0x734D, 0x6B4C, 0x734E, 0x738E, 0x630C,   // 0x3E50 (15952)
+0x5268, 0x6B4E, 0x6B0D, 0x62EC, 0x736E, 0x736E, 0x5ACA, 0x6B4C, 0x9451, 0xACF3, 0xA491, 0xACF3, 0x9C70, 0x83AC, 0x7B4B, 0x7B6C,   // 0x3E60 (15968)
+0x8BAD, 0xA470, 0xAC90, 0x8BCC, 0x7B4B, 0x9C30, 0xA491, 0x940F, 0x7AEA, 0xA44F, 0xA490, 0x93CD, 0x93EE, 0x940E, 0x8BCD, 0x836C,   // 0x3E70 (15984)
+0x9C2F, 0xB534, 0xBD55, 0xBD75, 0xB555, 0xBD97, 0xCE1A, 0xC5D9, 0xA4D5, 0x9C93, 0x8C31, 0x83CF, 0x83CF, 0x9452, 0xA4D5, 0xAD16,   // 0x3E80 (16000)
+0xA4F4, 0xA4D4, 0xAD15, 0xB536, 0xBD77, 0xBD98, 0xC5B8, 0xBD97, 0xBD98, 0xBD97, 0xC5D8, 0xBD56, 0xB4F4, 0xBD77, 0xB536, 0xACF5,   // 0x3E90 (16016)
+0xACF5, 0xAD16, 0xAD16, 0xB536, 0xB556, 0xB536, 0xC5D9, 0x8411, 0x9CB4, 0x8C51, 0x8C52, 0x9473, 0x8C52, 0x8C52, 0x8C52, 0x8C52,   // 0x3EA0 (16032)
+0x8C52, 0x8432, 0x8411, 0x8C31, 0x9493, 0x9C93, 0xA4F5, 0xBD98, 0xC5B9, 0xC5D8, 0xB577, 0xB556, 0x9492, 0x5268, 0x3185, 0x4208,   // 0x3EB0 (16048)
+0x630D, 0x8411, 0x8C51, 0x8C10, 0x83CE, 0x83AE, 0x942F, 0x9CB2, 0xAD14, 0xBD76, 0xC5D7, 0xD63A, 0xCE19, 0xCE3A, 0x8C31, 0x18E3,   // 0x3EC0 (16064)
+0x0020, 0x0020, 0x0861, 0x18E3, 0xAD36, 0xDEBD, 0xDEDE, 0xDEDE, 0xE71E, 0xDEDE, 0xD67D, 0x7BD0, 0x39A6, 0x39C6, 0x1881, 0x20E3,   // 0x3ED0 (16080)
+0x18C2, 0x1061, 0x1861, 0x2903, 0x2924, 0x18C2, 0x1061, 0x18E3, 0x20E3, 0x4A48, 0x738D, 0x83CF, 0x9CB3, 0xACF5, 0xAD15, 0xAD36,   // 0x3EE0 (16096)
+0xAD16, 0xAD16, 0xA4D5, 0xA4D5, 0xA4F5, 0x9472, 0x9451, 0x9452, 0x8C31, 0x9492, 0xAD15, 0xB576, 0xB534, 0xBD54, 0xB513, 0xA4B1,   // 0x3EF0 (16112)
+0x9C90, 0x9C90, 0x9C70, 0x9C2F, 0xA450, 0x93ED, 0x8BAC, 0xA490, 0xB513, 0xB4F3, 0xA470, 0x72C9, 0x72C9, 0x8BED, 0x836B, 0x93EE,   // 0x3F00 (16128)
+0x9C4F, 0xA490, 0x9C50, 0x8BCE, 0x9C4F, 0xC575, 0xD5F8, 0xCDD7, 0xC5B7, 0xD63B, 0xCDFA, 0xAD36, 0x9473, 0x9C93, 0xAD16, 0xAD35,   // 0x3F10 (16144)
+0xB536, 0xBD77, 0xC5B8, 0xBD97, 0xB536, 0xB557, 0xBD98, 0xC5D9, 0xCDF9, 0xCE19, 0xCE1A, 0xD63A, 0xD63A, 0xD63A, 0xD619, 0xCDD9,   // 0x3F20 (16160)
+};
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap_128x128/UTFT_Bitmap_128x128.pde b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap_128x128/UTFT_Bitmap_128x128.pde
new file mode 100644
index 0000000..1d10e99
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap_128x128/UTFT_Bitmap_128x128.pde	
@@ -0,0 +1,50 @@
+// UTFT_Bitmap_128x128 (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the drawBitmap()-function.
+//
+// This demo was made to work on the 128x128 modules.
+// Any other size displays may cause strange behaviour.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+#include 
+
+UTFT myGLCD(LPH9135,6,5,2,3,4);   // Remember to change the model parameter to suit your display module!
+
+extern unsigned int icon1[0x400];
+extern unsigned int icon2[0x400];
+extern unsigned int tux[0x1000];
+
+void setup()
+{
+  myGLCD.InitLCD(PORTRAIT);
+}
+
+void loop()
+{
+// Draw a 4 by 4 grid of a 32x32 icon.
+  myGLCD.fillScr(255, 255, 255);
+  for (int x=0; x<4; x++)
+    for (int y=0; y<4; y++)
+      myGLCD.drawBitmap (x*32, y*32, 32, 32, icon1);
+
+  delay(5000);
+  
+// Draw a 64x64 icon in double size.
+  myGLCD.fillScr(255, 255, 255);
+  myGLCD.drawBitmap (0, 0, 64, 64, tux, 2);
+
+  delay(5000);
+
+// Draw a 2 by 2 grid of a 32x32 icon in double size.
+  myGLCD.fillScr(255, 255, 255);
+  for (int x=0; x<2; x++)
+    for (int y=0; y<2; y++)
+      myGLCD.drawBitmap (x*64, y*64, 32, 32, icon2, 2);
+
+  delay(5000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap_128x128/icon1.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap_128x128/icon1.c
new file mode 100644
index 0000000..f85ff85
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap_128x128/icon1.c	
@@ -0,0 +1,74 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: exit.png
+// Time generated: 14.10.2010 21:53:03
+// Dimensions    : 32x32 pixels
+// Size          : 2 048 Bytes
+
+#include 
+
+prog_uint16_t icon1[0x400] PROGMEM ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF1C, 0xE618, 0xE638, 0xE638, 0xE638, 0xE659, 0xE659, 0xE659, 0xE659, 0xE659, 0xE679, 0xE679,   // 0x0010 (16)
+0xE679, 0xE679, 0xE679, 0xE679, 0xEE79, 0xEE9A, 0xEE9A, 0xEE9A, 0xEE9A, 0xEE9A, 0xE638, 0xEEBA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xD555, 0xCCD3, 0xDDB6, 0xDDD7, 0xDDF7, 0xDDF7, 0xDE18, 0xE618, 0xE638, 0xE638, 0xE659, 0xE679, 0xE679,   // 0x0030 (48)
+0xEE9A, 0xEE9A, 0xEEBA, 0xEEBA, 0xEEBA, 0xEEDB, 0xEEDB, 0xEEFB, 0xEEFB, 0xEEFB, 0xEEFB, 0xE659, 0xD575, 0xF77D, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFDF, 0xFFFF, 0xD534, 0xC471, 0xD575, 0xCCF3, 0xCCD3, 0xCCD3, 0xCCF3, 0xCCF3, 0xD4F3, 0xD514, 0xD514, 0xD514, 0xD534, 0xDD55,   // 0x0050 (80)
+0xDD55, 0xDD55, 0xDD55, 0xDD75, 0xDD75, 0xDD75, 0xDD96, 0xDD96, 0xDD96, 0xDDB6, 0xDDD7, 0xEE79, 0xEEBA, 0xD534, 0xFFBE, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xEEDB, 0xB38E, 0xC4B2, 0xBC30, 0xC451, 0xC471, 0xC471, 0xCC71, 0xCC92, 0xCC92, 0xCC92, 0xCCB2, 0xD4B2, 0xD4B2, 0xCC71,   // 0x0070 (112)
+0xCC71, 0xD4D3, 0xD4F3, 0xDCF3, 0xDCF3, 0xDD14, 0xDD14, 0xDD14, 0xDD34, 0xDD34, 0xDD34, 0xDD14, 0xE5D7, 0xDD96, 0xDDF7, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xC4F3, 0xAB2C, 0xC430, 0xC410, 0xC430, 0xC430, 0xC430, 0xCC51, 0xCC51, 0xCC51, 0xCC71, 0xCC71, 0xD471, 0xCC71, 0xD5F7,   // 0x0090 (144)
+0xD5F7, 0xCC92, 0xDCB2, 0xDCD3, 0xDCD3, 0xDCD3, 0xDCD3, 0xDCF3, 0xDCF3, 0xDD14, 0xDD14, 0xDD34, 0xDD14, 0xDD34, 0xC492, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xB3EF, 0x9A28, 0xC430, 0xBBCF, 0xC3EF, 0xC3EF, 0xC3EF, 0xC410, 0xCC10, 0xCC10, 0xCC30, 0xCC51, 0xCBEF, 0xE638, 0xFFFF,   // 0x00B0 (176)
+0xFFFF, 0xE659, 0xD430, 0xDC92, 0xDC92, 0xDC92, 0xDCB2, 0xDCB2, 0xDCB2, 0xDCD3, 0xDCD3, 0xDCD3, 0xE514, 0xD410, 0xAB0C, 0xF7FF,   // 0x00C0 (192)
+0xFFFF, 0xABCF, 0x9165, 0xC3EF, 0xBB8E, 0xBBAE, 0xC3AE, 0xC3CF, 0xC3CF, 0xCBCF, 0xCBEF, 0xCC10, 0xCC10, 0xCBAE, 0xEE9A, 0xFFFF,   // 0x00D0 (208)
+0xFFFF, 0xF6DB, 0xD410, 0xDC71, 0xDC71, 0xDC71, 0xDC71, 0xDC71, 0xDC71, 0xE492, 0xE492, 0xE492, 0xE4F3, 0xCB2C, 0xA249, 0xF7FF,   // 0x00E0 (224)
+0xFFFF, 0xABCF, 0x88C3, 0xC3AE, 0xBB4D, 0xBB6D, 0xC36D, 0xC38E, 0xC38E, 0xCBAE, 0xC36D, 0xC34D, 0xCBCF, 0xCB8E, 0xEE59, 0xFFFF,   // 0x00F0 (240)
+0xFFFF, 0xF6BA, 0xDBCF, 0xD3CF, 0xCBAE, 0xD3CF, 0xE430, 0xE430, 0xE451, 0xE451, 0xE451, 0xE451, 0xECD3, 0xCAAA, 0xA208, 0xF7FF,   // 0x0100 (256)
+0xFFFF, 0xABCF, 0x8061, 0xBB6D, 0xBB2C, 0xBB2C, 0xC34D, 0xC34D, 0xCB4D, 0xBB0C, 0xC492, 0xCD14, 0xC38E, 0xCB2C, 0xEE59, 0xFFFF,   // 0x0110 (272)
+0xFFFF, 0xF6BA, 0xD36D, 0xD575, 0xE6DB, 0xDDB6, 0xD3AE, 0xE3EF, 0xE410, 0xE410, 0xE430, 0xE410, 0xECB2, 0xC986, 0xA208, 0xF7FF,   // 0x0120 (288)
+0xFFFF, 0xB3EF, 0x8041, 0xBB0C, 0xBAEB, 0xBAEB, 0xC30C, 0xC30C, 0xBACB, 0xD5B6, 0xFFFF, 0xFFFF, 0xEE79, 0xCACB, 0xEE59, 0xFFFF,   // 0x0130 (304)
+0xFFFF, 0xF679, 0xDBEF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEEBA, 0xD3CF, 0xE3AE, 0xE3EF, 0xE3CF, 0xEC10, 0xEB6D, 0xC000, 0xA249, 0xF7FF,   // 0x0140 (320)
+0xFFFF, 0xB3EF, 0x8020, 0xBACB, 0xBAAA, 0xBAAA, 0xC2EB, 0xBA8A, 0xD596, 0xFFFF, 0xFFDF, 0xFFFF, 0xF73C, 0xCAAA, 0xEE38, 0xFFFF,   // 0x0150 (336)
+0xFFFF, 0xF679, 0xDB4D, 0xFF7D, 0xFFFF, 0xFFDF, 0xFFFF, 0xEEDB, 0xDB6D, 0xEB8E, 0xEBAE, 0xEB8E, 0xE0A2, 0xC800, 0xAA49, 0xF7FF,   // 0x0160 (352)
+0xFFFF, 0xB3EF, 0x8000, 0xB28A, 0xBA69, 0xBA8A, 0xBA49, 0xCC30, 0xFFFF, 0xFFDF, 0xFFFF, 0xFF5D, 0xDBCF, 0xCA69, 0xEE18, 0xFFFF,   // 0x0170 (368)
+0xFFFF, 0xF679, 0xDAAA, 0xE3AE, 0xF6BA, 0xFFFF, 0xFFDF, 0xFFFF, 0xE5D7, 0xE30C, 0xEB8E, 0xE0E3, 0xE000, 0xC800, 0xAA49, 0xF7FF,   // 0x0180 (384)
+0xFFFF, 0xB3EF, 0x8800, 0xB249, 0xBA49, 0xBA49, 0xBA49, 0xEF1C, 0xFFFF, 0xFFFF, 0xFF7D, 0xD32C, 0xCA69, 0xD249, 0xEDF7, 0xFFFF,   // 0x0190 (400)
+0xFFFF, 0xF659, 0xDAAA, 0xE2CB, 0xE2EB, 0xFEBA, 0xFFFF, 0xFFDF, 0xFFDF, 0xE3CF, 0xE103, 0xE000, 0xE081, 0xD000, 0xAA69, 0xF7FF,   // 0x01A0 (416)
+0xFFFF, 0xB3EF, 0x8800, 0xB228, 0xBA08, 0xB9A6, 0xCBAE, 0xFFFF, 0xFFDF, 0xFFFF, 0xDC30, 0xC9E7, 0xD28A, 0xCA08, 0xF618, 0xFFFF,   // 0x01B0 (432)
+0xFFFF, 0xF679, 0xDA49, 0xE2CB, 0xE28A, 0xEB6D, 0xFFBE, 0xFFDF, 0xFFFF, 0xEC92, 0xE000, 0xE0A2, 0xE0C2, 0xD040, 0xAA89, 0xF7FF,   // 0x01C0 (448)
+0xFFFF, 0xB3EF, 0x8800, 0xB1E7, 0xB9E7, 0xB165, 0xDD55, 0xFFFF, 0xFFFF, 0xF71C, 0xCA08, 0xCA08, 0xD228, 0xD1E7, 0xE430, 0xFFDF,   // 0x01D0 (464)
+0xFFDF, 0xEC51, 0xDA08, 0xE28A, 0xE28A, 0xE228, 0xF618, 0xFFFF, 0xFFFF, 0xF679, 0xE081, 0xE0C2, 0xE903, 0xD081, 0xAA89, 0xF7FF,   // 0x01E0 (480)
+0xFFFF, 0xBBEF, 0x9000, 0xB1A6, 0xB986, 0xB145, 0xEE38, 0xFFFF, 0xFFFF, 0xED96, 0xC165, 0xC9E7, 0xD1E7, 0xD1E7, 0xD1C7, 0xDACB,   // 0x01F0 (496)
+0xE2EB, 0xD9E7, 0xE228, 0xE228, 0xEA69, 0xE9E7, 0xF40F, 0xFFFF, 0xFFFF, 0xFF5D, 0xE144, 0xE8E2, 0xE943, 0xD8C1, 0xAA8A, 0xF7FF,   // 0x0200 (512)
+0xFFFF, 0xBC10, 0x9000, 0xB165, 0xB145, 0xB924, 0xEE9A, 0xFFFF, 0xFFFF, 0xE514, 0xC124, 0xC9A6, 0xD1A6, 0xD1A6, 0xD1C7, 0xD9A6,   // 0x0210 (528)
+0xD9A6, 0xE1E7, 0xE208, 0xE208, 0xE9A6, 0xE041, 0xEA8A, 0xFFFF, 0xFFFF, 0xFF9E, 0xE9C6, 0xE902, 0xE984, 0xD902, 0xAAAA, 0xF7FF,   // 0x0220 (544)
+0xFFFF, 0xC410, 0x9000, 0xB124, 0xB124, 0xB0C3, 0xEE18, 0xFFFF, 0xFFFF, 0xE575, 0xC0E3, 0xC986, 0xD165, 0xD165, 0xD986, 0xD9A6,   // 0x0230 (560)
+0xD9A6, 0xE1A6, 0xE165, 0xE082, 0xE020, 0xE000, 0xEB4C, 0xFFFF, 0xFFFF, 0xFF7D, 0xE9A5, 0xE943, 0xE9A5, 0xD923, 0xAAAA, 0xF7FF,   // 0x0240 (576)
+0xFFFF, 0xC410, 0x9800, 0xB0E3, 0xB0E3, 0xB061, 0xE4F3, 0xFFFF, 0xFFFF, 0xF6FB, 0xC104, 0xC924, 0xD145, 0xD145, 0xD945, 0xD945,   // 0x0250 (592)
+0xD8E3, 0xD861, 0xD800, 0xE000, 0xE061, 0xE000, 0xED34, 0xFFFF, 0xFFFF, 0xFE9A, 0xE923, 0xE984, 0xE9C5, 0xE163, 0xAAAA, 0xF7FF,   // 0x0260 (608)
+0xFFFF, 0xC410, 0xA000, 0xB0A2, 0xB0A2, 0xB041, 0xCACB, 0xFFFF, 0xFFDF, 0xFFFF, 0xD34D, 0xC841, 0xD104, 0xD0A2, 0xD061, 0xD000,   // 0x0270 (624)
+0xD800, 0xD800, 0xE000, 0xE041, 0xE000, 0xD965, 0xFF9E, 0xFFDF, 0xFFFF, 0xF4D2, 0xE8E2, 0xE9A5, 0xE9E5, 0xE183, 0xAAAA, 0xF7FF,   // 0x0280 (640)
+0xFFFF, 0xCC10, 0xA000, 0xA861, 0xB061, 0xB061, 0xB882, 0xF6DB, 0xFFFF, 0xFFDF, 0xF75D, 0xC124, 0xC800, 0xD000, 0xD000, 0xD800,   // 0x0290 (656)
+0xD800, 0xE000, 0xE020, 0xE000, 0xD861, 0xF638, 0xFFFF, 0xFFDF, 0xFFDF, 0xEA68, 0xE943, 0xE9C5, 0xEA06, 0xE1A4, 0xB2CA, 0xF7FF,   // 0x02A0 (672)
+0xFFFF, 0xCC10, 0xA000, 0xA820, 0xB000, 0xB000, 0xB000, 0xCA49, 0xFFFF, 0xFFDF, 0xFFFF, 0xF71C, 0xCA08, 0xC800, 0xD000, 0xD800,   // 0x02B0 (688)
+0xD800, 0xD800, 0xD800, 0xD944, 0xEE18, 0xFFFF, 0xFFBE, 0xFFFF, 0xF4F2, 0xE902, 0xE9A5, 0xE9C5, 0xEA06, 0xE9A4, 0xB2CA, 0xF7FF,   // 0x02C0 (704)
+0xFFFF, 0xD410, 0xA800, 0xA800, 0xB000, 0xB000, 0xB800, 0xB800, 0xDC10, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xED96, 0xDAEB, 0xD1A6,   // 0x02D0 (720)
+0xD965, 0xDA69, 0xECD3, 0xFF9E, 0xFFFF, 0xFFBE, 0xFFFF, 0xFE17, 0xE923, 0xE964, 0xE9A5, 0xE9C5, 0xEA26, 0xE9C4, 0xBACA, 0xF7FF,   // 0x02E0 (736)
+0xF7FF, 0xD410, 0xA800, 0xA800, 0xB000, 0xB000, 0xB800, 0xB800, 0xB800, 0xE3EF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02F0 (752)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF5B6, 0xE923, 0xE923, 0xE984, 0xE9A5, 0xE9E5, 0xEA26, 0xE9C5, 0xBACA, 0xF7FF,   // 0x0300 (768)
+0xF7FF, 0xDC10, 0xB000, 0xA800, 0xB000, 0xB000, 0xB800, 0xB800, 0xC000, 0xC000, 0xD228, 0xF638, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0310 (784)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFEFB, 0xF3AE, 0xE0C1, 0xE903, 0xE964, 0xE984, 0xE9A5, 0xE9E5, 0xEA26, 0xE9E5, 0xC2CA, 0xF7DF,   // 0x0320 (800)
+0xF7FF, 0xDC51, 0xB800, 0xA800, 0xB000, 0xB000, 0xB800, 0xB800, 0xC000, 0xC000, 0xC000, 0xC800, 0xD9E7, 0xEC30, 0xF5D7, 0xFE9A,   // 0x0330 (816)
+0xFEBA, 0xF618, 0xF4D3, 0xEACB, 0xE0E2, 0xE040, 0xE903, 0xE943, 0xE943, 0xE984, 0xE9A5, 0xE9E5, 0xEA26, 0xEA05, 0xC30C, 0xF7DF,   // 0x0340 (832)
+0xFFFF, 0xD575, 0xD104, 0xA820, 0xB000, 0xB800, 0xB800, 0xC000, 0xC000, 0xC000, 0xC820, 0xC800, 0xD000, 0xD000, 0xD800, 0xD800,   // 0x0350 (848)
+0xE000, 0xE000, 0xE000, 0xE000, 0xE0A1, 0xE0E3, 0xE903, 0xE943, 0xE964, 0xE984, 0xE9C5, 0xE9C5, 0xF226, 0xE227, 0xBC10, 0xF7FF,   // 0x0360 (864)
+0xFFFF, 0xDF3C, 0xCAAA, 0xD186, 0xB082, 0xB000, 0xB800, 0xB800, 0xB800, 0xC000, 0xC000, 0xC800, 0xC800, 0xD000, 0xD000, 0xD800,   // 0x0370 (880)
+0xD800, 0xE000, 0xE020, 0xE040, 0xE061, 0xE0A1, 0xE0C2, 0xE102, 0xE123, 0xE943, 0xE984, 0xEA26, 0xFB0A, 0xBA08, 0xCE38, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFDF, 0xBDD7, 0xCA69, 0xE248, 0xD207, 0xD1C6, 0xD1C6, 0xD9C7, 0xD9C7, 0xE1C7, 0xE1C7, 0xE1C7, 0xE9C7, 0xE9C7, 0xE9C7,   // 0x0390 (912)
+0xF1C6, 0xF1C7, 0xF1E7, 0xF207, 0xF228, 0xF248, 0xF269, 0xF289, 0xF2A9, 0xF2CA, 0xFB0A, 0xF2EA, 0xC207, 0xACB3, 0xF7BE, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xF7BE, 0xBDF7, 0xAB8E, 0xC2EB, 0xC2EB, 0xC30B, 0xC30B, 0xC30B, 0xC30B, 0xC30B, 0xC30B, 0xC30B, 0xCB0B, 0xCAEB,   // 0x03B0 (944)
+0xCAEB, 0xCACA, 0xCACA, 0xCAAA, 0xCAAA, 0xCA8A, 0xCA69, 0xC269, 0xC269, 0xC289, 0xBA69, 0xA2CB, 0xAD34, 0xEF7D, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xDF3C, 0xBE39, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7,   // 0x03D0 (976)
+0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xBE38, 0xD71C, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap_128x128/icon2.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap_128x128/icon2.c
new file mode 100644
index 0000000..3713257
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap_128x128/icon2.c	
@@ -0,0 +1,74 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: video.png
+// Time generated: 14.10.2010 21:53:17
+// Dimensions    : 32x32 pixels
+// Size          : 2 048 Bytes
+
+#include 
+
+prog_uint16_t icon2[0x400] PROGMEM ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0010 (16)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE71C, 0xB5B6, 0x94B2, 0x8C71,   // 0x0030 (48)
+0x9492, 0xA534, 0xD6BA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF5D, 0x9CF3, 0x73AE, 0x6B6D, 0x73AE, 0x7BCF,   // 0x0050 (80)
+0x7BEF, 0x7BCF, 0x7BEF, 0xA534, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xC638, 0x7BCF, 0x6B6D, 0x738E, 0x7BCF, 0x8C71, 0x9492,   // 0x0070 (112)
+0x9492, 0x9492, 0x9492, 0x8C51, 0x8C71, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB596, 0x738E, 0x738E, 0x73AE, 0x6B4D, 0x8410, 0x9CF3, 0x9CF3,   // 0x0090 (144)
+0x9CF3, 0x9CF3, 0x9CF3, 0x9CF3, 0x94B2, 0x7BEF, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB596, 0x738E, 0x7BEF, 0x8410, 0x632C, 0x4A69, 0x9492, 0xAD75, 0xAD55,   // 0x00B0 (176)
+0xAD55, 0xAD55, 0xAD55, 0xA534, 0xAD55, 0x9492, 0x8430, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xBDF7, 0x7BCF, 0x8430, 0x7BCF, 0x6B4D, 0x528A, 0x6B6D, 0xB5B6, 0xB5B6, 0xB5B6,   // 0x00D0 (208)
+0xB5B6, 0xB596, 0xB596, 0xAD75, 0xAD75, 0xAD55, 0x8410, 0xB5B6, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00E0 (224)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDB, 0x7BEF, 0x9CD3, 0xA514, 0x5AEB, 0x630C, 0x6B4D, 0x9492, 0xC638, 0xC618, 0xC618,   // 0x00F0 (240)
+0xBDF7, 0xBDF7, 0xC618, 0xB5B6, 0xB5B6, 0xB596, 0x9492, 0x8C51, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x8C71, 0x94B2, 0xAD55, 0xB5B6, 0x738E, 0x6B4D, 0x632C, 0xB596, 0xD69A, 0xCE59, 0xCE59,   // 0x0110 (272)
+0xCE79, 0xCE59, 0x6B6D, 0x9492, 0xB5B6, 0xBDF7, 0x9CF3, 0x8430, 0xD69A, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0120 (288)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB5B6, 0x8C51, 0xAD55, 0xB5B6, 0xCE79, 0x8C51, 0x630C, 0x8C51, 0xCE79, 0xD6BA, 0xD69A, 0xDEDB,   // 0x0130 (304)
+0xBDD7, 0x8C51, 0x4228, 0x2965, 0xAD55, 0xC638, 0xA534, 0x8430, 0xB5B6, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0xFFFF, 0xEF5D, 0x8C51, 0xA514, 0xB5B6, 0xC618, 0xD6BA, 0xB5B6, 0xB596, 0xE71C, 0xDEFB, 0xDEFB, 0xE71C, 0xAD55,   // 0x0150 (336)
+0x738E, 0x7BEF, 0x5AEB, 0x2945, 0xC638, 0xCE59, 0xA534, 0x9492, 0xA534, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0160 (352)
+0xFFFF, 0xFFFF, 0xFFFF, 0xB596, 0x94B2, 0xB5B6, 0xC618, 0xCE79, 0xD6BA, 0xE73C, 0xEF7D, 0xE73C, 0xEF5D, 0xE73C, 0x9CF3, 0x738E,   // 0x0170 (368)
+0x7BCF, 0x8430, 0x6B6D, 0x2965, 0xB596, 0xD69A, 0xAD55, 0x94B2, 0x9CD3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0180 (384)
+0xFFFF, 0xFFFF, 0xF79E, 0x9492, 0x9CF3, 0xB5B6, 0xD69A, 0xDEFB, 0xE71C, 0xE73C, 0x6B6D, 0x528A, 0xDEDB, 0xEF5D, 0x7BEF, 0x8430,   // 0x0190 (400)
+0x7BEF, 0x8C51, 0x7BCF, 0x2104, 0xB596, 0xD6BA, 0xAD55, 0x9CD3, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73C, 0xE6FC,   // 0x01A0 (416)
+0xFFDF, 0xFFFF, 0xCE59, 0x9492, 0x9492, 0x6B4D, 0x7BCF, 0xBDD7, 0xF7BE, 0xA514, 0x4A49, 0x528A, 0xC638, 0xEF7D, 0x7BEF, 0x7BEF,   // 0x01B0 (432)
+0x7BEF, 0x8430, 0x5AEB, 0x10A2, 0xC618, 0xD69A, 0xAD55, 0x94B2, 0xA514, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCE5A, 0x8BF2,   // 0x01C0 (448)
+0xFFFF, 0xFFFF, 0xAD55, 0x94B2, 0x8C51, 0x5AEB, 0x632C, 0xBDD7, 0xE73C, 0x630C, 0x632C, 0xBDF7, 0xFFDF, 0xEF5D, 0xBDD7, 0xB5B6,   // 0x01D0 (464)
+0xAD75, 0xAD75, 0x8C51, 0x738E, 0xD69A, 0xCE59, 0xB596, 0x8C51, 0xB5B6, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xCE39, 0x7350,   // 0x01E0 (480)
+0xFFFF, 0xF79E, 0x94B2, 0x94B2, 0x7BCF, 0x5AEB, 0x738E, 0xD6BA, 0xD69A, 0x2104, 0x6B6D, 0xF79E, 0xF79E, 0xF79E, 0xF7BE, 0xF79E,   // 0x01F0 (496)
+0xEF7D, 0xEF5D, 0xE73C, 0xE73C, 0xDEFB, 0xBDF7, 0xBDF7, 0x7BEF, 0xD69A, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAD36, 0x7350,   // 0x0200 (512)
+0xFFFF, 0xDEDB, 0x8C51, 0x94B2, 0x738E, 0x632C, 0x73AE, 0xCE79, 0xF7BE, 0x7BEF, 0xA514, 0xF7BE, 0xF79E, 0xEF7D, 0xEF7D, 0xEF5D,   // 0x0210 (528)
+0xE73C, 0xE71C, 0xDEFB, 0xDEDB, 0xDEDB, 0xBDD7, 0xBDF7, 0x73AE, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x9C75, 0x736F,   // 0x0220 (544)
+0xFFFF, 0xCE59, 0x8430, 0x94B2, 0x6B4D, 0x6B4D, 0xB596, 0xE73C, 0xEF7D, 0xFFFF, 0xFFFF, 0xF7BE, 0xF79E, 0xEF7D, 0xEF7D, 0xEF5D,   // 0x0230 (560)
+0xE73C, 0xE73C, 0xDEFB, 0xDEFB, 0xD6BA, 0xC618, 0xAD55, 0x8C71, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDB, 0x6AEF, 0x9492,   // 0x0240 (576)
+0xFFFF, 0xBDF7, 0x8430, 0x8C71, 0x6B6D, 0xB596, 0xE71C, 0xE73C, 0xEF5D, 0xE73C, 0xBDF7, 0xCE59, 0xF7BE, 0xEF7D, 0xEF7D, 0xEF5D,   // 0x0250 (592)
+0xE73C, 0xE71C, 0xDEFB, 0xDEFB, 0xC638, 0xD69A, 0x8410, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x9474, 0x6B0E, 0xCE59,   // 0x0260 (608)
+0xFFFF, 0xB5B6, 0x8410, 0x9492, 0xBDD7, 0xD6BA, 0xD6BA, 0xE71C, 0xE73C, 0x8C71, 0x6B4D, 0xA514, 0xF7BE, 0xEF5D, 0xEF5D, 0xE73C,   // 0x0270 (624)
+0xE73C, 0xE71C, 0xDEFB, 0xDEDB, 0xCE59, 0xC618, 0x7BCF, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xC5F9, 0x7B51, 0x7BEF, 0xFFFF,   // 0x0280 (640)
+0xFFFF, 0xB596, 0x8C71, 0xAD75, 0xBDF7, 0xCE59, 0xD69A, 0xE71C, 0xCE79, 0x8410, 0x8410, 0x9CD3, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C,   // 0x0290 (656)
+0xE71C, 0xDEFB, 0xDEFB, 0xCE59, 0xDEDB, 0x8C71, 0xAD75, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEBB, 0x83B2, 0x630C, 0xE73C, 0xFFFF,   // 0x02A0 (672)
+0xFFFF, 0xB5B6, 0x9492, 0xAD55, 0xBDD7, 0xC638, 0xCE79, 0xDEFB, 0xB596, 0x73AE, 0x8410, 0x8410, 0xDEDB, 0xE73C, 0xE71C, 0xE71C,   // 0x02B0 (688)
+0xDEFB, 0xDEFB, 0xD6BA, 0xCE59, 0xC618, 0x738E, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDC, 0x8C14, 0x5ACC, 0xC658, 0xFFFF, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xC638, 0x8C51, 0xA534, 0xB5B6, 0xBDF7, 0xCE59, 0xD6BA, 0x94B2, 0x738E, 0x8410, 0x8430, 0xCE59, 0xE73C, 0xDEFB, 0xDEFB,   // 0x02D0 (720)
+0xDEDB, 0xDEFB, 0xBDF7, 0xDEDB, 0x73AE, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDC, 0x8BD2, 0x5ACC, 0xBDD6, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02E0 (736)
+0xFFFF, 0xDEDB, 0x8C51, 0xA514, 0xAD75, 0xBDD7, 0xC638, 0xC618, 0x73AE, 0x7BCF, 0x8410, 0x5ACB, 0x8C51, 0xE73C, 0xDEDB, 0xD6BA,   // 0x02F0 (752)
+0xDEFB, 0xBDD7, 0xD69A, 0x8C71, 0x8C51, 0xFFFF, 0xFFFF, 0xFFDE, 0xCE5A, 0x7B71, 0x62ED, 0xBDF7, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xF7BE, 0x94B2, 0x94B2, 0xA534, 0xB596, 0xBDF7, 0xB596, 0x6B6D, 0x4208, 0x2945, 0x18C3, 0x6B6D, 0xDEFB, 0xD69A, 0xDEDB,   // 0x0310 (784)
+0xB5B6, 0xC618, 0x9CF3, 0x6B4D, 0xFFDE, 0xFFFF, 0xEF5D, 0xAD37, 0x62EE, 0x6B4D, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0320 (800)
+0xFFDF, 0xFFFF, 0xBDF7, 0x8C51, 0xA514, 0xAD55, 0xB596, 0xBDD7, 0xA514, 0x738E, 0xA514, 0xB5B6, 0xCE59, 0xD69A, 0xDEDB, 0xB596,   // 0x0330 (816)
+0xBDF7, 0xA534, 0x6B4C, 0xEF5D, 0xF79E, 0xBDB8, 0x7370, 0x5AAC, 0x8C71, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xF79E, 0x94B2, 0x94B2, 0xA534, 0xAD55, 0xB5B6, 0xA534, 0xBDD7, 0xD69A, 0xCE59, 0xCE79, 0xCE59, 0xA534, 0x8430,   // 0x0350 (848)
+0x738E, 0x3186, 0x7BB0, 0x8C33, 0x7370, 0x62ED, 0x8410, 0xCE59, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0360 (864)
+0xFFFF, 0xFFFF, 0xFFFF, 0xDEFB, 0x8C71, 0x9CD3, 0xAD55, 0xB596, 0xBDD7, 0xBDD7, 0xBDF7, 0xC618, 0xB5B6, 0xA534, 0xA534, 0x632C,   // 0x0370 (880)
+0x6B6D, 0xB5B6, 0xAD76, 0xAD76, 0xBE17, 0xE71B, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEFB, 0x94B2, 0x8C51, 0x94B2, 0xA534, 0xAD55, 0xAD55, 0x9CD3, 0x8C71, 0x73AE, 0x632C, 0xA534,   // 0x0390 (912)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xCE59, 0xA514, 0x8430, 0x7BCF, 0x738E, 0x73AE, 0x8410, 0xA534, 0xEF7D, 0xFFFF,   // 0x03B0 (944)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xE73C, 0xE71C, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03D0 (976)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap_128x128/tux.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap_128x128/tux.c
new file mode 100644
index 0000000..1791ece
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Bitmap_128x128/tux.c	
@@ -0,0 +1,266 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: tux_64x64.png
+// Time generated: 14.10.2010 21:56:38
+// Dimensions    : 64x64 pixels
+// Size          : 8 192 Bytes
+
+#include 
+
+prog_uint16_t tux[0x1000] PROGMEM ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0010 (16)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCE79, 0x9CF3, 0x7BCF, 0x738E, 0x738E,   // 0x0020 (32)
+0x6B6D, 0x94B2, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0030 (48)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0050 (80)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCE79, 0x6B4D, 0x5ACB, 0x8410, 0x9CF3, 0x9CF3, 0x9CF3,   // 0x0060 (96)
+0x9CD3, 0x73AE, 0x4208, 0x5ACB, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0070 (112)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0090 (144)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xA514, 0x3186, 0x8C51, 0xBDF7, 0xC618, 0xBDF7, 0xBDF7, 0xBDF7,   // 0x00A0 (160)
+0xBDF7, 0xC618, 0xBDD7, 0x738E, 0x18C3, 0x8C51, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00B0 (176)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00D0 (208)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xBDD7, 0x10A2, 0x8C71, 0x9CF3, 0x8C71, 0x8C71, 0x8C71, 0x8C71, 0x8C71,   // 0x00E0 (224)
+0x8C71, 0x8C51, 0x8C51, 0x9CF3, 0x73AE, 0x0000, 0x7BEF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00F0 (240)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0110 (272)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x2945, 0x31A6, 0x7BCF, 0x6B4D, 0x6B6D, 0x6B6D, 0x6B6D, 0x6B6D, 0x6B6D,   // 0x0120 (288)
+0x6B6D, 0x6B6D, 0x6B6D, 0x6B4D, 0x73AE, 0x2124, 0x0000, 0xAD55, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0130 (304)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0150 (336)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xC638, 0x0000, 0x31A6, 0x52AA, 0x4A69, 0x4A69, 0x4A69, 0x4A69, 0x4A69, 0x4A69,   // 0x0160 (352)
+0x4A69, 0x4A69, 0x4A69, 0x4A69, 0x528A, 0x2104, 0x0000, 0x2965, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0170 (368)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0180 (384)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0190 (400)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8C71, 0x0000, 0x1082, 0x3186, 0x3186, 0x3186, 0x3186, 0x3186, 0x3186, 0x3186,   // 0x01A0 (416)
+0x3186, 0x3186, 0x3186, 0x3186, 0x2965, 0x0020, 0x0000, 0x0000, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01B0 (432)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01C0 (448)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01D0 (464)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x630C, 0x0000, 0x0000, 0x0861, 0x18C3, 0x10A2, 0x10A2, 0x10A2, 0x10A2, 0x18C3,   // 0x01E0 (480)
+0x1082, 0x0841, 0x1082, 0x10A2, 0x0020, 0x0000, 0x0000, 0x0000, 0x528A, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01F0 (496)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0200 (512)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0210 (528)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x4A49, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0220 (544)
+0x0861, 0x3186, 0x18C3, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2104, 0xD6BA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0230 (560)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0240 (576)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0250 (592)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x39C7, 0x0000, 0x3186, 0xAD75, 0x8C51, 0x0841, 0x0000, 0x0000, 0x0000, 0x4208,   // 0x0260 (608)
+0xD6BA, 0xFFDF, 0xE71C, 0x630C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0841, 0xAD75, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0270 (624)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0280 (640)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0290 (656)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x39C7, 0x0000, 0xCE59, 0xFFFF, 0xFFFF, 0x94B2, 0x0000, 0x0000, 0x10A2, 0xE73C,   // 0x02A0 (672)
+0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x2124, 0x0000, 0x0000, 0x0000, 0x0000, 0x94B2, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02B0 (688)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02D0 (720)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x2965, 0x18E3, 0xDEDB, 0x7BCF, 0xAD75, 0xEF5D, 0x2944, 0x0000, 0x5ACA, 0xFFFF,   // 0x02E0 (736)
+0xAD55, 0x94B2, 0xAD55, 0xF7BE, 0x8410, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C51, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02F0 (752)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0310 (784)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x39E7, 0x2945, 0xA514, 0x9CF3, 0x8C71, 0xD6BB, 0x39C9, 0x0000, 0x632E, 0xF7DF,   // 0x0320 (800)
+0x7BEF, 0xAD54, 0x7BEF, 0xBDF7, 0xB596, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C71, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0330 (816)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0350 (848)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x4A49, 0x18C3, 0x9492, 0x39E7, 0x3187, 0xA48F, 0x8323, 0x5A00, 0x93A6, 0xCDD5,   // 0x0360 (864)
+0x4209, 0x4249, 0x2965, 0x9CD2, 0xB575, 0x0000, 0x0000, 0x0000, 0x0000, 0x9492, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0370 (880)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0390 (912)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x5ACB, 0x0000, 0x9D14, 0x2905, 0x6A40, 0xE643, 0xFFAE, 0xFFF3, 0xFF70, 0xDD86,   // 0x03A0 (928)
+0x7240, 0x1840, 0x18C3, 0xC65A, 0x73CF, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C51, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03B0 (944)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03D0 (976)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x738E, 0x0000, 0x5A6A, 0xD566, 0xFF66, 0xFFF8, 0xFFFD, 0xFFDC, 0xFFFD, 0xFFFA,   // 0x03E0 (992)
+0xFF0E, 0xE566, 0xC464, 0xC4CC, 0x2103, 0x0000, 0x0000, 0x0000, 0x0000, 0x6B6D, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0410 (1040)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x7BEF, 0x0800, 0xB440, 0xFFC6, 0xFFF3, 0xFFB4, 0xFFB2, 0xFF92, 0xFF72, 0xFF53,   // 0x0420 (1056)
+0xFF55, 0xFF75, 0xFEF0, 0xF542, 0x8240, 0x0000, 0x0000, 0x0000, 0x0000, 0x4228, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0430 (1072)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0440 (1088)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0450 (1104)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8432, 0x4140, 0xFFE2, 0xFFEB, 0xFFAC, 0xFF8B, 0xFF4C, 0xFF2C, 0xFEEC, 0xFECB,   // 0x0460 (1120)
+0xFE6A, 0xFE08, 0xFDA7, 0xFDC3, 0xA320, 0x0000, 0x0000, 0x0000, 0x0000, 0x18E3, 0xD69A, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0470 (1136)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0480 (1152)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0490 (1168)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x9D14, 0x28A0, 0xF6E0, 0xFFE1, 0xFF43, 0xFF04, 0xFEC4, 0xFE84, 0xFE23, 0xFDE1,   // 0x04A0 (1184)
+0xFD60, 0xFD20, 0xFD20, 0xFD20, 0x7241, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x04B0 (1200)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x04C0 (1216)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x04D0 (1232)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xB5B6, 0x0000, 0xC4A9, 0xFEC0, 0xFF00, 0xFEA0, 0xFE40, 0xFE00, 0xFDA0, 0xFD60,   // 0x04E0 (1248)
+0xFD40, 0xFD20, 0xEC80, 0xDCC7, 0x8C0F, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x52AA, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x04F0 (1264)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0500 (1280)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0510 (1296)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xAD75, 0x0000, 0xD69B, 0xF631, 0xF5C0, 0xFE80, 0xFE00, 0xFDC0, 0xFD60, 0xFD40,   // 0x0520 (1312)
+0xFCC0, 0xDC86, 0xCD93, 0xE73D, 0xE71C, 0x0861, 0x0000, 0x0000, 0x0000, 0x0000, 0x0861, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0530 (1328)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0540 (1344)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0550 (1360)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x632C, 0x0000, 0xD6BA, 0xFFFF, 0xF5F1, 0xFD40, 0xFD80, 0xFD20, 0xFCE0, 0xECA3,   // 0x0560 (1376)
+0xDD6F, 0xE6FC, 0xFFFF, 0xFFFF, 0xFFFF, 0x632C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x5ACB, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0570 (1392)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0580 (1408)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0590 (1424)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xDEDB, 0x0861, 0x0000, 0xD69A, 0xFFFF, 0xFFFF, 0xFED8, 0xF631, 0xF610, 0xE5F2, 0xE6B9,   // 0x05A0 (1440)
+0xF7BF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xE71C, 0x10A2, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0xB5B6, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x05B0 (1456)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x05C0 (1472)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x05D0 (1488)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x39E7, 0x0000, 0x4228, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7FF, 0xF7DF, 0xFFFF,   // 0x05E0 (1504)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x73AE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3186, 0xEF7D, 0xFFFF, 0xFFFF,   // 0x05F0 (1520)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0600 (1536)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0610 (1552)
+0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x738E, 0x0000, 0x18C3, 0xDEFB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0620 (1568)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFFF, 0xCE59, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6B4D, 0xFFFF, 0xFFFF,   // 0x0630 (1584)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0640 (1600)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0650 (1616)
+0xFFFF, 0xFFDF, 0xFFFF, 0xA514, 0x0000, 0x0000, 0x9CD3, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0660 (1632)
+0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0x2965, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xAD55, 0xFFFF,   // 0x0670 (1648)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0680 (1664)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0690 (1680)
+0xFFDF, 0xFFFF, 0xD69A, 0x0861, 0x0000, 0x2945, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x06A0 (1696)
+0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xFFFF, 0x7BCF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x18C3, 0xD6BA,   // 0x06B0 (1712)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x06C0 (1728)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x06D0 (1744)
+0xFFFF, 0xFFDF, 0x39C7, 0x0000, 0x0000, 0x8430, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x06E0 (1760)
+0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xFFFF, 0xCE79, 0x0841, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x4228,   // 0x06F0 (1776)
+0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0700 (1792)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF,   // 0x0710 (1808)
+0xFFFF, 0x94B2, 0x0000, 0x0020, 0x0020, 0xCE79, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF,   // 0x0720 (1824)
+0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xFFDF, 0x4A69, 0x0000, 0x0841, 0x0000, 0x0000, 0x0000, 0x0020, 0x0000,   // 0x0730 (1840)
+0x8C71, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0740 (1856)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0750 (1872)
+0xEF7D, 0x2104, 0x0020, 0x0000, 0x3186, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF,   // 0x0760 (1888)
+0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xFFFF, 0xB5B6, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0000,   // 0x0770 (1904)
+0x10A2, 0xD6BA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0780 (1920)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF,   // 0x0790 (1936)
+0x8C71, 0x0000, 0x0861, 0x0000, 0x7BCF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF,   // 0x07A0 (1952)
+0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xFFDF, 0x528A, 0x0000, 0x0841, 0x0020, 0x0020, 0x0020, 0x0020,   // 0x07B0 (1968)
+0x0000, 0x630C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x07C0 (1984)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE,   // 0x07D0 (2000)
+0x3186, 0x0000, 0x0841, 0x10A2, 0xE71C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF,   // 0x07E0 (2016)
+0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xF79E, 0xEF5D, 0xF7BE, 0xBDD7, 0x0841, 0x0861, 0x0841, 0x0841, 0x0841, 0x0020,   // 0x07F0 (2032)
+0x0020, 0x1082, 0xC638, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0800 (2048)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xBDD7,   // 0x0810 (2064)
+0x0020, 0x1082, 0x0000, 0x7BEF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE,   // 0x0820 (2080)
+0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF7D, 0x4208, 0x0020, 0x0861, 0x0861, 0x0841, 0x0841,   // 0x0830 (2096)
+0x0841, 0x0000, 0x630C, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0840 (2112)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x6B4D,   // 0x0850 (2128)
+0x0000, 0x0861, 0x2104, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE,   // 0x0860 (2144)
+0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xE73C, 0xF7BE, 0x8430, 0x0000, 0x1082, 0x0861, 0x0861, 0x0861,   // 0x0870 (2160)
+0x0861, 0x0020, 0x18C3, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0880 (2176)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF5D, 0x2124,   // 0x0890 (2192)
+0x0861, 0x0020, 0x8410, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE,   // 0x08A0 (2208)
+0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xEF7D, 0xB5B6, 0x0861, 0x1082, 0x1082, 0x0861, 0x0861,   // 0x08B0 (2224)
+0x0861, 0x0861, 0x0000, 0x8430, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x08C0 (2240)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xA514, 0x0020,   // 0x08D0 (2256)
+0x10A2, 0x1082, 0xD69A, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE,   // 0x08E0 (2272)
+0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xEF5D, 0xCE79, 0x2124, 0x1082, 0x10A2, 0x1082, 0x1082,   // 0x08F0 (2288)
+0x0861, 0x1082, 0x0000, 0x4208, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0900 (2304)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x4208, 0x0861,   // 0x0910 (2320)
+0x1082, 0x31A6, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E,   // 0x0920 (2336)
+0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEDB, 0x39C7, 0x1082, 0x10A2, 0x10A2, 0x1082,   // 0x0930 (2352)
+0x1082, 0x1082, 0x0841, 0x18C3, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0940 (2368)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xA534, 0x0841, 0x18C3,   // 0x0950 (2384)
+0x0841, 0x630C, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E,   // 0x0960 (2400)
+0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xDEFB, 0xE73C, 0x4A49, 0x0861, 0x18C3, 0x10A2, 0x10A2,   // 0x0970 (2416)
+0x10A2, 0x1082, 0x1082, 0x0841, 0x9CD3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0980 (2432)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x3186, 0x1082, 0x18E3,   // 0x0990 (2448)
+0x0861, 0x94B2, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D,   // 0x09A0 (2464)
+0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEDB, 0xE73C, 0x4A69, 0x1082, 0x18E3, 0x18C3, 0x10A2,   // 0x09B0 (2480)
+0x10A2, 0x10A2, 0x10A2, 0x0020, 0x73AE, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x09C0 (2496)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B2, 0x0841, 0x18E3, 0x18E3,   // 0x09D0 (2512)
+0x0861, 0xAD75, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D,   // 0x09E0 (2528)
+0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEDB, 0xE73C, 0x52AA, 0x10A2, 0x2104, 0x18E3, 0x18C3,   // 0x09F0 (2544)
+0x18C3, 0x18C3, 0x10A2, 0x0841, 0x630C, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0A00 (2560)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x632C, 0x0861, 0x18E4, 0x18E4,   // 0x0A10 (2576)
+0x1082, 0xC638, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D,   // 0x0A20 (2592)
+0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xD6BA, 0xE71C, 0x6B4D, 0x10A2, 0x18C3, 0x18C3, 0x10A2,   // 0x0A30 (2608)
+0x10A2, 0x10A2, 0x18C3, 0x0861, 0x5AEB, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0A40 (2624)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x8410, 0x0862, 0x3143, 0x2924,   // 0x0A50 (2640)
+0x0882, 0xBDD7, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D,   // 0x0A60 (2656)
+0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB, 0xE73C, 0x630C, 0x2103, 0x4A69, 0x632C, 0x6B4D,   // 0x0A70 (2672)
+0x528A, 0x2965, 0x18C3, 0x1081, 0x738E, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0A80 (2688)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB596, 0x7A40, 0xECA0, 0xCC00,   // 0x0A90 (2704)
+0x3941, 0xA535, 0xFFFF, 0xF7BE, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D,   // 0x0AA0 (2720)
+0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEFB, 0xD6DB, 0xCE38, 0xC618, 0x4A48, 0x4A49, 0x6B6D, 0x6B4D, 0x6B4D,   // 0x0AB0 (2736)
+0x6B4D, 0x630C, 0x3186, 0x18E4, 0x9492, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0AC0 (2752)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xC488, 0xFD41, 0xFE6D, 0xFE6A,   // 0x0AD0 (2768)
+0xDC60, 0x5A25, 0xB5D8, 0xFFFF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C,   // 0x0AE0 (2784)
+0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xD6BB, 0xBCAB, 0xD462, 0xD462, 0x49E4, 0x10C3, 0x18C3, 0x18C3, 0x18C3,   // 0x0AF0 (2800)
+0x18C3, 0x18E3, 0x10A3, 0x49C4, 0xB575, 0xF7BF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0B00 (2816)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCD70, 0xECA0, 0xFF14, 0xFF9B, 0xFF7B,   // 0x0B10 (2832)
+0xFECF, 0xC3A0, 0x3143, 0x9CF3, 0xFFFF, 0xF7BE, 0xF79E, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C,   // 0x0B20 (2848)
+0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEFB, 0xC617, 0xDC60, 0xFD60, 0xFD20, 0x3120, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0B30 (2864)
+0x0000, 0x0000, 0x3900, 0xE460, 0xB46A, 0xEF9F, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0B40 (2880)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD5F4, 0xDC20, 0xFE8E, 0xFF59, 0xFF36, 0xFF36,   // 0x0B50 (2896)
+0xFF59, 0xFE6B, 0xA300, 0x18E4, 0x8410, 0xFFBE, 0xF7BE, 0xEF7D, 0xF79E, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C,   // 0x0B60 (2912)
+0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEBA, 0xDEFB, 0xC5B5, 0xE4A1, 0xFEF2, 0xF716, 0x3164, 0x18E4, 0x2103, 0x1082, 0x1082,   // 0x0B70 (2928)
+0x0021, 0x1061, 0xD5D0, 0xFE27, 0xB3E3, 0xCE9B, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0B80 (2944)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF77D, 0xE697, 0xDDAF, 0xD4C8, 0xE480, 0xFE29, 0xFF36, 0xFF15, 0xFF35, 0xFF15,   // 0x0B90 (2960)
+0xFF15, 0xFF36, 0xFDA5, 0x6A42, 0x1905, 0x6B4C, 0xE73C, 0xFFDF, 0xEF5D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C,   // 0x0BA0 (2976)
+0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB, 0xD6BA, 0xDEDB, 0xBDB5, 0xE4C3, 0xFF56, 0xFFDB, 0xAD10, 0x10A2, 0x10C3, 0x18E4, 0x1082,   // 0x0BB0 (2992)
+0x2922, 0xC5B1, 0xFFDC, 0xFED1, 0xB3A2, 0xBE19, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0BC0 (3008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE6B8, 0xD484, 0xE4C0, 0xF584, 0xFE28, 0xFECF, 0xFF14, 0xFF13, 0xFF13, 0xFF13, 0xFF13,   // 0x0BD0 (3024)
+0xFF13, 0xFF14, 0xFEF0, 0xDC80, 0x41C5, 0x2945, 0x5269, 0xCE59, 0xF7BE, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C,   // 0x0BE0 (3040)
+0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB, 0xD6BA, 0xD69A, 0xD6DB, 0xBD95, 0xE4E2, 0xFF33, 0xFF36, 0xFF97, 0xDDF1, 0x8B66, 0x7AE4, 0x9BC7,   // 0x0BF0 (3056)
+0xEEB2, 0xFF97, 0xFF37, 0xFEF0, 0xC3E0, 0xB5B7, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C00 (3072)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD52B, 0xFD60, 0xFECD, 0xFF33, 0xFF13, 0xFF12, 0xFEF1, 0xFEF1, 0xFEF1, 0xFEF1, 0xFEF1,   // 0x0C10 (3088)
+0xFEF1, 0xFEF1, 0xFF12, 0xFE69, 0x9B41, 0x31A8, 0x31A6, 0x39E7, 0xB5B6, 0xF79E, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB,   // 0x0C20 (3104)
+0xDEFB, 0xDEDB, 0xDEDB, 0xD6BA, 0xD6BA, 0xD699, 0xD6BA, 0xBD94, 0xE502, 0xFF12, 0xFF15, 0xFEF4, 0xFF55, 0xFF95, 0xFF54, 0xFF95,   // 0x0C30 (3120)
+0xFF35, 0xFEF4, 0xFF14, 0xFF14, 0xF5A4, 0xB426, 0xE75E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C40 (3136)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD54C, 0xFDA0, 0xFECE, 0xFEF0, 0xFECF, 0xFEEF, 0xFEEF, 0xFEF0, 0xFEEF, 0xFEF0, 0xFEF0,   // 0x0C50 (3152)
+0xFEF0, 0xFEEF, 0xFEF0, 0xFEEF, 0xF582, 0x6244, 0x39E8, 0x39C6, 0x528A, 0xE71C, 0xE73C, 0xE71C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB,   // 0x0C60 (3168)
+0xDEDB, 0xDEDB, 0xD6BA, 0xD6BA, 0xD69A, 0xCE79, 0xCE9A, 0xBD94, 0xE522, 0xFF10, 0xFEF2, 0xFEF2, 0xFEF2, 0xFEF2, 0xFEF2, 0xFEF2,   // 0x0C70 (3184)
+0xFEF2, 0xFF12, 0xFEF2, 0xFEF2, 0xFF12, 0xED85, 0xBC68, 0xE73D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C80 (3200)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD5B0, 0xF580, 0xFECB, 0xFEEE, 0xFECD, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE,   // 0x0C90 (3216)
+0xFEEE, 0xFEEE, 0xFECD, 0xFECE, 0xFECA, 0xCC60, 0x41C7, 0x39C7, 0x4228, 0xCE79, 0xEF5D, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB,   // 0x0CA0 (3232)
+0xDEDB, 0xD6BA, 0xD6BA, 0xD69A, 0xCE79, 0xCE59, 0xCE9A, 0xBD73, 0xED42, 0xFF0F, 0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0,   // 0x0CB0 (3248)
+0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0, 0xFF31, 0xF628, 0xC4A7, 0xDE57, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0CC0 (3264)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDE13, 0xF560, 0xFEC9, 0xFECD, 0xFECC, 0xFECC, 0xFECC, 0xFECC, 0xFECC, 0xFECC, 0xFECC,   // 0x0CD0 (3280)
+0xFEEC, 0xFEEC, 0xFECC, 0xFECC, 0xFEED, 0xFE44, 0x9323, 0x52CC, 0x73AE, 0xD69A, 0xE73C, 0xDEFB, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB,   // 0x0CE0 (3296)
+0xD6BA, 0xD6BA, 0xD69A, 0xCE79, 0xCE59, 0xD69A, 0xB5D8, 0x7B28, 0xF5A2, 0xFF0F, 0xFECE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE,   // 0x0CF0 (3312)
+0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFECD, 0xFF10, 0xFEA9, 0xCC60, 0xD615, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D00 (3328)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDE55, 0xED80, 0xFEA4, 0xFECA, 0xFECA, 0xFECA, 0xFECA, 0xFECA, 0xFECA, 0xFECA, 0xFEC9,   // 0x0D10 (3344)
+0xFEA7, 0xFEA6, 0xFEA8, 0xFEC9, 0xFECB, 0xFEEA, 0xEDA2, 0xB4F0, 0xCE9A, 0xDEFB, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB, 0xD6BA,   // 0x0D20 (3360)
+0xD6BA, 0xD69A, 0xCE79, 0xCE79, 0xD6BA, 0xB596, 0x4A8B, 0x72A4, 0xFE45, 0xFEEC, 0xFECC, 0xFEEC, 0xFEEC, 0xFEEC, 0xFEEC, 0xFEEC,   // 0x0D30 (3376)
+0xFEEC, 0xFECB, 0xFECB, 0xFEEC, 0xFEEC, 0xFEEC, 0xFECC, 0xFEA5, 0xFDE0, 0xAC8B, 0xE75E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D40 (3392)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE632, 0xF5E0, 0xFE80, 0xFE82, 0xFEC7, 0xFEC8, 0xFEC8, 0xFEC8, 0xFEC7, 0xFEA4, 0xFE61,   // 0x0D50 (3408)
+0xFE60, 0xFE60, 0xFE60, 0xFE61, 0xFE83, 0xFEA6, 0xFEA3, 0xDD22, 0xD658, 0xE75D, 0xDEDB, 0xDEDB, 0xDEDB, 0xD6BA, 0xD6BA, 0xD69A,   // 0x0D60 (3424)
+0xD69A, 0xD69A, 0xD6BA, 0xCE59, 0x9492, 0x5289, 0x39E9, 0x9B84, 0xFEA3, 0xFEEB, 0xFEEA, 0xFEEA, 0xFEEA, 0xFEEA, 0xFEEA, 0xFEC8,   // 0x0D70 (3440)
+0xFE84, 0xFE61, 0xFE61, 0xFEA5, 0xFEC9, 0xFEA7, 0xFEA2, 0xFE80, 0xBC41, 0x8C0F, 0xE71C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D80 (3456)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDDCE, 0xFE40, 0xFEA0, 0xFE80, 0xFE80, 0xFEA2, 0xFEA2, 0xFEA2, 0xFEA0, 0xFE80, 0xFE80,   // 0x0D90 (3472)
+0xFEA0, 0xFEA0, 0xFEA0, 0xFE80, 0xFE80, 0xFE80, 0xFE80, 0xFE80, 0xCCE5, 0xD69A, 0xE73C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB,   // 0x0DA0 (3488)
+0xD69A, 0xBDF7, 0x9CD3, 0x630C, 0x4228, 0x4A69, 0x422A, 0xB423, 0xFEC0, 0xFEA5, 0xFEE7, 0xFEC7, 0xFEC7, 0xFEC6, 0xFEA3, 0xFE80,   // 0x0DB0 (3504)
+0xFE80, 0xFE80, 0xFE80, 0xFE60, 0xFEA0, 0xFEC0, 0xEDC0, 0xA3A4, 0x732C, 0xAD96, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0DC0 (3520)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE5A8, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0DD0 (3536)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEE0, 0xF640, 0x93A8, 0x8C72, 0xA534, 0xAD75, 0xA534, 0x9CF3, 0x8C51,   // 0x0DE0 (3552)
+0x738E, 0x5ACB, 0x4A49, 0x4A69, 0x528A, 0x4A8A, 0x5249, 0xD502, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEC1, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0,   // 0x0DF0 (3568)
+0xFEA0, 0xFEA0, 0xFEA0, 0xFEE0, 0xFE60, 0xC482, 0x7B09, 0x7BD0, 0xB5B7, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E00 (3584)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDD8A, 0xFEC0, 0xFF20, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0,   // 0x0E10 (3600)
+0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEC0, 0xFF20, 0xAC02, 0x4209, 0x4A69, 0x4A69, 0x4A69, 0x4A69, 0x4A69,   // 0x0E20 (3616)
+0x528A, 0x528A, 0x52AA, 0x52AA, 0x528A, 0x4A8A, 0x5A69, 0xE5C1, 0xFF00, 0xFEC0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0,   // 0x0E30 (3632)
+0xFEC0, 0xFEE0, 0xFF00, 0xE561, 0x9367, 0x736E, 0x9D14, 0xD6BA, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E40 (3648)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD617, 0xCCC5, 0xF620, 0xFEE0, 0xFF40, 0xFF40, 0xFF40, 0xFF20, 0xFF00, 0xFF00, 0xFF00,   // 0x0E50 (3664)
+0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF40, 0xB483, 0x4A8B, 0x5ACA, 0x5ACB, 0x5ACB, 0x5ACB, 0x5ACB,   // 0x0E60 (3680)
+0x5ACB, 0x52AA, 0x52AA, 0x52AA, 0x52AA, 0x4A8A, 0x6289, 0xEE20, 0xFF20, 0xFEE0, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFEE0,   // 0x0E70 (3696)
+0xFF20, 0xFEC0, 0xBC64, 0x732B, 0x8C72, 0xCE58, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E80 (3712)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7E, 0xB576, 0x93EE, 0xA408, 0xC4A5, 0xDD63, 0xF641, 0xFEC0, 0xFF40, 0xFF80, 0xFF60,   // 0x0E90 (3728)
+0xFF40, 0xFF20, 0xFF20, 0xFF40, 0xFF40, 0xFF40, 0xFF20, 0xFF20, 0xFF80, 0xAC03, 0x4A6B, 0x5ACA, 0x5ACB, 0x5ACB, 0x5AEB, 0x5AEB,   // 0x0EA0 (3744)
+0x5AEB, 0x630C, 0x630C, 0x630C, 0x5AEB, 0x52CB, 0x5A69, 0xE5E1, 0xFF60, 0xFF20, 0xFF20, 0xFF20, 0xFF20, 0xFF20, 0xFF20, 0xFF60,   // 0x0EB0 (3760)
+0xF640, 0xA3A7, 0x738F, 0xAD96, 0xE71C, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0EC0 (3776)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0xD6DB, 0xB5B8, 0x9CD4, 0x9431, 0x93EE, 0x9C0A, 0xB467, 0xD544, 0xF660,   // 0x0ED0 (3792)
+0xFF60, 0xFFA0, 0xFF80, 0xFF60, 0xFF40, 0xFF40, 0xFF60, 0xFFA0, 0xD521, 0x730A, 0x73CF, 0x8C71, 0x9CD3, 0x9CF3, 0xA514, 0xA534,   // 0x0EE0 (3808)
+0xAD55, 0xB596, 0xB5B6, 0xB596, 0xAD55, 0x9CF3, 0x83F0, 0xCD04, 0xFFA0, 0xFF40, 0xFF40, 0xFF40, 0xFF40, 0xFF40, 0xFFA0, 0xF621,   // 0x0EF0 (3824)
+0x8B49, 0x8431, 0xCE58, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F00 (3840)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xF79E, 0xE73C, 0xD6BB, 0xBE19, 0xA556, 0x9472, 0x9C0D,   // 0x0F10 (3856)
+0xB447, 0xDD82, 0xFEE0, 0xFFA0, 0xFFC0, 0xFFC0, 0xFF80, 0xC4C2, 0x730C, 0x9CF4, 0xD69A, 0xEF5D, 0xEF7D, 0xF79E, 0xF79E, 0xF7BE,   // 0x0F20 (3872)
+0xF7BE, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xEF7D, 0xDF1C, 0xC530, 0xF620, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFF80, 0xE5A2, 0x834A,   // 0x0F30 (3888)
+0x8C93, 0xDEDA, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F40 (3904)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDE, 0xEF7D, 0xD6BB,   // 0x0F50 (3920)
+0xAD77, 0x9452, 0x9BEB, 0xB466, 0xC524, 0xC543, 0xA3E5, 0x734D, 0xAD76, 0xEF5C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F60 (3936)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDF1C, 0xACB0, 0xBCA6, 0xD544, 0xCD64, 0xCD05, 0xAC07, 0x7B6D, 0x9CF4,   // 0x0F70 (3952)
+0xE6FB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F80 (3968)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F90 (3984)
+0xFFDE, 0xE75D, 0xC65A, 0xA536, 0x9493, 0x8C53, 0x94B4, 0xBE18, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FA0 (4000)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xDEFC, 0xAD57, 0x9493, 0x8C73, 0x8C73, 0x94D4, 0xBE18, 0xEF5D,   // 0x0FB0 (4016)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FC0 (4032)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FD0 (4048)
+0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xEF5C, 0xE73C, 0xEF5C, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FE0 (4064)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xEF5C, 0xE73C, 0xEF5C, 0xEF7D, 0xFFDE, 0xFFFF,   // 0x0FF0 (4080)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x1000 (4096)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_128x128_Serial/UTFT_Demo_128x128_Serial.pde b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_128x128_Serial/UTFT_Demo_128x128_Serial.pde
new file mode 100644
index 0000000..45a97e6
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_128x128_Serial/UTFT_Demo_128x128_Serial.pde	
@@ -0,0 +1,335 @@
+// UTFT_Demo_128x128_Serial (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made to work on the 128x128 modules.
+// Any other size displays may cause strange behaviour.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Declare an instance of the class
+UTFT myGLCD(LPH9135,6,5,2,3,4);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD(PORTRAIT);
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  byte buf[126];
+  int x, x2;
+  int y, y2;
+  int r;
+  
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+  myGLCD.setContrast(64);
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0,0,127,12);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0,117,127,127);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255,0,0);
+  myGLCD.print("Universal TFT", CENTER, 0);
+  myGLCD.setBackColor(64,64,64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("H.Karlsen", LEFT, 116);
+  myGLCD.print("(C)2012", RIGHT, 116);
+  myGLCD.setColor(0,255,0);
+  myGLCD.drawRect(0,13,127,116);
+
+// Draw crosshairs
+  myGLCD.setColor(0,0,255);
+  myGLCD.drawLine(63,14,63,115);
+  myGLCD.drawLine(1,63,126,63);
+  for (int i=3; i<128; i+=10)
+    myGLCD.drawLine(i, 61, i, 65);
+  for (int i=14; i<118; i+=10)
+    myGLCD.drawLine(61, i, 65, i);
+  
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.setBackColor(0,0,0);
+  myGLCD.print("Sin", 2, 14);
+  for (int i=1; i<126; i++)
+  {
+    myGLCD.drawPixel(i,63+(sin(((i*2.85)*3.14)/180)*45));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 2, 26);
+  for (int i=1; i<126; i++)
+  {
+    myGLCD.drawPixel(i,63+(cos(((i*2.85)*3.14)/180)*45));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 2, 38);
+  for (int i=1; i<126; i++)
+  {
+    myGLCD.drawPixel(i,63+(tan(((i*2.85)*3.14)/180)));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+  myGLCD.setColor(0,0,255);
+  myGLCD.drawLine(63,14,63,115);
+  myGLCD.drawLine(1,63,126,63);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<3654; i++)
+  {
+    x++;
+    if (x==127)
+      x=1;
+    if (i>127)
+    {
+      if ((x==63)||(buf[x-1]==63))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=63+(sin(((i*1.3)*3.14)/180)*45);
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+//    delay(3);
+  }
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+  
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(10+(i*10),10+(i*10), 60+(i*10), 60+(i*10));
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+  
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(70-(i*10),10+(i*10), 120-(i*10), 60+(i*10));
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+  
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(30+(i*10),35+(i*10), 25);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+  // Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=11; i<115; i+=3)
+  {
+    myGLCD.drawLine(1, i, i-10, 115);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=112; i>14; i-=3)
+  {
+    myGLCD.drawLine(126, i, i+14, 14);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=115; i>14; i-=3)
+  {
+    myGLCD.drawLine(1, i, 116-i, 14);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=14; i<115; i+=3)
+  {
+    myGLCD.drawLine(126, i, 140-i, 115);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=22+random(85);
+    y=35+random(59);
+    r=random(20);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(124);
+    y=15+random(101);
+    x2=2+random(124);
+    y2=15+random(101);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(124);
+    y=15+random(101);
+    x2=2+random(124);
+    y2=15+random(101);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random lines
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(124);
+    y=15+random(101);
+    x2=2+random(124);
+    y2=15+random(101);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random pixels
+  for (int i=0; i<5000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(124), 15+random(101));
+  }
+  
+  delay (2000);
+  
+// Set up the "Finished"-screen
+  myGLCD.setContrast(0);
+  myGLCD.fillScr(0,0,255);
+  myGLCD.setColor(255,0,0);
+  myGLCD.fillRoundRect(2, 40, 125, 88);
+  
+  myGLCD.setColor(255,255,255);
+  myGLCD.setBackColor(255,0,0);
+  myGLCD.print("That's it!", CENTER, 46);
+  myGLCD.print("Restarting in a", CENTER, 66);
+  myGLCD.print("few seconds...", CENTER, 76);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.setBackColor(0,0,255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 108);
+  myGLCD.printNumI(millis(), CENTER, 118);
+  
+  myGLCD.setContrast(64);
+  
+  delay (10000);
+  
+// Fade screen to black
+  for (int i=64; i>0; i--)
+  {
+    myGLCD.setContrast(i);
+    delay(100);
+  }
+}
+
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_160x128_Serial/UTFT_Demo_160x128_Serial.pde b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_160x128_Serial/UTFT_Demo_160x128_Serial.pde
new file mode 100644
index 0000000..35ccb5d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_160x128_Serial/UTFT_Demo_160x128_Serial.pde	
@@ -0,0 +1,323 @@
+// UTFT_Demo_160x128_Serial (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 160x128 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(ITDB18SP,11,10,9,12,8);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[158];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 159, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 114, 159, 127);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("Universal TFT Lib.", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("H.Karlsen", LEFT, 114);
+  myGLCD.print("(C)2012", RIGHT, 114);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 13, 159, 113);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(79, 14, 79, 113);
+  myGLCD.drawLine(1, 63, 158, 63);
+
+  for (int i=9; i<150; i+=10)
+    myGLCD.drawLine(i, 61, i, 65);
+  for (int i=19; i<110; i+=10)
+    myGLCD.drawLine(77, i, 81, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<158; i++)
+  {
+    myGLCD.drawPixel(i,63+(sin(((i*2.27)*3.14)/180)*40));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<158; i++)
+  {
+    myGLCD.drawPixel(i,63+(cos(((i*2.27)*3.14)/180)*40));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<158; i++)
+  {
+    myGLCD.drawPixel(i,63+(tan(((i*2.27)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(79, 14, 79, 113);
+  myGLCD.drawLine(1, 63, 158, 63);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(158*20); i++) 
+  {
+    x++;
+    if (x==159)
+      x=1;
+    if (i>159)
+    {
+      if ((x==79)||(buf[x-1]==63))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=63+(sin(((i*2.5)*3.14)/180)*(40-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(39+(i*10), 23+(i*10), 59+(i*10), 43+(i*10));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(99-(i*10), 23+(i*10), 119-(i*10), 43+(i*10));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(49+(i*10),33+(i*10), 15);
+  }
+  
+  delay(2000);
+    
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=14; i<113; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 112);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=112; i>15; i-=5)
+  {
+    myGLCD.drawLine(158, i, (i*1.44)-12, 14);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=112; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 172-(i*1.44), 14);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<112; i+=5)
+  {
+    myGLCD.drawLine(158, i, 171-(i*1.44), 112);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=22+random(116);
+    y=35+random(57);
+    r=random(20);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(156);
+    y=16+random(95);
+    x2=2+random(156);
+    y2=16+random(95);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(156);
+    y=16+random(95);
+    x2=2+random(156);
+    y2=16+random(95);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(156);
+    y=16+random(95);
+    x2=2+random(156);
+    y2=16+random(95);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+  for (int i=0; i<5000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(156), 16+random(95));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(10, 17, 149, 72);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 20);
+  myGLCD.print("Restarting in a", CENTER, 45);
+  myGLCD.print("few seconds...", CENTER, 57);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 103);
+  myGLCD.printNumI(millis(), CENTER, 115);
+
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_220x176/UTFT_Demo_220x176.pde b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_220x176/UTFT_Demo_220x176.pde
new file mode 100644
index 0000000..45f4898
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_220x176/UTFT_Demo_220x176.pde	
@@ -0,0 +1,326 @@
+// UTFT_Demo_220x176 (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 220x176 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for Arduino 2009/Uno
+UTFT myGLCD(ITDB22,19,18,17,16);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for Arduino Mega
+//UTFT myGLCD(ITDB22,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[218];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 219, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 162, 219, 175);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("** Universal TFT Library **", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("> elec.henningkarlsen.com <", CENTER, 163);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 219, 161);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(109, 15, 109, 160);
+  myGLCD.drawLine(1, 88, 218, 88);
+
+  for (int i=9; i<210; i+=10)
+    myGLCD.drawLine(i, 86, i, 90);
+  for (int i=19; i<155; i+=10)
+    myGLCD.drawLine(107, i, 111, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(sin(((i*1.65)*3.14)/180)*70));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(cos(((i*1.65)*3.14)/180)*70));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(tan(((i*1.65)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(109, 15, 109, 160);
+  myGLCD.drawLine(1, 88, 218, 88);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(218*20); i++) 
+  {
+    x++;
+    if (x==219)
+      x=1;
+    if (i>219)
+    {
+      if ((x==109)||(buf[x-1]==88))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=88+(sin(((i*1.6)*3.14)/180)*(65-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(44+(i*15), 23+(i*15), 88+(i*15), 63+(i*15));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(132-(i*15), 23+(i*15), 172-(i*15), 63+(i*15));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(64+(i*15),43+(i*15), 20);
+  }
+  
+  delay(2000);
+    
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<160; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 160);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=160; i>15; i-=5)
+  {
+    myGLCD.drawLine(218, i, (i*1.44)-12, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=160; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 232-(i*1.44), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<160; i+=5)
+  {
+    myGLCD.drawLine(218, i, 231-(i*1.44), 160);
+  }
+  
+  delay(2000);
+  
+    myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=22+random(176);
+    y=35+random(105);
+    r=random(20);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(216), 16+random(143));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(40, 57, 179, 119);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 62);
+  myGLCD.print("Restarting in a", CENTER, 88);
+  myGLCD.print("few seconds...", CENTER, 101);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 146);
+  myGLCD.printNumI(millis(), CENTER, 161);
+
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_220x176_Serial/UTFT_Demo_220x176_Serial.pde b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_220x176_Serial/UTFT_Demo_220x176_Serial.pde
new file mode 100644
index 0000000..ec66344
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_220x176_Serial/UTFT_Demo_220x176_Serial.pde	
@@ -0,0 +1,322 @@
+// UTFT_Demo_220x176_Serial (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for serial modules with a screen resolution 
+// of 220x176 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(ITDB22SP,11,10,9,12);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[218];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 219, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 162, 219, 175);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("** Universal TFT Library **", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("> elec.henningkarlsen.com <", CENTER, 163);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 219, 161);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(109, 15, 109, 160);
+  myGLCD.drawLine(1, 88, 218, 88);
+
+  for (int i=9; i<210; i+=10)
+    myGLCD.drawLine(i, 86, i, 90);
+  for (int i=19; i<155; i+=10)
+    myGLCD.drawLine(107, i, 111, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(sin(((i*1.65)*3.14)/180)*70));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(cos(((i*1.65)*3.14)/180)*70));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(tan(((i*1.65)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(109, 15, 109, 160);
+  myGLCD.drawLine(1, 88, 218, 88);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(218*20); i++) 
+  {
+    x++;
+    if (x==219)
+      x=1;
+    if (i>219)
+    {
+      if ((x==109)||(buf[x-1]==88))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=88+(sin(((i*1.6)*3.14)/180)*(65-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(44+(i*15), 23+(i*15), 88+(i*15), 63+(i*15));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(132-(i*15), 23+(i*15), 172-(i*15), 63+(i*15));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(64+(i*15),43+(i*15), 20);
+  }
+  
+  delay(2000);
+    
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<160; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 160);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=160; i>15; i-=5)
+  {
+    myGLCD.drawLine(218, i, (i*1.44)-12, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=160; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 232-(i*1.44), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<160; i+=5)
+  {
+    myGLCD.drawLine(218, i, 231-(i*1.44), 160);
+  }
+  
+  delay(2000);
+  
+    myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,161);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=22+random(176);
+    y=35+random(105);
+    r=random(20);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(216), 16+random(143));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(40, 57, 179, 119);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 62);
+  myGLCD.print("Restarting in a", CENTER, 88);
+  myGLCD.print("few seconds...", CENTER, 101);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 146);
+  myGLCD.printNumI(millis(), CENTER, 161);
+
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_320x240/UTFT_Demo_320x240.pde b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_320x240/UTFT_Demo_320x240.pde
new file mode 100644
index 0000000..25f7f1b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_320x240/UTFT_Demo_320x240.pde	
@@ -0,0 +1,325 @@
+// UTFT_Demo_320x240 (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 320x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for Arduino 2009/Uno
+UTFT myGLCD(ITDB32S,19,18,17,16);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for Arduino Mega
+//UTFT myGLCD(ITDB32S,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[318];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 319, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 226, 319, 239);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 227);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 319, 225);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+  for (int i=9; i<310; i+=10)
+    myGLCD.drawLine(i, 117, i, 121);
+  for (int i=19; i<220; i+=10)
+    myGLCD.drawLine(157, i, 161, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(sin(((i*1.13)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(cos(((i*1.13)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(tan(((i*1.13)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(318*20); i++) 
+  {
+    x++;
+    if (x==319)
+      x=1;
+    if (i>319)
+    {
+      if ((x==159)||(buf[x-1]==119))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=119+(sin(((i*1.1)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(70+(i*20), 30+(i*20), 130+(i*20), 90+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(190-(i*20), 30+(i*20), 250-(i*20), 90+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(100+(i*20),60+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 224);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(318, i, (i*1.44)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 331-(i*1.44), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(318, i, 330-(i*1.44), 224);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(256);
+    y=45+random(146);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(207);
+    x2=2+random(316);
+    y2=16+random(207);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(207);
+    x2=2+random(316);
+    y2=16+random(207);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(209);
+    x2=2+random(316);
+    y2=16+random(209);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(316), 16+random(209));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(80, 70, 239, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 210);
+  myGLCD.printNumI(millis(), CENTER, 225);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_320x240_Serial/UTFT_Demo_320x240_Serial.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_320x240_Serial/UTFT_Demo_320x240_Serial.ino
new file mode 100644
index 0000000..19f9d39
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_320x240_Serial/UTFT_Demo_320x240_Serial.ino	
@@ -0,0 +1,327 @@
+// UTFT_Demo_320x240_Serial (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for serial modules with a screen 
+// resolution of 320x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the line for your display:
+//UTFT myGLCD(TFT01_22SP,9,8,12,11,10);  // ElecFreaks TFT01-2.2SP
+UTFT myGLCD(MI0283QT9,11,13,7,8);        // Watterott MI0283QT9
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+// The following two lines are needed for the MI0283QT9 display
+// module to enable the backlight. If you are using any other 
+// display module these lines can be commented out.
+  pinMode(9, OUTPUT);
+  digitalWrite(9, HIGH);
+}
+
+void loop()
+{
+  int buf[318];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 319, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 226, 319, 239);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 227);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 319, 225);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+  for (int i=9; i<310; i+=10)
+    myGLCD.drawLine(i, 117, i, 121);
+  for (int i=19; i<220; i+=10)
+    myGLCD.drawLine(157, i, 161, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(sin(((i*1.13)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(cos(((i*1.13)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(tan(((i*1.13)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(318*20); i++) 
+  {
+    x++;
+    if (x==319)
+      x=1;
+    if (i>319)
+    {
+      if ((x==159)||(buf[x-1]==119))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=119+(sin(((i*1.1)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(70+(i*20), 30+(i*20), 130+(i*20), 90+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(190-(i*20), 30+(i*20), 250-(i*20), 90+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(100+(i*20),60+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 224);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(318, i, (i*1.44)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 331-(i*1.44), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(318, i, 330-(i*1.44), 224);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(256);
+    y=45+random(146);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(207);
+    x2=2+random(316);
+    y2=16+random(207);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(207);
+    x2=2+random(316);
+    y2=16+random(207);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(209);
+    x2=2+random(316);
+    y2=16+random(209);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(316), 16+random(209));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(80, 70, 239, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 210);
+  myGLCD.printNumI(millis(), CENTER, 225);
+  
+  delay (10000);
+}
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_400x240/UTFT_Demo_400x240.pde b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_400x240/UTFT_Demo_400x240.pde
new file mode 100644
index 0000000..ede8e1c
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_400x240/UTFT_Demo_400x240.pde	
@@ -0,0 +1,327 @@
+// UTFT_Demo_400x240 (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 400x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for Arduino 2009/Uno
+UTFT myGLCD(ITDB32WD,19,18,17,16);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for Arduino Mega
+//UTFT myGLCD(ITDB32WD,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[398];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 399, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 226, 399, 239);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("*** Universal Color TFT Display Library ***", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("< http://electronics.henningkarlsen.com >", CENTER, 227);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 399, 225);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(199, 15, 199, 224);
+  myGLCD.drawLine(1, 119, 398, 119);
+  for (int i=9; i<390; i+=10)
+    myGLCD.drawLine(i, 117, i, 121);
+  for (int i=19; i<220; i+=10)
+    myGLCD.drawLine(197, i, 201, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<398; i++)
+  {
+    myGLCD.drawPixel(i,119+(sin(((i*0.9)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<398; i++)
+  {
+    myGLCD.drawPixel(i,119+(cos(((i*0.9)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<398; i++)
+  {
+    y=119+(tan(((i*0.9)*3.14)/180));
+    if ((y>15) && (y<224))
+    myGLCD.drawPixel(i,y);
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(199, 15, 199, 224);
+  myGLCD.drawLine(1, 119, 398, 119);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(398*20); i++) 
+  {
+    x++;
+    if (x==399)
+      x=1;
+    if (i>399)
+    {
+      if ((x==199)||(buf[x-1]==119))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=119+(sin(((i)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(110+(i*20), 30+(i*20), 170+(i*20), 90+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(230-(i*20), 30+(i*20), 290-(i*20), 90+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(110+(i*30),60+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.77)-10, 224);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(398, i, (i*1.77)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 411-(i*1.77), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(398, i, 410-(i*1.77), 224);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(336);
+    y=45+random(146);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(396);
+    y=16+random(207);
+    x2=2+random(396);
+    y2=16+random(207);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(396);
+    y=16+random(207);
+    x2=2+random(396);
+    y2=16+random(207);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(396);
+    y=16+random(209);
+    x2=2+random(396);
+    y2=16+random(209);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(396), 16+random(209));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(120, 70, 279, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 210);
+  myGLCD.printNumI(millis(), CENTER, 225);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_480x272/UTFT_Demo_480x272.pde b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_480x272/UTFT_Demo_480x272.pde
new file mode 100644
index 0000000..3798dc1
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_480x272/UTFT_Demo_480x272.pde	
@@ -0,0 +1,324 @@
+// UTFT_Demo_480x272 (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 480x272 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for Arduino 2009/Uno
+//UTFT myGLCD(ITDB43,19,18,17,16);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for Arduino Mega
+UTFT myGLCD(ITDB43,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[478];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 479, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 258, 479, 271);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 259);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 479, 257);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(239, 15, 239, 256);
+  myGLCD.drawLine(1, 135, 478, 135);
+  for (int i=9; i<470; i+=10)
+    myGLCD.drawLine(i, 133, i, 138);
+  for (int i=15; i<256; i+=10)
+    myGLCD.drawLine(237, i, 241, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,135+(sin(((i*1.13)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,135+(cos(((i*1.13)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,135+(tan(((i*1.13)*3.14)/180)));
+  }
+
+  delay(2000);
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(239, 15, 239, 256);
+  myGLCD.drawLine(1, 135, 478, 135);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(478*20); i++) 
+  {
+    x++;
+    if (x==479)
+      x=1;
+    if (i>479)
+    {
+      if ((x==239)||(buf[x-1]==135))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=135+(sin(((i*1.65)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(150+(i*20), 46+(i*20), 210+(i*20), 106+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(330-(i*20), 46+(i*20), 270-(i*20), 106+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(180+(i*20),75+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<256; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.88)-10, 256);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=256; i>15; i-=5)
+  {
+    myGLCD.drawLine(478, i, (i*1.88)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=256; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 491-(i*1.88), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<256; i+=5)
+  {
+    myGLCD.drawLine(478, i, 490-(i*1.88), 256);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some random circles
+  for (int i=0; i<150; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(416);
+    y=45+random(178);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some random rectangles
+  for (int i=0; i<150; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(239);
+    x2=2+random(476);
+    y2=16+random(239);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<150; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(239);
+    x2=2+random(476);
+    y2=16+random(239);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+  for (int i=0; i<150; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(239);
+    x2=2+random(476);
+    y2=16+random(239);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,256);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(476), 16+random(239));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(160, 70, 319, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 243);
+  myGLCD.printNumI(millis(), CENTER, 258);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_480x320/UTFT_Demo_480x320.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_480x320/UTFT_Demo_480x320.ino
new file mode 100644
index 0000000..72f5652
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_480x320/UTFT_Demo_480x320.ino	
@@ -0,0 +1,325 @@
+// UTFT_Demo_480x320 (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 480x320 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for Arduino 2009/Uno
+//UTFT myGLCD(CTE32HR,19,18,17,16);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for Arduino Mega
+UTFT myGLCD(CTE32HR,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[478];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 479, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 306, 479, 319);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 307);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 479, 305);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(239, 15, 239, 304);
+  myGLCD.drawLine(1, 159, 478, 159);
+  for (int i=9; i<470; i+=10)
+    myGLCD.drawLine(i, 157, i, 161);
+  for (int i=19; i<220; i+=10)
+    myGLCD.drawLine(237, i, 241, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,159+(sin(((i*1.13)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,159+(cos(((i*1.13)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,159+(tan(((i*1.13)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(239, 15, 239, 304);
+  myGLCD.drawLine(1, 159, 478, 159);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(478*15); i++) 
+  {
+    x++;
+    if (x==479)
+      x=1;
+    if (i>479)
+    {
+      if ((x==239)||(buf[x-1]==159))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=159+(sin(((i*0.7)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(150+(i*20), 70+(i*20), 210+(i*20), 130+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(270-(i*20), 70+(i*20), 330-(i*20), 130+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(180+(i*20),100+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<304; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.6)-10, 304);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=304; i>15; i-=5)
+  {
+    myGLCD.drawLine(478, i, (i*1.6)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=304; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 491-(i*1.6), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<304; i+=5)
+  {
+    myGLCD.drawLine(478, i, 490-(i*1.6), 304);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(416);
+    y=45+random(226);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(289);
+    x2=2+random(476);
+    y2=16+random(289);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(289);
+    x2=2+random(476);
+    y2=16+random(289);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(289);
+    x2=2+random(476);
+    y2=16+random(289);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(476), 16+random(289));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(160, 70, 319, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 290);
+  myGLCD.printNumI(millis(), CENTER, 305);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_800x480/UTFT_Demo_800x480.pde b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_800x480/UTFT_Demo_800x480.pde
new file mode 100644
index 0000000..fa2d195
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Demo_800x480/UTFT_Demo_800x480.pde	
@@ -0,0 +1,284 @@
+// UTFT_Demo_800x480 (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 800x480 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for Arduino 2009/Uno
+//UTFT myGLCD(ITDB43,19,18,17,16);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for Arduino Mega
+UTFT myGLCD(ITDB50,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[798];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 799, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 466, 799, 479);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 467);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 799, 465);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(399, 15, 399, 464);
+  myGLCD.drawLine(1, 239, 798, 239);
+  for (int i=9; i<790; i+=10)
+    myGLCD.drawLine(i, 237, i, 242);
+  for (int i=19; i<470; i+=10)
+    myGLCD.drawLine(397, i, 402, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<798; i++)
+  {
+    myGLCD.drawPixel(i,239+(sin(((i*1.13)*3.14)/180)*200));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<798; i++)
+  {
+    myGLCD.drawPixel(i,239+(cos(((i*1.13)*3.14)/180)*200));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<798; i++)
+  {
+    myGLCD.drawPixel(i,239+(tan(((i*0.9)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(399, 15, 399, 464);
+  myGLCD.drawLine(1, 239, 798, 239);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(798*20); i++) 
+  {
+    x++;
+    if (x==799)
+      x=1;
+    if (i>799)
+    {
+      if ((x==399)||(buf[x-1]==239))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=239+(sin(((i*1.65)*3.14)/180)*(200-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random filled rectangles
+  for (int i=0; i<50; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(746);
+    y=16+random(397);
+    x2=x+50;
+    y2=y+50;
+    myGLCD.fillRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random filled, rounded rectangles
+  for (int i=0; i<50; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(746);
+    y=16+random(397);
+    x2=x+50;
+    y2=y+50;
+    myGLCD.fillRoundRect(x, y, x2, y2);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random filled circles
+  for (int i=0; i<50; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=27+random(746);
+    y=41+random(397);
+    myGLCD.fillCircle(x, y, 25);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<463; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.66)-10, 463);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=463; i>15; i-=5)
+  {
+    myGLCD.drawLine(798, i, (i*1.66)+30, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=463; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 770-(i*1.66), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<463; i+=5)
+  {
+    myGLCD.drawLine(798, i, 810-(i*1.66), 463);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random circles
+  for (int i=0; i<250; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(736);
+    y=45+random(386);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random rectangles
+  for (int i=0; i<250; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(796);
+    y=16+random(447);
+    x2=2+random(796);
+    y2=16+random(447);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<250; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(796);
+    y=16+random(447);
+    x2=2+random(796);
+    y2=16+random(447);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+  for (int i=0; i<250; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(796);
+    y=16+random(447);
+    x2=2+random(796);
+    y2=16+random(447);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(796), 16+random(447));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(320, 190, 479, 289);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 213);
+  myGLCD.print("Restarting in a", CENTER, 239);
+  myGLCD.print("few seconds...", CENTER, 252);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 450);
+  myGLCD.printNumI(millis(), CENTER, 465);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Leonardo_Demo_320x240/UTFT_Leonardo_Demo_320x240.ino b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Leonardo_Demo_320x240/UTFT_Leonardo_Demo_320x240.ino
new file mode 100644
index 0000000..4e8a9d1
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Leonardo_Demo_320x240/UTFT_Leonardo_Demo_320x240.ino	
@@ -0,0 +1,252 @@
+// UTFT_Leonardo_Demo_320x240 (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a reduced demo of how to use some of the functions
+// of the library with a supported display modules on an Arduino Leonardo.
+//
+// It has been reduced in size to fit in the limited flash memory of 
+// the Leonardo. It has not been tested on all display modules so
+// some modules may still produce too large binares.
+//
+// This demo was made for modules with a screen resolution 
+// of 320x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(ITDB24E_8,A5,A4,A3,A2);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[318];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 319, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 226, 319, 239);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 227);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 319, 225);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+  for (int i=9; i<310; i+=10)
+    myGLCD.drawLine(i, 117, i, 121);
+  for (int i=19; i<220; i+=10)
+    myGLCD.drawLine(157, i, 161, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(sin(((i*1.13)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(cos(((i*1.13)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(tan(((i*1.13)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(318*20); i++) 
+  {
+    x++;
+    if (x==319)
+      x=1;
+    if (i>319)
+    {
+      if ((x==159)||(buf[x-1]==119))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=119+(sin(((i*1.1)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(70+(i*20), 30+(i*20), 130+(i*20), 90+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(190-(i*20), 30+(i*20), 250-(i*20), 90+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(100+(i*20),60+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 224);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(318, i, (i*1.44)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 331-(i*1.44), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(318, i, 330-(i*1.44), 224);
+  }
+  
+  delay(2000);
+  
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(80, 70, 239, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 210);
+  myGLCD.printNumI(millis(), CENTER, 225);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Rotate_Bitmap/UTFT_Rotate_Bitmap.pde b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Rotate_Bitmap/UTFT_Rotate_Bitmap.pde
new file mode 100644
index 0000000..23d49e9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Rotate_Bitmap/UTFT_Rotate_Bitmap.pde	
@@ -0,0 +1,34 @@
+// UTFT_Rotate_Bitmap (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the drawBitmap()-function.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+#include 
+
+// Uncomment the next line for Arduino 2009/Uno
+UTFT myGLCD(ITDB32S,19,18,17,16);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for Arduino Mega
+//UTFT myGLCD(ITDB32S,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+extern unsigned int tux[0x400];
+
+void setup()
+{
+  myGLCD.InitLCD(LANDSCAPE);
+  myGLCD.fillScr(255, 255, 255);
+  myGLCD.setColor(0, 0, 0);
+}
+
+void loop()
+{
+    for (int i=0; i<360; i+=5)
+    {
+      myGLCD.drawBitmap (10, 10, 32, 32, tux, i, 16, 16);
+    }
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Rotate_Bitmap/tux.c b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Rotate_Bitmap/tux.c
new file mode 100644
index 0000000..3babe53
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Rotate_Bitmap/tux.c	
@@ -0,0 +1,73 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: tux.png
+// Time generated: 11.10.2010 22:51:32
+// Size          : 2 048 Bytes
+
+#include 
+
+const unsigned short tux[0x400] PROGMEM ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73C, 0x9CD3, 0x9CF3, 0xA514,   // 0x0010 (16)
+0x9CF3, 0x8C51, 0xAD75, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x5AEB, 0x7BEF, 0x9CD3, 0x94B2,   // 0x0030 (48)
+0x94B2, 0x94B2, 0x4228, 0x7BEF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x9CF3, 0x18E3, 0x630C, 0x4A49, 0x4A69,   // 0x0050 (80)
+0x4A69, 0x528A, 0x4A49, 0x0000, 0xC638, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x6B6D, 0x0000, 0x0020, 0x10A2, 0x1082,   // 0x0070 (112)
+0x0841, 0x0841, 0x0841, 0x0000, 0x630C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x528A, 0x4228, 0x8410, 0x0000, 0x0861,   // 0x0090 (144)
+0xAD55, 0xBDD7, 0x10A2, 0x0000, 0x2945, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x5ACB, 0x8C71, 0xE75D, 0x2126, 0x528B,   // 0x00B0 (176)
+0xE75D, 0xDEDB, 0x7BCF, 0x0000, 0x18E3, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x6B6D, 0x4A4A, 0x6B2A, 0x8BE7, 0xA48A,   // 0x00D0 (208)
+0x6B09, 0x4A8A, 0x8431, 0x0000, 0x2104, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00E0 (224)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x6B6E, 0x5204, 0xDE6A, 0xFFF7, 0xFFF8,   // 0x00F0 (240)
+0xD5AC, 0xBCAA, 0x5A66, 0x0000, 0x1082, 0xDEFB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8C10, 0xC540, 0xFFED, 0xFF2C, 0xFEEC,   // 0x0110 (272)
+0xFECC, 0xFE66, 0x8260, 0x0000, 0x0000, 0xB596, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0120 (288)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B3, 0x9C25, 0xFF20, 0xFE40, 0xFDA0,   // 0x0130 (304)
+0xFCC0, 0xF524, 0x836A, 0x0000, 0x0000, 0x630C, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x630C, 0x94B4, 0xFF13, 0xFD83, 0xF523,   // 0x0150 (336)
+0xE5CF, 0xF79E, 0xE71D, 0x0861, 0x0000, 0x0861, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0160 (352)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xCE59, 0x0841, 0xD69A, 0xFFFF, 0xFF7D, 0xF77D,   // 0x0170 (368)
+0xFFFF, 0xFFFF, 0xFFFF, 0x73AE, 0x0000, 0x0000, 0x4A69, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0180 (384)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0x10A2, 0x8410, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF,   // 0x0190 (400)
+0xFFFF, 0xFFDF, 0xFFFF, 0xCE59, 0x0000, 0x0000, 0x0000, 0x9492, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01A0 (416)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x52AA, 0x0020, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01B0 (432)
+0xFFDF, 0xFFDF, 0xF7BE, 0xFFDF, 0x3186, 0x0000, 0x0020, 0x0841, 0xCE79, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01C0 (448)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xC638, 0x0000, 0x52AA, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFDF,   // 0x01D0 (464)
+0xFFDF, 0xF7BE, 0xF79E, 0xFFFF, 0x9CF3, 0x0000, 0x0841, 0x0000, 0x39E7, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01E0 (480)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x5ACB, 0x0000, 0xBDF7, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFDF, 0xFFDF,   // 0x01F0 (496)
+0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0x3186, 0x0000, 0x0861, 0x0000, 0xAD55, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0200 (512)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73C, 0x0861, 0x4A49, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF,   // 0x0210 (528)
+0xF7BE, 0xF79E, 0xEF7D, 0xEF5D, 0xFFDF, 0x8410, 0x0000, 0x1082, 0x0000, 0x39E7, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0220 (544)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B2, 0x0000, 0xB596, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE,   // 0x0230 (560)
+0xF79E, 0xEF7D, 0xEF7D, 0xE73C, 0xF79E, 0xAD55, 0x0861, 0x10A2, 0x0861, 0x0841, 0xCE59, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0240 (576)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0x3185, 0x10A2, 0xE71C, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF79E,   // 0x0250 (592)
+0xEF7D, 0xEF7D, 0xEF5D, 0xE73C, 0xEF5D, 0xBDF7, 0x18C3, 0x18C3, 0x18C3, 0x0000, 0x8C71, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0260 (608)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B2, 0x0000, 0x39E7, 0xF7BE, 0xFFFF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF79E, 0xEF7D,   // 0x0270 (624)
+0xEF7D, 0xEF5D, 0xE73C, 0xE71C, 0xE71C, 0xC618, 0x18E3, 0x10A2, 0x10A2, 0x0020, 0x6B4D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0280 (640)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8C51, 0x38E0, 0x4A27, 0xFFFF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF79E, 0xEF7D, 0xEF7D,   // 0x0290 (656)
+0xEF5D, 0xE73C, 0xE71C, 0xDEFB, 0xDF1D, 0xBDF8, 0x39C7, 0x5ACB, 0x528A, 0x10A3, 0x738F, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02A0 (672)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDD6C, 0xFE2B, 0xBC45, 0xA513, 0xFFFF, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF5D,   // 0x02B0 (688)
+0xE73C, 0xE71C, 0xDEFB, 0xD6DC, 0xDD8E, 0xB3E4, 0x2124, 0x2965, 0x2945, 0x20C1, 0xB511, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF77C, 0xE5CF, 0xF60B, 0xFF9B, 0xFF54, 0x8B02, 0x7BF0, 0xFFDF, 0xF79E, 0xEF5D, 0xEF5D, 0xE73C,   // 0x02D0 (720)
+0xE71C, 0xDEFB, 0xDEDB, 0xCE7A, 0xED89, 0xDDAD, 0x0842, 0x0000, 0x0000, 0xAC69, 0xDD6B, 0xEFBF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02E0 (736)
+0xFFFF, 0xFFFF, 0xFFBE, 0xE5CB, 0xEDC9, 0xFE4B, 0xFF14, 0xFEF3, 0xFF35, 0xFE8D, 0x51C1, 0x634E, 0xE73C, 0xEF5D, 0xE73C, 0xE71C,   // 0x02F0 (752)
+0xDEFB, 0xDEDB, 0xD6DB, 0xCE59, 0xE58B, 0xFF98, 0xBD4F, 0x8B88, 0xCD90, 0xFFB7, 0xCCE8, 0xE73D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xEF3B, 0xF583, 0xFF30, 0xFF11, 0xFECF, 0xFEEF, 0xFECF, 0xFF30, 0xDD46, 0x2903, 0x6B8E, 0xEF7D, 0xE71C, 0xDEFB,   // 0x0310 (784)
+0xDEDB, 0xD6BA, 0xD69A, 0xCE59, 0xE5AA, 0xFF11, 0xFF53, 0xFF73, 0xFF33, 0xFF12, 0xFE6C, 0xDDAD, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0320 (800)
+0xFFFF, 0xFFFF, 0xF79E, 0xEDC5, 0xFECB, 0xFECC, 0xFECC, 0xFEEC, 0xFECB, 0xFECC, 0xFEEA, 0x9BE5, 0x8432, 0xE73C, 0xDEDB, 0xDEDB,   // 0x0330 (816)
+0xD6BA, 0xD69A, 0xDEDB, 0xA4F3, 0xD547, 0xFF2E, 0xFECD, 0xFECE, 0xFEEE, 0xFEEE, 0xFF10, 0xFEAB, 0xE5A8, 0xEF7D, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xF79E, 0xF603, 0xFEA2, 0xFEC7, 0xFEC7, 0xFEA4, 0xFE81, 0xFE61, 0xFEA4, 0xFE43, 0xDE33, 0xE75E, 0xE71C, 0xDEFB,   // 0x0350 (848)
+0xDEDB, 0xCE58, 0x8C72, 0x5247, 0xEDE4, 0xFF0A, 0xFECA, 0xFEC9, 0xFE84, 0xFE83, 0xFEE7, 0xFEA3, 0xB443, 0xD69B, 0xFFFF, 0xFFFF,   // 0x0360 (864)
+0xFFFF, 0xFFFF, 0xF75B, 0xFE60, 0xFF00, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEE0, 0xE5C1, 0x9492, 0xA514, 0x9CD3,   // 0x0370 (880)
+0x8410, 0x630B, 0x4229, 0x6AE8, 0xFE80, 0xFEC1, 0xFEC1, 0xFEA0, 0xFEA0, 0xFEE0, 0xDD80, 0x9BE8, 0xB597, 0xFFDF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xF79E, 0xD589, 0xE600, 0xFEA0, 0xFF00, 0xFF40, 0xFF40, 0xFF00, 0xFF00, 0xFF20, 0xFEC0, 0x5267, 0x4229, 0x4A48,   // 0x0390 (912)
+0x4A49, 0x5289, 0x424A, 0x7B46, 0xFF20, 0xFEE0, 0xFEE0, 0xFF20, 0xFEE0, 0xB4A5, 0x9C92, 0xDEFD, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xFFFF, 0xE71D, 0xBDB6, 0xB530, 0xBD0B, 0xCD65, 0xEE60, 0xFF40, 0xFFA0, 0xFF80, 0xBD03, 0x8410, 0xA514, 0xA534,   // 0x03B0 (944)
+0xAD75, 0xB596, 0xA555, 0x9C8F, 0xF6C0, 0xFFA0, 0xFFA0, 0xF6E0, 0xA449, 0xB5B8, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7F, 0xD69C, 0xBD95, 0xBD4C, 0xCDC6, 0xB4E8, 0xAD35, 0xF7BF, 0xFFFF, 0xFFFF,   // 0x03D0 (976)
+0xFFFF, 0xFFFF, 0xFFFF, 0xF7BF, 0xCDD0, 0xCDC6, 0xCDA7, 0xA48D, 0xCE7B, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDF1F, 0xB59A, 0xBDDA, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFDF, 0xFFDF, 0xFFFF, 0xEF7F, 0xB59A, 0xAD59, 0xDF1D, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Textrotation_Demo/UTFT_Textrotation_Demo.pde b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Textrotation_Demo/UTFT_Textrotation_Demo.pde
new file mode 100644
index 0000000..92002bf
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_Textrotation_Demo/UTFT_Textrotation_Demo.pde	
@@ -0,0 +1,48 @@
+// UTFT_Textrotation_Demo (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the textrotation-functions.
+//
+// This demo was made for modules with a screen resolution 
+// of 320x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t BigFont[];
+extern uint8_t SevenSegNumFont[];
+
+// Uncomment the next line for Arduino 2009/Uno
+UTFT myGLCD(ITDB32S,19,18,17,16);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for Arduino Mega
+//UTFT myGLCD(ITDB32S,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  myGLCD.InitLCD();
+  myGLCD.clrScr();
+  myGLCD.setFont(BigFont);
+}
+
+void loop()
+{
+    myGLCD.print("Text rotation", 0, 0);
+    myGLCD.setColor(0, 0, 255);
+    myGLCD.print("0 degrees", 0, 16, 0);
+    myGLCD.print("90 degrees", 319, 0, 90);
+    myGLCD.print("180 degrees", 319, 239, 180);
+    myGLCD.print("270 degrees", 0, 239, 270);
+
+    myGLCD.setFont(SevenSegNumFont);
+    myGLCD.setColor(0, 255, 0);
+    myGLCD.print("45", 90, 100, 45);
+    myGLCD.print("90", 200, 50, 90);
+    myGLCD.print("180", 300, 200, 180);
+
+  while (true) {};
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_ViewFont/UTFT_ViewFont.pde b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_ViewFont/UTFT_ViewFont.pde
new file mode 100644
index 0000000..c2284ce
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/Arduino (AVR)/UTFT_ViewFont/UTFT_ViewFont.pde	
@@ -0,0 +1,55 @@
+// UTFT_ViewFont (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the included fonts.
+//
+// This demo was made for modules with a screen resolution 
+// of 320x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+extern uint8_t BigFont[];
+extern uint8_t SevenSegNumFont[];
+
+// Uncomment the next line for Arduino 2009/Uno
+UTFT myGLCD(ITDB32S,19,18,17,16);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for Arduino Mega
+//UTFT myGLCD(ITDB32S,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  myGLCD.InitLCD();
+
+  myGLCD.clrScr();
+}
+
+void loop()
+{
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 0);
+
+  myGLCD.setFont(BigFont);
+  myGLCD.print(" !\"#$%&'()*+,-./", CENTER, 0);
+  myGLCD.print("0123456789:;<=>?", CENTER, 16);
+  myGLCD.print("@ABCDEFGHIJKLMNO", CENTER, 32);
+  myGLCD.print("PQRSTUVWXYZ[\\]^_", CENTER, 48);
+  myGLCD.print("`abcdefghijklmno", CENTER, 64);
+  myGLCD.print("pqrstuvwxyz{|}~ ", CENTER, 80);
+
+  myGLCD.setFont(SmallFont);
+  myGLCD.print(" !\"#$%&'()*+,-./0123456789:;<=>?", CENTER, 120);
+  myGLCD.print("@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_", CENTER, 132);
+  myGLCD.print("`abcdefghijklmnopqrstuvwxyz{|}~ ", CENTER, 144);
+
+  myGLCD.setFont(SevenSegNumFont);
+  myGLCD.print("0123456789", CENTER, 190);
+
+  while(1) {};
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap/UTFT_Bitmap.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap/UTFT_Bitmap.pde
new file mode 100644
index 0000000..4574d9f
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap/UTFT_Bitmap.pde
@@ -0,0 +1,62 @@
+// UTFT_Bitmap (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the drawBitmap()-function.
+//
+// This demo was made to work on the 320x240 modules.
+// Any other size displays may cause strange behaviour.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for chipKit Uno32/uC32
+UTFT myGLCD(ITDB24D,34,35,36,37);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for chipKit Max32
+//UTFT myGLCD(ITDB24D,82,83,84,85);   // Remember to change the model parameter to suit your display module!
+
+extern unsigned short info[0x400];
+extern unsigned short icon[0x400];
+extern unsigned short tux[0x400];
+
+void setup()
+{
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  myGLCD.fillScr(255, 255, 255);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.print(" *** A 10 by 7 grid of a 32x32 icon *** ", CENTER, 228);
+  for (int x=0; x<10; x++)
+    for (int y=0; y<7; y++)
+      myGLCD.drawBitmap (x*32, y*32, 32, 32, info);
+
+  delay(5000);
+  
+  myGLCD.fillScr(255, 255, 255);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.print("   Two different icons in scale 1 to 4  ", CENTER, 228);
+  int x=0;
+  for (int s=0; s<4; s++)
+  {
+    x+=(s*32);
+    myGLCD.drawBitmap (x, 0, 32, 32, tux, s+1);
+  }
+  x=0;
+  for (int s=4; s>0; s--)
+  {
+    myGLCD.drawBitmap (x, 224-(s*32), 32, 32, icon, s);
+    x+=(s*32);
+  }
+
+  delay(5000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap/icon.c b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap/icon.c
new file mode 100644
index 0000000..9cb97a1
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap/icon.c
@@ -0,0 +1,71 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: taskmgr.png
+// Time generated: 11.10.2010 22:51:23
+// Size          : 2 048 Bytes
+
+const unsigned short icon[0x400] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0xCE79, 0xBDD7, 0xAD75,   // 0x0010 (16)
+0xAD55, 0xAD75, 0xBDF7, 0xD6BA, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xC638, 0x9492, 0x8C51, 0x9492, 0xA514, 0xA534,   // 0x0030 (48)
+0xA534, 0xA534, 0x9CF3, 0x8C71, 0x8430, 0x9CD3, 0xD69A, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCE59, 0x8410, 0x9492, 0xB5B6, 0xC618, 0xBDD7, 0xAD75, 0xA514,   // 0x0050 (80)
+0xA514, 0xA4F4, 0xAD55, 0xB5B6, 0xBDD7, 0xAD55, 0x8430, 0x8C71, 0xDEFB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x9CD3, 0x8430, 0xBDF7, 0xC618, 0xAD75, 0x94F2, 0x8CF1, 0x84B0, 0x8CD1,   // 0x0070 (112)
+0x9612, 0x8CB1, 0x7C6F, 0x7C8F, 0x8490, 0xA533, 0xBDF7, 0xB596, 0x7BEF, 0xB596, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x8430, 0x9CF3, 0xCE39, 0xA514, 0x94B2, 0x9E93, 0x94F2, 0x8CD1, 0x8CB1, 0x9D12,   // 0x0090 (144)
+0x9F74, 0x9D52, 0x8450, 0x7C8F, 0x73AE, 0x740E, 0x73CE, 0x9CD3, 0xC638, 0x8C51, 0x9CD3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x8430, 0xA534, 0xBDF7, 0x8CB1, 0x8C31, 0x9DB3, 0xA735, 0x9D13, 0x8CB1, 0x8C71, 0x9D13,   // 0x00B0 (176)
+0xB756, 0xA5D4, 0x8C71, 0x8490, 0x8390, 0x7C70, 0x73EE, 0x6B4D, 0x8450, 0xBDF7, 0x8C71, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x94B2, 0x9CF3, 0xBDD7, 0x8490, 0x8CF1, 0x9D72, 0xA694, 0xAE94, 0x9DD3, 0xA593, 0xA553, 0x9592,   // 0x00D0 (208)
+0x9672, 0x75CE, 0x5BAA, 0x64EB, 0x5D8C, 0x5BCA, 0x4B69, 0x634C, 0x748D, 0x7C4F, 0xBE18, 0x8430, 0xB5B6, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00E0 (224)
+0xFFFF, 0xFFFF, 0xFFFF, 0xC618, 0x8410, 0xBDF7, 0x8410, 0x83F0, 0x94F2, 0x9613, 0x9D13, 0xAE55, 0x9D12, 0x750E, 0x55CB, 0x4BC8,   // 0x00F0 (240)
+0x4447, 0x3BC6, 0x4B67, 0x44E8, 0x3CE8, 0x3325, 0x20E2, 0x2B45, 0x43E7, 0x3946, 0x732D, 0xC5F8, 0x7BCF, 0xE71C, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xF7BE, 0x7BEF, 0xBDB6, 0x9533, 0x8D71, 0x9552, 0x9E73, 0x9DD3, 0x94B2, 0x6D6D, 0x4BA8, 0x44A8, 0x55EA, 0x5D2A,   // 0x0110 (272)
+0x43E7, 0x4327, 0x46CA, 0x4B87, 0x42C6, 0x4E0A, 0x4D09, 0x4468, 0x4548, 0x3386, 0x2B25, 0x7C6F, 0xAD35, 0x9492, 0xFFFF, 0xFFFF,   // 0x0120 (288)
+0xFFDF, 0xFFFF, 0xBDD7, 0x8C71, 0xAD75, 0x8CF0, 0x8D71, 0x8D51, 0x9DF3, 0x740E, 0x21C4, 0x33E5, 0x558A, 0x554A, 0x650A, 0x566B,   // 0x0130 (304)
+0x43E7, 0x21C3, 0x3345, 0x2283, 0x1962, 0x3C87, 0x3386, 0x2163, 0x3345, 0x3346, 0x33A6, 0x32C6, 0x9CB3, 0x7BEF, 0xDEDB, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0x8430, 0xAD75, 0x8C31, 0x7C0F, 0x7BCF, 0x83F0, 0x636B, 0x0000, 0x0000, 0x4387, 0x462A, 0x4B27, 0x4B88, 0x4E8B,   // 0x0150 (336)
+0x42E6, 0x0000, 0x0020, 0x0100, 0x0000, 0x1121, 0x0040, 0x0000, 0x0941, 0x0000, 0x0020, 0x00E0, 0x5AAB, 0x94B2, 0x9CD3, 0xFFFF,   // 0x0160 (352)
+0xFFFF, 0xE71C, 0x8410, 0xB596, 0x7BEF, 0x7C6F, 0x84B0, 0x5B6B, 0x09E1, 0x0901, 0x1161, 0x3C06, 0x3D89, 0x32C5, 0x43E7, 0x470B,   // 0x0170 (368)
+0x4BC7, 0x0961, 0x11E2, 0x1282, 0x0961, 0x1262, 0x09E2, 0x0961, 0x12A2, 0x0961, 0x09C2, 0x0A01, 0x29E5, 0xA514, 0x7BEF, 0xFFDF,   // 0x0180 (384)
+0xFFFF, 0xBDD7, 0x9472, 0xA514, 0x6B4D, 0x7C6F, 0x634C, 0x0040, 0x0981, 0x0060, 0x00E0, 0x11E2, 0x10A1, 0x09C1, 0x19E3, 0x2B25,   // 0x0190 (400)
+0x22A3, 0x0060, 0x0120, 0x09E1, 0x0060, 0x09E1, 0x0120, 0x0060, 0x0A21, 0x0060, 0x0100, 0x01A0, 0x0040, 0x9CD3, 0x7BEF, 0xDEDB,   // 0x01A0 (416)
+0xFFFF, 0xA514, 0x9CF3, 0xB596, 0x73AE, 0x7C0F, 0x2945, 0x10A2, 0x2184, 0x18C3, 0x1923, 0x2184, 0x18C3, 0x21A4, 0x2964, 0x2905,   // 0x01B0 (432)
+0x2A25, 0x2104, 0x2965, 0x2A05, 0x2104, 0x2A05, 0x2985, 0x2104, 0x2A25, 0x2104, 0x2164, 0x29C4, 0x3166, 0xB5B6, 0x8410, 0xC618,   // 0x01C0 (448)
+0xFFFF, 0x9492, 0xA514, 0xDEDB, 0xC618, 0xA514, 0x8C51, 0x94B2, 0x9CB3, 0x9CF3, 0xA514, 0xA534, 0xAD75, 0xAD75, 0xB596, 0xB5D6,   // 0x01D0 (464)
+0xBDB7, 0xBDF7, 0xBDF7, 0xBDF7, 0xC618, 0xC5F8, 0xC5F8, 0xBDF7, 0xBDD7, 0xBDD7, 0xB5B6, 0xB596, 0xC638, 0xDEFB, 0x8430, 0xB596,   // 0x01E0 (480)
+0xFFFF, 0x8C51, 0x9CF3, 0xE73C, 0xDEFB, 0xD69A, 0xD6BA, 0xD6BA, 0xDEDB, 0xDEDB, 0xDEFB, 0xDF1B, 0xE71C, 0xE73C, 0xE73C, 0xE73C,   // 0x01F0 (496)
+0xEF5D, 0xEF5D, 0xEF5D, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xDEFB, 0xE71C, 0x8C51, 0xAD75,   // 0x0200 (512)
+0xFFFF, 0x8C71, 0x9CD3, 0xDEFB, 0xAD75, 0x9492, 0x9CD3, 0xA4F3, 0xA514, 0xAD55, 0xAD75, 0xB596, 0xBDB6, 0xBDD7, 0xC5F7, 0xC618,   // 0x0210 (528)
+0xC638, 0xCE59, 0xCE59, 0xCE79, 0xD679, 0xD679, 0xCE79, 0xCE59, 0xCE59, 0xC638, 0xC618, 0xBDF7, 0xCE79, 0xE71C, 0x8C51, 0xB596,   // 0x0220 (544)
+0xFFFF, 0x9CD3, 0x9492, 0xAD55, 0x2965, 0x2104, 0x2124, 0x2145, 0x1945, 0x2165, 0x2165, 0x2186, 0x2186, 0x29A6, 0x29A6, 0x31C7,   // 0x0230 (560)
+0x39C7, 0x31E7, 0x31E7, 0x31E7, 0x3208, 0x3208, 0x31E7, 0x31E7, 0x29E7, 0x31C7, 0x39C7, 0x31A6, 0x4A49, 0xBDF7, 0x8C51, 0xBDF7,   // 0x0240 (576)
+0xFFFF, 0xB5B6, 0x8430, 0x7BEF, 0x0000, 0x0000, 0x0000, 0x2000, 0x3000, 0x3000, 0x3000, 0x3000, 0x3000, 0x3000, 0x3800, 0x2000,   // 0x0250 (592)
+0x0000, 0x3000, 0x3800, 0x3000, 0x3800, 0x3800, 0x3800, 0x3000, 0x3800, 0x0800, 0x0000, 0x0000, 0x0000, 0xA514, 0x8430, 0xD6BA,   // 0x0260 (608)
+0xFFFF, 0xDEDB, 0x7BCF, 0x8430, 0x0020, 0x0000, 0x0000, 0x8000, 0xC800, 0xC000, 0xC800, 0xC820, 0xC820, 0xC820, 0xD020, 0x9800,   // 0x0270 (624)
+0x0000, 0xB820, 0xD020, 0xD020, 0xD020, 0xD020, 0xD020, 0xC820, 0xD020, 0x4800, 0x0000, 0x0000, 0x2144, 0xAD75, 0x8410, 0xF7BE,   // 0x0280 (640)
+0xFFFF, 0xFFFF, 0x7BEF, 0x8C71, 0x2945, 0x0000, 0x0000, 0x6800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xB000, 0x8000,   // 0x0290 (656)
+0x0000, 0x9800, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0x4000, 0x0000, 0x0000, 0x632C, 0xA534, 0x94B2, 0xFFFF,   // 0x02A0 (672)
+0xFFDF, 0xFFFF, 0xAD75, 0x73AE, 0x632C, 0x0000, 0x0000, 0x6920, 0xA9E0, 0xA1C0, 0xA9E0, 0xA9E0, 0xA9E0, 0xA9E0, 0xA9E0, 0x7960,   // 0x02B0 (688)
+0x0000, 0x99C0, 0xB200, 0xA9E0, 0xB200, 0xB200, 0xB1E0, 0xA9E0, 0xB200, 0x40C0, 0x0000, 0x1082, 0xAD75, 0x8410, 0xD69A, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xF79E, 0x630C, 0x8C51, 0x2965, 0x0000, 0x7400, 0xB620, 0xAE00, 0xB620, 0xB640, 0xB640, 0xB620, 0xB660, 0x84A0,   // 0x02D0 (720)
+0x0000, 0xA5A0, 0xBE60, 0xB660, 0xBE60, 0xBE60, 0xB660, 0xB640, 0xBE80, 0x4260, 0x0000, 0x6B6D, 0xAD75, 0x8430, 0xFFFF, 0xFFFF,   // 0x02E0 (736)
+0xFFFF, 0xFFDF, 0xFFFF, 0xB5B6, 0x632C, 0x8410, 0x0021, 0x7360, 0xBD40, 0xB520, 0xBD40, 0xBD60, 0xBD60, 0xBD40, 0xC580, 0x8C00,   // 0x02F0 (752)
+0x0000, 0xACE0, 0xC580, 0xC580, 0xC580, 0xC580, 0xC580, 0xBD60, 0xC5A0, 0x39C0, 0x2126, 0xBDF7, 0x73AE, 0xD6BA, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x7BEF, 0x7BEF, 0x630D, 0x4AE1, 0x6D21, 0x6D01, 0x6D21, 0x6D41, 0x6D41, 0x6D41, 0x6D61, 0x53E1,   // 0x0310 (784)
+0x0000, 0x64C1, 0x7562, 0x6D62, 0x6D62, 0x6D62, 0x6D62, 0x6D42, 0x6D41, 0x4263, 0xA515, 0x8C51, 0xA534, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0320 (800)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0x6B4D, 0x8410, 0x636E, 0x04A6, 0x05E5, 0x05C5, 0x0585, 0x0585, 0x0586, 0x05A6, 0x0424,   // 0x0330 (816)
+0x0000, 0x0505, 0x05C6, 0x05A6, 0x05A6, 0x05C7, 0x0606, 0x0606, 0x1CE9, 0xA535, 0x9492, 0x8C71, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x6B4D, 0x83EF, 0x9411, 0x3A47, 0x0403, 0x0584, 0x05A4, 0x0585, 0x0585, 0x0404,   // 0x0350 (848)
+0x0000, 0x04E5, 0x05A5, 0x05A5, 0x05C5, 0x0584, 0x1405, 0x634B, 0xBD76, 0x8C51, 0x8C51, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0360 (864)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x8410, 0x6B6D, 0x9CB3, 0x7C6F, 0x3CA9, 0x0BE4, 0x0443, 0x0504, 0x03C2,   // 0x0370 (880)
+0x0000, 0x0483, 0x0504, 0x0444, 0x1426, 0x552D, 0xA554, 0xB576, 0x73CE, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB5B6, 0x6B4D, 0x7BAF, 0x9432, 0x8BD1, 0x6BCE, 0x4C6B, 0x3C09,   // 0x0390 (912)
+0x3186, 0x3C8A, 0x5C8C, 0x8430, 0xA493, 0xACD4, 0x8410, 0x7BEF, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xAD75, 0x7BEF, 0x73AE, 0x83F0, 0x8C11, 0x9431,   // 0x03B0 (944)
+0x9492, 0x9452, 0x9432, 0x8430, 0x7BEF, 0x8450, 0xBDF7, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEFB, 0xBDD7, 0xA534, 0x94D3,   // 0x03D0 (976)
+0x94B2, 0x9CF3, 0xA554, 0xC618, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap/info.c b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap/info.c
new file mode 100644
index 0000000..312bee1
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap/info.c
@@ -0,0 +1,71 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: info.png
+// Time generated: 11.10.2010 22:27:55
+// Size          : 2 048 Bytes
+
+const unsigned short info[0x400] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0010 (16)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF9F, 0xC69D, 0x95BB, 0x7D1A, 0x6CB9,   // 0x0030 (48)
+0x6499, 0x74F9, 0x8D7A, 0xB63C, 0xE73E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAE1C, 0x4C18, 0x2B56, 0x3397, 0x4C38, 0x64B9, 0x751A,   // 0x0050 (80)
+0x7D3A, 0x6CD9, 0x5458, 0x3BD7, 0x2B56, 0x3BB7, 0x855A, 0xE77E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xA5FB, 0x2B56, 0x2B77, 0x751A, 0xB67C, 0xD73E, 0xE75E, 0xE77E, 0xE77E,   // 0x0070 (112)
+0xE77E, 0xE77E, 0xE75E, 0xDF3E, 0xC6DD, 0x8D9B, 0x43D7, 0x1B16, 0x74D9, 0xF7BF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF9F, 0x4C18, 0x1AF6, 0x855A, 0xCEFE, 0xD71E, 0xCEFD, 0xC6DD, 0xC6BD, 0xC6BD, 0xBEBD,   // 0x0090 (144)
+0xC6BD, 0xBEBD, 0xC6BD, 0xC6DD, 0xC6DD, 0xD71E, 0xD71E, 0xA61C, 0x33B7, 0x2316, 0xBE7C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDF3E, 0x2336, 0x3BD7, 0xBE9D, 0xC6DD, 0xBE9D, 0xBE9D, 0xBE9D, 0xBEBD, 0xBE9D, 0xCEFD, 0xEF9F,   // 0x00B0 (176)
+0xEF9F, 0xD73E, 0xBE9D, 0xBEBD, 0xBE9D, 0xBE9D, 0xB69D, 0xC6BD, 0xCEDD, 0x6CFA, 0x0295, 0x9DBB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xE75E, 0x1AF6, 0x4C58, 0xBEBD, 0xB67D, 0xAE5C, 0xB67D, 0xB67D, 0xB69D, 0xB67D, 0xBEBD, 0xF7DF, 0xFFFF,   // 0x00D0 (208)
+0xFFFF, 0xFFFF, 0xCF1E, 0xB67D, 0xB67D, 0xB67D, 0xB67D, 0xAE5C, 0xAE5C, 0xC6BD, 0x857B, 0x0295, 0xA5DB, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00E0 (224)
+0xFFFF, 0xFFFF, 0xFFDF, 0x3BB7, 0x33D8, 0xB67D, 0xA63C, 0xA63C, 0xAE5C, 0xAE5D, 0xAE5D, 0xAE7D, 0xA65D, 0xC6DD, 0xFFFF, 0xFFFF,   // 0x00F0 (240)
+0xFFDF, 0xFFFF, 0xDF5E, 0xA65D, 0xAE7D, 0xAE5D, 0xAE5D, 0xAE5C, 0xA63C, 0xA61C, 0xB67D, 0x753A, 0x0295, 0xCEBC, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xF7DF, 0xFFFF, 0x957A, 0x12F6, 0x9E1C, 0x9E1C, 0x9E1C, 0x9E1C, 0xA63C, 0xA63C, 0xA63D, 0xA63D, 0xA65D, 0x9DFC, 0xDF3E, 0xFFFF,   // 0x0110 (272)
+0xFFFF, 0xFFDF, 0xA61C, 0xA65D, 0xA65D, 0xA63D, 0xA63C, 0xA63C, 0x9E1C, 0x9E1C, 0x9DFC, 0xAE3C, 0x3C18, 0x3396, 0xFFDF, 0xFFFF,   // 0x0120 (288)
+0xFFFF, 0xF79F, 0x2336, 0x64DA, 0x9DFC, 0x95DC, 0x95FC, 0x95FC, 0x9E1C, 0x9E1C, 0x9E3D, 0x9E3D, 0x9E3D, 0x9E3D, 0x7D3B, 0xA63C,   // 0x0130 (304)
+0xB6BD, 0x8DBB, 0x8DFC, 0xA65D, 0x9E3D, 0x9E3D, 0x9E1C, 0x9E1C, 0x95FC, 0x95FC, 0x95DC, 0x95DC, 0x8DBB, 0x0AF6, 0xA5DA, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xA5FB, 0x1337, 0x8DBB, 0x8DBB, 0x8DBC, 0x8DDC, 0x95FC, 0x95FC, 0x961C, 0x961D, 0x963D, 0x9E3D, 0x963D, 0xA67D, 0xB6BD,   // 0x0150 (336)
+0xB6BD, 0xAE7D, 0x9E3D, 0x9E3D, 0x961D, 0x961D, 0x961C, 0x95FC, 0x95FC, 0x8DDC, 0x8DDC, 0x859B, 0x95DC, 0x3C18, 0x4BD7, 0xFFFF,   // 0x0160 (352)
+0xFFFF, 0x6499, 0x33F8, 0x8DBB, 0x859B, 0x85BC, 0x85BC, 0x8DDC, 0x8DFC, 0x8DFD, 0x8E1D, 0x961D, 0x961D, 0x9E3D, 0xF7BF, 0xFFFF,   // 0x0170 (368)
+0xFFFF, 0xFFFF, 0xA67D, 0x8E1D, 0x961D, 0x8E1D, 0x8DFD, 0x8DFC, 0x8DDC, 0x85BC, 0x85BC, 0x859B, 0x859B, 0x5CDA, 0x2336, 0xE71C,   // 0x0180 (384)
+0xFFFF, 0x43F8, 0x4C79, 0x859B, 0x7D7B, 0x7D9C, 0x85BC, 0x85DC, 0x85DC, 0x8DFD, 0x8DFD, 0x8E1D, 0x8E1D, 0xA67E, 0xFFFF, 0xFFFF,   // 0x0190 (400)
+0xFFFF, 0xFFFF, 0xBEDE, 0x85FD, 0x8E1D, 0x8DFD, 0x8DFD, 0x85DC, 0x85DC, 0x85BC, 0x7D9C, 0x7D7B, 0x7D7B, 0x753B, 0x1B36, 0xBE5A,   // 0x01A0 (416)
+0xFFBE, 0x3BF8, 0x3419, 0x6D1B, 0x757B, 0x7D9C, 0x7D9C, 0x7DBC, 0x7DDD, 0x85FD, 0x85FD, 0x861D, 0x861D, 0x9E7E, 0xFFFF, 0xFFFF,   // 0x01B0 (432)
+0xFFFF, 0xFFFF, 0xB6DE, 0x85FD, 0x8E1D, 0x85FD, 0x85FD, 0x7DDD, 0x7DBC, 0x7D9C, 0x7D9C, 0x757B, 0x6D3B, 0x4C9A, 0x1337, 0xADD9,   // 0x01C0 (448)
+0xFFBE, 0x4418, 0x23B9, 0x3439, 0x4CBA, 0x653B, 0x759C, 0x7DBD, 0x7DDD, 0x7DFD, 0x861D, 0x861E, 0x861E, 0x9E7E, 0xFFFF, 0xFFFF,   // 0x01D0 (464)
+0xFFFF, 0xFFFF, 0xB6DE, 0x7E1E, 0x861E, 0x85FD, 0x7DFD, 0x7DDD, 0x7DBD, 0x759C, 0x653B, 0x4CDB, 0x3439, 0x2BF9, 0x1337, 0xA5B9,   // 0x01E0 (480)
+0xFF9E, 0x4C39, 0x2BF9, 0x345A, 0x3C7A, 0x3C9B, 0x4CFC, 0x5D5C, 0x659D, 0x75DD, 0x7DFE, 0x861E, 0x7E3E, 0x969F, 0xFFFF, 0xFFFF,   // 0x01F0 (496)
+0xFFFF, 0xFFFF, 0xB6FF, 0x7E1E, 0x863E, 0x7DFE, 0x75DD, 0x6D9D, 0x5D5C, 0x4CFC, 0x3C9B, 0x347A, 0x345A, 0x343A, 0x1B78, 0xA5B9,   // 0x0200 (512)
+0xF79E, 0x4418, 0x2C3A, 0x3C7A, 0x449B, 0x44DB, 0x4CFC, 0x4D3C, 0x555D, 0x5D7D, 0x65BE, 0x6DFE, 0x6DFF, 0x867F, 0xFFFF, 0xFFFF,   // 0x0210 (528)
+0xFFFF, 0xFFFF, 0xA6DF, 0x65FF, 0x6DFE, 0x65BE, 0x5D9E, 0x555D, 0x4D3C, 0x4CFC, 0x44DB, 0x44BB, 0x3C7A, 0x345A, 0x1B78, 0xA599,   // 0x0220 (544)
+0xFFDE, 0x43D8, 0x345A, 0x3C9A, 0x44DB, 0x4CFC, 0x4D3C, 0x555D, 0x5D9D, 0x5DBE, 0x65DE, 0x6DFF, 0x661F, 0x867F, 0xFFFF, 0xFFFF,   // 0x0230 (560)
+0xFFFF, 0xFFFF, 0xA6DF, 0x65FF, 0x6DFF, 0x65DE, 0x5DBE, 0x5D9D, 0x555D, 0x4D3C, 0x4CFC, 0x44DB, 0x3C7A, 0x3C9B, 0x1B57, 0xADB9,   // 0x0240 (576)
+0xFFFF, 0x4BD7, 0x2C1A, 0x44DB, 0x44DB, 0x4D1C, 0x555D, 0x5D7D, 0x5DBE, 0x65DE, 0x6E1F, 0x6E3F, 0x765F, 0x96BF, 0xFFFF, 0xFFFF,   // 0x0250 (592)
+0xFFFF, 0xFFFF, 0xAEFF, 0x6E3F, 0x763F, 0x6E1F, 0x65DE, 0x5DBE, 0x5D7D, 0x555D, 0x4D1C, 0x44DC, 0x3C9B, 0x44DC, 0x1AD5, 0xC639,   // 0x0260 (608)
+0xFFFF, 0x84D8, 0x1317, 0x5D7D, 0x44DB, 0x553C, 0x557D, 0x5D9E, 0x65DE, 0x65FF, 0x6E3F, 0x7E5F, 0x7E7F, 0x9EDF, 0xFFFF, 0xFFFF,   // 0x0270 (624)
+0xFFFF, 0xFFFF, 0xB73F, 0x7E7F, 0x7E5F, 0x6E3F, 0x65FF, 0x65DE, 0x5D9E, 0x557D, 0x553C, 0x44DC, 0x4D1C, 0x345B, 0x22B4, 0xE71B,   // 0x0280 (640)
+0xFFFF, 0xD6BC, 0x0234, 0x4CFC, 0x5D7D, 0x4D3C, 0x5D9D, 0x5DBE, 0x65FF, 0x6E3F, 0x765F, 0x867F, 0x8EBF, 0xA6DF, 0xFFFF, 0xFFFF,   // 0x0290 (656)
+0xFFFF, 0xFFFF, 0xB71F, 0x8EBF, 0x869F, 0x765F, 0x6E3F, 0x65FF, 0x5DBE, 0x5D7D, 0x553D, 0x4D1C, 0x65BE, 0x0AB7, 0x6C15, 0xFFBE,   // 0x02A0 (672)
+0xFFFF, 0xFFFF, 0x53B6, 0x0296, 0x75FE, 0x5D9D, 0x557D, 0x65DE, 0x6E1F, 0x763F, 0x7E7F, 0x8EBF, 0x9EFF, 0x96BE, 0xAE3C, 0xE77E,   // 0x02B0 (688)
+0xEF9E, 0xC69D, 0x967E, 0x9EFF, 0x8EBF, 0x7E7F, 0x763F, 0x6E1F, 0x65DE, 0x5D9E, 0x555D, 0x761E, 0x341A, 0x1294, 0xBE18, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xCE9B, 0x0A13, 0x2378, 0x7E5F, 0x6E1E, 0x5DBE, 0x6E1F, 0x7E5F, 0x869F, 0x96DF, 0x9EFF, 0xAF5F, 0x9E9E, 0x8DFC,   // 0x02D0 (720)
+0x8E1C, 0x967D, 0xAF3F, 0xA6FF, 0x96DF, 0x869F, 0x7E5F, 0x6E1F, 0x5DBE, 0x65DE, 0x7E5F, 0x4CBB, 0x0AB5, 0x7454, 0xEF5C, 0xFFFF,   // 0x02E0 (736)
+0xFFFF, 0xFFFF, 0xFFFF, 0x8D17, 0x01D3, 0x23B9, 0x7E3E, 0x8E9F, 0x763F, 0x765F, 0x8E9F, 0x9EDF, 0xA71F, 0xB75F, 0xC7BF, 0xCFDF,   // 0x02F0 (752)
+0xCFDF, 0xC7BF, 0xB75F, 0xA71F, 0x9EDF, 0x8E9F, 0x765F, 0x6E1F, 0x867F, 0x8E7F, 0x4CBB, 0x1317, 0x4BB4, 0xD679, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFBD, 0x7476, 0x0214, 0x1B78, 0x659D, 0x9EDF, 0x9EFF, 0x96DF, 0x9EFF, 0xAF1F, 0xB75F, 0xC79F, 0xD7DF,   // 0x0310 (784)
+0xD7DF, 0xC79F, 0xB75F, 0xAF1F, 0x9EDF, 0x96DF, 0x96DF, 0x9EFF, 0x7E1E, 0x3C5A, 0x1B77, 0x43B5, 0xBDD6, 0xF7BE, 0xFFFF, 0xFFFF,   // 0x0320 (800)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF77D, 0x7CB6, 0x12B4, 0x1337, 0x449B, 0x7DFD, 0xA6FF, 0xB75F, 0xBF7F, 0xC79F, 0xCFBF, 0xD7FF,   // 0x0330 (816)
+0xD7FF, 0xCFBF, 0xC79F, 0xBF7F, 0xB77F, 0xAF1F, 0x8E5E, 0x551B, 0x3419, 0x2BD7, 0x5415, 0xB5B6, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79D, 0xA577, 0x3B75, 0x1B36, 0x2BD9, 0x4CBB, 0x759D, 0x965E, 0xAEDF, 0xBF3F, 0xC77F,   // 0x0350 (848)
+0xC77F, 0xBF3F, 0xB6FF, 0x9E7F, 0x7DDD, 0x5D1C, 0x447A, 0x3C59, 0x4437, 0x7474, 0xC617, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0360 (864)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDE, 0xD699, 0x84D5, 0x43D5, 0x33B7, 0x3418, 0x4C7A, 0x5CFC, 0x753D, 0x857E,   // 0x0370 (880)
+0x859E, 0x755D, 0x653C, 0x5CFB, 0x4CDA, 0x4CB9, 0x5497, 0x6C95, 0xA555, 0xDEDA, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79D, 0xCE79, 0x9D56, 0x7495, 0x5C56, 0x4C77, 0x4C97, 0x4CB8,   // 0x0390 (912)
+0x54D8, 0x5CD8, 0x5CF8, 0x64D7, 0x74D6, 0x8CF5, 0xAD96, 0xD699, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFBE, 0xEF1B, 0xD679, 0xBDF7, 0xAD96, 0xA576,   // 0x03B0 (944)
+0xA576, 0xAD76, 0xB5B6, 0xC5F7, 0xD679, 0xEF3C, 0xFFDE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFBE,   // 0x03D0 (976)
+0xF7BE, 0xF7BE, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap/tux.c b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap/tux.c
new file mode 100644
index 0000000..69a04a1
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap/tux.c
@@ -0,0 +1,71 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: tux.png
+// Time generated: 11.10.2010 22:51:32
+// Size          : 2 048 Bytes
+
+const unsigned short tux[0x400] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73C, 0x9CD3, 0x9CF3, 0xA514,   // 0x0010 (16)
+0x9CF3, 0x8C51, 0xAD75, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x5AEB, 0x7BEF, 0x9CD3, 0x94B2,   // 0x0030 (48)
+0x94B2, 0x94B2, 0x4228, 0x7BEF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x9CF3, 0x18E3, 0x630C, 0x4A49, 0x4A69,   // 0x0050 (80)
+0x4A69, 0x528A, 0x4A49, 0x0000, 0xC638, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x6B6D, 0x0000, 0x0020, 0x10A2, 0x1082,   // 0x0070 (112)
+0x0841, 0x0841, 0x0841, 0x0000, 0x630C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x528A, 0x4228, 0x8410, 0x0000, 0x0861,   // 0x0090 (144)
+0xAD55, 0xBDD7, 0x10A2, 0x0000, 0x2945, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x5ACB, 0x8C71, 0xE75D, 0x2126, 0x528B,   // 0x00B0 (176)
+0xE75D, 0xDEDB, 0x7BCF, 0x0000, 0x18E3, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x6B6D, 0x4A4A, 0x6B2A, 0x8BE7, 0xA48A,   // 0x00D0 (208)
+0x6B09, 0x4A8A, 0x8431, 0x0000, 0x2104, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00E0 (224)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x6B6E, 0x5204, 0xDE6A, 0xFFF7, 0xFFF8,   // 0x00F0 (240)
+0xD5AC, 0xBCAA, 0x5A66, 0x0000, 0x1082, 0xDEFB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8C10, 0xC540, 0xFFED, 0xFF2C, 0xFEEC,   // 0x0110 (272)
+0xFECC, 0xFE66, 0x8260, 0x0000, 0x0000, 0xB596, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0120 (288)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B3, 0x9C25, 0xFF20, 0xFE40, 0xFDA0,   // 0x0130 (304)
+0xFCC0, 0xF524, 0x836A, 0x0000, 0x0000, 0x630C, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x630C, 0x94B4, 0xFF13, 0xFD83, 0xF523,   // 0x0150 (336)
+0xE5CF, 0xF79E, 0xE71D, 0x0861, 0x0000, 0x0861, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0160 (352)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xCE59, 0x0841, 0xD69A, 0xFFFF, 0xFF7D, 0xF77D,   // 0x0170 (368)
+0xFFFF, 0xFFFF, 0xFFFF, 0x73AE, 0x0000, 0x0000, 0x4A69, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0180 (384)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0x10A2, 0x8410, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF,   // 0x0190 (400)
+0xFFFF, 0xFFDF, 0xFFFF, 0xCE59, 0x0000, 0x0000, 0x0000, 0x9492, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01A0 (416)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x52AA, 0x0020, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01B0 (432)
+0xFFDF, 0xFFDF, 0xF7BE, 0xFFDF, 0x3186, 0x0000, 0x0020, 0x0841, 0xCE79, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01C0 (448)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xC638, 0x0000, 0x52AA, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFDF,   // 0x01D0 (464)
+0xFFDF, 0xF7BE, 0xF79E, 0xFFFF, 0x9CF3, 0x0000, 0x0841, 0x0000, 0x39E7, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01E0 (480)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x5ACB, 0x0000, 0xBDF7, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFDF, 0xFFDF,   // 0x01F0 (496)
+0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0x3186, 0x0000, 0x0861, 0x0000, 0xAD55, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0200 (512)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73C, 0x0861, 0x4A49, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF,   // 0x0210 (528)
+0xF7BE, 0xF79E, 0xEF7D, 0xEF5D, 0xFFDF, 0x8410, 0x0000, 0x1082, 0x0000, 0x39E7, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0220 (544)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B2, 0x0000, 0xB596, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE,   // 0x0230 (560)
+0xF79E, 0xEF7D, 0xEF7D, 0xE73C, 0xF79E, 0xAD55, 0x0861, 0x10A2, 0x0861, 0x0841, 0xCE59, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0240 (576)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0x3185, 0x10A2, 0xE71C, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF79E,   // 0x0250 (592)
+0xEF7D, 0xEF7D, 0xEF5D, 0xE73C, 0xEF5D, 0xBDF7, 0x18C3, 0x18C3, 0x18C3, 0x0000, 0x8C71, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0260 (608)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B2, 0x0000, 0x39E7, 0xF7BE, 0xFFFF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF79E, 0xEF7D,   // 0x0270 (624)
+0xEF7D, 0xEF5D, 0xE73C, 0xE71C, 0xE71C, 0xC618, 0x18E3, 0x10A2, 0x10A2, 0x0020, 0x6B4D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0280 (640)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8C51, 0x38E0, 0x4A27, 0xFFFF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF79E, 0xEF7D, 0xEF7D,   // 0x0290 (656)
+0xEF5D, 0xE73C, 0xE71C, 0xDEFB, 0xDF1D, 0xBDF8, 0x39C7, 0x5ACB, 0x528A, 0x10A3, 0x738F, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02A0 (672)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDD6C, 0xFE2B, 0xBC45, 0xA513, 0xFFFF, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF5D,   // 0x02B0 (688)
+0xE73C, 0xE71C, 0xDEFB, 0xD6DC, 0xDD8E, 0xB3E4, 0x2124, 0x2965, 0x2945, 0x20C1, 0xB511, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF77C, 0xE5CF, 0xF60B, 0xFF9B, 0xFF54, 0x8B02, 0x7BF0, 0xFFDF, 0xF79E, 0xEF5D, 0xEF5D, 0xE73C,   // 0x02D0 (720)
+0xE71C, 0xDEFB, 0xDEDB, 0xCE7A, 0xED89, 0xDDAD, 0x0842, 0x0000, 0x0000, 0xAC69, 0xDD6B, 0xEFBF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02E0 (736)
+0xFFFF, 0xFFFF, 0xFFBE, 0xE5CB, 0xEDC9, 0xFE4B, 0xFF14, 0xFEF3, 0xFF35, 0xFE8D, 0x51C1, 0x634E, 0xE73C, 0xEF5D, 0xE73C, 0xE71C,   // 0x02F0 (752)
+0xDEFB, 0xDEDB, 0xD6DB, 0xCE59, 0xE58B, 0xFF98, 0xBD4F, 0x8B88, 0xCD90, 0xFFB7, 0xCCE8, 0xE73D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xEF3B, 0xF583, 0xFF30, 0xFF11, 0xFECF, 0xFEEF, 0xFECF, 0xFF30, 0xDD46, 0x2903, 0x6B8E, 0xEF7D, 0xE71C, 0xDEFB,   // 0x0310 (784)
+0xDEDB, 0xD6BA, 0xD69A, 0xCE59, 0xE5AA, 0xFF11, 0xFF53, 0xFF73, 0xFF33, 0xFF12, 0xFE6C, 0xDDAD, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0320 (800)
+0xFFFF, 0xFFFF, 0xF79E, 0xEDC5, 0xFECB, 0xFECC, 0xFECC, 0xFEEC, 0xFECB, 0xFECC, 0xFEEA, 0x9BE5, 0x8432, 0xE73C, 0xDEDB, 0xDEDB,   // 0x0330 (816)
+0xD6BA, 0xD69A, 0xDEDB, 0xA4F3, 0xD547, 0xFF2E, 0xFECD, 0xFECE, 0xFEEE, 0xFEEE, 0xFF10, 0xFEAB, 0xE5A8, 0xEF7D, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xF79E, 0xF603, 0xFEA2, 0xFEC7, 0xFEC7, 0xFEA4, 0xFE81, 0xFE61, 0xFEA4, 0xFE43, 0xDE33, 0xE75E, 0xE71C, 0xDEFB,   // 0x0350 (848)
+0xDEDB, 0xCE58, 0x8C72, 0x5247, 0xEDE4, 0xFF0A, 0xFECA, 0xFEC9, 0xFE84, 0xFE83, 0xFEE7, 0xFEA3, 0xB443, 0xD69B, 0xFFFF, 0xFFFF,   // 0x0360 (864)
+0xFFFF, 0xFFFF, 0xF75B, 0xFE60, 0xFF00, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEE0, 0xE5C1, 0x9492, 0xA514, 0x9CD3,   // 0x0370 (880)
+0x8410, 0x630B, 0x4229, 0x6AE8, 0xFE80, 0xFEC1, 0xFEC1, 0xFEA0, 0xFEA0, 0xFEE0, 0xDD80, 0x9BE8, 0xB597, 0xFFDF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xF79E, 0xD589, 0xE600, 0xFEA0, 0xFF00, 0xFF40, 0xFF40, 0xFF00, 0xFF00, 0xFF20, 0xFEC0, 0x5267, 0x4229, 0x4A48,   // 0x0390 (912)
+0x4A49, 0x5289, 0x424A, 0x7B46, 0xFF20, 0xFEE0, 0xFEE0, 0xFF20, 0xFEE0, 0xB4A5, 0x9C92, 0xDEFD, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xFFFF, 0xE71D, 0xBDB6, 0xB530, 0xBD0B, 0xCD65, 0xEE60, 0xFF40, 0xFFA0, 0xFF80, 0xBD03, 0x8410, 0xA514, 0xA534,   // 0x03B0 (944)
+0xAD75, 0xB596, 0xA555, 0x9C8F, 0xF6C0, 0xFFA0, 0xFFA0, 0xF6E0, 0xA449, 0xB5B8, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7F, 0xD69C, 0xBD95, 0xBD4C, 0xCDC6, 0xB4E8, 0xAD35, 0xF7BF, 0xFFFF, 0xFFFF,   // 0x03D0 (976)
+0xFFFF, 0xFFFF, 0xFFFF, 0xF7BF, 0xCDD0, 0xCDC6, 0xCDA7, 0xA48D, 0xCE7B, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDF1F, 0xB59A, 0xBDDA, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFDF, 0xFFDF, 0xFFFF, 0xEF7F, 0xB59A, 0xAD59, 0xDF1D, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap_128x128/UTFT_Bitmap_128x128.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap_128x128/UTFT_Bitmap_128x128.pde
new file mode 100644
index 0000000..85f0573
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap_128x128/UTFT_Bitmap_128x128.pde
@@ -0,0 +1,49 @@
+// UTFT_Bitmap_128x128 (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the drawBitmap()-function.
+//
+// This demo was made to work on the 128x128 modules.
+// Any other size displays may cause strange behaviour.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+UTFT myGLCD(LPH9135,6,5,2,3,4);   // Remember to change the model parameter to suit your display module!
+
+extern unsigned short icon1[0x400];
+extern unsigned short icon2[0x400];
+extern unsigned short tux[0x1000];
+
+void setup()
+{
+  myGLCD.InitLCD(PORTRAIT);
+}
+
+void loop()
+{
+// Draw a 4 by 4 grid of a 32x32 icon.
+  myGLCD.fillScr(255, 255, 255);
+  for (int x=0; x<4; x++)
+    for (int y=0; y<4; y++)
+      myGLCD.drawBitmap (x*32, y*32, 32, 32, icon1);
+
+  delay(5000);
+  
+// Draw a 64x64 icon in double size.
+  myGLCD.fillScr(255, 255, 255);
+  myGLCD.drawBitmap (0, 0, 64, 64, tux, 2);
+
+  delay(5000);
+
+// Draw a 2 by 2 grid of a 32x32 icon in double size.
+  myGLCD.fillScr(255, 255, 255);
+  for (int x=0; x<2; x++)
+    for (int y=0; y<2; y++)
+      myGLCD.drawBitmap (x*64, y*64, 32, 32, icon2, 2);
+
+  delay(5000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap_128x128/icon1.c b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap_128x128/icon1.c
new file mode 100644
index 0000000..b9c2c97
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap_128x128/icon1.c
@@ -0,0 +1,72 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: exit.png
+// Time generated: 14.10.2010 21:53:03
+// Dimensions    : 32x32 pixels
+// Size          : 2 048 Bytes
+
+const unsigned short icon1[0x400] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF1C, 0xE618, 0xE638, 0xE638, 0xE638, 0xE659, 0xE659, 0xE659, 0xE659, 0xE659, 0xE679, 0xE679,   // 0x0010 (16)
+0xE679, 0xE679, 0xE679, 0xE679, 0xEE79, 0xEE9A, 0xEE9A, 0xEE9A, 0xEE9A, 0xEE9A, 0xE638, 0xEEBA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xD555, 0xCCD3, 0xDDB6, 0xDDD7, 0xDDF7, 0xDDF7, 0xDE18, 0xE618, 0xE638, 0xE638, 0xE659, 0xE679, 0xE679,   // 0x0030 (48)
+0xEE9A, 0xEE9A, 0xEEBA, 0xEEBA, 0xEEBA, 0xEEDB, 0xEEDB, 0xEEFB, 0xEEFB, 0xEEFB, 0xEEFB, 0xE659, 0xD575, 0xF77D, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFDF, 0xFFFF, 0xD534, 0xC471, 0xD575, 0xCCF3, 0xCCD3, 0xCCD3, 0xCCF3, 0xCCF3, 0xD4F3, 0xD514, 0xD514, 0xD514, 0xD534, 0xDD55,   // 0x0050 (80)
+0xDD55, 0xDD55, 0xDD55, 0xDD75, 0xDD75, 0xDD75, 0xDD96, 0xDD96, 0xDD96, 0xDDB6, 0xDDD7, 0xEE79, 0xEEBA, 0xD534, 0xFFBE, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xEEDB, 0xB38E, 0xC4B2, 0xBC30, 0xC451, 0xC471, 0xC471, 0xCC71, 0xCC92, 0xCC92, 0xCC92, 0xCCB2, 0xD4B2, 0xD4B2, 0xCC71,   // 0x0070 (112)
+0xCC71, 0xD4D3, 0xD4F3, 0xDCF3, 0xDCF3, 0xDD14, 0xDD14, 0xDD14, 0xDD34, 0xDD34, 0xDD34, 0xDD14, 0xE5D7, 0xDD96, 0xDDF7, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xC4F3, 0xAB2C, 0xC430, 0xC410, 0xC430, 0xC430, 0xC430, 0xCC51, 0xCC51, 0xCC51, 0xCC71, 0xCC71, 0xD471, 0xCC71, 0xD5F7,   // 0x0090 (144)
+0xD5F7, 0xCC92, 0xDCB2, 0xDCD3, 0xDCD3, 0xDCD3, 0xDCD3, 0xDCF3, 0xDCF3, 0xDD14, 0xDD14, 0xDD34, 0xDD14, 0xDD34, 0xC492, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xB3EF, 0x9A28, 0xC430, 0xBBCF, 0xC3EF, 0xC3EF, 0xC3EF, 0xC410, 0xCC10, 0xCC10, 0xCC30, 0xCC51, 0xCBEF, 0xE638, 0xFFFF,   // 0x00B0 (176)
+0xFFFF, 0xE659, 0xD430, 0xDC92, 0xDC92, 0xDC92, 0xDCB2, 0xDCB2, 0xDCB2, 0xDCD3, 0xDCD3, 0xDCD3, 0xE514, 0xD410, 0xAB0C, 0xF7FF,   // 0x00C0 (192)
+0xFFFF, 0xABCF, 0x9165, 0xC3EF, 0xBB8E, 0xBBAE, 0xC3AE, 0xC3CF, 0xC3CF, 0xCBCF, 0xCBEF, 0xCC10, 0xCC10, 0xCBAE, 0xEE9A, 0xFFFF,   // 0x00D0 (208)
+0xFFFF, 0xF6DB, 0xD410, 0xDC71, 0xDC71, 0xDC71, 0xDC71, 0xDC71, 0xDC71, 0xE492, 0xE492, 0xE492, 0xE4F3, 0xCB2C, 0xA249, 0xF7FF,   // 0x00E0 (224)
+0xFFFF, 0xABCF, 0x88C3, 0xC3AE, 0xBB4D, 0xBB6D, 0xC36D, 0xC38E, 0xC38E, 0xCBAE, 0xC36D, 0xC34D, 0xCBCF, 0xCB8E, 0xEE59, 0xFFFF,   // 0x00F0 (240)
+0xFFFF, 0xF6BA, 0xDBCF, 0xD3CF, 0xCBAE, 0xD3CF, 0xE430, 0xE430, 0xE451, 0xE451, 0xE451, 0xE451, 0xECD3, 0xCAAA, 0xA208, 0xF7FF,   // 0x0100 (256)
+0xFFFF, 0xABCF, 0x8061, 0xBB6D, 0xBB2C, 0xBB2C, 0xC34D, 0xC34D, 0xCB4D, 0xBB0C, 0xC492, 0xCD14, 0xC38E, 0xCB2C, 0xEE59, 0xFFFF,   // 0x0110 (272)
+0xFFFF, 0xF6BA, 0xD36D, 0xD575, 0xE6DB, 0xDDB6, 0xD3AE, 0xE3EF, 0xE410, 0xE410, 0xE430, 0xE410, 0xECB2, 0xC986, 0xA208, 0xF7FF,   // 0x0120 (288)
+0xFFFF, 0xB3EF, 0x8041, 0xBB0C, 0xBAEB, 0xBAEB, 0xC30C, 0xC30C, 0xBACB, 0xD5B6, 0xFFFF, 0xFFFF, 0xEE79, 0xCACB, 0xEE59, 0xFFFF,   // 0x0130 (304)
+0xFFFF, 0xF679, 0xDBEF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEEBA, 0xD3CF, 0xE3AE, 0xE3EF, 0xE3CF, 0xEC10, 0xEB6D, 0xC000, 0xA249, 0xF7FF,   // 0x0140 (320)
+0xFFFF, 0xB3EF, 0x8020, 0xBACB, 0xBAAA, 0xBAAA, 0xC2EB, 0xBA8A, 0xD596, 0xFFFF, 0xFFDF, 0xFFFF, 0xF73C, 0xCAAA, 0xEE38, 0xFFFF,   // 0x0150 (336)
+0xFFFF, 0xF679, 0xDB4D, 0xFF7D, 0xFFFF, 0xFFDF, 0xFFFF, 0xEEDB, 0xDB6D, 0xEB8E, 0xEBAE, 0xEB8E, 0xE0A2, 0xC800, 0xAA49, 0xF7FF,   // 0x0160 (352)
+0xFFFF, 0xB3EF, 0x8000, 0xB28A, 0xBA69, 0xBA8A, 0xBA49, 0xCC30, 0xFFFF, 0xFFDF, 0xFFFF, 0xFF5D, 0xDBCF, 0xCA69, 0xEE18, 0xFFFF,   // 0x0170 (368)
+0xFFFF, 0xF679, 0xDAAA, 0xE3AE, 0xF6BA, 0xFFFF, 0xFFDF, 0xFFFF, 0xE5D7, 0xE30C, 0xEB8E, 0xE0E3, 0xE000, 0xC800, 0xAA49, 0xF7FF,   // 0x0180 (384)
+0xFFFF, 0xB3EF, 0x8800, 0xB249, 0xBA49, 0xBA49, 0xBA49, 0xEF1C, 0xFFFF, 0xFFFF, 0xFF7D, 0xD32C, 0xCA69, 0xD249, 0xEDF7, 0xFFFF,   // 0x0190 (400)
+0xFFFF, 0xF659, 0xDAAA, 0xE2CB, 0xE2EB, 0xFEBA, 0xFFFF, 0xFFDF, 0xFFDF, 0xE3CF, 0xE103, 0xE000, 0xE081, 0xD000, 0xAA69, 0xF7FF,   // 0x01A0 (416)
+0xFFFF, 0xB3EF, 0x8800, 0xB228, 0xBA08, 0xB9A6, 0xCBAE, 0xFFFF, 0xFFDF, 0xFFFF, 0xDC30, 0xC9E7, 0xD28A, 0xCA08, 0xF618, 0xFFFF,   // 0x01B0 (432)
+0xFFFF, 0xF679, 0xDA49, 0xE2CB, 0xE28A, 0xEB6D, 0xFFBE, 0xFFDF, 0xFFFF, 0xEC92, 0xE000, 0xE0A2, 0xE0C2, 0xD040, 0xAA89, 0xF7FF,   // 0x01C0 (448)
+0xFFFF, 0xB3EF, 0x8800, 0xB1E7, 0xB9E7, 0xB165, 0xDD55, 0xFFFF, 0xFFFF, 0xF71C, 0xCA08, 0xCA08, 0xD228, 0xD1E7, 0xE430, 0xFFDF,   // 0x01D0 (464)
+0xFFDF, 0xEC51, 0xDA08, 0xE28A, 0xE28A, 0xE228, 0xF618, 0xFFFF, 0xFFFF, 0xF679, 0xE081, 0xE0C2, 0xE903, 0xD081, 0xAA89, 0xF7FF,   // 0x01E0 (480)
+0xFFFF, 0xBBEF, 0x9000, 0xB1A6, 0xB986, 0xB145, 0xEE38, 0xFFFF, 0xFFFF, 0xED96, 0xC165, 0xC9E7, 0xD1E7, 0xD1E7, 0xD1C7, 0xDACB,   // 0x01F0 (496)
+0xE2EB, 0xD9E7, 0xE228, 0xE228, 0xEA69, 0xE9E7, 0xF40F, 0xFFFF, 0xFFFF, 0xFF5D, 0xE144, 0xE8E2, 0xE943, 0xD8C1, 0xAA8A, 0xF7FF,   // 0x0200 (512)
+0xFFFF, 0xBC10, 0x9000, 0xB165, 0xB145, 0xB924, 0xEE9A, 0xFFFF, 0xFFFF, 0xE514, 0xC124, 0xC9A6, 0xD1A6, 0xD1A6, 0xD1C7, 0xD9A6,   // 0x0210 (528)
+0xD9A6, 0xE1E7, 0xE208, 0xE208, 0xE9A6, 0xE041, 0xEA8A, 0xFFFF, 0xFFFF, 0xFF9E, 0xE9C6, 0xE902, 0xE984, 0xD902, 0xAAAA, 0xF7FF,   // 0x0220 (544)
+0xFFFF, 0xC410, 0x9000, 0xB124, 0xB124, 0xB0C3, 0xEE18, 0xFFFF, 0xFFFF, 0xE575, 0xC0E3, 0xC986, 0xD165, 0xD165, 0xD986, 0xD9A6,   // 0x0230 (560)
+0xD9A6, 0xE1A6, 0xE165, 0xE082, 0xE020, 0xE000, 0xEB4C, 0xFFFF, 0xFFFF, 0xFF7D, 0xE9A5, 0xE943, 0xE9A5, 0xD923, 0xAAAA, 0xF7FF,   // 0x0240 (576)
+0xFFFF, 0xC410, 0x9800, 0xB0E3, 0xB0E3, 0xB061, 0xE4F3, 0xFFFF, 0xFFFF, 0xF6FB, 0xC104, 0xC924, 0xD145, 0xD145, 0xD945, 0xD945,   // 0x0250 (592)
+0xD8E3, 0xD861, 0xD800, 0xE000, 0xE061, 0xE000, 0xED34, 0xFFFF, 0xFFFF, 0xFE9A, 0xE923, 0xE984, 0xE9C5, 0xE163, 0xAAAA, 0xF7FF,   // 0x0260 (608)
+0xFFFF, 0xC410, 0xA000, 0xB0A2, 0xB0A2, 0xB041, 0xCACB, 0xFFFF, 0xFFDF, 0xFFFF, 0xD34D, 0xC841, 0xD104, 0xD0A2, 0xD061, 0xD000,   // 0x0270 (624)
+0xD800, 0xD800, 0xE000, 0xE041, 0xE000, 0xD965, 0xFF9E, 0xFFDF, 0xFFFF, 0xF4D2, 0xE8E2, 0xE9A5, 0xE9E5, 0xE183, 0xAAAA, 0xF7FF,   // 0x0280 (640)
+0xFFFF, 0xCC10, 0xA000, 0xA861, 0xB061, 0xB061, 0xB882, 0xF6DB, 0xFFFF, 0xFFDF, 0xF75D, 0xC124, 0xC800, 0xD000, 0xD000, 0xD800,   // 0x0290 (656)
+0xD800, 0xE000, 0xE020, 0xE000, 0xD861, 0xF638, 0xFFFF, 0xFFDF, 0xFFDF, 0xEA68, 0xE943, 0xE9C5, 0xEA06, 0xE1A4, 0xB2CA, 0xF7FF,   // 0x02A0 (672)
+0xFFFF, 0xCC10, 0xA000, 0xA820, 0xB000, 0xB000, 0xB000, 0xCA49, 0xFFFF, 0xFFDF, 0xFFFF, 0xF71C, 0xCA08, 0xC800, 0xD000, 0xD800,   // 0x02B0 (688)
+0xD800, 0xD800, 0xD800, 0xD944, 0xEE18, 0xFFFF, 0xFFBE, 0xFFFF, 0xF4F2, 0xE902, 0xE9A5, 0xE9C5, 0xEA06, 0xE9A4, 0xB2CA, 0xF7FF,   // 0x02C0 (704)
+0xFFFF, 0xD410, 0xA800, 0xA800, 0xB000, 0xB000, 0xB800, 0xB800, 0xDC10, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xED96, 0xDAEB, 0xD1A6,   // 0x02D0 (720)
+0xD965, 0xDA69, 0xECD3, 0xFF9E, 0xFFFF, 0xFFBE, 0xFFFF, 0xFE17, 0xE923, 0xE964, 0xE9A5, 0xE9C5, 0xEA26, 0xE9C4, 0xBACA, 0xF7FF,   // 0x02E0 (736)
+0xF7FF, 0xD410, 0xA800, 0xA800, 0xB000, 0xB000, 0xB800, 0xB800, 0xB800, 0xE3EF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02F0 (752)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF5B6, 0xE923, 0xE923, 0xE984, 0xE9A5, 0xE9E5, 0xEA26, 0xE9C5, 0xBACA, 0xF7FF,   // 0x0300 (768)
+0xF7FF, 0xDC10, 0xB000, 0xA800, 0xB000, 0xB000, 0xB800, 0xB800, 0xC000, 0xC000, 0xD228, 0xF638, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0310 (784)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFEFB, 0xF3AE, 0xE0C1, 0xE903, 0xE964, 0xE984, 0xE9A5, 0xE9E5, 0xEA26, 0xE9E5, 0xC2CA, 0xF7DF,   // 0x0320 (800)
+0xF7FF, 0xDC51, 0xB800, 0xA800, 0xB000, 0xB000, 0xB800, 0xB800, 0xC000, 0xC000, 0xC000, 0xC800, 0xD9E7, 0xEC30, 0xF5D7, 0xFE9A,   // 0x0330 (816)
+0xFEBA, 0xF618, 0xF4D3, 0xEACB, 0xE0E2, 0xE040, 0xE903, 0xE943, 0xE943, 0xE984, 0xE9A5, 0xE9E5, 0xEA26, 0xEA05, 0xC30C, 0xF7DF,   // 0x0340 (832)
+0xFFFF, 0xD575, 0xD104, 0xA820, 0xB000, 0xB800, 0xB800, 0xC000, 0xC000, 0xC000, 0xC820, 0xC800, 0xD000, 0xD000, 0xD800, 0xD800,   // 0x0350 (848)
+0xE000, 0xE000, 0xE000, 0xE000, 0xE0A1, 0xE0E3, 0xE903, 0xE943, 0xE964, 0xE984, 0xE9C5, 0xE9C5, 0xF226, 0xE227, 0xBC10, 0xF7FF,   // 0x0360 (864)
+0xFFFF, 0xDF3C, 0xCAAA, 0xD186, 0xB082, 0xB000, 0xB800, 0xB800, 0xB800, 0xC000, 0xC000, 0xC800, 0xC800, 0xD000, 0xD000, 0xD800,   // 0x0370 (880)
+0xD800, 0xE000, 0xE020, 0xE040, 0xE061, 0xE0A1, 0xE0C2, 0xE102, 0xE123, 0xE943, 0xE984, 0xEA26, 0xFB0A, 0xBA08, 0xCE38, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFDF, 0xBDD7, 0xCA69, 0xE248, 0xD207, 0xD1C6, 0xD1C6, 0xD9C7, 0xD9C7, 0xE1C7, 0xE1C7, 0xE1C7, 0xE9C7, 0xE9C7, 0xE9C7,   // 0x0390 (912)
+0xF1C6, 0xF1C7, 0xF1E7, 0xF207, 0xF228, 0xF248, 0xF269, 0xF289, 0xF2A9, 0xF2CA, 0xFB0A, 0xF2EA, 0xC207, 0xACB3, 0xF7BE, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xF7BE, 0xBDF7, 0xAB8E, 0xC2EB, 0xC2EB, 0xC30B, 0xC30B, 0xC30B, 0xC30B, 0xC30B, 0xC30B, 0xC30B, 0xCB0B, 0xCAEB,   // 0x03B0 (944)
+0xCAEB, 0xCACA, 0xCACA, 0xCAAA, 0xCAAA, 0xCA8A, 0xCA69, 0xC269, 0xC269, 0xC289, 0xBA69, 0xA2CB, 0xAD34, 0xEF7D, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xDF3C, 0xBE39, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7,   // 0x03D0 (976)
+0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xB5F7, 0xBE38, 0xD71C, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap_128x128/icon2.c b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap_128x128/icon2.c
new file mode 100644
index 0000000..9b843cc
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap_128x128/icon2.c
@@ -0,0 +1,72 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: video.png
+// Time generated: 14.10.2010 21:53:17
+// Dimensions    : 32x32 pixels
+// Size          : 2 048 Bytes
+
+const unsigned short icon2[0x400] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0010 (16)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0020 (32)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE71C, 0xB5B6, 0x94B2, 0x8C71,   // 0x0030 (48)
+0x9492, 0xA534, 0xD6BA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF5D, 0x9CF3, 0x73AE, 0x6B6D, 0x73AE, 0x7BCF,   // 0x0050 (80)
+0x7BEF, 0x7BCF, 0x7BEF, 0xA534, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0060 (96)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xC638, 0x7BCF, 0x6B6D, 0x738E, 0x7BCF, 0x8C71, 0x9492,   // 0x0070 (112)
+0x9492, 0x9492, 0x9492, 0x8C51, 0x8C71, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB596, 0x738E, 0x738E, 0x73AE, 0x6B4D, 0x8410, 0x9CF3, 0x9CF3,   // 0x0090 (144)
+0x9CF3, 0x9CF3, 0x9CF3, 0x9CF3, 0x94B2, 0x7BEF, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00A0 (160)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB596, 0x738E, 0x7BEF, 0x8410, 0x632C, 0x4A69, 0x9492, 0xAD75, 0xAD55,   // 0x00B0 (176)
+0xAD55, 0xAD55, 0xAD55, 0xA534, 0xAD55, 0x9492, 0x8430, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xBDF7, 0x7BCF, 0x8430, 0x7BCF, 0x6B4D, 0x528A, 0x6B6D, 0xB5B6, 0xB5B6, 0xB5B6,   // 0x00D0 (208)
+0xB5B6, 0xB596, 0xB596, 0xAD75, 0xAD75, 0xAD55, 0x8410, 0xB5B6, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00E0 (224)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDB, 0x7BEF, 0x9CD3, 0xA514, 0x5AEB, 0x630C, 0x6B4D, 0x9492, 0xC638, 0xC618, 0xC618,   // 0x00F0 (240)
+0xBDF7, 0xBDF7, 0xC618, 0xB5B6, 0xB5B6, 0xB596, 0x9492, 0x8C51, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x8C71, 0x94B2, 0xAD55, 0xB5B6, 0x738E, 0x6B4D, 0x632C, 0xB596, 0xD69A, 0xCE59, 0xCE59,   // 0x0110 (272)
+0xCE79, 0xCE59, 0x6B6D, 0x9492, 0xB5B6, 0xBDF7, 0x9CF3, 0x8430, 0xD69A, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0120 (288)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB5B6, 0x8C51, 0xAD55, 0xB5B6, 0xCE79, 0x8C51, 0x630C, 0x8C51, 0xCE79, 0xD6BA, 0xD69A, 0xDEDB,   // 0x0130 (304)
+0xBDD7, 0x8C51, 0x4228, 0x2965, 0xAD55, 0xC638, 0xA534, 0x8430, 0xB5B6, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0xFFFF, 0xEF5D, 0x8C51, 0xA514, 0xB5B6, 0xC618, 0xD6BA, 0xB5B6, 0xB596, 0xE71C, 0xDEFB, 0xDEFB, 0xE71C, 0xAD55,   // 0x0150 (336)
+0x738E, 0x7BEF, 0x5AEB, 0x2945, 0xC638, 0xCE59, 0xA534, 0x9492, 0xA534, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0160 (352)
+0xFFFF, 0xFFFF, 0xFFFF, 0xB596, 0x94B2, 0xB5B6, 0xC618, 0xCE79, 0xD6BA, 0xE73C, 0xEF7D, 0xE73C, 0xEF5D, 0xE73C, 0x9CF3, 0x738E,   // 0x0170 (368)
+0x7BCF, 0x8430, 0x6B6D, 0x2965, 0xB596, 0xD69A, 0xAD55, 0x94B2, 0x9CD3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0180 (384)
+0xFFFF, 0xFFFF, 0xF79E, 0x9492, 0x9CF3, 0xB5B6, 0xD69A, 0xDEFB, 0xE71C, 0xE73C, 0x6B6D, 0x528A, 0xDEDB, 0xEF5D, 0x7BEF, 0x8430,   // 0x0190 (400)
+0x7BEF, 0x8C51, 0x7BCF, 0x2104, 0xB596, 0xD6BA, 0xAD55, 0x9CD3, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73C, 0xE6FC,   // 0x01A0 (416)
+0xFFDF, 0xFFFF, 0xCE59, 0x9492, 0x9492, 0x6B4D, 0x7BCF, 0xBDD7, 0xF7BE, 0xA514, 0x4A49, 0x528A, 0xC638, 0xEF7D, 0x7BEF, 0x7BEF,   // 0x01B0 (432)
+0x7BEF, 0x8430, 0x5AEB, 0x10A2, 0xC618, 0xD69A, 0xAD55, 0x94B2, 0xA514, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCE5A, 0x8BF2,   // 0x01C0 (448)
+0xFFFF, 0xFFFF, 0xAD55, 0x94B2, 0x8C51, 0x5AEB, 0x632C, 0xBDD7, 0xE73C, 0x630C, 0x632C, 0xBDF7, 0xFFDF, 0xEF5D, 0xBDD7, 0xB5B6,   // 0x01D0 (464)
+0xAD75, 0xAD75, 0x8C51, 0x738E, 0xD69A, 0xCE59, 0xB596, 0x8C51, 0xB5B6, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xCE39, 0x7350,   // 0x01E0 (480)
+0xFFFF, 0xF79E, 0x94B2, 0x94B2, 0x7BCF, 0x5AEB, 0x738E, 0xD6BA, 0xD69A, 0x2104, 0x6B6D, 0xF79E, 0xF79E, 0xF79E, 0xF7BE, 0xF79E,   // 0x01F0 (496)
+0xEF7D, 0xEF5D, 0xE73C, 0xE73C, 0xDEFB, 0xBDF7, 0xBDF7, 0x7BEF, 0xD69A, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAD36, 0x7350,   // 0x0200 (512)
+0xFFFF, 0xDEDB, 0x8C51, 0x94B2, 0x738E, 0x632C, 0x73AE, 0xCE79, 0xF7BE, 0x7BEF, 0xA514, 0xF7BE, 0xF79E, 0xEF7D, 0xEF7D, 0xEF5D,   // 0x0210 (528)
+0xE73C, 0xE71C, 0xDEFB, 0xDEDB, 0xDEDB, 0xBDD7, 0xBDF7, 0x73AE, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x9C75, 0x736F,   // 0x0220 (544)
+0xFFFF, 0xCE59, 0x8430, 0x94B2, 0x6B4D, 0x6B4D, 0xB596, 0xE73C, 0xEF7D, 0xFFFF, 0xFFFF, 0xF7BE, 0xF79E, 0xEF7D, 0xEF7D, 0xEF5D,   // 0x0230 (560)
+0xE73C, 0xE73C, 0xDEFB, 0xDEFB, 0xD6BA, 0xC618, 0xAD55, 0x8C71, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDB, 0x6AEF, 0x9492,   // 0x0240 (576)
+0xFFFF, 0xBDF7, 0x8430, 0x8C71, 0x6B6D, 0xB596, 0xE71C, 0xE73C, 0xEF5D, 0xE73C, 0xBDF7, 0xCE59, 0xF7BE, 0xEF7D, 0xEF7D, 0xEF5D,   // 0x0250 (592)
+0xE73C, 0xE71C, 0xDEFB, 0xDEFB, 0xC638, 0xD69A, 0x8410, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x9474, 0x6B0E, 0xCE59,   // 0x0260 (608)
+0xFFFF, 0xB5B6, 0x8410, 0x9492, 0xBDD7, 0xD6BA, 0xD6BA, 0xE71C, 0xE73C, 0x8C71, 0x6B4D, 0xA514, 0xF7BE, 0xEF5D, 0xEF5D, 0xE73C,   // 0x0270 (624)
+0xE73C, 0xE71C, 0xDEFB, 0xDEDB, 0xCE59, 0xC618, 0x7BCF, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xC5F9, 0x7B51, 0x7BEF, 0xFFFF,   // 0x0280 (640)
+0xFFFF, 0xB596, 0x8C71, 0xAD75, 0xBDF7, 0xCE59, 0xD69A, 0xE71C, 0xCE79, 0x8410, 0x8410, 0x9CD3, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C,   // 0x0290 (656)
+0xE71C, 0xDEFB, 0xDEFB, 0xCE59, 0xDEDB, 0x8C71, 0xAD75, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEBB, 0x83B2, 0x630C, 0xE73C, 0xFFFF,   // 0x02A0 (672)
+0xFFFF, 0xB5B6, 0x9492, 0xAD55, 0xBDD7, 0xC638, 0xCE79, 0xDEFB, 0xB596, 0x73AE, 0x8410, 0x8410, 0xDEDB, 0xE73C, 0xE71C, 0xE71C,   // 0x02B0 (688)
+0xDEFB, 0xDEFB, 0xD6BA, 0xCE59, 0xC618, 0x738E, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDC, 0x8C14, 0x5ACC, 0xC658, 0xFFFF, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xC638, 0x8C51, 0xA534, 0xB5B6, 0xBDF7, 0xCE59, 0xD6BA, 0x94B2, 0x738E, 0x8410, 0x8430, 0xCE59, 0xE73C, 0xDEFB, 0xDEFB,   // 0x02D0 (720)
+0xDEDB, 0xDEFB, 0xBDF7, 0xDEDB, 0x73AE, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDC, 0x8BD2, 0x5ACC, 0xBDD6, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02E0 (736)
+0xFFFF, 0xDEDB, 0x8C51, 0xA514, 0xAD75, 0xBDD7, 0xC638, 0xC618, 0x73AE, 0x7BCF, 0x8410, 0x5ACB, 0x8C51, 0xE73C, 0xDEDB, 0xD6BA,   // 0x02F0 (752)
+0xDEFB, 0xBDD7, 0xD69A, 0x8C71, 0x8C51, 0xFFFF, 0xFFFF, 0xFFDE, 0xCE5A, 0x7B71, 0x62ED, 0xBDF7, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xF7BE, 0x94B2, 0x94B2, 0xA534, 0xB596, 0xBDF7, 0xB596, 0x6B6D, 0x4208, 0x2945, 0x18C3, 0x6B6D, 0xDEFB, 0xD69A, 0xDEDB,   // 0x0310 (784)
+0xB5B6, 0xC618, 0x9CF3, 0x6B4D, 0xFFDE, 0xFFFF, 0xEF5D, 0xAD37, 0x62EE, 0x6B4D, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0320 (800)
+0xFFDF, 0xFFFF, 0xBDF7, 0x8C51, 0xA514, 0xAD55, 0xB596, 0xBDD7, 0xA514, 0x738E, 0xA514, 0xB5B6, 0xCE59, 0xD69A, 0xDEDB, 0xB596,   // 0x0330 (816)
+0xBDF7, 0xA534, 0x6B4C, 0xEF5D, 0xF79E, 0xBDB8, 0x7370, 0x5AAC, 0x8C71, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xF79E, 0x94B2, 0x94B2, 0xA534, 0xAD55, 0xB5B6, 0xA534, 0xBDD7, 0xD69A, 0xCE59, 0xCE79, 0xCE59, 0xA534, 0x8430,   // 0x0350 (848)
+0x738E, 0x3186, 0x7BB0, 0x8C33, 0x7370, 0x62ED, 0x8410, 0xCE59, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0360 (864)
+0xFFFF, 0xFFFF, 0xFFFF, 0xDEFB, 0x8C71, 0x9CD3, 0xAD55, 0xB596, 0xBDD7, 0xBDD7, 0xBDF7, 0xC618, 0xB5B6, 0xA534, 0xA534, 0x632C,   // 0x0370 (880)
+0x6B6D, 0xB5B6, 0xAD76, 0xAD76, 0xBE17, 0xE71B, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEFB, 0x94B2, 0x8C51, 0x94B2, 0xA534, 0xAD55, 0xAD55, 0x9CD3, 0x8C71, 0x73AE, 0x632C, 0xA534,   // 0x0390 (912)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03A0 (928)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xCE59, 0xA514, 0x8430, 0x7BCF, 0x738E, 0x73AE, 0x8410, 0xA534, 0xEF7D, 0xFFFF,   // 0x03B0 (944)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xE73C, 0xE71C, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03D0 (976)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03E0 (992)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap_128x128/tux.c b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap_128x128/tux.c
new file mode 100644
index 0000000..7fefd80
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Bitmap_128x128/tux.c
@@ -0,0 +1,264 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: tux_64x64.png
+// Time generated: 14.10.2010 21:56:38
+// Dimensions    : 64x64 pixels
+// Size          : 8 192 Bytes
+
+const unsigned short tux[0x1000] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0010 (16)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCE79, 0x9CF3, 0x7BCF, 0x738E, 0x738E,   // 0x0020 (32)
+0x6B6D, 0x94B2, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0030 (48)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0050 (80)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCE79, 0x6B4D, 0x5ACB, 0x8410, 0x9CF3, 0x9CF3, 0x9CF3,   // 0x0060 (96)
+0x9CD3, 0x73AE, 0x4208, 0x5ACB, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0070 (112)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0090 (144)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xA514, 0x3186, 0x8C51, 0xBDF7, 0xC618, 0xBDF7, 0xBDF7, 0xBDF7,   // 0x00A0 (160)
+0xBDF7, 0xC618, 0xBDD7, 0x738E, 0x18C3, 0x8C51, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00B0 (176)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00D0 (208)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xBDD7, 0x10A2, 0x8C71, 0x9CF3, 0x8C71, 0x8C71, 0x8C71, 0x8C71, 0x8C71,   // 0x00E0 (224)
+0x8C71, 0x8C51, 0x8C51, 0x9CF3, 0x73AE, 0x0000, 0x7BEF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00F0 (240)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0110 (272)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x2945, 0x31A6, 0x7BCF, 0x6B4D, 0x6B6D, 0x6B6D, 0x6B6D, 0x6B6D, 0x6B6D,   // 0x0120 (288)
+0x6B6D, 0x6B6D, 0x6B6D, 0x6B4D, 0x73AE, 0x2124, 0x0000, 0xAD55, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0130 (304)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0150 (336)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xC638, 0x0000, 0x31A6, 0x52AA, 0x4A69, 0x4A69, 0x4A69, 0x4A69, 0x4A69, 0x4A69,   // 0x0160 (352)
+0x4A69, 0x4A69, 0x4A69, 0x4A69, 0x528A, 0x2104, 0x0000, 0x2965, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0170 (368)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0180 (384)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0190 (400)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8C71, 0x0000, 0x1082, 0x3186, 0x3186, 0x3186, 0x3186, 0x3186, 0x3186, 0x3186,   // 0x01A0 (416)
+0x3186, 0x3186, 0x3186, 0x3186, 0x2965, 0x0020, 0x0000, 0x0000, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01B0 (432)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01C0 (448)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01D0 (464)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x630C, 0x0000, 0x0000, 0x0861, 0x18C3, 0x10A2, 0x10A2, 0x10A2, 0x10A2, 0x18C3,   // 0x01E0 (480)
+0x1082, 0x0841, 0x1082, 0x10A2, 0x0020, 0x0000, 0x0000, 0x0000, 0x528A, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01F0 (496)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0200 (512)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0210 (528)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x4A49, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0220 (544)
+0x0861, 0x3186, 0x18C3, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2104, 0xD6BA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0230 (560)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0240 (576)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0250 (592)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x39C7, 0x0000, 0x3186, 0xAD75, 0x8C51, 0x0841, 0x0000, 0x0000, 0x0000, 0x4208,   // 0x0260 (608)
+0xD6BA, 0xFFDF, 0xE71C, 0x630C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0841, 0xAD75, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0270 (624)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0280 (640)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0290 (656)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x39C7, 0x0000, 0xCE59, 0xFFFF, 0xFFFF, 0x94B2, 0x0000, 0x0000, 0x10A2, 0xE73C,   // 0x02A0 (672)
+0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x2124, 0x0000, 0x0000, 0x0000, 0x0000, 0x94B2, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02B0 (688)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02D0 (720)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x2965, 0x18E3, 0xDEDB, 0x7BCF, 0xAD75, 0xEF5D, 0x2944, 0x0000, 0x5ACA, 0xFFFF,   // 0x02E0 (736)
+0xAD55, 0x94B2, 0xAD55, 0xF7BE, 0x8410, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C51, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02F0 (752)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0310 (784)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x39E7, 0x2945, 0xA514, 0x9CF3, 0x8C71, 0xD6BB, 0x39C9, 0x0000, 0x632E, 0xF7DF,   // 0x0320 (800)
+0x7BEF, 0xAD54, 0x7BEF, 0xBDF7, 0xB596, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C71, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0330 (816)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0350 (848)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x4A49, 0x18C3, 0x9492, 0x39E7, 0x3187, 0xA48F, 0x8323, 0x5A00, 0x93A6, 0xCDD5,   // 0x0360 (864)
+0x4209, 0x4249, 0x2965, 0x9CD2, 0xB575, 0x0000, 0x0000, 0x0000, 0x0000, 0x9492, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0370 (880)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0390 (912)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x5ACB, 0x0000, 0x9D14, 0x2905, 0x6A40, 0xE643, 0xFFAE, 0xFFF3, 0xFF70, 0xDD86,   // 0x03A0 (928)
+0x7240, 0x1840, 0x18C3, 0xC65A, 0x73CF, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C51, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03B0 (944)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03D0 (976)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x738E, 0x0000, 0x5A6A, 0xD566, 0xFF66, 0xFFF8, 0xFFFD, 0xFFDC, 0xFFFD, 0xFFFA,   // 0x03E0 (992)
+0xFF0E, 0xE566, 0xC464, 0xC4CC, 0x2103, 0x0000, 0x0000, 0x0000, 0x0000, 0x6B6D, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03F0 (1008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0410 (1040)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x7BEF, 0x0800, 0xB440, 0xFFC6, 0xFFF3, 0xFFB4, 0xFFB2, 0xFF92, 0xFF72, 0xFF53,   // 0x0420 (1056)
+0xFF55, 0xFF75, 0xFEF0, 0xF542, 0x8240, 0x0000, 0x0000, 0x0000, 0x0000, 0x4228, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0430 (1072)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0440 (1088)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0450 (1104)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8432, 0x4140, 0xFFE2, 0xFFEB, 0xFFAC, 0xFF8B, 0xFF4C, 0xFF2C, 0xFEEC, 0xFECB,   // 0x0460 (1120)
+0xFE6A, 0xFE08, 0xFDA7, 0xFDC3, 0xA320, 0x0000, 0x0000, 0x0000, 0x0000, 0x18E3, 0xD69A, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0470 (1136)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0480 (1152)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0490 (1168)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x9D14, 0x28A0, 0xF6E0, 0xFFE1, 0xFF43, 0xFF04, 0xFEC4, 0xFE84, 0xFE23, 0xFDE1,   // 0x04A0 (1184)
+0xFD60, 0xFD20, 0xFD20, 0xFD20, 0x7241, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x9CF3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x04B0 (1200)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x04C0 (1216)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x04D0 (1232)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xB5B6, 0x0000, 0xC4A9, 0xFEC0, 0xFF00, 0xFEA0, 0xFE40, 0xFE00, 0xFDA0, 0xFD60,   // 0x04E0 (1248)
+0xFD40, 0xFD20, 0xEC80, 0xDCC7, 0x8C0F, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x52AA, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x04F0 (1264)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0500 (1280)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0510 (1296)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xAD75, 0x0000, 0xD69B, 0xF631, 0xF5C0, 0xFE80, 0xFE00, 0xFDC0, 0xFD60, 0xFD40,   // 0x0520 (1312)
+0xFCC0, 0xDC86, 0xCD93, 0xE73D, 0xE71C, 0x0861, 0x0000, 0x0000, 0x0000, 0x0000, 0x0861, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0530 (1328)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0540 (1344)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0550 (1360)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x632C, 0x0000, 0xD6BA, 0xFFFF, 0xF5F1, 0xFD40, 0xFD80, 0xFD20, 0xFCE0, 0xECA3,   // 0x0560 (1376)
+0xDD6F, 0xE6FC, 0xFFFF, 0xFFFF, 0xFFFF, 0x632C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x5ACB, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0570 (1392)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0580 (1408)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0590 (1424)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xDEDB, 0x0861, 0x0000, 0xD69A, 0xFFFF, 0xFFFF, 0xFED8, 0xF631, 0xF610, 0xE5F2, 0xE6B9,   // 0x05A0 (1440)
+0xF7BF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xE71C, 0x10A2, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0xB5B6, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x05B0 (1456)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x05C0 (1472)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x05D0 (1488)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x39E7, 0x0000, 0x4228, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7FF, 0xF7DF, 0xFFFF,   // 0x05E0 (1504)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x73AE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3186, 0xEF7D, 0xFFFF, 0xFFFF,   // 0x05F0 (1520)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0600 (1536)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0610 (1552)
+0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x738E, 0x0000, 0x18C3, 0xDEFB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0620 (1568)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFFF, 0xCE59, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6B4D, 0xFFFF, 0xFFFF,   // 0x0630 (1584)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0640 (1600)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0650 (1616)
+0xFFFF, 0xFFDF, 0xFFFF, 0xA514, 0x0000, 0x0000, 0x9CD3, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0660 (1632)
+0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0x2965, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xAD55, 0xFFFF,   // 0x0670 (1648)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0680 (1664)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0690 (1680)
+0xFFDF, 0xFFFF, 0xD69A, 0x0861, 0x0000, 0x2945, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x06A0 (1696)
+0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xFFFF, 0x7BCF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x18C3, 0xD6BA,   // 0x06B0 (1712)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x06C0 (1728)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x06D0 (1744)
+0xFFFF, 0xFFDF, 0x39C7, 0x0000, 0x0000, 0x8430, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x06E0 (1760)
+0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xFFFF, 0xCE79, 0x0841, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x4228,   // 0x06F0 (1776)
+0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0700 (1792)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF,   // 0x0710 (1808)
+0xFFFF, 0x94B2, 0x0000, 0x0020, 0x0020, 0xCE79, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF,   // 0x0720 (1824)
+0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xFFDF, 0x4A69, 0x0000, 0x0841, 0x0000, 0x0000, 0x0000, 0x0020, 0x0000,   // 0x0730 (1840)
+0x8C71, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0740 (1856)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0750 (1872)
+0xEF7D, 0x2104, 0x0020, 0x0000, 0x3186, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF,   // 0x0760 (1888)
+0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xFFFF, 0xB5B6, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0000,   // 0x0770 (1904)
+0x10A2, 0xD6BA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0780 (1920)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF,   // 0x0790 (1936)
+0x8C71, 0x0000, 0x0861, 0x0000, 0x7BCF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF,   // 0x07A0 (1952)
+0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xFFDF, 0x528A, 0x0000, 0x0841, 0x0020, 0x0020, 0x0020, 0x0020,   // 0x07B0 (1968)
+0x0000, 0x630C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x07C0 (1984)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE,   // 0x07D0 (2000)
+0x3186, 0x0000, 0x0841, 0x10A2, 0xE71C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF,   // 0x07E0 (2016)
+0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xF79E, 0xEF5D, 0xF7BE, 0xBDD7, 0x0841, 0x0861, 0x0841, 0x0841, 0x0841, 0x0020,   // 0x07F0 (2032)
+0x0020, 0x1082, 0xC638, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0800 (2048)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xBDD7,   // 0x0810 (2064)
+0x0020, 0x1082, 0x0000, 0x7BEF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE,   // 0x0820 (2080)
+0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF7D, 0x4208, 0x0020, 0x0861, 0x0861, 0x0841, 0x0841,   // 0x0830 (2096)
+0x0841, 0x0000, 0x630C, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0840 (2112)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x6B4D,   // 0x0850 (2128)
+0x0000, 0x0861, 0x2104, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE,   // 0x0860 (2144)
+0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xE73C, 0xF7BE, 0x8430, 0x0000, 0x1082, 0x0861, 0x0861, 0x0861,   // 0x0870 (2160)
+0x0861, 0x0020, 0x18C3, 0xCE79, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0880 (2176)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF5D, 0x2124,   // 0x0890 (2192)
+0x0861, 0x0020, 0x8410, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE,   // 0x08A0 (2208)
+0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xEF7D, 0xB5B6, 0x0861, 0x1082, 0x1082, 0x0861, 0x0861,   // 0x08B0 (2224)
+0x0861, 0x0861, 0x0000, 0x8430, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x08C0 (2240)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xA514, 0x0020,   // 0x08D0 (2256)
+0x10A2, 0x1082, 0xD69A, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE,   // 0x08E0 (2272)
+0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xEF5D, 0xCE79, 0x2124, 0x1082, 0x10A2, 0x1082, 0x1082,   // 0x08F0 (2288)
+0x0861, 0x1082, 0x0000, 0x4208, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0900 (2304)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0x4208, 0x0861,   // 0x0910 (2320)
+0x1082, 0x31A6, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E,   // 0x0920 (2336)
+0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEDB, 0x39C7, 0x1082, 0x10A2, 0x10A2, 0x1082,   // 0x0930 (2352)
+0x1082, 0x1082, 0x0841, 0x18C3, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0940 (2368)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xA534, 0x0841, 0x18C3,   // 0x0950 (2384)
+0x0841, 0x630C, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E,   // 0x0960 (2400)
+0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xDEFB, 0xE73C, 0x4A49, 0x0861, 0x18C3, 0x10A2, 0x10A2,   // 0x0970 (2416)
+0x10A2, 0x1082, 0x1082, 0x0841, 0x9CD3, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0980 (2432)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0x3186, 0x1082, 0x18E3,   // 0x0990 (2448)
+0x0861, 0x94B2, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D,   // 0x09A0 (2464)
+0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEDB, 0xE73C, 0x4A69, 0x1082, 0x18E3, 0x18C3, 0x10A2,   // 0x09B0 (2480)
+0x10A2, 0x10A2, 0x10A2, 0x0020, 0x73AE, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x09C0 (2496)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B2, 0x0841, 0x18E3, 0x18E3,   // 0x09D0 (2512)
+0x0861, 0xAD75, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D,   // 0x09E0 (2528)
+0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEDB, 0xE73C, 0x52AA, 0x10A2, 0x2104, 0x18E3, 0x18C3,   // 0x09F0 (2544)
+0x18C3, 0x18C3, 0x10A2, 0x0841, 0x630C, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0A00 (2560)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x632C, 0x0861, 0x18E4, 0x18E4,   // 0x0A10 (2576)
+0x1082, 0xC638, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D,   // 0x0A20 (2592)
+0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xD6BA, 0xE71C, 0x6B4D, 0x10A2, 0x18C3, 0x18C3, 0x10A2,   // 0x0A30 (2608)
+0x10A2, 0x10A2, 0x18C3, 0x0861, 0x5AEB, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0A40 (2624)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x8410, 0x0862, 0x3143, 0x2924,   // 0x0A50 (2640)
+0x0882, 0xBDD7, 0xFFFF, 0xFFDF, 0xFFDF, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D,   // 0x0A60 (2656)
+0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB, 0xE73C, 0x630C, 0x2103, 0x4A69, 0x632C, 0x6B4D,   // 0x0A70 (2672)
+0x528A, 0x2965, 0x18C3, 0x1081, 0x738E, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0A80 (2688)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xB596, 0x7A40, 0xECA0, 0xCC00,   // 0x0A90 (2704)
+0x3941, 0xA535, 0xFFFF, 0xF7BE, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D,   // 0x0AA0 (2720)
+0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEFB, 0xD6DB, 0xCE38, 0xC618, 0x4A48, 0x4A49, 0x6B6D, 0x6B4D, 0x6B4D,   // 0x0AB0 (2736)
+0x6B4D, 0x630C, 0x3186, 0x18E4, 0x9492, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0AC0 (2752)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xC488, 0xFD41, 0xFE6D, 0xFE6A,   // 0x0AD0 (2768)
+0xDC60, 0x5A25, 0xB5D8, 0xFFFF, 0xF7BE, 0xF7BE, 0xF7BE, 0xF79E, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C,   // 0x0AE0 (2784)
+0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xD6BB, 0xBCAB, 0xD462, 0xD462, 0x49E4, 0x10C3, 0x18C3, 0x18C3, 0x18C3,   // 0x0AF0 (2800)
+0x18C3, 0x18E3, 0x10A3, 0x49C4, 0xB575, 0xF7BF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0B00 (2816)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xCD70, 0xECA0, 0xFF14, 0xFF9B, 0xFF7B,   // 0x0B10 (2832)
+0xFECF, 0xC3A0, 0x3143, 0x9CF3, 0xFFFF, 0xF7BE, 0xF79E, 0xF79E, 0xF79E, 0xEF7D, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C,   // 0x0B20 (2848)
+0xE73C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEFB, 0xC617, 0xDC60, 0xFD60, 0xFD20, 0x3120, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0B30 (2864)
+0x0000, 0x0000, 0x3900, 0xE460, 0xB46A, 0xEF9F, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0B40 (2880)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD5F4, 0xDC20, 0xFE8E, 0xFF59, 0xFF36, 0xFF36,   // 0x0B50 (2896)
+0xFF59, 0xFE6B, 0xA300, 0x18E4, 0x8410, 0xFFBE, 0xF7BE, 0xEF7D, 0xF79E, 0xEF7D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C,   // 0x0B60 (2912)
+0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEBA, 0xDEFB, 0xC5B5, 0xE4A1, 0xFEF2, 0xF716, 0x3164, 0x18E4, 0x2103, 0x1082, 0x1082,   // 0x0B70 (2928)
+0x0021, 0x1061, 0xD5D0, 0xFE27, 0xB3E3, 0xCE9B, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0B80 (2944)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF77D, 0xE697, 0xDDAF, 0xD4C8, 0xE480, 0xFE29, 0xFF36, 0xFF15, 0xFF35, 0xFF15,   // 0x0B90 (2960)
+0xFF15, 0xFF36, 0xFDA5, 0x6A42, 0x1905, 0x6B4C, 0xE73C, 0xFFDF, 0xEF5D, 0xEF7D, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C,   // 0x0BA0 (2976)
+0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB, 0xD6BA, 0xDEDB, 0xBDB5, 0xE4C3, 0xFF56, 0xFFDB, 0xAD10, 0x10A2, 0x10C3, 0x18E4, 0x1082,   // 0x0BB0 (2992)
+0x2922, 0xC5B1, 0xFFDC, 0xFED1, 0xB3A2, 0xBE19, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0BC0 (3008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE6B8, 0xD484, 0xE4C0, 0xF584, 0xFE28, 0xFECF, 0xFF14, 0xFF13, 0xFF13, 0xFF13, 0xFF13,   // 0x0BD0 (3024)
+0xFF13, 0xFF14, 0xFEF0, 0xDC80, 0x41C5, 0x2945, 0x5269, 0xCE59, 0xF7BE, 0xEF5D, 0xEF5D, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C,   // 0x0BE0 (3040)
+0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB, 0xD6BA, 0xD69A, 0xD6DB, 0xBD95, 0xE4E2, 0xFF33, 0xFF36, 0xFF97, 0xDDF1, 0x8B66, 0x7AE4, 0x9BC7,   // 0x0BF0 (3056)
+0xEEB2, 0xFF97, 0xFF37, 0xFEF0, 0xC3E0, 0xB5B7, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C00 (3072)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD52B, 0xFD60, 0xFECD, 0xFF33, 0xFF13, 0xFF12, 0xFEF1, 0xFEF1, 0xFEF1, 0xFEF1, 0xFEF1,   // 0x0C10 (3088)
+0xFEF1, 0xFEF1, 0xFF12, 0xFE69, 0x9B41, 0x31A8, 0x31A6, 0x39E7, 0xB5B6, 0xF79E, 0xE73C, 0xE73C, 0xE73C, 0xE71C, 0xE71C, 0xDEFB,   // 0x0C20 (3104)
+0xDEFB, 0xDEDB, 0xDEDB, 0xD6BA, 0xD6BA, 0xD699, 0xD6BA, 0xBD94, 0xE502, 0xFF12, 0xFF15, 0xFEF4, 0xFF55, 0xFF95, 0xFF54, 0xFF95,   // 0x0C30 (3120)
+0xFF35, 0xFEF4, 0xFF14, 0xFF14, 0xF5A4, 0xB426, 0xE75E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C40 (3136)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD54C, 0xFDA0, 0xFECE, 0xFEF0, 0xFECF, 0xFEEF, 0xFEEF, 0xFEF0, 0xFEEF, 0xFEF0, 0xFEF0,   // 0x0C50 (3152)
+0xFEF0, 0xFEEF, 0xFEF0, 0xFEEF, 0xF582, 0x6244, 0x39E8, 0x39C6, 0x528A, 0xE71C, 0xE73C, 0xE71C, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB,   // 0x0C60 (3168)
+0xDEDB, 0xDEDB, 0xD6BA, 0xD6BA, 0xD69A, 0xCE79, 0xCE9A, 0xBD94, 0xE522, 0xFF10, 0xFEF2, 0xFEF2, 0xFEF2, 0xFEF2, 0xFEF2, 0xFEF2,   // 0x0C70 (3184)
+0xFEF2, 0xFF12, 0xFEF2, 0xFEF2, 0xFF12, 0xED85, 0xBC68, 0xE73D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C80 (3200)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD5B0, 0xF580, 0xFECB, 0xFEEE, 0xFECD, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE,   // 0x0C90 (3216)
+0xFEEE, 0xFEEE, 0xFECD, 0xFECE, 0xFECA, 0xCC60, 0x41C7, 0x39C7, 0x4228, 0xCE79, 0xEF5D, 0xE71C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB,   // 0x0CA0 (3232)
+0xDEDB, 0xD6BA, 0xD6BA, 0xD69A, 0xCE79, 0xCE59, 0xCE9A, 0xBD73, 0xED42, 0xFF0F, 0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0,   // 0x0CB0 (3248)
+0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0, 0xFEF0, 0xFF31, 0xF628, 0xC4A7, 0xDE57, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0CC0 (3264)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDE13, 0xF560, 0xFEC9, 0xFECD, 0xFECC, 0xFECC, 0xFECC, 0xFECC, 0xFECC, 0xFECC, 0xFECC,   // 0x0CD0 (3280)
+0xFEEC, 0xFEEC, 0xFECC, 0xFECC, 0xFEED, 0xFE44, 0x9323, 0x52CC, 0x73AE, 0xD69A, 0xE73C, 0xDEFB, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB,   // 0x0CE0 (3296)
+0xD6BA, 0xD6BA, 0xD69A, 0xCE79, 0xCE59, 0xD69A, 0xB5D8, 0x7B28, 0xF5A2, 0xFF0F, 0xFECE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE,   // 0x0CF0 (3312)
+0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFEEE, 0xFECD, 0xFF10, 0xFEA9, 0xCC60, 0xD615, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D00 (3328)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDE55, 0xED80, 0xFEA4, 0xFECA, 0xFECA, 0xFECA, 0xFECA, 0xFECA, 0xFECA, 0xFECA, 0xFEC9,   // 0x0D10 (3344)
+0xFEA7, 0xFEA6, 0xFEA8, 0xFEC9, 0xFECB, 0xFEEA, 0xEDA2, 0xB4F0, 0xCE9A, 0xDEFB, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB, 0xD6BA,   // 0x0D20 (3360)
+0xD6BA, 0xD69A, 0xCE79, 0xCE79, 0xD6BA, 0xB596, 0x4A8B, 0x72A4, 0xFE45, 0xFEEC, 0xFECC, 0xFEEC, 0xFEEC, 0xFEEC, 0xFEEC, 0xFEEC,   // 0x0D30 (3376)
+0xFEEC, 0xFECB, 0xFECB, 0xFEEC, 0xFEEC, 0xFEEC, 0xFECC, 0xFEA5, 0xFDE0, 0xAC8B, 0xE75E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D40 (3392)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE632, 0xF5E0, 0xFE80, 0xFE82, 0xFEC7, 0xFEC8, 0xFEC8, 0xFEC8, 0xFEC7, 0xFEA4, 0xFE61,   // 0x0D50 (3408)
+0xFE60, 0xFE60, 0xFE60, 0xFE61, 0xFE83, 0xFEA6, 0xFEA3, 0xDD22, 0xD658, 0xE75D, 0xDEDB, 0xDEDB, 0xDEDB, 0xD6BA, 0xD6BA, 0xD69A,   // 0x0D60 (3424)
+0xD69A, 0xD69A, 0xD6BA, 0xCE59, 0x9492, 0x5289, 0x39E9, 0x9B84, 0xFEA3, 0xFEEB, 0xFEEA, 0xFEEA, 0xFEEA, 0xFEEA, 0xFEEA, 0xFEC8,   // 0x0D70 (3440)
+0xFE84, 0xFE61, 0xFE61, 0xFEA5, 0xFEC9, 0xFEA7, 0xFEA2, 0xFE80, 0xBC41, 0x8C0F, 0xE71C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D80 (3456)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDDCE, 0xFE40, 0xFEA0, 0xFE80, 0xFE80, 0xFEA2, 0xFEA2, 0xFEA2, 0xFEA0, 0xFE80, 0xFE80,   // 0x0D90 (3472)
+0xFEA0, 0xFEA0, 0xFEA0, 0xFE80, 0xFE80, 0xFE80, 0xFE80, 0xFE80, 0xCCE5, 0xD69A, 0xE73C, 0xE71C, 0xDEFB, 0xDEFB, 0xDEDB, 0xDEDB,   // 0x0DA0 (3488)
+0xD69A, 0xBDF7, 0x9CD3, 0x630C, 0x4228, 0x4A69, 0x422A, 0xB423, 0xFEC0, 0xFEA5, 0xFEE7, 0xFEC7, 0xFEC7, 0xFEC6, 0xFEA3, 0xFE80,   // 0x0DB0 (3504)
+0xFE80, 0xFE80, 0xFE80, 0xFE60, 0xFEA0, 0xFEC0, 0xEDC0, 0xA3A4, 0x732C, 0xAD96, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0DC0 (3520)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE5A8, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0DD0 (3536)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEE0, 0xF640, 0x93A8, 0x8C72, 0xA534, 0xAD75, 0xA534, 0x9CF3, 0x8C51,   // 0x0DE0 (3552)
+0x738E, 0x5ACB, 0x4A49, 0x4A69, 0x528A, 0x4A8A, 0x5249, 0xD502, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEC1, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0,   // 0x0DF0 (3568)
+0xFEA0, 0xFEA0, 0xFEA0, 0xFEE0, 0xFE60, 0xC482, 0x7B09, 0x7BD0, 0xB5B7, 0xEF5D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E00 (3584)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDD8A, 0xFEC0, 0xFF20, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0,   // 0x0E10 (3600)
+0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEC0, 0xFF20, 0xAC02, 0x4209, 0x4A69, 0x4A69, 0x4A69, 0x4A69, 0x4A69,   // 0x0E20 (3616)
+0x528A, 0x528A, 0x52AA, 0x52AA, 0x528A, 0x4A8A, 0x5A69, 0xE5C1, 0xFF00, 0xFEC0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0, 0xFEE0,   // 0x0E30 (3632)
+0xFEC0, 0xFEE0, 0xFF00, 0xE561, 0x9367, 0x736E, 0x9D14, 0xD6BA, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E40 (3648)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD617, 0xCCC5, 0xF620, 0xFEE0, 0xFF40, 0xFF40, 0xFF40, 0xFF20, 0xFF00, 0xFF00, 0xFF00,   // 0x0E50 (3664)
+0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF40, 0xB483, 0x4A8B, 0x5ACA, 0x5ACB, 0x5ACB, 0x5ACB, 0x5ACB,   // 0x0E60 (3680)
+0x5ACB, 0x52AA, 0x52AA, 0x52AA, 0x52AA, 0x4A8A, 0x6289, 0xEE20, 0xFF20, 0xFEE0, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFEE0,   // 0x0E70 (3696)
+0xFF20, 0xFEC0, 0xBC64, 0x732B, 0x8C72, 0xCE58, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E80 (3712)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7E, 0xB576, 0x93EE, 0xA408, 0xC4A5, 0xDD63, 0xF641, 0xFEC0, 0xFF40, 0xFF80, 0xFF60,   // 0x0E90 (3728)
+0xFF40, 0xFF20, 0xFF20, 0xFF40, 0xFF40, 0xFF40, 0xFF20, 0xFF20, 0xFF80, 0xAC03, 0x4A6B, 0x5ACA, 0x5ACB, 0x5ACB, 0x5AEB, 0x5AEB,   // 0x0EA0 (3744)
+0x5AEB, 0x630C, 0x630C, 0x630C, 0x5AEB, 0x52CB, 0x5A69, 0xE5E1, 0xFF60, 0xFF20, 0xFF20, 0xFF20, 0xFF20, 0xFF20, 0xFF20, 0xFF60,   // 0x0EB0 (3760)
+0xF640, 0xA3A7, 0x738F, 0xAD96, 0xE71C, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0EC0 (3776)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF79E, 0xD6DB, 0xB5B8, 0x9CD4, 0x9431, 0x93EE, 0x9C0A, 0xB467, 0xD544, 0xF660,   // 0x0ED0 (3792)
+0xFF60, 0xFFA0, 0xFF80, 0xFF60, 0xFF40, 0xFF40, 0xFF60, 0xFFA0, 0xD521, 0x730A, 0x73CF, 0x8C71, 0x9CD3, 0x9CF3, 0xA514, 0xA534,   // 0x0EE0 (3808)
+0xAD55, 0xB596, 0xB5B6, 0xB596, 0xAD55, 0x9CF3, 0x83F0, 0xCD04, 0xFFA0, 0xFF40, 0xFF40, 0xFF40, 0xFF40, 0xFF40, 0xFFA0, 0xF621,   // 0x0EF0 (3824)
+0x8B49, 0x8431, 0xCE58, 0xF79E, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F00 (3840)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xF79E, 0xE73C, 0xD6BB, 0xBE19, 0xA556, 0x9472, 0x9C0D,   // 0x0F10 (3856)
+0xB447, 0xDD82, 0xFEE0, 0xFFA0, 0xFFC0, 0xFFC0, 0xFF80, 0xC4C2, 0x730C, 0x9CF4, 0xD69A, 0xEF5D, 0xEF7D, 0xF79E, 0xF79E, 0xF7BE,   // 0x0F20 (3872)
+0xF7BE, 0xFFDF, 0xFFDF, 0xF7BE, 0xF7BE, 0xEF7D, 0xDF1C, 0xC530, 0xF620, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFF80, 0xE5A2, 0x834A,   // 0x0F30 (3888)
+0x8C93, 0xDEDA, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F40 (3904)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDE, 0xEF7D, 0xD6BB,   // 0x0F50 (3920)
+0xAD77, 0x9452, 0x9BEB, 0xB466, 0xC524, 0xC543, 0xA3E5, 0x734D, 0xAD76, 0xEF5C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F60 (3936)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDF1C, 0xACB0, 0xBCA6, 0xD544, 0xCD64, 0xCD05, 0xAC07, 0x7B6D, 0x9CF4,   // 0x0F70 (3952)
+0xE6FB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F80 (3968)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F90 (3984)
+0xFFDE, 0xE75D, 0xC65A, 0xA536, 0x9493, 0x8C53, 0x94B4, 0xBE18, 0xEF7D, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FA0 (4000)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xDEFC, 0xAD57, 0x9493, 0x8C73, 0x8C73, 0x94D4, 0xBE18, 0xEF5D,   // 0x0FB0 (4016)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FC0 (4032)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FD0 (4048)
+0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xEF5C, 0xE73C, 0xEF5C, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FE0 (4064)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xEF5C, 0xE73C, 0xEF5C, 0xEF7D, 0xFFDE, 0xFFFF,   // 0x0FF0 (4080)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x1000 (4096)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_128x128_Serial/UTFT_Demo_128x128_Serial.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_128x128_Serial/UTFT_Demo_128x128_Serial.pde
new file mode 100644
index 0000000..45a97e6
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_128x128_Serial/UTFT_Demo_128x128_Serial.pde
@@ -0,0 +1,335 @@
+// UTFT_Demo_128x128_Serial (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made to work on the 128x128 modules.
+// Any other size displays may cause strange behaviour.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Declare an instance of the class
+UTFT myGLCD(LPH9135,6,5,2,3,4);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD(PORTRAIT);
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  byte buf[126];
+  int x, x2;
+  int y, y2;
+  int r;
+  
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+  myGLCD.setContrast(64);
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0,0,127,12);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0,117,127,127);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255,0,0);
+  myGLCD.print("Universal TFT", CENTER, 0);
+  myGLCD.setBackColor(64,64,64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("H.Karlsen", LEFT, 116);
+  myGLCD.print("(C)2012", RIGHT, 116);
+  myGLCD.setColor(0,255,0);
+  myGLCD.drawRect(0,13,127,116);
+
+// Draw crosshairs
+  myGLCD.setColor(0,0,255);
+  myGLCD.drawLine(63,14,63,115);
+  myGLCD.drawLine(1,63,126,63);
+  for (int i=3; i<128; i+=10)
+    myGLCD.drawLine(i, 61, i, 65);
+  for (int i=14; i<118; i+=10)
+    myGLCD.drawLine(61, i, 65, i);
+  
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.setBackColor(0,0,0);
+  myGLCD.print("Sin", 2, 14);
+  for (int i=1; i<126; i++)
+  {
+    myGLCD.drawPixel(i,63+(sin(((i*2.85)*3.14)/180)*45));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 2, 26);
+  for (int i=1; i<126; i++)
+  {
+    myGLCD.drawPixel(i,63+(cos(((i*2.85)*3.14)/180)*45));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 2, 38);
+  for (int i=1; i<126; i++)
+  {
+    myGLCD.drawPixel(i,63+(tan(((i*2.85)*3.14)/180)));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+  myGLCD.setColor(0,0,255);
+  myGLCD.drawLine(63,14,63,115);
+  myGLCD.drawLine(1,63,126,63);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<3654; i++)
+  {
+    x++;
+    if (x==127)
+      x=1;
+    if (i>127)
+    {
+      if ((x==63)||(buf[x-1]==63))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=63+(sin(((i*1.3)*3.14)/180)*45);
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+//    delay(3);
+  }
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+  
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(10+(i*10),10+(i*10), 60+(i*10), 60+(i*10));
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+  
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(70-(i*10),10+(i*10), 120-(i*10), 60+(i*10));
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+  
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(30+(i*10),35+(i*10), 25);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+  // Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=11; i<115; i+=3)
+  {
+    myGLCD.drawLine(1, i, i-10, 115);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=112; i>14; i-=3)
+  {
+    myGLCD.drawLine(126, i, i+14, 14);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=115; i>14; i-=3)
+  {
+    myGLCD.drawLine(1, i, 116-i, 14);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=14; i<115; i+=3)
+  {
+    myGLCD.drawLine(126, i, 140-i, 115);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=22+random(85);
+    y=35+random(59);
+    r=random(20);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(124);
+    y=15+random(101);
+    x2=2+random(124);
+    y2=15+random(101);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(124);
+    y=15+random(101);
+    x2=2+random(124);
+    y2=15+random(101);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random lines
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(124);
+    y=15+random(101);
+    x2=2+random(124);
+    y2=15+random(101);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+  
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,126,115);
+
+// Draw some random pixels
+  for (int i=0; i<5000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(124), 15+random(101));
+  }
+  
+  delay (2000);
+  
+// Set up the "Finished"-screen
+  myGLCD.setContrast(0);
+  myGLCD.fillScr(0,0,255);
+  myGLCD.setColor(255,0,0);
+  myGLCD.fillRoundRect(2, 40, 125, 88);
+  
+  myGLCD.setColor(255,255,255);
+  myGLCD.setBackColor(255,0,0);
+  myGLCD.print("That's it!", CENTER, 46);
+  myGLCD.print("Restarting in a", CENTER, 66);
+  myGLCD.print("few seconds...", CENTER, 76);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.setBackColor(0,0,255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 108);
+  myGLCD.printNumI(millis(), CENTER, 118);
+  
+  myGLCD.setContrast(64);
+  
+  delay (10000);
+  
+// Fade screen to black
+  for (int i=64; i>0; i--)
+  {
+    myGLCD.setContrast(i);
+    delay(100);
+  }
+}
+
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_160x128_Serial/UTFT_Demo_160x128_Serial.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_160x128_Serial/UTFT_Demo_160x128_Serial.pde
new file mode 100644
index 0000000..35ccb5d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_160x128_Serial/UTFT_Demo_160x128_Serial.pde
@@ -0,0 +1,323 @@
+// UTFT_Demo_160x128_Serial (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 160x128 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(ITDB18SP,11,10,9,12,8);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[158];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 159, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 114, 159, 127);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("Universal TFT Lib.", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("H.Karlsen", LEFT, 114);
+  myGLCD.print("(C)2012", RIGHT, 114);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 13, 159, 113);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(79, 14, 79, 113);
+  myGLCD.drawLine(1, 63, 158, 63);
+
+  for (int i=9; i<150; i+=10)
+    myGLCD.drawLine(i, 61, i, 65);
+  for (int i=19; i<110; i+=10)
+    myGLCD.drawLine(77, i, 81, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<158; i++)
+  {
+    myGLCD.drawPixel(i,63+(sin(((i*2.27)*3.14)/180)*40));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<158; i++)
+  {
+    myGLCD.drawPixel(i,63+(cos(((i*2.27)*3.14)/180)*40));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<158; i++)
+  {
+    myGLCD.drawPixel(i,63+(tan(((i*2.27)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(79, 14, 79, 113);
+  myGLCD.drawLine(1, 63, 158, 63);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(158*20); i++) 
+  {
+    x++;
+    if (x==159)
+      x=1;
+    if (i>159)
+    {
+      if ((x==79)||(buf[x-1]==63))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=63+(sin(((i*2.5)*3.14)/180)*(40-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(39+(i*10), 23+(i*10), 59+(i*10), 43+(i*10));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(99-(i*10), 23+(i*10), 119-(i*10), 43+(i*10));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(49+(i*10),33+(i*10), 15);
+  }
+  
+  delay(2000);
+    
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=14; i<113; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 112);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=112; i>15; i-=5)
+  {
+    myGLCD.drawLine(158, i, (i*1.44)-12, 14);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=112; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 172-(i*1.44), 14);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<112; i+=5)
+  {
+    myGLCD.drawLine(158, i, 171-(i*1.44), 112);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=22+random(116);
+    y=35+random(57);
+    r=random(20);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(156);
+    y=16+random(95);
+    x2=2+random(156);
+    y2=16+random(95);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(156);
+    y=16+random(95);
+    x2=2+random(156);
+    y2=16+random(95);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(156);
+    y=16+random(95);
+    x2=2+random(156);
+    y2=16+random(95);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,14,158,113);
+
+  for (int i=0; i<5000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(156), 16+random(95));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(10, 17, 149, 72);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 20);
+  myGLCD.print("Restarting in a", CENTER, 45);
+  myGLCD.print("few seconds...", CENTER, 57);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 103);
+  myGLCD.printNumI(millis(), CENTER, 115);
+
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_220x176/UTFT_Demo_220x176.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_220x176/UTFT_Demo_220x176.pde
new file mode 100644
index 0000000..0be1fcb
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_220x176/UTFT_Demo_220x176.pde
@@ -0,0 +1,326 @@
+// UTFT_Demo_220x176 (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 220x176 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for chipKit Uno32/uC32
+UTFT myGLCD(ITDB22,34,35,36,37);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for chipKit Max32
+//UTFT myGLCD(ITDB22,82,83,84,85);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[218];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 219, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 162, 219, 175);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("** Universal TFT Library **", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("> elec.henningkarlsen.com <", CENTER, 163);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 219, 161);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(109, 15, 109, 160);
+  myGLCD.drawLine(1, 88, 218, 88);
+
+  for (int i=9; i<210; i+=10)
+    myGLCD.drawLine(i, 86, i, 90);
+  for (int i=19; i<155; i+=10)
+    myGLCD.drawLine(107, i, 111, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(sin(((i*1.65)*3.14)/180)*70));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(cos(((i*1.65)*3.14)/180)*70));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(tan(((i*1.65)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(109, 15, 109, 160);
+  myGLCD.drawLine(1, 88, 218, 88);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(218*20); i++) 
+  {
+    x++;
+    if (x==219)
+      x=1;
+    if (i>219)
+    {
+      if ((x==109)||(buf[x-1]==88))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=88+(sin(((i*1.6)*3.14)/180)*(65-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(44+(i*15), 23+(i*15), 88+(i*15), 63+(i*15));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(132-(i*15), 23+(i*15), 172-(i*15), 63+(i*15));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(64+(i*15),43+(i*15), 20);
+  }
+  
+  delay(2000);
+    
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<160; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 160);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=160; i>15; i-=5)
+  {
+    myGLCD.drawLine(218, i, (i*1.44)-12, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=160; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 232-(i*1.44), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<160; i+=5)
+  {
+    myGLCD.drawLine(218, i, 231-(i*1.44), 160);
+  }
+  
+  delay(2000);
+  
+    myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=22+random(176);
+    y=35+random(105);
+    r=random(20);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(216), 16+random(143));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(40, 57, 179, 119);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 62);
+  myGLCD.print("Restarting in a", CENTER, 88);
+  myGLCD.print("few seconds...", CENTER, 101);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 146);
+  myGLCD.printNumI(millis(), CENTER, 161);
+
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_220x176_Serial/UTFT_Demo_220x176_Serial.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_220x176_Serial/UTFT_Demo_220x176_Serial.pde
new file mode 100644
index 0000000..ec66344
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_220x176_Serial/UTFT_Demo_220x176_Serial.pde
@@ -0,0 +1,322 @@
+// UTFT_Demo_220x176_Serial (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for serial modules with a screen resolution 
+// of 220x176 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(ITDB22SP,11,10,9,12);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[218];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 219, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 162, 219, 175);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("** Universal TFT Library **", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("> elec.henningkarlsen.com <", CENTER, 163);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 219, 161);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(109, 15, 109, 160);
+  myGLCD.drawLine(1, 88, 218, 88);
+
+  for (int i=9; i<210; i+=10)
+    myGLCD.drawLine(i, 86, i, 90);
+  for (int i=19; i<155; i+=10)
+    myGLCD.drawLine(107, i, 111, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(sin(((i*1.65)*3.14)/180)*70));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(cos(((i*1.65)*3.14)/180)*70));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<218; i++)
+  {
+    myGLCD.drawPixel(i,88+(tan(((i*1.65)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(109, 15, 109, 160);
+  myGLCD.drawLine(1, 88, 218, 88);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(218*20); i++) 
+  {
+    x++;
+    if (x==219)
+      x=1;
+    if (i>219)
+    {
+      if ((x==109)||(buf[x-1]==88))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=88+(sin(((i*1.6)*3.14)/180)*(65-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(44+(i*15), 23+(i*15), 88+(i*15), 63+(i*15));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(132-(i*15), 23+(i*15), 172-(i*15), 63+(i*15));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(64+(i*15),43+(i*15), 20);
+  }
+  
+  delay(2000);
+    
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<160; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 160);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=160; i>15; i-=5)
+  {
+    myGLCD.drawLine(218, i, (i*1.44)-12, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=160; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 232-(i*1.44), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<160; i+=5)
+  {
+    myGLCD.drawLine(218, i, 231-(i*1.44), 160);
+  }
+  
+  delay(2000);
+  
+    myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,161);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=22+random(176);
+    y=35+random(105);
+    r=random(20);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(216);
+    y=16+random(143);
+    x2=2+random(216);
+    y2=16+random(143);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,218,160);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(216), 16+random(143));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(40, 57, 179, 119);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 62);
+  myGLCD.print("Restarting in a", CENTER, 88);
+  myGLCD.print("few seconds...", CENTER, 101);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 146);
+  myGLCD.printNumI(millis(), CENTER, 161);
+
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_320x240/UTFT_Demo_320x240.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_320x240/UTFT_Demo_320x240.pde
new file mode 100644
index 0000000..4a50a2c
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_320x240/UTFT_Demo_320x240.pde
@@ -0,0 +1,325 @@
+// UTFT_Demo_320x240 (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 320x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for chipKit Uno32/uC32
+UTFT myGLCD(ITDB24D,34,35,36,37);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for chipKit Max32
+//UTFT myGLCD(ITDB24D,82,83,84,85);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[318];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 319, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 226, 319, 239);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 227);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 319, 225);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+  for (int i=9; i<310; i+=10)
+    myGLCD.drawLine(i, 117, i, 121);
+  for (int i=19; i<220; i+=10)
+    myGLCD.drawLine(157, i, 161, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(sin(((i*1.13)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(cos(((i*1.13)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(tan(((i*1.13)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(318*20); i++) 
+  {
+    x++;
+    if (x==319)
+      x=1;
+    if (i>319)
+    {
+      if ((x==159)||(buf[x-1]==119))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=119+(sin(((i*1.1)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(70+(i*20), 30+(i*20), 130+(i*20), 90+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(190-(i*20), 30+(i*20), 250-(i*20), 90+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(100+(i*20),60+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 224);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(318, i, (i*1.44)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 331-(i*1.44), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(318, i, 330-(i*1.44), 224);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(256);
+    y=45+random(146);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(207);
+    x2=2+random(316);
+    y2=16+random(207);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(207);
+    x2=2+random(316);
+    y2=16+random(207);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(209);
+    x2=2+random(316);
+    y2=16+random(209);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(316), 16+random(209));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(80, 70, 239, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 210);
+  myGLCD.printNumI(millis(), CENTER, 225);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_320x240_Serial/UTFT_Demo_320x240_Serial.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_320x240_Serial/UTFT_Demo_320x240_Serial.pde
new file mode 100644
index 0000000..6781e9b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_320x240_Serial/UTFT_Demo_320x240_Serial.pde
@@ -0,0 +1,321 @@
+// UTFT_Demo_320x240_Serial (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 320x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+UTFT myGLCD(TFT01_22SP,9,8,12,11,10);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[318];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 319, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 226, 319, 239);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 227);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 319, 225);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+  for (int i=9; i<310; i+=10)
+    myGLCD.drawLine(i, 117, i, 121);
+  for (int i=19; i<220; i+=10)
+    myGLCD.drawLine(157, i, 161, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(sin(((i*1.13)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(cos(((i*1.13)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<318; i++)
+  {
+    myGLCD.drawPixel(i,119+(tan(((i*1.13)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(159, 15, 159, 224);
+  myGLCD.drawLine(1, 119, 318, 119);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(318*20); i++) 
+  {
+    x++;
+    if (x==319)
+      x=1;
+    if (i>319)
+    {
+      if ((x==159)||(buf[x-1]==119))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=119+(sin(((i*1.1)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(70+(i*20), 30+(i*20), 130+(i*20), 90+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(190-(i*20), 30+(i*20), 250-(i*20), 90+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(100+(i*20),60+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.44)-10, 224);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(318, i, (i*1.44)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 331-(i*1.44), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(318, i, 330-(i*1.44), 224);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(256);
+    y=45+random(146);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(207);
+    x2=2+random(316);
+    y2=16+random(207);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(207);
+    x2=2+random(316);
+    y2=16+random(207);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(316);
+    y=16+random(209);
+    x2=2+random(316);
+    y2=16+random(209);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,318,224);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(316), 16+random(209));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(80, 70, 239, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 210);
+  myGLCD.printNumI(millis(), CENTER, 225);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_400x240/UTFT_Demo_400x240.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_400x240/UTFT_Demo_400x240.pde
new file mode 100644
index 0000000..71e2903
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_400x240/UTFT_Demo_400x240.pde
@@ -0,0 +1,327 @@
+// UTFT_Demo_400x240 (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 400x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for chipKit Uno32/uC32
+UTFT myGLCD(ITDB32WD,34,35,36,37);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for chipKit Max32
+//UTFT myGLCD(ITDB32WD,82,83,84,85);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[398];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 399, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 226, 399, 239);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("*** Universal Color TFT Display Library ***", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("< http://electronics.henningkarlsen.com >", CENTER, 227);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 399, 225);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(199, 15, 199, 224);
+  myGLCD.drawLine(1, 119, 398, 119);
+  for (int i=9; i<390; i+=10)
+    myGLCD.drawLine(i, 117, i, 121);
+  for (int i=19; i<220; i+=10)
+    myGLCD.drawLine(197, i, 201, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<398; i++)
+  {
+    myGLCD.drawPixel(i,119+(sin(((i*0.9)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<398; i++)
+  {
+    myGLCD.drawPixel(i,119+(cos(((i*0.9)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<398; i++)
+  {
+    y=119+(tan(((i*0.9)*3.14)/180));
+    if ((y>15) && (y<224))
+    myGLCD.drawPixel(i,y);
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(199, 15, 199, 224);
+  myGLCD.drawLine(1, 119, 398, 119);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(398*20); i++) 
+  {
+    x++;
+    if (x==399)
+      x=1;
+    if (i>399)
+    {
+      if ((x==199)||(buf[x-1]==119))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=119+(sin(((i)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(110+(i*20), 30+(i*20), 170+(i*20), 90+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(230-(i*20), 30+(i*20), 290-(i*20), 90+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(110+(i*30),60+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.77)-10, 224);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(398, i, (i*1.77)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=224; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 411-(i*1.77), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<224; i+=5)
+  {
+    myGLCD.drawLine(398, i, 410-(i*1.77), 224);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(336);
+    y=45+random(146);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(396);
+    y=16+random(207);
+    x2=2+random(396);
+    y2=16+random(207);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(396);
+    y=16+random(207);
+    x2=2+random(396);
+    y2=16+random(207);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(396);
+    y=16+random(209);
+    x2=2+random(396);
+    y2=16+random(209);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,398,224);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(396), 16+random(209));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(120, 70, 279, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 210);
+  myGLCD.printNumI(millis(), CENTER, 225);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_480x272/UTFT_Demo_480x272.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_480x272/UTFT_Demo_480x272.pde
new file mode 100644
index 0000000..ae97893
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_480x272/UTFT_Demo_480x272.pde
@@ -0,0 +1,324 @@
+// UTFT_Demo_480x272 (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 480x272 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for chipKit Uno32/uC32
+//UTFT myGLCD(ITDB43,34,35,36,37);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for chipKit Max32
+UTFT myGLCD(ITDB43,82,83,84,85);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[478];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 479, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 258, 479, 271);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 259);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 479, 257);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(239, 15, 239, 256);
+  myGLCD.drawLine(1, 135, 478, 135);
+  for (int i=9; i<470; i+=10)
+    myGLCD.drawLine(i, 133, i, 138);
+  for (int i=15; i<256; i+=10)
+    myGLCD.drawLine(237, i, 241, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,135+(sin(((i*1.13)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,135+(cos(((i*1.13)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,135+(tan(((i*1.13)*3.14)/180)));
+  }
+
+  delay(2000);
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,257);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(239, 15, 239, 256);
+  myGLCD.drawLine(1, 135, 478, 135);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(478*20); i++) 
+  {
+    x++;
+    if (x==479)
+      x=1;
+    if (i>479)
+    {
+      if ((x==239)||(buf[x-1]==135))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=135+(sin(((i*1.65)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,257);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(150+(i*20), 46+(i*20), 210+(i*20), 106+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,257);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(330-(i*20), 46+(i*20), 270-(i*20), 106+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,257);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(180+(i*20),75+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,257);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<256; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.88)-10, 256);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=256; i>15; i-=5)
+  {
+    myGLCD.drawLine(478, i, (i*1.88)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=256; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 491-(i*1.88), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<256; i+=5)
+  {
+    myGLCD.drawLine(478, i, 490-(i*1.88), 256);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,257);
+
+// Draw some random circles
+  for (int i=0; i<150; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(416);
+    y=45+random(178);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,257);
+
+// Draw some random rectangles
+  for (int i=0; i<150; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(239);
+    x2=2+random(476);
+    y2=16+random(239);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,257);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<150; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(239);
+    x2=2+random(476);
+    y2=16+random(239);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,257);
+
+  for (int i=0; i<150; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(239);
+    x2=2+random(476);
+    y2=16+random(239);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,257);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(476), 16+random(239));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(160, 70, 319, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 243);
+  myGLCD.printNumI(millis(), CENTER, 258);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_480x320/UTFT_Demo_480x320.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_480x320/UTFT_Demo_480x320.pde
new file mode 100644
index 0000000..ca47ee0
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_480x320/UTFT_Demo_480x320.pde
@@ -0,0 +1,325 @@
+// UTFT_Demo_480x320 (C)2013 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 480x320 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for chipKit Uno32/uC32
+UTFT myGLCD(CTE32HR,34,35,36,37);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for chipKit Max32
+//UTFT myGLCD(CTE32HR,82,83,84,85);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[478];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 479, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 306, 479, 319);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 307);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 479, 305);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(239, 15, 239, 304);
+  myGLCD.drawLine(1, 159, 478, 159);
+  for (int i=9; i<470; i+=10)
+    myGLCD.drawLine(i, 157, i, 161);
+  for (int i=19; i<220; i+=10)
+    myGLCD.drawLine(237, i, 241, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,159+(sin(((i*1.13)*3.14)/180)*95));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,159+(cos(((i*1.13)*3.14)/180)*95));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<478; i++)
+  {
+    myGLCD.drawPixel(i,159+(tan(((i*1.13)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(239, 15, 239, 304);
+  myGLCD.drawLine(1, 159, 478, 159);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(478*15); i++) 
+  {
+    x++;
+    if (x==479)
+      x=1;
+    if (i>479)
+    {
+      if ((x==239)||(buf[x-1]==159))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=159+(sin(((i*0.7)*3.14)/180)*(90-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some filled rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRect(150+(i*20), 70+(i*20), 210+(i*20), 130+(i*20));
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some filled, rounded rectangles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillRoundRect(270-(i*20), 70+(i*20), 330-(i*20), 130+(i*20));
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some filled circles
+  for (int i=1; i<6; i++)
+  {
+    switch (i)
+    {
+      case 1:
+        myGLCD.setColor(255,0,255);
+        break;
+      case 2:
+        myGLCD.setColor(255,0,0);
+        break;
+      case 3:
+        myGLCD.setColor(0,255,0);
+        break;
+      case 4:
+        myGLCD.setColor(0,0,255);
+        break;
+      case 5:
+        myGLCD.setColor(255,255,0);
+        break;
+    }
+    myGLCD.fillCircle(180+(i*20),100+(i*20), 30);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<304; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.6)-10, 304);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=304; i>15; i-=5)
+  {
+    myGLCD.drawLine(478, i, (i*1.6)-11, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=304; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 491-(i*1.6), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<304; i+=5)
+  {
+    myGLCD.drawLine(478, i, 490-(i*1.6), 304);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some random circles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(416);
+    y=45+random(226);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some random rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(289);
+    x2=2+random(476);
+    y2=16+random(289);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(289);
+    x2=2+random(476);
+    y2=16+random(289);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+  for (int i=0; i<100; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(476);
+    y=16+random(289);
+    x2=2+random(476);
+    y2=16+random(289);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,478,304);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(476), 16+random(289));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(160, 70, 319, 169);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 93);
+  myGLCD.print("Restarting in a", CENTER, 119);
+  myGLCD.print("few seconds...", CENTER, 132);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 290);
+  myGLCD.printNumI(millis(), CENTER, 305);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_800x480/UTFT_Demo_800x480.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_800x480/UTFT_Demo_800x480.pde
new file mode 100644
index 0000000..6c6f306
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Demo_800x480/UTFT_Demo_800x480.pde
@@ -0,0 +1,284 @@
+// UTFT_Demo_800x480 (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of how to use most of the functions
+// of the library with a supported display modules.
+//
+// This demo was made for modules with a screen resolution 
+// of 800x480 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for chipKit Uno32/uC32
+//UTFT myGLCD(ITDB50,34,35,36,37);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for chipKit Max32
+UTFT myGLCD(ITDB50,82,83,84,85);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  randomSeed(analogRead(0));
+  
+// Setup the LCD
+  myGLCD.InitLCD();
+  myGLCD.setFont(SmallFont);
+}
+
+void loop()
+{
+  int buf[798];
+  int x, x2;
+  int y, y2;
+  int r;
+
+// Clear the screen and draw the frame
+  myGLCD.clrScr();
+
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, 799, 13);
+  myGLCD.setColor(64, 64, 64);
+  myGLCD.fillRect(0, 466, 799, 479);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("* Universal Color TFT Display Library *", CENTER, 1);
+  myGLCD.setBackColor(64, 64, 64);
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("", CENTER, 467);
+
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.drawRect(0, 14, 799, 465);
+
+// Draw crosshairs
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(399, 15, 399, 464);
+  myGLCD.drawLine(1, 239, 798, 239);
+  for (int i=9; i<790; i+=10)
+    myGLCD.drawLine(i, 237, i, 242);
+  for (int i=19; i<470; i+=10)
+    myGLCD.drawLine(397, i, 402, i);
+
+// Draw sin-, cos- and tan-lines  
+  myGLCD.setColor(0,255,255);
+  myGLCD.print("Sin", 5, 15);
+  for (int i=1; i<798; i++)
+  {
+    myGLCD.drawPixel(i,239+(sin(((i*1.13)*3.14)/180)*200));
+  }
+  
+  myGLCD.setColor(255,0,0);
+  myGLCD.print("Cos", 5, 27);
+  for (int i=1; i<798; i++)
+  {
+    myGLCD.drawPixel(i,239+(cos(((i*1.13)*3.14)/180)*200));
+  }
+
+  myGLCD.setColor(255,255,0);
+  myGLCD.print("Tan", 5, 39);
+  for (int i=1; i<798; i++)
+  {
+    myGLCD.drawPixel(i,239+(tan(((i*0.9)*3.14)/180)));
+  }
+
+  delay(2000);
+
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.setBackColor(0, 0, 0);
+  myGLCD.drawLine(399, 15, 399, 464);
+  myGLCD.drawLine(1, 239, 798, 239);
+
+// Draw a moving sinewave
+  x=1;
+  for (int i=1; i<(798*20); i++) 
+  {
+    x++;
+    if (x==799)
+      x=1;
+    if (i>799)
+    {
+      if ((x==399)||(buf[x-1]==239))
+        myGLCD.setColor(0,0,255);
+      else
+        myGLCD.setColor(0,0,0);
+      myGLCD.drawPixel(x,buf[x-1]);
+    }
+    myGLCD.setColor(0,255,255);
+    y=239+(sin(((i*1.65)*3.14)/180)*(200-(i / 100)));
+    myGLCD.drawPixel(x,y);
+    buf[x-1]=y;
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random filled rectangles
+  for (int i=0; i<50; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(746);
+    y=16+random(397);
+    x2=x+50;
+    y2=y+50;
+    myGLCD.fillRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random filled, rounded rectangles
+  for (int i=0; i<50; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(746);
+    y=16+random(397);
+    x2=x+50;
+    y2=y+50;
+    myGLCD.fillRoundRect(x, y, x2, y2);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random filled circles
+  for (int i=0; i<50; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=27+random(746);
+    y=41+random(397);
+    myGLCD.fillCircle(x, y, 25);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some lines in a pattern
+  myGLCD.setColor (255,0,0);
+  for (int i=15; i<463; i+=5)
+  {
+    myGLCD.drawLine(1, i, (i*1.66)-10, 463);
+  }
+  myGLCD.setColor (255,0,0);
+  for (int i=463; i>15; i-=5)
+  {
+    myGLCD.drawLine(798, i, (i*1.66)+30, 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=463; i>15; i-=5)
+  {
+    myGLCD.drawLine(1, i, 770-(i*1.66), 15);
+  }
+  myGLCD.setColor (0,255,255);
+  for (int i=15; i<463; i+=5)
+  {
+    myGLCD.drawLine(798, i, 810-(i*1.66), 463);
+  }
+  
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random circles
+  for (int i=0; i<250; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=32+random(736);
+    y=45+random(386);
+    r=random(30);
+    myGLCD.drawCircle(x, y, r);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random rectangles
+  for (int i=0; i<250; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(796);
+    y=16+random(447);
+    x2=2+random(796);
+    y2=16+random(447);
+    myGLCD.drawRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+// Draw some random rounded rectangles
+  for (int i=0; i<250; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(796);
+    y=16+random(447);
+    x2=2+random(796);
+    y2=16+random(447);
+    myGLCD.drawRoundRect(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+  for (int i=0; i<250; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    x=2+random(796);
+    y=16+random(447);
+    x2=2+random(796);
+    y2=16+random(447);
+    myGLCD.drawLine(x, y, x2, y2);
+  }
+
+  delay(2000);
+  
+  myGLCD.setColor(0,0,0);
+  myGLCD.fillRect(1,15,798,464);
+
+  for (int i=0; i<10000; i++)
+  {
+    myGLCD.setColor(random(255), random(255), random(255));
+    myGLCD.drawPixel(2+random(796), 16+random(447));
+  }
+
+  delay(2000);
+
+  myGLCD.fillScr(0, 0, 255);
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRoundRect(320, 190, 479, 289);
+  
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("That's it!", CENTER, 213);
+  myGLCD.print("Restarting in a", CENTER, 239);
+  myGLCD.print("few seconds...", CENTER, 252);
+  
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 255);
+  myGLCD.print("Runtime: (msecs)", CENTER, 450);
+  myGLCD.printNumI(millis(), CENTER, 465);
+  
+  delay (10000);
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Rotate_Bitmap/UTFT_Rotate_Bitmap.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Rotate_Bitmap/UTFT_Rotate_Bitmap.pde
new file mode 100644
index 0000000..863201b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Rotate_Bitmap/UTFT_Rotate_Bitmap.pde
@@ -0,0 +1,33 @@
+// UTFT_Rotate_Bitmap (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the drawBitmap()-function.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Uncomment the next line for chipKit Uno32/uC32
+UTFT myGLCD(ITDB24D,34,35,36,37);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for chipKit Max32
+//UTFT myGLCD(ITDB24D,82,83,84,85);   // Remember to change the model parameter to suit your display module!
+
+extern unsigned short biohazard[0x1000];
+
+void setup()
+{
+  myGLCD.InitLCD(LANDSCAPE);
+  myGLCD.fillScr(255, 255, 255);
+  myGLCD.setColor(0, 0, 0);
+}
+
+void loop()
+{
+    for (int i=0; i<360; i+=5)
+    {
+      myGLCD.drawBitmap (10, 10, 64, 64, biohazard, i, 32, 32);
+    }
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Rotate_Bitmap/biohazard.c b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Rotate_Bitmap/biohazard.c
new file mode 100644
index 0000000..ca1348d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Rotate_Bitmap/biohazard.c
@@ -0,0 +1,264 @@
+// Generated by  : ImageConverter 565 v1.0
+// Generated from: biohazard1_L.png
+// Time generated: 12.06.2011 00:23:59
+// Dimensions    : 64x64 pixels
+// Size          : 8 192 Bytes
+
+const unsigned short biohazard[0x1000] ={
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0010 (16)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF7D, 0xC638, 0x9492, 0x6B4D, 0x4228, 0x2945, 0x2124, 0x18C3, 0x1082,   // 0x0020 (32)
+0x1082, 0x10A2, 0x18C3, 0x2124, 0x2965, 0x4A49, 0x6B6D, 0x9CD3, 0xCE79, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0030 (48)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0040 (64)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0050 (80)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0xBDD7, 0x6B6D, 0x2965, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0060 (96)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0841, 0x31A6, 0x73AE, 0xC618, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0070 (112)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0080 (128)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0090 (144)
+0xFFFF, 0xFFFF, 0xE73C, 0x8C71, 0x3186, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0020, 0x0020, 0x0000, 0x0000,   // 0x00A0 (160)
+0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x4207, 0x9CF3, 0xF79E, 0xFFFF,   // 0x00B0 (176)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00C0 (192)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x00D0 (208)
+0xEF7D, 0x8C51, 0x2104, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x00E0 (224)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x2965, 0x9CD3,   // 0x00F0 (240)
+0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0100 (256)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAD75,   // 0x0110 (272)
+0x2965, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0000, 0x0000, 0x0000, 0x0020, 0x2901, 0x5241, 0x7B41, 0x9C02, 0xACA2, 0xBD02,   // 0x0120 (288)
+0xC521, 0xBD02, 0xACA2, 0x9C22, 0x7B41, 0x5241, 0x2901, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0130 (304)
+0x39E7, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0140 (320)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xEF5D, 0x630C, 0x0000,   // 0x0150 (336)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x41C1, 0x93E1, 0xD5A1, 0xFEA1, 0xFF01, 0xFF20, 0xFF20, 0xFF20, 0xFF00,   // 0x0160 (352)
+0xFF00, 0xFF00, 0xFF20, 0xFF20, 0xFF20, 0xFF01, 0xFEA1, 0xD5A1, 0x93E1, 0x49E1, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0170 (368)
+0x0000, 0x0841, 0x7BEF, 0xF7BE, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0180 (384)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xC638, 0x2965, 0x0000, 0x0000,   // 0x0190 (400)
+0x0000, 0x0000, 0x0000, 0x0000, 0x18A0, 0x7B41, 0xD5A1, 0xFF01, 0xFF20, 0xFEE0, 0xFEC0, 0xFEA0, 0xF680, 0xF680, 0xFEA0, 0xFEA0,   // 0x01A0 (416)
+0xFEA0, 0xFEA0, 0xFEA0, 0xF680, 0xF680, 0xFEA0, 0xFEC0, 0xFF00, 0xFF20, 0xFF01, 0xD5A1, 0x7B41, 0x1880, 0x0000, 0x0000, 0x0000,   // 0x01B0 (432)
+0x0000, 0x0000, 0x0000, 0x4208, 0xDEDB, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x01C0 (448)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAD55, 0x1082, 0x0000, 0x0000, 0x0000,   // 0x01D0 (464)
+0x0000, 0x0000, 0x0840, 0x7B62, 0xEE41, 0xFF21, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF20, 0xFF20, 0xFEA1, 0xFEC0,   // 0x01E0 (480)
+0xFEC0, 0xFEC0, 0xFEA1, 0xFF00, 0xFF20, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEE0, 0xFF21, 0xEE41, 0x7B62, 0x0840, 0x0000,   // 0x01F0 (496)
+0x0000, 0x0000, 0x0000, 0x0000, 0x18E3, 0xC618, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0200 (512)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x94B2, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0210 (528)
+0x0000, 0x5201, 0xDDE1, 0xFF21, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF40, 0xF6A1, 0xB4C1, 0x7322, 0xA441, 0xFEE0,   // 0x0220 (544)
+0xFEA0, 0xFEE0, 0xA461, 0x7322, 0xACA1, 0xF681, 0xFF40, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF21, 0xDDE2, 0x4A01,   // 0x0230 (560)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1082, 0xB596, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0240 (576)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x9492, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0820,   // 0x0250 (592)
+0x9402, 0xFF01, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEE0, 0xFF01, 0x9401, 0x3961, 0x7341, 0xCD81, 0xF680, 0xFEC0,   // 0x0260 (608)
+0xFEA0, 0xFEC0, 0xF681, 0xCD81, 0x7B61, 0x3961, 0x8BE1, 0xFEE1, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEE0, 0xFF01,   // 0x0270 (624)
+0x9402, 0x0820, 0x0000, 0x0000, 0x0000, 0x0000, 0x0841, 0xB596, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0280 (640)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xA534, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x20C0, 0xCD61,   // 0x0290 (656)
+0xFF40, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF01, 0xE621, 0x39A1, 0x20E1, 0xCD81, 0xFF40, 0xFEE0, 0xFEC0, 0xFEC0,   // 0x02A0 (672)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEE0, 0xFF41, 0xCDC1, 0x2901, 0x3961, 0xDE01, 0xFF00, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEA0,   // 0x02B0 (688)
+0xFF21, 0xC561, 0x18A1, 0x0000, 0x0000, 0x0000, 0x0000, 0x1082, 0xC618, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x02C0 (704)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xC618, 0x0861, 0x0000, 0x0000, 0x0000, 0x0000, 0x3121, 0xDE01, 0xFF00,   // 0x02D0 (720)
+0xFE80, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF01, 0xD5A2, 0x18A0, 0x20E0, 0xF682, 0xFF01, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x02E0 (736)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF00, 0xF6A1, 0x2920, 0x1080, 0xCDA2, 0xFF01, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x02F0 (752)
+0xFE80, 0xFF00, 0xDE01, 0x2921, 0x0000, 0x0000, 0x0000, 0x0000, 0x18E3, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0300 (768)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE73C, 0x2124, 0x0000, 0x0000, 0x0000, 0x0000, 0x2921, 0xEE41, 0xFF00, 0xFEA0,   // 0x0310 (784)
+0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEE0, 0xDE02, 0x18A1, 0x0840, 0xDDE1, 0xFF00, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x0320 (800)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEE0, 0xE621, 0x0860, 0x1880, 0xD5E2, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0330 (816)
+0xFEA0, 0xFEA0, 0xFF00, 0xE641, 0x2921, 0x0000, 0x0000, 0x0000, 0x0000, 0x4208, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0340 (832)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x5ACB, 0x0000, 0x0000, 0x0000, 0x0000, 0x18C0, 0xDE21, 0xFF00, 0xFEA0, 0xFEC0,   // 0x0350 (848)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC1, 0x39A1, 0x0000, 0x8382, 0xFF21, 0xFE80, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0360 (864)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFE80, 0xFF20, 0x8BC1, 0x0000, 0x3161, 0xF6A1, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0370 (880)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFF00, 0xDE01, 0x18A0, 0x0000, 0x0000, 0x0000, 0x0000, 0x7BCF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0380 (896)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xA534, 0x0000, 0x0000, 0x0000, 0x0000, 0x0820, 0xCD61, 0xFF00, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x0390 (912)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF21, 0x93E1, 0x0000, 0x1060, 0xDE01, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x03A0 (928)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEE0, 0xE621, 0x1080, 0x0000, 0x8BA1, 0xFF20, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x03B0 (944)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF00, 0xCD61, 0x0820, 0x0000, 0x0000, 0x0000, 0x0021, 0xBDF7, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x03C0 (960)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xEF5D, 0x2104, 0x0000, 0x0000, 0x0000, 0x0000, 0x9402, 0xFF41, 0xFE80, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x03D0 (976)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0, 0xF681, 0x20E0, 0x0000, 0x41A1, 0xFEE1, 0xFEA0, 0xFEA1, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x03E0 (992)
+0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF01, 0x49E1, 0x0000, 0x18A1, 0xEE41, 0xFEC0, 0xFEA0, 0xFEC0,   // 0x03F0 (1008)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFE80, 0xFF41, 0x9402, 0x0000, 0x0000, 0x0000, 0x0000, 0x39C7, 0xF7BE, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0400 (1024)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x7BCF, 0x0000, 0x0000, 0x0000, 0x0000, 0x4A01, 0xFF01, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0410 (1040)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFF20, 0xA461, 0x0000, 0x0000, 0x6AC1, 0xFF21, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x0420 (1056)
+0xFEE0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFE80, 0xFF20, 0x7300, 0x0000, 0x0000, 0x9C21, 0xFF20, 0xFEA0, 0xFEC0,   // 0x0430 (1072)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFF01, 0x49E1, 0x0000, 0x0000, 0x0000, 0x0000, 0x9CD3, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0440 (1088)
+0xFFFF, 0xFFFF, 0xFFFF, 0xDEFB, 0x10A2, 0x0000, 0x0000, 0x0000, 0x0840, 0xDDE1, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0450 (1104)
+0xFEA0, 0xFEA0, 0xFEA0, 0xFF20, 0x6261, 0x0000, 0x0000, 0x7300, 0xFF21, 0xF6A0, 0xFEA0, 0xFEE0, 0xFF20, 0xFF00, 0xFEA1, 0xEE42,   // 0x0460 (1120)
+0xE602, 0xEE42, 0xFEA1, 0xFF00, 0xFF20, 0xFEE0, 0xFEA0, 0xF681, 0xFF40, 0x8360, 0x0000, 0x0000, 0x5241, 0xFF01, 0xFEA0, 0xFEA0,   // 0x0470 (1136)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF00, 0xDDC1, 0x0840, 0x0000, 0x0000, 0x0000, 0x2945, 0xEF7D, 0xFFFF, 0xFFFF,   // 0x0480 (1152)
+0xFFFF, 0xFFDF, 0xFFFF, 0x7BEF, 0x0000, 0x0000, 0x0000, 0x0000, 0x7B42, 0xFF21, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0490 (1168)
+0xFEC0, 0xFEA0, 0xFEC0, 0xFEA0, 0x2900, 0x0000, 0x0000, 0x6AE0, 0xFF21, 0xFEC0, 0xFF01, 0xDE01, 0x9C01, 0x5241, 0x2921, 0x18A1,   // 0x04A0 (1184)
+0x1061, 0x1881, 0x2921, 0x5241, 0x9C02, 0xDDE1, 0xFF21, 0xFEC0, 0xFF20, 0x7321, 0x0000, 0x0000, 0x20E0, 0xF681, 0xFEC0, 0xFEA0,   // 0x04B0 (1200)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF21, 0x7B41, 0x0000, 0x0000, 0x0000, 0x0000, 0x9CD3, 0xFFFF, 0xFFDF,   // 0x04C0 (1216)
+0xFFDF, 0xFFFF, 0xEF7D, 0x2104, 0x0000, 0x0000, 0x0000, 0x1080, 0xEE41, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x04D0 (1232)
+0xFEC0, 0xFEA0, 0xFEC0, 0xEE21, 0x1060, 0x0000, 0x0000, 0x41C1, 0xFF21, 0xDDE1, 0x6AC1, 0x0860, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x04E0 (1248)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0860, 0x62C1, 0xDDC1, 0xFF41, 0x49E1, 0x0000, 0x0000, 0x0840, 0xE601, 0xFEE0, 0xFEA0,   // 0x04F0 (1264)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0, 0xEE41, 0x1080, 0x0000, 0x0000, 0x0000, 0x39C7, 0xF7BE, 0xFFFF,   // 0x0500 (1280)
+0xFFDF, 0xFFFF, 0xA534, 0x0000, 0x0000, 0x0000, 0x0000, 0x7B21, 0xFF21, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0510 (1296)
+0xFEA0, 0xFEA0, 0xFEE0, 0xE602, 0x0841, 0x0000, 0x0000, 0x1080, 0xACC2, 0x1060, 0x0000, 0x0000, 0x0000, 0x0020, 0x2920, 0x4A01,   // 0x0520 (1312)
+0x5241, 0x4A01, 0x3140, 0x0821, 0x0000, 0x0000, 0x0000, 0x0860, 0xACA2, 0x18A0, 0x0000, 0x0000, 0x0820, 0xDDE2, 0xFEE0, 0xFEA0,   // 0x0530 (1328)
+0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFE80, 0xFF21, 0x7321, 0x0000, 0x0000, 0x0000, 0x0020, 0xC618, 0xFFFF,   // 0x0540 (1344)
+0xFFFF, 0xFFFF, 0x52AA, 0x0000, 0x0020, 0x0000, 0x0820, 0xDDA1, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0550 (1360)
+0xFEC0, 0xFEA0, 0xFEE0, 0xE621, 0x1060, 0x0000, 0x0000, 0x0000, 0x6AE2, 0x20C1, 0x0000, 0x20E1, 0x8BA2, 0xD5A1, 0xFEA1, 0xFF00,   // 0x0560 (1376)
+0xFF01, 0xFF00, 0xFEC1, 0xD5C1, 0x8BC2, 0x2901, 0x0000, 0x18A1, 0x7302, 0x0000, 0x0000, 0x0000, 0x0840, 0xDE01, 0xFEE0, 0xFEA0,   // 0x0570 (1392)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEE0, 0xD5A1, 0x0020, 0x0000, 0x0000, 0x0000, 0x738E, 0xFFFF,   // 0x0580 (1408)
+0xFFFF, 0xE71C, 0x18C3, 0x0000, 0x0020, 0x0000, 0x49C1, 0xFF01, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0590 (1424)
+0xFEA0, 0xFEA0, 0xFEC0, 0xF661, 0x18A0, 0x0000, 0x0000, 0x0000, 0x2101, 0x8363, 0x7321, 0xEE81, 0xFF21, 0xFEE0, 0xFEC0, 0xFEA0,   // 0x05A0 (1440)
+0xFEA0, 0xFEA0, 0xFEC0, 0xFEE0, 0xFF20, 0xF681, 0x7B41, 0x8362, 0x2921, 0x0000, 0x0000, 0x0000, 0x1080, 0xEE41, 0xFEC0, 0xFEA0,   // 0x05B0 (1456)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFF01, 0x41C1, 0x0000, 0x0020, 0x0000, 0x3186, 0xF79E,   // 0x05C0 (1472)
+0xFFFF, 0xAD75, 0x0000, 0x0000, 0x0020, 0x0000, 0x93E1, 0xFF20, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0,   // 0x05D0 (1488)
+0xFEC0, 0xFEA0, 0xFEA0, 0xFF41, 0x5221, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0xFF01, 0xFF00, 0xF660, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x05E0 (1504)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xF660, 0xFF00, 0xFF22, 0x49E1, 0x0000, 0x0000, 0x0000, 0x0000, 0x49E1, 0xFF40, 0xFEA0, 0xFEA0,   // 0x05F0 (1520)
+0xFEA1, 0xFEC0, 0xFEA1, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF20, 0x93E1, 0x0000, 0x0020, 0x0000, 0x0020, 0xC638,   // 0x0600 (1536)
+0xFFFF, 0x73AE, 0x0000, 0x0000, 0x0000, 0x0020, 0xD5A1, 0xFF00, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA1, 0xFEA0,   // 0x0610 (1552)
+0xFEA1, 0xFF20, 0xFEC1, 0xD5C1, 0x5220, 0x0000, 0x0000, 0x0000, 0x0020, 0x0000, 0x3981, 0xE622, 0xFF20, 0xFEC0, 0xFEA0, 0xFEA0,   // 0x0620 (1568)
+0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF21, 0xE621, 0x41C1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x49E0, 0xCDA2, 0xFEA1, 0xFF20,   // 0x0630 (1584)
+0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF00, 0xD5A1, 0x0020, 0x0000, 0x0000, 0x0000, 0x9492,   // 0x0640 (1600)
+0xFFFF, 0x4A49, 0x0000, 0x0020, 0x0000, 0x2901, 0xFEA1, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEE0,   // 0x0650 (1616)
+0xFEE1, 0xA461, 0x3981, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1881, 0x93E1, 0xE622, 0xFF01, 0xFF00,   // 0x0660 (1632)
+0xFEA0, 0xFF00, 0xFF21, 0xEE41, 0x9401, 0x18A1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3141, 0x9C21,   // 0x0670 (1648)
+0xFEC1, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEA1, 0x2901, 0x0000, 0x0020, 0x0000, 0x632C,   // 0x0680 (1664)
+0xE71C, 0x2124, 0x0000, 0x0020, 0x0000, 0x5241, 0xFF01, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF00, 0xD5C1,   // 0x0690 (1680)
+0x41C1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1081, 0x4A01, 0xAC81,   // 0x06A0 (1696)
+0xFF21, 0xB4C1, 0x5221, 0x1081, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x06B0 (1712)
+0x3981, 0xCD81, 0xFF21, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF01, 0x5221, 0x0000, 0x0020, 0x0000, 0x4228,   // 0x06C0 (1728)
+0xBDF7, 0x18C3, 0x0000, 0x0020, 0x0000, 0x7B41, 0xFF20, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF20, 0xBD02, 0x1060,   // 0x06D0 (1744)
+0x0000, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x5201,   // 0x06E0 (1760)
+0xFFC0, 0x5A41, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020,   // 0x06F0 (1776)
+0x0000, 0x0840, 0xACA1, 0xFF21, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF20, 0x7B41, 0x0000, 0x0020, 0x0000, 0x2945,   // 0x0700 (1792)
+0x94B2, 0x0861, 0x0000, 0x0000, 0x0000, 0x9C02, 0xFF20, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF00, 0xBD22, 0x0820, 0x0000,   // 0x0710 (1808)
+0x0820, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1881, 0xAC81,   // 0x0720 (1824)
+0xFF20, 0xB4A1, 0x18A1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0730 (1840)
+0x0020, 0x0000, 0x0000, 0xB4C2, 0xFF00, 0xFE80, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF20, 0x9C02, 0x0000, 0x0020, 0x0000, 0x2104,   // 0x0740 (1856)
+0x73AE, 0x0841, 0x0000, 0x0000, 0x0000, 0xACA2, 0xFF20, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEE0, 0xE622, 0x18A1, 0x0000, 0x0000,   // 0x0750 (1872)
+0x0000, 0x1080, 0x5221, 0x6B03, 0x6AE2, 0x6AE3, 0x4A01, 0x1080, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1061, 0xCD82, 0xFF20,   // 0x0760 (1888)
+0xFE80, 0xFF20, 0xD5C2, 0x1881, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1080, 0x5241, 0x6AE3, 0x6AE2, 0x6AE3, 0x5A62, 0x18C0,   // 0x0770 (1904)
+0x0000, 0x0000, 0x0000, 0x1060, 0xDDE2, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF20, 0xACA2, 0x0000, 0x0000, 0x0000, 0x10A2,   // 0x0780 (1920)
+0x52AA, 0x0000, 0x0000, 0x0000, 0x0000, 0xBD02, 0xFF00, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF01, 0x5A61, 0x0000, 0x0000, 0x18A0,   // 0x0790 (1936)
+0x9401, 0xEE61, 0xFEE2, 0x49E2, 0x18A1, 0x62A1, 0xFF41, 0xE621, 0x8BC2, 0x1880, 0x0000, 0x0820, 0x0000, 0x7B21, 0xFF40, 0xFE80,   // 0x07A0 (1952)
+0xFEC0, 0xFE80, 0xFF40, 0x8381, 0x0000, 0x0820, 0x0000, 0x1080, 0x8BE2, 0xEE41, 0xFF41, 0x62A2, 0x10A1, 0x3982, 0xFEC2, 0xF6A1,   // 0x07B0 (1968)
+0xA462, 0x2101, 0x0000, 0x0000, 0x49E1, 0xFF01, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF00, 0xBD02, 0x0000, 0x0000, 0x0000, 0x1082,   // 0x07C0 (1984)
+0x528A, 0x0000, 0x0000, 0x0000, 0x0000, 0xC521, 0xFF00, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF00, 0xCD41, 0x0000, 0x0000, 0x49C1, 0xE642,   // 0x07D0 (2000)
+0xFF21, 0xFEE0, 0xEE42, 0x1081, 0x0000, 0x41A0, 0xFEE0, 0xFEC0, 0xFF40, 0xE621, 0x41A1, 0x0000, 0x0000, 0x93E1, 0xFF20, 0xFEA0,   // 0x07E0 (2016)
+0xFEA0, 0xFEA0, 0xFF20, 0x9C22, 0x0000, 0x0000, 0x3981, 0xDE01, 0xFF21, 0xFEC0, 0xFEE1, 0x49E1, 0x0000, 0x0840, 0xE602, 0xFEC0,   // 0x07F0 (2032)
+0xFF20, 0xEE81, 0x5A61, 0x0000, 0x0000, 0xBCE1, 0xFF00, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF00, 0xC521, 0x0000, 0x0000, 0x0000, 0x1082,   // 0x0800 (2048)
+0x52AA, 0x0000, 0x0000, 0x0000, 0x0000, 0xBD02, 0xFF00, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF20, 0x6AC1, 0x0000, 0x49E1, 0xFEE2, 0xFEE0,   // 0x0810 (2064)
+0xFE80, 0xFEC0, 0xF682, 0x20E1, 0x0000, 0x39A0, 0xFEE0, 0xFEA0, 0xFE80, 0xFEE0, 0xF6A2, 0x41A1, 0x3961, 0xDDC1, 0xFF00, 0xFE80,   // 0x0820 (2080)
+0xFEA0, 0xFEA0, 0xFF00, 0xE601, 0x41C1, 0x3981, 0xF682, 0xFF00, 0xFE80, 0xFEA0, 0xFF00, 0x41C1, 0x0000, 0x20C1, 0xF661, 0xFEC0,   // 0x0830 (2096)
+0xF6A0, 0xFEC0, 0xFF01, 0x6261, 0x0000, 0x5A41, 0xFF01, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF00, 0xBD02, 0x0000, 0x0000, 0x0000, 0x1082,   // 0x0840 (2112)
+0x738E, 0x0841, 0x0000, 0x0000, 0x0000, 0xACA2, 0xFF20, 0xFEA0, 0xFEA0, 0xFEC0, 0xF681, 0x18A0, 0x1080, 0xEE41, 0xFEE0, 0xFEA0,   // 0x0850 (2128)
+0xFEC0, 0xFEA0, 0xFEE1, 0x3980, 0x0000, 0x20C0, 0xF662, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEE0, 0xF681, 0xFEE1, 0xFF01, 0xDDC1, 0xFF21,   // 0x0860 (2144)
+0xFF20, 0xFF21, 0xDDC1, 0xFEC1, 0xFF01, 0xF661, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEA1, 0x2900, 0x0000, 0x3140, 0xFEA1, 0xFEA0,   // 0x0870 (2160)
+0xFEA0, 0xFEA0, 0xFEC0, 0xF6A1, 0x2101, 0x0840, 0xEE41, 0xFEE0, 0xFEA0, 0xFEA0, 0xFF20, 0xAC82, 0x0000, 0x0000, 0x0000, 0x10A2,   // 0x0880 (2176)
+0x9492, 0x0861, 0x0000, 0x0000, 0x0000, 0x9C02, 0xFF20, 0xFEA0, 0xFEA0, 0xFF00, 0xD582, 0x0000, 0x93C1, 0xFF40, 0xFE80, 0xFEC0,   // 0x0890 (2192)
+0xFEC0, 0xFEA0, 0xFF21, 0x6AC1, 0x0000, 0x0000, 0xCD41, 0xFF00, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEE0, 0xDDE1, 0x41A1, 0x0860, 0x6AC1,   // 0x08A0 (2208)
+0x93E1, 0x6AE1, 0x0841, 0x3161, 0xD5C1, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF00, 0xCD61, 0x0000, 0x0000, 0x5A81, 0xFF21, 0xFEA0,   // 0x08B0 (2224)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFF20, 0xAC81, 0x0000, 0xC521, 0xFF00, 0xFEA0, 0xFEA0, 0xFF20, 0x9C02, 0x0000, 0x0020, 0x0000, 0x2104,   // 0x08C0 (2240)
+0xB5B6, 0x10A2, 0x0000, 0x0020, 0x0000, 0x7B41, 0xFF20, 0xFEA0, 0xFEA0, 0xFF20, 0xAC80, 0x0820, 0xEE41, 0xFEC0, 0xFEA0, 0xFEC0,   // 0x08D0 (2256)
+0xFEC0, 0xFEA0, 0xFF00, 0xAC81, 0x0000, 0x0000, 0x7301, 0xFF20, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEE0, 0xD5C1, 0x0000, 0x0000, 0x0000,   // 0x08E0 (2272)
+0x0000, 0x0000, 0x0000, 0x0000, 0xD561, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF41, 0x7B42, 0x0000, 0x0000, 0xA442, 0xFF21, 0xFEA0,   // 0x08F0 (2288)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA1, 0x1080, 0x9C00, 0xFF40, 0xFEA0, 0xFEA0, 0xFF20, 0x7B41, 0x0000, 0x0020, 0x0000, 0x2124,   // 0x0900 (2304)
+0xDEFB, 0x2104, 0x0000, 0x0020, 0x0000, 0x5221, 0xFF01, 0xFEA0, 0xFEA0, 0xFF40, 0x93C0, 0x3961, 0xFF21, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x0910 (2320)
+0xFEC0, 0xFEA0, 0xFEC0, 0xEE61, 0x1881, 0x0000, 0x1080, 0xEE21, 0xFEE0, 0xFEA0, 0xFEC0, 0xFEA0, 0xFF01, 0x41C1, 0x0000, 0x0020,   // 0x0920 (2336)
+0x0000, 0x0020, 0x0000, 0x3961, 0xFEE1, 0xFEA0, 0xFEC0, 0xFEA0, 0xFEC0, 0xEE61, 0x18A1, 0x0000, 0x1060, 0xE621, 0xFEC0, 0xFEA0,   // 0x0930 (2352)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF21, 0x4A01, 0x8361, 0xFF40, 0xFEA0, 0xFEA0, 0xFF01, 0x5221, 0x0000, 0x0020, 0x0000, 0x4208,   // 0x0940 (2368)
+0xFFDF, 0x4208, 0x0000, 0x0000, 0x0000, 0x2901, 0xFEA1, 0xFEC0, 0xFEA0, 0xFF40, 0x93C0, 0x5A60, 0xFF41, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x0950 (2384)
+0xFEA0, 0xFEC0, 0xFEA0, 0xFF21, 0x7B41, 0x0000, 0x0000, 0x6281, 0xFF21, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF21, 0x62A1, 0x0000, 0x0000,   // 0x0960 (2400)
+0x0000, 0x0000, 0x0000, 0x5A41, 0xFF01, 0xFEA0, 0xFEA0, 0xF680, 0xFF41, 0x6AC1, 0x0000, 0x0000, 0x7301, 0xFF21, 0xFEA0, 0xFEA0,   // 0x0970 (2416)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF40, 0x6AE1, 0x8361, 0xFF40, 0xFEA0, 0xFEC0, 0xFEA1, 0x2901, 0x0000, 0x0020, 0x0000, 0x630C,   // 0x0980 (2432)
+0xFFFF, 0x6B6D, 0x0000, 0x0020, 0x0000, 0x0020, 0xD5A1, 0xFF00, 0xFEA0, 0xFF20, 0xA461, 0x6AC0, 0xFF40, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x0990 (2448)
+0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xEE61, 0x18C0, 0x0000, 0x0000, 0x93E2, 0xFF41, 0xFEA0, 0xFE80, 0xFF20, 0x6AE1, 0x0000, 0x0000,   // 0x09A0 (2464)
+0x0000, 0x0000, 0x0000, 0x62A1, 0xFF21, 0xFE80, 0xFEA0, 0xFF40, 0x9C22, 0x0000, 0x0000, 0x1881, 0xE641, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x09B0 (2480)
+0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF40, 0x7B61, 0x9C00, 0xFF40, 0xFE80, 0xFF00, 0xD581, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C51,   // 0x09C0 (2496)
+0xFFFF, 0xA534, 0x0000, 0x0000, 0x0000, 0x0000, 0x93E1, 0xFF20, 0xFE80, 0xFF00, 0xC541, 0x72E1, 0xFF20, 0xFEA0, 0xFEC0, 0xFEC0,   // 0x09D0 (2512)
+0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF00, 0xB4C1, 0x0000, 0x0020, 0x0000, 0x93E1, 0xFF21, 0xFEC0, 0xFF01, 0x5A81, 0x0000, 0x0000,   // 0x09E0 (2528)
+0x0000, 0x0000, 0x0000, 0x5222, 0xFF01, 0xFEC0, 0xFF21, 0x9C01, 0x0000, 0x0020, 0x0000, 0xAC81, 0xFF01, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x09F0 (2544)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF20, 0x7B40, 0xBD01, 0xFF20, 0xF680, 0xFF20, 0x93C1, 0x0000, 0x0020, 0x0000, 0x0000, 0xBDF7,   // 0x0A00 (2560)
+0xFFFF, 0xDEDB, 0x1082, 0x0000, 0x0000, 0x0000, 0x41C1, 0xFF01, 0xFEA0, 0xFEC0, 0xF660, 0x6AC2, 0xF6A1, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0A10 (2576)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFF21, 0x8BA1, 0x0000, 0x0000, 0x0000, 0x6281, 0xDE21, 0xFF01, 0x3161, 0x0000, 0x0000,   // 0x0A20 (2592)
+0x0000, 0x0000, 0x0000, 0x2921, 0xFEE1, 0xE641, 0x62A1, 0x0000, 0x0000, 0x0000, 0x8381, 0xFF21, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0A30 (2608)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEC1, 0x6AC2, 0xE621, 0xFEE0, 0xFEA0, 0xFF01, 0x41C1, 0x0000, 0x0020, 0x0000, 0x2124, 0xEF5D,   // 0x0A40 (2624)
+0xFFFF, 0xFFFF, 0x4A49, 0x0000, 0x0000, 0x0000, 0x0020, 0xD5A1, 0xFEE0, 0xFEA0, 0xFEC0, 0xCD41, 0xF660, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0A50 (2640)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFF21, 0x8BC1, 0x0000, 0x0000, 0x0000, 0x1060, 0xA442, 0x0860, 0x0000, 0x0000,   // 0x0A60 (2656)
+0x0000, 0x0000, 0x0000, 0x0820, 0xA442, 0x18A0, 0x0000, 0x0000, 0x0000, 0x8381, 0xFF21, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0A70 (2672)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFE80, 0xCD62, 0xFEC0, 0xFEA1, 0xFEE0, 0xD5A1, 0x0020, 0x0000, 0x0000, 0x0000, 0x630C, 0xFFFF,   // 0x0A80 (2688)
+0xFFDF, 0xFFFF, 0x94B2, 0x0000, 0x0000, 0x0000, 0x0000, 0x7321, 0xFF21, 0xFEA0, 0xFEA0, 0xFEE0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x0A90 (2704)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFF21, 0xB4C1, 0x20E1, 0x0000, 0x3161, 0x62A2, 0x0000, 0x0000, 0x0000,   // 0x0AA0 (2720)
+0x0000, 0x0000, 0x0000, 0x0000, 0x5A82, 0x39A1, 0x0000, 0x20C1, 0xAC82, 0xFF21, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0AB0 (2736)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEC0, 0xFEE0, 0xFEA0, 0xFEA0, 0xFF21, 0x7321, 0x0000, 0x0000, 0x0000, 0x0000, 0xB596, 0xFFFF,   // 0x0AC0 (2752)
+0xFFDF, 0xFFFF, 0xE73C, 0x18C3, 0x0000, 0x0000, 0x0000, 0x1080, 0xEE41, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA1, 0xFF00, 0xFEE0, 0xFEA0,   // 0x0AD0 (2768)
+0xFEC0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFF00, 0xEE41, 0x83C1, 0x8BA3, 0x1081, 0x0000, 0x0000, 0x0000,   // 0x0AE0 (2784)
+0x0000, 0x0000, 0x0000, 0x0000, 0x1060, 0x8383, 0x83A1, 0xEE41, 0xFF00, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0,   // 0x0AF0 (2800)
+0xFEC0, 0xFEA0, 0xFEC0, 0xFF00, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xEE21, 0x1080, 0x0000, 0x0000, 0x0000, 0x2945, 0xEF7D, 0xFFFF,   // 0x0B00 (2816)
+0xFFFF, 0xFFFF, 0xFFFF, 0x6B4D, 0x0000, 0x0000, 0x0000, 0x0000, 0x7B41, 0xFF21, 0xFEA0, 0xFEA0, 0xFF00, 0xB482, 0xD5C1, 0xFF20,   // 0x0B10 (2832)
+0xFE80, 0xFEA0, 0xFEA0, 0xFEA1, 0xFEA0, 0xFEC0, 0xFEA1, 0xFEA0, 0xF680, 0xFF20, 0xF6A2, 0x3121, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0B20 (2848)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x20E1, 0xEE62, 0xFF40, 0xF680, 0xFEA0, 0xFEA1, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0,   // 0x0B30 (2864)
+0xF681, 0xFF20, 0xE601, 0xAC62, 0xFF00, 0xFEA0, 0xFE80, 0xFF21, 0x7B41, 0x0000, 0x0000, 0x0000, 0x0000, 0x8410, 0xFFFF, 0xFFFF,   // 0x0B40 (2880)
+0xFFFF, 0xFFDF, 0xFFFF, 0xD69A, 0x0841, 0x0000, 0x0000, 0x0000, 0x0840, 0xDDC1, 0xFEE0, 0xFEA0, 0xFEE1, 0xD5A1, 0x5221, 0xBD21,   // 0x0B50 (2896)
+0xFF41, 0xFF00, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA1, 0xFEC0, 0xFF00, 0xFF21, 0xCD61, 0x20E1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020,   // 0x0B60 (2912)
+0x7322, 0x0840, 0x0000, 0x0000, 0x0000, 0x0000, 0x18A1, 0xBD22, 0xFF21, 0xFF00, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEE0,   // 0x0B70 (2928)
+0xFF40, 0xC561, 0x5221, 0xCD81, 0xFEE0, 0xFE81, 0xFEE0, 0xDDC1, 0x0840, 0x0000, 0x0000, 0x0000, 0x18E3, 0xE71C, 0xFFFF, 0xFFFF,   // 0x0B80 (2944)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x632C, 0x0000, 0x0000, 0x0000, 0x0000, 0x49E1, 0xFF01, 0xFEA0, 0xFEA0, 0xFF00, 0xDE01, 0x4181,   // 0x0B90 (2960)
+0x5A81, 0xD581, 0xFEE1, 0xFF20, 0xFF20, 0xFF01, 0xFEC1, 0xD582, 0x6AE1, 0x0020, 0x0000, 0x0020, 0x0000, 0x0000, 0x1060, 0xACA2,   // 0x0BA0 (2976)
+0xFF61, 0xBD21, 0x18A1, 0x0000, 0x0000, 0x0020, 0x0000, 0x0000, 0x62A2, 0xCD62, 0xFEA1, 0xFF01, 0xFF20, 0xFF20, 0xFEE1, 0xD5C1,   // 0x0BB0 (2992)
+0x62C1, 0x3981, 0xD5C1, 0xFF21, 0xFEA0, 0xFEA0, 0xFF01, 0x49E1, 0x0000, 0x0000, 0x0000, 0x0000, 0x7BEF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0BC0 (3008)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDB, 0x1082, 0x0000, 0x0000, 0x0000, 0x0000, 0x93E2, 0xFF40, 0xFE80, 0xFE80, 0xFEE0, 0xFEC1,   // 0x0BD0 (3024)
+0x6B01, 0x1061, 0x18C1, 0x4A00, 0x5AA0, 0x5240, 0x3141, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x4A01, 0xDDC1, 0xFF20,   // 0x0BE0 (3040)
+0xFE80, 0xFF00, 0xE602, 0x5A41, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2921, 0x5220, 0x5AA0, 0x4A00, 0x20E1, 0x1060,   // 0x0BF0 (3056)
+0x6AE1, 0xF6A1, 0xFEE0, 0xFEA1, 0xFEA0, 0xFF41, 0x93E1, 0x0000, 0x0000, 0x0000, 0x0000, 0x2124, 0xE71C, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C00 (3072)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x8C71, 0x0000, 0x0000, 0x0000, 0x0000, 0x0820, 0xCD61, 0xFF00, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x0C10 (3088)
+0xFF41, 0xDDE1, 0x6B01, 0x18C1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x18A0, 0x5A61, 0xBCE2, 0xFF01, 0xFEE0, 0xFEA0,   // 0x0C20 (3104)
+0xFEC0, 0xFEA0, 0xFEE0, 0xFF01, 0xC541, 0x6281, 0x20C1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x18C1, 0x6AE1, 0xDDC1,   // 0x0C30 (3120)
+0xFF41, 0xFEC0, 0xFEA0, 0xFEA0, 0xFF01, 0xC541, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0xA514, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C40 (3136)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF7BE, 0x4208, 0x0000, 0x0000, 0x0000, 0x0000, 0x18A1, 0xDE01, 0xFF00, 0xFE80, 0xFEC0,   // 0x0C50 (3152)
+0xFEA0, 0xFEE0, 0xFF20, 0xFEC1, 0xD5A2, 0xAC82, 0x9401, 0x93E1, 0x9C42, 0xC522, 0xEE41, 0xFF01, 0xFF00, 0xFEA0, 0xFEA0, 0xFEC0,   // 0x0C60 (3168)
+0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFF00, 0xFF21, 0xF661, 0xC542, 0xA462, 0x93E1, 0x9C01, 0xB4A2, 0xD5A1, 0xFEC1, 0xFF20, 0xFEE0,   // 0x0C70 (3184)
+0xFEA0, 0xFEC0, 0xFE80, 0xFF00, 0xDE01, 0x18A1, 0x0000, 0x0000, 0x0000, 0x0000, 0x52AA, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0C80 (3200)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xD6BA, 0x10A2, 0x0000, 0x0000, 0x0000, 0x0000, 0x2921, 0xE641, 0xFF00, 0xFE80,   // 0x0C90 (3216)
+0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF00, 0xFF20, 0xFF20, 0xFF20, 0xFF20, 0xFF00, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0CA0 (3232)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF00, 0xFF20, 0xFF20, 0xFF20, 0xFF20, 0xFF00, 0xFEC0, 0xFEA0, 0xFEA0,   // 0x0CB0 (3248)
+0xFEA0, 0xFE80, 0xFF00, 0xE641, 0x2901, 0x0000, 0x0000, 0x0000, 0x0000, 0x2124, 0xE71C, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0CC0 (3264)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAD55, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2901, 0xDE01, 0xFF00,   // 0x0CD0 (3280)
+0xFE80, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0CE0 (3296)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEA0,   // 0x0CF0 (3312)
+0xFE80, 0xFF00, 0xDE01, 0x2900, 0x0000, 0x0000, 0x0000, 0x0000, 0x0861, 0xBDD7, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D00 (3328)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0x8430, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x18A1, 0xC561,   // 0x0D10 (3344)
+0xFF21, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0D20 (3360)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0,   // 0x0D30 (3376)
+0xFF41, 0xC561, 0x18A1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x9CD3, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D40 (3392)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x73AE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0820,   // 0x0D50 (3408)
+0x9402, 0xFF01, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0D60 (3424)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEE0, 0xFF01,   // 0x0D70 (3440)
+0x9402, 0x0820, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C51, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0D80 (3456)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x73AE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0D90 (3472)
+0x0000, 0x4A01, 0xDDC1, 0xFF41, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0DA0 (3488)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF21, 0xD5C1, 0x4A01,   // 0x0DB0 (3504)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x8C51, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0DC0 (3520)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x8430, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0DD0 (3536)
+0x0000, 0x0000, 0x0840, 0x7B61, 0xE641, 0xFF21, 0xFEE0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0,   // 0x0DE0 (3552)
+0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEE0, 0xFF21, 0xE621, 0x7B42, 0x0840, 0x0000,   // 0x0DF0 (3568)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0841, 0x9492, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E00 (3584)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xAD55, 0x10A2, 0x0000, 0x0000,   // 0x0E10 (3600)
+0x0000, 0x0000, 0x0000, 0x0000, 0x1880, 0x7B21, 0xD5A1, 0xFF01, 0xFF20, 0xFF00, 0xFEC0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0,   // 0x0E20 (3616)
+0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEA0, 0xFEC0, 0xFF00, 0xFF20, 0xFF01, 0xD5A1, 0x7321, 0x1880, 0x0000, 0x0000, 0x0000,   // 0x0E30 (3632)
+0x0000, 0x0000, 0x0000, 0x18E3, 0xAD75, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E40 (3648)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xD69A, 0x4228, 0x0000,   // 0x0E50 (3664)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x41C1, 0x93E1, 0xD5A1, 0xFEA1, 0xFF01, 0xFF20, 0xFF20, 0xFF20, 0xFF00,   // 0x0E60 (3680)
+0xFF00, 0xFF00, 0xFF20, 0xFF20, 0xFF20, 0xFF01, 0xFEA1, 0xD5A1, 0x93E1, 0x41C1, 0x0020, 0x0000, 0x0000, 0x0020, 0x0000, 0x0000,   // 0x0E70 (3696)
+0x0000, 0x0000, 0x528A, 0xD6BA, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0E80 (3712)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFDF, 0x8C71,   // 0x0E90 (3728)
+0x10A2, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2901, 0x5221, 0x7B41, 0x9402, 0xAC82, 0xBCE2,   // 0x0EA0 (3744)
+0xC521, 0xBCE2, 0xAC82, 0x9401, 0x7B41, 0x5221, 0x2901, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0EB0 (3760)
+0x18E3, 0x94B2, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0EC0 (3776)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0ED0 (3792)
+0xD6BA, 0x632C, 0x0841, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0EE0 (3808)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x10A2, 0x738E,   // 0x0EF0 (3824)
+0xDEFB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F00 (3840)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F10 (3856)
+0xFFFF, 0xFFFF, 0xCE79, 0x6B4D, 0x18C3, 0x0000, 0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0000, 0x0000,   // 0x0F20 (3872)
+0x0000, 0x0000, 0x0000, 0x0020, 0x0020, 0x0020, 0x0020, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2104, 0x738E, 0xD69A, 0xFFFF,   // 0x0F30 (3888)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F40 (3904)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F50 (3920)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xE71C, 0x94B2, 0x4A49, 0x1082, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,   // 0x0F60 (3936)
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x18C3, 0x4A69, 0x9CD3, 0xE73C, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F70 (3952)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F80 (3968)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0F90 (3984)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDB, 0xA534, 0x6B6D, 0x4208, 0x2104, 0x18C3, 0x0861, 0x0841, 0x0000,   // 0x0FA0 (4000)
+0x0000, 0x0000, 0x0841, 0x0861, 0x18C3, 0x2124, 0x4228, 0x6B6D, 0xA534, 0xDEDB, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FB0 (4016)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FC0 (4032)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FD0 (4048)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xDEDB, 0xB5B6, 0x9492, 0x6B6D, 0x4A49,   // 0x0FE0 (4064)
+0x4228, 0x4A49, 0x6B6D, 0x8C51, 0xAD75, 0xDEDB, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFDF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x0FF0 (4080)
+0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,   // 0x1000 (4096)
+};
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Textrotation_Demo/UTFT_Textrotation_Demo.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Textrotation_Demo/UTFT_Textrotation_Demo.pde
new file mode 100644
index 0000000..0d107a9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_Textrotation_Demo/UTFT_Textrotation_Demo.pde
@@ -0,0 +1,48 @@
+// UTFT_Textrotation_Demo (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the textrotation-functions.
+//
+// This demo was made for modules with a screen resolution 
+// of 320x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t BigFont[];
+extern uint8_t SevenSegNumFont[];
+
+// Uncomment the next line for chipKit Uno32/uC32
+UTFT myGLCD(ITDB24D,34,35,36,37);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for chipKit Max32
+//UTFT myGLCD(ITDB24D,82,83,84,85);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  myGLCD.InitLCD();
+  myGLCD.clrScr();
+  myGLCD.setFont(BigFont);
+}
+
+void loop()
+{
+    myGLCD.print("Text rotation", 0, 0);
+    myGLCD.setColor(0, 0, 255);
+    myGLCD.print("0 degrees", 0, 16, 0);
+    myGLCD.print("90 degrees", 319, 0, 90);
+    myGLCD.print("180 degrees", 319, 239, 180);
+    myGLCD.print("270 degrees", 0, 239, 270);
+
+    myGLCD.setFont(SevenSegNumFont);
+    myGLCD.setColor(0, 255, 0);
+    myGLCD.print("45", 90, 100, 45);
+    myGLCD.print("90", 200, 50, 90);
+    myGLCD.print("180", 300, 200, 180);
+
+  while (true) {};
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_ViewFont/UTFT_ViewFont.pde b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_ViewFont/UTFT_ViewFont.pde
new file mode 100644
index 0000000..e844621
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/examples/chipKit/UTFT_ViewFont/UTFT_ViewFont.pde
@@ -0,0 +1,55 @@
+// UTFT_ViewFont (C)2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a demo of the included fonts.
+//
+// This demo was made for modules with a screen resolution 
+// of 320x240 pixels.
+//
+// This program requires the UTFT library.
+//
+
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+extern uint8_t BigFont[];
+extern uint8_t SevenSegNumFont[];
+
+// Uncomment the next line for chipKit Uno32/uC32
+UTFT myGLCD(ITDB24D,34,35,36,37);   // Remember to change the model parameter to suit your display module!
+
+// Uncomment the next line for chipKit Max32
+//UTFT myGLCD(ITDB24D,82,83,84,85);   // Remember to change the model parameter to suit your display module!
+
+void setup()
+{
+  myGLCD.InitLCD();
+
+  myGLCD.clrScr();
+}
+
+void loop()
+{
+  myGLCD.setColor(0, 255, 0);
+  myGLCD.setBackColor(0, 0, 0);
+
+  myGLCD.setFont(BigFont);
+  myGLCD.print(" !\"#$%&'()*+,-./", CENTER, 0);
+  myGLCD.print("0123456789:;<=>?", CENTER, 16);
+  myGLCD.print("@ABCDEFGHIJKLMNO", CENTER, 32);
+  myGLCD.print("PQRSTUVWXYZ[\\]^_", CENTER, 48);
+  myGLCD.print("`abcdefghijklmno", CENTER, 64);
+  myGLCD.print("pqrstuvwxyz{|}~ ", CENTER, 80);
+
+  myGLCD.setFont(SmallFont);
+  myGLCD.print(" !\"#$%&'()*+,-./0123456789:;<=>?", CENTER, 120);
+  myGLCD.print("@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_", CENTER, 132);
+  myGLCD.print("`abcdefghijklmnopqrstuvwxyz{|}~ ", CENTER, 144);
+
+  myGLCD.setFont(SevenSegNumFont);
+  myGLCD.print("0123456789", CENTER, 190);
+
+  while(1) {};
+}
+
diff --git a/hardware/digistump/sam/libraries/UTFT/hardware/arm/HW_ARM.h b/hardware/digistump/sam/libraries/UTFT/hardware/arm/HW_ARM.h
new file mode 100644
index 0000000..c71a5ff
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/hardware/arm/HW_ARM.h
@@ -0,0 +1,7 @@
+void UTFT::_convert_float(char *buf, double num, int width, byte prec)
+{
+	char format[10];
+	
+	sprintf(format, "%%%i.%if", width, prec);
+	sprintf(buf, format, num);
+}
diff --git a/hardware/digistump/sam/libraries/UTFT/hardware/arm/HW_ARM_defines.h b/hardware/digistump/sam/libraries/UTFT/hardware/arm/HW_ARM_defines.h
new file mode 100644
index 0000000..35dda02
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/hardware/arm/HW_ARM_defines.h
@@ -0,0 +1,26 @@
+// CTE TFT LCD/SD Shield for Arduino Due
+// -------------------------------------
+// Uncomment the following line if you are using this shield
+//#define CTE_DUE_SHIELD 1
+//
+// For this shield: RS=25, WR=26, CS=27, RST=28
+//********************************************************************
+
+// *** Hardwarespecific defines ***
+#define cbi(reg, bitmask) *reg &= ~bitmask
+#define sbi(reg, bitmask) *reg |= bitmask
+#define pulse_high(reg, bitmask) sbi(reg, bitmask); cbi(reg, bitmask);
+#define pulse_low(reg, bitmask) cbi(reg, bitmask); sbi(reg, bitmask);
+
+#define cport(port, data) port &= data
+#define sport(port, data) port |= data
+
+#define swap(type, i, j) {type t = i; i = j; j = t;}
+
+#define fontbyte(x) cfont.font[x]  
+
+#define pgm_read_word(data) *data
+#define pgm_read_byte(data) *data
+#define regtype volatile uint32_t
+#define regsize uint32_t
+#define bitmapdatatype unsigned short*
diff --git a/hardware/digistump/sam/libraries/UTFT/hardware/arm/HW_SAM3X8E.h b/hardware/digistump/sam/libraries/UTFT/hardware/arm/HW_SAM3X8E.h
new file mode 100644
index 0000000..75e9e5b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/hardware/arm/HW_SAM3X8E.h
@@ -0,0 +1,338 @@
+// *** Hardwarespecific functions ***
+void UTFT::_hw_special_init()
+{
+	//REG_PIOA_OWER = 0xFFFFFFFF;
+	//REG_PIOB_OWER = 0xFFFFFFFF;
+	//REG_PIOC_OWER = 0xFFFFFFFF;  
+}
+
+void UTFT::LCD_Writ_Bus(char VH,char VL, byte mode)
+{   
+	switch (mode)
+	{
+	case 1:
+		if (display_serial_mode==SERIAL_4PIN)
+		{
+			if (VH==1)
+				sbi(P_SDA, B_SDA);
+			else
+				cbi(P_SDA, B_SDA);
+			pulse_low(P_SCL, B_SCL);
+		}
+		else
+		{
+			if (VH==1)
+				sbi(P_RS, B_RS);
+			else
+				cbi(P_RS, B_RS);
+		}
+
+		if (VL & 0x80)
+			sbi(P_SDA, B_SDA);
+		else
+			cbi(P_SDA, B_SDA);
+		pulse_low(P_SCL, B_SCL);
+		if (VL & 0x40)
+			sbi(P_SDA, B_SDA);
+		else
+			cbi(P_SDA, B_SDA);
+		pulse_low(P_SCL, B_SCL);
+		if (VL & 0x20)
+			sbi(P_SDA, B_SDA);
+		else
+			cbi(P_SDA, B_SDA);
+		pulse_low(P_SCL, B_SCL);
+		if (VL & 0x10)
+			sbi(P_SDA, B_SDA);
+		else
+			cbi(P_SDA, B_SDA);
+		pulse_low(P_SCL, B_SCL);
+		if (VL & 0x08)
+			sbi(P_SDA, B_SDA);
+		else
+			cbi(P_SDA, B_SDA);
+		pulse_low(P_SCL, B_SCL);
+		if (VL & 0x04)
+			sbi(P_SDA, B_SDA);
+		else
+			cbi(P_SDA, B_SDA);
+		pulse_low(P_SCL, B_SCL);
+		if (VL & 0x02)
+			sbi(P_SDA, B_SDA);
+		else
+			cbi(P_SDA, B_SDA);
+		pulse_low(P_SCL, B_SCL);
+		if (VL & 0x01)
+			sbi(P_SDA, B_SDA);
+		else
+			cbi(P_SDA, B_SDA);
+		pulse_low(P_SCL, B_SCL);
+		break;
+	case 8:
+#ifdef CTE_DUE_SHIELD
+		REG_PIOC_CODR=0xFF000;
+		REG_PIOC_SODR=(VH<<12) & 0xFF000;
+		pulse_low(P_WR, B_WR);
+		REG_PIOC_CODR=0xFF000;
+		REG_PIOC_SODR=(VL<<12) & 0xFF000;
+		pulse_low(P_WR, B_WR);
+#else
+		//Clear port registers
+		REG_PIOA_CODR=0xc000; //PA14,PA15
+		REG_PIOB_CODR=0x4000000; //PB26
+		REG_PIOD_CODR=0x64f; //PD0-3,PD6,PD9-10
+
+		//DB08 on PIN22 -> PIO_PB26
+		REG_PIOB_SODR=(VH<<26) & 0x4000000;
+		//DB09 on PIN23 -> PIO_PA14
+		REG_PIOA_SODR=(VH<<13) & 0x4000;
+		//DB10 on PIN24 -> PIO_PA15
+		REG_PIOA_SODR=(VH<<13) & 0x8000;
+		//DB11 on PIN25 -> PIO_PD0
+		REG_PIOD_SODR=(VH>>3) & 0x01;
+		//DB12 on PIN26 -> PIO_PD1
+		REG_PIOD_SODR=(VH>>3) & 0x02;
+		//DB13 on PIN27 -> PIO_PD2
+		REG_PIOD_SODR=(VH>>3) & 0x04;
+		//DB14 on PIN28 -> PIO_PD3
+		REG_PIOD_SODR=(VH>>3) & 0x08;
+		//DB15 on PIN29 -> PIO_PD6
+		REG_PIOD_SODR=(VH>>1) & 0x40;
+		pulse_low(P_WR, B_WR);
+
+		REG_PIOA_CODR=0xc000; //PA14,PA15
+		REG_PIOB_CODR=0x4000000; //PB26
+		REG_PIOD_CODR=0x64f; //PD0-3,PD6,PD9-10
+		//DB08 on PIN22 -> PIO_PB26
+		REG_PIOB_SODR=(VL<<26) & 0x4000000;
+		//DB09 on PIN23 -> PIO_PA14
+		REG_PIOA_SODR=(VL<<13) & 0x4000;
+		//DB10 on PIN24 -> PIO_PA15
+		REG_PIOA_SODR=(VL<<13) & 0x8000;
+		//DB11 on PIN25 -> PIO_PD0
+		REG_PIOD_SODR=(VL>>3) & 0x01;
+		//DB12 on PIN26 -> PIO_PD1
+		REG_PIOD_SODR=(VL>>3) & 0x02;
+		//DB13 on PIN27 -> PIO_PD2
+		REG_PIOD_SODR=(VL>>3) & 0x04;
+		//DB14 on PIN28 -> PIO_PD3
+		REG_PIOD_SODR=(VL>>3) & 0x08;
+		//DB15 on PIN29 -> PIO_PD6
+		REG_PIOD_SODR=(VL>>1) & 0x40;
+		pulse_low(P_WR, B_WR);
+#endif
+		break;
+	case 16:
+#ifdef CTE_DUE_SHIELD
+        REG_PIOC_CODR=0xFF1FE;
+		REG_PIOC_SODR=(VL<<1) & 0x1FE;
+		REG_PIOC_SODR=(VH<<12) & 0xFF000;
+#else
+		//Clear port registers
+		REG_PIOA_CODR=0xc080; //PA7,PA14,PA15
+		REG_PIOB_CODR=0x4000000; //PB26
+		REG_PIOC_CODR=0x3e; //PC1 - PC5
+		REG_PIOD_CODR=0x64f; //PD0-3,PD6,PD9-10
+                
+		//DB00 on PIN37 -> PIO_PC5
+		REG_PIOC_SODR=(VL<<5) & 0x20;
+		//DB01 on PIN36 -> PIO_PC4
+		REG_PIOC_SODR=(VL<<3) & 0x10;
+		//DB02 on PIN35 -> PIO_PC3
+		REG_PIOC_SODR=(VL<<1) & 0x08;
+		//DB03 on PIN34 -> PIO_PC2
+		REG_PIOC_SODR=(VL>>1) & 0x04;
+		//DB04 on PIN33 -> PIO_PC1
+		REG_PIOC_SODR=(VL>>3) & 0x02;
+		//DB05 on PIN32 -> PIO_PD10
+		REG_PIOD_SODR=(VL<<5) & 0x400;
+		//DB06 on PIN31 -> PIO_PA7
+		REG_PIOA_SODR=(VL<<1) & 0x80;
+		//DB07 on PIN30 -> PIO_PD9
+		REG_PIOD_SODR=(VL<<2) & 0x200;
+		//DB08 on PIN22 -> PIO_PB26
+		REG_PIOB_SODR=(VH<<26) & 0x4000000;
+		//DB09 on PIN23 -> PIO_PA14
+		REG_PIOA_SODR=(VH<<13) & 0x4000;
+		//DB10 on PIN24 -> PIO_PA15
+		REG_PIOA_SODR=(VH<<13) & 0x8000;
+		//DB11 on PIN25 -> PIO_PD0
+		REG_PIOD_SODR=(VH>>3) & 0x01;
+		//DB12 on PIN26 -> PIO_PD1
+		REG_PIOD_SODR=(VH>>3) & 0x02;
+		//DB13 on PIN27 -> PIO_PD2
+		REG_PIOD_SODR=(VH>>3) & 0x04;
+		//DB14 on PIN28 -> PIO_PD3
+		REG_PIOD_SODR=(VH>>3) & 0x08;
+		//DB15 on PIN29 -> PIO_PD6
+		REG_PIOD_SODR=(VH>>1) & 0x40;
+#endif
+		pulse_low(P_WR, B_WR);
+		break;
+	case LATCHED_16:
+		asm("nop");		// Mode is unsupported
+		break;
+	}
+}
+
+void UTFT::_set_direction_registers(byte mode)
+{
+	if (mode!=LATCHED_16)
+	{
+#ifdef CTE_DUE_SHIELD
+		if (mode==16)
+		{
+			REG_PIOC_OER=0x000FF1FE;
+		}
+		else
+			REG_PIOC_OER=0x000FF000;
+#else
+		REG_PIOA_OER=0x0000c000; //PA14,PA15 enable
+		REG_PIOB_OER=0x04000000; //PB26 enable
+		REG_PIOD_OER=0x0000064f; //PD0-3,PD6,PD9-10 enable
+		if (mode==16)
+		{
+			REG_PIOA_OER=0x00000080; //PA7 enable
+			REG_PIOC_OER=0x0000003e; //PC1 - PC5 enable
+		}
+#endif
+	}
+	else
+	{
+		asm("nop");		// Mode is unsupported
+	}
+}
+
+void UTFT::_fast_fill_16(int ch, int cl, long pix)
+{
+	long blocks;
+
+#ifdef CTE_DUE_SHIELD
+    REG_PIOC_CODR=0xFF1FE;
+	REG_PIOC_SODR=(cl<<1) & 0x1FE;
+	REG_PIOC_SODR=(ch<<12) & 0xFF000;
+#else
+	//Clear port registers
+	REG_PIOA_CODR=0xc080; //PA7,PA14,PA15
+	REG_PIOB_CODR=0x4000000; //PB26
+	REG_PIOC_CODR=0x3e; //PC1 - PC5
+	REG_PIOD_CODR=0x64f; //PD0-3,PD6,PD9-10
+                
+	//DB00 on PIN37 -> PIO_PC5
+	REG_PIOC_SODR=(cl<<5) & 0x20;
+	//DB01 on PIN36 -> PIO_PC4
+	REG_PIOC_SODR=(cl<<3) & 0x10;
+	//DB02 on PIN35 -> PIO_PC3
+	REG_PIOC_SODR=(cl<<1) & 0x08;
+	//DB03 on PIN34 -> PIO_PC2
+	REG_PIOC_SODR=(cl>>1) & 0x04;
+	//DB04 on PIN33 -> PIO_PC1
+	REG_PIOC_SODR=(cl>>3) & 0x02;
+	//DB05 on PIN32 -> PIO_PD10
+	REG_PIOD_SODR=(cl<<5) & 0x400;
+	//DB06 on PIN31 -> PIO_PA7
+	REG_PIOA_SODR=(cl<<1) & 0x80;
+	//DB07 on PIN30 -> PIO_PD9
+	REG_PIOD_SODR=(cl<<2) & 0x200;
+	//DB08 on PIN22 -> PIO_PB26
+	REG_PIOB_SODR=(ch<<26) & 0x4000000;
+	//DB09 on PIN23 -> PIO_PA14
+	REG_PIOA_SODR=(ch<<13) & 0x4000;
+	//DB10 on PIN24 -> PIO_PA15
+	REG_PIOA_SODR=(ch<<13) & 0x8000;
+	//DB11 on PIN25 -> PIO_PD0
+	REG_PIOD_SODR=(ch>>3) & 0x01;
+	//DB12 on PIN26 -> PIO_PD1
+	REG_PIOD_SODR=(ch>>3) & 0x02;
+	//DB13 on PIN27 -> PIO_PD2
+	REG_PIOD_SODR=(ch>>3) & 0x04;
+	//DB14 on PIN28 -> PIO_PD3
+	REG_PIOD_SODR=(ch>>3) & 0x08;
+	//DB15 on PIN29 -> PIO_PD6
+	REG_PIOD_SODR=(ch>>1) & 0x40;
+#endif
+
+	blocks = pix/16;
+	for (int i=0; i PIO_PB26
+	REG_PIOB_SODR=(ch<<26) & 0x4000000;
+	//DB09 on PIN23 -> PIO_PA14
+	REG_PIOA_SODR=(ch<<13) & 0x4000;
+	//DB10 on PIN24 -> PIO_PA15
+	REG_PIOA_SODR=(ch<<13) & 0x8000;
+	//DB11 on PIN25 -> PIO_PD0
+	REG_PIOD_SODR=(ch>>3) & 0x01;
+	//DB12 on PIN26 -> PIO_PD1
+	REG_PIOD_SODR=(ch>>3) & 0x02;
+	//DB13 on PIN27 -> PIO_PD2
+	REG_PIOD_SODR=(ch>>3) & 0x04;
+	//DB14 on PIN28 -> PIO_PD3
+	REG_PIOD_SODR=(ch>>3) & 0x08;
+	//DB15 on PIN29 -> PIO_PD6
+	REG_PIOD_SODR=(ch>>1) & 0x40;
+#endif
+
+	blocks = pix/16;
+	for (int i=0; i>3;
+		PORTE &= ~0x3B;
+		PORTE |= (VH & 0x03) + ((VH & 0x0C)<<2) + ((VH & 0x20)>>2);
+		pulse_low(P_WR, B_WR);
+		PORTG &= ~0x20;
+		PORTG |= (VL & 0x10)<<1;
+		PORTH &= ~0x18;
+		PORTH |= (VL & 0xC0)>>3;
+		PORTE &= ~0x3B;
+		PORTE |= (VL & 0x03) + ((VL & 0x0C)<<2) + ((VL & 0x20)>>2);
+		pulse_low(P_WR, B_WR);
+#else
+		PORTA = VH;
+		pulse_low(P_WR, B_WR);
+		PORTA = VL;
+		pulse_low(P_WR, B_WR);
+#endif
+		break;
+	case 16:
+		PORTA = VH;
+		PORTC = VL;
+		pulse_low(P_WR, B_WR);
+		break;
+	case LATCHED_16:
+		PORTG &= ~0x20;	
+		PORTG |= (VH & 0x10)<<1;	
+		PORTH &= ~0x18;	
+		PORTH |= (VH & 0xC0)>>3;	
+		PORTE &= ~0x3B;	
+		PORTE |= (VH & 0x03) + ((VH & 0x0C)<<2) + ((VH & 0x20)>>2);
+		cbi(P_ALE, B_ALE);
+		pulse_high(P_ALE, B_ALE);
+		cbi(P_CS, B_CS);
+		PORTG &= ~0x20;	
+		PORTG |= (VL & 0x10)<<1;	
+		PORTH &= ~0x18;	
+		PORTH |= (VL & 0xC0)>>3;	
+		PORTE &= ~0x3B;	
+		PORTE |= (VL & 0x03) + ((VL & 0x0C)<<2) + ((VL & 0x20)>>2);
+		pulse_low(P_WR, B_WR);
+		sbi(P_CS, B_CS);
+		break;
+	}
+}
+
+void UTFT::_set_direction_registers(byte mode)
+{
+#if defined(USE_UNO_SHIELD_ON_MEGA)
+	DDRH = 0x18;
+	DDRG = 0x20;
+	DDRE = 0x3B;
+#else
+	if (mode!=LATCHED_16)
+	{
+		DDRA = 0xFF;
+		if (mode==16)
+			DDRC = 0xFF;
+	}
+	else
+	{
+		DDRH = 0x18;
+		DDRG = 0x20;
+		DDRE = 0x3B;
+	}
+#endif
+}
+
+void UTFT::_fast_fill_16(int ch, int cl, long pix)
+{
+#if defined(USE_UNO_SHIELD_ON_MEGA)
+	if (ch==cl)
+		_fast_fill_8(ch, pix);
+	else
+	{
+		for (int i=0; i>3;
+			PORTE &= ~0x3B;
+			PORTE |= (ch & 0x03) + ((ch & 0x0C)<<2) + ((ch & 0x20)>>2);
+			pulse_low(P_WR, B_WR);
+			PORTG &= ~0x20;
+			PORTG |= (cl & 0x10)<<1;
+			PORTH &= ~0x18;
+			PORTH |= (cl & 0xC0)>>3;
+			PORTE &= ~0x3B;
+			PORTE |= (cl & 0x03) + ((cl & 0x0C)<<2) + ((cl & 0x20)>>2);
+			pulse_low(P_WR, B_WR);
+		}
+	}
+#else
+	long blocks;
+
+	PORTA = ch;
+	PORTC = cl;
+
+	blocks = pix/16;
+	for (int i=0; i>3;
+	PORTE &= ~0x3B;
+	PORTE |= (ch & 0x03) + ((ch & 0x0C)<<2) + ((ch & 0x20)>>2);
+#else
+	PORTA = ch;
+#endif
+
+	blocks = pix/16;
+	for (int i=0; i>6) & 0x03);
+		PORTB =  VL & 0x3F;
+		pulse_low(P_WR, B_WR);
+		break;
+	case LATCHED_16:
+		PORTD = VH;
+		cbi(P_ALE, B_ALE);
+		pulse_high(P_ALE, B_ALE);
+		cbi(P_CS, B_CS);
+		PORTD =  VL;
+		pulse_low(P_WR, B_WR);
+		sbi(P_CS, B_CS);
+		break;
+	}
+}
+
+void UTFT::_set_direction_registers(byte mode)
+{
+	DDRD = 0xFF;
+	if (mode==16)
+	{
+		DDRB |= 0x3F;
+		DDRC |= 0x03;
+	}
+
+}
+
+void UTFT::_fast_fill_16(int ch, int cl, long pix)
+{
+	long blocks;
+
+	PORTD = ch;
+	cport(PORTC, 0xFC);
+	sport(PORTC, (cl>>6) & 0x03);
+	PORTB =  cl & 0x3F;
+
+	blocks = pix/16;
+	for (int i=0; i>3) + ((VH & 0x04)>>1) + ((VH & 0x03)<<2);
+		PORTE += ((VH & 0x80)>>1);
+		pulse_low(P_WR, B_WR);
+
+		cport(PORTC, 0xBF);
+		cport(PORTD, 0x60);
+		cport(PORTE, 0xBF);
+		PORTC += ((VL & 0x20)<<1);
+		PORTD += ((VL & 0x40)<<1) + (VL & 0x10) + ((VL & 0x08)>>3) + ((VL & 0x04)>>1) + ((VL & 0x03)<<2);
+		PORTE += ((VL & 0x80)>>1);
+		pulse_low(P_WR, B_WR);
+		break;
+	case 16:
+		cport(PORTB, 0x0F);
+		cport(PORTC, 0x3F);
+		cport(PORTD, 0x20);
+		cport(PORTE, 0xBF);
+		cport(PORTF, 0x3F);
+
+		PORTB |= ((VL & 0x0F)<<4);
+		PORTC |= ((VL & 0x20)<<2) + ((VH & 0x20)<<1);
+		PORTD |= ((VH & 0x40)<<1) + (VH & 0x10) + ((VH & 0x08)>>3) + ((VH & 0x04)>>1) + ((VH & 0x03)<<2) + ((VL & 0x10)<<2);
+		PORTE |= ((VH & 0x80)>>1);
+		PORTF |= ((VL & 0x80)>>1) + ((VL & 0x40)<<1);
+
+		pulse_low(P_WR, B_WR);
+		break;
+	case LATCHED_16:
+		cport(PORTC, 0xBF);
+		cport(PORTD, 0x60);
+		cport(PORTE, 0xBF);
+		PORTC += ((VH & 0x20)<<1);
+		PORTD += ((VH & 0x40)<<1) + (VH & 0x10) + ((VH & 0x08)>>3) + ((VH & 0x04)>>1) + ((VH & 0x03)<<2);
+		PORTE += ((VH & 0x80)>>1);
+		cbi(P_ALE, B_ALE);
+		pulse_high(P_ALE, B_ALE);
+		cbi(P_CS, B_CS);
+		cport(PORTC, 0xBF);
+		cport(PORTD, 0x60);
+		cport(PORTE, 0xBF);
+		PORTC += ((VL & 0x20)<<1);
+		PORTD += ((VL & 0x40)<<1) + (VL & 0x10) + ((VL & 0x08)>>3) + ((VL & 0x04)>>1) + ((VL & 0x03)<<2);
+		PORTE += ((VL & 0x80)>>1);
+		pulse_low(P_WR, B_WR);
+		sbi(P_CS, B_CS);
+		break;
+	}
+}
+
+void UTFT::_set_direction_registers(byte mode)
+{
+	switch (mode)
+	{
+	case 8:
+	case LATCHED_16:
+		DDRC |= 0x40;
+		DDRD |= 0x9F;
+		DDRE |= 0x40;
+		break;
+	case 16:
+		DDRB |= 0xF0;
+		DDRC |= 0xC0;
+		DDRD |= 0xDF;
+		DDRE |= 0x40;
+		DDRF |= 0xC0;
+		break;
+	}
+}
+
+void UTFT::_fast_fill_16(int ch, int cl, long pix)
+{
+	long blocks;
+
+	cport(PORTB, 0x0F);
+	cport(PORTC, 0x3F);
+	cport(PORTD, 0x20);
+	cport(PORTE, 0xBF);
+	cport(PORTF, 0x3F);
+
+	PORTB |= ((cl & 0x0F)<<4);
+	PORTC |= ((cl & 0x20)<<2) + ((ch & 0x20)<<1);
+	PORTD |= ((ch & 0x40)<<1) + (ch & 0x10) + ((ch & 0x08)>>3) + ((ch & 0x04)>>1) + ((ch & 0x03)<<2) + ((cl & 0x10)<<2);
+	PORTE |= ((ch & 0x80)>>1);
+	PORTF |= ((cl & 0x80)>>1) + ((cl & 0x40)<<1);
+
+	blocks = pix/16;
+	for (int i=0; i>3) + ((ch & 0x04)>>1) + ((ch & 0x03)<<2);
+	PORTE |= ((ch & 0x80)>>1);
+
+	blocks = pix/16;
+	for (int i=0; i>8);
+  	LCD_Write_DATA(x1);
+  	LCD_Write_DATA(x2>>8);
+  	LCD_Write_DATA(x2);
+	LCD_Write_COM(0x2b); 
+  	LCD_Write_DATA(y1>>8);
+  	LCD_Write_DATA(y1);
+  	LCD_Write_DATA(y2>>8);
+  	LCD_Write_DATA(y2);
+	LCD_Write_COM(0x2c); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/hx8347a/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/hx8347a/initlcd.h
new file mode 100644
index 0000000..76bf08e
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/hx8347a/initlcd.h
@@ -0,0 +1,88 @@
+case HX8347A:
+	LCD_Write_COM_DATA(0x46,0x00A4);
+	LCD_Write_COM_DATA(0x47,0x0053);
+	LCD_Write_COM_DATA(0x48,0x0000);
+	LCD_Write_COM_DATA(0x49,0x0044);
+	LCD_Write_COM_DATA(0x4a,0x0004);
+	LCD_Write_COM_DATA(0x4b,0x0067);
+	LCD_Write_COM_DATA(0x4c,0x0033);
+	LCD_Write_COM_DATA(0x4d,0x0077);
+	LCD_Write_COM_DATA(0x4e,0x0012);
+	LCD_Write_COM_DATA(0x4f,0x004C);
+	LCD_Write_COM_DATA(0x50,0x0046);
+	LCD_Write_COM_DATA(0x51,0x0044);
+
+	//240x320 window setting
+	LCD_Write_COM_DATA(0x02,0x0000); // Column address start2
+	LCD_Write_COM_DATA(0x03,0x0000); // Column address start1
+	LCD_Write_COM_DATA(0x04,0x0000); // Column address end2
+	LCD_Write_COM_DATA(0x05,0x00ef); // Column address end1
+	LCD_Write_COM_DATA(0x06,0x0000); // Row address start2
+	LCD_Write_COM_DATA(0x07,0x0000); // Row address start1
+	LCD_Write_COM_DATA(0x08,0x0001); // Row address end2
+	LCD_Write_COM_DATA(0x09,0x003f); // Row address end1
+
+	// Display Setting
+	LCD_Write_COM_DATA(0x01,0x0006); // IDMON=0, INVON=1, NORON=1, PTLON=0
+	LCD_Write_COM_DATA(0x16,0x00C8); // MY=0, MX=0, MV=0, ML=1, BGR=0, TEON=0   0048
+	LCD_Write_COM_DATA(0x23,0x0095); // N_DC=1001 0101
+	LCD_Write_COM_DATA(0x24,0x0095); // PI_DC=1001 0101
+	LCD_Write_COM_DATA(0x25,0x00FF); // I_DC=1111 1111
+
+	LCD_Write_COM_DATA(0x27,0x0002); // N_BP=0000 0010
+	LCD_Write_COM_DATA(0x28,0x0002); // N_FP=0000 0010
+	LCD_Write_COM_DATA(0x29,0x0002); // PI_BP=0000 0010
+	LCD_Write_COM_DATA(0x2a,0x0002); // PI_FP=0000 0010
+	LCD_Write_COM_DATA(0x2C,0x0002); // I_BP=0000 0010
+	LCD_Write_COM_DATA(0x2d,0x0002); // I_FP=0000 0010
+
+	LCD_Write_COM_DATA(0x3a,0x0001); // N_RTN=0000, N_NW=001    0001
+	LCD_Write_COM_DATA(0x3b,0x0000); // P_RTN=0000, P_NW=001
+	LCD_Write_COM_DATA(0x3c,0x00f0); // I_RTN=1111, I_NW=000
+	LCD_Write_COM_DATA(0x3d,0x0000); // DIV=00
+	delay(1);
+	LCD_Write_COM_DATA(0x35,0x0038); // EQS=38h
+	LCD_Write_COM_DATA(0x36,0x0078); // EQP=78h
+	LCD_Write_COM_DATA(0x3E,0x0038); // SON=38h
+	LCD_Write_COM_DATA(0x40,0x000F); // GDON=0Fh
+	LCD_Write_COM_DATA(0x41,0x00F0); // GDOFF
+
+	// Power Supply Setting
+	LCD_Write_COM_DATA(0x19,0x0049); // CADJ=0100, CUADJ=100, OSD_EN=1 ,60Hz
+	LCD_Write_COM_DATA(0x93,0x000F); // RADJ=1111, 100%
+	delay(1);
+	LCD_Write_COM_DATA(0x20,0x0040); // BT=0100
+	LCD_Write_COM_DATA(0x1D,0x0007); // VC1=111   0007
+	LCD_Write_COM_DATA(0x1E,0x0000); // VC3=000
+	LCD_Write_COM_DATA(0x1F,0x0004); // VRH=0011
+
+	//VCOM SETTING
+	LCD_Write_COM_DATA(0x44,0x004D); // VCM=101 0000  4D
+	LCD_Write_COM_DATA(0x45,0x000E); // VDV=1 0001   0011
+	delay(1);
+	LCD_Write_COM_DATA(0x1C,0x0004); // AP=100
+	delay(2);
+
+	LCD_Write_COM_DATA(0x1B,0x0018); // GASENB=0, PON=0, DK=1, XDK=0, VLCD_TRI=0, STB=0
+	delay(1);
+	LCD_Write_COM_DATA(0x1B,0x0010); // GASENB=0, PON=1, DK=0, XDK=0, VLCD_TRI=0, STB=0
+	delay(1);
+	LCD_Write_COM_DATA(0x43,0x0080); //set VCOMG=1
+	delay(2);
+
+	// Display ON Setting
+	LCD_Write_COM_DATA(0x90,0x007F); // SAP=0111 1111
+	LCD_Write_COM_DATA(0x26,0x0004); //GON=0, DTE=0, D=01
+	delay(1);
+	LCD_Write_COM_DATA(0x26,0x0024); //GON=1, DTE=0, D=01
+	LCD_Write_COM_DATA(0x26,0x002C); //GON=1, DTE=0, D=11
+	delay(1);
+	LCD_Write_COM_DATA(0x26,0x003C); //GON=1, DTE=1, D=11
+
+	// INTERNAL REGISTER SETTING
+	LCD_Write_COM_DATA(0x57,0x0002); // TEST_Mode=1: into TEST mode
+	LCD_Write_COM_DATA(0x95,0x0001); // SET DISPLAY CLOCK AND PUMPING CLOCK TO SYNCHRONIZE
+	LCD_Write_COM_DATA(0x57,0x0000); // TEST_Mode=0: exit TEST mode
+	//LCD_Write_COM_DATA(0x21,0x0000);
+	LCD_Write_COM(0x22);   
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/hx8347a/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/hx8347a/setxy.h
new file mode 100644
index 0000000..bf82d6b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/hx8347a/setxy.h
@@ -0,0 +1,11 @@
+case HX8347A:
+	LCD_Write_COM_DATA(0x02,x1>>8);
+	LCD_Write_COM_DATA(0x03,x1);
+	LCD_Write_COM_DATA(0x04,x2>>8);
+	LCD_Write_COM_DATA(0x05,x2);
+	LCD_Write_COM_DATA(0x06,y1>>8);
+	LCD_Write_COM_DATA(0x07,y1);
+	LCD_Write_COM_DATA(0x08,y2>>8);
+	LCD_Write_COM_DATA(0x09,y2);
+	LCD_Write_COM(0x22);      
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/hx8352a/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/hx8352a/initlcd.h
new file mode 100644
index 0000000..5645bbe
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/hx8352a/initlcd.h
@@ -0,0 +1,131 @@
+case HX8352A:
+	LCD_Write_COM(0x83);           
+	LCD_Write_DATA(0x02);  //TESTM=1 
+             
+	LCD_Write_COM(0x85);  
+	LCD_Write_DATA(0x03);  //VDC_SEL=011
+	LCD_Write_COM(0x8B);  
+	LCD_Write_DATA(0x01);
+	LCD_Write_COM(0x8C);  
+	LCD_Write_DATA(0x93); //STBA[7]=1,STBA[5:4]=01,STBA[1:0]=11
+        
+	LCD_Write_COM(0x91);  
+	LCD_Write_DATA(0x01); //DCDC_SYNC=1
+        
+	LCD_Write_COM(0x83);  
+	LCD_Write_DATA(0x00); //TESTM=0
+	//Gamma Setting
+
+	LCD_Write_COM(0x3E);  
+	LCD_Write_DATA(0xB0);
+	LCD_Write_COM(0x3F);  
+	LCD_Write_DATA(0x03);
+	LCD_Write_COM(0x40);  
+	LCD_Write_DATA(0x10);
+	LCD_Write_COM(0x41);  
+	LCD_Write_DATA(0x56);
+	LCD_Write_COM(0x42);  
+	LCD_Write_DATA(0x13);
+	LCD_Write_COM(0x43);  
+	LCD_Write_DATA(0x46);
+	LCD_Write_COM(0x44);  
+	LCD_Write_DATA(0x23);
+	LCD_Write_COM(0x45);  
+	LCD_Write_DATA(0x76);
+	LCD_Write_COM(0x46);  
+	LCD_Write_DATA(0x00);
+	LCD_Write_COM(0x47);  
+	LCD_Write_DATA(0x5E);
+	LCD_Write_COM(0x48);  
+	LCD_Write_DATA(0x4F);
+	LCD_Write_COM(0x49);  
+	LCD_Write_DATA(0x40);	
+	//**********Power On sequence************
+        
+	LCD_Write_COM(0x17);  
+	LCD_Write_DATA(0x91);
+       
+	LCD_Write_COM(0x2B);  
+	LCD_Write_DATA(0xF9);
+	delay(10);
+        
+	LCD_Write_COM(0x1B);  
+	LCD_Write_DATA(0x14);
+        
+	LCD_Write_COM(0x1A);  
+	LCD_Write_DATA(0x11);
+              
+	LCD_Write_COM(0x1C);  
+	LCD_Write_DATA(0x06);
+        
+	LCD_Write_COM(0x1F);  
+	LCD_Write_DATA(0x42);
+	delay(20);
+        
+	LCD_Write_COM(0x19);  
+	LCD_Write_DATA(0x0A);
+     
+	LCD_Write_COM(0x19);  
+	LCD_Write_DATA(0x1A);
+	delay(40);
+        
+        
+	LCD_Write_COM(0x19);  
+	LCD_Write_DATA(0x12);
+	delay(40);
+        
+	LCD_Write_COM(0x1E);  
+	LCD_Write_DATA(0x27);
+	delay(100);	   
+        
+        
+	//**********DISPLAY ON SETTING***********
+        
+	LCD_Write_COM(0x24);  
+	LCD_Write_DATA(0x60);
+        
+	LCD_Write_COM(0x3D);  
+	LCD_Write_DATA(0x40);
+        
+	LCD_Write_COM(0x34);  
+	LCD_Write_DATA(0x38);
+        
+	LCD_Write_COM(0x35);  
+	LCD_Write_DATA(0x38);
+        
+	LCD_Write_COM(0x24);  
+	LCD_Write_DATA(0x38);
+	delay(40);
+        
+	LCD_Write_COM(0x24);  
+	LCD_Write_DATA(0x3C);
+        
+	LCD_Write_COM(0x16);  
+	LCD_Write_DATA(0x1C);
+        
+	LCD_Write_COM(0x01);  
+	LCD_Write_DATA(0x06);
+        
+	LCD_Write_COM(0x55);  
+	LCD_Write_DATA(0x00); 
+
+	LCD_Write_COM(0x02);           
+	LCD_Write_DATA(0x00);
+	LCD_Write_COM(0x03);           
+	LCD_Write_DATA(0x00);
+	LCD_Write_COM(0x04);           
+	LCD_Write_DATA(0x00);
+	LCD_Write_COM(0x05);           
+	LCD_Write_DATA(0xef);
+        
+	LCD_Write_COM(0x06);           
+	LCD_Write_DATA(0x00);
+	LCD_Write_COM(0x07);           
+	LCD_Write_DATA(0x00);
+	LCD_Write_COM(0x08);           
+	LCD_Write_DATA(0x01);
+	LCD_Write_COM(0x09);           
+	LCD_Write_DATA(0x8f);
+
+	LCD_Write_COM(0x22);
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/hx8352a/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/hx8352a/setxy.h
new file mode 100644
index 0000000..225fe65
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/hx8352a/setxy.h
@@ -0,0 +1,11 @@
+case HX8352A:
+	LCD_Write_COM_DATA(0x02,x1>>8);
+	LCD_Write_COM_DATA(0x03,x1);
+	LCD_Write_COM_DATA(0x04,x2>>8);
+	LCD_Write_COM_DATA(0x05,x2);
+	LCD_Write_COM_DATA(0x06,y1>>8);
+	LCD_Write_COM_DATA(0x07,y1);
+	LCD_Write_COM_DATA(0x08,y2>>8);
+	LCD_Write_COM_DATA(0x09,y2);
+	LCD_Write_COM(0x22);      
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9320/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9320/initlcd.h
new file mode 100644
index 0000000..a49f118
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9320/initlcd.h
@@ -0,0 +1,67 @@
+case ILI9320_8:
+case ILI9320_16:
+	LCD_Write_COM_DATA(0xe5, 0x8000);        
+	LCD_Write_COM_DATA(0x00, 0x0001);        
+	LCD_Write_COM_DATA(0x01, 0x0100);
+	LCD_Write_COM_DATA(0x02, 0x0700);
+	LCD_Write_COM_DATA(0x03, 0x1030);
+	LCD_Write_COM_DATA(0x04, 0x0000);
+	LCD_Write_COM_DATA(0x08, 0x0202);        
+	LCD_Write_COM_DATA(0x09, 0x0000);        
+	LCD_Write_COM_DATA(0x0A, 0x0000);
+	LCD_Write_COM_DATA(0x0C, 0x0000);        
+	LCD_Write_COM_DATA(0x0D, 0x0000);        
+	LCD_Write_COM_DATA(0x0F, 0x0000);        
+	//-----Power On sequence-----------------------        
+	LCD_Write_COM_DATA(0x10, 0x0000);        
+	LCD_Write_COM_DATA(0x11, 0x0007);        
+	LCD_Write_COM_DATA(0x12, 0x0000);        
+	LCD_Write_COM_DATA(0x13, 0x0000);        
+	delay(50);
+	LCD_Write_COM_DATA(0x10, 0x17B0);        
+	LCD_Write_COM_DATA(0x11, 0x0007);        
+	delay(10);
+	LCD_Write_COM_DATA(0x12, 0x013A);        
+	delay(10);
+	LCD_Write_COM_DATA(0x13, 0x1A00);        
+	LCD_Write_COM_DATA(0x29, 0x000c);                
+	delay(10);
+	//-----Gamma control-----------------------        
+	LCD_Write_COM_DATA(0x30, 0x0000);        
+	LCD_Write_COM_DATA(0x31, 0x0505);        
+	LCD_Write_COM_DATA(0x32, 0x0004);        
+	LCD_Write_COM_DATA(0x35, 0x0006);        
+	LCD_Write_COM_DATA(0x36, 0x0707);        
+	LCD_Write_COM_DATA(0x37, 0x0105);        
+	LCD_Write_COM_DATA(0x38, 0x0002);        
+	LCD_Write_COM_DATA(0x39, 0x0707);        
+	LCD_Write_COM_DATA(0x3C, 0x0704);        
+	LCD_Write_COM_DATA(0x3D, 0x0807);        
+	//-----Set RAM area-----------------------        
+	LCD_Write_COM_DATA(0x50, 0x0000);
+	LCD_Write_COM_DATA(0x51, 0x00EF);
+	LCD_Write_COM_DATA(0x52, 0x0000);
+	LCD_Write_COM_DATA(0x53, 0x013F);
+	LCD_Write_COM_DATA(0x60, 0x2700);
+	LCD_Write_COM_DATA(0x61, 0x0001);
+	LCD_Write_COM_DATA(0x6A, 0x0000);
+	LCD_Write_COM_DATA(0x21, 0x0000);        
+	LCD_Write_COM_DATA(0x20, 0x0000);        
+	//-----Partial Display Control------------        
+	LCD_Write_COM_DATA(0x80, 0x0000);        
+	LCD_Write_COM_DATA(0x81, 0x0000);
+	LCD_Write_COM_DATA(0x82, 0x0000);
+	LCD_Write_COM_DATA(0x83, 0x0000);
+	LCD_Write_COM_DATA(0x84, 0x0000);        
+	LCD_Write_COM_DATA(0x85, 0x0000);
+	//-----Panel Control----------------------
+	LCD_Write_COM_DATA(0x90, 0x0010);        
+	LCD_Write_COM_DATA(0x92, 0x0000);
+	LCD_Write_COM_DATA(0x93, 0x0003);
+	LCD_Write_COM_DATA(0x95, 0x0110);
+	LCD_Write_COM_DATA(0x97, 0x0000);        
+	LCD_Write_COM_DATA(0x98, 0x0000);
+	//-----Display on-----------------------        
+	LCD_Write_COM_DATA(0x07, 0x0173);        
+	delay(50);
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9320/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9320/setxy.h
new file mode 100644
index 0000000..d54564f
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9320/setxy.h
@@ -0,0 +1,10 @@
+case ILI9320_8:
+case ILI9320_16:
+	LCD_Write_COM_DATA(0x20,x1);
+	LCD_Write_COM_DATA(0x21,y1);
+	LCD_Write_COM_DATA(0x50,x1);
+	LCD_Write_COM_DATA(0x52,y1);
+	LCD_Write_COM_DATA(0x51,x2);
+	LCD_Write_COM_DATA(0x53,y2);
+	LCD_Write_COM(0x22); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325c/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325c/initlcd.h
new file mode 100644
index 0000000..23fba46
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325c/initlcd.h
@@ -0,0 +1,61 @@
+case ILI9325C:
+	LCD_Write_COM_DATA(0xE5, 0x78F0); // set SRAM internal timing
+	LCD_Write_COM_DATA(0x01, 0x0100); // set Driver Output Control  
+	LCD_Write_COM_DATA(0x02, 0x0700); // set 1 line inversion  
+	LCD_Write_COM_DATA(0x03, 0x1030); // set GRAM write direction and BGR=1.  
+	LCD_Write_COM_DATA(0x04, 0x0000); // Resize register  
+	LCD_Write_COM_DATA(0x08, 0x0207); // set the back porch and front porch  
+	LCD_Write_COM_DATA(0x09, 0x0000); // set non-display area refresh cycle ISC[3:0]  
+	LCD_Write_COM_DATA(0x0A, 0x0000); // FMARK function  
+	LCD_Write_COM_DATA(0x0C, 0x0000); // RGB interface setting  
+	LCD_Write_COM_DATA(0x0D, 0x0000); // Frame marker Position  
+	LCD_Write_COM_DATA(0x0F, 0x0000); // RGB interface polarity  
+	//*************Power On sequence ****************//  
+	LCD_Write_COM_DATA(0x10, 0x0000); // SAP, BT[3:0], AP, DSTB, SLP, STB  
+	LCD_Write_COM_DATA(0x11, 0x0007); // DC1[2:0], DC0[2:0], VC[2:0]  
+	LCD_Write_COM_DATA(0x12, 0x0000); // VREG1OUT voltage  
+	LCD_Write_COM_DATA(0x13, 0x0000); // VDV[4:0] for VCOM amplitude  
+	LCD_Write_COM_DATA(0x07, 0x0001);  
+	delay(200); // Dis-charge capacitor power voltage  
+	LCD_Write_COM_DATA(0x10, 0x1090); // SAP, BT[3:0], AP, DSTB, SLP, STB  
+	LCD_Write_COM_DATA(0x11, 0x0227); // Set DC1[2:0], DC0[2:0], VC[2:0]  
+	delay(50); // Delay 50ms  
+	LCD_Write_COM_DATA(0x12, 0x001F); // 0012  
+	delay(50); // Delay 50ms  
+	LCD_Write_COM_DATA(0x13, 0x1500); // VDV[4:0] for VCOM amplitude  
+	LCD_Write_COM_DATA(0x29, 0x0027); // 04  VCM[5:0] for VCOMH  
+	LCD_Write_COM_DATA(0x2B, 0x000D); // Set Frame Rate  
+	delay(50); // Delay 50ms  
+	LCD_Write_COM_DATA(0x20, 0x0000); // GRAM horizontal Address  
+	LCD_Write_COM_DATA(0x21, 0x0000); // GRAM Vertical Address  
+	// ----------- Adjust the Gamma Curve ----------//  
+	LCD_Write_COM_DATA(0x30, 0x0000);  
+	LCD_Write_COM_DATA(0x31, 0x0707);  
+	LCD_Write_COM_DATA(0x32, 0x0307);  
+	LCD_Write_COM_DATA(0x35, 0x0200);  
+	LCD_Write_COM_DATA(0x36, 0x0008);  
+	LCD_Write_COM_DATA(0x37, 0x0004);  
+	LCD_Write_COM_DATA(0x38, 0x0000);  
+	LCD_Write_COM_DATA(0x39, 0x0707);  
+	LCD_Write_COM_DATA(0x3C, 0x0002);  
+	LCD_Write_COM_DATA(0x3D, 0x1D04);  
+	//------------------ Set GRAM area ---------------//  
+	LCD_Write_COM_DATA(0x50, 0x0000); // Horizontal GRAM Start Address  
+	LCD_Write_COM_DATA(0x51, 0x00EF); // Horizontal GRAM End Address  
+	LCD_Write_COM_DATA(0x52, 0x0000); // Vertical GRAM Start Address  
+	LCD_Write_COM_DATA(0x53, 0x013F); // Vertical GRAM Start Address  
+	LCD_Write_COM_DATA(0x60, 0xA700); // Gate Scan Line  
+	LCD_Write_COM_DATA(0x61, 0x0001); // NDL,VLE, REV   
+	LCD_Write_COM_DATA(0x6A, 0x0000); // set scrolling line  
+	//-------------- Partial Display Control ---------//  
+	LCD_Write_COM_DATA(0x80, 0x0000);  
+	LCD_Write_COM_DATA(0x81, 0x0000);  
+	LCD_Write_COM_DATA(0x82, 0x0000);  
+	LCD_Write_COM_DATA(0x83, 0x0000);  
+	LCD_Write_COM_DATA(0x84, 0x0000);  
+	LCD_Write_COM_DATA(0x85, 0x0000);  
+	//-------------- Panel Control -------------------//  
+	LCD_Write_COM_DATA(0x90, 0x0010);  
+	LCD_Write_COM_DATA(0x92, 0x0600);  
+	LCD_Write_COM_DATA(0x07, 0x0133); // 262K color and display ON        
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325c/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325c/setxy.h
new file mode 100644
index 0000000..6e7428d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325c/setxy.h
@@ -0,0 +1,9 @@
+case ILI9325C:
+	LCD_Write_COM_DATA(0x20,x1);
+	LCD_Write_COM_DATA(0x21,y1);
+	LCD_Write_COM_DATA(0x50,x1);
+	LCD_Write_COM_DATA(0x52,y1);
+	LCD_Write_COM_DATA(0x51,x2);
+	LCD_Write_COM_DATA(0x53,y2);
+	LCD_Write_COM(0x22); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325d/alt/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325d/alt/initlcd.h
new file mode 100644
index 0000000..fa52c8d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325d/alt/initlcd.h
@@ -0,0 +1,61 @@
+case ILI9325D_16ALT:
+	LCD_Write_COM_DATA(0xE5, 0x78F0); // set SRAM internal timing
+	LCD_Write_COM_DATA(0x01, 0x0100); // set Driver Output Control  
+	LCD_Write_COM_DATA(0x02, 0x0700); // set 1 line inversion  
+	LCD_Write_COM_DATA(0x03, 0x1030); // set GRAM write direction and BGR=1.  
+	LCD_Write_COM_DATA(0x04, 0x0000); // Resize register  
+	LCD_Write_COM_DATA(0x08, 0x0207); // set the back porch and front porch  
+	LCD_Write_COM_DATA(0x09, 0x0000); // set non-display area refresh cycle ISC[3:0]  
+	LCD_Write_COM_DATA(0x0A, 0x0000); // FMARK function  
+	LCD_Write_COM_DATA(0x0C, 0x0000); // RGB interface setting  
+	LCD_Write_COM_DATA(0x0D, 0x0000); // Frame marker Position  
+	LCD_Write_COM_DATA(0x0F, 0x0000); // RGB interface polarity  
+	//*************Power On sequence ****************//  
+	LCD_Write_COM_DATA(0x10, 0x0000); // SAP, BT[3:0], AP, DSTB, SLP, STB  
+	LCD_Write_COM_DATA(0x11, 0x0007); // DC1[2:0], DC0[2:0], VC[2:0]  
+	LCD_Write_COM_DATA(0x12, 0x0000); // VREG1OUT voltage  
+	LCD_Write_COM_DATA(0x13, 0x0000); // VDV[4:0] for VCOM amplitude  
+	LCD_Write_COM_DATA(0x07, 0x0001);  
+	delay(200); // Dis-charge capacitor power voltage  
+	LCD_Write_COM_DATA(0x10, 0x1590); // SAP, BT[3:0], AP, DSTB, SLP, STB  
+	LCD_Write_COM_DATA(0x11, 0x0227); // Set DC1[2:0], DC0[2:0], VC[2:0]  
+	delay(50); // Delay 50ms  
+	LCD_Write_COM_DATA(0x12, 0x009C); // 0012  
+	delay(50); // Delay 50ms  
+	LCD_Write_COM_DATA(0x13, 0x1900); // VDV[4:0] for VCOM amplitude  
+	LCD_Write_COM_DATA(0x29, 0x0023); // 04  VCM[5:0] for VCOMH  
+	LCD_Write_COM_DATA(0x2B, 0x000E); // Set Frame Rate  
+	delay(50); // Delay 50ms  
+	LCD_Write_COM_DATA(0x20, 0x0000); // GRAM horizontal Address  
+	LCD_Write_COM_DATA(0x21, 0x0000); // GRAM Vertical Address  
+	// ----------- Adjust the Gamma Curve ----------//  
+	LCD_Write_COM_DATA(0x30, 0x0000);  
+	LCD_Write_COM_DATA(0x31, 0x0404);  
+	LCD_Write_COM_DATA(0x32, 0x0003);  
+	LCD_Write_COM_DATA(0x35, 0x0405);  
+	LCD_Write_COM_DATA(0x36, 0x0808);  
+	LCD_Write_COM_DATA(0x37, 0x0407);  
+	LCD_Write_COM_DATA(0x38, 0x0303);  
+	LCD_Write_COM_DATA(0x39, 0x0707);  
+	LCD_Write_COM_DATA(0x3C, 0x0504);  
+	LCD_Write_COM_DATA(0x3D, 0x0808);  
+	//------------------ Set GRAM area ---------------//  
+	LCD_Write_COM_DATA(0x50, 0x0000); // Horizontal GRAM Start Address  
+	LCD_Write_COM_DATA(0x51, 0x00EF); // Horizontal GRAM End Address  
+	LCD_Write_COM_DATA(0x52, 0x0000); // Vertical GRAM Start Address  
+	LCD_Write_COM_DATA(0x53, 0x013F); // Vertical GRAM Start Address  
+	LCD_Write_COM_DATA(0x60, 0xA700); // Gate Scan Line  
+	LCD_Write_COM_DATA(0x61, 0x0001); // NDL,VLE, REV   
+	LCD_Write_COM_DATA(0x6A, 0x0000); // set scrolling line  
+	//-------------- Partial Display Control ---------//  
+	LCD_Write_COM_DATA(0x80, 0x0000);  
+	LCD_Write_COM_DATA(0x81, 0x0000);  
+	LCD_Write_COM_DATA(0x82, 0x0000);  
+	LCD_Write_COM_DATA(0x83, 0x0000);  
+	LCD_Write_COM_DATA(0x84, 0x0000);  
+	LCD_Write_COM_DATA(0x85, 0x0000);  
+	//-------------- Panel Control -------------------//  
+	LCD_Write_COM_DATA(0x90, 0x0010);  
+	LCD_Write_COM_DATA(0x92, 0x0000);  
+	LCD_Write_COM_DATA(0x07, 0x0133); // 262K color and display ON        
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325d/alt/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325d/alt/setxy.h
new file mode 100644
index 0000000..95361e0
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325d/alt/setxy.h
@@ -0,0 +1,9 @@
+case ILI9325D_16ALT:
+	LCD_Write_COM_DATA(0x20,x1);
+	LCD_Write_COM_DATA(0x21,y1);
+	LCD_Write_COM_DATA(0x50,x1);
+	LCD_Write_COM_DATA(0x52,y1);
+	LCD_Write_COM_DATA(0x51,x2);
+	LCD_Write_COM_DATA(0x53,y2);
+	LCD_Write_COM(0x22); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325d/default/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325d/default/initlcd.h
new file mode 100644
index 0000000..6ecb6e2
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325d/default/initlcd.h
@@ -0,0 +1,62 @@
+case ILI9325D_8:
+case ILI9325D_16:
+	LCD_Write_COM_DATA(0xE5, 0x78F0); // set SRAM internal timing
+	LCD_Write_COM_DATA(0x01, 0x0100); // set Driver Output Control  
+	LCD_Write_COM_DATA(0x02, 0x0200); // set 1 line inversion  
+	LCD_Write_COM_DATA(0x03, 0x1030); // set GRAM write direction and BGR=1.  
+	LCD_Write_COM_DATA(0x04, 0x0000); // Resize register  
+	LCD_Write_COM_DATA(0x08, 0x0207); // set the back porch and front porch  
+	LCD_Write_COM_DATA(0x09, 0x0000); // set non-display area refresh cycle ISC[3:0]  
+	LCD_Write_COM_DATA(0x0A, 0x0000); // FMARK function  
+	LCD_Write_COM_DATA(0x0C, 0x0000); // RGB interface setting  
+	LCD_Write_COM_DATA(0x0D, 0x0000); // Frame marker Position  
+	LCD_Write_COM_DATA(0x0F, 0x0000); // RGB interface polarity  
+	//*************Power On sequence ****************//  
+	LCD_Write_COM_DATA(0x10, 0x0000); // SAP, BT[3:0], AP, DSTB, SLP, STB  
+	LCD_Write_COM_DATA(0x11, 0x0007); // DC1[2:0], DC0[2:0], VC[2:0]  
+	LCD_Write_COM_DATA(0x12, 0x0000); // VREG1OUT voltage  
+	LCD_Write_COM_DATA(0x13, 0x0000); // VDV[4:0] for VCOM amplitude  
+	LCD_Write_COM_DATA(0x07, 0x0001);  
+	delay(200); // Dis-charge capacitor power voltage  
+	LCD_Write_COM_DATA(0x10, 0x1690); // SAP, BT[3:0], AP, DSTB, SLP, STB  
+	LCD_Write_COM_DATA(0x11, 0x0227); // Set DC1[2:0], DC0[2:0], VC[2:0]  
+	delay(50); // Delay 50ms  
+	LCD_Write_COM_DATA(0x12, 0x000D); // 0012  
+	delay(50); // Delay 50ms  
+	LCD_Write_COM_DATA(0x13, 0x1200); // VDV[4:0] for VCOM amplitude  
+	LCD_Write_COM_DATA(0x29, 0x000A); // 04  VCM[5:0] for VCOMH  
+	LCD_Write_COM_DATA(0x2B, 0x000D); // Set Frame Rate  
+	delay(50); // Delay 50ms  
+	LCD_Write_COM_DATA(0x20, 0x0000); // GRAM horizontal Address  
+	LCD_Write_COM_DATA(0x21, 0x0000); // GRAM Vertical Address  
+	// ----------- Adjust the Gamma Curve ----------//  
+	LCD_Write_COM_DATA(0x30, 0x0000);  
+	LCD_Write_COM_DATA(0x31, 0x0404);  
+	LCD_Write_COM_DATA(0x32, 0x0003);  
+	LCD_Write_COM_DATA(0x35, 0x0405);  
+	LCD_Write_COM_DATA(0x36, 0x0808);  
+	LCD_Write_COM_DATA(0x37, 0x0407);  
+	LCD_Write_COM_DATA(0x38, 0x0303);  
+	LCD_Write_COM_DATA(0x39, 0x0707);  
+	LCD_Write_COM_DATA(0x3C, 0x0504);  
+	LCD_Write_COM_DATA(0x3D, 0x0808);  
+	//------------------ Set GRAM area ---------------//  
+	LCD_Write_COM_DATA(0x50, 0x0000); // Horizontal GRAM Start Address  
+	LCD_Write_COM_DATA(0x51, 0x00EF); // Horizontal GRAM End Address  
+	LCD_Write_COM_DATA(0x52, 0x0000); // Vertical GRAM Start Address  
+	LCD_Write_COM_DATA(0x53, 0x013F); // Vertical GRAM Start Address  
+	LCD_Write_COM_DATA(0x60, 0xA700); // Gate Scan Line  
+	LCD_Write_COM_DATA(0x61, 0x0001); // NDL,VLE, REV   
+	LCD_Write_COM_DATA(0x6A, 0x0000); // set scrolling line  
+	//-------------- Partial Display Control ---------//  
+	LCD_Write_COM_DATA(0x80, 0x0000);  
+	LCD_Write_COM_DATA(0x81, 0x0000);  
+	LCD_Write_COM_DATA(0x82, 0x0000);  
+	LCD_Write_COM_DATA(0x83, 0x0000);  
+	LCD_Write_COM_DATA(0x84, 0x0000);  
+	LCD_Write_COM_DATA(0x85, 0x0000);  
+	//-------------- Panel Control -------------------//  
+	LCD_Write_COM_DATA(0x90, 0x0010);  
+	LCD_Write_COM_DATA(0x92, 0x0000);  
+	LCD_Write_COM_DATA(0x07, 0x0133); // 262K color and display ON        
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325d/default/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325d/default/setxy.h
new file mode 100644
index 0000000..f5fdd94
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9325d/default/setxy.h
@@ -0,0 +1,10 @@
+case ILI9325D_8:
+case ILI9325D_16:
+	LCD_Write_COM_DATA(0x20,x1);
+	LCD_Write_COM_DATA(0x21,y1);
+	LCD_Write_COM_DATA(0x50,x1);
+	LCD_Write_COM_DATA(0x52,y1);
+	LCD_Write_COM_DATA(0x51,x2);
+	LCD_Write_COM_DATA(0x53,y2);
+	LCD_Write_COM(0x22); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9327/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9327/initlcd.h
new file mode 100644
index 0000000..451806b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9327/initlcd.h
@@ -0,0 +1,63 @@
+case ILI9327:
+	LCD_Write_COM(0xE9);
+	LCD_Write_DATA(0x00,0x20);
+	LCD_Write_COM(0x11); //Exit Sleep
+	delay(100);
+	LCD_Write_COM(0xD1);
+	LCD_Write_DATA(0x00,0x00);
+	LCD_Write_DATA(0x00,0x71);
+	LCD_Write_DATA(0x00,0x19);
+	LCD_Write_COM(0xD0);
+	LCD_Write_DATA(0x00,0x07);
+	LCD_Write_DATA(0x00,0x01);
+	LCD_Write_DATA(0x00,0x08);
+	LCD_Write_COM(0x36);
+	LCD_Write_DATA(0x00,0x48);
+	LCD_Write_COM(0x3A);
+	LCD_Write_DATA(0x00,0x05);
+	LCD_Write_COM(0xC1);
+	LCD_Write_DATA(0x00,0x10);
+	LCD_Write_DATA(0x00,0x10);
+	LCD_Write_DATA(0x00,0x02);
+	LCD_Write_DATA(0x00,0x02);
+	LCD_Write_COM(0xC0); //Set Default Gamma
+	LCD_Write_DATA(0x00,0x00);
+	LCD_Write_DATA(0x00,0x35);
+	LCD_Write_DATA(0x00,0x00);
+	LCD_Write_DATA(0x00,0x00);
+	LCD_Write_DATA(0x00,0x01);
+	LCD_Write_DATA(0x00,0x02);
+	LCD_Write_COM(0xC5); //Set frame rate
+	LCD_Write_DATA(0x00,0x04);
+	LCD_Write_COM(0xD2); //power setting
+	LCD_Write_DATA(0x00,0x01);
+	LCD_Write_DATA(0x00,0x44);
+	LCD_Write_COM(0xC8); //Set Gamma
+	LCD_Write_DATA(0x00,0x04);
+	LCD_Write_DATA(0x00,0x67);
+	LCD_Write_DATA(0x00,0x35);
+	LCD_Write_DATA(0x00,0x04);
+	LCD_Write_DATA(0x00,0x08);
+	LCD_Write_DATA(0x00,0x06);
+	LCD_Write_DATA(0x00,0x24);
+	LCD_Write_DATA(0x00,0x01);
+	LCD_Write_DATA(0x00,0x37);
+	LCD_Write_DATA(0x00,0x40);
+	LCD_Write_DATA(0x00,0x03);
+	LCD_Write_DATA(0x00,0x10);
+	LCD_Write_DATA(0x00,0x08);
+	LCD_Write_DATA(0x00,0x80);
+	LCD_Write_DATA(0x00,0x00);
+	LCD_Write_COM(0x2A); 
+	LCD_Write_DATA(0x00,0x00);
+	LCD_Write_DATA(0x00,0x00);
+	LCD_Write_DATA(0x00,0x00);
+	LCD_Write_DATA(0x00,0xeF);
+	LCD_Write_COM(0x2B); 
+	LCD_Write_DATA(0x00,0x00);
+	LCD_Write_DATA(0x00,0x00);
+	LCD_Write_DATA(0x00,0x01);
+	LCD_Write_DATA(0x00,0x8F);
+	LCD_Write_COM(0x29); //display on      
+	LCD_Write_COM(0x2C); //display on
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9327/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9327/setxy.h
new file mode 100644
index 0000000..6390c65
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9327/setxy.h
@@ -0,0 +1,13 @@
+case ILI9327:
+	LCD_Write_COM(0x2a);
+  	LCD_Write_DATA(0x00,x1>>8);
+  	LCD_Write_DATA(0x00,x1);
+  	LCD_Write_DATA(0x00,x2>>8);
+  	LCD_Write_DATA(0x00,x2);
+  	LCD_Write_COM(0x2b);
+  	LCD_Write_DATA(0x00,y1>>8);
+  	LCD_Write_DATA(0x00,y1);
+  	LCD_Write_DATA(0x00,y2>>8);
+  	LCD_Write_DATA(0x00,y2);
+  	LCD_Write_COM(0x2c); 							 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9341/s4p/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9341/s4p/initlcd.h
new file mode 100644
index 0000000..0a5a082
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9341/s4p/initlcd.h
@@ -0,0 +1,58 @@
+case ILI9341_S4P:
+	LCD_Write_COM(0x11);//sleep out 
+	delay(20);
+  //LCD_Write_COM(0x01); //reset
+  //delay(15);
+  LCD_Write_COM(0x28); //display off
+  delay(5);
+  LCD_Write_COM(0xCF); //power control b
+  LCD_Write_DATA(0x00);
+  LCD_Write_DATA(0x83); //83 81 AA
+  LCD_Write_DATA(0x30);
+  LCD_Write_COM(0xED); //power on seq control
+  LCD_Write_DATA(0x64); //64 67
+  LCD_Write_DATA(0x03);
+  LCD_Write_DATA(0x12);
+  LCD_Write_DATA(0x81);
+  LCD_Write_COM(0xE8); //timing control a
+  LCD_Write_DATA(0x85);
+  LCD_Write_DATA(0x01);
+  LCD_Write_DATA(0x79); //79 78
+  LCD_Write_COM(0xCB); //power control a
+  LCD_Write_DATA(0x39);
+  LCD_Write_DATA(0X2C);
+  LCD_Write_DATA(0x00);
+  LCD_Write_DATA(0x34);
+  LCD_Write_DATA(0x02);
+  LCD_Write_COM(0xF7); //pump ratio control
+  LCD_Write_DATA(0x20);
+  LCD_Write_COM(0xEA); //timing control b
+  LCD_Write_DATA(0x00);
+  LCD_Write_DATA(0x00);
+  LCD_Write_COM(0xC0); //power control 2
+  LCD_Write_DATA(0x26); //26 25
+  LCD_Write_COM(0xC1); //power control 2
+  LCD_Write_DATA(0x11);
+  LCD_Write_COM(0xC5); //vcom control 1
+  LCD_Write_DATA(0x35);
+  LCD_Write_DATA(0x3E);
+  LCD_Write_COM(0xC7); //vcom control 2
+  LCD_Write_DATA(0xBE); //BE 94
+  LCD_Write_COM(0xB1); //frame control
+  LCD_Write_DATA(0x00);
+  LCD_Write_DATA(0x1B); //1B 70
+  LCD_Write_COM(0xB6); //display control
+  LCD_Write_DATA(0x0A);
+  LCD_Write_DATA(0x82);
+  LCD_Write_DATA(0x27);
+  LCD_Write_DATA(0x00);
+  LCD_Write_COM(0xB7); //emtry mode
+  LCD_Write_DATA(0x07);
+  LCD_Write_COM(0x3A); //pixel format
+  LCD_Write_DATA(0x55); //16bit
+  LCD_Write_COM(0x36); //mem access
+  LCD_Write_DATA((1<<3)|(1<<6));
+  //LCD_Write_DATA((1<<3)|(1<<7)); //rotate 180
+  LCD_Write_COM(0x29); //display on
+  delay(5);
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9341/s4p/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9341/s4p/setxy.h
new file mode 100644
index 0000000..08ac212
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9341/s4p/setxy.h
@@ -0,0 +1,13 @@
+case ILI9341_S4P:
+	LCD_Write_COM(0x2A); //column
+	LCD_Write_DATA(x1>>8);
+	LCD_Write_DATA(x1);
+	LCD_Write_DATA(x2>>8);
+	LCD_Write_DATA(x2);
+	LCD_Write_COM(0x2B); //page
+	LCD_Write_DATA(y1>>8);
+	LCD_Write_DATA(y1);
+	LCD_Write_DATA(y2>>8);
+	LCD_Write_DATA(y2);
+	LCD_Write_COM(0x2C); //write
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9341/s5p/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9341/s5p/initlcd.h
new file mode 100644
index 0000000..7afa6f6
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9341/s5p/initlcd.h
@@ -0,0 +1,105 @@
+case ILI9341_S5P:
+    LCD_Write_COM(0xCB);  
+    LCD_Write_DATA(0x39); 
+    LCD_Write_DATA(0x2C); 
+    LCD_Write_DATA(0x00); 
+    LCD_Write_DATA(0x34); 
+    LCD_Write_DATA(0x02); 
+
+    LCD_Write_COM(0xCF);  
+    LCD_Write_DATA(0x00); 
+    LCD_Write_DATA(0XC1); 
+    LCD_Write_DATA(0X30); 
+
+    LCD_Write_COM(0xE8);  
+    LCD_Write_DATA(0x85); 
+    LCD_Write_DATA(0x00); 
+    LCD_Write_DATA(0x78); 
+
+    LCD_Write_COM(0xEA);  
+    LCD_Write_DATA(0x00); 
+    LCD_Write_DATA(0x00); 
+ 
+    LCD_Write_COM(0xED);  
+    LCD_Write_DATA(0x64); 
+    LCD_Write_DATA(0x03); 
+    LCD_Write_DATA(0X12); 
+    LCD_Write_DATA(0X81); 
+
+    LCD_Write_COM(0xF7);  
+    LCD_Write_DATA(0x20); 
+  
+    LCD_Write_COM(0xC0);    //Power control 
+    LCD_Write_DATA(0x23);   //VRH[5:0] 
+ 
+    LCD_Write_COM(0xC1);    //Power control 
+    LCD_Write_DATA(0x10);   //SAP[2:0];BT[3:0] 
+
+    LCD_Write_COM(0xC5);    //VCM control 
+    LCD_Write_DATA(0x3e);   //Contrast
+    LCD_Write_DATA(0x28); 
+ 
+    LCD_Write_COM(0xC7);    //VCM control2 
+    LCD_Write_DATA(0x86);   //--
+ 
+    LCD_Write_COM(0x36);    // Memory Access Control 
+    LCD_Write_DATA(0x48);   
+
+    LCD_Write_COM(0x3A);    
+    LCD_Write_DATA(0x55); 
+
+    LCD_Write_COM(0xB1);    
+    LCD_Write_DATA(0x00);  
+    LCD_Write_DATA(0x18); 
+ 
+    LCD_Write_COM(0xB6);    // Display Function Control 
+    LCD_Write_DATA(0x08); 
+    LCD_Write_DATA(0x82);
+    LCD_Write_DATA(0x27);  
+/* 
+    LCD_Write_COM(0xF2);    // 3Gamma Function Disable 
+    LCD_Write_DATA(0x00); 
+ 
+    LCD_Write_COM(0x26);    //Gamma curve selected 
+    LCD_Write_DATA(0x01); 
+
+    LCD_Write_COM(0xE0);    //Set Gamma 
+    LCD_Write_DATA(0x0F); 
+    LCD_Write_DATA(0x31); 
+    LCD_Write_DATA(0x2B); 
+    LCD_Write_DATA(0x0C); 
+    LCD_Write_DATA(0x0E); 
+    LCD_Write_DATA(0x08); 
+    LCD_Write_DATA(0x4E); 
+    LCD_Write_DATA(0xF1); 
+    LCD_Write_DATA(0x37); 
+    LCD_Write_DATA(0x07); 
+    LCD_Write_DATA(0x10); 
+    LCD_Write_DATA(0x03); 
+    LCD_Write_DATA(0x0E); 
+    LCD_Write_DATA(0x09); 
+    LCD_Write_DATA(0x00); 
+
+    LCD_Write_COM(0XE1);    //Set Gamma 
+    LCD_Write_DATA(0x00); 
+    LCD_Write_DATA(0x0E); 
+    LCD_Write_DATA(0x14); 
+    LCD_Write_DATA(0x03); 
+    LCD_Write_DATA(0x11); 
+    LCD_Write_DATA(0x07); 
+    LCD_Write_DATA(0x31); 
+    LCD_Write_DATA(0xC1); 
+    LCD_Write_DATA(0x48); 
+    LCD_Write_DATA(0x08); 
+    LCD_Write_DATA(0x0F); 
+    LCD_Write_DATA(0x0C); 
+    LCD_Write_DATA(0x31); 
+    LCD_Write_DATA(0x36); 
+    LCD_Write_DATA(0x0F); 
+*/
+    LCD_Write_COM(0x11);    //Exit Sleep 
+    delay(120); 
+				
+    LCD_Write_COM(0x29);    //Display on 
+    LCD_Write_COM(0x2c); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9341/s5p/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9341/s5p/setxy.h
new file mode 100644
index 0000000..965f21d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9341/s5p/setxy.h
@@ -0,0 +1,13 @@
+case ILI9341_S5P:
+	LCD_Write_COM(0x2a); 
+	LCD_Write_DATA(x1>>8);
+	LCD_Write_DATA(x1);
+	LCD_Write_DATA(x2>>8);
+	LCD_Write_DATA(x2);
+	LCD_Write_COM(0x2b); 
+	LCD_Write_DATA(y1>>8);
+	LCD_Write_DATA(y1);
+	LCD_Write_DATA(y2>>8);
+	LCD_Write_DATA(y2);
+	LCD_Write_COM(0x2c); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9481/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9481/initlcd.h
new file mode 100644
index 0000000..74260ed
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9481/initlcd.h
@@ -0,0 +1,62 @@
+case ILI9481:
+	LCD_Write_COM(0x11);
+	delay(20);
+	LCD_Write_COM(0xD0);
+	LCD_Write_DATA(0x07);
+	LCD_Write_DATA(0x42);
+	LCD_Write_DATA(0x18);
+
+	LCD_Write_COM(0xD1);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x07);
+	LCD_Write_DATA(0x10);
+
+	LCD_Write_COM(0xD2);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x02);
+
+	LCD_Write_COM(0xC0);
+	LCD_Write_DATA(0x10);
+	LCD_Write_DATA(0x3B);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x02);
+	LCD_Write_DATA(0x11);
+
+	LCD_Write_COM(0xC5);
+	LCD_Write_DATA(0x03);
+
+	LCD_Write_COM(0xC8);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x32);
+	LCD_Write_DATA(0x36);
+	LCD_Write_DATA(0x45);
+	LCD_Write_DATA(0x06);
+	LCD_Write_DATA(0x16);
+	LCD_Write_DATA(0x37);
+	LCD_Write_DATA(0x75);
+	LCD_Write_DATA(0x77);
+	LCD_Write_DATA(0x54);
+	LCD_Write_DATA(0x0C);
+	LCD_Write_DATA(0x00);
+
+	LCD_Write_COM(0x36);
+	LCD_Write_DATA(0x0A);
+
+
+	LCD_Write_COM(0x3A);
+	LCD_Write_DATA(0x55);
+
+	LCD_Write_COM(0x2A);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x3F);
+
+	LCD_Write_COM(0x2B);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0xE0);
+	delay(120);
+	LCD_Write_COM(0x29);
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9481/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9481/setxy.h
new file mode 100644
index 0000000..e3e7ce2
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ili9481/setxy.h
@@ -0,0 +1,13 @@
+case ILI9481:
+	LCD_Write_COM(0x2a); 
+	LCD_Write_DATA(x1>>8);
+	LCD_Write_DATA(x1);
+	LCD_Write_DATA(x2>>8);
+	LCD_Write_DATA(x2);
+	LCD_Write_COM(0x2b); 
+	LCD_Write_DATA(y1>>8);
+	LCD_Write_DATA(y1);
+	LCD_Write_DATA(y2>>8);
+	LCD_Write_DATA(y2);
+	LCD_Write_COM(0x2c); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/pcf8833/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/pcf8833/initlcd.h
new file mode 100644
index 0000000..685f855
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/pcf8833/initlcd.h
@@ -0,0 +1,30 @@
+case PCF8833:
+	LCD_Write_COM(0x01);
+	LCD_Write_COM(0x25);
+	LCD_Write_DATA(0x40);
+	LCD_Write_COM(0x11);
+	delay(10);
+	LCD_Write_COM(0x20);
+	LCD_Write_COM(0x38);
+	LCD_Write_COM(0x29);
+	LCD_Write_COM(0x13);
+	LCD_Write_COM(0x36);
+	LCD_Write_DATA(0x60);
+	LCD_Write_COM(0x3A);
+	LCD_Write_DATA(0x05);
+	LCD_Write_COM(0x2A);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x7F);
+	LCD_Write_COM(0xB4);
+	LCD_Write_DATA(0x03);
+	LCD_Write_DATA(0x08);
+	LCD_Write_DATA(0x0b);
+	LCD_Write_DATA(0x0e);
+	LCD_Write_COM(0xBA);
+	LCD_Write_DATA(0x07);
+	LCD_Write_DATA(0x0D);
+	LCD_Write_COM(0x2B);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x7F);
+	LCD_Write_COM(0x2C);
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/pcf8833/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/pcf8833/setxy.h
new file mode 100644
index 0000000..34dd38c
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/pcf8833/setxy.h
@@ -0,0 +1,9 @@
+case PCF8833:
+	LCD_Write_COM(0x2a); 
+  	LCD_Write_DATA(x1);
+  	LCD_Write_DATA(x2);
+	LCD_Write_COM(0x2b); 
+  	LCD_Write_DATA(y1);
+  	LCD_Write_DATA(y2);
+	LCD_Write_COM(0x2c); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/s1d19122/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/s1d19122/initlcd.h
new file mode 100644
index 0000000..33f2c65
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/s1d19122/initlcd.h
@@ -0,0 +1,183 @@
+case S1D19122:
+	//************* Start Initial Sequence **********//
+
+	int i,R,G,B;
+	LCD_Write_COM(0x11);
+	LCD_Write_COM(0x13);
+	LCD_Write_COM(0x29);
+    
+	//--------------  Display Control ---------//
+	LCD_Write_COM(0xB0);
+
+	LCD_Write_DATA(0x05);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0xF0);
+	LCD_Write_DATA(0x0A);
+	LCD_Write_DATA(0x41);
+	LCD_Write_DATA(0x02); 
+	LCD_Write_DATA(0x0A);
+	LCD_Write_DATA(0x30);
+	LCD_Write_DATA(0x31);
+	LCD_Write_DATA(0x36);
+	LCD_Write_DATA(0x37);
+	LCD_Write_DATA(0x40);
+	LCD_Write_DATA(0x02);
+	LCD_Write_DATA(0x3F);
+	LCD_Write_DATA(0x40);
+	LCD_Write_DATA(0x02);
+	LCD_Write_DATA(0x81);
+	LCD_Write_DATA(0x04);
+	LCD_Write_DATA(0x05);
+	LCD_Write_DATA(0x64);
+
+	// ----------- Gamma  Curve  Set3 Postive----------//
+	LCD_Write_COM(0xFC);
+
+	LCD_Write_DATA(0x88);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x10);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x10);
+	LCD_Write_DATA(0x42);
+	LCD_Write_DATA(0x42);
+	LCD_Write_DATA(0x22);
+	LCD_Write_DATA(0x11);
+	LCD_Write_DATA(0x11);
+	LCD_Write_DATA(0x22);
+	LCD_Write_DATA(0x99);
+	LCD_Write_DATA(0xAA);
+	LCD_Write_DATA(0xAA);
+	LCD_Write_DATA(0xAA);
+	LCD_Write_DATA(0xBB);
+	LCD_Write_DATA(0xBB);
+	LCD_Write_DATA(0xAA);
+	LCD_Write_DATA(0x33);
+	LCD_Write_DATA(0x33);
+	LCD_Write_DATA(0x11);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0xC0);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+
+	// ----------- Gamma  Curve  Set3 Negative----------//
+	LCD_Write_COM(0xFD);
+
+	LCD_Write_DATA(0x88);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x10);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x10);
+	LCD_Write_DATA(0x42);
+	LCD_Write_DATA(0x42);
+	LCD_Write_DATA(0x22);
+	LCD_Write_DATA(0x11);
+	LCD_Write_DATA(0x11);
+	LCD_Write_DATA(0x22);
+	LCD_Write_DATA(0x99);
+	LCD_Write_DATA(0xAA);
+	LCD_Write_DATA(0xAA);
+	LCD_Write_DATA(0xAA);
+	LCD_Write_DATA(0xBB);
+	LCD_Write_DATA(0xBB);
+	LCD_Write_DATA(0xAA);
+	LCD_Write_DATA(0x33);
+	LCD_Write_DATA(0x33);
+	LCD_Write_DATA(0x11);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x03);
+
+	// ----------- EVRSER Regulator Voltage Setting---------//
+	LCD_Write_COM(0xBE);
+
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x15);
+	LCD_Write_DATA(0x16);
+	LCD_Write_DATA(0x08);
+	LCD_Write_DATA(0x09);
+	LCD_Write_DATA(0x15);
+	LCD_Write_DATA(0x10);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+
+	// -----------Module Definiton Setting---------//
+	LCD_Write_COM(0xC0);
+
+	LCD_Write_DATA(0x0E);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+
+	// -----------PWRDEF Power Ability Ddfinition----------//
+	LCD_Write_COM(0xC1);
+
+	LCD_Write_DATA(0x2F);
+	LCD_Write_DATA(0x23);
+	LCD_Write_DATA(0xB4);
+	LCD_Write_DATA(0xFF);
+	LCD_Write_DATA(0x24);
+	LCD_Write_DATA(0x03);
+	LCD_Write_DATA(0x20);
+	LCD_Write_DATA(0x02);
+	LCD_Write_DATA(0x02);
+	LCD_Write_DATA(0x02);
+	LCD_Write_DATA(0x20);
+	LCD_Write_DATA(0x20);
+	LCD_Write_DATA(0x00);
+
+	// -----------Other Setting----------//
+	LCD_Write_COM(0xC2);
+	LCD_Write_DATA(0x03);
+	LCD_Write_COM(0x26);
+	LCD_Write_DATA(0x08);
+	LCD_Write_COM(0x35);
+   
+	LCD_Write_COM(0x36);
+	LCD_Write_DATA(0x64);
+	LCD_Write_COM(0x3A);
+	LCD_Write_DATA(0x05);
+	LCD_Write_COM(0x2A);
+	LCD_Write_DATA(0x01,0x3f);
+	LCD_Write_COM(0x2B);
+	LCD_Write_DATA(0xEF);
+	LCD_Write_COM(0x2c);
+
+	// -----------RGB Setting----------//
+	LCD_Write_COM(0x2D);
+	R=0;
+	G=0;
+	B=0;   
+    
+	for(i=0;i<32;i++)
+	{ 
+		LCD_Write_DATA(R);
+		R=R+2;
+	}
+	for(i=0;i<64;i++)
+	{ 
+		LCD_Write_DATA(G);
+		G=G+1;
+	} 
+	for(i=0;i<32;i++)
+	{ 
+		LCD_Write_DATA(B);
+		B=B+2;
+	}    
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/s1d19122/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/s1d19122/setxy.h
new file mode 100644
index 0000000..d88c733
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/s1d19122/setxy.h
@@ -0,0 +1,13 @@
+case S1D19122:
+	LCD_Write_COM(0x2a); 
+  	LCD_Write_DATA(x1>>8);
+  	LCD_Write_DATA(x1);
+  	LCD_Write_DATA(x2>>8);
+  	LCD_Write_DATA(x2);
+	LCD_Write_COM(0x2b); 
+  	LCD_Write_DATA(y1>>8);
+  	LCD_Write_DATA(y1);
+  	LCD_Write_DATA(y2>>8);
+  	LCD_Write_DATA(y2);
+	LCD_Write_COM(0x2c); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/s6d0164/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/s6d0164/initlcd.h
new file mode 100644
index 0000000..7b2716b
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/s6d0164/initlcd.h
@@ -0,0 +1,44 @@
+case S6D0164:
+	LCD_Write_COM_DATA(0x11,0x001A);
+	LCD_Write_COM_DATA(0x12,0x3121);
+	LCD_Write_COM_DATA(0x13,0x006C);
+	LCD_Write_COM_DATA(0x14,0x4249);
+
+	LCD_Write_COM_DATA(0x10,0x0800);
+	delay(10);
+	LCD_Write_COM_DATA(0x11,0x011A);
+	delay(10);	
+	LCD_Write_COM_DATA(0x11,0x031A);
+	delay(10);
+	LCD_Write_COM_DATA(0x11,0x071A);
+	delay(10);
+	LCD_Write_COM_DATA(0x11,0x0F1A);
+	delay(10);	
+	LCD_Write_COM_DATA(0x11,0x0F3A);
+	delay(30);
+
+	LCD_Write_COM_DATA(0x01,0x011C);
+	LCD_Write_COM_DATA(0x02,0x0100);
+	LCD_Write_COM_DATA(0x03,0x1030);
+	LCD_Write_COM_DATA(0x07,0x0000);
+	LCD_Write_COM_DATA(0x08,0x0808);
+	LCD_Write_COM_DATA(0x0B,0x1100);
+	LCD_Write_COM_DATA(0x0C,0x0000);
+
+	LCD_Write_COM_DATA(0x0F,0x1401);
+	LCD_Write_COM_DATA(0x15,0x0000);
+	LCD_Write_COM_DATA(0x20,0x0000);
+	LCD_Write_COM_DATA(0x21,0x0000);
+	
+
+	LCD_Write_COM_DATA(0x36,0x00AF); 
+	LCD_Write_COM_DATA(0x37,0x0000); 	
+	LCD_Write_COM_DATA(0x38,0x00DB);
+	LCD_Write_COM_DATA(0x39,0x0000); 
+	
+	LCD_Write_COM_DATA(0x0F,0x0B01);
+	LCD_Write_COM_DATA(0x07,0x0016);	
+	LCD_Write_COM_DATA(0x07,0x0017);
+
+	LCD_Write_COM(0x22);
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/s6d0164/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/s6d0164/setxy.h
new file mode 100644
index 0000000..6e5d5e9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/s6d0164/setxy.h
@@ -0,0 +1,9 @@
+case S6D0164:
+	LCD_Write_COM_DATA(0x36,x2); 
+	LCD_Write_COM_DATA(0x37,x1);
+	LCD_Write_COM_DATA(0x38,y2);
+	LCD_Write_COM_DATA(0x39,y1); 
+	LCD_Write_COM_DATA(0x20,x1);
+	LCD_Write_COM_DATA(0x21,y1); 	
+	LCD_Write_COM(0x22);
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/s6d1121/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/s6d1121/initlcd.h
new file mode 100644
index 0000000..c8d80e6
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/s6d1121/initlcd.h
@@ -0,0 +1,47 @@
+case S6D1121_8:
+case S6D1121_16:
+	LCD_Write_COM_DATA(0x11,0x2004);		
+	LCD_Write_COM_DATA(0x13,0xCC00);		
+	LCD_Write_COM_DATA(0x15,0x2600);	
+	LCD_Write_COM_DATA(0x14,0x252A);	
+	LCD_Write_COM_DATA(0x12,0x0033);		
+	LCD_Write_COM_DATA(0x13,0xCC04);		
+	LCD_Write_COM_DATA(0x13,0xCC06);		
+	LCD_Write_COM_DATA(0x13,0xCC4F);		
+	LCD_Write_COM_DATA(0x13,0x674F);
+	LCD_Write_COM_DATA(0x11,0x2003);
+	LCD_Write_COM_DATA(0x30,0x2609);		
+	LCD_Write_COM_DATA(0x31,0x242C);		
+	LCD_Write_COM_DATA(0x32,0x1F23);		
+	LCD_Write_COM_DATA(0x33,0x2425);		
+	LCD_Write_COM_DATA(0x34,0x2226);		
+	LCD_Write_COM_DATA(0x35,0x2523);		
+	LCD_Write_COM_DATA(0x36,0x1C1A);		
+	LCD_Write_COM_DATA(0x37,0x131D);		
+	LCD_Write_COM_DATA(0x38,0x0B11);		
+	LCD_Write_COM_DATA(0x39,0x1210);		
+	LCD_Write_COM_DATA(0x3A,0x1315);		
+	LCD_Write_COM_DATA(0x3B,0x3619);		
+	LCD_Write_COM_DATA(0x3C,0x0D00);		
+	LCD_Write_COM_DATA(0x3D,0x000D);		
+	LCD_Write_COM_DATA(0x16,0x0007);		
+	LCD_Write_COM_DATA(0x02,0x0013);		
+	LCD_Write_COM_DATA(0x03,0x0003);		
+	LCD_Write_COM_DATA(0x01,0x0127);		
+	LCD_Write_COM_DATA(0x08,0x0303);		
+	LCD_Write_COM_DATA(0x0A,0x000B);		
+	LCD_Write_COM_DATA(0x0B,0x0003);   
+	LCD_Write_COM_DATA(0x0C,0x0000);   
+	LCD_Write_COM_DATA(0x41,0x0000);    
+	LCD_Write_COM_DATA(0x50,0x0000);   
+	LCD_Write_COM_DATA(0x60,0x0005);    
+	LCD_Write_COM_DATA(0x70,0x000B);    
+	LCD_Write_COM_DATA(0x71,0x0000);    
+	LCD_Write_COM_DATA(0x78,0x0000);    
+	LCD_Write_COM_DATA(0x7A,0x0000);   
+	LCD_Write_COM_DATA(0x79,0x0007);		
+	LCD_Write_COM_DATA(0x07,0x0051);   
+	LCD_Write_COM_DATA(0x07,0x0053);		
+	LCD_Write_COM_DATA(0x79,0x0000);
+	LCD_Write_COM(0x22);
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/s6d1121/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/s6d1121/setxy.h
new file mode 100644
index 0000000..c2f5a1f
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/s6d1121/setxy.h
@@ -0,0 +1,9 @@
+case S6D1121_8:
+case S6D1121_16:
+	LCD_Write_COM_DATA(0x46,(x2 << 8) | x1);
+	LCD_Write_COM_DATA(0x47,y2);
+	LCD_Write_COM_DATA(0x48,y1);
+	LCD_Write_COM_DATA(0x20,x1);
+	LCD_Write_COM_DATA(0x21,y1);
+	LCD_Write_COM(0x22);
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1289/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1289/initlcd.h
new file mode 100644
index 0000000..0d63d92
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1289/initlcd.h
@@ -0,0 +1,46 @@
+case SSD1289:
+case SSD1289_8:
+case SSD1289LATCHED:
+	LCD_Write_COM_DATA(0x00,0x0001);
+	LCD_Write_COM_DATA(0x03,0xA8A4);
+	LCD_Write_COM_DATA(0x0C,0x0000);
+	LCD_Write_COM_DATA(0x0D,0x080C);
+	LCD_Write_COM_DATA(0x0E,0x2B00);
+	LCD_Write_COM_DATA(0x1E,0x00B7);
+	LCD_Write_COM_DATA(0x01,0x2B3F);
+	LCD_Write_COM_DATA(0x02,0x0600);
+	LCD_Write_COM_DATA(0x10,0x0000);
+	LCD_Write_COM_DATA(0x11,0x6070);
+	LCD_Write_COM_DATA(0x05,0x0000);
+	LCD_Write_COM_DATA(0x06,0x0000);
+	LCD_Write_COM_DATA(0x16,0xEF1C);
+	LCD_Write_COM_DATA(0x17,0x0003);
+	LCD_Write_COM_DATA(0x07,0x0233);
+	LCD_Write_COM_DATA(0x0B,0x0000);
+	LCD_Write_COM_DATA(0x0F,0x0000);
+	LCD_Write_COM_DATA(0x41,0x0000);
+	LCD_Write_COM_DATA(0x42,0x0000);
+	LCD_Write_COM_DATA(0x48,0x0000);
+	LCD_Write_COM_DATA(0x49,0x013F);
+	LCD_Write_COM_DATA(0x4A,0x0000);
+	LCD_Write_COM_DATA(0x4B,0x0000);
+	LCD_Write_COM_DATA(0x44,0xEF00);
+	LCD_Write_COM_DATA(0x45,0x0000);
+	LCD_Write_COM_DATA(0x46,0x013F);
+	LCD_Write_COM_DATA(0x30,0x0707);
+	LCD_Write_COM_DATA(0x31,0x0204);
+	LCD_Write_COM_DATA(0x32,0x0204);
+	LCD_Write_COM_DATA(0x33,0x0502);
+	LCD_Write_COM_DATA(0x34,0x0507);
+	LCD_Write_COM_DATA(0x35,0x0204);
+	LCD_Write_COM_DATA(0x36,0x0204);
+	LCD_Write_COM_DATA(0x37,0x0502);
+	LCD_Write_COM_DATA(0x3A,0x0302);
+	LCD_Write_COM_DATA(0x3B,0x0302);
+	LCD_Write_COM_DATA(0x23,0x0000);
+	LCD_Write_COM_DATA(0x24,0x0000);
+	LCD_Write_COM_DATA(0x25,0x8000);
+	LCD_Write_COM_DATA(0x4f,0x0000);
+	LCD_Write_COM_DATA(0x4e,0x0000);
+	LCD_Write_COM(0x22);   
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1289/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1289/setxy.h
new file mode 100644
index 0000000..28b0efd
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1289/setxy.h
@@ -0,0 +1,10 @@
+case SSD1289:
+case SSD1289_8:
+case SSD1289LATCHED:
+	LCD_Write_COM_DATA(0x44,(x2<<8)+x1);
+	LCD_Write_COM_DATA(0x45,y1);
+	LCD_Write_COM_DATA(0x46,y2);
+	LCD_Write_COM_DATA(0x4e,x1);
+	LCD_Write_COM_DATA(0x4f,y1);
+	LCD_Write_COM(0x22); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/480/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/480/initlcd.h
new file mode 100644
index 0000000..a051795
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/480/initlcd.h
@@ -0,0 +1,78 @@
+case SSD1963_480:
+	LCD_Write_COM(0xE2);		//PLL multiplier, set PLL clock to 120M
+	LCD_Write_DATA(0x23);	    //N=0x36 for 6.5M, 0x23 for 10M crystal
+	LCD_Write_DATA(0x02);
+	LCD_Write_DATA(0x54);
+	LCD_Write_COM(0xE0);		// PLL enable
+	LCD_Write_DATA(0x01);
+	delay(10);
+	LCD_Write_COM(0xE0);
+	LCD_Write_DATA(0x03);
+	delay(10);
+	LCD_Write_COM(0x01);		// software reset
+	delay(100);
+	LCD_Write_COM(0xE6);		//PLL setting for PCLK, depends on resolution
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x1F);
+	LCD_Write_DATA(0xFF);
+
+	LCD_Write_COM(0xB0);		//LCD SPECIFICATION
+	LCD_Write_DATA(0x20);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x01);		//Set HDP	479
+	LCD_Write_DATA(0xDF);
+	LCD_Write_DATA(0x01);		//Set VDP	271
+	LCD_Write_DATA(0x0F);
+	LCD_Write_DATA(0x00);
+
+	LCD_Write_COM(0xB4);		//HSYNC
+	LCD_Write_DATA(0x02);		//Set HT	531
+	LCD_Write_DATA(0x13);
+	LCD_Write_DATA(0x00);		//Set HPS	8
+	LCD_Write_DATA(0x08);
+	LCD_Write_DATA(0x2B);		//Set HPW	43
+	LCD_Write_DATA(0x00);		//Set LPS	2
+	LCD_Write_DATA(0x02);
+	LCD_Write_DATA(0x00);
+
+	LCD_Write_COM(0xB6);		//VSYNC
+	LCD_Write_DATA(0x01);		//Set VT	288
+	LCD_Write_DATA(0x20);
+	LCD_Write_DATA(0x00);		//Set VPS	4
+	LCD_Write_DATA(0x04);
+	LCD_Write_DATA(0x0c);		//Set VPW	12
+	LCD_Write_DATA(0x00);		//Set FPS	2
+	LCD_Write_DATA(0x02);
+
+	LCD_Write_COM(0xBA);
+	LCD_Write_DATA(0x0F);		//GPIO[3:0] out 1
+
+	LCD_Write_COM(0xB8);
+	LCD_Write_DATA(0x07);	    //GPIO3=input, GPIO[2:0]=output
+	LCD_Write_DATA(0x01);		//GPIO0 normal
+
+	LCD_Write_COM(0x36);		//rotation
+	LCD_Write_DATA(0x22);
+
+	LCD_Write_COM(0xF0);		//pixel data interface
+	LCD_Write_DATA(0x03);
+
+
+	delay(1);
+
+	setXY(0, 0, 479, 271);
+	LCD_Write_COM(0x29);		//display on
+
+	LCD_Write_COM(0xBE);		//set PWM for B/L
+	LCD_Write_DATA(0x06);
+	LCD_Write_DATA(0xf0);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0xf0);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+
+	LCD_Write_COM(0xd0); 
+	LCD_Write_DATA(0x0d);	
+
+	LCD_Write_COM(0x2C); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/480/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/480/setxy.h
new file mode 100644
index 0000000..e2b9297
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/480/setxy.h
@@ -0,0 +1,15 @@
+case SSD1963_480:
+	swap(word, x1, y1);
+	swap(word, x2, y2);
+	LCD_Write_COM(0x2a); 
+  	LCD_Write_DATA(x1>>8);
+  	LCD_Write_DATA(x1);
+  	LCD_Write_DATA(x2>>8);
+  	LCD_Write_DATA(x2);
+	LCD_Write_COM(0x2b); 
+  	LCD_Write_DATA(y1>>8);
+  	LCD_Write_DATA(y1);
+  	LCD_Write_DATA(y2>>8);
+  	LCD_Write_DATA(y2);
+	LCD_Write_COM(0x2c); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/800/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/800/initlcd.h
new file mode 100644
index 0000000..722286d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/800/initlcd.h
@@ -0,0 +1,78 @@
+case SSD1963_800:
+	LCD_Write_COM(0xE2);		//PLL multiplier, set PLL clock to 120M
+	LCD_Write_DATA(0x1E);	    //N=0x36 for 6.5M, 0x23 for 10M crystal
+	LCD_Write_DATA(0x02);
+	LCD_Write_DATA(0x54);
+	LCD_Write_COM(0xE0);		// PLL enable
+	LCD_Write_DATA(0x01);
+	delay(10);
+	LCD_Write_COM(0xE0);
+	LCD_Write_DATA(0x03);
+	delay(10);
+	LCD_Write_COM(0x01);		// software reset
+	delay(100);
+	LCD_Write_COM(0xE6);		//PLL setting for PCLK, depends on resolution
+	LCD_Write_DATA(0x03);
+	LCD_Write_DATA(0xFF);
+	LCD_Write_DATA(0xFF);
+
+	LCD_Write_COM(0xB0);		//LCD SPECIFICATION
+	LCD_Write_DATA(0x24);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x03);		//Set HDP	799
+	LCD_Write_DATA(0x1F);
+	LCD_Write_DATA(0x01);		//Set VDP	479
+	LCD_Write_DATA(0xDF);
+	LCD_Write_DATA(0x00);
+
+	LCD_Write_COM(0xB4);		//HSYNC
+	LCD_Write_DATA(0x03);		//Set HT	928
+	LCD_Write_DATA(0xA0);
+	LCD_Write_DATA(0x00);		//Set HPS	46
+	LCD_Write_DATA(0x2E);
+	LCD_Write_DATA(0x30);		//Set HPW	48
+	LCD_Write_DATA(0x00);		//Set LPS	15
+	LCD_Write_DATA(0x0F);
+	LCD_Write_DATA(0x00);
+
+	LCD_Write_COM(0xB6);		//VSYNC
+	LCD_Write_DATA(0x02);		//Set VT	525
+	LCD_Write_DATA(0x0D);
+	LCD_Write_DATA(0x00);		//Set VPS	16
+	LCD_Write_DATA(0x10);
+	LCD_Write_DATA(0x10);		//Set VPW	16
+	LCD_Write_DATA(0x00);		//Set FPS	8
+	LCD_Write_DATA(0x08);
+
+	LCD_Write_COM(0xBA);
+	LCD_Write_DATA(0x0F);		//GPIO[3:0] out 1
+
+	LCD_Write_COM(0xB8);
+	LCD_Write_DATA(0x07);	    //GPIO3=input, GPIO[2:0]=output
+	LCD_Write_DATA(0x01);		//GPIO0 normal
+
+	LCD_Write_COM(0x36);		//rotation
+	LCD_Write_DATA(0x22);
+
+	LCD_Write_COM(0xF0);		//pixel data interface
+	LCD_Write_DATA(0x03);
+
+
+	delay(1);
+
+	setXY(0, 0, 799, 479);
+	LCD_Write_COM(0x29);		//display on
+
+	LCD_Write_COM(0xBE);		//set PWM for B/L
+	LCD_Write_DATA(0x06);
+	LCD_Write_DATA(0xf0);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0xf0);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+
+	LCD_Write_COM(0xd0); 
+	LCD_Write_DATA(0x0d);	
+
+	LCD_Write_COM(0x2C); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/800/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/800/setxy.h
new file mode 100644
index 0000000..1b2fed7
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/800/setxy.h
@@ -0,0 +1,15 @@
+case SSD1963_800:
+	swap(word, x1, y1);
+	swap(word, x2, y2);
+	LCD_Write_COM(0x2a); 
+  	LCD_Write_DATA(x1>>8);
+  	LCD_Write_DATA(x1);
+  	LCD_Write_DATA(x2>>8);
+  	LCD_Write_DATA(x2);
+	LCD_Write_COM(0x2b); 
+  	LCD_Write_DATA(y1>>8);
+  	LCD_Write_DATA(y1);
+  	LCD_Write_DATA(y2>>8);
+  	LCD_Write_DATA(y2);
+	LCD_Write_COM(0x2c); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/800alt/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/800alt/initlcd.h
new file mode 100644
index 0000000..a0cbecc
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/800alt/initlcd.h
@@ -0,0 +1,78 @@
+case SSD1963_800ALT:
+	LCD_Write_COM(0xE2);		//PLL multiplier, set PLL clock to 120M
+	LCD_Write_DATA(0x23);	    //N=0x36 for 6.5M, 0x23 for 10M crystal
+	LCD_Write_DATA(0x02);
+	LCD_Write_DATA(0x04);
+	LCD_Write_COM(0xE0);		// PLL enable
+	LCD_Write_DATA(0x01);
+	delay(10);
+	LCD_Write_COM(0xE0);
+	LCD_Write_DATA(0x03);
+	delay(10);
+	LCD_Write_COM(0x01);		// software reset
+	delay(100);
+	LCD_Write_COM(0xE6);		//PLL setting for PCLK, depends on resolution
+	LCD_Write_DATA(0x04);
+	LCD_Write_DATA(0x93);
+	LCD_Write_DATA(0xE0);
+
+	LCD_Write_COM(0xB0);		//LCD SPECIFICATION
+	LCD_Write_DATA(0x00);	// 0x24
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x03);		//Set HDP	799
+	LCD_Write_DATA(0x1F);
+	LCD_Write_DATA(0x01);		//Set VDP	479
+	LCD_Write_DATA(0xDF);
+	LCD_Write_DATA(0x00);
+
+	LCD_Write_COM(0xB4);		//HSYNC
+	LCD_Write_DATA(0x03);		//Set HT	928
+	LCD_Write_DATA(0xA0);
+	LCD_Write_DATA(0x00);		//Set HPS	46
+	LCD_Write_DATA(0x2E);
+	LCD_Write_DATA(0x30);		//Set HPW	48
+	LCD_Write_DATA(0x00);		//Set LPS	15
+	LCD_Write_DATA(0x0F);
+	LCD_Write_DATA(0x00);
+
+	LCD_Write_COM(0xB6);		//VSYNC
+	LCD_Write_DATA(0x02);		//Set VT	525
+	LCD_Write_DATA(0x0D);
+	LCD_Write_DATA(0x00);		//Set VPS	16
+	LCD_Write_DATA(0x10);
+	LCD_Write_DATA(0x10);		//Set VPW	16
+	LCD_Write_DATA(0x00);		//Set FPS	8
+	LCD_Write_DATA(0x08);
+
+	LCD_Write_COM(0xBA);
+	LCD_Write_DATA(0x05);		//GPIO[3:0] out 1
+
+	LCD_Write_COM(0xB8);
+	LCD_Write_DATA(0x07);	    //GPIO3=input, GPIO[2:0]=output
+	LCD_Write_DATA(0x01);		//GPIO0 normal
+
+	LCD_Write_COM(0x36);		//rotation
+	LCD_Write_DATA(0x22);		// -- Set to 0x21 to rotate 180 degrees
+
+	LCD_Write_COM(0xF0);		//pixel data interface
+	LCD_Write_DATA(0x03);
+
+
+	delay(10);
+
+	setXY(0, 0, 799, 479);
+	LCD_Write_COM(0x29);		//display on
+
+	LCD_Write_COM(0xBE);		//set PWM for B/L
+	LCD_Write_DATA(0x06);
+	LCD_Write_DATA(0xF0);
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0xF0);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+
+	LCD_Write_COM(0xD0); 
+	LCD_Write_DATA(0x0D);	
+
+	LCD_Write_COM(0x2C); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/800alt/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/800alt/setxy.h
new file mode 100644
index 0000000..7e6a81d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/ssd1963/800alt/setxy.h
@@ -0,0 +1,15 @@
+case SSD1963_800ALT:
+	swap(word, x1, y1);
+	swap(word, x2, y2);
+	LCD_Write_COM(0x2a); 
+  	LCD_Write_DATA(x1>>8);
+  	LCD_Write_DATA(x1);
+  	LCD_Write_DATA(x2>>8);
+  	LCD_Write_DATA(x2);
+	LCD_Write_COM(0x2b); 
+  	LCD_Write_DATA(y1>>8);
+  	LCD_Write_DATA(y1);
+  	LCD_Write_DATA(y2>>8);
+  	LCD_Write_DATA(y2);
+	LCD_Write_COM(0x2c); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/st7735/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/st7735/initlcd.h
new file mode 100644
index 0000000..63439c7
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/st7735/initlcd.h
@@ -0,0 +1,104 @@
+case ST7735:
+	LCD_Write_COM(0x11);//Sleep exit 
+	delay(12);
+ 
+	//ST7735R Frame Rate
+	LCD_Write_COM(0xB1); 
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x2C);
+	LCD_Write_DATA(0x2D); 
+	LCD_Write_COM(0xB2); 
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x2C);
+	LCD_Write_DATA(0x2D); 
+	LCD_Write_COM(0xB3); 
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x2C);
+	LCD_Write_DATA(0x2D); 
+	LCD_Write_DATA(0x01);
+	LCD_Write_DATA(0x2C);
+	LCD_Write_DATA(0x2D); 
+
+	LCD_Write_COM(0xB4); //Column inversion 
+	LCD_Write_DATA(0x07); 
+ 
+	//ST7735R Power Sequence
+	LCD_Write_COM(0xC0); 
+	LCD_Write_DATA(0xA2);
+	LCD_Write_DATA(0x02);
+	LCD_Write_DATA(0x84); 
+	LCD_Write_COM(0xC1);
+	LCD_Write_DATA(0xC5); 
+	LCD_Write_COM(0xC2); 
+	LCD_Write_DATA(0x0A);
+	LCD_Write_DATA(0x00); 
+	LCD_Write_COM(0xC3); 
+	LCD_Write_DATA(0x8A);
+	LCD_Write_DATA(0x2A); 
+	LCD_Write_COM(0xC4); 
+	LCD_Write_DATA(0x8A);
+	LCD_Write_DATA(0xEE); 
+ 
+	LCD_Write_COM(0xC5); //VCOM 
+	LCD_Write_DATA(0x0E); 
+ 
+	LCD_Write_COM(0x36); //MX, MY, RGB mode 
+	LCD_Write_DATA(0xC8); 
+
+	//ST7735R Gamma Sequence
+	LCD_Write_COM(0xe0); 
+	LCD_Write_DATA(0x0f);
+	LCD_Write_DATA(0x1a); 
+	LCD_Write_DATA(0x0f);
+	LCD_Write_DATA(0x18); 
+	LCD_Write_DATA(0x2f);
+	LCD_Write_DATA(0x28); 
+	LCD_Write_DATA(0x20);
+	LCD_Write_DATA(0x22); 
+	LCD_Write_DATA(0x1f);
+	LCD_Write_DATA(0x1b); 
+	LCD_Write_DATA(0x23);
+	LCD_Write_DATA(0x37);
+	LCD_Write_DATA(0x00); 
+
+	LCD_Write_DATA(0x07); 
+	LCD_Write_DATA(0x02);
+	LCD_Write_DATA(0x10); 
+	LCD_Write_COM(0xe1); 
+	LCD_Write_DATA(0x0f);
+	LCD_Write_DATA(0x1b); 
+	LCD_Write_DATA(0x0f);
+	LCD_Write_DATA(0x17); 
+	LCD_Write_DATA(0x33);
+	LCD_Write_DATA(0x2c); 
+	LCD_Write_DATA(0x29);
+	LCD_Write_DATA(0x2e); 
+	LCD_Write_DATA(0x30);
+	LCD_Write_DATA(0x30); 
+	LCD_Write_DATA(0x39);
+	LCD_Write_DATA(0x3f); 
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x07); 
+	LCD_Write_DATA(0x03);
+	LCD_Write_DATA(0x10);  
+
+	LCD_Write_COM(0x2a);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x7f);
+	LCD_Write_COM(0x2b);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x9f);
+
+	LCD_Write_COM(0xF0); //Enable test command  
+	LCD_Write_DATA(0x01); 
+	LCD_Write_COM(0xF6); //Disable ram power save mode 
+	LCD_Write_DATA(0x00); 
+ 
+	LCD_Write_COM(0x3A); //65k mode 
+	LCD_Write_DATA(0x05); 
+	LCD_Write_COM(0x29);//Display on
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/st7735/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/st7735/setxy.h
new file mode 100644
index 0000000..ff38181
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/st7735/setxy.h
@@ -0,0 +1,13 @@
+case ST7735:
+	LCD_Write_COM(0x2a); 
+  	LCD_Write_DATA(x1>>8);
+  	LCD_Write_DATA(x1);
+  	LCD_Write_DATA(x2>>8);
+  	LCD_Write_DATA(x2);
+	LCD_Write_COM(0x2b); 
+  	LCD_Write_DATA(y1>>8);
+  	LCD_Write_DATA(y1);
+  	LCD_Write_DATA(y2>>8);
+  	LCD_Write_DATA(y2);
+	LCD_Write_COM(0x2c); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/st7735s/initlcd.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/st7735s/initlcd.h
new file mode 100644
index 0000000..d28296d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/st7735s/initlcd.h
@@ -0,0 +1,98 @@
+case ST7735S:
+	LCD_Write_COM(0x11);//Sleep exit 
+	delay(120);
+ 
+	//ST7735R Frame Rate
+	LCD_Write_COM(0xB1); 
+	LCD_Write_DATA(0x05);
+	LCD_Write_DATA(0x3C);
+	LCD_Write_DATA(0x3C); 
+	LCD_Write_COM(0xB2); 
+	LCD_Write_DATA(0x05);
+	LCD_Write_DATA(0x3C);
+	LCD_Write_DATA(0x3C); 
+	LCD_Write_COM(0xB3); 
+	LCD_Write_DATA(0x05);
+	LCD_Write_DATA(0x3C);
+	LCD_Write_DATA(0x3C); 
+	LCD_Write_DATA(0x05);
+	LCD_Write_DATA(0x3C);
+	LCD_Write_DATA(0x3C); 
+
+	LCD_Write_COM(0xB4); //Column inversion 
+	LCD_Write_DATA(0x03); 
+ 
+	//ST7735R Power Sequence
+	LCD_Write_COM(0xC0); 
+	LCD_Write_DATA(0x28);
+	LCD_Write_DATA(0x08);
+	LCD_Write_DATA(0x04); 
+	LCD_Write_COM(0xC1);
+	LCD_Write_DATA(0xC0); 
+	LCD_Write_COM(0xC2); 
+	LCD_Write_DATA(0x0D);
+	LCD_Write_DATA(0x00); 
+	LCD_Write_COM(0xC3); 
+	LCD_Write_DATA(0x8D);
+	LCD_Write_DATA(0x2A); 
+	LCD_Write_COM(0xC4); 
+	LCD_Write_DATA(0x8D);
+	LCD_Write_DATA(0xEE); 
+ 
+	LCD_Write_COM(0xC5); //VCOM 
+	LCD_Write_DATA(0x1A); 
+ 
+	LCD_Write_COM(0x36); //MX, MY, RGB mode 
+	LCD_Write_DATA(0xC0); 
+
+	//ST7735R Gamma Sequence
+	LCD_Write_COM(0xE0); 
+	LCD_Write_DATA(0x03);
+	LCD_Write_DATA(0x22); 
+	LCD_Write_DATA(0x07);
+	LCD_Write_DATA(0x0A); 
+	LCD_Write_DATA(0x2E);
+	LCD_Write_DATA(0x30); 
+	LCD_Write_DATA(0x25);
+	LCD_Write_DATA(0x2A); 
+	LCD_Write_DATA(0x28);
+	LCD_Write_DATA(0x26); 
+	LCD_Write_DATA(0x2E);
+	LCD_Write_DATA(0x3A);
+	LCD_Write_DATA(0x00); 
+	LCD_Write_DATA(0x01); 
+	LCD_Write_DATA(0x03);
+	LCD_Write_DATA(0x13); 
+	LCD_Write_COM(0xE1); 
+	LCD_Write_DATA(0x04);
+	LCD_Write_DATA(0x16); 
+	LCD_Write_DATA(0x06);
+	LCD_Write_DATA(0x0D); 
+	LCD_Write_DATA(0x2D);
+	LCD_Write_DATA(0x26); 
+	LCD_Write_DATA(0x23);
+	LCD_Write_DATA(0x27); 
+	LCD_Write_DATA(0x27);
+	LCD_Write_DATA(0x25); 
+	LCD_Write_DATA(0x2D);
+	LCD_Write_DATA(0x3B); 
+	LCD_Write_DATA(0x00);
+	LCD_Write_DATA(0x01); 
+	LCD_Write_DATA(0x04);
+	LCD_Write_DATA(0x13);  
+
+	//LCD_Write_COM(0x2A);
+	//LCD_Write_DATA(0x00);
+	//LCD_Write_DATA(0x00);
+	//LCD_Write_DATA(0x00);
+	//LCD_Write_DATA(0x7F);
+	//LCD_Write_COM(0x2B);
+	//LCD_Write_DATA(0x00);
+	//LCD_Write_DATA(0x00);
+	//LCD_Write_DATA(0x00);
+	//LCD_Write_DATA(0x9F);
+
+	LCD_Write_COM(0x3A); //65k mode 
+	LCD_Write_DATA(0x05); 
+	LCD_Write_COM(0x29);//Display on
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/tft_drivers/st7735s/setxy.h b/hardware/digistump/sam/libraries/UTFT/tft_drivers/st7735s/setxy.h
new file mode 100644
index 0000000..b7a1c64
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/tft_drivers/st7735s/setxy.h
@@ -0,0 +1,13 @@
+case ST7735S:
+	LCD_Write_COM(0x2a); 
+  	LCD_Write_DATA(x1>>8);
+  	LCD_Write_DATA(x1);
+  	LCD_Write_DATA(x2>>8);
+  	LCD_Write_DATA(x2);
+	LCD_Write_COM(0x2b); 
+  	LCD_Write_DATA(y1>>8);
+  	LCD_Write_DATA(y1);
+  	LCD_Write_DATA(y2>>8);
+  	LCD_Write_DATA(y2);
+	LCD_Write_COM(0x2c); 
+	break;
diff --git a/hardware/digistump/sam/libraries/UTFT/version.txt b/hardware/digistump/sam/libraries/UTFT/version.txt
new file mode 100644
index 0000000..aadd534
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTFT/version.txt
@@ -0,0 +1,48 @@
+Version:
+	1.0	12 Feb 2012  -  initial release
+	1.1	09 Apr 2012  -	added support for more display modules
+				added support for String objects to print()
+				fixed a bug in printNumF()
+				added optional minimum length and filler character to pintNumI() and printNumF()
+				added option to disable unneeded controller chip code to minimize memory use
+	1.2	14 Apr 2012  -	added support for more display modules
+				added getDisplayXSize() and getDisplayYSize()
+	1.3	03 Jun 2012  -	added support for more display modules
+				fixed a bug in the ITDB02-25H init
+	2.0	21 Jan 2013  -	added support for Arduino Due and Arduino Leonardo
+				added support for the "AquaLEDSource All in One Super Screw Shield" on chipKit Max32
+				added support for more display modules
+				fixed a bug in printNumF()
+				optimized drawLine()
+				optimized 16bit data transfer
+				optimized some 8bit data transfer
+				added option to use pre-defined RGB565 values with setColor(), setBackColor() and fillScr()
+				added functions getColor(), getBackColor(), getFont(), getFontXsize() and getFontYsize()
+				added 16 VGA standard colors as pre-defined color literal
+				rearranged the manual to keep related functions grouped together
+	2.01	05 Feb 2013  -  fixed a bug that only shows up on linux-based systems
+	2.1	29 Mar 2013  -  added support for Electronics Lees 3.2" display shield Rev B on Arduinos
+				fixed a bug that only shows up on some linux-based systems
+				added built-in support for using display shields designed for Arduino Uno on Arduino Mega
+				changed license to CC BY-NC-SA 3.0
+	2.2	01 May 2013  -  added support for ElecFreaks TFT01-5.0 and TFT01-7.0
+				added support for chipKit uC32
+				restructured files slightly
+	2.3	08 May 2013  -  added support for transparent text background
+				fixed a bug in printNumF()
+	2.4	11 May 2013  -  added basic support for multiple display modules from Coldtears
+	2.41	12 May 2013  -  made some changes to facilitate the use of add-on libraries
+	2.42	17 Jun 2013  -  fixed a small bug in drawBitmap()
+				fixed a bug in the 16-bit Arduino Due driver
+	2.5	25 Jul 2013  -  fixed a bug where some lines were 1 pixel too short
+				fixed a bug in the init code for 7" modules that were only visible in portrait mode
+				added basic support for more display modules from Coldtears
+				updated ImageConverter565 to v2.0
+				added ImgConv v1.0 - Command line image converter
+				added manual for image converters
+				fixed some omissions in memorysaver.h
+	2.51	02 Aug 2013  -  updated ImageConverter565 to v2.1
+				fixed a typo in the tools manual name
+	2.6	07 Sep 2013  -  added support for 4 more ElecFreaks display modules
+				added support for Watterott electronics MI0283QT-9A display module
+				fixed a bug in the "Arduino (ARM)/UTFT_Demo_480x272" example
diff --git a/hardware/digistump/sam/libraries/UTouch/License - CC BY-NC-SA 3.0 - Legal.pdf b/hardware/digistump/sam/libraries/UTouch/License - CC BY-NC-SA 3.0 - Legal.pdf
new file mode 100644
index 0000000..ed326c9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTouch/License - CC BY-NC-SA 3.0 - Legal.pdf	
@@ -0,0 +1,336 @@
+Attribution-NonCommercial-ShareAlike 3.0 Unported (CC BY-NC-SA 3.0)
+
+CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE LEGAL SERVICES.
+DISTRIBUTION OF THIS LICENSE DOES NOT CREATE AN ATTORNEY-CLIENT RELATIONSHIP. CREATIVE
+COMMONS PROVIDES THIS INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO
+WARRANTIES REGARDING THE INFORMATION PROVIDED, AND DISCLAIMS LIABILITY FOR DAMAGES
+RESULTING FROM ITS USE.
+
+License
+
+THE WORK (AS DEFINED BELOW) IS PROVIDED UNDER THE TERMS OF THIS CREATIVE
+COMMONS PUBLIC LICENSE ("CCPL" OR "LICENSE"). THE WORK IS PROTECTED BY
+COPYRIGHT AND/OR OTHER APPLICABLE LAW. ANY USE OF THE WORK OTHER THAN AS
+AUTHORIZED UNDER THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
+
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+
diff --git a/hardware/digistump/sam/libraries/UTouch/License - CC BY-NC-SA 3.0 - Summary.pdf b/hardware/digistump/sam/libraries/UTouch/License - CC BY-NC-SA 3.0 - Summary.pdf
new file mode 100644
index 0000000..b35e677
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTouch/License - CC BY-NC-SA 3.0 - Summary.pdf	
@@ -0,0 +1,43 @@
+Attribution-NonCommercial-ShareAlike 3.0 Unported (CC BY-NC-SA 3.0)
+
+You are free:
+
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+
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+
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+        distribute the resulting work only under the same or similar license to
+        this one.
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+
diff --git a/hardware/digistump/sam/libraries/UTouch/UTouch.cpp b/hardware/digistump/sam/libraries/UTouch/UTouch.cpp
new file mode 100644
index 0000000..b7db163
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTouch/UTouch.cpp
@@ -0,0 +1,223 @@
+/*
+  UTouch.cpp - Arduino/chipKit library support for Color TFT LCD Touch screens 
+  Copyright (C)2010-2013 Henning Karlsen. All right reserved
+  
+  Basic functionality of this library are based on the demo-code provided by
+  ITead studio. You can find the latest version of the library at
+  http://www.henningkarlsen.com/electronics
+
+  If you make any modifications or improvements to the code, I would appreciate
+  that you share the code with me so that I might include it in the next release.
+  I can be contacted through http://www.henningkarlsen.com/electronics/contact.php
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the CC BY-NC-SA 3.0 license.
+  Please see the included documents for further information.
+*/
+
+#include "UTouch.h"
+#include "UTouchCD.h"
+
+UTouch::UTouch(byte tclk, byte tcs, byte din, byte dout, byte irq)
+{
+    T_CLK        = tclk;
+    T_CS         = tcs;
+    T_DIN        = din;
+    T_DOUT       = dout;
+    T_IRQ        = irq;
+}
+
+void UTouch::InitTouch(byte orientation)
+{
+	orient					= orientation;
+	_default_orientation	= CAL_S>>31;
+	touch_x_left			= (CAL_X>>14) & 0x3FFF;
+	touch_x_right			= CAL_X & 0x3FFF;
+	touch_y_top				= (CAL_Y>>14) & 0x3FFF;
+	touch_y_bottom			= CAL_Y & 0x3FFF;
+	disp_x_size				= (CAL_S>>12) & 0x0FFF;
+	disp_y_size				= CAL_S & 0x0FFF;
+	prec					= 10;
+
+	pinMode(T_CLK,  OUTPUT);
+    pinMode(T_CS,   OUTPUT);
+    pinMode(T_DIN,  OUTPUT);
+    pinMode(T_DOUT, INPUT);
+    pinMode(T_IRQ,  OUTPUT);
+
+	digitalWrite(T_CS,  HIGH);
+	digitalWrite(T_CLK, HIGH);
+	digitalWrite(T_DIN, HIGH);
+	digitalWrite(T_CLK, HIGH);
+}
+
+void UTouch::touch_WriteData(byte data)
+{
+	byte temp;
+	byte nop;
+
+	temp=data;
+	digitalWrite(T_CLK,LOW);
+
+	for(byte count=0; count<8; count++)
+	{
+		if(temp & 0x80)
+			digitalWrite(T_DIN, HIGH);
+		else
+			digitalWrite(T_DIN, LOW);
+		temp = temp << 1; 
+		digitalWrite(T_CLK, LOW);                
+		nop++;
+		digitalWrite(T_CLK, HIGH);
+		nop++;
+	}
+}
+
+word UTouch::touch_ReadData()
+{
+	byte nop;
+	word data = 0;
+	for(byte count=0; count<12; count++)
+	{
+		data <<= 1;
+		digitalWrite(T_CLK, HIGH);               
+		nop++;
+		digitalWrite(T_CLK, LOW);
+		nop++;
+		if (digitalRead(T_DOUT))
+			data++;
+	}
+	return(data);
+}
+
+void UTouch::read()
+{
+	unsigned long tx=0, temp_x=0;
+	unsigned long ty=0, temp_y=0;
+	int datacount=0;
+
+	digitalWrite(T_CS,LOW);                    
+
+	for (int i=0; imax(touch_x_left, touch_x_right)) or (temp_x==0) or (temp_y>max(touch_y_top, touch_y_bottom)) or (temp_y==0)))
+		{
+			ty+=temp_x;
+			tx+=temp_y;
+			datacount++;
+		}
+	}
+
+	digitalWrite(T_CS,HIGH);
+	if (datacount>0)
+	{
+		if (orient == _default_orientation)
+		{
+			TP_X=tx/datacount;
+			TP_Y=ty/datacount;
+		}
+		else
+		{
+			TP_X=ty/datacount;
+			TP_Y=tx/datacount;
+		}
+	}
+	else
+	{
+		TP_X=-1;
+		TP_Y=-1;
+	}
+}
+
+bool UTouch::dataAvailable()
+{
+	bool avail;
+	pinMode(T_IRQ,  INPUT);
+	avail = !digitalRead(T_IRQ);
+	pinMode(T_IRQ,  OUTPUT);
+	return avail;
+}
+
+int UTouch::getX()
+{
+	long c;
+
+	if (orient == _default_orientation)
+	{
+		c = long(long(TP_X - touch_x_left) * (disp_x_size)) / long(touch_x_right - touch_x_left);
+		if (c<0)
+			c = 0;
+		if (c>disp_x_size)
+			c = disp_x_size;
+	}
+	else
+	{
+		if (_default_orientation == PORTRAIT)
+			c = long(long(TP_X - touch_y_top) * (-disp_y_size)) / long(touch_y_bottom - touch_y_top) + long(disp_y_size);
+		else
+			c = long(long(TP_X - touch_y_top) * (disp_y_size)) / long(touch_y_bottom - touch_y_top);
+		if (c<0)
+			c = 0;
+		if (c>disp_y_size)
+			c = disp_y_size;
+	}
+	return c;
+}
+
+int UTouch::getY()
+{
+	int c;
+
+	if (orient == _default_orientation)
+	{
+		c = long(long(TP_Y - touch_y_top) * (disp_y_size)) / long(touch_y_bottom - touch_y_top);
+		if (c<0)
+			c = 0;
+		if (c>disp_y_size)
+			c = disp_y_size;
+	}
+	else
+	{
+		if (_default_orientation == PORTRAIT)
+			c = long(long(TP_Y - touch_x_left) * (disp_x_size)) / long(touch_x_right - touch_x_left);
+		else
+			c = long(long(TP_Y - touch_x_left) * (-disp_x_size)) / long(touch_x_right - touch_x_left) + long(disp_x_size);
+		if (c<0)
+			c = 0;
+		if (c>disp_x_size)
+			c = disp_x_size;
+	}
+	return c;
+}
+
+void UTouch::setPrecision(byte precision)
+{
+	switch (precision)
+	{
+		case PREC_LOW:
+			prec=1;
+			break;
+		case PREC_MEDIUM:
+			prec=10;
+			break;
+		case PREC_HI:
+			prec=25;
+			break;
+		case PREC_EXTREME:
+			prec=100;
+			break;
+		default:
+			prec=10;
+			break;
+	}
+}
\ No newline at end of file
diff --git a/hardware/digistump/sam/libraries/UTouch/UTouch.h b/hardware/digistump/sam/libraries/UTouch/UTouch.h
new file mode 100644
index 0000000..ad63398
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTouch/UTouch.h
@@ -0,0 +1,62 @@
+/*
+  UTouch.h - Arduino/chipKit library support for Color TFT LCD Touch screens 
+  Copyright (C)2010-2013 Henning Karlsen. All right reserved
+  
+  Basic functionality of this library are based on the demo-code provided by
+  ITead studio. You can find the latest version of the library at
+  http://www.henningkarlsen.com/electronics
+
+  If you make any modifications or improvements to the code, I would appreciate
+  that you share the code with me so that I might include it in the next release.
+  I can be contacted through http://www.henningkarlsen.com/electronics/contact.php
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the CC BY-NC-SA 3.0 license.
+  Please see the included documents for further information.
+*/
+
+#ifndef UTouch_h
+#define UTouch_h
+
+#if defined(ARDUINO) && ARDUINO >= 100
+	#include "Arduino.h"
+#else
+	#include "WProgram.h"
+#endif
+
+#define PORTRAIT			0
+#define LANDSCAPE			1
+
+#define PREC_LOW			1
+#define PREC_MEDIUM			2
+#define PREC_HI				3
+#define PREC_EXTREME		4
+
+class UTouch
+{
+	public:
+		word	TP_X ,TP_Y;
+
+				UTouch(byte tclk, byte tcs, byte tdin, byte dout, byte irq);
+
+		void	InitTouch(byte orientation = LANDSCAPE);
+		void	read();
+		bool	dataAvailable();
+		int		getX();
+		int		getY();
+		void	setPrecision(byte precision);
+    
+    private:
+		byte	T_CLK, T_CS, T_DIN, T_DOUT, T_IRQ;
+		long	_default_orientation;
+		byte	orient;
+		byte	prec;
+		byte	display_model;
+		long	disp_x_size, disp_y_size, default_orientation;
+		long	touch_x_left, touch_x_right, touch_y_top, touch_y_bottom;
+
+		void	touch_WriteData(byte data);
+		word	touch_ReadData();
+};
+
+#endif
\ No newline at end of file
diff --git a/hardware/digistump/sam/libraries/UTouch/UTouch.pdf b/hardware/digistump/sam/libraries/UTouch/UTouch.pdf
new file mode 100644
index 0000000..0706ab6
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTouch/UTouch.pdf
@@ -0,0 +1,136 @@
+     UTouch
+
+Arduino and chipKit Universal TFT touchscreen library
+
+             Manual
+
+http://electronics.henningkarlsen.com  (C)2013 Henning Karlsen
+PREFACE:
+
+This library was made to complement UTFT to provide touch screen functionality.
+
+You can always find the latest version of the library at
+http://electronics.henningkarlsen.com/
+
+If you make any modifications or improvements to the code, I would appreciate that you share
+the code with me so that I might include it in the next release. I can be contacted through
+http://electronics.henningkarlsen.com/contact.php.
+
+For version information, please refer to version.txt.
+
+REGARDING CALIBRATION:
+
+All touch screens will have slight variations. It is therefore important that you calibrate
+your particular touch screen for the best possible performance.
+
+To calibrate your touch screen you will need to run the UTouch_Calibration sketch supplied in
+the examples of the library.
+
+Before you compile and upload the sketch there are a couple of things you must do.
+      1. Make sure you have uncommented the correct section for your development board
+      2. Make sure the UTFT display model code is correct for your display module
+      3. Make sure the TOUCH_ORIENTATION define is correct. You can find a list of the correct
+             parameter for all the tested displays in the UTouch_Supported_display_modules PDF.
+
+Further instructions will be given on screen when you run the sketch.
+
+Remember that if you have more than one touch display module you may have to run the
+calibration on each module.
+
+Some touch screens, espcially the larger ones (4.3†and larger), have some flaws where they
+have problems registering touch near the edges. The calibration sketch tries to take this into
+account when calibrating. Because of this some calibration points takes longer to register.
+
+It is also recommended that you power your Arduino/chipKit using an external power source when
+running the calibration on 4.3†and larger screens.
+
+This library is licensed under a CC BY-NC-SA 3.0 (Creative Commons Attribution-
+NonCommercial-ShareAlike 3.0 Unported) License.
+
+For more information see: http://creativecommons.org/licenses/by-nc-sa/3.0/
+
+UTouch library                                                                   Page 1
+Defined Literals:                           Orientation
+
+For use with InitTouch()            PORTRAIT: 0
+                                  LANDSCAPE: 1
+For use with setPrecision()
+                                              Precision
+
+                                    PREC_LOW: 1
+                              PREC_MEDIUM: 2
+
+                                      PREC_HI: 3
+                             PREC_EXTREME: 4
+
+UTouch library                                           Page 2
+Functions:
+
+                                        UTouch(TCLK, TCS, TDIN, TDOUT, IRQ);
+
+The main class of the interface.
+
+Parameters:  TCLK: Pin for Touch Clock (D_CLK)
+Usage:       TCS: Pin for Touch Chip Select (D_CS)
+             TDIN: Pin for Touch Data input (D_DIN)
+             TDOUT: Pin for Touch Data output (D_OUT)
+             IRQ: Pin for Touch IRQ (DPenirq)
+
+             UTouch myTouch(15,10,14,9,8); // Start an instance of the UTouch class
+
+                                                                                   InitTouch([orientation]);
+
+Initialize the touch screen and set display orientation. If the library is used together with UTFT the orientation should be set to
+the same orientation for both libraries.
+
+Parameters:  orientation: 
+                                    PORTRAIT
+Returns:                            LANDSCAPE (default)
+Usage:
+             Nothing
+             myTouch.InitTouch();// Initialize the touch screen
+
+                                                                                           dataAvailable();
+Check to see if new data from the touch screen is waiting.
+
+Parameters:  None
+Returns:     Boolean: true means data is waiting, otherwise false
+Usage:       check = myTouch.dataAvailable() // See if data is waiting
+
+                                                                                                   read();
+
+Read waiting data from the touch screen. This function should be called if dataAvailable() is true. Use getX() and getY() to get
+the coordinates.
+
+Parameters:  None
+Returns:     Nothing
+Usage:       myTouch.read(); // Read data from touch screen
+Notes:       After calling read(), raw data from the touch screen is available in the variables TP_X and TP_Y. Do
+             not use these if you do not know how to handle the raw data. Use getX() and getY() instead.
+
+                                                                                                   getX();
+Get the x-coordinate of the last position read from the touch screen.
+
+Parameters:  None
+Returns:     Integer
+Usage:       x = myTouch.getX(); // Get the x-coordinate
+
+                                                                                                   getY();
+Get the y-coordinate of the last position read from the touch screen.
+
+Parameters:  None
+Returns:     Integer
+Usage:       y = myTouch.getY(); // Get the y-coordinate
+
+                                        setPrecision(precision);
+
+Set the precision of the touch screen.
+
+Parameters:  precision: PREC_LOW, PREC_MEDIUM, PREC_HI, PREC_EXTREME
+Returns:     Nothing
+Usage:       myTouch.setPrecision(PREC_MEDIUM); // Set precision to medium
+Notes:       Higher precision data will take longer to read, so take care when using PREC_HI or PREC_EXTREME with
+             fast-moving input.
+
+UTouch library                                                                                               Page 3
+
diff --git a/hardware/digistump/sam/libraries/UTouch/UTouchCD.h b/hardware/digistump/sam/libraries/UTouch/UTouchCD.h
new file mode 100644
index 0000000..50bc7e4
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTouch/UTouchCD.h
@@ -0,0 +1,21 @@
+// UTouchCD.h
+// ----------
+//
+// Since there are slight deviations in all touch screens you should run a
+// calibration on your display module. Run the UTouch_Calibration sketch
+// that came with this library and follow the on-screen instructions to
+// update this file.
+//
+// Remember that is you have multiple display modules they will probably 
+// require different calibration data so you should run the calibration
+// every time you switch to another module.
+// You can, of course, store calibration data for all your modules here
+// and comment out the ones you dont need at the moment.
+//
+
+// These calibration settings works with my ITDB02-3.2S.
+// They MIGHT work on your display module, but you should run the
+// calibration sketch anyway.
+#define CAL_X 0x00314ED0UL
+#define CAL_Y 0x03D6C174UL
+#define CAL_S 0x000EF13FUL
diff --git a/hardware/digistump/sam/libraries/UTouch/UTouch_Supported_display_modules.pdf b/hardware/digistump/sam/libraries/UTouch/UTouch_Supported_display_modules.pdf
new file mode 100644
index 0000000..21686c3
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTouch/UTouch_Supported_display_modules.pdf
@@ -0,0 +1,63 @@
+      UTouch
+
+         Arduino and chipKit Universal TFT touchscreen library
+
+Supported display modules
+
+http://electronics.henningkarlsen.com  (C)2013 Henning Karlsen
+These display modules have been tested, and work well with the library.
+
+Supplier:                      ITead Studio                      Notes
+
+Website:                       http://iteadstudio.com/store/     Retired
+Module                         TOUCH_ORIENTATION                 Retired
+
+ITDB02-2.2                     PORTRAIT                          Retired
+ITDB02-2.4                     PORTRAIT
+ITDB02-2.4D                    PORTRAIT                          Retired
+ITDB02-2.4E                    PORTRAIT                          Retired
+ITDB02-2.5H                    LANDSCAPE
+ITDB02-2.8                     PORTRAIT
+ITDB02-3.2                     PORTRAIT
+ITDB02-3.2WC                   PORTRAIT
+ITDB02-3.2S                    PORTRAIT
+ITDB02-3.2WD                   PORTRAIT
+ITDB02-4.3                     LANDSCAPE
+ITDB02-5.0                     LANDSCAPE
+
+Supplier:                      ElecFreaks                        Notes
+
+Website:                       http://www.elecfreaks.com/store/  Retired
+Module                         TOUCH_ORIENTATION
+
+TFT01-2.4                      PORTRAIT
+TFT01-3.2                      PORTRAIT
+TFT01-3.2W                     PORTRAIT
+TFT01-3.2WD                    PORTRAIT
+TFT01-5.0                      LANDSCAPE
+TFT01-7.0                      LANDSCAPE
+
+Supplier:                      Coldtears Electronics
+
+Website:                       http://stores.ebay.com/coldtears-electronics-store
+Module
+                               TOUCH_ORIENTATION                 Notes
+3.2" TFT LCD Module
+3.2" (480x320) TFT LCD Module  PORTRAIT
+5.0" TFT LCD Module
+7.0" TFT LCD Module            PORTRAIT
+
+                               LANDSCAPE
+
+                               LANDSCAPE
+
+Unlisted display modules:
+
+If your display module isn’t listed here it might still work fine. To find the
+TOUCH_ORIENTATION for your module you must look for the Flat Flex Cable (FFC) from the
+touch screen. It is usually a 4 wire FFC. If the FFC is on one of the short sides it
+is highly likely that the TOUCH_ORIENTATION should be PORTRAIT. If it is on one of the
+long sides you should probably use LANDSCAPE as TOUCH_ORIENTATION.
+
+                                                                          Page 1
+
diff --git a/hardware/digistump/sam/libraries/UTouch/examples/Arduino/UTouch_ButtonTest/UTouch_ButtonTest.pde b/hardware/digistump/sam/libraries/UTouch/examples/Arduino/UTouch_ButtonTest/UTouch_ButtonTest.pde
new file mode 100644
index 0000000..f43498f
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTouch/examples/Arduino/UTouch_ButtonTest/UTouch_ButtonTest.pde
@@ -0,0 +1,236 @@
+// UTouch_ButtonTest (C)2010-2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a quick demo of how create and use buttons.
+//
+// This program requires the UTFT library.
+//
+// It is assumed that the display module is connected to an
+// appropriate shield or that you know how to change the pin 
+// numbers in the setup.
+//
+
+#include 
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t BigFont[];
+
+// Uncomment the next two lines for the Arduino 2009/UNO
+//UTFT        myGLCD(ITDB24D,19,18,17,16);   // Remember to change the model parameter to suit your display module!
+//UTouch      myTouch(15,10,14,9,8);
+
+// Uncomment the next two lines for the Arduino Mega
+UTFT        myGLCD(ITDB32S, 38,39,40,41);   // Remember to change the model parameter to suit your display module!
+UTouch      myTouch(6,5,4,3,2);
+
+int x, y;
+char stCurrent[20]="";
+int stCurrentLen=0;
+char stLast[20]="";
+
+/*************************
+**   Custom functions   **
+*************************/
+
+void drawButtons()
+{
+// Draw the upper row of buttons
+  for (x=0; x<5; x++)
+  {
+    myGLCD.setColor(0, 0, 255);
+    myGLCD.fillRoundRect (10+(x*60), 10, 60+(x*60), 60);
+    myGLCD.setColor(255, 255, 255);
+    myGLCD.drawRoundRect (10+(x*60), 10, 60+(x*60), 60);
+    myGLCD.printNumI(x+1, 27+(x*60), 27);
+  }
+// Draw the center row of buttons
+  for (x=0; x<5; x++)
+  {
+    myGLCD.setColor(0, 0, 255);
+    myGLCD.fillRoundRect (10+(x*60), 70, 60+(x*60), 120);
+    myGLCD.setColor(255, 255, 255);
+    myGLCD.drawRoundRect (10+(x*60), 70, 60+(x*60), 120);
+    if (x<4)
+      myGLCD.printNumI(x+6, 27+(x*60), 87);
+  }
+  myGLCD.print("0", 267, 87);
+// Draw the lower row of buttons
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.fillRoundRect (10, 130, 150, 180);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.drawRoundRect (10, 130, 150, 180);
+  myGLCD.print("Clear", 40, 147);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.fillRoundRect (160, 130, 300, 180);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.drawRoundRect (160, 130, 300, 180);
+  myGLCD.print("Enter", 190, 147);
+  myGLCD.setBackColor (0, 0, 0);
+}
+
+void updateStr(int val)
+{
+  if (stCurrentLen<20)
+  {
+    stCurrent[stCurrentLen]=val;
+    stCurrent[stCurrentLen+1]='\0';
+    stCurrentLen++;
+    myGLCD.setColor(0, 255, 0);
+    myGLCD.print(stCurrent, LEFT, 224);
+  }
+  else
+  {
+    myGLCD.setColor(255, 0, 0);
+    myGLCD.print("BUFFER FULL!", CENTER, 192);
+    delay(500);
+    myGLCD.print("            ", CENTER, 192);
+    delay(500);
+    myGLCD.print("BUFFER FULL!", CENTER, 192);
+    delay(500);
+    myGLCD.print("            ", CENTER, 192);
+    myGLCD.setColor(0, 255, 0);
+  }
+}
+
+// Draw a red frame while a button is touched
+void waitForIt(int x1, int y1, int x2, int y2)
+{
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.drawRoundRect (x1, y1, x2, y2);
+  while (myTouch.dataAvailable())
+    myTouch.read();
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.drawRoundRect (x1, y1, x2, y2);
+}
+
+/*************************
+**  Required functions  **
+*************************/
+
+void setup()
+{
+// Initial setup
+  myGLCD.InitLCD();
+  myGLCD.clrScr();
+
+  myTouch.InitTouch();
+  myTouch.setPrecision(PREC_MEDIUM);
+
+  myGLCD.setFont(BigFont);
+  myGLCD.setBackColor(0, 0, 255);
+  drawButtons();  
+}
+
+void loop()
+{
+  while (true)
+  {
+    if (myTouch.dataAvailable())
+    {
+      myTouch.read();
+      x=myTouch.getX();
+      y=myTouch.getY();
+      
+      if ((y>=10) && (y<=60))  // Upper row
+      {
+        if ((x>=10) && (x<=60))  // Button: 1
+        {
+          waitForIt(10, 10, 60, 60);
+          updateStr('1');
+        }
+        if ((x>=70) && (x<=120))  // Button: 2
+        {
+          waitForIt(70, 10, 120, 60);
+          updateStr('2');
+        }
+        if ((x>=130) && (x<=180))  // Button: 3
+        {
+          waitForIt(130, 10, 180, 60);
+          updateStr('3');
+        }
+        if ((x>=190) && (x<=240))  // Button: 4
+        {
+          waitForIt(190, 10, 240, 60);
+          updateStr('4');
+        }
+        if ((x>=250) && (x<=300))  // Button: 5
+        {
+          waitForIt(250, 10, 300, 60);
+          updateStr('5');
+        }
+      }
+
+      if ((y>=70) && (y<=120))  // Center row
+      {
+        if ((x>=10) && (x<=60))  // Button: 6
+        {
+          waitForIt(10, 70, 60, 120);
+          updateStr('6');
+        }
+        if ((x>=70) && (x<=120))  // Button: 7
+        {
+          waitForIt(70, 70, 120, 120);
+          updateStr('7');
+        }
+        if ((x>=130) && (x<=180))  // Button: 8
+        {
+          waitForIt(130, 70, 180, 120);
+          updateStr('8');
+        }
+        if ((x>=190) && (x<=240))  // Button: 9
+        {
+          waitForIt(190, 70, 240, 120);
+          updateStr('9');
+        }
+        if ((x>=250) && (x<=300))  // Button: 0
+        {
+          waitForIt(250, 70, 300, 120);
+          updateStr('0');
+        }
+      }
+
+      if ((y>=130) && (y<=180))  // Upper row
+      {
+        if ((x>=10) && (x<=150))  // Button: Clear
+        {
+          waitForIt(10, 130, 150, 180);
+          stCurrent[0]='\0';
+          stCurrentLen=0;
+          myGLCD.setColor(0, 0, 0);
+          myGLCD.fillRect(0, 224, 319, 239);
+        }
+        if ((x>=160) && (x<=300))  // Button: Enter
+        {
+          waitForIt(160, 130, 300, 180);
+          if (stCurrentLen>0)
+          {
+            for (x=0; x
+#include 
+
+// Define the orientation of the touch screen. Further 
+// information can be found in the instructions.
+#define TOUCH_ORIENTATION  PORTRAIT
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next two lines for the Arduino 2009/UNO
+//UTFT        myGLCD(ITDB24D,19,18,17,16);   // Remember to change the model parameter to suit your display module!
+//UTouch      myTouch(15,10,14,9,8);
+
+// Uncomment the next two lines for the Arduino Mega
+UTFT        myGLCD(ITDB32S,38,39,40,41);   // Remember to change the model parameter to suit your display module!
+UTouch      myTouch(6,5,4,3,2);
+
+// ************************************
+// DO NOT EDIT ANYTHING BELOW THIS LINE
+// ************************************
+uint32_t cx, cy;
+uint32_t rx[10], ry[10];
+uint32_t clx, crx, cty, cby;
+float px, py;
+int dispx, dispy, text_y_center;
+uint32_t calx, caly, cals;
+char buf[13];
+
+void setup()
+{
+  myGLCD.InitLCD();
+  myGLCD.clrScr();
+  myGLCD.setFont(SmallFont);
+
+  myTouch.InitTouch(TOUCH_ORIENTATION);
+  myTouch.setPrecision(PREC_LOW);
+  dispx=myGLCD.getDisplayXSize();
+  dispy=myGLCD.getDisplayYSize();
+  text_y_center=(dispy/2)-6;
+}
+
+void drawCrossHair(int x, int y)
+{
+  myGLCD.drawRect(x-10, y-10, x+10, y+10);
+  myGLCD.drawLine(x-5, y, x+5, y);
+  myGLCD.drawLine(x, y-5, x, y+5);
+}
+
+void readCoordinates()
+{
+  int iter = 2000;
+  int cnt = 0;
+  uint32_t tx=0;
+  uint32_t ty=0;
+  boolean OK = false;
+  
+  while (OK == false)
+  {
+    myGLCD.setColor(255, 255, 255);
+    myGLCD.print("*  PRESS  *", CENTER, text_y_center);
+    while (myTouch.dataAvailable() == false) {}
+    myGLCD.print("*  HOLD!  *", CENTER, text_y_center);
+    while ((myTouch.dataAvailable() == true) && (cnt=iter)
+    {
+      OK = true;
+    }
+    else
+    {
+      tx = 0;
+      ty = 0;
+      cnt = 0;
+    }
+  }
+
+  cx = tx / iter;
+  cy = ty / iter;
+
+}
+
+void calibrate(int x, int y, int i)
+{
+  myGLCD.setColor(255, 255, 255);
+  drawCrossHair(x,y);
+  myGLCD.setBackColor(255, 0, 0);
+  readCoordinates();
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.print("* RELEASE *", CENTER, text_y_center);
+  myGLCD.setColor(80, 80, 80);
+  drawCrossHair(x,y);
+  rx[i]=cx;
+  ry[i]=cy;
+  while (myTouch.dataAvailable() == true)
+  {
+    myTouch.read();
+  }
+}
+
+void waitForTouch()
+{
+  while (myTouch.dataAvailable() == true)
+  {
+    myTouch.read();
+  }
+  while (myTouch.dataAvailable() == false) {}
+  while (myTouch.dataAvailable() == true)
+  {
+    myTouch.read();
+  }
+}
+
+void toHex(uint32_t num)
+{
+  buf[0] = '0';
+  buf[1] = 'x';
+  buf[10] = 'U';
+  buf[11] = 'L';
+  buf[12] = 0;
+  for (int zz=9; zz>1; zz--)
+  {
+    if ((num & 0xF) > 9)
+      buf[zz] = (num & 0xF) + 55;
+    else
+      buf[zz] = (num & 0xF) + 48;
+    num=num>>4;
+  }
+}
+
+void startup()
+{
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, dispx-1, 13);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.drawLine(0, 14, dispx-1, 14);
+  myGLCD.print("UTouch Calibration", CENTER, 1);
+  myGLCD.setBackColor(0, 0, 0);
+
+  if (dispx==220)
+  {  
+    myGLCD.print("Use a stylus or something", LEFT, 30);
+    myGLCD.print("similar to touch as close", LEFT, 42);
+    myGLCD.print("to the center of the", LEFT, 54);
+    myGLCD.print("highlighted crosshair as", LEFT, 66);
+    myGLCD.print("possible. Keep as still as", LEFT, 78);
+    myGLCD.print("possible and keep holding", LEFT, 90);
+    myGLCD.print("until the highlight is", LEFT, 102);
+    myGLCD.print("removed. Repeat for all", LEFT, 114);
+    myGLCD.print("crosshairs in sequence.", LEFT, 126);
+    myGLCD.print("Touch screen to continue", CENTER, 162);
+  }
+  else
+  {
+    myGLCD.print("INSTRUCTIONS", CENTER, 30);
+    myGLCD.print("Use a stylus or something similar to", LEFT, 50);
+    myGLCD.print("touch as close to the center of the", LEFT, 62);
+    myGLCD.print("highlighted crosshair as possible. Keep", LEFT, 74);
+    myGLCD.print("as still as possible and keep holding", LEFT, 86);
+    myGLCD.print("until the highlight is removed. Repeat", LEFT, 98);
+    myGLCD.print("for all crosshairs in sequence.", LEFT, 110);
+
+    myGLCD.print("Further instructions will be displayed", LEFT, 134);
+    myGLCD.print("when the calibration is complete.", LEFT, 146);
+
+    myGLCD.print("Do NOT use your finger as a calibration", LEFT, 170);
+    myGLCD.print("stylus or the result WILL BE imprecise.", LEFT, 182);
+
+    myGLCD.print("Touch screen to continue", CENTER, 226);
+  }
+
+  waitForTouch();
+  myGLCD.clrScr();
+}
+
+void done()
+{
+  myGLCD.clrScr();
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, dispx-1, 13);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.drawLine(0, 14, dispx-1, 14);
+  myGLCD.print("UTouch Calibration", CENTER, 1);
+  myGLCD.setBackColor(0, 0, 0);
+  
+  if (dispx==220)
+  {  
+    myGLCD.print("To use the new calibration", LEFT, 30);
+    myGLCD.print("settings you must edit the", LEFT, 42);
+    myGLCD.setColor(160, 160, 255);
+    myGLCD.print("UTouchCD.h", LEFT, 54);
+    myGLCD.setColor(255, 255, 255);
+    myGLCD.print("file and change", 88, 54);
+    myGLCD.print("the following values. The", LEFT, 66);
+    myGLCD.print("values are located right", LEFT, 78);
+    myGLCD.print("below the opening comment.", LEFT, 90);
+    myGLCD.print("CAL_X", LEFT, 110);
+    myGLCD.print("CAL_Y", LEFT, 122);
+    myGLCD.print("CAL_S", LEFT, 134);
+    toHex(calx);
+    myGLCD.print(buf, 75, 110);
+    toHex(caly);
+    myGLCD.print(buf, 75, 122);
+    toHex(cals);
+    myGLCD.print(buf, 75, 134);
+  }
+  else
+  {  
+    myGLCD.print("CALIBRATION COMPLETE", CENTER, 30);
+    myGLCD.print("To use the new calibration", LEFT, 50);
+    myGLCD.print("settings you must edit the", LEFT, 62);
+    myGLCD.setColor(160, 160, 255);
+    myGLCD.print("UTouchCD.h", LEFT, 74);
+    myGLCD.setColor(255, 255, 255);
+    myGLCD.print("file and change", 88, 74);
+    myGLCD.print("the following values.", LEFT, 86);
+    myGLCD.print("The values are located right", LEFT, 98);
+    myGLCD.print("below the opening comment in", LEFT, 110);
+    myGLCD.print("the file.", LEFT, 122);
+    myGLCD.print("CAL_X", LEFT, 150);
+    myGLCD.print("CAL_Y", LEFT, 162);
+    myGLCD.print("CAL_S", LEFT, 174);
+
+    toHex(calx);
+    myGLCD.print(buf, 75, 150);
+    toHex(caly);
+    myGLCD.print(buf, 75, 162);
+    toHex(cals);
+    myGLCD.print(buf, 75, 174);
+  }
+  
+}
+
+void loop()
+{
+  startup();
+  
+  myGLCD.setColor(80, 80, 80);
+  drawCrossHair(dispx-11, 10);
+  drawCrossHair(dispx/2, 10);
+  drawCrossHair(10, 10);
+  drawCrossHair(dispx-11, dispy/2);
+  drawCrossHair(10, dispy/2);
+  drawCrossHair(dispx-11, dispy-11);
+  drawCrossHair(dispx/2, dispy-11);
+  drawCrossHair(10, dispy-11);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("***********", CENTER, text_y_center-12);
+  myGLCD.print("***********", CENTER, text_y_center+12);
+
+  calibrate(10, 10, 0);
+  calibrate(10, dispy/2, 1);
+  calibrate(10, dispy-11, 2);
+  calibrate(dispx/2, 10, 3);
+  calibrate(dispx/2, dispy-11, 4);
+  calibrate(dispx-11, 10, 5);
+  calibrate(dispx-11, dispy/2, 6);
+  calibrate(dispx-11, dispy-11, 7);
+  
+  if (TOUCH_ORIENTATION == LANDSCAPE)
+    cals=(long(dispx-1)<<12)+(dispy-1);
+  else
+    cals=(long(dispy-1)<<12)+(dispx-1);
+
+  if (TOUCH_ORIENTATION == PORTRAIT)
+    px = abs(((float(rx[2]+rx[4]+rx[7])/3)-(float(rx[0]+rx[3]+rx[5])/3))/(dispy-20));  // PORTRAIT
+  else
+    px = abs(((float(rx[5]+rx[6]+rx[7])/3)-(float(rx[0]+rx[1]+rx[2])/3))/(dispy-20));  // LANDSCAPE
+
+  if (TOUCH_ORIENTATION == PORTRAIT)
+  {
+    clx = (((rx[0]+rx[3]+rx[5])/3));  // PORTRAIT
+    crx = (((rx[2]+rx[4]+rx[7])/3));  // PORTRAIT
+  }
+  else
+  {
+    clx = (((rx[0]+rx[1]+rx[2])/3));  // LANDSCAPE
+    crx = (((rx[5]+rx[6]+rx[7])/3));  // LANDSCAPE
+  }
+  if (clx
+#include 
+
+// Uncomment the next two lines for the Arduino 2009/UNO
+//UTFT        myGLCD(ITDB24D,19,18,17,16);   // Remember to change the model parameter to suit your display module!
+//UTouch      myTouch(15,10,14,9,8);
+
+// Uncomment the next two lines for the Arduino Mega
+UTFT        myGLCD(ITDB32S, 38,39,40,41);   // Remember to change the model parameter to suit your display module!
+UTouch      myTouch(6,5,4,3,2);
+
+void setup()
+{
+  myGLCD.InitLCD();
+  myGLCD.clrScr();
+
+  myTouch.InitTouch();
+  myTouch.setPrecision(PREC_MEDIUM);
+}
+
+void loop()
+{
+  long x, y;
+  
+  while (myTouch.dataAvailable() == true)
+  {
+    myTouch.read();
+    x = myTouch.getX();
+    y = myTouch.getY();
+    if ((x!=-1) and (y!=-1))
+    {
+      myGLCD.drawPixel (x, y);
+    }
+  }
+}
+
diff --git a/hardware/digistump/sam/libraries/UTouch/examples/chipKit/UTouch_ButtonTest/UTouch_ButtonTest.pde b/hardware/digistump/sam/libraries/UTouch/examples/chipKit/UTouch_ButtonTest/UTouch_ButtonTest.pde
new file mode 100644
index 0000000..1344e86
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTouch/examples/chipKit/UTouch_ButtonTest/UTouch_ButtonTest.pde
@@ -0,0 +1,236 @@
+// UTouch_ButtonTest (C)2010-2012 Henning Karlsen
+// web: http://www.henningkarlsen.com/electronics
+//
+// This program is a quick demo of how create and use buttons.
+//
+// This program requires the UTFT library.
+//
+// It is assumed that the display module is connected to an
+// appropriate shield or that you know how to change the pin 
+// numbers in the setup.
+//
+
+#include 
+#include 
+
+// Declare which fonts we will be using
+extern uint8_t BigFont[];
+
+// Uncomment the next line for chipKit Uno32
+UTFT        myGLCD(ITDB24D,34,35,36,37);   // Remember to change the model parameter to suit your display module!
+UTouch      myTouch(20,21,22,23,24);
+
+// Uncomment the next line for chipKit Max32
+//UTFT        myGLCD(ITDB32S,82,83,84,85);   // Remember to change the model parameter to suit your display module!
+//UTouch      myTouch(62,63,64,65,66);
+
+int x, y;
+char stCurrent[20]="";
+int stCurrentLen=0;
+char stLast[20]="";
+
+/*************************
+**   Custom functions   **
+*************************/
+
+void drawButtons()
+{
+// Draw the upper row of buttons
+  for (x=0; x<5; x++)
+  {
+    myGLCD.setColor(0, 0, 255);
+    myGLCD.fillRoundRect (10+(x*60), 10, 60+(x*60), 60);
+    myGLCD.setColor(255, 255, 255);
+    myGLCD.drawRoundRect (10+(x*60), 10, 60+(x*60), 60);
+    myGLCD.printNumI(x+1, 27+(x*60), 27);
+  }
+// Draw the center row of buttons
+  for (x=0; x<5; x++)
+  {
+    myGLCD.setColor(0, 0, 255);
+    myGLCD.fillRoundRect (10+(x*60), 70, 60+(x*60), 120);
+    myGLCD.setColor(255, 255, 255);
+    myGLCD.drawRoundRect (10+(x*60), 70, 60+(x*60), 120);
+    if (x<4)
+      myGLCD.printNumI(x+6, 27+(x*60), 87);
+  }
+  myGLCD.print("0", 267, 87);
+// Draw the lower row of buttons
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.fillRoundRect (10, 130, 150, 180);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.drawRoundRect (10, 130, 150, 180);
+  myGLCD.print("Clear", 40, 147);
+  myGLCD.setColor(0, 0, 255);
+  myGLCD.fillRoundRect (160, 130, 300, 180);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.drawRoundRect (160, 130, 300, 180);
+  myGLCD.print("Enter", 190, 147);
+  myGLCD.setBackColor (0, 0, 0);
+}
+
+void updateStr(int val)
+{
+  if (stCurrentLen<20)
+  {
+    stCurrent[stCurrentLen]=val;
+    stCurrent[stCurrentLen+1]='\0';
+    stCurrentLen++;
+    myGLCD.setColor(0, 255, 0);
+    myGLCD.print(stCurrent, LEFT, 224);
+  }
+  else
+  {
+    myGLCD.setColor(255, 0, 0);
+    myGLCD.print("BUFFER FULL!", CENTER, 192);
+    delay(500);
+    myGLCD.print("            ", CENTER, 192);
+    delay(500);
+    myGLCD.print("BUFFER FULL!", CENTER, 192);
+    delay(500);
+    myGLCD.print("            ", CENTER, 192);
+    myGLCD.setColor(0, 255, 0);
+  }
+}
+
+// Draw a red frame while a button is touched
+void waitForIt(int x1, int y1, int x2, int y2)
+{
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.drawRoundRect (x1, y1, x2, y2);
+  while (myTouch.dataAvailable())
+    myTouch.read();
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.drawRoundRect (x1, y1, x2, y2);
+}
+
+/*************************
+**  Required functions  **
+*************************/
+
+void setup()
+{
+// Initial setup
+  myGLCD.InitLCD();
+  myGLCD.clrScr();
+
+  myTouch.InitTouch();
+  myTouch.setPrecision(PREC_MEDIUM);
+
+  myGLCD.setFont(BigFont);
+  myGLCD.setBackColor(0, 0, 255);
+  drawButtons();  
+}
+
+void loop()
+{
+  while (true)
+  {
+    if (myTouch.dataAvailable())
+    {
+      myTouch.read();
+      x=myTouch.getX();
+      y=myTouch.getY();
+      
+      if ((y>=10) && (y<=60))  // Upper row
+      {
+        if ((x>=10) && (x<=60))  // Button: 1
+        {
+          waitForIt(10, 10, 60, 60);
+          updateStr('1');
+        }
+        if ((x>=70) && (x<=120))  // Button: 2
+        {
+          waitForIt(70, 10, 120, 60);
+          updateStr('2');
+        }
+        if ((x>=130) && (x<=180))  // Button: 3
+        {
+          waitForIt(130, 10, 180, 60);
+          updateStr('3');
+        }
+        if ((x>=190) && (x<=240))  // Button: 4
+        {
+          waitForIt(190, 10, 240, 60);
+          updateStr('4');
+        }
+        if ((x>=250) && (x<=300))  // Button: 5
+        {
+          waitForIt(250, 10, 300, 60);
+          updateStr('5');
+        }
+      }
+
+      if ((y>=70) && (y<=120))  // Center row
+      {
+        if ((x>=10) && (x<=60))  // Button: 6
+        {
+          waitForIt(10, 70, 60, 120);
+          updateStr('6');
+        }
+        if ((x>=70) && (x<=120))  // Button: 7
+        {
+          waitForIt(70, 70, 120, 120);
+          updateStr('7');
+        }
+        if ((x>=130) && (x<=180))  // Button: 8
+        {
+          waitForIt(130, 70, 180, 120);
+          updateStr('8');
+        }
+        if ((x>=190) && (x<=240))  // Button: 9
+        {
+          waitForIt(190, 70, 240, 120);
+          updateStr('9');
+        }
+        if ((x>=250) && (x<=300))  // Button: 0
+        {
+          waitForIt(250, 70, 300, 120);
+          updateStr('0');
+        }
+      }
+
+      if ((y>=130) && (y<=180))  // Upper row
+      {
+        if ((x>=10) && (x<=150))  // Button: Clear
+        {
+          waitForIt(10, 130, 150, 180);
+          stCurrent[0]='\0';
+          stCurrentLen=0;
+          myGLCD.setColor(0, 0, 0);
+          myGLCD.fillRect(0, 224, 319, 239);
+        }
+        if ((x>=160) && (x<=300))  // Button: Enter
+        {
+          waitForIt(160, 130, 300, 180);
+          if (stCurrentLen>0)
+          {
+            for (x=0; x
+#include 
+
+// Define the orientation of the touch screen. Further 
+// information can be found in the instructions.
+#define TOUCH_ORIENTATION  PORTRAIT
+
+// Declare which fonts we will be using
+extern uint8_t SmallFont[];
+
+// Uncomment the next line for chipKit Uno32
+UTFT        myGLCD(ITDB24D,34,35,36,37);   // Remember to change the model parameter to suit your display module!
+UTouch      myTouch(20,21,22,23,24);
+
+// Uncomment the next line for chipKit Max32
+//UTFT        myGLCD(ITDB32S,82,83,84,85);   // Remember to change the model parameter to suit your display module!
+//UTouch      myTouch(62,63,64,65,66);
+
+// ************************************
+// DO NOT EDIT ANYTHING BELOW THIS LINE
+// ************************************
+uint32_t cx, cy;
+uint32_t rx[10], ry[10];
+uint32_t clx, crx, cty, cby;
+float px, py;
+int dispx, dispy, text_y_center;
+uint32_t calx, caly, cals;
+char buf[13];
+
+void setup()
+{
+  myGLCD.InitLCD();
+  myGLCD.clrScr();
+  myGLCD.setFont(SmallFont);
+
+  myTouch.InitTouch(TOUCH_ORIENTATION);
+  myTouch.setPrecision(PREC_LOW);
+  dispx=myGLCD.getDisplayXSize();
+  dispy=myGLCD.getDisplayYSize();
+  text_y_center=(dispy/2)-6;
+}
+
+void drawCrossHair(int x, int y)
+{
+  myGLCD.drawRect(x-10, y-10, x+10, y+10);
+  myGLCD.drawLine(x-5, y, x+5, y);
+  myGLCD.drawLine(x, y-5, x, y+5);
+}
+
+void readCoordinates()
+{
+  int iter = 2000;
+  int cnt = 0;
+  uint32_t tx=0;
+  uint32_t ty=0;
+  boolean OK = false;
+  
+  while (OK == false)
+  {
+    myGLCD.setColor(255, 255, 255);
+    myGLCD.print("*  PRESS  *", CENTER, text_y_center);
+    while (myTouch.dataAvailable() == false) {}
+    myGLCD.print("*  HOLD!  *", CENTER, text_y_center);
+    while ((myTouch.dataAvailable() == true) && (cnt=iter)
+    {
+      OK = true;
+    }
+    else
+    {
+      tx = 0;
+      ty = 0;
+      cnt = 0;
+    }
+  }
+
+  cx = tx / iter;
+  cy = ty / iter;
+
+}
+
+void calibrate(int x, int y, int i)
+{
+  myGLCD.setColor(255, 255, 255);
+  drawCrossHair(x,y);
+  myGLCD.setBackColor(255, 0, 0);
+  readCoordinates();
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.print("* RELEASE *", CENTER, text_y_center);
+  myGLCD.setColor(80, 80, 80);
+  drawCrossHair(x,y);
+  rx[i]=cx;
+  ry[i]=cy;
+  while (myTouch.dataAvailable() == true)
+  {
+    myTouch.read();
+  }
+}
+
+void waitForTouch()
+{
+  while (myTouch.dataAvailable() == true)
+  {
+    myTouch.read();
+  }
+  while (myTouch.dataAvailable() == false) {}
+  while (myTouch.dataAvailable() == true)
+  {
+    myTouch.read();
+  }
+}
+
+void toHex(uint32_t num)
+{
+  buf[0] = '0';
+  buf[1] = 'x';
+  buf[10] = 'U';
+  buf[11] = 'L';
+  buf[12] = 0;
+  for (int zz=9; zz>1; zz--)
+  {
+    if ((num & 0xF) > 9)
+      buf[zz] = (num & 0xF) + 55;
+    else
+      buf[zz] = (num & 0xF) + 48;
+    num=num>>4;
+  }
+}
+
+void startup()
+{
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, dispx-1, 13);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.drawLine(0, 14, dispx-1, 14);
+  myGLCD.print("UTouch Calibration", CENTER, 1);
+  myGLCD.setBackColor(0, 0, 0);
+
+  if (dispx==220)
+  {  
+    myGLCD.print("Use a stylus or something", LEFT, 30);
+    myGLCD.print("similar to touch as close", LEFT, 42);
+    myGLCD.print("to the center of the", LEFT, 54);
+    myGLCD.print("highlighted crosshair as", LEFT, 66);
+    myGLCD.print("possible. Keep as still as", LEFT, 78);
+    myGLCD.print("possible and keep holding", LEFT, 90);
+    myGLCD.print("until the highlight is", LEFT, 102);
+    myGLCD.print("removed. Repeat for all", LEFT, 114);
+    myGLCD.print("crosshairs in sequence.", LEFT, 126);
+    myGLCD.print("Touch screen to continue", CENTER, 162);
+  }
+  else
+  {
+    myGLCD.print("INSTRUCTIONS", CENTER, 30);
+    myGLCD.print("Use a stylus or something similar to", LEFT, 50);
+    myGLCD.print("touch as close to the center of the", LEFT, 62);
+    myGLCD.print("highlighted crosshair as possible. Keep", LEFT, 74);
+    myGLCD.print("as still as possible and keep holding", LEFT, 86);
+    myGLCD.print("until the highlight is removed. Repeat", LEFT, 98);
+    myGLCD.print("for all crosshairs in sequence.", LEFT, 110);
+
+    myGLCD.print("Further instructions will be displayed", LEFT, 134);
+    myGLCD.print("when the calibration is complete.", LEFT, 146);
+
+    myGLCD.print("Do NOT use your finger as a calibration", LEFT, 170);
+    myGLCD.print("stylus or the result WILL BE imprecise.", LEFT, 182);
+
+    myGLCD.print("Touch screen to continue", CENTER, 226);
+  }
+
+  waitForTouch();
+  myGLCD.clrScr();
+}
+
+void done()
+{
+  myGLCD.clrScr();
+  myGLCD.setColor(255, 0, 0);
+  myGLCD.fillRect(0, 0, dispx-1, 13);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.drawLine(0, 14, dispx-1, 14);
+  myGLCD.print("UTouch Calibration", CENTER, 1);
+  myGLCD.setBackColor(0, 0, 0);
+  
+  if (dispx==220)
+  {  
+    myGLCD.print("To use the new calibration", LEFT, 30);
+    myGLCD.print("settings you must edit the", LEFT, 42);
+    myGLCD.setColor(160, 160, 255);
+    myGLCD.print("UTouchCD.h", LEFT, 54);
+    myGLCD.setColor(255, 255, 255);
+    myGLCD.print("file and change", 88, 54);
+    myGLCD.print("the following values. The", LEFT, 66);
+    myGLCD.print("values are located right", LEFT, 78);
+    myGLCD.print("below the opening comment.", LEFT, 90);
+    myGLCD.print("CAL_X", LEFT, 110);
+    myGLCD.print("CAL_Y", LEFT, 122);
+    myGLCD.print("CAL_S", LEFT, 134);
+    toHex(calx);
+    myGLCD.print(buf, 75, 110);
+    toHex(caly);
+    myGLCD.print(buf, 75, 122);
+    toHex(cals);
+    myGLCD.print(buf, 75, 134);
+  }
+  else
+  {  
+    myGLCD.print("CALIBRATION COMPLETE", CENTER, 30);
+    myGLCD.print("To use the new calibration", LEFT, 50);
+    myGLCD.print("settings you must edit the", LEFT, 62);
+    myGLCD.setColor(160, 160, 255);
+    myGLCD.print("UTouchCD.h", LEFT, 74);
+    myGLCD.setColor(255, 255, 255);
+    myGLCD.print("file and change", 88, 74);
+    myGLCD.print("the following values.", LEFT, 86);
+    myGLCD.print("The values are located right", LEFT, 98);
+    myGLCD.print("below the opening comment in", LEFT, 110);
+    myGLCD.print("the file.", LEFT, 122);
+    myGLCD.print("CAL_X", LEFT, 150);
+    myGLCD.print("CAL_Y", LEFT, 162);
+    myGLCD.print("CAL_S", LEFT, 174);
+
+    toHex(calx);
+    myGLCD.print(buf, 75, 150);
+    toHex(caly);
+    myGLCD.print(buf, 75, 162);
+    toHex(cals);
+    myGLCD.print(buf, 75, 174);
+  }
+  
+}
+
+void loop()
+{
+  startup();
+  
+  myGLCD.setColor(80, 80, 80);
+  drawCrossHair(dispx-11, 10);
+  drawCrossHair(dispx/2, 10);
+  drawCrossHair(10, 10);
+  drawCrossHair(dispx-11, dispy/2);
+  drawCrossHair(10, dispy/2);
+  drawCrossHair(dispx-11, dispy-11);
+  drawCrossHair(dispx/2, dispy-11);
+  drawCrossHair(10, dispy-11);
+  myGLCD.setColor(255, 255, 255);
+  myGLCD.setBackColor(255, 0, 0);
+  myGLCD.print("***********", CENTER, text_y_center-12);
+  myGLCD.print("***********", CENTER, text_y_center+12);
+
+  calibrate(10, 10, 0);
+  calibrate(10, dispy/2, 1);
+  calibrate(10, dispy-11, 2);
+  calibrate(dispx/2, 10, 3);
+  calibrate(dispx/2, dispy-11, 4);
+  calibrate(dispx-11, 10, 5);
+  calibrate(dispx-11, dispy/2, 6);
+  calibrate(dispx-11, dispy-11, 7);
+  
+  if (TOUCH_ORIENTATION == LANDSCAPE)
+    cals=(long(dispx-1)<<12)+(dispy-1);
+  else
+    cals=(long(dispy-1)<<12)+(dispx-1);
+
+  if (TOUCH_ORIENTATION == PORTRAIT)
+    px = abs(((float(rx[2]+rx[4]+rx[7])/3)-(float(rx[0]+rx[3]+rx[5])/3))/(dispy-20));  // PORTRAIT
+  else
+    px = abs(((float(rx[5]+rx[6]+rx[7])/3)-(float(rx[0]+rx[1]+rx[2])/3))/(dispy-20));  // LANDSCAPE
+
+  if (TOUCH_ORIENTATION == PORTRAIT)
+  {
+    clx = (((rx[0]+rx[3]+rx[5])/3));  // PORTRAIT
+    crx = (((rx[2]+rx[4]+rx[7])/3));  // PORTRAIT
+  }
+  else
+  {
+    clx = (((rx[0]+rx[1]+rx[2])/3));  // LANDSCAPE
+    crx = (((rx[5]+rx[6]+rx[7])/3));  // LANDSCAPE
+  }
+  if (clx
+#include 
+
+// Uncomment the next line for chipKit Uno32
+UTFT        myGLCD(ITDB24D,34,35,36,37);   // Remember to change the model parameter to suit your display module!
+UTouch      myTouch(20,21,22,23,24);
+
+// Uncomment the next line for chipKit Max32
+//UTFT        myGLCD(ITDB32S,82,83,84,85);   // Remember to change the model parameter to suit your display module!
+//UTouch      myTouch(62,63,64,65,66);
+
+void setup()
+{
+  myGLCD.InitLCD();
+  myGLCD.clrScr();
+
+  myTouch.InitTouch();
+  myTouch.setPrecision(PREC_MEDIUM);
+}
+
+void loop()
+{
+  long x, y;
+  
+  while (myTouch.dataAvailable() == true)
+  {
+    myTouch.read();
+    x = myTouch.getX();
+    y = myTouch.getY();
+    if ((x!=-1) and (y!=-1))
+      myGLCD.drawPixel (x, y);
+  }
+}
+
diff --git a/hardware/digistump/sam/libraries/UTouch/keywords.txt b/hardware/digistump/sam/libraries/UTouch/keywords.txt
new file mode 100644
index 0000000..a79eafe
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTouch/keywords.txt
@@ -0,0 +1,17 @@
+UTouch	KEYWORD1
+
+InitTouch	KEYWORD2
+read	KEYWORD2
+dataAvailable	KEYWORD2
+getX	KEYWORD2
+getY	KEYWORD2
+setPrecision	KEYWORD2
+
+PREC_LOW	LITERAL1
+PREC_MEDIUM	LITERAL1
+PREC_HI	LITERAL1
+PREC_EXTREME	LITERAL1
+PORTRAIT	LITERAL1
+LANDSCAPE	LITERAL1
+TP_X	LITERAL1
+TP_Y	LITERAL1
diff --git a/hardware/digistump/sam/libraries/UTouch/version.txt b/hardware/digistump/sam/libraries/UTouch/version.txt
new file mode 100644
index 0000000..cd943e4
--- /dev/null
+++ b/hardware/digistump/sam/libraries/UTouch/version.txt
@@ -0,0 +1,5 @@
+Version:
+	1.0	 1 Dec 2012  -  initial release
+	1.1	23 May 2013  -  added support for more display modules
+				modified calibration to try to compensate for slight flaws in some (larger) touchscreens
+				changed license to CC BY-NC-SA 3.0
diff --git a/hardware/digistump/sam/libraries/Wire/Wire.cpp b/hardware/digistump/sam/libraries/Wire/Wire.cpp
new file mode 100644
index 0000000..90947cb
--- /dev/null
+++ b/hardware/digistump/sam/libraries/Wire/Wire.cpp
@@ -0,0 +1,384 @@
+/*
+ * TwoWire.h - TWI/I2C library for Arduino Due
+ * Copyright (c) 2011 Cristian Maglie .
+ * All rights reserved.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+extern "C" {
+#include 
+}
+
+#include "Wire.h"
+
+static inline bool TWI_FailedAcknowledge(Twi *pTwi) {
+	return pTwi->TWI_SR & TWI_SR_NACK;
+}
+
+static inline bool TWI_WaitTransferComplete(Twi *_twi, uint32_t _timeout) {
+	while (!TWI_TransferComplete(_twi)) {
+		if (TWI_FailedAcknowledge(_twi))
+			return false;
+		if (--_timeout == 0)
+			return false;
+	}
+	return true;
+}
+
+static inline bool TWI_WaitByteSent(Twi *_twi, uint32_t _timeout) {
+	while (!TWI_ByteSent(_twi)) {
+		if (TWI_FailedAcknowledge(_twi))
+			return false;
+		if (--_timeout == 0)
+			return false;
+	}
+	return true;
+}
+
+static inline bool TWI_WaitByteReceived(Twi *_twi, uint32_t _timeout) {
+	while (!TWI_ByteReceived(_twi)) {
+		if (TWI_FailedAcknowledge(_twi))
+			return false;
+		if (--_timeout == 0)
+			return false;
+	}
+	return true;
+}
+
+static inline bool TWI_STATUS_SVREAD(uint32_t status) {
+	return (status & TWI_SR_SVREAD) == TWI_SR_SVREAD;
+}
+
+static inline bool TWI_STATUS_SVACC(uint32_t status) {
+	return (status & TWI_SR_SVACC) == TWI_SR_SVACC;
+}
+
+static inline bool TWI_STATUS_GACC(uint32_t status) {
+	return (status & TWI_SR_GACC) == TWI_SR_GACC;
+}
+
+static inline bool TWI_STATUS_EOSACC(uint32_t status) {
+	return (status & TWI_SR_EOSACC) == TWI_SR_EOSACC;
+}
+
+static inline bool TWI_STATUS_NACK(uint32_t status) {
+	return (status & TWI_SR_NACK) == TWI_SR_NACK;
+}
+
+TwoWire::TwoWire(Twi *_twi, void(*_beginCb)(void)) :
+	twi(_twi), rxBufferIndex(0), rxBufferLength(0), txAddress(0),
+			txBufferLength(0), srvBufferIndex(0), srvBufferLength(0), status(
+					UNINITIALIZED), onBeginCallback(_beginCb) {
+	// Empty
+}
+
+void TwoWire::begin(void) {
+	if (onBeginCallback)
+		onBeginCallback();
+
+	// Disable PDC channel
+	twi->TWI_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS;
+
+	TWI_ConfigureMaster(twi, TWI_CLOCK, VARIANT_MCK);
+	status = MASTER_IDLE;
+}
+
+void TwoWire::begin(uint8_t address) {
+	if (onBeginCallback)
+		onBeginCallback();
+
+	// Disable PDC channel
+	twi->TWI_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS;
+
+	TWI_ConfigureSlave(twi, address);
+	status = SLAVE_IDLE;
+	TWI_EnableIt(twi, TWI_IER_SVACC);
+	//| TWI_IER_RXRDY | TWI_IER_TXRDY	| TWI_IER_TXCOMP);
+}
+
+void TwoWire::begin(int address) {
+	begin((uint8_t) address);
+}
+
+uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop) {
+	if (quantity > BUFFER_LENGTH)
+		quantity = BUFFER_LENGTH;
+
+	// perform blocking read into buffer
+	int readed = 0;
+	TWI_StartRead(twi, address, 0, 0);
+	do {
+		// Stop condition must be set during the reception of last byte
+		if (readed + 1 == quantity)
+			TWI_SendSTOPCondition( twi);
+
+		TWI_WaitByteReceived(twi, RECV_TIMEOUT);
+		rxBuffer[readed++] = TWI_ReadByte(twi);
+	} while (readed < quantity);
+	TWI_WaitTransferComplete(twi, RECV_TIMEOUT);
+
+	// set rx buffer iterator vars
+	rxBufferIndex = 0;
+	rxBufferLength = readed;
+
+	return readed;
+}
+
+uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity) {
+	return requestFrom((uint8_t) address, (uint8_t) quantity, (uint8_t) true);
+}
+
+uint8_t TwoWire::requestFrom(int address, int quantity) {
+	return requestFrom((uint8_t) address, (uint8_t) quantity, (uint8_t) true);
+}
+
+uint8_t TwoWire::requestFrom(int address, int quantity, int sendStop) {
+	return requestFrom((uint8_t) address, (uint8_t) quantity, (uint8_t) sendStop);
+}
+
+void TwoWire::beginTransmission(uint8_t address) {
+	status = MASTER_SEND;
+
+	// save address of target and empty buffer
+	txAddress = address;
+	txBufferLength = 0;
+}
+
+void TwoWire::beginTransmission(int address) {
+	beginTransmission((uint8_t) address);
+}
+
+//
+//	Originally, 'endTransmission' was an f(void) function.
+//	It has been modified to take one parameter indicating
+//	whether or not a STOP should be performed on the bus.
+//	Calling endTransmission(false) allows a sketch to
+//	perform a repeated start.
+//
+//	WARNING: Nothing in the library keeps track of whether
+//	the bus tenure has been properly ended with a STOP. It
+//	is very possible to leave the bus in a hung state if
+//	no call to endTransmission(true) is made. Some I2C
+//	devices will behave oddly if they do not see a STOP.
+//
+uint8_t TwoWire::endTransmission(uint8_t sendStop) {
+	// transmit buffer (blocking)
+	TWI_StartWrite(twi, txAddress, 0, 0, txBuffer[0]);
+	TWI_WaitByteSent(twi, XMIT_TIMEOUT);
+	int sent = 1;
+	while (sent < txBufferLength) {
+		TWI_WriteByte(twi, txBuffer[sent++]);
+		TWI_WaitByteSent(twi, XMIT_TIMEOUT);
+	}
+	TWI_Stop( twi);
+	TWI_WaitTransferComplete(twi, XMIT_TIMEOUT);
+
+	// empty buffer
+	txBufferLength = 0;
+
+	status = MASTER_IDLE;
+	return sent;
+}
+
+//	This provides backwards compatibility with the original
+//	definition, and expected behaviour, of endTransmission
+//
+uint8_t TwoWire::endTransmission(void)
+{
+	return endTransmission(true);
+}
+
+size_t TwoWire::write(uint8_t data) {
+	if (status == MASTER_SEND) {
+		if (txBufferLength >= BUFFER_LENGTH)
+			return 0;
+		txBuffer[txBufferLength++] = data;
+		return 1;
+	} else {
+		if (srvBufferLength >= BUFFER_LENGTH)
+			return 0;
+		srvBuffer[srvBufferLength++] = data;
+		return 1;
+	}
+}
+
+size_t TwoWire::write(const uint8_t *data, size_t quantity) {
+	if (status == MASTER_SEND) {
+		for (size_t i = 0; i < quantity; ++i) {
+			if (txBufferLength >= BUFFER_LENGTH)
+				return i;
+			txBuffer[txBufferLength++] = data[i];
+		}
+	} else {
+		for (size_t i = 0; i < quantity; ++i) {
+			if (srvBufferLength >= BUFFER_LENGTH)
+				return i;
+			srvBuffer[srvBufferLength++] = data[i];
+		}
+	}
+	return quantity;
+}
+
+int TwoWire::available(void) {
+	return rxBufferLength - rxBufferIndex;
+}
+
+int TwoWire::read(void) {
+	if (rxBufferIndex < rxBufferLength)
+		return rxBuffer[rxBufferIndex++];
+	return -1;
+}
+
+int TwoWire::peek(void) {
+	if (rxBufferIndex < rxBufferLength)
+		return rxBuffer[rxBufferIndex];
+	return -1;
+}
+
+void TwoWire::flush(void) {
+	// Do nothing, use endTransmission(..) to force
+	// data transfer.
+}
+
+void TwoWire::onReceive(void(*function)(int)) {
+	onReceiveCallback = function;
+}
+
+void TwoWire::onRequest(void(*function)(void)) {
+	onRequestCallback = function;
+}
+
+void TwoWire::onService(void) {
+	// Retrieve interrupt status
+	uint32_t sr = TWI_GetStatus(twi);
+
+	if (status == SLAVE_IDLE && TWI_STATUS_SVACC(sr)) {
+		TWI_DisableIt(twi, TWI_IDR_SVACC);
+		TWI_EnableIt(twi, TWI_IER_RXRDY | TWI_IER_GACC | TWI_IER_NACK
+				| TWI_IER_EOSACC | TWI_IER_SCL_WS | TWI_IER_TXCOMP);
+
+		srvBufferLength = 0;
+		srvBufferIndex = 0;
+
+		// Detect if we should go into RECV or SEND status
+		// SVREAD==1 means *master* reading -> SLAVE_SEND
+		if (!TWI_STATUS_SVREAD(sr)) {
+			status = SLAVE_RECV;
+		} else {
+			status = SLAVE_SEND;
+
+			// Alert calling program to generate a response ASAP
+			if (onRequestCallback)
+				onRequestCallback();
+			else
+				// create a default 1-byte response
+				write((uint8_t) 0);
+		}
+	}
+
+	if (status != SLAVE_IDLE) {
+		if (TWI_STATUS_TXCOMP(sr) && TWI_STATUS_EOSACC(sr)) {
+			if (status == SLAVE_RECV && onReceiveCallback) {
+				// Copy data into rxBuffer
+				// (allows to receive another packet while the
+				// user program reads actual data)
+				for (uint8_t i = 0; i < srvBufferLength; ++i)
+					rxBuffer[i] = srvBuffer[i];
+				rxBufferIndex = 0;
+				rxBufferLength = srvBufferLength;
+
+				// Alert calling program
+				onReceiveCallback( rxBufferLength);
+			}
+
+			// Transfer completed
+			TWI_EnableIt(twi, TWI_SR_SVACC);
+			TWI_DisableIt(twi, TWI_IDR_RXRDY | TWI_IDR_GACC | TWI_IDR_NACK
+					| TWI_IDR_EOSACC | TWI_IDR_SCL_WS | TWI_IER_TXCOMP);
+			status = SLAVE_IDLE;
+		}
+	}
+
+	if (status == SLAVE_RECV) {
+		if (TWI_STATUS_RXRDY(sr)) {
+			if (srvBufferLength < BUFFER_LENGTH)
+				srvBuffer[srvBufferLength++] = TWI_ReadByte(twi);
+		}
+	}
+
+	if (status == SLAVE_SEND) {
+		if (TWI_STATUS_TXRDY(sr) && !TWI_STATUS_NACK(sr)) {
+			uint8_t c = 'x';
+			if (srvBufferIndex < srvBufferLength)
+				c = srvBuffer[srvBufferIndex++];
+			TWI_WriteByte(twi, c);
+		}
+	}
+}
+
+#if WIRE_INTERFACES_COUNT > 0
+static void Wire_Init(void) {
+	pmc_enable_periph_clk(WIRE_INTERFACE_ID);
+	PIO_Configure(
+			g_APinDescription[PIN_WIRE_SDA].pPort,
+			g_APinDescription[PIN_WIRE_SDA].ulPinType,
+			g_APinDescription[PIN_WIRE_SDA].ulPin,
+			g_APinDescription[PIN_WIRE_SDA].ulPinConfiguration);
+	PIO_Configure(
+			g_APinDescription[PIN_WIRE_SCL].pPort,
+			g_APinDescription[PIN_WIRE_SCL].ulPinType,
+			g_APinDescription[PIN_WIRE_SCL].ulPin,
+			g_APinDescription[PIN_WIRE_SCL].ulPinConfiguration);
+
+	NVIC_DisableIRQ(TWI1_IRQn);
+	NVIC_ClearPendingIRQ(TWI1_IRQn);
+	NVIC_SetPriority(TWI1_IRQn, 0);
+	NVIC_EnableIRQ(TWI1_IRQn);
+}
+
+TwoWire Wire = TwoWire(WIRE_INTERFACE, Wire_Init);
+
+void WIRE_ISR_HANDLER(void) {
+	Wire.onService();
+}
+#endif
+
+#if WIRE_INTERFACES_COUNT > 1
+static void Wire1_Init(void) {
+	pmc_enable_periph_clk(WIRE1_INTERFACE_ID);
+	PIO_Configure(
+			g_APinDescription[PIN_WIRE1_SDA].pPort,
+			g_APinDescription[PIN_WIRE1_SDA].ulPinType,
+			g_APinDescription[PIN_WIRE1_SDA].ulPin,
+			g_APinDescription[PIN_WIRE1_SDA].ulPinConfiguration);
+	PIO_Configure(
+			g_APinDescription[PIN_WIRE1_SCL].pPort,
+			g_APinDescription[PIN_WIRE1_SCL].ulPinType,
+			g_APinDescription[PIN_WIRE1_SCL].ulPin,
+			g_APinDescription[PIN_WIRE1_SCL].ulPinConfiguration);
+
+	NVIC_DisableIRQ(TWI0_IRQn);
+	NVIC_ClearPendingIRQ(TWI0_IRQn);
+	NVIC_SetPriority(TWI0_IRQn, 0);
+	NVIC_EnableIRQ(TWI0_IRQn);
+}
+
+TwoWire Wire1 = TwoWire(WIRE1_INTERFACE, Wire1_Init);
+
+void WIRE1_ISR_HANDLER(void) {
+	Wire1.onService();
+}
+#endif
diff --git a/hardware/digistump/sam/libraries/Wire/Wire.h b/hardware/digistump/sam/libraries/Wire/Wire.h
new file mode 100644
index 0000000..d36faa9
--- /dev/null
+++ b/hardware/digistump/sam/libraries/Wire/Wire.h
@@ -0,0 +1,117 @@
+/*
+ * TwoWire.h - TWI/I2C library for Arduino Due
+ * Copyright (c) 2011 Cristian Maglie .
+ * All rights reserved.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef TwoWire_h
+#define TwoWire_h
+
+// Include Atmel CMSIS driver
+#include 
+
+#include "Stream.h"
+#include "variant.h"
+
+#define BUFFER_LENGTH 32
+
+class TwoWire : public Stream {
+public:
+	TwoWire(Twi *twi, void(*begin_cb)(void));
+	void begin();
+	void begin(uint8_t);
+	void begin(int);
+	void beginTransmission(uint8_t);
+	void beginTransmission(int);
+	uint8_t endTransmission(void);
+    uint8_t endTransmission(uint8_t);
+	uint8_t requestFrom(uint8_t, uint8_t);
+    uint8_t requestFrom(uint8_t, uint8_t, uint8_t);
+	uint8_t requestFrom(int, int);
+    uint8_t requestFrom(int, int, int);
+	virtual size_t write(uint8_t);
+	virtual size_t write(const uint8_t *, size_t);
+	virtual int available(void);
+	virtual int read(void);
+	virtual int peek(void);
+	virtual void flush(void);
+	void onReceive(void(*)(int));
+	void onRequest(void(*)(void));
+
+    inline size_t write(unsigned long n) { return write((uint8_t)n); }
+    inline size_t write(long n) { return write((uint8_t)n); }
+    inline size_t write(unsigned int n) { return write((uint8_t)n); }
+    inline size_t write(int n) { return write((uint8_t)n); }
+    using Print::write;
+
+	void onService(void);
+
+private:
+	// RX Buffer
+	uint8_t rxBuffer[BUFFER_LENGTH];
+	uint8_t rxBufferIndex;
+	uint8_t rxBufferLength;
+
+	// TX Buffer
+	uint8_t txAddress;
+	uint8_t txBuffer[BUFFER_LENGTH];
+	uint8_t txBufferLength;
+
+	// Service buffer
+	uint8_t srvBuffer[BUFFER_LENGTH];
+	uint8_t srvBufferIndex;
+	uint8_t srvBufferLength;
+
+	// Callback user functions
+	void (*onRequestCallback)(void);
+	void (*onReceiveCallback)(int);
+
+	// Called before initialization
+	void (*onBeginCallback)(void);
+
+	// TWI instance
+	Twi *twi;
+
+	// TWI state
+	enum TwoWireStatus {
+		UNINITIALIZED,
+		MASTER_IDLE,
+		MASTER_SEND,
+		MASTER_RECV,
+		SLAVE_IDLE,
+		SLAVE_RECV,
+		SLAVE_SEND
+	};
+	TwoWireStatus status;
+
+	// TWI clock frequency
+	static const uint32_t TWI_CLOCK = 100000;
+
+	// Timeouts (
+	static const uint32_t RECV_TIMEOUT = 100000;
+	static const uint32_t XMIT_TIMEOUT = 100000;
+};
+
+#if WIRE_INTERFACES_COUNT > 0
+extern TwoWire Wire;
+#endif
+#if WIRE_INTERFACES_COUNT > 1
+extern TwoWire Wire1;
+#endif
+
+#endif
+
diff --git a/hardware/digistump/sam/libraries/Wire/examples/SFRRanger_reader/SFRRanger_reader.pde b/hardware/digistump/sam/libraries/Wire/examples/SFRRanger_reader/SFRRanger_reader.pde
new file mode 100644
index 0000000..9c41c18
--- /dev/null
+++ b/hardware/digistump/sam/libraries/Wire/examples/SFRRanger_reader/SFRRanger_reader.pde
@@ -0,0 +1,87 @@
+// I2C SRF10 or SRF08 Devantech Ultrasonic Ranger Finder 
+// by Nicholas Zambetti 
+// and James Tichenor  
+
+// Demonstrates use of the Wire library reading data from the 
+// Devantech Utrasonic Rangers SFR08 and SFR10
+
+// Created 29 April 2006
+
+// This example code is in the public domain.
+
+
+#include 
+
+void setup()
+{
+  Wire.begin();                // join i2c bus (address optional for master)
+  Serial.begin(9600);          // start serial communication at 9600bps
+}
+
+int reading = 0;
+
+void loop()
+{
+  // step 1: instruct sensor to read echoes
+  Wire.beginTransmission(112); // transmit to device #112 (0x70)
+                               // the address specified in the datasheet is 224 (0xE0)
+                               // but i2c adressing uses the high 7 bits so it's 112
+  Wire.write(byte(0x00));      // sets register pointer to the command register (0x00)  
+  Wire.write(byte(0x50));      // command sensor to measure in "inches" (0x50) 
+                               // use 0x51 for centimeters
+                               // use 0x52 for ping microseconds
+  Wire.endTransmission();      // stop transmitting
+
+  // step 2: wait for readings to happen
+  delay(70);                   // datasheet suggests at least 65 milliseconds
+
+  // step 3: instruct sensor to return a particular echo reading
+  Wire.beginTransmission(112); // transmit to device #112
+  Wire.write(byte(0x02));      // sets register pointer to echo #1 register (0x02)
+  Wire.endTransmission();      // stop transmitting
+
+  // step 4: request reading from sensor
+  Wire.requestFrom(112, 2);    // request 2 bytes from slave device #112
+
+  // step 5: receive reading from sensor
+  if(2 <= Wire.available())    // if two bytes were received
+  {
+    reading = Wire.read();  // receive high byte (overwrites previous reading)
+    reading = reading << 8;    // shift high byte to be high 8 bits
+    reading |= Wire.read(); // receive low byte as lower 8 bits
+    Serial.println(reading);   // print the reading
+  }
+
+  delay(250);                  // wait a bit since people have to read the output :)
+}
+
+
+/*
+
+// The following code changes the address of a Devantech Ultrasonic Range Finder (SRF10 or SRF08)
+// usage: changeAddress(0x70, 0xE6);
+
+void changeAddress(byte oldAddress, byte newAddress)
+{
+  Wire.beginTransmission(oldAddress);
+  Wire.write(byte(0x00));
+  Wire.write(byte(0xA0));
+  Wire.endTransmission();
+
+  Wire.beginTransmission(oldAddress);
+  Wire.write(byte(0x00));
+  Wire.write(byte(0xAA));
+  Wire.endTransmission();
+
+  Wire.beginTransmission(oldAddress);
+  Wire.write(byte(0x00));
+  Wire.write(byte(0xA5));
+  Wire.endTransmission();
+
+  Wire.beginTransmission(oldAddress);
+  Wire.write(byte(0x00));
+  Wire.write(newAddress);
+  Wire.endTransmission();
+}
+
+*/
diff --git a/hardware/digistump/sam/libraries/Wire/examples/digital_potentiometer/digital_potentiometer.pde b/hardware/digistump/sam/libraries/Wire/examples/digital_potentiometer/digital_potentiometer.pde
new file mode 100644
index 0000000..38da1c5
--- /dev/null
+++ b/hardware/digistump/sam/libraries/Wire/examples/digital_potentiometer/digital_potentiometer.pde
@@ -0,0 +1,39 @@
+// I2C Digital Potentiometer
+// by Nicholas Zambetti 
+// and Shawn Bonkowski 
+
+// Demonstrates use of the Wire library
+// Controls AD5171 digital potentiometer via I2C/TWI
+
+// Created 31 March 2006
+
+// This example code is in the public domain.
+
+// This example code is in the public domain.
+
+
+#include 
+
+void setup()
+{
+  Wire.begin(); // join i2c bus (address optional for master)
+}
+
+byte val = 0;
+
+void loop()
+{
+  Wire.beginTransmission(44); // transmit to device #44 (0x2c)
+                              // device address is specified in datasheet
+  Wire.write(byte(0x00));            // sends instruction byte  
+  Wire.write(val);             // sends potentiometer value byte  
+  Wire.endTransmission();     // stop transmitting
+
+  val++;        // increment value
+  if(val == 64) // if reached 64th position (max)
+  {
+    val = 0;    // start over from lowest value
+  }
+  delay(500);
+}
+
diff --git a/hardware/digistump/sam/libraries/Wire/examples/master_reader/master_reader.pde b/hardware/digistump/sam/libraries/Wire/examples/master_reader/master_reader.pde
new file mode 100644
index 0000000..4124d7d
--- /dev/null
+++ b/hardware/digistump/sam/libraries/Wire/examples/master_reader/master_reader.pde
@@ -0,0 +1,32 @@
+// Wire Master Reader
+// by Nicholas Zambetti 
+
+// Demonstrates use of the Wire library
+// Reads data from an I2C/TWI slave device
+// Refer to the "Wire Slave Sender" example for use with this
+
+// Created 29 March 2006
+
+// This example code is in the public domain.
+
+
+#include 
+
+void setup()
+{
+  Wire.begin();        // join i2c bus (address optional for master)
+  Serial.begin(9600);  // start serial for output
+}
+
+void loop()
+{
+  Wire.requestFrom(2, 6);    // request 6 bytes from slave device #2
+
+  while(Wire.available())    // slave may send less than requested
+  { 
+    char c = Wire.read(); // receive a byte as character
+    Serial.print(c);         // print the character
+  }
+
+  delay(500);
+}
diff --git a/hardware/digistump/sam/libraries/Wire/examples/master_writer/master_writer.pde b/hardware/digistump/sam/libraries/Wire/examples/master_writer/master_writer.pde
new file mode 100644
index 0000000..ccaa036
--- /dev/null
+++ b/hardware/digistump/sam/libraries/Wire/examples/master_writer/master_writer.pde
@@ -0,0 +1,31 @@
+// Wire Master Writer
+// by Nicholas Zambetti 
+
+// Demonstrates use of the Wire library
+// Writes data to an I2C/TWI slave device
+// Refer to the "Wire Slave Receiver" example for use with this
+
+// Created 29 March 2006
+
+// This example code is in the public domain.
+
+
+#include 
+
+void setup()
+{
+  Wire.begin(); // join i2c bus (address optional for master)
+}
+
+byte x = 0;
+
+void loop()
+{
+  Wire.beginTransmission(4); // transmit to device #4
+  Wire.write("x is ");        // sends five bytes
+  Wire.write(x);              // sends one byte  
+  Wire.endTransmission();    // stop transmitting
+
+  x++;
+  delay(500);
+}
diff --git a/hardware/digistump/sam/libraries/Wire/examples/slave_receiver/slave_receiver.pde b/hardware/digistump/sam/libraries/Wire/examples/slave_receiver/slave_receiver.pde
new file mode 100644
index 0000000..60dd4bd
--- /dev/null
+++ b/hardware/digistump/sam/libraries/Wire/examples/slave_receiver/slave_receiver.pde
@@ -0,0 +1,38 @@
+// Wire Slave Receiver
+// by Nicholas Zambetti 
+
+// Demonstrates use of the Wire library
+// Receives data as an I2C/TWI slave device
+// Refer to the "Wire Master Writer" example for use with this
+
+// Created 29 March 2006
+
+// This example code is in the public domain.
+
+
+#include 
+
+void setup()
+{
+  Wire.begin(4);                // join i2c bus with address #4
+  Wire.onReceive(receiveEvent); // register event
+  Serial.begin(9600);           // start serial for output
+}
+
+void loop()
+{
+  delay(100);
+}
+
+// function that executes whenever data is received from master
+// this function is registered as an event, see setup()
+void receiveEvent(int howMany)
+{
+  while(1 < Wire.available()) // loop through all but the last
+  {
+    char c = Wire.read(); // receive byte as a character
+    Serial.print(c);         // print the character
+  }
+  int x = Wire.read();    // receive byte as an integer
+  Serial.println(x);         // print the integer
+}
diff --git a/hardware/digistump/sam/libraries/Wire/examples/slave_sender/slave_sender.pde b/hardware/digistump/sam/libraries/Wire/examples/slave_sender/slave_sender.pde
new file mode 100644
index 0000000..d3b238a
--- /dev/null
+++ b/hardware/digistump/sam/libraries/Wire/examples/slave_sender/slave_sender.pde
@@ -0,0 +1,32 @@
+// Wire Slave Sender
+// by Nicholas Zambetti 
+
+// Demonstrates use of the Wire library
+// Sends data as an I2C/TWI slave device
+// Refer to the "Wire Master Reader" example for use with this
+
+// Created 29 March 2006
+
+// This example code is in the public domain.
+
+
+#include 
+
+void setup()
+{
+  Wire.begin(2);                // join i2c bus with address #2
+  Wire.onRequest(requestEvent); // register event
+}
+
+void loop()
+{
+  delay(100);
+}
+
+// function that executes whenever data is requested by master
+// this function is registered as an event, see setup()
+void requestEvent()
+{
+  Wire.write("hello "); // respond with message of 6 bytes
+                       // as expected by master
+}
diff --git a/hardware/digistump/sam/libraries/Wire/keywords.txt b/hardware/digistump/sam/libraries/Wire/keywords.txt
new file mode 100644
index 0000000..e75e929
--- /dev/null
+++ b/hardware/digistump/sam/libraries/Wire/keywords.txt
@@ -0,0 +1,32 @@
+#######################################
+# Syntax Coloring Map For Wire
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+begin	KEYWORD2
+beginTransmission	KEYWORD2
+endTransmission	KEYWORD2
+requestFrom	KEYWORD2
+send	KEYWORD2
+receive	KEYWORD2
+onReceive	KEYWORD2
+onRequest	KEYWORD2
+
+#######################################
+# Instances (KEYWORD2)
+#######################################
+
+Wire	KEYWORD2
+Wire1	KEYWORD2
+
+#######################################
+# Constants (LITERAL1)
+#######################################
+
diff --git a/hardware/digistump/sam/platform.txt b/hardware/digistump/sam/platform.txt
new file mode 100644
index 0000000..061c4fe
--- /dev/null
+++ b/hardware/digistump/sam/platform.txt
@@ -0,0 +1,81 @@
+
+# Arduino SAM Core and platform.
+#
+# For more info:
+# https://github.com/arduino/Arduino/wiki/Arduino-IDE-1.5---3rd-party-Hardware-specification
+
+name=Digistump ARM (32-bits) Boards
+version=1.5.3
+
+# SAM3 compile variables
+# ----------------------
+
+compiler.path={runtime.ide.path}/hardware/tools/gcc-arm-none-eabi-4.8.3-2014q1/bin/
+compiler.c.cmd=arm-none-eabi-gcc
+compiler.c.flags=-c -g -Os -w -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -Dprintf=iprintf
+compiler.c.elf.cmd=arm-none-eabi-g++
+compiler.c.elf.flags=-Os -Wl,--gc-sections
+compiler.S.flags=-c -g -assembler-with-cpp
+compiler.cpp.cmd=arm-none-eabi-g++
+compiler.cpp.flags=-c -g -Os -w -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -Dprintf=iprintf
+compiler.ar.cmd=arm-none-eabi-ar
+compiler.ar.flags=rcs
+compiler.objcopy.cmd=arm-none-eabi-objcopy
+compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0
+compiler.elf2hex.flags=-O binary
+compiler.elf2hex.cmd=arm-none-eabi-objcopy
+compiler.ldflags=
+compiler.size.cmd=arm-none-eabi-size
+compiler.define=-DARDUINO=
+# this can be overriden in boards.txt
+build.extra_flags=
+
+
+compiler.libsam.c.flags="-I{build.system.path}/libsam" "-I{build.system.path}/CMSIS/CMSIS/Include/" "-I{build.system.path}/CMSIS/Device/ATMEL/"
+
+# USB Flags
+# ---------
+build.usb_flags=-DUSB_VID={build.vid} -DUSB_PID={build.pid} -DUSBCON '-DUSB_MANUFACTURER={build.usb_manufacturer}' '-DUSB_PRODUCT={build.usb_product}'
+
+# Default usb manufacturer will be replaced at compile time using
+# numeric vendor ID if available or by board's specific value. 
+build.usb_manufacturer="Unknown"
+
+
+# SAM3 compile patterns
+# ---------------------
+
+## Compile c files
+recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {build.extra_flags} {compiler.libsam.c.flags} {includes} "{source_file}" -o "{object_file}"
+
+## Compile c++ files
+recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {build.extra_flags} {compiler.libsam.c.flags} {includes} "{source_file}" -o "{object_file}"
+
+## Create archives
+recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} "{build.path}/{archive_file}" "{object_file}"
+
+## Combine gc-sections, archives, and objects
+recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mcpu={build.mcu} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -lm -lgcc -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols -Wl,--start-group "{build.path}/syscalls_sam3.c.o" {object_files} "{build.variant.path}/{build.variant_system_lib}" "{build.path}/{archive_file}" -Wl,--end-group
+
+## Create eeprom
+recipe.objcopy.eep.pattern=
+
+## Create hex
+recipe.objcopy.hex.pattern="{compiler.path}{compiler.elf2hex.cmd}" {compiler.elf2hex.flags} "{build.path}/{build.project_name}.elf" "{build.path}/{build.project_name}.bin"
+
+## Compute size
+recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf"
+recipe.size.regex=\.text\s+([0-9]+).*
+
+
+# SAM3 Uploader tools
+# -------------------
+
+tools.bossac.cmd=bossac
+tools.bossac.cmd.windows=bossac.exe
+tools.bossac.path={runtime.ide.path}/hardware/tools
+
+tools.bossac.upload.params.verbose=-i -d
+tools.bossac.upload.params.quiet=
+tools.bossac.upload.pattern="{path}/{cmd}" {upload.verbose} --port={serial.port.file} -U {upload.native_usb} -e -w -v -b "{build.path}/{build.project_name}.bin" -R
+
diff --git a/hardware/digistump/sam/programmers.txt b/hardware/digistump/sam/programmers.txt
new file mode 100644
index 0000000..e69de29
diff --git a/hardware/digistump/sam/sam.bat b/hardware/digistump/sam/sam.bat
new file mode 100644
index 0000000..2744187
--- /dev/null
+++ b/hardware/digistump/sam/sam.bat
@@ -0,0 +1,10 @@
+set Path=%ARM_GCC_TOOLCHAIN%
+export Path
+
+start "libsam" /d"system\libsam\build_gcc" /max "cd"
+start "libarduino" /d"cores\arduino\build_gcc" /max "cd"
+rem start "libvariant Arduino Due U" /d"variants\arduino_due_u\build_gcc" /max "cd"
+start "libvariant Arduino Due X" /d"variants\arduino_due_x\build_gcc" /max "cd"
+rem start "libvariant ADK2" /d"..\..\google\sam\variants\adk2\build_gcc" /max "cd"
+rem start "libvariant SAM3X-EK" /d"..\..\atmel\sam\variants\sam3x_ek\build_gcc" /max "cd"
+start "test" /d"cores\arduino\validation_usb_host\build_gcc" /max "cd"
diff --git a/hardware/digistump/sam/system/CMSIS/ATMEL Version 2.10.107 b/hardware/digistump/sam/system/CMSIS/ATMEL Version 2.10.107
new file mode 100644
index 0000000..e69de29
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf b/hardware/digistump/sam/system/CMSIS/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf
new file mode 100644
index 0000000..e04afae
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf	
@@ -0,0 +1,182 @@
+06 December, 2010  CONFIDENTIAL  LEC-PRE-00489-V6.0
+
+END USER LICENCE AGREEMENT FOR THE CORTEX MICROCONTROLLER SOFTWARE INTERFACE
+STANDARD (CMSIS) SPECIFICATION AND SOFTWARE
+
+THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A
+SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE
+CMSIS SPECIFICATION, EXAMPLE CODE, DSP LIBRARY SPECIFICATION AND DSP LIBRARY
+IMPLEMENTATION AS SUCH TERMS ARE DEFINED BELOW (COLLECTIVELY, THE “ARM
+DELIVERABLESâ€). ARM IS ONLY WILLING TO LICENSE THE ARM DELIVERABLES TO YOU ON CONDITION
+THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING
+OR OTHERWISE USING OR COPYING THE ARM DELIVERABLES YOU INDICATE THAT YOU AGREE TO
+BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS
+LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE THE ARM DELIVERABLES AND YOU MAY NOT
+INSTALL, USE OR COPY THE ARM DELIVERABLES.
+
+“CMSIS Specification†means any documentation and C programming language files defining the application
+programming interface, naming and coding conventions of the Cortex Microcontroller Software Interface
+Standard (CMSIS) as well as the System View Description (SVD) documentation and associated XML schema
+file. Notwithstanding the foregoing, “CMSIS Specification†shall not include (i) the implementation of other
+published specifications referenced in the CMSIS Specification; (ii) any enabling technologies that may be
+necessary to make or use any product or portion thereof that complies with the CMSIS Specification, but are not
+themselves expressly set forth in the CMSIS Specification (e.g. compiler front ends, code generators, back ends,
+libraries or other compiler, assembler or linker technologies; validation or debug software or hardware;
+applications, operating system or driver software; RISC architecture; processor microarchitecture); (iii)
+maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high level representations of
+integrated circuit designs.
+
+“DSP Library Implementation†means any C programming language source code implementing the functionality
+of the digital signal processor (DSP) algorithms and the application programming interface as defined in the DSP
+Library Specification. The DSP Library Implementation makes use of CMSIS application programming interface
+and therefore is targeted at Cortex-M class processors.
+
+“DSP Library Specification†means the DSP library documentation and C programming language file defining the
+application programming interface of the DSP Library Implementation. Notwithstanding the foregoing, “DSP
+Library Specification†shall not include (i) the implementation of other published specifications referenced in the
+DSP Library Specification; (ii) any enabling technologies that may be necessary to make or use any product or
+portion thereof that complies with the DSP Library Specification, but are not themselves expressly set forth in the
+DSP Library Specification (e.g. compiler front ends, code generators, back ends, libraries or other compiler,
+assembler or linker technologies; validation or debug software or hardware; applications, operating system or
+driver software; RISC architecture; processor microarchitecture); (iii) maskworks and physical layouts of
+integrated circuit designs; or (iv) RTL or other high level representations of integrated circuit designs.
+
+“Example Code†means any files in C, C++ or ARM assembly programming languages, associated project and
+configuration files that demonstrate the usage of the CMSIS Specification, the DSP Library Specification and the
+DSP Library Implementation, for microprocessors or device specific software applications that are for use with
+microprocessors.
+
+1. LICENCE GRANTS.
+
+1.1 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-
+transferable licence, to;
+
+(i) use and copy the CMSIS Specification for the purpose of developing, having developed, manufacturing,
+having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the
+CMSIS Specification, provided that you preserve any copyright notices which are included with, or in, the CMSIS
+Specification and provided that you do not use ARM's name, logo or trademarks to market such products;
+
+(ii) use, copy, and modify (solely to the extent necessary to incorporate the whole or any part of the DSP Library
+Specification into your documentation), the DSP Library Specification, for the purpose of developing, having
+developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing
+products that comply with the DSP Library Specification, and distribute and have distributed any documentation
+created by or for you that has been derived from the DSP Library Specification with such products, provided that
+
+AP                 1 of 3                            ARM/
+06 December, 2010  CONFIDENTIAL  LEC-PRE-00489-V6.0
+
+you preserve any copyright notices which are included with, or in, the DSP Library Specification and provided that
+you do not use ARM's name, logo or trademarks to market such products;
+
+(iii) use, copy, modify and sublicense the Example Code solely for the purpose of developing, having developed,
+manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that
+comply with either or both the CMSIS Specification and the DSP Library Specification, provided that you preserve
+any copyright notices which are included with, or in, the Example Code and that you do not use ARM's name,
+logo or trademarks to market such products;
+
+(iv) use, copy and modify (provided that the logical functionality and the application programming interface of the
+DSP Library Implementation are maintained) the DSP Library Implementation, solely for the purposes of
+developing; (a) software applications for use with microprocessors manufactured or simulated under licence from
+ARM (“Software Applicationsâ€); and (b) tools that are designed to develop software programs for use with
+microprocessors manufactured or simulated under licence from ARM (“Tools"); and
+
+(v) subject to clause 1.1(vi) below; (a) distribute and sublicense the use of the DSP Library Implementation
+(including any modified forms thereof created under Clause 1.1(iv) above) in binary or source format, solely as
+incorporated into Software Library Applications and Tools to third parties; and (b) sublicense to such third parties
+the right to use and copy the Tools for the purposes of developing and distribute software programs for use with
+microprocessors manufactured or simulated under licence from ARM.
+
+(vi) CONDITIONS ON REDISTRIBUTION: If you choose to redistribute the whole or any part of the DSP Library
+Implementation as incorporated into Software Library Applications or Tools, you agree to; (a) ensure that the
+DSP Library Implementation is licensed for use only as part of Software Library Applications and Tools and only
+for use with microprocessors manufactured or simulated under licence from ARM; (b) not to use ARM's name,
+logo or trademarks to market Software Applications and Tools; and (c) include valid copyright notices on
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+
+2. RESTRICTIONS ON USE OF THE ARM DELIVERABLES.
+
+PERMITTED USERS: The ARM Deliverables shall be used only by you (either a single individual, or single legal
+entity) your employees, or by your on-site bona fide sub-contractors for whose acts and omissions you hereby
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+COPYRIGHT AND RESERVATION OF RIGHTS: The ARM Deliverables are owned by ARM or its licensors and
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+
+AP                 2 of 3                            ARM/
+06 December, 2010  CONFIDENTIAL  LEC-PRE-00489-V6.0
+
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+THIS LICENCE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW.
+
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+
+US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this
+commercial product and accompanying documentation is restricted in accordance with the terms of this Licence.
+
+7. TERM AND TERMINATION.
+
+7.1 This Licence shall remain in force until terminated in accordance with the terms of Clause 7.2 or Clause 7.3
+below.
+
+7.2 Without prejudice to any of its other rights if you are in breach of any of the terms and conditions of this
+Licence then ARM may terminate this Licence immediately upon giving written notice to you. You may terminate
+this Licence at any time.
+
+7.3 This Licence shall immediately terminate and shall be unavailable to you if you or any party affiliated to you
+asserts any patents against ARM, ARM affiliates, third parties who have a valid licence from ARM for the ARM
+Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate)
+patent is Necessary to implement the CMSIS Specification or DSP Library Specification. In this Licence; (i)
+"affiliate" means any entity controlling, controlled by or under common control with a party (in fact or in law, via
+voting securities, management control or otherwise) and "affiliated" shall be construed accordingly; (ii) "assert"
+means to allege infringement in legal or administrative proceedings, or proceedings before any other competent
+trade, arbitral or international authority; (iii) “Necessary†means with respect to any claims of any patent, those
+claims which, without the appropriate permission of the patent owner, will be infringed when implementing the
+CMSIS Specification or DSP Library Specification because no alternative, commercially reasonable, non-
+infringing way of implementing the CMSIS Specification or DSP Library Specification is known.
+
+7.4 Upon termination of this Licence, you shall stop using the ARM Deliverables and destroy all copies of the
+ARM Deliverables in your possession. The provisions of clauses 5, 6, 7, and 8 shall survive termination of this
+Licence.
+
+8. GENERAL.
+
+This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by
+you and ARM, this is the only agreement between you and ARM relating to the ARM Deliverables and it may only
+be modified by written agreement between you and ARM. Except as expressly agreed in writing, this Licence
+may not be modified by purchase orders, advertising or other representation by any person. If any clause or
+sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisions of this
+Licence shall not be affected thereby. The failure by ARM to enforce any of the provisions of this Licence, unless
+waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of
+this Licence in the future. This Licence may not be assigned without the prior written consent of ARM.
+
+ARM contract reference LEC-PRE-00489
+
+AP                 3 of 3                            ARM/
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/Common/Include/math_helper.h b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/Common/Include/math_helper.h
new file mode 100644
index 0000000..947c0d9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/Common/Include/math_helper.h
@@ -0,0 +1,54 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010 ARM Limited. All rights reserved.  
+*  
+* $Date:        29. November 2010  
+* $Revision: 	V1.0.3  
+*  
+* Project: 	    CMSIS DSP Library 
+*
+* Title:	    math_helper.h
+* 
+*
+* Description:	Prototypes of all helper functions required.  
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation.  
+*   
+* Version 1.0.2 2010/11/11  
+*    Documentation updated.   
+*  
+* Version 1.0.1 2010/10/05   
+*    Production release and review comments incorporated.  
+*  
+* Version 1.0.0 2010/09/20   
+*    Production release and review comments incorporated.  
+*  
+* Version 0.0.7  2010/06/10   
+*    Misra-C changes done 
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+#ifndef MATH_HELPER_H
+#define MATH_HELPER_H
+
+float arm_snr_f32(float *pRef, float *pTest,  uint32_t buffSize);  
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
+void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_provide_guard_bits_q7 (q7_t * input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
+void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_clip_f32(float *pIn, uint32_t numSamples);
+uint32_t arm_calc_guard_bits(uint32_t num_adds);
+void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
+uint32_t arm_calc_2pow(uint32_t guard_bits);
+#endif
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/Common/Source/math_helper.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/Common/Source/math_helper.c
new file mode 100644
index 0000000..75dcd5f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/Common/Source/math_helper.c
@@ -0,0 +1,447 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010 ARM Limited. All rights reserved.  
+*  
+* $Date:        29. November 2010  
+* $Revision: 	V1.0.3  
+*  
+* Project: 	    CMSIS DSP Library 
+*
+* Title:	    math_helper.c
+*
+* Description:	Definition of all helper functions required.  
+*  
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation.  
+*   
+* Version 1.0.2 2010/11/11  
+*    Documentation updated.   
+*  
+* Version 1.0.1 2010/10/05   
+*    Production release and review comments incorporated.  
+*  
+* Version 1.0.0 2010/09/20   
+*    Production release and review comments incorporated.  
+*  
+* Version 0.0.7  2010/06/10   
+*    Misra-C changes done 
+* -------------------------------------------------------------------- */
+
+/* ----------------------------------------------------------------------
+*		Include standard header files  
+* -------------------------------------------------------------------- */
+#include
+
+/* ----------------------------------------------------------------------
+*		Include project header files  
+* -------------------------------------------------------------------- */
+#include "math_helper.h"
+
+/** 
+ * @brief  Caluclation of SNR
+ * @param  float* 	Pointer to the reference buffer
+ * @param  float*	Pointer to the test buffer
+ * @param  uint32_t	total number of samples
+ * @return float	SNR
+ * The function Caluclates signal to noise ratio for the reference output 
+ * and test output 
+ */
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
+{
+  float EnergySignal = 0.0, EnergyError = 0.0;
+  uint32_t i;
+  float SNR;
+  int temp;
+  int *test;
+
+  for (i = 0; i < buffSize; i++)
+    {
+ 	  /* Checking for a NAN value in pRef array */
+	  test =   (int *)(&pRef[i]);
+      temp =  *test;
+
+	  if(temp == 0x7FC00000)
+	  {
+	  		return(0);
+	  }
+
+	  /* Checking for a NAN value in pTest array */
+	  test =   (int *)(&pTest[i]);
+      temp =  *test;
+
+	  if(temp == 0x7FC00000)
+	  {
+	  		return(0);
+	  }
+      EnergySignal += pRef[i] * pRef[i];
+      EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); 
+    }
+
+	/* Checking for a NAN value in EnergyError */
+	test =   (int *)(&EnergyError);
+    temp =  *test;
+
+    if(temp == 0x7FC00000)
+    {
+  		return(0);
+    }
+	
+
+  SNR = 10 * log10 (EnergySignal / EnergyError);
+
+  return (SNR);
+
+}
+
+
+/** 
+ * @brief  Provide guard bits for Input buffer
+ * @param  q15_t* 	    Pointer to input buffer
+ * @param  uint32_t 	blockSize
+ * @param  uint32_t 	guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer 
+ * to avoid overflow 
+ */
+
+void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
+                            uint32_t guard_bits)
+{
+  uint32_t i;
+
+  for (i = 0; i < blockSize; i++)
+    {
+      input_buf[i] = input_buf[i] >> guard_bits;
+    }
+}
+
+/** 
+ * @brief  Converts float to fixed in q12.20 format
+ * @param  uint32_t 	number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point(q12.20) values 
+ */
+
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+	  /* 1048576.0f corresponds to pow(2, 20) */
+      pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
+
+      pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+      if (pIn[i] == (float) 1.0)
+        {
+          pOut[i] = 0x000FFFFF;
+        }
+    }
+}
+
+/** 
+ * @brief  Compare MATLAB Reference Output and ARM Test output
+ * @param  q15_t* 	Pointer to Ref buffer
+ * @param  q15_t* 	Pointer to Test buffer
+ * @param  uint32_t 	number of samples in the buffer
+ * @return none 
+ */
+
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples)
+{
+  uint32_t i; 
+  int32_t diff, diffCrnt = 0;
+  uint32_t maxDiff = 0;
+
+  for (i = 0; i < numSamples; i++)
+  {
+  	diff = pIn[i] - pOut[i];
+  	diffCrnt = (diff > 0) ? diff : -diff;
+
+	if(diffCrnt > maxDiff)
+	{
+		maxDiff = diffCrnt;
+	}	
+  }
+
+  return(maxDiff);
+}
+
+/** 
+ * @brief  Compare MATLAB Reference Output and ARM Test output
+ * @param  q31_t* 	Pointer to Ref buffer
+ * @param  q31_t* 	Pointer to Test buffer
+ * @param  uint32_t 	number of samples in the buffer
+ * @return none 
+ */
+
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
+{
+  uint32_t i; 
+  int32_t diff, diffCrnt = 0;
+  uint32_t maxDiff = 0;
+
+  for (i = 0; i < numSamples; i++)
+  {
+  	diff = pIn[i] - pOut[i];
+  	diffCrnt = (diff > 0) ? diff : -diff;
+
+	if(diffCrnt > maxDiff)
+	{
+		maxDiff = diffCrnt;
+	}
+  }
+
+  return(maxDiff);
+}
+
+/** 
+ * @brief  Provide guard bits for Input buffer
+ * @param  q31_t* 	Pointer to input buffer
+ * @param  uint32_t 	blockSize
+ * @param  uint32_t 	guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer 
+ * to avoid overflow 
+ */
+
+void arm_provide_guard_bits_q31 (q31_t * input_buf, 
+								 uint32_t blockSize,
+                                 uint32_t guard_bits)
+{
+  uint32_t i;
+
+  for (i = 0; i < blockSize; i++)
+    {
+      input_buf[i] = input_buf[i] >> guard_bits;
+    }
+}
+
+/** 
+ * @brief  Provide guard bits for Input buffer
+ * @param  q31_t* 	Pointer to input buffer
+ * @param  uint32_t 	blockSize
+ * @param  uint32_t 	guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer 
+ * to avoid overflow 
+ */
+
+void arm_provide_guard_bits_q7 (q7_t * input_buf, 
+								uint32_t blockSize,
+                                uint32_t guard_bits)
+{
+  uint32_t i;
+
+  for (i = 0; i < blockSize; i++)
+    {
+      input_buf[i] = input_buf[i] >> guard_bits;
+    }
+}
+
+
+
+/** 
+ * @brief  Caluclates number of guard bits 
+ * @param  uint32_t 	number of additions
+ * @return none
+ * The function Caluclates the number of guard bits  
+ * depending on the numtaps 
+ */
+
+uint32_t arm_calc_guard_bits (uint32_t num_adds)
+{
+  uint32_t i = 1, j = 0;
+
+  if (num_adds == 1)
+    {
+      return (0);
+    }
+
+  while (i < num_adds)
+    {
+      i = i * 2;
+      j++;
+    }
+
+  return (j);
+}
+
+/** 
+ * @brief  Converts Q15 to floating-point
+ * @param  uint32_t 	number of samples in the buffer
+ * @return none
+ */
+
+void arm_apply_guard_bits (float32_t * pIn, 
+						   uint32_t numSamples, 
+						   uint32_t guard_bits)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+      pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
+    }
+}
+
+/** 
+ * @brief  Calculates pow(2, numShifts)
+ * @param  uint32_t 	number of shifts
+ * @return pow(2, numShifts)
+ */
+uint32_t arm_calc_2pow(uint32_t numShifts)
+{
+
+  uint32_t i, val = 1;
+
+  for (i = 0; i < numShifts; i++)
+    {
+      val = val * 2;
+    }	
+
+  return(val);
+}
+
+
+
+/** 
+ * @brief  Converts float to fixed q14 
+ * @param  uint32_t 	number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values 
+ */
+
+void arm_float_to_q14 (float *pIn, q15_t * pOut, 
+                       uint32_t numSamples)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+	  /* 16384.0f corresponds to pow(2, 14) */
+      pOut[i] = (q15_t) (pIn[i] * 16384.0f);
+
+      pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+      if (pIn[i] == (float) 2.0)
+        {
+          pOut[i] = 0x7FFF;
+        }
+
+    }
+
+}
+
+ 
+/** 
+ * @brief  Converts float to fixed q30 format
+ * @param  uint32_t 	number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values 
+ */
+
+void arm_float_to_q30 (float *pIn, q31_t * pOut, 
+					   uint32_t numSamples)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+	  /* 1073741824.0f corresponds to pow(2, 30) */
+      pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
+
+      pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+      if (pIn[i] == (float) 2.0)
+        {
+          pOut[i] = 0x7FFFFFFF;
+        }
+    }
+}
+
+/** 
+ * @brief  Converts float to fixed q30 format
+ * @param  uint32_t 	number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values 
+ */
+
+void arm_float_to_q29 (float *pIn, q31_t * pOut, 
+					   uint32_t numSamples)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+	  /* 1073741824.0f corresponds to pow(2, 30) */
+      pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
+
+      pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+      if (pIn[i] == (float) 4.0)
+        {
+          pOut[i] = 0x7FFFFFFF;
+        }
+    }
+}
+
+
+/** 
+ * @brief  Converts float to fixed q28 format
+ * @param  uint32_t 	number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values 
+ */
+
+void arm_float_to_q28 (float *pIn, q31_t * pOut, 
+                       uint32_t numSamples)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+	/* 268435456.0f corresponds to pow(2, 28) */
+      pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
+
+      pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+      if (pIn[i] == (float) 8.0)
+        {
+          pOut[i] = 0x7FFFFFFF;
+        }
+    }
+}
+
+/** 
+ * @brief  Clip the float values to +/- 1 
+ * @param  pIn 	input buffer
+ * @param  numSamples 	number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values 
+ */
+
+void arm_clip_f32 (float *pIn, uint32_t numSamples)
+{
+  uint32_t i;
+
+  for (i = 0; i < numSamples; i++)
+    {
+      if(pIn[i] > 1.0f)
+	  {
+	    pIn[i] = 1.0;
+	  }
+	  else if( pIn[i] < -1.0f)
+	  {
+	    pIn[i] = -1.0;
+	  }
+	       
+    }
+}
+
+
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_class_marks_example.ini b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_class_marks_example.ini
new file mode 100644
index 0000000..0ca6ba5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_class_marks_example.ini
@@ -0,0 +1,14 @@
+
+/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions 
+   
+   The file can be executed in the following way:
+   1) manually from uVision command window (in debug mode) using command:
+   INCLUIDE arm_class_marks_example.ini	 
+
+*/
+
+
+// usual initialisation	for target setup
+MAP  0x20000000, 0x20008000  READ WRITE  // allow R/W access to IO space
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvopt
new file mode 100644
index 0000000..2654ad9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvopt
@@ -0,0 +1,281 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\debug\
+      
+      
+        1
+        1
+        1
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+        1
+        1
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+        1
+        0
+        0
+        0
+        0
+      
+      
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+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        SARMCM3.DLL
+        
+        DARMCM1.DLL
+        -pCM0
+        SARMCM3.DLL
+        
+        TARMCM1.DLL
+        -pCM0
+      
+      
+        1
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        1
+        1
+        0
+        1
+        0
+        0
+        -1
+        
+        
+        
+        
+        .\arm_class_marks_example.ini
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          -T0
+        
+      
+      
+        
+          0
+          0
+          193
+          1
+          
330

+          0
+          0
+          0
+          0
+          1
+          
+          
+          \\arm_cortexM0l_class_marks_example\../arm_class_marks_example_f32.c\193
+        
+      
+      
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+    
+  
+
+  
+    Source Group 1
+    1
+    0
+    0
+    
+      1
+      1
+      1
+      0
+      0
+      0
+      0
+      183
+      193
+      0
+      ..\arm_class_marks_example_f32.c
+      arm_class_marks_example_f32.c
+    
+  
+
+  
+    CMSIS Device
+    0
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      0
+      0
+      0
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+      ..\system_ARMCM0.c
+      system_ARMCM0.c
+    
+    
+      2
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+      2
+      0
+      0
+      0
+      0
+      78
+      78
+      0
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvproj
new file mode 100644
index 0000000..989129c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM0l_class_marks_example.uvproj
@@ -0,0 +1,425 @@
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+
+
+  1.1
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### uVision Project, (C) Keil Software

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvopt
new file mode 100644
index 0000000..439df65
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvopt
@@ -0,0 +1,287 @@
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+  1.0
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### uVision Project, (C) Keil Software

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvproj
new file mode 100644
index 0000000..cd8c06a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM3l_class_marks_example.uvproj
@@ -0,0 +1,425 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
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+      Target 1
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvopt
new file mode 100644
index 0000000..3640e45
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvopt
@@ -0,0 +1,281 @@
+
+
+
+  1.0
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+  
### uVision Project, (C) Keil Software

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+    1
+    0
+    0
+    
+      1
+      1
+      1
+      0
+      0
+      0
+      0
+      183
+      193
+      0
+      ..\arm_class_marks_example_f32.c
+      arm_class_marks_example_f32.c
+    
+  
+
+  
+    CMSIS Device
+    1
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\system_ARMCM4.c
+      system_ARMCM4.c
+    
+    
+      2
+      3
+      2
+      0
+      0
+      0
+      0
+      78
+      78
+      0
+      .\startup_ARMCM4.s
+      startup_ARMCM4.s
+    
+  
+
+  
+    CMSIS SW_DSP_Library
+    1
+    0
+    0
+    
+      3
+      4
+      4
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib
+      arm_cortexM4lf_math.lib
+    
+  
+
+  
+    1
+    0
+    
+      100
+      0
+      
+        
+          ..\arm_class_marks_example_f32.c
+          0
+          183
+          193
+        
+        
+          .\startup_ARMCM4.s
+          0
+          78
+          78
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvproj
new file mode 100644
index 0000000..5cc7c3d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/arm_cortexM4lf_class_marks_example.uvproj
@@ -0,0 +1,425 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M4 FPU
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2
+          
+          
+          
+          5237
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\debug\
+          arm_cortexM4lfclass_marks_example
+          1
+          0
+          0
+          1
+          1
+          .\debug\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
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+            0
+            0
+            
+            
+            0
+            0
+          
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+          
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+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          
+          DCM.DLL
+          -pCM3
+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM3
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            0
+            1
+            0
+            1
+            1
+            1
+            0
+            1
+          
+          0
+          -1
+          
+            
+            
+            
+            
+            .\arm_class_marks_example.ini
+          
+          
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            0
+            -1
+          
+          
+          
+          
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
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+            0
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
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+                0x0
+                0x0
+              
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+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
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+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+            
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+          
+            1
+            3
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              ARM_MATH_CM4, __FPU_PRESENT = 1
+              
+              ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x00000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Source Group 1
+          
+            
+              arm_class_marks_example_f32.c
+              1
+              ..\arm_class_marks_example_f32.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM4.c
+              1
+              ..\system_ARMCM4.c
+            
+            
+              startup_ARMCM4.s
+              2
+              .\startup_ARMCM4.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+          
+            
+              arm_cortexM4lf_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..0acd346
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM0.s
@@ -0,0 +1,144 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Cortex-M0 Core Device Startup File
+; *           for CM0 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..5af584b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM3.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Cortex-M3 Core Device Startup File
+; *           for CM3 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..09fdbd6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/ARM/startup_ARMCM4.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM4 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/ARMCMx.ld b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/ARMCMx.ld
new file mode 100644
index 0000000..9cf8c92
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/ARMCMx.ld
@@ -0,0 +1,198 @@
+/* Linker script for Cortex-M0
+ *
+ * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ *  Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(_start)
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)
+
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00000000, LENGTH = 64K
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH =  8K
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_cortex_m)
+EXTERN(__cs3_interrupt_vector_cortex_m)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __cs3_region_start_rom = .;
+    *(.cs3.region-head.rom)
+    __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
+    *(.cs3.interrupt_vector)
+    /* Make sure we pulled in an interrupt vector.  */
+    ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
+    *(.rom)
+    *(.rom.b)
+
+    __cs3_reset = __cs3_reset_cortex_m;
+    *(.cs3.reset)
+    /* Make sure we pulled in some reset code.  */
+    ASSERT (. != __cs3_reset, "No reset code");
+
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table)
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    . = ALIGN(4);
+    KEEP(*(.init))
+
+    . = ALIGN(4);
+    __preinit_array_start = .;
+    KEEP (*(.preinit_array))
+    __preinit_array_end = .;
+
+    . = ALIGN(4);
+    __init_array_start = .;
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    __init_array_end = .;
+
+    . = ALIGN(0x4);
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+
+    . = ALIGN(4);
+    KEEP(*(.fini))
+
+    . = ALIGN(4);
+    __fini_array_start = .;
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    __fini_array_end = .;
+
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    . = ALIGN(4);
+    __cs3_regions = .;
+    LONG (0)
+    LONG (__cs3_region_init_ram)
+    LONG (__cs3_region_start_ram)
+    LONG (__cs3_region_init_size_ram)
+    LONG (__cs3_region_zero_size_ram)
+  }
+
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >rom
+  __exidx_end = .;
+  .text.align :
+  {
+    . = ALIGN(8);
+    _etext = .;
+  } >rom
+  __cs3_region_size_rom = LENGTH(rom);
+  __cs3_region_num = 1;
+
+  .data :
+  {
+    __cs3_region_start_ram = .;
+    *(.cs3.region-head.ram)
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    *(.ram)
+    . = ALIGN (8);
+    _edata = .;
+  } >ram AT>rom
+  .bss :
+  {
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    *(.ram.b)
+    . = ALIGN (8);
+    _end = .;
+    __end = .;
+  } >ram AT>rom
+  .heap :
+  {
+    *(.heap)
+  } >ram
+  .stack (__cs3_stack - __cs3_stack_size) :
+  {
+    *(.stack)
+  } >ram
+  __cs3_region_init_ram = LOADADDR (.data);
+  __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
+  __cs3_region_zero_size_ram = _end - _edata;
+  __cs3_region_size_ram = LENGTH(ram);
+  __cs3_region_num = 1;
+
+  .stab 0 (NOLOAD) : { *(.stab) }
+  .stabstr 0 (NOLOAD) : { *(.stabstr) }
+  /* DWARF debug sections.
+   * Symbols in the DWARF debugging sections are relative to the beginning
+   * of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_class_marks_example.ini b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_class_marks_example.ini
new file mode 100644
index 0000000..0ca6ba5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_class_marks_example.ini
@@ -0,0 +1,14 @@
+
+/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions 
+   
+   The file can be executed in the following way:
+   1) manually from uVision command window (in debug mode) using command:
+   INCLUIDE arm_class_marks_example.ini	 
+
+*/
+
+
+// usual initialisation	for target setup
+MAP  0x20000000, 0x20008000  READ WRITE  // allow R/W access to IO space
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvopt
new file mode 100644
index 0000000..4efa018
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvopt
@@ -0,0 +1,261 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x3
+    ARM-GNU
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        120
+        65
+        8
+        .\debug\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        SARMCM3.DLL
+        
+        DARMCM1.DLL
+        -pCM0
+        SARMCM3.DLL
+        
+        TARMCM1.DLL
+        -pCM0
+      
+      
+        1
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        1
+        1
+        0
+        1
+        0
+        0
+        -1
+        
+        
+        
+        
+        .\arm_class_marks_example.ini
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          -T0
+        
+      
+      
+        
+          0
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+          193
+          1
+          
268

+          0
+          0
+          0
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+          
+          
+          \\arm_cortexM0l_class_marks_example\../arm_class_marks_example_f32.c\193
+        
+      
+      
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+        0
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+        0
+        0
+      
+      
+      
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+
+  
+    Source Group 1
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+    
+      1
+      1
+      1
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+      0
+      0
+      0
+      183
+      193
+      0
+      ../arm_class_marks_example_f32.c
+      arm_class_marks_example_f32.c
+    
+  
+
+  
+    CMSIS Device
+    1
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ../system_ARMCM0.c
+      system_ARMCM0.c
+    
+    
+      2
+      3
+      2
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      .\startup_ARMCM0.s
+      startup_ARMCM0.s
+    
+  
+
+  
+    CMSIS SW_DSP_Library
+    1
+    0
+    0
+  
+
+  
+    1
+    0
+    
+      100
+      0
+      
+        
+          ../arm_class_marks_example_f32.c
+          0
+          183
+          193
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvproj
new file mode 100644
index 0000000..902e454
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM0l_class_marks_example.uvproj
@@ -0,0 +1,328 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x3
+      ARM-GNU
+      
+        
+          Cortex-M0
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE
+          
+          
+          
+          4803
+          
+          
+          
+          
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+          .\debug\
+          arm_cortexM0l_class_marks_example
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+          .\debug\
+          1
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+          
+        
+        
+          SARMCM3.DLL
+          
+          DARMCM1.DLL
+          -pCM0
+          SARMCM3.DLL
+          
+          TARMCM1.DLL
+          -pCM0
+        
+        
+          
+            1
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+          
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+          
+            
+            
+            
+            
+            .\arm_class_marks_example.ini
+          
+          
+            
+            
+            
+            
+            
+            
+          
+        
+        
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+            1
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+            "Cortex-M0"
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+            0
+            
+              
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+              
+            
+          
+          
+            1
+            0
+            0
+            1
+            0
+            0
+            1
+            2
+            1
+            
+              
+              ARM_MATH_CM0
+              
+              ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include
+            
+          
+          
+            0
+            1
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            1
+            
+            
+            
+            arm_cortexM0l_math
+            ..\..\..\..\Lib\GCC
+            -Wl,--gc-sections
+            ARMCMx.ld
+          
+        
+      
+      
+        
+          Source Group 1
+          
+            
+              arm_class_marks_example_f32.c
+              1
+              ../arm_class_marks_example_f32.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM0.c
+              1
+              ../system_ARMCM0.c
+            
+            
+              startup_ARMCM0.s
+              2
+              .\startup_ARMCM0.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvopt
new file mode 100644
index 0000000..d8322ed
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvopt
@@ -0,0 +1,261 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x3
+    ARM-GNU
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        120
+        65
+        8
+        .\debug\
+      
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+        1
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+      
+      255
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+        SARMCM3.DLL
+        
+        DCM.DLL
+        -pCM3
+        SARMCM3.DLL
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+        TCM.DLL
+        -pCM3
+      
+      
+        1
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+        1
+        1
+        1
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+        1
+        0
+        0
+        -1
+        
+        
+        
+        
+        .\arm_class_marks_example.ini
+        
+        
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+        
+        
+        
+      
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+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)
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+      arm_class_marks_example_f32.c
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+
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+      system_ARMCM3.c
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+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvproj
new file mode 100644
index 0000000..23eeea7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM3l_class_marks_example.uvproj
@@ -0,0 +1,328 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x3
+      ARM-GNU
+      
+        
+          Cortex-M3
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE
+          
+          
+          
+          4349
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
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+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\debug\
+          arm_cortexM3l_class_marks_example
+          1
+          0
+          0
+          1
+          0
+          .\debug\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
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+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          
+          DCM.DLL
+          -pCM3
+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM3
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            0
+            1
+            0
+            1
+            1
+            1
+            0
+            1
+          
+          0
+          -1
+          
+            
+            
+            
+            
+            .\arm_class_marks_example.ini
+          
+          
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            1
+            0
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+          
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+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            "Cortex-M3"
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+                0
+                0x0
+                0x0
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+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
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+                0x0
+              
+              
+                0
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+                0x0
+              
+              
+                0
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+                0x0
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+              
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+              
+              
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+                0x0
+              
+              
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+                0x0
+              
+            
+          
+          
+            1
+            0
+            0
+            1
+            0
+            0
+            1
+            2
+            1
+            
+              
+              ARM_MATH_CM3
+              
+              ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include
+            
+          
+          
+            0
+            1
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            1
+            
+            
+            
+            arm_cortexM3l_math
+            ..\..\..\..\Lib\GCC
+            -Wl,--gc-sections
+            ARMCMx.ld
+          
+        
+      
+      
+        
+          Source Group 1
+          
+            
+              arm_class_marks_example_f32.c
+              1
+              ../arm_class_marks_example_f32.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM3.c
+              1
+              ../system_ARMCM3.c
+            
+            
+              startup_ARMCM3.s
+              2
+              .\startup_ARMCM3.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvopt
new file mode 100644
index 0000000..d42b1f7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvopt
@@ -0,0 +1,261 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x3
+    ARM-GNU
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        120
+        65
+        8
+        .\debug\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      255
+      
+        SARMCM3.DLL
+        
+        DCM.DLL
+        -pCM3
+        SARMCM3.DLL
+        
+        TCM.DLL
+        -pCM3
+      
+      
+        1
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        1
+        1
+        0
+        1
+        0
+        0
+        -1
+        
+        
+        
+        
+        .\arm_class_marks_example.ini
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          -T0
+        
+      
+      
+        
+          0
+          0
+          193
+          1
+          
392

+          0
+          0
+          0
+          0
+          1
+          
+          
+          \\arm_cortexM4lf_class_marks_example\../arm_class_marks_example_f32.c\193
+        
+      
+      
+        0
+        0
+        1
+        0
+        0
+        0
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+        1
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+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+    
+  
+
+  
+    Source Group 1
+    1
+    0
+    0
+    
+      1
+      1
+      1
+      0
+      0
+      0
+      0
+      183
+      193
+      0
+      ../arm_class_marks_example_f32.c
+      arm_class_marks_example_f32.c
+    
+  
+
+  
+    CMSIS Device
+    1
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ../system_ARMCM4.c
+      system_ARMCM4.c
+    
+    
+      2
+      3
+      2
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      .\startup_ARMCM4.s
+      startup_ARMCM4.s
+    
+  
+
+  
+    CMSIS SW_DSP_Library
+    1
+    0
+    0
+  
+
+  
+    1
+    0
+    
+      100
+      0
+      
+        
+          ../arm_class_marks_example_f32.c
+          0
+          183
+          193
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvproj
new file mode 100644
index 0000000..16828d0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/arm_cortexM4lf_class_marks_example.uvproj
@@ -0,0 +1,328 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x3
+      ARM-GNU
+      
+        
+          Cortex-M4 FPU
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2
+          
+          
+          
+          5237
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\debug\
+          arm_cortexM4lf_class_marks_example
+          1
+          0
+          0
+          1
+          0
+          .\debug\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          
+          DCM.DLL
+          -pCM3
+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM3
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            0
+            1
+            0
+            1
+            1
+            1
+            0
+            1
+          
+          0
+          -1
+          
+            
+            
+            
+            
+            .\arm_class_marks_example.ini
+          
+          
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            0
+            -1
+          
+          
+          
+          
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            "Cortex-M4"
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+          
+          
+            1
+            0
+            0
+            1
+            0
+            0
+            1
+            2
+            1
+            
+              -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -fno-strict-aliasing -ffunction-sections
+              ARM_MATH_CM4, __FPU_PRESENT = 1
+              
+              ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include
+            
+          
+          
+            0
+            1
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            1
+            
+            
+            
+            arm_cortexM4lf_math
+            ..\..\..\..\Lib\GCC
+            -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections
+            ARMCMx.ld
+          
+        
+      
+      
+        
+          Source Group 1
+          
+            
+              arm_class_marks_example_f32.c
+              1
+              ../arm_class_marks_example_f32.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM4.c
+              1
+              ../system_ARMCM4.c
+            
+            
+              startup_ARMCM4.s
+              2
+              .\startup_ARMCM4.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM0.s
new file mode 100644
index 0000000..faa7909
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM0.s
@@ -0,0 +1,155 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM0.s
+ * @brief    CMSIS Cortex-M0 Core Device Startup File
+ *           for CM0 Device Series
+ * @version  V1.04
+ * @date     14. January 2011
+ *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+ *
+ ******************************************************************************/
+
+/*****************************************************************************/
+/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
+/*****************************************************************************/
+
+
+/*
+//  Stack Configuration
+//    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Stack_Size, 0x00000100
+    .section ".stack", "w"
+    .align  3
+    .globl  __cs3_stack_mem
+    .globl  __cs3_stack_size
+__cs3_stack_mem:
+    .if     Stack_Size
+    .space  Stack_Size
+    .endif
+    .size   __cs3_stack_mem,  . - __cs3_stack_mem
+    .set    __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+//  Heap Configuration
+//     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Heap_Size,  0x00001000
+    
+    .section ".heap", "w"
+    .align  3
+    .globl  __cs3_heap_start
+    .globl  __cs3_heap_end
+__cs3_heap_start:
+    .if     Heap_Size
+    .space  Heap_Size
+    .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+    .section ".cs3.interrupt_vector"
+    .globl  __cs3_interrupt_vector_cortex_m
+    .type   __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+    .long   __cs3_stack                 /* Top of Stack                 */
+    .long   __cs3_reset                 /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+    /* External Interrupts */
+    .long   DEF_IRQHandler              /*  0: Default                  */
+
+
+    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+    .thumb
+
+
+/* Reset Handler */
+
+    .section .cs3.reset,"x",%progbits
+    .thumb_func
+    .globl  __cs3_reset_cortex_m
+    .type   __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+    .fnstart
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0,=_start
+    BX      R0
+    .pool
+    .cantunwind
+    .fnend
+    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ     DEF_IRQHandler
+
+    .end
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM3.s
new file mode 100644
index 0000000..07b53c8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM3.s
@@ -0,0 +1,179 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM3.s
+ * @brief    CMSIS Cortex-M3 Core Device Startup File
+ *           for CM3 Device Series
+ * @version  V1.04
+ * @date     14. January 2011
+ *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+ *
+ ******************************************************************************/
+
+/*****************************************************************************/
+/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
+/*****************************************************************************/
+
+
+/*
+//  Stack Configuration
+//    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Stack_Size, 0x00000100
+    .section ".stack", "w"
+    .align  3
+    .globl  __cs3_stack_mem
+    .globl  __cs3_stack_size
+__cs3_stack_mem:
+    .if     Stack_Size
+    .space  Stack_Size
+    .endif
+    .size   __cs3_stack_mem,  . - __cs3_stack_mem
+    .set    __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+//  Heap Configuration
+//     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Heap_Size,  0x00001000
+    
+    .section ".heap", "w"
+    .align  3
+    .globl  __cs3_heap_start
+    .globl  __cs3_heap_end
+__cs3_heap_start:
+    .if     Heap_Size
+    .space  Heap_Size
+    .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+    .section ".cs3.interrupt_vector"
+    .globl  __cs3_interrupt_vector_cortex_m
+    .type   __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+    .long   __cs3_stack                 /* Top of Stack                 */
+    .long   __cs3_reset                 /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   MemManage_Handler           /* MPU Fault Handler            */
+    .long   BusFault_Handler            /* Bus Fault Handler            */
+    .long   UsageFault_Handler          /* Usage Fault Handler          */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   DebugMon_Handler            /* Debug Monitor Handler        */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+    /* External Interrupts */
+    .long   DEF_IRQHandler              /*  0: Default                  */
+
+
+    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+    .thumb
+
+
+/* Reset Handler */
+
+    .section .cs3.reset,"x",%progbits
+    .thumb_func
+    .globl  __cs3_reset_cortex_m
+    .type   __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+    .fnstart
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0,=_start
+    BX      R0
+    .pool
+    .cantunwind
+    .fnend
+    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B       .
+    .size   MemManage_Handler, . - MemManage_Handler
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B       .
+    .size   DebugMon_Handler, . - DebugMon_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ     DEF_IRQHandler
+
+    .end
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM4.s
new file mode 100644
index 0000000..004d001
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/GCC/startup_ARMCM4.s
@@ -0,0 +1,179 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM4.s
+ * @brief    CMSIS Cortex-M4 Core Device Startup File
+ *           for CM4 Device Series
+ * @version  V1.04
+ * @date     14. January 2011
+ *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+ *
+ ******************************************************************************/
+
+/*****************************************************************************/
+/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
+/*****************************************************************************/
+
+
+/*
+//  Stack Configuration
+//    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Stack_Size, 0x00000100
+    .section ".stack", "w"
+    .align  3
+    .globl  __cs3_stack_mem
+    .globl  __cs3_stack_size
+__cs3_stack_mem:
+    .if     Stack_Size
+    .space  Stack_Size
+    .endif
+    .size   __cs3_stack_mem,  . - __cs3_stack_mem
+    .set    __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+//  Heap Configuration
+//     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Heap_Size,  0x00001000
+    
+    .section ".heap", "w"
+    .align  3
+    .globl  __cs3_heap_start
+    .globl  __cs3_heap_end
+__cs3_heap_start:
+    .if     Heap_Size
+    .space  Heap_Size
+    .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+    .section ".cs3.interrupt_vector"
+    .globl  __cs3_interrupt_vector_cortex_m
+    .type   __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+    .long   __cs3_stack                 /* Top of Stack                 */
+    .long   __cs3_reset                 /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   MemManage_Handler           /* MPU Fault Handler            */
+    .long   BusFault_Handler            /* Bus Fault Handler            */
+    .long   UsageFault_Handler          /* Usage Fault Handler          */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   DebugMon_Handler            /* Debug Monitor Handler        */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+    /* External Interrupts */
+    .long   DEF_IRQHandler              /*  0: Default                  */
+
+
+    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+    .thumb
+
+
+/* Reset Handler */
+
+    .section .cs3.reset,"x",%progbits
+    .thumb_func
+    .globl  __cs3_reset_cortex_m
+    .type   __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+    .fnstart
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0,=_start
+    BX      R0
+    .pool
+    .cantunwind
+    .fnend
+    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B       .
+    .size   MemManage_Handler, . - MemManage_Handler
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B       .
+    .size   DebugMon_Handler, . - DebugMon_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ     DEF_IRQHandler
+
+    .end
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/arm_class_marks_example_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/arm_class_marks_example_f32.c
new file mode 100644
index 0000000..c194c7a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/arm_class_marks_example_f32.c
@@ -0,0 +1,196 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision: 	V1.0.3 
+*  
+* Project: 	    CMSIS DSP Library  
+* Title:        arm_class_marks_example_f32.c		  
+*  
+* Description:	Example code to calculate Minimum, Maximum 
+*               Mean, std and variance of marks obtained in a class 
+* 
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+*  
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+/** 
+ * @ingroup groupExamples 
+ */ 
+ 
+/**    
+ * @defgroup ClassMarks Class Marks Example  
+ *
+ * \par Description: 
+ * \par
+ * Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance
+ * and Matrix functions to calculate statistical values of marks obtained in a class.
+ *
+ * \note This example also demonstrates the usage of static initialization.
+ *  
+ * \par Variables Description:
+ * \par
+ * \li \c testMarks_f32 points to the marks scored by 20 students in 4 subjects
+ * \li \c max_marks     Maximum of all marks 
+ * \li \c min_marks     Minimum of all marks 
+ * \li \c mean          Mean of all marks
+ * \li \c var           Variance of the marks
+ * \li \c std           Standard deviation of the marks 
+ * \li \c numStudents   Total number of students in the class
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_mat_init_f32()
+ * - arm_mat_mult_f32()
+ * - arm_max_f32()
+ * - arm_min_f32()
+ * - arm_mean_f32()
+ * - arm_std_f32()
+ * - arm_var_f32()
+ * 
+ *  Refer   
+ * \link arm_class_marks_example_f32.c \endlink
+ * 
+ */ 
+ 
+ 
+/** \example arm_class_marks_example_f32.c 
+  */  
+#include "arm_math.h" 
+
+#define USE_STATIC_INIT 
+ 
+ /* ---------------------------------------------------------------------- 
+** Global defines  
+** ------------------------------------------------------------------- */ 
+ 
+#define TEST_LENGTH_SAMPLES 	(20*4) 
+ 
+/* ---------------------------------------------------------------------- 
+** List of Marks scored by 20 students for 4 subjects 
+** ------------------------------------------------------------------- */  
+const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] =  
+{    
+	42.000000,	37.000000,	81.000000,	28.000000,	 
+	83.000000,	72.000000,	36.000000,	38.000000,	 
+	32.000000,	51.000000,	63.000000,	64.000000,	 
+	97.000000,	82.000000,	95.000000,	90.000000,	 
+	66.000000,	51.000000,	54.000000,	42.000000,	 
+	67.000000,	56.000000,	45.000000,	57.000000,	 
+	67.000000,	69.000000,	35.000000,	52.000000,	 
+	29.000000,	81.000000,	58.000000,	47.000000,	 
+	38.000000,	76.000000,	100.000000,	29.000000,	 
+	33.000000,	47.000000,	29.000000,	50.000000,	 
+	34.000000,	41.000000,	61.000000,	46.000000,	 
+	52.000000,	50.000000,	48.000000,	36.000000,	 
+	47.000000,	55.000000,	44.000000,	40.000000,	 
+	100.000000,	94.000000,	84.000000,	37.000000,	 
+	32.000000,	71.000000,	47.000000,	77.000000,	 
+	31.000000,	50.000000,	49.000000,	35.000000,	 
+	63.000000,	67.000000,	40.000000,	31.000000,	 
+	29.000000,	68.000000,	61.000000,	38.000000,	 
+	31.000000,	28.000000,	28.000000,	76.000000,	 
+	55.000000,	33.000000,	29.000000,	39.000000 
+};  
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Number of subjects X 1  
+* ------------------------------------------------------------------- */  
+const float32_t testUnity_f32[4] =  
+{    
+	1.000,  1.000, 	1.000,  1.000 
+}; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+** f32 Output buffer 
+** ------------------------------------------------------------------- */  
+static float32_t testOutput[TEST_LENGTH_SAMPLES]; 
+ 
+ 
+/* ------------------------------------------------------------------ 
+* Global defines  
+*------------------------------------------------------------------- */ 
+#define 	NUMSTUDENTS  20 
+#define     NUMSUBJECTS  4 
+ 
+/* ------------------------------------------------------------------ 
+* Global variables  
+*------------------------------------------------------------------- */ 
+ 
+uint32_t  	numStudents = 20; 
+uint32_t  	numSubjects = 4;  
+float32_t	max_marks, min_marks, mean, std, var; 
+uint32_t 	student_num;    
+ 
+/* ---------------------------------------------------------------------------------- 
+* Main f32 test function.  It returns maximum marks secured and student number 
+* ------------------------------------------------------------------------------- */ 
+ 
+int32_t main() 
+{ 
+ 
+#ifndef  USE_STATIC_INIT 
+ 
+  	arm_matrix_instance_f32 srcA; 
+  	arm_matrix_instance_f32 srcB; 
+  	arm_matrix_instance_f32 dstC;  
+ 
+	/* Input and output matrices initializations */  
+	arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32);  
+	arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32);  
+	arm_mat_init_f32(&dstC, numStudents, 1, testOutput);  
+ 
+#else 
+ 
+	/* Static Initializations of Input and output matrix sizes and array */ 
+	arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32}; 
+	arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32}; 
+	arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput}; 
+ 
+#endif 
+ 
+	 
+	/* ---------------------------------------------------------------------- 
+	*Call the Matrix multiplication process function   
+	* ------------------------------------------------------------------- */ 
+	arm_mat_mult_f32(&srcA, &srcB, &dstC); 
+	 
+	/* ---------------------------------------------------------------------- 
+	** Call the Max function to calculate max marks among numStudents 
+	** ------------------------------------------------------------------- */ 
+	arm_max_f32(testOutput, numStudents, &max_marks, &student_num);  
+ 
+	/* ---------------------------------------------------------------------- 
+	** Call the Min function to calculate min marks among numStudents 
+	** ------------------------------------------------------------------- */ 
+	arm_min_f32(testOutput, numStudents, &min_marks, &student_num);  
+ 
+	/* ---------------------------------------------------------------------- 
+	** Call the Mean function to calculate mean 
+	** ------------------------------------------------------------------- */ 
+	arm_mean_f32(testOutput, numStudents, &mean); 
+ 
+	/* ---------------------------------------------------------------------- 
+	** Call the std function to calculate standard deviation 
+	** ------------------------------------------------------------------- */ 
+	arm_std_f32(testOutput, numStudents, &std); 
+ 
+	/* ---------------------------------------------------------------------- 
+	** Call the var function to calculate variance 
+	** ------------------------------------------------------------------- */ 
+	arm_var_f32(testOutput, numStudents, &var); 
+ 
+    while(1);                             /* main function does not return */
+} 
+ 
+ 
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM0.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM0.c
new file mode 100644
index 0000000..ece74d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM0.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Cortex-M0 Device System Source File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM3.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM3.c
new file mode 100644
index 0000000..2f5fa0b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM3.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Cortex-M3 Device System Source File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM4.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM4.c
new file mode 100644
index 0000000..beaaf6f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_class_marks_example/system_ARMCM4.c
@@ -0,0 +1,81 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Cortex-M4 Device System Source File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM4.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_convolution_example.ini b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_convolution_example.ini
new file mode 100644
index 0000000..5509390
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_convolution_example.ini
@@ -0,0 +1,14 @@
+
+/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions 
+   
+   The file can be executed in the following way:
+   1) manually from uVision command window (in debug mode) using command:
+   INCLUIDE arm_convolution_example.ini	 
+
+*/
+
+
+// usual initialisation	for target setup
+MAP  0x20000000, 0x20008000  READ WRITE  // allow R/W access to IO space
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvopt
new file mode 100644
index 0000000..06c25dd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvopt
@@ -0,0 +1,325 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\debug\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
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+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        SARMCM3.DLL
+        
+        DARMCM1.DLL
+        -pCM0
+        SARMCM3.DLL
+        
+        TARMCM1.DLL
+        -pCM0
+      
+      
+        1
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        1
+        1
+        0
+        1
+        0
+        0
+        -1
+        
+        
+        
+        
+        .\arm_convolution_example.ini
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          -T0
+        
+      
+      
+        
+          0
+          0
+          94
+          1
+          
1414

+          0
+          0
+          0
+          0
+          1
+          
+          
+          \\arm_cortexM0l_convolution_example\startup_ARMCM0.s\94
+        
+        
+          1
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+          228
+          1
+          
384

+          0
+          0
+          0
+          0
+          1
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+          
+          \\arm_cortexM0l_convolution_example\../arm_convolution_example_f32.c\228
+        
+        
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+          225
+          1
+          
382

+          0
+          0
+          0
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+          1
+          
+          
+          \\arm_cortexM0l_convolution_example\../arm_convolution_example_f32.c\225
+        
+      
+      
+        1
+        0
+        1
+        0
+        0
+        0
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+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+    
+  
+
+  
+    Source Group 1
+    1
+    0
+    0
+    
+      1
+      1
+      1
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+      0
+      0
+      0
+      218
+      228
+      0
+      ..\arm_convolution_example_f32.c
+      arm_convolution_example_f32.c
+    
+    
+      1
+      2
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\Common\Source\math_helper.c
+      math_helper.c
+    
+  
+
+  
+    CMSIS Device
+    1
+    0
+    0
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\system_ARMCM0.c
+      system_ARMCM0.c
+    
+    
+      2
+      4
+      2
+      0
+      0
+      0
+      0
+      78
+      78
+      0
+      .\startup_ARMCM0.s
+      startup_ARMCM0.s
+    
+  
+
+  
+    CMSIS SW_DSP_library
+    1
+    0
+    0
+    
+      3
+      5
+      4
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib
+      arm_cortexM0l_math.lib
+    
+  
+
+  
+    1
+    0
+    
+      100
+      1
+      
+        
+          .\startup_ARMCM0.s
+          0
+          78
+          78
+        
+        
+          ..\arm_convolution_example_f32.c
+          0
+          218
+          228
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvproj
new file mode 100644
index 0000000..e2f1000
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM0l_convolution_example.uvproj
@@ -0,0 +1,430 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M0
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE
+          
+          
+          
+          4803
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\debug\
+          arm_cortexM0l_convolution_example
+          1
+          0
+          0
+          1
+          1
+          .\debug\
+          1
+          0
+          0
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+            0
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+          0
+          0
+          0
+          1
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+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          
+          DARMCM1.DLL
+          -pCM0
+          SARMCM3.DLL
+          
+          TARMCM1.DLL
+          -pCM0
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
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+          
+          
+            0
+            1
+            0
+            1
+            1
+            1
+            0
+            1
+          
+          0
+          -1
+          
+            
+            
+            
+            
+            .\arm_convolution_example.ini
+          
+          
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            0
+            -1
+          
+          
+          "" ()
+          
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
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+            1
+            1
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+            1
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+            1
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+            "Cortex-M0"
+            
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+            0
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+              
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+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              ARM_MATH_CM0
+              
+              ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
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+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Source Group 1
+          
+            
+              arm_convolution_example_f32.c
+              1
+              ..\arm_convolution_example_f32.c
+            
+            
+              math_helper.c
+              1
+              ..\..\Common\Source\math_helper.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM0.c
+              1
+              ..\system_ARMCM0.c
+            
+            
+              startup_ARMCM0.s
+              2
+              .\startup_ARMCM0.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+          
+            
+              arm_cortexM0l_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvopt
new file mode 100644
index 0000000..6318984
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvopt
@@ -0,0 +1,310 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\debug\
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+      
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+        
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+        SARMCM3.DLL
+        
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+        -pCM3
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+        1
+        1
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+        1
+        0
+        0
+        -1
+        
+        
+        
+        
+        .\arm_convolution_example.ini
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)
+        
+        
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380

+          0
+          0
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+          1
+          
382

+          0
+          0
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+          
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+
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+      228
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+      arm_convolution_example_f32.c
+    
+    
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+      math_helper.c
+    
+  
+
+  
+    CMSIS Device
+    1
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+    
+      2
+      3
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+      system_ARMCM3.c
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+
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+      arm_cortexM3l_math.lib
+    
+  
+
+  
+    1
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+    
+      100
+      0
+      
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+          ..\arm_convolution_example_f32.c
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+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvproj
new file mode 100644
index 0000000..e21b525
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM3l_convolution_example.uvproj
@@ -0,0 +1,430 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M3
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE
+          
+          
+          
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+          arm_cortexM3l_convolution_example
+          1
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+              
+              ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM3\Include
+            
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+          Source Group 1
+          
+            
+              arm_convolution_example_f32.c
+              1
+              ..\arm_convolution_example_f32.c
+            
+            
+              math_helper.c
+              1
+              ..\..\Common\Source\math_helper.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM3.c
+              1
+              ..\system_ARMCM3.c
+            
+            
+              startup_ARMCM3.s
+              2
+              .\startup_ARMCM3.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+          
+            
+              arm_cortexM3l_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvopt
new file mode 100644
index 0000000..1976ab0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvopt
@@ -0,0 +1,310 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
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+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
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+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)
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+      arm_cortexM4lf_math.lib
+    
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvproj
new file mode 100644
index 0000000..5f10472
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/arm_cortexM4lf_convolution_example.uvproj
@@ -0,0 +1,430 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M4 FPU
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2
+          
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+              
+              ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include
+            
+          
+          
+            1
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+      
+      
+        
+          Source Group 1
+          
+            
+              arm_convolution_example_f32.c
+              1
+              ..\arm_convolution_example_f32.c
+            
+            
+              math_helper.c
+              1
+              ..\..\Common\Source\math_helper.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM4.c
+              1
+              ..\system_ARMCM4.c
+            
+            
+              startup_ARMCM4.s
+              2
+              .\startup_ARMCM4.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+          
+            
+              arm_cortexM4lf_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..0acd346
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM0.s
@@ -0,0 +1,144 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Cortex-M0 Core Device Startup File
+; *           for CM0 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..5af584b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM3.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Cortex-M3 Core Device Startup File
+; *           for CM3 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..09fdbd6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/ARM/startup_ARMCM4.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM4 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/ARMCMx.ld b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/ARMCMx.ld
new file mode 100644
index 0000000..9cf8c92
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/ARMCMx.ld
@@ -0,0 +1,198 @@
+/* Linker script for Cortex-M0
+ *
+ * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ *  Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(_start)
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)
+
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00000000, LENGTH = 64K
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH =  8K
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_cortex_m)
+EXTERN(__cs3_interrupt_vector_cortex_m)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __cs3_region_start_rom = .;
+    *(.cs3.region-head.rom)
+    __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
+    *(.cs3.interrupt_vector)
+    /* Make sure we pulled in an interrupt vector.  */
+    ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
+    *(.rom)
+    *(.rom.b)
+
+    __cs3_reset = __cs3_reset_cortex_m;
+    *(.cs3.reset)
+    /* Make sure we pulled in some reset code.  */
+    ASSERT (. != __cs3_reset, "No reset code");
+
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table)
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    . = ALIGN(4);
+    KEEP(*(.init))
+
+    . = ALIGN(4);
+    __preinit_array_start = .;
+    KEEP (*(.preinit_array))
+    __preinit_array_end = .;
+
+    . = ALIGN(4);
+    __init_array_start = .;
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    __init_array_end = .;
+
+    . = ALIGN(0x4);
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+
+    . = ALIGN(4);
+    KEEP(*(.fini))
+
+    . = ALIGN(4);
+    __fini_array_start = .;
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    __fini_array_end = .;
+
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    . = ALIGN(4);
+    __cs3_regions = .;
+    LONG (0)
+    LONG (__cs3_region_init_ram)
+    LONG (__cs3_region_start_ram)
+    LONG (__cs3_region_init_size_ram)
+    LONG (__cs3_region_zero_size_ram)
+  }
+
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >rom
+  __exidx_end = .;
+  .text.align :
+  {
+    . = ALIGN(8);
+    _etext = .;
+  } >rom
+  __cs3_region_size_rom = LENGTH(rom);
+  __cs3_region_num = 1;
+
+  .data :
+  {
+    __cs3_region_start_ram = .;
+    *(.cs3.region-head.ram)
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    *(.ram)
+    . = ALIGN (8);
+    _edata = .;
+  } >ram AT>rom
+  .bss :
+  {
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    *(.ram.b)
+    . = ALIGN (8);
+    _end = .;
+    __end = .;
+  } >ram AT>rom
+  .heap :
+  {
+    *(.heap)
+  } >ram
+  .stack (__cs3_stack - __cs3_stack_size) :
+  {
+    *(.stack)
+  } >ram
+  __cs3_region_init_ram = LOADADDR (.data);
+  __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
+  __cs3_region_zero_size_ram = _end - _edata;
+  __cs3_region_size_ram = LENGTH(ram);
+  __cs3_region_num = 1;
+
+  .stab 0 (NOLOAD) : { *(.stab) }
+  .stabstr 0 (NOLOAD) : { *(.stabstr) }
+  /* DWARF debug sections.
+   * Symbols in the DWARF debugging sections are relative to the beginning
+   * of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_convolution_example.ini b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_convolution_example.ini
new file mode 100644
index 0000000..5509390
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_convolution_example.ini
@@ -0,0 +1,14 @@
+
+/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions 
+   
+   The file can be executed in the following way:
+   1) manually from uVision command window (in debug mode) using command:
+   INCLUIDE arm_convolution_example.ini	 
+
+*/
+
+
+// usual initialisation	for target setup
+MAP  0x20000000, 0x20008000  READ WRITE  // allow R/W access to IO space
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvopt
new file mode 100644
index 0000000..e7a7637
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvopt
@@ -0,0 +1,290 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x3
+    ARM-GNU
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        120
+        65
+        8
+        .\debug\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        SARMCM3.DLL
+        
+        DARMCM1.DLL
+        -pCM0
+        SARMCM3.DLL
+        
+        TARMCM1.DLL
+        -pCM0
+      
+      
+        1
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        1
+        1
+        0
+        1
+        0
+        0
+        -1
+        
+        
+        
+        
+        .\arm_convolution_example.ini
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          -T0
+        
+      
+      
+        
+          0
+          0
+          228
+          1
+          
398

+          0
+          0
+          0
+          0
+          1
+          
+          
+          \\arm_cortexM0l_convolution_example\../arm_convolution_example_f32.c\228
+        
+        
+          1
+          0
+          225
+          1
+          
396

+          0
+          0
+          0
+          0
+          1
+          
+          
+          \\arm_cortexM0l_convolution_example\../arm_convolution_example_f32.c\225
+        
+      
+      
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+    
+  
+
+  
+    Source Group 1
+    1
+    0
+    0
+    
+      1
+      1
+      1
+      0
+      0
+      0
+      0
+      218
+      228
+      0
+      ../arm_convolution_example_f32.c
+      arm_convolution_example_f32.c
+    
+    
+      1
+      2
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ../../Common/Source/math_helper.c
+      math_helper.c
+    
+  
+
+  
+    CMSIS Device
+    1
+    0
+    0
+    
+      2
+      3
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ../system_ARMCM0.c
+      system_ARMCM0.c
+    
+    
+      2
+      4
+      2
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      .\startup_ARMCM0.s
+      startup_ARMCM0.s
+    
+  
+
+  
+    CMSIS SW_DSP_library
+    1
+    0
+    0
+  
+
+  
+    1
+    0
+    
+      100
+      0
+      
+        
+          ../arm_convolution_example_f32.c
+          0
+          218
+          228
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvproj
new file mode 100644
index 0000000..12121a5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/arm_cortexM0l_convolution_example.uvproj
@@ -0,0 +1,333 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x3
+      ARM-GNU
+      
+        
+          Cortex-M0
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE
+          
+          
+          
+          4803
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\debug\
+          arm_cortexM0l_convolution_example
+          1
+          0
+          0
+          1
+          0
+          .\debug\
+          1
+          0
+          0
+          
+            0
+            0
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index 0000000..8d0514a
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### uVision Project, (C) Keil Software

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new file mode 100644
index 0000000..eda231e
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### uVision Project, (C) Keil Software

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+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+          
+          
+            1
+            0
+            0
+            1
+            0
+            0
+            1
+            2
+            1
+            
+              -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -fno-strict-aliasing -ffunction-sections
+              ARM_MATH_CM4, __FPU_PRESENT = 1
+              
+              ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include
+            
+          
+          
+            0
+            1
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            1
+            
+            
+            
+            arm_cortexM4lf_math
+            ..\..\..\..\Lib\GCC
+            -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections
+            ARMCMx.ld
+          
+        
+      
+      
+        
+          Source Group 1
+          
+            
+              arm_convolution_example_f32.c
+              1
+              ../arm_convolution_example_f32.c
+            
+            
+              math_helper.c
+              1
+              ../../Common/Source/math_helper.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM4.c
+              1
+              ../system_ARMCM4.c
+            
+            
+              startup_ARMCM4.s
+              2
+              .\startup_ARMCM4.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM0.s
new file mode 100644
index 0000000..faa7909
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM0.s
@@ -0,0 +1,155 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM0.s
+ * @brief    CMSIS Cortex-M0 Core Device Startup File
+ *           for CM0 Device Series
+ * @version  V1.04
+ * @date     14. January 2011
+ *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+ *
+ ******************************************************************************/
+
+/*****************************************************************************/
+/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
+/*****************************************************************************/
+
+
+/*
+//  Stack Configuration
+//    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Stack_Size, 0x00000100
+    .section ".stack", "w"
+    .align  3
+    .globl  __cs3_stack_mem
+    .globl  __cs3_stack_size
+__cs3_stack_mem:
+    .if     Stack_Size
+    .space  Stack_Size
+    .endif
+    .size   __cs3_stack_mem,  . - __cs3_stack_mem
+    .set    __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+//  Heap Configuration
+//     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Heap_Size,  0x00001000
+    
+    .section ".heap", "w"
+    .align  3
+    .globl  __cs3_heap_start
+    .globl  __cs3_heap_end
+__cs3_heap_start:
+    .if     Heap_Size
+    .space  Heap_Size
+    .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+    .section ".cs3.interrupt_vector"
+    .globl  __cs3_interrupt_vector_cortex_m
+    .type   __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+    .long   __cs3_stack                 /* Top of Stack                 */
+    .long   __cs3_reset                 /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+    /* External Interrupts */
+    .long   DEF_IRQHandler              /*  0: Default                  */
+
+
+    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+    .thumb
+
+
+/* Reset Handler */
+
+    .section .cs3.reset,"x",%progbits
+    .thumb_func
+    .globl  __cs3_reset_cortex_m
+    .type   __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+    .fnstart
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0,=_start
+    BX      R0
+    .pool
+    .cantunwind
+    .fnend
+    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ     DEF_IRQHandler
+
+    .end
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM3.s
new file mode 100644
index 0000000..07b53c8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM3.s
@@ -0,0 +1,179 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM3.s
+ * @brief    CMSIS Cortex-M3 Core Device Startup File
+ *           for CM3 Device Series
+ * @version  V1.04
+ * @date     14. January 2011
+ *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+ *
+ ******************************************************************************/
+
+/*****************************************************************************/
+/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
+/*****************************************************************************/
+
+
+/*
+//  Stack Configuration
+//    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Stack_Size, 0x00000100
+    .section ".stack", "w"
+    .align  3
+    .globl  __cs3_stack_mem
+    .globl  __cs3_stack_size
+__cs3_stack_mem:
+    .if     Stack_Size
+    .space  Stack_Size
+    .endif
+    .size   __cs3_stack_mem,  . - __cs3_stack_mem
+    .set    __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+//  Heap Configuration
+//     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Heap_Size,  0x00001000
+    
+    .section ".heap", "w"
+    .align  3
+    .globl  __cs3_heap_start
+    .globl  __cs3_heap_end
+__cs3_heap_start:
+    .if     Heap_Size
+    .space  Heap_Size
+    .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+    .section ".cs3.interrupt_vector"
+    .globl  __cs3_interrupt_vector_cortex_m
+    .type   __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+    .long   __cs3_stack                 /* Top of Stack                 */
+    .long   __cs3_reset                 /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   MemManage_Handler           /* MPU Fault Handler            */
+    .long   BusFault_Handler            /* Bus Fault Handler            */
+    .long   UsageFault_Handler          /* Usage Fault Handler          */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   DebugMon_Handler            /* Debug Monitor Handler        */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+    /* External Interrupts */
+    .long   DEF_IRQHandler              /*  0: Default                  */
+
+
+    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+    .thumb
+
+
+/* Reset Handler */
+
+    .section .cs3.reset,"x",%progbits
+    .thumb_func
+    .globl  __cs3_reset_cortex_m
+    .type   __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+    .fnstart
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0,=_start
+    BX      R0
+    .pool
+    .cantunwind
+    .fnend
+    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B       .
+    .size   MemManage_Handler, . - MemManage_Handler
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B       .
+    .size   DebugMon_Handler, . - DebugMon_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ     DEF_IRQHandler
+
+    .end
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM4.s
new file mode 100644
index 0000000..004d001
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/GCC/startup_ARMCM4.s
@@ -0,0 +1,179 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM4.s
+ * @brief    CMSIS Cortex-M4 Core Device Startup File
+ *           for CM4 Device Series
+ * @version  V1.04
+ * @date     14. January 2011
+ *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+ *
+ ******************************************************************************/
+
+/*****************************************************************************/
+/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
+/*****************************************************************************/
+
+
+/*
+//  Stack Configuration
+//    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Stack_Size, 0x00000100
+    .section ".stack", "w"
+    .align  3
+    .globl  __cs3_stack_mem
+    .globl  __cs3_stack_size
+__cs3_stack_mem:
+    .if     Stack_Size
+    .space  Stack_Size
+    .endif
+    .size   __cs3_stack_mem,  . - __cs3_stack_mem
+    .set    __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+//  Heap Configuration
+//     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Heap_Size,  0x00001000
+    
+    .section ".heap", "w"
+    .align  3
+    .globl  __cs3_heap_start
+    .globl  __cs3_heap_end
+__cs3_heap_start:
+    .if     Heap_Size
+    .space  Heap_Size
+    .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+    .section ".cs3.interrupt_vector"
+    .globl  __cs3_interrupt_vector_cortex_m
+    .type   __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+    .long   __cs3_stack                 /* Top of Stack                 */
+    .long   __cs3_reset                 /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   MemManage_Handler           /* MPU Fault Handler            */
+    .long   BusFault_Handler            /* Bus Fault Handler            */
+    .long   UsageFault_Handler          /* Usage Fault Handler          */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   DebugMon_Handler            /* Debug Monitor Handler        */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+    /* External Interrupts */
+    .long   DEF_IRQHandler              /*  0: Default                  */
+
+
+    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+    .thumb
+
+
+/* Reset Handler */
+
+    .section .cs3.reset,"x",%progbits
+    .thumb_func
+    .globl  __cs3_reset_cortex_m
+    .type   __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+    .fnstart
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0,=_start
+    BX      R0
+    .pool
+    .cantunwind
+    .fnend
+    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B       .
+    .size   MemManage_Handler, . - MemManage_Handler
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B       .
+    .size   DebugMon_Handler, . - DebugMon_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ     DEF_IRQHandler
+
+    .end
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/arm_convolution_example_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/arm_convolution_example_f32.c
new file mode 100644
index 0000000..4d547b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/arm_convolution_example_f32.c
@@ -0,0 +1,232 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision: 	V1.0.3 
+*  
+* Project: 	    CMSIS DSP Library  
+* Title:	    arm_convolution_example_f32.c		  
+*  
+* Description:	Example code demonstrating Convolution of two input signals using fft. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+/** 
+ * @ingroup groupExamples 
+ */ 
+ 
+/**    
+ * @defgroup ConvolutionExample Convolution Example    
+ * 
+ * \par Description: 
+ * \par
+ * Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex 
+ * Multiplication, and Support Functions.
+ *
+ * \par Algorithm:
+ * \par
+ * The convolution theorem states that convolution in the time domain corresponds to 
+ * multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of 
+ * two signals is equal to the product of their individual Fourier transforms. 
+ * The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT). 
+ * \par
+ * Two input signals, a[n] and b[n], with lengths \c n1 and \c n2 respectively,
+ * are zero padded so that their lengths become \c N, which is greater than or equal to (n1+n2-1)
+ * and is a power of 4 as FFT implementation is radix-4.  
+ * The convolution of a[n] and b[n] is obtained by taking the FFT of the input 
+ * signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of 
+ * the multiplied result.
+ * \par
+ * This is denoted by the following equations:
+ * 
 A[k] = FFT(a[n],N)
+ * B[k] = FFT(b[n],N)
+ * conv(a[n], b[n]) = IFFT(A[k] * B[k], N)

+ * where A[k] and B[k] are the N-point FFTs of the signals a[n] 
+ * and b[n] respectively. 
+ * The length of the convolved signal is (n1+n2-1).
+ *
+ * \par Block Diagram:
+ * \par
+ * \image html Convolution.gif 
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInputA_f32 points to the first input sequence
+ * \li \c srcALen length of the first input sequence
+ * \li \c testInputB_f32 points to the second input sequence
+ * \li \c srcBLen length of the second input sequence
+ * \li \c outLen length of convolution output sequence, (srcALen + srcBLen - 1)
+ * \li \c AxB points to the output array where the product of individual FFTs of inputs is stored.
+ * 
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_fill_f32()
+ * - arm_copy_f32()
+ * - arm_cfft_radix4_init_f32()
+ * - arm_cfft_radix4_f32()
+ * - arm_cmplx_mult_cmplx_f32()  
+ * 
+ *  Refer   
+ * \link arm_convolution_example_f32.c \endlink
+ * 
+ */ 
+ 
+ 
+/** \example arm_convolution_example_f32.c 
+  */  
+     
+#include "arm_math.h" 
+#include "math_helper.h"				 
+ 
+/* ---------------------------------------------------------------------- 
+* Defines each of the tests performed 
+* ------------------------------------------------------------------- */ 
+#define MAX_BLOCKSIZE	128 
+#define DELTA           (0.000001f) 
+#define SNR_THRESHOLD 	90 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare I/O buffers  
+* ------------------------------------------------------------------- */ 
+float32_t Ak[MAX_BLOCKSIZE];		/* Input A */ 
+float32_t Bk[MAX_BLOCKSIZE];		/* Input B */ 
+float32_t AxB[MAX_BLOCKSIZE * 2];	/* Output */ 
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for Floating point Convolution example for 32-blockSize 
+* Generated by the MATLAB randn() function 
+* ------------------------------------------------------------------- */ 
+float32_t testInputA_f32[64] =  
+{  
+-0.808920,	1.357369,	1.180861,	-0.504544,	1.762637,	-0.703285,	 
+1.696966,	0.620571,	-0.151093,	-0.100235,	-0.872382,	-0.403579,	 
+-0.860749,	-0.382648,	-1.052338,	0.128113,	-0.646269,	1.093377,	 
+-2.209198,	0.471706,	0.408901,	1.266242,	0.598252,	1.176827,	 
+-0.203421,	0.213596,	-0.851964,	-0.466958,	0.021841,	-0.698938,	 
+-0.604107,	0.461778,	-0.318219,	0.942520,	0.577585,	0.417619,	 
+0.614665,	0.563679,	-1.295073,	-0.764437,	0.952194,	-0.859222,	 
+-0.618554,	-2.268542,	-1.210592,	1.655853,	-2.627219,	-0.994249,	 
+-1.374704,	0.343799,	0.025619,	1.227481,	-0.708031,	0.069355,	 
+-1.845228,	-1.570886,	1.010668,	-1.802084,	1.630088,	1.286090,	 
+-0.161050,	-0.940794,	0.367961,	0.291907 
+		 
+};  
+  
+float32_t testInputB_f32[64] =  
+{  
+0.933724,	0.046881,	1.316470,	0.438345,	0.332682,	2.094885,	 
+0.512081,	0.035546,	0.050894,	-2.320371,	0.168711,	-1.830493,	 
+-0.444834,	-1.003242,	-0.531494,	-1.365600,	-0.155420,	-0.757692,	 
+-0.431880,	-0.380021,	0.096243,	-0.695835,	0.558850,	-1.648962,	 
+0.020369,	-0.363630,	0.887146,	0.845503,	-0.252864,	-0.330397,	 
+1.269131,	-1.109295,	-1.027876,	0.135940,	0.116721,	-0.293399,	 
+-1.349799,	0.166078,	-0.802201,	0.369367,	-0.964568,	-2.266011,	 
+0.465178,	0.651222,	-0.325426,	0.320245,	-0.784178,	-0.579456,	 
+0.093374,	0.604778,	-0.048225,	0.376297,	-0.394412,	0.578182,	 
+-1.218141,	-1.387326,	0.692462,	-0.631297,	0.153137,	-0.638952,	 
+0.635474,	-0.970468,	1.334057,	-0.111370 
+};  
+  
+const float testRefOutput_f32[126] =   
+{  
+-0.818943,	1.229484,	-0.533664,	1.016604,	0.341875,	-1.963656,	 
+5.171476,	3.478033,	7.616361,	6.648384,	0.479069,	1.792012,	 
+-1.295591,	-7.447818,	0.315830,	-10.657445,	-2.483469,	-6.524236,	 
+-7.380591,	-3.739005,	-8.388957,	0.184147,	-1.554888,	3.786508,	 
+-1.684421,	5.400610,	-1.578126,	7.403361,	8.315999,	2.080267,	 
+11.077776,	2.749673,	7.138962,	2.748762,	0.660363,	0.981552,	 
+1.442275,	0.552721,	-2.576892,	4.703989,	0.989156,	8.759344,	 
+-0.564825,	-3.994680,	0.954710,	-5.014144,	6.592329,	1.599488,	 
+-13.979146,	-0.391891,	-4.453369,	-2.311242,	-2.948764,	1.761415,	 
+-0.138322,	10.433007,	-2.309103,	4.297153,	8.535523,	3.209462,	 
+8.695819,	5.569919,	2.514304,	5.582029,	2.060199,	0.642280,	 
+7.024616,	1.686615,	-6.481756,	1.343084,	-3.526451,	1.099073,	 
+-2.965764,	-0.173723,	-4.111484,	6.528384,	-6.965658,	1.726291,	 
+1.535172,	11.023435,	2.338401,	-4.690188,	1.298210,	3.943885,	 
+8.407885,	5.168365,	0.684131,	1.559181,	1.859998,	2.852417,	 
+8.574070,	-6.369078,	6.023458,	11.837963,	-6.027632,	4.469678,	 
+-6.799093,	-2.674048,	6.250367,	-6.809971,	-3.459360,	9.112410,	 
+-2.711621,	-1.336678,	1.564249,	-1.564297,	-1.296760,	8.904013,	 
+-3.230109,	6.878013,	-7.819823,	3.369909,	-1.657410,	-2.007358,	 
+-4.112825,	1.370685,	-3.420525,	-6.276605,	3.244873,	-3.352638,	 
+1.545372,	0.902211,	0.197489,	-1.408732,	0.523390,	0.348440 
+}; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare Global variables  
+* ------------------------------------------------------------------- */ 
+uint32_t srcALen = 64;	 /* Length of Input A */ 
+uint32_t srcBLen = 64;	 /* Length of Input B */ 
+uint32_t outLen;		 /* Length of convolution output */ 
+float32_t snr; 			 /* output SNR */ 
+ 
+int32_t main(void) 
+{ 
+	arm_status status;	   /* Status of the example */ 
+	arm_cfft_radix4_instance_f32 cfft_instance;	/* CFFT Structure instance */ 
+ 
+	/* CFFT Structure instance pointer */ 
+    arm_cfft_radix4_instance_f32 *cfft_instance_ptr =  
+			(arm_cfft_radix4_instance_f32*) &cfft_instance; 
+ 
+	/* output length of convolution */ 
+	outLen = srcALen + srcBLen - 1; 
+ 
+	/* Initialise the fft input buffers with all zeros */ 
+	arm_fill_f32(0.0,  Ak, MAX_BLOCKSIZE); 
+	arm_fill_f32(0.0,  Bk, MAX_BLOCKSIZE); 
+ 
+	/* Copy the input values to the fft input buffers */ 
+	arm_copy_f32(testInputA_f32,  Ak, MAX_BLOCKSIZE/2); 
+	arm_copy_f32(testInputB_f32,  Bk, MAX_BLOCKSIZE/2); 
+	 
+	/* Initialize the CFFT function to compute 64 point fft */  
+    status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1); 
+ 
+	/* Transform input a[n] from time domain to frequency domain A[k] */ 
+	arm_cfft_radix4_f32(cfft_instance_ptr, Ak); 
+	/* Transform input b[n] from time domain to frequency domain B[k] */ 
+	arm_cfft_radix4_f32(cfft_instance_ptr, Bk); 
+	 
+	/* Complex Multiplication of the two input buffers in frequency domain */ 
+	arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2);  
+ 
+    /* Initialize the CIFFT function to compute 64 point ifft */  
+	status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1); 
+ 
+	/* Transform the multiplication output from frequency domain to time domain, 
+	   that gives the convolved output  */ 
+	arm_cfft_radix4_f32(cfft_instance_ptr, AxB); 
+ 
+	/* SNR Calculation */ 
+	snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1); 
+	 
+	/* Compare the SNR with threshold to test whether the  
+	   computed output is matched with the reference output values. */ 
+	if( snr > SNR_THRESHOLD) 
+	{ 
+		status = ARM_MATH_SUCCESS; 
+	} 
+		 
+	if( status != ARM_MATH_SUCCESS) 
+	{ 
+	  while(1); 
+	} 
+
+    while(1);                             /* main function does not return */
+} 
+								  
+ /** \endlink */ 
+ 
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM0.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM0.c
new file mode 100644
index 0000000..ece74d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM0.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Cortex-M0 Device System Source File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM3.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM3.c
new file mode 100644
index 0000000..2f5fa0b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM3.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Cortex-M3 Device System Source File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM4.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM4.c
new file mode 100644
index 0000000..beaaf6f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_convolution_example/system_ARMCM4.c
@@ -0,0 +1,81 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Cortex-M4 Device System Source File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM4.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvopt
new file mode 100644
index 0000000..0c77fcd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvopt
@@ -0,0 +1,290 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\debug\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        SARMCM3.DLL
+        
+        DARMCM1.DLL
+        -pCM0
+        SARMCM3.DLL
+        
+        TARMCM1.DLL
+        -pCM0
+      
+      
+        1
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        1
+        1
+        0
+        1
+        0
+        0
+        -1
+        
+        
+        
+        
+        .\arm_dotproduct_example.ini
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          -T0
+        
+      
+      
+        
+          0
+          0
+          156
+          1
+          
306

+          0
+          0
+          0
+          0
+          1
+          
+          
+          \\arm_cortexM0l_dotproduct_example\../arm_dotproduct_example_f32.c\156
+        
+        
+          1
+          0
+          159
+          1
+          
304

+          0
+          0
+          0
+          0
+          1
+          
+          
+          \\arm_cortexM0l_dotproduct_example\../arm_dotproduct_example_f32.c\159
+        
+      
+      
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+    
+  
+
+  
+    Source Group 1
+    1
+    0
+    0
+    
+      1
+      1
+      1
+      0
+      0
+      0
+      0
+      1
+      1
+      0
+      ..\arm_dotproduct_example_f32.c
+      arm_dotproduct_example_f32.c
+    
+  
+
+  
+    CMSIS
+    1
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\system_ARMCM0.c
+      system_ARMCM0.c
+    
+    
+      2
+      3
+      2
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      .\startup_ARMCM0.s
+      startup_ARMCM0.s
+    
+  
+
+  
+    CMSIS SW_DSP_Library
+    1
+    0
+    0
+    
+      3
+      4
+      4
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib
+      arm_cortexM0l_math.lib
+    
+  
+
+  
+    1
+    0
+    
+      100
+      0
+      
+        
+          ..\arm_dotproduct_example_f32.c
+          0
+          1
+          1
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvproj
new file mode 100644
index 0000000..46580ad
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM0l_dotproduct_example.uvproj
@@ -0,0 +1,425 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M0
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE
+          
+          
+          
+          4803
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\debug\
+          arm_cortexM0l_dotproduct_example
+          1
+          0
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+              ..\system_ARMCM0.c
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+              startup_ARMCM0.s
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+              .\startup_ARMCM0.s
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+          CMSIS DSP_Library
+          
+            
+              arm_cortexM0l_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvopt
new file mode 100644
index 0000000..4b80fb8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvopt
@@ -0,0 +1,290 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
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+    *.txt; *.h; *.inc
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvproj
new file mode 100644
index 0000000..e2fd21a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM3l_dotproduct_example.uvproj
@@ -0,0 +1,425 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
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+    
+      Target 1
+      0x4
+      ARM-ADS
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+          CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE
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+            
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+          CMSIS DSP_Library
+          
+            
+              arm_cortexM3l_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib
+            
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+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM4lf_dotproduct_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM4lf_dotproduct_example.uvopt
new file mode 100644
index 0000000..f7363bb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM4lf_dotproduct_example.uvopt
@@ -0,0 +1,290 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
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+
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+  
+    Target 1
+    0x4
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+      12000000
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM4lf_dotproduct_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM4lf_dotproduct_example.uvproj
new file mode 100644
index 0000000..341c39a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_cortexM4lf_dotproduct_example.uvproj
@@ -0,0 +1,425 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M4 FPU
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2
+          
+          
+          
+          5237
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\debug\
+          arm_cortexM4lf_dotProduct_example
+          1
+          0
+          0
+          1
+          1
+          .\debug\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          
+          DCM.DLL
+          -pCM3
+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM3
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            0
+            0
+            0
+            1
+            1
+            1
+            0
+            1
+          
+          0
+          -1
+          
+            
+            
+            
+            
+            .\arm_dotProduct_example.ini
+          
+          
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            0
+            -1
+          
+          
+          
+          
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            5
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            3
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            
+              
+              ARM_MATH_CM4, __FPU_PRESENT = 1
+              
+              ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x00000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Source Group 1
+          
+            
+              arm_dotproduct_example_f32.c
+              1
+              ..\arm_dotproduct_example_f32.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM4.c
+              1
+              ..\system_ARMCM4.c
+            
+            
+              startup_ARMCM4.s
+              2
+              .\startup_ARMCM4.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+          
+            
+              arm_cortexM4lf_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_dotproduct_example.ini b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_dotproduct_example.ini
new file mode 100644
index 0000000..df2ec0e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/arm_dotproduct_example.ini
@@ -0,0 +1,12 @@
+
+/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions 
+   
+   The file can be executed in the following way:
+   1) manually from uVision command window (in debug mode) using command:
+   INCLUIDE arm_dotproduct_example.ini	 
+
+*/
+
+// usual initialisation	for target setup
+MAP  0x20000000, 0x20008000  READ WRITE  // allow R/W access to IO space
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..0acd346
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM0.s
@@ -0,0 +1,144 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Cortex-M0 Core Device Startup File
+; *           for CM0 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..5af584b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM3.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Cortex-M3 Core Device Startup File
+; *           for CM3 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..09fdbd6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/ARM/startup_ARMCM4.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM4 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/arm_dotproduct_example_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/arm_dotproduct_example_f32.c
new file mode 100644
index 0000000..7028b09
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/arm_dotproduct_example_f32.c
@@ -0,0 +1,163 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision: 	V1.0.3 
+*  
+* Project: 	    CMSIS DSP Library  
+* Title:	    arm_dotproduct_example_f32.c		  
+*  
+* Description:	Example code computing dot product of two vectors. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+/** 
+ * @ingroup groupExamples 
+ */ 
+ 
+/**    
+ * @defgroup DotproductExample Dot Product Example    
+ * 
+ * \par Description: 
+ * \par
+ * Demonstrates the use of the Multiply and Add functions to perform the dot product.
+ * The dot product of two vectors is obtained by multiplying corresponding elements
+ * and summing the products.
+
+ * \par Algorithm:
+ * \par
+ * The two input vectors \c A and \c B with length \c n, are multiplied element-by-element
+ * and then added to obtain dot product.
+ * \par
+ * This is denoted by the following equation:
+ *         
  dotProduct = A[0] * B[0] + A[1] * B[1] + ... + A[n-1] * B[n-1]
 
+ *
+ * \par Block Diagram:
+ * \par
+ * \image html dotProduct.gif 
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c srcA_buf_f32 points to first input vector
+ * \li \c srcB_buf_f32 points to second input vector 
+ * \li \c testOutput   stores dot product of the two input vectors.
+ * 
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_mult_f32() 
+ * - arm_add_f32()
+ * 
+ *  Refer   
+ * \link arm_dotproduct_example_f32.c \endlink
+ * 
+ */ 
+ 
+ 
+/** \example arm_dotproduct_example_f32.c 
+  */  
+
+#include      
+#include "arm_math.h"
+ 
+/* ---------------------------------------------------------------------- 
+* Defines each of the tests performed 
+* ------------------------------------------------------------------- */ 
+#define MAX_BLOCKSIZE	32 
+#define DELTA           (0.000001f) 
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for Floating point Dot Product example for 32-blockSize 
+* Generated by the MATLAB randn() function 
+* ------------------------------------------------------------------- */  
+/* ----------------------------------------------------------------------  
+** Test input data of srcA for blockSize 32   
+** ------------------------------------------------------------------- */  
+float32_t srcA_buf_f32[MAX_BLOCKSIZE] =   
+{   
+-0.4325648115282207,	-1.6655843782380970,	0.1253323064748307,	 
+ 0.2876764203585489,    -1.1464713506814637,	1.1909154656429988,	 
+ 1.1891642016521031,    -0.0376332765933176,	0.3272923614086541,	 
+ 0.1746391428209245,    -0.1867085776814394,	0.7257905482933027,	 
+-0.5883165430141887,	 2.1831858181971011,   -0.1363958830865957,	 
+ 0.1139313135208096,	 1.0667682113591888,	0.0592814605236053,	 
+-0.0956484054836690,	-0.8323494636500225,	0.2944108163926404,	 
+-1.3361818579378040,	 0.7143245518189522,	1.6235620644462707,	 
+-0.6917757017022868,	 0.8579966728282626,	1.2540014216025324,	 
+-1.5937295764474768,	-1.4409644319010200,	0.5711476236581780,	 
+-0.3998855777153632,	 0.6899973754643451 
+};   
+  
+/* ----------------------------------------------------------------------  
+** Test input data of srcB for blockSize 32   
+** ------------------------------------------------------------------- */   
+float32_t srcB_buf_f32[MAX_BLOCKSIZE] =   
+{   
+ 1.7491401329284098,	0.1325982188803279,	 0.3252281811989881,	 
+-0.7938091410349637,	0.3149236145048914,	-0.5272704888029532,	 
+ 0.9322666565031119,	1.1646643544607362,	-2.0456694357357357,	 
+-0.6443728590041911,	1.7410657940825480,	 0.4867684246821860,	 
+ 1.0488288293660140,	1.4885752747099299,	 1.2705014969484090,	 
+-1.8561241921210170,	2.1343209047321410,  1.4358467535865909,	 
+-0.9173023332875400,   -1.1060770780029008,	 0.8105708062681296,	 
+ 0.6985430696369063,   -0.4015827425012831,	 1.2687512030669628,	 
+-0.7836083053674872,	0.2132664971465569,	 0.7878984786088954,	 
+ 0.8966819356782295,   -0.1869172943544062,	 1.0131816724341454,	 
+ 0.2484350696132857,	0.0596083377937976 
+};   
+ 
+/* Reference dot product output */ 
+float32_t  refDotProdOut = 5.9273644806352142; 	 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare Global variables  
+* ------------------------------------------------------------------- */ 
+float32_t multOutput[MAX_BLOCKSIZE];  /* Intermediate output */ 
+float32_t testOutput;  /* Final ouput */ 
+ 
+arm_status status;	 /* Status of the example */ 
+
+int32_t main(void) 
+{ 
+	uint32_t i;			 /* Loop counter */ 
+	float32_t diff;		 /* Difference between reference and test outputs */ 
+ 
+	/* Multiplication of two input buffers */ 
+	arm_mult_f32(srcA_buf_f32, srcB_buf_f32, multOutput, MAX_BLOCKSIZE); 
+	 
+	/* Accumulate the multiplication output values to  
+	   get the dot product of the two inputs */ 
+	for(i=0; i< MAX_BLOCKSIZE; i++) 
+    {          
+		arm_add_f32(&testOutput, &multOutput[i], &testOutput, 1);	 
+    } 
+ 
+	/* absolute value of difference between ref and test */ 
+	diff = fabsf(refDotProdOut - testOutput); 
+	 
+	/* Comparison of dot product value with reference */ 
+	if(diff > DELTA) 
+	{ 
+		status = ARM_MATH_TEST_FAILURE; 
+	} 
+		 
+	if( status == ARM_MATH_TEST_FAILURE) 
+	{ 
+	  while(1); 
+	} 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+ /** \endlink */ 
+ 
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM0.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM0.c
new file mode 100644
index 0000000..ece74d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM0.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Cortex-M0 Device System Source File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM3.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM3.c
new file mode 100644
index 0000000..2f5fa0b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM3.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Cortex-M3 Device System Source File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM4.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM4.c
new file mode 100644
index 0000000..beaaf6f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_dotproduct_example/system_ARMCM4.c
@@ -0,0 +1,81 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Cortex-M4 Device System Source File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM4.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvopt
new file mode 100644
index 0000000..a5def48
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvopt
@@ -0,0 +1,304 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
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+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)
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+      arm_fft_bin_example_f32.c
+    
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvproj
new file mode 100644
index 0000000..417abdc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM0l_fft_bin_example.uvproj
@@ -0,0 +1,430 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvopt
new file mode 100644
index 0000000..39bfd9c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvopt
@@ -0,0 +1,304 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvproj
new file mode 100644
index 0000000..c8b8fd6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM3l_fft_bin_example.uvproj
@@ -0,0 +1,430 @@
+
+
+
+  1.1
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+  
### uVision Project, (C) Keil Software

+
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+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvopt
new file mode 100644
index 0000000..1235613
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvopt
@@ -0,0 +1,304 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
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+    *.cpp
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+
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvproj
new file mode 100644
index 0000000..5fe326d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_cortexM4lf_fft_bin_example.uvproj
@@ -0,0 +1,430 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
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+      0x4
+      ARM-ADS
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+            
+            
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            0
+            -1
+          
+          
+          
+          
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            5
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            3
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            
+              
+              ARM_MATH_CM4, __FPU_PRESENT = 1
+              
+              ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x00000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Source Group 1
+          
+            
+              arm_fft_bin_data.c
+              1
+              ..\arm_fft_bin_data.c
+            
+            
+              arm_fft_bin_example_f32.c
+              1
+              ..\arm_fft_bin_example_f32.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM4.c
+              1
+              ..\system_ARMCM4.c
+            
+            
+              startup_ARMCM4.s
+              2
+              .\startup_ARMCM4.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+          
+            
+              arm_cortexM4lf_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_fft_bin_example.ini b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_fft_bin_example.ini
new file mode 100644
index 0000000..fdf91be
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/arm_fft_bin_example.ini
@@ -0,0 +1,12 @@
+
+/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions 
+   
+   The file can be executed in the following way:
+   1) manually from uVision command window (in debug mode) using command:
+   INCLUIDE arm_fft_bin_example.ini	 
+
+*/
+
+// usual initialisation	for target setup
+MAP  0x20000000, 0x20008000  READ WRITE  // allow R/W access to IO space
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..0acd346
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM0.s
@@ -0,0 +1,144 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Cortex-M0 Core Device Startup File
+; *           for CM0 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..5af584b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM3.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Cortex-M3 Core Device Startup File
+; *           for CM3 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..09fdbd6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/ARM/startup_ARMCM4.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM4 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_data.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_data.c
new file mode 100644
index 0000000..64c9df2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_data.c
@@ -0,0 +1,268 @@
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+Test Input signal contains 10KHz signal + Uniformly distributed white noise
+** ------------------------------------------------------------------- */
+
+float32_t testInput_f32_10khz[2048] = 
+{   
+-0.865129623056441, 	0.000000000000000, 	-2.655020678073846, 	0.000000000000000, 	0.600664612949661, 	0.000000000000000, 	0.080378093886515, 	0.000000000000000, 	
+-2.899160484012034, 	0.000000000000000, 	2.563004262857762, 	0.000000000000000, 	3.078328403304206, 	0.000000000000000, 	0.105906778385130, 	0.000000000000000, 	
+0.048366940168201, 	0.000000000000000, 	-0.145696461188734, 	0.000000000000000, 	-0.023417155362879, 	0.000000000000000, 	2.127729174988954, 	0.000000000000000, 	
+-1.176633086028377, 	0.000000000000000, 	3.690223557991855, 	0.000000000000000, 	-0.622791766173194, 	0.000000000000000, 	0.722837373872203, 	0.000000000000000, 	
+2.739754205367484, 	0.000000000000000, 	-0.062610410524552, 	0.000000000000000, 	-0.891296810967338, 	0.000000000000000, 	-1.845872258871811, 	0.000000000000000, 	
+1.195039415434387, 	0.000000000000000, 	-2.177388969045026, 	0.000000000000000, 	1.078649103637905, 	0.000000000000000, 	2.570976050490193, 	0.000000000000000, 	
+-1.383551403404574, 	0.000000000000000, 	2.392141424058873, 	0.000000000000000, 	2.858002843205065, 	0.000000000000000, 	-3.682433899725536, 	0.000000000000000, 	
+-3.488146646451150, 	0.000000000000000, 	1.323468578888120, 	0.000000000000000, 	-0.099771155430726, 	0.000000000000000, 	1.561168082500454, 	0.000000000000000, 	
+1.025026795103179, 	0.000000000000000, 	0.928841900171200, 	0.000000000000000, 	2.930499509864950, 	0.000000000000000, 	2.013349089766430, 	0.000000000000000, 	
+2.381676148486737, 	0.000000000000000, 	-3.081062307950236, 	0.000000000000000, 	-0.389579115537544, 	0.000000000000000, 	0.181540149166620, 	0.000000000000000, 	
+-2.601953341353208, 	0.000000000000000, 	0.333435137783218, 	0.000000000000000, 	-2.812945856162965, 	0.000000000000000, 	2.649109640172910, 	0.000000000000000, 	
+-1.003963025744654, 	0.000000000000000, 	1.552460768755035, 	0.000000000000000, 	0.088641345335247, 	0.000000000000000, 	-2.519951327113426, 	0.000000000000000, 	
+-4.341348988610527, 	0.000000000000000, 	0.557772429359965, 	0.000000000000000, 	-1.671267412948494, 	0.000000000000000, 	0.733951350960387, 	0.000000000000000, 	
+0.409263788034864, 	0.000000000000000, 	3.566033071952806, 	0.000000000000000, 	1.882565173848352, 	0.000000000000000, 	-1.106017073793287, 	0.000000000000000, 	
+0.154456720778718, 	0.000000000000000, 	-2.513205795512153, 	0.000000000000000, 	0.310978660939421, 	0.000000000000000, 	0.579706500111723, 	0.000000000000000, 	
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+-3.899429237481194, 	0.000000000000000, 	0.362439009175350, 	0.000000000000000, 	-1.124461670265618, 	0.000000000000000, 	1.806000360163583, 	0.000000000000000, 	
+-2.768333362600288, 	0.000000000000000, 	0.244387897900379, 	0.000000000000000, 	0.908767296720926, 	0.000000000000000, 	1.254669374391882, 	0.000000000000000, 	
+-1.420441929463686, 	0.000000000000000, 	-0.875658895966293, 	0.000000000000000, 	0.183824603376167, 	0.000000000000000, 	-3.361653917011686, 	0.000000000000000, 	
+-0.796615630227952, 	0.000000000000000, 	-1.660226542658673, 	0.000000000000000, 	1.654439358307226, 	0.000000000000000, 	2.782812946709771, 	0.000000000000000, 	
+1.418064412811531, 	0.000000000000000, 	-0.819645647243761, 	0.000000000000000, 	0.807724772592699, 	0.000000000000000, 	-0.941967976379298, 	0.000000000000000, 	
+-2.312768306047469, 	0.000000000000000, 	0.872426936477443, 	0.000000000000000, 	0.919528961530845, 	0.000000000000000, 	-2.084904575264847, 	0.000000000000000, 	
+-1.972464868459322, 	0.000000000000000, 	-1.050687203338466, 	0.000000000000000, 	1.659579707007902, 	0.000000000000000, 	-1.820640014705855, 	0.000000000000000, 	
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+-2.016391579662071, 	0.000000000000000, 	-0.653096251969787, 	0.000000000000000, 	1.466353155666821, 	0.000000000000000, 	-2.872058864320412, 	0.000000000000000, 	
+-2.157180779503830, 	0.000000000000000, 	0.723257479841560, 	0.000000000000000, 	3.769951308104384, 	0.000000000000000, 	-1.923392042420024, 	0.000000000000000, 	
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+2.518120645960652, 	0.000000000000000, 	1.040820431111488, 	0.000000000000000, 	-4.560583754742486, 	0.000000000000000, 	-0.226899614918836, 	0.000000000000000, 	
+1.713331231108959, 	0.000000000000000, 	-3.293941019163642, 	0.000000000000000, 	-1.113331444648290, 	0.000000000000000, 	-1.032308423149906, 	0.000000000000000, 	
+1.593774272982443, 	0.000000000000000, 	-1.246840475090529, 	0.000000000000000, 	-0.190344684920137, 	0.000000000000000, 	-1.719386356896355, 	0.000000000000000, 	
+-2.827721754659679, 	0.000000000000000, 	-0.092438285279020, 	0.000000000000000, 	-0.565844430675246, 	0.000000000000000, 	-1.077916121691716, 	0.000000000000000, 	
+-1.208665809504693, 	0.000000000000000, 	-2.996014266381254, 	0.000000000000000, 	2.888573323402423, 	0.000000000000000, 	2.829507048720695, 	0.000000000000000, 	
+-0.859177034120755, 	0.000000000000000, 	-1.969302377743254, 	0.000000000000000, 	0.777437674525362, 	0.000000000000000, 	-0.124910190157646, 	0.000000000000000, 	
+0.129875493115290, 	0.000000000000000, 	-4.192139262163992, 	0.000000000000000, 	3.023496047962126, 	0.000000000000000, 	1.149775163736637, 	0.000000000000000, 	
+2.038151304801731, 	0.000000000000000, 	3.016122489841263, 	0.000000000000000, 	-4.829481812137012, 	0.000000000000000, 	-1.668436615909279, 	0.000000000000000, 	
+0.958586784636918, 	0.000000000000000, 	1.550652410058678, 	0.000000000000000, 	-1.456305257976716, 	0.000000000000000, 	-0.079588392344731, 	0.000000000000000, 	
+-2.453213599392345, 	0.000000000000000, 	0.296795909127105, 	0.000000000000000, 	-0.253426616607643, 	0.000000000000000, 	1.418937160028195, 	0.000000000000000, 	
+-1.672949529066915, 	0.000000000000000, 	-1.620990298572947, 	0.000000000000000, 	-1.085103073196045, 	0.000000000000000, 	0.738606361195386, 	0.000000000000000, 	
+-2.097831202853255, 	0.000000000000000, 	2.711952282071310, 	0.000000000000000, 	1.498539238246888, 	0.000000000000000, 	1.317457282535915, 	0.000000000000000, 	
+-0.302765938349717, 	0.000000000000000, 	-0.044623707947201, 	0.000000000000000, 	2.337405215062395, 	0.000000000000000, 	-3.980689173859100, 	0.000000000000000, 	
+
+
+};
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_example_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_example_f32.c
new file mode 100644
index 0000000..f9a01dd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/arm_fft_bin_example_f32.c
@@ -0,0 +1,151 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision: 	V1.0.3  
+*  
+* Project: 	    CMSIS DSP Library  
+* Title:	    arm_fft_bin_example_f32.c		  
+*  
+* Description:	Example code demonstrating calculation of Max energy bin of  
+*				frequency domain of input signal. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+/** 
+ * @ingroup groupExamples 
+ */ 
+ 
+/**    
+ * @defgroup FrequencyBin Frequency Bin Example    
+ * 
+ * \par Description
+ * \par
+ * Demonstrates the calculation of the maximum energy bin in the frequency 
+ * domain of the input signal with the use of Complex FFT, Complex 
+ * Magnitude, and Maximum functions. 
+ * 
+ * \par Algorithm:
+ * \par
+ * The input test signal contains a 10 kHz signal with uniformly distributed white noise.  
+ * Calculating the FFT of the input signal will give us the maximum energy of the 
+ * bin corresponding to the input frequency of 10 kHz.  
+ * 
+ * \par Block Diagram:
+ * \image html FFTBin.gif "Block Diagram"
+ * \par
+ * The figure below shows the time domain signal of 10 kHz signal with 
+ * uniformly distributed white noise, and the next figure shows the input
+ * in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal. 
+ * \par
+ * \image html FFTBinInput.gif "Input signal in Time domain" 
+ * \image html FFTBinOutput.gif "Input signal in Frequency domain"
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInput_f32_10khz points to the input data
+ * \li \c testOutput points to the output data
+ * \li \c fftSize length of FFT
+ * \li \c ifftFlag flag for the selection of CFFT/CIFFT
+ * \li \c doBitReverse Flag for selection of normal order or bit reversed order
+ * \li \c refIndex reference index value at which maximum energy of bin ocuurs
+ * \li \c testIndex calculated index value at which maximum energy of bin ocuurs
+ * 
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_cfft_radix4_init_f32()
+ * - arm_cfft_radix4_f32()
+ * - arm_cmplx_mag_f32()
+ * - arm_max_f32()
+ *
+ *  Refer   
+ * \link arm_fft_bin_example_f32.c \endlink
+ * 
+ */ 
+ 
+ 
+/** \example arm_fft_bin_example_f32.c 
+  */  
+
+#include "arm_math.h" 
+ 
+#define TEST_LENGTH_SAMPLES 2048 
+ 
+/* ------------------------------------------------------------------- 
+* External Input and Output buffer Declarations for FFT Bin Example 
+* ------------------------------------------------------------------- */ 
+extern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]; 
+static float32_t testOutput[TEST_LENGTH_SAMPLES/2]; 
+ 
+/* ------------------------------------------------------------------ 
+* Global variables for FFT Bin Example 
+* ------------------------------------------------------------------- */ 
+uint32_t fftSize = 1024; 
+uint32_t ifftFlag = 0; 
+uint32_t doBitReverse = 1; 
+ 
+/* Reference index at which max energy of bin ocuurs */ 
+uint32_t refIndex = 213, testIndex = 0; 
+ 
+/* ---------------------------------------------------------------------- 
+* Max magnitude FFT Bin test 
+* ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+   
+	arm_status status; 
+	arm_cfft_radix4_instance_f32 S; 
+	float32_t maxValue; 
+	 
+	status = ARM_MATH_SUCCESS; 
+	 
+	/* Initialize the CFFT/CIFFT module */  
+	status = arm_cfft_radix4_init_f32(&S, fftSize,  
+	  								ifftFlag, doBitReverse); 
+	 
+	/* Process the data through the CFFT/CIFFT module */ 
+	arm_cfft_radix4_f32(&S, testInput_f32_10khz); 
+	 
+	 
+	/* Process the data through the Complex Magnitude Module for  
+	calculating the magnitude at each bin */ 
+	arm_cmplx_mag_f32(testInput_f32_10khz, testOutput,  
+	  				fftSize);  
+	 
+	/* Calculates maxValue and returns corresponding BIN value */ 
+	arm_max_f32(testOutput, fftSize, &maxValue, &testIndex); 
+	 
+	if(testIndex !=  refIndex) 
+	{ 
+		status = ARM_MATH_TEST_FAILURE; 
+	} 
+	 
+	/* ---------------------------------------------------------------------- 
+	** Loop here if the signals fail the PASS check. 
+	** This denotes a test failure 
+	** ------------------------------------------------------------------- */ 
+	 
+	if( status != ARM_MATH_SUCCESS) 
+	{ 
+		while(1); 
+	} 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+ /** \endlink */ 
+ 
+ 
+ 
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM0.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM0.c
new file mode 100644
index 0000000..ece74d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM0.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Cortex-M0 Device System Source File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM3.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM3.c
new file mode 100644
index 0000000..2f5fa0b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM3.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Cortex-M3 Device System Source File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM4.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM4.c
new file mode 100644
index 0000000..beaaf6f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fft_bin_example/system_ARMCM4.c
@@ -0,0 +1,81 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Cortex-M4 Device System Source File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM4.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM0l_fir_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM0l_fir_example.uvopt
new file mode 100644
index 0000000..0c6ce41
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM0l_fir_example.uvopt
@@ -0,0 +1,318 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\debug\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        SARMCM3.DLL
+        
+        DARMCM1.DLL
+        -pCM0
+        SARMCM3.DLL
+        
+        TARMCM1.DLL
+        -pCM0
+      
+      
+        1
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        1
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM0l_fir_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM0l_fir_example.uvproj
new file mode 100644
index 0000000..fdacdfc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM0l_fir_example.uvproj
@@ -0,0 +1,435 @@
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+  
### uVision Project, (C) Keil Software

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM3l_fir_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM3l_fir_example.uvopt
new file mode 100644
index 0000000..35da163
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM3l_fir_example.uvopt
@@ -0,0 +1,318 @@
+
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+  1.0
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+  
### uVision Project, (C) Keil Software

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM3l_fir_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM3l_fir_example.uvproj
new file mode 100644
index 0000000..182decb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM3l_fir_example.uvproj
@@ -0,0 +1,435 @@
+
+
+
+  1.1
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+  
### uVision Project, (C) Keil Software

+
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+            
+              arm_cortexM3l_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM3l_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvopt
new file mode 100644
index 0000000..18ec066
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvopt
@@ -0,0 +1,318 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\debug\
+      
+      
+        1
+        1
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+        1
+      
+      255
+      
+        SARMCM3.DLL
+        
+        DCM.DLL
+        -pCM3
+        SARMCM3.DLL
+        
+        TCM.DLL
+        -pCM3
+      
+      
+        1
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
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+        1
+        1
+        1
+        0
+        1
+        0
+        0
+        -1
+        
+        
+        
+        
+        .\arm_fir_example.ini
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          -T0
+        
+      
+      
+        
+          0
+          0
+          211
+          1
+          
388

+          0
+          0
+          0
+          0
+          1
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+          \\arm_cortexM4lf_fir_example\../arm_fir_example_f32.c\211
+        
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+          214
+          1
+          
390

+          0
+          0
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+          \\arm_cortexM4lf_fir_example\../arm_fir_example_f32.c\214
+        
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+        0
+        0
+        0
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+        0
+        0
+      
+      
+      
+    
+  
+
+  
+    Source Group 1
+    1
+    0
+    0
+    
+      1
+      1
+      1
+      0
+      0
+      77
+      0
+      0
+      0
+      0
+      ..\arm_fir_data.c
+      arm_fir_data.c
+    
+    
+      1
+      2
+      1
+      0
+      0
+      0
+      0
+      1
+      1
+      0
+      ..\arm_fir_example_f32.c
+      arm_fir_example_f32.c
+    
+    
+      1
+      3
+      1
+      0
+      0
+      16
+      0
+      0
+      0
+      0
+      ..\..\Common\Source\math_helper.c
+      math_helper.c
+    
+  
+
+  
+    CMSIS DeviceSupport
+    1
+    0
+    0
+    
+      2
+      4
+      1
+      0
+      0
+      43
+      0
+      0
+      0
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+      ..\system_ARMCM4.c
+      system_ARMCM4.c
+    
+    
+      2
+      5
+      2
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      .\startup_ARMCM4.s
+      startup_ARMCM4.s
+    
+  
+
+  
+    CMSIS SW_DSP_Library
+    1
+    0
+    0
+    
+      3
+      6
+      4
+      0
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+      0
+      0
+      0
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+      ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib
+      arm_cortexM4lf_math.lib
+    
+  
+
+  
+    1
+    0
+    
+      100
+      0
+      
+        
+          ..\arm_fir_example_f32.c
+          0
+          1
+          1
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvproj
new file mode 100644
index 0000000..8d68e44
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_cortexM4lf_fir_example.uvproj
@@ -0,0 +1,435 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M4 FPU
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2
+          
+          
+          
+          5237
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\debug\
+          arm_cortexM4lf_fir_example
+          1
+          0
+          0
+          1
+          1
+          .\debug\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
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+            0
+          
+          
+            0
+            0
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+            0
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+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          
+          DCM.DLL
+          -pCM3
+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM3
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            0
+            1
+            0
+            1
+            1
+            1
+            0
+            1
+          
+          0
+          -1
+          
+            
+            
+            
+            
+            .\arm_fir_example.ini
+          
+          
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            0
+            -1
+          
+          
+          
+          
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
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+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            0
+            0
+            0
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+            2
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+            
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+                0x0
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+              
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+                0x0
+              
+              
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+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
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+              
+                1
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+                0x0
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+            3
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            
+              
+              ARM_MATH_CM4, __FPU_PRESENT = 1
+              
+              ..\..\Common\Include;..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x00000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Source Group 1
+          
+            
+              arm_fir_data.c
+              1
+              ..\arm_fir_data.c
+            
+            
+              arm_fir_example_f32.c
+              1
+              ..\arm_fir_example_f32.c
+            
+            
+              math_helper.c
+              1
+              ..\..\Common\Source\math_helper.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM4.c
+              1
+              ..\system_ARMCM4.c
+            
+            
+              startup_ARMCM4.s
+              2
+              .\startup_ARMCM4.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+          
+            
+              arm_cortexM4lf_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_fir_example.ini b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_fir_example.ini
new file mode 100644
index 0000000..06c86a6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/arm_fir_example.ini
@@ -0,0 +1,12 @@
+
+/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions 
+   
+   The file can be executed in the following way:
+   1) manually from uVision command window (in debug mode) using command:
+   INCLUIDE arm_fir_lpf_example.ini	 
+
+*/
+
+// usual initialisation	for target setup
+MAP  0x20000000, 0x20008000  READ WRITE  // allow R/W access to IO space
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..0acd346
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM0.s
@@ -0,0 +1,144 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Cortex-M0 Core Device Startup File
+; *           for CM0 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..5af584b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM3.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Cortex-M3 Core Device Startup File
+; *           for CM3 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..09fdbd6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/ARM/startup_ARMCM4.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM4 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_data.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_data.c
new file mode 100644
index 0000000..e2e9ad6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_data.c
@@ -0,0 +1,94 @@
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+** Test input signal contains 1000Hz + 15000 Hz
+** ------------------------------------------------------------------- */
+
+float32_t testInput_f32_1kHz_15kHz[320] =
+{
++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, 
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, 
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, 
+-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, 
+-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, 
+-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, 
++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, 
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, 
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, 
++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, 
+-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, 
+-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, 
++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, 
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, 
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, 
++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, 
+-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, 
+-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, 
+-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, 
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, 
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, 
+-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, 
+-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, 
+-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, 
++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, 
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, 
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, 
++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, 
+-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, 
+-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, 
+-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, 
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, 
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, 
++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, 
+-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, 
+-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, 
+-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, 
++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, 
++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, 
++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, 
+};
+
+float32_t refOutput[320] = 
+{
++0.0000000000f, -0.0010797829f, -0.0007681386f, -0.0001982932f, +0.0000644313f, +0.0020854271f, +0.0036891871f, +0.0015855941f, 
+-0.0026280805f, -0.0075907658f, -0.0119390538f, -0.0086665968f, +0.0088981202f, +0.0430539279f, +0.0974468742f, +0.1740405600f, 
++0.2681416601f, +0.3747720089f, +0.4893362230f, +0.6024154672f, +0.7058740791f, +0.7968348987f, +0.8715901940f, +0.9277881093f, 
++0.9682182661f, +0.9934674267f, +1.0012052245f, +0.9925859371f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, 
++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, 
+-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, 
+-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, 
+-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, 
++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, 
++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, 
++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, 
+-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, 
+-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, 
+-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, 
++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, 
++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, 
++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, 
+-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, 
+-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, 
+-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, 
++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, 
++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, 
++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, 
+-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, 
+-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, 
+-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, 
++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, 
++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, 
++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, 
+-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, 
+-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, 
+-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, -0.0000000000f, +0.1309866321f, 
++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, 
++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, 
++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, 
+-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, 
+-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, 
+-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, 
++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, 
++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f 
+};
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_example_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_example_f32.c
new file mode 100644
index 0000000..fba4140
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/arm_fir_example_f32.c
@@ -0,0 +1,220 @@
+/* ---------------------------------------------------------------------- 
+ * Copyright (C) 2010 ARM Limited. All rights reserved.   
+ *  
+ * $Date:           29. November 2010  
+ * $Revision: 	    V1.0.3  
+ *  
+ * Project: 	    CMSIS DSP Library  
+ * Title:	        arm_fir_example_f32.c		  
+ *  
+ * Description:	Example code demonstrating how an FIR filter can be used
+ *               as a low pass filter.
+ * 
+ * Target Processor: Cortex-M4/Cortex-M3  
+ *
+ *
+ * Version 1.0.3 2010/11/29 
+ *    Re-organized the CMSIS folders and updated documentation. 
+ * 
+ * Version 1.0.1 2010/10/05 KK 
+ *    Production release and review comments incorporated.  
+ *
+ * Version 1.0.0 2010/09/20 KK
+ *    Production release and review comments incorporated.
+ * ------------------------------------------------------------------- */ 
+ 
+/** 
+ * @ingroup groupExamples 
+ */ 
+ 
+/**    
+ * @defgroup FIRLPF FIR Lowpass Filter Example
+ * 
+ * \par Description: 
+ * \par
+ * Removes high frequency signal components from the input using an FIR lowpass filter.
+ * The example demonstrates how to configure an FIR filter and then pass data through
+ * it in a block-by-block fashion.
+ * \image html FIRLPF_signalflow.gif 
+ * 
+ * \par Algorithm:
+ * \par
+ * The input signal is a sum of two sine waves:  1 kHz and 15 kHz.
+ * This is processed by an FIR lowpass filter with cutoff frequency 6 kHz.
+ * The lowpass filter eliminates the 15 kHz signal leaving only the 1 kHz sine wave at the output.
+ * \par
+ * The lowpass filter was designed using MATLAB with a sample rate of 48 kHz and 
+ * a length of 29 points.
+ * The MATLAB code to generate the filter coefficients is shown below:
+ * 
+ *     h = fir1(28, 6/24);
+ * 

+ * The first argument is the "order" of the filter and is always one less than the desired length.
+ * The second argument is the normalized cutoff frequency.  This is in the range 0 (DC) to 1.0 (Nyquist).
+ * A 6 kHz cutoff with a Nyquist frequency of 24 kHz lies at a normalized frequency of 6/24 = 0.25.
+ * The CMSIS FIR filter function requires the coefficients to be in time reversed order.
+ * 
+ *     fliplr(h)
+ * 

+ * The resulting filter coefficients and are shown below.  
+ * Note that the filter is symmetric (a property of linear phase FIR filters)
+ * and the point of symmetry is sample 14.  Thus the filter will have a delay of
+ * 14 samples for all frequencies.
+ * \par
+ * \image html FIRLPF_coeffs.gif 
+ * \par
+ * The frequency response of the filter is shown next.  
+ * The passband gain of the filter is 1.0 and it reaches 0.5 at the cutoff frequency 6 kHz.
+ * \par
+ * \image html FIRLPF_response.gif 
+ * \par
+ * The input signal is shown below.
+ * The left hand side shows the signal in the time domain while the right hand side is a frequency domain representation.
+ * The two sine wave components can be clearly seen.
+ * \par
+ * \image html FIRLPF_input.gif 
+ * \par
+ * The output of the filter is shown below.  The 15 kHz component has been eliminated.
+ * \par
+ * \image html FIRLPF_output.gif 
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInput_f32_1kHz_15kHz points to the input data
+ * \li \c refOutput points to the reference output data
+ * \li \c testOutput points to the test output data
+ * \li \c firStateF32 points to state buffer
+ * \li \c firCoeffs32 points to coefficient buffer
+ * \li \c blockSize number of samples processed at a time
+ * \li \c numBlocks number of frames 
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_fir_init_f32()
+ * - arm_fir_f32() 
+ * 
+ *  Refer   
+ * \link arm_fir_example_f32.c \endlink
+ * 
+ */ 
+ 
+ 
+/** \example arm_fir_example_f32.c 
+ */  
+ 
+/* ---------------------------------------------------------------------- 
+** Include Files  
+** ------------------------------------------------------------------- */ 
+
+#include "arm_math.h" 
+#include "math_helper.h"
+ 
+/* ---------------------------------------------------------------------- 
+** Macro Defines  
+** ------------------------------------------------------------------- */ 
+
+#define TEST_LENGTH_SAMPLES 320 
+#define SNR_THRESHOLD_F32	140.0f 
+#define BLOCK_SIZE			32 
+#define NUM_TAPS			29 
+ 
+/* ------------------------------------------------------------------- 
+ * The input signal and reference output (computed with MATLAB)
+ * are defined externally in arm_fir_lpf_data.c.
+ * ------------------------------------------------------------------- */ 
+
+extern float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]; 
+extern float32_t refOutput[TEST_LENGTH_SAMPLES]; 
+ 
+/* ------------------------------------------------------------------- 
+ * Declare Test output buffer 
+ * ------------------------------------------------------------------- */ 
+
+static float32_t testOutput[TEST_LENGTH_SAMPLES]; 
+ 
+/* ------------------------------------------------------------------- 
+ * Declare State buffer of size (numTaps + blockSize - 1) 
+ * ------------------------------------------------------------------- */ 
+
+static float32_t firStateF32[BLOCK_SIZE + NUM_TAPS - 1]; 
+ 
+/* ---------------------------------------------------------------------- 
+** FIR Coefficients buffer generated using fir1() MATLAB function. 
+** fir1(28, 6/24)
+** ------------------------------------------------------------------- */ 
+ 
+const float32_t firCoeffs32[NUM_TAPS] = { 
+-0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, 
+-0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, 
++0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, 
++0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f 
+}; 
+ 
+/* ------------------------------------------------------------------ 
+ * Global variables for FIR LPF Example 
+ * ------------------------------------------------------------------- */ 
+
+uint32_t blockSize = BLOCK_SIZE; 
+uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE; 
+ 
+float32_t  snr; 
+ 
+/* ---------------------------------------------------------------------- 
+ * FIR LPF Example 
+ * ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+  uint32_t i; 
+  arm_fir_instance_f32 S; 
+  arm_status status; 
+  float32_t  *inputF32, *outputF32; 
+ 
+  /* Initialize input and output buffer pointers */ 
+  inputF32 = &testInput_f32_1kHz_15kHz[0];	 
+  outputF32 = &testOutput[0]; 
+
+  /* Call FIR init function to initialize the instance structure. */
+  arm_fir_init_f32(&S, NUM_TAPS, (float32_t *)&firCoeffs32[0], &firStateF32[0], blockSize); 
+ 
+  /* ---------------------------------------------------------------------- 
+  ** Call the FIR process function for every blockSize samples  
+  ** ------------------------------------------------------------------- */ 
+
+  for(i=0; i < numBlocks; i++)  
+    {	 
+      arm_fir_f32(&S, inputF32 + (i * blockSize), outputF32 + (i * blockSize), blockSize);  
+    } 
+ 
+  /* ---------------------------------------------------------------------- 
+  ** Compare the generated output against the reference output computed
+  ** in MATLAB.
+  ** ------------------------------------------------------------------- */ 
+
+  snr = arm_snr_f32(&refOutput[0], &testOutput[0], TEST_LENGTH_SAMPLES); 
+ 
+  if (snr < SNR_THRESHOLD_F32) 
+    { 
+      status = ARM_MATH_TEST_FAILURE; 
+    } 
+  else
+    {
+      status = ARM_MATH_SUCCESS; 
+    }
+	 
+  /* ---------------------------------------------------------------------- 
+  ** Loop here if the signal does not match the reference output.
+  ** ------------------------------------------------------------------- */ 
+	 
+  if( status != ARM_MATH_SUCCESS) 
+    { 
+      while(1); 
+    } 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+/** \endlink */ 
+ 
+ 
+ 
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM0.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM0.c
new file mode 100644
index 0000000..ece74d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM0.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Cortex-M0 Device System Source File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM3.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM3.c
new file mode 100644
index 0000000..2f5fa0b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM3.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Cortex-M3 Device System Source File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM4.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM4.c
new file mode 100644
index 0000000..beaaf6f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_fir_example/system_ARMCM4.c
@@ -0,0 +1,81 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Cortex-M4 Device System Source File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM4.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvopt
new file mode 100644
index 0000000..bcef850
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvopt
@@ -0,0 +1,318 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
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+        1
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+      
+        1
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+          0
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+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)
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+      arm_graphic_equalizer_example_q31.c
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvproj
new file mode 100644
index 0000000..dc567cc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM0l_graphic_equalizer_example.uvproj
@@ -0,0 +1,435 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M0
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE
+          
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new file mode 100644
index 0000000..8dff7c4
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+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM3l_graphic_equalizer_example.uvopt
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new file mode 100644
index 0000000..f1246b6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM4lf_graphic_equalizer_example.uvopt
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+      0
+      0
+      ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib
+      arm_cortexM4lf_math.lib
+    
+  
+
+  
+    1
+    0
+    
+      100
+      0
+      
+        
+          ..\arm_graphic_equalizer_example_q31.c
+          0
+          1
+          1
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM4lf_graphic_equalizer_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM4lf_graphic_equalizer_example.uvproj
new file mode 100644
index 0000000..71acd00
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_cortexM4lf_graphic_equalizer_example.uvproj
@@ -0,0 +1,435 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M4 FPU
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2
+          
+          
+          
+          5237
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\debug\
+          arm_cortexM4lf_graphic_equalizer_example
+          1
+          0
+          0
+          1
+          1
+          .\debug\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            0
+            1
+            0
+            1
+            1
+            1
+            0
+            1
+          
+          0
+          -1
+          
+            
+            
+            
+            
+            .\arm_graphic_equalizer_example.ini
+          
+          
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            0
+            -1
+          
+          
+          
+          
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            5
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            3
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            
+              
+              ARM_MATH_CM4, __FPU_PRESENT = 1
+              
+              ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x00000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Source Group 1
+          
+            
+              arm_graphic_equalizer_data.c
+              1
+              ..\arm_graphic_equalizer_data.c
+            
+            
+              arm_graphic_equalizer_example_q31.c
+              1
+              ..\arm_graphic_equalizer_example_q31.c
+            
+            
+              math_helper.c
+              1
+              ..\..\Common\Source\math_helper.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM4.c
+              1
+              ..\system_ARMCM4.c
+            
+            
+              startup_ARMCM4.s
+              2
+              .\startup_ARMCM4.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+          
+            
+              arm_cortexM4lf_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_graphic_equalizer_example.ini b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_graphic_equalizer_example.ini
new file mode 100644
index 0000000..4e1a3e4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/arm_graphic_equalizer_example.ini
@@ -0,0 +1,14 @@
+
+/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions 
+   
+   The file can be executed in the following way:
+   1) manually from uVision command window (in debug mode) using command:
+   INCLUIDE arm_geq_5band_example.ini	 
+
+*/
+
+
+// usual initialisation	for target setup
+MAP  0x20000000, 0x20008000  READ WRITE  // allow R/W access to IO space
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..0acd346
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM0.s
@@ -0,0 +1,144 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Cortex-M0 Core Device Startup File
+; *           for CM0 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..5af584b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM3.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Cortex-M3 Core Device Startup File
+; *           for CM3 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..09fdbd6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/ARM/startup_ARMCM4.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM4 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c
new file mode 100644
index 0000000..b1a314e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c
@@ -0,0 +1,94 @@
+#include "arm_math.h"
+
+float32_t testRefOutput_f32[320] = {
+
+0.000000000000000000,	0.001898396760225296,	0.004215449094772339,	0.007432077080011368,	0.010948467999696732,	0.015026375651359558,	0.019191544502973557,	0.023574527353048325,	
+0.027919445186853409,	0.032277785241603851,	0.036551639437675476,	0.040732793509960175,	0.044799156486988068,	0.048710610717535019,	0.052476800978183746,	0.056059073656797409,	
+0.059482168406248093,	0.062726479023694992,	0.065821025520563126,	0.068763464689254761,	0.071577839553356171,	0.074270240962505341,	0.076856281608343124,	0.079344697296619415,	
+0.081745062023401260,	0.084067162126302719,	0.086318407207727432,	0.088509257882833481,	0.090647127479314804,	0.092742368578910828,	0.094802625477313995,	0.096837285906076431,	
+0.098853722214698792,	0.100859899073839190,	0.102862443774938580,	0.104867763817310330,	0.106881409883499150,	0.108908228576183320,	0.110952425748109820,	0.113017357885837550,	
+0.115105822682380680,	0.117219865322113040,	0.119361080229282380,	0.121530555188655850,	0.123729091137647630,	0.125957202166318890,	0.128215309232473370,	0.130503740161657330,	
+0.132822841405868530,	0.135173004120588300,	0.137554679065942760,	0.139968376606702800,	0.142414685338735580,	0.144894234836101530,	0.147407654672861100,	0.149955596774816510,	
+0.152538605034351350,	0.155157200992107390,	0.157811731100082400,	0.160502441227436070,	0.163229387253522870,	0.165992442518472670,	0.168791320174932480,	0.171625509858131410,	
+0.174494370818138120,	0.177397061139345170,	0.180332608520984650,	0.183299910277128220,	0.186297744512557980,	0.189324837177991870,	0.192379791289567950,	0.195461250841617580,	
+0.198567759245634080,	0.201697919517755510,	0.204850304871797560,	0.208023533225059510,	0.211216274648904800,	0.214427210390567780,	0.217655111104249950,	0.220898788422346120,	
+0.224157124757766720,	0.227429077029228210,	0.230713658034801480,	0.234009962528944020,	0.237317133694887160,	0.240634419023990630,	0.243961080908775330,	0.247296508401632310,	
+0.250640105456113820,	0.253991369158029560,	0.257349837571382520,	0.260715119540691380,	0.264086868613958360,	0.267464816570281980,	0.270848698914051060,	0.274238351732492450,	
+0.277633611112833020,	0.281034380197525020,	0.284440591931343080,	0.287852220237255100,	0.291269283741712570,	0.294691801071166990,	0.298119872808456420,	0.301553562283515930,	
+0.304993014782667160,	0.308438356965780260,	0.311889752745628360,	0.315347377210855480,	0.318811416625976560,	0.322282072156667710,	0.325759567320346830,	0.329244095832109450,	
+0.332735907286405560,	0.336235217750072480,	0.339742250740528110,	0.343257248401641850,	0.346780419349670410,	0.350311983376741410,	0.353852160274982450,	0.357401121407747270,	
+0.360959105193614960,	0.364526227116584780,	0.368102725595235820,	0.371688675135374070,	0.375284302979707720,	0.378889638930559160,	0.382504884153604510,	0.386130042374134060,	
+0.389765247702598570,	0.393410529941320420,	0.397065933793783190,	0.400731507688760760,	0.404407206922769550,	0.408093083649873730,	0.411789052188396450,	0.415495119988918300,	
+0.419211201369762420,	0.422937240451574330,	0.426673140376806260,	0.430418811738491060,	0.434174135327339170,	0.437938995659351350,	0.441713258624076840,	0.445496778935194020,	
+0.449289388954639430,	0.453090950846672060,	0.456901267170906070,	0.460720170289278030,	0.464547459036111830,	0.468382950872182850,	0.472226426005363460,	0.476077698171138760,	
+0.479936532676219940,	0.483802750706672670,	0.487676106393337250,	0.491556398570537570,	0.495443399995565410,	0.499336875975131990,	0.503236617892980580,	0.507142387330532070,	
+0.511053957045078280,	0.514971107244491580,	0.518893606960773470,	0.522821225225925450,	0.526753749698400500,	0.530690938234329220,	0.534632585942745210,	0.538578454405069350,	
+0.542528338730335240,	0.546481993049383160,	0.550439231097698210,	0.554399792104959490,	0.558363504707813260,	0.562330115586519240,	0.566299438476562500,	0.570271246135234830,	
+0.574245333671569820,	0.578221492469310760,	0.582199502736330030,	0.586179181933403020,	0.590160276740789410,	0.594142623245716090,	0.598125983029603960,	0.602110169827938080,	
+0.606094967573881150,	0.610080175101757050,	0.614065583795309070,	0.618050977587699890,	0.622036151587963100,	0.626020893454551700,	0.630004994571208950,	0.633988231420516970,	
+0.637970402836799620,	0.641951277852058410,	0.645930647850036620,	0.649908289313316350,	0.653883971273899080,	0.657857488840818410,	0.661828581243753430,	0.665797054767608640,	
+0.669762641191482540,	0.673725124448537830,	0.677684243768453600,	0.681639779359102250,	0.685591462999582290,	0.689539063721895220,	0.693482317030429840,	0.697420965880155560,	
+0.701354760676622390,	0.705283410847187040,	0.709206689149141310,	0.713124278932809830,	0.717035952955484390,	0.720941375941038130,	0.724840316921472550,	0.728732451796531680,	
+0.732617516070604320,	0.736495196819305420,	0.740365199744701390,	0.744227230548858640,	0.748080968856811520,	0.751926124095916750,	0.755762357264757160,	0.759589381515979770,	
+0.763406842947006230,	0.767214450985193250,	0.771011855453252790,	0.774798732250928880,	0.778574761003255840,	0.782339565455913540,	0.786092851310968400,	0.789834223687648770,	
+0.793563373386859890,	0.797279909253120420,	0.800983514636754990,	0.804673787206411360,	0.808350402861833570,	0.812012966722249980,	0.815661124885082240,	0.819294504821300510,	
+0.822912722826004030,	0.826515413820743560,	0.830102190375328060,	0.833672653883695600,	0.837226435542106630,	0.840763118118047710,	0.844282336533069610,	0.847783654928207400,	
+0.851266715675592420,	0.854731071740388870,	0.858176350593566890,	0.861602116376161580,	0.865007970482110980,	0.868393491953611370,	0.871758259832859040,	0.875101849436759950,	
+0.878423850983381270,	0.881723806262016300,	0.885001312941312790,	0.888255912810564040,	0.891487173736095430,	0.894694659858942030,	0.897877920418977740,	0.901036512106657030,	
+0.904169965535402300,	0.907277844846248630,	0.910359673202037810,	0.913415014743804930,	0.916443370282649990,	0.919444311410188670,	0.922417331486940380,	0.925361987203359600,	
+0.928277771919965740,	0.931164238601922990,	0.934020876884460450,	0.936847217381000520,	0.939642757177352910,	0.942407000809907910,	0.945139460265636440,	0.947839632630348210,	
+0.950507018715143200,	0.953141096979379650,	0.955741371959447860,	0.958307322114706040,	0.960838429629802700,	0.963334184139966960,	0.965794049203395840,	0.968217510730028150,	
+0.970604017376899720,	0.972953058779239650,	0.975264083594083790,	0.977536566555500030,	0.979769956320524220,	0.981963708996772770,	0.984117280691862110,	0.986230112612247470,	
+0.988301653414964680,	0.990331344306468960,	0.992318630218505860,	0.994262944906950000,	0.996163722127676010,	0.998020399361848830,	0.999832402914762500,	1.001599155366420700,	
+1.003320086747407900,	1.004994612187147100,	1.006622135639190700,	1.008202098309993700,	1.009733878076076500,	1.011216927319765100,	1.012650609016418500,	1.014034371823072400,	
+1.015367589890956900,	1.016649682074785200,	1.017880033701658200,	1.019058048725128200,	1.020183108747005500,	1.021254621446132700,	1.022271949797868700,	1.023234523832798000,	
+
+};
+/* ----------------------------------------------------------------------
+** Test input - logarithmic chirp signal
+** ------------------------------------------------------------------- */
+
+float32_t testInput_f32[320] =
+  {
+    0.000000000000000061,	0.002622410992047861,	0.005253663973466970,	0.007893770384930297,	0.010542741395035495,	0.013200587895525877,	0.015867320496454066,	0.018542949521290073,	
+0.021227485001971542,	0.023920936673895138,	0.026623313970853074,	0.029334626019908643,	0.032054881636210709,	0.034784089317753723,	0.037522257240071598,	0.040269393250875855,	
+0.043025504864628375,	0.045790599257054837,	0.048564683259595690,	0.051347763353792118,	0.054139845665610427,	0.056940935959702531,	0.059751039633601337,	0.062570161711849828,	
+0.065398306840066575,	0.068235479278943648,	0.071081682898178900,	0.073936921170339814,	0.076801197164660218,	0.079674513540768196,	0.082556872542344922,	0.085448275990715375,	
+0.088348725278367082,	0.091258221362398390,	0.094176764757897533,	0.097104355531246703,	0.100040993293358240,	0.102986677192832010,	0.105941405909045980,	0.108905177645166230,	
+0.111877990121087980,	0.114859840566297130,	0.117850725712659680,	0.120850641787131110,	0.123859584504392860,	0.126877549059407400,	0.129904530119898690,	0.132940521818751430,	
+0.135985517746334080,	0.139039510942737950,	0.142102493889940090,	0.145174458503884160,	0.148255396126476810,	0.151345297517508140,	0.154444152846483080,	0.157551951684374300,	
+0.160668682995289720,	0.163794335128054890,	0.166928895807713030,	0.170072352126936720,	0.173224690537355760,	0.176385896840798810,	0.179555956180445340,	0.182734853031894270,	
+0.185922571194139130,	0.189119093780459800,	0.192324403209221870,	0.195538481194587030,	0.198761308737133020,	0.201992866114384050,	0.205233132871247170,	0.208482087810360570,	
+0.211739708982344370,	0.215005973675965020,	0.218280858408200220,	0.221564338914212730,	0.224856390137231970,	0.228156986218334190,	0.231466100486134670,	0.234783705446379690,	
+0.238109772771442410,	0.241444273289723230,	0.244787176974952890,	0.248138452935395580,	0.251498069402956710,	0.254865993722190930,	0.258242192339209860,	0.261626630790492030,	
+0.265019273691591620,	0.268420084725748410,	0.271829026632395280,	0.275246061195565440,	0.278671149232197430,	0.282104250580339830,	0.285545324087251580,	0.288994327597401960,	
+0.292451217940364990,	0.295915950918612280,	0.299388481295203350,	0.302868762781368150,	0.306356748023990040,	0.309852388592980640,	0.313355634968552230,	0.316866436528383590,	
+0.320384741534681720,	0.323910497121136620,	0.327443649279772870,	0.330984142847692230,	0.334531921493712690,	0.338086927704900790,	0.341649102772995210,	0.345218386780727190,	
+0.348794718588032520,	0.352378035818156910,	0.355968274843654950,	0.359565370772282730,	0.363169257432780890,	0.366779867360555120,	0.370397131783246010,	0.374020980606193880,	
+0.377651342397795690,	0.381288144374756830,	0.384931312387234990,	0.388580770903877330,	0.392236442996751310,	0.395898250326170650,	0.399566113125414350,	0.403239950185338420,	
+0.406919678838884410,	0.410605214945482130,	0.414296472875345100,	0.417993365493664670,	0.421695804144698540,	0.425403698635752780,	0.429116957221065130,	0.432835486585582130,	
+0.436559191828633180,	0.440287976447505720,	0.444021742320914510,	0.447760389692375140,	0.451503817153472210,	0.455251921627031540,	0.459004598350192470,	0.462761740857380200,	
+0.466523240963184150,	0.470288988745136360,	0.474058872526396560,	0.477832778858340690,	0.481610592503056990,	0.485392196415748600,	0.489177471727042850,	0.492966297725213780,	
+0.496758551838309250,	0.500554109616195060,	0.504352844712508190,	0.508154628866524960,	0.511959331884944910,	0.515766821623591440,	0.519576963969030530,	0.523389622820107150,	
+0.527204660069405030,	0.531021935584629400,	0.534841307189911630,	0.538662630647041900,	0.542485759636628150,	0.546310545739186690,	0.550136838416161340,	0.553964484990880020,	
+0.557793330629441700,	0.561623218321546380,	0.565453988861259300,	0.569285480827721570,	0.573117530565801950,	0.576949972166696630,	0.580782637448476910,	0.584615355936589420,	
+0.588447954844309340,	0.592280259053150400,	0.596112091093235260,	0.599943271123626440,	0.603773616912622660,	0.607602943818024150,	0.611431064767369080,	0.615257790238142090,	
+0.619082928237961740,	0.622906284284749700,	0.626727661386881850,	0.630546860023327600,	0.634363678123782030,	0.638177911048790960,	0.641989351569874020,	0.645797789849653410,	
+0.649603013421986450,	0.653404807172108140,	0.657202953316791350,	0.660997231384523490,	0.664787418195706640,	0.668573287842887610,	0.672354611671016960,	0.676131158257749170,	
+0.679902693393781730,	0.683668980063242500,	0.687429778424128110,	0.691184845788802130,	0.694933936604551380,	0.698676802434213370,	0.702413191936877570,	0.706142850848662460,	
+0.709865521963579990,	0.713580945114492330,	0.717288857154159800,	0.720988991936399870,	0.724681080297347790,	0.728364850036839040,	0.732040025899910680,	0.735706329558433620,	
+0.739363479592880620,	0.743011191474238440,	0.746649177546067850,	0.750277147006723990,	0.753894805891742180,	0.757501857056394940,	0.761098000158428880,	0.764682931640995540,	
+0.768256344715771980,	0.771817929346292900,	0.775367372231492210,	0.778904356789468790,	0.782428563141483460,	0.785939668096195860,	0.789437345134148760,	0.792921264392515420,	
+0.796391092650110770,	0.799846493312681210,	0.803287126398485760,	0.806712648524170680,	0.810122712890953390,	0.813516969271127150,	0.816895063994893090,	0.820256639937531280,	
+0.823601336506926020,	0.826928789631450890,	0.830238631748229430,	0.833530491791779850,	0.836803995183058700,	0.840058763818912760,	0.843294416061954100,	0.846510566730867220,	
+0.849706827091166740,	0.852882804846411770,	0.856038104129895340,	0.859172325496819990,	0.862285065916973510,	0.865375918767918860,	0.868444473828712590,	0.871490317274166260,	
+0.874513031669661770,	0.877512195966544280,	0.880487385498096800,	0.883438171976119850,	0.886364123488128100,	0.889264804495180530,	0.892139775830360640,	0.894988594697921020,	
+0.897810814673113080,	0.900605985702712770,	0.903373654106265470,	0.906113362578062300,	0.908824650189867690,	0.911507052394417540,	0.914160101029702910,	0.916783324324059180,	
+0.919376246902079860,	0.921938389791372770,	0.924469270430179120,	0.926968402675872660,	0.929435296814361430,	0.931869459570409790,	0.934270394118903560,	0.936637600097074200,	
+0.938970573617708970,	0.941268807283364040,	0.943531790201601380,	0.945759008001275100,	0.947949942849885320,	0.950104073472023970,	0.952220875168933280,	0.954299819839202090,	
+0.956340376000621160,	0.958342008813221960,	0.960304180103520260,	0.962226348389994210,	0.964107968909812760,	0.965948493646846980,	0.967747371360983650,	0.969504047618768740,	
+0.971217964825405680,	0.972888562258134030,	0.974515276101013520,	0.976097539481141750,	0.977634782506330400,	0.979126432304266880,	0.980571913063189360,	0.981970646074102120,	
+0.983322049774557390,	0.984625539794035220,	0.985880529000944810,	0.987086427551279730,	0.988242642938953360,	0.989348580047844540,	0.990403641205582440,	0.991407226239099710,	
+0.992358732531984260,	0.993257555083659870,	0.994103086570423680,	0.994894717408374870,	0.995631835818261310,	0.996313827892278070,	0.996940077662846650,	0.997509967173408010,	
+
+  };
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c
new file mode 100644
index 0000000..3a551fc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c
@@ -0,0 +1,394 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:         29. November 2010  
+* $Revision: 	  V1.0.3 
+*  
+* Project: 	  CMSIS DSP Library  
+* Title:	      arm_graphic_equalizer_example_q31.c		  
+*  
+* Description:	Example showing an audio graphic equalizer constructed
+*              out of Biquad filters.
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+/** 
+ * @ingroup groupExamples 
+ */ 
+ 
+/**    
+ * @defgroup GEQ5Band Graphic Audio Equalizer Example
+ * 
+ * \par Description: 
+ * \par
+ * This example demonstrates how a 5-band graphic equalizer can be constructed
+ * using the Biquad cascade functions.  
+ * A graphic equalizer is used in audio applications to vary the tonal quality
+ * of the audio.
+ *
+ * \par Block Diagram:
+ * \par
+ * The design is based on a cascade of 5 filter sections.
+ * \image html GEQ_signalflow.gif 
+ * Each filter section is 4th order and consists of a cascade of two Biquads.
+ * Each filter has a nominal gain of 0 dB (1.0 in linear units) and
+ * boosts or cuts signals within a specific frequency range.
+ * The edge frequencies between the 5 bands are 100, 500, 2000, and 6000 Hz.
+ * Each band has an adjustable boost or cut in the range of +/- 9 dB.
+ * For example, the band that extends from 500 to 2000 Hz has the response shown below:
+ * \par
+ * \image html GEQ_bandresponse.gif 
+ * \par
+ * With 1 dB steps, each filter has a total of 19 different settings.
+ * The filter coefficients for all possible 19 settings were precomputed
+ * in MATLAB and stored in a table.  With 5 different tables, there are
+ * a total of 5 x 19 = 95 different 4th order filters. 
+ * All 95 responses are shown below:
+ * \par
+ * \image html GEQ_allbandresponse.gif 
+ * \par
+ * Each 4th order filter has 10 coefficents for a grand total of 950 different filter
+ * coefficients that must be tabulated. The input and output data is in Q31 format.
+ * For better noise performance, the two low frequency bands are implemented using the high 
+ * precision 32x64-bit Biquad filters. The remaining 3 high frequency bands use standard 
+ * 32x32-bit Biquad filters. The input signal used in the example is a logarithmic chirp.
+ * \par
+ * \image html GEQ_inputchirp.gif
+ * \par
+ * The array bandGains specifies the gain in dB to apply in each band.
+ * For example, if bandGains={0, -3, 6, 4, -6}; then the output signal will be:
+ * \par
+ * \image html GEQ_outputchirp.gif
+ * \par
+ * \note The output chirp signal follows the gain or boost of each band.
+ * \par
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInput_f32 points to the input data
+ * \li \c testRefOutput_f32 points to the reference output data
+ * \li \c testOutput points to the test output data
+ * \li \c inputQ31 temporary input buffer
+ * \li \c outputQ31 temporary output buffer 
+ * \li \c biquadStateBand1Q31 points to state buffer for band1
+ * \li \c biquadStateBand2Q31 points to state buffer for band2
+ * \li \c biquadStateBand3Q31 points to state buffer for band3
+ * \li \c biquadStateBand4Q31 points to state buffer for band4
+ * \li \c biquadStateBand5Q31 points to state buffer for band5
+ * \li \c coeffTable points to coefficient buffer for all bands
+ * \li \c gainDB gain buffer which has gains applied for all the bands
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_biquad_cas_df1_32x64_init_q31()
+ * - arm_biquad_cas_df1_32x64_q31()
+ * - arm_biquad_cascade_df1_init_q31()
+ * - arm_biquad_cascade_df1_q31()
+ * - arm_scale_q31()
+ * - arm_scale_f32()
+ * - arm_float_to_q31()
+ * - arm_q31_to_float()
+ *
+ *  Refer   
+ * \link arm_graphic_equalizer_example_q31.c \endlink
+ * 
+ */ 
+ 
+ 
+/** \example arm_graphic_equalizer_example_q31.c 
+ */  
+ 
+#include "arm_math.h" 
+#include "math_helper.h"
+
+/* Length of the overall data in the test */ 
+#define TESTLENGTH 320
+
+/* Block size for the underlying processing */
+#define BLOCKSIZE 32
+
+/* Total number of blocks to run */
+#define NUMBLOCKS (TESTLENGTH/BLOCKSIZE)
+
+/* Number of 2nd order Biquad stages per filter */
+#define NUMSTAGES 2
+
+#define SNR_THRESHOLD_F32  98
+ 
+/* ------------------------------------------------------------------- 
+ * External Declarations for Input and Output buffers 
+ * ------------------------------------------------------------------- */
+ 
+extern float32_t testInput_f32[TESTLENGTH]; 
+static float32_t testOutput[TESTLENGTH]; 
+
+extern float32_t testRefOutput_f32[TESTLENGTH];
+
+/* ----------------------------------------------------------------------  
+** Q31 state buffers for Band1, Band2, Band3, Band4, Band5  
+** ------------------------------------------------------------------- */  
+   
+static q63_t biquadStateBand1Q31[4 * 2];   
+static q63_t biquadStateBand2Q31[4 * 2];   
+static q31_t biquadStateBand3Q31[4 * 2];   
+static q31_t biquadStateBand4Q31[4 * 2];   
+static q31_t biquadStateBand5Q31[4 * 2];   
+ 
+/* ----------------------------------------------------------------------  
+** Q31 input and output buffers  
+** ------------------------------------------------------------------- */  
+
+q31_t inputQ31[BLOCKSIZE];   
+q31_t outputQ31[BLOCKSIZE];  
+ 
+/* ----------------------------------------------------------------------
+** Entire coefficient table.  There are 10 coefficients per 4th order Biquad
+** cascade filter.  The first 10 coefficients correspond to the -9 dB gain
+** setting of band 1; the next 10 coefficient correspond to the -8 dB gain
+** setting of band 1; and so on.  There are 10*19=190 coefficients in total
+** for band 1 (gains = -9, -8, -7, ..., 9).  After this come the 190 coefficients
+** for band 2.
+**
+** The coefficients are in Q29 format and require a postShift of 2.
+** ------------------------------------------------------------------- */
+
+const q31_t coeffTable[950] = {
+
+	/* Band 1, -9 dB gain */
+	535576962, -1071153923, 535576962, 1073741824, -536870912, 535576962, -1063501998, 527979313, 1060865294, -524146981, 
+	/* Band 1, -8 dB gain */
+	535723226, -1071446451, 535723226, 1073741824, -536870912, 535723226, -1063568947, 527903217, 1061230578, -524503778, 
+	535868593, -1071737186, 535868593, 1073741824, -536870912, 535868593, -1063627467, 527819780, 1061585502, -524850686, 
+	536013181, -1072026363, 536013181, 1073741824, -536870912, 536013181, -1063677598, 527728935, 1061930361, -525187972, 
+	536157109, -1072314217, 536157109, 1073741824, -536870912, 536157109, -1063719372, 527630607, 1062265438, -525515897, 
+	536300492, -1072600983, 536300492, 1073741824, -536870912, 536300492, -1063752815, 527524720, 1062591011, -525834716, 
+	536443447, -1072886894, 536443447, 1073741824, -536870912, 536443447, -1063777945, 527411186, 1062907350, -526144676, 
+	536586091, -1073172183, 536586091, 1073741824, -536870912, 536586091, -1063794775, 527289917, 1063214717, -526446017, 
+	536728541, -1073457082, 536728541, 1073741824, -536870912, 536728541, -1063803308, 527160815, 1063513366, -526738975, 
+	536870912, -1073741824, 536870912, 1073741824, -536870912, 536870912, -1063803543, 527023777, 1063803543, -527023777, 
+	537013321, -1074026642, 537013321, 1073741824, -536870912, 537013321, -1063795470, 526878696, 1064085490, -527300648, 
+	537155884, -1074311768, 537155884, 1073741824, -536870912, 537155884, -1063779073, 526725455, 1064359439, -527569803, 
+	537298718, -1074597435, 537298718, 1073741824, -536870912, 537298718, -1063754328, 526563934, 1064625617, -527831454, 
+	537441939, -1074883878, 537441939, 1073741824, -536870912, 537441939, -1063721205, 526394005, 1064884245, -528085806, 
+	537585666, -1075171331, 537585666, 1073741824, -536870912, 537585666, -1063679666, 526215534, 1065135536, -528333059, 
+	537730015, -1075460030, 537730015, 1073741824, -536870912, 537730015, -1063629666, 526028380, 1065379699, -528573409, 
+	537875106, -1075750212, 537875106, 1073741824, -536870912, 537875106, -1063571152, 525832396, 1065616936, -528807045, 
+	538021057, -1076042114, 538021057, 1073741824, -536870912, 538021057, -1063504065, 525627429, 1065847444, -529034151, 
+	538167989, -1076335977, 538167989, 1073741824, -536870912, 538167989, -1063428338, 525413317, 1066071412, -529254907, 
+	
+	/* Band 2, -9 dB gain */
+	531784976, -1055497692, 523873415, 1066213307, -529420241, 531784976, -1040357886, 509828014, 1028908252, -494627367,
+	/* Band 2, -8 dB gain */ 
+	532357636, -1056601982, 524400080, 1066115844, -529326645, 532357636, -1040623406, 509562600, 1030462237, -496062122, 
+	532927392, -1057707729, 524931110, 1066024274, -529239070, 532927392, -1040848253, 509262081, 1031969246, -497457090, 
+	533494678, -1058816094, 525467240, 1065939047, -529157961, 533494678, -1041032161, 508925950, 1033429976, -498812573, 
+	534059929, -1059928204, 526009170, 1065860582, -529083734, 534059929, -1041174868, 508553717, 1034845124, -500128887, 
+	534623580, -1061045148, 526557561, 1065789260, -529016764, 534623580, -1041276126, 508144920, 1036215393, -501406373, 
+	535186068, -1062167969, 527113032, 1065725420, -528957385, 535186068, -1041335703, 507699125, 1037541500, -502645399, 
+	535747827, -1063297666, 527676151, 1065669351, -528905879, 535747827, -1041353386, 507215934, 1038824183, -503846368, 
+	536309295, -1064435183, 528247436, 1065621289, -528862476, 536309295, -1041328990, 506694984, 1040064203, -505009724, 
+	536870912, -1065581413, 528827349, 1065581413, -528827349, 536870912, -1041262354, 506135953, 1041262354, -506135953, 
+	537433117, -1066737194, 529416295, 1065549847, -528800610, 537433117, -1041153346, 505538564, 1042419457, -507225588, 
+	537996352, -1067903307, 530014622, 1065526651, -528782316, 537996352, -1041001864, 504902578, 1043536370, -508279208, 
+	538561061, -1069080480, 530622620, 1065511830, -528772462, 538561061, -1040807833, 504227800, 1044613981, -509297437, 
+	539127690, -1070269387, 531240527, 1065505333, -528770987, 539127690, -1040571205, 503514074, 1045653211, -510280946, 
+	539696690, -1071470656, 531868525, 1065507054, -528777778, 539696690, -1040291951, 502761277, 1046655011, -511230450, 
+	540268512, -1072684867, 532506750, 1065516837, -528792672, 540268512, -1039970063, 501969320, 1047620358, -512146700, 
+	540843613, -1073912567, 533155297, 1065534483, -528815459, 540843613, -1039605542, 501138139, 1048550251, -513030484, 
+	541422451, -1075154268, 533814224, 1065559750, -528845892, 541422451, -1039198394, 500267687, 1049445708, -513882621, 
+	542005489, -1076410460, 534483561, 1065592362, -528883686, 542005489, -1038748624, 499357932, 1050307760, -514703956, 
+	518903861, -1001986830, 486725277, 1037235801, -502367695, 518903861, -945834422, 446371043, 902366163, -400700571, 
+	520899989, -1005630916, 488289126, 1036926846, -502147311, 520899989, -946490935, 445581846, 907921945, -404936158, 
+	522893209, -1009290002, 489869792, 1036650484, -501961419, 522893209, -947006359, 444685310, 913306106, -409075225, 
+	524884763, -1012968199, 491470256, 1036407567, -501810737, 524884763, -947377809, 443679533, 918521018, -413116221, 
+	526875910, -1016669649, 493093518, 1036198712, -501695739, 526875910, -947602324, 442562672, 923569247, -417057897, 
+	528867927, -1020398503, 494742575, 1036024293, -501616651, 528867927, -947676875, 441332970, 928453558, -420899319, 
+	530862111, -1024158905, 496420407, 1035884447, -501573457, 530862111, -947598385, 439988777, 933176909, -424639872, 
+	532859778, -1027954970, 498129955, 1035779077, -501565907, 532859778, -947363742, 438528571, 937742446, -428279254, 
+	534862260, -1031790763, 499874098, 1035707863, -501593525, 534862260, -946969823, 436950987, 942153486, -431817474, 
+	536870912, -1035670279, 501655630, 1035670279, -501655630, 536870912, -946413508, 435254839, 946413508, -435254839, 
+	538887107, -1039597419, 503477238, 1035665609, -501751354, 538887107, -945691703, 433439146, 950526127, -438591937, 
+	540912240, -1043575967, 505341475, 1035692963, -501879659, 540912240, -944801359, 431503152, 954495080, -441829621, 
+	542947726, -1047609569, 507250741, 1035751307, -502039364, 542947726, -943739490, 429446349, 958324201, -444968987, 
+	544995000, -1051701717, 509207261, 1035839473, -502229165, 544995000, -942503190, 427268492, 962017400, -448011351, 
+	547055523, -1055855728, 511213065, 1035956193, -502447657, 547055523, -941089647, 424969617, 965578640, -450958226, 
+	549130774, -1060074734, 513269973, 1036100110, -502693359, 549130774, -939496155, 422550049, 969011913, -453811298, 
+	551222259, -1064361672, 515379585, 1036269804, -502964731, 551222259, -937720119, 420010407, 972321228, -456572401, 
+	553331507, -1068719280, 517543273, 1036463810, -503260192, 553331507, -935759057, 417351601, 975510582, -459243495, 
+	555460072, -1073150100, 519762181, 1036680633, -503578144, 555460072, -933610600, 414574832, 978583948, -461826644, 
+	494084017, -851422604, 404056273, 930151631, -423619864, 494084017, -673714108, 339502486, 561843007, -265801750, 
+	498713542, -859177141, 406587077, 929211656, -423786402, 498713542, -673274906, 338185129, 573719128, -272222942, 
+	503369016, -867012190, 409148384, 928362985, -424054784, 503369016, -672533059, 336693984, 585290277, -278599028, 
+	508052536, -874935599, 411746438, 927604291, -424422151, 508052536, -671478538, 335026905, 596558312, -284920289, 
+	512766286, -882955583, 414387826, 926933782, -424885216, 512766286, -670100998, 333182045, 607525792, -291177811, 
+	517512534, -891080712, 417079474, 926349262, -425440318, 517512534, -668389789, 331157902, 618195914, -297363485, 
+	522293635, -899319903, 419828635, 925848177, -426083491, 522293635, -666333963, 328953368, 628572440, -303470012, 
+	527112032, -907682405, 422642886, 925427679, -426810526, 527112032, -663922286, 326567785, 638659631, -309490882, 
+	531970251, -916177781, 425530105, 925084675, -427617023, 531970251, -661143261, 324000998, 648462180, -315420352, 
+	536870912, -924815881, 428498454, 924815881, -428498454, 536870912, -657985147, 321253420, 657985147, -321253420, 
+	541816719, -933606817, 431556352, 924617870, -429450209, 541816719, -654435997, 318326093, 667233900, -326985786, 
+	546810467, -942560921, 434712438, 924487114, -430467639, 546810467, -650483688, 315220754, 676214053, -332613816, 
+	551855042, -951688708, 437975532, 924420027, -431546101, 551855042, -646115970, 311939896, 684931422, -338134495, 
+	556953421, -961000826, 441354588, 924413001, -432680993, 556953421, -641320513, 308486839, 693391970, -343545389, 
+	562108672, -970508005, 444858642, 924462435, -433867780, 562108672, -636084967, 304865786, 701601770, -348844597, 
+	567323959, -980220994, 448496743, 924564764, -435102022, 567323959, -630397020, 301081886, 709566963, -354030710, 
+	572602539, -990150500, 452277894, 924716482, -436379394, 572602539, -624244471, 297141281, 717293726, -359102767, 
+	577947763, -1000307125, 456210977, 924914158, -437695705, 577947763, -617615296, 293051155, 724788245, -364060214, 
+	583363084, -1010701292, 460304674, 925154455, -439046908, 583363084, -610497723, 288819761, 732056685, -368902865, 
+	387379495, -506912469, 196933274, 840112184, -347208270, 387379495, 506912469, 196933274, -840112184, -347208270, 
+	401658082, -532275898, 207149427, 833765363, -343175316, 401658082, 532275898, 207149427, -833765363, -343175316, 
+	416472483, -558722695, 217902617, 827270154, -339107319, 416472483, 558722695, 217902617, -827270154, -339107319, 
+	431841949, -586290861, 229212798, 820624988, -335007540, 431841949, 586290861, 229212798, -820624988, -335007540, 
+	447786335, -615019650, 241100489, 813828443, -330879528, 447786335, 615019650, 241100489, -813828443, -330879528, 
+	464326111, -644949597, 253586805, 806879270, -326727141, 464326111, 644949597, 253586805, -806879270, -326727141, 
+	481482377, -676122557, 266693475, 799776409, -322554559, 481482377, 676122557, 266693475, -799776409, -322554559, 
+	499276882, -708581728, 280442865, 792519013, -318366296, 499276882, 708581728, 280442865, -792519013, -318366296, 
+	517732032, -742371685, 294857996, 785106465, -314167221, 517732032, 742371685, 294857996, -785106465, -314167221, 
+	536870912, -777538408, 309962566, 777538408, -309962566, 536870912, 777538408, 309962566, -777538408, -309962566, 
+	556717294, -814129313, 325780968, 769814766, -305757943, 556717294, 814129313, 325780968, -769814766, -305757943, 
+	577295658, -852193284, 342338310, 761935777, -301559360, 577295658, 852193284, 342338310, -761935777, -301559360, 
+	598631206, -891780698, 359660433, 753902014, -297373230, 598631206, 891780698, 359660433, -753902014, -297373230, 
+	620749877, -932943463, 377773927, 745714425, -293206383, 620749877, 932943463, 377773927, -745714425, -293206383, 
+	643678365, -975735041, 396706151, 737374355, -289066077, 643678365, 975735041, 396706151, -737374355, -289066077, 
+	667444134, -1020210487, 416485252, 728883588, -284960004, 667444134, 1020210487, 416485252, -728883588, -284960004, 
+	692075438, -1066426476, 437140179, 720244375, -280896294, 692075438, 1066426476, 437140179, -720244375, -280896294, 
+	717601336, -1114441339, 458700704, 711459472, -276883515, 717601336, 1114441339, 458700704, -711459472, -276883515, 
+	744051710, -1164315096, 481197437, 702532174, -272930673, 744051710, 1164315096, 481197437, -702532174, -272930673 
+
+};
+
+/* ----------------------------------------------------------------------
+** Desired gains, in dB, per band
+** ------------------------------------------------------------------- */
+
+int gainDB[5] = {0, -3, 6, 4, -6};
+
+float32_t snr;
+
+
+/* ---------------------------------------------------------------------- 
+ * Graphic equalizer Example 
+ * ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+  float32_t  *inputF32, *outputF32;  
+  arm_biquad_cas_df1_32x64_ins_q31 S1; 
+  arm_biquad_cas_df1_32x64_ins_q31 S2; 
+  arm_biquad_casd_df1_inst_q31 S3; 
+  arm_biquad_casd_df1_inst_q31 S4; 
+  arm_biquad_casd_df1_inst_q31 S5; 
+  int i;
+  int32_t status;
+	 
+  inputF32 = &testInput_f32[0];	 
+  outputF32 = &testOutput[0]; 
+	 
+  /* Initialize the state and coefficient buffers for all Biquad sections */
+
+  arm_biquad_cas_df1_32x64_init_q31(&S1, NUMSTAGES, 
+				    (q31_t *) &coeffTable[190*0 + 10*(gainDB[0] + 9)],
+				    &biquadStateBand1Q31[0], 2);
+
+  arm_biquad_cas_df1_32x64_init_q31(&S2, NUMSTAGES, 
+				    (q31_t *) &coeffTable[190*1 + 10*(gainDB[1] + 9)],
+				    &biquadStateBand2Q31[0], 2);
+	 
+  arm_biquad_cascade_df1_init_q31(&S3, NUMSTAGES, 
+				  (q31_t *) &coeffTable[190*2 + 10*(gainDB[2] + 9)],
+				  &biquadStateBand3Q31[0], 2);
+
+  arm_biquad_cascade_df1_init_q31(&S4, NUMSTAGES, 
+				  (q31_t *) &coeffTable[190*3 + 10*(gainDB[3] + 9)],
+				  &biquadStateBand4Q31[0], 2); 
+	 
+  arm_biquad_cascade_df1_init_q31(&S5, NUMSTAGES, 
+				  (q31_t *) &coeffTable[190*4 + 10*(gainDB[4] + 9)],
+				  &biquadStateBand5Q31[0], 2); 
+	 
+ 
+  /* Call the process functions and needs to change filter coefficients  
+     for varying the gain of each band */ 
+ 
+  for(i=0; i < NUMBLOCKS; i++) 
+    {	 
+
+      /* ---------------------------------------------------------------------- 
+      ** Convert block of input data from float to Q31 
+      ** ------------------------------------------------------------------- */ 
+
+      arm_float_to_q31(inputF32 + (i*BLOCKSIZE), inputQ31, BLOCKSIZE);	   
+	  	 
+      /* ----------------------------------------------------------------------
+      ** Scale down by 1/8.  This provides additional headroom so that the
+      ** graphic EQ can apply gain.
+      ** ------------------------------------------------------------------- */
+
+      arm_scale_q31(inputQ31, 0x7FFFFFFF, -3, inputQ31, BLOCKSIZE);
+
+      /* ----------------------------------------------------------------------
+      ** Call the Q31 Biquad Cascade DF1 32x64 process function for band1, band2
+      ** ------------------------------------------------------------------- */
+
+      arm_biquad_cas_df1_32x64_q31(&S1, inputQ31, outputQ31, BLOCKSIZE); 
+      arm_biquad_cas_df1_32x64_q31(&S2, outputQ31, outputQ31, BLOCKSIZE); 
+
+      /* ---------------------------------------------------------------------- 
+      ** Call the Q31 Biquad Cascade DF1 process function for band3, band4, band5
+      ** ------------------------------------------------------------------- */		   
+
+      arm_biquad_cascade_df1_q31(&S3, outputQ31, outputQ31, BLOCKSIZE); 
+      arm_biquad_cascade_df1_q31(&S4, outputQ31, outputQ31, BLOCKSIZE);	 
+      arm_biquad_cascade_df1_q31(&S5, outputQ31, outputQ31, BLOCKSIZE); 
+ 
+      /* ---------------------------------------------------------------------- 
+      ** Convert Q31 result back to float 
+      ** ------------------------------------------------------------------- */ 
+
+      arm_q31_to_float(outputQ31, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);
+
+      /* ---------------------------------------------------------------------- 
+      ** Scale back up
+      ** ------------------------------------------------------------------- */ 
+
+      arm_scale_f32(outputF32 + (i * BLOCKSIZE), 8.0f, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);
+    }; 
+
+	snr = arm_snr_f32(testRefOutput_f32, testOutput, TESTLENGTH);
+
+	if (snr < SNR_THRESHOLD_F32) 
+	{ 
+	    status = ARM_MATH_TEST_FAILURE; 
+	} 
+	else
+	{
+	    status = ARM_MATH_SUCCESS; 
+	}
+		 
+  /* ---------------------------------------------------------------------- 
+  ** Loop here if the signal does not match the reference output.
+  ** ------------------------------------------------------------------- */ 
+	 
+  if( status != ARM_MATH_SUCCESS) 
+    { 
+      while(1); 
+    } 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+/** \endlink */ 
+ 
+ 
+ 
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM0.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM0.c
new file mode 100644
index 0000000..ece74d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM0.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Cortex-M0 Device System Source File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM3.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM3.c
new file mode 100644
index 0000000..2f5fa0b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM3.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Cortex-M3 Device System Source File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM4.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM4.c
new file mode 100644
index 0000000..beaaf6f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_graphic_equalizer_example/system_ARMCM4.c
@@ -0,0 +1,81 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Cortex-M4 Device System Source File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM4.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvopt
new file mode 100644
index 0000000..082f09c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvopt
@@ -0,0 +1,318 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
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+      
+      
+        1
+        65535
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+        -pCM0
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+        
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+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)
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+      arm_linear_interp_example_f32.c
+    
+    
+      1
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+      arm_linear_interp_data.c
+    
+    
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+      0
+      0
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+      ..\..\Common\Source\math_helper.c
+      math_helper.c
+    
+  
+
+  
+    CMSIS
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+      arm_cortexM0l_math.lib
+    
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+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvproj
new file mode 100644
index 0000000..7d3baf1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM0l_linear_interp_example.uvproj
@@ -0,0 +1,435 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M0
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE
+          
+          
+          
+          4803
+          
+          
+          
+          
+          
+          
+          
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+          arm_cortexM0l_linear_interp_example
+          1
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+            
+            
+            
+            
+            .\arm_linear_interp_example.ini
+          
+          
+            
+            
+            
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+            
+            
+          
+        
+        
+          
+            1
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+          
+          
+          "" ()
+          
+        
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+              
+              ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include
+            
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+          
+            
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+              1
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+            
+            
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+              1
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+            
+            
+              math_helper.c
+              1
+              ..\..\Common\Source\math_helper.c
+            
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+          
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+              2
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+          
+            
+              arm_cortexM0l_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib
+            
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+        
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM3l_linear_interp_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM3l_linear_interp_example.uvopt
new file mode 100644
index 0000000..f5c5cfc
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM3l_linear_interp_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM3l_linear_interp_example.uvproj
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvopt
new file mode 100644
index 0000000..05a822e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvopt
@@ -0,0 +1,318 @@
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### uVision Project, (C) Keil Software

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new file mode 100644
index 0000000..24aef81
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+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_cortexM4lf_linear_interp_example.uvproj
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### uVision Project, (C) Keil Software

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+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            3
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            
+              
+              ARM_MATH_CM4, __FPU_PRESENT = 1
+              
+              ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x00000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Source Group 1
+          
+            
+              arm_linear_interp_example_f32.c
+              1
+              ..\arm_linear_interp_example_f32.c
+            
+            
+              arm_linear_interp_data.c
+              1
+              ..\arm_linear_interp_data.c
+            
+            
+              math_helper.c
+              1
+              ..\..\Common\Source\math_helper.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM4.c
+              1
+              ..\system_ARMCM4.c
+            
+            
+              startup_ARMCM4.s
+              2
+              .\startup_ARMCM4.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+          
+            
+              arm_cortexM4lf_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_linear_interp_example.ini b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_linear_interp_example.ini
new file mode 100644
index 0000000..63e18b0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/arm_linear_interp_example.ini
@@ -0,0 +1,14 @@
+
+/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions 
+   
+   The file can be executed in the following way:
+   1) manually from uVision command window (in debug mode) using command:
+   INCLUIDE arm_linear_interp_example.ini	 
+
+*/
+
+
+// usual initialisation	for target setup
+MAP  0x20000000, 0x20008000  READ WRITE  // allow R/W access to IO space
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..0acd346
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM0.s
@@ -0,0 +1,144 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Cortex-M0 Core Device Startup File
+; *           for CM0 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..5af584b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM3.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Cortex-M3 Core Device Startup File
+; *           for CM3 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..09fdbd6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/ARM/startup_ARMCM4.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM4 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_data.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_data.c
new file mode 100644
index 0000000..464ce85
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_data.c
@@ -0,0 +1,23576 @@
+
+/* ---------------------------------------------------------------------- 
+* Table generated from following MATLAB Command
+* x = -pi: 0.00005 : (2*pi - 0.00005);
+* y = sin(x);
+* where pi value is 3.141592653589793
+* --------------------------------------------------------------------*/
+
+const float arm_linear_interep_table[188495] =  {
+
+
+-0.000000000000000122,	-0.000049999999979173,	-0.000099999999833667,	-0.000149999999437717,	-0.000199999998666767,	-0.000249999997395817,	-0.000299999995500311,	-0.000349999992854362,	
+-0.000399999989333412,	-0.000449999984812462,	-0.000499999979166956,	-0.000549999972271007,	-0.000599999964000057,	-0.000649999954229107,	-0.000699999942833602,	-0.000749999929687653,	
+-0.000799999914666704,	-0.000849999897645755,	-0.000899999878500250,	-0.000949999857104302,	-0.000999999833333354,	-0.001049999807062851,	-0.001099999778166904,	-0.001149999746520957,	
+-0.001199999712000011,	-0.001249999674479510,	-0.001299999633833566,	-0.001349999589937622,	-0.001399999542666680,	-0.001449999491896183,	-0.001499999437500243,	-0.001549999379354304,	
+-0.001599999317333367,	-0.001649999251312876,	-0.001699999181166942,	-0.001749999106771011,	-0.001799999028000082,	-0.001849998944729599,	-0.001899998856833675,	-0.001949998764187754,	
+-0.001999998666666836,	-0.002049998564146365,	-0.002099998456500453,	-0.002149998343604546,	-0.002199998225334087,	-0.002249998101563188,	-0.002299997972167294,	-0.002349997837021405,	
+-0.002399997696000966,	-0.002449997548980088,	-0.002499997395834216,	-0.002549997236438351,	-0.002599997070667937,	-0.002649996898397086,	-0.002699996719501243,	-0.002749996533855408,	
+-0.002799996341335026,	-0.002849996141814208,	-0.002899995935168401,	-0.002949995721272604,	-0.002999995500002261,	-0.003049995271231486,	-0.003099995034835722,	-0.003149994790690415,	
+-0.003199994538669677,	-0.003249994278648952,	-0.003299994010503243,	-0.003349993734107991,	-0.003399993449337312,	-0.003449993156066649,	-0.003499992854171003,	-0.003549992543525819,	
+-0.003599992224005209,	-0.003649991895484619,	-0.003699991557839049,	-0.003749991210943944,	-0.003799990854673418,	-0.003849990488902914,	-0.003899990113507434,	-0.003949989728362423,	
+-0.003999989333341993,	-0.004049988928321590,	-0.004099988513176658,	-0.004149988087781312,	-0.004199987652010995,	-0.004249987205740709,	-0.004299986748845899,	-0.004349986281200678,	
+-0.004399985802680492,	-0.004449985313160341,	-0.004499984812515671,	-0.004549984300620594,	-0.004599983777350557,	-0.004649983242580561,	-0.004699982696186050,	-0.004749982138041138,	
+-0.004799981568021272,	-0.004849980986001451,	-0.004899980391857122,	-0.004949979785462398,	-0.004999979166692725,	-0.005049978535423547,	-0.005099977891528979,	-0.005149977234884466,	
+-0.005199976565365011,	-0.005249975882846058,	-0.005299975187201721,	-0.005349974478307446,	-0.005399973756038235,	-0.005449973020269535,	-0.005499972270875456,	-0.005549971507731448,	
+-0.005599970730712511,	-0.005649969939694091,	-0.005699969134550302,	-0.005749968315156590,	-0.005799967481387958,	-0.005849966633119851,	-0.005899965770226383,	-0.005949964892583000,	
+-0.005999964000064706,	-0.006049963092546945,	-0.006099962169903833,	-0.006149961232010816,	-0.006199960278743339,	-0.006249959309975518,	-0.006299958325582797,	-0.006349957325440182,	
+-0.006399956309423117,	-0.006449955277405718,	-0.006499954229263430,	-0.006549953164871257,	-0.006599952084104644,	-0.006649950986837708,	-0.006699949872945895,	-0.006749948742304206,	
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+};
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_example_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_example_f32.c
new file mode 100644
index 0000000..9f16cda
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/arm_linear_interp_example_f32.c
@@ -0,0 +1,182 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision: 	V1.0.3 
+*  
+* Project: 	    CMSIS DSP Library  
+* Title:	    arm_linear_interp_example_f32.c		  
+*  
+* Description:	Example code demonstrating usage of sin function  
+*               and uses linear interpolation to get higher precision 
+*				 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+/** 
+ * @ingroup groupExamples 
+ */ 
+ 
+/**    
+ * @defgroup LinearInterpExample Linear Interpolate Example    
+ * 
+ *  CMSIS DSP Software Library -- Linear Interpolate Example   
+ *
+ *  Description  
+ * This example demonstrates usage of linear interpolate modules and fast math modules. 
+ * Method 1 uses fast math sine function to calculate sine values using cubic interpolation and method 2 uses 
+ * linear interpolation function and results are compared to reference output. 
+ * Example shows linear interpolation function can be used to get higher precision compared to fast math sin calculation.
+ *
+ * \par Block Diagram:
+ * \par
+ * \image html linearInterpExampleMethod1.gif "Method 1: Sine caluclation using fast math"
+ * \par
+ * \image html linearInterpExampleMethod2.gif "Method 2: Sine caluclation using interpolation function"
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInputSin_f32         points to the input values for sine calculation
+ * \li \c testRefSinOutput32_f32   points to the reference values caculated from sin() matlab function 
+ * \li \c testOutput               points to output buffer calculation from cubic interpolation
+ * \li \c testLinIntOutput         points to output buffer calculation from linear interpolation
+ * \li \c snr1                     Signal to noise ratio for reference and cubic interpolation output
+ * \li \c snr2                     Signal to noise ratio for reference and linear interpolation output
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_sin_f32()
+ * - arm_linear_interp_f32() 
+ * 
+ *  Refer   
+ * \link arm_linear_interp_example_f32.c \endlink
+ * 
+ */ 
+ 
+ 
+/** \example arm_linear_interp_example_f32.c 
+  */  
+     
+#include "arm_math.h" 
+#include "math_helper.h"
+ 
+#define SNR_THRESHOLD 			90 
+#define TEST_LENGTH_SAMPLES 	10 
+#define XSPACING				(0.00005f)
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for F32 SIN function 
+* Generated by the MATLAB rand() function 
+* randn('state', 0)
+* xi = (((1/4.18318581819710)* randn(blockSize, 1) * 2* pi));
+* --------------------------------------------------------------------*/ 
+float32_t testInputSin_f32[TEST_LENGTH_SAMPLES] =  
+{
+	-0.649716504673081170,	-2.501723745497831200,	0.188250329003310100,	0.432092748487532540,	-1.722010988459680800,	1.788766476323060600,	1.786136060975809500,	-0.056525543169408797,	
+	0.491596272728153760,	0.262309671126153390   
+};  
+ 
+/*------------------------------------------------------------------------------ 
+*  Reference out of SIN F32 function for Block Size = 10  
+*  Calculated from sin(testInputSin_f32) 
+*------------------------------------------------------------------------------*/ 
+float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES] =   
+{
+	-0.604960695383043530,	-0.597090287967934840,	0.187140422442966500,	0.418772124875992690,	-0.988588831792106880,	0.976338412038794010,	0.976903856413481100,	-0.056495446835214236,	
+	0.472033731854734240,	0.259311907228582830
+}; 
+ 
+/*------------------------------------------------------------------------------ 
+*  Method 1: Test out Buffer Calculated from Cubic Interpolation 
+*------------------------------------------------------------------------------*/ 
+float32_t testOutput[TEST_LENGTH_SAMPLES]; 
+ 
+/*------------------------------------------------------------------------------ 
+*  Method 2: Test out buffer Calculated from Linear Interpolation 
+*------------------------------------------------------------------------------*/ 
+float32_t testLinIntOutput[TEST_LENGTH_SAMPLES]; 
+
+/*------------------------------------------------------------------------------ 
+*  External table used for linear interpolation 
+*------------------------------------------------------------------------------*/ 
+extern float32_t arm_linear_interep_table[188495];
+ 
+/* ---------------------------------------------------------------------- 
+* Global Variables for caluclating SNR's for Method1 & Method 2 
+* ------------------------------------------------------------------- */ 
+float32_t snr1; 
+float32_t snr2; 
+ 
+/* ---------------------------------------------------------------------------- 
+* Calculation of Sine values from Cubic Interpolation and Linear interpolation 
+* ---------------------------------------------------------------------------- */ 
+int32_t main(void) 
+{ 
+	uint32_t i; 
+	arm_status status; 
+			
+	arm_linear_interp_instance_f32 S = {188495, -3.141592653589793238, XSPACING, &arm_linear_interep_table[0]}; 
+
+	/*------------------------------------------------------------------------------ 
+	*  Method 1: Test out Calculated from Cubic Interpolation 
+	*------------------------------------------------------------------------------*/ 
+	for(i=0; i< TEST_LENGTH_SAMPLES; i++) 
+	{ 
+		testOutput[i] = arm_sin_f32(testInputSin_f32[i]); 
+	} 
+	 
+	/*------------------------------------------------------------------------------ 
+	*  Method 2: Test out Calculated from Cubic Interpolation and Linear interpolation 
+	*------------------------------------------------------------------------------*/
+	
+	for(i=0; i< TEST_LENGTH_SAMPLES; i++) 
+	{ 
+	  	testLinIntOutput[i] = arm_linear_interp_f32(&S, testInputSin_f32[i]);
+	}
+ 
+	/*------------------------------------------------------------------------------ 
+	*  					SNR calculation for method 1 
+	*------------------------------------------------------------------------------*/   
+	snr1 = arm_snr_f32(testRefSinOutput32_f32, testOutput, 2); 
+ 
+	/*------------------------------------------------------------------------------ 
+	*  					SNR calculation for method 2 
+	*------------------------------------------------------------------------------*/   
+	snr2 = arm_snr_f32(testRefSinOutput32_f32, testLinIntOutput, 2); 
+	 
+	/*------------------------------------------------------------------------------ 
+	*  					Initialise status depending on SNR calculations 
+	*------------------------------------------------------------------------------*/  
+	if( snr2 > snr1) 
+	{ 
+		status = ARM_MATH_SUCCESS; 
+	} 
+	else 
+	{ 
+		status = ARM_MATH_TEST_FAILURE; 
+	} 
+	 
+	/* ---------------------------------------------------------------------- 
+	** Loop here if the signals fail the PASS check. 
+	** This denotes a test failure 
+	** ------------------------------------------------------------------- */ 
+	if( status != ARM_MATH_SUCCESS) 
+	{ 
+		while(1); 
+	} 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+ /** \endlink */ 
+ 
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM0.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM0.c
new file mode 100644
index 0000000..ece74d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM0.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Cortex-M0 Device System Source File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM3.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM3.c
new file mode 100644
index 0000000..2f5fa0b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM3.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Cortex-M3 Device System Source File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM4.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM4.c
new file mode 100644
index 0000000..beaaf6f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_linear_interp_example/system_ARMCM4.c
@@ -0,0 +1,81 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Cortex-M4 Device System Source File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM4.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvopt
new file mode 100644
index 0000000..527f80e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvopt
@@ -0,0 +1,304 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
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+        0
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+        SARMCM3.DLL
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+        -pCM0
+        SARMCM3.DLL
+        
+        TARMCM1.DLL
+        -pCM0
+      
+      
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+        1
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+        -1
+        
+        
+        
+        
+        .\arm_matrix_example.ini
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)
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+          0
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+        0
+        0
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+        0
+      
+      
+      
+    
+  
+
+  
+    Source Group 1
+    1
+    0
+    0
+    
+      1
+      2
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+      0
+      0
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+      arm_matrix_example_f32.c
+    
+    
+      1
+      3
+      1
+      0
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+      0
+      0
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+      ..\..\Common\Source\math_helper.c
+      math_helper.c
+    
+  
+
+  
+    CMSIS
+    1
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+      system_ARMCM0.c
+    
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+
+  
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+      arm_cortexM0l_math.lib
+    
+  
+
+  
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+          ..\arm_matrix_example_f32.c
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+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvproj
new file mode 100644
index 0000000..ed3d980
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM0l_matrix_example.uvproj
@@ -0,0 +1,430 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M0
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE
+          
+          
+          
+          4803
+          
+          
+          
+          
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+          
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+          arm_cortexM0l_matrix_example
+          1
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+          
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+          
+          TARMCM1.DLL
+          -pCM0
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+          
+            
+            
+            
+            
+            .\arm_matrix_example.ini
+          
+          
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            1
+            0
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+          
+          
+          "" ()
+          
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+              
+              ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include
+            
+          
+          
+            1
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+          Source Group 1
+          
+            
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+              1
+              ..\arm_matrix_example_f32.c
+            
+            
+              math_helper.c
+              1
+              ..\..\Common\Source\math_helper.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM0.c
+              1
+              ..\system_ARMCM0.c
+            
+            
+              startup_ARMCM0.s
+              2
+              .\startup_ARMCM0.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+          
+            
+              arm_cortexM0l_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM0l_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM3l_matrix_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM3l_matrix_example.uvopt
new file mode 100644
index 0000000..cef203a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_cortexM3l_matrix_example.uvopt
@@ -0,0 +1,304 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
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index 0000000..d7072dc
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new file mode 100644
index 0000000..3fcf3ca
--- /dev/null
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new file mode 100644
index 0000000..52ae6fb
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+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_matrix_example.ini b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_matrix_example.ini
new file mode 100644
index 0000000..6d6cba4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/arm_matrix_example.ini
@@ -0,0 +1,14 @@
+
+/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions 
+   
+   The file can be executed in the following way:
+   1) manually from uVision command window (in debug mode) using command:
+   INCLUIDE arm_matrix_example.ini	 
+
+*/
+
+
+// usual initialisation	for target setup
+MAP  0x20000000, 0x20008000  READ WRITE  // allow R/W access to IO space
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..0acd346
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM0.s
@@ -0,0 +1,144 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Cortex-M0 Core Device Startup File
+; *           for CM0 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..5af584b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM3.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Cortex-M3 Core Device Startup File
+; *           for CM3 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..09fdbd6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/ARM/startup_ARMCM4.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM4 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/arm_matrix_example_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/arm_matrix_example_f32.c
new file mode 100644
index 0000000..9582878
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/arm_matrix_example_f32.c
@@ -0,0 +1,218 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision: 	V1.0.3
+*  
+* Project: 	    CMSIS DSP Library  
+* Title:	    arm_matrix_example_f32.c		  
+*  
+* Description:	Example code demonstrating least square fit to data  
+*				using matrix functions  
+*				 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+/** 
+ * @ingroup groupExamples 
+ */ 
+ 
+/**    
+ * @defgroup MatrixExample Matrix Example    
+ * 
+ * \par Description: 
+ * \par
+ * Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse 
+ * functions to apply least squares fitting to input data. Least squares fitting is 
+ * the procedure for finding the best-fitting curve that minimizes the sum of the 
+ * squares of the offsets (least square error) from a given set of data.
+ *
+ * \par Algorithm:
+ * \par
+ * The linear combination of parameters considered is as follows: 
+ * \par 
+ * A * X = B, where \c X is the unknown value and can be estimated 
+ * from \c A & \c B.
+ * \par
+ * The least squares estimate \c X is given by the following equation:
+ * \par
+ * X = Inverse(AT * A) *  AT * B
+ *
+ * \par Block Diagram:
+ * \par
+ * \image html matrixExample.gif
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c A_f32 input matrix in the linear combination equation
+ * \li \c B_f32 output matrix in the linear combination equation
+ * \li \c X_f32 unknown matrix estimated using \c A_f32 & \c B_f32 matrices
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_mat_init_f32()
+ * - arm_mat_trans_f32()
+ * - arm_mat_mult_f32()
+ * - arm_mat_inverse_f32() 
+ * 
+ *  Refer   
+ * \link arm_matrix_example_f32.c \endlink
+ * 
+ */ 
+ 
+ 
+/** \example arm_matrix_example_f32.c 
+  */  
+     
+#include "arm_math.h" 
+#include "math_helper.h"
+ 
+#define SNR_THRESHOLD 	90 
+ 
+/* -------------------------------------------------------------------------------- 
+* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize  
+* and tapSize 
+* --------------------------------------------------------------------------------- */ 
+ 
+const float32_t B_f32[4] =  
+{    
+	782.0, 7577.0, 470.0, 4505.0 
+}; 
+ 
+/* -------------------------------------------------------------------------------- 
+* Formula to fit is  C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize 
+* -------------------------------------------------------------------------------- */ 
+ 
+const float32_t A_f32[16] =  
+{ 
+	/* Const, 	numTaps, 	blockSize, 	numTaps*blockSize */    
+	1.0, 		32.0, 		4.0, 		128.0,  
+	1.0, 		32.0, 		64.0, 		2048.0, 
+	1.0, 		16.0, 		4.0, 		64.0, 
+	1.0, 		16.0, 		64.0, 		1024.0, 
+};  
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Temporary buffers  for storing intermediate values 
+* ------------------------------------------------------------------- */ 
+/* Transpose of A Buffer */ 
+float32_t AT_f32[16]; 
+/* (Transpose of A * A) Buffer */ 
+float32_t ATMA_f32[16]; 
+/* Inverse(Transpose of A * A)  Buffer */ 
+float32_t ATMAI_f32[16]; 
+/* Test Output Buffer */ 
+float32_t X_f32[4]; 
+ 
+/* ---------------------------------------------------------------------- 
+* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB  
+* ------------------------------------------------------------------- */ 
+const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875}; 
+ 
+float32_t snr; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Max magnitude FFT Bin test 
+* ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+ 
+	arm_matrix_instance_f32 A;		/* Matrix A Instance */ 
+	arm_matrix_instance_f32 AT;		/* Matrix AT(A transpose) instance */ 
+	arm_matrix_instance_f32 ATMA;	/* Matrix ATMA( AT multiply with A) instance */ 
+	arm_matrix_instance_f32 ATMAI;	/* Matrix ATMAI(Inverse of ATMA) instance */ 
+	arm_matrix_instance_f32 B;		/* Matrix B instance */ 
+	arm_matrix_instance_f32 X;		/* Matrix X(Unknown Matrix) instance */ 
+ 
+	uint32_t srcRows, srcColumns;	/* Temporary variables */
+	arm_status status; 
+ 
+	/* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */ 
+	srcRows = 4; 
+    srcColumns = 4; 
+	arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32); 
+ 
+	/* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */ 
+	srcRows = 4; 
+    srcColumns = 4; 
+	arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32); 
+ 
+	/* calculation of A transpose */ 
+	status = arm_mat_trans_f32(&A, &AT); 
+	 
+ 
+	/* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */ 
+	srcRows = 4; 
+    srcColumns = 4; 
+	arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32); 
+ 
+	/* calculation of AT Multiply with A */ 
+	status = arm_mat_mult_f32(&AT, &A, &ATMA); 
+ 
+	/* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */ 
+	srcRows = 4; 
+    srcColumns = 4; 
+	arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32); 
+ 
+	/* calculation of Inverse((Transpose(A) * A) */ 
+	status = arm_mat_inverse_f32(&ATMA, &ATMAI); 
+ 
+	/* calculation of (Inverse((Transpose(A) * A)) *  Transpose(A)) */ 
+	status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA); 
+ 
+	/* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */ 
+	srcRows = 4; 
+    srcColumns = 1; 
+	arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32);  
+ 
+	/* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */ 
+	srcRows = 4; 
+    srcColumns = 1; 
+	arm_mat_init_f32(&X, srcRows, srcColumns, X_f32); 
+ 
+	/* calculation ((Inverse((Transpose(A) * A)) *  Transpose(A)) * B) */ 
+	status = arm_mat_mult_f32(&ATMA, &B, &X); 
+	 
+	/* Comparison of reference with test output */	   
+	snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4); 
+ 
+	/*------------------------------------------------------------------------------ 
+	*  					Initialise status depending on SNR calculations 
+	*------------------------------------------------------------------------------*/  
+	if( snr > SNR_THRESHOLD) 
+	{ 
+		status = ARM_MATH_SUCCESS; 
+	} 
+	else 
+	{ 
+		status = ARM_MATH_TEST_FAILURE; 
+	} 
+ 
+	 
+	/* ---------------------------------------------------------------------- 
+	** Loop here if the signals fail the PASS check. 
+	** This denotes a test failure 
+	** ------------------------------------------------------------------- */	 
+	if( status != ARM_MATH_SUCCESS) 
+	{ 
+	  while(1); 
+	} 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+ /** \endlink */ 
+ 
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM0.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM0.c
new file mode 100644
index 0000000..ece74d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM0.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Cortex-M0 Device System Source File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM3.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM3.c
new file mode 100644
index 0000000..2f5fa0b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM3.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Cortex-M3 Device System Source File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM4.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM4.c
new file mode 100644
index 0000000..beaaf6f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_matrix_example/system_ARMCM4.c
@@ -0,0 +1,81 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Cortex-M4 Device System Source File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM4.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvopt
new file mode 100644
index 0000000..bee0dbd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvopt
@@ -0,0 +1,318 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
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+        SARMCM3.DLL
+        
+        DARMCM1.DLL
+        -pCM0
+        SARMCM3.DLL
+        
+        TARMCM1.DLL
+        -pCM0
+      
+      
+        1
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+        
+        
+        
+        
+        .\arm_cortexM0l_biquad_cascade_df1_coverage.ini
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
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+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)
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+          
420

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+
+  
+    Source Group 1
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+      arm_signal_converge_example_f32.c
+    
+    
+      1
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+      0
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+    
+    
+      1
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+      0
+      0
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+      ..\..\Common\Source\math_helper.c
+      math_helper.c
+    
+  
+
+  
+    CMSIS
+    1
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+      arm_cortexM0l_math.lib
+    
+  
+
+  
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+      100
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+          ..\arm_signal_converge_example_f32.c
+          0
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+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvproj
new file mode 100644
index 0000000..0fc9af2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM0l_signal_converge_example.uvproj
@@ -0,0 +1,435 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M0
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE
+          
+          
+          
+          4803
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
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+          arm_cortexM0l_signal_converge_example
+          1
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+          
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+          -pCM0
+          SARMCM3.DLL
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+          TARMCM1.DLL
+          -pCM0
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+            .\arm_cortexM0l_biquad_cascade_df1_coverage.ini
+          
+          
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+            
+            
+            
+            
+            
+          
+        
+        
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+          
+          "" ()
+          
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+              
+              ..\..\..\..\Include;..\..\Common\Include;..\..\..\..\..\Device\ARM\ARMCM0\Include
+            
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+          Source Group 1
+          
+            
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+              1
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+            
+            
+              arm_signal_converge_data.c
+              1
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+            
+            
+              math_helper.c
+              1
+              ..\..\Common\Source\math_helper.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
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+              1
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+              startup_ARMCM0.s
+              2
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+          
+            
+              arm_cortexM0l_math.lib
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+            
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+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM3l_signal_converge_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM3l_signal_converge_example.uvopt
new file mode 100644
index 0000000..8ac491b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM3l_signal_converge_example.uvopt
@@ -0,0 +1,318 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
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+      
+      
+        1
+        65535
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new file mode 100644
index 0000000..0d35a26
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_cortexM3l_signal_converge_example.uvproj
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index 0000000..c951310
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index 0000000..103c61c
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+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_signal_converge_example.ini b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_signal_converge_example.ini
new file mode 100644
index 0000000..d48a8f2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/arm_signal_converge_example.ini
@@ -0,0 +1,14 @@
+
+/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions 
+   
+   The file can be executed in the following way:
+   1) manually from uVision command window (in debug mode) using command:
+   INCLUIDE arm_signal_converge_example.ini	 
+
+*/
+
+
+// usual initialisation	for target setup
+MAP  0x20000000, 0x20008000  READ WRITE  // allow R/W access to IO space
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..0acd346
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM0.s
@@ -0,0 +1,144 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Cortex-M0 Core Device Startup File
+; *           for CM0 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..5af584b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM3.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Cortex-M3 Core Device Startup File
+; *           for CM3 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..09fdbd6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/ARM/startup_ARMCM4.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM4 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_data.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_data.c
new file mode 100644
index 0000000..be64907
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_data.c
@@ -0,0 +1,229 @@
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+** Test input data for Floating point LMS Norm FIR filter
+** Generated by the MATLAB randn() function
+** ------------------------------------------------------------------- */
+
+float32_t testInput_f32[1536] = 
+{   
+-0.432565,	-1.665584,	0.125332,	0.287676,	-1.146471,	1.190915,	1.189164,	-0.037633,	
+0.327292,	0.174639,	-0.186709,	0.725791,	-0.588317,	2.183186,	-0.136396,	0.113931,	
+1.066768,	0.059281,	-0.095648,	-0.832349,	0.294411,	-1.336182,	0.714325,	1.623562,	
+-0.691776,	0.857997,	1.254001,	-1.593730,	-1.440964,	0.571148,	-0.399886,	0.689997,	
+0.815622,	0.711908,	1.290250,	0.668601,	1.190838,	-1.202457,	-0.019790,	-0.156717,	
+-1.604086,	0.257304,	-1.056473,	1.415141,	-0.805090,	0.528743,	0.219321,	-0.921902,	
+-2.170674,	-0.059188,	-1.010634,	0.614463,	0.507741,	1.692430,	0.591283,	-0.643595,	
+0.380337,	-1.009116,	-0.019511,	-0.048221,	0.000043,	-0.317859,	1.095004,	-1.873990,	
+0.428183,	0.895638,	0.730957,	0.577857,	0.040314,	0.677089,	0.568900,	-0.255645,	
+-0.377469,	-0.295887,	-1.475135,	-0.234004,	0.118445,	0.314809,	1.443508,	-0.350975,	
+0.623234,	0.799049,	0.940890,	-0.992092,	0.212035,	0.237882,	-1.007763,	-0.742045,	
+1.082295,	-0.131500,	0.389880,	0.087987,	-0.635465,	-0.559573,	0.443653,	-0.949904,	
+0.781182,	0.568961,	-0.821714,	-0.265607,	-1.187777,	-2.202321,	0.986337,	-0.518635,	
+0.327368,	0.234057,	0.021466,	-1.003944,	-0.947146,	-0.374429,	-1.185886,	-1.055903,	
+1.472480,	0.055744,	-1.217317,	-0.041227,	-1.128344,	-1.349278,	-0.261102,	0.953465,	
+0.128644,	0.656468,	-1.167819,	-0.460605,	-0.262440,	-1.213152,	-1.319437,	0.931218,	
+0.011245,	-0.645146,	0.805729,	0.231626,	-0.989760,	1.339586,	0.289502,	1.478917,	
+1.138028,	-0.684139,	-1.291936,	-0.072926,	-0.330599,	-0.843628,	0.497770,	1.488490,	
+-0.546476,	-0.846758,	-0.246337,	0.663024,	-0.854197,	-1.201315,	-0.119869,	-0.065294,	
+0.485296,	-0.595491,	-0.149668,	-0.434752,	-0.079330,	1.535152,	-0.606483,	-1.347363,	
+0.469383,	-0.903567,	0.035880,	-0.627531,	0.535398,	0.552884,	-0.203690,	-2.054325,	
+0.132561,	1.592941,	1.018412,	-1.580402,	-0.078662,	-0.681657,	-1.024553,	-1.234353,	
+0.288807,	-0.429303,	0.055801,	-0.367874,	-0.464973,	0.370961,	0.728283,	2.112160,	
+-1.357298,	-1.022610,	1.037834,	-0.389800,	-1.381266,	0.315543,	1.553243,	0.707894,	
+1.957385,	0.504542,	1.864529,	-0.339812,	-1.139779,	-0.211123,	1.190245,	-1.116209,	
+0.635274,	-0.601412,	0.551185,	-1.099840,	0.085991,	-2.004563,	-0.493088,	0.462048,	
+-0.321005,	1.236556,	-0.631280,	-2.325211,	-1.231637,	1.055648,	-0.113224,	0.379224,	
+0.944200,	-2.120427,	-0.644679,	-0.704302,	-1.018137,	-0.182082,	1.521013,	-0.038439,	
+1.227448,	-0.696205,	0.007524,	-0.782893,	0.586939,	-0.251207,	0.480136,	0.668155,	
+-0.078321,	0.889173,	2.309287,	0.524639,	-0.011787,	0.913141,	0.055941,	-1.107070,	
+0.485498,	-0.005005,	-0.276218,	1.276452,	1.863401,	-0.522559,	0.103424,	-0.807649,	
+0.680439,	-2.364590,	0.990115,	0.218899,	0.261662,	1.213444,	-0.274667,	-0.133134,	
+-1.270500,	-1.663606,	-0.703554,	0.280880,	-0.541209,	-1.333531,	1.072686,	-0.712085,	
+-0.011286,	-0.000817,	-0.249436,	0.396575,	-0.264013,	-1.664011,	-1.028975,	0.243095,	
+-1.256590,	-0.347183,	-0.941372,	-1.174560,	-1.021142,	-0.401667,	0.173666,	-0.116118,	
+1.064119,	-0.245386,	-1.517539,	0.009734,	0.071373,	0.316536,	0.499826,	1.278084,	
+-0.547816,	0.260808,	-0.013177,	-0.580264,	2.136308,	-0.257617,	-1.409528,	1.770101,	
+0.325546,	-1.119040,	0.620350,	1.269782,	-0.896043,	0.135175,	-0.139040,	-1.163395,	
+1.183720,	-0.015430,	0.536219,	-0.716429,	-0.655559,	0.314363,	0.106814,	1.848216,	
+-0.275106,	2.212554,	1.508526,	-1.945079,	-1.680543,	-0.573534,	-0.185817,	0.008934,	
+0.836950,	-0.722271,	-0.721490,	-0.201181,	-0.020464,	0.278890,	1.058295,	0.621673,	
+-1.750615,	0.697348,	0.811486,	0.636345,	1.310080,	0.327098,	-0.672993,	-0.149327,	
+-2.449018,	0.473286,	0.116946,	-0.591104,	-0.654708,	-1.080662,	-0.047731,	0.379345,	
+-0.330361,	-0.499898,	-0.035979,	-0.174760,	-0.957265,	1.292548,	0.440910,	1.280941,	
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+-0.403325,	0.084076,	-0.435349,	-0.562623,	0.878062,	-0.814650,	-0.258363,	0.493299,	
+-0.802694,	-0.008329,	0.627571,	0.154382,	2.580735,	-1.306246,	1.023526,	0.777795,	
+-0.833884,	-0.586663,	0.065664,	-0.012342,	-0.076987,	-1.558587,	1.702607,	-0.468984,	
+0.094619,	0.287071,	0.919354,	0.510136,	0.245440,	-1.400519,	0.969571,	1.593698,	
+-1.437917,	-1.534230,	-0.074710,	0.081459,	-0.843240,	-0.564640,	-0.028207,	-1.243702,	
+0.733039,	0.059580,	0.149144,	1.595857,	-0.777250,	1.550277,	1.055002,	-0.166654,	
+0.314484,	1.419571,	0.327348,	0.475653,	0.398754,	-0.072770,	1.314784,	0.978279,	
+1.722114,	-0.412302,	0.565133,	0.739851,	0.220138,	1.312807,	0.629152,	-1.107987,	
+-0.447001,	-0.725993,	0.354045,	-0.506772,	-2.103747,	-0.664684,	1.450110,	-0.329805,	
+2.701872,	-1.634939,	-0.536325,	0.547223,	1.492603,	-0.455243,	-0.496416,	1.235260,	
+0.040926,	0.748467,	1.230764,	0.304903,	1.077771,	0.765151,	-1.319580,	-0.509191,	
+0.555116,	-1.957625,	-0.760453,	-2.443886,	-0.659366,	-0.114779,	0.300079,	-0.583996,	
+-3.073745,	1.551042,	-0.407369,	1.428095,	-1.353242,	0.903970,	0.541671,	-0.465020
+};
+
+
+
+/* ----------------------------------------------------------------------
+** Coefficients for 32-tap filter for Floating point LMS FIR filter
+*  FIR high pass filter with cutoff freq 9.6kHz (transition 9.6KHz to 11.52KHz) 
+** ------------------------------------------------------------------- */  
+float32_t lmsNormCoeff_f32[32] = {
+-0.004240,	0.002301,	0.008860,	-0.000000,	-0.019782,	-0.010543,	0.032881,	0.034736,	
+-0.037374,	-0.069586,	0.022397,	0.102169,	0.014185,	-0.115908,	-0.061648,	0.101018,	
+0.101018,	-0.061648,	-0.115908,	0.014185,	0.102169,	0.022397,	-0.069586,	-0.037374,	
+0.034736,	0.032881,	-0.010543,	-0.019782,	-0.000000,	0.008860,	0.002301,	-0.004240	
+
+};
+
+/* ----------------------------------------------------------------------
+** Coefficients for 32-tap filter for Floating point FIR filter
+*  FIR low pass filter with cutoff freq 24Hz (transition 24Hz to 240Hz) 
+** ------------------------------------------------------------------- */  
+const float32_t FIRCoeff_f32[32] = {
+0.004502,	0.005074,	0.006707,	0.009356,	0.012933,	0.017303,	0.022298,	0.027717,	
+0.033338,	0.038930,	0.044258,	0.049098,	0.053243,	0.056519,	0.058784,	0.059941,	
+0.059941,	0.058784,	0.056519,	0.053243,	0.049098,	0.044258,	0.038930,	0.033338,	
+0.027717,	0.022298,	0.017303,	0.012933,	0.009356,	0.006707,	0.005074,	0.004502
+
+};
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_example_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_example_f32.c
new file mode 100644
index 0000000..df08ecf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/arm_signal_converge_example_f32.c
@@ -0,0 +1,246 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision: 	V1.0.3
+*  
+* Project: 	    CMSIS DSP Library  
+* Title:	    arm_signal_converge_example_f32.c		  
+*  
+* Description:	Example code demonstrating convergence of an adaptive 
+*               filter. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+/** 
+ * @ingroup groupExamples 
+ */ 
+ 
+/**    
+ * @defgroup SignalConvergence Signal Convergence Example    
+ * 
+ * \par Description: 
+ * \par
+ * Demonstrates the ability of an adaptive filter to "learn" the transfer function of 
+ * a FIR lowpass filter using the Normalized LMS Filter, Finite Impulse 
+ * Response (FIR) Filter, and Basic Math Functions.
+ * 
+ * \par Algorithm:
+ * \par
+ * The figure below illustrates the signal flow in this example. Uniformly distributed white 
+ * noise is passed through an FIR lowpass filter. The output of the FIR filter serves as the 
+ * reference input of the adaptive filter (normalized LMS filter). The white noise is input 
+ * to the adaptive filter. The adaptive filter learns the transfer function of the FIR filter.
+ * The filter outputs two signals: (1) the output of the internal adaptive FIR filter, and 
+ * (2) the error signal which is the difference between the adaptive filter and the reference 
+ * output of the FIR filter. Over time as the adaptive filter learns the transfer function 
+ * of the FIR filter, the first output approaches the reference output of the FIR filter,
+ * and the error signal approaches zero. 
+ * \par
+ * The adaptive filter converges properly even if the input signal has a large dynamic 
+ * range (i.e., varies from small to large values). The coefficients of the adaptive filter 
+ * are initially zero, and then converge over 1536 samples. The internal function test_signal_converge() 
+ * implements the stopping condition. The function checks if all of the values of the error signal have a 
+ * magnitude below a threshold DELTA. 
+ * 
+ * \par Block Diagram:
+ * \par
+ * \image html SignalFlow.gif 
+ *
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInput_f32 points to the input data
+ * \li \c firStateF32 points to FIR state buffer
+ * \li \c lmsStateF32 points to Normalised Least mean square FIR filter state buffer
+ * \li \c FIRCoeff_f32 points to coefficient buffer
+ * \li \c lmsNormCoeff_f32 points to Normalised Least mean square FIR filter coefficient buffer
+ * \li \c wire1, wir2, wire3 temporary buffers
+ * \li \c errOutput, err_signal temporary error buffers 
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_lms_norm_init_f32()
+ * - arm_fir_init_f32()
+ * - arm_fir_f32()
+ * - arm_lms_norm_f32()
+ * - arm_scale_f32()
+ * - arm_abs_f32()
+ * - arm_sub_f32()
+ * - arm_min_f32()
+ * - arm_copy_f32()
+ *
+ *  Refer   
+ * \link arm_signal_converge_example_f32.c \endlink
+ * 
+ */  
+ 
+ 
+/** \example arm_signal_converge_example_f32.c 
+  */  
+     
+#include "arm_math.h" 
+#include "math_helper.h"
+ 
+/* ---------------------------------------------------------------------- 
+** Global defines for the simulation 
+* ------------------------------------------------------------------- */ 
+ 
+#define TEST_LENGTH_SAMPLES 1536 
+#define NUMTAPS 			32 
+#define BLOCKSIZE 			32 
+#define DELTA_ERROR         0.000001f 
+#define DELTA_COEFF         0.0001f 
+#define MU 					0.5f 
+ 
+#define NUMFRAMES (TEST_LENGTH_SAMPLES / BLOCKSIZE) 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare FIR state buffers and structure  
+* ------------------------------------------------------------------- */ 
+  
+float32_t firStateF32[NUMTAPS + BLOCKSIZE];  
+arm_fir_instance_f32 LPF_instance; 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare LMSNorm state buffers and structure  
+* ------------------------------------------------------------------- */ 
+  
+float32_t lmsStateF32[NUMTAPS + BLOCKSIZE];  
+float32_t errOutput[TEST_LENGTH_SAMPLES]; 
+arm_lms_norm_instance_f32 lmsNorm_instance; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Function Declarations for Signal Convergence Example  
+* ------------------------------------------------------------------- */ 
+ 
+arm_status test_signal_converge_example( void ); 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Internal functions 
+* ------------------------------------------------------------------- */ 
+arm_status test_signal_converge(float32_t* err_signal, 
+			       			     uint32_t blockSize); 
+ 
+void getinput(float32_t* input, 
+		 uint32_t fr_cnt,  
+   	     uint32_t blockSize);  
+ 
+/* ---------------------------------------------------------------------- 
+* External Declarations for FIR F32 module Test 
+* ------------------------------------------------------------------- */ 
+extern float32_t testInput_f32[TEST_LENGTH_SAMPLES]; 
+extern float32_t lmsNormCoeff_f32[32]; 
+extern const float32_t FIRCoeff_f32[32]; 
+extern arm_lms_norm_instance_f32 lmsNorm_instance; 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare I/O buffers  
+* ------------------------------------------------------------------- */ 
+ 
+float32_t wire1[BLOCKSIZE]; 
+float32_t wire2[BLOCKSIZE]; 
+float32_t wire3[BLOCKSIZE]; 
+float32_t err_signal[BLOCKSIZE]; 
+ 
+/* ---------------------------------------------------------------------- 
+* Signal converge test 
+* ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+  uint32_t i; 
+  arm_status status; 
+  uint32_t index; 
+  float32_t minValue; 
+ 
+  /* Initialize the LMSNorm data structure */ 
+  arm_lms_norm_init_f32(&lmsNorm_instance, NUMTAPS, lmsNormCoeff_f32, lmsStateF32, MU, BLOCKSIZE); 
+ 
+  /* Initialize the FIR data structure */ 
+  arm_fir_init_f32(&LPF_instance, NUMTAPS, (float32_t *)FIRCoeff_f32, firStateF32, BLOCKSIZE); 
+ 
+  /* ---------------------------------------------------------------------- 
+  * Loop over the frames of data and execute each of the processing 
+  * functions in the system. 
+  * ------------------------------------------------------------------- */ 
+ 
+  for(i=0; i < NUMFRAMES; i++)  
+    { 
+      /* Read the input data - uniformly distributed random noise - into wire1 */  
+      arm_copy_f32(testInput_f32 + (i * BLOCKSIZE), wire1, BLOCKSIZE); 
+ 
+      /* Execute the FIR processing function.  Input wire1 and output wire2 */  
+      arm_fir_f32(&LPF_instance, wire1, wire2, BLOCKSIZE); 
+       
+      /* Execute the LMS Norm processing function*/  
+ 
+      arm_lms_norm_f32(&lmsNorm_instance, /* LMSNorm instance */ 
+		       wire1,                     /* Input signal */  
+		       wire2,			          /* Reference Signal */ 
+		       wire3, 			          /* Converged Signal */ 
+		       err_signal, 		          /* Error Signal, this will become small as the signal converges */ 
+		       BLOCKSIZE);		          /* BlockSize */ 
+ 
+      /* apply overall gain */  
+      arm_scale_f32(wire3, 5, wire3, BLOCKSIZE);	 /* in-place buffer */  
+    } 
+ 
+  status = ARM_MATH_SUCCESS; 
+ 
+  /* ------------------------------------------------------------------------------- 
+  * Test whether the error signal has reached towards 0. 
+  * ----------------------------------------------------------------------------- */ 
+ 
+  arm_abs_f32(err_signal, err_signal, BLOCKSIZE); 
+  arm_min_f32(err_signal, BLOCKSIZE, &minValue, &index); 
+ 
+  if (minValue > DELTA_ERROR) 
+  { 
+      status = ARM_MATH_TEST_FAILURE; 
+  } 
+ 
+  /* ---------------------------------------------------------------------- 
+  * Test whether the filter coefficients have converged. 
+  * ------------------------------------------------------------------- */ 
+ 
+  arm_sub_f32((float32_t *)FIRCoeff_f32, lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); 
+ 
+  arm_abs_f32(lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); 
+  arm_min_f32(lmsNormCoeff_f32, NUMTAPS, &minValue, &index); 
+ 
+  if (minValue > DELTA_COEFF) 
+  { 
+      status = ARM_MATH_TEST_FAILURE; 
+  } 
+ 
+  /* ---------------------------------------------------------------------- 
+  * Loop here if the signals did not pass the convergence check. 
+  * This denotes a test failure 
+  * ------------------------------------------------------------------- */ 
+ 
+  if( status != ARM_MATH_SUCCESS) 
+  { 
+      while(1); 
+  } 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+ /** \endlink */ 
+		 
+ 
+		 
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM0.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM0.c
new file mode 100644
index 0000000..ece74d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM0.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Cortex-M0 Device System Source File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM3.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM3.c
new file mode 100644
index 0000000..2f5fa0b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM3.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Cortex-M3 Device System Source File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM4.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM4.c
new file mode 100644
index 0000000..beaaf6f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_signal_converge_example/system_ARMCM4.c
@@ -0,0 +1,81 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Cortex-M4 Device System Source File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM4.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvopt
new file mode 100644
index 0000000..cf1481b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvopt
@@ -0,0 +1,290 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\debug\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      0
+      
+        SARMCM3.DLL
+        
+        DARMCM1.DLL
+        -pCM0
+        SARMCM3.DLL
+        
+        TARMCM1.DLL
+        -pCM0
+      
+      
+        1
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        1
+        1
+        0
+        1
+        0
+        0
+        -1
+        
+        
+        
+        
+        .\arm_sin_cos_example.ini
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvproj
new file mode 100644
index 0000000..36d5788
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM0l_sin_cos_example.uvproj
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### uVision Project, (C) Keil Software

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvopt
new file mode 100644
index 0000000..94565c8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvopt
@@ -0,0 +1,290 @@
+
+
+
+  1.0
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+  
### uVision Project, (C) Keil Software

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvproj
new file mode 100644
index 0000000..f950fda
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM3l_sin_cos_example.uvproj
@@ -0,0 +1,425 @@
+
+
+
+  1.1
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+  
### uVision Project, (C) Keil Software

+
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+      Target 1
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvopt
new file mode 100644
index 0000000..06373a0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvopt
@@ -0,0 +1,290 @@
+
+
+
+  1.0
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+  
### uVision Project, (C) Keil Software

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+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      255
+      
+        SARMCM3.DLL
+        
+        DCM.DLL
+        -pCM4
+        SARMCM3.DLL
+        
+        TCM.DLL
+        -pCM4
+      
+      
+        1
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        1
+        1
+        0
+        1
+        0
+        0
+        -1
+        
+        
+        
+        
+        .\arm_sin_cos_example.ini
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          -T0
+        
+      
+      
+        
+          0
+          0
+          137
+          1
+          
368

+          0
+          0
+          0
+          0
+          1
+          
+          
+          \\arm_cortexM4lf_sin_cos_example\../arm_sin_cos_example_f32.c\137
+        
+        
+          1
+          0
+          142
+          1
+          
366

+          0
+          0
+          0
+          0
+          1
+          
+          
+          \\arm_cortexM4lf_sin_cos_example\../arm_sin_cos_example_f32.c\142
+        
+      
+      
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+    
+  
+
+  
+    Source Group 1
+    1
+    0
+    0
+    
+      1
+      1
+      1
+      0
+      0
+      0
+      0
+      1
+      1
+      0
+      ..\arm_sin_cos_example_f32.c
+      arm_sin_cos_example_f32.c
+    
+  
+
+  
+    CMSIS DeviceSupport
+    1
+    0
+    0
+    
+      2
+      2
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\system_ARMCM4.c
+      system_ARMCM4.c
+    
+    
+      2
+      3
+      2
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      .\startup_ARMCM4.s
+      startup_ARMCM4.s
+    
+  
+
+  
+    CMSIS SW_DSP_Library
+    1
+    0
+    0
+    
+      3
+      4
+      4
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib
+      arm_cortexM4lf_math.lib
+    
+  
+
+  
+    1
+    0
+    
+      100
+      0
+      
+        
+          ..\arm_sin_cos_example_f32.c
+          0
+          1
+          1
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvproj
new file mode 100644
index 0000000..9677178
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_cortexM4lf_sin_cos_example.uvproj
@@ -0,0 +1,425 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M4 FPU
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2
+          
+          
+          
+          5237
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\debug\
+          arm_cortexM4lf_sin_cos_example
+          1
+          0
+          0
+          1
+          1
+          .\debug\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            0
+            0
+            0
+            1
+            1
+            1
+            0
+            1
+          
+          0
+          -1
+          
+            
+            
+            
+            
+            .\arm_sin_cos_example.ini
+          
+          
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            0
+            -1
+          
+          
+          
+          
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            1
+            0
+            0
+            5
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            3
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            
+              
+              ARM_MATH_CM4, __FPU_PRESENT = 1
+              
+              ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x00000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Source Group 1
+          
+            
+              arm_sin_cos_example_f32.c
+              1
+              ..\arm_sin_cos_example_f32.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM4.c
+              1
+              ..\system_ARMCM4.c
+            
+            
+              startup_ARMCM4.s
+              2
+              .\startup_ARMCM4.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+          
+            
+              arm_cortexM4lf_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_sin_cos_example.ini b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_sin_cos_example.ini
new file mode 100644
index 0000000..813fb16
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/arm_sin_cos_example.ini
@@ -0,0 +1,14 @@
+
+/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions 
+   
+   The file can be executed in the following way:
+   1) manually from uVision command window (in debug mode) using command:
+   INCLUIDE arm_sin_cos_example.ini	 
+
+*/
+
+
+// usual initialisation	for target setup
+MAP  0x20000000, 0x20008000  READ WRITE  // allow R/W access to IO space
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..0acd346
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM0.s
@@ -0,0 +1,144 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Cortex-M0 Core Device Startup File
+; *           for CM0 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..5af584b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM3.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Cortex-M3 Core Device Startup File
+; *           for CM3 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..09fdbd6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/ARM/startup_ARMCM4.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM4 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/arm_sin_cos_example_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/arm_sin_cos_example_f32.c
new file mode 100644
index 0000000..5cb6672
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/arm_sin_cos_example_f32.c
@@ -0,0 +1,146 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision: 	V1.0.3
+*  
+* Project: 	    CMSIS DSP Library  
+* Title:	    arm_sin_cos_example_f32.c		  
+*  
+* Description:	Example code demonstrating sin and cos calculation of input signal. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+/** 
+ * @ingroup groupExamples 
+ */ 
+ 
+/**    
+ * @defgroup SinCosExample SineCosine Example    
+ * 
+ * \par Description:
+ * \par
+ * Demonstrates the Pythagorean trignometric identity with the use of Cosine, Sine, Vector
+ * Multiplication, and Vector Addition functions.
+ *
+ * \par Algorithm:
+ * \par
+ * Mathematically, the Pythagorean trignometric identity is defined by the following equation:
+ *  
sin(x) * sin(x) + cos(x) * cos(x) = 1
 
+ * where \c x is the angle in radians. 
+ *
+ * \par Block Diagram:
+ * \par
+ * \image html sinCos.gif 
+ * 
+ * \par Variables Description:
+ * \par
+ * \li \c testInput_f32 array of input angle in radians
+ * \li \c testOutput stores sum of the squares of sine and cosine values of input angle
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_cos_f32()
+ * - arm_sin_f32()
+ * - arm_mult_f32()
+ * - arm_add_f32()
+ * 
+ *  Refer   
+ * \link arm_sin_cos_example_f32.c \endlink
+ * 
+ */ 
+ 
+ 
+/** \example arm_sin_cos_example_f32.c 
+  */  
+ 
+#include      
+#include "arm_math.h"
+ 
+/* ---------------------------------------------------------------------- 
+* Defines each of the tests performed 
+* ------------------------------------------------------------------- */ 
+#define MAX_BLOCKSIZE	32 
+#define DELTA           (0.000001f) 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for Floating point sin_cos example for 32-blockSize 
+* Generated by the MATLAB randn() function 
+* ------------------------------------------------------------------- */ 
+ 
+const float32_t testInput_f32[MAX_BLOCKSIZE] =  
+{    
+	-1.244916875853235400,	-4.793533929171324800,	0.360705030233248850,	0.827929644170887320,	-3.299532218312426900,	3.427441903227623800,	3.422401784294607700,	-0.108308165334010680,	 
+	0.941943896490312180,	0.502609575000365850,	-0.537345278736373500,	2.088817392965764500,	-1.693168684143455700,	6.283185307179590700,	-0.392545884746175080,	0.327893095115825040,	 
+	3.070147440456292300,	0.170611405884662230,	-0.275275082396073010,	-2.395492805446796300,	0.847311163536506600,	-3.845517018083148800,	2.055818378415868300,	4.672594161978930800,	 
+	-1.990923030266425800,	2.469305197656249500,	3.609002606064021000,	-4.586736582331667500,	-4.147080139136136300,	1.643756718868359500,	-1.150866392366494800,	1.985805026477433800 
+ 
+ 
+};  
+ 
+const float32_t testRefOutput_f32 = 1.000000000; 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare Global variables  
+* ------------------------------------------------------------------- */ 
+uint32_t blockSize = 32; 
+float32_t  testOutput;  
+float32_t  cosOutput;  
+float32_t  sinOutput;  
+float32_t  cosSquareOutput;  
+float32_t  sinSquareOutput; 
+ 
+/* ---------------------------------------------------------------------- 
+* Max magnitude FFT Bin test 
+* ------------------------------------------------------------------- */ 
+
+arm_status status; 
+ 
+int32_t main(void) 
+{ 
+	float32_t diff; 
+	uint32_t i; 
+ 
+	for(i=0; i< blockSize; i++) 
+    { 
+        cosOutput = arm_cos_f32(testInput_f32[i]); 
+		sinOutput = arm_sin_f32(testInput_f32[i]); 
+ 
+		arm_mult_f32(&cosOutput, &cosOutput, &cosSquareOutput, 1); 
+		arm_mult_f32(&sinOutput, &sinOutput, &sinSquareOutput, 1); 
+ 
+		arm_add_f32(&cosSquareOutput, &sinSquareOutput, &testOutput, 1);
+ 
+		/* absolute value of difference between ref and test */ 
+	    diff = fabsf(testRefOutput_f32 - testOutput); 
+	 
+	    /* Comparison of sin_cos value with reference */ 
+	    if(diff > DELTA) 
+	    { 
+		   status = ARM_MATH_TEST_FAILURE; 
+	    } 
+		 
+	    if( status == ARM_MATH_TEST_FAILURE) 
+	    { 
+	       while(1); 
+	    } 
+ 
+    } 
+
+    while(1);                             /* main function does not return */
+} 
+ 
+ /** \endlink */ 
+ 
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM0.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM0.c
new file mode 100644
index 0000000..ece74d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM0.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Cortex-M0 Device System Source File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM3.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM3.c
new file mode 100644
index 0000000..2f5fa0b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM3.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Cortex-M3 Device System Source File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM4.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM4.c
new file mode 100644
index 0000000..beaaf6f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_sin_cos_example/system_ARMCM4.c
@@ -0,0 +1,81 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Cortex-M4 Device System Source File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM4.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvopt
new file mode 100644
index 0000000..b2f3f6d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvopt
@@ -0,0 +1,290 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    Target 1
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
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+        DARMCM1.DLL
+        -pCM0
+        SARMCM3.DLL
+        
+        TARMCM1.DLL
+        -pCM0
+      
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+        1
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+        .\arm_variance_example.ini
+        
+        
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+        
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+        
+      
+      
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          -T0
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+          0
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+          1
+          
402

+          0
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+          
404

+          0
+          0
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+    
+  
+
+  
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+      arm_variance_example_f32.c
+    
+  
+
+  
+    CMSIS
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+      system_ARMCM0.c
+    
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+
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvproj
new file mode 100644
index 0000000..c5354ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM0l_variance_example.uvproj
@@ -0,0 +1,425 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M0
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE
+          
+          
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+          4803
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+          
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+          SARMCM3.DLL
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvopt
new file mode 100644
index 0000000..37249e0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvopt
@@ -0,0 +1,290 @@
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+
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+  1.0
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+  
### uVision Project, (C) Keil Software

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvproj
new file mode 100644
index 0000000..bd68975
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM3l_variance_example.uvproj
@@ -0,0 +1,425 @@
+
+
+
+  1.1
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+  
### uVision Project, (C) Keil Software

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvopt
new file mode 100644
index 0000000..7cd95d3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvopt
@@ -0,0 +1,290 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvproj
new file mode 100644
index 0000000..42eace1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_cortexM4lf_variance_example.uvproj
@@ -0,0 +1,425 @@
+
+
+
+  1.1
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+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x4
+      ARM-ADS
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+        
+          Cortex-M4 FPU
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2
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+            0
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+            0
+            0
+            1
+          
+          .\debug\
+          arm_cortexM4lf_variance_example
+          1
+          0
+          0
+          1
+          1
+          .\debug\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            0
+            1
+            0
+            1
+            1
+            1
+            0
+            1
+          
+          0
+          -1
+          
+            
+            
+            
+            
+            .\arm_variance_example.ini
+          
+          
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            0
+            -1
+          
+          
+          
+          
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M4"
+            
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            1
+            0
+            0
+            5
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            3
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            
+              
+              ARM_MATH_CM4, __FPU_PRESENT = 1
+              
+              ..\..\..\..\Include;..\..\..\..\..\Device\ARM\ARMCM4\Include
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x00000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Source Group 1
+          
+            
+              arm_variance_example_f32.c
+              1
+              ..\arm_variance_example_f32.c
+            
+          
+        
+        
+          CMSIS Device
+          
+            
+              system_ARMCM4.c
+              1
+              ..\system_ARMCM4.c
+            
+            
+              startup_ARMCM4.s
+              2
+              .\startup_ARMCM4.s
+            
+          
+        
+        
+          CMSIS DSP_Library
+          
+            
+              arm_cortexM4lf_math.lib
+              4
+              ..\..\..\..\Lib\ARM\arm_cortexM4lf_math.lib
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_variance_example.ini b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_variance_example.ini
new file mode 100644
index 0000000..0aab2ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/arm_variance_example.ini
@@ -0,0 +1,14 @@
+
+/* This file demonstrates how to Map memory ranges, specify read, write, and execute permissions 
+   
+   The file can be executed in the following way:
+   1) manually from uVision command window (in debug mode) using command:
+   INCLUIDE arm_variance_example.ini
+
+*/
+
+
+// usual initialisation	for target setup
+MAP  0x20000000, 0x20008000  READ WRITE  // allow R/W access to IO space
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..0acd346
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM0.s
@@ -0,0 +1,144 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Cortex-M0 Core Device Startup File
+; *           for CM0 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..5af584b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM3.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Cortex-M3 Core Device Startup File
+; *           for CM3 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..09fdbd6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/ARM/startup_ARMCM4.s
@@ -0,0 +1,164 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM4 Device Series
+; * @version  V1.04
+; * @date     14. January 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; ******************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/arm_variance_example_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/arm_variance_example_f32.c
new file mode 100644
index 0000000..a163302
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/arm_variance_example_f32.c
@@ -0,0 +1,189 @@
+/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.     
+*    
+* $Date:        29. November 2010  
+* $Revision: 	V1.0.3
+*     
+* Project: 	    CMSIS DSP Library  
+* Title:	    arm_variance_example_f32.c		 
+* 
+* Description:	Example code demonstrating variance calculation of input sequence.
+*     
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**   
+ * @defgroup VarianceExample Variance Example   
+ *
+ * \par Description: 
+ * \par
+ * Demonstrates the use of Basic Math and Support Functions to calculate the variance of an 
+ * input sequence with N samples. Uniformly distributed white noise is taken as input. 
+ * 
+ * \par Algorithm:
+ * \par
+ * The variance of a sequence is the mean of the squared deviation of the sequence from its mean.
+ * \par
+ * This is denoted by the following equation: 
+ * 
 variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)

+ * where, x[n] is the input sequence, N is the number of input samples, and
+ * x' is the mean value of the input sequence, x[n].
+ * \par
+ * The mean value x' is defined as:
+ * 
 x' = (x[0] + x[1] + ... + x[n-1]) / N

+ *
+ * \par Block Diagram:
+ * \par
+ * \image html Variance.gif
+ *
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c testInput_f32 points to the input data
+ * \li \c wire1, \c wir2, \c wire3 temporary buffers
+ * \li \c blockSize number of samples processed at a time
+ * \li \c refVarianceOut reference variance value 
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_dot_prod_f32()
+ * - arm_mult_f32()
+ * - arm_sub_f32()
+ * - arm_fill_f32()
+ * - arm_copy_f32()
+ *
+ *  Refer  
+ * \link arm_variance_example_f32.c \endlink
+ *
+ */
+
+
+/** \example arm_variance_example_f32.c
+  */ 
+#include     
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+* Defines each of the tests performed
+* ------------------------------------------------------------------- */
+#define MAX_BLOCKSIZE	32
+#define DELTA           (0.000001f)
+
+
+/* ----------------------------------------------------------------------
+* Declare I/O buffers 
+* ------------------------------------------------------------------- */
+float32_t wire1[MAX_BLOCKSIZE];
+float32_t wire2[MAX_BLOCKSIZE];
+float32_t wire3[MAX_BLOCKSIZE];
+
+/* ----------------------------------------------------------------------
+* Test input data for Floating point Variance example for 32-blockSize
+* Generated by the MATLAB randn() function
+* ------------------------------------------------------------------- */
+
+float32_t testInput_f32[32] = 
+{ 
+-0.432564811528221, 	-1.665584378238097, 	0.125332306474831, 		0.287676420358549, 	
+-1.146471350681464, 	1.190915465642999, 		1.189164201652103, 		-0.037633276593318, 	
+0.327292361408654, 		0.174639142820925, 		-0.186708577681439, 	0.725790548293303, 	
+-0.588316543014189, 	2.183185818197101, 		-0.136395883086596, 	0.113931313520810, 	
+1.066768211359189, 		0.059281460523605, 		-0.095648405483669, 	-0.832349463650022, 	
+0.294410816392640, 		-1.336181857937804, 	0.714324551818952, 		1.623562064446271, 	
+-0.691775701702287, 	0.857996672828263, 		1.254001421602532, 		-1.593729576447477, 	
+-1.440964431901020, 	0.571147623658178, 		-0.399885577715363, 	0.689997375464345
+  
+};
+
+/* ----------------------------------------------------------------------
+* Declare Global variables 
+* ------------------------------------------------------------------- */
+uint32_t blockSize = 32;
+float32_t  refVarianceOut = 0.903941793931839; 
+
+/* ----------------------------------------------------------------------
+* Variance calculation test
+* ------------------------------------------------------------------- */
+
+int32_t main(void)
+{
+	arm_status status;
+	float32_t mean, oneByBlockSize;
+	float32_t variance;
+	float32_t diff;
+	
+	status = ARM_MATH_SUCCESS;
+	
+	/* Calculation of mean value of input */
+	
+	/* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */
+	
+	/* Fill wire1 buffer with 1.0 value */
+	arm_fill_f32(1.0,  wire1, blockSize);
+	
+	/* Calculate the dot product of wire1 and wire2 */
+	/* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */
+	arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean);
+	
+	/* Calculation of 1/blockSize */
+	oneByBlockSize = 1.0 / (blockSize);
+	
+	/* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1)  */
+	arm_mult_f32(&mean, &oneByBlockSize, &mean, 1);
+	
+	
+	/* Calculation of variance value of input */
+	
+	/* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */
+	
+	/* Fill wire2 with mean value x' */
+	arm_fill_f32(mean,  wire2, blockSize);
+	
+	/* wire3 contains (x-x') */		
+	arm_sub_f32(testInput_f32, wire2, wire3, blockSize);
+	
+	/* wire2 contains (x-x') */				
+	arm_copy_f32(wire3, wire2, blockSize);
+	
+	/* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */
+	arm_dot_prod_f32(wire2, wire3, blockSize, &variance); 
+
+    /* Calculation of 1/blockSize */
+	oneByBlockSize = 1.0 / (blockSize - 1);
+
+	/* Calculation of variance */		
+	arm_mult_f32(&variance, &oneByBlockSize, &variance, 1);
+	
+	/* absolute value of difference between ref and test */
+	diff = fabsf(refVarianceOut - variance);
+	
+	/* Comparison of variance value with reference */
+	if(diff > DELTA)
+	{
+		status = ARM_MATH_TEST_FAILURE;
+	}
+		
+	if( status != ARM_MATH_SUCCESS)
+	{
+	  while(1);
+	}
+
+    while(1);                             /* main function does not return */
+}
+
+ /** \endlink */
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM0.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM0.c
new file mode 100644
index 0000000..ece74d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM0.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Cortex-M0 Device System Source File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM3.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM3.c
new file mode 100644
index 0000000..2f5fa0b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM3.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Cortex-M3 Device System Source File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM4.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM4.c
new file mode 100644
index 0000000..beaaf6f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Examples/arm_variance_example/system_ARMCM4.c
@@ -0,0 +1,81 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Cortex-M4 Device System Source File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM4.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvopt
new file mode 100644
index 0000000..ff5038c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvopt
@@ -0,0 +1,3711 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
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+
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+    DSP_Lib CM0 BE
+    0x4
+    ARM-ADS
+    
+      12000000
+      
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvproj
new file mode 100644
index 0000000..2bc90b4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvproj
@@ -0,0 +1,3269 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      DSP_Lib CM0 LE
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M0
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE
+          
+          
+          
+          4803
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+            cmd.exe /C copy "!L" "..\..\..\Lib\ARM\"
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+          SARMCM3.DLL
+          
+          DARMCM1.DLL
+          -pCM0
+          SARMCM3.DLL
+          
+          TARMCM1.DLL
+          -pCM0
+        
+        
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+          "" ()
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+              1
+              ..\ComplexMathFunctions\arm_cmplx_conj_f32.c
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+            
+              arm_cmplx_conj_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_conj_q15.c
+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_dot_prod_f32.c
+            
+            
+              arm_cmplx_dot_prod_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_dot_prod_q15.c
+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_dot_prod_q31.c
+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_q15.c
+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ..\FilteringFunctions\arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ..\FilteringFunctions\arm_conv_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ..\FilteringFunctions\arm_conv_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ..\FilteringFunctions\arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ..\FilteringFunctions\arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ..\FilteringFunctions\arm_correlate_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ..\FilteringFunctions\arm_correlate_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ..\FilteringFunctions\arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_cfft_radix4_f32.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ..\ControllerFunctions\arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ..\ControllerFunctions\arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ..\ControllerFunctions\arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ..\StatisticsFunctions\arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ..\StatisticsFunctions\arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ..\StatisticsFunctions\arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ..\StatisticsFunctions\arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ..\StatisticsFunctions\arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ..\StatisticsFunctions\arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ..\StatisticsFunctions\arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ..\StatisticsFunctions\arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ..\StatisticsFunctions\arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ..\StatisticsFunctions\arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ..\StatisticsFunctions\arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ..\StatisticsFunctions\arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ..\StatisticsFunctions\arm_power_f32.c
+            
+            
+              arm_power_q7.c
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+              ..\FilteringFunctions\arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_cfft_radix4_f32.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ..\ControllerFunctions\arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ..\ControllerFunctions\arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ..\ControllerFunctions\arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ..\StatisticsFunctions\arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ..\StatisticsFunctions\arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ..\StatisticsFunctions\arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ..\StatisticsFunctions\arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ..\StatisticsFunctions\arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ..\StatisticsFunctions\arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ..\StatisticsFunctions\arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ..\StatisticsFunctions\arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ..\StatisticsFunctions\arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ..\StatisticsFunctions\arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ..\StatisticsFunctions\arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ..\StatisticsFunctions\arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ..\StatisticsFunctions\arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ..\StatisticsFunctions\arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ..\StatisticsFunctions\arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ..\StatisticsFunctions\arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ..\StatisticsFunctions\arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ..\StatisticsFunctions\arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ..\StatisticsFunctions\arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ..\StatisticsFunctions\arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              ..\StatisticsFunctions\arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ..\StatisticsFunctions\arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ..\StatisticsFunctions\arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ..\StatisticsFunctions\arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              ..\StatisticsFunctions\arm_var_q31.c
+            
+          
+        
+        
+          SupportFunctions
+          
+            
+              arm_copy_f32.c
+              1
+              ..\SupportFunctions\arm_copy_f32.c
+            
+            
+              arm_copy_q7.c
+              1
+              ..\SupportFunctions\arm_copy_q7.c
+            
+            
+              arm_copy_q15.c
+              1
+              ..\SupportFunctions\arm_copy_q15.c
+            
+            
+              arm_copy_q31.c
+              1
+              ..\SupportFunctions\arm_copy_q31.c
+            
+            
+              arm_fill_f32.c
+              1
+              ..\SupportFunctions\arm_fill_f32.c
+            
+            
+              arm_fill_q7.c
+              1
+              ..\SupportFunctions\arm_fill_q7.c
+            
+            
+              arm_fill_q15.c
+              1
+              ..\SupportFunctions\arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              ..\SupportFunctions\arm_fill_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              ..\SupportFunctions\arm_float_to_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              ..\SupportFunctions\arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              ..\SupportFunctions\arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
+              ..\SupportFunctions\arm_q7_to_float.c
+            
+            
+              arm_q7_to_q15.c
+              1
+              ..\SupportFunctions\arm_q7_to_q15.c
+            
+            
+              arm_q7_to_q31.c
+              1
+              ..\SupportFunctions\arm_q7_to_q31.c
+            
+            
+              arm_q15_to_float.c
+              1
+              ..\SupportFunctions\arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              ..\SupportFunctions\arm_q15_to_q7.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              ..\SupportFunctions\arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ..\SupportFunctions\arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ..\SupportFunctions\arm_q31_to_q7.c
+            
+            
+              arm_q31_to_q15.c
+              1
+              ..\SupportFunctions\arm_q31_to_q15.c
+            
+          
+        
+        
+          CommonTables
+          
+            
+              arm_common_tables.c
+              1
+              ..\CommonTables\arm_common_tables.c
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM3x_math.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM3x_math.uvopt
new file mode 100644
index 0000000..bc07c81
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM3x_math.uvopt
@@ -0,0 +1,3711 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
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+
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+    0
+    0
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+    DSP_Lib CM3 LE
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+        0
+        0
+        -1
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+        
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+        
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+
+  
+    DSP_Lib CM3 BE
+    0x4
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+      12000000
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+      0
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+        SARMCM3.DLL
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+        -pCM3
+        SARMCM3.DLL
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+        TCM.DLL
+        -pCM3
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+      
+        1
+        0
+        1
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM3x_math.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM3x_math.uvproj
new file mode 100644
index 0000000..fcbeb09
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM3x_math.uvproj
@@ -0,0 +1,3269 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      DSP_Lib CM3 LE
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M3
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE
+          
+          
+          
+          4349
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+          
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+          
+        
+        
+          SARMCM3.DLL
+          
+          DCM.DLL
+          -pCM3
+          SARMCM3.DLL
+          
+          TCM.DLL
+          -pCM3
+        
+        
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+          "" ()
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+            
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+            
+              arm_dot_prod_q31.c
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+            
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+            
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+            
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+            
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+            
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+            
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+            
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+            
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+            
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+            
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+            
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+            
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+            
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+            
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+              ..\ComplexMathFunctions\arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ..\FilteringFunctions\arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ..\FilteringFunctions\arm_conv_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ..\FilteringFunctions\arm_conv_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ..\FilteringFunctions\arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ..\FilteringFunctions\arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ..\FilteringFunctions\arm_correlate_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ..\FilteringFunctions\arm_correlate_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ..\FilteringFunctions\arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_cfft_radix4_f32.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ..\ControllerFunctions\arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ..\ControllerFunctions\arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ..\ControllerFunctions\arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ..\StatisticsFunctions\arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ..\StatisticsFunctions\arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ..\StatisticsFunctions\arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ..\StatisticsFunctions\arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ..\StatisticsFunctions\arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ..\StatisticsFunctions\arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ..\StatisticsFunctions\arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ..\StatisticsFunctions\arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ..\StatisticsFunctions\arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ..\StatisticsFunctions\arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ..\StatisticsFunctions\arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ..\StatisticsFunctions\arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ..\StatisticsFunctions\arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ..\StatisticsFunctions\arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ..\StatisticsFunctions\arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ..\StatisticsFunctions\arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ..\StatisticsFunctions\arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ..\StatisticsFunctions\arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ..\StatisticsFunctions\arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ..\StatisticsFunctions\arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              ..\StatisticsFunctions\arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ..\StatisticsFunctions\arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ..\StatisticsFunctions\arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ..\StatisticsFunctions\arm_var_q15.c
+            
+            
+              arm_var_q31.c
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM4x_math.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM4x_math.uvopt
new file mode 100644
index 0000000..5498da9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM4x_math.uvopt
@@ -0,0 +1,3969 @@
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM4x_math.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM4x_math.uvproj
new file mode 100644
index 0000000..8c2c8bb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexM4x_math.uvproj
@@ -0,0 +1,6527 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

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+            
+            
+              arm_correlate_f32.c
+              1
+              ..\FilteringFunctions\arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ..\FilteringFunctions\arm_correlate_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ..\FilteringFunctions\arm_correlate_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ..\FilteringFunctions\arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_cfft_radix4_f32.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ..\ControllerFunctions\arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ..\ControllerFunctions\arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ..\ControllerFunctions\arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ..\StatisticsFunctions\arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ..\StatisticsFunctions\arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ..\StatisticsFunctions\arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ..\StatisticsFunctions\arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ..\StatisticsFunctions\arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ..\StatisticsFunctions\arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ..\StatisticsFunctions\arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ..\StatisticsFunctions\arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ..\StatisticsFunctions\arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ..\StatisticsFunctions\arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ..\StatisticsFunctions\arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ..\StatisticsFunctions\arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ..\StatisticsFunctions\arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ..\StatisticsFunctions\arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ..\StatisticsFunctions\arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ..\StatisticsFunctions\arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ..\StatisticsFunctions\arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ..\StatisticsFunctions\arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ..\StatisticsFunctions\arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ..\StatisticsFunctions\arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              ..\StatisticsFunctions\arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ..\StatisticsFunctions\arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ..\StatisticsFunctions\arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ..\StatisticsFunctions\arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              ..\StatisticsFunctions\arm_var_q31.c
+            
+          
+        
+        
+          SupportFunctions
+          
+            
+              arm_copy_f32.c
+              1
+              ..\SupportFunctions\arm_copy_f32.c
+            
+            
+              arm_copy_q7.c
+              1
+              ..\SupportFunctions\arm_copy_q7.c
+            
+            
+              arm_copy_q15.c
+              1
+              ..\SupportFunctions\arm_copy_q15.c
+            
+            
+              arm_copy_q31.c
+              1
+              ..\SupportFunctions\arm_copy_q31.c
+            
+            
+              arm_fill_f32.c
+              1
+              ..\SupportFunctions\arm_fill_f32.c
+            
+            
+              arm_fill_q7.c
+              1
+              ..\SupportFunctions\arm_fill_q7.c
+            
+            
+              arm_fill_q15.c
+              1
+              ..\SupportFunctions\arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              ..\SupportFunctions\arm_fill_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              ..\SupportFunctions\arm_float_to_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              ..\SupportFunctions\arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              ..\SupportFunctions\arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
+              ..\SupportFunctions\arm_q7_to_float.c
+            
+            
+              arm_q7_to_q15.c
+              1
+              ..\SupportFunctions\arm_q7_to_q15.c
+            
+            
+              arm_q7_to_q31.c
+              1
+              ..\SupportFunctions\arm_q7_to_q31.c
+            
+            
+              arm_q15_to_float.c
+              1
+              ..\SupportFunctions\arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              ..\SupportFunctions\arm_q15_to_q7.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              ..\SupportFunctions\arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ..\SupportFunctions\arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ..\SupportFunctions\arm_q31_to_q7.c
+            
+            
+              arm_q31_to_q15.c
+              1
+              ..\SupportFunctions\arm_q31_to_q15.c
+            
+          
+        
+        
+          CommonTables
+          
+            
+              arm_common_tables.c
+              1
+              ..\CommonTables\arm_common_tables.c
+            
+          
+        
+      
+    
+    
+      DSP_Lib CM4 LE FPU
+      0x4
+      ARM-ADS
+      
+        
+          Cortex-M4 FPU
+          ARM
+          CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2
+          
+          
+          
+          5237
+          
+          
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+          SARMCM3.DLL
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+            
+              arm_lms_norm_init_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_f32.c
+            
+            
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+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_f32.c
+            
+            
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+              1
+              ..\MatrixFunctions\arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_q31.c
+            
+            
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+              1
+              ..\MatrixFunctions\arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
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+              1
+              ..\TransformFunctions\arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_q31.c
+            
+          
+        
+        
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+          
+            
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+              1
+              ..\ControllerFunctions\arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q31.c
+            
+            
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+              1
+              ..\ControllerFunctions\arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q31.c
+            
+            
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+              1
+              ..\ControllerFunctions\arm_sin_cos_f32.c
+            
+            
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+              1
+              ..\ControllerFunctions\arm_sin_cos_q31.c
+            
+          
+        
+        
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+          
+            
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+              1
+              ..\StatisticsFunctions\arm_max_f32.c
+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
+              ..\StatisticsFunctions\arm_mean_f32.c
+            
+            
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+              1
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+            
+            
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+              1
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+            
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+              1
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+            
+            
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+              1
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+            
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+              1
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+            
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+            
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+            
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+            
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+            
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+            
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+            
+            
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+            
+            
+              arm_var_q31.c
+              1
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+            
+          
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+            
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+              1
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+            
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+              1
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+            
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+            
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+              1
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+            
+              arm_float_to_q7.c
+              1
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+            
+              arm_float_to_q15.c
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+            
+            
+              arm_float_to_q31.c
+              1
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+            
+            
+              arm_q7_to_float.c
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+            
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+            
+              arm_q7_to_q31.c
+              1
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+            
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+            
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+              1
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+            
+            
+              arm_q15_to_q31.c
+              1
+              ..\SupportFunctions\arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ..\SupportFunctions\arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ..\SupportFunctions\arm_q31_to_q7.c
+            
+            
+              arm_q31_to_q15.c
+              1
+              ..\SupportFunctions\arm_q31_to_q15.c
+            
+          
+        
+        
+          CommonTables
+          
+            
+              arm_common_tables.c
+              1
+              ..\CommonTables\arm_common_tables.c
+            
+          
+        
+      
+    
+    
+      DSP_Lib CM4 BE
+      0x4
+      ARM-ADS
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+              1
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+            
+              arm_abs_q7.c
+              1
+              ..\BasicMathFunctions\arm_abs_q7.c
+            
+            
+              arm_abs_q15.c
+              1
+              ..\BasicMathFunctions\arm_abs_q15.c
+            
+            
+              arm_abs_q31.c
+              1
+              ..\BasicMathFunctions\arm_abs_q31.c
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+            
+              arm_add_f32.c
+              1
+              ..\BasicMathFunctions\arm_add_f32.c
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+            
+              arm_add_q7.c
+              1
+              ..\BasicMathFunctions\arm_add_q7.c
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+            
+              arm_add_q15.c
+              1
+              ..\BasicMathFunctions\arm_add_q15.c
+            
+            
+              arm_add_q31.c
+              1
+              ..\BasicMathFunctions\arm_add_q31.c
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+            
+              arm_dot_prod_f32.c
+              1
+              ..\BasicMathFunctions\arm_dot_prod_f32.c
+            
+            
+              arm_dot_prod_q7.c
+              1
+              ..\BasicMathFunctions\arm_dot_prod_q7.c
+            
+            
+              arm_dot_prod_q15.c
+              1
+              ..\BasicMathFunctions\arm_dot_prod_q15.c
+            
+            
+              arm_dot_prod_q31.c
+              1
+              ..\BasicMathFunctions\arm_dot_prod_q31.c
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+            
+              arm_mult_f32.c
+              1
+              ..\BasicMathFunctions\arm_mult_f32.c
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+            
+              arm_mult_q7.c
+              1
+              ..\BasicMathFunctions\arm_mult_q7.c
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+            
+              arm_mult_q15.c
+              1
+              ..\BasicMathFunctions\arm_mult_q15.c
+            
+            
+              arm_mult_q31.c
+              1
+              ..\BasicMathFunctions\arm_mult_q31.c
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+            
+              arm_negate_f32.c
+              1
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+            
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+              1
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+            
+              arm_negate_q15.c
+              1
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+            
+              arm_negate_q31.c
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+            
+              arm_offset_f32.c
+              1
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+            
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+              1
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+            
+              arm_offset_q15.c
+              1
+              ..\BasicMathFunctions\arm_offset_q15.c
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+            
+              arm_offset_q31.c
+              1
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+            
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+            
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+            
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+            
+              arm_scale_q31.c
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+            
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+            
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+            
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+            
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+              ..\BasicMathFunctions\arm_sub_q31.c
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+          
+        
+        
+          FastMathFunctions
+          
+            
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+              1
+              ..\FastMathFunctions\arm_cos_f32.c
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+            
+              arm_cos_q15.c
+              1
+              ..\FastMathFunctions\arm_cos_q15.c
+            
+            
+              arm_cos_q31.c
+              1
+              ..\FastMathFunctions\arm_cos_q31.c
+            
+            
+              arm_sin_f32.c
+              1
+              ..\FastMathFunctions\arm_sin_f32.c
+            
+            
+              arm_sin_q15.c
+              1
+              ..\FastMathFunctions\arm_sin_q15.c
+            
+            
+              arm_sin_q31.c
+              1
+              ..\FastMathFunctions\arm_sin_q31.c
+            
+            
+              arm_sqrt_q15.c
+              1
+              ..\FastMathFunctions\arm_sqrt_q15.c
+            
+            
+              arm_sqrt_q31.c
+              1
+              ..\FastMathFunctions\arm_sqrt_q31.c
+            
+          
+        
+        
+          ComplexMathFunctions
+          
+            
+              arm_cmplx_conj_f32.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_conj_f32.c
+            
+            
+              arm_cmplx_conj_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_conj_q15.c
+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_dot_prod_f32.c
+            
+            
+              arm_cmplx_dot_prod_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_dot_prod_q15.c
+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_dot_prod_q31.c
+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_q15.c
+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ..\ComplexMathFunctions\arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ..\FilteringFunctions\arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ..\FilteringFunctions\arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ..\FilteringFunctions\arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ..\FilteringFunctions\arm_conv_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ..\FilteringFunctions\arm_conv_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ..\FilteringFunctions\arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ..\FilteringFunctions\arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ..\FilteringFunctions\arm_correlate_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ..\FilteringFunctions\arm_correlate_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ..\FilteringFunctions\arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_cfft_radix4_f32.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ..\ControllerFunctions\arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ..\ControllerFunctions\arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ..\ControllerFunctions\arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ..\StatisticsFunctions\arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ..\StatisticsFunctions\arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ..\StatisticsFunctions\arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ..\StatisticsFunctions\arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ..\StatisticsFunctions\arm_mean_f32.c
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+            
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+              ..\FilteringFunctions\arm_correlate_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ..\FilteringFunctions\arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ..\FilteringFunctions\arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ..\FilteringFunctions\arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ..\FilteringFunctions\arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ..\FilteringFunctions\arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ..\MatrixFunctions\arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_cfft_radix4_f32.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ..\TransformFunctions\arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ..\TransformFunctions\arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ..\TransformFunctions\arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ..\TransformFunctions\arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ..\TransformFunctions\arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ..\TransformFunctions\arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ..\TransformFunctions\arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ..\ControllerFunctions\arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ..\ControllerFunctions\arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ..\ControllerFunctions\arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ..\ControllerFunctions\arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ..\StatisticsFunctions\arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ..\StatisticsFunctions\arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ..\StatisticsFunctions\arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ..\StatisticsFunctions\arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ..\StatisticsFunctions\arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ..\StatisticsFunctions\arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ..\StatisticsFunctions\arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ..\StatisticsFunctions\arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ..\StatisticsFunctions\arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ..\StatisticsFunctions\arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ..\StatisticsFunctions\arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ..\StatisticsFunctions\arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ..\StatisticsFunctions\arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ..\StatisticsFunctions\arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ..\StatisticsFunctions\arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ..\StatisticsFunctions\arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ..\StatisticsFunctions\arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ..\StatisticsFunctions\arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ..\StatisticsFunctions\arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ..\StatisticsFunctions\arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              ..\StatisticsFunctions\arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ..\StatisticsFunctions\arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ..\StatisticsFunctions\arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ..\StatisticsFunctions\arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              ..\StatisticsFunctions\arm_var_q31.c
+            
+          
+        
+        
+          SupportFunctions
+          
+            
+              arm_copy_f32.c
+              1
+              ..\SupportFunctions\arm_copy_f32.c
+            
+            
+              arm_copy_q7.c
+              1
+              ..\SupportFunctions\arm_copy_q7.c
+            
+            
+              arm_copy_q15.c
+              1
+              ..\SupportFunctions\arm_copy_q15.c
+            
+            
+              arm_copy_q31.c
+              1
+              ..\SupportFunctions\arm_copy_q31.c
+            
+            
+              arm_fill_f32.c
+              1
+              ..\SupportFunctions\arm_fill_f32.c
+            
+            
+              arm_fill_q7.c
+              1
+              ..\SupportFunctions\arm_fill_q7.c
+            
+            
+              arm_fill_q15.c
+              1
+              ..\SupportFunctions\arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              ..\SupportFunctions\arm_fill_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              ..\SupportFunctions\arm_float_to_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              ..\SupportFunctions\arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              ..\SupportFunctions\arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
+              ..\SupportFunctions\arm_q7_to_float.c
+            
+            
+              arm_q7_to_q15.c
+              1
+              ..\SupportFunctions\arm_q7_to_q15.c
+            
+            
+              arm_q7_to_q31.c
+              1
+              ..\SupportFunctions\arm_q7_to_q31.c
+            
+            
+              arm_q15_to_float.c
+              1
+              ..\SupportFunctions\arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              ..\SupportFunctions\arm_q15_to_q7.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              ..\SupportFunctions\arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ..\SupportFunctions\arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ..\SupportFunctions\arm_q31_to_q7.c
+            
+            
+              arm_q31_to_q15.c
+              1
+              ..\SupportFunctions\arm_q31_to_q15.c
+            
+          
+        
+        
+          CommonTables
+          
+            
+              arm_common_tables.c
+              1
+              ..\CommonTables\arm_common_tables.c
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat
new file mode 100644
index 0000000..600ceb5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat
@@ -0,0 +1,14 @@
+
+SET TMP=C:\Temp
+SET TEMP=C:\Temp
+
+SET UVEXE=C:\Keil\UV4\UV4.EXE
+
+%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 LE" -o"DSP_Lib CM0 LE.txt"
+%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 BE" -o"DSP_Lib CM0 BE.txt"
+%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 LE" -o"DSP_Lib CM3 LE.txt"
+%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 BE" -o"DSP_Lib CM3 BE.txt"
+%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE" -o"DSP_Lib CM4 LE.txt"
+%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 BE" -o"DSP_Lib CM4 BE.txt"
+%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE FPU" -o"DSP_Lib CM4 LE FPU.txt"
+%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 BE FPU" -o"DSP_Lib CM4 BE FPU.txt"
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c
new file mode 100644
index 0000000..2b6bd53
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_abs_f32.c   
+*   
+* Description:	Vector absolute value.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include 
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @defgroup BasicAbs Vector Absolute Value   
+ *   
+ * Computes the absolute value of a vector on an element-by-element basis.   
+ *   
+ * 
   
+ *     pDst[n] = abs(pSrcA[n]),   0 <= n < blockSize.   
+ * 
   
+ *   
+ * The operation can be done in-place by setting the input and output pointers to the same buffer.   
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup BasicAbs   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point vector absolute value.   
+ * @param[in]       *pSrc points to the input buffer   
+ * @param[out]      *pDst points to the output buffer   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ */
+
+void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Calculate absolute and then store the results in the destination buffer. */
+    *pDst++ = fabsf(*pSrc++);
+    *pDst++ = fabsf(*pSrc++);
+    *pDst++ = fabsf(*pSrc++);
+    *pDst++ = fabsf(*pSrc++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /*   #ifndef ARM_MATH_CM0   */
+
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Calculate absolute and then store the results in the destination buffer. */
+    *pDst++ = fabsf(*pSrc++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of BasicAbs group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c
new file mode 100644
index 0000000..0a3941b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c
@@ -0,0 +1,170 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_abs_q15.c   
+*   
+* Description:	Q15 vector absolute value.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup BasicAbs   
+ * @{   
+ */
+
+/**   
+ * @brief Q15 vector absolute value.   
+ * @param[in]       *pSrc points to the input buffer   
+ * @param[out]      *pDst points to the output buffer   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.   
+ */
+
+void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t in1;                                     /* Input value1 */
+  q15_t in2;                                     /* Input value2 */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Read two inputs */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+
+
+    /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(((in1 > 0) ? in1 : __SSAT(-in1, 16)),
+              ((in2 > 0) ? in2 : __SSAT(-in2, 16)), 16);
+
+#else
+
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(((in2 > 0) ? in2 : __SSAT(-in2, 16)),
+              ((in1 > 0) ? in1 : __SSAT(-in1, 16)), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(((in1 > 0) ? in1 : __SSAT(-in1, 16)),
+              ((in2 > 0) ? in2 : __SSAT(-in2, 16)), 16);
+
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(((in2 > 0) ? in2 : __SSAT(-in2, 16)),
+              ((in1 > 0) ? in1 : __SSAT(-in1, 16)), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Read the input */
+    in1 = *pSrc++;
+
+    /* Calculate absolute value of input and then store the result in the destination buffer. */
+    *pDst++ = (in1 > 0) ? in1 : __SSAT(-in1, 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* Temporary input variable */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Read the input */
+    in = *pSrc++;
+
+    /* Calculate absolute value of input and then store the result in the destination buffer. */
+    *pDst++ = (in > 0) ? in : __SSAT(-in, 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of BasicAbs group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c
new file mode 100644
index 0000000..52d7d3d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_abs_q31.c   
+*   
+* Description:	Q31 vector absolute value.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup BasicAbs   
+ * @{   
+ */
+
+
+/**   
+ * @brief Q31 vector absolute value.   
+ * @param[in]       *pSrc points to the input buffer   
+ * @param[out]      *pDst points to the output buffer   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.   
+ */
+
+void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in;                                      /* Input value */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
+    in = *pSrc++;
+    *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in);
+    in = *pSrc++;
+    *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in);
+    in = *pSrc++;
+    *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in);
+    in = *pSrc++;
+    *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /*   #ifndef ARM_MATH_CM0   */
+
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
+    in = *pSrc++;
+    *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of BasicAbs group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c
new file mode 100644
index 0000000..81019fd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_abs_q7.c   
+*   
+* Description:	Q7 vector absolute value.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup BasicAbs   
+ * @{   
+ */
+
+/**   
+ * @brief Q7 vector absolute value.   
+ * @param[in]       *pSrc points to the input buffer   
+ * @param[out]      *pDst points to the output buffer   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.   
+ */
+
+void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  q7_t in1;                                      /* Input value1 */
+  q7_t in2;                                      /* Input value2 */
+  q7_t in3;                                      /* Input value3 */
+  q7_t in4;                                      /* Input value4 */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Read 4 inputs */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    /* Store the Absolute result in the destination buffer by packing the 4 values in single cycle */
+    *__SIMD32(pDst)++ =
+      __PACKq7(((in1 > 0) ? in1 : __SSAT(-in1, 8)),
+               ((in2 > 0) ? in2 : __SSAT(-in2, 8)),
+               ((in3 > 0) ? in3 : __SSAT(-in3, 8)),
+               ((in4 > 0) ? in4 : __SSAT(-in4, 8)));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Read the input */
+    in1 = *pSrc++;
+
+    /* Store the Absolute result in the destination buffer */
+    *pDst++ = (in1 > 0) ? in1 : __SSAT(-in1, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t in;                                       /* Temporary input varible */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = |A| */
+    /* Read the input */
+    in = *pSrc++;
+
+    /* Store the Absolute result in the destination buffer */
+    *pDst++ = (in > 0) ? in : __SSAT(-in, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0   */
+
+}
+
+/**   
+ * @} end of BasicAbs group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c
new file mode 100644
index 0000000..d73a6ef
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_add_f32.c   
+*   
+* Description:	Floating-point vector addition.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @defgroup BasicAdd Vector Addition   
+ *   
+ * Element-by-element addition of two vectors.   
+ *   
+ * 
   
+ *     pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.   
+ * 
   
+ *   
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup BasicAdd   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point vector addition.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ */
+
+void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = (*pSrcA++) + (*pSrcB++);
+    *pDst++ = (*pSrcA++) + (*pSrcB++);
+    *pDst++ = (*pSrcA++) + (*pSrcB++);
+    *pDst++ = (*pSrcA++) + (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = (*pSrcA++) + (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicAdd group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c
new file mode 100644
index 0000000..f4ede53
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_add_q15.c   
+*   
+* Description:	Q15 vector addition   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup BasicAdd   
+ * @{   
+ */
+
+/**   
+ * @brief Q15 vector addition.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ */
+
+void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+    *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+}
+
+/**   
+ * @} end of BasicAdd group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c
new file mode 100644
index 0000000..e33b9e2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c
@@ -0,0 +1,129 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_add_q31.c   
+*   
+* Description:	Q31 vector addition.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup BasicAdd   
+ * @{   
+ */
+
+
+/**   
+ * @brief Q31 vector addition.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.   
+ */
+
+void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+    *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+    *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+    *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of BasicAdd group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c
new file mode 100644
index 0000000..08199c3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c
@@ -0,0 +1,126 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_add_q7.c   
+*   
+* Description:	Q7 vector addition.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup BasicAdd   
+ * @{   
+ */
+
+/**   
+ * @brief Q7 vector addition.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.   
+ */
+
+void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + B */
+    /* Add and then store the results in the destination buffer. */
+    *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+}
+
+/**   
+ * @} end of BasicAdd group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c
new file mode 100644
index 0000000..bc7516e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_dot_prod_f32.c   
+*   
+* Description:	Floating-point dot product.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @defgroup dot_prod Vector Dot Product   
+ *   
+ * Computes the dot product of two vectors.   
+ * The vectors are multiplied element-by-element and then summed.   
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup dot_prod   
+ * @{   
+ */
+
+/**   
+ * @brief Dot product of floating-point vectors.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @param[out]      *result output result returned here   
+ * @return none.   
+ */
+
+
+void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the result in a temporary buffer */
+    sum += (*pSrcA++) * (*pSrcB++);
+    sum += (*pSrcA++) * (*pSrcB++);
+    sum += (*pSrcA++) * (*pSrcB++);
+    sum += (*pSrcA++) * (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the result in a temporary buffer. */
+    sum += (*pSrcA++) * (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+  /* Store the result back in the destination buffer */
+  *result = sum;
+}
+
+/**   
+ * @} end of dot_prod group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c
new file mode 100644
index 0000000..50be68c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_dot_prod_q15.c   
+*   
+* Description:	Q15 dot product.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup dot_prod   
+ * @{   
+ */
+
+/**   
+ * @brief Dot product of Q15 vectors.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @param[out]      *result output result returned here   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these   
+ * results are added to a 64-bit accumulator in 34.30 format.   
+ * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator   
+ * there is no risk of overflow.   
+ * The return result is in 34.30 format.   
+ */
+
+void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the result in a temporary buffer. */
+    sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
+    sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the results in a temporary buffer. */
+    sum = __SMLALD(*pSrcA++, *pSrcB++, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the results in a temporary buffer. */
+    sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the result in the destination buffer in 34.30 format */
+  *result = sum;
+
+}
+
+/**   
+ * @} end of dot_prod group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c
new file mode 100644
index 0000000..eb5f674
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_dot_prod_q31.c   
+*   
+* Description:	Q31 dot product.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup dot_prod   
+ * @{   
+ */
+
+/**   
+ * @brief Dot product of Q31 vectors.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @param[out]      *result output result returned here   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these   
+ * are truncated to 2.48 format by discarding the lower 14 bits.   
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.   
+ * There are 15 guard bits in the accumulator and there is no risk of overflow as long as   
+ * the length of the vectors is less than 2^16 elements.   
+ * The return result is in 16.48 format.   
+ */
+
+void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the result in a temporary buffer. */
+    sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u;
+    sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u;
+    sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u;
+    sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Calculate dot product and then store the result in a temporary buffer. */
+    sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result in the destination buffer in 16.48 format */
+  *result = sum;
+}
+
+/**   
+ * @} end of dot_prod group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c
new file mode 100644
index 0000000..cfea032
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c
@@ -0,0 +1,163 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_dot_prod_q7.c   
+*   
+* Description:	Q7 dot product.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup dot_prod   
+ * @{   
+ */
+
+/**   
+ * @brief Dot product of Q7 vectors.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @param[out]      *result output result returned here   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these   
+ * results are added to an accumulator in 18.14 format.   
+ * Nonsaturating additions are used and there is no danger of wrap around as long as   
+ * the vectors are less than 2^18 elements long.   
+ * The return result is in 18.14 format.   
+ */
+
+void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+  q31_t sum = 0;                                 /* Temporary variables to store output */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t input1, input2;                          /* Temporary variables to store input */
+  q15_t in1, in2;                                /* Temporary variables to store input */
+
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Reading two inputs of SrcA buffer and packing */
+    in1 = (q15_t) * pSrcA++;
+    in2 = (q15_t) * pSrcA++;
+    input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+    /* Reading two inputs of SrcB buffer and packing */
+    in1 = (q15_t) * pSrcB++;
+    in2 = (q15_t) * pSrcB++;
+    input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Perform Dot product of 2 packed inputs using SMLALD and store the result in a temporary variable. */
+    sum = __SMLAD(input1, input2, sum);
+
+    /* Reading two inputs of SrcA buffer and packing */
+    in1 = (q15_t) * pSrcA++;
+    in2 = (q15_t) * pSrcA++;
+    input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+    /* Reading two inputs of SrcB buffer and packing */
+    in1 = (q15_t) * pSrcB++;
+    in2 = (q15_t) * pSrcB++;
+    input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Perform Dot product of 2 packed inputs using SMLALD and store the result in a temporary variable. */
+    sum = __SMLAD(input1, input2, sum);
+
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Dot product and then store the results in a temporary buffer. */
+    sum = __SMLAD(*pSrcA++, *pSrcB++, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+    /* Dot product and then store the results in a temporary buffer. */
+    sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  /* Store the result in the destination buffer in 18.14 format */
+  *result = sum;
+}
+
+/**   
+ * @} end of dot_prod group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c
new file mode 100644
index 0000000..5c2dac0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c
@@ -0,0 +1,126 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mult_f32.c   
+*   
+* Description:	Floating-point vector multiplication.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @defgroup BasicMult Vector Multiplication   
+ *   
+ * Element-by-element multiplication of two vectors.   
+ *   
+ * 
   
+ *     pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.   
+ * 
   
+ *   
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup BasicMult   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point vector multiplication.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ */
+
+void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the results in output buffer */
+    *pDst++ = (*pSrcA++) * (*pSrcB++);
+    *pDst++ = (*pSrcA++) * (*pSrcB++);
+    *pDst++ = (*pSrcA++) * (*pSrcB++);
+    *pDst++ = (*pSrcA++) * (*pSrcB++);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the results in output buffer */
+    *pDst++ = (*pSrcA++) * (*pSrcB++);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of BasicMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c
new file mode 100644
index 0000000..76a3843
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mult_q15.c   
+*   
+* Description:	Q15 vector multiplication.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup BasicMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief           Q15 vector multiplication   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ */
+
+void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the result in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16);
+    *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16);
+    *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16);
+    *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the result in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c
new file mode 100644
index 0000000..c682c11
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mult_q31.c   
+*   
+* Description:	Q31 vector multiplication.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup BasicMult   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 vector multiplication.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.   
+ */
+
+void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and then store the results in the destination buffer. */
+    *pDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31);
+    *pDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31);
+    *pDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31);
+    *pDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and then store the results in the destination buffer. */
+    *pDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c
new file mode 100644
index 0000000..285fc04
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c
@@ -0,0 +1,125 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mult_q7.c   
+*   
+* Description:	Q7 vector multiplication.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10 DP   
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup BasicMult   
+ * @{   
+ */
+
+/**   
+ * @brief           Q7 vector multiplication   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.   
+ */
+
+void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q7_t out1, out2, out3, out4;                   /* Temporary variables to store the product */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the results in temporary variables */
+    out1 = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7);
+    out2 = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7);
+    out3 = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7);
+    out4 = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7);
+
+    /* Store the results of 4 inputs in the destination buffer in single cycle by packing */
+    *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * B */
+    /* Multiply the inputs and store the result in the destination buffer */
+    *pDst++ = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c
new file mode 100644
index 0000000..13deaa9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c
@@ -0,0 +1,117 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_negate_f32.c   
+*   
+* Description:	Negates floating-point vectors.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @defgroup negate Vector Negate   
+ *   
+ * Negates the elements of a vector.   
+ *   
+ * 
   
+ *     pDst[n] = -pSrc[n],   0 <= n < blockSize.   
+ * 
   
+ */
+
+/**   
+ * @addtogroup negate   
+ * @{   
+ */
+
+/**   
+ * @brief  Negates the elements of a floating-point vector.   
+ * @param[in]  *pSrc points to the input vector   
+ * @param[out]  *pDst points to the output vector   
+ * @param[in]  blockSize number of samples in the vector   
+ * @return none.   
+ */
+
+void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Negate and then store the results in the destination buffer. */
+    *pDst++ = -*pSrc++;
+    *pDst++ = -*pSrc++;
+    *pDst++ = -*pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Negate and then store the results in the destination buffer. */
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of negate group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c
new file mode 100644
index 0000000..7051431
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_negate_q15.c   
+*   
+* Description:	Negates Q15 vectors.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup negate   
+ * @{   
+ */
+
+/**   
+ * @brief  Negates the elements of a Q15 vector.   
+ * @param[in]  *pSrc points to the input vector   
+ * @param[out]  *pDst points to the output vector   
+ * @param[in]  blockSize number of samples in the vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.   
+ */
+
+void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t in1, in2;                                /* Temporary variables */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Read two inputs */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    /* Negate and then store the results in the destination buffer by packing. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = __PKHBT(__SSAT(-in1, 16), __SSAT(-in2, 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ = __PKHBT(__SSAT(-in2, 16), __SSAT(-in1, 16), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = __PKHBT(__SSAT(-in1, 16), __SSAT(-in2, 16), 16);
+
+#else
+
+
+    *__SIMD32(pDst)++ = __PKHBT(__SSAT(-in2, 16), __SSAT(-in1, 16), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Negate and then store the result in the destination buffer. */
+    *pDst++ = __SSAT(-*pSrc++, 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of negate group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c
new file mode 100644
index 0000000..c917a84
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_negate_q31.c   
+*   
+* Description:	Negates Q31 vectors.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup negate   
+ * @{   
+ */
+
+/**   
+ * @brief  Negates the elements of a Q31 vector.   
+ * @param[in]  *pSrc points to the input vector   
+ * @param[out]  *pDst points to the output vector   
+ * @param[in]  blockSize number of samples in the vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.   
+ */
+
+void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t in;                                      /* Temporary variable */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Negate and then store the results in the destination buffer. */
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Negate and then store the result in the destination buffer. */
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of negate group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c
new file mode 100644
index 0000000..ec991bd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_negate_q7.c   
+*   
+* Description:	Negates Q7 vectors.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup negate   
+ * @{   
+ */
+
+/**   
+ * @brief  Negates the elements of a Q7 vector.   
+ * @param[in]  *pSrc points to the input vector   
+ * @param[out]  *pDst points to the output vector   
+ * @param[in]  blockSize number of samples in the vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.   
+ */
+
+void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q7_t in1;                                      /* Input value1 */
+  q7_t in2;                                      /* Input value2 */
+  q7_t in3;                                      /* Input value3 */
+  q7_t in4;                                      /* Input value4 */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Read four inputs */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    /* Store the Negated results in the destination buffer in a single cycle by packing the results */
+    *__SIMD32(pDst)++ =
+      __PACKq7(__SSAT(-in1, 8), __SSAT(-in2, 8), __SSAT(-in3, 8),
+               __SSAT(-in4, 8));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = -A */
+    /* Negate and then store the results in the destination buffer. */
+    *pDst++ = __SSAT(-*pSrc++, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of negate group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c
new file mode 100644
index 0000000..4fcbbbe
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_offset_f32.c   
+*   
+* Description:	Floating-point vector offset.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @defgroup offset Vector Offset   
+ *   
+ * Adds a constant offset to each element of a vector.   
+ *   
+ * 
   
+ *     pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.   
+ * 
   
+ *   
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup offset   
+ * @{   
+ */
+
+/**   
+ * @brief  Adds a constant offset to a floating-point vector.   
+ * @param[in]  *pSrc points to the input vector   
+ * @param[in]  offset is the offset to be added   
+ * @param[out]  *pDst points to the output vector   
+ * @param[in]  blockSize number of samples in the vector   
+ * @return none.   
+ */
+
+
+void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the results in the destination buffer. */
+    *pDst++ = (*pSrc++) + offset;
+    *pDst++ = (*pSrc++) + offset;
+    *pDst++ = (*pSrc++) + offset;
+    *pDst++ = (*pSrc++) + offset;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the result in the destination buffer. */
+    *pDst++ = (*pSrc++) + offset;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of offset group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c
new file mode 100644
index 0000000..a6eaa86
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_offset_q15.c   
+*   
+* Description:	Q15 vector offset.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup offset   
+ * @{   
+ */
+
+/**   
+ * @brief  Adds a constant offset to a Q15 vector.   
+ * @param[in]  *pSrc points to the input vector   
+ * @param[in]  offset is the offset to be added   
+ * @param[out]  *pDst points to the output vector   
+ * @param[in]  blockSize number of samples in the vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.   
+ */
+
+void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t offset_packed;                           /* Offset packed to 32 bit */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+  offset_packed = __PKHBT(offset, offset, 16);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the results in the destination buffer, 2 samples at a time. */
+    *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
+    *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the results in the destination buffer. */
+    *pDst++ = (q15_t) __QADD16(*pSrc++, offset);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the results in the destination buffer. */
+    *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of offset group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c
new file mode 100644
index 0000000..dab3a77
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c
@@ -0,0 +1,126 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_offset_q31.c   
+*   
+* Description:	Q31 vector offset.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup offset   
+ * @{   
+ */
+
+/**   
+ * @brief  Adds a constant offset to a Q31 vector.   
+ * @param[in]  *pSrc points to the input vector   
+ * @param[in]  offset is the offset to be added   
+ * @param[out]  *pDst points to the output vector   
+ * @param[in]  blockSize number of samples in the vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated.   
+ */
+
+void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the results in the destination buffer. */
+    *pDst++ = __QADD(*pSrc++, offset);
+    *pDst++ = __QADD(*pSrc++, offset);
+    *pDst++ = __QADD(*pSrc++, offset);
+    *pDst++ = __QADD(*pSrc++, offset);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the result in the destination buffer. */
+    *pDst++ = __QADD(*pSrc++, offset);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the result in the destination buffer. */
+    *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of offset group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c
new file mode 100644
index 0000000..8ed8ddd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_offset_q7.c   
+*   
+* Description:	Q7 vector offset.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup offset   
+ * @{   
+ */
+
+/**   
+ * @brief  Adds a constant offset to a Q7 vector.   
+ * @param[in]  *pSrc points to the input vector   
+ * @param[in]  offset is the offset to be added   
+ * @param[out]  *pDst points to the output vector   
+ * @param[in]  blockSize number of samples in the vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q7 range [0x80 0x7F] are saturated.   
+ */
+
+void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q31_t offset_packed;                           /* Offset packed to 32 bit */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+  offset_packed = __PACKq7(offset, offset, offset, offset);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */
+    *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the result in the destination buffer. */
+    *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A + offset */
+    /* Add offset and then store the result in the destination buffer. */
+    *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of offset group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c
new file mode 100644
index 0000000..f51f78e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_scale_f32.c   
+*   
+* Description:	Multiplies a floating-point vector by a scalar.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @defgroup scale Vector Scale   
+ *   
+ * Multiply a vector by a scalar value.  For floating-point data, the algorithm used is:   
+ *   
+ * 
   
+ *     pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.   
+ * 
   
+ *   
+ * In the fixed-point Q7, Q15, and Q31 functions, scale is represented by   
+ * a fractional multiplication scaleFract and an arithmetic shift shift.   
+ * The shift allows the gain of the scaling operation to exceed 1.0.   
+ * The algorithm used with fixed-point data is:   
+ *   
+ * 
   
+ *     pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.   
+ * 
   
+ *   
+ * The overall scale factor applied to the fixed-point data is   
+ * 
   
+ *     scale = scaleFract * 2^shift.   
+ * 
   
+ */
+
+/**   
+ * @addtogroup scale   
+ * @{   
+ */
+
+/**   
+ * @brief Multiplies a floating-point vector by a scalar.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       scale scale factor to be applied   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in the vector   
+ * @return none.   
+ */
+
+
+void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the results in the destination buffer. */
+    *pDst++ = (*pSrc++) * scale;
+    *pDst++ = (*pSrc++) * scale;
+    *pDst++ = (*pSrc++) * scale;
+    *pDst++ = (*pSrc++) * scale;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the result in the destination buffer. */
+    *pDst++ = (*pSrc++) * scale;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of scale group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c
new file mode 100644
index 0000000..5e4615f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_scale_q15.c   
+*   
+* Description:	Multiplies a Q15 vector by a scalar.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup scale   
+ * @{   
+ */
+
+/**   
+ * @brief Multiplies a Q15 vector by a scalar.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       scaleFract fractional portion of the scale value   
+ * @param[in]       shift number of bits to shift the result by   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in the vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The input data *pSrc and scaleFract are in 1.15 format.   
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.   
+ */
+
+
+void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  int8_t kShift = 15 - shift;                    /* shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t in1, in2;                                /* Temporary variables */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Reading 2 inputs from memory */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    /* C = A * scale */
+    /* Scale the inputs and then store the 2 results in the destination buffer   
+     * in single cycle by packing the outputs */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((in1 * scaleFract) >> kShift, 16),
+              __SSAT((in2 * scaleFract) >> kShift, 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((in2 * scaleFract) >> kShift, 16),
+              __SSAT((in1 * scaleFract) >> kShift, 16), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((in1 * scaleFract) >> kShift, 16),
+              __SSAT((in2 * scaleFract) >> kShift, 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((in2 * scaleFract) >> kShift, 16),
+              __SSAT((in1 * scaleFract) >> kShift, 16), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the result in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the result in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of scale group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c
new file mode 100644
index 0000000..1b2b7de
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c
@@ -0,0 +1,117 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_scale_q31.c   
+*   
+* Description:	Multiplies a Q31 vector by a scalar.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup scale   
+ * @{   
+ */
+
+/**   
+ * @brief Multiplies a Q31 vector by a scalar.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       scaleFract fractional portion of the scale value   
+ * @param[in]       shift number of bits to shift the result by   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in the vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The input data *pSrc and scaleFract are in 1.31 format.   
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.   
+ */
+
+void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  int8_t kShift = 31 - shift;                    /* Shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the results in the destination buffer. */
+    *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift);
+    *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift);
+    *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift);
+    *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the result in the destination buffer. */
+    *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of scale group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c
new file mode 100644
index 0000000..f058b0e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_scale_q7.c   
+*   
+* Description:	Multiplies a Q7 vector by a scalar.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup scale   
+ * @{   
+ */
+
+/**   
+ * @brief Multiplies a Q7 vector by a scalar.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       scaleFract fractional portion of the scale value   
+ * @param[in]       shift number of bits to shift the result by   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in the vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The input data *pSrc and scaleFract are in 1.7 format.   
+ * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format.   
+ */
+
+void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  int8_t kShift = 7 - shift;                     /* shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q7_t in1, in2, in3, in4, out1, out2, out3, out4;      /* Temporary variables to store input & output */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Reading 4 inputs from memory */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    in3 = *pSrc++;
+    in4 = *pSrc++;
+
+    /* C = A * scale */
+    /* Scale the inputs and then store the results in the temporary variables. */
+    out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8));
+    out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8));
+    out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8));
+    out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8));
+
+    /* Packing the individual outputs into 32bit and storing in   
+     * destination buffer in single write */
+    *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the result in the destination buffer. */
+    *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A * scale */
+    /* Scale the input and then store the result in the destination buffer. */
+    *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of scale group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c
new file mode 100644
index 0000000..70a80c2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_shift_q15.c   
+*   
+* Description:	Shifts the elements of a Q15 vector by a specified number of bits.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup shift   
+ * @{   
+ */
+
+/**   
+ * @brief  Shifts the elements of a Q15 vector a specified number of bits.   
+ * @param[in]  *pSrc points to the input vector   
+ * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.   
+ * @param[out]  *pDst points to the output vector   
+ * @param[in]  blockSize number of samples in the vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ */
+
+void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  uint8_t sign;                                  /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t in1, in2;                                /* Temporary variables */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Getting the sign of shiftBits */
+  sign = (shiftBits & 0x80);
+
+  /* If the shift value is positive then do right shift else left shift */
+  if(sign == 0u)
+  {
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* Read 2 inputs */
+      in1 = *pSrc++;
+      in2 = *pSrc++;
+      /* C = A << shiftBits */
+      /* Shift the inputs and then store the results in the destination buffer. */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
+                                  __SSAT((in2 << shiftBits), 16), 16);
+
+#else
+
+      *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
+                                  __SSAT((in1 << shiftBits), 16), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      in1 = *pSrc++;
+      in2 = *pSrc++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
+                                  __SSAT((in2 << shiftBits), 16), 16);
+
+#else
+
+      *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
+                                  __SSAT((in1 << shiftBits), 16), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A << shiftBits */
+      /* Shift and then store the results in the destination buffer. */
+      *pDst++ = __SSAT((*pSrc++ << shiftBits), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* Read 2 inputs */
+      in1 = *pSrc++;
+      in2 = *pSrc++;
+      /* C = A >> shiftBits */
+      /* Shift the inputs and then store the results in the destination buffer. */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
+                                  (in2 >> -shiftBits), 16);
+
+#else
+
+      *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
+                                  (in1 >> -shiftBits), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      in1 = *pSrc++;
+      in2 = *pSrc++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
+                                  (in2 >> -shiftBits), 16);
+
+#else
+
+      *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
+                                  (in1 >> -shiftBits), 16);
+
+#endif /* #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A >> shiftBits */
+      /* Shift the inputs and then store the results in the destination buffer. */
+      *pDst++ = (*pSrc++ >> -shiftBits);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Getting the sign of shiftBits */
+  sign = (shiftBits & 0x80);
+
+  /* If the shift value is positive then do right shift else left shift */
+  if(sign == 0u)
+  {
+    /* Initialize blkCnt with number of samples */
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A << shiftBits */
+      /* Shift and then store the results in the destination buffer. */
+      *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* Initialize blkCnt with number of samples */
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A >> shiftBits */
+      /* Shift the inputs and then store the results in the destination buffer. */
+      *pDst++ = (*pSrc++ >> -shiftBits);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of shift group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c
new file mode 100644
index 0000000..81f45bd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_shift_q31.c   
+*   
+* Description:	Shifts the elements of a Q31 vector by a specified number of bits.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+/**   
+ * @defgroup shift Vector Shift   
+ *   
+ * Shifts the elements of a fixed-point vector by a specified number of bits.   
+ * There are separate functions for Q7, Q15, and Q31 data types.   
+ * The underlying algorithm used is:   
+ *   
+ * 
   
+ *     pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.   
+ * 
   
+ *   
+ * If shift is positive then the elements of the vector are shifted to the left.   
+ * If shift is negative then the elements of the vector are shifted to the right.   
+ */
+
+/**   
+ * @addtogroup shift   
+ * @{   
+ */
+
+/**   
+ * @brief  Shifts the elements of a Q31 vector a specified number of bits.   
+ * @param[in]  *pSrc points to the input vector   
+ * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.   
+ * @param[out]  *pDst points to the output vector   
+ * @param[in]  blockSize number of samples in the vector   
+ * @return none.   
+ *   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.   
+ */
+
+void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  uint8_t sign;                                  /* Sign of shiftBits */
+  /* Getting the sign of shiftBits */
+  sign = (shiftBits & 0x80);
+
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A (>> or <<) shiftBits */
+    /* Shift the input and then store the results in the destination buffer. */
+    *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) :
+      (*pSrc++ >> -shiftBits);
+    *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) :
+      (*pSrc++ >> -shiftBits);
+    *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) :
+      (*pSrc++ >> -shiftBits);
+    *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) :
+      (*pSrc++ >> -shiftBits);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A (>> or <<) shiftBits */
+    /* Shift the input and then store the result in the destination buffer. */
+    *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) :
+      (*pSrc++ >> -shiftBits);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of shift group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c
new file mode 100644
index 0000000..cf13ef3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c
@@ -0,0 +1,202 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_shift_q7.c   
+*   
+* Description:	Processing function for the Q7 Shifting   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup shift   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Shifts the elements of a Q7 vector a specified number of bits.   
+ * @param[in]  *pSrc points to the input vector   
+ * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.   
+ * @param[out]  *pDst points to the output vector   
+ * @param[in]  blockSize number of samples in the vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated.   
+ */
+
+void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+  uint8_t sign;                                  /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  q7_t in1;                                      /* Input value1 */
+  q7_t in2;                                      /* Input value2 */
+  q7_t in3;                                      /* Input value3 */
+  q7_t in4;                                      /* Input value4 */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Getting the sign of shiftBits */
+  sign = (shiftBits & 0x80);
+
+  /* If the shift value is positive then do right shift else left shift */
+  if(sign == 0u)
+  {
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C = A << shiftBits */
+      /* Read 4 inputs */
+      in1 = *pSrc++;
+      in2 = *pSrc++;
+      in3 = *pSrc++;
+      in4 = *pSrc++;
+
+      /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
+      *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8),
+                                   __SSAT((in2 << shiftBits), 8),
+                                   __SSAT((in3 << shiftBits), 8),
+                                   __SSAT((in4 << shiftBits), 8));
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A << shiftBits */
+      /* Shift the input and then store the result in the destination buffer. */
+      *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C = A >> shiftBits */
+      /* Read 4 inputs */
+      in1 = *pSrc++;
+      in2 = *pSrc++;
+      in3 = *pSrc++;
+      in4 = *pSrc++;
+
+      /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
+      *__SIMD32(pDst)++ = __PACKq7((in1 >> -shiftBits), (in2 >> -shiftBits),
+                                   (in3 >> -shiftBits), (in4 >> -shiftBits));
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A >> shiftBits */
+      /* Shift the input and then store the result in the destination buffer. */
+      *pDst++ = (*pSrc++ >> -shiftBits);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Getting the sign of shiftBits */
+  sign = (shiftBits & 0x80);
+
+  /* If the shift value is positive then do right shift else left shift */
+  if(sign == 0u)
+  {
+    /* Initialize blkCnt with number of samples */
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A << shiftBits */
+      /* Shift the input and then store the result in the destination buffer. */
+      *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* Initialize blkCnt with number of samples */
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* C = A >> shiftBits */
+      /* Shift the input and then store the result in the destination buffer. */
+      *pDst++ = (*pSrc++ >> -shiftBits);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of shift group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c
new file mode 100644
index 0000000..3ec5c74
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sub_f32.c   
+*   
+* Description:	Floating-point vector subtraction.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @defgroup BasicSub Vector Subtraction   
+ *   
+ * Element-by-element subtraction of two vectors.   
+ *   
+ * 
   
+ *     pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.   
+ * 
   
+ *   
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup BasicSub   
+ * @{   
+ */
+
+
+/**   
+ * @brief Floating-point vector subtraction.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ */
+
+void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the results in the destination buffer. */
+    *pDst++ = (*pSrcA++) - (*pSrcB++);
+    *pDst++ = (*pSrcA++) - (*pSrcB++);
+    *pDst++ = (*pSrcA++) - (*pSrcB++);
+    *pDst++ = (*pSrcA++) - (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the results in the destination buffer. */
+    *pDst++ = (*pSrcA++) - (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicSub group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c
new file mode 100644
index 0000000..6d170e2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sub_q15.c   
+*   
+* Description:	Q15 vector subtraction.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup BasicSub   
+ * @{   
+ */
+
+/**   
+ * @brief Q15 vector subtraction.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ */
+
+void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the results in the destination buffer two samples at a time. */
+    *__SIMD32(pDst)++ = __QSUB16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+    *__SIMD32(pDst)++ = __QSUB16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the result in the destination buffer. */
+    *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the result in the destination buffer. */
+    *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+}
+
+/**   
+ * @} end of BasicSub group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c
new file mode 100644
index 0000000..489a28f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c
@@ -0,0 +1,125 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sub_q31.c   
+*   
+* Description:	Q31 vector subtraction.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup BasicSub   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 vector subtraction.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.   
+ */
+
+void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the results in the destination buffer. */
+    *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+    *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+    *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+    *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the result in the destination buffer. */
+    *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the result in the destination buffer. */
+    *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of BasicSub group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c
new file mode 100644
index 0000000..f1bb2c6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sub_q7.c   
+*   
+* Description:	Q7 vector subtraction.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMath   
+ */
+
+/**   
+ * @addtogroup BasicSub   
+ * @{   
+ */
+
+/**   
+ * @brief Q7 vector subtraction.   
+ * @param[in]       *pSrcA points to the first input vector   
+ * @param[in]       *pSrcB points to the second input vector   
+ * @param[out]      *pDst points to the output vector   
+ * @param[in]       blockSize number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.   
+ */
+
+void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the results in the destination buffer 4 samples at a time. */
+    *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the result in the destination buffer. */
+    *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initialize blkCnt with number of samples */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A - B */
+    /* Subtract and then store the result in the destination buffer. */
+    *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+}
+
+/**   
+ * @} end of BasicSub group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c
new file mode 100644
index 0000000..6193158
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c
@@ -0,0 +1,257 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2011 ARM Limited. All rights reserved.   
+*   
+* $Date:        17. August 2011  
+* $Revision: 	V1.0.11  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_common_tables.c   
+*   
+* Description:	This file has common tables like Bitreverse, reciprocal etc which are used across different functions   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Version 1.0.11 2011/08/17 
+*    Updated Bit Reversal table to support 4096 CFFT length.  
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/**   
+* \par   
+* Pseudo code for Generation of Bit reversal Table is   
+* \par   
+* 
for(l=1;l <= N/4;l++)   
+* {   
+*   for(i=0;i> 1;   
+*  } 
   
+* \par   
+* where N = 1024	logN2 = 10   
+* \par   
+* N is the maximum FFT Size supported   
+*/
+
+/*   
+* @brief  Table for bit reversal process   
+*/
+uint16_t armBitRevTable[1024] = {
+  0x400,  0x200,  0x600,  0x100,  0x500,  0x300,  0x700,  
+0x80,  0x480,  0x280,  0x680,  0x180,  0x580,  0x380,  
+0x780,  0x40,  0x440,  0x240,  0x640,  0x140,  0x540,  
+0x340,  0x740,  0xc0,  0x4c0,  0x2c0,  0x6c0,  0x1c0,  
+0x5c0,  0x3c0,  0x7c0,  0x20,  0x420,  0x220,  0x620,  
+0x120,  0x520,  0x320,  0x720,  0xa0,  0x4a0,  0x2a0,  
+0x6a0,  0x1a0,  0x5a0,  0x3a0,  0x7a0,  0x60,  0x460,  
+0x260,  0x660,  0x160,  0x560,  0x360,  0x760,  0xe0,  
+0x4e0,  0x2e0,  0x6e0,  0x1e0,  0x5e0,  0x3e0,  0x7e0,  
+0x10,  0x410,  0x210,  0x610,  0x110,  0x510,  0x310,  
+0x710,  0x90,  0x490,  0x290,  0x690,  0x190,  0x590,  
+0x390,  0x790,  0x50,  0x450,  0x250,  0x650,  0x150,  
+0x550,  0x350,  0x750,  0xd0,  0x4d0,  0x2d0,  0x6d0,  
+0x1d0,  0x5d0,  0x3d0,  0x7d0,  0x30,  0x430,  0x230,  
+0x630,  0x130,  0x530,  0x330,  0x730,  0xb0,  0x4b0,  
+0x2b0,  0x6b0,  0x1b0,  0x5b0,  0x3b0,  0x7b0,  0x70,  
+0x470,  0x270,  0x670,  0x170,  0x570,  0x370,  0x770,  
+0xf0,  0x4f0,  0x2f0,  0x6f0,  0x1f0,  0x5f0,  0x3f0,  
+0x7f0,  0x8,  0x408,  0x208,  0x608,  0x108,  0x508,  
+0x308,  0x708,  0x88,  0x488,  0x288,  0x688,  0x188,  
+0x588,  0x388,  0x788,  0x48,  0x448,  0x248,  0x648,  
+0x148,  0x548,  0x348,  0x748,  0xc8,  0x4c8,  0x2c8,  
+0x6c8,  0x1c8,  0x5c8,  0x3c8,  0x7c8,  0x28,  0x428,  
+0x228,  0x628,  0x128,  0x528,  0x328,  0x728,  0xa8,  
+0x4a8,  0x2a8,  0x6a8,  0x1a8,  0x5a8,  0x3a8,  0x7a8,  
+0x68,  0x468,  0x268,  0x668,  0x168,  0x568,  0x368,  
+0x768,  0xe8,  0x4e8,  0x2e8,  0x6e8,  0x1e8,  0x5e8,  
+0x3e8,  0x7e8,  0x18,  0x418,  0x218,  0x618,  0x118,  
+0x518,  0x318,  0x718,  0x98,  0x498,  0x298,  0x698,  
+0x198,  0x598,  0x398,  0x798,  0x58,  0x458,  0x258,  
+0x658,  0x158,  0x558,  0x358,  0x758,  0xd8,  0x4d8,  
+0x2d8,  0x6d8,  0x1d8,  0x5d8,  0x3d8,  0x7d8,  0x38,  
+0x438,  0x238,  0x638,  0x138,  0x538,  0x338,  0x738,  
+0xb8,  0x4b8,  0x2b8,  0x6b8,  0x1b8,  0x5b8,  0x3b8,  
+0x7b8,  0x78,  0x478,  0x278,  0x678,  0x178,  0x578,  
+0x378,  0x778,  0xf8,  0x4f8,  0x2f8,  0x6f8,  0x1f8,  
+0x5f8,  0x3f8,  0x7f8,  0x4,  0x404,  0x204,  0x604,  
+0x104,  0x504,  0x304,  0x704,  0x84,  0x484,  0x284,  
+0x684,  0x184,  0x584,  0x384,  0x784,  0x44,  0x444,  
+0x244,  0x644,  0x144,  0x544,  0x344,  0x744,  0xc4,  
+0x4c4,  0x2c4,  0x6c4,  0x1c4,  0x5c4,  0x3c4,  0x7c4,  
+0x24,  0x424,  0x224,  0x624,  0x124,  0x524,  0x324,  
+0x724,  0xa4,  0x4a4,  0x2a4,  0x6a4,  0x1a4,  0x5a4,  
+0x3a4,  0x7a4,  0x64,  0x464,  0x264,  0x664,  0x164,  
+0x564,  0x364,  0x764,  0xe4,  0x4e4,  0x2e4,  0x6e4,  
+0x1e4,  0x5e4,  0x3e4,  0x7e4,  0x14,  0x414,  0x214,  
+0x614,  0x114,  0x514,  0x314,  0x714,  0x94,  0x494,  
+0x294,  0x694,  0x194,  0x594,  0x394,  0x794,  0x54,  
+0x454,  0x254,  0x654,  0x154,  0x554,  0x354,  0x754,  
+0xd4,  0x4d4,  0x2d4,  0x6d4,  0x1d4,  0x5d4,  0x3d4,  
+0x7d4,  0x34,  0x434,  0x234,  0x634,  0x134,  0x534,  
+0x334,  0x734,  0xb4,  0x4b4,  0x2b4,  0x6b4,  0x1b4,  
+0x5b4,  0x3b4,  0x7b4,  0x74,  0x474,  0x274,  0x674,  
+0x174,  0x574,  0x374,  0x774,  0xf4,  0x4f4,  0x2f4,  
+0x6f4,  0x1f4,  0x5f4,  0x3f4,  0x7f4,  0xc,  0x40c,  
+0x20c,  0x60c,  0x10c,  0x50c,  0x30c,  0x70c,  0x8c,  
+0x48c,  0x28c,  0x68c,  0x18c,  0x58c,  0x38c,  0x78c,  
+0x4c,  0x44c,  0x24c,  0x64c,  0x14c,  0x54c,  0x34c,  
+0x74c,  0xcc,  0x4cc,  0x2cc,  0x6cc,  0x1cc,  0x5cc,  
+0x3cc,  0x7cc,  0x2c,  0x42c,  0x22c,  0x62c,  0x12c,  
+0x52c,  0x32c,  0x72c,  0xac,  0x4ac,  0x2ac,  0x6ac,  
+0x1ac,  0x5ac,  0x3ac,  0x7ac,  0x6c,  0x46c,  0x26c,  
+0x66c,  0x16c,  0x56c,  0x36c,  0x76c,  0xec,  0x4ec,  
+0x2ec,  0x6ec,  0x1ec,  0x5ec,  0x3ec,  0x7ec,  0x1c,  
+0x41c,  0x21c,  0x61c,  0x11c,  0x51c,  0x31c,  0x71c,  
+0x9c,  0x49c,  0x29c,  0x69c,  0x19c,  0x59c,  0x39c,  
+0x79c,  0x5c,  0x45c,  0x25c,  0x65c,  0x15c,  0x55c,  
+0x35c,  0x75c,  0xdc,  0x4dc,  0x2dc,  0x6dc,  0x1dc,  
+0x5dc,  0x3dc,  0x7dc,  0x3c,  0x43c,  0x23c,  0x63c,  
+0x13c,  0x53c,  0x33c,  0x73c,  0xbc,  0x4bc,  0x2bc,  
+0x6bc,  0x1bc,  0x5bc,  0x3bc,  0x7bc,  0x7c,  0x47c,  
+0x27c,  0x67c,  0x17c,  0x57c,  0x37c,  0x77c,  0xfc,  
+0x4fc,  0x2fc,  0x6fc,  0x1fc,  0x5fc,  0x3fc,  0x7fc,  
+0x2,  0x402,  0x202,  0x602,  0x102,  0x502,  0x302,  
+0x702,  0x82,  0x482,  0x282,  0x682,  0x182,  0x582,  
+0x382,  0x782,  0x42,  0x442,  0x242,  0x642,  0x142,  
+0x542,  0x342,  0x742,  0xc2,  0x4c2,  0x2c2,  0x6c2,  
+0x1c2,  0x5c2,  0x3c2,  0x7c2,  0x22,  0x422,  0x222,  
+0x622,  0x122,  0x522,  0x322,  0x722,  0xa2,  0x4a2,  
+0x2a2,  0x6a2,  0x1a2,  0x5a2,  0x3a2,  0x7a2,  0x62,  
+0x462,  0x262,  0x662,  0x162,  0x562,  0x362,  0x762,  
+0xe2,  0x4e2,  0x2e2,  0x6e2,  0x1e2,  0x5e2,  0x3e2,  
+0x7e2,  0x12,  0x412,  0x212,  0x612,  0x112,  0x512,  
+0x312,  0x712,  0x92,  0x492,  0x292,  0x692,  0x192,  
+0x592,  0x392,  0x792,  0x52,  0x452,  0x252,  0x652,  
+0x152,  0x552,  0x352,  0x752,  0xd2,  0x4d2,  0x2d2,  
+0x6d2,  0x1d2,  0x5d2,  0x3d2,  0x7d2,  0x32,  0x432,  
+0x232,  0x632,  0x132,  0x532,  0x332,  0x732,  0xb2,  
+0x4b2,  0x2b2,  0x6b2,  0x1b2,  0x5b2,  0x3b2,  0x7b2,  
+0x72,  0x472,  0x272,  0x672,  0x172,  0x572,  0x372,  
+0x772,  0xf2,  0x4f2,  0x2f2,  0x6f2,  0x1f2,  0x5f2,  
+0x3f2,  0x7f2,  0xa,  0x40a,  0x20a,  0x60a,  0x10a,  
+0x50a,  0x30a,  0x70a,  0x8a,  0x48a,  0x28a,  0x68a,  
+0x18a,  0x58a,  0x38a,  0x78a,  0x4a,  0x44a,  0x24a,  
+0x64a,  0x14a,  0x54a,  0x34a,  0x74a,  0xca,  0x4ca,  
+0x2ca,  0x6ca,  0x1ca,  0x5ca,  0x3ca,  0x7ca,  0x2a,  
+0x42a,  0x22a,  0x62a,  0x12a,  0x52a,  0x32a,  0x72a,  
+0xaa,  0x4aa,  0x2aa,  0x6aa,  0x1aa,  0x5aa,  0x3aa,  
+0x7aa,  0x6a,  0x46a,  0x26a,  0x66a,  0x16a,  0x56a,  
+0x36a,  0x76a,  0xea,  0x4ea,  0x2ea,  0x6ea,  0x1ea,  
+0x5ea,  0x3ea,  0x7ea,  0x1a,  0x41a,  0x21a,  0x61a,  
+0x11a,  0x51a,  0x31a,  0x71a,  0x9a,  0x49a,  0x29a,  
+0x69a,  0x19a,  0x59a,  0x39a,  0x79a,  0x5a,  0x45a,  
+0x25a,  0x65a,  0x15a,  0x55a,  0x35a,  0x75a,  0xda,  
+0x4da,  0x2da,  0x6da,  0x1da,  0x5da,  0x3da,  0x7da,  
+0x3a,  0x43a,  0x23a,  0x63a,  0x13a,  0x53a,  0x33a,  
+0x73a,  0xba,  0x4ba,  0x2ba,  0x6ba,  0x1ba,  0x5ba,  
+0x3ba,  0x7ba,  0x7a,  0x47a,  0x27a,  0x67a,  0x17a,  
+0x57a,  0x37a,  0x77a,  0xfa,  0x4fa,  0x2fa,  0x6fa,  
+0x1fa,  0x5fa,  0x3fa,  0x7fa,  0x6,  0x406,  0x206,  
+0x606,  0x106,  0x506,  0x306,  0x706,  0x86,  0x486,  
+0x286,  0x686,  0x186,  0x586,  0x386,  0x786,  0x46,  
+0x446,  0x246,  0x646,  0x146,  0x546,  0x346,  0x746,  
+0xc6,  0x4c6,  0x2c6,  0x6c6,  0x1c6,  0x5c6,  0x3c6,  
+0x7c6,  0x26,  0x426,  0x226,  0x626,  0x126,  0x526,  
+0x326,  0x726,  0xa6,  0x4a6,  0x2a6,  0x6a6,  0x1a6,  
+0x5a6,  0x3a6,  0x7a6,  0x66,  0x466,  0x266,  0x666,  
+0x166,  0x566,  0x366,  0x766,  0xe6,  0x4e6,  0x2e6,  
+0x6e6,  0x1e6,  0x5e6,  0x3e6,  0x7e6,  0x16,  0x416,  
+0x216,  0x616,  0x116,  0x516,  0x316,  0x716,  0x96,  
+0x496,  0x296,  0x696,  0x196,  0x596,  0x396,  0x796,  
+0x56,  0x456,  0x256,  0x656,  0x156,  0x556,  0x356,  
+0x756,  0xd6,  0x4d6,  0x2d6,  0x6d6,  0x1d6,  0x5d6,  
+0x3d6,  0x7d6,  0x36,  0x436,  0x236,  0x636,  0x136,  
+0x536,  0x336,  0x736,  0xb6,  0x4b6,  0x2b6,  0x6b6,  
+0x1b6,  0x5b6,  0x3b6,  0x7b6,  0x76,  0x476,  0x276,  
+0x676,  0x176,  0x576,  0x376,  0x776,  0xf6,  0x4f6,  
+0x2f6,  0x6f6,  0x1f6,  0x5f6,  0x3f6,  0x7f6,  0xe,  
+0x40e,  0x20e,  0x60e,  0x10e,  0x50e,  0x30e,  0x70e,  
+0x8e,  0x48e,  0x28e,  0x68e,  0x18e,  0x58e,  0x38e,  
+0x78e,  0x4e,  0x44e,  0x24e,  0x64e,  0x14e,  0x54e,  
+0x34e,  0x74e,  0xce,  0x4ce,  0x2ce,  0x6ce,  0x1ce,  
+0x5ce,  0x3ce,  0x7ce,  0x2e,  0x42e,  0x22e,  0x62e,  
+0x12e,  0x52e,  0x32e,  0x72e,  0xae,  0x4ae,  0x2ae,  
+0x6ae,  0x1ae,  0x5ae,  0x3ae,  0x7ae,  0x6e,  0x46e,  
+0x26e,  0x66e,  0x16e,  0x56e,  0x36e,  0x76e,  0xee,  
+0x4ee,  0x2ee,  0x6ee,  0x1ee,  0x5ee,  0x3ee,  0x7ee,  
+0x1e,  0x41e,  0x21e,  0x61e,  0x11e,  0x51e,  0x31e,  
+0x71e,  0x9e,  0x49e,  0x29e,  0x69e,  0x19e,  0x59e,  
+0x39e,  0x79e,  0x5e,  0x45e,  0x25e,  0x65e,  0x15e,  
+0x55e,  0x35e,  0x75e,  0xde,  0x4de,  0x2de,  0x6de,  
+0x1de,  0x5de,  0x3de,  0x7de,  0x3e,  0x43e,  0x23e,  
+0x63e,  0x13e,  0x53e,  0x33e,  0x73e,  0xbe,  0x4be,  
+0x2be,  0x6be,  0x1be,  0x5be,  0x3be,  0x7be,  0x7e,  
+0x47e,  0x27e,  0x67e,  0x17e,  0x57e,  0x37e,  0x77e,  
+0xfe,  0x4fe,  0x2fe,  0x6fe,  0x1fe,  0x5fe,  0x3fe,  
+0x7fe,  0x1
+};
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
+
+/*   
+* @brief  Q15 table for reciprocal   
+*/
+const q15_t armRecipTableQ15[64] = {
+  0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0,
+  0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82,
+  0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484,
+  0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0,
+  0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E,
+  0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255,
+  0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6,
+  0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978,
+  0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8,
+  0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255,
+  0x41CC, 0x4146, 0x40C2, 0x4040
+};
+
+/*   
+* @brief  Q31 table for reciprocal   
+*/
+const q31_t armRecipTableQ31[64] = {
+  0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928,
+  0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3,
+  0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519,
+  0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB,
+  0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318,
+  0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0,
+  0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D,
+  0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96,
+  0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2,
+  0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426,
+  0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102
+};
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
new file mode 100644
index 0000000..4623357
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_conj_f32.c   
+*   
+* Description:	Floating-point complex conjugate.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup cmplx_conj Complex Conjugate   
+ *   
+ * Conjugates the elements of a complex data vector.   
+ *  
+ * The pSrc points to the source data and   
+ * pDst points to the where the result should be written.   
+ * numSamples specifies the number of complex samples   
+ * and the data in each array is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * Each array has a total of 2*numSamples values.   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup cmplx_conj   
+ * @{   
+ */
+
+/**   
+ * @brief  Floating-point complex conjugate.   
+ * @param  *pSrc points to the input vector   
+ * @param  *pDst points to the output vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @return none.   
+ */
+
+void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut + j (imagOut) = realIn + j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_conj group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
new file mode 100644
index 0000000..5c4c389
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_conj_q15.c   
+*   
+* Description:	Q15 complex conjugate.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_conj   
+ * @{   
+ */
+
+/**   
+ * @brief  Q15 complex conjugate.   
+ * @param  *pSrc points to the input vector   
+ * @param  *pDst points to the output vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.   
+ */
+
+void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_conj group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
new file mode 100644
index 0000000..b139ea2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_conj_q31.c   
+*   
+* Description:	Q31 complex conjugate.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_conj   
+ * @{   
+ */
+
+/**   
+ * @brief  Q31 complex conjugate.   
+ * @param  *pSrc points to the input vector   
+ * @param  *pDst points to the output vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.   
+ */
+
+void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in;                                      /* Input value */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_conj group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
new file mode 100644
index 0000000..90b8a8b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_dot_prod_f32.c   
+*   
+* Description:	Floating-point complex dot product   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup cmplx_dot_prod Complex Dot Product   
+ *   
+ * Computes the dot product of two complex vectors.   
+ * The vectors are multiplied element-by-element and then summed.   
+ *  
+ * The pSrcA points to the first complex input vector and   
+ * pSrcB points to the second complex input vector.   
+ * numSamples specifies the number of complex samples   
+ * and the data in each array is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * Each array has a total of 2*numSamples values.   
+ *   
+ * The underlying algorithm is used:   
+ * 
   
+ * realResult=0;   
+ * imagResult=0;   
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup cmplx_dot_prod   
+ * @{   
+ */
+
+/**   
+ * @brief  Floating-point complex dot product   
+ * @param  *pSrcA points to the first input vector   
+ * @param  *pSrcB points to the second input vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @param  *realResult real part of the result returned here   
+ * @param  *imagResult imaginary part of the result returned here   
+ * @return none.   
+ */
+
+void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult)
+{
+  float32_t real_sum = 0.0f, imag_sum = 0.0f;    /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the real and imaginary results in the destination buffers */
+  *realResult = real_sum;
+  *imagResult = imag_sum;
+}
+
+/**   
+ * @} end of cmplx_dot_prod group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
new file mode 100644
index 0000000..2e341bf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_dot_prod_q15.c   
+*   
+* Description:	Processing function for the Q15 Complex Dot product   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_dot_prod   
+ * @{   
+ */
+
+/**   
+ * @brief  Q15 complex dot product   
+ * @param  *pSrcA points to the first input vector   
+ * @param  *pSrcB points to the second input vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @param  *realResult real part of the result returned here   
+ * @param  *imagResult imaginary part of the result returned here   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.   
+ * These are accumulated in a 64-bit accumulator with 34.30 precision.   
+ * As a final step, the accumulators are converted to 8.24 format.   
+ * The return results realResult and imagResult are in 8.24 format.   
+ */
+
+void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult)
+{
+  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the real and imaginary results in 8.24 format  */
+  /* Convert real data in 34.30 to 8.24 by 6 right shifts */
+  *realResult = (q31_t) (real_sum) >> 6;
+  /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
+  *imagResult = (q31_t) (imag_sum) >> 6;
+}
+
+/**   
+ * @} end of cmplx_dot_prod group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
new file mode 100644
index 0000000..30ee59c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_dot_prod_q31.c   
+*   
+* Description:	Q31 complex dot product   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_dot_prod   
+ * @{   
+ */
+
+/**   
+ * @brief  Q31 complex dot product   
+ * @param  *pSrcA points to the first input vector   
+ * @param  *pSrcB points to the second input vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @param  *realResult real part of the result returned here   
+ * @param  *imagResult imaginary part of the result returned here   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.   
+ * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.   
+ * Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768.   
+ * The return results realResult and imagResult are in 16.48 format.   
+ * Input down scaling is not required.   
+ */
+
+void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult)
+{
+  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    /* Convert real data in 2.62 to 16.48 by 14 right shifts */
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    /* Convert imag data in 2.62 to 16.48 by 14 right shifts */
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples  is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* outReal = realA[0]* realB[0] + realA[2]* realB[2] + realA[4]* realB[4] + .....+ realA[numSamples-2]* realB[numSamples-2] */
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    /* outImag = imagA[1]* imagB[1] + imagA[3]* imagB[3] + imagA[5]* imagB[5] + .....+ imagA[numSamples-1]* imagB[numSamples-1] */
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the real and imaginary results in 16.48 format  */
+  *realResult = real_sum;
+  *imagResult = imag_sum;
+}
+
+/**   
+ * @} end of cmplx_dot_prod group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
new file mode 100644
index 0000000..e84195e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_f32.c   
+*   
+* Description:	Floating-point complex magnitude.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup cmplx_mag Complex Magnitude   
+ *   
+ * Computes the magnitude of the elements of a complex data vector.   
+ *  
+ * The pSrc points to the source data and   
+ * pDst points to the where the result should be written.   
+ * numSamples specifies the number of complex samples   
+ * in the input array and the data is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * The input array has a total of 2*numSamples values;   
+ * the output array has a total of numSamples values.   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup cmplx_mag   
+ * @{   
+ */
+/**   
+ * @brief Floating-point complex magnitude.   
+ * @param[in]       *pSrc points to complex input buffer   
+ * @param[out]      *pDst points to real output buffer   
+ * @param[in]       numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ */
+
+
+void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t realIn, imagIn;                      /* Temporary variables to hold input values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = sqrt((real * real) + (imag * imag)) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
new file mode 100644
index 0000000..6f5f7e0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_q15.c   
+*   
+* Description:	Q15 complex magnitude.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_mag   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q15 complex magnitude   
+ * @param  *pSrc points to the complex input vector   
+ * @param  *pDst points to the real output vector   
+ * @param  numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.   
+ */
+
+void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q15_t real, imag;                              /* Temporary variables to hold input values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = sqrt(real * real + imag * imag) */
+    real = *pSrc++;
+    imag = *pSrc++;
+
+    acc0 = (real * real);
+    acc1 = (imag * imag);
+
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
new file mode 100644
index 0000000..07b683d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_q31.c   
+*   
+* Description:	Q31 complex magnitude   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_mag   
+ * @{   
+ */
+
+/**   
+ * @brief  Q31 complex magnitude   
+ * @param  *pSrc points to the complex input vector   
+ * @param  *pDst points to the real output vector   
+ * @param  numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.   
+ * Input down scaling is not required.   
+ */
+
+void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t real, imag;                              /* Temporary variables to hold input values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = sqrt((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
new file mode 100644
index 0000000..87b89de
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
@@ -0,0 +1,155 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_squared_f32.c   
+*   
+* Description:	Floating-point complex magnitude squared.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup cmplx_mag_squared Complex Magnitude Squared   
+ *   
+ * Computes the magnitude squared of the elements of a complex data vector.   
+ *  
+ * The pSrc points to the source data and   
+ * pDst points to the where the result should be written.   
+ * numSamples specifies the number of complex samples   
+ * in the input array and the data is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * The input array has a total of 2*numSamples values;   
+ * the output array has a total of numSamples values.   
+ *   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup cmplx_mag_squared   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Floating-point complex magnitude squared   
+ * @param[in]  *pSrc points to the complex input vector   
+ * @param[out]  *pDst points to the real output vector   
+ * @param[in]  numSamples number of complex samples in the input vector   
+ * @return none.   
+ */
+
+void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t real, imag;                          /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    /* store the result in the destination buffer. */
+    *pDst++ = (real * real) + (imag * imag);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    *pDst++ = (real * real) + (imag * imag);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    *pDst++ = (real * real) + (imag * imag);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    *pDst++ = (real * real) + (imag * imag);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    /* store the result in the destination buffer. */
+    *pDst++ = (real * real) + (imag * imag);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* reading real and imaginary values */
+    real = *pSrc++;
+    imag = *pSrc++;
+
+    /* out = (real * real) + (imag * imag) */
+    /* store the result in the destination buffer. */
+    *pDst++ = (real * real) + (imag * imag);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag_squared group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
new file mode 100644
index 0000000..31fb79d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_squared_q15.c   
+*   
+* Description:	Q15 complex magnitude squared.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_mag_squared   
+ * @{   
+ */
+
+/**   
+ * @brief  Q15 complex magnitude squared   
+ * @param  *pSrc points to the complex input vector   
+ * @param  *pDst points to the real output vector   
+ * @param  numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.   
+ */
+
+void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q15_t real, imag;                              /* Temporary variables to store real and imaginary values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = ((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (real * real);
+    acc1 = (imag * imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag_squared group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
new file mode 100644
index 0000000..807632e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_squared_q31.c   
+*   
+* Description:	Q31 complex magnitude squared.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_mag_squared   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q31 complex magnitude squared   
+ * @param  *pSrc points to the complex input vector   
+ * @param  *pDst points to the real output vector   
+ * @param  numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.   
+ * Input down scaling is not required.   
+ */
+
+void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t real, imag;                              /* Temporary variables to store real and imaginary values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = ((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag_squared group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
new file mode 100644
index 0000000..4cdda32
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
@@ -0,0 +1,180 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_cmplx_f32.c   
+*   
+* Description:	Floating-point complex-by-complex multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication   
+ *   
+ * Multiplies a complex vector by another complex vector and generates a complex result.   
+ * The data in the complex arrays is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * The parameter numSamples represents the number of complex   
+ * samples processed.  The complex arrays have a total of 2*numSamples   
+ * real values.   
+ *   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup CmplxByCmplxMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Floating-point complex-by-complex multiplication   
+ * @param[in]  *pSrcA points to the first input vector   
+ * @param[in]  *pSrcB points to the second input vector   
+ * @param[out]  *pDst  points to the output vector   
+ * @param[in]  numSamples number of complex samples in each vector   
+ * @return none.   
+ */
+
+void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t a, b, c, d;                          /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in the destination buffer. */
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in the destination buffer. */
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in the destination buffer. */
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByCmplxMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
new file mode 100644
index 0000000..b31e1bd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
@@ -0,0 +1,182 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_cmplx_q15.c   
+*   
+* Description:	Q15 complex-by-complex multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup CmplxByCmplxMult   
+ * @{   
+ */
+
+/**   
+ * @brief  Q15 complex-by-complex multiplication   
+ * @param[in]  *pSrcA points to the first input vector   
+ * @param[in]  *pSrcB points to the second input vector   
+ * @param[out]  *pDst  points to the output vector   
+ * @param[in]  numSamples number of complex samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.   
+ */
+
+void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q15_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByCmplxMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
new file mode 100644
index 0000000..ba8e352
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
@@ -0,0 +1,209 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_cmplx_q31.c   
+*   
+* Description:	Q31 complex-by-complex multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup CmplxByCmplxMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q31 complex-by-complex multiplication   
+ * @param[in]  *pSrcA points to the first input vector   
+ * @param[in]  *pSrcB points to the second input vector   
+ * @param[out]  *pDst  points to the output vector   
+ * @param[in]  numSamples number of complex samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.   
+ * Input down scaling is not required.   
+ */
+
+void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 1u;
+
+  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.    
+   ** a second loop below computes the remaining 1 sample. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x2u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByCmplxMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
new file mode 100644
index 0000000..5d00cdc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_real_f32.c   
+*   
+* Description:	Floating-point complex by real multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup CmplxByRealMult Complex-by-Real Multiplication   
+ *   
+ * Multiplies a complex vector by a real vector and generates a complex result.   
+ * The data in the complex arrays is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * The parameter numSamples represents the number of complex   
+ * samples processed.  The complex arrays have a total of 2*numSamples   
+ * real values while the real array has a total of numSamples   
+ * real values.   
+ *   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup CmplxByRealMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Floating-point complex-by-real multiplication   
+ * @param[in]  *pSrcCmplx points to the complex input vector   
+ * @param[in]  *pSrcReal points to the real input vector   
+ * @param[out]  *pCmplxDst points to the complex output vector   
+ * @param[in]  numSamples number of samples in each vector   
+ * @return none.   
+ */
+
+void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  float32_t in;                                  /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut = realA * realB.            */
+    /* imagOut = imagA * realB.                */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByRealMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
new file mode 100644
index 0000000..253fc20
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_real_q15.c   
+*   
+* Description:	Q15 complex by real multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup CmplxByRealMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q15 complex-by-real multiplication   
+ * @param[in]  *pSrcCmplx points to the complex input vector   
+ * @param[in]  *pSrcReal points to the real input vector   
+ * @param[out]  *pCmplxDst points to the complex output vector   
+ * @param[in]  numSamples number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ */
+
+void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  q15_t in;                                      /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut = realA * realB.            */
+    /* imagOut = imagA * realB.                */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByRealMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
new file mode 100644
index 0000000..cb5f9d7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_real_q31.c   
+*   
+* Description:	Q31 complex by real multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup CmplxByRealMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q31 complex-by-real multiplication   
+ * @param[in]  *pSrcCmplx points to the complex input vector   
+ * @param[in]  *pSrcReal points to the real input vector   
+ * @param[out]  *pCmplxDst points to the complex output vector   
+ * @param[in]  numSamples number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.   
+ */
+
+void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  q31_t in;                                      /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut = realA * realB.            */
+    /* imagReal = imagA * realB.               */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByRealMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
new file mode 100644
index 0000000..3fd6509
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_init_f32.c   
+*   
+* Description:	Floating-point PID Control initialization function   
+*				  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point PID Control.  
+ * @param[in,out] *S points to an instance of the PID structure.  
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state & 1 = reset the state.  
+ * @return none.  
+ * \par Description:  
+ * \par   
+ * The resetStateFlag specifies whether to set state to zero or not. \n  
+ * The function computes the structure fields: A0, A1 A2   
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)   
+ * also sets the state variables to all zeros.   
+ */
+
+void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag)
+{
+
+  /* Derived coefficient A0 */
+  S->A0 = S->Kp + S->Ki + S->Kd;
+
+  /* Derived coefficient A1 */
+  S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
+
+  /* Derived coefficient A2 */
+  S->A2 = S->Kd;
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(float32_t));
+  }
+
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
new file mode 100644
index 0000000..c1a09e5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_init_q15.c   
+*   
+* Description:	Q15 PID Control initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @param[in,out] *S points to an instance of the Q15 PID structure.   
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.   
+ * @return none.   
+ * \par Description:  
+ * \par   
+ * The resetStateFlag specifies whether to set state to zero or not. \n  
+ * The function computes the structure fields: A0, A1 A2   
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)   
+ * also sets the state variables to all zeros.   
+ */
+
+void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Derived coefficient A0 */
+  S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
+
+  /* Derived coefficients and pack into A1 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+  S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
+
+#else
+
+  S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q15_t));
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t temp;                                    /*to store the sum */
+
+  /* Derived coefficient A0 */
+  temp = S->Kp + S->Ki + S->Kd;
+  S->A0 = (q15_t) __SSAT(temp, 16);
+
+  /* Derived coefficients and pack into A1 */
+  temp = -(S->Kd + S->Kd + S->Kp);
+  S->A1 = (q15_t) __SSAT(temp, 16);
+  S->A2 = S->Kd;
+
+
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q15_t));
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
new file mode 100644
index 0000000..78f1d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_init_q31.c   
+*   
+* Description:	Q31 PID Control initialization function    
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the Q31 PID Control.  
+ * @param[in,out] *S points to an instance of the Q31 PID structure.  
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.  
+ * @return none.   
+ * \par Description:  
+ * \par   
+ * The resetStateFlag specifies whether to set state to zero or not. \n  
+ * The function computes the structure fields: A0, A1 A2   
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)   
+ * also sets the state variables to all zeros.   
+ */
+
+void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Derived coefficient A0 */
+  S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
+
+  /* Derived coefficient A1 */
+  S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t temp;
+
+  /* Derived coefficient A0 */
+  temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
+  S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
+
+  /* Derived coefficient A1 */
+  temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
+  S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Derived coefficient A2 */
+  S->A2 = S->Kd;
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q31_t));
+  }
+
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
new file mode 100644
index 0000000..4d2feda
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
@@ -0,0 +1,54 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_reset_f32.c   
+*   
+* Description:	Floating-point PID Control reset function  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+* @brief  Reset function for the floating-point PID Control.  
+* @param[in] *S	Instance pointer of PID control data structure.  
+* @return none.   
+* \par Description:  
+* The function resets the state buffer to zeros.   
+*/
+void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S)
+{
+
+  /* Clear the state buffer.  The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(float32_t));
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
new file mode 100644
index 0000000..b6200f1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_reset_q15.c   
+*   
+* Description:	Q15 PID Control reset function  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+* @brief  Reset function for the Q15 PID Control.  
+* @param[in] *S		Instance pointer of PID control data structure.  
+* @return none.   
+* \par Description:  
+* The function resets the state buffer to zeros.   
+*/
+void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S)
+{
+  /* Reset state to zero, The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(q15_t));
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
new file mode 100644
index 0000000..0b609a4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
@@ -0,0 +1,54 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_reset_q31.c   
+*   
+* Description:	Q31 PID Control reset function  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+* @brief  Reset function for the Q31 PID Control.  
+* @param[in] *S	Instance pointer of PID control data structure.  
+* @return none.   
+* \par Description:  
+* The function resets the state buffer to zeros.   
+*/
+void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S)
+{
+
+  /* Clear the state buffer.  The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(q31_t));
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
new file mode 100644
index 0000000..6eded6d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
@@ -0,0 +1,408 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_cos_f32.c   
+*   
+* Description:	Sine and Cosine calculation for floating-point values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupController   
+ */
+
+/**   
+ * @defgroup SinCos Sine Cosine  
+ *   
+ * Computes the trigonometric sine and cosine values using a combination of table lookup  
+ * and linear interpolation.    
+ * There are separate functions for Q31 and floating-point data types.  
+ * The input to the floating-point version is in degrees while the  
+ * fixed-point Q31 have a scaled input with the range  
+ * [-1 1) mapping to [-180 180) degrees.  
+ *  
+ * The implementation is based on table lookup using 360 values together with linear interpolation.  
+ * The steps used are:  
+ *  -# Calculation of the nearest integer table index.  
+ *  -# Compute the fractional portion (fract) of the input.  
+ *  -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.     
+ *  -# Sine value is computed as  *psinVal = y0 + (fract * (y1 - y0)).   
+ *  -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.     
+ *  -# Cosine value is computed as  *pcosVal = y0 + (fract * (y1 - y0)).   
+ */
+
+ /**   
+ * @addtogroup SinCos   
+ * @{   
+ */
+
+
+/**   
+* \par   
+* Cosine Table is generated from following loop   
+* 
for(i = 0; i < 360; i++)   
+* {   
+*    cosTable[i]= cos((i-180) * PI/180.0);   
+* } 
  
+*/
+
+static const float32_t cosTable[360] = {
+  -0.999847695156391270f, -0.999390827019095760f, -0.998629534754573830f,
+  -0.997564050259824200f, -0.996194698091745550f, -0.994521895368273290f,
+  -0.992546151641321980f, -0.990268068741570250f,
+  -0.987688340595137660f, -0.984807753012208020f, -0.981627183447663980f,
+  -0.978147600733805690f, -0.974370064785235250f, -0.970295726275996470f,
+  -0.965925826289068200f, -0.961261695938318670f,
+  -0.956304755963035440f, -0.951056516295153530f, -0.945518575599316740f,
+  -0.939692620785908320f, -0.933580426497201740f, -0.927183854566787310f,
+  -0.920504853452440150f, -0.913545457642600760f,
+  -0.906307787036649940f, -0.898794046299167040f, -0.891006524188367790f,
+  -0.882947592858926770f, -0.874619707139395740f, -0.866025403784438710f,
+  -0.857167300702112220f, -0.848048096156425960f,
+  -0.838670567945424160f, -0.829037572555041620f, -0.819152044288991580f,
+  -0.809016994374947340f, -0.798635510047292940f, -0.788010753606721900f,
+  -0.777145961456970680f, -0.766044443118977900f,
+  -0.754709580222772010f, -0.743144825477394130f, -0.731353701619170460f,
+  -0.719339800338651300f, -0.707106781186547460f, -0.694658370458997030f,
+  -0.681998360062498370f, -0.669130606358858240f,
+  -0.656059028990507500f, -0.642787609686539360f, -0.629320391049837280f,
+  -0.615661475325658290f, -0.601815023152048380f, -0.587785252292473030f,
+  -0.573576436351045830f, -0.559192903470746680f,
+  -0.544639035015027080f, -0.529919264233204790f, -0.515038074910054270f,
+  -0.499999999999999780f, -0.484809620246337000f, -0.469471562785890530f,
+  -0.453990499739546750f, -0.438371146789077510f,
+  -0.422618261740699330f, -0.406736643075800100f, -0.390731128489273600f,
+  -0.374606593415912070f, -0.358367949545300270f, -0.342020143325668710f,
+  -0.325568154457156420f, -0.309016994374947340f,
+  -0.292371704722736660f, -0.275637355816999050f, -0.258819045102520850f,
+  -0.241921895599667790f, -0.224951054343864810f, -0.207911690817759120f,
+  -0.190808995376544800f, -0.173648177666930300f,
+  -0.156434465040231040f, -0.139173100960065350f, -0.121869343405147370f,
+  -0.104528463267653330f, -0.087155742747658235f, -0.069756473744125330f,
+  -0.052335956242943620f, -0.034899496702500733f,
+  -0.017452406437283477f, 0.000000000000000061f, 0.017452406437283376f,
+  0.034899496702501080f, 0.052335956242943966f, 0.069756473744125455f,
+  0.087155742747658138f, 0.104528463267653460f,
+  0.121869343405147490f, 0.139173100960065690f, 0.156434465040230920f,
+  0.173648177666930410f, 0.190808995376544920f, 0.207911690817759450f,
+  0.224951054343864920f, 0.241921895599667900f,
+  0.258819045102520740f, 0.275637355816999160f, 0.292371704722736770f,
+  0.309016994374947450f, 0.325568154457156760f, 0.342020143325668820f,
+  0.358367949545300380f, 0.374606593415911960f,
+  0.390731128489273940f, 0.406736643075800210f, 0.422618261740699440f,
+  0.438371146789077460f, 0.453990499739546860f, 0.469471562785890860f,
+  0.484809620246337110f, 0.500000000000000110f,
+  0.515038074910054380f, 0.529919264233204900f, 0.544639035015027200f,
+  0.559192903470746790f, 0.573576436351046050f, 0.587785252292473140f,
+  0.601815023152048270f, 0.615661475325658290f,
+  0.629320391049837500f, 0.642787609686539360f, 0.656059028990507280f,
+  0.669130606358858240f, 0.681998360062498480f, 0.694658370458997370f,
+  0.707106781186547570f, 0.719339800338651190f,
+  0.731353701619170570f, 0.743144825477394240f, 0.754709580222772010f,
+  0.766044443118978010f, 0.777145961456970900f, 0.788010753606722010f,
+  0.798635510047292830f, 0.809016994374947450f,
+  0.819152044288991800f, 0.829037572555041620f, 0.838670567945424050f,
+  0.848048096156425960f, 0.857167300702112330f, 0.866025403784438710f,
+  0.874619707139395740f, 0.882947592858926990f,
+  0.891006524188367900f, 0.898794046299167040f, 0.906307787036649940f,
+  0.913545457642600870f, 0.920504853452440370f, 0.927183854566787420f,
+  0.933580426497201740f, 0.939692620785908430f,
+  0.945518575599316850f, 0.951056516295153530f, 0.956304755963035440f,
+  0.961261695938318890f, 0.965925826289068310f, 0.970295726275996470f,
+  0.974370064785235250f, 0.978147600733805690f,
+  0.981627183447663980f, 0.984807753012208020f, 0.987688340595137770f,
+  0.990268068741570360f, 0.992546151641321980f, 0.994521895368273290f,
+  0.996194698091745550f, 0.997564050259824200f,
+  0.998629534754573830f, 0.999390827019095760f, 0.999847695156391270f,
+  1.000000000000000000f, 0.999847695156391270f, 0.999390827019095760f,
+  0.998629534754573830f, 0.997564050259824200f,
+  0.996194698091745550f, 0.994521895368273290f, 0.992546151641321980f,
+  0.990268068741570360f, 0.987688340595137770f, 0.984807753012208020f,
+  0.981627183447663980f, 0.978147600733805690f,
+  0.974370064785235250f, 0.970295726275996470f, 0.965925826289068310f,
+  0.961261695938318890f, 0.956304755963035440f, 0.951056516295153530f,
+  0.945518575599316850f, 0.939692620785908430f,
+  0.933580426497201740f, 0.927183854566787420f, 0.920504853452440370f,
+  0.913545457642600870f, 0.906307787036649940f, 0.898794046299167040f,
+  0.891006524188367900f, 0.882947592858926990f,
+  0.874619707139395740f, 0.866025403784438710f, 0.857167300702112330f,
+  0.848048096156425960f, 0.838670567945424050f, 0.829037572555041620f,
+  0.819152044288991800f, 0.809016994374947450f,
+  0.798635510047292830f, 0.788010753606722010f, 0.777145961456970900f,
+  0.766044443118978010f, 0.754709580222772010f, 0.743144825477394240f,
+  0.731353701619170570f, 0.719339800338651190f,
+  0.707106781186547570f, 0.694658370458997370f, 0.681998360062498480f,
+  0.669130606358858240f, 0.656059028990507280f, 0.642787609686539360f,
+  0.629320391049837500f, 0.615661475325658290f,
+  0.601815023152048270f, 0.587785252292473140f, 0.573576436351046050f,
+  0.559192903470746790f, 0.544639035015027200f, 0.529919264233204900f,
+  0.515038074910054380f, 0.500000000000000110f,
+  0.484809620246337110f, 0.469471562785890860f, 0.453990499739546860f,
+  0.438371146789077460f, 0.422618261740699440f, 0.406736643075800210f,
+  0.390731128489273940f, 0.374606593415911960f,
+  0.358367949545300380f, 0.342020143325668820f, 0.325568154457156760f,
+  0.309016994374947450f, 0.292371704722736770f, 0.275637355816999160f,
+  0.258819045102520740f, 0.241921895599667900f,
+  0.224951054343864920f, 0.207911690817759450f, 0.190808995376544920f,
+  0.173648177666930410f, 0.156434465040230920f, 0.139173100960065690f,
+  0.121869343405147490f, 0.104528463267653460f,
+  0.087155742747658138f, 0.069756473744125455f, 0.052335956242943966f,
+  0.034899496702501080f, 0.017452406437283376f, 0.000000000000000061f,
+  -0.017452406437283477f, -0.034899496702500733f,
+  -0.052335956242943620f, -0.069756473744125330f, -0.087155742747658235f,
+  -0.104528463267653330f, -0.121869343405147370f, -0.139173100960065350f,
+  -0.156434465040231040f, -0.173648177666930300f,
+  -0.190808995376544800f, -0.207911690817759120f, -0.224951054343864810f,
+  -0.241921895599667790f, -0.258819045102520850f, -0.275637355816999050f,
+  -0.292371704722736660f, -0.309016994374947340f,
+  -0.325568154457156420f, -0.342020143325668710f, -0.358367949545300270f,
+  -0.374606593415912070f, -0.390731128489273600f, -0.406736643075800100f,
+  -0.422618261740699330f, -0.438371146789077510f,
+  -0.453990499739546750f, -0.469471562785890530f, -0.484809620246337000f,
+  -0.499999999999999780f, -0.515038074910054270f, -0.529919264233204790f,
+  -0.544639035015027080f, -0.559192903470746680f,
+  -0.573576436351045830f, -0.587785252292473030f, -0.601815023152048380f,
+  -0.615661475325658290f, -0.629320391049837280f, -0.642787609686539360f,
+  -0.656059028990507500f, -0.669130606358858240f,
+  -0.681998360062498370f, -0.694658370458997030f, -0.707106781186547460f,
+  -0.719339800338651300f, -0.731353701619170460f, -0.743144825477394130f,
+  -0.754709580222772010f, -0.766044443118977900f,
+  -0.777145961456970680f, -0.788010753606721900f, -0.798635510047292940f,
+  -0.809016994374947340f, -0.819152044288991580f, -0.829037572555041620f,
+  -0.838670567945424160f, -0.848048096156425960f,
+  -0.857167300702112220f, -0.866025403784438710f, -0.874619707139395740f,
+  -0.882947592858926770f, -0.891006524188367790f, -0.898794046299167040f,
+  -0.906307787036649940f, -0.913545457642600760f,
+  -0.920504853452440150f, -0.927183854566787310f, -0.933580426497201740f,
+  -0.939692620785908320f, -0.945518575599316740f, -0.951056516295153530f,
+  -0.956304755963035440f, -0.961261695938318670f,
+  -0.965925826289068200f, -0.970295726275996470f, -0.974370064785235250f,
+  -0.978147600733805690f, -0.981627183447663980f, -0.984807753012208020f,
+  -0.987688340595137660f, -0.990268068741570250f,
+  -0.992546151641321980f, -0.994521895368273290f, -0.996194698091745550f,
+  -0.997564050259824200f, -0.998629534754573830f, -0.999390827019095760f,
+  -0.999847695156391270f, -1.000000000000000000f
+};
+
+/**   
+* \par   
+* Sine Table is generated from following loop   
+* 
for(i = 0; i < 360; i++)   
+* {   
+*    sinTable[i]= sin((i-180) * PI/180.0);   
+* } 
   
+*/
+
+
+static const float32_t sinTable[360] = {
+  -0.017452406437283439f, -0.034899496702500699f, -0.052335956242943807f,
+  -0.069756473744125524f, -0.087155742747658638f, -0.104528463267653730f,
+  -0.121869343405147550f, -0.139173100960065740f,
+  -0.156434465040230980f, -0.173648177666930280f, -0.190808995376544970f,
+  -0.207911690817759310f, -0.224951054343864780f, -0.241921895599667730f,
+  -0.258819045102521020f, -0.275637355816999660f,
+  -0.292371704722737050f, -0.309016994374947510f, -0.325568154457156980f,
+  -0.342020143325668880f, -0.358367949545300210f, -0.374606593415912240f,
+  -0.390731128489274160f, -0.406736643075800430f,
+  -0.422618261740699500f, -0.438371146789077290f, -0.453990499739546860f,
+  -0.469471562785891080f, -0.484809620246337170f, -0.499999999999999940f,
+  -0.515038074910054380f, -0.529919264233204900f,
+  -0.544639035015026860f, -0.559192903470746900f, -0.573576436351046380f,
+  -0.587785252292473250f, -0.601815023152048160f, -0.615661475325658400f,
+  -0.629320391049837720f, -0.642787609686539470f,
+  -0.656059028990507280f, -0.669130606358858350f, -0.681998360062498590f,
+  -0.694658370458997140f, -0.707106781186547570f, -0.719339800338651410f,
+  -0.731353701619170570f, -0.743144825477394240f,
+  -0.754709580222771790f, -0.766044443118978010f, -0.777145961456971010f,
+  -0.788010753606722010f, -0.798635510047292720f, -0.809016994374947450f,
+  -0.819152044288992020f, -0.829037572555041740f,
+  -0.838670567945424050f, -0.848048096156426070f, -0.857167300702112330f,
+  -0.866025403784438710f, -0.874619707139395850f, -0.882947592858927100f,
+  -0.891006524188367900f, -0.898794046299166930f,
+  -0.906307787036650050f, -0.913545457642600980f, -0.920504853452440370f,
+  -0.927183854566787420f, -0.933580426497201740f, -0.939692620785908430f,
+  -0.945518575599316850f, -0.951056516295153640f,
+  -0.956304755963035550f, -0.961261695938318890f, -0.965925826289068310f,
+  -0.970295726275996470f, -0.974370064785235250f, -0.978147600733805690f,
+  -0.981627183447663980f, -0.984807753012208020f,
+  -0.987688340595137660f, -0.990268068741570360f, -0.992546151641322090f,
+  -0.994521895368273400f, -0.996194698091745550f, -0.997564050259824200f,
+  -0.998629534754573830f, -0.999390827019095760f,
+  -0.999847695156391270f, -1.000000000000000000f, -0.999847695156391270f,
+  -0.999390827019095760f, -0.998629534754573830f, -0.997564050259824200f,
+  -0.996194698091745550f, -0.994521895368273290f,
+  -0.992546151641321980f, -0.990268068741570250f, -0.987688340595137770f,
+  -0.984807753012208020f, -0.981627183447663980f, -0.978147600733805580f,
+  -0.974370064785235250f, -0.970295726275996470f,
+  -0.965925826289068310f, -0.961261695938318890f, -0.956304755963035440f,
+  -0.951056516295153530f, -0.945518575599316740f, -0.939692620785908320f,
+  -0.933580426497201740f, -0.927183854566787420f,
+  -0.920504853452440260f, -0.913545457642600870f, -0.906307787036649940f,
+  -0.898794046299167040f, -0.891006524188367790f, -0.882947592858926880f,
+  -0.874619707139395740f, -0.866025403784438600f,
+  -0.857167300702112220f, -0.848048096156426070f, -0.838670567945423940f,
+  -0.829037572555041740f, -0.819152044288991800f, -0.809016994374947450f,
+  -0.798635510047292830f, -0.788010753606722010f,
+  -0.777145961456970790f, -0.766044443118978010f, -0.754709580222772010f,
+  -0.743144825477394240f, -0.731353701619170460f, -0.719339800338651080f,
+  -0.707106781186547460f, -0.694658370458997250f,
+  -0.681998360062498480f, -0.669130606358858240f, -0.656059028990507160f,
+  -0.642787609686539250f, -0.629320391049837390f, -0.615661475325658180f,
+  -0.601815023152048270f, -0.587785252292473140f,
+  -0.573576436351046050f, -0.559192903470746900f, -0.544639035015027080f,
+  -0.529919264233204900f, -0.515038074910054160f, -0.499999999999999940f,
+  -0.484809620246337060f, -0.469471562785890810f,
+  -0.453990499739546750f, -0.438371146789077400f, -0.422618261740699440f,
+  -0.406736643075800150f, -0.390731128489273720f, -0.374606593415912010f,
+  -0.358367949545300270f, -0.342020143325668710f,
+  -0.325568154457156640f, -0.309016994374947400f, -0.292371704722736770f,
+  -0.275637355816999160f, -0.258819045102520740f, -0.241921895599667730f,
+  -0.224951054343865000f, -0.207911690817759310f,
+  -0.190808995376544800f, -0.173648177666930330f, -0.156434465040230870f,
+  -0.139173100960065440f, -0.121869343405147480f, -0.104528463267653460f,
+  -0.087155742747658166f, -0.069756473744125302f,
+  -0.052335956242943828f, -0.034899496702500969f, -0.017452406437283512f,
+  0.000000000000000000f, 0.017452406437283512f, 0.034899496702500969f,
+  0.052335956242943828f, 0.069756473744125302f,
+  0.087155742747658166f, 0.104528463267653460f, 0.121869343405147480f,
+  0.139173100960065440f, 0.156434465040230870f, 0.173648177666930330f,
+  0.190808995376544800f, 0.207911690817759310f,
+  0.224951054343865000f, 0.241921895599667730f, 0.258819045102520740f,
+  0.275637355816999160f, 0.292371704722736770f, 0.309016994374947400f,
+  0.325568154457156640f, 0.342020143325668710f,
+  0.358367949545300270f, 0.374606593415912010f, 0.390731128489273720f,
+  0.406736643075800150f, 0.422618261740699440f, 0.438371146789077400f,
+  0.453990499739546750f, 0.469471562785890810f,
+  0.484809620246337060f, 0.499999999999999940f, 0.515038074910054160f,
+  0.529919264233204900f, 0.544639035015027080f, 0.559192903470746900f,
+  0.573576436351046050f, 0.587785252292473140f,
+  0.601815023152048270f, 0.615661475325658180f, 0.629320391049837390f,
+  0.642787609686539250f, 0.656059028990507160f, 0.669130606358858240f,
+  0.681998360062498480f, 0.694658370458997250f,
+  0.707106781186547460f, 0.719339800338651080f, 0.731353701619170460f,
+  0.743144825477394240f, 0.754709580222772010f, 0.766044443118978010f,
+  0.777145961456970790f, 0.788010753606722010f,
+  0.798635510047292830f, 0.809016994374947450f, 0.819152044288991800f,
+  0.829037572555041740f, 0.838670567945423940f, 0.848048096156426070f,
+  0.857167300702112220f, 0.866025403784438600f,
+  0.874619707139395740f, 0.882947592858926880f, 0.891006524188367790f,
+  0.898794046299167040f, 0.906307787036649940f, 0.913545457642600870f,
+  0.920504853452440260f, 0.927183854566787420f,
+  0.933580426497201740f, 0.939692620785908320f, 0.945518575599316740f,
+  0.951056516295153530f, 0.956304755963035440f, 0.961261695938318890f,
+  0.965925826289068310f, 0.970295726275996470f,
+  0.974370064785235250f, 0.978147600733805580f, 0.981627183447663980f,
+  0.984807753012208020f, 0.987688340595137770f, 0.990268068741570250f,
+  0.992546151641321980f, 0.994521895368273290f,
+  0.996194698091745550f, 0.997564050259824200f, 0.998629534754573830f,
+  0.999390827019095760f, 0.999847695156391270f, 1.000000000000000000f,
+  0.999847695156391270f, 0.999390827019095760f,
+  0.998629534754573830f, 0.997564050259824200f, 0.996194698091745550f,
+  0.994521895368273400f, 0.992546151641322090f, 0.990268068741570360f,
+  0.987688340595137660f, 0.984807753012208020f,
+  0.981627183447663980f, 0.978147600733805690f, 0.974370064785235250f,
+  0.970295726275996470f, 0.965925826289068310f, 0.961261695938318890f,
+  0.956304755963035550f, 0.951056516295153640f,
+  0.945518575599316850f, 0.939692620785908430f, 0.933580426497201740f,
+  0.927183854566787420f, 0.920504853452440370f, 0.913545457642600980f,
+  0.906307787036650050f, 0.898794046299166930f,
+  0.891006524188367900f, 0.882947592858927100f, 0.874619707139395850f,
+  0.866025403784438710f, 0.857167300702112330f, 0.848048096156426070f,
+  0.838670567945424050f, 0.829037572555041740f,
+  0.819152044288992020f, 0.809016994374947450f, 0.798635510047292720f,
+  0.788010753606722010f, 0.777145961456971010f, 0.766044443118978010f,
+  0.754709580222771790f, 0.743144825477394240f,
+  0.731353701619170570f, 0.719339800338651410f, 0.707106781186547570f,
+  0.694658370458997140f, 0.681998360062498590f, 0.669130606358858350f,
+  0.656059028990507280f, 0.642787609686539470f,
+  0.629320391049837720f, 0.615661475325658400f, 0.601815023152048160f,
+  0.587785252292473250f, 0.573576436351046380f, 0.559192903470746900f,
+  0.544639035015026860f, 0.529919264233204900f,
+  0.515038074910054380f, 0.499999999999999940f, 0.484809620246337170f,
+  0.469471562785891080f, 0.453990499739546860f, 0.438371146789077290f,
+  0.422618261740699500f, 0.406736643075800430f,
+  0.390731128489274160f, 0.374606593415912240f, 0.358367949545300210f,
+  0.342020143325668880f, 0.325568154457156980f, 0.309016994374947510f,
+  0.292371704722737050f, 0.275637355816999660f,
+  0.258819045102521020f, 0.241921895599667730f, 0.224951054343864780f,
+  0.207911690817759310f, 0.190808995376544970f, 0.173648177666930280f,
+  0.156434465040230980f, 0.139173100960065740f,
+  0.121869343405147550f, 0.104528463267653730f, 0.087155742747658638f,
+  0.069756473744125524f, 0.052335956242943807f, 0.034899496702500699f,
+  0.017452406437283439f, 0.000000000000000122f
+};
+
+
+/**   
+ * @brief  Floating-point sin_cos function.  
+ * @param[in]  theta    input value in degrees   
+ * @param[out] *pSinVal points to the processed sine output.   
+ * @param[out] *pCosVal points to the processed cos output.   
+ * @return none.  
+ */
+
+
+void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCosVal)
+{
+  uint32_t i;                                    /* Index for reading nearwst output values */
+  float32_t x1 = -179.0f;                        /* Initial input value */
+  float32_t y0, y1;                              /* nearest output values */
+  float32_t fract;                               /* fractional part of input */
+
+  /* Calculation of fractional part */
+  if(theta > 0.0f)
+  {
+    fract = theta - (float32_t) ((int32_t) theta);
+  }
+  else
+  {
+    fract = (theta - (float32_t) ((int32_t) theta)) + 1.0f;
+  }
+
+  /* index calculation for reading nearest output values */
+  i = (uint32_t) (theta - x1);
+
+  /* reading nearest sine output values */
+  y0 = sinTable[i];
+  y1 = sinTable[i + 1u];
+
+  /* Calculation of sine value */
+  *pSinVal = y0 + (fract * (y1 - y0));
+
+  /* reading nearest cosine output values */
+  y0 = cosTable[i];
+  y1 = cosTable[i + 1u];
+
+  /* Calculation of cosine value */
+  *pCosVal = y0 + (fract * (y1 - y0));
+
+}
+
+/**   
+ * @} end of SinCos group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
new file mode 100644
index 0000000..1185994
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
@@ -0,0 +1,311 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_cos_q31.c   
+*   
+* Description:	Cosine & Sine calculation for Q31 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupController   
+ */
+
+ /**   
+ * @addtogroup SinCos   
+ * @{   
+ */
+
+/**   
+* \par   
+* Sine Table is generated from following loop   
+* 
for(i = 0; i < 360; i++)   
+* {   
+*    sinTable[i]= sin((i-180) * PI/180.0);   
+* } 
  
+* Convert above coefficients to fixed point 1.31 format.   
+*/
+
+static const int32_t sinTableQ31[360] = {
+
+  0x0, 0xfdc41e9b, 0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2,
+  0xf06695da,
+  0xee2f9369, 0xebf9f498, 0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9,
+  0xe108b40d, 0xdedf047d,
+  0xdcb7ea46, 0xda939061, 0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0,
+  0xd00ce422, 0xcdfc85bb,
+  0xcbf00dbe, 0xc9e7a512, 0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224,
+  0xc0000000, 0xbe133b7c,
+  0xbc2b9b05, 0xba4944a2, 0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af,
+  0xb1320139, 0xaf726def,
+  0xadb922b7, 0xac0641fb, 0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666,
+  0xa3ecac65, 0xa263007d,
+  0xa0e0a15f, 0x9f65ad2d, 0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5,
+  0x98722192, 0x9726069c,
+  0x95e218c9, 0x94a6715d, 0x937328f5, 0x92485786, 0x9126145f, 0x900c7621,
+  0x8efb92c2, 0x8df37f8b,
+  0x8cf45113, 0x8bfe1b3f, 0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4,
+  0x87b826f7, 0x86f93f50,
+  0x8643c7b3, 0x8597ce46, 0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b,
+  0x82cc0f36, 0x825a0a5b,
+  0x81f1d1ce, 0x81936daf, 0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130,
+  0x804fd23a, 0x802ce84c,
+  0x8013f61d, 0x8004fda0, 0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c,
+  0x804fd23a, 0x807cb130,
+  0x80b381ac, 0x80f43f69, 0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b,
+  0x82cc0f36, 0x8347d77b,
+  0x83cd5982, 0x845c8ae3, 0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50,
+  0x87b826f7, 0x88806fc4,
+  0x89520a1a, 0x8a2ce59f, 0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b,
+  0x8efb92c2, 0x900c7621,
+  0x9126145f, 0x92485786, 0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c,
+  0x98722192, 0x99c64fc5,
+  0x9b2276b0, 0x9c867b2c, 0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d,
+  0xa3ecac65, 0xa57d8666,
+  0xa7156f3c, 0xa8b4471a, 0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def,
+  0xb1320139, 0xb2f7b9af,
+  0xb4c373ee, 0xb6950c1e, 0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c,
+  0xc0000000, 0xc1f1c224,
+  0xc3e85b18, 0xc5e3a3a9, 0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb,
+  0xd00ce422, 0xd220ffc0,
+  0xd438af17, 0xd653c860, 0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d,
+  0xe108b40d, 0xe334cdc9,
+  0xe5632654, 0xe7939223, 0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da,
+  0xf29ecfb2, 0xf4d814a4,
+  0xf7123849, 0xf94d0e2e, 0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632,
+  0x6b2f1d2,
+  0x8edc7b7, 0xb27eb5c, 0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68,
+  0x163a1a7e, 0x186c6ddd,
+  0x1a9cd9ac, 0x1ccb3237, 0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f,
+  0x278dde6e, 0x29ac37a0,
+  0x2bc750e9, 0x2ddf0040, 0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee,
+  0x381c8bb5, 0x3a1c5c57,
+  0x3c17a4e8, 0x3e0e3ddc, 0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e,
+  0x4793a210, 0x496af3e2,
+  0x4b3c8c12, 0x4d084651, 0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05,
+  0x55a6125c, 0x574bb8e6,
+  0x58ea90c4, 0x5a82799a, 0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3,
+  0x620dbe8b, 0x637984d4,
+  0x64dd8950, 0x6639b03b, 0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3,
+  0x6c8cd70b, 0x6db7a87a,
+  0x6ed9eba1, 0x6ff389df, 0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1,
+  0x74ef0ebc, 0x75d31a61,
+  0x76adf5e6, 0x777f903c, 0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba,
+  0x7b0a9f8d, 0x7ba3751d,
+  0x7c32a67e, 0x7cb82885, 0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251,
+  0x7ec11aa5, 0x7f0bc097,
+  0x7f4c7e54, 0x7f834ed0, 0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260,
+  0x7fffffff, 0x7ffb0260,
+  0x7fec09e3, 0x7fd317b4, 0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097,
+  0x7ec11aa5, 0x7e6c9251,
+  0x7e0e2e32, 0x7da5f5a5, 0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d,
+  0x7b0a9f8d, 0x7a6831ba,
+  0x79bc384d, 0x7906c0b0, 0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61,
+  0x74ef0ebc, 0x7401e4c1,
+  0x730baeed, 0x720c8075, 0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a,
+  0x6c8cd70b, 0x6b598ea3,
+  0x6a1de737, 0x68d9f964, 0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4,
+  0x620dbe8b, 0x609a52d3,
+  0x5f1f5ea1, 0x5d9cff83, 0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6,
+  0x55a6125c, 0x53f9be05,
+  0x5246dd49, 0x508d9211, 0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2,
+  0x4793a210, 0x45b6bb5e,
+  0x43d464fb, 0x41ecc484, 0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57,
+  0x381c8bb5, 0x36185aee,
+  0x340ff242, 0x32037a45, 0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0,
+  0x278dde6e, 0x256c6f9f,
+  0x234815ba, 0x2120fb83, 0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd,
+  0x163a1a7e, 0x14060b68,
+  0x11d06c97, 0xf996a26, 0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2,
+  0x4779632, 0x23be165,
+
+
+};
+
+/**   
+* \par   
+* Cosine Table is generated from following loop   
+* 
for(i = 0; i < 360; i++)   
+* {   
+*    cosTable[i]= cos((i-180) * PI/180.0);   
+* } 
  
+* \par   
+* Convert above coefficients to fixed point 1.31 format.   
+*/
+static const int32_t cosTableQ31[360] = {
+  0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c, 0x804fd23a, 0x807cb130,
+  0x80b381ac, 0x80f43f69,
+  0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b, 0x82cc0f36, 0x8347d77b,
+  0x83cd5982, 0x845c8ae3,
+  0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50, 0x87b826f7, 0x88806fc4,
+  0x89520a1a, 0x8a2ce59f,
+  0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b, 0x8efb92c2, 0x900c7621,
+  0x9126145f, 0x92485786,
+  0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c, 0x98722192, 0x99c64fc5,
+  0x9b2276b0, 0x9c867b2c,
+  0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d, 0xa3ecac65, 0xa57d8666,
+  0xa7156f3c, 0xa8b4471a,
+  0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def, 0xb1320139, 0xb2f7b9af,
+  0xb4c373ee, 0xb6950c1e,
+  0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c, 0xc0000000, 0xc1f1c224,
+  0xc3e85b18, 0xc5e3a3a9,
+  0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb, 0xd00ce422, 0xd220ffc0,
+  0xd438af17, 0xd653c860,
+  0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d, 0xe108b40d, 0xe334cdc9,
+  0xe5632654, 0xe7939223,
+  0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da, 0xf29ecfb2, 0xf4d814a4,
+  0xf7123849, 0xf94d0e2e,
+  0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632, 0x6b2f1d2, 0x8edc7b7,
+  0xb27eb5c,
+  0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68, 0x163a1a7e, 0x186c6ddd,
+  0x1a9cd9ac, 0x1ccb3237,
+  0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f, 0x278dde6e, 0x29ac37a0,
+  0x2bc750e9, 0x2ddf0040,
+  0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee, 0x381c8bb5, 0x3a1c5c57,
+  0x3c17a4e8, 0x3e0e3ddc,
+  0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e, 0x4793a210, 0x496af3e2,
+  0x4b3c8c12, 0x4d084651,
+  0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05, 0x55a6125c, 0x574bb8e6,
+  0x58ea90c4, 0x5a82799a,
+  0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3, 0x620dbe8b, 0x637984d4,
+  0x64dd8950, 0x6639b03b,
+  0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3, 0x6c8cd70b, 0x6db7a87a,
+  0x6ed9eba1, 0x6ff389df,
+  0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1, 0x74ef0ebc, 0x75d31a61,
+  0x76adf5e6, 0x777f903c,
+  0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba, 0x7b0a9f8d, 0x7ba3751d,
+  0x7c32a67e, 0x7cb82885,
+  0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251, 0x7ec11aa5, 0x7f0bc097,
+  0x7f4c7e54, 0x7f834ed0,
+  0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260, 0x7fffffff, 0x7ffb0260,
+  0x7fec09e3, 0x7fd317b4,
+  0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097, 0x7ec11aa5, 0x7e6c9251,
+  0x7e0e2e32, 0x7da5f5a5,
+  0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d, 0x7b0a9f8d, 0x7a6831ba,
+  0x79bc384d, 0x7906c0b0,
+  0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61, 0x74ef0ebc, 0x7401e4c1,
+  0x730baeed, 0x720c8075,
+  0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a, 0x6c8cd70b, 0x6b598ea3,
+  0x6a1de737, 0x68d9f964,
+  0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4, 0x620dbe8b, 0x609a52d3,
+  0x5f1f5ea1, 0x5d9cff83,
+  0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6, 0x55a6125c, 0x53f9be05,
+  0x5246dd49, 0x508d9211,
+  0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2, 0x4793a210, 0x45b6bb5e,
+  0x43d464fb, 0x41ecc484,
+  0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57, 0x381c8bb5, 0x36185aee,
+  0x340ff242, 0x32037a45,
+  0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0, 0x278dde6e, 0x256c6f9f,
+  0x234815ba, 0x2120fb83,
+  0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd, 0x163a1a7e, 0x14060b68,
+  0x11d06c97, 0xf996a26,
+  0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2, 0x4779632, 0x23be165, 0x0,
+  0xfdc41e9b,
+  0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2, 0xf06695da,
+  0xee2f9369, 0xebf9f498,
+  0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9, 0xe108b40d, 0xdedf047d,
+  0xdcb7ea46, 0xda939061,
+  0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0, 0xd00ce422, 0xcdfc85bb,
+  0xcbf00dbe, 0xc9e7a512,
+  0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224, 0xc0000000, 0xbe133b7c,
+  0xbc2b9b05, 0xba4944a2,
+  0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af, 0xb1320139, 0xaf726def,
+  0xadb922b7, 0xac0641fb,
+  0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666, 0xa3ecac65, 0xa263007d,
+  0xa0e0a15f, 0x9f65ad2d,
+  0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5, 0x98722192, 0x9726069c,
+  0x95e218c9, 0x94a6715d,
+  0x937328f5, 0x92485786, 0x9126145f, 0x900c7621, 0x8efb92c2, 0x8df37f8b,
+  0x8cf45113, 0x8bfe1b3f,
+  0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4, 0x87b826f7, 0x86f93f50,
+  0x8643c7b3, 0x8597ce46,
+  0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b, 0x82cc0f36, 0x825a0a5b,
+  0x81f1d1ce, 0x81936daf,
+  0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130, 0x804fd23a, 0x802ce84c,
+  0x8013f61d, 0x8004fda0,
+
+};
+
+
+/**   
+ * @brief  Q31 sin_cos function.  
+ * @param[in]  theta    scaled input value in degrees   
+ * @param[out] *pSinVal points to the processed sine output.   
+ * @param[out] *pCosVal points to the processed cosine output.   
+ * @return none.  
+ *   
+ * The Q31 input value is in the range [-1 +1) and is mapped to a degree value in the range [-180 180).  
+ *   
+ */
+
+
+void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal)
+{
+  q31_t x0;                                      /* Nearest input value */
+  q31_t y0, y1;                                  /* Nearest output values */
+  q31_t xSpacing = INPUT_SPACING;                /* Spaing between inputs */
+  uint32_t i;                                    /* Index */
+  q31_t oneByXSpacing;                           /* 1/ xSpacing value */
+  q31_t out;                                     /* temporary variable */
+  uint32_t sign_bits;                            /* No.of sign bits */
+  uint32_t firstX = 0x80000000;                  /* First X value */
+
+  /* Calculation of index */
+  i = ((uint32_t) theta - firstX) / (uint32_t) xSpacing;
+
+  /* Calculation of first nearest input value */
+  x0 = (q31_t) firstX + ((q31_t) i * xSpacing);
+
+  /* Reading nearest sine output values from table */
+  y0 = sinTableQ31[i];
+  y1 = sinTableQ31[i + 1u];
+
+  /* Calculation of 1/(x1-x0) */
+  /* (x1-x0) is xSpacing which is fixed value */
+  sign_bits = 8u;
+  oneByXSpacing = 0x5A000000;
+
+  /* Calculation of (theta - x0)/(x1-x0) */
+  out =
+    (((q31_t) (((q63_t) (theta - x0) * oneByXSpacing) >> 32)) << sign_bits);
+
+  /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
+  *pSinVal = y0 + ((q31_t) (((q63_t) (y1 - y0) * out) >> 30));
+
+  /* Reading nearest cosine output values from table */
+  y0 = cosTableQ31[i];
+  y1 = cosTableQ31[i + 1u];
+
+  /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
+  *pCosVal = y0 + ((q31_t) (((q63_t) (y1 - y0) * out) >> 30));
+
+}
+
+/**   
+ * @} end of SinCos group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
new file mode 100644
index 0000000..59f7877
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
@@ -0,0 +1,254 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cos_f32.c   
+*   
+* Description:	Fast cosine calculation for floating-point values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**   
+ * @ingroup groupFastMath   
+ */
+
+/**   
+ * @defgroup cos Cosine   
+ *   
+ * Computes the trigonometric cosine function using a combination of table lookup  
+ * and cubic interpolation.  There are separate functions for  
+ * Q15, Q31, and floating-point data types.  
+ * The input to the floating-point version is in radians while the  
+ * fixed-point Q15 and Q31 have a scaled input with the range  
+ * [0 1) mapping to [0 2*pi).  
+ *  
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.  
+ * The steps used are:  
+ *  -# Calculation of the nearest integer table index  
+ *  -# Fetch the four table values a, b, c, and d    
+ *  -# Compute the fractional portion (fract) of the table index.  
+ *  -# Calculation of wa, wb, wc, wd   
+ *  -# The final result equals a*wa + b*wb + c*wc + d*wd  
+ *  
+ * where  
+ * 
   
+ *    a=Table[index-1];   
+ *    b=Table[index+0];   
+ *    c=Table[index+1];   
+ *    d=Table[index+2];   
+ * 
  
+ * and  
+ * 
   
+ *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;   
+ *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;   
+ *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;   
+ *    wd=(1/6)*fract.^3 - (1/6)*fract;   
+ * 
   
+ */
+
+ /**   
+ * @addtogroup cos   
+ * @{   
+ */
+
+
+/**   
+* \par   
+* Example code for Generation of Cos Table:  
+* tableSize = 256;   
+* 
for(n = -1; n < (tableSize + 1); n++)   
+* {   
+*	cosTable[n+1]= cos(2*pi*n/tableSize);   
+* } 
   
+* where pi value is  3.14159265358979   
+*/
+
+static const float32_t cosTable[259] = {
+  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+  0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
+  0.992479562759399410f, 0.989176511764526370f,
+  0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
+  0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
+  0.949528157711029050f, 0.941544055938720700f,
+  0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
+  0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
+  0.870086967945098880f, 0.857728600502014160f,
+  0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
+  0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
+  0.757208824157714840f, 0.740951120853424070f,
+  0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
+  0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
+  0.615231573581695560f, 0.595699310302734380f,
+  0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
+  0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
+  0.449611335992813110f, 0.427555084228515630f,
+  0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
+  0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
+  0.266712754964828490f, 0.242980182170867920f,
+  0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
+  0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
+  0.073564566671848297f, 0.049067676067352295f,
+  0.024541229009628296f, 0.000000000000000061f, -0.024541229009628296f,
+  -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
+  -0.122410677373409270f, -0.146730467677116390f,
+  -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
+  -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
+  -0.313681751489639280f, -0.336889863014221190f,
+  -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
+  -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
+  -0.492898195981979370f, -0.514102756977081300f,
+  -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
+  -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
+  -0.653172850608825680f, -0.671558976173400880f,
+  -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
+  -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
+  -0.788346409797668460f, -0.803207516670227050f,
+  -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
+  -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
+  -0.893224298954010010f, -0.903989315032958980f,
+  -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
+  -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
+  -0.963776051998138430f, -0.970031261444091800f,
+  -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
+  -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
+  -0.997290432453155520f, -0.998795449733734130f,
+  -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
+  -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
+  -0.992479562759399410f, -0.989176511764526370f,
+  -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
+  -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
+  -0.949528157711029050f, -0.941544055938720700f,
+  -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
+  -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
+  -0.870086967945098880f, -0.857728600502014160f,
+  -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
+  -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
+  -0.757208824157714840f, -0.740951120853424070f,
+  -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
+  -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
+  -0.615231573581695560f, -0.595699310302734380f,
+  -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
+  -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
+  -0.449611335992813110f, -0.427555084228515630f,
+  -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
+  -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
+  -0.266712754964828490f, -0.242980182170867920f,
+  -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
+  -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
+  -0.073564566671848297f, -0.049067676067352295f,
+  -0.024541229009628296f, -0.000000000000000184f, 0.024541229009628296f,
+  0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
+  0.122410677373409270f, 0.146730467677116390f,
+  0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
+  0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
+  0.313681751489639280f, 0.336889863014221190f,
+  0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
+  0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
+  0.492898195981979370f, 0.514102756977081300f,
+  0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
+  0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
+  0.653172850608825680f, 0.671558976173400880f,
+  0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
+  0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
+  0.788346409797668460f, 0.803207516670227050f,
+  0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
+  0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
+  0.893224298954010010f, 0.903989315032958980f,
+  0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
+  0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
+  0.963776051998138430f, 0.970031261444091800f,
+  0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
+  0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
+  0.997290432453155520f, 0.998795449733734130f,
+  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f
+};
+
+/**  
+ * @brief  Fast approximation to the trigonometric cosine function for floating-point data.  
+ * @param[in] x input value in radians.  
+ * @return cos(x).  
+ */
+
+float32_t arm_cos_f32(
+  float32_t x)
+{
+  float32_t cosVal, fract, in;
+  uint32_t index;
+  uint32_t tableSize = (uint32_t) TABLE_SIZE;
+  float32_t wa, wb, wc, wd;
+  float32_t a, b, c, d;
+  float32_t *tablePtr;
+  int32_t n;
+
+  /* input x is in radians */
+  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+  in = x * 0.159154943092f;
+
+  /* Calculation of floor value of input */
+  n = (int32_t) in;
+
+  /* Make negative values towards -infinity */
+  if(x < 0.0f)
+  {
+    n = n - 1;
+  }
+
+  /* Map input value to [0 1] */
+  in = in - (float32_t) n;
+
+  /* Calculation of index of the table */
+  index = (uint32_t) (tableSize * in);
+
+  /* fractional value calculation */
+  fract = ((float32_t) tableSize * in) - (float32_t) index;
+
+  /* Initialise table pointer */
+  tablePtr = (float32_t *) & cosTable[index];
+
+  /* Read four nearest values of input value from the cos table */
+  a = *tablePtr++;
+  b = *tablePtr++;
+  c = *tablePtr++;
+  d = *tablePtr++;
+
+  /* Cubic interpolation process */
+  wa = -(((0.166666667f) * fract) * (fract * fract)) +
+    (((0.5f) * (fract * fract)) - ((0.3333333333333f) * fract));
+  wb = ((((0.5f) * fract) * (fract * fract)) - (fract * fract)) +
+    (-((0.5f) * fract) + 1.0f);
+  wc = -(((0.5f) * fract) * (fract * fract)) +
+    (((0.5f) * (fract * fract)) + fract);
+  wd = (((0.166666667f) * fract) * (fract * fract)) -
+    ((0.166666667f) * fract);
+
+  /* Calculate cos value */
+  cosVal = ((a * wa) + (b * wb)) + ((c * wc) + (d * wd));
+
+  /* Return the output value */
+  return (cosVal);
+
+}
+
+/**   
+ * @} end of cos group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
new file mode 100644
index 0000000..6e804c3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
@@ -0,0 +1,189 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cos_q15.c   
+*   
+* Description:	Fast cosine calculation for Q15 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+ /**   
+ * @addtogroup cos   
+ * @{   
+ */
+
+/**  
+* \par   
+* Table Values are in Q15(1.15 Fixed point format) and generation is done in three steps   
+* \par   
+* First Generate cos values in floating point:   
+* tableSize = 256;    
+* 
for(n = -1; n < (tableSize + 1); n++)   
+* {   
+*	cosTable[n+1]= cos(2*pi*n/tableSize);   
+* }
  
+* where pi value is  3.14159265358979   
+* \par   
+* Secondly Convert Floating point to Q15(Fixed point):   
+*	(cosTable[i] * pow(2, 15))   
+* \par   
+* Finally Rounding to nearest integer is done   
+* 	cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);   
+*/
+
+static const q15_t cosTableQ15[259] = {
+  0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
+  0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
+  0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
+  0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
+  0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
+  0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
+  0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
+  0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
+  0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
+  0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
+  0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
+  0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
+  0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
+  0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
+  0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
+  0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
+  0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
+  0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
+  0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
+  0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
+  0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
+  0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
+  0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
+  0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
+  0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
+  0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
+  0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
+  0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
+  0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
+  0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
+  0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
+  0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
+  0x7ff6, 0x7fff, 0x7ff6
+};
+
+
+/**  
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.  
+ * @param[in] x Scaled input value in radians.  
+ * @return  cos(x).  
+ *  
+ * The Q15 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi).  
+ */
+
+q15_t arm_cos_q15(
+  q15_t x)
+{
+  q31_t cosVal;                                  /* Temporary variable for output */
+  q15_t *tablePtr;                               /* Pointer to table */
+  q15_t in, in2;                                 /* Temporary variables for input */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q15_t a, b, c, d;                              /* Four nearest output values */
+  q15_t fract, fractCube, fractSquare;           /* Variables for fractional value */
+  q15_t oneBy6 = 0x1555;                         /* Fixed point value of 1/6 */
+  q15_t tableSpacing = TABLE_SPACING_Q15;        /* Table spacing */
+  int32_t index;                                 /* Index variable */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = (int32_t) in / tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = (q15_t) index *tableSpacing;
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = (q15_t) ((fract * fract) >> 15);
+
+  /* fractCube = fract * fract * fract */
+  fractCube = (q15_t) ((fractSquare * fract) >> 15);
+
+  /* Initialise table pointer */
+  tablePtr = (q15_t *) & cosTableQ15[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
+  wa = (q31_t) oneBy6 *fractCube;
+  wa += (q31_t) 0x2AAA *fract;
+  wa = -(wa >> 15);
+  wa += (fractSquare >> 1u);
+
+  /* Read first nearest value of output from the cos table */
+  a = *tablePtr++;
+
+  /* cosVal = a * wa */
+  cosVal = a * wa;
+
+  /* Calculation of wb */
+  wb = (((fractCube >> 1u) - fractSquare) - (fract >> 1u)) + 0x7FFF;
+
+  /* Read second nearest value of output from the cos table */
+  b = *tablePtr++;
+
+  /*      cosVal += b*wb */
+  cosVal += b * wb;
+
+  /* Calculation of wc */
+  wc = -(q31_t) fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+
+  /* Read third nearest value of output from the cos table */
+  c = *tablePtr++;
+
+  /*      cosVal += c*wc */
+  cosVal += c * wc;
+
+  /* Calculation of wd */
+  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+  fractCube = fractCube - fract;
+  wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
+
+  /* Read fourth nearest value of output from the cos table */
+  d = *tablePtr++;
+
+  /* cosVal += d*wd; */
+  cosVal += d * wd;
+
+  /* Return the output value in 1.15(q15) format */
+  return ((q15_t) (cosVal >> 15u));
+
+}
+
+/**   
+ * @} end of cos group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
new file mode 100644
index 0000000..bcbda59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
@@ -0,0 +1,225 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cos_q31.c   
+*   
+* Description:	Fast cosine calculation for Q31 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+ /**   
+ * @addtogroup cos   
+ * @{   
+ */
+
+/**   
+ * \par   
+ * Table Values are in Q31(1.31 Fixed point format) and generation is done in three steps   
+ * First Generate cos values in floating point:   
+ * tableSize = 256;     
+ * 
for(n = -1; n < (tableSize + 1); n++)   
+ * {   
+ *	cosTable[n+1]= cos(2*pi*n/tableSize);   
+ * } 
    
+ * where pi value is  3.14159265358979   
+ * \par   
+ * Secondly Convert Floating point to Q31(Fixed point):   
+ *	(cosTable[i] * pow(2, 31))   
+ * \par   
+ * Finally Rounding to nearest integer is done   
+ * 	cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);   
+ */
+
+
+static const q31_t cosTableQ31[259] = {
+  0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
+  0x7f0991c4, 0x7e9d55fc,
+  0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
+  0x798a23b1, 0x78848414,
+  0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
+  0x6f5f02b2, 0x6dca0d14,
+  0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
+  0x60ec3830, 0x5ed77c8a,
+  0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
+  0x4ebfe8a5, 0x4c3fdff4,
+  0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
+  0x398cdd32, 0x36ba2014,
+  0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
+  0x2223a4c5, 0x1f19f97b,
+  0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
+  0x96a9049, 0x647d97c,
+  0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
+  0xed37ef91,
+  0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
+  0xd7d946d8, 0xd4e0cb15,
+  0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
+  0xc0e8b648, 0xbe31e19b,
+  0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
+  0xac64d510, 0xaa0a5b2e,
+  0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
+  0x9b1776da, 0x99307ee0,
+  0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
+  0x8daad37b, 0x8c4a142f,
+  0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
+  0x84a2fc62, 0x83d60412,
+  0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
+  0x8058c94c, 0x80277872,
+  0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
+  0x80f66e3c, 0x8162aa04,
+  0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
+  0x8675dc4f, 0x877b7bec,
+  0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
+  0x90a0fd4e, 0x9235f2ec,
+  0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
+  0x9f13c7d0, 0xa1288376,
+  0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
+  0xb140175b, 0xb3c0200c,
+  0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
+  0xc67322ce, 0xc945dfec,
+  0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
+  0xdddc5b3b, 0xe0e60685,
+  0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
+  0xf6956fb7, 0xf9b82684,
+  0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
+  0x12c8106f,
+  0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
+  0x2826b928, 0x2b1f34eb,
+  0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
+  0x3f1749b8, 0x41ce1e65,
+  0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
+  0x539b2af0, 0x55f5a4d2,
+  0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
+  0x64e88926, 0x66cf8120,
+  0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
+  0x72552c85, 0x73b5ebd1,
+  0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
+  0x7b5d039e, 0x7c29fbee,
+  0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
+  0x7fa736b4, 0x7fd8878e,
+  0x7ff62182, 0x7fffffff, 0x7ff62182
+};
+
+/**  
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.  
+ * @param[in] x Scaled input value in radians.  
+ * @return  cos(x).  
+ *  
+ * The Q31 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi).  
+ */
+
+q31_t arm_cos_q31(
+  q31_t x)
+{
+  q31_t cosVal, in, in2;                         /* Temporary variables for input, output */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q31_t a, b, c, d;                              /* Four nearest output values */
+  q31_t *tablePtr;                               /* Pointer to table */
+  q31_t fract, fractCube, fractSquare;           /* Temporary values for fractional values */
+  q31_t oneBy6 = 0x15555555;                     /* Fixed point value of 1/6 */
+  q31_t tableSpacing = TABLE_SPACING_Q31;        /* Table spacing */
+  q31_t temp;                                    /* Temporary variable for intermediate process */
+  uint32_t index;                                /* Index variable */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = in / tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = ((q31_t) index) * tableSpacing;
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
+  fractSquare = fractSquare << 1;
+
+  /* fractCube = fract * fract * fract */
+  fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
+  fractCube = fractCube << 1;
+
+  /* Initialise table pointer */
+  tablePtr = (q31_t *) & cosTableQ31[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
+  wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  temp = 0x2AAAAAAA;
+  wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
+  wa = -(wa << 1u);
+  wa += (fractSquare >> 1u);
+
+  /* Read first nearest value of output from the cos table */
+  a = *tablePtr++;
+
+  /* cosVal = a*wa */
+  cosVal = ((q31_t) (((q63_t) a * wa) >> 32));
+
+  /* q31(1.31) Fixed point value of 1 */
+  temp = 0x7FFFFFFF;
+
+  /* Calculation of wb */
+  wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
+  /* Read second nearest value of output from the cos table */
+  b = *tablePtr++;
+
+  /*      cosVal += b*wb */
+  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) b * (wb))) >> 32);
+
+  /* Calculation of wc */
+  wc = -fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+  /* Read third nearest values of output value from the cos table */
+  c = *tablePtr++;
+
+  /*      cosVal += c*wc */
+  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) c * (wc))) >> 32);
+
+  /* Calculation of wd */
+  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+  fractCube = fractCube - fract;
+  wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  wd = (wd << 1u);
+
+  /* Read fourth nearest value of output from the cos table */
+  d = *tablePtr++;
+
+  /* cosVal += d*wd; */
+  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) d * (wd))) >> 32);
+
+  /* convert cosVal in 2.30 format to 1.31 format */
+  return (cosVal << 1u);
+
+}
+
+/**   
+ * @} end of cos group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
new file mode 100644
index 0000000..877cfa4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
@@ -0,0 +1,257 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_f32.c   
+*   
+* Description:	Fast sine calculation for floating-point values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+/**   
+ * @defgroup sin Sine   
+ *   
+ * Computes the trigonometric sine function using a combination of table lookup  
+ * and cubic interpolation.  There are separate functions for  
+ * Q15, Q31, and floating-point data types.  
+ * The input to the floating-point version is in radians while the  
+ * fixed-point Q15 and Q31 have a scaled input with the range  
+ * [0 1) mapping to [0 2*pi).  
+ *  
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.  
+ * The steps used are:  
+ *  -# Calculation of the nearest integer table index  
+ *  -# Fetch the four table values a, b, c, and d    
+ *  -# Compute the fractional portion (fract) of the table index.  
+ *  -# Calculation of wa, wb, wc, wd   
+ *  -# The final result equals a*wa + b*wb + c*wc + d*wd  
+ *  
+ * where  
+ * 
   
+ *    a=Table[index-1];   
+ *    b=Table[index+0];   
+ *    c=Table[index+1];   
+ *    d=Table[index+2];   
+ * 
  
+ * and  
+ * 
   
+ *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;   
+ *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;   
+ *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;   
+ *    wd=(1/6)*fract.^3 - (1/6)*fract;   
+ * 
   
+ */
+
+/**   
+ * @addtogroup sin   
+ * @{   
+ */
+
+
+/**  
+ * \par   
+ * Example code for Generation of Floating-point Sin Table:  
+ * tableSize = 256;   
+ * 
for(n = -1; n < (tableSize + 1); n++)   
+ * {   
+ *	sinTable[n+1]=sin(2*pi*n/tableSize);   
+ * }
   
+ * \par   
+ * where pi value is  3.14159265358979   
+ */
+
+static const float32_t sinTable[259] = {
+  -0.024541229009628296f, 0.000000000000000000f, 0.024541229009628296f,
+  0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
+  0.122410677373409270f, 0.146730467677116390f,
+  0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
+  0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
+  0.313681751489639280f, 0.336889863014221190f,
+  0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
+  0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
+  0.492898195981979370f, 0.514102756977081300f,
+  0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
+  0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
+  0.653172850608825680f, 0.671558976173400880f,
+  0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
+  0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
+  0.788346409797668460f, 0.803207516670227050f,
+  0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
+  0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
+  0.893224298954010010f, 0.903989315032958980f,
+  0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
+  0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
+  0.963776051998138430f, 0.970031261444091800f,
+  0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
+  0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
+  0.997290432453155520f, 0.998795449733734130f,
+  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+  0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
+  0.992479562759399410f, 0.989176511764526370f,
+  0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
+  0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
+  0.949528157711029050f, 0.941544055938720700f,
+  0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
+  0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
+  0.870086967945098880f, 0.857728600502014160f,
+  0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
+  0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
+  0.757208824157714840f, 0.740951120853424070f,
+  0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
+  0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
+  0.615231573581695560f, 0.595699310302734380f,
+  0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
+  0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
+  0.449611335992813110f, 0.427555084228515630f,
+  0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
+  0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
+  0.266712754964828490f, 0.242980182170867920f,
+  0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
+  0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
+  0.073564566671848297f, 0.049067676067352295f,
+  0.024541229009628296f, 0.000000000000000122f, -0.024541229009628296f,
+  -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
+  -0.122410677373409270f, -0.146730467677116390f,
+  -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
+  -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
+  -0.313681751489639280f, -0.336889863014221190f,
+  -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
+  -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
+  -0.492898195981979370f, -0.514102756977081300f,
+  -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
+  -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
+  -0.653172850608825680f, -0.671558976173400880f,
+  -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
+  -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
+  -0.788346409797668460f, -0.803207516670227050f,
+  -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
+  -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
+  -0.893224298954010010f, -0.903989315032958980f,
+  -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
+  -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
+  -0.963776051998138430f, -0.970031261444091800f,
+  -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
+  -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
+  -0.997290432453155520f, -0.998795449733734130f,
+  -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
+  -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
+  -0.992479562759399410f, -0.989176511764526370f,
+  -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
+  -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
+  -0.949528157711029050f, -0.941544055938720700f,
+  -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
+  -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
+  -0.870086967945098880f, -0.857728600502014160f,
+  -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
+  -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
+  -0.757208824157714840f, -0.740951120853424070f,
+  -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
+  -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
+  -0.615231573581695560f, -0.595699310302734380f,
+  -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
+  -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
+  -0.449611335992813110f, -0.427555084228515630f,
+  -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
+  -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
+  -0.266712754964828490f, -0.242980182170867920f,
+  -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
+  -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
+  -0.073564566671848297f, -0.049067676067352295f,
+  -0.024541229009628296f, -0.000000000000000245f, 0.024541229009628296f
+};
+
+
+/**  
+ * @brief  Fast approximation to the trigonometric sine function for floating-point data.  
+ * @param[in] x input value in radians.  
+ * @return  sin(x).  
+ */
+
+float32_t arm_sin_f32(
+  float32_t x)
+{
+  float32_t sinVal, fract, in;                   /* Temporary variables for input, output */
+  uint32_t index;                                /* Index variable */
+  uint32_t tableSize = (uint32_t) TABLE_SIZE;    /* Initialise tablesize */
+  float32_t wa, wb, wc, wd;                      /* Cubic interpolation coefficients */
+  float32_t a, b, c, d;                          /* Four nearest output values */
+  float32_t *tablePtr;                           /* Pointer to table */
+  int32_t n;
+
+  /* input x is in radians */
+  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+  in = x * 0.159154943092f;
+
+  /* Calculation of floor value of input */
+  n = (int32_t) in;
+
+  /* Make negative values towards -infinity */
+  if(x < 0.0f)
+  {
+    n = n - 1;
+  }
+
+  /* Map input value to [0 1] */
+  in = in - (float32_t) n;
+
+  /* Calculation of index of the table */
+  index = (uint32_t) (tableSize * in);
+
+  /* fractional value calculation */
+  fract = ((float32_t) tableSize * in) - (float32_t) index;
+
+  /* Initialise table pointer */
+  tablePtr = (float32_t *) & sinTable[index];
+
+  /* Read four nearest values of output value from the sin table */
+  a = *tablePtr++;
+  b = *tablePtr++;
+  c = *tablePtr++;
+  d = *tablePtr++;
+
+  /* Cubic interpolation process */
+  wa = -(((0.166666667f) * (fract * (fract * fract))) +
+         ((0.3333333333333f) * fract)) + ((0.5f) * (fract * fract));
+  wb = (((0.5f) * (fract * (fract * fract))) -
+        ((fract * fract) + ((0.5f) * fract))) + 1.0f;
+  wc = (-((0.5f) * (fract * (fract * fract))) +
+        ((0.5f) * (fract * fract))) + fract;
+  wd = ((0.166666667f) * (fract * (fract * fract))) -
+    ((0.166666667f) * fract);
+
+  /* Calculate sin value */
+  sinVal = ((a * wa) + (b * wb)) + ((c * wc) + (d * wd));
+
+  /* Return the output value */
+  return (sinVal);
+
+}
+
+/**   
+ * @} end of sin group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
new file mode 100644
index 0000000..8f3f365
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_q15.c   
+*   
+* Description:	Fast sine calculation for Q15 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+ /**   
+ * @addtogroup sin   
+ * @{   
+ */
+
+
+/**   
+ * \par   
+ * Example code for Generation of Q15 Sin Table:  
+ * \par   
+ * 
tableSize = 256;   
+ * for(n = -1; n < (tableSize + 1); n++)   
+ * {   
+ *	sinTable[n+1]=sin(2*pi*n/tableSize);   
+ * } 
   
+ * where pi value is  3.14159265358979   
+ * \par   
+ * Convert Floating point to Q15(Fixed point):   
+ *	(sinTable[i] * pow(2, 15))   
+ * \par   
+ * rounding to nearest integer is done   
+ * 	sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);   
+ */
+
+
+static const q15_t sinTableQ15[259] = {
+  0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
+  0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
+  0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
+  0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
+  0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
+  0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
+  0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
+  0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
+  0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
+  0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
+  0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
+  0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
+  0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
+  0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
+  0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
+  0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
+  0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
+  0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
+  0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
+  0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
+  0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
+  0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
+  0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
+  0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
+  0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
+  0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
+  0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
+  0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
+  0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
+  0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
+  0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
+  0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
+  0xfcdc, 0x0, 0x324
+};
+
+
+/**  
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.  
+ * @param[in] x Scaled input value in radians.  
+ * @return  sin(x).  
+ *  
+ * The Q15 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi).  
+ */
+
+q15_t arm_sin_q15(
+  q15_t x)
+{
+  q31_t sinVal;                                  /* Temporary variables output */
+  q15_t *tablePtr;                               /* Pointer to table */
+  q15_t fract, in, in2;                          /* Temporary variables for input, output */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q15_t a, b, c, d;                              /* Four nearest output values */
+  q15_t fractCube, fractSquare;                  /* Temporary values for fractional value */
+  q15_t oneBy6 = 0x1555;                         /* Fixed point value of 1/6 */
+  q15_t tableSpacing = TABLE_SPACING_Q15;        /* Table spacing */
+  int32_t index;                                 /* Index variable */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = (int32_t) in / tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = (q15_t) ((index) * tableSpacing);
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = (q15_t) ((fract * fract) >> 15);
+
+  /* fractCube = fract * fract * fract */
+  fractCube = (q15_t) ((fractSquare * fract) >> 15);
+
+  /* Initialise table pointer */
+  tablePtr = (q15_t *) & sinTableQ15[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
+  wa = (q31_t) oneBy6 *fractCube;
+  wa += (q31_t) 0x2AAA *fract;
+  wa = -(wa >> 15);
+  wa += ((q31_t) fractSquare >> 1u);
+
+  /* Read first nearest value of output from the sin table */
+  a = *tablePtr++;
+
+  /* sinVal = a * wa */
+  sinVal = a * wa;
+
+  /* Calculation of wb */
+  wb = (((q31_t) fractCube >> 1u) - (q31_t) fractSquare) -
+    (((q31_t) fract >> 1u) - 0x7FFF);
+
+  /* Read second nearest value of output from the sin table */
+  b = *tablePtr++;
+
+  /*      sinVal += b*wb */
+  sinVal += b * wb;
+
+
+  /* Calculation of wc */
+  wc = -(q31_t) fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+
+  /* Read third nearest value of output from the sin table */
+  c = *tablePtr++;
+
+  /*      sinVal += c*wc */
+  sinVal += c * wc;
+
+  /* Calculation of wd */
+  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+  fractCube = fractCube - fract;
+  wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
+
+  /* Read fourth nearest value of output from the sin table */
+  d = *tablePtr++;
+
+  /* sinVal += d*wd; */
+  sinVal += d * wd;
+
+  /* Return the output value in 1.15(q15) format */
+  return ((q15_t) (sinVal >> 15u));
+
+}
+
+/**   
+ * @} end of sin group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
new file mode 100644
index 0000000..28b58ab
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
@@ -0,0 +1,227 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_q31.c   
+*   
+* Description:	Fast sine calculation for Q31 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+ /**   
+ * @addtogroup sin   
+ * @{   
+ */
+
+/**  
+ * \par   
+ * Tables generated are in Q31(1.31 Fixed point format)   
+ * Generation of sin values in floating point:   
+ * 
tableSize = 256;     
+ * for(n = -1; n < (tableSize + 1); n++)   
+ * {   
+ *	sinTable[n+1]= sin(2*pi*n/tableSize);   
+ * } 
   
+ * where pi value is  3.14159265358979   
+ * \par   
+ * Convert Floating point to Q31(Fixed point):   
+ *	(sinTable[i] * pow(2, 31))   
+ * \par   
+ * rounding to nearest integer is done   
+ * 	sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);   
+ */
+
+static const q31_t sinTableQ31[259] = {
+  0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
+  0x12c8106f,
+  0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
+  0x2826b928, 0x2b1f34eb,
+  0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
+  0x3f1749b8, 0x41ce1e65,
+  0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
+  0x539b2af0, 0x55f5a4d2,
+  0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
+  0x64e88926, 0x66cf8120,
+  0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
+  0x72552c85, 0x73b5ebd1,
+  0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
+  0x7b5d039e, 0x7c29fbee,
+  0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
+  0x7fa736b4, 0x7fd8878e,
+  0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
+  0x7f0991c4, 0x7e9d55fc,
+  0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
+  0x798a23b1, 0x78848414,
+  0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
+  0x6f5f02b2, 0x6dca0d14,
+  0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
+  0x60ec3830, 0x5ed77c8a,
+  0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
+  0x4ebfe8a5, 0x4c3fdff4,
+  0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
+  0x398cdd32, 0x36ba2014,
+  0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
+  0x2223a4c5, 0x1f19f97b,
+  0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
+  0x96a9049, 0x647d97c,
+  0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
+  0xed37ef91,
+  0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
+  0xd7d946d8, 0xd4e0cb15,
+  0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
+  0xc0e8b648, 0xbe31e19b,
+  0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
+  0xac64d510, 0xaa0a5b2e,
+  0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
+  0x9b1776da, 0x99307ee0,
+  0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
+  0x8daad37b, 0x8c4a142f,
+  0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
+  0x84a2fc62, 0x83d60412,
+  0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
+  0x8058c94c, 0x80277872,
+  0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
+  0x80f66e3c, 0x8162aa04,
+  0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
+  0x8675dc4f, 0x877b7bec,
+  0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
+  0x90a0fd4e, 0x9235f2ec,
+  0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
+  0x9f13c7d0, 0xa1288376,
+  0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
+  0xb140175b, 0xb3c0200c,
+  0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
+  0xc67322ce, 0xc945dfec,
+  0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
+  0xdddc5b3b, 0xe0e60685,
+  0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
+  0xf6956fb7, 0xf9b82684,
+  0xfcdbd541, 0x0, 0x3242abf
+};
+
+
+/**  
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.  
+ * @param[in] x Scaled input value in radians.  
+ * @return  sin(x).  
+ *  
+ * The Q31 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi).  
+ */
+
+q31_t arm_sin_q31(
+  q31_t x)
+{
+  q31_t sinVal, in, in2;                         /* Temporary variables for input, output */
+  uint32_t index;                                /* Index variables */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q31_t a, b, c, d;                              /* Four nearest output values */
+  q31_t *tablePtr;                               /* Pointer to table */
+  q31_t fract, fractCube, fractSquare;           /* Temporary values for fractional values */
+  q31_t oneBy6 = 0x15555555;                     /* Fixed point value of 1/6 */
+  q31_t tableSpacing = TABLE_SPACING_Q31;        /* Table spacing */
+  q31_t temp;                                    /* Temporary variable for intermediate process */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = (uint32_t) in / (uint32_t) tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = (q31_t) index *tableSpacing;
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
+  fractSquare = fractSquare << 1;
+
+  /* fractCube = fract * fract * fract */
+  fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
+  fractCube = fractCube << 1;
+
+  /* Initialise table pointer */
+  tablePtr = (q31_t *) & sinTableQ31[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
+  wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  temp = 0x2AAAAAAA;
+  wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
+  wa = -(wa << 1u);
+  wa += (fractSquare >> 1u);
+
+  /* Read first nearest value of output from the sin table */
+  a = *tablePtr++;
+
+  /* sinVal = a*wa */
+  sinVal = ((q31_t) (((q63_t) a * wa) >> 32));
+
+  /* q31(1.31) Fixed point value of 1 */
+  temp = 0x7FFFFFFF;
+
+  /* Calculation of wb */
+  wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
+
+  /* Read second nearest value of output from the sin table */
+  b = *tablePtr++;
+
+  /*  sinVal += b*wb */
+  sinVal = (q31_t) ((((q63_t) sinVal << 32) + (q63_t) b * (wb)) >> 32);
+
+  /* Calculation of wc */
+  wc = -fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+
+  /* Read third nearest value of output from the sin table */
+  c = *tablePtr++;
+
+  /*      sinVal += c*wc */
+  sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) c * wc)) >> 32);
+
+  /* Calculation of wd */
+  /* wd = (oneBy6) * fractCube - (oneBy6) * fract; */
+  fractCube = fractCube - fract;
+  wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  wd = (wd << 1u);
+
+  /* Read fourth nearest value of output from the sin table */
+  d = *tablePtr++;
+
+  /* sinVal += d*wd; */
+  sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) d * wd)) >> 32);
+
+  /* convert sinVal in 2.30 format to 1.31 format */
+  return (sinVal << 1u);
+
+}
+
+/**   
+ * @} end of sin group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
new file mode 100644
index 0000000..bcd5287
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
@@ -0,0 +1,178 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sqrt_q15.c   
+*   
+* Description:	Q15 square root function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+/**   
+ * @addtogroup SQRT   
+ * @{   
+ */
+
+  /**  
+   * @brief  Q15 square root function.  
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.  
+   * @param[out]  *pOut  square root of input value.  
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if  
+   * in is negative value and returns zero output for negative values.  
+   */
+
+arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut)
+{
+  q31_t prevOut;
+  q15_t oneByOut;
+  uint32_t sign_bits;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t out;
+
+  if(in > 0)
+  {
+    /* run for ten iterations */
+
+    /* Take initial guess as half of the input and first iteration */
+    out = ((q31_t) in >> 1u) + 0x3FFF;
+
+    /* Calculation of reciprocal of out */
+    /* oneByOut contains reciprocal of out which is in 2.14 format   
+       and oneByOut should be upscaled by signBits */
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+
+    /* 0.5 * (out) */
+    out = out >> 1u;
+    /* prevOut = 0.5 * out + (in * (oneByOut << signBits))) */
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* Third iteration */
+    sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+    out = out >> 1u;
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* Fifth iteration */
+    sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+    out = out >> 1u;
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* Seventh iteration */
+    sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+    out = out >> 1u;
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* tenth iteration */
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+    out = out >> 1u;
+    *pOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    return (ARM_MATH_SUCCESS);
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t out, loopVar;                            /* Temporary variable for output, loop variable */
+  if(in > 0)
+  {
+    /* run for ten iterations */
+
+    /* Take initial guess as half of the input and first iteration */
+    out = ((q31_t) in >> 1u) + 0x3FFF;
+
+    /* Calculation of reciprocal of out */
+
+    /* oneByOut contains reciprocal of out which is in 2.14 format   
+       and oneByOut should be upscaled by sign bits */
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+
+    /* 0.5 * (out) */
+    out = out >> 1u;
+    /* prevOut = 0.5 * out + (in * oneByOut) << signbits))) */
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* loop for third iteration to tenth iteration */
+
+    for (loopVar = 1; loopVar <= 8; loopVar++)
+    {
+
+      sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+      /* 0.5 * (prevOut) */
+      prevOut = prevOut >> 1u;
+      /* prevOut = 0.5 * prevOut+ (in * oneByOut) << signbits))) */
+      out =
+        prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+      /* prevOut      = out */
+      prevOut = out;
+
+    }
+    /* output is moved to pOut pointer */
+    *pOut = prevOut;
+
+    return (ARM_MATH_SUCCESS);
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  else
+  {
+
+    *pOut = 0;
+    return (ARM_MATH_ARGUMENT_ERROR);
+  }
+
+}
+
+/**   
+ * @} end of SQRT group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
new file mode 100644
index 0000000..043678d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
@@ -0,0 +1,199 @@
+/* ----------------------------------------------------------------------  
+* Copyright (C) 2010 ARM Limited. All rights reserved.  
+*  
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*  
+* Project: 	    CMSIS DSP Library  
+* Title:		arm_sqrt_q31.c  
+*  
+* Description:	Q31 square root function. 
+*  
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.2 2010/11/11  
+*    Documentation updated.   
+*  
+* Version 1.0.1 2010/10/05   
+*    Production release and review comments incorporated.  
+*  
+* Version 1.0.0 2010/09/20   
+*    Production release and review comments incorporated. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**  
+ * @ingroup groupFastMath  
+ */
+
+/**  
+ * @addtogroup SQRT  
+ * @{  
+ */
+
+/** 
+ * @brief Q31 square root function. 
+ * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. 
+ * @param[out]  *pOut square root of input value. 
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if 
+ * in is negative value and returns zero output for negative values. 
+ */
+
+arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut)
+{
+  q63_t prevOut;
+  q31_t oneByOut;
+  uint32_t signBits;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q63_t out;
+
+  if(in > 0)
+  {
+
+    /* run for ten iterations */
+
+    /* Take initial guess as half of the input and first iteration */
+    out = (in >> 1) + 0x3FFFFFFF;
+
+    /* Calculation of reciprocal of out */
+    /* oneByOut contains reciprocal of out which is in 2.30 format  
+       and oneByOut should be upscaled by signBits */
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+
+    /* 0.5 * (out) */
+    out = out >> 1u;
+
+    /* prevOut = 0.5 * out + (in * (oneByOut << signBits))) */
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    /* Third iteration */
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    /* Fifth iteration */
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    /* Seventh iteration */
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    /* tenth iteration */
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    *pOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    return (ARM_MATH_SUCCESS);
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t out, loopVar;                            /* Temporary variable for output, loop variable */
+  if(in > 0)
+  {
+
+    /* run for ten iterations */
+
+    /* Take initial guess as half of the input and first iteration */
+    out = (in >> 1) + 0x3FFFFFFF;
+
+    /* Calculation of reciprocal of out */
+    /* oneByOut contains reciprocal of out which is in 2.30 format   
+       and oneByOut should be upscaled by sign bits */
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+
+    /* 0.5 * (out) */
+    out = out >> 1u;
+
+    /* prevOut = 0.5 * out + (in * (oneByOut) << signbits) */
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+
+    /* loop for third iteration to tength iteration */
+
+    for (loopVar = 1; loopVar <= 14; loopVar++)
+    {
+
+      signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+      /* 0.5 * (prevOut) */
+      prevOut = prevOut >> 1u;
+      /* out = 0.5 * prevOut + (in * oneByOut) << signbits))) */
+      out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+      /* prevOut      = out */
+      prevOut = out;
+
+    }
+    /* output is moved to pOut pointer */
+    *pOut = prevOut;
+
+    return (ARM_MATH_SUCCESS);
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  else
+  {
+    *pOut = 0;
+    return (ARM_MATH_ARGUMENT_ERROR);
+  }
+}
+
+/**  
+ * @} end of SQRT group  
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
new file mode 100644
index 0000000..ff6239a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
@@ -0,0 +1,102 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_32x64_init_q31.c   
+*   
+* Description:	High precision Q31 Biquad cascade filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1_32x64   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S           	points to an instance of the high precision Q31 Biquad cascade filter structure.   
+ * @param[in]     numStages     number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs      points to the filter coefficients.   
+ * @param[in]     *pState       points to the state buffer.   
+ * @param[in]     postShift     Shift to be applied after the accumulator.  Varies according to the coefficients format.   
+ * @return        none   
+ *   
+ * Coefficient and State Ordering:   
+ *   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
   
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ * 
   
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.   
+ *   
+ * \par   
+ * The pState points to state variables array and size of each state variable is 1.63 format.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the state array as:   
+ * 
   
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ */
+
+void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF1_32x64 group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
new file mode 100644
index 0000000..73ff8b0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
@@ -0,0 +1,476 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_32x64_q31.c   
+*   
+* Description:	High precision Q31 Biquad cascade filter processing function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter   
+ *   
+ * This function implements a high precision Biquad cascade filter which operates on   
+ * Q31 data values.  The filter coefficients are in 1.31 format and the state variables   
+ * are in 1.63 format.  The double precision state variables reduce quantization noise   
+ * in the filter and provide a cleaner output.   
+ * These filters are particularly useful when implementing filters in which the   
+ * singularities are close to the unit circle.  This is common for low pass or high   
+ * pass filters with very low cutoff frequencies.   
+ *   
+ * The function operates on blocks of input and output data   
+ * and each call to the function processes blockSize samples through   
+ * the filter. pSrc and pDst points to input and output arrays   
+ * containing blockSize Q31 values.   
+ *   
+ * \par Algorithm   
+ * Each Biquad stage implements a second order filter using the difference equation:   
+ * 
   
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+ * 
   
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.   
+ * \image html Biquad.gif "Single Biquad filter stage"   
+ * Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.   
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.   
+ * Pay careful attention to the sign of the feedback coefficients.   
+ * Some design tools use the difference equation   
+ * 
   
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]   
+ * 
   
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.   
+ *   
+ * \par   
+ * Higher order filters are realized as a cascade of second order sections.   
+ * numStages refers to the number of second order stages used.   
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.   
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"   
+ * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).   
+ *   
+ * \par   
+ * The pState points to state variables array .   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision.   
+ * The state variables are arranged in the array as:   
+ * 
   
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
   
+ *   
+ * \par   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values of data in 1.63 format.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ *   
+ * \par Init Function   
+ * There is also an associated initialization function which performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * For example, to statically initialize the filter instance structure use   
+ * 
   
+ *     arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};   
+ * 
   
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below.   
+ * \par Fixed-Point Behavior   
+ * Care must be taken while using Biquad Cascade 32x64 filter function.   
+ * Following issues must be considered:   
+ * - Scaling of coefficients   
+ * - Filter gain   
+ * - Overflow and saturation   
+ *   
+ * \par   
+ * Filter coefficients are represented as fractional values and   
+ * restricted to lie in the range [-1 +1).   
+ * The processing function has an additional scaling parameter postShift   
+ * which allows the filter coefficients to exceed the range [+1 -1).   
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.   
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"   
+ * This essentially scales the filter coefficients by 2^postShift.   
+ * For example, to realize the coefficients   
+ * 
   
+ *    {1.5, -0.8, 1.2, 1.6, -0.9}   
+ * 
   
+ * set the Coefficient array to:   
+ * 
   
+ *    {0.75, -0.4, 0.6, 0.8, -0.45}   
+ * 
   
+ * and set postShift=1   
+ *   
+ * \par   
+ * The second thing to keep in mind is the gain through the filter.   
+ * The frequency response of a Biquad filter is a function of its coefficients.   
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.   
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.   
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.   
+ *   
+ * \par   
+ * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.   
+ * This is described in the function specific documentation below.   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1_32x64   
+ * @{   
+ */
+
+/**   
+ * @details   
+   
+ * @param[in]  *S points to an instance of the high precision Q31 Biquad cascade filter.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in]  blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).   
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to   
+ * 1.31 format by discarding the low 32 bits.   
+ *   
+ * \par   
+ * Two related functions are provided in the CMSIS DSP library.   
+ * arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.   
+ * arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.   
+ */
+
+void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q63_t *pState = S->pState;                     /*  state pointer initialization  */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q63_t acc;                                     /*  accumulator                   */
+  q63_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q63_t Xn;                                      /*  temporary input               */
+  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /* The variable acc hold output value that is being computed and   
+     * stored in the destination buffer   
+     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling. Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn = Xn << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn1, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn2, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* The result is converted to 1.63 , Yn2 variable is reused */
+      Yn2 = acc << shift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* Read the second input into Xn2, to reuse the value */
+      Xn2 = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn2 = Xn2 << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn2, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn1, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn2, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn1, a2);
+
+      /* The result is converted to 1.63, Yn1 variable is reused */
+      Yn1 = acc << shift;
+
+      /* The result is converted to 1.31 */
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* Read the third input into Xn1, to reuse the value */
+      Xn1 = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn1 = Xn1 << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn1, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn2, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* The result is converted to 1.63, Yn2 variable is reused  */
+      Yn2 = acc << shift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* Read the fourth input into Xn, to reuse the value */
+      Xn = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn = Xn << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn1, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn2, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn2, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn1, a2);
+
+      /* The result is converted to 1.63, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn = Xn << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn1, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn2, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc << shift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage output is given as input to the second stage. */
+    pIn = pDst;
+
+    /* Reset to destination buffer working pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* The variable acc hold output value that is being computed and       
+     * stored in the destination buffer           
+     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]           
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn = Xn << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn1, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn2, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc << shift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage output is given as input to the second stage. */
+    pIn = pDst;
+
+    /* Reset to destination buffer working pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*    #ifndef ARM_MATH_CM0     */
+}
+
+  /**   
+   * @} end of BiquadCascadeDF1_32x64 group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
new file mode 100644
index 0000000..bdfbf22
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
@@ -0,0 +1,418 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_f32.c   
+*   
+* Description:	Processing function for the   
+*               floating-point Biquad cascade DirectFormI(DF1) filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure   
+ *   
+ * This set of functions implements arbitrary order recursive (IIR) filters.   
+ * The filters are implemented as a cascade of second order Biquad sections.   
+ * The functions support Q15, Q31 and floating-point data types. 
+ * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.   
+ *   
+ * The functions operate on blocks of input and output data and each call to the function   
+ * processes blockSize samples through the filter.   
+ * pSrc points to the array of input data and   
+ * pDst points to the array of output data.   
+ * Both arrays contain blockSize values.   
+ *   
+ * \par Algorithm   
+ * Each Biquad stage implements a second order filter using the difference equation:   
+ * 
   
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+ * 
   
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.   
+ * \image html Biquad.gif "Single Biquad filter stage"   
+ * Coefficients b0, b1 and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.   
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.   
+ * Pay careful attention to the sign of the feedback coefficients.   
+ * Some design tools use the difference equation   
+ * 
   
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]   
+ * 
   
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.   
+ *   
+ * \par   
+ * Higher order filters are realized as a cascade of second order sections.   
+ * numStages refers to the number of second order stages used.   
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.   
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"   
+ * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).   
+ *   
+ * \par   
+ * The pState points to state variables array.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the pState array as:   
+ * 
   
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
   
+ *   
+ * \par   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Init Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * The code below statically initializes each of the 3 different data type filter instance structures   
+ * 
   
+ *     arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};   
+ *     arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};   
+ *     arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};   
+ * 
   
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer; postShift shift to be applied.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.   
+ * Following issues must be considered:   
+ * - Scaling of coefficients   
+ * - Filter gain   
+ * - Overflow and saturation   
+ *   
+ * \par   
+ * Scaling of coefficients:    
+ * Filter coefficients are represented as fractional values and   
+ * coefficients are restricted to lie in the range [-1 +1).   
+ * The fixed-point functions have an additional scaling parameter postShift   
+ * which allow the filter coefficients to exceed the range [+1 -1).   
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.   
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"   
+ * This essentially scales the filter coefficients by 2^postShift.   
+ * For example, to realize the coefficients   
+ * 
   
+ *    {1.5, -0.8, 1.2, 1.6, -0.9}   
+ * 
   
+ * set the pCoeffs array to:   
+ * 
   
+ *    {0.75, -0.4, 0.6, 0.8, -0.45}   
+ * 
   
+ * and set postShift=1   
+ *   
+ * \par   
+ * Filter gain:    
+ * The frequency response of a Biquad filter is a function of its coefficients.   
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.   
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.   
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.   
+ *   
+ * \par   
+ * Overflow and saturation:    
+ * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.   
+ * @param[in]  *pSrc      points to the block of input data.   
+ * @param[out] *pDst      points to the block of output data.   
+ * @param[in]  blockSize  number of samples to process per call.   
+ * @return     none.   
+ *   
+ */
+
+void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /*  source pointer            */
+  float32_t *pOut = pDst;                        /*  destination pointer       */
+  float32_t *pState = S->pState;                 /*  pState pointer            */
+  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+  float32_t acc;                                 /*  Simulates the accumulator */
+  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+  float32_t Xn1, Xn2, Yn1, Yn2;                  /*  Filter pState variables   */
+  float32_t Xn;                                  /*  temporary input           */
+  uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the pState values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:   
+     *   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]   
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the first input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the third input */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as: */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = blockSize & 0x3u;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:    */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent numStages  occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the pState values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:       
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]       
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:    */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent numStages  occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#endif /*   #ifndef ARM_MATH_CM0         */
+
+}
+
+
+  /**   
+   * @} end of BiquadCascadeDF1 group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
new file mode 100644
index 0000000..c2ac802
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
@@ -0,0 +1,283 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_fast_q15.c   
+*   
+* Description:	Fast processing function for the   
+*				Q15 Biquad cascade filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.9  2010/08/16    
+*    Initial version   
+*   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).   
+ * The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.   
+ *   
+ * \par   
+ * Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure.   
+ *   
+ */
+
+void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q31_t in;                                      /*  Temporary variable to hold input value       */
+  q31_t out;                                     /*  Temporary variable to hold output value      */
+  q31_t b0;                                      /*  Temporary variable to hold bo value          */
+  q31_t b1, a1;                                  /*  Filter coefficients                          */
+  q31_t state_in, state_out;                     /*  Filter state variables                       */
+  q31_t acc0;                                    /*  Accumulator                                  */
+  int32_t shift = (int32_t) (15 - S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  q31_t *pState_q31;                             /*  32-bit state pointer for SIMD implementation */
+  uint32_t sample, stage = S->numStages;         /*  Stage loop counter                           */
+
+
+
+  do
+  {
+    /* Initialize state pointer of type q31 */
+    pState_q31 = (q31_t *) (pState);
+
+    /* Read the b0 and 0 coefficients using SIMD  */
+    b0 = *__SIMD32(pCoeffs)++;
+
+    /* Read the b1 and b2 coefficients using SIMD */
+    b1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the a1 and a2 coefficients using SIMD */
+    a1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
+    state_in = (q31_t) (*pState_q31++);
+
+    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
+    state_out = (q31_t) (*pState_q31);
+
+    /* Apply loop unrolling and compute 2 output values simultaneously. */
+    /*      The variables acc0 ... acc3 hold output values that are being computed:   
+     *   
+     *    acc0 =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     *    acc0 =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+    sample = blockSize >> 1u;
+
+    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.   
+     ** a second loop below computes the remaining 1 sample. */
+    while(sample > 0u)
+    {
+
+      /* Read the input */
+      in = *__SIMD32(pIn)++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUAD(b0, in);
+      /* acc0 =  b1 * x[n-1] + acc0 +=  b2 * x[n-2] + out */
+      acc0 = __SMLAD(b1, state_in, out);
+      /* acc0 +=  a1 * y[n-1] + acc0 +=  a2 * y[n-2] */
+      acc0 = __SMLAD(a1, state_out, acc0);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc0 >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc0   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+      state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUADX(b0, in);
+      /* acc0 =  b1 * x[n-1] + acc0 +=  b2 * x[n-2] + out */
+      acc0 = __SMLAD(b1, state_in, out);
+      /* acc0 +=  a1 * y[n-1] + acc0 +=  a2 * y[n-2] */
+      acc0 = __SMLAD(a1, state_out, acc0);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc0 >> shift), 16);
+
+
+      /* Store the output in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc0   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in >> 16, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+      /* Decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+
+    if((blockSize & 0x1u) != 0u)
+    {
+      /* Read the input */
+      in = *pIn++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      out = __SMUAD(b0, in);
+
+#else
+
+      out = __SMUADX(b0, in);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* acc0 =  b1 * x[n-1] + acc0 +=  b2 * x[n-2] + out */
+      acc0 = __SMLAD(b1, state_in, out);
+      /* acc0 +=  a1 * y[n-1] + acc0 +=  a2 * y[n-2] */
+      acc0 = __SMLAD(a1, state_out, acc0);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc0 >> shift), 16);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) out;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc0   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer.  */
+    /*  Subsequent (numStages - 1) occur in-place in the output buffer  */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the state array */
+    *__SIMD32(pState)++ = state_in;
+    *__SIMD32(pState)++ = state_out;
+
+
+    /* Decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+}
+
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
new file mode 100644
index 0000000..1242ae7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
@@ -0,0 +1,271 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_fast_q31.c   
+*   
+* Description:	Processing function for the   
+*				Q31 Fast Biquad cascade DirectFormI(DF1) filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.9  2010/08/27    
+*    Initial version   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in]  *S        points to an instance of the Q31 Biquad cascade structure.   
+ * @param[in]  *pSrc     points to the block of input data.   
+ * @param[out] *pDst     points to the block of output data.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return 	   none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are added to a 2.30 accumulator.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function   
+ * arm_biquad_cascade_df1_init_q31() to initialize filter structure.   
+ *   
+ * \par   
+ * Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.  Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure.   
+ */
+
+void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q31_t *pState = S->pState;                     /*  pState pointer initialization */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q31_t acc;                                     /*  accumulator                   */
+  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t Xn;                                      /*  temporary input               */
+  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variables acc ... acc3 hold output values that are being computed:   
+     *   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * Xn) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+
+      /* The result is converted to 1.31 , Yn2 variable is reused */
+      Yn2 = acc << shift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Read the third input  */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+
+      /* The result is converted to 1.31, Yn2 variable is reused  */
+      Yn2 = acc << shift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+      /* The result is converted to 1.31  */
+      acc = acc << shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+}
+
+/**   
+  * @} end of BiquadCascadeDF1 group   
+  */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
new file mode 100644
index 0000000..e3e5a85
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
@@ -0,0 +1,104 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_biquad_cascade_df1_init_f32.c   
+*   
+* Description:  floating-point Biquad cascade DirectFormI(DF1) filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @brief  Initialization function for the floating-point Biquad cascade filter.   
+ * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.   
+ * @param[in]     numStages    number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs     points to the filter coefficients array.   
+ * @param[in]     *pState      points to the state array.   
+ * @return        none   
+ *   
+ *   
+ * Coefficient and State Ordering:   
+ *   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
   
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ * 
   
+ *   
+ * \par   
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.   
+ *   
+ * \par   
+ * The pState is a pointer to state array.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the pState array as:   
+ * 
   
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ *   
+ */
+
+void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
new file mode 100644
index 0000000..42c60fb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
@@ -0,0 +1,106 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_biquad_cascade_df1_init_q15.c   
+*   
+* Description:  Q15 Biquad cascade DirectFormI(DF1) filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.   
+ * @param[in]     numStages    number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs     points to the filter coefficients.   
+ * @param[in]     *pState      points to the state buffer.   
+ * @param[in]     postShift    Shift to be applied to the accumulator result. Varies according to the coefficients format   
+ * @return        none   
+ *   
+ * Coefficient and State Ordering:   
+ *   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
   
+ *     {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}   
+ * 
   
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 6*numStages values.   
+ * The zero coefficient between b1 and b2 facilities  use of 16-bit SIMD instructions on the Cortex-M4.   
+ *   
+ * \par   
+ * The state variables are stored in the array pState.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the pState array as:   
+ * 
   
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ */
+
+void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
new file mode 100644
index 0000000..2e6028e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
@@ -0,0 +1,106 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_init_q31.c   
+*   
+* Description:	Q31 Biquad cascade DirectFormI(DF1) filter initialization function.   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.   
+ * @param[in]     numStages    number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs     points to the filter coefficients buffer.   
+ * @param[in]     *pState      points to the state buffer.   
+ * @param[in]     postShift    Shift to be applied after the accumulator.  Varies according to the coefficients format   
+ * @return        none   
+ *   
+ * Coefficient and State Ordering:   
+ *   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
   
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ * 
   
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.   
+ *   
+ * \par   
+ * The pState points to state variables array.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the pState array as:   
+ * 
   
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ */
+
+void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
new file mode 100644
index 0000000..9e7bd01
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
@@ -0,0 +1,380 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_q15.c   
+*   
+* Description:	Processing function for the   
+*				Q15 Biquad cascade DirectFormI(DF1) filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 Biquad cascade filter.   
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the location where the output result is written.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits.   
+ * Finally, the result is saturated to 1.15 format.   
+ *   
+ * \par   
+ * Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q31_t in;                                      /*  Temporary variable to hold input value       */
+  q31_t out;                                     /*  Temporary variable to hold output value      */
+  q31_t b0;                                      /*  Temporary variable to hold bo value          */
+  q31_t b1, a1;                                  /*  Filter coefficients                          */
+  q31_t state_in, state_out;                     /*  Filter state variables                       */
+  q63_t acc;                                     /*  Accumulator                                  */
+  int32_t shift = (15 - (int32_t) S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  q31_t *pState_q31;                             /*  32-bit state pointer for SIMD implementation */
+  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
+
+  do
+  {
+    /* Initialize state pointer of type q31 */
+    pState_q31 = (q31_t *) (pState);
+
+    /* Read the b0 and 0 coefficients using SIMD  */
+    b0 = *__SIMD32(pCoeffs)++;
+
+    /* Read the b1 and b2 coefficients using SIMD */
+    b1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the a1 and a2 coefficients using SIMD */
+    a1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
+    state_in = (q31_t) (*pState_q31++);
+
+    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
+    state_out = (q31_t) (*pState_q31);
+
+    /* Apply loop unrolling and compute 2 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:   
+     *   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+    sample = blockSize >> 1u;
+
+    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.   
+     ** a second loop below computes the remaining 1 sample. */
+    while(sample > 0u)
+    {
+
+      /* Read the input */
+      in = *__SIMD32(pIn)++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUAD(b0, in);
+
+      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] +  a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+      state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUADX(b0, in);
+      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Store the output in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in >> 16, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+      /* Decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+
+    if((blockSize & 0x1u) != 0u)
+    {
+      /* Read the input */
+      in = *pIn++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      out = __SMUAD(b0, in);
+
+#else
+
+      out = __SMUADX(b0, in);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* acc =  b1 * x[n-1] + b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) out;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    }
+
+    /*  The first stage goes from the input wire to the output wire.  */
+    /*  Subsequent numStages occur in-place in the output wire  */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the state array */
+    *__SIMD32(pState)++ = state_in;
+    *__SIMD32(pState)++ = state_out;
+
+
+    /* Decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q15_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q15_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q15_t Xn;                                      /*  temporary input               */
+  q63_t acc;                                     /*  Accumulator                                  */
+  int32_t shift = (15 - (int32_t) S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:        
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]        
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) b0 *Xn;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q31_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q31_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q31_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q31_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = __SSAT((acc >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q15_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*     #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
new file mode 100644
index 0000000..0687227
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
@@ -0,0 +1,362 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_q31.c   
+*   
+* Description:	Processing function for the   
+*				Q31 Biquad cascade filter   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 Biquad cascade filter.   
+ * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.   
+ * @param[in]  *pSrc      points to the block of input data.   
+ * @param[out] *pDst      points to the block of output data.   
+ * @param[in]  blockSize  number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).   
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to   
+ * 1.31 format by discarding the low 32 bits.   
+ *   
+ * \par   
+ * Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q31_t *pState = S->pState;                     /*  pState pointer initialization */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q63_t acc;                                     /*  accumulator                   */
+  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t Xn;                                      /*  temporary input               */
+  uint32_t shift = 32u - ((uint32_t) S->postShift + 1u);        /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:   
+     *   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31 , Yn2 variable is reused */
+      Yn2 = (q31_t) (acc >> shift);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn2;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn1;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn2;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn1;
+
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = (q31_t) (acc >> shift);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Read the third input  */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn1;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn2;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31, Yn2 variable is reused  */
+      Yn2 = (q31_t) (acc >> shift);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn2;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn1;
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = (q31_t) (acc >> shift);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = acc >> shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q31_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:        
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]        
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = acc >> shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q31_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+}
+
+/**   
+  * @} end of BiquadCascadeDF1 group   
+  */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
new file mode 100644
index 0000000..4cf4217
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
@@ -0,0 +1,359 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df2T_f32.c   
+*   
+* Description:  Processing function for the floating-point transposed   
+*               direct form II Biquad cascade filter.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure   
+ *   
+ * This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.   
+ * The filters are implemented as a cascade of second order Biquad sections.   
+ * These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.  
+ * Only floating-point data is supported.   
+ *   
+ * This function operate on blocks of input and output data and each call to the function   
+ * processes blockSize samples through the filter.   
+ * pSrc points to the array of input data and   
+ * pDst points to the array of output data.   
+ * Both arrays contain blockSize values.   
+ *   
+ * \par Algorithm   
+ * Each Biquad stage implements a second order filter using the difference equation:   
+ * 
   
+ *    y[n] = b0 * x[n] + d1   
+ *    d1 = b1 * x[n] + a1 * y[n] + d2   
+ *    d2 = b2 * x[n] + a2 * y[n]   
+ * 
   
+ * where d1 and d2 represent the two state values.   
+ *   
+ * \par   
+ * A Biquad filter using a transposed Direct Form II structure is shown below.   
+ * \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"   
+ * Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.   
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.   
+ * Pay careful attention to the sign of the feedback coefficients.   
+ * Some design tools flip the sign of the feedback coefficients:   
+ * 
   
+ *    y[n] = b0 * x[n] + d1;   
+ *    d1 = b1 * x[n] - a1 * y[n] + d2;   
+ *    d2 = b2 * x[n] - a2 * y[n];   
+ * 
   
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.   
+ *   
+ * \par   
+ * Higher order filters are realized as a cascade of second order sections.   
+ * numStages refers to the number of second order stages used.   
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.   
+ * A 9th order filter would be realized with numStages=5 second order stages with the   
+ * coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).   
+ *   
+ * \par   
+ * pState points to the state variable array.   
+ * Each Biquad stage has 2 state variables d1 and d2.   
+ * The state variables are arranged in the pState array as:   
+ * 
   
+ *     {d11, d12, d21, d22, ...}   
+ * 
   
+ * where d1x refers to the state variables for the first Biquad and   
+ * d2x refers to the state variables for the second Biquad.   
+ * The state array has a total length of 2*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ *   
+ * \par   
+ * The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.   
+ * The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.   
+ * That is why the Direct Form I structure supports Q15 and Q31 data types.   
+ * The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.   
+ * Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.   
+ * The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ *   
+ * \par Init Functions   
+ * There is also an associated initialization function.  
+ * The initialization function performs following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * For example, to statically initialize the instance structure use   
+ * 
   
+ *     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};   
+ * 
   
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.   
+ * pCoeffs is the address of the coefficient buffer;    
+ *   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF2T   
+ * @{   
+ */
+
+/**  
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.  
+ * @param[in]  *S        points to an instance of the filter data structure.  
+ * @param[in]  *pSrc     points to the block of input data.  
+ * @param[out] *pDst     points to the block of output data  
+ * @param[in]  blockSize number of samples to process.  
+ * @return none.  
+ */
+
+void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+
+  float32_t *pIn = pSrc;                         /*  source pointer            */
+  float32_t *pOut = pDst;                        /*  destination pointer       */
+  float32_t *pState = S->pState;                 /*  State pointer            */
+  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+  float32_t acc0;                                /*  Simulates the accumulator */
+  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+  float32_t Xn;                                  /*  temporary input           */
+  float32_t d1, d2;                              /*  state variables          */
+  uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /*Reading the state values */
+    d1 = pState[0];
+    d2 = pState[1];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the first input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* Read the second input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* Read the third input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* Read the fourth input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = (b1 * Xn) + (a1 * acc0) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = blockSize & 0x3u;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* Store the updated state variables back into the state array */
+    *pState++ = d1;
+    *pState++ = d2;
+
+    /* The current stage input is given as the output to the next stage */
+    pIn = pDst;
+
+    /*Reset the output working pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /*Reading the state values */
+    d1 = pState[0];
+    d2 = pState[1];
+
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* Store the updated state variables back into the state array */
+    *pState++ = d1;
+    *pState++ = d2;
+
+    /* The current stage input is given as the output to the next stage */
+    pIn = pDst;
+
+    /*Reset the output working pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#endif /*  #ifndef ARM_MATH_CM0         */
+
+}
+
+
+  /**   
+   * @} end of BiquadCascadeDF2T group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
new file mode 100644
index 0000000..5527785
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
@@ -0,0 +1,94 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_biquad_cascade_df2T_init_f32.c   
+*   
+* Description:  Initialization function for the floating-point transposed  
+*               direct form II Biquad cascade filter.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF2T   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.  
+ * @param[in,out] *S           points to an instance of the filter data structure.  
+ * @param[in]     numStages    number of 2nd order stages in the filter.  
+ * @param[in]     *pCoeffs     points to the filter coefficients.  
+ * @param[in]     *pState      points to the state buffer.  
+ * @return        none  
+ *   
+ * Coefficient and State Ordering:   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
   
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ * 
   
+ *   
+ * \par   
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.   
+ *   
+ * \par   
+ * The pState is a pointer to state array.   
+ * Each Biquad stage has 2 state variables d1, and d2.   
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.   
+ * The state array has a total length of 2*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ */
+
+void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 2 * numStages */
+  memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF2T group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
new file mode 100644
index 0000000..db3990c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
@@ -0,0 +1,623 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_f32.c   
+*   
+* Description:	Convolution of floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup Conv Convolution   
+ *   
+ * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.   
+ * Convolution is similar to correlation and is frequently used in filtering and data analysis.   
+ * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.   
+ * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.   
+ *   
+ * \par Algorithm   
+ * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.   
+ * Then the convolution   
+ *   
+ * 
   
+ *                   c[n] = a[n] * b[n]   
+ * 
   
+ *   
+ * \par   
+ * is defined as   
+ * \image html ConvolutionEquation.gif   
+ * \par   
+ * Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2.   
+ * pSrcA points to the first input vector of length srcALen and   
+ * pSrcB points to the second input vector of length srcBLen.   
+ * The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.   
+ *   
+ * \par   
+ * Conceptually, when two signals a[n] and b[n] are convolved,   
+ * the signal b[n] slides over a[n].   
+ * For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.   
+ *   
+ * \par   
+ * Note that convolution is a commutative operation:   
+ *   
+ * 
   
+ *                   a[n] * b[n] = b[n] * a[n].   
+ * 
   
+ *   
+ * \par   
+ * This means that switching the A and B arguments to the convolution functions has no effect.   
+ *   
+ * Fixed-Point Behavior   
+ *   
+ * \par   
+ * Convolution requires summing up a large number of intermediate products.   
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.   
+ * Refer to the function specific documentation below for further details of the particular algorithm used.   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of floating-point sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ */
+
+void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1;                               /* inputA pointer */
+  float32_t *pIn2;                               /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counters */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum += *px++ * *py--;
+
+      /* x[1] * y[srcBLen - 2] */
+      sum += *px++ * *py--;
+
+      /* x[2] * y[srcBLen - 3] */
+      sum += *px++ * *py--;
+
+      /* x[3] * y[srcBLen - 4] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 += x0 * c0;
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 += x1 * c0;
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 += x2 * c0;
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 += x3 * c0;
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 += x1 * c0;
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 += x2 * c0;
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 += x3 * c0;
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 += x0 * c0;
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 += x2 * c0;
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 += x3 * c0;
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 += x0 * c0;
+        /* acc3 +=  x[5] * y[srcBLen - 2] */
+        acc3 += x1 * c0;
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 += x3 * c0;
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 += x0 * c0;
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 += x1 * c0;
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 += x2 * c0;
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += x3 * c0;
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+      *pOut++ = acc1;
+      *pOut++ = acc2;
+      *pOut++ = acc3;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i < ((srcALen + srcBLen) - 1u); i++)
+  {
+    /* Initialize sum with zero to carry out MAC operations */
+    sum = 0.0f;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += pIn1[j] * pIn2[i - j];
+      }
+    }
+    /* Store the output in the destination buffer */
+    pDst[i] = sum;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
new file mode 100644
index 0000000..70038f8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
@@ -0,0 +1,677 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_fast_q15.c   
+*   
+* Description:	Fast Q15 Convolution.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results   
+ * but provides only a single guard bit. There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.   
+ */
+
+void arm_conv_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between   
+     * inputA samples and inputB samples */
+    k = count;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:   
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1u);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* Initialize inputB pointer of type q31 */
+  pb = (q31_t *) (py - 1u);
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *(q31_t *) (px++);
+      /* read x[1], x[2] samples */
+      x1 = *(q31_t *) (px++);
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *(pb--);
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLADX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLADX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *(q31_t *) (px++);
+
+        /* Read x[3], x[4] */
+        x3 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLADX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLADX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *(pb--);
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLADX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLADX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = *(q31_t *) (px++);
+
+        /* Read x[5], x[6] */
+        x1 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLADX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLADX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+      py = (q15_t *) pb;
+      py = py + 1;
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+//          c0 = unallign_rev(p, c0); 
+        c0 = c0 << 16;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = *(pb);
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = *pb--;
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+
+        /* Read y[srcBLen - 7] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = (*pb);
+//              c0 = (c0 & 0x0000FFFF)<<16;     
+        c0 = (c0) << 16;
+
+#else
+
+        c0 = (q15_t) (*pb >> 16);
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);
+      *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);
+      *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+      pb = (q31_t *) (py - 1);
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  pIn2 = pSrc2 - 1u;
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2u;
+
+  while((j > 0u) && (blockSize3 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,   
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1u;
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
new file mode 100644
index 0000000..d1eeeac
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
@@ -0,0 +1,567 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_fast_q31.c   
+*   
+* Description:	Q31 Convolution (fast version).   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ *   
+ * \par   
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signals must be scaled down.   
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   
+ *   
+ * \par   
+ * See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.   
+ */
+
+void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+  q31_t *pIn1;                                   /* inputA pointer */
+  q31_t *pIn2;                                   /* inputB pointer */
+  q31_t *pOut = pDst;                            /* output pointer */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[1] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[2] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[3] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum << 1;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc3 +=  x[5] * y[srcBLen - 2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = (q31_t) (acc0 << 1);
+      *pOut++ = (q31_t) (acc1 << 1);
+      *pOut++ = (q31_t) (acc2 << 1);
+      *pOut++ = (q31_t) (acc3 << 1);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum << 1;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
new file mode 100644
index 0000000..74b8c8e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
@@ -0,0 +1,641 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_f32.c   
+*   
+* Description:	Partial convolution of floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup PartialConv Partial Convolution   
+ *   
+ * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.   
+ * Each function has two additional arguments.   
+ * firstIndex specifies the starting index of the subset of output samples.   
+ * numPoints is the number of output samples to compute.   
+ * The function computes the output in the range   
+ * [firstIndex, ..., firstIndex+numPoints-1].   
+ * The output array pDst contains numPoints values.   
+ *   
+ * The allowable range of output indices is [0 srcALen+srcBLen-2].   
+ * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.   
+ * Otherwise the functions return ARM_MATH_SUCCESS.   
+ * \note Refer arm_conv_f32() for details on fixed point behavior.  
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of floating-point sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ */
+
+arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count = 0u, blkCnt, check;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = (int32_t) check - (int32_t) srcALen;
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = ((int32_t) check - blockSize3) -
+      (blockSize1 + (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc1 = pIn2 + firstIndex;
+    py = pSrc1;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first stage starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum += *px++ * *py--;
+
+        /* x[1] * y[srcBLen - 2] */
+        sum += *px++ * *py--;
+
+        /* x[2] * y[srcBLen - 3] */
+        sum += *px++ * *py--;
+
+        /* x[3] * y[srcBLen - 4] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc1;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0.0f;
+        acc1 = 0.0f;
+        acc2 = 0.0f;
+        acc3 = 0.0f;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 += x0 * c0;
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 += x1 * c0;
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 += x2 * c0;
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 += x3 * c0;
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 += x1 * c0;
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 += x2 * c0;
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 += x3 * c0;
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 += x0 * c0;
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 += x2 * c0;
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 += x3 * c0;
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 += x0 * c0;
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 += x1 * c0;
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 += x3 * c0;
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 += x0 * c0;
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 += x1 * c0;
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 += x2 * c0;
+
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += x0 * c0;
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += x1 * c0;
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += x2 * c0;
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += x3 * c0;
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = acc0;
+        *pOut++ = acc1;
+        *pOut++ = acc2;
+        *pOut++ = acc3;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0.0f;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0.0f;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0.0f;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0u; j <= i; j++)
+      {
+        /* Check the array limitations for inputs */
+        if((((i - j) < srcBLen) && (j < srcALen)))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += pIn1[j] * pIn2[i - j];
+        }
+      }
+      /* Store the output in the destination buffer */
+      pDst[i] = sum;
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
new file mode 100644
index 0000000..dcb4ed7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
@@ -0,0 +1,705 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_fast_q15.c   
+*   
+* Description:	Fast Q15 Partial convolution.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
+ */
+
+
+arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    while((count < 4u) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between   
+       * inputA samples and inputB samples */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:   
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1u;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* Initialize inputB pointer of type q31 */
+    pb = (q31_t *) (py - 1u);
+
+    /* count is the index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+
+    /* --------------------   
+     * Stage2 process   
+     * -------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+
+        /* read x[0], x[1] samples */
+        x0 = *(q31_t *) (px++);
+        /* read x[1], x[2] samples */
+        x1 = *(q31_t *) (px++);
+
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read the last two inputB samples using SIMD:   
+           * y[srcBLen - 1] and y[srcBLen - 2] */
+          c0 = *(pb--);
+
+          /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+          acc0 = __SMLADX(x0, c0, acc0);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+          acc1 = __SMLADX(x1, c0, acc1);
+
+          /* Read x[2], x[3] */
+          x2 = *(q31_t *) (px++);
+
+          /* Read x[3], x[4] */
+          x3 = *(q31_t *) (px++);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+          acc2 = __SMLADX(x2, c0, acc2);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+          acc3 = __SMLADX(x3, c0, acc3);
+
+          /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+          c0 = *(pb--);
+
+          /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+          acc0 = __SMLADX(x2, c0, acc0);
+
+          /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+          acc1 = __SMLADX(x3, c0, acc1);
+
+          /* Read x[4], x[5] */
+          x0 = *(q31_t *) (px++);
+
+          /* Read x[5], x[6] */
+          x1 = *(q31_t *) (px++);
+
+          /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+          acc2 = __SMLADX(x0, c0, acc2);
+
+          /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+          acc3 = __SMLADX(x1, c0, acc3);
+
+        } while(--k);
+
+        /* For the next MAC operations, SIMD is not used   
+         * So, the 16 bit pointer if inputB, py is updated */
+        py = (q15_t *) pb;
+        py = py + 1;
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        if(k == 1u)
+        {
+          /* Read y[srcBLen - 5] */
+          c0 = *(py);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+          c0 = c0 << 16;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[7] */
+          x3 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLAD(x0, c0, acc0);
+          acc1 = __SMLAD(x1, c0, acc1);
+          acc2 = __SMLADX(x1, c0, acc2);
+          acc3 = __SMLADX(x3, c0, acc3);
+        }
+
+        if(k == 2u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+          c0 = *(pb);
+
+          /* Read x[7], x[8] */
+          x3 = *(q31_t *) px++;
+
+          /* Read x[9] */
+          x2 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x0, c0, acc0);
+          acc1 = __SMLADX(x1, c0, acc1);
+          acc2 = __SMLADX(x3, c0, acc2);
+          acc3 = __SMLADX(x2, c0, acc3);
+        }
+
+        if(k == 3u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+          c0 = *pb--;
+
+          /* Read x[7], x[8] */
+          x3 = *(q31_t *) px++;
+
+          /* Read x[9] */
+          x2 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x0, c0, acc0);
+          acc1 = __SMLADX(x1, c0, acc1);
+          acc2 = __SMLADX(x3, c0, acc2);
+          acc3 = __SMLADX(x2, c0, acc3);
+
+          /* Read y[srcBLen - 7] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+          c0 = (*pb);
+          c0 = (c0) << 16;
+
+#else
+
+          c0 = (q15_t) (*pb >> 16);
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[10] */
+          x3 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x1, c0, acc0);
+          acc1 = __SMLAD(x2, c0, acc1);
+          acc2 = __SMLADX(x2, c0, acc2);
+          acc3 = __SMLADX(x3, c0, acc3);
+        }
+
+        /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);
+        *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);
+
+#else
+
+        *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);
+        *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+        pb = (q31_t *) (py - 1);
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    pIn2 = pSrc2 - 1u;
+    py = pIn2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2u;
+
+    while((j > 0u) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,   
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1u;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
new file mode 100644
index 0000000..0b84805
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
@@ -0,0 +1,593 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_fast_q31.c   
+*   
+* Description:	Fast Q31 Partial convolution.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * \par   
+ * See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.   
+ */
+
+arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first loop starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[1] * y[srcBLen - 2] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[2] * y[srcBLen - 3] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[3] * y[srcBLen - 4] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (acc0 << 1);
+        *pOut++ = (q31_t) (acc1 << 1);
+        *pOut++ = (q31_t) (acc2 << 1);
+        *pOut++ = (q31_t) (acc3 << 1);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum << 1;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum << 1;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
new file mode 100644
index 0000000..4a74726
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
@@ -0,0 +1,765 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_q15.c   
+*   
+* Description:	Partial convolution of Q15 sequences.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q15 sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+
+arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary input variables */
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
+  arm_status status;                             /* status of Partial convolution */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    while((count < 4u) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between   
+       * inputA samples and inputB samples */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:   
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1u;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* Initialize inputB pointer of type q31 */
+    pb = (q31_t *) (py - 1u);
+
+    /* count is the index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+
+    /* --------------------   
+     * Stage2 process   
+     * -------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+
+        /* read x[0], x[1] samples */
+        x0 = *(q31_t *) (px++);
+        /* read x[1], x[2] samples */
+        x1 = *(q31_t *) (px++);
+
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read the last two inputB samples using SIMD:   
+           * y[srcBLen - 1] and y[srcBLen - 2] */
+          c0 = *(pb--);
+
+          /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+          acc0 = __SMLALDX(x0, c0, acc0);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+          acc1 = __SMLALDX(x1, c0, acc1);
+
+          /* Read x[2], x[3] */
+          x2 = *(q31_t *) (px++);
+
+          /* Read x[3], x[4] */
+          x3 = *(q31_t *) (px++);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+          acc2 = __SMLALDX(x2, c0, acc2);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+          acc3 = __SMLALDX(x3, c0, acc3);
+
+          /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+          c0 = *(pb--);
+
+          /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+          acc0 = __SMLALDX(x2, c0, acc0);
+
+          /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+          acc1 = __SMLALDX(x3, c0, acc1);
+
+          /* Read x[4], x[5] */
+          x0 = *(q31_t *) (px++);
+
+          /* Read x[5], x[6] */
+          x1 = *(q31_t *) (px++);
+
+          /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+          acc2 = __SMLALDX(x0, c0, acc2);
+
+          /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+          acc3 = __SMLALDX(x1, c0, acc3);
+
+        } while(--k);
+
+        /* For the next MAC operations, SIMD is not used   
+         * So, the 16 bit pointer if inputB, py is updated */
+        py = (q15_t *) pb;
+        py = py + 1;
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        if(k == 1u)
+        {
+          /* Read y[srcBLen - 5] */
+          c0 = *(py);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+          c0 = c0 << 16u;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+          /* Read x[7] */
+          x3 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLALD(x0, c0, acc0);
+          acc1 = __SMLALD(x1, c0, acc1);
+          acc2 = __SMLALDX(x1, c0, acc2);
+          acc3 = __SMLALDX(x3, c0, acc3);
+        }
+
+        if(k == 2u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+          c0 = *(pb);
+
+          /* Read x[7], x[8] */
+          x3 = *(q31_t *) px++;
+
+          /* Read x[9] */
+          x2 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLALDX(x0, c0, acc0);
+          acc1 = __SMLALDX(x1, c0, acc1);
+          acc2 = __SMLALDX(x3, c0, acc2);
+          acc3 = __SMLALDX(x2, c0, acc3);
+        }
+
+        if(k == 3u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+          c0 = *pb--;
+
+          /* Read x[7], x[8] */
+          x3 = *(q31_t *) px++;
+
+          /* Read x[9] */
+          x2 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLALDX(x0, c0, acc0);
+          acc1 = __SMLALDX(x1, c0, acc1);
+          acc2 = __SMLALDX(x3, c0, acc2);
+          acc3 = __SMLALDX(x2, c0, acc3);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+          /* Read y[srcBLen - 7] */
+          c0 = (*pb);
+          c0 = (c0) << 16;
+
+#else
+
+          /* Read y[srcBLen - 7] */
+          c0 = (q15_t) (*pb >> 16);
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[10] */
+          x3 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLALDX(x1, c0, acc0);
+          acc1 = __SMLALD(x2, c0, acc1);
+          acc2 = __SMLALDX(x2, c0, acc2);
+          acc3 = __SMLALDX(x3, c0, acc3);
+        }
+
+        /* Store the results in the accumulators in the destination buffer. */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+        *__SIMD32(pOut)++ =
+          __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+        *__SIMD32(pOut)++ =
+          __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+        *__SIMD32(pOut)++ =
+          __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+        *__SIMD32(pOut)++ =
+          __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+        pb = (q31_t *) (py - 1);
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    pIn2 = pSrc2 - 1u;
+    py = pIn2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2u;
+
+    while((j > 0u) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,   
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1u;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* inputA pointer */
+  q15_t *pIn2 = pSrcB;                           /* inputB pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q31_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*     #ifndef ARM_MATH_CM0      */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
new file mode 100644
index 0000000..a592d74
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
@@ -0,0 +1,616 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_q31.c   
+*   
+* Description:	Partial convolution of Q31 sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q31 sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first loop starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[1] * y[srcBLen - 2] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[2] * y[srcBLen - 3] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[3] * y[srcBLen - 4] */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 += (q63_t) x0 *c0;
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 += (q63_t) x1 *c0;
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 += (q63_t) x2 *c0;
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 += (q63_t) x3 *c0;
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 += (q63_t) x1 *c0;
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 += (q63_t) x2 *c0;
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 += (q63_t) x3 *c0;
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 += (q63_t) x0 *c0;
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 += (q63_t) x2 *c0;
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 += (q63_t) x3 *c0;
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 += (q63_t) x0 *c0;
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 += (q63_t) x1 *c0;
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 += (q63_t) x3 *c0;
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 += (q63_t) x0 *c0;
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 += (q63_t) x1 *c0;
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 += (q63_t) x2 *c0;
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += (q63_t) x0 *c0;
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += (q63_t) x1 *c0;
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += (q63_t) x2 *c0;
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += (q63_t) x3 *c0;
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (acc0 >> 31);
+        *pOut++ = (q31_t) (acc1 >> 31);
+        *pOut++ = (q31_t) (acc2 >> 31);
+        *pOut++ = (q31_t) (acc3 >> 31);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (sum >> 31);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (sum >> 31);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The blockSize3 variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* inputA pointer */
+  q31_t *pIn2 = pSrcB;                           /* inputB pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q31_t) (sum >> 31u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*    #ifndef ARM_MATH_CM0      */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
new file mode 100644
index 0000000..d49903f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
@@ -0,0 +1,723 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_q7.c   
+*   
+* Description:	Partial convolution of Q7 sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q7 sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ */
+
+arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer */
+  q7_t *pIn2;                                    /* inputB pointer */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t *px;                                      /* Intermediate inputA pointer */
+  q7_t *py;                                      /* Intermediate inputB pointer */
+  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t input1, input2;
+  q15_t in1, in2;
+  q7_t x0, x1, x2, x3, c0, c1;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter */
+  arm_status status;
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first stage starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] , x[1] */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[srcBLen - 1] , y[srcBLen - 2] */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* x[0] * y[srcBLen - 1] */
+        /* x[1] * y[srcBLen - 2] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* x[2] , x[3] */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[srcBLen - 3] , y[srcBLen - 4] */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* x[2] * y[srcBLen - 3] */
+        /* x[3] * y[srcBLen - 4] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+          /* Read y[srcBLen - 2] sample */
+          c1 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* x[0] and x[1] are packed */
+          in1 = (q15_t) x0;
+          in2 = (q15_t) x1;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
+          in1 = (q15_t) c0;
+          in2 = (q15_t) c1;
+
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
+          acc0 = __SMLAD(input1, input2, acc0);
+
+          /* x[1] and x[2] are packed */
+          in1 = (q15_t) x1;
+          in2 = (q15_t) x2;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
+          acc1 = __SMLAD(input1, input2, acc1);
+
+          /* x[2] and x[3] are packed */
+          in1 = (q15_t) x2;
+          in2 = (q15_t) x3;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
+          acc2 = __SMLAD(input1, input2, acc2);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* x[3] and x[4] are packed */
+          in1 = (q15_t) x3;
+          in2 = (q15_t) x0;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
+          acc3 = __SMLAD(input1, input2, acc3);
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+          /* Read y[srcBLen - 4] sample */
+          c1 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* x[2] and x[3] are packed */
+          in1 = (q15_t) x2;
+          in2 = (q15_t) x3;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+          in1 = (q15_t) c0;
+          in2 = (q15_t) c1;
+
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
+          acc0 = __SMLAD(input1, input2, acc0);
+
+          /* x[3] and x[4] are packed */
+          in1 = (q15_t) x3;
+          in2 = (q15_t) x0;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
+          acc1 = __SMLAD(input1, input2, acc1);
+
+          /* x[4] and x[5] are packed */
+          in1 = (q15_t) x0;
+          in2 = (q15_t) x1;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
+          acc2 = __SMLAD(input1, input2, acc2);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* x[5] and x[6] are packed */
+          in1 = (q15_t) x1;
+          in2 = (q15_t) x2;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
+          acc3 = __SMLAD(input1, input2, acc3);
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += ((q31_t) x0 * c0);
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += ((q31_t) x1 * c0);
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += ((q31_t) x2 * c0);
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += ((q31_t) x3 * c0);
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count * 4u;
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+
+          /* Reading two inputs of SrcA buffer and packing */
+          in1 = (q15_t) * px++;
+          in2 = (q15_t) * px++;
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Reading two inputs of SrcB buffer and packing */
+          in1 = (q15_t) * py--;
+          in2 = (q15_t) * py--;
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Perform the multiply-accumulates */
+          sum = __SMLAD(input1, input2, sum);
+
+          /* Reading two inputs of SrcA buffer and packing */
+          in1 = (q15_t) * px++;
+          in2 = (q15_t) * px++;
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Reading two inputs of SrcB buffer and packing */
+          in1 = (q15_t) * py--;
+          in2 = (q15_t) * py--;
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Perform the multiply-accumulates */
+          sum = __SMLAD(input1, input2, sum);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
+  q7_t *pIn2 = pSrcB;                            /* inputB pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
new file mode 100644
index 0000000..a33a834
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
@@ -0,0 +1,727 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_q15.c   
+*   
+* Description:	Convolution of Q15 sequences.     
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q15 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * This approach provides 33 guard bits and there is no risk of overflow.   
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
+ *   
+ * \par   
+ * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between   
+     * inputA samples and inputB samples */
+    k = count;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:   
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1u);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* Initialize inputB pointer of type q31 */
+  pb = (q31_t *) (py - 1u);
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *(q31_t *) (px++);
+      /* read x[1], x[2] samples */
+      x1 = *(q31_t *) (px++);
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *(pb--);
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLALDX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLALDX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *(q31_t *) (px++);
+
+        /* Read x[3], x[4] */
+        x3 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLALDX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLALDX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *(pb--);
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLALDX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLALDX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = *(q31_t *) (px++);
+
+        /* Read x[5], x[6] */
+        x1 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLALDX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLALDX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+      py = (q15_t *) pb;
+      py = py + 1;
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = *(pb);
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = *pb--;
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        /* Read y[srcBLen - 7] */
+        c0 = (*pb);
+
+        //c0 = (c0 & 0x0000FFFF)<<16; 
+        c0 = (c0) << 16;
+
+#else
+
+        /* Read y[srcBLen - 7] */
+        c0 = (q15_t) (*pb >> 16);
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+      pb = (q31_t *) (py - 1);
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  blockSize3 = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  pIn2 = pSrc2 - 1u;
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2u;
+
+  while((j > 0u) && (blockSize3 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,   
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1u;
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* input pointer */
+  q15_t *pIn2 = pSrcB;                           /* coefficient pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += (q31_t) pIn1[j] * (pIn2[i - j]);
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
new file mode 100644
index 0000000..22a2a95
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
@@ -0,0 +1,583 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_q31.c   
+*   
+* Description:	Convolution of Q31 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q31 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer */
+  q31_t *pIn2;                                   /* inputB pointer */
+  q31_t *pOut = pDst;                            /* output pointer */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q63_t sum;                                     /* Accumulator */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (q31_t *) pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = (q31_t *) pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[1] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[2] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[3] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q31_t) (sum >> 31);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 += ((q63_t) x2 * c0);
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 += ((q63_t) x3 * c0);
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 += ((q63_t) x1 * c0);
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 += ((q63_t) x2 * c0);
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 += ((q63_t) x3 * c0);
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 += ((q63_t) x0 * c0);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 += ((q63_t) x2 * c0);
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 += ((q63_t) x3 * c0);
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 += ((q63_t) x0 * c0);
+        /* acc3 +=  x[5] * y[srcBLen - 2] */
+        acc3 += ((q63_t) x1 * c0);
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 += ((q63_t) x3 * c0);
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 += ((q63_t) x0 * c0);
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 += ((q63_t) x1 * c0);
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 += ((q63_t) x2 * c0);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += ((q63_t) x2 * c0);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += ((q63_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = (q31_t) (acc0 >> 31);
+      *pOut++ = (q31_t) (acc1 >> 31);
+      *pOut++ = (q31_t) (acc2 >> 31);
+      *pOut++ = (q31_t) (acc3 >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q31_t) (sum >> 31);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* input pointer */
+  q31_t *pIn2 = pSrcB;                           /* coefficient pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q31_t) (sum >> 31u);
+  }
+
+#endif /*     #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
new file mode 100644
index 0000000..6f844dd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
@@ -0,0 +1,680 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_q7.c   
+*   
+* Description:	Convolution of Q7 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q7 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.   
+ */
+
+void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer */
+  q7_t *pIn2;                                    /* inputB pointer */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t *px;                                      /* Intermediate inputA pointer */
+  q7_t *py;                                      /* Intermediate inputB pointer */
+  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
+  q7_t x0, x1, x2, x3, c0, c1;                   /* Temporary variables to hold state and coefficient values */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t input1, input2;                          /* Temporary input variables */
+  q15_t in1, in2;                                /* Temporary input variables */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = (srcALen - srcBLen) + 1u;
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] , x[1] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* y[srcBLen - 1] , y[srcBLen - 2] */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* x[0] * y[srcBLen - 1] */
+      /* x[1] * y[srcBLen - 2] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[2] , x[3] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* y[srcBLen - 3] , y[srcBLen - 4] */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* x[2] * y[srcBLen - 3] */
+      /* x[3] * y[srcBLen - 4] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+        /* Read y[srcBLen - 2] sample */
+        c1 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* x[0] and x[1] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[1] and x[2] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+        /* Read y[srcBLen - 4] sample */
+        c1 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[4] and x[5] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* x[5] and x[6] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += ((q15_t) x0 * c0);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += ((q15_t) x1 * c0);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += ((q15_t) x2 * c0);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += ((q15_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q15_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q15_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* input pointer */
+  q7_t *pIn2 = pSrcB;                            /* coefficient pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += (q15_t) pIn1[j] * (pIn2[i - j]);
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
new file mode 100644
index 0000000..bfbe0d3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
@@ -0,0 +1,718 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_f32.c   
+*   
+* Description:	 Correlation of floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup Corr Correlation   
+ *   
+ * Correlation is a mathematical operation that is similar to convolution.   
+ * As with convolution, correlation uses two signals to produce a third signal.   
+ * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.   
+ * Correlation is commonly used to measure the similarity between two signals.   
+ * It has applications in pattern recognition, cryptanalysis, and searching.   
+ * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.   
+ * Fast versions of the Q15 and Q31 functions are also provided.   
+ *   
+ * \par Algorithm   
+ * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.   
+ * The convolution of the two signals is denoted by   
+ * 
   
+ *                   c[n] = a[n] * b[n]   
+ * 
   
+ * In correlation, one of the signals is flipped in time   
+ * 
   
+ *                   c[n] = a[n] * b[-n]   
+ * 
   
+ *   
+ * \par   
+ * and this is mathematically defined as   
+ * \image html CorrelateEquation.gif   
+ * \par   
+ * The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen.   
+ * The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2).   
+ * The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.   
+ *   
+ * Note  
+ * \par 
+ * The pDst should be initialized to all zeros before being used. 
+ * 
+ * Fixed-Point Behavior   
+ * \par   
+ * Correlation requires summing up a large number of intermediate products.   
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.   
+ * Refer to the function specific documentation below for further details of the particular algorithm used.   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+/**   
+ * @brief Correlation of floating-point sequences.   
+ * @param[in]  *pSrcA points to the first input sequence.   
+ * @param[in]  srcALen length of the first input sequence.   
+ * @param[in]  *pSrcB points to the second input sequence.   
+ * @param[in]  srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ */
+
+void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1;                               /* inputA pointer */
+  float32_t *pIn2;                               /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1;                              /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulators */
+  float32_t x0, x1, x2, x3, c0;                  /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counters */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding has to be done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+    //while(j > 0u)  
+    //{  
+    //  /* Zero is stored in the destination buffer */  
+    //  *pOut++ = 0.0f;  
+
+    //  /* Decrement the loop counter */  
+    //  j--;  
+    //}  
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum += *px++ * *py++;
+      /* x[1] * y[srcBLen - 3] */
+      sum += *px++ * *py++;
+      /* x[2] * y[srcBLen - 2] */
+      sum += *px++ * *py++;
+      /* x[3] * y[srcBLen - 1] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* x[0] * y[srcBLen - 1] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[1] * y[0] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[2] * y[0] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[3] * y[0] */
+        acc3 += x3 * c0;
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 += x1 * c0;
+        /* acc1 +=  x[2] * y[1] */
+        acc1 += x2 * c0;
+        /* acc2 +=  x[3] * y[1] */
+        acc2 += x3 * c0;
+        /* acc3 +=  x[4] * y[1] */
+        acc3 += x0 * c0;
+
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 += x2 * c0;
+        /* acc1 +=  x[3] * y[2] */
+        acc1 += x3 * c0;
+        /* acc2 +=  x[4] * y[2] */
+        acc2 += x0 * c0;
+        /* acc3 +=  x[5] * y[2] */
+        acc3 += x1 * c0;
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 += x3 * c0;
+        /* acc1 +=  x[4] * y[3] */
+        acc1 += x0 * c0;
+        /* acc2 +=  x[5] * y[3] */
+        acc2 += x1 * c0;
+        /* acc3 +=  x[6] * y[3] */
+        acc3 += x2 * c0;
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += x3 * c0;
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = acc0;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = acc1;
+      pOut += inc;
+
+      *pOut = acc2;
+      pOut += inc;
+
+      *pOut = acc3;
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB + (srcBLen - 1u);      /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0.0f;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += pIn1[j] * pIn2[-((int32_t) i - j)];
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = sum;
+    else
+      *pDst++ = sum;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
new file mode 100644
index 0000000..f93d85a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
@@ -0,0 +1,622 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_fast_q15.c   
+*   
+* Description:	Fast Q15 Correlation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a   
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.   
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
+ */
+
+void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = __SMLAD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* Initialize inputB pointer of type q31 */
+  pb = (q31_t *) (py);
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *(q31_t *) (px++);
+      /* read x[1], x[2] samples */
+      x1 = *(q31_t *) (px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:   
+         * y[0] and y[1] */
+        c0 = *(pb++);
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLAD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *(q31_t *) (px++);
+
+        /* Read x[3], x[4] */
+        x3 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLAD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLAD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+        c0 = *(pb++);
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLAD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLAD(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = *(q31_t *) (px++);
+
+        /* Read x[5], x[6] */
+        x1 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLAD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLAD(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+      py = (q15_t *) (pb);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *(pb);
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *pb++;
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+        c0 = (*pb);
+        c0 = c0 & 0xFFFF0000;
+
+#else
+        c0 = (q15_t) (*pb);
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (acc0 >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (acc1 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc2 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc3 >> 15);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+      pb = (q31_t *) (py);
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
new file mode 100644
index 0000000..62d35dd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
@@ -0,0 +1,599 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_fast_q31.c   
+*   
+* Description:	Fast Q31 Correlation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ *   
+ * \par   
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signals must be scaled down.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a   
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.   
+ *   
+ * \par   
+ * See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.   
+ */
+
+void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[1] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[2] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[3] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum << 1;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[1] * y[0] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[2] * y[0] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[3] * y[0] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc1 +=  x[2] * y[1] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc2 +=  x[3] * y[1] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc3 +=  x[4] * y[1] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc1 +=  x[3] * y[2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc2 +=  x[4] * y[2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc3 +=  x[5] * y[2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc1 +=  x[4] * y[3] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc2 +=  x[5] * y[3] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc3 +=  x[6] * y[3] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (acc0 << 1);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q31_t) (acc1 << 1);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc2 << 1);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc3 << 1);
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum << 1;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum << 1;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1u;
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum << 1;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
new file mode 100644
index 0000000..424cc31
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
@@ -0,0 +1,714 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_q15.c   
+*   
+* Description:	Correlation of Q15 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q15 sequences. 
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * This approach provides 33 guard bits and there is no risk of overflow.   
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
+ *   
+ * \par   
+ * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = __SMLALD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* Initialize inputB pointer of type q31 */
+  pb = (q31_t *) (py);
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *(q31_t *) (px++);
+      /* read x[1], x[2] samples */
+      x1 = *(q31_t *) (px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:   
+         * y[0] and y[1] */
+        c0 = *(pb++);
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLALD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLALD(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *(q31_t *) (px++);
+
+        /* Read x[3], x[4] */
+        x3 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLALD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLALD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+        c0 = *(pb++);
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLALD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLALD(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = *(q31_t *) (px++);
+
+        /* Read x[5], x[6] */
+        x1 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLALD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLALD(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+      py = (q15_t *) (pb);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[7] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *(pb);
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALD(x3, c0, acc2);
+        acc3 = __SMLALD(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *pb++;
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALD(x3, c0, acc2);
+        acc3 = __SMLALD(x2, c0, acc3);
+
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = (*pb);
+        c0 = c0 & 0xFFFF0000;
+
+#else
+
+        c0 = (q15_t) (*pb);
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[10] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(acc0 >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc1 >> 15, 16));
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc2 >> 15, 16));
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc3 >> 15, 16));
+      pOut += inc;
+
+      /* Increment the count by 4 as 4 output values are computed */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+      pb = (q31_t *) (py);
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment count by 1, as one output value is computed */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* inputA pointer               */
+  q15_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
+  q63_t sum;                                     /* Accumulators                  */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q15_t) __SSAT((sum >> 15u), 16u);
+    else
+      *pDst++ = (q15_t) __SSAT((sum >> 15u), 16u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
new file mode 100644
index 0000000..df1a457
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
@@ -0,0 +1,683 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_q31.c   
+*   
+* Description:	Correlation of Q31 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q31 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a   
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.   
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1;                                  /* Intermediate pointers        */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[1] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[2] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[3] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q31_t) (sum >> 31);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[1] * y[0] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[2] * y[0] */
+        acc2 += ((q63_t) x2 * c0);
+        /* acc3 +=  x[3] * y[0] */
+        acc3 += ((q63_t) x3 * c0);
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 += ((q63_t) x1 * c0);
+        /* acc1 +=  x[2] * y[1] */
+        acc1 += ((q63_t) x2 * c0);
+        /* acc2 +=  x[3] * y[1] */
+        acc2 += ((q63_t) x3 * c0);
+        /* acc3 +=  x[4] * y[1] */
+        acc3 += ((q63_t) x0 * c0);
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 += ((q63_t) x2 * c0);
+        /* acc1 +=  x[3] * y[2] */
+        acc1 += ((q63_t) x3 * c0);
+        /* acc2 +=  x[4] * y[2] */
+        acc2 += ((q63_t) x0 * c0);
+        /* acc3 +=  x[5] * y[2] */
+        acc3 += ((q63_t) x1 * c0);
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 += ((q63_t) x3 * c0);
+        /* acc1 +=  x[4] * y[3] */
+        acc1 += ((q63_t) x0 * c0);
+        /* acc2 +=  x[5] * y[3] */
+        acc2 += ((q63_t) x1 * c0);
+        /* acc3 +=  x[6] * y[3] */
+        acc3 += ((q63_t) x2 * c0);
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += ((q63_t) x2 * c0);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += ((q63_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (acc0 >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q31_t) (acc1 >> 31);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc2 >> 31);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc3 >> 31);
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (sum >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (sum >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q31_t) (sum >> 31);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* inputA pointer               */
+  q31_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
+  q63_t sum;                                     /* Accumulators                  */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q31_t) (sum >> 31u);
+    else
+      *pDst++ = (q31_t) (sum >> 31u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
new file mode 100644
index 0000000..2496e2c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
@@ -0,0 +1,780 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_q7.c   
+*   
+* Description:	Correlation of Q7 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q7 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.   
+ */
+
+void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer               */
+  q7_t *pIn2;                                    /* inputB pointer               */
+  q7_t *pOut = pDst;                             /* output pointer               */
+  q7_t *px;                                      /* Intermediate inputA pointer  */
+  q7_t *py;                                      /* Intermediate inputB pointer  */
+  q7_t *pSrc1;                                   /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t input1, input2;                          /* temporary variables */
+  q15_t in1, in2;                                /* temporary variables */
+  q7_t x0, x1, x2, x3, c0, c1;                   /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] , x[1] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[srcBLen - 4] , y[srcBLen - 3] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* x[0] * y[srcBLen - 4] */
+      /* x[1] * y[srcBLen - 3] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[2] , x[3] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[srcBLen - 2] , y[srcBLen - 1] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* x[2] * y[srcBLen - 2] */
+      /* x[3] * y[srcBLen - 1] */
+      sum = __SMLAD(input1, input2, sum);
+
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q31_t) ((q15_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *px++;
+      x1 = *px++;
+      x2 = *px++;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *py++;
+        /* Read y[1] sample */
+        c1 = *py++;
+
+        /* Read x[3] sample */
+        x3 = *px++;
+
+        /* x[0] and x[1] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[0] and y[1] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc0 += x[0] * y[0] + x[1] * y[1]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[1] and x[2] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc1 += x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc2 += x[2] * y[0] + x[3] * y[1]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc3 += x[3] * y[0] + x[4] * y[1]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+        /* Read y[2] sample */
+        c0 = *py++;
+        /* Read y[3] sample */
+        c1 = *py++;
+
+        /* Read x[5] sample */
+        x1 = *px++;
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[2] and y[3] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc0 += x[2] * y[2] + x[3] * y[3]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc1 += x[3] * y[2] + x[4] * y[3]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[4] and x[5] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc2 += x[4] * y[2] + x[5] * y[3]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[6] sample */
+        x2 = *px++;
+
+        /* x[5] and x[6] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc3 += x[5] * y[2] + x[6] * y[3]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *py++;
+
+        /* Read x[7] sample */
+        x3 = *px++;
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += ((q15_t) x0 * c0);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += ((q15_t) x1 * c0);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += ((q15_t) x2 * c0);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += ((q15_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py++;
+        in2 = (q15_t) * py++;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py++;
+        in2 = (q15_t) * py++;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q15_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q15_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2]  */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[0] , y[1] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[2] , y[3] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
+  q7_t *pIn2 = pSrcB + (srcBLen - 1u);           /* inputB pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q7_t) __SSAT((sum >> 7u), 8u);
+    else
+      *pDst++ = (q7_t) __SSAT((sum >> 7u), 8u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
new file mode 100644
index 0000000..0ee7d16
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
@@ -0,0 +1,370 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_f32.c   
+*   
+* Description:	FIR decimation for floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator   
+ *   
+ * These functions combine an FIR filter together with a decimator.   
+ * They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.   
+ * Conceptually, the functions are equivalent to the block diagram below:   
+ * \image html FIRDecimator.gif "Components included in the FIR Decimator functions"   
+ * When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized   
+ * cutoff frequency of 1/M in order to prevent aliasing distortion.   
+ * The user of the function is responsible for providing the filter coefficients.   
+ *   
+ * The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.   
+ * Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the   
+ * samples output by the decimator are computed.   
+ * The functions operate on blocks of input and output data.   
+ * pSrc points to an array of blockSize input values and   
+ * pDst points to an array of blockSize/M output values.   
+ * In order to have an integer number of output samples blockSize   
+ * must always be a multiple of the decimation factor M.   
+ *   
+ * The library provides separate functions for Q15, Q31 and floating-point data types.   
+ *   
+ * \par Algorithm:   
+ * The FIR portion of the algorithm uses the standard form filter:   
+ * 
   
+ *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ * 
   
+ * where, b[n] are the filter coefficients.   
+ * \par  
+ * The pCoeffs points to a coefficient array of size numTaps.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to a state array of size numTaps + blockSize - 1.   
+ * Samples in the state buffer are stored in the order:   
+ * \par   
+ * 
   
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
   
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * - Checks to make sure that the size of the input is a multiple of the decimation factor.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * The code below statically initializes each of the 3 different data type filter instance structures   
+ * 
   
+ *arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};   
+ *arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};   
+ *arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};   
+ * 
   
+ * where M is the decimation factor; numTaps is the number of filter coefficients in the filter;   
+ * pCoeffs is the address of the coefficient buffer;   
+ * pState is the address of the state buffer.   
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the FIR decimate filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+  /**   
+   * @brief Processing function for the floating-point FIR decimator.   
+   * @param[in] *S        points to an instance of the floating-point FIR decimator structure.   
+   * @param[in] *pSrc     points to the block of input data.   
+   * @param[out] *pDst    points to the block of output data.   
+   * @param[in] blockSize number of input samples to process per call.   
+   * @return none.   
+   */
+
+void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t sum0;                                /* Accumulator */
+  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = sum0;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor          
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = sum0;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  i = (numTaps - 1u);
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
new file mode 100644
index 0000000..ae1ddf8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
@@ -0,0 +1,199 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_fast_q15.c   
+*   
+* Description:	Fast Q15 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).   
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.   
+ * Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_fir_decimate_init_q15() to initialize the filter structure.   
+ */
+
+void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t sum0;                                    /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output , smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) ((sum0 >> 15));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
new file mode 100644
index 0000000..86833d8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
@@ -0,0 +1,220 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_fast_q31.c   
+*   
+* Description:	Fast Q31 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are added to a 2.30 accumulator.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).   
+ *   
+ * \par   
+ * Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.   
+ * Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_fir_decimate_init_q31() to initialize the filter structure.   
+ */
+
+void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t *px;                                     /* Temporary pointers for state buffer */
+  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
+  q63_t sum0;                                    /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 << 1);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
new file mode 100644
index 0000000..be970eb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
@@ -0,0 +1,109 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_decimate_init_f32.c   
+*   
+* Description:  Floating-point FIR Decimator initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point FIR decimator.   
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.   
+ * @param[in] numTaps  number of coefficients in the filter.   
+ * @param[in] M  decimation factor.   
+ * @param[in] *pCoeffs points to the filter coefficients.   
+ * @param[in] *pState points to the state buffer.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * blockSize is not a multiple of M.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32().   
+ * M is the decimation factor.   
+ */
+
+arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear state buffer and size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation Factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
new file mode 100644
index 0000000..c9f1f3c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_decimate_init_q15.c   
+*   
+* Description:  Initialization function for the Q15 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the Q15 FIR decimator.   
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.   
+ * @param[in] numTaps  number of coefficients in the filter.   
+ * @param[in] M  decimation factor.   
+ * @param[in] *pCoeffs points to the filter coefficients.   
+ * @param[in] *pState points to the state buffer.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * blockSize is not a multiple of M.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples   
+ * to the call arm_fir_decimate_q15().   
+ * M is the decimation factor.   
+ */
+
+arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size of buffer is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
new file mode 100644
index 0000000..7fdb693
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_decimate_init_q31.c   
+*   
+* Description:  Initialization function for Q31 FIR Decimation filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the Q31 FIR decimator.   
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.   
+ * @param[in] numTaps  number of coefficients in the filter.   
+ * @param[in] M  decimation factor.   
+ * @param[in] *pCoeffs points to the filter coefficients.   
+ * @param[in] *pState points to the state buffer.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * blockSize is not a multiple of M.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31().   
+ * M is the decimation factor.   
+ */
+
+arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
new file mode 100644
index 0000000..be26459
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
@@ -0,0 +1,285 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_q15.c   
+*   
+* Description:	Q15 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 FIR decimator.   
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the location where the output result is written.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q63_t sum0;                                    /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q31_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor          
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /*Store filter output , smlad will return the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = numTaps - 1u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
new file mode 100644
index 0000000..96f7ce1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_q31.c   
+*   
+* Description:	Q31 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 FIR decimator.   
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).   
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t *px;                                     /* Temporary pointers for state buffer */
+  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
+  q63_t sum0;                                    /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 >> 31);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor          
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 >> 31);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = numTaps - 1u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
new file mode 100644
index 0000000..1a16654
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
@@ -0,0 +1,436 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_f32.c   
+*   
+* Description:	Floating-point FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup FIR Finite Impulse Response (FIR) Filters   
+ *   
+ * This set of functions implements Finite Impulse Response (FIR) filters   
+ * for Q7, Q15, Q31, and floating-point data types.   
+ * Fast versions of Q15 and Q31 are also provided on Cortex-M4 and Cortex-M3.   
+ * The functions operate on blocks of input and output data and each call to the function processes   
+ * blockSize samples through the filter.  pSrc and   
+ * pDst points to input and output arrays containing blockSize values.   
+ *   
+ * \par Algorithm:   
+ * The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations.   
+ * Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n].   
+ * 
   
+ *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ * 
   
+ * \par   
+ * \image html FIR.gif "Finite Impulse Response filter"   
+ * \par   
+ * pCoeffs points to a coefficient array of size numTaps.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to a state array of size numTaps + blockSize - 1.   
+ * Samples in the state buffer are stored in the following order.   
+ * \par   
+ * 
   
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
   
+ * \par   
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1.   
+ * The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters,   
+ * to be avoided and yields a significant speed improvement.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 4 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * The code below statically initializes each of the 4 different data type filter instance structures   
+ * 
   
+ *arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};   
+ *arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};   
+ *arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};   
+ *arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};   
+ * 
   
+ *   
+ * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the FIR filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ *   
+ * @param[in]  *S points to an instance of the floating-point FIR filter structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return     none.   
+ *   
+ */
+
+void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t acc0, acc1, acc2, acc3;              /* Accumulators */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0.0f;
+    acc1 = 0.0f;
+    acc2 = 0.0f;
+    acc3 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the first three samples from the state buffer:  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *px++;
+    x1 = *px++;
+    x2 = *px++;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2u;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps-1] * x[n-numTaps] */
+      acc0 += x0 * c0;
+
+      /* acc1 +=  b[numTaps-1] * x[n-numTaps-1] */
+      acc1 += x1 * c0;
+
+      /* acc2 +=  b[numTaps-1] * x[n-numTaps-2] */
+      acc2 += x2 * c0;
+
+      /* acc3 +=  b[numTaps-1] * x[n-numTaps-3] */
+      acc3 += x3 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x1 * c0;
+      acc1 += x2 * c0;
+      acc2 += x3 * c0;
+      acc3 += x0 * c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x2 * c0;
+      acc1 += x3 * c0;
+      acc2 += x0 * c0;
+      acc3 += x1 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x3 * c0;
+      acc1 += x0 * c0;
+      acc2 += x1 * c0;
+      acc3 += x2 * c0;
+
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    *pDst++ = acc0;
+    *pDst++ = acc1;
+    *pDst++ = acc2;
+    *pDst++ = acc3;
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += *px++ * *pb++;
+      i--;
+
+    } while(i > 0u);
+
+    /* The result is store in the destination buffer. */
+    *pDst++ = acc0;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t acc;
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += *px++ * *pb++;
+      i--;
+
+    } while(i > 0u);
+
+    /* The result is store in the destination buffer. */
+    *pDst++ = acc;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = numTaps - 1u;
+
+  /* Copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
new file mode 100644
index 0000000..cbd0827
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
@@ -0,0 +1,279 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_fast_q15.c   
+*   
+* Description:  Q15 Fast FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.9  2010/08/16    
+*    Initial version   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.   
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_fir_init_q15() to initialize the filter structure.   
+ */
+
+void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px1;                                    /* Temporary q15 pointer for state buffer */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q31_t *px2;                                    /* Temporary q31 pointer for SIMD state buffer accesses */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold SIMD state and coefficient values */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer.   
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer of type q15 */
+    px1 = pState;
+
+    /* Initialize coeff pointer of type q31 */
+    pb = (q31_t *) (pCoeffs);
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = *(q31_t *) (px1++);
+
+    /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
+    x1 = *(q31_t *) (px1++);
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    tapCnt = numTaps >> 2;
+    do
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *(pb++);
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLAD(x0, c0, acc0);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLAD(x1, c0, acc1);
+
+      /* Read state x[n-N-2], x[n-N-3] */
+      x2 = *(q31_t *) (px1++);
+
+      /* Read state x[n-N-3], x[n-N-4] */
+      x3 = *(q31_t *) (px1++);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLAD(x2, c0, acc2);
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLAD(x3, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *(pb++);
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLAD(x2, c0, acc0);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLAD(x3, c0, acc1);
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = *(q31_t *) (px1++);
+
+      /* Read state x[n-N-5], x[n-N-6] */
+      x1 = *(q31_t *) (px1++);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLAD(x0, c0, acc2);
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLAD(x1, c0, acc3);
+      tapCnt--;
+
+    }
+    while(tapCnt > 0u);
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.   
+     ** This is always 2 taps since the filter length is always even. */
+    if((numTaps & 0x3u) != 0u)
+    {
+      /* Read 2 coefficients */
+      c0 = *(pb++);
+      /* Fetch 4 state variables */
+      x2 = *(q31_t *) (px1++);
+      x3 = *(q31_t *) (px1++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLAD(x0, c0, acc0);
+      acc1 = __SMLAD(x1, c0, acc1);
+      acc2 = __SMLAD(x2, c0, acc2);
+      acc3 = __SMLAD(x3, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.   
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16u);
+    *__SIMD32(pDst)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16u);
+
+#else
+
+    *__SIMD32(pDst)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16u);
+    *__SIMD32(pDst)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16u);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+  while(blkCnt > 0u)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Use SIMD to hold states and coefficients */
+    px2 = (q31_t *) pState;
+    pb = (q31_t *) (pCoeffs);
+    tapCnt = numTaps >> 1;
+
+    do
+    {
+      acc0 = __SMLAD(*px2++, *(pb++), acc0);
+      tapCnt--;
+    }
+    while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) ((acc0 >> 15));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy remaining data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
new file mode 100644
index 0000000..6cbfa7f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_fast_q31.c   
+*   
+* Description:	Processing function for the Q31 Fast FIR filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.9  2010/08/27    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in] *S points to an instance of the Q31 structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block output data.   
+ * @param[in] blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are added to a 2.30 accumulator.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.  Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_fir_init_q31() to initialize the filter structure.   
+ */
+
+void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, x1, x2, x3;                          /* Temporary variables to hold state */
+  q31_t c0;                                      /* Temporary variable to hold coefficient value */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:   
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      acc0 = (q31_t) ((((q63_t) x0 * c0) + (acc0 << 32)) >> 32);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      acc1 = (q31_t) ((((q63_t) x1 * c0) + (acc1 << 32)) >> 32);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      acc2 = (q31_t) ((((q63_t) x2 * c0) + (acc2 << 32)) >> 32);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      acc3 = (q31_t) ((((q63_t) x3 * c0) + (acc3 << 32)) >> 32);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) x1 * c0) + (acc0 << 32)) >> 32);
+      acc1 = (q31_t) ((((q63_t) x2 * c0) + (acc1 << 32)) >> 32);
+      acc2 = (q31_t) ((((q63_t) x3 * c0) + (acc2 << 32)) >> 32);
+      acc3 = (q31_t) ((((q63_t) x0 * c0) + (acc3 << 32)) >> 32);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) x2 * c0) + (acc0 << 32)) >> 32);
+      acc1 = (q31_t) ((((q63_t) x3 * c0) + (acc1 << 32)) >> 32);
+      acc2 = (q31_t) ((((q63_t) x0 * c0) + (acc2 << 32)) >> 32);
+      acc3 = (q31_t) ((((q63_t) x1 * c0) + (acc3 << 32)) >> 32);
+
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) x3 * c0) + (acc0 << 32)) >> 32);
+      acc1 = (q31_t) ((((q63_t) x0 * c0) + (acc1 << 32)) >> 32);
+      acc2 = (q31_t) ((((q63_t) x1 * c0) + (acc2 << 32)) >> 32);
+      acc3 = (q31_t) ((((q63_t) x2 * c0) + (acc3 << 32)) >> 32);
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4u);
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) x0 * c0) + (acc0 << 32)) >> 32);
+      acc1 = (q31_t) ((((q63_t) x1 * c0) + (acc1 << 32)) >> 32);
+      acc2 = (q31_t) ((((q63_t) x2 * c0) + (acc2 << 32)) >> 32);
+      acc3 = (q31_t) ((((q63_t) x3 * c0) + (acc3 << 32)) >> 32);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.31   
+     ** Then store the 4 outputs in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+    *pDst++ = (q31_t) (acc1 << 1);
+    *pDst++ = (q31_t) (acc2 << 1);
+    *pDst++ = (q31_t) (acc3 << 1);
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 = (q31_t) ((((q63_t) * (px++) * (*(pb++))) + (acc0 << 32)) >> 32);
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.31   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
new file mode 100644
index 0000000..100d4ac
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_init_f32.c   
+*   
+* Description:  Floating-point FIR filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.   
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.   
+ * @param[in]     *pCoeffs points to the filter coefficients buffer.   
+ * @param[in]     *pState points to the state buffer.   
+ * @param[in] 	  blockSize number of samples that are processed per call.   
+ * @return 		  none.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32().   
+ */
+
+void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and the size of state buffer is (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
new file mode 100644
index 0000000..9d01aa1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_init_q15.c   
+*   
+* Description:  Q15 FIR filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in,out]  *S points to an instance of the Q15 FIR filter structure.   
+ * @param[in] 	   numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.   
+ * @param[in]      *pCoeffs points to the filter coefficients buffer.   
+ * @param[in]      *pState points to the state buffer.   
+ * @param[in]      blockSize is number of samples processed per call.   
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if   
+ * numTaps is not greater than or equal to 4 and even.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * Note that numTaps must be even and greater than or equal to 4.   
+ * To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero.   
+ * For example, to implement a filter with numTaps=3 and coefficients   
+ * 
   
+ *     {0.3, -0.8, 0.3}   
+ * 
   
+ * set numTaps=4 and use the coefficients:   
+ * 
   
+ *     {0.3, -0.8, 0.3, 0}.   
+ * 
   
+ * Similarly, to implement a two point filter   
+ * 
   
+ *     {0.3, -0.3}   
+ * 
   
+ * set numTaps=4 and use the coefficients:   
+ * 
   
+ *     {0.3, -0.3, 0, 0}.   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1, where blockSize is the number of input samples processed by each call to arm_fir_q15().   
+ */
+
+arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* The Number of filter coefficients in the filter must be even and at least 4 */
+  if((numTaps < 4u) || (numTaps & 0x1u))
+  {
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  status = ARM_MATH_SUCCESS;
+
+  return (status);
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
new file mode 100644
index 0000000..1976228
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
@@ -0,0 +1,91 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_init_q31.c   
+*   
+* Description:	Q31 FIR filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S points to an instance of the Q31 FIR filter structure.   
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.   
+ * @param[in] 	  *pCoeffs points to the filter coefficients buffer.   
+ * @param[in] 	  *pState points to the state buffer.   
+ * @param[in] 	  blockSize number of samples that are processed per call.   
+ * @return        none.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31().   
+ */
+
+void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and state array size is (blockSize + numTaps - 1) */
+  memset(pState, 0, (blockSize + ((uint32_t) numTaps - 1u)) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
new file mode 100644
index 0000000..33b80a6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
@@ -0,0 +1,89 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_init_q7.c   
+*   
+* Description:  Q7 FIR filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+/**   
+ * @param[in,out] *S points to an instance of the Q7 FIR filter structure.   
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.   
+ * @param[in] 	  *pCoeffs points to the filter coefficients buffer.   
+ * @param[in]     *pState points to the state buffer.   
+ * @param[in]     blockSize number of samples that are processed per call.   
+ * @return     	  none   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7().   
+ */
+
+void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize)
+{
+
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q7_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
new file mode 100644
index 0000000..abee5bf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
@@ -0,0 +1,399 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_interpolate_f32.c   
+*   
+* Description:	FIR interpolation for floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator   
+ *   
+ * These functions combine an upsampler (zero stuffer) and an FIR filter.   
+ * They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.   
+ * Conceptually, the functions are equivalent to the block diagram below:   
+ * \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions"   
+ * After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized   
+ * cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum.   
+ * The user of the function is responsible for providing the filter coefficients.   
+ *   
+ * The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.   
+ * The upsampler inserts L-1 zeros between each sample.   
+ * Instead of multiplying by these zero values, the FIR filter is designed to skip them.   
+ * This leads to an efficient implementation without any wasted effort.   
+ * The functions operate on blocks of input and output data.   
+ * pSrc points to an array of blockSize input values and   
+ * pDst points to an array of blockSize*L output values.   
+ *   
+ * The library provides separate functions for Q15, Q31, and floating-point data types.   
+ *   
+ * \par Algorithm:   
+ * The functions use a polyphase filter structure:   
+ * 
   
+ *    y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]   
+ *    y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]   
+ *    ...   
+ *    y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]   
+ * 
   
+ * This approach is more efficient than straightforward upsample-then-filter algorithms.   
+ * With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter.   
+ * \par   
+ * pCoeffs points to a coefficient array of size numTaps.   
+ * numTaps must be a multiple of the interpolation factor L and this is checked by the   
+ * initialization functions.   
+ * Internally, the function divides the FIR filter's impulse response into shorter filters of length   
+ * phaseLength=numTaps/L.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to a state array of size blockSize + phaseLength - 1.   
+ * Samples in the state buffer are stored in the order:   
+ * \par   
+ * 
   
+ *    {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
   
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * - Checks to make sure that the length of the filter is a multiple of the interpolation factor.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * The code below statically initializes each of the 3 different data type filter instance structures   
+ * 
   
+ * arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};   
+ * arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};   
+ * arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};   
+ * 
   
+ * where L is the interpolation factor; phaseLength=numTaps/L is the   
+ * length of each of the shorter FIR filters used internally,   
+ * pCoeffs is the address of the coefficient buffer;   
+ * pState is the address of the state buffer.   
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the floating-point FIR interpolator.   
+ * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.   
+ * @param[in] *pSrc     points to the block of input data.   
+ * @param[out] *pDst    points to the block of output data.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none.   
+ */
+
+void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t sum0;                                /* Accumulators */
+  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j;                         /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.   
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2u;
+      while(tapCnt > 0u)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.   
+         * So instead of multiplying zeros with coefficients,   
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4u;
+
+      while(tapCnt > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum0 += *(ptr1++) * (*ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = sum0;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1   
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  tapCnt = (phaseLen - 1u) % 0x04u;
+
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      /* Loop over the polyPhase length */
+      tapCnt = phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *ptr1++ * *ptr2;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = sum;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1          
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = phaseLen - 1u;
+
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
new file mode 100644
index 0000000..59802b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
@@ -0,0 +1,113 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_interpolate_init_f32.c   
+*   
+* Description:  Floating-point FIR interpolator initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point FIR interpolator.   
+ * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.   
+ * @param[in]     L         upsample factor.   
+ * @param[in]     numTaps   number of filter coefficients in the filter.   
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.   
+ * @param[in]     *pState   points to the state buffer.   
+ * @param[in]     blockSize number of input samples to process per call.   
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * the filter length numTaps is not a multiple of the interpolation factor L.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ * 
   
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length (numTaps/L)+blockSize-1 words   
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32().   
+ */
+
+arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of state array is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize +
+            ((uint32_t) S->phaseLength - 1u)) * sizeof(float32_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
new file mode 100644
index 0000000..0ab6e6b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
@@ -0,0 +1,112 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_interpolate_init_q15.c   
+*   
+* Description:  Q15 FIR interpolator initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the Q15 FIR interpolator.   
+ * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.   
+ * @param[in]     L         upsample factor.   
+ * @param[in]     numTaps   number of filter coefficients in the filter.   
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.   
+ * @param[in]     *pState   points to the state buffer.   
+ * @param[in]     blockSize number of input samples to process per call.   
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * the filter length numTaps is not a multiple of the interpolation factor L.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ * 
   
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length (numTaps/L)+blockSize-1 words   
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15().   
+ */
+
+arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
new file mode 100644
index 0000000..92906c1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
@@ -0,0 +1,113 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_interpolate_init_q31.c   
+*   
+* Description:  Q31 FIR interpolator initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Initialization function for the Q31 FIR interpolator.   
+ * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.   
+ * @param[in]     L         upsample factor.   
+ * @param[in]     numTaps   number of filter coefficients in the filter.   
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.   
+ * @param[in]     *pState   points to the state buffer.   
+ * @param[in]     blockSize number of input samples to process per call.   
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * the filter length numTaps is not a multiple of the interpolation factor L.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ * 
   
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length (numTaps/L)+blockSize-1 words   
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31().   
+ */
+
+arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q31_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
new file mode 100644
index 0000000..56dddcc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
@@ -0,0 +1,349 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fir_interpolate_q15.c   
+*   
+* Description:	Q15 FIR interpolation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 FIR interpolator.   
+ * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.   
+ * @param[in] *pSrc     points to the block of input data.   
+ * @param[out] *pDst    points to the block of output data.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ */
+
+void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer                                            */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */
+  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q63_t sum0;                                    /* Accumulators                                             */
+  q15_t x0, c0, c1;                              /* Temporary variables to hold state and coefficient values */
+  q31_t c, x;
+  uint32_t i, blkCnt, j, tapCnt;                 /* Loop counters                                            */
+  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.   
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = (uint32_t) phaseLen >> 2u;
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.   
+         * So instead of multiplying zeros with coefficients,   
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the coefficient */
+        c1 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Pack the coefficients */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+        c = __PKHBT(c0, c1, 16);
+
+#else
+
+        c = __PKHBT(c1, c0, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+        /* Read twp consecutive input samples */
+        x = *__SIMD32(ptr1)++;
+
+        /* Perform the multiply-accumulate */
+        sum0 = __SMLALD(x, c, sum0);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.   
+         * So insted of multiplying zeros with coefficients,   
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the coefficient */
+        c1 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Pack the coefficients */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+        c = __PKHBT(c0, c1, 16);
+
+#else
+
+        c = __PKHBT(c1, c0, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN            */
+
+        /* Read twp consecutive input samples */
+        x = *__SIMD32(ptr1)++;
+
+        /* Perform the multiply-accumulate */
+        sum0 = __SMLALD(x, c, sum0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = (uint32_t) phaseLen & 0x3u;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 = __SMLALD(x0, c0, sum0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1   
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = ((uint32_t) phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = ((uint32_t) phaseLen - 1u) % 0x04u;
+
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sum;                                     /* Accumulator */
+  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, tapCnt;                    /* Loop counters                                            */
+  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      /* Loop over the polyPhase length */
+      tapCnt = (uint32_t) phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *ptr2;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *ptr1++;
+
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) x0 * c0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Store the result after converting to 1.15 format in the destination buffer */
+      *pDst++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1          
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (uint32_t) phaseLen - 1u;
+
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
new file mode 100644
index 0000000..660b7dd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
@@ -0,0 +1,340 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fir_interpolate_q31.c   
+*   
+* Description:	Q31 FIR interpolation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 FIR interpolator.   
+ * @param[in] *S        points to an instance of the Q31 FIR interpolator structure.   
+ * @param[in] *pSrc     points to the block of input data.   
+ * @param[out] *pDst    points to the block of output data.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L).   
+ * since numTaps/L additions occur per output sample.   
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.   
+ */
+
+
+void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q63_t sum0;                                    /* Accumulators */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j;                         /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.   
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2;
+      while(tapCnt > 0u)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.   
+         * So instead of multiplying zeros with coefficients,   
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen & 0x3u;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q31_t) (sum0 >> 31);
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1   
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  tapCnt = (phaseLen - 1u) % 0x04u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sum;                                     /* Accumulator */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      tapCnt = phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *ptr1++;
+
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q31_t) (sum >> 31);
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1          
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = phaseLen - 1u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
new file mode 100644
index 0000000..4192992
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
@@ -0,0 +1,496 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_lattice_f32.c   
+*   
+* Description:	Processing function for the floating-point FIR Lattice filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters   
+ *   
+ * This set of functions implements Finite Impulse Response (FIR) lattice filters   
+ * for Q15, Q31 and floating-point data types.  Lattice filters are used in a    
+ * variety of adaptive filter applications.  The filter structure is feedforward and   
+ * the net impulse response is finite length.   
+ * The functions operate on blocks   
+ * of input and output data and each call to the function processes   
+ * blockSize samples through the filter.  pSrc and   
+ * pDst point to input and output arrays containing blockSize values.   
+ *   
+ * \par Algorithm:   
+ * \image html FIRLattice.gif "Finite Impulse Response Lattice filter"   
+ * The following difference equation is implemented:   
+ * 
   
+ *    f0[n] = g0[n] = x[n]   
+ *    fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M   
+ *    gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M   
+ *    y[n] = fM[n]   
+ * 
   
+ * \par   
+ * pCoeffs points to tha array of reflection coefficients of size numStages.   
+ * Reflection Coefficients are stored in the following order.   
+ * \par   
+ * 
   
+ *    {k1, k2, ..., kM}   
+ * 
   
+ * where M is number of stages   
+ * \par   
+ * pState points to a state array of size numStages.   
+ * The state variables (g values) hold previous inputs and are stored in the following order.   
+ * 
   
+ *    {g0[n], g1[n], g2[n] ...gM-1[n]}   
+ * 
   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:   
+ * 
   
+ *arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};   
+ *arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};   
+ *arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};   
+ * 
   
+ * \par   
+ * where numStages is the number of stages in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer.   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+
+  /**   
+   * @brief Processing function for the floating-point FIR lattice filter.   
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.   
+   * @param[in]  *pSrc     points to the block of input data.   
+   * @param[out] *pDst     points to the block of output data   
+   * @param[in]  blockSize number of samples to process.   
+   * @return none.   
+   */
+
+void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState;                             /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *px;                                 /* temporary state pointer */
+  float32_t *pk;                                 /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t fcurr1, fnext1, gcurr1, gnext1;      /* temporary variables for first sample in loop unrolling */
+  float32_t fcurr2, fnext2, gnext2;              /* temporary variables for second sample in loop unrolling */
+  float32_t fcurr3, fnext3, gnext3;              /* temporary variables for third sample in loop unrolling */
+  float32_t fcurr4, fnext4, gnext4;              /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  gcurr1 = 0.0f;
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+    fcurr2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurr1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = fcurr1 + ((*pk) * gcurr1);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (fcurr1 * (*pk)) + gcurr1;
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = fcurr2 + ((*pk) * fcurr1);
+    gnext2 = (fcurr2 * (*pk)) + fcurr1;
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurr3 = *pSrc++;
+    fcurr4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer   
+       which will be used for next four samples processing */
+    *px++ = fcurr4;
+
+    /* Process third sample for first tap */
+    fnext3 = fcurr3 + ((*pk) * fcurr2);
+    gnext3 = (fcurr3 * (*pk)) + fcurr2;
+
+    /* Process fourth sample for first tap */
+    fnext4 = fcurr4 + ((*pk) * fcurr3);
+    gnext4 = (fcurr4 * (*pk++)) + fcurr3;
+
+    /* Update of f values for next coefficient set processing */
+    fcurr1 = fnext1;
+    fcurr2 = fnext2;
+    fcurr3 = fnext3;
+    fcurr4 = fnext4;
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1u) >> 2u;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while(stageCnt > 0u)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      /* Process fourth sample for 2nd, 6th .. tap */
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g2(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurr1 = fnext1 + ((*pk) * gcurr1);
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurr2 = fnext2 + ((*pk) * gnext1);
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurr3 = fnext3 + ((*pk) * gnext2);
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurr4 = fnext4 + ((*pk) * gnext3);
+
+      /* Calculation of state values for next stage */
+      /* g3(n) = f2(n) * K3  +  g2(n-1) */
+      gnext4 = (fnext4 * (*pk)) + gnext3;
+      gnext3 = (fnext3 * (*pk)) + gnext2;
+      gnext2 = (fnext2 * (*pk)) + gnext1;
+      gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g3(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurr1 = fnext1 + ((*pk) * gcurr1);
+      /* Process second sample for 5th, 9th .. tap */
+      fcurr2 = fnext2 + ((*pk) * gnext1);
+      /* Process third sample for 5th, 9th .. tap */
+      fcurr3 = fnext3 + ((*pk) * gnext2);
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurr4 = fnext4 + ((*pk) * gnext3);
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (fnext4 * (*pk)) + gnext3;
+      gnext3 = (fnext3 * (*pk)) + gnext2;
+      gnext2 = (fnext2 * (*pk)) + gnext1;
+      gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1u) % 0x4u;
+
+    while(stageCnt > 0u)
+    {
+      gcurr1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* Update of f values for next coefficient set processing */
+      fcurr1 = fnext1;
+      fcurr2 = fnext2;
+      fcurr3 = fnext3;
+      fcurr4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+    *pDst++ = fcurr2;
+    *pDst++ = fcurr3;
+    *pDst++ = fcurr4;
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurr1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = fcurr1 + ((*pk) * gcurr1);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+    /* save g1(n) in state buffer */
+    *px++ = fcurr1;
+
+    /* f1(n) is saved in fcurr1   
+       for next stage processing */
+    fcurr1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* f1(n) is saved in fcurr1   
+         for next stage processing */
+      fcurr1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+
+    blkCnt--;
+
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t fcurr, fnext, gcurr, gnext;          /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = pCoeffs;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurr = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = fcurr + ((*pk) * gcurr);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = (fcurr * (*pk++)) + gcurr;
+
+    /* save f0(n) in state buffer */
+    *px++ = fcurr;
+
+    /* f1(n) is saved in fcurr           
+       for next stage processing */
+    fcurr = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = fcurr + ((*pk) * gcurr);
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = (fcurr * (*pk++)) + gcurr;
+
+      /* f1(n) is saved in fcurr1           
+         for next stage processing */
+      fcurr = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr;
+
+    blkCnt--;
+
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
new file mode 100644
index 0000000..36e19c2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
@@ -0,0 +1,75 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_lattice_init_f32.c   
+*   
+* Description:  Floating-point FIR Lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Initialization function for the floating-point FIR lattice filter.   
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.   
+ * @param[in] numStages  number of filter stages.   
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.   
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.   
+ * @return none.   
+ */
+
+void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
new file mode 100644
index 0000000..905e718
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
@@ -0,0 +1,75 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_lattice_init_q15.c   
+*   
+* Description:  Q15 FIR Lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for the Q15 FIR lattice filter.   
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.   
+   * @param[in] numStages  number of filter stages.   
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.    
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.    
+   * @return none.   
+   */
+
+void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
new file mode 100644
index 0000000..43ba1af
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
@@ -0,0 +1,75 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_lattice_init_q31.c   
+*   
+* Description:  Q31 FIR lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for the Q31 FIR lattice filter.   
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.   
+   * @param[in] numStages  number of filter stages.   
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.   
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.   
+   * @return none.   
+   */
+
+void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
new file mode 100644
index 0000000..3aff889
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
@@ -0,0 +1,528 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_lattice_q15.c   
+*   
+* Description:	Q15 FIR lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+
+/**   
+ * @brief Processing function for the Q15 FIR lattice filter.   
+ * @param[in]  *S        points to an instance of the Q15 FIR lattice structure.   
+ * @param[in]  *pSrc     points to the block of input data.   
+ * @param[out] *pDst     points to the block of output data   
+ * @param[in]  blockSize number of samples to process.   
+ * @return none.   
+ */
+
+void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *px;                                     /* temporary state pointer */
+  q15_t *pk;                                     /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurnt1, fnext1, gcurnt1 = 0, gnext1;    /* temporary variables for first sample in loop unrolling */
+  q31_t fcurnt2, fnext2, gnext2;                 /* temporary variables for second sample in loop unrolling */
+  q31_t fcurnt3, fnext3, gnext3;                 /* temporary variables for third sample in loop unrolling */
+  q31_t fcurnt4, fnext4, gnext4;                 /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurnt1 = *pSrc++;
+    fcurnt2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurnt1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+    fnext1 = __SSAT(fnext1, 16);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + gcurnt1;
+    gnext1 = __SSAT(gnext1, 16);
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + fcurnt2;
+    fnext2 = __SSAT(fnext2, 16);
+
+    gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt1;
+    gnext2 = __SSAT(gnext2, 16);
+
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurnt3 = *pSrc++;
+    fcurnt4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer   
+       which is used for next four samples processing */
+    *px++ = (q15_t) fcurnt4;
+
+    /* Process third sample for first tap */
+    fnext3 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt3;
+    fnext3 = __SSAT(fnext3, 16);
+    gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt2;
+    gnext3 = __SSAT(gnext3, 16);
+
+    /* Process fourth sample for first tap */
+    fnext4 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt4;
+    fnext4 = __SSAT(fnext4, 16);
+    gnext4 = (q31_t) ((fcurnt4 * (*pk++)) >> 15u) + fcurnt3;
+    gnext4 = __SSAT(gnext4, 16);
+
+    /* Update of f values for next coefficient set processing */
+    fcurnt1 = fnext1;
+    fcurnt2 = fnext2;
+    fcurnt3 = fnext3;
+    fcurnt4 = fnext4;
+
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1u) >> 2;
+
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while(stageCnt > 0u)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f1(n) = f0(n) +  K1 * g0(n-1) */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+      /* Process fourth sample for 2nd, 6th .. tap */
+      /* fnext4 = fcurnt4 + (*pk) * gnext3; */
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+      fcurnt1 = __SSAT(fcurnt1, 16);
+
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+      fcurnt2 = __SSAT(fcurnt2, 16);
+
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+      fcurnt3 = __SSAT(fcurnt3, 16);
+
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+      fcurnt4 = __SSAT(fcurnt4, 16);
+
+      /* Calculation of state values for next stage */
+      /* g3(n) = f2(n) * K3  +  g2(n-1) */
+      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+
+      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+
+      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+      fcurnt1 = __SSAT(fcurnt1, 16);
+
+      /* Process second sample for 5th, 9th .. tap */
+      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+      fcurnt2 = __SSAT(fcurnt2, 16);
+
+      /* Process third sample for 5th, 9th .. tap */
+      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+      fcurnt3 = __SSAT(fcurnt3, 16);
+
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+      fcurnt4 = __SSAT(fcurnt4, 16);
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1u) % 0x4u;
+
+    while(stageCnt > 0u)
+    {
+      gcurnt1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      /* Update of f values for next coefficient set processing */
+      fcurnt1 = fnext1;
+      fcurnt2 = fnext2;
+      fcurnt3 = fnext3;
+      fcurnt4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt1, fcurnt2, 16);
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt3, fcurnt4, 16);
+
+#else
+
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt2, fcurnt1, 16);
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt4, fcurnt3, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurnt1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurnt1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+    fnext1 = __SSAT(fnext1, 16);
+
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+    gnext1 = __SSAT(gnext1, 16);
+
+    /* save g1(n) in state buffer */
+    *px++ = (q15_t) fcurnt1;
+
+    /* f1(n) is saved in fcurnt1   
+       for next stage processing */
+    fcurnt1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* f1(n) is saved in fcurnt1   
+         for next stage processing */
+      fcurnt1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = __SSAT(fcurnt1, 16);
+
+
+    blkCnt--;
+
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t fcurnt, fnext, gcurnt, gnext;            /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurnt = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurnt = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+    fnext = __SSAT(fnext, 16);
+
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+    gnext = __SSAT(gnext, 16);
+
+    /* save f0(n) in state buffer */
+    *px++ = (q15_t) fcurnt;
+
+    /* f1(n) is saved in fcurnt           
+       for next stage processing */
+    fcurnt = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g1(n-1) from state buffer */
+      gcurnt = *px;
+
+      /* save g0(n-1) in state buffer */
+      *px++ = (q15_t) gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+      fnext = __SSAT(fnext, 16);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+      gnext = __SSAT(gnext, 16);
+
+
+      /* f1(n) is saved in fcurnt           
+         for next stage processing */
+      fcurnt = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = __SSAT(fcurnt, 16);
+
+
+    blkCnt--;
+
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
new file mode 100644
index 0000000..99c9a87
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_lattice_q31.c   
+*   
+* Description:	Q31 FIR lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+
+/**   
+ * @brief Processing function for the Q31 FIR lattice filter.   
+ * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.   
+ * @param[in]  *pSrc     points to the block of input data.   
+ * @param[out] *pDst     points to the block of output data   
+ * @param[in]  blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.   
+ */
+
+void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* temporary state pointer */
+  q31_t *pk;                                     /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurr1, fnext1, gcurr1 = 0, gnext1;      /* temporary variables for first sample in loop unrolling */
+  q63_t fcurr2, fnext2, gnext2;                  /* temporary variables for second sample in loop unrolling */
+  q63_t fcurr3, fnext3, gnext3;                  /* temporary variables for third sample in loop unrolling */
+  q63_t fcurr4, fnext4, gnext4;                  /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+    /* f0(n) = x(n) */
+    fcurr2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurr1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 31) + gcurr1;
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 31) + fcurr2;
+    gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + fcurr1;
+
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurr3 = *pSrc++;
+    fcurr4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer   
+       which will be used for next four samples processing */
+    *px++ = (q31_t) fcurr4;
+
+    /* Process third sample for first tap */
+    fnext3 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + fcurr3;
+    gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + fcurr2;
+
+    /* Process fourth sample for first tap */
+    fnext4 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + fcurr4;
+    gnext4 = (q31_t) (((q63_t) fcurr4 * (*pk++)) >> 31) + fcurr3;
+
+    /* save g1(n) in state buffer for next sample processing */
+    /* *px++ = gnext4;       */
+
+    /* Update of f values for next coefficient set processing */
+    fcurr1 = fnext1;
+    fcurr2 = fnext2;
+    fcurr3 = fnext3;
+    fcurr4 = fnext4;
+
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1u) >> 2u;
+
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while(stageCnt > 0u)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fcurr2;
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fcurr3;
+      /* Process fourth sample for 2nd, 6th .. tap */
+      fnext4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fcurr4;
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) (((q63_t) fcurr4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + gnext2;
+      gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + gnext1;
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g2(n) in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurr1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fnext1;
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fnext2;
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fnext3;
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurr4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fnext4;
+
+      /* Calculation of state values for next stage */
+      /*  gnext4 = fnext4 * (*pk) +  gnext3; */
+      gnext4 = (q31_t) (((q63_t) fnext4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 31) + gnext2;
+      /*  gnext2 = fnext2 * (*pk) +  gnext1; */
+      gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 31) + gnext1;
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      /*  gnext1 = fnext1 * (*pk++) +  gcurr1; */
+      gnext1 = (q31_t) (((q63_t) fnext1 * (*pk++)) >> 31) + gcurr1;
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fcurr2;
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fcurr3;
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fcurr4;
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) (((q63_t) fcurr4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + gnext2;
+      gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + gnext1;
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurr1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fnext1;
+      /* Process second sample for 5th, 9th .. tap */
+      fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fnext2;
+      /* Process third sample for 5th, 9th .. tap */
+      fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fnext3;
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurr4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fnext4;
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (q31_t) (((q63_t) fnext4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 31) + gnext2;
+      gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 31) + gnext1;
+      gnext1 = (q31_t) (((q63_t) fnext1 * (*pk++)) >> 31) + gcurr1;
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1u) % 0x4u;
+
+    while(stageCnt > 0u)
+    {
+      gcurr1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+      fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fcurr2;
+      fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fcurr3;
+      fnext4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fcurr4;
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (q31_t) (((q63_t) fcurr4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + gnext2;
+      gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + gnext1;
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+
+      /* Update of f values for next coefficient set processing */
+      fcurr1 = fnext1;
+      fcurr2 = fnext2;
+      fcurr3 = fnext3;
+      fcurr4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+    *pDst++ = (q31_t) fcurr2;
+    *pDst++ = (q31_t) fcurr3;
+    *pDst++ = (q31_t) fcurr4;
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurr1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+    /* save g1(n) in state buffer */
+    *px++ = fcurr1;
+
+    /* f1(n) is saved in fcurr1   
+       for next stage processing */
+    fcurr1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+
+      /* f1(n) is saved in fcurr1   
+         for next stage processing */
+      fcurr1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+
+    blkCnt--;
+
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q31_t fcurr, fnext, gcurr, gnext;              /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurr = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+    /* save g1(n) in state buffer */
+    *px++ = fcurr;
+
+    /* f1(n) is saved in fcurr1           
+       for next stage processing */
+    fcurr = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+
+      /* f1(n) is saved in fcurr1           
+         for next stage processing */
+      fcurr = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr;
+
+    blkCnt--;
+
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
new file mode 100644
index 0000000..ea011d5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
@@ -0,0 +1,368 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_q15.c   
+*   
+* Description:  Q15 FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 FIR filter.   
+ * @param[in] *S points to an instance of the Q15 FIR structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *px1;                                    /* Temporary q15 pointer for state buffer */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q31_t *px2;                                    /* Temporary q31 pointer for SIMD state buffer accesses */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold SIMD state and coefficient values */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer.   
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer of type q15 */
+    px1 = pState;
+
+    /* Initialize coeff pointer of type q31 */
+    pb = (q31_t *) (pCoeffs);
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = *(q31_t *) (px1++);
+
+    /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
+    x1 = *(q31_t *) (px1++);
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    tapCnt = numTaps >> 2;
+    do
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *(pb++);
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Read state x[n-N-2], x[n-N-3] */
+      x2 = *(q31_t *) (px1++);
+
+      /* Read state x[n-N-3], x[n-N-4] */
+      x3 = *(q31_t *) (px1++);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLALD(x2, c0, acc2);
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLALD(x3, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *(pb++);
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLALD(x2, c0, acc0);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLALD(x3, c0, acc1);
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = *(q31_t *) (px1++);
+
+      /* Read state x[n-N-5], x[n-N-6] */
+      x1 = *(q31_t *) (px1++);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLALD(x0, c0, acc2);
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLALD(x1, c0, acc3);
+      tapCnt--;
+
+    }
+    while(tapCnt > 0u);
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.   
+     ** This is always be 2 taps since the filter length is even. */
+    if((numTaps & 0x3u) != 0u)
+    {
+      /* Read 2 coefficients */
+      c0 = *(pb++);
+      /* Fetch 4 state variables */
+      x2 = *(q31_t *) (px1++);
+      x3 = *(q31_t *) (px1++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLALD(x0, c0, acc0);
+      acc1 = __SMLALD(x1, c0, acc1);
+      acc2 = __SMLALD(x2, c0, acc2);
+      acc3 = __SMLALD(x3, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.   
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+  while(blkCnt > 0u)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Use SIMD to hold states and coefficients */
+    px2 = (q31_t *) pState;
+    pb = (q31_t *) (pCoeffs);
+    tapCnt = numTaps >> 1;
+
+    do
+    {
+      acc0 = __SMLALD(*px2++, *(pb++), acc0);
+      tapCnt--;
+    }
+    while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy remaining data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc;                                     /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of nTaps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q31_t) * px++ * *pb++;
+      tapCnt--;
+    } while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15        
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) __SSAT((acc >> 15u), 16);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = (numTaps - 1u);
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
new file mode 100644
index 0000000..0891a76
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
@@ -0,0 +1,383 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_q31.c   
+*   
+* Description:	Q31 FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.   
+ * After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. 
+ *   
+ * \par   
+ * Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t x0, x1, x2, x3;                          /* Temporary variables to hold state */
+  q31_t c0;                                      /* Temporary variable to hold coefficient value */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:   
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      acc0 += ((q63_t) x0 * c0);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      acc1 += ((q63_t) x1 * c0);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      acc2 += ((q63_t) x2 * c0);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      acc3 += ((q63_t) x3 * c0);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x1 * c0);
+      acc1 += ((q63_t) x2 * c0);
+      acc2 += ((q63_t) x3 * c0);
+      acc3 += ((q63_t) x0 * c0);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x2 * c0);
+      acc1 += ((q63_t) x3 * c0);
+      acc2 += ((q63_t) x0 * c0);
+      acc3 += ((q63_t) x1 * c0);
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x3 * c0);
+      acc1 += ((q63_t) x0 * c0);
+      acc2 += ((q63_t) x1 * c0);
+      acc3 += ((q63_t) x2 * c0);
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4u);
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x0 * c0);
+      acc1 += ((q63_t) x1 * c0);
+      acc2 += ((q63_t) x2 * c0);
+      acc3 += ((q63_t) x3 * c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.62 format.  Convert to 1.31   
+     ** Then store the 4 outputs in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 >> 31u);
+    *pDst++ = (q31_t) (acc1 >> 31u);
+    *pDst++ = (q31_t) (acc2 >> 31u);
+    *pDst++ = (q31_t) (acc3 >> 31u);
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += (q63_t) * (px++) * (*(pb++));
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.62 format.  Convert to 1.31   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 >> 31u);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc;                                     /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Length of the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q63_t) * px++ * *pb++;
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.62 format.  Convert to 1.31        
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = numTaps - 1u;
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
new file mode 100644
index 0000000..42529d0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
@@ -0,0 +1,385 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_q7.c   
+*   
+* Description:  Q7 FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in]   *S points to an instance of the Q7 FIR filter structure.   
+ * @param[in]   *pSrc points to the block of input data.   
+ * @param[out]  *pDst points to the block of output data.   
+ * @param[in]   blockSize number of samples to process per call.   
+ * @return 	none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * The accumulator is converted to 18.7 format by discarding the low 7 bits.   
+ * Finally, the result is truncated to 1.7 format.   
+ */
+
+void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
+  q7_t x0, x1, x2, x3;                           /* Temporary variables to hold state */
+  q7_t c0;                                       /* Temporary variable to hold coefficient value */
+  q7_t *px;                                      /* Temporary pointer for state */
+  q7_t *pb;                                      /* Temporary pointer for coefficient buffer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:   
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      acc0 += ((q15_t) x0 * c0);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      acc1 += ((q15_t) x1 * c0);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      acc2 += ((q15_t) x2 * c0);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      acc3 += ((q15_t) x3 * c0);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x1 * c0);
+      acc1 += ((q15_t) x2 * c0);
+      acc2 += ((q15_t) x3 * c0);
+      acc3 += ((q15_t) x0 * c0);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x2 * c0);
+      acc1 += ((q15_t) x3 * c0);
+      acc2 += ((q15_t) x0 * c0);
+      acc3 += ((q15_t) x1 * c0);
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x3 * c0);
+      acc1 += ((q15_t) x0 * c0);
+      acc2 += ((q15_t) x1 * c0);
+      acc3 += ((q15_t) x2 * c0);
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4u);
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x0 * c0);
+      acc1 += ((q15_t) x1 * c0);
+      acc2 += ((q15_t) x2 * c0);
+      acc3 += ((q15_t) x3 * c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.62 format.  Convert to 1.31   
+     ** Then store the 4 outputs in the destination buffer. */
+    acc0 = __SSAT((acc0 >> 7u), 8);
+    *pDst++ = acc0;
+    acc1 = __SSAT((acc1 >> 7u), 8);
+    *pDst++ = acc1;
+    acc2 = __SSAT((acc2 >> 7u), 8);
+    *pDst++ = acc2;
+    acc3 = __SSAT((acc3 >> 7u), 8);
+    *pDst++ = acc3;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += (q15_t) * (px++) * (*(pb++));
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.14 format.  Convert to 1.7   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = __SSAT((acc0 >> 7u), 8);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *px, *pb;                                 /* Temporary pointers to state and coeff */
+  q31_t acc = 0;                                 /* Accumlator */
+  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  /* Perform filtering upto BlockSize - BlockSize%4  */
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer of type q7 */
+    px = pState;
+
+    /* Initialize coeff pointer of type q7 */
+    pb = pCoeffs;
+
+
+    i = numTaps;
+
+    while(i > 0u)
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q15_t) * px++ * *pb++;
+      i--;
+    }
+
+    /* Store the 1.7 format filter output in destination buffer */
+    *pDst++ = (q7_t) __SSAT((acc >> 7), 8);
+
+    /* Advance the state pointer by 1 to process the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+
+  /* Copy numTaps number of values */
+  i = (numTaps - 1u);
+
+  /* Copy q7_t data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
new file mode 100644
index 0000000..aaede62
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
@@ -0,0 +1,362 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_sparse_f32.c   
+*   
+* Description:	Floating-point sparse FIR filter processing function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters   
+ *   
+ * This group of functions implements sparse FIR filters.    
+ * Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.  
+ * Sparse filters are used for simulating reflections in communications and audio applications.  
+ *  
+ * There are separate functions for Q7, Q15, Q31, and floating-point data types.   
+ * The functions operate on blocks  of input and output data and each call to the function processes   
+ * blockSize samples through the filter.  pSrc and   
+ * pDst points to input and output arrays respectively containing blockSize values.   
+ *   
+ * \par Algorithm:   
+ * The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients.  
+ * This is in addition to the coefficient array b.  
+ * The implementation essentially skips the multiplications by zero and leads to an efficient realization.  
+ * 
  
+ *     y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]   
+ * 
   
+ * \par   
+ * \image html FIRSparse.gif "Sparse FIR filter.  b[n] represents the filter coefficients"  
+ * \par   
+ * pCoeffs points to a coefficient array of size numTaps;   
+ * pTapDelay points to an array of nonzero indices and is also of size numTaps;  
+ * pState points to a state array of size maxDelay + blockSize, where  
+ * maxDelay is the largest offset value that is ever used in the pTapDelay array.  
+ * Some of the processing functions also require temporary working buffers.  
+ *  
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 4 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * The code below statically initializes each of the 4 different data type filter instance structures   
+ * 
   
+ *arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ *arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ *arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ *arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ * 
   
+ * \par   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the sparse FIR filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief Processing function for the floating-point sparse FIR filter.  
+ * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.  
+ * @param[in]  *pSrc       points to the block of input data.  
+ * @param[out] *pDst       points to the block of output data  
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.  
+ * @param[in]  blockSize   number of input samples to process per call.  
+ * @return none.  
+ */
+
+void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize)
+{
+
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *px;                                 /* Scratch buffer pointer */
+  float32_t *py = pState;                        /* Temporary pointers for state buffer */
+  float32_t *pb = pScratchIn;                    /* Temporary pointers for scratch buffer */
+  float32_t *pOut;                               /* Destination pointer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter  */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  float32_t coeff = *pCoeffs++;                  /* Read the first coefficient value */
+
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+                        (int32_t *) pSrc, 1, blockSize);
+
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                       blockSize);
+
+  /* Working pointer for the scratch buffer */
+  px = pb;
+
+  /* Working pointer for destination buffer */
+  pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * Compute 4 Multiplications at a time. */
+  blkCnt = blockSize >> 2u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and   
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer */
+    px = pb;
+
+    /* Working pointer for destination buffer */
+    pOut = pDst;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.   
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,   
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and   
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = ((int32_t) S->stateIndex -
+                 (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and          
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer */
+    px = pb;
+
+    /* Working pointer for destination buffer */
+    pOut = pDst;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and          
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex =
+      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
new file mode 100644
index 0000000..3e423a1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_sparse_init_f32.c   
+*   
+* Description:	Floating-point sparse FIR filter initialization function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the floating-point sparse FIR filter.  
+ * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.  
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.  
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.  
+ * @param[in]     *pState    points to the state buffer.  
+ * @param[in]     *pTapDelay points to the array of offset times.  
+ * @param[in]     maxDelay   maximum offset time supported.  
+ * @param[in]     blockSize  number of samples that will be processed per block.  
+ * @return none  
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs holds the filter coefficients and has length numTaps.   
+ * pState holds the filter's state variables and must be of length   
+ * maxDelay + blockSize, where maxDelay   
+ * is the maximum number of delay line values.   
+ * blockSize is the   
+ * number of samples processed by the arm_fir_sparse_f32() function.   
+ */
+
+void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
new file mode 100644
index 0000000..196b45e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_sparse_init_q15.c   
+*   
+* Description:	Q15 sparse FIR filter initialization function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the Q15 sparse FIR filter.  
+ * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.  
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.  
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.  
+ * @param[in]     *pState    points to the state buffer.  
+ * @param[in]     *pTapDelay points to the array of offset times.  
+ * @param[in]     maxDelay   maximum offset time supported.  
+ * @param[in]     blockSize  number of samples that will be processed per block.  
+ * @return none  
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs holds the filter coefficients and has length numTaps.   
+ * pState holds the filter's state variables and must be of length   
+ * maxDelay + blockSize, where maxDelay   
+ * is the maximum number of delay line values.   
+ * blockSize is the   
+ * number of words processed by arm_fir_sparse_q15() function.   
+ */
+
+void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
new file mode 100644
index 0000000..7d1f35d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_sparse_init_q31.c   
+*   
+* Description:	Q31 sparse FIR filter initialization function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the Q31 sparse FIR filter.  
+ * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.  
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.  
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.  
+ * @param[in]     *pState    points to the state buffer.  
+ * @param[in]     *pTapDelay points to the array of offset times.  
+ * @param[in]     maxDelay   maximum offset time supported.  
+ * @param[in]     blockSize  number of samples that will be processed per block.  
+ * @return none  
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs holds the filter coefficients and has length numTaps.   
+ * pState holds the filter's state variables and must be of length   
+ * maxDelay + blockSize, where maxDelay   
+ * is the maximum number of delay line values.   
+ * blockSize is the number of words processed by arm_fir_sparse_q31() function.   
+ */
+
+void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
new file mode 100644
index 0000000..c93d6a2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_sparse_init_q7.c   
+*   
+* Description:	Q7 sparse FIR filter initialization function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the Q7 sparse FIR filter.  
+ * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.  
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.  
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.  
+ * @param[in]     *pState    points to the state buffer.  
+ * @param[in]     *pTapDelay points to the array of offset times.  
+ * @param[in]     maxDelay   maximum offset time supported.  
+ * @param[in]     blockSize  number of samples that will be processed per block.  
+ * @return none  
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs holds the filter coefficients and has length numTaps.   
+ * pState holds the filter's state variables and must be of length   
+ * maxDelay + blockSize, where maxDelay   
+ * is the maximum number of delay line values.   
+ * blockSize is the   
+ * number of samples processed by the arm_fir_sparse_q7() function.   
+ */
+
+void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
new file mode 100644
index 0000000..28abfa5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_sparse_q15.c   
+*   
+* Description:	Q15 sparse FIR filter processing function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief Processing function for the Q15 sparse FIR filter.  
+ * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.  
+ * @param[in]  *pSrc        points to the block of input data.  
+ * @param[out] *pDst        points to the block of output data  
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.  
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.  
+ * @param[in]  blockSize    number of input samples to process per call.  
+ * @return none.  
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 32-bit accumulator.  
+ * The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.  
+ * Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.  
+ * If the accumulator result overflows it will wrap around rather than saturate.  
+ * After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.   
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.  
+ */
+
+
+void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize)
+{
+
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pIn = pSrc;                             /* Working pointer for input */
+  q15_t *pOut = pDst;                            /* Working pointer for output */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *px;                                     /* Temporary pointers for scratch buffer */
+  q15_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
+  q15_t *py = pState;                            /* Temporary pointers for state buffer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q15_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
+  q31_t *pScr2 = pScratchOut;                    /* Working pointer for pScratchOut */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in1, in2;                                /* Temporary variables */
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                       pb, pb, blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * Compute 4 multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and   
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                         pb, pb, blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.   
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,   
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and   
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.   
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in1 = *pScr2++;
+    in2 = *pScr2++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+              16);
+
+#else
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+              16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    in1 = *pScr2++;
+
+    in2 = *pScr2++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+              16);
+
+#else
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+              16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+    blkCnt--;
+
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+     remaining samples are processed in the below loop */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                       pb, pb, blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and          
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                         pb, pb, blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and          
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.      
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
new file mode 100644
index 0000000..5bbd110
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
@@ -0,0 +1,367 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_sparse_q31.c   
+*   
+* Description:	Q31 sparse FIR filter processing function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief Processing function for the Q31 sparse FIR filter.  
+ * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.  
+ * @param[in]  *pSrc       points to the block of input data.  
+ * @param[out] *pDst       points to the block of output data  
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.  
+ * @param[in]  blockSize   number of input samples to process per call.  
+ * @return none.  
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 32-bit accumulator.  
+ * The 1.31 x 1.31 multiplications are truncated to 2.30 format.  
+ * This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.   
+ * If the accumulator result overflows, it wraps around rather than saturate.  
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.  
+ */
+
+void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize)
+{
+
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* Scratch buffer pointer */
+  q31_t *py = pState;                            /* Temporary pointers for state buffer */
+  q31_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
+  q31_t *pOut;                                   /* Destination pointer */
+  q63_t out;                                     /* Temporary output variable */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q31_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
+  q31_t in;
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+                        (int32_t *) pSrc, 1, blockSize);
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                       blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * Compute 4 Multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and   
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pOut = pDst;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.   
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,   
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and   
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* Working output pointer is updated */
+  pOut = pDst;
+
+  /* Output is converted into 1.31 format. */
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * process 4 output samples at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * process the remaining output samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and          
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pOut = pDst;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and          
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* Working output pointer is updated */
+  pOut = pDst;
+
+  /* Output is converted into 1.31 format. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
new file mode 100644
index 0000000..bcba31a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_sparse_q7.c   
+*   
+* Description:	Q7 sparse FIR filter processing function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+
+/**  
+ * @brief Processing function for the Q7 sparse FIR filter.  
+ * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.  
+ * @param[in]  *pSrc        points to the block of input data.  
+ * @param[out] *pDst        points to the block of output data  
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.  
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.  
+ * @param[in]  blockSize    number of input samples to process per call.  
+ * @return none.  
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * The accumulator is then converted to 18.7 format by discarding the low 7 bits.  
+ * Finally, the result is truncated to 1.7 format.  
+ */
+
+void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize)
+{
+
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *px;                                      /* Scratch buffer pointer */
+  q7_t *py = pState;                             /* Temporary pointers for state buffer */
+  q7_t *pb = pScratchIn;                         /* Temporary pointers for scratch buffer */
+  q7_t *pOut = pDst;                             /* Destination pointer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q7_t coeff = *pCoeffs++;                       /* Read the coefficient value */
+  q31_t *pScr2 = pScratchOut;                    /* Working pointer for scratch buffer of output values */
+  q31_t in;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t in1, in2, in3, in4;
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+                       blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                      (int32_t) blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * Compute 4 multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and   
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                        (int32_t) blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.   
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,   
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and   
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = ((int32_t) S->stateIndex -
+                 (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.   
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    *__SIMD32(pOut)++ = __PACKq7(in1, in2, in3, in4);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+     remaining samples are processed in the below loop */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+                       blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                      (int32_t) blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and          
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                        (int32_t) blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize */
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and          
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex =
+      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.      
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
new file mode 100644
index 0000000..6185ccd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
@@ -0,0 +1,402 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_iir_lattice_f32.c   
+*   
+* Description:	Floating-point IIR Lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters   
+ *   
+ * This set of functions implements lattice filters   
+ * for Q15, Q31 and floating-point data types.  Lattice filters are used in a    
+ * variety of adaptive filter applications.  The filter structure has feedforward and   
+ * feedback components and the net impulse response is infinite length.   
+ * The functions operate on blocks   
+ * of input and output data and each call to the function processes   
+ * blockSize samples through the filter.  pSrc and   
+ * pDst point to input and output arrays containing blockSize values.   
+   
+ * \par Algorithm:   
+ * \image html IIRLattice.gif "Infinite Impulse Response Lattice filter"   
+ * 
   
+ *    fN(n)   =  x(n)   
+ *    fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ...1   
+ *    gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1   
+ *    y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)   
+ * 
   
+ * \par   
+ * pkCoeffs points to array of reflection coefficients of size numStages.    
+ * Reflection coefficients are stored in time-reversed order.   
+ * \par   
+ * 
   
+ *    {kN, kN-1, ....k1}   
+ * 
   
+ * pvCoeffs points to the array of ladder coefficients of size (numStages+1).    
+ * Ladder coefficients are stored in time-reversed order.   
+ * \par   
+ * 
   
+ *    {vN, vN-1, ...v0}   
+ * 
   
+ * pState points to a state array of size numStages + blockSize.   
+ * The state variables shown in the figure above (the g values) are stored in the pState array.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+  *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:   
+ * 
   
+ *arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+ *arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+ *arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+ * 
   
+ * \par   
+ * where numStages is the number of stages in the filter; pState points to the state buffer array;   
+ * pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients.   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the IIR lattice filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the floating-point IIR lattice filter.   
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ */
+
+void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t fcurr, fnext = 0, gcurr, gnext;      /* Temporary variables for lattice stages */
+  float32_t acc;                                 /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */
+  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  float32_t *pState;                             /* State pointer */
+  float32_t *pStateCurnt;                        /* State current pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  gcurr = 0.0f;
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0.0f;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = fcurr - ((*pk) * gcurr);
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = (fnext * (*pk++)) + gcurr;
+    /* write gN(n) into state for next sample processing */
+    *px2++ = gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += (gnext * (*pv++));
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1u) >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Process sample for 2nd, 6th ...taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 2nd, 6th .. taps */
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = fcurr - ((*pk) * gcurr);
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = (fnext * (*pk++)) + gcurr;
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      acc += (gnext * (*pv++));
+      /* write gN-1(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = fnext - ((*pk) * gcurr);
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = (fcurr * (*pk++)) + gcurr;
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc += (gnext * (*pv++));
+      /* write gN-2(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = fcurr - ((*pk) * gcurr);
+      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+      gnext = (fnext * (*pk++)) + gcurr;
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc += (gnext * (*pv++));
+      /* write gN-3(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
+      fcurr = fnext - ((*pk) * gcurr);
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = (fcurr * (*pk++)) + gcurr;
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      acc += (gnext * (*pv++));
+      /* write gN-4(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1u) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - ((*pk) * gcurr);
+      gnext = (fnext * (*pk++)) + gcurr;
+      /* Output samples for last taps */
+      acc += (gnext * (*pv++));
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+
+    }
+
+
+    /* y(n) += g0(n) * v0 */
+    acc += (fnext * (*pv));
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = acc;
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer   
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numStages) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0.0f;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for numStages */
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - ((*pk) * gcurr);
+      gnext = (fnext * (*pk++)) + gcurr;
+
+      /* Output samples for last taps */
+      acc += (gnext * (*pv++));
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      /* Decrementing loop counter */
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (fnext * (*pv));
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = acc;
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer          
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages;
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
new file mode 100644
index 0000000..07f58b9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_iir_lattice_init_f32.c   
+*   
+* Description:  Floating-point IIR lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Initialization function for the floating-point IIR lattice filter.   
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.   
+ * @param[in] numStages number of stages in the filter.   
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.   
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.   
+ * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ */
+
+void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+  /**   
+   * @} end of IIR_Lattice group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
new file mode 100644
index 0000000..d346a93
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_iir_lattice_init_q15.c   
+*   
+* Description:  Q15 IIR lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for the Q15 IIR lattice filter.   
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.   
+   * @param[in] numStages  number of stages in the filter.   
+   * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.   
+   * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.   
+   * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.   
+   * @param[in] blockSize number of samples to process per call.   
+   * @return none.   
+   */
+
+void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
new file mode 100644
index 0000000..d3fe2df
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_iir_lattice_init_q31.c   
+*   
+* Description:  Initialization function for the Q31 IIR lattice filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for the Q31 IIR lattice filter.   
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.   
+   * @param[in] numStages number of stages in the filter.   
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.   
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.   
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.   
+   * @param[in] blockSize number of samples to process.   
+   * @return none.   
+   */
+
+void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
new file mode 100644
index 0000000..d823337
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_iir_lattice_q15.c   
+*   
+* Description:	Q15 IIR lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 IIR lattice filter.   
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ */
+
+void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurr, fnext, gcurr = 0, gnext;          /* Temporary variables for lattice stages */
+  q15_t gnext1, gnext2;                          /* Temporary variables for lattice stages */
+  uint32_t stgCnt;                               /* Temporary variables for counts */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pStateCurnt;                            /* State current pointer */
+  q15_t out;                                     /* Temporary variable for output */
+  q31_t v;                                       /* Temporary variable for ladder coefficient */
+
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+    fnext = __SSAT(fnext, 16);
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+    gnext = __SSAT(gnext, 16);
+    /* write gN(n) into state for next sample processing */
+    *px2++ = (q15_t) gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += (q31_t) ((gnext * (*pv++)));
+
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1u) >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Process sample for 2nd, 6th ...taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 2nd, 6th .. taps */
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext1 = (q15_t) __SSAT(gnext, 16);
+      /* write gN-1(n) into state */
+      *px2++ = (q15_t) gnext1;
+
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+      fcurr = __SSAT(fcurr, 16);
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+      gnext2 = (q15_t) __SSAT(gnext, 16);
+      /* write gN-2(n) into state */
+      *px2++ = (q15_t) gnext2;
+
+      /* Read vN-1 and vN-2 at a time */
+      v = *__SIMD32(pv)++;
+
+
+      /* Pack gN-1(n) and gN-2(n) */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+      gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc = __SMLALD(gnext, v, acc);
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext1 = (q15_t) __SSAT(gnext, 16);
+      /* write  gN-3(n) for the next sample process */
+      *px2++ = (q15_t) gnext1;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
+      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+      fcurr = __SSAT(fcurr, 16);
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+      gnext2 = (q15_t) __SSAT(gnext, 16);
+      /* write      gN-4(n) for the next sample process */
+      *px2++ = (q15_t) gnext2;
+
+      /* Read vN-3 and vN-4 at a time */
+      v = *__SIMD32(pv)++;
+
+      /* Pack gN-3(n) and gN-4(n) */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+      gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc = __SMLALD(gnext, v, acc);
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1u) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext = __SSAT(gnext, 16);
+      /* Output samples for last taps */
+      acc += (q31_t) (((q31_t) gnext * (*pv++)));
+      *px2++ = (q15_t) gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q31_t) (((q31_t) fnext * (*pv++)));
+
+    out = (q15_t) __SSAT(acc >> 15, 16);
+    *px2++ = (q15_t) fnext;
+
+    /* write out into pDst */
+    *pDst++ = out;
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer   
+     for the preperation of next frame process */
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  stgCnt = (numStages >> 2u);
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  stgCnt = (numStages) % 0x4u;
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
+  uint32_t stgCnt;                               /* Temporary variables for counts */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pStateCurnt;                            /* State current pointer */
+  q15_t out;                                     /* Temporary variable for output */
+
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample */
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext = fcurr - ((gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+      gnext = ((fnext * (*pk++)) >> 15) + gcurr;
+      gnext = __SSAT(gnext, 16);
+      /* Output samples */
+      /* y(n) += gN(n) * vN */
+      acc += (q31_t) ((gnext * (*pv++)));
+      /* write gN(n) into state for next sample processing */
+      *px2++ = (q15_t) gnext;
+      /* Update f values for next coefficient processing */
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q31_t) ((fnext * (*pv++)));
+
+    out = (q15_t) __SSAT(acc >> 15, 16);
+    *px2++ = (q15_t) fnext;
+
+    /* write out into pDst */
+    *pDst++ = out;
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer          
+     for the preperation of next frame process */
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  stgCnt = numStages;
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
new file mode 100644
index 0000000..1152246
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
@@ -0,0 +1,342 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_iir_lattice_q31.c   
+*   
+* Description:	Q31 IIR lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 IIR lattice filter.   
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.   
+ * After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.   
+ */
+
+void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q31_t *px1, *px2, *pk, *pv;                    /* Temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pStateCurnt;                            /* State current pointer */
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+    /* write gN-1(n-1) into state for next sample processing */
+    *px2++ = gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += ((q63_t) gnext * *pv++);
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1u) >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Process sample for 2nd, 6th .. taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-1(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-2(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-3(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
+      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-4(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1u) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* Output samples for last taps */
+      acc += ((q63_t) gnext * *pv++);
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q63_t) fnext *(
+  *pv++);
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer   
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numStages) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  };
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample */
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext =
+        clip_q63_to_q31(((q63_t) fcurr -
+                         ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));
+      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+      gnext =
+        clip_q63_to_q31(((q63_t) gcurr +
+                         ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
+      /* Output samples */
+      /* y(n) += gN(n) * vN  */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-1(n-1) into state for next sample processing */
+      *px2++ = gnext;
+      /* Update f values for next coefficient processing */
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q63_t) fnext *(
+  *pv++);
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer          
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
new file mode 100644
index 0000000..1305321
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
@@ -0,0 +1,431 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_f32.c   
+*   
+* Description:	Processing function for the floating-point LMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup LMS Least Mean Square (LMS) Filters   
+ *   
+ * LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions.   
+ * LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.   
+ * Adaptive filters are often used in communication systems, equalizers, and noise removal.   
+ * The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.   
+ * The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.   
+ *   
+ * An LMS filter consists of two components as shown below.   
+ * The first component is a standard transversal or FIR filter.   
+ * The second component is a coefficient update mechanism.   
+ * The LMS filter has two input signals.   
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.   
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.   
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.   
+ * This "error signal" tends towards zero as the filter adapts.   
+ * The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.   
+ * \image html LMS.gif "Internal structure of the Least Mean Square filter"   
+ *   
+ * The functions operate on blocks of data and each call to the function processes   
+ * blockSize samples through the filter.   
+ * pSrc points to input signal, pRef points to reference signal,   
+ * pOut points to output signal and pErr points to error signal.   
+ * All arrays contain blockSize values.   
+ *   
+ * The functions operate on a block-by-block basis.   
+ * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.   
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.   
+ *   
+ * \par Algorithm:   
+ * The output signal y[n] is computed by a standard FIR filter:   
+ * 
   
+ *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ * 
   
+ *   
+ * \par   
+ * The error signal equals the difference between the reference signal d[n] and the filter output:   
+ * 
   
+ *     e[n] = d[n] - y[n].   
+ * 
   
+ *   
+ * \par   
+ * After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis:   
+ * 
   
+ *     b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1   
+ * 
   
+ * where mu is the step size and controls the rate of coefficient convergence.   
+ *\par   
+ * In the APIs, pCoeffs points to a coefficient array of size numTaps.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to a state array of size numTaps + blockSize - 1.   
+ * Samples in the state buffer are stored in the order:   
+ * \par   
+ * 
   
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
   
+ * \par   
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.   
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,   
+ * to be avoided and yields a significant speed improvement.   
+ * The state variables are updated after each block of data is processed.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter and   
+ * coefficient and state arrays cannot be shared among instances.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * The code below statically initializes each of the 3 different data type filter instance structures   
+ * 
   
+ *    arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};   
+ *    arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};   
+ *    arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};   
+ * 
   
+ * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.   
+ *   
+ * \par Fixed-Point Behavior:   
+ * Care must be taken when using the Q15 and Q31 versions of the LMS filter.   
+ * The following issues must be considered:   
+ * - Scaling of coefficients   
+ * - Overflow and saturation   
+ *   
+ * \par Scaling of Coefficients:   
+ * Filter coefficients are represented as fractional values and   
+ * coefficients are restricted to lie in the range [-1 +1).   
+ * The fixed-point functions have an additional scaling parameter postShift.   
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.   
+ * This essentially scales the filter coefficients by 2^postShift and   
+ * allows the filter coefficients to exceed the range [+1 -1).   
+ * The value of postShift is set by the user based on the expected gain through the system being modeled.   
+ *   
+ * \par Overflow and Saturation:   
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are   
+ * described separately as part of the function specific documentation below.   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+/**          
+ * @details          
+ * This function operates on floating-point data types.      
+ *   
+ * @brief Processing function for floating-point LMS filter.   
+ * @param[in]  *S points to an instance of the floating-point LMS filter structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[in]  *pRef points to the block of reference data.   
+ * @param[out] *pOut points to the block of output data.   
+ * @param[out] *pErr points to the block of error data.   
+ * @param[in]  blockSize number of samples to process.   
+ * @return     none.   
+ */
+
+void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t mu = S->mu;                          /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
+  float32_t w = 0.0f;                            /* weight factor */
+
+  e = 0.0f;
+  d = 0.0f;
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator, store in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for the updating filter coefficients */
+    w = e * mu;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result is stored in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Weighting factor for the LMS version */
+    w = e * mu;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the       
+   * start of the state buffer. This prepares the state buffer for the       
+   * next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of LMS group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
new file mode 100644
index 0000000..46c0104
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
@@ -0,0 +1,87 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_init_f32.c   
+*   
+* Description:  Floating-point LMS filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for floating-point LMS filter.   
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to the coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @return none.   
+   */
+
+/**   
+ * \par Description:   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32().   
+ */
+
+void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps */
+  memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+}
+
+/**   
+ * @} end of LMS group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
new file mode 100644
index 0000000..5caa0a3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
@@ -0,0 +1,97 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_init_q15.c   
+*   
+* Description:  Q15 LMS filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+/**   
+* @brief Initialization function for the Q15 LMS filter.   
+* @param[in] *S points to an instance of the Q15 LMS filter structure.   
+* @param[in] numTaps  number of filter coefficients.   
+* @param[in] *pCoeffs points to the coefficient buffer.   
+* @param[in] *pState points to the state buffer.   
+* @param[in] mu step size that controls filter coefficient updates.   
+* @param[in] blockSize number of samples to process.   
+* @param[in] postShift bit shift applied to coefficients.   
+* @return    none.   
+*   
+* \par Description:   
+* pCoeffs points to the array of filter coefficients stored in time reversed order:   
+* 
   
+*    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+* 
   
+* The initial filter coefficients serve as a starting point for the adaptive filter.   
+* pState points to the array of state variables and size of array is   
+* numTaps+blockSize-1 samples, where blockSize is the number of   
+* input samples processed by each call to arm_lms_q15().   
+*/
+
+void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Assign postShift value to be applied */
+  S->postShift = postShift;
+
+}
+
+/**   
+ * @} end of LMS group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
new file mode 100644
index 0000000..7d8fd49
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
@@ -0,0 +1,97 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_init_q31.c   
+*   
+* Description:  Q31 LMS filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for Q31 LMS filter.   
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @param[in] postShift bit shift applied to coefficients.   
+   * @return none.   
+ *   
+ * \par Description:   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to an array of length numTaps+blockSize-1 samples,   
+ * where blockSize is the number of input samples processed by each call to   
+ * arm_lms_q31().   
+ */
+
+void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, ((uint32_t) numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Assign postShift value to be applied */
+  S->postShift = postShift;
+
+}
+
+/**   
+ * @} end of LMS group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
new file mode 100644
index 0000000..ee60229
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
@@ -0,0 +1,453 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_norm_f32.c   
+*   
+* Description:	Processing function for the floating-point Normalised LMS.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup LMS_NORM Normalized LMS Filters   
+ *   
+ * This set of functions implements a commonly used adaptive filter.   
+ * It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization   
+ * factor which increases the adaptation rate of the filter.   
+ * The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.   
+ *   
+ * A normalized least mean square (NLMS) filter consists of two components as shown below.   
+ * The first component is a standard transversal or FIR filter.   
+ * The second component is a coefficient update mechanism.   
+ * The NLMS filter has two input signals.   
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.   
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.   
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.   
+ * This "error signal" tends towards zero as the filter adapts.   
+ * The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.   
+ * \image html LMS.gif "Internal structure of the NLMS adaptive filter"   
+ *   
+ * The functions operate on blocks of data and each call to the function processes   
+ * blockSize samples through the filter.   
+ * pSrc points to input signal, pRef points to reference signal,   
+ * pOut points to output signal and pErr points to error signal.   
+ * All arrays contain blockSize values.   
+ *   
+ * The functions operate on a block-by-block basis.   
+ * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.   
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.   
+ *   
+ * \par Algorithm:   
+ * The output signal y[n] is computed by a standard FIR filter:   
+ * 
   
+ *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ * 
   
+ *   
+ * \par   
+ * The error signal equals the difference between the reference signal d[n] and the filter output:   
+ * 
   
+ *     e[n] = d[n] - y[n].   
+ * 
   
+ *   
+ * \par   
+ * After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:   
+ * 
   
+ *    E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.   
+ * 
   
+ * The filter coefficients b[k] are then updated on a sample-by-sample basis:   
+ * 
   
+ *     b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1   
+ * 
   
+ * where mu is the step size and controls the rate of coefficient convergence.   
+ *\par   
+ * In the APIs, pCoeffs points to a coefficient array of size numTaps.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * \par   
+ * pState points to a state array of size numTaps + blockSize - 1.   
+ * Samples in the state buffer are stored in the order:   
+ * \par   
+ * 
   
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
   
+ * \par   
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.   
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,   
+ * to be avoided and yields a significant speed improvement.   
+ * The state variables are updated after each block of data is processed.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter and   
+ * coefficient and state arrays cannot be shared among instances.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * \par   
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.   
+ * \par Fixed-Point Behavior:   
+ * Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.   
+ * The following issues must be considered:   
+ * - Scaling of coefficients   
+ * - Overflow and saturation   
+ *   
+ * \par Scaling of Coefficients:   
+ * Filter coefficients are represented as fractional values and   
+ * coefficients are restricted to lie in the range [-1 +1).   
+ * The fixed-point functions have an additional scaling parameter postShift.   
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.   
+ * This essentially scales the filter coefficients by 2^postShift and   
+ * allows the filter coefficients to exceed the range [+1 -1).   
+ * The value of postShift is set by the user based on the expected gain through the system being modeled.   
+ *   
+ * \par Overflow and Saturation:   
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are   
+ * described separately as part of the function specific documentation below.   
+ */
+
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+
+  /**   
+   * @brief Processing function for floating-point normalized LMS filter.   
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.   
+   * @param[in] *pSrc points to the block of input data.   
+   * @param[in] *pRef points to the block of reference data.   
+   * @param[out] *pOut points to the block of output data.   
+   * @param[out] *pErr points to the block of error data.   
+   * @param[in] blockSize number of samples to process.   
+   * @return none.   
+   */
+
+void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t mu = S->mu;                          /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  float32_t energy;                              /* Energy of the input */
+  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
+  float32_t w, x0, in;                           /* weight factor, temporary variable to hold input sample and state */
+
+  /* Initializations of error,  difference, Coefficient update */
+  e = 0.0f;
+  d = 0.0f;
+  w = 0.0f;
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= x0 * x0;
+    energy += in * in;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator, store in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for updating filter coefficients */
+    /* epsilon value 0.000000119209289f */
+    w = (e * mu) / (energy + 0.000000119209289f);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  S->energy = energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u)/4 samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= x0 * x0;
+    energy += in * in;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator is stored in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for updating filter coefficients */
+    /* epsilon value 0.000000119209289f */
+    w = (e * mu) / (energy + 0.000000119209289f);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCcoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  S->energy = energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the       
+     satrt of the state buffer. This prepares the state buffer for the       
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of LMS_NORM group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
new file mode 100644
index 0000000..7621ca1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
@@ -0,0 +1,97 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_norm_init_f32.c   
+*   
+* Description:  Floating-point NLMS filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for floating-point normalized LMS filter.   
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @return none.   
+   *   
+ * \par Description:   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to an array of length numTaps+blockSize-1 samples,   
+ * where blockSize is the number of input samples processed by each call to arm_lms_norm_f32().   
+ */
+
+void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialise Energy to zero */
+  S->energy = 0.0f;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0.0f;
+
+}
+
+/**   
+ * @} end of LMS_NORM group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
new file mode 100644
index 0000000..758a578
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
@@ -0,0 +1,104 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_norm_init_q15.c   
+*   
+* Description:  Q15 NLMS initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for Q15 normalized LMS filter.   
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @param[in] postShift bit shift applied to coefficients.   
+   * @return none.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to the array of state variables and size of array is   
+ * numTaps+blockSize-1 samples, where blockSize is the number of input samples processed   
+ * by each call to arm_lms_norm_q15().   
+ */
+
+void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign post Shift value applied to coefficients */
+  S->postShift = postShift;
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialize reciprocal pointer table */
+  S->recipTable = armRecipTableQ15;
+
+  /* Initialise Energy to zero */
+  S->energy = 0;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0;
+
+}
+
+/**   
+ * @} end of LMS_NORM group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
new file mode 100644
index 0000000..781201e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
@@ -0,0 +1,103 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_norm_init_q31.c   
+*   
+* Description:  Q31 NLMS initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for Q31 normalized LMS filter.   
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @param[in] postShift bit shift applied to coefficients.   
+   * @return none.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
   
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
   
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to an array of length numTaps+blockSize-1 samples,   
+ * where blockSize is the number of input samples processed by each call to arm_lms_norm_q31().   
+ */
+
+void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1  */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+  /* Assign post Shift value applied to coefficients */
+  S->postShift = postShift;
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialize reciprocal pointer table */
+  S->recipTable = armRecipTableQ31;
+
+  /* Initialise Energy to zero */
+  S->energy = 0;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0;
+
+}
+
+/**   
+ * @} end of LMS_NORM group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
new file mode 100644
index 0000000..6417fe4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
@@ -0,0 +1,386 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_norm_q15.c   
+*   
+* Description:	Q15 NLMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+/**   
+* @brief Processing function for Q15 normalized LMS filter.   
+* @param[in] *S points to an instance of the Q15 normalized LMS filter structure.   
+* @param[in] *pSrc points to the block of input data.   
+* @param[in] *pRef points to the block of reference data.   
+* @param[out] *pOut points to the block of output data.   
+* @param[out] *pErr points to the block of error data.   
+* @param[in] blockSize number of samples to process.   
+* @return none.   
+*   
+* Scaling and Overflow Behavior:    
+* \par    
+* The function is implemented using a 64-bit internal accumulator.    
+* Both coefficients and state variables are represented in 1.15 format and   
+* multiplications yield a 2.30 result. The 2.30 intermediate results are   
+* accumulated in a 64-bit accumulator in 34.30 format.    
+* There is no risk of internal overflow with this approach and the full   
+* precision of intermediate multiplications is preserved. After all additions   
+* have been performed, the accumulator is truncated to 34.15 format by   
+* discarding low 15 bits. Lastly, the accumulator is saturated to yield a   
+* result in 1.15 format.   
+*   
+* \par  
+* 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.   
+*   
+ */
+
+void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
+  q15_t mu = S->mu;                              /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q31_t energy;                                  /* Energy of the input */
+  q63_t acc;                                     /* Accumulator */
+  q15_t e = 0, d = 0;                            /* error, reference data sample */
+  q15_t w = 0, in;                               /* weight factor and state */
+  q15_t x0;                                      /* temporary variable to hold input sample */
+  uint32_t shift = (uint32_t) S->postShift + 1u; /* Shift to be applied to the output */
+  q15_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
+  q15_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
+  q31_t coef;                                    /* Teporary variable for coefficient */
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= (((q31_t) x0 * (x0)) >> 15);
+    energy += (((q31_t) in * (in)) >> 15);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Perform the multiply-accumulate */
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (((q31_t) * px++ * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.15 format */
+    acc = __SSAT((acc >> (16u - shift)), 16u);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q15_t) acc;
+    *pErr++ = e;
+
+    /* Calculation of 1/energy */
+    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+                              &oneByEnergy, S->recipTable);
+
+    /* Calculation of e * mu value */
+    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+    /* Calculation of (e * mu) * (1/energy) value */
+    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+    /* Weighting factor for the normalized version */
+    w = (q15_t) __SSAT((q31_t) acc, 16);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q15_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= (((q31_t) x0 * (x0)) >> 15);
+    energy += (((q31_t) in * (in)) >> 15);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (((q31_t) * px++ * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.15 format */
+    acc = __SSAT((acc >> (16u - shift)), 16u);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q15_t) acc;
+    *pErr++ = e;
+
+    /* Calculation of 1/energy */
+    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+                              &oneByEnergy, S->recipTable);
+
+    /* Calculation of e * mu value */
+    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+    /* Calculation of (e * mu) * (1/energy) value */
+    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+    /* Weighting factor for the normalized version */
+    w = (q15_t) __SSAT((q31_t) acc, 16);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q15_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the       
+     satrt of the state buffer. This prepares the state buffer for the       
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* copy (numTaps - 1u) data */
+  tapCnt = (numTaps - 1u);
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**   
+   * @} end of LMS_NORM group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
new file mode 100644
index 0000000..05e7329
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
@@ -0,0 +1,404 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_norm_q31.c   
+*   
+* Description:	Processing function for the Q31 NLMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+/**   
+* @brief Processing function for Q31 normalized LMS filter.   
+* @param[in] *S points to an instance of the Q31 normalized LMS filter structure.   
+* @param[in] *pSrc points to the block of input data.   
+* @param[in] *pRef points to the block of reference data.   
+* @param[out] *pOut points to the block of output data.   
+* @param[out] *pErr points to the block of error data.   
+* @param[in] blockSize number of samples to process.   
+* @return none.   
+*   
+* Scaling and Overflow Behavior:    
+* \par    
+* The function is implemented using an internal 64-bit accumulator.    
+* The accumulator has a 2.62 format and maintains full precision of the intermediate  
+* multiplication results but provides only a single guard bit.    
+* Thus, if the accumulator result overflows it wraps around rather than clip.    
+* In order to avoid overflows completely the input signal must be scaled down by   
+* log2(numTaps) bits. The reference signal should not be scaled down.    
+* After all multiply-accumulates are performed, the 2.62 accumulator is shifted   
+* and saturated to 1.31 format to yield the final result.    
+* The output signal and error signal are in 1.31 format.    
+*   
+* \par   
+* 	In this filter, filter coefficients are updated for each sample and the   
+* updation of filter cofficients are saturted.   
+*    
+*/
+
+void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
+  q31_t mu = S->mu;                              /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t energy;                                  /* Energy of the input */
+  q63_t acc;                                     /* Accumulator */
+  q31_t e = 0, d = 0;                            /* error, reference data sample */
+  q31_t w = 0, in;                               /* weight factor and state */
+  q31_t x0;                                      /* temporary variable to hold input sample */
+  uint32_t shift = 32u - ((uint32_t) S->postShift + 1u);        /* Shift to be applied to the output */
+  q31_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
+  q31_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
+  q31_t coef;                                    /* Temporary variable for coef */
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy = (q31_t) ((((q63_t) energy << 32) -
+                       (((q63_t) x0 * x0) << 1)) >> 32);
+    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    acc = (q31_t) (acc >> shift);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q31_t) acc;
+    *pErr++ = e;
+
+    /* Calculates the reciprocal of energy */
+    postShift = arm_recip_q31(energy + DELTA_Q31,
+                              &oneByEnergy, &S->recipTable[0]);
+
+    /* Calculation of product of (e * mu) */
+    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Weighting factor for the normalized version */
+    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q31_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy =
+      (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);
+    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    acc = (q31_t) (acc >> shift);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q31_t) acc;
+    *pErr++ = e;
+
+    /* Calculates the reciprocal of energy */
+    postShift =
+      arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);
+
+    /* Calculation of product of (e * mu) */
+    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Weighting factor for the normalized version */
+    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q31_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     start of the state buffer. This prepares the state buffer for the       
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of LMS_NORM group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
new file mode 100644
index 0000000..eb62f1f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
@@ -0,0 +1,331 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_q15.c   
+*   
+* Description:	Processing function for the Q15 LMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+ /**   
+ * @brief Processing function for Q15 LMS filter.   
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[in] *pRef points to the block of reference data.   
+ * @param[out] *pOut points to the block of output data.   
+ * @param[out] *pErr points to the block of error data.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * \par Scaling and Overflow Behavior:   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ *  
+ * \par  
+ * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.  
+ *   
+ */
+
+void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t mu = S->mu;                              /* Adaptive factor */
+  q15_t *px;                                     /* Temporary pointer for state */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t acc;                                     /* Accumulator */
+  q15_t e = 0;                                   /* error of data sample */
+  q15_t alpha;                                   /* Intermediate constant for taps update */
+  uint32_t shift = S->postShift + 1u;            /* Shift to be applied to the output */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t coef;                                    /* Teporary variable for coefficient */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initializing blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2u;
+
+    while(tapCnt > 0u)
+    {
+      /* acc +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      /* Perform the multiply-accumulate */
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT((acc >> (16 - shift)), 16);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q15_t) acc;
+
+    *pErr++ = (q15_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+    /* Initialize state pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2u;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (q63_t) ((q31_t) (*px++) * (*pb++));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT((acc >> (16 - shift)), 16);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q15_t) acc;
+
+    *pErr++ = (q15_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+    /* Initialize pState pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb++ += (q15_t) (((q31_t) alpha * (*px++)) >> 15);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the       
+     start of the state buffer. This prepares the state buffer for the  
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of LMS group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
new file mode 100644
index 0000000..dced452
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
@@ -0,0 +1,347 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_q31.c   
+*   
+* Description:	Processing function for the Q31 LMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+ /**   
+ * @brief Processing function for Q31 LMS filter.   
+ * @param[in]  *S points to an instance of the Q15 LMS filter structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[in]  *pRef points to the block of reference data.   
+ * @param[out] *pOut points to the block of output data.   
+ * @param[out] *pErr points to the block of error data.   
+ * @param[in]  blockSize number of samples to process.   
+ * @return     none.   
+ *   
+ * \par Scaling and Overflow Behavior:    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate   
+ * multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clips.    
+ * In order to avoid overflows completely the input signal must be scaled down by   
+ * log2(numTaps) bits.    
+ * The reference signal should not be scaled down.    
+ * After all multiply-accumulates are performed, the 2.62 accumulator is shifted   
+ * and saturated to 1.31 format to yield the final result.    
+ * The output signal and error signal are in 1.31 format.    
+ *   
+ * \par   
+ * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.   
+ */
+
+void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t mu = S->mu;                              /* Adaptive factor */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t acc;                                     /* Accumulator */
+  q31_t e = 0;                                   /* error of data sample */
+  q31_t alpha;                                   /* Intermediate constant for taps update */
+  uint8_t shift = (uint8_t) (32u - (S->postShift + 1u));        /* Shift to be applied to the output */
+  q31_t coef;                                    /* Temporary variable for coef */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initializing blkCnt with blockSize */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* acc +=  b[N] * x[n-N] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-1] * x[n-N-1] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-2] * x[n-N-2] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-3] * x[n-N-3] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Store the result from accumulator into the destination buffer. */
+    acc = (q31_t) (acc >> shift);
+
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q31_t) acc;
+
+    *pErr++ = (q31_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Initialize state pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Store the result from accumulator into the destination buffer. */
+    acc = (q31_t) (acc >> shift);
+
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q31_t) acc;
+
+    *pErr++ = (q31_t) e;
+
+    /* Weighting factor for the LMS version */
+    alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Initialize pState pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb += (coef << 1u);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     start of the state buffer. This prepares the state buffer for the  
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of LMS group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvopt
new file mode 100644
index 0000000..ff9c4eb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvopt
@@ -0,0 +1,3582 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    DSP_Lib CM0 LE
+    0x3
+    ARM-GNU
+    
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+        SARMCM3.DLL
+        
+        DARMCM1.DLL
+        -pCM0
+        SARMCM3.DLL
+        
+        TARMCM1.DLL
+        -pCM0
+      
+      
+        1
+        0
+        1
+        1
+        1
+        1
+        1
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+        -1
+        
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvproj
new file mode 100644
index 0000000..3d89fa1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvproj
@@ -0,0 +1,1550 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

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+            
+            
+              arm_dot_prod_q7.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q7.c
+            
+            
+              arm_dot_prod_q15.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q15.c
+            
+            
+              arm_dot_prod_q31.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q31.c
+            
+            
+              arm_mult_f32.c
+              1
+              ../BasicMathFunctions/arm_mult_f32.c
+            
+            
+              arm_mult_q7.c
+              1
+              ../BasicMathFunctions/arm_mult_q7.c
+            
+            
+              arm_mult_q15.c
+              1
+              ../BasicMathFunctions/arm_mult_q15.c
+            
+            
+              arm_mult_q31.c
+              1
+              ../BasicMathFunctions/arm_mult_q31.c
+            
+            
+              arm_negate_f32.c
+              1
+              ../BasicMathFunctions/arm_negate_f32.c
+            
+            
+              arm_negate_q7.c
+              1
+              ../BasicMathFunctions/arm_negate_q7.c
+            
+            
+              arm_negate_q15.c
+              1
+              ../BasicMathFunctions/arm_negate_q15.c
+            
+            
+              arm_negate_q31.c
+              1
+              ../BasicMathFunctions/arm_negate_q31.c
+            
+            
+              arm_offset_f32.c
+              1
+              ../BasicMathFunctions/arm_offset_f32.c
+            
+            
+              arm_offset_q7.c
+              1
+              ../BasicMathFunctions/arm_offset_q7.c
+            
+            
+              arm_offset_q15.c
+              1
+              ../BasicMathFunctions/arm_offset_q15.c
+            
+            
+              arm_offset_q31.c
+              1
+              ../BasicMathFunctions/arm_offset_q31.c
+            
+            
+              arm_scale_f32.c
+              1
+              ../BasicMathFunctions/arm_scale_f32.c
+            
+            
+              arm_scale_q7.c
+              1
+              ../BasicMathFunctions/arm_scale_q7.c
+            
+            
+              arm_scale_q15.c
+              1
+              ../BasicMathFunctions/arm_scale_q15.c
+            
+            
+              arm_scale_q31.c
+              1
+              ../BasicMathFunctions/arm_scale_q31.c
+            
+            
+              arm_shift_q7.c
+              1
+              ../BasicMathFunctions/arm_shift_q7.c
+            
+            
+              arm_shift_q15.c
+              1
+              ../BasicMathFunctions/arm_shift_q15.c
+            
+            
+              arm_shift_q31.c
+              1
+              ../BasicMathFunctions/arm_shift_q31.c
+            
+            
+              arm_sub_f32.c
+              1
+              ../BasicMathFunctions/arm_sub_f32.c
+            
+            
+              arm_sub_q7.c
+              1
+              ../BasicMathFunctions/arm_sub_q7.c
+            
+            
+              arm_sub_q15.c
+              1
+              ../BasicMathFunctions/arm_sub_q15.c
+            
+            
+              arm_sub_q31.c
+              1
+              ../BasicMathFunctions/arm_sub_q31.c
+            
+          
+        
+        
+          FastMathFunctions
+          
+            
+              arm_cos_f32.c
+              1
+              ../FastMathFunctions/arm_cos_f32.c
+            
+            
+              arm_cos_q15.c
+              1
+              ../FastMathFunctions/arm_cos_q15.c
+            
+            
+              arm_cos_q31.c
+              1
+              ../FastMathFunctions/arm_cos_q31.c
+            
+            
+              arm_sin_f32.c
+              1
+              ../FastMathFunctions/arm_sin_f32.c
+            
+            
+              arm_sin_q15.c
+              1
+              ../FastMathFunctions/arm_sin_q15.c
+            
+            
+              arm_sin_q31.c
+              1
+              ../FastMathFunctions/arm_sin_q31.c
+            
+            
+              arm_sqrt_q15.c
+              1
+              ../FastMathFunctions/arm_sqrt_q15.c
+            
+            
+              arm_sqrt_q31.c
+              1
+              ../FastMathFunctions/arm_sqrt_q31.c
+            
+          
+        
+        
+          ComplexMathFunctions
+          
+            
+              arm_cmplx_conj_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_f32.c
+            
+            
+              arm_cmplx_conj_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q15.c
+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+            
+            
+              arm_cmplx_dot_prod_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q15.c
+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvopt
new file mode 100644
index 0000000..aac0be6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvopt
@@ -0,0 +1,3582 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvproj
new file mode 100644
index 0000000..936116c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvproj
@@ -0,0 +1,1550 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

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+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ../StatisticsFunctions/arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ../StatisticsFunctions/arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ../StatisticsFunctions/arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ../StatisticsFunctions/arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ../StatisticsFunctions/arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ../StatisticsFunctions/arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ../StatisticsFunctions/arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ../StatisticsFunctions/arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ../StatisticsFunctions/arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ../StatisticsFunctions/arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ../StatisticsFunctions/arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ../StatisticsFunctions/arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ../StatisticsFunctions/arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ../StatisticsFunctions/arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ../StatisticsFunctions/arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              ../StatisticsFunctions/arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ../StatisticsFunctions/arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ../StatisticsFunctions/arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ../StatisticsFunctions/arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              ../StatisticsFunctions/arm_var_q31.c
+            
+          
+        
+        
+          SupportFunctions
+          
+            
+              arm_copy_f32.c
+              1
+              ../SupportFunctions/arm_copy_f32.c
+            
+            
+              arm_copy_q7.c
+              1
+              ../SupportFunctions/arm_copy_q7.c
+            
+            
+              arm_copy_q15.c
+              1
+              ../SupportFunctions/arm_copy_q15.c
+            
+            
+              arm_copy_q31.c
+              1
+              ../SupportFunctions/arm_copy_q31.c
+            
+            
+              arm_fill_f32.c
+              1
+              ../SupportFunctions/arm_fill_f32.c
+            
+            
+              arm_fill_q7.c
+              1
+              ../SupportFunctions/arm_fill_q7.c
+            
+            
+              arm_fill_q15.c
+              1
+              ../SupportFunctions/arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              ../SupportFunctions/arm_fill_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              ../SupportFunctions/arm_float_to_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              ../SupportFunctions/arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              ../SupportFunctions/arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
+              ../SupportFunctions/arm_q7_to_float.c
+            
+            
+              arm_q7_to_q15.c
+              1
+              ../SupportFunctions/arm_q7_to_q15.c
+            
+            
+              arm_q7_to_q31.c
+              1
+              ../SupportFunctions/arm_q7_to_q31.c
+            
+            
+              arm_q15_to_float.c
+              1
+              ../SupportFunctions/arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              ../SupportFunctions/arm_q15_to_q7.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              ../SupportFunctions/arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ../SupportFunctions/arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ../SupportFunctions/arm_q31_to_q7.c
+            
+            
+              arm_q31_to_q15.c
+              1
+              ../SupportFunctions/arm_q31_to_q15.c
+            
+          
+        
+        
+          CommonTables
+          
+            
+              arm_common_tables.c
+              1
+              ../CommonTables/arm_common_tables.c
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvopt b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvopt
new file mode 100644
index 0000000..b0b7086
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvopt
@@ -0,0 +1,3711 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

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+        -1
+        
+        
+        
+        
+        .\Simulator.ini
+        
+        
+        
+        
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+        
+      
+      
+        0
+        0
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvproj b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvproj
new file mode 100644
index 0000000..6e5a240
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvproj
@@ -0,0 +1,3089 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

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+              -mcpu=cortex-m4 -fno-strict-aliasing -ffunction-sections
+              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING
+              
+              ..\..\..\Include
+            
+          
+          
+            0
+            1
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            1
+            0
+            1
+            
+            
+            
+            
+            
+            -mcpu=cortex-m4 -Wl,--gc-sections
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+          
+        
+      
+      
+        
+          BasicMathFunctions
+          
+            
+              arm_abs_f32.c
+              1
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+            
+              arm_abs_q7.c
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+              ../BasicMathFunctions/arm_abs_q7.c
+            
+            
+              arm_abs_q15.c
+              1
+              ../BasicMathFunctions/arm_abs_q15.c
+            
+            
+              arm_abs_q31.c
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+            
+            
+              arm_add_f32.c
+              1
+              ../BasicMathFunctions/arm_add_f32.c
+            
+            
+              arm_add_q7.c
+              1
+              ../BasicMathFunctions/arm_add_q7.c
+            
+            
+              arm_add_q15.c
+              1
+              ../BasicMathFunctions/arm_add_q15.c
+            
+            
+              arm_add_q31.c
+              1
+              ../BasicMathFunctions/arm_add_q31.c
+            
+            
+              arm_dot_prod_f32.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_f32.c
+            
+            
+              arm_dot_prod_q7.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q7.c
+            
+            
+              arm_dot_prod_q15.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q15.c
+            
+            
+              arm_dot_prod_q31.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q31.c
+            
+            
+              arm_mult_f32.c
+              1
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+            
+            
+              arm_mult_q7.c
+              1
+              ../BasicMathFunctions/arm_mult_q7.c
+            
+            
+              arm_mult_q15.c
+              1
+              ../BasicMathFunctions/arm_mult_q15.c
+            
+            
+              arm_mult_q31.c
+              1
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+            
+            
+              arm_negate_f32.c
+              1
+              ../BasicMathFunctions/arm_negate_f32.c
+            
+            
+              arm_negate_q7.c
+              1
+              ../BasicMathFunctions/arm_negate_q7.c
+            
+            
+              arm_negate_q15.c
+              1
+              ../BasicMathFunctions/arm_negate_q15.c
+            
+            
+              arm_negate_q31.c
+              1
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+            
+              arm_offset_f32.c
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+            
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+            
+            
+              arm_offset_q15.c
+              1
+              ../BasicMathFunctions/arm_offset_q15.c
+            
+            
+              arm_offset_q31.c
+              1
+              ../BasicMathFunctions/arm_offset_q31.c
+            
+            
+              arm_scale_f32.c
+              1
+              ../BasicMathFunctions/arm_scale_f32.c
+            
+            
+              arm_scale_q7.c
+              1
+              ../BasicMathFunctions/arm_scale_q7.c
+            
+            
+              arm_scale_q15.c
+              1
+              ../BasicMathFunctions/arm_scale_q15.c
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+            
+              arm_scale_q31.c
+              1
+              ../BasicMathFunctions/arm_scale_q31.c
+            
+            
+              arm_shift_q7.c
+              1
+              ../BasicMathFunctions/arm_shift_q7.c
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+            
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+              1
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+              1
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+            
+            
+              arm_sub_f32.c
+              1
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+            
+            
+              arm_sub_q7.c
+              1
+              ../BasicMathFunctions/arm_sub_q7.c
+            
+            
+              arm_sub_q15.c
+              1
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+            
+            
+              arm_sub_q31.c
+              1
+              ../BasicMathFunctions/arm_sub_q31.c
+            
+          
+        
+        
+          FastMathFunctions
+          
+            
+              arm_cos_f32.c
+              1
+              ../FastMathFunctions/arm_cos_f32.c
+            
+            
+              arm_cos_q15.c
+              1
+              ../FastMathFunctions/arm_cos_q15.c
+            
+            
+              arm_cos_q31.c
+              1
+              ../FastMathFunctions/arm_cos_q31.c
+            
+            
+              arm_sin_f32.c
+              1
+              ../FastMathFunctions/arm_sin_f32.c
+            
+            
+              arm_sin_q15.c
+              1
+              ../FastMathFunctions/arm_sin_q15.c
+            
+            
+              arm_sin_q31.c
+              1
+              ../FastMathFunctions/arm_sin_q31.c
+            
+            
+              arm_sqrt_q15.c
+              1
+              ../FastMathFunctions/arm_sqrt_q15.c
+            
+            
+              arm_sqrt_q31.c
+              1
+              ../FastMathFunctions/arm_sqrt_q31.c
+            
+          
+        
+        
+          ComplexMathFunctions
+          
+            
+              arm_cmplx_conj_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_f32.c
+            
+            
+              arm_cmplx_conj_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q15.c
+            
+            
+              arm_cmplx_conj_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_conj_q31.c
+            
+            
+              arm_cmplx_dot_prod_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+            
+            
+              arm_cmplx_dot_prod_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+            
+            
+              arm_cmplx_dot_prod_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+            
+            
+              arm_cmplx_mag_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_f32.c
+            
+            
+              arm_cmplx_mag_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q15.c
+            
+            
+              arm_cmplx_mag_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_q31.c
+            
+            
+              arm_cmplx_mag_squared_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+            
+            
+              arm_cmplx_mag_squared_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+            
+            
+              arm_cmplx_mag_squared_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+            
+            
+              arm_cmplx_mult_cmplx_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+            
+            
+              arm_cmplx_mult_cmplx_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+            
+            
+              arm_cmplx_mult_cmplx_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+            
+            
+              arm_cmplx_mult_real_f32.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+            
+            
+              arm_cmplx_mult_real_q15.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+            
+            
+              arm_cmplx_mult_real_q31.c
+              1
+              ../ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+            
+          
+        
+        
+          FilteringFunctions
+          
+            
+              arm_biquad_cascade_df1_32x64_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
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+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
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+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
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+              1
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+              1
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+            
+            
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+            
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+              arm_float_to_q31.c
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+            
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+            
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+          
+            
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+              1
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+            
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+              1
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+            
+              arm_abs_q15.c
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+            
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+              1
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+            
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+              1
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+            
+            
+              arm_add_q7.c
+              1
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+            
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+              1
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+            
+            
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+              1
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+            
+            
+              arm_dot_prod_f32.c
+              1
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+            
+            
+              arm_dot_prod_q7.c
+              1
+              ../BasicMathFunctions/arm_dot_prod_q7.c
+            
+            
+              arm_dot_prod_q15.c
+              1
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+            
+              arm_dot_prod_q31.c
+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
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+              1
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+            
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+              1
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+              1
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+            
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+              1
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+              1
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+            
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+              1
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+            
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+              1
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+            
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+            
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+              1
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+            
+            
+              arm_offset_q31.c
+              1
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+            
+            
+              arm_scale_f32.c
+              1
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+            
+            
+              arm_scale_q7.c
+              1
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+            
+            
+              arm_scale_q15.c
+              1
+              ../BasicMathFunctions/arm_scale_q15.c
+            
+            
+              arm_scale_q31.c
+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
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+          
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+              1
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+            
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+              1
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+            
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+          
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+              1
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+            
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+              1
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+            
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+              1
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+            
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+              1
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+            
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+              1
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+            
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+              1
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+            
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+              1
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+            
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+              1
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+            
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+              1
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+            
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+              1
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+            
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+            
+              arm_biquad_cascade_df1_32x64_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+            
+            
+              arm_biquad_cascade_df1_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_f32.c
+            
+            
+              arm_biquad_cascade_df1_fast_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+            
+            
+              arm_biquad_cascade_df1_fast_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+            
+            
+              arm_biquad_cascade_df1_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+            
+            
+              arm_biquad_cascade_df1_init_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+            
+            
+              arm_biquad_cascade_df1_init_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+            
+            
+              arm_biquad_cascade_df1_q15.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q15.c
+            
+            
+              arm_biquad_cascade_df1_q31.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df1_q31.c
+            
+            
+              arm_biquad_cascade_df2T_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+            
+            
+              arm_biquad_cascade_df2T_init_f32.c
+              1
+              ../FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+            
+            
+              arm_conv_f32.c
+              1
+              ../FilteringFunctions/arm_conv_f32.c
+            
+            
+              arm_conv_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q15.c
+            
+            
+              arm_conv_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_fast_q31.c
+            
+            
+              arm_conv_partial_f32.c
+              1
+              ../FilteringFunctions/arm_conv_partial_f32.c
+            
+            
+              arm_conv_partial_fast_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q15.c
+            
+            
+              arm_conv_partial_fast_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_fast_q31.c
+            
+            
+              arm_conv_partial_q7.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q7.c
+            
+            
+              arm_conv_partial_q15.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q15.c
+            
+            
+              arm_conv_partial_q31.c
+              1
+              ../FilteringFunctions/arm_conv_partial_q31.c
+            
+            
+              arm_conv_q7.c
+              1
+              ../FilteringFunctions/arm_conv_q7.c
+            
+            
+              arm_conv_q15.c
+              1
+              ../FilteringFunctions/arm_conv_q15.c
+            
+            
+              arm_conv_q31.c
+              1
+              ../FilteringFunctions/arm_conv_q31.c
+            
+            
+              arm_correlate_f32.c
+              1
+              ../FilteringFunctions/arm_correlate_f32.c
+            
+            
+              arm_correlate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q15.c
+            
+            
+              arm_correlate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_fast_q31.c
+            
+            
+              arm_correlate_q7.c
+              1
+              ../FilteringFunctions/arm_correlate_q7.c
+            
+            
+              arm_correlate_q15.c
+              1
+              ../FilteringFunctions/arm_correlate_q15.c
+            
+            
+              arm_correlate_q31.c
+              1
+              ../FilteringFunctions/arm_correlate_q31.c
+            
+            
+              arm_fir_decimate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_f32.c
+            
+            
+              arm_fir_decimate_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q15.c
+            
+            
+              arm_fir_decimate_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_fast_q31.c
+            
+            
+              arm_fir_decimate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_f32.c
+            
+            
+              arm_fir_decimate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q15.c
+            
+            
+              arm_fir_decimate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_init_q31.c
+            
+            
+              arm_fir_decimate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q15.c
+            
+            
+              arm_fir_decimate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_decimate_q31.c
+            
+            
+              arm_fir_f32.c
+              1
+              ../FilteringFunctions/arm_fir_f32.c
+            
+            
+              arm_fir_fast_q15.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q15.c
+            
+            
+              arm_fir_fast_q31.c
+              1
+              ../FilteringFunctions/arm_fir_fast_q31.c
+            
+            
+              arm_fir_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_init_f32.c
+            
+            
+              arm_fir_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_init_q7.c
+            
+            
+              arm_fir_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_init_q15.c
+            
+            
+              arm_fir_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_init_q31.c
+            
+            
+              arm_fir_interpolate_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_f32.c
+            
+            
+              arm_fir_interpolate_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
+            
+            
+              arm_fir_interpolate_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
+            
+            
+              arm_fir_interpolate_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
+            
+            
+              arm_fir_interpolate_q15.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q15.c
+            
+            
+              arm_fir_interpolate_q31.c
+              1
+              ../FilteringFunctions/arm_fir_interpolate_q31.c
+            
+            
+              arm_fir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_f32.c
+            
+            
+              arm_fir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_f32.c
+            
+            
+              arm_fir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q15.c
+            
+            
+              arm_fir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_init_q31.c
+            
+            
+              arm_fir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q15.c
+            
+            
+              arm_fir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_fir_lattice_q31.c
+            
+            
+              arm_fir_q7.c
+              1
+              ../FilteringFunctions/arm_fir_q7.c
+            
+            
+              arm_fir_q15.c
+              1
+              ../FilteringFunctions/arm_fir_q15.c
+            
+            
+              arm_fir_q31.c
+              1
+              ../FilteringFunctions/arm_fir_q31.c
+            
+            
+              arm_fir_sparse_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_f32.c
+            
+            
+              arm_fir_sparse_init_f32.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_f32.c
+            
+            
+              arm_fir_sparse_init_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q7.c
+            
+            
+              arm_fir_sparse_init_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q15.c
+            
+            
+              arm_fir_sparse_init_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_init_q31.c
+            
+            
+              arm_fir_sparse_q7.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q7.c
+            
+            
+              arm_fir_sparse_q15.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q15.c
+            
+            
+              arm_fir_sparse_q31.c
+              1
+              ../FilteringFunctions/arm_fir_sparse_q31.c
+            
+            
+              arm_iir_lattice_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_f32.c
+            
+            
+              arm_iir_lattice_init_f32.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_f32.c
+            
+            
+              arm_iir_lattice_init_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q15.c
+            
+            
+              arm_iir_lattice_init_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_init_q31.c
+            
+            
+              arm_iir_lattice_q15.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q15.c
+            
+            
+              arm_iir_lattice_q31.c
+              1
+              ../FilteringFunctions/arm_iir_lattice_q31.c
+            
+            
+              arm_lms_f32.c
+              1
+              ../FilteringFunctions/arm_lms_f32.c
+            
+            
+              arm_lms_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_init_f32.c
+            
+            
+              arm_lms_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_init_q15.c
+            
+            
+              arm_lms_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_init_q31.c
+            
+            
+              arm_lms_norm_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_f32.c
+            
+            
+              arm_lms_norm_init_f32.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_f32.c
+            
+            
+              arm_lms_norm_init_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q15.c
+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              ../FilteringFunctions/arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              ../FilteringFunctions/arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              ../FilteringFunctions/arm_lms_q31.c
+            
+          
+        
+        
+          MatrixFunctions
+          
+            
+              arm_mat_add_f32.c
+              1
+              ../MatrixFunctions/arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              ../MatrixFunctions/arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              ../MatrixFunctions/arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              ../MatrixFunctions/arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              ../MatrixFunctions/arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              ../MatrixFunctions/arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              ../MatrixFunctions/arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              ../MatrixFunctions/arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              ../MatrixFunctions/arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              ../MatrixFunctions/arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              ../MatrixFunctions/arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              ../MatrixFunctions/arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              ../MatrixFunctions/arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              ../MatrixFunctions/arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              ../MatrixFunctions/arm_mat_trans_q31.c
+            
+          
+        
+        
+          TransformFunctions
+          
+            
+              arm_cfft_radix4_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              ../TransformFunctions/arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              ../TransformFunctions/arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              ../TransformFunctions/arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              ../TransformFunctions/arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              ../TransformFunctions/arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              ../TransformFunctions/arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              ../TransformFunctions/arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              ../TransformFunctions/arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              ../TransformFunctions/arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              ../TransformFunctions/arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              ../TransformFunctions/arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              ../TransformFunctions/arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              ../TransformFunctions/arm_rfft_q31.c
+            
+          
+        
+        
+          ControllerFunctions
+          
+            
+              arm_pid_init_f32.c
+              1
+              ../ControllerFunctions/arm_pid_init_f32.c
+            
+            
+              arm_pid_init_q15.c
+              1
+              ../ControllerFunctions/arm_pid_init_q15.c
+            
+            
+              arm_pid_init_q31.c
+              1
+              ../ControllerFunctions/arm_pid_init_q31.c
+            
+            
+              arm_pid_reset_f32.c
+              1
+              ../ControllerFunctions/arm_pid_reset_f32.c
+            
+            
+              arm_pid_reset_q15.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q15.c
+            
+            
+              arm_pid_reset_q31.c
+              1
+              ../ControllerFunctions/arm_pid_reset_q31.c
+            
+            
+              arm_sin_cos_f32.c
+              1
+              ../ControllerFunctions/arm_sin_cos_f32.c
+            
+            
+              arm_sin_cos_q31.c
+              1
+              ../ControllerFunctions/arm_sin_cos_q31.c
+            
+          
+        
+        
+          StatisticsFunctions
+          
+            
+              arm_max_f32.c
+              1
+              ../StatisticsFunctions/arm_max_f32.c
+            
+            
+              arm_max_q7.c
+              1
+              ../StatisticsFunctions/arm_max_q7.c
+            
+            
+              arm_max_q15.c
+              1
+              ../StatisticsFunctions/arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              ../StatisticsFunctions/arm_max_q31.c
+            
+            
+              arm_mean_f32.c
+              1
+              ../StatisticsFunctions/arm_mean_f32.c
+            
+            
+              arm_mean_q7.c
+              1
+              ../StatisticsFunctions/arm_mean_q7.c
+            
+            
+              arm_mean_q15.c
+              1
+              ../StatisticsFunctions/arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              ../StatisticsFunctions/arm_mean_q31.c
+            
+            
+              arm_min_f32.c
+              1
+              ../StatisticsFunctions/arm_min_f32.c
+            
+            
+              arm_min_q7.c
+              1
+              ../StatisticsFunctions/arm_min_q7.c
+            
+            
+              arm_min_q15.c
+              1
+              ../StatisticsFunctions/arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              ../StatisticsFunctions/arm_min_q31.c
+            
+            
+              arm_power_f32.c
+              1
+              ../StatisticsFunctions/arm_power_f32.c
+            
+            
+              arm_power_q7.c
+              1
+              ../StatisticsFunctions/arm_power_q7.c
+            
+            
+              arm_power_q15.c
+              1
+              ../StatisticsFunctions/arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              ../StatisticsFunctions/arm_power_q31.c
+            
+            
+              arm_rms_f32.c
+              1
+              ../StatisticsFunctions/arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              ../StatisticsFunctions/arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              ../StatisticsFunctions/arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              ../StatisticsFunctions/arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              ../StatisticsFunctions/arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              ../StatisticsFunctions/arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              ../StatisticsFunctions/arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              ../StatisticsFunctions/arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              ../StatisticsFunctions/arm_var_q31.c
+            
+          
+        
+        
+          SupportFunctions
+          
+            
+              arm_copy_f32.c
+              1
+              ../SupportFunctions/arm_copy_f32.c
+            
+            
+              arm_copy_q7.c
+              1
+              ../SupportFunctions/arm_copy_q7.c
+            
+            
+              arm_copy_q15.c
+              1
+              ../SupportFunctions/arm_copy_q15.c
+            
+            
+              arm_copy_q31.c
+              1
+              ../SupportFunctions/arm_copy_q31.c
+            
+            
+              arm_fill_f32.c
+              1
+              ../SupportFunctions/arm_fill_f32.c
+            
+            
+              arm_fill_q7.c
+              1
+              ../SupportFunctions/arm_fill_q7.c
+            
+            
+              arm_fill_q15.c
+              1
+              ../SupportFunctions/arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              ../SupportFunctions/arm_fill_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              ../SupportFunctions/arm_float_to_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              ../SupportFunctions/arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              ../SupportFunctions/arm_float_to_q31.c
+            
+            
+              arm_q7_to_float.c
+              1
+              ../SupportFunctions/arm_q7_to_float.c
+            
+            
+              arm_q7_to_q15.c
+              1
+              ../SupportFunctions/arm_q7_to_q15.c
+            
+            
+              arm_q7_to_q31.c
+              1
+              ../SupportFunctions/arm_q7_to_q31.c
+            
+            
+              arm_q15_to_float.c
+              1
+              ../SupportFunctions/arm_q15_to_float.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              ../SupportFunctions/arm_q15_to_q7.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              ../SupportFunctions/arm_q15_to_q31.c
+            
+            
+              arm_q31_to_float.c
+              1
+              ../SupportFunctions/arm_q31_to_float.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              ../SupportFunctions/arm_q31_to_q7.c
+            
+            
+              arm_q31_to_q15.c
+              1
+              ../SupportFunctions/arm_q31_to_q15.c
+            
+          
+        
+        
+          CommonTables
+          
+            
+              arm_common_tables.c
+              1
+              ../CommonTables/arm_common_tables.c
+            
+          
+        
+      
+    
+  
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexMx_math_Build.bat b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexMx_math_Build.bat
new file mode 100644
index 0000000..a194c70
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/GCC/arm_cortexMx_math_Build.bat
@@ -0,0 +1,10 @@
+
+SET TMP=C:\Temp
+SET TEMP=C:\Temp
+
+SET UVEXE=C:\Keil\UV4\UV4.EXE
+
+%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 LE" -o"DSP_Lib CM0 LE.txt"
+%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 LE" -o"DSP_Lib CM3 LE.txt"
+%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE" -o"DSP_Lib CM4 LE.txt"
+%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE FPU" -o"DSP_Lib CM4 LE FPU.txt"
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
new file mode 100644
index 0000000..23348a1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_add_f32.c   
+*   
+* Description:	Floating-point matrix addition   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixAdd Matrix Addition   
+ *   
+ * Adds two matrices.   
+ * \image html MatrixAddition.gif "Addition of two 3 x 3 matrices"   
+ *   
+ * The functions check to make sure that   
+ * pSrcA, pSrcB, and pDst have the same   
+ * number of rows and columns.   
+ */
+
+/**   
+ * @addtogroup MatrixAdd   
+ * @{   
+ */
+
+
+/**   
+ * @brief Floating-point matrix addition.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer   */
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) + (*pIn2++);
+      *pOut++ = (*pIn1++) + (*pIn2++);
+      *pOut++ = (*pIn1++) + (*pIn2++);
+      *pOut++ = (*pIn1++) + (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) + (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixAdd group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
new file mode 100644
index 0000000..b96feb4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
@@ -0,0 +1,158 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_add_q15.c   
+*   
+* Description:	Q15 matrix addition   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixAdd   
+ * @{   
+ */
+
+/**   
+ * @brief Q15 matrix addition.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ */
+
+arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A  */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint16_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix addition  */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint16_t) (pSrcA->numRows * pSrcA->numCols);
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop unrolling */
+    blkCnt = (uint32_t) numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = (uint32_t) numSamples % 0x4u;
+
+    /* q15 pointers of input and output are initialized */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = (uint32_t) numSamples;
+
+
+    /* q15 pointers of input and output are initialized */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ + *pInB++), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixAdd group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
new file mode 100644
index 0000000..af4ada0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_add_q31.c   
+*   
+* Description:	Q31 matrix addition   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixAdd   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix addition.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.   
+ */
+
+arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      *pOut++ = clip_q63_to_q31(((q63_t) (*pIn1++)) + (*pIn2++));
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixAdd group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
new file mode 100644
index 0000000..e27a685
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
@@ -0,0 +1,83 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_init_f32.c   
+*   
+* Description:	Floating-point matrix initialization.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixInit Matrix Initialization   
+ *   
+ * Initializes the underlying matrix data structure.   
+ * The functions set the numRows,   
+ * numCols, and pData fields   
+ * of the matrix data structure.   
+ */
+
+/**   
+ * @addtogroup MatrixInit   
+ * @{   
+ */
+
+/**   
+   * @brief  Floating-point matrix initialization.   
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.   
+   * @param[in]     nRows          number of rows in the matrix.   
+   * @param[in]     nColumns       number of columns in the matrix.   
+   * @param[in]     *pData	   points to the matrix data array.   
+   * @return        none   
+   */
+
+void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**   
+ * @} end of MatrixInit group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
new file mode 100644
index 0000000..addc2b0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
@@ -0,0 +1,75 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_init_q15.c   
+*   
+* Description:	Q15 matrix initialization.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixInit   
+ * @{   
+ */
+
+  /**   
+   * @brief  Q15 matrix initialization.   
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.   
+   * @param[in]     nRows          number of rows in the matrix.   
+   * @param[in]     nColumns       number of columns in the matrix.   
+   * @param[in]     *pData	   points to the matrix data array.   
+   * @return        none   
+   */
+
+void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**   
+ * @} end of MatrixInit group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
new file mode 100644
index 0000000..7e11659
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_init_q31.c   
+*   
+* Description:	Q31 matrix initialization.   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixInit Matrix Initialization   
+ *   
+ */
+
+/**   
+ * @addtogroup MatrixInit   
+ * @{   
+ */
+
+  /**   
+   * @brief  Q31 matrix initialization.   
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.   
+   * @param[in]     nRows          number of rows in the matrix.   
+   * @param[in]     nColumns       number of columns in the matrix.   
+   * @param[in]     *pData	   points to the matrix data array.   
+   * @return        none   
+   */
+
+void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**   
+ * @} end of MatrixInit group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
new file mode 100644
index 0000000..6a1e0e4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
@@ -0,0 +1,665 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_inverse_f32.c   
+*   
+* Description:	Floating-point matrix inverse.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixInv Matrix Inverse   
+ *   
+ * Computes the inverse of a matrix.   
+ *   
+ * The inverse is defined only if the input matrix is square and non-singular (the determinant   
+ * is non-zero). The function checks that the input and output matrices are square and of the   
+ * same size.   
+ *   
+ * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix   
+ * inversion of floating-point matrices.   
+ *   
+ * \par Algorithm   
+ * The Gauss-Jordan method is used to find the inverse.   
+ * The algorithm performs a sequence of elementary row-operations till it   
+ * reduces the input matrix to an identity matrix. Applying the same sequence   
+ * of elementary row-operations to an identity matrix yields the inverse matrix.   
+ * If the input matrix is singular, then the algorithm terminates and returns error status   
+ * ARM_MATH_SINGULAR.   
+ * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"   
+ */
+
+/**   
+ * @addtogroup MatrixInv   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point matrix inverse.   
+ * @param[in]       *pSrc points to input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns   
+ * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size   
+ * of the output matrix does not match the size of the input matrix.   
+ * If the input matrix is found to be singular (non-invertible), then the function returns   
+ * ARM_MATH_SINGULAR.  Otherwise, the function returns ARM_MATH_SUCCESS.   
+ */
+
+arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *pInT1, *pInT2;                      /* Temporary input data matrix pointer */
+  float32_t *pInT3, *pInT4;                      /* Temporary output data matrix pointer */
+  float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst;  /* Temporary input and output data matrix pointer */
+  uint32_t numRows = pSrc->numRows;              /* Number of rows in the matrix  */
+  uint32_t numCols = pSrc->numCols;              /* Number of Cols in the matrix  */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t Xchg, in = 0.0f, in1;                /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------   
+	 * Matrix Inverse can be solved using elementary row operations.   
+	 *   
+	 *	Gauss-Jordan Method:   
+	 *   
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an   
+	 *        augmented matrix as follows:   
+	 *				        _ 	      	       _         _	       _   
+	 *					   |  a11  a12 | 1   0  |       |  X11 X12  |   
+	 *					   |           |        |   =   |           |   
+	 *					   |_ a21  a22 | 0   1 _|       |_ X21 X21 _|   
+	 *   
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.   
+	 *   
+	 *		3. Begin with the first row. Let i = 1.   
+	 *   
+	 *	    4. Check to see if the pivot for row i is zero.   
+	 *		   The pivot is the element of the main diagonal that is on the current row.   
+	 *		   For instance, if working with row i, then the pivot element is aii.   
+	 *		   If the pivot is zero, exchange that row with a row below it that does not   
+	 *		   contain a zero in column i. If this is not possible, then an inverse   
+	 *		   to that matrix does not exist.   
+	 *   
+	 *	    5. Divide every element of row i by the pivot.   
+	 *   
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and   
+	 *		   a multiple of row i so that each new element in column i below row i is zero.   
+	 *   
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros   
+	 *		   for every element below and above the main diagonal.   
+	 *   
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).   
+	 *		   Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).   
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pInT2 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while(rowCnt > 0u)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pInT2++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1u;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.   
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0u;
+
+    while(loopCnt > 0u)
+    {
+      /* Check if the pivot element is zero..   
+       * If it is zero then interchange the row with non zero row below.   
+       * If there is no non zero element to replace in the rows below,   
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points   
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points   
+       * to the pivot element of the particular row  */
+      pInT3 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Destination pointer modifier */
+      k = 1u;
+
+      /* Check if the pivot element is zero */
+      if(*pInT1 == 0.0f)
+      {
+        /* Loop over the number rows present below */
+        i = numRows - (l + 1u);
+
+        while(i > 0u)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pInT4 = pInT3 + (numCols * k);
+
+          /* Check if there is a non zero pivot element to   
+           * replace in the rows below */
+          if(*pInT2 != 0.0f)
+          {
+            /* Loop over number of columns   
+             * to the right of the pilot element */
+            j = numCols - l;
+
+            while(j > 0u)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Loop over number of columns of the destination matrix */
+            j = numCols;
+
+            while(j > 0u)
+            {
+              /* Exchange the row elements of the destination matrix */
+              Xchg = *pInT4;
+              *pInT4++ = *pInT3;
+              *pInT3++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1u;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+
+          /* Decrement the loop counter */
+          i--;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if((flag != 1u) && (in == 0.0f))
+      {
+        status = ARM_MATH_SINGULAR;
+
+        break;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pInT2 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *(pIn + (l * numCols));
+
+      /* Loop over number of columns   
+       * to the right of the pilot element */
+      j = (numCols - l);
+
+      while(j > 0u)
+      {
+        /* Divide each element of the row of the input matrix   
+         * by the pivot element */
+        in1 = *pInT1;
+        *pInT1++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Loop over number of columns of the destination matrix */
+      j = numCols;
+
+      while(j > 0u)
+      {
+        /* Divide each element of the row of the destination matrix   
+         * by the pivot element */
+        in1 = *pInT2;
+        *pInT2++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i   
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pInT2 = pOut;
+
+      /* index used to check for pivot element */
+      i = 0u;
+
+      /* Loop over number of rows */
+      /*  to be replaced by the sum of that row and a multiple of row i */
+      k = numRows;
+
+      while(k > 0u)
+      {
+        /* Check for the pivot element */
+        if(i == l)
+        {
+          /* If the processing element is the pivot element,   
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+
+          pInT2 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,   
+             to replace the elements in the input matrix */
+          j = (numCols - l);
+
+          while(j > 0u)
+          {
+            /* Replace the element by the sum of that row   
+               and a multiple of the reference row  */
+            in1 = *pInT1;
+            *pInT1++ = in1 - (in * *pPRT_in++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+          /* Loop over the number of columns to   
+             replace the elements in the destination matrix */
+          j = numCols;
+
+          while(j > 0u)
+          {
+            /* Replace the element by the sum of that row   
+               and a multiple of the reference row  */
+            in1 = *pInT2;
+            *pInT2++ = in1 - (in * *pPRT_pDst++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+        }
+
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+
+        /* Decrement the loop counter */
+        k--;
+
+        /* Increment the pivot index */
+        i++;
+      }
+
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t Xchg, in = 0.0f;                     /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------      
+	 * Matrix Inverse can be solved using elementary row operations.       
+	 *       
+	 *	Gauss-Jordan Method:      
+	 *	 	      
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an       
+	 *        augmented matrix as follows:       
+	 *				        _  _	      _	    _	   _   _         _	       _      
+	 *					   |  |  a11  a12  | | | 1   0  |   |       |  X11 X12  |        
+	 *					   |  |            | | |        |   |   =   |           |       
+	 *					   |_ |_ a21  a22 _| | |_0   1 _|  _|       |_ X21 X21 _|      
+	 *					         
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.   
+	 *      
+	 *		3. Begin with the first row. Let i = 1.      
+	 *      
+	 *	    4. Check to see if the pivot for row i is zero.      
+	 *		   The pivot is the element of the main diagonal that is on the current row.      
+	 *		   For instance, if working with row i, then the pivot element is aii.      
+	 *		   If the pivot is zero, exchange that row with a row below it that does not       
+	 *		   contain a zero in column i. If this is not possible, then an inverse       
+	 *		   to that matrix does not exist.      
+	 *	      
+	 *	    5. Divide every element of row i by the pivot.      
+	 *	      
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and       
+	 *		   a multiple of row i so that each new element in column i below row i is zero.      
+	 *	      
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros      
+	 *		   for every element below and above the main diagonal.       
+	 *		   		         
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, src).      
+	 *		   Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).        
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pInT2 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while(rowCnt > 0u)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pInT2++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1u;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.    
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0u;
+    //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)  
+    while(loopCnt > 0u)
+    {
+      /* Check if the pivot element is zero..   
+       * If it is zero then interchange the row with non zero row below.  
+       * If there is no non zero element to replace in the rows below,  
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points    
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points    
+       * to the pivot element of the particular row  */
+      pInT3 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Destination pointer modifier */
+      k = 1u;
+
+      /* Check if the pivot element is zero */
+      if(*pInT1 == 0.0f)
+      {
+        /* Loop over the number rows present below */
+        for (i = (l + 1u); i < numRows; i++)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pInT4 = pInT3 + (numCols * k);
+
+          /* Check if there is a non zero pivot element to    
+           * replace in the rows below */
+          if(*pInT2 != 0.0f)
+          {
+            /* Loop over number of columns    
+             * to the right of the pilot element */
+            for (j = 0u; j < (numCols - l); j++)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+            }
+
+            for (j = 0u; j < numCols; j++)
+            {
+              Xchg = *pInT4;
+              *pInT4++ = *pInT3;
+              *pInT3++ = Xchg;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1u;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if((flag != 1u) && (in == 0.0f))
+      {
+        status = ARM_MATH_SINGULAR;
+
+        break;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pInT2 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *(pIn + (l * numCols));
+
+      /* Loop over number of columns    
+       * to the right of the pilot element */
+      for (j = 0u; j < (numCols - l); j++)
+      {
+        /* Divide each element of the row of the input matrix    
+         * by the pivot element */
+        *pInT1++ = *pInT1 / in;
+      }
+      for (j = 0u; j < numCols; j++)
+      {
+        /* Divide each element of the row of the destination matrix    
+         * by the pivot element */
+        *pInT2++ = *pInT2 / in;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i    
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pInT2 = pOut;
+
+      for (i = 0u; i < numRows; i++)
+      {
+        /* Check for the pivot element */
+        if(i == l)
+        {
+          /* If the processing element is the pivot element,    
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+          pInT2 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,    
+             to replace the elements in the input matrix */
+          for (j = 0u; j < (numCols - l); j++)
+          {
+            /* Replace the element by the sum of that row    
+               and a multiple of the reference row  */
+            *pInT1++ = *pInT1 - (in * *pPRT_in++);
+          }
+          /* Loop over the number of columns to    
+             replace the elements in the destination matrix */
+          for (j = 0u; j < numCols; j++)
+          {
+            /* Replace the element by the sum of that row    
+               and a multiple of the reference row  */
+            *pInT2++ = *pInT2 - (in * *pPRT_pDst++);
+          }
+
+        }
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+      }
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+    if((flag != 1u) && (in == 0.0f))
+    {
+      status = ARM_MATH_SINGULAR;
+    }
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixInv group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
new file mode 100644
index 0000000..c916032
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
@@ -0,0 +1,270 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_f32.c   
+*   
+* Description:  Floating-point matrix multiplication.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixMult Matrix Multiplication   
+ *   
+ * Multiplies two matrices.   
+ *   
+ * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices"   
+   
+ * Matrix multiplication is only defined if the number of columns of the   
+ * first matrix equals the number of rows of the second matrix.   
+ * Multiplying an M x N matrix with an N x P matrix results   
+ * in an M x P matrix.   
+ * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of   
+ * pSrcA and pSrcB are equal; and (2) that the size of the output   
+ * matrix equals the outer dimensions of pSrcA and pSrcB.   
+ */
+
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point matrix multiplication.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pInA = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0.0f;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+        /* matrix multiplication        */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop count */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = sum;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pInB = pSrcB->pData;                /* input data matrix pointer B */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pInA with each column in pInB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set    
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0.0f;
+
+        /* Initialize the pointer pIn1 to point to the starting address of the row being processed */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = sum;
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
new file mode 100644
index 0000000..e97c888
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
@@ -0,0 +1,284 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_fast_q15.c   
+*   
+* Description:	 Q15 matrix multiplication (fast variant)   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @param[in]		*pState points to the array for storing intermediate results   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The difference between the function arm_mat_mult_q15() and this fast variant is that   
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.   
+ * The result of each 1.15 x 1.15 multiplication is truncated to   
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30   
+ * format. Finally, the accumulator is saturated and converted to a 1.15 result.   
+ *   
+ * \par   
+ * The fast version has the same overflow behavior as the standard version but provides   
+ * less precision since it discards the low 16 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signals must be scaled down.   
+ * Scale down one of the input matrices by log2(numColsA) bits to   
+ * avoid overflows, as a total of numColsA additions are computed internally for each   
+ * output element.   
+ *   
+ * \par   
+ * See arm_mat_mult_q15() for a slower implementation of this function   
+ * which uses 64-bit accumulation to provide higher precision.   
+ */
+
+arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState)
+{
+  q31_t sum;                                     /* accumulator */
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+//  q15_t *pDst = pDst->pData;                   /* output data matrix pointer */   
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4u;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pInB++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0u;
+    px = pDst->pData;
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 2 MACs simultaneously. */
+        colCnt = numColsA >> 1;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum = __SMLAD(*__SIMD32(pInA)++, *__SIMD32(pInB)++, sum);
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process odd column samples */
+        if((numColsA & 0x1u) > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += ((q31_t) * pInA * (*pInB++));
+        }
+
+        /* Saturate and store the result in the destination buffer */
+        *px = (q15_t) (sum >> 15);
+        px++;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      i = i + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
new file mode 100644
index 0000000..8a6ff61
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
@@ -0,0 +1,202 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_fast_q31.c   
+*   
+* Description:	 Q31 matrix multiplication (fast variant).   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The difference between the function arm_mat_mult_q31() and this fast variant is that   
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to   
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30   
+ * format. Finally, the accumulator is saturated and converted to a 1.31 result.   
+ *   
+ * \par   
+ * The fast version has the same overflow behavior as the standard version but provides   
+ * less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signals must be scaled down.   
+ * Scale down one of the input matrices by log2(numColsA) bits to   
+ * avoid overflows, as a total of numColsA additions are computed internally for each   
+ * output element.   
+ *   
+ * \par   
+ * See arm_mat_mult_q31() for a slower implementation of this function   
+ * which uses 64-bit accumulation to provide higher precision.   
+ */
+
+arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+//  q31_t *pSrcB = pSrcB->pData;                    /* input data matrix pointer B */   
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.   
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
+        *px++ = sum << 1;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
new file mode 100644
index 0000000..224d815
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
@@ -0,0 +1,378 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_q15.c   
+*   
+* Description:	 Q15 matrix multiplication.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief Q15 matrix multiplication   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @param[in]		*pState points to the array for storing intermediate results  
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator. The inputs to the   
+ * multiplications are in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate   
+ * results are accumulated in a 64-bit accumulator in 34.30 format. This approach   
+ * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then   
+ * truncated to 34.15 format by discarding the low 15 bits and then saturated to   
+ * 1.15 format.   
+ *   
+ * \par   
+ * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ *   
+ */
+
+arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState)
+{
+  q63_t sum;                                     /* accumulator */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4u;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pInB++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0u;
+    px = pDst->pData;
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 2 MACs simultaneously. */
+        colCnt = numColsA >> 1;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum = __SMLALD(*__SIMD32(pInA)++, *__SIMD32(pInB)++, sum);
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process odd column samples */
+        if((numColsA & 0x1u) > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += ((q31_t) * pInA * (*pInB++));
+        }
+
+        /* Saturate and store the result in the destination buffer */
+        *px = (q15_t) (__SSAT((sum >> 15), 16));
+        px++;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      i = i + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q15_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set         
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pSrcA */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q31_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */
+        /* Saturate and store the result in the destination buffer */
+        *px++ = (q15_t) __SSAT((sum >> 15), 16);
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+      /* Update the pointer pSrcA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
new file mode 100644
index 0000000..51999eb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
@@ -0,0 +1,278 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_q31.c   
+*   
+* Description:	 Q31 matrix multiplication.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix multiplication   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate   
+ * multiplication results but provides only a single guard bit. There is no saturation   
+ * on intermediate additions. Thus, if the accumulator overflows it wraps around and   
+ * distorts the result. The input signals should be scaled down to avoid intermediate   
+ * overflows. The input is thus scaled down by log2(numColsA) bits   
+ * to avoid overflows, as a total of numColsA additions are performed internally.   
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ *   
+ */
+
+arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.   
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+        *px++ = (q31_t) (sum >> 31);
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = (pSrcB->pData) + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set         
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+        *px++ = (q31_t) (sum >> 31);
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+#endif
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
new file mode 100644
index 0000000..39d1ff9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_scale_f32.c   
+*   
+* Description:	Multiplies a floating-point matrix by a scalar.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixScale Matrix Scale   
+ *   
+ * Multiplies a matrix by a scalar.  This is accomplished by multiplying each element in the   
+ * matrix by the scalar.  For example:   
+ * \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix"   
+ *   
+ * The function checks to make sure that the input and output matrices are of the same size.   
+ *   
+ * In the fixed-point Q15 and Q31 functions, scale is represented by   
+ * a fractional multiplication scaleFract and an arithmetic shift shift.   
+ * The shift allows the gain of the scaling operation to exceed 1.0.   
+ * The overall scale factor applied to the fixed-point data is   
+ * 
   
+ *     scale = scaleFract * 2^shift.   
+ * 
   
+ */
+
+/**   
+ * @addtogroup MatrixScale   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point matrix scaling.   
+ * @param[in]       *pSrc points to input matrix structure   
+ * @param[in]       scale scale factor to be applied    
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either ARM_MATH_SIZE_MISMATCH    
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ */
+
+arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix scaling     */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * scale */
+      /* Scaling and results are stored in the destination buffer. */
+      *pOut++ = (*pIn++) * scale;
+      *pOut++ = (*pIn++) * scale;
+      *pOut++ = (*pIn++) * scale;
+      *pOut++ = (*pIn++) * scale;
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * scale */
+      /* The results are stored in the destination buffer. */
+      *pOut++ = (*pIn++) * scale;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixScale group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
new file mode 100644
index 0000000..aec9904
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_scale_q15.c   
+*   
+* Description:	Multiplies a Q15 matrix by a scalar.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixScale   
+ * @{   
+ */
+
+/**   
+ * @brief Q15 matrix scaling.   
+ * @param[in]       *pSrc points to input matrix   
+ * @param[in]       scaleFract fractional portion of the scale factor   
+ * @param[in]       shift number of bits to shift the result by   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The input data *pSrc and scaleFract are in 1.15 format.   
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.   
+ */
+
+arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pIn = pSrc->pData;                      /* input data matrix pointer */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  int32_t totShift = 15 - shift;                 /* total shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix scaling     */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixScale group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
new file mode 100644
index 0000000..4b894af
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_scale_q31.c   
+*   
+* Description:	Multiplies a Q31 matrix by a scalar.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixScale   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix scaling.   
+ * @param[in]       *pSrc points to input matrix   
+ * @param[in]       scaleFract fractional portion of the scale factor   
+ * @param[in]       shift number of bits to shift the result by   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The input data *pSrc and scaleFract are in 1.31 format.   
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.   
+ */
+
+arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q63_t out;                                     /* temporary variable to hold output value */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  int32_t totShift = 31 - shift;                 /* shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix scaling      */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch  */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixScale group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
new file mode 100644
index 0000000..d2cce68
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_sub_f32.c   
+*   
+* Description:	Floating-point matrix subtraction.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixSub Matrix Subtraction   
+ *   
+ * Subtract two matrices.   
+ * \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices"   
+ *   
+ * The functions check to make sure that   
+ * pSrcA, pSrcB, and pDst have the same   
+ * number of rows and columns.   
+ */
+
+/**   
+ * @addtogroup MatrixSub   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point matrix subtraction   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer  */
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix subtraction */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) - (*pIn2++);
+      *pOut++ = (*pIn1++) - (*pIn2++);
+      *pOut++ = (*pIn1++) - (*pIn2++);
+      *pOut++ = (*pIn1++) - (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) - (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixSub group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
new file mode 100644
index 0000000..5f6dd58
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
@@ -0,0 +1,155 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_sub_q15.c   
+*   
+* Description:	Q15 Matrix subtraction   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixSub   
+ * @{   
+ */
+
+/**   
+ * @brief Q15 matrix subtraction.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ */
+
+arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix subtraction  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Apply loop unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, Saturate and then store the results in the destination buffer. */
+      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixSub group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
new file mode 100644
index 0000000..3de675c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
@@ -0,0 +1,158 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_sub_q31.c   
+*   
+* Description:	Q31 matrix subtraction   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixSub   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix subtraction.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.   
+ */
+
+
+arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix subtraction */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition  */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      *pOut++ = clip_q63_to_q31(((q63_t) (*pIn1++)) - (*pIn2++));
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixSub group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
new file mode 100644
index 0000000..876fab6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
@@ -0,0 +1,213 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_trans_f32.c   
+*   
+* Description:	Floating-point matrix transpose.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+/**   
+ * @defgroup MatrixTrans Matrix Transpose   
+ *   
+ * Tranposes a matrix.   
+ * Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix.   
+ * \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix"   
+ */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixTrans   
+ * @{   
+ */
+
+/**   
+  * @brief Floating-point matrix transpose.   
+  * @param[in]  *pSrc points to the input matrix   
+  * @param[out] *pDst points to the output matrix   
+  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH   
+  * or ARM_MATH_SUCCESS based on the outcome of size checking.   
+  */
+
+
+arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of rows */
+  uint16_t nColumns = pSrc->numCols;             /* number of columns */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
+  arm_status status;                             /* status of matrix transpose  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Loop Unrolling */
+      blkCnt = nColumns >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(blkCnt > 0u)        /* column loop */
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      blkCnt = nColumns % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  uint16_t col, i = 0u, row = nRows;             /* loop counters */
+  arm_status status;                             /* status of matrix transpose  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);          /* row loop end  */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixTrans group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
new file mode 100644
index 0000000..44cb0f3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
@@ -0,0 +1,234 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_trans_q15.c   
+*   
+* Description:	Q15 matrix transpose.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixTrans   
+ * @{   
+ */
+
+/*   
+ * @brief Q15 matrix transpose.   
+ * @param[in]  *pSrc points to the input matrix   
+ * @param[out] *pDst points to the output matrix   
+ * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH   
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pSrcA = pSrc->pData;                    /* input data matrix pointer */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of nRows */
+  uint16_t nColumns = pSrc->numCols;             /* number of nColumns */
+  uint16_t col, row = nRows, i = 0u;             /* row and column loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* variable to hold temporary output  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = nColumns >> 2u;
+
+      /* The pointer pOut is set to starting address of the column being processed */
+      pOut = pDst->pData + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+        /* Read two elements from the row */
+        in = *__SIMD32(pSrcA)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) in;
+
+#else
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *pOut = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read two elements from the row */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        in = *__SIMD32(pSrcA)++;
+
+#else
+
+        in = *__SIMD32(pSrcA)++;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) in;
+
+#else
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *pOut = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      col = nColumns % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer pOut is set to starting address of the column being processed */
+      pOut = pDst->pData + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *pOut = *pSrcA++;
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixTrans group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
new file mode 100644
index 0000000..ef81039
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_trans_q31.c   
+*   
+* Description:	Q31 matrix transpose.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixTrans   
+ * @{   
+ */
+
+/*   
+  * @brief Q31 matrix transpose.   
+  * @param[in]  *pSrc points to the input matrix   
+  * @param[out] *pDst points to the output matrix   
+  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH   
+  * or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer  */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer  */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of nRows */
+  uint16_t nColumns = pSrc->numCols;             /* number of nColumns  */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      blkCnt = nColumns >> 2u;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      blkCnt = nColumns % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  uint16_t col, i = 0u, row = nRows;             /* loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    }
+    while(row > 0u);            /* row loop end */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixTrans group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
new file mode 100644
index 0000000..eb3fc24
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_max_f32.c   
+*   
+* Description:	Maximum value of a floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup Max Maximum   
+ *   
+ * Computes the maximum value of an array of data.    
+ * The function returns both the maximum value and its position within the array.    
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.   
+ */
+
+/**   
+ * @addtogroup Max   
+ * @{   
+ */
+
+
+/**   
+ * @brief Maximum value of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult maximum value returned here   
+ * @param[out]      *pIndex index of maximum value returned here   
+ * @return none.   
+ */
+
+void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex)
+{
+  float32_t maxVal, out;                         /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  /* Store the maximum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Max group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
new file mode 100644
index 0000000..371e597
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_max_q15.c   
+*   
+* Description:	Maximum value of a Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup Max   
+ * @{   
+ */
+
+
+/**   
+ * @brief Maximum value of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult maximum value returned here   
+ * @param[out]      *pIndex index of maximum value returned here   
+ * @return none.   
+ */
+
+void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex)
+{
+  q15_t maxVal, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Max group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
new file mode 100644
index 0000000..38451b0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_max_q31.c   
+*   
+* Description:	Maximum value of a Q31 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup Max   
+ * @{   
+ */
+
+
+/**   
+ * @brief Maximum value of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult maximum value returned here   
+ * @param[out]      *pIndex index of maximum value returned here   
+ * @return none.   
+ */
+
+void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex)
+{
+  q31_t maxVal, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* Compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Max group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
new file mode 100644
index 0000000..ff9a7c0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
@@ -0,0 +1,206 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_max_q7.c   
+*   
+* Description:	Maximum value of a Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup Max   
+ * @{   
+ */
+
+
+/**   
+ * @brief Maximum value of a Q7 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult maximum value returned here   
+ * @param[out]      *pIndex index of maximum value returned here   
+  * @return none.   
+ */
+
+void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t res, maxVal, x0, x1, maxVal2, maxVal1;    /* Temporary variables to store the output value. */
+  uint32_t blkCnt, index1, index2, index3, indx, indxMod;       /* loop counter */
+
+  /* Initialise the index value to zero. */
+  indx = 0u;
+
+  /* Load first input value that act as reference value for comparision */
+  res = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.  
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    indxMod = blockSize - (blkCnt * 4u);
+
+    /* Load two input values for comparision */
+    x0 = *pSrc++;
+    x1 = *pSrc++;
+
+    if(x0 < x1)
+    {
+      /* Update the maximum value and its index */
+      maxVal1 = x1;
+      index1 = indxMod + 1u;
+    }
+    else
+    {
+      /* Update the maximum value and its index */
+      maxVal1 = x0;
+      index1 = indxMod;
+    }
+
+    /* Load two input values for comparision */
+    x0 = *pSrc++;
+    x1 = *pSrc++;
+
+    if(x0 < x1)
+    {
+      /* Update the maximum value and its index */
+      maxVal2 = x1;
+      index2 = indxMod + 3u;
+    }
+    else
+    {
+      /* Update the maximum value and its index */
+      maxVal2 = x0;
+      index2 = indxMod + 2u;
+    }
+
+    if(maxVal1 < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      maxVal = maxVal2;
+      index3 = index2;
+    }
+    else
+    {
+      /* Update the maximum value and its index */
+      maxVal = maxVal1;
+      index3 = index1;
+    }
+
+    if(res < maxVal)
+    {
+      /* Update the maximum value and its index */
+      res = maxVal;
+      indx = index3;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* If the blockSize - 1 is not a multiple of 4, compute any remaining output samples here.  
+   ** No loop unrolling is used. */
+  blkCnt = (blockSize - 1u) % 0x04u;
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(res < maxVal)
+    {
+      /* Update the maximum value and its index */
+      res = maxVal;
+      indx = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = res;
+  *pIndex = indx;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t maxVal, out;                              /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize - 1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Max group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
new file mode 100644
index 0000000..fdda942
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_mean_f32.c   
+*   
+* Description:	Mean value of a floating-point vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup mean Mean   
+ *   
+ * Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * 	Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;   
+ * 
   
+ *   
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.   
+ */
+
+/**   
+ * @addtogroup mean   
+ * @{   
+ */
+
+
+/**   
+ * @brief Mean value of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult mean value returned here   
+ * @return none.   
+ */
+
+
+void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = sum / (float32_t) blockSize;
+}
+
+/**   
+ * @} end of mean group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
new file mode 100644
index 0000000..2f31a4d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_mean_q15.c   
+*   
+* Description:	Mean value of a Q15 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup mean   
+ * @{   
+ */
+
+/**   
+ * @brief Mean value of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult mean value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * The input is represented in 1.15 format and is accumulated in a 32-bit    
+ * accumulator in 17.15 format.    
+ * There is no risk of internal overflow with this approach, and the    
+ * full precision of intermediate result is preserved.    
+ * Finally, the accumulator is saturated and truncated to yield a result of 1.15 format.   
+ *   
+ */
+
+
+void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q15_t) (sum / blockSize);
+}
+
+/**   
+ * @} end of mean group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
new file mode 100644
index 0000000..6692c7c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_mean_q31.c   
+*   
+* Description:	Mean value of a Q31 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup mean   
+ * @{   
+ */
+
+/**   
+ * @brief Mean value of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult mean value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *\par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.31 format and is accumulated in a 64-bit   
+ * accumulator in 33.31 format.   
+ * There is no risk of internal overflow with this approach, and the    
+ * full precision of intermediate result is preserved.    
+ * Finally, the accumulator is truncated to yield a result of 1.31 format.   
+ *   
+ */
+
+
+void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q31_t) (sum / (int32_t) blockSize);
+}
+
+/**   
+ * @} end of mean group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
new file mode 100644
index 0000000..b61d104
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_mean_q7.c   
+*   
+* Description:	Mean value of a Q7 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup mean   
+ * @{   
+ */
+
+/**   
+ * @brief Mean value of a Q7 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult mean value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.    
+ * The input is represented in 1.7 format and is accumulated in a 32-bit   
+ * accumulator in 25.7 format.   
+ * There is no risk of internal overflow with this approach, and the    
+ * full precision of intermediate result is preserved.    
+ * Finally, the accumulator is truncated to yield a result of 1.7 format.   
+ *   
+ */
+
+
+void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q7_t) (sum / (int32_t) blockSize);
+}
+
+/**   
+ * @} end of mean group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
new file mode 100644
index 0000000..b6846bc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_min_f32.c   
+*   
+* Description:	Minimum value of a floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup Min Minimum   
+ *   
+ * Computes the minimum value of an array of data.    
+ * The function returns both the minimum value and its position within the array.    
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.   
+ */
+
+/**   
+ * @addtogroup Min   
+ * @{   
+ */
+
+
+/**   
+ * @brief Minimum value of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult minimum value returned here   
+ * @param[out]      *pIndex index of minimum value returned here   
+  * @return none.   
+ *   
+ */
+
+void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex)
+{
+  float32_t minVal, out;                         /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+  do
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize - 1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  /* Store the minimum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Min group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
new file mode 100644
index 0000000..788c8f1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_min_q15.c   
+*   
+* Description:	Minimum value of a Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+
+/**   
+ * @addtogroup Min   
+ * @{   
+ */
+
+
+/**   
+ * @brief Minimum value of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult minimum value returned here   
+ * @param[out]      *pIndex index of minimum value returned here   
+ * @return none.   
+ *   
+ */
+
+void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex)
+{
+  q15_t minVal, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+  do
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize - 1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Min group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
new file mode 100644
index 0000000..5d285d0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
@@ -0,0 +1,125 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_min_q31.c   
+*   
+* Description:	Minimum value of a Q31 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+
+/**   
+ * @addtogroup Min   
+ * @{   
+ */
+
+
+/**   
+ * @brief Minimum value of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult minimum value returned here   
+ * @param[out]      *pIndex index of minimum value returned here   
+ * @return none.   
+ *   
+ */
+
+void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex)
+{
+  q31_t minVal, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+  do
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize -1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Min group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
new file mode 100644
index 0000000..da6dc75
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_min_q7.c   
+*   
+* Description:	Minimum value of a Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup Min   
+ * @{   
+ */
+
+
+/**   
+ * @brief Minimum value of a Q7 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult minimum value returned here   
+ * @param[out]      *pIndex index of minimum value returned here   
+ * @return none.   
+ *   
+ */
+
+void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t minVal, minVal1, minVal2, res, x0, x1;    /* Temporary variables to store the output value. */
+  uint32_t blkCnt, indx, index1, index2, index3, indxMod;       /* loop counter */
+
+  /* Initialise the index value to zero. */
+  indx = 0u;
+
+  /* Load first input value that act as reference value for comparision */
+  res = *pSrc++;
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  while(blkCnt > 0u)
+  {
+    indxMod = blockSize - (blkCnt * 4u);
+
+    /* Load two input values for comparision */
+    x0 = *pSrc++;
+    x1 = *pSrc++;
+
+    if(x0 > x1)
+    {
+      /* Update the minimum value and its index */
+      minVal1 = x1;
+      index1 = indxMod + 1u;
+    }
+    else
+    {
+      /* Update the minimum value and its index */
+      minVal1 = x0;
+      index1 = indxMod;
+    }
+
+    /* Load two input values for comparision */
+    x0 = *pSrc++;
+    x1 = *pSrc++;
+
+    if(x0 > x1)
+    {
+      /* Update the minimum value and its index */
+      minVal2 = x1;
+      index2 = indxMod + 3u;
+    }
+    else
+    {
+      /* Update the minimum value and its index */
+      minVal2 = x0;
+      index2 = indxMod + 2u;
+    }
+
+    if(minVal1 > minVal2)
+    {
+      /* Update the minimum value and its index */
+      minVal = minVal2;
+      index3 = index2;
+    }
+    else
+    {
+      /* Update the minimum value and its index */
+      minVal = minVal1;
+      index3 = index1;
+    }
+
+    if(res > minVal)
+    {
+      /* Update the minimum value and its index */
+      res = minVal;
+      indx = index3;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  blkCnt = (blockSize - 1u) % 0x04u;
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(res > minVal)
+    {
+      /* Update the minimum value and its index */
+      res = minVal;
+      indx = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = res;
+  *pIndex = indx;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t minVal, out;                              /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize - 1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Min group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
new file mode 100644
index 0000000..70a188b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_power_f32.c   
+*   
+* Description:	Sum of the squares of the elements of a floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup power Power   
+ *   
+ * Calculates the sum of the squares of the elements in the input vector.   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * 	Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];   
+ * 
   
+ *  
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.    
+ */
+
+/**   
+ * @addtogroup power   
+ * @{   
+ */
+
+
+/**   
+ * @brief Sum of the squares of the elements of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult sum of the squares value returned here   
+ * @return none.   
+ *   
+ */
+
+
+void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* accumulator */
+  float32_t in;                                  /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* compute power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result to the destination */
+  *pResult = sum;
+}
+
+/**   
+ * @} end of power group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
new file mode 100644
index 0000000..3b5b848
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_power_q15.c   
+*   
+* Description:	Sum of the squares of the elements of a Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup power   
+ * @{   
+ */
+
+/**   
+ * @brief Sum of the squares of the elements of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult sum of the squares value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.    
+ * The input is represented in 1.15 format.  
+ * Intermediate multiplication yields a 2.30 format, and this   
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.   
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the return result is in 34.30 format.    
+ *   
+ */
+
+void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in32;                                    /* Temporary variable to store input value */
+  q15_t in16;                                    /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in32 = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in32, in32, sum);
+    in32 = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in32, in32, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in16 = *pSrc++;
+    sum = __SMLALD(in16, in16, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q31_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the results in 34.30 format  */
+  *pResult = sum;
+}
+
+/**   
+ * @} end of power group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
new file mode 100644
index 0000000..c25621e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_power_q31.c   
+*   
+* Description:	Sum of the squares of the elements of a Q31 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup power   
+ * @{   
+ */
+
+/**   
+ * @brief Sum of the squares of the elements of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult sum of the squares value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.31 format.   
+ * Intermediate multiplication yields a 2.62 format, and this   
+ * result is truncated to 2.48 format by discarding the lower 14 bits.   
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.   
+ * With 15 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the return result is in 16.48 format.    
+ *   
+ */
+
+void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  q31_t in;
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the results in 16.48 format  */
+  *pResult = sum;
+}
+
+/**   
+ * @} end of power group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
new file mode 100644
index 0000000..457950e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
@@ -0,0 +1,137 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_power_q7.c   
+*   
+* Description:	Sum of the squares of the elements of a Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup power   
+ * @{   
+ */
+
+/**   
+ * @brief Sum of the squares of the elements of a Q7 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult sum of the squares value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.    
+ * The input is represented in 1.7 format.  
+ * Intermediate multiplication yields a 2.14 format, and this   
+ * result is added without saturation to an accumulator in 18.14 format.   
+ * With 17 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the return result is in 18.14 format.    
+ *   
+ */
+
+void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  q7_t in;                                       /* Temporary variable to store input */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t input1;                                  /* Temporary variable to store packed input */
+  q15_t in1, in2;                                /* Temporary variables to store input */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Reading two inputs of pSrc vector and packing */
+    in1 = (q15_t) * pSrc++;
+    in2 = (q15_t) * pSrc++;
+    input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    sum = __SMLAD(input1, input1, sum);
+
+    /* Reading two inputs of pSrc vector and packing */
+    in1 = (q15_t) * pSrc++;
+    in2 = (q15_t) * pSrc++;
+    input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    sum = __SMLAD(input1, input1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q15_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result in 18.14 format  */
+  *pResult = sum;
+}
+
+/**   
+ * @} end of power group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
new file mode 100644
index 0000000..de3ea39
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
@@ -0,0 +1,130 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_rms_f32.c   
+*   
+* Description:	Root mean square value of an array of F32 type   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup RMS Root mean square (RMS)   
+ *   
+ *    
+ * Calculates the Root Mean Sqaure of the elements in the input vector.   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * 	Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));   
+ * 
   
+ *  
+ * There are separate functions for floating point, Q31, and Q15 data types.    
+ */
+
+/**   
+ * @addtogroup RMS   
+ * @{   
+ */
+
+
+/**   
+ * @brief Root Mean Square of the elements of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult rms value returned here   
+ * @return none.   
+ *   
+ */
+
+void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Accumulator */
+  float32_t in;                                  /* Tempoprary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the result in a temporary variable, sum  */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum  */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Rms and store the result in the destination */
+  arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
+}
+
+/**   
+ * @} end of RMS group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
new file mode 100644
index 0000000..e57485f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_rms_q15.c   
+*   
+* Description:	Root Mean Square of the elements of a Q15 vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup RMS   
+ * @{   
+ */
+
+/**   
+ * @brief Root Mean Square of the elements of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult rms value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.15 format.   
+ * Intermediate multiplication yields a 2.30 format, and this   
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.   
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower    
+ * 15 bits, and then saturated to yield a result in 1.15 format.   
+ *   
+ */
+
+void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q63_t sum = 0;                                 /* accumulator */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* temporary variable to store the input value */
+  q15_t in1;                                     /* temporary variable to store the input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in1 = *pSrc++;
+    sum = __SMLALD(in1, in1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Truncating and saturating the accumulator to 1.15 format */
+  sum = __SSAT((q31_t) (sum >> 15), 16);
+
+  in1 = (q15_t) (sum / blockSize);
+
+  /* Store the result in the destination */
+  arm_sqrt_q15(in1, pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* temporary variable to store the input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pSrc++;
+    sum += ((q31_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Truncating and saturating the accumulator to 1.15 format */
+  sum = __SSAT((q31_t) (sum >> 15), 16);
+
+  in = (q15_t) (sum / blockSize);
+
+  /* Store the result in the destination */
+  arm_sqrt_q15(in, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of RMS group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
new file mode 100644
index 0000000..a2533b1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_rms_q31.c   
+*   
+* Description:	Root Mean Square of the elements of a Q31 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup RMS   
+ * @{   
+ */
+
+
+/**   
+ * @brief Root Mean Square of the elements of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult rms value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ *\par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The input is represented in 1.31 format, and intermediate multiplication   
+ * yields a 2.62 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results,    
+ * but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * If the accumulator overflows, it wraps around and distorts the result.    
+ * In order to avoid overflows completely, the input signal must be scaled down by    
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.    
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.   
+ *   
+ */
+
+void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* accumulator */
+  q31_t in;                                      /* Temporary variable to store the input */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1 = pSrc;                            /* SrcA pointer */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the result in a temporary variable, sum */
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pSrc++;
+    sum += (q63_t) in *in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Convert data in 2.62 to 1.31 by 31 right shifts */
+  sum = sum >> 31;
+
+  /* Compute Rms and store the result in the destination vector */
+  arm_sqrt_q31((q31_t) (sum / (int32_t) blockSize), pResult);
+}
+
+/**   
+ * @} end of RMS group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
new file mode 100644
index 0000000..8009697
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
@@ -0,0 +1,222 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_std_f32.c   
+*   
+* Description:	Standard deviation of the elements of a floating-point vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup STD Standard deviation   
+ *   
+ * Calculates the standard deviation of the elements in the input vector.    
+ * The underlying algorithm is used:   
+ *  
+ * 
   
+ * 	Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))  
+ *  
+ *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]  
+ *  
+ *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]  
+ * 
  
+ *   
+ * There are separate functions for floating point, Q31, and Q15 data types.   
+ */
+
+/**   
+ * @addtogroup STD   
+ * @{   
+ */
+
+
+/**   
+ * @brief Standard deviation of the elements of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult standard deviation value returned here   
+ * @return none.   
+ *   
+ */
+
+
+void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t meanOfSquares, mean, in, squareOfMean;
+  uint32_t blkCnt;                               /* loop counter */
+  float32_t *pIn;                                /* Temporary pointer */
+
+  pIn = pSrc;
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sum / ((float32_t) blockSize - 1.0f);
+
+  /* Reset the accumulator */
+  sum = 0.0f;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+  /* Compute mean of all input values */
+  mean = sum / (float32_t) blockSize;
+
+  /* Compute square of mean */
+  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+                                  ((float32_t) blockSize - 1.0f));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
+  float32_t squareOfSum;                         /* Square of Sum */
+  float32_t in;                                  /* input value */
+  float32_t var;                                 /* Temporary varaince storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += in * in;
+
+    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+    /* Compute Sum of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute the square of sum */
+  squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+  /* Compute the variance */
+  var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_f32(var, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of STD group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
new file mode 100644
index 0000000..19d9884
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
@@ -0,0 +1,229 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_std_q15.c   
+*   
+* Description:	Standard deviation of an array of Q15 type.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup STD   
+ * @{   
+ */
+
+/**   
+ * @brief Standard deviation of the elements of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult standard deviation value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.15 format.  
+ * Intermediate multiplication yields a 2.30 format, and this   
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.   
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower    
+ * 15 bits, and then saturated to yield a result in 1.15 format.   
+ */
+
+void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  q15_t mean;                                    /* mean */
+  uint32_t blkCnt;                               /* loop counter */
+  q15_t t;                                       /* Temporary variable */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn;                                    /* Temporary pointer */
+  q31_t in;                                      /* input value */
+  q15_t in1;                                     /* input value */
+
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in1 = *pSrc++;
+    sum = __SMLALD(in1, in1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
+  sum = __SSAT((sum >> 15u), 16u);
+
+  meanOfSquares = (q31_t) ((sum * t) >> 14u);
+
+  /* Reset the accumulator */
+  sum = 0;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+  /* Compute mean of all input values */
+  t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
+  mean = (q15_t) __SSAT(sum, 16u);
+
+  /* Compute square of mean */
+  squareOfMean = ((q31_t) mean * mean) >> 15;
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+  /* mean of the squares minus the square of the mean. */
+  in1 = (q15_t) (meanOfSquares - squareOfMean);
+
+  /* Compute standard deviation and store the result to the destination */
+  arm_sqrt_q15(in1, pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+  q15_t in;                                      /* input value */
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += (in * in);
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
+  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+  /* Compute mean of all input values */
+  mean = (q15_t) __SSAT(sum, 16u);
+
+  /* Compute square of mean of the input samples  
+   * and then store the result in a temporary variable, squareOfMean.*/
+  t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
+  squareOfMean = ((q31_t) mean * mean) >> 15;
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+  /* mean of the squares minus the square of the mean. */
+  in = (q15_t) (meanOfSquares - squareOfMean);
+
+  /* Compute standard deviation and store the result to the destination */
+  arm_sqrt_q15(in, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+}
+
+/**   
+ * @} end of STD group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
new file mode 100644
index 0000000..d167ed7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
@@ -0,0 +1,219 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_std_q31.c   
+*   
+* Description:	Standard deviation of an array of Q31 type.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup STD   
+ * @{   
+ */
+
+
+/**   
+ * @brief Standard deviation of the elements of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult standard deviation value returned here   
+ * @return none.   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ *\par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The input is represented in 1.31 format, and intermediate multiplication   
+ * yields a 2.62 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results,    
+ * but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * If the accumulator overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by    
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.    
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.   
+ *   
+ */
+
+
+void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  q31_t mean;                                    /* mean */
+  q31_t in;                                      /* input value */
+  q31_t t;                                       /* Temporary variable */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn;                                    /* Temporary pointer */
+
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  sum = (sum >> 31);
+  meanOfSquares = (q31_t) ((sum * t) >> 30);
+
+  /* Reset the accumulator */
+  sum = 0;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+  sumOfSquares = (sumOfSquares >> 31);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Compute mean of all input values */
+  t = (q31_t) ((1.0f / (blockSize * (blockSize - 1u))) * 2147483648.0f);
+  mean = (q31_t) (sum);
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
+
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_q31(meanOfSquares - squareOfMean, pResult);
+
+}
+
+/**   
+ * @} end of STD group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
new file mode 100644
index 0000000..9b6a5a8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
@@ -0,0 +1,219 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_var_f32.c   
+*   
+* Description:	Variance of the elements of a floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup variance  Variance   
+ *   
+ * Calculates the variance of the elements in the input vector.   
+ * The underlying algorithm is used:   
+ *   
+ * 
   
+ * 	Result = (sumOfSquares - sum2 / blockSize) / (blockSize - 1)  
+ *  
+ *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]  
+ *  
+ *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]  
+ * 
  
+ *   
+ * There are separate functions for floating point, Q31, and Q15 data types.   
+ */
+
+/**   
+ * @addtogroup variance   
+ * @{   
+ */
+
+
+/**   
+ * @brief Variance of the elements of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult variance value returned here   
+ * @return none.   
+ *   
+ */
+
+
+void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t sum = (float32_t) 0.0;               /* Accumulator */
+  float32_t meanOfSquares, mean, in, squareOfMean;      /* Temporary variables */
+  uint32_t blkCnt;                               /* loop counter */
+  float32_t *pIn;                                /* Temporary pointer */
+
+  /* updating temporary pointer */
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sum / ((float32_t) blockSize - 1.0f);
+
+  /* Reset the accumulator */
+  sum = 0.0f;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+  /* Compute mean of all input values */
+  mean = sum / (float32_t) blockSize;
+
+  /* Compute square of mean */
+  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+                                  ((float32_t) blockSize - 1.0f));
+
+  /* Compute variance and then store the result to the destination */
+  *pResult = meanOfSquares - squareOfMean;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
+  float32_t squareOfSum;                         /* Square of Sum */
+  float32_t in;                                  /* input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += in * in;
+
+    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+    /* Compute Sum of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute the square of sum */
+  squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+  /* Compute the variance */
+  *pResult = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of variance group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
new file mode 100644
index 0000000..e557a0d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
@@ -0,0 +1,214 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_var_q15.c   
+*   
+* Description:	Variance of an array of Q15 type.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup variance   
+ * @{   
+ */
+
+/**   
+ * @brief Variance of the elements of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult variance value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.15 format.  
+ * Intermediate multiplication yields a 2.30 format, and this   
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.   
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower    
+ * 15 bits, and then saturated to yield a result in 1.15 format.   
+ *   
+ */
+
+
+void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* Mean of square and square of mean */
+  q15_t mean;                                    /* mean */
+  uint32_t blkCnt;                               /* loop counter */
+  q15_t t;                                       /* Temporary variable */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* Input variable */
+  q15_t in1;                                     /* Temporary variable */
+  q15_t *pIn;                                    /* Temporary pointer */
+
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in1 = *pSrc++;
+    sum = __SMLALD(in1, in1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
+  sum = __SSAT((sum >> 15u), 16u);
+
+  meanOfSquares = (q31_t) ((sum * t) >> 14u);
+
+  /* Reset the accumulator */
+  sum = 0;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+  q15_t in;                                      /* Temporary variable */
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += (in * in);
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
+  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Compute mean of all input values */
+  t = (q15_t) ((1.0f / (float32_t) (blockSize * (blockSize - 1u))) * 32768);
+  mean = __SSAT(sum, 16u);
+
+  /* Compute square of mean */
+  squareOfMean = ((q31_t) mean * mean) >> 15;
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+  /* Compute variance and then store the result to the destination */
+  *pResult = (meanOfSquares - squareOfMean);
+
+}
+
+/**   
+ * @} end of variance group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
new file mode 100644
index 0000000..c22f022
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
@@ -0,0 +1,216 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_var_q31.c   
+*   
+* Description:	Variance of an array of Q31 type.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup variance   
+ * @{   
+ */
+
+/**   
+ * @brief Variance of the elements of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult variance value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ *\par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The input is represented in 1.31 format, and intermediate multiplication   
+ * yields a 2.62 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results,    
+ * but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * If the accumulator overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by    
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.    
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.   
+ *   
+ */
+
+
+void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* Mean of square and square of mean */
+  q31_t mean;                                    /* Mean */
+  q31_t in;                                      /* Input variable */
+  q31_t t;                                       /* Temporary variable */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn;                                    /* Temporary pointer */
+
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q31_t) ((1.0 / (blockSize - 1)) * 1073741824LL);
+  sum = (sum >> 31);
+  meanOfSquares = (q31_t) ((sum * t) >> 30);
+
+  /* Reset the accumulator */
+  sum = 0;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q31_t) ((1.0 / (blockSize - 1)) * 1073741824LL);
+  sumOfSquares = (sumOfSquares >> 31);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Compute mean of all input values */
+  t = (q31_t) ((1.0 / (blockSize * (blockSize - 1u))) * 2147483648LL);
+  mean = (q31_t) (sum);
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
+
+  /* Compute variance and then store the result to the destination */
+  *pResult = (q63_t) meanOfSquares - squareOfMean;
+
+}
+
+/**   
+ * @} end of variance group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
new file mode 100644
index 0000000..86652cd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_copy_f32.c   
+*   
+* Description:	Copies the elements of a floating-point vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup copy Vector Copy   
+ *   
+ * Copies sample by sample from source vector to destination vector.   
+ *   
+ * 
   
+ * 	pDst[n] = pSrc[n];   0 <= n < blockSize.   
+ * 
   
+ *  
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.    
+ */
+
+/**   
+ * @addtogroup copy   
+ * @{   
+ */
+
+/**   
+ * @brief Copies the elements of a floating-point vector.    
+ * @param[in]       *pSrc points to input vector   
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the input vector  
+ * @return none.   
+ *   
+ */
+
+
+void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicCopy group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
new file mode 100644
index 0000000..d1a9c48
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
@@ -0,0 +1,130 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_copy_q15.c   
+*   
+* Description:	Copies the elements of a Q15 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup copy   
+ * @{   
+ */
+/**   
+ * @brief Copies the elements of a Q15 vector.    
+ * @param[in]       *pSrc points to input vector   
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the input vector  
+ * @return none.   
+ *   
+ */
+
+void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t in1, in2;                                /* Temporary variables */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Read two inputs */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* Store the values in the destination buffer by packing the two inputs */
+    *__SIMD32(pDst)++ = __PKHBT(in1, in2, 16);
+
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    *__SIMD32(pDst)++ = __PKHBT(in1, in2, 16);
+
+#else
+
+    /* Store the values in the destination buffer by packing the two inputs */
+    *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);
+
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the value in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicCopy group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
new file mode 100644
index 0000000..db445b3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_copy_q31.c   
+*   
+* Description:	Copies the elements of a Q31 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup copy   
+ * @{   
+ */
+
+/**   
+ * @brief Copies the elements of a Q31 vector.    
+ * @param[in]       *pSrc points to input vector   
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the input vector  
+ * @return none.   
+ *   
+ */
+
+void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the values in the destination buffer */
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the value in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicCopy group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
new file mode 100644
index 0000000..57647d8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_copy_q7.c   
+*   
+* Description:	Copies the elements of a Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup copy   
+ * @{   
+ */
+
+/**   
+ * @brief Copies the elements of a Q7 vector.   
+ * @param[in]       *pSrc points to input vector   
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the input vector  
+ * @return none.   
+ *   
+ */
+
+void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    /* 4 samples are copied and stored at a time using SIMD */
+    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicCopy group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
new file mode 100644
index 0000000..ec9e2a1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fill_f32.c   
+*   
+* Description:	Fills a constant value into a floating-point vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup Fill Vector Fill   
+ *   
+ * Fills the destination vector with a constant value.   
+ *   
+ * 
   
+ * 	pDst[n] = value;   0 <= n < blockSize.   
+ * 
   
+ *  
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.    
+ */
+
+/**   
+ * @addtogroup Fill   
+ * @{   
+ */
+
+/**   
+ * @brief Fills a constant value into a floating-point vector.    
+ * @param[in]       value input value to be filled  
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the output vector  
+ * @return none.   
+ *   
+ */
+
+
+void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+    *pDst++ = value;
+    *pDst++ = value;
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of Fill group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
new file mode 100644
index 0000000..2d8d7ad
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
@@ -0,0 +1,112 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fill_q15.c   
+*   
+* Description:	Fills a constant value into a Q15 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup Fill   
+ * @{   
+ */
+
+/**   
+ * @brief Fills a constant value into a Q15 vector.   
+ * @param[in]       value input value to be filled  
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the output vector  
+ * @return none.   
+ *   
+ */
+
+void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t packedValue;                             /* value packed to 32 bits */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Packing two 16 bit values to 32 bit value in order to use SIMD */
+  packedValue = __PKHBT(value, value, 16u);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *__SIMD32(pDst)++ = packedValue;
+    *__SIMD32(pDst)++ = packedValue;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of Fill group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
new file mode 100644
index 0000000..559f671
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fill_q31.c   
+*   
+* Description:	Fills a constant value into a Q31 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup Fill   
+ * @{   
+ */
+
+/**   
+ * @brief Fills a constant value into a Q31 vector.   
+ * @param[in]       value input value to be filled  
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the output vector  
+ * @return none.   
+ *   
+ */
+
+void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+    *pDst++ = value;
+    *pDst++ = value;
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of Fill group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
new file mode 100644
index 0000000..277f918
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fill_q7.c   
+*   
+* Description:	Fills a constant value into a Q7 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup Fill   
+ * @{   
+ */
+
+/**   
+ * @brief Fills a constant value into a Q7 vector.   
+ * @param[in]       value input value to be filled  
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the output vector  
+ * @return none.   
+ *   
+ */
+
+void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t packedValue;                             /* value packed to 32 bits */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Packing four 8 bit values to 32 bit value in order to use SIMD */
+  packedValue = __PACKq7(value, value, value, value);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *__SIMD32(pDst)++ = packedValue;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of Fill group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
new file mode 100644
index 0000000..c0f354d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
@@ -0,0 +1,193 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_float_to_q15.c   
+*   
+* Description:	Converts the elements of the floating-point vector to Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup float_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the floating-point vector to Q15 vector.   
+ * @param[in]       *pSrc points to the floating-point input vector   
+ * @param[out]      *pDst points to the Q15 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ * \par  
+ * The equation used for the conversion process is:   
+ * 
   
+ * 	pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.   
+ * 
   
+ * \par Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ * \note  
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro    
+ * defined in the preprocessor section of project options.    
+ *   
+ */
+
+
+void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of float_to_x group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
new file mode 100644
index 0000000..4d77624
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
@@ -0,0 +1,200 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_float_to_q31.c   
+*   
+* Description:	Converts the elements of the floating-point vector to Q31 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup float_to_x  Convert 32-bit floating point value   
+ */
+
+/**   
+ * @addtogroup float_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the floating-point vector to Q31 vector.   
+ * @param[in]       *pSrc points to the floating-point input vector   
+ * @param[out]      *pDst points to the Q31 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ *\par Description:   
+ * \par  
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.   
+ * 
   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.   
+ *  
+ * \note In order to apply rounding, the library should be rebuilt with the ROUNDING macro    
+ * defined in the preprocessor section of project options.    
+ */
+
+
+void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 32768 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of float_to_x group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
new file mode 100644
index 0000000..1a8a4a5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_float_to_q7.c   
+*   
+* Description:	Converts the elements of the floating-point vector to Q7 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup float_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the floating-point vector to Q7 vector.   
+ * @param[in]       *pSrc points to the floating-point input vector   
+ * @param[out]      *pDst points to the Q7 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ *\par Description:   
+ * \par  
+ * The equation used for the conversion process is:   
+ * 
   
+ * 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.   
+ * 
   
+ * \par Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.   
+ * \note  
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro    
+ * defined in the preprocessor section of project options.    
+ */
+
+
+void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q31_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of float_to_x group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
new file mode 100644
index 0000000..42aa072
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q15_to_float.c   
+*   
+* Description:	Converts the elements of the Q15 vector to floating-point vector.    
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup q15_to_x  Convert 16-bit Integer value   
+ */
+
+/**   
+ * @addtogroup q15_to_x   
+ * @{   
+ */
+
+
+
+
+/**   
+ * @brief  Converts the elements of the Q15 vector to floating-point vector.    
+ * @param[in]       *pSrc points to the Q15 input vector   
+ * @param[out]      *pDst points to the floating-point output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.   
+ * 
   
+ *  
+ */
+
+
+void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 32768 */
+    /* convert from q15 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 32768 */
+    /* convert from q15 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of q15_to_x group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
new file mode 100644
index 0000000..16043e0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q15_to_q31.c   
+*   
+* Description:	Converts the elements of the Q15 vector to Q31 vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q15_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q15 vector to Q31 vector.    
+ * @param[in]       *pSrc points to the Q15 input vector   
+ * @param[out]      *pDst points to the Q31 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:  
+ *  
+ * 
   
+ * 	pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.   
+ * 
   
+ *  
+ */
+
+
+void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t)A << 16 */
+    /* convert from q15 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 16;
+    *pDst++ = (q31_t) * pIn++ << 16;
+    *pDst++ = (q31_t) * pIn++ << 16;
+    *pDst++ = (q31_t) * pIn++ << 16;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t)A << 16 */
+    /* convert from q15 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 16;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q15_to_x group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
new file mode 100644
index 0000000..0ca22df
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
@@ -0,0 +1,117 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q15_to_q7.c   
+*   
+* Description:	Converts the elements of the Q15 vector to Q7 vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q15_to_x   
+ * @{   
+ */
+
+
+/**   
+ * @brief Converts the elements of the Q15 vector to Q7 vector.    
+ * @param[in]       *pSrc points to the Q15 input vector   
+ * @param[out]      *pDst points to the Q7 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.   
+ * 
  
+ *  
+ */
+
+
+void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 8 */
+    /* convert from q15 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 8 */
+    /* convert from q15 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q15_to_x group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
new file mode 100644
index 0000000..48a7694
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q31_to_float.c   
+*   
+* Description:	Converts the elements of the Q31 vector to floating-point vector.     
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup q31_to_x  Convert 32-bit Integer value   
+ */
+
+/**   
+ * @addtogroup q31_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q31 vector to floating-point vector.   
+ * @param[in]       *pSrc points to the Q31 input vector   
+ * @param[out]      *pDst points to the floating-point output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.   
+ * 
   
+ *  
+ */
+
+
+void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 2147483648 */
+    /* convert from q31 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 2147483648 */
+    /* convert from q31 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of q31_to_x group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
new file mode 100644
index 0000000..dafc1d8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q31_to_q15.c   
+*   
+* Description:	Converts the elements of the Q31 vector to Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q31_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q31 vector to Q15 vector.   
+ * @param[in]       *pSrc points to the Q31 input vector   
+ * @param[out]      *pDst points to the Q15 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *    
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.   
+ * 
   
+ *  
+ */
+
+
+void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A >> 16 */
+    /* convert from q31 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A >> 16 */
+    /* convert from q31 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q31_to_x group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
new file mode 100644
index 0000000..c7aedb0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q31_to_q7.c   
+*   
+* Description:	Converts the elements of the Q31 vector to Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q31_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q31 vector to Q7 vector.   
+ * @param[in]       *pSrc points to the Q31 input vector   
+ * @param[out]      *pDst points to the Q7 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.    
+ * 
   
+ *  
+ */
+
+
+void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 24 */
+    /* convert from q31 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 24 */
+    /* convert from q31 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q31_to_x group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
new file mode 100644
index 0000000..8669969
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q7_to_float.c   
+*   
+* Description:	Converts the elements of the Q7 vector to floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup q7_to_x  Convert 8-bit Integer value   
+ */
+
+/**   
+ * @addtogroup q7_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q7 vector to floating-point vector.   
+ * @param[in]       *pSrc points to the Q7 input vector   
+ * @param[out]      *pDst points to the floating-point output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *		    
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.   
+ * 
   
+ *  
+ */
+
+
+void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 128 */
+    /* convert from q7 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 128 */
+    /* convert from q7 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of q7_to_x group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
new file mode 100644
index 0000000..9d3b292
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q7_to_q15.c   
+*   
+* Description:	Converts the elements of the Q7 vector to Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q7_to_x   
+ * @{   
+ */
+
+
+
+
+/**   
+ * @brief Converts the elements of the Q7 vector to Q15 vector.   
+ * @param[in]       *pSrc points to the Q7 input vector   
+ * @param[out]      *pDst points to the Q15 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.   
+ * 
   
+ *  
+ */
+
+
+void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A << 8 */
+    /* convert from q7 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) * pIn++ << 8;
+    *pDst++ = (q15_t) * pIn++ << 8;
+    *pDst++ = (q15_t) * pIn++ << 8;
+    *pDst++ = (q15_t) * pIn++ << 8;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A << 8 */
+    /* convert from q7 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) * pIn++ << 8;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q7_to_x group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
new file mode 100644
index 0000000..11f2656
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q7_to_q31.c   
+*   
+* Description:	Converts the elements of the Q7 vector to Q31 vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q7_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q7 vector to Q31 vector.   
+ * @param[in]       *pSrc points to the Q7 input vector   
+ * @param[out]      *pDst points to the Q31 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
   
+ * 	pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.  
+ * 
    
+ *  
+ */
+
+
+void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t) A << 24 */
+    /* convert from q7 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 24;
+    *pDst++ = (q31_t) * pIn++ << 24;
+    *pDst++ = (q31_t) * pIn++ << 24;
+    *pDst++ = (q31_t) * pIn++ << 24;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t) A << 24 */
+    /* convert from q7 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 24;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q7_to_x group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
new file mode 100644
index 0000000..7dfe4c3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
@@ -0,0 +1,1236 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_f32.c   
+*   
+* Description:	Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @defgroup CFFT_CIFFT Complex FFT Functions   
+ *   
+ * \par   
+ * Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).   
+ * Computational complexity of CFFT reduces drastically when compared to DFT.   
+ * \par   
+ * This set of functions implements CFFT/CIFFT   
+ * for Q15, Q31, and floating-point data types.  The functions operates on in-place buffer which uses same buffer for input and output.   
+ * Complex input is stored in input buffer in an interleaved fashion.   
+ *   
+ * \par   
+ * The functions operate on blocks of input and output data and each call to the function processes   
+ * 2*fftLen samples through the transform.  pSrc  points to In-place arrays containing 2*fftLen values.   
+ * \par  
+ * The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below.   
+ * 
 {real[0], imag[0], real[1], imag[1],..} 
   
+ *   
+ * \par Lengths supported by the transform:  
+ * \par   
+ * Internally, the function utilize a radix-4 decimation in frequency(DIF) algorithm   
+ * and the size of the FFT supported are of the lengths [16, 64, 256, 1024].  
+ *    
+ *   
+ * \par Algorithm:   
+ *   
+ * Complex Fast Fourier Transform:   
+ * \par    
+ * Input real and imaginary data:   
+ * 
   
+ * x(n) = xa + j * ya   
+ * x(n+N/4 ) = xb + j * yb   
+ * x(n+N/2 ) = xc + j * yc   
+ * x(n+3N 4) = xd + j * yd   
+ * 
   
+ * where N is length of FFT   
+ * \par   
+ * Output real and imaginary data:   
+ * 
   
+ * X(4r) = xa'+ j * ya'   
+ * X(4r+1) = xb'+ j * yb'   
+ * X(4r+2) = xc'+ j * yc'   
+ * X(4r+3) = xd'+ j * yd'   
+ * 
   
+ * \par   
+ * Twiddle factors for radix-4 FFT:   
+ * 
   
+ * Wn = co1 + j * (- si1)   
+ * W2n = co2 + j * (- si2)   
+ * W3n = co3 + j * (- si3)   
+ * 
   
+ *   
+ * \par   
+ * \image html CFFT.gif "Radix-4 Decimation-in Frequency Complex Fast Fourier Transform"   
+ *   
+ * \par   
+ * Output from Radix-4 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output.   
+ * \par   
+ *  Butterfly CFFT equations:   
+ * 
   
+ * xa' = xa + xb + xc + xd   
+ * ya' = ya + yb + yc + yd   
+ * xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)   
+ * yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)   
+ * xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)   
+ * yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)   
+ * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)   
+ * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)   
+ * 
   
+ *   
+ *   
+ * Complex Inverse Fast Fourier Transform:   
+ * \par   
+ * CIFFT uses same twiddle factor table as CFFT with modifications in the design equation as shown below.   
+ *   
+ * \par   
+ *  Modified Butterfly CIFFT equations:   
+ * 
   
+ * xa' = xa + xb + xc + xd   
+ * ya' = ya + yb + yc + yd   
+ * xc' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)   
+ * yc' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)   
+ * xb' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)   
+ * yb' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)   
+ * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)   
+ * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)   
+ * 
   
+ *   
+ * \par Instance Structure   
+ * A separate instance structure must be defined for each Instance but the twiddle factors and bit reversal tables can be reused.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Initializes twiddle factor table and bit reversal table pointers   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Manually initialize the instance structure as follows:   
+ * 
   
+ *arm_cfft_radix4_instance_f32 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor, onebyfftLen};   
+ *arm_cfft_radix4_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+ *arm_cfft_radix4_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+ * 
   
+ * \par   
+ * where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT);   
+ * bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order);    
+ * pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table.   
+ * twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table;    
+ * pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table.   
+ * onebyfftLen value of 1/fftLen to calculate CIFFT;   
+ *  
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the CFFT/CIFFT function.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @brief Processing function for the floating-point CFFT/CIFFT.  
+ * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.  
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
+ * @return none.  
+ */
+
+void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc)
+{
+
+  if(S->ifftFlag == 1u)
+  {
+    /*  Complex IFFT radix-4  */
+    arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier, S->onebyfftLen);
+  }
+  else
+  {
+    /*  Complex FFT radix-4  */
+    arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
+
+
+
+/* ----------------------------------------------------------------------   
+** Internal helper function used by the FFTs   
+** ------------------------------------------------------------------- */
+
+/*   
+ * @brief  Core function for the floating-point CFFT butterfly process.  
+ * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef           points to the twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+void arm_radix4_butterfly_f32(
+  float32_t * pSrc,
+  uint16_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier)
+{
+
+  float32_t co1, co2, co3, si1, si2, si3;
+  float32_t t1, t2, r1, r2, s1, s2;
+  uint32_t ia1, ia2, ia3;
+  uint32_t i0, i1, i2, i3;
+  uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+
+    /* xa + xc */
+    r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xb + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = r1 + t1;
+
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = s1 + t2;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* xb - xd */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /*  index calculation for the coefficients */
+    ia2 = ia1 + ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+    /* (xa - xc) + (yb - yd) */
+    r1 = r2 + t1;
+
+    /* (xa - xc) - (yb - yd) */
+    r2 = r2 - t1;
+
+    /* (ya - yc) - (xb - xd) */
+    s1 = s2 - t2;
+
+    /* (ya - yc) + (xb - xd) */
+    s2 = s2 + t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+    /*  index calculation for the coefficients */
+    ia3 = ia2 + ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  }
+  while(--j);
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+
+    /* xa + xb */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+    /* xa - xb */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = r1 + t1;
+
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = s1 + t2;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1;
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1;
+
+    /* (xa+yb-xc-yd) */
+    r1 = r2 + t1;
+
+    /* (xa-yb-xc+yd) */
+    r2 = r2 - t1;
+
+    /* (ya-xb-yc+xd) */
+    s1 = s2 - t2;
+
+    /* (ya+xb-yc-xd) */
+    s2 = s2 + t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1;
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1;
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2;
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /*  Initializations for the fft calculation */
+  n2 = fftLen;
+  n1 = n2;
+  for (k = fftLen; k > 1u; k >>= 2u)
+  {
+    /*  Initializations for the fft calculation */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  FFT Calculation */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/*   
+ * @brief  Core function for the floating-point CIFFT butterfly process.  
+ * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @param[in]      onebyfftLen      value of 1/fftLen.  
+ * @return none.  
+ */
+
+void arm_radix4_butterfly_inverse_f32(
+  float32_t * pSrc,
+  uint16_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier,
+  float32_t onebyfftLen)
+{
+  float32_t co1, co2, co3, si1, si2, si3;
+  float32_t t1, t2, r1, r2, s1, s2;
+  uint32_t ia1, ia2, ia3;
+  uint32_t i0, i1, i2, i3;
+  uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xb + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = r1 + t1;
+
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = s1 + t2;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* xb - xd */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /*  index calculation for the coefficients */
+    ia2 = ia1 + ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+    /* (xa - xc) - (yb - yd) */
+    r1 = r2 - t1;
+
+    /* (xa - xc) + (yb - yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb - xd) */
+    s1 = s2 + t2;
+
+    /* (ya - yc) - (xb - xd) */
+    s2 = s2 - t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+    /*  index calculation for the coefficients */
+    ia3 = ia2 + ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  }
+  while(--j);
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
+
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1 * onebyfftLen;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
+
+
+    /* (xa - xc) - (yb-yd) */
+    r1 = r2 - t1;
+
+    /* (xa - xc) + (yb-yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb-xd) */
+    s1 = s2 + t2;
+
+    /* (ya - yc) - (xb-xd) */
+    s2 = s2 - t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1 * onebyfftLen;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2 * onebyfftLen;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /*  Calculation of first stage */
+  for (k = fftLen; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
+
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1 * onebyfftLen;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
+
+
+    /* (xa - xc) - (yb-yd) */
+    r1 = r2 - t1;
+
+    /* (xa - xc) + (yb-yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb-xd) */
+    s1 = s2 + t2;
+
+    /* (ya - yc) - (xb-xd) */
+    s2 = s2 - t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1 * onebyfftLen;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2 * onebyfftLen;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/*   
+ * @brief  In-place bit reversal function.  
+ * @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.  
+ * @param[in]      fftSize      length of the FFT.  
+ * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.  
+ * @param[in]      *pBitRevTab  points to the bit reversal table.  
+ * @return none.  
+ */
+
+void arm_bitreversal_f32(
+  float32_t * pSrc,
+  uint16_t fftSize,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab)
+{
+  uint16_t fftLenBy2, fftLenBy2p1;
+  uint16_t i, j;
+  float32_t in;
+
+  /*  Initializations */
+  j = 0u;
+  fftLenBy2 = fftSize >> 1u;
+  fftLenBy2p1 = (fftSize >> 1u) + 1u;
+
+  /* Bit Reversal Implementation */
+  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+  {
+    if(i < j)
+    {
+      /*  pSrc[i] <-> pSrc[j]; */
+      in = pSrc[2u * i];
+      pSrc[2u * i] = pSrc[2u * j];
+      pSrc[2u * j] = in;
+
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[(2u * i) + 1u];
+      pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+      pSrc[(2u * j) + 1u] = in;
+
+      /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+      in = pSrc[2u * (i + fftLenBy2p1)];
+      pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+      pSrc[2u * (j + fftLenBy2p1)] = in;
+
+      /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+      in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+        pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+    }
+
+    /*  pSrc[i+1u] <-> pSrc[j+1u] */
+    in = pSrc[2u * (i + 1u)];
+    pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+    pSrc[2u * (j + fftLenBy2)] = in;
+
+    /*  pSrc[i+2u] <-> pSrc[j+2u] */
+    in = pSrc[(2u * (i + 1u)) + 1u];
+    pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+    pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+    /*  Reading the index for the bit reversal */
+    j = *pBitRevTab;
+
+    /*  Updating the bit reversal index depending on the fft length  */
+    pBitRevTab += bitRevFactor;
+  }
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
new file mode 100644
index 0000000..c186541
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
@@ -0,0 +1,1551 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2011 ARM Limited. All rights reserved.   
+*   
+* $Date:        17. August 2011  
+* $Revision: 	V1.0.11  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_init_f32.c   
+*   
+* Description:	Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+** Version 1.0.11 2011/08/17 
+*    Updated to support 4096 CFFT length.  
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/*   
+* @brief  Floating-point Twiddle factors Table Generation   
+*/
+
+
+/**   
+* \par   
+* Example code for Floating-point Twiddle factors Generation:   
+* \par   
+* 
for(i = 0; i< N; i++)   
+* {   
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);   
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);   
+* } 
   
+* \par   
+* where N = 1024	and PI = 3.14159265358979   
+* \par   
+* Cos and Sin values are in interleaved fashion   
+*    
+*/
+
+static const float32_t twiddleCoef[4096*2] = {
+			1.000000000000000000f,	0.000000000000000000f,	0.999998823451701880f,	0.001533980186284766f,	0.999995293809576190f,	0.003067956762965976f,
+	0.999989411081928400f,	0.004601926120448571f,	0.999981175282601110f,	0.006135884649154475f,	0.999970586430974140f,	0.007669828739531097f,
+	0.999957644551963900f,	0.009203754782059819f,	0.999942349676023910f,	0.010737659167264491f,	0.999924701839144500f,	0.012271538285719925f,
+	0.999904701082852900f,	0.013805388528060391f,	0.999882347454212560f,	0.015339206284988100f,	0.999857641005823860f,	0.016872987947281710f,
+	0.999830581795823400f,	0.018406729905804820f,	0.999801169887884260f,	0.019940428551514441f,	0.999769405351215280f,	0.021474080275469508f,
+	0.999735288260561680f,	0.023007681468839369f,	0.999698818696204250f,	0.024541228522912288f,	0.999659996743959220f,	0.026074717829103901f,
+	0.999618822495178640f,	0.027608145778965740f,	0.999575296046749220f,	0.029141508764193722f,	0.999529417501093140f,	0.030674803176636626f,
+	0.999481186966166950f,	0.032208025408304586f,	0.999430604555461730f,	0.033741171851377580f,	0.999377670388002850f,	0.035274238898213947f,
+	0.999322384588349540f,	0.036807222941358832f,	0.999264747286594420f,	0.038340120373552694f,	0.999204758618363890f,	0.039872927587739811f,
+	0.999142418724816910f,	0.041405640977076739f,	0.999077727752645360f,	0.042938256934940820f,	0.999010685854073380f,	0.044470771854938668f,
+	0.998941293186856870f,	0.046003182130914623f,	0.998869549914283560f,	0.047535484156959303f,	0.998795456205172410f,	0.049067674327418015f,
+	0.998719012233872940f,	0.050599749036899282f,	0.998640218180265270f,	0.052131704680283324f,	0.998559074229759310f,	0.053663537652730520f,
+	0.998475580573294770f,	0.055195244349689934f,	0.998389737407340160f,	0.056726821166907748f,	0.998301544933892890f,	0.058258264500435752f,
+	0.998211003360478190f,	0.059789570746639868f,	0.998118112900149180f,	0.061320736302208578f,	0.998022873771486240f,	0.062851757564161406f,
+	0.997925286198596000f,	0.064382630929857465f,	0.997825350411111640f,	0.065913352797003805f,	0.997723066644191640f,	0.067443919563664051f,
+	0.997618435138519550f,	0.068974327628266746f,	0.997511456140303450f,	0.070504573389613856f,	0.997402129901275300f,	0.072034653246889332f,
+	0.997290456678690210f,	0.073564563599667426f,	0.997176436735326190f,	0.075094300847921305f,	0.997060070339482960f,	0.076623861392031492f,
+	0.996941357764982160f,	0.078153241632794232f,	0.996820299291165670f,	0.079682437971430126f,	0.996696895202896060f,	0.081211446809592441f,
+	0.996571145790554840f,	0.082740264549375692f,	0.996443051350042630f,	0.084268887593324071f,	0.996312612182778000f,	0.085797312344439894f,
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+	0.999998823451701880f,	-0.001533980186285172f,
+  };
+
+/**   
+* @brief  Initialization function for the floating-point CFFT/CIFFT.  
+* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.  
+* @param[in]     fftLen         length of the FFT.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+
+arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (float32_t *) twiddleCoef;
+
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+
+  case 4096u:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = armBitRevTable;
+    /*  Initialise the 1/N Value */
+    S->onebyfftLen = 0.000244140625;
+    break;
+
+  case 1024u:
+    /*  Initializations of structure parameters for 1024 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = &armBitRevTable[3];
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.0009765625f;
+    break;
+
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = &armBitRevTable[15];
+    S->onebyfftLen = 0.00390625f;
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = &armBitRevTable[63];
+    S->onebyfftLen = 0.015625f;
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = &armBitRevTable[255];
+    S->onebyfftLen = 0.0625f;
+    break;
+
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
new file mode 100644
index 0000000..176aee1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
@@ -0,0 +1,1197 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_init_q15.c   
+*   
+* Description:	Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/*   
+* @brief  Twiddle factors Table   
+*/
+
+/**  
+* \par   
+* Example code for Q15 Twiddle factors Generation::   
+* \par   
+* 
for(i = 0; i< N; i++)   
+* {   
+*	twiddleCoefQ15[2*i]= cos(i * 2*PI/(float)N);   
+*	twiddleCoefQ15[2*i+1]= sin(i * 2*PI/(float)N);   
+* } 
   
+* \par   
+* where N = 1024	and PI = 3.14159265358979   
+* \par   
+* Cos and Sin values are interleaved fashion   
+* \par   
+* Convert Floating point to Q15(Fixed point 1.15):   
+*	round(twiddleCoefQ15(i) * pow(2, 15))   
+*   
+*/
+
+static const q15_t twiddleCoefQ15[4096*2] = {
+
+0x7fff,	0x0,	0x7fff,	0x32,	0x7fff,	0x65,	0x7fff,	0x97,
+	0x7fff,	0xc9,	0x7fff,	0xfb,	0x7fff,	0x12e,	0x7ffe,	0x160,
+	0x7ffe,	0x192,	0x7ffd,	0x1c4,	0x7ffc,	0x1f7,	0x7ffb,	0x229,
+	0x7ffa,	0x25b,	0x7ff9,	0x28d,	0x7ff8,	0x2c0,	0x7ff7,	0x2f2,
+	0x7ff6,	0x324,	0x7ff5,	0x356,	0x7ff4,	0x389,	0x7ff2,	0x3bb,
+	0x7ff1,	0x3ed,	0x7fef,	0x41f,	0x7fed,	0x452,	0x7fec,	0x484,
+	0x7fea,	0x4b6,	0x7fe8,	0x4e8,	0x7fe6,	0x51b,	0x7fe4,	0x54d,
+	0x7fe2,	0x57f,	0x7fe0,	0x5b1,	0x7fdd,	0x5e3,	0x7fdb,	0x616,
+	0x7fd9,	0x648,	0x7fd6,	0x67a,	0x7fd3,	0x6ac,	0x7fd1,	0x6de,
+	0x7fce,	0x711,	0x7fcb,	0x743,	0x7fc8,	0x775,	0x7fc5,	0x7a7,
+	0x7fc2,	0x7d9,	0x7fbf,	0x80c,	0x7fbc,	0x83e,	0x7fb9,	0x870,
+	0x7fb5,	0x8a2,	0x7fb2,	0x8d4,	0x7fae,	0x906,	0x7fab,	0x938,
+	0x7fa7,	0x96b,	0x7fa3,	0x99d,	0x7fa0,	0x9cf,	0x7f9c,	0xa01,
+	0x7f98,	0xa33,	0x7f94,	0xa65,	0x7f90,	0xa97,	0x7f8b,	0xac9,
+	0x7f87,	0xafb,	0x7f83,	0xb2d,	0x7f7e,	0xb60,	0x7f7a,	0xb92,
+	0x7f75,	0xbc4,	0x7f71,	0xbf6,	0x7f6c,	0xc28,	0x7f67,	0xc5a,
+	0x7f62,	0xc8c,	0x7f5d,	0xcbe,	0x7f58,	0xcf0,	0x7f53,	0xd22,
+	0x7f4e,	0xd54,	0x7f49,	0xd86,	0x7f43,	0xdb8,	0x7f3e,	0xdea,
+	0x7f38,	0xe1c,	0x7f33,	0xe4e,	0x7f2d,	0xe80,	0x7f27,	0xeb2,
+	0x7f22,	0xee4,	0x7f1c,	0xf15,	0x7f16,	0xf47,	0x7f10,	0xf79,
+	0x7f0a,	0xfab,	0x7f03,	0xfdd,	0x7efd,	0x100f,	0x7ef7,	0x1041,
+	0x7ef0,	0x1073,	0x7eea,	0x10a4,	0x7ee3,	0x10d6,	0x7edd,	0x1108,
+	0x7ed6,	0x113a,	0x7ecf,	0x116c,	0x7ec8,	0x119e,	0x7ec1,	0x11cf,
+	0x7eba,	0x1201,	0x7eb3,	0x1233,	0x7eac,	0x1265,	0x7ea5,	0x1296,
+	0x7e9d,	0x12c8,	0x7e96,	0x12fa,	0x7e8e,	0x132b,	0x7e87,	0x135d,
+	0x7e7f,	0x138f,	0x7e78,	0x13c1,	0x7e70,	0x13f2,	0x7e68,	0x1424,
+	0x7e60,	0x1455,	0x7e58,	0x1487,	0x7e50,	0x14b9,	0x7e48,	0x14ea,
+	0x7e3f,	0x151c,	0x7e37,	0x154d,	0x7e2f,	0x157f,	0x7e26,	0x15b1,
+	0x7e1e,	0x15e2,	0x7e15,	0x1614,	0x7e0c,	0x1645,	0x7e03,	0x1677,
+	0x7dfb,	0x16a8,	0x7df2,	0x16da,	0x7de9,	0x170b,	0x7de0,	0x173c,
+	0x7dd6,	0x176e,	0x7dcd,	0x179f,	0x7dc4,	0x17d1,	0x7dba,	0x1802,
+	0x7db1,	0x1833,	0x7da7,	0x1865,	0x7d9e,	0x1896,	0x7d94,	0x18c7,
+	0x7d8a,	0x18f9,	0x7d81,	0x192a,	0x7d77,	0x195b,	0x7d6d,	0x198d,
+	0x7d63,	0x19be,	0x7d58,	0x19ef,	0x7d4e,	0x1a20,	0x7d44,	0x1a51,
+	0x7d3a,	0x1a83,	0x7d2f,	0x1ab4,	0x7d25,	0x1ae5,	0x7d1a,	0x1b16,
+	0x7d0f,	0x1b47,	0x7d05,	0x1b78,	0x7cfa,	0x1ba9,	0x7cef,	0x1bda,
+	0x7ce4,	0x1c0c,	0x7cd9,	0x1c3d,	0x7cce,	0x1c6e,	0x7cc2,	0x1c9f,
+	0x7cb7,	0x1cd0,	0x7cac,	0x1d01,	0x7ca0,	0x1d31,	0x7c95,	0x1d62,
+	0x7c89,	0x1d93,	0x7c7e,	0x1dc4,	0x7c72,	0x1df5,	0x7c66,	0x1e26,
+	0x7c5a,	0x1e57,	0x7c4e,	0x1e88,	0x7c42,	0x1eb8,	0x7c36,	0x1ee9,
+	0x7c2a,	0x1f1a,	0x7c1e,	0x1f4b,	0x7c11,	0x1f7b,	0x7c05,	0x1fac,
+	0x7bf9,	0x1fdd,	0x7bec,	0x200e,	0x7bdf,	0x203e,	0x7bd3,	0x206f,
+	0x7bc6,	0x209f,	0x7bb9,	0x20d0,	0x7bac,	0x2101,	0x7b9f,	0x2131,
+	0x7b92,	0x2162,	0x7b85,	0x2192,	0x7b78,	0x21c3,	0x7b6a,	0x21f3,
+	0x7b5d,	0x2224,	0x7b50,	0x2254,	0x7b42,	0x2284,	0x7b34,	0x22b5,
+	0x7b27,	0x22e5,	0x7b19,	0x2316,	0x7b0b,	0x2346,	0x7afd,	0x2376,
+	0x7aef,	0x23a7,	0x7ae1,	0x23d7,	0x7ad3,	0x2407,	0x7ac5,	0x2437,
+	0x7ab7,	0x2467,	0x7aa8,	0x2498,	0x7a9a,	0x24c8,	0x7a8c,	0x24f8,
+	0x7a7d,	0x2528,	0x7a6e,	0x2558,	0x7a60,	0x2588,	0x7a51,	0x25b8,
+	0x7a42,	0x25e8,	0x7a33,	0x2618,	0x7a24,	0x2648,	0x7a15,	0x2678,
+	0x7a06,	0x26a8,	0x79f7,	0x26d8,	0x79e7,	0x2708,	0x79d8,	0x2738,
+	0x79c9,	0x2768,	0x79b9,	0x2797,	0x79aa,	0x27c7,	0x799a,	0x27f7,
+	0x798a,	0x2827,	0x797a,	0x2856,	0x796a,	0x2886,	0x795b,	0x28b6,
+	0x794a,	0x28e5,	0x793a,	0x2915,	0x792a,	0x2945,	0x791a,	0x2974,
+	0x790a,	0x29a4,	0x78f9,	0x29d3,	0x78e9,	0x2a03,	0x78d8,	0x2a32,
+	0x78c8,	0x2a62,	0x78b7,	0x2a91,	0x78a6,	0x2ac1,	0x7895,	0x2af0,
+	0x7885,	0x2b1f,	0x7874,	0x2b4f,	0x7863,	0x2b7e,	0x7851,	0x2bad,
+	0x7840,	0x2bdc,	0x782f,	0x2c0c,	0x781e,	0x2c3b,	0x780c,	0x2c6a,
+	0x77fb,	0x2c99,	0x77e9,	0x2cc8,	0x77d8,	0x2cf7,	0x77c6,	0x2d26,
+	0x77b4,	0x2d55,	0x77a2,	0x2d84,	0x7790,	0x2db3,	0x777e,	0x2de2,
+	0x776c,	0x2e11,	0x775a,	0x2e40,	0x7748,	0x2e6f,	0x7736,	0x2e9e,
+	0x7723,	0x2ecc,	0x7711,	0x2efb,	0x76fe,	0x2f2a,	0x76ec,	0x2f59,
+	0x76d9,	0x2f87,	0x76c7,	0x2fb6,	0x76b4,	0x2fe5,	0x76a1,	0x3013,
+	0x768e,	0x3042,	0x767b,	0x3070,	0x7668,	0x309f,	0x7655,	0x30cd,
+	0x7642,	0x30fc,	0x762e,	0x312a,	0x761b,	0x3159,	0x7608,	0x3187,
+	0x75f4,	0x31b5,	0x75e1,	0x31e4,	0x75cd,	0x3212,	0x75b9,	0x3240,
+	0x75a6,	0x326e,	0x7592,	0x329d,	0x757e,	0x32cb,	0x756a,	0x32f9,
+	0x7556,	0x3327,	0x7542,	0x3355,	0x752d,	0x3383,	0x7519,	0x33b1,
+	0x7505,	0x33df,	0x74f0,	0x340d,	0x74dc,	0x343b,	0x74c7,	0x3469,
+	0x74b3,	0x3497,	0x749e,	0x34c4,	0x7489,	0x34f2,	0x7475,	0x3520,
+	0x7460,	0x354e,	0x744b,	0x357b,	0x7436,	0x35a9,	0x7421,	0x35d7,
+	0x740b,	0x3604,	0x73f6,	0x3632,	0x73e1,	0x365f,	0x73cb,	0x368d,
+	0x73b6,	0x36ba,	0x73a0,	0x36e8,	0x738b,	0x3715,	0x7375,	0x3742,
+	0x735f,	0x3770,	0x734a,	0x379d,	0x7334,	0x37ca,	0x731e,	0x37f7,
+	0x7308,	0x3825,	0x72f2,	0x3852,	0x72dc,	0x387f,	0x72c5,	0x38ac,
+	0x72af,	0x38d9,	0x7299,	0x3906,	0x7282,	0x3933,	0x726c,	0x3960,
+	0x7255,	0x398d,	0x723f,	0x39ba,	0x7228,	0x39e7,	0x7211,	0x3a13,
+	0x71fa,	0x3a40,	0x71e3,	0x3a6d,	0x71cc,	0x3a9a,	0x71b5,	0x3ac6,
+	0x719e,	0x3af3,	0x7187,	0x3b20,	0x7170,	0x3b4c,	0x7158,	0x3b79,
+	0x7141,	0x3ba5,	0x712a,	0x3bd2,	0x7112,	0x3bfe,	0x70fa,	0x3c2a,
+	0x70e3,	0x3c57,	0x70cb,	0x3c83,	0x70b3,	0x3caf,	0x709b,	0x3cdc,
+	0x7083,	0x3d08,	0x706b,	0x3d34,	0x7053,	0x3d60,	0x703b,	0x3d8c,
+	0x7023,	0x3db8,	0x700b,	0x3de4,	0x6ff2,	0x3e10,	0x6fda,	0x3e3c,
+	0x6fc2,	0x3e68,	0x6fa9,	0x3e94,	0x6f90,	0x3ec0,	0x6f78,	0x3eec,
+	0x6f5f,	0x3f17,	0x6f46,	0x3f43,	0x6f2d,	0x3f6f,	0x6f14,	0x3f9a,
+	0x6efb,	0x3fc6,	0x6ee2,	0x3ff1,	0x6ec9,	0x401d,	0x6eb0,	0x4048,
+	0x6e97,	0x4074,	0x6e7d,	0x409f,	0x6e64,	0x40cb,	0x6e4a,	0x40f6,
+	0x6e31,	0x4121,	0x6e17,	0x414d,	0x6dfe,	0x4178,	0x6de4,	0x41a3,
+	0x6dca,	0x41ce,	0x6db0,	0x41f9,	0x6d96,	0x4224,	0x6d7c,	0x424f,
+	0x6d62,	0x427a,	0x6d48,	0x42a5,	0x6d2e,	0x42d0,	0x6d14,	0x42fb,
+	0x6cf9,	0x4326,	0x6cdf,	0x4351,	0x6cc4,	0x437b,	0x6caa,	0x43a6,
+	0x6c8f,	0x43d1,	0x6c75,	0x43fb,	0x6c5a,	0x4426,	0x6c3f,	0x4450,
+	0x6c24,	0x447b,	0x6c09,	0x44a5,	0x6bee,	0x44d0,	0x6bd3,	0x44fa,
+	0x6bb8,	0x4524,	0x6b9d,	0x454f,	0x6b82,	0x4579,	0x6b66,	0x45a3,
+	0x6b4b,	0x45cd,	0x6b30,	0x45f7,	0x6b14,	0x4621,	0x6af8,	0x464b,
+	0x6add,	0x4675,	0x6ac1,	0x469f,	0x6aa5,	0x46c9,	0x6a89,	0x46f3,
+	0x6a6e,	0x471d,	0x6a52,	0x4747,	0x6a36,	0x4770,	0x6a1a,	0x479a,
+	0x69fd,	0x47c4,	0x69e1,	0x47ed,	0x69c5,	0x4817,	0x69a9,	0x4840,
+	0x698c,	0x486a,	0x6970,	0x4893,	0x6953,	0x48bd,	0x6937,	0x48e6,
+	0x691a,	0x490f,	0x68fd,	0x4939,	0x68e0,	0x4962,	0x68c4,	0x498b,
+	0x68a7,	0x49b4,	0x688a,	0x49dd,	0x686d,	0x4a06,	0x6850,	0x4a2f,
+	0x6832,	0x4a58,	0x6815,	0x4a81,	0x67f8,	0x4aaa,	0x67da,	0x4ad3,
+	0x67bd,	0x4afb,	0x67a0,	0x4b24,	0x6782,	0x4b4d,	0x6764,	0x4b75,
+	0x6747,	0x4b9e,	0x6729,	0x4bc7,	0x670b,	0x4bef,	0x66ed,	0x4c17,
+	0x66d0,	0x4c40,	0x66b2,	0x4c68,	0x6693,	0x4c91,	0x6675,	0x4cb9,
+	0x6657,	0x4ce1,	0x6639,	0x4d09,	0x661b,	0x4d31,	0x65fc,	0x4d59,
+	0x65de,	0x4d81,	0x65c0,	0x4da9,	0x65a1,	0x4dd1,	0x6582,	0x4df9,
+	0x6564,	0x4e21,	0x6545,	0x4e49,	0x6526,	0x4e71,	0x6507,	0x4e98,
+	0x64e9,	0x4ec0,	0x64ca,	0x4ee8,	0x64ab,	0x4f0f,	0x648b,	0x4f37,
+	0x646c,	0x4f5e,	0x644d,	0x4f85,	0x642e,	0x4fad,	0x640f,	0x4fd4,
+	0x63ef,	0x4ffb,	0x63d0,	0x5023,	0x63b0,	0x504a,	0x6391,	0x5071,
+	0x6371,	0x5098,	0x6351,	0x50bf,	0x6332,	0x50e6,	0x6312,	0x510d,
+	0x62f2,	0x5134,	0x62d2,	0x515b,	0x62b2,	0x5181,	0x6292,	0x51a8,
+	0x6272,	0x51cf,	0x6252,	0x51f5,	0x6232,	0x521c,	0x6211,	0x5243,
+	0x61f1,	0x5269,	0x61d1,	0x5290,	0x61b0,	0x52b6,	0x6190,	0x52dc,
+	0x616f,	0x5303,	0x614e,	0x5329,	0x612e,	0x534f,	0x610d,	0x5375,
+	0x60ec,	0x539b,	0x60cb,	0x53c1,	0x60aa,	0x53e7,	0x6089,	0x540d,
+	0x6068,	0x5433,	0x6047,	0x5459,	0x6026,	0x547f,	0x6005,	0x54a4,
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+	0xfb4a,	0x7fea,	0xfb18,	0x7fe8,	0xfae5,	0x7fe6,	0xfab3,	0x7fe4,
+	0xfa81,	0x7fe2,	0xfa4f,	0x7fe0,	0xfa1d,	0x7fdd,	0xf9ea,	0x7fdb,
+	0xf9b8,	0x7fd9,	0xf986,	0x7fd6,	0xf954,	0x7fd3,	0xf922,	0x7fd1,
+	0xf8ef,	0x7fce,	0xf8bd,	0x7fcb,	0xf88b,	0x7fc8,	0xf859,	0x7fc5,
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+	0xf75e,	0x7fb5,	0xf72c,	0x7fb2,	0xf6fa,	0x7fae,	0xf6c8,	0x7fab,
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+	0xf5cd,	0x7f98,	0xf59b,	0x7f94,	0xf569,	0x7f90,	0xf537,	0x7f8b,
+	0xf505,	0x7f87,	0xf4d3,	0x7f83,	0xf4a0,	0x7f7e,	0xf46e,	0x7f7a,
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+	0xf374,	0x7f62,	0xf342,	0x7f5d,	0xf310,	0x7f58,	0xf2de,	0x7f53,
+	0xf2ac,	0x7f4e,	0xf27a,	0x7f49,	0xf248,	0x7f43,	0xf216,	0x7f3e,
+	0xf1e4,	0x7f38,	0xf1b2,	0x7f33,	0xf180,	0x7f2d,	0xf14e,	0x7f27,
+	0xf11c,	0x7f22,	0xf0eb,	0x7f1c,	0xf0b9,	0x7f16,	0xf087,	0x7f10,
+	0xf055,	0x7f0a,	0xf023,	0x7f03,	0xeff1,	0x7efd,	0xefbf,	0x7ef7,
+	0xef8d,	0x7ef0,	0xef5c,	0x7eea,	0xef2a,	0x7ee3,	0xeef8,	0x7edd,
+	0xeec6,	0x7ed6,	0xee94,	0x7ecf,	0xee62,	0x7ec8,	0xee31,	0x7ec1,
+	0xedff,	0x7eba,	0xedcd,	0x7eb3,	0xed9b,	0x7eac,	0xed6a,	0x7ea5,
+	0xed38,	0x7e9d,	0xed06,	0x7e96,	0xecd5,	0x7e8e,	0xeca3,	0x7e87,
+	0xec71,	0x7e7f,	0xec3f,	0x7e78,	0xec0e,	0x7e70,	0xebdc,	0x7e68,
+	0xebab,	0x7e60,	0xeb79,	0x7e58,	0xeb47,	0x7e50,	0xeb16,	0x7e48,
+	0xeae4,	0x7e3f,	0xeab3,	0x7e37,	0xea81,	0x7e2f,	0xea4f,	0x7e26,
+	0xea1e,	0x7e1e,	0xe9ec,	0x7e15,	0xe9bb,	0x7e0c,	0xe989,	0x7e03,
+	0xe958,	0x7dfb,	0xe926,	0x7df2,	0xe8f5,	0x7de9,	0xe8c4,	0x7de0,
+	0xe892,	0x7dd6,	0xe861,	0x7dcd,	0xe82f,	0x7dc4,	0xe7fe,	0x7dba,
+	0xe7cd,	0x7db1,	0xe79b,	0x7da7,	0xe76a,	0x7d9e,	0xe739,	0x7d94,
+	0xe707,	0x7d8a,	0xe6d6,	0x7d81,	0xe6a5,	0x7d77,	0xe673,	0x7d6d,
+	0xe642,	0x7d63,	0xe611,	0x7d58,	0xe5e0,	0x7d4e,	0xe5af,	0x7d44,
+	0xe57d,	0x7d3a,	0xe54c,	0x7d2f,	0xe51b,	0x7d25,	0xe4ea,	0x7d1a,
+	0xe4b9,	0x7d0f,	0xe488,	0x7d05,	0xe457,	0x7cfa,	0xe426,	0x7cef,
+	0xe3f4,	0x7ce4,	0xe3c3,	0x7cd9,	0xe392,	0x7cce,	0xe361,	0x7cc2,
+	0xe330,	0x7cb7,	0xe2ff,	0x7cac,	0xe2cf,	0x7ca0,	0xe29e,	0x7c95,
+	0xe26d,	0x7c89,	0xe23c,	0x7c7e,	0xe20b,	0x7c72,	0xe1da,	0x7c66,
+	0xe1a9,	0x7c5a,	0xe178,	0x7c4e,	0xe148,	0x7c42,	0xe117,	0x7c36,
+	0xe0e6,	0x7c2a,	0xe0b5,	0x7c1e,	0xe085,	0x7c11,	0xe054,	0x7c05,
+	0xe023,	0x7bf9,	0xdff2,	0x7bec,	0xdfc2,	0x7bdf,	0xdf91,	0x7bd3,
+	0xdf61,	0x7bc6,	0xdf30,	0x7bb9,	0xdeff,	0x7bac,	0xdecf,	0x7b9f,
+	0xde9e,	0x7b92,	0xde6e,	0x7b85,	0xde3d,	0x7b78,	0xde0d,	0x7b6a,
+	0xdddc,	0x7b5d,	0xddac,	0x7b50,	0xdd7c,	0x7b42,	0xdd4b,	0x7b34,
+	0xdd1b,	0x7b27,	0xdcea,	0x7b19,	0xdcba,	0x7b0b,	0xdc8a,	0x7afd,
+	0xdc59,	0x7aef,	0xdc29,	0x7ae1,	0xdbf9,	0x7ad3,	0xdbc9,	0x7ac5,
+	0xdb99,	0x7ab7,	0xdb68,	0x7aa8,	0xdb38,	0x7a9a,	0xdb08,	0x7a8c,
+	0xdad8,	0x7a7d,	0xdaa8,	0x7a6e,	0xda78,	0x7a60,	0xda48,	0x7a51,
+	0xda18,	0x7a42,	0xd9e8,	0x7a33,	0xd9b8,	0x7a24,	0xd988,	0x7a15,
+	0xd958,	0x7a06,	0xd928,	0x79f7,	0xd8f8,	0x79e7,	0xd8c8,	0x79d8,
+	0xd898,	0x79c9,	0xd869,	0x79b9,	0xd839,	0x79aa,	0xd809,	0x799a,
+	0xd7d9,	0x798a,	0xd7aa,	0x797a,	0xd77a,	0x796a,	0xd74a,	0x795b,
+	0xd71b,	0x794a,	0xd6eb,	0x793a,	0xd6bb,	0x792a,	0xd68c,	0x791a,
+	0xd65c,	0x790a,	0xd62d,	0x78f9,	0xd5fd,	0x78e9,	0xd5ce,	0x78d8,
+	0xd59e,	0x78c8,	0xd56f,	0x78b7,	0xd53f,	0x78a6,	0xd510,	0x7895,
+	0xd4e1,	0x7885,	0xd4b1,	0x7874,	0xd482,	0x7863,	0xd453,	0x7851,
+	0xd424,	0x7840,	0xd3f4,	0x782f,	0xd3c5,	0x781e,	0xd396,	0x780c,
+	0xd367,	0x77fb,	0xd338,	0x77e9,	0xd309,	0x77d8,	0xd2da,	0x77c6,
+	0xd2ab,	0x77b4,	0xd27c,	0x77a2,	0xd24d,	0x7790,	0xd21e,	0x777e,
+	0xd1ef,	0x776c,	0xd1c0,	0x775a,	0xd191,	0x7748,	0xd162,	0x7736,
+	0xd134,	0x7723,	0xd105,	0x7711,	0xd0d6,	0x76fe,	0xd0a7,	0x76ec,
+	0xd079,	0x76d9,	0xd04a,	0x76c7,	0xd01b,	0x76b4,	0xcfed,	0x76a1,
+	0xcfbe,	0x768e,	0xcf90,	0x767b,	0xcf61,	0x7668,	0xcf33,	0x7655,
+	0xcf04,	0x7642,	0xced6,	0x762e,	0xcea7,	0x761b,	0xce79,	0x7608,
+	0xce4b,	0x75f4,	0xce1c,	0x75e1,	0xcdee,	0x75cd,	0xcdc0,	0x75b9,
+	0xcd92,	0x75a6,	0xcd63,	0x7592,	0xcd35,	0x757e,	0xcd07,	0x756a,
+	0xccd9,	0x7556,	0xccab,	0x7542,	0xcc7d,	0x752d,	0xcc4f,	0x7519,
+	0xcc21,	0x7505,	0xcbf3,	0x74f0,	0xcbc5,	0x74dc,	0xcb97,	0x74c7,
+	0xcb69,	0x74b3,	0xcb3c,	0x749e,	0xcb0e,	0x7489,	0xcae0,	0x7475,
+	0xcab2,	0x7460,	0xca85,	0x744b,	0xca57,	0x7436,	0xca29,	0x7421,
+	0xc9fc,	0x740b,	0xc9ce,	0x73f6,	0xc9a1,	0x73e1,	0xc973,	0x73cb,
+	0xc946,	0x73b6,	0xc918,	0x73a0,	0xc8eb,	0x738b,	0xc8be,	0x7375,
+	0xc890,	0x735f,	0xc863,	0x734a,	0xc836,	0x7334,	0xc809,	0x731e,
+	0xc7db,	0x7308,	0xc7ae,	0x72f2,	0xc781,	0x72dc,	0xc754,	0x72c5,
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+	0xc673,	0x7255,	0xc646,	0x723f,	0xc619,	0x7228,	0xc5ed,	0x7211,
+	0xc5c0,	0x71fa,	0xc593,	0x71e3,	0xc566,	0x71cc,	0xc53a,	0x71b5,
+	0xc50d,	0x719e,	0xc4e0,	0x7187,	0xc4b4,	0x7170,	0xc487,	0x7158,
+	0xc45b,	0x7141,	0xc42e,	0x712a,	0xc402,	0x7112,	0xc3d6,	0x70fa,
+	0xc3a9,	0x70e3,	0xc37d,	0x70cb,	0xc351,	0x70b3,	0xc324,	0x709b,
+	0xc2f8,	0x7083,	0xc2cc,	0x706b,	0xc2a0,	0x7053,	0xc274,	0x703b,
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+	0xc198,	0x6fc2,	0xc16c,	0x6fa9,	0xc140,	0x6f90,	0xc114,	0x6f78,
+	0xc0e9,	0x6f5f,	0xc0bd,	0x6f46,	0xc091,	0x6f2d,	0xc066,	0x6f14,
+	0xc03a,	0x6efb,	0xc00f,	0x6ee2,	0xbfe3,	0x6ec9,	0xbfb8,	0x6eb0,
+	0xbf8c,	0x6e97,	0xbf61,	0x6e7d,	0xbf35,	0x6e64,	0xbf0a,	0x6e4a,
+	0xbedf,	0x6e31,	0xbeb3,	0x6e17,	0xbe88,	0x6dfe,	0xbe5d,	0x6de4,
+	0xbe32,	0x6dca,	0xbe07,	0x6db0,	0xbddc,	0x6d96,	0xbdb1,	0x6d7c,
+	0xbd86,	0x6d62,	0xbd5b,	0x6d48,	0xbd30,	0x6d2e,	0xbd05,	0x6d14,
+	0xbcda,	0x6cf9,	0xbcaf,	0x6cdf,	0xbc85,	0x6cc4,	0xbc5a,	0x6caa,
+	0xbc2f,	0x6c8f,	0xbc05,	0x6c75,	0xbbda,	0x6c5a,	0xbbb0,	0x6c3f,
+	0xbb85,	0x6c24,	0xbb5b,	0x6c09,	0xbb30,	0x6bee,	0xbb06,	0x6bd3,
+	0xbadc,	0x6bb8,	0xbab1,	0x6b9d,	0xba87,	0x6b82,	0xba5d,	0x6b66,
+	0xba33,	0x6b4b,	0xba09,	0x6b30,	0xb9df,	0x6b14,	0xb9b5,	0x6af8,
+	0xb98b,	0x6add,	0xb961,	0x6ac1,	0xb937,	0x6aa5,	0xb90d,	0x6a89,
+	0xb8e3,	0x6a6e,	0xb8b9,	0x6a52,	0xb890,	0x6a36,	0xb866,	0x6a1a,
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+	0xb6f1,	0x691a,	0xb6c7,	0x68fd,	0xb69e,	0x68e0,	0xb675,	0x68c4,
+	0xb64c,	0x68a7,	0xb623,	0x688a,	0xb5fa,	0x686d,	0xb5d1,	0x6850,
+	0xb5a8,	0x6832,	0xb57f,	0x6815,	0xb556,	0x67f8,	0xb52d,	0x67da,
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+	0xb3c0,	0x66d0,	0xb398,	0x66b2,	0xb36f,	0x6693,	0xb347,	0x6675,
+	0xb31f,	0x6657,	0xb2f7,	0x6639,	0xb2cf,	0x661b,	0xb2a7,	0x65fc,
+	0xb27f,	0x65de,	0xb257,	0x65c0,	0xb22f,	0x65a1,	0xb207,	0x6582,
+	0xb1df,	0x6564,	0xb1b7,	0x6545,	0xb18f,	0x6526,	0xb168,	0x6507,
+	0xb140,	0x64e9,	0xb118,	0x64ca,	0xb0f1,	0x64ab,	0xb0c9,	0x648b,
+	0xb0a2,	0x646c,	0xb07b,	0x644d,	0xb053,	0x642e,	0xb02c,	0x640f,
+	0xb005,	0x63ef,	0xafdd,	0x63d0,	0xafb6,	0x63b0,	0xaf8f,	0x6391,
+	0xaf68,	0x6371,	0xaf41,	0x6351,	0xaf1a,	0x6332,	0xaef3,	0x6312,
+	0xaecc,	0x62f2,	0xaea5,	0x62d2,	0xae7f,	0x62b2,	0xae58,	0x6292,
+	0xae31,	0x6272,	0xae0b,	0x6252,	0xade4,	0x6232,	0xadbd,	0x6211,
+	0xad97,	0x61f1,	0xad70,	0x61d1,	0xad4a,	0x61b0,	0xad24,	0x6190,
+	0xacfd,	0x616f,	0xacd7,	0x614e,	0xacb1,	0x612e,	0xac8b,	0x610d,
+	0xac65,	0x60ec,	0xac3f,	0x60cb,	0xac19,	0x60aa,	0xabf3,	0x6089,
+	0xabcd,	0x6068,	0xaba7,	0x6047,	0xab81,	0x6026,	0xab5c,	0x6005,
+	0xab36,	0x5fe4,	0xab10,	0x5fc2,	0xaaeb,	0x5fa1,	0xaac5,	0x5f80,
+	0xaaa0,	0x5f5e,	0xaa7a,	0x5f3c,	0xaa55,	0x5f1b,	0xaa30,	0x5ef9,
+	0xaa0a,	0x5ed7,	0xa9e5,	0x5eb6,	0xa9c0,	0x5e94,	0xa99b,	0x5e72,
+	0xa976,	0x5e50,	0xa951,	0x5e2e,	0xa92c,	0x5e0c,	0xa907,	0x5dea,
+	0xa8e2,	0x5dc8,	0xa8bd,	0x5da5,	0xa899,	0x5d83,	0xa874,	0x5d61,
+	0xa84f,	0x5d3e,	0xa82b,	0x5d1c,	0xa806,	0x5cf9,	0xa7e2,	0x5cd7,
+	0xa7bd,	0x5cb4,	0xa799,	0x5c91,	0xa774,	0x5c6f,	0xa750,	0x5c4c,
+	0xa72c,	0x5c29,	0xa708,	0x5c06,	0xa6e4,	0x5be3,	0xa6c0,	0x5bc0,
+	0xa69c,	0x5b9d,	0xa678,	0x5b7a,	0xa654,	0x5b57,	0xa630,	0x5b34,
+	0xa60c,	0x5b10,	0xa5e8,	0x5aed,	0xa5c5,	0x5ac9,	0xa5a1,	0x5aa6,
+	0xa57e,	0x5a82,	0xa55a,	0x5a5f,	0xa537,	0x5a3b,	0xa513,	0x5a18,
+	0xa4f0,	0x59f4,	0xa4cc,	0x59d0,	0xa4a9,	0x59ac,	0xa486,	0x5988,
+	0xa463,	0x5964,	0xa440,	0x5940,	0xa41d,	0x591c,	0xa3fa,	0x58f8,
+	0xa3d7,	0x58d4,	0xa3b4,	0x58b0,	0xa391,	0x588c,	0xa36f,	0x5867,
+	0xa34c,	0x5843,	0xa329,	0x581e,	0xa307,	0x57fa,	0xa2e4,	0x57d5,
+	0xa2c2,	0x57b1,	0xa29f,	0x578c,	0xa27d,	0x5767,	0xa25b,	0x5743,
+	0xa238,	0x571e,	0xa216,	0x56f9,	0xa1f4,	0x56d4,	0xa1d2,	0x56af,
+	0xa1b0,	0x568a,	0xa18e,	0x5665,	0xa16c,	0x5640,	0xa14a,	0x561b,
+	0xa129,	0x55f6,	0xa107,	0x55d0,	0xa0e5,	0x55ab,	0xa0c4,	0x5586,
+	0xa0a2,	0x5560,	0xa080,	0x553b,	0xa05f,	0x5515,	0xa03e,	0x54f0,
+	0xa01c,	0x54ca,	0x9ffb,	0x54a4,	0x9fda,	0x547f,	0x9fb9,	0x5459,
+	0x9f98,	0x5433,	0x9f77,	0x540d,	0x9f56,	0x53e7,	0x9f35,	0x53c1,
+	0x9f14,	0x539b,	0x9ef3,	0x5375,	0x9ed2,	0x534f,	0x9eb2,	0x5329,
+	0x9e91,	0x5303,	0x9e70,	0x52dc,	0x9e50,	0x52b6,	0x9e2f,	0x5290,
+	0x9e0f,	0x5269,	0x9def,	0x5243,	0x9dce,	0x521c,	0x9dae,	0x51f5,
+	0x9d8e,	0x51cf,	0x9d6e,	0x51a8,	0x9d4e,	0x5181,	0x9d2e,	0x515b,
+	0x9d0e,	0x5134,	0x9cee,	0x510d,	0x9cce,	0x50e6,	0x9caf,	0x50bf,
+	0x9c8f,	0x5098,	0x9c6f,	0x5071,	0x9c50,	0x504a,	0x9c30,	0x5023,
+	0x9c11,	0x4ffb,	0x9bf1,	0x4fd4,	0x9bd2,	0x4fad,	0x9bb3,	0x4f85,
+	0x9b94,	0x4f5e,	0x9b75,	0x4f37,	0x9b55,	0x4f0f,	0x9b36,	0x4ee8,
+	0x9b17,	0x4ec0,	0x9af9,	0x4e98,	0x9ada,	0x4e71,	0x9abb,	0x4e49,
+	0x9a9c,	0x4e21,	0x9a7e,	0x4df9,	0x9a5f,	0x4dd1,	0x9a40,	0x4da9,
+	0x9a22,	0x4d81,	0x9a04,	0x4d59,	0x99e5,	0x4d31,	0x99c7,	0x4d09,
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+	0x9930,	0x4c40,	0x9913,	0x4c17,	0x98f5,	0x4bef,	0x98d7,	0x4bc7,
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+	0x8001,	0xc9,	0x8000,	0x97,	0x8000,	0x65,	0x8000,	0x32,
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+	0x8016,	0xfb4a,	0x8018,	0xfb18,	0x801a,	0xfae5,	0x801c,	0xfab3,
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+	0x8027,	0xf9b8,	0x802a,	0xf986,	0x802d,	0xf954,	0x802f,	0xf922,
+	0x8032,	0xf8ef,	0x8035,	0xf8bd,	0x8038,	0xf88b,	0x803b,	0xf859,
+	0x803e,	0xf827,	0x8041,	0xf7f4,	0x8044,	0xf7c2,	0x8047,	0xf790,
+	0x804b,	0xf75e,	0x804e,	0xf72c,	0x8052,	0xf6fa,	0x8055,	0xf6c8,
+	0x8059,	0xf695,	0x805d,	0xf663,	0x8060,	0xf631,	0x8064,	0xf5ff,
+	0x8068,	0xf5cd,	0x806c,	0xf59b,	0x8070,	0xf569,	0x8075,	0xf537,
+	0x8079,	0xf505,	0x807d,	0xf4d3,	0x8082,	0xf4a0,	0x8086,	0xf46e,
+	0x808b,	0xf43c,	0x808f,	0xf40a,	0x8094,	0xf3d8,	0x8099,	0xf3a6,
+	0x809e,	0xf374,	0x80a3,	0xf342,	0x80a8,	0xf310,	0x80ad,	0xf2de,
+	0x80b2,	0xf2ac,	0x80b7,	0xf27a,	0x80bd,	0xf248,	0x80c2,	0xf216,
+	0x80c8,	0xf1e4,	0x80cd,	0xf1b2,	0x80d3,	0xf180,	0x80d9,	0xf14e,
+	0x80de,	0xf11c,	0x80e4,	0xf0eb,	0x80ea,	0xf0b9,	0x80f0,	0xf087,
+	0x80f6,	0xf055,	0x80fd,	0xf023,	0x8103,	0xeff1,	0x8109,	0xefbf,
+	0x8110,	0xef8d,	0x8116,	0xef5c,	0x811d,	0xef2a,	0x8123,	0xeef8,
+	0x812a,	0xeec6,	0x8131,	0xee94,	0x8138,	0xee62,	0x813f,	0xee31,
+	0x8146,	0xedff,	0x814d,	0xedcd,	0x8154,	0xed9b,	0x815b,	0xed6a,
+	0x8163,	0xed38,	0x816a,	0xed06,	0x8172,	0xecd5,	0x8179,	0xeca3,
+	0x8181,	0xec71,	0x8188,	0xec3f,	0x8190,	0xec0e,	0x8198,	0xebdc,
+	0x81a0,	0xebab,	0x81a8,	0xeb79,	0x81b0,	0xeb47,	0x81b8,	0xeb16,
+	0x81c1,	0xeae4,	0x81c9,	0xeab3,	0x81d1,	0xea81,	0x81da,	0xea4f,
+	0x81e2,	0xea1e,	0x81eb,	0xe9ec,	0x81f4,	0xe9bb,	0x81fd,	0xe989,
+	0x8205,	0xe958,	0x820e,	0xe926,	0x8217,	0xe8f5,	0x8220,	0xe8c4,
+	0x822a,	0xe892,	0x8233,	0xe861,	0x823c,	0xe82f,	0x8246,	0xe7fe,
+	0x824f,	0xe7cd,	0x8259,	0xe79b,	0x8262,	0xe76a,	0x826c,	0xe739,
+	0x8276,	0xe707,	0x827f,	0xe6d6,	0x8289,	0xe6a5,	0x8293,	0xe673,
+	0x829d,	0xe642,	0x82a8,	0xe611,	0x82b2,	0xe5e0,	0x82bc,	0xe5af,
+	0x82c6,	0xe57d,	0x82d1,	0xe54c,	0x82db,	0xe51b,	0x82e6,	0xe4ea,
+	0x82f1,	0xe4b9,	0x82fb,	0xe488,	0x8306,	0xe457,	0x8311,	0xe426,
+	0x831c,	0xe3f4,	0x8327,	0xe3c3,	0x8332,	0xe392,	0x833e,	0xe361,
+	0x8349,	0xe330,	0x8354,	0xe2ff,	0x8360,	0xe2cf,	0x836b,	0xe29e,
+	0x8377,	0xe26d,	0x8382,	0xe23c,	0x838e,	0xe20b,	0x839a,	0xe1da,
+	0x83a6,	0xe1a9,	0x83b2,	0xe178,	0x83be,	0xe148,	0x83ca,	0xe117,
+	0x83d6,	0xe0e6,	0x83e2,	0xe0b5,	0x83ef,	0xe085,	0x83fb,	0xe054,
+	0x8407,	0xe023,	0x8414,	0xdff2,	0x8421,	0xdfc2,	0x842d,	0xdf91,
+	0x843a,	0xdf61,	0x8447,	0xdf30,	0x8454,	0xdeff,	0x8461,	0xdecf,
+	0x846e,	0xde9e,	0x847b,	0xde6e,	0x8488,	0xde3d,	0x8496,	0xde0d,
+	0x84a3,	0xdddc,	0x84b0,	0xddac,	0x84be,	0xdd7c,	0x84cc,	0xdd4b,
+	0x84d9,	0xdd1b,	0x84e7,	0xdcea,	0x84f5,	0xdcba,	0x8503,	0xdc8a,
+	0x8511,	0xdc59,	0x851f,	0xdc29,	0x852d,	0xdbf9,	0x853b,	0xdbc9,
+	0x8549,	0xdb99,	0x8558,	0xdb68,	0x8566,	0xdb38,	0x8574,	0xdb08,
+	0x8583,	0xdad8,	0x8592,	0xdaa8,	0x85a0,	0xda78,	0x85af,	0xda48,
+	0x85be,	0xda18,	0x85cd,	0xd9e8,	0x85dc,	0xd9b8,	0x85eb,	0xd988,
+	0x85fa,	0xd958,	0x8609,	0xd928,	0x8619,	0xd8f8,	0x8628,	0xd8c8,
+	0x8637,	0xd898,	0x8647,	0xd869,	0x8656,	0xd839,	0x8666,	0xd809,
+	0x8676,	0xd7d9,	0x8686,	0xd7aa,	0x8696,	0xd77a,	0x86a5,	0xd74a,
+	0x86b6,	0xd71b,	0x86c6,	0xd6eb,	0x86d6,	0xd6bb,	0x86e6,	0xd68c,
+	0x86f6,	0xd65c,	0x8707,	0xd62d,	0x8717,	0xd5fd,	0x8728,	0xd5ce,
+	0x8738,	0xd59e,	0x8749,	0xd56f,	0x875a,	0xd53f,	0x876b,	0xd510,
+	0x877b,	0xd4e1,	0x878c,	0xd4b1,	0x879d,	0xd482,	0x87af,	0xd453,
+	0x87c0,	0xd424,	0x87d1,	0xd3f4,	0x87e2,	0xd3c5,	0x87f4,	0xd396,
+	0x8805,	0xd367,	0x8817,	0xd338,	0x8828,	0xd309,	0x883a,	0xd2da,
+	0x884c,	0xd2ab,	0x885e,	0xd27c,	0x8870,	0xd24d,	0x8882,	0xd21e,
+	0x8894,	0xd1ef,	0x88a6,	0xd1c0,	0x88b8,	0xd191,	0x88ca,	0xd162,
+	0x88dd,	0xd134,	0x88ef,	0xd105,	0x8902,	0xd0d6,	0x8914,	0xd0a7,
+	0x8927,	0xd079,	0x8939,	0xd04a,	0x894c,	0xd01b,	0x895f,	0xcfed,
+	0x8972,	0xcfbe,	0x8985,	0xcf90,	0x8998,	0xcf61,	0x89ab,	0xcf33,
+	0x89be,	0xcf04,	0x89d2,	0xced6,	0x89e5,	0xcea7,	0x89f8,	0xce79,
+	0x8a0c,	0xce4b,	0x8a1f,	0xce1c,	0x8a33,	0xcdee,	0x8a47,	0xcdc0,
+	0x8a5a,	0xcd92,	0x8a6e,	0xcd63,	0x8a82,	0xcd35,	0x8a96,	0xcd07,
+	0x8aaa,	0xccd9,	0x8abe,	0xccab,	0x8ad3,	0xcc7d,	0x8ae7,	0xcc4f,
+	0x8afb,	0xcc21,	0x8b10,	0xcbf3,	0x8b24,	0xcbc5,	0x8b39,	0xcb97,
+	0x8b4d,	0xcb69,	0x8b62,	0xcb3c,	0x8b77,	0xcb0e,	0x8b8b,	0xcae0,
+	0x8ba0,	0xcab2,	0x8bb5,	0xca85,	0x8bca,	0xca57,	0x8bdf,	0xca29,
+	0x8bf5,	0xc9fc,	0x8c0a,	0xc9ce,	0x8c1f,	0xc9a1,	0x8c35,	0xc973,
+	0x8c4a,	0xc946,	0x8c60,	0xc918,	0x8c75,	0xc8eb,	0x8c8b,	0xc8be,
+	0x8ca1,	0xc890,	0x8cb6,	0xc863,	0x8ccc,	0xc836,	0x8ce2,	0xc809,
+	0x8cf8,	0xc7db,	0x8d0e,	0xc7ae,	0x8d24,	0xc781,	0x8d3b,	0xc754,
+	0x8d51,	0xc727,	0x8d67,	0xc6fa,	0x8d7e,	0xc6cd,	0x8d94,	0xc6a0,
+	0x8dab,	0xc673,	0x8dc1,	0xc646,	0x8dd8,	0xc619,	0x8def,	0xc5ed,
+	0x8e06,	0xc5c0,	0x8e1d,	0xc593,	0x8e34,	0xc566,	0x8e4b,	0xc53a,
+	0x8e62,	0xc50d,	0x8e79,	0xc4e0,	0x8e90,	0xc4b4,	0x8ea8,	0xc487,
+	0x8ebf,	0xc45b,	0x8ed6,	0xc42e,	0x8eee,	0xc402,	0x8f06,	0xc3d6,
+	0x8f1d,	0xc3a9,	0x8f35,	0xc37d,	0x8f4d,	0xc351,	0x8f65,	0xc324,
+	0x8f7d,	0xc2f8,	0x8f95,	0xc2cc,	0x8fad,	0xc2a0,	0x8fc5,	0xc274,
+	0x8fdd,	0xc248,	0x8ff5,	0xc21c,	0x900e,	0xc1f0,	0x9026,	0xc1c4,
+	0x903e,	0xc198,	0x9057,	0xc16c,	0x9070,	0xc140,	0x9088,	0xc114,
+	0x90a1,	0xc0e9,	0x90ba,	0xc0bd,	0x90d3,	0xc091,	0x90ec,	0xc066,
+	0x9105,	0xc03a,	0x911e,	0xc00f,	0x9137,	0xbfe3,	0x9150,	0xbfb8,
+	0x9169,	0xbf8c,	0x9183,	0xbf61,	0x919c,	0xbf35,	0x91b6,	0xbf0a,
+	0x91cf,	0xbedf,	0x91e9,	0xbeb3,	0x9202,	0xbe88,	0x921c,	0xbe5d,
+	0x9236,	0xbe32,	0x9250,	0xbe07,	0x926a,	0xbddc,	0x9284,	0xbdb1,
+	0x929e,	0xbd86,	0x92b8,	0xbd5b,	0x92d2,	0xbd30,	0x92ec,	0xbd05,
+	0x9307,	0xbcda,	0x9321,	0xbcaf,	0x933c,	0xbc85,	0x9356,	0xbc5a,
+	0x9371,	0xbc2f,	0x938b,	0xbc05,	0x93a6,	0xbbda,	0x93c1,	0xbbb0,
+	0x93dc,	0xbb85,	0x93f7,	0xbb5b,	0x9412,	0xbb30,	0x942d,	0xbb06,
+	0x9448,	0xbadc,	0x9463,	0xbab1,	0x947e,	0xba87,	0x949a,	0xba5d,
+	0x94b5,	0xba33,	0x94d0,	0xba09,	0x94ec,	0xb9df,	0x9508,	0xb9b5,
+	0x9523,	0xb98b,	0x953f,	0xb961,	0x955b,	0xb937,	0x9577,	0xb90d,
+	0x9592,	0xb8e3,	0x95ae,	0xb8b9,	0x95ca,	0xb890,	0x95e6,	0xb866,
+	0x9603,	0xb83c,	0x961f,	0xb813,	0x963b,	0xb7e9,	0x9657,	0xb7c0,
+	0x9674,	0xb796,	0x9690,	0xb76d,	0x96ad,	0xb743,	0x96c9,	0xb71a,
+	0x96e6,	0xb6f1,	0x9703,	0xb6c7,	0x9720,	0xb69e,	0x973c,	0xb675,
+	0x9759,	0xb64c,	0x9776,	0xb623,	0x9793,	0xb5fa,	0x97b0,	0xb5d1,
+	0x97ce,	0xb5a8,	0x97eb,	0xb57f,	0x9808,	0xb556,	0x9826,	0xb52d,
+	0x9843,	0xb505,	0x9860,	0xb4dc,	0x987e,	0xb4b3,	0x989c,	0xb48b,
+	0x98b9,	0xb462,	0x98d7,	0xb439,	0x98f5,	0xb411,	0x9913,	0xb3e9,
+	0x9930,	0xb3c0,	0x994e,	0xb398,	0x996d,	0xb36f,	0x998b,	0xb347,
+	0x99a9,	0xb31f,	0x99c7,	0xb2f7,	0x99e5,	0xb2cf,	0x9a04,	0xb2a7,
+	0x9a22,	0xb27f,	0x9a40,	0xb257,	0x9a5f,	0xb22f,	0x9a7e,	0xb207,
+	0x9a9c,	0xb1df,	0x9abb,	0xb1b7,	0x9ada,	0xb18f,	0x9af9,	0xb168,
+	0x9b17,	0xb140,	0x9b36,	0xb118,	0x9b55,	0xb0f1,	0x9b75,	0xb0c9,
+	0x9b94,	0xb0a2,	0x9bb3,	0xb07b,	0x9bd2,	0xb053,	0x9bf1,	0xb02c,
+	0x9c11,	0xb005,	0x9c30,	0xafdd,	0x9c50,	0xafb6,	0x9c6f,	0xaf8f,
+	0x9c8f,	0xaf68,	0x9caf,	0xaf41,	0x9cce,	0xaf1a,	0x9cee,	0xaef3,
+	0x9d0e,	0xaecc,	0x9d2e,	0xaea5,	0x9d4e,	0xae7f,	0x9d6e,	0xae58,
+	0x9d8e,	0xae31,	0x9dae,	0xae0b,	0x9dce,	0xade4,	0x9def,	0xadbd,
+	0x9e0f,	0xad97,	0x9e2f,	0xad70,	0x9e50,	0xad4a,	0x9e70,	0xad24,
+	0x9e91,	0xacfd,	0x9eb2,	0xacd7,	0x9ed2,	0xacb1,	0x9ef3,	0xac8b,
+	0x9f14,	0xac65,	0x9f35,	0xac3f,	0x9f56,	0xac19,	0x9f77,	0xabf3,
+	0x9f98,	0xabcd,	0x9fb9,	0xaba7,	0x9fda,	0xab81,	0x9ffb,	0xab5c,
+	0xa01c,	0xab36,	0xa03e,	0xab10,	0xa05f,	0xaaeb,	0xa080,	0xaac5,
+	0xa0a2,	0xaaa0,	0xa0c4,	0xaa7a,	0xa0e5,	0xaa55,	0xa107,	0xaa30,
+	0xa129,	0xaa0a,	0xa14a,	0xa9e5,	0xa16c,	0xa9c0,	0xa18e,	0xa99b,
+	0xa1b0,	0xa976,	0xa1d2,	0xa951,	0xa1f4,	0xa92c,	0xa216,	0xa907,
+	0xa238,	0xa8e2,	0xa25b,	0xa8bd,	0xa27d,	0xa899,	0xa29f,	0xa874,
+	0xa2c2,	0xa84f,	0xa2e4,	0xa82b,	0xa307,	0xa806,	0xa329,	0xa7e2,
+	0xa34c,	0xa7bd,	0xa36f,	0xa799,	0xa391,	0xa774,	0xa3b4,	0xa750,
+	0xa3d7,	0xa72c,	0xa3fa,	0xa708,	0xa41d,	0xa6e4,	0xa440,	0xa6c0,
+	0xa463,	0xa69c,	0xa486,	0xa678,	0xa4a9,	0xa654,	0xa4cc,	0xa630,
+	0xa4f0,	0xa60c,	0xa513,	0xa5e8,	0xa537,	0xa5c5,	0xa55a,	0xa5a1,
+	0xa57e,	0xa57e,	0xa5a1,	0xa55a,	0xa5c5,	0xa537,	0xa5e8,	0xa513,
+	0xa60c,	0xa4f0,	0xa630,	0xa4cc,	0xa654,	0xa4a9,	0xa678,	0xa486,
+	0xa69c,	0xa463,	0xa6c0,	0xa440,	0xa6e4,	0xa41d,	0xa708,	0xa3fa,
+	0xa72c,	0xa3d7,	0xa750,	0xa3b4,	0xa774,	0xa391,	0xa799,	0xa36f,
+	0xa7bd,	0xa34c,	0xa7e2,	0xa329,	0xa806,	0xa307,	0xa82b,	0xa2e4,
+	0xa84f,	0xa2c2,	0xa874,	0xa29f,	0xa899,	0xa27d,	0xa8bd,	0xa25b,
+	0xa8e2,	0xa238,	0xa907,	0xa216,	0xa92c,	0xa1f4,	0xa951,	0xa1d2,
+	0xa976,	0xa1b0,	0xa99b,	0xa18e,	0xa9c0,	0xa16c,	0xa9e5,	0xa14a,
+	0xaa0a,	0xa129,	0xaa30,	0xa107,	0xaa55,	0xa0e5,	0xaa7a,	0xa0c4,
+	0xaaa0,	0xa0a2,	0xaac5,	0xa080,	0xaaeb,	0xa05f,	0xab10,	0xa03e,
+	0xab36,	0xa01c,	0xab5c,	0x9ffb,	0xab81,	0x9fda,	0xaba7,	0x9fb9,
+	0xabcd,	0x9f98,	0xabf3,	0x9f77,	0xac19,	0x9f56,	0xac3f,	0x9f35,
+	0xac65,	0x9f14,	0xac8b,	0x9ef3,	0xacb1,	0x9ed2,	0xacd7,	0x9eb2,
+	0xacfd,	0x9e91,	0xad24,	0x9e70,	0xad4a,	0x9e50,	0xad70,	0x9e2f,
+	0xad97,	0x9e0f,	0xadbd,	0x9def,	0xade4,	0x9dce,	0xae0b,	0x9dae,
+	0xae31,	0x9d8e,	0xae58,	0x9d6e,	0xae7f,	0x9d4e,	0xaea5,	0x9d2e,
+	0xaecc,	0x9d0e,	0xaef3,	0x9cee,	0xaf1a,	0x9cce,	0xaf41,	0x9caf,
+	0xaf68,	0x9c8f,	0xaf8f,	0x9c6f,	0xafb6,	0x9c50,	0xafdd,	0x9c30,
+	0xb005,	0x9c11,	0xb02c,	0x9bf1,	0xb053,	0x9bd2,	0xb07b,	0x9bb3,
+	0xb0a2,	0x9b94,	0xb0c9,	0x9b75,	0xb0f1,	0x9b55,	0xb118,	0x9b36,
+	0xb140,	0x9b17,	0xb168,	0x9af9,	0xb18f,	0x9ada,	0xb1b7,	0x9abb,
+	0xb1df,	0x9a9c,	0xb207,	0x9a7e,	0xb22f,	0x9a5f,	0xb257,	0x9a40,
+	0xb27f,	0x9a22,	0xb2a7,	0x9a04,	0xb2cf,	0x99e5,	0xb2f7,	0x99c7,
+	0xb31f,	0x99a9,	0xb347,	0x998b,	0xb36f,	0x996d,	0xb398,	0x994e,
+	0xb3c0,	0x9930,	0xb3e9,	0x9913,	0xb411,	0x98f5,	0xb439,	0x98d7,
+	0xb462,	0x98b9,	0xb48b,	0x989c,	0xb4b3,	0x987e,	0xb4dc,	0x9860,
+	0xb505,	0x9843,	0xb52d,	0x9826,	0xb556,	0x9808,	0xb57f,	0x97eb,
+	0xb5a8,	0x97ce,	0xb5d1,	0x97b0,	0xb5fa,	0x9793,	0xb623,	0x9776,
+	0xb64c,	0x9759,	0xb675,	0x973c,	0xb69e,	0x9720,	0xb6c7,	0x9703,
+	0xb6f1,	0x96e6,	0xb71a,	0x96c9,	0xb743,	0x96ad,	0xb76d,	0x9690,
+	0xb796,	0x9674,	0xb7c0,	0x9657,	0xb7e9,	0x963b,	0xb813,	0x961f,
+	0xb83c,	0x9603,	0xb866,	0x95e6,	0xb890,	0x95ca,	0xb8b9,	0x95ae,
+	0xb8e3,	0x9592,	0xb90d,	0x9577,	0xb937,	0x955b,	0xb961,	0x953f,
+	0xb98b,	0x9523,	0xb9b5,	0x9508,	0xb9df,	0x94ec,	0xba09,	0x94d0,
+	0xba33,	0x94b5,	0xba5d,	0x949a,	0xba87,	0x947e,	0xbab1,	0x9463,
+	0xbadc,	0x9448,	0xbb06,	0x942d,	0xbb30,	0x9412,	0xbb5b,	0x93f7,
+	0xbb85,	0x93dc,	0xbbb0,	0x93c1,	0xbbda,	0x93a6,	0xbc05,	0x938b,
+	0xbc2f,	0x9371,	0xbc5a,	0x9356,	0xbc85,	0x933c,	0xbcaf,	0x9321,
+	0xbcda,	0x9307,	0xbd05,	0x92ec,	0xbd30,	0x92d2,	0xbd5b,	0x92b8,
+	0xbd86,	0x929e,	0xbdb1,	0x9284,	0xbddc,	0x926a,	0xbe07,	0x9250,
+	0xbe32,	0x9236,	0xbe5d,	0x921c,	0xbe88,	0x9202,	0xbeb3,	0x91e9,
+	0xbedf,	0x91cf,	0xbf0a,	0x91b6,	0xbf35,	0x919c,	0xbf61,	0x9183,
+	0xbf8c,	0x9169,	0xbfb8,	0x9150,	0xbfe3,	0x9137,	0xc00f,	0x911e,
+	0xc03a,	0x9105,	0xc066,	0x90ec,	0xc091,	0x90d3,	0xc0bd,	0x90ba,
+	0xc0e9,	0x90a1,	0xc114,	0x9088,	0xc140,	0x9070,	0xc16c,	0x9057,
+	0xc198,	0x903e,	0xc1c4,	0x9026,	0xc1f0,	0x900e,	0xc21c,	0x8ff5,
+	0xc248,	0x8fdd,	0xc274,	0x8fc5,	0xc2a0,	0x8fad,	0xc2cc,	0x8f95,
+	0xc2f8,	0x8f7d,	0xc324,	0x8f65,	0xc351,	0x8f4d,	0xc37d,	0x8f35,
+	0xc3a9,	0x8f1d,	0xc3d6,	0x8f06,	0xc402,	0x8eee,	0xc42e,	0x8ed6,
+	0xc45b,	0x8ebf,	0xc487,	0x8ea8,	0xc4b4,	0x8e90,	0xc4e0,	0x8e79,
+	0xc50d,	0x8e62,	0xc53a,	0x8e4b,	0xc566,	0x8e34,	0xc593,	0x8e1d,
+	0xc5c0,	0x8e06,	0xc5ed,	0x8def,	0xc619,	0x8dd8,	0xc646,	0x8dc1,
+	0xc673,	0x8dab,	0xc6a0,	0x8d94,	0xc6cd,	0x8d7e,	0xc6fa,	0x8d67,
+	0xc727,	0x8d51,	0xc754,	0x8d3b,	0xc781,	0x8d24,	0xc7ae,	0x8d0e,
+	0xc7db,	0x8cf8,	0xc809,	0x8ce2,	0xc836,	0x8ccc,	0xc863,	0x8cb6,
+	0xc890,	0x8ca1,	0xc8be,	0x8c8b,	0xc8eb,	0x8c75,	0xc918,	0x8c60,
+	0xc946,	0x8c4a,	0xc973,	0x8c35,	0xc9a1,	0x8c1f,	0xc9ce,	0x8c0a,
+	0xc9fc,	0x8bf5,	0xca29,	0x8bdf,	0xca57,	0x8bca,	0xca85,	0x8bb5,
+	0xcab2,	0x8ba0,	0xcae0,	0x8b8b,	0xcb0e,	0x8b77,	0xcb3c,	0x8b62,
+	0xcb69,	0x8b4d,	0xcb97,	0x8b39,	0xcbc5,	0x8b24,	0xcbf3,	0x8b10,
+	0xcc21,	0x8afb,	0xcc4f,	0x8ae7,	0xcc7d,	0x8ad3,	0xccab,	0x8abe,
+	0xccd9,	0x8aaa,	0xcd07,	0x8a96,	0xcd35,	0x8a82,	0xcd63,	0x8a6e,
+	0xcd92,	0x8a5a,	0xcdc0,	0x8a47,	0xcdee,	0x8a33,	0xce1c,	0x8a1f,
+	0xce4b,	0x8a0c,	0xce79,	0x89f8,	0xcea7,	0x89e5,	0xced6,	0x89d2,
+	0xcf04,	0x89be,	0xcf33,	0x89ab,	0xcf61,	0x8998,	0xcf90,	0x8985,
+	0xcfbe,	0x8972,	0xcfed,	0x895f,	0xd01b,	0x894c,	0xd04a,	0x8939,
+	0xd079,	0x8927,	0xd0a7,	0x8914,	0xd0d6,	0x8902,	0xd105,	0x88ef,
+	0xd134,	0x88dd,	0xd162,	0x88ca,	0xd191,	0x88b8,	0xd1c0,	0x88a6,
+	0xd1ef,	0x8894,	0xd21e,	0x8882,	0xd24d,	0x8870,	0xd27c,	0x885e,
+	0xd2ab,	0x884c,	0xd2da,	0x883a,	0xd309,	0x8828,	0xd338,	0x8817,
+	0xd367,	0x8805,	0xd396,	0x87f4,	0xd3c5,	0x87e2,	0xd3f4,	0x87d1,
+	0xd424,	0x87c0,	0xd453,	0x87af,	0xd482,	0x879d,	0xd4b1,	0x878c,
+	0xd4e1,	0x877b,	0xd510,	0x876b,	0xd53f,	0x875a,	0xd56f,	0x8749,
+	0xd59e,	0x8738,	0xd5ce,	0x8728,	0xd5fd,	0x8717,	0xd62d,	0x8707,
+	0xd65c,	0x86f6,	0xd68c,	0x86e6,	0xd6bb,	0x86d6,	0xd6eb,	0x86c6,
+	0xd71b,	0x86b6,	0xd74a,	0x86a5,	0xd77a,	0x8696,	0xd7aa,	0x8686,
+	0xd7d9,	0x8676,	0xd809,	0x8666,	0xd839,	0x8656,	0xd869,	0x8647,
+	0xd898,	0x8637,	0xd8c8,	0x8628,	0xd8f8,	0x8619,	0xd928,	0x8609,
+	0xd958,	0x85fa,	0xd988,	0x85eb,	0xd9b8,	0x85dc,	0xd9e8,	0x85cd,
+	0xda18,	0x85be,	0xda48,	0x85af,	0xda78,	0x85a0,	0xdaa8,	0x8592,
+	0xdad8,	0x8583,	0xdb08,	0x8574,	0xdb38,	0x8566,	0xdb68,	0x8558,
+	0xdb99,	0x8549,	0xdbc9,	0x853b,	0xdbf9,	0x852d,	0xdc29,	0x851f,
+	0xdc59,	0x8511,	0xdc8a,	0x8503,	0xdcba,	0x84f5,	0xdcea,	0x84e7,
+	0xdd1b,	0x84d9,	0xdd4b,	0x84cc,	0xdd7c,	0x84be,	0xddac,	0x84b0,
+	0xdddc,	0x84a3,	0xde0d,	0x8496,	0xde3d,	0x8488,	0xde6e,	0x847b,
+	0xde9e,	0x846e,	0xdecf,	0x8461,	0xdeff,	0x8454,	0xdf30,	0x8447,
+	0xdf61,	0x843a,	0xdf91,	0x842d,	0xdfc2,	0x8421,	0xdff2,	0x8414,
+	0xe023,	0x8407,	0xe054,	0x83fb,	0xe085,	0x83ef,	0xe0b5,	0x83e2,
+	0xe0e6,	0x83d6,	0xe117,	0x83ca,	0xe148,	0x83be,	0xe178,	0x83b2,
+	0xe1a9,	0x83a6,	0xe1da,	0x839a,	0xe20b,	0x838e,	0xe23c,	0x8382,
+	0xe26d,	0x8377,	0xe29e,	0x836b,	0xe2cf,	0x8360,	0xe2ff,	0x8354,
+	0xe330,	0x8349,	0xe361,	0x833e,	0xe392,	0x8332,	0xe3c3,	0x8327,
+	0xe3f4,	0x831c,	0xe426,	0x8311,	0xe457,	0x8306,	0xe488,	0x82fb,
+	0xe4b9,	0x82f1,	0xe4ea,	0x82e6,	0xe51b,	0x82db,	0xe54c,	0x82d1,
+	0xe57d,	0x82c6,	0xe5af,	0x82bc,	0xe5e0,	0x82b2,	0xe611,	0x82a8,
+	0xe642,	0x829d,	0xe673,	0x8293,	0xe6a5,	0x8289,	0xe6d6,	0x827f,
+	0xe707,	0x8276,	0xe739,	0x826c,	0xe76a,	0x8262,	0xe79b,	0x8259,
+	0xe7cd,	0x824f,	0xe7fe,	0x8246,	0xe82f,	0x823c,	0xe861,	0x8233,
+	0xe892,	0x822a,	0xe8c4,	0x8220,	0xe8f5,	0x8217,	0xe926,	0x820e,
+	0xe958,	0x8205,	0xe989,	0x81fd,	0xe9bb,	0x81f4,	0xe9ec,	0x81eb,
+	0xea1e,	0x81e2,	0xea4f,	0x81da,	0xea81,	0x81d1,	0xeab3,	0x81c9,
+	0xeae4,	0x81c1,	0xeb16,	0x81b8,	0xeb47,	0x81b0,	0xeb79,	0x81a8,
+	0xebab,	0x81a0,	0xebdc,	0x8198,	0xec0e,	0x8190,	0xec3f,	0x8188,
+	0xec71,	0x8181,	0xeca3,	0x8179,	0xecd5,	0x8172,	0xed06,	0x816a,
+	0xed38,	0x8163,	0xed6a,	0x815b,	0xed9b,	0x8154,	0xedcd,	0x814d,
+	0xedff,	0x8146,	0xee31,	0x813f,	0xee62,	0x8138,	0xee94,	0x8131,
+	0xeec6,	0x812a,	0xeef8,	0x8123,	0xef2a,	0x811d,	0xef5c,	0x8116,
+	0xef8d,	0x8110,	0xefbf,	0x8109,	0xeff1,	0x8103,	0xf023,	0x80fd,
+	0xf055,	0x80f6,	0xf087,	0x80f0,	0xf0b9,	0x80ea,	0xf0eb,	0x80e4,
+	0xf11c,	0x80de,	0xf14e,	0x80d9,	0xf180,	0x80d3,	0xf1b2,	0x80cd,
+	0xf1e4,	0x80c8,	0xf216,	0x80c2,	0xf248,	0x80bd,	0xf27a,	0x80b7,
+	0xf2ac,	0x80b2,	0xf2de,	0x80ad,	0xf310,	0x80a8,	0xf342,	0x80a3,
+	0xf374,	0x809e,	0xf3a6,	0x8099,	0xf3d8,	0x8094,	0xf40a,	0x808f,
+	0xf43c,	0x808b,	0xf46e,	0x8086,	0xf4a0,	0x8082,	0xf4d3,	0x807d,
+	0xf505,	0x8079,	0xf537,	0x8075,	0xf569,	0x8070,	0xf59b,	0x806c,
+	0xf5cd,	0x8068,	0xf5ff,	0x8064,	0xf631,	0x8060,	0xf663,	0x805d,
+	0xf695,	0x8059,	0xf6c8,	0x8055,	0xf6fa,	0x8052,	0xf72c,	0x804e,
+	0xf75e,	0x804b,	0xf790,	0x8047,	0xf7c2,	0x8044,	0xf7f4,	0x8041,
+	0xf827,	0x803e,	0xf859,	0x803b,	0xf88b,	0x8038,	0xf8bd,	0x8035,
+	0xf8ef,	0x8032,	0xf922,	0x802f,	0xf954,	0x802d,	0xf986,	0x802a,
+	0xf9b8,	0x8027,	0xf9ea,	0x8025,	0xfa1d,	0x8023,	0xfa4f,	0x8020,
+	0xfa81,	0x801e,	0xfab3,	0x801c,	0xfae5,	0x801a,	0xfb18,	0x8018,
+	0xfb4a,	0x8016,	0xfb7c,	0x8014,	0xfbae,	0x8013,	0xfbe1,	0x8011,
+	0xfc13,	0x800f,	0xfc45,	0x800e,	0xfc77,	0x800c,	0xfcaa,	0x800b,
+	0xfcdc,	0x800a,	0xfd0e,	0x8009,	0xfd40,	0x8008,	0xfd73,	0x8007,
+	0xfda5,	0x8006,	0xfdd7,	0x8005,	0xfe09,	0x8004,	0xfe3c,	0x8003,
+	0xfe6e,	0x8002,	0xfea0,	0x8002,	0xfed2,	0x8001,	0xff05,	0x8001,
+	0xff37,	0x8001,	0xff69,	0x8000,	0xff9b,	0x8000,	0xffce,	0x8000,
+	0x0,	0x8000,	0x32,	0x8000,	0x65,	0x8000,	0x97,	0x8000,
+	0xc9,	0x8001,	0xfb,	0x8001,	0x12e,	0x8001,	0x160,	0x8002,
+	0x192,	0x8002,	0x1c4,	0x8003,	0x1f7,	0x8004,	0x229,	0x8005,
+	0x25b,	0x8006,	0x28d,	0x8007,	0x2c0,	0x8008,	0x2f2,	0x8009,
+	0x324,	0x800a,	0x356,	0x800b,	0x389,	0x800c,	0x3bb,	0x800e,
+	0x3ed,	0x800f,	0x41f,	0x8011,	0x452,	0x8013,	0x484,	0x8014,
+	0x4b6,	0x8016,	0x4e8,	0x8018,	0x51b,	0x801a,	0x54d,	0x801c,
+	0x57f,	0x801e,	0x5b1,	0x8020,	0x5e3,	0x8023,	0x616,	0x8025,
+	0x648,	0x8027,	0x67a,	0x802a,	0x6ac,	0x802d,	0x6de,	0x802f,
+	0x711,	0x8032,	0x743,	0x8035,	0x775,	0x8038,	0x7a7,	0x803b,
+	0x7d9,	0x803e,	0x80c,	0x8041,	0x83e,	0x8044,	0x870,	0x8047,
+	0x8a2,	0x804b,	0x8d4,	0x804e,	0x906,	0x8052,	0x938,	0x8055,
+	0x96b,	0x8059,	0x99d,	0x805d,	0x9cf,	0x8060,	0xa01,	0x8064,
+	0xa33,	0x8068,	0xa65,	0x806c,	0xa97,	0x8070,	0xac9,	0x8075,
+	0xafb,	0x8079,	0xb2d,	0x807d,	0xb60,	0x8082,	0xb92,	0x8086,
+	0xbc4,	0x808b,	0xbf6,	0x808f,	0xc28,	0x8094,	0xc5a,	0x8099,
+	0xc8c,	0x809e,	0xcbe,	0x80a3,	0xcf0,	0x80a8,	0xd22,	0x80ad,
+	0xd54,	0x80b2,	0xd86,	0x80b7,	0xdb8,	0x80bd,	0xdea,	0x80c2,
+	0xe1c,	0x80c8,	0xe4e,	0x80cd,	0xe80,	0x80d3,	0xeb2,	0x80d9,
+	0xee4,	0x80de,	0xf15,	0x80e4,	0xf47,	0x80ea,	0xf79,	0x80f0,
+	0xfab,	0x80f6,	0xfdd,	0x80fd,	0x100f,	0x8103,	0x1041,	0x8109,
+	0x1073,	0x8110,	0x10a4,	0x8116,	0x10d6,	0x811d,	0x1108,	0x8123,
+	0x113a,	0x812a,	0x116c,	0x8131,	0x119e,	0x8138,	0x11cf,	0x813f,
+	0x1201,	0x8146,	0x1233,	0x814d,	0x1265,	0x8154,	0x1296,	0x815b,
+	0x12c8,	0x8163,	0x12fa,	0x816a,	0x132b,	0x8172,	0x135d,	0x8179,
+	0x138f,	0x8181,	0x13c1,	0x8188,	0x13f2,	0x8190,	0x1424,	0x8198,
+	0x1455,	0x81a0,	0x1487,	0x81a8,	0x14b9,	0x81b0,	0x14ea,	0x81b8,
+	0x151c,	0x81c1,	0x154d,	0x81c9,	0x157f,	0x81d1,	0x15b1,	0x81da,
+	0x15e2,	0x81e2,	0x1614,	0x81eb,	0x1645,	0x81f4,	0x1677,	0x81fd,
+	0x16a8,	0x8205,	0x16da,	0x820e,	0x170b,	0x8217,	0x173c,	0x8220,
+	0x176e,	0x822a,	0x179f,	0x8233,	0x17d1,	0x823c,	0x1802,	0x8246,
+	0x1833,	0x824f,	0x1865,	0x8259,	0x1896,	0x8262,	0x18c7,	0x826c,
+	0x18f9,	0x8276,	0x192a,	0x827f,	0x195b,	0x8289,	0x198d,	0x8293,
+	0x19be,	0x829d,	0x19ef,	0x82a8,	0x1a20,	0x82b2,	0x1a51,	0x82bc,
+	0x1a83,	0x82c6,	0x1ab4,	0x82d1,	0x1ae5,	0x82db,	0x1b16,	0x82e6,
+	0x1b47,	0x82f1,	0x1b78,	0x82fb,	0x1ba9,	0x8306,	0x1bda,	0x8311,
+	0x1c0c,	0x831c,	0x1c3d,	0x8327,	0x1c6e,	0x8332,	0x1c9f,	0x833e,
+	0x1cd0,	0x8349,	0x1d01,	0x8354,	0x1d31,	0x8360,	0x1d62,	0x836b,
+	0x1d93,	0x8377,	0x1dc4,	0x8382,	0x1df5,	0x838e,	0x1e26,	0x839a,
+	0x1e57,	0x83a6,	0x1e88,	0x83b2,	0x1eb8,	0x83be,	0x1ee9,	0x83ca,
+	0x1f1a,	0x83d6,	0x1f4b,	0x83e2,	0x1f7b,	0x83ef,	0x1fac,	0x83fb,
+	0x1fdd,	0x8407,	0x200e,	0x8414,	0x203e,	0x8421,	0x206f,	0x842d,
+	0x209f,	0x843a,	0x20d0,	0x8447,	0x2101,	0x8454,	0x2131,	0x8461,
+	0x2162,	0x846e,	0x2192,	0x847b,	0x21c3,	0x8488,	0x21f3,	0x8496,
+	0x2224,	0x84a3,	0x2254,	0x84b0,	0x2284,	0x84be,	0x22b5,	0x84cc,
+	0x22e5,	0x84d9,	0x2316,	0x84e7,	0x2346,	0x84f5,	0x2376,	0x8503,
+	0x23a7,	0x8511,	0x23d7,	0x851f,	0x2407,	0x852d,	0x2437,	0x853b,
+	0x2467,	0x8549,	0x2498,	0x8558,	0x24c8,	0x8566,	0x24f8,	0x8574,
+	0x2528,	0x8583,	0x2558,	0x8592,	0x2588,	0x85a0,	0x25b8,	0x85af,
+	0x25e8,	0x85be,	0x2618,	0x85cd,	0x2648,	0x85dc,	0x2678,	0x85eb,
+	0x26a8,	0x85fa,	0x26d8,	0x8609,	0x2708,	0x8619,	0x2738,	0x8628,
+	0x2768,	0x8637,	0x2797,	0x8647,	0x27c7,	0x8656,	0x27f7,	0x8666,
+	0x2827,	0x8676,	0x2856,	0x8686,	0x2886,	0x8696,	0x28b6,	0x86a5,
+	0x28e5,	0x86b6,	0x2915,	0x86c6,	0x2945,	0x86d6,	0x2974,	0x86e6,
+	0x29a4,	0x86f6,	0x29d3,	0x8707,	0x2a03,	0x8717,	0x2a32,	0x8728,
+	0x2a62,	0x8738,	0x2a91,	0x8749,	0x2ac1,	0x875a,	0x2af0,	0x876b,
+	0x2b1f,	0x877b,	0x2b4f,	0x878c,	0x2b7e,	0x879d,	0x2bad,	0x87af,
+	0x2bdc,	0x87c0,	0x2c0c,	0x87d1,	0x2c3b,	0x87e2,	0x2c6a,	0x87f4,
+	0x2c99,	0x8805,	0x2cc8,	0x8817,	0x2cf7,	0x8828,	0x2d26,	0x883a,
+	0x2d55,	0x884c,	0x2d84,	0x885e,	0x2db3,	0x8870,	0x2de2,	0x8882,
+	0x2e11,	0x8894,	0x2e40,	0x88a6,	0x2e6f,	0x88b8,	0x2e9e,	0x88ca,
+	0x2ecc,	0x88dd,	0x2efb,	0x88ef,	0x2f2a,	0x8902,	0x2f59,	0x8914,
+	0x2f87,	0x8927,	0x2fb6,	0x8939,	0x2fe5,	0x894c,	0x3013,	0x895f,
+	0x3042,	0x8972,	0x3070,	0x8985,	0x309f,	0x8998,	0x30cd,	0x89ab,
+	0x30fc,	0x89be,	0x312a,	0x89d2,	0x3159,	0x89e5,	0x3187,	0x89f8,
+	0x31b5,	0x8a0c,	0x31e4,	0x8a1f,	0x3212,	0x8a33,	0x3240,	0x8a47,
+	0x326e,	0x8a5a,	0x329d,	0x8a6e,	0x32cb,	0x8a82,	0x32f9,	0x8a96,
+	0x3327,	0x8aaa,	0x3355,	0x8abe,	0x3383,	0x8ad3,	0x33b1,	0x8ae7,
+	0x33df,	0x8afb,	0x340d,	0x8b10,	0x343b,	0x8b24,	0x3469,	0x8b39,
+	0x3497,	0x8b4d,	0x34c4,	0x8b62,	0x34f2,	0x8b77,	0x3520,	0x8b8b,
+	0x354e,	0x8ba0,	0x357b,	0x8bb5,	0x35a9,	0x8bca,	0x35d7,	0x8bdf,
+	0x3604,	0x8bf5,	0x3632,	0x8c0a,	0x365f,	0x8c1f,	0x368d,	0x8c35,
+	0x36ba,	0x8c4a,	0x36e8,	0x8c60,	0x3715,	0x8c75,	0x3742,	0x8c8b,
+	0x3770,	0x8ca1,	0x379d,	0x8cb6,	0x37ca,	0x8ccc,	0x37f7,	0x8ce2,
+	0x3825,	0x8cf8,	0x3852,	0x8d0e,	0x387f,	0x8d24,	0x38ac,	0x8d3b,
+	0x38d9,	0x8d51,	0x3906,	0x8d67,	0x3933,	0x8d7e,	0x3960,	0x8d94,
+	0x398d,	0x8dab,	0x39ba,	0x8dc1,	0x39e7,	0x8dd8,	0x3a13,	0x8def,
+	0x3a40,	0x8e06,	0x3a6d,	0x8e1d,	0x3a9a,	0x8e34,	0x3ac6,	0x8e4b,
+	0x3af3,	0x8e62,	0x3b20,	0x8e79,	0x3b4c,	0x8e90,	0x3b79,	0x8ea8,
+	0x3ba5,	0x8ebf,	0x3bd2,	0x8ed6,	0x3bfe,	0x8eee,	0x3c2a,	0x8f06,
+	0x3c57,	0x8f1d,	0x3c83,	0x8f35,	0x3caf,	0x8f4d,	0x3cdc,	0x8f65,
+	0x3d08,	0x8f7d,	0x3d34,	0x8f95,	0x3d60,	0x8fad,	0x3d8c,	0x8fc5,
+	0x3db8,	0x8fdd,	0x3de4,	0x8ff5,	0x3e10,	0x900e,	0x3e3c,	0x9026,
+	0x3e68,	0x903e,	0x3e94,	0x9057,	0x3ec0,	0x9070,	0x3eec,	0x9088,
+	0x3f17,	0x90a1,	0x3f43,	0x90ba,	0x3f6f,	0x90d3,	0x3f9a,	0x90ec,
+	0x3fc6,	0x9105,	0x3ff1,	0x911e,	0x401d,	0x9137,	0x4048,	0x9150,
+	0x4074,	0x9169,	0x409f,	0x9183,	0x40cb,	0x919c,	0x40f6,	0x91b6,
+	0x4121,	0x91cf,	0x414d,	0x91e9,	0x4178,	0x9202,	0x41a3,	0x921c,
+	0x41ce,	0x9236,	0x41f9,	0x9250,	0x4224,	0x926a,	0x424f,	0x9284,
+	0x427a,	0x929e,	0x42a5,	0x92b8,	0x42d0,	0x92d2,	0x42fb,	0x92ec,
+	0x4326,	0x9307,	0x4351,	0x9321,	0x437b,	0x933c,	0x43a6,	0x9356,
+	0x43d1,	0x9371,	0x43fb,	0x938b,	0x4426,	0x93a6,	0x4450,	0x93c1,
+	0x447b,	0x93dc,	0x44a5,	0x93f7,	0x44d0,	0x9412,	0x44fa,	0x942d,
+	0x4524,	0x9448,	0x454f,	0x9463,	0x4579,	0x947e,	0x45a3,	0x949a,
+	0x45cd,	0x94b5,	0x45f7,	0x94d0,	0x4621,	0x94ec,	0x464b,	0x9508,
+	0x4675,	0x9523,	0x469f,	0x953f,	0x46c9,	0x955b,	0x46f3,	0x9577,
+	0x471d,	0x9592,	0x4747,	0x95ae,	0x4770,	0x95ca,	0x479a,	0x95e6,
+	0x47c4,	0x9603,	0x47ed,	0x961f,	0x4817,	0x963b,	0x4840,	0x9657,
+	0x486a,	0x9674,	0x4893,	0x9690,	0x48bd,	0x96ad,	0x48e6,	0x96c9,
+	0x490f,	0x96e6,	0x4939,	0x9703,	0x4962,	0x9720,	0x498b,	0x973c,
+	0x49b4,	0x9759,	0x49dd,	0x9776,	0x4a06,	0x9793,	0x4a2f,	0x97b0,
+	0x4a58,	0x97ce,	0x4a81,	0x97eb,	0x4aaa,	0x9808,	0x4ad3,	0x9826,
+	0x4afb,	0x9843,	0x4b24,	0x9860,	0x4b4d,	0x987e,	0x4b75,	0x989c,
+	0x4b9e,	0x98b9,	0x4bc7,	0x98d7,	0x4bef,	0x98f5,	0x4c17,	0x9913,
+	0x4c40,	0x9930,	0x4c68,	0x994e,	0x4c91,	0x996d,	0x4cb9,	0x998b,
+	0x4ce1,	0x99a9,	0x4d09,	0x99c7,	0x4d31,	0x99e5,	0x4d59,	0x9a04,
+	0x4d81,	0x9a22,	0x4da9,	0x9a40,	0x4dd1,	0x9a5f,	0x4df9,	0x9a7e,
+	0x4e21,	0x9a9c,	0x4e49,	0x9abb,	0x4e71,	0x9ada,	0x4e98,	0x9af9,
+	0x4ec0,	0x9b17,	0x4ee8,	0x9b36,	0x4f0f,	0x9b55,	0x4f37,	0x9b75,
+	0x4f5e,	0x9b94,	0x4f85,	0x9bb3,	0x4fad,	0x9bd2,	0x4fd4,	0x9bf1,
+	0x4ffb,	0x9c11,	0x5023,	0x9c30,	0x504a,	0x9c50,	0x5071,	0x9c6f,
+	0x5098,	0x9c8f,	0x50bf,	0x9caf,	0x50e6,	0x9cce,	0x510d,	0x9cee,
+	0x5134,	0x9d0e,	0x515b,	0x9d2e,	0x5181,	0x9d4e,	0x51a8,	0x9d6e,
+	0x51cf,	0x9d8e,	0x51f5,	0x9dae,	0x521c,	0x9dce,	0x5243,	0x9def,
+	0x5269,	0x9e0f,	0x5290,	0x9e2f,	0x52b6,	0x9e50,	0x52dc,	0x9e70,
+	0x5303,	0x9e91,	0x5329,	0x9eb2,	0x534f,	0x9ed2,	0x5375,	0x9ef3,
+	0x539b,	0x9f14,	0x53c1,	0x9f35,	0x53e7,	0x9f56,	0x540d,	0x9f77,
+	0x5433,	0x9f98,	0x5459,	0x9fb9,	0x547f,	0x9fda,	0x54a4,	0x9ffb,
+	0x54ca,	0xa01c,	0x54f0,	0xa03e,	0x5515,	0xa05f,	0x553b,	0xa080,
+	0x5560,	0xa0a2,	0x5586,	0xa0c4,	0x55ab,	0xa0e5,	0x55d0,	0xa107,
+	0x55f6,	0xa129,	0x561b,	0xa14a,	0x5640,	0xa16c,	0x5665,	0xa18e,
+	0x568a,	0xa1b0,	0x56af,	0xa1d2,	0x56d4,	0xa1f4,	0x56f9,	0xa216,
+	0x571e,	0xa238,	0x5743,	0xa25b,	0x5767,	0xa27d,	0x578c,	0xa29f,
+	0x57b1,	0xa2c2,	0x57d5,	0xa2e4,	0x57fa,	0xa307,	0x581e,	0xa329,
+	0x5843,	0xa34c,	0x5867,	0xa36f,	0x588c,	0xa391,	0x58b0,	0xa3b4,
+	0x58d4,	0xa3d7,	0x58f8,	0xa3fa,	0x591c,	0xa41d,	0x5940,	0xa440,
+	0x5964,	0xa463,	0x5988,	0xa486,	0x59ac,	0xa4a9,	0x59d0,	0xa4cc,
+	0x59f4,	0xa4f0,	0x5a18,	0xa513,	0x5a3b,	0xa537,	0x5a5f,	0xa55a,
+	0x5a82,	0xa57e,	0x5aa6,	0xa5a1,	0x5ac9,	0xa5c5,	0x5aed,	0xa5e8,
+	0x5b10,	0xa60c,	0x5b34,	0xa630,	0x5b57,	0xa654,	0x5b7a,	0xa678,
+	0x5b9d,	0xa69c,	0x5bc0,	0xa6c0,	0x5be3,	0xa6e4,	0x5c06,	0xa708,
+	0x5c29,	0xa72c,	0x5c4c,	0xa750,	0x5c6f,	0xa774,	0x5c91,	0xa799,
+	0x5cb4,	0xa7bd,	0x5cd7,	0xa7e2,	0x5cf9,	0xa806,	0x5d1c,	0xa82b,
+	0x5d3e,	0xa84f,	0x5d61,	0xa874,	0x5d83,	0xa899,	0x5da5,	0xa8bd,
+	0x5dc8,	0xa8e2,	0x5dea,	0xa907,	0x5e0c,	0xa92c,	0x5e2e,	0xa951,
+	0x5e50,	0xa976,	0x5e72,	0xa99b,	0x5e94,	0xa9c0,	0x5eb6,	0xa9e5,
+	0x5ed7,	0xaa0a,	0x5ef9,	0xaa30,	0x5f1b,	0xaa55,	0x5f3c,	0xaa7a,
+	0x5f5e,	0xaaa0,	0x5f80,	0xaac5,	0x5fa1,	0xaaeb,	0x5fc2,	0xab10,
+	0x5fe4,	0xab36,	0x6005,	0xab5c,	0x6026,	0xab81,	0x6047,	0xaba7,
+	0x6068,	0xabcd,	0x6089,	0xabf3,	0x60aa,	0xac19,	0x60cb,	0xac3f,
+	0x60ec,	0xac65,	0x610d,	0xac8b,	0x612e,	0xacb1,	0x614e,	0xacd7,
+	0x616f,	0xacfd,	0x6190,	0xad24,	0x61b0,	0xad4a,	0x61d1,	0xad70,
+	0x61f1,	0xad97,	0x6211,	0xadbd,	0x6232,	0xade4,	0x6252,	0xae0b,
+	0x6272,	0xae31,	0x6292,	0xae58,	0x62b2,	0xae7f,	0x62d2,	0xaea5,
+	0x62f2,	0xaecc,	0x6312,	0xaef3,	0x6332,	0xaf1a,	0x6351,	0xaf41,
+	0x6371,	0xaf68,	0x6391,	0xaf8f,	0x63b0,	0xafb6,	0x63d0,	0xafdd,
+	0x63ef,	0xb005,	0x640f,	0xb02c,	0x642e,	0xb053,	0x644d,	0xb07b,
+	0x646c,	0xb0a2,	0x648b,	0xb0c9,	0x64ab,	0xb0f1,	0x64ca,	0xb118,
+	0x64e9,	0xb140,	0x6507,	0xb168,	0x6526,	0xb18f,	0x6545,	0xb1b7,
+	0x6564,	0xb1df,	0x6582,	0xb207,	0x65a1,	0xb22f,	0x65c0,	0xb257,
+	0x65de,	0xb27f,	0x65fc,	0xb2a7,	0x661b,	0xb2cf,	0x6639,	0xb2f7,
+	0x6657,	0xb31f,	0x6675,	0xb347,	0x6693,	0xb36f,	0x66b2,	0xb398,
+	0x66d0,	0xb3c0,	0x66ed,	0xb3e9,	0x670b,	0xb411,	0x6729,	0xb439,
+	0x6747,	0xb462,	0x6764,	0xb48b,	0x6782,	0xb4b3,	0x67a0,	0xb4dc,
+	0x67bd,	0xb505,	0x67da,	0xb52d,	0x67f8,	0xb556,	0x6815,	0xb57f,
+	0x6832,	0xb5a8,	0x6850,	0xb5d1,	0x686d,	0xb5fa,	0x688a,	0xb623,
+	0x68a7,	0xb64c,	0x68c4,	0xb675,	0x68e0,	0xb69e,	0x68fd,	0xb6c7,
+	0x691a,	0xb6f1,	0x6937,	0xb71a,	0x6953,	0xb743,	0x6970,	0xb76d,
+	0x698c,	0xb796,	0x69a9,	0xb7c0,	0x69c5,	0xb7e9,	0x69e1,	0xb813,
+	0x69fd,	0xb83c,	0x6a1a,	0xb866,	0x6a36,	0xb890,	0x6a52,	0xb8b9,
+	0x6a6e,	0xb8e3,	0x6a89,	0xb90d,	0x6aa5,	0xb937,	0x6ac1,	0xb961,
+	0x6add,	0xb98b,	0x6af8,	0xb9b5,	0x6b14,	0xb9df,	0x6b30,	0xba09,
+	0x6b4b,	0xba33,	0x6b66,	0xba5d,	0x6b82,	0xba87,	0x6b9d,	0xbab1,
+	0x6bb8,	0xbadc,	0x6bd3,	0xbb06,	0x6bee,	0xbb30,	0x6c09,	0xbb5b,
+	0x6c24,	0xbb85,	0x6c3f,	0xbbb0,	0x6c5a,	0xbbda,	0x6c75,	0xbc05,
+	0x6c8f,	0xbc2f,	0x6caa,	0xbc5a,	0x6cc4,	0xbc85,	0x6cdf,	0xbcaf,
+	0x6cf9,	0xbcda,	0x6d14,	0xbd05,	0x6d2e,	0xbd30,	0x6d48,	0xbd5b,
+	0x6d62,	0xbd86,	0x6d7c,	0xbdb1,	0x6d96,	0xbddc,	0x6db0,	0xbe07,
+	0x6dca,	0xbe32,	0x6de4,	0xbe5d,	0x6dfe,	0xbe88,	0x6e17,	0xbeb3,
+	0x6e31,	0xbedf,	0x6e4a,	0xbf0a,	0x6e64,	0xbf35,	0x6e7d,	0xbf61,
+	0x6e97,	0xbf8c,	0x6eb0,	0xbfb8,	0x6ec9,	0xbfe3,	0x6ee2,	0xc00f,
+	0x6efb,	0xc03a,	0x6f14,	0xc066,	0x6f2d,	0xc091,	0x6f46,	0xc0bd,
+	0x6f5f,	0xc0e9,	0x6f78,	0xc114,	0x6f90,	0xc140,	0x6fa9,	0xc16c,
+	0x6fc2,	0xc198,	0x6fda,	0xc1c4,	0x6ff2,	0xc1f0,	0x700b,	0xc21c,
+	0x7023,	0xc248,	0x703b,	0xc274,	0x7053,	0xc2a0,	0x706b,	0xc2cc,
+	0x7083,	0xc2f8,	0x709b,	0xc324,	0x70b3,	0xc351,	0x70cb,	0xc37d,
+	0x70e3,	0xc3a9,	0x70fa,	0xc3d6,	0x7112,	0xc402,	0x712a,	0xc42e,
+	0x7141,	0xc45b,	0x7158,	0xc487,	0x7170,	0xc4b4,	0x7187,	0xc4e0,
+	0x719e,	0xc50d,	0x71b5,	0xc53a,	0x71cc,	0xc566,	0x71e3,	0xc593,
+	0x71fa,	0xc5c0,	0x7211,	0xc5ed,	0x7228,	0xc619,	0x723f,	0xc646,
+	0x7255,	0xc673,	0x726c,	0xc6a0,	0x7282,	0xc6cd,	0x7299,	0xc6fa,
+	0x72af,	0xc727,	0x72c5,	0xc754,	0x72dc,	0xc781,	0x72f2,	0xc7ae,
+	0x7308,	0xc7db,	0x731e,	0xc809,	0x7334,	0xc836,	0x734a,	0xc863,
+	0x735f,	0xc890,	0x7375,	0xc8be,	0x738b,	0xc8eb,	0x73a0,	0xc918,
+	0x73b6,	0xc946,	0x73cb,	0xc973,	0x73e1,	0xc9a1,	0x73f6,	0xc9ce,
+	0x740b,	0xc9fc,	0x7421,	0xca29,	0x7436,	0xca57,	0x744b,	0xca85,
+	0x7460,	0xcab2,	0x7475,	0xcae0,	0x7489,	0xcb0e,	0x749e,	0xcb3c,
+	0x74b3,	0xcb69,	0x74c7,	0xcb97,	0x74dc,	0xcbc5,	0x74f0,	0xcbf3,
+	0x7505,	0xcc21,	0x7519,	0xcc4f,	0x752d,	0xcc7d,	0x7542,	0xccab,
+	0x7556,	0xccd9,	0x756a,	0xcd07,	0x757e,	0xcd35,	0x7592,	0xcd63,
+	0x75a6,	0xcd92,	0x75b9,	0xcdc0,	0x75cd,	0xcdee,	0x75e1,	0xce1c,
+	0x75f4,	0xce4b,	0x7608,	0xce79,	0x761b,	0xcea7,	0x762e,	0xced6,
+	0x7642,	0xcf04,	0x7655,	0xcf33,	0x7668,	0xcf61,	0x767b,	0xcf90,
+	0x768e,	0xcfbe,	0x76a1,	0xcfed,	0x76b4,	0xd01b,	0x76c7,	0xd04a,
+	0x76d9,	0xd079,	0x76ec,	0xd0a7,	0x76fe,	0xd0d6,	0x7711,	0xd105,
+	0x7723,	0xd134,	0x7736,	0xd162,	0x7748,	0xd191,	0x775a,	0xd1c0,
+	0x776c,	0xd1ef,	0x777e,	0xd21e,	0x7790,	0xd24d,	0x77a2,	0xd27c,
+	0x77b4,	0xd2ab,	0x77c6,	0xd2da,	0x77d8,	0xd309,	0x77e9,	0xd338,
+	0x77fb,	0xd367,	0x780c,	0xd396,	0x781e,	0xd3c5,	0x782f,	0xd3f4,
+	0x7840,	0xd424,	0x7851,	0xd453,	0x7863,	0xd482,	0x7874,	0xd4b1,
+	0x7885,	0xd4e1,	0x7895,	0xd510,	0x78a6,	0xd53f,	0x78b7,	0xd56f,
+	0x78c8,	0xd59e,	0x78d8,	0xd5ce,	0x78e9,	0xd5fd,	0x78f9,	0xd62d,
+	0x790a,	0xd65c,	0x791a,	0xd68c,	0x792a,	0xd6bb,	0x793a,	0xd6eb,
+	0x794a,	0xd71b,	0x795b,	0xd74a,	0x796a,	0xd77a,	0x797a,	0xd7aa,
+	0x798a,	0xd7d9,	0x799a,	0xd809,	0x79aa,	0xd839,	0x79b9,	0xd869,
+	0x79c9,	0xd898,	0x79d8,	0xd8c8,	0x79e7,	0xd8f8,	0x79f7,	0xd928,
+	0x7a06,	0xd958,	0x7a15,	0xd988,	0x7a24,	0xd9b8,	0x7a33,	0xd9e8,
+	0x7a42,	0xda18,	0x7a51,	0xda48,	0x7a60,	0xda78,	0x7a6e,	0xdaa8,
+	0x7a7d,	0xdad8,	0x7a8c,	0xdb08,	0x7a9a,	0xdb38,	0x7aa8,	0xdb68,
+	0x7ab7,	0xdb99,	0x7ac5,	0xdbc9,	0x7ad3,	0xdbf9,	0x7ae1,	0xdc29,
+	0x7aef,	0xdc59,	0x7afd,	0xdc8a,	0x7b0b,	0xdcba,	0x7b19,	0xdcea,
+	0x7b27,	0xdd1b,	0x7b34,	0xdd4b,	0x7b42,	0xdd7c,	0x7b50,	0xddac,
+	0x7b5d,	0xdddc,	0x7b6a,	0xde0d,	0x7b78,	0xde3d,	0x7b85,	0xde6e,
+	0x7b92,	0xde9e,	0x7b9f,	0xdecf,	0x7bac,	0xdeff,	0x7bb9,	0xdf30,
+	0x7bc6,	0xdf61,	0x7bd3,	0xdf91,	0x7bdf,	0xdfc2,	0x7bec,	0xdff2,
+	0x7bf9,	0xe023,	0x7c05,	0xe054,	0x7c11,	0xe085,	0x7c1e,	0xe0b5,
+	0x7c2a,	0xe0e6,	0x7c36,	0xe117,	0x7c42,	0xe148,	0x7c4e,	0xe178,
+	0x7c5a,	0xe1a9,	0x7c66,	0xe1da,	0x7c72,	0xe20b,	0x7c7e,	0xe23c,
+	0x7c89,	0xe26d,	0x7c95,	0xe29e,	0x7ca0,	0xe2cf,	0x7cac,	0xe2ff,
+	0x7cb7,	0xe330,	0x7cc2,	0xe361,	0x7cce,	0xe392,	0x7cd9,	0xe3c3,
+	0x7ce4,	0xe3f4,	0x7cef,	0xe426,	0x7cfa,	0xe457,	0x7d05,	0xe488,
+	0x7d0f,	0xe4b9,	0x7d1a,	0xe4ea,	0x7d25,	0xe51b,	0x7d2f,	0xe54c,
+	0x7d3a,	0xe57d,	0x7d44,	0xe5af,	0x7d4e,	0xe5e0,	0x7d58,	0xe611,
+	0x7d63,	0xe642,	0x7d6d,	0xe673,	0x7d77,	0xe6a5,	0x7d81,	0xe6d6,
+	0x7d8a,	0xe707,	0x7d94,	0xe739,	0x7d9e,	0xe76a,	0x7da7,	0xe79b,
+	0x7db1,	0xe7cd,	0x7dba,	0xe7fe,	0x7dc4,	0xe82f,	0x7dcd,	0xe861,
+	0x7dd6,	0xe892,	0x7de0,	0xe8c4,	0x7de9,	0xe8f5,	0x7df2,	0xe926,
+	0x7dfb,	0xe958,	0x7e03,	0xe989,	0x7e0c,	0xe9bb,	0x7e15,	0xe9ec,
+	0x7e1e,	0xea1e,	0x7e26,	0xea4f,	0x7e2f,	0xea81,	0x7e37,	0xeab3,
+	0x7e3f,	0xeae4,	0x7e48,	0xeb16,	0x7e50,	0xeb47,	0x7e58,	0xeb79,
+	0x7e60,	0xebab,	0x7e68,	0xebdc,	0x7e70,	0xec0e,	0x7e78,	0xec3f,
+	0x7e7f,	0xec71,	0x7e87,	0xeca3,	0x7e8e,	0xecd5,	0x7e96,	0xed06,
+	0x7e9d,	0xed38,	0x7ea5,	0xed6a,	0x7eac,	0xed9b,	0x7eb3,	0xedcd,
+	0x7eba,	0xedff,	0x7ec1,	0xee31,	0x7ec8,	0xee62,	0x7ecf,	0xee94,
+	0x7ed6,	0xeec6,	0x7edd,	0xeef8,	0x7ee3,	0xef2a,	0x7eea,	0xef5c,
+	0x7ef0,	0xef8d,	0x7ef7,	0xefbf,	0x7efd,	0xeff1,	0x7f03,	0xf023,
+	0x7f0a,	0xf055,	0x7f10,	0xf087,	0x7f16,	0xf0b9,	0x7f1c,	0xf0eb,
+	0x7f22,	0xf11c,	0x7f27,	0xf14e,	0x7f2d,	0xf180,	0x7f33,	0xf1b2,
+	0x7f38,	0xf1e4,	0x7f3e,	0xf216,	0x7f43,	0xf248,	0x7f49,	0xf27a,
+	0x7f4e,	0xf2ac,	0x7f53,	0xf2de,	0x7f58,	0xf310,	0x7f5d,	0xf342,
+	0x7f62,	0xf374,	0x7f67,	0xf3a6,	0x7f6c,	0xf3d8,	0x7f71,	0xf40a,
+	0x7f75,	0xf43c,	0x7f7a,	0xf46e,	0x7f7e,	0xf4a0,	0x7f83,	0xf4d3,
+	0x7f87,	0xf505,	0x7f8b,	0xf537,	0x7f90,	0xf569,	0x7f94,	0xf59b,
+	0x7f98,	0xf5cd,	0x7f9c,	0xf5ff,	0x7fa0,	0xf631,	0x7fa3,	0xf663,
+	0x7fa7,	0xf695,	0x7fab,	0xf6c8,	0x7fae,	0xf6fa,	0x7fb2,	0xf72c,
+	0x7fb5,	0xf75e,	0x7fb9,	0xf790,	0x7fbc,	0xf7c2,	0x7fbf,	0xf7f4,
+	0x7fc2,	0xf827,	0x7fc5,	0xf859,	0x7fc8,	0xf88b,	0x7fcb,	0xf8bd,
+	0x7fce,	0xf8ef,	0x7fd1,	0xf922,	0x7fd3,	0xf954,	0x7fd6,	0xf986,
+	0x7fd9,	0xf9b8,	0x7fdb,	0xf9ea,	0x7fdd,	0xfa1d,	0x7fe0,	0xfa4f,
+	0x7fe2,	0xfa81,	0x7fe4,	0xfab3,	0x7fe6,	0xfae5,	0x7fe8,	0xfb18,
+	0x7fea,	0xfb4a,	0x7fec,	0xfb7c,	0x7fed,	0xfbae,	0x7fef,	0xfbe1,
+	0x7ff1,	0xfc13,	0x7ff2,	0xfc45,	0x7ff4,	0xfc77,	0x7ff5,	0xfcaa,
+	0x7ff6,	0xfcdc,	0x7ff7,	0xfd0e,	0x7ff8,	0xfd40,	0x7ff9,	0xfd73,
+	0x7ffa,	0xfda5,	0x7ffb,	0xfdd7,	0x7ffc,	0xfe09,	0x7ffd,	0xfe3c,
+	0x7ffe,	0xfe6e,	0x7ffe,	0xfea0,	0x7fff,	0xfed2,	0x7fff,	0xff05,
+	0x7fff,	0xff37,	0x7fff,	0xff69,	0x7fff,	0xff9b,	0x7fff,	0xffce
+};
+
+
+/**   
+* @brief Initialization function for the Q15 CFFT/CIFFT.  
+* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.  
+* @param[in]     fftLen         length of the FFT.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+
+arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q15_t *) twiddleCoefQ15;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+  case 4096u:
+    /*  Initializations of structure parameters for 4096 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = armBitRevTable;
+
+    break;
+	
+  case 1024u:
+    /*  Initializations of structure parameters for 1024 point FFT */
+    S->twidCoefModifier = 4u;
+    S->bitRevFactor = 4u;
+    S->pBitRevTable = &armBitRevTable[3];
+
+    break;
+	
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = &armBitRevTable[15];
+
+    break;
+	
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = &armBitRevTable[63];
+
+    break;
+	
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = &armBitRevTable[255];
+
+    break;
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
new file mode 100644
index 0000000..fb12905
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
@@ -0,0 +1,1197 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_init_q31.c   
+*   
+* Description:	Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+* 
+** Version 1.0.11 2011/08/17 
+*    Updated to support 4096 CFFT length.  
+*
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/*   
+* @brief  Twiddle factors Table   
+*/
+
+/**   
+* \par  
+* Example code for Q31 Twiddle factors Generation::   
+* \par   
+* 
for(i = 0; i< N; i++)   
+* {   
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);   
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);   
+* } 
   
+* \par   
+* where N = 1024	and PI = 3.14159265358979   
+* \par   
+* Cos and Sin values are interleaved fashion   
+* \par   
+* Convert Floating point to Q31(Fixed point 1.31):   
+*	round(twiddleCoefQ31(i) * pow(2, 31))   
+*   
+*/
+
+static const q31_t twiddleCoefQ31[4096*2] = {
+  0x7fffffff,	0x0,	0x7ffff621,	0x3243f5,	0x7fffd886,	0x6487e3,	0x7fffa72c,	0x96cbc1,
+	0x7fff6216,	0xc90f88,	0x7fff0943,	0xfb5330,	0x7ffe9cb2,	0x12d96b1,	0x7ffe1c65,	0x15fda03,
+	0x7ffd885a,	0x1921d20,	0x7ffce093,	0x1c45ffe,	0x7ffc250f,	0x1f6a297,	0x7ffb55ce,	0x228e4e2,
+	0x7ffa72d1,	0x25b26d7,	0x7ff97c18,	0x28d6870,	0x7ff871a2,	0x2bfa9a4,	0x7ff75370,	0x2f1ea6c,
+	0x7ff62182,	0x3242abf,	0x7ff4dbd9,	0x3566a96,	0x7ff38274,	0x388a9ea,	0x7ff21553,	0x3bae8b2,
+	0x7ff09478,	0x3ed26e6,	0x7feeffe1,	0x41f6480,	0x7fed5791,	0x451a177,	0x7feb9b85,	0x483ddc3,
+	0x7fe9cbc0,	0x4b6195d,	0x7fe7e841,	0x4e8543e,	0x7fe5f108,	0x51a8e5c,	0x7fe3e616,	0x54cc7b1,
+	0x7fe1c76b,	0x57f0035,	0x7fdf9508,	0x5b137df,	0x7fdd4eec,	0x5e36ea9,	0x7fdaf519,	0x615a48b,
+	0x7fd8878e,	0x647d97c,	0x7fd6064c,	0x67a0d76,	0x7fd37153,	0x6ac406f,	0x7fd0c8a3,	0x6de7262,
+	0x7fce0c3e,	0x710a345,	0x7fcb3c23,	0x742d311,	0x7fc85854,	0x77501be,	0x7fc560cf,	0x7a72f45,
+	0x7fc25596,	0x7d95b9e,	0x7fbf36aa,	0x80b86c2,	0x7fbc040a,	0x83db0a7,	0x7fb8bdb8,	0x86fd947,
+	0x7fb563b3,	0x8a2009a,	0x7fb1f5fc,	0x8d42699,	0x7fae7495,	0x9064b3a,	0x7faadf7c,	0x9386e78,
+	0x7fa736b4,	0x96a9049,	0x7fa37a3c,	0x99cb0a7,	0x7f9faa15,	0x9cecf89,	0x7f9bc640,	0xa00ece8,
+	0x7f97cebd,	0xa3308bd,	0x7f93c38c,	0xa6522fe,	0x7f8fa4b0,	0xa973ba5,	0x7f8b7227,	0xac952aa,
+	0x7f872bf3,	0xafb6805,	0x7f82d214,	0xb2d7baf,	0x7f7e648c,	0xb5f8d9f,	0x7f79e35a,	0xb919dcf,
+	0x7f754e80,	0xbc3ac35,	0x7f70a5fe,	0xbf5b8cb,	0x7f6be9d4,	0xc27c389,	0x7f671a05,	0xc59cc68,
+	0x7f62368f,	0xc8bd35e,	0x7f5d3f75,	0xcbdd865,	0x7f5834b7,	0xcefdb76,	0x7f531655,	0xd21dc87,
+	0x7f4de451,	0xd53db92,	0x7f489eaa,	0xd85d88f,	0x7f434563,	0xdb7d376,	0x7f3dd87c,	0xde9cc40,
+	0x7f3857f6,	0xe1bc2e4,	0x7f32c3d1,	0xe4db75b,	0x7f2d1c0e,	0xe7fa99e,	0x7f2760af,	0xeb199a4,
+	0x7f2191b4,	0xee38766,	0x7f1baf1e,	0xf1572dc,	0x7f15b8ee,	0xf475bff,	0x7f0faf25,	0xf7942c7,
+	0x7f0991c4,	0xfab272b,	0x7f0360cb,	0xfdd0926,	0x7efd1c3c,	0x100ee8ad,	0x7ef6c418,	0x1040c5bb,
+	0x7ef05860,	0x1072a048,	0x7ee9d914,	0x10a4784b,	0x7ee34636,	0x10d64dbd,	0x7edc9fc6,	0x11082096,
+	0x7ed5e5c6,	0x1139f0cf,	0x7ecf1837,	0x116bbe60,	0x7ec8371a,	0x119d8941,	0x7ec14270,	0x11cf516a,
+	0x7eba3a39,	0x120116d5,	0x7eb31e78,	0x1232d979,	0x7eabef2c,	0x1264994e,	0x7ea4ac58,	0x1296564d,
+	0x7e9d55fc,	0x12c8106f,	0x7e95ec1a,	0x12f9c7aa,	0x7e8e6eb2,	0x132b7bf9,	0x7e86ddc6,	0x135d2d53,
+	0x7e7f3957,	0x138edbb1,	0x7e778166,	0x13c0870a,	0x7e6fb5f4,	0x13f22f58,	0x7e67d703,	0x1423d492,
+	0x7e5fe493,	0x145576b1,	0x7e57dea7,	0x148715ae,	0x7e4fc53e,	0x14b8b17f,	0x7e47985b,	0x14ea4a1f,
+	0x7e3f57ff,	0x151bdf86,	0x7e37042a,	0x154d71aa,	0x7e2e9cdf,	0x157f0086,	0x7e26221f,	0x15b08c12,
+	0x7e1d93ea,	0x15e21445,	0x7e14f242,	0x16139918,	0x7e0c3d29,	0x16451a83,	0x7e0374a0,	0x1676987f,
+	0x7dfa98a8,	0x16a81305,	0x7df1a942,	0x16d98a0c,	0x7de8a670,	0x170afd8d,	0x7ddf9034,	0x173c6d80,
+	0x7dd6668f,	0x176dd9de,	0x7dcd2981,	0x179f429f,	0x7dc3d90d,	0x17d0a7bc,	0x7dba7534,	0x1802092c,
+	0x7db0fdf8,	0x183366e9,	0x7da77359,	0x1864c0ea,	0x7d9dd55a,	0x18961728,	0x7d9423fc,	0x18c7699b,
+	0x7d8a5f40,	0x18f8b83c,	0x7d808728,	0x192a0304,	0x7d769bb5,	0x195b49ea,	0x7d6c9ce9,	0x198c8ce7,
+	0x7d628ac6,	0x19bdcbf3,	0x7d58654d,	0x19ef0707,	0x7d4e2c7f,	0x1a203e1b,	0x7d43e05e,	0x1a517128,
+	0x7d3980ec,	0x1a82a026,	0x7d2f0e2b,	0x1ab3cb0d,	0x7d24881b,	0x1ae4f1d6,	0x7d19eebf,	0x1b161479,
+	0x7d0f4218,	0x1b4732ef,	0x7d048228,	0x1b784d30,	0x7cf9aef0,	0x1ba96335,	0x7ceec873,	0x1bda74f6,
+	0x7ce3ceb2,	0x1c0b826a,	0x7cd8c1ae,	0x1c3c8b8c,	0x7ccda169,	0x1c6d9053,	0x7cc26de5,	0x1c9e90b8,
+	0x7cb72724,	0x1ccf8cb3,	0x7cabcd28,	0x1d00843d,	0x7ca05ff1,	0x1d31774d,	0x7c94df83,	0x1d6265dd,
+	0x7c894bde,	0x1d934fe5,	0x7c7da505,	0x1dc4355e,	0x7c71eaf9,	0x1df5163f,	0x7c661dbc,	0x1e25f282,
+	0x7c5a3d50,	0x1e56ca1e,	0x7c4e49b7,	0x1e879d0d,	0x7c4242f2,	0x1eb86b46,	0x7c362904,	0x1ee934c3,
+	0x7c29fbee,	0x1f19f97b,	0x7c1dbbb3,	0x1f4ab968,	0x7c116853,	0x1f7b7481,	0x7c0501d2,	0x1fac2abf,
+	0x7bf88830,	0x1fdcdc1b,	0x7bebfb70,	0x200d888d,	0x7bdf5b94,	0x203e300d,	0x7bd2a89e,	0x206ed295,
+	0x7bc5e290,	0x209f701c,	0x7bb9096b,	0x20d0089c,	0x7bac1d31,	0x21009c0c,	0x7b9f1de6,	0x21312a65,
+	0x7b920b89,	0x2161b3a0,	0x7b84e61f,	0x219237b5,	0x7b77ada8,	0x21c2b69c,	0x7b6a6227,	0x21f3304f,
+	0x7b5d039e,	0x2223a4c5,	0x7b4f920e,	0x225413f8,	0x7b420d7a,	0x22847de0,	0x7b3475e5,	0x22b4e274,
+	0x7b26cb4f,	0x22e541af,	0x7b190dbc,	0x23159b88,	0x7b0b3d2c,	0x2345eff8,	0x7afd59a4,	0x23763ef7,
+	0x7aef6323,	0x23a6887f,	0x7ae159ae,	0x23d6cc87,	0x7ad33d45,	0x24070b08,	0x7ac50dec,	0x243743fa,
+	0x7ab6cba4,	0x24677758,	0x7aa8766f,	0x2497a517,	0x7a9a0e50,	0x24c7cd33,	0x7a8b9348,	0x24f7efa2,
+	0x7a7d055b,	0x25280c5e,	0x7a6e648a,	0x2558235f,	0x7a5fb0d8,	0x2588349d,	0x7a50ea47,	0x25b84012,
+	0x7a4210d8,	0x25e845b6,	0x7a332490,	0x26184581,	0x7a24256f,	0x26483f6c,	0x7a151378,	0x26783370,
+	0x7a05eead,	0x26a82186,	0x79f6b711,	0x26d809a5,	0x79e76ca7,	0x2707ebc7,	0x79d80f6f,	0x2737c7e3,
+	0x79c89f6e,	0x27679df4,	0x79b91ca4,	0x27976df1,	0x79a98715,	0x27c737d3,	0x7999dec4,	0x27f6fb92,
+	0x798a23b1,	0x2826b928,	0x797a55e0,	0x2856708d,	0x796a7554,	0x288621b9,	0x795a820e,	0x28b5cca5,
+	0x794a7c12,	0x28e5714b,	0x793a6361,	0x29150fa1,	0x792a37fe,	0x2944a7a2,	0x7919f9ec,	0x29743946,
+	0x7909a92d,	0x29a3c485,	0x78f945c3,	0x29d34958,	0x78e8cfb2,	0x2a02c7b8,	0x78d846fb,	0x2a323f9e,
+	0x78c7aba2,	0x2a61b101,	0x78b6fda8,	0x2a911bdc,	0x78a63d11,	0x2ac08026,	0x789569df,	0x2aefddd8,
+	0x78848414,	0x2b1f34eb,	0x78738bb3,	0x2b4e8558,	0x786280bf,	0x2b7dcf17,	0x7851633b,	0x2bad1221,
+	0x78403329,	0x2bdc4e6f,	0x782ef08b,	0x2c0b83fa,	0x781d9b65,	0x2c3ab2b9,	0x780c33b8,	0x2c69daa6,
+	0x77fab989,	0x2c98fbba,	0x77e92cd9,	0x2cc815ee,	0x77d78daa,	0x2cf72939,	0x77c5dc01,	0x2d263596,
+	0x77b417df,	0x2d553afc,	0x77a24148,	0x2d843964,	0x7790583e,	0x2db330c7,	0x777e5cc3,	0x2de2211e,
+	0x776c4edb,	0x2e110a62,	0x775a2e89,	0x2e3fec8b,	0x7747fbce,	0x2e6ec792,	0x7735b6af,	0x2e9d9b70,
+	0x77235f2d,	0x2ecc681e,	0x7710f54c,	0x2efb2d95,	0x76fe790e,	0x2f29ebcc,	0x76ebea77,	0x2f58a2be,
+	0x76d94989,	0x2f875262,	0x76c69647,	0x2fb5fab2,	0x76b3d0b4,	0x2fe49ba7,	0x76a0f8d2,	0x30133539,
+	0x768e0ea6,	0x3041c761,	0x767b1231,	0x30705217,	0x76680376,	0x309ed556,	0x7654e279,	0x30cd5115,
+	0x7641af3d,	0x30fbc54d,	0x762e69c4,	0x312a31f8,	0x761b1211,	0x3158970e,	0x7607a828,	0x3186f487,
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+	0x8058c94c,	0x96a9049,	0x80552084,	0x9386e78,	0x80518b6b,	0x9064b3a,	0x804e0a04,	0x8d42699,
+	0x804a9c4d,	0x8a2009a,	0x80474248,	0x86fd947,	0x8043fbf6,	0x83db0a7,	0x8040c956,	0x80b86c2,
+	0x803daa6a,	0x7d95b9e,	0x803a9f31,	0x7a72f45,	0x8037a7ac,	0x77501be,	0x8034c3dd,	0x742d311,
+	0x8031f3c2,	0x710a345,	0x802f375d,	0x6de7262,	0x802c8ead,	0x6ac406f,	0x8029f9b4,	0x67a0d76,
+	0x80277872,	0x647d97c,	0x80250ae7,	0x615a48b,	0x8022b114,	0x5e36ea9,	0x80206af8,	0x5b137df,
+	0x801e3895,	0x57f0035,	0x801c19ea,	0x54cc7b1,	0x801a0ef8,	0x51a8e5c,	0x801817bf,	0x4e8543e,
+	0x80163440,	0x4b6195d,	0x8014647b,	0x483ddc3,	0x8012a86f,	0x451a177,	0x8011001f,	0x41f6480,
+	0x800f6b88,	0x3ed26e6,	0x800deaad,	0x3bae8b2,	0x800c7d8c,	0x388a9ea,	0x800b2427,	0x3566a96,
+	0x8009de7e,	0x3242abf,	0x8008ac90,	0x2f1ea6c,	0x80078e5e,	0x2bfa9a4,	0x800683e8,	0x28d6870,
+	0x80058d2f,	0x25b26d7,	0x8004aa32,	0x228e4e2,	0x8003daf1,	0x1f6a297,	0x80031f6d,	0x1c45ffe,
+	0x800277a6,	0x1921d20,	0x8001e39b,	0x15fda03,	0x8001634e,	0x12d96b1,	0x8000f6bd,	0xfb5330,
+	0x80009dea,	0xc90f88,	0x800058d4,	0x96cbc1,	0x8000277a,	0x6487e3,	0x800009df,	0x3243f5,
+	0x80000000,	0x0,	0x800009df,	0xffcdbc0b,	0x8000277a,	0xff9b781d,	0x800058d4,	0xff69343f,
+	0x80009dea,	0xff36f078,	0x8000f6bd,	0xff04acd0,	0x8001634e,	0xfed2694f,	0x8001e39b,	0xfea025fd,
+	0x800277a6,	0xfe6de2e0,	0x80031f6d,	0xfe3ba002,	0x8003daf1,	0xfe095d69,	0x8004aa32,	0xfdd71b1e,
+	0x80058d2f,	0xfda4d929,	0x800683e8,	0xfd729790,	0x80078e5e,	0xfd40565c,	0x8008ac90,	0xfd0e1594,
+	0x8009de7e,	0xfcdbd541,	0x800b2427,	0xfca9956a,	0x800c7d8c,	0xfc775616,	0x800deaad,	0xfc45174e,
+	0x800f6b88,	0xfc12d91a,	0x8011001f,	0xfbe09b80,	0x8012a86f,	0xfbae5e89,	0x8014647b,	0xfb7c223d,
+	0x80163440,	0xfb49e6a3,	0x801817bf,	0xfb17abc2,	0x801a0ef8,	0xfae571a4,	0x801c19ea,	0xfab3384f,
+	0x801e3895,	0xfa80ffcb,	0x80206af8,	0xfa4ec821,	0x8022b114,	0xfa1c9157,	0x80250ae7,	0xf9ea5b75,
+	0x80277872,	0xf9b82684,	0x8029f9b4,	0xf985f28a,	0x802c8ead,	0xf953bf91,	0x802f375d,	0xf9218d9e,
+	0x8031f3c2,	0xf8ef5cbb,	0x8034c3dd,	0xf8bd2cef,	0x8037a7ac,	0xf88afe42,	0x803a9f31,	0xf858d0bb,
+	0x803daa6a,	0xf826a462,	0x8040c956,	0xf7f4793e,	0x8043fbf6,	0xf7c24f59,	0x80474248,	0xf79026b9,
+	0x804a9c4d,	0xf75dff66,	0x804e0a04,	0xf72bd967,	0x80518b6b,	0xf6f9b4c6,	0x80552084,	0xf6c79188,
+	0x8058c94c,	0xf6956fb7,	0x805c85c4,	0xf6634f59,	0x806055eb,	0xf6313077,	0x806439c0,	0xf5ff1318,
+	0x80683143,	0xf5ccf743,	0x806c3c74,	0xf59add02,	0x80705b50,	0xf568c45b,	0x80748dd9,	0xf536ad56,
+	0x8078d40d,	0xf50497fb,	0x807d2dec,	0xf4d28451,	0x80819b74,	0xf4a07261,	0x80861ca6,	0xf46e6231,
+	0x808ab180,	0xf43c53cb,	0x808f5a02,	0xf40a4735,	0x8094162c,	0xf3d83c77,	0x8098e5fb,	0xf3a63398,
+	0x809dc971,	0xf3742ca2,	0x80a2c08b,	0xf342279b,	0x80a7cb49,	0xf310248a,	0x80ace9ab,	0xf2de2379,
+	0x80b21baf,	0xf2ac246e,	0x80b76156,	0xf27a2771,	0x80bcba9d,	0xf2482c8a,	0x80c22784,	0xf21633c0,
+	0x80c7a80a,	0xf1e43d1c,	0x80cd3c2f,	0xf1b248a5,	0x80d2e3f2,	0xf1805662,	0x80d89f51,	0xf14e665c,
+	0x80de6e4c,	0xf11c789a,	0x80e450e2,	0xf0ea8d24,	0x80ea4712,	0xf0b8a401,	0x80f050db,	0xf086bd39,
+	0x80f66e3c,	0xf054d8d5,	0x80fc9f35,	0xf022f6da,	0x8102e3c4,	0xeff11753,	0x81093be8,	0xefbf3a45,
+	0x810fa7a0,	0xef8d5fb8,	0x811626ec,	0xef5b87b5,	0x811cb9ca,	0xef29b243,	0x8123603a,	0xeef7df6a,
+	0x812a1a3a,	0xeec60f31,	0x8130e7c9,	0xee9441a0,	0x8137c8e6,	0xee6276bf,	0x813ebd90,	0xee30ae96,
+	0x8145c5c7,	0xedfee92b,	0x814ce188,	0xedcd2687,	0x815410d4,	0xed9b66b2,	0x815b53a8,	0xed69a9b3,
+	0x8162aa04,	0xed37ef91,	0x816a13e6,	0xed063856,	0x8171914e,	0xecd48407,	0x8179223a,	0xeca2d2ad,
+	0x8180c6a9,	0xec71244f,	0x81887e9a,	0xec3f78f6,	0x81904a0c,	0xec0dd0a8,	0x819828fd,	0xebdc2b6e,
+	0x81a01b6d,	0xebaa894f,	0x81a82159,	0xeb78ea52,	0x81b03ac2,	0xeb474e81,	0x81b867a5,	0xeb15b5e1,
+	0x81c0a801,	0xeae4207a,	0x81c8fbd6,	0xeab28e56,	0x81d16321,	0xea80ff7a,	0x81d9dde1,	0xea4f73ee,
+	0x81e26c16,	0xea1debbb,	0x81eb0dbe,	0xe9ec66e8,	0x81f3c2d7,	0xe9bae57d,	0x81fc8b60,	0xe9896781,
+	0x82056758,	0xe957ecfb,	0x820e56be,	0xe92675f4,	0x82175990,	0xe8f50273,	0x82206fcc,	0xe8c39280,
+	0x82299971,	0xe8922622,	0x8232d67f,	0xe860bd61,	0x823c26f3,	0xe82f5844,	0x82458acc,	0xe7fdf6d4,
+	0x824f0208,	0xe7cc9917,	0x82588ca7,	0xe79b3f16,	0x82622aa6,	0xe769e8d8,	0x826bdc04,	0xe7389665,
+	0x8275a0c0,	0xe70747c4,	0x827f78d8,	0xe6d5fcfc,	0x8289644b,	0xe6a4b616,	0x82936317,	0xe6737319,
+	0x829d753a,	0xe642340d,	0x82a79ab3,	0xe610f8f9,	0x82b1d381,	0xe5dfc1e5,	0x82bc1fa2,	0xe5ae8ed8,
+	0x82c67f14,	0xe57d5fda,	0x82d0f1d5,	0xe54c34f3,	0x82db77e5,	0xe51b0e2a,	0x82e61141,	0xe4e9eb87,
+	0x82f0bde8,	0xe4b8cd11,	0x82fb7dd8,	0xe487b2d0,	0x83065110,	0xe4569ccb,	0x8311378d,	0xe4258b0a,
+	0x831c314e,	0xe3f47d96,	0x83273e52,	0xe3c37474,	0x83325e97,	0xe3926fad,	0x833d921b,	0xe3616f48,
+	0x8348d8dc,	0xe330734d,	0x835432d8,	0xe2ff7bc3,	0x835fa00f,	0xe2ce88b3,	0x836b207d,	0xe29d9a23,
+	0x8376b422,	0xe26cb01b,	0x83825afb,	0xe23bcaa2,	0x838e1507,	0xe20ae9c1,	0x8399e244,	0xe1da0d7e,
+	0x83a5c2b0,	0xe1a935e2,	0x83b1b649,	0xe17862f3,	0x83bdbd0e,	0xe14794ba,	0x83c9d6fc,	0xe116cb3d,
+	0x83d60412,	0xe0e60685,	0x83e2444d,	0xe0b54698,	0x83ee97ad,	0xe0848b7f,	0x83fafe2e,	0xe053d541,
+	0x840777d0,	0xe02323e5,	0x84140490,	0xdff27773,	0x8420a46c,	0xdfc1cff3,	0x842d5762,	0xdf912d6b,
+	0x843a1d70,	0xdf608fe4,	0x8446f695,	0xdf2ff764,	0x8453e2cf,	0xdeff63f4,	0x8460e21a,	0xdeced59b,
+	0x846df477,	0xde9e4c60,	0x847b19e1,	0xde6dc84b,	0x84885258,	0xde3d4964,	0x84959dd9,	0xde0ccfb1,
+	0x84a2fc62,	0xdddc5b3b,	0x84b06df2,	0xddabec08,	0x84bdf286,	0xdd7b8220,	0x84cb8a1b,	0xdd4b1d8c,
+	0x84d934b1,	0xdd1abe51,	0x84e6f244,	0xdcea6478,	0x84f4c2d4,	0xdcba1008,	0x8502a65c,	0xdc89c109,
+	0x85109cdd,	0xdc597781,	0x851ea652,	0xdc293379,	0x852cc2bb,	0xdbf8f4f8,	0x853af214,	0xdbc8bc06,
+	0x8549345c,	0xdb9888a8,	0x85578991,	0xdb685ae9,	0x8565f1b0,	0xdb3832cd,	0x85746cb8,	0xdb08105e,
+	0x8582faa5,	0xdad7f3a2,	0x85919b76,	0xdaa7dca1,	0x85a04f28,	0xda77cb63,	0x85af15b9,	0xda47bfee,
+	0x85bdef28,	0xda17ba4a,	0x85ccdb70,	0xd9e7ba7f,	0x85dbda91,	0xd9b7c094,	0x85eaec88,	0xd987cc90,
+	0x85fa1153,	0xd957de7a,	0x860948ef,	0xd927f65b,	0x86189359,	0xd8f81439,	0x8627f091,	0xd8c8381d,
+	0x86376092,	0xd898620c,	0x8646e35c,	0xd868920f,	0x865678eb,	0xd838c82d,	0x8666213c,	0xd809046e,
+	0x8675dc4f,	0xd7d946d8,	0x8685aa20,	0xd7a98f73,	0x86958aac,	0xd779de47,	0x86a57df2,	0xd74a335b,
+	0x86b583ee,	0xd71a8eb5,	0x86c59c9f,	0xd6eaf05f,	0x86d5c802,	0xd6bb585e,	0x86e60614,	0xd68bc6ba,
+	0x86f656d3,	0xd65c3b7b,	0x8706ba3d,	0xd62cb6a8,	0x8717304e,	0xd5fd3848,	0x8727b905,	0xd5cdc062,
+	0x8738545e,	0xd59e4eff,	0x87490258,	0xd56ee424,	0x8759c2ef,	0xd53f7fda,	0x876a9621,	0xd5102228,
+	0x877b7bec,	0xd4e0cb15,	0x878c744d,	0xd4b17aa8,	0x879d7f41,	0xd48230e9,	0x87ae9cc5,	0xd452eddf,
+	0x87bfccd7,	0xd423b191,	0x87d10f75,	0xd3f47c06,	0x87e2649b,	0xd3c54d47,	0x87f3cc48,	0xd396255a,
+	0x88054677,	0xd3670446,	0x8816d327,	0xd337ea12,	0x88287256,	0xd308d6c7,	0x883a23ff,	0xd2d9ca6a,
+	0x884be821,	0xd2aac504,	0x885dbeb8,	0xd27bc69c,	0x886fa7c2,	0xd24ccf39,	0x8881a33d,	0xd21ddee2,
+	0x8893b125,	0xd1eef59e,	0x88a5d177,	0xd1c01375,	0x88b80432,	0xd191386e,	0x88ca4951,	0xd1626490,
+	0x88dca0d3,	0xd13397e2,	0x88ef0ab4,	0xd104d26b,	0x890186f2,	0xd0d61434,	0x89141589,	0xd0a75d42,
+	0x8926b677,	0xd078ad9e,	0x893969b9,	0xd04a054e,	0x894c2f4c,	0xd01b6459,	0x895f072e,	0xcfeccac7,
+	0x8971f15a,	0xcfbe389f,	0x8984edcf,	0xcf8fade9,	0x8997fc8a,	0xcf612aaa,	0x89ab1d87,	0xcf32aeeb,
+	0x89be50c3,	0xcf043ab3,	0x89d1963c,	0xced5ce08,	0x89e4edef,	0xcea768f2,	0x89f857d8,	0xce790b79,
+	0x8a0bd3f5,	0xce4ab5a2,	0x8a1f6243,	0xce1c6777,	0x8a3302be,	0xcdee20fc,	0x8a46b564,	0xcdbfe23a,
+	0x8a5a7a31,	0xcd91ab39,	0x8a6e5123,	0xcd637bfe,	0x8a823a36,	0xcd355491,	0x8a963567,	0xcd0734f9,
+	0x8aaa42b4,	0xccd91d3d,	0x8abe6219,	0xccab0d65,	0x8ad29394,	0xcc7d0578,	0x8ae6d720,	0xcc4f057c,
+	0x8afb2cbb,	0xcc210d79,	0x8b0f9462,	0xcbf31d75,	0x8b240e11,	0xcbc53579,	0x8b3899c6,	0xcb97558a,
+	0x8b4d377c,	0xcb697db0,	0x8b61e733,	0xcb3badf3,	0x8b76a8e4,	0xcb0de658,	0x8b8b7c8f,	0xcae026e8,
+	0x8ba0622f,	0xcab26fa9,	0x8bb559c1,	0xca84c0a3,	0x8bca6343,	0xca5719db,	0x8bdf7eb0,	0xca297b5a,
+	0x8bf4ac05,	0xc9fbe527,	0x8c09eb40,	0xc9ce5748,	0x8c1f3c5d,	0xc9a0d1c5,	0x8c349f58,	0xc97354a4,
+	0x8c4a142f,	0xc945dfec,	0x8c5f9ade,	0xc91873a5,	0x8c753362,	0xc8eb0fd6,	0x8c8addb7,	0xc8bdb485,
+	0x8ca099da,	0xc89061ba,	0x8cb667c8,	0xc863177b,	0x8ccc477d,	0xc835d5d0,	0x8ce238f6,	0xc8089cbf,
+	0x8cf83c30,	0xc7db6c50,	0x8d0e5127,	0xc7ae4489,	0x8d2477d8,	0xc7812572,	0x8d3ab03f,	0xc7540f11,
+	0x8d50fa59,	0xc727016d,	0x8d675623,	0xc6f9fc8d,	0x8d7dc399,	0xc6cd0079,	0x8d9442b8,	0xc6a00d37,
+	0x8daad37b,	0xc67322ce,	0x8dc175e0,	0xc6464144,	0x8dd829e4,	0xc61968a2,	0x8deeef82,	0xc5ec98ee,
+	0x8e05c6b7,	0xc5bfd22e,	0x8e1caf80,	0xc593146a,	0x8e33a9da,	0xc5665fa9,	0x8e4ab5bf,	0xc539b3f1,
+	0x8e61d32e,	0xc50d1149,	0x8e790222,	0xc4e077b8,	0x8e904298,	0xc4b3e746,	0x8ea7948c,	0xc4875ff9,
+	0x8ebef7fb,	0xc45ae1d7,	0x8ed66ce1,	0xc42e6ce8,	0x8eedf33b,	0xc4020133,	0x8f058b04,	0xc3d59ebe,
+	0x8f1d343a,	0xc3a94590,	0x8f34eed8,	0xc37cf5b0,	0x8f4cbadb,	0xc350af26,	0x8f649840,	0xc32471f7,
+	0x8f7c8701,	0xc2f83e2a,	0x8f94871d,	0xc2cc13c7,	0x8fac988f,	0xc29ff2d4,	0x8fc4bb53,	0xc273db58,
+	0x8fdcef66,	0xc247cd5a,	0x8ff534c4,	0xc21bc8e1,	0x900d8b69,	0xc1efcdf3,	0x9025f352,	0xc1c3dc97,
+	0x903e6c7b,	0xc197f4d4,	0x9056f6df,	0xc16c16b0,	0x906f927c,	0xc1404233,	0x90883f4d,	0xc1147764,
+	0x90a0fd4e,	0xc0e8b648,	0x90b9cc7d,	0xc0bcfee7,	0x90d2acd4,	0xc0915148,	0x90eb9e50,	0xc065ad70,
+	0x9104a0ee,	0xc03a1368,	0x911db4a9,	0xc00e8336,	0x9136d97d,	0xbfe2fcdf,	0x91500f67,	0xbfb7806c,
+	0x91695663,	0xbf8c0de3,	0x9182ae6d,	0xbf60a54a,	0x919c1781,	0xbf3546a8,	0x91b5919a,	0xbf09f205,
+	0x91cf1cb6,	0xbedea765,	0x91e8b8d0,	0xbeb366d1,	0x920265e4,	0xbe88304f,	0x921c23ef,	0xbe5d03e6,
+	0x9235f2ec,	0xbe31e19b,	0x924fd2d7,	0xbe06c977,	0x9269c3ac,	0xbddbbb7f,	0x9283c568,	0xbdb0b7bb,
+	0x929dd806,	0xbd85be30,	0x92b7fb82,	0xbd5acee5,	0x92d22fd9,	0xbd2fe9e2,	0x92ec7505,	0xbd050f2c,
+	0x9306cb04,	0xbcda3ecb,	0x932131d1,	0xbcaf78c4,	0x933ba968,	0xbc84bd1f,	0x935631c5,	0xbc5a0be2,
+	0x9370cae4,	0xbc2f6513,	0x938b74c1,	0xbc04c8ba,	0x93a62f57,	0xbbda36dd,	0x93c0faa3,	0xbbafaf82,
+	0x93dbd6a0,	0xbb8532b0,	0x93f6c34a,	0xbb5ac06d,	0x9411c09e,	0xbb3058c0,	0x942cce96,	0xbb05fbb0,
+	0x9447ed2f,	0xbadba943,	0x94631c65,	0xbab16180,	0x947e5c33,	0xba87246d,	0x9499ac95,	0xba5cf210,
+	0x94b50d87,	0xba32ca71,	0x94d07f05,	0xba08ad95,	0x94ec010b,	0xb9de9b83,	0x95079394,	0xb9b49442,
+	0x9523369c,	0xb98a97d8,	0x953eea1e,	0xb960a64c,	0x955aae17,	0xb936bfa4,	0x95768283,	0xb90ce3e6,
+	0x9592675c,	0xb8e31319,	0x95ae5c9f,	0xb8b94d44,	0x95ca6247,	0xb88f926d,	0x95e67850,	0xb865e299,
+	0x96029eb6,	0xb83c3dd1,	0x961ed574,	0xb812a41a,	0x963b1c86,	0xb7e9157a,	0x965773e7,	0xb7bf91f8,
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+	0x1072a048,	0x810fa7a0,	0x10a4784b,	0x811626ec,	0x10d64dbd,	0x811cb9ca,	0x11082096,	0x8123603a,
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+	0x1ccf8cb3,	0x8348d8dc,	0x1d00843d,	0x835432d8,	0x1d31774d,	0x835fa00f,	0x1d6265dd,	0x836b207d,
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+	0x209f701c,	0x843a1d70,	0x20d0089c,	0x8446f695,	0x21009c0c,	0x8453e2cf,	0x21312a65,	0x8460e21a,
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+	0x26a82186,	0x85fa1153,	0x26d809a5,	0x860948ef,	0x2707ebc7,	0x86189359,	0x2737c7e3,	0x8627f091,
+	0x27679df4,	0x86376092,	0x27976df1,	0x8646e35c,	0x27c737d3,	0x865678eb,	0x27f6fb92,	0x8666213c,
+	0x2826b928,	0x8675dc4f,	0x2856708d,	0x8685aa20,	0x288621b9,	0x86958aac,	0x28b5cca5,	0x86a57df2,
+	0x28e5714b,	0x86b583ee,	0x29150fa1,	0x86c59c9f,	0x2944a7a2,	0x86d5c802,	0x29743946,	0x86e60614,
+	0x29a3c485,	0x86f656d3,	0x29d34958,	0x8706ba3d,	0x2a02c7b8,	0x8717304e,	0x2a323f9e,	0x8727b905,
+	0x2a61b101,	0x8738545e,	0x2a911bdc,	0x87490258,	0x2ac08026,	0x8759c2ef,	0x2aefddd8,	0x876a9621,
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+	0x2bdc4e6f,	0x87bfccd7,	0x2c0b83fa,	0x87d10f75,	0x2c3ab2b9,	0x87e2649b,	0x2c69daa6,	0x87f3cc48,
+	0x2c98fbba,	0x88054677,	0x2cc815ee,	0x8816d327,	0x2cf72939,	0x88287256,	0x2d263596,	0x883a23ff,
+	0x2d553afc,	0x884be821,	0x2d843964,	0x885dbeb8,	0x2db330c7,	0x886fa7c2,	0x2de2211e,	0x8881a33d,
+	0x2e110a62,	0x8893b125,	0x2e3fec8b,	0x88a5d177,	0x2e6ec792,	0x88b80432,	0x2e9d9b70,	0x88ca4951,
+	0x2ecc681e,	0x88dca0d3,	0x2efb2d95,	0x88ef0ab4,	0x2f29ebcc,	0x890186f2,	0x2f58a2be,	0x89141589,
+	0x2f875262,	0x8926b677,	0x2fb5fab2,	0x893969b9,	0x2fe49ba7,	0x894c2f4c,	0x30133539,	0x895f072e,
+	0x3041c761,	0x8971f15a,	0x30705217,	0x8984edcf,	0x309ed556,	0x8997fc8a,	0x30cd5115,	0x89ab1d87,
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+	0x6f5f02b2,	0xc0e8b648,	0x6f77c0b3,	0xc1147764,	0x6f906d84,	0xc1404233,	0x6fa90921,	0xc16c16b0,
+	0x6fc19385,	0xc197f4d4,	0x6fda0cae,	0xc1c3dc97,	0x6ff27497,	0xc1efcdf3,	0x700acb3c,	0xc21bc8e1,
+	0x7023109a,	0xc247cd5a,	0x703b44ad,	0xc273db58,	0x70536771,	0xc29ff2d4,	0x706b78e3,	0xc2cc13c7,
+	0x708378ff,	0xc2f83e2a,	0x709b67c0,	0xc32471f7,	0x70b34525,	0xc350af26,	0x70cb1128,	0xc37cf5b0,
+	0x70e2cbc6,	0xc3a94590,	0x70fa74fc,	0xc3d59ebe,	0x71120cc5,	0xc4020133,	0x7129931f,	0xc42e6ce8,
+	0x71410805,	0xc45ae1d7,	0x71586b74,	0xc4875ff9,	0x716fbd68,	0xc4b3e746,	0x7186fdde,	0xc4e077b8,
+	0x719e2cd2,	0xc50d1149,	0x71b54a41,	0xc539b3f1,	0x71cc5626,	0xc5665fa9,	0x71e35080,	0xc593146a,
+	0x71fa3949,	0xc5bfd22e,	0x7211107e,	0xc5ec98ee,	0x7227d61c,	0xc61968a2,	0x723e8a20,	0xc6464144,
+	0x72552c85,	0xc67322ce,	0x726bbd48,	0xc6a00d37,	0x72823c67,	0xc6cd0079,	0x7298a9dd,	0xc6f9fc8d,
+	0x72af05a7,	0xc727016d,	0x72c54fc1,	0xc7540f11,	0x72db8828,	0xc7812572,	0x72f1aed9,	0xc7ae4489,
+	0x7307c3d0,	0xc7db6c50,	0x731dc70a,	0xc8089cbf,	0x7333b883,	0xc835d5d0,	0x73499838,	0xc863177b,
+	0x735f6626,	0xc89061ba,	0x73752249,	0xc8bdb485,	0x738acc9e,	0xc8eb0fd6,	0x73a06522,	0xc91873a5,
+	0x73b5ebd1,	0xc945dfec,	0x73cb60a8,	0xc97354a4,	0x73e0c3a3,	0xc9a0d1c5,	0x73f614c0,	0xc9ce5748,
+	0x740b53fb,	0xc9fbe527,	0x74208150,	0xca297b5a,	0x74359cbd,	0xca5719db,	0x744aa63f,	0xca84c0a3,
+	0x745f9dd1,	0xcab26fa9,	0x74748371,	0xcae026e8,	0x7489571c,	0xcb0de658,	0x749e18cd,	0xcb3badf3,
+	0x74b2c884,	0xcb697db0,	0x74c7663a,	0xcb97558a,	0x74dbf1ef,	0xcbc53579,	0x74f06b9e,	0xcbf31d75,
+	0x7504d345,	0xcc210d79,	0x751928e0,	0xcc4f057c,	0x752d6c6c,	0xcc7d0578,	0x75419de7,	0xccab0d65,
+	0x7555bd4c,	0xccd91d3d,	0x7569ca99,	0xcd0734f9,	0x757dc5ca,	0xcd355491,	0x7591aedd,	0xcd637bfe,
+	0x75a585cf,	0xcd91ab39,	0x75b94a9c,	0xcdbfe23a,	0x75ccfd42,	0xcdee20fc,	0x75e09dbd,	0xce1c6777,
+	0x75f42c0b,	0xce4ab5a2,	0x7607a828,	0xce790b79,	0x761b1211,	0xcea768f2,	0x762e69c4,	0xced5ce08,
+	0x7641af3d,	0xcf043ab3,	0x7654e279,	0xcf32aeeb,	0x76680376,	0xcf612aaa,	0x767b1231,	0xcf8fade9,
+	0x768e0ea6,	0xcfbe389f,	0x76a0f8d2,	0xcfeccac7,	0x76b3d0b4,	0xd01b6459,	0x76c69647,	0xd04a054e,
+	0x76d94989,	0xd078ad9e,	0x76ebea77,	0xd0a75d42,	0x76fe790e,	0xd0d61434,	0x7710f54c,	0xd104d26b,
+	0x77235f2d,	0xd13397e2,	0x7735b6af,	0xd1626490,	0x7747fbce,	0xd191386e,	0x775a2e89,	0xd1c01375,
+	0x776c4edb,	0xd1eef59e,	0x777e5cc3,	0xd21ddee2,	0x7790583e,	0xd24ccf39,	0x77a24148,	0xd27bc69c,
+	0x77b417df,	0xd2aac504,	0x77c5dc01,	0xd2d9ca6a,	0x77d78daa,	0xd308d6c7,	0x77e92cd9,	0xd337ea12,
+	0x77fab989,	0xd3670446,	0x780c33b8,	0xd396255a,	0x781d9b65,	0xd3c54d47,	0x782ef08b,	0xd3f47c06,
+	0x78403329,	0xd423b191,	0x7851633b,	0xd452eddf,	0x786280bf,	0xd48230e9,	0x78738bb3,	0xd4b17aa8,
+	0x78848414,	0xd4e0cb15,	0x789569df,	0xd5102228,	0x78a63d11,	0xd53f7fda,	0x78b6fda8,	0xd56ee424,
+	0x78c7aba2,	0xd59e4eff,	0x78d846fb,	0xd5cdc062,	0x78e8cfb2,	0xd5fd3848,	0x78f945c3,	0xd62cb6a8,
+	0x7909a92d,	0xd65c3b7b,	0x7919f9ec,	0xd68bc6ba,	0x792a37fe,	0xd6bb585e,	0x793a6361,	0xd6eaf05f,
+	0x794a7c12,	0xd71a8eb5,	0x795a820e,	0xd74a335b,	0x796a7554,	0xd779de47,	0x797a55e0,	0xd7a98f73,
+	0x798a23b1,	0xd7d946d8,	0x7999dec4,	0xd809046e,	0x79a98715,	0xd838c82d,	0x79b91ca4,	0xd868920f,
+	0x79c89f6e,	0xd898620c,	0x79d80f6f,	0xd8c8381d,	0x79e76ca7,	0xd8f81439,	0x79f6b711,	0xd927f65b,
+	0x7a05eead,	0xd957de7a,	0x7a151378,	0xd987cc90,	0x7a24256f,	0xd9b7c094,	0x7a332490,	0xd9e7ba7f,
+	0x7a4210d8,	0xda17ba4a,	0x7a50ea47,	0xda47bfee,	0x7a5fb0d8,	0xda77cb63,	0x7a6e648a,	0xdaa7dca1,
+	0x7a7d055b,	0xdad7f3a2,	0x7a8b9348,	0xdb08105e,	0x7a9a0e50,	0xdb3832cd,	0x7aa8766f,	0xdb685ae9,
+	0x7ab6cba4,	0xdb9888a8,	0x7ac50dec,	0xdbc8bc06,	0x7ad33d45,	0xdbf8f4f8,	0x7ae159ae,	0xdc293379,
+	0x7aef6323,	0xdc597781,	0x7afd59a4,	0xdc89c109,	0x7b0b3d2c,	0xdcba1008,	0x7b190dbc,	0xdcea6478,
+	0x7b26cb4f,	0xdd1abe51,	0x7b3475e5,	0xdd4b1d8c,	0x7b420d7a,	0xdd7b8220,	0x7b4f920e,	0xddabec08,
+	0x7b5d039e,	0xdddc5b3b,	0x7b6a6227,	0xde0ccfb1,	0x7b77ada8,	0xde3d4964,	0x7b84e61f,	0xde6dc84b,
+	0x7b920b89,	0xde9e4c60,	0x7b9f1de6,	0xdeced59b,	0x7bac1d31,	0xdeff63f4,	0x7bb9096b,	0xdf2ff764,
+	0x7bc5e290,	0xdf608fe4,	0x7bd2a89e,	0xdf912d6b,	0x7bdf5b94,	0xdfc1cff3,	0x7bebfb70,	0xdff27773,
+	0x7bf88830,	0xe02323e5,	0x7c0501d2,	0xe053d541,	0x7c116853,	0xe0848b7f,	0x7c1dbbb3,	0xe0b54698,
+	0x7c29fbee,	0xe0e60685,	0x7c362904,	0xe116cb3d,	0x7c4242f2,	0xe14794ba,	0x7c4e49b7,	0xe17862f3,
+	0x7c5a3d50,	0xe1a935e2,	0x7c661dbc,	0xe1da0d7e,	0x7c71eaf9,	0xe20ae9c1,	0x7c7da505,	0xe23bcaa2,
+	0x7c894bde,	0xe26cb01b,	0x7c94df83,	0xe29d9a23,	0x7ca05ff1,	0xe2ce88b3,	0x7cabcd28,	0xe2ff7bc3,
+	0x7cb72724,	0xe330734d,	0x7cc26de5,	0xe3616f48,	0x7ccda169,	0xe3926fad,	0x7cd8c1ae,	0xe3c37474,
+	0x7ce3ceb2,	0xe3f47d96,	0x7ceec873,	0xe4258b0a,	0x7cf9aef0,	0xe4569ccb,	0x7d048228,	0xe487b2d0,
+	0x7d0f4218,	0xe4b8cd11,	0x7d19eebf,	0xe4e9eb87,	0x7d24881b,	0xe51b0e2a,	0x7d2f0e2b,	0xe54c34f3,
+	0x7d3980ec,	0xe57d5fda,	0x7d43e05e,	0xe5ae8ed8,	0x7d4e2c7f,	0xe5dfc1e5,	0x7d58654d,	0xe610f8f9,
+	0x7d628ac6,	0xe642340d,	0x7d6c9ce9,	0xe6737319,	0x7d769bb5,	0xe6a4b616,	0x7d808728,	0xe6d5fcfc,
+	0x7d8a5f40,	0xe70747c4,	0x7d9423fc,	0xe7389665,	0x7d9dd55a,	0xe769e8d8,	0x7da77359,	0xe79b3f16,
+	0x7db0fdf8,	0xe7cc9917,	0x7dba7534,	0xe7fdf6d4,	0x7dc3d90d,	0xe82f5844,	0x7dcd2981,	0xe860bd61,
+	0x7dd6668f,	0xe8922622,	0x7ddf9034,	0xe8c39280,	0x7de8a670,	0xe8f50273,	0x7df1a942,	0xe92675f4,
+	0x7dfa98a8,	0xe957ecfb,	0x7e0374a0,	0xe9896781,	0x7e0c3d29,	0xe9bae57d,	0x7e14f242,	0xe9ec66e8,
+	0x7e1d93ea,	0xea1debbb,	0x7e26221f,	0xea4f73ee,	0x7e2e9cdf,	0xea80ff7a,	0x7e37042a,	0xeab28e56,
+	0x7e3f57ff,	0xeae4207a,	0x7e47985b,	0xeb15b5e1,	0x7e4fc53e,	0xeb474e81,	0x7e57dea7,	0xeb78ea52,
+	0x7e5fe493,	0xebaa894f,	0x7e67d703,	0xebdc2b6e,	0x7e6fb5f4,	0xec0dd0a8,	0x7e778166,	0xec3f78f6,
+	0x7e7f3957,	0xec71244f,	0x7e86ddc6,	0xeca2d2ad,	0x7e8e6eb2,	0xecd48407,	0x7e95ec1a,	0xed063856,
+	0x7e9d55fc,	0xed37ef91,	0x7ea4ac58,	0xed69a9b3,	0x7eabef2c,	0xed9b66b2,	0x7eb31e78,	0xedcd2687,
+	0x7eba3a39,	0xedfee92b,	0x7ec14270,	0xee30ae96,	0x7ec8371a,	0xee6276bf,	0x7ecf1837,	0xee9441a0,
+	0x7ed5e5c6,	0xeec60f31,	0x7edc9fc6,	0xeef7df6a,	0x7ee34636,	0xef29b243,	0x7ee9d914,	0xef5b87b5,
+	0x7ef05860,	0xef8d5fb8,	0x7ef6c418,	0xefbf3a45,	0x7efd1c3c,	0xeff11753,	0x7f0360cb,	0xf022f6da,
+	0x7f0991c4,	0xf054d8d5,	0x7f0faf25,	0xf086bd39,	0x7f15b8ee,	0xf0b8a401,	0x7f1baf1e,	0xf0ea8d24,
+	0x7f2191b4,	0xf11c789a,	0x7f2760af,	0xf14e665c,	0x7f2d1c0e,	0xf1805662,	0x7f32c3d1,	0xf1b248a5,
+	0x7f3857f6,	0xf1e43d1c,	0x7f3dd87c,	0xf21633c0,	0x7f434563,	0xf2482c8a,	0x7f489eaa,	0xf27a2771,
+	0x7f4de451,	0xf2ac246e,	0x7f531655,	0xf2de2379,	0x7f5834b7,	0xf310248a,	0x7f5d3f75,	0xf342279b,
+	0x7f62368f,	0xf3742ca2,	0x7f671a05,	0xf3a63398,	0x7f6be9d4,	0xf3d83c77,	0x7f70a5fe,	0xf40a4735,
+	0x7f754e80,	0xf43c53cb,	0x7f79e35a,	0xf46e6231,	0x7f7e648c,	0xf4a07261,	0x7f82d214,	0xf4d28451,
+	0x7f872bf3,	0xf50497fb,	0x7f8b7227,	0xf536ad56,	0x7f8fa4b0,	0xf568c45b,	0x7f93c38c,	0xf59add02,
+	0x7f97cebd,	0xf5ccf743,	0x7f9bc640,	0xf5ff1318,	0x7f9faa15,	0xf6313077,	0x7fa37a3c,	0xf6634f59,
+	0x7fa736b4,	0xf6956fb7,	0x7faadf7c,	0xf6c79188,	0x7fae7495,	0xf6f9b4c6,	0x7fb1f5fc,	0xf72bd967,
+	0x7fb563b3,	0xf75dff66,	0x7fb8bdb8,	0xf79026b9,	0x7fbc040a,	0xf7c24f59,	0x7fbf36aa,	0xf7f4793e,
+	0x7fc25596,	0xf826a462,	0x7fc560cf,	0xf858d0bb,	0x7fc85854,	0xf88afe42,	0x7fcb3c23,	0xf8bd2cef,
+	0x7fce0c3e,	0xf8ef5cbb,	0x7fd0c8a3,	0xf9218d9e,	0x7fd37153,	0xf953bf91,	0x7fd6064c,	0xf985f28a,
+	0x7fd8878e,	0xf9b82684,	0x7fdaf519,	0xf9ea5b75,	0x7fdd4eec,	0xfa1c9157,	0x7fdf9508,	0xfa4ec821,
+	0x7fe1c76b,	0xfa80ffcb,	0x7fe3e616,	0xfab3384f,	0x7fe5f108,	0xfae571a4,	0x7fe7e841,	0xfb17abc2,
+	0x7fe9cbc0,	0xfb49e6a3,	0x7feb9b85,	0xfb7c223d,	0x7fed5791,	0xfbae5e89,	0x7feeffe1,	0xfbe09b80,
+	0x7ff09478,	0xfc12d91a,	0x7ff21553,	0xfc45174e,	0x7ff38274,	0xfc775616,	0x7ff4dbd9,	0xfca9956a,
+	0x7ff62182,	0xfcdbd541,	0x7ff75370,	0xfd0e1594,	0x7ff871a2,	0xfd40565c,	0x7ff97c18,	0xfd729790,
+	0x7ffa72d1,	0xfda4d929,	0x7ffb55ce,	0xfdd71b1e,	0x7ffc250f,	0xfe095d69,	0x7ffce093,	0xfe3ba002,
+	0x7ffd885a,	0xfe6de2e0,	0x7ffe1c65,	0xfea025fd,	0x7ffe9cb2,	0xfed2694f,	0x7fff0943,	0xff04acd0,
+	0x7fff6216,	0xff36f078,	0x7fffa72c,	0xff69343f,	0x7fffd886,	0xff9b781d,	0x7ffff621,	0xffcdbc0b
+
+};
+
+/**   
+*   
+* @brief  Initialization function for the Q31 CFFT/CIFFT.  
+* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.  
+* @param[in]     fftLen         length of the FFT.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+
+arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q31_t *) twiddleCoefQ31;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of Instance structure depending on the FFT length */
+  switch (S->fftLen)
+  {
+
+  /*  Initializations of structure parameters for 4096 point FFT */
+  case 4096u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = armBitRevTable;
+    break;
+
+    /*  Initializations of structure parameters for 1024 point FFT */
+  case 1024u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 4u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 4u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    break;
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = &armBitRevTable[63];
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 256u;
+    S->bitRevFactor = 256u;
+    S->pBitRevTable = &armBitRevTable[255];
+    break;
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
new file mode 100644
index 0000000..d855a10
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
@@ -0,0 +1,1952 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_q15.c   
+*   
+* Description:	This file has function definition of Radix-4 FFT & IFFT function and   
+*				In-place bit reversal using bit reversal table   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+
+/**   
+ * @details   
+ * @brief Processing function for the Q15 CFFT/CIFFT.  
+ * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.  
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.  
+ * @return none.  
+ *    
+ * \par Input and output formats:   
+ * \par   
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.  
+ * Hence the output format is different for different FFT sizes.   
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:  
+ * \par  
+ * \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT"   
+ * \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT"   
+ */
+
+void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc)
+{
+  if(S->ifftFlag == 1u)
+  {
+    /*  Complex IFFT radix-4  */
+    arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier);
+  }
+  else
+  {
+    /*  Complex FFT radix-4  */
+    arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
+
+/*   
+* Radix-4 FFT algorithm used is :   
+*   
+* Input real and imaginary data:   
+* x(n) = xa + j * ya   
+* x(n+N/4 ) = xb + j * yb   
+* x(n+N/2 ) = xc + j * yc   
+* x(n+3N 4) = xd + j * yd   
+*   
+*   
+* Output real and imaginary data:   
+* x(4r) = xa'+ j * ya'   
+* x(4r+1) = xb'+ j * yb'   
+* x(4r+2) = xc'+ j * yc'   
+* x(4r+3) = xd'+ j * yd'   
+*   
+*   
+* Twiddle factors for radix-4 FFT:   
+* Wn = co1 + j * (- si1)   
+* W2n = co2 + j * (- si2)   
+* W3n = co3 + j * (- si3)   
+   
+* The real and imaginary output values for the radix-4 butterfly are   
+* xa' = xa + xb + xc + xd   
+* ya' = ya + yb + yc + yd   
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)   
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)   
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)   
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)   
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)   
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)   
+*   
+*/
+
+/**   
+ * @brief  Core function for the Q15 CFFT butterfly process.  
+ * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef16         points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+void arm_radix4_butterfly_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t R, S, T, U;
+  q31_t C1, C2, C3, out1, out2;
+  q31_t *pSrc, *pCoeff;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+  q15_t in;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  pointer initializations for SIMD calculations */
+  pSrc = (q31_t *) pSrc16;
+  pCoeff = (q31_t *) pCoef16;
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = pSrc[i0];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* Read yc (real), xc(imag) input */
+    S = pSrc[i2];
+    in = ((int16_t) (S & 0xFFFF)) >> 2;
+    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* R = packed((ya + yc), (xa + xc) ) */
+    R = __QADD16(T, S);
+    /* S = packed((ya - yc), (xa - xc) ) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* T = packed((yb + yd), (xb + xd) ) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc[i0] = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+    R = __QSUB16(R, T);
+
+    /* co2 & si2 are read from SIMD Coefficient pointer */
+    C2 = pCoeff[2u * ic];
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = __SMUAD(C2, R) >> 16u;
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = __SMUSDX(C2, R);
+
+#else
+
+    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out1 = __SMUSDX(R, C2) >> 16u;
+    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out2 = __SMUAD(C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /*  Reading i0+fftLen/4 */
+    /* T = packed(yb, xb) */
+    T = pSrc[i1];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc[i1] = (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Butterfly calculations */
+    /* U = packed(yd, xd) */
+    U = pSrc[i3];
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* T = packed(yb-yd, xb-xd) */
+    T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QASX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QSAX(S, T);
+
+#else
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QSAX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QASX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* co1 & si1 are read from SIMD Coefficient pointer */
+    C1 = pCoeff[ic];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = __SMUAD(C1, S) >> 16u;
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = __SMUSDX(C1, S);
+
+#else
+
+    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out1 = __SMUSDX(S, C1) >> 16u;
+    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out2 = __SMUAD(C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xb', yb') in little endian format */
+    pSrc[i2] = ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+
+
+    /* co3 & si3 are read from SIMD Coefficient pointer */
+    C3 = pCoeff[3u * ic];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = __SMUAD(C3, R) >> 16u;
+    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = __SMUSDX(C3, R);
+
+#else
+
+    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out1 = __SMUSDX(R, C3) >> 16u;
+    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out2 = __SMUAD(C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xd', yd') in little endian format */
+    pSrc[i3] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      C1 = pCoeff[ic];
+      C2 = pCoeff[2u * ic];
+      C3 = pCoeff[3u * ic];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T = pSrc[i0];
+
+        /* Read yc (real), xc(imag) input */
+        S = pSrc[i2];
+
+        /* R = packed( (ya + yc), (xa + xc)) */
+        R = __QADD16(T, S);
+
+        /* S = packed((ya - yc), (xa - xc)) */
+        S = __QSUB16(T, S);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T = pSrc[i1];
+
+        /* Read yd (real), xd(imag) input */
+        U = pSrc[i3];
+
+
+        /* T = packed( (yb + yd), (xb + xd)) */
+        T = __QADD16(T, U);
+
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = __SHADD16(R, T);
+        in = ((int16_t) (out1 & 0xFFFF)) >> 1;
+        out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+        pSrc[i0] = out1;
+
+        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+        R = __SHSUB16(R, T);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = __SMUAD(C2, R) >> 16u;
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = __SMUSDX(C2, R);
+
+#else
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out1 = __SMUSDX(R, C2) >> 16u;
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out2 = __SMUAD(C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T = pSrc[i1];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        pSrc[i1] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U = pSrc[i3];
+
+        /* T = packed(yb-yd, xb-xd) */
+        T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHASX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHSAX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUAD(C1, S) >> 16u;
+        out2 = __SMUSDX(C1, S);
+
+#else
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHSAX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHASX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUSDX(S, C1) >> 16u;
+        out2 = __SMUAD(C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        pSrc[i2] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(C3, R) >> 16u;
+        out2 = __SMUSDX(C3, R);
+
+#else
+
+        out1 = __SMUSDX(R, C3) >> 16u;
+        out2 = __SMUAD(C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+        pSrc[i3] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /* end of middle stage process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = pSrc[i0];
+    /* Read yc (real), xc(imag) input */
+    S = pSrc[i2];
+
+    /* R = packed((ya + yc), (xa + xc)) */
+    R = __QADD16(T, S);
+    /* S = packed((ya - yc), (xa - xc)) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc[i0] = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+    R = __SHSUB16(R, T);
+
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc[i1] = R;
+
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+    /* T = packed( (yb - yd), (xb - xd))  */
+    T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    pSrc[i2] = __SHSAX(S, T);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    pSrc[i3] = __SHASX(S, T);
+
+#else
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    pSrc[i2] = __SHASX(S, T);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    pSrc[i3] = __SHSAX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+  }
+
+  /* end of last stage process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u] >> 2u;
+    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u] >> 2u;
+    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+    /* R0 = (ya + yc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    /* R1 = (xa + xc) */
+    R1 = __SSAT(T1 + S1, 16u);
+
+    /* S0 = (ya - yc) */
+    S0 = __SSAT(T0 - S0, 16);
+    /* S1 = (xa - xc) */
+    S1 = __SSAT(T1 - S1, 16);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1] >> 2u;
+
+    /* T0 = (yb + yd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    /* T1 = (xb + xd) */
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* ya' = ya + yb + yc + yd */
+    /* xa' = xa + xb + xc + xd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd) */
+    /* R1 = (xa + xc) - (xb + xd) */
+    R0 = __SSAT(R0 - T0, 16u);
+    R1 = __SSAT(R1 - T1, 16u);
+
+    /* co2 & si2 are read from Coefficient pointer */
+    Co2 = pCoef16[2u * ic * 2u];
+    Si2 = pCoef16[(2u * ic * 2u) + 1];
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+    /*  Reading i0+fftLen/4 */
+    /* input is down scale by 4 to avoid overflow */
+    /* T0 = yb, T1 =  xb */
+    T0 = pSrc16[i1 * 2u] >> 2;
+    T1 = pSrc16[(i1 * 2u) + 1] >> 2;
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc16[i1 * 2u] = out1;
+    pSrc16[(i1 * 2u) + 1] = out2;
+
+    /*  Butterfly calculations */
+    /* input is down scale by 4 to avoid overflow */
+    /* U0 = yd, U1 = xd */
+    U0 = pSrc16[i3 * 2u] >> 2;
+    U1 = pSrc16[(i3 * 2u) + 1] >> 2;
+    /* T0 = yb-yd */
+    T0 = __SSAT(T0 - U0, 16);
+    /* T1 = xb-xd */
+    T1 = __SSAT(T1 - U1, 16);
+
+    /* R1 = (ya-yc) + (xb- xd),  R0 = (xa-xc) - (yb-yd)) */
+    R0 = (short) __SSAT((q31_t) (S0 - T1), 16);
+    R1 = (short) __SSAT((q31_t) (S1 + T0), 16);
+
+    /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */
+    S0 = (short) __SSAT(((q31_t) S0 + T1), 16u);
+    S1 = (short) __SSAT(((q31_t) S1 - T0), 16u);
+
+    /* co1 & si1 are read from Coefficient pointer */
+    Co1 = pCoef16[ic * 2u];
+    Si1 = pCoef16[(ic * 2u) + 1];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = (short) ((Si1 * S1 + Co1 * S0) >> 16);
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16);
+
+    /* writing output(xb', yb') in little endian format */
+    pSrc16[i2 * 2u] = out1;
+    pSrc16[(i2 * 2u) + 1] = out2;
+
+    /* Co3 & si3 are read from Coefficient pointer */
+    Co3 = pCoef16[3u * (ic * 2u)];
+    Si3 = pCoef16[(3u * (ic * 2u)) + 1];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
+    /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
+    /* writing output(xd', yd') in little endian format */
+    pSrc16[i3 * 2u] = out1;
+    pSrc16[(i3 * 2u) + 1] = out2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      Co1 = pCoef16[ic * 2u];
+      Si1 = pCoef16[(ic * 2u) + 1u];
+      Co2 = pCoef16[2u * (ic * 2u)];
+      Si2 = pCoef16[(2u * (ic * 2u)) + 1u];
+      Co3 = pCoef16[3u * (ic * 2u)];
+      Si3 = pCoef16[(3u * (ic * 2u)) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T0 = pSrc16[i0 * 2u];
+        T1 = pSrc16[(i0 * 2u) + 1u];
+
+        /* Read yc (real), xc(imag) input */
+        S0 = pSrc16[i2 * 2u];
+        S1 = pSrc16[(i2 * 2u) + 1u];
+
+        /* R0 = (ya + yc), R1 = (xa + xc) */
+        R0 = __SSAT(T0 + S0, 16);
+        R1 = __SSAT(T1 + S1, 16);
+
+        /* S0 = (ya - yc), S1 =(xa - xc) */
+        S0 = __SSAT(T0 - S0, 16);
+        S1 = __SSAT(T1 - S1, 16);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+
+        /* T0 = (yb + yd), T1 = (xb + xd) */
+        T0 = __SSAT(T0 + U0, 16);
+        T1 = __SSAT(T1 + U1, 16);
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+        out2 = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+        pSrc16[i0 * 2u] = out1;
+        pSrc16[(2u * i0) + 1u] = out2;
+
+        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+        R0 = (R0 >> 1u) - (T0 >> 1u);
+        R1 = (R1 >> 1u) - (T1 >> 1u);
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        pSrc16[i1 * 2u] = out1;
+        pSrc16[(i1 * 2u) + 1u] = out2;
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = yb-yd, T1 = xb-xd */
+        T0 = __SSAT(T0 - U0, 16);
+        T1 = __SSAT(T1 - U1, 16);
+
+        /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */
+        R0 = (S0 >> 1u) - (T1 >> 1u);
+        R1 = (S1 >> 1u) + (T0 >> 1u);
+
+        /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */
+        S0 = (S0 >> 1u) + (T1 >> 1u);
+        S1 = (S1 >> 1u) - (T0 >> 1u);
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = (short) ((Co1 * S0 + Si1 * S1) >> 16u);
+
+        out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16u);
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        pSrc16[i2 * 2u] = out1;
+        pSrc16[(i2 * 2u) + 1u] = out2;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+        out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
+
+        out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
+        /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+        pSrc16[i3 * 2u] = out1;
+        pSrc16[(i3 * 2u) + 1u] = out2;
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /* end of middle stage process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u];
+    T1 = pSrc16[(i0 * 2u) + 1u];
+
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u];
+    S1 = pSrc16[(i2 * 2u) + 1u];
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+
+    /* T0 = (yb + yd), T1 = (xb + xd)) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+    R0 = (R0 >> 1u) - (T0 >> 1u);
+    R1 = (R1 >> 1u) - (T1 >> 1u);
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc16[i1 * 2u] = R0;
+    pSrc16[(i1 * 2u) + 1u] = R1;
+
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+    /* T0 = (yb - yd), T1 = (xb - xd)  */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    pSrc16[i2 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    pSrc16[i3 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+  }
+
+  /* end of last stage process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**   
+ * @brief  Core function for the Q15 CIFFT butterfly process.  
+ * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef16         points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+/*   
+* Radix-4 IFFT algorithm used is :   
+*   
+* CIFFT uses same twiddle coefficients as CFFT function   
+*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]   
+*   
+*   
+* IFFT is implemented with following changes in equations from FFT   
+*   
+* Input real and imaginary data:   
+* x(n) = xa + j * ya   
+* x(n+N/4 ) = xb + j * yb   
+* x(n+N/2 ) = xc + j * yc   
+* x(n+3N 4) = xd + j * yd   
+*   
+*   
+* Output real and imaginary data:   
+* x(4r) = xa'+ j * ya'   
+* x(4r+1) = xb'+ j * yb'   
+* x(4r+2) = xc'+ j * yc'   
+* x(4r+3) = xd'+ j * yd'   
+*   
+*   
+* Twiddle factors for radix-4 IFFT:   
+* Wn = co1 + j * (si1)   
+* W2n = co2 + j * (si2)   
+* W3n = co3 + j * (si3)   
+   
+* The real and imaginary output values for the radix-4 butterfly are   
+* xa' = xa + xb + xc + xd   
+* ya' = ya + yb + yc + yd   
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)   
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)   
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)   
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)   
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)   
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)   
+*   
+*/
+
+void arm_radix4_butterfly_inverse_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t R, S, T, U;
+  q31_t C1, C2, C3, out1, out2;
+  q31_t *pSrc, *pCoeff;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+  q15_t in;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  pointer initializations for SIMD calculations */
+  pSrc = (q31_t *) pSrc16;
+  pCoeff = (q31_t *) pCoef16;
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  Start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = pSrc[i0];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* Read yc (real), xc(imag) input */
+    S = pSrc[i2];
+    in = ((int16_t) (S & 0xFFFF)) >> 2;
+    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* R = packed((ya + yc), (xa + xc) ) */
+    R = __QADD16(T, S);
+    /* S = packed((ya - yc), (xa - xc) ) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* T = packed((yb + yd), (xb + xd) ) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc[i0] = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+    R = __QSUB16(R, T);
+    /* co2 & si2 are read from SIMD Coefficient pointer */
+    C2 = pCoeff[2u * ic];
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+    out1 = __SMUSD(C2, R) >> 16u;
+    /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+    out2 = __SMUADX(C2, R);
+
+#else
+
+    /* xc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+    out1 = __SMUADX(C2, R) >> 16u;
+    /* yc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+    out2 = __SMUSD(-C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /*  Reading i0+fftLen/4 */
+    /* T = packed(yb, xb) */
+    T = pSrc[i1];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc[i1] = (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Butterfly calculations */
+    /* U = packed(yd, xd) */
+    U = pSrc[i3];
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* T = packed(yb-yd, xb-xd) */
+    T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* R = packed((ya-yc) - (xb- xd) , (xa-xc) + (yb-yd)) */
+    R = __QSAX(S, T);
+    /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+    S = __QASX(S, T);
+
+#else
+
+    /* R = packed((ya-yc) - (xb- xd) , (xa-xc) + (yb-yd)) */
+    R = __QASX(S, T);
+    /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+    S = __QSAX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* co1 & si1 are read from SIMD Coefficient pointer */
+    C1 = pCoeff[ic];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+    out1 = __SMUSD(C1, S) >> 16u;
+    /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+    out2 = __SMUADX(C1, S);
+
+#else
+
+    /* xb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+    out1 = __SMUADX(C1, S) >> 16u;
+    /* yb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+    out2 = __SMUSD(-C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xb', yb') in little endian format */
+    pSrc[i2] = ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+
+    /* co3 & si3 are read from SIMD Coefficient pointer */
+    C3 = pCoeff[3u * ic];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) */
+    out1 = __SMUSD(C3, R) >> 16u;
+    /* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) */
+    out2 = __SMUADX(C3, R);
+
+#else
+
+    /* xd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) */
+    out1 = __SMUADX(C3, R) >> 16u;
+    /* yd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) */
+    out2 = __SMUSD(-C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xd', yd') in little endian format */
+    pSrc[i3] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /*  End of first stage process */
+
+  /* data is in 4.11(q11) format */
+
+
+  /*  Start of Middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      C1 = pCoeff[ic];
+      C2 = pCoeff[2u * ic];
+      C3 = pCoeff[3u * ic];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T = pSrc[i0];
+
+        /* Read yc (real), xc(imag) input */
+        S = pSrc[i2];
+
+
+        /* R = packed( (ya + yc), (xa + xc)) */
+        R = __QADD16(T, S);
+        /* S = packed((ya - yc), (xa - xc)) */
+        S = __QSUB16(T, S);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T = pSrc[i1];
+
+        /* Read yd (real), xd(imag) input */
+        U = pSrc[i3];
+
+
+        /* T = packed( (yb + yd), (xb + xd)) */
+        T = __QADD16(T, U);
+
+        /*  writing the butterfly processed i0 sample */
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = __SHADD16(R, T);
+        in = ((int16_t) (out1 & 0xFFFF)) >> 1;
+        out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+        pSrc[i0] = out1;
+
+
+
+        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+        R = __SHSUB16(R, T);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+        out1 = __SMUSD(C2, R) >> 16u;
+        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        out2 = __SMUADX(C2, R);
+
+#else
+
+        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        out1 = __SMUADX(R, C2) >> 16u;
+        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+        out2 = __SMUSD(-C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T = pSrc[i1];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        pSrc[i1] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly calculations */
+        /* Read yd (real), xd(imag) input */
+        U = pSrc[i3];
+
+        /* T = packed(yb-yd, xb-xd) */
+        T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* R = packed((ya-yc) - (xb- xd) , (xa-xc) + (yb-yd)) */
+        R = __SHSAX(S, T);
+
+        /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+        S = __SHASX(S, T);
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUSD(C1, S) >> 16u;
+        out2 = __SMUADX(C1, S);
+
+#else
+
+        /* R = packed((ya-yc) - (xb- xd) , (xa-xc) + (yb-yd)) */
+        R = __SHASX(S, T);
+
+        /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+        S = __SHSAX(S, T);
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUADX(S, C1) >> 16u;
+        out2 = __SMUSD(-C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+        /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+        pSrc[i2] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(C3, R) >> 16u;
+        out2 = __SMUADX(C3, R);
+
+#else
+
+        out1 = __SMUADX(C3, R) >> 16u;
+        out2 = __SMUSD(-C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) */
+        /* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) */
+        pSrc[i3] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /*  End of Middle stages process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point   */
+  /* data is in 6.10(q10) format for the 64 point  */
+  /* data is in 4.12(q12) format for the 16 point  */
+
+  /* start of last stage process */
+
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = pSrc[i0];
+    /* Read yc (real), xc(imag) input */
+    S = pSrc[i2];
+
+    /* R = packed((ya + yc), (xa + xc)) */
+    R = __QADD16(T, S);
+    /* S = packed((ya - yc), (xa - xc)) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc[i0] = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+    R = __SHSUB16(R, T);
+
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc[i1] = R;
+
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+    /* T = packed( (yb - yd), (xb - xd))  */
+    T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd) */
+    /* yb' = (ya+xb-yc-xd) */
+    pSrc[i2] = __SHASX(S, T);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd) */
+    /* yd' = (ya-xb-yc+xd) */
+    pSrc[i3] = __SHSAX(S, T);
+
+
+#else
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd) */
+    /* yb' = (ya+xb-yc-xd) */
+    pSrc[i2] = __SHSAX(S, T);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd) */
+    /* yd' = (ya-xb-yc+xd) */
+    pSrc[i3] = __SHASX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+  }
+  /* end of last stage  process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  Start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u] >> 2u;
+    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u] >> 2u;
+    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+    /* Read yd (real), xd(imag) input */
+    /* input is down scale by 4 to avoid overflow */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+    /* T0 = (yb + yd), T1 = (xb + xd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */
+    R0 = __SSAT(R0 - T0, 16u);
+    R1 = __SSAT(R1 - T1, 16u);
+    /* co2 & si2 are read from Coefficient pointer */
+    Co2 = pCoef16[2u * ic * 2u];
+    Si2 = pCoef16[(2u * ic * 2u) + 1u];
+    /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+    out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16u);
+    /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+    out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16u);
+
+    /*  Reading i0+fftLen/4 */
+    /* input is down scale by 4 to avoid overflow */
+    /* T0 = yb, T1 = xb */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc16[i1 * 2u] = out1;
+    pSrc16[(i1 * 2u) + 1u] = out2;
+
+    /*  Butterfly calculations */
+    /* input is down scale by 4 to avoid overflow */
+    /* U0 = yd, U1 = xd) */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+    /* T0 = yb-yd, T1 = xb-xd) */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+    /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+    R0 = (short) __SSAT((q31_t) (S0 + T1), 16);
+    R1 = (short) __SSAT((q31_t) (S1 - T0), 16);
+    /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+    S0 = (short) __SSAT((q31_t) (S0 - T1), 16);
+    S1 = (short) __SSAT((q31_t) (S1 + T0), 16);
+
+    /* co1 & si1 are read from Coefficient pointer */
+    Co1 = pCoef16[ic * 2u];
+    Si1 = pCoef16[(ic * 2u) + 1u];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+    out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
+    /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+    out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
+    /* writing output(xb', yb') in little endian format */
+    pSrc16[i2 * 2u] = out1;
+    pSrc16[(i2 * 2u) + 1u] = out2;
+
+    /* Co3 & si3 are read from Coefficient pointer */
+    Co3 = pCoef16[3u * ic * 2u];
+    Si3 = pCoef16[(3u * ic * 2u) + 1u];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+    out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
+    /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+    out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
+    /* writing output(xd', yd') in little endian format */
+    pSrc16[i3 * 2u] = out1;
+    pSrc16[(i3 * 2u) + 1u] = out2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /*  End of first stage process */
+
+  /* data is in 4.11(q11) format */
+
+
+  /*  Start of Middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      Co1 = pCoef16[ic * 2u];
+      Si1 = pCoef16[(ic * 2u) + 1u];
+      Co2 = pCoef16[2u * ic * 2u];
+      Si2 = pCoef16[2u * ic * 2u + 1u];
+      Co3 = pCoef16[3u * ic * 2u];
+      Si3 = pCoef16[(3u * ic * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T0 = pSrc16[i0 * 2u];
+        T1 = pSrc16[(i0 * 2u) + 1u];
+
+        /* Read yc (real), xc(imag) input */
+        S0 = pSrc16[i2 * 2u];
+        S1 = pSrc16[(i2 * 2u) + 1u];
+
+
+        /* R0 = (ya + yc), R1 = (xa + xc) */
+        R0 = __SSAT(T0 + S0, 16u);
+        R1 = __SSAT(T1 + S1, 16u);
+        /* S0 = (ya - yc), S1 = (xa - xc) */
+        S0 = __SSAT(T0 - S0, 16u);
+        S1 = __SSAT(T1 - S1, 16u);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = (yb + yd), T1 = (xb + xd) */
+        T0 = __SSAT(T0 + U0, 16u);
+        T1 = __SSAT(T1 + U1, 16u);
+
+        /*  writing the butterfly processed i0 sample */
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        pSrc16[i0 * 2u] = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+        pSrc16[(i0 * 2u) + 1u] = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+        R0 = (R0 >> 1u) - (T0 >> 1u);
+        R1 = (R1 >> 1u) - (T1 >> 1u);
+
+        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+        out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16);
+        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16);
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        pSrc16[i1 * 2u] = out1;
+        pSrc16[(i1 * 2u) + 1u] = out2;
+
+        /*  Butterfly calculations */
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = yb-yd, T1 = xb-xd) */
+        T0 = __SSAT(T0 - U0, 16u);
+        T1 = __SSAT(T1 - U1, 16u);
+
+        /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+        R0 = (S0 >> 1u) + (T1 >> 1u);
+        R1 = (S1 >> 1u) - (T0 >> 1u);
+
+        /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+        S0 = (S0 >> 1u) - (T1 >> 1u);
+        S1 = (S1 >> 1u) + (T0 >> 1u);
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
+        out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
+        /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+        /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+        pSrc16[i2 * 2u] = out1;
+        pSrc16[(i2 * 2u) + 1u] = out2;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+        out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
+
+        out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
+        /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+        /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+        pSrc16[i3 * 2u] = out1;
+        pSrc16[(i3 * 2u) + 1u] = out2;
+
+
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /*  End of Middle stages process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point   */
+  /* data is in 6.10(q10) format for the 64 point  */
+  /* data is in 4.12(q12) format for the 16 point  */
+
+  /* start of last stage process */
+
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u];
+    T1 = pSrc16[(i0 * 2u) + 1u];
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u];
+    S1 = pSrc16[(i2 * 2u) + 1u];
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+
+    /* T0 = (yb + yd), T1 = (xb + xd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+    R0 = (R0 >> 1u) - (T0 >> 1u);
+    R1 = (R1 >> 1u) - (T1 >> 1u);
+
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc16[i1 * 2u] = R0;
+    pSrc16[(i1 * 2u) + 1u] = R1;
+
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+    /* T0 = (yb - yd), T1 = (xb - xd) */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd) */
+    /* yb' = (ya+xb-yc-xd) */
+    pSrc16[i2 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd) */
+    /* yd' = (ya-xb-yc+xd) */
+    pSrc16[i3 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+  }
+  /* end of last stage  process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/*   
+   * @brief  In-place bit reversal function.  
+   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.  
+   * @param[in]      fftLen       length of the FFT.  
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table  
+   * @param[in]      *pBitRevTab  points to bit reversal table.  
+   * @return none.  
+ */
+
+void arm_bitreversal_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab)
+{
+  q31_t *pSrc = (q31_t *) pSrc16;
+  q31_t in;
+  uint32_t fftLenBy2, fftLenBy2p1;
+  uint32_t i, j;
+
+  /*  Initializations */
+  j = 0u;
+  fftLenBy2 = fftLen / 2u;
+  fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+  /* Bit Reversal Implementation */
+  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+  {
+    if(i < j)
+    {
+      /*  pSrc[i] <-> pSrc[j]; */
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[i];
+      pSrc[i] = pSrc[j];
+      pSrc[j] = in;
+
+      /*  pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1];  */
+      /*  pSrc[i + fftLenBy2p1+1u] <-> pSrc[j + fftLenBy2p1+1u] */
+      in = pSrc[i + fftLenBy2p1];
+      pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1];
+      pSrc[j + fftLenBy2p1] = in;
+    }
+
+    /*  pSrc[i+1u] <-> pSrc[j+fftLenBy2];         */
+    /*  pSrc[i+2] <-> pSrc[j+fftLenBy2+1u]  */
+    in = pSrc[i + 1u];
+    pSrc[i + 1u] = pSrc[j + fftLenBy2];
+    pSrc[j + fftLenBy2] = in;
+
+    /*  Reading the index for the bit reversal */
+    j = *pBitRevTab;
+
+    /*  Updating the bit reversal index depending on the fft length  */
+    pBitRevTab += bitRevFactor;
+  }
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
new file mode 100644
index 0000000..ad02656
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
@@ -0,0 +1,906 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_q31.c   
+*   
+* Description:	This file has function definition of Radix-4 FFT & IFFT function and   
+*				In-place bit reversal using bit reversal table   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @brief Processing function for the Q31 CFFT/CIFFT.   
+ * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.  
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
+ * @return none.   
+ *    
+ * \par Input and output formats:   
+ * \par   
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.  
+ * Hence the output format is different for different FFT sizes.   
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:  
+ * \par  
+ * \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT"   
+ * \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT"   
+ *   
+ */
+
+void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc)
+{
+  if(S->ifftFlag == 1u)
+  {
+    /* Complex IFFT radix-4 */
+    arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier);
+  }
+  else
+  {
+    /* Complex FFT radix-4 */
+    arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
+
+/*   
+* Radix-4 FFT algorithm used is :   
+*   
+* Input real and imaginary data:   
+* x(n) = xa + j * ya   
+* x(n+N/4 ) = xb + j * yb   
+* x(n+N/2 ) = xc + j * yc   
+* x(n+3N 4) = xd + j * yd   
+*   
+*   
+* Output real and imaginary data:   
+* x(4r) = xa'+ j * ya'   
+* x(4r+1) = xb'+ j * yb'   
+* x(4r+2) = xc'+ j * yc'   
+* x(4r+3) = xd'+ j * yd'   
+*   
+*   
+* Twiddle factors for radix-4 FFT:   
+* Wn = co1 + j * (- si1)   
+* W2n = co2 + j * (- si2)   
+* W3n = co3 + j * (- si3)   
+*   
+*  Butterfly implementation:   
+* xa' = xa + xb + xc + xd   
+* ya' = ya + yb + yc + yd   
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)   
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)   
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)   
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)   
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)   
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)   
+*   
+*/
+
+/**   
+ * @brief  Core function for the Q31 CFFT butterfly process.  
+ * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+void arm_radix4_butterfly_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier)
+{
+  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+
+  /* start of first stage process */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSrc[(2u * i0)] >> 4u) + (pSrc[(2u * i2)] >> 4u);
+    /* xa - xc */
+    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+    /* ya + yc */
+    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+    /* ya - yc */
+    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+    /* xb + xd */
+    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+    /* xb - xd */
+    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2u * ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+    /* (xa - xc) + (yb - yd) */
+    r1 = r2 + t1;
+    /* (xa - xc) - (yb - yd) */
+    r2 = r2 - t1;
+
+    /* (ya - yc) - (xb - xd) */
+    s1 = s2 - t2;
+    /* (ya - yc) + (xb - xd) */
+    s2 = s2 + t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3u * ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /* end of first stage process */
+
+  /* data is in 5.27(q27) format */
+
+
+  /* start of Middle stages process */
+
+
+  /* each stage in middle stages provides two down scaling of the input */
+
+  twidCoefModifier <<= 2u;
+
+
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSrc[2u * i0] + pSrc[2u * i2];
+        /* xa - xc */
+        r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = (r1 + t1) >> 2u;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                         ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /* End of Middle stages process */
+
+  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+  /* start of Last stage process */
+
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xb */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+    /* xa - xb */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1;
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1;
+
+    /* (xa+yb-xc-yd) */
+    r1 = r2 + t1;
+    /* (xa-yb-xc+yd) */
+    r2 = r2 - t1;
+
+    /* (ya-xb-yc+xd) */
+    s1 = s2 - t2;
+    /* (ya+xb-yc-xd) */
+    s2 = s2 + t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1;
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1;
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2;
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2;
+
+
+  }
+
+  /* output is in 11.21(q21) format for the 1024 point */
+  /* output is in 9.23(q23) format for the 256 point */
+  /* output is in 7.25(q25) format for the 64 point */
+  /* output is in 5.27(q27) format for the 16 point */
+
+  /* End of last stage process */
+
+}
+
+
+/**   
+ * @brief  Core function for the Q31 CIFFT butterfly process.  
+ * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+
+/*   
+* Radix-4 IFFT algorithm used is :   
+*   
+* CIFFT uses same twiddle coefficients as CFFT Function   
+*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]   
+*   
+*   
+* IFFT is implemented with following changes in equations from FFT   
+*   
+* Input real and imaginary data:   
+* x(n) = xa + j * ya   
+* x(n+N/4 ) = xb + j * yb   
+* x(n+N/2 ) = xc + j * yc   
+* x(n+3N 4) = xd + j * yd   
+*   
+*   
+* Output real and imaginary data:   
+* x(4r) = xa'+ j * ya'   
+* x(4r+1) = xb'+ j * yb'   
+* x(4r+2) = xc'+ j * yc'   
+* x(4r+3) = xd'+ j * yd'   
+*   
+*   
+* Twiddle factors for radix-4 IFFT:   
+* Wn = co1 + j * (si1)   
+* W2n = co2 + j * (si2)   
+* W3n = co3 + j * (si3)   
+   
+* The real and imaginary output values for the radix-4 butterfly are   
+* xa' = xa + xb + xc + xd   
+* ya' = ya + yb + yc + yd   
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)   
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)   
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)   
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)   
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)   
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)   
+*   
+*/
+
+void arm_radix4_butterfly_inverse_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier)
+{
+  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+  /* input is be 1.31(q31) format for all FFT sizes */
+  /* Total process is divided into three stages */
+  /* process first stage, middle stages, & last stage */
+
+  /* Start of first stage process */
+
+  /* Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  do
+  {
+
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSrc[2u * i0] >> 4u) + (pSrc[2u * i2] >> 4u);
+    /* xa - xc */
+    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+    /* ya + yc */
+    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+    /* ya - yc */
+    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+    /* xb + xd */
+    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+    /* xb - xd */
+    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2u * ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[2u * i1 + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
+                          ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+    /* (xa - xc) - (yb - yd) */
+    r1 = r2 - t1;
+    /* (xa - xc) + (yb - yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb - xd) */
+    s1 = s2 + t2;
+    /* (ya - yc) - (xb - xd) */
+    s2 = s2 - t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3u * ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /* data is in 5.27(q27) format */
+  /* each stage provides two down scaling of the input */
+
+
+  /* Start of Middle stages process */
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    for (j = 0; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSrc[2u * i0] + pSrc[2u * i2];
+        /* xa - xc */
+        r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = (r1 + t1) >> 2u;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
+                         ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] =
+          (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
+           ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[(2u * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                           ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /* End of Middle stages process */
+
+  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+  /* Start of last stage process */
+
+
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1;
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1;
+
+    /* (xa - xc) - (yb-yd) */
+    r1 = r2 - t1;
+
+    /* (xa - xc) + (yb-yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb-xd) */
+    s1 = s2 + t2;
+
+    /* (ya - yc) - (xb-xd) */
+    s2 = s2 - t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1;
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1;
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2;
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2;
+
+  }
+
+  /* output is in 11.21(q21) format for the 1024 point */
+  /* output is in 9.23(q23) format for the 256 point */
+  /* output is in 7.25(q25) format for the 64 point */
+  /* output is in 5.27(q27) format for the 16 point */
+
+  /* End of last stage process */
+}
+
+
+/*   
+ * @brief  In-place bit reversal function.  
+ * @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.  
+ * @param[in]      fftLen       length of the FFT.  
+ * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table  
+ * @param[in]      *pBitRevTab  points to bit reversal table.  
+ * @return none.  
+ */
+
+void arm_bitreversal_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTable)
+{
+  uint32_t fftLenBy2, fftLenBy2p1, i, j;
+  q31_t in;
+
+  /*  Initializations      */
+  j = 0u;
+  fftLenBy2 = fftLen / 2u;
+  fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+  /* Bit Reversal Implementation */
+  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+  {
+    if(i < j)
+    {
+      /*  pSrc[i] <-> pSrc[j]; */
+      in = pSrc[2u * i];
+      pSrc[2u * i] = pSrc[2u * j];
+      pSrc[2u * j] = in;
+
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[(2u * i) + 1u];
+      pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+      pSrc[(2u * j) + 1u] = in;
+
+      /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+      in = pSrc[2u * (i + fftLenBy2p1)];
+      pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+      pSrc[2u * (j + fftLenBy2p1)] = in;
+
+      /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+      in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+        pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+    }
+
+    /*  pSrc[i+1u] <-> pSrc[j+1u] */
+    in = pSrc[2u * (i + 1u)];
+    pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+    pSrc[2u * (j + fftLenBy2)] = in;
+
+    /*  pSrc[i+2u] <-> pSrc[j+2u] */
+    in = pSrc[(2u * (i + 1u)) + 1u];
+    pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+    pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+    /*  Reading the index for the bit reversal */
+    j = *pBitRevTable;
+
+    /*  Updating the bit reversal index depending on the fft length */
+    pBitRevTable += bitRevFactor;
+  }
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
new file mode 100644
index 0000000..c9a3ec5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
@@ -0,0 +1,450 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_f32.c   
+*   
+* Description:	Processing function of DCT4 & IDCT4 F32.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @defgroup DCT4_IDCT4 DCT Type IV Functions   
+ * Representation of signals by minimum number of values is important for storage and transmission.   
+ * The possibility of large discontinuity between the beginning and end of a period of a signal   
+ * in DFT can be avoided by extending the signal so that it is even-symmetric.   
+ * Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the   
+ * spectrum and is very widely used in signal and image coding applications.   
+ * The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.   
+ * DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.   
+ *   
+ * DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.   
+ * Reordering of the input data makes the computation of DCT just a problem of   
+ * computing the DFT of a real signal with a few additional operations.   
+ * This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.   
+ *    
+ * DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.   
+ * DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.   
+ * DCT2 implementation can be described in the following steps:   
+ * - Re-ordering input   
+ * - Calculating Real FFT   
+ * - Multiplication of weights and Real FFT output and getting real part from the product.   
+ *   
+ * This process is explained by the block diagram below:   
+ * \image html DCT4.gif "Discrete Cosine Transform - type-IV"   
+ *   
+ * \par Algorithm:   
+ * The N-point type-IV DCT is defined as a real, linear transformation by the formula:   
+ * \image html DCT4Equation.gif   
+ * where k = 0,1,2,.....N-1   
+ *\par   
+ * Its inverse is defined as follows:   
+ * \image html IDCT4Equation.gif   
+ * where n = 0,1,2,.....N-1   
+ *\par   
+ * The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).   
+ * The symmetry of the transform matrix indicates that the fast algorithms for the forward   
+ * and inverse transform computation are identical.   
+ * Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.   
+ *   
+ * \par Lengths supported by the transform:   
+ *  As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32().   
+ * The library provides separate functions for Q15, Q31, and floating-point data types.   
+ * \par Instance Structure   
+ * The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.   
+ * A separate instance structure must be defined for each transform.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32().   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Manually initialize the instance structure as follows:   
+ * 
   
+ *arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
+ *arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};  
+ *arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};  
+ * 
  
+ * where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4;  
+ * \c normalize is normalizing factor used and is equal to sqrt(2/N);   
+ * \c pTwiddle points to the twiddle factor table;  
+ * \c pCosFactor points to the cosFactor table;  
+ * \c pRfft points to the real FFT instance;  
+ * \c pCfft points to the complex FFT instance;  
+ * The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()  
+ * and arm_rfft_f32() respectively for details regarding static initialization.  
+ *  
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the DCT4 transform functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+ /**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the floating-point DCT4/IDCT4.  
+ * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.  
+ * @param[in]       *pState        points to state buffer.  
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.  
+ * @return none.  
+ */
+
+void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer)
+{
+  uint32_t i;                                    /* Loop counter */
+  float32_t *weights = S->pTwiddle;              /* Pointer to the Weights table */
+  float32_t *cosFact = S->pCosFactor;            /* Pointer to the cos factors table */
+  float32_t *pS1, *pS2, *pbuff;                  /* Temporary pointers for input buffer and pState buffer */
+  float32_t in;                                  /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)   
+   * along with some pre-processing and post-processing.   
+   * Computational procedure is explained as follows:   
+   * (a) Pre-processing involves multiplying input with cos factor,   
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))   
+   *              where,   
+   *                 r(n) -- output of preprocessing   
+   *                 u(n) -- input to preprocessing(actual Source buffer)   
+   * (b) Calculation of DCT2 using FFT is divided into three steps:   
+   *                  Step1: Re-ordering of even and odd elements of input.   
+   *                  Step2: Calculating FFT of the re-ordered input.   
+   *                  Step3: Taking the real part of the product of FFT output and weights.   
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:   
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *                        where,   
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output   
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).   
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);
+  arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------   
+   * Step1: Re-ordering of even and odd elements as,   
+   *             pState[i] =  pInlineBuffer[2*i] and   
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2   
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = (uint32_t) S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.   
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+        /*----------------------------------------------------------------------   
+	 *  Step3: Multiply the FFT output with the weights.   
+	 *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = ((uint32_t) S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ * (float32_t) 0.5;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  i = ((uint32_t) S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = (uint32_t) S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+        /*----------------------------------------------------------------------   
+	 *  Step3: Multiply the FFT output with the weights.   
+	 *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ * (float32_t) 0.5;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* Initializing the loop counter */
+  i = ((uint32_t) S->N - 1u);
+
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
new file mode 100644
index 0000000..af576f2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
@@ -0,0 +1,4208 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_init_f32.c   
+*   
+* Description:	Initialization function of DCT-4 & IDCT4 F32   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/*   
+* @brief  Weights Table   
+*/
+
+/**   
+* \par   
+* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
   
+* \par   
+* C command to generate the table   
+* 
   
+* for(i = 0; i< N; i++)   
+* {   
+*    weights[2*i]= cos(i*c);   
+*    weights[(2*i)+1]= -sin(i * c);   
+* } 
   
+* \par   
+* Where N is the Number of weights to be calculated and c is pi/(2*N)   
+* \par   
+* In the tables below the real and imaginary values are placed alternatively, hence the   
+* array length is 2*N.   
+*/
+
+static const float32_t Weights_128[256] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f,
+  -0.012271538285719925f,
+  0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f,
+  -0.036807222941358832f,
+  0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f,
+  -0.061320736302208578f,
+  0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f,
+  -0.085797312344439894f,
+  0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f,
+  -0.110222207293883060f,
+  0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f,
+  -0.134580708507126170f,
+  0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f,
+  -0.158858143333861450f,
+  0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f,
+  -0.183039887955140950f,
+  0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f,
+  -0.207111376192218560f,
+  0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f,
+  -0.231058108280671110f,
+  0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f,
+  -0.254865659604514570f,
+  0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f,
+  -0.278519689385053060f,
+  0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f,
+  -0.302005949319228080f,
+  0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f,
+  -0.325310292162262930f,
+  0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f,
+  -0.348418680249434560f,
+  0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f,
+  -0.371317193951837540f,
+  0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f,
+  -0.393992040061048100f,
+  0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f,
+  -0.416429560097637150f,
+  0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f,
+  -0.438616238538527660f,
+  0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f,
+  -0.460538710958240010f,
+  0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f,
+  -0.482183772079122720f,
+  0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f,
+  -0.503538383725717580f,
+  0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f,
+  -0.524589682678468950f,
+  0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f,
+  -0.545324988422046460f,
+  0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f,
+  -0.565731810783613120f,
+  0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f,
+  -0.585797857456438860f,
+  0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f,
+  -0.605511041404325550f,
+  0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f,
+  -0.624859488142386340f,
+  0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f,
+  -0.643831542889791390f,
+  0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f,
+  -0.662415777590171780f,
+  0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f,
+  -0.680600997795453020f,
+  0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f,
+  -0.698376249408972920f,
+  0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f,
+  -0.715730825283818590f,
+  0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f,
+  -0.732654271672412820f,
+  0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f,
+  -0.749136394523459260f,
+  0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f,
+  -0.765167265622458960f,
+  0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f,
+  -0.780737228572094380f,
+  0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f,
+  -0.795836904608883460f,
+  0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f,
+  -0.810457198252594770f,
+  0.575808191417845340f, -0.817584813151583710f, 0.565731810783613230f,
+  -0.824589302785025290f,
+  0.555570233019602290f, -0.831469612302545240f, 0.545324988422046460f,
+  -0.838224705554837970f,
+  0.534997619887097260f, -0.844853565249707010f, 0.524589682678468840f,
+  -0.851355193105265200f,
+  0.514102744193221660f, -0.857728610000272120f, 0.503538383725717580f,
+  -0.863972856121586700f,
+  0.492898192229784090f, -0.870086991108711350f, 0.482183772079122830f,
+  -0.876070094195406600f,
+  0.471396736825997810f, -0.881921264348354940f, 0.460538710958240010f,
+  -0.887639620402853930f,
+  0.449611329654606600f, -0.893224301195515320f, 0.438616238538527710f,
+  -0.898674465693953820f,
+  0.427555093430282200f, -0.903989293123443340f, 0.416429560097637320f,
+  -0.909167983090522270f,
+  0.405241314004989860f, -0.914209755703530690f, 0.393992040061048100f,
+  -0.919113851690057770f,
+  0.382683432365089840f, -0.923879532511286740f, 0.371317193951837600f,
+  -0.928506080473215480f,
+  0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f,
+  -0.937339011912574960f,
+  0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f,
+  -0.945607325380521280f,
+  0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f,
+  -0.953306040354193750f,
+  0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f,
+  -0.960430519415565790f,
+  0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f,
+  -0.966976471044852070f,
+  0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f,
+  -0.972939952205560070f,
+  0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f,
+  -0.978317370719627650f,
+  0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f,
+  -0.983105487431216290f,
+  0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f,
+  -0.987301418157858430f,
+  0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f,
+  -0.990902635427780010f,
+  0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f,
+  -0.993906970002356060f,
+  0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f,
+  -0.996312612182778000f,
+  0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f,
+  -0.998118112900149180f,
+  0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f,
+  -0.999322384588349540f,
+  0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f,
+  -0.999924701839144500f
+};
+
+static const float32_t Weights_512[1024] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999995293809576190f,
+  -0.003067956762965976f,
+  0.999981175282601110f, -0.006135884649154475f, 0.999957644551963900f,
+  -0.009203754782059819f,
+  0.999924701839144500f, -0.012271538285719925f, 0.999882347454212560f,
+  -0.015339206284988100f,
+  0.999830581795823400f, -0.018406729905804820f, 0.999769405351215280f,
+  -0.021474080275469508f,
+  0.999698818696204250f, -0.024541228522912288f, 0.999618822495178640f,
+  -0.027608145778965740f,
+  0.999529417501093140f, -0.030674803176636626f, 0.999430604555461730f,
+  -0.033741171851377580f,
+  0.999322384588349540f, -0.036807222941358832f, 0.999204758618363890f,
+  -0.039872927587739811f,
+  0.999077727752645360f, -0.042938256934940820f, 0.998941293186856870f,
+  -0.046003182130914623f,
+  0.998795456205172410f, -0.049067674327418015f, 0.998640218180265270f,
+  -0.052131704680283324f,
+  0.998475580573294770f, -0.055195244349689934f, 0.998301544933892890f,
+  -0.058258264500435752f,
+  0.998118112900149180f, -0.061320736302208578f, 0.997925286198596000f,
+  -0.064382630929857465f,
+  0.997723066644191640f, -0.067443919563664051f, 0.997511456140303450f,
+  -0.070504573389613856f,
+  0.997290456678690210f, -0.073564563599667426f, 0.997060070339482960f,
+  -0.076623861392031492f,
+  0.996820299291165670f, -0.079682437971430126f, 0.996571145790554840f,
+  -0.082740264549375692f,
+  0.996312612182778000f, -0.085797312344439894f, 0.996044700901251970f,
+  -0.088853552582524600f,
+  0.995767414467659820f, -0.091908956497132724f, 0.995480755491926940f,
+  -0.094963495329638992f,
+  0.995184726672196930f, -0.098017140329560604f, 0.994879330794805620f,
+  -0.101069862754827820f,
+  0.994564570734255420f, -0.104121633872054590f, 0.994240449453187900f,
+  -0.107172424956808840f,
+  0.993906970002356060f, -0.110222207293883060f, 0.993564135520595300f,
+  -0.113270952177564350f,
+  0.993211949234794500f, -0.116318630911904750f, 0.992850414459865100f,
+  -0.119365214810991350f,
+  0.992479534598709970f, -0.122410675199216200f, 0.992099313142191800f,
+  -0.125454983411546230f,
+  0.991709753669099530f, -0.128498110793793170f, 0.991310859846115440f,
+  -0.131540028702883120f,
+  0.990902635427780010f, -0.134580708507126170f, 0.990485084256457090f,
+  -0.137620121586486040f,
+  0.990058210262297120f, -0.140658239332849210f, 0.989622017463200890f,
+  -0.143695033150294470f,
+  0.989176509964781010f, -0.146730474455361750f, 0.988721691960323780f,
+  -0.149764534677321510f,
+  0.988257567730749460f, -0.152797185258443440f, 0.987784141644572180f,
+  -0.155828397654265230f,
+  0.987301418157858430f, -0.158858143333861450f, 0.986809401814185530f,
+  -0.161886393780111830f,
+  0.986308097244598670f, -0.164913120489969890f, 0.985797509167567480f,
+  -0.167938294974731170f,
+  0.985277642388941220f, -0.170961888760301220f, 0.984748501801904210f,
+  -0.173983873387463820f,
+  0.984210092386929030f, -0.177004220412148750f, 0.983662419211730250f,
+  -0.180022901405699510f,
+  0.983105487431216290f, -0.183039887955140950f, 0.982539302287441240f,
+  -0.186055151663446630f,
+  0.981963869109555240f, -0.189068664149806190f, 0.981379193313754560f,
+  -0.192080397049892440f,
+  0.980785280403230430f, -0.195090322016128250f, 0.980182135968117430f,
+  -0.198098410717953560f,
+  0.979569765685440520f, -0.201104634842091900f, 0.978948175319062200f,
+  -0.204108966092816870f,
+  0.978317370719627650f, -0.207111376192218560f, 0.977677357824509930f,
+  -0.210111836880469610f,
+  0.977028142657754390f, -0.213110319916091360f, 0.976369731330021140f,
+  -0.216106797076219520f,
+  0.975702130038528570f, -0.219101240156869800f, 0.975025345066994120f,
+  -0.222093620973203510f,
+  0.974339382785575860f, -0.225083911359792830f, 0.973644249650811980f,
+  -0.228072083170885730f,
+  0.972939952205560180f, -0.231058108280671110f, 0.972226497078936270f,
+  -0.234041958583543430f,
+  0.971503890986251780f, -0.237023605994367200f, 0.970772140728950350f,
+  -0.240003022448741500f,
+  0.970031253194543970f, -0.242980179903263870f, 0.969281235356548530f,
+  -0.245955050335794590f,
+  0.968522094274417380f, -0.248927605745720150f, 0.967753837093475510f,
+  -0.251897818154216970f,
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+  -0.999430604555461730f,
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+  -0.999618822495178640f,
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+  -0.999769405351215280f,
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+  -0.999882347454212560f,
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+  -0.999957644551963900f,
+  0.006135884649154515f, -0.999981175282601110f, 0.003067956762966138f,
+  -0.999995293809576190f
+};
+
+static const float32_t Weights_2048[4096] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999999705862882230f,
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+  -0.003834942569706228f,
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+  -0.005368906963996343f,
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+  -0.006902858724729756f,
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+  -0.008436794242369799f,
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+  -0.009970709907418031f,
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+  -0.011504602110422714f,
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+  -0.013038467241987334f,
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+  -0.014572301692779064f,
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+  -0.097253814448363271f,
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+  -0.098780408549799623f,
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+  -0.987903369972977790f,
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+  -0.988140083085692570f,
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+  -0.988606533192386450f,
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+  -0.988836269088763540f,
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+  -0.989731939077910570f,
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+  -0.989950035541608990f,
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+  -0.990165802557248400f,
+  0.139139344163826280f, -0.990272812363169110f, 0.138379773577783890f,
+  -0.990379239617108160f,
+  0.137620121586486180f, -0.990485084256456980f, 0.136860388636816430f,
+  -0.990590346218950150f,
+  0.136100575175706200f, -0.990695025442664630f, 0.135340681650134330f,
+  -0.990799121866020370f,
+  0.134580708507126220f, -0.990902635427780010f, 0.133820656193754690f,
+  -0.991005566067049370f,
+  0.133060525157139180f, -0.991107913723276780f, 0.132300315844444680f,
+  -0.991209678336254060f,
+  0.131540028702883280f, -0.991310859846115440f, 0.130779664179711790f,
+  -0.991411458193338540f,
+  0.130019222722233350f, -0.991511473318743900f, 0.129258704777796270f,
+  -0.991610905163495370f,
+  0.128498110793793220f, -0.991709753669099530f, 0.127737441217662280f,
+  -0.991808018777406430f,
+  0.126976696496885980f, -0.991905700430609330f, 0.126215877078990400f,
+  -0.992002798571244520f,
+  0.125454983411546210f, -0.992099313142191800f, 0.124694015942167770f,
+  -0.992195244086673920f,
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+  -0.992385354870851670f,
+  0.122410675199216280f, -0.992479534598709970f, 0.121649416999105540f,
+  -0.992573130476428810f,
+  0.120888087235777220f, -0.992666142448948020f, 0.120126686357101580f,
+  -0.992758570461551140f,
+  0.119365214810991350f, -0.992850414459865100f, 0.118603673045400840f,
+  -0.992941674389860470f,
+  0.117842061508325020f, -0.993032350197851410f, 0.117080380647800550f,
+  -0.993122441830495580f,
+  0.116318630911904880f, -0.993211949234794500f, 0.115556812748755290f,
+  -0.993300872358093280f,
+  0.114794926606510250f, -0.993389211148080650f, 0.114032972933367300f,
+  -0.993476965552789190f,
+  0.113270952177564360f, -0.993564135520595300f, 0.112508864787378830f,
+  -0.993650721000219120f,
+  0.111746711211126660f, -0.993736721940724600f, 0.110984491897163380f,
+  -0.993822138291519660f,
+  0.110222207293883180f, -0.993906970002356060f, 0.109459857849718030f,
+  -0.993991217023329380f,
+  0.108697444013138670f, -0.994074879304879370f, 0.107934966232653760f,
+  -0.994157956797789730f,
+  0.107172424956808870f, -0.994240449453187900f, 0.106409820634187840f,
+  -0.994322357222545810f,
+  0.105647153713410700f, -0.994403680057679100f, 0.104884424643134970f,
+  -0.994484417910747600f,
+  0.104121633872054730f, -0.994564570734255420f, 0.103358781848899700f,
+  -0.994644138481050710f,
+  0.102595869022436280f, -0.994723121104325700f, 0.101832895841466670f,
+  -0.994801518557617110f,
+  0.101069862754827880f, -0.994879330794805620f, 0.100306770211392820f,
+  -0.994956557770116380f,
+  0.099543618660069444f, -0.995033199438118630f, 0.098780408549799664f,
+  -0.995109255753726110f,
+  0.098017140329560770f, -0.995184726672196820f, 0.097253814448363354f,
+  -0.995259612149133390f,
+  0.096490431355252607f, -0.995333912140482280f, 0.095726991499307315f,
+  -0.995407626602534900f,
+  0.094963495329639061f, -0.995480755491926940f, 0.094199943295393190f,
+  -0.995553298765638470f,
+  0.093436335845747912f, -0.995625256380994310f, 0.092672673429913366f,
+  -0.995696628295663520f,
+  0.091908956497132696f, -0.995767414467659820f, 0.091145185496681130f,
+  -0.995837614855341610f,
+  0.090381360877865011f, -0.995907229417411720f, 0.089617483090022917f,
+  -0.995976258112917790f,
+  0.088853552582524684f, -0.996044700901251970f, 0.088089569804770507f,
+  -0.996112557742151130f,
+  0.087325535206192226f, -0.996179828595696870f, 0.086561449236251239f,
+  -0.996246513422315520f,
+  0.085797312344439880f, -0.996312612182778000f, 0.085033124980280414f,
+  -0.996378124838200210f,
+  0.084268887593324127f, -0.996443051350042630f, 0.083504600633152404f,
+  -0.996507391680110820f,
+  0.082740264549375803f, -0.996571145790554840f, 0.081975879791633108f,
+  -0.996634313643869900f,
+  0.081211446809592386f, -0.996696895202896060f, 0.080446966052950097f,
+  -0.996758890430818000f,
+  0.079682437971430126f, -0.996820299291165670f, 0.078917863014785095f,
+  -0.996881121747813850f,
+  0.078153241632794315f, -0.996941357764982160f, 0.077388574275265049f,
+  -0.997001007307235290f,
+  0.076623861392031617f, -0.997060070339482960f, 0.075859103432954503f,
+  -0.997118546826979980f,
+  0.075094300847921291f, -0.997176436735326190f, 0.074329454086845867f,
+  -0.997233740030466160f,
+  0.073564563599667454f, -0.997290456678690210f, 0.072799629836351618f,
+  -0.997346586646633230f,
+  0.072034653246889416f, -0.997402129901275300f, 0.071269634281296415f,
+  -0.997457086409941910f,
+  0.070504573389614009f, -0.997511456140303450f, 0.069739471021907376f,
+  -0.997565239060375750f,
+  0.068974327628266732f, -0.997618435138519550f, 0.068209143658806454f,
+  -0.997671044343441000f,
+  0.067443919563664106f, -0.997723066644191640f, 0.066678655793001543f,
+  -0.997774502010167820f,
+  0.065913352797003930f, -0.997825350411111640f, 0.065148011025878860f,
+  -0.997875611817110150f,
+  0.064382630929857410f, -0.997925286198596000f, 0.063617212959193190f,
+  -0.997974373526346990f,
+  0.062851757564161420f, -0.998022873771486240f, 0.062086265195060247f,
+  -0.998070786905482340f,
+  0.061320736302208648f, -0.998118112900149180f, 0.060555171335947781f,
+  -0.998164851727646240f,
+  0.059789570746640007f, -0.998211003360478190f, 0.059023934984667986f,
+  -0.998256567771495180f,
+  0.058258264500435732f, -0.998301544933892890f, 0.057492559744367684f,
+  -0.998345934821212370f,
+  0.056726821166907783f, -0.998389737407340160f, 0.055961049218520520f,
+  -0.998432952666508440f,
+  0.055195244349690031f, -0.998475580573294770f, 0.054429407010919147f,
+  -0.998517621102622210f,
+  0.053663537652730679f, -0.998559074229759310f, 0.052897636725665401f,
+  -0.998599939930320370f,
+  0.052131704680283317f, -0.998640218180265270f, 0.051365741967162731f,
+  -0.998679908955899090f,
+  0.050599749036899337f, -0.998719012233872940f, 0.049833726340107257f,
+  -0.998757527991183340f,
+  0.049067674327418126f, -0.998795456205172410f, 0.048301593449480172f,
+  -0.998832796853527990f,
+  0.047535484156959261f, -0.998869549914283560f, 0.046769346900537960f,
+  -0.998905715365818290f,
+  0.046003182130914644f, -0.998941293186856870f, 0.045236990298804750f,
+  -0.998976283356469820f,
+  0.044470771854938744f, -0.999010685854073380f, 0.043704527250063421f,
+  -0.999044500659429290f,
+  0.042938256934940959f, -0.999077727752645360f, 0.042171961360348002f,
+  -0.999110367114174890f,
+  0.041405640977076712f, -0.999142418724816910f, 0.040639296235933854f,
+  -0.999173882565716380f,
+  0.039872927587739845f, -0.999204758618363890f, 0.039106535483329839f,
+  -0.999235046864595850f,
+  0.038340120373552791f, -0.999264747286594420f, 0.037573682709270514f,
+  -0.999293859866887790f,
+  0.036807222941358991f, -0.999322384588349540f, 0.036040741520706299f,
+  -0.999350321434199440f,
+  0.035274238898213947f, -0.999377670388002850f, 0.034507715524795889f,
+  -0.999404431433671300f,
+  0.033741171851377642f, -0.999430604555461730f, 0.032974608328897315f,
+  -0.999456189737977340f,
+  0.032208025408304704f, -0.999481186966166950f, 0.031441423540560343f,
+  -0.999505596225325310f,
+  0.030674803176636581f, -0.999529417501093140f, 0.029908164767516655f,
+  -0.999552650779456990f,
+  0.029141508764193740f, -0.999575296046749220f, 0.028374835617672258f,
+  -0.999597353289648380f,
+  0.027608145778965820f, -0.999618822495178640f, 0.026841439699098527f,
+  -0.999639703650710200f,
+  0.026074717829104040f, -0.999659996743959220f, 0.025307980620024630f,
+  -0.999679701762987930f,
+  0.024541228522912264f, -0.999698818696204250f, 0.023774461988827676f,
+  -0.999717347532362190f,
+  0.023007681468839410f, -0.999735288260561680f, 0.022240887414024919f,
+  -0.999752640870248840f,
+  0.021474080275469605f, -0.999769405351215280f, 0.020707260504265912f,
+  -0.999785581693599210f,
+  0.019940428551514598f, -0.999801169887884260f, 0.019173584868322699f,
+  -0.999816169924900410f,
+  0.018406729905804820f, -0.999830581795823400f, 0.017639864115082195f,
+  -0.999844405492175240f,
+  0.016872987947281773f, -0.999857641005823860f, 0.016106101853537263f,
+  -0.999870288328982950f,
+  0.015339206284988220f, -0.999882347454212560f, 0.014572301692779104f,
+  -0.999893818374418490f,
+  0.013805388528060349f, -0.999904701082852900f, 0.013038467241987433f,
+  -0.999914995573113470f,
+  0.012271538285719944f, -0.999924701839144500f, 0.011504602110422875f,
+  -0.999933819875236000f,
+  0.010737659167264572f, -0.999942349676023910f, 0.009970709907418029f,
+  -0.999950291236490480f,
+  0.009203754782059960f, -0.999957644551963900f, 0.008436794242369860f,
+  -0.999964409618118280f,
+  0.007669828739531077f, -0.999970586430974140f, 0.006902858724729877f,
+  -0.999976174986897610f,
+  0.006135884649154515f, -0.999981175282601110f, 0.005368906963996303f,
+  -0.999985587315143200f,
+  0.004601926120448672f, -0.999989411081928400f, 0.003834942569706248f,
+  -0.999992646580707190f,
+  0.003067956762966138f, -0.999995293809576190f, 0.002300969151425887f,
+  -0.999997352766978210f,
+  0.001533980186284766f, -0.999998823451701880f, 0.000766990318742846f,
+  -0.999999705862882230f
+};
+
+/**   
+* \par   
+* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
   
+* \par   
+* C command to generate the table   
+* \par   
+* 
 for(i = 0; i< N; i++)   
+* {   
+*    cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+* } 
   
+* \par   
+* where N is the number of factors to generate and c is pi/(2*N)   
+*/
+static const float32_t cos_factors_128[128] = {
+  0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f,
+  0.999077727752645360f,
+  0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f,
+  0.995767414467659820f,
+  0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f,
+  0.990058210262297120f,
+  0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f,
+  0.981963869109555240f,
+  0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f,
+  0.971503890986251780f,
+  0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f,
+  0.958703474895871600f,
+  0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f,
+  0.943593458161960390f,
+  0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f,
+  0.926210242138311380f,
+  0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f,
+  0.906595704514915330f,
+  0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f,
+  0.884797098430937790f,
+  0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f,
+  0.860866938637767310f,
+  0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f,
+  0.834862874986380010f,
+  0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f,
+  0.806847553543799330f,
+  0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f,
+  0.776888465673232440f,
+  0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f,
+  0.745057785441466060f,
+  0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f,
+  0.711432195745216430f,
+  0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f,
+  0.676092703575316030f,
+  0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f,
+  0.639124444863775730f,
+  0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f,
+  0.600616479383868970f,
+  0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f,
+  0.560661576197336030f,
+  0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f,
+  0.519355990165589530f,
+  0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f,
+  0.476799230063322250f,
+  0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f,
+  0.433093818853152010f,
+  0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f,
+  0.388345046698826300f,
+  0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f,
+  0.342660717311994380f,
+  0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f,
+  0.296150888243623960f,
+  0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f,
+  0.248927605745720260f,
+  0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f,
+  0.201104634842091960f,
+  0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f,
+  0.152797185258443410f,
+  0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f,
+  0.104121633872054730f,
+  0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f,
+  0.055195244349690031f,
+  0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f,
+  0.006135884649154515f
+};
+
+static const float32_t cos_factors_512[512] = {
+  0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f,
+  0.999942349676023910f,
+  0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f,
+  0.999735288260561680f,
+  0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f,
+  0.999377670388002850f,
+  0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f,
+  0.998869549914283560f,
+  0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f,
+  0.998211003360478190f,
+  0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f,
+  0.997402129901275300f,
+  0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f,
+  0.996443051350042630f,
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+  0.995333912140482280f,
+  0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f,
+  0.994074879304879370f,
+  0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f,
+  0.992666142448948020f,
+  0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f,
+  0.991107913723276890f,
+  0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f,
+  0.989400427791380380f,
+  0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f,
+  0.987543941794359230f,
+  0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f,
+  0.985538735312176060f,
+  0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f,
+  0.983385110321551180f,
+  0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f,
+  0.981083391150486710f,
+  0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f,
+  0.978633924429423210f,
+  0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f,
+  0.976037079039039020f,
+  0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f,
+  0.973293246054698250f,
+  0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f,
+  0.970402838687555500f,
+  0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f,
+  0.967366292222328510f,
+  0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f,
+  0.964184063951745830f,
+  0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f,
+  0.960856633107679660f,
+  0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f,
+  0.957384500788975860f,
+  0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f,
+  0.953768189885990330f,
+  0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f,
+  0.950008245001843000f,
+  0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f,
+  0.946105232370403450f,
+  0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f,
+  0.942059739771017310f,
+  0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f,
+  0.937872376439989890f,
+  0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f,
+  0.933543772978836170f,
+  0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f,
+  0.929074581259315860f,
+  0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f,
+  0.924465474325262600f,
+  0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f,
+  0.919717146291227360f,
+  0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f,
+  0.914830312237946200f,
+  0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f,
+  0.909805708104652220f,
+  0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f,
+  0.904644090578246240f,
+  0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f,
+  0.899346236979341570f,
+  0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f,
+  0.893912945145203250f,
+  0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f,
+  0.888345033309596350f,
+  0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f,
+  0.882643339979562790f,
+  0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f,
+  0.876808723809145650f,
+  0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f,
+  0.870842063470078980f,
+  0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f,
+  0.864744257519462380f,
+  0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f,
+  0.858516224264442740f,
+  0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f,
+  0.852158901623919830f,
+  0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f,
+  0.845673246987299070f,
+  0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f,
+  0.839060237070312740f,
+  0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f,
+  0.832320867767929680f,
+  0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f,
+  0.825456154004377550f,
+  0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f,
+  0.818467129580298660f,
+  0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f,
+  0.811354847017063730f,
+  0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f,
+  0.804120377398265810f,
+  0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f,
+  0.796764810208418830f,
+  0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f,
+  0.789289253168885650f,
+  0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f,
+  0.781694832071059390f,
+  0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f,
+  0.773982690606822900f,
+  0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f,
+  0.766153990196312920f,
+  0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f,
+  0.758209909813015280f,
+  0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f,
+  0.750151645806215070f,
+  0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f,
+  0.741980411720831070f,
+  0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f,
+  0.733697438114660370f,
+  0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f,
+  0.725303972373060770f,
+  0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f,
+  0.716801278521099540f,
+  0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f,
+  0.708190637033195400f,
+  0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f,
+  0.699473344640283770f,
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+  0.690650714134534720f,
+  0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f,
+  0.681724074171649820f,
+  0.679476319899365080f, 0.677222170137180450f, 0.674961646102012040f,
+  0.672694769070772970f,
+  0.670421560380173090f, 0.668142041426518560f, 0.665856233665509720f,
+  0.663564158612039880f,
+  0.661265837839992270f, 0.658961292982037320f, 0.656650545729429050f,
+  0.654333617831800550f,
+  0.652010531096959500f, 0.649681307390683190f, 0.647345968636512060f,
+  0.645004536815544040f,
+  0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f,
+  0.635578320488556230f,
+  0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f,
+  0.626056388404343520f,
+  0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f,
+  0.616440174530853650f,
+  0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f,
+  0.606731127034524480f,
+  0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f,
+  0.596930708062196500f,
+  0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f,
+  0.587040393520918080f,
+  0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f,
+  0.577061672855679550f,
+  0.574553355047715760f, 0.572039629324757050f, 0.569520519346947250f,
+  0.566996048825108680f,
+  0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f,
+  0.556845037275160100f,
+  0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f,
+  0.546610166910834860f,
+  0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f,
+  0.536292979065963180f,
+  0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f,
+  0.525895027471084740f,
+  0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f,
+  0.515417878019463150f,
+  0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f,
+  0.504863108531267480f,
+  0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f,
+  0.494232308515959730f,
+  0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f,
+  0.483527078932918740f,
+  0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f,
+  0.472749031950342900f,
+  0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f,
+  0.461899790702462840f,
+  0.459176547521944150f, 0.456448982396883860f, 0.453717121000163930f,
+  0.450980989045103810f,
+  0.448240612285220000f, 0.445496016513981740f, 0.442747227564570130f,
+  0.439994271309633260f,
+  0.437237173661044200f, 0.434475960569655710f, 0.431710658025057370f,
+  0.428941292055329550f,
+  0.426167888726799620f, 0.423390474143796100f, 0.420609074448402510f,
+  0.417823715820212380f,
+  0.415034424476081630f, 0.412241226669883000f, 0.409444148692257590f,
+  0.406643216870369140f,
+  0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f,
+  0.395401478947816300f,
+  0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f,
+  0.384100195016935040f,
+  0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f,
+  0.372741067009515810f,
+  0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f,
+  0.361325805568454340f,
+  0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f,
+  0.349856129790135030f,
+  0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f,
+  0.338333766965541290f,
+  0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f,
+  0.326760452320131790f,
+  0.323859366517852960f, 0.320955232427875210f, 0.318048077385015060f,
+  0.315137928752522440f,
+  0.312224813921825050f, 0.309308760312268780f, 0.306389795370861080f,
+  0.303467946572011370f,
+  0.300543241417273400f, 0.297615707435086310f, 0.294685372180514330f,
+  0.291752263234989370f,
+  0.288816408206049480f, 0.285877834727080730f, 0.282936570457055390f,
+  0.279992643080273380f,
+  0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f,
+  0.268190857063403180f,
+  0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f,
+  0.256348682489942910f,
+  0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f,
+  0.244467902747824210f,
+  0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f,
+  0.232550307038775330f,
+  0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f,
+  0.220597690108873650f,
+  0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f,
+  0.208611851978263460f,
+  0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f,
+  0.196594597670080220f,
+  0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f,
+  0.184547736938619640f,
+  0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f,
+  0.172473083996796030f,
+  0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f,
+  0.160372457242928400f,
+  0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f,
+  0.148247678986896200f,
+  0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f,
+  0.136100575175706200f,
+  0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f,
+  0.123932975118512200f,
+  0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f,
+  0.111746711211126660f,
+  0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f,
+  0.099543618660069444f,
+  0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f,
+  0.087325535206192226f,
+  0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f,
+  0.075094300847921291f,
+  0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f,
+  0.062851757564161420f,
+  0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f,
+  0.050599749036899337f,
+  0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f,
+  0.038340120373552791f,
+  0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f,
+  0.026074717829104040f,
+  0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f,
+  0.013805388528060349f,
+  0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f,
+  0.001533980186284766f
+};
+
+static const float32_t cos_factors_2048[2048] = {
+  0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f,
+  0.999996396822294350f,
+  0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f,
+  0.999983454831937730f,
+  0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f,
+  0.999961100616462820f,
+  0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f,
+  0.999929334386276070f,
+  0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f,
+  0.999888156440373320f,
+  0.999876391416790410f, 0.999864038191687680f, 0.999851096772332190f,
+  0.999837567166337090f,
+  0.999823449381661570f, 0.999808743426610520f, 0.999793449309835270f,
+  0.999777567040332940f,
+  0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f,
+  0.999708156627104880f,
+  0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f,
+  0.999629336579970110f,
+  0.999608161397882110f, 0.999586398172067070f, 0.999564046915327740f,
+  0.999541107640812940f,
+  0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f,
+  0.999443470640077770f,
+  0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f,
+  0.999336426496761240f,
+  0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f,
+  0.999219976218403530f,
+  0.999189394066714920f, 0.999158224117649430f, 0.999126466389543390f,
+  0.999094120901079070f,
+  0.999061187671284600f, 0.999027666719533690f, 0.998993558065545680f,
+  0.998958861729386080f,
+  0.998923577731465780f, 0.998887706092541290f, 0.998851246833715180f,
+  0.998814199976435390f,
+  0.998776565542495610f, 0.998738343554035230f, 0.998699534033539280f,
+  0.998660137003838490f,
+  0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f,
+  0.998496674261694640f,
+  0.998454340040524800f, 0.998411418454391300f, 0.998367909528543820f,
+  0.998323813288577560f,
+  0.998279129760433200f, 0.998233858970396850f, 0.998188000945100300f,
+  0.998141555711520520f,
+  0.998094523296980010f, 0.998046903729146840f, 0.997998697036034390f,
+  0.997949903246001190f,
+  0.997900522387751620f, 0.997850554490335110f, 0.997799999583146470f,
+  0.997748857695925690f,
+  0.997697128858758500f, 0.997644813102075420f, 0.997591910456652630f,
+  0.997538420953611340f,
+  0.997484344624417930f, 0.997429681500884180f, 0.997374431615167150f,
+  0.997318594999768600f,
+  0.997262171687536170f, 0.997205161711661850f, 0.997147565105683480f,
+  0.997089381903483400f,
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+  0.134960705002868830f,
+  0.134200692218792020f, 0.133440600487905820f, 0.132680430257352130f,
+  0.131920181974319760f,
+  0.131159856086043410f, 0.130399453039802740f, 0.129638973282923540f,
+  0.128878417262776660f,
+  0.128117785426777150f, 0.127357078222385570f, 0.126596296097105960f,
+  0.125835439498487020f,
+  0.125074508874121300f, 0.124313504671644300f, 0.123552427338735370f,
+  0.122791277323116900f,
+  0.122030055072553410f, 0.121268761034852550f, 0.120507395657864240f,
+  0.119745959389479630f,
+  0.118984452677632520f, 0.118222875970297250f, 0.117461229715489990f,
+  0.116699514361267840f,
+  0.115937730355727850f, 0.115175878147008180f, 0.114413958183287050f,
+  0.113651970912781920f,
+  0.112889916783750470f, 0.112127796244489750f, 0.111365609743335190f,
+  0.110603357728661910f,
+  0.109841040648882680f, 0.109078658952449240f, 0.108316213087851300f,
+  0.107553703503615710f,
+  0.106791130648307380f, 0.106028494970528530f, 0.105265796918917650f,
+  0.104503036942150550f,
+  0.103740215488939480f, 0.102977333008032250f, 0.102214389948213370f,
+  0.101451386758302160f,
+  0.100688323887153970f, 0.099925201783659226f, 0.099162020896742573f,
+  0.098398781675363881f,
+  0.097635484568517339f, 0.096872130025230527f, 0.096108718494565468f,
+  0.095345250425617742f,
+  0.094581726267515473f, 0.093818146469420494f, 0.093054511480527333f,
+  0.092290821750062355f,
+  0.091527077727284981f, 0.090763279861485704f, 0.089999428601987341f,
+  0.089235524398144139f,
+  0.088471567699340822f, 0.087707558954993645f, 0.086943498614549489f,
+  0.086179387127484922f,
+  0.085415224943307277f, 0.084651012511553700f, 0.083886750281790226f,
+  0.083122438703613077f,
+  0.082358078226646619f, 0.081593669300544638f, 0.080829212374989468f,
+  0.080064707899690932f,
+  0.079300156324387569f, 0.078535558098845590f, 0.077770913672857989f,
+  0.077006223496245585f,
+  0.076241488018856149f, 0.075476707690563416f, 0.074711882961268378f,
+  0.073947014280897269f,
+  0.073182102099402888f, 0.072417146866763538f, 0.071652149032982254f,
+  0.070887109048087787f,
+  0.070122027362133646f, 0.069356904425197236f, 0.068591740687380900f,
+  0.067826536598810966f,
+  0.067061292609636836f, 0.066296009170032283f, 0.065530686730193397f,
+  0.064765325740339871f,
+  0.063999926650714078f, 0.063234489911580136f, 0.062469015973224969f,
+  0.061703505285957416f,
+  0.060937958300107238f, 0.060172375466026218f, 0.059406757234087247f,
+  0.058641104054683348f,
+  0.057875416378229017f, 0.057109694655158132f, 0.056343939335925283f,
+  0.055578150871004817f,
+  0.054812329710889909f, 0.054046476306093640f, 0.053280591107148056f,
+  0.052514674564603257f,
+  0.051748727129028414f, 0.050982749251010900f, 0.050216741381155325f,
+  0.049450703970084824f,
+  0.048684637468439020f, 0.047918542326875327f, 0.047152418996068000f,
+  0.046386267926707213f,
+  0.045620089569500123f, 0.044853884375169933f, 0.044087652794454979f,
+  0.043321395278109784f,
+  0.042555112276904117f, 0.041788804241622082f, 0.041022471623063397f,
+  0.040256114872041358f,
+  0.039489734439384118f, 0.038723330775933762f, 0.037956904332545366f,
+  0.037190455560088091f,
+  0.036423984909444228f, 0.035657492831508264f, 0.034890979777187955f,
+  0.034124446197403423f,
+  0.033357892543086159f, 0.032591319265180385f, 0.031824726814640963f,
+  0.031058115642434700f,
+  0.030291486199539423f, 0.029524838936943035f, 0.028758174305644590f,
+  0.027991492756653365f,
+  0.027224794740987910f, 0.026458080709677145f, 0.025691351113759395f,
+  0.024924606404281485f,
+  0.024157847032300020f, 0.023391073448879338f, 0.022624286105092803f,
+  0.021857485452021874f,
+  0.021090671940755180f, 0.020323846022389572f, 0.019557008148029204f,
+  0.018790158768784596f,
+  0.018023298335773701f, 0.017256427300120978f, 0.016489546112956454f,
+  0.015722655225417017f,
+  0.014955755088644378f, 0.014188846153786343f, 0.013421928871995907f,
+  0.012655003694430301f,
+  0.011888071072252072f, 0.011121131456628141f, 0.010354185298728884f,
+  0.009587233049729183f,
+  0.008820275160807512f, 0.008053312083144991f, 0.007286344267926684f,
+  0.006519372166339549f,
+  0.005752396229573737f, 0.004985416908821652f, 0.004218434655277024f,
+  0.003451449920135975f,
+  0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f,
+  0.000383495187571497f
+};
+
+/**   
+ * @brief  Initialization function for the floating-point DCT4/IDCT4.  
+ * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.  
+ * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.  
+ * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.  
+ * @param[in]     N			 length of the DCT4.  
+ * @param[in]     Nby2       half of the length of the DCT4.  
+ * @param[in]     normalize  normalizing factor.  
+ * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.  
+ * \par Normalizing factor:   
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.   
+ * Floating-point normalizing factors are mentioned in the table below for different DCT sizes:   
+ * \image html dct4NormalizingF32Table.gif   
+ */
+
+arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize)
+{
+  /*  Initialize the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  float32_t *twiddlePtr[3] =
+    { (float32_t *) Weights_128, (float32_t *) Weights_512,
+    (float32_t *) Weights_2048
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  float32_t *pCosFactor[3] =
+    { (float32_t *) cos_factors_128, (float32_t *) cos_factors_512,
+    (float32_t *) cos_factors_2048
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT */
+  arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
new file mode 100644
index 0000000..260f1b7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
@@ -0,0 +1,1190 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_init_q15.c   
+*   
+* Description:	Initialization function of DCT-4 & IDCT4 Q15   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/*   
+* @brief  Weights Table   
+*/
+
+/**   
+* \par   
+* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
   
+* \par   
+* C command to generate the table   
+* 
   
+* for(i = 0; i< N; i++)   
+* {   
+*   weights[2*i]= cos(i*c);   
+*   weights[(2*i)+1]= -sin(i * c);   
+* } 
   
+* \par   
+* where N is the Number of weights to be calculated and c is pi/(2*N)   
+* \par   
+* Converted the output to q15 format by multiplying with 2^31 and saturated if required.   
+* \par   
+* In the tables below the real and imaginary values are placed alternatively, hence the   
+* array length is 2*N.   
+*/
+
+static const q15_t WeightsQ15_128[256] = {
+  0x7fff, 0x0, 0x7ffd, 0xfe6e, 0x7ff6, 0xfcdc, 0x7fe9, 0xfb4a,
+  0x7fd8, 0xf9b9, 0x7fc2, 0xf827, 0x7fa7, 0xf696, 0x7f87, 0xf505,
+  0x7f62, 0xf375, 0x7f38, 0xf1e5, 0x7f09, 0xf055, 0x7ed5, 0xeec7,
+  0x7e9d, 0xed38, 0x7e5f, 0xebab, 0x7e1d, 0xea1e, 0x7dd6, 0xe893,
+  0x7d8a, 0xe708, 0x7d39, 0xe57e, 0x7ce3, 0xe3f5, 0x7c89, 0xe26d,
+  0x7c29, 0xe0e7, 0x7bc5, 0xdf61, 0x7b5d, 0xdddd, 0x7aef, 0xdc5a,
+  0x7a7d, 0xdad8, 0x7a05, 0xd958, 0x798a, 0xd7da, 0x7909, 0xd65d,
+  0x7884, 0xd4e1, 0x77fa, 0xd368, 0x776c, 0xd1ef, 0x76d9, 0xd079,
+  0x7641, 0xcf05, 0x75a5, 0xcd92, 0x7504, 0xcc22, 0x745f, 0xcab3,
+  0x73b5, 0xc946, 0x7307, 0xc7dc, 0x7255, 0xc674, 0x719e, 0xc50e,
+  0x70e2, 0xc3aa, 0x7023, 0xc248, 0x6f5f, 0xc0e9, 0x6e96, 0xbf8d,
+  0x6dca, 0xbe32, 0x6cf9, 0xbcdb, 0x6c24, 0xbb86, 0x6b4a, 0xba33,
+  0x6a6d, 0xb8e4, 0x698c, 0xb797, 0x68a6, 0xb64c, 0x67bd, 0xb505,
+  0x66cf, 0xb3c1, 0x65dd, 0xb27f, 0x64e8, 0xb141, 0x63ef, 0xb005,
+  0x62f2, 0xaecd, 0x61f1, 0xad97, 0x60ec, 0xac65, 0x5fe3, 0xab36,
+  0x5ed7, 0xaa0b, 0x5dc7, 0xa8e3, 0x5cb4, 0xa7be, 0x5b9d, 0xa69c,
+  0x5a82, 0xa57e, 0x5964, 0xa463, 0x5842, 0xa34c, 0x571d, 0xa239,
+  0x55f5, 0xa129, 0x54ca, 0xa01d, 0x539b, 0x9f14, 0x5269, 0x9e0f,
+  0x5133, 0x9d0e, 0x4ffb, 0x9c11, 0x4ebf, 0x9b18, 0x4d81, 0x9a23,
+  0x4c3f, 0x9931, 0x4afb, 0x9843, 0x49b4, 0x975a, 0x4869, 0x9674,
+  0x471c, 0x9593, 0x45cd, 0x94b6, 0x447a, 0x93dc, 0x4325, 0x9307,
+  0x41ce, 0x9236, 0x4073, 0x916a, 0x3f17, 0x90a1, 0x3db8, 0x8fdd,
+  0x3c56, 0x8f1e, 0x3af2, 0x8e62, 0x398c, 0x8dab, 0x3824, 0x8cf9,
+  0x36ba, 0x8c4b, 0x354d, 0x8ba1, 0x33de, 0x8afc, 0x326e, 0x8a5b,
+  0x30fb, 0x89bf, 0x2f87, 0x8927, 0x2e11, 0x8894, 0x2c98, 0x8806,
+  0x2b1f, 0x877c, 0x29a3, 0x86f7, 0x2826, 0x8676, 0x26a8, 0x85fb,
+  0x2528, 0x8583, 0x23a6, 0x8511, 0x2223, 0x84a3, 0x209f, 0x843b,
+  0x1f19, 0x83d7, 0x1d93, 0x8377, 0x1c0b, 0x831d, 0x1a82, 0x82c7,
+  0x18f8, 0x8276, 0x176d, 0x822a, 0x15e2, 0x81e3, 0x1455, 0x81a1,
+  0x12c8, 0x8163, 0x1139, 0x812b, 0xfab, 0x80f7, 0xe1b, 0x80c8,
+  0xc8b, 0x809e, 0xafb, 0x8079, 0x96a, 0x8059, 0x7d9, 0x803e,
+  0x647, 0x8028, 0x4b6, 0x8017, 0x324, 0x800a, 0x192, 0x8003,
+};
+
+static const q15_t WeightsQ15_512[1024] = {
+  0x7fff, 0x0, 0x7fff, 0xff9c, 0x7fff, 0xff37, 0x7ffe, 0xfed3,
+  0x7ffd, 0xfe6e, 0x7ffc, 0xfe0a, 0x7ffa, 0xfda5, 0x7ff8, 0xfd41,
+  0x7ff6, 0xfcdc, 0x7ff3, 0xfc78, 0x7ff0, 0xfc13, 0x7fed, 0xfbaf,
+  0x7fe9, 0xfb4a, 0x7fe5, 0xfae6, 0x7fe1, 0xfa81, 0x7fdd, 0xfa1d,
+  0x7fd8, 0xf9b9, 0x7fd3, 0xf954, 0x7fce, 0xf8f0, 0x7fc8, 0xf88b,
+  0x7fc2, 0xf827, 0x7fbc, 0xf7c3, 0x7fb5, 0xf75e, 0x7fae, 0xf6fa,
+  0x7fa7, 0xf696, 0x7f9f, 0xf632, 0x7f97, 0xf5cd, 0x7f8f, 0xf569,
+  0x7f87, 0xf505, 0x7f7e, 0xf4a1, 0x7f75, 0xf43d, 0x7f6b, 0xf3d9,
+  0x7f62, 0xf375, 0x7f58, 0xf311, 0x7f4d, 0xf2ad, 0x7f43, 0xf249,
+  0x7f38, 0xf1e5, 0x7f2d, 0xf181, 0x7f21, 0xf11d, 0x7f15, 0xf0b9,
+  0x7f09, 0xf055, 0x7efd, 0xeff2, 0x7ef0, 0xef8e, 0x7ee3, 0xef2a,
+  0x7ed5, 0xeec7, 0x7ec8, 0xee63, 0x7eba, 0xedff, 0x7eab, 0xed9c,
+  0x7e9d, 0xed38, 0x7e8e, 0xecd5, 0x7e7f, 0xec72, 0x7e6f, 0xec0e,
+  0x7e5f, 0xebab, 0x7e4f, 0xeb48, 0x7e3f, 0xeae5, 0x7e2e, 0xea81,
+  0x7e1d, 0xea1e, 0x7e0c, 0xe9bb, 0x7dfa, 0xe958, 0x7de8, 0xe8f6,
+  0x7dd6, 0xe893, 0x7dc3, 0xe830, 0x7db0, 0xe7cd, 0x7d9d, 0xe76a,
+  0x7d8a, 0xe708, 0x7d76, 0xe6a5, 0x7d62, 0xe643, 0x7d4e, 0xe5e0,
+  0x7d39, 0xe57e, 0x7d24, 0xe51c, 0x7d0f, 0xe4b9, 0x7cf9, 0xe457,
+  0x7ce3, 0xe3f5, 0x7ccd, 0xe393, 0x7cb7, 0xe331, 0x7ca0, 0xe2cf,
+  0x7c89, 0xe26d, 0x7c71, 0xe20b, 0x7c5a, 0xe1aa, 0x7c42, 0xe148,
+  0x7c29, 0xe0e7, 0x7c11, 0xe085, 0x7bf8, 0xe024, 0x7bdf, 0xdfc2,
+  0x7bc5, 0xdf61, 0x7bac, 0xdf00, 0x7b92, 0xde9f, 0x7b77, 0xde3e,
+  0x7b5d, 0xdddd, 0x7b42, 0xdd7c, 0x7b26, 0xdd1b, 0x7b0b, 0xdcbb,
+  0x7aef, 0xdc5a, 0x7ad3, 0xdbf9, 0x7ab6, 0xdb99, 0x7a9a, 0xdb39,
+  0x7a7d, 0xdad8, 0x7a5f, 0xda78, 0x7a42, 0xda18, 0x7a24, 0xd9b8,
+  0x7a05, 0xd958, 0x79e7, 0xd8f9, 0x79c8, 0xd899, 0x79a9, 0xd839,
+  0x798a, 0xd7da, 0x796a, 0xd77a, 0x794a, 0xd71b, 0x792a, 0xd6bc,
+  0x7909, 0xd65d, 0x78e8, 0xd5fe, 0x78c7, 0xd59f, 0x78a6, 0xd540,
+  0x7884, 0xd4e1, 0x7862, 0xd483, 0x7840, 0xd424, 0x781d, 0xd3c6,
+  0x77fa, 0xd368, 0x77d7, 0xd309, 0x77b4, 0xd2ab, 0x7790, 0xd24d,
+  0x776c, 0xd1ef, 0x7747, 0xd192, 0x7723, 0xd134, 0x76fe, 0xd0d7,
+  0x76d9, 0xd079, 0x76b3, 0xd01c, 0x768e, 0xcfbf, 0x7668, 0xcf62,
+  0x7641, 0xcf05, 0x761b, 0xcea8, 0x75f4, 0xce4b, 0x75cc, 0xcdef,
+  0x75a5, 0xcd92, 0x757d, 0xcd36, 0x7555, 0xccda, 0x752d, 0xcc7e,
+  0x7504, 0xcc22, 0x74db, 0xcbc6, 0x74b2, 0xcb6a, 0x7489, 0xcb0e,
+  0x745f, 0xcab3, 0x7435, 0xca58, 0x740b, 0xc9fc, 0x73e0, 0xc9a1,
+  0x73b5, 0xc946, 0x738a, 0xc8ec, 0x735f, 0xc891, 0x7333, 0xc836,
+  0x7307, 0xc7dc, 0x72db, 0xc782, 0x72af, 0xc728, 0x7282, 0xc6ce,
+  0x7255, 0xc674, 0x7227, 0xc61a, 0x71fa, 0xc5c0, 0x71cc, 0xc567,
+  0x719e, 0xc50e, 0x716f, 0xc4b4, 0x7141, 0xc45b, 0x7112, 0xc403,
+  0x70e2, 0xc3aa, 0x70b3, 0xc351, 0x7083, 0xc2f9, 0x7053, 0xc2a0,
+  0x7023, 0xc248, 0x6ff2, 0xc1f0, 0x6fc1, 0xc198, 0x6f90, 0xc141,
+  0x6f5f, 0xc0e9, 0x6f2d, 0xc092, 0x6efb, 0xc03b, 0x6ec9, 0xbfe3,
+  0x6e96, 0xbf8d, 0x6e63, 0xbf36, 0x6e30, 0xbedf, 0x6dfd, 0xbe89,
+  0x6dca, 0xbe32, 0x6d96, 0xbddc, 0x6d62, 0xbd86, 0x6d2d, 0xbd30,
+  0x6cf9, 0xbcdb, 0x6cc4, 0xbc85, 0x6c8f, 0xbc30, 0x6c59, 0xbbdb,
+  0x6c24, 0xbb86, 0x6bee, 0xbb31, 0x6bb8, 0xbadc, 0x6b81, 0xba88,
+  0x6b4a, 0xba33, 0x6b13, 0xb9df, 0x6adc, 0xb98b, 0x6aa5, 0xb937,
+  0x6a6d, 0xb8e4, 0x6a35, 0xb890, 0x69fd, 0xb83d, 0x69c4, 0xb7ea,
+  0x698c, 0xb797, 0x6953, 0xb744, 0x6919, 0xb6f1, 0x68e0, 0xb69f,
+  0x68a6, 0xb64c, 0x686c, 0xb5fa, 0x6832, 0xb5a8, 0x67f7, 0xb557,
+  0x67bd, 0xb505, 0x6782, 0xb4b4, 0x6746, 0xb462, 0x670b, 0xb411,
+  0x66cf, 0xb3c1, 0x6693, 0xb370, 0x6657, 0xb31f, 0x661a, 0xb2cf,
+  0x65dd, 0xb27f, 0x65a0, 0xb22f, 0x6563, 0xb1df, 0x6526, 0xb190,
+  0x64e8, 0xb141, 0x64aa, 0xb0f1, 0x646c, 0xb0a2, 0x642d, 0xb054,
+  0x63ef, 0xb005, 0x63b0, 0xafb7, 0x6371, 0xaf69, 0x6331, 0xaf1b,
+  0x62f2, 0xaecd, 0x62b2, 0xae7f, 0x6271, 0xae32, 0x6231, 0xade4,
+  0x61f1, 0xad97, 0x61b0, 0xad4b, 0x616f, 0xacfe, 0x612d, 0xacb2,
+  0x60ec, 0xac65, 0x60aa, 0xac19, 0x6068, 0xabcd, 0x6026, 0xab82,
+  0x5fe3, 0xab36, 0x5fa0, 0xaaeb, 0x5f5e, 0xaaa0, 0x5f1a, 0xaa55,
+  0x5ed7, 0xaa0b, 0x5e93, 0xa9c0, 0x5e50, 0xa976, 0x5e0b, 0xa92c,
+  0x5dc7, 0xa8e3, 0x5d83, 0xa899, 0x5d3e, 0xa850, 0x5cf9, 0xa807,
+  0x5cb4, 0xa7be, 0x5c6e, 0xa775, 0x5c29, 0xa72c, 0x5be3, 0xa6e4,
+  0x5b9d, 0xa69c, 0x5b56, 0xa654, 0x5b10, 0xa60d, 0x5ac9, 0xa5c5,
+  0x5a82, 0xa57e, 0x5a3b, 0xa537, 0x59f3, 0xa4f0, 0x59ac, 0xa4aa,
+  0x5964, 0xa463, 0x591c, 0xa41d, 0x58d4, 0xa3d7, 0x588b, 0xa392,
+  0x5842, 0xa34c, 0x57f9, 0xa307, 0x57b0, 0xa2c2, 0x5767, 0xa27d,
+  0x571d, 0xa239, 0x56d4, 0xa1f5, 0x568a, 0xa1b0, 0x5640, 0xa16d,
+  0x55f5, 0xa129, 0x55ab, 0xa0e6, 0x5560, 0xa0a2, 0x5515, 0xa060,
+  0x54ca, 0xa01d, 0x547e, 0x9fda, 0x5433, 0x9f98, 0x53e7, 0x9f56,
+  0x539b, 0x9f14, 0x534e, 0x9ed3, 0x5302, 0x9e91, 0x52b5, 0x9e50,
+  0x5269, 0x9e0f, 0x521c, 0x9dcf, 0x51ce, 0x9d8f, 0x5181, 0x9d4e,
+  0x5133, 0x9d0e, 0x50e5, 0x9ccf, 0x5097, 0x9c8f, 0x5049, 0x9c50,
+  0x4ffb, 0x9c11, 0x4fac, 0x9bd3, 0x4f5e, 0x9b94, 0x4f0f, 0x9b56,
+  0x4ebf, 0x9b18, 0x4e70, 0x9ada, 0x4e21, 0x9a9d, 0x4dd1, 0x9a60,
+  0x4d81, 0x9a23, 0x4d31, 0x99e6, 0x4ce1, 0x99a9, 0x4c90, 0x996d,
+  0x4c3f, 0x9931, 0x4bef, 0x98f5, 0x4b9e, 0x98ba, 0x4b4c, 0x987e,
+  0x4afb, 0x9843, 0x4aa9, 0x9809, 0x4a58, 0x97ce, 0x4a06, 0x9794,
+  0x49b4, 0x975a, 0x4961, 0x9720, 0x490f, 0x96e7, 0x48bc, 0x96ad,
+  0x4869, 0x9674, 0x4816, 0x963c, 0x47c3, 0x9603, 0x4770, 0x95cb,
+  0x471c, 0x9593, 0x46c9, 0x955b, 0x4675, 0x9524, 0x4621, 0x94ed,
+  0x45cd, 0x94b6, 0x4578, 0x947f, 0x4524, 0x9448, 0x44cf, 0x9412,
+  0x447a, 0x93dc, 0x4425, 0x93a7, 0x43d0, 0x9371, 0x437b, 0x933c,
+  0x4325, 0x9307, 0x42d0, 0x92d3, 0x427a, 0x929e, 0x4224, 0x926a,
+  0x41ce, 0x9236, 0x4177, 0x9203, 0x4121, 0x91d0, 0x40ca, 0x919d,
+  0x4073, 0x916a, 0x401d, 0x9137, 0x3fc5, 0x9105, 0x3f6e, 0x90d3,
+  0x3f17, 0x90a1, 0x3ebf, 0x9070, 0x3e68, 0x903f, 0x3e10, 0x900e,
+  0x3db8, 0x8fdd, 0x3d60, 0x8fad, 0x3d07, 0x8f7d, 0x3caf, 0x8f4d,
+  0x3c56, 0x8f1e, 0x3bfd, 0x8eee, 0x3ba5, 0x8ebf, 0x3b4c, 0x8e91,
+  0x3af2, 0x8e62, 0x3a99, 0x8e34, 0x3a40, 0x8e06, 0x39e6, 0x8dd9,
+  0x398c, 0x8dab, 0x3932, 0x8d7e, 0x38d8, 0x8d51, 0x387e, 0x8d25,
+  0x3824, 0x8cf9, 0x37ca, 0x8ccd, 0x376f, 0x8ca1, 0x3714, 0x8c76,
+  0x36ba, 0x8c4b, 0x365f, 0x8c20, 0x3604, 0x8bf5, 0x35a8, 0x8bcb,
+  0x354d, 0x8ba1, 0x34f2, 0x8b77, 0x3496, 0x8b4e, 0x343a, 0x8b25,
+  0x33de, 0x8afc, 0x3382, 0x8ad3, 0x3326, 0x8aab, 0x32ca, 0x8a83,
+  0x326e, 0x8a5b, 0x3211, 0x8a34, 0x31b5, 0x8a0c, 0x3158, 0x89e5,
+  0x30fb, 0x89bf, 0x309e, 0x8998, 0x3041, 0x8972, 0x2fe4, 0x894d,
+  0x2f87, 0x8927, 0x2f29, 0x8902, 0x2ecc, 0x88dd, 0x2e6e, 0x88b9,
+  0x2e11, 0x8894, 0x2db3, 0x8870, 0x2d55, 0x884c, 0x2cf7, 0x8829,
+  0x2c98, 0x8806, 0x2c3a, 0x87e3, 0x2bdc, 0x87c0, 0x2b7d, 0x879e,
+  0x2b1f, 0x877c, 0x2ac0, 0x875a, 0x2a61, 0x8739, 0x2a02, 0x8718,
+  0x29a3, 0x86f7, 0x2944, 0x86d6, 0x28e5, 0x86b6, 0x2886, 0x8696,
+  0x2826, 0x8676, 0x27c7, 0x8657, 0x2767, 0x8638, 0x2707, 0x8619,
+  0x26a8, 0x85fb, 0x2648, 0x85dc, 0x25e8, 0x85be, 0x2588, 0x85a1,
+  0x2528, 0x8583, 0x24c7, 0x8566, 0x2467, 0x854a, 0x2407, 0x852d,
+  0x23a6, 0x8511, 0x2345, 0x84f5, 0x22e5, 0x84da, 0x2284, 0x84be,
+  0x2223, 0x84a3, 0x21c2, 0x8489, 0x2161, 0x846e, 0x2100, 0x8454,
+  0x209f, 0x843b, 0x203e, 0x8421, 0x1fdc, 0x8408, 0x1f7b, 0x83ef,
+  0x1f19, 0x83d7, 0x1eb8, 0x83be, 0x1e56, 0x83a6, 0x1df5, 0x838f,
+  0x1d93, 0x8377, 0x1d31, 0x8360, 0x1ccf, 0x8349, 0x1c6d, 0x8333,
+  0x1c0b, 0x831d, 0x1ba9, 0x8307, 0x1b47, 0x82f1, 0x1ae4, 0x82dc,
+  0x1a82, 0x82c7, 0x1a20, 0x82b2, 0x19bd, 0x829e, 0x195b, 0x828a,
+  0x18f8, 0x8276, 0x1896, 0x8263, 0x1833, 0x8250, 0x17d0, 0x823d,
+  0x176d, 0x822a, 0x170a, 0x8218, 0x16a8, 0x8206, 0x1645, 0x81f4,
+  0x15e2, 0x81e3, 0x157f, 0x81d2, 0x151b, 0x81c1, 0x14b8, 0x81b1,
+  0x1455, 0x81a1, 0x13f2, 0x8191, 0x138e, 0x8181, 0x132b, 0x8172,
+  0x12c8, 0x8163, 0x1264, 0x8155, 0x1201, 0x8146, 0x119d, 0x8138,
+  0x1139, 0x812b, 0x10d6, 0x811d, 0x1072, 0x8110, 0x100e, 0x8103,
+  0xfab, 0x80f7, 0xf47, 0x80eb, 0xee3, 0x80df, 0xe7f, 0x80d3,
+  0xe1b, 0x80c8, 0xdb7, 0x80bd, 0xd53, 0x80b3, 0xcef, 0x80a8,
+  0xc8b, 0x809e, 0xc27, 0x8095, 0xbc3, 0x808b, 0xb5f, 0x8082,
+  0xafb, 0x8079, 0xa97, 0x8071, 0xa33, 0x8069, 0x9ce, 0x8061,
+  0x96a, 0x8059, 0x906, 0x8052, 0x8a2, 0x804b, 0x83d, 0x8044,
+  0x7d9, 0x803e, 0x775, 0x8038, 0x710, 0x8032, 0x6ac, 0x802d,
+  0x647, 0x8028, 0x5e3, 0x8023, 0x57f, 0x801f, 0x51a, 0x801b,
+  0x4b6, 0x8017, 0x451, 0x8013, 0x3ed, 0x8010, 0x388, 0x800d,
+  0x324, 0x800a, 0x2bf, 0x8008, 0x25b, 0x8006, 0x1f6, 0x8004,
+  0x192, 0x8003, 0x12d, 0x8002, 0xc9, 0x8001, 0x64, 0x8001,
+};
+
+static const q15_t WeightsQ15_2048[4096] = {
+  0x7fff, 0x0, 0x7fff, 0xffe7, 0x7fff, 0xffce, 0x7fff, 0xffb5,
+  0x7fff, 0xff9c, 0x7fff, 0xff83, 0x7fff, 0xff6a, 0x7fff, 0xff51,
+  0x7fff, 0xff37, 0x7fff, 0xff1e, 0x7fff, 0xff05, 0x7ffe, 0xfeec,
+  0x7ffe, 0xfed3, 0x7ffe, 0xfeba, 0x7ffe, 0xfea1, 0x7ffd, 0xfe88,
+  0x7ffd, 0xfe6e, 0x7ffd, 0xfe55, 0x7ffc, 0xfe3c, 0x7ffc, 0xfe23,
+  0x7ffc, 0xfe0a, 0x7ffb, 0xfdf1, 0x7ffb, 0xfdd8, 0x7ffa, 0xfdbe,
+  0x7ffa, 0xfda5, 0x7ff9, 0xfd8c, 0x7ff9, 0xfd73, 0x7ff8, 0xfd5a,
+  0x7ff8, 0xfd41, 0x7ff7, 0xfd28, 0x7ff7, 0xfd0f, 0x7ff6, 0xfcf5,
+  0x7ff6, 0xfcdc, 0x7ff5, 0xfcc3, 0x7ff4, 0xfcaa, 0x7ff4, 0xfc91,
+  0x7ff3, 0xfc78, 0x7ff2, 0xfc5f, 0x7ff2, 0xfc46, 0x7ff1, 0xfc2c,
+  0x7ff0, 0xfc13, 0x7fef, 0xfbfa, 0x7fee, 0xfbe1, 0x7fee, 0xfbc8,
+  0x7fed, 0xfbaf, 0x7fec, 0xfb96, 0x7feb, 0xfb7d, 0x7fea, 0xfb64,
+  0x7fe9, 0xfb4a, 0x7fe8, 0xfb31, 0x7fe7, 0xfb18, 0x7fe6, 0xfaff,
+  0x7fe5, 0xfae6, 0x7fe4, 0xfacd, 0x7fe3, 0xfab4, 0x7fe2, 0xfa9b,
+  0x7fe1, 0xfa81, 0x7fe0, 0xfa68, 0x7fdf, 0xfa4f, 0x7fde, 0xfa36,
+  0x7fdd, 0xfa1d, 0x7fdc, 0xfa04, 0x7fda, 0xf9eb, 0x7fd9, 0xf9d2,
+  0x7fd8, 0xf9b9, 0x7fd7, 0xf9a0, 0x7fd6, 0xf986, 0x7fd4, 0xf96d,
+  0x7fd3, 0xf954, 0x7fd2, 0xf93b, 0x7fd0, 0xf922, 0x7fcf, 0xf909,
+  0x7fce, 0xf8f0, 0x7fcc, 0xf8d7, 0x7fcb, 0xf8be, 0x7fc9, 0xf8a5,
+  0x7fc8, 0xf88b, 0x7fc6, 0xf872, 0x7fc5, 0xf859, 0x7fc3, 0xf840,
+  0x7fc2, 0xf827, 0x7fc0, 0xf80e, 0x7fbf, 0xf7f5, 0x7fbd, 0xf7dc,
+  0x7fbc, 0xf7c3, 0x7fba, 0xf7aa, 0x7fb8, 0xf791, 0x7fb7, 0xf778,
+  0x7fb5, 0xf75e, 0x7fb3, 0xf745, 0x7fb1, 0xf72c, 0x7fb0, 0xf713,
+  0x7fae, 0xf6fa, 0x7fac, 0xf6e1, 0x7faa, 0xf6c8, 0x7fa9, 0xf6af,
+  0x7fa7, 0xf696, 0x7fa5, 0xf67d, 0x7fa3, 0xf664, 0x7fa1, 0xf64b,
+  0x7f9f, 0xf632, 0x7f9d, 0xf619, 0x7f9b, 0xf600, 0x7f99, 0xf5e7,
+  0x7f97, 0xf5cd, 0x7f95, 0xf5b4, 0x7f93, 0xf59b, 0x7f91, 0xf582,
+  0x7f8f, 0xf569, 0x7f8d, 0xf550, 0x7f8b, 0xf537, 0x7f89, 0xf51e,
+  0x7f87, 0xf505, 0x7f85, 0xf4ec, 0x7f82, 0xf4d3, 0x7f80, 0xf4ba,
+  0x7f7e, 0xf4a1, 0x7f7c, 0xf488, 0x7f79, 0xf46f, 0x7f77, 0xf456,
+  0x7f75, 0xf43d, 0x7f72, 0xf424, 0x7f70, 0xf40b, 0x7f6e, 0xf3f2,
+  0x7f6b, 0xf3d9, 0x7f69, 0xf3c0, 0x7f67, 0xf3a7, 0x7f64, 0xf38e,
+  0x7f62, 0xf375, 0x7f5f, 0xf35c, 0x7f5d, 0xf343, 0x7f5a, 0xf32a,
+  0x7f58, 0xf311, 0x7f55, 0xf2f8, 0x7f53, 0xf2df, 0x7f50, 0xf2c6,
+  0x7f4d, 0xf2ad, 0x7f4b, 0xf294, 0x7f48, 0xf27b, 0x7f45, 0xf262,
+  0x7f43, 0xf249, 0x7f40, 0xf230, 0x7f3d, 0xf217, 0x7f3b, 0xf1fe,
+  0x7f38, 0xf1e5, 0x7f35, 0xf1cc, 0x7f32, 0xf1b3, 0x7f2f, 0xf19a,
+  0x7f2d, 0xf181, 0x7f2a, 0xf168, 0x7f27, 0xf14f, 0x7f24, 0xf136,
+  0x7f21, 0xf11d, 0x7f1e, 0xf104, 0x7f1b, 0xf0eb, 0x7f18, 0xf0d2,
+  0x7f15, 0xf0b9, 0x7f12, 0xf0a0, 0x7f0f, 0xf087, 0x7f0c, 0xf06e,
+  0x7f09, 0xf055, 0x7f06, 0xf03c, 0x7f03, 0xf023, 0x7f00, 0xf00b,
+  0x7efd, 0xeff2, 0x7ef9, 0xefd9, 0x7ef6, 0xefc0, 0x7ef3, 0xefa7,
+  0x7ef0, 0xef8e, 0x7eed, 0xef75, 0x7ee9, 0xef5c, 0x7ee6, 0xef43,
+  0x7ee3, 0xef2a, 0x7edf, 0xef11, 0x7edc, 0xeef8, 0x7ed9, 0xeedf,
+  0x7ed5, 0xeec7, 0x7ed2, 0xeeae, 0x7ecf, 0xee95, 0x7ecb, 0xee7c,
+  0x7ec8, 0xee63, 0x7ec4, 0xee4a, 0x7ec1, 0xee31, 0x7ebd, 0xee18,
+  0x7eba, 0xedff, 0x7eb6, 0xede7, 0x7eb3, 0xedce, 0x7eaf, 0xedb5,
+  0x7eab, 0xed9c, 0x7ea8, 0xed83, 0x7ea4, 0xed6a, 0x7ea1, 0xed51,
+  0x7e9d, 0xed38, 0x7e99, 0xed20, 0x7e95, 0xed07, 0x7e92, 0xecee,
+  0x7e8e, 0xecd5, 0x7e8a, 0xecbc, 0x7e86, 0xeca3, 0x7e83, 0xec8a,
+  0x7e7f, 0xec72, 0x7e7b, 0xec59, 0x7e77, 0xec40, 0x7e73, 0xec27,
+  0x7e6f, 0xec0e, 0x7e6b, 0xebf5, 0x7e67, 0xebdd, 0x7e63, 0xebc4,
+  0x7e5f, 0xebab, 0x7e5b, 0xeb92, 0x7e57, 0xeb79, 0x7e53, 0xeb61,
+  0x7e4f, 0xeb48, 0x7e4b, 0xeb2f, 0x7e47, 0xeb16, 0x7e43, 0xeafd,
+  0x7e3f, 0xeae5, 0x7e3b, 0xeacc, 0x7e37, 0xeab3, 0x7e32, 0xea9a,
+  0x7e2e, 0xea81, 0x7e2a, 0xea69, 0x7e26, 0xea50, 0x7e21, 0xea37,
+  0x7e1d, 0xea1e, 0x7e19, 0xea06, 0x7e14, 0xe9ed, 0x7e10, 0xe9d4,
+  0x7e0c, 0xe9bb, 0x7e07, 0xe9a3, 0x7e03, 0xe98a, 0x7dff, 0xe971,
+  0x7dfa, 0xe958, 0x7df6, 0xe940, 0x7df1, 0xe927, 0x7ded, 0xe90e,
+  0x7de8, 0xe8f6, 0x7de4, 0xe8dd, 0x7ddf, 0xe8c4, 0x7dda, 0xe8ab,
+  0x7dd6, 0xe893, 0x7dd1, 0xe87a, 0x7dcd, 0xe861, 0x7dc8, 0xe849,
+  0x7dc3, 0xe830, 0x7dbf, 0xe817, 0x7dba, 0xe7fe, 0x7db5, 0xe7e6,
+  0x7db0, 0xe7cd, 0x7dac, 0xe7b4, 0x7da7, 0xe79c, 0x7da2, 0xe783,
+  0x7d9d, 0xe76a, 0x7d98, 0xe752, 0x7d94, 0xe739, 0x7d8f, 0xe720,
+  0x7d8a, 0xe708, 0x7d85, 0xe6ef, 0x7d80, 0xe6d6, 0x7d7b, 0xe6be,
+  0x7d76, 0xe6a5, 0x7d71, 0xe68d, 0x7d6c, 0xe674, 0x7d67, 0xe65b,
+  0x7d62, 0xe643, 0x7d5d, 0xe62a, 0x7d58, 0xe611, 0x7d53, 0xe5f9,
+  0x7d4e, 0xe5e0, 0x7d49, 0xe5c8, 0x7d43, 0xe5af, 0x7d3e, 0xe596,
+  0x7d39, 0xe57e, 0x7d34, 0xe565, 0x7d2f, 0xe54d, 0x7d29, 0xe534,
+  0x7d24, 0xe51c, 0x7d1f, 0xe503, 0x7d19, 0xe4ea, 0x7d14, 0xe4d2,
+  0x7d0f, 0xe4b9, 0x7d09, 0xe4a1, 0x7d04, 0xe488, 0x7cff, 0xe470,
+  0x7cf9, 0xe457, 0x7cf4, 0xe43f, 0x7cee, 0xe426, 0x7ce9, 0xe40e,
+  0x7ce3, 0xe3f5, 0x7cde, 0xe3dc, 0x7cd8, 0xe3c4, 0x7cd3, 0xe3ab,
+  0x7ccd, 0xe393, 0x7cc8, 0xe37a, 0x7cc2, 0xe362, 0x7cbc, 0xe349,
+  0x7cb7, 0xe331, 0x7cb1, 0xe318, 0x7cab, 0xe300, 0x7ca6, 0xe2e8,
+  0x7ca0, 0xe2cf, 0x7c9a, 0xe2b7, 0x7c94, 0xe29e, 0x7c8f, 0xe286,
+  0x7c89, 0xe26d, 0x7c83, 0xe255, 0x7c7d, 0xe23c, 0x7c77, 0xe224,
+  0x7c71, 0xe20b, 0x7c6c, 0xe1f3, 0x7c66, 0xe1db, 0x7c60, 0xe1c2,
+  0x7c5a, 0xe1aa, 0x7c54, 0xe191, 0x7c4e, 0xe179, 0x7c48, 0xe160,
+  0x7c42, 0xe148, 0x7c3c, 0xe130, 0x7c36, 0xe117, 0x7c30, 0xe0ff,
+  0x7c29, 0xe0e7, 0x7c23, 0xe0ce, 0x7c1d, 0xe0b6, 0x7c17, 0xe09d,
+  0x7c11, 0xe085, 0x7c0b, 0xe06d, 0x7c05, 0xe054, 0x7bfe, 0xe03c,
+  0x7bf8, 0xe024, 0x7bf2, 0xe00b, 0x7beb, 0xdff3, 0x7be5, 0xdfdb,
+  0x7bdf, 0xdfc2, 0x7bd9, 0xdfaa, 0x7bd2, 0xdf92, 0x7bcc, 0xdf79,
+  0x7bc5, 0xdf61, 0x7bbf, 0xdf49, 0x7bb9, 0xdf30, 0x7bb2, 0xdf18,
+  0x7bac, 0xdf00, 0x7ba5, 0xdee8, 0x7b9f, 0xdecf, 0x7b98, 0xdeb7,
+  0x7b92, 0xde9f, 0x7b8b, 0xde87, 0x7b84, 0xde6e, 0x7b7e, 0xde56,
+  0x7b77, 0xde3e, 0x7b71, 0xde26, 0x7b6a, 0xde0d, 0x7b63, 0xddf5,
+  0x7b5d, 0xdddd, 0x7b56, 0xddc5, 0x7b4f, 0xddac, 0x7b48, 0xdd94,
+  0x7b42, 0xdd7c, 0x7b3b, 0xdd64, 0x7b34, 0xdd4c, 0x7b2d, 0xdd33,
+  0x7b26, 0xdd1b, 0x7b1f, 0xdd03, 0x7b19, 0xdceb, 0x7b12, 0xdcd3,
+  0x7b0b, 0xdcbb, 0x7b04, 0xdca2, 0x7afd, 0xdc8a, 0x7af6, 0xdc72,
+  0x7aef, 0xdc5a, 0x7ae8, 0xdc42, 0x7ae1, 0xdc2a, 0x7ada, 0xdc12,
+  0x7ad3, 0xdbf9, 0x7acc, 0xdbe1, 0x7ac5, 0xdbc9, 0x7abd, 0xdbb1,
+  0x7ab6, 0xdb99, 0x7aaf, 0xdb81, 0x7aa8, 0xdb69, 0x7aa1, 0xdb51,
+  0x7a9a, 0xdb39, 0x7a92, 0xdb21, 0x7a8b, 0xdb09, 0x7a84, 0xdaf1,
+  0x7a7d, 0xdad8, 0x7a75, 0xdac0, 0x7a6e, 0xdaa8, 0x7a67, 0xda90,
+  0x7a5f, 0xda78, 0x7a58, 0xda60, 0x7a50, 0xda48, 0x7a49, 0xda30,
+  0x7a42, 0xda18, 0x7a3a, 0xda00, 0x7a33, 0xd9e8, 0x7a2b, 0xd9d0,
+  0x7a24, 0xd9b8, 0x7a1c, 0xd9a0, 0x7a15, 0xd988, 0x7a0d, 0xd970,
+  0x7a05, 0xd958, 0x79fe, 0xd940, 0x79f6, 0xd928, 0x79ef, 0xd911,
+  0x79e7, 0xd8f9, 0x79df, 0xd8e1, 0x79d8, 0xd8c9, 0x79d0, 0xd8b1,
+  0x79c8, 0xd899, 0x79c0, 0xd881, 0x79b9, 0xd869, 0x79b1, 0xd851,
+  0x79a9, 0xd839, 0x79a1, 0xd821, 0x7999, 0xd80a, 0x7992, 0xd7f2,
+  0x798a, 0xd7da, 0x7982, 0xd7c2, 0x797a, 0xd7aa, 0x7972, 0xd792,
+  0x796a, 0xd77a, 0x7962, 0xd763, 0x795a, 0xd74b, 0x7952, 0xd733,
+  0x794a, 0xd71b, 0x7942, 0xd703, 0x793a, 0xd6eb, 0x7932, 0xd6d4,
+  0x792a, 0xd6bc, 0x7922, 0xd6a4, 0x7919, 0xd68c, 0x7911, 0xd675,
+  0x7909, 0xd65d, 0x7901, 0xd645, 0x78f9, 0xd62d, 0x78f1, 0xd615,
+  0x78e8, 0xd5fe, 0x78e0, 0xd5e6, 0x78d8, 0xd5ce, 0x78cf, 0xd5b7,
+  0x78c7, 0xd59f, 0x78bf, 0xd587, 0x78b6, 0xd56f, 0x78ae, 0xd558,
+  0x78a6, 0xd540, 0x789d, 0xd528, 0x7895, 0xd511, 0x788c, 0xd4f9,
+  0x7884, 0xd4e1, 0x787c, 0xd4ca, 0x7873, 0xd4b2, 0x786b, 0xd49a,
+  0x7862, 0xd483, 0x7859, 0xd46b, 0x7851, 0xd453, 0x7848, 0xd43c,
+  0x7840, 0xd424, 0x7837, 0xd40d, 0x782e, 0xd3f5, 0x7826, 0xd3dd,
+  0x781d, 0xd3c6, 0x7814, 0xd3ae, 0x780c, 0xd397, 0x7803, 0xd37f,
+  0x77fa, 0xd368, 0x77f1, 0xd350, 0x77e9, 0xd338, 0x77e0, 0xd321,
+  0x77d7, 0xd309, 0x77ce, 0xd2f2, 0x77c5, 0xd2da, 0x77bc, 0xd2c3,
+  0x77b4, 0xd2ab, 0x77ab, 0xd294, 0x77a2, 0xd27c, 0x7799, 0xd265,
+  0x7790, 0xd24d, 0x7787, 0xd236, 0x777e, 0xd21e, 0x7775, 0xd207,
+  0x776c, 0xd1ef, 0x7763, 0xd1d8, 0x775a, 0xd1c1, 0x7751, 0xd1a9,
+  0x7747, 0xd192, 0x773e, 0xd17a, 0x7735, 0xd163, 0x772c, 0xd14b,
+  0x7723, 0xd134, 0x771a, 0xd11d, 0x7710, 0xd105, 0x7707, 0xd0ee,
+  0x76fe, 0xd0d7, 0x76f5, 0xd0bf, 0x76eb, 0xd0a8, 0x76e2, 0xd091,
+  0x76d9, 0xd079, 0x76cf, 0xd062, 0x76c6, 0xd04b, 0x76bd, 0xd033,
+  0x76b3, 0xd01c, 0x76aa, 0xd005, 0x76a0, 0xcfed, 0x7697, 0xcfd6,
+  0x768e, 0xcfbf, 0x7684, 0xcfa7, 0x767b, 0xcf90, 0x7671, 0xcf79,
+  0x7668, 0xcf62, 0x765e, 0xcf4a, 0x7654, 0xcf33, 0x764b, 0xcf1c,
+  0x7641, 0xcf05, 0x7638, 0xceee, 0x762e, 0xced6, 0x7624, 0xcebf,
+  0x761b, 0xcea8, 0x7611, 0xce91, 0x7607, 0xce7a, 0x75fd, 0xce62,
+  0x75f4, 0xce4b, 0x75ea, 0xce34, 0x75e0, 0xce1d, 0x75d6, 0xce06,
+  0x75cc, 0xcdef, 0x75c3, 0xcdd8, 0x75b9, 0xcdc0, 0x75af, 0xcda9,
+  0x75a5, 0xcd92, 0x759b, 0xcd7b, 0x7591, 0xcd64, 0x7587, 0xcd4d,
+  0x757d, 0xcd36, 0x7573, 0xcd1f, 0x7569, 0xcd08, 0x755f, 0xccf1,
+  0x7555, 0xccda, 0x754b, 0xccc3, 0x7541, 0xccac, 0x7537, 0xcc95,
+  0x752d, 0xcc7e, 0x7523, 0xcc67, 0x7519, 0xcc50, 0x750f, 0xcc39,
+  0x7504, 0xcc22, 0x74fa, 0xcc0b, 0x74f0, 0xcbf4, 0x74e6, 0xcbdd,
+  0x74db, 0xcbc6, 0x74d1, 0xcbaf, 0x74c7, 0xcb98, 0x74bd, 0xcb81,
+  0x74b2, 0xcb6a, 0x74a8, 0xcb53, 0x749e, 0xcb3c, 0x7493, 0xcb25,
+  0x7489, 0xcb0e, 0x747e, 0xcaf8, 0x7474, 0xcae1, 0x746a, 0xcaca,
+  0x745f, 0xcab3, 0x7455, 0xca9c, 0x744a, 0xca85, 0x7440, 0xca6e,
+  0x7435, 0xca58, 0x742b, 0xca41, 0x7420, 0xca2a, 0x7415, 0xca13,
+  0x740b, 0xc9fc, 0x7400, 0xc9e6, 0x73f6, 0xc9cf, 0x73eb, 0xc9b8,
+  0x73e0, 0xc9a1, 0x73d6, 0xc98b, 0x73cb, 0xc974, 0x73c0, 0xc95d,
+  0x73b5, 0xc946, 0x73ab, 0xc930, 0x73a0, 0xc919, 0x7395, 0xc902,
+  0x738a, 0xc8ec, 0x737f, 0xc8d5, 0x7375, 0xc8be, 0x736a, 0xc8a8,
+  0x735f, 0xc891, 0x7354, 0xc87a, 0x7349, 0xc864, 0x733e, 0xc84d,
+  0x7333, 0xc836, 0x7328, 0xc820, 0x731d, 0xc809, 0x7312, 0xc7f3,
+  0x7307, 0xc7dc, 0x72fc, 0xc7c5, 0x72f1, 0xc7af, 0x72e6, 0xc798,
+  0x72db, 0xc782, 0x72d0, 0xc76b, 0x72c5, 0xc755, 0x72ba, 0xc73e,
+  0x72af, 0xc728, 0x72a3, 0xc711, 0x7298, 0xc6fa, 0x728d, 0xc6e4,
+  0x7282, 0xc6ce, 0x7276, 0xc6b7, 0x726b, 0xc6a1, 0x7260, 0xc68a,
+  0x7255, 0xc674, 0x7249, 0xc65d, 0x723e, 0xc647, 0x7233, 0xc630,
+  0x7227, 0xc61a, 0x721c, 0xc603, 0x7211, 0xc5ed, 0x7205, 0xc5d7,
+  0x71fa, 0xc5c0, 0x71ee, 0xc5aa, 0x71e3, 0xc594, 0x71d7, 0xc57d,
+  0x71cc, 0xc567, 0x71c0, 0xc551, 0x71b5, 0xc53a, 0x71a9, 0xc524,
+  0x719e, 0xc50e, 0x7192, 0xc4f7, 0x7186, 0xc4e1, 0x717b, 0xc4cb,
+  0x716f, 0xc4b4, 0x7164, 0xc49e, 0x7158, 0xc488, 0x714c, 0xc472,
+  0x7141, 0xc45b, 0x7135, 0xc445, 0x7129, 0xc42f, 0x711d, 0xc419,
+  0x7112, 0xc403, 0x7106, 0xc3ec, 0x70fa, 0xc3d6, 0x70ee, 0xc3c0,
+  0x70e2, 0xc3aa, 0x70d6, 0xc394, 0x70cb, 0xc37d, 0x70bf, 0xc367,
+  0x70b3, 0xc351, 0x70a7, 0xc33b, 0x709b, 0xc325, 0x708f, 0xc30f,
+  0x7083, 0xc2f9, 0x7077, 0xc2e3, 0x706b, 0xc2cd, 0x705f, 0xc2b7,
+  0x7053, 0xc2a0, 0x7047, 0xc28a, 0x703b, 0xc274, 0x702f, 0xc25e,
+  0x7023, 0xc248, 0x7016, 0xc232, 0x700a, 0xc21c, 0x6ffe, 0xc206,
+  0x6ff2, 0xc1f0, 0x6fe6, 0xc1da, 0x6fda, 0xc1c4, 0x6fcd, 0xc1ae,
+  0x6fc1, 0xc198, 0x6fb5, 0xc183, 0x6fa9, 0xc16d, 0x6f9c, 0xc157,
+  0x6f90, 0xc141, 0x6f84, 0xc12b, 0x6f77, 0xc115, 0x6f6b, 0xc0ff,
+  0x6f5f, 0xc0e9, 0x6f52, 0xc0d3, 0x6f46, 0xc0bd, 0x6f39, 0xc0a8,
+  0x6f2d, 0xc092, 0x6f20, 0xc07c, 0x6f14, 0xc066, 0x6f07, 0xc050,
+  0x6efb, 0xc03b, 0x6eee, 0xc025, 0x6ee2, 0xc00f, 0x6ed5, 0xbff9,
+  0x6ec9, 0xbfe3, 0x6ebc, 0xbfce, 0x6eaf, 0xbfb8, 0x6ea3, 0xbfa2,
+  0x6e96, 0xbf8d, 0x6e89, 0xbf77, 0x6e7d, 0xbf61, 0x6e70, 0xbf4b,
+  0x6e63, 0xbf36, 0x6e57, 0xbf20, 0x6e4a, 0xbf0a, 0x6e3d, 0xbef5,
+  0x6e30, 0xbedf, 0x6e24, 0xbeca, 0x6e17, 0xbeb4, 0x6e0a, 0xbe9e,
+  0x6dfd, 0xbe89, 0x6df0, 0xbe73, 0x6de3, 0xbe5e, 0x6dd6, 0xbe48,
+  0x6dca, 0xbe32, 0x6dbd, 0xbe1d, 0x6db0, 0xbe07, 0x6da3, 0xbdf2,
+  0x6d96, 0xbddc, 0x6d89, 0xbdc7, 0x6d7c, 0xbdb1, 0x6d6f, 0xbd9c,
+  0x6d62, 0xbd86, 0x6d55, 0xbd71, 0x6d48, 0xbd5b, 0x6d3a, 0xbd46,
+  0x6d2d, 0xbd30, 0x6d20, 0xbd1b, 0x6d13, 0xbd06, 0x6d06, 0xbcf0,
+  0x6cf9, 0xbcdb, 0x6cec, 0xbcc5, 0x6cde, 0xbcb0, 0x6cd1, 0xbc9b,
+  0x6cc4, 0xbc85, 0x6cb7, 0xbc70, 0x6ca9, 0xbc5b, 0x6c9c, 0xbc45,
+  0x6c8f, 0xbc30, 0x6c81, 0xbc1b, 0x6c74, 0xbc05, 0x6c67, 0xbbf0,
+  0x6c59, 0xbbdb, 0x6c4c, 0xbbc5, 0x6c3f, 0xbbb0, 0x6c31, 0xbb9b,
+  0x6c24, 0xbb86, 0x6c16, 0xbb70, 0x6c09, 0xbb5b, 0x6bfb, 0xbb46,
+  0x6bee, 0xbb31, 0x6be0, 0xbb1c, 0x6bd3, 0xbb06, 0x6bc5, 0xbaf1,
+  0x6bb8, 0xbadc, 0x6baa, 0xbac7, 0x6b9c, 0xbab2, 0x6b8f, 0xba9d,
+  0x6b81, 0xba88, 0x6b73, 0xba73, 0x6b66, 0xba5d, 0x6b58, 0xba48,
+  0x6b4a, 0xba33, 0x6b3d, 0xba1e, 0x6b2f, 0xba09, 0x6b21, 0xb9f4,
+  0x6b13, 0xb9df, 0x6b06, 0xb9ca, 0x6af8, 0xb9b5, 0x6aea, 0xb9a0,
+  0x6adc, 0xb98b, 0x6ace, 0xb976, 0x6ac1, 0xb961, 0x6ab3, 0xb94c,
+  0x6aa5, 0xb937, 0x6a97, 0xb922, 0x6a89, 0xb90d, 0x6a7b, 0xb8f8,
+  0x6a6d, 0xb8e4, 0x6a5f, 0xb8cf, 0x6a51, 0xb8ba, 0x6a43, 0xb8a5,
+  0x6a35, 0xb890, 0x6a27, 0xb87b, 0x6a19, 0xb866, 0x6a0b, 0xb852,
+  0x69fd, 0xb83d, 0x69ef, 0xb828, 0x69e1, 0xb813, 0x69d3, 0xb7fe,
+  0x69c4, 0xb7ea, 0x69b6, 0xb7d5, 0x69a8, 0xb7c0, 0x699a, 0xb7ab,
+  0x698c, 0xb797, 0x697d, 0xb782, 0x696f, 0xb76d, 0x6961, 0xb758,
+  0x6953, 0xb744, 0x6944, 0xb72f, 0x6936, 0xb71a, 0x6928, 0xb706,
+  0x6919, 0xb6f1, 0x690b, 0xb6dd, 0x68fd, 0xb6c8, 0x68ee, 0xb6b3,
+  0x68e0, 0xb69f, 0x68d1, 0xb68a, 0x68c3, 0xb676, 0x68b5, 0xb661,
+  0x68a6, 0xb64c, 0x6898, 0xb638, 0x6889, 0xb623, 0x687b, 0xb60f,
+  0x686c, 0xb5fa, 0x685e, 0xb5e6, 0x684f, 0xb5d1, 0x6840, 0xb5bd,
+  0x6832, 0xb5a8, 0x6823, 0xb594, 0x6815, 0xb57f, 0x6806, 0xb56b,
+  0x67f7, 0xb557, 0x67e9, 0xb542, 0x67da, 0xb52e, 0x67cb, 0xb519,
+  0x67bd, 0xb505, 0x67ae, 0xb4f1, 0x679f, 0xb4dc, 0x6790, 0xb4c8,
+  0x6782, 0xb4b4, 0x6773, 0xb49f, 0x6764, 0xb48b, 0x6755, 0xb477,
+  0x6746, 0xb462, 0x6737, 0xb44e, 0x6729, 0xb43a, 0x671a, 0xb426,
+  0x670b, 0xb411, 0x66fc, 0xb3fd, 0x66ed, 0xb3e9, 0x66de, 0xb3d5,
+  0x66cf, 0xb3c1, 0x66c0, 0xb3ac, 0x66b1, 0xb398, 0x66a2, 0xb384,
+  0x6693, 0xb370, 0x6684, 0xb35c, 0x6675, 0xb348, 0x6666, 0xb334,
+  0x6657, 0xb31f, 0x6648, 0xb30b, 0x6639, 0xb2f7, 0x6629, 0xb2e3,
+  0x661a, 0xb2cf, 0x660b, 0xb2bb, 0x65fc, 0xb2a7, 0x65ed, 0xb293,
+  0x65dd, 0xb27f, 0x65ce, 0xb26b, 0x65bf, 0xb257, 0x65b0, 0xb243,
+  0x65a0, 0xb22f, 0x6591, 0xb21b, 0x6582, 0xb207, 0x6573, 0xb1f3,
+  0x6563, 0xb1df, 0x6554, 0xb1cc, 0x6545, 0xb1b8, 0x6535, 0xb1a4,
+  0x6526, 0xb190, 0x6516, 0xb17c, 0x6507, 0xb168, 0x64f7, 0xb154,
+  0x64e8, 0xb141, 0x64d9, 0xb12d, 0x64c9, 0xb119, 0x64ba, 0xb105,
+  0x64aa, 0xb0f1, 0x649b, 0xb0de, 0x648b, 0xb0ca, 0x647b, 0xb0b6,
+  0x646c, 0xb0a2, 0x645c, 0xb08f, 0x644d, 0xb07b, 0x643d, 0xb067,
+  0x642d, 0xb054, 0x641e, 0xb040, 0x640e, 0xb02c, 0x63fe, 0xb019,
+  0x63ef, 0xb005, 0x63df, 0xaff1, 0x63cf, 0xafde, 0x63c0, 0xafca,
+  0x63b0, 0xafb7, 0x63a0, 0xafa3, 0x6390, 0xaf90, 0x6380, 0xaf7c,
+  0x6371, 0xaf69, 0x6361, 0xaf55, 0x6351, 0xaf41, 0x6341, 0xaf2e,
+  0x6331, 0xaf1b, 0x6321, 0xaf07, 0x6311, 0xaef4, 0x6301, 0xaee0,
+  0x62f2, 0xaecd, 0x62e2, 0xaeb9, 0x62d2, 0xaea6, 0x62c2, 0xae92,
+  0x62b2, 0xae7f, 0x62a2, 0xae6c, 0x6292, 0xae58, 0x6282, 0xae45,
+  0x6271, 0xae32, 0x6261, 0xae1e, 0x6251, 0xae0b, 0x6241, 0xadf8,
+  0x6231, 0xade4, 0x6221, 0xadd1, 0x6211, 0xadbe, 0x6201, 0xadab,
+  0x61f1, 0xad97, 0x61e0, 0xad84, 0x61d0, 0xad71, 0x61c0, 0xad5e,
+  0x61b0, 0xad4b, 0x619f, 0xad37, 0x618f, 0xad24, 0x617f, 0xad11,
+  0x616f, 0xacfe, 0x615e, 0xaceb, 0x614e, 0xacd8, 0x613e, 0xacc5,
+  0x612d, 0xacb2, 0x611d, 0xac9e, 0x610d, 0xac8b, 0x60fc, 0xac78,
+  0x60ec, 0xac65, 0x60db, 0xac52, 0x60cb, 0xac3f, 0x60ba, 0xac2c,
+  0x60aa, 0xac19, 0x6099, 0xac06, 0x6089, 0xabf3, 0x6078, 0xabe0,
+  0x6068, 0xabcd, 0x6057, 0xabbb, 0x6047, 0xaba8, 0x6036, 0xab95,
+  0x6026, 0xab82, 0x6015, 0xab6f, 0x6004, 0xab5c, 0x5ff4, 0xab49,
+  0x5fe3, 0xab36, 0x5fd3, 0xab24, 0x5fc2, 0xab11, 0x5fb1, 0xaafe,
+  0x5fa0, 0xaaeb, 0x5f90, 0xaad8, 0x5f7f, 0xaac6, 0x5f6e, 0xaab3,
+  0x5f5e, 0xaaa0, 0x5f4d, 0xaa8e, 0x5f3c, 0xaa7b, 0x5f2b, 0xaa68,
+  0x5f1a, 0xaa55, 0x5f0a, 0xaa43, 0x5ef9, 0xaa30, 0x5ee8, 0xaa1d,
+  0x5ed7, 0xaa0b, 0x5ec6, 0xa9f8, 0x5eb5, 0xa9e6, 0x5ea4, 0xa9d3,
+  0x5e93, 0xa9c0, 0x5e82, 0xa9ae, 0x5e71, 0xa99b, 0x5e60, 0xa989,
+  0x5e50, 0xa976, 0x5e3f, 0xa964, 0x5e2d, 0xa951, 0x5e1c, 0xa93f,
+  0x5e0b, 0xa92c, 0x5dfa, 0xa91a, 0x5de9, 0xa907, 0x5dd8, 0xa8f5,
+  0x5dc7, 0xa8e3, 0x5db6, 0xa8d0, 0x5da5, 0xa8be, 0x5d94, 0xa8ab,
+  0x5d83, 0xa899, 0x5d71, 0xa887, 0x5d60, 0xa874, 0x5d4f, 0xa862,
+  0x5d3e, 0xa850, 0x5d2d, 0xa83d, 0x5d1b, 0xa82b, 0x5d0a, 0xa819,
+  0x5cf9, 0xa807, 0x5ce8, 0xa7f4, 0x5cd6, 0xa7e2, 0x5cc5, 0xa7d0,
+  0x5cb4, 0xa7be, 0x5ca2, 0xa7ab, 0x5c91, 0xa799, 0x5c80, 0xa787,
+  0x5c6e, 0xa775, 0x5c5d, 0xa763, 0x5c4b, 0xa751, 0x5c3a, 0xa73f,
+  0x5c29, 0xa72c, 0x5c17, 0xa71a, 0x5c06, 0xa708, 0x5bf4, 0xa6f6,
+  0x5be3, 0xa6e4, 0x5bd1, 0xa6d2, 0x5bc0, 0xa6c0, 0x5bae, 0xa6ae,
+  0x5b9d, 0xa69c, 0x5b8b, 0xa68a, 0x5b79, 0xa678, 0x5b68, 0xa666,
+  0x5b56, 0xa654, 0x5b45, 0xa642, 0x5b33, 0xa630, 0x5b21, 0xa61f,
+  0x5b10, 0xa60d, 0x5afe, 0xa5fb, 0x5aec, 0xa5e9, 0x5adb, 0xa5d7,
+  0x5ac9, 0xa5c5, 0x5ab7, 0xa5b3, 0x5aa5, 0xa5a2, 0x5a94, 0xa590,
+  0x5a82, 0xa57e, 0x5a70, 0xa56c, 0x5a5e, 0xa55b, 0x5a4d, 0xa549,
+  0x5a3b, 0xa537, 0x5a29, 0xa525, 0x5a17, 0xa514, 0x5a05, 0xa502,
+  0x59f3, 0xa4f0, 0x59e1, 0xa4df, 0x59d0, 0xa4cd, 0x59be, 0xa4bb,
+  0x59ac, 0xa4aa, 0x599a, 0xa498, 0x5988, 0xa487, 0x5976, 0xa475,
+  0x5964, 0xa463, 0x5952, 0xa452, 0x5940, 0xa440, 0x592e, 0xa42f,
+  0x591c, 0xa41d, 0x590a, 0xa40c, 0x58f8, 0xa3fa, 0x58e6, 0xa3e9,
+  0x58d4, 0xa3d7, 0x58c1, 0xa3c6, 0x58af, 0xa3b5, 0x589d, 0xa3a3,
+  0x588b, 0xa392, 0x5879, 0xa380, 0x5867, 0xa36f, 0x5855, 0xa35e,
+  0x5842, 0xa34c, 0x5830, 0xa33b, 0x581e, 0xa32a, 0x580c, 0xa318,
+  0x57f9, 0xa307, 0x57e7, 0xa2f6, 0x57d5, 0xa2e5, 0x57c3, 0xa2d3,
+  0x57b0, 0xa2c2, 0x579e, 0xa2b1, 0x578c, 0xa2a0, 0x5779, 0xa28f,
+  0x5767, 0xa27d, 0x5755, 0xa26c, 0x5742, 0xa25b, 0x5730, 0xa24a,
+  0x571d, 0xa239, 0x570b, 0xa228, 0x56f9, 0xa217, 0x56e6, 0xa206,
+  0x56d4, 0xa1f5, 0x56c1, 0xa1e4, 0x56af, 0xa1d3, 0x569c, 0xa1c1,
+  0x568a, 0xa1b0, 0x5677, 0xa1a0, 0x5665, 0xa18f, 0x5652, 0xa17e,
+  0x5640, 0xa16d, 0x562d, 0xa15c, 0x561a, 0xa14b, 0x5608, 0xa13a,
+  0x55f5, 0xa129, 0x55e3, 0xa118, 0x55d0, 0xa107, 0x55bd, 0xa0f6,
+  0x55ab, 0xa0e6, 0x5598, 0xa0d5, 0x5585, 0xa0c4, 0x5572, 0xa0b3,
+  0x5560, 0xa0a2, 0x554d, 0xa092, 0x553a, 0xa081, 0x5528, 0xa070,
+  0x5515, 0xa060, 0x5502, 0xa04f, 0x54ef, 0xa03e, 0x54dc, 0xa02d,
+  0x54ca, 0xa01d, 0x54b7, 0xa00c, 0x54a4, 0x9ffc, 0x5491, 0x9feb,
+  0x547e, 0x9fda, 0x546b, 0x9fca, 0x5458, 0x9fb9, 0x5445, 0x9fa9,
+  0x5433, 0x9f98, 0x5420, 0x9f88, 0x540d, 0x9f77, 0x53fa, 0x9f67,
+  0x53e7, 0x9f56, 0x53d4, 0x9f46, 0x53c1, 0x9f35, 0x53ae, 0x9f25,
+  0x539b, 0x9f14, 0x5388, 0x9f04, 0x5375, 0x9ef3, 0x5362, 0x9ee3,
+  0x534e, 0x9ed3, 0x533b, 0x9ec2, 0x5328, 0x9eb2, 0x5315, 0x9ea2,
+  0x5302, 0x9e91, 0x52ef, 0x9e81, 0x52dc, 0x9e71, 0x52c9, 0x9e61,
+  0x52b5, 0x9e50, 0x52a2, 0x9e40, 0x528f, 0x9e30, 0x527c, 0x9e20,
+  0x5269, 0x9e0f, 0x5255, 0x9dff, 0x5242, 0x9def, 0x522f, 0x9ddf,
+  0x521c, 0x9dcf, 0x5208, 0x9dbf, 0x51f5, 0x9daf, 0x51e2, 0x9d9f,
+  0x51ce, 0x9d8f, 0x51bb, 0x9d7e, 0x51a8, 0x9d6e, 0x5194, 0x9d5e,
+  0x5181, 0x9d4e, 0x516e, 0x9d3e, 0x515a, 0x9d2e, 0x5147, 0x9d1e,
+  0x5133, 0x9d0e, 0x5120, 0x9cff, 0x510c, 0x9cef, 0x50f9, 0x9cdf,
+  0x50e5, 0x9ccf, 0x50d2, 0x9cbf, 0x50bf, 0x9caf, 0x50ab, 0x9c9f,
+  0x5097, 0x9c8f, 0x5084, 0x9c80, 0x5070, 0x9c70, 0x505d, 0x9c60,
+  0x5049, 0x9c50, 0x5036, 0x9c40, 0x5022, 0x9c31, 0x500f, 0x9c21,
+  0x4ffb, 0x9c11, 0x4fe7, 0x9c02, 0x4fd4, 0x9bf2, 0x4fc0, 0x9be2,
+  0x4fac, 0x9bd3, 0x4f99, 0x9bc3, 0x4f85, 0x9bb3, 0x4f71, 0x9ba4,
+  0x4f5e, 0x9b94, 0x4f4a, 0x9b85, 0x4f36, 0x9b75, 0x4f22, 0x9b65,
+  0x4f0f, 0x9b56, 0x4efb, 0x9b46, 0x4ee7, 0x9b37, 0x4ed3, 0x9b27,
+  0x4ebf, 0x9b18, 0x4eac, 0x9b09, 0x4e98, 0x9af9, 0x4e84, 0x9aea,
+  0x4e70, 0x9ada, 0x4e5c, 0x9acb, 0x4e48, 0x9abb, 0x4e34, 0x9aac,
+  0x4e21, 0x9a9d, 0x4e0d, 0x9a8d, 0x4df9, 0x9a7e, 0x4de5, 0x9a6f,
+  0x4dd1, 0x9a60, 0x4dbd, 0x9a50, 0x4da9, 0x9a41, 0x4d95, 0x9a32,
+  0x4d81, 0x9a23, 0x4d6d, 0x9a13, 0x4d59, 0x9a04, 0x4d45, 0x99f5,
+  0x4d31, 0x99e6, 0x4d1d, 0x99d7, 0x4d09, 0x99c7, 0x4cf5, 0x99b8,
+  0x4ce1, 0x99a9, 0x4ccc, 0x999a, 0x4cb8, 0x998b, 0x4ca4, 0x997c,
+  0x4c90, 0x996d, 0x4c7c, 0x995e, 0x4c68, 0x994f, 0x4c54, 0x9940,
+  0x4c3f, 0x9931, 0x4c2b, 0x9922, 0x4c17, 0x9913, 0x4c03, 0x9904,
+  0x4bef, 0x98f5, 0x4bda, 0x98e6, 0x4bc6, 0x98d7, 0x4bb2, 0x98c9,
+  0x4b9e, 0x98ba, 0x4b89, 0x98ab, 0x4b75, 0x989c, 0x4b61, 0x988d,
+  0x4b4c, 0x987e, 0x4b38, 0x9870, 0x4b24, 0x9861, 0x4b0f, 0x9852,
+  0x4afb, 0x9843, 0x4ae7, 0x9835, 0x4ad2, 0x9826, 0x4abe, 0x9817,
+  0x4aa9, 0x9809, 0x4a95, 0x97fa, 0x4a81, 0x97eb, 0x4a6c, 0x97dd,
+  0x4a58, 0x97ce, 0x4a43, 0x97c0, 0x4a2f, 0x97b1, 0x4a1a, 0x97a2,
+  0x4a06, 0x9794, 0x49f1, 0x9785, 0x49dd, 0x9777, 0x49c8, 0x9768,
+  0x49b4, 0x975a, 0x499f, 0x974b, 0x498a, 0x973d, 0x4976, 0x972f,
+  0x4961, 0x9720, 0x494d, 0x9712, 0x4938, 0x9703, 0x4923, 0x96f5,
+  0x490f, 0x96e7, 0x48fa, 0x96d8, 0x48e6, 0x96ca, 0x48d1, 0x96bc,
+  0x48bc, 0x96ad, 0x48a8, 0x969f, 0x4893, 0x9691, 0x487e, 0x9683,
+  0x4869, 0x9674, 0x4855, 0x9666, 0x4840, 0x9658, 0x482b, 0x964a,
+  0x4816, 0x963c, 0x4802, 0x962d, 0x47ed, 0x961f, 0x47d8, 0x9611,
+  0x47c3, 0x9603, 0x47ae, 0x95f5, 0x479a, 0x95e7, 0x4785, 0x95d9,
+  0x4770, 0x95cb, 0x475b, 0x95bd, 0x4746, 0x95af, 0x4731, 0x95a1,
+  0x471c, 0x9593, 0x4708, 0x9585, 0x46f3, 0x9577, 0x46de, 0x9569,
+  0x46c9, 0x955b, 0x46b4, 0x954d, 0x469f, 0x953f, 0x468a, 0x9532,
+  0x4675, 0x9524, 0x4660, 0x9516, 0x464b, 0x9508, 0x4636, 0x94fa,
+  0x4621, 0x94ed, 0x460c, 0x94df, 0x45f7, 0x94d1, 0x45e2, 0x94c3,
+  0x45cd, 0x94b6, 0x45b8, 0x94a8, 0x45a3, 0x949a, 0x458d, 0x948d,
+  0x4578, 0x947f, 0x4563, 0x9471, 0x454e, 0x9464, 0x4539, 0x9456,
+  0x4524, 0x9448, 0x450f, 0x943b, 0x44fa, 0x942d, 0x44e4, 0x9420,
+  0x44cf, 0x9412, 0x44ba, 0x9405, 0x44a5, 0x93f7, 0x4490, 0x93ea,
+  0x447a, 0x93dc, 0x4465, 0x93cf, 0x4450, 0x93c1, 0x443b, 0x93b4,
+  0x4425, 0x93a7, 0x4410, 0x9399, 0x43fb, 0x938c, 0x43e5, 0x937f,
+  0x43d0, 0x9371, 0x43bb, 0x9364, 0x43a5, 0x9357, 0x4390, 0x9349,
+  0x437b, 0x933c, 0x4365, 0x932f, 0x4350, 0x9322, 0x433b, 0x9314,
+  0x4325, 0x9307, 0x4310, 0x92fa, 0x42fa, 0x92ed, 0x42e5, 0x92e0,
+  0x42d0, 0x92d3, 0x42ba, 0x92c6, 0x42a5, 0x92b8, 0x428f, 0x92ab,
+  0x427a, 0x929e, 0x4264, 0x9291, 0x424f, 0x9284, 0x4239, 0x9277,
+  0x4224, 0x926a, 0x420e, 0x925d, 0x41f9, 0x9250, 0x41e3, 0x9243,
+  0x41ce, 0x9236, 0x41b8, 0x922a, 0x41a2, 0x921d, 0x418d, 0x9210,
+  0x4177, 0x9203, 0x4162, 0x91f6, 0x414c, 0x91e9, 0x4136, 0x91dc,
+  0x4121, 0x91d0, 0x410b, 0x91c3, 0x40f6, 0x91b6, 0x40e0, 0x91a9,
+  0x40ca, 0x919d, 0x40b5, 0x9190, 0x409f, 0x9183, 0x4089, 0x9177,
+  0x4073, 0x916a, 0x405e, 0x915d, 0x4048, 0x9151, 0x4032, 0x9144,
+  0x401d, 0x9137, 0x4007, 0x912b, 0x3ff1, 0x911e, 0x3fdb, 0x9112,
+  0x3fc5, 0x9105, 0x3fb0, 0x90f9, 0x3f9a, 0x90ec, 0x3f84, 0x90e0,
+  0x3f6e, 0x90d3, 0x3f58, 0x90c7, 0x3f43, 0x90ba, 0x3f2d, 0x90ae,
+  0x3f17, 0x90a1, 0x3f01, 0x9095, 0x3eeb, 0x9089, 0x3ed5, 0x907c,
+  0x3ebf, 0x9070, 0x3ea9, 0x9064, 0x3e93, 0x9057, 0x3e7d, 0x904b,
+  0x3e68, 0x903f, 0x3e52, 0x9033, 0x3e3c, 0x9026, 0x3e26, 0x901a,
+  0x3e10, 0x900e, 0x3dfa, 0x9002, 0x3de4, 0x8ff6, 0x3dce, 0x8fea,
+  0x3db8, 0x8fdd, 0x3da2, 0x8fd1, 0x3d8c, 0x8fc5, 0x3d76, 0x8fb9,
+  0x3d60, 0x8fad, 0x3d49, 0x8fa1, 0x3d33, 0x8f95, 0x3d1d, 0x8f89,
+  0x3d07, 0x8f7d, 0x3cf1, 0x8f71, 0x3cdb, 0x8f65, 0x3cc5, 0x8f59,
+  0x3caf, 0x8f4d, 0x3c99, 0x8f41, 0x3c83, 0x8f35, 0x3c6c, 0x8f2a,
+  0x3c56, 0x8f1e, 0x3c40, 0x8f12, 0x3c2a, 0x8f06, 0x3c14, 0x8efa,
+  0x3bfd, 0x8eee, 0x3be7, 0x8ee3, 0x3bd1, 0x8ed7, 0x3bbb, 0x8ecb,
+  0x3ba5, 0x8ebf, 0x3b8e, 0x8eb4, 0x3b78, 0x8ea8, 0x3b62, 0x8e9c,
+  0x3b4c, 0x8e91, 0x3b35, 0x8e85, 0x3b1f, 0x8e7a, 0x3b09, 0x8e6e,
+  0x3af2, 0x8e62, 0x3adc, 0x8e57, 0x3ac6, 0x8e4b, 0x3aaf, 0x8e40,
+  0x3a99, 0x8e34, 0x3a83, 0x8e29, 0x3a6c, 0x8e1d, 0x3a56, 0x8e12,
+  0x3a40, 0x8e06, 0x3a29, 0x8dfb, 0x3a13, 0x8def, 0x39fd, 0x8de4,
+  0x39e6, 0x8dd9, 0x39d0, 0x8dcd, 0x39b9, 0x8dc2, 0x39a3, 0x8db7,
+  0x398c, 0x8dab, 0x3976, 0x8da0, 0x395f, 0x8d95, 0x3949, 0x8d8a,
+  0x3932, 0x8d7e, 0x391c, 0x8d73, 0x3906, 0x8d68, 0x38ef, 0x8d5d,
+  0x38d8, 0x8d51, 0x38c2, 0x8d46, 0x38ab, 0x8d3b, 0x3895, 0x8d30,
+  0x387e, 0x8d25, 0x3868, 0x8d1a, 0x3851, 0x8d0f, 0x383b, 0x8d04,
+  0x3824, 0x8cf9, 0x380d, 0x8cee, 0x37f7, 0x8ce3, 0x37e0, 0x8cd8,
+  0x37ca, 0x8ccd, 0x37b3, 0x8cc2, 0x379c, 0x8cb7, 0x3786, 0x8cac,
+  0x376f, 0x8ca1, 0x3758, 0x8c96, 0x3742, 0x8c8b, 0x372b, 0x8c81,
+  0x3714, 0x8c76, 0x36fe, 0x8c6b, 0x36e7, 0x8c60, 0x36d0, 0x8c55,
+  0x36ba, 0x8c4b, 0x36a3, 0x8c40, 0x368c, 0x8c35, 0x3675, 0x8c2a,
+  0x365f, 0x8c20, 0x3648, 0x8c15, 0x3631, 0x8c0a, 0x361a, 0x8c00,
+  0x3604, 0x8bf5, 0x35ed, 0x8beb, 0x35d6, 0x8be0, 0x35bf, 0x8bd5,
+  0x35a8, 0x8bcb, 0x3592, 0x8bc0, 0x357b, 0x8bb6, 0x3564, 0x8bab,
+  0x354d, 0x8ba1, 0x3536, 0x8b96, 0x351f, 0x8b8c, 0x3508, 0x8b82,
+  0x34f2, 0x8b77, 0x34db, 0x8b6d, 0x34c4, 0x8b62, 0x34ad, 0x8b58,
+  0x3496, 0x8b4e, 0x347f, 0x8b43, 0x3468, 0x8b39, 0x3451, 0x8b2f,
+  0x343a, 0x8b25, 0x3423, 0x8b1a, 0x340c, 0x8b10, 0x33f5, 0x8b06,
+  0x33de, 0x8afc, 0x33c7, 0x8af1, 0x33b0, 0x8ae7, 0x3399, 0x8add,
+  0x3382, 0x8ad3, 0x336b, 0x8ac9, 0x3354, 0x8abf, 0x333d, 0x8ab5,
+  0x3326, 0x8aab, 0x330f, 0x8aa1, 0x32f8, 0x8a97, 0x32e1, 0x8a8d,
+  0x32ca, 0x8a83, 0x32b3, 0x8a79, 0x329c, 0x8a6f, 0x3285, 0x8a65,
+  0x326e, 0x8a5b, 0x3257, 0x8a51, 0x3240, 0x8a47, 0x3228, 0x8a3d,
+  0x3211, 0x8a34, 0x31fa, 0x8a2a, 0x31e3, 0x8a20, 0x31cc, 0x8a16,
+  0x31b5, 0x8a0c, 0x319e, 0x8a03, 0x3186, 0x89f9, 0x316f, 0x89ef,
+  0x3158, 0x89e5, 0x3141, 0x89dc, 0x312a, 0x89d2, 0x3112, 0x89c8,
+  0x30fb, 0x89bf, 0x30e4, 0x89b5, 0x30cd, 0x89ac, 0x30b6, 0x89a2,
+  0x309e, 0x8998, 0x3087, 0x898f, 0x3070, 0x8985, 0x3059, 0x897c,
+  0x3041, 0x8972, 0x302a, 0x8969, 0x3013, 0x8960, 0x2ffb, 0x8956,
+  0x2fe4, 0x894d, 0x2fcd, 0x8943, 0x2fb5, 0x893a, 0x2f9e, 0x8931,
+  0x2f87, 0x8927, 0x2f6f, 0x891e, 0x2f58, 0x8915, 0x2f41, 0x890b,
+  0x2f29, 0x8902, 0x2f12, 0x88f9, 0x2efb, 0x88f0, 0x2ee3, 0x88e6,
+  0x2ecc, 0x88dd, 0x2eb5, 0x88d4, 0x2e9d, 0x88cb, 0x2e86, 0x88c2,
+  0x2e6e, 0x88b9, 0x2e57, 0x88af, 0x2e3f, 0x88a6, 0x2e28, 0x889d,
+  0x2e11, 0x8894, 0x2df9, 0x888b, 0x2de2, 0x8882, 0x2dca, 0x8879,
+  0x2db3, 0x8870, 0x2d9b, 0x8867, 0x2d84, 0x885e, 0x2d6c, 0x8855,
+  0x2d55, 0x884c, 0x2d3d, 0x8844, 0x2d26, 0x883b, 0x2d0e, 0x8832,
+  0x2cf7, 0x8829, 0x2cdf, 0x8820, 0x2cc8, 0x8817, 0x2cb0, 0x880f,
+  0x2c98, 0x8806, 0x2c81, 0x87fd, 0x2c69, 0x87f4, 0x2c52, 0x87ec,
+  0x2c3a, 0x87e3, 0x2c23, 0x87da, 0x2c0b, 0x87d2, 0x2bf3, 0x87c9,
+  0x2bdc, 0x87c0, 0x2bc4, 0x87b8, 0x2bad, 0x87af, 0x2b95, 0x87a7,
+  0x2b7d, 0x879e, 0x2b66, 0x8795, 0x2b4e, 0x878d, 0x2b36, 0x8784,
+  0x2b1f, 0x877c, 0x2b07, 0x8774, 0x2aef, 0x876b, 0x2ad8, 0x8763,
+  0x2ac0, 0x875a, 0x2aa8, 0x8752, 0x2a91, 0x874a, 0x2a79, 0x8741,
+  0x2a61, 0x8739, 0x2a49, 0x8731, 0x2a32, 0x8728, 0x2a1a, 0x8720,
+  0x2a02, 0x8718, 0x29eb, 0x870f, 0x29d3, 0x8707, 0x29bb, 0x86ff,
+  0x29a3, 0x86f7, 0x298b, 0x86ef, 0x2974, 0x86e7, 0x295c, 0x86de,
+  0x2944, 0x86d6, 0x292c, 0x86ce, 0x2915, 0x86c6, 0x28fd, 0x86be,
+  0x28e5, 0x86b6, 0x28cd, 0x86ae, 0x28b5, 0x86a6, 0x289d, 0x869e,
+  0x2886, 0x8696, 0x286e, 0x868e, 0x2856, 0x8686, 0x283e, 0x867e,
+  0x2826, 0x8676, 0x280e, 0x866e, 0x27f6, 0x8667, 0x27df, 0x865f,
+  0x27c7, 0x8657, 0x27af, 0x864f, 0x2797, 0x8647, 0x277f, 0x8640,
+  0x2767, 0x8638, 0x274f, 0x8630, 0x2737, 0x8628, 0x271f, 0x8621,
+  0x2707, 0x8619, 0x26ef, 0x8611, 0x26d8, 0x860a, 0x26c0, 0x8602,
+  0x26a8, 0x85fb, 0x2690, 0x85f3, 0x2678, 0x85eb, 0x2660, 0x85e4,
+  0x2648, 0x85dc, 0x2630, 0x85d5, 0x2618, 0x85cd, 0x2600, 0x85c6,
+  0x25e8, 0x85be, 0x25d0, 0x85b7, 0x25b8, 0x85b0, 0x25a0, 0x85a8,
+  0x2588, 0x85a1, 0x2570, 0x8599, 0x2558, 0x8592, 0x2540, 0x858b,
+  0x2528, 0x8583, 0x250f, 0x857c, 0x24f7, 0x8575, 0x24df, 0x856e,
+  0x24c7, 0x8566, 0x24af, 0x855f, 0x2497, 0x8558, 0x247f, 0x8551,
+  0x2467, 0x854a, 0x244f, 0x8543, 0x2437, 0x853b, 0x241f, 0x8534,
+  0x2407, 0x852d, 0x23ee, 0x8526, 0x23d6, 0x851f, 0x23be, 0x8518,
+  0x23a6, 0x8511, 0x238e, 0x850a, 0x2376, 0x8503, 0x235e, 0x84fc,
+  0x2345, 0x84f5, 0x232d, 0x84ee, 0x2315, 0x84e7, 0x22fd, 0x84e1,
+  0x22e5, 0x84da, 0x22cd, 0x84d3, 0x22b4, 0x84cc, 0x229c, 0x84c5,
+  0x2284, 0x84be, 0x226c, 0x84b8, 0x2254, 0x84b1, 0x223b, 0x84aa,
+  0x2223, 0x84a3, 0x220b, 0x849d, 0x21f3, 0x8496, 0x21da, 0x848f,
+  0x21c2, 0x8489, 0x21aa, 0x8482, 0x2192, 0x847c, 0x2179, 0x8475,
+  0x2161, 0x846e, 0x2149, 0x8468, 0x2131, 0x8461, 0x2118, 0x845b,
+  0x2100, 0x8454, 0x20e8, 0x844e, 0x20d0, 0x8447, 0x20b7, 0x8441,
+  0x209f, 0x843b, 0x2087, 0x8434, 0x206e, 0x842e, 0x2056, 0x8427,
+  0x203e, 0x8421, 0x2025, 0x841b, 0x200d, 0x8415, 0x1ff5, 0x840e,
+  0x1fdc, 0x8408, 0x1fc4, 0x8402, 0x1fac, 0x83fb, 0x1f93, 0x83f5,
+  0x1f7b, 0x83ef, 0x1f63, 0x83e9, 0x1f4a, 0x83e3, 0x1f32, 0x83dd,
+  0x1f19, 0x83d7, 0x1f01, 0x83d0, 0x1ee9, 0x83ca, 0x1ed0, 0x83c4,
+  0x1eb8, 0x83be, 0x1ea0, 0x83b8, 0x1e87, 0x83b2, 0x1e6f, 0x83ac,
+  0x1e56, 0x83a6, 0x1e3e, 0x83a0, 0x1e25, 0x839a, 0x1e0d, 0x8394,
+  0x1df5, 0x838f, 0x1ddc, 0x8389, 0x1dc4, 0x8383, 0x1dab, 0x837d,
+  0x1d93, 0x8377, 0x1d7a, 0x8371, 0x1d62, 0x836c, 0x1d49, 0x8366,
+  0x1d31, 0x8360, 0x1d18, 0x835a, 0x1d00, 0x8355, 0x1ce8, 0x834f,
+  0x1ccf, 0x8349, 0x1cb7, 0x8344, 0x1c9e, 0x833e, 0x1c86, 0x8338,
+  0x1c6d, 0x8333, 0x1c55, 0x832d, 0x1c3c, 0x8328, 0x1c24, 0x8322,
+  0x1c0b, 0x831d, 0x1bf2, 0x8317, 0x1bda, 0x8312, 0x1bc1, 0x830c,
+  0x1ba9, 0x8307, 0x1b90, 0x8301, 0x1b78, 0x82fc, 0x1b5f, 0x82f7,
+  0x1b47, 0x82f1, 0x1b2e, 0x82ec, 0x1b16, 0x82e7, 0x1afd, 0x82e1,
+  0x1ae4, 0x82dc, 0x1acc, 0x82d7, 0x1ab3, 0x82d1, 0x1a9b, 0x82cc,
+  0x1a82, 0x82c7, 0x1a6a, 0x82c2, 0x1a51, 0x82bd, 0x1a38, 0x82b7,
+  0x1a20, 0x82b2, 0x1a07, 0x82ad, 0x19ef, 0x82a8, 0x19d6, 0x82a3,
+  0x19bd, 0x829e, 0x19a5, 0x8299, 0x198c, 0x8294, 0x1973, 0x828f,
+  0x195b, 0x828a, 0x1942, 0x8285, 0x192a, 0x8280, 0x1911, 0x827b,
+  0x18f8, 0x8276, 0x18e0, 0x8271, 0x18c7, 0x826c, 0x18ae, 0x8268,
+  0x1896, 0x8263, 0x187d, 0x825e, 0x1864, 0x8259, 0x184c, 0x8254,
+  0x1833, 0x8250, 0x181a, 0x824b, 0x1802, 0x8246, 0x17e9, 0x8241,
+  0x17d0, 0x823d, 0x17b7, 0x8238, 0x179f, 0x8233, 0x1786, 0x822f,
+  0x176d, 0x822a, 0x1755, 0x8226, 0x173c, 0x8221, 0x1723, 0x821c,
+  0x170a, 0x8218, 0x16f2, 0x8213, 0x16d9, 0x820f, 0x16c0, 0x820a,
+  0x16a8, 0x8206, 0x168f, 0x8201, 0x1676, 0x81fd, 0x165d, 0x81f9,
+  0x1645, 0x81f4, 0x162c, 0x81f0, 0x1613, 0x81ec, 0x15fa, 0x81e7,
+  0x15e2, 0x81e3, 0x15c9, 0x81df, 0x15b0, 0x81da, 0x1597, 0x81d6,
+  0x157f, 0x81d2, 0x1566, 0x81ce, 0x154d, 0x81c9, 0x1534, 0x81c5,
+  0x151b, 0x81c1, 0x1503, 0x81bd, 0x14ea, 0x81b9, 0x14d1, 0x81b5,
+  0x14b8, 0x81b1, 0x149f, 0x81ad, 0x1487, 0x81a9, 0x146e, 0x81a5,
+  0x1455, 0x81a1, 0x143c, 0x819d, 0x1423, 0x8199, 0x140b, 0x8195,
+  0x13f2, 0x8191, 0x13d9, 0x818d, 0x13c0, 0x8189, 0x13a7, 0x8185,
+  0x138e, 0x8181, 0x1376, 0x817d, 0x135d, 0x817a, 0x1344, 0x8176,
+  0x132b, 0x8172, 0x1312, 0x816e, 0x12f9, 0x816b, 0x12e0, 0x8167,
+  0x12c8, 0x8163, 0x12af, 0x815f, 0x1296, 0x815c, 0x127d, 0x8158,
+  0x1264, 0x8155, 0x124b, 0x8151, 0x1232, 0x814d, 0x1219, 0x814a,
+  0x1201, 0x8146, 0x11e8, 0x8143, 0x11cf, 0x813f, 0x11b6, 0x813c,
+  0x119d, 0x8138, 0x1184, 0x8135, 0x116b, 0x8131, 0x1152, 0x812e,
+  0x1139, 0x812b, 0x1121, 0x8127, 0x1108, 0x8124, 0x10ef, 0x8121,
+  0x10d6, 0x811d, 0x10bd, 0x811a, 0x10a4, 0x8117, 0x108b, 0x8113,
+  0x1072, 0x8110, 0x1059, 0x810d, 0x1040, 0x810a, 0x1027, 0x8107,
+  0x100e, 0x8103, 0xff5, 0x8100, 0xfdd, 0x80fd, 0xfc4, 0x80fa,
+  0xfab, 0x80f7, 0xf92, 0x80f4, 0xf79, 0x80f1, 0xf60, 0x80ee,
+  0xf47, 0x80eb, 0xf2e, 0x80e8, 0xf15, 0x80e5, 0xefc, 0x80e2,
+  0xee3, 0x80df, 0xeca, 0x80dc, 0xeb1, 0x80d9, 0xe98, 0x80d6,
+  0xe7f, 0x80d3, 0xe66, 0x80d1, 0xe4d, 0x80ce, 0xe34, 0x80cb,
+  0xe1b, 0x80c8, 0xe02, 0x80c5, 0xde9, 0x80c3, 0xdd0, 0x80c0,
+  0xdb7, 0x80bd, 0xd9e, 0x80bb, 0xd85, 0x80b8, 0xd6c, 0x80b5,
+  0xd53, 0x80b3, 0xd3a, 0x80b0, 0xd21, 0x80ad, 0xd08, 0x80ab,
+  0xcef, 0x80a8, 0xcd6, 0x80a6, 0xcbd, 0x80a3, 0xca4, 0x80a1,
+  0xc8b, 0x809e, 0xc72, 0x809c, 0xc59, 0x8099, 0xc40, 0x8097,
+  0xc27, 0x8095, 0xc0e, 0x8092, 0xbf5, 0x8090, 0xbdc, 0x808e,
+  0xbc3, 0x808b, 0xbaa, 0x8089, 0xb91, 0x8087, 0xb78, 0x8084,
+  0xb5f, 0x8082, 0xb46, 0x8080, 0xb2d, 0x807e, 0xb14, 0x807b,
+  0xafb, 0x8079, 0xae2, 0x8077, 0xac9, 0x8075, 0xab0, 0x8073,
+  0xa97, 0x8071, 0xa7e, 0x806f, 0xa65, 0x806d, 0xa4c, 0x806b,
+  0xa33, 0x8069, 0xa19, 0x8067, 0xa00, 0x8065, 0x9e7, 0x8063,
+  0x9ce, 0x8061, 0x9b5, 0x805f, 0x99c, 0x805d, 0x983, 0x805b,
+  0x96a, 0x8059, 0x951, 0x8057, 0x938, 0x8056, 0x91f, 0x8054,
+  0x906, 0x8052, 0x8ed, 0x8050, 0x8d4, 0x804f, 0x8bb, 0x804d,
+  0x8a2, 0x804b, 0x888, 0x8049, 0x86f, 0x8048, 0x856, 0x8046,
+  0x83d, 0x8044, 0x824, 0x8043, 0x80b, 0x8041, 0x7f2, 0x8040,
+  0x7d9, 0x803e, 0x7c0, 0x803d, 0x7a7, 0x803b, 0x78e, 0x803a,
+  0x775, 0x8038, 0x75b, 0x8037, 0x742, 0x8035, 0x729, 0x8034,
+  0x710, 0x8032, 0x6f7, 0x8031, 0x6de, 0x8030, 0x6c5, 0x802e,
+  0x6ac, 0x802d, 0x693, 0x802c, 0x67a, 0x802a, 0x660, 0x8029,
+  0x647, 0x8028, 0x62e, 0x8027, 0x615, 0x8026, 0x5fc, 0x8024,
+  0x5e3, 0x8023, 0x5ca, 0x8022, 0x5b1, 0x8021, 0x598, 0x8020,
+  0x57f, 0x801f, 0x565, 0x801e, 0x54c, 0x801d, 0x533, 0x801c,
+  0x51a, 0x801b, 0x501, 0x801a, 0x4e8, 0x8019, 0x4cf, 0x8018,
+  0x4b6, 0x8017, 0x49c, 0x8016, 0x483, 0x8015, 0x46a, 0x8014,
+  0x451, 0x8013, 0x438, 0x8012, 0x41f, 0x8012, 0x406, 0x8011,
+  0x3ed, 0x8010, 0x3d4, 0x800f, 0x3ba, 0x800e, 0x3a1, 0x800e,
+  0x388, 0x800d, 0x36f, 0x800c, 0x356, 0x800c, 0x33d, 0x800b,
+  0x324, 0x800a, 0x30b, 0x800a, 0x2f1, 0x8009, 0x2d8, 0x8009,
+  0x2bf, 0x8008, 0x2a6, 0x8008, 0x28d, 0x8007, 0x274, 0x8007,
+  0x25b, 0x8006, 0x242, 0x8006, 0x228, 0x8005, 0x20f, 0x8005,
+  0x1f6, 0x8004, 0x1dd, 0x8004, 0x1c4, 0x8004, 0x1ab, 0x8003,
+  0x192, 0x8003, 0x178, 0x8003, 0x15f, 0x8002, 0x146, 0x8002,
+  0x12d, 0x8002, 0x114, 0x8002, 0xfb, 0x8001, 0xe2, 0x8001,
+  0xc9, 0x8001, 0xaf, 0x8001, 0x96, 0x8001, 0x7d, 0x8001,
+  0x64, 0x8001, 0x4b, 0x8001, 0x32, 0x8001, 0x19, 0x8001,
+};
+
+/**   
+* \par   
+* cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) 
   
+* \par   
+* C command to generate the table   
+* 
   
+* for(i = 0; i< N; i++)   
+* {   
+*   cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+* } 
   
+* \par   
+* where N is the number of factors to generate and c is pi/(2*N)   
+* \par   
+* Then converted to q15 format by multiplying with 2^31 and saturated if required.   
+   
+*/
+
+static const q15_t cos_factorsQ15_128[128] = {
+  0x7fff, 0x7ffa, 0x7ff0, 0x7fe1, 0x7fce, 0x7fb5, 0x7f97, 0x7f75,
+  0x7f4d, 0x7f21, 0x7ef0, 0x7eba, 0x7e7f, 0x7e3f, 0x7dfa, 0x7db0,
+  0x7d62, 0x7d0f, 0x7cb7, 0x7c5a, 0x7bf8, 0x7b92, 0x7b26, 0x7ab6,
+  0x7a42, 0x79c8, 0x794a, 0x78c7, 0x7840, 0x77b4, 0x7723, 0x768e,
+  0x75f4, 0x7555, 0x74b2, 0x740b, 0x735f, 0x72af, 0x71fa, 0x7141,
+  0x7083, 0x6fc1, 0x6efb, 0x6e30, 0x6d62, 0x6c8f, 0x6bb8, 0x6adc,
+  0x69fd, 0x6919, 0x6832, 0x6746, 0x6657, 0x6563, 0x646c, 0x6371,
+  0x6271, 0x616f, 0x6068, 0x5f5e, 0x5e50, 0x5d3e, 0x5c29, 0x5b10,
+  0x59f3, 0x58d4, 0x57b0, 0x568a, 0x5560, 0x5433, 0x5302, 0x51ce,
+  0x5097, 0x4f5e, 0x4e21, 0x4ce1, 0x4b9e, 0x4a58, 0x490f, 0x47c3,
+  0x4675, 0x4524, 0x43d0, 0x427a, 0x4121, 0x3fc5, 0x3e68, 0x3d07,
+  0x3ba5, 0x3a40, 0x38d8, 0x376f, 0x3604, 0x3496, 0x3326, 0x31b5,
+  0x3041, 0x2ecc, 0x2d55, 0x2bdc, 0x2a61, 0x28e5, 0x2767, 0x25e8,
+  0x2467, 0x22e5, 0x2161, 0x1fdc, 0x1e56, 0x1ccf, 0x1b47, 0x19bd,
+  0x1833, 0x16a8, 0x151b, 0x138e, 0x1201, 0x1072, 0xee3, 0xd53,
+  0xbc3, 0xa33, 0x8a2, 0x710, 0x57f, 0x3ed, 0x25b, 0xc9
+};
+
+static const q15_t cos_factorsQ15_512[512] = {
+  0x7fff, 0x7fff, 0x7fff, 0x7ffe, 0x7ffc, 0x7ffb, 0x7ff9, 0x7ff7,
+  0x7ff4, 0x7ff2, 0x7fee, 0x7feb, 0x7fe7, 0x7fe3, 0x7fdf, 0x7fda,
+  0x7fd6, 0x7fd0, 0x7fcb, 0x7fc5, 0x7fbf, 0x7fb8, 0x7fb1, 0x7faa,
+  0x7fa3, 0x7f9b, 0x7f93, 0x7f8b, 0x7f82, 0x7f79, 0x7f70, 0x7f67,
+  0x7f5d, 0x7f53, 0x7f48, 0x7f3d, 0x7f32, 0x7f27, 0x7f1b, 0x7f0f,
+  0x7f03, 0x7ef6, 0x7ee9, 0x7edc, 0x7ecf, 0x7ec1, 0x7eb3, 0x7ea4,
+  0x7e95, 0x7e86, 0x7e77, 0x7e67, 0x7e57, 0x7e47, 0x7e37, 0x7e26,
+  0x7e14, 0x7e03, 0x7df1, 0x7ddf, 0x7dcd, 0x7dba, 0x7da7, 0x7d94,
+  0x7d80, 0x7d6c, 0x7d58, 0x7d43, 0x7d2f, 0x7d19, 0x7d04, 0x7cee,
+  0x7cd8, 0x7cc2, 0x7cab, 0x7c94, 0x7c7d, 0x7c66, 0x7c4e, 0x7c36,
+  0x7c1d, 0x7c05, 0x7beb, 0x7bd2, 0x7bb9, 0x7b9f, 0x7b84, 0x7b6a,
+  0x7b4f, 0x7b34, 0x7b19, 0x7afd, 0x7ae1, 0x7ac5, 0x7aa8, 0x7a8b,
+  0x7a6e, 0x7a50, 0x7a33, 0x7a15, 0x79f6, 0x79d8, 0x79b9, 0x7999,
+  0x797a, 0x795a, 0x793a, 0x7919, 0x78f9, 0x78d8, 0x78b6, 0x7895,
+  0x7873, 0x7851, 0x782e, 0x780c, 0x77e9, 0x77c5, 0x77a2, 0x777e,
+  0x775a, 0x7735, 0x7710, 0x76eb, 0x76c6, 0x76a0, 0x767b, 0x7654,
+  0x762e, 0x7607, 0x75e0, 0x75b9, 0x7591, 0x7569, 0x7541, 0x7519,
+  0x74f0, 0x74c7, 0x749e, 0x7474, 0x744a, 0x7420, 0x73f6, 0x73cb,
+  0x73a0, 0x7375, 0x7349, 0x731d, 0x72f1, 0x72c5, 0x7298, 0x726b,
+  0x723e, 0x7211, 0x71e3, 0x71b5, 0x7186, 0x7158, 0x7129, 0x70fa,
+  0x70cb, 0x709b, 0x706b, 0x703b, 0x700a, 0x6fda, 0x6fa9, 0x6f77,
+  0x6f46, 0x6f14, 0x6ee2, 0x6eaf, 0x6e7d, 0x6e4a, 0x6e17, 0x6de3,
+  0x6db0, 0x6d7c, 0x6d48, 0x6d13, 0x6cde, 0x6ca9, 0x6c74, 0x6c3f,
+  0x6c09, 0x6bd3, 0x6b9c, 0x6b66, 0x6b2f, 0x6af8, 0x6ac1, 0x6a89,
+  0x6a51, 0x6a19, 0x69e1, 0x69a8, 0x696f, 0x6936, 0x68fd, 0x68c3,
+  0x6889, 0x684f, 0x6815, 0x67da, 0x679f, 0x6764, 0x6729, 0x66ed,
+  0x66b1, 0x6675, 0x6639, 0x65fc, 0x65bf, 0x6582, 0x6545, 0x6507,
+  0x64c9, 0x648b, 0x644d, 0x640e, 0x63cf, 0x6390, 0x6351, 0x6311,
+  0x62d2, 0x6292, 0x6251, 0x6211, 0x61d0, 0x618f, 0x614e, 0x610d,
+  0x60cb, 0x6089, 0x6047, 0x6004, 0x5fc2, 0x5f7f, 0x5f3c, 0x5ef9,
+  0x5eb5, 0x5e71, 0x5e2d, 0x5de9, 0x5da5, 0x5d60, 0x5d1b, 0x5cd6,
+  0x5c91, 0x5c4b, 0x5c06, 0x5bc0, 0x5b79, 0x5b33, 0x5aec, 0x5aa5,
+  0x5a5e, 0x5a17, 0x59d0, 0x5988, 0x5940, 0x58f8, 0x58af, 0x5867,
+  0x581e, 0x57d5, 0x578c, 0x5742, 0x56f9, 0x56af, 0x5665, 0x561a,
+  0x55d0, 0x5585, 0x553a, 0x54ef, 0x54a4, 0x5458, 0x540d, 0x53c1,
+  0x5375, 0x5328, 0x52dc, 0x528f, 0x5242, 0x51f5, 0x51a8, 0x515a,
+  0x510c, 0x50bf, 0x5070, 0x5022, 0x4fd4, 0x4f85, 0x4f36, 0x4ee7,
+  0x4e98, 0x4e48, 0x4df9, 0x4da9, 0x4d59, 0x4d09, 0x4cb8, 0x4c68,
+  0x4c17, 0x4bc6, 0x4b75, 0x4b24, 0x4ad2, 0x4a81, 0x4a2f, 0x49dd,
+  0x498a, 0x4938, 0x48e6, 0x4893, 0x4840, 0x47ed, 0x479a, 0x4746,
+  0x46f3, 0x469f, 0x464b, 0x45f7, 0x45a3, 0x454e, 0x44fa, 0x44a5,
+  0x4450, 0x43fb, 0x43a5, 0x4350, 0x42fa, 0x42a5, 0x424f, 0x41f9,
+  0x41a2, 0x414c, 0x40f6, 0x409f, 0x4048, 0x3ff1, 0x3f9a, 0x3f43,
+  0x3eeb, 0x3e93, 0x3e3c, 0x3de4, 0x3d8c, 0x3d33, 0x3cdb, 0x3c83,
+  0x3c2a, 0x3bd1, 0x3b78, 0x3b1f, 0x3ac6, 0x3a6c, 0x3a13, 0x39b9,
+  0x395f, 0x3906, 0x38ab, 0x3851, 0x37f7, 0x379c, 0x3742, 0x36e7,
+  0x368c, 0x3631, 0x35d6, 0x357b, 0x351f, 0x34c4, 0x3468, 0x340c,
+  0x33b0, 0x3354, 0x32f8, 0x329c, 0x3240, 0x31e3, 0x3186, 0x312a,
+  0x30cd, 0x3070, 0x3013, 0x2fb5, 0x2f58, 0x2efb, 0x2e9d, 0x2e3f,
+  0x2de2, 0x2d84, 0x2d26, 0x2cc8, 0x2c69, 0x2c0b, 0x2bad, 0x2b4e,
+  0x2aef, 0x2a91, 0x2a32, 0x29d3, 0x2974, 0x2915, 0x28b5, 0x2856,
+  0x27f6, 0x2797, 0x2737, 0x26d8, 0x2678, 0x2618, 0x25b8, 0x2558,
+  0x24f7, 0x2497, 0x2437, 0x23d6, 0x2376, 0x2315, 0x22b4, 0x2254,
+  0x21f3, 0x2192, 0x2131, 0x20d0, 0x206e, 0x200d, 0x1fac, 0x1f4a,
+  0x1ee9, 0x1e87, 0x1e25, 0x1dc4, 0x1d62, 0x1d00, 0x1c9e, 0x1c3c,
+  0x1bda, 0x1b78, 0x1b16, 0x1ab3, 0x1a51, 0x19ef, 0x198c, 0x192a,
+  0x18c7, 0x1864, 0x1802, 0x179f, 0x173c, 0x16d9, 0x1676, 0x1613,
+  0x15b0, 0x154d, 0x14ea, 0x1487, 0x1423, 0x13c0, 0x135d, 0x12f9,
+  0x1296, 0x1232, 0x11cf, 0x116b, 0x1108, 0x10a4, 0x1040, 0xfdd,
+  0xf79, 0xf15, 0xeb1, 0xe4d, 0xde9, 0xd85, 0xd21, 0xcbd,
+  0xc59, 0xbf5, 0xb91, 0xb2d, 0xac9, 0xa65, 0xa00, 0x99c,
+  0x938, 0x8d4, 0x86f, 0x80b, 0x7a7, 0x742, 0x6de, 0x67a,
+  0x615, 0x5b1, 0x54c, 0x4e8, 0x483, 0x41f, 0x3ba, 0x356,
+  0x2f1, 0x28d, 0x228, 0x1c4, 0x15f, 0xfb, 0x96, 0x32,
+};
+
+static const q15_t cos_factorsQ15_2048[2048] = {
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd,
+  0x7ffd, 0x7ffd, 0x7ffc, 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa,
+  0x7ffa, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff6,
+  0x7ff5, 0x7ff5, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff1, 0x7ff0,
+  0x7ff0, 0x7fef, 0x7fee, 0x7fed, 0x7fec, 0x7fec, 0x7feb, 0x7fea,
+  0x7fe9, 0x7fe8, 0x7fe7, 0x7fe6, 0x7fe5, 0x7fe4, 0x7fe3, 0x7fe2,
+  0x7fe1, 0x7fe0, 0x7fdf, 0x7fdd, 0x7fdc, 0x7fdb, 0x7fda, 0x7fd9,
+  0x7fd7, 0x7fd6, 0x7fd5, 0x7fd4, 0x7fd2, 0x7fd1, 0x7fd0, 0x7fce,
+  0x7fcd, 0x7fcb, 0x7fca, 0x7fc9, 0x7fc7, 0x7fc6, 0x7fc4, 0x7fc3,
+  0x7fc1, 0x7fc0, 0x7fbe, 0x7fbc, 0x7fbb, 0x7fb9, 0x7fb7, 0x7fb6,
+  0x7fb4, 0x7fb2, 0x7fb1, 0x7faf, 0x7fad, 0x7fab, 0x7fa9, 0x7fa8,
+  0x7fa6, 0x7fa4, 0x7fa2, 0x7fa0, 0x7f9e, 0x7f9c, 0x7f9a, 0x7f98,
+  0x7f96, 0x7f94, 0x7f92, 0x7f90, 0x7f8e, 0x7f8c, 0x7f8a, 0x7f88,
+  0x7f86, 0x7f83, 0x7f81, 0x7f7f, 0x7f7d, 0x7f7b, 0x7f78, 0x7f76,
+  0x7f74, 0x7f71, 0x7f6f, 0x7f6d, 0x7f6a, 0x7f68, 0x7f65, 0x7f63,
+  0x7f60, 0x7f5e, 0x7f5b, 0x7f59, 0x7f56, 0x7f54, 0x7f51, 0x7f4f,
+  0x7f4c, 0x7f49, 0x7f47, 0x7f44, 0x7f41, 0x7f3f, 0x7f3c, 0x7f39,
+  0x7f36, 0x7f34, 0x7f31, 0x7f2e, 0x7f2b, 0x7f28, 0x7f25, 0x7f23,
+  0x7f20, 0x7f1d, 0x7f1a, 0x7f17, 0x7f14, 0x7f11, 0x7f0e, 0x7f0b,
+  0x7f08, 0x7f04, 0x7f01, 0x7efe, 0x7efb, 0x7ef8, 0x7ef5, 0x7ef1,
+  0x7eee, 0x7eeb, 0x7ee8, 0x7ee4, 0x7ee1, 0x7ede, 0x7eda, 0x7ed7,
+  0x7ed4, 0x7ed0, 0x7ecd, 0x7ec9, 0x7ec6, 0x7ec3, 0x7ebf, 0x7ebb,
+  0x7eb8, 0x7eb4, 0x7eb1, 0x7ead, 0x7eaa, 0x7ea6, 0x7ea2, 0x7e9f,
+  0x7e9b, 0x7e97, 0x7e94, 0x7e90, 0x7e8c, 0x7e88, 0x7e84, 0x7e81,
+  0x7e7d, 0x7e79, 0x7e75, 0x7e71, 0x7e6d, 0x7e69, 0x7e65, 0x7e61,
+  0x7e5d, 0x7e59, 0x7e55, 0x7e51, 0x7e4d, 0x7e49, 0x7e45, 0x7e41,
+  0x7e3d, 0x7e39, 0x7e34, 0x7e30, 0x7e2c, 0x7e28, 0x7e24, 0x7e1f,
+  0x7e1b, 0x7e17, 0x7e12, 0x7e0e, 0x7e0a, 0x7e05, 0x7e01, 0x7dfc,
+  0x7df8, 0x7df3, 0x7def, 0x7dea, 0x7de6, 0x7de1, 0x7ddd, 0x7dd8,
+  0x7dd4, 0x7dcf, 0x7dca, 0x7dc6, 0x7dc1, 0x7dbc, 0x7db8, 0x7db3,
+  0x7dae, 0x7da9, 0x7da5, 0x7da0, 0x7d9b, 0x7d96, 0x7d91, 0x7d8c,
+  0x7d87, 0x7d82, 0x7d7e, 0x7d79, 0x7d74, 0x7d6f, 0x7d6a, 0x7d65,
+  0x7d60, 0x7d5a, 0x7d55, 0x7d50, 0x7d4b, 0x7d46, 0x7d41, 0x7d3c,
+  0x7d36, 0x7d31, 0x7d2c, 0x7d27, 0x7d21, 0x7d1c, 0x7d17, 0x7d11,
+  0x7d0c, 0x7d07, 0x7d01, 0x7cfc, 0x7cf6, 0x7cf1, 0x7cec, 0x7ce6,
+  0x7ce1, 0x7cdb, 0x7cd5, 0x7cd0, 0x7cca, 0x7cc5, 0x7cbf, 0x7cb9,
+  0x7cb4, 0x7cae, 0x7ca8, 0x7ca3, 0x7c9d, 0x7c97, 0x7c91, 0x7c8c,
+  0x7c86, 0x7c80, 0x7c7a, 0x7c74, 0x7c6e, 0x7c69, 0x7c63, 0x7c5d,
+  0x7c57, 0x7c51, 0x7c4b, 0x7c45, 0x7c3f, 0x7c39, 0x7c33, 0x7c2d,
+  0x7c26, 0x7c20, 0x7c1a, 0x7c14, 0x7c0e, 0x7c08, 0x7c01, 0x7bfb,
+  0x7bf5, 0x7bef, 0x7be8, 0x7be2, 0x7bdc, 0x7bd5, 0x7bcf, 0x7bc9,
+  0x7bc2, 0x7bbc, 0x7bb5, 0x7baf, 0x7ba8, 0x7ba2, 0x7b9b, 0x7b95,
+  0x7b8e, 0x7b88, 0x7b81, 0x7b7a, 0x7b74, 0x7b6d, 0x7b67, 0x7b60,
+  0x7b59, 0x7b52, 0x7b4c, 0x7b45, 0x7b3e, 0x7b37, 0x7b31, 0x7b2a,
+  0x7b23, 0x7b1c, 0x7b15, 0x7b0e, 0x7b07, 0x7b00, 0x7af9, 0x7af2,
+  0x7aeb, 0x7ae4, 0x7add, 0x7ad6, 0x7acf, 0x7ac8, 0x7ac1, 0x7aba,
+  0x7ab3, 0x7aac, 0x7aa4, 0x7a9d, 0x7a96, 0x7a8f, 0x7a87, 0x7a80,
+  0x7a79, 0x7a72, 0x7a6a, 0x7a63, 0x7a5c, 0x7a54, 0x7a4d, 0x7a45,
+  0x7a3e, 0x7a36, 0x7a2f, 0x7a27, 0x7a20, 0x7a18, 0x7a11, 0x7a09,
+  0x7a02, 0x79fa, 0x79f2, 0x79eb, 0x79e3, 0x79db, 0x79d4, 0x79cc,
+  0x79c4, 0x79bc, 0x79b5, 0x79ad, 0x79a5, 0x799d, 0x7995, 0x798e,
+  0x7986, 0x797e, 0x7976, 0x796e, 0x7966, 0x795e, 0x7956, 0x794e,
+  0x7946, 0x793e, 0x7936, 0x792e, 0x7926, 0x791e, 0x7915, 0x790d,
+  0x7905, 0x78fd, 0x78f5, 0x78ec, 0x78e4, 0x78dc, 0x78d4, 0x78cb,
+  0x78c3, 0x78bb, 0x78b2, 0x78aa, 0x78a2, 0x7899, 0x7891, 0x7888,
+  0x7880, 0x7877, 0x786f, 0x7866, 0x785e, 0x7855, 0x784d, 0x7844,
+  0x783b, 0x7833, 0x782a, 0x7821, 0x7819, 0x7810, 0x7807, 0x77ff,
+  0x77f6, 0x77ed, 0x77e4, 0x77db, 0x77d3, 0x77ca, 0x77c1, 0x77b8,
+  0x77af, 0x77a6, 0x779d, 0x7794, 0x778b, 0x7782, 0x7779, 0x7770,
+  0x7767, 0x775e, 0x7755, 0x774c, 0x7743, 0x773a, 0x7731, 0x7727,
+  0x771e, 0x7715, 0x770c, 0x7703, 0x76f9, 0x76f0, 0x76e7, 0x76dd,
+  0x76d4, 0x76cb, 0x76c1, 0x76b8, 0x76af, 0x76a5, 0x769c, 0x7692,
+  0x7689, 0x767f, 0x7676, 0x766c, 0x7663, 0x7659, 0x7650, 0x7646,
+  0x763c, 0x7633, 0x7629, 0x761f, 0x7616, 0x760c, 0x7602, 0x75f9,
+  0x75ef, 0x75e5, 0x75db, 0x75d1, 0x75c8, 0x75be, 0x75b4, 0x75aa,
+  0x75a0, 0x7596, 0x758c, 0x7582, 0x7578, 0x756e, 0x7564, 0x755a,
+  0x7550, 0x7546, 0x753c, 0x7532, 0x7528, 0x751e, 0x7514, 0x7509,
+  0x74ff, 0x74f5, 0x74eb, 0x74e1, 0x74d6, 0x74cc, 0x74c2, 0x74b7,
+  0x74ad, 0x74a3, 0x7498, 0x748e, 0x7484, 0x7479, 0x746f, 0x7464,
+  0x745a, 0x744f, 0x7445, 0x743a, 0x7430, 0x7425, 0x741b, 0x7410,
+  0x7406, 0x73fb, 0x73f0, 0x73e6, 0x73db, 0x73d0, 0x73c6, 0x73bb,
+  0x73b0, 0x73a5, 0x739b, 0x7390, 0x7385, 0x737a, 0x736f, 0x7364,
+  0x7359, 0x734f, 0x7344, 0x7339, 0x732e, 0x7323, 0x7318, 0x730d,
+  0x7302, 0x72f7, 0x72ec, 0x72e1, 0x72d5, 0x72ca, 0x72bf, 0x72b4,
+  0x72a9, 0x729e, 0x7293, 0x7287, 0x727c, 0x7271, 0x7266, 0x725a,
+  0x724f, 0x7244, 0x7238, 0x722d, 0x7222, 0x7216, 0x720b, 0x71ff,
+  0x71f4, 0x71e9, 0x71dd, 0x71d2, 0x71c6, 0x71bb, 0x71af, 0x71a3,
+  0x7198, 0x718c, 0x7181, 0x7175, 0x7169, 0x715e, 0x7152, 0x7146,
+  0x713b, 0x712f, 0x7123, 0x7117, 0x710c, 0x7100, 0x70f4, 0x70e8,
+  0x70dc, 0x70d1, 0x70c5, 0x70b9, 0x70ad, 0x70a1, 0x7095, 0x7089,
+  0x707d, 0x7071, 0x7065, 0x7059, 0x704d, 0x7041, 0x7035, 0x7029,
+  0x701d, 0x7010, 0x7004, 0x6ff8, 0x6fec, 0x6fe0, 0x6fd3, 0x6fc7,
+  0x6fbb, 0x6faf, 0x6fa2, 0x6f96, 0x6f8a, 0x6f7d, 0x6f71, 0x6f65,
+  0x6f58, 0x6f4c, 0x6f3f, 0x6f33, 0x6f27, 0x6f1a, 0x6f0e, 0x6f01,
+  0x6ef5, 0x6ee8, 0x6edc, 0x6ecf, 0x6ec2, 0x6eb6, 0x6ea9, 0x6e9c,
+  0x6e90, 0x6e83, 0x6e76, 0x6e6a, 0x6e5d, 0x6e50, 0x6e44, 0x6e37,
+  0x6e2a, 0x6e1d, 0x6e10, 0x6e04, 0x6df7, 0x6dea, 0x6ddd, 0x6dd0,
+  0x6dc3, 0x6db6, 0x6da9, 0x6d9c, 0x6d8f, 0x6d82, 0x6d75, 0x6d68,
+  0x6d5b, 0x6d4e, 0x6d41, 0x6d34, 0x6d27, 0x6d1a, 0x6d0c, 0x6cff,
+  0x6cf2, 0x6ce5, 0x6cd8, 0x6cca, 0x6cbd, 0x6cb0, 0x6ca3, 0x6c95,
+  0x6c88, 0x6c7b, 0x6c6d, 0x6c60, 0x6c53, 0x6c45, 0x6c38, 0x6c2a,
+  0x6c1d, 0x6c0f, 0x6c02, 0x6bf5, 0x6be7, 0x6bd9, 0x6bcc, 0x6bbe,
+  0x6bb1, 0x6ba3, 0x6b96, 0x6b88, 0x6b7a, 0x6b6d, 0x6b5f, 0x6b51,
+  0x6b44, 0x6b36, 0x6b28, 0x6b1a, 0x6b0d, 0x6aff, 0x6af1, 0x6ae3,
+  0x6ad5, 0x6ac8, 0x6aba, 0x6aac, 0x6a9e, 0x6a90, 0x6a82, 0x6a74,
+  0x6a66, 0x6a58, 0x6a4a, 0x6a3c, 0x6a2e, 0x6a20, 0x6a12, 0x6a04,
+  0x69f6, 0x69e8, 0x69da, 0x69cb, 0x69bd, 0x69af, 0x69a1, 0x6993,
+  0x6985, 0x6976, 0x6968, 0x695a, 0x694b, 0x693d, 0x692f, 0x6921,
+  0x6912, 0x6904, 0x68f5, 0x68e7, 0x68d9, 0x68ca, 0x68bc, 0x68ad,
+  0x689f, 0x6890, 0x6882, 0x6873, 0x6865, 0x6856, 0x6848, 0x6839,
+  0x682b, 0x681c, 0x680d, 0x67ff, 0x67f0, 0x67e1, 0x67d3, 0x67c4,
+  0x67b5, 0x67a6, 0x6798, 0x6789, 0x677a, 0x676b, 0x675d, 0x674e,
+  0x673f, 0x6730, 0x6721, 0x6712, 0x6703, 0x66f4, 0x66e5, 0x66d6,
+  0x66c8, 0x66b9, 0x66aa, 0x669b, 0x668b, 0x667c, 0x666d, 0x665e,
+  0x664f, 0x6640, 0x6631, 0x6622, 0x6613, 0x6603, 0x65f4, 0x65e5,
+  0x65d6, 0x65c7, 0x65b7, 0x65a8, 0x6599, 0x658a, 0x657a, 0x656b,
+  0x655c, 0x654c, 0x653d, 0x652d, 0x651e, 0x650f, 0x64ff, 0x64f0,
+  0x64e0, 0x64d1, 0x64c1, 0x64b2, 0x64a2, 0x6493, 0x6483, 0x6474,
+  0x6464, 0x6454, 0x6445, 0x6435, 0x6426, 0x6416, 0x6406, 0x63f7,
+  0x63e7, 0x63d7, 0x63c7, 0x63b8, 0x63a8, 0x6398, 0x6388, 0x6378,
+  0x6369, 0x6359, 0x6349, 0x6339, 0x6329, 0x6319, 0x6309, 0x62f9,
+  0x62ea, 0x62da, 0x62ca, 0x62ba, 0x62aa, 0x629a, 0x628a, 0x627a,
+  0x6269, 0x6259, 0x6249, 0x6239, 0x6229, 0x6219, 0x6209, 0x61f9,
+  0x61e8, 0x61d8, 0x61c8, 0x61b8, 0x61a8, 0x6197, 0x6187, 0x6177,
+  0x6166, 0x6156, 0x6146, 0x6135, 0x6125, 0x6115, 0x6104, 0x60f4,
+  0x60e4, 0x60d3, 0x60c3, 0x60b2, 0x60a2, 0x6091, 0x6081, 0x6070,
+  0x6060, 0x604f, 0x603f, 0x602e, 0x601d, 0x600d, 0x5ffc, 0x5fec,
+  0x5fdb, 0x5fca, 0x5fba, 0x5fa9, 0x5f98, 0x5f87, 0x5f77, 0x5f66,
+  0x5f55, 0x5f44, 0x5f34, 0x5f23, 0x5f12, 0x5f01, 0x5ef0, 0x5edf,
+  0x5ecf, 0x5ebe, 0x5ead, 0x5e9c, 0x5e8b, 0x5e7a, 0x5e69, 0x5e58,
+  0x5e47, 0x5e36, 0x5e25, 0x5e14, 0x5e03, 0x5df2, 0x5de1, 0x5dd0,
+  0x5dbf, 0x5dad, 0x5d9c, 0x5d8b, 0x5d7a, 0x5d69, 0x5d58, 0x5d46,
+  0x5d35, 0x5d24, 0x5d13, 0x5d01, 0x5cf0, 0x5cdf, 0x5cce, 0x5cbc,
+  0x5cab, 0x5c9a, 0x5c88, 0x5c77, 0x5c66, 0x5c54, 0x5c43, 0x5c31,
+  0x5c20, 0x5c0e, 0x5bfd, 0x5beb, 0x5bda, 0x5bc8, 0x5bb7, 0x5ba5,
+  0x5b94, 0x5b82, 0x5b71, 0x5b5f, 0x5b4d, 0x5b3c, 0x5b2a, 0x5b19,
+  0x5b07, 0x5af5, 0x5ae4, 0x5ad2, 0x5ac0, 0x5aae, 0x5a9d, 0x5a8b,
+  0x5a79, 0x5a67, 0x5a56, 0x5a44, 0x5a32, 0x5a20, 0x5a0e, 0x59fc,
+  0x59ea, 0x59d9, 0x59c7, 0x59b5, 0x59a3, 0x5991, 0x597f, 0x596d,
+  0x595b, 0x5949, 0x5937, 0x5925, 0x5913, 0x5901, 0x58ef, 0x58dd,
+  0x58cb, 0x58b8, 0x58a6, 0x5894, 0x5882, 0x5870, 0x585e, 0x584b,
+  0x5839, 0x5827, 0x5815, 0x5803, 0x57f0, 0x57de, 0x57cc, 0x57b9,
+  0x57a7, 0x5795, 0x5783, 0x5770, 0x575e, 0x574b, 0x5739, 0x5727,
+  0x5714, 0x5702, 0x56ef, 0x56dd, 0x56ca, 0x56b8, 0x56a5, 0x5693,
+  0x5680, 0x566e, 0x565b, 0x5649, 0x5636, 0x5624, 0x5611, 0x55fe,
+  0x55ec, 0x55d9, 0x55c7, 0x55b4, 0x55a1, 0x558f, 0x557c, 0x5569,
+  0x5556, 0x5544, 0x5531, 0x551e, 0x550b, 0x54f9, 0x54e6, 0x54d3,
+  0x54c0, 0x54ad, 0x549a, 0x5488, 0x5475, 0x5462, 0x544f, 0x543c,
+  0x5429, 0x5416, 0x5403, 0x53f0, 0x53dd, 0x53ca, 0x53b7, 0x53a4,
+  0x5391, 0x537e, 0x536b, 0x5358, 0x5345, 0x5332, 0x531f, 0x530c,
+  0x52f8, 0x52e5, 0x52d2, 0x52bf, 0x52ac, 0x5299, 0x5285, 0x5272,
+  0x525f, 0x524c, 0x5238, 0x5225, 0x5212, 0x51ff, 0x51eb, 0x51d8,
+  0x51c5, 0x51b1, 0x519e, 0x518b, 0x5177, 0x5164, 0x5150, 0x513d,
+  0x512a, 0x5116, 0x5103, 0x50ef, 0x50dc, 0x50c8, 0x50b5, 0x50a1,
+  0x508e, 0x507a, 0x5067, 0x5053, 0x503f, 0x502c, 0x5018, 0x5005,
+  0x4ff1, 0x4fdd, 0x4fca, 0x4fb6, 0x4fa2, 0x4f8f, 0x4f7b, 0x4f67,
+  0x4f54, 0x4f40, 0x4f2c, 0x4f18, 0x4f05, 0x4ef1, 0x4edd, 0x4ec9,
+  0x4eb6, 0x4ea2, 0x4e8e, 0x4e7a, 0x4e66, 0x4e52, 0x4e3e, 0x4e2a,
+  0x4e17, 0x4e03, 0x4def, 0x4ddb, 0x4dc7, 0x4db3, 0x4d9f, 0x4d8b,
+  0x4d77, 0x4d63, 0x4d4f, 0x4d3b, 0x4d27, 0x4d13, 0x4cff, 0x4ceb,
+  0x4cd6, 0x4cc2, 0x4cae, 0x4c9a, 0x4c86, 0x4c72, 0x4c5e, 0x4c49,
+  0x4c35, 0x4c21, 0x4c0d, 0x4bf9, 0x4be4, 0x4bd0, 0x4bbc, 0x4ba8,
+  0x4b93, 0x4b7f, 0x4b6b, 0x4b56, 0x4b42, 0x4b2e, 0x4b19, 0x4b05,
+  0x4af1, 0x4adc, 0x4ac8, 0x4ab4, 0x4a9f, 0x4a8b, 0x4a76, 0x4a62,
+  0x4a4d, 0x4a39, 0x4a24, 0x4a10, 0x49fb, 0x49e7, 0x49d2, 0x49be,
+  0x49a9, 0x4995, 0x4980, 0x496c, 0x4957, 0x4942, 0x492e, 0x4919,
+  0x4905, 0x48f0, 0x48db, 0x48c7, 0x48b2, 0x489d, 0x4888, 0x4874,
+  0x485f, 0x484a, 0x4836, 0x4821, 0x480c, 0x47f7, 0x47e2, 0x47ce,
+  0x47b9, 0x47a4, 0x478f, 0x477a, 0x4765, 0x4751, 0x473c, 0x4727,
+  0x4712, 0x46fd, 0x46e8, 0x46d3, 0x46be, 0x46a9, 0x4694, 0x467f,
+  0x466a, 0x4655, 0x4640, 0x462b, 0x4616, 0x4601, 0x45ec, 0x45d7,
+  0x45c2, 0x45ad, 0x4598, 0x4583, 0x456e, 0x4559, 0x4544, 0x452e,
+  0x4519, 0x4504, 0x44ef, 0x44da, 0x44c5, 0x44af, 0x449a, 0x4485,
+  0x4470, 0x445a, 0x4445, 0x4430, 0x441b, 0x4405, 0x43f0, 0x43db,
+  0x43c5, 0x43b0, 0x439b, 0x4385, 0x4370, 0x435b, 0x4345, 0x4330,
+  0x431b, 0x4305, 0x42f0, 0x42da, 0x42c5, 0x42af, 0x429a, 0x4284,
+  0x426f, 0x425a, 0x4244, 0x422f, 0x4219, 0x4203, 0x41ee, 0x41d8,
+  0x41c3, 0x41ad, 0x4198, 0x4182, 0x416d, 0x4157, 0x4141, 0x412c,
+  0x4116, 0x4100, 0x40eb, 0x40d5, 0x40bf, 0x40aa, 0x4094, 0x407e,
+  0x4069, 0x4053, 0x403d, 0x4027, 0x4012, 0x3ffc, 0x3fe6, 0x3fd0,
+  0x3fbb, 0x3fa5, 0x3f8f, 0x3f79, 0x3f63, 0x3f4d, 0x3f38, 0x3f22,
+  0x3f0c, 0x3ef6, 0x3ee0, 0x3eca, 0x3eb4, 0x3e9e, 0x3e88, 0x3e73,
+  0x3e5d, 0x3e47, 0x3e31, 0x3e1b, 0x3e05, 0x3def, 0x3dd9, 0x3dc3,
+  0x3dad, 0x3d97, 0x3d81, 0x3d6b, 0x3d55, 0x3d3e, 0x3d28, 0x3d12,
+  0x3cfc, 0x3ce6, 0x3cd0, 0x3cba, 0x3ca4, 0x3c8e, 0x3c77, 0x3c61,
+  0x3c4b, 0x3c35, 0x3c1f, 0x3c09, 0x3bf2, 0x3bdc, 0x3bc6, 0x3bb0,
+  0x3b99, 0x3b83, 0x3b6d, 0x3b57, 0x3b40, 0x3b2a, 0x3b14, 0x3afe,
+  0x3ae7, 0x3ad1, 0x3abb, 0x3aa4, 0x3a8e, 0x3a78, 0x3a61, 0x3a4b,
+  0x3a34, 0x3a1e, 0x3a08, 0x39f1, 0x39db, 0x39c4, 0x39ae, 0x3998,
+  0x3981, 0x396b, 0x3954, 0x393e, 0x3927, 0x3911, 0x38fa, 0x38e4,
+  0x38cd, 0x38b7, 0x38a0, 0x388a, 0x3873, 0x385d, 0x3846, 0x382f,
+  0x3819, 0x3802, 0x37ec, 0x37d5, 0x37be, 0x37a8, 0x3791, 0x377a,
+  0x3764, 0x374d, 0x3736, 0x3720, 0x3709, 0x36f2, 0x36dc, 0x36c5,
+  0x36ae, 0x3698, 0x3681, 0x366a, 0x3653, 0x363d, 0x3626, 0x360f,
+  0x35f8, 0x35e1, 0x35cb, 0x35b4, 0x359d, 0x3586, 0x356f, 0x3558,
+  0x3542, 0x352b, 0x3514, 0x34fd, 0x34e6, 0x34cf, 0x34b8, 0x34a1,
+  0x348b, 0x3474, 0x345d, 0x3446, 0x342f, 0x3418, 0x3401, 0x33ea,
+  0x33d3, 0x33bc, 0x33a5, 0x338e, 0x3377, 0x3360, 0x3349, 0x3332,
+  0x331b, 0x3304, 0x32ed, 0x32d6, 0x32bf, 0x32a8, 0x3290, 0x3279,
+  0x3262, 0x324b, 0x3234, 0x321d, 0x3206, 0x31ef, 0x31d8, 0x31c0,
+  0x31a9, 0x3192, 0x317b, 0x3164, 0x314c, 0x3135, 0x311e, 0x3107,
+  0x30f0, 0x30d8, 0x30c1, 0x30aa, 0x3093, 0x307b, 0x3064, 0x304d,
+  0x3036, 0x301e, 0x3007, 0x2ff0, 0x2fd8, 0x2fc1, 0x2faa, 0x2f92,
+  0x2f7b, 0x2f64, 0x2f4c, 0x2f35, 0x2f1e, 0x2f06, 0x2eef, 0x2ed8,
+  0x2ec0, 0x2ea9, 0x2e91, 0x2e7a, 0x2e63, 0x2e4b, 0x2e34, 0x2e1c,
+  0x2e05, 0x2ded, 0x2dd6, 0x2dbe, 0x2da7, 0x2d8f, 0x2d78, 0x2d60,
+  0x2d49, 0x2d31, 0x2d1a, 0x2d02, 0x2ceb, 0x2cd3, 0x2cbc, 0x2ca4,
+  0x2c8d, 0x2c75, 0x2c5e, 0x2c46, 0x2c2e, 0x2c17, 0x2bff, 0x2be8,
+  0x2bd0, 0x2bb8, 0x2ba1, 0x2b89, 0x2b71, 0x2b5a, 0x2b42, 0x2b2b,
+  0x2b13, 0x2afb, 0x2ae4, 0x2acc, 0x2ab4, 0x2a9c, 0x2a85, 0x2a6d,
+  0x2a55, 0x2a3e, 0x2a26, 0x2a0e, 0x29f6, 0x29df, 0x29c7, 0x29af,
+  0x2997, 0x2980, 0x2968, 0x2950, 0x2938, 0x2920, 0x2909, 0x28f1,
+  0x28d9, 0x28c1, 0x28a9, 0x2892, 0x287a, 0x2862, 0x284a, 0x2832,
+  0x281a, 0x2802, 0x27eb, 0x27d3, 0x27bb, 0x27a3, 0x278b, 0x2773,
+  0x275b, 0x2743, 0x272b, 0x2713, 0x26fb, 0x26e4, 0x26cc, 0x26b4,
+  0x269c, 0x2684, 0x266c, 0x2654, 0x263c, 0x2624, 0x260c, 0x25f4,
+  0x25dc, 0x25c4, 0x25ac, 0x2594, 0x257c, 0x2564, 0x254c, 0x2534,
+  0x251c, 0x2503, 0x24eb, 0x24d3, 0x24bb, 0x24a3, 0x248b, 0x2473,
+  0x245b, 0x2443, 0x242b, 0x2413, 0x23fa, 0x23e2, 0x23ca, 0x23b2,
+  0x239a, 0x2382, 0x236a, 0x2352, 0x2339, 0x2321, 0x2309, 0x22f1,
+  0x22d9, 0x22c0, 0x22a8, 0x2290, 0x2278, 0x2260, 0x2247, 0x222f,
+  0x2217, 0x21ff, 0x21e7, 0x21ce, 0x21b6, 0x219e, 0x2186, 0x216d,
+  0x2155, 0x213d, 0x2125, 0x210c, 0x20f4, 0x20dc, 0x20c3, 0x20ab,
+  0x2093, 0x207a, 0x2062, 0x204a, 0x2032, 0x2019, 0x2001, 0x1fe9,
+  0x1fd0, 0x1fb8, 0x1f9f, 0x1f87, 0x1f6f, 0x1f56, 0x1f3e, 0x1f26,
+  0x1f0d, 0x1ef5, 0x1edd, 0x1ec4, 0x1eac, 0x1e93, 0x1e7b, 0x1e62,
+  0x1e4a, 0x1e32, 0x1e19, 0x1e01, 0x1de8, 0x1dd0, 0x1db7, 0x1d9f,
+  0x1d87, 0x1d6e, 0x1d56, 0x1d3d, 0x1d25, 0x1d0c, 0x1cf4, 0x1cdb,
+  0x1cc3, 0x1caa, 0x1c92, 0x1c79, 0x1c61, 0x1c48, 0x1c30, 0x1c17,
+  0x1bff, 0x1be6, 0x1bce, 0x1bb5, 0x1b9d, 0x1b84, 0x1b6c, 0x1b53,
+  0x1b3a, 0x1b22, 0x1b09, 0x1af1, 0x1ad8, 0x1ac0, 0x1aa7, 0x1a8e,
+  0x1a76, 0x1a5d, 0x1a45, 0x1a2c, 0x1a13, 0x19fb, 0x19e2, 0x19ca,
+  0x19b1, 0x1998, 0x1980, 0x1967, 0x194e, 0x1936, 0x191d, 0x1905,
+  0x18ec, 0x18d3, 0x18bb, 0x18a2, 0x1889, 0x1871, 0x1858, 0x183f,
+  0x1827, 0x180e, 0x17f5, 0x17dd, 0x17c4, 0x17ab, 0x1792, 0x177a,
+  0x1761, 0x1748, 0x1730, 0x1717, 0x16fe, 0x16e5, 0x16cd, 0x16b4,
+  0x169b, 0x1682, 0x166a, 0x1651, 0x1638, 0x161f, 0x1607, 0x15ee,
+  0x15d5, 0x15bc, 0x15a4, 0x158b, 0x1572, 0x1559, 0x1541, 0x1528,
+  0x150f, 0x14f6, 0x14dd, 0x14c5, 0x14ac, 0x1493, 0x147a, 0x1461,
+  0x1449, 0x1430, 0x1417, 0x13fe, 0x13e5, 0x13cc, 0x13b4, 0x139b,
+  0x1382, 0x1369, 0x1350, 0x1337, 0x131f, 0x1306, 0x12ed, 0x12d4,
+  0x12bb, 0x12a2, 0x1289, 0x1271, 0x1258, 0x123f, 0x1226, 0x120d,
+  0x11f4, 0x11db, 0x11c2, 0x11a9, 0x1191, 0x1178, 0x115f, 0x1146,
+  0x112d, 0x1114, 0x10fb, 0x10e2, 0x10c9, 0x10b0, 0x1098, 0x107f,
+  0x1066, 0x104d, 0x1034, 0x101b, 0x1002, 0xfe9, 0xfd0, 0xfb7,
+  0xf9e, 0xf85, 0xf6c, 0xf53, 0xf3a, 0xf21, 0xf08, 0xef0,
+  0xed7, 0xebe, 0xea5, 0xe8c, 0xe73, 0xe5a, 0xe41, 0xe28,
+  0xe0f, 0xdf6, 0xddd, 0xdc4, 0xdab, 0xd92, 0xd79, 0xd60,
+  0xd47, 0xd2e, 0xd15, 0xcfc, 0xce3, 0xcca, 0xcb1, 0xc98,
+  0xc7f, 0xc66, 0xc4d, 0xc34, 0xc1b, 0xc02, 0xbe9, 0xbd0,
+  0xbb7, 0xb9e, 0xb85, 0xb6c, 0xb53, 0xb3a, 0xb20, 0xb07,
+  0xaee, 0xad5, 0xabc, 0xaa3, 0xa8a, 0xa71, 0xa58, 0xa3f,
+  0xa26, 0xa0d, 0x9f4, 0x9db, 0x9c2, 0x9a9, 0x990, 0x977,
+  0x95e, 0x944, 0x92b, 0x912, 0x8f9, 0x8e0, 0x8c7, 0x8ae,
+  0x895, 0x87c, 0x863, 0x84a, 0x831, 0x818, 0x7fe, 0x7e5,
+  0x7cc, 0x7b3, 0x79a, 0x781, 0x768, 0x74f, 0x736, 0x71d,
+  0x704, 0x6ea, 0x6d1, 0x6b8, 0x69f, 0x686, 0x66d, 0x654,
+  0x63b, 0x622, 0x609, 0x5ef, 0x5d6, 0x5bd, 0x5a4, 0x58b,
+  0x572, 0x559, 0x540, 0x527, 0x50d, 0x4f4, 0x4db, 0x4c2,
+  0x4a9, 0x490, 0x477, 0x45e, 0x445, 0x42b, 0x412, 0x3f9,
+  0x3e0, 0x3c7, 0x3ae, 0x395, 0x37c, 0x362, 0x349, 0x330,
+  0x317, 0x2fe, 0x2e5, 0x2cc, 0x2b3, 0x299, 0x280, 0x267,
+  0x24e, 0x235, 0x21c, 0x203, 0x1ea, 0x1d0, 0x1b7, 0x19e,
+  0x185, 0x16c, 0x153, 0x13a, 0x121, 0x107, 0xee, 0xd5,
+  0xbc, 0xa3, 0x8a, 0x71, 0x57, 0x3e, 0x25, 0xc,
+
+};
+
+/**   
+ * @brief  Initialization function for the Q15 DCT4/IDCT4.  
+ * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.  
+ * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.  
+ * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.  
+ * @param[in]     N          length of the DCT4.  
+ * @param[in]     Nby2       half of the length of the DCT4.  
+ * @param[in]     normalize  normalizing factor.  
+ * @return  	  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.  
+ * \par Normalizing factor:   
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.   
+ * Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes:   
+ * \image html dct4NormalizingQ15Table.gif   
+ */
+
+arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  q15_t *twiddlePtr[3] = { (q15_t *) WeightsQ15_128, (q15_t *) WeightsQ15_512,
+    (q15_t *) WeightsQ15_2048
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  q15_t *pCosFactor[3] =
+    { (q15_t *) cos_factorsQ15_128, (q15_t *) cos_factorsQ15_512,
+    (q15_t *) cos_factorsQ15_2048
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT */
+  arm_rfft_init_q15(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
new file mode 100644
index 0000000..62ac374
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
@@ -0,0 +1,2198 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_init_q31.c   
+*   
+* Description:	Initialization function of DCT-4 & IDCT4 Q31   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/*   
+* @brief  Weights Table   
+*/
+
+/**   
+* \par   
+* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
   
+* \par   
+* C command to generate the table   
+* 
   
+* for(i = 0; i< N; i++)   
+* {   
+*   weights[2*i]= cos(i*c);   
+*   weights[(2*i)+1]= -sin(i * c);   
+* } 
   
+* \par   
+* where N is the Number of weights to be calculated and c is pi/(2*N)   
+* \par   
+* Convert the output to q31 format by multiplying with 2^31 and saturated if required.   
+* \par   
+* In the tables below the real and imaginary values are placed alternatively, hence the   
+* array length is 2*N.   
+*/
+
+static const q31_t WeightsQ31_128[256] = {
+  0x7fffffff, 0x0, 0x7ffd885a, 0xfe6de2e0, 0x7ff62182, 0xfcdbd541, 0x7fe9cbc0,
+  0xfb49e6a3,
+  0x7fd8878e, 0xf9b82684, 0x7fc25596, 0xf826a462, 0x7fa736b4, 0xf6956fb7,
+  0x7f872bf3, 0xf50497fb,
+  0x7f62368f, 0xf3742ca2, 0x7f3857f6, 0xf1e43d1c, 0x7f0991c4, 0xf054d8d5,
+  0x7ed5e5c6, 0xeec60f31,
+  0x7e9d55fc, 0xed37ef91, 0x7e5fe493, 0xebaa894f, 0x7e1d93ea, 0xea1debbb,
+  0x7dd6668f, 0xe8922622,
+  0x7d8a5f40, 0xe70747c4, 0x7d3980ec, 0xe57d5fda, 0x7ce3ceb2, 0xe3f47d96,
+  0x7c894bde, 0xe26cb01b,
+  0x7c29fbee, 0xe0e60685, 0x7bc5e290, 0xdf608fe4, 0x7b5d039e, 0xdddc5b3b,
+  0x7aef6323, 0xdc597781,
+  0x7a7d055b, 0xdad7f3a2, 0x7a05eead, 0xd957de7a, 0x798a23b1, 0xd7d946d8,
+  0x7909a92d, 0xd65c3b7b,
+  0x78848414, 0xd4e0cb15, 0x77fab989, 0xd3670446, 0x776c4edb, 0xd1eef59e,
+  0x76d94989, 0xd078ad9e,
+  0x7641af3d, 0xcf043ab3, 0x75a585cf, 0xcd91ab39, 0x7504d345, 0xcc210d79,
+  0x745f9dd1, 0xcab26fa9,
+  0x73b5ebd1, 0xc945dfec, 0x7307c3d0, 0xc7db6c50, 0x72552c85, 0xc67322ce,
+  0x719e2cd2, 0xc50d1149,
+  0x70e2cbc6, 0xc3a94590, 0x7023109a, 0xc247cd5a, 0x6f5f02b2, 0xc0e8b648,
+  0x6e96a99d, 0xbf8c0de3,
+  0x6dca0d14, 0xbe31e19b, 0x6cf934fc, 0xbcda3ecb, 0x6c242960, 0xbb8532b0,
+  0x6b4af279, 0xba32ca71,
+  0x6a6d98a4, 0xb8e31319, 0x698c246c, 0xb796199b, 0x68a69e81, 0xb64beacd,
+  0x67bd0fbd, 0xb5049368,
+  0x66cf8120, 0xb3c0200c, 0x65ddfbd3, 0xb27e9d3c, 0x64e88926, 0xb140175b,
+  0x63ef3290, 0xb0049ab3,
+  0x62f201ac, 0xaecc336c, 0x61f1003f, 0xad96ed92, 0x60ec3830, 0xac64d510,
+  0x5fe3b38d, 0xab35f5b5,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5dc79d7c, 0xa8e21106, 0x5cb420e0, 0xa7bd22ac,
+  0x5b9d1154, 0xa69b9b68,
+  0x5a82799a, 0xa57d8666, 0x59646498, 0xa462eeac, 0x5842dd54, 0xa34bdf20,
+  0x571deefa, 0xa2386284,
+  0x55f5a4d2, 0xa1288376, 0x54ca0a4b, 0xa01c4c73, 0x539b2af0, 0x9f13c7d0,
+  0x5269126e, 0x9e0effc1,
+  0x5133cc94, 0x9d0dfe54, 0x4ffb654d, 0x9c10cd70, 0x4ebfe8a5, 0x9b1776da,
+  0x4d8162c4, 0x9a22042d,
+  0x4c3fdff4, 0x99307ee0, 0x4afb6c98, 0x9842f043, 0x49b41533, 0x9759617f,
+  0x4869e665, 0x9673db94,
+  0x471cece7, 0x9592675c, 0x45cd358f, 0x94b50d87, 0x447acd50, 0x93dbd6a0,
+  0x4325c135, 0x9306cb04,
+  0x41ce1e65, 0x9235f2ec, 0x4073f21d, 0x91695663, 0x3f1749b8, 0x90a0fd4e,
+  0x3db832a6, 0x8fdcef66,
+  0x3c56ba70, 0x8f1d343a, 0x3af2eeb7, 0x8e61d32e, 0x398cdd32, 0x8daad37b,
+  0x382493b0, 0x8cf83c30,
+  0x36ba2014, 0x8c4a142f, 0x354d9057, 0x8ba0622f, 0x33def287, 0x8afb2cbb,
+  0x326e54c7, 0x8a5a7a31,
+  0x30fbc54d, 0x89be50c3, 0x2f875262, 0x8926b677, 0x2e110a62, 0x8893b125,
+  0x2c98fbba, 0x88054677,
+  0x2b1f34eb, 0x877b7bec, 0x29a3c485, 0x86f656d3, 0x2826b928, 0x8675dc4f,
+  0x26a82186, 0x85fa1153,
+  0x25280c5e, 0x8582faa5, 0x23a6887f, 0x85109cdd, 0x2223a4c5, 0x84a2fc62,
+  0x209f701c, 0x843a1d70,
+  0x1f19f97b, 0x83d60412, 0x1d934fe5, 0x8376b422, 0x1c0b826a, 0x831c314e,
+  0x1a82a026, 0x82c67f14,
+  0x18f8b83c, 0x8275a0c0, 0x176dd9de, 0x82299971, 0x15e21445, 0x81e26c16,
+  0x145576b1, 0x81a01b6d,
+  0x12c8106f, 0x8162aa04, 0x1139f0cf, 0x812a1a3a, 0xfab272b, 0x80f66e3c,
+  0xe1bc2e4, 0x80c7a80a,
+  0xc8bd35e, 0x809dc971, 0xafb6805, 0x8078d40d, 0x96a9049, 0x8058c94c,
+  0x7d95b9e, 0x803daa6a,
+  0x647d97c, 0x80277872, 0x4b6195d, 0x80163440, 0x3242abf, 0x8009de7e,
+  0x1921d20, 0x800277a6,
+};
+
+static const q31_t WeightsQ31_512[1024] = {
+  0x7fffffff, 0x0, 0x7fffd886, 0xff9b781d, 0x7fff6216, 0xff36f078, 0x7ffe9cb2,
+  0xfed2694f,
+  0x7ffd885a, 0xfe6de2e0, 0x7ffc250f, 0xfe095d69, 0x7ffa72d1, 0xfda4d929,
+  0x7ff871a2, 0xfd40565c,
+  0x7ff62182, 0xfcdbd541, 0x7ff38274, 0xfc775616, 0x7ff09478, 0xfc12d91a,
+  0x7fed5791, 0xfbae5e89,
+  0x7fe9cbc0, 0xfb49e6a3, 0x7fe5f108, 0xfae571a4, 0x7fe1c76b, 0xfa80ffcb,
+  0x7fdd4eec, 0xfa1c9157,
+  0x7fd8878e, 0xf9b82684, 0x7fd37153, 0xf953bf91, 0x7fce0c3e, 0xf8ef5cbb,
+  0x7fc85854, 0xf88afe42,
+  0x7fc25596, 0xf826a462, 0x7fbc040a, 0xf7c24f59, 0x7fb563b3, 0xf75dff66,
+  0x7fae7495, 0xf6f9b4c6,
+  0x7fa736b4, 0xf6956fb7, 0x7f9faa15, 0xf6313077, 0x7f97cebd, 0xf5ccf743,
+  0x7f8fa4b0, 0xf568c45b,
+  0x7f872bf3, 0xf50497fb, 0x7f7e648c, 0xf4a07261, 0x7f754e80, 0xf43c53cb,
+  0x7f6be9d4, 0xf3d83c77,
+  0x7f62368f, 0xf3742ca2, 0x7f5834b7, 0xf310248a, 0x7f4de451, 0xf2ac246e,
+  0x7f434563, 0xf2482c8a,
+  0x7f3857f6, 0xf1e43d1c, 0x7f2d1c0e, 0xf1805662, 0x7f2191b4, 0xf11c789a,
+  0x7f15b8ee, 0xf0b8a401,
+  0x7f0991c4, 0xf054d8d5, 0x7efd1c3c, 0xeff11753, 0x7ef05860, 0xef8d5fb8,
+  0x7ee34636, 0xef29b243,
+  0x7ed5e5c6, 0xeec60f31, 0x7ec8371a, 0xee6276bf, 0x7eba3a39, 0xedfee92b,
+  0x7eabef2c, 0xed9b66b2,
+  0x7e9d55fc, 0xed37ef91, 0x7e8e6eb2, 0xecd48407, 0x7e7f3957, 0xec71244f,
+  0x7e6fb5f4, 0xec0dd0a8,
+  0x7e5fe493, 0xebaa894f, 0x7e4fc53e, 0xeb474e81, 0x7e3f57ff, 0xeae4207a,
+  0x7e2e9cdf, 0xea80ff7a,
+  0x7e1d93ea, 0xea1debbb, 0x7e0c3d29, 0xe9bae57d, 0x7dfa98a8, 0xe957ecfb,
+  0x7de8a670, 0xe8f50273,
+  0x7dd6668f, 0xe8922622, 0x7dc3d90d, 0xe82f5844, 0x7db0fdf8, 0xe7cc9917,
+  0x7d9dd55a, 0xe769e8d8,
+  0x7d8a5f40, 0xe70747c4, 0x7d769bb5, 0xe6a4b616, 0x7d628ac6, 0xe642340d,
+  0x7d4e2c7f, 0xe5dfc1e5,
+  0x7d3980ec, 0xe57d5fda, 0x7d24881b, 0xe51b0e2a, 0x7d0f4218, 0xe4b8cd11,
+  0x7cf9aef0, 0xe4569ccb,
+  0x7ce3ceb2, 0xe3f47d96, 0x7ccda169, 0xe3926fad, 0x7cb72724, 0xe330734d,
+  0x7ca05ff1, 0xe2ce88b3,
+  0x7c894bde, 0xe26cb01b, 0x7c71eaf9, 0xe20ae9c1, 0x7c5a3d50, 0xe1a935e2,
+  0x7c4242f2, 0xe14794ba,
+  0x7c29fbee, 0xe0e60685, 0x7c116853, 0xe0848b7f, 0x7bf88830, 0xe02323e5,
+  0x7bdf5b94, 0xdfc1cff3,
+  0x7bc5e290, 0xdf608fe4, 0x7bac1d31, 0xdeff63f4, 0x7b920b89, 0xde9e4c60,
+  0x7b77ada8, 0xde3d4964,
+  0x7b5d039e, 0xdddc5b3b, 0x7b420d7a, 0xdd7b8220, 0x7b26cb4f, 0xdd1abe51,
+  0x7b0b3d2c, 0xdcba1008,
+  0x7aef6323, 0xdc597781, 0x7ad33d45, 0xdbf8f4f8, 0x7ab6cba4, 0xdb9888a8,
+  0x7a9a0e50, 0xdb3832cd,
+  0x7a7d055b, 0xdad7f3a2, 0x7a5fb0d8, 0xda77cb63, 0x7a4210d8, 0xda17ba4a,
+  0x7a24256f, 0xd9b7c094,
+  0x7a05eead, 0xd957de7a, 0x79e76ca7, 0xd8f81439, 0x79c89f6e, 0xd898620c,
+  0x79a98715, 0xd838c82d,
+  0x798a23b1, 0xd7d946d8, 0x796a7554, 0xd779de47, 0x794a7c12, 0xd71a8eb5,
+  0x792a37fe, 0xd6bb585e,
+  0x7909a92d, 0xd65c3b7b, 0x78e8cfb2, 0xd5fd3848, 0x78c7aba2, 0xd59e4eff,
+  0x78a63d11, 0xd53f7fda,
+  0x78848414, 0xd4e0cb15, 0x786280bf, 0xd48230e9, 0x78403329, 0xd423b191,
+  0x781d9b65, 0xd3c54d47,
+  0x77fab989, 0xd3670446, 0x77d78daa, 0xd308d6c7, 0x77b417df, 0xd2aac504,
+  0x7790583e, 0xd24ccf39,
+  0x776c4edb, 0xd1eef59e, 0x7747fbce, 0xd191386e, 0x77235f2d, 0xd13397e2,
+  0x76fe790e, 0xd0d61434,
+  0x76d94989, 0xd078ad9e, 0x76b3d0b4, 0xd01b6459, 0x768e0ea6, 0xcfbe389f,
+  0x76680376, 0xcf612aaa,
+  0x7641af3d, 0xcf043ab3, 0x761b1211, 0xcea768f2, 0x75f42c0b, 0xce4ab5a2,
+  0x75ccfd42, 0xcdee20fc,
+  0x75a585cf, 0xcd91ab39, 0x757dc5ca, 0xcd355491, 0x7555bd4c, 0xccd91d3d,
+  0x752d6c6c, 0xcc7d0578,
+  0x7504d345, 0xcc210d79, 0x74dbf1ef, 0xcbc53579, 0x74b2c884, 0xcb697db0,
+  0x7489571c, 0xcb0de658,
+  0x745f9dd1, 0xcab26fa9, 0x74359cbd, 0xca5719db, 0x740b53fb, 0xc9fbe527,
+  0x73e0c3a3, 0xc9a0d1c5,
+  0x73b5ebd1, 0xc945dfec, 0x738acc9e, 0xc8eb0fd6, 0x735f6626, 0xc89061ba,
+  0x7333b883, 0xc835d5d0,
+  0x7307c3d0, 0xc7db6c50, 0x72db8828, 0xc7812572, 0x72af05a7, 0xc727016d,
+  0x72823c67, 0xc6cd0079,
+  0x72552c85, 0xc67322ce, 0x7227d61c, 0xc61968a2, 0x71fa3949, 0xc5bfd22e,
+  0x71cc5626, 0xc5665fa9,
+  0x719e2cd2, 0xc50d1149, 0x716fbd68, 0xc4b3e746, 0x71410805, 0xc45ae1d7,
+  0x71120cc5, 0xc4020133,
+  0x70e2cbc6, 0xc3a94590, 0x70b34525, 0xc350af26, 0x708378ff, 0xc2f83e2a,
+  0x70536771, 0xc29ff2d4,
+  0x7023109a, 0xc247cd5a, 0x6ff27497, 0xc1efcdf3, 0x6fc19385, 0xc197f4d4,
+  0x6f906d84, 0xc1404233,
+  0x6f5f02b2, 0xc0e8b648, 0x6f2d532c, 0xc0915148, 0x6efb5f12, 0xc03a1368,
+  0x6ec92683, 0xbfe2fcdf,
+  0x6e96a99d, 0xbf8c0de3, 0x6e63e87f, 0xbf3546a8, 0x6e30e34a, 0xbedea765,
+  0x6dfd9a1c, 0xbe88304f,
+  0x6dca0d14, 0xbe31e19b, 0x6d963c54, 0xbddbbb7f, 0x6d6227fa, 0xbd85be30,
+  0x6d2dd027, 0xbd2fe9e2,
+  0x6cf934fc, 0xbcda3ecb, 0x6cc45698, 0xbc84bd1f, 0x6c8f351c, 0xbc2f6513,
+  0x6c59d0a9, 0xbbda36dd,
+  0x6c242960, 0xbb8532b0, 0x6bee3f62, 0xbb3058c0, 0x6bb812d1, 0xbadba943,
+  0x6b81a3cd, 0xba87246d,
+  0x6b4af279, 0xba32ca71, 0x6b13fef5, 0xb9de9b83, 0x6adcc964, 0xb98a97d8,
+  0x6aa551e9, 0xb936bfa4,
+  0x6a6d98a4, 0xb8e31319, 0x6a359db9, 0xb88f926d, 0x69fd614a, 0xb83c3dd1,
+  0x69c4e37a, 0xb7e9157a,
+  0x698c246c, 0xb796199b, 0x69532442, 0xb7434a67, 0x6919e320, 0xb6f0a812,
+  0x68e06129, 0xb69e32cd,
+  0x68a69e81, 0xb64beacd, 0x686c9b4b, 0xb5f9d043, 0x683257ab, 0xb5a7e362,
+  0x67f7d3c5, 0xb556245e,
+  0x67bd0fbd, 0xb5049368, 0x67820bb7, 0xb4b330b3, 0x6746c7d8, 0xb461fc70,
+  0x670b4444, 0xb410f6d3,
+  0x66cf8120, 0xb3c0200c, 0x66937e91, 0xb36f784f, 0x66573cbb, 0xb31effcc,
+  0x661abbc5, 0xb2ceb6b5,
+  0x65ddfbd3, 0xb27e9d3c, 0x65a0fd0b, 0xb22eb392, 0x6563bf92, 0xb1def9e9,
+  0x6526438f, 0xb18f7071,
+  0x64e88926, 0xb140175b, 0x64aa907f, 0xb0f0eeda, 0x646c59bf, 0xb0a1f71d,
+  0x642de50d, 0xb0533055,
+  0x63ef3290, 0xb0049ab3, 0x63b0426d, 0xafb63667, 0x637114cc, 0xaf6803a2,
+  0x6331a9d4, 0xaf1a0293,
+  0x62f201ac, 0xaecc336c, 0x62b21c7b, 0xae7e965b, 0x6271fa69, 0xae312b92,
+  0x62319b9d, 0xade3f33e,
+  0x61f1003f, 0xad96ed92, 0x61b02876, 0xad4a1aba, 0x616f146c, 0xacfd7ae8,
+  0x612dc447, 0xacb10e4b,
+  0x60ec3830, 0xac64d510, 0x60aa7050, 0xac18cf69, 0x60686ccf, 0xabccfd83,
+  0x60262dd6, 0xab815f8d,
+  0x5fe3b38d, 0xab35f5b5, 0x5fa0fe1f, 0xaaeac02c, 0x5f5e0db3, 0xaa9fbf1e,
+  0x5f1ae274, 0xaa54f2ba,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5e93dc1f, 0xa9bff8a8, 0x5e50015d, 0xa975cb57,
+  0x5e0bec6e, 0xa92bd367,
+  0x5dc79d7c, 0xa8e21106, 0x5d8314b1, 0xa8988463, 0x5d3e5237, 0xa84f2daa,
+  0x5cf95638, 0xa8060d08,
+  0x5cb420e0, 0xa7bd22ac, 0x5c6eb258, 0xa7746ec0, 0x5c290acc, 0xa72bf174,
+  0x5be32a67, 0xa6e3aaf2,
+  0x5b9d1154, 0xa69b9b68, 0x5b56bfbd, 0xa653c303, 0x5b1035cf, 0xa60c21ee,
+  0x5ac973b5, 0xa5c4b855,
+  0x5a82799a, 0xa57d8666, 0x5a3b47ab, 0xa5368c4b, 0x59f3de12, 0xa4efca31,
+  0x59ac3cfd, 0xa4a94043,
+  0x59646498, 0xa462eeac, 0x591c550e, 0xa41cd599, 0x58d40e8c, 0xa3d6f534,
+  0x588b9140, 0xa3914da8,
+  0x5842dd54, 0xa34bdf20, 0x57f9f2f8, 0xa306a9c8, 0x57b0d256, 0xa2c1adc9,
+  0x57677b9d, 0xa27ceb4f,
+  0x571deefa, 0xa2386284, 0x56d42c99, 0xa1f41392, 0x568a34a9, 0xa1affea3,
+  0x56400758, 0xa16c23e1,
+  0x55f5a4d2, 0xa1288376, 0x55ab0d46, 0xa0e51d8c, 0x556040e2, 0xa0a1f24d,
+  0x55153fd4, 0xa05f01e1,
+  0x54ca0a4b, 0xa01c4c73, 0x547ea073, 0x9fd9d22a, 0x5433027d, 0x9f979331,
+  0x53e73097, 0x9f558fb0,
+  0x539b2af0, 0x9f13c7d0, 0x534ef1b5, 0x9ed23bb9, 0x53028518, 0x9e90eb94,
+  0x52b5e546, 0x9e4fd78a,
+  0x5269126e, 0x9e0effc1, 0x521c0cc2, 0x9dce6463, 0x51ced46e, 0x9d8e0597,
+  0x518169a5, 0x9d4de385,
+  0x5133cc94, 0x9d0dfe54, 0x50e5fd6d, 0x9cce562c, 0x5097fc5e, 0x9c8eeb34,
+  0x5049c999, 0x9c4fbd93,
+  0x4ffb654d, 0x9c10cd70, 0x4faccfab, 0x9bd21af3, 0x4f5e08e3, 0x9b93a641,
+  0x4f0f1126, 0x9b556f81,
+  0x4ebfe8a5, 0x9b1776da, 0x4e708f8f, 0x9ad9bc71, 0x4e210617, 0x9a9c406e,
+  0x4dd14c6e, 0x9a5f02f5,
+  0x4d8162c4, 0x9a22042d, 0x4d31494b, 0x99e5443b, 0x4ce10034, 0x99a8c345,
+  0x4c9087b1, 0x996c816f,
+  0x4c3fdff4, 0x99307ee0, 0x4bef092d, 0x98f4bbbc, 0x4b9e0390, 0x98b93828,
+  0x4b4ccf4d, 0x987df449,
+  0x4afb6c98, 0x9842f043, 0x4aa9dba2, 0x98082c3b, 0x4a581c9e, 0x97cda855,
+  0x4a062fbd, 0x979364b5,
+  0x49b41533, 0x9759617f, 0x4961cd33, 0x971f9ed7, 0x490f57ee, 0x96e61ce0,
+  0x48bcb599, 0x96acdbbe,
+  0x4869e665, 0x9673db94, 0x4816ea86, 0x963b1c86, 0x47c3c22f, 0x96029eb6,
+  0x47706d93, 0x95ca6247,
+  0x471cece7, 0x9592675c, 0x46c9405c, 0x955aae17, 0x46756828, 0x9523369c,
+  0x4621647d, 0x94ec010b,
+  0x45cd358f, 0x94b50d87, 0x4578db93, 0x947e5c33, 0x452456bd, 0x9447ed2f,
+  0x44cfa740, 0x9411c09e,
+  0x447acd50, 0x93dbd6a0, 0x4425c923, 0x93a62f57, 0x43d09aed, 0x9370cae4,
+  0x437b42e1, 0x933ba968,
+  0x4325c135, 0x9306cb04, 0x42d0161e, 0x92d22fd9, 0x427a41d0, 0x929dd806,
+  0x42244481, 0x9269c3ac,
+  0x41ce1e65, 0x9235f2ec, 0x4177cfb1, 0x920265e4, 0x4121589b, 0x91cf1cb6,
+  0x40cab958, 0x919c1781,
+  0x4073f21d, 0x91695663, 0x401d0321, 0x9136d97d, 0x3fc5ec98, 0x9104a0ee,
+  0x3f6eaeb8, 0x90d2acd4,
+  0x3f1749b8, 0x90a0fd4e, 0x3ebfbdcd, 0x906f927c, 0x3e680b2c, 0x903e6c7b,
+  0x3e10320d, 0x900d8b69,
+  0x3db832a6, 0x8fdcef66, 0x3d600d2c, 0x8fac988f, 0x3d07c1d6, 0x8f7c8701,
+  0x3caf50da, 0x8f4cbadb,
+  0x3c56ba70, 0x8f1d343a, 0x3bfdfecd, 0x8eedf33b, 0x3ba51e29, 0x8ebef7fb,
+  0x3b4c18ba, 0x8e904298,
+  0x3af2eeb7, 0x8e61d32e, 0x3a99a057, 0x8e33a9da, 0x3a402dd2, 0x8e05c6b7,
+  0x39e6975e, 0x8dd829e4,
+  0x398cdd32, 0x8daad37b, 0x3932ff87, 0x8d7dc399, 0x38d8fe93, 0x8d50fa59,
+  0x387eda8e, 0x8d2477d8,
+  0x382493b0, 0x8cf83c30, 0x37ca2a30, 0x8ccc477d, 0x376f9e46, 0x8ca099da,
+  0x3714f02a, 0x8c753362,
+  0x36ba2014, 0x8c4a142f, 0x365f2e3b, 0x8c1f3c5d, 0x36041ad9, 0x8bf4ac05,
+  0x35a8e625, 0x8bca6343,
+  0x354d9057, 0x8ba0622f, 0x34f219a8, 0x8b76a8e4, 0x34968250, 0x8b4d377c,
+  0x343aca87, 0x8b240e11,
+  0x33def287, 0x8afb2cbb, 0x3382fa88, 0x8ad29394, 0x3326e2c3, 0x8aaa42b4,
+  0x32caab6f, 0x8a823a36,
+  0x326e54c7, 0x8a5a7a31, 0x3211df04, 0x8a3302be, 0x31b54a5e, 0x8a0bd3f5,
+  0x3158970e, 0x89e4edef,
+  0x30fbc54d, 0x89be50c3, 0x309ed556, 0x8997fc8a, 0x3041c761, 0x8971f15a,
+  0x2fe49ba7, 0x894c2f4c,
+  0x2f875262, 0x8926b677, 0x2f29ebcc, 0x890186f2, 0x2ecc681e, 0x88dca0d3,
+  0x2e6ec792, 0x88b80432,
+  0x2e110a62, 0x8893b125, 0x2db330c7, 0x886fa7c2, 0x2d553afc, 0x884be821,
+  0x2cf72939, 0x88287256,
+  0x2c98fbba, 0x88054677, 0x2c3ab2b9, 0x87e2649b, 0x2bdc4e6f, 0x87bfccd7,
+  0x2b7dcf17, 0x879d7f41,
+  0x2b1f34eb, 0x877b7bec, 0x2ac08026, 0x8759c2ef, 0x2a61b101, 0x8738545e,
+  0x2a02c7b8, 0x8717304e,
+  0x29a3c485, 0x86f656d3, 0x2944a7a2, 0x86d5c802, 0x28e5714b, 0x86b583ee,
+  0x288621b9, 0x86958aac,
+  0x2826b928, 0x8675dc4f, 0x27c737d3, 0x865678eb, 0x27679df4, 0x86376092,
+  0x2707ebc7, 0x86189359,
+  0x26a82186, 0x85fa1153, 0x26483f6c, 0x85dbda91, 0x25e845b6, 0x85bdef28,
+  0x2588349d, 0x85a04f28,
+  0x25280c5e, 0x8582faa5, 0x24c7cd33, 0x8565f1b0, 0x24677758, 0x8549345c,
+  0x24070b08, 0x852cc2bb,
+  0x23a6887f, 0x85109cdd, 0x2345eff8, 0x84f4c2d4, 0x22e541af, 0x84d934b1,
+  0x22847de0, 0x84bdf286,
+  0x2223a4c5, 0x84a2fc62, 0x21c2b69c, 0x84885258, 0x2161b3a0, 0x846df477,
+  0x21009c0c, 0x8453e2cf,
+  0x209f701c, 0x843a1d70, 0x203e300d, 0x8420a46c, 0x1fdcdc1b, 0x840777d0,
+  0x1f7b7481, 0x83ee97ad,
+  0x1f19f97b, 0x83d60412, 0x1eb86b46, 0x83bdbd0e, 0x1e56ca1e, 0x83a5c2b0,
+  0x1df5163f, 0x838e1507,
+  0x1d934fe5, 0x8376b422, 0x1d31774d, 0x835fa00f, 0x1ccf8cb3, 0x8348d8dc,
+  0x1c6d9053, 0x83325e97,
+  0x1c0b826a, 0x831c314e, 0x1ba96335, 0x83065110, 0x1b4732ef, 0x82f0bde8,
+  0x1ae4f1d6, 0x82db77e5,
+  0x1a82a026, 0x82c67f14, 0x1a203e1b, 0x82b1d381, 0x19bdcbf3, 0x829d753a,
+  0x195b49ea, 0x8289644b,
+  0x18f8b83c, 0x8275a0c0, 0x18961728, 0x82622aa6, 0x183366e9, 0x824f0208,
+  0x17d0a7bc, 0x823c26f3,
+  0x176dd9de, 0x82299971, 0x170afd8d, 0x82175990, 0x16a81305, 0x82056758,
+  0x16451a83, 0x81f3c2d7,
+  0x15e21445, 0x81e26c16, 0x157f0086, 0x81d16321, 0x151bdf86, 0x81c0a801,
+  0x14b8b17f, 0x81b03ac2,
+  0x145576b1, 0x81a01b6d, 0x13f22f58, 0x81904a0c, 0x138edbb1, 0x8180c6a9,
+  0x132b7bf9, 0x8171914e,
+  0x12c8106f, 0x8162aa04, 0x1264994e, 0x815410d4, 0x120116d5, 0x8145c5c7,
+  0x119d8941, 0x8137c8e6,
+  0x1139f0cf, 0x812a1a3a, 0x10d64dbd, 0x811cb9ca, 0x1072a048, 0x810fa7a0,
+  0x100ee8ad, 0x8102e3c4,
+  0xfab272b, 0x80f66e3c, 0xf475bff, 0x80ea4712, 0xee38766, 0x80de6e4c,
+  0xe7fa99e, 0x80d2e3f2,
+  0xe1bc2e4, 0x80c7a80a, 0xdb7d376, 0x80bcba9d, 0xd53db92, 0x80b21baf,
+  0xcefdb76, 0x80a7cb49,
+  0xc8bd35e, 0x809dc971, 0xc27c389, 0x8094162c, 0xbc3ac35, 0x808ab180,
+  0xb5f8d9f, 0x80819b74,
+  0xafb6805, 0x8078d40d, 0xa973ba5, 0x80705b50, 0xa3308bd, 0x80683143,
+  0x9cecf89, 0x806055eb,
+  0x96a9049, 0x8058c94c, 0x9064b3a, 0x80518b6b, 0x8a2009a, 0x804a9c4d,
+  0x83db0a7, 0x8043fbf6,
+  0x7d95b9e, 0x803daa6a, 0x77501be, 0x8037a7ac, 0x710a345, 0x8031f3c2,
+  0x6ac406f, 0x802c8ead,
+  0x647d97c, 0x80277872, 0x5e36ea9, 0x8022b114, 0x57f0035, 0x801e3895,
+  0x51a8e5c, 0x801a0ef8,
+  0x4b6195d, 0x80163440, 0x451a177, 0x8012a86f, 0x3ed26e6, 0x800f6b88,
+  0x388a9ea, 0x800c7d8c,
+  0x3242abf, 0x8009de7e, 0x2bfa9a4, 0x80078e5e, 0x25b26d7, 0x80058d2f,
+  0x1f6a297, 0x8003daf1,
+  0x1921d20, 0x800277a6, 0x12d96b1, 0x8001634e, 0xc90f88, 0x80009dea,
+  0x6487e3, 0x8000277a,
+};
+
+static const q31_t WeightsQ31_2048[4096] = {
+  0x7fffffff, 0x0, 0x7ffffd88, 0xffe6de05, 0x7ffff621, 0xffcdbc0b, 0x7fffe9cb,
+  0xffb49a12,
+  0x7fffd886, 0xff9b781d, 0x7fffc251, 0xff82562c, 0x7fffa72c, 0xff69343f,
+  0x7fff8719, 0xff501258,
+  0x7fff6216, 0xff36f078, 0x7fff3824, 0xff1dcea0, 0x7fff0943, 0xff04acd0,
+  0x7ffed572, 0xfeeb8b0a,
+  0x7ffe9cb2, 0xfed2694f, 0x7ffe5f03, 0xfeb947a0, 0x7ffe1c65, 0xfea025fd,
+  0x7ffdd4d7, 0xfe870467,
+  0x7ffd885a, 0xfe6de2e0, 0x7ffd36ee, 0xfe54c169, 0x7ffce093, 0xfe3ba002,
+  0x7ffc8549, 0xfe227eac,
+  0x7ffc250f, 0xfe095d69, 0x7ffbbfe6, 0xfdf03c3a, 0x7ffb55ce, 0xfdd71b1e,
+  0x7ffae6c7, 0xfdbdfa18,
+  0x7ffa72d1, 0xfda4d929, 0x7ff9f9ec, 0xfd8bb850, 0x7ff97c18, 0xfd729790,
+  0x7ff8f954, 0xfd5976e9,
+  0x7ff871a2, 0xfd40565c, 0x7ff7e500, 0xfd2735ea, 0x7ff75370, 0xfd0e1594,
+  0x7ff6bcf0, 0xfcf4f55c,
+  0x7ff62182, 0xfcdbd541, 0x7ff58125, 0xfcc2b545, 0x7ff4dbd9, 0xfca9956a,
+  0x7ff4319d, 0xfc9075af,
+  0x7ff38274, 0xfc775616, 0x7ff2ce5b, 0xfc5e36a0, 0x7ff21553, 0xfc45174e,
+  0x7ff1575d, 0xfc2bf821,
+  0x7ff09478, 0xfc12d91a, 0x7fefcca4, 0xfbf9ba39, 0x7feeffe1, 0xfbe09b80,
+  0x7fee2e30, 0xfbc77cf0,
+  0x7fed5791, 0xfbae5e89, 0x7fec7c02, 0xfb95404d, 0x7feb9b85, 0xfb7c223d,
+  0x7feab61a, 0xfb630459,
+  0x7fe9cbc0, 0xfb49e6a3, 0x7fe8dc78, 0xfb30c91b, 0x7fe7e841, 0xfb17abc2,
+  0x7fe6ef1c, 0xfafe8e9b,
+  0x7fe5f108, 0xfae571a4, 0x7fe4ee06, 0xfacc54e0, 0x7fe3e616, 0xfab3384f,
+  0x7fe2d938, 0xfa9a1bf3,
+  0x7fe1c76b, 0xfa80ffcb, 0x7fe0b0b1, 0xfa67e3da, 0x7fdf9508, 0xfa4ec821,
+  0x7fde7471, 0xfa35ac9f,
+  0x7fdd4eec, 0xfa1c9157, 0x7fdc247a, 0xfa037648, 0x7fdaf519, 0xf9ea5b75,
+  0x7fd9c0ca, 0xf9d140de,
+  0x7fd8878e, 0xf9b82684, 0x7fd74964, 0xf99f0c68, 0x7fd6064c, 0xf985f28a,
+  0x7fd4be46, 0xf96cd8ed,
+  0x7fd37153, 0xf953bf91, 0x7fd21f72, 0xf93aa676, 0x7fd0c8a3, 0xf9218d9e,
+  0x7fcf6ce8, 0xf908750a,
+  0x7fce0c3e, 0xf8ef5cbb, 0x7fcca6a7, 0xf8d644b2, 0x7fcb3c23, 0xf8bd2cef,
+  0x7fc9ccb2, 0xf8a41574,
+  0x7fc85854, 0xf88afe42, 0x7fc6df08, 0xf871e759, 0x7fc560cf, 0xf858d0bb,
+  0x7fc3dda9, 0xf83fba68,
+  0x7fc25596, 0xf826a462, 0x7fc0c896, 0xf80d8ea9, 0x7fbf36aa, 0xf7f4793e,
+  0x7fbd9fd0, 0xf7db6423,
+  0x7fbc040a, 0xf7c24f59, 0x7fba6357, 0xf7a93ae0, 0x7fb8bdb8, 0xf79026b9,
+  0x7fb7132b, 0xf77712e5,
+  0x7fb563b3, 0xf75dff66, 0x7fb3af4e, 0xf744ec3b, 0x7fb1f5fc, 0xf72bd967,
+  0x7fb037bf, 0xf712c6ea,
+  0x7fae7495, 0xf6f9b4c6, 0x7facac7f, 0xf6e0a2fa, 0x7faadf7c, 0xf6c79188,
+  0x7fa90d8e, 0xf6ae8071,
+  0x7fa736b4, 0xf6956fb7, 0x7fa55aee, 0xf67c5f59, 0x7fa37a3c, 0xf6634f59,
+  0x7fa1949e, 0xf64a3fb8,
+  0x7f9faa15, 0xf6313077, 0x7f9dbaa0, 0xf6182196, 0x7f9bc640, 0xf5ff1318,
+  0x7f99ccf4, 0xf5e604fc,
+  0x7f97cebd, 0xf5ccf743, 0x7f95cb9a, 0xf5b3e9f0, 0x7f93c38c, 0xf59add02,
+  0x7f91b694, 0xf581d07b,
+  0x7f8fa4b0, 0xf568c45b, 0x7f8d8de1, 0xf54fb8a4, 0x7f8b7227, 0xf536ad56,
+  0x7f895182, 0xf51da273,
+  0x7f872bf3, 0xf50497fb, 0x7f850179, 0xf4eb8def, 0x7f82d214, 0xf4d28451,
+  0x7f809dc5, 0xf4b97b21,
+  0x7f7e648c, 0xf4a07261, 0x7f7c2668, 0xf4876a10, 0x7f79e35a, 0xf46e6231,
+  0x7f779b62, 0xf4555ac5,
+  0x7f754e80, 0xf43c53cb, 0x7f72fcb4, 0xf4234d45, 0x7f70a5fe, 0xf40a4735,
+  0x7f6e4a5e, 0xf3f1419a,
+  0x7f6be9d4, 0xf3d83c77, 0x7f698461, 0xf3bf37cb, 0x7f671a05, 0xf3a63398,
+  0x7f64aabf, 0xf38d2fe0,
+  0x7f62368f, 0xf3742ca2, 0x7f5fbd77, 0xf35b29e0, 0x7f5d3f75, 0xf342279b,
+  0x7f5abc8a, 0xf32925d3,
+  0x7f5834b7, 0xf310248a, 0x7f55a7fa, 0xf2f723c1, 0x7f531655, 0xf2de2379,
+  0x7f507fc7, 0xf2c523b2,
+  0x7f4de451, 0xf2ac246e, 0x7f4b43f2, 0xf29325ad, 0x7f489eaa, 0xf27a2771,
+  0x7f45f47b, 0xf26129ba,
+  0x7f434563, 0xf2482c8a, 0x7f409164, 0xf22f2fe1, 0x7f3dd87c, 0xf21633c0,
+  0x7f3b1aad, 0xf1fd3829,
+  0x7f3857f6, 0xf1e43d1c, 0x7f359057, 0xf1cb429a, 0x7f32c3d1, 0xf1b248a5,
+  0x7f2ff263, 0xf1994f3d,
+  0x7f2d1c0e, 0xf1805662, 0x7f2a40d2, 0xf1675e17, 0x7f2760af, 0xf14e665c,
+  0x7f247ba5, 0xf1356f32,
+  0x7f2191b4, 0xf11c789a, 0x7f1ea2dc, 0xf1038295, 0x7f1baf1e, 0xf0ea8d24,
+  0x7f18b679, 0xf0d19848,
+  0x7f15b8ee, 0xf0b8a401, 0x7f12b67c, 0xf09fb051, 0x7f0faf25, 0xf086bd39,
+  0x7f0ca2e7, 0xf06dcaba,
+  0x7f0991c4, 0xf054d8d5, 0x7f067bba, 0xf03be78a, 0x7f0360cb, 0xf022f6da,
+  0x7f0040f6, 0xf00a06c8,
+  0x7efd1c3c, 0xeff11753, 0x7ef9f29d, 0xefd8287c, 0x7ef6c418, 0xefbf3a45,
+  0x7ef390ae, 0xefa64cae,
+  0x7ef05860, 0xef8d5fb8, 0x7eed1b2c, 0xef747365, 0x7ee9d914, 0xef5b87b5,
+  0x7ee69217, 0xef429caa,
+  0x7ee34636, 0xef29b243, 0x7edff570, 0xef10c883, 0x7edc9fc6, 0xeef7df6a,
+  0x7ed94538, 0xeedef6f9,
+  0x7ed5e5c6, 0xeec60f31, 0x7ed28171, 0xeead2813, 0x7ecf1837, 0xee9441a0,
+  0x7ecbaa1a, 0xee7b5bd9,
+  0x7ec8371a, 0xee6276bf, 0x7ec4bf36, 0xee499253, 0x7ec14270, 0xee30ae96,
+  0x7ebdc0c6, 0xee17cb88,
+  0x7eba3a39, 0xedfee92b, 0x7eb6aeca, 0xede60780, 0x7eb31e78, 0xedcd2687,
+  0x7eaf8943, 0xedb44642,
+  0x7eabef2c, 0xed9b66b2, 0x7ea85033, 0xed8287d7, 0x7ea4ac58, 0xed69a9b3,
+  0x7ea1039b, 0xed50cc46,
+  0x7e9d55fc, 0xed37ef91, 0x7e99a37c, 0xed1f1396, 0x7e95ec1a, 0xed063856,
+  0x7e922fd6, 0xeced5dd0,
+  0x7e8e6eb2, 0xecd48407, 0x7e8aa8ac, 0xecbbaafb, 0x7e86ddc6, 0xeca2d2ad,
+  0x7e830dff, 0xec89fb1e,
+  0x7e7f3957, 0xec71244f, 0x7e7b5fce, 0xec584e41, 0x7e778166, 0xec3f78f6,
+  0x7e739e1d, 0xec26a46d,
+  0x7e6fb5f4, 0xec0dd0a8, 0x7e6bc8eb, 0xebf4fda8, 0x7e67d703, 0xebdc2b6e,
+  0x7e63e03b, 0xebc359fb,
+  0x7e5fe493, 0xebaa894f, 0x7e5be40c, 0xeb91b96c, 0x7e57dea7, 0xeb78ea52,
+  0x7e53d462, 0xeb601c04,
+  0x7e4fc53e, 0xeb474e81, 0x7e4bb13c, 0xeb2e81ca, 0x7e47985b, 0xeb15b5e1,
+  0x7e437a9c, 0xeafceac6,
+  0x7e3f57ff, 0xeae4207a, 0x7e3b3083, 0xeacb56ff, 0x7e37042a, 0xeab28e56,
+  0x7e32d2f4, 0xea99c67e,
+  0x7e2e9cdf, 0xea80ff7a, 0x7e2a61ed, 0xea683949, 0x7e26221f, 0xea4f73ee,
+  0x7e21dd73, 0xea36af69,
+  0x7e1d93ea, 0xea1debbb, 0x7e194584, 0xea0528e5, 0x7e14f242, 0xe9ec66e8,
+  0x7e109a24, 0xe9d3a5c5,
+  0x7e0c3d29, 0xe9bae57d, 0x7e07db52, 0xe9a22610, 0x7e0374a0, 0xe9896781,
+  0x7dff0911, 0xe970a9ce,
+  0x7dfa98a8, 0xe957ecfb, 0x7df62362, 0xe93f3107, 0x7df1a942, 0xe92675f4,
+  0x7ded2a47, 0xe90dbbc2,
+  0x7de8a670, 0xe8f50273, 0x7de41dc0, 0xe8dc4a07, 0x7ddf9034, 0xe8c39280,
+  0x7ddafdce, 0xe8aadbde,
+  0x7dd6668f, 0xe8922622, 0x7dd1ca75, 0xe879714d, 0x7dcd2981, 0xe860bd61,
+  0x7dc883b4, 0xe8480a5d,
+  0x7dc3d90d, 0xe82f5844, 0x7dbf298d, 0xe816a716, 0x7dba7534, 0xe7fdf6d4,
+  0x7db5bc02, 0xe7e5477f,
+  0x7db0fdf8, 0xe7cc9917, 0x7dac3b15, 0xe7b3eb9f, 0x7da77359, 0xe79b3f16,
+  0x7da2a6c6, 0xe782937e,
+  0x7d9dd55a, 0xe769e8d8, 0x7d98ff17, 0xe7513f25, 0x7d9423fc, 0xe7389665,
+  0x7d8f4409, 0xe71fee99,
+  0x7d8a5f40, 0xe70747c4, 0x7d85759f, 0xe6eea1e4, 0x7d808728, 0xe6d5fcfc,
+  0x7d7b93da, 0xe6bd590d,
+  0x7d769bb5, 0xe6a4b616, 0x7d719eba, 0xe68c141a, 0x7d6c9ce9, 0xe6737319,
+  0x7d679642, 0xe65ad315,
+  0x7d628ac6, 0xe642340d, 0x7d5d7a74, 0xe6299604, 0x7d58654d, 0xe610f8f9,
+  0x7d534b50, 0xe5f85cef,
+  0x7d4e2c7f, 0xe5dfc1e5, 0x7d4908d9, 0xe5c727dd, 0x7d43e05e, 0xe5ae8ed8,
+  0x7d3eb30f, 0xe595f6d7,
+  0x7d3980ec, 0xe57d5fda, 0x7d3449f5, 0xe564c9e3, 0x7d2f0e2b, 0xe54c34f3,
+  0x7d29cd8c, 0xe533a10a,
+  0x7d24881b, 0xe51b0e2a, 0x7d1f3dd6, 0xe5027c53, 0x7d19eebf, 0xe4e9eb87,
+  0x7d149ad5, 0xe4d15bc6,
+  0x7d0f4218, 0xe4b8cd11, 0x7d09e489, 0xe4a03f69, 0x7d048228, 0xe487b2d0,
+  0x7cff1af5, 0xe46f2745,
+  0x7cf9aef0, 0xe4569ccb, 0x7cf43e1a, 0xe43e1362, 0x7ceec873, 0xe4258b0a,
+  0x7ce94dfb, 0xe40d03c6,
+  0x7ce3ceb2, 0xe3f47d96, 0x7cde4a98, 0xe3dbf87a, 0x7cd8c1ae, 0xe3c37474,
+  0x7cd333f3, 0xe3aaf184,
+  0x7ccda169, 0xe3926fad, 0x7cc80a0f, 0xe379eeed, 0x7cc26de5, 0xe3616f48,
+  0x7cbcccec, 0xe348f0bd,
+  0x7cb72724, 0xe330734d, 0x7cb17c8d, 0xe317f6fa, 0x7cabcd28, 0xe2ff7bc3,
+  0x7ca618f3, 0xe2e701ac,
+  0x7ca05ff1, 0xe2ce88b3, 0x7c9aa221, 0xe2b610da, 0x7c94df83, 0xe29d9a23,
+  0x7c8f1817, 0xe285248d,
+  0x7c894bde, 0xe26cb01b, 0x7c837ad8, 0xe2543ccc, 0x7c7da505, 0xe23bcaa2,
+  0x7c77ca65, 0xe223599e,
+  0x7c71eaf9, 0xe20ae9c1, 0x7c6c06c0, 0xe1f27b0b, 0x7c661dbc, 0xe1da0d7e,
+  0x7c602fec, 0xe1c1a11b,
+  0x7c5a3d50, 0xe1a935e2, 0x7c5445e9, 0xe190cbd4, 0x7c4e49b7, 0xe17862f3,
+  0x7c4848ba, 0xe15ffb3f,
+  0x7c4242f2, 0xe14794ba, 0x7c3c3860, 0xe12f2f63, 0x7c362904, 0xe116cb3d,
+  0x7c3014de, 0xe0fe6848,
+  0x7c29fbee, 0xe0e60685, 0x7c23de35, 0xe0cda5f5, 0x7c1dbbb3, 0xe0b54698,
+  0x7c179467, 0xe09ce871,
+  0x7c116853, 0xe0848b7f, 0x7c0b3777, 0xe06c2fc4, 0x7c0501d2, 0xe053d541,
+  0x7bfec765, 0xe03b7bf6,
+  0x7bf88830, 0xe02323e5, 0x7bf24434, 0xe00acd0e, 0x7bebfb70, 0xdff27773,
+  0x7be5ade6, 0xdfda2314,
+  0x7bdf5b94, 0xdfc1cff3, 0x7bd9047c, 0xdfa97e0f, 0x7bd2a89e, 0xdf912d6b,
+  0x7bcc47fa, 0xdf78de07,
+  0x7bc5e290, 0xdf608fe4, 0x7bbf7860, 0xdf484302, 0x7bb9096b, 0xdf2ff764,
+  0x7bb295b0, 0xdf17ad0a,
+  0x7bac1d31, 0xdeff63f4, 0x7ba59fee, 0xdee71c24, 0x7b9f1de6, 0xdeced59b,
+  0x7b989719, 0xdeb69059,
+  0x7b920b89, 0xde9e4c60, 0x7b8b7b36, 0xde8609b1, 0x7b84e61f, 0xde6dc84b,
+  0x7b7e4c45, 0xde558831,
+  0x7b77ada8, 0xde3d4964, 0x7b710a49, 0xde250be3, 0x7b6a6227, 0xde0ccfb1,
+  0x7b63b543, 0xddf494ce,
+  0x7b5d039e, 0xdddc5b3b, 0x7b564d36, 0xddc422f8, 0x7b4f920e, 0xddabec08,
+  0x7b48d225, 0xdd93b66a,
+  0x7b420d7a, 0xdd7b8220, 0x7b3b4410, 0xdd634f2b, 0x7b3475e5, 0xdd4b1d8c,
+  0x7b2da2fa, 0xdd32ed43,
+  0x7b26cb4f, 0xdd1abe51, 0x7b1feee5, 0xdd0290b8, 0x7b190dbc, 0xdcea6478,
+  0x7b1227d3, 0xdcd23993,
+  0x7b0b3d2c, 0xdcba1008, 0x7b044dc7, 0xdca1e7da, 0x7afd59a4, 0xdc89c109,
+  0x7af660c2, 0xdc719b96,
+  0x7aef6323, 0xdc597781, 0x7ae860c7, 0xdc4154cd, 0x7ae159ae, 0xdc293379,
+  0x7ada4dd8, 0xdc111388,
+  0x7ad33d45, 0xdbf8f4f8, 0x7acc27f7, 0xdbe0d7cd, 0x7ac50dec, 0xdbc8bc06,
+  0x7abdef25, 0xdbb0a1a4,
+  0x7ab6cba4, 0xdb9888a8, 0x7aafa367, 0xdb807114, 0x7aa8766f, 0xdb685ae9,
+  0x7aa144bc, 0xdb504626,
+  0x7a9a0e50, 0xdb3832cd, 0x7a92d329, 0xdb2020e0, 0x7a8b9348, 0xdb08105e,
+  0x7a844eae, 0xdaf00149,
+  0x7a7d055b, 0xdad7f3a2, 0x7a75b74f, 0xdabfe76a, 0x7a6e648a, 0xdaa7dca1,
+  0x7a670d0d, 0xda8fd349,
+  0x7a5fb0d8, 0xda77cb63, 0x7a584feb, 0xda5fc4ef, 0x7a50ea47, 0xda47bfee,
+  0x7a497feb, 0xda2fbc61,
+  0x7a4210d8, 0xda17ba4a, 0x7a3a9d0f, 0xd9ffb9a9, 0x7a332490, 0xd9e7ba7f,
+  0x7a2ba75a, 0xd9cfbccd,
+  0x7a24256f, 0xd9b7c094, 0x7a1c9ece, 0xd99fc5d4, 0x7a151378, 0xd987cc90,
+  0x7a0d836d, 0xd96fd4c7,
+  0x7a05eead, 0xd957de7a, 0x79fe5539, 0xd93fe9ab, 0x79f6b711, 0xd927f65b,
+  0x79ef1436, 0xd910048a,
+  0x79e76ca7, 0xd8f81439, 0x79dfc064, 0xd8e0256a, 0x79d80f6f, 0xd8c8381d,
+  0x79d059c8, 0xd8b04c52,
+  0x79c89f6e, 0xd898620c, 0x79c0e062, 0xd880794b, 0x79b91ca4, 0xd868920f,
+  0x79b15435, 0xd850ac5a,
+  0x79a98715, 0xd838c82d, 0x79a1b545, 0xd820e589, 0x7999dec4, 0xd809046e,
+  0x79920392, 0xd7f124dd,
+  0x798a23b1, 0xd7d946d8, 0x79823f20, 0xd7c16a5f, 0x797a55e0, 0xd7a98f73,
+  0x797267f2, 0xd791b616,
+  0x796a7554, 0xd779de47, 0x79627e08, 0xd7620808, 0x795a820e, 0xd74a335b,
+  0x79528167, 0xd732603f,
+  0x794a7c12, 0xd71a8eb5, 0x79427210, 0xd702bec0, 0x793a6361, 0xd6eaf05f,
+  0x79325006, 0xd6d32393,
+  0x792a37fe, 0xd6bb585e, 0x79221b4b, 0xd6a38ec0, 0x7919f9ec, 0xd68bc6ba,
+  0x7911d3e2, 0xd674004e,
+  0x7909a92d, 0xd65c3b7b, 0x790179cd, 0xd6447844, 0x78f945c3, 0xd62cb6a8,
+  0x78f10d0f, 0xd614f6a9,
+  0x78e8cfb2, 0xd5fd3848, 0x78e08dab, 0xd5e57b85, 0x78d846fb, 0xd5cdc062,
+  0x78cffba3, 0xd5b606e0,
+  0x78c7aba2, 0xd59e4eff, 0x78bf56f9, 0xd58698c0, 0x78b6fda8, 0xd56ee424,
+  0x78ae9fb0, 0xd557312d,
+  0x78a63d11, 0xd53f7fda, 0x789dd5cb, 0xd527d02e, 0x789569df, 0xd5102228,
+  0x788cf94c, 0xd4f875ca,
+  0x78848414, 0xd4e0cb15, 0x787c0a36, 0xd4c92209, 0x78738bb3, 0xd4b17aa8,
+  0x786b088c, 0xd499d4f2,
+  0x786280bf, 0xd48230e9, 0x7859f44f, 0xd46a8e8d, 0x7851633b, 0xd452eddf,
+  0x7848cd83, 0xd43b4ee0,
+  0x78403329, 0xd423b191, 0x7837942b, 0xd40c15f3, 0x782ef08b, 0xd3f47c06,
+  0x78264849, 0xd3dce3cd,
+  0x781d9b65, 0xd3c54d47, 0x7814e9df, 0xd3adb876, 0x780c33b8, 0xd396255a,
+  0x780378f1, 0xd37e93f4,
+  0x77fab989, 0xd3670446, 0x77f1f581, 0xd34f764f, 0x77e92cd9, 0xd337ea12,
+  0x77e05f91, 0xd3205f8f,
+  0x77d78daa, 0xd308d6c7, 0x77ceb725, 0xd2f14fba, 0x77c5dc01, 0xd2d9ca6a,
+  0x77bcfc3f, 0xd2c246d8,
+  0x77b417df, 0xd2aac504, 0x77ab2ee2, 0xd29344f0, 0x77a24148, 0xd27bc69c,
+  0x77994f11, 0xd2644a0a,
+  0x7790583e, 0xd24ccf39, 0x77875cce, 0xd235562b, 0x777e5cc3, 0xd21ddee2,
+  0x7775581d, 0xd206695d,
+  0x776c4edb, 0xd1eef59e, 0x776340ff, 0xd1d783a6, 0x775a2e89, 0xd1c01375,
+  0x77511778, 0xd1a8a50d,
+  0x7747fbce, 0xd191386e, 0x773edb8b, 0xd179cd99, 0x7735b6af, 0xd1626490,
+  0x772c8d3a, 0xd14afd52,
+  0x77235f2d, 0xd13397e2, 0x771a2c88, 0xd11c343f, 0x7710f54c, 0xd104d26b,
+  0x7707b979, 0xd0ed7267,
+  0x76fe790e, 0xd0d61434, 0x76f5340e, 0xd0beb7d2, 0x76ebea77, 0xd0a75d42,
+  0x76e29c4b, 0xd0900486,
+  0x76d94989, 0xd078ad9e, 0x76cff232, 0xd061588b, 0x76c69647, 0xd04a054e,
+  0x76bd35c7, 0xd032b3e7,
+  0x76b3d0b4, 0xd01b6459, 0x76aa670d, 0xd00416a3, 0x76a0f8d2, 0xcfeccac7,
+  0x76978605, 0xcfd580c6,
+  0x768e0ea6, 0xcfbe389f, 0x768492b4, 0xcfa6f255, 0x767b1231, 0xcf8fade9,
+  0x76718d1c, 0xcf786b5a,
+  0x76680376, 0xcf612aaa, 0x765e7540, 0xcf49ebda, 0x7654e279, 0xcf32aeeb,
+  0x764b4b23, 0xcf1b73de,
+  0x7641af3d, 0xcf043ab3, 0x76380ec8, 0xceed036b, 0x762e69c4, 0xced5ce08,
+  0x7624c031, 0xcebe9a8a,
+  0x761b1211, 0xcea768f2, 0x76115f63, 0xce903942, 0x7607a828, 0xce790b79,
+  0x75fdec60, 0xce61df99,
+  0x75f42c0b, 0xce4ab5a2, 0x75ea672a, 0xce338d97, 0x75e09dbd, 0xce1c6777,
+  0x75d6cfc5, 0xce054343,
+  0x75ccfd42, 0xcdee20fc, 0x75c32634, 0xcdd700a4, 0x75b94a9c, 0xcdbfe23a,
+  0x75af6a7b, 0xcda8c5c1,
+  0x75a585cf, 0xcd91ab39, 0x759b9c9b, 0xcd7a92a2, 0x7591aedd, 0xcd637bfe,
+  0x7587bc98, 0xcd4c674d,
+  0x757dc5ca, 0xcd355491, 0x7573ca75, 0xcd1e43ca, 0x7569ca99, 0xcd0734f9,
+  0x755fc635, 0xccf0281f,
+  0x7555bd4c, 0xccd91d3d, 0x754bafdc, 0xccc21455, 0x75419de7, 0xccab0d65,
+  0x7537876c, 0xcc940871,
+  0x752d6c6c, 0xcc7d0578, 0x75234ce8, 0xcc66047b, 0x751928e0, 0xcc4f057c,
+  0x750f0054, 0xcc38087b,
+  0x7504d345, 0xcc210d79, 0x74faa1b3, 0xcc0a1477, 0x74f06b9e, 0xcbf31d75,
+  0x74e63108, 0xcbdc2876,
+  0x74dbf1ef, 0xcbc53579, 0x74d1ae55, 0xcbae447f, 0x74c7663a, 0xcb97558a,
+  0x74bd199f, 0xcb80689a,
+  0x74b2c884, 0xcb697db0, 0x74a872e8, 0xcb5294ce, 0x749e18cd, 0xcb3badf3,
+  0x7493ba34, 0xcb24c921,
+  0x7489571c, 0xcb0de658, 0x747eef85, 0xcaf7059a, 0x74748371, 0xcae026e8,
+  0x746a12df, 0xcac94a42,
+  0x745f9dd1, 0xcab26fa9, 0x74552446, 0xca9b971e, 0x744aa63f, 0xca84c0a3,
+  0x744023bc, 0xca6dec37,
+  0x74359cbd, 0xca5719db, 0x742b1144, 0xca404992, 0x74208150, 0xca297b5a,
+  0x7415ece2, 0xca12af37,
+  0x740b53fb, 0xc9fbe527, 0x7400b69a, 0xc9e51d2d, 0x73f614c0, 0xc9ce5748,
+  0x73eb6e6e, 0xc9b7937a,
+  0x73e0c3a3, 0xc9a0d1c5, 0x73d61461, 0xc98a1227, 0x73cb60a8, 0xc97354a4,
+  0x73c0a878, 0xc95c993a,
+  0x73b5ebd1, 0xc945dfec, 0x73ab2ab4, 0xc92f28ba, 0x73a06522, 0xc91873a5,
+  0x73959b1b, 0xc901c0ae,
+  0x738acc9e, 0xc8eb0fd6, 0x737ff9ae, 0xc8d4611d, 0x73752249, 0xc8bdb485,
+  0x736a4671, 0xc8a70a0e,
+  0x735f6626, 0xc89061ba, 0x73548168, 0xc879bb89, 0x73499838, 0xc863177b,
+  0x733eaa96, 0xc84c7593,
+  0x7333b883, 0xc835d5d0, 0x7328c1ff, 0xc81f3834, 0x731dc70a, 0xc8089cbf,
+  0x7312c7a5, 0xc7f20373,
+  0x7307c3d0, 0xc7db6c50, 0x72fcbb8c, 0xc7c4d757, 0x72f1aed9, 0xc7ae4489,
+  0x72e69db7, 0xc797b3e7,
+  0x72db8828, 0xc7812572, 0x72d06e2b, 0xc76a992a, 0x72c54fc1, 0xc7540f11,
+  0x72ba2cea, 0xc73d8727,
+  0x72af05a7, 0xc727016d, 0x72a3d9f7, 0xc7107de4, 0x7298a9dd, 0xc6f9fc8d,
+  0x728d7557, 0xc6e37d69,
+  0x72823c67, 0xc6cd0079, 0x7276ff0d, 0xc6b685bd, 0x726bbd48, 0xc6a00d37,
+  0x7260771b, 0xc68996e7,
+  0x72552c85, 0xc67322ce, 0x7249dd86, 0xc65cb0ed, 0x723e8a20, 0xc6464144,
+  0x72333251, 0xc62fd3d6,
+  0x7227d61c, 0xc61968a2, 0x721c7580, 0xc602ffaa, 0x7211107e, 0xc5ec98ee,
+  0x7205a716, 0xc5d6346f,
+  0x71fa3949, 0xc5bfd22e, 0x71eec716, 0xc5a9722c, 0x71e35080, 0xc593146a,
+  0x71d7d585, 0xc57cb8e9,
+  0x71cc5626, 0xc5665fa9, 0x71c0d265, 0xc55008ab, 0x71b54a41, 0xc539b3f1,
+  0x71a9bdba, 0xc523617a,
+  0x719e2cd2, 0xc50d1149, 0x71929789, 0xc4f6c35d, 0x7186fdde, 0xc4e077b8,
+  0x717b5fd3, 0xc4ca2e5b,
+  0x716fbd68, 0xc4b3e746, 0x7164169d, 0xc49da27a, 0x71586b74, 0xc4875ff9,
+  0x714cbbeb, 0xc4711fc2,
+  0x71410805, 0xc45ae1d7, 0x71354fc0, 0xc444a639, 0x7129931f, 0xc42e6ce8,
+  0x711dd220, 0xc41835e6,
+  0x71120cc5, 0xc4020133, 0x7106430e, 0xc3ebced0, 0x70fa74fc, 0xc3d59ebe,
+  0x70eea28e, 0xc3bf70fd,
+  0x70e2cbc6, 0xc3a94590, 0x70d6f0a4, 0xc3931c76, 0x70cb1128, 0xc37cf5b0,
+  0x70bf2d53, 0xc366d140,
+  0x70b34525, 0xc350af26, 0x70a7589f, 0xc33a8f62, 0x709b67c0, 0xc32471f7,
+  0x708f728b, 0xc30e56e4,
+  0x708378ff, 0xc2f83e2a, 0x70777b1c, 0xc2e227cb, 0x706b78e3, 0xc2cc13c7,
+  0x705f7255, 0xc2b6021f,
+  0x70536771, 0xc29ff2d4, 0x70475839, 0xc289e5e7, 0x703b44ad, 0xc273db58,
+  0x702f2ccd, 0xc25dd329,
+  0x7023109a, 0xc247cd5a, 0x7016f014, 0xc231c9ec, 0x700acb3c, 0xc21bc8e1,
+  0x6ffea212, 0xc205ca38,
+  0x6ff27497, 0xc1efcdf3, 0x6fe642ca, 0xc1d9d412, 0x6fda0cae, 0xc1c3dc97,
+  0x6fcdd241, 0xc1ade781,
+  0x6fc19385, 0xc197f4d4, 0x6fb5507a, 0xc182048d, 0x6fa90921, 0xc16c16b0,
+  0x6f9cbd79, 0xc1562b3d,
+  0x6f906d84, 0xc1404233, 0x6f841942, 0xc12a5b95, 0x6f77c0b3, 0xc1147764,
+  0x6f6b63d8, 0xc0fe959f,
+  0x6f5f02b2, 0xc0e8b648, 0x6f529d40, 0xc0d2d960, 0x6f463383, 0xc0bcfee7,
+  0x6f39c57d, 0xc0a726df,
+  0x6f2d532c, 0xc0915148, 0x6f20dc92, 0xc07b7e23, 0x6f1461b0, 0xc065ad70,
+  0x6f07e285, 0xc04fdf32,
+  0x6efb5f12, 0xc03a1368, 0x6eeed758, 0xc0244a14, 0x6ee24b57, 0xc00e8336,
+  0x6ed5bb10, 0xbff8bece,
+  0x6ec92683, 0xbfe2fcdf, 0x6ebc8db0, 0xbfcd3d69, 0x6eaff099, 0xbfb7806c,
+  0x6ea34f3d, 0xbfa1c5ea,
+  0x6e96a99d, 0xbf8c0de3, 0x6e89ffb9, 0xbf765858, 0x6e7d5193, 0xbf60a54a,
+  0x6e709f2a, 0xbf4af4ba,
+  0x6e63e87f, 0xbf3546a8, 0x6e572d93, 0xbf1f9b16, 0x6e4a6e66, 0xbf09f205,
+  0x6e3daaf8, 0xbef44b74,
+  0x6e30e34a, 0xbedea765, 0x6e24175c, 0xbec905d9, 0x6e174730, 0xbeb366d1,
+  0x6e0a72c5, 0xbe9dca4e,
+  0x6dfd9a1c, 0xbe88304f, 0x6df0bd35, 0xbe7298d7, 0x6de3dc11, 0xbe5d03e6,
+  0x6dd6f6b1, 0xbe47717c,
+  0x6dca0d14, 0xbe31e19b, 0x6dbd1f3c, 0xbe1c5444, 0x6db02d29, 0xbe06c977,
+  0x6da336dc, 0xbdf14135,
+  0x6d963c54, 0xbddbbb7f, 0x6d893d93, 0xbdc63856, 0x6d7c3a98, 0xbdb0b7bb,
+  0x6d6f3365, 0xbd9b39ad,
+  0x6d6227fa, 0xbd85be30, 0x6d551858, 0xbd704542, 0x6d48047e, 0xbd5acee5,
+  0x6d3aec6e, 0xbd455b1a,
+  0x6d2dd027, 0xbd2fe9e2, 0x6d20afac, 0xbd1a7b3d, 0x6d138afb, 0xbd050f2c,
+  0x6d066215, 0xbcefa5b0,
+  0x6cf934fc, 0xbcda3ecb, 0x6cec03af, 0xbcc4da7b, 0x6cdece2f, 0xbcaf78c4,
+  0x6cd1947c, 0xbc9a19a5,
+  0x6cc45698, 0xbc84bd1f, 0x6cb71482, 0xbc6f6333, 0x6ca9ce3b, 0xbc5a0be2,
+  0x6c9c83c3, 0xbc44b72c,
+  0x6c8f351c, 0xbc2f6513, 0x6c81e245, 0xbc1a1598, 0x6c748b3f, 0xbc04c8ba,
+  0x6c67300b, 0xbbef7e7c,
+  0x6c59d0a9, 0xbbda36dd, 0x6c4c6d1a, 0xbbc4f1df, 0x6c3f055d, 0xbbafaf82,
+  0x6c319975, 0xbb9a6fc7,
+  0x6c242960, 0xbb8532b0, 0x6c16b521, 0xbb6ff83c, 0x6c093cb6, 0xbb5ac06d,
+  0x6bfbc021, 0xbb458b43,
+  0x6bee3f62, 0xbb3058c0, 0x6be0ba7b, 0xbb1b28e4, 0x6bd3316a, 0xbb05fbb0,
+  0x6bc5a431, 0xbaf0d125,
+  0x6bb812d1, 0xbadba943, 0x6baa7d49, 0xbac6840c, 0x6b9ce39b, 0xbab16180,
+  0x6b8f45c7, 0xba9c41a0,
+  0x6b81a3cd, 0xba87246d, 0x6b73fdae, 0xba7209e7, 0x6b66536b, 0xba5cf210,
+  0x6b58a503, 0xba47dce8,
+  0x6b4af279, 0xba32ca71, 0x6b3d3bcb, 0xba1dbaaa, 0x6b2f80fb, 0xba08ad95,
+  0x6b21c208, 0xb9f3a332,
+  0x6b13fef5, 0xb9de9b83, 0x6b0637c1, 0xb9c99688, 0x6af86c6c, 0xb9b49442,
+  0x6aea9cf8, 0xb99f94b2,
+  0x6adcc964, 0xb98a97d8, 0x6acef1b2, 0xb9759db6, 0x6ac115e2, 0xb960a64c,
+  0x6ab335f4, 0xb94bb19b,
+  0x6aa551e9, 0xb936bfa4, 0x6a9769c1, 0xb921d067, 0x6a897d7d, 0xb90ce3e6,
+  0x6a7b8d1e, 0xb8f7fa21,
+  0x6a6d98a4, 0xb8e31319, 0x6a5fa010, 0xb8ce2ecf, 0x6a51a361, 0xb8b94d44,
+  0x6a43a29a, 0xb8a46e78,
+  0x6a359db9, 0xb88f926d, 0x6a2794c1, 0xb87ab922, 0x6a1987b0, 0xb865e299,
+  0x6a0b7689, 0xb8510ed4,
+  0x69fd614a, 0xb83c3dd1, 0x69ef47f6, 0xb8276f93, 0x69e12a8c, 0xb812a41a,
+  0x69d3090e, 0xb7fddb67,
+  0x69c4e37a, 0xb7e9157a, 0x69b6b9d3, 0xb7d45255, 0x69a88c19, 0xb7bf91f8,
+  0x699a5a4c, 0xb7aad465,
+  0x698c246c, 0xb796199b, 0x697dea7b, 0xb781619c, 0x696fac78, 0xb76cac69,
+  0x69616a65, 0xb757fa01,
+  0x69532442, 0xb7434a67, 0x6944da10, 0xb72e9d9b, 0x69368bce, 0xb719f39e,
+  0x6928397e, 0xb7054c6f,
+  0x6919e320, 0xb6f0a812, 0x690b88b5, 0xb6dc0685, 0x68fd2a3d, 0xb6c767ca,
+  0x68eec7b9, 0xb6b2cbe2,
+  0x68e06129, 0xb69e32cd, 0x68d1f68f, 0xb6899c8d, 0x68c387e9, 0xb6750921,
+  0x68b5153a, 0xb660788c,
+  0x68a69e81, 0xb64beacd, 0x689823bf, 0xb6375fe5, 0x6889a4f6, 0xb622d7d6,
+  0x687b2224, 0xb60e529f,
+  0x686c9b4b, 0xb5f9d043, 0x685e106c, 0xb5e550c1, 0x684f8186, 0xb5d0d41a,
+  0x6840ee9b, 0xb5bc5a50,
+  0x683257ab, 0xb5a7e362, 0x6823bcb7, 0xb5936f53, 0x68151dbe, 0xb57efe22,
+  0x68067ac3, 0xb56a8fd0,
+  0x67f7d3c5, 0xb556245e, 0x67e928c5, 0xb541bbcd, 0x67da79c3, 0xb52d561e,
+  0x67cbc6c0, 0xb518f351,
+  0x67bd0fbd, 0xb5049368, 0x67ae54ba, 0xb4f03663, 0x679f95b7, 0xb4dbdc42,
+  0x6790d2b6, 0xb4c78507,
+  0x67820bb7, 0xb4b330b3, 0x677340ba, 0xb49edf45, 0x676471c0, 0xb48a90c0,
+  0x67559eca, 0xb4764523,
+  0x6746c7d8, 0xb461fc70, 0x6737ecea, 0xb44db6a8, 0x67290e02, 0xb43973ca,
+  0x671a2b20, 0xb42533d8,
+  0x670b4444, 0xb410f6d3, 0x66fc596f, 0xb3fcbcbb, 0x66ed6aa1, 0xb3e88592,
+  0x66de77dc, 0xb3d45157,
+  0x66cf8120, 0xb3c0200c, 0x66c0866d, 0xb3abf1b2, 0x66b187c3, 0xb397c649,
+  0x66a28524, 0xb3839dd3,
+  0x66937e91, 0xb36f784f, 0x66847408, 0xb35b55bf, 0x6675658c, 0xb3473623,
+  0x6666531d, 0xb333197c,
+  0x66573cbb, 0xb31effcc, 0x66482267, 0xb30ae912, 0x66390422, 0xb2f6d550,
+  0x6629e1ec, 0xb2e2c486,
+  0x661abbc5, 0xb2ceb6b5, 0x660b91af, 0xb2baabde, 0x65fc63a9, 0xb2a6a402,
+  0x65ed31b5, 0xb2929f21,
+  0x65ddfbd3, 0xb27e9d3c, 0x65cec204, 0xb26a9e54, 0x65bf8447, 0xb256a26a,
+  0x65b0429f, 0xb242a97e,
+  0x65a0fd0b, 0xb22eb392, 0x6591b38c, 0xb21ac0a6, 0x65826622, 0xb206d0ba,
+  0x657314cf, 0xb1f2e3d0,
+  0x6563bf92, 0xb1def9e9, 0x6554666d, 0xb1cb1304, 0x6545095f, 0xb1b72f23,
+  0x6535a86b, 0xb1a34e47,
+  0x6526438f, 0xb18f7071, 0x6516dacd, 0xb17b95a0, 0x65076e25, 0xb167bdd7,
+  0x64f7fd98, 0xb153e915,
+  0x64e88926, 0xb140175b, 0x64d910d1, 0xb12c48ab, 0x64c99498, 0xb1187d05,
+  0x64ba147d, 0xb104b46a,
+  0x64aa907f, 0xb0f0eeda, 0x649b08a0, 0xb0dd2c56, 0x648b7ce0, 0xb0c96ce0,
+  0x647bed3f, 0xb0b5b077,
+  0x646c59bf, 0xb0a1f71d, 0x645cc260, 0xb08e40d2, 0x644d2722, 0xb07a8d97,
+  0x643d8806, 0xb066dd6d,
+  0x642de50d, 0xb0533055, 0x641e3e38, 0xb03f864f, 0x640e9386, 0xb02bdf5c,
+  0x63fee4f8, 0xb0183b7d,
+  0x63ef3290, 0xb0049ab3, 0x63df7c4d, 0xaff0fcfe, 0x63cfc231, 0xafdd625f,
+  0x63c0043b, 0xafc9cad7,
+  0x63b0426d, 0xafb63667, 0x63a07cc7, 0xafa2a50f, 0x6390b34a, 0xaf8f16d1,
+  0x6380e5f6, 0xaf7b8bac,
+  0x637114cc, 0xaf6803a2, 0x63613fcd, 0xaf547eb3, 0x635166f9, 0xaf40fce1,
+  0x63418a50, 0xaf2d7e2b,
+  0x6331a9d4, 0xaf1a0293, 0x6321c585, 0xaf068a1a, 0x6311dd64, 0xaef314c0,
+  0x6301f171, 0xaedfa285,
+  0x62f201ac, 0xaecc336c, 0x62e20e17, 0xaeb8c774, 0x62d216b3, 0xaea55e9e,
+  0x62c21b7e, 0xae91f8eb,
+  0x62b21c7b, 0xae7e965b, 0x62a219aa, 0xae6b36f0, 0x6292130c, 0xae57daab,
+  0x628208a1, 0xae44818b,
+  0x6271fa69, 0xae312b92, 0x6261e866, 0xae1dd8c0, 0x6251d298, 0xae0a8916,
+  0x6241b8ff, 0xadf73c96,
+  0x62319b9d, 0xade3f33e, 0x62217a72, 0xadd0ad12, 0x6211557e, 0xadbd6a10,
+  0x62012cc2, 0xadaa2a3b,
+  0x61f1003f, 0xad96ed92, 0x61e0cff5, 0xad83b416, 0x61d09be5, 0xad707dc8,
+  0x61c06410, 0xad5d4aaa,
+  0x61b02876, 0xad4a1aba, 0x619fe918, 0xad36edfc, 0x618fa5f7, 0xad23c46e,
+  0x617f5f12, 0xad109e12,
+  0x616f146c, 0xacfd7ae8, 0x615ec603, 0xacea5af2, 0x614e73da, 0xacd73e30,
+  0x613e1df0, 0xacc424a3,
+  0x612dc447, 0xacb10e4b, 0x611d66de, 0xac9dfb29, 0x610d05b7, 0xac8aeb3e,
+  0x60fca0d2, 0xac77de8b,
+  0x60ec3830, 0xac64d510, 0x60dbcbd1, 0xac51cecf, 0x60cb5bb7, 0xac3ecbc7,
+  0x60bae7e1, 0xac2bcbfa,
+  0x60aa7050, 0xac18cf69, 0x6099f505, 0xac05d613, 0x60897601, 0xabf2dffb,
+  0x6078f344, 0xabdfed1f,
+  0x60686ccf, 0xabccfd83, 0x6057e2a2, 0xabba1125, 0x604754bf, 0xaba72807,
+  0x6036c325, 0xab944229,
+  0x60262dd6, 0xab815f8d, 0x601594d1, 0xab6e8032, 0x6004f819, 0xab5ba41a,
+  0x5ff457ad, 0xab48cb46,
+  0x5fe3b38d, 0xab35f5b5, 0x5fd30bbc, 0xab23236a, 0x5fc26038, 0xab105464,
+  0x5fb1b104, 0xaafd88a4,
+  0x5fa0fe1f, 0xaaeac02c, 0x5f90478a, 0xaad7fafb, 0x5f7f8d46, 0xaac53912,
+  0x5f6ecf53, 0xaab27a73,
+  0x5f5e0db3, 0xaa9fbf1e, 0x5f4d4865, 0xaa8d0713, 0x5f3c7f6b, 0xaa7a5253,
+  0x5f2bb2c5, 0xaa67a0e0,
+  0x5f1ae274, 0xaa54f2ba, 0x5f0a0e77, 0xaa4247e1, 0x5ef936d1, 0xaa2fa056,
+  0x5ee85b82, 0xaa1cfc1a,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5ec699e9, 0xa9f7bd92, 0x5eb5b3a2, 0xa9e52347,
+  0x5ea4c9b3, 0xa9d28c4e,
+  0x5e93dc1f, 0xa9bff8a8, 0x5e82eae5, 0xa9ad6855, 0x5e71f606, 0xa99adb56,
+  0x5e60fd84, 0xa98851ac,
+  0x5e50015d, 0xa975cb57, 0x5e3f0194, 0xa9634858, 0x5e2dfe29, 0xa950c8b0,
+  0x5e1cf71c, 0xa93e4c5f,
+  0x5e0bec6e, 0xa92bd367, 0x5dfade20, 0xa9195dc7, 0x5de9cc33, 0xa906eb82,
+  0x5dd8b6a7, 0xa8f47c97,
+  0x5dc79d7c, 0xa8e21106, 0x5db680b4, 0xa8cfa8d2, 0x5da5604f, 0xa8bd43fa,
+  0x5d943c4e, 0xa8aae280,
+  0x5d8314b1, 0xa8988463, 0x5d71e979, 0xa88629a5, 0x5d60baa7, 0xa873d246,
+  0x5d4f883b, 0xa8617e48,
+  0x5d3e5237, 0xa84f2daa, 0x5d2d189a, 0xa83ce06e, 0x5d1bdb65, 0xa82a9693,
+  0x5d0a9a9a, 0xa818501c,
+  0x5cf95638, 0xa8060d08, 0x5ce80e41, 0xa7f3cd59, 0x5cd6c2b5, 0xa7e1910f,
+  0x5cc57394, 0xa7cf582a,
+  0x5cb420e0, 0xa7bd22ac, 0x5ca2ca99, 0xa7aaf094, 0x5c9170bf, 0xa798c1e5,
+  0x5c801354, 0xa786969e,
+  0x5c6eb258, 0xa7746ec0, 0x5c5d4dcc, 0xa7624a4d, 0x5c4be5b0, 0xa7502943,
+  0x5c3a7a05, 0xa73e0ba5,
+  0x5c290acc, 0xa72bf174, 0x5c179806, 0xa719daae, 0x5c0621b2, 0xa707c757,
+  0x5bf4a7d2, 0xa6f5b76d,
+  0x5be32a67, 0xa6e3aaf2, 0x5bd1a971, 0xa6d1a1e7, 0x5bc024f0, 0xa6bf9c4b,
+  0x5bae9ce7, 0xa6ad9a21,
+  0x5b9d1154, 0xa69b9b68, 0x5b8b8239, 0xa689a022, 0x5b79ef96, 0xa677a84e,
+  0x5b68596d, 0xa665b3ee,
+  0x5b56bfbd, 0xa653c303, 0x5b452288, 0xa641d58c, 0x5b3381ce, 0xa62feb8b,
+  0x5b21dd90, 0xa61e0501,
+  0x5b1035cf, 0xa60c21ee, 0x5afe8a8b, 0xa5fa4252, 0x5aecdbc5, 0xa5e8662f,
+  0x5adb297d, 0xa5d68d85,
+  0x5ac973b5, 0xa5c4b855, 0x5ab7ba6c, 0xa5b2e6a0, 0x5aa5fda5, 0xa5a11866,
+  0x5a943d5e, 0xa58f4da8,
+  0x5a82799a, 0xa57d8666, 0x5a70b258, 0xa56bc2a2, 0x5a5ee79a, 0xa55a025b,
+  0x5a4d1960, 0xa5484594,
+  0x5a3b47ab, 0xa5368c4b, 0x5a29727b, 0xa524d683, 0x5a1799d1, 0xa513243b,
+  0x5a05bdae, 0xa5017575,
+  0x59f3de12, 0xa4efca31, 0x59e1faff, 0xa4de2270, 0x59d01475, 0xa4cc7e32,
+  0x59be2a74, 0xa4badd78,
+  0x59ac3cfd, 0xa4a94043, 0x599a4c12, 0xa497a693, 0x598857b2, 0xa486106a,
+  0x59765fde, 0xa4747dc7,
+  0x59646498, 0xa462eeac, 0x595265df, 0xa4516319, 0x594063b5, 0xa43fdb10,
+  0x592e5e19, 0xa42e568f,
+  0x591c550e, 0xa41cd599, 0x590a4893, 0xa40b582e, 0x58f838a9, 0xa3f9de4e,
+  0x58e62552, 0xa3e867fa,
+  0x58d40e8c, 0xa3d6f534, 0x58c1f45b, 0xa3c585fb, 0x58afd6bd, 0xa3b41a50,
+  0x589db5b3, 0xa3a2b234,
+  0x588b9140, 0xa3914da8, 0x58796962, 0xa37fecac, 0x58673e1b, 0xa36e8f41,
+  0x58550f6c, 0xa35d3567,
+  0x5842dd54, 0xa34bdf20, 0x5830a7d6, 0xa33a8c6c, 0x581e6ef1, 0xa3293d4b,
+  0x580c32a7, 0xa317f1bf,
+  0x57f9f2f8, 0xa306a9c8, 0x57e7afe4, 0xa2f56566, 0x57d5696d, 0xa2e4249b,
+  0x57c31f92, 0xa2d2e766,
+  0x57b0d256, 0xa2c1adc9, 0x579e81b8, 0xa2b077c5, 0x578c2dba, 0xa29f4559,
+  0x5779d65b, 0xa28e1687,
+  0x57677b9d, 0xa27ceb4f, 0x57551d80, 0xa26bc3b2, 0x5742bc06, 0xa25a9fb1,
+  0x5730572e, 0xa2497f4c,
+  0x571deefa, 0xa2386284, 0x570b8369, 0xa2274959, 0x56f9147e, 0xa21633cd,
+  0x56e6a239, 0xa20521e0,
+  0x56d42c99, 0xa1f41392, 0x56c1b3a1, 0xa1e308e4, 0x56af3750, 0xa1d201d7,
+  0x569cb7a8, 0xa1c0fe6c,
+  0x568a34a9, 0xa1affea3, 0x5677ae54, 0xa19f027c, 0x566524aa, 0xa18e09fa,
+  0x565297ab, 0xa17d151b,
+  0x56400758, 0xa16c23e1, 0x562d73b2, 0xa15b364d, 0x561adcb9, 0xa14a4c5e,
+  0x5608426e, 0xa1396617,
+  0x55f5a4d2, 0xa1288376, 0x55e303e6, 0xa117a47e, 0x55d05faa, 0xa106c92f,
+  0x55bdb81f, 0xa0f5f189,
+  0x55ab0d46, 0xa0e51d8c, 0x55985f20, 0xa0d44d3b, 0x5585adad, 0xa0c38095,
+  0x5572f8ed, 0xa0b2b79b,
+  0x556040e2, 0xa0a1f24d, 0x554d858d, 0xa09130ad, 0x553ac6ee, 0xa08072ba,
+  0x55280505, 0xa06fb876,
+  0x55153fd4, 0xa05f01e1, 0x5502775c, 0xa04e4efc, 0x54efab9c, 0xa03d9fc8,
+  0x54dcdc96, 0xa02cf444,
+  0x54ca0a4b, 0xa01c4c73, 0x54b734ba, 0xa00ba853, 0x54a45be6, 0x9ffb07e7,
+  0x54917fce, 0x9fea6b2f,
+  0x547ea073, 0x9fd9d22a, 0x546bbdd7, 0x9fc93cdb, 0x5458d7f9, 0x9fb8ab41,
+  0x5445eedb, 0x9fa81d5e,
+  0x5433027d, 0x9f979331, 0x542012e1, 0x9f870cbc, 0x540d2005, 0x9f7689ff,
+  0x53fa29ed, 0x9f660afb,
+  0x53e73097, 0x9f558fb0, 0x53d43406, 0x9f45181f, 0x53c13439, 0x9f34a449,
+  0x53ae3131, 0x9f24342f,
+  0x539b2af0, 0x9f13c7d0, 0x53882175, 0x9f035f2e, 0x537514c2, 0x9ef2fa49,
+  0x536204d7, 0x9ee29922,
+  0x534ef1b5, 0x9ed23bb9, 0x533bdb5d, 0x9ec1e210, 0x5328c1d0, 0x9eb18c26,
+  0x5315a50e, 0x9ea139fd,
+  0x53028518, 0x9e90eb94, 0x52ef61ee, 0x9e80a0ee, 0x52dc3b92, 0x9e705a09,
+  0x52c91204, 0x9e6016e8,
+  0x52b5e546, 0x9e4fd78a, 0x52a2b556, 0x9e3f9bf0, 0x528f8238, 0x9e2f641b,
+  0x527c4bea, 0x9e1f300b,
+  0x5269126e, 0x9e0effc1, 0x5255d5c5, 0x9dfed33e, 0x524295f0, 0x9deeaa82,
+  0x522f52ee, 0x9dde858e,
+  0x521c0cc2, 0x9dce6463, 0x5208c36a, 0x9dbe4701, 0x51f576ea, 0x9dae2d68,
+  0x51e22740, 0x9d9e179a,
+  0x51ced46e, 0x9d8e0597, 0x51bb7e75, 0x9d7df75f, 0x51a82555, 0x9d6decf4,
+  0x5194c910, 0x9d5de656,
+  0x518169a5, 0x9d4de385, 0x516e0715, 0x9d3de482, 0x515aa162, 0x9d2de94d,
+  0x5147388c, 0x9d1df1e9,
+  0x5133cc94, 0x9d0dfe54, 0x51205d7b, 0x9cfe0e8f, 0x510ceb40, 0x9cee229c,
+  0x50f975e6, 0x9cde3a7b,
+  0x50e5fd6d, 0x9cce562c, 0x50d281d5, 0x9cbe75b0, 0x50bf031f, 0x9cae9907,
+  0x50ab814d, 0x9c9ec033,
+  0x5097fc5e, 0x9c8eeb34, 0x50847454, 0x9c7f1a0a, 0x5070e92f, 0x9c6f4cb6,
+  0x505d5af1, 0x9c5f8339,
+  0x5049c999, 0x9c4fbd93, 0x50363529, 0x9c3ffbc5, 0x50229da1, 0x9c303dcf,
+  0x500f0302, 0x9c2083b3,
+  0x4ffb654d, 0x9c10cd70, 0x4fe7c483, 0x9c011b08, 0x4fd420a4, 0x9bf16c7a,
+  0x4fc079b1, 0x9be1c1c8,
+  0x4faccfab, 0x9bd21af3, 0x4f992293, 0x9bc277fa, 0x4f857269, 0x9bb2d8de,
+  0x4f71bf2e, 0x9ba33da0,
+  0x4f5e08e3, 0x9b93a641, 0x4f4a4f89, 0x9b8412c1, 0x4f369320, 0x9b748320,
+  0x4f22d3aa, 0x9b64f760,
+  0x4f0f1126, 0x9b556f81, 0x4efb4b96, 0x9b45eb83, 0x4ee782fb, 0x9b366b68,
+  0x4ed3b755, 0x9b26ef2f,
+  0x4ebfe8a5, 0x9b1776da, 0x4eac16eb, 0x9b080268, 0x4e984229, 0x9af891db,
+  0x4e846a60, 0x9ae92533,
+  0x4e708f8f, 0x9ad9bc71, 0x4e5cb1b9, 0x9aca5795, 0x4e48d0dd, 0x9abaf6a1,
+  0x4e34ecfc, 0x9aab9993,
+  0x4e210617, 0x9a9c406e, 0x4e0d1c30, 0x9a8ceb31, 0x4df92f46, 0x9a7d99de,
+  0x4de53f5a, 0x9a6e4c74,
+  0x4dd14c6e, 0x9a5f02f5, 0x4dbd5682, 0x9a4fbd61, 0x4da95d96, 0x9a407bb9,
+  0x4d9561ac, 0x9a313dfc,
+  0x4d8162c4, 0x9a22042d, 0x4d6d60df, 0x9a12ce4b, 0x4d595bfe, 0x9a039c57,
+  0x4d455422, 0x99f46e51,
+  0x4d31494b, 0x99e5443b, 0x4d1d3b7a, 0x99d61e14, 0x4d092ab0, 0x99c6fbde,
+  0x4cf516ee, 0x99b7dd99,
+  0x4ce10034, 0x99a8c345, 0x4ccce684, 0x9999ace3, 0x4cb8c9dd, 0x998a9a74,
+  0x4ca4aa41, 0x997b8bf8,
+  0x4c9087b1, 0x996c816f, 0x4c7c622d, 0x995d7adc, 0x4c6839b7, 0x994e783d,
+  0x4c540e4e, 0x993f7993,
+  0x4c3fdff4, 0x99307ee0, 0x4c2baea9, 0x99218824, 0x4c177a6e, 0x9912955f,
+  0x4c034345, 0x9903a691,
+  0x4bef092d, 0x98f4bbbc, 0x4bdacc28, 0x98e5d4e0, 0x4bc68c36, 0x98d6f1fe,
+  0x4bb24958, 0x98c81316,
+  0x4b9e0390, 0x98b93828, 0x4b89badd, 0x98aa6136, 0x4b756f40, 0x989b8e40,
+  0x4b6120bb, 0x988cbf46,
+  0x4b4ccf4d, 0x987df449, 0x4b387af9, 0x986f2d4a, 0x4b2423be, 0x98606a49,
+  0x4b0fc99d, 0x9851ab46,
+  0x4afb6c98, 0x9842f043, 0x4ae70caf, 0x98343940, 0x4ad2a9e2, 0x9825863d,
+  0x4abe4433, 0x9816d73b,
+  0x4aa9dba2, 0x98082c3b, 0x4a957030, 0x97f9853d, 0x4a8101de, 0x97eae242,
+  0x4a6c90ad, 0x97dc4349,
+  0x4a581c9e, 0x97cda855, 0x4a43a5b0, 0x97bf1165, 0x4a2f2be6, 0x97b07e7a,
+  0x4a1aaf3f, 0x97a1ef94,
+  0x4a062fbd, 0x979364b5, 0x49f1ad61, 0x9784dddc, 0x49dd282a, 0x97765b0a,
+  0x49c8a01b, 0x9767dc41,
+  0x49b41533, 0x9759617f, 0x499f8774, 0x974aeac6, 0x498af6df, 0x973c7817,
+  0x49766373, 0x972e0971,
+  0x4961cd33, 0x971f9ed7, 0x494d341e, 0x97113847, 0x49389836, 0x9702d5c3,
+  0x4923f97b, 0x96f4774b,
+  0x490f57ee, 0x96e61ce0, 0x48fab391, 0x96d7c682, 0x48e60c62, 0x96c97432,
+  0x48d16265, 0x96bb25f0,
+  0x48bcb599, 0x96acdbbe, 0x48a805ff, 0x969e959b, 0x48935397, 0x96905388,
+  0x487e9e64, 0x96821585,
+  0x4869e665, 0x9673db94, 0x48552b9b, 0x9665a5b4, 0x48406e08, 0x965773e7,
+  0x482badab, 0x9649462d,
+  0x4816ea86, 0x963b1c86, 0x48022499, 0x962cf6f2, 0x47ed5be6, 0x961ed574,
+  0x47d8906d, 0x9610b80a,
+  0x47c3c22f, 0x96029eb6, 0x47aef12c, 0x95f48977, 0x479a1d67, 0x95e67850,
+  0x478546de, 0x95d86b3f,
+  0x47706d93, 0x95ca6247, 0x475b9188, 0x95bc5d66, 0x4746b2bc, 0x95ae5c9f,
+  0x4731d131, 0x95a05ff0,
+  0x471cece7, 0x9592675c, 0x470805df, 0x958472e2, 0x46f31c1a, 0x95768283,
+  0x46de2f99, 0x9568963f,
+  0x46c9405c, 0x955aae17, 0x46b44e65, 0x954cca0c, 0x469f59b4, 0x953eea1e,
+  0x468a624a, 0x95310e4e,
+  0x46756828, 0x9523369c, 0x46606b4e, 0x95156308, 0x464b6bbe, 0x95079394,
+  0x46366978, 0x94f9c83f,
+  0x4621647d, 0x94ec010b, 0x460c5cce, 0x94de3df8, 0x45f7526b, 0x94d07f05,
+  0x45e24556, 0x94c2c435,
+  0x45cd358f, 0x94b50d87, 0x45b82318, 0x94a75afd, 0x45a30df0, 0x9499ac95,
+  0x458df619, 0x948c0252,
+  0x4578db93, 0x947e5c33, 0x4563be60, 0x9470ba39, 0x454e9e80, 0x94631c65,
+  0x45397bf4, 0x945582b7,
+  0x452456bd, 0x9447ed2f, 0x450f2edb, 0x943a5bcf, 0x44fa0450, 0x942cce96,
+  0x44e4d71c, 0x941f4585,
+  0x44cfa740, 0x9411c09e, 0x44ba74bd, 0x94043fdf, 0x44a53f93, 0x93f6c34a,
+  0x449007c4, 0x93e94adf,
+  0x447acd50, 0x93dbd6a0, 0x44659039, 0x93ce668b, 0x4450507e, 0x93c0faa3,
+  0x443b0e21, 0x93b392e6,
+  0x4425c923, 0x93a62f57, 0x44108184, 0x9398cff5, 0x43fb3746, 0x938b74c1,
+  0x43e5ea68, 0x937e1dbb,
+  0x43d09aed, 0x9370cae4, 0x43bb48d4, 0x93637c3d, 0x43a5f41e, 0x935631c5,
+  0x43909ccd, 0x9348eb7e,
+  0x437b42e1, 0x933ba968, 0x4365e65b, 0x932e6b84, 0x4350873c, 0x932131d1,
+  0x433b2585, 0x9313fc51,
+  0x4325c135, 0x9306cb04, 0x43105a50, 0x92f99deb, 0x42faf0d4, 0x92ec7505,
+  0x42e584c3, 0x92df5054,
+  0x42d0161e, 0x92d22fd9, 0x42baa4e6, 0x92c51392, 0x42a5311b, 0x92b7fb82,
+  0x428fbabe, 0x92aae7a8,
+  0x427a41d0, 0x929dd806, 0x4264c653, 0x9290cc9b, 0x424f4845, 0x9283c568,
+  0x4239c7aa, 0x9276c26d,
+  0x42244481, 0x9269c3ac, 0x420ebecb, 0x925cc924, 0x41f93689, 0x924fd2d7,
+  0x41e3abbc, 0x9242e0c4,
+  0x41ce1e65, 0x9235f2ec, 0x41b88e84, 0x9229094f, 0x41a2fc1a, 0x921c23ef,
+  0x418d6729, 0x920f42cb,
+  0x4177cfb1, 0x920265e4, 0x416235b2, 0x91f58d3b, 0x414c992f, 0x91e8b8d0,
+  0x4136fa27, 0x91dbe8a4,
+  0x4121589b, 0x91cf1cb6, 0x410bb48c, 0x91c25508, 0x40f60dfb, 0x91b5919a,
+  0x40e064ea, 0x91a8d26d,
+  0x40cab958, 0x919c1781, 0x40b50b46, 0x918f60d6, 0x409f5ab6, 0x9182ae6d,
+  0x4089a7a8, 0x91760047,
+  0x4073f21d, 0x91695663, 0x405e3a16, 0x915cb0c3, 0x40487f94, 0x91500f67,
+  0x4032c297, 0x91437250,
+  0x401d0321, 0x9136d97d, 0x40074132, 0x912a44f0, 0x3ff17cca, 0x911db4a9,
+  0x3fdbb5ec, 0x911128a8,
+  0x3fc5ec98, 0x9104a0ee, 0x3fb020ce, 0x90f81d7b, 0x3f9a5290, 0x90eb9e50,
+  0x3f8481dd, 0x90df236e,
+  0x3f6eaeb8, 0x90d2acd4, 0x3f58d921, 0x90c63a83, 0x3f430119, 0x90b9cc7d,
+  0x3f2d26a0, 0x90ad62c0,
+  0x3f1749b8, 0x90a0fd4e, 0x3f016a61, 0x90949c28, 0x3eeb889c, 0x90883f4d,
+  0x3ed5a46b, 0x907be6be,
+  0x3ebfbdcd, 0x906f927c, 0x3ea9d4c3, 0x90634287, 0x3e93e950, 0x9056f6df,
+  0x3e7dfb73, 0x904aaf86,
+  0x3e680b2c, 0x903e6c7b, 0x3e52187f, 0x90322dbf, 0x3e3c2369, 0x9025f352,
+  0x3e262bee, 0x9019bd36,
+  0x3e10320d, 0x900d8b69, 0x3dfa35c8, 0x90015dee, 0x3de4371f, 0x8ff534c4,
+  0x3dce3614, 0x8fe90fec,
+  0x3db832a6, 0x8fdcef66, 0x3da22cd7, 0x8fd0d333, 0x3d8c24a8, 0x8fc4bb53,
+  0x3d761a19, 0x8fb8a7c7,
+  0x3d600d2c, 0x8fac988f, 0x3d49fde1, 0x8fa08dab, 0x3d33ec39, 0x8f94871d,
+  0x3d1dd835, 0x8f8884e4,
+  0x3d07c1d6, 0x8f7c8701, 0x3cf1a91c, 0x8f708d75, 0x3cdb8e09, 0x8f649840,
+  0x3cc5709e, 0x8f58a761,
+  0x3caf50da, 0x8f4cbadb, 0x3c992ec0, 0x8f40d2ad, 0x3c830a50, 0x8f34eed8,
+  0x3c6ce38a, 0x8f290f5c,
+  0x3c56ba70, 0x8f1d343a, 0x3c408f03, 0x8f115d72, 0x3c2a6142, 0x8f058b04,
+  0x3c143130, 0x8ef9bcf2,
+  0x3bfdfecd, 0x8eedf33b, 0x3be7ca1a, 0x8ee22de0, 0x3bd19318, 0x8ed66ce1,
+  0x3bbb59c7, 0x8ecab040,
+  0x3ba51e29, 0x8ebef7fb, 0x3b8ee03e, 0x8eb34415, 0x3b78a007, 0x8ea7948c,
+  0x3b625d86, 0x8e9be963,
+  0x3b4c18ba, 0x8e904298, 0x3b35d1a5, 0x8e84a02d, 0x3b1f8848, 0x8e790222,
+  0x3b093ca3, 0x8e6d6877,
+  0x3af2eeb7, 0x8e61d32e, 0x3adc9e86, 0x8e564246, 0x3ac64c0f, 0x8e4ab5bf,
+  0x3aaff755, 0x8e3f2d9b,
+  0x3a99a057, 0x8e33a9da, 0x3a834717, 0x8e282a7b, 0x3a6ceb96, 0x8e1caf80,
+  0x3a568dd4, 0x8e1138ea,
+  0x3a402dd2, 0x8e05c6b7, 0x3a29cb91, 0x8dfa58ea, 0x3a136712, 0x8deeef82,
+  0x39fd0056, 0x8de38a80,
+  0x39e6975e, 0x8dd829e4, 0x39d02c2a, 0x8dcccdaf, 0x39b9bebc, 0x8dc175e0,
+  0x39a34f13, 0x8db6227a,
+  0x398cdd32, 0x8daad37b, 0x39766919, 0x8d9f88e5, 0x395ff2c9, 0x8d9442b8,
+  0x39497a43, 0x8d8900f3,
+  0x3932ff87, 0x8d7dc399, 0x391c8297, 0x8d728aa9, 0x39060373, 0x8d675623,
+  0x38ef821c, 0x8d5c2609,
+  0x38d8fe93, 0x8d50fa59, 0x38c278d9, 0x8d45d316, 0x38abf0ef, 0x8d3ab03f,
+  0x389566d6, 0x8d2f91d5,
+  0x387eda8e, 0x8d2477d8, 0x38684c19, 0x8d196249, 0x3851bb77, 0x8d0e5127,
+  0x383b28a9, 0x8d034474,
+  0x382493b0, 0x8cf83c30, 0x380dfc8d, 0x8ced385b, 0x37f76341, 0x8ce238f6,
+  0x37e0c7cc, 0x8cd73e01,
+  0x37ca2a30, 0x8ccc477d, 0x37b38a6d, 0x8cc1556a, 0x379ce885, 0x8cb667c8,
+  0x37864477, 0x8cab7e98,
+  0x376f9e46, 0x8ca099da, 0x3758f5f2, 0x8c95b98f, 0x37424b7b, 0x8c8addb7,
+  0x372b9ee3, 0x8c800652,
+  0x3714f02a, 0x8c753362, 0x36fe3f52, 0x8c6a64e5, 0x36e78c5b, 0x8c5f9ade,
+  0x36d0d746, 0x8c54d54c,
+  0x36ba2014, 0x8c4a142f, 0x36a366c6, 0x8c3f5788, 0x368cab5c, 0x8c349f58,
+  0x3675edd9, 0x8c29eb9f,
+  0x365f2e3b, 0x8c1f3c5d, 0x36486c86, 0x8c149192, 0x3631a8b8, 0x8c09eb40,
+  0x361ae2d3, 0x8bff4966,
+  0x36041ad9, 0x8bf4ac05, 0x35ed50c9, 0x8bea131e, 0x35d684a6, 0x8bdf7eb0,
+  0x35bfb66e, 0x8bd4eebc,
+  0x35a8e625, 0x8bca6343, 0x359213c9, 0x8bbfdc44, 0x357b3f5d, 0x8bb559c1,
+  0x356468e2, 0x8baadbba,
+  0x354d9057, 0x8ba0622f, 0x3536b5be, 0x8b95ed21, 0x351fd918, 0x8b8b7c8f,
+  0x3508fa66, 0x8b81107b,
+  0x34f219a8, 0x8b76a8e4, 0x34db36df, 0x8b6c45cc, 0x34c4520d, 0x8b61e733,
+  0x34ad6b32, 0x8b578d18,
+  0x34968250, 0x8b4d377c, 0x347f9766, 0x8b42e661, 0x3468aa76, 0x8b3899c6,
+  0x3451bb81, 0x8b2e51ab,
+  0x343aca87, 0x8b240e11, 0x3423d78a, 0x8b19cef8, 0x340ce28b, 0x8b0f9462,
+  0x33f5eb89, 0x8b055e4d,
+  0x33def287, 0x8afb2cbb, 0x33c7f785, 0x8af0ffac, 0x33b0fa84, 0x8ae6d720,
+  0x3399fb85, 0x8adcb318,
+  0x3382fa88, 0x8ad29394, 0x336bf78f, 0x8ac87894, 0x3354f29b, 0x8abe6219,
+  0x333debab, 0x8ab45024,
+  0x3326e2c3, 0x8aaa42b4, 0x330fd7e1, 0x8aa039cb, 0x32f8cb07, 0x8a963567,
+  0x32e1bc36, 0x8a8c358b,
+  0x32caab6f, 0x8a823a36, 0x32b398b3, 0x8a784368, 0x329c8402, 0x8a6e5123,
+  0x32856d5e, 0x8a646365,
+  0x326e54c7, 0x8a5a7a31, 0x32573a3f, 0x8a509585, 0x32401dc6, 0x8a46b564,
+  0x3228ff5c, 0x8a3cd9cc,
+  0x3211df04, 0x8a3302be, 0x31fabcbd, 0x8a29303b, 0x31e39889, 0x8a1f6243,
+  0x31cc7269, 0x8a1598d6,
+  0x31b54a5e, 0x8a0bd3f5, 0x319e2067, 0x8a0213a0, 0x3186f487, 0x89f857d8,
+  0x316fc6be, 0x89eea09d,
+  0x3158970e, 0x89e4edef, 0x31416576, 0x89db3fcf, 0x312a31f8, 0x89d1963c,
+  0x3112fc95, 0x89c7f138,
+  0x30fbc54d, 0x89be50c3, 0x30e48c22, 0x89b4b4dd, 0x30cd5115, 0x89ab1d87,
+  0x30b61426, 0x89a18ac0,
+  0x309ed556, 0x8997fc8a, 0x308794a6, 0x898e72e4, 0x30705217, 0x8984edcf,
+  0x30590dab, 0x897b6d4c,
+  0x3041c761, 0x8971f15a, 0x302a7f3a, 0x896879fb, 0x30133539, 0x895f072e,
+  0x2ffbe95d, 0x895598f3,
+  0x2fe49ba7, 0x894c2f4c, 0x2fcd4c19, 0x8942ca39, 0x2fb5fab2, 0x893969b9,
+  0x2f9ea775, 0x89300dce,
+  0x2f875262, 0x8926b677, 0x2f6ffb7a, 0x891d63b5, 0x2f58a2be, 0x89141589,
+  0x2f41482e, 0x890acbf2,
+  0x2f29ebcc, 0x890186f2, 0x2f128d99, 0x88f84687, 0x2efb2d95, 0x88ef0ab4,
+  0x2ee3cbc1, 0x88e5d378,
+  0x2ecc681e, 0x88dca0d3, 0x2eb502ae, 0x88d372c6, 0x2e9d9b70, 0x88ca4951,
+  0x2e863267, 0x88c12475,
+  0x2e6ec792, 0x88b80432, 0x2e575af3, 0x88aee888, 0x2e3fec8b, 0x88a5d177,
+  0x2e287c5a, 0x889cbf01,
+  0x2e110a62, 0x8893b125, 0x2df996a3, 0x888aa7e3, 0x2de2211e, 0x8881a33d,
+  0x2dcaa9d5, 0x8878a332,
+  0x2db330c7, 0x886fa7c2, 0x2d9bb5f6, 0x8866b0ef, 0x2d843964, 0x885dbeb8,
+  0x2d6cbb10, 0x8854d11e,
+  0x2d553afc, 0x884be821, 0x2d3db928, 0x884303c1, 0x2d263596, 0x883a23ff,
+  0x2d0eb046, 0x883148db,
+  0x2cf72939, 0x88287256, 0x2cdfa071, 0x881fa06f, 0x2cc815ee, 0x8816d327,
+  0x2cb089b1, 0x880e0a7f,
+  0x2c98fbba, 0x88054677, 0x2c816c0c, 0x87fc870f, 0x2c69daa6, 0x87f3cc48,
+  0x2c52478a, 0x87eb1621,
+  0x2c3ab2b9, 0x87e2649b, 0x2c231c33, 0x87d9b7b7, 0x2c0b83fa, 0x87d10f75,
+  0x2bf3ea0d, 0x87c86bd5,
+  0x2bdc4e6f, 0x87bfccd7, 0x2bc4b120, 0x87b7327d, 0x2bad1221, 0x87ae9cc5,
+  0x2b957173, 0x87a60bb1,
+  0x2b7dcf17, 0x879d7f41, 0x2b662b0e, 0x8794f774, 0x2b4e8558, 0x878c744d,
+  0x2b36ddf7, 0x8783f5ca,
+  0x2b1f34eb, 0x877b7bec, 0x2b078a36, 0x877306b4, 0x2aefddd8, 0x876a9621,
+  0x2ad82fd2, 0x87622a35,
+  0x2ac08026, 0x8759c2ef, 0x2aa8ced3, 0x87516050, 0x2a911bdc, 0x87490258,
+  0x2a796740, 0x8740a907,
+  0x2a61b101, 0x8738545e, 0x2a49f920, 0x8730045d, 0x2a323f9e, 0x8727b905,
+  0x2a1a847b, 0x871f7255,
+  0x2a02c7b8, 0x8717304e, 0x29eb0957, 0x870ef2f1, 0x29d34958, 0x8706ba3d,
+  0x29bb87bc, 0x86fe8633,
+  0x29a3c485, 0x86f656d3, 0x298bffb2, 0x86ee2c1e, 0x29743946, 0x86e60614,
+  0x295c7140, 0x86dde4b5,
+  0x2944a7a2, 0x86d5c802, 0x292cdc6d, 0x86cdaffa, 0x29150fa1, 0x86c59c9f,
+  0x28fd4140, 0x86bd8df0,
+  0x28e5714b, 0x86b583ee, 0x28cd9fc1, 0x86ad7e99, 0x28b5cca5, 0x86a57df2,
+  0x289df7f8, 0x869d81f8,
+  0x288621b9, 0x86958aac, 0x286e49ea, 0x868d980e, 0x2856708d, 0x8685aa20,
+  0x283e95a1, 0x867dc0e0,
+  0x2826b928, 0x8675dc4f, 0x280edb23, 0x866dfc6e, 0x27f6fb92, 0x8666213c,
+  0x27df1a77, 0x865e4abb,
+  0x27c737d3, 0x865678eb, 0x27af53a6, 0x864eabcb, 0x27976df1, 0x8646e35c,
+  0x277f86b5, 0x863f1f9e,
+  0x27679df4, 0x86376092, 0x274fb3ae, 0x862fa638, 0x2737c7e3, 0x8627f091,
+  0x271fda96, 0x86203f9c,
+  0x2707ebc7, 0x86189359, 0x26effb76, 0x8610ebca, 0x26d809a5, 0x860948ef,
+  0x26c01655, 0x8601aac7,
+  0x26a82186, 0x85fa1153, 0x26902b39, 0x85f27c93, 0x26783370, 0x85eaec88,
+  0x26603a2c, 0x85e36132,
+  0x26483f6c, 0x85dbda91, 0x26304333, 0x85d458a6, 0x26184581, 0x85ccdb70,
+  0x26004657, 0x85c562f1,
+  0x25e845b6, 0x85bdef28, 0x25d0439f, 0x85b68015, 0x25b84012, 0x85af15b9,
+  0x25a03b11, 0x85a7b015,
+  0x2588349d, 0x85a04f28, 0x25702cb7, 0x8598f2f3, 0x2558235f, 0x85919b76,
+  0x25401896, 0x858a48b1,
+  0x25280c5e, 0x8582faa5, 0x250ffeb7, 0x857bb152, 0x24f7efa2, 0x85746cb8,
+  0x24dfdf20, 0x856d2cd7,
+  0x24c7cd33, 0x8565f1b0, 0x24afb9da, 0x855ebb44, 0x2497a517, 0x85578991,
+  0x247f8eec, 0x85505c99,
+  0x24677758, 0x8549345c, 0x244f5e5c, 0x854210db, 0x243743fa, 0x853af214,
+  0x241f2833, 0x8533d809,
+  0x24070b08, 0x852cc2bb, 0x23eeec78, 0x8525b228, 0x23d6cc87, 0x851ea652,
+  0x23beab33, 0x85179f39,
+  0x23a6887f, 0x85109cdd, 0x238e646a, 0x85099f3e, 0x23763ef7, 0x8502a65c,
+  0x235e1826, 0x84fbb239,
+  0x2345eff8, 0x84f4c2d4, 0x232dc66d, 0x84edd82d, 0x23159b88, 0x84e6f244,
+  0x22fd6f48, 0x84e0111b,
+  0x22e541af, 0x84d934b1, 0x22cd12bd, 0x84d25d06, 0x22b4e274, 0x84cb8a1b,
+  0x229cb0d5, 0x84c4bbf0,
+  0x22847de0, 0x84bdf286, 0x226c4996, 0x84b72ddb, 0x225413f8, 0x84b06df2,
+  0x223bdd08, 0x84a9b2ca,
+  0x2223a4c5, 0x84a2fc62, 0x220b6b32, 0x849c4abd, 0x21f3304f, 0x84959dd9,
+  0x21daf41d, 0x848ef5b7,
+  0x21c2b69c, 0x84885258, 0x21aa77cf, 0x8481b3bb, 0x219237b5, 0x847b19e1,
+  0x2179f64f, 0x847484ca,
+  0x2161b3a0, 0x846df477, 0x21496fa7, 0x846768e7, 0x21312a65, 0x8460e21a,
+  0x2118e3dc, 0x845a6012,
+  0x21009c0c, 0x8453e2cf, 0x20e852f6, 0x844d6a50, 0x20d0089c, 0x8446f695,
+  0x20b7bcfe, 0x844087a0,
+  0x209f701c, 0x843a1d70, 0x208721f9, 0x8433b806, 0x206ed295, 0x842d5762,
+  0x205681f1, 0x8426fb84,
+  0x203e300d, 0x8420a46c, 0x2025dcec, 0x841a521a, 0x200d888d, 0x84140490,
+  0x1ff532f2, 0x840dbbcc,
+  0x1fdcdc1b, 0x840777d0, 0x1fc4840a, 0x8401389b, 0x1fac2abf, 0x83fafe2e,
+  0x1f93d03c, 0x83f4c889,
+  0x1f7b7481, 0x83ee97ad, 0x1f63178f, 0x83e86b99, 0x1f4ab968, 0x83e2444d,
+  0x1f325a0b, 0x83dc21cb,
+  0x1f19f97b, 0x83d60412, 0x1f0197b8, 0x83cfeb22, 0x1ee934c3, 0x83c9d6fc,
+  0x1ed0d09d, 0x83c3c7a0,
+  0x1eb86b46, 0x83bdbd0e, 0x1ea004c1, 0x83b7b746, 0x1e879d0d, 0x83b1b649,
+  0x1e6f342c, 0x83abba17,
+  0x1e56ca1e, 0x83a5c2b0, 0x1e3e5ee5, 0x839fd014, 0x1e25f282, 0x8399e244,
+  0x1e0d84f5, 0x8393f940,
+  0x1df5163f, 0x838e1507, 0x1ddca662, 0x8388359b, 0x1dc4355e, 0x83825afb,
+  0x1dabc334, 0x837c8528,
+  0x1d934fe5, 0x8376b422, 0x1d7adb73, 0x8370e7e9, 0x1d6265dd, 0x836b207d,
+  0x1d49ef26, 0x83655ddf,
+  0x1d31774d, 0x835fa00f, 0x1d18fe54, 0x8359e70d, 0x1d00843d, 0x835432d8,
+  0x1ce80906, 0x834e8373,
+  0x1ccf8cb3, 0x8348d8dc, 0x1cb70f43, 0x83433314, 0x1c9e90b8, 0x833d921b,
+  0x1c861113, 0x8337f5f1,
+  0x1c6d9053, 0x83325e97, 0x1c550e7c, 0x832ccc0d, 0x1c3c8b8c, 0x83273e52,
+  0x1c240786, 0x8321b568,
+  0x1c0b826a, 0x831c314e, 0x1bf2fc3a, 0x8316b205, 0x1bda74f6, 0x8311378d,
+  0x1bc1ec9e, 0x830bc1e6,
+  0x1ba96335, 0x83065110, 0x1b90d8bb, 0x8300e50b, 0x1b784d30, 0x82fb7dd8,
+  0x1b5fc097, 0x82f61b77,
+  0x1b4732ef, 0x82f0bde8, 0x1b2ea43a, 0x82eb652b, 0x1b161479, 0x82e61141,
+  0x1afd83ad, 0x82e0c22a,
+  0x1ae4f1d6, 0x82db77e5, 0x1acc5ef6, 0x82d63274, 0x1ab3cb0d, 0x82d0f1d5,
+  0x1a9b361d, 0x82cbb60b,
+  0x1a82a026, 0x82c67f14, 0x1a6a0929, 0x82c14cf1, 0x1a517128, 0x82bc1fa2,
+  0x1a38d823, 0x82b6f727,
+  0x1a203e1b, 0x82b1d381, 0x1a07a311, 0x82acb4b0, 0x19ef0707, 0x82a79ab3,
+  0x19d669fc, 0x82a2858c,
+  0x19bdcbf3, 0x829d753a, 0x19a52ceb, 0x829869be, 0x198c8ce7, 0x82936317,
+  0x1973ebe6, 0x828e6146,
+  0x195b49ea, 0x8289644b, 0x1942a6f3, 0x82846c26, 0x192a0304, 0x827f78d8,
+  0x19115e1c, 0x827a8a61,
+  0x18f8b83c, 0x8275a0c0, 0x18e01167, 0x8270bbf7, 0x18c7699b, 0x826bdc04,
+  0x18aec0db, 0x826700e9,
+  0x18961728, 0x82622aa6, 0x187d6c82, 0x825d593a, 0x1864c0ea, 0x82588ca7,
+  0x184c1461, 0x8253c4eb,
+  0x183366e9, 0x824f0208, 0x181ab881, 0x824a43fe, 0x1802092c, 0x82458acc,
+  0x17e958ea, 0x8240d673,
+  0x17d0a7bc, 0x823c26f3, 0x17b7f5a3, 0x82377c4c, 0x179f429f, 0x8232d67f,
+  0x17868eb3, 0x822e358b,
+  0x176dd9de, 0x82299971, 0x17552422, 0x82250232, 0x173c6d80, 0x82206fcc,
+  0x1723b5f9, 0x821be240,
+  0x170afd8d, 0x82175990, 0x16f2443e, 0x8212d5b9, 0x16d98a0c, 0x820e56be,
+  0x16c0cef9, 0x8209dc9e,
+  0x16a81305, 0x82056758, 0x168f5632, 0x8200f6ef, 0x1676987f, 0x81fc8b60,
+  0x165dd9f0, 0x81f824ae,
+  0x16451a83, 0x81f3c2d7, 0x162c5a3b, 0x81ef65dc, 0x16139918, 0x81eb0dbe,
+  0x15fad71b, 0x81e6ba7c,
+  0x15e21445, 0x81e26c16, 0x15c95097, 0x81de228d, 0x15b08c12, 0x81d9dde1,
+  0x1597c6b7, 0x81d59e13,
+  0x157f0086, 0x81d16321, 0x15663982, 0x81cd2d0c, 0x154d71aa, 0x81c8fbd6,
+  0x1534a901, 0x81c4cf7d,
+  0x151bdf86, 0x81c0a801, 0x1503153a, 0x81bc8564, 0x14ea4a1f, 0x81b867a5,
+  0x14d17e36, 0x81b44ec4,
+  0x14b8b17f, 0x81b03ac2, 0x149fe3fc, 0x81ac2b9e, 0x148715ae, 0x81a82159,
+  0x146e4694, 0x81a41bf4,
+  0x145576b1, 0x81a01b6d, 0x143ca605, 0x819c1fc5, 0x1423d492, 0x819828fd,
+  0x140b0258, 0x81943715,
+  0x13f22f58, 0x81904a0c, 0x13d95b93, 0x818c61e3, 0x13c0870a, 0x81887e9a,
+  0x13a7b1bf, 0x8184a032,
+  0x138edbb1, 0x8180c6a9, 0x137604e2, 0x817cf201, 0x135d2d53, 0x8179223a,
+  0x13445505, 0x81755754,
+  0x132b7bf9, 0x8171914e, 0x1312a230, 0x816dd02a, 0x12f9c7aa, 0x816a13e6,
+  0x12e0ec6a, 0x81665c84,
+  0x12c8106f, 0x8162aa04, 0x12af33ba, 0x815efc65, 0x1296564d, 0x815b53a8,
+  0x127d7829, 0x8157afcd,
+  0x1264994e, 0x815410d4, 0x124bb9be, 0x815076bd, 0x1232d979, 0x814ce188,
+  0x1219f880, 0x81495136,
+  0x120116d5, 0x8145c5c7, 0x11e83478, 0x81423f3a, 0x11cf516a, 0x813ebd90,
+  0x11b66dad, 0x813b40ca,
+  0x119d8941, 0x8137c8e6, 0x1184a427, 0x813455e6, 0x116bbe60, 0x8130e7c9,
+  0x1152d7ed, 0x812d7e8f,
+  0x1139f0cf, 0x812a1a3a, 0x11210907, 0x8126bac8, 0x11082096, 0x8123603a,
+  0x10ef377d, 0x81200a90,
+  0x10d64dbd, 0x811cb9ca, 0x10bd6356, 0x81196de9, 0x10a4784b, 0x811626ec,
+  0x108b8c9b, 0x8112e4d4,
+  0x1072a048, 0x810fa7a0, 0x1059b352, 0x810c6f52, 0x1040c5bb, 0x81093be8,
+  0x1027d784, 0x81060d63,
+  0x100ee8ad, 0x8102e3c4, 0xff5f938, 0x80ffbf0a, 0xfdd0926, 0x80fc9f35,
+  0xfc41876, 0x80f98446,
+  0xfab272b, 0x80f66e3c, 0xf923546, 0x80f35d19, 0xf7942c7, 0x80f050db,
+  0xf604faf, 0x80ed4984,
+  0xf475bff, 0x80ea4712, 0xf2e67b8, 0x80e74987, 0xf1572dc, 0x80e450e2,
+  0xefc7d6b, 0x80e15d24,
+  0xee38766, 0x80de6e4c, 0xeca90ce, 0x80db845b, 0xeb199a4, 0x80d89f51,
+  0xe98a1e9, 0x80d5bf2e,
+  0xe7fa99e, 0x80d2e3f2, 0xe66b0c3, 0x80d00d9d, 0xe4db75b, 0x80cd3c2f,
+  0xe34bd66, 0x80ca6fa9,
+  0xe1bc2e4, 0x80c7a80a, 0xe02c7d7, 0x80c4e553, 0xde9cc40, 0x80c22784,
+  0xdd0d01f, 0x80bf6e9c,
+  0xdb7d376, 0x80bcba9d, 0xd9ed646, 0x80ba0b85, 0xd85d88f, 0x80b76156,
+  0xd6cda53, 0x80b4bc0e,
+  0xd53db92, 0x80b21baf, 0xd3adc4e, 0x80af8039, 0xd21dc87, 0x80ace9ab,
+  0xd08dc3f, 0x80aa5806,
+  0xcefdb76, 0x80a7cb49, 0xcd6da2d, 0x80a54376, 0xcbdd865, 0x80a2c08b,
+  0xca4d620, 0x80a04289,
+  0xc8bd35e, 0x809dc971, 0xc72d020, 0x809b5541, 0xc59cc68, 0x8098e5fb,
+  0xc40c835, 0x80967b9f,
+  0xc27c389, 0x8094162c, 0xc0ebe66, 0x8091b5a2, 0xbf5b8cb, 0x808f5a02,
+  0xbdcb2bb, 0x808d034c,
+  0xbc3ac35, 0x808ab180, 0xbaaa53b, 0x8088649e, 0xb919dcf, 0x80861ca6,
+  0xb7895f0, 0x8083d998,
+  0xb5f8d9f, 0x80819b74, 0xb4684df, 0x807f623b, 0xb2d7baf, 0x807d2dec,
+  0xb147211, 0x807afe87,
+  0xafb6805, 0x8078d40d, 0xae25d8d, 0x8076ae7e, 0xac952aa, 0x80748dd9,
+  0xab0475c, 0x8072721f,
+  0xa973ba5, 0x80705b50, 0xa7e2f85, 0x806e496c, 0xa6522fe, 0x806c3c74,
+  0xa4c1610, 0x806a3466,
+  0xa3308bd, 0x80683143, 0xa19fb04, 0x8066330c, 0xa00ece8, 0x806439c0,
+  0x9e7de6a, 0x80624560,
+  0x9cecf89, 0x806055eb, 0x9b5c048, 0x805e6b62, 0x99cb0a7, 0x805c85c4,
+  0x983a0a7, 0x805aa512,
+  0x96a9049, 0x8058c94c, 0x9517f8f, 0x8056f272, 0x9386e78, 0x80552084,
+  0x91f5d06, 0x80535381,
+  0x9064b3a, 0x80518b6b, 0x8ed3916, 0x804fc841, 0x8d42699, 0x804e0a04,
+  0x8bb13c5, 0x804c50b2,
+  0x8a2009a, 0x804a9c4d, 0x888ed1b, 0x8048ecd5, 0x86fd947, 0x80474248,
+  0x856c520, 0x80459ca9,
+  0x83db0a7, 0x8043fbf6, 0x8249bdd, 0x80426030, 0x80b86c2, 0x8040c956,
+  0x7f27157, 0x803f376a,
+  0x7d95b9e, 0x803daa6a, 0x7c04598, 0x803c2257, 0x7a72f45, 0x803a9f31,
+  0x78e18a7, 0x803920f8,
+  0x77501be, 0x8037a7ac, 0x75bea8c, 0x8036334e, 0x742d311, 0x8034c3dd,
+  0x729bb4e, 0x80335959,
+  0x710a345, 0x8031f3c2, 0x6f78af6, 0x80309318, 0x6de7262, 0x802f375d,
+  0x6c5598a, 0x802de08e,
+  0x6ac406f, 0x802c8ead, 0x6932713, 0x802b41ba, 0x67a0d76, 0x8029f9b4,
+  0x660f398, 0x8028b69c,
+  0x647d97c, 0x80277872, 0x62ebf22, 0x80263f36, 0x615a48b, 0x80250ae7,
+  0x5fc89b8, 0x8023db86,
+  0x5e36ea9, 0x8022b114, 0x5ca5361, 0x80218b8f, 0x5b137df, 0x80206af8,
+  0x5981c26, 0x801f4f4f,
+  0x57f0035, 0x801e3895, 0x565e40d, 0x801d26c8, 0x54cc7b1, 0x801c19ea,
+  0x533ab20, 0x801b11fa,
+  0x51a8e5c, 0x801a0ef8, 0x5017165, 0x801910e4, 0x4e8543e, 0x801817bf,
+  0x4cf36e5, 0x80172388,
+  0x4b6195d, 0x80163440, 0x49cfba7, 0x801549e6, 0x483ddc3, 0x8014647b,
+  0x46abfb3, 0x801383fe,
+  0x451a177, 0x8012a86f, 0x4388310, 0x8011d1d0, 0x41f6480, 0x8011001f,
+  0x40645c7, 0x8010335c,
+  0x3ed26e6, 0x800f6b88, 0x3d407df, 0x800ea8a3, 0x3bae8b2, 0x800deaad,
+  0x3a1c960, 0x800d31a5,
+  0x388a9ea, 0x800c7d8c, 0x36f8a51, 0x800bce63, 0x3566a96, 0x800b2427,
+  0x33d4abb, 0x800a7edb,
+  0x3242abf, 0x8009de7e, 0x30b0aa4, 0x80094310, 0x2f1ea6c, 0x8008ac90,
+  0x2d8ca16, 0x80081b00,
+  0x2bfa9a4, 0x80078e5e, 0x2a68917, 0x800706ac, 0x28d6870, 0x800683e8,
+  0x27447b0, 0x80060614,
+  0x25b26d7, 0x80058d2f, 0x24205e8, 0x80051939, 0x228e4e2, 0x8004aa32,
+  0x20fc3c6, 0x8004401a,
+  0x1f6a297, 0x8003daf1, 0x1dd8154, 0x80037ab7, 0x1c45ffe, 0x80031f6d,
+  0x1ab3e97, 0x8002c912,
+  0x1921d20, 0x800277a6, 0x178fb99, 0x80022b29, 0x15fda03, 0x8001e39b,
+  0x146b860, 0x8001a0fd,
+  0x12d96b1, 0x8001634e, 0x11474f6, 0x80012a8e, 0xfb5330, 0x8000f6bd,
+  0xe23160, 0x8000c7dc,
+  0xc90f88, 0x80009dea, 0xafeda8, 0x800078e7, 0x96cbc1, 0x800058d4, 0x7da9d4,
+  0x80003daf,
+  0x6487e3, 0x8000277a, 0x4b65ee, 0x80001635, 0x3243f5, 0x800009df, 0x1921fb,
+  0x80000278,
+};
+
+/**   
+* \par   
+* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
   
+* \par   
+* C command to generate the table   
+* 
   
+* for(i = 0; i< N; i++)   
+* {   
+*   cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+* } 
   
+* \par   
+* where N is the number of factors to generate and c is pi/(2*N)   
+* \par   
+* Then converted to q31 format by multiplying with 2^31 and saturated if required.   
+*/
+
+
+static const q31_t cos_factorsQ31_128[128] = {
+  0x7fff6216, 0x7ffa72d1, 0x7ff09478, 0x7fe1c76b, 0x7fce0c3e, 0x7fb563b3,
+  0x7f97cebd, 0x7f754e80,
+  0x7f4de451, 0x7f2191b4, 0x7ef05860, 0x7eba3a39, 0x7e7f3957, 0x7e3f57ff,
+  0x7dfa98a8, 0x7db0fdf8,
+  0x7d628ac6, 0x7d0f4218, 0x7cb72724, 0x7c5a3d50, 0x7bf88830, 0x7b920b89,
+  0x7b26cb4f, 0x7ab6cba4,
+  0x7a4210d8, 0x79c89f6e, 0x794a7c12, 0x78c7aba2, 0x78403329, 0x77b417df,
+  0x77235f2d, 0x768e0ea6,
+  0x75f42c0b, 0x7555bd4c, 0x74b2c884, 0x740b53fb, 0x735f6626, 0x72af05a7,
+  0x71fa3949, 0x71410805,
+  0x708378ff, 0x6fc19385, 0x6efb5f12, 0x6e30e34a, 0x6d6227fa, 0x6c8f351c,
+  0x6bb812d1, 0x6adcc964,
+  0x69fd614a, 0x6919e320, 0x683257ab, 0x6746c7d8, 0x66573cbb, 0x6563bf92,
+  0x646c59bf, 0x637114cc,
+  0x6271fa69, 0x616f146c, 0x60686ccf, 0x5f5e0db3, 0x5e50015d, 0x5d3e5237,
+  0x5c290acc, 0x5b1035cf,
+  0x59f3de12, 0x58d40e8c, 0x57b0d256, 0x568a34a9, 0x556040e2, 0x5433027d,
+  0x53028518, 0x51ced46e,
+  0x5097fc5e, 0x4f5e08e3, 0x4e210617, 0x4ce10034, 0x4b9e0390, 0x4a581c9e,
+  0x490f57ee, 0x47c3c22f,
+  0x46756828, 0x452456bd, 0x43d09aed, 0x427a41d0, 0x4121589b, 0x3fc5ec98,
+  0x3e680b2c, 0x3d07c1d6,
+  0x3ba51e29, 0x3a402dd2, 0x38d8fe93, 0x376f9e46, 0x36041ad9, 0x34968250,
+  0x3326e2c3, 0x31b54a5e,
+  0x3041c761, 0x2ecc681e, 0x2d553afc, 0x2bdc4e6f, 0x2a61b101, 0x28e5714b,
+  0x27679df4, 0x25e845b6,
+  0x24677758, 0x22e541af, 0x2161b3a0, 0x1fdcdc1b, 0x1e56ca1e, 0x1ccf8cb3,
+  0x1b4732ef, 0x19bdcbf3,
+  0x183366e9, 0x16a81305, 0x151bdf86, 0x138edbb1, 0x120116d5, 0x1072a048,
+  0xee38766, 0xd53db92,
+  0xbc3ac35, 0xa3308bd, 0x8a2009a, 0x710a345, 0x57f0035, 0x3ed26e6, 0x25b26d7,
+  0xc90f88,
+};
+
+static const q31_t cos_factorsQ31_512[512] = {
+  0x7ffff621, 0x7fffa72c, 0x7fff0943, 0x7ffe1c65, 0x7ffce093, 0x7ffb55ce,
+  0x7ff97c18, 0x7ff75370,
+  0x7ff4dbd9, 0x7ff21553, 0x7feeffe1, 0x7feb9b85, 0x7fe7e841, 0x7fe3e616,
+  0x7fdf9508, 0x7fdaf519,
+  0x7fd6064c, 0x7fd0c8a3, 0x7fcb3c23, 0x7fc560cf, 0x7fbf36aa, 0x7fb8bdb8,
+  0x7fb1f5fc, 0x7faadf7c,
+  0x7fa37a3c, 0x7f9bc640, 0x7f93c38c, 0x7f8b7227, 0x7f82d214, 0x7f79e35a,
+  0x7f70a5fe, 0x7f671a05,
+  0x7f5d3f75, 0x7f531655, 0x7f489eaa, 0x7f3dd87c, 0x7f32c3d1, 0x7f2760af,
+  0x7f1baf1e, 0x7f0faf25,
+  0x7f0360cb, 0x7ef6c418, 0x7ee9d914, 0x7edc9fc6, 0x7ecf1837, 0x7ec14270,
+  0x7eb31e78, 0x7ea4ac58,
+  0x7e95ec1a, 0x7e86ddc6, 0x7e778166, 0x7e67d703, 0x7e57dea7, 0x7e47985b,
+  0x7e37042a, 0x7e26221f,
+  0x7e14f242, 0x7e0374a0, 0x7df1a942, 0x7ddf9034, 0x7dcd2981, 0x7dba7534,
+  0x7da77359, 0x7d9423fc,
+  0x7d808728, 0x7d6c9ce9, 0x7d58654d, 0x7d43e05e, 0x7d2f0e2b, 0x7d19eebf,
+  0x7d048228, 0x7ceec873,
+  0x7cd8c1ae, 0x7cc26de5, 0x7cabcd28, 0x7c94df83, 0x7c7da505, 0x7c661dbc,
+  0x7c4e49b7, 0x7c362904,
+  0x7c1dbbb3, 0x7c0501d2, 0x7bebfb70, 0x7bd2a89e, 0x7bb9096b, 0x7b9f1de6,
+  0x7b84e61f, 0x7b6a6227,
+  0x7b4f920e, 0x7b3475e5, 0x7b190dbc, 0x7afd59a4, 0x7ae159ae, 0x7ac50dec,
+  0x7aa8766f, 0x7a8b9348,
+  0x7a6e648a, 0x7a50ea47, 0x7a332490, 0x7a151378, 0x79f6b711, 0x79d80f6f,
+  0x79b91ca4, 0x7999dec4,
+  0x797a55e0, 0x795a820e, 0x793a6361, 0x7919f9ec, 0x78f945c3, 0x78d846fb,
+  0x78b6fda8, 0x789569df,
+  0x78738bb3, 0x7851633b, 0x782ef08b, 0x780c33b8, 0x77e92cd9, 0x77c5dc01,
+  0x77a24148, 0x777e5cc3,
+  0x775a2e89, 0x7735b6af, 0x7710f54c, 0x76ebea77, 0x76c69647, 0x76a0f8d2,
+  0x767b1231, 0x7654e279,
+  0x762e69c4, 0x7607a828, 0x75e09dbd, 0x75b94a9c, 0x7591aedd, 0x7569ca99,
+  0x75419de7, 0x751928e0,
+  0x74f06b9e, 0x74c7663a, 0x749e18cd, 0x74748371, 0x744aa63f, 0x74208150,
+  0x73f614c0, 0x73cb60a8,
+  0x73a06522, 0x73752249, 0x73499838, 0x731dc70a, 0x72f1aed9, 0x72c54fc1,
+  0x7298a9dd, 0x726bbd48,
+  0x723e8a20, 0x7211107e, 0x71e35080, 0x71b54a41, 0x7186fdde, 0x71586b74,
+  0x7129931f, 0x70fa74fc,
+  0x70cb1128, 0x709b67c0, 0x706b78e3, 0x703b44ad, 0x700acb3c, 0x6fda0cae,
+  0x6fa90921, 0x6f77c0b3,
+  0x6f463383, 0x6f1461b0, 0x6ee24b57, 0x6eaff099, 0x6e7d5193, 0x6e4a6e66,
+  0x6e174730, 0x6de3dc11,
+  0x6db02d29, 0x6d7c3a98, 0x6d48047e, 0x6d138afb, 0x6cdece2f, 0x6ca9ce3b,
+  0x6c748b3f, 0x6c3f055d,
+  0x6c093cb6, 0x6bd3316a, 0x6b9ce39b, 0x6b66536b, 0x6b2f80fb, 0x6af86c6c,
+  0x6ac115e2, 0x6a897d7d,
+  0x6a51a361, 0x6a1987b0, 0x69e12a8c, 0x69a88c19, 0x696fac78, 0x69368bce,
+  0x68fd2a3d, 0x68c387e9,
+  0x6889a4f6, 0x684f8186, 0x68151dbe, 0x67da79c3, 0x679f95b7, 0x676471c0,
+  0x67290e02, 0x66ed6aa1,
+  0x66b187c3, 0x6675658c, 0x66390422, 0x65fc63a9, 0x65bf8447, 0x65826622,
+  0x6545095f, 0x65076e25,
+  0x64c99498, 0x648b7ce0, 0x644d2722, 0x640e9386, 0x63cfc231, 0x6390b34a,
+  0x635166f9, 0x6311dd64,
+  0x62d216b3, 0x6292130c, 0x6251d298, 0x6211557e, 0x61d09be5, 0x618fa5f7,
+  0x614e73da, 0x610d05b7,
+  0x60cb5bb7, 0x60897601, 0x604754bf, 0x6004f819, 0x5fc26038, 0x5f7f8d46,
+  0x5f3c7f6b, 0x5ef936d1,
+  0x5eb5b3a2, 0x5e71f606, 0x5e2dfe29, 0x5de9cc33, 0x5da5604f, 0x5d60baa7,
+  0x5d1bdb65, 0x5cd6c2b5,
+  0x5c9170bf, 0x5c4be5b0, 0x5c0621b2, 0x5bc024f0, 0x5b79ef96, 0x5b3381ce,
+  0x5aecdbc5, 0x5aa5fda5,
+  0x5a5ee79a, 0x5a1799d1, 0x59d01475, 0x598857b2, 0x594063b5, 0x58f838a9,
+  0x58afd6bd, 0x58673e1b,
+  0x581e6ef1, 0x57d5696d, 0x578c2dba, 0x5742bc06, 0x56f9147e, 0x56af3750,
+  0x566524aa, 0x561adcb9,
+  0x55d05faa, 0x5585adad, 0x553ac6ee, 0x54efab9c, 0x54a45be6, 0x5458d7f9,
+  0x540d2005, 0x53c13439,
+  0x537514c2, 0x5328c1d0, 0x52dc3b92, 0x528f8238, 0x524295f0, 0x51f576ea,
+  0x51a82555, 0x515aa162,
+  0x510ceb40, 0x50bf031f, 0x5070e92f, 0x50229da1, 0x4fd420a4, 0x4f857269,
+  0x4f369320, 0x4ee782fb,
+  0x4e984229, 0x4e48d0dd, 0x4df92f46, 0x4da95d96, 0x4d595bfe, 0x4d092ab0,
+  0x4cb8c9dd, 0x4c6839b7,
+  0x4c177a6e, 0x4bc68c36, 0x4b756f40, 0x4b2423be, 0x4ad2a9e2, 0x4a8101de,
+  0x4a2f2be6, 0x49dd282a,
+  0x498af6df, 0x49389836, 0x48e60c62, 0x48935397, 0x48406e08, 0x47ed5be6,
+  0x479a1d67, 0x4746b2bc,
+  0x46f31c1a, 0x469f59b4, 0x464b6bbe, 0x45f7526b, 0x45a30df0, 0x454e9e80,
+  0x44fa0450, 0x44a53f93,
+  0x4450507e, 0x43fb3746, 0x43a5f41e, 0x4350873c, 0x42faf0d4, 0x42a5311b,
+  0x424f4845, 0x41f93689,
+  0x41a2fc1a, 0x414c992f, 0x40f60dfb, 0x409f5ab6, 0x40487f94, 0x3ff17cca,
+  0x3f9a5290, 0x3f430119,
+  0x3eeb889c, 0x3e93e950, 0x3e3c2369, 0x3de4371f, 0x3d8c24a8, 0x3d33ec39,
+  0x3cdb8e09, 0x3c830a50,
+  0x3c2a6142, 0x3bd19318, 0x3b78a007, 0x3b1f8848, 0x3ac64c0f, 0x3a6ceb96,
+  0x3a136712, 0x39b9bebc,
+  0x395ff2c9, 0x39060373, 0x38abf0ef, 0x3851bb77, 0x37f76341, 0x379ce885,
+  0x37424b7b, 0x36e78c5b,
+  0x368cab5c, 0x3631a8b8, 0x35d684a6, 0x357b3f5d, 0x351fd918, 0x34c4520d,
+  0x3468aa76, 0x340ce28b,
+  0x33b0fa84, 0x3354f29b, 0x32f8cb07, 0x329c8402, 0x32401dc6, 0x31e39889,
+  0x3186f487, 0x312a31f8,
+  0x30cd5115, 0x30705217, 0x30133539, 0x2fb5fab2, 0x2f58a2be, 0x2efb2d95,
+  0x2e9d9b70, 0x2e3fec8b,
+  0x2de2211e, 0x2d843964, 0x2d263596, 0x2cc815ee, 0x2c69daa6, 0x2c0b83fa,
+  0x2bad1221, 0x2b4e8558,
+  0x2aefddd8, 0x2a911bdc, 0x2a323f9e, 0x29d34958, 0x29743946, 0x29150fa1,
+  0x28b5cca5, 0x2856708d,
+  0x27f6fb92, 0x27976df1, 0x2737c7e3, 0x26d809a5, 0x26783370, 0x26184581,
+  0x25b84012, 0x2558235f,
+  0x24f7efa2, 0x2497a517, 0x243743fa, 0x23d6cc87, 0x23763ef7, 0x23159b88,
+  0x22b4e274, 0x225413f8,
+  0x21f3304f, 0x219237b5, 0x21312a65, 0x20d0089c, 0x206ed295, 0x200d888d,
+  0x1fac2abf, 0x1f4ab968,
+  0x1ee934c3, 0x1e879d0d, 0x1e25f282, 0x1dc4355e, 0x1d6265dd, 0x1d00843d,
+  0x1c9e90b8, 0x1c3c8b8c,
+  0x1bda74f6, 0x1b784d30, 0x1b161479, 0x1ab3cb0d, 0x1a517128, 0x19ef0707,
+  0x198c8ce7, 0x192a0304,
+  0x18c7699b, 0x1864c0ea, 0x1802092c, 0x179f429f, 0x173c6d80, 0x16d98a0c,
+  0x1676987f, 0x16139918,
+  0x15b08c12, 0x154d71aa, 0x14ea4a1f, 0x148715ae, 0x1423d492, 0x13c0870a,
+  0x135d2d53, 0x12f9c7aa,
+  0x1296564d, 0x1232d979, 0x11cf516a, 0x116bbe60, 0x11082096, 0x10a4784b,
+  0x1040c5bb, 0xfdd0926,
+  0xf7942c7, 0xf1572dc, 0xeb199a4, 0xe4db75b, 0xde9cc40, 0xd85d88f, 0xd21dc87,
+  0xcbdd865,
+  0xc59cc68, 0xbf5b8cb, 0xb919dcf, 0xb2d7baf, 0xac952aa, 0xa6522fe, 0xa00ece8,
+  0x99cb0a7,
+  0x9386e78, 0x8d42699, 0x86fd947, 0x80b86c2, 0x7a72f45, 0x742d311, 0x6de7262,
+  0x67a0d76,
+  0x615a48b, 0x5b137df, 0x54cc7b1, 0x4e8543e, 0x483ddc3, 0x41f6480, 0x3bae8b2,
+  0x3566a96,
+  0x2f1ea6c, 0x28d6870, 0x228e4e2, 0x1c45ffe, 0x15fda03, 0xfb5330, 0x96cbc1,
+  0x3243f5,
+};
+
+static const q31_t cos_factorsQ31_2048[2048] = {
+  0x7fffff62, 0x7ffffa73, 0x7ffff094, 0x7fffe1c6, 0x7fffce09, 0x7fffb55c,
+  0x7fff97c1, 0x7fff7536,
+  0x7fff4dbb, 0x7fff2151, 0x7ffeeff8, 0x7ffeb9b0, 0x7ffe7e79, 0x7ffe3e52,
+  0x7ffdf93c, 0x7ffdaf37,
+  0x7ffd6042, 0x7ffd0c5f, 0x7ffcb38c, 0x7ffc55ca, 0x7ffbf319, 0x7ffb8b78,
+  0x7ffb1ee9, 0x7ffaad6a,
+  0x7ffa36fc, 0x7ff9bba0, 0x7ff93b54, 0x7ff8b619, 0x7ff82bef, 0x7ff79cd6,
+  0x7ff708ce, 0x7ff66fd7,
+  0x7ff5d1f1, 0x7ff52f1d, 0x7ff48759, 0x7ff3daa6, 0x7ff32905, 0x7ff27275,
+  0x7ff1b6f6, 0x7ff0f688,
+  0x7ff0312c, 0x7fef66e1, 0x7fee97a7, 0x7fedc37e, 0x7fecea67, 0x7fec0c62,
+  0x7feb296d, 0x7fea418b,
+  0x7fe954ba, 0x7fe862fa, 0x7fe76c4c, 0x7fe670b0, 0x7fe57025, 0x7fe46aac,
+  0x7fe36045, 0x7fe250ef,
+  0x7fe13cac, 0x7fe0237a, 0x7fdf055a, 0x7fdde24d, 0x7fdcba51, 0x7fdb8d67,
+  0x7fda5b8f, 0x7fd924ca,
+  0x7fd7e917, 0x7fd6a875, 0x7fd562e7, 0x7fd4186a, 0x7fd2c900, 0x7fd174a8,
+  0x7fd01b63, 0x7fcebd31,
+  0x7fcd5a11, 0x7fcbf203, 0x7fca8508, 0x7fc91320, 0x7fc79c4b, 0x7fc62089,
+  0x7fc49fda, 0x7fc31a3d,
+  0x7fc18fb4, 0x7fc0003e, 0x7fbe6bdb, 0x7fbcd28b, 0x7fbb344e, 0x7fb99125,
+  0x7fb7e90f, 0x7fb63c0d,
+  0x7fb48a1e, 0x7fb2d343, 0x7fb1177b, 0x7faf56c7, 0x7fad9127, 0x7fabc69b,
+  0x7fa9f723, 0x7fa822bf,
+  0x7fa6496e, 0x7fa46b32, 0x7fa2880b, 0x7fa09ff7, 0x7f9eb2f8, 0x7f9cc10d,
+  0x7f9aca37, 0x7f98ce76,
+  0x7f96cdc9, 0x7f94c831, 0x7f92bdad, 0x7f90ae3f, 0x7f8e99e6, 0x7f8c80a1,
+  0x7f8a6272, 0x7f883f58,
+  0x7f861753, 0x7f83ea64, 0x7f81b88a, 0x7f7f81c6, 0x7f7d4617, 0x7f7b057e,
+  0x7f78bffb, 0x7f76758e,
+  0x7f742637, 0x7f71d1f6, 0x7f6f78cb, 0x7f6d1ab6, 0x7f6ab7b8, 0x7f684fd0,
+  0x7f65e2ff, 0x7f637144,
+  0x7f60faa0, 0x7f5e7f13, 0x7f5bfe9d, 0x7f59793e, 0x7f56eef5, 0x7f545fc5,
+  0x7f51cbab, 0x7f4f32a9,
+  0x7f4c94be, 0x7f49f1eb, 0x7f474a30, 0x7f449d8c, 0x7f41ec01, 0x7f3f358d,
+  0x7f3c7a31, 0x7f39b9ee,
+  0x7f36f4c3, 0x7f342ab1, 0x7f315bb7, 0x7f2e87d6, 0x7f2baf0d, 0x7f28d15d,
+  0x7f25eec7, 0x7f230749,
+  0x7f201ae5, 0x7f1d299a, 0x7f1a3368, 0x7f173850, 0x7f143852, 0x7f11336d,
+  0x7f0e29a3, 0x7f0b1af2,
+  0x7f08075c, 0x7f04eedf, 0x7f01d17d, 0x7efeaf36, 0x7efb8809, 0x7ef85bf7,
+  0x7ef52b00, 0x7ef1f524,
+  0x7eeeba62, 0x7eeb7abc, 0x7ee83632, 0x7ee4ecc3, 0x7ee19e6f, 0x7ede4b38,
+  0x7edaf31c, 0x7ed7961c,
+  0x7ed43438, 0x7ed0cd70, 0x7ecd61c5, 0x7ec9f137, 0x7ec67bc5, 0x7ec3016f,
+  0x7ebf8237, 0x7ebbfe1c,
+  0x7eb8751e, 0x7eb4e73d, 0x7eb1547a, 0x7eadbcd4, 0x7eaa204c, 0x7ea67ee2,
+  0x7ea2d896, 0x7e9f2d68,
+  0x7e9b7d58, 0x7e97c867, 0x7e940e94, 0x7e904fe0, 0x7e8c8c4b, 0x7e88c3d5,
+  0x7e84f67e, 0x7e812447,
+  0x7e7d4d2f, 0x7e797136, 0x7e75905d, 0x7e71aaa4, 0x7e6dc00c, 0x7e69d093,
+  0x7e65dc3b, 0x7e61e303,
+  0x7e5de4ec, 0x7e59e1f5, 0x7e55da20, 0x7e51cd6c, 0x7e4dbbd9, 0x7e49a567,
+  0x7e458a17, 0x7e4169e9,
+  0x7e3d44dd, 0x7e391af3, 0x7e34ec2b, 0x7e30b885, 0x7e2c8002, 0x7e2842a2,
+  0x7e240064, 0x7e1fb94a,
+  0x7e1b6d53, 0x7e171c7f, 0x7e12c6ce, 0x7e0e6c42, 0x7e0a0cd9, 0x7e05a894,
+  0x7e013f74, 0x7dfcd178,
+  0x7df85ea0, 0x7df3e6ee, 0x7def6a60, 0x7deae8f7, 0x7de662b3, 0x7de1d795,
+  0x7ddd479d, 0x7dd8b2ca,
+  0x7dd4191d, 0x7dcf7a96, 0x7dcad736, 0x7dc62efc, 0x7dc181e8, 0x7dbccffc,
+  0x7db81936, 0x7db35d98,
+  0x7dae9d21, 0x7da9d7d2, 0x7da50dab, 0x7da03eab, 0x7d9b6ad3, 0x7d969224,
+  0x7d91b49e, 0x7d8cd240,
+  0x7d87eb0a, 0x7d82fefe, 0x7d7e0e1c, 0x7d791862, 0x7d741dd2, 0x7d6f1e6c,
+  0x7d6a1a31, 0x7d65111f,
+  0x7d600338, 0x7d5af07b, 0x7d55d8e9, 0x7d50bc82, 0x7d4b9b46, 0x7d467536,
+  0x7d414a51, 0x7d3c1a98,
+  0x7d36e60b, 0x7d31acaa, 0x7d2c6e76, 0x7d272b6e, 0x7d21e393, 0x7d1c96e5,
+  0x7d174564, 0x7d11ef11,
+  0x7d0c93eb, 0x7d0733f3, 0x7d01cf29, 0x7cfc658d, 0x7cf6f720, 0x7cf183e1,
+  0x7cec0bd1, 0x7ce68ef0,
+  0x7ce10d3f, 0x7cdb86bd, 0x7cd5fb6a, 0x7cd06b48, 0x7ccad656, 0x7cc53c94,
+  0x7cbf9e03, 0x7cb9faa2,
+  0x7cb45272, 0x7caea574, 0x7ca8f3a7, 0x7ca33d0c, 0x7c9d81a3, 0x7c97c16b,
+  0x7c91fc66, 0x7c8c3294,
+  0x7c8663f4, 0x7c809088, 0x7c7ab84e, 0x7c74db48, 0x7c6ef976, 0x7c6912d7,
+  0x7c63276d, 0x7c5d3737,
+  0x7c574236, 0x7c514869, 0x7c4b49d2, 0x7c45466f, 0x7c3f3e42, 0x7c39314b,
+  0x7c331f8a, 0x7c2d08ff,
+  0x7c26edab, 0x7c20cd8d, 0x7c1aa8a6, 0x7c147ef6, 0x7c0e507e, 0x7c081d3d,
+  0x7c01e534, 0x7bfba863,
+  0x7bf566cb, 0x7bef206b, 0x7be8d544, 0x7be28556, 0x7bdc30a1, 0x7bd5d726,
+  0x7bcf78e5, 0x7bc915dd,
+  0x7bc2ae10, 0x7bbc417e, 0x7bb5d026, 0x7baf5a09, 0x7ba8df28, 0x7ba25f82,
+  0x7b9bdb18, 0x7b9551ea,
+  0x7b8ec3f8, 0x7b883143, 0x7b8199ca, 0x7b7afd8f, 0x7b745c91, 0x7b6db6d0,
+  0x7b670c4d, 0x7b605d09,
+  0x7b59a902, 0x7b52f03a, 0x7b4c32b1, 0x7b457068, 0x7b3ea95d, 0x7b37dd92,
+  0x7b310d07, 0x7b2a37bc,
+  0x7b235db2, 0x7b1c7ee8, 0x7b159b5f, 0x7b0eb318, 0x7b07c612, 0x7b00d44d,
+  0x7af9ddcb, 0x7af2e28b,
+  0x7aebe28d, 0x7ae4ddd2, 0x7addd45b, 0x7ad6c626, 0x7acfb336, 0x7ac89b89,
+  0x7ac17f20, 0x7aba5dfc,
+  0x7ab3381d, 0x7aac0d82, 0x7aa4de2d, 0x7a9daa1d, 0x7a967153, 0x7a8f33d0,
+  0x7a87f192, 0x7a80aa9c,
+  0x7a795eec, 0x7a720e84, 0x7a6ab963, 0x7a635f8a, 0x7a5c00f9, 0x7a549db0,
+  0x7a4d35b0, 0x7a45c8f9,
+  0x7a3e578b, 0x7a36e166, 0x7a2f668c, 0x7a27e6fb, 0x7a2062b5, 0x7a18d9b9,
+  0x7a114c09, 0x7a09b9a4,
+  0x7a02228a, 0x79fa86bc, 0x79f2e63a, 0x79eb4105, 0x79e3971c, 0x79dbe880,
+  0x79d43532, 0x79cc7d31,
+  0x79c4c07e, 0x79bcff19, 0x79b53903, 0x79ad6e3c, 0x79a59ec3, 0x799dca9a,
+  0x7995f1c1, 0x798e1438,
+  0x798631ff, 0x797e4b16, 0x79765f7f, 0x796e6f39, 0x79667a44, 0x795e80a1,
+  0x79568250, 0x794e7f52,
+  0x794677a6, 0x793e6b4e, 0x79365a49, 0x792e4497, 0x79262a3a, 0x791e0b31,
+  0x7915e77c, 0x790dbf1d,
+  0x79059212, 0x78fd605d, 0x78f529fe, 0x78eceef6, 0x78e4af44, 0x78dc6ae8,
+  0x78d421e4, 0x78cbd437,
+  0x78c381e2, 0x78bb2ae5, 0x78b2cf41, 0x78aa6ef5, 0x78a20a03, 0x7899a06a,
+  0x7891322a, 0x7888bf45,
+  0x788047ba, 0x7877cb89, 0x786f4ab4, 0x7866c53a, 0x785e3b1c, 0x7855ac5a,
+  0x784d18f4, 0x784480ea,
+  0x783be43e, 0x783342ef, 0x782a9cfe, 0x7821f26b, 0x78194336, 0x78108f60,
+  0x7807d6e9, 0x77ff19d1,
+  0x77f65819, 0x77ed91c0, 0x77e4c6c9, 0x77dbf732, 0x77d322fc, 0x77ca4a27,
+  0x77c16cb4, 0x77b88aa3,
+  0x77afa3f5, 0x77a6b8a9, 0x779dc8c0, 0x7794d43b, 0x778bdb19, 0x7782dd5c,
+  0x7779db03, 0x7770d40f,
+  0x7767c880, 0x775eb857, 0x7755a394, 0x774c8a36, 0x77436c40, 0x773a49b0,
+  0x77312287, 0x7727f6c6,
+  0x771ec66e, 0x7715917d, 0x770c57f5, 0x770319d6, 0x76f9d721, 0x76f08fd5,
+  0x76e743f4, 0x76ddf37c,
+  0x76d49e70, 0x76cb44cf, 0x76c1e699, 0x76b883d0, 0x76af1c72, 0x76a5b082,
+  0x769c3ffe, 0x7692cae8,
+  0x7689513f, 0x767fd304, 0x76765038, 0x766cc8db, 0x76633ced, 0x7659ac6f,
+  0x76501760, 0x76467dc2,
+  0x763cdf94, 0x76333cd8, 0x7629958c, 0x761fe9b3, 0x7616394c, 0x760c8457,
+  0x7602cad5, 0x75f90cc7,
+  0x75ef4a2c, 0x75e58305, 0x75dbb753, 0x75d1e715, 0x75c8124d, 0x75be38fa,
+  0x75b45b1d, 0x75aa78b6,
+  0x75a091c6, 0x7596a64d, 0x758cb64c, 0x7582c1c2, 0x7578c8b0, 0x756ecb18,
+  0x7564c8f8, 0x755ac251,
+  0x7550b725, 0x7546a772, 0x753c933a, 0x75327a7d, 0x75285d3b, 0x751e3b75,
+  0x7514152b, 0x7509ea5d,
+  0x74ffbb0d, 0x74f58739, 0x74eb4ee3, 0x74e1120c, 0x74d6d0b2, 0x74cc8ad8,
+  0x74c2407d, 0x74b7f1a1,
+  0x74ad9e46, 0x74a3466b, 0x7498ea11, 0x748e8938, 0x748423e0, 0x7479ba0b,
+  0x746f4bb8, 0x7464d8e8,
+  0x745a619b, 0x744fe5d2, 0x7445658d, 0x743ae0cc, 0x74305790, 0x7425c9da,
+  0x741b37a9, 0x7410a0fe,
+  0x740605d9, 0x73fb663c, 0x73f0c226, 0x73e61997, 0x73db6c91, 0x73d0bb13,
+  0x73c6051f, 0x73bb4ab3,
+  0x73b08bd1, 0x73a5c87a, 0x739b00ad, 0x7390346b, 0x738563b5, 0x737a8e8a,
+  0x736fb4ec, 0x7364d6da,
+  0x7359f456, 0x734f0d5f, 0x734421f6, 0x7339321b, 0x732e3dcf, 0x73234512,
+  0x731847e5, 0x730d4648,
+  0x7302403c, 0x72f735c0, 0x72ec26d6, 0x72e1137d, 0x72d5fbb7, 0x72cadf83,
+  0x72bfbee3, 0x72b499d6,
+  0x72a9705c, 0x729e4277, 0x72931027, 0x7287d96c, 0x727c9e47, 0x72715eb8,
+  0x72661abf, 0x725ad25d,
+  0x724f8593, 0x72443460, 0x7238dec5, 0x722d84c4, 0x7222265b, 0x7216c38c,
+  0x720b5c57, 0x71fff0bc,
+  0x71f480bc, 0x71e90c57, 0x71dd938f, 0x71d21662, 0x71c694d2, 0x71bb0edf,
+  0x71af848a, 0x71a3f5d2,
+  0x719862b9, 0x718ccb3f, 0x71812f65, 0x71758f29, 0x7169ea8f, 0x715e4194,
+  0x7152943b, 0x7146e284,
+  0x713b2c6e, 0x712f71fb, 0x7123b32b, 0x7117effe, 0x710c2875, 0x71005c90,
+  0x70f48c50, 0x70e8b7b5,
+  0x70dcdec0, 0x70d10171, 0x70c51fc8, 0x70b939c7, 0x70ad4f6d, 0x70a160ba,
+  0x70956db1, 0x70897650,
+  0x707d7a98, 0x70717a8a, 0x70657626, 0x70596d6d, 0x704d6060, 0x70414efd,
+  0x70353947, 0x70291f3e,
+  0x701d00e1, 0x7010de32, 0x7004b731, 0x6ff88bde, 0x6fec5c3b, 0x6fe02846,
+  0x6fd3f001, 0x6fc7b36d,
+  0x6fbb728a, 0x6faf2d57, 0x6fa2e3d7, 0x6f969608, 0x6f8a43ed, 0x6f7ded84,
+  0x6f7192cf, 0x6f6533ce,
+  0x6f58d082, 0x6f4c68eb, 0x6f3ffd09, 0x6f338cde, 0x6f271868, 0x6f1a9faa,
+  0x6f0e22a3, 0x6f01a155,
+  0x6ef51bbe, 0x6ee891e1, 0x6edc03bc, 0x6ecf7152, 0x6ec2daa2, 0x6eb63fad,
+  0x6ea9a073, 0x6e9cfcf5,
+  0x6e905534, 0x6e83a92f, 0x6e76f8e7, 0x6e6a445d, 0x6e5d8b91, 0x6e50ce84,
+  0x6e440d37, 0x6e3747a9,
+  0x6e2a7ddb, 0x6e1dafce, 0x6e10dd82, 0x6e0406f8, 0x6df72c30, 0x6dea4d2b,
+  0x6ddd69e9, 0x6dd0826a,
+  0x6dc396b0, 0x6db6a6ba, 0x6da9b28a, 0x6d9cba1f, 0x6d8fbd7a, 0x6d82bc9d,
+  0x6d75b786, 0x6d68ae37,
+  0x6d5ba0b0, 0x6d4e8ef2, 0x6d4178fd, 0x6d345ed1, 0x6d274070, 0x6d1a1dda,
+  0x6d0cf70f, 0x6cffcc0f,
+  0x6cf29cdc, 0x6ce56975, 0x6cd831dc, 0x6ccaf610, 0x6cbdb613, 0x6cb071e4,
+  0x6ca32985, 0x6c95dcf6,
+  0x6c888c36, 0x6c7b3748, 0x6c6dde2b, 0x6c6080e0, 0x6c531f67, 0x6c45b9c1,
+  0x6c384fef, 0x6c2ae1f0,
+  0x6c1d6fc6, 0x6c0ff971, 0x6c027ef1, 0x6bf50047, 0x6be77d74, 0x6bd9f677,
+  0x6bcc6b53, 0x6bbedc06,
+  0x6bb14892, 0x6ba3b0f7, 0x6b961536, 0x6b88754f, 0x6b7ad142, 0x6b6d2911,
+  0x6b5f7cbc, 0x6b51cc42,
+  0x6b4417a6, 0x6b365ee7, 0x6b28a206, 0x6b1ae103, 0x6b0d1bdf, 0x6aff529a,
+  0x6af18536, 0x6ae3b3b2,
+  0x6ad5de0f, 0x6ac8044e, 0x6aba266e, 0x6aac4472, 0x6a9e5e58, 0x6a907423,
+  0x6a8285d1, 0x6a749365,
+  0x6a669cdd, 0x6a58a23c, 0x6a4aa381, 0x6a3ca0ad, 0x6a2e99c0, 0x6a208ebb,
+  0x6a127f9f, 0x6a046c6c,
+  0x69f65523, 0x69e839c4, 0x69da1a50, 0x69cbf6c7, 0x69bdcf29, 0x69afa378,
+  0x69a173b5, 0x69933fde,
+  0x698507f6, 0x6976cbfc, 0x69688bf1, 0x695a47d6, 0x694bffab, 0x693db371,
+  0x692f6328, 0x69210ed1,
+  0x6912b66c, 0x690459fb, 0x68f5f97d, 0x68e794f3, 0x68d92c5d, 0x68cabfbd,
+  0x68bc4f13, 0x68adda5f,
+  0x689f61a1, 0x6890e4dc, 0x6882640e, 0x6873df38, 0x6865565c, 0x6856c979,
+  0x68483891, 0x6839a3a4,
+  0x682b0ab1, 0x681c6dbb, 0x680dccc1, 0x67ff27c4, 0x67f07ec5, 0x67e1d1c4,
+  0x67d320c1, 0x67c46bbe,
+  0x67b5b2bb, 0x67a6f5b8, 0x679834b6, 0x67896fb6, 0x677aa6b8, 0x676bd9bd,
+  0x675d08c4, 0x674e33d0,
+  0x673f5ae0, 0x67307df5, 0x67219d10, 0x6712b831, 0x6703cf58, 0x66f4e287,
+  0x66e5f1be, 0x66d6fcfd,
+  0x66c80445, 0x66b90797, 0x66aa06f3, 0x669b0259, 0x668bf9cb, 0x667ced49,
+  0x666ddcd3, 0x665ec86b,
+  0x664fb010, 0x664093c3, 0x66317385, 0x66224f56, 0x66132738, 0x6603fb2a,
+  0x65f4cb2d, 0x65e59742,
+  0x65d65f69, 0x65c723a3, 0x65b7e3f1, 0x65a8a052, 0x659958c9, 0x658a0d54,
+  0x657abdf6, 0x656b6aae,
+  0x655c137d, 0x654cb863, 0x653d5962, 0x652df679, 0x651e8faa, 0x650f24f5,
+  0x64ffb65b, 0x64f043dc,
+  0x64e0cd78, 0x64d15331, 0x64c1d507, 0x64b252fa, 0x64a2cd0c, 0x6493433c,
+  0x6483b58c, 0x647423fb,
+  0x64648e8c, 0x6454f53d, 0x64455810, 0x6435b706, 0x6426121e, 0x6416695a,
+  0x6406bcba, 0x63f70c3f,
+  0x63e757ea, 0x63d79fba, 0x63c7e3b1, 0x63b823cf, 0x63a86015, 0x63989884,
+  0x6388cd1b, 0x6378fddc,
+  0x63692ac7, 0x635953dd, 0x6349791f, 0x63399a8d, 0x6329b827, 0x6319d1ef,
+  0x6309e7e4, 0x62f9fa09,
+  0x62ea085c, 0x62da12df, 0x62ca1992, 0x62ba1c77, 0x62aa1b8d, 0x629a16d5,
+  0x628a0e50, 0x627a01fe,
+  0x6269f1e1, 0x6259ddf8, 0x6249c645, 0x6239aac7, 0x62298b81, 0x62196871,
+  0x62094199, 0x61f916f9,
+  0x61e8e893, 0x61d8b666, 0x61c88074, 0x61b846bc, 0x61a80940, 0x6197c800,
+  0x618782fd, 0x61773a37,
+  0x6166edb0, 0x61569d67, 0x6146495d, 0x6135f193, 0x6125960a, 0x611536c2,
+  0x6104d3bc, 0x60f46cf9,
+  0x60e40278, 0x60d3943b, 0x60c32243, 0x60b2ac8f, 0x60a23322, 0x6091b5fa,
+  0x60813519, 0x6070b080,
+  0x6060282f, 0x604f9c27, 0x603f0c69, 0x602e78f4, 0x601de1ca, 0x600d46ec,
+  0x5ffca859, 0x5fec0613,
+  0x5fdb601b, 0x5fcab670, 0x5fba0914, 0x5fa95807, 0x5f98a34a, 0x5f87eade,
+  0x5f772ec2, 0x5f666ef9,
+  0x5f55ab82, 0x5f44e45e, 0x5f34198e, 0x5f234b12, 0x5f1278eb, 0x5f01a31a,
+  0x5ef0c99f, 0x5edfec7b,
+  0x5ecf0baf, 0x5ebe273b, 0x5ead3f1f, 0x5e9c535e, 0x5e8b63f7, 0x5e7a70ea,
+  0x5e697a39, 0x5e587fe5,
+  0x5e4781ed, 0x5e368053, 0x5e257b17, 0x5e147239, 0x5e0365bb, 0x5df2559e,
+  0x5de141e1, 0x5dd02a85,
+  0x5dbf0f8c, 0x5dadf0f5, 0x5d9ccec2, 0x5d8ba8f3, 0x5d7a7f88, 0x5d695283,
+  0x5d5821e4, 0x5d46edac,
+  0x5d35b5db, 0x5d247a72, 0x5d133b72, 0x5d01f8dc, 0x5cf0b2af, 0x5cdf68ed,
+  0x5cce1b97, 0x5cbccaac,
+  0x5cab762f, 0x5c9a1e1e, 0x5c88c27c, 0x5c776348, 0x5c660084, 0x5c549a30,
+  0x5c43304d, 0x5c31c2db,
+  0x5c2051db, 0x5c0edd4e, 0x5bfd6534, 0x5bebe98e, 0x5bda6a5d, 0x5bc8e7a2,
+  0x5bb7615d, 0x5ba5d78e,
+  0x5b944a37, 0x5b82b958, 0x5b7124f2, 0x5b5f8d06, 0x5b4df193, 0x5b3c529c,
+  0x5b2ab020, 0x5b190a20,
+  0x5b07609d, 0x5af5b398, 0x5ae40311, 0x5ad24f09, 0x5ac09781, 0x5aaedc78,
+  0x5a9d1df1, 0x5a8b5bec,
+  0x5a799669, 0x5a67cd69, 0x5a5600ec, 0x5a4430f5, 0x5a325d82, 0x5a208695,
+  0x5a0eac2e, 0x59fcce4f,
+  0x59eaecf8, 0x59d90829, 0x59c71fe3, 0x59b53427, 0x59a344f6, 0x59915250,
+  0x597f5c36, 0x596d62a9,
+  0x595b65aa, 0x59496538, 0x59376155, 0x59255a02, 0x59134f3e, 0x5901410c,
+  0x58ef2f6b, 0x58dd1a5d,
+  0x58cb01e1, 0x58b8e5f9, 0x58a6c6a5, 0x5894a3e7, 0x58827dbe, 0x5870542c,
+  0x585e2730, 0x584bf6cd,
+  0x5839c302, 0x58278bd1, 0x58155139, 0x5803133c, 0x57f0d1da, 0x57de8d15,
+  0x57cc44ec, 0x57b9f960,
+  0x57a7aa73, 0x57955825, 0x57830276, 0x5770a968, 0x575e4cfa, 0x574bed2f,
+  0x57398a05, 0x5727237f,
+  0x5714b99d, 0x57024c5f, 0x56efdbc7, 0x56dd67d4, 0x56caf088, 0x56b875e4,
+  0x56a5f7e7, 0x56937694,
+  0x5680f1ea, 0x566e69ea, 0x565bde95, 0x56494fec, 0x5636bdef, 0x5624289f,
+  0x56118ffe, 0x55fef40a,
+  0x55ec54c6, 0x55d9b232, 0x55c70c4f, 0x55b4631d, 0x55a1b69d, 0x558f06d0,
+  0x557c53b6, 0x55699d51,
+  0x5556e3a1, 0x554426a7, 0x55316663, 0x551ea2d6, 0x550bdc01, 0x54f911e5,
+  0x54e64482, 0x54d373d9,
+  0x54c09feb, 0x54adc8b8, 0x549aee42, 0x54881089, 0x54752f8d, 0x54624b50,
+  0x544f63d2, 0x543c7914,
+  0x54298b17, 0x541699db, 0x5403a561, 0x53f0adaa, 0x53ddb2b6, 0x53cab486,
+  0x53b7b31c, 0x53a4ae77,
+  0x5391a699, 0x537e9b82, 0x536b8d33, 0x53587bad, 0x534566f0, 0x53324efd,
+  0x531f33d5, 0x530c1579,
+  0x52f8f3e9, 0x52e5cf27, 0x52d2a732, 0x52bf7c0b, 0x52ac4db4, 0x52991c2d,
+  0x5285e777, 0x5272af92,
+  0x525f7480, 0x524c3640, 0x5238f4d4, 0x5225b03d, 0x5212687b, 0x51ff1d8f,
+  0x51ebcf7a, 0x51d87e3c,
+  0x51c529d7, 0x51b1d24a, 0x519e7797, 0x518b19bf, 0x5177b8c2, 0x516454a0,
+  0x5150ed5c, 0x513d82f4,
+  0x512a156b, 0x5116a4c1, 0x510330f7, 0x50efba0d, 0x50dc4005, 0x50c8c2de,
+  0x50b5429a, 0x50a1bf39,
+  0x508e38bd, 0x507aaf25, 0x50672273, 0x505392a8, 0x503fffc4, 0x502c69c8,
+  0x5018d0b4, 0x5005348a,
+  0x4ff1954b, 0x4fddf2f6, 0x4fca4d8d, 0x4fb6a510, 0x4fa2f981, 0x4f8f4ae0,
+  0x4f7b992d, 0x4f67e46a,
+  0x4f542c98, 0x4f4071b6, 0x4f2cb3c7, 0x4f18f2c9, 0x4f052ec0, 0x4ef167aa,
+  0x4edd9d89, 0x4ec9d05e,
+  0x4eb60029, 0x4ea22ceb, 0x4e8e56a5, 0x4e7a7d58, 0x4e66a105, 0x4e52c1ab,
+  0x4e3edf4d, 0x4e2af9ea,
+  0x4e171184, 0x4e03261b, 0x4def37b0, 0x4ddb4644, 0x4dc751d8, 0x4db35a6c,
+  0x4d9f6001, 0x4d8b6298,
+  0x4d776231, 0x4d635ece, 0x4d4f5870, 0x4d3b4f16, 0x4d2742c2, 0x4d133374,
+  0x4cff212e, 0x4ceb0bf0,
+  0x4cd6f3bb, 0x4cc2d88f, 0x4caeba6e, 0x4c9a9958, 0x4c86754e, 0x4c724e50,
+  0x4c5e2460, 0x4c49f77f,
+  0x4c35c7ac, 0x4c2194e9, 0x4c0d5f37, 0x4bf92697, 0x4be4eb08, 0x4bd0ac8d,
+  0x4bbc6b25, 0x4ba826d1,
+  0x4b93df93, 0x4b7f956b, 0x4b6b485a, 0x4b56f861, 0x4b42a580, 0x4b2e4fb8,
+  0x4b19f70a, 0x4b059b77,
+  0x4af13d00, 0x4adcdba5, 0x4ac87767, 0x4ab41046, 0x4a9fa645, 0x4a8b3963,
+  0x4a76c9a2, 0x4a625701,
+  0x4a4de182, 0x4a396926, 0x4a24edee, 0x4a106fda, 0x49fbeeea, 0x49e76b21,
+  0x49d2e47e, 0x49be5b02,
+  0x49a9ceaf, 0x49953f84, 0x4980ad84, 0x496c18ae, 0x49578103, 0x4942e684,
+  0x492e4933, 0x4919a90f,
+  0x4905061a, 0x48f06054, 0x48dbb7be, 0x48c70c59, 0x48b25e25, 0x489dad25,
+  0x4888f957, 0x487442be,
+  0x485f8959, 0x484acd2a, 0x48360e32, 0x48214c71, 0x480c87e8, 0x47f7c099,
+  0x47e2f682, 0x47ce29a7,
+  0x47b95a06, 0x47a487a2, 0x478fb27b, 0x477ada91, 0x4765ffe6, 0x4751227a,
+  0x473c424e, 0x47275f63,
+  0x471279ba, 0x46fd9154, 0x46e8a631, 0x46d3b852, 0x46bec7b8, 0x46a9d464,
+  0x4694de56, 0x467fe590,
+  0x466aea12, 0x4655ebdd, 0x4640eaf2, 0x462be751, 0x4616e0fc, 0x4601d7f3,
+  0x45eccc37, 0x45d7bdc9,
+  0x45c2acaa, 0x45ad98da, 0x4598825a, 0x4583692c, 0x456e4d4f, 0x45592ec6,
+  0x45440d90, 0x452ee9ae,
+  0x4519c321, 0x450499eb, 0x44ef6e0b, 0x44da3f83, 0x44c50e53, 0x44afda7d,
+  0x449aa400, 0x44856adf,
+  0x44702f19, 0x445af0b0, 0x4445afa4, 0x44306bf6, 0x441b25a8, 0x4405dcb9,
+  0x43f0912b, 0x43db42fe,
+  0x43c5f234, 0x43b09ecc, 0x439b48c9, 0x4385f02a, 0x437094f1, 0x435b371f,
+  0x4345d6b3, 0x433073b0,
+  0x431b0e15, 0x4305a5e5, 0x42f03b1e, 0x42dacdc3, 0x42c55dd4, 0x42afeb53,
+  0x429a763f, 0x4284fe99,
+  0x426f8463, 0x425a079e, 0x42448849, 0x422f0667, 0x421981f7, 0x4203fafb,
+  0x41ee7174, 0x41d8e561,
+  0x41c356c5, 0x41adc5a0, 0x419831f3, 0x41829bbe, 0x416d0302, 0x415767c1,
+  0x4141c9fb, 0x412c29b1,
+  0x411686e4, 0x4100e194, 0x40eb39c3, 0x40d58f71, 0x40bfe29f, 0x40aa334e,
+  0x4094817f, 0x407ecd32,
+  0x40691669, 0x40535d24, 0x403da165, 0x4027e32b, 0x40122278, 0x3ffc5f4d,
+  0x3fe699aa, 0x3fd0d191,
+  0x3fbb0702, 0x3fa539fd, 0x3f8f6a85, 0x3f799899, 0x3f63c43b, 0x3f4ded6b,
+  0x3f38142a, 0x3f22387a,
+  0x3f0c5a5a, 0x3ef679cc, 0x3ee096d1, 0x3ecab169, 0x3eb4c995, 0x3e9edf57,
+  0x3e88f2ae, 0x3e73039d,
+  0x3e5d1222, 0x3e471e41, 0x3e3127f9, 0x3e1b2f4a, 0x3e053437, 0x3def36c0,
+  0x3dd936e6, 0x3dc334a9,
+  0x3dad300b, 0x3d97290b, 0x3d811fac, 0x3d6b13ee, 0x3d5505d2, 0x3d3ef559,
+  0x3d28e282, 0x3d12cd51,
+  0x3cfcb5c4, 0x3ce69bde, 0x3cd07f9f, 0x3cba6107, 0x3ca44018, 0x3c8e1cd3,
+  0x3c77f737, 0x3c61cf48,
+  0x3c4ba504, 0x3c35786d, 0x3c1f4983, 0x3c091849, 0x3bf2e4be, 0x3bdcaee3,
+  0x3bc676b9, 0x3bb03c42,
+  0x3b99ff7d, 0x3b83c06c, 0x3b6d7f10, 0x3b573b69, 0x3b40f579, 0x3b2aad3f,
+  0x3b1462be, 0x3afe15f6,
+  0x3ae7c6e7, 0x3ad17593, 0x3abb21fb, 0x3aa4cc1e, 0x3a8e7400, 0x3a78199f,
+  0x3a61bcfd, 0x3a4b5e1b,
+  0x3a34fcf9, 0x3a1e9999, 0x3a0833fc, 0x39f1cc21, 0x39db620b, 0x39c4f5ba,
+  0x39ae872f, 0x3998166a,
+  0x3981a36d, 0x396b2e38, 0x3954b6cd, 0x393e3d2c, 0x3927c155, 0x3911434b,
+  0x38fac30e, 0x38e4409e,
+  0x38cdbbfc, 0x38b7352a, 0x38a0ac29, 0x388a20f8, 0x38739399, 0x385d040d,
+  0x38467255, 0x382fde72,
+  0x38194864, 0x3802b02c, 0x37ec15cb, 0x37d57943, 0x37beda93, 0x37a839be,
+  0x379196c3, 0x377af1a3,
+  0x37644a60, 0x374da0fa, 0x3736f573, 0x372047ca, 0x37099802, 0x36f2e61a,
+  0x36dc3214, 0x36c57bf0,
+  0x36aec3b0, 0x36980954, 0x36814cde, 0x366a8e4d, 0x3653cda3, 0x363d0ae2,
+  0x36264609, 0x360f7f19,
+  0x35f8b614, 0x35e1eafa, 0x35cb1dcc, 0x35b44e8c, 0x359d7d39, 0x3586a9d5,
+  0x356fd461, 0x3558fcde,
+  0x3542234c, 0x352b47ad, 0x35146a00, 0x34fd8a48, 0x34e6a885, 0x34cfc4b7,
+  0x34b8dee1, 0x34a1f702,
+  0x348b0d1c, 0x3474212f, 0x345d333c, 0x34464345, 0x342f5149, 0x34185d4b,
+  0x3401674a, 0x33ea6f48,
+  0x33d37546, 0x33bc7944, 0x33a57b44, 0x338e7b46, 0x3377794b, 0x33607554,
+  0x33496f62, 0x33326776,
+  0x331b5d91, 0x330451b3, 0x32ed43de, 0x32d63412, 0x32bf2250, 0x32a80e99,
+  0x3290f8ef, 0x3279e151,
+  0x3262c7c1, 0x324bac40, 0x32348ecf, 0x321d6f6e, 0x32064e1e, 0x31ef2ae1,
+  0x31d805b7, 0x31c0dea1,
+  0x31a9b5a0, 0x31928ab4, 0x317b5de0, 0x31642f23, 0x314cfe7f, 0x3135cbf4,
+  0x311e9783, 0x3107612e,
+  0x30f028f4, 0x30d8eed8, 0x30c1b2da, 0x30aa74fa, 0x3093353a, 0x307bf39b,
+  0x3064b01d, 0x304d6ac1,
+  0x30362389, 0x301eda75, 0x30078f86, 0x2ff042bd, 0x2fd8f41b, 0x2fc1a3a0,
+  0x2faa514f, 0x2f92fd26,
+  0x2f7ba729, 0x2f644f56, 0x2f4cf5b0, 0x2f359a37, 0x2f1e3ced, 0x2f06ddd1,
+  0x2eef7ce5, 0x2ed81a29,
+  0x2ec0b5a0, 0x2ea94f49, 0x2e91e725, 0x2e7a7d36, 0x2e63117c, 0x2e4ba3f8,
+  0x2e3434ac, 0x2e1cc397,
+  0x2e0550bb, 0x2deddc19, 0x2dd665b2, 0x2dbeed86, 0x2da77397, 0x2d8ff7e5,
+  0x2d787a72, 0x2d60fb3e,
+  0x2d497a4a, 0x2d31f797, 0x2d1a7325, 0x2d02ecf7, 0x2ceb650d, 0x2cd3db67,
+  0x2cbc5006, 0x2ca4c2ed,
+  0x2c8d341a, 0x2c75a390, 0x2c5e114f, 0x2c467d58, 0x2c2ee7ad, 0x2c17504d,
+  0x2bffb73a, 0x2be81c74,
+  0x2bd07ffe, 0x2bb8e1d7, 0x2ba14200, 0x2b89a07b, 0x2b71fd48, 0x2b5a5868,
+  0x2b42b1dd, 0x2b2b09a6,
+  0x2b135fc6, 0x2afbb43c, 0x2ae4070a, 0x2acc5831, 0x2ab4a7b1, 0x2a9cf58c,
+  0x2a8541c3, 0x2a6d8c55,
+  0x2a55d545, 0x2a3e1c93, 0x2a266240, 0x2a0ea64d, 0x29f6e8bb, 0x29df298b,
+  0x29c768be, 0x29afa654,
+  0x2997e24f, 0x29801caf, 0x29685576, 0x29508ca4, 0x2938c23a, 0x2920f63a,
+  0x290928a3, 0x28f15978,
+  0x28d988b8, 0x28c1b666, 0x28a9e281, 0x28920d0a, 0x287a3604, 0x28625d6d,
+  0x284a8349, 0x2832a796,
+  0x281aca57, 0x2802eb8c, 0x27eb0b36, 0x27d32956, 0x27bb45ed, 0x27a360fc,
+  0x278b7a84, 0x27739285,
+  0x275ba901, 0x2743bdf9, 0x272bd16d, 0x2713e35f, 0x26fbf3ce, 0x26e402bd,
+  0x26cc102d, 0x26b41c1d,
+  0x269c268f, 0x26842f84, 0x266c36fe, 0x26543cfb, 0x263c417f, 0x26244489,
+  0x260c461b, 0x25f44635,
+  0x25dc44d9, 0x25c44207, 0x25ac3dc0, 0x25943806, 0x257c30d8, 0x25642839,
+  0x254c1e28, 0x253412a8,
+  0x251c05b8, 0x2503f75a, 0x24ebe78f, 0x24d3d657, 0x24bbc3b4, 0x24a3afa6,
+  0x248b9a2f, 0x2473834f,
+  0x245b6b07, 0x24435158, 0x242b3644, 0x241319ca, 0x23fafbec, 0x23e2dcac,
+  0x23cabc09, 0x23b29a05,
+  0x239a76a0, 0x238251dd, 0x236a2bba, 0x2352043b, 0x2339db5e, 0x2321b126,
+  0x23098593, 0x22f158a7,
+  0x22d92a61, 0x22c0fac4, 0x22a8c9cf, 0x22909785, 0x227863e5, 0x22602ef1,
+  0x2247f8aa, 0x222fc111,
+  0x22178826, 0x21ff4dea, 0x21e71260, 0x21ced586, 0x21b6975f, 0x219e57eb,
+  0x2186172b, 0x216dd521,
+  0x215591cc, 0x213d4d2f, 0x21250749, 0x210cc01d, 0x20f477aa, 0x20dc2df2,
+  0x20c3e2f5, 0x20ab96b5,
+  0x20934933, 0x207afa6f, 0x2062aa6b, 0x204a5927, 0x203206a4, 0x2019b2e4,
+  0x20015de7, 0x1fe907ae,
+  0x1fd0b03a, 0x1fb8578b, 0x1f9ffda4, 0x1f87a285, 0x1f6f462f, 0x1f56e8a2,
+  0x1f3e89e0, 0x1f2629ea,
+  0x1f0dc8c0, 0x1ef56664, 0x1edd02d6, 0x1ec49e17, 0x1eac3829, 0x1e93d10c,
+  0x1e7b68c2, 0x1e62ff4a,
+  0x1e4a94a7, 0x1e3228d9, 0x1e19bbe0, 0x1e014dbf, 0x1de8de75, 0x1dd06e04,
+  0x1db7fc6d, 0x1d9f89b1,
+  0x1d8715d0, 0x1d6ea0cc, 0x1d562aa6, 0x1d3db35e, 0x1d253af5, 0x1d0cc16c,
+  0x1cf446c5, 0x1cdbcb00,
+  0x1cc34e1f, 0x1caad021, 0x1c925109, 0x1c79d0d6, 0x1c614f8b, 0x1c48cd27,
+  0x1c3049ac, 0x1c17c51b,
+  0x1bff3f75, 0x1be6b8ba, 0x1bce30ec, 0x1bb5a80c, 0x1b9d1e1a, 0x1b849317,
+  0x1b6c0705, 0x1b5379e5,
+  0x1b3aebb6, 0x1b225c7b, 0x1b09cc34, 0x1af13ae3, 0x1ad8a887, 0x1ac01522,
+  0x1aa780b6, 0x1a8eeb42,
+  0x1a7654c8, 0x1a5dbd49, 0x1a4524c6, 0x1a2c8b3f, 0x1a13f0b6, 0x19fb552c,
+  0x19e2b8a2, 0x19ca1b17,
+  0x19b17c8f, 0x1998dd09, 0x19803c86, 0x19679b07, 0x194ef88e, 0x1936551b,
+  0x191db0af, 0x19050b4b,
+  0x18ec64f0, 0x18d3bda0, 0x18bb155a, 0x18a26c20, 0x1889c1f3, 0x187116d4,
+  0x18586ac3, 0x183fbdc3,
+  0x18270fd3, 0x180e60f4, 0x17f5b129, 0x17dd0070, 0x17c44ecd, 0x17ab9c3e,
+  0x1792e8c6, 0x177a3466,
+  0x17617f1d, 0x1748c8ee, 0x173011d9, 0x171759df, 0x16fea102, 0x16e5e741,
+  0x16cd2c9f, 0x16b4711b,
+  0x169bb4b7, 0x1682f774, 0x166a3953, 0x16517a55, 0x1638ba7a, 0x161ff9c4,
+  0x16073834, 0x15ee75cb,
+  0x15d5b288, 0x15bcee6f, 0x15a4297f, 0x158b63b9, 0x15729d1f, 0x1559d5b1,
+  0x15410d70, 0x1528445d,
+  0x150f7a7a, 0x14f6afc7, 0x14dde445, 0x14c517f4, 0x14ac4ad7, 0x14937cee,
+  0x147aae3a, 0x1461debc,
+  0x14490e74, 0x14303d65, 0x14176b8e, 0x13fe98f1, 0x13e5c58e, 0x13ccf167,
+  0x13b41c7d, 0x139b46d0,
+  0x13827062, 0x13699933, 0x1350c144, 0x1337e897, 0x131f0f2c, 0x13063505,
+  0x12ed5a21, 0x12d47e83,
+  0x12bba22b, 0x12a2c51b, 0x1289e752, 0x127108d2, 0x1258299c, 0x123f49b2,
+  0x12266913, 0x120d87c1,
+  0x11f4a5bd, 0x11dbc307, 0x11c2dfa2, 0x11a9fb8d, 0x119116c9, 0x11783159,
+  0x115f4b3c, 0x11466473,
+  0x112d7d00, 0x111494e4, 0x10fbac1e, 0x10e2c2b2, 0x10c9d89e, 0x10b0ede5,
+  0x10980287, 0x107f1686,
+  0x106629e1, 0x104d3c9b, 0x10344eb4, 0x101b602d, 0x10027107, 0xfe98143,
+  0xfd090e1, 0xfb79fe4,
+  0xf9eae4c, 0xf85bc19, 0xf6cc94e, 0xf53d5ea, 0xf3ae1ee, 0xf21ed5d, 0xf08f836,
+  0xef0027b,
+  0xed70c2c, 0xebe154b, 0xea51dd8, 0xe8c25d5, 0xe732d42, 0xe5a3421, 0xe413a72,
+  0xe284036,
+  0xe0f456f, 0xdf64a1c, 0xddd4e40, 0xdc451dc, 0xdab54ef, 0xd92577b, 0xd795982,
+  0xd605b03,
+  0xd475c00, 0xd2e5c7b, 0xd155c73, 0xcfc5bea, 0xce35ae1, 0xcca5959, 0xcb15752,
+  0xc9854cf,
+  0xc7f51cf, 0xc664e53, 0xc4d4a5d, 0xc3445ee, 0xc1b4107, 0xc023ba7, 0xbe935d2,
+  0xbd02f87,
+  0xbb728c7, 0xb9e2193, 0xb8519ed, 0xb6c11d5, 0xb53094d, 0xb3a0055, 0xb20f6ee,
+  0xb07ed19,
+  0xaeee2d7, 0xad5d829, 0xabccd11, 0xaa3c18e, 0xa8ab5a2, 0xa71a94f, 0xa589c94,
+  0xa3f8f73,
+  0xa2681ed, 0xa0d7403, 0x9f465b5, 0x9db5706, 0x9c247f5, 0x9a93884, 0x99028b3,
+  0x9771884,
+  0x95e07f8, 0x944f70f, 0x92be5ca, 0x912d42c, 0x8f9c233, 0x8e0afe2, 0x8c79d3a,
+  0x8ae8a3a,
+  0x89576e5, 0x87c633c, 0x8634f3e, 0x84a3aee, 0x831264c, 0x8181159, 0x7fefc16,
+  0x7e5e685,
+  0x7ccd0a5, 0x7b3ba78, 0x79aa400, 0x7818d3c, 0x768762e, 0x74f5ed7, 0x7364738,
+  0x71d2f52,
+  0x7041726, 0x6eafeb4, 0x6d1e5fe, 0x6b8cd05, 0x69fb3c9, 0x6869a4c, 0x66d808f,
+  0x6546692,
+  0x63b4c57, 0x62231de, 0x6091729, 0x5effc38, 0x5d6e10c, 0x5bdc5a7, 0x5a4aa09,
+  0x58b8e34,
+  0x5727228, 0x55955e6, 0x540396f, 0x5271cc4, 0x50dffe7, 0x4f4e2d8, 0x4dbc597,
+  0x4c2a827,
+  0x4a98a88, 0x4906cbb, 0x4774ec1, 0x45e309a, 0x4451249, 0x42bf3cd, 0x412d528,
+  0x3f9b65b,
+  0x3e09767, 0x3c7784d, 0x3ae590d, 0x39539a9, 0x37c1a22, 0x362fa78, 0x349daac,
+  0x330bac1,
+  0x3179ab5, 0x2fe7a8c, 0x2e55a44, 0x2cc39e1, 0x2b31961, 0x299f8c7, 0x280d813,
+  0x267b747,
+  0x24e9662, 0x2357567, 0x21c5457, 0x2033331, 0x1ea11f7, 0x1d0f0ab, 0x1b7cf4d,
+  0x19eaddd,
+  0x1858c5e, 0x16c6ad0, 0x1534934, 0x13a278a, 0x12105d5, 0x107e414, 0xeec249,
+  0xd5a075,
+  0xbc7e99, 0xa35cb5, 0x8a3acb, 0x7118dc, 0x57f6e9, 0x3ed4f2, 0x25b2f8,
+  0xc90fe,
+
+};
+
+/**   
+ * @brief  Initialization function for the Q31 DCT4/IDCT4.  
+ * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.  
+ * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure  
+ * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure  
+ * @param[in]     N          length of the DCT4.  
+ * @param[in]     Nby2       half of the length of the DCT4.  
+ * @param[in]     normalize  normalizing factor.  
+ * @return		  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.  
+ * \par Normalizing factor:   
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.   
+ * Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes:   
+ * \image html dct4NormalizingQ31Table.gif   
+ */
+
+arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  q31_t *twiddlePtr[3] = { (q31_t *) WeightsQ31_128, (q31_t *) WeightsQ31_512,
+    (q31_t *) WeightsQ31_2048
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  q31_t *pCosFactor[3] =
+    { (q31_t *) cos_factorsQ31_128, (q31_t *) cos_factorsQ31_512,
+    (q31_t *) cos_factorsQ31_2048
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT Function */
+  arm_rfft_init_q31(S->pRfft, S->pCfft, S->N, 0, 1);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
new file mode 100644
index 0000000..75199b4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
@@ -0,0 +1,383 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_q15.c   
+*   
+* Description:	Processing function of DCT4 & IDCT4 Q15.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 DCT4/IDCT4.  
+ * @param[in]       *S             points to an instance of the Q15 DCT4 structure.  
+ * @param[in]       *pState        points to state buffer.  
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.  
+ * @return none.  
+ *    
+ * \par Input an output formats:   
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.   
+ * Number of bits downscaled, depends on the size of the transform.   
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:    
+ *   
+ * \image html dct4FormatsQ15Table.gif   
+ */
+
+void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer)
+{
+  uint32_t i;                                    /* Loop counter */
+  q15_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
+  q15_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
+  q15_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
+  q15_t in;                                      /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)   
+   * along with some pre-processing and post-processing.   
+   * Computational procedure is explained as follows:   
+   * (a) Pre-processing involves multiplying input with cos factor,   
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))   
+   *              where,   
+   *                 r(n) -- output of preprocessing   
+   *                 u(n) -- input to preprocessing(actual Source buffer)   
+   * (b) Calculation of DCT2 using FFT is divided into three steps:   
+   *                  Step1: Re-ordering of even and odd elements of input.   
+   *                  Step2: Calculating FFT of the re-ordered input.   
+   *                  Step3: Taking the real part of the product of FFT output and weights.   
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:   
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *                        where,   
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output   
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).   
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_mult_q15(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+  arm_shift_q15(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------   
+   * Step1: Re-ordering of even and odd elements as   
+   *             pState[i] =  pInlineBuffer[2*i] and   
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2   
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = (uint32_t) S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.   
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------   
+  *  Step3: Multiply the FFT output with the weights.   
+  *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.13 format.   
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+  arm_shift_q15(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = ((uint32_t) S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  i = ((uint32_t) S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = (uint32_t) S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------   
+  *  Step3: Multiply the FFT output with the weights.   
+  *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.13 format.   
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+  arm_shift_q15(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter */
+  i = ((uint32_t) S->N - 1u);
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
new file mode 100644
index 0000000..1f2c8ce
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
@@ -0,0 +1,384 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_q31.c   
+*   
+* Description:	Processing function of DCT4 & IDCT4 Q31.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 DCT4/IDCT4.  
+ * @param[in]       *S             points to an instance of the Q31 DCT4 structure.  
+ * @param[in]       *pState        points to state buffer.  
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.  
+ * @return none.  
+ * \par Input an output formats:   
+ * Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process,   
+ * as the conversion from DCT2 to DCT4 involves one subtraction.   
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.   
+ * Number of bits downscaled, depends on the size of the transform.   
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:    
+ *   
+ * \image html dct4FormatsQ31Table.gif   
+ */
+
+void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer)
+{
+  uint16_t i;                                    /* Loop counter */
+  q31_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
+  q31_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
+  q31_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
+  q31_t in;                                      /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)   
+   * along with some pre-processing and post-processing.   
+   * Computational procedure is explained as follows:   
+   * (a) Pre-processing involves multiplying input with cos factor,   
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))   
+   *              where,   
+   *                 r(n) -- output of preprocessing   
+   *                 u(n) -- input to preprocessing(actual Source buffer)   
+   * (b) Calculation of DCT2 using FFT is divided into three steps:   
+   *                  Step1: Re-ordering of even and odd elements of input.   
+   *                  Step2: Calculating FFT of the re-ordered input.   
+   *                  Step3: Taking the real part of the product of FFT output and weights.   
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:   
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *                        where,   
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output   
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).   
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_mult_q31(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+  arm_shift_q31(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------   
+   * Step1: Re-ordering of even and odd elements as   
+   *             pState[i] =  pInlineBuffer[2*i] and   
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2   
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.   
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+  /*----------------------------------------------------------------------   
+   *  Step3: Multiply the FFT output with the weights.   
+   *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.29 format.   
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+  arm_shift_q31(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = (S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  i = (S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+  /*----------------------------------------------------------------------   
+   *  Step3: Multiply the FFT output with the weights.   
+   *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.29 format.   
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+  arm_shift_q31(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* Initializing the loop counter */
+  i = (S->N - 1u);
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
new file mode 100644
index 0000000..c3c2f76
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
@@ -0,0 +1,383 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_f32.c   
+*   
+* Description:	RFFT & RIFFT Floating point process function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @defgroup RFFT_RIFFT Real FFT Functions   
+ *   
+ * \par   
+ * Complex FFT/IFFT typically assumes complex input and output. However many applications use real valued data in time domain.    
+ * Real FFT/IFFT efficiently process real valued sequences with the advantage of requirement of low memory and with less complexity.   
+ *   
+ * \par   
+ * This set of functions implements Real Fast Fourier Transforms(RFFT) and Real Inverse Fast Fourier Transform(RIFFT)   
+ * for Q15, Q31, and floating-point data types.     
+ *   
+ *   
+ * \par Algorithm:   
+ *   
+ * Real Fast Fourier Transform:   
+ * \par   
+ * Real FFT of N-point is calculated using CFFT of N/2-point and Split RFFT process as shown below figure.   
+ * \par   
+ * \image html RFFT.gif "Real Fast Fourier Transform"   
+ * \par   
+ * The RFFT functions operate on blocks of input and output data and each call to the function processes   
+ * fftLenR samples through the transform.  pSrc  points to input array containing fftLenR values.   
+ * pDst  points to output array containing 2*fftLenR values. \n  
+ * Input for real FFT is in the order of    
+ * 
{real[0], real[1], real[2], real[3], ..}
   
+ * Output for real FFT is complex and are in the order of   
+ * 
{real(0), imag(0), real(1), imag(1), ...}
    
+ *   
+ * Real Inverse Fast Fourier Transform:   
+ * \par   
+ * Real IFFT of N-point is calculated using Split RIFFT process and CFFT of N/2-point as shown below figure.   
+ * \par   
+ * \image html RIFFT.gif "Real Inverse Fast Fourier Transform"   
+ * \par   
+ * The RIFFT functions operate on blocks of input and output data and each call to the function processes   
+ * 2*fftLenR samples through the transform.  pSrc  points to input array containing 2*fftLenR values.   
+ * pDst  points to output array containing fftLenR values. \n   
+ * Input for real IFFT is complex and are in the order of  
+ * 
{real(0), imag(0), real(1), imag(1), ...}
  
+ *  Output for real IFFT is real and in the order of    
+ * 
{real[0], real[1], real[2], real[3], ..}
  
+ *   
+ * \par Lengths supported by the transform:  
+ * \par   
+ * Real FFT/IFFT supports the lengths [128, 512, 2048], as it internally uses CFFT/CIFFT.   
+ *   
+ * \par Instance Structure   
+ * A separate instance structure must be defined for each Instance but the twiddle factors can be reused.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Initializes twiddle factor tables.  
+ * - Initializes CFFT data structure fields.    
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Manually initialize the instance structure as follows:   
+ * 
   
+ *arm_rfft_instance_f32 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+ *arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+ *arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+ * 
   
+ * where fftLenReal length of RFFT/RIFFT; fftLenBy2 length of CFFT/CIFFT.    
+ * ifftFlagR Flag for selection of RFFT or RIFFT(Set ifftFlagR to calculate RIFFT otherwise calculates RFFT);   
+ * bitReverseFlagR Flag for selection of output order(Set bitReverseFlagR to output in normal order otherwise output in bit reversed order);    
+ * twidCoefRModifier modifier for twiddle factor table which supports 128, 512, 2048 RFFT lengths with same table;   
+ * pTwiddleARealpoints to A array of twiddle coefficients; pTwiddleBRealpoints to B array of twiddle coefficients;   
+ * pCfft points to the CFFT Instance structure. The CFFT structure also needs to be initialized, refer to arm_cfft_radix4_f32() for details regarding   
+ * static initialization of cfft structure.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the RFFT/RIFFT function.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/*--------------------------------------------------------------------   
+ *		Internal functions prototypes   
+ *--------------------------------------------------------------------*/
+
+void arm_split_rfft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier);
+void arm_split_rifft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier);
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the floating-point RFFT/RIFFT.  
+ * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.  
+ * @param[in]  *pSrc points to the input buffer.  
+ * @param[out] *pDst points to the output buffer.  
+ * @return none.  
+ */
+
+void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst)
+{
+  const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;
+
+
+  /* Calculation of Real IFFT of input */
+  if(S->ifftFlagR == 1u)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+
+    /* Complex radix-4 IFFT process */
+    arm_radix4_butterfly_inverse_f32(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier,
+                                     S_CFFT->onebyfftLen);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_f32(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+
+    /* Calculation of RFFT of input */
+
+    /* Complex radix-4 FFT process */
+    arm_radix4_butterfly_f32(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_f32(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+
+    /*  Real FFT core process */
+    arm_split_rfft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+/**   
+   * @} end of RFFT_RIFFT group   
+   */
+
+/**   
+ * @brief  Core Real FFT process   
+ * @param[in]   *pSrc 				points to the input buffer.   
+ * @param[in]   fftLen  			length of FFT.   
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.   
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ */
+
+void arm_split_rfft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  float32_t outR, outI;                          /* Temporary variables for output */
+  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
+  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
+  float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4u * fftLen) - 1u];      /* temp pointers for output buffer */
+  float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2u * fftLen) - 1u];      /* temp pointers for input buffer */
+
+
+  pSrc[2u * fftLen] = pSrc[0];
+  pSrc[(2u * fftLen) + 1u] = pSrc[1];
+
+  /* Init coefficient pointers */
+  pCoefA = &pATable[modifier * 2u];
+  pCoefB = &pBTable[modifier * 2u];
+
+  i = fftLen - 1u;
+
+  while(i > 0u)
+  {
+    /*   
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]   
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+    /* read pATable[2 * i] */
+    CoefA1 = *pCoefA++;
+    /* pATable[2 * i + 1] */
+    CoefA2 = *pCoefA;
+
+    /* pSrc[2 * i] * pATable[2 * i] */
+    outR = *pSrc1 * CoefA1;
+    /* pSrc[2 * i] * CoefA2 */
+    outI = *pSrc1++ * CoefA2;
+
+    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+    outR -= (*pSrc1 + *pSrc2) * CoefA2;
+    /* pSrc[2 * i + 1] * CoefA1 */
+    outI += *pSrc1++ * CoefA1;
+
+    CoefB1 = *pCoefB;
+
+    /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+    outI -= *pSrc2-- * CoefB1;
+    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+    outI -= *pSrc2 * CoefA2;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+    outR += *pSrc2-- * CoefB1;
+
+    /* write output */
+    *pDst1++ = outR;
+    *pDst1++ = outI;
+
+    /* write complex conjugate output */
+    *pDst2-- = -outI;
+    *pDst2-- = outR;
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    i--;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0.0f;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0.0f;
+
+}
+
+
+/**   
+ * @brief  Core Real IFFT process   
+ * @param[in]   *pSrc 				points to the input buffer.   
+ * @param[in]   fftLen  			length of FFT.  
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.  
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.  
+ * @param[out]  *pDst 				points to the output buffer.  
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.   
+ */
+
+void arm_split_rifft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier)
+{
+  float32_t outR, outI;                          /* Temporary variables for output */
+  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
+  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
+  float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2u * fftLen) + 1u];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  while(fftLen > 0u)
+  {
+    /*   
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+
+     */
+
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pSrc[2 * i] * CoefA1 */
+    outR = *pSrc1 * CoefA1;
+
+    /* - pSrc[2 * i] * CoefA2 */
+    outI = -(*pSrc1++) * CoefA2;
+
+    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+    outR += (*pSrc1 + *pSrc2) * CoefA2;
+
+    /* pSrc[2 * i + 1] * CoefA1 */
+    outI += (*pSrc1++) * CoefA1;
+
+    CoefB1 = *pCoefB;
+
+    /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+    outI -= *pSrc2-- * CoefB1;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+    outR += *pSrc2 * CoefB1;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+    outI += *pSrc2-- * CoefA2;
+
+    /* write output */
+    *pDst++ = outR;
+    *pDst++ = outI;
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    /* Decrement loop count */
+    fftLen--;
+  }
+
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
new file mode 100644
index 0000000..de0a47a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
@@ -0,0 +1,1707 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_init_f32.c   
+*   
+* Description:	RFFT & RIFFT Floating point initialisation function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+* \par   
+* Generation of realCoefA array:   
+* \par   
+* 	n = 1024   
+* 
for (i = 0; i < n; i++)   
+*  {   
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+*  } 
   
+*/
+
+
+
+static const float32_t realCoefA[2048] = {
+  0.500000000000000000f, -0.500000000000000000f, 0.498466014862060550f,
+  -0.499997645616531370f, 0.496932059526443480f, -0.499990582466125490f,
+  0.495398133993148800f, -0.499978810548782350f,
+  0.493864238262176510f, -0.499962359666824340f, 0.492330402135849000f,
+  -0.499941170215606690f, 0.490796625614166260f, -0.499915301799774170f,
+  0.489262968301773070f, -0.499884694814682010f,
+  0.487729400396347050f, -0.499849408864974980f, 0.486195921897888180f,
+  -0.499809414148330690f, 0.484662592411041260f, -0.499764710664749150f,
+  0.483129411935806270f, -0.499715298414230350f,
+  0.481596380472183230f, -0.499661177396774290f, 0.480063527822494510f,
+  -0.499602377414703370f, 0.478530883789062500f, -0.499538868665695190f,
+  0.476998418569564820f, -0.499470651149749760f,
+  0.475466161966323850f, -0.499397724866867070f, 0.473934143781661990f,
+  -0.499320119619369510f, 0.472402364015579220f, -0.499237775802612300f,
+  0.470870882272720340f, -0.499150782823562620f,
+  0.469339638948440550f, -0.499059051275253300f, 0.467808693647384640f,
+  -0.498962640762329100f, 0.466278046369552610f, -0.498861521482467650f,
+  0.464747726917266850f, -0.498755723237991330f,
+  0.463217705488204960f, -0.498645216226577760f, 0.461688071489334110f,
+  -0.498530030250549320f, 0.460158795118331910f, -0.498410135507583620f,
+  0.458629876375198360f, -0.498285561800003050f,
+  0.457101345062255860f, -0.498156309127807620f, 0.455573230981826780f,
+  -0.498022347688674930f, 0.454045534133911130f, -0.497883707284927370f,
+  0.452518254518508910f, -0.497740387916564940f,
+  0.450991421937942500f, -0.497592359781265260f, 0.449465066194534300f,
+  -0.497439652681350710f, 0.447939187288284300f, -0.497282296419143680f,
+  0.446413785219192500f, -0.497120231389999390f,
+  0.444888889789581300f, -0.496953487396240230f, 0.443364530801773070f,
+  -0.496782064437866210f, 0.441840678453445430f, -0.496605962514877320f,
+  0.440317392349243160f, -0.496425211429595950f,
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+  0.384470939636230470f, 0.486469984054565430f, 0.385963946580886840f,
+  0.486822128295898440f, 0.387458056211471560f, 0.487169682979583740f,
+  0.388953179121017460f, 0.487512677907943730f,
+  0.390449374914169310f, 0.487851053476333620f, 0.391946613788604740f,
+  0.488184869289398190f, 0.393444836139678960f, 0.488514065742492680f,
+  0.394944071769714360f, 0.488838672637939450f,
+  0.396444320678710940f, 0.489158689975738530f, 0.397945523262023930f,
+  0.489474087953567500f, 0.399447679519653320f, 0.489784896373748780f,
+  0.400950789451599120f, 0.490091055631637570f,
+  0.402454853057861330f, 0.490392625331878660f, 0.403959810733795170f,
+  0.490689605474472050f, 0.405465662479400630f, 0.490981936454772950f,
+  0.406972438097000120f, 0.491269648075103760f,
+  0.408480048179626460f, 0.491552740335464480f, 0.409988552331924440f,
+  0.491831213235855100f, 0.411497890949249270f, 0.492105036973953250f,
+  0.413008064031600950f, 0.492374241352081300f,
+  0.414519041776657100f, 0.492638826370239260f, 0.416030853986740110f,
+  0.492898762226104740f, 0.417543441057205200f, 0.493154048919677730f,
+  0.419056802988052370f, 0.493404686450958250f,
+  0.420570939779281620f, 0.493650704622268680f, 0.422085791826248170f,
+  0.493892073631286620f, 0.423601418733596800f, 0.494128793478012080f,
+  0.425117731094360350f, 0.494360834360122680f,
+  0.426634758710861210f, 0.494588255882263180f, 0.428152471780776980f,
+  0.494810998439788820f, 0.429670870304107670f, 0.495029091835021970f,
+  0.431189924478530880f, 0.495242536067962650f,
+  0.432709634304046630f, 0.495451331138610840f, 0.434229999780654910f,
+  0.495655417442321780f, 0.435750931501388550f, 0.495854884386062620f,
+  0.437272518873214720f, 0.496049642562866210f,
+  0.438794672489166260f, 0.496239781379699710f, 0.440317392349243160f,
+  0.496425211429595950f, 0.441840678453445430f, 0.496605962514877320f,
+  0.443364530801773070f, 0.496782064437866210f,
+  0.444888889789581300f, 0.496953487396240230f, 0.446413785219192500f,
+  0.497120231389999390f, 0.447939187288284300f, 0.497282296419143680f,
+  0.449465066194534300f, 0.497439652681350710f,
+  0.450991421937942500f, 0.497592359781265260f, 0.452518254518508910f,
+  0.497740387916564940f, 0.454045534133911130f, 0.497883707284927370f,
+  0.455573230981826780f, 0.498022347688674930f,
+  0.457101345062255860f, 0.498156309127807620f, 0.458629876375198360f,
+  0.498285561800003050f, 0.460158795118331910f, 0.498410135507583620f,
+  0.461688071489334110f, 0.498530030250549320f,
+  0.463217705488204960f, 0.498645216226577760f, 0.464747726917266850f,
+  0.498755723237991330f, 0.466278046369552610f, 0.498861521482467650f,
+  0.467808693647384640f, 0.498962640762329100f,
+  0.469339638948440550f, 0.499059051275253300f, 0.470870882272720340f,
+  0.499150782823562620f, 0.472402364015579220f, 0.499237775802612300f,
+  0.473934143781661990f, 0.499320119619369510f,
+  0.475466161966323850f, 0.499397724866867070f, 0.476998418569564820f,
+  0.499470651149749760f, 0.478530883789062500f, 0.499538868665695190f,
+  0.480063527822494510f, 0.499602377414703370f,
+  0.481596380472183230f, 0.499661177396774290f, 0.483129411935806270f,
+  0.499715298414230350f, 0.484662592411041260f, 0.499764710664749150f,
+  0.486195921897888180f, 0.499809414148330690f,
+  0.487729400396347050f, 0.499849408864974980f, 0.489262968301773070f,
+  0.499884694814682010f, 0.490796625614166260f, 0.499915301799774170f,
+  0.492330402135849000f, 0.499941170215606690f,
+  0.493864238262176510f, 0.499962359666824340f, 0.495398133993148800f,
+  0.499978810548782350f, 0.496932059526443480f, 0.499990582466125490f,
+  0.498466014862060550f, 0.499997645616531370f
+};
+
+
+/**   
+* \par  
+* Generation of realCoefB array:   
+* \par  
+* n = 1024   
+* 
for (i = 0; i < n; i++)   
+* {   
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+*  } 
   
+*   
+*/
+static const float32_t realCoefB[2048] = {
+  0.500000000000000000f, 0.500000000000000000f, 0.501533985137939450f,
+  0.499997645616531370f, 0.503067970275878910f, 0.499990582466125490f,
+  0.504601895809173580f, 0.499978810548782350f,
+  0.506135761737823490f, 0.499962359666824340f, 0.507669627666473390f,
+  0.499941170215606690f, 0.509203374385833740f, 0.499915301799774170f,
+  0.510737061500549320f, 0.499884694814682010f,
+  0.512270629405975340f, 0.499849408864974980f, 0.513804078102111820f,
+  0.499809414148330690f, 0.515337407588958740f, 0.499764710664749150f,
+  0.516870558261871340f, 0.499715298414230350f,
+  0.518403589725494380f, 0.499661177396774290f, 0.519936442375183110f,
+  0.499602377414703370f, 0.521469116210937500f, 0.499538868665695190f,
+  0.523001611232757570f, 0.499470651149749760f,
+  0.524533808231353760f, 0.499397724866867070f, 0.526065826416015630f,
+  0.499320119619369510f, 0.527597606182098390f, 0.499237775802612300f,
+  0.529129147529602050f, 0.499150782823562620f,
+  0.530660390853881840f, 0.499059051275253300f, 0.532191336154937740f,
+  0.498962640762329100f, 0.533721983432769780f, 0.498861521482467650f,
+  0.535252273082733150f, 0.498755723237991330f,
+  0.536782264709472660f, 0.498645216226577760f, 0.538311958312988280f,
+  0.498530030250549320f, 0.539841234683990480f, 0.498410135507583620f,
+  0.541370153427124020f, 0.498285561800003050f,
+  0.542898654937744140f, 0.498156309127807620f, 0.544426798820495610f,
+  0.498022347688674930f, 0.545954465866088870f, 0.497883707284927370f,
+  0.547481775283813480f, 0.497740387916564940f,
+  0.549008548259735110f, 0.497592359781265260f, 0.550534904003143310f,
+  0.497439652681350710f, 0.552060842514038090f, 0.497282296419143680f,
+  0.553586184978485110f, 0.497120231389999390f,
+  0.555111110210418700f, 0.496953487396240230f, 0.556635499000549320f,
+  0.496782064437866210f, 0.558159291744232180f, 0.496605962514877320f,
+  0.559682607650756840f, 0.496425211429595950f,
+  0.561205327510833740f, 0.496239781379699710f, 0.562727510929107670f,
+  0.496049642562866210f, 0.564249038696289060f, 0.495854884386062620f,
+  0.565770030021667480f, 0.495655417442321780f,
+  0.567290365695953370f, 0.495451331138610840f, 0.568810045719146730f,
+  0.495242536067962650f, 0.570329129695892330f, 0.495029091835021970f,
+  0.571847498416900630f, 0.494810998439788820f,
+  0.573365211486816410f, 0.494588255882263180f, 0.574882268905639650f,
+  0.494360834360122680f, 0.576398611068725590f, 0.494128793478012080f,
+  0.577914178371429440f, 0.493892073631286620f,
+  0.579429090023040770f, 0.493650704622268680f, 0.580943167209625240f,
+  0.493404686450958250f, 0.582456588745117190f, 0.493154048919677730f,
+  0.583969175815582280f, 0.492898762226104740f,
+  0.585480928421020510f, 0.492638826370239260f, 0.586991965770721440f,
+  0.492374241352081300f, 0.588502109050750730f, 0.492105036973953250f,
+  0.590011477470397950f, 0.491831213235855100f,
+  0.591519951820373540f, 0.491552740335464480f, 0.593027591705322270f,
+  0.491269648075103760f, 0.594534337520599370f, 0.490981936454772950f,
+  0.596040189266204830f, 0.490689605474472050f,
+  0.597545146942138670f, 0.490392625331878660f, 0.599049210548400880f,
+  0.490091055631637570f, 0.600552320480346680f, 0.489784896373748780f,
+  0.602054476737976070f, 0.489474087953567500f,
+  0.603555679321289060f, 0.489158689975738530f, 0.605055928230285640f,
+  0.488838672637939450f, 0.606555163860321040f, 0.488514065742492680f,
+  0.608053386211395260f, 0.488184869289398190f,
+  0.609550595283508300f, 0.487851053476333620f, 0.611046791076660160f,
+  0.487512677907943730f, 0.612541973590850830f, 0.487169682979583740f,
+  0.614036023616790770f, 0.486822128295898440f,
+  0.615529060363769530f, 0.486469984054565430f, 0.617020964622497560f,
+  0.486113250255584720f, 0.618511795997619630f, 0.485751956701278690f,
+  0.620001494884490970f, 0.485386073589324950f,
+  0.621490061283111570f, 0.485015630722045900f, 0.622977554798126220f,
+  0.484640628099441530f, 0.624463796615600590f, 0.484261035919189450f,
+  0.625948905944824220f, 0.483876913785934450f,
+  0.627432823181152340f, 0.483488231897354130f, 0.628915548324584960f,
+  0.483094990253448490f, 0.630397081375122070f, 0.482697218656539920f,
+  0.631877362728118900f, 0.482294887304306030f,
+  0.633356392383575440f, 0.481888025999069210f, 0.634834170341491700f,
+  0.481476634740829470f, 0.636310696601867680f, 0.481060713529586790f,
+  0.637785911560058590f, 0.480640232563018800f,
+  0.639259815216064450f, 0.480215251445770260f, 0.640732467174530030f,
+  0.479785770177841190f, 0.642203748226165770f, 0.479351729154586790f,
+  0.643673717975616460f, 0.478913217782974240f,
+  0.645142316818237300f, 0.478470176458358760f, 0.646609604358673100f,
+  0.478022634983062740f, 0.648075461387634280f, 0.477570593357086180f,
+  0.649539887905120850f, 0.477114051580429080f,
+  0.651003003120422360f, 0.476653009653091430f, 0.652464628219604490f,
+  0.476187497377395630f, 0.653924822807312010f, 0.475717514753341670f,
+  0.655383586883544920f, 0.475243031978607180f,
+  0.656840860843658450f, 0.474764078855514530f, 0.658296704292297360f,
+  0.474280685186386110f, 0.659750998020172120f, 0.473792791366577150f,
+  0.661203861236572270f, 0.473300457000732420f,
+  0.662655174732208250f, 0.472803652286529540f, 0.664104938507080080f,
+  0.472302407026290890f, 0.665553152561187740f, 0.471796721220016480f,
+  0.666999816894531250f, 0.471286594867706300f,
+  0.668444931507110600f, 0.470772027969360350f, 0.669888436794281010f,
+  0.470253020524978640f, 0.671330332756042480f, 0.469729602336883540f,
+  0.672770678997039790f, 0.469201773405075070f,
+  0.674209356307983400f, 0.468669503927230830f, 0.675646364688873290f,
+  0.468132823705673220f, 0.677081763744354250f, 0.467591762542724610f,
+  0.678515493869781490f, 0.467046260833740230f,
+  0.679947495460510250f, 0.466496407985687260f, 0.681377887725830080f,
+  0.465942144393920900f, 0.682806491851806640f, 0.465383470058441160f,
+  0.684233427047729490f, 0.464820444583892820f,
+  0.685658574104309080f, 0.464253038167953490f, 0.687082052230834960f,
+  0.463681250810623170f, 0.688503682613372800f, 0.463105112314224240f,
+  0.689923584461212160f, 0.462524622678756710f,
+  0.691341698169708250f, 0.461939752101898190f, 0.692758023738861080f,
+  0.461350560188293460f, 0.694172501564025880f, 0.460757017135620120f,
+  0.695585191249847410f, 0.460159152746200560f,
+  0.696996033191680910f, 0.459556937217712400f, 0.698404967784881590f,
+  0.458950400352478030f, 0.699812114238739010f, 0.458339542150497440f,
+  0.701217353343963620f, 0.457724362611770630f,
+  0.702620685100555420f, 0.457104891538620000f, 0.704022109508514400f,
+  0.456481099128723140f, 0.705421566963195800f, 0.455853015184402470f,
+  0.706819176673889160f, 0.455220639705657960f,
+  0.708214759826660160f, 0.454584002494812010f, 0.709608435630798340f,
+  0.453943043947219850f, 0.711000144481658940f, 0.453297853469848630f,
+  0.712389826774597170f, 0.452648371458053590f,
+  0.713777542114257810f, 0.451994657516479490f, 0.715163230895996090f,
+  0.451336652040481570f, 0.716546893119812010f, 0.450674414634704590f,
+  0.717928528785705570f, 0.450007945299148560f,
+  0.719308137893676760f, 0.449337244033813480f, 0.720685660839080810f,
+  0.448662281036376950f, 0.722061097621917720f, 0.447983115911483760f,
+  0.723434448242187500f, 0.447299748659133910f,
+  0.724805653095245360f, 0.446612149477005000f, 0.726174771785736080f,
+  0.445920348167419430f, 0.727541804313659670f, 0.445224374532699580f,
+  0.728906631469726560f, 0.444524168968200680f,
+  0.730269372463226320f, 0.443819820880889890f, 0.731629908084869380f,
+  0.443111270666122440f, 0.732988238334655760f, 0.442398548126220700f,
+  0.734344422817230220f, 0.441681683063507080f,
+  0.735698342323303220f, 0.440960645675659180f, 0.737050116062164310f,
+  0.440235435962677000f, 0.738399624824523930f, 0.439506113529205320f,
+  0.739746868610382080f, 0.438772648572921750f,
+  0.741091907024383540f, 0.438035041093826290f, 0.742434620857238770f,
+  0.437293320894241330f, 0.743775069713592530f, 0.436547487974166870f,
+  0.745113253593444820f, 0.435797542333602910f,
+  0.746449112892150880f, 0.435043483972549440f, 0.747782647609710690f,
+  0.434285342693328860f, 0.749113857746124270f, 0.433523118495941160f,
+  0.750442683696746830f, 0.432756811380386350f,
+  0.751769185066223140f, 0.431986421346664430f, 0.753093302249908450f,
+  0.431211978197097780f, 0.754415094852447510f, 0.430433481931686400f,
+  0.755734443664550780f, 0.429650902748107910f,
+  0.757051348686218260f, 0.428864300251007080f, 0.758365929126739500f,
+  0.428073674440383910f, 0.759678006172180180f, 0.427278995513916020f,
+  0.760987639427185060f, 0.426480293273925780f,
+  0.762294828891754150f, 0.425677597522735600f, 0.763599574565887450f,
+  0.424870878458023070f, 0.764901816844940190f, 0.424060165882110600f,
+  0.766201555728912350f, 0.423245459794998170f,
+  0.767498791217803960f, 0.422426789999008180f, 0.768793523311614990f,
+  0.421604126691818240f, 0.770085752010345460f, 0.420777499675750730f,
+  0.771375417709350590f, 0.419946908950805660f,
+  0.772662520408630370f, 0.419112354516983030f, 0.773947000503540040f,
+  0.418273866176605220f, 0.775228977203369140f, 0.417431443929672240f,
+  0.776508331298828130f, 0.416585087776184080f,
+  0.777785122394561770f, 0.415734797716140750f, 0.779059290885925290f,
+  0.414880603551864620f, 0.780330777168273930f, 0.414022535085678100f,
+  0.781599700450897220f, 0.413160532712936400f,
+  0.782865881919860840f, 0.412294656038284300f, 0.784129500389099120f,
+  0.411424905061721800f, 0.785390377044677730f, 0.410551249980926510f,
+  0.786648571491241460f, 0.409673750400543210f,
+  0.787904083728790280f, 0.408792406320571900f, 0.789156913757324220f,
+  0.407907217741012570f, 0.790407001972198490f, 0.407018154859542850f,
+  0.791654348373413090f, 0.406125307083129880f,
+  0.792898952960968020f, 0.405228585004806520f, 0.794140756130218510f,
+  0.404328078031539920f, 0.795379877090454100f, 0.403423786163330080f,
+  0.796616137027740480f, 0.402515679597854610f,
+  0.797849655151367190f, 0.401603758335113530f, 0.799080371856689450f,
+  0.400688081979751590f, 0.800308227539062500f, 0.399768620729446410f,
+  0.801533281803131100f, 0.398845434188842770f,
+  0.802755534648895260f, 0.397918462753295900f, 0.803974866867065430f,
+  0.396987736225128170f, 0.805191397666931150f, 0.396053284406661990f,
+  0.806405067443847660f, 0.395115107297897340f,
+  0.807615816593170170f, 0.394173204898834230f, 0.808823645114898680f,
+  0.393227607011795040f, 0.810028612613677980f, 0.392278283834457400f,
+  0.811230659484863280f, 0.391325294971466060f,
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+  0.787904083728790280f, -0.408792406320571900f, 0.786648571491241460f,
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+  0.708214759826660160f, -0.454584002494812010f, 0.706819176673889160f,
+  -0.455220639705657960f, 0.705421566963195800f, -0.455853015184402470f,
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+  -0.460159152746200560f, 0.694172501564025880f, -0.460757017135620120f,
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+  0.691341698169708250f, -0.461939752101898190f, 0.689923584461212160f,
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+  -0.475243031978607180f, 0.653924822807312010f, -0.475717514753341670f,
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+  0.646609604358673100f, -0.478022634983062740f,
+  0.645142316818237300f, -0.478470176458358760f, 0.643673717975616460f,
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+  0.640732467174530030f, -0.479785770177841190f,
+  0.639259815216064450f, -0.480215251445770260f, 0.637785911560058590f,
+  -0.480640232563018800f, 0.636310696601867680f, -0.481060713529586790f,
+  0.634834170341491700f, -0.481476634740829470f,
+  0.633356392383575440f, -0.481888025999069210f, 0.631877362728118900f,
+  -0.482294887304306030f, 0.630397081375122070f, -0.482697218656539920f,
+  0.628915548324584960f, -0.483094990253448490f,
+  0.627432823181152340f, -0.483488231897354130f, 0.625948905944824220f,
+  -0.483876913785934450f, 0.624463796615600590f, -0.484261035919189450f,
+  0.622977554798126220f, -0.484640628099441530f,
+  0.621490061283111570f, -0.485015630722045900f, 0.620001494884490970f,
+  -0.485386073589324950f, 0.618511795997619630f, -0.485751956701278690f,
+  0.617020964622497560f, -0.486113250255584720f,
+  0.615529060363769530f, -0.486469984054565430f, 0.614036023616790770f,
+  -0.486822128295898440f, 0.612541973590850830f, -0.487169682979583740f,
+  0.611046791076660160f, -0.487512677907943730f,
+  0.609550595283508300f, -0.487851053476333620f, 0.608053386211395260f,
+  -0.488184869289398190f, 0.606555163860321040f, -0.488514065742492680f,
+  0.605055928230285640f, -0.488838672637939450f,
+  0.603555679321289060f, -0.489158689975738530f, 0.602054476737976070f,
+  -0.489474087953567500f, 0.600552320480346680f, -0.489784896373748780f,
+  0.599049210548400880f, -0.490091055631637570f,
+  0.597545146942138670f, -0.490392625331878660f, 0.596040189266204830f,
+  -0.490689605474472050f, 0.594534337520599370f, -0.490981936454772950f,
+  0.593027591705322270f, -0.491269648075103760f,
+  0.591519951820373540f, -0.491552740335464480f, 0.590011477470397950f,
+  -0.491831213235855100f, 0.588502109050750730f, -0.492105036973953250f,
+  0.586991965770721440f, -0.492374241352081300f,
+  0.585480928421020510f, -0.492638826370239260f, 0.583969175815582280f,
+  -0.492898762226104740f, 0.582456588745117190f, -0.493154048919677730f,
+  0.580943167209625240f, -0.493404686450958250f,
+  0.579429090023040770f, -0.493650704622268680f, 0.577914178371429440f,
+  -0.493892073631286620f, 0.576398611068725590f, -0.494128793478012080f,
+  0.574882268905639650f, -0.494360834360122680f,
+  0.573365211486816410f, -0.494588255882263180f, 0.571847498416900630f,
+  -0.494810998439788820f, 0.570329129695892330f, -0.495029091835021970f,
+  0.568810045719146730f, -0.495242536067962650f,
+  0.567290365695953370f, -0.495451331138610840f, 0.565770030021667480f,
+  -0.495655417442321780f, 0.564249038696289060f, -0.495854884386062620f,
+  0.562727510929107670f, -0.496049642562866210f,
+  0.561205327510833740f, -0.496239781379699710f, 0.559682607650756840f,
+  -0.496425211429595950f, 0.558159291744232180f, -0.496605962514877320f,
+  0.556635499000549320f, -0.496782064437866210f,
+  0.555111110210418700f, -0.496953487396240230f, 0.553586184978485110f,
+  -0.497120231389999390f, 0.552060842514038090f, -0.497282296419143680f,
+  0.550534904003143310f, -0.497439652681350710f,
+  0.549008548259735110f, -0.497592359781265260f, 0.547481775283813480f,
+  -0.497740387916564940f, 0.545954465866088870f, -0.497883707284927370f,
+  0.544426798820495610f, -0.498022347688674930f,
+  0.542898654937744140f, -0.498156309127807620f, 0.541370153427124020f,
+  -0.498285561800003050f, 0.539841234683990480f, -0.498410135507583620f,
+  0.538311958312988280f, -0.498530030250549320f,
+  0.536782264709472660f, -0.498645216226577760f, 0.535252273082733150f,
+  -0.498755723237991330f, 0.533721983432769780f, -0.498861521482467650f,
+  0.532191336154937740f, -0.498962640762329100f,
+  0.530660390853881840f, -0.499059051275253300f, 0.529129147529602050f,
+  -0.499150782823562620f, 0.527597606182098390f, -0.499237775802612300f,
+  0.526065826416015630f, -0.499320119619369510f,
+  0.524533808231353760f, -0.499397724866867070f, 0.523001611232757570f,
+  -0.499470651149749760f, 0.521469116210937500f, -0.499538868665695190f,
+  0.519936442375183110f, -0.499602377414703370f,
+  0.518403589725494380f, -0.499661177396774290f, 0.516870558261871340f,
+  -0.499715298414230350f, 0.515337407588958740f, -0.499764710664749150f,
+  0.513804078102111820f, -0.499809414148330690f,
+  0.512270629405975340f, -0.499849408864974980f, 0.510737061500549320f,
+  -0.499884694814682010f, 0.509203374385833740f, -0.499915301799774170f,
+  0.507669627666473390f, -0.499941170215606690f,
+  0.506135761737823490f, -0.499962359666824340f, 0.504601895809173580f,
+  -0.499978810548782350f, 0.503067970275878910f, -0.499990582466125490f,
+  0.501533985137939450f, -0.499997645616531370f
+};
+
+
+
+/**   
+* @brief  Initialization function for the floating-point RFFT/RIFFT.  
+* @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.  
+* @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.  
+* @param[in]     fftLenReal     length of the FFT.  
+* @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.  
+*   
+* \par Description:  
+* \par  
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.   
+* \par   
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.   
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.  
+* \par   
+* This function also initializes Twiddle factor table.    
+*/
+
+arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (float32_t *) realCoefA;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (float32_t *) realCoefB;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+    /* Init table modifier value */
+  case 2048u:
+    S->twidCoefRModifier = 1u;
+    break;
+  case 512u:
+    S->twidCoefRModifier = 4u;
+    break;
+  case 128u:
+    S->twidCoefRModifier = 16u;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if(S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1u, 0u);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0u, 0u);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
new file mode 100644
index 0000000..843a33b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
@@ -0,0 +1,688 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_init_q15.c   
+*   
+* Description:	RFFT & RIFFT Q15 initialisation function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+
+
+/**   
+* \par   
+* Generation floating point real_CoefA array:   
+* \par   
+* n = 1024   
+* 
for (i = 0; i < n; i++)   
+*  {   
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+*  } 
   
+* \par   
+* Convert to fixed point Q15 format   
+*       round(pATable[i] * pow(2, 15))   
+*/
+
+
+static const q15_t realCoefAQ15[2048] = {
+
+  0x4000, 0xc000, 0x3fce, 0xc000, 0x3f9b, 0xc000, 0x3f69, 0xc001,
+  0x3f37, 0xc001, 0x3f05, 0xc002, 0x3ed2, 0xc003, 0x3ea0, 0xc004,
+  0x3e6e, 0xc005, 0x3e3c, 0xc006, 0x3e09, 0xc008, 0x3dd7, 0xc009,
+  0x3da5, 0xc00b, 0x3d73, 0xc00d, 0x3d40, 0xc00f, 0x3d0e, 0xc011,
+  0x3cdc, 0xc014, 0x3caa, 0xc016, 0x3c78, 0xc019, 0x3c45, 0xc01c,
+  0x3c13, 0xc01f, 0x3be1, 0xc022, 0x3baf, 0xc025, 0x3b7d, 0xc029,
+  0x3b4b, 0xc02c, 0x3b19, 0xc030, 0x3ae6, 0xc034, 0x3ab4, 0xc038,
+  0x3a82, 0xc03c, 0x3a50, 0xc041, 0x3a1e, 0xc045, 0x39ec, 0xc04a,
+  0x39ba, 0xc04f, 0x3988, 0xc054, 0x3956, 0xc059, 0x3924, 0xc05e,
+  0x38f2, 0xc064, 0x38c0, 0xc069, 0x388e, 0xc06f, 0x385c, 0xc075,
+  0x382a, 0xc07b, 0x37f9, 0xc081, 0x37c7, 0xc088, 0x3795, 0xc08e,
+  0x3763, 0xc095, 0x3731, 0xc09c, 0x36ff, 0xc0a3, 0x36ce, 0xc0aa,
+  0x369c, 0xc0b1, 0x366a, 0xc0b9, 0x3639, 0xc0c0, 0x3607, 0xc0c8,
+  0x35d5, 0xc0d0, 0x35a4, 0xc0d8, 0x3572, 0xc0e0, 0x3540, 0xc0e9,
+  0x350f, 0xc0f1, 0x34dd, 0xc0fa, 0x34ac, 0xc103, 0x347b, 0xc10c,
+  0x3449, 0xc115, 0x3418, 0xc11e, 0x33e6, 0xc128, 0x33b5, 0xc131,
+  0x3384, 0xc13b, 0x3352, 0xc145, 0x3321, 0xc14f, 0x32f0, 0xc159,
+  0x32bf, 0xc163, 0x328e, 0xc16e, 0x325c, 0xc178, 0x322b, 0xc183,
+  0x31fa, 0xc18e, 0x31c9, 0xc199, 0x3198, 0xc1a4, 0x3167, 0xc1b0,
+  0x3136, 0xc1bb, 0x3105, 0xc1c7, 0x30d5, 0xc1d3, 0x30a4, 0xc1df,
+  0x3073, 0xc1eb, 0x3042, 0xc1f7, 0x3012, 0xc204, 0x2fe1, 0xc210,
+  0x2fb0, 0xc21d, 0x2f80, 0xc22a, 0x2f4f, 0xc237, 0x2f1f, 0xc244,
+  0x2eee, 0xc251, 0x2ebe, 0xc25f, 0x2e8d, 0xc26d, 0x2e5d, 0xc27a,
+  0x2e2d, 0xc288, 0x2dfc, 0xc296, 0x2dcc, 0xc2a5, 0x2d9c, 0xc2b3,
+  0x2d6c, 0xc2c1, 0x2d3c, 0xc2d0, 0x2d0c, 0xc2df, 0x2cdc, 0xc2ee,
+  0x2cac, 0xc2fd, 0x2c7c, 0xc30c, 0x2c4c, 0xc31c, 0x2c1c, 0xc32b,
+  0x2bed, 0xc33b, 0x2bbd, 0xc34b, 0x2b8d, 0xc35b, 0x2b5e, 0xc36b,
+  0x2b2e, 0xc37b, 0x2aff, 0xc38c, 0x2acf, 0xc39c, 0x2aa0, 0xc3ad,
+  0x2a70, 0xc3be, 0x2a41, 0xc3cf, 0x2a12, 0xc3e0, 0x29e3, 0xc3f1,
+  0x29b4, 0xc403, 0x2984, 0xc414, 0x2955, 0xc426, 0x2926, 0xc438,
+  0x28f7, 0xc44a, 0x28c9, 0xc45c, 0x289a, 0xc46e, 0x286b, 0xc481,
+  0x283c, 0xc493, 0x280e, 0xc4a6, 0x27df, 0xc4b9, 0x27b1, 0xc4cc,
+  0x2782, 0xc4df, 0x2754, 0xc4f2, 0x2725, 0xc506, 0x26f7, 0xc51a,
+  0x26c9, 0xc52d, 0x269b, 0xc541, 0x266d, 0xc555, 0x263f, 0xc569,
+  0x2611, 0xc57e, 0x25e3, 0xc592, 0x25b5, 0xc5a7, 0x2587, 0xc5bb,
+  0x2559, 0xc5d0, 0x252c, 0xc5e5, 0x24fe, 0xc5fa, 0x24d0, 0xc610,
+  0x24a3, 0xc625, 0x2476, 0xc63b, 0x2448, 0xc650, 0x241b, 0xc666,
+  0x23ee, 0xc67c, 0x23c1, 0xc692, 0x2394, 0xc6a8, 0x2367, 0xc6bf,
+  0x233a, 0xc6d5, 0x230d, 0xc6ec, 0x22e0, 0xc703, 0x22b3, 0xc71a,
+  0x2287, 0xc731, 0x225a, 0xc748, 0x222d, 0xc75f, 0x2201, 0xc777,
+  0x21d5, 0xc78f, 0x21a8, 0xc7a6, 0x217c, 0xc7be, 0x2150, 0xc7d6,
+  0x2124, 0xc7ee, 0x20f8, 0xc807, 0x20cc, 0xc81f, 0x20a0, 0xc838,
+  0x2074, 0xc850, 0x2049, 0xc869, 0x201d, 0xc882, 0x1ff1, 0xc89b,
+  0x1fc6, 0xc8b5, 0x1f9b, 0xc8ce, 0x1f6f, 0xc8e8, 0x1f44, 0xc901,
+  0x1f19, 0xc91b, 0x1eee, 0xc935, 0x1ec3, 0xc94f, 0x1e98, 0xc969,
+  0x1e6d, 0xc983, 0x1e42, 0xc99e, 0x1e18, 0xc9b8, 0x1ded, 0xc9d3,
+  0x1dc3, 0xc9ee, 0x1d98, 0xca09, 0x1d6e, 0xca24, 0x1d44, 0xca3f,
+  0x1d19, 0xca5b, 0x1cef, 0xca76, 0x1cc5, 0xca92, 0x1c9b, 0xcaad,
+  0x1c72, 0xcac9, 0x1c48, 0xcae5, 0x1c1e, 0xcb01, 0x1bf5, 0xcb1e,
+  0x1bcb, 0xcb3a, 0x1ba2, 0xcb56, 0x1b78, 0xcb73, 0x1b4f, 0xcb90,
+  0x1b26, 0xcbad, 0x1afd, 0xcbca, 0x1ad4, 0xcbe7, 0x1aab, 0xcc04,
+  0x1a82, 0xcc21, 0x1a5a, 0xcc3f, 0x1a31, 0xcc5d, 0x1a08, 0xcc7a,
+  0x19e0, 0xcc98, 0x19b8, 0xccb6, 0x198f, 0xccd4, 0x1967, 0xccf3,
+  0x193f, 0xcd11, 0x1917, 0xcd30, 0x18ef, 0xcd4e, 0x18c8, 0xcd6d,
+  0x18a0, 0xcd8c, 0x1878, 0xcdab, 0x1851, 0xcdca, 0x182a, 0xcde9,
+  0x1802, 0xce08, 0x17db, 0xce28, 0x17b4, 0xce47, 0x178d, 0xce67,
+  0x1766, 0xce87, 0x173f, 0xcea7, 0x1719, 0xcec7, 0x16f2, 0xcee7,
+  0x16cb, 0xcf07, 0x16a5, 0xcf28, 0x167f, 0xcf48, 0x1659, 0xcf69,
+  0x1632, 0xcf8a, 0x160c, 0xcfab, 0x15e6, 0xcfcc, 0x15c1, 0xcfed,
+  0x159b, 0xd00e, 0x1575, 0xd030, 0x1550, 0xd051, 0x152a, 0xd073,
+  0x1505, 0xd094, 0x14e0, 0xd0b6, 0x14bb, 0xd0d8, 0x1496, 0xd0fa,
+  0x1471, 0xd11c, 0x144c, 0xd13e, 0x1428, 0xd161, 0x1403, 0xd183,
+  0x13df, 0xd1a6, 0x13ba, 0xd1c9, 0x1396, 0xd1eb, 0x1372, 0xd20e,
+  0x134e, 0xd231, 0x132a, 0xd255, 0x1306, 0xd278, 0x12e2, 0xd29b,
+  0x12bf, 0xd2bf, 0x129b, 0xd2e2, 0x1278, 0xd306, 0x1255, 0xd32a,
+  0x1231, 0xd34e, 0x120e, 0xd372, 0x11eb, 0xd396, 0x11c9, 0xd3ba,
+  0x11a6, 0xd3df, 0x1183, 0xd403, 0x1161, 0xd428, 0x113e, 0xd44c,
+  0x111c, 0xd471, 0x10fa, 0xd496, 0x10d8, 0xd4bb, 0x10b6, 0xd4e0,
+  0x1094, 0xd505, 0x1073, 0xd52a, 0x1051, 0xd550, 0x1030, 0xd575,
+  0x100e, 0xd59b, 0xfed, 0xd5c1, 0xfcc, 0xd5e6, 0xfab, 0xd60c,
+  0xf8a, 0xd632, 0xf69, 0xd659, 0xf48, 0xd67f, 0xf28, 0xd6a5,
+  0xf07, 0xd6cb, 0xee7, 0xd6f2, 0xec7, 0xd719, 0xea7, 0xd73f,
+  0xe87, 0xd766, 0xe67, 0xd78d, 0xe47, 0xd7b4, 0xe28, 0xd7db,
+  0xe08, 0xd802, 0xde9, 0xd82a, 0xdca, 0xd851, 0xdab, 0xd878,
+  0xd8c, 0xd8a0, 0xd6d, 0xd8c8, 0xd4e, 0xd8ef, 0xd30, 0xd917,
+  0xd11, 0xd93f, 0xcf3, 0xd967, 0xcd4, 0xd98f, 0xcb6, 0xd9b8,
+  0xc98, 0xd9e0, 0xc7a, 0xda08, 0xc5d, 0xda31, 0xc3f, 0xda5a,
+  0xc21, 0xda82, 0xc04, 0xdaab, 0xbe7, 0xdad4, 0xbca, 0xdafd,
+  0xbad, 0xdb26, 0xb90, 0xdb4f, 0xb73, 0xdb78, 0xb56, 0xdba2,
+  0xb3a, 0xdbcb, 0xb1e, 0xdbf5, 0xb01, 0xdc1e, 0xae5, 0xdc48,
+  0xac9, 0xdc72, 0xaad, 0xdc9b, 0xa92, 0xdcc5, 0xa76, 0xdcef,
+  0xa5b, 0xdd19, 0xa3f, 0xdd44, 0xa24, 0xdd6e, 0xa09, 0xdd98,
+  0x9ee, 0xddc3, 0x9d3, 0xdded, 0x9b8, 0xde18, 0x99e, 0xde42,
+  0x983, 0xde6d, 0x969, 0xde98, 0x94f, 0xdec3, 0x935, 0xdeee,
+  0x91b, 0xdf19, 0x901, 0xdf44, 0x8e8, 0xdf6f, 0x8ce, 0xdf9b,
+  0x8b5, 0xdfc6, 0x89b, 0xdff1, 0x882, 0xe01d, 0x869, 0xe049,
+  0x850, 0xe074, 0x838, 0xe0a0, 0x81f, 0xe0cc, 0x807, 0xe0f8,
+  0x7ee, 0xe124, 0x7d6, 0xe150, 0x7be, 0xe17c, 0x7a6, 0xe1a8,
+  0x78f, 0xe1d5, 0x777, 0xe201, 0x75f, 0xe22d, 0x748, 0xe25a,
+  0x731, 0xe287, 0x71a, 0xe2b3, 0x703, 0xe2e0, 0x6ec, 0xe30d,
+  0x6d5, 0xe33a, 0x6bf, 0xe367, 0x6a8, 0xe394, 0x692, 0xe3c1,
+  0x67c, 0xe3ee, 0x666, 0xe41b, 0x650, 0xe448, 0x63b, 0xe476,
+  0x625, 0xe4a3, 0x610, 0xe4d0, 0x5fa, 0xe4fe, 0x5e5, 0xe52c,
+  0x5d0, 0xe559, 0x5bb, 0xe587, 0x5a7, 0xe5b5, 0x592, 0xe5e3,
+  0x57e, 0xe611, 0x569, 0xe63f, 0x555, 0xe66d, 0x541, 0xe69b,
+  0x52d, 0xe6c9, 0x51a, 0xe6f7, 0x506, 0xe725, 0x4f2, 0xe754,
+  0x4df, 0xe782, 0x4cc, 0xe7b1, 0x4b9, 0xe7df, 0x4a6, 0xe80e,
+  0x493, 0xe83c, 0x481, 0xe86b, 0x46e, 0xe89a, 0x45c, 0xe8c9,
+  0x44a, 0xe8f7, 0x438, 0xe926, 0x426, 0xe955, 0x414, 0xe984,
+  0x403, 0xe9b4, 0x3f1, 0xe9e3, 0x3e0, 0xea12, 0x3cf, 0xea41,
+  0x3be, 0xea70, 0x3ad, 0xeaa0, 0x39c, 0xeacf, 0x38c, 0xeaff,
+  0x37b, 0xeb2e, 0x36b, 0xeb5e, 0x35b, 0xeb8d, 0x34b, 0xebbd,
+  0x33b, 0xebed, 0x32b, 0xec1c, 0x31c, 0xec4c, 0x30c, 0xec7c,
+  0x2fd, 0xecac, 0x2ee, 0xecdc, 0x2df, 0xed0c, 0x2d0, 0xed3c,
+  0x2c1, 0xed6c, 0x2b3, 0xed9c, 0x2a5, 0xedcc, 0x296, 0xedfc,
+  0x288, 0xee2d, 0x27a, 0xee5d, 0x26d, 0xee8d, 0x25f, 0xeebe,
+  0x251, 0xeeee, 0x244, 0xef1f, 0x237, 0xef4f, 0x22a, 0xef80,
+  0x21d, 0xefb0, 0x210, 0xefe1, 0x204, 0xf012, 0x1f7, 0xf042,
+  0x1eb, 0xf073, 0x1df, 0xf0a4, 0x1d3, 0xf0d5, 0x1c7, 0xf105,
+  0x1bb, 0xf136, 0x1b0, 0xf167, 0x1a4, 0xf198, 0x199, 0xf1c9,
+  0x18e, 0xf1fa, 0x183, 0xf22b, 0x178, 0xf25c, 0x16e, 0xf28e,
+  0x163, 0xf2bf, 0x159, 0xf2f0, 0x14f, 0xf321, 0x145, 0xf352,
+  0x13b, 0xf384, 0x131, 0xf3b5, 0x128, 0xf3e6, 0x11e, 0xf418,
+  0x115, 0xf449, 0x10c, 0xf47b, 0x103, 0xf4ac, 0xfa, 0xf4dd,
+  0xf1, 0xf50f, 0xe9, 0xf540, 0xe0, 0xf572, 0xd8, 0xf5a4,
+  0xd0, 0xf5d5, 0xc8, 0xf607, 0xc0, 0xf639, 0xb9, 0xf66a,
+  0xb1, 0xf69c, 0xaa, 0xf6ce, 0xa3, 0xf6ff, 0x9c, 0xf731,
+  0x95, 0xf763, 0x8e, 0xf795, 0x88, 0xf7c7, 0x81, 0xf7f9,
+  0x7b, 0xf82a, 0x75, 0xf85c, 0x6f, 0xf88e, 0x69, 0xf8c0,
+  0x64, 0xf8f2, 0x5e, 0xf924, 0x59, 0xf956, 0x54, 0xf988,
+  0x4f, 0xf9ba, 0x4a, 0xf9ec, 0x45, 0xfa1e, 0x41, 0xfa50,
+  0x3c, 0xfa82, 0x38, 0xfab4, 0x34, 0xfae6, 0x30, 0xfb19,
+  0x2c, 0xfb4b, 0x29, 0xfb7d, 0x25, 0xfbaf, 0x22, 0xfbe1,
+  0x1f, 0xfc13, 0x1c, 0xfc45, 0x19, 0xfc78, 0x16, 0xfcaa,
+  0x14, 0xfcdc, 0x11, 0xfd0e, 0xf, 0xfd40, 0xd, 0xfd73,
+  0xb, 0xfda5, 0x9, 0xfdd7, 0x8, 0xfe09, 0x6, 0xfe3c,
+  0x5, 0xfe6e, 0x4, 0xfea0, 0x3, 0xfed2, 0x2, 0xff05,
+  0x1, 0xff37, 0x1, 0xff69, 0x0, 0xff9b, 0x0, 0xffce,
+  0x0, 0x0, 0x0, 0x32, 0x0, 0x65, 0x1, 0x97,
+  0x1, 0xc9, 0x2, 0xfb, 0x3, 0x12e, 0x4, 0x160,
+  0x5, 0x192, 0x6, 0x1c4, 0x8, 0x1f7, 0x9, 0x229,
+  0xb, 0x25b, 0xd, 0x28d, 0xf, 0x2c0, 0x11, 0x2f2,
+  0x14, 0x324, 0x16, 0x356, 0x19, 0x388, 0x1c, 0x3bb,
+  0x1f, 0x3ed, 0x22, 0x41f, 0x25, 0x451, 0x29, 0x483,
+  0x2c, 0x4b5, 0x30, 0x4e7, 0x34, 0x51a, 0x38, 0x54c,
+  0x3c, 0x57e, 0x41, 0x5b0, 0x45, 0x5e2, 0x4a, 0x614,
+  0x4f, 0x646, 0x54, 0x678, 0x59, 0x6aa, 0x5e, 0x6dc,
+  0x64, 0x70e, 0x69, 0x740, 0x6f, 0x772, 0x75, 0x7a4,
+  0x7b, 0x7d6, 0x81, 0x807, 0x88, 0x839, 0x8e, 0x86b,
+  0x95, 0x89d, 0x9c, 0x8cf, 0xa3, 0x901, 0xaa, 0x932,
+  0xb1, 0x964, 0xb9, 0x996, 0xc0, 0x9c7, 0xc8, 0x9f9,
+  0xd0, 0xa2b, 0xd8, 0xa5c, 0xe0, 0xa8e, 0xe9, 0xac0,
+  0xf1, 0xaf1, 0xfa, 0xb23, 0x103, 0xb54, 0x10c, 0xb85,
+  0x115, 0xbb7, 0x11e, 0xbe8, 0x128, 0xc1a, 0x131, 0xc4b,
+  0x13b, 0xc7c, 0x145, 0xcae, 0x14f, 0xcdf, 0x159, 0xd10,
+  0x163, 0xd41, 0x16e, 0xd72, 0x178, 0xda4, 0x183, 0xdd5,
+  0x18e, 0xe06, 0x199, 0xe37, 0x1a4, 0xe68, 0x1b0, 0xe99,
+  0x1bb, 0xeca, 0x1c7, 0xefb, 0x1d3, 0xf2b, 0x1df, 0xf5c,
+  0x1eb, 0xf8d, 0x1f7, 0xfbe, 0x204, 0xfee, 0x210, 0x101f,
+  0x21d, 0x1050, 0x22a, 0x1080, 0x237, 0x10b1, 0x244, 0x10e1,
+  0x251, 0x1112, 0x25f, 0x1142, 0x26d, 0x1173, 0x27a, 0x11a3,
+  0x288, 0x11d3, 0x296, 0x1204, 0x2a5, 0x1234, 0x2b3, 0x1264,
+  0x2c1, 0x1294, 0x2d0, 0x12c4, 0x2df, 0x12f4, 0x2ee, 0x1324,
+  0x2fd, 0x1354, 0x30c, 0x1384, 0x31c, 0x13b4, 0x32b, 0x13e4,
+  0x33b, 0x1413, 0x34b, 0x1443, 0x35b, 0x1473, 0x36b, 0x14a2,
+  0x37b, 0x14d2, 0x38c, 0x1501, 0x39c, 0x1531, 0x3ad, 0x1560,
+  0x3be, 0x1590, 0x3cf, 0x15bf, 0x3e0, 0x15ee, 0x3f1, 0x161d,
+  0x403, 0x164c, 0x414, 0x167c, 0x426, 0x16ab, 0x438, 0x16da,
+  0x44a, 0x1709, 0x45c, 0x1737, 0x46e, 0x1766, 0x481, 0x1795,
+  0x493, 0x17c4, 0x4a6, 0x17f2, 0x4b9, 0x1821, 0x4cc, 0x184f,
+  0x4df, 0x187e, 0x4f2, 0x18ac, 0x506, 0x18db, 0x51a, 0x1909,
+  0x52d, 0x1937, 0x541, 0x1965, 0x555, 0x1993, 0x569, 0x19c1,
+  0x57e, 0x19ef, 0x592, 0x1a1d, 0x5a7, 0x1a4b, 0x5bb, 0x1a79,
+  0x5d0, 0x1aa7, 0x5e5, 0x1ad4, 0x5fa, 0x1b02, 0x610, 0x1b30,
+  0x625, 0x1b5d, 0x63b, 0x1b8a, 0x650, 0x1bb8, 0x666, 0x1be5,
+  0x67c, 0x1c12, 0x692, 0x1c3f, 0x6a8, 0x1c6c, 0x6bf, 0x1c99,
+  0x6d5, 0x1cc6, 0x6ec, 0x1cf3, 0x703, 0x1d20, 0x71a, 0x1d4d,
+  0x731, 0x1d79, 0x748, 0x1da6, 0x75f, 0x1dd3, 0x777, 0x1dff,
+  0x78f, 0x1e2b, 0x7a6, 0x1e58, 0x7be, 0x1e84, 0x7d6, 0x1eb0,
+  0x7ee, 0x1edc, 0x807, 0x1f08, 0x81f, 0x1f34, 0x838, 0x1f60,
+  0x850, 0x1f8c, 0x869, 0x1fb7, 0x882, 0x1fe3, 0x89b, 0x200f,
+  0x8b5, 0x203a, 0x8ce, 0x2065, 0x8e8, 0x2091, 0x901, 0x20bc,
+  0x91b, 0x20e7, 0x935, 0x2112, 0x94f, 0x213d, 0x969, 0x2168,
+  0x983, 0x2193, 0x99e, 0x21be, 0x9b8, 0x21e8, 0x9d3, 0x2213,
+  0x9ee, 0x223d, 0xa09, 0x2268, 0xa24, 0x2292, 0xa3f, 0x22bc,
+  0xa5b, 0x22e7, 0xa76, 0x2311, 0xa92, 0x233b, 0xaad, 0x2365,
+  0xac9, 0x238e, 0xae5, 0x23b8, 0xb01, 0x23e2, 0xb1e, 0x240b,
+  0xb3a, 0x2435, 0xb56, 0x245e, 0xb73, 0x2488, 0xb90, 0x24b1,
+  0xbad, 0x24da, 0xbca, 0x2503, 0xbe7, 0x252c, 0xc04, 0x2555,
+  0xc21, 0x257e, 0xc3f, 0x25a6, 0xc5d, 0x25cf, 0xc7a, 0x25f8,
+  0xc98, 0x2620, 0xcb6, 0x2648, 0xcd4, 0x2671, 0xcf3, 0x2699,
+  0xd11, 0x26c1, 0xd30, 0x26e9, 0xd4e, 0x2711, 0xd6d, 0x2738,
+  0xd8c, 0x2760, 0xdab, 0x2788, 0xdca, 0x27af, 0xde9, 0x27d6,
+  0xe08, 0x27fe, 0xe28, 0x2825, 0xe47, 0x284c, 0xe67, 0x2873,
+  0xe87, 0x289a, 0xea7, 0x28c1, 0xec7, 0x28e7, 0xee7, 0x290e,
+  0xf07, 0x2935, 0xf28, 0x295b, 0xf48, 0x2981, 0xf69, 0x29a7,
+  0xf8a, 0x29ce, 0xfab, 0x29f4, 0xfcc, 0x2a1a, 0xfed, 0x2a3f,
+  0x100e, 0x2a65, 0x1030, 0x2a8b, 0x1051, 0x2ab0, 0x1073, 0x2ad6,
+  0x1094, 0x2afb, 0x10b6, 0x2b20, 0x10d8, 0x2b45, 0x10fa, 0x2b6a,
+  0x111c, 0x2b8f, 0x113e, 0x2bb4, 0x1161, 0x2bd8, 0x1183, 0x2bfd,
+  0x11a6, 0x2c21, 0x11c9, 0x2c46, 0x11eb, 0x2c6a, 0x120e, 0x2c8e,
+  0x1231, 0x2cb2, 0x1255, 0x2cd6, 0x1278, 0x2cfa, 0x129b, 0x2d1e,
+  0x12bf, 0x2d41, 0x12e2, 0x2d65, 0x1306, 0x2d88, 0x132a, 0x2dab,
+  0x134e, 0x2dcf, 0x1372, 0x2df2, 0x1396, 0x2e15, 0x13ba, 0x2e37,
+  0x13df, 0x2e5a, 0x1403, 0x2e7d, 0x1428, 0x2e9f, 0x144c, 0x2ec2,
+  0x1471, 0x2ee4, 0x1496, 0x2f06, 0x14bb, 0x2f28, 0x14e0, 0x2f4a,
+  0x1505, 0x2f6c, 0x152a, 0x2f8d, 0x1550, 0x2faf, 0x1575, 0x2fd0,
+  0x159b, 0x2ff2, 0x15c1, 0x3013, 0x15e6, 0x3034, 0x160c, 0x3055,
+  0x1632, 0x3076, 0x1659, 0x3097, 0x167f, 0x30b8, 0x16a5, 0x30d8,
+  0x16cb, 0x30f9, 0x16f2, 0x3119, 0x1719, 0x3139, 0x173f, 0x3159,
+  0x1766, 0x3179, 0x178d, 0x3199, 0x17b4, 0x31b9, 0x17db, 0x31d8,
+  0x1802, 0x31f8, 0x182a, 0x3217, 0x1851, 0x3236, 0x1878, 0x3255,
+  0x18a0, 0x3274, 0x18c8, 0x3293, 0x18ef, 0x32b2, 0x1917, 0x32d0,
+  0x193f, 0x32ef, 0x1967, 0x330d, 0x198f, 0x332c, 0x19b8, 0x334a,
+  0x19e0, 0x3368, 0x1a08, 0x3386, 0x1a31, 0x33a3, 0x1a5a, 0x33c1,
+  0x1a82, 0x33df, 0x1aab, 0x33fc, 0x1ad4, 0x3419, 0x1afd, 0x3436,
+  0x1b26, 0x3453, 0x1b4f, 0x3470, 0x1b78, 0x348d, 0x1ba2, 0x34aa,
+  0x1bcb, 0x34c6, 0x1bf5, 0x34e2, 0x1c1e, 0x34ff, 0x1c48, 0x351b,
+  0x1c72, 0x3537, 0x1c9b, 0x3553, 0x1cc5, 0x356e, 0x1cef, 0x358a,
+  0x1d19, 0x35a5, 0x1d44, 0x35c1, 0x1d6e, 0x35dc, 0x1d98, 0x35f7,
+  0x1dc3, 0x3612, 0x1ded, 0x362d, 0x1e18, 0x3648, 0x1e42, 0x3662,
+  0x1e6d, 0x367d, 0x1e98, 0x3697, 0x1ec3, 0x36b1, 0x1eee, 0x36cb,
+  0x1f19, 0x36e5, 0x1f44, 0x36ff, 0x1f6f, 0x3718, 0x1f9b, 0x3732,
+  0x1fc6, 0x374b, 0x1ff1, 0x3765, 0x201d, 0x377e, 0x2049, 0x3797,
+  0x2074, 0x37b0, 0x20a0, 0x37c8, 0x20cc, 0x37e1, 0x20f8, 0x37f9,
+  0x2124, 0x3812, 0x2150, 0x382a, 0x217c, 0x3842, 0x21a8, 0x385a,
+  0x21d5, 0x3871, 0x2201, 0x3889, 0x222d, 0x38a1, 0x225a, 0x38b8,
+  0x2287, 0x38cf, 0x22b3, 0x38e6, 0x22e0, 0x38fd, 0x230d, 0x3914,
+  0x233a, 0x392b, 0x2367, 0x3941, 0x2394, 0x3958, 0x23c1, 0x396e,
+  0x23ee, 0x3984, 0x241b, 0x399a, 0x2448, 0x39b0, 0x2476, 0x39c5,
+  0x24a3, 0x39db, 0x24d0, 0x39f0, 0x24fe, 0x3a06, 0x252c, 0x3a1b,
+  0x2559, 0x3a30, 0x2587, 0x3a45, 0x25b5, 0x3a59, 0x25e3, 0x3a6e,
+  0x2611, 0x3a82, 0x263f, 0x3a97, 0x266d, 0x3aab, 0x269b, 0x3abf,
+  0x26c9, 0x3ad3, 0x26f7, 0x3ae6, 0x2725, 0x3afa, 0x2754, 0x3b0e,
+  0x2782, 0x3b21, 0x27b1, 0x3b34, 0x27df, 0x3b47, 0x280e, 0x3b5a,
+  0x283c, 0x3b6d, 0x286b, 0x3b7f, 0x289a, 0x3b92, 0x28c9, 0x3ba4,
+  0x28f7, 0x3bb6, 0x2926, 0x3bc8, 0x2955, 0x3bda, 0x2984, 0x3bec,
+  0x29b4, 0x3bfd, 0x29e3, 0x3c0f, 0x2a12, 0x3c20, 0x2a41, 0x3c31,
+  0x2a70, 0x3c42, 0x2aa0, 0x3c53, 0x2acf, 0x3c64, 0x2aff, 0x3c74,
+  0x2b2e, 0x3c85, 0x2b5e, 0x3c95, 0x2b8d, 0x3ca5, 0x2bbd, 0x3cb5,
+  0x2bed, 0x3cc5, 0x2c1c, 0x3cd5, 0x2c4c, 0x3ce4, 0x2c7c, 0x3cf4,
+  0x2cac, 0x3d03, 0x2cdc, 0x3d12, 0x2d0c, 0x3d21, 0x2d3c, 0x3d30,
+  0x2d6c, 0x3d3f, 0x2d9c, 0x3d4d, 0x2dcc, 0x3d5b, 0x2dfc, 0x3d6a,
+  0x2e2d, 0x3d78, 0x2e5d, 0x3d86, 0x2e8d, 0x3d93, 0x2ebe, 0x3da1,
+  0x2eee, 0x3daf, 0x2f1f, 0x3dbc, 0x2f4f, 0x3dc9, 0x2f80, 0x3dd6,
+  0x2fb0, 0x3de3, 0x2fe1, 0x3df0, 0x3012, 0x3dfc, 0x3042, 0x3e09,
+  0x3073, 0x3e15, 0x30a4, 0x3e21, 0x30d5, 0x3e2d, 0x3105, 0x3e39,
+  0x3136, 0x3e45, 0x3167, 0x3e50, 0x3198, 0x3e5c, 0x31c9, 0x3e67,
+  0x31fa, 0x3e72, 0x322b, 0x3e7d, 0x325c, 0x3e88, 0x328e, 0x3e92,
+  0x32bf, 0x3e9d, 0x32f0, 0x3ea7, 0x3321, 0x3eb1, 0x3352, 0x3ebb,
+  0x3384, 0x3ec5, 0x33b5, 0x3ecf, 0x33e6, 0x3ed8, 0x3418, 0x3ee2,
+  0x3449, 0x3eeb, 0x347b, 0x3ef4, 0x34ac, 0x3efd, 0x34dd, 0x3f06,
+  0x350f, 0x3f0f, 0x3540, 0x3f17, 0x3572, 0x3f20, 0x35a4, 0x3f28,
+  0x35d5, 0x3f30, 0x3607, 0x3f38, 0x3639, 0x3f40, 0x366a, 0x3f47,
+  0x369c, 0x3f4f, 0x36ce, 0x3f56, 0x36ff, 0x3f5d, 0x3731, 0x3f64,
+  0x3763, 0x3f6b, 0x3795, 0x3f72, 0x37c7, 0x3f78, 0x37f9, 0x3f7f,
+  0x382a, 0x3f85, 0x385c, 0x3f8b, 0x388e, 0x3f91, 0x38c0, 0x3f97,
+  0x38f2, 0x3f9c, 0x3924, 0x3fa2, 0x3956, 0x3fa7, 0x3988, 0x3fac,
+  0x39ba, 0x3fb1, 0x39ec, 0x3fb6, 0x3a1e, 0x3fbb, 0x3a50, 0x3fbf,
+  0x3a82, 0x3fc4, 0x3ab4, 0x3fc8, 0x3ae6, 0x3fcc, 0x3b19, 0x3fd0,
+  0x3b4b, 0x3fd4, 0x3b7d, 0x3fd7, 0x3baf, 0x3fdb, 0x3be1, 0x3fde,
+  0x3c13, 0x3fe1, 0x3c45, 0x3fe4, 0x3c78, 0x3fe7, 0x3caa, 0x3fea,
+  0x3cdc, 0x3fec, 0x3d0e, 0x3fef, 0x3d40, 0x3ff1, 0x3d73, 0x3ff3,
+  0x3da5, 0x3ff5, 0x3dd7, 0x3ff7, 0x3e09, 0x3ff8, 0x3e3c, 0x3ffa,
+  0x3e6e, 0x3ffb, 0x3ea0, 0x3ffc, 0x3ed2, 0x3ffd, 0x3f05, 0x3ffe,
+  0x3f37, 0x3fff, 0x3f69, 0x3fff, 0x3f9b, 0x4000, 0x3fce, 0x4000
+};
+
+/**   
+* \par  
+* Generation of real_CoefB array:   
+* \par   
+* n = 1024   
+* 
for (i = 0; i < n; i++)   
+*  {   
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+*  } 
  
+* \par   
+* Convert to fixed point Q15 format   
+*       round(pBTable[i] * pow(2, 15))   
+*   
+*/
+
+static const q15_t realCoefBQ15[2048] = {
+  0x4000, 0x4000, 0x4032, 0x4000, 0x4065, 0x4000, 0x4097, 0x3fff,
+  0x40c9, 0x3fff, 0x40fb, 0x3ffe, 0x412e, 0x3ffd, 0x4160, 0x3ffc,
+  0x4192, 0x3ffb, 0x41c4, 0x3ffa, 0x41f7, 0x3ff8, 0x4229, 0x3ff7,
+  0x425b, 0x3ff5, 0x428d, 0x3ff3, 0x42c0, 0x3ff1, 0x42f2, 0x3fef,
+  0x4324, 0x3fec, 0x4356, 0x3fea, 0x4388, 0x3fe7, 0x43bb, 0x3fe4,
+  0x43ed, 0x3fe1, 0x441f, 0x3fde, 0x4451, 0x3fdb, 0x4483, 0x3fd7,
+  0x44b5, 0x3fd4, 0x44e7, 0x3fd0, 0x451a, 0x3fcc, 0x454c, 0x3fc8,
+  0x457e, 0x3fc4, 0x45b0, 0x3fbf, 0x45e2, 0x3fbb, 0x4614, 0x3fb6,
+  0x4646, 0x3fb1, 0x4678, 0x3fac, 0x46aa, 0x3fa7, 0x46dc, 0x3fa2,
+  0x470e, 0x3f9c, 0x4740, 0x3f97, 0x4772, 0x3f91, 0x47a4, 0x3f8b,
+  0x47d6, 0x3f85, 0x4807, 0x3f7f, 0x4839, 0x3f78, 0x486b, 0x3f72,
+  0x489d, 0x3f6b, 0x48cf, 0x3f64, 0x4901, 0x3f5d, 0x4932, 0x3f56,
+  0x4964, 0x3f4f, 0x4996, 0x3f47, 0x49c7, 0x3f40, 0x49f9, 0x3f38,
+  0x4a2b, 0x3f30, 0x4a5c, 0x3f28, 0x4a8e, 0x3f20, 0x4ac0, 0x3f17,
+  0x4af1, 0x3f0f, 0x4b23, 0x3f06, 0x4b54, 0x3efd, 0x4b85, 0x3ef4,
+  0x4bb7, 0x3eeb, 0x4be8, 0x3ee2, 0x4c1a, 0x3ed8, 0x4c4b, 0x3ecf,
+  0x4c7c, 0x3ec5, 0x4cae, 0x3ebb, 0x4cdf, 0x3eb1, 0x4d10, 0x3ea7,
+  0x4d41, 0x3e9d, 0x4d72, 0x3e92, 0x4da4, 0x3e88, 0x4dd5, 0x3e7d,
+  0x4e06, 0x3e72, 0x4e37, 0x3e67, 0x4e68, 0x3e5c, 0x4e99, 0x3e50,
+  0x4eca, 0x3e45, 0x4efb, 0x3e39, 0x4f2b, 0x3e2d, 0x4f5c, 0x3e21,
+  0x4f8d, 0x3e15, 0x4fbe, 0x3e09, 0x4fee, 0x3dfc, 0x501f, 0x3df0,
+  0x5050, 0x3de3, 0x5080, 0x3dd6, 0x50b1, 0x3dc9, 0x50e1, 0x3dbc,
+  0x5112, 0x3daf, 0x5142, 0x3da1, 0x5173, 0x3d93, 0x51a3, 0x3d86,
+  0x51d3, 0x3d78, 0x5204, 0x3d6a, 0x5234, 0x3d5b, 0x5264, 0x3d4d,
+  0x5294, 0x3d3f, 0x52c4, 0x3d30, 0x52f4, 0x3d21, 0x5324, 0x3d12,
+  0x5354, 0x3d03, 0x5384, 0x3cf4, 0x53b4, 0x3ce4, 0x53e4, 0x3cd5,
+  0x5413, 0x3cc5, 0x5443, 0x3cb5, 0x5473, 0x3ca5, 0x54a2, 0x3c95,
+  0x54d2, 0x3c85, 0x5501, 0x3c74, 0x5531, 0x3c64, 0x5560, 0x3c53,
+  0x5590, 0x3c42, 0x55bf, 0x3c31, 0x55ee, 0x3c20, 0x561d, 0x3c0f,
+  0x564c, 0x3bfd, 0x567c, 0x3bec, 0x56ab, 0x3bda, 0x56da, 0x3bc8,
+  0x5709, 0x3bb6, 0x5737, 0x3ba4, 0x5766, 0x3b92, 0x5795, 0x3b7f,
+  0x57c4, 0x3b6d, 0x57f2, 0x3b5a, 0x5821, 0x3b47, 0x584f, 0x3b34,
+  0x587e, 0x3b21, 0x58ac, 0x3b0e, 0x58db, 0x3afa, 0x5909, 0x3ae6,
+  0x5937, 0x3ad3, 0x5965, 0x3abf, 0x5993, 0x3aab, 0x59c1, 0x3a97,
+  0x59ef, 0x3a82, 0x5a1d, 0x3a6e, 0x5a4b, 0x3a59, 0x5a79, 0x3a45,
+  0x5aa7, 0x3a30, 0x5ad4, 0x3a1b, 0x5b02, 0x3a06, 0x5b30, 0x39f0,
+  0x5b5d, 0x39db, 0x5b8a, 0x39c5, 0x5bb8, 0x39b0, 0x5be5, 0x399a,
+  0x5c12, 0x3984, 0x5c3f, 0x396e, 0x5c6c, 0x3958, 0x5c99, 0x3941,
+  0x5cc6, 0x392b, 0x5cf3, 0x3914, 0x5d20, 0x38fd, 0x5d4d, 0x38e6,
+  0x5d79, 0x38cf, 0x5da6, 0x38b8, 0x5dd3, 0x38a1, 0x5dff, 0x3889,
+  0x5e2b, 0x3871, 0x5e58, 0x385a, 0x5e84, 0x3842, 0x5eb0, 0x382a,
+  0x5edc, 0x3812, 0x5f08, 0x37f9, 0x5f34, 0x37e1, 0x5f60, 0x37c8,
+  0x5f8c, 0x37b0, 0x5fb7, 0x3797, 0x5fe3, 0x377e, 0x600f, 0x3765,
+  0x603a, 0x374b, 0x6065, 0x3732, 0x6091, 0x3718, 0x60bc, 0x36ff,
+  0x60e7, 0x36e5, 0x6112, 0x36cb, 0x613d, 0x36b1, 0x6168, 0x3697,
+  0x6193, 0x367d, 0x61be, 0x3662, 0x61e8, 0x3648, 0x6213, 0x362d,
+  0x623d, 0x3612, 0x6268, 0x35f7, 0x6292, 0x35dc, 0x62bc, 0x35c1,
+  0x62e7, 0x35a5, 0x6311, 0x358a, 0x633b, 0x356e, 0x6365, 0x3553,
+  0x638e, 0x3537, 0x63b8, 0x351b, 0x63e2, 0x34ff, 0x640b, 0x34e2,
+  0x6435, 0x34c6, 0x645e, 0x34aa, 0x6488, 0x348d, 0x64b1, 0x3470,
+  0x64da, 0x3453, 0x6503, 0x3436, 0x652c, 0x3419, 0x6555, 0x33fc,
+  0x657e, 0x33df, 0x65a6, 0x33c1, 0x65cf, 0x33a3, 0x65f8, 0x3386,
+  0x6620, 0x3368, 0x6648, 0x334a, 0x6671, 0x332c, 0x6699, 0x330d,
+  0x66c1, 0x32ef, 0x66e9, 0x32d0, 0x6711, 0x32b2, 0x6738, 0x3293,
+  0x6760, 0x3274, 0x6788, 0x3255, 0x67af, 0x3236, 0x67d6, 0x3217,
+  0x67fe, 0x31f8, 0x6825, 0x31d8, 0x684c, 0x31b9, 0x6873, 0x3199,
+  0x689a, 0x3179, 0x68c1, 0x3159, 0x68e7, 0x3139, 0x690e, 0x3119,
+  0x6935, 0x30f9, 0x695b, 0x30d8, 0x6981, 0x30b8, 0x69a7, 0x3097,
+  0x69ce, 0x3076, 0x69f4, 0x3055, 0x6a1a, 0x3034, 0x6a3f, 0x3013,
+  0x6a65, 0x2ff2, 0x6a8b, 0x2fd0, 0x6ab0, 0x2faf, 0x6ad6, 0x2f8d,
+  0x6afb, 0x2f6c, 0x6b20, 0x2f4a, 0x6b45, 0x2f28, 0x6b6a, 0x2f06,
+  0x6b8f, 0x2ee4, 0x6bb4, 0x2ec2, 0x6bd8, 0x2e9f, 0x6bfd, 0x2e7d,
+  0x6c21, 0x2e5a, 0x6c46, 0x2e37, 0x6c6a, 0x2e15, 0x6c8e, 0x2df2,
+  0x6cb2, 0x2dcf, 0x6cd6, 0x2dab, 0x6cfa, 0x2d88, 0x6d1e, 0x2d65,
+  0x6d41, 0x2d41, 0x6d65, 0x2d1e, 0x6d88, 0x2cfa, 0x6dab, 0x2cd6,
+  0x6dcf, 0x2cb2, 0x6df2, 0x2c8e, 0x6e15, 0x2c6a, 0x6e37, 0x2c46,
+  0x6e5a, 0x2c21, 0x6e7d, 0x2bfd, 0x6e9f, 0x2bd8, 0x6ec2, 0x2bb4,
+  0x6ee4, 0x2b8f, 0x6f06, 0x2b6a, 0x6f28, 0x2b45, 0x6f4a, 0x2b20,
+  0x6f6c, 0x2afb, 0x6f8d, 0x2ad6, 0x6faf, 0x2ab0, 0x6fd0, 0x2a8b,
+  0x6ff2, 0x2a65, 0x7013, 0x2a3f, 0x7034, 0x2a1a, 0x7055, 0x29f4,
+  0x7076, 0x29ce, 0x7097, 0x29a7, 0x70b8, 0x2981, 0x70d8, 0x295b,
+  0x70f9, 0x2935, 0x7119, 0x290e, 0x7139, 0x28e7, 0x7159, 0x28c1,
+  0x7179, 0x289a, 0x7199, 0x2873, 0x71b9, 0x284c, 0x71d8, 0x2825,
+  0x71f8, 0x27fe, 0x7217, 0x27d6, 0x7236, 0x27af, 0x7255, 0x2788,
+  0x7274, 0x2760, 0x7293, 0x2738, 0x72b2, 0x2711, 0x72d0, 0x26e9,
+  0x72ef, 0x26c1, 0x730d, 0x2699, 0x732c, 0x2671, 0x734a, 0x2648,
+  0x7368, 0x2620, 0x7386, 0x25f8, 0x73a3, 0x25cf, 0x73c1, 0x25a6,
+  0x73df, 0x257e, 0x73fc, 0x2555, 0x7419, 0x252c, 0x7436, 0x2503,
+  0x7453, 0x24da, 0x7470, 0x24b1, 0x748d, 0x2488, 0x74aa, 0x245e,
+  0x74c6, 0x2435, 0x74e2, 0x240b, 0x74ff, 0x23e2, 0x751b, 0x23b8,
+  0x7537, 0x238e, 0x7553, 0x2365, 0x756e, 0x233b, 0x758a, 0x2311,
+  0x75a5, 0x22e7, 0x75c1, 0x22bc, 0x75dc, 0x2292, 0x75f7, 0x2268,
+  0x7612, 0x223d, 0x762d, 0x2213, 0x7648, 0x21e8, 0x7662, 0x21be,
+  0x767d, 0x2193, 0x7697, 0x2168, 0x76b1, 0x213d, 0x76cb, 0x2112,
+  0x76e5, 0x20e7, 0x76ff, 0x20bc, 0x7718, 0x2091, 0x7732, 0x2065,
+  0x774b, 0x203a, 0x7765, 0x200f, 0x777e, 0x1fe3, 0x7797, 0x1fb7,
+  0x77b0, 0x1f8c, 0x77c8, 0x1f60, 0x77e1, 0x1f34, 0x77f9, 0x1f08,
+  0x7812, 0x1edc, 0x782a, 0x1eb0, 0x7842, 0x1e84, 0x785a, 0x1e58,
+  0x7871, 0x1e2b, 0x7889, 0x1dff, 0x78a1, 0x1dd3, 0x78b8, 0x1da6,
+  0x78cf, 0x1d79, 0x78e6, 0x1d4d, 0x78fd, 0x1d20, 0x7914, 0x1cf3,
+  0x792b, 0x1cc6, 0x7941, 0x1c99, 0x7958, 0x1c6c, 0x796e, 0x1c3f,
+  0x7984, 0x1c12, 0x799a, 0x1be5, 0x79b0, 0x1bb8, 0x79c5, 0x1b8a,
+  0x79db, 0x1b5d, 0x79f0, 0x1b30, 0x7a06, 0x1b02, 0x7a1b, 0x1ad4,
+  0x7a30, 0x1aa7, 0x7a45, 0x1a79, 0x7a59, 0x1a4b, 0x7a6e, 0x1a1d,
+  0x7a82, 0x19ef, 0x7a97, 0x19c1, 0x7aab, 0x1993, 0x7abf, 0x1965,
+  0x7ad3, 0x1937, 0x7ae6, 0x1909, 0x7afa, 0x18db, 0x7b0e, 0x18ac,
+  0x7b21, 0x187e, 0x7b34, 0x184f, 0x7b47, 0x1821, 0x7b5a, 0x17f2,
+  0x7b6d, 0x17c4, 0x7b7f, 0x1795, 0x7b92, 0x1766, 0x7ba4, 0x1737,
+  0x7bb6, 0x1709, 0x7bc8, 0x16da, 0x7bda, 0x16ab, 0x7bec, 0x167c,
+  0x7bfd, 0x164c, 0x7c0f, 0x161d, 0x7c20, 0x15ee, 0x7c31, 0x15bf,
+  0x7c42, 0x1590, 0x7c53, 0x1560, 0x7c64, 0x1531, 0x7c74, 0x1501,
+  0x7c85, 0x14d2, 0x7c95, 0x14a2, 0x7ca5, 0x1473, 0x7cb5, 0x1443,
+  0x7cc5, 0x1413, 0x7cd5, 0x13e4, 0x7ce4, 0x13b4, 0x7cf4, 0x1384,
+  0x7d03, 0x1354, 0x7d12, 0x1324, 0x7d21, 0x12f4, 0x7d30, 0x12c4,
+  0x7d3f, 0x1294, 0x7d4d, 0x1264, 0x7d5b, 0x1234, 0x7d6a, 0x1204,
+  0x7d78, 0x11d3, 0x7d86, 0x11a3, 0x7d93, 0x1173, 0x7da1, 0x1142,
+  0x7daf, 0x1112, 0x7dbc, 0x10e1, 0x7dc9, 0x10b1, 0x7dd6, 0x1080,
+  0x7de3, 0x1050, 0x7df0, 0x101f, 0x7dfc, 0xfee, 0x7e09, 0xfbe,
+  0x7e15, 0xf8d, 0x7e21, 0xf5c, 0x7e2d, 0xf2b, 0x7e39, 0xefb,
+  0x7e45, 0xeca, 0x7e50, 0xe99, 0x7e5c, 0xe68, 0x7e67, 0xe37,
+  0x7e72, 0xe06, 0x7e7d, 0xdd5, 0x7e88, 0xda4, 0x7e92, 0xd72,
+  0x7e9d, 0xd41, 0x7ea7, 0xd10, 0x7eb1, 0xcdf, 0x7ebb, 0xcae,
+  0x7ec5, 0xc7c, 0x7ecf, 0xc4b, 0x7ed8, 0xc1a, 0x7ee2, 0xbe8,
+  0x7eeb, 0xbb7, 0x7ef4, 0xb85, 0x7efd, 0xb54, 0x7f06, 0xb23,
+  0x7f0f, 0xaf1, 0x7f17, 0xac0, 0x7f20, 0xa8e, 0x7f28, 0xa5c,
+  0x7f30, 0xa2b, 0x7f38, 0x9f9, 0x7f40, 0x9c7, 0x7f47, 0x996,
+  0x7f4f, 0x964, 0x7f56, 0x932, 0x7f5d, 0x901, 0x7f64, 0x8cf,
+  0x7f6b, 0x89d, 0x7f72, 0x86b, 0x7f78, 0x839, 0x7f7f, 0x807,
+  0x7f85, 0x7d6, 0x7f8b, 0x7a4, 0x7f91, 0x772, 0x7f97, 0x740,
+  0x7f9c, 0x70e, 0x7fa2, 0x6dc, 0x7fa7, 0x6aa, 0x7fac, 0x678,
+  0x7fb1, 0x646, 0x7fb6, 0x614, 0x7fbb, 0x5e2, 0x7fbf, 0x5b0,
+  0x7fc4, 0x57e, 0x7fc8, 0x54c, 0x7fcc, 0x51a, 0x7fd0, 0x4e7,
+  0x7fd4, 0x4b5, 0x7fd7, 0x483, 0x7fdb, 0x451, 0x7fde, 0x41f,
+  0x7fe1, 0x3ed, 0x7fe4, 0x3bb, 0x7fe7, 0x388, 0x7fea, 0x356,
+  0x7fec, 0x324, 0x7fef, 0x2f2, 0x7ff1, 0x2c0, 0x7ff3, 0x28d,
+  0x7ff5, 0x25b, 0x7ff7, 0x229, 0x7ff8, 0x1f7, 0x7ffa, 0x1c4,
+  0x7ffb, 0x192, 0x7ffc, 0x160, 0x7ffd, 0x12e, 0x7ffe, 0xfb,
+  0x7fff, 0xc9, 0x7fff, 0x97, 0x7fff, 0x65, 0x7fff, 0x32,
+  0x7fff, 0x0, 0x7fff, 0xffce, 0x7fff, 0xff9b, 0x7fff, 0xff69,
+  0x7fff, 0xff37, 0x7ffe, 0xff05, 0x7ffd, 0xfed2, 0x7ffc, 0xfea0,
+  0x7ffb, 0xfe6e, 0x7ffa, 0xfe3c, 0x7ff8, 0xfe09, 0x7ff7, 0xfdd7,
+  0x7ff5, 0xfda5, 0x7ff3, 0xfd73, 0x7ff1, 0xfd40, 0x7fef, 0xfd0e,
+  0x7fec, 0xfcdc, 0x7fea, 0xfcaa, 0x7fe7, 0xfc78, 0x7fe4, 0xfc45,
+  0x7fe1, 0xfc13, 0x7fde, 0xfbe1, 0x7fdb, 0xfbaf, 0x7fd7, 0xfb7d,
+  0x7fd4, 0xfb4b, 0x7fd0, 0xfb19, 0x7fcc, 0xfae6, 0x7fc8, 0xfab4,
+  0x7fc4, 0xfa82, 0x7fbf, 0xfa50, 0x7fbb, 0xfa1e, 0x7fb6, 0xf9ec,
+  0x7fb1, 0xf9ba, 0x7fac, 0xf988, 0x7fa7, 0xf956, 0x7fa2, 0xf924,
+  0x7f9c, 0xf8f2, 0x7f97, 0xf8c0, 0x7f91, 0xf88e, 0x7f8b, 0xf85c,
+  0x7f85, 0xf82a, 0x7f7f, 0xf7f9, 0x7f78, 0xf7c7, 0x7f72, 0xf795,
+  0x7f6b, 0xf763, 0x7f64, 0xf731, 0x7f5d, 0xf6ff, 0x7f56, 0xf6ce,
+  0x7f4f, 0xf69c, 0x7f47, 0xf66a, 0x7f40, 0xf639, 0x7f38, 0xf607,
+  0x7f30, 0xf5d5, 0x7f28, 0xf5a4, 0x7f20, 0xf572, 0x7f17, 0xf540,
+  0x7f0f, 0xf50f, 0x7f06, 0xf4dd, 0x7efd, 0xf4ac, 0x7ef4, 0xf47b,
+  0x7eeb, 0xf449, 0x7ee2, 0xf418, 0x7ed8, 0xf3e6, 0x7ecf, 0xf3b5,
+  0x7ec5, 0xf384, 0x7ebb, 0xf352, 0x7eb1, 0xf321, 0x7ea7, 0xf2f0,
+  0x7e9d, 0xf2bf, 0x7e92, 0xf28e, 0x7e88, 0xf25c, 0x7e7d, 0xf22b,
+  0x7e72, 0xf1fa, 0x7e67, 0xf1c9, 0x7e5c, 0xf198, 0x7e50, 0xf167,
+  0x7e45, 0xf136, 0x7e39, 0xf105, 0x7e2d, 0xf0d5, 0x7e21, 0xf0a4,
+  0x7e15, 0xf073, 0x7e09, 0xf042, 0x7dfc, 0xf012, 0x7df0, 0xefe1,
+  0x7de3, 0xefb0, 0x7dd6, 0xef80, 0x7dc9, 0xef4f, 0x7dbc, 0xef1f,
+  0x7daf, 0xeeee, 0x7da1, 0xeebe, 0x7d93, 0xee8d, 0x7d86, 0xee5d,
+  0x7d78, 0xee2d, 0x7d6a, 0xedfc, 0x7d5b, 0xedcc, 0x7d4d, 0xed9c,
+  0x7d3f, 0xed6c, 0x7d30, 0xed3c, 0x7d21, 0xed0c, 0x7d12, 0xecdc,
+  0x7d03, 0xecac, 0x7cf4, 0xec7c, 0x7ce4, 0xec4c, 0x7cd5, 0xec1c,
+  0x7cc5, 0xebed, 0x7cb5, 0xebbd, 0x7ca5, 0xeb8d, 0x7c95, 0xeb5e,
+  0x7c85, 0xeb2e, 0x7c74, 0xeaff, 0x7c64, 0xeacf, 0x7c53, 0xeaa0,
+  0x7c42, 0xea70, 0x7c31, 0xea41, 0x7c20, 0xea12, 0x7c0f, 0xe9e3,
+  0x7bfd, 0xe9b4, 0x7bec, 0xe984, 0x7bda, 0xe955, 0x7bc8, 0xe926,
+  0x7bb6, 0xe8f7, 0x7ba4, 0xe8c9, 0x7b92, 0xe89a, 0x7b7f, 0xe86b,
+  0x7b6d, 0xe83c, 0x7b5a, 0xe80e, 0x7b47, 0xe7df, 0x7b34, 0xe7b1,
+  0x7b21, 0xe782, 0x7b0e, 0xe754, 0x7afa, 0xe725, 0x7ae6, 0xe6f7,
+  0x7ad3, 0xe6c9, 0x7abf, 0xe69b, 0x7aab, 0xe66d, 0x7a97, 0xe63f,
+  0x7a82, 0xe611, 0x7a6e, 0xe5e3, 0x7a59, 0xe5b5, 0x7a45, 0xe587,
+  0x7a30, 0xe559, 0x7a1b, 0xe52c, 0x7a06, 0xe4fe, 0x79f0, 0xe4d0,
+  0x79db, 0xe4a3, 0x79c5, 0xe476, 0x79b0, 0xe448, 0x799a, 0xe41b,
+  0x7984, 0xe3ee, 0x796e, 0xe3c1, 0x7958, 0xe394, 0x7941, 0xe367,
+  0x792b, 0xe33a, 0x7914, 0xe30d, 0x78fd, 0xe2e0, 0x78e6, 0xe2b3,
+  0x78cf, 0xe287, 0x78b8, 0xe25a, 0x78a1, 0xe22d, 0x7889, 0xe201,
+  0x7871, 0xe1d5, 0x785a, 0xe1a8, 0x7842, 0xe17c, 0x782a, 0xe150,
+  0x7812, 0xe124, 0x77f9, 0xe0f8, 0x77e1, 0xe0cc, 0x77c8, 0xe0a0,
+  0x77b0, 0xe074, 0x7797, 0xe049, 0x777e, 0xe01d, 0x7765, 0xdff1,
+  0x774b, 0xdfc6, 0x7732, 0xdf9b, 0x7718, 0xdf6f, 0x76ff, 0xdf44,
+  0x76e5, 0xdf19, 0x76cb, 0xdeee, 0x76b1, 0xdec3, 0x7697, 0xde98,
+  0x767d, 0xde6d, 0x7662, 0xde42, 0x7648, 0xde18, 0x762d, 0xdded,
+  0x7612, 0xddc3, 0x75f7, 0xdd98, 0x75dc, 0xdd6e, 0x75c1, 0xdd44,
+  0x75a5, 0xdd19, 0x758a, 0xdcef, 0x756e, 0xdcc5, 0x7553, 0xdc9b,
+  0x7537, 0xdc72, 0x751b, 0xdc48, 0x74ff, 0xdc1e, 0x74e2, 0xdbf5,
+  0x74c6, 0xdbcb, 0x74aa, 0xdba2, 0x748d, 0xdb78, 0x7470, 0xdb4f,
+  0x7453, 0xdb26, 0x7436, 0xdafd, 0x7419, 0xdad4, 0x73fc, 0xdaab,
+  0x73df, 0xda82, 0x73c1, 0xda5a, 0x73a3, 0xda31, 0x7386, 0xda08,
+  0x7368, 0xd9e0, 0x734a, 0xd9b8, 0x732c, 0xd98f, 0x730d, 0xd967,
+  0x72ef, 0xd93f, 0x72d0, 0xd917, 0x72b2, 0xd8ef, 0x7293, 0xd8c8,
+  0x7274, 0xd8a0, 0x7255, 0xd878, 0x7236, 0xd851, 0x7217, 0xd82a,
+  0x71f8, 0xd802, 0x71d8, 0xd7db, 0x71b9, 0xd7b4, 0x7199, 0xd78d,
+  0x7179, 0xd766, 0x7159, 0xd73f, 0x7139, 0xd719, 0x7119, 0xd6f2,
+  0x70f9, 0xd6cb, 0x70d8, 0xd6a5, 0x70b8, 0xd67f, 0x7097, 0xd659,
+  0x7076, 0xd632, 0x7055, 0xd60c, 0x7034, 0xd5e6, 0x7013, 0xd5c1,
+  0x6ff2, 0xd59b, 0x6fd0, 0xd575, 0x6faf, 0xd550, 0x6f8d, 0xd52a,
+  0x6f6c, 0xd505, 0x6f4a, 0xd4e0, 0x6f28, 0xd4bb, 0x6f06, 0xd496,
+  0x6ee4, 0xd471, 0x6ec2, 0xd44c, 0x6e9f, 0xd428, 0x6e7d, 0xd403,
+  0x6e5a, 0xd3df, 0x6e37, 0xd3ba, 0x6e15, 0xd396, 0x6df2, 0xd372,
+  0x6dcf, 0xd34e, 0x6dab, 0xd32a, 0x6d88, 0xd306, 0x6d65, 0xd2e2,
+  0x6d41, 0xd2bf, 0x6d1e, 0xd29b, 0x6cfa, 0xd278, 0x6cd6, 0xd255,
+  0x6cb2, 0xd231, 0x6c8e, 0xd20e, 0x6c6a, 0xd1eb, 0x6c46, 0xd1c9,
+  0x6c21, 0xd1a6, 0x6bfd, 0xd183, 0x6bd8, 0xd161, 0x6bb4, 0xd13e,
+  0x6b8f, 0xd11c, 0x6b6a, 0xd0fa, 0x6b45, 0xd0d8, 0x6b20, 0xd0b6,
+  0x6afb, 0xd094, 0x6ad6, 0xd073, 0x6ab0, 0xd051, 0x6a8b, 0xd030,
+  0x6a65, 0xd00e, 0x6a3f, 0xcfed, 0x6a1a, 0xcfcc, 0x69f4, 0xcfab,
+  0x69ce, 0xcf8a, 0x69a7, 0xcf69, 0x6981, 0xcf48, 0x695b, 0xcf28,
+  0x6935, 0xcf07, 0x690e, 0xcee7, 0x68e7, 0xcec7, 0x68c1, 0xcea7,
+  0x689a, 0xce87, 0x6873, 0xce67, 0x684c, 0xce47, 0x6825, 0xce28,
+  0x67fe, 0xce08, 0x67d6, 0xcde9, 0x67af, 0xcdca, 0x6788, 0xcdab,
+  0x6760, 0xcd8c, 0x6738, 0xcd6d, 0x6711, 0xcd4e, 0x66e9, 0xcd30,
+  0x66c1, 0xcd11, 0x6699, 0xccf3, 0x6671, 0xccd4, 0x6648, 0xccb6,
+  0x6620, 0xcc98, 0x65f8, 0xcc7a, 0x65cf, 0xcc5d, 0x65a6, 0xcc3f,
+  0x657e, 0xcc21, 0x6555, 0xcc04, 0x652c, 0xcbe7, 0x6503, 0xcbca,
+  0x64da, 0xcbad, 0x64b1, 0xcb90, 0x6488, 0xcb73, 0x645e, 0xcb56,
+  0x6435, 0xcb3a, 0x640b, 0xcb1e, 0x63e2, 0xcb01, 0x63b8, 0xcae5,
+  0x638e, 0xcac9, 0x6365, 0xcaad, 0x633b, 0xca92, 0x6311, 0xca76,
+  0x62e7, 0xca5b, 0x62bc, 0xca3f, 0x6292, 0xca24, 0x6268, 0xca09,
+  0x623d, 0xc9ee, 0x6213, 0xc9d3, 0x61e8, 0xc9b8, 0x61be, 0xc99e,
+  0x6193, 0xc983, 0x6168, 0xc969, 0x613d, 0xc94f, 0x6112, 0xc935,
+  0x60e7, 0xc91b, 0x60bc, 0xc901, 0x6091, 0xc8e8, 0x6065, 0xc8ce,
+  0x603a, 0xc8b5, 0x600f, 0xc89b, 0x5fe3, 0xc882, 0x5fb7, 0xc869,
+  0x5f8c, 0xc850, 0x5f60, 0xc838, 0x5f34, 0xc81f, 0x5f08, 0xc807,
+  0x5edc, 0xc7ee, 0x5eb0, 0xc7d6, 0x5e84, 0xc7be, 0x5e58, 0xc7a6,
+  0x5e2b, 0xc78f, 0x5dff, 0xc777, 0x5dd3, 0xc75f, 0x5da6, 0xc748,
+  0x5d79, 0xc731, 0x5d4d, 0xc71a, 0x5d20, 0xc703, 0x5cf3, 0xc6ec,
+  0x5cc6, 0xc6d5, 0x5c99, 0xc6bf, 0x5c6c, 0xc6a8, 0x5c3f, 0xc692,
+  0x5c12, 0xc67c, 0x5be5, 0xc666, 0x5bb8, 0xc650, 0x5b8a, 0xc63b,
+  0x5b5d, 0xc625, 0x5b30, 0xc610, 0x5b02, 0xc5fa, 0x5ad4, 0xc5e5,
+  0x5aa7, 0xc5d0, 0x5a79, 0xc5bb, 0x5a4b, 0xc5a7, 0x5a1d, 0xc592,
+  0x59ef, 0xc57e, 0x59c1, 0xc569, 0x5993, 0xc555, 0x5965, 0xc541,
+  0x5937, 0xc52d, 0x5909, 0xc51a, 0x58db, 0xc506, 0x58ac, 0xc4f2,
+  0x587e, 0xc4df, 0x584f, 0xc4cc, 0x5821, 0xc4b9, 0x57f2, 0xc4a6,
+  0x57c4, 0xc493, 0x5795, 0xc481, 0x5766, 0xc46e, 0x5737, 0xc45c,
+  0x5709, 0xc44a, 0x56da, 0xc438, 0x56ab, 0xc426, 0x567c, 0xc414,
+  0x564c, 0xc403, 0x561d, 0xc3f1, 0x55ee, 0xc3e0, 0x55bf, 0xc3cf,
+  0x5590, 0xc3be, 0x5560, 0xc3ad, 0x5531, 0xc39c, 0x5501, 0xc38c,
+  0x54d2, 0xc37b, 0x54a2, 0xc36b, 0x5473, 0xc35b, 0x5443, 0xc34b,
+  0x5413, 0xc33b, 0x53e4, 0xc32b, 0x53b4, 0xc31c, 0x5384, 0xc30c,
+  0x5354, 0xc2fd, 0x5324, 0xc2ee, 0x52f4, 0xc2df, 0x52c4, 0xc2d0,
+  0x5294, 0xc2c1, 0x5264, 0xc2b3, 0x5234, 0xc2a5, 0x5204, 0xc296,
+  0x51d3, 0xc288, 0x51a3, 0xc27a, 0x5173, 0xc26d, 0x5142, 0xc25f,
+  0x5112, 0xc251, 0x50e1, 0xc244, 0x50b1, 0xc237, 0x5080, 0xc22a,
+  0x5050, 0xc21d, 0x501f, 0xc210, 0x4fee, 0xc204, 0x4fbe, 0xc1f7,
+  0x4f8d, 0xc1eb, 0x4f5c, 0xc1df, 0x4f2b, 0xc1d3, 0x4efb, 0xc1c7,
+  0x4eca, 0xc1bb, 0x4e99, 0xc1b0, 0x4e68, 0xc1a4, 0x4e37, 0xc199,
+  0x4e06, 0xc18e, 0x4dd5, 0xc183, 0x4da4, 0xc178, 0x4d72, 0xc16e,
+  0x4d41, 0xc163, 0x4d10, 0xc159, 0x4cdf, 0xc14f, 0x4cae, 0xc145,
+  0x4c7c, 0xc13b, 0x4c4b, 0xc131, 0x4c1a, 0xc128, 0x4be8, 0xc11e,
+  0x4bb7, 0xc115, 0x4b85, 0xc10c, 0x4b54, 0xc103, 0x4b23, 0xc0fa,
+  0x4af1, 0xc0f1, 0x4ac0, 0xc0e9, 0x4a8e, 0xc0e0, 0x4a5c, 0xc0d8,
+  0x4a2b, 0xc0d0, 0x49f9, 0xc0c8, 0x49c7, 0xc0c0, 0x4996, 0xc0b9,
+  0x4964, 0xc0b1, 0x4932, 0xc0aa, 0x4901, 0xc0a3, 0x48cf, 0xc09c,
+  0x489d, 0xc095, 0x486b, 0xc08e, 0x4839, 0xc088, 0x4807, 0xc081,
+  0x47d6, 0xc07b, 0x47a4, 0xc075, 0x4772, 0xc06f, 0x4740, 0xc069,
+  0x470e, 0xc064, 0x46dc, 0xc05e, 0x46aa, 0xc059, 0x4678, 0xc054,
+  0x4646, 0xc04f, 0x4614, 0xc04a, 0x45e2, 0xc045, 0x45b0, 0xc041,
+  0x457e, 0xc03c, 0x454c, 0xc038, 0x451a, 0xc034, 0x44e7, 0xc030,
+  0x44b5, 0xc02c, 0x4483, 0xc029, 0x4451, 0xc025, 0x441f, 0xc022,
+  0x43ed, 0xc01f, 0x43bb, 0xc01c, 0x4388, 0xc019, 0x4356, 0xc016,
+  0x4324, 0xc014, 0x42f2, 0xc011, 0x42c0, 0xc00f, 0x428d, 0xc00d,
+  0x425b, 0xc00b, 0x4229, 0xc009, 0x41f7, 0xc008, 0x41c4, 0xc006,
+  0x4192, 0xc005, 0x4160, 0xc004, 0x412e, 0xc003, 0x40fb, 0xc002,
+  0x40c9, 0xc001, 0x4097, 0xc001, 0x4065, 0xc000, 0x4032, 0xc000
+};
+
+/**   
+* @brief  Initialization function for the Q15 RFFT/RIFFT.  
+* @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.  
+* @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.  
+* @param[in]      fftLenReal     length of the FFT.  
+* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.  
+* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.  
+*   
+* \par Description:  
+* \par  
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.   
+* \par   
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.   
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.  
+* \par   
+* This function also initializes Twiddle factor table.    
+*/
+
+arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (q15_t *) realCoefAQ15;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (q15_t *) realCoefBQ15;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initialization of coef modifier depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+  case 2048u:
+    S->twidCoefRModifier = 1u;
+    break;
+  case 512u:
+    S->twidCoefRModifier = 4u;
+    break;
+  case 128u:
+    S->twidCoefRModifier = 16u;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if(S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 1u, 1u);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 0u, 1u);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
new file mode 100644
index 0000000..cabb994
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
@@ -0,0 +1,681 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_init_q31.c   
+*   
+* Description:	RFFT & RIFFT Q31 initialisation function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+* \par   
+* Generation floating point realCoefAQ31 array:   
+* \par   
+* n = 1024   
+* 
for (i = 0; i < n; i++)   
+* {   
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+* }
   
+* \par   
+* Convert to fixed point Q31 format   
+*     round(pATable[i] * pow(2, 31))   
+*/
+
+
+const q31_t realCoefAQ31[1024] = {
+  0x40000000, 0xc0000000, 0x3f9b783c, 0xc0004ef5,
+  0x3f36f170, 0xc0013bd3, 0x3ed26c94, 0xc002c697,
+  0x3e6deaa1, 0xc004ef3f, 0x3e096c8d, 0xc007b5c4,
+  0x3da4f351, 0xc00b1a20, 0x3d407fe6, 0xc00f1c4a,
+  0x3cdc1342, 0xc013bc39, 0x3c77ae5e, 0xc018f9e1,
+  0x3c135231, 0xc01ed535, 0x3baeffb3, 0xc0254e27,
+  0x3b4ab7db, 0xc02c64a6, 0x3ae67ba2, 0xc03418a2,
+  0x3a824bfd, 0xc03c6a07, 0x3a1e29e5, 0xc04558c0,
+  0x39ba1651, 0xc04ee4b8, 0x39561237, 0xc0590dd8,
+  0x38f21e8e, 0xc063d405, 0x388e3c4d, 0xc06f3726,
+  0x382a6c6a, 0xc07b371e, 0x37c6afdc, 0xc087d3d0,
+  0x37630799, 0xc0950d1d, 0x36ff7496, 0xc0a2e2e3,
+  0x369bf7c9, 0xc0b15502, 0x36389228, 0xc0c06355,
+  0x35d544a7, 0xc0d00db6, 0x3572103d, 0xc0e05401,
+  0x350ef5de, 0xc0f1360b, 0x34abf67e, 0xc102b3ac,
+  0x34491311, 0xc114ccb9, 0x33e64c8c, 0xc1278104,
+  0x3383a3e2, 0xc13ad060, 0x33211a07, 0xc14eba9d,
+  0x32beafed, 0xc1633f8a, 0x325c6688, 0xc1785ef4,
+  0x31fa3ecb, 0xc18e18a7, 0x319839a6, 0xc1a46c6e,
+  0x3136580d, 0xc1bb5a11, 0x30d49af1, 0xc1d2e158,
+  0x30730342, 0xc1eb0209, 0x301191f3, 0xc203bbe8,
+  0x2fb047f2, 0xc21d0eb8, 0x2f4f2630, 0xc236fa3b,
+  0x2eee2d9d, 0xc2517e31, 0x2e8d5f29, 0xc26c9a58,
+  0x2e2cbbc1, 0xc2884e6e, 0x2dcc4454, 0xc2a49a2e,
+  0x2d6bf9d1, 0xc2c17d52, 0x2d0bdd25, 0xc2def794,
+  0x2cabef3d, 0xc2fd08a9, 0x2c4c3106, 0xc31bb049,
+  0x2beca36c, 0xc33aee27, 0x2b8d475b, 0xc35ac1f7,
+  0x2b2e1dbe, 0xc37b2b6a, 0x2acf277f, 0xc39c2a2f,
+  0x2a70658a, 0xc3bdbdf6, 0x2a11d8c8, 0xc3dfe66c,
+  0x29b38223, 0xc402a33c, 0x29556282, 0xc425f410,
+  0x28f77acf, 0xc449d892, 0x2899cbf1, 0xc46e5069,
+  0x283c56cf, 0xc4935b3c, 0x27df1c50, 0xc4b8f8ad,
+  0x27821d59, 0xc4df2862, 0x27255ad1, 0xc505e9fb,
+  0x26c8d59c, 0xc52d3d18, 0x266c8e9f, 0xc555215a,
+  0x261086bc, 0xc57d965d, 0x25b4bed8, 0xc5a69bbe,
+  0x255937d5, 0xc5d03118, 0x24fdf294, 0xc5fa5603,
+  0x24a2eff6, 0xc6250a18, 0x244830dd, 0xc6504ced,
+  0x23edb628, 0xc67c1e18, 0x239380b6, 0xc6a87d2d,
+  0x23399167, 0xc6d569be, 0x22dfe917, 0xc702e35c,
+  0x228688a4, 0xc730e997, 0x222d70eb, 0xc75f7bfe,
+  0x21d4a2c8, 0xc78e9a1d, 0x217c1f15, 0xc7be4381,
+  0x2123e6ad, 0xc7ee77b3, 0x20cbfa6a, 0xc81f363d,
+  0x20745b24, 0xc8507ea7, 0x201d09b4, 0xc8825077,
+  0x1fc606f1, 0xc8b4ab32, 0x1f6f53b3, 0xc8e78e5b,
+  0x1f18f0ce, 0xc91af976, 0x1ec2df18, 0xc94eec03,
+  0x1e6d1f65, 0xc9836582, 0x1e17b28a, 0xc9b86572,
+  0x1dc29958, 0xc9edeb50, 0x1d6dd4a2, 0xca23f698,
+  0x1d196538, 0xca5a86c4, 0x1cc54bec, 0xca919b4e,
+  0x1c71898d, 0xcac933ae, 0x1c1e1ee9, 0xcb014f5b,
+  0x1bcb0cce, 0xcb39edca, 0x1b785409, 0xcb730e70,
+  0x1b25f566, 0xcbacb0bf, 0x1ad3f1b1, 0xcbe6d42b,
+  0x1a8249b4, 0xcc217822, 0x1a30fe38, 0xcc5c9c14,
+  0x19e01006, 0xcc983f70, 0x198f7fe6, 0xccd461a2,
+  0x193f4e9e, 0xcd110216, 0x18ef7cf4, 0xcd4e2037,
+  0x18a00bae, 0xcd8bbb6d, 0x1850fb8e, 0xcdc9d320,
+  0x18024d59, 0xce0866b8, 0x17b401d1, 0xce47759a,
+  0x176619b6, 0xce86ff2a, 0x171895c9, 0xcec702cb,
+  0x16cb76c9, 0xcf077fe1, 0x167ebd74, 0xcf4875ca,
+  0x16326a88, 0xcf89e3e8, 0x15e67ec1, 0xcfcbc999,
+  0x159afadb, 0xd00e2639, 0x154fdf8f, 0xd050f926,
+  0x15052d97, 0xd09441bb, 0x14bae5ab, 0xd0d7ff51,
+  0x14710883, 0xd11c3142, 0x142796d5, 0xd160d6e5,
+  0x13de9156, 0xd1a5ef90, 0x1395f8ba, 0xd1eb7a9a,
+  0x134dcdb4, 0xd2317756, 0x130610f7, 0xd277e518,
+  0x12bec333, 0xd2bec333, 0x1277e518, 0xd30610f7,
+  0x12317756, 0xd34dcdb4, 0x11eb7a9a, 0xd395f8ba,
+  0x11a5ef90, 0xd3de9156, 0x1160d6e5, 0xd42796d5,
+  0x111c3142, 0xd4710883, 0x10d7ff51, 0xd4bae5ab,
+  0x109441bb, 0xd5052d97, 0x1050f926, 0xd54fdf8f,
+  0x100e2639, 0xd59afadb, 0xfcbc999, 0xd5e67ec1,
+  0xf89e3e8, 0xd6326a88, 0xf4875ca, 0xd67ebd74,
+  0xf077fe1, 0xd6cb76c9, 0xec702cb, 0xd71895c9,
+  0xe86ff2a, 0xd76619b6, 0xe47759a, 0xd7b401d1,
+  0xe0866b8, 0xd8024d59, 0xdc9d320, 0xd850fb8e,
+  0xd8bbb6d, 0xd8a00bae, 0xd4e2037, 0xd8ef7cf4,
+  0xd110216, 0xd93f4e9e, 0xcd461a2, 0xd98f7fe6,
+  0xc983f70, 0xd9e01006, 0xc5c9c14, 0xda30fe38,
+  0xc217822, 0xda8249b4, 0xbe6d42b, 0xdad3f1b1,
+  0xbacb0bf, 0xdb25f566, 0xb730e70, 0xdb785409,
+  0xb39edca, 0xdbcb0cce, 0xb014f5b, 0xdc1e1ee9,
+  0xac933ae, 0xdc71898d, 0xa919b4e, 0xdcc54bec,
+  0xa5a86c4, 0xdd196538, 0xa23f698, 0xdd6dd4a2,
+  0x9edeb50, 0xddc29958, 0x9b86572, 0xde17b28a,
+  0x9836582, 0xde6d1f65, 0x94eec03, 0xdec2df18,
+  0x91af976, 0xdf18f0ce, 0x8e78e5b, 0xdf6f53b3,
+  0x8b4ab32, 0xdfc606f1, 0x8825077, 0xe01d09b4,
+  0x8507ea7, 0xe0745b24, 0x81f363d, 0xe0cbfa6a,
+  0x7ee77b3, 0xe123e6ad, 0x7be4381, 0xe17c1f15,
+  0x78e9a1d, 0xe1d4a2c8, 0x75f7bfe, 0xe22d70eb,
+  0x730e997, 0xe28688a4, 0x702e35c, 0xe2dfe917,
+  0x6d569be, 0xe3399167, 0x6a87d2d, 0xe39380b6,
+  0x67c1e18, 0xe3edb628, 0x6504ced, 0xe44830dd,
+  0x6250a18, 0xe4a2eff6, 0x5fa5603, 0xe4fdf294,
+  0x5d03118, 0xe55937d5, 0x5a69bbe, 0xe5b4bed8,
+  0x57d965d, 0xe61086bc, 0x555215a, 0xe66c8e9f,
+  0x52d3d18, 0xe6c8d59c, 0x505e9fb, 0xe7255ad1,
+  0x4df2862, 0xe7821d59, 0x4b8f8ad, 0xe7df1c50,
+  0x4935b3c, 0xe83c56cf, 0x46e5069, 0xe899cbf1,
+  0x449d892, 0xe8f77acf, 0x425f410, 0xe9556282,
+  0x402a33c, 0xe9b38223, 0x3dfe66c, 0xea11d8c8,
+  0x3bdbdf6, 0xea70658a, 0x39c2a2f, 0xeacf277f,
+  0x37b2b6a, 0xeb2e1dbe, 0x35ac1f7, 0xeb8d475b,
+  0x33aee27, 0xebeca36c, 0x31bb049, 0xec4c3106,
+  0x2fd08a9, 0xecabef3d, 0x2def794, 0xed0bdd25,
+  0x2c17d52, 0xed6bf9d1, 0x2a49a2e, 0xedcc4454,
+  0x2884e6e, 0xee2cbbc1, 0x26c9a58, 0xee8d5f29,
+  0x2517e31, 0xeeee2d9d, 0x236fa3b, 0xef4f2630,
+  0x21d0eb8, 0xefb047f2, 0x203bbe8, 0xf01191f3,
+  0x1eb0209, 0xf0730342, 0x1d2e158, 0xf0d49af1,
+  0x1bb5a11, 0xf136580d, 0x1a46c6e, 0xf19839a6,
+  0x18e18a7, 0xf1fa3ecb, 0x1785ef4, 0xf25c6688,
+  0x1633f8a, 0xf2beafed, 0x14eba9d, 0xf3211a07,
+  0x13ad060, 0xf383a3e2, 0x1278104, 0xf3e64c8c,
+  0x114ccb9, 0xf4491311, 0x102b3ac, 0xf4abf67e,
+  0xf1360b, 0xf50ef5de, 0xe05401, 0xf572103d,
+  0xd00db6, 0xf5d544a7, 0xc06355, 0xf6389228,
+  0xb15502, 0xf69bf7c9, 0xa2e2e3, 0xf6ff7496,
+  0x950d1d, 0xf7630799, 0x87d3d0, 0xf7c6afdc,
+  0x7b371e, 0xf82a6c6a, 0x6f3726, 0xf88e3c4d,
+  0x63d405, 0xf8f21e8e, 0x590dd8, 0xf9561237,
+  0x4ee4b8, 0xf9ba1651, 0x4558c0, 0xfa1e29e5,
+  0x3c6a07, 0xfa824bfd, 0x3418a2, 0xfae67ba2,
+  0x2c64a6, 0xfb4ab7db, 0x254e27, 0xfbaeffb3,
+  0x1ed535, 0xfc135231, 0x18f9e1, 0xfc77ae5e,
+  0x13bc39, 0xfcdc1342, 0xf1c4a, 0xfd407fe6,
+  0xb1a20, 0xfda4f351, 0x7b5c4, 0xfe096c8d,
+  0x4ef3f, 0xfe6deaa1, 0x2c697, 0xfed26c94,
+  0x13bd3, 0xff36f170, 0x4ef5, 0xff9b783c,
+  0x0, 0x0, 0x4ef5, 0x6487c4,
+  0x13bd3, 0xc90e90, 0x2c697, 0x12d936c,
+  0x4ef3f, 0x192155f, 0x7b5c4, 0x1f69373,
+  0xb1a20, 0x25b0caf, 0xf1c4a, 0x2bf801a,
+  0x13bc39, 0x323ecbe, 0x18f9e1, 0x38851a2,
+  0x1ed535, 0x3ecadcf, 0x254e27, 0x451004d,
+  0x2c64a6, 0x4b54825, 0x3418a2, 0x519845e,
+  0x3c6a07, 0x57db403, 0x4558c0, 0x5e1d61b,
+  0x4ee4b8, 0x645e9af, 0x590dd8, 0x6a9edc9,
+  0x63d405, 0x70de172, 0x6f3726, 0x771c3b3,
+  0x7b371e, 0x7d59396, 0x87d3d0, 0x8395024,
+  0x950d1d, 0x89cf867, 0xa2e2e3, 0x9008b6a,
+  0xb15502, 0x9640837, 0xc06355, 0x9c76dd8,
+  0xd00db6, 0xa2abb59, 0xe05401, 0xa8defc3,
+  0xf1360b, 0xaf10a22, 0x102b3ac, 0xb540982,
+  0x114ccb9, 0xbb6ecef, 0x1278104, 0xc19b374,
+  0x13ad060, 0xc7c5c1e, 0x14eba9d, 0xcdee5f9,
+  0x1633f8a, 0xd415013, 0x1785ef4, 0xda39978,
+  0x18e18a7, 0xe05c135, 0x1a46c6e, 0xe67c65a,
+  0x1bb5a11, 0xec9a7f3, 0x1d2e158, 0xf2b650f,
+  0x1eb0209, 0xf8cfcbe, 0x203bbe8, 0xfee6e0d,
+  0x21d0eb8, 0x104fb80e, 0x236fa3b, 0x10b0d9d0,
+  0x2517e31, 0x1111d263, 0x26c9a58, 0x1172a0d7,
+  0x2884e6e, 0x11d3443f, 0x2a49a2e, 0x1233bbac,
+  0x2c17d52, 0x1294062f, 0x2def794, 0x12f422db,
+  0x2fd08a9, 0x135410c3, 0x31bb049, 0x13b3cefa,
+  0x33aee27, 0x14135c94, 0x35ac1f7, 0x1472b8a5,
+  0x37b2b6a, 0x14d1e242, 0x39c2a2f, 0x1530d881,
+  0x3bdbdf6, 0x158f9a76, 0x3dfe66c, 0x15ee2738,
+  0x402a33c, 0x164c7ddd, 0x425f410, 0x16aa9d7e,
+  0x449d892, 0x17088531, 0x46e5069, 0x1766340f,
+  0x4935b3c, 0x17c3a931, 0x4b8f8ad, 0x1820e3b0,
+  0x4df2862, 0x187de2a7, 0x505e9fb, 0x18daa52f,
+  0x52d3d18, 0x19372a64, 0x555215a, 0x19937161,
+  0x57d965d, 0x19ef7944, 0x5a69bbe, 0x1a4b4128,
+  0x5d03118, 0x1aa6c82b, 0x5fa5603, 0x1b020d6c,
+  0x6250a18, 0x1b5d100a, 0x6504ced, 0x1bb7cf23,
+  0x67c1e18, 0x1c1249d8, 0x6a87d2d, 0x1c6c7f4a,
+  0x6d569be, 0x1cc66e99, 0x702e35c, 0x1d2016e9,
+  0x730e997, 0x1d79775c, 0x75f7bfe, 0x1dd28f15,
+  0x78e9a1d, 0x1e2b5d38, 0x7be4381, 0x1e83e0eb,
+  0x7ee77b3, 0x1edc1953, 0x81f363d, 0x1f340596,
+  0x8507ea7, 0x1f8ba4dc, 0x8825077, 0x1fe2f64c,
+  0x8b4ab32, 0x2039f90f, 0x8e78e5b, 0x2090ac4d,
+  0x91af976, 0x20e70f32, 0x94eec03, 0x213d20e8,
+  0x9836582, 0x2192e09b, 0x9b86572, 0x21e84d76,
+  0x9edeb50, 0x223d66a8, 0xa23f698, 0x22922b5e,
+  0xa5a86c4, 0x22e69ac8, 0xa919b4e, 0x233ab414,
+  0xac933ae, 0x238e7673, 0xb014f5b, 0x23e1e117,
+  0xb39edca, 0x2434f332, 0xb730e70, 0x2487abf7,
+  0xbacb0bf, 0x24da0a9a, 0xbe6d42b, 0x252c0e4f,
+  0xc217822, 0x257db64c, 0xc5c9c14, 0x25cf01c8,
+  0xc983f70, 0x261feffa, 0xcd461a2, 0x2670801a,
+  0xd110216, 0x26c0b162, 0xd4e2037, 0x2710830c,
+  0xd8bbb6d, 0x275ff452, 0xdc9d320, 0x27af0472,
+  0xe0866b8, 0x27fdb2a7, 0xe47759a, 0x284bfe2f,
+  0xe86ff2a, 0x2899e64a, 0xec702cb, 0x28e76a37,
+  0xf077fe1, 0x29348937, 0xf4875ca, 0x2981428c,
+  0xf89e3e8, 0x29cd9578, 0xfcbc999, 0x2a19813f,
+  0x100e2639, 0x2a650525, 0x1050f926, 0x2ab02071,
+  0x109441bb, 0x2afad269, 0x10d7ff51, 0x2b451a55,
+  0x111c3142, 0x2b8ef77d, 0x1160d6e5, 0x2bd8692b,
+  0x11a5ef90, 0x2c216eaa, 0x11eb7a9a, 0x2c6a0746,
+  0x12317756, 0x2cb2324c, 0x1277e518, 0x2cf9ef09,
+  0x12bec333, 0x2d413ccd, 0x130610f7, 0x2d881ae8,
+  0x134dcdb4, 0x2dce88aa, 0x1395f8ba, 0x2e148566,
+  0x13de9156, 0x2e5a1070, 0x142796d5, 0x2e9f291b,
+  0x14710883, 0x2ee3cebe, 0x14bae5ab, 0x2f2800af,
+  0x15052d97, 0x2f6bbe45, 0x154fdf8f, 0x2faf06da,
+  0x159afadb, 0x2ff1d9c7, 0x15e67ec1, 0x30343667,
+  0x16326a88, 0x30761c18, 0x167ebd74, 0x30b78a36,
+  0x16cb76c9, 0x30f8801f, 0x171895c9, 0x3138fd35,
+  0x176619b6, 0x317900d6, 0x17b401d1, 0x31b88a66,
+  0x18024d59, 0x31f79948, 0x1850fb8e, 0x32362ce0,
+  0x18a00bae, 0x32744493, 0x18ef7cf4, 0x32b1dfc9,
+  0x193f4e9e, 0x32eefdea, 0x198f7fe6, 0x332b9e5e,
+  0x19e01006, 0x3367c090, 0x1a30fe38, 0x33a363ec,
+  0x1a8249b4, 0x33de87de, 0x1ad3f1b1, 0x34192bd5,
+  0x1b25f566, 0x34534f41, 0x1b785409, 0x348cf190,
+  0x1bcb0cce, 0x34c61236, 0x1c1e1ee9, 0x34feb0a5,
+  0x1c71898d, 0x3536cc52, 0x1cc54bec, 0x356e64b2,
+  0x1d196538, 0x35a5793c, 0x1d6dd4a2, 0x35dc0968,
+  0x1dc29958, 0x361214b0, 0x1e17b28a, 0x36479a8e,
+  0x1e6d1f65, 0x367c9a7e, 0x1ec2df18, 0x36b113fd,
+  0x1f18f0ce, 0x36e5068a, 0x1f6f53b3, 0x371871a5,
+  0x1fc606f1, 0x374b54ce, 0x201d09b4, 0x377daf89,
+  0x20745b24, 0x37af8159, 0x20cbfa6a, 0x37e0c9c3,
+  0x2123e6ad, 0x3811884d, 0x217c1f15, 0x3841bc7f,
+  0x21d4a2c8, 0x387165e3, 0x222d70eb, 0x38a08402,
+  0x228688a4, 0x38cf1669, 0x22dfe917, 0x38fd1ca4,
+  0x23399167, 0x392a9642, 0x239380b6, 0x395782d3,
+  0x23edb628, 0x3983e1e8, 0x244830dd, 0x39afb313,
+  0x24a2eff6, 0x39daf5e8, 0x24fdf294, 0x3a05a9fd,
+  0x255937d5, 0x3a2fcee8, 0x25b4bed8, 0x3a596442,
+  0x261086bc, 0x3a8269a3, 0x266c8e9f, 0x3aaadea6,
+  0x26c8d59c, 0x3ad2c2e8, 0x27255ad1, 0x3afa1605,
+  0x27821d59, 0x3b20d79e, 0x27df1c50, 0x3b470753,
+  0x283c56cf, 0x3b6ca4c4, 0x2899cbf1, 0x3b91af97,
+  0x28f77acf, 0x3bb6276e, 0x29556282, 0x3bda0bf0,
+  0x29b38223, 0x3bfd5cc4, 0x2a11d8c8, 0x3c201994,
+  0x2a70658a, 0x3c42420a, 0x2acf277f, 0x3c63d5d1,
+  0x2b2e1dbe, 0x3c84d496, 0x2b8d475b, 0x3ca53e09,
+  0x2beca36c, 0x3cc511d9, 0x2c4c3106, 0x3ce44fb7,
+  0x2cabef3d, 0x3d02f757, 0x2d0bdd25, 0x3d21086c,
+  0x2d6bf9d1, 0x3d3e82ae, 0x2dcc4454, 0x3d5b65d2,
+  0x2e2cbbc1, 0x3d77b192, 0x2e8d5f29, 0x3d9365a8,
+  0x2eee2d9d, 0x3dae81cf, 0x2f4f2630, 0x3dc905c5,
+  0x2fb047f2, 0x3de2f148, 0x301191f3, 0x3dfc4418,
+  0x30730342, 0x3e14fdf7, 0x30d49af1, 0x3e2d1ea8,
+  0x3136580d, 0x3e44a5ef, 0x319839a6, 0x3e5b9392,
+  0x31fa3ecb, 0x3e71e759, 0x325c6688, 0x3e87a10c,
+  0x32beafed, 0x3e9cc076, 0x33211a07, 0x3eb14563,
+  0x3383a3e2, 0x3ec52fa0, 0x33e64c8c, 0x3ed87efc,
+  0x34491311, 0x3eeb3347, 0x34abf67e, 0x3efd4c54,
+  0x350ef5de, 0x3f0ec9f5, 0x3572103d, 0x3f1fabff,
+  0x35d544a7, 0x3f2ff24a, 0x36389228, 0x3f3f9cab,
+  0x369bf7c9, 0x3f4eaafe, 0x36ff7496, 0x3f5d1d1d,
+  0x37630799, 0x3f6af2e3, 0x37c6afdc, 0x3f782c30,
+  0x382a6c6a, 0x3f84c8e2, 0x388e3c4d, 0x3f90c8da,
+  0x38f21e8e, 0x3f9c2bfb, 0x39561237, 0x3fa6f228,
+  0x39ba1651, 0x3fb11b48, 0x3a1e29e5, 0x3fbaa740,
+  0x3a824bfd, 0x3fc395f9, 0x3ae67ba2, 0x3fcbe75e,
+  0x3b4ab7db, 0x3fd39b5a, 0x3baeffb3, 0x3fdab1d9,
+  0x3c135231, 0x3fe12acb, 0x3c77ae5e, 0x3fe7061f,
+  0x3cdc1342, 0x3fec43c7, 0x3d407fe6, 0x3ff0e3b6,
+  0x3da4f351, 0x3ff4e5e0, 0x3e096c8d, 0x3ff84a3c,
+  0x3e6deaa1, 0x3ffb10c1, 0x3ed26c94, 0x3ffd3969,
+  0x3f36f170, 0x3ffec42d, 0x3f9b783c, 0x3fffb10b
+};
+
+
+/**   
+* \par  
+* Generation of realCoefBQ31 array:   
+* \par   
+*  n = 512   
+* 
for (i = 0; i < n; i++)   
+* {   
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+* } 
   
+* \par   
+* Convert to fixed point Q31 format   
+*     round(pBTable[i] * pow(2, 31))   
+*   
+*/
+
+const q31_t realCoefBQ31[1024] = {
+  0x40000000, 0x40000000, 0x406487c4, 0x3fffb10b,
+  0x40c90e90, 0x3ffec42d, 0x412d936c, 0x3ffd3969,
+  0x4192155f, 0x3ffb10c1, 0x41f69373, 0x3ff84a3c,
+  0x425b0caf, 0x3ff4e5e0, 0x42bf801a, 0x3ff0e3b6,
+  0x4323ecbe, 0x3fec43c7, 0x438851a2, 0x3fe7061f,
+  0x43ecadcf, 0x3fe12acb, 0x4451004d, 0x3fdab1d9,
+  0x44b54825, 0x3fd39b5a, 0x4519845e, 0x3fcbe75e,
+  0x457db403, 0x3fc395f9, 0x45e1d61b, 0x3fbaa740,
+  0x4645e9af, 0x3fb11b48, 0x46a9edc9, 0x3fa6f228,
+  0x470de172, 0x3f9c2bfb, 0x4771c3b3, 0x3f90c8da,
+  0x47d59396, 0x3f84c8e2, 0x48395024, 0x3f782c30,
+  0x489cf867, 0x3f6af2e3, 0x49008b6a, 0x3f5d1d1d,
+  0x49640837, 0x3f4eaafe, 0x49c76dd8, 0x3f3f9cab,
+  0x4a2abb59, 0x3f2ff24a, 0x4a8defc3, 0x3f1fabff,
+  0x4af10a22, 0x3f0ec9f5, 0x4b540982, 0x3efd4c54,
+  0x4bb6ecef, 0x3eeb3347, 0x4c19b374, 0x3ed87efc,
+  0x4c7c5c1e, 0x3ec52fa0, 0x4cdee5f9, 0x3eb14563,
+  0x4d415013, 0x3e9cc076, 0x4da39978, 0x3e87a10c,
+  0x4e05c135, 0x3e71e759, 0x4e67c65a, 0x3e5b9392,
+  0x4ec9a7f3, 0x3e44a5ef, 0x4f2b650f, 0x3e2d1ea8,
+  0x4f8cfcbe, 0x3e14fdf7, 0x4fee6e0d, 0x3dfc4418,
+  0x504fb80e, 0x3de2f148, 0x50b0d9d0, 0x3dc905c5,
+  0x5111d263, 0x3dae81cf, 0x5172a0d7, 0x3d9365a8,
+  0x51d3443f, 0x3d77b192, 0x5233bbac, 0x3d5b65d2,
+  0x5294062f, 0x3d3e82ae, 0x52f422db, 0x3d21086c,
+  0x535410c3, 0x3d02f757, 0x53b3cefa, 0x3ce44fb7,
+  0x54135c94, 0x3cc511d9, 0x5472b8a5, 0x3ca53e09,
+  0x54d1e242, 0x3c84d496, 0x5530d881, 0x3c63d5d1,
+  0x558f9a76, 0x3c42420a, 0x55ee2738, 0x3c201994,
+  0x564c7ddd, 0x3bfd5cc4, 0x56aa9d7e, 0x3bda0bf0,
+  0x57088531, 0x3bb6276e, 0x5766340f, 0x3b91af97,
+  0x57c3a931, 0x3b6ca4c4, 0x5820e3b0, 0x3b470753,
+  0x587de2a7, 0x3b20d79e, 0x58daa52f, 0x3afa1605,
+  0x59372a64, 0x3ad2c2e8, 0x59937161, 0x3aaadea6,
+  0x59ef7944, 0x3a8269a3, 0x5a4b4128, 0x3a596442,
+  0x5aa6c82b, 0x3a2fcee8, 0x5b020d6c, 0x3a05a9fd,
+  0x5b5d100a, 0x39daf5e8, 0x5bb7cf23, 0x39afb313,
+  0x5c1249d8, 0x3983e1e8, 0x5c6c7f4a, 0x395782d3,
+  0x5cc66e99, 0x392a9642, 0x5d2016e9, 0x38fd1ca4,
+  0x5d79775c, 0x38cf1669, 0x5dd28f15, 0x38a08402,
+  0x5e2b5d38, 0x387165e3, 0x5e83e0eb, 0x3841bc7f,
+  0x5edc1953, 0x3811884d, 0x5f340596, 0x37e0c9c3,
+  0x5f8ba4dc, 0x37af8159, 0x5fe2f64c, 0x377daf89,
+  0x6039f90f, 0x374b54ce, 0x6090ac4d, 0x371871a5,
+  0x60e70f32, 0x36e5068a, 0x613d20e8, 0x36b113fd,
+  0x6192e09b, 0x367c9a7e, 0x61e84d76, 0x36479a8e,
+  0x623d66a8, 0x361214b0, 0x62922b5e, 0x35dc0968,
+  0x62e69ac8, 0x35a5793c, 0x633ab414, 0x356e64b2,
+  0x638e7673, 0x3536cc52, 0x63e1e117, 0x34feb0a5,
+  0x6434f332, 0x34c61236, 0x6487abf7, 0x348cf190,
+  0x64da0a9a, 0x34534f41, 0x652c0e4f, 0x34192bd5,
+  0x657db64c, 0x33de87de, 0x65cf01c8, 0x33a363ec,
+  0x661feffa, 0x3367c090, 0x6670801a, 0x332b9e5e,
+  0x66c0b162, 0x32eefdea, 0x6710830c, 0x32b1dfc9,
+  0x675ff452, 0x32744493, 0x67af0472, 0x32362ce0,
+  0x67fdb2a7, 0x31f79948, 0x684bfe2f, 0x31b88a66,
+  0x6899e64a, 0x317900d6, 0x68e76a37, 0x3138fd35,
+  0x69348937, 0x30f8801f, 0x6981428c, 0x30b78a36,
+  0x69cd9578, 0x30761c18, 0x6a19813f, 0x30343667,
+  0x6a650525, 0x2ff1d9c7, 0x6ab02071, 0x2faf06da,
+  0x6afad269, 0x2f6bbe45, 0x6b451a55, 0x2f2800af,
+  0x6b8ef77d, 0x2ee3cebe, 0x6bd8692b, 0x2e9f291b,
+  0x6c216eaa, 0x2e5a1070, 0x6c6a0746, 0x2e148566,
+  0x6cb2324c, 0x2dce88aa, 0x6cf9ef09, 0x2d881ae8,
+  0x6d413ccd, 0x2d413ccd, 0x6d881ae8, 0x2cf9ef09,
+  0x6dce88aa, 0x2cb2324c, 0x6e148566, 0x2c6a0746,
+  0x6e5a1070, 0x2c216eaa, 0x6e9f291b, 0x2bd8692b,
+  0x6ee3cebe, 0x2b8ef77d, 0x6f2800af, 0x2b451a55,
+  0x6f6bbe45, 0x2afad269, 0x6faf06da, 0x2ab02071,
+  0x6ff1d9c7, 0x2a650525, 0x70343667, 0x2a19813f,
+  0x70761c18, 0x29cd9578, 0x70b78a36, 0x2981428c,
+  0x70f8801f, 0x29348937, 0x7138fd35, 0x28e76a37,
+  0x717900d6, 0x2899e64a, 0x71b88a66, 0x284bfe2f,
+  0x71f79948, 0x27fdb2a7, 0x72362ce0, 0x27af0472,
+  0x72744493, 0x275ff452, 0x72b1dfc9, 0x2710830c,
+  0x72eefdea, 0x26c0b162, 0x732b9e5e, 0x2670801a,
+  0x7367c090, 0x261feffa, 0x73a363ec, 0x25cf01c8,
+  0x73de87de, 0x257db64c, 0x74192bd5, 0x252c0e4f,
+  0x74534f41, 0x24da0a9a, 0x748cf190, 0x2487abf7,
+  0x74c61236, 0x2434f332, 0x74feb0a5, 0x23e1e117,
+  0x7536cc52, 0x238e7673, 0x756e64b2, 0x233ab414,
+  0x75a5793c, 0x22e69ac8, 0x75dc0968, 0x22922b5e,
+  0x761214b0, 0x223d66a8, 0x76479a8e, 0x21e84d76,
+  0x767c9a7e, 0x2192e09b, 0x76b113fd, 0x213d20e8,
+  0x76e5068a, 0x20e70f32, 0x771871a5, 0x2090ac4d,
+  0x774b54ce, 0x2039f90f, 0x777daf89, 0x1fe2f64c,
+  0x77af8159, 0x1f8ba4dc, 0x77e0c9c3, 0x1f340596,
+  0x7811884d, 0x1edc1953, 0x7841bc7f, 0x1e83e0eb,
+  0x787165e3, 0x1e2b5d38, 0x78a08402, 0x1dd28f15,
+  0x78cf1669, 0x1d79775c, 0x78fd1ca4, 0x1d2016e9,
+  0x792a9642, 0x1cc66e99, 0x795782d3, 0x1c6c7f4a,
+  0x7983e1e8, 0x1c1249d8, 0x79afb313, 0x1bb7cf23,
+  0x79daf5e8, 0x1b5d100a, 0x7a05a9fd, 0x1b020d6c,
+  0x7a2fcee8, 0x1aa6c82b, 0x7a596442, 0x1a4b4128,
+  0x7a8269a3, 0x19ef7944, 0x7aaadea6, 0x19937161,
+  0x7ad2c2e8, 0x19372a64, 0x7afa1605, 0x18daa52f,
+  0x7b20d79e, 0x187de2a7, 0x7b470753, 0x1820e3b0,
+  0x7b6ca4c4, 0x17c3a931, 0x7b91af97, 0x1766340f,
+  0x7bb6276e, 0x17088531, 0x7bda0bf0, 0x16aa9d7e,
+  0x7bfd5cc4, 0x164c7ddd, 0x7c201994, 0x15ee2738,
+  0x7c42420a, 0x158f9a76, 0x7c63d5d1, 0x1530d881,
+  0x7c84d496, 0x14d1e242, 0x7ca53e09, 0x1472b8a5,
+  0x7cc511d9, 0x14135c94, 0x7ce44fb7, 0x13b3cefa,
+  0x7d02f757, 0x135410c3, 0x7d21086c, 0x12f422db,
+  0x7d3e82ae, 0x1294062f, 0x7d5b65d2, 0x1233bbac,
+  0x7d77b192, 0x11d3443f, 0x7d9365a8, 0x1172a0d7,
+  0x7dae81cf, 0x1111d263, 0x7dc905c5, 0x10b0d9d0,
+  0x7de2f148, 0x104fb80e, 0x7dfc4418, 0xfee6e0d,
+  0x7e14fdf7, 0xf8cfcbe, 0x7e2d1ea8, 0xf2b650f,
+  0x7e44a5ef, 0xec9a7f3, 0x7e5b9392, 0xe67c65a,
+  0x7e71e759, 0xe05c135, 0x7e87a10c, 0xda39978,
+  0x7e9cc076, 0xd415013, 0x7eb14563, 0xcdee5f9,
+  0x7ec52fa0, 0xc7c5c1e, 0x7ed87efc, 0xc19b374,
+  0x7eeb3347, 0xbb6ecef, 0x7efd4c54, 0xb540982,
+  0x7f0ec9f5, 0xaf10a22, 0x7f1fabff, 0xa8defc3,
+  0x7f2ff24a, 0xa2abb59, 0x7f3f9cab, 0x9c76dd8,
+  0x7f4eaafe, 0x9640837, 0x7f5d1d1d, 0x9008b6a,
+  0x7f6af2e3, 0x89cf867, 0x7f782c30, 0x8395024,
+  0x7f84c8e2, 0x7d59396, 0x7f90c8da, 0x771c3b3,
+  0x7f9c2bfb, 0x70de172, 0x7fa6f228, 0x6a9edc9,
+  0x7fb11b48, 0x645e9af, 0x7fbaa740, 0x5e1d61b,
+  0x7fc395f9, 0x57db403, 0x7fcbe75e, 0x519845e,
+  0x7fd39b5a, 0x4b54825, 0x7fdab1d9, 0x451004d,
+  0x7fe12acb, 0x3ecadcf, 0x7fe7061f, 0x38851a2,
+  0x7fec43c7, 0x323ecbe, 0x7ff0e3b6, 0x2bf801a,
+  0x7ff4e5e0, 0x25b0caf, 0x7ff84a3c, 0x1f69373,
+  0x7ffb10c1, 0x192155f, 0x7ffd3969, 0x12d936c,
+  0x7ffec42d, 0xc90e90, 0x7fffb10b, 0x6487c4,
+  0x7fffffff, 0x0, 0x7fffb10b, 0xff9b783c,
+  0x7ffec42d, 0xff36f170, 0x7ffd3969, 0xfed26c94,
+  0x7ffb10c1, 0xfe6deaa1, 0x7ff84a3c, 0xfe096c8d,
+  0x7ff4e5e0, 0xfda4f351, 0x7ff0e3b6, 0xfd407fe6,
+  0x7fec43c7, 0xfcdc1342, 0x7fe7061f, 0xfc77ae5e,
+  0x7fe12acb, 0xfc135231, 0x7fdab1d9, 0xfbaeffb3,
+  0x7fd39b5a, 0xfb4ab7db, 0x7fcbe75e, 0xfae67ba2,
+  0x7fc395f9, 0xfa824bfd, 0x7fbaa740, 0xfa1e29e5,
+  0x7fb11b48, 0xf9ba1651, 0x7fa6f228, 0xf9561237,
+  0x7f9c2bfb, 0xf8f21e8e, 0x7f90c8da, 0xf88e3c4d,
+  0x7f84c8e2, 0xf82a6c6a, 0x7f782c30, 0xf7c6afdc,
+  0x7f6af2e3, 0xf7630799, 0x7f5d1d1d, 0xf6ff7496,
+  0x7f4eaafe, 0xf69bf7c9, 0x7f3f9cab, 0xf6389228,
+  0x7f2ff24a, 0xf5d544a7, 0x7f1fabff, 0xf572103d,
+  0x7f0ec9f5, 0xf50ef5de, 0x7efd4c54, 0xf4abf67e,
+  0x7eeb3347, 0xf4491311, 0x7ed87efc, 0xf3e64c8c,
+  0x7ec52fa0, 0xf383a3e2, 0x7eb14563, 0xf3211a07,
+  0x7e9cc076, 0xf2beafed, 0x7e87a10c, 0xf25c6688,
+  0x7e71e759, 0xf1fa3ecb, 0x7e5b9392, 0xf19839a6,
+  0x7e44a5ef, 0xf136580d, 0x7e2d1ea8, 0xf0d49af1,
+  0x7e14fdf7, 0xf0730342, 0x7dfc4418, 0xf01191f3,
+  0x7de2f148, 0xefb047f2, 0x7dc905c5, 0xef4f2630,
+  0x7dae81cf, 0xeeee2d9d, 0x7d9365a8, 0xee8d5f29,
+  0x7d77b192, 0xee2cbbc1, 0x7d5b65d2, 0xedcc4454,
+  0x7d3e82ae, 0xed6bf9d1, 0x7d21086c, 0xed0bdd25,
+  0x7d02f757, 0xecabef3d, 0x7ce44fb7, 0xec4c3106,
+  0x7cc511d9, 0xebeca36c, 0x7ca53e09, 0xeb8d475b,
+  0x7c84d496, 0xeb2e1dbe, 0x7c63d5d1, 0xeacf277f,
+  0x7c42420a, 0xea70658a, 0x7c201994, 0xea11d8c8,
+  0x7bfd5cc4, 0xe9b38223, 0x7bda0bf0, 0xe9556282,
+  0x7bb6276e, 0xe8f77acf, 0x7b91af97, 0xe899cbf1,
+  0x7b6ca4c4, 0xe83c56cf, 0x7b470753, 0xe7df1c50,
+  0x7b20d79e, 0xe7821d59, 0x7afa1605, 0xe7255ad1,
+  0x7ad2c2e8, 0xe6c8d59c, 0x7aaadea6, 0xe66c8e9f,
+  0x7a8269a3, 0xe61086bc, 0x7a596442, 0xe5b4bed8,
+  0x7a2fcee8, 0xe55937d5, 0x7a05a9fd, 0xe4fdf294,
+  0x79daf5e8, 0xe4a2eff6, 0x79afb313, 0xe44830dd,
+  0x7983e1e8, 0xe3edb628, 0x795782d3, 0xe39380b6,
+  0x792a9642, 0xe3399167, 0x78fd1ca4, 0xe2dfe917,
+  0x78cf1669, 0xe28688a4, 0x78a08402, 0xe22d70eb,
+  0x787165e3, 0xe1d4a2c8, 0x7841bc7f, 0xe17c1f15,
+  0x7811884d, 0xe123e6ad, 0x77e0c9c3, 0xe0cbfa6a,
+  0x77af8159, 0xe0745b24, 0x777daf89, 0xe01d09b4,
+  0x774b54ce, 0xdfc606f1, 0x771871a5, 0xdf6f53b3,
+  0x76e5068a, 0xdf18f0ce, 0x76b113fd, 0xdec2df18,
+  0x767c9a7e, 0xde6d1f65, 0x76479a8e, 0xde17b28a,
+  0x761214b0, 0xddc29958, 0x75dc0968, 0xdd6dd4a2,
+  0x75a5793c, 0xdd196538, 0x756e64b2, 0xdcc54bec,
+  0x7536cc52, 0xdc71898d, 0x74feb0a5, 0xdc1e1ee9,
+  0x74c61236, 0xdbcb0cce, 0x748cf190, 0xdb785409,
+  0x74534f41, 0xdb25f566, 0x74192bd5, 0xdad3f1b1,
+  0x73de87de, 0xda8249b4, 0x73a363ec, 0xda30fe38,
+  0x7367c090, 0xd9e01006, 0x732b9e5e, 0xd98f7fe6,
+  0x72eefdea, 0xd93f4e9e, 0x72b1dfc9, 0xd8ef7cf4,
+  0x72744493, 0xd8a00bae, 0x72362ce0, 0xd850fb8e,
+  0x71f79948, 0xd8024d59, 0x71b88a66, 0xd7b401d1,
+  0x717900d6, 0xd76619b6, 0x7138fd35, 0xd71895c9,
+  0x70f8801f, 0xd6cb76c9, 0x70b78a36, 0xd67ebd74,
+  0x70761c18, 0xd6326a88, 0x70343667, 0xd5e67ec1,
+  0x6ff1d9c7, 0xd59afadb, 0x6faf06da, 0xd54fdf8f,
+  0x6f6bbe45, 0xd5052d97, 0x6f2800af, 0xd4bae5ab,
+  0x6ee3cebe, 0xd4710883, 0x6e9f291b, 0xd42796d5,
+  0x6e5a1070, 0xd3de9156, 0x6e148566, 0xd395f8ba,
+  0x6dce88aa, 0xd34dcdb4, 0x6d881ae8, 0xd30610f7,
+  0x6d413ccd, 0xd2bec333, 0x6cf9ef09, 0xd277e518,
+  0x6cb2324c, 0xd2317756, 0x6c6a0746, 0xd1eb7a9a,
+  0x6c216eaa, 0xd1a5ef90, 0x6bd8692b, 0xd160d6e5,
+  0x6b8ef77d, 0xd11c3142, 0x6b451a55, 0xd0d7ff51,
+  0x6afad269, 0xd09441bb, 0x6ab02071, 0xd050f926,
+  0x6a650525, 0xd00e2639, 0x6a19813f, 0xcfcbc999,
+  0x69cd9578, 0xcf89e3e8, 0x6981428c, 0xcf4875ca,
+  0x69348937, 0xcf077fe1, 0x68e76a37, 0xcec702cb,
+  0x6899e64a, 0xce86ff2a, 0x684bfe2f, 0xce47759a,
+  0x67fdb2a7, 0xce0866b8, 0x67af0472, 0xcdc9d320,
+  0x675ff452, 0xcd8bbb6d, 0x6710830c, 0xcd4e2037,
+  0x66c0b162, 0xcd110216, 0x6670801a, 0xccd461a2,
+  0x661feffa, 0xcc983f70, 0x65cf01c8, 0xcc5c9c14,
+  0x657db64c, 0xcc217822, 0x652c0e4f, 0xcbe6d42b,
+  0x64da0a9a, 0xcbacb0bf, 0x6487abf7, 0xcb730e70,
+  0x6434f332, 0xcb39edca, 0x63e1e117, 0xcb014f5b,
+  0x638e7673, 0xcac933ae, 0x633ab414, 0xca919b4e,
+  0x62e69ac8, 0xca5a86c4, 0x62922b5e, 0xca23f698,
+  0x623d66a8, 0xc9edeb50, 0x61e84d76, 0xc9b86572,
+  0x6192e09b, 0xc9836582, 0x613d20e8, 0xc94eec03,
+  0x60e70f32, 0xc91af976, 0x6090ac4d, 0xc8e78e5b,
+  0x6039f90f, 0xc8b4ab32, 0x5fe2f64c, 0xc8825077,
+  0x5f8ba4dc, 0xc8507ea7, 0x5f340596, 0xc81f363d,
+  0x5edc1953, 0xc7ee77b3, 0x5e83e0eb, 0xc7be4381,
+  0x5e2b5d38, 0xc78e9a1d, 0x5dd28f15, 0xc75f7bfe,
+  0x5d79775c, 0xc730e997, 0x5d2016e9, 0xc702e35c,
+  0x5cc66e99, 0xc6d569be, 0x5c6c7f4a, 0xc6a87d2d,
+  0x5c1249d8, 0xc67c1e18, 0x5bb7cf23, 0xc6504ced,
+  0x5b5d100a, 0xc6250a18, 0x5b020d6c, 0xc5fa5603,
+  0x5aa6c82b, 0xc5d03118, 0x5a4b4128, 0xc5a69bbe,
+  0x59ef7944, 0xc57d965d, 0x59937161, 0xc555215a,
+  0x59372a64, 0xc52d3d18, 0x58daa52f, 0xc505e9fb,
+  0x587de2a7, 0xc4df2862, 0x5820e3b0, 0xc4b8f8ad,
+  0x57c3a931, 0xc4935b3c, 0x5766340f, 0xc46e5069,
+  0x57088531, 0xc449d892, 0x56aa9d7e, 0xc425f410,
+  0x564c7ddd, 0xc402a33c, 0x55ee2738, 0xc3dfe66c,
+  0x558f9a76, 0xc3bdbdf6, 0x5530d881, 0xc39c2a2f,
+  0x54d1e242, 0xc37b2b6a, 0x5472b8a5, 0xc35ac1f7,
+  0x54135c94, 0xc33aee27, 0x53b3cefa, 0xc31bb049,
+  0x535410c3, 0xc2fd08a9, 0x52f422db, 0xc2def794,
+  0x5294062f, 0xc2c17d52, 0x5233bbac, 0xc2a49a2e,
+  0x51d3443f, 0xc2884e6e, 0x5172a0d7, 0xc26c9a58,
+  0x5111d263, 0xc2517e31, 0x50b0d9d0, 0xc236fa3b,
+  0x504fb80e, 0xc21d0eb8, 0x4fee6e0d, 0xc203bbe8,
+  0x4f8cfcbe, 0xc1eb0209, 0x4f2b650f, 0xc1d2e158,
+  0x4ec9a7f3, 0xc1bb5a11, 0x4e67c65a, 0xc1a46c6e,
+  0x4e05c135, 0xc18e18a7, 0x4da39978, 0xc1785ef4,
+  0x4d415013, 0xc1633f8a, 0x4cdee5f9, 0xc14eba9d,
+  0x4c7c5c1e, 0xc13ad060, 0x4c19b374, 0xc1278104,
+  0x4bb6ecef, 0xc114ccb9, 0x4b540982, 0xc102b3ac,
+  0x4af10a22, 0xc0f1360b, 0x4a8defc3, 0xc0e05401,
+  0x4a2abb59, 0xc0d00db6, 0x49c76dd8, 0xc0c06355,
+  0x49640837, 0xc0b15502, 0x49008b6a, 0xc0a2e2e3,
+  0x489cf867, 0xc0950d1d, 0x48395024, 0xc087d3d0,
+  0x47d59396, 0xc07b371e, 0x4771c3b3, 0xc06f3726,
+  0x470de172, 0xc063d405, 0x46a9edc9, 0xc0590dd8,
+  0x4645e9af, 0xc04ee4b8, 0x45e1d61b, 0xc04558c0,
+  0x457db403, 0xc03c6a07, 0x4519845e, 0xc03418a2,
+  0x44b54825, 0xc02c64a6, 0x4451004d, 0xc0254e27,
+  0x43ecadcf, 0xc01ed535, 0x438851a2, 0xc018f9e1,
+  0x4323ecbe, 0xc013bc39, 0x42bf801a, 0xc00f1c4a,
+  0x425b0caf, 0xc00b1a20, 0x41f69373, 0xc007b5c4,
+  0x4192155f, 0xc004ef3f, 0x412d936c, 0xc002c697,
+  0x40c90e90, 0xc0013bd3, 0x406487c4, 0xc0004ef5
+};
+
+/**   
+* @brief  Initialization function for the Q31 RFFT/RIFFT.  
+* @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.  
+* @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.  
+* @param[in]      fftLenReal     length of the FFT.  
+* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.  
+* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.  
+*   
+* \par Description:  
+* \par  
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.   
+* \par   
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.   
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.  
+* \par   
+* This function also initializes Twiddle factor table.   
+*/
+
+arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (q31_t *) realCoefAQ31;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (q31_t *) realCoefBQ31;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initialization of coef modifier depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+  case 512u:
+    S->twidCoefRModifier = 2u;
+    break;
+  case 128u:
+    S->twidCoefRModifier = 8u;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if(S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 1u, 1u);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 0u, 1u);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
new file mode 100644
index 0000000..dabde59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
@@ -0,0 +1,457 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_q15.c   
+*   
+* Description:	RFFT & RIFFT Q15 process function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------   
+*		Internal functions prototypes   
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier);
+
+void arm_split_rifft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier);
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 RFFT/RIFFT.  
+ * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.  
+ * @param[in]  *pSrc points to the input buffer.  
+ * @param[out] *pDst points to the output buffer.  
+ * @return none.  
+ *   
+ * \par Input an output formats:  
+ * \par   
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
+ * Hence the output format is different for different RFFT sizes.   
+ * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:  
+ * \par   
+ * \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"   
+ * \par   
+ * \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"   
+ */
+
+void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst)
+{
+  const arm_cfft_radix4_instance_q15 *S_CFFT = S->pCfft;
+
+  /* Calculation of RIFFT of input */
+  if(S->ifftFlagR == 1u)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+    /* Complex readix-4 IFFT process */
+    arm_radix4_butterfly_inverse_q15(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q15(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+    /* Calculation of RFFT of input */
+
+    /* Complex readix-4 FFT process */
+    arm_radix4_butterfly_q15(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q15(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+    arm_split_rfft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
+
+/**   
+ * @brief  Core Real FFT process   
+ * @param  *pSrc 				points to the input buffer.  
+ * @param  fftLen  				length of FFT.  
+ * @param  *pATable 			points to the A twiddle Coef buffer.   
+ * @param  *pBTable 			points to the B twiddle Coef buffer.  
+ * @param  *pDst 				points to the output buffer.  
+ * @param  modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ * The function implements a Real FFT   
+ */
+
+void arm_split_rfft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q15_t *pSrc1, *pSrc2;
+
+
+  pSrc[2u * fftLen] = pSrc[0];
+  pSrc[(2u * fftLen) + 1u] = pSrc[1];
+
+  pCoefA = &pATable[modifier * 2u];
+  pCoefB = &pBTable[modifier * 2u];
+
+  pSrc1 = &pSrc[2];
+  pSrc2 = &pSrc[(2u * fftLen) - 2u];
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  i = 1u;
+
+  while(i < fftLen)
+  {
+    /*   
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]   
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+    outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));
+
+#else
+
+    /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
+    outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+    outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 15u;
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+#else
+
+    outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
+    outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);
+
+    /* write output */
+    pDst[2u * i] = (q15_t) outR;
+    pDst[(2u * i) + 1u] = outI >> 15u;
+
+    /* write complex conjugate output */
+    pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+    pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i++;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  i = 1u;
+
+  while(i < fftLen)
+  {
+    /*   
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]   
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    outR = *pSrc1 * *pCoefA;
+    outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));
+    outR = outR + (*pSrc2 * *pCoefB);
+    outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 15;
+
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);  
+     */
+
+    outI = *pSrc2 * *(pCoefB + 1);
+    outI = outI - (*(pSrc2 + 1) * *pCoefB);
+    outI = outI + (*(pSrc1 + 1) * *pCoefA);
+    outI = outI + (*pSrc1 * *(pCoefA + 1));
+
+    /* update input pointers */
+    pSrc1 += 2u;
+    pSrc2 -= 2u;
+
+    /* write output */
+    pDst[2u * i] = (q15_t) outR;
+    pDst[(2u * i) + 1u] = outI >> 15u;
+
+    /* write complex conjugate output */
+    pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+    pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i++;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**   
+ * @brief  Core Real IFFT process   
+ * @param[in]   *pSrc 				points to the input buffer.   
+ * @param[in]   fftLen  		    length of FFT.  
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.  
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.  
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ * The function implements a Real IFFT   
+ */
+void arm_split_rifft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q15_t *pSrc1, *pSrc2;
+  q15_t *pDst1 = &pDst[0];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  pSrc1 = &pSrc[0];
+  pSrc2 = &pSrc[2u * fftLen];
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  i = fftLen;
+
+  while(i > 0u)
+  {
+
+    /*   
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+
+     */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+    outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));
+
+#else
+
+    /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] + 
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
+    outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] */
+    outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 15u;
+
+    /*   
+       -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+    outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+    /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);
+
+#else
+
+    outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+    /* write output */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 15u), 16);
+
+#else
+
+    *__SIMD32(pDst1)++ = __PKHBT((outI >> 15u), outR, 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i--;
+
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  i = fftLen;
+
+  while(i > 0u)
+  {
+
+    /*   
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    outR = *pSrc2 * *pCoefB;
+    outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));
+    outR = outR + (*pSrc1 * *pCoefA);
+    outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 15;
+
+    /*  
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -  
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -  
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);  
+     */
+
+    outI = *(pSrc1 + 1) * *pCoefA;
+    outI = outI - (*pSrc1 * *(pCoefA + 1));
+    outI = outI - (*pSrc2 * *(pCoefB + 1));
+    outI = outI - (*(pSrc2 + 1) * *(pCoefB));
+
+    /* update input pointers */
+    pSrc1 += 2u;
+    pSrc2 -= 2u;
+
+    /* write output */
+    *pDst1++ = (q15_t) outR;
+    *pDst1++ = (q15_t) (outI >> 15);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
new file mode 100644
index 0000000..76c92cd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
@@ -0,0 +1,326 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_q31.c   
+*   
+* Description:	RFFT & RIFFT Q31 process function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------   
+*		Internal functions prototypes   
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier);
+
+void arm_split_rifft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier);
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 RFFT/RIFFT.  
+ * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.  
+ * @param[in]  *pSrc points to the input buffer.  
+ * @param[out] *pDst points to the output buffer.  
+ * @return none.  
+ *   
+ * \par Input an output formats:  
+ * \par   
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.  
+ * Hence the output format is different for different RFFT sizes.   
+ * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:  
+ * \par   
+ * \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT"   
+ *   
+ * \par   
+ * \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT"   
+ */
+
+void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst)
+{
+  const arm_cfft_radix4_instance_q31 *S_CFFT = S->pCfft;
+
+  /* Calculation of RIFFT of input */
+  if(S->ifftFlagR == 1u)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+    /* Complex readix-4 IFFT process */
+    arm_radix4_butterfly_inverse_q31(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier);
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q31(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+    /* Calculation of RFFT of input */
+
+    /* Complex readix-4 FFT process */
+    arm_radix4_butterfly_q31(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q31(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+    /*  Real FFT core process */
+    arm_split_rfft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
+
+/**   
+ * @brief  Core Real FFT process   
+ * @param[in]   *pSrc 				points to the input buffer.   
+ * @param[in]   fftLen  			length of FFT.  
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.   
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ */
+
+void arm_split_rfft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
+  q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[(4u * fftLen) - 1u];
+  q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[(2u * fftLen) - 1u];
+
+  pSrc[2u * fftLen] = pSrc[0];
+  pSrc[(2u * fftLen) + 1u] = pSrc[1];
+
+  /* Init coefficient pointers */
+  pCoefA = &pATable[modifier * 2u];
+  pCoefB = &pBTable[modifier * 2u];
+
+  i = fftLen - 1u;
+
+  while(i > 0u)
+  {
+    /*   
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]   
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pSrc[2 * i] * pATable[2 * i] */
+    outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
+
+    /* outI = pIn[2 * i] * pATable[2 * i + 1] */
+    outI = ((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
+
+    /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (-CoefA2))) >> 32);
+
+    /* (pIn[2 * i + 1] * pATable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
+
+    /* pSrc[2 * n - 2 * i] * pBTable[2 * i]  */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (-CoefA2))) >> 32);
+    CoefB1 = *pCoefB;
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefB1))) >> 32);
+
+    /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
+
+    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefA2))) >> 32);
+
+    /* write output */
+    *pOut1++ = (outR << 1u);
+    *pOut1++ = (outI << 1u);
+
+    /* write complex conjugate output */
+    *pOut2-- = -(outI << 1u);
+    *pOut2-- = (outR << 1u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    i--;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0;
+
+}
+
+
+/**   
+ * @brief  Core Real IFFT process   
+ * @param[in]   *pSrc 				points to the input buffer.  
+ * @param[in]   fftLen  			length of FFT.   
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.  
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.  
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ */
+
+void arm_split_rifft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier)
+{
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
+  q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[(2u * fftLen) + 1u];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  while(fftLen > 0u)
+  {
+    /*   
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+
+     */
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pIn[2 * i] * pATable[2 * i] */
+    outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
+
+    /* - pIn[2 * i] * pATable[2 * i + 1] */
+    outI = -((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
+
+    /* pIn[2 * i + 1] * pATable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (CoefA2))) >> 32);
+
+    /* pIn[2 * i + 1] * pATable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefA2))) >> 32);
+
+    CoefB1 = *pCoefB;
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) - ((q63_t) * pIn2-- * (CoefB1))) >> 32);
+
+    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
+
+    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (CoefA2))) >> 32);
+
+    /* write output */
+    *pDst++ = (outR << 1u);
+    *pDst++ = (outI << 1u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    /* Decrement loop count */
+    fftLen--;
+
+  }
+
+
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM0_math.ewp b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM0_math.ewp
new file mode 100644
index 0000000..362e181
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM0_math.ewp
@@ -0,0 +1,4345 @@
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM3_math.ewp b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM3_math.ewp
new file mode 100644
index 0000000..b3c8952
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM3_math.ewp
@@ -0,0 +1,4393 @@
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM4F_math.ewp b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM4F_math.ewp
new file mode 100644
index 0000000..c9956fe
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM4F_math.ewp
@@ -0,0 +1,4397 @@
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+      $PROJ_DIR$\..\BasicMathFunctions\arm_offset_q31.c
+    
+    
+      $PROJ_DIR$\..\BasicMathFunctions\arm_offset_q7.c
+    
+    
+      $PROJ_DIR$\..\BasicMathFunctions\arm_scale_f32.c
+    
+    
+      $PROJ_DIR$\..\BasicMathFunctions\arm_scale_q15.c
+    
+    
+      $PROJ_DIR$\..\BasicMathFunctions\arm_scale_q31.c
+    
+    
+      $PROJ_DIR$\..\BasicMathFunctions\arm_scale_q7.c
+    
+    
+      $PROJ_DIR$\..\BasicMathFunctions\arm_shift_q15.c
+    
+    
+      $PROJ_DIR$\..\BasicMathFunctions\arm_shift_q31.c
+    
+    
+      $PROJ_DIR$\..\BasicMathFunctions\arm_shift_q7.c
+    
+    
+      $PROJ_DIR$\..\BasicMathFunctions\arm_sub_f32.c
+    
+    
+      $PROJ_DIR$\..\BasicMathFunctions\arm_sub_q15.c
+    
+    
+      $PROJ_DIR$\..\BasicMathFunctions\arm_sub_q31.c
+    
+    
+      $PROJ_DIR$\..\BasicMathFunctions\arm_sub_q7.c
+    
+  
+  
+    CommonTables
+    
+      $PROJ_DIR$\..\CommonTables\arm_common_tables.c
+    
+  
+  
+    ComplexMathFunctions
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_conj_f32.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_conj_q15.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_conj_q31.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_dot_prod_f32.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_dot_prod_q15.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_dot_prod_q31.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_mag_f32.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_mag_q15.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_mag_q31.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_mag_squared_f32.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_mag_squared_q15.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_mag_squared_q31.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_mult_cmplx_f32.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_mult_cmplx_q15.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_mult_cmplx_q31.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_mult_real_f32.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_mult_real_q15.c
+    
+    
+      $PROJ_DIR$\..\ComplexMathFunctions\arm_cmplx_mult_real_q31.c
+    
+  
+  
+    ControllerFunctions
+    
+      $PROJ_DIR$\..\ControllerFunctions\arm_pid_init_f32.c
+    
+    
+      $PROJ_DIR$\..\ControllerFunctions\arm_pid_init_q15.c
+    
+    
+      $PROJ_DIR$\..\ControllerFunctions\arm_pid_init_q31.c
+    
+    
+      $PROJ_DIR$\..\ControllerFunctions\arm_pid_reset_f32.c
+    
+    
+      $PROJ_DIR$\..\ControllerFunctions\arm_pid_reset_q15.c
+    
+    
+      $PROJ_DIR$\..\ControllerFunctions\arm_pid_reset_q31.c
+    
+    
+      $PROJ_DIR$\..\ControllerFunctions\arm_sin_cos_f32.c
+    
+    
+      $PROJ_DIR$\..\ControllerFunctions\arm_sin_cos_q31.c
+    
+  
+  
+    FastMathFunctions
+    
+      $PROJ_DIR$\..\FastMathFunctions\arm_cos_f32.c
+    
+    
+      $PROJ_DIR$\..\FastMathFunctions\arm_cos_q15.c
+    
+    
+      $PROJ_DIR$\..\FastMathFunctions\arm_cos_q31.c
+    
+    
+      $PROJ_DIR$\..\FastMathFunctions\arm_sin_f32.c
+    
+    
+      $PROJ_DIR$\..\FastMathFunctions\arm_sin_q15.c
+    
+    
+      $PROJ_DIR$\..\FastMathFunctions\arm_sin_q31.c
+    
+    
+      $PROJ_DIR$\..\FastMathFunctions\arm_sqrt_q15.c
+    
+    
+      $PROJ_DIR$\..\FastMathFunctions\arm_sqrt_q31.c
+    
+  
+  
+    FilteringFunctions
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_biquad_cascade_df1_32x64_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_biquad_cascade_df1_32x64_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_biquad_cascade_df1_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_biquad_cascade_df1_fast_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_biquad_cascade_df1_fast_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_biquad_cascade_df1_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_biquad_cascade_df1_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_biquad_cascade_df1_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_biquad_cascade_df1_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_biquad_cascade_df1_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_biquad_cascade_df2T_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_biquad_cascade_df2T_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_conv_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_conv_fast_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_conv_fast_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_conv_partial_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_conv_partial_fast_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_conv_partial_fast_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_conv_partial_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_conv_partial_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_conv_partial_q7.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_conv_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_conv_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_conv_q7.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_correlate_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_correlate_fast_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_correlate_fast_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_correlate_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_correlate_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_correlate_q7.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_decimate_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_decimate_fast_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_decimate_fast_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_decimate_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_decimate_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_decimate_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_decimate_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_decimate_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_fast_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_fast_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_init_q7.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_interpolate_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_interpolate_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_interpolate_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_interpolate_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_interpolate_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_interpolate_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_lattice_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_lattice_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_lattice_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_lattice_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_lattice_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_lattice_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_q7.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_init_q7.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_q7.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_iir_lattice_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_iir_lattice_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_iir_lattice_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_iir_lattice_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_iir_lattice_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_iir_lattice_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_norm_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_norm_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_norm_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_norm_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_norm_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_norm_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_q31.c
+    
+  
+  
+    MatrixFunctions
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_add_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_add_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_add_q31.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_init_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_init_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_init_q31.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_inverse_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_mult_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_mult_fast_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_mult_fast_q31.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_mult_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_mult_q31.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_scale_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_scale_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_scale_q31.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_sub_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_sub_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_sub_q31.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_trans_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_trans_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_trans_q31.c
+    
+  
+  
+    StatisticsFunctions
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_max_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_max_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_max_q31.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_max_q7.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_mean_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_mean_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_mean_q31.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_mean_q7.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_min_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_min_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_min_q31.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_min_q7.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_power_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_power_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_power_q31.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_power_q7.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_rms_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_rms_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_rms_q31.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_std_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_std_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_std_q31.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_var_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_var_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_var_q31.c
+    
+  
+  
+    SupportFunctions
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_copy_f32.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_copy_q15.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_copy_q31.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_copy_q7.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_fill_f32.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_fill_q15.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_fill_q31.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_fill_q7.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_float_to_q15.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_float_to_q31.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_float_to_q7.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q15_to_float.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q15_to_q31.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q15_to_q7.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q31_to_float.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q31_to_q15.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q31_to_q7.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q7_to_float.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q7_to_q15.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q7_to_q31.c
+    
+  
+  
+    TransformFunctions
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_cfft_radix4_f32.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_cfft_radix4_init_f32.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_cfft_radix4_init_q15.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_cfft_radix4_init_q31.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_cfft_radix4_q15.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_cfft_radix4_q31.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_dct4_f32.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_dct4_init_f32.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_dct4_init_q15.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_dct4_init_q31.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_dct4_q15.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_dct4_q31.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_rfft_f32.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_rfft_init_f32.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_rfft_init_q15.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_rfft_init_q31.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_rfft_q15.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_rfft_q31.c
+    
+  
+
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM4_math.ewp b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM4_math.ewp
new file mode 100644
index 0000000..0a61689
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM4_math.ewp
@@ -0,0 +1,4393 @@
+
+
+
+  2
+  
+    Debug LE without FPU
+    
+      ARM
+    
+    1
+    
+      General
+      3
+      
+        21
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ICCARM
+      2
+      
+        28
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      AARM
+      2
+      
+        8
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
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+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_decimate_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_decimate_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_fast_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_fast_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_init_q7.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_interpolate_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_interpolate_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_interpolate_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_interpolate_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_interpolate_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_interpolate_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_lattice_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_lattice_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_lattice_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_lattice_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_lattice_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_lattice_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_q7.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_init_q7.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_fir_sparse_q7.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_iir_lattice_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_iir_lattice_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_iir_lattice_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_iir_lattice_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_iir_lattice_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_iir_lattice_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_norm_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_norm_init_f32.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_norm_init_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_norm_init_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_norm_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_norm_q31.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_q15.c
+    
+    
+      $PROJ_DIR$\..\FilteringFunctions\arm_lms_q31.c
+    
+  
+  
+    MatrixFunctions
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_add_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_add_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_add_q31.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_init_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_init_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_init_q31.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_inverse_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_mult_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_mult_fast_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_mult_fast_q31.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_mult_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_mult_q31.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_scale_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_scale_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_scale_q31.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_sub_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_sub_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_sub_q31.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_trans_f32.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_trans_q15.c
+    
+    
+      $PROJ_DIR$\..\MatrixFunctions\arm_mat_trans_q31.c
+    
+  
+  
+    StatisticsFunctions
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_max_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_max_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_max_q31.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_max_q7.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_mean_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_mean_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_mean_q31.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_mean_q7.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_min_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_min_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_min_q31.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_min_q7.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_power_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_power_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_power_q31.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_power_q7.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_rms_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_rms_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_rms_q31.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_std_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_std_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_std_q31.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_var_f32.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_var_q15.c
+    
+    
+      $PROJ_DIR$\..\StatisticsFunctions\arm_var_q31.c
+    
+  
+  
+    SupportFunctions
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_copy_f32.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_copy_q15.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_copy_q31.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_copy_q7.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_fill_f32.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_fill_q15.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_fill_q31.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_fill_q7.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_float_to_q15.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_float_to_q31.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_float_to_q7.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q15_to_float.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q15_to_q31.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q15_to_q7.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q31_to_float.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q31_to_q15.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q31_to_q7.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q7_to_float.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q7_to_q15.c
+    
+    
+      $PROJ_DIR$\..\SupportFunctions\arm_q7_to_q31.c
+    
+  
+  
+    TransformFunctions
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_cfft_radix4_f32.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_cfft_radix4_init_f32.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_cfft_radix4_init_q15.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_cfft_radix4_init_q31.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_cfft_radix4_q15.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_cfft_radix4_q31.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_dct4_f32.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_dct4_init_f32.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_dct4_init_q15.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_dct4_init_q31.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_dct4_q15.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_dct4_q31.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_rfft_f32.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_rfft_init_f32.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_rfft_init_q15.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_rfft_init_q31.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_rfft_q15.c
+    
+    
+      $PROJ_DIR$\..\TransformFunctions\arm_rfft_q31.c
+    
+  
+
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM_math.eww b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM_math.eww
new file mode 100644
index 0000000..0442a7e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/DSP_Lib/Source/iar/iar_cortexM_math.eww
@@ -0,0 +1,18 @@
+
+
+
+  
+    $WS_DIR$\iar_cortexM0_math.ewp
+  
+  
+    $WS_DIR$\iar_cortexM3_math.ewp
+  
+  
+    $WS_DIR$\iar_cortexM4_math.ewp
+  
+  
+    $WS_DIR$\iar_cortexM4F_math.ewp
+  
+
+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd
new file mode 100644
index 0000000..4f9aef6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd
@@ -0,0 +1,257 @@
+
+
+  
+  
+    
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+    
+  
+
+  
+    
+      
+    
+  
+
+  
+    
+      
+      
+      
+        
+          
+            
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+      
+      
+        
+          
+            
+            
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+      
+    
+  
+
+  
+    
+      
+      
+      
+      
+    
+  
+
+  
+    
+      
+      
+    
+  
+
+  
+    
+      
+         
+     
+  
+
+  
+    
+      
+      
+      
+    
+  
+
+  
+    
+      
+        
+        
+        
+        
+        
+        
+        
+          
+            
+              
+                
+                  
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                    
+                      
+                        
+                          
+                            
+                              
+                                
+                                 
+                                
+                                
+                                
+                                
+                                
+                                
+                                
+                                
+                                
+                                  
+                                    
+                                      
+                                      
+                                        
+                                          
+                                          
+                                          
+                                            
+                                            
+                                            
+                                          
+                                          
+                                          
+                                          
+                                          
+                                          
+                                            
+                                              
+                                                
+                                                
+                                                
+                                                  
+                                                    
+                                                      
+                                                      
+                                                      
+                                                        
+                                                        
+                                                      
+                                                    
+                                                  
+                                                
+                                              
+                                              
+                                            
+                                          
+                                        
+                                        
+                                      
+                                    
+                                    
+                                  
+                                
+                              
+                              
+                            
+                          
+                        
+                      
+                    
+                  
+                  
+                
+              
+            
+          
+        
+        
+          
+            
+              
+              
+            
+          
+        
+      
+      
+    
+  
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_CM4_SIMD.htm b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_CM4_SIMD.htm
new file mode 100644
index 0000000..243f377
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_CM4_SIMD.htm
@@ -0,0 +1,3809 @@
+
+
+  
+  CMSIS: Cortex-M4 SIMD Instructions
+  
+  
+
+
+
+
+
CMSIS Support for Cortex-M4 SIMD Instructions

+
+
This file describes the Cortex-M4 SIMD instructions supported by CMSIS.

+
Version: 1.00 - 25. November 2010

+
+
Information in this file, the accompany manuals, and software is

+                 Copyright © ARM Ltd.
All rights reserved.
+

+
+

+
+
Revision History

+
    
+	
  • Revision 0.01 - January 2010: Initial version
    • 
+	
  • Revision 0.02 - June 2010: added __QADD, __QSUB
    • 
+	
  • Revision 1.00 - November 2010: 
    • 
+

+
+

+
+
Contents

+
+
    
+  
  1. About
    2. 
+  
  2. Cortex-M4 SIMD instruction support
    3. 
+  
  3. Examples
    4. 
+

+
+
+
+
 

+
About

+

+  CMSIS provides for the Cortex-M4 a set of functions supporting Cortex-M4 SIMD instructions.
+

+
+
 

+
Cortex-M4 SIMD instruction support

+
CMSIS supports the following functions for Cortex-M4 instructions:
+

+
+
+  
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+
NameMnemonicDescription
__SADD8SADD8GE setting quad 8-bit signed addition
__QADD8QADD8Q setting quad 8-bit saturating addition
__SHADD8SHADD8Quad 8-bit signed addition with halved results
__UADD8UADD8GE setting quad 8-bit unsigned addition
__UQADD8UQADD8Quad 8-bit unsigned saturating addition
__UHADD8UHADD8Quad 8-bit unsigned addition with halved results
__SSUB8SSUB8GE setting quad 8-bit signed subtraction
__QSUB8QSUB8Q setting quad 8-bit saturating subtract
__SHSUB8SHSUB8Quad 8-bit signed subtraction with halved results
__USUB8USUB8GE setting quad 8-bit unsigned subtract
__UQSUB8UQSUB8Quad 8-bit unsigned saturating subtraction
__UHSUB8UHSUB8Quad 8-bit unsigned subtraction with halved results
__SADD16SADD16GE setting dual 16-bit signed addition
__QADD16QADD16Q setting dual 16-bit saturating addition
__SHADD16SHADD16Dual 16-bit signed addition with halved results
__UADD16UADD16GE setting dual 16-bit unsigned addition
__UQADD16UQADD16Dual 16-bit unsigned saturating addition
__UHADD16UHADD16Dual 16-bit unsigned addition with halved results
__SSUB16SSUB16GE setting dual 16-bit signed subtraction
__QSUB16QSUB16Q setting dual 16-bit saturating subtract
__SHSUB16SHSUB16Dual 16-bit signed subtraction with halved results
__USUB16USUB16GE setting dual 16-bit unsigned subtract
__UQSUB16UQSUB16Dual 16-bit unsigned saturating subtraction
__UHSUB16UHSUB16Dual 16-bit unsigned subtraction with halved results
__SASXSASXGE setting dual 16-bit addition and subtraction with exchange
__QASXQASXQ setting dual 16-bit add and subtract with exchange
__SHASXSHASXDual 16-bit signed addition and subtraction with halved results
__UASXUASXGE setting dual 16-bit unsigned addition and subtraction with exchange
__UQASXUQASXDual 16-bit unsigned saturating addition and subtraction with exchange
__UHASXUHASXDual 16-bit unsigned addition and subtraction with halved results and exchange
__SSAXSSAXGE setting dual 16-bit signed subtraction and addition with exchange
__QSAXQSAXQ setting dual 16-bit subtract and add with exchange
__SHSAXSHSAXDual 16-bit signed subtraction and addition with halved results
__USAXUSAXGE setting dual 16-bit unsigned subtract and add with exchange
__UQSAXUQSAXDual 16-bit unsigned saturating subtraction and addition with exchange
__UHSAXUHSAXDual 16-bit unsigned subtraction and addition with halved results and exchange
__USAD8USAD8Unsigned sum of quad 8-bit unsigned absolute difference
__USADA8USADA8Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate
__SSAT16SSAT16Q setting dual 16-bit saturate
__USAT16USAT16Q setting dual 16-bit unsigned saturate
__UXTB16UXTB16Dual extract 8-bits and zero-extend to 16-bits
__UXTAB16UXTAB16Extracted 16-bit to 32-bit unsigned addition
__SXTB16SXTB16Dual extract 8-bits and sign extend each to 16-bits
__SXTAB16SXTAB16Dual extracted 8-bit to 16-bit signed addition
__SMUADSMUADQ setting sum of dual 16-bit signed multiply
__SMUADXSMUADXQ setting sum of dual 16-bit signed multiply with exchange
__SMLADSMLADQ setting dual 16-bit signed multiply with single 32-bit accumulator
__SMLADXSMLADXQ setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator
__SMLALDSMLALDDual 16-bit signed multiply with single 64-bit accumulator
__SMLALDXSMLALDXDual 16-bit signed multiply with exchange with single 64-bit accumulator
__SMUSDSMUSDDual 16-bit signed multiply returning difference
__SMUSDXSMUSDXDual 16-bit signed multiply with exchange returning difference
__SMLSDSMLSDQ setting dual 16-bit signed multiply subtract with 32-bit accumulate
__SMLSDXSMLSDXQ setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate
__SMLSLDSMLSLDQ setting dual 16-bit signed multiply subtract with 64-bit accumulate
__SMLSLDXSMLSLDXQ setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate
__SELSELSelect bytes based on GE bits
__QADDQADDQ setting saturating add
__QSUBQSUB/td>
+      Q setting saturating subtract

+
+
+
+
+
Function __SADD8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four 8-bit signed integer additions.

+          The GE bits in the APSR are set according to the results of the additions.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit summands.
    • 
+          
  • val2: second four 8-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the first bytes from each operand, in the first byte of the return value.
    • 
+            
  • the addition of the second bytes of each operand, in the second byte of the return value.
    • 
+            
  • the addition of the third bytes of each operand, in the third byte of the return value.
    • 
+            
  • the addition of the fourth bytes of each operand, in the fourth byte of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[7:0] ≥ 0 then APSR.GE[0] = 1 else 0
    • 
+            
  • if res[15:8] ≥ 0 then APSR.GE[1] = 1 else 0
    • 
+            
  • if res[23:16] ≥ 0 then APSR.GE[2] = 1 else 0
    • 
+            
  • if res[31:24] ≥ 0 then APSR.GE[3] = 1 else 0
    • 
+         
      
+      
Operation
+        
+res[7:0]   = val1[7:0]   + val2[7:0]
+res[15:8]  = val1[15:8]  + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]

+      

+
+
Function __QADD8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __QADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four 8-bit integer additions, saturating the results to 
+          the 8-bit signed integer range -27 ≤ x ≤ 27 - 1.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit summands.
    • 
+          
  • val2: second four 8-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the saturated addition of the first byte of each operand in the first byte of the return value.
    • 
+            
  • the saturated addition of the second byte of each operand in the second byte of the return value.
    • 
+            
  • the saturated addition of the third byte of each operand in the third byte of the return value.
    • 
+            
  • the saturated addition of the fourth byte of each operand in the fourth byte of the return value.
    • 
+          

+          
The returned results are saturated to the 16-bit signed integer range -27 ≤ x ≤ 27 - 1.
+          

+      
Operation
+        
+res[7:0]   = val1[7:0]   + val2[7:0]
+res[15:8]  = val1[15:8]  + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]

+      

+
+
Function __SHADD8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SHADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four signed 8-bit integer additions, halving the results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit summands.
    • 
+          
  • val2: second four 8-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved addition of the first bytes from each operand, in the first byte of the return value.
    • 
+            
  • the halved addition of the second bytes from each operand, in the second byte of the return value.
    • 
+            
  • the halved addition fo the third bytes from each operand, in the third byte of the return value.
    • 
+            
  • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
    • 
+          

+      
Operation
+        
+res[7:0]   = (val1[7:0]   + val2[7:0])   >> 1
+res[15:8]  = (val1[15:8]  + val2[15:8])  >> 1
+res[23:16] = (val1[23:16] + val2[23:16]) >> 1
+res[31:24] = (val1[31:24] + val2[31:24]) >> 1

+      

+
+
Function __UADD8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four unsigned 8-bit integer additions.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit summands for each addition.
    • 
+          
  • val2: second four 8-bit summands for each addition.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the first bytes in each operand, in the first byte of the return value.
    • 
+            
  • the addition of the second bytes in each operand, in the second byte of the return value.
    • 
+            
  • the addition of the third bytes in each operand, in the third byte of the return value.
    • 
+            
  • the addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[7:0] ≥ 0x100 then APSR.GE[0] = 1 else 0
    • 
+            
  • if res[15:8] ≥ 0x100 then APSR.GE[1] = 1 else 0
    • 
+            
  • if res[23:16] ≥ 0x100 then APSR.GE[2] = 1 else 0
    • 
+            
  • if res[31:24] ≥ 0x100 then APSR.GE[3] = 1 else 0
    • 
+         
      
+      
Operation
+        
+res[7:0]   = val1[7:0]   + val2[7:0]
+res[15:8]  = val1[15:8]  + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]

+      

+
+
Function __UQADD8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UQADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four unsigned 8-bit integer additions, saturating the 
+          results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 - 1.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit summands.
    • 
+          
  • val2: second four 8-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the first bytes in each operand, in the first byte of the return value.
    • 
+            
  • the addition of the second bytes in each operand, in the second byte of the return value.
    • 
+            
  • the addition of the third bytes in each operand, in the third byte of the return value.
    • 
+            
  • the addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • 
+          

+          
The results are saturated to the 8-bit unsigned integer range 0 ≤ x ≤ 28 - 1.
+          

+      
Operation
+        
+res[7:0]   = val1[7:0]   + val2[7:0]
+res[15:8]  = val1[15:8]  + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]

+      

+
+
Function __UHADD8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UHADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four unsigned 8-bit integer additions, halving the results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit summands.
    • 
+          
  • val2: second four 8-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved addition of the first bytes in each operand, in the first byte of the return value.
    • 
+            
  • the halved addition of the second bytes in each operand, in the second byte of the return value.
    • 
+            
  • the halved addition of the third bytes in each operand, in the third byte of the return value.
    • 
+            
  • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • 
+          

+      
Operation
+        
+res[7:0]   = (val1[7:0]   + val2[7:0])   >> 1
+res[15:8]  = (val1[15:8]  + val2[15:8])  >> 1
+res[23:16] = (val1[23:16] + val2[23:16]) >> 1
+res[31:24] = (val1[31:24] + val2[31:24]) >> 1

+      

+
+
Function __SSUB8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SSUB8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four 8-bit signed integer subtractions.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands of each subtraction.
    • 
+          
  • val2: second four 8-bit operands of each subtraction.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the first byte in the second operand from the first byte in the 
+                first operand, in the first bytes of the return value.
    • 
+            
  • the subtraction of the second byte in the second operand from the second byte in 
+                the first operand, in the second byte of the return value.
    • 
+            
  • the subtraction of the third byte in the second operand from the third byte in the 
+                first operand, in the third byte of the return value.
    • 
+            
  • the subtraction of the fourth byte in the second operand from the fourth byte in 
+                the first operand, in the fourth byte of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation. If res is the return value, then:
+          

+          
    
+            
  • if res[8:0] ≥ 0 then APSR.GE[0] = 1 else 0
    • 
+            
  • if res[15:8] ≥ 0 then APSR.GE[1] = 1 else 0
    • 
+            
  • if res[23:16] ≥ 0 then APSR.GE[2] = 1 else 0
    • 
+            
  • if res[31:24] ≥ 0 then APSR.GE[3] = 1 else 0
    • 
+         
      
+      
Operation
+        
+res[7:0]   = val1[7:0]   - val2[7:0]
+res[15:8]  = val1[15:8]  - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]

+      

+
+
Function __QSUB8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __QADD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four 8-bit integer subtractions, saturating the results 
+          to the 8-bit signed integer range -27 ≤ x ≤ 27 - 1.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands.
    • 
+          
  • val2: second four 8-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the first byte in the second operand from the first byte in the 
+                first operand, in the first byte of the return value.
    • 
+            
  • the subtraction of the second byte in the second operand from the second byte in 
+                the first operand, in the second byte of the return value.
    • 
+            
  • the subtraction of the third byte in the second operand from the third byte in the 
+                first operand, in the third byte of the return value.
    • 
+            
  • the subtraction of the fourth byte in the second operand from the fourth byte in 
+                the first operand, in the fourth byte of the return value.
    • 
+          

+          
The returned results are saturated to the 8-bit signed integer range -27 ≤ x ≤ 27 - 1.
+          

+      
Operation
+        
+res[7:0]   = val1[7:0]   - val2[7:0]
+res[15:8]  = val1[15:8]  - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]

+      

+
+
Function __SHSUB8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SHSUB8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four signed 8-bit integer subtractions, halving the 
+          results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands.
    • 
+          
  • val2: second four 8-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved subtraction of the first byte in the second operand from the first byte 
+                in the first operand, in the first byte of the return value.
    • 
+            
  • the halved subtraction of the second byte in the second operand from the second 
+                byte in the first operand, in the second byte of the return value.
    • 
+            
  • the halved subtraction of the third byte in the second operand from the third byte 
+                in the first operand, in the third byte of the return value.
    • 
+            
  • the halved subtraction of the fourth byte in the second operand from the fourth 
+                byte in the first operand, in the fourth byte of the return value.
    • 
+          

+      
Operation
+        
+res[7:0]   = (val1[7:0]   - val2[7:0])  >> 1
+res[15:8]  = (val1[15:8]  - val2[15:8]) >> 1
+res[23:16] = (val1[23:16] - val2[23:16] >> 1
+res[31:24] = (val1[31:24] - val2[31:24] >> 1

+      

+
+
Function __USUB8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __USUB8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function It enables you to perform four 8-bit unsigned integer subtractions.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands.
    • 
+          
  • val2: second four 8-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the first byte in the second operand from the first byte in the 
+                first operand, in the first byte of the return value.
    • 
+            
  • the subtraction of the second byte in the second operand from the second byte in 
+                the first operand, in the second byte of the return value.
    • 
+            
  • the subtraction of the third byte in the second operand from the third byte in the 
+                first operand, in the third byte of the return value.
    • 
+            
  • the subtraction of the fourth byte in the second operand from the fourth byte in 
+                the first operand, in the fourth byte of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[7:0] ≥ 0 then APSR.GE[0] = 1 else 0
    • 
+            
  • if res[15:8] ≥ 0 then APSR.GE[1] = 1 else 0
    • 
+            
  • if res[23:16] ≥ 0 then APSR.GE[2] = 1 else 0
    • 
+            
  • if res[31:24] ≥ 0 then APSR.GE[3] = 1 else 0
    • 
+         
      
+      
Operation
+        
+res[7:0]   = val1[7:0]   - val2[7:0]
+res[15:8]  = val1[15:8]  - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]

+      

+
+
Function __UQSUB8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UQSUB8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four unsigned 8-bit integer subtractions, saturating 
+          the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 - 1.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands.
    • 
+          
  • val2: second four 8-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the first byte in the second operand from the first byte in the 
+                first operand, in the first byte of the return value.
    • 
+            
  • the subtraction of the second byte in the second operand from the second byte in 
+                the first operand, in the second byte of the return value.
    • 
+            
  • the subtraction of the third byte in the second operand from the third byte in the 
+                first operand, in the third byte of the return value.
    • 
+            
  • the subtraction of the fourth byte in the second operand from the fourth byte in 
+                the first operand, in the fourth byte of the return value.
    • 
+          

+          
The results are saturated to the 8-bit unsigned integer range 0 ≤ x ≤ 28 - 1.
+          

+      
Operation
+        
+res[7:0]   = val1[7:0]   - val2[7:0]
+res[15:8]  = val1[15:8]  - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]

+      

+
+
Function __UHSUB8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UHSUB8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four unsigned 8-bit integer subtractions, halving the 
+          results.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands.
    • 
+          
  • val2: second four 8-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved subtraction of the first byte in the second operand from the first byte 
+                in the first operand, in the first byte of the return value.
    • 
+            
  • the halved subtraction of the second byte in the second operand from the second 
+                byte in the first operand, in the second byte of the return value.
    • 
+            
  • the halved subtraction of the third byte in the second operand from the third byte 
+                in the first operand, in the third byte of the return value.
    • 
+            
  • the halved subtraction of the fourth byte in the second operand from the fourth 
+                byte in the first operand, in the fourth byte of the return value.
    • 
+          

+      
Operation
+        
+res[7:0]   = (val1[7:0]   - val2[7:0])   >> 1
+res[15:8]  = (val1[15:8]  - val2[15:8])  >> 1
+res[23:16] = (val1[23:16] - val2[23:16]) >> 1
+res[31:24] = (val1[31:24] - val2[31:24]) >> 1

+      

+
+
Function __SADD16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SADD16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit signed integer additions.

+          The GE bits in the APSR are set according to the results of the additions.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit summands.
    • 
+          
  • val2: second two 16-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the low halfwords in the low halfword of the return value.
    • 
+            
  • the addition of the high halfwords in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[15:0]
+res[31:16] = val1[31:16] + val2[31:16]

+      

+
+
Function __QADD16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __QADD16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit integer arithmetic additions in parallel, 
+          saturating the results to the 16-bit signed integer range -215 ≤ x ≤ 215 - 1.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit summands.
    • 
+          
  • val2: second two 16-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the saturated addition of the low halfwords in the low halfword of the return value.
    • 
+            
  • the saturated addition of the high halfwords in the high halfword of the return value.
    • 
+          

+          
The returned results are saturated to the 16-bit signed integer 
+             range -215 ≤ x ≤ 215 - 1
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[15:0]
+res[16:31] = val1[31:16] + val2[31:16]

+      

+
+
Function __SHADD16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SHADD16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two signed 16-bit integer additions, halving the 
+          results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit summands.
    • 
+          
  • val2: second two 16-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved addition of the low halfwords from each operand, in the low halfword 
+                of the return value.
    • 
+            
  • the halved addition of the high halfwords from each operand, in the high halfword 
+                of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  + val2[15:0])  >> 1
+res[31:16] = (val1[31:16] + val2[31:16]) >> 1

+      

+
+
Function __UADD16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UADD16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit unsigned integer additions.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit summands for each addition.
    • 
+          
  • val2: second two 16-bit summands for each addition.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the low halfwords in each operand, in the low halfword of the 
+                return value.
    • 
+            
  • the addition of the high halfwords in each operand, in the high halfword of the 
+                return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0x10000 then APSR.GE[0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0x10000 then APSR.GE[1] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[15:0]
+res[31:16] = val1[31:16] + val2[31:16]

+      

+
+
Function __UQADD16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UQADD16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two unsigned 16-bit integer additions, saturating the 
+          results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit summands.
    • 
+          
  • val2: second two 16-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the low halfword in the first operand and the low halfword in the 
+                second operand, in the low halfword of the return value.
    • 
+            
  • the addition of the high halfword in the first operand and the high halfword in the 
+                second operand, in the high halfword of the return value.
    • 
+          

+          
The results are saturated to the 16-bit unsigned integer 
+             range 0 ≤ x ≤ 216 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[15:0]
+res[31:16] = val1[31:16] + val2[31:16]

+      

+
+
Function __UHADD16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UHADD16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two unsigned 16-bit integer additions, halving the 
+          results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit summands.
    • 
+          
  • val2: second two 16-bit summands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved addition of the low halfwords in each operand, in the low halfword of 
+                the return value.
    • 
+            
  • the halved addition of the high halfwords in each operand, in the high halfword 
+                of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  + val2[15:0])  >> 1
+res[31:16] = (val1[31:16] + val2[31:16]) >> 1

+      

+
+
Function __SSUB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SSUB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit signed integer subtractions.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands of each subtraction.
    • 
+          
  • val2: second two 16-bit operands of each subtraction.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the low halfword in the second operand from the low halfword 
+                in the first operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the high halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]

+      

+
+
Function __QSUB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __QSUB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit integer subtractions, saturating the 
+          results to the 16-bit signed integer range -215 ≤ x ≤ 215 - 1.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands.
    • 
+          
  • val2: second two 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the saturated subtraction of the low halfword in the second operand from the low 
+                halfword in the first operand, in the low halfword of the returned result.
    • 
+            
  • the saturated subtraction of the high halfword in the second operand from the high 
+                halfword in the first operand, in the high halfword of the returned result.
    • 
+          

+          
The returned results are saturated to the 16-bit signed integer 
+             range -215 ≤ x ≤ 215 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]

+      

+
+
Function __SHSUB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SHSUB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two signed 16-bit integer subtractions, halving the 
+          results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands.
    • 
+          
  • val2: second two 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved subtraction of the low halfword in the second operand from the low 
+                halfword in the first operand, in the low halfword of the return value.
    • 
+            
  • the halved subtraction of the high halfword in the second operand from the high 
+                halfword in the first operand, in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  - val2[15:0])  >> 1
+res[31:16] = (val1[31:16] - val2[31:16]) >> 1

+      

+
+
Function __USUB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __USUB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit unsigned integer subtractions.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands.
    • 
+          
  • val2: second two 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the low halfword in the second operand from the low halfword 
+                in the first operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the high halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]

+      

+
+
Function __UQSUB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UQSUB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two unsigned 16-bit integer subtractions, saturating 
+          the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands for each subtraction.
    • 
+          
  • val2: second two 16-bit operands for each subtraction.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the low halfword in the second operand from the low halfword 
+                in the first operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the high halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
The results are saturated to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]

+      

+
+
Function __UHSUB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UHSUB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two unsigned 16-bit integer subtractions, halving 
+          the results.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands.
    • 
+          
  • val2: second two 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved subtraction of the low halfword in the second operand from the low 
+                halfword in the first operand, in the low halfword of the return value.
    • 
+            
  • the halved subtraction of the high halfword in the second operand from the high 
+                halfword in the first operand, in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  - val2[15:0])  >> 1
+res[31:16] = (val1[31:16] - val2[31:16]) >> 1

+      

+
+
Function __SASX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SASX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function inserts an SASX instruction into the instruction stream generated by the 
+          compiler. It enables you to exchange the halfwords of the second operand, add the high 
+          halfwords and subtract the low halfwords.

+          The GE bits in the APRS are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first operand for the subtraction in the low halfword, and the
+              first operand for the addition in the high halfword.
    • 
+          
  • val2: second operand for the subtraction in the high halfword, and the 
+              second operand for the addition in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the high halfword in the second operand from the low halfword 
+                in the first operand, in the low halfword of the return value.
    • 
+            
  • the addition of the high halfword in the first operand and the low halfword in the 
+                second operand, in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0] - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]

+      

+
+
Function __QASX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __QASX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of the one operand, then add the high
+          halfwords and subtract the low halfwords, saturating the results to the 16-bit signed 
+          integer range -215 ≤ x ≤ 215 - 1.
+      
Parameter
+        
    
+          
  • val1: first operand for the subtraction in the low halfword, and the 
+                       first operand for the addition in the high halfword.
    • 
+          
  • val2: second operand for the subtraction in the high halfword, and the
+                       second operand for the addition in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the saturated subtraction of the high halfword in the second operand from the low 
+                halfword in the first operand, in the low halfword of the return value.
    • 
+            
  • the saturated addition of the high halfword in the first operand and the low 
+                halfword in the second operand, in the high halfword of the return value.
    • 
+          

+          
The returned results are saturated to the 16-bit signed integer 
+             range -215 ≤ x ≤ 215 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]

+      

+
+
Function __SHASX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SHASX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the two halfwords of one operand, perform one 
+          signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands.
    • 
+          
  • val2: second 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved subtraction of the high halfword in the second operand from the low 
+                halfword in the first operand, in the low halfword of the return value.
    • 
+            
  • the halved subtraction of the low halfword in the second operand from the high 
+                halfword in the first operand, in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1
+res[31:16] = (val1[31:16] - val2[15:0])  >> 1

+      

+
+
Function __UASX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UASX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the two halfwords of the second operand, add the 
+          high halfwords and subtract the low halfwords.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first operand for the subtraction in the low halfword, and the
+              first operand for the addition in the high halfword.
    • 
+          
  • val2: second operand for the subtraction in the high halfword and the
+              second operand for the addition in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the high halfword in the second operand from the low halfword 
+                in the first operand, in the low halfword of the return value.
    • 
+            
  • the addition of the high halfword in the first operand and the low halfword in the 
+                second operand, in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0x10000 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]

+      

+
+
Function __UQASX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UQASX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand and perform 
+          one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the 
+          results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1.
+      
Parameter
+        
    
+          
  • val1: first two 16-bit operands.
    • 
+          
  • val2: second two 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the subtraction of the high halfword in the second operand from the low halfword 
+                in the first operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the low halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
The results are saturated to the 16-bit unsigned integer  
+             range 0 ≤ x ≤ 216 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]

+      

+
+
Function __UHASX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UHASX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand, add the high 
+          halfwords and subtract the low halfwords, halving the results.
+      
Parameter
+        
    
+          
  • val1: first operand for the subtraction in the low halfword, and the
+           first operand for the addition in the high halfword.
    • 
+          
  • val2: second operand for the subtraction in the high halfword, and the 
+           second operand for the addition in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved subtraction of the high halfword in the second operand from the low 
+                halfword in the first operand.
    • 
+            
  • the halved addition of the high halfword in the first operand and the low halfword 
+                in the second operand.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1
+res[31:16] = (val1[31:16] + val2[15:0])  >> 1

+      

+
+
Function __SSAX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SSAX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the two halfwords of one operand and perform one 
+          16-bit integer subtraction and one 16-bit addition.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first operand for the addition in the low halfword, and the first 
+              operand for the subtraction in the high halfword.
    • 
+          
  • val2: second operand for the addition in the high halfword, and the
+              second operand for the subtraction in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the low halfword in the first operand and the high halfword in the 
+                second operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the low halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]

+      

+
+
Function __QSAX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __QSAX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of one operand, then subtract the 
+          high halfwords and add the low halfwords, saturating the results to the 16-bit signed 
+          integer range -215 ≤ x ≤ 215 - 1.
+      
Parameter
+        
    
+          
  • val1: first operand for the addition in the low halfword, and the first
+           operand for the subtraction in the high halfword.
    • 
+          
  • val2: second operand for the addition in the high halfword, and the 
+           second operand for the subtraction in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the saturated addition of the low halfword of the first operand and the high 
+                halfword of the second operand, in the low halfword of the return value.
    • 
+            
  • the saturated subtraction of the low halfword of the second operand from the high 
+                halfword of the first operand, in the high halfword of the return value.
    • 
+          

+          
The returned results are saturated to the 16-bit signed integer 
+             range -215 ≤ x ≤ 215 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]

+      

+
+
Function __SHSAX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SHSAX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the two halfwords of one operand, perform one 
+          signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands.
    • 
+          
  • val2: second 16-bit operands.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved addition of the low halfword in the first operand and the high halfword 
+                in the second operand, in the low halfword of the return value.
    • 
+            
  • the halved subtraction of the low halfword in the second operand from the high 
+                halfword in the first operand, in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1
+res[31:16] = (val1[31:16] - val2[15:0])  >> 1

+      

+
+
Function __USAX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __USAX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand, subtract the 
+          high halfwords and add the low halfwords.

+          The GE bits in the APSR are set according to the results.
+      
Parameter
+        
    
+          
  • val1: first operand for the addition in the low halfword, and the first
+              operand for the subtraction in the high halfword.
    • 
+          
  • val2: second operand for the addition in the high halfword, and the
+              second operand for the subtraction in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the low halfword in the first operand and the high halfword in the 
+                second operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the low halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
+             the results of the operation.

+             If res is the return value, then:
+          

+          
    
+            
  • if res[15:0] ≥ 0x10000 then APSR.GE[1:0] = 11 else 00
    • 
+            
  • if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00
    • 
+         
      
+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]

+      

+
+
Function __UQSAX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UQSAX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand and perform 
+          one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the 
+          results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 - 1.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operand for the addition in the low halfword, and the
+              first 16-bit operand for the subtraction in the high halfword.
    • 
+          
  • val2: second 16-bit halfword for the addition in the high halfword,
+              and the second 16-bit halfword for the subtraction in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the addition of the low halfword in the first operand and the high halfword in the 
+                second operand, in the low halfword of the return value.
    • 
+            
  • the subtraction of the low halfword in the second operand from the high halfword 
+                in the first operand, in the high halfword of the return value.
    • 
+          

+          
The results are saturated to the 16-bit unsigned integer 
+             range 0 ≤ x ≤ 216 - 1.
+          

+      
Operation
+        
+res[15:0]  = val1[15:0]  + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]

+      

+
+
Function __UHSAX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UHSAX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand, subtract the 
+          high halfwords and add the low halfwords, halving the results.
+      
Parameter
+        
    
+          
  • val1: first operand for the addition in the low halfword, and the first
+              operand for the subtraction in the high halfword.
    • 
+          
  • val2: second operand for the addition in the high halfword, and the
+              second operand for the subtraction in the low halfword.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the halved addition of the high halfword in the second operand and the low 
+                halfword in the first operand, in the low halfword of the return value.
    • 
+            
  • the halved subtraction of the low halfword in the second operand from the high 
+                halfword in the first operand, in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1
+res[31:16] = (val1[31:16] - val2[15:0])  >> 1

+      

+
+
Function __USAD8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __USAD8(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform four unsigned 8-bit subtractions, and add the 
+          absolute values of the differences together, returning the result as a single unsigned 
+          integer.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands for the subtractions.
    • 
+          
  • val2: second four 8-bit operands for the subtractions.
    • 
+        

+      
Return Value
+         
The function returns the sum of the absolute differences of:

+         
    
+            
  • the subtraction of the first byte in the second operand from the first byte in the 
+                first operand.
    • 
+            
  • the subtraction of the second byte in the second operand from the second byte in 
+                the first operand.
    • 
+            
  • the subtraction of the third byte in the second operand from the third byte in the 
+                first operand.
    • 
+            
  • the subtraction of the fourth byte in the second operand from the fourth byte in 
+                the first operand.
    • 
+          

+          
The sum is returned as a single unsigned integer.

+      
Operation
+        
+absdiff1  = val1[7:0]   - val2[7:0]
+absdiff2  = val1[15:8]  - val2[15:8]
+absdiff3  = val1[23:16] - val2[23:16]
+absdiff4  = val1[31:24] - val2[31:24]
+res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4

+      

+
+
Function __USADA8

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __USADA8(uint32_t val1, uint32_t val2, uint32_t val3);

+      
DescriptionThis function enables you to perform four unsigned 8-bit subtractions, and add the 
+          absolute values of the differences to a 32-bit accumulate operand.
+      
Parameter
+        
    
+          
  • val1: first four 8-bit operands for the subtractions.
    • 
+          
  • val2: second four 8-bit operands for the subtractions.
    • 
+          
  • val3: accumulation value.
    • 
+        

+      
Return Value
+         
The function returns the sum of the absolute differences of the following 
+            bytes, added to the accumulation value:

+         
    
+            
  • the subtraction of the first byte in the second operand from the first byte in the 
+                first operand.
    • 
+            
  • the subtraction of the second byte in the second operand from the second byte in 
+                the first operand.
    • 
+            
  • the subtraction of the third byte in the second operand from the third byte in the 
+                first operand.
    • 
+            
  • the subtraction of the fourth byte in the second operand from the fourth byte in 
+                the first operand.
    • 
+          

+      
Operation
+        
+absdiff1  = val1[7:0]   - val2[7:0]
+absdiff2  = val1[15:8]  - val2[15:8]
+absdiff3  = val1[23:16] - val2[23:16]
+absdiff4  = val1[31:24] - val2[31:24]
+sum       = absdiff1 + absdiff2 + absdiff3 + absdiff4
+res[31:0] = sum[31:0] + val3[31:0]

+      

+
+
Function __SSAT16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SSAT16(uint32_t val1, const uint32_t val2);

+      
DescriptionThis function enables you to saturate two signed 16-bit values to a selected signed range.

+          The Q bit is set if either operation saturates.
+      
Parameter
+        
    
+          
  • val1: two signed 16-bit values to be saturated.
    • 
+          
  • val2: bit position for saturation, an integral constant expression in the
+              range 1 to 16.
    • 
+        

+      
Return Value
+         
The function returns:

+         
    
+            
  • the signed saturation of the low halfword in val1, saturated to the bit position 
+                specified in val2 and returned in the low halfword of the return value.
    • 
+            
  • the signed saturation of the high halfword in val1, saturated to the bit position 
+                specified in val2 and returned in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+Saturate halfwords in val1 to the signed range specified by the bit position in val2

+      

+
+
Function __USAT16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __USAT16(uint32_t val1, const uint32_t val2);

+      
DescriptionThis function enables you to saturate two signed 16-bit values to a selected unsigned 
+         range.

+         The Q bit is set if either operation saturates.
+      
Parameter
+        
    
+          
  • val1: two 16-bit values that are to be saturated.
    • 
+          
  • val2: bit position for saturation, and must be an integral constant 
+           expression in the range 0 to 15.
    • 
+        

+      
Return Value
+         
The function returns the saturation of the two signed 16-bit values, as non-negative values.

+         
    
+            
  • the saturation of the low halfword in val1, saturated to the bit position 
+                specified in val2 and returned in the low halfword of the return value.
    • 
+            
  • the saturation of the high halfword in val1, saturated to the bit position 
+                specified in val2 and returned in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+Saturate halfwords in val1 to the unsigned range specified by the bit position in val2

+      

+
+
Function __UXTB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UXTB16(uint32_t val);

+      
DescriptionThis function enables you to extract two 8-bit values from an operand and zero-extend 
+          them to 16 bits each.
+      
Parameter
+        
    
+          
  • val1: two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
    • 
+        

+      
Return Value
+         
The function returns the 8-bit values zero-extended to 16-bit values.

+         
    
+            
  • zero-extended value of val[7:0] in the low halfword of the return value.
    • 
+            
  • zero-extended value of val[23:16] in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = ZeroExtended(val[7:0]  )
+res[31:16] = ZeroExtended(val[23:16])

+      

+
+
Function __UXTAB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __UXTAB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to extract two 8-bit values from one operand, zero-extend them 
+          to 16 bits each, and add the results to two 16-bit values from another operand.
+      
Parameter
+        
    
+          
  • val1: value added to the zero-extended to 16-bit values.
    • 
+          
  • val2: two 8-bit values to be extracted and zero-extended.
    • 
+        

+      
Return Value
+         
The function returns the 8-bit values in val2, zero-extended to 16-bit values 
+            and added to val1.

+      
Operation
+        
+res[15:0]  = ZeroExt(val2[7:0]   to 16 bits) + val1[15:0]
+res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]

+      

+
+
Function __SXTB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SXTB16(uint32_t val);

+      
DescriptionThis function enables you to extract two 8-bit values from an operand and sign-extend 
+          them to 16 bits each.
+      
Parameter
+        
    
+          
  • val1: two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
    • 
+        

+      
Return Value
+         
The function returns the 8-bit values sign-extended to 16-bit values.

+         
    
+            
  • sign-extended value of val[7:0] in the low halfword of the return value.
    • 
+            
  • sign-extended value of val[23:16] in the high halfword of the return value.
    • 
+          

+      
Operation
+        
+res[15:0]  = SignExtended(val[7:0]
+res[31:16] = SignExtended(val[23:16]

+      

+
+
Function __SXTAB16

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SXTAB16(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to extract two 8-bit values from the second operand (at bit 
+          positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the 
+          first operand.
+      
Parameter
+        
    
+          
  • val1: values added to the zero-extended to 16-bit values.
    • 
+          
  • val2: two 8-bit values to be extracted and zero-extended.
    • 
+        

+      
Return Value
+         
The function returns the addition of val1 and val2, where the 8-bit values in 
+            val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.

+      
Operation
+        
+res[15:0]  = val1[15:0]  + SignExtended(val2[7:0])
+res[31:16] = val1[31:16] + SignExtended(val2[23:16])

+      

+
+
Function __SMUAD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMUAD(uint32_t val1, uint32_t val2);

+      
DescriptionThis function It enables you to perform two 16-bit signed multiplications, adding the 
+          products together.

+          The Q bit is set if the addition overflows.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+        

+      
Return Value
+         
The function returns the sum of the products of the two 16-bit signed multiplications.

+      
Operation
+        
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 + p2

+      

+
+
Function __SMUADX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMUADX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit signed multiplications with exchanged
+          halfwords of the second operand, adding the products together.

+          The Q bit is set if the addition overflows.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+        

+      
Return Value
+         
The function returns the sum of the products of the two 16-bit signed multiplications with exchanged
+            halfwords of the second operand.

+      
Operation
+        
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 + p2

+      

+
+
Function __SMLAD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMLAD(uint32_t val1, uint32_t val2, uint32_t val3);

+      
DescriptionThis function enables you to perform two signed 16-bit multiplications, adding both 
+          results to a 32-bit accumulate operand.

+          The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val2: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the product of each multiplication added to the accumulate 
+            value, as a 32-bit integer.

+      
Operation
+        
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 + p2 + val3[31:0]

+      

+
+
Function __SMLADX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMLADX(uint32_t val1, uint32_t val2, uint32_t val3);

+      
DescriptionThis function enables you to perform two signed 16-bit multiplications with exchanged
+          halfwords of the second operand, adding both results to a 32-bit accumulate operand.

+          The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val2: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the product of each multiplication with exchanged
+            halfwords of the second operand added to the accumulate value, as a 32-bit integer.

+      
Operation
+        
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 + p2 + val3[31:0]

+      

+
+
Function __SMLALD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint64_t __SMLALD(uint32_t val1, uint32_t val2, uint64_t val3);

+      
DescriptionThis function enables you to perform two signed 16-bit multiplications, adding both 
+          results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit 
+          addition. This overflow is not detected if it occurs. Instead, the result wraps around 
+          modulo264.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val2: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the product of each multiplication added to the accumulate value.

+      
Operation
+        
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+sum = p1 + p2 + val3[63:32][31:0]
+res[63:32] = sum[63:32]
+res[31:0]  = sum[31:0]

+      

+
+
Function __SMLALDX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+unsigned long long __SMLALDX(uint32_t val1, uint32_t val2, unsigned long long val3);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand, and perform 
+          two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. 
+          Overflow is only possible as a result of the 64-bit addition. This overflow is not detected 
+          if it occurs. Instead, the result wraps around modulo264.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val2: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the product of each multiplication added to the accumulate value.

+      
Operation
+        
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+sum = p1 + p2 + val3[63:32][31:0]
+res[63:32] = sum[63:32]
+res[31:0] = sum[31:0]

+      

+
+
Function __SMUSD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMUSD(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit signed multiplications, taking the 
+          difference of the products by subtracting the high halfword product from the low 
+          halfword product.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+        

+      
Return Value
+         
The function returns the difference of the products of the two 16-bit signed multiplications.

+      
Operation
+        
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 - p2

+      

+
+
Function __SMUSDX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMUSDX(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to perform two 16-bit signed multiplications, subtracting one 
+          of the products from the other. The halfwords of the second operand are exchanged 
+          before performing the arithmetic. This produces top * bottom and bottom * top 
+          multiplication.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+        

+      
Return Value
+         
The function returns the difference of the products of the two 16-bit signed multiplications.

+      
Operation
+        
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 - p2

+      

+
+
Function __SMLSD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMLSD(uint32_t val1, uint32_t val2, uint32_t val3);

+      
DescriptionThis function enables you to perform two 16-bit signed multiplications, take the 
+          difference of the products, subtracting the high halfword product from the low halfword 
+          product, and add the difference to a 32-bit accumulate operand.

+          The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the 
+          subtraction.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val3: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the difference of the product of each multiplication, added 
+            to the accumulate value.

+      
Operation
+        
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 - p2 + val3[31:0]

+      

+
+
Function __SMLSDX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint32_t __SMLSDX(uint32_t val1, uint32_t val2, uint32_t val3);

+      
DescriptionThis function enables you to exchange the halfwords in the second operand, then perform 
+          two 16-bit signed multiplications. The difference of the products is added to a 32-bit 
+          accumulate operand.

+          The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val3: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the difference of the product of each multiplication, added 
+            to the accumulate value.

+      
Operation
+        
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 - p2 + val3[31:0]

+      

+
+
Function __SMLSLD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+uint64_t __SMLSLD(uint32_t val1, uint32_t val2, uint64_t val3);

+      
DescriptionThis function It enables you to perform two 16-bit signed multiplications, take the 
+          difference of the products, subtracting the high halfword product from the low halfword 
+          product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur 
+          during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit 
+          addition, and this overflow is not detected. Instead, the result wraps round to  
+          modulo264.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val3: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the difference of the product of each multiplication, 
+            added to the accumulate value.

+      
Operation
+        
+p1 = val1[15:0]  * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[63:0] = p1 - p2 + val3[63:0]

+      

+
+
Function __SMLSLDX

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+  
+
Summary
+        
+unsigned long long __SMLSLDX(uint32_t val1, uint32_t val2, unsigned long long val3);

+      
DescriptionThis function enables you to exchange the halfwords of the second operand, perform two 
+          16-bit multiplications, adding the difference of the products to a 64-bit accumulate 
+          operand. Overflow cannot occur during the multiplications or the subtraction. Overflow 
+          can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, 
+          the result wraps round to modulo264.
+      
Parameter
+        
    
+          
  • val1: first 16-bit operands for each multiplication.
    • 
+          
  • val2: second 16-bit operands for each multiplication.
    • 
+          
  • val3: accumulate value.
    • 
+        

+      
Return Value
+         
The function returns the difference of the product of each multiplication, 
+            added to the accumulate value.

+      
Operation
+        
+p1 = val1[15:0]  * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[63:0] = p1 - p2 + val3[63:0]

+      

+
+
+
Function __SEL

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+  
+
Summary
+        
+uint32_t __SEL(uint32_t val1, uint32_t val2);

+      
DescriptionThis function inserts a SEL instruction into the instruction stream generated by the 
+          compiler. It enables you to select bytes from the input parameters, whereby the bytes 
+          that are selected depend upon the results of previous SIMD instruction function. The 
+          results of previous SIMD instruction function are represented by the Greater than or 
+          Equal flags in the Application Program Status Register (APSR).
+          The __SEL function works equally well on both halfword and byte operand function 
+          results. This is because halfword operand operations set two (duplicate) GE bits per 
+          value.
+      
Parameter
+        
    
+          
  • val1: four selectable 8-bit values.
    • 
+          
  • val2: four selectable 8-bit values.
    • 
+        

+      
Return Value
+         
The function selects bytes from the input parameters and returns them in the 
+            return value, res, according to the following criteria:

+         
    
+            
  • if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0]
    • 
+            
  • if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8]
    • 
+            
  • if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16]
    • 
+            
  • if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24]
    • 
+          

+      

+
+
Function __QADD

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+  
+
Summary
+        
+uint32_t __QADD(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to obtain the saturating add of two integers.

+         The Q bit is set if the operation saturates.
+      
Parameter
+        
    
+          
  • val1: first summand of the saturating add operation.
    • 
+          
  • val2: second summand of the saturating add operation.
    • 
+        

+      
Return Value
+         
The function returns the saturating addition of val1 and val2.

+      
Operation
+        
+res[31:0] = SAT(val1 + SAT(val2 * 2))

+      

+
+
Function __QSUB

+
+  
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+    
+      
+      
+    
+
+  
+
Summary
+        
+uint32_t __QSUB(uint32_t val1, uint32_t val2);

+      
DescriptionThis function enables you to obtain the saturating subtraction of two integers.

+         The Q bit is set if the operation saturates.
+      
Parameter
+        
    
+          
  • val1: minuend of the saturating subtraction operation.
    • 
+          
  • val2: subtrahend of the saturating subtraction operation.
    • 
+        

+      
Return Value
+         
The function returns the saturating subtraction of val1 and val2.

+      
Operation
+        
+res[31:0] = SAT(val1 - SAT(val2 * 2))

+      

+
+
+
+
 

+
Examples

+
Following are some coding examples using the SIMD functions:
+

+
+
+  
+    
+      
+      
+    
+ 
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+    
+      
+      
+      
+    
+
+  
+
NameDescription
AdditionAdd two values using SIMD function
SubtractionSubtract two values using SIMD function
MultiplicationPerforming a multiplication using SIMD function

+
+
+
Addition

+
+  
+    
+      
+      
+    
+  
+
Example
+        
+uint32_t add_halfwords(uint32_t val1, uint32_t val2)
+{
+   uint32_t res;
+   res = __SADD16(val1, val2);
+   return res;
+}

+      

+
+
Subtraction

+
+  
+    
+      
+      
+    
+  
+
Example
+        
+uint32_t sub_halfwords(uint32_t val1, uint32_t val2)
+{
+  uint32_t res;
+  res = __SSUB16(val1, val2);
+  return res;
+}

+      

+
+
Multiplication

+
+  
+    
+      
+      
+    
+  
+
Example
+        
+uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)
+{
+  uint32_t res;
+  res = __SMUAD(val1, val2);
+  return res;
+}

+      

+
+
+
+
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_Core.htm b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_Core.htm
new file mode 100644
index 0000000..d52ea1e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_Core.htm
@@ -0,0 +1,1470 @@
+
+
+  
+  CMSIS: Cortex Microcontroller Software Interface Standard
+  
+  
+
+
Cortex Microcontroller Software Interface Standard

+
+
This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).

+
Version: 2.10 - July 2011

+
+
Information in this file, the accompany manuals, and software is

+                 Copyright © ARM Ltd.
All rights reserved.
+

+
+

+
+
Revision History

+
    
+	
  • Version 1.00: initial release. 
    • 
+	
  • Version 1.01: added __LDREXx, __STREXx, and __CLREX.
    • 
+	
  • Version 1.02: added Cortex-M0. 
    • 
+	
  • Version 1.10: second review. 
    • 
+	
  • Version 1.20: third review. 
    • 
+	
  • Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.
    • 
+	
  • Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.
    • 
+	
  • Version 1.30: updated Device Support Packages.
    • 
+	
  • Version 2.00: added Cortex-M4 support.
    • 
+	
  • Version 2.01: internal review.
    • 
+	
  • Version 2.02: updated Device Specific Defines
    • 
+	
  • Version 2.10: reworked core include files
    • 
+

+
+

+
+
Contents

+
+
    
+  
  1. About
    2. 
+  
  2. Coding Rules and Conventions
    3. 
+  
  3. CMSIS Files
    4. 
+  
  4. Core Peripheral Access Layer
    5. 
+  
  5. CMSIS Example
    6. 
+  
  6. CMSIS MISRA-C:2004 Compliance Exceptions
    7. 
+

+
+
About

+
+

+  The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges
+  that are faced when software components are deployed to physical microcontroller devices based on a
+  Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M 
+  processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation
+  with various silicon and software vendors and provides a common approach to interface to peripherals, 
+  real-time operating systems, and middleware components.
+

+
+
ARM provides as part of the CMSIS the following software layers that are
+available for various compiler implementations:

+
    
+  
  • Core Peripheral Access Layer: contains name definitions, 
+    address definitions and helper functions to
+    access core registers and peripherals. It defines also a device
+    independent interface for RTOS Kernels that includes debug channel
+    definitions.
    • 
+

+
+
These software layers are expanded by Silicon partners with:

+
    
+  
  • Device Peripheral Access Layer: provides definitions
+    for all device peripherals
    • 
+  
  • Access Functions for Peripherals (optional): provides
+    additional helper functions for peripherals
    • 
+

+
+
CMSIS defines for a Cortex-M Microcontroller System:

+
    
+  
  • A common way to access peripheral registers
+    and a common way to define exception vectors.
    • 
+  
  • The register names of the Core
+    Peripherals and the names of the Core
+    Exception Vectors.
    • 
+  
  • An device independent interface for RTOS Kernels including a debug
+    channel.
    • 
+

+
+

+  By using CMSIS compliant software components, the user can easier re-use template code. 
+  CMSIS is intended to enable the combination of software components from multiple middleware vendors.
+

+
+
Coding Rules and Conventions

+
+

+  The following section describes the coding rules and conventions used in the CMSIS 
+  implementation. It contains also information about data types and version number information.
+

+
+
Essentials

+
    
+  
  • The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, 
+      there are disable and enable sequences for PC-LINT inserted.
    • 
+  
  • ANSI standard data types defined in the ANSI C header file
+    <stdint.h> are used.
    • 
+  
  • #define constants that include expressions must be enclosed by
+    parenthesis.
    • 
+  
  • Variables and parameters have a complete data type.
    • 
+  
  • All functions in the Core Peripheral Access Layer are
+    re-entrant.
    • 
+  
  • The Core Peripheral Access Layer has no blocking code
+    (which means that wait/query loops are done at other software layers).
    • 
+  
  • For each exception/interrupt there is definition for:
+  
      
+    
    • an exception/interrupt handler with the postfix _Handler 
+	(for exceptions) or _IRQHandler (for interrupts).
      • 
+    
    • a default exception/interrupt handler (weak definition) that contains an endless loop.
      • 
+    
    • a #define of the interrupt number with the postfix _IRQn.
      • 
+  
    • 
+

+
+
Recommendations

+
+
The CMSIS recommends the following conventions for identifiers.

+
    
+  
  • CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
    • 
+  
  • CamelCase names to identify peripherals access functions and interrupts.
    • 
+  
  • PERIPHERAL_ prefix to identify functions that belong to specify peripherals.
    • 
+  
  • Doxygen comments for all functions are included as described under Function Comments below.
    • 
+

+
+Comments
+
+
    
+  
  • Comments use the ANSI C90 style (/* comment */) or C++ style 
+  (// comment). It is assumed that the programming tools support today 
+	consistently the C++ comment style.
    • 
+  
  • Function Comments provide for each function the following information:
+  
      
+    
    • one-line brief function overview.
      • 
+    
    • detailed parameter explanation.
      • 
+    
    • detailed information about return values.
      • 
+    
    • detailed description of the actual function.
      • 
+  
    
+  
    Doxygen Example:
    
+  
    +/** 
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ * @param  IRQn  interrupt number that specifies the interrupt
+ * @return none.
+ * Enable the specified interrupt in the NVIC Interrupt Controller.
+ * Other settings of the interrupt such as priority are not affected.
+ */
    
+  
    • 
+

+
+
Data Types and IO Type Qualifiers

+
+

+  The Cortex-M HAL uses the standard types from the standard ANSI C header file
+  <stdint.h>. IO Type Qualifiers are used to specify the access
+  to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of 
+  debug information of peripheral registers.
+

+
+
+  
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+  
+
IO Type Qualifier#defineDescription
__Ivolatile constRead access only
__OvolatileWrite access only
__IOvolatileRead and write access

+
+
CMSIS Version Number

+

+  File core_cm4.h contains the version number of the CMSIS with the following define:
+

+
+
+#define __CM4_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
+#define __CM4_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB)

+
+

+  File core_cm3.h contains the version number of the CMSIS with the following define:
+

+
+
+#define __CM3_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
+#define __CM3_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)

+
+

+  File core_cm0.h contains the version number of the CMSIS with the following define:
+

+
+
+#define __CM0_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
+#define __CM0_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)

+
+
+
CMSIS Cortex Core

+

+  File core_cm4.h contains the type of the CMSIS Cortex-M with the following define:
+

+
+
+#define __CORTEX_M                (0x04)

+
+

+  File core_cm3.h contains the type of the CMSIS Cortex-M with the following define:
+

+
+
+#define __CORTEX_M                (0x03)

+
+

+  File core_cm0.h contains the type of the CMSIS Cortex-M with the following define:
+

+
+
+#define __CORTEX_M                (0x00)

+
+
+
CMSIS Files

+

+  This section describes the Files provided in context with the CMSIS to access the Cortex-M
+  hardware and peripherals.
+

+
+
+  
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+  
+
FileProviderDescription
device.hDevice specific (provided by silicon partner)Defines the peripherals for the actual device. The file may use 
+        several other include files to define the peripherals of the actual device.
core_cm0.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M0 CPU and core peripherals.
core_cm3.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M3 CPU and core peripherals.
core_cm4.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M4 CPU and core peripherals.
core_cm4_simd.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the Cortex-M4 Core SIMD functions.
core_cmFunc.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the Cortex-M Core Register access functions.
core_cmInstr.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the Cortex-M Core instructions.
startup_deviceARM (adapted by compiler partner / silicon partner)Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table
system_deviceARM (adapted by silicon partner)Provides a device specific configuration file for the device. It configures the device initializes 
+        typically the oscillator (PLL) that is part of the microcontroller device

+
+
device.h

+
+

+  The file device.h is provided by the silicon vendor and is the 
+  central include file that the application programmer is using in 
+  the C source code. This file contains:
+

+
    
+  
  • 
+	
    Interrupt Number Definition: provides interrupt numbers 
+	(IRQn) for all core and device specific exceptions and interrupts.
    
+	
    • 
+	
  • 
+	
    Configuration for core_cm0.h / core_cm3.h / core_cm4.h: reflects the 
+	actual configuration of the Cortex-M processor that is part of the actual 
+	device. As such the file core_cm0.h / core_cm3.h / core_cm4.h is included that 
+	implements access to processor registers and core peripherals. 
    
+	
    • 
+	
  • 
+	
    Device Peripheral Access Layer: provides definitions
+    for all device peripherals. It contains all data structures and the address 
+	mapping for the device specific peripherals. 
    
+	
    • 
+  
  • Access Functions for Peripherals (optional): provides
+    additional helper functions for peripherals that are useful for programming 
+	of these peripherals. Access Functions may be provided as inline functions 
+	or can be extern references to a device specific library provided by the 
+	silicon vendor.
    • 
+

+
+
+
Interrupt Number Definition

+
+
To access the device specific interrupts the device.h file defines IRQn 
+numbers for the complete device using a enum typedef as shown below:

+
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
+  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                              */
+  HardFault_IRQn                  = -13,      /*!< 3 Cortex-M3 Hard Fault Interrupt                      */
+  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt               */
+  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                       */
+  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                     */
+  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                        */
+  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                  */
+  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                        */
+  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                    */
+/******  STM32 specific Interrupt Numbers ****************************************************************/
+  WWDG_STM_IRQn                   = 0,        /*!< Window WatchDog Interrupt                             */
+  PVD_STM_IRQn                    = 1,        /*!< PVD through EXTI Line detection Interrupt             */
+  :
+  :
+  } IRQn_Type;

+
+
+
Device Specific Defines

+

+  The following device implementation specific defines are set in the device header file and are 
+  used for the Cortex-M core configuration options. Some configuration options are reflected 
+  in the CMSIS layer using the #define settings described below.
+

+

+  Several features in core_cm#.h are configured by the following defines 
+  that must be defined before #include <core_cm#.h>
+  preprocessor command.
+

+
+
+  
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+    
+      
+      
+      
+      
+    
+  
+
#defineCoreValueDescription
__CM0_REVM00x0000Core revision number ([15:8] revision number, [7:0] patch number)
__CM3_REVM30x0101 | 0x0200Core revision number ([15:8] revision number, [7:0] patch number)
__CM4_REVM40x0000Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITSM0, M3, M42 .. 8Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENTM0, M3, M40 | 1Defines if a MPU is present or not
__FPU_PRESENTM40 | 1Defines if a FPU is present or not
__Vendor_SysTickConfigM0, M3, M40 | 1When this define is setup to 1, the SysTickConfig function 
+		in core_cm3.h is excluded. In this case the device.h 
+		file must contain a vendor specific implementation of this function.

+
+
+
Device Peripheral Access Layer

+

+  Each peripheral uses a prefix which consists of <device abbreviation>_ 
+  and <peripheral name>_ to identify peripheral registers that access this 
+  specific peripheral. The intention of this is to avoid name collisions caused
+  due to short names. If more than one peripheral of the same type exists, 
+  identifiers have a postfix (digit or letter). For example:
+

+
    
+	
  • <device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device.
+      
    +typedef struct
+{
+  union {
+  __I  uint8_t  RBR;                     /*!< Offset: 0x000 (R/ )  Receiver Buffer Register    */
+  __O  uint8_t  THR;                     /*!< Offset: 0x000 ( /W)  Transmit Holding Register   */
+  __IO uint8_t  DLL;                     /*!< Offset: 0x000 (R/W)  Divisor Latch LSB           */
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;                     /*!< Offset: 0x004 (R/W)  Divisor Latch MSB           */
+  __IO uint32_t IER;                     /*!< Offset: 0x004 (R/W)  Interrupt Enable Register   */
+  };
+  union {
+  __I  uint32_t IIR;                     /*!< Offset: 0x008 (R/ )  Interrupt ID Register       */
+  __O  uint8_t  FCR;                     /*!< Offset: 0x008 ( /W)  FIFO Control Register       */
+  };
+  __IO uint8_t  LCR;                     /*!< Offset: 0x00C (R/W)  Line Control Register       */
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;                     /*!< Offset: 0x014 (R/ )  Line Status Register        */
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;                     /*!< Offset: 0x01C (R/W)  Scratch Pad Register        */
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;                     /*!< Offset: 0x020 (R/W)  Autobaud Control Register   */
+  __IO uint8_t  ICR;                     /*!< Offset: 0x024 (R/W)  IrDA Control Register       */
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;                     /*!< Offset: 0x028 (R/W)  Fractional Divider Register */
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;                     /*!< Offset: 0x030 (R/W)  Transmit Enable Register    */
+       uint8_t  RESERVED6[39];
+  __I  uint8_t  FIFOLVL;                 /*!< Offset: 0x058 (R/ )  FIFO Level Register         */
+} LPC_UART_TypeDef;
    
+  
    • 
+	
  • <device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART. 
+      For example UART1->THR is the transmit holding register of UART1.
+      
    +#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
    
+  
    • 
+

+
+
Minimal Requiements

+

+  To access the peripheral registers and related function in a device the files device.h 
+  and core_cm0.h / core_cm3.h defines as a minimum:
+

+
    
+  
  • The Register Layout Typedef for each peripheral that defines all register names.
+      Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
+      the peripheral registers. For example:
+      
    +typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
    
+  
    • 
+
+  
  • 
+    Base Address for each peripheral (in case of multiple peripherals 
+    that use the same register layout typedef multiple base addresses are defined). For example:
+    
    +#define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */
    
+  
    • 
+
+  
  • 
+    Access Definition for each peripheral (in case of multiple peripherals that use 
+    the same register layout typedef multiple access definitions exist, i.e. LPC_UART0, 
+    LPC_UART2). For Example:
+    
    +#define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */
    
+  
    • 
+

+
+

+  These definitions allow to access the peripheral registers from user code with simple assignments like:
+

+
SysTick->CTRL = 0;

+
+
Optional Features

+
In addition the  device.h file may define:

+
    
+	
  • 
+    #define constants that simplify access to the peripheral registers. 
+	  These constant define bit-positions or other specific patterns are that required for the 
+    programming of the peripheral registers. The identifiers used start with 
+    <device abbreviation>_ and <peripheral name>_. 
+    It is recommended to use CAPITAL letters for such #define constants.
+  
    • 
+	
  • 
+    Functions that perform more complex functions with the peripheral (i.e. status query before 
+    a sending register is accessed). Again these function start with 
+    <device abbreviation>_ and <peripheral name>_. 
+  
    • 
+

+
+
core_cm0.h

+

+  File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does 
+  the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers 
+  and core peripherals with efficient functions (defined as static inline).
+

+
This file implement the Core Peripheral Access Layer for a Cortex-M0.

+
The define  __CMSIS_GENERIC allows to use core_cm0.h in generic 
+   library projects that are device independent. Only core relevant types and defines are used.

+
+
core_cm3.h

+

+  File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does 
+  the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers 
+  and core peripherals with efficient functions (defined as static inline).
+

+
This file implement the Core Peripheral Access Layer for a Cortex-M3.

+
The define  __CMSIS_GENERIC allows to use core_cm3.h in generic 
+   library projects that are device independent. Only core relevant types and defines are used.

+
+
core_cm4.h, core_cm4_simd.h

+

+  File core_cm4.h describes the data structures for the Cortex-M4 core peripherals and does 
+  the address mapping of this structures. It also provides basic access to the Cortex-M4 core registers 
+  and core peripherals with efficient functions (defined as static inline).
+

+

+  File core_cm4_simd.h defines Cortex-M4 SIMD instructions.
+

+
Together these files implement the Core Peripheral Access Layer for a Cortex-M4.

+
The define  __CMSIS_GENERIC allows to use core_cm4.h in generic 
+   library projects that are device independent. Only core relevant types and defines are used.

+
+
core_cmFunc.h and core_cmInstr.h

+

+  File core_cmFunc.h defines the Cortex-M Core Register access functions (defined as static inline).
+

+

+  File core_cmInstr.h defines the Cortex-M Core instructions (defined as static inline).
+

+
These files are part of the Core Peripheral Access Layer for a Cortex-M.

+
+
startup_device

+

+  A template file for startup_device is provided by ARM for each supported
+  compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific 
+  interrupt handlers. Each interrupt handler is defined as weak function 
+  to an dummy handler. Therefore the interrupt handler can be directly used in application software 
+  without any requirements to adapt the startup_device file.
+

+

+  The following exception names are fixed and define the start of the vector table for a Cortex-M0:
+

+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler

+
+

+  The following exception names are fixed and define the start of the vector table for a Cortex-M3:
+

+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler

+
+

+  In the following examples for device specific interrupts are shown:
+

+
+; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler         ; Tamper

+
+

+  Device specific interrupts must have a dummy function that can be overwritten in user code. 
+  Below is an example for this dummy function.
+

+
+Default_Handler PROC
+                EXPORT WWDG_IRQHandler   [WEAK]
+                EXPORT PVD_IRQHandler    [WEAK]
+                EXPORT TAMPER_IRQHandler [WEAK]
+                :
+                :
+                WWDG_IRQHandler
+                PVD_IRQHandler
+                TAMPER_IRQHandler
+                :
+                :
+                B .
+                ENDP

+                
+

+  The user application may simply define an interrupt handler function by using the handler name
+  as shown below.
+

+
+void WWDG_IRQHandler(void)
+{
+  :
+  :
+}

+
+
+
system_device.c

+

+  A template file for system_device.c is provided by ARM but adapted by 
+  the silicon vendor to match their actual device. As a minimum requirement 
+  this file must provide a device specific system configuration function and a global variable 
+  that contains the system frequency. It configures the device and initializes typically the 
+  oscillator (PLL) that is part of the microcontroller device.
+

+

+  The file system_device.c must provide
+  as a minimum requirement the SystemInit function as shown below.
+

+
+
+  
+    
+      
+      
+    
+    
+      
+      
+    
+    
+      
+      
+    
+  
+
Function DefinitionDescription
void SystemInit (void)Setup the microcontroller system. Typically this function configures the 
+                     oscillator (PLL) that is part of the microcontroller device. For systems 
+                     with variable clock speed it also updates the variable SystemCoreClock.

+                     SystemInit is called from startup_device file.
void SystemCoreClockUpdate (void)Updates the variable SystemCoreClock and must be called whenever the 
+                     core clock is changed during program execution. SystemCoreClockUpdate()
+                     evaluates the clock register settings and calculates the current core clock.
+

+
+

+  Also part of the file system_device.c 
+  is the variable SystemCoreClock which contains the current CPU clock speed shown below.
+

+
+
+  
+    
+      
+      
+    
+    
+      
+      
+    
+  
+
Variable DefinitionDescription
uint32_t SystemCoreClockContains the system core clock (which is the system clock	frequency supplied 
+                     to the SysTick timer and the processor core clock). This variable can be 
+                     used by the user application to setup the SysTick timer or configure other 
+                     parameters. It may also be used by debugger to query the frequency of the 
+                     debug timer or configure the trace clock speed.

+                     SystemCoreClock is initialized with a correct predefined value.


+		                 The compiler must be configured to avoid the removal of this variable in 
+		                 case that the application program is not using it. It is important for 
+		                 debug systems that the variable is physically present in memory so that 
+		                 it can be examined to configure the debugger.

+
+
Note

+
    
+  
  • The above definitions are the minimum requirements for the file 
+	system_device.c. This 
+	file may export more functions or variables that provide a more flexible 
+	configuration of the microcontroller system.
    
+  
    • 
+

+
+
+
Core Peripheral Access Layer

+
+
Cortex-M Core Register Access

+

+  The following functions are defined in core_cm0.h / core_cm3.h
+  and provide access to Cortex-M core registers.
+

+
+
+  
+    
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+
Function DefinitionCoreCore RegisterDescription
void __enable_irq (void)M0, M3, M4PRIMASK = 0Global Interrupt enable (using the instruction CPSIE	i)
void __disable_irq (void)M0, M3, M4PRIMASK = 1Global Interrupt disable (using the instruction CPSID i)
uint32_t __get_CONTROL (void)M0, M3, M4return CONTROLReturn Control Register Value (using the instruction MRS)
void __set_CONTROL (uint32_t value)M0, M3, M4CONTROL = valueSet CONTROL register value (using the instruction MSR)
uint32_t __get_IPSR (void)M0, M3, M4return IPSRReturn IPSR Register Value (using the instruction MRS)
uint32_t __get_APSR (void)M0, M3, M4return APSRReturn APSR Register Value (using the instruction MRS)
uint32_t __get_xPSR (void)M0, M3, M4return xPSRReturn xPSR Register Value (using the instruction MRS)
uint32_t __get_PSP (void)M0, M3, M4return PSPReturn Process Stack Pointer (using the instruction MRS)
void __set_PSP (uint32_t TopOfProcStack)>M0, M3, M4PSP = TopOfProcStackSet Process Stack Pointer value (using the instruction MSR)
uint32_t __get_MSP (void)M0, M3, M4return MSPReturn Main Stack Pointer (using the instruction MRS)
void __set_MSP (uint32_t TopOfMainStack)M0, M3, M4MSP = TopOfMainStackSet Main Stack Pointer (using the instruction MSR)
uint32_t __get_PRIMASK (void)M0, M3, M4return PRIMASKReturn Priority Mask Register (using the instruction MRS)
void __set_PRIMASK (uint32_t value)M0, M3, M4PRIMASK = valueAssign value to Priority Mask Register (using the instruction MSR)
void __enable_fault_irq (void)M3, M4FAULTMASK = 0Global Fault exception and Interrupt enable (using the instruction CPSIE f)
void __disable_fault_irq (void)M3, M4FAULTMASK = 1Global Fault exception and Interrupt disable (using the instruction CPSID f)
uint32_t __get_BASEPRI (void)M3, M4return BASEPRIReturn Base Priority (using the instruction MRS)
void __set_BASEPRI (uint32_t value)M3, M4BASEPRI = valueSet Base Priority (using the instruction MSR)
uint32_t __get_FAULTMASK (void)M3, M4return FAULTMASKReturn Fault Mask Register (using the instruction MRS)
void __set_FAULTMASK (uint32_t value)M3, M4FAULTMASK = valueAssign value to Fault Mask Register (using the instruction MSR)
uint32_t __get_FPSCR (void)M4return FPSCRReturn Floating Point Status / Control Register
void __set_FPSCR (uint32_t value)M4FPSCR = valueAssign value to Floating Point Status / Control Register

+
+
Cortex-M Instruction Access

+

+  The following functions are defined in core_cm0.h / core_cm3.hand
+  generate specific Cortex-M instructions. The functions are implemented in the file 
+  core_cm0.c / core_cm3.c.
+

+
+
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+  
+
NameCoreGenerated CPU InstructionDescription
void __NOP (void)M0, M3, M4NOPNo Operation
void __WFI (void)M0, M3, M4WFIWait for Interrupt
void __WFE (void)M0, M3, M4WFEWait for Event
void __SEV (void)M0, M3, M4SEVSet Event
void __ISB (void)M0, M3, M4ISBInstruction Synchronization Barrier
void __DSB (void)M0, M3, M4DSBData Synchronization Barrier
void __DMB (void)M0, M3, M4DMBData Memory Barrier
uint32_t __REV (uint32_t value)M0, M3, M4REVReverse byte order in integer value.
uint32_t __REV16 (uint16_t value)M0, M3, M4REV16Reverse byte order in unsigned short value. 
sint32_t __REVSH (sint16_t value)M0, M3, M4REVSHReverse byte order in signed short value with sign extension to integer.
uint32_t __RBIT (uint32_t value)M3, M4RBITReverse bit order of value
uint8_t __LDREXB (uint8_t *addr)M3, M4LDREXBLoad exclusive byte
uint16_t __LDREXH (uint16_t *addr)M3, M4LDREXHLoad exclusive half-word
uint32_t __LDREXW (uint32_t *addr)M3, M4LDREXWLoad exclusive word
uint8_t __STREXB (uint8_t value, uint8_t *addr)M3, M4STREXBStore exclusive byte
uint16_t __STREXH (uint16_t value, uint16_t *addr)M3, M4STREXHStore exclusive half-word
uint32_t __STREXW (uint32_t value, uint32_t *addr)M3, M4STREXWStore exclusive word
void  __CLREX (void)M3, M4CLREXRemove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW
void  __SSAT (void)M3, M4SSATsaturate a signed value
void  __USAT (void)M3, M4USATsaturate an unsigned value

+
+
+
NVIC Access Functions

+

+  The CMSIS provides access to the NVIC via the register interface structure and several helper
+  functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to 
+  identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative 
+  IRQn values are used for processor core exceptions.
+

+

+  For the IRQn values of core exceptions the file device.h provides 
+  the following enum names.
+

+
+
+  
+    
+      
+      
+      
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+    
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+  
+
Core Exception enum ValueCoreIRQnDescription
NonMaskableInt_IRQnM0, M3, M4-14Cortex-M Non Maskable Interrupt
HardFault_IRQnM0, M3, M4-13Cortex-M Hard Fault Interrupt
MemoryManagement_IRQnM3, M4-12Cortex-M Memory Management Interrupt
BusFault_IRQnM3, M4-11Cortex-M Bus Fault Interrupt
UsageFault_IRQnM3, M4-10Cortex-M Usage Fault Interrupt
SVCall_IRQnM0, M3, M4-5Cortex-M SV Call Interrupt 
DebugMonitor_IRQnM3, M4-4Cortex-M Debug Monitor Interrupt
PendSV_IRQnM0, M3, M4-2Cortex-M Pend SV Interrupt
SysTick_IRQnM0, M3, M4-1Cortex-M System Tick Interrupt

+
+
The following functions simplify the setup of the NVIC.
+The functions are defined as static inline.

+
+
+  
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+    
+  
+
NameCoreParameterDescription
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)M3, M4Priority Grouping ValueSet the Priority Grouping (Groups . Subgroups)
uint32_t NVIC_GetPriorityGrouping (void)M3, M4(void)Get the Priority Grouping (Groups . Subgroups)
void NVIC_EnableIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberEnable IRQn
void NVIC_DisableIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberDisable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberReturn 1 if IRQn is pending else 0
void NVIC_SetPendingIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberSet IRQn Pending
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)M0, M3, M4IRQ NumberClear IRQn Pending Status
uint32_t NVIC_GetActive (IRQn_Type IRQn)M3, M4IRQ NumberReturn 1 if IRQn is active else 0
void NVIC_SetPriority (

+	    IRQn_Type IRQn,

+	    uint32_t priority)		M0, M3, M4IRQ Number, PrioritySet Priority for IRQn

+                     (not threadsafe for Cortex-M0)
uint32_t NVIC_GetPriority (IRQn_Type IRQn)M0, M3, M4IRQ NumberGet Priority for IRQn
uint32_t NVIC_EncodePriority (

+	    uint32_t PriorityGroup,

+	    uint32_t PreemptPriority,

+	    uint32_t SubPriority)		M3, M4IRQ Number,

+	  Priority Group,

+	  Preemptive Priority,

+	  Sub Priority		Encode priority for given group, preemptive and sub priority
void NVIC_DecodePriority (

+	    uint32_t Priority,
 
+	    uint32_t PriorityGroup,
 
+	    uint32_t* pPreemptPriority,
 
+	    uint32_t* pSubPriority)		M3, M4

+	  Priority,

+	  Priority Group,

+	  pointer to Preempt. Priority,

+	  pointer to Sub Priority		Decode given priority to group, preemptive and sub priority
void NVIC_SystemReset (void)M0, M3, M4(void)Resets the System

+
Note

+
    
+  
  • The processor exceptions have negative enum values. Device specific interrupts 
+         have positive enum values and start with 0. The values are defined in
+         device.h file.
+      
    
+  
    • 
+  
  • The values for PreemptPriority and SubPriority
+         used in functions NVIC_EncodePriority and NVIC_DecodePriority
+         depend on the available __NVIC_PRIO_BITS implemented in the NVIC.
+      
    
+  
    • 
+

+
+
+
SysTick Configuration Function

+
+
The following function is used to configure the SysTick timer and start the 
+SysTick interrupt.

+
+
+  
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+  
+
NameParameterDescription
uint32_t SysTickConfig (uint32_t ticks)ticks is SysTick counter reload valueSetup the SysTick timer and enable the SysTick interrupt. After this 
+        call the SysTick timer creates interrupts with the specified time interval.


+        Return: 0 when successful, 1 on failure.

+      

+
+
+
Cortex-M3 / Cortex-M4 ITM Debug Access

+
+
The Cortex-M3 / Cortex-M4 incorporates the Instrumented Trace Macrocell (ITM) that 
+provides together with the Serial Viewer Output trace capabilities for the 
+microcontroller system. The ITM has 32 communication channels; two ITM 
+communication channels are used by CMSIS to output the following information:

+
    
+  
  • ITM Channel 0: implements the ITM_SendChar function 
+      which can be used for printf-style output via the debug interface.
    • 
+  
  • ITM Channel 31: is reserved for the RTOS kernel and can be used for 
+      kernel awareness debugging.
    • 
+

+
Note

+
    
+  
  • The ITM channel 31 is selected for the RTOS kernel since some kernels 
+      may use the Privileged level for program execution. ITM 
+      channels have 4 groups with 8 channels each, whereby each group can be 
+      configured for access rights in the Unprivileged level. The ITM channel 0 
+      may be therefore enabled for the user task whereas ITM channel 31 may be 
+      accessible only in Privileged level from the RTOS kernel itself.
    
+  
    • 
+

+
+
The prototype of the ITM_SendChar routine is shown in the 
+table below.

+
+
+  
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+  
+
NameParameterDescription
void uint32_t ITM_SendChar(uint32_t chr)character to outputThe function outputs a character via the ITM channel 0. The 
+                     function returns when no debugger is connected that has booked the 
+                     output. It is blocking when a debugger is connected, but the 
+                     previous character send is not transmitted.


+                     Return: the input character 'chr'.
+      

+
+

+  Example for the usage of the ITM Channel 31 for RTOS Kernels:
+

+
+  // check if debugger connected and ITM channel enabled for tracing
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+  (ITM->TCR & ITM_TCR_ITMENA) &&
+  (ITM->TER & (1UL << 31))) {
+    // transmit trace data
+    while (ITM->PORT31_U32 == 0);
+    ITM->PORT[31].u8 = task_id;      // id of next task
+    while (ITM->PORT[31].u32 == 0);
+    ITM->PORT[31].u32 = task_status; // status information
+  }

+
+
+
Cortex-M3 additional Debug Access

+
+
CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access.
+Data can be transmitted via a certain global buffer variable towards the target system.

+
+
The buffer variable and the prototypes of the additional functions are shown in the 
+table below.

+
+
+  
+    
+      
+      
+      
+    
+    
+      
+      
+      
+    
+    
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+      
+      
+    
+  
+
NameParameterDescription
extern volatile int ITM_RxBuffer Buffer to transmit data towards debug system. 


+                     Value 0x5AA55AA5 indicates that buffer is empty.
int ITM_ReceiveChar (void)noneThe nonblocking functions returns the character stored in 
+                     ITM_RxBuffer. 


+                     Return: -1 indicates that no character was received.
int ITM_CheckChar (void)noneThe function checks if a character is available in ITM_RxBuffer. 


+                     Return: 1 indicates that a character is available, 0 indicates that
+                     no character is available.

+
+
+
CMSIS Example

+

+  The following section shows a typical example for using the CMSIS layer in user applications.
+  The example is based on a STM32F10x Device.
+

+
+#include "stm32f10x.h"
+
+volatile uint32_t msTicks;                       /* timeTicks counter */
+
+void SysTick_Handler(void) {
+  msTicks++;                                     /* increment timeTicks counter */
+}
+
+__INLINE static void Delay (uint32_t dlyTicks) {
+  uint32_t curTicks = msTicks;
+
+  while ((msTicks - curTicks) < dlyTicks);
+}
+
+__INLINE static void LED_Config(void) {
+  ;                                              /* Configure the LEDs */
+}
+
+__INLINE static void LED_On (uint32_t led) {
+  ;                                              /* Turn On  LED */
+}
+
+__INLINE static void LED_Off (uint32_t led) {
+  ;                                              /* Turn Off LED */
+}
+
+int main (void) {
+  if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
+    ;                                            /* Handle Error */
+    while (1);
+  }
+  
+  LED_Config();                                  /* configure the LEDs */                            
+ 
+  while(1) {
+    LED_On (0x100);                              /* Turn  on the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+    LED_Off (0x100);                             /* Turn off the LED   */
+    Delay (100);                                 /* delay  100 Msec    */
+  }
+}

+
+
+
CMSIS MISRA-C:2004 Compliance Exceptions

+

+  CMSIS violates following MISRA-C2004 Rules:
+

+
    
+   
  • Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
    
+       Function definitions in header files are used to allow 'inlining'.
    •  
+
+   
  • Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    
+       Unions are used for effective representation of core registers.
    • 
+   
+   
  • Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
    
+       Function-like macros are used to allow more efficient code.
    •  
+

+
+
  

+
+
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_DebugSupport.htm b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_DebugSupport.htm
new file mode 100644
index 0000000..9ed077d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_DebugSupport.htm
@@ -0,0 +1,240 @@
+
+
+
+CMSIS Debug Support
+
+
+
+
+
+
+
+
+
CMSIS Debug Support

+
This file describes the CMSIS Debug support available with CMSIS (starting V1.30).

+
Version: 1.02 - 25. July 2011

+
+
Information in this file, the accompany manuals, and software is

+                 Copyright © ARM Ltd.
All rights reserved.
+

+
+

+
+
Revision History

+
    
+	
  • Version 1.00: Initial Release. 
    • 
+	
  • Version 1.01: Internal Review. 
    • 
+	
  • Version 1.02: Removed product specific information. 
    • 
+

+
+

+
+
Contents

+
+
    
+  
  1. About
    2. 
+  
  2. Cortex-M3 / Cortex-M4 ITM Debug Access
    3. 
+  
  3. Debug IN / OUT functions
    4. 
+  
  4. ITM Debug Support in Debugger
    5. 
+

+
+
 

+
About

+

+  CMSIS provides for Cortex-M3 / Cortex-M4 processor based microcontrollers debug support via the Instrumented Trace Macrocell (ITM).
+  This document describes the available CMSIS Debug functions and the used methods.
+

+
+
 

+
Cortex-M3 / Cortex-M4 ITM Debug Access

+

+  The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with 
+  the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has 
+  32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM 
+  communication channels are used by CMSIS to output the following information:
+

+
    
+	
  • ITM Channel 0: used for printf-style output via the debug interface.
    • 
+	
  • ITM Channel 31: is reserved for RTOS kernel awareness debugging.
    • 
+

+
+
 

+
Debug IN / OUT functions

+
CMSIS provides following debug functions:

+
    
+	
  • ITM_SendChar (uses ITM channel 0)
    • 
+	
  • ITM_ReceiveChar (uses global variable)
    • 
+	
  • ITM_CheckChar (uses global variable)
    • 
+

+
+
ITM_SendChar

+

+  ITM_SendChar is used to transmit a character over ITM channel 0 from 
+  the microcontroller system to the debug system. 

+  Only a 8 bit value is transmitted.
+

+
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  /* check if debugger connected and ITM channel enabled for tracing */
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&
+      (ITM->TCR & ITM_TCR_ITMENA)                  &&
+      (ITM->TER & (1UL << 0))  ) 
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }  
+  return (ch);
+}

+
+
ITM_ReceiveChar

+

+  ITM communication channel is only capable for OUT direction. For IN direction
+  a global variable is used. A simple mechanism detects if a character is received.
+  The project to test need to be build with debug information.
+

+
+

+  The global variable ITM_RxBuffer is used to transmit a 8 bit value from debug system
+  to microcontroller system. ITM_RxBuffer is 32 bit wide to 
+	ensure a proper handshake.
+

+
+extern volatile int32_t ITM_RxBuffer;                    /* variable to receive characters                             */
+

+

+  A dedicated bit pattern is used to determine if ITM_RxBuffer is empty
+  or contains a valid value.
+

+
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
+

+

+  ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking.
+  It returns the received character or '-1' if no character was available.
+

+
+static __INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                               /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+  
+  return (ch); 
+}
+

+
+
ITM_CheckChar

+

+  ITM_CheckChar is used to check if a character is received.
+

+
+static __INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}

+
+
+
 

+
ITM Debug Support in a Debugger

+

+  The Debugger shall offer a dedicated console window for printf style debug input and output using the CMSIS defined ITM methods described above.
+

+
Direction: Microcontroller -> Debugger:

+
    
+  
  • 
+    at the beginning of a debug session the debugger shall enable ITM trace on channel 0 and continuously snoop for channel 0 data on the ITM trace
+    stream it receives from the Microcontroller's CoreSight ITM unit
+  
    • 
+  
  • 
+    data received via the ITM communication channel 0 is interpreted as charater and gets redirected into the dedicated Console Window
+  
    • 
+

+
+
Direction: Debugger -> Microcontroller:

+
    
+  
  • 
+    at the beginning of a debug session the debugger shall seek for the presence of the global variable named ITM_RxBuffer in the debug
+    information of the application being loaded
+  
    • 
+  
  • 
+    strings entered into the Console Window are written by the debugger as a stream of char values via the variable ITM_RxBuffer.
+  
    • 
+  
  • 
+    the debugger writes the next character into the ITM_RxBuffer only once the value has been read and the ITM_RXBUFFER_EMPTY value being set.
+    (refer to: ITM_ReceiveChar()).
+

+
+
+
+
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_History.htm b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_History.htm
new file mode 100644
index 0000000..9b44a3f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_History.htm
@@ -0,0 +1,472 @@
+
+
+
+CMSIS Version History
+
+
+
+
+
+
+
+
+
CMSIS Version History

+
This document describes the changes between the different CMSIS versions.

+
Version: 2.10 - July 2011

+
+
Information in this file, the accompany manuals, and software is

+                 Copyright © ARM Ltd.
All rights reserved.
+

+
+

+
+
+
Contents

+
+
    
+  
  1. Used Toolchains
    2. 
+  
  2. Changes to version V2.00
    3. 
+  
  3. Changes to version V1.30
    4. 
+  
  4. Changes to version V1.20
    5. 
+  
  5. Open Points
    6. 
+  
  6. Limitations
    7. 
+

+
+
+
Used Toolchains

+

+  Following toolchains have been used for test / verification:.
+

+  
    
+    
  • ARM: MDK-ARM Version 4.21
    • 
+    
  • GNU: Sourcery G++ Lite Edition for ARM 2010.09-51
    • 
+    
  • IAR: IAR Embedded Workbench Kickstart Edition V6.10
    • 
+  

+
+
+
Changes to version V2.00

+
+
Added CMSIS DSP Software Library support for Cortex-M0 based MCUs

+

+  The CMSIS DSP Software Library provides now also libraries and examples for Cortex-M0.
+

+

+  For more information refer to CMSIS DSP Library documentation.
+

+
+
Added big endian support for DSP library

+

+  The CMSIS DSP Software Library provides now also pre-build libraries 
+	and projects for big endian devices.
+

+

+  For more information refer to CMSIS DSP Library documentation.
+

+
+
+
Simplified folder structure for CMSIS include files

+

+  All CMSIS core include files as well as the DSP-Library header files are located in 
+	a single folder ./CMSIS/Include.
+

+
+
Changed folder structure for Device Support packages

+

+  Device Support packages are expected to be in folder ./Device located at the
+  same level as ./CMSIS.
+

+
The new Device folder contains the following subfolders:

+  
    
+     
  • Device
    • 
+       
      
+         
    • <Vendor> 
+           
        
+             
      • <Device> | <Device Series>
+               
          
+                  
        • Include
          
+                      <device>.h
          
+                      system_<device>.h
          
+                  
          • 
+                  
        • Source
+                    
            
+                       
          • Templates
            
+                           system_<device>.c
            
+                          
              
+                             
            • <Toolchain>
              
+                                 startup_<device>.s
              
+                             
              • 
+                             
            • <Toolchain>
              • 
+                                
            • ...
              • 
+                          
            
+                       
            • 
+                    
          
+                  
          • 
+               
        
+             
      • <Device> | <Device Series>
        • 
+             
      • ...
        • 
+           
      
+         
      • 
+         
    • <Vendor>
      • 
+         
    • ...
      • 
+       
    
+     
+  

+
Template files are application specific files and are required to be copied to the project prior to use!

+
+
Removed CMSIS core source files

+

+  The CMSIS core source files core_cm0.c, core_cm3.c, core_cm4.c 
+  containing helper functions for older ARM compiler versions got removed.
+

+

+  For the ARM Compiler Toolchain version V4.0.677 or later is 
+	required!

+
+
+
Changes to version V1.30

+
+
Added CMSIS DSP Software Library

+

+  The CMSIS DSP Software Library is a suite of common signal processing functions targeted 
+  to Cortex-M processor based microcontrollers. Even though the code has been specifically 
+  optimized towards using the extended DSP instruction set of the Cortex-M4 processor, 
+  the library can be compiled for any Cortex-M processor.
+

+

+  For more information see CMSIS DSP Library documentation.
+

+
+
Added CMSIS System View Description

+

+  The CMSIS System View Description answers the challenges of accurate, detailed and 
+  timely device aware peripheral debugging support for Cortex Microcontroller based 
+  devices by the software development tools vendor community.
+

+

+  Silicon vendors shall create and maintain a formalized description of the debug view 
+  for all the peripherals contained in their Cortex Microcontroller based devices.
+  Tool vendors use such descriptions to establish device specific debug support in 
+  their debugging tools.
+

+

+  A standardized System View Description shall provide a common approach to 
+  capturing peripheral debug related information in a machine readable files.
+

+

+  For more information see CMSIS System View Description.
+

+
+
Added Cortex-M4 Core Support

+

+  Additional folder CM4, containing the Cortex-M4 core support files, has been added.
+

+  
    
+    
  • CM0
    • 
+    
  • CM3
    • 
+    
  • CM4
+       
      
+         
    • CoreSupport
      • 
+         
    • DeviceSupport
      • 
+       
    
+    
    • 
+  

+
+
New naming for Core Support Files

+

+  The new Core Support Files are:
+

+
    
+  
  • core_cm#.h  (# = 0, 3, 4)
    • 
+  
  • core_cmFunc.h  (Cortex-M Core Register access functions)
    • 
+  
  • core_cmInstr.h  (Cortex-M Core instructions)
    • 
+  
  • core_cm4_simd.h (Cortex-M4 SIMD instructions)
    • 
+

+
+
Changes to version V1.20

+
+
Removed CMSIS Middelware packages

+

+  CMSIS Middleware is removed and no longer focus of CMSIS.
+

+
+
SystemFrequency renamed to SystemCoreClock

+

+  The variable name SystemCoreClock is more precise than SystemFrequency
+  because the variable holds the clock value at which the core is running.
+

+
+
Changed startup concept

+

+  The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit 
+  from main) has the weakness that it does not work for controllers which need a already 
+  configuerd clock system to configure the external memory controller.
+

+
+
Changed startup concept

+
    
+  
  • 
+    SystemInit() is called from startup file before premain.
+  
    • 
+  
  • 
+    SystemInit() configures the clock system and also configures
+    an existing external memory controller.
+  
    • 
+  
  • 
+    SystemInit() must not use global variables.
+  
    • 
+  
  • 
+    SystemCoreClock is initialized with a correct predefined value.
+  
    • 
+  
  • 
+    Additional function void SystemCoreClockUpdate (void) is provided.
    
+   SystemCoreClockUpdate() updates the variable SystemCoreClock
+   and must be called whenever the core clock is changed.
    
+   SystemCoreClockUpdate() evaluates the clock register settings and calculates
+   the current core clock.
+  
    • 
+

+      
+
+
Advanced Debug Functions

+

+  ITM communication channel is only capable for OUT direction. To allow also communication for
+  IN direction a simple concept is provided.
+

+
    
+  
  • 
+    Global variable volatile int ITM_RxBuffer used for IN data.
+  
    • 
+  
  • 
+    Function int ITM_CheckChar (void) checks if a new character is available.
+  
    • 
+  
  • 
+    Function int ITM_ReceiveChar (void) retrieves the new character.
+  
    • 
+

+
+

+  For detailed explanation see file CMSIS debug support.htm. 
+

+
+
+
Core Register Bit Definitions

+

+  Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
+  defines correspond with the Cortex-M Technical Reference Manual.  
+

+

+  e.g. SysTick structure with bit definitions
+

+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */

+
+
DoxyGen Tags

+

+  DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
+  using DoxyGen.
+

+
+
Folder Structure

+

+  The folder structure is changed to differentiate the single support packages.
+

+
+  
    
+    
  • CM0
    • 
+    
  • CM3
+       
      
+         
    • CoreSupport
      • 
+         
    • DeviceSupport
      • 
+           
        
+             
      • Vendor 
+               
          
+                 
        • Device
+                   
            
+                      
          • Startup
+                        
              
+                          
            • Toolchain
              • 
+                          
            • Toolchain
              • 
+                          
            • ...
              • 
+                        
            
+                      
            • 
+                   
          
+                 
          • 
+                 
        • Device
          • 
+                 
        • ...
          • 
+               
        
+             
        • 
+             
      • Vendor
        • 
+             
      • ...
        • 
+           
      
+         
+         
    • Example (optional)
+           
        
+             
      • Toolchain 
+               
          
+                 
        • Device
          • 
+                 
        • Device
          • 
+                 
        • ...
          • 
+               
        
+             
        • 
+             
      • Toolchain
        • 
+             
      • ...
        • 
+           
      
+         
      • 
+       
    
+    
    • 
+     
+    
  • Documentation
    • 
+  

+
+
Open Points

+

+  Following points need to be clarified and solved:
+

+
    
+  
  • 
+    
    
+      Equivalent C and Assembler startup files.
+    
    
+    
    
+      Is there a need for having C startup files although assembler startup files are
+      very efficient and do not need to be changed?
+    
    
+  
    • 
+  
  • 
+    
    
+      Placing of HEAP in external RAM.
+    
    
+    
    
+      It must be possible to place HEAP in external RAM if the device supports an 
+      external memory controller.
+    
    
+  
    • 
+  
  • 
+    
    
+      Placing of STACK /HEAP.
+    
    
+    
    
+      STACK should always be placed at the end of internal RAM.
+    
    
+    
    
+      If HEAP is placed in internal RAM than it should be placed after RW ZI section.
+    
    
+  
    • 
+

+
+
+
Limitations

+

+  The following limitations are not covered with the current CMSIS version:
+

+
    
+ 
  • 
+  No C startup files are available. 
+ 
    • 
+

+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_Logo_Final.jpg b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_Logo_Final.jpg
new file mode 100644
index 0000000..e045601
Binary files /dev/null and b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_Logo_Final.jpg differ
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_System_View_Description.htm b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_System_View_Description.htm
new file mode 100644
index 0000000..d47878e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/CMSIS_System_View_Description.htm
@@ -0,0 +1,1157 @@
+
+
+  
+  CMSIS - SVD: Cortex Microcontroller Software Interface Standard - System View Description
+  
+  
+	
+
+
+
+
Cortex Microcontroller Software Interface Standard

+System View Description

+
+
This file describes the Cortex Microcontroller Software 
+Interface Standard - System View Description (CMSIS - SVD) concept and syntax.

+
Version: 1.02 - 27. July 2011

+
+
Information in this file, the accompany manuals, and software is

+                 Copyright © ARM Ltd.
All rights reserved.
+

+
+

+
+
Revision History

+
    
+	
  • Version 0.91: initial proposal.
    • 
+	
  • Version 0.92: revised proposal considering forum feedback (e.g. consider 
+	IP-XACT constructs and naming scheme)
    • 
+	
  • Version 1.0: new elements: peripheral version, vendor specific 
+	extension section, interrupt mapping information, global peripheral disable 
+	condition, naming of register arrays, enhanced naming schemes, etc.
    • 
+	
  • Version 1.0: SVD versioning and updated schema file
    • 
+	
  • Version 1.01: Error corrections in the example code. "include" has been removed. Restricted to one device per file.
    • 
+	
  • Version 1.02: Adding the use case of device header file generation.
    • 
+

+
+
 

+
+

+
+
Contents

+
+
    
+  
  1. About
    2. 
+  
  2. Motivation
    3. 
+  
  3. Requirements
    4. 
+  
  4. Format
    5. 
+  
  5. Example
    6. 
+  
  6. Questions & Answers
    7. 
+

+
+
About

+
+

+  The Cortex Microcontroller Software Interface Standard - System View 
+	Description (CMSIS - SVD) answers the challenges
+  of accurate, detailed and timely device aware peripheral debugging support for Cortex 
+	Microcontroller based devices by the software development 
+	tools vendor community.
+

+

+  Silicon vendors shall create and maintain a formalized description of the 
+	debug view for all the peripherals contained in their Cortex 
+	Microcontroller based devices. Tool vendors use such descriptions to 
+	establish device specific debug support in their debugging tools with minimal turn around times and 
+	manageable effort. Device support across many development tools  is 
+	essential for silicon provider in order to promote new devices and device 
+	variants entering the market. Device aware debug views provide fast and 
+	convenient access to all registers and fields as well as a detailed 
+	description. This enables software developer to 
+	develop and debug code most efficiently and adopt new devices early and 
+	quickly.

+

+  A standardized System View Description shall provide a common approach to 
+	capturing peripheral debug related information in a machine readable files. 
+	The scope of the contained information is agreed to match the level usually 
+	provided by silicon vendors in their device reference manuals, however in a 
+	formalized XML based format. There 
+	are other description languages already available. IP-XACT from the SPIRIT 
+	consortium is a prominent example. IP-XACT covers the register description 
+	sufficiently, however it comprises many other aspects of the devices like 
+	ports, bus-protocols, modeling, tool flows, etc. making a direct use of 
+	IP-XACT too complex. The design of the SVD language is 
+	taking some guidance from IP-XACT thus allowing straight forward conversion 
+	from IP-XACT to CMSIS-SVD where IP-XACT device information is already 
+	available.

+

+  In a second step the CMSIS-SVD description shall be used for automatically 
+	generating CMSIS compliant a device header file. This enables the 
+	information in the header file to be consistent with what the debugger will 
+	display and CMSIS compliant by construction. The header file generation will 
+	require some additional pieces of information and therefore a future version 
+	of the description will need to include some extensions for this purpose.

+

+  Device aware debugging support is only one aspect of device 
+	support essential to software development environments, however it is one of 
+	the most time consuming and error prone ones.

+
Motivation

+

+
+The software developer of microcontroller devices is faced with a growing number 
+of devices with an ever increasing number of peripheral blocks providing a wide 
+range of distinct and complex functionality. The development of drivers for 
+these peripherals is in the critical path of every project. Modern debuggers are supporting the software developer in getting the 
+software to run according to the requirements. A debugger providing peripheral awareness improves the 
+ability to access and interpret complex configuration and status information of 
+peripherals. Even though this is only one aspect of device support within microcontroller 
+development environments it is essential for the successful and timely adoption 
+of development tools and the device by the market.

+
Today software development environments address device aware 
+debugging in various ways. They either use documents or proprietary file formats 
+as input for providing peripheral views in the debuggers. 
+Extracting peripheral information from written documentation is a very time 
+consuming, tedious and error prone task. Having a file containing peripheral specific information to generate peripheral views 
+is going to make device support more affordable, reliable and timely. 
+The challenge for the tool providers is the support of many 
+different and incompatible file formats from a growing number of silicon vendors. 
+For silicon vendors it is time consuming and costly to engage with many tool 
+provider in order to achieve device support in a wide range of development 
+environments.

+
Standardizing on a System View Description aims to ease this challenge 
+by agreeing on a formal XML-based file format. In conjunction with supporting web server infrastructure silicon partner 
+shall upload and maintain such descriptions in a tool vendor agnostic device 
+database, hosted e.g. by the web server infrastructure 
+
+cmsis.arm.com . Access control to sensitive information is managed on a per user 
+basis. This allows silicon vendors to upload information for devices that have 
+not been made public.  

+
Such an approach provides benefits for silicon and tool vendors as well as 
+software developers of Cortex-M based microcontroller devices

+
    
+  
  • timely and accurate device support provided by a whole range of tool providers 
    • 
+	
  • tool providers become more efficient in supporting a multitude of devices 
+	and device variants
    • 
+	
  • less interaction required between silicon vendors and the  
+	tool providers
    • 
+	
  • silicon provider has control over and maintains the System View 
+	Description during the life cycle of the device
    • 
+	
  • high quality device support in terms of completeness and correctness of 
+	device aware debugging
    • 
+	
  • improved productivity and user experience for the software developer
    • 
+

+
Requirements

+
The debug description shall capture the information about all 
+the peripherals contained in a specific device. This section describes which 
+items of information are deemed relevant for a debugger. Silicon vendors are expected to 
+provide the System View Description for their devices, matching the information 
+contained in device reference manuals. The System View Description shall be suitable for straight forward 
+generation from existing databases like IP-XACT descriptions or SIDSC. The size 
+of device description is a concern and therefore redundancy in the description 
+shall be avoided. The size of SVD files affects the efficiency of 
+distribution as well as the loading time by the development tools. Last but not least manual editing of SVD files shall be possible for 
+the purpose of customization by SW developers.

+
Required content of the description

+
From a programmer's perspective a peripheral can be seen as a set of registers 
+with unique names being mapped to fixed addresses allocated 
+within a defined range of an address space.

+
From a debugger's point of view read accesses to a physical register need to be 
+executed in order to display its current value. The debugger executes a write 
+access to a register when a user edits its value. For this purpose the debugger 
+needs to know about the following additional attributes: 

+
    
+				
  • minimal addressable unit = smallest series of bits 
+				identified by a unique address (e.g. byte-addressable memory) 
    • 
+				
  • register size = number of bits forming a register (ARM Cortex-M usually 
+				32 bits)
    • 
+				
  • access permission = read and write, read only, 
+				write only
    • 
+				
  • access side effects = accesses by the debugger must 
+				be avoided if it has side effects. Some side effects may be 
+				reversed by the debugger to compensate for the side effect
    • 
+

+
In many cases peripheral registers are partitioned into chunks of bits of 
+distinct functionality. In this document these chunks are referred to as 
+field. Each 
+register that consists of fields shall  be described by a list 
+of uniquely named fields (Note: field names are not required to be 
+unique across registers). In order for a debugger to extract the 
+value of a field from the corresponding register the following attributes are required:

+
    
+				
  • most significant bit = highest bit position of the 
+				bit-field in the corresponding register
    • 
+				
  • least significant bit = lowest bit position of the 
+				bit-field within the corresponding register
    • 
+				
  • access permission = read and write, read only, 
+				write only
    • 
+

+
An enumerated value maps a number to a specific descriptive string 
+representing the semantics of the value of a field. The debugger displays the 
+descriptive string rather than the number to simplify the access to the 
+information thus 
+avoiding the necessity of a look-up in the device reference manual. Each item of 
+an enumerated value has the following attributes:

+
    
+				
  • value = value of the bit-field that corresponds to 
+				the string attribute
    • 
+				
  • name = short string that describes the semantics of a 
+				field when the corresponding value is set
    • 
+				
  • description = detailed description of the semantics 
+				of the field when the corresponding value is set
    • 
+

+
The hierarchical structure of the description looks like this:

+
Device =

+
    
+	
  • 
+		
     Peripherals
    
+		
      
+						
    • 
+						
      Peripheral
      
+						
        
+										
      • 
+										
        Registers
        
+										
          
+														
        • 
+														
          
+														Register
          
+														
            
+																		
          • 
+																		
            
+																		Fields
            
+																		
              
+																						
            • 
+																						
              Field
              
+																						
                
+																										
              • 
+																										
                Enumerated Values
                
+																										
                  
+																														
                • 
+																														
                  Enumerated Value
                  
+																														
                  • 
+																										
                
+																										
                • 
+																						
              
+																						
              • 
+																		
            
+																		
            • 
+														
          
+														
          • 
+										
        
+										
        • 
+						
      
+						
      • 
+		
    
+	
    • 
+

+
+
One file can only contain a description for a single device or device family 
+sharing the identical description. Devices consists of a one or more peripherals. 
+Each peripheral contains 
+one or more registers, where each register may consist of one or more fields. 
+The values of a field maybe represented through descriptive strings and detailed 
+descriptions, the enumerated values.

+
In many cases there are multiple 
+instances of the same peripheral in a device (e.g. Timer0, Timer1, etc.). For 
+this reason the description has the concept of deriving a peripheral from a peripheral 
+that has already been described. The attribute derivedFrom specifies 
+such a relationship. 
+Similarly registers or fields can be reused within the device description. The 
+grouping of  peripherals providing 
+similar functionality (e.g. Simple Timer, Complex Timer) is controlled via the element groupName. 
+All peripherals associated with the same group name are collectively listed under this group 
+in the order they have been specified in the file. 
+Collecting  
+similar or related peripherals into peripheral groups helps structuring the list 
+of peripherals e.g. in a drop down menu (tool dependent). Devices with a large 
+set of peripherals will benefit from this additional level of structure.

+
Each of the items (i.e. Device, Peripheral, Register and 
+Field) owns an description element containing verbose information about 
+the respective element. The description field plays 
+an important part in improving the software development productivity. Instead of 
+searching through the reference manual the detailed explanation from the manual 
+could become immediately accessible from within the development environment.

+
Details about the exact display format and layout of the peripheral view are 
+considered beyond the scope of the description. It is up to the tool vendor to 
+visualize the contained information appropriately. The  
+silicon vendor provides details about the device's peripherals that is commonly available. 

+
System View Description files need to be validated for:

+
    
+				
  1. syntactical correctness using XML-Schema checking utilities
    2. 
+				
  2. consistency  of the provided information (e.g. multiple registers mapped to the same address, 
+				all registers located within the specified address ranges of a 
+				peripheral, all fields are within the range of the register 
+				size, etc.) by a utility developed by ARM (SVDConv.exe)
    3. 
+				
  3.  semantical correctness of the System View Description 
+				against the silicon specification executed by the silicon vendor
    4. 
+

+
The SVD description format was extended by numerous elements during the 
+review period targeting version 1.0 and new extensions are expected for future 
+versions of this format. A new section named "vendorExtensions" has been added 
+to the end of the top level to allow silicon vendors and tool partners to 
+innovate and expand the description in order to overcome limitations of the 
+current specification until these can be incorporated into new versions of 
+CMSIS-SVD. 

+

+
+
 Format

+
+

+  The following section describes the SVD file format in detail. Each subsection 
+	defines a single hierarchy level of the description and lists all mandatory 
+	and optional language elements for that specific level including type 
+	information for each element. Each element is discussed in more detail and a 
+	brief snippet is provided as an example. The sequence of elements shown 
+	below is binding. Optional elements are highlighted in green, blue elements 
+	are mandatory unless they have been already specified globally on a higher 
+	level.

+

+  An XML-schema file is provided alongside this document for syntactical 
+	checking of descriptions being developed.

+
<device schemaVersion="xs:decimal" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">

+
   <name>xs:Name</name>

+   <version>xs:string</version>

+   <description>xs:string</description>

+   <addressUnitBits>scaledNonNegativeInteger</addressUnitBits>

+   <width>scaledNonNegativeInteger </width>

+

+   <size>scaledNonNegativeInteger</size>

+   <access>accessType</access>

+   <resetValue>scaledNonNegativeInteger</resetValue>

+   <resetMask>scaledNonNegativeInteger</resetMask>

+
   <peripherals>

+      ...

+   </peripherals>

+   <vendorExtensions>

+      ...

+    </vendorExtensions>

+
</device>

+
The device provides the outermost frame of the description. All other 
+elements like peripherals, registers and fields are described inside of this scope. A device contains one or more peripherals.
+The optional elements size, access, resetValue and resetMask are used as default values throughout the 
+device description unless they get overruled on a lower level of the description 
+(e.g. peripheral or register).

+
Mandatory items:

+
name = the unique name string is used to identify the device. 
+All devices of a silicon vendor are required to have a unique name. In case an 
+SVD description covers a family or series of devices, the name of the series or 
+family is placed here. The device names of the members of the series or family 
+are listed in <memberDevices>

+
description = string describing main features of a device 
+(e.g. CPU, clock frequency, peripheral overview, etc.)

+
version = the string is defining the version of the 
+description for this device. Silicon vendors will maintain the description 
+throughout the lifecycle of the device and need to ensure that all updated and 
+released copies have a unique version string indicating the order in which. Note: this must not be used for 
+detailing the version of the device.

+
 

+
addressUnitBits = defines the number of data bits for each address 
+increment. The value for Cortex-M based devices is  8 (byte-addressable).

+
width = defines the number of bits for the maximum single 
+transfer size allowed by the bus interface hence the maximum size of a single 
+register that can be defined for the address space. This information is relevant 
+for debuggers when determining the size of debug transfers. The expected value 
+for Cortex-M based devices is 32.

+
peripherals = next level of description (see next section 
+for details)

+
Optional Items:

+
size = defines the default bit-width of registers contained 
+in the device. This element can be overruled by re-specifying the size element on a lower level of the 
+description.

+
access = defines the default access permissions for all 
+registers in the device. The allowed tokens are:

+  - read-only: read access is permitted. Write operations have an undefined 
+result.

+  - write-only: write access is permitted. Read operations have an 
+undefined result. 

+  -read-write: both read and write accesses are permitted. Writes affect 
+the state of the register and reads return a value related to the register

+  -writeOnce: only the first write after reset has an effect on the 
+register. Read operations deliver undefined results

+  -read-writeOnce: Read operations deliver a result related to the register 
+content. Only the first write access to this register after a reset will have an 
+effect on the register content.

+
resetValue = defines the default value of all registers 
+after a reset. There are scenarios where SW developers need to know, what the 
+reset value of a register or field is. Even though listed as optional on this 
+level of the description, silicon vendors should ensure that this information is 
+provided for all registers. 

+
resetMask = defines those bit positions set to one to be 
+taken from resetValue element. All other elements are undefined. If a register 
+does not have a defined reset value the resetMask needs to be set to 0.

+
vendorExtensions = the content and format of this section of 
+the description is unspecified. Silicon vendors may choose to provide additional 
+information. The assumption is that by default this section is completely 
+ignored by the debugger. It is up to the silicon vendor to specify the content 
+of this section and share the specification with the tool vendors. The new 
+elements shall be considered for a future version of the description format.

+
Example:

+
<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
+  <name>CMSIS_Cortex-M3</name>
+  <version>0.1</version>
+  <description>ARM Cortex-M3 based Microcontroller demonstration device</description>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <size>32</size>
+  <access>read-write</access>
+  <resetValue>0</resetValue>
+  <resetMask>0xffffffff</resetMask>

+
  <peripherals>
+    ...
+  </peripherals>
+</device>

+
The device description above is at version 0.1 and uniquely identifies the 
+device by the name "CMSIS_Cortex-M3". The peripherals are memory mapped in a 
+byte-addressable address space with a bus width of 32 bits. The default size of 
+the registers contained in the peripherals is set to 32 bits. Unless redefined 
+for specific peripherals, registers or fields all registers are read-write 
+accessible. A reset value of 0 valid for all 32 bits as specified by the reset 
+mask is set for all registers unless overruled at a lower level of the description.

+

+
<peripherals>

+
   <peripheral>

+     ...

+   </peripheral>

+
     ...

+
   <peripheral>

+     ...

+   </peripheral>

+
</peripherals>

+
This construct sets the frame for all peripherals and peripheral groups contained in a device. This 
+creates a container element which ease-up processing with languages like Java.

+

+
<peripheral derivedFrom="xs:Name">

+
   <name>xs:Name</name>

+   <version>xs:string</name>

+   <description>xs:string </description>

+   <groupName>xs:string</groupName>

+   <prependToName>xs:string</prependToName>

+   <appendToName>xs:string</appendToName>

+   <disableCondition>xs:string</disableCondition>

+   <baseAddress>scaledNonNegativeInteger</baseAddress>

+   <size>scaledNonNegativeInteger</size>

+   <access>accessType</access>

+   <resetValue>scaledNonNegativeInteger</resetValue>

+   <resetMask>scaledNonNegativeInteger</resetMask>

+
   <addressBlock>

+      <offset>scaledNonNegativeInteger</offset>

+      <size>scaledNonNegativeInteger</size>

+      <usage>usageType</usage>

+   </addressBlock>

+   ...

+  <addressBlock>

+      <offset>scaledNonNegativeInteger</offset>

+      <size>scaledNonNegativeInteger</size>

+      <usage>usageType</usage>

+   </addressBlock>

+   <interrupt>

+      <name>xs:string</name>

+      <value>scaledNonNegativeInteger</value>

+   </interrupt>

+   <registers>

+   ...

+   </registers>

+
</peripheral>

+
A peripheral encloses the description of one or more registers belonging to 
+this named peripheral. The address range allocated in the address space for this 
+peripheral is defined through one or more address ranges. An address range is 
+specified relative to the base address of the peripheral. This information 
+allows to display a memory map overview for all peripherals. Please note that 
+such a memory map does not contain any information for memories and unoccupied 
+address ranges.

+
Mandatory items:

+
name = name string used to identify the peripheral. Peripheral 
+names are required to be unique within the scope of a device.

+
baseAddress = lowest address reserved or used by the peripheral

+
description = string providing an overview of the purpose 
+and functionality of the peripheral

+
addressBlock = a peripheral may occupy one or more disparate 
+blocks in the address space. An addressBlock is a complex element consisting of 
+the mandatory elements:

+    offset: specifying the start address of an address block. It 
+is calculated from the sum of baseAddress and offset

+    size: specifying the number of addressUnitBits being covered 
+by this address block. The end address of an address block is the sum of start 
+address and the size - 1.

+    usage: the usage element is of usageType specifying 
+if the addresses within the specified address block is used for 
+registers or buffer or is reserved. 
+

+Note: registers must not be allocated 
+to an address within a reserved or buffer address range.

+
registers = next lower level of description (see next section 
+for details)

+
Optional items:

+
derivedFrom = this attribute specifies the name of a peripheral 
+that has already been described for this device. The description of that device 
+will be copied. It is mandatory to overwrite the name as well as the 
+addressOffset. All other specified information will overwrite the respective 
+elements in the copy.

+
version = the string specifies the version of this 
+peripheral description.

+
disableCondition = C language compliant logical expression 
+resulting in a true or false result. If "true" the refresh of the display 
+for this peripheral is disabled 
+and related accesses by the debugger are suppressed. Only constants and references to other registers 
+contained in the description are allowed:  
+<peripheral>-><register>-><field> (e.g.: (System->ClockControl->apbEnable == 0)). 
+Only the following operators are allowed [&&,||, ==, !=, >>, <<, &, |]. Warning! 
+This feature must only be use in case accesses from the debugger to registers of 
+un-clocked peripherals result in severe debugging failures. SVD is intended to 
+be fully static information and not include any run-time computation or 
+functions such capabilities may be added by the tools but is considered beyond 
+the scope of this description language.

+
prependToName = all register names of this peripheral have 
+their names prepended with the string specified

+
appendToName = all register names of this peripheral have 
+their names appended with the string specified

+
size = defines the default bit-width of registers contained 
+in the device. This element can be overruled by re-specifying the size element on a lower level of the 
+description.

+
access = defines the default access permissions for all 
+registers in the peripheral. The value can be reset on a lower level of the 
+description. The allowed tokens are:

+  - read-only: read access is permitted. Write operations have an undefined 
+result.

+  - write-only: write access is permitted. Read operations have an 
+undefined result. 

+  -read-write: both read and write accesses are permitted. Writes affect 
+the state of the register and reads return a value related to the register

+  -writeOnce: only the first write after reset has an effect on the 
+register. Read operations deliver undefined results

+  -read-writeOnce: Read operations deliver a result related to the register 
+content. Only the first write access to this register after a reset will have an 
+effect on the register content.

+
resetValue = defines the default value of all registers 
+after a reset but can be set for individual registers and fields on a lower 
+level of the description.

+
resetMask = defines those bit positions set to one to be 
+taken from resetValue element. All other elements are undefined. This is the 
+default value for the whole peripheral but can be readjusted on lower levels. If 
+a register does not have a defined reset value the resetMask needs to be set to 
+0.

+
interrupt = is a complex type that consists of the name of 
+the interrupt and the associated enumeration value. A peripheral can also have 
+multiple associated interrupts. This entry is mainly intended for information 
+only purposes in order to display the interrupts and respective interrupt 
+numbers associated with a peripheral.

+
Example:

+
... 
+    <peripheral>
+       <name>Timer0</name>
+       <version>1.0.32</version>
+       <description>Timer 0 is a simple 16 bit timer counting down ... </description>
+       <baseAddress>0x40000000</baseAddress>
+       <addressBlock>
+         <offset>0x0</offset>
+         <size>0x400</size>
+         <usage>registers</usage>
+       </addressBlock>
+       <interrupt><name>TIM0_INT</name><value>34</value></interrupt>
+       <registers>
+         ...
+       </registers>
+    </peripheral>
+    <peripheral derivedFrom="Timer0">
+      <name>Timer1</name>
+      <baseAddress>0x40000400</baseAddress>
+    </peripheral>
+
+...

+

+
<registers> ... </registers>

+
This construct sets the frame for all registers contained in a peripheral. 
+This creates container elements which ease-up processing with languages like Java.

+

+
<register derivedFrom=xs:Name>

+
   <dim>scaledNonNegativeInteger</dim>

+   <dimIncrement>scaledNonNegativeInteger</dimIncrement>

+   <dimIndex>xs:string</dimIndex>

+   <name>xs:Name</name>

+   <displayName>xs:string</displayName>

+   <description>xs:string</description>

+   <alternateGroup>xs:Name</alternateGroup>

+   <addressOffset>scaledNonNegativeInteger 
+</addressOffset>

+    <size>scaledNonNegativeInteger</size>

+   <access>accessType</access>

+   <resetValue>scaledNonNegativeInteger</resetValue>

+   <resetMask>scaledNonNegativeInteger</resetMask>

+
+   <modifiedWriteValues>writeValueType</modifiedWriteValues>

+   <writeConstraint>writeConstraintType</writeConstraint>

+   <readAction>readActionType </readAction>

+   <fields>

+      ...

+   </fields> 

+
</register>

+
The definition of registers is the central part of the description. A 
+register may use its complete size for a single purpose and therefore not 
+consist of fields. Otherwise the description 
+of fields is mandatory.

+
Mandatory items:

+

+
name = name string used to identify the register. Register 
+names are required to be unique within the scope of a peripheral.

+
description = string describing the details of the register.

+
addressOffset = value defining the address of the register relative to 
+the baseAddress defined by the peripheral the register belongs to.

+

+
The following elements can be omitted if the corresponding value has been set 
+on a higher level of the description and matches the value required for this register:

+
size =value defining the bit-width of the register

+
access = predefined tokens: read-only, write-only, read-write, 
+writeOnce, read-writeOnce strings defining the allowed 
+accesses for this register.

+
resetValue = element defining the value of the register 
+immediately after a reset.

+
resetMask= element specifying those bits of the resetValue that 
+are defined (bit positions containing a 0 bit are ignored, bit 
+positions containing a 1 bit are taken from the corresponding bit position of 
+the resetValue). If a register does not have a defined reset value the resetMask 
+needs to be set to 0.

+
Optional items:

+
dim = if this field is specified the value defines the 
+number of elements in an array of registers.

+
dimIncrement = if dim is specified this element becomes 
+mandatory and specifies the address increment in between 
+two neighboring registers of the register array in the address map.

+
dimIndex = this element specifies the substrings within the 
+register array names that will replace the %s within the register name. By 
+default the index is a decimal value starting with 0 for the first register. 
+Examples:

+   <dim>6</dim> <dimIncrement>4</dimIncrement> <dimIndex>A,B,C,D,E,Z</dimIndex> 
+<name>GPIO_%s_CTRL</name> ...

+   => GPIO_A_CTRL, GPIO_B_CTRL, GPIO_C_CTRL, GPIO_D_CTRL, GPIO_E_CTRL, 
+GPIO_Z_CTRL

+   <dim>4</dim> <dimIncrement>4</dimIncrement> <dimIndex>3-6</dimIndex> 
+<name>IRQ%s</name> ... 

+   => IRQ3, IRQ4, IRQ5, IRQ6                  

+
displayName = when used, this is the string being used by a 
+graphical frontend to visualize the register otherwise the name element is used. 
+Note: the display name may contain special characters and white spaces. It also 
+uses "%s" as the place holder for the dimIndex substring.

+
alternateGroup = when used, this element specifies a name of 
+a group that all alternate register with the same name a associated with. At the 
+same time it indicates that there is a register description allocating the same 
+absolute address in the address space. 

+
modifiedWriteValues = element to describe the manipulation of 
+data written to a register. If not specified the value written to the field is the 
+value stored in the field. The other options are bitwise operations: 

+  oneToClear: write data bits of one shall clear (set to zero) the 
+corresponding bit in the register

+  oneToSet: write data bits of one shall set (set to one) the 
+corresponding bit in the register

+  oneToToggle: write data bits of one shall toggle (invert) the 
+corresponding bit in the register

+  zeroToClear: write data bits of zero shall clear (set to zero) 
+the corresponding bit in the register

+  zeroToSet: write data bits of zero shall set (set to one) the 
+corresponding bit in the register

+  zeroToToggle: write data bits of zero shall toggle (invert) the 
+corresponding bit in the register

+  clear: after a write operation all bits in the field are cleared (set to 
+zero)

+  set: after a write operation all bits in the field are set (set to one)

+  modify: after a write operation all bit in the field may be modified 
+(default)

+
writeConstraint: has a set of options:

+  writeAsRead = if true only the last read value can be written

+  useEnumeratedValues = if true only those values listed in the 
+enumeratedValues list are considered valid write values

+  minimum = specifies the smallest number to be written to the 
+register

+  maximum = specifies the largest number to be written to the 
+register

+
readAction: if set it specifies the side effect following 
+read operations. If not set the register is not modified following a read 
+operations. The defined side effects are:

+  clear: indicates that the register is cleared (set to zero) 
+following a read operation

+  set: indicates that the register is set (set to ones) following a 
+read operation

+  modify: indicates that the register is modified in some way 
+after a read operation

+  modifyExternal: indicates that one or more dependent resources 
+other than the current register 
+are immediately affected by a read (it is recommended that the register 
+description specifies these dependencies). Debuggers are not expected to read 
+this register location unless explicitly instructed by user.

+
fields = next lower level of description (see next section 
+for details).

+
Optional attribute:

+
derivedFrom = specifies the name of the register to be 
+replicated. Elements being specified underneath will override the values specified 
+from the register being derived from. Note that it is mandatory to overwrite at 
+least name and addressOffset.

+
Example:

+
... 
+       <register>
+         <name>TimerCtrl0</name>
+         <description>Timer Control Register</description>
+         <addressOffset>0x0</addressOffset>
+         <access>read-write</access>
+         <resetValue>0x00008001</resetValue>
+         <resetMask>0x0000ffff</resetMask>
+         <size>32<size>
+         <fields>
+           ...
+         </fields>
+       </register>
+       <register derivedFrom="TimerCtrl0">
+         <name>TimerCtrl1</name>
+         <addressOffset>0x4<addressOffset>
+       </register>
+...

+

+
<fields> ... </fields>

+
This construct sets the frame for all fields contained in a register. 
+This creates container elements which ease-up processing with languages like Java.

+

+
 <field derivedFrom="xs:Name">

+
   <name>xs:Name</name>

+   <description>xs:string</description>

+   
+<bitOffset>scaledNonNegativeInteger</bitOffset>
+<bitWidth>scaledNonNegativeInteger</bitWidth>

+   or

+   <lsb>scaledNonNegativeInteger</lsb> <msb>scaledNonNegativeInteger</msb>

+   or

+   <bitRange>pattern</bitRange>

+   <access>accessType</access>

+   <modifiedWriteValues>writeValueType</modifiedWriteValues>

+   <writeConstraint>writeConstraintType</writeConstraint>

+   <readAction>readActionType </readAction>

+   <enumeratedValues>

+      ...

+   </enumeratedValues>

+
</field>

+
A bit-field has a name that is unique for the register it belongs to. The 
+position and size within the register is either described by the combination of 
+the least significant bit's position (lsb) and the most significant bit's 
+position (msb) or the lsb and the size, specifying the bit-width of the 
+field.  A field may define an enumeratedValue in order to make the display 
+more intuitive to read. 

+
Mandatory items:

+
name = name string used to identify the field. Field names 
+are required to be unique within the scope of a register.

+

+
description = string describing the details of the register.

+

+
There are 3 ways to describe a field to be used mutually exclusive:

+a) specifying bitOffset and bitWidth (IP-XACT like)

+b) specifying lsb and msb of the field.

+c) specifying a bit range in the format "[<msb>:<lsb>]"

+
bitOffset = value defining the position of the least significant bit 
+of the field within the register it belongs to.

+bitWidth = value defining the bit-width of the bitfield within the 
+register it belongs to.

+

+

+lsb = value defining the bit position of the least significant 
+bit within the register it belongs to.

+msb = value defining the bit position of the most significant 
+bit within the register it belongs to. 
+

+
bitRange = a string in the format: [<msb>:<lsb>]

+

+
Optional items:

+
derivedFrom = the field is cloned 
+from a previously defined field with a unique name.

+
access = predefined strings defining the allowed 
+accesses for this register: read-only, write-only, read-write, writeOnce, 
+read-writeOnce. Can be omitted if it matches the access permission set for the parent register.

+
enumeratedValues = next lower level of description (see next section 
+for details)

+
modifiedWriteValues = element to describe the manipulation of 
+data written to a field. If not specified the value written to the field is the 
+value stored in the field. The other options are bitwise operations: 

+  oneToClear: write data bit of one shall clear (set to zero) the 
+corresponding bit in the field

+  oneToSet: write data bit of one shall set (set to one) the corresponding 
+bit in the field

+  oneToToggle: write data bit of one shall toggle (invert) the 
+corresponding bit in the field

+  zeroToClear: write data bit of zero shall clear (set to zero) the 
+corresponding bit in the field

+  zeroToSet: write data bit of zero shall set (set to one) the 
+corresponding bit in the field

+  zeroToToggle: write data bit of zero shall toggle (invert) the 
+corresponding bit in the field

+  clear: after a write operation all bits in the field are cleared (set to 
+zero)

+  set: after a write operation all bits in the field are set (set to one)

+  modify: after a write operation all bit in the field may be modified 
+(default)

+
writeConstraint: has a set of options:

+  writeAsRead = if true only the last read value can be written

+  useEnumeratedValues = if true only those values listed in the 
+enumeratedValues list are considered valid write values

+  minimum = specifies the smallest number to be written to the field

+  maximum = specifies the largest number to be written to the field

+
readAction: if set it specifies the side effect following 
+read operations. If not set the field is not modified following a read 
+operations. The defined side effects are:

+  clear: indicates that the field is cleared (set to zero) 
+following a read operation

+  set: indicates that the field is set (set to ones) following a 
+read operation

+  modify: indicates that the field is modified in some way after a 
+read operation 
+

+  modifyExternal: indicates that one or more dependent resources 
+other than this field are immediately affected by a read (it is recommended that 
+the field description specifies these dependencies). Debuggers are not expected 
+to read the field unless explicitly instructed by user.

+
Example:

+
...
+         <field>
+           <name>TimerCtrl0_IntSel</name>
+           <description>Select interrupt line that is triggered by timer overflow.</description>
+	   <bitOffset>1</bitOffset>
+           <bitWidth>3</bitWidth>
+           <access>read-write</access>
+	   <resetValue>0x0</resetValue>
+           <modifiedWriteValues>oneToSet</modifiedWriteValues>
+           <writeConstraint>
+              <range>
+                <minimum>0</minimum>
+                <maximum>5</maximum>
+              </range>
+           </writeConstraint>
+           <readAction>clear</readAction>
+ 
+           <enumeratedValues>
+              ...
+           </enumeratedValues>
+         </field>
+...

+

+
<enumeratedValues 
+derivedFrom="xs:Name">

+
   <name>xs:Name</name>

+   <usage>usageType</usage>

+   <enumeratedValue>

+      ...

+   </enumeratedValue>

+
      ... 

+
   <enumeratedValue>

+      ...

+   </enumeratedValue>

+
</enumeratedValues>

+
An enumerated value provides one or more enumeration items (enumeratedValue), defining a map 
+between all possible values of the bit-field it belongs to and the corresponding 
+human readable semantics of that value.

+
Mandatory items:

+enumeratedValue = next lower level of description (see next section 
+for details)

+
Optional items:

+derivedFrom = the enumeratedValues can be copied or derived 
+from a previously defined enumeratedValue that has been given a unique name.

+name = name string to identify an enumeratedValue. Named 
+enumeratedValues need to be unique in the scope of a device in order to be reusable 
+throughout the description of a device.

+usage = possible values are read, write or
+read-write. This allows to specify two different enumerated values 
+depending whether it is to be used for a read or a write access. If not specified the enueratedValues are valid for read and write.

+
Example:

+
...
+           <enumeratedValues>
+              <name>TimerIntSelect</name>
+              <usage>read-write</usage>
+              <enumeratedValue>
+                <name>disabled</name>
+                <description>disabled bit</description>
+                <value>0</value>
+              </enumeratedValue>
+              ...
+              <enumeratedValue>
+                <name>reserved</name>
+	        <description>reserved values. Do not use</description>
+                <isDefault>true</isDefault>
+              </enumeratedValue>
+           </enumeratedValues>
+...

+

+
<enumeratedValue>

+
   <name>xs:name</name>

+   <description>xs:string</description>

+   <value>scaledNonNegativeInteger</value>

+  
+or

+   <isDefault>xs:boolean</isDefault>

+

+
</enumeratedValue>

+
An enumeratedValue defines a map between a value and the string reading the 
+corresponding human readable semantics for that value in a brief and a detailed 
+version

+
Mandatory items:

+
name= brief string verbally describing the semantics of the value 
+defined for this enumeratedValue. E.g. used for display in visualization of a bit-field 
+instead of the value.

+

+value = defines the constant of the bit-field that the name 
+corresponds to.

+
isDefault = defines the name and description for all other 
+values that are not explicitly listed

+
Optional item:

+
description = extended string verbally describing the semantics 
+of the value defined for this enumeratedValue in full detail.

+
Example:

+
...
+         <enumeratedValue>
+            <name>disabled</name>
+            <description>Timer does not generate interrupts</description>
+            <value>0</value>
+         </enumeratedValue>
+         ...
+         <enumeratedValue>
+            <name>enabled</name>
+            <description>Timer does not generate interrupts</description>
+            <isDefault>true</isDefault>
+         </enumeratedValue>
+
+...

+

+
Names

+
Names shall comply with ANSI C variable naming restrictions.

+
Constants

+
Number constants shall be entered in hexadecimal, decimal or binary format.

+
    
+				
  • hexadecimal is indicated by a leading "0x"
    • 
+				
  • binary format is indicated by a leading  "#"
    • 
+				
  • all other formats are interpreted as decimal numbers
    • 
+				
  • the value tag in enumeratedValue accepts do not care bits 
+				represented by "x"
    • 
+

+
Comments 

+
Comments have the standard XML format "<!--" starts a comment
+	"-->" terminates a comment

+
Example

+
+<?xml version="1.0" encoding="utf-8"?>
+ 
+<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
+  <name>Cortex_M3_Sample</name>
+  <version>0.1</version>
+  <description>ARM Cortex-M3 based Microcontroller dummy device</description>
+  <!-- Bus Interface Properties -->
+  <!-- Cortex-M3 is byte addressable -->
+  <addressUnitBits>8</addressUnitBits>
+  <!-- the maximum data bit width accessible within a single transfer is 32bits -->
+  <width>32</width>
+
+  <!-- Register Default Properties -->
+  <!-- the size of the registers is set to a bit width of 32. This can be overruled for individual peripherals and/or registers -->
+  <size>32</size>
+  <!-- the access to all registers is set to be readable and writeable. This can be overruled for individual peripherals and/or registers -->
+  <access>read-write</access>
+  <!-- for demonstration purposes the resetValue for all registers of the device is set to be 0. This can be overruled within the description -->
+  <resetValue>0</resetValue>
+  <!-- the resetMask = 0 specifies that by default no register of this device has a defined reset value -->
+  <resetMask>0</resetMask>
+
+  <peripherals>
+    <peripheral>
+      <name>Timer0</name>
+      <description>A simple 16 bit timer counting down ... </description>
+      <groupName>Timer</groupName>
+      <baseAddress>0x40000000</baseAddress>
+      <!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <addressBlock>
+        <offset>0x8</offset>
+        <size>0x3f8</size>
+        <usage>reserved</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TIM0_IRQn</name>
+        <value>34</value>
+      </interrupt>
+      <registers>
+        <register> 
+          <name>TimerCtrl0</name>
+          <!-- the display name is an unrestricted string. -->
+          <displayName>Timer Ctrl 0</displayName>
+          <description>Timer Control Register</description>
+          <addressOffset>0x0</addressOffset>
+          <!-- size=32, access=read-write, resetValue=0x0, resetMask=0xffffffff, volatile=false -->
+          <fields>
+            <field>
+              <name>TimerCtrl0_En</name>
+              <description>Enable Bit activates the timer.</description>
+              <!-- Spirit like bit range description: [0:0] -->
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <!-- Writing 1 enables, writing 0 has no effect -->
+	      <modifiedWriteValues>oneToSet</modifiedWriteValues>
+              <!-- The write constraint is defined to be that only the values provided by the enumeratedValues below are allowed -->
+              <writeConstraint>
+                <useEnumeratedValues>true</useEnumeratedValues>
+              </writeConstraint>
+              <!-- there is no side effect on reads, therefore <readAction> is not set -->
+              <!-- oneBitEnable named enumeration that can be reused in other parts of the description -->
+              <enumeratedValues>
+                <name>oneBitEnable</name>
+                <!-- the same enumerated Values are used for read and write. This default is assumed when this tag is missing -->
+                <usage>read-write</usage>
+                <enumeratedValue>
+                  <name>enabled</name>
+                  <description>Timer is enabled and active</description>
+                  <value>0x0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>disabled</name>
+                  <description>Timer is disabled and inactive</description>
+                  <value>0x1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>TimerCtrl0_Dis</name>
+              <description>Disable Bit deactivates the timer.</description>
+              <!-- Spirit like bit range description: [1:1] -->
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <!-- Writing 1 sets, writing 0 has no effect -->
+	      <modifiedWriteValues>oneToSet</modifiedWriteValues>
+              <!-- The write constraint is defined to be that only the values provided by the enumeratedValues below are allowed -->
+              <writeConstraint>
+                <useEnumeratedValues>true</useEnumeratedValues>
+              </writeConstraint>
+              <!-- there is no side effect on reads, therefore <readAction> is not set -->
+              <!-- oneBitEnable named enumeration that can be reused in other parts of the description -->
+              <enumeratedValues derivedFrom="oneBitEnable"></enumeratedValues>
+            </field>
+            <field>
+              <name>TimerCtrl0_Int</name>
+              <description>Select interrupt line that is triggered by timer overflow.</description>
+              <!-- the position of the bit field is described in the bitRange style. -->
+              <bitRange>[4:2]</bitRange>
+              <enumeratedValues>
+                <enumeratedValue>
+                  <name>disabled</name>
+                  <description>Timer does not generate interrupts</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 0</name>
+                  <description>Timer does generate interrupts on interrupt line 0</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 1</name>
+                  <description>Timer does generate interrupts on interrupt line 1</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 2</name>
+                  <description>Timer does generate interrupts on interrupt line 2</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 3</name>
+                  <description>Timer does generate interrupts on interrupt line 3</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>int 4</name>
+                  <description>Timer does generate interrupts on interrupt line 4</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <!-- this is the default element. All the valid value not listed above (6,7) have the following name and description -->
+                <enumeratedValue>
+                  <name>reserved</name>
+                  <description>Timer is configured incorrectly and the functionality is considered unpredictable</description>
+                  <isDefault>true</isDefault>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TimerCounter0</name>
+          <description>Timer0 16 Bit Counter Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>16</size>
+        </register>
+        <!-- a copy of the counter register TimerCounter0 with the name="TimerCounter1" and the addressOffset="0x8" -->
+        <register derivedFrom="TimerCounter0">
+          <name>TimerCounter1</name>
+          <addressOffset>0x6</addressOffset>
+        </register>
+        <!-- ... this is a restricted demo example and a real timer peripheral would have more register to be complete -->
+      </registers>
+    </peripheral>
+    <!-- a copy of Timer0 with the name="Timer1 and the baseAddress="0x40000400" -->
+    <peripheral derivedFrom="Timer0">
+      <name>Timer1</name>
+      <baseAddress>0x40000400</baseAddress>
+      <interrupt>
+        <name>TIM1_IRQn</name>
+        <value>35</value>
+      </interrupt>
+    </peripheral>
+  </peripherals>
+</device>

+
+
Questions & Answers

+
Is there any relation between the System View Description and the CMSIS 
+standard?

+
Initiallly there was no immediate link but both initiatives had a common goal: 
+Create a sound software development eco-system for Cortex-M based 
+Microcontroller, giving the customers the free choice of devices and software 
+development environments and all resources required for a successful product 
+development in a single location. Meanwhile we have started to generate 
+CMSIS compliant device header files from the same CMSIS-SVD description. We will 
+introduce a small number of additional description tags in the next version of 
+the specification. The benefit is the synchronization between symbols used in 
+the application and the symbols displayed by the debugger.  

+
Why does the format not provide constructs like macros and 
+conditional statements?

+
It is assumed that the description is generated from other sources and 
+therefore such concepts would only complicate the language unnecessarily. It is 
+recommended to use a standard C pre-processor to generate the debug description 
+format from a redundancy optimized description.

+
Do we need to consider endianess in the description?

+
This should be specified on a device configuration level and is not specific 
+to the visualization of peripheral details in a System View. Endianess becomes 
+relevant when using bit fields in the CMSIS compliant device header file.

+
Is the System View Description limited to Cortex-M based devices ?

+
+
+
There may have been assumptions made about the structure of the device due to 
+it being developed around a Cortex-M processor. E.g. that all peripherals are 
+assumed to be memory mapped and to reside in a single address space. It is quite 
+likely that the description format may also serve other architectures 
+sufficiently. There is no intent to limit the format to Cortex-M 
+processor based devices. 

+
+
+
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/README.txt b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/README.txt
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+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/README.txt
@@ -0,0 +1,3 @@
+
+NOTE - Open the index.html file inside the html directory to access CMSIS DSP Library documentation
+
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+CMSIS DSP Software Library: Data Structures
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+
Data Structures
  

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+

+Here are the data structures with brief descriptions:
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arm_bilinear_interp_instance_f32Instance structure for the floating-point bilinear interpolation function 
arm_bilinear_interp_instance_q15Instance structure for the Q15 bilinear interpolation function 
arm_bilinear_interp_instance_q31Instance structure for the Q31 bilinear interpolation function 
arm_bilinear_interp_instance_q7Instance structure for the Q15 bilinear interpolation function 
arm_biquad_cas_df1_32x64_ins_q31Instance structure for the high precision Q31 Biquad cascade filter 
arm_biquad_cascade_df2T_instance_f32Instance structure for the floating-point transposed direct form II Biquad cascade filter 
arm_biquad_casd_df1_inst_f32Instance structure for the floating-point Biquad cascade filter 
arm_biquad_casd_df1_inst_q15Instance structure for the Q15 Biquad cascade filter 
arm_biquad_casd_df1_inst_q31Instance structure for the Q31 Biquad cascade filter 
arm_cfft_radix4_instance_f32Instance structure for the floating-point CFFT/CIFFT function 
arm_cfft_radix4_instance_q15Instance structure for the Q15 CFFT/CIFFT function 
arm_cfft_radix4_instance_q31Instance structure for the Q31 CFFT/CIFFT function 
arm_dct4_instance_f32Instance structure for the floating-point DCT4/IDCT4 function 
arm_dct4_instance_q15Instance structure for the Q15 DCT4/IDCT4 function 
arm_dct4_instance_q31Instance structure for the Q31 DCT4/IDCT4 function 
arm_fir_decimate_instance_f32Instance structure for the floating-point FIR decimator 
arm_fir_decimate_instance_q15Instance structure for the Q15 FIR decimator 
arm_fir_decimate_instance_q31Instance structure for the Q31 FIR decimator 
arm_fir_instance_f32Instance structure for the floating-point FIR filter 
arm_fir_instance_q15Instance structure for the Q15 FIR filter 
arm_fir_instance_q31Instance structure for the Q31 FIR filter 
arm_fir_instance_q7Instance structure for the Q7 FIR filter 
arm_fir_interpolate_instance_f32Instance structure for the floating-point FIR interpolator 
arm_fir_interpolate_instance_q15Instance structure for the Q15 FIR interpolator 
arm_fir_interpolate_instance_q31Instance structure for the Q31 FIR interpolator 
arm_fir_lattice_instance_f32Instance structure for the floating-point FIR lattice filter 
arm_fir_lattice_instance_q15Instance structure for the Q15 FIR lattice filter 
arm_fir_lattice_instance_q31Instance structure for the Q31 FIR lattice filter 
arm_fir_sparse_instance_f32Instance structure for the floating-point sparse FIR filter 
arm_fir_sparse_instance_q15Instance structure for the Q15 sparse FIR filter 
arm_fir_sparse_instance_q31Instance structure for the Q31 sparse FIR filter 
arm_fir_sparse_instance_q7Instance structure for the Q7 sparse FIR filter 
arm_iir_lattice_instance_f32Instance structure for the floating-point IIR lattice filter 
arm_iir_lattice_instance_q15Instance structure for the Q15 IIR lattice filter 
arm_iir_lattice_instance_q31Instance structure for the Q31 IIR lattice filter 
arm_linear_interp_instance_f32Instance structure for the floating-point Linear Interpolate function 
arm_lms_instance_f32Instance structure for the floating-point LMS filter 
arm_lms_instance_q15Instance structure for the Q15 LMS filter 
arm_lms_instance_q31Instance structure for the Q31 LMS filter 
arm_lms_norm_instance_f32Instance structure for the floating-point normalized LMS filter 
arm_lms_norm_instance_q15Instance structure for the Q15 normalized LMS filter 
arm_lms_norm_instance_q31Instance structure for the Q31 normalized LMS filter 
arm_matrix_instance_f32Instance structure for the floating-point matrix structure 
arm_matrix_instance_q15Instance structure for the Q15 matrix structure 
arm_matrix_instance_q31Instance structure for the Q31 matrix structure 
arm_pid_instance_f32Instance structure for the floating-point PID Control 
arm_pid_instance_q15Instance structure for the Q15 PID Control 
arm_pid_instance_q31Instance structure for the Q31 PID Control 
arm_rfft_instance_f32Instance structure for the floating-point RFFT/RIFFT function 
arm_rfft_instance_q15Instance structure for the Q15 RFFT/RIFFT function 
arm_rfft_instance_q31Instance structure for the Q31 RFFT/RIFFT function 

+

+
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+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__f32_8c.html
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+
+CMSIS DSP Software Library: arm_abs_f32.c File Reference
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+
+
+
+
+
+

+  

+Functions  

+  

+
arm_abs_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include <math.h>

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_abs_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__f32_8c_source.html
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+CMSIS DSP Software Library: arm_abs_f32.c Source File
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Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__q15_8c.html
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+CMSIS DSP Software Library: arm_abs_q15.c File Reference
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+
+
+

+  

+Functions  

+  

+
arm_abs_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_abs_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

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+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__q15_8c_source.html
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+CMSIS DSP Software Library: arm_abs_q15.c Source File
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Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__q31_8c.html
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+CMSIS DSP Software Library: arm_abs_q31.c File Reference
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+

+  

+Functions  

+  

+
arm_abs_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_abs_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

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+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__q31_8c_source.html
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+CMSIS DSP Software Library: arm_abs_q31.c Source File
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Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__q7_8c.html
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+CMSIS DSP Software Library: arm_abs_q7.c File Reference
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+  

+Functions  

+  

+
arm_abs_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_abs_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

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Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__abs__q7_8c_source.html
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+CMSIS DSP Software Library: arm_abs_q7.c Source File
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Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__f32_8c.html
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+CMSIS DSP Software Library: arm_add_f32.c File Reference
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+

+  

+Functions  

+  

+
arm_add_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_add_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)

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+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__f32_8c_source.html
new file mode 100644
index 0000000..a6de216
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__f32_8c_source.html
@@ -0,0 +1,161 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q15_8c.html
new file mode 100644
index 0000000..a8ec015
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_add_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_add_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q15_8c_source.html
new file mode 100644
index 0000000..040323f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q15_8c_source.html
@@ -0,0 +1,174 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q31_8c.html
new file mode 100644
index 0000000..c190d56
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_add_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_add_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q31_8c_source.html
new file mode 100644
index 0000000..5887596
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q31_8c_source.html
@@ -0,0 +1,175 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q7_8c.html
new file mode 100644
index 0000000..9b2192e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_add_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_add_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q7_8c_source.html
new file mode 100644
index 0000000..8208388
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__add__q7_8c_source.html
@@ -0,0 +1,173 @@
+
+
+
+
+CMSIS DSP Software Library: arm_add_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__init__q31_8c.html
new file mode 100644
index 0000000..275b77a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_32x64_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_32x64_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__init__q31_8c_source.html
new file mode 100644
index 0000000..b36c37c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__init__q31_8c_source.html
@@ -0,0 +1,130 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_32x64_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__q31_8c.html
new file mode 100644
index 0000000..ec4e914
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_32x64_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_32x64_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__q31_8c_source.html
new file mode 100644
index 0000000..93966d0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__32x64__q31_8c_source.html
@@ -0,0 +1,405 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_32x64_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__f32_8c.html
new file mode 100644
index 0000000..03352c5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__f32_8c_source.html
new file mode 100644
index 0000000..58e5b94
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__f32_8c_source.html
@@ -0,0 +1,356 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q15_8c.html
new file mode 100644
index 0000000..add09a6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q15_8c_source.html
new file mode 100644
index 0000000..e211ac2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q15_8c_source.html
@@ -0,0 +1,322 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_fast_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q31_8c.html
new file mode 100644
index 0000000..7273769
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q31_8c_source.html
new file mode 100644
index 0000000..0980770
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__fast__q31_8c_source.html
@@ -0,0 +1,308 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_fast_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__f32_8c.html
new file mode 100644
index 0000000..98e9982
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__f32_8c_source.html
new file mode 100644
index 0000000..8e3ad09
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__f32_8c_source.html
@@ -0,0 +1,129 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q15_8c.html
new file mode 100644
index 0000000..5ed36d7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q15_8c_source.html
new file mode 100644
index 0000000..1ea3146
--- /dev/null
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@@ -0,0 +1,133 @@
+
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+
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+CMSIS DSP Software Library: arm_biquad_cascade_df1_init_q15.c Source File
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q31_8c.html
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@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__init__q31_8c_source.html
new file mode 100644
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--- /dev/null
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@@ -0,0 +1,134 @@
+
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+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_init_q31.c Source File
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+
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q15_8c.html
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@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q15_8c_source.html
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--- /dev/null
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@@ -0,0 +1,419 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_q15.c Source File
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+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q31_8c.html
new file mode 100644
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--- /dev/null
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@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df1_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df1_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df1__q31_8c_source.html
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--- /dev/null
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@@ -0,0 +1,402 @@
+
+
+
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+CMSIS DSP Software Library: arm_biquad_cascade_df1_q31.c Source File
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+
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+
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+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__f32_8c.html
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@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df2T_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df2T_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
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+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__f32_8c_source.html
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@@ -0,0 +1,322 @@
+
+
+
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+CMSIS DSP Software Library: arm_biquad_cascade_df2T_f32.c Source File
+
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+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__init__f32_8c.html
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+
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+CMSIS DSP Software Library: arm_biquad_cascade_df2T_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_biquad_cascade_df2T_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__biquad__cascade__df2_t__init__f32_8c_source.html
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--- /dev/null
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@@ -0,0 +1,127 @@
+
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+CMSIS DSP Software Library: arm_biquad_cascade_df2T_init_f32.c Source File
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+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__f32_8c.html
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@@ -0,0 +1,244 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cfft_radix4_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc)
void arm_radix4_butterfly_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier)
void arm_radix4_butterfly_inverse_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier, float32_t onebyfftLen)
void arm_bitreversal_f32 (float32_t *pSrc, uint16_t fftSize, uint16_t bitRevFactor, uint16_t *pBitRevTab)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
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+        
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+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_radix4_butterfly_f32 (float32_t *  pSrc, 
uint16_t  fftLen, 
float32_t *  pCoef, 
uint16_t  twidCoefModifier 
)

+

+

+
+
Core function for the floating-point CFFT butterfly process. 

+
end of CFFT_CIFFT group 

+
+
Definition at line 223 of file arm_cfft_radix4_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
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+        
+        
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+      
void arm_radix4_butterfly_inverse_f32 (float32_t *  pSrc, 
uint16_t  fftLen, 
float32_t *  pCoef, 
uint16_t  twidCoefModifier, 
float32_t  onebyfftLen 
)

+

+

+
+
Core function for the floating-point CIFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
[in]onebyfftLenvalue of 1/fftLen. 

+  

+

+
Returns:
none. 

+
+
Definition at line 660 of file arm_cfft_radix4_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
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+          
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+        
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+        
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+          
+          
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+        
+          
+          
+          
+        
+      
void arm_bitreversal_f32 (float32_t *  pSrc, 
uint16_t  fftSize, 
uint16_t  bitRevFactor, 
uint16_t *  pBitRevTab 
)

+

+

+
+
In-place bit reversal function. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftSizelength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table. 
[in]*pBitRevTabpoints to the bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 1177 of file arm_cfft_radix4_f32.c.

+
+

+

+

+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__f32_8c_source.html
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+
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+
+CMSIS DSP Software Library: arm_cfft_radix4_f32.c Source File
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__f32_8c.html
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--- /dev/null
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@@ -0,0 +1,88 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_cfft_radix4_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)

+Variables
static const float32_t twiddleCoef [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__f32_8c_source.html
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@@ -0,0 +1,1217 @@
+
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+
+CMSIS DSP Software Library: arm_cfft_radix4_init_f32.c Source File
+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q15_8c.html
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index 0000000..c19dc6a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q15_8c.html
@@ -0,0 +1,88 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_cfft_radix4_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)

+Variables
static const q15_t twiddleCoefQ15 [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q15_8c_source.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q15_8c_source.html
@@ -0,0 +1,435 @@
+
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+
+
+CMSIS DSP Software Library: arm_cfft_radix4_init_q15.c Source File
+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q31_8c.html
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+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_cfft_radix4_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)

+Variables
static const q31_t twiddleCoefQ31 [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__init__q31_8c_source.html
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+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q15_8c.html
new file mode 100644
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+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cfft_radix4_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc)
void arm_radix4_butterfly_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
void arm_radix4_butterfly_inverse_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
void arm_bitreversal_q15 (q15_t *pSrc16, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)

+
Function Documentation

+
+

+

+      
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void arm_radix4_butterfly_q15 (q15_t *  pSrc16, 
uint32_t  fftLen, 
q15_t *  pCoef16, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q15 CFFT butterfly process. 

+
end of CFFT_CIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 138 of file arm_cfft_radix4_q15.c.

+
+

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void arm_radix4_butterfly_inverse_q15 (q15_t *  pSrc16, 
uint32_t  fftLen, 
q15_t *  pCoef16, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q15 CIFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 1053 of file arm_cfft_radix4_q15.c.

+
+

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+
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+      
void arm_bitreversal_q15 (q15_t *  pSrc, 
uint32_t  fftLen, 
uint16_t  bitRevFactor, 
uint16_t *  pBitRevTab 
)

+

+

+
+
In-place bit reversal function. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table 
[in]*pBitRevTabpoints to bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 1906 of file arm_cfft_radix4_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q15_8c_source.html
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+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q31_8c.html
new file mode 100644
index 0000000..5afb7e4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q31_8c.html
@@ -0,0 +1,247 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cfft_radix4_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc)
void arm_radix4_butterfly_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
void arm_radix4_butterfly_inverse_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
void arm_bitreversal_q31 (q31_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTable)

+
Function Documentation

+
+

+

+      
+        
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+          
+          
+        
+      
void arm_radix4_butterfly_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
q31_t *  pCoef, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q31 CFFT butterfly process. 

+
end of CFFT_CIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 139 of file arm_cfft_radix4_q31.c.

+
+

+

+
+

+

+      
+        
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+          
+        
+      
void arm_radix4_butterfly_inverse_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
q31_t *  pCoef, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q31 CIFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 517 of file arm_cfft_radix4_q31.c.

+
+

+

+
+

+

+      
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+          
+          
+        
+      
void arm_bitreversal_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
uint16_t  bitRevFactor, 
uint16_t *  pBitRevTab 
)

+

+

+
+
In-place bit reversal function. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table 
[in]*pBitRevTabpoints to bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 848 of file arm_cfft_radix4_q31.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cfft__radix4__q31_8c_source.html
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index 0000000..5d01552
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+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_q31.c Source File
+
+
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+
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+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__class__marks__example__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__class__marks__example__f32_8c.html
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index 0000000..764cd25
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__class__marks__example__f32_8c.html
@@ -0,0 +1,393 @@
+
+
+
+
+CMSIS DSP Software Library: arm_class_marks_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_class_marks_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define USE_STATIC_INIT
#define TEST_LENGTH_SAMPLES   (20*4)
#define NUMSTUDENTS   20
#define NUMSUBJECTS   4

+Functions
int32_t main ()

+Variables
const float32_t testMarks_f32 [TEST_LENGTH_SAMPLES]
const float32_t testUnity_f32 [4]
static float32_t testOutput [TEST_LENGTH_SAMPLES]
uint32_t numStudents = 20
uint32_t numSubjects = 4
float32_t max_marks
float32_t min_marks
float32_t mean
float32_t std
float32_t var
uint32_t student_num

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define USE_STATIC_INIT

+

+

+
+
Definition at line 69 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES   (20*4)

+

+

+
Examples: 
arm_class_marks_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_linear_interp_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 75 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMSTUDENTS   20

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 123 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMSUBJECTS   4

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 124 of file arm_class_marks_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
Examples: 
arm_class_marks_example_f32.c, arm_convolution_example_f32.c, arm_dotproduct_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, arm_matrix_example_f32.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 139 of file arm_class_marks_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t testMarks_f32[TEST_LENGTH_SAMPLES]

+

+

+Initial value:
  
+{    
+    42.000000,  37.000000,  81.000000,  28.000000,   
+    83.000000,  72.000000,  36.000000,  38.000000,   
+    32.000000,  51.000000,  63.000000,  64.000000,   
+    97.000000,  82.000000,  95.000000,  90.000000,   
+    66.000000,  51.000000,  54.000000,  42.000000,   
+    67.000000,  56.000000,  45.000000,  57.000000,   
+    67.000000,  69.000000,  35.000000,  52.000000,   
+    29.000000,  81.000000,  58.000000,  47.000000,   
+    38.000000,  76.000000,  100.000000, 29.000000,   
+    33.000000,  47.000000,  29.000000,  50.000000,   
+    34.000000,  41.000000,  61.000000,  46.000000,   
+    52.000000,  50.000000,  48.000000,  36.000000,   
+    47.000000,  55.000000,  44.000000,  40.000000,   
+    100.000000, 94.000000,  84.000000,  37.000000,   
+    32.000000,  71.000000,  47.000000,  77.000000,   
+    31.000000,  50.000000,  49.000000,  35.000000,   
+    63.000000,  67.000000,  40.000000,  31.000000,   
+    29.000000,  68.000000,  61.000000,  38.000000,   
+    31.000000,  28.000000,  28.000000,  76.000000,   
+    55.000000,  33.000000,  29.000000,  39.000000 
+}
+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 80 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t testUnity_f32[4]

+

+

+Initial value:
  
+{    
+    1.000,  1.000,  1.000,  1.000 
+}
+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 108 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TEST_LENGTH_SAMPLES] [static]

+

+

+
Examples: 
arm_class_marks_example_f32.c, arm_dotproduct_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, and arm_sin_cos_example_f32.c.

+

+
Definition at line 117 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t numStudents = 20

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 130 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t numSubjects = 4

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 131 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t max_marks

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 132 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t min_marks

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 132 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t mean

+

+

+
Examples: 
arm_class_marks_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 132 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t std

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 132 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t var

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 132 of file arm_class_marks_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t student_num

+

+

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 133 of file arm_class_marks_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__class__marks__example__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__class__marks__example__f32_8c_source.html
new file mode 100644
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--- /dev/null
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+CMSIS DSP Software Library: arm_class_marks_example_f32.c Source File
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+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__f32_8c.html
new file mode 100644
index 0000000..9eb1ffa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_conj_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_conj_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_conj_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__f32_8c_source.html
new file mode 100644
index 0000000..84868b1
--- /dev/null
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@@ -0,0 +1,171 @@
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+CMSIS DSP Software Library: arm_cmplx_conj_f32.c Source File
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+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q15_8c.html
new file mode 100644
index 0000000..d266b06
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_conj_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_conj_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_conj_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q15_8c_source.html
new file mode 100644
index 0000000..96d9a69
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q15_8c_source.html
@@ -0,0 +1,171 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_conj_q15.c Source File
+
+
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+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q31_8c.html
new file mode 100644
index 0000000..463c919
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_conj_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_conj_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_conj_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q31_8c_source.html
new file mode 100644
index 0000000..1eb0d09
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__conj__q31_8c_source.html
@@ -0,0 +1,179 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_conj_q31.c Source File
+
+
+
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+
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+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__f32_8c.html
new file mode 100644
index 0000000..2823695
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_dot_prod_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_dot_prod_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__f32_8c_source.html
new file mode 100644
index 0000000..c0394dd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__f32_8c_source.html
@@ -0,0 +1,182 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_dot_prod_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q15_8c.html
new file mode 100644
index 0000000..b90697c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_dot_prod_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_dot_prod_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q15_8c_source.html
new file mode 100644
index 0000000..6a3cb4a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q15_8c_source.html
@@ -0,0 +1,184 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_dot_prod_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q31_8c.html
new file mode 100644
index 0000000..2195b74
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_dot_prod_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_dot_prod_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q31_8c_source.html
new file mode 100644
index 0000000..e292ea3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__dot__prod__q31_8c_source.html
@@ -0,0 +1,184 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_dot_prod_q31.c Source File
+
+
+
+
+
+
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+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__f32_8c.html
new file mode 100644
index 0000000..e1bd36b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mag_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mag_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__f32_8c_source.html
new file mode 100644
index 0000000..7f1716c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__f32_8c_source.html
@@ -0,0 +1,183 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q15_8c.html
new file mode 100644
index 0000000..cf8cc0e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mag_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mag_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q15_8c_source.html
new file mode 100644
index 0000000..7d8d590
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q15_8c_source.html
@@ -0,0 +1,201 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q31_8c.html
new file mode 100644
index 0000000..e99318c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mag_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mag_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q31_8c_source.html
new file mode 100644
index 0000000..f45c0f6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__q31_8c_source.html
@@ -0,0 +1,199 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__f32_8c.html
new file mode 100644
index 0000000..e6ed8a8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_squared_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mag_squared_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mag_squared_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__f32_8c_source.html
new file mode 100644
index 0000000..c26a7bd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__f32_8c_source.html
@@ -0,0 +1,183 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_squared_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q15_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_squared_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mag_squared_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mag_squared_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q15_8c_source.html
new file mode 100644
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--- /dev/null
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@@ -0,0 +1,197 @@
+
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+CMSIS DSP Software Library: arm_cmplx_mag_squared_q15.c Source File
+
+
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+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q31_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_squared_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mag_squared_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mag_squared_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q31_8c_source.html
new file mode 100644
index 0000000..a308689
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mag__squared__q31_8c_source.html
@@ -0,0 +1,197 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mag_squared_q31.c Source File
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+
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+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__f32_8c.html
new file mode 100644
index 0000000..7caccac
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_cmplx_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mult_cmplx_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mult_cmplx_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__f32_8c_source.html
new file mode 100644
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--- /dev/null
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@@ -0,0 +1,209 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_cmplx_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q15_8c.html
new file mode 100644
index 0000000..d6b4626
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_cmplx_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mult_cmplx_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mult_cmplx_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q15_8c_source.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q15_8c_source.html
@@ -0,0 +1,230 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_cmplx_q15.c Source File
+
+
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+
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+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q31_8c.html
new file mode 100644
index 0000000..95dd398
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_cmplx_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mult_cmplx_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mult_cmplx_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__cmplx__q31_8c_source.html
new file mode 100644
index 0000000..a7b3b32
--- /dev/null
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@@ -0,0 +1,255 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_cmplx_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__f32_8c.html
new file mode 100644
index 0000000..18f40cc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_real_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mult_real_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mult_real_f32 (float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__f32_8c_source.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__f32_8c_source.html
@@ -0,0 +1,185 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_real_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q15_8c.html
new file mode 100644
index 0000000..e9db6d3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_real_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mult_real_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mult_real_q15 (q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q15_8c_source.html
new file mode 100644
index 0000000..76bbf4e
--- /dev/null
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@@ -0,0 +1,197 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_real_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q31_8c.html
new file mode 100644
index 0000000..e57b4ca
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_real_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_cmplx_mult_real_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_cmplx_mult_real_q31 (q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cmplx__mult__real__q31_8c_source.html
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--- /dev/null
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@@ -0,0 +1,197 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cmplx_mult_real_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__common__tables_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__common__tables_8c.html
new file mode 100644
index 0000000..2a6fff0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__common__tables_8c.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_common_tables.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Variables  

+  

+
arm_common_tables.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Variables
const uint16_t armBitRevTable [256]
const q15_t armRecipTableQ15 [64]
const q31_t armRecipTableQ31 [64]

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const q15_t armRecipTableQ15[64]

+

+

+Initial value:
 {
+  0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0,
+  0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82,
+  0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484,
+  0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0,
+  0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E,
+  0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255,
+  0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6,
+  0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978,
+  0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8,
+  0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255,
+  0x41CC, 0x4146, 0x40C2, 0x4040
+}
+
end of CFFT_CIFFT group 

+
+
Definition at line 115 of file arm_common_tables.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t armRecipTableQ31[64]

+

+

+Initial value:
 {
+  0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928,
+  0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3,
+  0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519,
+  0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB,
+  0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318,
+  0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0,
+  0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D,
+  0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96,
+  0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2,
+  0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426,
+  0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102
+}
+

+
Definition at line 132 of file arm_common_tables.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__common__tables_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__common__tables_8c_source.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__common__tables_8c_source.html
@@ -0,0 +1,181 @@
+
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+
+
+CMSIS DSP Software Library: arm_common_tables.c Source File
+
+
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+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__f32_8c.html
new file mode 100644
index 0000000..4c7cf3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_conv_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__f32_8c_source.html
new file mode 100644
index 0000000..61c2d8f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__f32_8c_source.html
@@ -0,0 +1,626 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q15_8c.html
new file mode 100644
index 0000000..d39f7d6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_conv_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q15_8c_source.html
new file mode 100644
index 0000000..13b0274
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q15_8c_source.html
@@ -0,0 +1,713 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_fast_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q31_8c.html
new file mode 100644
index 0000000..a9a80e4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_conv_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q31_8c_source.html
new file mode 100644
index 0000000..a4525b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__fast__q31_8c_source.html
@@ -0,0 +1,601 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_fast_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__f32_8c.html
new file mode 100644
index 0000000..d9c433f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_partial_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_conv_partial_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__f32_8c_source.html
new file mode 100644
index 0000000..d043ca9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__f32_8c_source.html
@@ -0,0 +1,673 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q15_8c.html
new file mode 100644
index 0000000..ff4703f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_partial_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_conv_partial_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q15_8c_source.html
new file mode 100644
index 0000000..449cde1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q15_8c_source.html
@@ -0,0 +1,751 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_fast_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q31_8c.html
new file mode 100644
index 0000000..885d423
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_partial_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_conv_partial_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q31_8c_source.html
new file mode 100644
index 0000000..f0a8d4e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__fast__q31_8c_source.html
@@ -0,0 +1,639 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_fast_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q15_8c.html
new file mode 100644
index 0000000..9ad51bc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_partial_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_conv_partial_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q15_8c_source.html
new file mode 100644
index 0000000..31a90ec
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q15_8c_source.html
@@ -0,0 +1,811 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q31_8c.html
new file mode 100644
index 0000000..1440909
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_partial_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_conv_partial_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q31_8c_source.html
new file mode 100644
index 0000000..8599501
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q31_8c_source.html
@@ -0,0 +1,663 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q7_8c.html
new file mode 100644
index 0000000..b6da190
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_partial_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_conv_partial_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q7_8c_source.html
new file mode 100644
index 0000000..988b71d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__partial__q7_8c_source.html
@@ -0,0 +1,771 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_partial_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q15_8c.html
new file mode 100644
index 0000000..3d7eee6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_conv_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q15_8c_source.html
new file mode 100644
index 0000000..9d80ded
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q15_8c_source.html
@@ -0,0 +1,765 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q31_8c.html
new file mode 100644
index 0000000..2fa09ee
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_conv_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q31_8c_source.html
new file mode 100644
index 0000000..e583f74
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q31_8c_source.html
@@ -0,0 +1,618 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q7_8c.html
new file mode 100644
index 0000000..3864658
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_conv_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_conv_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q7_8c_source.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__conv__q7_8c_source.html
@@ -0,0 +1,721 @@
+
+
+
+
+CMSIS DSP Software Library: arm_conv_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__convolution__example__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__convolution__example__f32_8c.html
new file mode 100644
index 0000000..dff62b0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__convolution__example__f32_8c.html
@@ -0,0 +1,386 @@
+
+
+
+
+CMSIS DSP Software Library: arm_convolution_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_convolution_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include "math_helper.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define MAX_BLOCKSIZE   128
#define DELTA   (0.000001f)
#define SNR_THRESHOLD   90

+Functions
int32_t main (void)

+Variables
float32_t Ak [MAX_BLOCKSIZE]
float32_t Bk [MAX_BLOCKSIZE]
float32_t AxB [MAX_BLOCKSIZE *2]
float32_t testInputA_f32 [64]
float32_t testInputB_f32 [64]
const float testRefOutput_f32 [126]
uint32_t srcALen = 64
uint32_t srcBLen = 64
uint32_t outLen
float32_t snr

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define MAX_BLOCKSIZE   128

+

+

+
Examples: 
arm_convolution_example_f32.c, arm_dotproduct_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 95 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA   (0.000001f)

+

+

+
Examples: 
arm_dotproduct_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 96 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD   90

+

+

+
Examples: 
arm_convolution_example_f32.c, and arm_matrix_example_f32.c.

+

+
Definition at line 97 of file arm_convolution_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 175 of file arm_convolution_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t Ak[MAX_BLOCKSIZE]

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 102 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t Bk[MAX_BLOCKSIZE]

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 103 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t AxB[MAX_BLOCKSIZE *2]

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 104 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInputA_f32[64]

+

+

+Initial value:
  
+{  
+-0.808920,  1.357369,   1.180861,   -0.504544,  1.762637,   -0.703285,   
+1.696966,   0.620571,   -0.151093,  -0.100235,  -0.872382,  -0.403579,   
+-0.860749,  -0.382648,  -1.052338,  0.128113,   -0.646269,  1.093377,    
+-2.209198,  0.471706,   0.408901,   1.266242,   0.598252,   1.176827,    
+-0.203421,  0.213596,   -0.851964,  -0.466958,  0.021841,   -0.698938,   
+-0.604107,  0.461778,   -0.318219,  0.942520,   0.577585,   0.417619,    
+0.614665,   0.563679,   -1.295073,  -0.764437,  0.952194,   -0.859222,   
+-0.618554,  -2.268542,  -1.210592,  1.655853,   -2.627219,  -0.994249,   
+-1.374704,  0.343799,   0.025619,   1.227481,   -0.708031,  0.069355,    
+-1.845228,  -1.570886,  1.010668,   -1.802084,  1.630088,   1.286090,    
+-0.161050,  -0.940794,  0.367961,   0.291907 
+         
+}
+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 110 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInputB_f32[64]

+

+

+Initial value:
  
+{  
+0.933724,   0.046881,   1.316470,   0.438345,   0.332682,   2.094885,    
+0.512081,   0.035546,   0.050894,   -2.320371,  0.168711,   -1.830493,   
+-0.444834,  -1.003242,  -0.531494,  -1.365600,  -0.155420,  -0.757692,   
+-0.431880,  -0.380021,  0.096243,   -0.695835,  0.558850,   -1.648962,   
+0.020369,   -0.363630,  0.887146,   0.845503,   -0.252864,  -0.330397,   
+1.269131,   -1.109295,  -1.027876,  0.135940,   0.116721,   -0.293399,   
+-1.349799,  0.166078,   -0.802201,  0.369367,   -0.964568,  -2.266011,   
+0.465178,   0.651222,   -0.325426,  0.320245,   -0.784178,  -0.579456,   
+0.093374,   0.604778,   -0.048225,  0.376297,   -0.394412,  0.578182,    
+-1.218141,  -1.387326,  0.692462,   -0.631297,  0.153137,   -0.638952,   
+0.635474,   -0.970468,  1.334057,   -0.111370 
+}
+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 126 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float testRefOutput_f32[126]

+

+

+Initial value:
   
+{  
+-0.818943,  1.229484,   -0.533664,  1.016604,   0.341875,   -1.963656,   
+5.171476,   3.478033,   7.616361,   6.648384,   0.479069,   1.792012,    
+-1.295591,  -7.447818,  0.315830,   -10.657445, -2.483469,  -6.524236,   
+-7.380591,  -3.739005,  -8.388957,  0.184147,   -1.554888,  3.786508,    
+-1.684421,  5.400610,   -1.578126,  7.403361,   8.315999,   2.080267,    
+11.077776,  2.749673,   7.138962,   2.748762,   0.660363,   0.981552,    
+1.442275,   0.552721,   -2.576892,  4.703989,   0.989156,   8.759344,    
+-0.564825,  -3.994680,  0.954710,   -5.014144,  6.592329,   1.599488,    
+-13.979146, -0.391891,  -4.453369,  -2.311242,  -2.948764,  1.761415,    
+-0.138322,  10.433007,  -2.309103,  4.297153,   8.535523,   3.209462,    
+8.695819,   5.569919,   2.514304,   5.582029,   2.060199,   0.642280,    
+7.024616,   1.686615,   -6.481756,  1.343084,   -3.526451,  1.099073,    
+-2.965764,  -0.173723,  -4.111484,  6.528384,   -6.965658,  1.726291,    
+1.535172,   11.023435,  2.338401,   -4.690188,  1.298210,   3.943885,    
+8.407885,   5.168365,   0.684131,   1.559181,   1.859998,   2.852417,    
+8.574070,   -6.369078,  6.023458,   11.837963,  -6.027632,  4.469678,    
+-6.799093,  -2.674048,  6.250367,   -6.809971,  -3.459360,  9.112410,    
+-2.711621,  -1.336678,  1.564249,   -1.564297,  -1.296760,  8.904013,    
+-3.230109,  6.878013,   -7.819823,  3.369909,   -1.657410,  -2.007358,   
+-4.112825,  1.370685,   -3.420525,  -6.276605,  3.244873,   -3.352638,   
+1.545372,   0.902211,   0.197489,   -1.408732,  0.523390,   0.348440 
+}
+
Examples: 
arm_convolution_example_f32.c, arm_graphic_equalizer_example_q31.c, and arm_sin_cos_example_f32.c.

+

+
Definition at line 141 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t srcALen = 64

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 170 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t srcBLen = 64

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 171 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t outLen

+

+

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 172 of file arm_convolution_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr

+

+

+
Examples: 
arm_convolution_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, and arm_matrix_example_f32.c.

+

+
Definition at line 173 of file arm_convolution_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__convolution__example__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__convolution__example__f32_8c_source.html
new file mode 100644
index 0000000..5fc7237
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__convolution__example__f32_8c_source.html
@@ -0,0 +1,237 @@
+
+
+
+
+CMSIS DSP Software Library: arm_convolution_example_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__f32_8c.html
new file mode 100644
index 0000000..ba5c552
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_copy_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_copy_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__f32_8c_source.html
new file mode 100644
index 0000000..7533e38
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__f32_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q15_8c.html
new file mode 100644
index 0000000..229bcae
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_copy_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_copy_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q15_8c_source.html
new file mode 100644
index 0000000..fa1ed3a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q15_8c_source.html
@@ -0,0 +1,183 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q31_8c.html
new file mode 100644
index 0000000..b487ad6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_copy_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_copy_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q31_8c_source.html
new file mode 100644
index 0000000..4ee3b5b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q31_8c_source.html
@@ -0,0 +1,161 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q7_8c.html
new file mode 100644
index 0000000..a655ee2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_copy_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_copy_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q7_8c_source.html
new file mode 100644
index 0000000..8c52643
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__copy__q7_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_copy_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__f32_8c.html
new file mode 100644
index 0000000..88a960d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_correlate_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_correlate_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__f32_8c_source.html
new file mode 100644
index 0000000..557b9b0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__f32_8c_source.html
@@ -0,0 +1,729 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q15_8c.html
new file mode 100644
index 0000000..7d3f2d9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_correlate_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_correlate_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q15_8c_source.html
new file mode 100644
index 0000000..345b342
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q15_8c_source.html
@@ -0,0 +1,658 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_fast_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q31_8c.html
new file mode 100644
index 0000000..23d3b06
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_correlate_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_correlate_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q31_8c_source.html
new file mode 100644
index 0000000..39b1af4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__fast__q31_8c_source.html
@@ -0,0 +1,631 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_fast_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q15_8c.html
new file mode 100644
index 0000000..4a5a870
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_correlate_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_correlate_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q15_8c_source.html
new file mode 100644
index 0000000..1982577
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q15_8c_source.html
@@ -0,0 +1,752 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q31_8c.html
new file mode 100644
index 0000000..0f01228
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_correlate_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_correlate_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q31_8c_source.html
new file mode 100644
index 0000000..d00827c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q31_8c_source.html
@@ -0,0 +1,718 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q7_8c.html
new file mode 100644
index 0000000..7055386
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_correlate_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_correlate_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q7_8c_source.html
new file mode 100644
index 0000000..b86b037
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__correlate__q7_8c_source.html
@@ -0,0 +1,821 @@
+
+
+
+
+CMSIS DSP Software Library: arm_correlate_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__f32_8c.html
new file mode 100644
index 0000000..137febf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__f32_8c.html
@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cos_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_cos_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
float32_t arm_cos_f32 (float32_t x)

+Variables
static const float32_t cosTable [259]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__f32_8c_source.html
new file mode 100644
index 0000000..4acf4da
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__f32_8c_source.html
@@ -0,0 +1,263 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cos_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__q15_8c.html
new file mode 100644
index 0000000..564549d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__q15_8c.html
@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cos_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_cos_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
q15_t arm_cos_q15 (q15_t x)

+Variables
static const q15_t cosTableQ15 [259]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__q15_8c_source.html
new file mode 100644
index 0000000..2108656
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__q15_8c_source.html
@@ -0,0 +1,223 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cos_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__q31_8c.html
new file mode 100644
index 0000000..0448801
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__q31_8c.html
@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cos_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_cos_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
q31_t arm_cos_q31 (q31_t x)

+Variables
static const q31_t cosTableQ31 [259]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__q31_8c_source.html
new file mode 100644
index 0000000..28a5823
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__cos__q31_8c_source.html
@@ -0,0 +1,259 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cos_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__f32_8c.html
new file mode 100644
index 0000000..ba9322e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dct4_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dct4_f32 (const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__f32_8c_source.html
new file mode 100644
index 0000000..96213b0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__f32_8c_source.html
@@ -0,0 +1,426 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__f32_8c.html
new file mode 100644
index 0000000..2172416
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__f32_8c.html
@@ -0,0 +1,92 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_dct4_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize)

+Variables
static const float32_t Weights_128 [256]
static const float32_t Weights_512 [1024]
static const float32_t Weights_2048 [4096]
static const float32_t cos_factors_128 [128]
static const float32_t cos_factors_512 [512]
static const float32_t cos_factors_2048 [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__f32_8c_source.html
new file mode 100644
index 0000000..480fd61
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__f32_8c_source.html
@@ -0,0 +1,4223 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_init_f32.c Source File
+
+
+
+
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+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q15_8c.html
new file mode 100644
index 0000000..325fa1d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q15_8c.html
@@ -0,0 +1,92 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_dct4_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize)

+Variables
static const q15_t WeightsQ15_128 [256]
static const q15_t WeightsQ15_512 [1024]
static const q15_t WeightsQ15_2048 [4096]
static const q15_t cos_factorsQ15_128 [128]
static const q15_t cos_factorsQ15_512 [512]
static const q15_t cos_factorsQ15_2048 [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q15_8c_source.html
new file mode 100644
index 0000000..2dd02fe
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q15_8c_source.html
@@ -0,0 +1,1199 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_init_q15.c Source File
+
+
+
+
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+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q31_8c.html
new file mode 100644
index 0000000..cdd7741
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q31_8c.html
@@ -0,0 +1,92 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_dct4_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize)

+Variables
static const q31_t WeightsQ31_128 [256]
static const q31_t WeightsQ31_512 [1024]
static const q31_t WeightsQ31_2048 [4096]
static const q31_t cos_factorsQ31_128 [128]
static const q31_t cos_factorsQ31_512 [512]
static const q31_t cos_factorsQ31_2048 [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q31_8c_source.html
new file mode 100644
index 0000000..0ee51b3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__init__q31_8c_source.html
@@ -0,0 +1,2207 @@
+
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+
+
+CMSIS DSP Software Library: arm_dct4_init_q31.c Source File
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q15_8c.html
new file mode 100644
index 0000000..0460728
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dct4_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dct4_q15 (const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q15_8c_source.html
new file mode 100644
index 0000000..58c55a9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q15_8c_source.html
@@ -0,0 +1,433 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_q15.c Source File
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q31_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dct4_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dct4_q31 (const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q31_8c_source.html
new file mode 100644
index 0000000..5ec0283
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dct4__q31_8c_source.html
@@ -0,0 +1,433 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_q31.c Source File
+
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+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__f32_8c.html
new file mode 100644
index 0000000..3089dca
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dot_prod_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__f32_8c_source.html
new file mode 100644
index 0000000..514a12a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__f32_8c_source.html
@@ -0,0 +1,165 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_f32.c Source File
+
+
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+
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+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q15_8c.html
new file mode 100644
index 0000000..abf9862
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dot_prod_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q15_8c_source.html
new file mode 100644
index 0000000..f1667c6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q15_8c_source.html
@@ -0,0 +1,176 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_q15.c Source File
+
+
+
+
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+
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+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q31_8c.html
new file mode 100644
index 0000000..f50681b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dot_prod_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q31_8c_source.html
new file mode 100644
index 0000000..0dcf860
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q31_8c_source.html
@@ -0,0 +1,167 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_q31.c Source File
+
+
+
+
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+
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+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q7_8c.html
new file mode 100644
index 0000000..c12b4bc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_dot_prod_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_dot_prod_q7 (q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q7_8c_source.html
new file mode 100644
index 0000000..8103c5e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dot__prod__q7_8c_source.html
@@ -0,0 +1,207 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dot_prod_q7.c Source File
+
+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dotproduct__example__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dotproduct__example__f32_8c.html
new file mode 100644
index 0000000..891dbbd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dotproduct__example__f32_8c.html
@@ -0,0 +1,273 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dotproduct_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_dotproduct_example_f32.c File Reference
  

+

+

+#include <math.h>

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define MAX_BLOCKSIZE   32
#define DELTA   (0.000001f)

+Functions
int32_t main (void)

+Variables
float32_t srcA_buf_f32 [MAX_BLOCKSIZE]
float32_t srcB_buf_f32 [MAX_BLOCKSIZE]
float32_t refDotProdOut = 5.9273644806352142
float32_t multOutput [MAX_BLOCKSIZE]
float32_t testOutput
arm_status status

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define MAX_BLOCKSIZE   32

+

+

+
+
Definition at line 76 of file arm_dotproduct_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA   (0.000001f)

+

+

+
+
Definition at line 77 of file arm_dotproduct_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 130 of file arm_dotproduct_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t srcA_buf_f32[MAX_BLOCKSIZE]

+

+

+Initial value:
   
+{   
+-0.4325648115282207,    -1.6655843782380970,    0.1253323064748307,  
+ 0.2876764203585489,    -1.1464713506814637,    1.1909154656429988,  
+ 1.1891642016521031,    -0.0376332765933176,    0.3272923614086541,  
+ 0.1746391428209245,    -0.1867085776814394,    0.7257905482933027,  
+-0.5883165430141887,     2.1831858181971011,   -0.1363958830865957,  
+ 0.1139313135208096,     1.0667682113591888,    0.0592814605236053,  
+-0.0956484054836690,    -0.8323494636500225,    0.2944108163926404,  
+-1.3361818579378040,     0.7143245518189522,    1.6235620644462707,  
+-0.6917757017022868,     0.8579966728282626,    1.2540014216025324,  
+-1.5937295764474768,    -1.4409644319010200,    0.5711476236581780,  
+-0.3998855777153632,     0.6899973754643451 
+}
+
Examples: 
arm_dotproduct_example_f32.c.

+

+
Definition at line 86 of file arm_dotproduct_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t srcB_buf_f32[MAX_BLOCKSIZE]

+

+

+Initial value:
   
+{   
+ 1.7491401329284098,    0.1325982188803279,  0.3252281811989881,     
+-0.7938091410349637,    0.3149236145048914, -0.5272704888029532,     
+ 0.9322666565031119,    1.1646643544607362, -2.0456694357357357,     
+-0.6443728590041911,    1.7410657940825480,  0.4867684246821860,     
+ 1.0488288293660140,    1.4885752747099299,  1.2705014969484090,     
+-1.8561241921210170,    2.1343209047321410,  1.4358467535865909,     
+-0.9173023332875400,   -1.1060770780029008,  0.8105708062681296,     
+ 0.6985430696369063,   -0.4015827425012831,  1.2687512030669628,     
+-0.7836083053674872,    0.2132664971465569,  0.7878984786088954,     
+ 0.8966819356782295,   -0.1869172943544062,  1.0131816724341454,     
+ 0.2484350696132857,    0.0596083377937976 
+}
+
Examples: 
arm_dotproduct_example_f32.c.

+

+
Definition at line 104 of file arm_dotproduct_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t refDotProdOut = 5.9273644806352142

+

+

+
Examples: 
arm_dotproduct_example_f32.c.

+

+
Definition at line 120 of file arm_dotproduct_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t multOutput[MAX_BLOCKSIZE]

+

+

+
Examples: 
arm_dotproduct_example_f32.c.

+

+
Definition at line 125 of file arm_dotproduct_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput

+

+

+
+
Definition at line 126 of file arm_dotproduct_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_status status

+

+

+
Examples: 
arm_convolution_example_f32.c, arm_dotproduct_example_f32.c, arm_fft_bin_example_f32.c, arm_fir_example_f32.c, arm_graphic_equalizer_example_q31.c, arm_linear_interp_example_f32.c, arm_matrix_example_f32.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 128 of file arm_dotproduct_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dotproduct__example__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dotproduct__example__f32_8c_source.html
new file mode 100644
index 0000000..e7fa374
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__dotproduct__example__f32_8c_source.html
@@ -0,0 +1,187 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dotproduct_example_f32.c Source File
+
+
+
+
+
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fft__bin__example__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fft__bin__example__f32_8c.html
new file mode 100644
index 0000000..bc30832
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fft__bin__example__f32_8c.html
@@ -0,0 +1,243 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fft_bin_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_fft_bin_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define TEST_LENGTH_SAMPLES   2048

+Functions
int32_t main (void)

+Variables
float32_t testInput_f32_10khz [TEST_LENGTH_SAMPLES]
static float32_t testOutput [TEST_LENGTH_SAMPLES/2]
uint32_t fftSize = 1024
uint32_t ifftFlag = 0
uint32_t doBitReverse = 1
uint32_t refIndex = 213
uint32_t testIndex = 0

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES   2048

+

+

+
+
Definition at line 84 of file arm_fft_bin_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 106 of file arm_fft_bin_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TEST_LENGTH_SAMPLES/2] [static]

+

+

+
+
Definition at line 90 of file arm_fft_bin_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t fftSize = 1024

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Definition at line 95 of file arm_fft_bin_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t ifftFlag = 0

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Definition at line 96 of file arm_fft_bin_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t doBitReverse = 1

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Definition at line 97 of file arm_fft_bin_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t refIndex = 213

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Definition at line 100 of file arm_fft_bin_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t testIndex = 0

+

+

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Definition at line 100 of file arm_fft_bin_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fft__bin__example__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fft__bin__example__f32_8c_source.html
new file mode 100644
index 0000000..5c91369
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fft__bin__example__f32_8c_source.html
@@ -0,0 +1,163 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fft_bin_example_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__f32_8c.html
new file mode 100644
index 0000000..6f1d99a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fill_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fill_f32 (float32_t value, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__f32_8c_source.html
new file mode 100644
index 0000000..8180689
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__f32_8c_source.html
@@ -0,0 +1,161 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q15_8c.html
new file mode 100644
index 0000000..ecadb61
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fill_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fill_q15 (q15_t value, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q15_8c_source.html
new file mode 100644
index 0000000..104ed93
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q15_8c_source.html
@@ -0,0 +1,164 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q31_8c.html
new file mode 100644
index 0000000..c8e9566
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fill_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fill_q31 (q31_t value, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q31_8c_source.html
new file mode 100644
index 0000000..ff91f12
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q31_8c_source.html
@@ -0,0 +1,161 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q7_8c.html
new file mode 100644
index 0000000..c460095
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fill_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fill_q7 (q7_t value, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q7_8c_source.html
new file mode 100644
index 0000000..3d9697d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fill__q7_8c_source.html
@@ -0,0 +1,162 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fill_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__f32_8c.html
new file mode 100644
index 0000000..2191d97
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__f32_8c_source.html
new file mode 100644
index 0000000..08e6065
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__f32_8c_source.html
@@ -0,0 +1,344 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q15_8c.html
new file mode 100644
index 0000000..e138f18
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q15_8c_source.html
new file mode 100644
index 0000000..bd50191
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q15_8c_source.html
@@ -0,0 +1,238 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_fast_q15.c Source File
+
+
+
+
+
+
+
+
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+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q31_8c.html
new file mode 100644
index 0000000..04834a1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q31_8c_source.html
new file mode 100644
index 0000000..6b965a2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__fast__q31_8c_source.html
@@ -0,0 +1,257 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_fast_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__f32_8c.html
new file mode 100644
index 0000000..648ce3b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__f32_8c_source.html
new file mode 100644
index 0000000..d3f76da
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__f32_8c_source.html
@@ -0,0 +1,147 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q15_8c.html
new file mode 100644
index 0000000..c00d58e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q15_8c_source.html
new file mode 100644
index 0000000..efe8740
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q15_8c_source.html
@@ -0,0 +1,148 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q31_8c.html
new file mode 100644
index 0000000..7aa5afe
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q31_8c_source.html
new file mode 100644
index 0000000..2df1f14
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__init__q31_8c_source.html
@@ -0,0 +1,147 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q15_8c.html
new file mode 100644
index 0000000..cd67a34
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q15_8c_source.html
new file mode 100644
index 0000000..00aeb50
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q15_8c_source.html
@@ -0,0 +1,325 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q31_8c.html
new file mode 100644
index 0000000..6ecbaaa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_decimate_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q31_8c_source.html
new file mode 100644
index 0000000..324f51e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__decimate__q31_8c_source.html
@@ -0,0 +1,344 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_q31.c Source File
+
+
+
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+
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+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__example__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__example__f32_8c.html
new file mode 100644
index 0000000..ee46c0e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__example__f32_8c.html
@@ -0,0 +1,314 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_fir_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include "math_helper.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define TEST_LENGTH_SAMPLES   320
#define SNR_THRESHOLD_F32   140.0f
#define BLOCK_SIZE   32
#define NUM_TAPS   29

+Functions
int32_t main (void)

+Variables
float32_t testInput_f32_1kHz_15kHz [TEST_LENGTH_SAMPLES]
float32_t refOutput [TEST_LENGTH_SAMPLES]
static float32_t testOutput [TEST_LENGTH_SAMPLES]
static float32_t firStateF32 [BLOCK_SIZE+NUM_TAPS-1]
const float32_t firCoeffs32 [NUM_TAPS]
uint32_t blockSize = BLOCK_SIZE
uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE
float32_t snr

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES   320

+

+

+
+
Definition at line 116 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD_F32   140.0f

+

+

+
Examples: 
arm_fir_example_f32.c, and arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 117 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define BLOCK_SIZE   32

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+
Definition at line 118 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUM_TAPS   29

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+
Definition at line 119 of file arm_fir_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 166 of file arm_fir_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
float32_t refOutput[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TEST_LENGTH_SAMPLES] [static]

+

+

+
+
Definition at line 133 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t firStateF32[BLOCK_SIZE+NUM_TAPS-1] [static]

+

+

+
+
Definition at line 139 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t firCoeffs32[NUM_TAPS]

+

+

+Initial value:
 { 
+-0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, 
+-0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, 
++0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, 
++0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f 
+}
+
Examples: 
arm_fir_example_f32.c.

+

+
Definition at line 146 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t blockSize = BLOCK_SIZE

+

+

+
Examples: 
arm_fir_example_f32.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 157 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE

+

+

+
Examples: 
arm_fir_example_f32.c.

+

+
Definition at line 158 of file arm_fir_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr

+

+

+
+
Definition at line 160 of file arm_fir_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__example__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__example__f32_8c_source.html
new file mode 100644
index 0000000..fe4d3aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__example__f32_8c_source.html
@@ -0,0 +1,208 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_example_f32.c Source File
+
+
+
+
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+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__f32_8c.html
new file mode 100644
index 0000000..a3da1e9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_f32 (const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__f32_8c_source.html
new file mode 100644
index 0000000..e817d7c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__f32_8c_source.html
@@ -0,0 +1,416 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q15_8c.html
new file mode 100644
index 0000000..8ba6f40
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_fast_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q15_8c_source.html
new file mode 100644
index 0000000..93947ef
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q15_8c_source.html
@@ -0,0 +1,320 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_fast_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q31_8c.html
new file mode 100644
index 0000000..60079ce
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_fast_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q31_8c_source.html
new file mode 100644
index 0000000..cb4ecec
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__fast__q31_8c_source.html
@@ -0,0 +1,342 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_fast_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__f32_8c.html
new file mode 100644
index 0000000..ea1fb61
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_init_f32 (arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__f32_8c_source.html
new file mode 100644
index 0000000..923683c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__f32_8c_source.html
@@ -0,0 +1,131 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q15_8c.html
new file mode 100644
index 0000000..e072bfe
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_init_q15 (arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q15_8c_source.html
new file mode 100644
index 0000000..1eed913
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q15_8c_source.html
@@ -0,0 +1,172 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q31_8c.html
new file mode 100644
index 0000000..cbd399b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_init_q31 (arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q31_8c_source.html
new file mode 100644
index 0000000..8f9f025
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q31_8c_source.html
@@ -0,0 +1,131 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q7_8c.html
new file mode 100644
index 0000000..1f1549f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_init_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_init_q7 (arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q7_8c_source.html
new file mode 100644
index 0000000..f9735f0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__init__q7_8c_source.html
@@ -0,0 +1,132 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_init_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__f32_8c.html
new file mode 100644
index 0000000..b572895
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_interpolate_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__f32_8c_source.html
new file mode 100644
index 0000000..562656f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__f32_8c_source.html
@@ -0,0 +1,369 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__f32_8c.html
new file mode 100644
index 0000000..e728cda
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_interpolate_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__f32_8c_source.html
new file mode 100644
index 0000000..da0b102
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__f32_8c_source.html
@@ -0,0 +1,150 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q15_8c.html
new file mode 100644
index 0000000..8770df2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_interpolate_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q15_8c_source.html
new file mode 100644
index 0000000..9c48e93
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q15_8c_source.html
@@ -0,0 +1,149 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q31_8c.html
new file mode 100644
index 0000000..9a0a55f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_interpolate_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q31_8c_source.html
new file mode 100644
index 0000000..7d7407d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__init__q31_8c_source.html
@@ -0,0 +1,149 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q15_8c.html
new file mode 100644
index 0000000..48d14c6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_interpolate_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q15_8c_source.html
new file mode 100644
index 0000000..526d1aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q15_8c_source.html
@@ -0,0 +1,392 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q31_8c.html
new file mode 100644
index 0000000..40bd2e7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_interpolate_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q31_8c_source.html
new file mode 100644
index 0000000..2649b86
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__interpolate__q31_8c_source.html
@@ -0,0 +1,382 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__f32_8c.html
new file mode 100644
index 0000000..23fbdc7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_lattice_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__f32_8c_source.html
new file mode 100644
index 0000000..d49d771
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__f32_8c_source.html
@@ -0,0 +1,480 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__f32_8c.html
new file mode 100644
index 0000000..630fb10
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_lattice_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__f32_8c_source.html
new file mode 100644
index 0000000..efc2413
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__f32_8c_source.html
@@ -0,0 +1,127 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q15_8c.html
new file mode 100644
index 0000000..3819d45
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_lattice_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q15_8c_source.html
new file mode 100644
index 0000000..8074450
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q15_8c_source.html
@@ -0,0 +1,127 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q31_8c.html
new file mode 100644
index 0000000..3caba1a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_lattice_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q31_8c_source.html
new file mode 100644
index 0000000..2406c94
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__init__q31_8c_source.html
@@ -0,0 +1,127 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q15_8c.html
new file mode 100644
index 0000000..ba6230f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_lattice_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q15_8c_source.html
new file mode 100644
index 0000000..3f58e8c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q15_8c_source.html
@@ -0,0 +1,579 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q31_8c.html
new file mode 100644
index 0000000..cd8ecfb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_lattice_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q31_8c_source.html
new file mode 100644
index 0000000..c67c9f8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__lattice__q31_8c_source.html
@@ -0,0 +1,487 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q15_8c.html
new file mode 100644
index 0000000..584d689
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q15_8c_source.html
new file mode 100644
index 0000000..a72742c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q15_8c_source.html
@@ -0,0 +1,408 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q31_8c.html
new file mode 100644
index 0000000..3cdf06a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q31_8c_source.html
new file mode 100644
index 0000000..180d2cd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q31_8c_source.html
@@ -0,0 +1,424 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q7_8c.html
new file mode 100644
index 0000000..3eb3d09
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_q7 (const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q7_8c_source.html
new file mode 100644
index 0000000..a53eeb3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__q7_8c_source.html
@@ -0,0 +1,429 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__f32_8c.html
new file mode 100644
index 0000000..15470fc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__f32_8c_source.html
new file mode 100644
index 0000000..d718ec1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__f32_8c_source.html
@@ -0,0 +1,353 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__f32_8c.html
new file mode 100644
index 0000000..d51dbc8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__f32_8c_source.html
new file mode 100644
index 0000000..71362e3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__f32_8c_source.html
@@ -0,0 +1,139 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q15_8c.html
new file mode 100644
index 0000000..037f0f5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q15_8c_source.html
new file mode 100644
index 0000000..fc1d687
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q15_8c_source.html
@@ -0,0 +1,139 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q31_8c.html
new file mode 100644
index 0000000..21f6344
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q31_8c_source.html
new file mode 100644
index 0000000..b943d7f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q31_8c_source.html
@@ -0,0 +1,139 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q7_8c.html
new file mode 100644
index 0000000..58985ec
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_init_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q7_8c_source.html
new file mode 100644
index 0000000..4a75391
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__init__q7_8c_source.html
@@ -0,0 +1,139 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_init_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q15_8c.html
new file mode 100644
index 0000000..0105940
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q15_8c_source.html
new file mode 100644
index 0000000..88a9a3c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q15_8c_source.html
@@ -0,0 +1,447 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q31_8c.html
new file mode 100644
index 0000000..a804e84
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q31_8c_source.html
new file mode 100644
index 0000000..73c7590
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q31_8c_source.html
@@ -0,0 +1,414 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q7_8c.html
new file mode 100644
index 0000000..e972a69
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_fir_sparse_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q7_8c_source.html
new file mode 100644
index 0000000..1ea8590
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__fir__sparse__q7_8c_source.html
@@ -0,0 +1,435 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q15_8c.html
new file mode 100644
index 0000000..e111bf6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_float_to_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_float_to_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_float_to_q15 (float32_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q15_8c_source.html
new file mode 100644
index 0000000..33fe550
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q15_8c_source.html
@@ -0,0 +1,230 @@
+
+
+
+
+CMSIS DSP Software Library: arm_float_to_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q31_8c.html
new file mode 100644
index 0000000..3f66fd8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_float_to_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_float_to_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_float_to_q31 (float32_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q31_8c_source.html
new file mode 100644
index 0000000..5fb55c3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q31_8c_source.html
@@ -0,0 +1,233 @@
+
+
+
+
+CMSIS DSP Software Library: arm_float_to_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q7_8c.html
new file mode 100644
index 0000000..7ef7c98
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_float_to_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_float_to_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_float_to_q7 (float32_t *pSrc, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q7_8c_source.html
new file mode 100644
index 0000000..844731d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__float__to__q7_8c_source.html
@@ -0,0 +1,230 @@
+
+
+
+
+CMSIS DSP Software Library: arm_float_to_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__graphic__equalizer__example__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__graphic__equalizer__example__q31_8c.html
new file mode 100644
index 0000000..7fb393a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__graphic__equalizer__example__q31_8c.html
@@ -0,0 +1,414 @@
+
+
+
+
+CMSIS DSP Software Library: arm_graphic_equalizer_example_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_graphic_equalizer_example_q31.c File Reference
  

+

+

+#include "arm_math.h"

+#include "math_helper.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+

+Defines
#define TESTLENGTH   320
#define BLOCKSIZE   32
#define NUMBLOCKS   (TESTLENGTH/BLOCKSIZE)
#define NUMSTAGES   2
#define SNR_THRESHOLD_F32   98

+Functions
int32_t main (void)

+Variables
float32_t testInput_f32 [TESTLENGTH]
static float32_t testOutput [TESTLENGTH]
float32_t testRefOutput_f32 [TESTLENGTH]
static q63_t biquadStateBand1Q31 [4 *2]
static q63_t biquadStateBand2Q31 [4 *2]
static q31_t biquadStateBand3Q31 [4 *2]
static q31_t biquadStateBand4Q31 [4 *2]
static q31_t biquadStateBand5Q31 [4 *2]
q31_t inputQ31 [BLOCKSIZE]
q31_t outputQ31 [BLOCKSIZE]
const q31_t coeffTable [950]
int gainDB [5] = {0, -3, 6, 4, -6}
float32_t snr

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define TESTLENGTH   320

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 117 of file arm_graphic_equalizer_example_q31.c.

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+      
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#define BLOCKSIZE   32

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 120 of file arm_graphic_equalizer_example_q31.c.

+
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+      
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#define NUMBLOCKS   (TESTLENGTH/BLOCKSIZE)

+

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+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 123 of file arm_graphic_equalizer_example_q31.c.

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#define NUMSTAGES   2

+

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Examples: 
arm_graphic_equalizer_example_q31.c.

+

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Definition at line 126 of file arm_graphic_equalizer_example_q31.c.

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#define SNR_THRESHOLD_F32   98

+

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Definition at line 128 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

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Definition at line 285 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32[TESTLENGTH]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c, arm_signal_converge_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 83 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TESTLENGTH] [static]

+

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+
Definition at line 135 of file arm_graphic_equalizer_example_q31.c.

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+

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+      
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float32_t testRefOutput_f32[TESTLENGTH]

+

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Definition at line 141 of file arm_convolution_example_f32.c.

+
+

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+

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+      
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q63_t biquadStateBand1Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 143 of file arm_graphic_equalizer_example_q31.c.

+
+

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+

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+      
+        
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q63_t biquadStateBand2Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 144 of file arm_graphic_equalizer_example_q31.c.

+
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+

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+      
+        
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q31_t biquadStateBand3Q31[4 *2] [static]

+

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+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 145 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t biquadStateBand4Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 146 of file arm_graphic_equalizer_example_q31.c.

+
+

+

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+

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+      
+        
+          
+        
+      
q31_t biquadStateBand5Q31[4 *2] [static]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 147 of file arm_graphic_equalizer_example_q31.c.

+
+

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+

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+      
+        
+          
+        
+      
q31_t inputQ31[BLOCKSIZE]

+

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+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 153 of file arm_graphic_equalizer_example_q31.c.

+
+

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+

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+      
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+      
q31_t outputQ31[BLOCKSIZE]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 154 of file arm_graphic_equalizer_example_q31.c.

+
+

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+

+

+      
+        
+          
+        
+      
const q31_t coeffTable[950]

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 167 of file arm_graphic_equalizer_example_q31.c.

+
+

+

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+

+

+      
+        
+          
+        
+      
int gainDB[5] = {0, -3, 6, 4, -6}

+

+

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 276 of file arm_graphic_equalizer_example_q31.c.

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+        
+      
float32_t snr

+

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+
Definition at line 278 of file arm_graphic_equalizer_example_q31.c.

+
+

+

+

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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__graphic__equalizer__example__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__graphic__equalizer__example__q31_8c_source.html
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+CMSIS DSP Software Library: arm_graphic_equalizer_example_q31.c Source File
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+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__f32_8c.html
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index 0000000..53bf9eb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__f32_8c.html
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+
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+
+
+CMSIS DSP Software Library: arm_iir_lattice_f32.c File Reference
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+
+
+
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+
+
+
+
+

+  

+Functions  

+  

+
arm_iir_lattice_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__f32_8c_source.html
new file mode 100644
index 0000000..829588e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__f32_8c_source.html
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+CMSIS DSP Software Library: arm_iir_lattice_f32.c Source File
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+

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+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__f32_8c.html
new file mode 100644
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+CMSIS DSP Software Library: arm_iir_lattice_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_iir_lattice_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__f32_8c_source.html
new file mode 100644
index 0000000..606ef4f
--- /dev/null
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@@ -0,0 +1,133 @@
+
+
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+
+CMSIS DSP Software Library: arm_iir_lattice_init_f32.c Source File
+
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q15_8c.html
new file mode 100644
index 0000000..29f5ab5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_iir_lattice_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q15_8c_source.html
new file mode 100644
index 0000000..1fcbc32
--- /dev/null
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@@ -0,0 +1,133 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_init_q15.c Source File
+
+
+
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+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q31_8c.html
new file mode 100644
index 0000000..659c893
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_iir_lattice_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q31_8c_source.html
new file mode 100644
index 0000000..8856244
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__init__q31_8c_source.html
@@ -0,0 +1,133 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_init_q31.c Source File
+
+
+
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+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q15_8c.html
new file mode 100644
index 0000000..8c1d940
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_iir_lattice_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q15_8c_source.html
new file mode 100644
index 0000000..a3c70e0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q15_8c_source.html
@@ -0,0 +1,445 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_q15.c Source File
+
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q31_8c.html
new file mode 100644
index 0000000..2fc40f9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_iir_lattice_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q31_8c_source.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__iir__lattice__q31_8c_source.html
@@ -0,0 +1,385 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_q31.c Source File
+
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__linear__interp__example__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__linear__interp__example__f32_8c.html
new file mode 100644
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@@ -0,0 +1,287 @@
+
+
+
+
+CMSIS DSP Software Library: arm_linear_interp_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_linear_interp_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include "math_helper.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
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+
+
+
+
+

+Defines
#define SNR_THRESHOLD   90
#define TEST_LENGTH_SAMPLES   10
#define XSPACING   (0.00005f)

+Functions
int32_t main (void)

+Variables
float32_t testInputSin_f32 [TEST_LENGTH_SAMPLES]
float32_t testRefSinOutput32_f32 [TEST_LENGTH_SAMPLES]
float32_t testOutput [TEST_LENGTH_SAMPLES]
float32_t testLinIntOutput [TEST_LENGTH_SAMPLES]
float32_t arm_linear_interep_table [188495]
float32_t snr1
float32_t snr2

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD   90

+

+

+
+
Definition at line 73 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES   10

+

+

+
+
Definition at line 74 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define XSPACING   (0.00005f)

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 75 of file arm_linear_interp_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 123 of file arm_linear_interp_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t testInputSin_f32[TEST_LENGTH_SAMPLES]

+

+

+Initial value:
  
+{
+    -0.649716504673081170,  -2.501723745497831200,  0.188250329003310100,   0.432092748487532540,   -1.722010988459680800,  1.788766476323060600,   1.786136060975809500,   -0.056525543169408797,  
+    0.491596272728153760,   0.262309671126153390   
+}
+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 83 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES]

+

+

+Initial value:
   
+{
+    -0.604960695383043530,  -0.597090287967934840,  0.187140422442966500,   0.418772124875992690,   -0.988588831792106880,  0.976338412038794010,   0.976903856413481100,   -0.056495446835214236,  
+    0.472033731854734240,   0.259311907228582830
+}
+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 93 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput[TEST_LENGTH_SAMPLES]

+

+

+
+
Definition at line 102 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testLinIntOutput[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 107 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_linear_interep_table[188495]

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr1

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 117 of file arm_linear_interp_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr2

+

+

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 118 of file arm_linear_interp_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__linear__interp__example__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__linear__interp__example__f32_8c_source.html
new file mode 100644
index 0000000..3fe9dee
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__linear__interp__example__f32_8c_source.html
@@ -0,0 +1,207 @@
+
+
+
+
+CMSIS DSP Software Library: arm_linear_interp_example_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__f32_8c.html
new file mode 100644
index 0000000..f76d803
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_f32 (const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__f32_8c_source.html
new file mode 100644
index 0000000..1787962
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__f32_8c_source.html
@@ -0,0 +1,366 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__f32_8c.html
new file mode 100644
index 0000000..95d8928
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_init_f32 (arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__f32_8c_source.html
new file mode 100644
index 0000000..7be3e8b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__f32_8c_source.html
@@ -0,0 +1,131 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q15_8c.html
new file mode 100644
index 0000000..6b2b593
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_init_q15 (arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q15_8c_source.html
new file mode 100644
index 0000000..d7485e9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q15_8c_source.html
@@ -0,0 +1,136 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q31_8c.html
new file mode 100644
index 0000000..65e5481
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_init_q31 (arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q31_8c_source.html
new file mode 100644
index 0000000..3f31d67
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__init__q31_8c_source.html
@@ -0,0 +1,136 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__f32_8c.html
new file mode 100644
index 0000000..09bae67
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_norm_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__f32_8c_source.html
new file mode 100644
index 0000000..1b609ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__f32_8c_source.html
@@ -0,0 +1,398 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__f32_8c.html
new file mode 100644
index 0000000..34ace14
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_norm_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__f32_8c_source.html
new file mode 100644
index 0000000..813bda8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__f32_8c_source.html
@@ -0,0 +1,138 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q15_8c.html
new file mode 100644
index 0000000..37afc92
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q15_8c.html
@@ -0,0 +1,84 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_norm_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q15_8c_source.html
new file mode 100644
index 0000000..f98cc7f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q15_8c_source.html
@@ -0,0 +1,146 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q31_8c.html
new file mode 100644
index 0000000..5f523b9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q31_8c.html
@@ -0,0 +1,84 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_norm_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:18 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q31_8c_source.html
new file mode 100644
index 0000000..b257f22
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__init__q31_8c_source.html
@@ -0,0 +1,146 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q15_8c.html
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index 0000000..12852f9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_norm_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q15_8c_source.html
new file mode 100644
index 0000000..efe324a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q15_8c_source.html
@@ -0,0 +1,420 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q31_8c.html
new file mode 100644
index 0000000..dc1d25b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_norm_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q31_8c_source.html
new file mode 100644
index 0000000..e857f90
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__norm__q31_8c_source.html
@@ -0,0 +1,437 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__q15_8c.html
new file mode 100644
index 0000000..a867659
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_q15 (const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__q15_8c_source.html
new file mode 100644
index 0000000..4270b3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__q15_8c_source.html
@@ -0,0 +1,369 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__q31_8c.html
new file mode 100644
index 0000000..9239af4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_lms_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_lms_q31 (const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__q31_8c_source.html
new file mode 100644
index 0000000..7fe78df
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__lms__q31_8c_source.html
@@ -0,0 +1,382 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__f32_8c.html
new file mode 100644
index 0000000..2b28518
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_add_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_add_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__f32_8c_source.html
new file mode 100644
index 0000000..75cb273
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__f32_8c_source.html
@@ -0,0 +1,194 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_add_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q15_8c.html
new file mode 100644
index 0000000..4d694ff
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_add_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_add_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q15_8c_source.html
new file mode 100644
index 0000000..7c7e5d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q15_8c_source.html
@@ -0,0 +1,205 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_add_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q31_8c.html
new file mode 100644
index 0000000..14c8e85
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_add_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_add_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q31_8c_source.html
new file mode 100644
index 0000000..6b603d1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__add__q31_8c_source.html
@@ -0,0 +1,204 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_add_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__f32_8c.html
new file mode 100644
index 0000000..90f2590
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mat_init_f32 (arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__f32_8c_source.html
new file mode 100644
index 0000000..55986e4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__f32_8c_source.html
@@ -0,0 +1,126 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q15_8c.html
new file mode 100644
index 0000000..c073677
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mat_init_q15 (arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q15_8c_source.html
new file mode 100644
index 0000000..c2f5ec3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q15_8c_source.html
@@ -0,0 +1,127 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q31_8c.html
new file mode 100644
index 0000000..a822f85
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mat_init_q31 (arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q31_8c_source.html
new file mode 100644
index 0000000..78c8a2c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__init__q31_8c_source.html
@@ -0,0 +1,126 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__inverse__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__inverse__f32_8c.html
new file mode 100644
index 0000000..8e211dc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__inverse__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_inverse_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_inverse_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__inverse__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__inverse__f32_8c_source.html
new file mode 100644
index 0000000..46a5d7e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__inverse__f32_8c_source.html
@@ -0,0 +1,693 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_inverse_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__f32_8c.html
new file mode 100644
index 0000000..55e68df
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_mult_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__f32_8c_source.html
new file mode 100644
index 0000000..3fc42a5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__f32_8c_source.html
@@ -0,0 +1,305 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q15_8c.html
new file mode 100644
index 0000000..9bbd1d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_fast_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_mult_fast_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q15_8c_source.html
new file mode 100644
index 0000000..3d98de7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q15_8c_source.html
@@ -0,0 +1,312 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_fast_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q31_8c.html
new file mode 100644
index 0000000..841d4c5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_fast_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_mult_fast_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q31_8c_source.html
new file mode 100644
index 0000000..35c2be4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__fast__q31_8c_source.html
@@ -0,0 +1,232 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_fast_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q15_8c.html
new file mode 100644
index 0000000..a7c43c1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_mult_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q15_8c_source.html
new file mode 100644
index 0000000..908c17a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q15_8c_source.html
@@ -0,0 +1,412 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q31_8c.html
new file mode 100644
index 0000000..340601c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_mult_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q31_8c_source.html
new file mode 100644
index 0000000..364177e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__mult__q31_8c_source.html
@@ -0,0 +1,313 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_mult_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__f32_8c.html
new file mode 100644
index 0000000..af76a94
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_scale_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_scale_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__f32_8c_source.html
new file mode 100644
index 0000000..83d5a64
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__f32_8c_source.html
@@ -0,0 +1,189 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_scale_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q15_8c.html
new file mode 100644
index 0000000..f0165bc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_scale_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_scale_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q15_8c_source.html
new file mode 100644
index 0000000..da0e424
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q15_8c_source.html
@@ -0,0 +1,195 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_scale_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q31_8c.html
new file mode 100644
index 0000000..fa9a500
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_scale_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_scale_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q31_8c_source.html
new file mode 100644
index 0000000..887007e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__scale__q31_8c_source.html
@@ -0,0 +1,197 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_scale_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__f32_8c.html
new file mode 100644
index 0000000..3f5edee
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_sub_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_sub_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__f32_8c_source.html
new file mode 100644
index 0000000..75e8317
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__f32_8c_source.html
@@ -0,0 +1,192 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_sub_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q15_8c.html
new file mode 100644
index 0000000..86e6da0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_sub_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_sub_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q15_8c_source.html
new file mode 100644
index 0000000..21ef30f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q15_8c_source.html
@@ -0,0 +1,202 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_sub_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q31_8c.html
new file mode 100644
index 0000000..c9aee4f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_sub_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mat_sub_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q31_8c_source.html
new file mode 100644
index 0000000..2511fb2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__sub__q31_8c_source.html
@@ -0,0 +1,204 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mat_sub_q31.c Source File
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Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__f32_8c.html
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+CMSIS DSP Software Library: arm_mat_trans_f32.c File Reference
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+

+  

+Functions  

+  

+
arm_mat_trans_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)

+

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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__f32_8c_source.html
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+CMSIS DSP Software Library: arm_mat_trans_f32.c Source File
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Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q15_8c.html
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+CMSIS DSP Software Library: arm_mat_trans_q15.c File Reference
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+  

+Functions  

+  

+
arm_mat_trans_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst)

+

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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q15_8c_source.html
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+CMSIS DSP Software Library: arm_mat_trans_q15.c Source File
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Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q31_8c.html
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+CMSIS DSP Software Library: arm_mat_trans_q31.c File Reference
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+  

+Functions  

+  

+
arm_mat_trans_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst)

+

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Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mat__trans__q31_8c_source.html
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+CMSIS DSP Software Library: arm_mat_trans_q31.c Source File
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+
+
Generated on Fri Jul 15 2011 13:16:16 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__math_8h.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__math_8h.html
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+CMSIS DSP Software Library: arm_math.h File Reference
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+  

+Data Structures |
+Defines |
+Typedefs |
+Enumerations |
+Functions  

+  

+
arm_math.h File Reference
  

+

+

+#include "ARMCM4.h"

+#include "string.h"

+#include "math.h"

+
+
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+Data Structures
struct  arm_fir_instance_q7
 Instance structure for the Q7 FIR filter.  More...
struct  arm_fir_instance_q15
 Instance structure for the Q15 FIR filter.  More...
struct  arm_fir_instance_q31
 Instance structure for the Q31 FIR filter.  More...
struct  arm_fir_instance_f32
 Instance structure for the floating-point FIR filter.  More...
struct  arm_biquad_casd_df1_inst_q15
 Instance structure for the Q15 Biquad cascade filter.  More...
struct  arm_biquad_casd_df1_inst_q31
 Instance structure for the Q31 Biquad cascade filter.  More...
struct  arm_biquad_casd_df1_inst_f32
 Instance structure for the floating-point Biquad cascade filter.  More...
struct  arm_matrix_instance_f32
 Instance structure for the floating-point matrix structure.  More...
struct  arm_matrix_instance_q15
 Instance structure for the Q15 matrix structure.  More...
struct  arm_matrix_instance_q31
 Instance structure for the Q31 matrix structure.  More...
struct  arm_pid_instance_q15
 Instance structure for the Q15 PID Control.  More...
struct  arm_pid_instance_q31
 Instance structure for the Q31 PID Control.  More...
struct  arm_pid_instance_f32
 Instance structure for the floating-point PID Control.  More...
struct  arm_linear_interp_instance_f32
 Instance structure for the floating-point Linear Interpolate function.  More...
struct  arm_bilinear_interp_instance_f32
 Instance structure for the floating-point bilinear interpolation function.  More...
struct  arm_bilinear_interp_instance_q31
 Instance structure for the Q31 bilinear interpolation function.  More...
struct  arm_bilinear_interp_instance_q15
 Instance structure for the Q15 bilinear interpolation function.  More...
struct  arm_bilinear_interp_instance_q7
 Instance structure for the Q15 bilinear interpolation function.  More...
struct  arm_cfft_radix4_instance_q15
 Instance structure for the Q15 CFFT/CIFFT function.  More...
struct  arm_cfft_radix4_instance_q31
 Instance structure for the Q31 CFFT/CIFFT function.  More...
struct  arm_cfft_radix4_instance_f32
 Instance structure for the floating-point CFFT/CIFFT function.  More...
struct  arm_rfft_instance_q15
 Instance structure for the Q15 RFFT/RIFFT function.  More...
struct  arm_rfft_instance_q31
 Instance structure for the Q31 RFFT/RIFFT function.  More...
struct  arm_rfft_instance_f32
 Instance structure for the floating-point RFFT/RIFFT function.  More...
struct  arm_dct4_instance_f32
 Instance structure for the floating-point DCT4/IDCT4 function.  More...
struct  arm_dct4_instance_q31
 Instance structure for the Q31 DCT4/IDCT4 function.  More...
struct  arm_dct4_instance_q15
 Instance structure for the Q15 DCT4/IDCT4 function.  More...
struct  arm_fir_decimate_instance_q15
 Instance structure for the Q15 FIR decimator.  More...
struct  arm_fir_decimate_instance_q31
 Instance structure for the Q31 FIR decimator.  More...
struct  arm_fir_decimate_instance_f32
 Instance structure for the floating-point FIR decimator.  More...
struct  arm_fir_interpolate_instance_q15
 Instance structure for the Q15 FIR interpolator.  More...
struct  arm_fir_interpolate_instance_q31
 Instance structure for the Q31 FIR interpolator.  More...
struct  arm_fir_interpolate_instance_f32
 Instance structure for the floating-point FIR interpolator.  More...
struct  arm_biquad_cas_df1_32x64_ins_q31
 Instance structure for the high precision Q31 Biquad cascade filter.  More...
struct  arm_biquad_cascade_df2T_instance_f32
 Instance structure for the floating-point transposed direct form II Biquad cascade filter.  More...
struct  arm_fir_lattice_instance_q15
 Instance structure for the Q15 FIR lattice filter.  More...
struct  arm_fir_lattice_instance_q31
 Instance structure for the Q31 FIR lattice filter.  More...
struct  arm_fir_lattice_instance_f32
 Instance structure for the floating-point FIR lattice filter.  More...
struct  arm_iir_lattice_instance_q15
 Instance structure for the Q15 IIR lattice filter.  More...
struct  arm_iir_lattice_instance_q31
 Instance structure for the Q31 IIR lattice filter.  More...
struct  arm_iir_lattice_instance_f32
 Instance structure for the floating-point IIR lattice filter.  More...
struct  arm_lms_instance_f32
 Instance structure for the floating-point LMS filter.  More...
struct  arm_lms_instance_q15
 Instance structure for the Q15 LMS filter.  More...
struct  arm_lms_instance_q31
 Instance structure for the Q31 LMS filter.  More...
struct  arm_lms_norm_instance_f32
 Instance structure for the floating-point normalized LMS filter.  More...
struct  arm_lms_norm_instance_q31
 Instance structure for the Q31 normalized LMS filter.  More...
struct  arm_lms_norm_instance_q15
 Instance structure for the Q15 normalized LMS filter.  More...
struct  arm_fir_sparse_instance_f32
 Instance structure for the floating-point sparse FIR filter.  More...
struct  arm_fir_sparse_instance_q31
 Instance structure for the Q31 sparse FIR filter.  More...
struct  arm_fir_sparse_instance_q15
 Instance structure for the Q15 sparse FIR filter.  More...
struct  arm_fir_sparse_instance_q7
 Instance structure for the Q7 sparse FIR filter.  More...

+Defines
#define __CMSIS_GENERIC
#define DELTA_Q31   (0x100)
#define DELTA_Q15   0x5
#define INDEX_MASK   0x0000003F
#define PI   3.14159265358979f
#define TABLE_SIZE   256
#define TABLE_SPACING_Q31   0x800000
#define TABLE_SPACING_Q15   0x80
#define INPUT_SPACING   0xB60B61
#define __SIMD32(addr)   (*(int32_t **) & (addr))
#define __PACKq7(v0, v1, v2, v3)

+Typedefs
typedef int8_t q7_t
typedef int16_t q15_t
typedef int32_t q31_t
typedef int64_t q63_t
typedef float float32_t
typedef double float64_t

+Enumerations
enum  arm_status { 

+  ARM_MATH_SUCCESS =  0, 
+ARM_MATH_ARGUMENT_ERROR =  -1, 
+ARM_MATH_LENGTH_ERROR =  -2, 
+ARM_MATH_SIZE_MISMATCH =  -3, 
+

+  ARM_MATH_NANINF =  -4, 
+ARM_MATH_SINGULAR =  -5, 
+ARM_MATH_TEST_FAILURE =  -6
+

+ }

+Functions
static __INLINE q31_t clip_q63_to_q31 (q63_t x)
static __INLINE q15_t clip_q63_to_q15 (q63_t x)
static __INLINE q7_t clip_q31_to_q7 (q31_t x)
static __INLINE q15_t clip_q31_to_q15 (q31_t x)
static __INLINE q63_t mult32x64 (q63_t x, q31_t y)
static __INLINE uint32_t arm_recip_q31 (q31_t in, q31_t *dst, q31_t *pRecipTable)
static __INLINE uint32_t arm_recip_q15 (q15_t in, q15_t *dst, q15_t *pRecipTable)
void arm_fir_q7 (const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
void arm_fir_init_q7 (arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize)
void arm_fir_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_fir_fast_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
arm_status arm_fir_init_q15 (arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
void arm_fir_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_fast_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_init_q31 (arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
void arm_fir_f32 (const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_fir_init_f32 (arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift)
void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift)
void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst)
arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)
arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst)
arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst)
void arm_mat_init_q31 (arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData)
void arm_mat_init_q15 (arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData)
void arm_mat_init_f32 (arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData)
void arm_pid_init_f32 (arm_pid_instance_f32 *S, int32_t resetStateFlag)
void arm_pid_reset_f32 (arm_pid_instance_f32 *S)
void arm_pid_init_q31 (arm_pid_instance_q31 *S, int32_t resetStateFlag)
void arm_pid_reset_q31 (arm_pid_instance_q31 *S)
void arm_pid_init_q15 (arm_pid_instance_q15 *S, int32_t resetStateFlag)
void arm_pid_reset_q15 (arm_pid_instance_q15 *S)
void arm_mult_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
void arm_mult_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
void arm_mult_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
void arm_mult_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc)
arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc)
arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc)
arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
void arm_radix4_butterfly_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier)
void arm_radix4_butterfly_inverse_f32 (float32_t *pSrc, uint16_t fftLen, float32_t *pCoef, uint16_t twidCoefModifier, float32_t onebyfftLen)
void arm_bitreversal_f32 (float32_t *pSrc, uint16_t fftSize, uint16_t bitRevFactor, uint16_t *pBitRevTab)
void arm_radix4_butterfly_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
void arm_radix4_butterfly_inverse_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pCoef, uint32_t twidCoefModifier)
void arm_bitreversal_q31 (q31_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
void arm_radix4_butterfly_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
void arm_radix4_butterfly_inverse_q15 (q15_t *pSrc16, uint32_t fftLen, q15_t *pCoef16, uint32_t twidCoefModifier)
void arm_bitreversal_q15 (q15_t *pSrc, uint32_t fftLen, uint16_t bitRevFactor, uint16_t *pBitRevTab)
void arm_rfft_q15 (const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst)
arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *S, arm_cfft_radix4_instance_q15 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
void arm_rfft_q31 (const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst)
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *S, arm_cfft_radix4_instance_q31 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
void arm_rfft_f32 (const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst)
arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize)
void arm_dct4_f32 (const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer)
arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize)
void arm_dct4_q31 (const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer)
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize)
void arm_dct4_q15 (const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer)
void arm_add_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
void arm_add_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
void arm_add_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
void arm_add_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
void arm_sub_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
void arm_sub_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)
void arm_sub_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
void arm_sub_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
void arm_scale_f32 (float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize)
void arm_scale_q7 (q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize)
void arm_scale_q15 (q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize)
void arm_scale_q31 (q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize)
void arm_abs_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
void arm_abs_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_abs_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_abs_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result)
void arm_dot_prod_q7 (q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result)
void arm_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result)
void arm_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result)
void arm_shift_q7 (q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize)
void arm_shift_q15 (q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize)
void arm_shift_q31 (q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize)
void arm_offset_f32 (float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize)
void arm_offset_q7 (q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize)
void arm_offset_q15 (q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize)
void arm_offset_q31 (q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize)
void arm_negate_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_negate_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
void arm_negate_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_negate_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_copy_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_copy_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)
void arm_copy_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_copy_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fill_f32 (float32_t value, float32_t *pDst, uint32_t blockSize)
void arm_fill_q7 (q7_t value, q7_t *pDst, uint32_t blockSize)
void arm_fill_q15 (q15_t value, q15_t *pDst, uint32_t blockSize)
void arm_fill_q31 (q31_t value, q31_t *pDst, uint32_t blockSize)
void arm_conv_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
void arm_conv_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_conv_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_conv_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_conv_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_conv_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
arm_status arm_conv_partial_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints)
void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift)
void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState)
void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState)
void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState)
void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize)
void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize)
void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize)
void arm_lms_f32 (const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
void arm_lms_init_f32 (arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
void arm_lms_init_q15 (arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift)
void arm_lms_q15 (const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
void arm_lms_q31 (const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
void arm_lms_init_q31 (arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift)
void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift)
void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)
void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift)
void arm_correlate_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
void arm_correlate_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_correlate_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_correlate_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_correlate_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_correlate_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize)
void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize)
void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_sin_cos_f32 (float32_t theta, float32_t *pSinVal, float32_t *pCcosVal)
void arm_sin_cos_q31 (q31_t theta, q31_t *pSinVal, q31_t *pCosVal)
void arm_cmplx_conj_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_conj_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_conj_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_squared_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_squared_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_squared_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
static __INLINE float32_t arm_pid_f32 (arm_pid_instance_f32 *S, float32_t in)
static __INLINE q31_t arm_pid_q31 (arm_pid_instance_q31 *S, q31_t in)
static __INLINE q15_t arm_pid_q15 (arm_pid_instance_q15 *S, q15_t in)
arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *src, arm_matrix_instance_f32 *dst)
static __INLINE void arm_clarke_f32 (float32_t Ia, float32_t Ib, float32_t *pIalpha, float32_t *pIbeta)
static __INLINE void arm_clarke_q31 (q31_t Ia, q31_t Ib, q31_t *pIalpha, q31_t *pIbeta)
void arm_q7_to_q31 (q7_t *pSrc, q31_t *pDst, uint32_t blockSize)
static __INLINE void arm_inv_clarke_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pIa, float32_t *pIb)
static __INLINE void arm_inv_clarke_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pIa, q31_t *pIb)
void arm_q7_to_q15 (q7_t *pSrc, q15_t *pDst, uint32_t blockSize)
static __INLINE void arm_park_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pId, float32_t *pIq, float32_t sinVal, float32_t cosVal)
static __INLINE void arm_park_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pId, q31_t *pIq, q31_t sinVal, q31_t cosVal)
void arm_q7_to_float (q7_t *pSrc, float32_t *pDst, uint32_t blockSize)
static __INLINE void arm_inv_park_f32 (float32_t Id, float32_t Iq, float32_t *pIalpha, float32_t *pIbeta, float32_t sinVal, float32_t cosVal)
static __INLINE void arm_inv_park_q31 (q31_t Id, q31_t Iq, q31_t *pIalpha, q31_t *pIbeta, q31_t sinVal, q31_t cosVal)
void arm_q31_to_float (q31_t *pSrc, float32_t *pDst, uint32_t blockSize)
static __INLINE float32_t arm_linear_interp_f32 (arm_linear_interp_instance_f32 *S, float32_t x)
static __INLINE q31_t arm_linear_interp_q31 (q31_t *pYData, q31_t x, uint32_t nValues)
static __INLINE q15_t arm_linear_interp_q15 (q15_t *pYData, q31_t x, uint32_t nValues)
static __INLINE q7_t arm_linear_interp_q7 (q7_t *pYData, q31_t x, uint32_t nValues)
float32_t arm_sin_f32 (float32_t x)
q31_t arm_sin_q31 (q31_t x)
q15_t arm_sin_q15 (q15_t x)
float32_t arm_cos_f32 (float32_t x)
q31_t arm_cos_q31 (q31_t x)
q15_t arm_cos_q15 (q15_t x)
static __INLINE arm_status arm_sqrt_f32 (float32_t in, float32_t *pOut)
arm_status arm_sqrt_q31 (q31_t in, q31_t *pOut)
arm_status arm_sqrt_q15 (q15_t in, q15_t *pOut)
static __INLINE void arm_circularWrite_f32 (int32_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const int32_t *src, int32_t srcInc, uint32_t blockSize)
static __INLINE void arm_circularRead_f32 (int32_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, int32_t *dst, int32_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize)
static __INLINE void arm_circularWrite_q15 (q15_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const q15_t *src, int32_t srcInc, uint32_t blockSize)
static __INLINE void arm_circularRead_q15 (q15_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, q15_t *dst, q15_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize)
static __INLINE void arm_circularWrite_q7 (q7_t *circBuffer, int32_t L, uint16_t *writeOffset, int32_t bufferInc, const q7_t *src, int32_t srcInc, uint32_t blockSize)
static __INLINE void arm_circularRead_q7 (q7_t *circBuffer, int32_t L, int32_t *readOffset, int32_t bufferInc, q7_t *dst, q7_t *dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize)
void arm_power_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
void arm_power_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_power_q15 (q15_t *pSrc, uint32_t blockSize, q63_t *pResult)
void arm_power_q7 (q7_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_mean_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult)
void arm_mean_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
void arm_mean_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_mean_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_var_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_var_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
void arm_var_q15 (q15_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_rms_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_rms_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_rms_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
void arm_std_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_std_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_std_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
void arm_cmplx_mag_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)
void arm_cmplx_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult)
void arm_cmplx_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult)
void arm_cmplx_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult)
void arm_cmplx_mult_real_q15 (q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples)
void arm_cmplx_mult_real_q31 (q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples)
void arm_cmplx_mult_real_f32 (float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples)
void arm_min_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *result, uint32_t *index)
void arm_min_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
void arm_min_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
void arm_min_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
void arm_max_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)
void arm_max_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
void arm_max_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
void arm_max_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
void arm_cmplx_mult_cmplx_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples)
void arm_cmplx_mult_cmplx_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_mult_cmplx_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples)
void arm_float_to_q31 (float32_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_float_to_q15 (float32_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_float_to_q7 (float32_t *pSrc, q7_t *pDst, uint32_t blockSize)
void arm_q31_to_q15 (q31_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_q31_to_q7 (q31_t *pSrc, q7_t *pDst, uint32_t blockSize)
void arm_q15_to_float (q15_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_q15_to_q31 (q15_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_q15_to_q7 (q15_t *pSrc, q7_t *pDst, uint32_t blockSize)
static __INLINE float32_t arm_bilinear_interp_f32 (const arm_bilinear_interp_instance_f32 *S, float32_t X, float32_t Y)
static __INLINE q31_t arm_bilinear_interp_q31 (arm_bilinear_interp_instance_q31 *S, q31_t X, q31_t Y)
static __INLINE q15_t arm_bilinear_interp_q15 (arm_bilinear_interp_instance_q15 *S, q31_t X, q31_t Y)
static __INLINE q7_t arm_bilinear_interp_q7 (arm_bilinear_interp_instance_q7 *S, q31_t X, q31_t Y)

+
Define Documentation

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#define __CMSIS_GENERIC

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Definition at line 254 of file arm_math.h.

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#define DELTA_Q31   (0x100)

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Macros required for reciprocal calculation in Normalized LMS. 

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+
Definition at line 280 of file arm_math.h.

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#define DELTA_Q15   0x5

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Definition at line 281 of file arm_math.h.

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#define INDEX_MASK   0x0000003F

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Definition at line 282 of file arm_math.h.

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#define PI   3.14159265358979f

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Definition at line 283 of file arm_math.h.

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#define TABLE_SIZE   256

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Macros required for SINE and COSINE Fast math approximations. 

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Definition at line 289 of file arm_math.h.

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#define TABLE_SPACING_Q31   0x800000

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Definition at line 290 of file arm_math.h.

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#define TABLE_SPACING_Q15   0x80

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Definition at line 291 of file arm_math.h.

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#define INPUT_SPACING   0xB60B61

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Macros required for SINE and COSINE Controller functions. 

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Definition at line 298 of file arm_math.h.

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#define __SIMD32( addr )   (*(int32_t **) & (addr))

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definition to read/write two 16 bit values. 

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Definition at line 349 of file arm_math.h.

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#define __PACKq7( v0, 
 v1, 
 v2, 
 v3 
)

+

+

+Value:
( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |   \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+

+
definition to pack four 8 bit values. 

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+
Definition at line 366 of file arm_math.h.

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Typedef Documentation

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typedef int8_t q7_t

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8-bit fractional data type in 1.7 format. 

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Definition at line 319 of file arm_math.h.

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typedef int16_t q15_t

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16-bit fractional data type in 1.15 format. 

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Definition at line 324 of file arm_math.h.

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typedef int32_t q31_t

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32-bit fractional data type in 1.31 format. 

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Definition at line 329 of file arm_math.h.

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typedef int64_t q63_t

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64-bit fractional data type in 1.63 format. 

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Definition at line 334 of file arm_math.h.

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typedef float float32_t

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32-bit floating-point type definition. 

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Definition at line 339 of file arm_math.h.

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typedef double float64_t

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64-bit floating-point type definition. 

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Definition at line 344 of file arm_math.h.

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Enumeration Type Documentation

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enum arm_status

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Error status returned by some functions in the library. 

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Enumerator: 

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ARM_MATH_SUCCESS 
+
No error 

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ARM_MATH_ARGUMENT_ERROR 
+
One or more arguments are incorrect 

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ARM_MATH_LENGTH_ERROR 
+
Length of data buffer is incorrect 

+
ARM_MATH_SIZE_MISMATCH 
+
Size of matrices is not compatible with the operation. 

+
ARM_MATH_NANINF 
+
Not-a-number (NaN) or infinity is generated 

+
ARM_MATH_SINGULAR 
+
Generated by matrix inversion if the input matrix is singular and cannot be inverted. 

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ARM_MATH_TEST_FAILURE 
+
Test Failed 

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Definition at line 305 of file arm_math.h.

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Function Documentation

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static __INLINE q31_t clip_q63_to_q31 (q63_t  x ) [static]

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Clips Q63 to Q31 values. 

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Definition at line 383 of file arm_math.h.

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static __INLINE q15_t clip_q63_to_q15 (q63_t  x ) [static]

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Clips Q63 to Q15 values. 

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Definition at line 393 of file arm_math.h.

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static __INLINE q7_t clip_q31_to_q7 (q31_t  x ) [static]

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Clips Q31 to Q7 values. 

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Definition at line 403 of file arm_math.h.

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static __INLINE q15_t clip_q31_to_q15 (q31_t  x ) [static]

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Clips Q31 to Q15 values. 

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Definition at line 413 of file arm_math.h.

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static __INLINE q63_t mult32x64 (q63_t  x, 
q31_t  y 
) [static]

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Multiplies 32 X 64 and returns 32 bit result in 2.30 format. 

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Definition at line 424 of file arm_math.h.

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static __INLINE uint32_t arm_recip_q31 (q31_t  in, 
q31_t *  dst, 
q31_t *  pRecipTable 
) [static]

+

+

+
+
Function to Calculates 1/in(reciprocal) value of Q31 Data type. 

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Definition at line 463 of file arm_math.h.

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static __INLINE uint32_t arm_recip_q15 (q15_t  in, 
q15_t *  dst, 
q15_t *  pRecipTable 
) [static]

+

+

+
+
Function to Calculates 1/in(reciprocal) value of Q15 Data type. 

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Definition at line 514 of file arm_math.h.

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void arm_radix4_butterfly_f32 (float32_t *  pSrc, 
uint16_t  fftLen, 
float32_t *  pCoef, 
uint16_t  twidCoefModifier 
)

+

+

+
+
Core function for the floating-point CFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to the twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none.

+
end of CFFT_CIFFT group 

+
+
Definition at line 223 of file arm_cfft_radix4_f32.c.

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void arm_radix4_butterfly_inverse_f32 (float32_t *  pSrc, 
uint16_t  fftLen, 
float32_t *  pCoef, 
uint16_t  twidCoefModifier, 
float32_t  onebyfftLen 
)

+

+

+
+
Core function for the floating-point CIFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
[in]onebyfftLenvalue of 1/fftLen. 

+  

+

+
Returns:
none. 

+
+
Definition at line 660 of file arm_cfft_radix4_f32.c.

+
+

+

+
+

+

+      
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+      
void arm_bitreversal_f32 (float32_t *  pSrc, 
uint16_t  fftSize, 
uint16_t  bitRevFactor, 
uint16_t *  pBitRevTab 
)

+

+

+
+
In-place bit reversal function. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of floating-point data type. 
[in]fftSizelength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table. 
[in]*pBitRevTabpoints to the bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 1177 of file arm_cfft_radix4_f32.c.

+
+

+

+
+

+

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+      
void arm_radix4_butterfly_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
q31_t *  pCoef, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q31 CFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none.

+
end of CFFT_CIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 139 of file arm_cfft_radix4_q31.c.

+
+

+

+
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void arm_radix4_butterfly_inverse_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
q31_t *  pCoef, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q31 CIFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoefpoints to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 517 of file arm_cfft_radix4_q31.c.

+
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+        
+      
void arm_bitreversal_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
uint16_t  bitRevFactor, 
uint16_t *  pBitRevTab 
)

+

+

+
+
In-place bit reversal function. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q31 data type. 
[in]fftLenlength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table 
[in]*pBitRevTabpoints to bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 848 of file arm_cfft_radix4_q31.c.

+
+

+

+
+

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+        
+      
void arm_radix4_butterfly_q15 (q15_t *  pSrc16, 
uint32_t  fftLen, 
q15_t *  pCoef16, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q15 CFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none.

+
end of CFFT_CIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 138 of file arm_cfft_radix4_q15.c.

+
+

+

+
+

+

+      
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+        
+      
void arm_radix4_butterfly_inverse_q15 (q15_t *  pSrc16, 
uint32_t  fftLen, 
q15_t *  pCoef16, 
uint32_t  twidCoefModifier 
)

+

+

+
+
Core function for the Q15 CIFFT butterfly process. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrc16points to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]*pCoef16points to twiddle coefficient buffer. 
[in]twidCoefModifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 1053 of file arm_cfft_radix4_q15.c.

+
+

+

+
+

+

+      
+        
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+          
+          
+          
+        
+      
void arm_bitreversal_q15 (q15_t *  pSrc, 
uint32_t  fftLen, 
uint16_t  bitRevFactor, 
uint16_t *  pBitRevTab 
)

+

+

+
+
In-place bit reversal function. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*pSrcpoints to the in-place buffer of Q15 data type. 
[in]fftLenlength of the FFT. 
[in]bitRevFactorbit reversal modifier that supports different size FFTs with the same bit reversal table 
[in]*pBitRevTabpoints to bit reversal table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 1906 of file arm_cfft_radix4_q15.c.

+
+

+

+
+

+

+      
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+        
+      
static __INLINE void arm_circularWrite_f32 (int32_t *  circBuffer, 
int32_t  L, 
uint16_t *  writeOffset, 
int32_t  bufferInc, 
const int32_t *  src, 
int32_t  srcInc, 
uint32_t  blockSize 
) [static]

+

+

+
+
floating-point Circular write function. 

+
end of SQRT group 

+
+
Definition at line 5751 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
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+        
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+          
+          
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+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_circularRead_f32 (int32_t *  circBuffer, 
int32_t  L, 
int32_t *  readOffset, 
int32_t  bufferInc, 
int32_t *  dst, 
int32_t *  dst_base, 
int32_t  dst_length, 
int32_t  dstInc, 
uint32_t  blockSize 
) [static]

+

+

+
+
floating-point Circular Read function. 

+
+
Definition at line 5796 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
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+          
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+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_circularWrite_q15 (q15_t *  circBuffer, 
int32_t  L, 
uint16_t *  writeOffset, 
int32_t  bufferInc, 
const q15_t *  src, 
int32_t  srcInc, 
uint32_t  blockSize 
) [static]

+

+

+
+
Q15 Circular write function. 

+
+
Definition at line 5851 of file arm_math.h.

+
+

+

+
+

+

+      
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+          
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+        
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+          
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_circularRead_q15 (q15_t *  circBuffer, 
int32_t  L, 
int32_t *  readOffset, 
int32_t  bufferInc, 
q15_t *  dst, 
q15_t *  dst_base, 
int32_t  dst_length, 
int32_t  dstInc, 
uint32_t  blockSize 
) [static]

+

+

+
+
Q15 Circular Read function. 

+
+
Definition at line 5896 of file arm_math.h.

+
+

+

+
+

+

+      
+        
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+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_circularWrite_q7 (q7_t *  circBuffer, 
int32_t  L, 
uint16_t *  writeOffset, 
int32_t  bufferInc, 
const q7_t *  src, 
int32_t  srcInc, 
uint32_t  blockSize 
) [static]

+

+

+
+
Q7 Circular write function. 

+
+
Definition at line 5953 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_circularRead_q7 (q7_t *  circBuffer, 
int32_t  L, 
int32_t *  readOffset, 
int32_t  bufferInc, 
q7_t *  dst, 
q7_t *  dst_base, 
int32_t  dst_length, 
int32_t  dstInc, 
uint32_t  blockSize 
) [static]

+

+

+
+
Q7 Circular Read function. 

+
+
Definition at line 5998 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__math_8h_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__math_8h_source.html
new file mode 100644
index 0000000..27f1cf8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__math_8h_source.html
@@ -0,0 +1,3817 @@
+
+
+
+
+CMSIS DSP Software Library: arm_math.h Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__matrix__example__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__matrix__example__f32_8c.html
new file mode 100644
index 0000000..397df9f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__matrix__example__f32_8c.html
@@ -0,0 +1,275 @@
+
+
+
+
+CMSIS DSP Software Library: arm_matrix_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_matrix_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include "math_helper.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define SNR_THRESHOLD   90

+Functions
int32_t main (void)

+Variables
const float32_t B_f32 [4]
const float32_t A_f32 [16]
float32_t AT_f32 [16]
float32_t ATMA_f32 [16]
float32_t ATMAI_f32 [16]
float32_t X_f32 [4]
const float32_t xRef_f32 [4] = {73.0, 8.0, 21.25, 2.875}
float32_t snr

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define SNR_THRESHOLD   90

+

+

+
+
Definition at line 80 of file arm_matrix_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 130 of file arm_matrix_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t B_f32[4]

+

+

+Initial value:
  
+{    
+    782.0, 7577.0, 470.0, 4505.0 
+}
+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 87 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t A_f32[16]

+

+

+Initial value:
  
+{ 
+        
+    1.0,        32.0,       4.0,        128.0,  
+    1.0,        32.0,       64.0,       2048.0, 
+    1.0,        16.0,       4.0,        64.0, 
+    1.0,        16.0,       64.0,       1024.0, 
+}
+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 96 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t AT_f32[16]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 110 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t ATMA_f32[16]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 112 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t ATMAI_f32[16]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 114 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t X_f32[4]

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 116 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875}

+

+

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 121 of file arm_matrix_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t snr

+

+

+
+
Definition at line 123 of file arm_matrix_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__matrix__example__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__matrix__example__f32_8c_source.html
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index 0000000..56288e9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__matrix__example__f32_8c_source.html
@@ -0,0 +1,236 @@
+
+
+
+
+CMSIS DSP Software Library: arm_matrix_example_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__f32_8c.html
new file mode 100644
index 0000000..cebc886
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_max_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_max_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__f32_8c_source.html
new file mode 100644
index 0000000..d6c3f7e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__f32_8c_source.html
@@ -0,0 +1,170 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q15_8c.html
new file mode 100644
index 0000000..5c404dd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_max_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_max_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q15_8c_source.html
new file mode 100644
index 0000000..ab3f7c2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q15_8c_source.html
@@ -0,0 +1,170 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q31_8c.html
new file mode 100644
index 0000000..cb5bf9c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_max_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_max_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q31_8c_source.html
new file mode 100644
index 0000000..f673f69
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q31_8c_source.html
@@ -0,0 +1,172 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q7_8c.html
new file mode 100644
index 0000000..0795a1a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_max_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_max_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q7_8c_source.html
new file mode 100644
index 0000000..accd448
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__max__q7_8c_source.html
@@ -0,0 +1,257 @@
+
+
+
+
+CMSIS DSP Software Library: arm_max_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__f32_8c.html
new file mode 100644
index 0000000..8893326
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mean_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mean_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__f32_8c_source.html
new file mode 100644
index 0000000..886fcdc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__f32_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q15_8c.html
new file mode 100644
index 0000000..8af8eb7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mean_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mean_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q15_8c_source.html
new file mode 100644
index 0000000..18d8b56
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q15_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q31_8c.html
new file mode 100644
index 0000000..e72b761
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mean_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mean_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q31_8c_source.html
new file mode 100644
index 0000000..5fb51c3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q31_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q7_8c.html
new file mode 100644
index 0000000..4a58692
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mean_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mean_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q7_8c_source.html
new file mode 100644
index 0000000..e28148b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mean__q7_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mean_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__f32_8c.html
new file mode 100644
index 0000000..806e098
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_min_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_min_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__f32_8c_source.html
new file mode 100644
index 0000000..bf395b3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__f32_8c_source.html
@@ -0,0 +1,175 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q15_8c.html
new file mode 100644
index 0000000..52a2c72
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_min_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_min_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q15_8c_source.html
new file mode 100644
index 0000000..30600e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q15_8c_source.html
@@ -0,0 +1,176 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q31_8c.html
new file mode 100644
index 0000000..97d75fa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_min_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_min_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q31_8c_source.html
new file mode 100644
index 0000000..8e268d0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q31_8c_source.html
@@ -0,0 +1,174 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q7_8c.html
new file mode 100644
index 0000000..c169619
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_min_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_min_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q7_8c_source.html
new file mode 100644
index 0000000..e780285
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__min__q7_8c_source.html
@@ -0,0 +1,254 @@
+
+
+
+
+CMSIS DSP Software Library: arm_min_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__f32_8c.html
new file mode 100644
index 0000000..0601319
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mult_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mult_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__f32_8c_source.html
new file mode 100644
index 0000000..e89956b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__f32_8c_source.html
@@ -0,0 +1,166 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q15_8c.html
new file mode 100644
index 0000000..9c2068d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mult_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mult_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q15_8c_source.html
new file mode 100644
index 0000000..549adde
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q15_8c_source.html
@@ -0,0 +1,165 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q31_8c.html
new file mode 100644
index 0000000..154851d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mult_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mult_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q31_8c_source.html
new file mode 100644
index 0000000..c235c1d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q31_8c_source.html
@@ -0,0 +1,168 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q7_8c.html
new file mode 100644
index 0000000..e0df57d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_mult_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_mult_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q7_8c_source.html
new file mode 100644
index 0000000..a7a6790
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__mult__q7_8c_source.html
@@ -0,0 +1,172 @@
+
+
+
+
+CMSIS DSP Software Library: arm_mult_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__f32_8c.html
new file mode 100644
index 0000000..08dbd5f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_negate_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_negate_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__f32_8c_source.html
new file mode 100644
index 0000000..2980f57
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__f32_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q15_8c.html
new file mode 100644
index 0000000..28dc3d6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_negate_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_negate_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q15_8c_source.html
new file mode 100644
index 0000000..cfda4c8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q15_8c_source.html
@@ -0,0 +1,188 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q31_8c.html
new file mode 100644
index 0000000..fa798f0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_negate_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_negate_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q31_8c_source.html
new file mode 100644
index 0000000..fd34eb2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q31_8c_source.html
@@ -0,0 +1,167 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q7_8c.html
new file mode 100644
index 0000000..43adc0e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_negate_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_negate_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q7_8c_source.html
new file mode 100644
index 0000000..6aff496
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__negate__q7_8c_source.html
@@ -0,0 +1,170 @@
+
+
+
+
+CMSIS DSP Software Library: arm_negate_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__f32_8c.html
new file mode 100644
index 0000000..8c6ca5f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_offset_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_offset_f32 (float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__f32_8c_source.html
new file mode 100644
index 0000000..b53a1b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__f32_8c_source.html
@@ -0,0 +1,161 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q15_8c.html
new file mode 100644
index 0000000..f773a85
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_offset_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_offset_q15 (q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q15_8c_source.html
new file mode 100644
index 0000000..5b96cf8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q15_8c_source.html
@@ -0,0 +1,175 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q31_8c.html
new file mode 100644
index 0000000..ac3b464
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_offset_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_offset_q31 (q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q31_8c_source.html
new file mode 100644
index 0000000..6739240
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q31_8c_source.html
@@ -0,0 +1,173 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q7_8c.html
new file mode 100644
index 0000000..4c3e36e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_offset_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_offset_q7 (q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q7_8c_source.html
new file mode 100644
index 0000000..d8bd330
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__offset__q7_8c_source.html
@@ -0,0 +1,174 @@
+
+
+
+
+CMSIS DSP Software Library: arm_offset_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__f32_8c.html
new file mode 100644
index 0000000..9923ee8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_pid_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_pid_init_f32 (arm_pid_instance_f32 *S, int32_t resetStateFlag)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__f32_8c_source.html
new file mode 100644
index 0000000..3ba4625
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__f32_8c_source.html
@@ -0,0 +1,128 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q15_8c.html
new file mode 100644
index 0000000..911792e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_pid_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_pid_init_q15 (arm_pid_instance_q15 *S, int32_t resetStateFlag)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q15_8c_source.html
new file mode 100644
index 0000000..ddd14a4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q15_8c_source.html
@@ -0,0 +1,163 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_init_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q31_8c.html
new file mode 100644
index 0000000..91105d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_pid_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_pid_init_q31 (arm_pid_instance_q31 *S, int32_t resetStateFlag)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q31_8c_source.html
new file mode 100644
index 0000000..abd1ce7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__init__q31_8c_source.html
@@ -0,0 +1,148 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__f32_8c.html
new file mode 100644
index 0000000..99c8112
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_reset_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_pid_reset_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_pid_reset_f32 (arm_pid_instance_f32 *S)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__f32_8c_source.html
new file mode 100644
index 0000000..f499a13
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__f32_8c_source.html
@@ -0,0 +1,112 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_reset_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q15_8c.html
new file mode 100644
index 0000000..20d3039
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_reset_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_pid_reset_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_pid_reset_q15 (arm_pid_instance_q15 *S)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q15_8c_source.html
new file mode 100644
index 0000000..333448d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q15_8c_source.html
@@ -0,0 +1,111 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_reset_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q31_8c.html
new file mode 100644
index 0000000..399b1af
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_reset_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_pid_reset_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_pid_reset_q31 (arm_pid_instance_q31 *S)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q31_8c_source.html
new file mode 100644
index 0000000..9446736
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__pid__reset__q31_8c_source.html
@@ -0,0 +1,112 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_reset_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__f32_8c.html
new file mode 100644
index 0000000..59073bb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_power_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_power_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__f32_8c_source.html
new file mode 100644
index 0000000..2e36246
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__f32_8c_source.html
@@ -0,0 +1,172 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q15_8c.html
new file mode 100644
index 0000000..14628a1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_power_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_power_q15 (q15_t *pSrc, uint32_t blockSize, q63_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q15_8c_source.html
new file mode 100644
index 0000000..89bc751
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q15_8c_source.html
@@ -0,0 +1,181 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q31_8c.html
new file mode 100644
index 0000000..9e8f094
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_power_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_power_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q31_8c_source.html
new file mode 100644
index 0000000..1bf1638
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q31_8c_source.html
@@ -0,0 +1,171 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q7_8c.html
new file mode 100644
index 0000000..e402b5e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_power_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_power_q7 (q7_t *pSrc, uint32_t blockSize, q31_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q7_8c_source.html
new file mode 100644
index 0000000..62f6e07
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__power__q7_8c_source.html
@@ -0,0 +1,177 @@
+
+
+
+
+CMSIS DSP Software Library: arm_power_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__float_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__float_8c.html
new file mode 100644
index 0000000..f0630f8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__float_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q15_to_float.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q15_to_float.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q15_to_float (q15_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__float_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__float_8c_source.html
new file mode 100644
index 0000000..861b56b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__float_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q15_to_float.c Source File
+
+
+
+
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+
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+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q31_8c.html
new file mode 100644
index 0000000..d629350
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q15_to_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q15_to_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q15_to_q31 (q15_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q31_8c_source.html
new file mode 100644
index 0000000..cc51ffa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q31_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q15_to_q31.c Source File
+
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+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q7_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q15_to_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q15_to_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q15_to_q7 (q15_t *pSrc, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q7_8c_source.html
new file mode 100644
index 0000000..3d32865
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q15__to__q7_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q15_to_q7.c Source File
+
+
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+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__float_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__float_8c.html
new file mode 100644
index 0000000..83104ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__float_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q31_to_float.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q31_to_float.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q31_to_float (q31_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__float_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__float_8c_source.html
new file mode 100644
index 0000000..4377b56
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__float_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q31_to_float.c Source File
+
+
+
+
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+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q15_8c.html
new file mode 100644
index 0000000..15d1d18
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q31_to_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q31_to_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q31_to_q15 (q31_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q15_8c_source.html
new file mode 100644
index 0000000..7c717aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q15_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q31_to_q15.c Source File
+
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+
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+
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+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q7_8c.html
new file mode 100644
index 0000000..6bc04e7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q31_to_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q31_to_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q31_to_q7 (q31_t *pSrc, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q7_8c_source.html
new file mode 100644
index 0000000..123304a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q31__to__q7_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q31_to_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__float_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__float_8c.html
new file mode 100644
index 0000000..cdecd22
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__float_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q7_to_float.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q7_to_float.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q7_to_float (q7_t *pSrc, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__float_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__float_8c_source.html
new file mode 100644
index 0000000..c1a91eb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__float_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q7_to_float.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q15_8c.html
new file mode 100644
index 0000000..7518527
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q7_to_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q7_to_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q7_to_q15 (q7_t *pSrc, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q15_8c_source.html
new file mode 100644
index 0000000..6cad6a6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q15_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q7_to_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q31_8c.html
new file mode 100644
index 0000000..39c1986
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q7_to_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_q7_to_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_q7_to_q31 (q7_t *pSrc, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q31_8c_source.html
new file mode 100644
index 0000000..991a96e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__q7__to__q31_8c_source.html
@@ -0,0 +1,159 @@
+
+
+
+
+CMSIS DSP Software Library: arm_q7_to_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__f32_8c.html
new file mode 100644
index 0000000..75be7ae
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__f32_8c.html
@@ -0,0 +1,221 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_rfft_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
void arm_split_rfft_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pATable, float32_t *pBTable, float32_t *pDst, uint32_t modifier)
void arm_split_rifft_f32 (float32_t *pSrc, uint32_t fftLen, float32_t *pATable, float32_t *pBTable, float32_t *pDst, uint32_t modifier)
void arm_rfft_f32 (const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
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+          
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+          
+          
+          
+        
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+          
+          
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+          
+        
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+          
+          
+          
+        
+      
void arm_split_rfft_f32 (float32_t *  pSrc, 
uint32_t  fftLen, 
float32_t *  pATable, 
float32_t *  pBTable, 
float32_t *  pDst, 
uint32_t  modifier 
)

+

+

+
+
Core Real FFT process. 

+
end of RFFT_RIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 218 of file arm_rfft_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
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+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rifft_f32 (float32_t *  pSrc, 
uint32_t  fftLen, 
float32_t *  pATable, 
float32_t *  pBTable, 
float32_t *  pDst, 
uint32_t  modifier 
)

+

+

+
+
Core Real IFFT process. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 316 of file arm_rfft_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__f32_8c_source.html
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index 0000000..ffd922b
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+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__f32_8c_source.html
@@ -0,0 +1,334 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_f32.c Source File
+
+
+
+
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+
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+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__f32_8c.html
new file mode 100644
index 0000000..87b07d6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__f32_8c.html
@@ -0,0 +1,88 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_init_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_rfft_init_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)

+Variables
static const float32_t realCoefA [2048]
static const float32_t realCoefB [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__f32_8c_source.html
new file mode 100644
index 0000000..ebb0ad6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__f32_8c_source.html
@@ -0,0 +1,1720 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_init_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q15_8c.html
new file mode 100644
index 0000000..bbdf7e7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q15_8c.html
@@ -0,0 +1,88 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_init_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_rfft_init_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *S, arm_cfft_radix4_instance_q15 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)

+Variables
static const q15_t realCoefAQ15 [2048]
static const q15_t realCoefBQ15 [2048]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q15_8c_source.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q15_8c_source.html
@@ -0,0 +1,693 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_init_q15.c Source File
+
+
+
+
+
+
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+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q31_8c.html
new file mode 100644
index 0000000..2d6216d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q31_8c.html
@@ -0,0 +1,88 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_init_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_rfft_init_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *S, arm_cfft_radix4_instance_q31 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)

+Variables
const q31_t realCoefAQ31 [1024]
const q31_t realCoefBQ31 [1024]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q31_8c_source.html
new file mode 100644
index 0000000..4191d96
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__init__q31_8c_source.html
@@ -0,0 +1,688 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_init_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q15_8c.html
new file mode 100644
index 0000000..9b4d727
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q15_8c.html
@@ -0,0 +1,221 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_rfft_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
void arm_split_rfft_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pATable, q15_t *pBTable, q15_t *pDst, uint32_t modifier)
void arm_split_rifft_q15 (q15_t *pSrc, uint32_t fftLen, q15_t *pATable, q15_t *pBTable, q15_t *pDst, uint32_t modifier)
void arm_rfft_q15 (const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
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+        
+        
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rfft_q15 (q15_t *  pSrc, 
uint32_t  fftLen, 
q15_t *  pATable, 
q15_t *  pBTable, 
q15_t *  pDst, 
uint32_t  modifier 
)

+

+

+
+
Core Real FFT process. 

+
end of RFFT_RIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
*pSrcpoints to the input buffer. 
fftLenlength of FFT. 
*pATablepoints to the A twiddle Coef buffer. 
*pBTablepoints to the B twiddle Coef buffer. 
*pDstpoints to the output buffer. 
modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. The function implements a Real FFT 

+
+
Definition at line 143 of file arm_rfft_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rifft_q15 (q15_t *  pSrc, 
uint32_t  fftLen, 
q15_t *  pATable, 
q15_t *  pBTable, 
q15_t *  pDst, 
uint32_t  modifier 
)

+

+

+
+
Core Real IFFT process. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. The function implements a Real IFFT 

+
+
Definition at line 312 of file arm_rfft_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q15_8c_source.html
new file mode 100644
index 0000000..02fd37a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q15_8c_source.html
@@ -0,0 +1,480 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q31_8c.html
new file mode 100644
index 0000000..7fb5a63
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q31_8c.html
@@ -0,0 +1,221 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_rfft_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
void arm_split_rfft_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pATable, q31_t *pBTable, q31_t *pDst, uint32_t modifier)
void arm_split_rifft_q31 (q31_t *pSrc, uint32_t fftLen, q31_t *pATable, q31_t *pBTable, q31_t *pDst, uint32_t modifier)
void arm_rfft_q31 (const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rfft_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
q31_t *  pATable, 
q31_t *  pBTable, 
q31_t *  pDst, 
uint32_t  modifier 
)

+

+

+
+
Core Real FFT process. 

+
end of RFFT_RIFFT group 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 143 of file arm_rfft_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
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+          
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_split_rifft_q31 (q31_t *  pSrc, 
uint32_t  fftLen, 
q31_t *  pATable, 
q31_t *  pBTable, 
q31_t *  pDst, 
uint32_t  modifier 
)

+

+

+
+
Core Real IFFT process. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer. 
[in]fftLenlength of FFT. 
[in]*pATablepoints to the twiddle Coef A buffer. 
[in]*pBTablepoints to the twiddle Coef B buffer. 
[out]*pDstpoints to the output buffer. 
[in]modifiertwiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+  

+

+
Returns:
none. 

+
+
Definition at line 249 of file arm_rfft_q31.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rfft__q31_8c_source.html
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index 0000000..a80f27d
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+
+
+
+
+CMSIS DSP Software Library: arm_rfft_q31.c Source File
+
+
+
+
+
+
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+
+
+
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+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__f32_8c.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rms_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_rms_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_rms_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__f32_8c_source.html
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@@ -0,0 +1,167 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rms_f32.c Source File
+
+
+
+
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+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__q15_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rms_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_rms_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_rms_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__q15_8c_source.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__q15_8c_source.html
@@ -0,0 +1,193 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rms_q15.c Source File
+
+
+
+
+
+
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+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__q31_8c.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rms_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_rms_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_rms_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__q31_8c_source.html
new file mode 100644
index 0000000..466bc8d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__rms__q31_8c_source.html
@@ -0,0 +1,183 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rms_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__f32_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_scale_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_scale_f32 (float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__f32_8c_source.html
new file mode 100644
index 0000000..0b690fc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__f32_8c_source.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_f32.c Source File
+
+
+
+
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+
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+
+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q15_8c.html
new file mode 100644
index 0000000..82e730a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_scale_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_scale_q15 (q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q15_8c_source.html
new file mode 100644
index 0000000..87057c1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q15_8c_source.html
@@ -0,0 +1,207 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_q15.c Source File
+
+
+
+
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+
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+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q31_8c.html
new file mode 100644
index 0000000..0d981fe
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_scale_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_scale_q31 (q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q31_8c_source.html
new file mode 100644
index 0000000..ee8e195
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q31_8c_source.html
@@ -0,0 +1,163 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q7_8c.html
new file mode 100644
index 0000000..3a83c80
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_scale_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_scale_q7 (q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q7_8c_source.html
new file mode 100644
index 0000000..cfcb293
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__scale__q7_8c_source.html
@@ -0,0 +1,187 @@
+
+
+
+
+CMSIS DSP Software Library: arm_scale_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q15_8c.html
new file mode 100644
index 0000000..0d89987
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_shift_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_shift_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_shift_q15 (q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q15_8c_source.html
new file mode 100644
index 0000000..276dd7a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q15_8c_source.html
@@ -0,0 +1,286 @@
+
+
+
+
+CMSIS DSP Software Library: arm_shift_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q31_8c.html
new file mode 100644
index 0000000..741ee90
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_shift_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_shift_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_shift_q31 (q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q31_8c_source.html
new file mode 100644
index 0000000..0367f45
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q31_8c_source.html
@@ -0,0 +1,173 @@
+
+
+
+
+CMSIS DSP Software Library: arm_shift_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q7_8c.html
new file mode 100644
index 0000000..8d864b9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_shift_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_shift_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_shift_q7 (q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q7_8c_source.html
new file mode 100644
index 0000000..343e4a4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__shift__q7_8c_source.html
@@ -0,0 +1,248 @@
+
+
+
+
+CMSIS DSP Software Library: arm_shift_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__signal__converge__example__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__signal__converge__example__f32_8c.html
new file mode 100644
index 0000000..e7ec791
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__signal__converge__example__f32_8c.html
@@ -0,0 +1,511 @@
+
+
+
+
+CMSIS DSP Software Library: arm_signal_converge_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_signal_converge_example_f32.c File Reference
  

+

+

+#include "arm_math.h"

+#include "math_helper.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define TEST_LENGTH_SAMPLES   1536
#define NUMTAPS   32
#define BLOCKSIZE   32
#define DELTA_ERROR   0.000001f
#define DELTA_COEFF   0.0001f
#define MU   0.5f
#define NUMFRAMES   (TEST_LENGTH_SAMPLES / BLOCKSIZE)

+Functions
arm_status test_signal_converge_example (void)
arm_status test_signal_converge (float32_t *err_signal, uint32_t blockSize)
void getinput (float32_t *input, uint32_t fr_cnt, uint32_t blockSize)
int32_t main (void)

+Variables
float32_t firStateF32 [NUMTAPS+BLOCKSIZE]
arm_fir_instance_f32 LPF_instance
float32_t lmsStateF32 [NUMTAPS+BLOCKSIZE]
float32_t errOutput [TEST_LENGTH_SAMPLES]
arm_lms_norm_instance_f32 lmsNorm_instance
float32_t testInput_f32 [TEST_LENGTH_SAMPLES]
float32_t lmsNormCoeff_f32 [32]
const float32_t FIRCoeff_f32 [32]
float32_t wire1 [BLOCKSIZE]
float32_t wire2 [BLOCKSIZE]
float32_t wire3 [BLOCKSIZE]
float32_t err_signal [BLOCKSIZE]

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define TEST_LENGTH_SAMPLES   1536

+

+

+
+
Definition at line 100 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMTAPS   32

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 101 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define BLOCKSIZE   32

+

+

+
+
Definition at line 102 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA_ERROR   0.000001f

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 103 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA_COEFF   0.0001f

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 104 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define MU   0.5f

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 105 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define NUMFRAMES   (TEST_LENGTH_SAMPLES / BLOCKSIZE)

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 107 of file arm_signal_converge_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
arm_status test_signal_converge_example (void  )

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status test_signal_converge (float32_t *  err_signal, 
uint32_t  blockSize 
)

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void getinput (float32_t *  input, 
uint32_t  fr_cnt, 
uint32_t  blockSize 
)

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 163 of file arm_signal_converge_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t firStateF32[NUMTAPS+BLOCKSIZE]

+

+

+
Examples: 
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 113 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_fir_instance_f32 LPF_instance

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 114 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t lmsStateF32[NUMTAPS+BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 120 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t errOutput[TEST_LENGTH_SAMPLES]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 121 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_lms_norm_instance_f32 lmsNorm_instance

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 122 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32[TEST_LENGTH_SAMPLES]

+

+

+
+
Definition at line 83 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t lmsNormCoeff_f32[32]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t FIRCoeff_f32[32]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire1[BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 154 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire2[BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 155 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire3[BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 156 of file arm_signal_converge_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t err_signal[BLOCKSIZE]

+

+

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 157 of file arm_signal_converge_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__signal__converge__example__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__signal__converge__example__f32_8c_source.html
new file mode 100644
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--- /dev/null
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@@ -0,0 +1,246 @@
+
+
+
+
+CMSIS DSP Software Library: arm_signal_converge_example_f32.c Source File
+
+
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+

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+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__example__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__example__f32_8c.html
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@@ -0,0 +1,301 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_sin_cos_example_f32.c File Reference
  

+

+

+#include <math.h>

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define MAX_BLOCKSIZE   32
#define DELTA   (0.000001f)

+Functions
int32_t main (void)

+Variables
const float32_t testInput_f32 [MAX_BLOCKSIZE]
const float32_t testRefOutput_f32 = 1.000000000
uint32_t blockSize = 32
float32_t testOutput
float32_t cosOutput
float32_t sinOutput
float32_t cosSquareOutput
float32_t sinSquareOutput
arm_status status

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define MAX_BLOCKSIZE   32

+

+

+
+
Definition at line 74 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA   (0.000001f)

+

+

+
+
Definition at line 75 of file arm_sin_cos_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 111 of file arm_sin_cos_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t testInput_f32[MAX_BLOCKSIZE]

+

+

+Initial value:
  
+{    
+    -1.244916875853235400,  -4.793533929171324800,  0.360705030233248850,   0.827929644170887320,   -3.299532218312426900,  3.427441903227623800,   3.422401784294607700,   -0.108308165334010680,   
+    0.941943896490312180,   0.502609575000365850,   -0.537345278736373500,  2.088817392965764500,   -1.693168684143455700,  6.283185307179590700,   -0.392545884746175080,  0.327893095115825040,    
+    3.070147440456292300,   0.170611405884662230,   -0.275275082396073010,  -2.395492805446796300,  0.847311163536506600,   -3.845517018083148800,  2.055818378415868300,   4.672594161978930800,    
+    -1.990923030266425800,  2.469305197656249500,   3.609002606064021000,   -4.586736582331667500,  -4.147080139136136300,  1.643756718868359500,   -1.150866392366494800,  1.985805026477433800 
+ 
+ 
+}
+

+
Definition at line 83 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t testRefOutput_f32 = 1.000000000

+

+

+
+
Definition at line 93 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t blockSize = 32

+

+

+
+
Definition at line 98 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testOutput

+

+

+
+
Definition at line 99 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t cosOutput

+

+

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Definition at line 100 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t sinOutput

+

+

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Definition at line 101 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t cosSquareOutput

+

+

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Definition at line 102 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t sinSquareOutput

+

+

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Definition at line 103 of file arm_sin_cos_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_status status

+

+

+
+
Definition at line 109 of file arm_sin_cos_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__example__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__example__f32_8c_source.html
new file mode 100644
index 0000000..75e7e6e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__example__f32_8c_source.html
@@ -0,0 +1,172 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_example_f32.c Source File
+
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__f32_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__f32_8c.html
@@ -0,0 +1,88 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_sin_cos_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
void arm_sin_cos_f32 (float32_t theta, float32_t *pSinVal, float32_t *pCosVal)

+Variables
static const float32_t cosTable [360]
static const float32_t sinTable [360]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__f32_8c_source.html
new file mode 100644
index 0000000..1100a56
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__f32_8c_source.html
@@ -0,0 +1,420 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_f32.c Source File
+
+
+
+
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+
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+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__q31_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__q31_8c.html
@@ -0,0 +1,88 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_sin_cos_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+

+Functions
void arm_sin_cos_q31 (q31_t theta, q31_t *pSinVal, q31_t *pCosVal)

+Variables
static const int32_t sinTableQ31 [360]
static const int32_t cosTableQ31 [360]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__q31_8c_source.html
new file mode 100644
index 0000000..43f8135
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__cos__q31_8c_source.html
@@ -0,0 +1,340 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_q31.c Source File
+
+
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+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__f32_8c.html
new file mode 100644
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--- /dev/null
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@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_sin_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
float32_t arm_sin_f32 (float32_t x)

+Variables
static const float32_t sinTable [259]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__f32_8c_source.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__f32_8c_source.html
@@ -0,0 +1,265 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__q15_8c.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__q15_8c.html
@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_sin_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
q15_t arm_sin_q15 (q15_t x)

+Variables
static const q15_t sinTableQ15 [259]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__q15_8c_source.html
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@@ -0,0 +1,225 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_q15.c Source File
+
+
+
+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__q31_8c.html
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--- /dev/null
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@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
arm_sin_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+

+Functions
q31_t arm_sin_q31 (q31_t x)

+Variables
static const q31_t sinTableQ31 [259]

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sin__q31_8c_source.html
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+
+CMSIS DSP Software Library: arm_sin_q31.c Source File
+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q15_8c.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q15_8c.html
@@ -0,0 +1,84 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sqrt_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_sqrt_q15.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_sqrt_q15 (q15_t in, q15_t *pOut)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q15_8c_source.html
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+
+CMSIS DSP Software Library: arm_sqrt_q15.c Source File
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q31_8c.html
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+
+
+
+
+CMSIS DSP Software Library: arm_sqrt_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_sqrt_q31.c File Reference
  

+

+

+#include "arm_math.h"

+#include "arm_common_tables.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
arm_status arm_sqrt_q31 (q31_t in, q31_t *pOut)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q31_8c_source.html
new file mode 100644
index 0000000..0ab4020
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sqrt__q31_8c_source.html
@@ -0,0 +1,252 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sqrt_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__f32_8c.html
new file mode 100644
index 0000000..9ad6b75
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_std_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_std_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_std_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__f32_8c_source.html
new file mode 100644
index 0000000..ed803cc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__f32_8c_source.html
@@ -0,0 +1,255 @@
+
+
+
+
+CMSIS DSP Software Library: arm_std_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__q15_8c.html
new file mode 100644
index 0000000..9669599
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_std_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_std_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_std_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__q15_8c_source.html
new file mode 100644
index 0000000..c6a6e54
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__q15_8c_source.html
@@ -0,0 +1,269 @@
+
+
+
+
+CMSIS DSP Software Library: arm_std_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__q31_8c.html
new file mode 100644
index 0000000..b988fbb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_std_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_std_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_std_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__q31_8c_source.html
new file mode 100644
index 0000000..d8b7665
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__std__q31_8c_source.html
@@ -0,0 +1,255 @@
+
+
+
+
+CMSIS DSP Software Library: arm_std_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__f32_8c.html
new file mode 100644
index 0000000..ddd54dd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_sub_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_sub_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__f32_8c_source.html
new file mode 100644
index 0000000..eaa1683
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__f32_8c_source.html
@@ -0,0 +1,161 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q15_8c.html
new file mode 100644
index 0000000..a21d711
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_sub_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_sub_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q15_8c_source.html
new file mode 100644
index 0000000..a868985
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q15_8c_source.html
@@ -0,0 +1,171 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q31_8c.html
new file mode 100644
index 0000000..5eb6a74
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_sub_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_sub_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q31_8c_source.html
new file mode 100644
index 0000000..942eaf9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q31_8c_source.html
@@ -0,0 +1,172 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q7_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q7_8c.html
new file mode 100644
index 0000000..65b0502
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q7_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_q7.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_sub_q7.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_sub_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q7_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q7_8c_source.html
new file mode 100644
index 0000000..5ea2044
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__sub__q7_8c_source.html
@@ -0,0 +1,170 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sub_q7.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__f32_8c.html
new file mode 100644
index 0000000..083bb93
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__f32_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_var_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_var_f32.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_var_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__f32_8c_source.html
new file mode 100644
index 0000000..0872862
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__f32_8c_source.html
@@ -0,0 +1,252 @@
+
+
+
+
+CMSIS DSP Software Library: arm_var_f32.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__q15_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__q15_8c.html
new file mode 100644
index 0000000..82ffd6a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__q15_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_var_q15.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_var_q15.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_var_q15 (q15_t *pSrc, uint32_t blockSize, q31_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__q15_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__q15_8c_source.html
new file mode 100644
index 0000000..b31c096
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__q15_8c_source.html
@@ -0,0 +1,252 @@
+
+
+
+
+CMSIS DSP Software Library: arm_var_q15.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__q31_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__q31_8c.html
new file mode 100644
index 0000000..1dd506b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__q31_8c.html
@@ -0,0 +1,83 @@
+
+
+
+
+CMSIS DSP Software Library: arm_var_q31.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
arm_var_q31.c File Reference
  

+

+

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+

+Functions
void arm_var_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__q31_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__q31_8c_source.html
new file mode 100644
index 0000000..de68b85
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__var__q31_8c_source.html
@@ -0,0 +1,252 @@
+
+
+
+
+CMSIS DSP Software Library: arm_var_q31.c Source File
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__variance__example__f32_8c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__variance__example__f32_8c.html
new file mode 100644
index 0000000..beead8f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__variance__example__f32_8c.html
@@ -0,0 +1,253 @@
+
+
+
+
+CMSIS DSP Software Library: arm_variance_example_f32.c File Reference
+
+
+
+
+
+
+
+
+
+

+  

+Defines |
+Functions |
+Variables  

+  

+
arm_variance_example_f32.c File Reference
  

+

+

+#include <math.h>

+#include "arm_math.h"

+
+
Go to the source code of this file.

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Defines
#define MAX_BLOCKSIZE   32
#define DELTA   (0.000001f)

+Functions
int32_t main (void)

+Variables
float32_t wire1 [MAX_BLOCKSIZE]
float32_t wire2 [MAX_BLOCKSIZE]
float32_t wire3 [MAX_BLOCKSIZE]
float32_t testInput_f32 [32]
uint32_t blockSize = 32
float32_t refVarianceOut = 0.903941793931839

+
Define Documentation

+
+

+

+      
+        
+          
+        
+      
#define MAX_BLOCKSIZE   32

+

+

+
+
Definition at line 83 of file arm_variance_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
#define DELTA   (0.000001f)

+

+

+
+
Definition at line 84 of file arm_variance_example_f32.c.

+
+

+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
int32_t main (void  )

+

+

+
+
Definition at line 122 of file arm_variance_example_f32.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t wire1[MAX_BLOCKSIZE]

+

+

+
+
Definition at line 90 of file arm_variance_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire2[MAX_BLOCKSIZE]

+

+

+
+
Definition at line 91 of file arm_variance_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t wire3[MAX_BLOCKSIZE]

+

+

+
+
Definition at line 92 of file arm_variance_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t testInput_f32[32]

+

+

+Initial value:
 
+{ 
+-0.432564811528221,     -1.665584378238097,     0.125332306474831,      0.287676420358549,  
+-1.146471350681464,     1.190915465642999,      1.189164201652103,      -0.037633276593318,     
+0.327292361408654,      0.174639142820925,      -0.186708577681439,     0.725790548293303,  
+-0.588316543014189,     2.183185818197101,      -0.136395883086596,     0.113931313520810,  
+1.066768211359189,      0.059281460523605,      -0.095648405483669,     -0.832349463650022,     
+0.294410816392640,      -1.336181857937804,     0.714324551818952,      1.623562064446271,  
+-0.691775701702287,     0.857996672828263,      1.254001421602532,      -1.593729576447477,     
+-1.440964431901020,     0.571147623658178,      -0.399885577715363,     0.689997375464345
+  
+}
+

+
Definition at line 99 of file arm_variance_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t blockSize = 32

+

+

+
+
Definition at line 115 of file arm_variance_example_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t refVarianceOut = 0.903941793931839

+

+

+
Examples: 
arm_variance_example_f32.c.

+

+
Definition at line 116 of file arm_variance_example_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__variance__example__f32_8c_source.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm__variance__example__f32_8c_source.html
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@@ -0,0 +1,206 @@
+
+
+
+
+CMSIS DSP Software Library: arm_variance_example_f32.c Source File
+
+
+
+
+
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+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:17 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_class_marks_example_f32_8c-example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_class_marks_example_f32_8c-example.html
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index 0000000..04469ea
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@@ -0,0 +1,221 @@
+
+
+
+
+CMSIS DSP Software Library: arm_class_marks_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_class_marks_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3 
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_class_marks_example_f32.c         
+*  
+* Description:  Example code to calculate Minimum, Maximum 
+*               Mean, std and variance of marks obtained in a class 
+* 
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+*  
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+ 
+#define USE_STATIC_INIT 
+ 
+ /* ---------------------------------------------------------------------- 
+** Global defines  
+** ------------------------------------------------------------------- */ 
+ 
+#define TEST_LENGTH_SAMPLES     (20*4) 
+ 
+/* ---------------------------------------------------------------------- 
+** List of Marks scored by 20 students for 4 subjects 
+** ------------------------------------------------------------------- */  
+const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] =  
+{    
+    42.000000,  37.000000,  81.000000,  28.000000,   
+    83.000000,  72.000000,  36.000000,  38.000000,   
+    32.000000,  51.000000,  63.000000,  64.000000,   
+    97.000000,  82.000000,  95.000000,  90.000000,   
+    66.000000,  51.000000,  54.000000,  42.000000,   
+    67.000000,  56.000000,  45.000000,  57.000000,   
+    67.000000,  69.000000,  35.000000,  52.000000,   
+    29.000000,  81.000000,  58.000000,  47.000000,   
+    38.000000,  76.000000,  100.000000, 29.000000,   
+    33.000000,  47.000000,  29.000000,  50.000000,   
+    34.000000,  41.000000,  61.000000,  46.000000,   
+    52.000000,  50.000000,  48.000000,  36.000000,   
+    47.000000,  55.000000,  44.000000,  40.000000,   
+    100.000000, 94.000000,  84.000000,  37.000000,   
+    32.000000,  71.000000,  47.000000,  77.000000,   
+    31.000000,  50.000000,  49.000000,  35.000000,   
+    63.000000,  67.000000,  40.000000,  31.000000,   
+    29.000000,  68.000000,  61.000000,  38.000000,   
+    31.000000,  28.000000,  28.000000,  76.000000,   
+    55.000000,  33.000000,  29.000000,  39.000000 
+};  
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Number of subjects X 1  
+* ------------------------------------------------------------------- */  
+const float32_t testUnity_f32[4] =  
+{    
+    1.000,  1.000,  1.000,  1.000 
+}; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+** f32 Output buffer 
+** ------------------------------------------------------------------- */  
+static float32_t testOutput[TEST_LENGTH_SAMPLES]; 
+ 
+ 
+/* ------------------------------------------------------------------ 
+* Global defines  
+*------------------------------------------------------------------- */ 
+#define     NUMSTUDENTS  20 
+#define     NUMSUBJECTS  4 
+ 
+/* ------------------------------------------------------------------ 
+* Global variables  
+*------------------------------------------------------------------- */ 
+ 
+uint32_t    numStudents = 20; 
+uint32_t    numSubjects = 4;  
+float32_t   max_marks, min_marks, mean, std, var; 
+uint32_t    student_num;    
+ 
+/* ---------------------------------------------------------------------------------- 
+* Main f32 test function.  It returns maximum marks secured and student number 
+* ------------------------------------------------------------------------------- */ 
+ 
+int32_t main() 
+{ 
+ 
+#ifndef  USE_STATIC_INIT 
+ 
+    arm_matrix_instance_f32 srcA; 
+    arm_matrix_instance_f32 srcB; 
+    arm_matrix_instance_f32 dstC;  
+ 
+    /* Input and output matrices initializations */  
+    arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32);  
+    arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32);  
+    arm_mat_init_f32(&dstC, numStudents, 1, testOutput);  
+ 
+#else 
+ 
+    /* Static Initializations of Input and output matrix sizes and array */ 
+    arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32}; 
+    arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32}; 
+    arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput}; 
+ 
+#endif 
+ 
+     
+    /* ---------------------------------------------------------------------- 
+    *Call the Matrix multiplication process function   
+    * ------------------------------------------------------------------- */ 
+    arm_mat_mult_f32(&srcA, &srcB, &dstC); 
+     
+    /* ---------------------------------------------------------------------- 
+    ** Call the Max function to calculate max marks among numStudents 
+    ** ------------------------------------------------------------------- */ 
+    arm_max_f32(testOutput, numStudents, &max_marks, &student_num);  
+ 
+    /* ---------------------------------------------------------------------- 
+    ** Call the Min function to calculate min marks among numStudents 
+    ** ------------------------------------------------------------------- */ 
+    arm_min_f32(testOutput, numStudents, &min_marks, &student_num);  
+ 
+    /* ---------------------------------------------------------------------- 
+    ** Call the Mean function to calculate mean 
+    ** ------------------------------------------------------------------- */ 
+    arm_mean_f32(testOutput, numStudents, &mean); 
+ 
+    /* ---------------------------------------------------------------------- 
+    ** Call the std function to calculate standard deviation 
+    ** ------------------------------------------------------------------- */ 
+    arm_std_f32(testOutput, numStudents, &std); 
+ 
+    /* ---------------------------------------------------------------------- 
+    ** Call the var function to calculate variance 
+    ** ------------------------------------------------------------------- */ 
+    arm_var_f32(testOutput, numStudents, &var); 
+ 
+} 
+ 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_convolution_example_f32_8c-example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_convolution_example_f32_8c-example.html
new file mode 100644
index 0000000..653284e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_convolution_example_f32_8c-example.html
@@ -0,0 +1,232 @@
+
+
+
+
+CMSIS DSP Software Library: arm_convolution_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_convolution_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3 
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_convolution_example_f32.c         
+*  
+* Description:  Example code demonstrating Convolution of two input signals using fft. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h"                 
+ 
+/* ---------------------------------------------------------------------- 
+* Defines each of the tests performed 
+* ------------------------------------------------------------------- */ 
+#define MAX_BLOCKSIZE   128 
+#define DELTA           (0.000001f) 
+#define SNR_THRESHOLD   90 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare I/O buffers  
+* ------------------------------------------------------------------- */ 
+float32_t Ak[MAX_BLOCKSIZE];        /* Input A */ 
+float32_t Bk[MAX_BLOCKSIZE];        /* Input B */ 
+float32_t AxB[MAX_BLOCKSIZE * 2];   /* Output */ 
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for Floating point Convolution example for 32-blockSize 
+* Generated by the MATLAB randn() function 
+* ------------------------------------------------------------------- */ 
+float32_t testInputA_f32[64] =  
+{  
+-0.808920,  1.357369,   1.180861,   -0.504544,  1.762637,   -0.703285,   
+1.696966,   0.620571,   -0.151093,  -0.100235,  -0.872382,  -0.403579,   
+-0.860749,  -0.382648,  -1.052338,  0.128113,   -0.646269,  1.093377,    
+-2.209198,  0.471706,   0.408901,   1.266242,   0.598252,   1.176827,    
+-0.203421,  0.213596,   -0.851964,  -0.466958,  0.021841,   -0.698938,   
+-0.604107,  0.461778,   -0.318219,  0.942520,   0.577585,   0.417619,    
+0.614665,   0.563679,   -1.295073,  -0.764437,  0.952194,   -0.859222,   
+-0.618554,  -2.268542,  -1.210592,  1.655853,   -2.627219,  -0.994249,   
+-1.374704,  0.343799,   0.025619,   1.227481,   -0.708031,  0.069355,    
+-1.845228,  -1.570886,  1.010668,   -1.802084,  1.630088,   1.286090,    
+-0.161050,  -0.940794,  0.367961,   0.291907 
+         
+};  
+  
+float32_t testInputB_f32[64] =  
+{  
+0.933724,   0.046881,   1.316470,   0.438345,   0.332682,   2.094885,    
+0.512081,   0.035546,   0.050894,   -2.320371,  0.168711,   -1.830493,   
+-0.444834,  -1.003242,  -0.531494,  -1.365600,  -0.155420,  -0.757692,   
+-0.431880,  -0.380021,  0.096243,   -0.695835,  0.558850,   -1.648962,   
+0.020369,   -0.363630,  0.887146,   0.845503,   -0.252864,  -0.330397,   
+1.269131,   -1.109295,  -1.027876,  0.135940,   0.116721,   -0.293399,   
+-1.349799,  0.166078,   -0.802201,  0.369367,   -0.964568,  -2.266011,   
+0.465178,   0.651222,   -0.325426,  0.320245,   -0.784178,  -0.579456,   
+0.093374,   0.604778,   -0.048225,  0.376297,   -0.394412,  0.578182,    
+-1.218141,  -1.387326,  0.692462,   -0.631297,  0.153137,   -0.638952,   
+0.635474,   -0.970468,  1.334057,   -0.111370 
+};  
+  
+const float testRefOutput_f32[126] =   
+{  
+-0.818943,  1.229484,   -0.533664,  1.016604,   0.341875,   -1.963656,   
+5.171476,   3.478033,   7.616361,   6.648384,   0.479069,   1.792012,    
+-1.295591,  -7.447818,  0.315830,   -10.657445, -2.483469,  -6.524236,   
+-7.380591,  -3.739005,  -8.388957,  0.184147,   -1.554888,  3.786508,    
+-1.684421,  5.400610,   -1.578126,  7.403361,   8.315999,   2.080267,    
+11.077776,  2.749673,   7.138962,   2.748762,   0.660363,   0.981552,    
+1.442275,   0.552721,   -2.576892,  4.703989,   0.989156,   8.759344,    
+-0.564825,  -3.994680,  0.954710,   -5.014144,  6.592329,   1.599488,    
+-13.979146, -0.391891,  -4.453369,  -2.311242,  -2.948764,  1.761415,    
+-0.138322,  10.433007,  -2.309103,  4.297153,   8.535523,   3.209462,    
+8.695819,   5.569919,   2.514304,   5.582029,   2.060199,   0.642280,    
+7.024616,   1.686615,   -6.481756,  1.343084,   -3.526451,  1.099073,    
+-2.965764,  -0.173723,  -4.111484,  6.528384,   -6.965658,  1.726291,    
+1.535172,   11.023435,  2.338401,   -4.690188,  1.298210,   3.943885,    
+8.407885,   5.168365,   0.684131,   1.559181,   1.859998,   2.852417,    
+8.574070,   -6.369078,  6.023458,   11.837963,  -6.027632,  4.469678,    
+-6.799093,  -2.674048,  6.250367,   -6.809971,  -3.459360,  9.112410,    
+-2.711621,  -1.336678,  1.564249,   -1.564297,  -1.296760,  8.904013,    
+-3.230109,  6.878013,   -7.819823,  3.369909,   -1.657410,  -2.007358,   
+-4.112825,  1.370685,   -3.420525,  -6.276605,  3.244873,   -3.352638,   
+1.545372,   0.902211,   0.197489,   -1.408732,  0.523390,   0.348440 
+}; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare Global variables  
+* ------------------------------------------------------------------- */ 
+uint32_t srcALen = 64;   /* Length of Input A */ 
+uint32_t srcBLen = 64;   /* Length of Input B */ 
+uint32_t outLen;         /* Length of convolution output */ 
+float32_t snr;           /* output SNR */ 
+ 
+int32_t main(void) 
+{ 
+    arm_status status;     /* Status of the example */ 
+    arm_cfft_radix4_instance_f32 cfft_instance; /* CFFT Structure instance */ 
+ 
+    /* CFFT Structure instance pointer */ 
+    arm_cfft_radix4_instance_f32 *cfft_instance_ptr =  
+            (arm_cfft_radix4_instance_f32*) &cfft_instance; 
+ 
+    /* output length of convolution */ 
+    outLen = srcALen + srcBLen - 1; 
+ 
+    /* Initialise the fft input buffers with all zeros */ 
+    arm_fill_f32(0.0,  Ak, MAX_BLOCKSIZE); 
+    arm_fill_f32(0.0,  Bk, MAX_BLOCKSIZE); 
+ 
+    /* Copy the input values to the fft input buffers */ 
+    arm_copy_f32(testInputA_f32,  Ak, MAX_BLOCKSIZE/2); 
+    arm_copy_f32(testInputB_f32,  Bk, MAX_BLOCKSIZE/2); 
+     
+    /* Initialize the CFFT function to compute 64 point fft */  
+    status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1); 
+ 
+    /* Transform input a[n] from time domain to frequency domain A[k] */ 
+    arm_cfft_radix4_f32(cfft_instance_ptr, Ak); 
+    /* Transform input b[n] from time domain to frequency domain B[k] */ 
+    arm_cfft_radix4_f32(cfft_instance_ptr, Bk); 
+     
+    /* Complex Multiplication of the two input buffers in frequency domain */ 
+    arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2);  
+ 
+    /* Initialize the CIFFT function to compute 64 point ifft */  
+    status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1); 
+ 
+    /* Transform the multiplication output from frequency domain to time domain, 
+       that gives the convolved output  */ 
+    arm_cfft_radix4_f32(cfft_instance_ptr, AxB); 
+ 
+    /* SNR Calculation */ 
+    snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1); 
+     
+    /* Compare the SNR with threshold to test whether the  
+       computed output is matched with the reference output values. */ 
+    if( snr > SNR_THRESHOLD) 
+    { 
+        status = ARM_MATH_SUCCESS; 
+    } 
+         
+    if( status != ARM_MATH_SUCCESS) 
+    { 
+      while(1); 
+    } 
+} 
+                                  
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_dotproduct_example_f32_8c-example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_dotproduct_example_f32_8c-example.html
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index 0000000..2dbc754
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_dotproduct_example_f32_8c-example.html
@@ -0,0 +1,182 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dotproduct_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_dotproduct_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3 
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_dotproduct_example_f32.c          
+*  
+* Description:  Example code computing dot product of two vectors. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include <math.h>     
+#include "arm_math.h" 
+ 
+/* ---------------------------------------------------------------------- 
+* Defines each of the tests performed 
+* ------------------------------------------------------------------- */ 
+#define MAX_BLOCKSIZE   32 
+#define DELTA           (0.000001f) 
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for Floating point Dot Product example for 32-blockSize 
+* Generated by the MATLAB randn() function 
+* ------------------------------------------------------------------- */  
+/* ----------------------------------------------------------------------  
+** Test input data of srcA for blockSize 32   
+** ------------------------------------------------------------------- */  
+float32_t srcA_buf_f32[MAX_BLOCKSIZE] =   
+{   
+-0.4325648115282207,    -1.6655843782380970,    0.1253323064748307,  
+ 0.2876764203585489,    -1.1464713506814637,    1.1909154656429988,  
+ 1.1891642016521031,    -0.0376332765933176,    0.3272923614086541,  
+ 0.1746391428209245,    -0.1867085776814394,    0.7257905482933027,  
+-0.5883165430141887,     2.1831858181971011,   -0.1363958830865957,  
+ 0.1139313135208096,     1.0667682113591888,    0.0592814605236053,  
+-0.0956484054836690,    -0.8323494636500225,    0.2944108163926404,  
+-1.3361818579378040,     0.7143245518189522,    1.6235620644462707,  
+-0.6917757017022868,     0.8579966728282626,    1.2540014216025324,  
+-1.5937295764474768,    -1.4409644319010200,    0.5711476236581780,  
+-0.3998855777153632,     0.6899973754643451 
+};   
+  
+/* ----------------------------------------------------------------------  
+** Test input data of srcB for blockSize 32   
+** ------------------------------------------------------------------- */   
+float32_t srcB_buf_f32[MAX_BLOCKSIZE] =   
+{   
+ 1.7491401329284098,    0.1325982188803279,  0.3252281811989881,     
+-0.7938091410349637,    0.3149236145048914, -0.5272704888029532,     
+ 0.9322666565031119,    1.1646643544607362, -2.0456694357357357,     
+-0.6443728590041911,    1.7410657940825480,  0.4867684246821860,     
+ 1.0488288293660140,    1.4885752747099299,  1.2705014969484090,     
+-1.8561241921210170,    2.1343209047321410,  1.4358467535865909,     
+-0.9173023332875400,   -1.1060770780029008,  0.8105708062681296,     
+ 0.6985430696369063,   -0.4015827425012831,  1.2687512030669628,     
+-0.7836083053674872,    0.2132664971465569,  0.7878984786088954,     
+ 0.8966819356782295,   -0.1869172943544062,  1.0131816724341454,     
+ 0.2484350696132857,    0.0596083377937976 
+};   
+ 
+/* Reference dot product output */ 
+float32_t  refDotProdOut = 5.9273644806352142;   
+ 
+/* ---------------------------------------------------------------------- 
+* Declare Global variables  
+* ------------------------------------------------------------------- */ 
+float32_t multOutput[MAX_BLOCKSIZE];  /* Intermediate output */ 
+float32_t testOutput;  /* Final ouput */ 
+ 
+arm_status status;   /* Status of the example */ 
+
+int32_t main(void) 
+{ 
+    uint32_t i;          /* Loop counter */ 
+    float32_t diff;      /* Difference between reference and test outputs */ 
+ 
+    /* Multiplication of two input buffers */ 
+    arm_mult_f32(srcA_buf_f32, srcB_buf_f32, multOutput, MAX_BLOCKSIZE); 
+     
+    /* Accumulate the multiplication output values to  
+       get the dot product of the two inputs */ 
+    for(i=0; i< MAX_BLOCKSIZE; i++) 
+    {          
+        arm_add_f32(&testOutput, &multOutput[i], &testOutput, 1);    
+    } 
+ 
+    /* absolute value of difference between ref and test */ 
+    diff = fabsf(refDotProdOut - testOutput); 
+     
+    /* Comparison of dot product value with reference */ 
+    if(diff > DELTA) 
+    { 
+        status = ARM_MATH_TEST_FAILURE; 
+    } 
+         
+    if( status == ARM_MATH_TEST_FAILURE) 
+    { 
+      while(1); 
+    } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_fft_bin_example_f32_8c-example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_fft_bin_example_f32_8c-example.html
new file mode 100644
index 0000000..9441dae
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_fft_bin_example_f32_8c-example.html
@@ -0,0 +1,158 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fft_bin_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_fft_bin_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3  
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_fft_bin_example_f32.c         
+*  
+* Description:  Example code demonstrating calculation of Max energy bin of  
+*               frequency domain of input signal. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+ 
+#define TEST_LENGTH_SAMPLES 2048 
+ 
+/* ------------------------------------------------------------------- 
+* External Input and Output buffer Declarations for FFT Bin Example 
+* ------------------------------------------------------------------- */ 
+extern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]; 
+static float32_t testOutput[TEST_LENGTH_SAMPLES/2]; 
+ 
+/* ------------------------------------------------------------------ 
+* Global variables for FFT Bin Example 
+* ------------------------------------------------------------------- */ 
+uint32_t fftSize = 1024; 
+uint32_t ifftFlag = 0; 
+uint32_t doBitReverse = 1; 
+ 
+/* Reference index at which max energy of bin ocuurs */ 
+uint32_t refIndex = 213, testIndex = 0; 
+ 
+/* ---------------------------------------------------------------------- 
+* Max magnitude FFT Bin test 
+* ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+   
+    arm_status status; 
+    arm_cfft_radix4_instance_f32 S; 
+    float32_t maxValue; 
+     
+    status = ARM_MATH_SUCCESS; 
+     
+    /* Initialize the CFFT/CIFFT module */  
+    status = arm_cfft_radix4_init_f32(&S, fftSize,  
+                                    ifftFlag, doBitReverse); 
+     
+    /* Process the data through the CFFT/CIFFT module */ 
+    arm_cfft_radix4_f32(&S, testInput_f32_10khz); 
+     
+     
+    /* Process the data through the Complex Magnitude Module for  
+    calculating the magnitude at each bin */ 
+    arm_cmplx_mag_f32(testInput_f32_10khz, testOutput,  
+                    fftSize);  
+     
+    /* Calculates maxValue and returns corresponding BIN value */ 
+    arm_max_f32(testOutput, fftSize, &maxValue, &testIndex); 
+     
+    if(testIndex !=  refIndex) 
+    { 
+        status = ARM_MATH_TEST_FAILURE; 
+    } 
+     
+    /* ---------------------------------------------------------------------- 
+    ** Loop here if the signals fail the PASS check. 
+    ** This denotes a test failure 
+    ** ------------------------------------------------------------------- */ 
+     
+    if( status != ARM_MATH_SUCCESS) 
+    { 
+        while(1); 
+    } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_fir_example_f32_8c-example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_fir_example_f32_8c-example.html
new file mode 100644
index 0000000..77c118a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_fir_example_f32_8c-example.html
@@ -0,0 +1,203 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_fir_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+ * Copyright (C) 2010 ARM Limited. All rights reserved.   
+ *  
+ * $Date:           29. November 2010  
+ * $Revision:       V1.0.3  
+ *  
+ * Project:         CMSIS DSP Library  
+ * Title:           arm_fir_example_f32.c         
+ *  
+ * Description: Example code demonstrating how an FIR filter can be used
+ *               as a low pass filter.
+ * 
+ * Target Processor: Cortex-M4/Cortex-M3  
+ *
+ *
+ * Version 1.0.3 2010/11/29 
+ *    Re-organized the CMSIS folders and updated documentation. 
+ * 
+ * Version 1.0.1 2010/10/05 KK 
+ *    Production release and review comments incorporated.  
+ *
+ * Version 1.0.0 2010/09/20 KK
+ *    Production release and review comments incorporated.
+ * ------------------------------------------------------------------- */ 
+ 
+/* ---------------------------------------------------------------------- 
+** Include Files  
+** ------------------------------------------------------------------- */ 
+
+#include "arm_math.h" 
+#include "math_helper.h" 
+ 
+/* ---------------------------------------------------------------------- 
+** Macro Defines  
+** ------------------------------------------------------------------- */ 
+
+#define TEST_LENGTH_SAMPLES 320 
+#define SNR_THRESHOLD_F32   140.0f 
+#define BLOCK_SIZE          32 
+#define NUM_TAPS            29 
+ 
+/* ------------------------------------------------------------------- 
+ * The input signal and reference output (computed with MATLAB)
+ * are defined externally in arm_fir_lpf_data.c.
+ * ------------------------------------------------------------------- */ 
+
+extern float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]; 
+extern float32_t refOutput[TEST_LENGTH_SAMPLES]; 
+ 
+/* ------------------------------------------------------------------- 
+ * Declare Test output buffer 
+ * ------------------------------------------------------------------- */ 
+
+static float32_t testOutput[TEST_LENGTH_SAMPLES]; 
+ 
+/* ------------------------------------------------------------------- 
+ * Declare State buffer of size (numTaps + blockSize - 1) 
+ * ------------------------------------------------------------------- */ 
+
+static float32_t firStateF32[BLOCK_SIZE + NUM_TAPS - 1]; 
+ 
+/* ---------------------------------------------------------------------- 
+** FIR Coefficients buffer generated using fir1() MATLAB function. 
+** fir1(28, 6/24)
+** ------------------------------------------------------------------- */ 
+ 
+const float32_t firCoeffs32[NUM_TAPS] = { 
+-0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, 
+-0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, 
++0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, 
++0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f 
+}; 
+ 
+/* ------------------------------------------------------------------ 
+ * Global variables for FIR LPF Example 
+ * ------------------------------------------------------------------- */ 
+
+uint32_t blockSize = BLOCK_SIZE; 
+uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE; 
+ 
+float32_t  snr; 
+ 
+/* ---------------------------------------------------------------------- 
+ * FIR LPF Example 
+ * ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+  uint32_t i; 
+  arm_fir_instance_f32 S; 
+  arm_status status; 
+  float32_t  *inputF32, *outputF32; 
+ 
+  /* Initialize input and output buffer pointers */ 
+  inputF32 = &testInput_f32_1kHz_15kHz[0];   
+  outputF32 = &testOutput[0]; 
+
+  /* Call FIR init function to initialize the instance structure. */
+  arm_fir_init_f32(&S, NUM_TAPS, (float32_t *)&firCoeffs32[0], &firStateF32[0], blockSize); 
+ 
+  /* ---------------------------------------------------------------------- 
+  ** Call the FIR process function for every blockSize samples  
+  ** ------------------------------------------------------------------- */ 
+
+  for(i=0; i < numBlocks; i++)  
+    {    
+      arm_fir_f32(&S, inputF32 + (i * blockSize), outputF32 + (i * blockSize), blockSize);  
+    } 
+ 
+  /* ---------------------------------------------------------------------- 
+  ** Compare the generated output against the reference output computed
+  ** in MATLAB.
+  ** ------------------------------------------------------------------- */ 
+
+  snr = arm_snr_f32(&refOutput[0], &testOutput[0], TEST_LENGTH_SAMPLES); 
+ 
+  if (snr < SNR_THRESHOLD_F32) 
+    { 
+      status = ARM_MATH_TEST_FAILURE; 
+    } 
+  else
+    {
+      status = ARM_MATH_SUCCESS; 
+    }
+     
+  /* ---------------------------------------------------------------------- 
+  ** Loop here if the signal does not match the reference output.
+  ** ------------------------------------------------------------------- */ 
+     
+  if( status != ARM_MATH_SUCCESS) 
+    { 
+      while(1); 
+    } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_graphic_equalizer_example_q31_8c-example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_graphic_equalizer_example_q31_8c-example.html
new file mode 100644
index 0000000..1789bb5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_graphic_equalizer_example_q31_8c-example.html
@@ -0,0 +1,372 @@
+
+
+
+
+CMSIS DSP Software Library: arm_graphic_equalizer_example_q31.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_graphic_equalizer_example_q31.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:         29. November 2010  
+* $Revision:      V1.0.3 
+*  
+* Project:    CMSIS DSP Library  
+* Title:          arm_graphic_equalizer_example_q31.c         
+*  
+* Description:  Example showing an audio graphic equalizer constructed
+*              out of Biquad filters.
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h"
+
+/* Length of the overall data in the test */ 
+#define TESTLENGTH 320
+
+/* Block size for the underlying processing */
+#define BLOCKSIZE 32
+
+/* Total number of blocks to run */
+#define NUMBLOCKS (TESTLENGTH/BLOCKSIZE)
+
+/* Number of 2nd order Biquad stages per filter */
+#define NUMSTAGES 2
+
+#define SNR_THRESHOLD_F32  98
+ 
+/* ------------------------------------------------------------------- 
+ * External Declarations for Input and Output buffers 
+ * ------------------------------------------------------------------- */
+ 
+extern float32_t testInput_f32[TESTLENGTH]; 
+static float32_t testOutput[TESTLENGTH]; 
+
+extern float32_t testRefOutput_f32[TESTLENGTH];
+
+/* ----------------------------------------------------------------------  
+** Q31 state buffers for Band1, Band2, Band3, Band4, Band5  
+** ------------------------------------------------------------------- */  
+   
+static q63_t biquadStateBand1Q31[4 * 2];   
+static q63_t biquadStateBand2Q31[4 * 2];   
+static q31_t biquadStateBand3Q31[4 * 2];   
+static q31_t biquadStateBand4Q31[4 * 2];   
+static q31_t biquadStateBand5Q31[4 * 2];   
+ 
+/* ----------------------------------------------------------------------  
+** Q31 input and output buffers  
+** ------------------------------------------------------------------- */  
+
+q31_t inputQ31[BLOCKSIZE];   
+q31_t outputQ31[BLOCKSIZE];  
+ 
+/* ----------------------------------------------------------------------
+** Entire coefficient table.  There are 10 coefficients per 4th order Biquad
+** cascade filter.  The first 10 coefficients correspond to the -9 dB gain
+** setting of band 1; the next 10 coefficient correspond to the -8 dB gain
+** setting of band 1; and so on.  There are 10*19=190 coefficients in total
+** for band 1 (gains = -9, -8, -7, ..., 9).  After this come the 190 coefficients
+** for band 2.
+**
+** The coefficients are in Q29 format and require a postShift of 2.
+** ------------------------------------------------------------------- */
+
+const q31_t coeffTable[950] = {
+
+    /* Band 1, -9 dB gain */
+    535576962, -1071153923, 535576962, 1073741824, -536870912, 535576962, -1063501998, 527979313, 1060865294, -524146981, 
+    /* Band 1, -8 dB gain */
+    535723226, -1071446451, 535723226, 1073741824, -536870912, 535723226, -1063568947, 527903217, 1061230578, -524503778, 
+    535868593, -1071737186, 535868593, 1073741824, -536870912, 535868593, -1063627467, 527819780, 1061585502, -524850686, 
+    536013181, -1072026363, 536013181, 1073741824, -536870912, 536013181, -1063677598, 527728935, 1061930361, -525187972, 
+    536157109, -1072314217, 536157109, 1073741824, -536870912, 536157109, -1063719372, 527630607, 1062265438, -525515897, 
+    536300492, -1072600983, 536300492, 1073741824, -536870912, 536300492, -1063752815, 527524720, 1062591011, -525834716, 
+    536443447, -1072886894, 536443447, 1073741824, -536870912, 536443447, -1063777945, 527411186, 1062907350, -526144676, 
+    536586091, -1073172183, 536586091, 1073741824, -536870912, 536586091, -1063794775, 527289917, 1063214717, -526446017, 
+    536728541, -1073457082, 536728541, 1073741824, -536870912, 536728541, -1063803308, 527160815, 1063513366, -526738975, 
+    536870912, -1073741824, 536870912, 1073741824, -536870912, 536870912, -1063803543, 527023777, 1063803543, -527023777, 
+    537013321, -1074026642, 537013321, 1073741824, -536870912, 537013321, -1063795470, 526878696, 1064085490, -527300648, 
+    537155884, -1074311768, 537155884, 1073741824, -536870912, 537155884, -1063779073, 526725455, 1064359439, -527569803, 
+    537298718, -1074597435, 537298718, 1073741824, -536870912, 537298718, -1063754328, 526563934, 1064625617, -527831454, 
+    537441939, -1074883878, 537441939, 1073741824, -536870912, 537441939, -1063721205, 526394005, 1064884245, -528085806, 
+    537585666, -1075171331, 537585666, 1073741824, -536870912, 537585666, -1063679666, 526215534, 1065135536, -528333059, 
+    537730015, -1075460030, 537730015, 1073741824, -536870912, 537730015, -1063629666, 526028380, 1065379699, -528573409, 
+    537875106, -1075750212, 537875106, 1073741824, -536870912, 537875106, -1063571152, 525832396, 1065616936, -528807045, 
+    538021057, -1076042114, 538021057, 1073741824, -536870912, 538021057, -1063504065, 525627429, 1065847444, -529034151, 
+    538167989, -1076335977, 538167989, 1073741824, -536870912, 538167989, -1063428338, 525413317, 1066071412, -529254907, 
+    
+    /* Band 2, -9 dB gain */
+    531784976, -1055497692, 523873415, 1066213307, -529420241, 531784976, -1040357886, 509828014, 1028908252, -494627367,
+    /* Band 2, -8 dB gain */ 
+    532357636, -1056601982, 524400080, 1066115844, -529326645, 532357636, -1040623406, 509562600, 1030462237, -496062122, 
+    532927392, -1057707729, 524931110, 1066024274, -529239070, 532927392, -1040848253, 509262081, 1031969246, -497457090, 
+    533494678, -1058816094, 525467240, 1065939047, -529157961, 533494678, -1041032161, 508925950, 1033429976, -498812573, 
+    534059929, -1059928204, 526009170, 1065860582, -529083734, 534059929, -1041174868, 508553717, 1034845124, -500128887, 
+    534623580, -1061045148, 526557561, 1065789260, -529016764, 534623580, -1041276126, 508144920, 1036215393, -501406373, 
+    535186068, -1062167969, 527113032, 1065725420, -528957385, 535186068, -1041335703, 507699125, 1037541500, -502645399, 
+    535747827, -1063297666, 527676151, 1065669351, -528905879, 535747827, -1041353386, 507215934, 1038824183, -503846368, 
+    536309295, -1064435183, 528247436, 1065621289, -528862476, 536309295, -1041328990, 506694984, 1040064203, -505009724, 
+    536870912, -1065581413, 528827349, 1065581413, -528827349, 536870912, -1041262354, 506135953, 1041262354, -506135953, 
+    537433117, -1066737194, 529416295, 1065549847, -528800610, 537433117, -1041153346, 505538564, 1042419457, -507225588, 
+    537996352, -1067903307, 530014622, 1065526651, -528782316, 537996352, -1041001864, 504902578, 1043536370, -508279208, 
+    538561061, -1069080480, 530622620, 1065511830, -528772462, 538561061, -1040807833, 504227800, 1044613981, -509297437, 
+    539127690, -1070269387, 531240527, 1065505333, -528770987, 539127690, -1040571205, 503514074, 1045653211, -510280946, 
+    539696690, -1071470656, 531868525, 1065507054, -528777778, 539696690, -1040291951, 502761277, 1046655011, -511230450, 
+    540268512, -1072684867, 532506750, 1065516837, -528792672, 540268512, -1039970063, 501969320, 1047620358, -512146700, 
+    540843613, -1073912567, 533155297, 1065534483, -528815459, 540843613, -1039605542, 501138139, 1048550251, -513030484, 
+    541422451, -1075154268, 533814224, 1065559750, -528845892, 541422451, -1039198394, 500267687, 1049445708, -513882621, 
+    542005489, -1076410460, 534483561, 1065592362, -528883686, 542005489, -1038748624, 499357932, 1050307760, -514703956, 
+    518903861, -1001986830, 486725277, 1037235801, -502367695, 518903861, -945834422, 446371043, 902366163, -400700571, 
+    520899989, -1005630916, 488289126, 1036926846, -502147311, 520899989, -946490935, 445581846, 907921945, -404936158, 
+    522893209, -1009290002, 489869792, 1036650484, -501961419, 522893209, -947006359, 444685310, 913306106, -409075225, 
+    524884763, -1012968199, 491470256, 1036407567, -501810737, 524884763, -947377809, 443679533, 918521018, -413116221, 
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+    531970251, -916177781, 425530105, 925084675, -427617023, 531970251, -661143261, 324000998, 648462180, -315420352, 
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+    546810467, -942560921, 434712438, 924487114, -430467639, 546810467, -650483688, 315220754, 676214053, -332613816, 
+    551855042, -951688708, 437975532, 924420027, -431546101, 551855042, -646115970, 311939896, 684931422, -338134495, 
+    556953421, -961000826, 441354588, 924413001, -432680993, 556953421, -641320513, 308486839, 693391970, -343545389, 
+    562108672, -970508005, 444858642, 924462435, -433867780, 562108672, -636084967, 304865786, 701601770, -348844597, 
+    567323959, -980220994, 448496743, 924564764, -435102022, 567323959, -630397020, 301081886, 709566963, -354030710, 
+    572602539, -990150500, 452277894, 924716482, -436379394, 572602539, -624244471, 297141281, 717293726, -359102767, 
+    577947763, -1000307125, 456210977, 924914158, -437695705, 577947763, -617615296, 293051155, 724788245, -364060214, 
+    583363084, -1010701292, 460304674, 925154455, -439046908, 583363084, -610497723, 288819761, 732056685, -368902865, 
+    387379495, -506912469, 196933274, 840112184, -347208270, 387379495, 506912469, 196933274, -840112184, -347208270, 
+    401658082, -532275898, 207149427, 833765363, -343175316, 401658082, 532275898, 207149427, -833765363, -343175316, 
+    416472483, -558722695, 217902617, 827270154, -339107319, 416472483, 558722695, 217902617, -827270154, -339107319, 
+    431841949, -586290861, 229212798, 820624988, -335007540, 431841949, 586290861, 229212798, -820624988, -335007540, 
+    447786335, -615019650, 241100489, 813828443, -330879528, 447786335, 615019650, 241100489, -813828443, -330879528, 
+    464326111, -644949597, 253586805, 806879270, -326727141, 464326111, 644949597, 253586805, -806879270, -326727141, 
+    481482377, -676122557, 266693475, 799776409, -322554559, 481482377, 676122557, 266693475, -799776409, -322554559, 
+    499276882, -708581728, 280442865, 792519013, -318366296, 499276882, 708581728, 280442865, -792519013, -318366296, 
+    517732032, -742371685, 294857996, 785106465, -314167221, 517732032, 742371685, 294857996, -785106465, -314167221, 
+    536870912, -777538408, 309962566, 777538408, -309962566, 536870912, 777538408, 309962566, -777538408, -309962566, 
+    556717294, -814129313, 325780968, 769814766, -305757943, 556717294, 814129313, 325780968, -769814766, -305757943, 
+    577295658, -852193284, 342338310, 761935777, -301559360, 577295658, 852193284, 342338310, -761935777, -301559360, 
+    598631206, -891780698, 359660433, 753902014, -297373230, 598631206, 891780698, 359660433, -753902014, -297373230, 
+    620749877, -932943463, 377773927, 745714425, -293206383, 620749877, 932943463, 377773927, -745714425, -293206383, 
+    643678365, -975735041, 396706151, 737374355, -289066077, 643678365, 975735041, 396706151, -737374355, -289066077, 
+    667444134, -1020210487, 416485252, 728883588, -284960004, 667444134, 1020210487, 416485252, -728883588, -284960004, 
+    692075438, -1066426476, 437140179, 720244375, -280896294, 692075438, 1066426476, 437140179, -720244375, -280896294, 
+    717601336, -1114441339, 458700704, 711459472, -276883515, 717601336, 1114441339, 458700704, -711459472, -276883515, 
+    744051710, -1164315096, 481197437, 702532174, -272930673, 744051710, 1164315096, 481197437, -702532174, -272930673 
+
+};
+
+/* ----------------------------------------------------------------------
+** Desired gains, in dB, per band
+** ------------------------------------------------------------------- */
+
+int gainDB[5] = {0, -3, 6, 4, -6};
+
+float32_t snr;
+
+
+/* ---------------------------------------------------------------------- 
+ * Graphic equalizer Example 
+ * ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+  float32_t  *inputF32, *outputF32;  
+  arm_biquad_cas_df1_32x64_ins_q31 S1; 
+  arm_biquad_cas_df1_32x64_ins_q31 S2; 
+  arm_biquad_casd_df1_inst_q31 S3; 
+  arm_biquad_casd_df1_inst_q31 S4; 
+  arm_biquad_casd_df1_inst_q31 S5; 
+  int i;
+  int32_t status;
+     
+  inputF32 = &testInput_f32[0];  
+  outputF32 = &testOutput[0]; 
+     
+  /* Initialize the state and coefficient buffers for all Biquad sections */
+
+  arm_biquad_cas_df1_32x64_init_q31(&S1, NUMSTAGES, 
+                    (q31_t *) &coeffTable[190*0 + 10*(gainDB[0] + 9)],
+                    &biquadStateBand1Q31[0], 2);
+
+  arm_biquad_cas_df1_32x64_init_q31(&S2, NUMSTAGES, 
+                    (q31_t *) &coeffTable[190*1 + 10*(gainDB[1] + 9)],
+                    &biquadStateBand2Q31[0], 2);
+     
+  arm_biquad_cascade_df1_init_q31(&S3, NUMSTAGES, 
+                  (q31_t *) &coeffTable[190*2 + 10*(gainDB[2] + 9)],
+                  &biquadStateBand3Q31[0], 2);
+
+  arm_biquad_cascade_df1_init_q31(&S4, NUMSTAGES, 
+                  (q31_t *) &coeffTable[190*3 + 10*(gainDB[3] + 9)],
+                  &biquadStateBand4Q31[0], 2); 
+     
+  arm_biquad_cascade_df1_init_q31(&S5, NUMSTAGES, 
+                  (q31_t *) &coeffTable[190*4 + 10*(gainDB[4] + 9)],
+                  &biquadStateBand5Q31[0], 2); 
+     
+ 
+  /* Call the process functions and needs to change filter coefficients  
+     for varying the gain of each band */ 
+ 
+  for(i=0; i < NUMBLOCKS; i++) 
+    {    
+
+      /* ---------------------------------------------------------------------- 
+      ** Convert block of input data from float to Q31 
+      ** ------------------------------------------------------------------- */ 
+
+      arm_float_to_q31(inputF32 + (i*BLOCKSIZE), inputQ31, BLOCKSIZE);     
+         
+      /* ----------------------------------------------------------------------
+      ** Scale down by 1/8.  This provides additional headroom so that the
+      ** graphic EQ can apply gain.
+      ** ------------------------------------------------------------------- */
+
+      arm_scale_q31(inputQ31, 0x7FFFFFFF, -3, inputQ31, BLOCKSIZE);
+
+      /* ----------------------------------------------------------------------
+      ** Call the Q31 Biquad Cascade DF1 32x64 process function for band1, band2
+      ** ------------------------------------------------------------------- */
+
+      arm_biquad_cas_df1_32x64_q31(&S1, inputQ31, outputQ31, BLOCKSIZE); 
+      arm_biquad_cas_df1_32x64_q31(&S2, outputQ31, outputQ31, BLOCKSIZE); 
+
+      /* ---------------------------------------------------------------------- 
+      ** Call the Q31 Biquad Cascade DF1 process function for band3, band4, band5
+      ** ------------------------------------------------------------------- */        
+
+      arm_biquad_cascade_df1_q31(&S3, outputQ31, outputQ31, BLOCKSIZE); 
+      arm_biquad_cascade_df1_q31(&S4, outputQ31, outputQ31, BLOCKSIZE);  
+      arm_biquad_cascade_df1_q31(&S5, outputQ31, outputQ31, BLOCKSIZE); 
+ 
+      /* ---------------------------------------------------------------------- 
+      ** Convert Q31 result back to float 
+      ** ------------------------------------------------------------------- */ 
+
+      arm_q31_to_float(outputQ31, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);
+
+      /* ---------------------------------------------------------------------- 
+      ** Scale back up
+      ** ------------------------------------------------------------------- */ 
+
+      arm_scale_f32(outputF32 + (i * BLOCKSIZE), 8.0f, outputF32 + (i * BLOCKSIZE), BLOCKSIZE);
+    }; 
+
+    snr = arm_snr_f32(testRefOutput_f32, testOutput, TESTLENGTH);
+
+    if (snr < SNR_THRESHOLD_F32) 
+    { 
+        status = ARM_MATH_TEST_FAILURE; 
+    } 
+    else
+    {
+        status = ARM_MATH_SUCCESS; 
+    }
+         
+  /* ---------------------------------------------------------------------- 
+  ** Loop here if the signal does not match the reference output.
+  ** ------------------------------------------------------------------- */ 
+     
+  if( status != ARM_MATH_SUCCESS) 
+    { 
+      while(1); 
+    } 
+
+
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_linear_interp_example_f32_8c-example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_linear_interp_example_f32_8c-example.html
new file mode 100644
index 0000000..544a5e7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_linear_interp_example_f32_8c-example.html
@@ -0,0 +1,202 @@
+
+
+
+
+CMSIS DSP Software Library: arm_linear_interp_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_linear_interp_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3 
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_linear_interp_example_f32.c       
+*  
+* Description:  Example code demonstrating usage of sin function  
+*               and uses linear interpolation to get higher precision 
+*                
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h" 
+ 
+#define SNR_THRESHOLD           90 
+#define TEST_LENGTH_SAMPLES     10 
+#define XSPACING                (0.00005f)
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for F32 SIN function 
+* Generated by the MATLAB rand() function 
+* randn('state', 0)
+* xi = (((1/4.18318581819710)* randn(blockSize, 1) * 2* pi));
+* --------------------------------------------------------------------*/ 
+float32_t testInputSin_f32[TEST_LENGTH_SAMPLES] =  
+{
+    -0.649716504673081170,  -2.501723745497831200,  0.188250329003310100,   0.432092748487532540,   -1.722010988459680800,  1.788766476323060600,   1.786136060975809500,   -0.056525543169408797,  
+    0.491596272728153760,   0.262309671126153390   
+};  
+ 
+/*------------------------------------------------------------------------------ 
+*  Reference out of SIN F32 function for Block Size = 10  
+*  Calculated from sin(testInputSin_f32) 
+*------------------------------------------------------------------------------*/ 
+float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES] =   
+{
+    -0.604960695383043530,  -0.597090287967934840,  0.187140422442966500,   0.418772124875992690,   -0.988588831792106880,  0.976338412038794010,   0.976903856413481100,   -0.056495446835214236,  
+    0.472033731854734240,   0.259311907228582830
+}; 
+ 
+/*------------------------------------------------------------------------------ 
+*  Method 1: Test out Buffer Calculated from Cubic Interpolation 
+*------------------------------------------------------------------------------*/ 
+float32_t testOutput[TEST_LENGTH_SAMPLES]; 
+ 
+/*------------------------------------------------------------------------------ 
+*  Method 2: Test out buffer Calculated from Linear Interpolation 
+*------------------------------------------------------------------------------*/ 
+float32_t testLinIntOutput[TEST_LENGTH_SAMPLES]; 
+
+/*------------------------------------------------------------------------------ 
+*  External table used for linear interpolation 
+*------------------------------------------------------------------------------*/ 
+extern float32_t arm_linear_interep_table[188495];
+ 
+/* ---------------------------------------------------------------------- 
+* Global Variables for caluclating SNR's for Method1 & Method 2 
+* ------------------------------------------------------------------- */ 
+float32_t snr1; 
+float32_t snr2; 
+ 
+/* ---------------------------------------------------------------------------- 
+* Calculation of Sine values from Cubic Interpolation and Linear interpolation 
+* ---------------------------------------------------------------------------- */ 
+int32_t main(void) 
+{ 
+    uint32_t i; 
+    arm_status status; 
+            
+    arm_linear_interp_instance_f32 S = {188495, -3.141592653589793238, XSPACING, &arm_linear_interep_table[0]}; 
+
+    /*------------------------------------------------------------------------------ 
+    *  Method 1: Test out Calculated from Cubic Interpolation 
+    *------------------------------------------------------------------------------*/ 
+    for(i=0; i< TEST_LENGTH_SAMPLES; i++) 
+    { 
+        testOutput[i] = arm_sin_f32(testInputSin_f32[i]); 
+    } 
+     
+    /*------------------------------------------------------------------------------ 
+    *  Method 2: Test out Calculated from Cubic Interpolation and Linear interpolation 
+    *------------------------------------------------------------------------------*/
+    
+    for(i=0; i< TEST_LENGTH_SAMPLES; i++) 
+    { 
+        testLinIntOutput[i] = arm_linear_interp_f32(&S, testInputSin_f32[i]);
+    }
+ 
+    /*------------------------------------------------------------------------------ 
+    *                   SNR calculation for method 1 
+    *------------------------------------------------------------------------------*/   
+    snr1 = arm_snr_f32(testRefSinOutput32_f32, testOutput, 2); 
+ 
+    /*------------------------------------------------------------------------------ 
+    *                   SNR calculation for method 2 
+    *------------------------------------------------------------------------------*/   
+    snr2 = arm_snr_f32(testRefSinOutput32_f32, testLinIntOutput, 2); 
+     
+    /*------------------------------------------------------------------------------ 
+    *                   Initialise status depending on SNR calculations 
+    *------------------------------------------------------------------------------*/  
+    if( snr2 > snr1) 
+    { 
+        status = ARM_MATH_SUCCESS; 
+    } 
+    else 
+    { 
+        status = ARM_MATH_TEST_FAILURE; 
+    } 
+     
+    /* ---------------------------------------------------------------------- 
+    ** Loop here if the signals fail the PASS check. 
+    ** This denotes a test failure 
+    ** ------------------------------------------------------------------- */ 
+    if( status != ARM_MATH_SUCCESS) 
+    { 
+        while(1); 
+    } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_matrix_example_f32_8c-example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_matrix_example_f32_8c-example.html
new file mode 100644
index 0000000..428e486
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_matrix_example_f32_8c-example.html
@@ -0,0 +1,231 @@
+
+
+
+
+CMSIS DSP Software Library: arm_matrix_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_matrix_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_matrix_example_f32.c          
+*  
+* Description:  Example code demonstrating least square fit to data  
+*               using matrix functions  
+*                
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h" 
+ 
+#define SNR_THRESHOLD   90 
+ 
+/* -------------------------------------------------------------------------------- 
+* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize  
+* and tapSize 
+* --------------------------------------------------------------------------------- */ 
+ 
+const float32_t B_f32[4] =  
+{    
+    782.0, 7577.0, 470.0, 4505.0 
+}; 
+ 
+/* -------------------------------------------------------------------------------- 
+* Formula to fit is  C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize 
+* -------------------------------------------------------------------------------- */ 
+ 
+const float32_t A_f32[16] =  
+{ 
+    /* Const,   numTaps,    blockSize,  numTaps*blockSize */    
+    1.0,        32.0,       4.0,        128.0,  
+    1.0,        32.0,       64.0,       2048.0, 
+    1.0,        16.0,       4.0,        64.0, 
+    1.0,        16.0,       64.0,       1024.0, 
+};  
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Temporary buffers  for storing intermediate values 
+* ------------------------------------------------------------------- */ 
+/* Transpose of A Buffer */ 
+float32_t AT_f32[16]; 
+/* (Transpose of A * A) Buffer */ 
+float32_t ATMA_f32[16]; 
+/* Inverse(Transpose of A * A)  Buffer */ 
+float32_t ATMAI_f32[16]; 
+/* Test Output Buffer */ 
+float32_t X_f32[4]; 
+ 
+/* ---------------------------------------------------------------------- 
+* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB  
+* ------------------------------------------------------------------- */ 
+const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875}; 
+ 
+float32_t snr; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Max magnitude FFT Bin test 
+* ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+ 
+    arm_matrix_instance_f32 A;      /* Matrix A Instance */ 
+    arm_matrix_instance_f32 AT;     /* Matrix AT(A transpose) instance */ 
+    arm_matrix_instance_f32 ATMA;   /* Matrix ATMA( AT multiply with A) instance */ 
+    arm_matrix_instance_f32 ATMAI;  /* Matrix ATMAI(Inverse of ATMA) instance */ 
+    arm_matrix_instance_f32 B;      /* Matrix B instance */ 
+    arm_matrix_instance_f32 X;      /* Matrix X(Unknown Matrix) instance */ 
+ 
+    uint32_t srcRows, srcColumns;   /* Temporary variables */
+    arm_status status; 
+ 
+    /* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */ 
+    srcRows = 4; 
+    srcColumns = 4; 
+    arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32); 
+ 
+    /* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */ 
+    srcRows = 4; 
+    srcColumns = 4; 
+    arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32); 
+ 
+    /* calculation of A transpose */ 
+    status = arm_mat_trans_f32(&A, &AT); 
+     
+ 
+    /* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */ 
+    srcRows = 4; 
+    srcColumns = 4; 
+    arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32); 
+ 
+    /* calculation of AT Multiply with A */ 
+    status = arm_mat_mult_f32(&AT, &A, &ATMA); 
+ 
+    /* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */ 
+    srcRows = 4; 
+    srcColumns = 4; 
+    arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32); 
+ 
+    /* calculation of Inverse((Transpose(A) * A) */ 
+    status = arm_mat_inverse_f32(&ATMA, &ATMAI); 
+ 
+    /* calculation of (Inverse((Transpose(A) * A)) *  Transpose(A)) */ 
+    status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA); 
+ 
+    /* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */ 
+    srcRows = 4; 
+    srcColumns = 1; 
+    arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32);  
+ 
+    /* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */ 
+    srcRows = 4; 
+    srcColumns = 1; 
+    arm_mat_init_f32(&X, srcRows, srcColumns, X_f32); 
+ 
+    /* calculation ((Inverse((Transpose(A) * A)) *  Transpose(A)) * B) */ 
+    status = arm_mat_mult_f32(&ATMA, &B, &X); 
+     
+    /* Comparison of reference with test output */     
+    snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4); 
+ 
+    /*------------------------------------------------------------------------------ 
+    *                   Initialise status depending on SNR calculations 
+    *------------------------------------------------------------------------------*/  
+    if( snr > SNR_THRESHOLD) 
+    { 
+        status = ARM_MATH_SUCCESS; 
+    } 
+    else 
+    { 
+        status = ARM_MATH_TEST_FAILURE; 
+    } 
+ 
+     
+    /* ---------------------------------------------------------------------- 
+    ** Loop here if the signals fail the PASS check. 
+    ** This denotes a test failure 
+    ** ------------------------------------------------------------------- */    
+    if( status != ARM_MATH_SUCCESS) 
+    { 
+      while(1); 
+    } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_signal_converge_example_f32_8c-example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_signal_converge_example_f32_8c-example.html
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@@ -0,0 +1,241 @@
+
+
+
+
+CMSIS DSP Software Library: arm_signal_converge_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_signal_converge_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_signal_converge_example_f32.c         
+*  
+* Description:  Example code demonstrating convergence of an adaptive 
+*               filter. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include "arm_math.h" 
+#include "math_helper.h" 
+ 
+/* ---------------------------------------------------------------------- 
+** Global defines for the simulation 
+* ------------------------------------------------------------------- */ 
+ 
+#define TEST_LENGTH_SAMPLES 1536 
+#define NUMTAPS             32 
+#define BLOCKSIZE           32 
+#define DELTA_ERROR         0.000001f 
+#define DELTA_COEFF         0.0001f 
+#define MU                  0.5f 
+ 
+#define NUMFRAMES (TEST_LENGTH_SAMPLES / BLOCKSIZE) 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare FIR state buffers and structure  
+* ------------------------------------------------------------------- */ 
+  
+float32_t firStateF32[NUMTAPS + BLOCKSIZE];  
+arm_fir_instance_f32 LPF_instance; 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare LMSNorm state buffers and structure  
+* ------------------------------------------------------------------- */ 
+  
+float32_t lmsStateF32[NUMTAPS + BLOCKSIZE];  
+float32_t errOutput[TEST_LENGTH_SAMPLES]; 
+arm_lms_norm_instance_f32 lmsNorm_instance; 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Function Declarations for Signal Convergence Example  
+* ------------------------------------------------------------------- */ 
+ 
+arm_status test_signal_converge_example( void ); 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Internal functions 
+* ------------------------------------------------------------------- */ 
+arm_status test_signal_converge(float32_t* err_signal, 
+                                 uint32_t blockSize); 
+ 
+void getinput(float32_t* input, 
+         uint32_t fr_cnt,  
+         uint32_t blockSize);  
+ 
+/* ---------------------------------------------------------------------- 
+* External Declarations for FIR F32 module Test 
+* ------------------------------------------------------------------- */ 
+extern float32_t testInput_f32[TEST_LENGTH_SAMPLES]; 
+extern float32_t lmsNormCoeff_f32[32]; 
+extern const float32_t FIRCoeff_f32[32]; 
+extern arm_lms_norm_instance_f32 lmsNorm_instance; 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare I/O buffers  
+* ------------------------------------------------------------------- */ 
+ 
+float32_t wire1[BLOCKSIZE]; 
+float32_t wire2[BLOCKSIZE]; 
+float32_t wire3[BLOCKSIZE]; 
+float32_t err_signal[BLOCKSIZE]; 
+ 
+/* ---------------------------------------------------------------------- 
+* Signal converge test 
+* ------------------------------------------------------------------- */ 
+ 
+int32_t main(void) 
+{ 
+  uint32_t i; 
+  arm_status status; 
+  uint32_t index; 
+  float32_t minValue; 
+ 
+  /* Initialize the LMSNorm data structure */ 
+  arm_lms_norm_init_f32(&lmsNorm_instance, NUMTAPS, lmsNormCoeff_f32, lmsStateF32, MU, BLOCKSIZE); 
+ 
+  /* Initialize the FIR data structure */ 
+  arm_fir_init_f32(&LPF_instance, NUMTAPS, (float32_t *)FIRCoeff_f32, firStateF32, BLOCKSIZE); 
+ 
+  /* ---------------------------------------------------------------------- 
+  * Loop over the frames of data and execute each of the processing 
+  * functions in the system. 
+  * ------------------------------------------------------------------- */ 
+ 
+  for(i=0; i < NUMFRAMES; i++)  
+    { 
+      /* Read the input data - uniformly distributed random noise - into wire1 */  
+      arm_copy_f32(testInput_f32 + (i * BLOCKSIZE), wire1, BLOCKSIZE); 
+ 
+      /* Execute the FIR processing function.  Input wire1 and output wire2 */  
+      arm_fir_f32(&LPF_instance, wire1, wire2, BLOCKSIZE); 
+       
+      /* Execute the LMS Norm processing function*/  
+ 
+      arm_lms_norm_f32(&lmsNorm_instance, /* LMSNorm instance */ 
+               wire1,                     /* Input signal */  
+               wire2,                     /* Reference Signal */ 
+               wire3,                     /* Converged Signal */ 
+               err_signal,                /* Error Signal, this will become small as the signal converges */ 
+               BLOCKSIZE);                /* BlockSize */ 
+ 
+      /* apply overall gain */  
+      arm_scale_f32(wire3, 5, wire3, BLOCKSIZE);     /* in-place buffer */  
+    } 
+ 
+  status = ARM_MATH_SUCCESS; 
+ 
+  /* ------------------------------------------------------------------------------- 
+  * Test whether the error signal has reached towards 0. 
+  * ----------------------------------------------------------------------------- */ 
+ 
+  arm_abs_f32(err_signal, err_signal, BLOCKSIZE); 
+  arm_min_f32(err_signal, BLOCKSIZE, &minValue, &index); 
+ 
+  if (minValue > DELTA_ERROR) 
+  { 
+      status = ARM_MATH_TEST_FAILURE; 
+  } 
+ 
+  /* ---------------------------------------------------------------------- 
+  * Test whether the filter coefficients have converged. 
+  * ------------------------------------------------------------------- */ 
+ 
+  arm_sub_f32((float32_t *)FIRCoeff_f32, lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); 
+ 
+  arm_abs_f32(lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); 
+  arm_min_f32(lmsNormCoeff_f32, NUMTAPS, &minValue, &index); 
+ 
+  if (minValue > DELTA_COEFF) 
+  { 
+      status = ARM_MATH_TEST_FAILURE; 
+  } 
+ 
+  /* ---------------------------------------------------------------------- 
+  * Loop here if the signals did not pass the convergence check. 
+  * This denotes a test failure 
+  * ------------------------------------------------------------------- */ 
+ 
+  if( status != ARM_MATH_SUCCESS) 
+  { 
+      while(1); 
+  } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_sin_cos_example_f32_8c-example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_sin_cos_example_f32_8c-example.html
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@@ -0,0 +1,167 @@
+
+
+
+
+CMSIS DSP Software Library: arm_sin_cos_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_sin_cos_example_f32.c
  

+

+

+
/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*  
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3
+*  
+* Project:      CMSIS DSP Library  
+* Title:        arm_sin_cos_example_f32.c         
+*  
+* Description:  Example code demonstrating sin and cos calculation of input signal. 
+* 
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */ 
+ 
+#include <math.h>     
+#include "arm_math.h" 
+ 
+/* ---------------------------------------------------------------------- 
+* Defines each of the tests performed 
+* ------------------------------------------------------------------- */ 
+#define MAX_BLOCKSIZE   32 
+#define DELTA           (0.000001f) 
+ 
+ 
+/* ---------------------------------------------------------------------- 
+* Test input data for Floating point sin_cos example for 32-blockSize 
+* Generated by the MATLAB randn() function 
+* ------------------------------------------------------------------- */ 
+ 
+const float32_t testInput_f32[MAX_BLOCKSIZE] =  
+{    
+    -1.244916875853235400,  -4.793533929171324800,  0.360705030233248850,   0.827929644170887320,   -3.299532218312426900,  3.427441903227623800,   3.422401784294607700,   -0.108308165334010680,   
+    0.941943896490312180,   0.502609575000365850,   -0.537345278736373500,  2.088817392965764500,   -1.693168684143455700,  6.283185307179590700,   -0.392545884746175080,  0.327893095115825040,    
+    3.070147440456292300,   0.170611405884662230,   -0.275275082396073010,  -2.395492805446796300,  0.847311163536506600,   -3.845517018083148800,  2.055818378415868300,   4.672594161978930800,    
+    -1.990923030266425800,  2.469305197656249500,   3.609002606064021000,   -4.586736582331667500,  -4.147080139136136300,  1.643756718868359500,   -1.150866392366494800,  1.985805026477433800 
+ 
+ 
+};  
+ 
+const float32_t testRefOutput_f32 = 1.000000000; 
+ 
+/* ---------------------------------------------------------------------- 
+* Declare Global variables  
+* ------------------------------------------------------------------- */ 
+uint32_t blockSize = 32; 
+float32_t  testOutput;  
+float32_t  cosOutput;  
+float32_t  sinOutput;  
+float32_t  cosSquareOutput;  
+float32_t  sinSquareOutput; 
+ 
+/* ---------------------------------------------------------------------- 
+* Max magnitude FFT Bin test 
+* ------------------------------------------------------------------- */ 
+
+arm_status status; 
+ 
+int32_t main(void) 
+{ 
+    float32_t diff; 
+    uint32_t i; 
+ 
+    for(i=0; i< blockSize; i++) 
+    { 
+        cosOutput = arm_cos_f32(testInput_f32[i]); 
+        sinOutput = arm_sin_f32(testInput_f32[i]); 
+ 
+        arm_mult_f32(&cosOutput, &cosOutput, &cosSquareOutput, 1); 
+        arm_mult_f32(&sinOutput, &sinOutput, &sinSquareOutput, 1); 
+ 
+        arm_add_f32(&cosSquareOutput, &sinSquareOutput, &testOutput, 1);
+ 
+        /* absolute value of difference between ref and test */ 
+        diff = fabsf(testRefOutput_f32 - testOutput); 
+     
+        /* Comparison of sin_cos value with reference */ 
+        if(diff > DELTA) 
+        { 
+           status = ARM_MATH_TEST_FAILURE; 
+        } 
+         
+        if( status == ARM_MATH_TEST_FAILURE) 
+        { 
+           while(1); 
+        } 
+ 
+    } 
+} 
+ 
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_variance_example_f32_8c-example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/arm_variance_example_f32_8c-example.html
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@@ -0,0 +1,201 @@
+
+
+
+
+CMSIS DSP Software Library: arm_variance_example_f32.c
+
+
+
+
+
+
+
+
+
+

+  

+
arm_variance_example_f32.c
  

+

+

+
/* ----------------------------------------------------------------------    
+* Copyright (C) 2010 ARM Limited. All rights reserved.     
+*    
+* $Date:        29. November 2010  
+* $Revision:    V1.0.3
+*     
+* Project:      CMSIS DSP Library  
+* Title:        arm_variance_example_f32.c       
+* 
+* Description:  Example code demonstrating variance calculation of input sequence.
+*     
+* Target Processor: Cortex-M4/Cortex-M3  
+*
+*
+* Version 1.0.3 2010/11/29 
+*    Re-organized the CMSIS folders and updated documentation. 
+* 
+* Version 1.0.1 2010/10/05 KK 
+*    Production release and review comments incorporated.  
+*
+* Version 1.0.0 2010/09/20 KK
+*    Production release and review comments incorporated.
+* ------------------------------------------------------------------- */
+
+#include <math.h>    
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+* Defines each of the tests performed
+* ------------------------------------------------------------------- */
+#define MAX_BLOCKSIZE   32
+#define DELTA           (0.000001f)
+
+
+/* ----------------------------------------------------------------------
+* Declare I/O buffers 
+* ------------------------------------------------------------------- */
+float32_t wire1[MAX_BLOCKSIZE];
+float32_t wire2[MAX_BLOCKSIZE];
+float32_t wire3[MAX_BLOCKSIZE];
+
+/* ----------------------------------------------------------------------
+* Test input data for Floating point Variance example for 32-blockSize
+* Generated by the MATLAB randn() function
+* ------------------------------------------------------------------- */
+
+float32_t testInput_f32[32] = 
+{ 
+-0.432564811528221,     -1.665584378238097,     0.125332306474831,      0.287676420358549,  
+-1.146471350681464,     1.190915465642999,      1.189164201652103,      -0.037633276593318,     
+0.327292361408654,      0.174639142820925,      -0.186708577681439,     0.725790548293303,  
+-0.588316543014189,     2.183185818197101,      -0.136395883086596,     0.113931313520810,  
+1.066768211359189,      0.059281460523605,      -0.095648405483669,     -0.832349463650022,     
+0.294410816392640,      -1.336181857937804,     0.714324551818952,      1.623562064446271,  
+-0.691775701702287,     0.857996672828263,      1.254001421602532,      -1.593729576447477,     
+-1.440964431901020,     0.571147623658178,      -0.399885577715363,     0.689997375464345
+  
+};
+
+/* ----------------------------------------------------------------------
+* Declare Global variables 
+* ------------------------------------------------------------------- */
+uint32_t blockSize = 32;
+float32_t  refVarianceOut = 0.903941793931839; 
+
+/* ----------------------------------------------------------------------
+* Variance calculation test
+* ------------------------------------------------------------------- */
+
+int32_t main(void)
+{
+    arm_status status;
+    float32_t mean, oneByBlockSize;
+    float32_t variance;
+    float32_t diff;
+    
+    status = ARM_MATH_SUCCESS;
+    
+    /* Calculation of mean value of input */
+    
+    /* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */
+    
+    /* Fill wire1 buffer with 1.0 value */
+    arm_fill_f32(1.0,  wire1, blockSize);
+    
+    /* Calculate the dot product of wire1 and wire2 */
+    /* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */
+    arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean);
+    
+    /* Calculation of 1/blockSize */
+    oneByBlockSize = 1.0 / (blockSize);
+    
+    /* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1)  */
+    arm_mult_f32(&mean, &oneByBlockSize, &mean, 1);
+    
+    
+    /* Calculation of variance value of input */
+    
+    /* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */
+    
+    /* Fill wire2 with mean value x' */
+    arm_fill_f32(mean,  wire2, blockSize);
+    
+    /* wire3 contains (x-x') */     
+    arm_sub_f32(testInput_f32, wire2, wire3, blockSize);
+    
+    /* wire2 contains (x-x') */             
+    arm_copy_f32(wire3, wire2, blockSize);
+    
+    /* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */
+    arm_dot_prod_f32(wire2, wire3, blockSize, &variance); 
+
+    /* Calculation of 1/blockSize */
+    oneByBlockSize = 1.0 / (blockSize - 1);
+
+    /* Calculation of variance */       
+    arm_mult_f32(&variance, &oneByBlockSize, &variance, 1);
+    
+    /* absolute value of difference between ref and test */
+    diff = fabsf(refVarianceOut - variance);
+    
+    /* Comparison of variance value with reference */
+    if(diff > DELTA)
+    {
+        status = ARM_MATH_TEST_FAILURE;
+    }
+        
+    if( status != ARM_MATH_SUCCESS)
+    {
+      while(1);
+    }
+}
+
+
 

+
+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
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+
+
+
+
+CMSIS DSP Software Library: Alphabetical List
+
+
+
+
+
+
+
+
+
+

+  

+
Data Structure Index
  

+

+

+
A

+
+
  A  

+		arm_cfft_radix4_instance_q15   arm_fir_instance_q7   arm_fir_sparse_instance_q7   arm_lms_norm_instance_q31   
arm_bilinear_interp_instance_f32   arm_cfft_radix4_instance_q31   arm_fir_interpolate_instance_f32   arm_iir_lattice_instance_f32   arm_matrix_instance_f32   
arm_bilinear_interp_instance_q15   arm_dct4_instance_f32   arm_fir_interpolate_instance_q15   arm_iir_lattice_instance_q15   arm_matrix_instance_q15   
arm_bilinear_interp_instance_q31   arm_dct4_instance_q15   arm_fir_interpolate_instance_q31   arm_iir_lattice_instance_q31   arm_matrix_instance_q31   
arm_bilinear_interp_instance_q7   arm_dct4_instance_q31   arm_fir_lattice_instance_f32   arm_linear_interp_instance_f32   arm_pid_instance_f32   
arm_biquad_cas_df1_32x64_ins_q31   arm_fir_decimate_instance_f32   arm_fir_lattice_instance_q15   arm_lms_instance_f32   arm_pid_instance_q15   
arm_biquad_cascade_df2T_instance_f32   arm_fir_decimate_instance_q15   arm_fir_lattice_instance_q31   arm_lms_instance_q15   arm_pid_instance_q31   
arm_biquad_casd_df1_inst_f32   arm_fir_decimate_instance_q31   arm_fir_sparse_instance_f32   arm_lms_instance_q31   arm_rfft_instance_f32   
arm_biquad_casd_df1_inst_q15   arm_fir_instance_f32   arm_fir_sparse_instance_q15   arm_lms_norm_instance_f32   arm_rfft_instance_q15   
arm_biquad_casd_df1_inst_q31   arm_fir_instance_q15   arm_fir_sparse_instance_q31   arm_lms_norm_instance_q15   arm_rfft_instance_q31   
arm_cfft_radix4_instance_f32   arm_fir_instance_q31   
A

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
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+}
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+	float:left;
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+	background-repeat:no-repeat;
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+}
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/doxygen.png b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/doxygen.png
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index 0000000..635ed52
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/examples.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/examples.html
new file mode 100644
index 0000000..0acc936
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/examples.html
@@ -0,0 +1,91 @@
+
+
+
+
+CMSIS DSP Software Library: Examples
+
+
+
+
+
+
+
+
+
+

+  

+
Examples
  

+

+

+Here is a list of all examples:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/files.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/files.html
new file mode 100644
index 0000000..8797c45
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/files.html
@@ -0,0 +1,327 @@
+
+
+
+
+CMSIS DSP Software Library: File Index
+
+
+
+
+
+
+
+
+
+

+  

+
File List
  

+

+

+Here is a list of all files with brief descriptions:
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
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arm_abs_f32.c [code]
arm_abs_q15.c [code]
arm_abs_q31.c [code]
arm_abs_q7.c [code]
arm_add_f32.c [code]
arm_add_q15.c [code]
arm_add_q31.c [code]
arm_add_q7.c [code]
arm_biquad_cascade_df1_32x64_init_q31.c [code]
arm_biquad_cascade_df1_32x64_q31.c [code]
arm_biquad_cascade_df1_f32.c [code]
arm_biquad_cascade_df1_fast_q15.c [code]
arm_biquad_cascade_df1_fast_q31.c [code]
arm_biquad_cascade_df1_init_f32.c [code]
arm_biquad_cascade_df1_init_q15.c [code]
arm_biquad_cascade_df1_init_q31.c [code]
arm_biquad_cascade_df1_q15.c [code]
arm_biquad_cascade_df1_q31.c [code]
arm_biquad_cascade_df2T_f32.c [code]
arm_biquad_cascade_df2T_init_f32.c [code]
arm_cfft_radix4_f32.c [code]
arm_cfft_radix4_init_f32.c [code]
arm_cfft_radix4_init_q15.c [code]
arm_cfft_radix4_init_q31.c [code]
arm_cfft_radix4_q15.c [code]
arm_cfft_radix4_q31.c [code]
arm_class_marks_example_f32.c [code]
arm_cmplx_conj_f32.c [code]
arm_cmplx_conj_q15.c [code]
arm_cmplx_conj_q31.c [code]
arm_cmplx_dot_prod_f32.c [code]
arm_cmplx_dot_prod_q15.c [code]
arm_cmplx_dot_prod_q31.c [code]
arm_cmplx_mag_f32.c [code]
arm_cmplx_mag_q15.c [code]
arm_cmplx_mag_q31.c [code]
arm_cmplx_mag_squared_f32.c [code]
arm_cmplx_mag_squared_q15.c [code]
arm_cmplx_mag_squared_q31.c [code]
arm_cmplx_mult_cmplx_f32.c [code]
arm_cmplx_mult_cmplx_q15.c [code]
arm_cmplx_mult_cmplx_q31.c [code]
arm_cmplx_mult_real_f32.c [code]
arm_cmplx_mult_real_q15.c [code]
arm_cmplx_mult_real_q31.c [code]
arm_common_tables.c [code]
arm_conv_f32.c [code]
arm_conv_fast_q15.c [code]
arm_conv_fast_q31.c [code]
arm_conv_partial_f32.c [code]
arm_conv_partial_fast_q15.c [code]
arm_conv_partial_fast_q31.c [code]
arm_conv_partial_q15.c [code]
arm_conv_partial_q31.c [code]
arm_conv_partial_q7.c [code]
arm_conv_q15.c [code]
arm_conv_q31.c [code]
arm_conv_q7.c [code]
arm_convolution_example_f32.c [code]
arm_copy_f32.c [code]
arm_copy_q15.c [code]
arm_copy_q31.c [code]
arm_copy_q7.c [code]
arm_correlate_f32.c [code]
arm_correlate_fast_q15.c [code]
arm_correlate_fast_q31.c [code]
arm_correlate_q15.c [code]
arm_correlate_q31.c [code]
arm_correlate_q7.c [code]
arm_cos_f32.c [code]
arm_cos_q15.c [code]
arm_cos_q31.c [code]
arm_dct4_f32.c [code]
arm_dct4_init_f32.c [code]
arm_dct4_init_q15.c [code]
arm_dct4_init_q31.c [code]
arm_dct4_q15.c [code]
arm_dct4_q31.c [code]
arm_dot_prod_f32.c [code]
arm_dot_prod_q15.c [code]
arm_dot_prod_q31.c [code]
arm_dot_prod_q7.c [code]
arm_dotproduct_example_f32.c [code]
arm_fft_bin_example_f32.c [code]
arm_fill_f32.c [code]
arm_fill_q15.c [code]
arm_fill_q31.c [code]
arm_fill_q7.c [code]
arm_fir_decimate_f32.c [code]
arm_fir_decimate_fast_q15.c [code]
arm_fir_decimate_fast_q31.c [code]
arm_fir_decimate_init_f32.c [code]
arm_fir_decimate_init_q15.c [code]
arm_fir_decimate_init_q31.c [code]
arm_fir_decimate_q15.c [code]
arm_fir_decimate_q31.c [code]
arm_fir_example_f32.c [code]
arm_fir_f32.c [code]
arm_fir_fast_q15.c [code]
arm_fir_fast_q31.c [code]
arm_fir_init_f32.c [code]
arm_fir_init_q15.c [code]
arm_fir_init_q31.c [code]
arm_fir_init_q7.c [code]
arm_fir_interpolate_f32.c [code]
arm_fir_interpolate_init_f32.c [code]
arm_fir_interpolate_init_q15.c [code]
arm_fir_interpolate_init_q31.c [code]
arm_fir_interpolate_q15.c [code]
arm_fir_interpolate_q31.c [code]
arm_fir_lattice_f32.c [code]
arm_fir_lattice_init_f32.c [code]
arm_fir_lattice_init_q15.c [code]
arm_fir_lattice_init_q31.c [code]
arm_fir_lattice_q15.c [code]
arm_fir_lattice_q31.c [code]
arm_fir_q15.c [code]
arm_fir_q31.c [code]
arm_fir_q7.c [code]
arm_fir_sparse_f32.c [code]
arm_fir_sparse_init_f32.c [code]
arm_fir_sparse_init_q15.c [code]
arm_fir_sparse_init_q31.c [code]
arm_fir_sparse_init_q7.c [code]
arm_fir_sparse_q15.c [code]
arm_fir_sparse_q31.c [code]
arm_fir_sparse_q7.c [code]
arm_float_to_q15.c [code]
arm_float_to_q31.c [code]
arm_float_to_q7.c [code]
arm_graphic_equalizer_example_q31.c [code]
arm_iir_lattice_f32.c [code]
arm_iir_lattice_init_f32.c [code]
arm_iir_lattice_init_q15.c [code]
arm_iir_lattice_init_q31.c [code]
arm_iir_lattice_q15.c [code]
arm_iir_lattice_q31.c [code]
arm_linear_interp_example_f32.c [code]
arm_lms_f32.c [code]
arm_lms_init_f32.c [code]
arm_lms_init_q15.c [code]
arm_lms_init_q31.c [code]
arm_lms_norm_f32.c [code]
arm_lms_norm_init_f32.c [code]
arm_lms_norm_init_q15.c [code]
arm_lms_norm_init_q31.c [code]
arm_lms_norm_q15.c [code]
arm_lms_norm_q31.c [code]
arm_lms_q15.c [code]
arm_lms_q31.c [code]
arm_mat_add_f32.c [code]
arm_mat_add_q15.c [code]
arm_mat_add_q31.c [code]
arm_mat_init_f32.c [code]
arm_mat_init_q15.c [code]
arm_mat_init_q31.c [code]
arm_mat_inverse_f32.c [code]
arm_mat_mult_f32.c [code]
arm_mat_mult_fast_q15.c [code]
arm_mat_mult_fast_q31.c [code]
arm_mat_mult_q15.c [code]
arm_mat_mult_q31.c [code]
arm_mat_scale_f32.c [code]
arm_mat_scale_q15.c [code]
arm_mat_scale_q31.c [code]
arm_mat_sub_f32.c [code]
arm_mat_sub_q15.c [code]
arm_mat_sub_q31.c [code]
arm_mat_trans_f32.c [code]
arm_mat_trans_q15.c [code]
arm_mat_trans_q31.c [code]
arm_math.h [code]
arm_matrix_example_f32.c [code]
arm_max_f32.c [code]
arm_max_q15.c [code]
arm_max_q31.c [code]
arm_max_q7.c [code]
arm_mean_f32.c [code]
arm_mean_q15.c [code]
arm_mean_q31.c [code]
arm_mean_q7.c [code]
arm_min_f32.c [code]
arm_min_q15.c [code]
arm_min_q31.c [code]
arm_min_q7.c [code]
arm_mult_f32.c [code]
arm_mult_q15.c [code]
arm_mult_q31.c [code]
arm_mult_q7.c [code]
arm_negate_f32.c [code]
arm_negate_q15.c [code]
arm_negate_q31.c [code]
arm_negate_q7.c [code]
arm_offset_f32.c [code]
arm_offset_q15.c [code]
arm_offset_q31.c [code]
arm_offset_q7.c [code]
arm_pid_init_f32.c [code]
arm_pid_init_q15.c [code]
arm_pid_init_q31.c [code]
arm_pid_reset_f32.c [code]
arm_pid_reset_q15.c [code]
arm_pid_reset_q31.c [code]
arm_power_f32.c [code]
arm_power_q15.c [code]
arm_power_q31.c [code]
arm_power_q7.c [code]
arm_q15_to_float.c [code]
arm_q15_to_q31.c [code]
arm_q15_to_q7.c [code]
arm_q31_to_float.c [code]
arm_q31_to_q15.c [code]
arm_q31_to_q7.c [code]
arm_q7_to_float.c [code]
arm_q7_to_q15.c [code]
arm_q7_to_q31.c [code]
arm_rfft_f32.c [code]
arm_rfft_init_f32.c [code]
arm_rfft_init_q15.c [code]
arm_rfft_init_q31.c [code]
arm_rfft_q15.c [code]
arm_rfft_q31.c [code]
arm_rms_f32.c [code]
arm_rms_q15.c [code]
arm_rms_q31.c [code]
arm_scale_f32.c [code]
arm_scale_q15.c [code]
arm_scale_q31.c [code]
arm_scale_q7.c [code]
arm_shift_q15.c [code]
arm_shift_q31.c [code]
arm_shift_q7.c [code]
arm_signal_converge_example_f32.c [code]
arm_sin_cos_example_f32.c [code]
arm_sin_cos_f32.c [code]
arm_sin_cos_q31.c [code]
arm_sin_f32.c [code]
arm_sin_q15.c [code]
arm_sin_q31.c [code]
arm_sqrt_q15.c [code]
arm_sqrt_q31.c [code]
arm_std_f32.c [code]
arm_std_q15.c [code]
arm_std_q31.c [code]
arm_sub_f32.c [code]
arm_sub_q15.c [code]
arm_sub_q31.c [code]
arm_sub_q7.c [code]
arm_var_f32.c [code]
arm_var_q15.c [code]
arm_var_q31.c [code]
arm_variance_example_f32.c [code]

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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions.html
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+CMSIS DSP Software Library: Data Fields
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_0x6e.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_0x6e.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_0x6f.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_0x6f.html
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
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+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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- p -

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+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
+
+
- r -

+

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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields
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+Here is a list of all struct and union fields with links to the structures/unions they belong to:
+
+
- s -

+

+
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+
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+

+
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+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+
+
+CMSIS DSP Software Library: Data Fields
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+
+
+
+
+
+
+
+

+Here is a list of all struct and union fields with links to the structures/unions they belong to:
+
+
- t -

+

+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_0x78.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_0x78.html
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+CMSIS DSP Software Library: Data Fields
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+
+
+
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+
+

+Here is a list of all struct and union fields with links to the structures/unions they belong to:
+
+
- x -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars.html
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+CMSIS DSP Software Library: Data Fields - Variables
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+ 
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- a -

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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x62.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x62.html
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+CMSIS DSP Software Library: Data Fields - Variables
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+

+ 
+
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- b -

+

+
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+

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+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x65.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x65.html
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--- /dev/null
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+CMSIS DSP Software Library: Data Fields - Variables
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+ 
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- e -

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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x66.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x66.html
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--- /dev/null
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+CMSIS DSP Software Library: Data Fields - Variables
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+

+ 
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- f -

+

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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x69.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x69.html
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+CMSIS DSP Software Library: Data Fields - Variables
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+ 
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- i -

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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+CMSIS DSP Software Library: Data Fields - Variables
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+ 
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- k -

+

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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6c.html
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--- /dev/null
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+CMSIS DSP Software Library: Data Fields - Variables
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+ 
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- l -

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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6d.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6d.html
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+CMSIS DSP Software Library: Data Fields - Variables
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+
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+

+ 
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- m -

+

+
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Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6e.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6e.html
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+CMSIS DSP Software Library: Data Fields - Variables
+
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+
+
+
+
+
+
+
+

+ 
+
+
- n -

+

+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6f.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6f.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x6f.html
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+CMSIS DSP Software Library: Data Fields - Variables
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+
+
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+
+
+
+
+

+ 
+
+
- o -

+

+
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+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x70.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x70.html
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index 0000000..8bbdedf
--- /dev/null
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+CMSIS DSP Software Library: Data Fields - Variables
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+
+
+
+
+
+

+ 
+
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- p -

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+
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+
+

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+

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+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x72.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x72.html
new file mode 100644
index 0000000..6006078
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x72.html
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+CMSIS DSP Software Library: Data Fields - Variables
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+
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+
+
+
+
+
+

+ 
+
+
- r -

+

+
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+
+

+
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+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x73.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x73.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x73.html
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+CMSIS DSP Software Library: Data Fields - Variables
+
+
+
+
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+
+
+
+
+

+ 
+
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- s -

+

+
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+

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+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
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+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x74.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x74.html
new file mode 100644
index 0000000..5dad55a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x74.html
@@ -0,0 +1,108 @@
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+
+
+
+CMSIS DSP Software Library: Data Fields - Variables
+
+
+
+
+
+
+
+
+
+

+ 
+
+
- t -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x78.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x78.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/functions_vars_0x78.html
@@ -0,0 +1,109 @@
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+
+
+CMSIS DSP Software Library: Data Fields - Variables
+
+
+
+
+
+
+
+
+
+

+ 
+
+
- x -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals.html
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+
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+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- _ -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x61.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x61.html
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+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- a -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x62.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x62.html
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+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x62.html
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+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- b -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x63.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x63.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x63.html
@@ -0,0 +1,169 @@
+
+
+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- c -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x64.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x64.html
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+
+
+CMSIS DSP Software Library: Data Fields
+
+
+
+
+
+
+
+
+
+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- d -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x65.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x65.html
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+CMSIS DSP Software Library: Data Fields
+
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+
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+
+
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+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- e -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x66.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/globals_0x66.html
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+
+CMSIS DSP Software Library: Data Fields
+
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+
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+
+
+
+
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+

+Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+
+
- f -

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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- x -

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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
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+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___basic_abs.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___basic_abs.html
new file mode 100644
index 0000000..f23be47
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___basic_abs.html
@@ -0,0 +1,277 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Absolute Value
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Absolute Value

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_abs_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_abs_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_abs_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_abs_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Computes the absolute value of a vector on an element-by-element basis.

+
   
+     pDst[n] = abs(pSrcA[n]),   0 <= n < blockSize.   
+ 
The operation can be done in-place by setting the input and output pointers to the same buffer. There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_abs_f32 (float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Floating-point vector absolute value. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 66 of file arm_abs_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_abs_q31 (q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q31 vector absolute value. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. 

+
+
Definition at line 58 of file arm_abs_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_abs_q15 (q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q15 vector absolute value. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. 

+
+
Definition at line 57 of file arm_abs_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_abs_q7 (q7_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q7 vector absolute value. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input buffer 
[out]*pDstpoints to the output buffer 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. 

+
+
Definition at line 57 of file arm_abs_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___basic_add.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___basic_add.html
new file mode 100644
index 0000000..9d5f8d1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___basic_add.html
@@ -0,0 +1,305 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Addition
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Addition

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_add_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
void arm_add_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
void arm_add_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
void arm_add_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Element-by-element addition of two vectors.

+
   
+     pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.   
+ 
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_add_f32 (float32_t *  pSrcA, 
float32_t *  pSrcB, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Floating-point vector addition. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_dotproduct_example_f32.c, and arm_sin_cos_example_f32.c.

+

+
Definition at line 65 of file arm_add_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_add_q31 (q31_t *  pSrcA, 
q31_t *  pSrcB, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q31 vector addition. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 59 of file arm_add_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_add_q15 (q15_t *  pSrcA, 
q15_t *  pSrcB, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q15 vector addition. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 58 of file arm_add_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_add_q7 (q7_t *  pSrcA, 
q7_t *  pSrcB, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q7 vector addition. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 

+
+
Definition at line 58 of file arm_add_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___basic_mult.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___basic_mult.html
new file mode 100644
index 0000000..f51ae33
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___basic_mult.html
@@ -0,0 +1,305 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Multiplication
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Multiplication

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_mult_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
void arm_mult_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
void arm_mult_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
void arm_mult_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Element-by-element multiplication of two vectors.

+
   
+     pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.   
+ 
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mult_f32 (float32_t *  pSrcA, 
float32_t *  pSrcB, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Floating-point vector multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_dotproduct_example_f32.c, arm_sin_cos_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 68 of file arm_mult_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mult_q31 (q31_t *  pSrcA, 
q31_t *  pSrcB, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q31 vector multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 61 of file arm_mult_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mult_q15 (q15_t *  pSrcA, 
q15_t *  pSrcB, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q15 vector multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 62 of file arm_mult_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_mult_q7 (q7_t *  pSrcA, 
q7_t *  pSrcB, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q7 vector multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 

+
+
Definition at line 64 of file arm_mult_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___basic_sub.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___basic_sub.html
new file mode 100644
index 0000000..34d69aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___basic_sub.html
@@ -0,0 +1,305 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Subtraction
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Subtraction

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_sub_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize)
void arm_sub_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize)
void arm_sub_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize)
void arm_sub_q7 (q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Element-by-element subtraction of two vectors.

+
   
+     pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.   
+ 
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sub_f32 (float32_t *  pSrcA, 
float32_t *  pSrcB, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Floating-point vector subtraction. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 66 of file arm_sub_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sub_q31 (q31_t *  pSrcA, 
q31_t *  pSrcB, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q31 vector subtraction. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 58 of file arm_sub_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sub_q15 (q15_t *  pSrcA, 
q15_t *  pSrcB, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q15 vector subtraction. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 58 of file arm_sub_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_sub_q7 (q7_t *  pSrcA, 
q7_t *  pSrcB, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Q7 vector subtraction. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 

+
+
Definition at line 58 of file arm_sub_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___bilinear_interpolate.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___bilinear_interpolate.html
new file mode 100644
index 0000000..110dac1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___bilinear_interpolate.html
@@ -0,0 +1,288 @@
+
+
+
+
+CMSIS DSP Software Library: Bilinear Interpolation
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Bilinear Interpolation

+
+[Interpolation Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
static __INLINE float32_t arm_bilinear_interp_f32 (const arm_bilinear_interp_instance_f32 *S, float32_t X, float32_t Y)
static __INLINE q31_t arm_bilinear_interp_q31 (arm_bilinear_interp_instance_q31 *S, q31_t X, q31_t Y)
static __INLINE q15_t arm_bilinear_interp_q15 (arm_bilinear_interp_instance_q15 *S, q31_t X, q31_t Y)
static __INLINE q7_t arm_bilinear_interp_q7 (arm_bilinear_interp_instance_q7 *S, q31_t X, q31_t Y)

+
Detailed Description

+
Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. The underlying function f(x, y) is sampled on a regular grid and the interpolation process determines values between the grid points. Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. Bilinear interpolation is often used in image processing to rescale images. The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.

+
Algorithm 

+
The instance structure used by the bilinear interpolation functions describes a two dimensional data table. For floating-point, the instance structure is defined as: 
+   typedef struct
+   {
+     uint16_t numRows;
+     uint16_t numCols;
+     float32_t *pData;
+ } arm_bilinear_interp_instance_f32;
+ 

+
where numRows specifies the number of rows in the table; numCols specifies the number of columns in the table; and pData points to an array of size numRows*numCols values. The data table pTable is organized in row order and the supplied data values fall on integer indexes. That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.

+
Let (x, y) specify the desired interpolation point. Then define: 
+     XF = floor(x)
+     YF = floor(y)
+ 
 

+
The interpolated output point is computed as: 
+  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ 
 Note that the coordinates (x, y) contain integer and fractional components. The integer components specify which portion of the table to use while the fractional components control the interpolation processor.

+
if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. 

+
Function Documentation

+
+

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static __INLINE float32_t arm_bilinear_interp_f32 (const arm_bilinear_interp_instance_f32 *  S, 
float32_t  X, 
float32_t  Y 
) [static]

+

+

+
+
Floating-point bilinear interpolation. 

+
Parameters:

+  
+    
+    
+    
+  
[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate. 
[in]Yinterpolation coordinate. 

+  

+

+
Returns:
out interpolated value. 

+
+
Definition at line 6739 of file arm_math.h.

+
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static __INLINE q31_t arm_bilinear_interp_q31 (arm_bilinear_interp_instance_q31 *  S, 
q31_t  X, 
q31_t  Y 
) [static]

+

+

+
+
Q31 bilinear interpolation. 

+
Parameters:

+  
+    
+    
+    
+  
[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate in 12.20 format. 
[in]Yinterpolation coordinate in 12.20 format. 

+  

+

+
Returns:
out interpolated value. 

+
+
Definition at line 6806 of file arm_math.h.

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static __INLINE q15_t arm_bilinear_interp_q15 (arm_bilinear_interp_instance_q15 *  S, 
q31_t  X, 
q31_t  Y 
) [static]

+

+

+
+
Q15 bilinear interpolation. 

+
Parameters:

+  
+    
+    
+    
+  
[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate in 12.20 format. 
[in]Yinterpolation coordinate in 12.20 format. 

+  

+

+
Returns:
out interpolated value. 

+
+
Definition at line 6882 of file arm_math.h.

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static __INLINE q7_t arm_bilinear_interp_q7 (arm_bilinear_interp_instance_q7 *  S, 
q31_t  X, 
q31_t  Y 
) [static]

+

+

+
+
Q7 bilinear interpolation. 

+
Parameters:

+  
+    
+    
+    
+  
[in,out]*Spoints to an instance of the interpolation structure. 
[in]Xinterpolation coordinate in 12.20 format. 
[in]Yinterpolation coordinate in 12.20 format. 

+  

+

+
Returns:
out interpolated value. 

+
+
Definition at line 6962 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f1.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f1.html
new file mode 100644
index 0000000..30166fa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f1.html
@@ -0,0 +1,605 @@
+
+
+
+
+CMSIS DSP Software Library: Biquad Cascade IIR Filters Using Direct Form I Structure
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Biquad Cascade IIR Filters Using Direct Form I Structure

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, q31_t *pCoeffs, q31_t *pState, int8_t postShift)
void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, q15_t *pCoeffs, q15_t *pState, int8_t postShift)
void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+
Detailed Description

+
This set of functions implements arbitrary order recursive (IIR) filters. The filters are implemented as a cascade of second order Biquad sections. The functions support Q15, Q31 and floating-point data types. Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.

+
The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc points to the array of input data and pDst points to the array of output data. Both arrays contain blockSize values.

+
Algorithm 
Each Biquad stage implements a second order filter using the difference equation: 
   
+     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+ 
 A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. 

+Biquad.gif
+
Single Biquad filter stage

+ Coefficients b0, b1 and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients. Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. Pay careful attention to the sign of the feedback coefficients. Some design tools use the difference equation 
   
+     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]   
+ 
 In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.

+
Higher order filters are realized as a cascade of second order sections. numStages refers to the number of second order stages used. For example, an 8th order filter would be realized with numStages=4 second order stages. 

+BiquadCascade.gif
+
8th order filter using a cascade of Biquad stages

+ A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).

+
The pState points to state variables array. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
   
+     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ 

+
The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed, the coefficients are untouched.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 3 supported data types.

+
Init Functions 
There is also an associated initialization function for each data type. The initialization function performs following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 3 different data type filter instance structures 
   
+     arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};   
+     arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};   
+     arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};   
+ 
 where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer; postShift shift to be applied.

+
Fixed-Point Behavior 
Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions. Following issues must be considered:
    
+
  • Scaling of coefficients
    • 
+
  • Filter gain
    • 
+
  • Overflow and saturation
    • 
+

+

+
Scaling of coefficients:  Filter coefficients are represented as fractional values and coefficients are restricted to lie in the range [-1 +1). The fixed-point functions have an additional scaling parameter postShift which allow the filter coefficients to exceed the range [+1 -1). At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. 

+BiquadPostshift.gif
+
Fixed-point Biquad with shift by postShift bits after accumulator

+ This essentially scales the filter coefficients by 2^postShift. For example, to realize the coefficients 
   
+    {1.5, -0.8, 1.2, 1.6, -0.9}   
+ 
 set the pCoeffs array to: 
   
+    {0.75, -0.4, 0.6, 0.8, -0.45}   
+ 
 and set postShift=1

+
Filter gain:  The frequency response of a Biquad filter is a function of its coefficients. It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies. This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter. To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.

+
Overflow and saturation:  For Q15 and Q31 versions, it is described separately as part of the function specific documentation below. 

+
Function Documentation

+
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void arm_biquad_cascade_df1_init_f32 (arm_biquad_casd_df1_inst_f32 *  S, 
uint8_t  numStages, 
float32_t *  pCoeffs, 
float32_t *  pState 
)

+

+

+
+
Initialization function for the floating-point Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point Biquad cascade structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients array. 
[in]*pStatepoints to the state array. 

+  

+

+
Returns:
none

+
Coefficient and State Ordering:

+
The coefficients are stored in the array pCoeffs in the following order: 
   
+     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ 

+
where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.

+
The pState is a pointer to state array. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
   
+     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ 
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
+
Definition at line 83 of file arm_biquad_cascade_df1_init_f32.c.

+
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void arm_biquad_cascade_df1_f32 (const arm_biquad_casd_df1_inst_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none. 

+
+
Definition at line 171 of file arm_biquad_cascade_df1_f32.c.

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void arm_biquad_cascade_df1_init_q31 (arm_biquad_casd_df1_inst_q31 *  S, 
uint8_t  numStages, 
q31_t *  pCoeffs, 
q31_t *  pState, 
int8_t  postShift 
)

+

+

+
+
Initialization function for the Q31 Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 Biquad cascade structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]postShiftShift to be applied after the accumulator. Varies according to the coefficients format 

+  

+

+
Returns:
none

+
Coefficient and State Ordering:

+
The coefficients are stored in the array pCoeffs in the following order: 
   
+     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ 
 where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.

+
The pState points to state variables array. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
   
+     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ 
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 81 of file arm_biquad_cascade_df1_init_q31.c.

+
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void arm_biquad_cascade_df1_q31 (const arm_biquad_casd_df1_inst_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to 1.31 format by discarding the low 32 bits.

+
Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 69 of file arm_biquad_cascade_df1_q31.c.

+
+

+

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void arm_biquad_cascade_df1_fast_q31 (const arm_biquad_casd_df1_inst_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are added to a 2.30 accumulator. Finally, the accumulator is saturated and converted to a 1.31 result. The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function arm_biquad_cascade_df1_init_q31() to initialize filter structure.

+
Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure. Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure. 

+
+
Definition at line 70 of file arm_biquad_cascade_df1_fast_q31.c.

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void arm_biquad_cascade_df1_init_q15 (arm_biquad_casd_df1_inst_q15 *  S, 
uint8_t  numStages, 
q15_t *  pCoeffs, 
q15_t *  pState, 
int8_t  postShift 
)

+

+

+
+
Initialization function for the Q15 Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 Biquad cascade structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]postShiftShift to be applied to the accumulator result. Varies according to the coefficients format 

+  

+

+
Returns:
none

+
Coefficient and State Ordering:

+
The coefficients are stored in the array pCoeffs in the following order: 
   
+     {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}   
+ 
 where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 6*numStages values. The zero coefficient between b1 and b2 facilities use of 16-bit SIMD instructions on the Cortex-M4.

+
The state variables are stored in the array pState. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the pState array as: 
   
+     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ 
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
+
Definition at line 81 of file arm_biquad_cascade_df1_init_q15.c.

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void arm_biquad_cascade_df1_q15 (const arm_biquad_casd_df1_inst_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the location where the output result is written. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits. Finally, the result is saturated to 1.15 format.

+
Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 70 of file arm_biquad_cascade_df1_q15.c.

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void arm_biquad_cascade_df1_fast_q15 (const arm_biquad_casd_df1_inst_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 Biquad cascade structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.

+
Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure. 

+
+
Definition at line 69 of file arm_biquad_cascade_df1_fast_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f1__32x64.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f1__32x64.html
new file mode 100644
index 0000000..6586fcd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f1__32x64.html
@@ -0,0 +1,243 @@
+
+
+
+
+CMSIS DSP Software Library: High Precision Q31 Biquad Cascade Filter
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
High Precision Q31 Biquad Cascade Filter

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, q31_t *pCoeffs, q63_t *pState, uint8_t postShift)
void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)

+
Detailed Description

+
This function implements a high precision Biquad cascade filter which operates on Q31 data values. The filter coefficients are in 1.31 format and the state variables are in 1.63 format. The double precision state variables reduce quantization noise in the filter and provide a cleaner output. These filters are particularly useful when implementing filters in which the singularities are close to the unit circle. This is common for low pass or high pass filters with very low cutoff frequencies.

+
The function operates on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst points to input and output arrays containing blockSize Q31 values.

+
Algorithm 
Each Biquad stage implements a second order filter using the difference equation: 
   
+     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+ 
 A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. 

+Biquad.gif
+
Single Biquad filter stage

+ Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients. Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. Pay careful attention to the sign of the feedback coefficients. Some design tools use the difference equation 
   
+     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]   
+ 
 In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.

+
Higher order filters are realized as a cascade of second order sections. numStages refers to the number of second order stages used. For example, an 8th order filter would be realized with numStages=4 second order stages. 

+BiquadCascade.gif
+
8th order filter using a cascade of Biquad stages

+ A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).

+
The pState points to state variables array . Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision. The state variables are arranged in the array as: 
   
+     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ 

+
The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values of data in 1.63 format. The state variables are updated after each block of data is processed; the coefficients are untouched.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.

+
Init Function 
There is also an associated initialization function which performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer. 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. For example, to statically initialize the filter instance structure use 
   
+     arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};   
+ 
 where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below. 

+
Fixed-Point Behavior 
Care must be taken while using Biquad Cascade 32x64 filter function. Following issues must be considered:
    
+
  • Scaling of coefficients
    • 
+
  • Filter gain
    • 
+
  • Overflow and saturation
    • 
+

+

+
Filter coefficients are represented as fractional values and restricted to lie in the range [-1 +1). The processing function has an additional scaling parameter postShift which allows the filter coefficients to exceed the range [+1 -1). At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. 

+BiquadPostshift.gif
+
Fixed-point Biquad with shift by postShift bits after accumulator

+ This essentially scales the filter coefficients by 2^postShift. For example, to realize the coefficients 
   
+    {1.5, -0.8, 1.2, 1.6, -0.9}   
+ 
 set the Coefficient array to: 
   
+    {0.75, -0.4, 0.6, 0.8, -0.45}   
+ 
 and set postShift=1

+
The second thing to keep in mind is the gain through the filter. The frequency response of a Biquad filter is a function of its coefficients. It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies. This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter. To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.

+
The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version. This is described in the function specific documentation below. 

+
Function Documentation

+
+

+

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void arm_biquad_cas_df1_32x64_init_q31 (arm_biquad_cas_df1_32x64_ins_q31 *  S, 
uint8_t  numStages, 
q31_t *  pCoeffs, 
q63_t *  pState, 
uint8_t  postShift 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the high precision Q31 Biquad cascade filter structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]postShiftShift to be applied after the accumulator. Varies according to the coefficients format. 

+  

+

+
Returns:
none

+
Coefficient and State Ordering:

+
The coefficients are stored in the array pCoeffs in the following order: 
   
+     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ 
 where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.

+
The pState points to state variables array and size of each state variable is 1.63 format. Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. The state variables are arranged in the state array as: 
   
+     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ 
 The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. The state array has a total length of 4*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 77 of file arm_biquad_cascade_df1_32x64_init_q31.c.

+
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void arm_biquad_cas_df1_32x64_q31 (const arm_biquad_cas_df1_32x64_ins_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the high precision Q31 Biquad cascade filter. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to 1.31 format by discarding the low 32 bits.

+
Two related functions are provided in the CMSIS DSP library. arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator. arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 176 of file arm_biquad_cascade_df1_32x64_q31.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f2_t.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f2_t.html
new file mode 100644
index 0000000..f95285b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___biquad_cascade_d_f2_t.html
@@ -0,0 +1,221 @@
+
+
+
+
+CMSIS DSP Software Library: Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+

+Functions
void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, float32_t *pCoeffs, float32_t *pState)
void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)

+
Detailed Description

+
This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure. The filters are implemented as a cascade of second order Biquad sections. These functions provide a slight memory savings as compared to the direct form I Biquad filter functions. Only floating-point data is supported.

+
This function operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc points to the array of input data and pDst points to the array of output data. Both arrays contain blockSize values.

+
Algorithm 
Each Biquad stage implements a second order filter using the difference equation: 
   
+    y[n] = b0 * x[n] + d1   
+    d1 = b1 * x[n] + a1 * y[n] + d2   
+    d2 = b2 * x[n] + a2 * y[n]   
+ 
 where d1 and d2 represent the two state values.

+
A Biquad filter using a transposed Direct Form II structure is shown below. 

+BiquadDF2Transposed.gif
+
Single transposed Direct Form II Biquad

+ Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients. Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. Pay careful attention to the sign of the feedback coefficients. Some design tools flip the sign of the feedback coefficients: 
   
+    y[n] = b0 * x[n] + d1;   
+    d1 = b1 * x[n] - a1 * y[n] + d2;   
+    d2 = b2 * x[n] - a2 * y[n];   
+ 
 In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.

+
Higher order filters are realized as a cascade of second order sections. numStages refers to the number of second order stages used. For example, an 8th order filter would be realized with numStages=4 second order stages. A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).

+
pState points to the state variable array. Each Biquad stage has 2 state variables d1 and d2. The state variables are arranged in the pState array as: 
   
+     {d11, d12, d21, d22, ...}   
+ 
 where d1x refers to the state variables for the first Biquad and d2x refers to the state variables for the second Biquad. The state array has a total length of 2*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched.

+
The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II. The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types. That is why the Direct Form I structure supports Q15 and Q31 data types. The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2. Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad. The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.

+
Init Functions 
There is also an associated initialization function. The initialization function performs following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. For example, to statically initialize the instance structure use 
   
+     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};   
+ 
 where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer. pCoeffs is the address of the coefficient buffer; 

+
Function Documentation

+
+

+

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void arm_biquad_cascade_df2T_init_f32 (arm_biquad_cascade_df2T_instance_f32 *  S, 
uint8_t  numStages, 
float32_t *  pCoeffs, 
float32_t *  pState 
)

+

+

+
+
Initialization function for the floating-point transposed direct form II Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the filter data structure. 
[in]numStagesnumber of 2nd order stages in the filter. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 

+  

+

+
Returns:
none

+
Coefficient and State Ordering: 

+
The coefficients are stored in the array pCoeffs in the following order: 
   
+     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ 

+
where b1x and a1x are the coefficients for the first stage, b2x and a2x are the coefficients for the second stage, and so on. The pCoeffs array contains a total of 5*numStages values.

+
The pState is a pointer to state array. Each Biquad stage has 2 state variables d1, and d2. The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. The state array has a total length of 2*numStages values. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
+
Definition at line 73 of file arm_biquad_cascade_df2T_init_f32.c.

+
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void arm_biquad_cascade_df2T_f32 (const arm_biquad_cascade_df2T_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point transposed direct form II Biquad cascade filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the filter data structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 143 of file arm_biquad_cascade_df2T_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___c_f_f_t___c_i_f_f_t.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___c_f_f_t___c_i_f_f_t.html
new file mode 100644
index 0000000..eb144c9
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+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___c_f_f_t___c_i_f_f_t.html
@@ -0,0 +1,570 @@
+
+
+
+
+CMSIS DSP Software Library: Complex FFT Functions
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
Complex FFT Functions

+
+[Transform Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc)
arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc)
arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag)
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc)

+Variables
static const float32_t twiddleCoef [2048]
static const q31_t twiddleCoefQ31 [2048]
static const q15_t twiddleCoefQ15 [2048]
const uint16_t armBitRevTable [256]

+
Detailed Description

+
Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT). Computational complexity of CFFT reduces drastically when compared to DFT. 

+
This set of functions implements CFFT/CIFFT for Q15, Q31, and floating-point data types. The functions operates on in-place buffer which uses same buffer for input and output. Complex input is stored in input buffer in an interleaved fashion.

+
The functions operate on blocks of input and output data and each call to the function processes 2*fftLen samples through the transform. pSrc points to In-place arrays containing 2*fftLen values. 

+
The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below. 
 {real[0], imag[0], real[1], imag[1],..} 

+
Lengths supported by the transform: 

+
Internally, the function utilize a radix-4 decimation in frequency(DIF) algorithm and the size of the FFT supported are of the lengths [16, 64, 256, 1024].

+
Algorithm: 

+
Complex Fast Fourier Transform: 

+
Input real and imaginary data: 
   
+ x(n) = xa + j * ya   
+ x(n+N/4 ) = xb + j * yb   
+ x(n+N/2 ) = xc + j * yc   
+ x(n+3N 4) = xd + j * yd   
+ 
 where N is length of FFT 

+
Output real and imaginary data: 
   
+ X(4r) = xa'+ j * ya'   
+ X(4r+1) = xb'+ j * yb'   
+ X(4r+2) = xc'+ j * yc'   
+ X(4r+3) = xd'+ j * yd'   
+ 
 

+
Twiddle factors for radix-4 FFT: 
   
+ Wn = co1 + j * (- si1)   
+ W2n = co2 + j * (- si2)   
+ W3n = co3 + j * (- si3)   
+ 

+

+CFFT.gif
+
Radix-4 Decimation-in Frequency Complex Fast Fourier Transform

+

+
Output from Radix-4 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output. 

+
 Butterfly CFFT equations: 
   
+ xa' = xa + xb + xc + xd   
+ ya' = ya + yb + yc + yd   
+ xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)   
+ yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)   
+ xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)   
+ yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)   
+ xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)   
+ yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)   
+ 

+
Complex Inverse Fast Fourier Transform: 

+
CIFFT uses same twiddle factor table as CFFT with modifications in the design equation as shown below.

+
 Modified Butterfly CIFFT equations: 
   
+ xa' = xa + xb + xc + xd   
+ ya' = ya + yb + yc + yd   
+ xc' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)   
+ yc' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)   
+ xb' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)   
+ yb' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)   
+ xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)   
+ yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)   
+ 

+
Instance Structure 
A separate instance structure must be defined for each Instance but the twiddle factors and bit reversal tables can be reused. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Initializes twiddle factor table and bit reversal table pointers 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Manually initialize the instance structure as follows: 
   
+arm_cfft_radix4_instance_f32 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor, onebyfftLen};   
+arm_cfft_radix4_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+arm_cfft_radix4_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+ 
 

+
where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT); bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order); pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table. twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table; pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table. onebyfftLen value of 1/fftLen to calculate CIFFT;

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the CFFT/CIFFT function. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
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+      
arm_status arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 *  S, 
uint16_t  fftLen, 
uint8_t  ifftFlag, 
uint8_t  bitReverseFlag 
)

+

+

+
+
Initialization function for the floating-point CFFT/CIFFT. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.

+
Description: 

+
The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 

+
This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 

+
Examples: 
arm_convolution_example_f32.c, and arm_fft_bin_example_f32.c.

+

+
Definition at line 1118 of file arm_cfft_radix4_init_f32.c.

+
+

+

+
+

+

+      
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+      
void arm_cfft_radix4_f32 (const arm_cfft_radix4_instance_f32 *  S, 
float32_t *  pSrc 
)

+

+

+
+
Processing function for the floating-point CFFT/CIFFT. 

+
Parameters:

+  
+    
+    
+  
[in]*Spoints to an instance of the floating-point CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 

+  

+

+
Returns:
none. 

+
Examples: 
arm_convolution_example_f32.c, and arm_fft_bin_example_f32.c.

+

+
Definition at line 177 of file arm_cfft_radix4_f32.c.

+
+

+

+
+

+

+      
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+        
+      
arm_status arm_cfft_radix4_init_q31 (arm_cfft_radix4_instance_q31 *  S, 
uint16_t  fftLen, 
uint8_t  ifftFlag, 
uint8_t  bitReverseFlag 
)

+

+

+
+
Initialization function for the Q31 CFFT/CIFFT. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.

+
Description: 

+
The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 

+
This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 

+
+
Definition at line 608 of file arm_cfft_radix4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cfft_radix4_q31 (const arm_cfft_radix4_instance_q31 *  S, 
q31_t *  pSrc 
)

+

+

+
+
Processing function for the Q31 CFFT/CIFFT. 

+
Parameters:

+  
+    
+    
+  
[in]*Spoints to an instance of the Q31 CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer of size 2*fftLen. Processing occurs in-place. 

+  

+

+
Returns:
none.

+
Input and output formats: 

+
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different FFT sizes. The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: 

+

+CFFTQ31.gif
+
Input and Output Formats for Q31 CFFT

+ 

+CIFFTQ31.gif
+
Input and Output Formats for Q31 CIFFT

+ 

+
+
Definition at line 66 of file arm_cfft_radix4_q31.c.

+
+

+

+
+

+

+      
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+      
arm_status arm_cfft_radix4_init_q15 (arm_cfft_radix4_instance_q15 *  S, 
uint16_t  fftLen, 
uint8_t  ifftFlag, 
uint8_t  bitReverseFlag 
)

+

+

+
+
Initialization function for the Q15 CFFT/CIFFT. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 CFFT/CIFFT structure. 
[in]fftLenlength of the FFT. 
[in]ifftFlagflag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.

+
Description: 

+
The parameter ifftFlag controls whether a forward or inverse transform is computed. Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. 

+
This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. 

+
+
Definition at line 353 of file arm_cfft_radix4_init_q15.c.

+
+

+

+
+

+

+      
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+      
void arm_cfft_radix4_q15 (const arm_cfft_radix4_instance_q15 *  S, 
q15_t *  pSrc 
)

+

+

+
+
Processing function for the Q15 CFFT/CIFFT. 

+
Parameters:

+  
+    
+    
+  
[in]*Spoints to an instance of the Q15 CFFT/CIFFT structure. 
[in,out]*pSrcpoints to the complex data buffer. Processing occurs in-place. 

+  

+

+
Returns:
none.

+
Input and output formats: 

+
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different FFT sizes. The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: 

+

+CFFTQ15.gif
+
Input and Output Formats for Q15 CFFT

+ 

+CIFFTQ15.gif
+
Input and Output Formats for Q15 CIFFT

+ 

+
+
Definition at line 66 of file arm_cfft_radix4_q15.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t twiddleCoef[2048] [static]

+

+

+
Example code for Floating-point Twiddle factors Generation: 

+
for(i = 0; i< N; i++)   
+ {   
+	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);   
+	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);   
+ } 
 

+
where N = 1024 and PI = 3.14159265358979 

+
Cos and Sin values are in interleaved fashion 

+
+
Definition at line 70 of file arm_cfft_radix4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t twiddleCoefQ31[2048] [static]

+

+

+
Example code for Q31 Twiddle factors Generation:: 

+
for(i = 0; i< N; i++)   
+ {   
+    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);   
+    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);   
+ } 
 

+
where N = 1024 and PI = 3.14159265358979 

+
Cos and Sin values are interleaved fashion 

+
Convert Floating point to Q31(Fixed point 1.31): round(twiddleCoefQ31(i) * pow(2, 31)) 

+
+
Definition at line 71 of file arm_cfft_radix4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t twiddleCoefQ15[2048] [static]

+

+

+
Example code for Q15 Twiddle factors Generation:: 

+
for(i = 0; i< N; i++)   
+ {   
+	twiddleCoefQ15[2*i]= cos(i * 2*PI/(float)N);   
+	twiddleCoefQ15[2*i+1]= sin(i * 2*PI/(float)N);   
+ } 
 

+
where N = 1024 and PI = 3.14159265358979 

+
Cos and Sin values are interleaved fashion 

+
Convert Floating point to Q15(Fixed point 1.15): round(twiddleCoefQ15(i) * pow(2, 15)) 

+
+
Definition at line 72 of file arm_cfft_radix4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const uint16_t armBitRevTable[256]

+

+

+
Pseudo code for Generation of Bit reversal Table is 

+
for(l=1;l <= N/4;l++)   
+ {   
+   for(i=0;i<logN2;i++)   
+   {    
+     a[i]=l&(1<<i);   
+   }   
+   for(j=0; j<logN2; j++)   
+   {   
+     if (a[j]!=0)   
+     y[l]+=(1<<((logN2-1)-j));   
+   }   
+   y[l] = y[l] >> 1;   
+  } 
 

+
where N = 1024 logN2 = 10 

+
N is the maximum FFT Size supported 

+
+
Definition at line 68 of file arm_common_tables.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___class_marks.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___class_marks.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___class_marks.html
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+
+
+
+
+CMSIS DSP Software Library: Class Marks Example
+
+
+
+
+
+
+
+
+
+

+  

+
Class Marks Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance and Matrix functions to calculate statistical values of marks obtained in a class.

+
Note:
This example also demonstrates the usage of static initialization.

+
Variables Description:

+
    
+
  • testMarks_f32 points to the marks scored by 20 students in 4 subjects 
    • 
+
  • max_marks Maximum of all marks 
    • 
+
  • min_marks Minimum of all marks 
    • 
+
  • mean Mean of all marks 
    • 
+
  • var Variance of the marks 
    • 
+
  • std Standard deviation of the marks 
    • 
+
  • numStudents Total number of students in the class
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_class_marks_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___cmplx_by_cmplx_mult.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___cmplx_by_cmplx_mult.html
new file mode 100644
index 0000000..6b7fb89
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+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___cmplx_by_cmplx_mult.html
@@ -0,0 +1,253 @@
+
+
+
+
+CMSIS DSP Software Library: Complex-by-Complex Multiplication
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Complex-by-Complex Multiplication

+
+[Complex Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_cmplx_mult_cmplx_f32 (float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_mult_cmplx_q31 (q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_mult_cmplx_q15 (q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples)

+
Detailed Description

+
Multiplies a complex vector by another complex vector and generates a complex result. The data in the complex arrays is stored in an interleaved fashion (real, imag, real, imag, ...). The parameter numSamples represents the number of complex samples processed. The complex arrays have a total of 2*numSamples real values.

+
The underlying algorithm is used:

+
   
+ for(n=0; n<numSamples; n++) {   
+     pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];   
+     pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];   
+ }   
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
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+        
+      
void arm_cmplx_mult_cmplx_f32 (float32_t *  pSrcA, 
float32_t *  pSrcB, 
float32_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Floating-point complex-by-complex multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_convolution_example_f32.c.

+

+
Definition at line 73 of file arm_cmplx_mult_cmplx_f32.c.

+
+

+

+
+

+

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+          
+        
+      
void arm_cmplx_mult_cmplx_q31 (q31_t *  pSrcA, 
q31_t *  pSrcB, 
q31_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q31 complex-by-complex multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. Input down scaling is not required. 

+
+
Definition at line 56 of file arm_cmplx_mult_cmplx_q31.c.

+
+

+

+
+

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+      
void arm_cmplx_mult_cmplx_q15 (q15_t *  pSrcA, 
q15_t *  pSrcB, 
q15_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q15 complex-by-complex multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[out]*pDstpoints to the output vector 
[in]numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. 

+
+
Definition at line 54 of file arm_cmplx_mult_cmplx_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___cmplx_by_real_mult.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___cmplx_by_real_mult.html
new file mode 100644
index 0000000..c2c76f6
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+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___cmplx_by_real_mult.html
@@ -0,0 +1,252 @@
+
+
+
+
+CMSIS DSP Software Library: Complex-by-Real Multiplication
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Complex-by-Real Multiplication

+
+[Complex Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_cmplx_mult_real_f32 (float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, uint32_t numSamples)
void arm_cmplx_mult_real_q31 (q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, uint32_t numSamples)
void arm_cmplx_mult_real_q15 (q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, uint32_t numSamples)

+
Detailed Description

+
Multiplies a complex vector by a real vector and generates a complex result. The data in the complex arrays is stored in an interleaved fashion (real, imag, real, imag, ...). The parameter numSamples represents the number of complex samples processed. The complex arrays have a total of 2*numSamples real values while the real array has a total of numSamples real values.

+
The underlying algorithm is used:

+
   
+ for(n=0; n<numSamples; n++) {   
+     pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];   
+     pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];   
+ }   
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+        
+      
void arm_cmplx_mult_real_f32 (float32_t *  pSrcCmplx, 
float32_t *  pSrcReal, 
float32_t *  pCmplxDst, 
uint32_t  numSamples 
)

+

+

+
+
Floating-point complex-by-real multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcCmplxpoints to the complex input vector 
[in]*pSrcRealpoints to the real input vector 
[out]*pCmplxDstpoints to the complex output vector 
[in]numSamplesnumber of samples in each vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 74 of file arm_cmplx_mult_real_f32.c.

+
+

+

+
+

+

+      
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+          
+        
+      
void arm_cmplx_mult_real_q31 (q31_t *  pSrcCmplx, 
q31_t *  pSrcReal, 
q31_t *  pCmplxDst, 
uint32_t  numSamples 
)

+

+

+
+
Q31 complex-by-real multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcCmplxpoints to the complex input vector 
[in]*pSrcRealpoints to the real input vector 
[out]*pCmplxDstpoints to the complex output vector 
[in]numSamplesnumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 56 of file arm_cmplx_mult_real_q31.c.

+
+

+

+
+

+

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+      
void arm_cmplx_mult_real_q15 (q15_t *  pSrcCmplx, 
q15_t *  pSrcReal, 
q15_t *  pCmplxDst, 
uint32_t  numSamples 
)

+

+

+
+
Q15 complex-by-real multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcCmplxpoints to the complex input vector 
[in]*pSrcRealpoints to the real input vector 
[out]*pCmplxDstpoints to the complex output vector 
[in]numSamplesnumber of samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 56 of file arm_cmplx_mult_real_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___conv.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___conv.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___conv.html
@@ -0,0 +1,475 @@
+
+
+
+
+CMSIS DSP Software Library: Convolution
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Convolution

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_conv_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
void arm_conv_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_conv_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_conv_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_conv_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_conv_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)

+
Detailed Description

+
Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector. Convolution is similar to correlation and is frequently used in filtering and data analysis. The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types. The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.

+
Algorithm 
Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. Then the convolution

+
   
+                   c[n] = a[n] * b[n]   
+ 
is defined as 

+ConvolutionEquation.gif
+

+ 

+
Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2. pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.

+
Conceptually, when two signals a[n] and b[n] are convolved, the signal b[n] slides over a[n]. For each offset n, the overlapping portions of a[n] and b[n] are multiplied and summed together.

+
Note that convolution is a commutative operation:

+
   
+                   a[n] * b[n] = b[n] * a[n].   
+ 
This means that switching the A and B arguments to the convolution functions has no effect.

+
Fixed-Point Behavior

+
Convolution requires summing up a large number of intermediate products. As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. Refer to the function specific documentation below for further details of the particular algorithm used. 

+
Function Documentation

+
+

+

+      
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void arm_conv_f32 (float32_t *  pSrcA, 
uint32_t  srcALen, 
float32_t *  pSrcB, 
uint32_t  srcBLen, 
float32_t *  pDst 
)

+

+

+
+
Convolution of floating-point sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none. 

+
+
Definition at line 103 of file arm_conv_f32.c.

+
+

+

+
+

+

+      
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void arm_conv_q31 (q31_t *  pSrcA, 
uint32_t  srcALen, 
q31_t *  pSrcB, 
uint32_t  srcBLen, 
q31_t *  pDst 
)

+

+

+
+
Convolution of Q31 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally. The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.

+
See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 71 of file arm_conv_q31.c.

+
+

+

+
+

+

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+        
+      
void arm_conv_fast_q31 (q31_t *  pSrcA, 
uint32_t  srcALen, 
q31_t *  pSrcB, 
uint32_t  srcBLen, 
q31_t *  pDst 
)

+

+

+
+
Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.31 result.

+
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally.

+
See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 

+
+
Definition at line 68 of file arm_conv_fast_q31.c.

+
+

+

+
+

+

+      
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+      
void arm_conv_q15 (q15_t *  pSrcA, 
uint32_t  srcALen, 
q15_t *  pSrcB, 
uint32_t  srcBLen, 
q15_t *  pDst 
)

+

+

+
+
Convolution of Q15 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.

+
Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 68 of file arm_conv_q15.c.

+
+

+

+
+

+

+      
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+      
void arm_conv_fast_q15 (q15_t *  pSrcA, 
uint32_t  srcALen, 
q15_t *  pSrcB, 
uint32_t  srcBLen, 
q15_t *  pDst 
)

+

+

+
+
Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.

+
See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. 

+
+
Definition at line 66 of file arm_conv_fast_q15.c.

+
+

+

+
+

+

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+        
+      
void arm_conv_q7 (q7_t *  pSrcA, 
uint32_t  srcALen, 
q7_t *  pSrcB, 
uint32_t  srcBLen, 
q7_t *  pDst 
)

+

+

+
+
Convolution of Q7 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. 

+
+
Definition at line 65 of file arm_conv_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___convolution_example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___convolution_example.html
new file mode 100644
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@@ -0,0 +1,105 @@
+
+
+
+
+CMSIS DSP Software Library: Convolution Example
+
+
+
+
+
+
+
+
+
+

+  

+
Convolution Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex Multiplication, and Support Functions.

+
Algorithm:

+
The convolution theorem states that convolution in the time domain corresponds to multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of two signals is equal to the product of their individual Fourier transforms. The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT). 

+
Two input signals, a[n] and b[n], with lengths n1 and n2 respectively, are zero padded so that their lengths become N, which is greater than or equal to (n1+n2-1) and is a power of 4 as FFT implementation is radix-4. The convolution of a[n] and b[n] is obtained by taking the FFT of the input signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of the multiplied result. 

+
This is denoted by the following equations: 
 A[k] = FFT(a[n],N)
+ B[k] = FFT(b[n],N)
+ conv(a[n], b[n]) = IFFT(A[k] * B[k], N)
 where A[k] and B[k] are the N-point FFTs of the signals a[n] and b[n] respectively. The length of the convolved signal is (n1+n2-1).

+
Block Diagram:

+

+Convolution.gif
+

+

+
Variables Description:

+
    
+
  • testInputA_f32 points to the first input sequence 
    • 
+
  • srcALen length of the first input sequence 
    • 
+
  • testInputB_f32 points to the second input sequence 
    • 
+
  • srcBLen length of the second input sequence 
    • 
+
  • outLen length of convolution output sequence, (srcALen + srcBLen - 1) 
    • 
+
  • AxB points to the output array where the product of individual FFTs of inputs is stored.
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_convolution_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___corr.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___corr.html
new file mode 100644
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+
+
+
+
+CMSIS DSP Software Library: Correlation
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Correlation

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_correlate_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
void arm_correlate_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_correlate_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
void arm_correlate_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_correlate_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
void arm_correlate_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)

+
Detailed Description

+
Correlation is a mathematical operation that is similar to convolution. As with convolution, correlation uses two signals to produce a third signal. The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution. Correlation is commonly used to measure the similarity between two signals. It has applications in pattern recognition, cryptanalysis, and searching. The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types. Fast versions of the Q15 and Q31 functions are also provided.

+
Algorithm 
Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. The convolution of the two signals is denoted by 
   
+                   c[n] = a[n] * b[n]   
+ 
 In correlation, one of the signals is flipped in time 
   
+                   c[n] = a[n] * b[-n]   
+ 

+
and this is mathematically defined as 

+CorrelateEquation.gif
+

+ 

+
The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2). The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.

+
Note 

+
The pDst should be initialized to all zeros before being used.

+
Fixed-Point Behavior 

+
Correlation requires summing up a large number of intermediate products. As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. Refer to the function specific documentation below for further details of the particular algorithm used. 

+
Function Documentation

+
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void arm_correlate_f32 (float32_t *  pSrcA, 
uint32_t  srcALen, 
float32_t *  pSrcB, 
uint32_t  srcBLen, 
float32_t *  pDst 
)

+

+

+
+
Correlation of floating-point sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none. 

+
+
Definition at line 95 of file arm_correlate_f32.c.

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void arm_correlate_q31 (q31_t *  pSrcA, 
uint32_t  srcALen, 
q31_t *  pSrcB, 
uint32_t  srcBLen, 
q31_t *  pDst 
)

+

+

+
+
Correlation of Q31 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a maximum of min(srcALen, srcBLen) number of additions is carried internally. The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.

+
See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 71 of file arm_correlate_q31.c.

+
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void arm_correlate_fast_q31 (q31_t *  pSrcA, 
uint32_t  srcALen, 
q31_t *  pSrcB, 
uint32_t  srcBLen, 
q31_t *  pDst 
)

+

+

+
+
Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.31 result.

+
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a maximum of min(srcALen, srcBLen) number of additions is carried internally.

+
See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 

+
+
Definition at line 70 of file arm_correlate_fast_q31.c.

+
+

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void arm_correlate_q15 (q15_t *  pSrcA, 
uint32_t  srcALen, 
q15_t *  pSrcB, 
uint32_t  srcBLen, 
q15_t *  pDst 
)

+

+

+
+
Correlation of Q15 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.

+
Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 68 of file arm_correlate_q15.c.

+
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void arm_correlate_fast_q15 (q15_t *  pSrcA, 
uint32_t  srcALen, 
q15_t *  pSrcB, 
uint32_t  srcBLen, 
q15_t *  pDst 
)

+

+

+
+
Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a maximum of min(srcALen, srcBLen) number of additions is carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.

+
See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. 

+
+
Definition at line 66 of file arm_correlate_fast_q15.c.

+
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void arm_correlate_q7 (q7_t *  pSrcA, 
uint32_t  srcALen, 
q7_t *  pSrcB, 
uint32_t  srcBLen, 
q7_t *  pDst 
)

+

+

+
+
Correlation of Q7 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format. 

+
+
Definition at line 65 of file arm_correlate_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___d_c_t4___i_d_c_t4.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___d_c_t4___i_d_c_t4.html
new file mode 100644
index 0000000..8a777ed
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___d_c_t4___i_d_c_t4.html
@@ -0,0 +1,839 @@
+
+
+
+
+CMSIS DSP Software Library: DCT Type IV Functions
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
DCT Type IV Functions

+
+[Transform Functions]
+
  

+

+

+
+
+
+
+
+
+
+
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+Functions
arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize)
void arm_dct4_f32 (const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer)
arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize)
void arm_dct4_q31 (const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer)
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize)
void arm_dct4_q15 (const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer)

+Variables
static const float32_t Weights_128 [256]
static const float32_t Weights_512 [1024]
static const float32_t Weights_2048 [4096]
static const float32_t cos_factors_128 [128]
static const float32_t cos_factors_512 [512]
static const float32_t cos_factors_2048 [2048]
static const q31_t WeightsQ31_128 [256]
static const q31_t WeightsQ31_512 [1024]
static const q31_t WeightsQ31_2048 [4096]
static const q31_t cos_factorsQ31_128 [128]
static const q31_t cos_factorsQ31_512 [512]
static const q31_t cos_factorsQ31_2048 [2048]
static const q15_t WeightsQ15_128 [256]
static const q15_t WeightsQ15_512 [1024]
static const q15_t WeightsQ15_2048 [4096]
static const q15_t cos_factorsQ15_128 [128]
static const q15_t cos_factorsQ15_512 [512]
static const q15_t cos_factorsQ15_2048 [2048]

+
Detailed Description

+
Representation of signals by minimum number of values is important for storage and transmission. The possibility of large discontinuity between the beginning and end of a period of a signal in DFT can be avoided by extending the signal so that it is even-symmetric. Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the spectrum and is very widely used in signal and image coding applications. The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions. DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.

+
DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal. Reordering of the input data makes the computation of DCT just a problem of computing the DFT of a real signal with a few additional operations. This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.

+
DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used. DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing. DCT2 implementation can be described in the following steps:

+
    
+
  • Re-ordering input
    • 
+
  • Calculating Real FFT
    • 
+
  • Multiplication of weights and Real FFT output and getting real part from the product.
    • 
+

+
This process is explained by the block diagram below: 

+

+DCT4.gif
+
Discrete Cosine Transform - type-IV

+
Algorithm: 
The N-point type-IV DCT is defined as a real, linear transformation by the formula: 

+DCT4Equation.gif
+

+ where k = 0,1,2,.....N-1 

+
Its inverse is defined as follows: 

+IDCT4Equation.gif
+

+ where n = 0,1,2,.....N-1 

+
The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N). The symmetry of the transform matrix indicates that the fast algorithms for the forward and inverse transform computation are identical. Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.

+
Lengths supported by the transform: 
As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32(). The library provides separate functions for Q15, Q31, and floating-point data types. 

+
Instance Structure 
The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure. A separate instance structure must be defined for each transform. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32(). 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Manually initialize the instance structure as follows: 
   
+arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
+arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};  
+arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};  
+ 
 where N is the length of the DCT4; Nby2 is half of the length of the DCT4; normalize is normalizing factor used and is equal to sqrt(2/N); pTwiddle points to the twiddle factor table; pCosFactor points to the cosFactor table; pRfft points to the real FFT instance; pCfft points to the complex FFT instance; The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32() and arm_rfft_f32() respectively for details regarding static initialization.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the DCT4 transform functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
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+

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arm_status arm_dct4_init_f32 (arm_dct4_instance_f32 *  S, 
arm_rfft_instance_f32 *  S_RFFT, 
arm_cfft_radix4_instance_f32 *  S_CFFT, 
uint16_t  N, 
uint16_t  Nby2, 
float32_t  normalize 
)

+

+

+
+
Initialization function for the floating-point DCT4/IDCT4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of floating-point DCT4/IDCT4 structure. 
[in]*S_RFFTpoints to an instance of floating-point RFFT/RIFFT structure. 
[in]*S_CFFTpoints to an instance of floating-point CFFT/CIFFT structure. 
[in]Nlength of the DCT4. 
[in]Nby2half of the length of the DCT4. 
[in]normalizenormalizing factor. 

+  

+

+
Returns:
arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. 

+
Normalizing factor: 
The normalizing factor is sqrt(2/N), which depends on the size of transform N. Floating-point normalizing factors are mentioned in the table below for different DCT sizes: 

+dct4NormalizingF32Table.gif
+

+ 

+
+
Definition at line 4142 of file arm_dct4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dct4_f32 (const arm_dct4_instance_f32 *  S, 
float32_t *  pState, 
float32_t *  pInlineBuffer 
)

+

+

+
+
Processing function for the floating-point DCT4/IDCT4. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point DCT4/IDCT4 structure. 
[in]*pStatepoints to state buffer. 
[in,out]*pInlineBufferpoints to the in-place input and output buffer. 

+  

+

+
Returns:
none. 

+
+
Definition at line 126 of file arm_dct4_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_dct4_init_q31 (arm_dct4_instance_q31 *  S, 
arm_rfft_instance_q31 *  S_RFFT, 
arm_cfft_radix4_instance_q31 *  S_CFFT, 
uint16_t  N, 
uint16_t  Nby2, 
q31_t  normalize 
)

+

+

+
+
Initialization function for the Q31 DCT4/IDCT4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of Q31 DCT4/IDCT4 structure. 
[in]*S_RFFTpoints to an instance of Q31 RFFT/RIFFT structure 
[in]*S_CFFTpoints to an instance of Q31 CFFT/CIFFT structure 
[in]Nlength of the DCT4. 
[in]Nby2half of the length of the DCT4. 
[in]normalizenormalizing factor. 

+  

+

+
Returns:
arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. 

+
Normalizing factor: 
The normalizing factor is sqrt(2/N), which depends on the size of transform N. Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes: 

+dct4NormalizingQ31Table.gif
+

+ 

+
+
Definition at line 2133 of file arm_dct4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dct4_q31 (const arm_dct4_instance_q31 *  S, 
q31_t *  pState, 
q31_t *  pInlineBuffer 
)

+

+

+
+
Processing function for the Q31 DCT4/IDCT4. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 DCT4 structure. 
[in]*pStatepoints to state buffer. 
[in,out]*pInlineBufferpoints to the in-place input and output buffer. 

+  

+

+
Returns:
none. 

+
Input an output formats: 
Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process, as the conversion from DCT2 to DCT4 involves one subtraction. Internally inputs are downscaled in the RFFT process function to avoid overflows. Number of bits downscaled, depends on the size of the transform. The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:

+

+dct4FormatsQ31Table.gif
+

+ 
+
Definition at line 53 of file arm_dct4_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_dct4_init_q15 (arm_dct4_instance_q15 *  S, 
arm_rfft_instance_q15 *  S_RFFT, 
arm_cfft_radix4_instance_q15 *  S_CFFT, 
uint16_t  N, 
uint16_t  Nby2, 
q15_t  normalize 
)

+

+

+
+
Initialization function for the Q15 DCT4/IDCT4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of Q15 DCT4/IDCT4 structure. 
[in]*S_RFFTpoints to an instance of Q15 RFFT/RIFFT structure. 
[in]*S_CFFTpoints to an instance of Q15 CFFT/CIFFT structure. 
[in]Nlength of the DCT4. 
[in]Nby2half of the length of the DCT4. 
[in]normalizenormalizing factor. 

+  

+

+
Returns:
arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. 

+
Normalizing factor: 
The normalizing factor is sqrt(2/N), which depends on the size of transform N. Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes: 

+dct4NormalizingQ15Table.gif
+

+ 

+
+
Definition at line 1125 of file arm_dct4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dct4_q15 (const arm_dct4_instance_q15 *  S, 
q15_t *  pState, 
q15_t *  pInlineBuffer 
)

+

+

+
+
Processing function for the Q15 DCT4/IDCT4. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 DCT4 structure. 
[in]*pStatepoints to state buffer. 
[in,out]*pInlineBufferpoints to the in-place input and output buffer. 

+  

+

+
Returns:
none.

+
Input an output formats: 
Internally inputs are downscaled in the RFFT process function to avoid overflows. Number of bits downscaled, depends on the size of the transform. The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:

+

+dct4FormatsQ15Table.gif
+

+ 
+
Definition at line 52 of file arm_dct4_q15.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t Weights_128[256] [static]

+

+

+
Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
 

+
C command to generate the table 
   
+ for(i = 0; i< N; i++)   
+ {   
+    weights[2*i]= cos(i*c);   
+    weights[(2*i)+1]= -sin(i * c);   
+ } 
 

+
Where N is the Number of weights to be calculated and c is pi/(2*N) 

+
In the tables below the real and imaginary values are placed alternatively, hence the array length is 2*N. 

+
+
Definition at line 64 of file arm_dct4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t Weights_512[1024] [static]

+

+

+
+
Definition at line 195 of file arm_dct4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t Weights_2048[4096] [static]

+

+

+
+
Definition at line 710 of file arm_dct4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t cos_factors_128[128] [static]

+

+

+
cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
 

+
C command to generate the table 

+
 for(i = 0; i< N; i++)   
+ {   
+    cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+ } 
 

+
where N is the number of factors to generate and c is pi/(2*N) 

+
+
Definition at line 2774 of file arm_dct4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t cos_factors_512[512] [static]

+

+

+
+
Definition at line 2841 of file arm_dct4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t cos_factors_2048[2048] [static]

+

+

+
+
Definition at line 3100 of file arm_dct4_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t WeightsQ31_128[256] [static]

+

+

+
Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
 

+
C command to generate the table 
   
+ for(i = 0; i< N; i++)   
+ {   
+   weights[2*i]= cos(i*c);   
+   weights[(2*i)+1]= -sin(i * c);   
+ } 
 

+
where N is the Number of weights to be calculated and c is pi/(2*N) 

+
Convert the output to q31 format by multiplying with 2^31 and saturated if required. 

+
In the tables below the real and imaginary values are placed alternatively, hence the array length is 2*N. 

+
+
Definition at line 66 of file arm_dct4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t WeightsQ31_512[1024] [static]

+

+

+
+
Definition at line 133 of file arm_dct4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t WeightsQ31_2048[4096] [static]

+

+

+
+
Definition at line 392 of file arm_dct4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t cos_factorsQ31_128[128] [static]

+

+

+
cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
 

+
C command to generate the table 
   
+ for(i = 0; i< N; i++)   
+ {   
+   cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+ } 
 

+
where N is the number of factors to generate and c is pi/(2*N) 

+
Then converted to q31 format by multiplying with 2^31 and saturated if required. 

+
+
Definition at line 1436 of file arm_dct4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t cos_factorsQ31_512[512] [static]

+

+

+
+
Definition at line 1471 of file arm_dct4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t cos_factorsQ31_2048[2048] [static]

+

+

+
+
Definition at line 1602 of file arm_dct4_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t WeightsQ15_128[256] [static]

+

+

+
Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
 

+
C command to generate the table 
   
+ for(i = 0; i< N; i++)   
+ {   
+   weights[2*i]= cos(i*c);   
+   weights[(2*i)+1]= -sin(i * c);   
+ } 
 

+
where N is the Number of weights to be calculated and c is pi/(2*N) 

+
Converted the output to q15 format by multiplying with 2^31 and saturated if required. 

+
In the tables below the real and imaginary values are placed alternatively, hence the array length is 2*N. 

+
+
Definition at line 66 of file arm_dct4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t WeightsQ15_512[1024] [static]

+

+

+
+
Definition at line 101 of file arm_dct4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t WeightsQ15_2048[4096] [static]

+

+

+
+
Definition at line 232 of file arm_dct4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t cos_factorsQ15_128[128] [static]

+

+

+Initial value:
 {
+  0x7fff, 0x7ffa, 0x7ff0, 0x7fe1, 0x7fce, 0x7fb5, 0x7f97, 0x7f75,
+  0x7f4d, 0x7f21, 0x7ef0, 0x7eba, 0x7e7f, 0x7e3f, 0x7dfa, 0x7db0,
+  0x7d62, 0x7d0f, 0x7cb7, 0x7c5a, 0x7bf8, 0x7b92, 0x7b26, 0x7ab6,
+  0x7a42, 0x79c8, 0x794a, 0x78c7, 0x7840, 0x77b4, 0x7723, 0x768e,
+  0x75f4, 0x7555, 0x74b2, 0x740b, 0x735f, 0x72af, 0x71fa, 0x7141,
+  0x7083, 0x6fc1, 0x6efb, 0x6e30, 0x6d62, 0x6c8f, 0x6bb8, 0x6adc,
+  0x69fd, 0x6919, 0x6832, 0x6746, 0x6657, 0x6563, 0x646c, 0x6371,
+  0x6271, 0x616f, 0x6068, 0x5f5e, 0x5e50, 0x5d3e, 0x5c29, 0x5b10,
+  0x59f3, 0x58d4, 0x57b0, 0x568a, 0x5560, 0x5433, 0x5302, 0x51ce,
+  0x5097, 0x4f5e, 0x4e21, 0x4ce1, 0x4b9e, 0x4a58, 0x490f, 0x47c3,
+  0x4675, 0x4524, 0x43d0, 0x427a, 0x4121, 0x3fc5, 0x3e68, 0x3d07,
+  0x3ba5, 0x3a40, 0x38d8, 0x376f, 0x3604, 0x3496, 0x3326, 0x31b5,
+  0x3041, 0x2ecc, 0x2d55, 0x2bdc, 0x2a61, 0x28e5, 0x2767, 0x25e8,
+  0x2467, 0x22e5, 0x2161, 0x1fdc, 0x1e56, 0x1ccf, 0x1b47, 0x19bd,
+  0x1833, 0x16a8, 0x151b, 0x138e, 0x1201, 0x1072, 0xee3, 0xd53,
+  0xbc3, 0xa33, 0x8a2, 0x710, 0x57f, 0x3ed, 0x25b, 0xc9
+}
+
cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) 
 

+
C command to generate the table 
   
+ for(i = 0; i< N; i++)   
+ {   
+   cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+ } 
 

+
where N is the number of factors to generate and c is pi/(2*N) 

+
Then converted to q15 format by multiplying with 2^31 and saturated if required. 

+
+
Definition at line 764 of file arm_dct4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t cos_factorsQ15_512[512] [static]

+

+

+
+
Definition at line 783 of file arm_dct4_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t cos_factorsQ15_2048[2048] [static]

+

+

+
+
Definition at line 850 of file arm_dct4_init_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___dotproduct_example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___dotproduct_example.html
new file mode 100644
index 0000000..3c4a96a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___dotproduct_example.html
@@ -0,0 +1,96 @@
+
+
+
+
+CMSIS DSP Software Library: Dot Product Example
+
+
+
+
+
+
+
+
+
+

+  

+
Dot Product Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Demonstrates the use of the Multiply and Add functions to perform the dot product. The dot product of two vectors is obtained by multiplying corresponding elements and summing the products.

+
Algorithm:

+
The two input vectors A and B with length n, are multiplied element-by-element and then added to obtain dot product. 

+
This is denoted by the following equation: 
  dotProduct = A[0] * B[0] + A[1] * B[1] + ... + A[n-1] * B[n-1]

+
Block Diagram:

+

+dotProduct.gif
+

+

+
Variables Description:

+
    
+
  • srcA_buf_f32 points to first input vector 
    • 
+
  • srcB_buf_f32 points to second input vector 
    • 
+
  • testOutput stores dot product of the two input vectors.
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_dotproduct_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r.html
new file mode 100644
index 0000000..72c41d6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r.html
@@ -0,0 +1,721 @@
+
+
+
+
+CMSIS DSP Software Library: Finite Impulse Response (FIR) Filters
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Filters

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_fir_init_f32 (arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
void arm_fir_f32 (const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_fir_init_q31 (arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
void arm_fir_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_fast_q31 (const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
arm_status arm_fir_init_q15 (arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
void arm_fir_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_fir_fast_q15 (const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_fir_init_q7 (arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, uint32_t blockSize)
void arm_fir_q7 (const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
This set of functions implements Finite Impulse Response (FIR) filters for Q7, Q15, Q31, and floating-point data types. Fast versions of Q15 and Q31 are also provided on Cortex-M4 and Cortex-M3. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst points to input and output arrays containing blockSize values.

+
Algorithm: 
The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations. Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n]. 
   
+    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ 
 

+

+FIR.gif
+
Finite Impulse Response filter

+ 

+
pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 

+
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the following order. 

+
   
+    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ 
 

+
Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1. The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters, to be avoided and yields a significant speed improvement. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 4 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 4 different data type filter instance structures 
   
+arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};   
+arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};   
+arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};   
+arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};   
+ 

+
where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

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void arm_fir_init_f32 (arm_fir_instance_f32 *  S, 
uint16_t  numTaps, 
float32_t *  pCoeffs, 
float32_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the floating-point FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of samples that are processed per call. 

+  

+

+
Returns:
none.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32(). 

+
Examples: 
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 68 of file arm_fir_init_f32.c.

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void arm_fir_f32 (const arm_fir_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none. 

+
Examples: 
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 128 of file arm_fir_f32.c.

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void arm_fir_init_q31 (arm_fir_instance_q31 *  S, 
uint16_t  numTaps, 
q31_t *  pCoeffs, 
q31_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q31 FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of samples that are processed per call. 

+  

+

+
Returns:
none.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31(). 

+
+
Definition at line 68 of file arm_fir_init_q31.c.

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void arm_fir_q31 (const arm_fir_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.

+
Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 67 of file arm_fir_q31.c.

+
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void arm_fir_fast_q31 (const arm_fir_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are added to a 2.30 accumulator. Finally, the accumulator is saturated and converted to a 1.31 result. The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.

+
Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_init_q31() to initialize the filter structure. 

+
+
Definition at line 66 of file arm_fir_fast_q31.c.

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arm_status arm_fir_init_q15 (arm_fir_instance_q15 *  S, 
uint16_t  numTaps, 
q15_t *  pCoeffs, 
q15_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q15 FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. Must be even and greater than or equal to 4. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizeis number of samples processed per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if numTaps is not greater than or equal to 4 and even.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 Note that numTaps must be even and greater than or equal to 4. To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero. For example, to implement a filter with numTaps=3 and coefficients 
   
+     {0.3, -0.8, 0.3}   
+ 
 set numTaps=4 and use the coefficients: 
   
+     {0.3, -0.8, 0.3, 0}.   
+ 
 Similarly, to implement a two point filter 
   
+     {0.3, -0.3}   
+ 
 set numTaps=4 and use the coefficients: 
   
+     {0.3, -0.3, 0, 0}.   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1, where blockSize is the number of input samples processed by each call to arm_fir_q15(). 

+
+
Definition at line 85 of file arm_fir_init_q15.c.

+
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void arm_fir_q15 (const arm_fir_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.

+
Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 68 of file arm_fir_q15.c.

+
+

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void arm_fir_fast_q15 (const arm_fir_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.

+
Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_init_q15() to initialize the filter structure. 

+
+
Definition at line 65 of file arm_fir_fast_q15.c.

+
+

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void arm_fir_init_q7 (arm_fir_instance_q7 *  S, 
uint16_t  numTaps, 
q7_t *  pCoeffs, 
q7_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q7 FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q7 FIR filter structure. 
[in]numTapsNumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficients buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of samples that are processed per call. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7(). 

+
+
Definition at line 65 of file arm_fir_init_q7.c.

+
+

+

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void arm_fir_q7 (const arm_fir_instance_q7 *  S, 
q7_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q7 FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q7 FIR filter structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 32-bit internal accumulator. Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. The accumulator is converted to 18.7 format by discarding the low 7 bits. Finally, the result is truncated to 1.7 format. 

+
+
Definition at line 64 of file arm_fir_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___interpolate.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___interpolate.html
new file mode 100644
index 0000000..cb4ae78
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___interpolate.html
@@ -0,0 +1,497 @@
+
+
+
+
+CMSIS DSP Software Library: Finite Impulse Response (FIR) Interpolator
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Interpolator

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *S, uint8_t L, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *S, uint8_t L, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *S, uint8_t L, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+
Detailed Description

+
These functions combine an upsampler (zero stuffer) and an FIR filter. They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images. Conceptually, the functions are equivalent to the block diagram below: 

+

+FIRInterpolator.gif
+
Components included in the FIR Interpolator functions

+
 After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum. The user of the function is responsible for providing the filter coefficients.

+
The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner. The upsampler inserts L-1 zeros between each sample. Instead of multiplying by these zero values, the FIR filter is designed to skip them. This leads to an efficient implementation without any wasted effort. The functions operate on blocks of input and output data. pSrc points to an array of blockSize input values and pDst points to an array of blockSize*L output values.

+
The library provides separate functions for Q15, Q31, and floating-point data types.

+
Algorithm: 
The functions use a polyphase filter structure: 
   
+    y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]   
+    y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]   
+    ...   
+    y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]   
+ 
 This approach is more efficient than straightforward upsample-then-filter algorithms. With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter. 

+
pCoeffs points to a coefficient array of size numTaps. numTaps must be a multiple of the interpolation factor L and this is checked by the initialization functions. Internally, the function divides the FIR filter's impulse response into shorter filters of length phaseLength=numTaps/L. Coefficients are stored in time reversed order. 

+
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to a state array of size blockSize + phaseLength - 1. Samples in the state buffer are stored in the order: 

+
   
+    {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}   
+ 
 The state variables are updated after each block of data is processed, the coefficients are untouched.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable array should be allocated separately. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+
  • Checks to make sure that the length of the filter is a multiple of the interpolation factor.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. The code below statically initializes each of the 3 different data type filter instance structures 
   
+ arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};   
+ arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};   
+ arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};   
+ 
 where L is the interpolation factor; phaseLength=numTaps/L is the length of each of the shorter FIR filters used internally, pCoeffs is the address of the coefficient buffer; pState is the address of the state buffer. Be sure to set the values in the state buffer to zeros when doing static initialization.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR interpolate filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
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arm_status arm_fir_interpolate_init_f32 (arm_fir_interpolate_instance_f32 *  S, 
uint8_t  L, 
uint16_t  numTaps, 
float32_t *  pCoeffs, 
float32_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the floating-point FIR interpolator. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point FIR interpolator structure. 
[in]Lupsample factor. 
[in]numTapsnumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ 
 The length of the filter numTaps must be a multiple of the interpolation factor L. 

+
pState points to the array of state variables. pState is of length (numTaps/L)+blockSize-1 words where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32(). 

+
+
Definition at line 68 of file arm_fir_interpolate_init_f32.c.

+
+

+

+
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void arm_fir_interpolate_f32 (const arm_fir_interpolate_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point FIR interpolator. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR interpolator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none. 

+
+
Definition at line 135 of file arm_fir_interpolate_f32.c.

+
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+

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arm_status arm_fir_interpolate_init_q31 (arm_fir_interpolate_instance_q31 *  S, 
uint8_t  L, 
uint16_t  numTaps, 
q31_t *  pCoeffs, 
q31_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q31 FIR interpolator. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 FIR interpolator structure. 
[in]Lupsample factor. 
[in]numTapsnumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ 
 The length of the filter numTaps must be a multiple of the interpolation factor L. 

+
pState points to the array of state variables. pState is of length (numTaps/L)+blockSize-1 words where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31(). 

+
+
Definition at line 69 of file arm_fir_interpolate_init_q31.c.

+
+

+

+
+

+

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void arm_fir_interpolate_q31 (const arm_fir_interpolate_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 FIR interpolator. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR interpolator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L). since numTaps/L additions occur per output sample. After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 

+
+
Definition at line 63 of file arm_fir_interpolate_q31.c.

+
+

+

+
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arm_status arm_fir_interpolate_init_q15 (arm_fir_interpolate_instance_q15 *  S, 
uint8_t  L, 
uint16_t  numTaps, 
q15_t *  pCoeffs, 
q15_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q15 FIR interpolator. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 FIR interpolator structure. 
[in]Lupsample factor. 
[in]numTapsnumber of filter coefficients in the filter. 
[in]*pCoeffspoints to the filter coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if the filter length numTaps is not a multiple of the interpolation factor L.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ 
 The length of the filter numTaps must be a multiple of the interpolation factor L. 

+
pState points to the array of state variables. pState is of length (numTaps/L)+blockSize-1 words where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15(). 

+
+
Definition at line 68 of file arm_fir_interpolate_init_q15.c.

+
+

+

+
+

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void arm_fir_interpolate_q15 (const arm_fir_interpolate_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 FIR interpolator. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR interpolator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format. 

+
+
Definition at line 62 of file arm_fir_interpolate_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___lattice.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___lattice.html
new file mode 100644
index 0000000..0f28c3f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___lattice.html
@@ -0,0 +1,433 @@
+
+
+
+
+CMSIS DSP Software Library: Finite Impulse Response (FIR) Lattice Filters
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Lattice Filters

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pCoeffs, float32_t *pState)
void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, q31_t *pState)
void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, q15_t *pState)
void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+
Detailed Description

+
This set of functions implements Finite Impulse Response (FIR) lattice filters for Q15, Q31 and floating-point data types. Lattice filters are used in a variety of adaptive filter applications. The filter structure is feedforward and the net impulse response is finite length. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst point to input and output arrays containing blockSize values.

+
Algorithm: 

+FIRLattice.gif
+
Finite Impulse Response Lattice filter

+ The following difference equation is implemented: 
   
+    f0[n] = g0[n] = x[n]   
+    fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M   
+    gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M   
+    y[n] = fM[n]   
+ 
 

+
pCoeffs points to tha array of reflection coefficients of size numStages. Reflection Coefficients are stored in the following order. 

+
   
+    {k1, k2, ..., kM}   
+ 
 where M is number of stages 

+
pState points to a state array of size numStages. The state variables (g values) hold previous inputs and are stored in the following order. 
   
+    {g0[n], g1[n], g2[n] ...gM-1[n]}   
+ 
 The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: 
   
+arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};   
+arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};   
+arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};   
+ 
 

+
where numStages is the number of stages in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer. 

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR Lattice filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

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void arm_fir_lattice_init_f32 (arm_fir_lattice_instance_f32 *  S, 
uint16_t  numStages, 
float32_t *  pCoeffs, 
float32_t *  pState 
)

+

+

+
+
Initialization function for the floating-point FIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR lattice structure. 
[in]numStagesnumber of filter stages. 
[in]*pCoeffspoints to the coefficient buffer. The array is of length numStages. 
[in]*pStatepoints to the state buffer. The array is of length numStages. 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_fir_lattice_init_f32.c.

+
+

+

+
+

+

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void arm_fir_lattice_f32 (const arm_fir_lattice_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point FIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 121 of file arm_fir_lattice_f32.c.

+
+

+

+
+

+

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void arm_fir_lattice_init_q31 (arm_fir_lattice_instance_q31 *  S, 
uint16_t  numStages, 
q31_t *  pCoeffs, 
q31_t *  pState 
)

+

+

+
+
Initialization function for the Q31 FIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR lattice structure. 
[in]numStagesnumber of filter stages. 
[in]*pCoeffspoints to the coefficient buffer. The array is of length numStages. 
[in]*pStatepoints to the state buffer. The array is of length numStages. 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_fir_lattice_init_q31.c.

+
+

+

+
+

+

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void arm_fir_lattice_q31 (const arm_fir_lattice_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 FIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits. 

+
+
Definition at line 58 of file arm_fir_lattice_q31.c.

+
+

+

+
+

+

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void arm_fir_lattice_init_q15 (arm_fir_lattice_instance_q15 *  S, 
uint16_t  numStages, 
q15_t *  pCoeffs, 
q15_t *  pState 
)

+

+

+
+
Initialization function for the Q15 FIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR lattice structure. 
[in]numStagesnumber of filter stages. 
[in]*pCoeffspoints to the coefficient buffer. The array is of length numStages. 
[in]*pStatepoints to the state buffer. The array is of length numStages. 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_fir_lattice_init_q15.c.

+
+

+

+
+

+

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void arm_fir_lattice_q15 (const arm_fir_lattice_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 FIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 54 of file arm_fir_lattice_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___sparse.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___sparse.html
new file mode 100644
index 0000000..ec3ef54
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r___sparse.html
@@ -0,0 +1,674 @@
+
+
+
+
+CMSIS DSP Software Library: Finite Impulse Response (FIR) Sparse Filters
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Sparse Filters

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, float32_t *pScratchIn, uint32_t blockSize)
void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, uint32_t blockSize)
void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)
void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, uint32_t blockSize)
void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, q31_t *pScratchOut, uint32_t blockSize)

+
Detailed Description

+
This group of functions implements sparse FIR filters. Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero. Sparse filters are used for simulating reflections in communications and audio applications.

+
There are separate functions for Q7, Q15, Q31, and floating-point data types. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst points to input and output arrays respectively containing blockSize values.

+
Algorithm: 
The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients. This is in addition to the coefficient array b. The implementation essentially skips the multiplications by zero and leads to an efficient realization. 
  
+     y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]   
+ 
 

+

+FIRSparse.gif
+
Sparse FIR filter. b[n] represents the filter coefficients

+ 

+
pCoeffs points to a coefficient array of size numTaps; pTapDelay points to an array of nonzero indices and is also of size numTaps; pState points to a state array of size maxDelay + blockSize, where maxDelay is the largest offset value that is ever used in the pTapDelay array. Some of the processing functions also require temporary working buffers.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 4 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 4 different data type filter instance structures 
   
+arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ 
 

+

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the sparse FIR filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

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void arm_fir_sparse_init_f32 (arm_fir_sparse_instance_f32 *  S, 
uint16_t  numTaps, 
float32_t *  pCoeffs, 
float32_t *  pState, 
int32_t *  pTapDelay, 
uint16_t  maxDelay, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the floating-point sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of samples processed by the arm_fir_sparse_f32() function. 

+
+
Definition at line 65 of file arm_fir_sparse_init_f32.c.

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void arm_fir_sparse_f32 (arm_fir_sparse_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
float32_t *  pScratchIn, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none. 

+
+
Definition at line 113 of file arm_fir_sparse_f32.c.

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void arm_fir_sparse_init_q31 (arm_fir_sparse_instance_q31 *  S, 
uint16_t  numTaps, 
q31_t *  pCoeffs, 
q31_t *  pState, 
int32_t *  pTapDelay, 
uint16_t  maxDelay, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q31 sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of words processed by arm_fir_sparse_q31() function. 

+
+
Definition at line 64 of file arm_fir_sparse_init_q31.c.

+
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void arm_fir_sparse_q31 (arm_fir_sparse_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
q31_t *  pScratchIn, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The 1.31 x 1.31 multiplications are truncated to 2.30 format. This leads to loss of precision on the intermediate multiplications and provides only a single guard bit. If the accumulator result overflows, it wraps around rather than saturate. In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. 

+
+
Definition at line 58 of file arm_fir_sparse_q31.c.

+
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void arm_fir_sparse_init_q15 (arm_fir_sparse_instance_q15 *  S, 
uint16_t  numTaps, 
q15_t *  pCoeffs, 
q15_t *  pState, 
int32_t *  pTapDelay, 
uint16_t  maxDelay, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q15 sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of words processed by arm_fir_sparse_q15() function. 

+
+
Definition at line 65 of file arm_fir_sparse_init_q15.c.

+
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void arm_fir_sparse_q15 (arm_fir_sparse_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
q15_t *  pScratchIn, 
q31_t *  pScratchOut, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]*pScratchOutpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator. Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator. If the accumulator result overflows it will wrap around rather than saturate. After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format. In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. 

+
+
Definition at line 60 of file arm_fir_sparse_q15.c.

+
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void arm_fir_sparse_init_q7 (arm_fir_sparse_instance_q7 *  S, 
uint16_t  numTaps, 
q7_t *  pCoeffs, 
q7_t *  pState, 
int32_t *  pTapDelay, 
uint16_t  maxDelay, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q7 sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q7 sparse FIR structure. 
[in]numTapsnumber of nonzero coefficients in the filter. 
[in]*pCoeffspoints to the array of filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]*pTapDelaypoints to the array of offset times. 
[in]maxDelaymaximum offset time supported. 
[in]blockSizenumber of samples that will be processed per block. 

+  

+

+
Returns:
none

+
Description: 

+
pCoeffs holds the filter coefficients and has length numTaps. pState holds the filter's state variables and must be of length maxDelay + blockSize, where maxDelay is the maximum number of delay line values. blockSize is the number of samples processed by the arm_fir_sparse_q7() function. 

+
+
Definition at line 65 of file arm_fir_sparse_init_q7.c.

+
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void arm_fir_sparse_q7 (arm_fir_sparse_instance_q7 *  S, 
q7_t *  pSrc, 
q7_t *  pDst, 
q7_t *  pScratchIn, 
q31_t *  pScratchOut, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q7 sparse FIR filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q7 sparse FIR structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]*pScratchInpoints to a temporary buffer of size blockSize. 
[in]*pScratchOutpoints to a temporary buffer of size blockSize. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 32-bit internal accumulator. Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. The accumulator is then converted to 18.7 format by discarding the low 7 bits. Finally, the result is truncated to 1.7 format. 

+
+
Definition at line 65 of file arm_fir_sparse_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r__decimate.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r__decimate.html
new file mode 100644
index 0000000..99def24
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r__decimate.html
@@ -0,0 +1,610 @@
+
+
+
+
+CMSIS DSP Software Library: Finite Impulse Response (FIR) Decimator
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Finite Impulse Response (FIR) Decimator

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize)
void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize)
void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize)
void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+
Detailed Description

+
These functions combine an FIR filter together with a decimator. They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion. Conceptually, the functions are equivalent to the block diagram below: 

+

+FIRDecimator.gif
+
Components included in the FIR Decimator functions

+
 When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized cutoff frequency of 1/M in order to prevent aliasing distortion. The user of the function is responsible for providing the filter coefficients.

+
The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner. Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the samples output by the decimator are computed. The functions operate on blocks of input and output data. pSrc points to an array of blockSize input values and pDst points to an array of blockSize/M output values. In order to have an integer number of output samples blockSize must always be a multiple of the decimation factor M.

+
The library provides separate functions for Q15, Q31 and floating-point data types.

+
Algorithm: 
The FIR portion of the algorithm uses the standard form filter: 
   
+    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ 
 where, b[n] are the filter coefficients. 

+
The pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 

+
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the order: 

+
   
+    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ 
 The state variables are updated after each block of data is processed, the coefficients are untouched.

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable array should be allocated separately. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+
  • Checks to make sure that the size of the input is a multiple of the decimation factor.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. The code below statically initializes each of the 3 different data type filter instance structures 
   
+arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};   
+arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};   
+arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};   
+ 
 where M is the decimation factor; numTaps is the number of filter coefficients in the filter; pCoeffs is the address of the coefficient buffer; pState is the address of the state buffer. Be sure to set the values in the state buffer to zeros when doing static initialization.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the FIR decimate filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

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arm_status arm_fir_decimate_init_f32 (arm_fir_decimate_instance_f32 *  S, 
uint16_t  numTaps, 
uint8_t  M, 
float32_t *  pCoeffs, 
float32_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the floating-point FIR decimator. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point FIR decimator structure. 
[in]numTapsnumber of coefficients in the filter. 
[in]Mdecimation factor. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if blockSize is not a multiple of M.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32(). M is the decimation factor. 

+
+
Definition at line 67 of file arm_fir_decimate_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
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+          
+        
+      
void arm_fir_decimate_f32 (const arm_fir_decimate_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point FIR decimator. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none. 

+
+
Definition at line 132 of file arm_fir_decimate_f32.c.

+
+

+

+
+

+

+      
+        
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+        
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+          
+          
+        
+      
arm_status arm_fir_decimate_init_q31 (arm_fir_decimate_instance_q31 *  S, 
uint16_t  numTaps, 
uint8_t  M, 
q31_t *  pCoeffs, 
q31_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q31 FIR decimator. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 FIR decimator structure. 
[in]numTapsnumber of coefficients in the filter. 
[in]Mdecimation factor. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if blockSize is not a multiple of M.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31(). M is the decimation factor. 

+
+
Definition at line 67 of file arm_fir_decimate_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
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+        
+        
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+          
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+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_decimate_q31 (const arm_fir_decimate_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 FIR decimator. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.

+
Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 64 of file arm_fir_decimate_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
+          
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_decimate_fast_q31 (arm_fir_decimate_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none

+
Scaling and Overflow Behavior:

+
This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are added to a 2.30 accumulator. Finally, the accumulator is saturated and converted to a 1.31 result. The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).

+
Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_decimate_init_q31() to initialize the filter structure. 

+
+
Definition at line 65 of file arm_fir_decimate_fast_q31.c.

+
+

+

+
+

+

+      
+        
+          
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+          
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+        
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+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_fir_decimate_init_q15 (arm_fir_decimate_instance_q15 *  S, 
uint16_t  numTaps, 
uint8_t  M, 
q15_t *  pCoeffs, 
q15_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q15 FIR decimator. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 FIR decimator structure. 
[in]numTapsnumber of coefficients in the filter. 
[in]Mdecimation factor. 
[in]*pCoeffspoints to the filter coefficients. 
[in]*pStatepoints to the state buffer. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if blockSize is not a multiple of M.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to the array of state variables. pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples to the call arm_fir_decimate_q15(). M is the decimation factor. 

+
+
Definition at line 68 of file arm_fir_decimate_init_q15.c.

+
+

+

+
+

+

+      
+        
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+          
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+          
+        
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+          
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+          
+          
+          
+        
+      
void arm_fir_decimate_q15 (const arm_fir_decimate_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 FIR decimator. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the location where the output result is written. 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.

+
Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 65 of file arm_fir_decimate_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
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+        
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+          
+          
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+          
+        
+        
+          
+          
+          
+        
+      
void arm_fir_decimate_fast_q15 (const arm_fir_decimate_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 FIR decimator structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data 
[in]blockSizenumber of input samples to process per call. 

+  

+

+
Returns:
none

+
Scaling and Overflow Behavior: 

+
This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2). The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.

+
Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. Use the function arm_fir_decimate_init_q15() to initialize the filter structure. 

+
+
Definition at line 63 of file arm_fir_decimate_fast_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r_l_p_f.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r_l_p_f.html
new file mode 100644
index 0000000..8d3f321
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___f_i_r_l_p_f.html
@@ -0,0 +1,121 @@
+
+
+
+
+CMSIS DSP Software Library: FIR Lowpass Filter Example
+
+
+
+
+
+
+
+
+
+

+  

+
FIR Lowpass Filter Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Removes high frequency signal components from the input using an FIR lowpass filter. The example demonstrates how to configure an FIR filter and then pass data through it in a block-by-block fashion. 

+FIRLPF_signalflow.gif
+

+

+
Algorithm:

+
The input signal is a sum of two sine waves: 1 kHz and 15 kHz. This is processed by an FIR lowpass filter with cutoff frequency 6 kHz. The lowpass filter eliminates the 15 kHz signal leaving only the 1 kHz sine wave at the output. 

+
The lowpass filter was designed using MATLAB with a sample rate of 48 kHz and a length of 29 points. The MATLAB code to generate the filter coefficients is shown below: 
+     h = fir1(28, 6/24);
+ 
 The first argument is the "order" of the filter and is always one less than the desired length. The second argument is the normalized cutoff frequency. This is in the range 0 (DC) to 1.0 (Nyquist). A 6 kHz cutoff with a Nyquist frequency of 24 kHz lies at a normalized frequency of 6/24 = 0.25. The CMSIS FIR filter function requires the coefficients to be in time reversed order. 
+     fliplr(h)
+ 
 The resulting filter coefficients and are shown below. Note that the filter is symmetric (a property of linear phase FIR filters) and the point of symmetry is sample 14. Thus the filter will have a delay of 14 samples for all frequencies. 

+

+FIRLPF_coeffs.gif
+

+ 

+
The frequency response of the filter is shown next. The passband gain of the filter is 1.0 and it reaches 0.5 at the cutoff frequency 6 kHz. 

+

+FIRLPF_response.gif
+

+ 

+
The input signal is shown below. The left hand side shows the signal in the time domain while the right hand side is a frequency domain representation. The two sine wave components can be clearly seen. 

+

+FIRLPF_input.gif
+

+ 

+
The output of the filter is shown below. The 15 kHz component has been eliminated. 

+

+FIRLPF_output.gif
+

+

+
Variables Description:

+
    
+
  • testInput_f32_1kHz_15kHz points to the input data 
    • 
+
  • refOutput points to the reference output data 
    • 
+
  • testOutput points to the test output data 
    • 
+
  • firStateF32 points to state buffer 
    • 
+
  • firCoeffs32 points to coefficient buffer 
    • 
+
  • blockSize number of samples processed at a time 
    • 
+
  • numBlocks number of frames
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_fir_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___fill.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___fill.html
new file mode 100644
index 0000000..cf67b44
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___fill.html
@@ -0,0 +1,271 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Fill
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Fill

+
+[Support Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_fill_f32 (float32_t value, float32_t *pDst, uint32_t blockSize)
void arm_fill_q31 (q31_t value, q31_t *pDst, uint32_t blockSize)
void arm_fill_q15 (q15_t value, q15_t *pDst, uint32_t blockSize)
void arm_fill_q7 (q7_t value, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Fills the destination vector with a constant value.

+
   
+ 	pDst[n] = value;   0 <= n < blockSize.   
+ 
There are separate functions for floating point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
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+        
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+        
+      
void arm_fill_f32 (float32_t  value, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Fills a constant value into a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_convolution_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 66 of file arm_fill_f32.c.

+
+

+

+
+

+

+      
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+          
+        
+      
void arm_fill_q31 (q31_t  value, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Fills a constant value into a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_fill_q31.c.

+
+

+

+
+

+

+      
+        
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+          
+          
+        
+      
void arm_fill_q15 (q15_t  value, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Fills a constant value into a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_fill_q15.c.

+
+

+

+
+

+

+      
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+          
+          
+        
+      
void arm_fill_q7 (q7_t  value, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Fills a constant value into a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]valueinput value to be filled 
[out]*pDstpoints to output vector 
[in]blockSizelength of the output vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_fill_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___frequency_bin.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___frequency_bin.html
new file mode 100644
index 0000000..63e11d8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___frequency_bin.html
@@ -0,0 +1,108 @@
+
+
+
+
+CMSIS DSP Software Library: Frequency Bin Example
+
+
+
+
+
+
+
+
+
+

+  

+
Frequency Bin Example

+
+[Examples]
+
  

+

+

+
+

+
Description

+
Demonstrates the calculation of the maximum energy bin in the frequency domain of the input signal with the use of Complex FFT, Complex Magnitude, and Maximum functions.

+
Algorithm:

+
The input test signal contains a 10 kHz signal with uniformly distributed white noise. Calculating the FFT of the input signal will give us the maximum energy of the bin corresponding to the input frequency of 10 kHz.

+
Block Diagram:

+FFTBin.gif
+
Block Diagram

+ 

+
The figure below shows the time domain signal of 10 kHz signal with uniformly distributed white noise, and the next figure shows the input in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal. 

+

+FFTBinInput.gif
+
Input signal in Time domain

+ 

+FFTBinOutput.gif
+
Input signal in Frequency domain

+ 

+
Variables Description:

+
    
+
  • testInput_f32_10khz points to the input data 
    • 
+
  • testOutput points to the output data 
    • 
+
  • fftSize length of FFT 
    • 
+
  • ifftFlag flag for the selection of CFFT/CIFFT 
    • 
+
  • doBitReverse Flag for selection of normal order or bit reversed order 
    • 
+
  • refIndex reference index value at which maximum energy of bin ocuurs 
    • 
+
  • testIndex calculated index value at which maximum energy of bin ocuurs
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_fft_bin_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___g_e_q5_band.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___g_e_q5_band.html
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+
+
+
+
+CMSIS DSP Software Library: Graphic Audio Equalizer Example
+
+
+
+
+
+
+
+
+
+

+  

+
Graphic Audio Equalizer Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
This example demonstrates how a 5-band graphic equalizer can be constructed using the Biquad cascade functions. A graphic equalizer is used in audio applications to vary the tonal quality of the audio.

+
Block Diagram:

+
The design is based on a cascade of 5 filter sections. 

+GEQ_signalflow.gif
+

+ Each filter section is 4th order and consists of a cascade of two Biquads. Each filter has a nominal gain of 0 dB (1.0 in linear units) and boosts or cuts signals within a specific frequency range. The edge frequencies between the 5 bands are 100, 500, 2000, and 6000 Hz. Each band has an adjustable boost or cut in the range of +/- 9 dB. For example, the band that extends from 500 to 2000 Hz has the response shown below: 

+

+GEQ_bandresponse.gif
+

+ 

+
With 1 dB steps, each filter has a total of 19 different settings. The filter coefficients for all possible 19 settings were precomputed in MATLAB and stored in a table. With 5 different tables, there are a total of 5 x 19 = 95 different 4th order filters. All 95 responses are shown below: 

+

+GEQ_allbandresponse.gif
+

+ 

+
Each 4th order filter has 10 coefficents for a grand total of 950 different filter coefficients that must be tabulated. The input and output data is in Q31 format. For better noise performance, the two low frequency bands are implemented using the high precision 32x64-bit Biquad filters. The remaining 3 high frequency bands use standard 32x32-bit Biquad filters. The input signal used in the example is a logarithmic chirp. 

+

+GEQ_inputchirp.gif
+

+ 

+
The array bandGains specifies the gain in dB to apply in each band. For example, if bandGains={0, -3, 6, 4, -6}; then the output signal will be: 

+

+GEQ_outputchirp.gif
+

+ 

+

+
Note:
The output chirp signal follows the gain or boost of each band. 

+

+
Variables Description:

+
    
+
  • testInput_f32 points to the input data 
    • 
+
  • testRefOutput_f32 points to the reference output data 
    • 
+
  • testOutput points to the test output data 
    • 
+
  • inputQ31 temporary input buffer 
    • 
+
  • outputQ31 temporary output buffer 
    • 
+
  • biquadStateBand1Q31 points to state buffer for band1 
    • 
+
  • biquadStateBand2Q31 points to state buffer for band2 
    • 
+
  • biquadStateBand3Q31 points to state buffer for band3 
    • 
+
  • biquadStateBand4Q31 points to state buffer for band4 
    • 
+
  • biquadStateBand5Q31 points to state buffer for band5 
    • 
+
  • coeffTable points to coefficient buffer for all bands 
    • 
+
  • gainDB gain buffer which has gains applied for all the bands
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_graphic_equalizer_example_q31.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___i_i_r___lattice.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___i_i_r___lattice.html
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+CMSIS DSP Software Library: Infinite Impulse Response (IIR) Lattice Filters
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Infinite Impulse Response (IIR) Lattice Filters

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *S, uint16_t numStages, float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, uint32_t blockSize)
void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize)
void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize)
void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize)

+
Detailed Description

+
This set of functions implements lattice filters for Q15, Q31 and floating-point data types. Lattice filters are used in a variety of adaptive filter applications. The filter structure has feedforward and feedback components and the net impulse response is infinite length. The functions operate on blocks of input and output data and each call to the function processes blockSize samples through the filter. pSrc and pDst point to input and output arrays containing blockSize values.

+
Algorithm: 

+IIRLattice.gif
+
Infinite Impulse Response Lattice filter

+ 
   
+    fN(n)   =  x(n)   
+    fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ...1   
+    gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1   
+    y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)   
+ 
 

+
pkCoeffs points to array of reflection coefficients of size numStages. Reflection coefficients are stored in time-reversed order. 

+
   
+    {kN, kN-1, ....k1}   
+ 
 pvCoeffs points to the array of ladder coefficients of size (numStages+1). Ladder coefficients are stored in time-reversed order. 

+
   
+    {vN, vN-1, ...v0}   
+ 
 pState points to a state array of size numStages + blockSize. The state variables shown in the figure above (the g values) are stored in the pState array. The state variables are updated after each block of data is processed; the coefficients are untouched. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter. Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: 
   
+arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+ 
 

+
where numStages is the number of stages in the filter; pState points to the state buffer array; pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients. 

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the IIR lattice filter functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
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void arm_iir_lattice_init_f32 (arm_iir_lattice_instance_f32 *  S, 
uint16_t  numStages, 
float32_t *  pkCoeffs, 
float32_t *  pvCoeffs, 
float32_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the floating-point IIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point IIR lattice structure. 
[in]numStagesnumber of stages in the filter. 
[in]*pkCoeffspoints to the reflection coefficient buffer. The array is of length numStages. 
[in]*pvCoeffspoints to the ladder coefficient buffer. The array is of length numStages+1. 
[in]*pStatepoints to the state buffer. The array is of length numStages+blockSize. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 55 of file arm_iir_lattice_init_f32.c.

+
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void arm_iir_lattice_f32 (const arm_iir_lattice_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the floating-point IIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point IIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 120 of file arm_iir_lattice_f32.c.

+
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void arm_iir_lattice_init_q31 (arm_iir_lattice_instance_q31 *  S, 
uint16_t  numStages, 
q31_t *  pkCoeffs, 
q31_t *  pvCoeffs, 
q31_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q31 IIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 IIR lattice structure. 
[in]numStagesnumber of stages in the filter. 
[in]*pkCoeffspoints to the reflection coefficient buffer. The array is of length numStages. 
[in]*pvCoeffspoints to the ladder coefficient buffer. The array is of length numStages+1. 
[in]*pStatepoints to the state buffer. The array is of length numStages+blockSize. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 55 of file arm_iir_lattice_init_q31.c.

+
+

+

+
+

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void arm_iir_lattice_q31 (const arm_iir_lattice_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q31 IIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 IIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits. After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format. 

+
+
Definition at line 62 of file arm_iir_lattice_q31.c.

+
+

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void arm_iir_lattice_init_q15 (arm_iir_lattice_instance_q15 *  S, 
uint16_t  numStages, 
q15_t *  pkCoeffs, 
q15_t *  pvCoeffs, 
q15_t *  pState, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for the Q15 IIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 IIR lattice structure. 
[in]numStagesnumber of stages in the filter. 
[in]*pkCoeffspoints to reflection coefficient buffer. The array is of length numStages. 
[in]*pvCoeffspoints to ladder coefficient buffer. The array is of length numStages+1. 
[in]*pStatepoints to state buffer. The array is of length numStages+blockSize. 
[in]blockSizenumber of samples to process per call. 

+  

+

+
Returns:
none. 

+
+
Definition at line 55 of file arm_iir_lattice_init_q15.c.

+
+

+

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void arm_iir_lattice_q15 (const arm_iir_lattice_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for the Q15 IIR lattice filter. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 IIR lattice structure. 
[in]*pSrcpoints to the block of input data. 
[out]*pDstpoints to the block of output data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format. 

+
+
Definition at line 63 of file arm_iir_lattice_q15.c.

+
+

+

+

+
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+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
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+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___l_m_s.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___l_m_s.html
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+
+
+
+
+CMSIS DSP Software Library: Least Mean Square (LMS) Filters
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Least Mean Square (LMS) Filters

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_lms_init_f32 (arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
void arm_lms_f32 (const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
void arm_lms_init_q31 (arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint32_t postShift)
void arm_lms_q31 (const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
void arm_lms_init_q15 (arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint32_t postShift)
void arm_lms_q15 (const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)

+
Detailed Description

+
LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions. LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal. Adaptive filters are often used in communication systems, equalizers, and noise removal. The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types. The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.

+
An LMS filter consists of two components as shown below. The first component is a standard transversal or FIR filter. The second component is a coefficient update mechanism. The LMS filter has two input signals. The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. This "error signal" tends towards zero as the filter adapts. The LMS processing functions accept the input and reference input signals and generate the filter output and error signal. 

+

+LMS.gif
+
Internal structure of the Least Mean Square filter

+
The functions operate on blocks of data and each call to the function processes blockSize samples through the filter. pSrc points to input signal, pRef points to reference signal, pOut points to output signal and pErr points to error signal. All arrays contain blockSize values.

+
The functions operate on a block-by-block basis. Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. The convergence of the LMS filter is slower compared to the normalized LMS algorithm.

+
Algorithm: 
The output signal y[n] is computed by a standard FIR filter: 
   
+     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ 

+
The error signal equals the difference between the reference signal d[n] and the filter output: 
   
+     e[n] = d[n] - y[n].   
+ 

+
After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis: 
   
+     b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1   
+ 
 where mu is the step size and controls the rate of coefficient convergence. 

+
In the APIs, pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 

+
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the order: 

+
   
+    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ 
 

+
Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, to be avoided and yields a significant speed improvement. The state variables are updated after each block of data is processed. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter and coefficient and state arrays cannot be shared among instances. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer. 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Set the values in the state buffer to zeros before static initialization. The code below statically initializes each of the 3 different data type filter instance structures 
   
+    arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};   
+    arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};   
+    arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};   
+ 
 where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.

+
Fixed-Point Behavior: 
Care must be taken when using the Q15 and Q31 versions of the LMS filter. The following issues must be considered:
    
+
  • Scaling of coefficients
    • 
+
  • Overflow and saturation
    • 
+

+

+
Scaling of Coefficients: 
Filter coefficients are represented as fractional values and coefficients are restricted to lie in the range [-1 +1). The fixed-point functions have an additional scaling parameter postShift. At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. This essentially scales the filter coefficients by 2^postShift and allows the filter coefficients to exceed the range [+1 -1). The value of postShift is set by the user based on the expected gain through the system being modeled.

+
Overflow and Saturation: 
Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are described separately as part of the function specific documentation below. 

+
Function Documentation

+
+

+

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+      
void arm_lms_init_f32 (arm_lms_instance_f32 *  S, 
uint16_t  numTaps, 
float32_t *  pCoeffs, 
float32_t *  pState, 
float32_t  mu, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for floating-point LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to the coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32(). 

+
+
Definition at line 61 of file arm_lms_init_f32.c.

+
+

+

+
+

+

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+        
+      
void arm_lms_f32 (const arm_lms_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pRef, 
float32_t *  pOut, 
float32_t *  pErr, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for floating-point LMS filter. 

+
This function operates on floating-point data types.

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
+
Definition at line 170 of file arm_lms_f32.c.

+
+

+

+
+

+

+      
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+      
void arm_lms_init_q31 (arm_lms_instance_q31 *  S, 
uint16_t  numTaps, 
q31_t *  pCoeffs, 
q31_t *  pState, 
q31_t  mu, 
uint32_t  blockSize, 
uint32_t  postShift 
)

+

+

+
+
Initialization function for Q31 LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 

+  

+

+
Returns:
none.

+
Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_q31(). 

+
+
Definition at line 66 of file arm_lms_init_q31.c.

+
+

+

+
+

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+          
+          
+        
+      
void arm_lms_q31 (const arm_lms_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pRef, 
q31_t *  pOut, 
q31_t *  pErr, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for Q31 LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clips. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. The reference signal should not be scaled down. After all multiply-accumulates are performed, the 2.62 accumulator is shifted and saturated to 1.31 format to yield the final result. The output signal and error signal are in 1.31 format.

+
In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 

+
+
Definition at line 69 of file arm_lms_q31.c.

+
+

+

+
+

+

+      
+        
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+        
+      
void arm_lms_init_q15 (arm_lms_instance_q15 *  S, 
uint16_t  numTaps, 
q15_t *  pCoeffs, 
q15_t *  pState, 
q15_t  mu, 
uint32_t  blockSize, 
uint32_t  postShift 
)

+

+

+
+
Initialization function for the Q15 LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to the coefficient buffer. 
[in]*pStatepoints to the state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 

+  

+

+
Returns:
none.

+
Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to the array of state variables and size of array is numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_q15(). 

+
+
Definition at line 66 of file arm_lms_init_q15.c.

+
+

+

+
+

+

+      
+        
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+          
+          
+        
+      
void arm_lms_q15 (const arm_lms_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pRef, 
q15_t *  pOut, 
q15_t *  pErr, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for Q15 LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.

+
In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 

+
+
Definition at line 66 of file arm_lms_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___l_m_s___n_o_r_m.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___l_m_s___n_o_r_m.html
new file mode 100644
index 0000000..d1f6e15
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___l_m_s___n_o_r_m.html
@@ -0,0 +1,560 @@
+
+
+
+
+CMSIS DSP Software Library: Normalized LMS Filters
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Normalized LMS Filters

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, float32_t mu, uint32_t blockSize)
void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, float32_t *pErr, uint32_t blockSize)
void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift)
void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, uint32_t blockSize)
void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift)
void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, uint32_t blockSize)

+
Detailed Description

+
This set of functions implements a commonly used adaptive filter. It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization factor which increases the adaptation rate of the filter. The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.

+
A normalized least mean square (NLMS) filter consists of two components as shown below. The first component is a standard transversal or FIR filter. The second component is a coefficient update mechanism. The NLMS filter has two input signals. The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. This "error signal" tends towards zero as the filter adapts. The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal. 

+

+LMS.gif
+
Internal structure of the NLMS adaptive filter

+
The functions operate on blocks of data and each call to the function processes blockSize samples through the filter. pSrc points to input signal, pRef points to reference signal, pOut points to output signal and pErr points to error signal. All arrays contain blockSize values.

+
The functions operate on a block-by-block basis. Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. The convergence of the LMS filter is slower compared to the normalized LMS algorithm.

+
Algorithm: 
The output signal y[n] is computed by a standard FIR filter: 
   
+     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ 

+
The error signal equals the difference between the reference signal d[n] and the filter output: 
   
+     e[n] = d[n] - y[n].   
+ 

+
After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated: 
   
+    E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.   
+ 
 The filter coefficients b[k] are then updated on a sample-by-sample basis: 
   
+     b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1   
+ 
 where mu is the step size and controls the rate of coefficient convergence. 

+
In the APIs, pCoeffs points to a coefficient array of size numTaps. Coefficients are stored in time reversed order. 

+
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 

+
pState points to a state array of size numTaps + blockSize - 1. Samples in the state buffer are stored in the order: 

+
   
+    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ 
 

+
Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, to be avoided and yields a significant speed improvement. The state variables are updated after each block of data is processed. 

+
Instance Structure 
The coefficients and state variables for a filter are stored together in an instance data structure. A separate instance structure must be defined for each filter and coefficient and state arrays cannot be shared among instances. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Zeros out the values in the state buffer. 
    • 
+

+

+
Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. 

+
Fixed-Point Behavior: 
Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter. The following issues must be considered:
    
+
  • Scaling of coefficients
    • 
+
  • Overflow and saturation
    • 
+

+

+
Scaling of Coefficients: 
Filter coefficients are represented as fractional values and coefficients are restricted to lie in the range [-1 +1). The fixed-point functions have an additional scaling parameter postShift. At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. This essentially scales the filter coefficients by 2^postShift and allows the filter coefficients to exceed the range [+1 -1). The value of postShift is set by the user based on the expected gain through the system being modeled.

+
Overflow and Saturation: 
Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are described separately as part of the function specific documentation below. 

+
Function Documentation

+
+

+

+      
+        
+          
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void arm_lms_norm_init_f32 (arm_lms_norm_instance_f32 *  S, 
uint16_t  numTaps, 
float32_t *  pCoeffs, 
float32_t *  pState, 
float32_t  mu, 
uint32_t  blockSize 
)

+

+

+
+
Initialization function for floating-point normalized LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Description: 
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_norm_f32(). 

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 64 of file arm_lms_norm_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
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+          
+          
+        
+      
void arm_lms_norm_f32 (arm_lms_norm_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pRef, 
float32_t *  pOut, 
float32_t *  pErr, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for floating-point normalized LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point normalized LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none. 

+
Examples: 
arm_signal_converge_example_f32.c.

+

+
Definition at line 160 of file arm_lms_norm_f32.c.

+
+

+

+
+

+

+      
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+      
void arm_lms_norm_init_q31 (arm_lms_norm_instance_q31 *  S, 
uint16_t  numTaps, 
q31_t *  pCoeffs, 
q31_t *  pState, 
q31_t  mu, 
uint32_t  blockSize, 
uint8_t  postShift 
)

+

+

+
+
Initialization function for Q31 normalized LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 normalized LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 

+  

+

+
Returns:
none.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_norm_q31(). 

+
+
Definition at line 63 of file arm_lms_norm_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
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+        
+      
void arm_lms_norm_q31 (arm_lms_norm_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pRef, 
q31_t *  pOut, 
q31_t *  pErr, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for Q31 normalized LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 normalized LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. The reference signal should not be scaled down. After all multiply-accumulates are performed, the 2.62 accumulator is shifted and saturated to 1.31 format to yield the final result. The output signal and error signal are in 1.31 format.

+
In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 

+
+
Definition at line 72 of file arm_lms_norm_q31.c.

+
+

+

+
+

+

+      
+        
+          
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void arm_lms_norm_init_q15 (arm_lms_norm_instance_q15 *  S, 
uint16_t  numTaps, 
q15_t *  pCoeffs, 
q15_t *  pState, 
q15_t  mu, 
uint32_t  blockSize, 
uint8_t  postShift 
)

+

+

+
+
Initialization function for Q15 normalized LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 normalized LMS filter structure. 
[in]numTapsnumber of filter coefficients. 
[in]*pCoeffspoints to coefficient buffer. 
[in]*pStatepoints to state buffer. 
[in]mustep size that controls filter coefficient updates. 
[in]blockSizenumber of samples to process. 
[in]postShiftbit shift applied to coefficients. 

+  

+

+
Returns:
none.

+
Description: 

+
pCoeffs points to the array of filter coefficients stored in time reversed order: 
   
+    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ 
 The initial filter coefficients serve as a starting point for the adaptive filter. pState points to the array of state variables and size of array is numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_norm_q15(). 

+
+
Definition at line 64 of file arm_lms_norm_init_q15.c.

+
+

+

+
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void arm_lms_norm_q15 (arm_lms_norm_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pRef, 
q15_t *  pOut, 
q15_t *  pErr, 
uint32_t  blockSize 
)

+

+

+
+
Processing function for Q15 normalized LMS filter. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 normalized LMS filter structure. 
[in]*pSrcpoints to the block of input data. 
[in]*pRefpoints to the block of reference data. 
[out]*pOutpoints to the block of output data. 
[out]*pErrpoints to the block of error data. 
[in]blockSizenumber of samples to process. 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format.

+
In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted. 

+
+
Definition at line 71 of file arm_lms_norm_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___linear_interp_example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___linear_interp_example.html
new file mode 100644
index 0000000..c3e0937
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___linear_interp_example.html
@@ -0,0 +1,100 @@
+
+
+
+
+CMSIS DSP Software Library: Linear Interpolate Example
+
+
+
+
+
+
+
+
+
+

+  

+
Linear Interpolate Example

+
+[Examples]
+
  

+

+

+
+

+
 CMSIS DSP Software Library -- Linear Interpolate Example 

+
 Description  This example demonstrates usage of linear interpolate modules and fast math modules. Method 1 uses fast math sine function to calculate sine values using cubic interpolation and method 2 uses linear interpolation function and results are compared to reference output. Example shows linear interpolation function can be used to get higher precision compared to fast math sin calculation.

+
Block Diagram:

+

+linearInterpExampleMethod1.gif
+
Method 1: Sine caluclation using fast math

+ 

+

+linearInterpExampleMethod2.gif
+
Method 2: Sine caluclation using interpolation function

+ 

+
Variables Description:

+
    
+
  • testInputSin_f32 points to the input values for sine calculation 
    • 
+
  • testRefSinOutput32_f32 points to the reference values caculated from sin() matlab function 
    • 
+
  • testOutput points to output buffer calculation from cubic interpolation 
    • 
+
  • testLinIntOutput points to output buffer calculation from linear interpolation 
    • 
+
  • snr1 Signal to noise ratio for reference and cubic interpolation output 
    • 
+
  • snr2 Signal to noise ratio for reference and linear interpolation output
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_linear_interp_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___linear_interpolate.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___linear_interpolate.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___linear_interpolate.html
@@ -0,0 +1,276 @@
+
+
+
+
+CMSIS DSP Software Library: Linear Interpolation
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Linear Interpolation

+
+[Interpolation Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
static __INLINE float32_t arm_linear_interp_f32 (arm_linear_interp_instance_f32 *S, float32_t x)
static __INLINE q31_t arm_linear_interp_q31 (q31_t *pYData, q31_t x, uint32_t nValues)
static __INLINE q15_t arm_linear_interp_q15 (q15_t *pYData, q31_t x, uint32_t nValues)
static __INLINE q7_t arm_linear_interp_q7 (q7_t *pYData, q31_t x, uint32_t nValues)

+
Detailed Description

+
Linear interpolation is a method of curve fitting using linear polynomials. Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line

+

+LinearInterp.gif
+
Linear interpolation

+ 

+
A Linear Interpolate function calculates an output value(y), for the input(x) using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)

+
Algorithm:
+       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+       where x0, x1 are nearest values of input x
+             y0, y1 are nearest values to output y
+ 

+
This set of functions implements Linear interpolation process for Q7, Q15, Q31, and floating-point data types. The functions operate on a single sample of data and each call to the function returns a single processed value. S points to an instance of the Linear Interpolate function data structure. x is the input sample value. The functions returns the output value.

+
if x is outside of the table boundary, Linear interpolation returns first value of the table if x is below input range and returns last value of table if x is above range. 

+
Function Documentation

+
+

+

+      
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static __INLINE float32_t arm_linear_interp_f32 (arm_linear_interp_instance_f32 *  S, 
float32_t  x 
) [static]

+

+

+
+
Process function for the floating-point Linear Interpolation Function. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Sis an instance of the floating-point Linear Interpolation structure 
[in]xinput sample to process 

+  

+

+
Returns:
y processed output sample. 

+
Examples: 
arm_linear_interp_example_f32.c.

+

+
Definition at line 5377 of file arm_math.h.

+
+

+

+
+

+

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static __INLINE q31_t arm_linear_interp_q31 (q31_t *  pYData, 
q31_t  x, 
uint32_t  nValues 
) [static]

+

+

+
+
Process function for the Q31 Linear Interpolation Function. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pYDatapointer to Q31 Linear Interpolation table 
[in]xinput sample to process 
[in]nValuesnumber of table values 

+  

+

+
Returns:
y processed output sample.

+
Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. This function can support maximum of table size 2^12. 

+
+
Definition at line 5436 of file arm_math.h.

+
+

+

+
+

+

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static __INLINE q15_t arm_linear_interp_q15 (q15_t *  pYData, 
q31_t  x, 
uint32_t  nValues 
) [static]

+

+

+
+
Process function for the Q15 Linear Interpolation Function. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pYDatapointer to Q15 Linear Interpolation table 
[in]xinput sample to process 
[in]nValuesnumber of table values 

+  

+

+
Returns:
y processed output sample.

+
Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. This function can support maximum of table size 2^12. 

+
+
Definition at line 5496 of file arm_math.h.

+
+

+

+
+

+

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static __INLINE q7_t arm_linear_interp_q7 (q7_t *  pYData, 
q31_t  x, 
uint32_t  nValues 
) [static]

+

+

+
+
Process function for the Q7 Linear Interpolation Function. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pYDatapointer to Q7 Linear Interpolation table 
[in]xinput sample to process 
[in]nValuesnumber of table values 

+  

+

+
Returns:
y processed output sample.

+
Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. This function can support maximum of table size 2^12. 

+
+
Definition at line 5553 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_add.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_add.html
new file mode 100644
index 0000000..6f28611
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_add.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Addition
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Addition

+
+[Matrix Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)

+
Detailed Description

+
Adds two matrices. 

+

+MatrixAddition.gif
+
Addition of two 3 x 3 matrices

+
The functions check to make sure that pSrcA, pSrcB, and pDst have the same number of rows and columns. 

+
Function Documentation

+
+

+

+      
+        
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+          
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arm_status arm_mat_add_f32 (const arm_matrix_instance_f32 *  pSrcA, 
const arm_matrix_instance_f32 *  pSrcB, 
arm_matrix_instance_f32 *  pDst 
)

+

+

+
+
Floating-point matrix addition. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
Definition at line 68 of file arm_mat_add_f32.c.

+
+

+

+
+

+

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arm_status arm_mat_add_q31 (const arm_matrix_instance_q31 *  pSrcA, 
const arm_matrix_instance_q31 *  pSrcB, 
arm_matrix_instance_q31 *  pDst 
)

+

+

+
+
Q31 matrix addition. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 61 of file arm_mat_add_q31.c.

+
+

+

+
+

+

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arm_status arm_mat_add_q15 (const arm_matrix_instance_q15 *  pSrcA, 
const arm_matrix_instance_q15 *  pSrcB, 
arm_matrix_instance_q15 *  pDst 
)

+

+

+
+
Q15 matrix addition. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 61 of file arm_mat_add_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_example.html
new file mode 100644
index 0000000..ca3c0ac
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_example.html
@@ -0,0 +1,100 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Example
+
+
+
+
+
+
+
+
+
+

+  

+
Matrix Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse functions to apply least squares fitting to input data. Least squares fitting is the procedure for finding the best-fitting curve that minimizes the sum of the squares of the offsets (least square error) from a given set of data.

+
Algorithm:

+
The linear combination of parameters considered is as follows: 

+
A * X = B, where X is the unknown value and can be estimated from A & B. 

+
The least squares estimate X is given by the following equation: 

+
X = Inverse(AT * A) * AT * B

+
Block Diagram:

+

+matrixExample.gif
+

+

+
Variables Description:

+
    
+
  • A_f32 input matrix in the linear combination equation 
    • 
+
  • B_f32 output matrix in the linear combination equation 
    • 
+
  • X_f32 unknown matrix estimated using A_f32 & B_f32 matrices
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_matrix_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_init.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_init.html
new file mode 100644
index 0000000..044685d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_init.html
@@ -0,0 +1,242 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Initialization
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Initialization

+
+[Matrix Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_mat_init_f32 (arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, float32_t *pData)
void arm_mat_init_q31 (arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData)
void arm_mat_init_q15 (arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData)

+
Detailed Description

+
Initializes the underlying matrix data structure. The functions set the numRows, numCols, and pData fields of the matrix data structure. 

+
Function Documentation

+
+

+

+      
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+      
void arm_mat_init_f32 (arm_matrix_instance_f32 *  S, 
uint16_t  nRows, 
uint16_t  nColumns, 
float32_t *  pData 
)

+

+

+
+
Floating-point matrix initialization. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point matrix structure. 
[in]nRowsnumber of rows in the matrix. 
[in]nColumnsnumber of columns in the matrix. 
[in]*pDatapoints to the matrix data array. 

+  

+

+
Returns:
none 

+
Examples: 
arm_class_marks_example_f32.c, and arm_matrix_example_f32.c.

+

+
Definition at line 65 of file arm_mat_init_f32.c.

+
+

+

+
+

+

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void arm_mat_init_q31 (arm_matrix_instance_q31 *  S, 
uint16_t  nRows, 
uint16_t  nColumns, 
q31_t *  pData 
)

+

+

+
+
Q31 matrix initialization. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point matrix structure. 
[in]nRowsnumber of rows in the matrix. 
[in]nColumnsnumber of columns in the matrix. 
[in]*pDatapoints to the matrix data array. 

+  

+

+
Returns:
none 

+
+
Definition at line 61 of file arm_mat_init_q31.c.

+
+

+

+
+

+

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void arm_mat_init_q15 (arm_matrix_instance_q15 *  S, 
uint16_t  nRows, 
uint16_t  nColumns, 
q15_t *  pData 
)

+

+

+
+
Q15 matrix initialization. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point matrix structure. 
[in]nRowsnumber of rows in the matrix. 
[in]nColumnsnumber of columns in the matrix. 
[in]*pDatapoints to the matrix data array. 

+  

+

+
Returns:
none 

+
+
Definition at line 57 of file arm_mat_init_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_inv.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_inv.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_inv.html
@@ -0,0 +1,126 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Inverse
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Inverse

+
+[Matrix Functions]
+
  

+

+

+
+
+
+

+Functions
arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)

+
Detailed Description

+
Computes the inverse of a matrix.

+
The inverse is defined only if the input matrix is square and non-singular (the determinant is non-zero). The function checks that the input and output matrices are square and of the same size.

+
Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix inversion of floating-point matrices.

+
Algorithm 
The Gauss-Jordan method is used to find the inverse. The algorithm performs a sequence of elementary row-operations till it reduces the input matrix to an identity matrix. Applying the same sequence of elementary row-operations to an identity matrix yields the inverse matrix. If the input matrix is singular, then the algorithm terminates and returns error status ARM_MATH_SINGULAR. 

+MatrixInverse.gif
+
Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method

+ 

+
Function Documentation

+
+

+

+      
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arm_status arm_mat_inverse_f32 (const arm_matrix_instance_f32 *  pSrc, 
arm_matrix_instance_f32 *  pDst 
)

+

+

+
+
Floating-point matrix inverse. 

+
Parameters:

+  
+    
+    
+  
[in]*pSrcpoints to input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size of the output matrix does not match the size of the input matrix. If the input matrix is found to be singular (non-invertible), then the function returns ARM_MATH_SINGULAR. Otherwise, the function returns ARM_MATH_SUCCESS. 

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 74 of file arm_mat_inverse_f32.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_mult.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_mult.html
new file mode 100644
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--- /dev/null
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+
+
+
+
+CMSIS DSP Software Library: Matrix Multiplication
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Multiplication

+
+[Matrix Functions]
+
  

+

+

+
+
+
+
+
+
+
+

+Functions
arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)
arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, q15_t *pState)

+
Detailed Description

+
Multiplies two matrices.

+

+MatrixMultiplication.gif
+
Multiplication of two 3 x 3 matrices

+
Matrix multiplication is only defined if the number of columns of the first matrix equals the number of rows of the second matrix. Multiplying an M x N matrix with an N x P matrix results in an M x P matrix. When matrix size checking is enabled, the functions check: (1) that the inner dimensions of pSrcA and pSrcB are equal; and (2) that the size of the output matrix equals the outer dimensions of pSrcA and pSrcB. 

+
Function Documentation

+
+

+

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arm_status arm_mat_mult_f32 (const arm_matrix_instance_f32 *  pSrcA, 
const arm_matrix_instance_f32 *  pSrcB, 
arm_matrix_instance_f32 *  pDst 
)

+

+

+
+
Floating-point matrix multiplication. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
Examples: 
arm_class_marks_example_f32.c, and arm_matrix_example_f32.c.

+

+
Definition at line 73 of file arm_mat_mult_f32.c.

+
+

+

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arm_status arm_mat_mult_q31 (const arm_matrix_instance_q31 *  pSrcA, 
const arm_matrix_instance_q31 *  pSrcB, 
arm_matrix_instance_q31 *  pDst 
)

+

+

+
+
Q31 matrix multiplication. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. The input is thus scaled down by log2(numColsA) bits to avoid overflows, as a total of numColsA additions are performed internally. The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.

+
See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 73 of file arm_mat_mult_q31.c.

+
+

+

+
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arm_status arm_mat_mult_fast_q31 (const arm_matrix_instance_q31 *  pSrcA, 
const arm_matrix_instance_q31 *  pSrcB, 
arm_matrix_instance_q31 *  pDst 
)

+

+

+
+
Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior:

+
The difference between the function arm_mat_mult_q31() and this fast variant is that the fast variant use a 32-bit rather than a 64-bit accumulator. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.31 result.

+
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, as a total of numColsA additions are computed internally for each output element.

+
See arm_mat_mult_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 

+
+
Definition at line 72 of file arm_mat_mult_fast_q31.c.

+
+

+

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arm_status arm_mat_mult_q15 (const arm_matrix_instance_q15 *  pSrcA, 
const arm_matrix_instance_q15 *  pSrcB, 
arm_matrix_instance_q15 *  pDst, 
q15_t *  pState 
)

+

+

+
+
Q15 matrix multiplication. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
[in]*pStatepoints to the array for storing intermediate results 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The inputs to the multiplications are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.

+
Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 74 of file arm_mat_mult_q15.c.

+
+

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+
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arm_status arm_mat_mult_fast_q15 (const arm_matrix_instance_q15 *  pSrcA, 
const arm_matrix_instance_q15 *  pSrcB, 
arm_matrix_instance_q15 *  pDst, 
q15_t *  pState 
)

+

+

+
+
Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 
[in]*pStatepoints to the array for storing intermediate results 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior:

+
The difference between the function arm_mat_mult_q15() and this fast variant is that the fast variant use a 32-bit rather than a 64-bit accumulator. The result of each 1.15 x 1.15 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.15 result.

+
The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 16 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, as a total of numColsA additions are computed internally for each output element.

+
See arm_mat_mult_q15() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. 

+
+
Definition at line 74 of file arm_mat_mult_fast_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_scale.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_scale.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_scale.html
@@ -0,0 +1,245 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Scale
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Scale

+
+[Matrix Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst)

+
Detailed Description

+
Multiplies a matrix by a scalar. This is accomplished by multiplying each element in the matrix by the scalar. For example: 

+

+MatrixScale.gif
+
Matrix Scaling of a 3 x 3 matrix

+
The function checks to make sure that the input and output matrices are of the same size.

+
In the fixed-point Q15 and Q31 functions, scale is represented by a fractional multiplication scaleFract and an arithmetic shift shift. The shift allows the gain of the scaling operation to exceed 1.0. The overall scale factor applied to the fixed-point data is 

+
   
+     scale = scaleFract * 2^shift.   
+ 
 
Function Documentation

+
+

+

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+      
arm_status arm_mat_scale_f32 (const arm_matrix_instance_f32 *  pSrc, 
float32_t  scale, 
arm_matrix_instance_f32 *  pDst 
)

+

+

+
+
Floating-point matrix scaling. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input matrix structure 
[in]scalescale factor to be applied 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
Definition at line 75 of file arm_mat_scale_f32.c.

+
+

+

+
+

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arm_status arm_mat_scale_q31 (const arm_matrix_instance_q31 *  pSrc, 
q31_t  scaleFract, 
int32_t  shift, 
arm_matrix_instance_q31 *  pDst 
)

+

+

+
+
Q31 matrix scaling. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to input matrix 
[in]scaleFractfractional portion of the scale factor 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.31 format. These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. 

+
+
Definition at line 63 of file arm_mat_scale_q31.c.

+
+

+

+
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arm_status arm_mat_scale_q15 (const arm_matrix_instance_q15 *  pSrc, 
q15_t  scaleFract, 
int32_t  shift, 
arm_matrix_instance_q15 *  pDst 
)

+

+

+
+
Q15 matrix scaling. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to input matrix 
[in]scaleFractfractional portion of the scale factor 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.15 format. These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. 

+
+
Definition at line 63 of file arm_mat_scale_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_sub.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_sub.html
new file mode 100644
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+
+
+
+
+CMSIS DSP Software Library: Matrix Subtraction
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Subtraction

+
+[Matrix Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst)

+
Detailed Description

+
Subtract two matrices. 

+

+MatrixSubtraction.gif
+
Subraction of two 3 x 3 matrices

+
The functions check to make sure that pSrcA, pSrcB, and pDst have the same number of rows and columns. 

+
Function Documentation

+
+

+

+      
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arm_status arm_mat_sub_f32 (const arm_matrix_instance_f32 *  pSrcA, 
const arm_matrix_instance_f32 *  pSrcB, 
arm_matrix_instance_f32 *  pDst 
)

+

+

+
+
Floating-point matrix subtraction. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
Definition at line 67 of file arm_mat_sub_f32.c.

+
+

+

+
+

+

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arm_status arm_mat_sub_q31 (const arm_matrix_instance_q31 *  pSrcA, 
const arm_matrix_instance_q31 *  pSrcB, 
arm_matrix_instance_q31 *  pDst 
)

+

+

+
+
Q31 matrix subtraction. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 62 of file arm_mat_sub_q31.c.

+
+

+

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arm_status arm_mat_sub_q15 (const arm_matrix_instance_q15 *  pSrcA, 
const arm_matrix_instance_q15 *  pSrcB, 
arm_matrix_instance_q15 *  pDst 
)

+

+

+
+
Q15 matrix subtraction. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcApoints to the first input matrix structure 
[in]*pSrcBpoints to the second input matrix structure 
[out]*pDstpoints to output matrix structure 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 61 of file arm_mat_sub_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_trans.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_trans.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___matrix_trans.html
@@ -0,0 +1,203 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Transpose
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Matrix Transpose

+
+[Matrix Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst)
arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst)
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst)

+
Detailed Description

+
Tranposes a matrix. Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. 

+

+MatrixTranspose.gif
+
Transpose of a 3 x 3 matrix

+ 
Function Documentation

+
+

+

+      
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arm_status arm_mat_trans_f32 (const arm_matrix_instance_f32 *  pSrc, 
arm_matrix_instance_f32 *  pDst 
)

+

+

+
+
Floating-point matrix transpose. 

+
Parameters:

+  
+    
+    
+  
[in]*pSrcpoints to the input matrix 
[out]*pDstpoints to the output matrix 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
Examples: 
arm_matrix_example_f32.c.

+

+
Definition at line 64 of file arm_mat_trans_f32.c.

+
+

+

+
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arm_status arm_mat_trans_q31 (const arm_matrix_instance_q31 *  pSrc, 
arm_matrix_instance_q31 *  pDst 
)

+

+

+
+
Q31 matrix transpose. 

+
Parameters:

+  
+    
+    
+  
[in]*pSrcpoints to the input matrix 
[out]*pDstpoints to the output matrix 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
Definition at line 55 of file arm_mat_trans_q31.c.

+
+

+

+
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+      
arm_status arm_mat_trans_q15 (const arm_matrix_instance_q15 *  pSrc, 
arm_matrix_instance_q15 *  pDst 
)

+

+

+
+
Q15 matrix transpose. 

+
Parameters:

+  
+    
+    
+  
[in]*pSrcpoints to the input matrix 
[out]*pDstpoints to the output matrix 

+  

+

+
Returns:
The function returns either ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. 

+
+
Definition at line 55 of file arm_mat_trans_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___max.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___max.html
new file mode 100644
index 0000000..4596fcc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___max.html
@@ -0,0 +1,296 @@
+
+
+
+
+CMSIS DSP Software Library: Maximum
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Maximum

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_max_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
void arm_max_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
void arm_max_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
void arm_max_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)

+
Detailed Description

+
Computes the maximum value of an array of data. The function returns both the maximum value and its position within the array. There are separate functions for floating-point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
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void arm_max_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Maximum value of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c, and arm_fft_bin_example_f32.c.

+

+
Definition at line 59 of file arm_max_f32.c.

+
+

+

+
+

+

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+      
void arm_max_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Maximum value of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 51 of file arm_max_q31.c.

+
+

+

+
+

+

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+      
void arm_max_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q15_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Maximum value of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 51 of file arm_max_q15.c.

+
+

+

+
+

+

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+      
void arm_max_q7 (q7_t *  pSrc, 
uint32_t  blockSize, 
q7_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Maximum value of a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmaximum value returned here 
[out]*pIndexindex of maximum value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 51 of file arm_max_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___min.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___min.html
new file mode 100644
index 0000000..93ca013
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___min.html
@@ -0,0 +1,296 @@
+
+
+
+
+CMSIS DSP Software Library: Minimum
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Minimum

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_min_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex)
void arm_min_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex)
void arm_min_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex)
void arm_min_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex)

+
Detailed Description

+
Computes the minimum value of an array of data. The function returns both the minimum value and its position within the array. There are separate functions for floating-point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
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+      
void arm_min_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Minimum value of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 60 of file arm_min_f32.c.

+
+

+

+
+

+

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+        
+      
void arm_min_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Minimum value of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_min_q31.c.

+
+

+

+
+

+

+      
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+      
void arm_min_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q15_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Minimum value of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_min_q15.c.

+
+

+

+
+

+

+      
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+          
+          
+        
+      
void arm_min_q7 (q7_t *  pSrc, 
uint32_t  blockSize, 
q7_t *  pResult, 
uint32_t *  pIndex 
)

+

+

+
+
Minimum value of a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultminimum value returned here 
[out]*pIndexindex of minimum value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 52 of file arm_min_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___p_i_d.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___p_i_d.html
new file mode 100644
index 0000000..209e2e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___p_i_d.html
@@ -0,0 +1,443 @@
+
+
+
+
+CMSIS DSP Software Library: PID Motor Control
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
PID Motor Control

+
+[Controller Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+

+Functions
void arm_pid_reset_f32 (arm_pid_instance_f32 *S)
void arm_pid_init_f32 (arm_pid_instance_f32 *S, int32_t resetStateFlag)
void arm_pid_reset_q31 (arm_pid_instance_q31 *S)
void arm_pid_init_q31 (arm_pid_instance_q31 *S, int32_t resetStateFlag)
void arm_pid_reset_q15 (arm_pid_instance_q15 *S)
void arm_pid_init_q15 (arm_pid_instance_q15 *S, int32_t resetStateFlag)
static __INLINE float32_t arm_pid_f32 (arm_pid_instance_f32 *S, float32_t in)
static __INLINE q31_t arm_pid_q31 (arm_pid_instance_q31 *S, q31_t in)
static __INLINE q15_t arm_pid_q15 (arm_pid_instance_q15 *S, q15_t in)

+
Detailed Description

+
A Proportional Integral Derivative (PID) controller is a generic feedback control loop mechanism widely used in industrial control systems. A PID controller is the most commonly used type of feedback controller.

+
This set of functions implements (PID) controllers for Q15, Q31, and floating-point data types. The functions operate on a single sample of data and each call to the function returns a single processed value. S points to an instance of the PID control data structure. in is the input sample value. The functions return the output value.

+
Algorithm:
+    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+    A0 = Kp + Ki + Kd
+    A1 = (-Kp ) - (2 * Kd )
+    A2 = Kd  

+
where Kp is proportional constant, Ki is Integral constant and Kd is Derivative constant

+

+PID.gif
+
Proportional Integral Derivative Controller

+

+
The PID controller calculates an "error" value as the difference between the measured output and the reference input. The controller attempts to minimize the error by adjusting the process control inputs. The proportional value determines the reaction to the current error, the integral value determines the reaction based on the sum of recent errors, and the derivative value determines the reaction based on the rate at which the error has been changing.

+
Instance Structure 
The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. A separate instance structure must be defined for each PID Controller. There are separate instance structure declarations for each of the 3 supported data types.

+
Reset Functions 
There is also an associated reset function for each data type which clears the state array.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
    • 
+
  • Zeros out the values in the state buffer.
    • 
+

+

+
Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the PID Controller functions. In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void arm_pid_reset_f32 (arm_pid_instance_f32 *  S )

+

+

+
+
Reset function for the floating-point PID Control. 

+
Parameters:

+  
+    
+  
[in]*SInstance pointer of PID control data structure. 

+  

+

+
Returns:
none. 

+
Description: 
The function resets the state buffer to zeros. 

+
+
Definition at line 44 of file arm_pid_reset_f32.c.

+
+

+

+
+

+

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void arm_pid_init_f32 (arm_pid_instance_f32 *  S, 
int32_t  resetStateFlag 
)

+

+

+
+
Initialization function for the floating-point PID Control. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the PID structure. 
[in]resetStateFlagflag to reset the state. 0 = no change in state & 1 = reset the state. 

+  

+

+
Returns:
none. 

+
Description: 

+
The resetStateFlag specifies whether to set state to zero or not. 

+ The function computes the structure fields: A0, A1 A2 using the proportional gain( Kp), integral gain( Ki) and derivative gain( Kd) also sets the state variables to all zeros. 

+
+
Definition at line 51 of file arm_pid_init_f32.c.

+
+

+

+
+

+

+      
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+          
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+      
void arm_pid_reset_q31 (arm_pid_instance_q31 *  S )

+

+

+
+
Reset function for the Q31 PID Control. 

+
Parameters:

+  
+    
+  
[in]*SInstance pointer of PID control data structure. 

+  

+

+
Returns:
none. 

+
Description: 
The function resets the state buffer to zeros. 

+
+
Definition at line 44 of file arm_pid_reset_q31.c.

+
+

+

+
+

+

+      
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+      
void arm_pid_init_q31 (arm_pid_instance_q31 *  S, 
int32_t  resetStateFlag 
)

+

+

+
+
Initialization function for the Q31 PID Control. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 PID structure. 
[in]resetStateFlagflag to reset the state. 0 = no change in state 1 = reset the state. 

+  

+

+
Returns:
none. 

+
Description: 

+
The resetStateFlag specifies whether to set state to zero or not. 

+ The function computes the structure fields: A0, A1 A2 using the proportional gain( Kp), integral gain( Ki) and derivative gain( Kd) also sets the state variables to all zeros. 

+
+
Definition at line 50 of file arm_pid_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
void arm_pid_reset_q15 (arm_pid_instance_q15 *  S )

+

+

+
+
Reset function for the Q15 PID Control. 

+
Parameters:

+  
+    
+  
[in]*SInstance pointer of PID control data structure. 

+  

+

+
Returns:
none. 

+
Description: 
The function resets the state buffer to zeros. 

+
+
Definition at line 44 of file arm_pid_reset_q15.c.

+
+

+

+
+

+

+      
+        
+          
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+      
void arm_pid_init_q15 (arm_pid_instance_q15 *  S, 
int32_t  resetStateFlag 
)

+

+

+
+
Initialization function for the Q15 PID Control. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 PID structure. 
[in]resetStateFlagflag to reset the state. 0 = no change in state 1 = reset the state. 

+  

+

+
Returns:
none. 

+
Description: 

+
The resetStateFlag specifies whether to set state to zero or not. 

+ The function computes the structure fields: A0, A1 A2 using the proportional gain( Kp), integral gain( Ki) and derivative gain( Kd) also sets the state variables to all zeros. 

+
+
Definition at line 50 of file arm_pid_init_q15.c.

+
+

+

+
+

+

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static __INLINE float32_t arm_pid_f32 (arm_pid_instance_f32 *  S, 
float32_t  in 
) [static]

+

+

+
+
Process function for the floating-point PID Control. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Sis an instance of the floating-point PID Control structure 
[in]ininput sample to process 

+  

+

+
Returns:
out processed output sample. 

+
+
Definition at line 4711 of file arm_math.h.

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static __INLINE q31_t arm_pid_q31 (arm_pid_instance_q31 *  S, 
q31_t  in 
) [static]

+

+

+
+
Process function for the Q31 PID Control. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 PID Control structure 
[in]ininput sample to process 

+  

+

+
Returns:
out processed output sample.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. Thus, if the accumulator result overflows it wraps around rather than clip. In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 

+
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Definition at line 4746 of file arm_math.h.

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static __INLINE q15_t arm_pid_q15 (arm_pid_instance_q15 *  S, 
q15_t  in 
) [static]

+

+

+
+
Process function for the Q15 PID Control. 

+
Parameters:

+  
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 PID Control structure 
[in]ininput sample to process 

+  

+

+
Returns:
out processed output sample.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. Lastly, the accumulator is saturated to yield a result in 1.15 format. 

+
+
Definition at line 4794 of file arm_math.h.

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Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___partial_conv.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___partial_conv.html
new file mode 100644
index 0000000..e528796
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___partial_conv.html
@@ -0,0 +1,535 @@
+
+
+
+
+CMSIS DSP Software Library: Partial Convolution
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Partial Convolution

+
+[Filtering Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_conv_partial_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, uint32_t numPoints)
arm_status arm_conv_partial_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, uint32_t firstIndex, uint32_t numPoints)

+
Detailed Description

+
Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated. Each function has two additional arguments. firstIndex specifies the starting index of the subset of output samples. numPoints is the number of output samples to compute. The function computes the output in the range [firstIndex, ..., firstIndex+numPoints-1]. The output array pDst contains numPoints values.

+
The allowable range of output indices is [0 srcALen+srcBLen-2]. If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR. Otherwise the functions return ARM_MATH_SUCCESS. 

+
Note:
Refer arm_conv_f32() for details on fixed point behavior. 

+
Function Documentation

+
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arm_status arm_conv_partial_f32 (float32_t *  pSrcA, 
uint32_t  srcALen, 
float32_t *  pSrcB, 
uint32_t  srcBLen, 
float32_t *  pDst, 
uint32_t  firstIndex, 
uint32_t  numPoints 
)

+

+

+
+
Partial convolution of floating-point sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. 

+
+
Definition at line 74 of file arm_conv_partial_f32.c.

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arm_status arm_conv_partial_q31 (q31_t *  pSrcA, 
uint32_t  srcALen, 
q31_t *  pSrcB, 
uint32_t  srcBLen, 
q31_t *  pDst, 
uint32_t  firstIndex, 
uint32_t  numPoints 
)

+

+

+
+
Partial convolution of Q31 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 59 of file arm_conv_partial_q31.c.

+
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arm_status arm_conv_partial_fast_q31 (q31_t *  pSrcA, 
uint32_t  srcALen, 
q31_t *  pSrcB, 
uint32_t  srcBLen, 
q31_t *  pDst, 
uint32_t  firstIndex, 
uint32_t  numPoints 
)

+

+

+
+
Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. 

+
+
Definition at line 56 of file arm_conv_partial_fast_q31.c.

+
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arm_status arm_conv_partial_q15 (q15_t *  pSrcA, 
uint32_t  srcALen, 
q15_t *  pSrcB, 
uint32_t  srcBLen, 
q15_t *  pDst, 
uint32_t  firstIndex, 
uint32_t  numPoints 
)

+

+

+
+
Partial convolution of Q15 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 

+
+
Definition at line 60 of file arm_conv_partial_q15.c.

+
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arm_status arm_conv_partial_fast_q15 (q15_t *  pSrcA, 
uint32_t  srcALen, 
q15_t *  pSrcB, 
uint32_t  srcBLen, 
q15_t *  pDst, 
uint32_t  firstIndex, 
uint32_t  numPoints 
)

+

+

+
+
Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].

+
See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. 

+
+
Definition at line 56 of file arm_conv_partial_fast_q15.c.

+
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arm_status arm_conv_partial_q7 (q7_t *  pSrcA, 
uint32_t  srcALen, 
q7_t *  pSrcB, 
uint32_t  srcBLen, 
q7_t *  pDst, 
uint32_t  firstIndex, 
uint32_t  numPoints 
)

+

+

+
+
Partial convolution of Q7 sequences. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input sequence. 
[in]srcALenlength of the first input sequence. 
[in]*pSrcBpoints to the second input sequence. 
[in]srcBLenlength of the second input sequence. 
[out]*pDstpoints to the location where the output result is written. 
[in]firstIndexis the first output sample to start with. 
[in]numPointsis the number of output points to be computed. 

+  

+

+
Returns:
Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. 

+
+
Definition at line 58 of file arm_conv_partial_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___r_f_f_t___r_i_f_f_t.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___r_f_f_t___r_i_f_f_t.html
new file mode 100644
index 0000000..6ab41e5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___r_f_f_t___r_i_f_f_t.html
@@ -0,0 +1,611 @@
+
+
+
+
+CMSIS DSP Software Library: Real FFT Functions
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
Real FFT Functions

+
+[Transform Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Functions
arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
void arm_rfft_f32 (const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst)
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *S, arm_cfft_radix4_instance_q31 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
void arm_rfft_q31 (const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst)
arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *S, arm_cfft_radix4_instance_q15 *S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag)
void arm_rfft_q15 (const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst)

+Variables
static const float32_t realCoefA [2048]
static const float32_t realCoefB [2048]
const q31_t realCoefAQ31 [1024]
const q31_t realCoefBQ31 [1024]
static const q15_t realCoefAQ15 [2048]
static const q15_t realCoefBQ15 [2048]

+
Detailed Description

+
Complex FFT/IFFT typically assumes complex input and output. However many applications use real valued data in time domain. Real FFT/IFFT efficiently process real valued sequences with the advantage of requirement of low memory and with less complexity.

+
This set of functions implements Real Fast Fourier Transforms(RFFT) and Real Inverse Fast Fourier Transform(RIFFT) for Q15, Q31, and floating-point data types.

+
Algorithm: 

+
Real Fast Fourier Transform: 

+
Real FFT of N-point is calculated using CFFT of N/2-point and Split RFFT process as shown below figure. 

+

+RFFT.gif
+
Real Fast Fourier Transform

+ 

+
The RFFT functions operate on blocks of input and output data and each call to the function processes fftLenR samples through the transform. pSrc points to input array containing fftLenR values. pDst points to output array containing 2*fftLenR values. 

+ Input for real FFT is in the order of 
{real[0], real[1], real[2], real[3], ..}
 Output for real FFT is complex and are in the order of 
{real(0), imag(0), real(1), imag(1), ...}

+
Real Inverse Fast Fourier Transform: 

+
Real IFFT of N-point is calculated using Split RIFFT process and CFFT of N/2-point as shown below figure. 

+

+RIFFT.gif
+
Real Inverse Fast Fourier Transform

+ 

+
The RIFFT functions operate on blocks of input and output data and each call to the function processes 2*fftLenR samples through the transform. pSrc points to input array containing 2*fftLenR values. pDst points to output array containing fftLenR values. 

+ Input for real IFFT is complex and are in the order of 
{real(0), imag(0), real(1), imag(1), ...}
 Output for real IFFT is real and in the order of 
{real[0], real[1], real[2], real[3], ..}

+
Lengths supported by the transform: 

+
Real FFT/IFFT supports the lengths [128, 512, 2048], as it internally uses CFFT/CIFFT.

+
Instance Structure 
A separate instance structure must be defined for each Instance but the twiddle factors can be reused. There are separate instance structure declarations for each of the 3 supported data types.

+
Initialization Functions 
There is also an associated initialization function for each data type. The initialization function performs the following operations:
    
+
  • Sets the values of the internal structure fields.
    • 
+
  • Initializes twiddle factor tables.
    • 
+
  • Initializes CFFT data structure fields. 
    • 
+

+

+
Use of the initialization function is optional. However, if the initialization function is used, then the instance structure cannot be placed into a const data section. To place an instance structure into a const data section, the instance structure must be manually initialized. Manually initialize the instance structure as follows: 
   
+arm_rfft_instance_f32 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+ 
 where fftLenReal length of RFFT/RIFFT; fftLenBy2 length of CFFT/CIFFT. ifftFlagR Flag for selection of RFFT or RIFFT(Set ifftFlagR to calculate RIFFT otherwise calculates RFFT); bitReverseFlagR Flag for selection of output order(Set bitReverseFlagR to output in normal order otherwise output in bit reversed order); twidCoefRModifier modifier for twiddle factor table which supports 128, 512, 2048 RFFT lengths with same table; pTwiddleARealpoints to A array of twiddle coefficients; pTwiddleBRealpoints to B array of twiddle coefficients; pCfft points to the CFFT Instance structure. The CFFT structure also needs to be initialized, refer to arm_cfft_radix4_f32() for details regarding static initialization of cfft structure.

+
Fixed-Point Behavior 
Care must be taken when using the fixed-point versions of the RFFT/RIFFT function. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

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arm_status arm_rfft_init_f32 (arm_rfft_instance_f32 *  S, 
arm_cfft_radix4_instance_f32 *  S_CFFT, 
uint32_t  fftLenReal, 
uint32_t  ifftFlagR, 
uint32_t  bitReverseFlag 
)

+

+

+
+
Initialization function for the floating-point RFFT/RIFFT. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the floating-point RFFT/RIFFT structure. 
[in,out]*S_CFFTpoints to an instance of the floating-point CFFT/CIFFT structure. 
[in]fftLenReallength of the FFT. 
[in]ifftFlagRflag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.

+
Description: 

+
The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048. 

+
The parameter ifftFlagR controls whether a forward or inverse transform is computed. Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
This function also initializes Twiddle factor table. 

+
+
Definition at line 1638 of file arm_rfft_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_rfft_f32 (const arm_rfft_instance_f32 *  S, 
float32_t *  pSrc, 
float32_t *  pDst 
)

+

+

+
+
Processing function for the floating-point RFFT/RIFFT. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the floating-point RFFT/RIFFT structure. 
[in]*pSrcpoints to the input buffer. 
[out]*pDstpoints to the output buffer. 

+  

+

+
Returns:
none. 

+
+
Definition at line 150 of file arm_rfft_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
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+        
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+        
+        
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+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_rfft_init_q31 (arm_rfft_instance_q31 *  S, 
arm_cfft_radix4_instance_q31 *  S_CFFT, 
uint32_t  fftLenReal, 
uint32_t  ifftFlagR, 
uint32_t  bitReverseFlag 
)

+

+

+
+
Initialization function for the Q31 RFFT/RIFFT. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q31 RFFT/RIFFT structure. 
[in,out]*S_CFFTpoints to an instance of the Q31 CFFT/CIFFT structure. 
[in]fftLenReallength of the FFT. 
[in]ifftFlagRflag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.

+
Description: 

+
The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048. 

+
The parameter ifftFlagR controls whether a forward or inverse transform is computed. Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
This function also initializes Twiddle factor table. 

+
+
Definition at line 617 of file arm_rfft_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
+        
+        
+          
+          
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+          
+        
+        
+          
+          
+          
+        
+      
void arm_rfft_q31 (const arm_rfft_instance_q31 *  S, 
q31_t *  pSrc, 
q31_t *  pDst 
)

+

+

+
+
Processing function for the Q31 RFFT/RIFFT. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the Q31 RFFT/RIFFT structure. 
[in]*pSrcpoints to the input buffer. 
[out]*pDstpoints to the output buffer. 

+  

+

+
Returns:
none.

+
Input an output formats: 

+
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different RFFT sizes. The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: 

+

+RFFTQ31.gif
+
Input and Output Formats for Q31 RFFT

+

+

+RIFFTQ31.gif
+
Input and Output Formats for Q31 RIFFT

+ 

+
+
Definition at line 80 of file arm_rfft_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+        
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_rfft_init_q15 (arm_rfft_instance_q15 *  S, 
arm_cfft_radix4_instance_q15 *  S_CFFT, 
uint32_t  fftLenReal, 
uint32_t  ifftFlagR, 
uint32_t  bitReverseFlag 
)

+

+

+
+
Initialization function for the Q15 RFFT/RIFFT. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in,out]*Spoints to an instance of the Q15 RFFT/RIFFT structure. 
[in]*S_CFFTpoints to an instance of the Q15 CFFT/CIFFT structure. 
[in]fftLenReallength of the FFT. 
[in]ifftFlagRflag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 
[in]bitReverseFlagflag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.

+
Description: 

+
The parameter fftLenReal Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048. 

+
The parameter ifftFlagR controls whether a forward or inverse transform is computed. Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. 

+
The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. 

+
This function also initializes Twiddle factor table. 

+
+
Definition at line 620 of file arm_rfft_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_rfft_q15 (const arm_rfft_instance_q15 *  S, 
q15_t *  pSrc, 
q15_t *  pDst 
)

+

+

+
+
Processing function for the Q15 RFFT/RIFFT. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*Spoints to an instance of the Q15 RFFT/RIFFT structure. 
[in]*pSrcpoints to the input buffer. 
[out]*pDstpoints to the output buffer. 

+  

+

+
Returns:
none.

+
Input an output formats: 

+
Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. Hence the output format is different for different RFFT sizes. The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: 

+

+RFFTQ15.gif
+
Input and Output Formats for Q15 RFFT

+ 

+

+RIFFTQ15.gif
+
Input and Output Formats for Q15 RIFFT

+ 

+
+
Definition at line 80 of file arm_rfft_q15.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t realCoefA[2048] [static]

+

+

+
Generation of realCoefA array: 

+
n = 1024 
for (i = 0; i < n; i++)   
+  {   
+    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+  } 
 

+
+
Definition at line 59 of file arm_rfft_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t realCoefB[2048] [static]

+

+

+
Generation of realCoefB array: 

+
n = 1024 
for (i = 0; i < n; i++)   
+ {   
+    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+  } 
 

+
+
Definition at line 843 of file arm_rfft_init_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t realCoefAQ31[1024]

+

+

+
Generation floating point realCoefAQ31 array: 

+
n = 1024 
for (i = 0; i < n; i++)   
+ {   
+    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+ }
 

+
Convert to fixed point Q31 format round(pATable[i] * pow(2, 31)) 

+
+
Definition at line 60 of file arm_rfft_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t realCoefBQ31[1024]

+

+

+
Generation of realCoefBQ31 array: 

+
n = 512 
for (i = 0; i < n; i++)   
+ {   
+    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+ } 
 

+
Convert to fixed point Q31 format round(pBTable[i] * pow(2, 31)) 

+
+
Definition at line 336 of file arm_rfft_init_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t realCoefAQ15[2048] [static]

+

+

+
Generation floating point real_CoefA array: 

+
n = 1024 
for (i = 0; i < n; i++)   
+  {   
+    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+  } 
 

+
Convert to fixed point Q15 format round(pATable[i] * pow(2, 15)) 

+
+
Definition at line 63 of file arm_rfft_init_q15.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t realCoefBQ15[2048] [static]

+

+

+
Generation of real_CoefB array: 

+
n = 1024 
for (i = 0; i < n; i++)   
+  {   
+    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+  } 
 

+
Convert to fixed point Q15 format round(pBTable[i] * pow(2, 15)) 

+
+
Definition at line 339 of file arm_rfft_init_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___r_m_s.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___r_m_s.html
new file mode 100644
index 0000000..6597a3c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___r_m_s.html
@@ -0,0 +1,227 @@
+
+
+
+
+CMSIS DSP Software Library: Root mean square (RMS)
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Root mean square (RMS)

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_rms_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_rms_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_rms_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)

+
Detailed Description

+
Calculates the Root Mean Sqaure of the elements in the input vector. The underlying algorithm is used:

+
   
+ 	Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));   
+ 
There are separate functions for floating point, Q31, and Q15 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
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+          
+        
+      
void arm_rms_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult 
)

+

+

+
+
Root Mean Square of the elements of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultrms value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 65 of file arm_rms_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
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+        
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+          
+          
+          
+        
+      
void arm_rms_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult 
)

+

+

+
+
Root Mean Square of the elements of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultrms value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The input is represented in 1.31 format, and intermediate multiplication yields a 2.62 format. The accumulator maintains full precision of the intermediate multiplication results, but provides only a single guard bit. There is no saturation on intermediate additions. If the accumulator overflows, it wraps around and distorts the result. In order to avoid overflows completely, the input signal must be scaled down by log2(blockSize) bits, as a total of blockSize additions are performed internally. Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. 

+
+
Definition at line 62 of file arm_rms_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
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+        
+        
+          
+          
+          
+        
+      
void arm_rms_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q15_t *  pResult 
)

+

+

+
+
Root Mean Square of the elements of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultrms value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the 34.30 result is truncated to 34.15 format by discarding the lower 15 bits, and then saturated to yield a result in 1.15 format. 

+
+
Definition at line 59 of file arm_rms_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___s_q_r_t.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___s_q_r_t.html
new file mode 100644
index 0000000..5805eea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___s_q_r_t.html
@@ -0,0 +1,205 @@
+
+
+
+
+CMSIS DSP Software Library: Square Root
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Square Root

+
+[Fast Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
arm_status arm_sqrt_q31 (q31_t in, q31_t *pOut)
arm_status arm_sqrt_q15 (q15_t in, q15_t *pOut)
static __INLINE arm_status arm_sqrt_f32 (float32_t in, float32_t *pOut)

+
Detailed Description

+
Computes the square root of a number. There are separate functions for Q15, Q31, and floating-point data types. The square root function is computed using the Newton-Raphson algorithm. This is an iterative algorithm of the form: 

+
+      x1 = x0 - f(x0)/f'(x0)
+ 
 where x1 is the current estimate, x0 is the previous estimate and f'(x0) is the derivative of f() evaluated at x0. For the square root function, the algorithm reduces to: 

+
+     x0 = in/2                         [initial guess]
+     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+ 
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_sqrt_q31 (q31_t  in, 
q31_t *  pOut 
)

+

+

+
+
Q31 square root function. 

+
Parameters:

+  
+    
+    
+  
[in]ininput value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. 
[out]*pOutsquare root of input value. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if in is negative value and returns zero output for negative values. 

+
+
Definition at line 47 of file arm_sqrt_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
arm_status arm_sqrt_q15 (q15_t  in, 
q15_t *  pOut 
)

+

+

+
+
Q15 square root function. 

+
Parameters:

+  
+    
+    
+  
[in]ininput value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. 
[out]*pOutsquare root of input value. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if in is negative value and returns zero output for negative values. 

+
+
Definition at line 51 of file arm_sqrt_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE arm_status arm_sqrt_f32 (float32_t  in, 
float32_t *  pOut 
) [static]

+

+

+
+
Floating-point square root function. 

+
Parameters:

+  
+    
+    
+  
[in]ininput value. 
[out]*pOutsquare root of input value. 

+  

+

+
Returns:
The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if in is negative value and returns zero output for negative values. 

+
+
Definition at line 5695 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___s_t_d.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___s_t_d.html
new file mode 100644
index 0000000..9873206
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___s_t_d.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: Standard deviation
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Standard deviation

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_std_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_std_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_std_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)

+
Detailed Description

+
Calculates the standard deviation of the elements in the input vector. The underlying algorithm is used:

+
   
+ 	Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))
	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]  
+ 
There are separate functions for floating point, Q31, and Q15 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_std_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult 
)

+

+

+
+
Standard deviation of the elements of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultstandard deviation value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 69 of file arm_std_f32.c.

+
+

+

+
+

+

+      
+        
+          
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+          
+        
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+        
+          
+          
+          
+        
+      
void arm_std_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult 
)

+

+

+
+
Standard deviation of the elements of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultstandard deviation value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The input is represented in 1.31 format, and intermediate multiplication yields a 2.62 format. The accumulator maintains full precision of the intermediate multiplication results, but provides only a single guard bit. There is no saturation on intermediate additions. If the accumulator overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(blockSize) bits, as a total of blockSize additions are performed internally. Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. 

+
+
Definition at line 66 of file arm_std_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
+          
+        
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+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_std_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q15_t *  pResult 
)

+

+

+
+
Standard deviation of the elements of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultstandard deviation value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the 34.30 result is truncated to 34.15 format by discarding the lower 15 bits, and then saturated to yield a result in 1.15 format. 

+
+
Definition at line 62 of file arm_std_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___signal_convergence.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___signal_convergence.html
new file mode 100644
index 0000000..11690e4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___signal_convergence.html
@@ -0,0 +1,107 @@
+
+
+
+
+CMSIS DSP Software Library: Signal Convergence Example
+
+
+
+
+
+
+
+
+
+

+  

+
Signal Convergence Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Demonstrates the ability of an adaptive filter to "learn" the transfer function of a FIR lowpass filter using the Normalized LMS Filter, Finite Impulse Response (FIR) Filter, and Basic Math Functions.

+
Algorithm:

+
The figure below illustrates the signal flow in this example. Uniformly distributed white noise is passed through an FIR lowpass filter. The output of the FIR filter serves as the reference input of the adaptive filter (normalized LMS filter). The white noise is input to the adaptive filter. The adaptive filter learns the transfer function of the FIR filter. The filter outputs two signals: (1) the output of the internal adaptive FIR filter, and (2) the error signal which is the difference between the adaptive filter and the reference output of the FIR filter. Over time as the adaptive filter learns the transfer function of the FIR filter, the first output approaches the reference output of the FIR filter, and the error signal approaches zero. 

+
The adaptive filter converges properly even if the input signal has a large dynamic range (i.e., varies from small to large values). The coefficients of the adaptive filter are initially zero, and then converge over 1536 samples. The internal function test_signal_converge() implements the stopping condition. The function checks if all of the values of the error signal have a magnitude below a threshold DELTA.

+
Block Diagram:

+

+SignalFlow.gif
+

+

+
Variables Description:

+
    
+
  • testInput_f32 points to the input data 
    • 
+
  • firStateF32 points to FIR state buffer 
    • 
+
  • lmsStateF32 points to Normalised Least mean square FIR filter state buffer 
    • 
+
  • FIRCoeff_f32 points to coefficient buffer 
    • 
+
  • lmsNormCoeff_f32 points to Normalised Least mean square FIR filter coefficient buffer 
    • 
+
  • wire1, wir2, wire3 temporary buffers 
    • 
+
  • errOutput, err_signal temporary error buffers
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_signal_converge_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___sin_cos.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___sin_cos.html
new file mode 100644
index 0000000..245c4fe
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___sin_cos.html
@@ -0,0 +1,268 @@
+
+
+
+
+CMSIS DSP Software Library: Sine Cosine
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
Sine Cosine

+
+[Controller Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+

+Functions
void arm_sin_cos_f32 (float32_t theta, float32_t *pSinVal, float32_t *pCosVal)
void arm_sin_cos_q31 (q31_t theta, q31_t *pSinVal, q31_t *pCosVal)

+Variables
static const float32_t cosTable [360]
static const float32_t sinTable [360]
static const int32_t sinTableQ31 [360]
static const int32_t cosTableQ31 [360]

+
Detailed Description

+
Computes the trigonometric sine and cosine values using a combination of table lookup and linear interpolation. There are separate functions for Q31 and floating-point data types. The input to the floating-point version is in degrees while the fixed-point Q31 have a scaled input with the range [-1 1) mapping to [-180 180) degrees.

+
The implementation is based on table lookup using 360 values together with linear interpolation. The steps used are:

+
    
+
  1. Calculation of the nearest integer table index.
    2. 
+
  2. Compute the fractional portion (fract) of the input.
    3. 
+
  3. Fetch the value corresponding to index from sine table to y0 and also value from index+1 to y1.
    4. 
+
  4. Sine value is computed as  *psinVal = y0 + (fract * (y1 - y0)).
    5. 
+
  5. Fetch the value corresponding to index from cosine table to y0 and also value from index+1 to y1.
    6. 
+
  6. Cosine value is computed as  *pcosVal = y0 + (fract * (y1 - y0)). 
    7. 
+

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
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+          
+          
+          
+        
+      
void arm_sin_cos_f32 (float32_t  theta, 
float32_t *  pSinVal, 
float32_t *  pCosVal 
)

+

+

+
+
Floating-point sin_cos function. 

+
Parameters:

+  
+    
+    
+    
+  
[in]thetainput value in degrees 
[out]*pSinValpoints to the processed sine output. 
[out]*pCosValpoints to the processed cos output. 

+  

+

+
Returns:
none. 

+
+
Definition at line 367 of file arm_sin_cos_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
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+          
+          
+          
+        
+      
void arm_sin_cos_q31 (q31_t  theta, 
q31_t *  pSinVal, 
q31_t *  pCosVal 
)

+

+

+
+
Q31 sin_cos function. 

+
Parameters:

+  
+    
+    
+    
+  
[in]thetascaled input value in degrees 
[out]*pSinValpoints to the processed sine output. 
[out]*pCosValpoints to the processed cosine output. 

+  

+

+
Returns:
none.

+
The Q31 input value is in the range [-1 +1) and is mapped to a degree value in the range [-180 180). 

+
+
Definition at line 264 of file arm_sin_cos_q31.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t cosTable[360] [static]

+

+

+
Cosine Table is generated from following loop 
for(i = 0; i < 360; i++)   
+ {   
+    cosTable[i]= cos((i-180) * PI/180.0);   
+ } 
 

+
+
Definition at line 71 of file arm_sin_cos_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const float32_t sinTable[360] [static]

+

+

+
Sine Table is generated from following loop 
for(i = 0; i < 360; i++)   
+ {   
+    sinTable[i]= sin((i-180) * PI/180.0);   
+ } 
 

+
+
Definition at line 219 of file arm_sin_cos_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const int32_t sinTableQ31[360] [static]

+

+

+
Sine Table is generated from following loop 
for(i = 0; i < 360; i++)   
+ {   
+    sinTable[i]= sin((i-180) * PI/180.0);   
+ } 
 Convert above coefficients to fixed point 1.31 format. 

+
+
Definition at line 51 of file arm_sin_cos_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const int32_t cosTableQ31[360] [static]

+

+

+
Cosine Table is generated from following loop 
for(i = 0; i < 360; i++)   
+ {   
+    cosTable[i]= cos((i-180) * PI/180.0);   
+ } 
 

+
Convert above coefficients to fixed point 1.31 format. 

+
+
Definition at line 157 of file arm_sin_cos_q31.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___sin_cos_example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___sin_cos_example.html
new file mode 100644
index 0000000..8772f3f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___sin_cos_example.html
@@ -0,0 +1,96 @@
+
+
+
+
+CMSIS DSP Software Library: SineCosine Example
+
+
+
+
+
+
+
+
+
+

+  

+
SineCosine Example

+
+[Examples]
+
  

+

+

+
+

+
Description:

+
Demonstrates the Pythagorean trignometric identity with the use of Cosine, Sine, Vector Multiplication, and Vector Addition functions.

+
Algorithm:

+
Mathematically, the Pythagorean trignometric identity is defined by the following equation: 
sin(x) * sin(x) + cos(x) * cos(x) = 1
 where x is the angle in radians.

+
Block Diagram:

+

+sinCos.gif
+

+

+
Variables Description:

+
    
+
  • testInput_f32 array of input angle in radians 
    • 
+
  • testOutput stores sum of the squares of sine and cosine values of input angle
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_sin_cos_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___variance_example.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___variance_example.html
new file mode 100644
index 0000000..01d3675
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group___variance_example.html
@@ -0,0 +1,101 @@
+
+
+
+
+CMSIS DSP Software Library: Variance Example
+
+
+
+
+
+
+
+
+
+

+  

+
Variance Example

+
+[Examples]
+
  

+

+

+
+

+
Description: 

+
Demonstrates the use of Basic Math and Support Functions to calculate the variance of an input sequence with N samples. Uniformly distributed white noise is taken as input.

+
Algorithm:

+
The variance of a sequence is the mean of the squared deviation of the sequence from its mean. 

+
This is denoted by the following equation: 
 variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)
 where, x[n] is the input sequence, N is the number of input samples, and x' is the mean value of the input sequence, x[n]. 

+
The mean value x' is defined as: 
 x' = (x[0] + x[1] + ... + x[n-1]) / N

+
Block Diagram:

+

+Variance.gif
+

+

+
Variables Description:

+
    
+
  • testInput_f32 points to the input data 
    • 
+
  • wire1, wir2, wire3 temporary buffers 
    • 
+
  • blockSize number of samples processed at a time 
    • 
+
  • refVarianceOut reference variance value
    • 
+

+

+
CMSIS DSP Software Library Functions Used:

+

+

+
 Refer  arm_variance_example_f32.c 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__clarke.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__clarke.html
new file mode 100644
index 0000000..b48719e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__clarke.html
@@ -0,0 +1,199 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Clarke Transform
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Clarke Transform

+
+[Controller Functions]
+
  

+

+

+
+
+
+
+

+Functions
static __INLINE void arm_clarke_f32 (float32_t Ia, float32_t Ib, float32_t *pIalpha, float32_t *pIbeta)
static __INLINE void arm_clarke_q31 (q31_t Ia, q31_t Ib, q31_t *pIalpha, q31_t *pIbeta)

+
Detailed Description

+
Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents in the two-phase orthogonal stator axis Ialpha and Ibeta. When Ialpha is superposed with Ia as shown in the figure below 

+

+clarke.gif
+
Stator current space vector and its components in (a,b).

+
 and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta can be calculated using only Ia and Ib.

+
The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 

+
Algorithm

+clarkeFormula.gif
+

+ where Ia and Ib are the instantaneous stator phases and pIalpha and pIbeta are the two coordinates of time invariant vector. 

+
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Clarke transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
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+        
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+          
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+        
+      
static __INLINE void arm_clarke_f32 (float32_t  Ia, 
float32_t  Ib, 
float32_t *  pIalpha, 
float32_t *  pIbeta 
) [static]

+

+

+
+
Floating-point Clarke transform. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]Iainput three-phase coordinate a 
[in]Ibinput three-phase coordinate b 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 

+  

+

+
Returns:
none. 

+
+
Definition at line 4905 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
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+        
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_clarke_q31 (q31_t  Ia, 
q31_t  Ib, 
q31_t *  pIalpha, 
q31_t *  pIbeta 
) [static]

+

+

+
+
Clarke transform for Q31 version. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]Iainput three-phase coordinate a 
[in]Ibinput three-phase coordinate b 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition, hence there is no risk of overflow. 

+
+
Definition at line 4934 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cmplx__conj.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cmplx__conj.html
new file mode 100644
index 0000000..75d80db
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cmplx__conj.html
@@ -0,0 +1,231 @@
+
+
+
+
+CMSIS DSP Software Library: Complex Conjugate
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Complex Conjugate

+
+[Complex Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_cmplx_conj_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_conj_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_conj_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)

+
Detailed Description

+
Conjugates the elements of a complex data vector.

+
The pSrc points to the source data and pDst points to the where the result should be written. numSamples specifies the number of complex samples and the data in each array is stored in an interleaved fashion (real, imag, real, imag, ...). Each array has a total of 2*numSamples values. The underlying algorithm is used:

+
   
+ for(n=0; n<numSamples; n++) {   
+     pDst[(2*n)+0)] = pSrc[(2*n)+0];     // real part   
+     pDst[(2*n)+1)] = -pSrc[(2*n)+1];    // imag part   
+ }   
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_conj_f32 (float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Floating-point complex conjugate. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the input vector 
*pDstpoints to the output vector 
numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 72 of file arm_cmplx_conj_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_conj_q31 (q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q31 complex conjugate. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the input vector 
*pDstpoints to the output vector 
numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. 

+
+
Definition at line 54 of file arm_cmplx_conj_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_conj_q15 (q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q15 complex conjugate. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the input vector 
*pDstpoints to the output vector 
numSamplesnumber of complex samples in each vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. 

+
+
Definition at line 54 of file arm_cmplx_conj_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cmplx__dot__prod.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cmplx__dot__prod.html
new file mode 100644
index 0000000..749b8cc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cmplx__dot__prod.html
@@ -0,0 +1,276 @@
+
+
+
+
+CMSIS DSP Software Library: Complex Dot Product
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Complex Dot Product

+
+[Complex Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_cmplx_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, float32_t *realResult, float32_t *imagResult)
void arm_cmplx_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, q63_t *imagResult)
void arm_cmplx_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, q31_t *imagResult)

+
Detailed Description

+
Computes the dot product of two complex vectors. The vectors are multiplied element-by-element and then summed.

+
The pSrcA points to the first complex input vector and pSrcB points to the second complex input vector. numSamples specifies the number of complex samples and the data in each array is stored in an interleaved fashion (real, imag, real, imag, ...). Each array has a total of 2*numSamples values.

+
The underlying algorithm is used: 

+
   
+ realResult=0;   
+ imagResult=0;   
+ for(n=0; n<numSamples; n++) {   
+     realResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+0] - pSrcA[(2*n)+1]*pSrcB[(2*n)+1];   
+     imagResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+1] + pSrcA[(2*n)+1]*pSrcB[(2*n)+0];   
+ }   
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_dot_prod_f32 (float32_t *  pSrcA, 
float32_t *  pSrcB, 
uint32_t  numSamples, 
float32_t *  realResult, 
float32_t *  imagResult 
)

+

+

+
+
Floating-point complex dot product. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
*pSrcApoints to the first input vector 
*pSrcBpoints to the second input vector 
numSamplesnumber of complex samples in each vector 
*realResultreal part of the result returned here 
*imagResultimaginary part of the result returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 77 of file arm_cmplx_dot_prod_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_dot_prod_q31 (q31_t *  pSrcA, 
q31_t *  pSrcB, 
uint32_t  numSamples, 
q63_t *  realResult, 
q63_t *  imagResult 
)

+

+

+
+
Q31 complex dot product. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
*pSrcApoints to the first input vector 
*pSrcBpoints to the second input vector 
numSamplesnumber of complex samples in each vector 
*realResultreal part of the result returned here 
*imagResultimaginary part of the result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format. The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits. Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768. The return results realResult and imagResult are in 16.48 format. Input down scaling is not required. 

+
+
Definition at line 60 of file arm_cmplx_dot_prod_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+        
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+          
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_dot_prod_q15 (q15_t *  pSrcA, 
q15_t *  pSrcB, 
uint32_t  numSamples, 
q31_t *  realResult, 
q31_t *  imagResult 
)

+

+

+
+
Q15 complex dot product. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
*pSrcApoints to the first input vector 
*pSrcBpoints to the second input vector 
numSamplesnumber of complex samples in each vector 
*realResultreal part of the result returned here 
*imagResultimaginary part of the result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 64-bit accumulator. The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result. These are accumulated in a 64-bit accumulator with 34.30 precision. As a final step, the accumulators are converted to 8.24 format. The return results realResult and imagResult are in 8.24 format. 

+
+
Definition at line 59 of file arm_cmplx_dot_prod_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cmplx__mag.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cmplx__mag.html
new file mode 100644
index 0000000..b111237
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cmplx__mag.html
@@ -0,0 +1,231 @@
+
+
+
+
+CMSIS DSP Software Library: Complex Magnitude
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Complex Magnitude

+
+[Complex Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_cmplx_mag_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)

+
Detailed Description

+
Computes the magnitude of the elements of a complex data vector.

+
The pSrc points to the source data and pDst points to the where the result should be written. numSamples specifies the number of complex samples in the input array and the data is stored in an interleaved fashion (real, imag, real, imag, ...). The input array has a total of 2*numSamples values; the output array has a total of numSamples values. The underlying algorithm is used:

+
   
+ for(n=0; n<numSamples; n++) {   
+     pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);   
+ }   
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_f32 (float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Floating-point complex magnitude. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to complex input buffer 
[out]*pDstpoints to real output buffer 
[in]numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_fft_bin_example_f32.c.

+

+
Definition at line 73 of file arm_cmplx_mag_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_q31 (q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q31 complex magnitude. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format. Input down scaling is not required. 

+
+
Definition at line 54 of file arm_cmplx_mag_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_q15 (q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q15 complex magnitude. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format. 

+
+
Definition at line 54 of file arm_cmplx_mag_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cmplx__mag__squared.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cmplx__mag__squared.html
new file mode 100644
index 0000000..84fe8dc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cmplx__mag__squared.html
@@ -0,0 +1,231 @@
+
+
+
+
+CMSIS DSP Software Library: Complex Magnitude Squared
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Complex Magnitude Squared

+
+[Complex Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_cmplx_mag_squared_f32 (float32_t *pSrc, float32_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_squared_q31 (q31_t *pSrc, q31_t *pDst, uint32_t numSamples)
void arm_cmplx_mag_squared_q15 (q15_t *pSrc, q15_t *pDst, uint32_t numSamples)

+
Detailed Description

+
Computes the magnitude squared of the elements of a complex data vector.

+
The pSrc points to the source data and pDst points to the where the result should be written. numSamples specifies the number of complex samples in the input array and the data is stored in an interleaved fashion (real, imag, real, imag, ...). The input array has a total of 2*numSamples values; the output array has a total of numSamples values.

+
The underlying algorithm is used:

+
   
+ for(n=0; n<numSamples; n++) {   
+     pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;   
+ }   
+ 
There are separate functions for floating-point, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_squared_f32 (float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Floating-point complex magnitude squared. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the complex input vector 
[out]*pDstpoints to the real output vector 
[in]numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 74 of file arm_cmplx_mag_squared_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_squared_q31 (q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q31 complex magnitude squared. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. Input down scaling is not required. 

+
+
Definition at line 55 of file arm_cmplx_mag_squared_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_cmplx_mag_squared_q15 (q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  numSamples 
)

+

+

+
+
Q15 complex magnitude squared. 

+
Parameters:

+  
+    
+    
+    
+  
*pSrcpoints to the complex input vector 
*pDstpoints to the real output vector 
numSamplesnumber of complex samples in the input vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. 

+
+
Definition at line 53 of file arm_cmplx_mag_squared_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__copy.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__copy.html
new file mode 100644
index 0000000..a511c79
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__copy.html
@@ -0,0 +1,271 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Copy
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Copy

+
+[Support Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_copy_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_copy_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_copy_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_copy_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Copies sample by sample from source vector to destination vector.

+
   
+ 	pDst[n] = pSrc[n];   0 <= n < blockSize.   
+ 
There are separate functions for floating point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_copy_f32 (float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Copies the elements of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_convolution_example_f32.c, arm_signal_converge_example_f32.c, and arm_variance_example_f32.c.

+

+
Definition at line 66 of file arm_copy_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_copy_q31 (q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Copies the elements of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_copy_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_copy_q15 (q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Copies the elements of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 52 of file arm_copy_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_copy_q7 (q7_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Copies the elements of a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to input vector 
[out]*pDstpoints to output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 53 of file arm_copy_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cos.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cos.html
new file mode 100644
index 0000000..763f78b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__cos.html
@@ -0,0 +1,258 @@
+
+
+
+
+CMSIS DSP Software Library: Cosine
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
Cosine

+
+[Fast Math Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+

+Functions
float32_t arm_cos_f32 (float32_t x)
q31_t arm_cos_q31 (q31_t x)
q15_t arm_cos_q15 (q15_t x)

+Variables
static const float32_t cosTable [259]
static const q31_t cosTableQ31 [259]
static const q15_t cosTableQ15 [259]

+
Detailed Description

+
Computes the trigonometric cosine function using a combination of table lookup and cubic interpolation. There are separate functions for Q15, Q31, and floating-point data types. The input to the floating-point version is in radians while the fixed-point Q15 and Q31 have a scaled input with the range [0 1) mapping to [0 2*pi).

+
The implementation is based on table lookup using 256 values together with cubic interpolation. The steps used are:

+
    
+
  1. Calculation of the nearest integer table index
    2. 
+
  2. Fetch the four table values a, b, c, and d
    3. 
+
  3. Compute the fractional portion (fract) of the table index.
    4. 
+
  4. Calculation of wa, wb, wc, wd
    5. 
+
  5. The final result equals a*wa + b*wb + c*wc + d*wd
    6. 
+

+
where 

+
   
+    a=Table[index-1];   
+    b=Table[index+0];   
+    c=Table[index+1];   
+    d=Table[index+2];   
+ 
 and 

+
   
+    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;   
+    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;   
+    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;   
+    wd=(1/6)*fract.^3 - (1/6)*fract;   
+ 
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
float32_t arm_cos_f32 (float32_t  x )

+

+

+
+
Fast approximation to the trigonometric cosine function for floating-point data. 

+
Parameters:

+  
+    
+  
[in]xinput value in radians. 

+  

+

+
Returns:
cos(x). 

+
Examples: 
arm_sin_cos_example_f32.c.

+

+
Definition at line 192 of file arm_cos_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
q31_t arm_cos_q31 (q31_t  x )

+

+

+
+
Fast approximation to the trigonometric cosine function for Q31 data. 

+
Parameters:

+  
+    
+  
[in]xScaled input value in radians. 

+  

+

+
Returns:
cos(x).

+
The Q31 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi). 

+
+
Definition at line 136 of file arm_cos_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
q15_t arm_cos_q15 (q15_t  x )

+

+

+
+
Fast approximation to the trigonometric cosine function for Q15 data. 

+
Parameters:

+  
+    
+  
[in]xScaled input value in radians. 

+  

+

+
Returns:
cos(x).

+
The Q15 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi). 

+
+
Definition at line 105 of file arm_cos_q15.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t cosTable[259] [static]

+

+

+
Example code for Generation of Cos Table: tableSize = 256; 
for(n = -1; n < (tableSize + 1); n++)   
+ {   
+	cosTable[n+1]= cos(2*pi*n/tableSize);   
+ } 
 where pi value is 3.14159265358979 

+
+
Definition at line 86 of file arm_cos_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t cosTableQ31[259] [static]

+

+

+
Table Values are in Q31(1.31 Fixed point format) and generation is done in three steps First Generate cos values in floating point: tableSize = 256; 
for(n = -1; n < (tableSize + 1); n++)   
+ {   
+	cosTable[n+1]= cos(2*pi*n/tableSize);   
+ } 
 where pi value is 3.14159265358979 

+
Secondly Convert Floating point to Q31(Fixed point): (cosTable[i] * pow(2, 31)) 

+
Finally Rounding to nearest integer is done cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5); 

+
+
Definition at line 60 of file arm_cos_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t cosTableQ15[259] [static]

+

+

+
Table Values are in Q15(1.15 Fixed point format) and generation is done in three steps 

+
First Generate cos values in floating point: tableSize = 256; 
for(n = -1; n < (tableSize + 1); n++)   
+ {   
+	cosTable[n+1]= cos(2*pi*n/tableSize);   
+ }
 where pi value is 3.14159265358979 

+
Secondly Convert Floating point to Q15(Fixed point): (cosTable[i] * pow(2, 15)) 

+
Finally Rounding to nearest integer is done cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5); 

+
+
Definition at line 60 of file arm_cos_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__dot__prod.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__dot__prod.html
new file mode 100644
index 0000000..878073c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__dot__prod.html
@@ -0,0 +1,302 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Dot Product
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Dot Product

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_dot_prod_f32 (float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result)
void arm_dot_prod_q31 (q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result)
void arm_dot_prod_q15 (q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result)
void arm_dot_prod_q7 (q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result)

+
Detailed Description

+
Computes the dot product of two vectors. The vectors are multiplied element-by-element and then summed. There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dot_prod_f32 (float32_t *  pSrcA, 
float32_t *  pSrcB, 
uint32_t  blockSize, 
float32_t *  result 
)

+

+

+
+
Dot product of floating-point vectors. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_variance_example_f32.c.

+

+
Definition at line 62 of file arm_dot_prod_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dot_prod_q31 (q31_t *  pSrcA, 
q31_t *  pSrcB, 
uint32_t  blockSize, 
q63_t *  result 
)

+

+

+
+
Dot product of Q31 vectors. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these are truncated to 2.48 format by discarding the lower 14 bits. The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. There are 15 guard bits in the accumulator and there is no risk of overflow as long as the length of the vectors is less than 2^16 elements. The return result is in 16.48 format. 

+
+
Definition at line 62 of file arm_dot_prod_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dot_prod_q15 (q15_t *  pSrcA, 
q15_t *  pSrcB, 
uint32_t  blockSize, 
q63_t *  result 
)

+

+

+
+
Dot product of Q15 vectors. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these results are added to a 64-bit accumulator in 34.30 format. Nonsaturating additions are used and given that there are 33 guard bits in the accumulator there is no risk of overflow. The return result is in 34.30 format. 

+
+
Definition at line 61 of file arm_dot_prod_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_dot_prod_q7 (q7_t *  pSrcA, 
q7_t *  pSrcB, 
uint32_t  blockSize, 
q31_t *  result 
)

+

+

+
+
Dot product of Q7 vectors. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcApoints to the first input vector 
[in]*pSrcBpoints to the second input vector 
[in]blockSizenumber of samples in each vector 
[out]*resultoutput result returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these results are added to an accumulator in 18.14 format. Nonsaturating additions are used and there is no danger of wrap around as long as the vectors are less than 2^18 elements long. The return result is in 18.14 format. 

+
+
Definition at line 61 of file arm_dot_prod_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:19 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__float__to__x.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__float__to__x.html
new file mode 100644
index 0000000..6b4dde5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__float__to__x.html
@@ -0,0 +1,240 @@
+
+
+
+
+CMSIS DSP Software Library: Convert 32-bit floating point value
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Convert 32-bit floating point value

+
+[Support Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_float_to_q31 (float32_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_float_to_q15 (float32_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_float_to_q7 (float32_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q31 (float32_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the floating-point vector to Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the floating-point input vector 
[out]*pDstpoints to the Q31 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.   
+ 
 Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.

+
Note:
In order to apply rounding, the library should be rebuilt with the ROUNDING macro defined in the preprocessor section of project options. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 69 of file arm_float_to_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q15 (float32_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the floating-point vector to Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the floating-point input vector 
[out]*pDstpoints to the Q15 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is: 
   
+ 	pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.   
+ 
 

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
Note:
In order to apply rounding, the library should be rebuilt with the ROUNDING macro defined in the preprocessor section of project options. 

+
+
Definition at line 65 of file arm_float_to_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_float_to_q7 (float32_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the floating-point vector to Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the floating-point input vector 
[out]*pDstpoints to the Q7 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is: 
   
+ 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.   
+ 
 

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. 

+
Note:
In order to apply rounding, the library should be rebuilt with the ROUNDING macro defined in the preprocessor section of project options. 

+
+
Definition at line 64 of file arm_float_to_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_cmplx_math.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_cmplx_math.html
new file mode 100644
index 0000000..dc545bf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_cmplx_math.html
@@ -0,0 +1,81 @@
+
+
+
+
+CMSIS DSP Software Library: Complex Math Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Complex Math Functions
  

+

+

+
+
+
+
+
+
+
+
+

+Modules
 Complex Conjugate
 Complex Dot Product
 Complex Magnitude
 Complex Magnitude Squared
 Complex-by-Complex Multiplication
 Complex-by-Real Multiplication

+
Detailed Description

+
This set of functions operates on complex data vectors. The data in the complex arrays is stored in an interleaved fashion (real, imag, real, imag, ...). In the API functions, the number of samples in a complex array refers to the number of complex values; the array contains twice this number of real values. 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_controller.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_controller.html
new file mode 100644
index 0000000..2762057
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_controller.html
@@ -0,0 +1,79 @@
+
+
+
+
+CMSIS DSP Software Library: Controller Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Controller Functions
  

+

+

+
+
+
+
+
+
+
+
+

+Modules
 Sine Cosine
 PID Motor Control
 Vector Clarke Transform
 Vector Inverse Clarke Transform
 Vector Park Transform
 Vector Inverse Park transform

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_examples.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_examples.html
new file mode 100644
index 0000000..cc4969c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_examples.html
@@ -0,0 +1,84 @@
+
+
+
+
+CMSIS DSP Software Library: Examples
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Examples
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Modules
 Class Marks Example
 Convolution Example
 Dot Product Example
 FIR Lowpass Filter Example
 Frequency Bin Example
 Graphic Audio Equalizer Example
 Linear Interpolate Example
 Matrix Example
 Signal Convergence Example
 SineCosine Example
 Variance Example

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_fast_math.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_fast_math.html
new file mode 100644
index 0000000..2b8978a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_fast_math.html
@@ -0,0 +1,78 @@
+
+
+
+
+CMSIS DSP Software Library: Fast Math Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Fast Math Functions
  

+

+

+
+
+
+
+
+

+Modules
 Cosine
 Sine
 Square Root

+
Detailed Description

+
This set of functions provides a fast approximation to sine, cosine, and square root. As compared to most of the other functions in the CMSIS math library, the fast math functions operate on individual values and not arrays. There are separate functions for Q15, Q31, and floating-point data. 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_filters.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_filters.html
new file mode 100644
index 0000000..6a16cc1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_filters.html
@@ -0,0 +1,87 @@
+
+
+
+
+CMSIS DSP Software Library: Filtering Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Filtering Functions
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+Modules
 Biquad Cascade IIR Filters Using Direct Form I Structure
 Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
 High Precision Q31 Biquad Cascade Filter
 Convolution
 Partial Convolution
 Correlation
 Finite Impulse Response (FIR) Decimator
 Finite Impulse Response (FIR) Filters
 Finite Impulse Response (FIR) Lattice Filters
 Finite Impulse Response (FIR) Sparse Filters
 Infinite Impulse Response (IIR) Lattice Filters
 Least Mean Square (LMS) Filters
 Normalized LMS Filters
 Finite Impulse Response (FIR) Interpolator

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_interpolation.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_interpolation.html
new file mode 100644
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--- /dev/null
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@@ -0,0 +1,77 @@
+
+
+
+
+CMSIS DSP Software Library: Interpolation Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Interpolation Functions
  

+

+

+
+
+
+
+

+Modules
 Linear Interpolation
 Bilinear Interpolation

+
Detailed Description

+
These functions perform 1- and 2-dimensional interpolation of data. Linear interpolation is used for 1-dimensional data and bilinear interpolation is used for 2-dimensional data. 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_math.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_math.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_math.html
@@ -0,0 +1,82 @@
+
+
+
+
+CMSIS DSP Software Library: Basic Math Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Basic Math Functions
  

+

+

+
+
+
+
+
+
+
+
+
+
+
+

+Modules
 Vector Absolute Value
 Vector Addition
 Vector Dot Product
 Vector Multiplication
 Vector Negate
 Vector Offset
 Vector Scale
 Vector Shift
 Vector Subtraction

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_matrix.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_matrix.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_matrix.html
@@ -0,0 +1,106 @@
+
+
+
+
+CMSIS DSP Software Library: Matrix Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Matrix Functions
  

+

+

+
+
+
+
+
+
+
+
+
+

+Modules
 Matrix Addition
 Matrix Initialization
 Matrix Inverse
 Matrix Multiplication
 Matrix Scale
 Matrix Subtraction
 Matrix Transpose

+
Detailed Description

+
This set of functions provides basic matrix math operations. The functions operate on matrix data structures. For example, the type definition for the floating-point matrix structure is shown below: 

+
+     typedef struct
+     {
+       uint16_t numRows;     // number of rows of the matrix.
+       uint16_t numCols;     // number of columns of the matrix.
+       float32_t *pData;     // points to the data of the matrix.
+     } arm_matrix_instance_f32;
+ 
 There are similar definitions for Q15 and Q31 data types.

+
The structure specifies the size of the matrix and then points to an array of data. The array is of size numRows X numCols and the values are arranged in row order. That is, the matrix element (i, j) is stored at: 

+
+     pData[i*numCols + j]
+ 
Init Functions
There is an associated initialization function for each type of matrix data structure. The initialization function sets the values of the internal structure fields. Refer to the function arm_mat_init_f32(), arm_mat_init_q31() and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.

+
Use of the initialization function is optional. However, if initialization function is used then the instance structure cannot be placed into a const data section. To place the instance structure in a const data section, manually initialize the data structure. For example: 
+ arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ 
 where nRows specifies the number of rows, nColumns specifies the number of columns, and pData points to the data array.

+
Size Checking
By default all of the matrix functions perform size checking on the input and output matrices. For example, the matrix addition function verifies that the two input matrices and the output matrix all have the same number of rows and columns. If the size check fails the functions return: 
+     ARM_MATH_SIZE_MISMATCH
+ 
 Otherwise the functions return 
+     ARM_MATH_SUCCESS
+ 
 There is some overhead associated with this matrix size checking. The matrix size checking is enabled via the define 
+     ARM_MATH_MATRIX_CHECK
+ 
 within the library project settings. By default this macro is defined and size checking is enabled. By changing the project settings and undefining this macro size checking is eliminated and the functions run a bit faster. With size checking disabled the functions always return ARM_MATH_SUCCESS. 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_stats.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_stats.html
new file mode 100644
index 0000000..1e0ed8a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_stats.html
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+
+
+
+
+CMSIS DSP Software Library: Statistics Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Statistics Functions
  

+

+

+
+
+
+
+
+
+
+
+
+

+Modules
 Maximum
 Mean
 Minimum
 Power
 Root mean square (RMS)
 Standard deviation
 Variance

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_support.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_support.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_support.html
@@ -0,0 +1,79 @@
+
+
+
+
+CMSIS DSP Software Library: Support Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Support Functions
  

+

+

+
+
+
+
+
+
+
+
+

+Modules
 Convert 16-bit Integer value
 Convert 32-bit Integer value
 Convert 32-bit floating point value
 Convert 8-bit Integer value
 Vector Copy
 Vector Fill

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_transforms.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_transforms.html
new file mode 100644
index 0000000..fad94d4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__group_transforms.html
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+
+
+
+
+CMSIS DSP Software Library: Transform Functions
+
+
+
+
+
+
+
+
+
+

+  

+Modules  

+  

+
Transform Functions
  

+

+

+
+
+
+
+
+

+Modules
 Complex FFT Functions
 DCT Type IV Functions
 Real FFT Functions

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__inv__clarke.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__inv__clarke.html
new file mode 100644
index 0000000..a4d75a0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__inv__clarke.html
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+
+
+
+
+CMSIS DSP Software Library: Vector Inverse Clarke Transform
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Inverse Clarke Transform

+
+[Controller Functions]
+
  

+

+

+
+
+
+
+

+Functions
static __INLINE void arm_inv_clarke_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pIa, float32_t *pIb)
static __INLINE void arm_inv_clarke_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pIa, q31_t *pIb)

+
Detailed Description

+
Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.

+
The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 

+
Algorithm

+clarkeInvFormula.gif
+

+ where pIa and pIb are the instantaneous stator phases and Ialpha and Ibeta are the two coordinates of time invariant vector. 

+
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Clarke transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
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+          
+          
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+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_inv_clarke_f32 (float32_t  Ialpha, 
float32_t  Ibeta, 
float32_t *  pIa, 
float32_t *  pIb 
) [static]

+

+

+
+
Floating-point Inverse Clarke transform. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]Ialphainput two-phase orthogonal vector axis alpha 
[in]Ibetainput two-phase orthogonal vector axis beta 
[out]*pIapoints to output three-phase coordinate a 
[out]*pIbpoints to output three-phase coordinate b 

+  

+

+
Returns:
none. 

+
+
Definition at line 5009 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_inv_clarke_q31 (q31_t  Ialpha, 
q31_t  Ibeta, 
q31_t *  pIa, 
q31_t *  pIb 
) [static]

+

+

+
+
Inverse Clarke transform for Q31 version. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]Ialphainput two-phase orthogonal vector axis alpha 
[in]Ibetainput two-phase orthogonal vector axis beta 
[out]*pIapoints to output three-phase coordinate a 
[out]*pIbpoints to output three-phase coordinate b 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the subtraction, hence there is no risk of overflow. 

+
+
Definition at line 5038 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__inv__park.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__inv__park.html
new file mode 100644
index 0000000..a97fddc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__inv__park.html
@@ -0,0 +1,223 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Inverse Park transform
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Inverse Park transform

+
+[Controller Functions]
+
  

+

+

+
+
+
+
+

+Functions
static __INLINE void arm_inv_park_f32 (float32_t Id, float32_t Iq, float32_t *pIalpha, float32_t *pIbeta, float32_t sinVal, float32_t cosVal)
static __INLINE void arm_inv_park_q31 (q31_t Id, q31_t Iq, q31_t *pIalpha, q31_t *pIbeta, q31_t sinVal, q31_t cosVal)

+
Detailed Description

+
Inverse Park transform converts the input flux and torque components to two-coordinate vector.

+
The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 

+
Algorithm

+parkInvFormula.gif
+

+ where pIalpha and pIbeta are the stator vector components, Id and Iq are rotor vector components and cosVal and sinVal are the cosine and sine values of theta (rotor flux position). 

+
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Park transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_inv_park_f32 (float32_t  Id, 
float32_t  Iq, 
float32_t *  pIalpha, 
float32_t *  pIbeta, 
float32_t  sinVal, 
float32_t  cosVal 
) [static]

+

+

+
+
Floating-point Inverse Park transform. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]Idinput coordinate of rotor reference frame d 
[in]Iqinput coordinate of rotor reference frame q 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 

+  

+

+
Returns:
none. 

+
+
Definition at line 5244 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
static __INLINE void arm_inv_park_q31 (q31_t  Id, 
q31_t  Iq, 
q31_t *  pIalpha, 
q31_t *  pIbeta, 
q31_t  sinVal, 
q31_t  cosVal 
) [static]

+

+

+
+
Inverse Park transform for Q31 version. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]Idinput coordinate of rotor reference frame d 
[in]Iqinput coordinate of rotor reference frame q 
[out]*pIalphapoints to output two-phase orthogonal vector axis alpha 
[out]*pIbetapoints to output two-phase orthogonal vector axis beta 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition, hence there is no risk of overflow. 

+
+
Definition at line 5279 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__mean.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__mean.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__mean.html
@@ -0,0 +1,277 @@
+
+
+
+
+CMSIS DSP Software Library: Mean
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Mean

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_mean_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_mean_q31 (q31_t *pSrc, uint32_t blockSize, q31_t *pResult)
void arm_mean_q15 (q15_t *pSrc, uint32_t blockSize, q15_t *pResult)
void arm_mean_q7 (q7_t *pSrc, uint32_t blockSize, q7_t *pResult)

+
Detailed Description

+
Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector. The underlying algorithm is used:

+
   
+ 	Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;   
+ 
There are separate functions for floating-point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
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+          
+          
+        
+      
void arm_mean_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult 
)

+

+

+
+
Mean value of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 64 of file arm_mean_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
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+        
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+          
+          
+          
+        
+      
void arm_mean_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult 
)

+

+

+
+
Mean value of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.31 format and is accumulated in a 64-bit accumulator in 33.31 format. There is no risk of internal overflow with this approach, and the full precision of intermediate result is preserved. Finally, the accumulator is truncated to yield a result of 1.31 format. 

+
+
Definition at line 61 of file arm_mean_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+          
+          
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+          
+        
+        
+          
+          
+          
+        
+      
void arm_mean_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q15_t *  pResult 
)

+

+

+
+
Mean value of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 32-bit internal accumulator. The input is represented in 1.15 format and is accumulated in a 32-bit accumulator in 17.15 format. There is no risk of internal overflow with this approach, and the full precision of intermediate result is preserved. Finally, the accumulator is saturated and truncated to yield a result of 1.15 format. 

+
+
Definition at line 61 of file arm_mean_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
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+        
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+          
+          
+          
+        
+      
void arm_mean_q7 (q7_t *  pSrc, 
uint32_t  blockSize, 
q7_t *  pResult 
)

+

+

+
+
Mean value of a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultmean value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using a 32-bit internal accumulator. The input is represented in 1.7 format and is accumulated in a 32-bit accumulator in 25.7 format. There is no risk of internal overflow with this approach, and the full precision of intermediate result is preserved. Finally, the accumulator is truncated to yield a result of 1.7 format. 

+
+
Definition at line 61 of file arm_mean_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__negate.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__negate.html
new file mode 100644
index 0000000..f128295
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__negate.html
@@ -0,0 +1,275 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Negate
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Negate

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_negate_f32 (float32_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_negate_q31 (q31_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_negate_q15 (q15_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_negate_q7 (q7_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Negates the elements of a vector.

+
   
+     pDst[n] = -pSrc[n],   0 <= n < blockSize.   
+ 
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
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+          
+          
+        
+      
void arm_negate_f32 (float32_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Negates the elements of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 62 of file arm_negate_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+          
+        
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+          
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+          
+        
+        
+          
+          
+          
+        
+      
void arm_negate_q31 (q31_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Negates the elements of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. 

+
+
Definition at line 57 of file arm_negate_q31.c.

+
+

+

+
+

+

+      
+        
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+          
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+          
+        
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+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_negate_q15 (q15_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Negates the elements of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. 

+
+
Definition at line 57 of file arm_negate_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
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+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_negate_q7 (q7_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Negates the elements of a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. 

+
+
Definition at line 57 of file arm_negate_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__offset.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__offset.html
new file mode 100644
index 0000000..2160d79
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__offset.html
@@ -0,0 +1,304 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Offset
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Offset

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_offset_f32 (float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize)
void arm_offset_q31 (q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize)
void arm_offset_q15 (q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize)
void arm_offset_q7 (q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Adds a constant offset to each element of a vector.

+
   
+     pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.   
+ 
There are separate functions for floating-point, Q7, Q15, and Q31 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
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+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_offset_f32 (float32_t *  pSrc, 
float32_t  offset, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Adds a constant offset to a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none. 

+
+
Definition at line 66 of file arm_offset_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
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+          
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+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_offset_q31 (q31_t *  pSrc, 
q31_t  offset, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Adds a constant offset to a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. 

+
+
Definition at line 58 of file arm_offset_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
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+        
+        
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+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_offset_q15 (q15_t *  pSrc, 
q15_t  offset, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Adds a constant offset to a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. 

+
+
Definition at line 58 of file arm_offset_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_offset_q7 (q7_t *  pSrc, 
q7_t  offset, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Adds a constant offset to a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]offsetis the offset to be added 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x80 0x7F] are saturated. 

+
+
Definition at line 58 of file arm_offset_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__park.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__park.html
new file mode 100644
index 0000000..c29f989
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__park.html
@@ -0,0 +1,227 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Park Transform
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Park Transform

+
+[Controller Functions]
+
  

+

+

+
+
+
+
+

+Functions
static __INLINE void arm_park_f32 (float32_t Ialpha, float32_t Ibeta, float32_t *pId, float32_t *pIq, float32_t sinVal, float32_t cosVal)
static __INLINE void arm_park_q31 (q31_t Ialpha, q31_t Ibeta, q31_t *pId, q31_t *pIq, q31_t sinVal, q31_t cosVal)

+
Detailed Description

+
Forward Park transform converts the input two-coordinate vector to flux and torque components. The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents from the stationary to the moving reference frame and control the spatial relationship between the stator vector current and rotor flux vector. If we consider the d axis aligned with the rotor flux, the diagram below shows the current vector and the relationship from the two reference frames: 

+

+park.gif
+
Stator current space vector and its component in (a,b) and in the d,q rotating reference frame

+
 The function operates on a single sample of data and each call to the function returns the processed output. The library provides separate functions for Q31 and floating-point data types. 

+
Algorithm

+parkFormula.gif
+

+ where Ialpha and Ibeta are the stator vector components, pId and pIq are rotor vector components and cosVal and sinVal are the cosine and sine values of theta (rotor flux position). 

+
Fixed-Point Behavior
Care must be taken when using the Q31 version of the Park transform. In particular, the overflow and saturation behavior of the accumulator used must be considered. Refer to the function specific documentation below for usage guidelines. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+        
+      
static __INLINE void arm_park_f32 (float32_t  Ialpha, 
float32_t  Ibeta, 
float32_t *  pId, 
float32_t *  pIq, 
float32_t  sinVal, 
float32_t  cosVal 
) [static]

+

+

+
+
Floating-point Park transform. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]Ialphainput two-phase vector coordinate alpha 
[in]Ibetainput two-phase vector coordinate beta 
[out]*pIdpoints to output rotor reference frame d 
[out]*pIqpoints to output rotor reference frame q 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 

+  

+

+
Returns:
none.

+
The function implements the forward Park transform. 

+
+
Definition at line 5125 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
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+          
+          
+          
+        
+      
static __INLINE void arm_park_q31 (q31_t  Ialpha, 
q31_t  Ibeta, 
q31_t *  pId, 
q31_t *  pIq, 
q31_t  sinVal, 
q31_t  cosVal 
) [static]

+

+

+
+
Park transform for Q31 version. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+    
+  
[in]Ialphainput two-phase vector coordinate alpha 
[in]Ibetainput two-phase vector coordinate beta 
[out]*pIdpoints to output rotor reference frame d 
[out]*pIqpoints to output rotor reference frame q 
[in]sinValsine value of rotation angle theta 
[in]cosValcosine value of rotation angle theta 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function is implemented using an internal 32-bit accumulator. The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. There is saturation on the addition and subtraction, hence there is no risk of overflow. 

+
+
Definition at line 5159 of file arm_math.h.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__power.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__power.html
new file mode 100644
index 0000000..ffd63a6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__power.html
@@ -0,0 +1,276 @@
+
+
+
+
+CMSIS DSP Software Library: Power
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Power

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_power_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_power_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
void arm_power_q15 (q15_t *pSrc, uint32_t blockSize, q63_t *pResult)
void arm_power_q7 (q7_t *pSrc, uint32_t blockSize, q31_t *pResult)

+
Detailed Description

+
Calculates the sum of the squares of the elements in the input vector. The underlying algorithm is used:

+
   
+ 	Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];   
+ 
There are separate functions for floating point, Q31, Q15, and Q7 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_power_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult 
)

+

+

+
+
Sum of the squares of the elements of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 

+  

+

+
Returns:
none. 

+
+
Definition at line 68 of file arm_power_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
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+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_power_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q63_t *  pResult 
)

+

+

+
+
Sum of the squares of the elements of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.31 format. Intermediate multiplication yields a 2.62 format, and this result is truncated to 2.48 format by discarding the lower 14 bits. The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. With 15 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the return result is in 16.48 format. 

+
+
Definition at line 63 of file arm_power_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_power_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q63_t *  pResult 
)

+

+

+
+
Sum of the squares of the elements of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the return result is in 34.30 format. 

+
+
Definition at line 62 of file arm_power_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
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+        
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+        
+          
+          
+          
+        
+      
void arm_power_q7 (q7_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult 
)

+

+

+
+
Sum of the squares of the elements of a Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultsum of the squares value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 32-bit internal accumulator. The input is represented in 1.7 format. Intermediate multiplication yields a 2.14 format, and this result is added without saturation to an accumulator in 18.14 format. With 17 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the return result is in 18.14 format. 

+
+
Definition at line 62 of file arm_power_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__q15__to__x.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__q15__to__x.html
new file mode 100644
index 0000000..9db84bf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__q15__to__x.html
@@ -0,0 +1,230 @@
+
+
+
+
+CMSIS DSP Software Library: Convert 16-bit Integer value
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Convert 16-bit Integer value

+
+[Support Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_q15_to_float (q15_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_q15_to_q31 (q15_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_q15_to_q7 (q15_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Function Documentation

+
+

+

+      
+        
+          
+          
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+        
+      
void arm_q15_to_float (q15_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q15 vector to floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q15 input vector 
[out]*pDstpoints to the floating-point output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.   
+ 
 
+
Definition at line 66 of file arm_q15_to_float.c.

+
+

+

+
+

+

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+          
+        
+      
void arm_q15_to_q31 (q15_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q15 vector to Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q15 input vector 
[out]*pDstpoints to the Q31 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.   
+ 
 
+
Definition at line 59 of file arm_q15_to_q31.c.

+
+

+

+
+

+

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+          
+          
+          
+        
+      
void arm_q15_to_q7 (q15_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q15 vector to Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q15 input vector 
[out]*pDstpoints to the Q7 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.   
+ 
 
+
Definition at line 60 of file arm_q15_to_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__q31__to__x.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__q31__to__x.html
new file mode 100644
index 0000000..05af0fc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__q31__to__x.html
@@ -0,0 +1,231 @@
+
+
+
+
+CMSIS DSP Software Library: Convert 32-bit Integer value
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Convert 32-bit Integer value

+
+[Support Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_q31_to_float (q31_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_q31_to_q15 (q31_t *pSrc, q15_t *pDst, uint32_t blockSize)
void arm_q31_to_q7 (q31_t *pSrc, q7_t *pDst, uint32_t blockSize)

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
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+          
+          
+          
+        
+      
void arm_q31_to_float (q31_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q31 vector to floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q31 input vector 
[out]*pDstpoints to the floating-point output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.   
+ 
 
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 63 of file arm_q31_to_float.c.

+
+

+

+
+

+

+      
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+      
void arm_q31_to_q15 (q31_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q31 vector to Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q31 input vector 
[out]*pDstpoints to the Q15 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.   
+ 
 
+
Definition at line 59 of file arm_q31_to_q15.c.

+
+

+

+
+

+

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+        
+      
void arm_q31_to_q7 (q31_t *  pSrc, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q31 vector to Q7 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q31 input vector 
[out]*pDstpoints to the Q7 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.    
+ 
 
+
Definition at line 59 of file arm_q31_to_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__q7__to__x.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__q7__to__x.html
new file mode 100644
index 0000000..f360d8a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__q7__to__x.html
@@ -0,0 +1,230 @@
+
+
+
+
+CMSIS DSP Software Library: Convert 8-bit Integer value
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Convert 8-bit Integer value

+
+[Support Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_q7_to_float (q7_t *pSrc, float32_t *pDst, uint32_t blockSize)
void arm_q7_to_q31 (q7_t *pSrc, q31_t *pDst, uint32_t blockSize)
void arm_q7_to_q15 (q7_t *pSrc, q15_t *pDst, uint32_t blockSize)

+
Function Documentation

+
+

+

+      
+        
+          
+          
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+        
+      
void arm_q7_to_float (q7_t *  pSrc, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q7 vector to floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q7 input vector 
[out]*pDstpoints to the floating-point output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.   
+ 
 
+
Definition at line 63 of file arm_q7_to_float.c.

+
+

+

+
+

+

+      
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+      
void arm_q7_to_q31 (q7_t *  pSrc, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q7 vector to Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q7 input vector 
[out]*pDstpoints to the Q31 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.  
+ 
 
+
Definition at line 59 of file arm_q7_to_q31.c.

+
+

+

+
+

+

+      
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+        
+      
void arm_q7_to_q15 (q7_t *  pSrc, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Converts the elements of the Q7 vector to Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the Q7 input vector 
[out]*pDstpoints to the Q15 output vector 
[in]blockSizelength of the input vector 

+  

+

+
Returns:
none.

+
Description: 

+
The equation used for the conversion process is:

+
   
+ 	pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.   
+ 
 
+
Definition at line 62 of file arm_q7_to_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__scale.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__scale.html
new file mode 100644
index 0000000..0fa7215
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__scale.html
@@ -0,0 +1,332 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Scale
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Scale

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+
+

+Functions
void arm_scale_f32 (float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize)
void arm_scale_q31 (q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize)
void arm_scale_q15 (q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize)
void arm_scale_q7 (q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Multiply a vector by a scalar value. For floating-point data, the algorithm used is:

+
   
+     pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.   
+ 
In the fixed-point Q7, Q15, and Q31 functions, scale is represented by a fractional multiplication scaleFract and an arithmetic shift shift. The shift allows the gain of the scaling operation to exceed 1.0. The algorithm used with fixed-point data is:

+
   
+     pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.   
+ 
The overall scale factor applied to the fixed-point data is 

+
   
+     scale = scaleFract * 2^shift.   
+ 
 
Function Documentation

+
+

+

+      
+        
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+      
void arm_scale_f32 (float32_t *  pSrc, 
float32_t  scale, 
float32_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Multiplies a floating-point vector by a scalar. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]scalescale factor to be applied 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none. 

+
Examples: 
arm_graphic_equalizer_example_q31.c, and arm_signal_converge_example_f32.c.

+

+
Definition at line 78 of file arm_scale_f32.c.

+
+

+

+
+

+

+      
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+      
void arm_scale_q31 (q31_t *  pSrc, 
q31_t  scaleFract, 
int8_t  shift, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Multiplies a Q31 vector by a scalar. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]scaleFractfractional portion of the scale value 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.31 format. These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. 

+
Examples: 
arm_graphic_equalizer_example_q31.c.

+

+
Definition at line 59 of file arm_scale_q31.c.

+
+

+

+
+

+

+      
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void arm_scale_q15 (q15_t *  pSrc, 
q15_t  scaleFract, 
int8_t  shift, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Multiplies a Q15 vector by a scalar. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]scaleFractfractional portion of the scale value 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.15 format. These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. 

+
+
Definition at line 60 of file arm_scale_q15.c.

+
+

+

+
+

+

+      
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+      
void arm_scale_q7 (q7_t *  pSrc, 
q7_t  scaleFract, 
int8_t  shift, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Multiplies a Q7 vector by a scalar. 

+
Parameters:

+  
+    
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]scaleFractfractional portion of the scale value 
[in]shiftnumber of bits to shift the result by 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The input data *pSrc and scaleFract are in 1.7 format. These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. 

+
+
Definition at line 59 of file arm_scale_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__shift.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__shift.html
new file mode 100644
index 0000000..e6a73c1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__shift.html
@@ -0,0 +1,250 @@
+
+
+
+
+CMSIS DSP Software Library: Vector Shift
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Vector Shift

+
+[Basic Math Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_shift_q31 (q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize)
void arm_shift_q15 (q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize)
void arm_shift_q7 (q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize)

+
Detailed Description

+
Shifts the elements of a fixed-point vector by a specified number of bits. There are separate functions for Q7, Q15, and Q31 data types. The underlying algorithm used is:

+
   
+     pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.   
+ 
If shift is positive then the elements of the vector are shifted to the left. If shift is negative then the elements of the vector are shifted to the right. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
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+        
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+        
+      
void arm_shift_q31 (q31_t *  pSrc, 
int8_t  shiftBits, 
q31_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Shifts the elements of a Q31 vector a specified number of bits. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]shiftBitsnumber of bits to shift. A positive value shifts left; a negative value shifts right. 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. 

+
+
Definition at line 73 of file arm_shift_q31.c.

+
+

+

+
+

+

+      
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+        
+      
void arm_shift_q15 (q15_t *  pSrc, 
int8_t  shiftBits, 
q15_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Shifts the elements of a Q15 vector a specified number of bits. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]shiftBitsnumber of bits to shift. A positive value shifts left; a negative value shifts right. 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 

+
+
Definition at line 58 of file arm_shift_q15.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_shift_q7 (q7_t *  pSrc, 
int8_t  shiftBits, 
q7_t *  pDst, 
uint32_t  blockSize 
)

+

+

+
+
Shifts the elements of a Q7 vector a specified number of bits. 

+
Parameters:

+  
+    
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]shiftBitsnumber of bits to shift. A positive value shifts left; a negative value shifts right. 
[out]*pDstpoints to the output vector 
[in]blockSizenumber of samples in the vector 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior: 

+
The function uses saturating arithmetic. Results outside of the allowable Q7 range [0x8 0x7F] will be saturated. 

+
+
Definition at line 59 of file arm_shift_q7.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__sin.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__sin.html
new file mode 100644
index 0000000..8e1a751
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__sin.html
@@ -0,0 +1,261 @@
+
+
+
+
+CMSIS DSP Software Library: Sine
+
+
+
+
+
+
+
+
+
+

+  

+Functions |
+Variables  

+  

+
Sine

+
+[Fast Math Functions]
+
  

+

+

+
+
+
+
+
+
+
+
+
+

+Functions
float32_t arm_sin_f32 (float32_t x)
q31_t arm_sin_q31 (q31_t x)
q15_t arm_sin_q15 (q15_t x)

+Variables
static const float32_t sinTable [259]
static const q31_t sinTableQ31 [259]
static const q15_t sinTableQ15 [259]

+
Detailed Description

+
Computes the trigonometric sine function using a combination of table lookup and cubic interpolation. There are separate functions for Q15, Q31, and floating-point data types. The input to the floating-point version is in radians while the fixed-point Q15 and Q31 have a scaled input with the range [0 1) mapping to [0 2*pi).

+
The implementation is based on table lookup using 256 values together with cubic interpolation. The steps used are:

+
    
+
  1. Calculation of the nearest integer table index
    2. 
+
  2. Fetch the four table values a, b, c, and d
    3. 
+
  3. Compute the fractional portion (fract) of the table index.
    4. 
+
  4. Calculation of wa, wb, wc, wd
    5. 
+
  5. The final result equals a*wa + b*wb + c*wc + d*wd
    6. 
+

+
where 

+
   
+    a=Table[index-1];   
+    b=Table[index+0];   
+    c=Table[index+1];   
+    d=Table[index+2];   
+ 
 and 

+
   
+    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;   
+    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;   
+    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;   
+    wd=(1/6)*fract.^3 - (1/6)*fract;   
+ 
 
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
float32_t arm_sin_f32 (float32_t  x )

+

+

+
+
Fast approximation to the trigonometric sine function for floating-point data. 

+
Parameters:

+  
+    
+  
[in]xinput value in radians. 

+  

+

+
Returns:
sin(x). 

+
Examples: 
arm_linear_interp_example_f32.c, and arm_sin_cos_example_f32.c.

+

+
Definition at line 195 of file arm_sin_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
q31_t arm_sin_q31 (q31_t  x )

+

+

+
+
Fast approximation to the trigonometric sine function for Q31 data. 

+
Parameters:

+  
+    
+  
[in]xScaled input value in radians. 

+  

+

+
Returns:
sin(x).

+
The Q31 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi). 

+
+
Definition at line 136 of file arm_sin_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+          
+        
+      
q15_t arm_sin_q15 (q15_t  x )

+

+

+
+
Fast approximation to the trigonometric sine function for Q15 data. 

+
Parameters:

+  
+    
+  
[in]xScaled input value in radians. 

+  

+

+
Returns:
sin(x).

+
The Q15 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi). 

+
+
Definition at line 106 of file arm_sin_q15.c.

+
+

+

+
Variable Documentation

+
+

+

+      
+        
+          
+        
+      
const float32_t sinTable[259] [static]

+

+

+
Example code for Generation of Floating-point Sin Table: tableSize = 256; 
for(n = -1; n < (tableSize + 1); n++)   
+ {   
+	sinTable[n+1]=sin(2*pi*n/tableSize);   
+ }
 

+
where pi value is 3.14159265358979 

+
+
Definition at line 88 of file arm_sin_f32.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q31_t sinTableQ31[259] [static]

+

+

+
Tables generated are in Q31(1.31 Fixed point format) Generation of sin values in floating point: 
tableSize = 256;     
+ for(n = -1; n < (tableSize + 1); n++)   
+ {   
+	sinTable[n+1]= sin(2*pi*n/tableSize);   
+ } 
 where pi value is 3.14159265358979 

+
Convert Floating point to Q31(Fixed point): (sinTable[i] * pow(2, 31)) 

+
rounding to nearest integer is done sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); 

+
+
Definition at line 59 of file arm_sin_q31.c.

+
+

+

+
+

+

+      
+        
+          
+        
+      
const q15_t sinTableQ15[259] [static]

+

+

+
Example code for Generation of Q15 Sin Table: 

+
tableSize = 256;   
+ for(n = -1; n < (tableSize + 1); n++)   
+ {   
+	sinTable[n+1]=sin(2*pi*n/tableSize);   
+ } 
 where pi value is 3.14159265358979 

+
Convert Floating point to Q15(Fixed point): (sinTable[i] * pow(2, 15)) 

+
rounding to nearest integer is done sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); 

+
+
Definition at line 61 of file arm_sin_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:20 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__variance.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__variance.html
new file mode 100644
index 0000000..478f25a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/group__variance.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: Variance
+
+
+
+
+
+
+
+
+
+

+  

+Functions  

+  

+
Variance

+
+[Statistics Functions]
+
  

+

+

+
+
+
+
+
+

+Functions
void arm_var_f32 (float32_t *pSrc, uint32_t blockSize, float32_t *pResult)
void arm_var_q31 (q31_t *pSrc, uint32_t blockSize, q63_t *pResult)
void arm_var_q15 (q15_t *pSrc, uint32_t blockSize, q31_t *pResult)

+
Detailed Description

+
Calculates the variance of the elements in the input vector. The underlying algorithm is used:

+
   
+ 	Result = (sumOfSquares - sum2 / blockSize) / (blockSize - 1)
	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]  
+ 
There are separate functions for floating point, Q31, and Q15 data types. 

+
Function Documentation

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_var_f32 (float32_t *  pSrc, 
uint32_t  blockSize, 
float32_t *  pResult 
)

+

+

+
+
Variance of the elements of a floating-point vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultvariance value returned here 

+  

+

+
Returns:
none. 

+
Examples: 
arm_class_marks_example_f32.c.

+

+
Definition at line 69 of file arm_var_f32.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_var_q31 (q31_t *  pSrc, 
uint32_t  blockSize, 
q63_t *  pResult 
)

+

+

+
+
Variance of the elements of a Q31 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultvariance value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using an internal 64-bit accumulator. The input is represented in 1.31 format, and intermediate multiplication yields a 2.62 format. The accumulator maintains full precision of the intermediate multiplication results, but provides only a single guard bit. There is no saturation on intermediate additions. If the accumulator overflows it wraps around and distorts the result. In order to avoid overflows completely the input signal must be scaled down by log2(blockSize) bits, as a total of blockSize additions are performed internally. Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. 

+
+
Definition at line 66 of file arm_var_q31.c.

+
+

+

+
+

+

+      
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+          
+        
+        
+          
+          
+          
+        
+      
void arm_var_q15 (q15_t *  pSrc, 
uint32_t  blockSize, 
q31_t *  pResult 
)

+

+

+
+
Variance of the elements of a Q15 vector. 

+
Parameters:

+  
+    
+    
+    
+  
[in]*pSrcpoints to the input vector 
[in]blockSizelength of the input vector 
[out]*pResultvariance value returned here 

+  

+

+
Returns:
none.

+
Scaling and Overflow Behavior:

+
The function is implemented using a 64-bit internal accumulator. The input is represented in 1.15 format. Intermediate multiplication yields a 2.30 format, and this result is added without saturation to a 64-bit accumulator in 34.30 format. With 33 guard bits in the accumulator, there is no risk of overflow, and the full precision of the intermediate multiplication is preserved. Finally, the 34.30 result is truncated to 34.15 format by discarding the lower 15 bits, and then saturated to yield a result in 1.15 format. 

+
+
Definition at line 64 of file arm_var_q15.c.

+
+

+

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:21 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/index.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/index.html
new file mode 100644
index 0000000..099de2d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/index.html
@@ -0,0 +1,124 @@
+
+
+
+
+CMSIS DSP Software Library: CMSIS DSP Software Library
+
+
+
+
+
+
+
+
+
+

+  

+
CMSIS DSP Software Library 
  

+

+

+
Version1.0.10 
Introduction

+
This user manual describes the CMSIS DSP software library, a suite of common signal processing functions for use on Cortex-M processor based devices.

+
The library is divided into a number of modules each covering a specific category:

+
    
+
  • Basic math functions
    • 
+
  • Fast math functions
    • 
+
  • Complex math functions
    • 
+
  • Filters
    • 
+
  • Matrix functions
    • 
+
  • Transforms
    • 
+
  • Motor control functions
    • 
+
  • Statistical functions
    • 
+
  • Support functions
    • 
+
  • Interpolation functions
    • 
+

+
The library has separate functions for operating on 8-bit integers, 16-bit integers, 32-bit integer and 32-bit floating-point values.

+
Processor Support

+
The library is completely written in C and is fully CMSIS compliant. High performance is achieved through maximum use of Cortex-M4 intrinsics.

+
The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, with the DSP intrinsics being emulated through software.

+
Toolchain Support

+
The library has been developed and tested with MDK-ARM version 4.21. The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.

+
Using the Library

+
The library installer contains prebuilt versions of the libraries in the Lib folder.

+
    
+
  • arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
    • 
+
  • arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
    • 
+
  • arm_cortexM4l_math.lib (Little endian on Cortex-M4)
    • 
+
  • arm_cortexM4b_math.lib (Big endian on Cortex-M4)
    • 
+
  • arm_cortexM3l_math.lib (Little endian on Cortex-M3)
    • 
+
  • arm_cortexM3b_math.lib (Big endian on Cortex-M3)
    • 
+
  • arm_cortexM0l_math.lib (Little endian on Cortex-M0)
    • 
+
  • arm_cortexM0b_math.lib (Big endian on Cortex-M3)
    • 
+

+
The library functions are declared in the public file arm_math.h which is placed in the Include folder. Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single public header file  arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or ARM_MATH_CM0 depending on the target processor in the application.

+
Examples

+
The library ships with a number of examples which demonstrate how to use the library functions.

+
Building the Library

+
The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS folder.

+
    
+
  • arm_cortexM0b_math.uvproj
    • 
+
  • arm_cortexM0l_math.uvproj
    • 
+
  • arm_cortexM3b_math.uvproj
    • 
+
  • arm_cortexM3l_math.uvproj
    • 
+
  • arm_cortexM4b_math.uvproj
    • 
+
  • arm_cortexM4l_math.uvproj
    • 
+
  • arm_cortexM4bf_math.uvproj
    • 
+
  • arm_cortexM4lf_math.uvproj
    • 
+

+
Each library project have differant pre-processor macros.

+
ARM_MATH_CMx: Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target and ARM_MATH_CM0 for building library on cortex-M0 target.

+
ARM_MATH_BIG_ENDIAN: Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.

+
ARM_MATH_MATRIX_CHECK: Define macro for checking on the input and output sizes of matrices

+
ARM_MATH_ROUNDING: Define macro for rounding on support functions

+
__FPU_PRESENT: Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries

+
The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.

+
Copyright Notice

+
Copyright (C) 2010 ARM Limited. All rights reserved. 

+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:15 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/installdox b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/installdox
new file mode 100644
index 0000000..2697a81
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/installdox
@@ -0,0 +1,117 @@
+#!/usr/bin/perl
+
+%subst = ( );
+$quiet   = 0;
+
+if (open(F,"search.cfg"))
+{
+  $_= ; s/[ \t\n]*$//g ; $subst{"_doc"} = $_;
+  $_= ; s/[ \t\n]*$//g ; $subst{"_cgi"} = $_;
+}
+
+while ( @ARGV ) {
+  $_ = shift @ARGV;
+  if ( s/^-// ) {
+    if ( /^l(.*)/ ) {
+      $v = ($1 eq "") ? shift @ARGV : $1;
+      ($v =~ /\/$/) || ($v .= "/");
+      $_ = $v;
+      if ( /(.+)\@(.+)/ ) {
+        if ( exists $subst{$1} ) {
+          $subst{$1} = $2;
+        } else {
+          print STDERR "Unknown tag file $1 given with option -l\n";
+          &usage();
+        }
+      } else {
+        print STDERR "Argument $_ is invalid for option -l\n";
+        &usage();
+      }
+    }
+    elsif ( /^q/ ) {
+      $quiet = 1;
+    }
+    elsif ( /^\?|^h/ ) {
+      &usage();
+    }
+    else {
+      print STDERR "Illegal option -$_\n";
+      &usage();
+    }
+  }
+  else {
+    push (@files, $_ );
+  }
+}
+
+foreach $sub (keys %subst)
+{
+  if ( $subst{$sub} eq "" ) 
+  {
+    print STDERR "No substitute given for tag file `$sub'\n";
+    &usage();
+  }
+  elsif ( ! $quiet && $sub ne "_doc" && $sub ne "_cgi" )
+  {
+    print "Substituting $subst{$sub} for each occurrence of tag file $sub\n"; 
+  }
+}
+
+if ( ! @files ) {
+  if (opendir(D,".")) {
+    foreach $file ( readdir(D) ) {
+      $match = ".html";
+      next if ( $file =~ /^\.\.?$/ );
+      ($file =~ /$match/) && (push @files, $file);
+      ($file =~ "tree.js") && (push @files, $file);
+    }
+    closedir(D);
+  }
+}
+
+if ( ! @files ) {
+  print STDERR "Warning: No input files given and none found!\n";
+}
+
+foreach $f (@files)
+{
+  if ( ! $quiet ) {
+    print "Editing: $f...\n";
+  }
+  $oldf = $f;
+  $f   .= ".bak";
+  unless (rename $oldf,$f) {
+    print STDERR "Error: cannot rename file $oldf\n";
+    exit 1;
+  }
+  if (open(F,"<$f")) {
+    unless (open(G,">$oldf")) {
+      print STDERR "Error: opening file $oldf for writing\n";
+      exit 1;
+    }
+    if ($oldf ne "tree.js") {
+      while () {
+        s/doxygen\=\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\" (href|src)=\"\2/doxygen\=\"$1:$subst{$1}\" \3=\"$subst{$1}/g;
+        print G "$_";
+      }
+    }
+    else {
+      while () {
+        s/\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\", \"\2/\"$1:$subst{$1}\" ,\"$subst{$1}/g;
+        print G "$_";
+      }
+    }
+  } 
+  else {
+    print STDERR "Warning file $f does not exist\n";
+  }
+  unlink $f;
+}
+
+sub usage {
+  print STDERR "Usage: installdox [options] [html-file [html-file ...]]\n";
+  print STDERR "Options:\n";
+  print STDERR "     -l tagfile\@linkName   tag file + URL or directory \n";
+  print STDERR "     -q                    Quiet mode\n\n";
+  exit 1;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/linearInterpExampleMethod1.gif b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/linearInterpExampleMethod1.gif
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/linearInterpExampleMethod2.gif b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/linearInterpExampleMethod2.gif
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/matrixExample.gif b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/matrixExample.gif
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+
+
+
+
+CMSIS DSP Software Library: Module Index
+
+
+
+
+
+
+
+
+
+

+  

+
Modules
  

+

+

+Here is a list of all modules:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_5f.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_5f.html
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--- /dev/null
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@@ -0,0 +1,38 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  __CMSIS_GENERIC
+  arm_math.h
+ 

+

+

+ 

+  __PACKq7
+  arm_math.h
+ 

+

+

+ 

+  __SIMD32
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_61.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_61.html
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_61.html
@@ -0,0 +1,4102 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+

+ 

+  A_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  Ak
+  arm_convolution_example_f32.c
+ 

+

+
+

+ 

+  arm_abs_f32.c
+ 

+

+
+

+ 

+  arm_abs_q15.c
+ 

+

+
+

+ 

+  arm_abs_q31.c
+ 

+

+
+

+ 

+  arm_abs_q7.c
+ 

+

+
+

+ 

+  arm_add_f32.c
+ 

+

+
+

+ 

+  arm_add_q15.c
+ 

+

+
+

+ 

+  arm_add_q31.c
+ 

+

+
+

+ 

+  arm_add_q7.c
+ 

+

+

+ 

+  arm_bilinear_interp_f32
+  arm_math.h
+ 

+

+
+
+
+
+

+ 

+  arm_bilinear_interp_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q7
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_circularRead_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_circularRead_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_circularRead_q7
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_q7
+  arm_math.h
+ 

+

+

+ 

+  arm_clarke_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_clarke_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_conv_q7.c
+ 

+

+
+
+
+
+
+
+
+
+

+ 

+  arm_copy_q7.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_cos_f32.c
+ 

+

+
+

+ 

+  arm_cos_q15.c
+ 

+

+
+

+ 

+  arm_cos_q31.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_fill_q7.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_fir_f32.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_fir_q15.c
+ 

+

+
+

+ 

+  arm_fir_q31.c
+ 

+

+
+

+ 

+  arm_fir_q7.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_inv_clarke_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_clarke_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_park_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_park_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interep_table
+  arm_linear_interp_example_f32.c
+ 

+

+
+

+ 

+  arm_linear_interp_f32
+  arm_math.h
+ 

+

+
+

+ 

+  arm_linear_interp_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q7
+  arm_math.h
+ 

+

+
+

+ 

+  arm_lms_f32.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_lms_q15.c
+ 

+

+
+

+ 

+  arm_lms_q31.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_ARGUMENT_ERROR
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_LENGTH_ERROR
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_NANINF
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_SINGULAR
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_SIZE_MISMATCH
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_SUCCESS
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_TEST_FAILURE
+  arm_math.h
+ 

+

+
+
+
+
+
+

+ 

+  arm_max_f32.c
+ 

+

+
+

+ 

+  arm_max_q15.c
+ 

+

+
+

+ 

+  arm_max_q31.c
+ 

+

+
+

+ 

+  arm_max_q7.c
+ 

+

+
+
+
+
+
+
+
+

+ 

+  arm_mean_q7.c
+ 

+

+
+

+ 

+  arm_min_f32.c
+ 

+

+
+

+ 

+  arm_min_q15.c
+ 

+

+
+

+ 

+  arm_min_q31.c
+ 

+

+
+

+ 

+  arm_min_q7.c
+ 

+

+
+
+
+
+
+
+
+

+ 

+  arm_mult_q7.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_park_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_park_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_pid_f32
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+

+ 

+  arm_pid_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_pid_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_recip_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_recip_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_rms_f32.c
+ 

+

+
+

+ 

+  arm_rms_q15.c
+ 

+

+
+

+ 

+  arm_rms_q31.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_sin_f32.c
+ 

+

+
+

+ 

+  arm_sin_q15.c
+ 

+

+
+

+ 

+  arm_sin_q31.c
+ 

+

+

+ 

+  arm_split_rfft_f32
+  arm_rfft_f32.c
+ 

+

+

+ 

+  arm_split_rfft_q15
+  arm_rfft_q15.c
+ 

+

+

+ 

+  arm_split_rfft_q31
+  arm_rfft_q31.c
+ 

+

+

+ 

+  arm_split_rifft_f32
+  arm_rfft_f32.c
+ 

+

+

+ 

+  arm_split_rifft_q15
+  arm_rfft_q15.c
+ 

+

+

+ 

+  arm_split_rifft_q31
+  arm_rfft_q31.c
+ 

+

+

+ 

+  arm_sqrt_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_sqrt_q15
+  arm_sqrt_q15.c
+ 

+

+
+

+ 

+  arm_sqrt_q31
+  arm_sqrt_q31.c
+ 

+

+
+

+ 

+  arm_status
+  arm_math.h
+ 

+

+
+

+ 

+  arm_std_f32.c
+ 

+

+
+

+ 

+  arm_std_q15.c
+ 

+

+
+

+ 

+  arm_std_q31.c
+ 

+

+
+

+ 

+  arm_sub_f32.c
+ 

+

+
+

+ 

+  arm_sub_q15.c
+ 

+

+
+

+ 

+  arm_sub_q31.c
+ 

+

+
+

+ 

+  arm_sub_q7.c
+ 

+

+
+

+ 

+  arm_var_f32.c
+ 

+

+
+

+ 

+  arm_var_q15.c
+ 

+

+
+

+ 

+  arm_var_q31.c
+ 

+

+
+

+ 

+  armBitRevTable
+  arm_common_tables.c
+ 

+

+

+ 

+  armRecipTableQ15
+  arm_common_tables.c
+ 

+

+

+ 

+  armRecipTableQ31
+  arm_common_tables.c
+ 

+

+

+ 

+  AT_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  ATMA_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  ATMAI_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  AxB
+  arm_convolution_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_62.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_62.html
new file mode 100644
index 0000000..d20bf17
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_62.html
@@ -0,0 +1,110 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  B_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  biquadStateBand1Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  biquadStateBand2Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  biquadStateBand3Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  biquadStateBand4Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  biquadStateBand5Q31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
+
+
+

+ 

+  Bk
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  BLOCK_SIZE
+  arm_fir_example_f32.c
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_63.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_63.html
new file mode 100644
index 0000000..94d9ae9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_63.html
@@ -0,0 +1,140 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  clip_q31_to_q15
+  arm_math.h
+ 

+

+

+ 

+  clip_q31_to_q7
+  arm_math.h
+ 

+

+

+ 

+  clip_q63_to_q15
+  arm_math.h
+ 

+

+

+ 

+  clip_q63_to_q31
+  arm_math.h
+ 

+

+

+ 

+  coeffTable
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  cos_factors_128
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  cos_factors_2048
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  cos_factors_512
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  cos_factorsQ15_128
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  cos_factorsQ15_2048
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  cos_factorsQ15_512
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  cos_factorsQ31_128
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  cos_factorsQ31_2048
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  cos_factorsQ31_512
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  cosOutput
+  arm_sin_cos_example_f32.c
+ 

+

+

+ 

+  cosSquareOutput
+  arm_sin_cos_example_f32.c
+ 

+

+
+

+ 

+  cosTableQ15
+  arm_cos_q15.c
+ 

+

+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_64.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_64.html
new file mode 100644
index 0000000..f57088b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_64.html
@@ -0,0 +1,61 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  DELTA_COEFF
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  DELTA_ERROR
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  DELTA_Q15
+  arm_math.h
+ 

+

+

+ 

+  DELTA_Q31
+  arm_math.h
+ 

+

+

+ 

+  doBitReverse
+  arm_fft_bin_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_65.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_65.html
new file mode 100644
index 0000000..c06f61f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_65.html
@@ -0,0 +1,42 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  err_signal
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

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+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_66.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_66.html
new file mode 100644
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@@ -0,0 +1,89 @@
+
+
+
+
+
+
+
+

+
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+
+
+
+

+ 

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+  arm_fft_bin_example_f32.c
+ 

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+

+ 

+  FIRCoeff_f32
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+ 

+

+

+ 

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+ 

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+

+ 

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+  arm_math.h
+ 

+

+

+ 

+  float64_t
+  arm_math.h
+ 

+

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Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_67.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_67.html
new file mode 100644
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@@ -0,0 +1,32 @@
+
+
+
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+
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+
Loading...

+

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+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

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+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_69.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_69.html
new file mode 100644
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@@ -0,0 +1,59 @@
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+
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+

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+  arm_graphic_equalizer_example_q31.c
+ 

+

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Searching...

+
No Matches

+
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+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_6b.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_6b.html
new file mode 100644
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+
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_6c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_6c.html
new file mode 100644
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@@ -0,0 +1,54 @@
+
+
+
+
+
+
+
+

+
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+
+

+ 

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+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

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+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

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+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  LPF_instance
+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
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+
+

+
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_6d.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_6d.html
new file mode 100644
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+  arm_dotproduct_example_f32.c
+ 

+

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Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_6e.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_6e.html
new file mode 100644
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@@ -0,0 +1,167 @@
+
+
+
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+
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+
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+
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+ 

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+  arm_fir_example_f32.c
+ 

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+ 

+

+
+
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+
+
+

+ 

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+  arm_linear_interp_instance_f32
+ 

+

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Searching...

+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_6f.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_6f.html
new file mode 100644
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@@ -0,0 +1,38 @@
+
+
+
+
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+
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+

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+ 

+

+

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+  arm_graphic_equalizer_example_q31.c
+ 

+

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+
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+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_70.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_70.html
new file mode 100644
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+
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+
+
+
+
+
+

+ 

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+  arm_linear_interp_instance_f32
+ 

+

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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_71.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_71.html
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@@ -0,0 +1,44 @@
+
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+
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+
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+
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+
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+  arm_math.h
+ 

+

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+
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+

+
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_72.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_72.html
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@@ -0,0 +1,89 @@
+
+
+
+
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+
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+
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+

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+ 

+

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+ 

+

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+

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+ 

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+  arm_rfft_init_q31.c
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+

+
+

+ 

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+ 

+

+

+ 

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+ 

+

+

+ 

+  refOutput
+  arm_fir_example_f32.c
+ 

+

+

+ 

+  refVarianceOut
+  arm_variance_example_f32.c
+ 

+

+
Searching...

+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_73.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_73.html
new file mode 100644
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@@ -0,0 +1,164 @@
+
+
+
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+
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+

+
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+

+ 

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+ 

+

+

+ 

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+ 

+

+
+

+ 

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+ 

+

+
+
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+ 

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+ 

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+ 

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+
+
+

+ 

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+ 

+

+

+ 

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+ 

+

+

+ 

+  srcB_buf_f32
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+ 

+

+

+ 

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+ 

+

+
+
+
+

+ 

+  std
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+ 

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+ 

+

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Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_74.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_74.html
new file mode 100644
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@@ -0,0 +1,201 @@
+
+
+
+
+
+
+
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+
Loading...

+

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+

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+ 

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+ 

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+ 

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+ 

+

+
+

+ 

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+ 

+

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+ 

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+ 

+

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+ 

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+  arm_convolution_example_f32.c
+ 

+

+

+ 

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+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  testInputSin_f32
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  TESTLENGTH
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  testLinIntOutput
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+ 

+

+

+ 

+  testMarks_f32
+  arm_class_marks_example_f32.c
+ 

+

+
+
+

+ 

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+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testUnity_f32
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+ 

+

+
+
+

+ 

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+ 

+

+

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+  arm_cfft_radix4_init_q15.c
+ 

+

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+  arm_cfft_radix4_init_q31.c
+ 

+

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Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_75.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_75.html
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+
+
+
+
+
+
+
+

+
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+

+ 

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+ 

+

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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_76.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_76.html
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+
+
+
+
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+
+
+

+
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+

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+  arm_class_marks_example_f32.c
+ 

+

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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_77.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_77.html
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+
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+
+
+
+
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+
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_78.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/all_78.html
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@@ -0,0 +1,57 @@
+
+
+
+
+
+
+
+

+
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+
+

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+  arm_linear_interp_instance_f32
+ 

+

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+

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+  arm_matrix_example_f32.c
+ 

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+
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+
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+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/classes_61.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/classes_61.html
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/close.png b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/close.png
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+
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+

+
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+

+ 

+  __CMSIS_GENERIC
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+

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+  arm_math.h
+ 

+

+

+ 

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+  arm_math.h
+ 

+

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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_62.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_62.html
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+
+
+
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+

+
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+

+ 

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+  arm_fir_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_64.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_64.html
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+
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+

+
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+

+ 

+  DELTA_COEFF
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  DELTA_ERROR
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  DELTA_Q15
+  arm_math.h
+ 

+

+

+ 

+  DELTA_Q31
+  arm_math.h
+ 

+

+
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+
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+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_69.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_69.html
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+
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+

+
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+

+ 

+  INDEX_MASK
+  arm_math.h
+ 

+

+

+ 

+  INPUT_SPACING
+  arm_math.h
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_6d.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_6d.html
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+
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+ 

+  MU
+  arm_signal_converge_example_f32.c
+ 

+

+
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+
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+

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+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_6e.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_6e.html
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+
+
+
+
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+
+
+

+
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+

+ 

+  NUM_TAPS
+  arm_fir_example_f32.c
+ 

+

+

+ 

+  NUMBLOCKS
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  NUMFRAMES
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  NUMSTAGES
+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

+  NUMSTUDENTS
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  NUMSUBJECTS
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  NUMTAPS
+  arm_signal_converge_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_70.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_70.html
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+
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+

+
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+

+ 

+  PI
+  arm_math.h
+ 

+

+
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+
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+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_73.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_73.html
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_74.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_74.html
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+
+
+
+
+
+
+
+

+
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+

+ 

+  TABLE_SIZE
+  arm_math.h
+ 

+

+

+ 

+  TABLE_SPACING_Q15
+  arm_math.h
+ 

+

+

+ 

+  TABLE_SPACING_Q31
+  arm_math.h
+ 

+

+
+

+ 

+  TESTLENGTH
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_75.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_75.html
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@@ -0,0 +1,26 @@
+
+
+
+
+
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+
+

+
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+

+ 

+  USE_STATIC_INIT
+  arm_class_marks_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_78.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/defines_78.html
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+
+
+
+
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+

+
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+

+ 

+  XSPACING
+  arm_linear_interp_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/enums_61.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/enums_61.html
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--- /dev/null
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@@ -0,0 +1,26 @@
+
+
+
+
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+
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+

+
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+

+ 

+  arm_status
+  arm_math.h
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/enumvalues_61.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/enumvalues_61.html
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+
+
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+
+
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+

+
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+

+ 

+  ARM_MATH_ARGUMENT_ERROR
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_LENGTH_ERROR
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_NANINF
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_SINGULAR
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_SIZE_MISMATCH
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_SUCCESS
+  arm_math.h
+ 

+

+

+ 

+  ARM_MATH_TEST_FAILURE
+  arm_math.h
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/files_61.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/files_61.html
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+
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+

+
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+ 

+  arm_abs_f32.c
+ 

+

+

+ 

+  arm_abs_q15.c
+ 

+

+

+ 

+  arm_abs_q31.c
+ 

+

+

+ 

+  arm_abs_q7.c
+ 

+

+

+ 

+  arm_add_f32.c
+ 

+

+

+ 

+  arm_add_q15.c
+ 

+

+

+ 

+  arm_add_q31.c
+ 

+

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+ 

+  arm_add_q7.c
+ 

+

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+ 

+  arm_conv_q7.c
+ 

+

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+
+
+

+ 

+  arm_copy_q7.c
+ 

+

+
+
+
+
+
+
+

+ 

+  arm_cos_f32.c
+ 

+

+

+ 

+  arm_cos_q15.c
+ 

+

+

+ 

+  arm_cos_q31.c
+ 

+

+
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+ 

+  arm_fill_q7.c
+ 

+

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+

+ 

+  arm_fir_f32.c
+ 

+

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+
+
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+
+
+
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+

+ 

+  arm_fir_q15.c
+ 

+

+

+ 

+  arm_fir_q31.c
+ 

+

+

+ 

+  arm_fir_q7.c
+ 

+

+
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+

+ 

+  arm_lms_f32.c
+ 

+

+
+
+
+
+
+
+
+
+
+

+ 

+  arm_lms_q15.c
+ 

+

+

+ 

+  arm_lms_q31.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_math.h
+ 

+

+
+

+ 

+  arm_max_f32.c
+ 

+

+

+ 

+  arm_max_q15.c
+ 

+

+

+ 

+  arm_max_q31.c
+ 

+

+

+ 

+  arm_max_q7.c
+ 

+

+
+
+
+

+ 

+  arm_mean_q7.c
+ 

+

+

+ 

+  arm_min_f32.c
+ 

+

+

+ 

+  arm_min_q15.c
+ 

+

+

+ 

+  arm_min_q31.c
+ 

+

+

+ 

+  arm_min_q7.c
+ 

+

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+

+ 

+  arm_mult_q7.c
+ 

+

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+
+
+

+ 

+  arm_rms_f32.c
+ 

+

+

+ 

+  arm_rms_q15.c
+ 

+

+

+ 

+  arm_rms_q31.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_sin_f32.c
+ 

+

+

+ 

+  arm_sin_q15.c
+ 

+

+

+ 

+  arm_sin_q31.c
+ 

+

+
+
+

+ 

+  arm_std_f32.c
+ 

+

+

+ 

+  arm_std_q15.c
+ 

+

+

+ 

+  arm_std_q31.c
+ 

+

+

+ 

+  arm_sub_f32.c
+ 

+

+

+ 

+  arm_sub_q15.c
+ 

+

+

+ 

+  arm_sub_q31.c
+ 

+

+

+ 

+  arm_sub_q7.c
+ 

+

+

+ 

+  arm_var_f32.c
+ 

+

+

+ 

+  arm_var_q15.c
+ 

+

+

+ 

+  arm_var_q31.c
+ 

+

+
+
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+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/functions_61.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/functions_61.html
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index 0000000..aa1936f
--- /dev/null
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@@ -0,0 +1,2450 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+
+
+
+
+
+
+
+

+ 

+  arm_bilinear_interp_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_bilinear_interp_q7
+  arm_math.h
+ 

+

+
+
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+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+

+ 

+  arm_circularRead_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_circularRead_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_circularRead_q7
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_circularWrite_q7
+  arm_math.h
+ 

+

+

+ 

+  arm_clarke_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_clarke_q31
+  arm_math.h
+ 

+

+
+
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+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_inv_clarke_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_clarke_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_park_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_inv_park_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_linear_interp_q7
+  arm_math.h
+ 

+

+
+
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+
+
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+
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+
+
+
+
+
+
+
+

+ 

+  arm_park_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_park_q31
+  arm_math.h
+ 

+

+

+ 

+  arm_pid_f32
+  arm_math.h
+ 

+

+
+
+
+

+ 

+  arm_pid_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_pid_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_recip_q15
+  arm_math.h
+ 

+

+

+ 

+  arm_recip_q31
+  arm_math.h
+ 

+

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

+ 

+  arm_split_rfft_f32
+  arm_rfft_f32.c
+ 

+

+

+ 

+  arm_split_rfft_q15
+  arm_rfft_q15.c
+ 

+

+

+ 

+  arm_split_rfft_q31
+  arm_rfft_q31.c
+ 

+

+

+ 

+  arm_split_rifft_f32
+  arm_rfft_f32.c
+ 

+

+

+ 

+  arm_split_rifft_q15
+  arm_rfft_q15.c
+ 

+

+

+ 

+  arm_split_rifft_q31
+  arm_rfft_q31.c
+ 

+

+

+ 

+  arm_sqrt_f32
+  arm_math.h
+ 

+

+

+ 

+  arm_sqrt_q15
+  arm_sqrt_q15.c
+ 

+

+

+ 

+  arm_sqrt_q31
+  arm_sqrt_q31.c
+ 

+

+
+
+
+
+
+
+
+
+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/functions_63.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/functions_63.html
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index 0000000..8f7169e
--- /dev/null
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@@ -0,0 +1,44 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  clip_q31_to_q15
+  arm_math.h
+ 

+

+

+ 

+  clip_q31_to_q7
+  arm_math.h
+ 

+

+

+ 

+  clip_q63_to_q15
+  arm_math.h
+ 

+

+

+ 

+  clip_q63_to_q31
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/functions_67.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/functions_67.html
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index 0000000..0a70c9e
--- /dev/null
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@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  getinput
+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/functions_6d.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/functions_6d.html
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@@ -0,0 +1,44 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  mult32x64
+  arm_math.h
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/functions_74.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/functions_74.html
new file mode 100644
index 0000000..bf5b59a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/functions_74.html
@@ -0,0 +1,32 @@
+
+
+
+
+
+
+
+

+
Loading...

+

+ 

+  test_signal_converge
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  test_signal_converge_example
+  arm_signal_converge_example_f32.c
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/mag_sel.png b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/mag_sel.png
new file mode 100644
index 0000000..81f6040
Binary files /dev/null and b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/mag_sel.png differ
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/nomatches.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/nomatches.html
new file mode 100644
index 0000000..b1ded27
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/nomatches.html
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
+

+
No Matches

+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/search.css b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/search.css
new file mode 100644
index 0000000..50249e5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/search.css
@@ -0,0 +1,240 @@
+/*---------------- Search Box */
+
+#FSearchBox {
+    float: left;
+}
+
+#searchli {
+    float: right;
+    display: block;
+    width: 170px;
+    height: 36px;
+}
+
+#MSearchBox {
+    white-space : nowrap;
+    position: absolute;
+    float: none;
+    display: inline;
+    margin-top: 8px;
+    right: 0px;
+    width: 170px;
+    z-index: 102;
+}
+
+#MSearchBox .left
+{
+    display:block;
+    position:absolute;
+    left:10px;
+    width:20px;
+    height:19px;
+    background:url('search_l.png') no-repeat;
+    background-position:right;
+}
+
+#MSearchSelect {
+    display:block;
+    position:absolute;
+    width:20px;
+    height:19px;
+}
+
+.left #MSearchSelect {
+    left:4px;
+}
+
+.right #MSearchSelect {
+    right:5px;
+}
+
+#MSearchField {
+    display:block;
+    position:absolute;
+    height:19px;
+    background:url('search_m.png') repeat-x;
+    border:none;
+    width:116px;
+    margin-left:20px;
+    padding-left:4px;
+    color: #909090;
+    outline: none;
+    font: 9pt Arial, Verdana, sans-serif;
+}
+
+#FSearchBox #MSearchField {
+    margin-left:15px;
+}
+
+#MSearchBox .right {
+    display:block;
+    position:absolute;
+    right:10px;
+    top:0px;
+    width:20px;
+    height:19px;
+    background:url('search_r.png') no-repeat;
+    background-position:left;
+}
+
+#MSearchClose {
+    display: none;
+    position: absolute;
+    top: 4px;
+    background : none;
+    border: none;
+    margin: 0px 4px 0px 0px;
+    padding: 0px 0px;
+    outline: none;
+}
+
+.left #MSearchClose {
+    left: 6px;
+}
+
+.right #MSearchClose {
+    right: 2px;
+}
+
+.MSearchBoxActive #MSearchField {
+    color: #000000;
+}
+
+/*---------------- Search filter selection */
+
+#MSearchSelectWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #90A5CE;
+    background-color: #F9FAFC;
+    z-index: 1;
+    padding-top: 4px;
+    padding-bottom: 4px;
+    -moz-border-radius: 4px;
+    -webkit-border-top-left-radius: 4px;
+    -webkit-border-top-right-radius: 4px;
+    -webkit-border-bottom-left-radius: 4px;
+    -webkit-border-bottom-right-radius: 4px;
+    -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+.SelectItem {
+    font: 8pt Arial, Verdana, sans-serif;
+    padding-left:  2px;
+    padding-right: 12px;
+    border: 0px;
+}
+
+span.SelectionMark {
+    margin-right: 4px;
+    font-family: monospace;
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem {
+    display: block;
+    outline-style: none;
+    color: #000000; 
+    text-decoration: none;
+    padding-left:   6px;
+    padding-right: 12px;
+}
+
+a.SelectItem:focus,
+a.SelectItem:active {
+    color: #000000; 
+    outline-style: none;
+    text-decoration: none;
+}
+
+a.SelectItem:hover {
+    color: #FFFFFF;
+    background-color: #3D578C;
+    outline-style: none;
+    text-decoration: none;
+    cursor: pointer;
+    display: block;
+}
+
+/*---------------- Search results window */
+
+iframe#MSearchResults {
+    width: 60ex;
+    height: 15em;
+}
+
+#MSearchResultsWindow {
+    display: none;
+    position: absolute;
+    left: 0; top: 0;
+    border: 1px solid #000;
+    background-color: #EEF1F7;
+}
+
+/* ----------------------------------- */
+
+
+#SRIndex {
+    clear:both; 
+    padding-bottom: 15px;
+}
+
+.SREntry {
+    font-size: 10pt;
+    padding-left: 1ex;
+}
+
+.SRPage .SREntry {
+    font-size: 8pt;
+    padding: 1px 5px;
+}
+
+body.SRPage {
+    margin: 5px 2px;
+}
+
+.SRChildren {
+    padding-left: 3ex; padding-bottom: .5em 
+}
+
+.SRPage .SRChildren {
+    display: none;
+}
+
+.SRSymbol {
+    font-weight: bold; 
+    color: #425E97;
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRScope {
+    display: block;
+    color: #425E97; 
+    font-family: Arial, Verdana, sans-serif;
+    text-decoration: none;
+    outline: none;
+}
+
+a.SRSymbol:focus, a.SRSymbol:active,
+a.SRScope:focus, a.SRScope:active {
+    text-decoration: underline;
+}
+
+.SRPage .SRStatus {
+    padding: 2px 5px;
+    font-size: 8pt;
+    font-style: italic;
+}
+
+.SRResult {
+    display: none;
+}
+
+DIV.searchresults {
+    margin-left: 10px;
+    margin-right: 10px;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/search.js b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/search.js
new file mode 100644
index 0000000..29a24bd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/search.js
@@ -0,0 +1,742 @@
+// Search script generated by doxygen
+// Copyright (C) 2009 by Dimitri van Heesch.
+
+// The code in this file is loosly based on main.js, part of Natural Docs,
+// which is Copyright (C) 2003-2008 Greg Valure
+// Natural Docs is licensed under the GPL.
+
+var indexSectionsWithContent =
+{
+  0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111101011111111111111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000100000100000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  4: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111101011111101110111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  5: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  6: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  7: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+  8: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100001000110100111001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
+};
+
+var indexSectionNames =
+{
+  0: "all",
+  1: "classes",
+  2: "files",
+  3: "functions",
+  4: "variables",
+  5: "typedefs",
+  6: "enums",
+  7: "enumvalues",
+  8: "defines"
+};
+
+function convertToId(search)
+{
+  var result = '';
+  for (i=0;i do a search
+    {
+      this.Search();
+    }
+  }
+
+  this.OnSearchSelectKey = function(evt)
+  {
+    var e = (evt) ? evt : window.event; // for IE
+    if (e.keyCode==40 && this.searchIndex0) // Up
+    {
+      this.searchIndex--;
+      this.OnSelectItem(this.searchIndex);
+    }
+    else if (e.keyCode==13 || e.keyCode==27)
+    {
+      this.OnSelectItem(this.searchIndex);
+      this.CloseSelectionWindow();
+      this.DOMSearchField().focus();
+    }
+    return false;
+  }
+
+  // --------- Actions
+
+  // Closes the results window.
+  this.CloseResultsWindow = function()
+  {
+    this.DOMPopupSearchResultsWindow().style.display = 'none';
+    this.DOMSearchClose().style.display = 'none';
+    this.Activate(false);
+  }
+
+  this.CloseSelectionWindow = function()
+  {
+    this.DOMSearchSelectWindow().style.display = 'none';
+  }
+
+  // Performs a search.
+  this.Search = function()
+  {
+    this.keyTimeout = 0;
+
+    // strip leading whitespace
+    var searchValue = this.DOMSearchField().value.replace(/^ +/, "");
+
+    var code = searchValue.toLowerCase().charCodeAt(0);
+    var hexCode;
+    if (code<16) 
+    {
+      hexCode="0"+code.toString(16);
+    }
+    else 
+    {
+      hexCode=code.toString(16);
+    }
+
+    var resultsPage;
+    var resultsPageWithSearch;
+    var hasResultsPage;
+
+    if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1')
+    {
+       resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';
+       resultsPageWithSearch = resultsPage+'?'+escape(searchValue);
+       hasResultsPage = true;
+    }
+    else // nothing available for this search term
+    {
+       resultsPage = this.resultsPath + '/nomatches.html';
+       resultsPageWithSearch = resultsPage;
+       hasResultsPage = false;
+    }
+
+    window.frames.MSearchResults.location.href = resultsPageWithSearch;  
+    var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();
+
+    if (domPopupSearchResultsWindow.style.display!='block')
+    {
+       var domSearchBox = this.DOMSearchBox();
+       this.DOMSearchClose().style.display = 'inline';
+       if (this.insideFrame)
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         domPopupSearchResultsWindow.style.position = 'relative';
+         domPopupSearchResultsWindow.style.display  = 'block';
+         var width = document.body.clientWidth - 8; // the -8 is for IE :-(
+         domPopupSearchResultsWindow.style.width    = width + 'px';
+         domPopupSearchResults.style.width          = width + 'px';
+       }
+       else
+       {
+         var domPopupSearchResults = this.DOMPopupSearchResults();
+         var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth;
+         var top  = getYPos(domSearchBox) + 20;  // domSearchBox.offsetHeight + 1;
+         domPopupSearchResultsWindow.style.display = 'block';
+         left -= domPopupSearchResults.offsetWidth;
+         domPopupSearchResultsWindow.style.top     = top  + 'px';
+         domPopupSearchResultsWindow.style.left    = left + 'px';
+       }
+    }
+
+    this.lastSearchValue = searchValue;
+    this.lastResultsPage = resultsPage;
+  }
+
+  // -------- Activation Functions
+
+  // Activates or deactivates the search panel, resetting things to 
+  // their default values if necessary. 
+  this.Activate = function(isActive)
+  {
+    if (isActive || // open it
+        this.DOMPopupSearchResultsWindow().style.display == 'block' 
+       )
+    {
+      this.DOMSearchBox().className = 'MSearchBoxActive';
+
+      var searchField = this.DOMSearchField();
+
+      if (searchField.value == this.searchLabel) // clear "Search" term upon entry
+      {  
+        searchField.value = '';  
+        this.searchActive = true;
+      }
+    }
+    else if (!isActive) // directly remove the panel
+    {
+      this.DOMSearchBox().className = 'MSearchBoxInactive';
+      this.DOMSearchField().value   = this.searchLabel;
+      this.searchActive             = false;
+      this.lastSearchValue          = ''
+      this.lastResultsPage          = '';
+    }
+  }
+}
+
+// -----------------------------------------------------------------------
+
+// The class that handles everything on the search results page.
+function SearchResults(name)
+{
+    // The number of matches from the last run of .
+    this.lastMatchCount = 0;
+    this.lastKey = 0;
+    this.repeatOn = false;
+
+    // Toggles the visibility of the passed element ID.
+    this.FindChildElement = function(id)
+    {
+      var parentElement = document.getElementById(id);
+      var element = parentElement.firstChild;
+
+      while (element && element!=parentElement)
+      {
+        if (element.nodeName == 'DIV' && element.className == 'SRChildren')
+        {
+          return element;
+        }
+
+        if (element.nodeName == 'DIV' && element.hasChildNodes())
+        {  
+           element = element.firstChild;  
+        }
+        else if (element.nextSibling)
+        {  
+           element = element.nextSibling;  
+        }
+        else
+        {
+          do
+          {
+            element = element.parentNode;
+          }
+          while (element && element!=parentElement && !element.nextSibling);
+
+          if (element && element!=parentElement)
+          {  
+            element = element.nextSibling;  
+          }
+        }
+      }
+    }
+
+    this.Toggle = function(id)
+    {
+      var element = this.FindChildElement(id);
+      if (element)
+      {
+        if (element.style.display == 'block')
+        {
+          element.style.display = 'none';
+        }
+        else
+        {
+          element.style.display = 'block';
+        }
+      }
+    }
+
+    // Searches for the passed string.  If there is no parameter,
+    // it takes it from the URL query.
+    //
+    // Always returns true, since other documents may try to call it
+    // and that may or may not be possible.
+    this.Search = function(search)
+    {
+      if (!search) // get search word from URL
+      {
+        search = window.location.search;
+        search = search.substring(1);  // Remove the leading '?'
+        search = unescape(search);
+      }
+
+      search = search.replace(/^ +/, ""); // strip leading spaces
+      search = search.replace(/ +$/, ""); // strip trailing spaces
+      search = search.toLowerCase();
+      search = convertToId(search);
+
+      var resultRows = document.getElementsByTagName("div");
+      var matches = 0;
+
+      var i = 0;
+      while (i < resultRows.length)
+      {
+        var row = resultRows.item(i);
+        if (row.className == "SRResult")
+        {
+          var rowMatchName = row.id.toLowerCase();
+          rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_'
+
+          if (search.length<=rowMatchName.length && 
+             rowMatchName.substr(0, search.length)==search)
+          {
+            row.style.display = 'block';
+            matches++;
+          }
+          else
+          {
+            row.style.display = 'none';
+          }
+        }
+        i++;
+      }
+      document.getElementById("Searching").style.display='none';
+      if (matches == 0) // no results
+      {
+        document.getElementById("NoMatches").style.display='block';
+      }
+      else // at least one result
+      {
+        document.getElementById("NoMatches").style.display='none';
+      }
+      this.lastMatchCount = matches;
+      return true;
+    }
+
+    // return the first item with index index or higher that is visible
+    this.NavNext = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index++;
+      }
+      return focusItem;
+    }
+
+    this.NavPrev = function(index)
+    {
+      var focusItem;
+      while (1)
+      {
+        var focusName = 'Item'+index;
+        focusItem = document.getElementById(focusName);
+        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+        {
+          break;
+        }
+        else if (!focusItem) // last element
+        {
+          break;
+        }
+        focusItem=null;
+        index--;
+      }
+      return focusItem;
+    }
+
+    this.ProcessKeys = function(e)
+    {
+      if (e.type == "keydown") 
+      {
+        this.repeatOn = false;
+        this.lastKey = e.keyCode;
+      }
+      else if (e.type == "keypress")
+      {
+        if (!this.repeatOn)
+        {
+          if (this.lastKey) this.repeatOn = true;
+          return false; // ignore first keypress after keydown
+        }
+      }
+      else if (e.type == "keyup")
+      {
+        this.lastKey = 0;
+        this.repeatOn = false;
+      }
+      return this.lastKey!=0;
+    }
+
+    this.Nav = function(evt,itemIndex) 
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        var newIndex = itemIndex-1;
+        var focusItem = this.NavPrev(newIndex);
+        if (focusItem)
+        {
+          var child = this.FindChildElement(focusItem.parentNode.parentNode.id);
+          if (child && child.style.display == 'block') // children visible
+          { 
+            var n=0;
+            var tmpElem;
+            while (1) // search for last child
+            {
+              tmpElem = document.getElementById('Item'+newIndex+'_c'+n);
+              if (tmpElem)
+              {
+                focusItem = tmpElem;
+              }
+              else // found it!
+              {
+                break;
+              }
+              n++;
+            }
+          }
+        }
+        if (focusItem)
+        {
+          focusItem.focus();
+        }
+        else // return focus to search field
+        {
+           parent.document.getElementById("MSearchField").focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = itemIndex+1;
+        var focusItem;
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem && elem.style.display == 'block') // children visible
+        {
+          focusItem = document.getElementById('Item'+itemIndex+'_c0');
+        }
+        if (!focusItem) focusItem = this.NavNext(newIndex);
+        if (focusItem)  focusItem.focus();
+      }
+      else if (this.lastKey==39) // Right
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'block';
+      }
+      else if (this.lastKey==37) // Left
+      {
+        var item = document.getElementById('Item'+itemIndex);
+        var elem = this.FindChildElement(item.parentNode.parentNode.id);
+        if (elem) elem.style.display = 'none';
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+
+    this.NavChild = function(evt,itemIndex,childIndex)
+    {
+      var e  = (evt) ? evt : window.event; // for IE
+      if (e.keyCode==13) return true;
+      if (!this.ProcessKeys(e)) return false;
+
+      if (this.lastKey==38) // Up
+      {
+        if (childIndex>0)
+        {
+          var newIndex = childIndex-1;
+          document.getElementById('Item'+itemIndex+'_c'+newIndex).focus();
+        }
+        else // already at first child, jump to parent
+        {
+          document.getElementById('Item'+itemIndex).focus();
+        }
+      }
+      else if (this.lastKey==40) // Down
+      {
+        var newIndex = childIndex+1;
+        var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex);
+        if (!elem) // last child, jump to parent next parent
+        {
+          elem = this.NavNext(itemIndex+1);
+        }
+        if (elem)
+        {
+          elem.focus();
+        } 
+      }
+      else if (this.lastKey==27) // Escape
+      {
+        parent.searchBox.CloseResultsWindow();
+        parent.document.getElementById("MSearchField").focus();
+      }
+      else if (this.lastKey==13) // Enter
+      {
+        return true;
+      }
+      return false;
+    }
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/search_l.png b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/search_l.png
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/search_m.png b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/search_m.png
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/search_r.png b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/search_r.png
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+  arm_math.h
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+  arm_math.h
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+

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+
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+

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+  arm_math.h
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+  arm_math.h
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+  arm_math.h
+ 

+

+

+ 

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+  arm_math.h
+ 

+

+
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+
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_61.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_61.html
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+
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+
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+ 

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+  arm_matrix_example_f32.c
+ 

+

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+ 

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+  arm_convolution_example_f32.c
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+  arm_linear_interp_example_f32.c
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+

+

+ 

+  AxB
+  arm_convolution_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_62.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_62.html
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+
+
+
+
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+
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+

+ 

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+  arm_matrix_example_f32.c
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+

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+  arm_graphic_equalizer_example_q31.c
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+  arm_graphic_equalizer_example_q31.c
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+  arm_graphic_equalizer_example_q31.c
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+  arm_convolution_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_63.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_63.html
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+
+
+
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+
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+
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+

+ 

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+  arm_graphic_equalizer_example_q31.c
+ 

+

+

+ 

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+  arm_dct4_init_f32.c
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+

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+ 

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+  arm_dct4_init_f32.c
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+ 

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+  arm_dct4_init_f32.c
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+  arm_dct4_init_q15.c
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+  arm_dct4_init_q15.c
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+  arm_dct4_init_q31.c
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+  arm_dct4_init_q31.c
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+

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+  arm_dct4_init_q31.c
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+

+

+ 

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+  arm_sin_cos_example_f32.c
+ 

+

+

+ 

+  cosSquareOutput
+  arm_sin_cos_example_f32.c
+ 

+

+
+

+ 

+  cosTableQ15
+  arm_cos_q15.c
+ 

+

+
+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_64.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_64.html
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+
+
+
+
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+

+
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+

+ 

+  doBitReverse
+  arm_fft_bin_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_65.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_65.html
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+
+
+
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+
+
+
+

+
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+
+

+ 

+  err_signal
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  errOutput
+  arm_signal_converge_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_66.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_66.html
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+
+
+
+
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+
+
+

+
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+
+
+
+

+ 

+  fftSize
+  arm_fft_bin_example_f32.c
+ 

+

+

+ 

+  FIRCoeff_f32
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  firCoeffs32
+  arm_fir_example_f32.c
+ 

+

+
+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_67.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_67.html
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+
+
+
+
+
+
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+

+
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+

+ 

+  gainDB
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_69.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_69.html
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+
+
+
+
+
+
+
+

+
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+
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+

+ 

+  inputQ31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_6b.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_6b.html
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+
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+
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_6c.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_6c.html
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+
+
+
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+

+
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+
+

+ 

+  lmsNorm_instance
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  lmsNormCoeff_f32
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  lmsStateF32
+  arm_signal_converge_example_f32.c
+ 

+

+

+ 

+  LPF_instance
+  arm_signal_converge_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_6d.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_6d.html
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+
+
+
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+
+
+

+
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+
+

+ 

+  max_marks
+  arm_class_marks_example_f32.c
+ 

+

+
+

+ 

+  mean
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

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+  arm_class_marks_example_f32.c
+ 

+

+
+

+ 

+  multOutput
+  arm_dotproduct_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_6e.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_6e.html
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+
+
+
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+
+

+
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+
+
+
+

+ 

+  numBlocks
+  arm_fir_example_f32.c
+ 

+

+
+
+
+

+ 

+  numStudents
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  numSubjects
+  arm_class_marks_example_f32.c
+ 

+

+
+

+ 

+  nValues
+  arm_linear_interp_instance_f32
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_6f.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_6f.html
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@@ -0,0 +1,38 @@
+
+
+
+
+
+
+
+

+
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+

+ 

+  onebyfftLen
+  arm_cfft_radix4_instance_f32
+ 

+

+

+ 

+  outLen
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  outputQ31
+  arm_graphic_equalizer_example_q31.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_70.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_70.html
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+
+
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+
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+
+
+
+
+
+
+
+
+
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+
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+

+ 

+  pYData
+  arm_linear_interp_instance_f32
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_72.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_72.html
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@@ -0,0 +1,89 @@
+
+
+
+
+
+
+
+

+
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+

+ 

+  realCoefA
+  arm_rfft_init_f32.c
+ 

+

+

+ 

+  realCoefAQ15
+  arm_rfft_init_q15.c
+ 

+

+

+ 

+  realCoefAQ31
+  arm_rfft_init_q31.c
+ 

+

+

+ 

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+  arm_rfft_init_f32.c
+ 

+

+

+ 

+  realCoefBQ15
+  arm_rfft_init_q15.c
+ 

+

+

+ 

+  realCoefBQ31
+  arm_rfft_init_q31.c
+ 

+

+
+

+ 

+  refDotProdOut
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  refIndex
+  arm_fft_bin_example_f32.c
+ 

+

+

+ 

+  refOutput
+  arm_fir_example_f32.c
+ 

+

+

+ 

+  refVarianceOut
+  arm_variance_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_73.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_73.html
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--- /dev/null
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@@ -0,0 +1,145 @@
+
+
+
+
+
+
+
+

+
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+

+ 

+  sinOutput
+  arm_sin_cos_example_f32.c
+ 

+

+

+ 

+  sinSquareOutput
+  arm_sin_cos_example_f32.c
+ 

+

+
+

+ 

+  sinTableQ15
+  arm_sin_q15.c
+ 

+

+
+
+

+ 

+  snr1
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  snr2
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  srcA_buf_f32
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  srcALen
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  srcB_buf_f32
+  arm_dotproduct_example_f32.c
+ 

+

+

+ 

+  srcBLen
+  arm_convolution_example_f32.c
+ 

+

+
+
+
+

+ 

+  std
+  arm_class_marks_example_f32.c
+ 

+

+

+ 

+  student_num
+  arm_class_marks_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_74.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_74.html
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@@ -0,0 +1,153 @@
+
+
+
+
+
+
+
+

+
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+

+ 

+  testIndex
+  arm_fft_bin_example_f32.c
+ 

+

+
+

+ 

+  testInput_f32_10khz
+  arm_fft_bin_example_f32.c
+ 

+

+

+ 

+  testInput_f32_1kHz_15kHz
+  arm_fir_example_f32.c
+ 

+

+

+ 

+  testInputA_f32
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  testInputB_f32
+  arm_convolution_example_f32.c
+ 

+

+

+ 

+  testInputSin_f32
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testLinIntOutput
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testMarks_f32
+  arm_class_marks_example_f32.c
+ 

+

+
+
+

+ 

+  testRefSinOutput32_f32
+  arm_linear_interp_example_f32.c
+ 

+

+

+ 

+  testUnity_f32
+  arm_class_marks_example_f32.c
+ 

+

+
+
+

+ 

+  twiddleCoef
+  arm_cfft_radix4_init_f32.c
+ 

+

+

+ 

+  twiddleCoefQ15
+  arm_cfft_radix4_init_q15.c
+ 

+

+

+ 

+  twiddleCoefQ31
+  arm_cfft_radix4_init_q31.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_76.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_76.html
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+
+
+
+
+
+
+
+

+
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+

+ 

+  var
+  arm_class_marks_example_f32.c
+ 

+

+
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+
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+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_77.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_77.html
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+
+
+
+
+
+
+
+

+
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+

+ 

+  Weights_128
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  Weights_2048
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  Weights_512
+  arm_dct4_init_f32.c
+ 

+

+

+ 

+  WeightsQ15_128
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  WeightsQ15_2048
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  WeightsQ15_512
+  arm_dct4_init_q15.c
+ 

+

+

+ 

+  WeightsQ31_128
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  WeightsQ31_2048
+  arm_dct4_init_q31.c
+ 

+

+

+ 

+  WeightsQ31_512
+  arm_dct4_init_q31.c
+ 

+

+
+
+
+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_78.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/search/variables_78.html
new file mode 100644
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@@ -0,0 +1,54 @@
+
+
+
+
+
+
+
+

+
Loading...

+
+

+ 

+  x1
+  arm_linear_interp_instance_f32
+ 

+

+

+ 

+  X_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  xRef_f32
+  arm_matrix_example_f32.c
+ 

+

+

+ 

+  xSpacing
+  arm_linear_interp_instance_f32
+ 

+

+
Searching...

+
No Matches

+
+

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/sinCos.gif b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/sinCos.gif
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__f32.html
new file mode 100644
index 0000000..92861cc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__f32.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_bilinear_interp_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_bilinear_interp_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point bilinear interpolation function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
float32_t * pData

+
Detailed Description

+
Instance structure for the floating-point bilinear interpolation function. 

+
+
Definition at line 1783 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_f32::numRows

+

+

+
number of rows in the data table. 

+
+
Definition at line 1785 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_f32::numCols

+

+

+
number of columns in the data table. 

+
+
Definition at line 1786 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_bilinear_interp_instance_f32::pData

+

+

+
points to the data table. 

+
+
Definition at line 1787 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q15.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q15.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_bilinear_interp_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_bilinear_interp_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 bilinear interpolation function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q15_t * pData

+
Detailed Description

+
Instance structure for the Q15 bilinear interpolation function. 

+
+
Definition at line 1805 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q15::numRows

+

+

+
number of rows in the data table. 

+
+
Definition at line 1807 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q15::numCols

+

+

+
number of columns in the data table. 

+
+
Definition at line 1808 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_bilinear_interp_instance_q15::pData

+

+

+
points to the data table. 

+
+
Definition at line 1809 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q31.html
new file mode 100644
index 0000000..6646773
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q31.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_bilinear_interp_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_bilinear_interp_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 bilinear interpolation function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q31_t * pData

+
Detailed Description

+
Instance structure for the Q31 bilinear interpolation function. 

+
+
Definition at line 1794 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q31::numRows

+

+

+
number of rows in the data table. 

+
+
Definition at line 1796 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q31::numCols

+

+

+
number of columns in the data table. 

+
+
Definition at line 1797 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_bilinear_interp_instance_q31::pData

+

+

+
points to the data table. 

+
+
Definition at line 1798 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q7.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q7.html
new file mode 100644
index 0000000..67de8f6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__bilinear__interp__instance__q7.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_bilinear_interp_instance_q7 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_bilinear_interp_instance_q7 Struct Reference
  

+

+

+
+
Instance structure for the Q15 bilinear interpolation function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q7_t * pData

+
Detailed Description

+
Instance structure for the Q15 bilinear interpolation function. 

+
+
Definition at line 1816 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q7::numRows

+

+

+
number of rows in the data table. 

+
+
Definition at line 1818 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_bilinear_interp_instance_q7::numCols

+

+

+
number of columns in the data table. 

+
+
Definition at line 1819 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_bilinear_interp_instance_q7::pData

+

+

+
points to the data table. 

+
+
Definition at line 1820 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__cas__df1__32x64__ins__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__cas__df1__32x64__ins__q31.html
new file mode 100644
index 0000000..0188826
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__cas__df1__32x64__ins__q31.html
@@ -0,0 +1,163 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cas_df1_32x64_ins_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_biquad_cas_df1_32x64_ins_q31 Struct Reference
  

+

+

+
+
Instance structure for the high precision Q31 Biquad cascade filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t numStages
q63_t * pState
q31_t * pCoeffs
uint8_t postShift

+
Detailed Description

+
Instance structure for the high precision Q31 Biquad cascade filter. 

+
Examples: 

+
arm_graphic_equalizer_example_q31.c.

+

+

+
Definition at line 3539 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_biquad_cas_df1_32x64_ins_q31::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Definition at line 3541 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q63_t* arm_biquad_cas_df1_32x64_ins_q31::pState

+

+

+
points to the array of state coefficients. The array is of length 4*numStages. 

+
+
Definition at line 3542 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_biquad_cas_df1_32x64_ins_q31::pCoeffs

+

+

+
points to the array of coefficients. The array is of length 5*numStages. 

+
+
Definition at line 3543 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_biquad_cas_df1_32x64_ins_q31::postShift

+

+

+
additional shift, in bits, applied to each output sample. 

+
+
Definition at line 3544 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__cascade__df2_t__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__cascade__df2_t__instance__f32.html
new file mode 100644
index 0000000..8e5a8a4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__cascade__df2_t__instance__f32.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_cascade_df2T_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_biquad_cascade_df2T_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point transposed direct form II Biquad cascade filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint8_t numStages
float32_t * pState
float32_t * pCoeffs

+
Detailed Description

+
Instance structure for the floating-point transposed direct form II Biquad cascade filter. 

+
+
Definition at line 3586 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_biquad_cascade_df2T_instance_f32::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Definition at line 3588 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_biquad_cascade_df2T_instance_f32::pState

+

+

+
points to the array of state coefficients. The array is of length 2*numStages. 

+
+
Definition at line 3589 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_biquad_cascade_df2T_instance_f32::pCoeffs

+

+

+
points to the array of coefficients. The array is of length 5*numStages. 

+
+
Definition at line 3590 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__f32.html
new file mode 100644
index 0000000..fb6327b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__f32.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_casd_df1_inst_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_biquad_casd_df1_inst_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point Biquad cascade filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint32_t numStages
float32_t * pState
float32_t * pCoeffs

+
Detailed Description

+
Instance structure for the floating-point Biquad cascade filter. 

+
+
Definition at line 1195 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_biquad_casd_df1_inst_f32::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Definition at line 1197 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_biquad_casd_df1_inst_f32::pState

+

+

+
Points to the array of state coefficients. The array is of length 4*numStages. 

+
+
Definition at line 1198 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_biquad_casd_df1_inst_f32::pCoeffs

+

+

+
Points to the array of coefficients. The array is of length 5*numStages. 

+
+
Definition at line 1199 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__q15.html
new file mode 100644
index 0000000..f0f77eb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__q15.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_casd_df1_inst_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_biquad_casd_df1_inst_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 Biquad cascade filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
int8_t numStages
q15_t * pState
q15_t * pCoeffs
int8_t postShift

+
Detailed Description

+
Instance structure for the Q15 Biquad cascade filter. 

+
+
Definition at line 1170 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
int8_t arm_biquad_casd_df1_inst_q15::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Definition at line 1172 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_biquad_casd_df1_inst_q15::pState

+

+

+
Points to the array of state coefficients. The array is of length 4*numStages. 

+
+
Definition at line 1173 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_biquad_casd_df1_inst_q15::pCoeffs

+

+

+
Points to the array of coefficients. The array is of length 5*numStages. 

+
+
Definition at line 1174 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
int8_t arm_biquad_casd_df1_inst_q15::postShift

+

+

+
Additional shift, in bits, applied to each output sample. 

+
+
Definition at line 1175 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__q31.html
new file mode 100644
index 0000000..2eb8acb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__biquad__casd__df1__inst__q31.html
@@ -0,0 +1,163 @@
+
+
+
+
+CMSIS DSP Software Library: arm_biquad_casd_df1_inst_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_biquad_casd_df1_inst_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 Biquad cascade filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint32_t numStages
q31_t * pState
q31_t * pCoeffs
uint8_t postShift

+
Detailed Description

+
Instance structure for the Q31 Biquad cascade filter. 

+
Examples: 

+
arm_graphic_equalizer_example_q31.c.

+

+

+
Definition at line 1183 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_biquad_casd_df1_inst_q31::numStages

+

+

+
number of 2nd order stages in the filter. Overall order is 2*numStages. 

+
+
Definition at line 1185 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_biquad_casd_df1_inst_q31::pState

+

+

+
Points to the array of state coefficients. The array is of length 4*numStages. 

+
+
Definition at line 1186 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_biquad_casd_df1_inst_q31::pCoeffs

+

+

+
Points to the array of coefficients. The array is of length 5*numStages. 

+
+
Definition at line 1187 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_biquad_casd_df1_inst_q31::postShift

+

+

+
Additional shift, in bits, applied to each output sample. 

+
+
Definition at line 1188 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__f32.html
new file mode 100644
index 0000000..eba95d4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__f32.html
@@ -0,0 +1,231 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_cfft_radix4_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point CFFT/CIFFT function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t fftLen
uint8_t ifftFlag
uint8_t bitReverseFlag
float32_t * pTwiddle
uint16_t * pBitRevTable
uint16_t twidCoefModifier
uint16_t bitRevFactor
float32_t onebyfftLen

+
Detailed Description

+
Instance structure for the floating-point CFFT/CIFFT function. 

+
Examples: 

+
arm_convolution_example_f32.c, and arm_fft_bin_example_f32.c.

+

+

+
Definition at line 1919 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_f32::fftLen

+

+

+
length of the FFT. 

+
+
Definition at line 1921 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_f32::ifftFlag

+

+

+
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 

+
+
Definition at line 1922 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_f32::bitReverseFlag

+

+

+
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+
+
Definition at line 1923 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_cfft_radix4_instance_f32::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Definition at line 1924 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t* arm_cfft_radix4_instance_f32::pBitRevTable

+

+

+
points to the bit reversal table. 

+
+
Definition at line 1925 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_f32::twidCoefModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Definition at line 1926 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_f32::bitRevFactor

+

+

+
bit reversal modifier that supports different size FFTs with the same bit reversal table. 

+
+
Definition at line 1927 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_cfft_radix4_instance_f32::onebyfftLen

+

+

+
value of 1/fftLen. 

+
+
Definition at line 1928 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__q15.html
new file mode 100644
index 0000000..7604ba2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__q15.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_cfft_radix4_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 CFFT/CIFFT function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t fftLen
uint8_t ifftFlag
uint8_t bitReverseFlag
q15_t * pTwiddle
uint16_t * pBitRevTable
uint16_t twidCoefModifier
uint16_t bitRevFactor

+
Detailed Description

+
Instance structure for the Q15 CFFT/CIFFT function. 

+
+
Definition at line 1889 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q15::fftLen

+

+

+
length of the FFT. 

+
+
Definition at line 1891 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_q15::ifftFlag

+

+

+
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 

+
+
Definition at line 1892 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_q15::bitReverseFlag

+

+

+
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+
+
Definition at line 1893 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_cfft_radix4_instance_q15::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Definition at line 1894 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t* arm_cfft_radix4_instance_q15::pBitRevTable

+

+

+
points to the bit reversal table. 

+
+
Definition at line 1895 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q15::twidCoefModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Definition at line 1896 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q15::bitRevFactor

+

+

+
bit reversal modifier that supports different size FFTs with the same bit reversal table. 

+
+
Definition at line 1897 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__q31.html
new file mode 100644
index 0000000..f8d1e78
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__cfft__radix4__instance__q31.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_cfft_radix4_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_cfft_radix4_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 CFFT/CIFFT function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t fftLen
uint8_t ifftFlag
uint8_t bitReverseFlag
q31_t * pTwiddle
uint16_t * pBitRevTable
uint16_t twidCoefModifier
uint16_t bitRevFactor

+
Detailed Description

+
Instance structure for the Q31 CFFT/CIFFT function. 

+
+
Definition at line 1904 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q31::fftLen

+

+

+
length of the FFT. 

+
+
Definition at line 1906 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_q31::ifftFlag

+

+

+
flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. 

+
+
Definition at line 1907 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_cfft_radix4_instance_q31::bitReverseFlag

+

+

+
flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. 

+
+
Definition at line 1908 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_cfft_radix4_instance_q31::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Definition at line 1909 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t* arm_cfft_radix4_instance_q31::pBitRevTable

+

+

+
points to the bit reversal table. 

+
+
Definition at line 1910 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q31::twidCoefModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Definition at line 1911 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_cfft_radix4_instance_q31::bitRevFactor

+

+

+
bit reversal modifier that supports different size FFTs with the same bit reversal table. 

+
+
Definition at line 1912 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__f32.html
new file mode 100644
index 0000000..d3efbc5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__f32.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_dct4_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point DCT4/IDCT4 function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t N
uint16_t Nby2
float32_t normalize
float32_t * pTwiddle
float32_t * pCosFactor
arm_rfft_instance_f32 * pRfft
arm_cfft_radix4_instance_f32 * pCfft

+
Detailed Description

+
Instance structure for the floating-point DCT4/IDCT4 function. 

+
+
Definition at line 2294 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_f32::N

+

+

+
length of the DCT4. 

+
+
Definition at line 2296 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_f32::Nby2

+

+

+
half of the length of the DCT4. 

+
+
Definition at line 2297 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_dct4_instance_f32::normalize

+

+

+
normalizing factor. 

+
+
Definition at line 2298 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_dct4_instance_f32::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Definition at line 2299 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_dct4_instance_f32::pCosFactor

+

+

+
points to the cosFactor table. 

+
+
Definition at line 2300 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_rfft_instance_f32* arm_dct4_instance_f32::pRfft

+

+

+
points to the real FFT instance. 

+
+
Definition at line 2301 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_f32* arm_dct4_instance_f32::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Definition at line 2302 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__q15.html
new file mode 100644
index 0000000..426d118
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__q15.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_dct4_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 DCT4/IDCT4 function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t N
uint16_t Nby2
q15_t normalize
q15_t * pTwiddle
q15_t * pCosFactor
arm_rfft_instance_q15 * pRfft
arm_cfft_radix4_instance_q15 * pCfft

+
Detailed Description

+
Instance structure for the Q15 DCT4/IDCT4 function. 

+
+
Definition at line 2388 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_q15::N

+

+

+
length of the DCT4. 

+
+
Definition at line 2390 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_q15::Nby2

+

+

+
half of the length of the DCT4. 

+
+
Definition at line 2391 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_dct4_instance_q15::normalize

+

+

+
normalizing factor. 

+
+
Definition at line 2392 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_dct4_instance_q15::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Definition at line 2393 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_dct4_instance_q15::pCosFactor

+

+

+
points to the cosFactor table. 

+
+
Definition at line 2394 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_rfft_instance_q15* arm_dct4_instance_q15::pRfft

+

+

+
points to the real FFT instance. 

+
+
Definition at line 2395 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_q15* arm_dct4_instance_q15::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Definition at line 2396 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__q31.html
new file mode 100644
index 0000000..680576e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__dct4__instance__q31.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_dct4_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_dct4_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 DCT4/IDCT4 function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t N
uint16_t Nby2
q31_t normalize
q31_t * pTwiddle
q31_t * pCosFactor
arm_rfft_instance_q31 * pRfft
arm_cfft_radix4_instance_q31 * pCfft

+
Detailed Description

+
Instance structure for the Q31 DCT4/IDCT4 function. 

+
+
Definition at line 2341 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_q31::N

+

+

+
length of the DCT4. 

+
+
Definition at line 2343 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_dct4_instance_q31::Nby2

+

+

+
half of the length of the DCT4. 

+
+
Definition at line 2344 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_dct4_instance_q31::normalize

+

+

+
normalizing factor. 

+
+
Definition at line 2345 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_dct4_instance_q31::pTwiddle

+

+

+
points to the twiddle factor table. 

+
+
Definition at line 2346 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_dct4_instance_q31::pCosFactor

+

+

+
points to the cosFactor table. 

+
+
Definition at line 2347 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_rfft_instance_q31* arm_dct4_instance_q31::pRfft

+

+

+
points to the real FFT instance. 

+
+
Definition at line 2348 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_q31* arm_dct4_instance_q31::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Definition at line 2349 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__f32.html
new file mode 100644
index 0000000..f77169a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__f32.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_decimate_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point FIR decimator.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t M
uint16_t numTaps
float32_t * pCoeffs
float32_t * pState

+
Detailed Description

+
Instance structure for the floating-point FIR decimator. 

+
+
Definition at line 3239 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_decimate_instance_f32::M

+

+

+
decimation factor. 

+
+
Definition at line 3241 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_decimate_instance_f32::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 3242 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_decimate_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 3243 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_decimate_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 3244 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__q15.html
new file mode 100644
index 0000000..1a9d0d6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__q15.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_decimate_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 FIR decimator.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t M
uint16_t numTaps
q15_t * pCoeffs
q15_t * pState

+
Detailed Description

+
Instance structure for the Q15 FIR decimator. 

+
+
Definition at line 3214 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_decimate_instance_q15::M

+

+

+
decimation factor. 

+
+
Definition at line 3216 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_decimate_instance_q15::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 3217 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_decimate_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 3218 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_decimate_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 3219 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:22 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__q31.html
new file mode 100644
index 0000000..60dfe5b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__decimate__instance__q31.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_decimate_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_decimate_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 FIR decimator.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t M
uint16_t numTaps
q31_t * pCoeffs
q31_t * pState

+
Detailed Description

+
Instance structure for the Q31 FIR decimator. 

+
+
Definition at line 3226 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_decimate_instance_q31::M

+

+

+
decimation factor. 

+
+
Definition at line 3228 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_decimate_instance_q31::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 3229 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_decimate_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 3230 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_decimate_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 3231 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__f32.html
new file mode 100644
index 0000000..ae49eef
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__f32.html
@@ -0,0 +1,146 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numTaps
float32_t * pState
float32_t * pCoeffs

+
Detailed Description

+
Instance structure for the floating-point FIR filter. 

+
Examples: 

+
arm_fir_example_f32.c, and arm_signal_converge_example_f32.c.

+

+

+
Definition at line 1006 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_instance_f32::numTaps

+

+

+
number of filter coefficients in the filter. 

+
+
Definition at line 1008 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 1009 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 1010 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q15.html
new file mode 100644
index 0000000..bd33eab
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q15.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q15_t * pState
q15_t * pCoeffs

+
Detailed Description

+
Instance structure for the Q15 FIR filter. 

+
+
Definition at line 986 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_instance_q15::numTaps

+

+

+
number of filter coefficients in the filter. 

+
+
Definition at line 988 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 989 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 990 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q31.html
new file mode 100644
index 0000000..3e6e20a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q31.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q31_t * pState
q31_t * pCoeffs

+
Detailed Description

+
Instance structure for the Q31 FIR filter. 

+
+
Definition at line 996 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_instance_q31::numTaps

+

+

+
number of filter coefficients in the filter. 

+
+
Definition at line 998 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 999 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 1000 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q7.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q7.html
new file mode 100644
index 0000000..37e77a0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__instance__q7.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_instance_q7 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_instance_q7 Struct Reference
  

+

+

+
+
Instance structure for the Q7 FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q7_t * pState
q7_t * pCoeffs

+
Detailed Description

+
Instance structure for the Q7 FIR filter. 

+
+
Definition at line 976 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_instance_q7::numTaps

+

+

+
number of filter coefficients in the filter. 

+
+
Definition at line 978 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_fir_instance_q7::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 979 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_fir_instance_q7::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 980 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__f32.html
new file mode 100644
index 0000000..3cbdb47
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__f32.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_interpolate_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point FIR interpolator.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t L
uint16_t phaseLength
float32_t * pCoeffs
float32_t * pState

+
Detailed Description

+
Instance structure for the floating-point FIR interpolator. 

+
+
Definition at line 3419 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_interpolate_instance_f32::L

+

+

+
upsample factor. 

+
+
Definition at line 3421 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_interpolate_instance_f32::phaseLength

+

+

+
length of each polyphase filter component. 

+
+
Definition at line 3422 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_interpolate_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length L*phaseLength. 

+
+
Definition at line 3423 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_interpolate_instance_f32::pState

+

+

+
points to the state variable array. The array is of length phaseLength+numTaps-1. 

+
+
Definition at line 3424 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__q15.html
new file mode 100644
index 0000000..5ff68a7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__q15.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_interpolate_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 FIR interpolator.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t L
uint16_t phaseLength
q15_t * pCoeffs
q15_t * pState

+
Detailed Description

+
Instance structure for the Q15 FIR interpolator. 

+
+
Definition at line 3395 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_interpolate_instance_q15::L

+

+

+
upsample factor. 

+
+
Definition at line 3397 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_interpolate_instance_q15::phaseLength

+

+

+
length of each polyphase filter component. 

+
+
Definition at line 3398 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_interpolate_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length L*phaseLength. 

+
+
Definition at line 3399 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_interpolate_instance_q15::pState

+

+

+
points to the state variable array. The array is of length blockSize+phaseLength-1. 

+
+
Definition at line 3400 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__q31.html
new file mode 100644
index 0000000..7c65829
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__interpolate__instance__q31.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_interpolate_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_interpolate_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 FIR interpolator.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint8_t L
uint16_t phaseLength
q31_t * pCoeffs
q31_t * pState

+
Detailed Description

+
Instance structure for the Q31 FIR interpolator. 

+
+
Definition at line 3407 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_fir_interpolate_instance_q31::L

+

+

+
upsample factor. 

+
+
Definition at line 3409 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_interpolate_instance_q31::phaseLength

+

+

+
length of each polyphase filter component. 

+
+
Definition at line 3410 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_interpolate_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length L*phaseLength. 

+
+
Definition at line 3411 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_interpolate_instance_q31::pState

+

+

+
points to the state variable array. The array is of length blockSize+phaseLength-1. 

+
+
Definition at line 3412 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__f32.html
new file mode 100644
index 0000000..0a4a838
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__f32.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_lattice_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point FIR lattice filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numStages
float32_t * pState
float32_t * pCoeffs

+
Detailed Description

+
Instance structure for the floating-point FIR lattice filter. 

+
+
Definition at line 3653 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_lattice_instance_f32::numStages

+

+

+
number of filter stages. 

+
+
Definition at line 3655 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_lattice_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numStages. 

+
+
Definition at line 3656 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_lattice_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numStages. 

+
+
Definition at line 3657 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__q15.html
new file mode 100644
index 0000000..b98bfa6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__q15.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_lattice_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 FIR lattice filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numStages
q15_t * pState
q15_t * pCoeffs

+
Detailed Description

+
Instance structure for the Q15 FIR lattice filter. 

+
+
Definition at line 3631 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_lattice_instance_q15::numStages

+

+

+
number of filter stages. 

+
+
Definition at line 3633 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_lattice_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numStages. 

+
+
Definition at line 3634 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_lattice_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numStages. 

+
+
Definition at line 3635 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__q31.html
new file mode 100644
index 0000000..bbfdc93
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__lattice__instance__q31.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_lattice_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_lattice_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 FIR lattice filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numStages
q31_t * pState
q31_t * pCoeffs

+
Detailed Description

+
Instance structure for the Q31 FIR lattice filter. 

+
+
Definition at line 3642 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_lattice_instance_q31::numStages

+

+

+
number of filter stages. 

+
+
Definition at line 3644 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_lattice_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numStages. 

+
+
Definition at line 3645 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_lattice_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numStages. 

+
+
Definition at line 3646 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__f32.html
new file mode 100644
index 0000000..209ddd3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__f32.html
@@ -0,0 +1,194 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_sparse_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point sparse FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
uint16_t stateIndex
float32_t * pState
float32_t * pCoeffs
uint16_t maxDelay
int32_t * pTapDelay

+
Detailed Description

+
Instance structure for the floating-point sparse FIR filter. 

+
+
Definition at line 4319 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_f32::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4321 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_f32::stateIndex

+

+

+
state buffer index. Points to the oldest sample in the state buffer. 

+
+
Definition at line 4322 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_sparse_instance_f32::pState

+

+

+
points to the state buffer array. The array is of length maxDelay+blockSize-1. 

+
+
Definition at line 4323 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_fir_sparse_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4324 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_f32::maxDelay

+

+

+
maximum offset specified by the pTapDelay array. 

+
+
Definition at line 4325 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
int32_t* arm_fir_sparse_instance_f32::pTapDelay

+

+

+
points to the array of delay values. The array is of length numTaps. 

+
+
Definition at line 4326 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q15.html
new file mode 100644
index 0000000..98cc504
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q15.html
@@ -0,0 +1,194 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_sparse_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 sparse FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
uint16_t stateIndex
q15_t * pState
q15_t * pCoeffs
uint16_t maxDelay
int32_t * pTapDelay

+
Detailed Description

+
Instance structure for the Q15 sparse FIR filter. 

+
+
Definition at line 4347 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q15::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4349 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q15::stateIndex

+

+

+
state buffer index. Points to the oldest sample in the state buffer. 

+
+
Definition at line 4350 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_sparse_instance_q15::pState

+

+

+
points to the state buffer array. The array is of length maxDelay+blockSize-1. 

+
+
Definition at line 4351 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_fir_sparse_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4352 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q15::maxDelay

+

+

+
maximum offset specified by the pTapDelay array. 

+
+
Definition at line 4353 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
int32_t* arm_fir_sparse_instance_q15::pTapDelay

+

+

+
points to the array of delay values. The array is of length numTaps. 

+
+
Definition at line 4354 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q31.html
new file mode 100644
index 0000000..3071cb5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q31.html
@@ -0,0 +1,194 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_sparse_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 sparse FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
uint16_t stateIndex
q31_t * pState
q31_t * pCoeffs
uint16_t maxDelay
int32_t * pTapDelay

+
Detailed Description

+
Instance structure for the Q31 sparse FIR filter. 

+
+
Definition at line 4333 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q31::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4335 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q31::stateIndex

+

+

+
state buffer index. Points to the oldest sample in the state buffer. 

+
+
Definition at line 4336 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_sparse_instance_q31::pState

+

+

+
points to the state buffer array. The array is of length maxDelay+blockSize-1. 

+
+
Definition at line 4337 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_fir_sparse_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4338 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q31::maxDelay

+

+

+
maximum offset specified by the pTapDelay array. 

+
+
Definition at line 4339 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
int32_t* arm_fir_sparse_instance_q31::pTapDelay

+

+

+
points to the array of delay values. The array is of length numTaps. 

+
+
Definition at line 4340 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q7.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q7.html
new file mode 100644
index 0000000..6002906
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__fir__sparse__instance__q7.html
@@ -0,0 +1,194 @@
+
+
+
+
+CMSIS DSP Software Library: arm_fir_sparse_instance_q7 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_fir_sparse_instance_q7 Struct Reference
  

+

+

+
+
Instance structure for the Q7 sparse FIR filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
uint16_t stateIndex
q7_t * pState
q7_t * pCoeffs
uint16_t maxDelay
int32_t * pTapDelay

+
Detailed Description

+
Instance structure for the Q7 sparse FIR filter. 

+
+
Definition at line 4361 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q7::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4363 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q7::stateIndex

+

+

+
state buffer index. Points to the oldest sample in the state buffer. 

+
+
Definition at line 4364 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_fir_sparse_instance_q7::pState

+

+

+
points to the state buffer array. The array is of length maxDelay+blockSize-1. 

+
+
Definition at line 4365 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q7_t* arm_fir_sparse_instance_q7::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4366 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_fir_sparse_instance_q7::maxDelay

+

+

+
maximum offset specified by the pTapDelay array. 

+
+
Definition at line 4367 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
int32_t* arm_fir_sparse_instance_q7::pTapDelay

+

+

+
points to the array of delay values. The array is of length numTaps. 

+
+
Definition at line 4368 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__f32.html
new file mode 100644
index 0000000..0b4bbdf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__f32.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_iir_lattice_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point IIR lattice filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint16_t numStages
float32_t * pState
float32_t * pkCoeffs
float32_t * pvCoeffs

+
Detailed Description

+
Instance structure for the floating-point IIR lattice filter. 

+
+
Definition at line 3776 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_iir_lattice_instance_f32::numStages

+

+

+
number of stages in the filter. 

+
+
Definition at line 3778 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_iir_lattice_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numStages+blockSize. 

+
+
Definition at line 3779 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_iir_lattice_instance_f32::pkCoeffs

+

+

+
points to the reflection coefficient array. The array is of length numStages. 

+
+
Definition at line 3780 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_iir_lattice_instance_f32::pvCoeffs

+

+

+
points to the ladder coefficient array. The array is of length numStages+1. 

+
+
Definition at line 3781 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__q15.html
new file mode 100644
index 0000000..8c1dfef
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__q15.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_iir_lattice_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 IIR lattice filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint16_t numStages
q15_t * pState
q15_t * pkCoeffs
q15_t * pvCoeffs

+
Detailed Description

+
Instance structure for the Q15 IIR lattice filter. 

+
+
Definition at line 3754 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_iir_lattice_instance_q15::numStages

+

+

+
number of stages in the filter. 

+
+
Definition at line 3756 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_iir_lattice_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numStages+blockSize. 

+
+
Definition at line 3757 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_iir_lattice_instance_q15::pkCoeffs

+

+

+
points to the reflection coefficient array. The array is of length numStages. 

+
+
Definition at line 3758 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_iir_lattice_instance_q15::pvCoeffs

+

+

+
points to the ladder coefficient array. The array is of length numStages+1. 

+
+
Definition at line 3759 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__q31.html
new file mode 100644
index 0000000..29ed095
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__iir__lattice__instance__q31.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_iir_lattice_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_iir_lattice_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 IIR lattice filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint16_t numStages
q31_t * pState
q31_t * pkCoeffs
q31_t * pvCoeffs

+
Detailed Description

+
Instance structure for the Q31 IIR lattice filter. 

+
+
Definition at line 3765 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_iir_lattice_instance_q31::numStages

+

+

+
number of stages in the filter. 

+
+
Definition at line 3767 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_iir_lattice_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numStages+blockSize. 

+
+
Definition at line 3768 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_iir_lattice_instance_q31::pkCoeffs

+

+

+
points to the reflection coefficient array. The array is of length numStages. 

+
+
Definition at line 3769 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_iir_lattice_instance_q31::pvCoeffs

+

+

+
points to the ladder coefficient array. The array is of length numStages+1. 

+
+
Definition at line 3770 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__linear__interp__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__linear__interp__instance__f32.html
new file mode 100644
index 0000000..6a7c4ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__linear__interp__instance__f32.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_linear_interp_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_linear_interp_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point Linear Interpolate function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint32_t nValues
float32_t x1
float32_t xSpacing
float32_t * pYData

+
Detailed Description

+
Instance structure for the floating-point Linear Interpolate function. 

+
Examples: 

+
arm_linear_interp_example_f32.c.

+

+

+
Definition at line 1771 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_linear_interp_instance_f32::nValues

+

+

+
+
Definition at line 1773 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_linear_interp_instance_f32::x1

+

+

+
+
Definition at line 1774 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_linear_interp_instance_f32::xSpacing

+

+

+
+
Definition at line 1775 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_linear_interp_instance_f32::pYData

+

+

+
pointer to the table of Y values 

+
+
Definition at line 1776 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__f32.html
new file mode 100644
index 0000000..00173fe
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__f32.html
@@ -0,0 +1,160 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_lms_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point LMS filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
float32_t * pState
float32_t * pCoeffs
float32_t mu

+
Detailed Description

+
Instance structure for the floating-point LMS filter. 

+
+
Definition at line 3894 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_instance_f32::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 3896 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_lms_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 3897 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_lms_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 3898 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_lms_instance_f32::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Definition at line 3899 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__q15.html
new file mode 100644
index 0000000..d9f5e32
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__q15.html
@@ -0,0 +1,177 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_lms_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 LMS filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q15_t * pState
q15_t * pCoeffs
q15_t mu
uint32_t postShift

+
Detailed Description

+
Instance structure for the Q15 LMS filter. 

+
+
Definition at line 3944 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_instance_q15::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 3946 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 3947 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 3948 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_lms_instance_q15::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Definition at line 3949 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_lms_instance_q15::postShift

+

+

+
bit shift applied to coefficients. 

+
+
Definition at line 3950 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__q31.html
new file mode 100644
index 0000000..0bddeb3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__instance__q31.html
@@ -0,0 +1,177 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_lms_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 LMS filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q31_t * pState
q31_t * pCoeffs
q31_t mu
uint32_t postShift

+
Detailed Description

+
Instance structure for the Q31 LMS filter. 

+
+
Definition at line 3999 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_instance_q31::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4001 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 4002 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4003 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_lms_instance_q31::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Definition at line 4004 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_lms_instance_q31::postShift

+

+

+
bit shift applied to coefficients. 

+
+
Definition at line 4005 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__f32.html
new file mode 100644
index 0000000..b017ecd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__f32.html
@@ -0,0 +1,197 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_lms_norm_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point normalized LMS filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
float32_t * pState
float32_t * pCoeffs
float32_t mu
float32_t energy
float32_t x0

+
Detailed Description

+
Instance structure for the floating-point normalized LMS filter. 

+
Examples: 

+
arm_signal_converge_example_f32.c.

+

+

+
Definition at line 4053 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_norm_instance_f32::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4055 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_lms_norm_instance_f32::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 4056 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_lms_norm_instance_f32::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4057 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_lms_norm_instance_f32::mu

+

+

+
step size that control filter coefficient updates. 

+
+
Definition at line 4058 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_lms_norm_instance_f32::energy

+

+

+
saves previous frame energy. 

+
+
Definition at line 4059 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_lms_norm_instance_f32::x0

+

+

+
saves previous input sample. 

+
+
Definition at line 4060 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__q15.html
new file mode 100644
index 0000000..da6419f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__q15.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_lms_norm_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 normalized LMS filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q15_t * pState
q15_t * pCoeffs
q15_t mu
uint8_t postShift
q15_t * recipTable
q15_t energy
q15_t x0

+
Detailed Description

+
Instance structure for the Q15 normalized LMS filter. 

+
+
Definition at line 4161 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_norm_instance_q15::numTaps

+

+

+
Number of coefficients in the filter. 

+
+
Definition at line 4163 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_norm_instance_q15::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 4164 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_norm_instance_q15::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4165 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_lms_norm_instance_q15::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Definition at line 4166 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_lms_norm_instance_q15::postShift

+

+

+
bit shift applied to coefficients. 

+
+
Definition at line 4167 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_lms_norm_instance_q15::recipTable

+

+

+
Points to the reciprocal initial value table. 

+
+
Definition at line 4168 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_lms_norm_instance_q15::energy

+

+

+
saves previous frame energy. 

+
+
Definition at line 4169 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_lms_norm_instance_q15::x0

+

+

+
saves previous input sample. 

+
+
Definition at line 4170 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__q31.html
new file mode 100644
index 0000000..1f12878
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__lms__norm__instance__q31.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: arm_lms_norm_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_lms_norm_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 normalized LMS filter.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint16_t numTaps
q31_t * pState
q31_t * pCoeffs
q31_t mu
uint8_t postShift
q31_t * recipTable
q31_t energy
q31_t x0

+
Detailed Description

+
Instance structure for the Q31 normalized LMS filter. 

+
+
Definition at line 4105 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_lms_norm_instance_q31::numTaps

+

+

+
number of coefficients in the filter. 

+
+
Definition at line 4107 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_norm_instance_q31::pState

+

+

+
points to the state variable array. The array is of length numTaps+blockSize-1. 

+
+
Definition at line 4108 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_norm_instance_q31::pCoeffs

+

+

+
points to the coefficient array. The array is of length numTaps. 

+
+
Definition at line 4109 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_lms_norm_instance_q31::mu

+

+

+
step size that controls filter coefficient updates. 

+
+
Definition at line 4110 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_lms_norm_instance_q31::postShift

+

+

+
bit shift applied to coefficients. 

+
+
Definition at line 4111 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_lms_norm_instance_q31::recipTable

+

+

+
points to the reciprocal initial value table. 

+
+
Definition at line 4112 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_lms_norm_instance_q31::energy

+

+

+
saves previous frame energy. 

+
+
Definition at line 4113 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_lms_norm_instance_q31::x0

+

+

+
saves previous input sample. 

+
+
Definition at line 4114 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__f32.html
new file mode 100644
index 0000000..ed00560
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__f32.html
@@ -0,0 +1,146 @@
+
+
+
+
+CMSIS DSP Software Library: arm_matrix_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_matrix_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point matrix structure.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
float32_t * pData

+
Detailed Description

+
Instance structure for the floating-point matrix structure. 

+
Examples: 

+
arm_class_marks_example_f32.c, and arm_matrix_example_f32.c.

+

+

+
Definition at line 1337 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_f32::numRows

+

+

+
number of rows of the matrix. 

+
+
Definition at line 1339 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_f32::numCols

+

+

+
number of columns of the matrix. 

+
+
Definition at line 1340 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_matrix_instance_f32::pData

+

+

+
points to the data of the matrix. 

+
+
Definition at line 1341 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__q15.html
new file mode 100644
index 0000000..ad22039
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__q15.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_matrix_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_matrix_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 matrix structure.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q15_t * pData

+
Detailed Description

+
Instance structure for the Q15 matrix structure. 

+
+
Definition at line 1348 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_q15::numRows

+

+

+
number of rows of the matrix. 

+
+
Definition at line 1350 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_q15::numCols

+

+

+
number of columns of the matrix. 

+
+
Definition at line 1351 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_matrix_instance_q15::pData

+

+

+
points to the data of the matrix. 

+
+
Definition at line 1352 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__q31.html
new file mode 100644
index 0000000..655ce0b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__matrix__instance__q31.html
@@ -0,0 +1,143 @@
+
+
+
+
+CMSIS DSP Software Library: arm_matrix_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_matrix_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 matrix structure.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+

+Data Fields
uint16_t numRows
uint16_t numCols
q31_t * pData

+
Detailed Description

+
Instance structure for the Q31 matrix structure. 

+
+
Definition at line 1360 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_q31::numRows

+

+

+
number of rows of the matrix. 

+
+
Definition at line 1362 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_matrix_instance_q31::numCols

+

+

+
number of columns of the matrix. 

+
+
Definition at line 1363 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_matrix_instance_q31::pData

+

+

+
points to the data of the matrix. 

+
+
Definition at line 1364 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__f32.html
new file mode 100644
index 0000000..9dfc257
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__f32.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_pid_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point PID Control.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
float32_t A0
float32_t A1
float32_t A2
float32_t state [3]
float32_t Kp
float32_t Ki
float32_t Kd

+
Detailed Description

+
Instance structure for the floating-point PID Control. 

+
+
Definition at line 1697 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::A0

+

+

+
The derived gain, A0 = Kp + Ki + Kd . 

+
+
Definition at line 1699 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::A1

+

+

+
The derived gain, A1 = -Kp - 2Kd. 

+
+
Definition at line 1700 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::A2

+

+

+
The derived gain, A2 = Kd . 

+
+
Definition at line 1701 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::state[3]

+

+

+
The state array of length 3. 

+
+
Definition at line 1702 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::Kp

+

+

+
The proportional gain. 

+
+
Definition at line 1703 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::Ki

+

+

+
The integral gain. 

+
+
Definition at line 1704 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t arm_pid_instance_f32::Kd

+

+

+
The derivative gain. 

+
+
Definition at line 1705 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__q15.html
new file mode 100644
index 0000000..a39c909
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__q15.html
@@ -0,0 +1,194 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_pid_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 PID Control.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+

+Data Fields
q15_t A0
q31_t A1
q15_t state [3]
q15_t Kp
q15_t Ki
q15_t Kd

+
Detailed Description

+
Instance structure for the Q15 PID Control. 

+
+
Definition at line 1664 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::A0

+

+

+
The derived gain, A0 = Kp + Ki + Kd . 

+
+
Definition at line 1666 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q15::A1

+

+

+
The derived gain A1 = -Kp - 2Kd | Kd. 

+
+
Definition at line 1671 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::state[3]

+

+

+
The state array of length 3. 

+
+
Definition at line 1673 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::Kp

+

+

+
The proportional gain. 

+
+
Definition at line 1674 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::Ki

+

+

+
The integral gain. 

+
+
Definition at line 1675 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t arm_pid_instance_q15::Kd

+

+

+
The derivative gain. 

+
+
Definition at line 1676 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__q31.html
new file mode 100644
index 0000000..ee06a18
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__pid__instance__q31.html
@@ -0,0 +1,211 @@
+
+
+
+
+CMSIS DSP Software Library: arm_pid_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_pid_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 PID Control.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+

+Data Fields
q31_t A0
q31_t A1
q31_t A2
q31_t state [3]
q31_t Kp
q31_t Ki
q31_t Kd

+
Detailed Description

+
Instance structure for the Q31 PID Control. 

+
+
Definition at line 1682 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::A0

+

+

+
The derived gain, A0 = Kp + Ki + Kd . 

+
+
Definition at line 1684 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::A1

+

+

+
The derived gain, A1 = -Kp - 2Kd. 

+
+
Definition at line 1685 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::A2

+

+

+
The derived gain, A2 = Kd . 

+
+
Definition at line 1686 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::state[3]

+

+

+
The state array of length 3. 

+
+
Definition at line 1687 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::Kp

+

+

+
The proportional gain. 

+
+
Definition at line 1688 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::Ki

+

+

+
The integral gain. 

+
+
Definition at line 1689 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t arm_pid_instance_q31::Kd

+

+

+
The derivative gain. 

+
+
Definition at line 1690 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__f32.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__f32.html
new file mode 100644
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__f32.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_instance_f32 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_rfft_instance_f32 Struct Reference
  

+

+

+
+
Instance structure for the floating-point RFFT/RIFFT function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t fftLenReal
uint16_t fftLenBy2
uint8_t ifftFlagR
uint8_t bitReverseFlagR
uint32_t twidCoefRModifier
float32_t * pTwiddleAReal
float32_t * pTwiddleBReal
arm_cfft_radix4_instance_f32 * pCfft

+
Detailed Description

+
Instance structure for the floating-point RFFT/RIFFT function. 

+
+
Definition at line 2188 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_f32::fftLenReal

+

+

+
length of the real FFT. 

+
+
Definition at line 2190 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint16_t arm_rfft_instance_f32::fftLenBy2

+

+

+
length of the complex FFT. 

+
+
Definition at line 2191 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_f32::ifftFlagR

+

+

+
flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 

+
+
Definition at line 2192 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_f32::bitReverseFlagR

+

+

+
flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. 

+
+
Definition at line 2193 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_f32::twidCoefRModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Definition at line 2194 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_rfft_instance_f32::pTwiddleAReal

+

+

+
points to the real twiddle factor table. 

+
+
Definition at line 2195 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
float32_t* arm_rfft_instance_f32::pTwiddleBReal

+

+

+
points to the imag twiddle factor table. 

+
+
Definition at line 2196 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_f32* arm_rfft_instance_f32::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Definition at line 2197 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__q15.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__q15.html
new file mode 100644
index 0000000..7f5a1b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__q15.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_instance_q15 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_rfft_instance_q15 Struct Reference
  

+

+

+
+
Instance structure for the Q15 RFFT/RIFFT function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t fftLenReal
uint32_t fftLenBy2
uint8_t ifftFlagR
uint8_t bitReverseFlagR
uint32_t twidCoefRModifier
q15_t * pTwiddleAReal
q15_t * pTwiddleBReal
arm_cfft_radix4_instance_q15 * pCfft

+
Detailed Description

+
Instance structure for the Q15 RFFT/RIFFT function. 

+
+
Definition at line 2156 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q15::fftLenReal

+

+

+
length of the real FFT. 

+
+
Definition at line 2158 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q15::fftLenBy2

+

+

+
length of the complex FFT. 

+
+
Definition at line 2159 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_q15::ifftFlagR

+

+

+
flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 

+
+
Definition at line 2160 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_q15::bitReverseFlagR

+

+

+
flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. 

+
+
Definition at line 2161 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q15::twidCoefRModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Definition at line 2162 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_rfft_instance_q15::pTwiddleAReal

+

+

+
points to the real twiddle factor table. 

+
+
Definition at line 2163 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q15_t* arm_rfft_instance_q15::pTwiddleBReal

+

+

+
points to the imag twiddle factor table. 

+
+
Definition at line 2164 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_q15* arm_rfft_instance_q15::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Definition at line 2165 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__q31.html b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__q31.html
new file mode 100644
index 0000000..50d6ce9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/structarm__rfft__instance__q31.html
@@ -0,0 +1,228 @@
+
+
+
+
+CMSIS DSP Software Library: arm_rfft_instance_q31 Struct Reference
+
+
+
+
+
+
+
+
+
+

+  

+Data Fields  

+  

+
arm_rfft_instance_q31 Struct Reference
  

+

+

+
+
Instance structure for the Q31 RFFT/RIFFT function.  
+More...

+
+
#include <arm_math.h>

+
+
+
+
+
+
+
+
+
+
+

+Data Fields
uint32_t fftLenReal
uint32_t fftLenBy2
uint8_t ifftFlagR
uint8_t bitReverseFlagR
uint32_t twidCoefRModifier
q31_t * pTwiddleAReal
q31_t * pTwiddleBReal
arm_cfft_radix4_instance_q31 * pCfft

+
Detailed Description

+
Instance structure for the Q31 RFFT/RIFFT function. 

+
+
Definition at line 2172 of file arm_math.h.

+
Field Documentation

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q31::fftLenReal

+

+

+
length of the real FFT. 

+
+
Definition at line 2174 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q31::fftLenBy2

+

+

+
length of the complex FFT. 

+
+
Definition at line 2175 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_q31::ifftFlagR

+

+

+
flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. 

+
+
Definition at line 2176 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint8_t arm_rfft_instance_q31::bitReverseFlagR

+

+

+
flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. 

+
+
Definition at line 2177 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
uint32_t arm_rfft_instance_q31::twidCoefRModifier

+

+

+
twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 

+
+
Definition at line 2178 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_rfft_instance_q31::pTwiddleAReal

+

+

+
points to the real twiddle factor table. 

+
+
Definition at line 2179 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
q31_t* arm_rfft_instance_q31::pTwiddleBReal

+

+

+
points to the imag twiddle factor table. 

+
+
Definition at line 2180 of file arm_math.h.

+
+

+

+
+

+

+      
+        
+          
+        
+      
arm_cfft_radix4_instance_q31* arm_rfft_instance_q31::pCfft

+

+

+
points to the complex FFT instance. 

+
+
Definition at line 2181 of file arm_math.h.

+
+

+

+
The documentation for this struct was generated from the following file:
+

+
+
+
+
+

+
+

+
+
Generated on Fri Jul 15 2011 13:16:23 for CMSIS DSP Software Library by 
+
+doxygen 1.7.2 

+
+
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/tab_a.png b/hardware/digistump/sam/system/CMSIS/CMSIS/Documentation/DSP_Lib/html/tab_a.png
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+.tabs, .tabs2, .tabs3 {
+    background-image: url('tab_b.png');
+    width: 100%;
+    z-index: 101;
+    font-size: 13px;
+}
+
+.tabs2 {
+    font-size: 10px;
+}
+.tabs3 {
+    font-size: 9px;
+}
+
+.tablist {
+    margin: 0;
+    padding: 0;
+    display: table;
+}
+
+.tablist li {
+    float: left;
+    display: table-cell;
+    background-image: url('tab_b.png');
+    line-height: 36px;
+    list-style: none;
+}
+
+.tablist a {
+    display: block;
+    padding: 0 20px;
+    font-weight: bold;
+    background-image:url('tab_s.png');
+    background-repeat:no-repeat;
+    background-position:right;
+    color: #283A5D;
+    text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
+    text-decoration: none;
+    outline: none;
+}
+
+.tabs3 .tablist a {
+    padding: 0 10px;
+}
+
+.tablist a:hover {
+    background-image: url('tab_h.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+    text-decoration: none;
+}
+
+.tablist li.current a {
+    background-image: url('tab_a.png');
+    background-repeat:repeat-x;
+    color: #fff;
+    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);
+}
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Include/arm_common_tables.h b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000..7245c4f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,35 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved. 
+* 
+* $Date:        11. November 2010  
+* $Revision: 	V1.0.2  
+* 
+* Project: 	    CMSIS DSP Library 
+* Title:	    arm_common_tables.h 
+* 
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 
+* 
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.2 2010/11/11 
+*    Documentation updated.  
+* 
+* Version 1.0.1 2010/10/05  
+*    Production release and review comments incorporated. 
+* 
+* Version 1.0.0 2010/09/20  
+*    Production release and review comments incorporated. 
+* -------------------------------------------------------------------- */ 
+ 
+#ifndef _ARM_COMMON_TABLES_H 
+#define _ARM_COMMON_TABLES_H 
+ 
+#include "arm_math.h" 
+ 
+extern uint16_t armBitRevTable[256]; 
+extern q15_t armRecipTableQ15[64]; 
+extern q31_t armRecipTableQ31[64]; 
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+ 
+#endif /*  ARM_COMMON_TABLES_H */ 
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Include/arm_math.h b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000..ffa03b6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/arm_math.h
@@ -0,0 +1,7051 @@
+/* ----------------------------------------------------------------------   
+ * Copyright (C) 2010 ARM Limited. All rights reserved.   
+ *   
+ * $Date:        15. July 2011  
+ * $Revision: 	V1.0.10  
+ *   
+ * Project: 	    CMSIS DSP Library   
+ * Title:	     arm_math.h
+ *   
+ * Description:	 Public header file for CMSIS DSP Library
+ *   
+ * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+ *  
+ * Version 1.0.10 2011/7/15 
+ *    Big Endian support added and Merged M0 and M3/M4 Source code.  
+ *   
+ * Version 1.0.3 2010/11/29  
+ *    Re-organized the CMSIS folders and updated documentation.   
+ *    
+ * Version 1.0.2 2010/11/11   
+ *    Documentation updated.    
+ *   
+ * Version 1.0.1 2010/10/05    
+ *    Production release and review comments incorporated.   
+ *   
+ * Version 1.0.0 2010/09/20    
+ *    Production release and review comments incorporated.   
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   *
+   * This user manual describes the CMSIS DSP software library, 
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of modules each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values. 
+   *
+   * Processor Support
+   *
+   * The library is completely written in C and is fully CMSIS compliant. 
+   * High performance is achieved through maximum use of Cortex-M4 intrinsics. 
+   *
+   * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,
+   * with the DSP intrinsics being emulated through software. 
+   *
+   *
+   * Toolchain Support
+   *
+   * The library has been developed and tested with MDK-ARM version 4.21. 
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Using the Library
+   *
+   * The library installer contains prebuilt versions of the libraries in the Lib folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single 
+   * public header file  arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. 
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or 
+   * ARM_MATH_CM0 depending on the target processor in the application.
+   *
+   * Examples
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Building the Library
+   *
+   * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder.
+   * - arm_cortexM0b_math.uvproj
+   * - arm_cortexM0l_math.uvproj
+   * - arm_cortexM3b_math.uvproj
+   * - arm_cortexM3l_math.uvproj  
+   * - arm_cortexM4b_math.uvproj
+   * - arm_cortexM4l_math.uvproj
+   * - arm_cortexM4bf_math.uvproj
+   * - arm_cortexM4lf_math.uvproj
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * ARM_MATH_CMx:
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target.
+   *
+   * ARM_MATH_BIG_ENDIAN:
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * ARM_MATH_MATRIX_CHECK:
+   * Define macro for checking on the input and output sizes of matrices
+   *
+   * ARM_MATH_ROUNDING:
+   * Define macro for rounding on support functions
+   *
+   * __FPU_PRESENT:
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries 
+   *
+   *
+   * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.
+   *
+   * Copyright Notice
+   *
+   * Copyright (C) 2010 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * 

+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size numRows X numCols
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * 
+ *     pData[i*numCols + j]
+ * 

+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ * 

+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * 
+ *     ARM_MATH_SIZE_MISMATCH
+ * 

+ * Otherwise the functions return
+ * 
+ *     ARM_MATH_SUCCESS
+ * 

+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the #define
+ * 
+ *     ARM_MATH_MATRIX_CHECK
+ * 

+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC              /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef  __CMSIS_GENERIC              /* enable NVIC and Systick functions */
+#include "string.h"
+    #include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#define PI					3.14159265358979f
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define TABLE_SIZE			256
+#define TABLE_SPACING_Q31	0x800000
+#define TABLE_SPACING_Q15	0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+    {
+      ARM_MATH_SUCCESS = 0,              /**< No error */
+      ARM_MATH_ARGUMENT_ERROR = -1,      /**< One or more arguments are incorrect */
+      ARM_MATH_LENGTH_ERROR = -2,        /**< Length of data buffer is incorrect */
+      ARM_MATH_SIZE_MISMATCH = -3,       /**< Size of matrices is not compatible with the operation. */
+      ARM_MATH_NANINF = -4,              /**< Not-a-number (NaN) or infinity is generated */
+      ARM_MATH_SINGULAR = -5,            /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+      ARM_MATH_TEST_FAILURE = -6         /**< Test Failed  */
+    } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#define __SIMD32(addr)  (*(int32_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else								
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+								
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+					q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+					q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+				      q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+					q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+				  q63_t x,
+				  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif 
+
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+  static __INLINE  uint32_t __CLZ(q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(q31_t data)
+  {
+	  uint32_t count = 0;
+	  uint32_t mask = 0x80000000;
+
+	  while((data & mask) ==  0)
+	  {
+		  count += 1u;
+		  mask = mask >> 1u;
+	  }
+
+	  return(count);
+
+  }
+
+#endif 
+
+  /**
+   * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+					 q31_t in,
+					 q31_t * dst,
+					 q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+      {
+	signBits = __CLZ(in) - 1;
+      }
+    else
+      {
+	signBits = __CLZ(-in) - 1;
+      }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+      {
+	tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+	tempVal = 0x7FFFFFFF - tempVal;
+	/*      1.31 with exp 1 */
+	//out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+	out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+      }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+					 q15_t in,
+					 q15_t * dst,
+					 q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+      {
+	signBits = __CLZ(in) - 17;
+      }
+    else
+      {
+	signBits = __CLZ(-in) - 17;
+      }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+      {
+	tempVal = (q15_t) (((q31_t) in * out) >> 15);
+	tempVal = 0x7FFF - tempVal;
+	/*      1.15 with exp 1 */
+	out = (q15_t) (((q31_t) out * tempVal) >> 14);
+      }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0)
+
+  static __INLINE q31_t __SSAT(
+			       q31_t x,
+			       uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+      {
+	posMax = posMax * 2;
+      }
+
+    if(x > 0)
+      {
+	posMax = (posMax - 1);
+
+	if(x > posMax)
+	  {
+	    x = posMax;
+	  }
+      }
+    else
+      {
+	negMin = -posMax;
+
+	if(x < negMin)
+	  {
+	    x = negMin;
+	  }
+      }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0 */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+				q31_t x,
+				q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (char) x;
+    s = (char) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+				q31_t x,
+				q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (char) x;
+    s = (char) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+				 q31_t x,
+				 q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+				  q31_t x,
+				  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+				 q31_t x,
+				 q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+				  q31_t x,
+				  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+			       q31_t x,
+			       q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+				q31_t x,
+				q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+			       q31_t x,
+			       q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+				q31_t x,
+				q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+				 q31_t x,
+				 q31_t y)
+  {
+
+    return ((q31_t)(((short) x * (short) (y >> 16)) -
+		    ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+				 q31_t x,
+				 q31_t y)
+  {
+
+    return ((q31_t)(((short) x * (short) (y >> 16)) +
+		    ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+			       q31_t x,
+			       q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+			       q31_t x,
+			       q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+				q31_t x,
+				q31_t y,
+				q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+				 q31_t x,
+				 q31_t y,
+				 q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+				 q31_t x,
+				 q31_t y,
+				 q31_t sum)
+  {
+
+    return (sum - ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+				 q31_t x,
+				 q31_t y,
+				 q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+				  q31_t x,
+				  q31_t y,
+				  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) y)) +
+      ((short) x * (short) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+				q31_t x,
+				q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+				q31_t x,
+				q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+
+
+#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+		  const arm_fir_instance_q7 * S,
+		   q7_t * pSrc,
+		  q7_t * pDst,
+		  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+		       arm_fir_instance_q7 * S,
+		       uint16_t numTaps,
+		       q7_t * pCoeffs,
+		       q7_t * pState,
+		       uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+		   const arm_fir_instance_q15 * S,
+		    q15_t * pSrc,
+		   q15_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+			const arm_fir_instance_q15 * S,
+			 q15_t * pSrc,
+			q15_t * pDst,
+			uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * numTaps is not a supported value.
+   */
+   
+       arm_status arm_fir_init_q15(
+			      arm_fir_instance_q15 * S,
+			      uint16_t numTaps,
+			      q15_t * pCoeffs,
+			      q15_t * pState,
+			      uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+		   const arm_fir_instance_q31 * S,
+		    q31_t * pSrc,
+		   q31_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+			const arm_fir_instance_q31 * S,
+			 q31_t * pSrc,
+			q31_t * pDst,
+			uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+			arm_fir_instance_q31 * S,
+			uint16_t numTaps,
+			q31_t * pCoeffs,
+			q31_t * pState,
+			uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+		   const arm_fir_instance_f32 * S,
+		    float32_t * pSrc,
+		   float32_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+			arm_fir_instance_f32 * S,
+			uint16_t numTaps,
+			float32_t * pCoeffs,
+			float32_t * pState,
+			uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+				  const arm_biquad_casd_df1_inst_q15 * S,
+				   q15_t * pSrc,
+				  q15_t * pDst,
+				  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+				       arm_biquad_casd_df1_inst_q15 * S,
+				       uint8_t numStages,
+				       q15_t * pCoeffs,
+				       q15_t * pState,
+				       int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+				       const arm_biquad_casd_df1_inst_q15 * S,
+				        q15_t * pSrc,
+				       q15_t * pDst,
+				       uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+				  const arm_biquad_casd_df1_inst_q31 * S,
+				   q31_t * pSrc,
+				  q31_t * pDst,
+				  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+				       const arm_biquad_casd_df1_inst_q31 * S,
+				        q31_t * pSrc,
+				       q31_t * pDst,
+				       uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+				       arm_biquad_casd_df1_inst_q31 * S,
+				       uint8_t numStages,
+				       q31_t * pCoeffs,
+				       q31_t * pState,
+				       int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+				  const arm_biquad_casd_df1_inst_f32 * S,
+				   float32_t * pSrc,
+				  float32_t * pDst,
+				  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+				       arm_biquad_casd_df1_inst_f32 * S,
+				       uint8_t numStages,
+				       float32_t * pCoeffs,
+				       float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+			     const arm_matrix_instance_f32 * pSrcA,
+			     const arm_matrix_instance_f32 * pSrcB,
+			     arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+			     const arm_matrix_instance_q15 * pSrcA,
+			     const arm_matrix_instance_q15 * pSrcB,
+			     arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+			     const arm_matrix_instance_q31 * pSrcA,
+			     const arm_matrix_instance_q31 * pSrcB,
+			     arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+			       const arm_matrix_instance_f32 * pSrc,
+			       arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+			       const arm_matrix_instance_q15 * pSrc,
+			       arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+			       const arm_matrix_instance_q31 * pSrc,
+			       arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+			      const arm_matrix_instance_f32 * pSrcA,
+			      const arm_matrix_instance_f32 * pSrcB,
+			      arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+			      const arm_matrix_instance_q15 * pSrcA,
+			      const arm_matrix_instance_q15 * pSrcB,
+			      arm_matrix_instance_q15 * pDst,
+			      q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results  
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+				   const arm_matrix_instance_q15 * pSrcA,
+				   const arm_matrix_instance_q15 * pSrcB,
+				   arm_matrix_instance_q15 * pDst,
+				   q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+			      const arm_matrix_instance_q31 * pSrcA,
+			      const arm_matrix_instance_q31 * pSrcB,
+			      arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+				   const arm_matrix_instance_q31 * pSrcA,
+				   const arm_matrix_instance_q31 * pSrcB,
+				   arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+			     const arm_matrix_instance_f32 * pSrcA,
+			     const arm_matrix_instance_f32 * pSrcB,
+			     arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+			     const arm_matrix_instance_q15 * pSrcA,
+			     const arm_matrix_instance_q15 * pSrcB,
+			     arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+			     const arm_matrix_instance_q31 * pSrcA,
+			     const arm_matrix_instance_q31 * pSrcB,
+			     arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+			       const arm_matrix_instance_f32 * pSrc,
+			       float32_t scale,
+			       arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+			       const arm_matrix_instance_q15 * pSrc,
+			       q15_t scaleFract,
+			       int32_t shift,
+			       arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+			       const arm_matrix_instance_q31 * pSrc,
+			       q31_t scaleFract,
+			       int32_t shift,
+			       arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+			arm_matrix_instance_q31 * S,
+			uint16_t nRows,
+			uint16_t nColumns,
+			q31_t   *pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+			arm_matrix_instance_q15 * S,
+			uint16_t nRows,
+			uint16_t nColumns,
+			q15_t    *pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+			arm_matrix_instance_f32 * S,
+			uint16_t nRows,
+			uint16_t nColumns,
+			float32_t   *pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0; 	 /**< The derived gain, A0 = Kp + Ki + Kd . */
+	#ifdef ARM_MATH_CM0  
+	q15_t A1;
+	q15_t A2; 
+	#else 	      
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+	#endif 
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+			arm_pid_instance_f32 * S,
+			int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+			 arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+			arm_pid_instance_q31 * S,
+			int32_t resetStateFlag);
+
+ 
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+			 arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+			arm_pid_instance_q15 * S,
+			int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+			 arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;
+    float32_t x1;
+    float32_t xSpacing;
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;	/**< number of rows in the data table. */
+    uint16_t numCols;	/**< number of columns in the data table. */
+    float32_t *pData;	/**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;	/**< number of rows in the data table. */
+    uint16_t numCols;	/**< number of columns in the data table. */
+    q31_t *pData;	/**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;	/**< number of rows in the data table. */
+    uint16_t numCols;	/**< number of columns in the data table. */
+    q15_t *pData;	/**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows; 	/**< number of rows in the data table. */
+    uint16_t numCols;	/**< number of columns in the data table. */
+    q7_t *pData;		/**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+		    q7_t * pSrcA,
+		    q7_t * pSrcB,
+		   q7_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+		     q15_t * pSrcA,
+		     q15_t * pSrcB,
+		    q15_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+		     q31_t * pSrcA,
+		     q31_t * pSrcB,
+		    q31_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+		     float32_t * pSrcA,
+		     float32_t * pSrcB,
+		    float32_t * pDst,
+		    uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t  fftLen;                /**< length of the FFT. */
+    uint8_t   ifftFlag;              /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t   bitReverseFlag;        /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t     *pTwiddle;             /**< points to the twiddle factor table. */
+    uint16_t  *pBitRevTable;         /**< points to the bit reversal table. */
+    uint16_t  twidCoefModifier;      /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t  bitRevFactor;          /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t    fftLen;              /**< length of the FFT. */
+    uint8_t     ifftFlag;            /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t     bitReverseFlag;      /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t       *pTwiddle;           /**< points to the twiddle factor table. */
+    uint16_t    *pBitRevTable;       /**< points to the bit reversal table. */
+    uint16_t    twidCoefModifier;    /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t    bitRevFactor;        /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t     fftLen;               /**< length of the FFT. */
+    uint8_t      ifftFlag;             /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t      bitReverseFlag;       /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t    *pTwiddle;            /**< points to the twiddle factor table. */
+    uint16_t     *pBitRevTable;        /**< points to the bit reversal table. */
+    uint16_t     twidCoefModifier;     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t     bitRevFactor;         /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+	float32_t    onebyfftLen;          /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+  /**
+   * @brief Processing function for the Q15 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_q15(
+			   const arm_cfft_radix4_instance_q15 * S,
+			   q15_t * pSrc);
+
+  /**
+   * @brief Initialization function for the Q15 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+
+  arm_status arm_cfft_radix4_init_q15(
+				      arm_cfft_radix4_instance_q15 * S,
+				      uint16_t fftLen,
+				      uint8_t ifftFlag,
+				      uint8_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the Q31 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_q31(
+			   const arm_cfft_radix4_instance_q31 * S,
+			   q31_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the Q31 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+  
+  arm_status arm_cfft_radix4_init_q31(
+				      arm_cfft_radix4_instance_q31 * S,
+				      uint16_t fftLen,
+				      uint8_t ifftFlag,
+				      uint8_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the floating-point CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_f32(
+			   const arm_cfft_radix4_instance_f32 * S,
+			   float32_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the floating-point CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+  
+  arm_status arm_cfft_radix4_init_f32(
+				      arm_cfft_radix4_instance_f32 * S,
+				      uint16_t fftLen,
+				      uint8_t ifftFlag,
+				      uint8_t bitReverseFlag);
+
+
+
+  /*----------------------------------------------------------------------
+   *		Internal functions prototypes FFT function
+   ----------------------------------------------------------------------*/
+
+  /**
+   * @brief  Core function for the floating-point CFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to the twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+  
+  void arm_radix4_butterfly_f32(
+				float32_t * pSrc,
+				uint16_t fftLen,
+				float32_t * pCoef,
+				uint16_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the floating-point CIFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @param[in]      onebyfftLen      value of 1/fftLen.
+   * @return none.
+   */
+  
+  void arm_radix4_butterfly_inverse_f32(
+					float32_t * pSrc,
+					uint16_t fftLen,
+					float32_t * pCoef,
+					uint16_t twidCoefModifier,
+					float32_t onebyfftLen);
+
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.
+   * @param[in]      fftSize      length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
+   * @param[in]      *pBitRevTab  points to the bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_f32(
+			   float32_t *pSrc,
+			   uint16_t fftSize,
+			   uint16_t bitRevFactor,
+			   uint16_t *pBitRevTab);
+
+  /**
+   * @brief  Core function for the Q31 CFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+  
+  void arm_radix4_butterfly_q31(
+				q31_t *pSrc,
+				uint32_t fftLen,
+				q31_t *pCoef,
+				uint32_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the Q31 CIFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+  
+  void arm_radix4_butterfly_inverse_q31(
+					q31_t * pSrc,
+					uint32_t fftLen,
+					q31_t * pCoef,
+					uint32_t twidCoefModifier);
+  
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen       length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+   * @param[in]      *pBitRevTab  points to bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_q31(
+			   q31_t * pSrc,
+			   uint32_t fftLen,
+			   uint16_t bitRevFactor,
+			   uint16_t *pBitRevTab);
+
+  /**
+   * @brief  Core function for the Q15 CFFT butterfly process.
+   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_q15(
+				q15_t *pSrc16,
+				uint32_t fftLen,
+				q15_t *pCoef16,
+				uint32_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the Q15 CIFFT butterfly process.
+   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_inverse_q15(
+					q15_t *pSrc16,
+					uint32_t fftLen,
+					q15_t *pCoef16,
+					uint32_t twidCoefModifier);
+
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen       length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+   * @param[in]      *pBitRevTab  points to bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_q15(
+			   q15_t * pSrc,
+			   uint32_t fftLen,
+			   uint16_t bitRevFactor,
+			   uint16_t *pBitRevTab);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
+    uint8_t  ifftFlagR;                       /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+	uint8_t  bitReverseFlagR;                 /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */  
+    q15_t    *pTwiddleAReal;                  /**< points to the real twiddle factor table. */
+    q15_t    *pTwiddleBReal;                  /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q15 *pCfft;	  /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t  ifftFlagR;                         /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+	uint8_t  bitReverseFlagR;                   /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t    *pTwiddleAReal;                    /**< points to the real twiddle factor table. */
+    q31_t    *pTwiddleBReal;                    /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t  fftLenReal;                       /**< length of the real FFT. */
+    uint16_t  fftLenBy2;                        /**< length of the complex FFT. */
+    uint8_t   ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t   bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+	uint32_t  twidCoefRModifier;                /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  /**
+   * @brief Processing function for the Q15 RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_q15(
+		    const arm_rfft_instance_q15 * S,
+		    q15_t * pSrc,
+		    q15_t * pDst);
+
+  /**
+   * @brief  Initialization function for the Q15 RFFT/RIFFT.
+   * @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.
+   * @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in]      fftLenReal     length of the FFT.
+   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   */
+
+  arm_status arm_rfft_init_q15(
+			       arm_rfft_instance_q15 * S,
+			       arm_cfft_radix4_instance_q15 * S_CFFT,
+			       uint32_t fftLenReal,
+			       uint32_t ifftFlagR,
+			       uint32_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the Q31 RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_q31(
+		    const arm_rfft_instance_q31 * S,
+		    q31_t * pSrc,
+		    q31_t * pDst);
+
+  /**
+   * @brief  Initialization function for the Q31 RFFT/RIFFT.
+   * @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.
+   * @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in]      fftLenReal     length of the FFT.
+   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   */
+
+  arm_status arm_rfft_init_q31(
+			       arm_rfft_instance_q31 * S,
+			       arm_cfft_radix4_instance_q31 * S_CFFT,
+			       uint32_t fftLenReal,
+			       uint32_t ifftFlagR,
+			       uint32_t bitReverseFlag);
+
+  /**
+   * @brief  Initialization function for the floating-point RFFT/RIFFT.
+   * @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.
+   * @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in]     fftLenReal     length of the FFT.
+   * @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   */
+
+  arm_status arm_rfft_init_f32(
+			       arm_rfft_instance_f32 * S,
+			       arm_cfft_radix4_instance_f32 * S_CFFT,
+			       uint32_t fftLenReal,
+			       uint32_t ifftFlagR,
+			       uint32_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the floating-point RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_f32(
+		    const arm_rfft_instance_f32 * S,
+		    float32_t * pSrc,
+		    float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+			       arm_dct4_instance_f32 * S,
+			       arm_rfft_instance_f32 * S_RFFT,
+			       arm_cfft_radix4_instance_f32 * S_CFFT,
+			       uint16_t N,
+			       uint16_t Nby2,
+			       float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+		    const arm_dct4_instance_f32 * S,
+		    float32_t * pState,
+		    float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+			       arm_dct4_instance_q31 * S,
+			       arm_rfft_instance_q31 * S_RFFT,
+			       arm_cfft_radix4_instance_q31 * S_CFFT,
+			       uint16_t N,
+			       uint16_t Nby2,
+			       q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+		    const arm_dct4_instance_q31 * S,
+		    q31_t * pState,
+		    q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+			       arm_dct4_instance_q15 * S,
+			       arm_rfft_instance_q15 * S_RFFT,
+			       arm_cfft_radix4_instance_q15 * S_CFFT,
+			       uint16_t N,
+			       uint16_t Nby2,
+			       q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+		    const arm_dct4_instance_q15 * S,
+		    q15_t * pState,
+		    q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+		   float32_t * pSrcA,
+		   float32_t * pSrcB,
+		   float32_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+		  q7_t * pSrcA,
+		  q7_t * pSrcB,
+		  q7_t * pDst,
+		  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+		    q15_t * pSrcA,
+		    q15_t * pSrcB,
+		   q15_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+		    q31_t * pSrcA,
+		    q31_t * pSrcB,
+		   q31_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+		    float32_t * pSrcA,
+		    float32_t * pSrcB,
+		   float32_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+		   q7_t * pSrcA,
+		   q7_t * pSrcB,
+		  q7_t * pDst,
+		  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+		    q15_t * pSrcA,
+		    q15_t * pSrcB,
+		   q15_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+		    q31_t * pSrcA,
+		    q31_t * pSrcB,
+		   q31_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+		      float32_t * pSrc,
+		     float32_t scale,
+		     float32_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+		     q7_t * pSrc,
+		    q7_t scaleFract,
+		    int8_t shift,
+		    q7_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+		      q15_t * pSrc,
+		     q15_t scaleFract,
+		     int8_t shift,
+		     q15_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+		      q31_t * pSrc,
+		     q31_t scaleFract,
+		     int8_t shift,
+		     q31_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+		   q7_t * pSrc,
+		  q7_t * pDst,
+		  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+		    float32_t * pSrc,
+		   float32_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+		    q15_t * pSrc,
+		   q15_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+		    q31_t * pSrc,
+		   q31_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+			 float32_t * pSrcA,
+			 float32_t * pSrcB,
+			uint32_t blockSize,
+			float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+		        q7_t * pSrcA,
+		        q7_t * pSrcB,
+		       uint32_t blockSize,
+		       q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+			 q15_t * pSrcA,
+			 q15_t * pSrcB,
+			uint32_t blockSize,
+			q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+			 q31_t * pSrcA,
+			 q31_t * pSrcB,
+			uint32_t blockSize,
+			q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+		     q7_t * pSrc,
+		    int8_t shiftBits,
+		    q7_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+		      q15_t * pSrc,
+		     int8_t shiftBits,
+		     q15_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+		      q31_t * pSrc,
+		     int8_t shiftBits,
+		     q31_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+		       float32_t * pSrc,
+		      float32_t offset,
+		      float32_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+		      q7_t * pSrc,
+		     q7_t offset,
+		     q7_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+		       q15_t * pSrc,
+		      q15_t offset,
+		      q15_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+		       q31_t * pSrc,
+		      q31_t offset,
+		      q31_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+		       float32_t * pSrc,
+		      float32_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+		      q7_t * pSrc,
+		     q7_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+		       q15_t * pSrc,
+		      q15_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+		       q31_t * pSrc,
+		      q31_t * pDst,
+		      uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+		     float32_t * pSrc,
+		    float32_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+		    q7_t * pSrc,
+		   q7_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+		     q15_t * pSrc,
+		    q15_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+		     q31_t * pSrc,
+		    q31_t * pDst,
+		    uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+		     float32_t value,
+		    float32_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+		    q7_t value,
+		   q7_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+		     q15_t value,
+		    q15_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+		     q31_t value,
+		    q31_t * pDst,
+		    uint32_t blockSize);
+
+/**  
+ * @brief Convolution of floating-point sequences.  
+ * @param[in] *pSrcA points to the first input sequence.  
+ * @param[in] srcALen length of the first input sequence.  
+ * @param[in] *pSrcB points to the second input sequence.  
+ * @param[in] srcBLen length of the second input sequence.  
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
+ * @return none.  
+ */ 
+
+  void arm_conv_f32(
+		     float32_t * pSrcA,
+		    uint32_t srcALen,
+		     float32_t * pSrcB,
+		    uint32_t srcBLen,
+		    float32_t * pDst);
+
+/**  
+ * @brief Convolution of Q15 sequences.  
+ * @param[in] *pSrcA points to the first input sequence.  
+ * @param[in] srcALen length of the first input sequence.  
+ * @param[in] *pSrcB points to the second input sequence.  
+ * @param[in] srcBLen length of the second input sequence.  
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
+ * @return none.  
+ */
+
+  void arm_conv_q15(
+		     q15_t * pSrcA,
+		    uint32_t srcALen,
+		     q15_t * pSrcB,
+		    uint32_t srcBLen,
+		    q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+		     q31_t * pSrcA,
+		    uint32_t srcALen,
+		     q31_t * pSrcB,
+		    uint32_t srcBLen,
+		    q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+			  q31_t * pSrcA,
+			 uint32_t srcALen,
+			  q31_t * pSrcB,
+			 uint32_t srcBLen,
+			 q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+		    q7_t * pSrcA,
+		   uint32_t srcALen,
+		    q7_t * pSrcB,
+		   uint32_t srcBLen,
+		   q7_t * pDst);
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+				   float32_t * pSrcA,
+				  uint32_t srcALen,
+				   float32_t * pSrcB,
+				  uint32_t srcBLen,
+				  float32_t * pDst,
+				  uint32_t firstIndex,
+				  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+				   q15_t * pSrcA,
+				  uint32_t srcALen,
+				   q15_t * pSrcB,
+				  uint32_t srcBLen,
+				  q15_t * pDst,
+				  uint32_t firstIndex,
+				  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+				   q31_t * pSrcA,
+				  uint32_t srcALen,
+				   q31_t * pSrcB,
+				  uint32_t srcBLen,
+				  q31_t * pDst,
+				  uint32_t firstIndex,
+				  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+				        q31_t * pSrcA,
+				       uint32_t srcALen,
+				        q31_t * pSrcB,
+				       uint32_t srcBLen,
+				       q31_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+				  q7_t * pSrcA,
+				 uint32_t srcALen,
+				  q7_t * pSrcB,
+				 uint32_t srcBLen,
+				 q7_t * pDst,
+				 uint32_t firstIndex,
+				 uint32_t numPoints);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+			    const arm_fir_decimate_instance_f32 * S,
+			     float32_t * pSrc,
+			    float32_t * pDst,
+			    uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+				       arm_fir_decimate_instance_f32 * S,
+				       uint16_t numTaps,
+				       uint8_t M,
+				       float32_t * pCoeffs,
+				       float32_t * pState,
+				       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+			    const arm_fir_decimate_instance_q15 * S,
+			     q15_t * pSrc,
+			    q15_t * pDst,
+			    uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+				 const arm_fir_decimate_instance_q15 * S,
+				  q15_t * pSrc,
+				 q15_t * pDst,
+				 uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+				       arm_fir_decimate_instance_q15 * S,
+				       uint16_t numTaps,
+				       uint8_t M,
+				       q15_t * pCoeffs,
+				       q15_t * pState,
+				       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+			    const arm_fir_decimate_instance_q31 * S,
+			     q31_t * pSrc,
+			    q31_t * pDst,
+			    uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+				 arm_fir_decimate_instance_q31 * S,
+				  q31_t * pSrc,
+				 q31_t * pDst,
+				 uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+				       arm_fir_decimate_instance_q31 * S,
+				       uint16_t numTaps,
+				       uint8_t M,
+				       q31_t * pCoeffs,
+				       q31_t * pState,
+				       uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+			       const arm_fir_interpolate_instance_q15 * S,
+			        q15_t * pSrc,
+			       q15_t * pDst,
+			       uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+					  arm_fir_interpolate_instance_q15 * S,
+					  uint8_t L,
+					  uint16_t numTaps,
+					  q15_t * pCoeffs,
+					  q15_t * pState,
+					  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+			       const arm_fir_interpolate_instance_q31 * S,
+			        q31_t * pSrc,
+			       q31_t * pDst,
+			       uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+					  arm_fir_interpolate_instance_q31 * S,
+					  uint8_t L,
+					  uint16_t numTaps,
+					  q31_t * pCoeffs,
+					  q31_t * pState,
+					  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+			       const arm_fir_interpolate_instance_f32 * S,
+			        float32_t * pSrc,
+			       float32_t * pDst,
+			       uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+					  arm_fir_interpolate_instance_f32 * S,
+					  uint8_t L,
+					  uint16_t numTaps,
+					  float32_t * pCoeffs,
+					  float32_t * pState,
+					  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+				    const arm_biquad_cas_df1_32x64_ins_q31 * S,
+				     q31_t * pSrc,
+				    q31_t * pDst,
+				    uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+					 arm_biquad_cas_df1_32x64_ins_q31 * S,
+					 uint8_t numStages,
+					 q31_t * pCoeffs,
+					 q63_t * pState,
+					 uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t   numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+				   const arm_biquad_cascade_df2T_instance_f32 * S,
+				    float32_t * pSrc,
+				   float32_t * pDst,
+				   uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+					arm_biquad_cascade_df2T_instance_f32 * S,
+					uint8_t numStages,
+					float32_t * pCoeffs,
+					float32_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages. 
+   * @param[in] *pState points to the state buffer.  The array is of length numStages. 
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+				arm_fir_lattice_instance_q15 * S,
+				uint16_t numStages,
+				q15_t * pCoeffs,
+				q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+			   const arm_fir_lattice_instance_q15 * S,
+			    q15_t * pSrc,
+			   q15_t * pDst,
+			   uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+				arm_fir_lattice_instance_q31 * S,
+				uint16_t numStages,
+				q31_t * pCoeffs,
+				q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+			   const arm_fir_lattice_instance_q31 * S,
+			    q31_t * pSrc,
+			   q31_t * pDst,
+			   uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+				arm_fir_lattice_instance_f32 * S,
+				uint16_t numStages,
+				float32_t * pCoeffs,
+				float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+			   const arm_fir_lattice_instance_f32 * S,
+			    float32_t * pSrc,
+			   float32_t * pDst,
+			   uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+			   const arm_iir_lattice_instance_f32 * S,
+			    float32_t * pSrc,
+			   float32_t * pDst,
+			   uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+				arm_iir_lattice_instance_f32 * S,
+				uint16_t numStages,
+				float32_t *pkCoeffs,
+				float32_t *pvCoeffs,
+				float32_t *pState,
+				uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+			   const arm_iir_lattice_instance_q31 * S,
+			    q31_t * pSrc,
+			   q31_t * pDst,
+			   uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+				arm_iir_lattice_instance_q31 * S,
+				uint16_t numStages,
+				q31_t *pkCoeffs,
+				q31_t *pvCoeffs,
+				q31_t *pState,
+				uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+			   const arm_iir_lattice_instance_q15 * S,
+			    q15_t * pSrc,
+			   q15_t * pDst,
+			   uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+				arm_iir_lattice_instance_q15 * S,
+				uint16_t numStages,
+				q15_t *pkCoeffs,
+				q15_t *pvCoeffs,
+				q15_t *pState,
+				uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+		   const arm_lms_instance_f32 * S,
+		    float32_t * pSrc,
+		    float32_t * pRef,
+		   float32_t * pOut,
+		   float32_t * pErr,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+			arm_lms_instance_f32 * S,
+			uint16_t numTaps,
+			float32_t * pCoeffs,
+			float32_t * pState,
+			float32_t mu,
+			uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+			arm_lms_instance_q15 * S,
+			uint16_t numTaps,
+			q15_t * pCoeffs,
+			q15_t * pState,
+			q15_t mu,
+			uint32_t blockSize,
+			uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+		   const arm_lms_instance_q15 * S,
+		    q15_t * pSrc,
+		    q15_t * pRef,
+		   q15_t * pOut,
+		   q15_t * pErr,
+		   uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+		   const arm_lms_instance_q31 * S,
+		    q31_t * pSrc,
+		    q31_t * pRef,
+		   q31_t * pOut,
+		   q31_t * pErr,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+			arm_lms_instance_q31 * S,
+			uint16_t numTaps,
+			q31_t *pCoeffs,
+			q31_t *pState,
+			q31_t mu,
+			uint32_t blockSize,
+			uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t  numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+			arm_lms_norm_instance_f32 * S,
+			 float32_t * pSrc,
+			 float32_t * pRef,
+			float32_t * pOut,
+			float32_t * pErr,
+			uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+			     arm_lms_norm_instance_f32 * S,
+			     uint16_t numTaps,
+			     float32_t * pCoeffs,
+			     float32_t * pState,
+			     float32_t mu,
+			     uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+			arm_lms_norm_instance_q31 * S,
+			 q31_t * pSrc,
+			 q31_t * pRef,
+			q31_t * pOut,
+			q31_t * pErr,
+			uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+			     arm_lms_norm_instance_q31 * S,
+			     uint16_t numTaps,
+			     q31_t * pCoeffs,
+			     q31_t * pState,
+			     q31_t mu,
+			     uint32_t blockSize,
+			     uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+			arm_lms_norm_instance_q15 * S,
+			 q15_t * pSrc,
+			 q15_t * pRef,
+			q15_t * pOut,
+			q15_t * pErr,
+			uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+			     arm_lms_norm_instance_q15 * S,
+			     uint16_t numTaps,
+			     q15_t * pCoeffs,
+			     q15_t * pState,
+			     q15_t mu,
+			     uint32_t blockSize,
+			     uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+			  float32_t * pSrcA,
+			 uint32_t srcALen,
+			  float32_t * pSrcB,
+			 uint32_t srcBLen,
+			 float32_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+			  q31_t * pSrcA,
+			 uint32_t srcALen,
+			  q31_t * pSrcB,
+			 uint32_t srcBLen,
+			 q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+			       q31_t * pSrcA,
+			      uint32_t srcALen,
+			       q31_t * pSrcB,
+			      uint32_t srcBLen,
+			      q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+			 q7_t * pSrcA,
+			uint32_t srcALen,
+			 q7_t * pSrcB,
+			uint32_t srcBLen,
+			q7_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+			  arm_fir_sparse_instance_f32 * S,
+			   float32_t * pSrc,
+			  float32_t * pDst,
+			  float32_t * pScratchIn,
+			  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+			       arm_fir_sparse_instance_f32 * S,
+			       uint16_t numTaps,
+			       float32_t * pCoeffs,
+			       float32_t * pState,
+			       int32_t * pTapDelay,
+			       uint16_t maxDelay,
+			       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+			  arm_fir_sparse_instance_q31 * S,
+			   q31_t * pSrc,
+			  q31_t * pDst,
+			  q31_t * pScratchIn,
+			  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+			       arm_fir_sparse_instance_q31 * S,
+			       uint16_t numTaps,
+			       q31_t * pCoeffs,
+			       q31_t * pState,
+			       int32_t * pTapDelay,
+			       uint16_t maxDelay,
+			       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+			  arm_fir_sparse_instance_q15 * S,
+			   q15_t * pSrc,
+			  q15_t * pDst,
+			  q15_t * pScratchIn,
+			  q31_t * pScratchOut,
+			  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+			       arm_fir_sparse_instance_q15 * S,
+			       uint16_t numTaps,
+			       q15_t * pCoeffs,
+			       q15_t * pState,
+			       int32_t * pTapDelay,
+			       uint16_t maxDelay,
+			       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+			 arm_fir_sparse_instance_q7 * S,
+			  q7_t * pSrc,
+			 q7_t * pDst,
+			 q7_t * pScratchIn,
+			 q31_t * pScratchOut,
+			 uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+			      arm_fir_sparse_instance_q7 * S,
+			      uint16_t numTaps,
+			      q7_t * pCoeffs,
+			      q7_t * pState,
+			      int32_t *pTapDelay,
+			      uint16_t maxDelay,
+			      uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees 
+   * @param[out] *pSinVal points to the processed sine output. 
+   * @param[out] *pCosVal points to the processed cos output. 
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+		       float32_t theta,
+		       float32_t *pSinVal,
+		       float32_t *pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees 
+   * @param[out] *pSinVal points to the processed sine output. 
+   * @param[out] *pCosVal points to the processed cosine output. 
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+		       q31_t theta,
+		       q31_t *pSinVal,
+		       q31_t *pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+			   float32_t * pSrc,
+			  float32_t * pDst,
+			  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+			   q31_t * pSrc,
+			  q31_t * pDst,
+			  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+			   q15_t * pSrc,
+			  q15_t * pDst,
+			  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+				  float32_t * pSrc,
+				 float32_t * pDst,
+				 uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+				  q31_t * pSrc,
+				 q31_t * pDst,
+				 uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+				  q15_t * pSrc,
+				 q15_t * pDst,
+				 uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control 
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * S points to an instance of the PID control data structure.  in
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  

+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   * 
+   * \par 
+   * \image html PID.gif "Proportional Integral Derivative Controller" 
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.  
+   * The proportional value determines the reaction to the current error, 
+   * the integral value determines the reaction based on the sum of recent errors, 
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure 
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. 
+   * A separate instance structure must be defined for each PID Controller. 
+   * There are separate instance structure declarations for each of the 3 supported data types. 
+   * 
+   * \par Reset Functions 
+   * There is also an associated reset function for each data type which clears the state array. 
+   *
+   * \par Initialization Functions 
+   * There is also an associated initialization function for each data type. 
+   * The initialization function performs the following operations: 
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.   
+   * 
+   * \par 
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. 
+   *
+   * \par Fixed-Point Behavior 
+   * Care must be taken when using the fixed-point versions of the PID Controller functions. 
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. 
+   * Refer to the function specific documentation below for usage guidelines. 
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+					arm_pid_instance_f32 * S,
+					float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * Scaling and Overflow Behavior: 
+   * \par 
+   * The function is implemented using an internal 64-bit accumulator. 
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. 
+   * Thus, if the accumulator result overflows it wraps around rather than clip. 
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. 
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+				    arm_pid_instance_q31 * S,
+				    q31_t in)
+  {
+    q63_t acc;
+	q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * Scaling and Overflow Behavior: 
+   * \par 
+   * The function is implemented using a 64-bit internal accumulator. 
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. 
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. 
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. 
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. 
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+				    arm_pid_instance_q15 * S,
+				    q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+    /* Implementation of PID controller */
+
+	#ifdef ARM_MATH_CM0
+
+ 	/* acc = A0 * x[n]  */
+	acc = ((q31_t) S->A0 )* in ;
+
+    #else
+				
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+	
+	#endif
+
+	#ifdef ARM_MATH_CM0
+						   
+	/* acc += A1 * x[n-1] + A2 * x[n-2]  */
+	acc += (q31_t) S->A1  *  S->state[0] ;
+	acc += (q31_t) S->A2  *  S->state[1] ;
+
+	#else
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);
+
+	#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+  
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+				 const arm_matrix_instance_f32 * src,
+				 arm_matrix_instance_f32 * dst);
+
+  
+ 
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+   * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+   * When Ialpha is superposed with Ia as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+   * can be calculated using only Ia and Ib.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where Ia and Ib are the instantaneous stator phases and
+   * pIalpha and pIbeta are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate a
+   * @param[in]       Ib       input three-phase coordinate b
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+				      float32_t Ia,
+				      float32_t Ib,
+				      float32_t * pIalpha,
+				      float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate a
+   * @param[in]       Ib       input three-phase coordinate b
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+				      q31_t Ia,
+				      q31_t Ib,
+				      q31_t * pIalpha,
+				      q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+		     q7_t * pSrc,
+		     q31_t * pDst,
+		     uint32_t blockSize);
+
+
+ 
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   * 
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where pIa and pIb are the instantaneous stator phases and
+   * Ialpha and Ibeta are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate a
+   * @param[out]      *pIb    points to output three-phase coordinate b
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+					  float32_t Ialpha,
+					  float32_t Ibeta,
+					  float32_t * pIa,
+					  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version 
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate a
+   * @param[out]      *pIb    points to output three-phase coordinate b
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+					  q31_t Ialpha,
+					  q31_t Ibeta,
+					  q31_t * pIa,
+					  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+		      q7_t * pSrc,
+		     q15_t * pDst,
+		     uint32_t blockSize);
+
+  
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents 
+   * from the stationary to the moving reference frame and control the spatial relationship between 
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the 
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where Ialpha and Ibeta are the stator vector components,  
+   * pId and pIq are rotor vector components and cosVal and sinVal are the 
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+				    float32_t Ialpha,
+				    float32_t Ibeta,
+				    float32_t * pId,
+				    float32_t * pIq,
+				    float32_t sinVal,
+				    float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version 
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+				    q31_t Ialpha,
+				    q31_t Ibeta,
+				    q31_t * pId,
+				    q31_t * pIq,
+				    q31_t sinVal,
+				    q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+		        q7_t * pSrc,
+		       float32_t * pDst,
+		       uint32_t blockSize);
+
+ 
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where pIalpha and pIbeta are the stator vector components,  
+   * Id and Iq are rotor vector components and cosVal and sinVal are the 
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+					float32_t Id,
+					float32_t Iq,
+					float32_t * pIalpha,
+					float32_t * pIbeta,
+					float32_t sinVal,
+					float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version 
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+					q31_t Id,
+					q31_t Iq,
+					q31_t * pIalpha,
+					q31_t * pIbeta,
+					q31_t sinVal,
+					q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+   
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+			 q31_t * pSrc,
+			float32_t * pDst,
+			uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par 
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * 

+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * S points to an instance of the Linear Interpolate function data structure.
+   * x is the input sample value. The functions returns the output value.
+   * 
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table 
+   * if x is below input range and returns last value of table if x is above range.  
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+						  arm_linear_interp_instance_f32 * S,
+						  float32_t x)
+  {
+
+	  float32_t y;
+	  float32_t x0, x1;						/* Nearest input values */
+	  float32_t y0, y1;	  					/* Nearest output values */
+	  float32_t xSpacing = S->xSpacing;		/* spacing between input values */
+	  int32_t i;  							/* Index variable */
+	  float32_t *pYData = S->pYData;	    /* pointer to output table */
+
+	  /* Calculation of index */
+	  i =   (x - S->x1) / xSpacing;
+
+	  if(i < 0)
+	  {
+	     /* Iniatilize output for below specified range as least output value of table */
+		 y = pYData[0];
+	  }
+	  else if(i >= S->nValues)
+	  {
+	  	  /* Iniatilize output for above specified range as last output value of table */
+	  	  y = pYData[S->nValues-1];	
+	  }
+	  else
+	  {	 
+	  	  /* Calculation of nearest input values */
+		  x0 = S->x1 + i * xSpacing;
+		  x1 = S->x1 + (i +1) * xSpacing;
+		 
+		 /* Read of nearest output values */
+		  y0 = pYData[i];
+		  y1 = pYData[i + 1];
+		
+		  /* Calculation of output */
+		  y = y0 + (x - x0) * ((y1 - y0)/(x1-x0));	
+		
+	  }
+
+      /* returns output value */
+	  return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData,
+					      q31_t x, uint32_t nValues)
+  {
+    q31_t y;                                   /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                              /* Index to read nearest output values */
+    
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+	if(index >= (nValues - 1))
+	{
+		return(pYData[nValues - 1]);
+	}
+	else if(index < 0)
+	{
+		return(pYData[0]);
+	}
+	else
+	{
+
+	    /* 20 bits for the fractional part */
+	    /* shift left by 11 to keep fract in 1.31 format */
+	    fract = (x & 0x000FFFFF) << 11;
+	
+	    /* Read two nearest output values from the index in 1.31(q31) format */
+	    y0 = pYData[index];
+	    y1 = pYData[index + 1u];
+	
+	    /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+	    y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+	
+	    /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+	    y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+	
+	    /* Convert y to 1.31 format */
+	    return (y << 1u);
+
+	}
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12. 
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)
+  {
+    q63_t y;                                   /* output */
+    q15_t y0, y1;                              /* Nearest output values */
+    q31_t fract;                               /* fractional part */
+    int32_t index;                            /* Index to read nearest output values */ 
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u); 
+
+	if(index >= (nValues - 1))
+	{
+		return(pYData[nValues - 1]);
+	}
+	else if(index < 0)
+	{
+		return(pYData[0]);
+	}
+	else
+	{	
+	    /* 20 bits for the fractional part */
+	    /* fract is in 12.20 format */
+	    fract = (x & 0x000FFFFF);
+	
+	    /* Read two nearest output values from the index */
+	    y0 = pYData[index];
+	    y1 = pYData[index + 1u];
+	
+	    /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+	    y = ((q63_t) y0 * (0xFFFFF - fract));
+	
+	    /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+	    y += ((q63_t) y1 * (fract));
+	
+	    /* convert y to 1.15 format */
+	    return (y >> 20);
+	}
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x,  uint32_t nValues)
+  {
+    q31_t y;                                   /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                              /* Index to read nearest output values */
+    
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+
+    if(index >= (nValues - 1))
+	{
+		return(pYData[nValues - 1]);
+	}
+	else if(index < 0)
+	{
+		return(pYData[0]);
+	}
+	else
+	{
+
+	    /* 20 bits for the fractional part */
+	    /* fract is in 12.20 format */
+	    fract = (x & 0x000FFFFF);
+	
+	    /* Read two nearest output values from the index and are in 1.7(q7) format */
+	    y0 = pYData[index];
+	    y1 = pYData[index + 1u];
+	
+	    /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+	    y = ((y0 * (0xFFFFF - fract)));
+	
+	    /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+	    y += (y1 * fract);
+	
+	    /* convert y to 1.7(q7) format */
+	    return (y >> 20u);
+
+	}
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+			 float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+		     q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+		     q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+			 float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+		     q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+		     q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.  
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   * 

+   * where x1 is the current estimate,
+   * x0 is the previous estimate and
+   * f'(x0) is the derivative of f() evaluated at x0.
+   * For the square root function, the algorithm reduces to:
+   * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * 

+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status  arm_sqrt_f32(
+					  float32_t in, float32_t *pOut)
+  {
+  	if(in > 0)
+	{
+
+//	#if __FPU_USED
+    #if (__FPU_USED == 1) && defined ( __CC_ARM   )
+		*pOut = __sqrtf(in);
+	#else	  
+		*pOut = sqrtf(in);
+	#endif
+
+		return (ARM_MATH_SUCCESS);
+	}
+  	else
+	{
+		*pOut = 0.0f;
+		return (ARM_MATH_ARGUMENT_ERROR);
+	}
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+		      q31_t in, q31_t *pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+		      q15_t in, q15_t *pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+					     int32_t * circBuffer,
+					     int32_t L,
+					     uint16_t * writeOffset,
+					     int32_t bufferInc,
+					     const int32_t * src,
+					     int32_t srcInc,
+					     uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the input sample to the circular buffer */
+	circBuffer[wOffset] = *src;
+
+	/* Update the input pointer */
+	src += srcInc;
+
+	/* Circularly update wOffset.  Watch out for positive and negative value */
+	wOffset += bufferInc;
+	if(wOffset >= L)
+	  wOffset -= L;
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+					    int32_t * circBuffer,
+					    int32_t L,
+					    int32_t * readOffset,
+					    int32_t bufferInc,
+					    int32_t * dst,
+					    int32_t * dst_base,
+					    int32_t dst_length,
+					    int32_t dstInc,
+					    uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the sample from the circular buffer to the destination buffer */
+	*dst = circBuffer[rOffset];
+
+	/* Update the input pointer */
+	dst += dstInc;
+
+	if(dst == (int32_t *) dst_end)
+	  {
+	    dst = dst_base;
+	  }
+
+	/* Circularly update rOffset.  Watch out for positive and negative value  */
+	rOffset += bufferInc;
+
+	if(rOffset >= L)
+	  {
+	    rOffset -= L;
+	  }
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+					     q15_t * circBuffer,
+					     int32_t L,
+					     uint16_t * writeOffset,
+					     int32_t bufferInc,
+					     const q15_t * src,
+					     int32_t srcInc,
+					     uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the input sample to the circular buffer */
+	circBuffer[wOffset] = *src;
+
+	/* Update the input pointer */
+	src += srcInc;
+
+	/* Circularly update wOffset.  Watch out for positive and negative value */
+	wOffset += bufferInc;
+	if(wOffset >= L)
+	  wOffset -= L;
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+					    q15_t * circBuffer,
+					    int32_t L,
+					    int32_t * readOffset,
+					    int32_t bufferInc,
+					    q15_t * dst,
+					    q15_t * dst_base,
+					    int32_t dst_length,
+					    int32_t dstInc,
+					    uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the sample from the circular buffer to the destination buffer */
+	*dst = circBuffer[rOffset];
+
+	/* Update the input pointer */
+	dst += dstInc;
+
+	if(dst == (q15_t *) dst_end)
+	  {
+	    dst = dst_base;
+	  }
+
+	/* Circularly update wOffset.  Watch out for positive and negative value */
+	rOffset += bufferInc;
+
+	if(rOffset >= L)
+	  {
+	    rOffset -= L;
+	  }
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+					    q7_t * circBuffer,
+					    int32_t L,
+					    uint16_t * writeOffset,
+					    int32_t bufferInc,
+					    const q7_t * src,
+					    int32_t srcInc,
+					    uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the input sample to the circular buffer */
+	circBuffer[wOffset] = *src;
+
+	/* Update the input pointer */
+	src += srcInc;
+
+	/* Circularly update wOffset.  Watch out for positive and negative value */
+	wOffset += bufferInc;
+	if(wOffset >= L)
+	  wOffset -= L;
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+					   q7_t * circBuffer,
+					   int32_t L,
+					   int32_t * readOffset,
+					   int32_t bufferInc,
+					   q7_t * dst,
+					   q7_t * dst_base,
+					   int32_t dst_length,
+					   int32_t dstInc,
+					   uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the sample from the circular buffer to the destination buffer */
+	*dst = circBuffer[rOffset];
+
+	/* Update the input pointer */
+	dst += dstInc;
+
+	if(dst == (q7_t *) dst_end)
+	  {
+	    dst = dst_base;
+	  }
+
+	/* Circularly update rOffset.  Watch out for positive and negative value */
+	rOffset += bufferInc;
+
+	if(rOffset >= L)
+	  {
+	    rOffset -= L;
+	  }
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+		      q31_t * pSrc,
+		     uint32_t blockSize,
+		     q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+		      float32_t * pSrc,
+		     uint32_t blockSize,
+		     float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+		      q15_t * pSrc,
+		     uint32_t blockSize,
+		     q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+		     q7_t * pSrc,
+		    uint32_t blockSize,
+		    q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+		    q7_t * pSrc,
+		   uint32_t blockSize,
+		   q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+		     q15_t * pSrc,
+		    uint32_t blockSize,
+		    q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+		     q31_t * pSrc,
+		    uint32_t blockSize,
+		    q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+		     float32_t * pSrc,
+		    uint32_t blockSize,
+		    float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q63_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+			  float32_t * pSrc,
+			 float32_t * pDst,
+			 uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+			  q31_t * pSrc,
+			 q31_t * pDst,
+			 uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+			  q15_t * pSrc,
+			 q15_t * pDst,
+			 uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+			       q15_t * pSrcA,
+			       q15_t * pSrcB,
+			      uint32_t numSamples,
+			      q31_t * realResult,
+			      q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+			       q31_t * pSrcA,
+			       q31_t * pSrcB,
+			      uint32_t numSamples,
+			      q63_t * realResult,
+			      q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+			       float32_t * pSrcA,
+			       float32_t * pSrcB,
+			      uint32_t numSamples,
+			      float32_t * realResult,
+			      float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+			        q15_t * pSrcCmplx,
+			        q15_t * pSrcReal,
+			       q15_t * pCmplxDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+			        q31_t * pSrcCmplx,
+			        q31_t * pSrcReal,
+			       q31_t * pCmplxDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+			        float32_t * pSrcCmplx,
+			        float32_t * pSrcReal,
+			       float32_t * pCmplxDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+		   q7_t * pSrc,
+		  uint32_t blockSize,
+		  q7_t * result,
+		  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q15_t * pResult,
+		   uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult,
+		   uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult,
+		   uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+		   q7_t * pSrc,
+		  uint32_t blockSize,
+		  q7_t * pResult,
+		  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q15_t * pResult,
+		   uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult,
+		   uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult,
+		   uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+			        q15_t * pSrcA,
+			        q15_t * pSrcB,
+			       q15_t * pDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+			        q31_t * pSrcA,
+			        q31_t * pSrcB,
+			       q31_t * pDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+			        float32_t * pSrcA,
+			        float32_t * pSrcB,
+			       float32_t * pDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return none. 
+   */
+  void arm_float_to_q31(
+			       float32_t * pSrc,
+			      q31_t * pDst,
+			      uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return          none
+   */
+  void arm_float_to_q15(
+			       float32_t * pSrc,
+			      q15_t * pDst,
+			      uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return          none
+   */
+  void arm_float_to_q7(
+			      float32_t * pSrc,
+			     q7_t * pDst,
+			     uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+		       q31_t * pSrc,
+		      q15_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+		      q31_t * pSrc,
+		     q7_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+			 q15_t * pSrc,
+			float32_t * pDst,
+			uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+		       q15_t * pSrc,
+		      q31_t * pDst,
+		      uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+		      q15_t * pSrc,
+		     q7_t * pDst,
+		     uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * Algorithm
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * 

+   *
+   * \par
+   * where numRows specifies the number of rows in the table;
+   * numCols specifies the number of columns in the table;
+   * and pData points to an array of size numRows*numCols values.
+   * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+   *
+   * \par
+   * Let (x, y) specify the desired interpolation point.  Then define:
+   * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * 

+   * \par
+   * The interpolated output point is computed as:
+   * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * 

+   * Note that the coordinates (x, y) contain integer and fractional components.  
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. 
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+  
+  static __INLINE float32_t arm_bilinear_interp_f32(
+						    const arm_bilinear_interp_instance_f32 * S,
+						    float32_t X,
+						    float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+	/* Care taken for table outside boundary */
+	/* Returns zero output when values are outside table boundary */
+	if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0  || yIndex > ( S->numCols-1))
+	{
+		return(0);
+	}
+	
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex-1) *  S->numCols ;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex-1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+     out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+   /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+						arm_bilinear_interp_instance_q31 * S,
+						q31_t X,
+						q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                             /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+	/* Care taken for table outside boundary */
+	/* Returns zero output when values are outside table boundary */
+	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
+	{
+		return(0);
+	}
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+						arm_bilinear_interp_instance_q15 * S,
+						q31_t X,
+						q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                             /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+	/* Care taken for table outside boundary */
+	/* Returns zero output when values are outside table boundary */
+	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
+	{
+		return(0);
+	}
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+					      arm_bilinear_interp_instance_q7 * S,
+					      q31_t X,
+					      q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                             /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+	/* Care taken for table outside boundary */
+	/* Returns zero output when values are outside table boundary */
+	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
+	{
+		return(0);
+	}
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cm0.h b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000..9d7a19f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cm0.h
@@ -0,0 +1,665 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M0
+
+  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+  It consists of:
+
+     - Cortex-M Core Register Definitions
+     - Cortex-M functions
+     - Cortex-M instructions
+
+  The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
+  access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
+  CMSIS violates following MISRA-C2004 Rules:
+  
+   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'. 
+
+   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+   
+   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code. 
+
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+   - CMSIS version number
+   - Cortex-M core
+   - Cortex-M core Revision Number
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x00)                                                       /*!< Cortex core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks */
+#endif
+
+#include                       /*!< standard types definitions                      */
+#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
+#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< defines 'write only' permissions                */
+#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+*/
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CORE CMSIS Core
+  Type definitions for the Cortex-M Core Registers
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_NVIC CMSIS NVIC
+  Type definitions for the Cortex-M NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB CMSIS SCB
+  Type definitions for the Cortex-M System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick CMSIS SysTick
+  Type definitions for the Cortex-M System Timer Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug CMSIS Core Debug
+  Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP
+  and not via processor. Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup  CMSIS_core_register
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    This function enables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    This function disables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    This function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for get pending
+    \return             0  Interrupt status is not pending
+    \return             1  Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    This function sets the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    This function clears the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    This function sets the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    Note: The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for set priority
+    \param [in]  priority  Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    This function reads the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    The returned priority value is automatically aligned to the implemented
+    priority bits of the microcontroller.
+
+    \param [in]   IRQn  Number of the interrupt for get priority
+    \return             Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    This function initialises the system tick timer and its interrupt and start the system tick timer.
+    Counter is in free running mode to generate periodical interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cm3.h b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000..185688f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1244 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V2.11
+ * @date     08. September 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M3
+
+  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+  It consists of:
+
+     - Cortex-M Core Register Definitions
+     - Cortex-M functions
+     - Cortex-M instructions
+
+  The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
+  access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
+  CMSIS violates following MISRA-C2004 Rules:
+  
+   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'. 
+
+   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+   
+   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code. 
+
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+   - CMSIS version number
+   - Cortex-M core
+   - Cortex-M core Revision Number
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+#define __FPU_USED       0 /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks */
+#endif
+
+#include                       /*!< standard types definitions                      */
+#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
+#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< defines 'write only' permissions                */
+#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+*/
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CORE CMSIS Core
+  Type definitions for the Cortex-M Core Registers
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_NVIC CMSIS NVIC
+  Type definitions for the Cortex-M NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB CMSIS SCB
+  Type definitions for the Cortex-M System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
+  Type definitions for the Cortex-M System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick CMSIS SysTick
+  Type definitions for the Cortex-M System Timer Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM CMSIS ITM
+  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU CMSIS MPU
+  Type definitions for the Cortex-M Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug CMSIS Core Debug
+  Type definitions for the Cortex-M Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup  CMSIS_core_register
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+  @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  This function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  This function gets the priority grouping from NVIC Interrupt Controller.
+  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+    \return                Priority grouping field
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    This function enables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    This function disables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    This function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for get pending
+    \return             0  Interrupt status is not pending
+    \return             1  Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    This function sets the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    This function clears the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    This function reads the active register in NVIC and returns the active bit.
+    \param [in]      IRQn  Number of the interrupt for get active
+    \return             0  Interrupt status is not active
+    \return             1  Interrupt status is active
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    This function sets the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    Note: The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for set priority
+    \param [in]  priority  Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    This function reads the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    The returned priority value is automatically aligned to the implemented
+    priority bits of the microcontroller.
+
+    \param [in]   IRQn  Number of the interrupt for get priority
+    \return             Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    This function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The returned priority value can be used for NVIC_SetPriority(...) function
+
+    \param [in]     PriorityGroup  Used priority group
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
+    \param [in]       SubPriority  Sub priority value (starting from 0)
+    \return                        Encoded priority for the interrupt
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    This function decodes an interrupt priority value with the given priority group to
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The priority value can be retrieved with NVIC_GetPriority(...) function
+
+    \param [in]         Priority   Priority value
+    \param [in]     PriorityGroup  Used priority group
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
+    \param [out]     pSubPriority  Sub priority value (starting from 0)
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    This function initialises the system tick timer and its interrupt and start the system tick timer.
+    Counter is in free running mode to generate periodical interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/** \brief  ITM Send Character
+
+    This function transmits a character via the ITM channel 0.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \param [in]     ch  Character to transmit
+    \return             Character to transmit
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
+      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    This function inputs a character via external variable ITM_RxBuffer.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \return             Received character
+    \return         -1  No character received
+ */
+static __INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    This function checks external variable ITM_RxBuffer whether a character is available or not.
+    It returns '1' if a character is available and '0' if no character is available.
+
+    \return          0  No character available
+    \return          1  Character available
+ */
+static __INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cm4.h b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000..bf022ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1378 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M4
+
+  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+  It consists of:
+
+     - Cortex-M Core Register Definitions
+     - Cortex-M functions
+     - Cortex-M instructions
+     - Cortex-M SIMD instructions
+
+  The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease
+  access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
+  CMSIS violates following MISRA-C2004 Rules:
+  
+   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'. 
+
+   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+   
+   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code. 
+
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+   - CMSIS version number
+   - Cortex-M core
+   - Cortex-M core Revision Number
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x04)                                                       /*!< Cortex core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks to define __FPU_USED */
+    #define __FPU_USED         0
+#endif
+
+#include                       /*!< standard types definitions                      */
+#include                 /*!< Core Instruction Access                         */
+#include                  /*!< Core Function Access                            */
+#include                /*!< Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< defines 'write only' permissions                */
+#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+*/
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CORE CMSIS Core
+  Type definitions for the Cortex-M Core Registers
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_NVIC CMSIS NVIC
+  Type definitions for the Cortex-M NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB CMSIS SCB
+  Type definitions for the Cortex-M System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
+  Type definitions for the Cortex-M System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick CMSIS SysTick
+  Type definitions for the Cortex-M System Timer Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM CMSIS ITM
+  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU CMSIS MPU
+  Type definitions for the Cortex-M Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU CMSIS FPU
+  Type definitions for the Cortex-M Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug CMSIS Core Debug
+  Type definitions for the Cortex-M Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup  CMSIS_core_register
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+  @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  This function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  This function gets the priority grouping from NVIC Interrupt Controller.
+  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+    \return                Priority grouping field
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    This function enables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    This function disables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    This function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for get pending
+    \return             0  Interrupt status is not pending
+    \return             1  Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    This function sets the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    This function clears the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    This function reads the active register in NVIC and returns the active bit.
+    \param [in]      IRQn  Number of the interrupt for get active
+    \return             0  Interrupt status is not active
+    \return             1  Interrupt status is active
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    This function sets the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    Note: The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for set priority
+    \param [in]  priority  Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    This function reads the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    The returned priority value is automatically aligned to the implemented
+    priority bits of the microcontroller.
+
+    \param [in]   IRQn  Number of the interrupt for get priority
+    \return             Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    This function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The returned priority value can be used for NVIC_SetPriority(...) function
+
+    \param [in]     PriorityGroup  Used priority group
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
+    \param [in]       SubPriority  Sub priority value (starting from 0)
+    \return                        Encoded priority for the interrupt
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    This function decodes an interrupt priority value with the given priority group to
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The priority value can be retrieved with NVIC_GetPriority(...) function
+
+    \param [in]         Priority   Priority value
+    \param [in]     PriorityGroup  Used priority group
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
+    \param [out]     pSubPriority  Sub priority value (starting from 0)
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    This function initialises the system tick timer and its interrupt and start the system tick timer.
+    Counter is in free running mode to generate periodical interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/** \brief  ITM Send Character
+
+    This function transmits a character via the ITM channel 0.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \param [in]     ch  Character to transmit
+    \return             Character to transmit
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
+      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    This function inputs a character via external variable ITM_RxBuffer.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \return             Received character
+    \return         -1  No character received
+ */
+static __INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    This function checks external variable ITM_RxBuffer whether a character is available or not.
+    It returns '1' if a character is available and '0' if no character is available.
+
+    \return          0  No character available
+    \return          1  Character available
+ */
+static __INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cm4_simd.h b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cm4_simd.h
new file mode 100644
index 0000000..e7b6765
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cm4_simd.h
@@ -0,0 +1,701 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include 
+
+/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
+/* intrinsic __SADD8      see intrinsics.h */
+/* intrinsic __QADD8      see intrinsics.h */
+/* intrinsic __SHADD8     see intrinsics.h */
+/* intrinsic __UADD8      see intrinsics.h */
+/* intrinsic __UQADD8     see intrinsics.h */
+/* intrinsic __UHADD8     see intrinsics.h */
+/* intrinsic __SSUB8      see intrinsics.h */
+/* intrinsic __QSUB8      see intrinsics.h */
+/* intrinsic __SHSUB8     see intrinsics.h */
+/* intrinsic __USUB8      see intrinsics.h */
+/* intrinsic __UQSUB8     see intrinsics.h */
+/* intrinsic __UHSUB8     see intrinsics.h */
+/* intrinsic __SADD16     see intrinsics.h */
+/* intrinsic __QADD16     see intrinsics.h */
+/* intrinsic __SHADD16    see intrinsics.h */
+/* intrinsic __UADD16     see intrinsics.h */
+/* intrinsic __UQADD16    see intrinsics.h */
+/* intrinsic __UHADD16    see intrinsics.h */
+/* intrinsic __SSUB16     see intrinsics.h */
+/* intrinsic __QSUB16     see intrinsics.h */
+/* intrinsic __SHSUB16    see intrinsics.h */
+/* intrinsic __USUB16     see intrinsics.h */
+/* intrinsic __UQSUB16    see intrinsics.h */
+/* intrinsic __UHSUB16    see intrinsics.h */
+/* intrinsic __SASX       see intrinsics.h */
+/* intrinsic __QASX       see intrinsics.h */
+/* intrinsic __SHASX      see intrinsics.h */
+/* intrinsic __UASX       see intrinsics.h */
+/* intrinsic __UQASX      see intrinsics.h */
+/* intrinsic __UHASX      see intrinsics.h */
+/* intrinsic __SSAX       see intrinsics.h */
+/* intrinsic __QSAX       see intrinsics.h */
+/* intrinsic __SHSAX      see intrinsics.h */
+/* intrinsic __USAX       see intrinsics.h */
+/* intrinsic __UQSAX      see intrinsics.h */
+/* intrinsic __UHSAX      see intrinsics.h */
+/* intrinsic __USAD8      see intrinsics.h */
+/* intrinsic __USADA8     see intrinsics.h */
+/* intrinsic __SSAT16     see intrinsics.h */
+/* intrinsic __USAT16     see intrinsics.h */
+/* intrinsic __UXTB16     see intrinsics.h */
+/* intrinsic __SXTB16     see intrinsics.h */
+/* intrinsic __UXTAB16    see intrinsics.h */
+/* intrinsic __SXTAB16    see intrinsics.h */
+/* intrinsic __SMUAD      see intrinsics.h */
+/* intrinsic __SMUADX     see intrinsics.h */
+/* intrinsic __SMLAD      see intrinsics.h */
+/* intrinsic __SMLADX     see intrinsics.h */
+/* intrinsic __SMLALD     see intrinsics.h */
+/* intrinsic __SMLALDX    see intrinsics.h */
+/* intrinsic __SMUSD      see intrinsics.h */
+/* intrinsic __SMUSDX     see intrinsics.h */
+/* intrinsic __SMLSD      see intrinsics.h */
+/* intrinsic __SMLSDX     see intrinsics.h */
+/* intrinsic __SMLSLD     see intrinsics.h */
+/* intrinsic __SMLSLDX    see intrinsics.h */
+/* intrinsic __SEL        see intrinsics.h */
+/* intrinsic __QADD       see intrinsics.h */
+/* intrinsic __QSUB       see intrinsics.h */
+/* intrinsic __PKHBT      see intrinsics.h */
+/* intrinsic __PKHTB      see intrinsics.h */
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+  
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else	\
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cmFunc.h b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000..88819f9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,609 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V2.10
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface   
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+static __INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+static __INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+static __INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+static __INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+ 
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include 
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cmInstr.h b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000..78d2ef8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,585 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static __INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz 
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include 
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint8_t result;
+  
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint16_t result;
+  
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+  
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint8_t result;
+  
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Lib/ARM/arm_cortexM3b_math.lib b/hardware/digistump/sam/system/CMSIS/CMSIS/Lib/ARM/arm_cortexM3b_math.lib
new file mode 100644
index 0000000..bad3306
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Lib/ARM/arm_cortexM3l_math.lib b/hardware/digistump/sam/system/CMSIS/CMSIS/Lib/ARM/arm_cortexM3l_math.lib
new file mode 100644
index 0000000..1139c73
Binary files /dev/null and b/hardware/digistump/sam/system/CMSIS/CMSIS/Lib/ARM/arm_cortexM3l_math.lib differ
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/Lib/GCC/libarm_cortexM3l_math.a b/hardware/digistump/sam/system/CMSIS/CMSIS/Lib/GCC/libarm_cortexM3l_math.a
new file mode 100644
index 0000000..89b0214
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diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/README.txt b/hardware/digistump/sam/system/CMSIS/CMSIS/README.txt
new file mode 100644
index 0000000..b0416f5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/README.txt
@@ -0,0 +1,34 @@
+* -------------------------------------------------------------------
+* Copyright (C) 2011 ARM Limited. All rights reserved.  
+* 
+* Date:        25 July 2011  
+* Revision:    V2.10 
+*  
+* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
+* Title:       Release Note for CMSIS
+*
+* -------------------------------------------------------------------
+
+
+NOTE - Open the index.html file to access CMSIS documentation
+
+
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
+and reduces time-to-market for new embedded applications.
+
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
+Any user of the software package is bound to the terms and conditions of the end user license agreement.
+
+
+You will find the following sub-directories:
+
+Documentation           - Contains CMSIS documentation.
+ 
+DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
+                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
+
+Include                 - CMSIS Core Support and CMSIS DSP Include Files.
+
+Lib                     - CMSIS DSP Binaries 
+---
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/CMSIS/index.htm b/hardware/digistump/sam/system/CMSIS/CMSIS/index.htm
new file mode 100644
index 0000000..823b361
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/CMSIS/index.htm
@@ -0,0 +1,115 @@
+
+
+
+CMSIS Release Notes
+
+
+
+
+
+
+
+
+
CMSIS Release Notes

+
Release Notes for CMSIS V2.00

+
November 2010

+
+
Information in this file, the accompany manuals, and software is

+                 Copyright © ARM Ltd.
All rights reserved.
+

+

+
+

+
+
Contents

+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Include/ARMCM0.h b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Include/ARMCM0.h
new file mode 100644
index 0000000..6a08082
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Include/ARMCM0.h
@@ -0,0 +1,113 @@
+/**************************************************************************//**
+ * @file     ARMCM0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef ARMCM0_H
+#define ARMCM0_H
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!<  2 Cortex-M0 Non Maskable Interrupt                  */
+  HardFault_IRQn              = -13,    /*!<  3 Cortex-M0 Hard Fault Interrupt                    */
+
+
+
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                       */
+
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                       */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                   */
+
+/******  ARMCM0 specific Interrupt Numbers ********************************************************/
+  GPIO_IRQn                   = 0       /*!< GPIO Interrupt                                       */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M0 Processor and Core Peripherals */
+#define __CM0_REV                 0x0000    /*!< Core Revision r0p0                               */
+#define __MPU_PRESENT             0         /*!< MPU present or not                               */
+#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+
+
+#include                        /* Cortex-M0 processor and core peripherals           */
+#include "system_ARMCM0.h"                  /* System Header                                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+
+/*--------------------- General Purpose Input and Ouptut ---------------------*/
+typedef union
+{
+  __IO uint32_t WORD;  
+  __IO uint8_t  BYTE[4];
+} GPIO_Data_TypeDef;
+
+typedef struct
+{
+  GPIO_Data_TypeDef DATA [256];
+  __O uint32_t  DIR;
+  uint32_t      RESERVED[3];
+  __O uint32_t  IE;
+} ARM_GPIO_TypeDef;
+
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* Peripheral and SRAM base address */
+#define ARM_SRAM_BASE             ((     uint32_t)0x20000000UL)
+#define ARM_PERIPH_BASE           ((     uint32_t)0x40000000UL)
+
+/* Peripheral memory map */
+#define ARM_GPIO_BASE              ARM_PERIPH_BASE
+
+#define ARM_GPIO0_BASE            (ARM_GPIO_BASE)
+#define ARM_GPIO1_BASE            (ARM_GPIO_BASE       + 0x0800UL)
+#define ARM_GPIO2_BASE            (ARM_GPIO_BASE       + 0x1000UL)
+
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+#define ARM_GPIO0                ((ARM_GPIO_TypeDef *) ARM_GPIO0_BASE)
+#define ARM_GPIO1                ((ARM_GPIO_TypeDef *) ARM_GPIO1_BASE)
+#define ARM_GPIO2                ((ARM_GPIO_TypeDef *) ARM_GPIO2_BASE)
+
+
+#endif  /* ARMCM0_H */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Include/system_ARMCM0.h b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Include/system_ARMCM0.h
new file mode 100644
index 0000000..5af6a1a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Include/system_ARMCM0.h
@@ -0,0 +1,62 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.h
+ * @brief    CMSIS Cortex-M0 Device System Header File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef SYSTEM_ARMCM0_H
+#define SYSTEM_ARMCM0_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ARMCM0_H */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/ARM/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..734d82c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/ARM/startup_ARMCM0.s
@@ -0,0 +1,161 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM0 Device Series
+; * @version  V1.05
+; * @date     25. July 2011
+; *
+; * @note
+; * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/GCC/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/GCC/startup_ARMCM0.s
new file mode 100644
index 0000000..a4c9ec7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/GCC/startup_ARMCM0.s
@@ -0,0 +1,168 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM0.s
+ * @brief    CMSIS Cortex-M4 Core Device Startup File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     25. July 2011
+ *
+ * @note     Version CodeSourcery Sourcery G++ Lite (with CS3)
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+/*
+//  Stack Configuration
+//    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Stack_Size, 0x00000400
+    .section ".stack", "w"
+    .align  3
+    .globl  __cs3_stack_mem
+    .globl  __cs3_stack_size
+__cs3_stack_mem:
+    .if     Stack_Size
+    .space  Stack_Size
+    .endif
+    .size   __cs3_stack_mem,  . - __cs3_stack_mem
+    .set    __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+//  Heap Configuration
+//     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Heap_Size,  0x00000000
+    
+    .section ".heap", "w"
+    .align  3
+    .globl  __cs3_heap_start
+    .globl  __cs3_heap_end
+__cs3_heap_start:
+    .if     Heap_Size
+    .space  Heap_Size
+    .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+    .section ".cs3.interrupt_vector"
+    .globl  __cs3_interrupt_vector_cortex_m
+    .type   __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+    .long   __cs3_stack                 /* Top of Stack                 */
+    .long   __cs3_reset                 /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+    /* External Interrupts */
+    .long   DEF_IRQHandler              /*  0: Default                  */
+
+
+    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+    .thumb
+
+
+/* Reset Handler */
+
+    .section .cs3.reset,"x",%progbits
+    .thumb_func
+    .globl  __cs3_reset_cortex_m
+    .type   __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+    .fnstart
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0,=_start
+    BX      R0
+    .pool
+    .cantunwind
+    .fnend
+    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ     DEF_IRQHandler
+
+    .end
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/GCC_ARM/gcc_arm.ld b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/GCC_ARM/gcc_arm.ld
new file mode 100644
index 0000000..7d21bb6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/GCC_ARM/gcc_arm.ld
@@ -0,0 +1,147 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128k */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32k */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.isr_vector))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab : 
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	__etext = .;
+		
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE (__preinit_array_start = .);
+		*(.preinit_array)
+		PROVIDE (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE (__init_array_start = .);
+		*(SORT(.init_array.*))
+		*(.init_array)
+		PROVIDE (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE (__fini_array_start = .);
+		*(SORT(.fini_array.*))
+		*(.fini_array)
+		PROVIDE (__fini_array_end = .);
+
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		__bss_end__ = .;
+	} > RAM
+	
+	.heap :
+	{
+		__end__ = .;
+		end = __end__;
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy :
+	{
+		*(.stack)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+	
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/GCC_ARM/startup_ARMCM0.S b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/GCC_ARM/startup_ARMCM0.S
new file mode 100644
index 0000000..ab79108
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/GCC_ARM/startup_ARMCM0.S
@@ -0,0 +1,151 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with 
+ *   GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ * 
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the ARM Limited nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+    .syntax unified
+    .arch armv6-m
+
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0xc00
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x100
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+    
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    NMI_Handler           /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+    /* External interrupts */
+    .long    Default_Handler
+    
+    .size    __isr_vector, . - __isr_vector
+
+    .text
+    .thumb
+    .thumb_func
+    .align 2
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in 
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble    .flash_to_ram_loop_end
+
+    movs    r4, 0
+.flash_to_ram_loop:
+    ldr    r0, [r1,r4]
+    str    r0, [r2,r4]
+    adds    r4, 4
+    cmp    r4, r3
+    blt    .flash_to_ram_loop
+.flash_to_ram_loop_end:
+
+    ldr    r0, =SystemInit
+    blx    r0
+    ldr    r0, =_start
+    bx    r0
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+    
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_default_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+    
+    def_default_handler    NMI_Handler
+    def_default_handler    HardFault_Handler
+    def_default_handler    SVC_Handler
+    def_default_handler    PendSV_Handler
+    def_default_handler    SysTick_Handler
+    def_default_handler    Default_Handler
+
+    .weak    DEF_IRQHandler
+    .set    DEF_IRQHandler, Default_Handler
+
+    .end
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/IAR/startup_ARMCM0.s b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/IAR/startup_ARMCM0.s
new file mode 100644
index 0000000..9dd3ea1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/IAR/startup_ARMCM0.s
@@ -0,0 +1,129 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM0 Device Series
+; * @version  V1.05
+; * @date     25. July 2011
+; *
+; * @note
+; * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+	
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     0
+        DCD     0
+        DCD     0
+__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     0
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK DEF_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DEF_IRQHandler
+        B DEF_IRQHandler
+
+        END
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/system_ARMCM0.c b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/system_ARMCM0.c
new file mode 100644
index 0000000..ece74d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM0/Source/Templates/system_ARMCM0.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Cortex-M0 Device System Source File
+ *           for CM0 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Include/ARMCM3.h b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Include/ARMCM3.h
new file mode 100644
index 0000000..b42f043
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Include/ARMCM3.h
@@ -0,0 +1,113 @@
+/**************************************************************************//**
+ * @file     ARMCM3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef ARMCM3_H
+#define ARMCM3_H
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!<  2 Cortex-M3 Non Maskable Interrupt                  */
+  HardFault_IRQn              = -13,    /*!<  3 Cortex-M3 Hard Fault Interrupt                    */
+  MemoryManagement_IRQn       = -12,    /*!<  4 Cortex-M3 Memory Management Interrupt             */
+  BusFault_IRQn               = -11,    /*!<  5 Cortex-M3 Bus Fault Interrupt                     */
+  UsageFault_IRQn             = -10,    /*!<  6 Cortex-M3 Usage Fault Interrupt                   */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
+
+/******  ARMCM3 specific Interrupt Numbers ********************************************************/
+  GPIO_IRQn                   = 0       /*!< GPIO Interrupt                                       */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __CM3_REV                 0x0201    /*!< Core Revision r2p1                               */
+#define __MPU_PRESENT             1         /*!< MPU present or not                               */
+#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+
+
+#include                        /* Cortex-M3 processor and core peripherals           */
+#include "system_ARMCM3.h"                  /* System Header                                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+
+/*--------------------- General Purpose Input and Ouptut ---------------------*/
+typedef union
+{
+  __IO uint32_t WORD;  
+  __IO uint8_t  BYTE[4];
+} GPIO_Data_TypeDef;
+
+typedef struct
+{
+  GPIO_Data_TypeDef DATA [256];
+  __O uint32_t  DIR;
+  uint32_t      RESERVED[3];
+  __O uint32_t  IE;
+} ARM_GPIO_TypeDef;
+
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* Peripheral and SRAM base address */
+#define ARM_SRAM_BASE             ((     uint32_t)0x20000000UL)
+#define ARM_PERIPH_BASE           ((     uint32_t)0x40000000UL)
+
+/* Peripheral memory map */
+#define ARM_GPIO_BASE              ARM_PERIPH_BASE
+
+#define ARM_GPIO0_BASE            (ARM_GPIO_BASE)
+#define ARM_GPIO1_BASE            (ARM_GPIO_BASE       + 0x0800UL)
+#define ARM_GPIO2_BASE            (ARM_GPIO_BASE       + 0x1000UL)
+
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+#define ARM_GPIO0                ((ARM_GPIO_TypeDef *) ARM_GPIO0_BASE)
+#define ARM_GPIO1                ((ARM_GPIO_TypeDef *) ARM_GPIO1_BASE)
+#define ARM_GPIO2                ((ARM_GPIO_TypeDef *) ARM_GPIO2_BASE)
+
+
+#endif  /* ARMCM3_H */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Include/system_ARMCM3.h b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Include/system_ARMCM3.h
new file mode 100644
index 0000000..abaeb73
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Include/system_ARMCM3.h
@@ -0,0 +1,62 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.h
+ * @brief    CMSIS Cortex-M3 Device System Header File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef SYSTEM_ARMCM3_H
+#define SYSTEM_ARMCM3_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ARMCM3_H */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/ARM/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..6fa12ec
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/ARM/startup_ARMCM3.s
@@ -0,0 +1,181 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM3 Device Series
+; * @version  V1.05
+; * @date     25. July 2011
+; *
+; * @note
+; * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/GCC/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/GCC/startup_ARMCM3.s
new file mode 100644
index 0000000..812127e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/GCC/startup_ARMCM3.s
@@ -0,0 +1,192 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM3.s
+ * @brief    CMSIS Cortex-M4 Core Device Startup File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     25. July 2011
+ *
+ * @note     Version CodeSourcery Sourcery G++ Lite (with CS3)
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+/*
+//  Stack Configuration
+//    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Stack_Size, 0x00000400
+    .section ".stack", "w"
+    .align  3
+    .globl  __cs3_stack_mem
+    .globl  __cs3_stack_size
+__cs3_stack_mem:
+    .if     Stack_Size
+    .space  Stack_Size
+    .endif
+    .size   __cs3_stack_mem,  . - __cs3_stack_mem
+    .set    __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+//  Heap Configuration
+//     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Heap_Size,  0x00000000
+    
+    .section ".heap", "w"
+    .align  3
+    .globl  __cs3_heap_start
+    .globl  __cs3_heap_end
+__cs3_heap_start:
+    .if     Heap_Size
+    .space  Heap_Size
+    .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+    .section ".cs3.interrupt_vector"
+    .globl  __cs3_interrupt_vector_cortex_m
+    .type   __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+    .long   __cs3_stack                 /* Top of Stack                 */
+    .long   __cs3_reset                 /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   MemManage_Handler           /* MPU Fault Handler            */
+    .long   BusFault_Handler            /* Bus Fault Handler            */
+    .long   UsageFault_Handler          /* Usage Fault Handler          */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   DebugMon_Handler            /* Debug Monitor Handler        */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+    /* External Interrupts */
+    .long   DEF_IRQHandler              /*  0: Default                  */
+
+
+    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+    .thumb
+
+
+/* Reset Handler */
+
+    .section .cs3.reset,"x",%progbits
+    .thumb_func
+    .globl  __cs3_reset_cortex_m
+    .type   __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+    .fnstart
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0,=_start
+    BX      R0
+    .pool
+    .cantunwind
+    .fnend
+    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B       .
+    .size   MemManage_Handler, . - MemManage_Handler
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B       .
+    .size   DebugMon_Handler, . - DebugMon_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ     DEF_IRQHandler
+
+    .end
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/GCC_ARM/gcc_arm.ld b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/GCC_ARM/gcc_arm.ld
new file mode 100644
index 0000000..7d21bb6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/GCC_ARM/gcc_arm.ld
@@ -0,0 +1,147 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128k */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32k */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.isr_vector))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab : 
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	__etext = .;
+		
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE (__preinit_array_start = .);
+		*(.preinit_array)
+		PROVIDE (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE (__init_array_start = .);
+		*(SORT(.init_array.*))
+		*(.init_array)
+		PROVIDE (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE (__fini_array_start = .);
+		*(SORT(.fini_array.*))
+		*(.fini_array)
+		PROVIDE (__fini_array_end = .);
+
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		__bss_end__ = .;
+	} > RAM
+	
+	.heap :
+	{
+		__end__ = .;
+		end = __end__;
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy :
+	{
+		*(.stack)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+	
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/GCC_ARM/startup_ARMCM3.S b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/GCC_ARM/startup_ARMCM3.S
new file mode 100644
index 0000000..7d1bf18
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/GCC_ARM/startup_ARMCM3.S
@@ -0,0 +1,165 @@
+/* File: startup_ARMCM3.S
+ * Purpose: startup file for Cortex-M3 devices. Should use with 
+ *   GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ * 
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the ARM Limited nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+    .syntax unified
+    .arch armv7-m
+
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0xc00
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x800
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+    
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    NMI_Handler           /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    MemManage_Handler     /* MPU Fault Handler */
+    .long    BusFault_Handler      /* Bus Fault Handler */
+    .long    UsageFault_Handler    /* Usage Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    DebugMon_Handler      /* Debug Monitor Handler */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+    /* External interrupts */
+    .long    Default_Handler
+    
+    .size    __isr_vector, . - __isr_vector
+
+    .text
+    .thumb
+    .thumb_func
+    .align 2
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in 
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+#if 1
+/* Here are two copies of loop implemenations. First one favors code size
+ * and the second one favors performance. Default uses the first one. 
+ * Change to "#if 0" to use the second one */
+.flash_to_ram_loop:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .flash_to_ram_loop
+#else
+    subs    r3, r2
+    ble    .flash_to_ram_loop_end    
+.flash_to_ram_loop:
+    subs    r3, #4
+    ldr    r0, [r1, r3]
+    str    r0, [r2, r3]
+    bgt    .flash_to_ram_loop
+.flash_to_ram_loop_end:
+#endif
+
+
+    ldr    r0, =SystemInit
+    blx    r0
+    ldr    r0, =_start
+    bx    r0
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+    
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_default_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+    
+    def_default_handler    NMI_Handler
+    def_default_handler    HardFault_Handler
+    def_default_handler    MemManage_Handler
+    def_default_handler    BusFault_Handler
+    def_default_handler    UsageFault_Handler
+    def_default_handler    SVC_Handler
+    def_default_handler    DebugMon_Handler
+    def_default_handler    PendSV_Handler
+    def_default_handler    SysTick_Handler
+    def_default_handler    Default_Handler
+
+    .weak    DEF_IRQHandler
+    .set    DEF_IRQHandler, Default_Handler
+
+    .end
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/IAR/startup_ARMCM3.s b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/IAR/startup_ARMCM3.s
new file mode 100644
index 0000000..0071c5c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/IAR/startup_ARMCM3.s
@@ -0,0 +1,151 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM3 Device Series
+; * @version  V1.05
+; * @date     25. July 2011
+; *
+; * @note
+; * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+	
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK DEF_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DEF_IRQHandler
+        B DEF_IRQHandler
+
+        END
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/system_ARMCM3.c b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/system_ARMCM3.c
new file mode 100644
index 0000000..2f5fa0b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM3/Source/Templates/system_ARMCM3.c
@@ -0,0 +1,76 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Cortex-M3 Device System Source File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Include/ARMCM4.h b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Include/ARMCM4.h
new file mode 100644
index 0000000..7127f77
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Include/ARMCM4.h
@@ -0,0 +1,114 @@
+/**************************************************************************//**
+ * @file     ARMCM4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef ARMCM4_H
+#define ARMCM4_H
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers ***************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!<  2 Cortex-M4 Non Maskable Interrupt                  */
+  HardFault_IRQn              = -13,    /*!<  3 Cortex-M4 Hard Fault Interrupt                    */
+  MemoryManagement_IRQn       = -12,    /*!<  4 Cortex-M4 Memory Management Interrupt             */
+  BusFault_IRQn               = -11,    /*!<  5 Cortex-M4 Bus Fault Interrupt                     */
+  UsageFault_IRQn             = -10,    /*!<  6 Cortex-M4 Usage Fault Interrupt                   */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                       */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                 */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                       */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                   */
+
+/******  ARMCM4 specific Interrupt Numbers ********************************************************/
+  GPIO_IRQn                   = 0       /*!< GPIO Interrupt                                       */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M4 Processor and Core Peripherals */
+#define __CM4_REV                 0x0001    /*!< Core revision r0p1                               */
+#define __MPU_PRESENT             1         /*!< MPU present or not                               */
+#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+#define __FPU_PRESENT             1         /*!< FPU present or not                               */
+
+
+#include                        /* Cortex-M4 processor and core peripherals           */
+#include "system_ARMCM4.h"                  /* System Header                                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+
+/*--------------------- General Purpose Input and Ouptut ---------------------*/
+typedef union
+{
+  __IO uint32_t WORD;  
+  __IO uint8_t  BYTE[4];
+} GPIO_Data_TypeDef;
+
+typedef struct
+{
+  GPIO_Data_TypeDef DATA [256];
+  __O uint32_t  DIR;
+  uint32_t      RESERVED[3];
+  __O uint32_t  IE;
+} ARM_GPIO_TypeDef;
+
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* Peripheral and SRAM base address */
+#define ARM_SRAM_BASE             ((     uint32_t)0x20000000UL)
+#define ARM_PERIPH_BASE           ((     uint32_t)0x40000000UL)
+
+/* Peripheral memory map */
+#define ARM_GPIO_BASE              ARM_PERIPH_BASE
+
+#define ARM_GPIO0_BASE            (ARM_GPIO_BASE)
+#define ARM_GPIO1_BASE            (ARM_GPIO_BASE       + 0x0800UL)
+#define ARM_GPIO2_BASE            (ARM_GPIO_BASE       + 0x1000UL)
+
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+#define ARM_GPIO0                ((ARM_GPIO_TypeDef *) ARM_GPIO0_BASE)
+#define ARM_GPIO1                ((ARM_GPIO_TypeDef *) ARM_GPIO1_BASE)
+#define ARM_GPIO2                ((ARM_GPIO_TypeDef *) ARM_GPIO2_BASE)
+
+
+#endif  /* ARMCM4_H */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Include/system_ARMCM4.h b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Include/system_ARMCM4.h
new file mode 100644
index 0000000..d50df10
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Include/system_ARMCM4.h
@@ -0,0 +1,62 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.h
+ * @brief    CMSIS Cortex-M4 Device System Header File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef SYSTEM_ARMCM4_H
+#define SYSTEM_ARMCM4_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ARMCM4_H */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/ARM/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..7d0b3c4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/ARM/startup_ARMCM4.s
@@ -0,0 +1,181 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM4 Device Series
+; * @version  V1.05
+; * @date     25. July 2011
+; *
+; * @note
+; * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DEF_IRQHandler            [WEAK]
+DEF_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/GCC/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/GCC/startup_ARMCM4.s
new file mode 100644
index 0000000..26d0f9c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/GCC/startup_ARMCM4.s
@@ -0,0 +1,192 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM4.s
+ * @brief    CMSIS Cortex-M4 Core Device Startup File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     25. July 2011
+ *
+ * @note     Version CodeSourcery Sourcery G++ Lite (with CS3)
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+/*
+//  Stack Configuration
+//    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Stack_Size, 0x00000400
+    .section ".stack", "w"
+    .align  3
+    .globl  __cs3_stack_mem
+    .globl  __cs3_stack_size
+__cs3_stack_mem:
+    .if     Stack_Size
+    .space  Stack_Size
+    .endif
+    .size   __cs3_stack_mem,  . - __cs3_stack_mem
+    .set    __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+//  Heap Configuration
+//     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// 
+*/
+
+    .equ    Heap_Size,  0x00000000
+    
+    .section ".heap", "w"
+    .align  3
+    .globl  __cs3_heap_start
+    .globl  __cs3_heap_end
+__cs3_heap_start:
+    .if     Heap_Size
+    .space  Heap_Size
+    .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+    .section ".cs3.interrupt_vector"
+    .globl  __cs3_interrupt_vector_cortex_m
+    .type   __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+    .long   __cs3_stack                 /* Top of Stack                 */
+    .long   __cs3_reset                 /* Reset Handler                */
+    .long   NMI_Handler                 /* NMI Handler                  */
+    .long   HardFault_Handler           /* Hard Fault Handler           */
+    .long   MemManage_Handler           /* MPU Fault Handler            */
+    .long   BusFault_Handler            /* Bus Fault Handler            */
+    .long   UsageFault_Handler          /* Usage Fault Handler          */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   0                           /* Reserved                     */
+    .long   SVC_Handler                 /* SVCall Handler               */
+    .long   DebugMon_Handler            /* Debug Monitor Handler        */
+    .long   0                           /* Reserved                     */
+    .long   PendSV_Handler              /* PendSV Handler               */
+    .long   SysTick_Handler             /* SysTick Handler              */
+
+    /* External Interrupts */
+    .long   DEF_IRQHandler              /*  0: Default                  */
+
+
+    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+    .thumb
+
+
+/* Reset Handler */
+
+    .section .cs3.reset,"x",%progbits
+    .thumb_func
+    .globl  __cs3_reset_cortex_m
+    .type   __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+    .fnstart
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0,=_start
+    BX      R0
+    .pool
+    .cantunwind
+    .fnend
+    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+    .section ".text"
+
+/* Exception Handlers */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B       .
+    .size   MemManage_Handler, . - MemManage_Handler
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B       .
+    .size   DebugMon_Handler, . - DebugMon_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ     DEF_IRQHandler
+
+    .end
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/GCC_ARM/gcc_arm.ld b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/GCC_ARM/gcc_arm.ld
new file mode 100644
index 0000000..7d21bb6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/GCC_ARM/gcc_arm.ld
@@ -0,0 +1,147 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128k */
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32k */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.isr_vector))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab : 
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	__etext = .;
+		
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE (__preinit_array_start = .);
+		*(.preinit_array)
+		PROVIDE (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE (__init_array_start = .);
+		*(SORT(.init_array.*))
+		*(.init_array)
+		PROVIDE (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE (__fini_array_start = .);
+		*(SORT(.fini_array.*))
+		*(.fini_array)
+		PROVIDE (__fini_array_end = .);
+
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		__bss_end__ = .;
+	} > RAM
+	
+	.heap :
+	{
+		__end__ = .;
+		end = __end__;
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy :
+	{
+		*(.stack)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+	
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/GCC_ARM/startup_ARMCM4.S b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/GCC_ARM/startup_ARMCM4.S
new file mode 100644
index 0000000..a6de1d7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/GCC_ARM/startup_ARMCM4.S
@@ -0,0 +1,164 @@
+/* File: startup_ARMCM4.S
+ * Purpose: startup file for Cortex-M4 devices. Should use with 
+ *   GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ * 
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the ARM Limited nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+    .syntax unified
+    .arch armv7-m
+
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0xc00
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x800
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+    
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    NMI_Handler           /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    MemManage_Handler     /* MPU Fault Handler */
+    .long    BusFault_Handler      /* Bus Fault Handler */
+    .long    UsageFault_Handler    /* Usage Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    DebugMon_Handler      /* Debug Monitor Handler */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+    /* External interrupts */
+    .long    Default_Handler
+    
+    .size    __isr_vector, . - __isr_vector
+
+    .text
+    .thumb
+    .thumb_func
+    .align 2
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in 
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+#if 1
+/* Here are two copies of loop implemenations. First one favors code size
+ * and the second one favors performance. Default uses the first one. 
+ * Change to "#if 0" to use the second one */
+.flash_to_ram_loop:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .flash_to_ram_loop
+#else
+    subs    r3, r2
+    ble    .flash_to_ram_loop_end    
+.flash_to_ram_loop:
+    subs    r3, #4
+    ldr    r0, [r1, r3]
+    str    r0, [r2, r3]
+    bgt    .flash_to_ram_loop
+.flash_to_ram_loop_end:
+#endif
+
+    ldr    r0, =SystemInit
+    blx    r0
+    ldr    r0, =_start
+    bx    r0
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+    
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_default_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+    
+    def_default_handler    NMI_Handler
+    def_default_handler    HardFault_Handler
+    def_default_handler    MemManage_Handler
+    def_default_handler    BusFault_Handler
+    def_default_handler    UsageFault_Handler
+    def_default_handler    SVC_Handler
+    def_default_handler    DebugMon_Handler
+    def_default_handler    PendSV_Handler
+    def_default_handler    SysTick_Handler
+    def_default_handler    Default_Handler
+
+    .weak    DEF_IRQHandler
+    .set    DEF_IRQHandler, Default_Handler
+
+    .end
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/IAR/startup_ARMCM4.s b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/IAR/startup_ARMCM4.s
new file mode 100644
index 0000000..27551c5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/IAR/startup_ARMCM4.s
@@ -0,0 +1,151 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File
+; *           for CM4 Device Series
+; * @version  V1.05
+; * @date     25. July 2011
+; *
+; * @note
+; * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+	
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD     DEF_IRQHandler            ;  0: Default
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU   __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK DEF_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DEF_IRQHandler
+        B DEF_IRQHandler
+
+        END
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/system_ARMCM4.c b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/system_ARMCM4.c
new file mode 100644
index 0000000..beaaf6f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ARM/ARMCM4/Source/Templates/system_ARMCM4.c
@@ -0,0 +1,81 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Cortex-M4 Device System Source File
+ *           for CM4 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include "ARMCM4.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
+                   (3UL << 11*2)  );               /* set CP11 Full Access */
+  #endif
+
+  SystemCoreClock = __SYSTEM_CLOCK;
+
+#ifdef __USE_GPIO
+  ARM_GPIO0->DATA[0].WORD = 0;
+  ARM_GPIO0->IE = 0;
+  ARM_GPIO0->DIR = 0xff83;
+  
+  ARM_GPIO1->DATA[0].WORD = 0;
+  ARM_GPIO1->IE = 0;
+  ARM_GPIO1->DIR = 0;
+  
+  ARM_GPIO2->DATA[0].WORD = 0;
+  ARM_GPIO2->IE = 0;
+  ARM_GPIO2->DIR = 0;
+#endif
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam.h
new file mode 100644
index 0000000..2c10bba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam.h
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM_INCLUDED_
+#define _SAM_INCLUDED_
+
+#define part_is_defined(part) (defined(__ ## part ## __))
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAM3 family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAM3N series */
+#define SAM3N00 ( \
+    part_is_defined( SAM3N00A ) || \
+    part_is_defined( SAM3N00B ) )
+
+#define SAM3N0 ( \
+    part_is_defined( SAM3N0A ) || \
+    part_is_defined( SAM3N0B ) || \
+    part_is_defined( SAM3N0C ) )
+
+#define SAM3N1 ( \
+    part_is_defined( SAM3N1A ) || \
+    part_is_defined( SAM3N1B ) || \
+    part_is_defined( SAM3N1C ) )
+
+#define SAM3N2 ( \
+    part_is_defined( SAM3N2A ) || \
+    part_is_defined( SAM3N2B ) || \
+    part_is_defined( SAM3N2C ) )
+
+#define SAM3N4 ( \
+    part_is_defined( SAM3N4A ) || \
+    part_is_defined( SAM3N4B ) || \
+    part_is_defined( SAM3N4C ) )
+
+/* Entire SAM3N series */
+#define SAM3N_SERIES (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4)
+
+
+/* SAM3S series */
+#define SAM3S00 ( \
+    part_is_defined( SAM3S00A ) || \
+    part_is_defined( SAM3S00B ) )
+
+#define SAM3S0 ( \
+    part_is_defined( SAM3S0A ) || \
+    part_is_defined( SAM3S0B ) || \
+    part_is_defined( SAM3S0C ) )
+
+#define SAM3S1 ( \
+    part_is_defined( SAM3S1A ) || \
+    part_is_defined( SAM3S1B ) || \
+    part_is_defined( SAM3S1C ) )
+
+#define SAM3S2 ( \
+    part_is_defined( SAM3S2A ) || \
+    part_is_defined( SAM3S2B ) || \
+    part_is_defined( SAM3S2C ) )
+
+#define SAM3S4 ( \
+    part_is_defined( SAM3S4A ) || \
+    part_is_defined( SAM3S4B ) || \
+    part_is_defined( SAM3S4C ) )
+
+/* Entire SAM3S series */
+#define SAM3S_SERIES (SAM3S00 || SAM3S0 ||SAM3S1 || SAM3S2 || SAM3S4)
+
+/* SAM3SD8 series */
+#define SAM3S8 ( \
+    part_is_defined( SAM3S8B ) || \
+    part_is_defined( SAM3S8C ) )
+
+#define SAM3SD8 ( \
+    part_is_defined( SAM3SD8B ) || \
+    part_is_defined( SAM3SD8C ) )
+
+/* Entire SAM3SD8 series */
+#define SAM3SD8_SERIES (SAM3S8 || SAM3SD8)
+
+/* SAM3U series */
+#define SAM3U1 ( \
+    part_is_defined( SAM3U1C ) || \
+    part_is_defined( SAM3U1E ) )
+
+#define SAM3U2 ( \
+    part_is_defined( SAM3U2C ) || \
+    part_is_defined( SAM3U2E ) )
+
+#define SAM3U4 ( \
+    part_is_defined( SAM3U4C ) || \
+    part_is_defined( SAM3U4E ) )
+
+/* Entire SAM3U series */
+#define SAM3U_SERIES (SAM3U1 || SAM3U2 || SAM3U4)
+
+/* SAM3XA series */
+#define SAM3X4 ( \
+    part_is_defined( SAM3X4C ) || \
+    part_is_defined( SAM3X4E ) )
+
+#define SAM3X8 ( \
+    part_is_defined( SAM3X8C ) || \
+    part_is_defined( SAM3X8E ) || \
+    part_is_defined( SAM3X8H ) )
+
+#define SAM3A4 ( \
+    part_is_defined( SAM3A4C ) )
+
+#define SAM3A8 ( \
+    part_is_defined( SAM3A8C ) )
+
+/* Entire SAM3XA series */
+#define SAM3XA_SERIES ( SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAM4 family
+ * ----------------------------------------------------------------------------
+ */
+
+
+/* Entire SAM3 Family */
+#define SAM3_SERIES ( SAM3N_SERIES || SAM3S_SERIES || SAM3SD8_SERIES || SAM3U_SERIES || SAM3XA_SERIES )
+
+/* SAM4S series */
+#define SAM4S8 ( \
+    part_is_defined( SAM4S8B ) || \
+    part_is_defined( SAM4S8C ) )
+
+#define SAM4S16 ( \
+    part_is_defined( SAM4S16B ) || \
+    part_is_defined( SAM4S16C ) )
+
+/* Entire SAM4S series */
+#define SAM4S_SERIES ( SAM4S8 || SAM4S16)
+
+/* Entire SAM4 Family */
+#define SAM4_SERIES ( SAM4S_SERIES )
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAM9 family
+ * ----------------------------------------------------------------------------
+ */
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAM7 family
+ * ----------------------------------------------------------------------------
+ */
+
+
+
+/*
+ * ----------------------------------------------------------------------------
+ * Whole SAM product line
+ * ----------------------------------------------------------------------------
+ */
+#define SAM ( SAM3_SERIES || SAM4_SERIES )
+
+/*
+ * ----------------------------------------------------------------------------
+ * Header inclusion
+ * ----------------------------------------------------------------------------
+ */
+
+#if SAM3_SERIES
+#include "sam3.h"
+#endif /* SAM3 */
+
+#if SAM4_SERIES
+#include "sam4.h"
+#endif /* SAM4 */
+
+#endif /* _SAM_INCLUDED_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3.h
new file mode 100644
index 0000000..071606b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3.h
@@ -0,0 +1,64 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3_INCLUDED_
+#define _SAM3_INCLUDED_
+
+#if (defined __SAM3S8A__) || (defined __SAM3S8B__) || (defined __SAM3S8C__) ||   /* SAM3S8 */ \
+    (defined __SAM3SD8A__) || (defined __SAM3SD8B__) || (defined __SAM3SD8C__) /* SAM3SD8 */
+  #include "sam3sd8/include/sam3sd8.h"
+
+#elif (defined __SAM3S4C__) || (defined __SAM3S4B__) || (defined __SAM3S4A__) ||   /* SAM3S4 */ \
+      (defined __SAM3S2C__) || (defined __SAM3S2B__) || (defined __SAM3S2A__) || /* SAM3S2 */ \
+      (defined __SAM3S1C__) || (defined __SAM3S1B__) || (defined __SAM3S1A__)    /* SAM3S1 */
+  #include "sam3s/include/sam3s.h"
+
+#elif (defined __SAM3U4C__) || (defined __SAM3U4E__) ||  /* SAM3U4 */ \
+      (defined __SAM3U2C__) || (defined __SAM3U2E__) || /* SAM3U2 */ \
+      (defined __SAM3U1C__) || (defined __SAM3U1E__)    /* SAM3U1 */
+  #include "sam3u/include/sam3u.h"
+
+#elif (defined __SAM3N4C__) || (defined __SAM3N4B__) || (defined __SAM3N4A__) || /* SAM3N4 */ \
+      (defined __SAM3N2C__) || (defined __SAM3N2B__) || (defined __SAM3N2A__) || /* SAM3N2 */ \
+      (defined __SAM3N1C__) || (defined __SAM3N1B__) || (defined __SAM3N1A__) || /* SAM3N1 */ \
+      (defined __SAM3N0C__) || (defined __SAM3N0B__) || (defined __SAM3N0A__) || /* SAM3N0 */ \
+      (defined __SAM3N00B__) || (defined __SAM3N00A__) /* SAM3N00 */
+  #include "sam3n/include/sam3n.h"
+
+#elif (defined __SAM3A8C__) || (defined __SAM3A4C__) /* SAM3A */
+  #include "sam3xa/include/sam3xa.h"
+
+#elif (defined __SAM3X8C__) || (defined __SAM3X8E__) || (defined __SAM3X8H__) || /* SAM3X8 */ \
+      (defined __SAM3X4C__) || (defined __SAM3X4E__) /* SAM3X4 */
+  #include "sam3xa/include/sam3xa.h"
+#else
+  #error Device not supported.
+#endif
+
+#endif /* _SAM3_INCLUDED_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_adc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_adc.h
new file mode 100644
index 0000000..9721868
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_adc.h
@@ -0,0 +1,397 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_ADC_COMPONENT_
+#define _SAM3N_ADC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM3N_ADC Analog-to-digital Converter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Adc hardware registers */
+typedef struct {
+  WoReg ADC_CR;        /**< \brief (Adc Offset: 0x00) Control Register */
+  RwReg ADC_MR;        /**< \brief (Adc Offset: 0x04) Mode Register */
+  RwReg ADC_SEQR1;     /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
+  RwReg ADC_SEQR2;     /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
+  WoReg ADC_CHER;      /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+  WoReg ADC_CHDR;      /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+  RoReg ADC_CHSR;      /**< \brief (Adc Offset: 0x18) Channel Status Register */
+  RoReg Reserved1[1];
+  RoReg ADC_LCDR;      /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+  WoReg ADC_IER;       /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC_IDR;       /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC_IMR;       /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC_ISR;       /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[2];
+  RoReg ADC_OVER;      /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
+  RwReg ADC_EMR;       /**< \brief (Adc Offset: 0x40) Extended Mode Register */
+  RwReg ADC_CWR;       /**< \brief (Adc Offset: 0x44) Compare Window Register */
+  RoReg Reserved3[2];
+  RoReg ADC_CDR[16];   /**< \brief (Adc Offset: 0x50) Channel Data Register */
+  RoReg Reserved4[21];
+  RwReg ADC_WPMR;      /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ADC_WPSR;      /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved5[5];
+  RwReg ADC_RPR;       /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+  RwReg ADC_RCR;       /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+  RoReg Reserved6[2];
+  RwReg ADC_RNPR;      /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC_RNCR;      /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+  RoReg Reserved7[2];
+  WoReg ADC_PTCR;      /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+  RoReg ADC_PTSR;      /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define   ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define   ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */
+#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */
+#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
+#define   ADC_MR_LOWRES_BITS_10 (0x0u << 4) /**< \brief (ADC_MR) 10-bit resolution */
+#define   ADC_MR_LOWRES_BITS_8 (0x1u << 4) /**< \brief (ADC_MR) 8-bit resolution */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define   ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
+#define   ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
+#define   ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
+#define   ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */
+#define   ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */
+#define   ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define   ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */
+#define ADC_MR_TRACKTIM_Pos 24
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
+#define   ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */
+#define   ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
+#define ADC_SEQR1_USCH1_Pos 0
+#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
+#define ADC_SEQR1_USCH2_Pos 4
+#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
+#define ADC_SEQR1_USCH3_Pos 8
+#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
+#define ADC_SEQR1_USCH4_Pos 12
+#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
+#define ADC_SEQR1_USCH5_Pos 16
+#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
+#define ADC_SEQR1_USCH6_Pos 20
+#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
+#define ADC_SEQR1_USCH7_Pos 24
+#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
+#define ADC_SEQR1_USCH8_Pos 28
+#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
+#define ADC_SEQR2_USCH9_Pos 0
+#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
+#define ADC_SEQR2_USCH10_Pos 4
+#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
+#define ADC_SEQR2_USCH11_Pos 8
+#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
+#define ADC_SEQR2_USCH12_Pos 12
+#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
+#define ADC_SEQR2_USCH13_Pos 16
+#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
+#define ADC_SEQR2_USCH14_Pos 20
+#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
+#define ADC_SEQR2_USCH15_Pos 24
+#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
+#define ADC_SEQR2_USCH16_Pos 28
+#define ADC_SEQR2_USCH16_Msk (0xfu << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+#define ADC_LCDR_CHNB_Pos 12
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
+#define ADC_EMR_CMPMODE_Pos 0
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
+#define   ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define   ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
+#define   ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
+#define ADC_EMR_CMPSEL_Pos 4
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
+#define ADC_CWR_LOWTHRES_Pos 0
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
+#define ADC_CWR_HIGHTHRES_Pos 16
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
+/* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[16]) Converted Data */
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
+#define ADC_WPMR_WPKEY_Pos 8
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
+#define ADC_WPSR_WPVSRC_Pos 8
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_ADC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_chipid.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_chipid.h
new file mode 100644
index 0000000..45790db
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_chipid.h
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_CHIPID_COMPONENT_
+#define _SAM3N_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM3N_CHIPID Chip Identifier */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Chipid hardware registers */
+typedef struct {
+  RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+  RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define   CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define   CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define   CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define   CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define   CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define   CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define   CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define   CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define   CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define   CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define   CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define   CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
+#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAM3N_CHIPID_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_dacc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_dacc.h
new file mode 100644
index 0000000..4977723
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_dacc.h
@@ -0,0 +1,137 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_DACC_COMPONENT_
+#define _SAM3N_DACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_DACC Digital-to-Analog Converter Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Dacc hardware registers */
+typedef struct {
+  WoReg DACC_CR;       /**< \brief (Dacc Offset: 0x00) Control Register */
+  RwReg DACC_MR;       /**< \brief (Dacc Offset: 0x04) Mode Register */
+  WoReg DACC_CDR;      /**< \brief (Dacc Offset: 0x08) Conversion Data Register */
+  WoReg DACC_IER;      /**< \brief (Dacc Offset: 0x0C) Interrupt Enable Register */
+  WoReg DACC_IDR;      /**< \brief (Dacc Offset: 0x10) Interrupt Disable Register */
+  RoReg DACC_IMR;      /**< \brief (Dacc Offset: 0x14) Interrupt Mask Register */
+  RoReg DACC_ISR;      /**< \brief (Dacc Offset: 0x18) Interrupt Status Register */
+  RoReg Reserved1[50];
+  RwReg DACC_WPMR;     /**< \brief (Dacc Offset: 0xE4) Write Protect Mode Register */
+  RoReg DACC_WPSR;     /**< \brief (Dacc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved2[7];
+  RwReg DACC_TPR;      /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
+  RwReg DACC_TCR;      /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
+  RoReg Reserved3[2];
+  RwReg DACC_TNPR;     /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg DACC_TNCR;     /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg DACC_PTCR;     /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
+  RoReg DACC_PTSR;     /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
+} Dacc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
+#define DACC_MR_TRGSEL_Pos 1
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
+#define   DACC_MR_TRGSEL_TRGSEL0 (0x0u << 1) /**< \brief (DACC_MR) External trigger */
+#define   DACC_MR_TRGSEL_TRGSEL1 (0x1u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 0 */
+#define   DACC_MR_TRGSEL_TRGSEL2 (0x2u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 1 */
+#define   DACC_MR_TRGSEL_TRGSEL3 (0x3u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 2 */
+#define DACC_MR_DACEN (0x1u << 4) /**< \brief (DACC_MR) DAC enable */
+#define DACC_MR_WORD (0x1u << 5) /**< \brief (DACC_MR) Word Transfer */
+#define DACC_MR_STARTUP_Pos 8
+#define DACC_MR_STARTUP_Msk (0xffu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
+#define DACC_MR_STARTUP(value) ((DACC_MR_STARTUP_Msk & ((value) << DACC_MR_STARTUP_Pos)))
+#define DACC_MR_CLKDIV_Pos 16
+#define DACC_MR_CLKDIV_Msk (0xffffu << DACC_MR_CLKDIV_Pos) /**< \brief (DACC_MR) DAC Clock Divider for Internal Trigger */
+#define DACC_MR_CLKDIV(value) ((DACC_MR_CLKDIV_Msk & ((value) << DACC_MR_CLKDIV_Pos)))
+/* -------- DACC_CDR : (DACC Offset: 0x08) Conversion Data Register -------- */
+#define DACC_CDR_DATA_Pos 0
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
+/* -------- DACC_IER : (DACC Offset: 0x0C) Interrupt Enable Register -------- */
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmission Ready Interrupt Enable */
+#define DACC_IER_ENDTX (0x1u << 1) /**< \brief (DACC_IER) End of PDC Interrupt Enable */
+#define DACC_IER_TXBUFE (0x1u << 2) /**< \brief (DACC_IER) Buffer Empty Interrupt Enable */
+/* -------- DACC_IDR : (DACC Offset: 0x10) Interrupt Disable Register -------- */
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmission Ready Interrupt Disable */
+#define DACC_IDR_ENDTX (0x1u << 1) /**< \brief (DACC_IDR) End of PDC Interrupt Disable */
+#define DACC_IDR_TXBUFE (0x1u << 2) /**< \brief (DACC_IDR) Buffer Empty Interrupt Disable */
+/* -------- DACC_IMR : (DACC Offset: 0x14) Interrupt Mask Register -------- */
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmission Ready Interrupt Mask */
+#define DACC_IMR_ENDTX (0x1u << 1) /**< \brief (DACC_IMR) End of PDC Interrupt Mask */
+#define DACC_IMR_TXBUFE (0x1u << 2) /**< \brief (DACC_IMR) Buffer Empty Interrupt Mask */
+/* -------- DACC_ISR : (DACC Offset: 0x18) Interrupt Status Register -------- */
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmission Ready Interrupt Flag */
+#define DACC_ISR_ENDTX (0x1u << 1) /**< \brief (DACC_ISR) End of PDC Interrupt Flag */
+#define DACC_ISR_TXBUFE (0x1u << 2) /**< \brief (DACC_ISR) Buffer Empty Interrupt Flag */
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode Register -------- */
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
+#define DACC_WPMR_WPKEY_Pos 8
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status Register -------- */
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
+#define DACC_WPSR_WPROTADDR_Pos 8
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
+#define DACC_TPR_TXPTR_Pos 0
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
+#define DACC_TCR_TXCTR_Pos 0
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define DACC_TNPR_TXNPTR_Pos 0
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define DACC_TNCR_TXNCTR_Pos 0
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_DACC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_efc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_efc.h
new file mode 100644
index 0000000..5365bb1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_efc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_EFC_COMPONENT_
+#define _SAM3N_EFC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_EFC Embedded Flash Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Efc hardware registers */
+typedef struct {
+  RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+  WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+  RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+  RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+
+#endif /* _SAM3N_EFC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_gpbr.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_gpbr.h
new file mode 100644
index 0000000..cc45aac
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_gpbr.h
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_GPBR_COMPONENT_
+#define _SAM3N_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM3N_GPBR General Purpose Backup Register */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Gpbr hardware registers */
+typedef struct {
+  RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3N_GPBR_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_matrix.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_matrix.h
new file mode 100644
index 0000000..ca9e63a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_matrix.h
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_MATRIX_COMPONENT_
+#define _SAM3N_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM3N_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Matrix hardware registers */
+typedef struct {
+  RwReg MATRIX_MCFG[3]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+  RoReg Reserved1[13];
+  RwReg MATRIX_SCFG[4]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+  RoReg Reserved2[12];
+  RwReg MATRIX_PRAS0;   /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+  RoReg Reserved3[1];
+  RwReg MATRIX_PRAS1;   /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+  RoReg Reserved4[1];
+  RwReg MATRIX_PRAS2;   /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+  RoReg Reserved5[1];
+  RwReg MATRIX_PRAS3;   /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+  RoReg Reserved6[1];
+  RoReg Reserved7[29];
+  RwReg CCFG_SYSIO;     /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */
+  RoReg Reserved8[51];
+  RwReg MATRIX_WPMR;    /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+  RoReg MATRIX_WPSR;    /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- MATRIX_MCFG[3] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[3]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[4] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[4]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[4]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[4]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[4]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */
+#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */
+#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */
+#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */
+#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3N_MATRIX_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_pdc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_pdc.h
new file mode 100644
index 0000000..d0cfa47
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_pdc.h
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PDC_COMPONENT_
+#define _SAM3N_PDC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_PDC Peripheral DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pdc hardware registers */
+typedef struct {
+  RwReg PERIPH_RPR;  /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
+  RwReg PERIPH_RCR;  /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
+  RwReg PERIPH_TPR;  /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
+  RwReg PERIPH_TCR;  /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
+  RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+  RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+  RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+  RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+  WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+  RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_PDC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_pio.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_pio.h
new file mode 100644
index 0000000..3379d92
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_pio.h
@@ -0,0 +1,1572 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PIO_COMPONENT_
+#define _SAM3N_PIO_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pio hardware registers */
+typedef struct {
+  WoReg PIO_PER;       /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+  WoReg PIO_PDR;       /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+  RoReg PIO_PSR;       /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+  RoReg Reserved1[1];
+  WoReg PIO_OER;       /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+  WoReg PIO_ODR;       /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+  RoReg PIO_OSR;       /**< \brief (Pio Offset: 0x0018) Output Status Register */
+  RoReg Reserved2[1];
+  WoReg PIO_IFER;      /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+  WoReg PIO_IFDR;      /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+  RoReg PIO_IFSR;      /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+  RoReg Reserved3[1];
+  WoReg PIO_SODR;      /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+  WoReg PIO_CODR;      /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+  RwReg PIO_ODSR;      /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+  RoReg PIO_PDSR;      /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+  WoReg PIO_IER;       /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+  WoReg PIO_IDR;       /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+  RoReg PIO_IMR;       /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+  RoReg PIO_ISR;       /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+  WoReg PIO_MDER;      /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+  WoReg PIO_MDDR;      /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+  RoReg PIO_MDSR;      /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+  RoReg Reserved4[1];
+  WoReg PIO_PUDR;      /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+  WoReg PIO_PUER;      /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+  RoReg PIO_PUSR;      /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+  RoReg Reserved5[1];
+  RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
+  RoReg Reserved6[2];
+  WoReg PIO_IFSCDR;    /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */
+  WoReg PIO_IFSCER;    /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */
+  RoReg PIO_IFSCSR;    /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */
+  RwReg PIO_SCDR;      /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+  WoReg PIO_PPDDR;     /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
+  WoReg PIO_PPDER;     /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
+  RoReg PIO_PPDSR;     /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
+  RoReg Reserved7[1];
+  WoReg PIO_OWER;      /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+  WoReg PIO_OWDR;      /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+  RoReg PIO_OWSR;      /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+  RoReg Reserved8[1];
+  WoReg PIO_AIMER;     /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+  WoReg PIO_AIMDR;     /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
+  RoReg PIO_AIMMR;     /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+  RoReg Reserved9[1];
+  WoReg PIO_ESR;       /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+  WoReg PIO_LSR;       /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+  RoReg PIO_ELSR;      /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+  RoReg Reserved10[1];
+  WoReg PIO_FELLSR;    /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
+  WoReg PIO_REHLSR;    /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
+  RoReg PIO_FRLHSR;    /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+  RoReg Reserved11[1];
+  RoReg PIO_LOCKSR;    /**< \brief (Pio Offset: 0x00E0) Lock Status */
+  RwReg PIO_WPMR;      /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PIO_WPSR;      /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved12[5];
+  RwReg PIO_SCHMITT;   /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
+} Pio;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
+/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
+#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
+#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
+#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
+#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR)  */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
+#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
+#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */
+/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
+#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
+/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
+#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT)  */
+
+/*@}*/
+
+
+#endif /* _SAM3N_PIO_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_pmc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_pmc.h
new file mode 100644
index 0000000..c6ac5d9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_pmc.h
@@ -0,0 +1,323 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PMC_COMPONENT_
+#define _SAM3N_PMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_PMC Power Management Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pmc hardware registers */
+typedef struct {
+  WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+  WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+  RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+  RoReg Reserved1[1];
+  WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+  WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+  RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+  RoReg Reserved2[1];
+  RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+  RoReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+  RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+  RoReg Reserved3[1];
+  RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+  RoReg Reserved4[3];
+  RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+  RoReg Reserved5[5];
+  WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+  WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+  RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
+  RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+  RwReg PMC_FSMR;      /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+  RwReg PMC_FSPR;      /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+  WoReg PMC_FOCR;      /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+  RoReg Reserved6[26];
+  RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+} Pmc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define   PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define   PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define   PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define   PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define   PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define   PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define   PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define   PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3N_PMC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_pwm.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_pwm.h
new file mode 100644
index 0000000..0851a78
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_pwm.h
@@ -0,0 +1,172 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PWM_COMPONENT_
+#define _SAM3N_PWM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+  RwReg      PWM_CMR;        /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+  RwReg      PWM_CDTY;       /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+  RwReg      PWM_CPRD;       /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Period Register */
+  RwReg      PWM_CCNT;       /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Counter Register */
+  RwReg      PWM_CUPD;       /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Update Register */
+  RoReg      Reserved1[3];
+} PwmCh_num;
+/** \brief Pwm hardware registers */
+#define PWMCH_NUM_NUMBER 4
+typedef struct {
+  RwReg      PWM_MR;         /**< \brief (Pwm Offset: 0x00) PWM Mode Register */
+  WoReg      PWM_ENA;        /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+  WoReg      PWM_DIS;        /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+  RoReg      PWM_SR;         /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+  WoReg      PWM_IER;        /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register */
+  WoReg      PWM_IDR;        /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register */
+  RoReg      PWM_IMR;        /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register */
+  RoReg      PWM_ISR;        /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register */
+  RoReg      Reserved1[120];
+  PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
+} Pwm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PWM_MR : (PWM Offset: 0x00) PWM Mode Register -------- */
+#define PWM_MR_DIVA_Pos 0
+#define PWM_MR_DIVA_Msk (0xffu << PWM_MR_DIVA_Pos) /**< \brief (PWM_MR) CLKA, CLKB Divide Factor */
+#define   PWM_MR_DIVA_CLK_OFF (0x0u << 0) /**< \brief (PWM_MR) CLKA, CLKB clock is turned off */
+#define   PWM_MR_DIVA_CLK_DIV1 (0x1u << 0) /**< \brief (PWM_MR) CLKA, CLKB clock is clock selected by PREA, PREB */
+#define PWM_MR_PREA_Pos 8
+#define PWM_MR_PREA_Msk (0xfu << PWM_MR_PREA_Pos) /**< \brief (PWM_MR)  */
+#define   PWM_MR_PREA_MCK (0x0u << 8) /**< \brief (PWM_MR) Master Clock */
+#define   PWM_MR_PREA_MCKDIV2 (0x1u << 8) /**< \brief (PWM_MR) Master Clock divided by 2 */
+#define   PWM_MR_PREA_MCKDIV4 (0x2u << 8) /**< \brief (PWM_MR) Master Clock divided by 4 */
+#define   PWM_MR_PREA_MCKDIV8 (0x3u << 8) /**< \brief (PWM_MR) Master Clock divided by 8 */
+#define   PWM_MR_PREA_MCKDIV16 (0x4u << 8) /**< \brief (PWM_MR) Master Clock divided by 16 */
+#define   PWM_MR_PREA_MCKDIV32 (0x5u << 8) /**< \brief (PWM_MR) Master Clock divided by 32 */
+#define   PWM_MR_PREA_MCKDIV64 (0x6u << 8) /**< \brief (PWM_MR) Master Clock divided by 64 */
+#define   PWM_MR_PREA_MCKDIV128 (0x7u << 8) /**< \brief (PWM_MR) Master Clock divided by 128 */
+#define   PWM_MR_PREA_MCKDIV256 (0x8u << 8) /**< \brief (PWM_MR) Master Clock divided by 256 */
+#define   PWM_MR_PREA_MCKDIV512 (0x9u << 8) /**< \brief (PWM_MR) Master Clock divided by 512 */
+#define   PWM_MR_PREA_MCKDIV1024 (0xAu << 8) /**< \brief (PWM_MR) Master Clock divided by 1024 */
+#define PWM_MR_DIVB_Pos 16
+#define PWM_MR_DIVB_Msk (0xffu << PWM_MR_DIVB_Pos) /**< \brief (PWM_MR) CLKA, CLKB Divide Factor */
+#define   PWM_MR_DIVB_CLK_OFF (0x0u << 16) /**< \brief (PWM_MR) CLKA, CLKB clock is turned off */
+#define   PWM_MR_DIVB_CLK_DIV1 (0x1u << 16) /**< \brief (PWM_MR) CLKA, CLKB clock is clock selected by PREA, PREB */
+#define PWM_MR_PREB_Pos 24
+#define PWM_MR_PREB_Msk (0xfu << PWM_MR_PREB_Pos) /**< \brief (PWM_MR)  */
+#define   PWM_MR_PREB_MCK (0x0u << 24) /**< \brief (PWM_MR) Master Clock */
+#define   PWM_MR_PREB_MCKDIV2 (0x1u << 24) /**< \brief (PWM_MR) Master Clock divided by 2 */
+#define   PWM_MR_PREB_MCKDIV4 (0x2u << 24) /**< \brief (PWM_MR) Master Clock divided by 4 */
+#define   PWM_MR_PREB_MCKDIV8 (0x3u << 24) /**< \brief (PWM_MR) Master Clock divided by 8 */
+#define   PWM_MR_PREB_MCKDIV16 (0x4u << 24) /**< \brief (PWM_MR) Master Clock divided by 16 */
+#define   PWM_MR_PREB_MCKDIV32 (0x5u << 24) /**< \brief (PWM_MR) Master Clock divided by 32 */
+#define   PWM_MR_PREB_MCKDIV64 (0x6u << 24) /**< \brief (PWM_MR) Master Clock divided by 64 */
+#define   PWM_MR_PREB_MCKDIV128 (0x7u << 24) /**< \brief (PWM_MR) Master Clock divided by 128 */
+#define   PWM_MR_PREB_MCKDIV256 (0x8u << 24) /**< \brief (PWM_MR) Master Clock divided by 256 */
+#define   PWM_MR_PREB_MCKDIV512 (0x9u << 24) /**< \brief (PWM_MR) Master Clock divided by 512 */
+#define   PWM_MR_PREB_MCKDIV1024 (0xAu << 24) /**< \brief (PWM_MR) Master Clock divided by 1024 */
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER : (PWM Offset: 0x10) PWM Interrupt Enable Register -------- */
+#define PWM_IER_CHID0 (0x1u << 0) /**< \brief (PWM_IER) Channel ID. */
+#define PWM_IER_CHID1 (0x1u << 1) /**< \brief (PWM_IER) Channel ID. */
+#define PWM_IER_CHID2 (0x1u << 2) /**< \brief (PWM_IER) Channel ID. */
+#define PWM_IER_CHID3 (0x1u << 3) /**< \brief (PWM_IER) Channel ID. */
+/* -------- PWM_IDR : (PWM Offset: 0x14) PWM Interrupt Disable Register -------- */
+#define PWM_IDR_CHID0 (0x1u << 0) /**< \brief (PWM_IDR) Channel ID. */
+#define PWM_IDR_CHID1 (0x1u << 1) /**< \brief (PWM_IDR) Channel ID. */
+#define PWM_IDR_CHID2 (0x1u << 2) /**< \brief (PWM_IDR) Channel ID. */
+#define PWM_IDR_CHID3 (0x1u << 3) /**< \brief (PWM_IDR) Channel ID. */
+/* -------- PWM_IMR : (PWM Offset: 0x18) PWM Interrupt Mask Register -------- */
+#define PWM_IMR_CHID0 (0x1u << 0) /**< \brief (PWM_IMR) Channel ID. */
+#define PWM_IMR_CHID1 (0x1u << 1) /**< \brief (PWM_IMR) Channel ID. */
+#define PWM_IMR_CHID2 (0x1u << 2) /**< \brief (PWM_IMR) Channel ID. */
+#define PWM_IMR_CHID3 (0x1u << 3) /**< \brief (PWM_IMR) Channel ID. */
+/* -------- PWM_ISR : (PWM Offset: 0x1C) PWM Interrupt Status Register -------- */
+#define PWM_ISR_CHID0 (0x1u << 0) /**< \brief (PWM_ISR) Channel ID */
+#define PWM_ISR_CHID1 (0x1u << 1) /**< \brief (PWM_ISR) Channel ID */
+#define PWM_ISR_CHID2 (0x1u << 2) /**< \brief (PWM_ISR) Channel ID */
+#define PWM_ISR_CHID3 (0x1u << 3) /**< \brief (PWM_ISR) Channel ID */
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master Clock */
+#define   PWM_CMR_CPRE_MCKDIV2 (0x1u << 0) /**< \brief (PWM_CMR) Master Clock divided by 2 */
+#define   PWM_CMR_CPRE_MCKDIV4 (0x2u << 0) /**< \brief (PWM_CMR) Master Clock divided by 4 */
+#define   PWM_CMR_CPRE_MCKDIV8 (0x3u << 0) /**< \brief (PWM_CMR) Master Clock divided by 8 */
+#define   PWM_CMR_CPRE_MCKDIV16 (0x4u << 0) /**< \brief (PWM_CMR) Master Clock divided by 16 */
+#define   PWM_CMR_CPRE_MCKDIV32 (0x5u << 0) /**< \brief (PWM_CMR) Master Clock divided by 32 */
+#define   PWM_CMR_CPRE_MCKDIV64 (0x6u << 0) /**< \brief (PWM_CMR) Master Clock divided by 64 */
+#define   PWM_CMR_CPRE_MCKDIV128 (0x7u << 0) /**< \brief (PWM_CMR) Master Clock divided by 128 */
+#define   PWM_CMR_CPRE_MCKDIV256 (0x8u << 0) /**< \brief (PWM_CMR) Master Clock divided by 256 */
+#define   PWM_CMR_CPRE_MCKDIV512 (0x9u << 0) /**< \brief (PWM_CMR) Master Clock divided by 512 */
+#define   PWM_CMR_CPRE_MCKDIV1024 (0xAu << 0) /**< \brief (PWM_CMR) Master Clock divided by 1024 */
+#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CPD (0x1u << 10) /**< \brief (PWM_CMR) Channel Update Period */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_CUPD : (PWM Offset: N/A) PWM Channel Update Register -------- */
+#define PWM_CUPD_CUPD_Pos 0
+#define PWM_CUPD_CUPD_Msk (0xffffffffu << PWM_CUPD_CUPD_Pos) /**< \brief (PWM_CUPD)  */
+#define PWM_CUPD_CUPD(value) ((PWM_CUPD_CUPD_Msk & ((value) << PWM_CUPD_CUPD_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3N_PWM_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_rstc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_rstc.h
new file mode 100644
index 0000000..79bd375
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_rstc.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_RSTC_COMPONENT_
+#define _SAM3N_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_RSTC Reset Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rstc hardware registers */
+typedef struct {
+  WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+  RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+  RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3N_RSTC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_rtc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_rtc.h
new file mode 100644
index 0000000..cd696bd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_rtc.h
@@ -0,0 +1,168 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_RTC_COMPONENT_
+#define _SAM3N_RTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM3N_RTC Real-time Clock */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtc hardware registers */
+typedef struct {
+  RwReg RTC_CR;        /**< \brief (Rtc Offset: 0x00) Control Register */
+  RwReg RTC_MR;        /**< \brief (Rtc Offset: 0x04) Mode Register */
+  RwReg RTC_TIMR;      /**< \brief (Rtc Offset: 0x08) Time Register */
+  RwReg RTC_CALR;      /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+  RwReg RTC_TIMALR;    /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+  RwReg RTC_CALALR;    /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+  RoReg RTC_SR;        /**< \brief (Rtc Offset: 0x18) Status Register */
+  WoReg RTC_SCCR;      /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+  WoReg RTC_IER;       /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+  WoReg RTC_IDR;       /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+  RoReg RTC_IMR;       /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+  RoReg RTC_VER;       /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+  RoReg Reserved1[45];
+  RwReg RTC_WPMR;      /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */
+#define RTC_WPMR_WPKEY_Pos 8
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR)  */
+#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3N_RTC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_rtt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_rtt.h
new file mode 100644
index 0000000..1051b4d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_rtt.h
@@ -0,0 +1,69 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_RTT_COMPONENT_
+#define _SAM3N_RTT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3N_RTT Real-time Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtt hardware registers */
+typedef struct {
+  RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+  RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+  RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+  RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+
+#endif /* _SAM3N_RTT_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_spi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_spi.h
new file mode 100644
index 0000000..f983bdf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_spi.h
@@ -0,0 +1,226 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_SPI_COMPONENT_
+#define _SAM3N_SPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3N_SPI Serial Peripheral Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Spi hardware registers */
+typedef struct {
+  WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
+  RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
+  RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
+  WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+  RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
+  WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+  WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+  RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+  RoReg Reserved1[4];
+  RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
+  RoReg Reserved2[41];
+  RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+  RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved3[5];
+  RwReg SPI_RPR;       /**< \brief (Spi Offset: 0x100) Receive Pointer Register */
+  RwReg SPI_RCR;       /**< \brief (Spi Offset: 0x104) Receive Counter Register */
+  RwReg SPI_TPR;       /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */
+  RwReg SPI_TCR;       /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */
+  RwReg SPI_RNPR;      /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */
+  RwReg SPI_RNCR;      /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */
+  RwReg SPI_TNPR;      /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg SPI_TNCR;      /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg SPI_PTCR;      /**< \brief (Spi Offset: 0x120) Transfer Control Register */
+  RoReg SPI_PTSR;      /**< \brief (Spi Offset: 0x124) Transfer Status Register */
+} Spi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */
+#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */
+#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */
+#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */
+#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */
+#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */
+#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */
+#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */
+#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */
+#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */
+#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */
+#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */
+#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */
+#define SPI_WPMR_WPKEY_Pos 8
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */
+#define SPI_WPSR_WPVSRC_Pos 8
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */
+/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */
+#define SPI_RPR_RXPTR_Pos 0
+#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */
+#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))
+/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */
+#define SPI_RCR_RXCTR_Pos 0
+#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */
+#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))
+/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */
+#define SPI_TPR_TXPTR_Pos 0
+#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */
+#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))
+/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */
+#define SPI_TCR_TXCTR_Pos 0
+#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */
+#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))
+/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */
+#define SPI_RNPR_RXNPTR_Pos 0
+#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */
+#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))
+/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */
+#define SPI_RNCR_RXNCTR_Pos 0
+#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */
+#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))
+/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define SPI_TNPR_TXNPTR_Pos 0
+#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */
+#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))
+/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define SPI_TNCR_TXNCTR_Pos 0
+#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */
+#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))
+/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */
+#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */
+#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */
+#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */
+#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */
+/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */
+#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */
+#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_SPI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_supc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_supc.h
new file mode 100644
index 0000000..74256f4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_supc.h
@@ -0,0 +1,297 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_SUPC_COMPONENT_
+#define _SAM3N_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3N_SUPC Supply Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Supc hardware registers */
+typedef struct {
+  WoReg SUPC_CR;   /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+  RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+  RwReg SUPC_MR;   /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+  RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+  RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+  RoReg SUPC_SR;   /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */
+#define   SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */
+#define   SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define   SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define   SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define   SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define   SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define   SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define   SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define   SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define   SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define   SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define   SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define   SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define   SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define   SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define   SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define   SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define   SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
+#define   SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
+#define   SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
+#define   SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
+#define   SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
+#define   SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
+#define   SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
+#define   SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
+#define   SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
+#define   SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
+#define   SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
+#define   SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
+#define   SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
+#define   SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
+#define   SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
+#define   SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
+#define   SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define   SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define   SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define   SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define   SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define   SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define   SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define   SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */
+#define   SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define   SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+
+#endif /* _SAM3N_SUPC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_tc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_tc.h
new file mode 100644
index 0000000..1616bdb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_tc.h
@@ -0,0 +1,299 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_TC_COMPONENT_
+#define _SAM3N_TC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM3N_TC Timer Counter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief TcChannel hardware registers */
+typedef struct {
+  RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+  RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+  RwReg      TC_SMMR;       /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
+  RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
+  RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
+  RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
+  RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
+  RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+  RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+  RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+  RoReg      Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+  TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+  WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
+  RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+  WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+  WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+  RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+  RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+  RoReg      Reserved1[3];
+  RwReg      TC_WPMR;       /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
+#define TC_WPMR_WPKEY_Pos 8
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3N_TC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_twi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_twi.h
new file mode 100644
index 0000000..90ee816
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_twi.h
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_TWI_COMPONENT_
+#define _SAM3N_TWI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3N_TWI Two-wire Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Twi hardware registers */
+typedef struct {
+  WoReg TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
+  RwReg TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
+  RwReg TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+  RwReg TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+  RwReg TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+  RoReg Reserved1[3];
+  RoReg TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
+  WoReg TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+  WoReg TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+  RoReg TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+  RoReg TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+  WoReg TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+  RoReg Reserved2[50];
+  RwReg TWI_RPR;       /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+  RwReg TWI_RCR;       /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+  RwReg TWI_TPR;       /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+  RwReg TWI_TCR;       /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+  RwReg TWI_RNPR;      /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+  RwReg TWI_RNCR;      /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+  RwReg TWI_TNPR;      /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg TWI_TNCR;      /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg TWI_PTCR;      /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+  RoReg TWI_PTSR;      /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_TWI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_uart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_uart.h
new file mode 100644
index 0000000..5433a5e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_uart.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_UART_COMPONENT_
+#define _SAM3N_UART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3N_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Uart hardware registers */
+typedef struct {
+  WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
+  RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
+  WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+  WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+  RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+  RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
+  RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+  WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+  RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+  RoReg Reserved1[55];
+  RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+  RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+  RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+  RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+  RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+  RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+  RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+  RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_UART_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_usart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_usart.h
new file mode 100644
index 0000000..1463431
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_usart.h
@@ -0,0 +1,305 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_USART_COMPONENT_
+#define _SAM3N_USART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3N_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Usart hardware registers */
+typedef struct {
+  WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
+  RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
+  WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+  WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+  RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+  RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+  RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+  WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+  RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+  RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+  RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+  RoReg Reserved1[5];
+  RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+  RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+  RoReg Reserved2[1];
+  RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+  RoReg Reserved3[37];
+  RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+  RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[5];
+  RwReg US_RPR;        /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+  RwReg US_RCR;        /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+  RwReg US_TPR;        /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+  RwReg US_TCR;        /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+  RwReg US_RNPR;       /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+  RwReg US_RNCR;       /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+  RwReg US_TNPR;       /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg US_TNCR;       /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg US_PTCR;       /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+  RoReg US_PTSR;       /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
+#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3N_USART_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_wdt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_wdt.h
new file mode 100644
index 0000000..8707b82
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/component/component_wdt.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_WDT_COMPONENT_
+#define _SAM3N_WDT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3N_WDT Watchdog Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Wdt hardware registers */
+typedef struct {
+  WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+  RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+  RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAM3N_WDT_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_adc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_adc.h
new file mode 100644
index 0000000..0f013ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_adc.h
@@ -0,0 +1,86 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_ADC_INSTANCE_
+#define _SAM3N_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CR               (0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR               (0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1            (0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2            (0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER             (0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR             (0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR             (0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR             (0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER              (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR              (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR              (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR              (0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER             (0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR              (0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR              (0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CDR              (0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_WPMR             (0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR             (0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR              (0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR              (0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR             (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR             (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR             (0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR             (0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#else
+#define REG_ADC_CR      (*(WoReg*)0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR      (*(RwReg*)0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1   (*(RwReg*)0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2   (*(RwReg*)0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER    (*(WoReg*)0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR    (*(WoReg*)0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR    (*(RoReg*)0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR    (*(RoReg*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER     (*(WoReg*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR     (*(WoReg*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR     (*(RoReg*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR     (*(RoReg*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER    (*(RoReg*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR     (*(RwReg*)0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR     (*(RwReg*)0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CDR     (*(RoReg*)0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_WPMR    (*(RwReg*)0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR    (*(RoReg*)0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR     (*(RwReg*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR     (*(RwReg*)0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR    (*(RwReg*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR    (*(RwReg*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR    (*(WoReg*)0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR    (*(RoReg*)0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_ADC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_chipid.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_chipid.h
new file mode 100644
index 0000000..00b2afa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_chipid.h
@@ -0,0 +1,42 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_CHIPID_INSTANCE_
+#define _SAM3N_CHIPID_INSTANCE_
+
+/* ========== Register definition for CHIPID peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CHIPID_CIDR          (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID          (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#else
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_CHIPID_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_dacc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_dacc.h
new file mode 100644
index 0000000..00e53ed
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_dacc.h
@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_DACC_INSTANCE_
+#define _SAM3N_DACC_INSTANCE_
+
+/* ========== Register definition for DACC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DACC_CR            (0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR            (0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CDR           (0x4003C008U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER           (0x4003C00CU) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR           (0x4003C010U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR           (0x4003C014U) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR           (0x4003C018U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_WPMR          (0x4003C0E4U) /**< \brief (DACC) Write Protect Mode Register */
+#define REG_DACC_WPSR          (0x4003C0E8U) /**< \brief (DACC) Write Protect Status Register */
+#define REG_DACC_TPR           (0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR           (0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_TNPR          (0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR          (0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR          (0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR          (0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#else
+#define REG_DACC_CR   (*(WoReg*)0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR   (*(RwReg*)0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CDR  (*(WoReg*)0x4003C008U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER  (*(WoReg*)0x4003C00CU) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR  (*(WoReg*)0x4003C010U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR  (*(RoReg*)0x4003C014U) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR  (*(RoReg*)0x4003C018U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_WPMR (*(RwReg*)0x4003C0E4U) /**< \brief (DACC) Write Protect Mode Register */
+#define REG_DACC_WPSR (*(RoReg*)0x4003C0E8U) /**< \brief (DACC) Write Protect Status Register */
+#define REG_DACC_TPR  (*(RwReg*)0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR  (*(RwReg*)0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_TNPR (*(RwReg*)0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR (*(RwReg*)0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR (*(WoReg*)0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR (*(RoReg*)0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_DACC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_efc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_efc.h
new file mode 100644
index 0000000..852c43c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_efc.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_EFC_INSTANCE_
+#define _SAM3N_EFC_INSTANCE_
+
+/* ========== Register definition for EFC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EFC_FMR           (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR           (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR           (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR           (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#else
+#define REG_EFC_FMR  (*(RwReg*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR  (*(WoReg*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR  (*(RoReg*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR  (*(RoReg*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_EFC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_gpbr.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_gpbr.h
new file mode 100644
index 0000000..deaf51d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_gpbr.h
@@ -0,0 +1,40 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_GPBR_INSTANCE_
+#define _SAM3N_GPBR_INSTANCE_
+
+/* ========== Register definition for GPBR peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GPBR_GPBR            (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#else
+#define REG_GPBR_GPBR   (*(RwReg*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_GPBR_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_matrix.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_matrix.h
new file mode 100644
index 0000000..4ede743
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_matrix.h
@@ -0,0 +1,56 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_MATRIX_INSTANCE_
+#define _SAM3N_MATRIX_INSTANCE_
+
+/* ========== Register definition for MATRIX peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MATRIX_MCFG             (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG             (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0            (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1            (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2            (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3            (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_CCFG_SYSIO              (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_MATRIX_WPMR             (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR             (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#else
+#define REG_MATRIX_MCFG    (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG    (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0   (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1   (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2   (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3   (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_CCFG_SYSIO     (*(RwReg*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_MATRIX_WPMR    (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR    (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_MATRIX_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_pioa.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_pioa.h
new file mode 100644
index 0000000..99c989a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_pioa.h
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PIOA_INSTANCE_
+#define _SAM3N_PIOA_INSTANCE_
+
+/* ========== Register definition for PIOA peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOA_PER                (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR                (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR                (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER                (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR                (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR                (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER               (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR               (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR               (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR               (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR               (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR               (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR               (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER                (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR                (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR                (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR                (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER               (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR               (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR               (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR               (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER               (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR               (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR             (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR             (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER             (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR             (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR               (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR              (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER              (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR              (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER               (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR               (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR               (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER              (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR              (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR              (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR                (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR                (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR               (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR             (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR             (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR             (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR             (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR               (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR               (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT            (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#else
+#define REG_PIOA_PER       (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR       (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR       (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER       (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR       (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR       (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER      (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR      (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR      (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR      (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR      (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR      (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR      (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER       (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR       (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR       (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR       (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER      (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR      (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR      (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR      (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER      (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR      (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR    (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR    (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER    (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR    (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR      (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR     (*(WoReg*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER     (*(WoReg*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR     (*(RoReg*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER      (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR      (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR      (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER     (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR     (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR     (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR       (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR       (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR      (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR    (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR    (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR    (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR    (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR      (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR      (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT   (*(RwReg*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_PIOA_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_piob.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_piob.h
new file mode 100644
index 0000000..576f72e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_piob.h
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PIOB_INSTANCE_
+#define _SAM3N_PIOB_INSTANCE_
+
+/* ========== Register definition for PIOB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOB_PER                (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR                (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR                (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER                (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR                (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR                (0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER               (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR               (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR               (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR               (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR               (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR               (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR               (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER                (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR                (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR                (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR                (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER               (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR               (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR               (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR               (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER               (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR               (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR             (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR             (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER             (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR             (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR               (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR              (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER              (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR              (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER               (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR               (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR               (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER              (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR              (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR              (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR                (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR                (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR               (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR             (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR             (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR             (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR             (0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR               (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR               (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT            (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#else
+#define REG_PIOB_PER       (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR       (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR       (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER       (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR       (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR       (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER      (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR      (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR      (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR      (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR      (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR      (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR      (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER       (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR       (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR       (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR       (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER      (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR      (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR      (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR      (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER      (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR      (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR    (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR    (*(WoReg*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER    (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR    (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR      (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR     (*(WoReg*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER     (*(WoReg*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR     (*(RoReg*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER      (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR      (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR      (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER     (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR     (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR     (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR       (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR       (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR      (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR    (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR    (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR    (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR    (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR      (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR      (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT   (*(RwReg*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_PIOB_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_pioc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_pioc.h
new file mode 100644
index 0000000..3aafe38
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_pioc.h
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PIOC_INSTANCE_
+#define _SAM3N_PIOC_INSTANCE_
+
+/* ========== Register definition for PIOC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOC_PER                (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR                (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR                (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER                (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR                (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR                (0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER               (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR               (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR               (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR               (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR               (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR               (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR               (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER                (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR                (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR                (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR                (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER               (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR               (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR               (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR               (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER               (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR               (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR             (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR             (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER             (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR             (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR               (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR              (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER              (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR              (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER               (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR               (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR               (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER              (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR              (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR              (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR                (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR                (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR               (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR             (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR             (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR             (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR             (0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR               (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR               (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT            (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#else
+#define REG_PIOC_PER       (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR       (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR       (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER       (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR       (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR       (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER      (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR      (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR      (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR      (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR      (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR      (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR      (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER       (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR       (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR       (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR       (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER      (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR      (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR      (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR      (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER      (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR      (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR    (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR    (*(WoReg*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER    (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR    (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR      (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR     (*(WoReg*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER     (*(WoReg*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR     (*(RoReg*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER      (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR      (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR      (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER     (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR     (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR     (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR       (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR       (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR      (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR    (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR    (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR    (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR    (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR      (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR      (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT   (*(RwReg*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_PIOC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_pmc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_pmc.h
new file mode 100644
index 0000000..0f29eae
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_pmc.h
@@ -0,0 +1,78 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PMC_INSTANCE_
+#define _SAM3N_PMC_INSTANCE_
+
+/* ========== Register definition for PMC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PMC_SCER            (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR            (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR            (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0           (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0           (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0           (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR            (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR           (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR          (0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR            (0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_PCK             (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER             (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR             (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR              (0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR             (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR            (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR            (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR            (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR            (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR            (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#else
+#define REG_PMC_SCER   (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR   (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR   (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0  (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0  (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0  (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR   (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR  (*(RoReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR   (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_PCK    (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER    (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR    (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR     (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR    (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR   (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR   (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR   (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR   (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR   (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_PMC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_pwm.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_pwm.h
new file mode 100644
index 0000000..9a4b321
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_pwm.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_PWM_INSTANCE_
+#define _SAM3N_PWM_INSTANCE_
+
+/* ========== Register definition for PWM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PWM_MR             (0x40020000U) /**< \brief (PWM) PWM Mode Register */
+#define REG_PWM_ENA            (0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS            (0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR             (0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER            (0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register */
+#define REG_PWM_IDR            (0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register */
+#define REG_PWM_IMR            (0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register */
+#define REG_PWM_ISR            (0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register */
+#define REG_PWM_CMR0           (0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0          (0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CPRD0          (0x40020208U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CCNT0          (0x4002020CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_CUPD0          (0x40020210U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 0) */
+#define REG_PWM_CMR1           (0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1          (0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CPRD1          (0x40020228U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CCNT1          (0x4002022CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_CUPD1          (0x40020230U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 1) */
+#define REG_PWM_CMR2           (0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2          (0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CPRD2          (0x40020248U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CCNT2          (0x4002024CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_CUPD2          (0x40020250U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 2) */
+#define REG_PWM_CMR3           (0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3          (0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CPRD3          (0x40020268U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CCNT3          (0x4002026CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_CUPD3          (0x40020270U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 3) */
+#else
+#define REG_PWM_MR    (*(RwReg*)0x40020000U) /**< \brief (PWM) PWM Mode Register */
+#define REG_PWM_ENA   (*(WoReg*)0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS   (*(WoReg*)0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR    (*(RoReg*)0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER   (*(WoReg*)0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register */
+#define REG_PWM_IDR   (*(WoReg*)0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register */
+#define REG_PWM_IMR   (*(RoReg*)0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register */
+#define REG_PWM_ISR   (*(RoReg*)0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register */
+#define REG_PWM_CMR0  (*(RwReg*)0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0 (*(RwReg*)0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CPRD0 (*(RwReg*)0x40020208U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CCNT0 (*(RoReg*)0x4002020CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_CUPD0 (*(WoReg*)0x40020210U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 0) */
+#define REG_PWM_CMR1  (*(RwReg*)0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1 (*(RwReg*)0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CPRD1 (*(RwReg*)0x40020228U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CCNT1 (*(RoReg*)0x4002022CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_CUPD1 (*(WoReg*)0x40020230U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 1) */
+#define REG_PWM_CMR2  (*(RwReg*)0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2 (*(RwReg*)0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CPRD2 (*(RwReg*)0x40020248U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CCNT2 (*(RoReg*)0x4002024CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_CUPD2 (*(WoReg*)0x40020250U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 2) */
+#define REG_PWM_CMR3  (*(RwReg*)0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3 (*(RwReg*)0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CPRD3 (*(RwReg*)0x40020268U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CCNT3 (*(RoReg*)0x4002026CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_CUPD3 (*(WoReg*)0x40020270U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 3) */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_PWM_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_rstc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_rstc.h
new file mode 100644
index 0000000..ac90186
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_rstc.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_RSTC_INSTANCE_
+#define _SAM3N_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RSTC_CR          (0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR          (0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR          (0x400E1408U) /**< \brief (RSTC) Mode Register */
+#else
+#define REG_RSTC_CR (*(WoReg*)0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR (*(RoReg*)0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR (*(RwReg*)0x400E1408U) /**< \brief (RSTC) Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_RSTC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_rtc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_rtc.h
new file mode 100644
index 0000000..20226d1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_rtc.h
@@ -0,0 +1,64 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_RTC_INSTANCE_
+#define _SAM3N_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_CR              (0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR              (0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR            (0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR            (0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR          (0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR          (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR              (0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR            (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER             (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR             (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR             (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER             (0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR            (0x400E1544U) /**< \brief (RTC) Write Protect Mode Register */
+#else
+#define REG_RTC_CR     (*(RwReg*)0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR     (*(RwReg*)0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR   (*(RwReg*)0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR   (*(RwReg*)0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR (*(RwReg*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR     (*(RoReg*)0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR   (*(WoReg*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER    (*(WoReg*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR    (*(WoReg*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR    (*(RoReg*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER    (*(RoReg*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR   (*(RwReg*)0x400E1544U) /**< \brief (RTC) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_RTC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_rtt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_rtt.h
new file mode 100644
index 0000000..3854b49
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_rtt.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_RTT_INSTANCE_
+#define _SAM3N_RTT_INSTANCE_
+
+/* ========== Register definition for RTT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTT_MR          (0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR          (0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR          (0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR          (0x400E143CU) /**< \brief (RTT) Status Register */
+#else
+#define REG_RTT_MR (*(RwReg*)0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR (*(RwReg*)0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR (*(RoReg*)0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR (*(RoReg*)0x400E143CU) /**< \brief (RTT) Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_RTT_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_spi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_spi.h
new file mode 100644
index 0000000..628b5db
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_spi.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_SPI_INSTANCE_
+#define _SAM3N_SPI_INSTANCE_
+
+/* ========== Register definition for SPI peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SPI_CR              (0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR              (0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR             (0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR             (0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR              (0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER             (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR             (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR             (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR             (0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR            (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR            (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR             (0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR             (0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR             (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR             (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR            (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR            (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR            (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR            (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR            (0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR            (0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#else
+#define REG_SPI_CR     (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR     (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR    (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR    (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR     (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER    (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR    (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR    (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR    (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR   (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR   (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR    (*(RwReg*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR    (*(RwReg*)0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR    (*(RwReg*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR    (*(RwReg*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR   (*(RwReg*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR   (*(RwReg*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR   (*(RwReg*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR   (*(RwReg*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR   (*(WoReg*)0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR   (*(RoReg*)0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_SPI_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_supc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_supc.h
new file mode 100644
index 0000000..c2a129b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_supc.h
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_SUPC_INSTANCE_
+#define _SAM3N_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SUPC_CR            (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR          (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR            (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR          (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR          (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR            (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#else
+#define REG_SUPC_CR   (*(WoReg*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR   (*(RwReg*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR (*(RwReg*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR   (*(RoReg*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_SUPC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_tc0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_tc0.h
new file mode 100644
index 0000000..d186494
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_tc0.h
@@ -0,0 +1,118 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_TC0_INSTANCE_
+#define _SAM3N_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC0_CCR0           (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0           (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0          (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0            (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0            (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0            (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0            (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0            (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0           (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0           (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0           (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1           (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1           (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1          (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1            (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1            (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1            (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1            (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1            (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1           (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1           (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1           (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2           (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2           (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2          (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2            (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2            (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2            (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2            (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2            (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2           (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2           (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2           (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR            (0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR            (0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER           (0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR           (0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR           (0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR           (0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_WPMR           (0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#else
+#define REG_TC0_CCR0  (*(WoReg*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0  (*(RwReg*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0 (*(RwReg*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0   (*(RoReg*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0   (*(RwReg*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0   (*(RwReg*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0   (*(RwReg*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0   (*(RoReg*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0  (*(WoReg*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0  (*(WoReg*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0  (*(RoReg*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1  (*(WoReg*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1  (*(RwReg*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1 (*(RwReg*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1   (*(RoReg*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1   (*(RwReg*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1   (*(RwReg*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1   (*(RwReg*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1   (*(RoReg*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1  (*(WoReg*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1  (*(WoReg*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1  (*(RoReg*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2  (*(WoReg*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2  (*(RwReg*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2 (*(RwReg*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2   (*(RoReg*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2   (*(RwReg*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2   (*(RwReg*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2   (*(RwReg*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2   (*(RoReg*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2  (*(WoReg*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2  (*(WoReg*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2  (*(RoReg*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR   (*(WoReg*)0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR   (*(RwReg*)0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER  (*(WoReg*)0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR  (*(WoReg*)0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR  (*(RoReg*)0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR  (*(RoReg*)0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_WPMR  (*(RwReg*)0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_TC0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_tc1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_tc1.h
new file mode 100644
index 0000000..5208256
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_tc1.h
@@ -0,0 +1,118 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_TC1_INSTANCE_
+#define _SAM3N_TC1_INSTANCE_
+
+/* ========== Register definition for TC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC1_CCR0           (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0           (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0          (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0            (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0            (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0            (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0            (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0            (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0           (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0           (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0           (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1           (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1           (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1          (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1            (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1            (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1            (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1            (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1            (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1           (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1           (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1           (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2           (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2           (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2          (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2            (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2            (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2            (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2            (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2            (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2           (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2           (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2           (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR            (0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR            (0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER           (0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR           (0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR           (0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR           (0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_WPMR           (0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#else
+#define REG_TC1_CCR0  (*(WoReg*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0  (*(RwReg*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0 (*(RwReg*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0   (*(RoReg*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0   (*(RwReg*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0   (*(RwReg*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0   (*(RwReg*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0   (*(RoReg*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0  (*(WoReg*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0  (*(WoReg*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0  (*(RoReg*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1  (*(WoReg*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1  (*(RwReg*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1 (*(RwReg*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1   (*(RoReg*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1   (*(RwReg*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1   (*(RwReg*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1   (*(RwReg*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1   (*(RoReg*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1  (*(WoReg*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1  (*(WoReg*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1  (*(RoReg*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2  (*(WoReg*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2  (*(RwReg*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2 (*(RwReg*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2   (*(RoReg*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2   (*(RwReg*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2   (*(RwReg*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2   (*(RwReg*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2   (*(RoReg*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2  (*(WoReg*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2  (*(WoReg*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2  (*(RoReg*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR   (*(WoReg*)0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR   (*(RwReg*)0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER  (*(WoReg*)0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR  (*(WoReg*)0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR  (*(RoReg*)0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR  (*(RoReg*)0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_WPMR  (*(RwReg*)0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_TC1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_twi0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_twi0.h
new file mode 100644
index 0000000..dbaa302
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_twi0.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_TWI0_INSTANCE_
+#define _SAM3N_TWI0_INSTANCE_
+
+/* ========== Register definition for TWI0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TWI0_CR            (0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR           (0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR           (0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR          (0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR          (0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR            (0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER           (0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR           (0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR           (0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR           (0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR           (0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR           (0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR           (0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR           (0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR           (0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR          (0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR          (0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR          (0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR          (0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR          (0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR          (0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#else
+#define REG_TWI0_CR   (*(WoReg*)0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR  (*(RwReg*)0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR  (*(RwReg*)0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR (*(RwReg*)0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR (*(RwReg*)0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR   (*(RoReg*)0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER  (*(WoReg*)0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR  (*(WoReg*)0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR  (*(RoReg*)0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR  (*(RoReg*)0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR  (*(WoReg*)0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR  (*(RwReg*)0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR  (*(RwReg*)0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR  (*(RwReg*)0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR  (*(RwReg*)0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR (*(RwReg*)0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR (*(RwReg*)0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR (*(RwReg*)0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR (*(RwReg*)0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR (*(WoReg*)0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR (*(RoReg*)0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_TWI0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_twi1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_twi1.h
new file mode 100644
index 0000000..c983411
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_twi1.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_TWI1_INSTANCE_
+#define _SAM3N_TWI1_INSTANCE_
+
+/* ========== Register definition for TWI1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TWI1_CR            (0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR           (0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR           (0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR          (0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR          (0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR            (0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER           (0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR           (0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR           (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR           (0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR           (0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#else
+#define REG_TWI1_CR   (*(WoReg*)0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR  (*(RwReg*)0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR  (*(RwReg*)0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR (*(RwReg*)0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR (*(RwReg*)0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR   (*(RoReg*)0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER  (*(WoReg*)0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR  (*(WoReg*)0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR  (*(RoReg*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR  (*(RoReg*)0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR  (*(WoReg*)0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_TWI1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_uart0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_uart0.h
new file mode 100644
index 0000000..c9a7359
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_uart0.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_UART0_INSTANCE_
+#define _SAM3N_UART0_INSTANCE_
+
+/* ========== Register definition for UART0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UART0_CR            (0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR            (0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER           (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR           (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR           (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR            (0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR           (0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR           (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR          (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR           (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR           (0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR           (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR           (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR          (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR          (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR          (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR          (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR          (0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR          (0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#else
+#define REG_UART0_CR   (*(WoReg*)0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR   (*(RwReg*)0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER  (*(WoReg*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR  (*(WoReg*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR  (*(RoReg*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR   (*(RoReg*)0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR  (*(RoReg*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR  (*(WoReg*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR  (*(RwReg*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR  (*(RwReg*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR  (*(RwReg*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR  (*(RwReg*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_UART0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_uart1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_uart1.h
new file mode 100644
index 0000000..1145f06
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_uart1.h
@@ -0,0 +1,56 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_UART1_INSTANCE_
+#define _SAM3N_UART1_INSTANCE_
+
+/* ========== Register definition for UART1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UART1_CR            (0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR            (0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER           (0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR           (0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR           (0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR            (0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR           (0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR           (0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR          (0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#else
+#define REG_UART1_CR   (*(WoReg*)0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR   (*(RwReg*)0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER  (*(WoReg*)0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR  (*(WoReg*)0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR  (*(RoReg*)0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR   (*(RoReg*)0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR  (*(RoReg*)0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR  (*(WoReg*)0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_UART1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_usart0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_usart0.h
new file mode 100644
index 0000000..6baaf1c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_usart0.h
@@ -0,0 +1,90 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_USART0_INSTANCE_
+#define _SAM3N_USART0_INSTANCE_
+
+/* ========== Register definition for USART0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART0_CR          (0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR          (0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER          (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR          (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR          (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR          (0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR          (0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR          (0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR          (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR          (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR          (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI          (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER          (0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF          (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_WPMR          (0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR          (0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_RPR          (0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR          (0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR          (0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR          (0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR          (0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR          (0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR          (0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR          (0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR          (0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR          (0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#else
+#define REG_USART0_CR (*(WoReg*)0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR (*(RwReg*)0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER (*(WoReg*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR (*(WoReg*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR (*(RoReg*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR (*(RoReg*)0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR (*(RoReg*)0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR (*(WoReg*)0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR (*(RwReg*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR (*(RwReg*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR (*(RwReg*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI (*(RwReg*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER (*(RoReg*)0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF (*(RwReg*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_WPMR (*(RwReg*)0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR (*(RoReg*)0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_RPR (*(RwReg*)0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR (*(RwReg*)0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR (*(RwReg*)0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR (*(RwReg*)0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR (*(RwReg*)0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR (*(RwReg*)0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR (*(RwReg*)0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR (*(RwReg*)0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR (*(WoReg*)0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR (*(RoReg*)0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_USART0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_usart1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_usart1.h
new file mode 100644
index 0000000..8c3dd9f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_usart1.h
@@ -0,0 +1,70 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_USART1_INSTANCE_
+#define _SAM3N_USART1_INSTANCE_
+
+/* ========== Register definition for USART1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART1_CR          (0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR          (0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER          (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR          (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR          (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR          (0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR          (0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR          (0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR          (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR          (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR          (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI          (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER          (0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF          (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_WPMR          (0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR          (0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#else
+#define REG_USART1_CR (*(WoReg*)0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR (*(RwReg*)0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER (*(WoReg*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR (*(WoReg*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR (*(RoReg*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR (*(RoReg*)0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR (*(RoReg*)0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR (*(WoReg*)0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR (*(RwReg*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR (*(RwReg*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR (*(RwReg*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI (*(RwReg*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER (*(RoReg*)0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF (*(RwReg*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_WPMR (*(RwReg*)0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR (*(RoReg*)0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_USART1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_wdt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_wdt.h
new file mode 100644
index 0000000..70c71a7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/instance/instance_wdt.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_WDT_INSTANCE_
+#define _SAM3N_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CR          (0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR          (0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR          (0x400E1458U) /**< \brief (WDT) Status Register */
+#else
+#define REG_WDT_CR (*(WoReg*)0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR (*(RwReg*)0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR (*(RoReg*)0x400E1458U) /**< \brief (WDT) Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3N_WDT_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n00a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n00a.h
new file mode 100644
index 0000000..dbc92f8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n00a.h
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N00A_PIO_
+#define _SAM3N00A_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+
+#endif /* _SAM3N00A_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n00b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n00b.h
new file mode 100644
index 0000000..4ded873
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n00b.h
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N00B_PIO_
+#define _SAM3N00B_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+
+#endif /* _SAM3N00B_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n0a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n0a.h
new file mode 100644
index 0000000..c080f26
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n0a.h
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N0A_PIO_
+#define _SAM3N0A_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+
+#endif /* _SAM3N0A_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n0b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n0b.h
new file mode 100644
index 0000000..4e024cc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n0b.h
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N0B_PIO_
+#define _SAM3N0B_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+
+#endif /* _SAM3N0B_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n0c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n0c.h
new file mode 100644
index 0000000..b360898
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n0c.h
@@ -0,0 +1,313 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N0C_PIO_
+#define _SAM3N0C_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0           (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1           (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2           (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3           (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4           (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5           (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6           (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7           (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8           (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9           (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10          (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11          (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12          (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13          (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14          (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15          (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16          (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17          (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18          (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19          (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20          (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21          (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22          (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23          (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24          (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25          (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26          (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27          (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28          (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29          (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30          (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31          (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3   (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4   (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5   (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3   (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4   (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5   (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3   (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4   (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5   (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PC0_IDX       64
+#define PIO_PC1_IDX       65
+#define PIO_PC2_IDX       66
+#define PIO_PC3_IDX       67
+#define PIO_PC4_IDX       68
+#define PIO_PC5_IDX       69
+#define PIO_PC6_IDX       70
+#define PIO_PC7_IDX       71
+#define PIO_PC8_IDX       72
+#define PIO_PC9_IDX       73
+#define PIO_PC10_IDX      74
+#define PIO_PC11_IDX      75
+#define PIO_PC12_IDX      76
+#define PIO_PC13_IDX      77
+#define PIO_PC14_IDX      78
+#define PIO_PC15_IDX      79
+#define PIO_PC16_IDX      80
+#define PIO_PC17_IDX      81
+#define PIO_PC18_IDX      82
+#define PIO_PC19_IDX      83
+#define PIO_PC20_IDX      84
+#define PIO_PC21_IDX      85
+#define PIO_PC22_IDX      86
+#define PIO_PC23_IDX      87
+#define PIO_PC24_IDX      88
+#define PIO_PC25_IDX      89
+#define PIO_PC26_IDX      90
+#define PIO_PC27_IDX      91
+#define PIO_PC28_IDX      92
+#define PIO_PC29_IDX      93
+#define PIO_PC30_IDX      94
+#define PIO_PC31_IDX      95
+
+#endif /* _SAM3N0C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n1a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n1a.h
new file mode 100644
index 0000000..33a9722
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n1a.h
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N1A_PIO_
+#define _SAM3N1A_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+
+#endif /* _SAM3N1A_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n1b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n1b.h
new file mode 100644
index 0000000..ed8e8d7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n1b.h
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N1B_PIO_
+#define _SAM3N1B_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+
+#endif /* _SAM3N1B_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n1c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n1c.h
new file mode 100644
index 0000000..f20ff6d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n1c.h
@@ -0,0 +1,313 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N1C_PIO_
+#define _SAM3N1C_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0           (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1           (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2           (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3           (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4           (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5           (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6           (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7           (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8           (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9           (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10          (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11          (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12          (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13          (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14          (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15          (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16          (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17          (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18          (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19          (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20          (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21          (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22          (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23          (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24          (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25          (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26          (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27          (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28          (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29          (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30          (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31          (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3   (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4   (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5   (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3   (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4   (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5   (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3   (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4   (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5   (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PC0_IDX       64
+#define PIO_PC1_IDX       65
+#define PIO_PC2_IDX       66
+#define PIO_PC3_IDX       67
+#define PIO_PC4_IDX       68
+#define PIO_PC5_IDX       69
+#define PIO_PC6_IDX       70
+#define PIO_PC7_IDX       71
+#define PIO_PC8_IDX       72
+#define PIO_PC9_IDX       73
+#define PIO_PC10_IDX      74
+#define PIO_PC11_IDX      75
+#define PIO_PC12_IDX      76
+#define PIO_PC13_IDX      77
+#define PIO_PC14_IDX      78
+#define PIO_PC15_IDX      79
+#define PIO_PC16_IDX      80
+#define PIO_PC17_IDX      81
+#define PIO_PC18_IDX      82
+#define PIO_PC19_IDX      83
+#define PIO_PC20_IDX      84
+#define PIO_PC21_IDX      85
+#define PIO_PC22_IDX      86
+#define PIO_PC23_IDX      87
+#define PIO_PC24_IDX      88
+#define PIO_PC25_IDX      89
+#define PIO_PC26_IDX      90
+#define PIO_PC27_IDX      91
+#define PIO_PC28_IDX      92
+#define PIO_PC29_IDX      93
+#define PIO_PC30_IDX      94
+#define PIO_PC31_IDX      95
+
+#endif /* _SAM3N1C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n2a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n2a.h
new file mode 100644
index 0000000..f6ad819
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n2a.h
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N2A_PIO_
+#define _SAM3N2A_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+
+#endif /* _SAM3N2A_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n2b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n2b.h
new file mode 100644
index 0000000..e80c12a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n2b.h
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N2B_PIO_
+#define _SAM3N2B_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+
+#endif /* _SAM3N2B_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n2c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n2c.h
new file mode 100644
index 0000000..1aa1ab6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n2c.h
@@ -0,0 +1,313 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N2C_PIO_
+#define _SAM3N2C_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0           (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1           (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2           (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3           (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4           (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5           (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6           (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7           (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8           (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9           (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10          (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11          (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12          (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13          (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14          (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15          (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16          (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17          (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18          (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19          (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20          (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21          (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22          (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23          (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24          (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25          (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26          (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27          (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28          (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29          (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30          (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31          (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3   (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4   (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5   (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3   (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4   (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5   (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3   (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4   (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5   (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PC0_IDX       64
+#define PIO_PC1_IDX       65
+#define PIO_PC2_IDX       66
+#define PIO_PC3_IDX       67
+#define PIO_PC4_IDX       68
+#define PIO_PC5_IDX       69
+#define PIO_PC6_IDX       70
+#define PIO_PC7_IDX       71
+#define PIO_PC8_IDX       72
+#define PIO_PC9_IDX       73
+#define PIO_PC10_IDX      74
+#define PIO_PC11_IDX      75
+#define PIO_PC12_IDX      76
+#define PIO_PC13_IDX      77
+#define PIO_PC14_IDX      78
+#define PIO_PC15_IDX      79
+#define PIO_PC16_IDX      80
+#define PIO_PC17_IDX      81
+#define PIO_PC18_IDX      82
+#define PIO_PC19_IDX      83
+#define PIO_PC20_IDX      84
+#define PIO_PC21_IDX      85
+#define PIO_PC22_IDX      86
+#define PIO_PC23_IDX      87
+#define PIO_PC24_IDX      88
+#define PIO_PC25_IDX      89
+#define PIO_PC26_IDX      90
+#define PIO_PC27_IDX      91
+#define PIO_PC28_IDX      92
+#define PIO_PC29_IDX      93
+#define PIO_PC30_IDX      94
+#define PIO_PC31_IDX      95
+
+#endif /* _SAM3N2C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n4a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n4a.h
new file mode 100644
index 0000000..ee1255b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n4a.h
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N4A_PIO_
+#define _SAM3N4A_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+
+#endif /* _SAM3N4A_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n4b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n4b.h
new file mode 100644
index 0000000..dcf0fc7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n4b.h
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N4B_PIO_
+#define _SAM3N4B_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+
+#endif /* _SAM3N4B_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n4c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n4c.h
new file mode 100644
index 0000000..1c0b572
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/pio/pio_sam3n4c.h
@@ -0,0 +1,313 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N4C_PIO_
+#define _SAM3N4C_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0           (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1           (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2           (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3           (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4           (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5           (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6           (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7           (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8           (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9           (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10          (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11          (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12          (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13          (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14          (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15          (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16          (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17          (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18          (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19          (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20          (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21          (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22          (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23          (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24          (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25          (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26          (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27          (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28          (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29          (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30          (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31          (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0    (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1    (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10   (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11   (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12   (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13   (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14   (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PC31X1_AD15   (1u << 31) /**< \brief Adc signal: AD15 */
+#define PIO_PA19X1_AD2    (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9  (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3    (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4     (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5     (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6     (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12  (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7     (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8    (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9    (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG    (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0   (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PA2C_DATRG    (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0     (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0    (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PC16B_PCK0    (1u << 16) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1    (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PC17B_PCK1    (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2    (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2    (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2     (1u << 3)  /**< \brief Pmc signal: PCK2 */
+#define PIO_PC14B_PCK2    (1u << 14) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PA11B_PWM0    (1u << 11) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA23B_PWM0    (1u << 23) /**< \brief Pwm signal: PWM0 */
+#define PIO_PB0A_PWM0     (1u << 0)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC8B_PWM0     (1u << 8)  /**< \brief Pwm signal: PWM0 */
+#define PIO_PC18B_PWM0    (1u << 18) /**< \brief Pwm signal: PWM0 */
+#define PIO_PC22B_PWM0    (1u << 22) /**< \brief Pwm signal: PWM0 */
+#define PIO_PA1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PA12B_PWM1    (1u << 12) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA24B_PWM1    (1u << 24) /**< \brief Pwm signal: PWM1 */
+#define PIO_PB1A_PWM1     (1u << 1)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC9B_PWM1     (1u << 9)  /**< \brief Pwm signal: PWM1 */
+#define PIO_PC19B_PWM1    (1u << 19) /**< \brief Pwm signal: PWM1 */
+#define PIO_PA2A_PWM2     (1u << 2)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PA13B_PWM2    (1u << 13) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA25B_PWM2    (1u << 25) /**< \brief Pwm signal: PWM2 */
+#define PIO_PB4B_PWM2     (1u << 4)  /**< \brief Pwm signal: PWM2 */
+#define PIO_PC10B_PWM2    (1u << 10) /**< \brief Pwm signal: PWM2 */
+#define PIO_PC20B_PWM2    (1u << 20) /**< \brief Pwm signal: PWM2 */
+#define PIO_PA7B_PWM3     (1u << 7)  /**< \brief Pwm signal: PWM3 */
+#define PIO_PA14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PB14B_PWM3    (1u << 14) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC11B_PWM3    (1u << 11) /**< \brief Pwm signal: PWM3 */
+#define PIO_PC21B_PWM3    (1u << 21) /**< \brief Pwm signal: PWM3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO    (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI    (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0   (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1    (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1   (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1   (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1    (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2   (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2   (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2    (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC7B_NPCS2    (1u << 7)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3    (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3   (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK    (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0    (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1   (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2   (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0    (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1   (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2   (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0    (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1   (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2   (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3   (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4   (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5   (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3   (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4   (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5   (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3   (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4   (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5   (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0    (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0     (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1    (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1     (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0    (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0   (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1    (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1    (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0     (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0     (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0     (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1    (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA24A_RTS1    (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1    (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1    (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PC0_IDX       64
+#define PIO_PC1_IDX       65
+#define PIO_PC2_IDX       66
+#define PIO_PC3_IDX       67
+#define PIO_PC4_IDX       68
+#define PIO_PC5_IDX       69
+#define PIO_PC6_IDX       70
+#define PIO_PC7_IDX       71
+#define PIO_PC8_IDX       72
+#define PIO_PC9_IDX       73
+#define PIO_PC10_IDX      74
+#define PIO_PC11_IDX      75
+#define PIO_PC12_IDX      76
+#define PIO_PC13_IDX      77
+#define PIO_PC14_IDX      78
+#define PIO_PC15_IDX      79
+#define PIO_PC16_IDX      80
+#define PIO_PC17_IDX      81
+#define PIO_PC18_IDX      82
+#define PIO_PC19_IDX      83
+#define PIO_PC20_IDX      84
+#define PIO_PC21_IDX      85
+#define PIO_PC22_IDX      86
+#define PIO_PC23_IDX      87
+#define PIO_PC24_IDX      88
+#define PIO_PC25_IDX      89
+#define PIO_PC26_IDX      90
+#define PIO_PC27_IDX      91
+#define PIO_PC28_IDX      92
+#define PIO_PC29_IDX      93
+#define PIO_PC30_IDX      94
+#define PIO_PC31_IDX      95
+
+#endif /* _SAM3N4C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n.h
new file mode 100644
index 0000000..2cace14
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n.h
@@ -0,0 +1,65 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N_
+#define _SAM3N_
+
+#if defined __SAM3N00A__
+  #include "sam3n00a.h"
+#elif defined __SAM3N0A__
+  #include "sam3n0a.h"
+#elif defined __SAM3N00B__
+  #include "sam3n00b.h"
+#elif defined __SAM3N0B__
+  #include "sam3n0b.h"
+#elif defined __SAM3N0C__
+  #include "sam3n0c.h"
+#elif defined __SAM3N1A__
+  #include "sam3n1a.h"
+#elif defined __SAM3N1B__
+  #include "sam3n1b.h"
+#elif defined __SAM3N1C__
+  #include "sam3n1c.h"
+#elif defined __SAM3N2A__
+  #include "sam3n2a.h"
+#elif defined __SAM3N2B__
+  #include "sam3n2b.h"
+#elif defined __SAM3N2C__
+  #include "sam3n2c.h"
+#elif defined __SAM3N4A__
+  #include "sam3n4a.h"
+#elif defined __SAM3N4B__
+  #include "sam3n4b.h"
+#elif defined __SAM3N4C__
+  #include "sam3n4c.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAM3N_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n00a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n00a.h
new file mode 100644
index 0000000..fb99b9b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n00a.h
@@ -0,0 +1,424 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N00A_
+#define _SAM3N00A_
+
+/** \addtogroup SAM3N00A_definitions SAM3N00A definitions
+  This file defines all structures and symbols for SAM3N00A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N00A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N00A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N00A specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N00A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N00A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N00A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N00A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N00A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N00A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N00A Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N00A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N00A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N00A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N00A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N00A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N00A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N00A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N00A Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N00A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N00A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N00A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N00A Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N00A Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N00A Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N00A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N00A does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N00A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N00A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N00A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N00A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N00A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N00A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N00A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N00A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N00A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N00A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N00A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n00a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N00A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x4000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (64u)
+#define IFLASH_NB_OF_LOCK_BITS  (1u)
+#define IRAM_SIZE               (0x1000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N00A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N00A_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n00b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n00b.h
new file mode 100644
index 0000000..1e73737
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n00b.h
@@ -0,0 +1,430 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N00B_
+#define _SAM3N00B_
+
+/** \addtogroup SAM3N00B_definitions SAM3N00B definitions
+  This file defines all structures and symbols for SAM3N00B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N00B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N00B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N00B specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N00B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N00B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N00B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N00B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N00B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N00B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N00B Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N00B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N00B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N00B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N00B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N00B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N00B USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N00B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N00B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N00B Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N00B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N00B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N00B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N00B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N00B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N00B Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N00B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N00B does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N00B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N00B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N00B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N00B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N00B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N00B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N00B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N00B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N00B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N00B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N00B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n00b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N00B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x4000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (64u)
+#define IFLASH_NB_OF_LOCK_BITS  (1u)
+#define IRAM_SIZE               (0x1000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N00B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N00B_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n0a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n0a.h
new file mode 100644
index 0000000..e051ad3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n0a.h
@@ -0,0 +1,424 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N0A_
+#define _SAM3N0A_
+
+/** \addtogroup SAM3N0A_definitions SAM3N0A definitions
+  This file defines all structures and symbols for SAM3N0A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N0A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N0A specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N0A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N0A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N0A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N0A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N0A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N0A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N0A Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N0A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N0A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N0A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N0A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N0A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N0A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N0A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N0A Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N0A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N0A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N0A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N0A Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N0A Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N0A Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N0A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N0A does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N0A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N0A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N0A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N0A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N0A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N0A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n0a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N0A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x8000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (128u)
+#define IFLASH_NB_OF_LOCK_BITS  (2u)
+#define IRAM_SIZE               (0x2000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N0A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N0A_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n0b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n0b.h
new file mode 100644
index 0000000..f831cd0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n0b.h
@@ -0,0 +1,430 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N0B_
+#define _SAM3N0B_
+
+/** \addtogroup SAM3N0B_definitions SAM3N0B definitions
+  This file defines all structures and symbols for SAM3N0B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N0B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N0B specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N0B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N0B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N0B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N0B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N0B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N0B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N0B Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N0B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N0B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N0B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N0B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N0B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N0B USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N0B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N0B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N0B Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N0B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N0B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N0B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N0B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N0B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N0B Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N0B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N0B does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N0B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N0B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N0B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N0B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N0B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N0B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n0b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N0B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x8000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (128u)
+#define IFLASH_NB_OF_LOCK_BITS  (2u)
+#define IRAM_SIZE               (0x2000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N0B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N0B_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n0c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n0c.h
new file mode 100644
index 0000000..1bd59e6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n0c.h
@@ -0,0 +1,448 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N0C_
+#define _SAM3N0C_
+
+/** \addtogroup SAM3N0C_definitions SAM3N0C definitions
+  This file defines all structures and symbols for SAM3N0C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N0C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N0C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N0C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N0C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N0C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N0C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N0C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N0C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N0C Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N0C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N0C UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N0C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N0C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3N0C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3N0C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N0C USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N0C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N0C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N0C Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N0C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N0C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N0C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3N0C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3N0C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3N0C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3N0C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N0C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N0C Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
+  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
+  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N0C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N0C does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N0C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N0C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N0C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N0C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N0C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N0C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N0C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n0c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N0C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x8000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (128u)
+#define IFLASH_NB_OF_LOCK_BITS  (2u)
+#define IRAM_SIZE               (0x2000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N0C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N0C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n1a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n1a.h
new file mode 100644
index 0000000..5e1d408
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n1a.h
@@ -0,0 +1,424 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N1A_
+#define _SAM3N1A_
+
+/** \addtogroup SAM3N1A_definitions SAM3N1A definitions
+  This file defines all structures and symbols for SAM3N1A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N1A specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N1A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N1A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N1A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N1A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N1A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N1A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N1A Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N1A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N1A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N1A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N1A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N1A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N1A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N1A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N1A Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N1A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N1A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N1A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N1A Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N1A Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N1A Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N1A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N1A does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N1A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n1a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x2000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N1A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N1A_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n1b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n1b.h
new file mode 100644
index 0000000..ba7d0ee
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n1b.h
@@ -0,0 +1,430 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N1B_
+#define _SAM3N1B_
+
+/** \addtogroup SAM3N1B_definitions SAM3N1B definitions
+  This file defines all structures and symbols for SAM3N1B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N1B specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N1B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N1B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N1B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N1B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N1B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N1B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N1B Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N1B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N1B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N1B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N1B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N1B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N1B USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N1B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N1B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N1B Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N1B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N1B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N1B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N1B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N1B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N1B Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N1B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N1B does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N1B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n1b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x2000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N1B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N1B_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n1c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n1c.h
new file mode 100644
index 0000000..02489b6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n1c.h
@@ -0,0 +1,448 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N1C_
+#define _SAM3N1C_
+
+/** \addtogroup SAM3N1C_definitions SAM3N1C definitions
+  This file defines all structures and symbols for SAM3N1C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N1C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N1C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N1C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N1C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N1C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N1C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N1C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N1C Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N1C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N1C UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N1C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N1C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3N1C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3N1C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N1C USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N1C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N1C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N1C Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N1C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N1C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N1C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3N1C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3N1C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3N1C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3N1C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N1C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N1C Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
+  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
+  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N1C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N1C does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N1C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N1C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n1c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x2000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N1C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N1C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n2a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n2a.h
new file mode 100644
index 0000000..6867ca3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n2a.h
@@ -0,0 +1,424 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N2A_
+#define _SAM3N2A_
+
+/** \addtogroup SAM3N2A_definitions SAM3N2A definitions
+  This file defines all structures and symbols for SAM3N2A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N2A specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N2A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N2A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N2A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N2A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N2A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N2A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N2A Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N2A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N2A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N2A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N2A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N2A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N2A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N2A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N2A Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N2A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N2A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N2A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N2A Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N2A Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N2A Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N2A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N2A does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N2A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n2a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x4000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N2A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N2A_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n2b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n2b.h
new file mode 100644
index 0000000..bf34408
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n2b.h
@@ -0,0 +1,430 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N2B_
+#define _SAM3N2B_
+
+/** \addtogroup SAM3N2B_definitions SAM3N2B definitions
+  This file defines all structures and symbols for SAM3N2B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N2B specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N2B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N2B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N2B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N2B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N2B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N2B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N2B Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N2B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N2B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N2B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N2B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N2B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N2B USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N2B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N2B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N2B Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N2B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N2B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N2B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N2B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N2B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N2B Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N2B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N2B does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N2B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n2b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x4000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N2B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N2B_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n2c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n2c.h
new file mode 100644
index 0000000..1a1690a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n2c.h
@@ -0,0 +1,448 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N2C_
+#define _SAM3N2C_
+
+/** \addtogroup SAM3N2C_definitions SAM3N2C definitions
+  This file defines all structures and symbols for SAM3N2C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N2C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N2C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N2C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N2C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N2C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N2C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N2C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N2C Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N2C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N2C UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N2C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N2C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3N2C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3N2C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N2C USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N2C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N2C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N2C Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N2C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N2C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N2C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3N2C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3N2C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3N2C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3N2C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N2C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N2C Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
+  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
+  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N2C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N2C does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N2C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N2C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n2c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x4000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N2C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N2C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n4a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n4a.h
new file mode 100644
index 0000000..8ebc08b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n4a.h
@@ -0,0 +1,424 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N4A_
+#define _SAM3N4A_
+
+/** \addtogroup SAM3N4A_definitions SAM3N4A definitions
+  This file defines all structures and symbols for SAM3N4A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N4A specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N4A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N4A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N4A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N4A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N4A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N4A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N4A Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N4A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N4A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N4A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N4A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N4A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N4A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N4A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N4A Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N4A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N4A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N4A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N4A Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N4A Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N4A Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N4A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N4A does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N4A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n4a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0x6000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N4A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N4A_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n4b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n4b.h
new file mode 100644
index 0000000..553cdc7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n4b.h
@@ -0,0 +1,430 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N4B_
+#define _SAM3N4B_
+
+/** \addtogroup SAM3N4B_definitions SAM3N4B definitions
+  This file defines all structures and symbols for SAM3N4B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N4B specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N4B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N4B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N4B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N4B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N4B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N4B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N4B Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N4B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N4B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N4B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N4B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3N4B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N4B USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N4B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N4B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N4B Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N4B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N4B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N4B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3N4B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N4B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N4B Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N4B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N4B does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N4B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n4b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0x6000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N4B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N4B_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n4c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n4c.h
new file mode 100644
index 0000000..1203694
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/sam3n4c.h
@@ -0,0 +1,448 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3N4C_
+#define _SAM3N4C_
+
+/** \addtogroup SAM3N4C_definitions SAM3N4C definitions
+  This file defines all structures and symbols for SAM3N4C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3N4C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3N4C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3N4C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3N4C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3N4C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3N4C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3N4C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3N4C Enhanced Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3N4C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3N4C UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3N4C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3N4C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3N4C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3N4C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3N4C USART 1 (USART1) */
+  TWI0_IRQn            = 19, /**< 19 SAM3N4C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3N4C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3N4C Serial Peripheral Interface (SPI) */
+  TC0_IRQn             = 23, /**< 23 SAM3N4C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3N4C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3N4C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3N4C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3N4C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3N4C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3N4C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3N4C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3N4C Pulse Width Modulation (PWM) */
+
+  PERIPH_COUNT_IRQn    = 32  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pvReserved22;
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
+  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
+  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3N4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N4C does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3n.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+
+#define ID_PERIPH_COUNT (32) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3N4C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3n4c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0x6000u)
+
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR   (0x20000000u) /**< Internal RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3N4C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (48000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (32000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (48000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3N4C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/system_sam3n.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/system_sam3n.h
new file mode 100644
index 0000000..b5ab717
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/include/system_sam3n.h
@@ -0,0 +1,70 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef SYSTEM_SAM3N_H_INCLUDED
+#define SYSTEM_SAM3N_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#include 
+
+extern uint32_t SystemCoreClock;	/* System Clock Frequency (Core Clock) */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock with current core Clock 
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+/** 
+ * Initialize flash.
+ */
+void system_init_flash(uint32_t dw_clk);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* SYSTEM_SAM3N_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00_flash.ld
new file mode 100644
index 0000000..7eaf292
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00004000 /* Flash, 16K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00_sram.ld
new file mode 100644
index 0000000..3e5fcb8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00004000 /* Flash, 16K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00a_flash.ld
new file mode 100644
index 0000000..14352b9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00a_sram.ld
new file mode 100644
index 0000000..2827713
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00b_flash.ld
new file mode 100644
index 0000000..14352b9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00b_sram.ld
new file mode 100644
index 0000000..2827713
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n00b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0_flash.ld
new file mode 100644
index 0000000..869521a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00008000 /* Flash, 32K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0_sram.ld
new file mode 100644
index 0000000..4f9f3a2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00008000 /* Flash, 32K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0a_flash.ld
new file mode 100644
index 0000000..b471c97
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0a_sram.ld
new file mode 100644
index 0000000..cfaa53d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0b_flash.ld
new file mode 100644
index 0000000..ead307a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0b_sram.ld
new file mode 100644
index 0000000..cfaa53d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0c_flash.ld
new file mode 100644
index 0000000..ead307a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0c_sram.ld
new file mode 100644
index 0000000..cfaa53d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n0c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1_flash.ld
new file mode 100644
index 0000000..3448812
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1_sram.ld
new file mode 100644
index 0000000..7989f7c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1a_flash.ld
new file mode 100644
index 0000000..d69e14a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1a_sram.ld
new file mode 100644
index 0000000..2b385b5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1b_flash.ld
new file mode 100644
index 0000000..d69e14a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1b_sram.ld
new file mode 100644
index 0000000..2b385b5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1c_flash.ld
new file mode 100644
index 0000000..d69e14a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1c_sram.ld
new file mode 100644
index 0000000..2b385b5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n1c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2_flash.ld
new file mode 100644
index 0000000..acc3f1f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2_sram.ld
new file mode 100644
index 0000000..924f267
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2a_flash.ld
new file mode 100644
index 0000000..d80fe70
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2a_sram.ld
new file mode 100644
index 0000000..7260ef6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2b_flash.ld
new file mode 100644
index 0000000..d80fe70
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2b_sram.ld
new file mode 100644
index 0000000..7260ef6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2c_flash.ld
new file mode 100644
index 0000000..d80fe70
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2c_sram.ld
new file mode 100644
index 0000000..7260ef6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n2c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4_flash.ld
new file mode 100644
index 0000000..25f638e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00006000 /* sram, 24K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4_sram.ld
new file mode 100644
index 0000000..3711e56
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00006000 /* sram, 24K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4a_flash.ld
new file mode 100644
index 0000000..8f2b699
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4a_sram.ld
new file mode 100644
index 0000000..2c1e8ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4b_flash.ld
new file mode 100644
index 0000000..8f2b699
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4b_sram.ld
new file mode 100644
index 0000000..2c1e8ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4c_flash.ld
new file mode 100644
index 0000000..8f2b699
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4c_sram.ld
new file mode 100644
index 0000000..2c1e8ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n_flash.ld
new file mode 100644
index 0000000..b8d50ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n_sram.ld
new file mode 100644
index 0000000..a3945ed
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/sam3n_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/startup_sam3n.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/startup_sam3n.c
new file mode 100644
index 0000000..f711eaa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/as_gcc/startup_sam3n.c
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3n.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3N_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3N_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3N_USART1_INSTANCE_
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3N_USART1_INSTANCE_ */
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3N_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3N_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+	(void*) (0UL),           /* 10 Reserved */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3N_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3N_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM3N_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3N_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+	(void*) (0UL),           /* 18 Reserved */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+ 	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) (0UL),           /* 22 Reserved */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3N_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3N_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler      /* 31 PWM */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00_flash.ld
new file mode 100644
index 0000000..7eaf292
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00004000 /* Flash, 16K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00_sram.ld
new file mode 100644
index 0000000..3e5fcb8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00004000 /* Flash, 16K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00a_flash.ld
new file mode 100644
index 0000000..14352b9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00a_sram.ld
new file mode 100644
index 0000000..2827713
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00b_flash.ld
new file mode 100644
index 0000000..14352b9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00b_sram.ld
new file mode 100644
index 0000000..2827713
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n00b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0_flash.ld
new file mode 100644
index 0000000..869521a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00008000 /* Flash, 32K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0_sram.ld
new file mode 100644
index 0000000..4f9f3a2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00008000 /* Flash, 32K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0a_flash.ld
new file mode 100644
index 0000000..b471c97
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0a_sram.ld
new file mode 100644
index 0000000..cfaa53d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0b_flash.ld
new file mode 100644
index 0000000..ead307a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0b_sram.ld
new file mode 100644
index 0000000..cfaa53d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0c_flash.ld
new file mode 100644
index 0000000..ead307a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0c_sram.ld
new file mode 100644
index 0000000..cfaa53d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n0c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1_flash.ld
new file mode 100644
index 0000000..3448812
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1_sram.ld
new file mode 100644
index 0000000..7989f7c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1a_flash.ld
new file mode 100644
index 0000000..d69e14a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1a_sram.ld
new file mode 100644
index 0000000..2b385b5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1b_flash.ld
new file mode 100644
index 0000000..d69e14a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1b_sram.ld
new file mode 100644
index 0000000..2b385b5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1c_flash.ld
new file mode 100644
index 0000000..d69e14a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1c_sram.ld
new file mode 100644
index 0000000..2b385b5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n1c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2_flash.ld
new file mode 100644
index 0000000..acc3f1f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2_sram.ld
new file mode 100644
index 0000000..924f267
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2a_flash.ld
new file mode 100644
index 0000000..d80fe70
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2a_sram.ld
new file mode 100644
index 0000000..7260ef6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2b_flash.ld
new file mode 100644
index 0000000..d80fe70
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2b_sram.ld
new file mode 100644
index 0000000..7260ef6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2c_flash.ld
new file mode 100644
index 0000000..d80fe70
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2c_sram.ld
new file mode 100644
index 0000000..7260ef6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n2c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4_flash.ld
new file mode 100644
index 0000000..25f638e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00006000 /* sram, 24K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4_sram.ld
new file mode 100644
index 0000000..3711e56
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00006000 /* sram, 24K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4a_flash.ld
new file mode 100644
index 0000000..8f2b699
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4a_sram.ld
new file mode 100644
index 0000000..2c1e8ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4b_flash.ld
new file mode 100644
index 0000000..8f2b699
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4b_sram.ld
new file mode 100644
index 0000000..2c1e8ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4c_flash.ld
new file mode 100644
index 0000000..8f2b699
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4c_sram.ld
new file mode 100644
index 0000000..2c1e8ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n_flash.ld
new file mode 100644
index 0000000..b8d50ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n_sram.ld
new file mode 100644
index 0000000..a3945ed
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/sam3n_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/startup_sam3n.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/startup_sam3n.c
new file mode 100644
index 0000000..f711eaa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc/startup_sam3n.c
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3n.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3N_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3N_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3N_USART1_INSTANCE_
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3N_USART1_INSTANCE_ */
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3N_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3N_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+	(void*) (0UL),           /* 10 Reserved */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3N_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3N_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM3N_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3N_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+	(void*) (0UL),           /* 18 Reserved */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+ 	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) (0UL),           /* 22 Reserved */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3N_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3N_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler      /* 31 PWM */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00_flash.ld
new file mode 100644
index 0000000..7eaf292
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00004000 /* Flash, 16K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00_sram.ld
new file mode 100644
index 0000000..3e5fcb8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00004000 /* Flash, 16K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00a_flash.ld
new file mode 100644
index 0000000..14352b9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00a_sram.ld
new file mode 100644
index 0000000..2827713
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00b_flash.ld
new file mode 100644
index 0000000..14352b9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00b_sram.ld
new file mode 100644
index 0000000..2827713
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n00b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0_flash.ld
new file mode 100644
index 0000000..869521a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00008000 /* Flash, 32K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0_sram.ld
new file mode 100644
index 0000000..4f9f3a2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00008000 /* Flash, 32K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0a_flash.ld
new file mode 100644
index 0000000..b471c97
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0a_sram.ld
new file mode 100644
index 0000000..cfaa53d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0b_flash.ld
new file mode 100644
index 0000000..ead307a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0b_sram.ld
new file mode 100644
index 0000000..cfaa53d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0c_flash.ld
new file mode 100644
index 0000000..ead307a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0c_sram.ld
new file mode 100644
index 0000000..cfaa53d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n0c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1_flash.ld
new file mode 100644
index 0000000..3448812
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1_sram.ld
new file mode 100644
index 0000000..7989f7c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1a_flash.ld
new file mode 100644
index 0000000..d69e14a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1a_sram.ld
new file mode 100644
index 0000000..2b385b5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1b_flash.ld
new file mode 100644
index 0000000..d69e14a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1b_sram.ld
new file mode 100644
index 0000000..2b385b5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1c_flash.ld
new file mode 100644
index 0000000..d69e14a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1c_sram.ld
new file mode 100644
index 0000000..2b385b5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n1c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2_flash.ld
new file mode 100644
index 0000000..acc3f1f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2_sram.ld
new file mode 100644
index 0000000..924f267
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2a_flash.ld
new file mode 100644
index 0000000..d80fe70
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2a_sram.ld
new file mode 100644
index 0000000..7260ef6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2b_flash.ld
new file mode 100644
index 0000000..d80fe70
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2b_sram.ld
new file mode 100644
index 0000000..7260ef6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2c_flash.ld
new file mode 100644
index 0000000..d80fe70
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2c_sram.ld
new file mode 100644
index 0000000..7260ef6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n2c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4_flash.ld
new file mode 100644
index 0000000..25f638e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00006000 /* sram, 24K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4_sram.ld
new file mode 100644
index 0000000..3711e56
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00006000 /* sram, 24K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4a_flash.ld
new file mode 100644
index 0000000..8f2b699
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4a_sram.ld
new file mode 100644
index 0000000..2c1e8ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4b_flash.ld
new file mode 100644
index 0000000..8f2b699
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4b_sram.ld
new file mode 100644
index 0000000..2c1e8ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4c_flash.ld
new file mode 100644
index 0000000..8f2b699
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4c_sram.ld
new file mode 100644
index 0000000..2c1e8ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n_flash.ld
new file mode 100644
index 0000000..b8d50ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n_sram.ld
new file mode 100644
index 0000000..a3945ed
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/sam3n_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/startup_sam3n.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/startup_sam3n.c
new file mode 100644
index 0000000..f711eaa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_arm/startup_sam3n.c
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3n.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3N_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3N_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3N_USART1_INSTANCE_
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3N_USART1_INSTANCE_ */
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3N_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3N_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+	(void*) (0UL),           /* 10 Reserved */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3N_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3N_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM3N_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3N_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+	(void*) (0UL),           /* 18 Reserved */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+ 	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) (0UL),           /* 22 Reserved */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3N_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3N_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler      /* 31 PWM */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00_flash.ld
new file mode 100644
index 0000000..7eaf292
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00004000 /* Flash, 16K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00_sram.ld
new file mode 100644
index 0000000..3e5fcb8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00004000 /* Flash, 16K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00a_flash.ld
new file mode 100644
index 0000000..14352b9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00a_sram.ld
new file mode 100644
index 0000000..2827713
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00b_flash.ld
new file mode 100644
index 0000000..14352b9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00b_sram.ld
new file mode 100644
index 0000000..2827713
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n00b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n00_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0_flash.ld
new file mode 100644
index 0000000..869521a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00008000 /* Flash, 32K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0_sram.ld
new file mode 100644
index 0000000..4f9f3a2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00008000 /* Flash, 32K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0a_flash.ld
new file mode 100644
index 0000000..b471c97
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0a_sram.ld
new file mode 100644
index 0000000..cfaa53d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0b_flash.ld
new file mode 100644
index 0000000..ead307a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0b_sram.ld
new file mode 100644
index 0000000..cfaa53d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0c_flash.ld
new file mode 100644
index 0000000..ead307a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0c_sram.ld
new file mode 100644
index 0000000..cfaa53d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n0c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n0_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1_flash.ld
new file mode 100644
index 0000000..3448812
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1_sram.ld
new file mode 100644
index 0000000..7989f7c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* sram, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1a_flash.ld
new file mode 100644
index 0000000..d69e14a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1a_sram.ld
new file mode 100644
index 0000000..2b385b5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1b_flash.ld
new file mode 100644
index 0000000..d69e14a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1b_sram.ld
new file mode 100644
index 0000000..2b385b5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1c_flash.ld
new file mode 100644
index 0000000..d69e14a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1c_sram.ld
new file mode 100644
index 0000000..2b385b5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n1c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2_flash.ld
new file mode 100644
index 0000000..acc3f1f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2_sram.ld
new file mode 100644
index 0000000..924f267
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2a_flash.ld
new file mode 100644
index 0000000..d80fe70
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2a_sram.ld
new file mode 100644
index 0000000..7260ef6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2b_flash.ld
new file mode 100644
index 0000000..d80fe70
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2b_sram.ld
new file mode 100644
index 0000000..7260ef6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2c_flash.ld
new file mode 100644
index 0000000..d80fe70
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2c_sram.ld
new file mode 100644
index 0000000..7260ef6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n2c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4_flash.ld
new file mode 100644
index 0000000..25f638e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00006000 /* sram, 24K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_flash.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4_sram.ld
new file mode 100644
index 0000000..3711e56
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00006000 /* sram, 24K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x800 ;
+
+INCLUDE sam3n_sram.ld
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4a_flash.ld
new file mode 100644
index 0000000..8f2b699
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4a_sram.ld
new file mode 100644
index 0000000..2c1e8ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4b_flash.ld
new file mode 100644
index 0000000..8f2b699
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4b_sram.ld
new file mode 100644
index 0000000..2c1e8ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4c_flash.ld
new file mode 100644
index 0000000..8f2b699
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4c_sram.ld
new file mode 100644
index 0000000..2c1e8ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3n4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n_flash.ld
new file mode 100644
index 0000000..b8d50ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n_sram.ld
new file mode 100644
index 0000000..a3945ed
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/sam3n_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/startup_sam3n.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/startup_sam3n.c
new file mode 100644
index 0000000..f711eaa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/gcc_atmel/startup_sam3n.c
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3n.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3N_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3N_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3N_USART1_INSTANCE_
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3N_USART1_INSTANCE_ */
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3N_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3N_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+	(void*) (0UL),           /* 10 Reserved */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3N_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3N_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM3N_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3N_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+	(void*) (0UL),           /* 18 Reserved */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+ 	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) (0UL),           /* 22 Reserved */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3N_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3N_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler      /* 31 PWM */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n1_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n1_flash.icf
new file mode 100644
index 0000000..de5fa0c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n1_flash.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00400000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20001FFF;
+define symbol __ICFEDIT_region_ROM_start__  = 0x00400000;
+define symbol __ICFEDIT_region_ROM_end__    = 0x0040FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x800;
+define symbol __ICFEDIT_size_heap__          = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region     = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in ROM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n1_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n1_sram.icf
new file mode 100644
index 0000000..7aeddd5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n1_sram.icf
@@ -0,0 +1,26 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20001FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x800;
+define symbol __ICFEDIT_size_heap__          = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in RAM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n2_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n2_flash.icf
new file mode 100644
index 0000000..4f0b887
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n2_flash.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00400000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__  = 0x00400000;
+define symbol __ICFEDIT_region_ROM_end__    = 0x0041FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x800;
+define symbol __ICFEDIT_size_heap__          = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region     = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in ROM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n2_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n2_sram.icf
new file mode 100644
index 0000000..5d8d0d8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n2_sram.icf
@@ -0,0 +1,26 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x800;
+define symbol __ICFEDIT_size_heap__          = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in RAM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n4_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n4_flash.icf
new file mode 100644
index 0000000..917dd34
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n4_flash.icf
@@ -0,0 +1,36 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00400000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20005FFF;
+define symbol __ICFEDIT_region_ROM_start__  = 0x00400000;
+define symbol __ICFEDIT_region_ROM_end__    = 0x0043FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x800;
+define symbol __ICFEDIT_size_heap__          = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+/* we place the stack at the end of RAM region */
+define symbol __cstack_start__ = __ICFEDIT_region_RAM_end__+1-__ICFEDIT_size_cstack__;
+export symbol __cstack_start__;
+define symbol __cstack_end__ = __cstack_start__+__ICFEDIT_size_cstack__-1;
+export symbol __cstack_end__;
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] - 
+                           mem:[from __cstack_start__ to __cstack_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block HEAP };
+place at address mem:__cstack_start__ { block CSTACK };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n4_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n4_sram.icf
new file mode 100644
index 0000000..79b3255
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/sam3n4_sram.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20005FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x800;
+define symbol __ICFEDIT_size_heap__          = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+/* we place the stack at the end of RAM region */
+define symbol __cstack_start__ = __ICFEDIT_region_RAM_end__+1-__ICFEDIT_size_cstack__;
+export symbol __cstack_start__;
+define symbol __cstack_end__ = __cstack_start__+__ICFEDIT_size_cstack__-1;
+export symbol __cstack_end__;
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] - 
+                           mem:[from __cstack_start__ to __cstack_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in RAM_region { readonly };
+place in RAM_region { readwrite, block HEAP };
+place at address mem:__cstack_start__ { block CSTACK };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/startup_sam3n.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/startup_sam3n.c
new file mode 100644
index 0000000..8e30c41
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/iar/startup_sam3n.c
@@ -0,0 +1,198 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3n.h"
+
+/* Initialize segments */
+extern uint32_t __cstack_start__;
+extern uint32_t __cstack_end__;
+
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+#pragma weak NMI_Handler=Dummy_Handler
+#pragma weak HardFault_Handler=Dummy_Handler
+#pragma weak MemManage_Handler=Dummy_Handler
+#pragma weak BusFault_Handler=Dummy_Handler
+#pragma weak UsageFault_Handler=Dummy_Handler
+#pragma weak SVC_Handler=Dummy_Handler
+#pragma weak DebugMon_Handler=Dummy_Handler
+#pragma weak PendSV_Handler=Dummy_Handler
+#pragma weak SysTick_Handler=Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak SUPC_Handler=Dummy_Handler
+#pragma weak RSTC_Handler=Dummy_Handler
+#pragma weak RTC_Handler=Dummy_Handler
+#pragma weak RTT_Handler=Dummy_Handler
+#pragma weak WDT_Handler=Dummy_Handler
+#pragma weak PMC_Handler=Dummy_Handler
+#pragma weak EFC_Handler=Dummy_Handler
+#pragma weak UART0_Handler=Dummy_Handler
+#pragma weak UART1_Handler=Dummy_Handler
+#pragma weak PIOA_Handler=Dummy_Handler
+#pragma weak PIOB_Handler=Dummy_Handler
+#ifdef _SAM3N_PIOC_INSTANCE_
+#pragma weak PIOC_Handler=Dummy_Handler
+#endif /* _SAM3N_PIOC_INSTANCE_ */
+#pragma weak USART0_Handler=Dummy_Handler
+#ifdef _SAM3N_USART1_INSTANCE_
+#pragma weak USART1_Handler=Dummy_Handler
+#endif /* _SAM3N_USART1_INSTANCE_ */
+#pragma weak TWI0_Handler=Dummy_Handler
+#pragma weak TWI1_Handler=Dummy_Handler
+#pragma weak SPI_Handler=Dummy_Handler
+#pragma weak TC0_Handler=Dummy_Handler
+#pragma weak TC1_Handler=Dummy_Handler
+#pragma weak TC2_Handler=Dummy_Handler
+#ifdef _SAM3N_TC1_INSTANCE_
+#pragma weak TC3_Handler=Dummy_Handler
+#pragma weak TC4_Handler=Dummy_Handler
+#pragma weak TC5_Handler=Dummy_Handler
+#endif /* _SAM3N_TC1_INSTANCE_ */
+#pragma weak ADC_Handler=Dummy_Handler
+#pragma weak DACC_Handler=Dummy_Handler
+#pragma weak PWM_Handler=Dummy_Handler
+
+/* Exception Table */
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section = ".intvec"
+#pragma location = ".intvec"
+const DeviceVectors __vector_table[] = {
+	(void*) (&__cstack_end__),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+	(void*) (0UL),           /* 10 Reserved */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3N_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3S_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM3N_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3N_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+	(void*) (0UL),           /* 18 Reserved */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+ 	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) (0UL),           /* 22 Reserved */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3N_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+ 	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3N_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler      /* 31 PWM */
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+	uint32_t *pSrc = __section_begin(".intvec");
+
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+	__iar_program_start();
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/system_sam3n.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/system_sam3n.c
new file mode 100644
index 0000000..5238e96
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3n/source/system_sam3n.c
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3n.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Clock settings (48MHz) */
+#define SYS_BOARD_OSCOUNT   (CKGR_MOR_MOSCXTST(0x8UL))
+#define SYS_BOARD_PLLAR		(CKGR_PLLAR_ONE \
+							| CKGR_PLLAR_MULA(0x7UL) \
+							| CKGR_PLLAR_PLLACOUNT(0x3fUL) \
+							| CKGR_PLLAR_DIVA(0x1UL))
+#define SYS_BOARD_MCKR      (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)
+
+#define SYS_CKGR_MOR_KEY_VALUE	CKGR_MOR_KEY(0x37UL) /* Key to unlock MOR register */
+
+/* FIXME: should be generated by sock */
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+/**
+ * \brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit(void)
+{
+	/* Set FWS according to SYS_BOARD_MCKR configuration */
+	EFC->EEFC_FMR = EEFC_FMR_FWS(3);
+
+	/* Initialize main oscillator */
+	if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
+		PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
+			                     CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+		while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
+		}
+	}
+
+	/* Switch to 3-20MHz Xtal oscillator */
+	PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
+	CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+
+	while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
+	}
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) |
+		                    PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Initialize PLL */
+	PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
+	while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
+	}
+
+	/* Switch to main clock */
+	PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Switch to PLLA */
+	PMC->PMC_MCKR = SYS_BOARD_MCKR;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	SystemCoreClock = CHIP_FREQ_CPU_MAX;
+}
+
+void SystemCoreClockUpdate(void)
+{
+	/* Determine clock frequency according to clock register values */
+	switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
+	case PMC_MCKR_CSS_SLOW_CLK:	/* Slow clock */
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_32K;
+		} else {
+			SystemCoreClock = CHIP_FREQ_SLCK_RC;
+		}
+		break;
+	case PMC_MCKR_CSS_MAIN_CLK:	/* Main clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	case PMC_MCKR_CSS_PLLA_CLK:	/* PLLA clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
+			                         CKGR_PLLAR_MULA_Pos) + 1U);
+		SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
+			                         CKGR_PLLAR_DIVA_Pos));
+		break;
+	default:
+		break;
+	}
+
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
+		SystemCoreClock /= 3U;
+	} else {
+		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
+	}
+}
+
+/**
+ * Initialize flash.
+ */
+void system_init_flash(uint32_t dw_clk)
+{
+	/* Set FWS for embedded Flash access according to operating frequency */
+	if (dw_clk < CHIP_FREQ_FWS_0) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(0);
+	} else if (dw_clk < CHIP_FREQ_FWS_1) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(1);
+	} else if (dw_clk < CHIP_FREQ_FWS_2) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(2);
+	} else {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(3);
+	}
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_acc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_acc.h
new file mode 100644
index 0000000..dcda142
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_acc.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_ACC_COMPONENT_
+#define _SAM3S_ACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog Comparator Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_ACC Analog Comparator Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Acc hardware registers */
+typedef struct {
+  WoReg ACC_CR;        /**< \brief (Acc Offset: 0x00) Control Register */
+  RwReg ACC_MR;        /**< \brief (Acc Offset: 0x04) Mode Register */
+  RoReg Reserved1[7];
+  WoReg ACC_IER;       /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */
+  WoReg ACC_IDR;       /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */
+  RoReg ACC_IMR;       /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ACC_ISR;       /**< \brief (Acc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[24];
+  RwReg ACC_ACR;       /**< \brief (Acc Offset: 0x94) Analog Control Register */
+  RoReg Reserved3[19];
+  RwReg ACC_WPMR;      /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ACC_WPSR;      /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */
+} Acc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
+#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) SoftWare ReSeT */
+/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
+#define ACC_MR_SELMINUS_Pos 0
+#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) SELection for MINUS comparator input */
+#define   ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) SelectTS */
+#define   ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */
+#define   ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */
+#define   ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */
+#define   ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */
+#define   ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */
+#define   ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */
+#define   ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */
+#define ACC_MR_SELPLUS_Pos 4
+#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) SELection for PLUS comparator input */
+#define   ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */
+#define   ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */
+#define   ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */
+#define   ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */
+#define   ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */
+#define   ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */
+#define   ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */
+#define   ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */
+#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator ENable */
+#define   ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog Comparator Disabled. */
+#define   ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enabled. */
+#define ACC_MR_EDGETYP_Pos 9
+#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) EDGE TYPe */
+#define   ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) only rising edge of comparator output */
+#define   ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) falling edge of comparator output */
+#define   ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) any edge of comparator output */
+#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) INVert comparator output */
+#define   ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog Comparator output is directly processed. */
+#define   ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog Comparator output is inverted prior to being processed. */
+#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) SELection of Fault Source */
+#define   ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) the CF flag is used to drive the FAULT output. */
+#define   ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) the output of the Analog Comparator flag is used to drive the FAULT output. */
+#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */
+#define   ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) the FAULT output is tied to 0. */
+#define   ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) the FAULT output is driven by the signal defined by SELFS. */
+/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
+#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */
+/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
+#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */
+/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */
+/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
+#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */
+#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */
+#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR)  */
+/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
+#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current SELection */
+#define   ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) low power option. */
+#define   ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) high speed option. */
+#define ACC_ACR_HYST_Pos 1
+#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) HYSTeresis selection */
+#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
+/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protect Enable */
+#define ACC_WPMR_WPKEY_Pos 8
+#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protect KEY */
+#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
+/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */
+#define ACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */
+
+/*@}*/
+
+
+#endif /* _SAM3S_ACC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_adc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_adc.h
new file mode 100644
index 0000000..1b6fef5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_adc.h
@@ -0,0 +1,501 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_ADC_COMPONENT_
+#define _SAM3S_ADC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM3S_ADC Analog-to-digital Converter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Adc hardware registers */
+typedef struct {
+  WoReg ADC_CR;        /**< \brief (Adc Offset: 0x00) Control Register */
+  RwReg ADC_MR;        /**< \brief (Adc Offset: 0x04) Mode Register */
+  RwReg ADC_SEQR1;     /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
+  RwReg ADC_SEQR2;     /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
+  WoReg ADC_CHER;      /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+  WoReg ADC_CHDR;      /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+  RoReg ADC_CHSR;      /**< \brief (Adc Offset: 0x18) Channel Status Register */
+  RoReg Reserved1[1];
+  RoReg ADC_LCDR;      /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+  WoReg ADC_IER;       /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC_IDR;       /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC_IMR;       /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC_ISR;       /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[2];
+  RoReg ADC_OVER;      /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
+  RwReg ADC_EMR;       /**< \brief (Adc Offset: 0x40) Extended Mode Register */
+  RwReg ADC_CWR;       /**< \brief (Adc Offset: 0x44) Compare Window Register */
+  RwReg ADC_CGR;       /**< \brief (Adc Offset: 0x48) Channel Gain Register */
+  RwReg ADC_COR;       /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
+  RoReg ADC_CDR[15];   /**< \brief (Adc Offset: 0x50) Channel Data Register */
+  RoReg Reserved3[2];
+  RwReg ADC_ACR;       /**< \brief (Adc Offset: 0x94) Analog Control Register */
+  RoReg Reserved4[19];
+  RwReg ADC_WPMR;      /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ADC_WPSR;      /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved5[5];
+  RwReg ADC_RPR;       /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+  RwReg ADC_RCR;       /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+  RoReg Reserved6[2];
+  RwReg ADC_RNPR;      /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC_RNCR;      /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+  RoReg Reserved7[2];
+  WoReg ADC_PTCR;      /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+  RoReg ADC_PTSR;      /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define   ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define   ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */
+#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */
+#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */
+#define   ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
+#define   ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */
+#define   ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define   ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
+#define   ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
+#define   ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
+#define   ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */
+#define   ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */
+#define   ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define   ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */
+#define ADC_MR_SETTLING_Pos 20
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */
+#define   ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */
+#define   ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */
+#define   ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */
+#define ADC_MR_TRACKTIM_Pos 24
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
+#define ADC_MR_TRANSFER_Pos 28
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
+#define   ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */
+#define   ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
+#define ADC_SEQR1_USCH1_Pos 0
+#define ADC_SEQR1_USCH1_Msk (0x7u << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
+#define ADC_SEQR1_USCH2_Pos 4
+#define ADC_SEQR1_USCH2_Msk (0x7u << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
+#define ADC_SEQR1_USCH3_Pos 8
+#define ADC_SEQR1_USCH3_Msk (0x7u << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
+#define ADC_SEQR1_USCH4_Pos 12
+#define ADC_SEQR1_USCH4_Msk (0x7u << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
+#define ADC_SEQR1_USCH5_Pos 16
+#define ADC_SEQR1_USCH5_Msk (0x7u << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
+#define ADC_SEQR1_USCH6_Pos 20
+#define ADC_SEQR1_USCH6_Msk (0x7u << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
+#define ADC_SEQR1_USCH7_Pos 24
+#define ADC_SEQR1_USCH7_Msk (0x7u << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
+#define ADC_SEQR1_USCH8_Pos 28
+#define ADC_SEQR1_USCH8_Msk (0x7u << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
+#define ADC_SEQR2_USCH9_Pos 0
+#define ADC_SEQR2_USCH9_Msk (0x7u << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
+#define ADC_SEQR2_USCH10_Pos 4
+#define ADC_SEQR2_USCH10_Msk (0x7u << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
+#define ADC_SEQR2_USCH11_Pos 8
+#define ADC_SEQR2_USCH11_Msk (0x7u << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
+#define ADC_SEQR2_USCH12_Pos 12
+#define ADC_SEQR2_USCH12_Msk (0x7u << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
+#define ADC_SEQR2_USCH13_Pos 16
+#define ADC_SEQR2_USCH13_Msk (0x7u << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
+#define ADC_SEQR2_USCH14_Pos 20
+#define ADC_SEQR2_USCH14_Msk (0x7u << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
+#define ADC_SEQR2_USCH15_Pos 24
+#define ADC_SEQR2_USCH15_Msk (0x7u << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
+#define ADC_SEQR2_USCH16_Pos 28
+#define ADC_SEQR2_USCH16_Msk (0x7u << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+#define ADC_LCDR_CHNB_Pos 12
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
+#define ADC_EMR_CMPMODE_Pos 0
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
+#define   ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define   ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
+#define   ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
+#define ADC_EMR_CMPSEL_Pos 4
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
+#define ADC_CWR_LOWTHRES_Pos 0
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
+#define ADC_CWR_HIGHTHRES_Pos 16
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
+#define ADC_CGR_GAIN0_Pos 0
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))
+#define ADC_CGR_GAIN1_Pos 2
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))
+#define ADC_CGR_GAIN2_Pos 4
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))
+#define ADC_CGR_GAIN3_Pos 6
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))
+#define ADC_CGR_GAIN4_Pos 8
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))
+#define ADC_CGR_GAIN5_Pos 10
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))
+#define ADC_CGR_GAIN6_Pos 12
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))
+#define ADC_CGR_GAIN7_Pos 14
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))
+#define ADC_CGR_GAIN8_Pos 16
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))
+#define ADC_CGR_GAIN9_Pos 18
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))
+#define ADC_CGR_GAIN10_Pos 20
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))
+#define ADC_CGR_GAIN11_Pos 22
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))
+#define ADC_CGR_GAIN12_Pos 24
+#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */
+#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))
+#define ADC_CGR_GAIN13_Pos 26
+#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */
+#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))
+#define ADC_CGR_GAIN14_Pos 28
+#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */
+#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))
+#define ADC_CGR_GAIN15_Pos 30
+#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */
+#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */
+#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */
+#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */
+#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */
+#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */
+#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */
+#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */
+#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */
+#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */
+/* -------- ADC_CDR[15] : (ADC Offset: 0x50) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[15]) Converted Data */
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
+#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */
+#define ADC_ACR_IBCTL_Pos 8
+#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */
+#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
+#define ADC_WPMR_WPKEY_Pos 8
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
+#define ADC_WPSR_WPVSRC_Pos 8
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_ADC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_chipid.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_chipid.h
new file mode 100644
index 0000000..c5e9801
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_chipid.h
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_CHIPID_COMPONENT_
+#define _SAM3S_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM3S_CHIPID Chip Identifier */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Chipid hardware registers */
+typedef struct {
+  RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+  RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define   CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define   CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define   CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define   CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define   CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define   CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define   CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define   CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define   CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define   CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define   CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define   CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
+#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAM3S_CHIPID_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_crccu.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_crccu.h
new file mode 100644
index 0000000..2e5d553
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_crccu.h
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_CRCCU_COMPONENT_
+#define _SAM3S_CRCCU_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */
+/* ============================================================================= */
+/** \addtogroup SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Crccu hardware registers */
+typedef struct {
+  RwReg CRCCU_DSCR;    /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */
+  RoReg Reserved1[1];
+  WoReg CRCCU_DMA_EN;  /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */
+  WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */
+  RoReg CRCCU_DMA_SR;  /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */
+  WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */
+  WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */
+  RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */
+  RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */
+  RoReg Reserved2[4];
+  WoReg CRCCU_CR;      /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */
+  RwReg CRCCU_MR;      /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */
+  RoReg CRCCU_SR;      /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */
+  WoReg CRCCU_IER;     /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */
+  WoReg CRCCU_IDR;     /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */
+  RoReg CRCCU_IMR;     /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */
+  RoReg CRCCU_ISR;     /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */
+} Crccu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */
+#define CRCCU_DSCR_DSCR_Pos 9
+#define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */
+#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos)))
+/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */
+#define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */
+/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */
+#define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */
+/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */
+#define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */
+/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */
+#define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */
+/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */
+#define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */
+/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */
+#define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */
+/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */
+#define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */
+/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */
+#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */
+/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */
+#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */
+#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */
+#define CRCCU_MR_PTYPE_Pos 2
+#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */
+#define   CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */
+#define   CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */
+#define   CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */
+#define CRCCU_MR_DIVIDER_Pos 4
+#define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */
+#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)))
+/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */
+#define CRCCU_SR_CRC_Pos 0
+#define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */
+/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */
+#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */
+/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */
+#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */
+/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */
+#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */
+/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */
+#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */
+
+/*@}*/
+
+
+#endif /* _SAM3S_CRCCU_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_dacc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_dacc.h
new file mode 100644
index 0000000..e8b26a3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_dacc.h
@@ -0,0 +1,210 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_DACC_COMPONENT_
+#define _SAM3S_DACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_DACC Digital-to-Analog Converter Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Dacc hardware registers */
+typedef struct {
+  WoReg DACC_CR;       /**< \brief (Dacc Offset: 0x00) Control Register */
+  RwReg DACC_MR;       /**< \brief (Dacc Offset: 0x04) Mode Register */
+  RoReg Reserved1[2];
+  WoReg DACC_CHER;     /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
+  WoReg DACC_CHDR;     /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
+  RoReg DACC_CHSR;     /**< \brief (Dacc Offset: 0x18) Channel Status Register */
+  RoReg Reserved2[1];
+  WoReg DACC_CDR;      /**< \brief (Dacc Offset: 0x20) Conversion Data Register */
+  WoReg DACC_IER;      /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
+  WoReg DACC_IDR;      /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
+  RoReg DACC_IMR;      /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
+  RoReg DACC_ISR;      /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved3[24];
+  RwReg DACC_ACR;      /**< \brief (Dacc Offset: 0x94) Analog Current Register */
+  RoReg Reserved4[19];
+  RwReg DACC_WPMR;     /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */
+  RoReg DACC_WPSR;     /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */
+  RoReg Reserved5[7];
+  RwReg DACC_TPR;      /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
+  RwReg DACC_TCR;      /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
+  RoReg Reserved6[2];
+  RwReg DACC_TNPR;     /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg DACC_TNCR;     /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg DACC_PTCR;     /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
+  RoReg DACC_PTSR;     /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
+} Dacc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
+#define   DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */
+#define   DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */
+#define DACC_MR_TRGSEL_Pos 1
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define   DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */
+#define   DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */
+#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */
+#define DACC_MR_REFRESH_Pos 8
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
+#define DACC_MR_USER_SEL_Pos 16
+#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */
+#define   DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */
+#define   DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */
+#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */
+#define   DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */
+#define   DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */
+#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */
+#define   DACC_MR_MAXS_NORMAL (0x0u << 21) /**< \brief (DACC_MR) Normal Mode */
+#define   DACC_MR_MAXS_MAXIMUM (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode enabled */
+#define DACC_MR_STARTUP_Pos 24
+#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
+#define   DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */
+#define   DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */
+#define   DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */
+#define   DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */
+#define   DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */
+#define   DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */
+#define   DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */
+#define   DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */
+#define   DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */
+#define   DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */
+#define   DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */
+#define   DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */
+#define   DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */
+#define   DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */
+#define   DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */
+#define   DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */
+#define   DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */
+#define   DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */
+#define   DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */
+#define   DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */
+#define   DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */
+#define   DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */
+#define   DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */
+#define   DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */
+#define   DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */
+#define   DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */
+#define   DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */
+#define   DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */
+#define   DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */
+#define   DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */
+#define   DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */
+#define   DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
+/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */
+#define DACC_CDR_DATA_Pos 0
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */
+#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */
+#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */
+#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */
+#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */
+#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */
+#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */
+#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */
+#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */
+#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */
+#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */
+#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */
+#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
+#define DACC_ACR_IBCTLCH0_Pos 0
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
+#define DACC_ACR_IBCTLCH1_Pos 2
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
+#define DACC_ACR_IBCTLDACCORE_Pos 8
+#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */
+#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
+#define DACC_WPMR_WPKEY_Pos 8
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
+#define DACC_WPSR_WPROTADDR_Pos 8
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
+#define DACC_TPR_TXPTR_Pos 0
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
+#define DACC_TCR_TXCTR_Pos 0
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define DACC_TNPR_TXNPTR_Pos 0
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define DACC_TNCR_TXNCTR_Pos 0
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_DACC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_efc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_efc.h
new file mode 100644
index 0000000..7875ccb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_efc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_EFC_COMPONENT_
+#define _SAM3S_EFC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_EFC Embedded Flash Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Efc hardware registers */
+typedef struct {
+  RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+  WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+  RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+  RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+
+#endif /* _SAM3S_EFC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_gpbr.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_gpbr.h
new file mode 100644
index 0000000..fbf477f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_gpbr.h
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_GPBR_COMPONENT_
+#define _SAM3S_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM3S_GPBR General Purpose Backup Register */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Gpbr hardware registers */
+typedef struct {
+  RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S_GPBR_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_hsmci.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_hsmci.h
new file mode 100644
index 0000000..5896931
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_hsmci.h
@@ -0,0 +1,384 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_HSMCI_COMPONENT_
+#define _SAM3S_HSMCI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3S_HSMCI High Speed MultiMedia Card Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Hsmci hardware registers */
+typedef struct {
+  WoReg HSMCI_CR;        /**< \brief (Hsmci Offset: 0x00) Control Register */
+  RwReg HSMCI_MR;        /**< \brief (Hsmci Offset: 0x04) Mode Register */
+  RwReg HSMCI_DTOR;      /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
+  RwReg HSMCI_SDCR;      /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
+  RwReg HSMCI_ARGR;      /**< \brief (Hsmci Offset: 0x10) Argument Register */
+  WoReg HSMCI_CMDR;      /**< \brief (Hsmci Offset: 0x14) Command Register */
+  RwReg HSMCI_BLKR;      /**< \brief (Hsmci Offset: 0x18) Block Register */
+  RwReg HSMCI_CSTOR;     /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
+  RoReg HSMCI_RSPR[4];   /**< \brief (Hsmci Offset: 0x20) Response Register */
+  RoReg HSMCI_RDR;       /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
+  WoReg HSMCI_TDR;       /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
+  RoReg Reserved1[2];
+  RoReg HSMCI_SR;        /**< \brief (Hsmci Offset: 0x40) Status Register */
+  WoReg HSMCI_IER;       /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
+  WoReg HSMCI_IDR;       /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
+  RoReg HSMCI_IMR;       /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved2[1];
+  RwReg HSMCI_CFG;       /**< \brief (Hsmci Offset: 0x54) Configuration Register */
+  RoReg Reserved3[35];
+  RwReg HSMCI_WPMR;      /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
+  RoReg HSMCI_WPSR;      /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved4[5];
+  RwReg HSMCI_RPR;       /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */
+  RwReg HSMCI_RCR;       /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */
+  RwReg HSMCI_TPR;       /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */
+  RwReg HSMCI_TCR;       /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */
+  RwReg HSMCI_RNPR;      /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */
+  RwReg HSMCI_RNCR;      /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */
+  RwReg HSMCI_TNPR;      /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */
+  RwReg HSMCI_TNCR;      /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */
+  WoReg HSMCI_PTCR;      /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */
+  RoReg HSMCI_PTSR;      /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */
+  RoReg Reserved5[54];
+  RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
+} Hsmci;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
+#define HSMCI_MR_CLKDIV_Pos 0
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
+#define HSMCI_MR_PWSDIV_Pos 8
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
+#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
+#define HSMCI_DTOR_DTOCYC_Pos 0
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
+#define HSMCI_DTOR_DTOMUL_Pos 4
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
+#define   HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
+#define   HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
+#define   HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
+#define   HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
+#define   HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
+#define   HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
+#define   HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
+#define   HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
+#define HSMCI_SDCR_SDCSEL_Pos 0
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
+#define   HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
+#define   HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCBUS_Pos 6
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
+#define   HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
+#define   HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
+#define   HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
+#define HSMCI_ARGR_ARG_Pos 0
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
+#define HSMCI_CMDR_CMDNB_Pos 0
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
+#define HSMCI_CMDR_RSPTYP_Pos 6
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
+#define   HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
+#define   HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
+#define   HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
+#define   HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
+#define HSMCI_CMDR_SPCMD_Pos 8
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
+#define   HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
+#define   HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
+#define   HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
+#define   HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
+#define   HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
+#define   HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
+#define   HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
+#define   HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
+#define   HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
+#define   HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
+#define HSMCI_CMDR_TRCMD_Pos 16
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
+#define   HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
+#define   HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
+#define   HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
+#define   HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
+#define   HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
+#define HSMCI_CMDR_TRTYP_Pos 19
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
+#define   HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
+#define   HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
+#define   HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
+#define   HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
+#define   HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
+#define HSMCI_CMDR_IOSPCMD_Pos 24
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
+#define   HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
+#define   HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
+#define   HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
+#define HSMCI_BLKR_BCNT_Pos 0
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
+#define   HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
+#define   HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define   HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BLKLEN_Pos 16
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
+#define HSMCI_CSTOR_CSTOCYC_Pos 0
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
+#define HSMCI_CSTOR_CSTOMUL_Pos 4
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
+#define   HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
+#define   HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
+#define   HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
+#define   HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
+#define   HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
+#define   HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
+#define   HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
+#define   HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
+#define HSMCI_RSPR_RSP_Pos 0
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
+#define HSMCI_RDR_DATA_Pos 0
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
+#define HSMCI_TDR_DATA_Pos 0
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
+#define HSMCI_SR_ENDRX (0x1u << 6) /**< \brief (HSMCI_SR) End of RX Buffer */
+#define HSMCI_SR_ENDTX (0x1u << 7) /**< \brief (HSMCI_SR) End of TX Buffer */
+#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
+#define HSMCI_SR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_SR) RX Buffer Full */
+#define HSMCI_SR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
+#define HSMCI_IER_ENDRX (0x1u << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */
+#define HSMCI_IER_ENDTX (0x1u << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */
+#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
+#define HSMCI_IER_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */
+#define HSMCI_IER_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
+#define HSMCI_IDR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */
+#define HSMCI_IDR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */
+#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
+#define HSMCI_IDR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */
+#define HSMCI_IDR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
+#define HSMCI_IMR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */
+#define HSMCI_IMR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */
+#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
+#define HSMCI_IMR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */
+#define HSMCI_IMR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
+#define HSMCI_WPMR_WP_KEY_Pos 8
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
+#define HSMCI_WPSR_WP_VS_Pos 0
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
+#define   HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
+#define   HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
+#define   HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
+#define   HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
+#define HSMCI_WPSR_WP_VSRC_Pos 8
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
+/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */
+#define HSMCI_RPR_RXPTR_Pos 0
+#define HSMCI_RPR_RXPTR_Msk (0xffffffffu << HSMCI_RPR_RXPTR_Pos) /**< \brief (HSMCI_RPR) Receive Pointer Register */
+#define HSMCI_RPR_RXPTR(value) ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos)))
+/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */
+#define HSMCI_RCR_RXCTR_Pos 0
+#define HSMCI_RCR_RXCTR_Msk (0xffffu << HSMCI_RCR_RXCTR_Pos) /**< \brief (HSMCI_RCR) Receive Counter Register */
+#define HSMCI_RCR_RXCTR(value) ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos)))
+/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */
+#define HSMCI_TPR_TXPTR_Pos 0
+#define HSMCI_TPR_TXPTR_Msk (0xffffffffu << HSMCI_TPR_TXPTR_Pos) /**< \brief (HSMCI_TPR) Transmit Counter Register */
+#define HSMCI_TPR_TXPTR(value) ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos)))
+/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */
+#define HSMCI_TCR_TXCTR_Pos 0
+#define HSMCI_TCR_TXCTR_Msk (0xffffu << HSMCI_TCR_TXCTR_Pos) /**< \brief (HSMCI_TCR) Transmit Counter Register */
+#define HSMCI_TCR_TXCTR(value) ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos)))
+/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */
+#define HSMCI_RNPR_RXNPTR_Pos 0
+#define HSMCI_RNPR_RXNPTR_Msk (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos) /**< \brief (HSMCI_RNPR) Receive Next Pointer */
+#define HSMCI_RNPR_RXNPTR(value) ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos)))
+/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */
+#define HSMCI_RNCR_RXNCTR_Pos 0
+#define HSMCI_RNCR_RXNCTR_Msk (0xffffu << HSMCI_RNCR_RXNCTR_Pos) /**< \brief (HSMCI_RNCR) Receive Next Counter */
+#define HSMCI_RNCR_RXNCTR(value) ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos)))
+/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define HSMCI_TNPR_TXNPTR_Pos 0
+#define HSMCI_TNPR_TXNPTR_Msk (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */
+#define HSMCI_TNPR_TXNPTR(value) ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos)))
+/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define HSMCI_TNCR_TXNCTR_Pos 0
+#define HSMCI_TNCR_TXNCTR_Msk (0xffffu << HSMCI_TNCR_TXNCTR_Pos) /**< \brief (HSMCI_TNCR) Transmit Counter Next */
+#define HSMCI_TNCR_TXNCTR(value) ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos)))
+/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */
+#define HSMCI_PTCR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */
+#define HSMCI_PTCR_RXTDIS (0x1u << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */
+#define HSMCI_PTCR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */
+#define HSMCI_PTCR_TXTDIS (0x1u << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */
+/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */
+#define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */
+#define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_HSMCI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_matrix.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_matrix.h
new file mode 100644
index 0000000..d90018c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_matrix.h
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_MATRIX_COMPONENT_
+#define _SAM3S_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM3S_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Matrix hardware registers */
+typedef struct {
+  RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+  RoReg Reserved1[12];
+  RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+  RoReg Reserved2[11];
+  RwReg MATRIX_PRAS0;   /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+  RoReg Reserved3[1];
+  RwReg MATRIX_PRAS1;   /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+  RoReg Reserved4[1];
+  RwReg MATRIX_PRAS2;   /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+  RoReg Reserved5[1];
+  RwReg MATRIX_PRAS3;   /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+  RoReg Reserved6[1];
+  RwReg MATRIX_PRAS4;   /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
+  RoReg Reserved7[1];
+  RoReg Reserved8[27];
+  RwReg CCFG_SYSIO;     /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */
+  RoReg Reserved9[1];
+  RwReg CCFG_SMCNFCS;   /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */
+  RoReg Reserved10[49];
+  RwReg MATRIX_WPMR;    /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+  RoReg MATRIX_WPSR;    /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[5]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+#define MATRIX_PRAS0_M4PR_Pos 16
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+#define MATRIX_PRAS1_M4PR_Pos 16
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+#define MATRIX_PRAS2_M4PR_Pos 16
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+#define MATRIX_PRAS3_M4PR_Pos 16
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
+#define MATRIX_PRAS4_M0PR_Pos 0
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
+#define MATRIX_PRAS4_M1PR_Pos 4
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
+#define MATRIX_PRAS4_M2PR_Pos 8
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
+#define MATRIX_PRAS4_M3PR_Pos 12
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
+#define MATRIX_PRAS4_M4PR_Pos 16
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */
+#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */
+#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */
+#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */
+#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */
+#define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */
+#define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */
+/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */
+#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3S_MATRIX_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_pdc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_pdc.h
new file mode 100644
index 0000000..22398c0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_pdc.h
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PDC_COMPONENT_
+#define _SAM3S_PDC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_PDC Peripheral DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pdc hardware registers */
+typedef struct {
+  RwReg PERIPH_RPR;  /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
+  RwReg PERIPH_RCR;  /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
+  RwReg PERIPH_TPR;  /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
+  RwReg PERIPH_TCR;  /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
+  RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+  RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+  RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+  RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+  WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+  RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_PDC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_pio.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_pio.h
new file mode 100644
index 0000000..a08fde6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_pio.h
@@ -0,0 +1,1644 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PIO_COMPONENT_
+#define _SAM3S_PIO_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pio hardware registers */
+typedef struct {
+  WoReg PIO_PER;        /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+  WoReg PIO_PDR;        /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+  RoReg PIO_PSR;        /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+  RoReg Reserved1[1];
+  WoReg PIO_OER;        /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+  WoReg PIO_ODR;        /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+  RoReg PIO_OSR;        /**< \brief (Pio Offset: 0x0018) Output Status Register */
+  RoReg Reserved2[1];
+  WoReg PIO_IFER;       /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+  WoReg PIO_IFDR;       /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+  RoReg PIO_IFSR;       /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+  RoReg Reserved3[1];
+  WoReg PIO_SODR;       /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+  WoReg PIO_CODR;       /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+  RwReg PIO_ODSR;       /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+  RoReg PIO_PDSR;       /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+  WoReg PIO_IER;        /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+  WoReg PIO_IDR;        /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+  RoReg PIO_IMR;        /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+  RoReg PIO_ISR;        /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+  WoReg PIO_MDER;       /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+  WoReg PIO_MDDR;       /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+  RoReg PIO_MDSR;       /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+  RoReg Reserved4[1];
+  WoReg PIO_PUDR;       /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+  WoReg PIO_PUER;       /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+  RoReg PIO_PUSR;       /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+  RoReg Reserved5[1];
+  RwReg PIO_ABCDSR[2];  /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
+  RoReg Reserved6[2];
+  WoReg PIO_IFSCDR;     /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */
+  WoReg PIO_IFSCER;     /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */
+  RoReg PIO_IFSCSR;     /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */
+  RwReg PIO_SCDR;       /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+  WoReg PIO_PPDDR;      /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
+  WoReg PIO_PPDER;      /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
+  RoReg PIO_PPDSR;      /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
+  RoReg Reserved7[1];
+  WoReg PIO_OWER;       /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+  WoReg PIO_OWDR;       /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+  RoReg PIO_OWSR;       /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+  RoReg Reserved8[1];
+  WoReg PIO_AIMER;      /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+  WoReg PIO_AIMDR;      /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
+  RoReg PIO_AIMMR;      /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+  RoReg Reserved9[1];
+  WoReg PIO_ESR;        /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+  WoReg PIO_LSR;        /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+  RoReg PIO_ELSR;       /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+  RoReg Reserved10[1];
+  WoReg PIO_FELLSR;     /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
+  WoReg PIO_REHLSR;     /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
+  RoReg PIO_FRLHSR;     /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+  RoReg Reserved11[1];
+  RoReg PIO_LOCKSR;     /**< \brief (Pio Offset: 0x00E0) Lock Status */
+  RwReg PIO_WPMR;       /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PIO_WPSR;       /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved12[5];
+  RwReg PIO_SCHMITT;    /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
+  RoReg Reserved13[19];
+  RwReg PIO_PCMR;       /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */
+  WoReg PIO_PCIER;      /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */
+  WoReg PIO_PCIDR;      /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */
+  RoReg PIO_PCIMR;      /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */
+  RoReg PIO_PCISR;      /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */
+  RoReg PIO_PCRHR;      /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */
+  RwReg PIO_RPR;        /**< \brief (Pio Offset: 0x168) Receive Pointer Register */
+  RwReg PIO_RCR;        /**< \brief (Pio Offset: 0x16C) Receive Counter Register */
+  RoReg Reserved14[2];
+  RwReg PIO_RNPR;       /**< \brief (Pio Offset: 0x178) Receive Next Pointer Register */
+  RwReg PIO_RNCR;       /**< \brief (Pio Offset: 0x17C) Receive Next Counter Register */
+  RoReg Reserved15[2];
+  WoReg PIO_PTCR;       /**< \brief (Pio Offset: 0x188) Transfer Control Register */
+  RoReg PIO_PTSR;       /**< \brief (Pio Offset: 0x18C) Transfer Status Register */
+} Pio;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
+/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
+#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
+#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
+#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
+#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR)  */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
+#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
+#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */
+/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
+#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
+/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
+#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT)  */
+/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */
+#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */
+#define PIO_PCMR_DSIZE_Pos 4
+#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */
+#define   PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a BYTE (8-bit) */
+#define   PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) */
+#define   PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a WORD (32-bit) */
+#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */
+#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */
+#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */
+/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */
+#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */
+#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */
+#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */
+#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */
+/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */
+#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */
+#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */
+#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */
+#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */
+/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */
+#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */
+#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */
+#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */
+#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */
+/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */
+#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */
+#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */
+#define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */
+#define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */
+/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */
+#define PIO_PCRHR_RDATA_Pos 0
+#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */
+/* -------- PIO_RPR : (PIO Offset: 0x168) Receive Pointer Register -------- */
+#define PIO_RPR_RXPTR_Pos 0
+#define PIO_RPR_RXPTR_Msk (0xffffffffu << PIO_RPR_RXPTR_Pos) /**< \brief (PIO_RPR) Receive Pointer Register */
+#define PIO_RPR_RXPTR(value) ((PIO_RPR_RXPTR_Msk & ((value) << PIO_RPR_RXPTR_Pos)))
+/* -------- PIO_RCR : (PIO Offset: 0x16C) Receive Counter Register -------- */
+#define PIO_RCR_RXCTR_Pos 0
+#define PIO_RCR_RXCTR_Msk (0xffffu << PIO_RCR_RXCTR_Pos) /**< \brief (PIO_RCR) Receive Counter Register */
+#define PIO_RCR_RXCTR(value) ((PIO_RCR_RXCTR_Msk & ((value) << PIO_RCR_RXCTR_Pos)))
+/* -------- PIO_RNPR : (PIO Offset: 0x178) Receive Next Pointer Register -------- */
+#define PIO_RNPR_RXNPTR_Pos 0
+#define PIO_RNPR_RXNPTR_Msk (0xffffffffu << PIO_RNPR_RXNPTR_Pos) /**< \brief (PIO_RNPR) Receive Next Pointer */
+#define PIO_RNPR_RXNPTR(value) ((PIO_RNPR_RXNPTR_Msk & ((value) << PIO_RNPR_RXNPTR_Pos)))
+/* -------- PIO_RNCR : (PIO Offset: 0x17C) Receive Next Counter Register -------- */
+#define PIO_RNCR_RXNCTR_Pos 0
+#define PIO_RNCR_RXNCTR_Msk (0xffffu << PIO_RNCR_RXNCTR_Pos) /**< \brief (PIO_RNCR) Receive Next Counter */
+#define PIO_RNCR_RXNCTR(value) ((PIO_RNCR_RXNCTR_Msk & ((value) << PIO_RNCR_RXNCTR_Pos)))
+/* -------- PIO_PTCR : (PIO Offset: 0x188) Transfer Control Register -------- */
+#define PIO_PTCR_RXTEN (0x1u << 0) /**< \brief (PIO_PTCR) Receiver Transfer Enable */
+#define PIO_PTCR_RXTDIS (0x1u << 1) /**< \brief (PIO_PTCR) Receiver Transfer Disable */
+#define PIO_PTCR_TXTEN (0x1u << 8) /**< \brief (PIO_PTCR) Transmitter Transfer Enable */
+#define PIO_PTCR_TXTDIS (0x1u << 9) /**< \brief (PIO_PTCR) Transmitter Transfer Disable */
+/* -------- PIO_PTSR : (PIO Offset: 0x18C) Transfer Status Register -------- */
+#define PIO_PTSR_RXTEN (0x1u << 0) /**< \brief (PIO_PTSR) Receiver Transfer Enable */
+#define PIO_PTSR_TXTEN (0x1u << 8) /**< \brief (PIO_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_PIO_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_pmc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_pmc.h
new file mode 100644
index 0000000..589cd3c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_pmc.h
@@ -0,0 +1,388 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PMC_COMPONENT_
+#define _SAM3S_PMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_PMC Power Management Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pmc hardware registers */
+typedef struct {
+  WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+  WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+  RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+  RoReg Reserved1[1];
+  WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+  WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+  RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+  RoReg Reserved2[1];
+  RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+  RoReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+  RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+  RwReg CKGR_PLLBR;    /**< \brief (Pmc Offset: 0x002C) PLLB Register */
+  RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+  RoReg Reserved3[1];
+  RwReg PMC_USB;       /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
+  RoReg Reserved4[1];
+  RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+  RoReg Reserved5[5];
+  WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+  WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+  RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
+  RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+  RwReg PMC_FSMR;      /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+  RwReg PMC_FSPR;      /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+  WoReg PMC_FOCR;      /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+  RoReg Reserved6[26];
+  RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved7[5];
+  WoReg PMC_PCER1;     /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
+  WoReg PMC_PCDR1;     /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
+  RoReg PMC_PCSR1;     /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
+  RoReg Reserved8[1];
+  RwReg PMC_OCR;       /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */
+} Pmc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */
+#define CKGR_PLLBR_DIVB_Pos 0
+#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */
+#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos)))
+#define CKGR_PLLBR_PLLBCOUNT_Pos 8
+#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */
+#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos)))
+#define CKGR_PLLBR_MULB_Pos 16
+#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */
+#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos)))
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define   PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLBClock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+#define PMC_MCKR_PLLBDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
+#define PMC_USB_USBDIV_Pos 8
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define   PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */
+#define   PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define   PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define   PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define   PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define   PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define   PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define   PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define   PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_LOCKB (0x1u << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_LOCKB (0x1u << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_LOCKB (0x1u << 2) /**< \brief (PMC_SR) PLLB Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_LOCKB (0x1u << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
+/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
+#define PMC_OCR_CAL4_Pos 0
+#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */
+#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
+#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */
+#define PMC_OCR_CAL8_Pos 8
+#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */
+#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
+#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */
+#define PMC_OCR_CAL12_Pos 16
+#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */
+#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
+#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */
+
+/*@}*/
+
+
+#endif /* _SAM3S_PMC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_pwm.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_pwm.h
new file mode 100644
index 0000000..23d1d14
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_pwm.h
@@ -0,0 +1,545 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PWM_COMPONENT_
+#define _SAM3S_PWM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+  RwReg      PWM_CMR;       /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+  RwReg      PWM_CDTY;      /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+  RwReg      PWM_CDTYUPD;   /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
+  RwReg      PWM_CPRD;      /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
+  RwReg      PWM_CPRDUPD;   /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
+  RwReg      PWM_CCNT;      /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
+  RwReg      PWM_DT;        /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
+  RwReg      PWM_DTUPD;     /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
+} PwmCh_num;
+/** \brief PwmCmp hardware registers */
+typedef struct {
+  RwReg      PWM_CMPV;      /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
+  RwReg      PWM_CMPVUPD;   /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
+  RwReg      PWM_CMPM;      /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
+  RwReg      PWM_CMPMUPD;   /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
+} PwmCmp;
+/** \brief Pwm hardware registers */
+#define PWMCMP_NUMBER 8
+#define PWMCH_NUM_NUMBER 4
+typedef struct {
+  RwReg      PWM_CLK;       /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
+  WoReg      PWM_ENA;       /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+  WoReg      PWM_DIS;       /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+  RoReg      PWM_SR;        /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+  WoReg      PWM_IER1;      /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
+  WoReg      PWM_IDR1;      /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
+  RoReg      PWM_IMR1;      /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
+  RoReg      PWM_ISR1;      /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
+  RwReg      PWM_SCM;       /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      PWM_SCUC;      /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
+  RwReg      PWM_SCUP;      /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
+  WoReg      PWM_SCUPUPD;   /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
+  WoReg      PWM_IER2;      /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
+  WoReg      PWM_IDR2;      /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
+  RoReg      PWM_IMR2;      /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
+  RoReg      PWM_ISR2;      /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
+  RwReg      PWM_OOV;       /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
+  RwReg      PWM_OS;        /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
+  WoReg      PWM_OSS;       /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
+  WoReg      PWM_OSC;       /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
+  WoReg      PWM_OSSUPD;    /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
+  WoReg      PWM_OSCUPD;    /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
+  RwReg      PWM_FMR;       /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
+  RoReg      PWM_FSR;       /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
+  WoReg      PWM_FCR;       /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
+  RwReg      PWM_FPV;       /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
+  RwReg      PWM_FPE;       /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
+  RoReg      Reserved2[3];
+  RwReg      PWM_ELMR[2];   /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
+  RoReg      Reserved3[11];
+  RwReg      PWM_SMMR;      /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
+  RoReg      Reserved4[12];
+  WoReg      PWM_WPCR;      /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
+  RoReg      PWM_WPSR;      /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
+  RoReg      Reserved5[7];
+  RwReg      PWM_TPR;       /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
+  RwReg      PWM_TCR;       /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
+  RoReg      Reserved6[2];
+  RwReg      PWM_TNPR;      /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
+  RwReg      PWM_TNCR;      /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
+  WoReg      PWM_PTCR;      /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
+  RoReg      PWM_PTSR;      /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
+  RoReg      Reserved7[2];
+  PwmCmp     PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
+  RoReg      Reserved8[20];
+  PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
+} Pwm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
+#define PWM_CLK_DIVA_Pos 0
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
+#define PWM_CLK_PREA_Pos 8
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
+#define PWM_CLK_DIVB_Pos 16
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
+#define PWM_CLK_PREB_Pos 24
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
+#define PWM_SCM_UPDM_Pos 16
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
+#define   PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
+#define PWM_SCM_PTRCS_Pos 21
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
+#define PWM_SCUP_UPR_Pos 0
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
+#define PWM_SCUP_UPRCNT_Pos 4
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
+#define PWM_SCUPUPD_UPRUPD_Pos 0
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
+#define PWM_FMR_FPOL_Pos 0
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
+#define PWM_FMR_FMOD_Pos 8
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
+#define PWM_FMR_FFIL_Pos 16
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
+#define PWM_FSR_FIV_Pos 0
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */
+#define PWM_FSR_FS_Pos 8
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
+#define PWM_FCR_FCLR_Pos 0
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
+#define PWM_FPE_FPE0_Pos 0
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
+#define PWM_FPE_FPE1_Pos 8
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
+#define PWM_FPE_FPE2_Pos 16
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
+#define PWM_FPE_FPE3_Pos 24
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
+#define PWM_WPCR_WPCMD_Pos 0
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
+#define PWM_WPCR_WPKEY_Pos 8
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPVSRC_Pos 16
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
+#define PWM_TPR_TXPTR_Pos 0
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
+#define PWM_TCR_TXCTR_Pos 0
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
+#define PWM_TNPR_TXNPTR_Pos 0
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
+#define PWM_TNCR_TXNCTR_Pos 0
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
+#define PWM_CMPV_CV_Pos 0
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
+#define PWM_CMPVUPD_CVUPD_Pos 0
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
+#define PWM_CMPM_CTR_Pos 4
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
+#define PWM_CMPM_CPR_Pos 8
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
+#define PWM_CMPM_CPRCNT_Pos 12
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
+#define PWM_CMPM_CUPR_Pos 16
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
+#define PWM_CMPM_CUPRCNT_Pos 20
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
+#define PWM_CMPMUPD_CTRUPD_Pos 4
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
+#define PWM_CMPMUPD_CPRUPD_Pos 8
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
+#define PWM_CMPMUPD_CUPRUPD_Pos 16
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
+#define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
+#define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
+#define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
+#define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
+#define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
+#define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
+#define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
+#define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
+#define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
+#define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
+#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
+#define PWM_CDTYUPD_CDTYUPD_Pos 0
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
+#define PWM_CPRDUPD_CPRDUPD_Pos 0
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
+#define PWM_DT_DTH_Pos 0
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
+#define PWM_DT_DTL_Pos 16
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
+#define PWM_DTUPD_DTHUPD_Pos 0
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
+#define PWM_DTUPD_DTLUPD_Pos 16
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S_PWM_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_rstc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_rstc.h
new file mode 100644
index 0000000..2c9c70a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_rstc.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_RSTC_COMPONENT_
+#define _SAM3S_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_RSTC Reset Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rstc hardware registers */
+typedef struct {
+  WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+  RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+  RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S_RSTC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_rtc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_rtc.h
new file mode 100644
index 0000000..380bd51
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_rtc.h
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_RTC_COMPONENT_
+#define _SAM3S_RTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM3S_RTC Real-time Clock */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtc hardware registers */
+typedef struct {
+  RwReg RTC_CR;     /**< \brief (Rtc Offset: 0x00) Control Register */
+  RwReg RTC_MR;     /**< \brief (Rtc Offset: 0x04) Mode Register */
+  RwReg RTC_TIMR;   /**< \brief (Rtc Offset: 0x08) Time Register */
+  RwReg RTC_CALR;   /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+  RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+  RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+  RoReg RTC_SR;     /**< \brief (Rtc Offset: 0x18) Status Register */
+  WoReg RTC_SCCR;   /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+  WoReg RTC_IER;    /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+  WoReg RTC_IDR;    /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+  RoReg RTC_IMR;    /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+  RoReg RTC_VER;    /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+
+/*@}*/
+
+
+#endif /* _SAM3S_RTC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_rtt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_rtt.h
new file mode 100644
index 0000000..fe7dc6f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_rtt.h
@@ -0,0 +1,69 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_RTT_COMPONENT_
+#define _SAM3S_RTT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3S_RTT Real-time Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtt hardware registers */
+typedef struct {
+  RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+  RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+  RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+  RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+
+#endif /* _SAM3S_RTT_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_smc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_smc.h
new file mode 100644
index 0000000..f68b5fb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_smc.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SMC_COMPONENT_
+#define _SAM3S_SMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Static Memory Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_SMC Static Memory Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief SmcCs_number hardware registers */
+typedef struct {
+  RwReg         SMC_SETUP;        /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
+  RwReg         SMC_PULSE;        /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
+  RwReg         SMC_CYCLE;        /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
+  RwReg         SMC_MODE;         /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */
+} SmcCs_number;
+/** \brief Smc hardware registers */
+#define SMCCS_NUMBER_NUMBER 5
+typedef struct {
+  SmcCs_number  SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */
+  RoReg         Reserved1[12];
+  RwReg         SMC_OCMS;         /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */
+  WoReg         SMC_KEY1;         /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */
+  WoReg         SMC_KEY2;         /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */
+  RoReg         Reserved2[22];
+  RwReg         SMC_WPMR;         /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */
+  RoReg         SMC_WPSR;         /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */
+} Smc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
+#define SMC_SETUP_NWE_SETUP_Pos 0
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
+#define SMC_SETUP_NRD_SETUP_Pos 16
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
+#define SMC_PULSE_NWE_PULSE_Pos 0
+#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
+#define SMC_PULSE_NRD_PULSE_Pos 16
+#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
+#define SMC_CYCLE_NWE_CYCLE_Pos 0
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
+#define SMC_CYCLE_NRD_CYCLE_Pos 16
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE)  */
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE)  */
+#define SMC_MODE_EXNW_MODE_Pos 4
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
+#define   SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
+#define   SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
+#define   SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
+#define SMC_MODE_DBW_Pos 12
+#define SMC_MODE_DBW_Msk (0x3u << SMC_MODE_DBW_Pos) /**< \brief (SMC_MODE) Data Bus Width */
+#define   SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
+#define   SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
+#define   SMC_MODE_DBW_32_BIT (0x2u << 12) /**< \brief (SMC_MODE) 32-bit bus */
+#define SMC_MODE_TDF_CYCLES_Pos 16
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
+#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */
+#define SMC_MODE_PS_Pos 28
+#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */
+#define   SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */
+#define   SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */
+#define   SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */
+#define   SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */
+/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
+#define SMC_OCMS_CS0SE (0x1u << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS1SE (0x1u << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS2SE (0x1u << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS3SE (0x1u << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */
+#define SMC_KEY1_KEY1_Pos 0
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
+/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */
+#define SMC_KEY2_KEY2_Pos 0
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
+/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */
+#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */
+#define SMC_WPMR_WPKEY_Pos 8
+#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */
+#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
+/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */
+#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */
+#define SMC_WPSR_WPVSRC_Pos 8
+#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3S_SMC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_spi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_spi.h
new file mode 100644
index 0000000..2c2e800
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_spi.h
@@ -0,0 +1,226 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SPI_COMPONENT_
+#define _SAM3S_SPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3S_SPI Serial Peripheral Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Spi hardware registers */
+typedef struct {
+  WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
+  RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
+  RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
+  WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+  RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
+  WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+  WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+  RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+  RoReg Reserved1[4];
+  RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
+  RoReg Reserved2[41];
+  RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+  RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved3[5];
+  RwReg SPI_RPR;       /**< \brief (Spi Offset: 0x100) Receive Pointer Register */
+  RwReg SPI_RCR;       /**< \brief (Spi Offset: 0x104) Receive Counter Register */
+  RwReg SPI_TPR;       /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */
+  RwReg SPI_TCR;       /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */
+  RwReg SPI_RNPR;      /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */
+  RwReg SPI_RNCR;      /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */
+  RwReg SPI_TNPR;      /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg SPI_TNCR;      /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg SPI_PTCR;      /**< \brief (Spi Offset: 0x120) Transfer Control Register */
+  RoReg SPI_PTSR;      /**< \brief (Spi Offset: 0x124) Transfer Status Register */
+} Spi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */
+#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */
+#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */
+#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */
+#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */
+#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */
+#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */
+#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */
+#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */
+#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */
+#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */
+#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */
+#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */
+#define SPI_WPMR_WPKEY_Pos 8
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */
+#define SPI_WPSR_WPVSRC_Pos 8
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */
+/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */
+#define SPI_RPR_RXPTR_Pos 0
+#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */
+#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))
+/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */
+#define SPI_RCR_RXCTR_Pos 0
+#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */
+#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))
+/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */
+#define SPI_TPR_TXPTR_Pos 0
+#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */
+#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))
+/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */
+#define SPI_TCR_TXCTR_Pos 0
+#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */
+#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))
+/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */
+#define SPI_RNPR_RXNPTR_Pos 0
+#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */
+#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))
+/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */
+#define SPI_RNCR_RXNCTR_Pos 0
+#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */
+#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))
+/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define SPI_TNPR_TXNPTR_Pos 0
+#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */
+#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))
+/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define SPI_TNCR_TXNCTR_Pos 0
+#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */
+#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))
+/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */
+#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */
+#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */
+#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */
+#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */
+/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */
+#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */
+#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_SPI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_ssc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_ssc.h
new file mode 100644
index 0000000..1061f60
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_ssc.h
@@ -0,0 +1,337 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SSC_COMPONENT_
+#define _SAM3S_SSC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_SSC Synchronous Serial Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Ssc hardware registers */
+typedef struct {
+  WoReg SSC_CR;        /**< \brief (Ssc Offset: 0x0) Control Register */
+  RwReg SSC_CMR;       /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
+  RoReg Reserved1[2];
+  RwReg SSC_RCMR;      /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
+  RwReg SSC_RFMR;      /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
+  RwReg SSC_TCMR;      /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
+  RwReg SSC_TFMR;      /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
+  RoReg SSC_RHR;       /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
+  WoReg SSC_THR;       /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
+  RoReg Reserved2[2];
+  RoReg SSC_RSHR;      /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
+  RwReg SSC_TSHR;      /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
+  RwReg SSC_RC0R;      /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
+  RwReg SSC_RC1R;      /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
+  RoReg SSC_SR;        /**< \brief (Ssc Offset: 0x40) Status Register */
+  WoReg SSC_IER;       /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
+  WoReg SSC_IDR;       /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
+  RoReg SSC_IMR;       /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved3[37];
+  RwReg SSC_WPMR;      /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
+  RoReg SSC_WPSR;      /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[5];
+  RwReg SSC_RPR;       /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */
+  RwReg SSC_RCR;       /**< \brief (Ssc Offset: 0x104) Receive Counter Register */
+  RwReg SSC_TPR;       /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */
+  RwReg SSC_TCR;       /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */
+  RwReg SSC_RNPR;      /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */
+  RwReg SSC_RNCR;      /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */
+  RwReg SSC_TNPR;      /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg SSC_TNCR;      /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg SSC_PTCR;      /**< \brief (Ssc Offset: 0x120) Transfer Control Register */
+  RoReg SSC_PTSR;      /**< \brief (Ssc Offset: 0x124) Transfer Status Register */
+} Ssc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
+#define SSC_CMR_DIV_Pos 0
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
+#define SSC_RCMR_CKS_Pos 0
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
+#define   SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
+#define   SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
+#define   SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
+#define SSC_RCMR_CKO_Pos 2
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
+#define   SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
+#define SSC_RCMR_CKG_Pos 6
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
+#define   SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_START_Pos 8
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
+#define   SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define   SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
+#define   SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
+#define   SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
+#define   SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
+#define   SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
+#define   SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
+#define   SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
+#define   SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
+#define SSC_RCMR_STTDLY_Pos 16
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
+#define SSC_RCMR_PERIOD_Pos 24
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
+#define SSC_RFMR_DATLEN_Pos 0
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
+#define SSC_RFMR_DATNB_Pos 8
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
+#define SSC_RFMR_FSLEN_Pos 16
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
+#define SSC_RFMR_FSOS_Pos 20
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
+#define   SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
+#define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
+#define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
+#define   SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
+#define   SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
+#define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
+#define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
+#define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
+#define SSC_RFMR_FSLEN_EXT_Pos 28
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
+#define SSC_TCMR_CKS_Pos 0
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
+#define   SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
+#define   SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
+#define   SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
+#define SSC_TCMR_CKO_Pos 2
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
+#define   SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
+#define   SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
+#define SSC_TCMR_CKG_Pos 6
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
+#define   SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
+#define   SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
+#define SSC_TCMR_START_Pos 8
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
+#define   SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
+#define   SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
+#define   SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
+#define   SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
+#define   SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
+#define   SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
+#define   SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
+#define   SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
+#define   SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
+#define SSC_TCMR_STTDLY_Pos 16
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
+#define SSC_TCMR_PERIOD_Pos 24
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
+#define SSC_TFMR_DATLEN_Pos 0
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
+#define SSC_TFMR_DATNB_Pos 8
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
+#define SSC_TFMR_FSLEN_Pos 16
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
+#define SSC_TFMR_FSOS_Pos 20
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
+#define   SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
+#define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
+#define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
+#define   SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
+#define   SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
+#define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
+#define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
+#define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
+#define SSC_TFMR_FSLEN_EXT_Pos 28
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
+#define SSC_RHR_RDAT_Pos 0
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
+#define SSC_THR_TDAT_Pos 0
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
+#define SSC_RSHR_RSDAT_Pos 0
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
+#define SSC_TSHR_TSDAT_Pos 0
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
+#define SSC_RC0R_CP0_Pos 0
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
+#define SSC_RC1R_CP1_Pos 0
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
+#define SSC_SR_ENDTX (0x1u << 2) /**< \brief (SSC_SR) End of Transmission */
+#define SSC_SR_TXBUFE (0x1u << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
+#define SSC_SR_ENDRX (0x1u << 6) /**< \brief (SSC_SR) End of Reception */
+#define SSC_SR_RXBUFF (0x1u << 7) /**< \brief (SSC_SR) Receive Buffer Full */
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
+#define SSC_IER_ENDTX (0x1u << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */
+#define SSC_IER_TXBUFE (0x1u << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
+#define SSC_IER_ENDRX (0x1u << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */
+#define SSC_IER_RXBUFF (0x1u << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
+#define SSC_IDR_ENDTX (0x1u << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */
+#define SSC_IDR_TXBUFE (0x1u << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
+#define SSC_IDR_ENDRX (0x1u << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */
+#define SSC_IDR_RXBUFF (0x1u << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
+#define SSC_IMR_ENDTX (0x1u << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */
+#define SSC_IMR_TXBUFE (0x1u << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
+#define SSC_IMR_ENDRX (0x1u << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */
+#define SSC_IMR_RXBUFF (0x1u << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
+#define SSC_WPMR_WPKEY_Pos 8
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
+#define SSC_WPSR_WPVSRC_Pos 8
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
+/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */
+#define SSC_RPR_RXPTR_Pos 0
+#define SSC_RPR_RXPTR_Msk (0xffffffffu << SSC_RPR_RXPTR_Pos) /**< \brief (SSC_RPR) Receive Pointer Register */
+#define SSC_RPR_RXPTR(value) ((SSC_RPR_RXPTR_Msk & ((value) << SSC_RPR_RXPTR_Pos)))
+/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */
+#define SSC_RCR_RXCTR_Pos 0
+#define SSC_RCR_RXCTR_Msk (0xffffu << SSC_RCR_RXCTR_Pos) /**< \brief (SSC_RCR) Receive Counter Register */
+#define SSC_RCR_RXCTR(value) ((SSC_RCR_RXCTR_Msk & ((value) << SSC_RCR_RXCTR_Pos)))
+/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */
+#define SSC_TPR_TXPTR_Pos 0
+#define SSC_TPR_TXPTR_Msk (0xffffffffu << SSC_TPR_TXPTR_Pos) /**< \brief (SSC_TPR) Transmit Counter Register */
+#define SSC_TPR_TXPTR(value) ((SSC_TPR_TXPTR_Msk & ((value) << SSC_TPR_TXPTR_Pos)))
+/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */
+#define SSC_TCR_TXCTR_Pos 0
+#define SSC_TCR_TXCTR_Msk (0xffffu << SSC_TCR_TXCTR_Pos) /**< \brief (SSC_TCR) Transmit Counter Register */
+#define SSC_TCR_TXCTR(value) ((SSC_TCR_TXCTR_Msk & ((value) << SSC_TCR_TXCTR_Pos)))
+/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */
+#define SSC_RNPR_RXNPTR_Pos 0
+#define SSC_RNPR_RXNPTR_Msk (0xffffffffu << SSC_RNPR_RXNPTR_Pos) /**< \brief (SSC_RNPR) Receive Next Pointer */
+#define SSC_RNPR_RXNPTR(value) ((SSC_RNPR_RXNPTR_Msk & ((value) << SSC_RNPR_RXNPTR_Pos)))
+/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */
+#define SSC_RNCR_RXNCTR_Pos 0
+#define SSC_RNCR_RXNCTR_Msk (0xffffu << SSC_RNCR_RXNCTR_Pos) /**< \brief (SSC_RNCR) Receive Next Counter */
+#define SSC_RNCR_RXNCTR(value) ((SSC_RNCR_RXNCTR_Msk & ((value) << SSC_RNCR_RXNCTR_Pos)))
+/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define SSC_TNPR_TXNPTR_Pos 0
+#define SSC_TNPR_TXNPTR_Msk (0xffffffffu << SSC_TNPR_TXNPTR_Pos) /**< \brief (SSC_TNPR) Transmit Next Pointer */
+#define SSC_TNPR_TXNPTR(value) ((SSC_TNPR_TXNPTR_Msk & ((value) << SSC_TNPR_TXNPTR_Pos)))
+/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define SSC_TNCR_TXNCTR_Pos 0
+#define SSC_TNCR_TXNCTR_Msk (0xffffu << SSC_TNCR_TXNCTR_Pos) /**< \brief (SSC_TNCR) Transmit Counter Next */
+#define SSC_TNCR_TXNCTR(value) ((SSC_TNCR_TXNCTR_Msk & ((value) << SSC_TNCR_TXNCTR_Pos)))
+/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */
+#define SSC_PTCR_RXTEN (0x1u << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */
+#define SSC_PTCR_RXTDIS (0x1u << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */
+#define SSC_PTCR_TXTEN (0x1u << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */
+#define SSC_PTCR_TXTDIS (0x1u << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */
+/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */
+#define SSC_PTSR_RXTEN (0x1u << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */
+#define SSC_PTSR_TXTEN (0x1u << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_SSC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_supc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_supc.h
new file mode 100644
index 0000000..a4bca3d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_supc.h
@@ -0,0 +1,297 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SUPC_COMPONENT_
+#define _SAM3S_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S_SUPC Supply Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Supc hardware registers */
+typedef struct {
+  WoReg SUPC_CR;   /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+  RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+  RwReg SUPC_MR;   /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+  RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+  RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+  RoReg SUPC_SR;   /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */
+#define   SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */
+#define   SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define   SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define   SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define   SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define   SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define   SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define   SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define   SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define   SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define   SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define   SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define   SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define   SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define   SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define   SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define   SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define   SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Type 0 */
+#define   SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Type 1 */
+#define   SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Type 2 */
+#define   SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Type 3 */
+#define   SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Type 4 */
+#define   SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Type 5 */
+#define   SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Type 6 */
+#define   SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Type 7 */
+#define   SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Type 8 */
+#define   SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Type 9 */
+#define   SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Type 10 */
+#define   SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Type 11 */
+#define   SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Type 12 */
+#define   SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Type 13 */
+#define   SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Type 14 */
+#define   SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Type 15 */
+#define   SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define   SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define   SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define   SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define   SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define   SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define   SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define   SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */
+#define   SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define   SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+
+#endif /* _SAM3S_SUPC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_tc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_tc.h
new file mode 100644
index 0000000..9dad489
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_tc.h
@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_TC_COMPONENT_
+#define _SAM3S_TC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM3S_TC Timer Counter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief TcChannel hardware registers */
+typedef struct {
+  RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+  RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+  RwReg      TC_SMMR;       /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
+  RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
+  RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
+  RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
+  RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
+  RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+  RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+  RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+  RoReg      Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+  TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+  WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
+  RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+  WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+  WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+  RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+  RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+  RwReg      TC_FMR;        /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
+  RoReg      Reserved1[2];
+  RwReg      TC_WPMR;       /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
+#define TC_WPMR_WPKEY_Pos 8
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S_TC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_twi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_twi.h
new file mode 100644
index 0000000..bee1295
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_twi.h
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_TWI_COMPONENT_
+#define _SAM3S_TWI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3S_TWI Two-wire Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Twi hardware registers */
+typedef struct {
+  WoReg TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
+  RwReg TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
+  RwReg TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+  RwReg TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+  RwReg TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+  RoReg Reserved1[3];
+  RoReg TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
+  WoReg TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+  WoReg TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+  RoReg TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+  RoReg TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+  WoReg TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+  RoReg Reserved2[50];
+  RwReg TWI_RPR;       /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+  RwReg TWI_RCR;       /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+  RwReg TWI_TPR;       /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+  RwReg TWI_TCR;       /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+  RwReg TWI_RNPR;      /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+  RwReg TWI_RNCR;      /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+  RwReg TWI_TNPR;      /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg TWI_TNCR;      /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg TWI_PTCR;      /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+  RoReg TWI_PTSR;      /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_TWI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_uart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_uart.h
new file mode 100644
index 0000000..46ff0ce
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_uart.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_UART_COMPONENT_
+#define _SAM3S_UART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3S_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Uart hardware registers */
+typedef struct {
+  WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
+  RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
+  WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+  WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+  RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+  RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
+  RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+  WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+  RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+  RoReg Reserved1[55];
+  RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+  RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+  RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+  RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+  RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+  RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+  RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+  RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_UART_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_udp.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_udp.h
new file mode 100644
index 0000000..1c0ec45
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_udp.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_UDP_COMPONENT_
+#define _SAM3S_UDP_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR USB Device Port */
+/* ============================================================================= */
+/** \addtogroup SAM3S_UDP USB Device Port */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Udp hardware registers */
+typedef struct {
+  RoReg UDP_FRM_NUM;  /**< \brief (Udp Offset: 0x000) Frame Number Register */
+  RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */
+  RwReg UDP_FADDR;    /**< \brief (Udp Offset: 0x008) Function Address Register */
+  RoReg Reserved1[1];
+  WoReg UDP_IER;      /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */
+  WoReg UDP_IDR;      /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */
+  RoReg UDP_IMR;      /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */
+  RoReg UDP_ISR;      /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */
+  WoReg UDP_ICR;      /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */
+  RoReg Reserved2[1];
+  RwReg UDP_RST_EP;   /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */
+  RoReg Reserved3[1];
+  RwReg UDP_CSR[8];   /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */
+  RwReg UDP_FDR[8];   /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */
+  RoReg Reserved4[1];
+  RwReg UDP_TXVC;     /**< \brief (Udp Offset: 0x074) Transceiver Control Register */
+} Udp;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */
+#define UDP_FRM_NUM_FRM_NUM_Pos 0
+#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */
+#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */
+#define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */
+/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */
+#define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */
+#define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */
+#define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */
+#define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT)  */
+#define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */
+/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */
+#define UDP_FADDR_FADD_Pos 0
+#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */
+#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos)))
+#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */
+#define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */
+#define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */
+#define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */
+#define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */
+#define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */
+#define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */
+#define UDP_IER_EP6INT (0x1u << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */
+#define UDP_IER_EP7INT (0x1u << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */
+#define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */
+#define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */
+#define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER)  */
+#define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */
+#define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */
+#define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */
+#define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */
+#define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */
+#define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */
+#define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */
+#define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */
+#define UDP_IDR_EP6INT (0x1u << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */
+#define UDP_IDR_EP7INT (0x1u << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */
+#define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */
+#define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */
+#define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR)  */
+#define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */
+#define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */
+/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */
+#define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */
+#define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */
+#define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */
+#define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */
+#define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */
+#define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */
+#define UDP_IMR_EP6INT (0x1u << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */
+#define UDP_IMR_EP7INT (0x1u << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */
+#define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */
+#define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */
+#define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR)  */
+#define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */
+#define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */
+#define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */
+/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */
+#define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */
+#define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */
+#define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */
+#define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */
+#define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */
+#define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */
+#define UDP_ISR_EP6INT (0x1u << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */
+#define UDP_ISR_EP7INT (0x1u << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */
+#define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */
+#define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
+#define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR)  */
+#define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */
+#define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */
+#define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
+/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */
+#define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */
+#define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */
+#define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR)  */
+#define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */
+#define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */
+#define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */
+/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */
+#define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */
+#define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */
+#define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */
+#define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */
+#define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */
+#define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */
+#define UDP_RST_EP_EP6 (0x1u << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */
+#define UDP_RST_EP_EP7 (0x1u << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */
+/* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */
+#define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */
+#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */
+#define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[8]) Received Setup */
+#define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */
+#define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */
+#define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */
+#define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */
+#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */
+#define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */
+#define UDP_CSR_EPTYPE_Pos 8
+#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */
+#define   UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */
+#define   UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */
+#define   UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */
+#define   UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */
+#define   UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */
+#define   UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */
+#define   UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */
+#define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[8]) Data Toggle */
+#define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */
+#define UDP_CSR_RXBYTECNT_Pos 16
+#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */
+#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos)))
+/* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */
+#define UDP_FDR_FIFO_DATA_Pos 0
+#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[8]) FIFO Data Value */
+#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos)))
+/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */
+#define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */
+#define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pullup On */
+
+/*@}*/
+
+
+#endif /* _SAM3S_UDP_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_usart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_usart.h
new file mode 100644
index 0000000..d63946d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_usart.h
@@ -0,0 +1,361 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_USART_COMPONENT_
+#define _SAM3S_USART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Usart hardware registers */
+typedef struct {
+  WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
+  RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
+  WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+  WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+  RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+  RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+  RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+  WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+  RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+  RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+  RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+  RoReg Reserved1[5];
+  RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+  RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+  RoReg Reserved2[1];
+  RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+  RwReg US_MAN;        /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
+  RoReg Reserved3[36];
+  RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+  RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[4];
+  RoReg US_VERSION;    /**< \brief (Usart Offset: 0xFC) Version Register */
+  RwReg US_RPR;        /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+  RwReg US_RCR;        /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+  RwReg US_TPR;        /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+  RwReg US_TCR;        /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+  RwReg US_RNPR;       /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+  RwReg US_RNCR;       /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+  RwReg US_TNPR;       /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg US_TNCR;       /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg US_PTCR;       /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+  RoReg US_PTSR;       /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */
+#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
+#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define   US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */
+#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
+#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */
+#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */
+#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
+#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */
+#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */
+#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
+#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */
+#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */
+#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
+#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */
+#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */
+#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */
+#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */
+#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
+#define US_MAN_TX_PL_Pos 0
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
+#define US_MAN_TX_PP_Pos 8
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
+#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
+#define US_MAN_RX_PL_Pos 16
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
+#define US_MAN_RX_PP_Pos 24
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
+#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN)  */
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */
+#define US_VERSION_VERSION_Pos 0
+#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION)  */
+#define US_VERSION_MFN_Pos 16
+#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION)  */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S_USART_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_wdt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_wdt.h
new file mode 100644
index 0000000..eba11d1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/component/component_wdt.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_WDT_COMPONENT_
+#define _SAM3S_WDT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3S_WDT Watchdog Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Wdt hardware registers */
+typedef struct {
+  WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+  RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+  RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAM3S_WDT_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_acc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_acc.h
new file mode 100644
index 0000000..cfd7e2b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_acc.h
@@ -0,0 +1,56 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_ACC_INSTANCE_
+#define _SAM3S_ACC_INSTANCE_
+
+/* ========== Register definition for ACC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ACC_CR            (0x40040000U) /**< \brief (ACC) Control Register */
+#define REG_ACC_MR            (0x40040004U) /**< \brief (ACC) Mode Register */
+#define REG_ACC_IER           (0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
+#define REG_ACC_IDR           (0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
+#define REG_ACC_IMR           (0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
+#define REG_ACC_ISR           (0x40040030U) /**< \brief (ACC) Interrupt Status Register */
+#define REG_ACC_ACR           (0x40040094U) /**< \brief (ACC) Analog Control Register */
+#define REG_ACC_WPMR          (0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
+#define REG_ACC_WPSR          (0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
+#else
+#define REG_ACC_CR   (*(WoReg*)0x40040000U) /**< \brief (ACC) Control Register */
+#define REG_ACC_MR   (*(RwReg*)0x40040004U) /**< \brief (ACC) Mode Register */
+#define REG_ACC_IER  (*(WoReg*)0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
+#define REG_ACC_IDR  (*(WoReg*)0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
+#define REG_ACC_IMR  (*(RoReg*)0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
+#define REG_ACC_ISR  (*(RoReg*)0x40040030U) /**< \brief (ACC) Interrupt Status Register */
+#define REG_ACC_ACR  (*(RwReg*)0x40040094U) /**< \brief (ACC) Analog Control Register */
+#define REG_ACC_WPMR (*(RwReg*)0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
+#define REG_ACC_WPSR (*(RoReg*)0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_ACC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_adc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_adc.h
new file mode 100644
index 0000000..852b366
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_adc.h
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_ADC_INSTANCE_
+#define _SAM3S_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CR               (0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR               (0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1            (0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2            (0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER             (0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR             (0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR             (0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR             (0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER              (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR              (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR              (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR              (0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER             (0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR              (0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR              (0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR              (0x40038048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR              (0x4003804CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR              (0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR              (0x40038094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR             (0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR             (0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR              (0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR              (0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR             (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR             (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR             (0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR             (0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#else
+#define REG_ADC_CR      (*(WoReg*)0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR      (*(RwReg*)0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1   (*(RwReg*)0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2   (*(RwReg*)0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER    (*(WoReg*)0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR    (*(WoReg*)0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR    (*(RoReg*)0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR    (*(RoReg*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER     (*(WoReg*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR     (*(WoReg*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR     (*(RoReg*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR     (*(RoReg*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER    (*(RoReg*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR     (*(RwReg*)0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR     (*(RwReg*)0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR     (*(RwReg*)0x40038048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR     (*(RwReg*)0x4003804CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR     (*(RoReg*)0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR     (*(RwReg*)0x40038094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR    (*(RwReg*)0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR    (*(RoReg*)0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR     (*(RwReg*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR     (*(RwReg*)0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR    (*(RwReg*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR    (*(RwReg*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR    (*(WoReg*)0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR    (*(RoReg*)0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_ADC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_chipid.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_chipid.h
new file mode 100644
index 0000000..65a250a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_chipid.h
@@ -0,0 +1,42 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_CHIPID_INSTANCE_
+#define _SAM3S_CHIPID_INSTANCE_
+
+/* ========== Register definition for CHIPID peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CHIPID_CIDR          (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID          (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#else
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_CHIPID_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_crccu.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_crccu.h
new file mode 100644
index 0000000..6817ad0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_crccu.h
@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_CRCCU_INSTANCE_
+#define _SAM3S_CRCCU_INSTANCE_
+
+/* ========== Register definition for CRCCU peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CRCCU_DSCR             (0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
+#define REG_CRCCU_DMA_EN           (0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
+#define REG_CRCCU_DMA_DIS          (0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
+#define REG_CRCCU_DMA_SR           (0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
+#define REG_CRCCU_DMA_IER          (0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
+#define REG_CRCCU_DMA_IDR          (0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
+#define REG_CRCCU_DMA_IMR          (0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
+#define REG_CRCCU_DMA_ISR          (0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
+#define REG_CRCCU_CR               (0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
+#define REG_CRCCU_MR               (0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
+#define REG_CRCCU_SR               (0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
+#define REG_CRCCU_IER              (0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
+#define REG_CRCCU_IDR              (0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
+#define REG_CRCCU_IMR              (0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
+#define REG_CRCCU_ISR              (0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
+#else
+#define REG_CRCCU_DSCR    (*(RwReg*)0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
+#define REG_CRCCU_DMA_EN  (*(WoReg*)0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
+#define REG_CRCCU_DMA_DIS (*(WoReg*)0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
+#define REG_CRCCU_DMA_SR  (*(RoReg*)0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
+#define REG_CRCCU_DMA_IER (*(WoReg*)0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
+#define REG_CRCCU_DMA_IDR (*(WoReg*)0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
+#define REG_CRCCU_DMA_IMR (*(RoReg*)0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
+#define REG_CRCCU_DMA_ISR (*(RoReg*)0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
+#define REG_CRCCU_CR      (*(WoReg*)0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
+#define REG_CRCCU_MR      (*(RwReg*)0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
+#define REG_CRCCU_SR      (*(RoReg*)0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
+#define REG_CRCCU_IER     (*(WoReg*)0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
+#define REG_CRCCU_IDR     (*(WoReg*)0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
+#define REG_CRCCU_IMR     (*(RoReg*)0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
+#define REG_CRCCU_ISR     (*(RoReg*)0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_CRCCU_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_dacc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_dacc.h
new file mode 100644
index 0000000..b513e27
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_dacc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_DACC_INSTANCE_
+#define _SAM3S_DACC_INSTANCE_
+
+/* ========== Register definition for DACC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DACC_CR            (0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR            (0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER          (0x4003C010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR          (0x4003C014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR          (0x4003C018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR           (0x4003C020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER           (0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR           (0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR           (0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR           (0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR           (0x4003C094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR          (0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR          (0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_TPR           (0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR           (0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_TNPR          (0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR          (0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR          (0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR          (0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#else
+#define REG_DACC_CR   (*(WoReg*)0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR   (*(RwReg*)0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER (*(WoReg*)0x4003C010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR (*(WoReg*)0x4003C014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR (*(RoReg*)0x4003C018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR  (*(WoReg*)0x4003C020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER  (*(WoReg*)0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR  (*(WoReg*)0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR  (*(RoReg*)0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR  (*(RoReg*)0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR  (*(RwReg*)0x4003C094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR (*(RwReg*)0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR (*(RoReg*)0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_TPR  (*(RwReg*)0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR  (*(RwReg*)0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_TNPR (*(RwReg*)0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR (*(RwReg*)0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR (*(WoReg*)0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR (*(RoReg*)0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_DACC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_efc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_efc.h
new file mode 100644
index 0000000..a4e6744
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_efc.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_EFC_INSTANCE_
+#define _SAM3S_EFC_INSTANCE_
+
+/* ========== Register definition for EFC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EFC_FMR           (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR           (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR           (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR           (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#else
+#define REG_EFC_FMR  (*(RwReg*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR  (*(WoReg*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR  (*(RoReg*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR  (*(RoReg*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_EFC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_gpbr.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_gpbr.h
new file mode 100644
index 0000000..9e46b65
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_gpbr.h
@@ -0,0 +1,40 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_GPBR_INSTANCE_
+#define _SAM3S_GPBR_INSTANCE_
+
+/* ========== Register definition for GPBR peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GPBR_GPBR            (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#else
+#define REG_GPBR_GPBR   (*(RwReg*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_GPBR_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_hsmci.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_hsmci.h
new file mode 100644
index 0000000..d4cc89f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_hsmci.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_HSMCI_INSTANCE_
+#define _SAM3S_HSMCI_INSTANCE_
+
+/* ========== Register definition for HSMCI peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_HSMCI_CR                 (0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR                 (0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR               (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR               (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR               (0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR               (0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR               (0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR              (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR               (0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR                (0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR                (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR                 (0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER                (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR                (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR                (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_CFG                (0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR               (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR               (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_RPR                (0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
+#define REG_HSMCI_RCR                (0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
+#define REG_HSMCI_TPR                (0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
+#define REG_HSMCI_TCR                (0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
+#define REG_HSMCI_RNPR               (0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
+#define REG_HSMCI_RNCR               (0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
+#define REG_HSMCI_TNPR               (0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
+#define REG_HSMCI_TNCR               (0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
+#define REG_HSMCI_PTCR               (0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
+#define REG_HSMCI_PTSR               (0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
+#define REG_HSMCI_FIFO               (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#else
+#define REG_HSMCI_CR        (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR        (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR      (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR      (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR      (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR      (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR      (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR     (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR      (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR       (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR       (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR        (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER       (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR       (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR       (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_CFG       (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR      (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR      (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_RPR       (*(RwReg*)0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
+#define REG_HSMCI_RCR       (*(RwReg*)0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
+#define REG_HSMCI_TPR       (*(RwReg*)0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
+#define REG_HSMCI_TCR       (*(RwReg*)0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
+#define REG_HSMCI_RNPR      (*(RwReg*)0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
+#define REG_HSMCI_RNCR      (*(RwReg*)0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
+#define REG_HSMCI_TNPR      (*(RwReg*)0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
+#define REG_HSMCI_TNCR      (*(RwReg*)0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
+#define REG_HSMCI_PTCR      (*(WoReg*)0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
+#define REG_HSMCI_PTSR      (*(RoReg*)0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
+#define REG_HSMCI_FIFO      (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_HSMCI_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_matrix.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_matrix.h
new file mode 100644
index 0000000..9b4881f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_matrix.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_MATRIX_INSTANCE_
+#define _SAM3S_MATRIX_INSTANCE_
+
+/* ========== Register definition for MATRIX peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MATRIX_MCFG             (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG             (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0            (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1            (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2            (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3            (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4            (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_CCFG_SYSIO              (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_CCFG_SMCNFCS            (0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */
+#define REG_MATRIX_WPMR             (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR             (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#else
+#define REG_MATRIX_MCFG    (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG    (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0   (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1   (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2   (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3   (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4   (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_CCFG_SYSIO     (*(RwReg*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_CCFG_SMCNFCS   (*(RwReg*)0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */
+#define REG_MATRIX_WPMR    (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR    (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_MATRIX_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_pioa.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_pioa.h
new file mode 100644
index 0000000..3c7da2d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_pioa.h
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PIOA_INSTANCE_
+#define _SAM3S_PIOA_INSTANCE_
+
+/* ========== Register definition for PIOA peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOA_PER                (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR                (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR                (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER                (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR                (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR                (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER               (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR               (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR               (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR               (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR               (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR               (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR               (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER                (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR                (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR                (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR                (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER               (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR               (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR               (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR               (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER               (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR               (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR             (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR             (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER             (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR             (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR               (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR              (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER              (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR              (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER               (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR               (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR               (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER              (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR              (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR              (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR                (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR                (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR               (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR             (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR             (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR             (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR             (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR               (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR               (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT            (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#define REG_PIOA_PCMR               (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
+#define REG_PIOA_PCIER              (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
+#define REG_PIOA_PCIDR              (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
+#define REG_PIOA_PCIMR              (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
+#define REG_PIOA_PCISR              (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
+#define REG_PIOA_PCRHR              (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
+#define REG_PIOA_RPR                (0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */
+#define REG_PIOA_RCR                (0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */
+#define REG_PIOA_RNPR               (0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */
+#define REG_PIOA_RNCR               (0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */
+#define REG_PIOA_PTCR               (0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */
+#define REG_PIOA_PTSR               (0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */
+#else
+#define REG_PIOA_PER       (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR       (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR       (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER       (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR       (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR       (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER      (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR      (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR      (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR      (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR      (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR      (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR      (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER       (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR       (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR       (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR       (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER      (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR      (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR      (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR      (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER      (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR      (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR    (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR    (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER    (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR    (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR      (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR     (*(WoReg*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER     (*(WoReg*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR     (*(RoReg*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER      (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR      (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR      (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER     (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR     (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR     (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR       (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR       (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR      (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR    (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR    (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR    (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR    (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR      (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR      (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT   (*(RwReg*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#define REG_PIOA_PCMR      (*(RwReg*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
+#define REG_PIOA_PCIER     (*(WoReg*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
+#define REG_PIOA_PCIDR     (*(WoReg*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
+#define REG_PIOA_PCIMR     (*(RoReg*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
+#define REG_PIOA_PCISR     (*(RoReg*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
+#define REG_PIOA_PCRHR     (*(RoReg*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
+#define REG_PIOA_RPR       (*(RwReg*)0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */
+#define REG_PIOA_RCR       (*(RwReg*)0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */
+#define REG_PIOA_RNPR      (*(RwReg*)0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */
+#define REG_PIOA_RNCR      (*(RwReg*)0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */
+#define REG_PIOA_PTCR      (*(WoReg*)0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */
+#define REG_PIOA_PTSR      (*(RoReg*)0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_PIOA_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_piob.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_piob.h
new file mode 100644
index 0000000..1d862fb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_piob.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PIOB_INSTANCE_
+#define _SAM3S_PIOB_INSTANCE_
+
+/* ========== Register definition for PIOB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOB_PER                (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR                (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR                (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER                (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR                (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR                (0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER               (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR               (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR               (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR               (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR               (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR               (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR               (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER                (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR                (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR                (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR                (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER               (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR               (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR               (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR               (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER               (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR               (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR             (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR             (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER             (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR             (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR               (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR              (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER              (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR              (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER               (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR               (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR               (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER              (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR              (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR              (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR                (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR                (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR               (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR             (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR             (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR             (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR             (0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR               (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR               (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT            (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#define REG_PIOB_PCMR               (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
+#define REG_PIOB_PCIER              (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
+#define REG_PIOB_PCIDR              (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
+#define REG_PIOB_PCIMR              (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
+#define REG_PIOB_PCISR              (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
+#define REG_PIOB_PCRHR              (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
+#else
+#define REG_PIOB_PER       (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR       (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR       (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER       (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR       (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR       (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER      (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR      (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR      (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR      (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR      (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR      (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR      (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER       (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR       (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR       (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR       (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER      (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR      (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR      (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR      (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER      (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR      (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR    (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR    (*(WoReg*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER    (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR    (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR      (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR     (*(WoReg*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER     (*(WoReg*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR     (*(RoReg*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER      (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR      (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR      (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER     (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR     (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR     (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR       (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR       (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR      (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR    (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR    (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR    (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR    (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR      (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR      (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT   (*(RwReg*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#define REG_PIOB_PCMR      (*(RwReg*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
+#define REG_PIOB_PCIER     (*(WoReg*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
+#define REG_PIOB_PCIDR     (*(WoReg*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
+#define REG_PIOB_PCIMR     (*(RoReg*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
+#define REG_PIOB_PCISR     (*(RoReg*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
+#define REG_PIOB_PCRHR     (*(RoReg*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_PIOB_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_pioc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_pioc.h
new file mode 100644
index 0000000..e4eae81
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_pioc.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PIOC_INSTANCE_
+#define _SAM3S_PIOC_INSTANCE_
+
+/* ========== Register definition for PIOC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOC_PER                (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR                (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR                (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER                (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR                (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR                (0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER               (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR               (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR               (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR               (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR               (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR               (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR               (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER                (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR                (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR                (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR                (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER               (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR               (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR               (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR               (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER               (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR               (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR             (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR             (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER             (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR             (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR               (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR              (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER              (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR              (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER               (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR               (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR               (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER              (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR              (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR              (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR                (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR                (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR               (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR             (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR             (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR             (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR             (0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR               (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR               (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT            (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#define REG_PIOC_PCMR               (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
+#define REG_PIOC_PCIER              (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
+#define REG_PIOC_PCIDR              (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
+#define REG_PIOC_PCIMR              (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
+#define REG_PIOC_PCISR              (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
+#define REG_PIOC_PCRHR              (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
+#else
+#define REG_PIOC_PER       (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR       (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR       (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER       (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR       (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR       (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER      (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR      (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR      (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR      (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR      (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR      (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR      (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER       (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR       (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR       (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR       (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER      (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR      (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR      (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR      (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER      (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR      (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR    (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR    (*(WoReg*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER    (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR    (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR      (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR     (*(WoReg*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER     (*(WoReg*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR     (*(RoReg*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER      (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR      (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR      (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER     (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR     (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR     (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR       (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR       (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR      (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR    (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR    (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR    (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR    (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR      (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR      (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT   (*(RwReg*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#define REG_PIOC_PCMR      (*(RwReg*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
+#define REG_PIOC_PCIER     (*(WoReg*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
+#define REG_PIOC_PCIDR     (*(WoReg*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
+#define REG_PIOC_PCIMR     (*(RoReg*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
+#define REG_PIOC_PCISR     (*(RoReg*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
+#define REG_PIOC_PCRHR     (*(RoReg*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_PIOC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_pmc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_pmc.h
new file mode 100644
index 0000000..0a84edc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_pmc.h
@@ -0,0 +1,90 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PMC_INSTANCE_
+#define _SAM3S_PMC_INSTANCE_
+
+/* ========== Register definition for PMC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PMC_SCER            (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR            (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR            (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0           (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0           (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0           (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR            (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR           (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR          (0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_CKGR_PLLBR          (0x400E042CU) /**< \brief (PMC) PLLB Register */
+#define REG_PMC_MCKR            (0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB             (0x400E0438U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK             (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER             (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR             (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR              (0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR             (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR            (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR            (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR            (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR            (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR            (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1           (0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1           (0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1           (0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_OCR             (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
+#else
+#define REG_PMC_SCER   (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR   (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR   (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0  (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0  (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0  (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR   (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR  (*(RoReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_CKGR_PLLBR (*(RwReg*)0x400E042CU) /**< \brief (PMC) PLLB Register */
+#define REG_PMC_MCKR   (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB    (*(RwReg*)0x400E0438U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK    (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER    (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR    (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR     (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR    (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR   (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR   (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR   (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR   (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR   (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1  (*(WoReg*)0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1  (*(WoReg*)0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1  (*(RoReg*)0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_OCR    (*(RwReg*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_PMC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_pwm.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_pwm.h
new file mode 100644
index 0000000..bf7f3d8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_pwm.h
@@ -0,0 +1,240 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_PWM_INSTANCE_
+#define _SAM3S_PWM_INSTANCE_
+
+/* ========== Register definition for PWM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PWM_CLK               (0x40020000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA               (0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS               (0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR                (0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1              (0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1              (0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1              (0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1              (0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM               (0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC              (0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP              (0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD           (0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2              (0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2              (0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2              (0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2              (0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV               (0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS                (0x40020048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS               (0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC               (0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD            (0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD            (0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR               (0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR               (0x40020060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR               (0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV               (0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE               (0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR              (0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR              (0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR              (0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR              (0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_TPR               (0x40020108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR               (0x4002010CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_TNPR              (0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR              (0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR              (0x40020120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR              (0x40020124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0             (0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0          (0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0             (0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0          (0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1             (0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1          (0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1             (0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1          (0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2             (0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2          (0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2             (0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2          (0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3             (0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3          (0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3             (0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3          (0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4             (0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4          (0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4             (0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4          (0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5             (0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5          (0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5             (0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5          (0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6             (0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6          (0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6             (0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6          (0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7             (0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7          (0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7             (0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7          (0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0              (0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0             (0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0          (0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0             (0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0          (0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0             (0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0               (0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0            (0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1              (0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1             (0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1          (0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1             (0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1          (0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1             (0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1               (0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1            (0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2              (0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2             (0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2          (0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2             (0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2          (0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2             (0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2               (0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2            (0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3              (0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3             (0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3          (0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3             (0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3          (0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3             (0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3               (0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3            (0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#else
+#define REG_PWM_CLK      (*(RwReg*)0x40020000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA      (*(WoReg*)0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS      (*(WoReg*)0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR       (*(RoReg*)0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1     (*(WoReg*)0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1     (*(WoReg*)0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1     (*(RoReg*)0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1     (*(RoReg*)0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM      (*(RwReg*)0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC     (*(RwReg*)0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP     (*(RwReg*)0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD  (*(WoReg*)0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2     (*(WoReg*)0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2     (*(WoReg*)0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2     (*(RoReg*)0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2     (*(RoReg*)0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV      (*(RwReg*)0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS       (*(RwReg*)0x40020048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS      (*(WoReg*)0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC      (*(WoReg*)0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD   (*(WoReg*)0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD   (*(WoReg*)0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR      (*(RwReg*)0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR      (*(RoReg*)0x40020060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR      (*(WoReg*)0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV      (*(RwReg*)0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE      (*(RwReg*)0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR     (*(RwReg*)0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR     (*(RwReg*)0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR     (*(WoReg*)0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR     (*(RoReg*)0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_TPR      (*(RwReg*)0x40020108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR      (*(RwReg*)0x4002010CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_TNPR     (*(RwReg*)0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR     (*(RwReg*)0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR     (*(WoReg*)0x40020120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR     (*(RoReg*)0x40020124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0    (*(RwReg*)0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0    (*(RwReg*)0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1    (*(RwReg*)0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1    (*(RwReg*)0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2    (*(RwReg*)0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2    (*(RwReg*)0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3    (*(RwReg*)0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3    (*(RwReg*)0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4    (*(RwReg*)0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4    (*(RwReg*)0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5    (*(RwReg*)0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5    (*(RwReg*)0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6    (*(RwReg*)0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6    (*(RwReg*)0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7    (*(RwReg*)0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7    (*(RwReg*)0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0     (*(RwReg*)0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0    (*(RwReg*)0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0    (*(RwReg*)0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0    (*(RoReg*)0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0      (*(RwReg*)0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0   (*(WoReg*)0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1     (*(RwReg*)0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1    (*(RwReg*)0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1    (*(RwReg*)0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1    (*(RoReg*)0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1      (*(RwReg*)0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1   (*(WoReg*)0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2     (*(RwReg*)0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2    (*(RwReg*)0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2    (*(RwReg*)0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2    (*(RoReg*)0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2      (*(RwReg*)0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2   (*(WoReg*)0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3     (*(RwReg*)0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3    (*(RwReg*)0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3    (*(RwReg*)0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3    (*(RoReg*)0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3      (*(RwReg*)0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3   (*(WoReg*)0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_PWM_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_rstc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_rstc.h
new file mode 100644
index 0000000..bb3793c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_rstc.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_RSTC_INSTANCE_
+#define _SAM3S_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RSTC_CR          (0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR          (0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR          (0x400E1408U) /**< \brief (RSTC) Mode Register */
+#else
+#define REG_RSTC_CR (*(WoReg*)0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR (*(RoReg*)0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR (*(RwReg*)0x400E1408U) /**< \brief (RSTC) Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_RSTC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_rtc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_rtc.h
new file mode 100644
index 0000000..621e0b3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_rtc.h
@@ -0,0 +1,62 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_RTC_INSTANCE_
+#define _SAM3S_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_CR              (0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR              (0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR            (0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR            (0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR          (0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR          (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR              (0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR            (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER             (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR             (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR             (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER             (0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#else
+#define REG_RTC_CR     (*(RwReg*)0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR     (*(RwReg*)0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR   (*(RwReg*)0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR   (*(RwReg*)0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR (*(RwReg*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR     (*(RoReg*)0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR   (*(WoReg*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER    (*(WoReg*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR    (*(WoReg*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR    (*(RoReg*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER    (*(RoReg*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_RTC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_rtt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_rtt.h
new file mode 100644
index 0000000..cfd84b3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_rtt.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_RTT_INSTANCE_
+#define _SAM3S_RTT_INSTANCE_
+
+/* ========== Register definition for RTT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTT_MR          (0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR          (0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR          (0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR          (0x400E143CU) /**< \brief (RTT) Status Register */
+#else
+#define REG_RTT_MR (*(RwReg*)0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR (*(RwReg*)0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR (*(RoReg*)0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR (*(RoReg*)0x400E143CU) /**< \brief (RTT) Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_RTT_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_smc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_smc.h
new file mode 100644
index 0000000..e806fed
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_smc.h
@@ -0,0 +1,88 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SMC_INSTANCE_
+#define _SAM3S_SMC_INSTANCE_
+
+/* ========== Register definition for SMC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SMC_SETUP0          (0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0          (0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0          (0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_MODE0           (0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1          (0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1          (0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1          (0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_MODE1           (0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2          (0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2          (0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2          (0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_MODE2           (0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3          (0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3          (0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3          (0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_MODE3           (0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4          (0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4          (0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4          (0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_MODE4           (0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_OCMS            (0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */
+#define REG_SMC_KEY1            (0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2            (0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPMR            (0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
+#define REG_SMC_WPSR            (0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */
+#else
+#define REG_SMC_SETUP0 (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0 (*(RwReg*)0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0 (*(RwReg*)0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_MODE0  (*(RwReg*)0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1 (*(RwReg*)0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1 (*(RwReg*)0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1 (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_MODE1  (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2 (*(RwReg*)0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2 (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2 (*(RwReg*)0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_MODE2  (*(RwReg*)0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3 (*(RwReg*)0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3 (*(RwReg*)0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3 (*(RwReg*)0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_MODE3  (*(RwReg*)0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4 (*(RwReg*)0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4 (*(RwReg*)0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4 (*(RwReg*)0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_MODE4  (*(RwReg*)0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_OCMS   (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */
+#define REG_SMC_KEY1   (*(WoReg*)0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2   (*(WoReg*)0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPMR   (*(RwReg*)0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
+#define REG_SMC_WPSR   (*(RoReg*)0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_SMC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_spi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_spi.h
new file mode 100644
index 0000000..5ccd0fb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_spi.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SPI_INSTANCE_
+#define _SAM3S_SPI_INSTANCE_
+
+/* ========== Register definition for SPI peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SPI_CR              (0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR              (0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR             (0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR             (0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR              (0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER             (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR             (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR             (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR             (0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR            (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR            (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR             (0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR             (0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR             (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR             (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR            (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR            (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR            (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR            (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR            (0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR            (0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#else
+#define REG_SPI_CR     (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR     (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR    (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR    (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR     (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER    (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR    (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR    (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR    (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR   (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR   (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR    (*(RwReg*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR    (*(RwReg*)0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR    (*(RwReg*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR    (*(RwReg*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR   (*(RwReg*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR   (*(RwReg*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR   (*(RwReg*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR   (*(RwReg*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR   (*(WoReg*)0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR   (*(RoReg*)0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_SPI_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_ssc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_ssc.h
new file mode 100644
index 0000000..aeabc11
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_ssc.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SSC_INSTANCE_
+#define _SAM3S_SSC_INSTANCE_
+
+/* ========== Register definition for SSC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SSC_CR            (0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR           (0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR          (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR          (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR          (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR          (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR           (0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR           (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR          (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR          (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R          (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R          (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR            (0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER           (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR           (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR           (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR          (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR          (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#define REG_SSC_RPR           (0x40004100U) /**< \brief (SSC) Receive Pointer Register */
+#define REG_SSC_RCR           (0x40004104U) /**< \brief (SSC) Receive Counter Register */
+#define REG_SSC_TPR           (0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
+#define REG_SSC_TCR           (0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
+#define REG_SSC_RNPR          (0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
+#define REG_SSC_RNCR          (0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
+#define REG_SSC_TNPR          (0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
+#define REG_SSC_TNCR          (0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
+#define REG_SSC_PTCR          (0x40004120U) /**< \brief (SSC) Transfer Control Register */
+#define REG_SSC_PTSR          (0x40004124U) /**< \brief (SSC) Transfer Status Register */
+#else
+#define REG_SSC_CR   (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR  (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR  (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR  (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR   (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER  (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR  (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR  (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#define REG_SSC_RPR  (*(RwReg*)0x40004100U) /**< \brief (SSC) Receive Pointer Register */
+#define REG_SSC_RCR  (*(RwReg*)0x40004104U) /**< \brief (SSC) Receive Counter Register */
+#define REG_SSC_TPR  (*(RwReg*)0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
+#define REG_SSC_TCR  (*(RwReg*)0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
+#define REG_SSC_RNPR (*(RwReg*)0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
+#define REG_SSC_RNCR (*(RwReg*)0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
+#define REG_SSC_TNPR (*(RwReg*)0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
+#define REG_SSC_TNCR (*(RwReg*)0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
+#define REG_SSC_PTCR (*(WoReg*)0x40004120U) /**< \brief (SSC) Transfer Control Register */
+#define REG_SSC_PTSR (*(RoReg*)0x40004124U) /**< \brief (SSC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_SSC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_supc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_supc.h
new file mode 100644
index 0000000..e033393
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_supc.h
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_SUPC_INSTANCE_
+#define _SAM3S_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SUPC_CR            (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR          (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR            (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR          (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR          (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR            (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#else
+#define REG_SUPC_CR   (*(WoReg*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR   (*(RwReg*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR (*(RwReg*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR   (*(RoReg*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_SUPC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_tc0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_tc0.h
new file mode 100644
index 0000000..dbb850e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_tc0.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_TC0_INSTANCE_
+#define _SAM3S_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC0_CCR0           (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0           (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0          (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0            (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0            (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0            (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0            (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0            (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0           (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0           (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0           (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1           (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1           (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1          (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1            (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1            (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1            (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1            (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1            (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1           (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1           (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1           (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2           (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2           (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2          (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2            (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2            (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2            (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2            (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2            (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2           (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2           (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2           (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR            (0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR            (0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER           (0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR           (0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR           (0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR           (0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR            (0x400100D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR           (0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#else
+#define REG_TC0_CCR0  (*(WoReg*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0  (*(RwReg*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0 (*(RwReg*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0   (*(RoReg*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0   (*(RwReg*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0   (*(RwReg*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0   (*(RwReg*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0   (*(RoReg*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0  (*(WoReg*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0  (*(WoReg*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0  (*(RoReg*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1  (*(WoReg*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1  (*(RwReg*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1 (*(RwReg*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1   (*(RoReg*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1   (*(RwReg*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1   (*(RwReg*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1   (*(RwReg*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1   (*(RoReg*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1  (*(WoReg*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1  (*(WoReg*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1  (*(RoReg*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2  (*(WoReg*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2  (*(RwReg*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2 (*(RwReg*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2   (*(RoReg*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2   (*(RwReg*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2   (*(RwReg*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2   (*(RwReg*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2   (*(RoReg*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2  (*(WoReg*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2  (*(WoReg*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2  (*(RoReg*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR   (*(WoReg*)0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR   (*(RwReg*)0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER  (*(WoReg*)0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR  (*(WoReg*)0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR  (*(RoReg*)0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR  (*(RoReg*)0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR   (*(RwReg*)0x400100D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR  (*(RwReg*)0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_TC0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_tc1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_tc1.h
new file mode 100644
index 0000000..a1f58bf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_tc1.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_TC1_INSTANCE_
+#define _SAM3S_TC1_INSTANCE_
+
+/* ========== Register definition for TC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC1_CCR0           (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0           (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0          (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0            (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0            (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0            (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0            (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0            (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0           (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0           (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0           (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1           (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1           (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1          (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1            (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1            (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1            (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1            (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1            (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1           (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1           (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1           (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2           (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2           (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2          (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2            (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2            (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2            (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2            (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2            (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2           (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2           (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2           (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR            (0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR            (0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER           (0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR           (0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR           (0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR           (0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR            (0x400140D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR           (0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#else
+#define REG_TC1_CCR0  (*(WoReg*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0  (*(RwReg*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0 (*(RwReg*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0   (*(RoReg*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0   (*(RwReg*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0   (*(RwReg*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0   (*(RwReg*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0   (*(RoReg*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0  (*(WoReg*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0  (*(WoReg*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0  (*(RoReg*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1  (*(WoReg*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1  (*(RwReg*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1 (*(RwReg*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1   (*(RoReg*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1   (*(RwReg*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1   (*(RwReg*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1   (*(RwReg*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1   (*(RoReg*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1  (*(WoReg*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1  (*(WoReg*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1  (*(RoReg*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2  (*(WoReg*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2  (*(RwReg*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2 (*(RwReg*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2   (*(RoReg*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2   (*(RwReg*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2   (*(RwReg*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2   (*(RwReg*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2   (*(RoReg*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2  (*(WoReg*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2  (*(WoReg*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2  (*(RoReg*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR   (*(WoReg*)0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR   (*(RwReg*)0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER  (*(WoReg*)0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR  (*(WoReg*)0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR  (*(RoReg*)0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR  (*(RoReg*)0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR   (*(RwReg*)0x400140D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR  (*(RwReg*)0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_TC1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_twi0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_twi0.h
new file mode 100644
index 0000000..6c9dd2b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_twi0.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_TWI0_INSTANCE_
+#define _SAM3S_TWI0_INSTANCE_
+
+/* ========== Register definition for TWI0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TWI0_CR            (0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR           (0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR           (0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR          (0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR          (0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR            (0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER           (0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR           (0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR           (0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR           (0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR           (0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR           (0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR           (0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR           (0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR           (0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR          (0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR          (0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR          (0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR          (0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR          (0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR          (0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#else
+#define REG_TWI0_CR   (*(WoReg*)0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR  (*(RwReg*)0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR  (*(RwReg*)0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR (*(RwReg*)0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR (*(RwReg*)0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR   (*(RoReg*)0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER  (*(WoReg*)0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR  (*(WoReg*)0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR  (*(RoReg*)0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR  (*(RoReg*)0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR  (*(WoReg*)0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR  (*(RwReg*)0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR  (*(RwReg*)0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR  (*(RwReg*)0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR  (*(RwReg*)0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR (*(RwReg*)0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR (*(RwReg*)0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR (*(RwReg*)0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR (*(RwReg*)0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR (*(WoReg*)0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR (*(RoReg*)0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_TWI0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_twi1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_twi1.h
new file mode 100644
index 0000000..d68887c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_twi1.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_TWI1_INSTANCE_
+#define _SAM3S_TWI1_INSTANCE_
+
+/* ========== Register definition for TWI1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TWI1_CR            (0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR           (0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR           (0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR          (0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR          (0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR            (0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER           (0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR           (0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR           (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR           (0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR           (0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR           (0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR           (0x4001C104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR           (0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR           (0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR          (0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR          (0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR          (0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR          (0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR          (0x4001C120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR          (0x4001C124U) /**< \brief (TWI1) Transfer Status Register */
+#else
+#define REG_TWI1_CR   (*(WoReg*)0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR  (*(RwReg*)0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR  (*(RwReg*)0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR (*(RwReg*)0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR (*(RwReg*)0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR   (*(RoReg*)0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER  (*(WoReg*)0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR  (*(WoReg*)0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR  (*(RoReg*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR  (*(RoReg*)0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR  (*(WoReg*)0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR  (*(RwReg*)0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR  (*(RwReg*)0x4001C104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR  (*(RwReg*)0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR  (*(RwReg*)0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR (*(RwReg*)0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR (*(RwReg*)0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR (*(RwReg*)0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR (*(RwReg*)0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR (*(WoReg*)0x4001C120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR (*(RoReg*)0x4001C124U) /**< \brief (TWI1) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_TWI1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_uart0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_uart0.h
new file mode 100644
index 0000000..3fd61b8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_uart0.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_UART0_INSTANCE_
+#define _SAM3S_UART0_INSTANCE_
+
+/* ========== Register definition for UART0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UART0_CR            (0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR            (0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER           (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR           (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR           (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR            (0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR           (0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR           (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR          (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR           (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR           (0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR           (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR           (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR          (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR          (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR          (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR          (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR          (0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR          (0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#else
+#define REG_UART0_CR   (*(WoReg*)0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR   (*(RwReg*)0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER  (*(WoReg*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR  (*(WoReg*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR  (*(RoReg*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR   (*(RoReg*)0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR  (*(RoReg*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR  (*(WoReg*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR  (*(RwReg*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR  (*(RwReg*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR  (*(RwReg*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR  (*(RwReg*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_UART0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_uart1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_uart1.h
new file mode 100644
index 0000000..38a1824
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_uart1.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_UART1_INSTANCE_
+#define _SAM3S_UART1_INSTANCE_
+
+/* ========== Register definition for UART1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UART1_CR            (0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR            (0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER           (0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR           (0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR           (0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR            (0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR           (0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR           (0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR          (0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#define REG_UART1_RPR           (0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
+#define REG_UART1_RCR           (0x400E0904U) /**< \brief (UART1) Receive Counter Register */
+#define REG_UART1_TPR           (0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
+#define REG_UART1_TCR           (0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
+#define REG_UART1_RNPR          (0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
+#define REG_UART1_RNCR          (0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
+#define REG_UART1_TNPR          (0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
+#define REG_UART1_TNCR          (0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
+#define REG_UART1_PTCR          (0x400E0920U) /**< \brief (UART1) Transfer Control Register */
+#define REG_UART1_PTSR          (0x400E0924U) /**< \brief (UART1) Transfer Status Register */
+#else
+#define REG_UART1_CR   (*(WoReg*)0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR   (*(RwReg*)0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER  (*(WoReg*)0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR  (*(WoReg*)0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR  (*(RoReg*)0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR   (*(RoReg*)0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR  (*(RoReg*)0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR  (*(WoReg*)0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#define REG_UART1_RPR  (*(RwReg*)0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
+#define REG_UART1_RCR  (*(RwReg*)0x400E0904U) /**< \brief (UART1) Receive Counter Register */
+#define REG_UART1_TPR  (*(RwReg*)0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
+#define REG_UART1_TCR  (*(RwReg*)0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
+#define REG_UART1_RNPR (*(RwReg*)0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
+#define REG_UART1_RNCR (*(RwReg*)0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
+#define REG_UART1_TNPR (*(RwReg*)0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
+#define REG_UART1_TNCR (*(RwReg*)0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
+#define REG_UART1_PTCR (*(WoReg*)0x400E0920U) /**< \brief (UART1) Transfer Control Register */
+#define REG_UART1_PTSR (*(RoReg*)0x400E0924U) /**< \brief (UART1) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_UART1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_udp.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_udp.h
new file mode 100644
index 0000000..94cf4b7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_udp.h
@@ -0,0 +1,62 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_UDP_INSTANCE_
+#define _SAM3S_UDP_INSTANCE_
+
+/* ========== Register definition for UDP peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UDP_FRM_NUM           (0x40034000U) /**< \brief (UDP) Frame Number Register */
+#define REG_UDP_GLB_STAT          (0x40034004U) /**< \brief (UDP) Global State Register */
+#define REG_UDP_FADDR             (0x40034008U) /**< \brief (UDP) Function Address Register */
+#define REG_UDP_IER               (0x40034010U) /**< \brief (UDP) Interrupt Enable Register */
+#define REG_UDP_IDR               (0x40034014U) /**< \brief (UDP) Interrupt Disable Register */
+#define REG_UDP_IMR               (0x40034018U) /**< \brief (UDP) Interrupt Mask Register */
+#define REG_UDP_ISR               (0x4003401CU) /**< \brief (UDP) Interrupt Status Register */
+#define REG_UDP_ICR               (0x40034020U) /**< \brief (UDP) Interrupt Clear Register */
+#define REG_UDP_RST_EP            (0x40034028U) /**< \brief (UDP) Reset Endpoint Register */
+#define REG_UDP_CSR               (0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */
+#define REG_UDP_FDR               (0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */
+#define REG_UDP_TXVC              (0x40034074U) /**< \brief (UDP) Transceiver Control Register */
+#else
+#define REG_UDP_FRM_NUM  (*(RoReg*)0x40034000U) /**< \brief (UDP) Frame Number Register */
+#define REG_UDP_GLB_STAT (*(RwReg*)0x40034004U) /**< \brief (UDP) Global State Register */
+#define REG_UDP_FADDR    (*(RwReg*)0x40034008U) /**< \brief (UDP) Function Address Register */
+#define REG_UDP_IER      (*(WoReg*)0x40034010U) /**< \brief (UDP) Interrupt Enable Register */
+#define REG_UDP_IDR      (*(WoReg*)0x40034014U) /**< \brief (UDP) Interrupt Disable Register */
+#define REG_UDP_IMR      (*(RoReg*)0x40034018U) /**< \brief (UDP) Interrupt Mask Register */
+#define REG_UDP_ISR      (*(RoReg*)0x4003401CU) /**< \brief (UDP) Interrupt Status Register */
+#define REG_UDP_ICR      (*(WoReg*)0x40034020U) /**< \brief (UDP) Interrupt Clear Register */
+#define REG_UDP_RST_EP   (*(RwReg*)0x40034028U) /**< \brief (UDP) Reset Endpoint Register */
+#define REG_UDP_CSR      (*(RwReg*)0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */
+#define REG_UDP_FDR      (*(RwReg*)0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */
+#define REG_UDP_TXVC     (*(RwReg*)0x40034074U) /**< \brief (UDP) Transceiver Control Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_UDP_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_usart0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_usart0.h
new file mode 100644
index 0000000..095651c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_usart0.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_USART0_INSTANCE_
+#define _SAM3S_USART0_INSTANCE_
+
+/* ========== Register definition for USART0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART0_CR            (0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR            (0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER           (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR           (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR           (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR           (0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR           (0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR           (0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR          (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR          (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR          (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI          (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER           (0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF            (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN           (0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR          (0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR          (0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_VERSION          (0x400240FCU) /**< \brief (USART0) Version Register */
+#define REG_USART0_RPR           (0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR           (0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR           (0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR           (0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR          (0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR          (0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR          (0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR          (0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR          (0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR          (0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#else
+#define REG_USART0_CR   (*(WoReg*)0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR   (*(RwReg*)0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER  (*(WoReg*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR  (*(WoReg*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR  (*(RoReg*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR  (*(RoReg*)0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR  (*(RoReg*)0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR  (*(WoReg*)0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR (*(RwReg*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR (*(RwReg*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR (*(RwReg*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI (*(RwReg*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER  (*(RoReg*)0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF   (*(RwReg*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN  (*(RwReg*)0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR (*(RwReg*)0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR (*(RoReg*)0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_VERSION (*(RoReg*)0x400240FCU) /**< \brief (USART0) Version Register */
+#define REG_USART0_RPR  (*(RwReg*)0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR  (*(RwReg*)0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR  (*(RwReg*)0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR  (*(RwReg*)0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR (*(RwReg*)0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR (*(RwReg*)0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR (*(RwReg*)0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR (*(RwReg*)0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR (*(WoReg*)0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR (*(RoReg*)0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_USART0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_usart1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_usart1.h
new file mode 100644
index 0000000..be1462b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_usart1.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_USART1_INSTANCE_
+#define _SAM3S_USART1_INSTANCE_
+
+/* ========== Register definition for USART1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART1_CR            (0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR            (0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER           (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR           (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR           (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR           (0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR           (0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR           (0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR          (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR          (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR          (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI          (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER           (0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF            (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN           (0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR          (0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR          (0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_VERSION          (0x400280FCU) /**< \brief (USART1) Version Register */
+#define REG_USART1_RPR           (0x40028100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR           (0x40028104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR           (0x40028108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR           (0x4002810CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR          (0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR          (0x40028114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR          (0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR          (0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR          (0x40028120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR          (0x40028124U) /**< \brief (USART1) Transfer Status Register */
+#else
+#define REG_USART1_CR   (*(WoReg*)0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR   (*(RwReg*)0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER  (*(WoReg*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR  (*(WoReg*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR  (*(RoReg*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR  (*(RoReg*)0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR  (*(RoReg*)0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR  (*(WoReg*)0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR (*(RwReg*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR (*(RwReg*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR (*(RwReg*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI (*(RwReg*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER  (*(RoReg*)0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF   (*(RwReg*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN  (*(RwReg*)0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR (*(RwReg*)0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR (*(RoReg*)0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_VERSION (*(RoReg*)0x400280FCU) /**< \brief (USART1) Version Register */
+#define REG_USART1_RPR  (*(RwReg*)0x40028100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR  (*(RwReg*)0x40028104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR  (*(RwReg*)0x40028108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR  (*(RwReg*)0x4002810CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR (*(RwReg*)0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR (*(RwReg*)0x40028114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR (*(RwReg*)0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR (*(RwReg*)0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR (*(WoReg*)0x40028120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR (*(RoReg*)0x40028124U) /**< \brief (USART1) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_USART1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_wdt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_wdt.h
new file mode 100644
index 0000000..289cfdc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/instance/instance_wdt.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_WDT_INSTANCE_
+#define _SAM3S_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CR          (0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR          (0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR          (0x400E1458U) /**< \brief (WDT) Status Register */
+#else
+#define REG_WDT_CR (*(WoReg*)0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR (*(RwReg*)0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR (*(RoReg*)0x400E1458U) /**< \brief (WDT) Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S_WDT_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s1a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s1a.h
new file mode 100644
index 0000000..f21dffc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s1a.h
@@ -0,0 +1,230 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S1A_PIO_
+#define _SAM3S1A_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+
+#endif /* _SAM3S1A_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s1b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s1b.h
new file mode 100644
index 0000000..fdeb11b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s1b.h
@@ -0,0 +1,277 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S1B_PIO_
+#define _SAM3S1B_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+
+#endif /* _SAM3S1B_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s1c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s1c.h
new file mode 100644
index 0000000..14e32aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s1c.h
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S1C_PIO_
+#define _SAM3S1C_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC18A_A0       (1u << 18) /**< \brief Ebi signal: A0 */
+#define PIO_PC19A_A1       (1u << 19) /**< \brief Ebi signal: A1 */
+#define PIO_PC28A_A10      (1u << 28) /**< \brief Ebi signal: A10 */
+#define PIO_PC29A_A11      (1u << 29) /**< \brief Ebi signal: A11 */
+#define PIO_PC30A_A12      (1u << 30) /**< \brief Ebi signal: A12 */
+#define PIO_PC31A_A13      (1u << 31) /**< \brief Ebi signal: A13 */
+#define PIO_PA18C_A14      (1u << 18) /**< \brief Ebi signal: A14 */
+#define PIO_PA19C_A15      (1u << 19) /**< \brief Ebi signal: A15 */
+#define PIO_PA20C_A16      (1u << 20) /**< \brief Ebi signal: A16 */
+#define PIO_PA0C_A17       (1u << 0)  /**< \brief Ebi signal: A17 */
+#define PIO_PA1C_A18       (1u << 1)  /**< \brief Ebi signal: A18 */
+#define PIO_PA23C_A19      (1u << 23) /**< \brief Ebi signal: A19 */
+#define PIO_PC20A_A2       (1u << 20) /**< \brief Ebi signal: A2 */
+#define PIO_PA24C_A20      (1u << 24) /**< \brief Ebi signal: A20 */
+#define PIO_PC16A_A21      (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC16A_NANDALE  (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC17A_A22      (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC17A_NANDCLE  (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PA25C_A23      (1u << 25) /**< \brief Ebi signal: A23 */
+#define PIO_PC21A_A3       (1u << 21) /**< \brief Ebi signal: A3 */
+#define PIO_PC22A_A4       (1u << 22) /**< \brief Ebi signal: A4 */
+#define PIO_PC23A_A5       (1u << 23) /**< \brief Ebi signal: A5 */
+#define PIO_PC24A_A6       (1u << 24) /**< \brief Ebi signal: A6 */
+#define PIO_PC25A_A7       (1u << 25) /**< \brief Ebi signal: A7 */
+#define PIO_PC26A_A8       (1u << 26) /**< \brief Ebi signal: A8 */
+#define PIO_PC27A_A9       (1u << 27) /**< \brief Ebi signal: A9 */
+#define PIO_PC0A_D0        (1u << 0)  /**< \brief Ebi signal: D0 */
+#define PIO_PC1A_D1        (1u << 1)  /**< \brief Ebi signal: D1 */
+#define PIO_PC2A_D2        (1u << 2)  /**< \brief Ebi signal: D2 */
+#define PIO_PC3A_D3        (1u << 3)  /**< \brief Ebi signal: D3 */
+#define PIO_PC4A_D4        (1u << 4)  /**< \brief Ebi signal: D4 */
+#define PIO_PC5A_D5        (1u << 5)  /**< \brief Ebi signal: D5 */
+#define PIO_PC6A_D6        (1u << 6)  /**< \brief Ebi signal: D6 */
+#define PIO_PC7A_D7        (1u << 7)  /**< \brief Ebi signal: D7 */
+#define PIO_PC9A_NANDOE    (1u << 9)  /**< \brief Ebi signal: NANDOE */
+#define PIO_PC10A_NANDWE   (1u << 10) /**< \brief Ebi signal: NANDWE */
+#define PIO_PC14A_NCS0     (1u << 14) /**< \brief Ebi signal: NCS0 */
+#define PIO_PC15A_NCS1     (1u << 15) /**< \brief Ebi signal: NCS1 */
+#define PIO_PA22C_NCS2     (1u << 22) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC12A_NCS3     (1u << 12) /**< \brief Ebi signal: NCS3 */
+#define PIO_PC11A_NRD      (1u << 11) /**< \brief Ebi signal: NRD */
+#define PIO_PC13A_NWAIT    (1u << 13) /**< \brief Ebi signal: NWAIT */
+#define PIO_PC8A_NWE       (1u << 8)  /**< \brief Ebi signal: NWE */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM3S1C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s2a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s2a.h
new file mode 100644
index 0000000..a888c5e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s2a.h
@@ -0,0 +1,230 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S2A_PIO_
+#define _SAM3S2A_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+
+#endif /* _SAM3S2A_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s2b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s2b.h
new file mode 100644
index 0000000..a71a8cf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s2b.h
@@ -0,0 +1,277 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S2B_PIO_
+#define _SAM3S2B_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+
+#endif /* _SAM3S2B_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s2c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s2c.h
new file mode 100644
index 0000000..3d06e00
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s2c.h
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S2C_PIO_
+#define _SAM3S2C_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC18A_A0       (1u << 18) /**< \brief Ebi signal: A0 */
+#define PIO_PC19A_A1       (1u << 19) /**< \brief Ebi signal: A1 */
+#define PIO_PC28A_A10      (1u << 28) /**< \brief Ebi signal: A10 */
+#define PIO_PC29A_A11      (1u << 29) /**< \brief Ebi signal: A11 */
+#define PIO_PC30A_A12      (1u << 30) /**< \brief Ebi signal: A12 */
+#define PIO_PC31A_A13      (1u << 31) /**< \brief Ebi signal: A13 */
+#define PIO_PA18C_A14      (1u << 18) /**< \brief Ebi signal: A14 */
+#define PIO_PA19C_A15      (1u << 19) /**< \brief Ebi signal: A15 */
+#define PIO_PA20C_A16      (1u << 20) /**< \brief Ebi signal: A16 */
+#define PIO_PA0C_A17       (1u << 0)  /**< \brief Ebi signal: A17 */
+#define PIO_PA1C_A18       (1u << 1)  /**< \brief Ebi signal: A18 */
+#define PIO_PA23C_A19      (1u << 23) /**< \brief Ebi signal: A19 */
+#define PIO_PC20A_A2       (1u << 20) /**< \brief Ebi signal: A2 */
+#define PIO_PA24C_A20      (1u << 24) /**< \brief Ebi signal: A20 */
+#define PIO_PC16A_A21      (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC16A_NANDALE  (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC17A_A22      (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC17A_NANDCLE  (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PA25C_A23      (1u << 25) /**< \brief Ebi signal: A23 */
+#define PIO_PC21A_A3       (1u << 21) /**< \brief Ebi signal: A3 */
+#define PIO_PC22A_A4       (1u << 22) /**< \brief Ebi signal: A4 */
+#define PIO_PC23A_A5       (1u << 23) /**< \brief Ebi signal: A5 */
+#define PIO_PC24A_A6       (1u << 24) /**< \brief Ebi signal: A6 */
+#define PIO_PC25A_A7       (1u << 25) /**< \brief Ebi signal: A7 */
+#define PIO_PC26A_A8       (1u << 26) /**< \brief Ebi signal: A8 */
+#define PIO_PC27A_A9       (1u << 27) /**< \brief Ebi signal: A9 */
+#define PIO_PC0A_D0        (1u << 0)  /**< \brief Ebi signal: D0 */
+#define PIO_PC1A_D1        (1u << 1)  /**< \brief Ebi signal: D1 */
+#define PIO_PC2A_D2        (1u << 2)  /**< \brief Ebi signal: D2 */
+#define PIO_PC3A_D3        (1u << 3)  /**< \brief Ebi signal: D3 */
+#define PIO_PC4A_D4        (1u << 4)  /**< \brief Ebi signal: D4 */
+#define PIO_PC5A_D5        (1u << 5)  /**< \brief Ebi signal: D5 */
+#define PIO_PC6A_D6        (1u << 6)  /**< \brief Ebi signal: D6 */
+#define PIO_PC7A_D7        (1u << 7)  /**< \brief Ebi signal: D7 */
+#define PIO_PC9A_NANDOE    (1u << 9)  /**< \brief Ebi signal: NANDOE */
+#define PIO_PC10A_NANDWE   (1u << 10) /**< \brief Ebi signal: NANDWE */
+#define PIO_PC14A_NCS0     (1u << 14) /**< \brief Ebi signal: NCS0 */
+#define PIO_PC15A_NCS1     (1u << 15) /**< \brief Ebi signal: NCS1 */
+#define PIO_PA22C_NCS2     (1u << 22) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC12A_NCS3     (1u << 12) /**< \brief Ebi signal: NCS3 */
+#define PIO_PC11A_NRD      (1u << 11) /**< \brief Ebi signal: NRD */
+#define PIO_PC13A_NWAIT    (1u << 13) /**< \brief Ebi signal: NWAIT */
+#define PIO_PC8A_NWE       (1u << 8)  /**< \brief Ebi signal: NWE */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM3S2C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s4a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s4a.h
new file mode 100644
index 0000000..bd8df4f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s4a.h
@@ -0,0 +1,230 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S4A_PIO_
+#define _SAM3S4A_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+
+#endif /* _SAM3S4A_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s4b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s4b.h
new file mode 100644
index 0000000..325874c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s4b.h
@@ -0,0 +1,277 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S4B_PIO_
+#define _SAM3S4B_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+
+#endif /* _SAM3S4B_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s4c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s4c.h
new file mode 100644
index 0000000..75b3515
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/pio/pio_sam3s4c.h
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S4C_PIO_
+#define _SAM3S4C_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC18A_A0       (1u << 18) /**< \brief Ebi signal: A0 */
+#define PIO_PC19A_A1       (1u << 19) /**< \brief Ebi signal: A1 */
+#define PIO_PC28A_A10      (1u << 28) /**< \brief Ebi signal: A10 */
+#define PIO_PC29A_A11      (1u << 29) /**< \brief Ebi signal: A11 */
+#define PIO_PC30A_A12      (1u << 30) /**< \brief Ebi signal: A12 */
+#define PIO_PC31A_A13      (1u << 31) /**< \brief Ebi signal: A13 */
+#define PIO_PA18C_A14      (1u << 18) /**< \brief Ebi signal: A14 */
+#define PIO_PA19C_A15      (1u << 19) /**< \brief Ebi signal: A15 */
+#define PIO_PA20C_A16      (1u << 20) /**< \brief Ebi signal: A16 */
+#define PIO_PA0C_A17       (1u << 0)  /**< \brief Ebi signal: A17 */
+#define PIO_PA1C_A18       (1u << 1)  /**< \brief Ebi signal: A18 */
+#define PIO_PA23C_A19      (1u << 23) /**< \brief Ebi signal: A19 */
+#define PIO_PC20A_A2       (1u << 20) /**< \brief Ebi signal: A2 */
+#define PIO_PA24C_A20      (1u << 24) /**< \brief Ebi signal: A20 */
+#define PIO_PC16A_A21      (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC16A_NANDALE  (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC17A_A22      (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC17A_NANDCLE  (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PA25C_A23      (1u << 25) /**< \brief Ebi signal: A23 */
+#define PIO_PC21A_A3       (1u << 21) /**< \brief Ebi signal: A3 */
+#define PIO_PC22A_A4       (1u << 22) /**< \brief Ebi signal: A4 */
+#define PIO_PC23A_A5       (1u << 23) /**< \brief Ebi signal: A5 */
+#define PIO_PC24A_A6       (1u << 24) /**< \brief Ebi signal: A6 */
+#define PIO_PC25A_A7       (1u << 25) /**< \brief Ebi signal: A7 */
+#define PIO_PC26A_A8       (1u << 26) /**< \brief Ebi signal: A8 */
+#define PIO_PC27A_A9       (1u << 27) /**< \brief Ebi signal: A9 */
+#define PIO_PC0A_D0        (1u << 0)  /**< \brief Ebi signal: D0 */
+#define PIO_PC1A_D1        (1u << 1)  /**< \brief Ebi signal: D1 */
+#define PIO_PC2A_D2        (1u << 2)  /**< \brief Ebi signal: D2 */
+#define PIO_PC3A_D3        (1u << 3)  /**< \brief Ebi signal: D3 */
+#define PIO_PC4A_D4        (1u << 4)  /**< \brief Ebi signal: D4 */
+#define PIO_PC5A_D5        (1u << 5)  /**< \brief Ebi signal: D5 */
+#define PIO_PC6A_D6        (1u << 6)  /**< \brief Ebi signal: D6 */
+#define PIO_PC7A_D7        (1u << 7)  /**< \brief Ebi signal: D7 */
+#define PIO_PC9A_NANDOE    (1u << 9)  /**< \brief Ebi signal: NANDOE */
+#define PIO_PC10A_NANDWE   (1u << 10) /**< \brief Ebi signal: NANDWE */
+#define PIO_PC14A_NCS0     (1u << 14) /**< \brief Ebi signal: NCS0 */
+#define PIO_PC15A_NCS1     (1u << 15) /**< \brief Ebi signal: NCS1 */
+#define PIO_PA22C_NCS2     (1u << 22) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC12A_NCS3     (1u << 12) /**< \brief Ebi signal: NCS3 */
+#define PIO_PC11A_NRD      (1u << 11) /**< \brief Ebi signal: NRD */
+#define PIO_PC13A_NWAIT    (1u << 13) /**< \brief Ebi signal: NWAIT */
+#define PIO_PC8A_NWE       (1u << 8)  /**< \brief Ebi signal: NWE */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM3S4C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s.h
new file mode 100644
index 0000000..5ea1020
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s.h
@@ -0,0 +1,55 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S_
+#define _SAM3S_
+
+#if defined __SAM3S1A__
+  #include "sam3s1a.h"
+#elif defined __SAM3S1B__
+  #include "sam3s1b.h"
+#elif defined __SAM3S1C__
+  #include "sam3s1c.h"
+#elif defined __SAM3S2A__
+  #include "sam3s2a.h"
+#elif defined __SAM3S2B__
+  #include "sam3s2b.h"
+#elif defined __SAM3S2C__
+  #include "sam3s2c.h"
+#elif defined __SAM3S4A__
+  #include "sam3s4a.h"
+#elif defined __SAM3S4B__
+  #include "sam3s4b.h"
+#elif defined __SAM3S4C__
+  #include "sam3s4c.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAM3S_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s1a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s1a.h
new file mode 100644
index 0000000..e9f2225
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s1a.h
@@ -0,0 +1,461 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S1A_
+#define _SAM3S1A_
+
+/** \addtogroup SAM3S1A_definitions SAM3S1A definitions
+  This file defines all structures and symbols for SAM3S1A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S1A specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3S1A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S1A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S1A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S1A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S1A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S1A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S1A Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S1A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S1A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S1A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S1A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S1A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S1A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S1A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S1A Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S1A Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S1A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S1A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S1A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S1A Analog To Digital Converter (ADC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S1A Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S1A CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S1A Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM3S1A USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controler */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pvReserved30;
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S1A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S1A does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S1A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3s.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s1a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x4000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S1A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (64000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S1A_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s1b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s1b.h
new file mode 100644
index 0000000..54ce6cf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s1b.h
@@ -0,0 +1,487 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S1B_
+#define _SAM3S1B_
+
+/** \addtogroup SAM3S1B_definitions SAM3S1B definitions
+  This file defines all structures and symbols for SAM3S1B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S1B specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3S1B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S1B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S1B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S1B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S1B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S1B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S1B Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S1B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S1B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S1B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S1B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S1B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S1B USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S1B Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S1B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S1B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S1B Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S1B Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S1B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S1B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S1B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S1B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S1B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S1B Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S1B CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S1B Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM3S1B USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controler */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S1B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S1B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S1B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3s.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s1b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x4000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S1B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (64000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S1B_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s1c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s1c.h
new file mode 100644
index 0000000..941e165
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s1c.h
@@ -0,0 +1,512 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S1C_
+#define _SAM3S1C_
+
+/** \addtogroup SAM3S1C_definitions SAM3S1C definitions
+  This file defines all structures and symbols for SAM3S1C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S1C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3S1C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S1C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S1C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S1C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S1C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S1C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S1C Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S1C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S1C UART 1 (UART1) */
+  SMC_IRQn             = 10, /**< 10 SAM3S1C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S1C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S1C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3S1C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3S1C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S1C USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S1C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S1C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S1C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S1C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S1C Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S1C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S1C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S1C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3S1C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3S1C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3S1C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3S1C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S1C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S1C Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S1C CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S1C Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM3S1C USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pfnSMC_Handler;    /* 10 Static Memory Controller */
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controler */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
+  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
+  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S1C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S1C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S1C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3s.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_SMC    (10) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S1C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s1c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x4000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S1C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (64000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S1C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s2a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s2a.h
new file mode 100644
index 0000000..56e1993
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s2a.h
@@ -0,0 +1,461 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S2A_
+#define _SAM3S2A_
+
+/** \addtogroup SAM3S2A_definitions SAM3S2A definitions
+  This file defines all structures and symbols for SAM3S2A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S2A specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3S2A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S2A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S2A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S2A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S2A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S2A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S2A Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S2A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S2A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S2A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S2A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S2A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S2A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S2A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S2A Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S2A Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S2A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S2A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S2A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S2A Analog To Digital Converter (ADC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S2A Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S2A CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S2A Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM3S2A USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controler */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pvReserved30;
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S2A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S2A does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S2A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3s.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s2a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x8000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S2A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (64000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S2A_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s2b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s2b.h
new file mode 100644
index 0000000..b789699
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s2b.h
@@ -0,0 +1,487 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S2B_
+#define _SAM3S2B_
+
+/** \addtogroup SAM3S2B_definitions SAM3S2B definitions
+  This file defines all structures and symbols for SAM3S2B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S2B specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3S2B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S2B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S2B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S2B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S2B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S2B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S2B Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S2B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S2B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S2B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S2B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S2B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S2B USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S2B Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S2B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S2B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S2B Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S2B Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S2B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S2B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S2B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S2B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S2B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S2B Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S2B CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S2B Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM3S2B USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controler */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S2B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S2B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S2B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3s.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s2b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x8000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S2B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (64000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S2B_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s2c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s2c.h
new file mode 100644
index 0000000..1b9571d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s2c.h
@@ -0,0 +1,512 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S2C_
+#define _SAM3S2C_
+
+/** \addtogroup SAM3S2C_definitions SAM3S2C definitions
+  This file defines all structures and symbols for SAM3S2C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S2C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3S2C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S2C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S2C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S2C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S2C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S2C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S2C Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S2C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S2C UART 1 (UART1) */
+  SMC_IRQn             = 10, /**< 10 SAM3S2C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S2C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S2C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3S2C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3S2C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S2C USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S2C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S2C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S2C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S2C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S2C Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S2C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S2C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S2C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3S2C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3S2C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3S2C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3S2C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S2C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S2C Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S2C CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S2C Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM3S2C USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pfnSMC_Handler;    /* 10 Static Memory Controller */
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controler */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
+  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
+  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S2C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S2C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S2C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3s.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_SMC    (10) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S2C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s2c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x8000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S2C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (64000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S2C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s4a.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s4a.h
new file mode 100644
index 0000000..7f67452
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s4a.h
@@ -0,0 +1,461 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S4A_
+#define _SAM3S4A_
+
+/** \addtogroup SAM3S4A_definitions SAM3S4A definitions
+  This file defines all structures and symbols for SAM3S4A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4A_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S4A specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3S4A Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S4A Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S4A Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S4A Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S4A Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S4A Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S4A Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S4A UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S4A UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S4A Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S4A Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S4A USART 0 (USART0) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S4A Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S4A Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S4A Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S4A Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S4A Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S4A Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S4A Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S4A Analog To Digital Converter (ADC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S4A Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S4A CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S4A Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM3S4A USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pvReserved18;
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controler */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pvReserved30;
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void EFC_Handler        ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S4A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S4A does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S4A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3s.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4A_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4A_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4A_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s4a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0xC000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S4A */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (64000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S4A_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s4b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s4b.h
new file mode 100644
index 0000000..f27f38d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s4b.h
@@ -0,0 +1,487 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S4B_
+#define _SAM3S4B_
+
+/** \addtogroup SAM3S4B_definitions SAM3S4B definitions
+  This file defines all structures and symbols for SAM3S4B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S4B specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3S4B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S4B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S4B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S4B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S4B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S4B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S4B Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S4B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S4B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S4B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S4B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S4B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S4B USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S4B Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S4B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S4B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S4B Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S4B Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S4B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S4B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S4B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S4B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S4B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S4B Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S4B CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S4B Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM3S4B USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controler */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S4B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S4B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S4B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3s.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s4b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0xC000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S4B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (64000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S4B_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s4c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s4c.h
new file mode 100644
index 0000000..1edad51
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/sam3s4c.h
@@ -0,0 +1,512 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S4C_
+#define _SAM3S4C_
+
+/** \addtogroup SAM3S4C_definitions SAM3S4C definitions
+  This file defines all structures and symbols for SAM3S4C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S4C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3S4C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S4C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S4C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S4C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S4C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S4C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S4C Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S4C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S4C UART 1 (UART1) */
+  SMC_IRQn             = 10, /**< 10 SAM3S4C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S4C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S4C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3S4C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3S4C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S4C USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S4C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S4C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S4C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S4C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S4C Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S4C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S4C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S4C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3S4C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3S4C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3S4C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3S4C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S4C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S4C Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S4C CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S4C Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM3S4C USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pfnSMC_Handler;    /* 10 Static Memory Controller */
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controler */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
+  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
+  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S4C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3s.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_SMC    (10) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S4C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s4c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0xC000u)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S4C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (64000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S4C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/system_sam3s.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/system_sam3s.h
new file mode 100644
index 0000000..39d3c3d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/include/system_sam3s.h
@@ -0,0 +1,58 @@
+/*! \file *********************************************************************
+ *
+ * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
+ *           for SAM3 devices.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef SYSTEM_SAM3S_H_INCLUDED
+#define SYSTEM_SAM3S_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#include 
+
+extern uint32_t SystemCoreClock;	/* System Clock Frequency (Core Clock) */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock with current core Clock 
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+/** 
+ * Initialize flash.
+ */
+void system_init_flash(uint32_t dw_clk);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* SYSTEM_SAM3S_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1_flash.ld
new file mode 100644
index 0000000..16efbed
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1_sram.ld
new file mode 100644
index 0000000..28b2d73
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1a_flash.ld
new file mode 100644
index 0000000..3063acf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1a_sram.ld
new file mode 100644
index 0000000..55fac4e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1b_flash.ld
new file mode 100644
index 0000000..3063acf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1b_sram.ld
new file mode 100644
index 0000000..55fac4e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1c_flash.ld
new file mode 100644
index 0000000..3063acf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1c_sram.ld
new file mode 100644
index 0000000..55fac4e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s1c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2_flash.ld
new file mode 100644
index 0000000..d5e3608
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram, 32K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2_sram.ld
new file mode 100644
index 0000000..bd4fc2d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram, 32K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2a_flash.ld
new file mode 100644
index 0000000..0a460aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2a_sram.ld
new file mode 100644
index 0000000..50840b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2b_flash.ld
new file mode 100644
index 0000000..0a460aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2b_sram.ld
new file mode 100644
index 0000000..50840b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2c_flash.ld
new file mode 100644
index 0000000..0a460aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2c_sram.ld
new file mode 100644
index 0000000..50840b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s2c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4_flash.ld
new file mode 100644
index 0000000..90e5494
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000c000 /* sram, 48K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4_sram.ld
new file mode 100644
index 0000000..991d755
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000c000 /* sram, 48K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4a_flash.ld
new file mode 100644
index 0000000..23527e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4a_sram.ld
new file mode 100644
index 0000000..fa48d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4b_flash.ld
new file mode 100644
index 0000000..23527e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4b_sram.ld
new file mode 100644
index 0000000..fa48d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4c_flash.ld
new file mode 100644
index 0000000..23527e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4c_sram.ld
new file mode 100644
index 0000000..fa48d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/sam3s_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/startup_sam3s.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/startup_sam3s.c
new file mode 100644
index 0000000..49df9fa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/as_gcc/startup_sam3s.c
@@ -0,0 +1,243 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3s.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_SMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_USART1_INSTANCE_
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_USART1_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_DACC_INSTANCE_
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_DACC_INSTANCE_ */
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ACC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDP_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM3S_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3S_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3S_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3S_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM3S_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3S_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+#ifdef _SAM3S_HSMCI_INSTANCE_
+	(void*) HSMCI_Handler,   /* 18 MCI */
+#else
+	(void*) (0UL),           /* 18 Reserved */
+#endif /* _SAM3S_HSMCI_INSTANCE_ */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3S_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3S_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+#ifdef _SAM3S_DACC_INSTANCE_
+	(void*) DACC_Handler,    /* 30 DAC controller */
+#else
+	(void*) (0UL),           /* 30 Reserved */
+#endif /* _SAM3S_DACC_INSTANCE_ */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1_flash.ld
new file mode 100644
index 0000000..16efbed
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1_sram.ld
new file mode 100644
index 0000000..28b2d73
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1a_flash.ld
new file mode 100644
index 0000000..3063acf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1a_sram.ld
new file mode 100644
index 0000000..55fac4e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1b_flash.ld
new file mode 100644
index 0000000..3063acf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1b_sram.ld
new file mode 100644
index 0000000..55fac4e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1c_flash.ld
new file mode 100644
index 0000000..3063acf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1c_sram.ld
new file mode 100644
index 0000000..55fac4e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s1c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2_flash.ld
new file mode 100644
index 0000000..d5e3608
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram, 32K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2_sram.ld
new file mode 100644
index 0000000..bd4fc2d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram, 32K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2a_flash.ld
new file mode 100644
index 0000000..0a460aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2a_sram.ld
new file mode 100644
index 0000000..50840b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2b_flash.ld
new file mode 100644
index 0000000..0a460aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2b_sram.ld
new file mode 100644
index 0000000..50840b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2c_flash.ld
new file mode 100644
index 0000000..0a460aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2c_sram.ld
new file mode 100644
index 0000000..50840b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s2c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4_flash.ld
new file mode 100644
index 0000000..90e5494
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000c000 /* sram, 48K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4_sram.ld
new file mode 100644
index 0000000..991d755
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000c000 /* sram, 48K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4a_flash.ld
new file mode 100644
index 0000000..23527e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4a_sram.ld
new file mode 100644
index 0000000..fa48d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4b_flash.ld
new file mode 100644
index 0000000..23527e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4b_sram.ld
new file mode 100644
index 0000000..fa48d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4c_flash.ld
new file mode 100644
index 0000000..23527e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4c_sram.ld
new file mode 100644
index 0000000..fa48d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/sam3s_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/startup_sam3s.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/startup_sam3s.c
new file mode 100644
index 0000000..49df9fa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc/startup_sam3s.c
@@ -0,0 +1,243 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3s.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_SMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_USART1_INSTANCE_
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_USART1_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_DACC_INSTANCE_
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_DACC_INSTANCE_ */
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ACC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDP_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM3S_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3S_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3S_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3S_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM3S_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3S_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+#ifdef _SAM3S_HSMCI_INSTANCE_
+	(void*) HSMCI_Handler,   /* 18 MCI */
+#else
+	(void*) (0UL),           /* 18 Reserved */
+#endif /* _SAM3S_HSMCI_INSTANCE_ */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3S_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3S_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+#ifdef _SAM3S_DACC_INSTANCE_
+	(void*) DACC_Handler,    /* 30 DAC controller */
+#else
+	(void*) (0UL),           /* 30 Reserved */
+#endif /* _SAM3S_DACC_INSTANCE_ */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1_flash.ld
new file mode 100644
index 0000000..16efbed
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1_sram.ld
new file mode 100644
index 0000000..28b2d73
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1a_flash.ld
new file mode 100644
index 0000000..3063acf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1a_sram.ld
new file mode 100644
index 0000000..55fac4e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1b_flash.ld
new file mode 100644
index 0000000..3063acf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1b_sram.ld
new file mode 100644
index 0000000..55fac4e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1c_flash.ld
new file mode 100644
index 0000000..3063acf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1c_sram.ld
new file mode 100644
index 0000000..55fac4e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s1c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2_flash.ld
new file mode 100644
index 0000000..d5e3608
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram, 32K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2_sram.ld
new file mode 100644
index 0000000..bd4fc2d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram, 32K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2a_flash.ld
new file mode 100644
index 0000000..0a460aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2a_sram.ld
new file mode 100644
index 0000000..50840b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2b_flash.ld
new file mode 100644
index 0000000..0a460aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2b_sram.ld
new file mode 100644
index 0000000..50840b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2c_flash.ld
new file mode 100644
index 0000000..0a460aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2c_sram.ld
new file mode 100644
index 0000000..50840b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s2c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4_flash.ld
new file mode 100644
index 0000000..90e5494
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000c000 /* sram, 48K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4_sram.ld
new file mode 100644
index 0000000..991d755
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000c000 /* sram, 48K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4a_flash.ld
new file mode 100644
index 0000000..23527e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4a_sram.ld
new file mode 100644
index 0000000..fa48d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4b_flash.ld
new file mode 100644
index 0000000..23527e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4b_sram.ld
new file mode 100644
index 0000000..fa48d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4c_flash.ld
new file mode 100644
index 0000000..23527e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4c_sram.ld
new file mode 100644
index 0000000..fa48d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/sam3s_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/startup_sam3s.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/startup_sam3s.c
new file mode 100644
index 0000000..49df9fa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_arm/startup_sam3s.c
@@ -0,0 +1,243 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3s.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_SMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_USART1_INSTANCE_
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_USART1_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_DACC_INSTANCE_
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_DACC_INSTANCE_ */
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ACC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDP_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM3S_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3S_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3S_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3S_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM3S_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3S_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+#ifdef _SAM3S_HSMCI_INSTANCE_
+	(void*) HSMCI_Handler,   /* 18 MCI */
+#else
+	(void*) (0UL),           /* 18 Reserved */
+#endif /* _SAM3S_HSMCI_INSTANCE_ */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3S_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3S_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+#ifdef _SAM3S_DACC_INSTANCE_
+	(void*) DACC_Handler,    /* 30 DAC controller */
+#else
+	(void*) (0UL),           /* 30 Reserved */
+#endif /* _SAM3S_DACC_INSTANCE_ */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1_flash.ld
new file mode 100644
index 0000000..16efbed
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1_sram.ld
new file mode 100644
index 0000000..28b2d73
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00010000 /* Flash, 64K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* sram, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1a_flash.ld
new file mode 100644
index 0000000..3063acf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1a_sram.ld
new file mode 100644
index 0000000..55fac4e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1b_flash.ld
new file mode 100644
index 0000000..3063acf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1b_sram.ld
new file mode 100644
index 0000000..55fac4e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1c_flash.ld
new file mode 100644
index 0000000..3063acf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1c_sram.ld
new file mode 100644
index 0000000..55fac4e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s1c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2_flash.ld
new file mode 100644
index 0000000..d5e3608
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram, 32K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2_sram.ld
new file mode 100644
index 0000000..bd4fc2d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00020000 /* flash, 128K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram, 32K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2a_flash.ld
new file mode 100644
index 0000000..0a460aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2a_sram.ld
new file mode 100644
index 0000000..50840b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2b_flash.ld
new file mode 100644
index 0000000..0a460aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2b_sram.ld
new file mode 100644
index 0000000..50840b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2c_flash.ld
new file mode 100644
index 0000000..0a460aa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2c_sram.ld
new file mode 100644
index 0000000..50840b2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s2c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4_flash.ld
new file mode 100644
index 0000000..90e5494
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000c000 /* sram, 48K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4_sram.ld
new file mode 100644
index 0000000..991d755
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash, 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000c000 /* sram, 48K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4a_flash.ld
new file mode 100644
index 0000000..23527e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4a_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4a_sram.ld
new file mode 100644
index 0000000..fa48d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4a_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4b_flash.ld
new file mode 100644
index 0000000..23527e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4b_sram.ld
new file mode 100644
index 0000000..fa48d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4c_flash.ld
new file mode 100644
index 0000000..23527e1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4c_sram.ld
new file mode 100644
index 0000000..fa48d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/sam3s_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/startup_sam3s.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/startup_sam3s.c
new file mode 100644
index 0000000..49df9fa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/gcc_atmel/startup_sam3s.c
@@ -0,0 +1,243 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3s.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_SMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_USART1_INSTANCE_
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_USART1_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S_DACC_INSTANCE_
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S_DACC_INSTANCE_ */
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ACC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDP_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM3S_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3S_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3S_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3S_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM3S_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3S_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+#ifdef _SAM3S_HSMCI_INSTANCE_
+	(void*) HSMCI_Handler,   /* 18 MCI */
+#else
+	(void*) (0UL),           /* 18 Reserved */
+#endif /* _SAM3S_HSMCI_INSTANCE_ */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3S_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3S_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+#ifdef _SAM3S_DACC_INSTANCE_
+	(void*) DACC_Handler,    /* 30 DAC controller */
+#else
+	(void*) (0UL),           /* 30 Reserved */
+#endif /* _SAM3S_DACC_INSTANCE_ */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s1_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s1_flash.icf
new file mode 100644
index 0000000..53c8247
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s1_flash.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00400000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20003FFF;
+define symbol __ICFEDIT_region_ROM_start__  = 0x00400000;
+define symbol __ICFEDIT_region_ROM_end__    = 0x0040FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region     = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors };
+place in ROM_region          { readonly };
+place in RAM_region          { readwrite,,block CSTACK,  block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s1_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s1_sram.icf
new file mode 100644
index 0000000..ca6e2ce
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s1_sram.icf
@@ -0,0 +1,26 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors };
+place in RAM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s2_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s2_flash.icf
new file mode 100644
index 0000000..d171373
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s2_flash.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00400000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF;
+define symbol __ICFEDIT_region_ROM_start__  = 0x00400000;
+define symbol __ICFEDIT_region_ROM_end__    = 0x0041FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region     = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors };
+place in ROM_region          { readonly };
+place in RAM_region          { readwrite,,block CSTACK,  block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s2_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s2_sram.icf
new file mode 100644
index 0000000..f428df5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s2_sram.icf
@@ -0,0 +1,26 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors };
+place in RAM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s4_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s4_flash.icf
new file mode 100644
index 0000000..ac5cb4f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s4_flash.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00400000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2000BFFF;
+define symbol __ICFEDIT_region_ROM_start__  = 0x00400000;
+define symbol __ICFEDIT_region_ROM_end__    = 0x0043FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region     = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in ROM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s4_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s4_sram.icf
new file mode 100644
index 0000000..adbeeff
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/sam3s4_sram.icf
@@ -0,0 +1,26 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2000BFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in RAM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/startup_sam3s.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/startup_sam3s.c
new file mode 100644
index 0000000..654da71
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/iar/startup_sam3s.c
@@ -0,0 +1,223 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3s.h"
+
+/* Initialize segments */
+extern uint32_t __cstack_start__;
+extern uint32_t __cstack_end__;
+
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+#pragma weak NMI_Handler=Dummy_Handler
+#pragma weak HardFault_Handler=Dummy_Handler
+#pragma weak MemManage_Handler=Dummy_Handler
+#pragma weak BusFault_Handler=Dummy_Handler
+#pragma weak UsageFault_Handler=Dummy_Handler
+#pragma weak SVC_Handler=Dummy_Handler
+#pragma weak DebugMon_Handler=Dummy_Handler
+#pragma weak PendSV_Handler=Dummy_Handler
+#pragma weak SysTick_Handler=Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak SUPC_Handler=Dummy_Handler
+#pragma weak RSTC_Handler=Dummy_Handler
+#pragma weak RTC_Handler=Dummy_Handler
+#pragma weak RTT_Handler=Dummy_Handler
+#pragma weak WDT_Handler=Dummy_Handler
+#pragma weak PMC_Handler=Dummy_Handler
+#pragma weak EFC_Handler=Dummy_Handler
+#pragma weak UART0_Handler=Dummy_Handler
+#pragma weak UART1_Handler=Dummy_Handler
+#ifdef _SAM3S_SMC_INSTANCE_
+#pragma weak SMC_Handler=Dummy_Handler
+#endif /* _SAM3S_SMC_INSTANCE_ */
+#pragma weak PIOA_Handler=Dummy_Handler
+#pragma weak PIOB_Handler=Dummy_Handler
+#ifdef _SAM3S_PIOC_INSTANCE_
+#pragma weak PIOC_Handler=Dummy_Handler
+#endif /* _SAM3S_PIOC_INSTANCE_ */
+#pragma weak USART0_Handler=Dummy_Handler
+#ifdef _SAM3S_USART1_INSTANCE_
+#pragma weak USART1_Handler=Dummy_Handler
+#endif /* _SAM3S_USART1_INSTANCE_ */
+#pragma weak HSMCI_Handler=Dummy_Handler
+#pragma weak TWI0_Handler=Dummy_Handler
+#pragma weak TWI1_Handler=Dummy_Handler
+#pragma weak SPI_Handler=Dummy_Handler
+#pragma weak SSC_Handler=Dummy_Handler
+#pragma weak TC0_Handler=Dummy_Handler
+#pragma weak TC1_Handler=Dummy_Handler
+#pragma weak TC2_Handler=Dummy_Handler
+#ifdef _SAM3S_TC1_INSTANCE_
+#pragma weak TC3_Handler=Dummy_Handler
+#pragma weak TC4_Handler=Dummy_Handler
+#pragma weak TC5_Handler=Dummy_Handler
+#endif /* _SAM3S_TC1_INSTANCE_ */
+#pragma weak ADC_Handler=Dummy_Handler
+#ifdef _SAM3S_DACC_INSTANCE_
+#pragma weak DACC_Handler=Dummy_Handler
+#endif /* _SAM3S_DACC_INSTANCE_ */
+#pragma weak PWM_Handler=Dummy_Handler
+#pragma weak CRCCU_Handler=Dummy_Handler
+#pragma weak ACC_Handler=Dummy_Handler
+#pragma weak UDP_Handler=Dummy_Handler
+
+/* Exception Table */
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section = ".intvec"
+#pragma location = ".intvec"
+const DeviceVectors __vector_table[] = {
+	(void*) (&__cstack_end__),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM3S_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3S_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3S_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3S_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM3S_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3S_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+#ifdef _SAM3S_HSMCI_INSTANCE_
+	(void*) HSMCI_Handler,   /* 18 MCI */
+#else
+	(void*) (0UL),           /* 18 Reserved */
+#endif /* _SAM3S_HSMCI_INSTANCE_ */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3S_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3S_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+#ifdef _SAM3S_DACC_INSTANCE_
+	(void*) DACC_Handler,    /* 30 DACC controller */
+#else
+	(void*) (0UL),           /* 30 Reserved */
+#endif /* _SAM3S_DACC_INSTANCE_ */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+	uint32_t *pSrc = __section_begin(".intvec");
+
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+	__iar_program_start();
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/system_sam3s.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/system_sam3s.c
new file mode 100644
index 0000000..81e59c4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3s/source/system_sam3s.c
@@ -0,0 +1,195 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3s.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Clock settings (64MHz) */
+#define SYS_BOARD_OSCOUNT   (CKGR_MOR_MOSCXTST(0x8UL))
+#define SYS_BOARD_PLLAR     (CKGR_PLLAR_ONE \
+							| CKGR_PLLAR_MULA(0x1fUL) \
+							| CKGR_PLLAR_PLLACOUNT(0x3fUL) \
+							| CKGR_PLLAR_DIVA(0x3UL))
+#define SYS_BOARD_MCKR      (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)
+
+#define SYS_CKGR_MOR_KEY_VALUE	CKGR_MOR_KEY(0x37UL) /* Key to unlock MOR register */
+
+/* FIXME: should be generated by sock */
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+/**
+ * \brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit(void)
+{
+	/* Set FWS according to SYS_BOARD_MCKR configuration */
+	EFC->EEFC_FMR = EEFC_FMR_FWS(3);
+
+	/* Initialize main oscillator */
+	if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
+		PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
+			                     CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+		while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
+		}
+	}
+
+	/* Switch to 3-20MHz Xtal oscillator */
+	PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN |
+                             CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+
+	while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
+	}
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Initialize PLLA */
+	PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
+	while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
+	}
+
+	/* Switch to main clock */
+	PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Switch to PLLA */
+	PMC->PMC_MCKR = SYS_BOARD_MCKR;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	SystemCoreClock = CHIP_FREQ_CPU_MAX;
+}
+
+void SystemCoreClockUpdate(void)
+{
+	/* Determine clock frequency according to clock register values */
+	switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
+	case PMC_MCKR_CSS_SLOW_CLK:	/* Slow clock */
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_32K;
+		} else {
+			SystemCoreClock = CHIP_FREQ_SLCK_RC;
+		}
+		break;
+	case PMC_MCKR_CSS_MAIN_CLK:	/* Main clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	case PMC_MCKR_CSS_PLLA_CLK:	/* PLLA clock */
+	case PMC_MCKR_CSS_PLLB_CLK:	/* PLLB clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
+			SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
+				                          CKGR_PLLAR_MULA_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
+				                          CKGR_PLLAR_DIVA_Pos));
+		} else {
+			SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >>
+				                          CKGR_PLLBR_MULB_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >>
+				                          CKGR_PLLBR_DIVB_Pos));
+		}
+		break;
+	default:
+		break;
+	}
+
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
+		SystemCoreClock /= 3U;
+	} else {
+		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
+	}
+}
+
+/**
+ * Initialize flash.
+ */
+void system_init_flash(uint32_t dw_clk)
+{
+	/* Set FWS for embedded Flash access according to operating frequency */
+	if (dw_clk < CHIP_FREQ_FWS_0) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(0);
+	} else if (dw_clk < CHIP_FREQ_FWS_1) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(1);
+	} else if (dw_clk < CHIP_FREQ_FWS_2) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(2);
+	} else {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(3);
+	}
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_acc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_acc.h
new file mode 100644
index 0000000..a309a19
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_acc.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_ACC_COMPONENT_
+#define _SAM3S8_ACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog Comparator Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_ACC Analog Comparator Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Acc hardware registers */
+typedef struct {
+  WoReg ACC_CR;        /**< \brief (Acc Offset: 0x00) Control Register */
+  RwReg ACC_MR;        /**< \brief (Acc Offset: 0x04) Mode Register */
+  RoReg Reserved1[7];
+  WoReg ACC_IER;       /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */
+  WoReg ACC_IDR;       /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */
+  RoReg ACC_IMR;       /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ACC_ISR;       /**< \brief (Acc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[24];
+  RwReg ACC_ACR;       /**< \brief (Acc Offset: 0x94) Analog Control Register */
+  RoReg Reserved3[19];
+  RwReg ACC_WPMR;      /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ACC_WPSR;      /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */
+} Acc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
+#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) SoftWare ReSeT */
+/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
+#define ACC_MR_SELMINUS_Pos 0
+#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) SELection for MINUS comparator input */
+#define   ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) SelectTS */
+#define   ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */
+#define   ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */
+#define   ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */
+#define   ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */
+#define   ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */
+#define   ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */
+#define   ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */
+#define ACC_MR_SELPLUS_Pos 4
+#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) SELection for PLUS comparator input */
+#define   ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */
+#define   ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */
+#define   ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */
+#define   ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */
+#define   ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */
+#define   ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */
+#define   ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */
+#define   ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */
+#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator ENable */
+#define   ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog Comparator Disabled. */
+#define   ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enabled. */
+#define ACC_MR_EDGETYP_Pos 9
+#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) EDGE TYPe */
+#define   ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) only rising edge of comparator output */
+#define   ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) falling edge of comparator output */
+#define   ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) any edge of comparator output */
+#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) INVert comparator output */
+#define   ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog Comparator output is directly processed. */
+#define   ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog Comparator output is inverted prior to being processed. */
+#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) SELection of Fault Source */
+#define   ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) the CF flag is used to drive the FAULT output. */
+#define   ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) the output of the Analog Comparator flag is used to drive the FAULT output. */
+#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */
+#define   ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) the FAULT output is tied to 0. */
+#define   ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) the FAULT output is driven by the signal defined by SELFS. */
+/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
+#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */
+/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
+#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */
+/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */
+/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
+#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */
+#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */
+#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR)  */
+/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
+#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current SELection */
+#define   ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) low power option. */
+#define   ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) high speed option. */
+#define ACC_ACR_HYST_Pos 1
+#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) HYSTeresis selection */
+#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
+/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protect Enable */
+#define ACC_WPMR_WPKEY_Pos 8
+#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protect KEY */
+#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
+/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */
+#define ACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_ACC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_adc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_adc.h
new file mode 100644
index 0000000..809e09f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_adc.h
@@ -0,0 +1,509 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_ADC_COMPONENT_
+#define _SAM3S8_ADC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_ADC Analog-to-digital Converter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Adc hardware registers */
+typedef struct {
+  WoReg ADC_CR;        /**< \brief (Adc Offset: 0x00) Control Register */
+  RwReg ADC_MR;        /**< \brief (Adc Offset: 0x04) Mode Register */
+  RwReg ADC_SEQR1;     /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
+  RwReg ADC_SEQR2;     /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
+  WoReg ADC_CHER;      /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+  WoReg ADC_CHDR;      /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+  RoReg ADC_CHSR;      /**< \brief (Adc Offset: 0x18) Channel Status Register */
+  RoReg Reserved1[1];
+  RoReg ADC_LCDR;      /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+  WoReg ADC_IER;       /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC_IDR;       /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC_IMR;       /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC_ISR;       /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[2];
+  RoReg ADC_OVER;      /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
+  RwReg ADC_EMR;       /**< \brief (Adc Offset: 0x40) Extended Mode Register */
+  RwReg ADC_CWR;       /**< \brief (Adc Offset: 0x44) Compare Window Register */
+  RwReg ADC_CGR;       /**< \brief (Adc Offset: 0x48) Channel Gain Register */
+  RwReg ADC_COR;       /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
+  RoReg ADC_CDR[15];   /**< \brief (Adc Offset: 0x50) Channel Data Register */
+  RoReg Reserved3[2];
+  RwReg ADC_ACR;       /**< \brief (Adc Offset: 0x94) Analog Control Register */
+  RoReg Reserved4[19];
+  RwReg ADC_WPMR;      /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ADC_WPSR;      /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved5[5];
+  RwReg ADC_RPR;       /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+  RwReg ADC_RCR;       /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+  RoReg Reserved6[2];
+  RwReg ADC_RNPR;      /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC_RNCR;      /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+  RoReg Reserved7[2];
+  WoReg ADC_PTCR;      /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+  RoReg ADC_PTSR;      /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+#define ADC_CR_AUTOCAL (0x1u << 3) /**< \brief (ADC_CR) Automatic Calibration of ADC */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define   ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define   ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */
+#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */
+#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */
+#define   ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
+#define   ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */
+#define   ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define   ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
+#define   ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
+#define   ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
+#define   ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */
+#define   ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */
+#define   ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define   ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */
+#define ADC_MR_SETTLING_Pos 20
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */
+#define   ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */
+#define   ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */
+#define   ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */
+#define ADC_MR_TRACKTIM_Pos 24
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
+#define ADC_MR_TRANSFER_Pos 28
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
+#define   ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */
+#define   ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
+#define ADC_SEQR1_USCH1_Pos 0
+#define ADC_SEQR1_USCH1_Msk (0x7u << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
+#define ADC_SEQR1_USCH2_Pos 4
+#define ADC_SEQR1_USCH2_Msk (0x7u << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
+#define ADC_SEQR1_USCH3_Pos 8
+#define ADC_SEQR1_USCH3_Msk (0x7u << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
+#define ADC_SEQR1_USCH4_Pos 12
+#define ADC_SEQR1_USCH4_Msk (0x7u << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
+#define ADC_SEQR1_USCH5_Pos 16
+#define ADC_SEQR1_USCH5_Msk (0x7u << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
+#define ADC_SEQR1_USCH6_Pos 20
+#define ADC_SEQR1_USCH6_Msk (0x7u << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
+#define ADC_SEQR1_USCH7_Pos 24
+#define ADC_SEQR1_USCH7_Msk (0x7u << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
+#define ADC_SEQR1_USCH8_Pos 28
+#define ADC_SEQR1_USCH8_Msk (0x7u << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
+#define ADC_SEQR2_USCH9_Pos 0
+#define ADC_SEQR2_USCH9_Msk (0x7u << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
+#define ADC_SEQR2_USCH10_Pos 4
+#define ADC_SEQR2_USCH10_Msk (0x7u << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
+#define ADC_SEQR2_USCH11_Pos 8
+#define ADC_SEQR2_USCH11_Msk (0x7u << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
+#define ADC_SEQR2_USCH12_Pos 12
+#define ADC_SEQR2_USCH12_Msk (0x7u << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
+#define ADC_SEQR2_USCH13_Pos 16
+#define ADC_SEQR2_USCH13_Msk (0x7u << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
+#define ADC_SEQR2_USCH14_Pos 20
+#define ADC_SEQR2_USCH14_Msk (0x7u << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
+#define ADC_SEQR2_USCH15_Pos 24
+#define ADC_SEQR2_USCH15_Msk (0x7u << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
+#define ADC_SEQR2_USCH16_Pos 28
+#define ADC_SEQR2_USCH16_Msk (0x7u << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+#define ADC_LCDR_CHNB_Pos 12
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
+#define ADC_IER_EOCAL (0x1u << 23) /**< \brief (ADC_IER) End of Calibration Sequence */
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
+#define ADC_IDR_EOCAL (0x1u << 23) /**< \brief (ADC_IDR) End of Calibration Sequence */
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
+#define ADC_IMR_EOCAL (0x1u << 23) /**< \brief (ADC_IMR) End of Calibration Sequence */
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
+#define ADC_ISR_EOCAL (0x1u << 23) /**< \brief (ADC_ISR) End of Calibration Sequence */
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
+#define ADC_EMR_CMPMODE_Pos 0
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
+#define   ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define   ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
+#define   ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
+#define ADC_EMR_CMPSEL_Pos 4
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
+#define ADC_EMR_CMPFILTER_Pos 12
+#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */
+#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos)))
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
+#define ADC_CWR_LOWTHRES_Pos 0
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
+#define ADC_CWR_HIGHTHRES_Pos 16
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
+#define ADC_CGR_GAIN0_Pos 0
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))
+#define ADC_CGR_GAIN1_Pos 2
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))
+#define ADC_CGR_GAIN2_Pos 4
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))
+#define ADC_CGR_GAIN3_Pos 6
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))
+#define ADC_CGR_GAIN4_Pos 8
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))
+#define ADC_CGR_GAIN5_Pos 10
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))
+#define ADC_CGR_GAIN6_Pos 12
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))
+#define ADC_CGR_GAIN7_Pos 14
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))
+#define ADC_CGR_GAIN8_Pos 16
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))
+#define ADC_CGR_GAIN9_Pos 18
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))
+#define ADC_CGR_GAIN10_Pos 20
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))
+#define ADC_CGR_GAIN11_Pos 22
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))
+#define ADC_CGR_GAIN12_Pos 24
+#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */
+#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))
+#define ADC_CGR_GAIN13_Pos 26
+#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */
+#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))
+#define ADC_CGR_GAIN14_Pos 28
+#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */
+#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))
+#define ADC_CGR_GAIN15_Pos 30
+#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */
+#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */
+#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */
+#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */
+#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */
+#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */
+#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */
+#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */
+#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */
+#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */
+/* -------- ADC_CDR[15] : (ADC Offset: 0x50) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[15]) Converted Data */
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
+#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */
+#define ADC_ACR_IBCTL_Pos 8
+#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */
+#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
+#define ADC_WPMR_WPKEY_Pos 8
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
+#define ADC_WPSR_WPVSRC_Pos 8
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_ADC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_chipid.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_chipid.h
new file mode 100644
index 0000000..71ff151
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_chipid.h
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_CHIPID_COMPONENT_
+#define _SAM3S8_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_CHIPID Chip Identifier */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Chipid hardware registers */
+typedef struct {
+  RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+  RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define   CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define   CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define   CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define   CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define   CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define   CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define   CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define   CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define   CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define   CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define   CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define   CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
+#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_CHIPID_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_crccu.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_crccu.h
new file mode 100644
index 0000000..545daf7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_crccu.h
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_CRCCU_COMPONENT_
+#define _SAM3S8_CRCCU_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_CRCCU Cyclic Redundancy Check Calculation Unit */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Crccu hardware registers */
+typedef struct {
+  RwReg CRCCU_DSCR;    /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */
+  RoReg Reserved1[1];
+  WoReg CRCCU_DMA_EN;  /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */
+  WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */
+  RoReg CRCCU_DMA_SR;  /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */
+  WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */
+  WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */
+  RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */
+  RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */
+  RoReg Reserved2[4];
+  WoReg CRCCU_CR;      /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */
+  RwReg CRCCU_MR;      /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */
+  RoReg CRCCU_SR;      /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */
+  WoReg CRCCU_IER;     /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */
+  WoReg CRCCU_IDR;     /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */
+  RoReg CRCCU_IMR;     /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */
+  RoReg CRCCU_ISR;     /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */
+} Crccu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */
+#define CRCCU_DSCR_DSCR_Pos 9
+#define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */
+#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos)))
+/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */
+#define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */
+/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */
+#define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */
+/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */
+#define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */
+/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */
+#define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */
+/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */
+#define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */
+/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */
+#define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */
+/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */
+#define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */
+/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */
+#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */
+/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */
+#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */
+#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */
+#define CRCCU_MR_PTYPE_Pos 2
+#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */
+#define   CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */
+#define   CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */
+#define   CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */
+#define CRCCU_MR_DIVIDER_Pos 4
+#define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */
+#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)))
+/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */
+#define CRCCU_SR_CRC_Pos 0
+#define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */
+/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */
+#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */
+/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */
+#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */
+/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */
+#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */
+/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */
+#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_CRCCU_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_dacc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_dacc.h
new file mode 100644
index 0000000..f169a68
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_dacc.h
@@ -0,0 +1,210 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_DACC_COMPONENT_
+#define _SAM3S8_DACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_DACC Digital-to-Analog Converter Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Dacc hardware registers */
+typedef struct {
+  WoReg DACC_CR;       /**< \brief (Dacc Offset: 0x00) Control Register */
+  RwReg DACC_MR;       /**< \brief (Dacc Offset: 0x04) Mode Register */
+  RoReg Reserved1[2];
+  WoReg DACC_CHER;     /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
+  WoReg DACC_CHDR;     /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
+  RoReg DACC_CHSR;     /**< \brief (Dacc Offset: 0x18) Channel Status Register */
+  RoReg Reserved2[1];
+  WoReg DACC_CDR;      /**< \brief (Dacc Offset: 0x20) Conversion Data Register */
+  WoReg DACC_IER;      /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
+  WoReg DACC_IDR;      /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
+  RoReg DACC_IMR;      /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
+  RoReg DACC_ISR;      /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved3[24];
+  RwReg DACC_ACR;      /**< \brief (Dacc Offset: 0x94) Analog Current Register */
+  RoReg Reserved4[19];
+  RwReg DACC_WPMR;     /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */
+  RoReg DACC_WPSR;     /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */
+  RoReg Reserved5[7];
+  RwReg DACC_TPR;      /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
+  RwReg DACC_TCR;      /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
+  RoReg Reserved6[2];
+  RwReg DACC_TNPR;     /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg DACC_TNCR;     /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg DACC_PTCR;     /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
+  RoReg DACC_PTSR;     /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
+} Dacc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
+#define   DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */
+#define   DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */
+#define DACC_MR_TRGSEL_Pos 1
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define   DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */
+#define   DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */
+#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */
+#define DACC_MR_REFRESH_Pos 8
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
+#define DACC_MR_USER_SEL_Pos 16
+#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */
+#define   DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */
+#define   DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */
+#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */
+#define   DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */
+#define   DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */
+#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */
+#define   DACC_MR_MAXS_NORMAL (0x0u << 21) /**< \brief (DACC_MR) Normal Mode */
+#define   DACC_MR_MAXS_MAXIMUM (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode enabled */
+#define DACC_MR_STARTUP_Pos 24
+#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
+#define   DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */
+#define   DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */
+#define   DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */
+#define   DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */
+#define   DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */
+#define   DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */
+#define   DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */
+#define   DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */
+#define   DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */
+#define   DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */
+#define   DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */
+#define   DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */
+#define   DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */
+#define   DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */
+#define   DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */
+#define   DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */
+#define   DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */
+#define   DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */
+#define   DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */
+#define   DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */
+#define   DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */
+#define   DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */
+#define   DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */
+#define   DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */
+#define   DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */
+#define   DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */
+#define   DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */
+#define   DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */
+#define   DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */
+#define   DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */
+#define   DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */
+#define   DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
+/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */
+#define DACC_CDR_DATA_Pos 0
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */
+#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */
+#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */
+#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */
+#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */
+#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */
+#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */
+#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */
+#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */
+#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */
+#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */
+#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */
+#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
+#define DACC_ACR_IBCTLCH0_Pos 0
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
+#define DACC_ACR_IBCTLCH1_Pos 2
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
+#define DACC_ACR_IBCTLDACCORE_Pos 8
+#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */
+#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
+#define DACC_WPMR_WPKEY_Pos 8
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
+#define DACC_WPSR_WPROTADDR_Pos 8
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
+#define DACC_TPR_TXPTR_Pos 0
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
+#define DACC_TCR_TXCTR_Pos 0
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define DACC_TNPR_TXNPTR_Pos 0
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define DACC_TNCR_TXNCTR_Pos 0
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_DACC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_efc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_efc.h
new file mode 100644
index 0000000..ecb9952
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_efc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_EFC_COMPONENT_
+#define _SAM3S8_EFC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_EFC Embedded Flash Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Efc hardware registers */
+typedef struct {
+  RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+  WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+  RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+  RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_EFC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_gpbr.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_gpbr.h
new file mode 100644
index 0000000..1cccf4c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_gpbr.h
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_GPBR_COMPONENT_
+#define _SAM3S8_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_GPBR General Purpose Backup Register */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Gpbr hardware registers */
+typedef struct {
+  RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S8_GPBR_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_hsmci.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_hsmci.h
new file mode 100644
index 0000000..9efa46c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_hsmci.h
@@ -0,0 +1,384 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_HSMCI_COMPONENT_
+#define _SAM3S8_HSMCI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_HSMCI High Speed MultiMedia Card Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Hsmci hardware registers */
+typedef struct {
+  WoReg HSMCI_CR;        /**< \brief (Hsmci Offset: 0x00) Control Register */
+  RwReg HSMCI_MR;        /**< \brief (Hsmci Offset: 0x04) Mode Register */
+  RwReg HSMCI_DTOR;      /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
+  RwReg HSMCI_SDCR;      /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
+  RwReg HSMCI_ARGR;      /**< \brief (Hsmci Offset: 0x10) Argument Register */
+  WoReg HSMCI_CMDR;      /**< \brief (Hsmci Offset: 0x14) Command Register */
+  RwReg HSMCI_BLKR;      /**< \brief (Hsmci Offset: 0x18) Block Register */
+  RwReg HSMCI_CSTOR;     /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
+  RoReg HSMCI_RSPR[4];   /**< \brief (Hsmci Offset: 0x20) Response Register */
+  RoReg HSMCI_RDR;       /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
+  WoReg HSMCI_TDR;       /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
+  RoReg Reserved1[2];
+  RoReg HSMCI_SR;        /**< \brief (Hsmci Offset: 0x40) Status Register */
+  WoReg HSMCI_IER;       /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
+  WoReg HSMCI_IDR;       /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
+  RoReg HSMCI_IMR;       /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved2[1];
+  RwReg HSMCI_CFG;       /**< \brief (Hsmci Offset: 0x54) Configuration Register */
+  RoReg Reserved3[35];
+  RwReg HSMCI_WPMR;      /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
+  RoReg HSMCI_WPSR;      /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved4[5];
+  RwReg HSMCI_RPR;       /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */
+  RwReg HSMCI_RCR;       /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */
+  RwReg HSMCI_TPR;       /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */
+  RwReg HSMCI_TCR;       /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */
+  RwReg HSMCI_RNPR;      /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */
+  RwReg HSMCI_RNCR;      /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */
+  RwReg HSMCI_TNPR;      /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */
+  RwReg HSMCI_TNCR;      /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */
+  WoReg HSMCI_PTCR;      /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */
+  RoReg HSMCI_PTSR;      /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */
+  RoReg Reserved5[54];
+  RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
+} Hsmci;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
+#define HSMCI_MR_CLKDIV_Pos 0
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
+#define HSMCI_MR_PWSDIV_Pos 8
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
+#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
+#define HSMCI_DTOR_DTOCYC_Pos 0
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
+#define HSMCI_DTOR_DTOMUL_Pos 4
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
+#define   HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
+#define   HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
+#define   HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
+#define   HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
+#define   HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
+#define   HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
+#define   HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
+#define   HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
+#define HSMCI_SDCR_SDCSEL_Pos 0
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
+#define   HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
+#define   HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCBUS_Pos 6
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
+#define   HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
+#define   HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
+#define   HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
+#define HSMCI_ARGR_ARG_Pos 0
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
+#define HSMCI_CMDR_CMDNB_Pos 0
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
+#define HSMCI_CMDR_RSPTYP_Pos 6
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
+#define   HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
+#define   HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
+#define   HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
+#define   HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
+#define HSMCI_CMDR_SPCMD_Pos 8
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
+#define   HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
+#define   HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
+#define   HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
+#define   HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
+#define   HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
+#define   HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
+#define   HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
+#define   HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
+#define   HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
+#define   HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
+#define HSMCI_CMDR_TRCMD_Pos 16
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
+#define   HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
+#define   HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
+#define   HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
+#define   HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
+#define   HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
+#define HSMCI_CMDR_TRTYP_Pos 19
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
+#define   HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
+#define   HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
+#define   HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
+#define   HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
+#define   HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
+#define HSMCI_CMDR_IOSPCMD_Pos 24
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
+#define   HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
+#define   HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
+#define   HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
+#define HSMCI_BLKR_BCNT_Pos 0
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
+#define   HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
+#define   HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define   HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BLKLEN_Pos 16
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
+#define HSMCI_CSTOR_CSTOCYC_Pos 0
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
+#define HSMCI_CSTOR_CSTOMUL_Pos 4
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
+#define   HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
+#define   HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
+#define   HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
+#define   HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
+#define   HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
+#define   HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
+#define   HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
+#define   HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
+#define HSMCI_RSPR_RSP_Pos 0
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
+#define HSMCI_RDR_DATA_Pos 0
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
+#define HSMCI_TDR_DATA_Pos 0
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
+#define HSMCI_SR_ENDRX (0x1u << 6) /**< \brief (HSMCI_SR) End of RX Buffer */
+#define HSMCI_SR_ENDTX (0x1u << 7) /**< \brief (HSMCI_SR) End of TX Buffer */
+#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
+#define HSMCI_SR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_SR) RX Buffer Full */
+#define HSMCI_SR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
+#define HSMCI_IER_ENDRX (0x1u << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */
+#define HSMCI_IER_ENDTX (0x1u << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */
+#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
+#define HSMCI_IER_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */
+#define HSMCI_IER_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
+#define HSMCI_IDR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */
+#define HSMCI_IDR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */
+#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
+#define HSMCI_IDR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */
+#define HSMCI_IDR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
+#define HSMCI_IMR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */
+#define HSMCI_IMR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */
+#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
+#define HSMCI_IMR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */
+#define HSMCI_IMR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
+#define HSMCI_WPMR_WP_KEY_Pos 8
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
+#define HSMCI_WPSR_WP_VS_Pos 0
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
+#define   HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
+#define   HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
+#define   HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
+#define   HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
+#define HSMCI_WPSR_WP_VSRC_Pos 8
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
+/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */
+#define HSMCI_RPR_RXPTR_Pos 0
+#define HSMCI_RPR_RXPTR_Msk (0xffffffffu << HSMCI_RPR_RXPTR_Pos) /**< \brief (HSMCI_RPR) Receive Pointer Register */
+#define HSMCI_RPR_RXPTR(value) ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos)))
+/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */
+#define HSMCI_RCR_RXCTR_Pos 0
+#define HSMCI_RCR_RXCTR_Msk (0xffffu << HSMCI_RCR_RXCTR_Pos) /**< \brief (HSMCI_RCR) Receive Counter Register */
+#define HSMCI_RCR_RXCTR(value) ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos)))
+/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */
+#define HSMCI_TPR_TXPTR_Pos 0
+#define HSMCI_TPR_TXPTR_Msk (0xffffffffu << HSMCI_TPR_TXPTR_Pos) /**< \brief (HSMCI_TPR) Transmit Counter Register */
+#define HSMCI_TPR_TXPTR(value) ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos)))
+/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */
+#define HSMCI_TCR_TXCTR_Pos 0
+#define HSMCI_TCR_TXCTR_Msk (0xffffu << HSMCI_TCR_TXCTR_Pos) /**< \brief (HSMCI_TCR) Transmit Counter Register */
+#define HSMCI_TCR_TXCTR(value) ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos)))
+/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */
+#define HSMCI_RNPR_RXNPTR_Pos 0
+#define HSMCI_RNPR_RXNPTR_Msk (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos) /**< \brief (HSMCI_RNPR) Receive Next Pointer */
+#define HSMCI_RNPR_RXNPTR(value) ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos)))
+/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */
+#define HSMCI_RNCR_RXNCTR_Pos 0
+#define HSMCI_RNCR_RXNCTR_Msk (0xffffu << HSMCI_RNCR_RXNCTR_Pos) /**< \brief (HSMCI_RNCR) Receive Next Counter */
+#define HSMCI_RNCR_RXNCTR(value) ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos)))
+/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define HSMCI_TNPR_TXNPTR_Pos 0
+#define HSMCI_TNPR_TXNPTR_Msk (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */
+#define HSMCI_TNPR_TXNPTR(value) ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos)))
+/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define HSMCI_TNCR_TXNCTR_Pos 0
+#define HSMCI_TNCR_TXNCTR_Msk (0xffffu << HSMCI_TNCR_TXNCTR_Pos) /**< \brief (HSMCI_TNCR) Transmit Counter Next */
+#define HSMCI_TNCR_TXNCTR(value) ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos)))
+/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */
+#define HSMCI_PTCR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */
+#define HSMCI_PTCR_RXTDIS (0x1u << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */
+#define HSMCI_PTCR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */
+#define HSMCI_PTCR_TXTDIS (0x1u << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */
+/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */
+#define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */
+#define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_HSMCI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_matrix.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_matrix.h
new file mode 100644
index 0000000..ab12261
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_matrix.h
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_MATRIX_COMPONENT_
+#define _SAM3S8_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Matrix hardware registers */
+typedef struct {
+  RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+  RoReg Reserved1[12];
+  RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+  RoReg Reserved2[11];
+  RwReg MATRIX_PRAS0;   /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+  RoReg Reserved3[1];
+  RwReg MATRIX_PRAS1;   /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+  RoReg Reserved4[1];
+  RwReg MATRIX_PRAS2;   /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+  RoReg Reserved5[1];
+  RwReg MATRIX_PRAS3;   /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+  RoReg Reserved6[1];
+  RwReg MATRIX_PRAS4;   /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
+  RoReg Reserved7[1];
+  RoReg Reserved8[27];
+  RwReg CCFG_SYSIO;     /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */
+  RoReg Reserved9[1];
+  RwReg CCFG_SMCNFCS;   /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */
+  RoReg Reserved10[49];
+  RwReg MATRIX_WPMR;    /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+  RoReg MATRIX_WPSR;    /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[5]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+#define MATRIX_PRAS0_M4PR_Pos 16
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+#define MATRIX_PRAS1_M4PR_Pos 16
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+#define MATRIX_PRAS2_M4PR_Pos 16
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+#define MATRIX_PRAS3_M4PR_Pos 16
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
+#define MATRIX_PRAS4_M0PR_Pos 0
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
+#define MATRIX_PRAS4_M1PR_Pos 4
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
+#define MATRIX_PRAS4_M2PR_Pos 8
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
+#define MATRIX_PRAS4_M3PR_Pos 12
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
+#define MATRIX_PRAS4_M4PR_Pos 16
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */
+#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */
+#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */
+#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */
+#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */
+#define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */
+#define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */
+/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */
+#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_MATRIX_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_pdc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_pdc.h
new file mode 100644
index 0000000..9022ab6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_pdc.h
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PDC_COMPONENT_
+#define _SAM3S8_PDC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_PDC Peripheral DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pdc hardware registers */
+typedef struct {
+  RwReg PERIPH_RPR;  /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
+  RwReg PERIPH_RCR;  /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
+  RwReg PERIPH_TPR;  /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
+  RwReg PERIPH_TCR;  /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
+  RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+  RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+  RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+  RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+  WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+  RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_PDC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_pio.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_pio.h
new file mode 100644
index 0000000..d151b9c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_pio.h
@@ -0,0 +1,1644 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PIO_COMPONENT_
+#define _SAM3S8_PIO_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pio hardware registers */
+typedef struct {
+  WoReg PIO_PER;        /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+  WoReg PIO_PDR;        /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+  RoReg PIO_PSR;        /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+  RoReg Reserved1[1];
+  WoReg PIO_OER;        /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+  WoReg PIO_ODR;        /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+  RoReg PIO_OSR;        /**< \brief (Pio Offset: 0x0018) Output Status Register */
+  RoReg Reserved2[1];
+  WoReg PIO_IFER;       /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+  WoReg PIO_IFDR;       /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+  RoReg PIO_IFSR;       /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+  RoReg Reserved3[1];
+  WoReg PIO_SODR;       /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+  WoReg PIO_CODR;       /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+  RwReg PIO_ODSR;       /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+  RoReg PIO_PDSR;       /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+  WoReg PIO_IER;        /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+  WoReg PIO_IDR;        /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+  RoReg PIO_IMR;        /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+  RoReg PIO_ISR;        /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+  WoReg PIO_MDER;       /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+  WoReg PIO_MDDR;       /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+  RoReg PIO_MDSR;       /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+  RoReg Reserved4[1];
+  WoReg PIO_PUDR;       /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+  WoReg PIO_PUER;       /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+  RoReg PIO_PUSR;       /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+  RoReg Reserved5[1];
+  RwReg PIO_ABCDSR[2];  /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
+  RoReg Reserved6[2];
+  WoReg PIO_IFSCDR;     /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */
+  WoReg PIO_IFSCER;     /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */
+  RoReg PIO_IFSCSR;     /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */
+  RwReg PIO_SCDR;       /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+  WoReg PIO_PPDDR;      /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
+  WoReg PIO_PPDER;      /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
+  RoReg PIO_PPDSR;      /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
+  RoReg Reserved7[1];
+  WoReg PIO_OWER;       /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+  WoReg PIO_OWDR;       /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+  RoReg PIO_OWSR;       /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+  RoReg Reserved8[1];
+  WoReg PIO_AIMER;      /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+  WoReg PIO_AIMDR;      /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
+  RoReg PIO_AIMMR;      /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+  RoReg Reserved9[1];
+  WoReg PIO_ESR;        /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+  WoReg PIO_LSR;        /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+  RoReg PIO_ELSR;       /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+  RoReg Reserved10[1];
+  WoReg PIO_FELLSR;     /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
+  WoReg PIO_REHLSR;     /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
+  RoReg PIO_FRLHSR;     /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+  RoReg Reserved11[1];
+  RoReg PIO_LOCKSR;     /**< \brief (Pio Offset: 0x00E0) Lock Status */
+  RwReg PIO_WPMR;       /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PIO_WPSR;       /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved12[5];
+  RwReg PIO_SCHMITT;    /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
+  RoReg Reserved13[19];
+  RwReg PIO_PCMR;       /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */
+  WoReg PIO_PCIER;      /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */
+  WoReg PIO_PCIDR;      /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */
+  RoReg PIO_PCIMR;      /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */
+  RoReg PIO_PCISR;      /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */
+  RoReg PIO_PCRHR;      /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */
+  RwReg PIO_RPR;        /**< \brief (Pio Offset: 0x168) Receive Pointer Register */
+  RwReg PIO_RCR;        /**< \brief (Pio Offset: 0x16C) Receive Counter Register */
+  RoReg Reserved14[2];
+  RwReg PIO_RNPR;       /**< \brief (Pio Offset: 0x178) Receive Next Pointer Register */
+  RwReg PIO_RNCR;       /**< \brief (Pio Offset: 0x17C) Receive Next Counter Register */
+  RoReg Reserved15[2];
+  WoReg PIO_PTCR;       /**< \brief (Pio Offset: 0x188) Transfer Control Register */
+  RoReg PIO_PTSR;       /**< \brief (Pio Offset: 0x18C) Transfer Status Register */
+} Pio;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
+/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
+#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
+#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
+#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
+#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR)  */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
+#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
+#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */
+/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
+#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
+/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
+#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT)  */
+/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */
+#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */
+#define PIO_PCMR_DSIZE_Pos 4
+#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */
+#define   PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a BYTE (8-bit) */
+#define   PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) */
+#define   PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a WORD (32-bit) */
+#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */
+#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */
+#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */
+/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */
+#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */
+#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */
+#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */
+#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */
+/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */
+#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */
+#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */
+#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */
+#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */
+/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */
+#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */
+#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */
+#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */
+#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */
+/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */
+#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */
+#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */
+#define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */
+#define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */
+/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */
+#define PIO_PCRHR_RDATA_Pos 0
+#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */
+/* -------- PIO_RPR : (PIO Offset: 0x168) Receive Pointer Register -------- */
+#define PIO_RPR_RXPTR_Pos 0
+#define PIO_RPR_RXPTR_Msk (0xffffffffu << PIO_RPR_RXPTR_Pos) /**< \brief (PIO_RPR) Receive Pointer Register */
+#define PIO_RPR_RXPTR(value) ((PIO_RPR_RXPTR_Msk & ((value) << PIO_RPR_RXPTR_Pos)))
+/* -------- PIO_RCR : (PIO Offset: 0x16C) Receive Counter Register -------- */
+#define PIO_RCR_RXCTR_Pos 0
+#define PIO_RCR_RXCTR_Msk (0xffffu << PIO_RCR_RXCTR_Pos) /**< \brief (PIO_RCR) Receive Counter Register */
+#define PIO_RCR_RXCTR(value) ((PIO_RCR_RXCTR_Msk & ((value) << PIO_RCR_RXCTR_Pos)))
+/* -------- PIO_RNPR : (PIO Offset: 0x178) Receive Next Pointer Register -------- */
+#define PIO_RNPR_RXNPTR_Pos 0
+#define PIO_RNPR_RXNPTR_Msk (0xffffffffu << PIO_RNPR_RXNPTR_Pos) /**< \brief (PIO_RNPR) Receive Next Pointer */
+#define PIO_RNPR_RXNPTR(value) ((PIO_RNPR_RXNPTR_Msk & ((value) << PIO_RNPR_RXNPTR_Pos)))
+/* -------- PIO_RNCR : (PIO Offset: 0x17C) Receive Next Counter Register -------- */
+#define PIO_RNCR_RXNCTR_Pos 0
+#define PIO_RNCR_RXNCTR_Msk (0xffffu << PIO_RNCR_RXNCTR_Pos) /**< \brief (PIO_RNCR) Receive Next Counter */
+#define PIO_RNCR_RXNCTR(value) ((PIO_RNCR_RXNCTR_Msk & ((value) << PIO_RNCR_RXNCTR_Pos)))
+/* -------- PIO_PTCR : (PIO Offset: 0x188) Transfer Control Register -------- */
+#define PIO_PTCR_RXTEN (0x1u << 0) /**< \brief (PIO_PTCR) Receiver Transfer Enable */
+#define PIO_PTCR_RXTDIS (0x1u << 1) /**< \brief (PIO_PTCR) Receiver Transfer Disable */
+#define PIO_PTCR_TXTEN (0x1u << 8) /**< \brief (PIO_PTCR) Transmitter Transfer Enable */
+#define PIO_PTCR_TXTDIS (0x1u << 9) /**< \brief (PIO_PTCR) Transmitter Transfer Disable */
+/* -------- PIO_PTSR : (PIO Offset: 0x18C) Transfer Status Register -------- */
+#define PIO_PTSR_RXTEN (0x1u << 0) /**< \brief (PIO_PTSR) Receiver Transfer Enable */
+#define PIO_PTSR_TXTEN (0x1u << 8) /**< \brief (PIO_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_PIO_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_pmc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_pmc.h
new file mode 100644
index 0000000..ea24ae7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_pmc.h
@@ -0,0 +1,393 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PMC_COMPONENT_
+#define _SAM3S8_PMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_PMC Power Management Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pmc hardware registers */
+typedef struct {
+  WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+  WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+  RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+  RoReg Reserved1[1];
+  WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+  WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+  RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+  RoReg Reserved2[1];
+  RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+  RwReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+  RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+  RwReg CKGR_PLLBR;    /**< \brief (Pmc Offset: 0x002C) PLLB Register */
+  RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+  RoReg Reserved3[1];
+  RwReg PMC_USB;       /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
+  RoReg Reserved4[1];
+  RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+  RoReg Reserved5[5];
+  WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+  WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+  RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
+  RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+  RwReg PMC_FSMR;      /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+  RwReg PMC_FSPR;      /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+  WoReg PMC_FOCR;      /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+  RoReg Reserved6[26];
+  RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved7[5];
+  WoReg PMC_PCER1;     /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
+  WoReg PMC_PCDR1;     /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
+  RoReg PMC_PCSR1;     /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
+  RoReg Reserved8[1];
+  RwReg PMC_OCR;       /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */
+} Pmc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */
+#define CKGR_PLLBR_DIVB_Pos 0
+#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */
+#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos)))
+#define CKGR_PLLBR_PLLBCOUNT_Pos 8
+#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */
+#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos)))
+#define CKGR_PLLBR_MULB_Pos 16
+#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */
+#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos)))
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define   PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLBClock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+#define PMC_MCKR_PLLBDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
+#define PMC_USB_USBDIV_Pos 8
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define   PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */
+#define   PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define   PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define   PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define   PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define   PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define   PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define   PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define   PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_LOCKB (0x1u << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_LOCKB (0x1u << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_LOCKB (0x1u << 2) /**< \brief (PMC_SR) PLLB Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_LOCKB (0x1u << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
+/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
+#define PMC_OCR_CAL4_Pos 0
+#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */
+#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
+#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */
+#define PMC_OCR_CAL8_Pos 8
+#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */
+#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
+#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */
+#define PMC_OCR_CAL12_Pos 16
+#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */
+#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
+#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_PMC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_pwm.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_pwm.h
new file mode 100644
index 0000000..0dc6fe1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_pwm.h
@@ -0,0 +1,545 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PWM_COMPONENT_
+#define _SAM3S8_PWM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+  RwReg      PWM_CMR;       /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+  RwReg      PWM_CDTY;      /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+  RwReg      PWM_CDTYUPD;   /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
+  RwReg      PWM_CPRD;      /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
+  RwReg      PWM_CPRDUPD;   /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
+  RwReg      PWM_CCNT;      /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
+  RwReg      PWM_DT;        /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
+  RwReg      PWM_DTUPD;     /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
+} PwmCh_num;
+/** \brief PwmCmp hardware registers */
+typedef struct {
+  RwReg      PWM_CMPV;      /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
+  RwReg      PWM_CMPVUPD;   /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
+  RwReg      PWM_CMPM;      /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
+  RwReg      PWM_CMPMUPD;   /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
+} PwmCmp;
+/** \brief Pwm hardware registers */
+#define PWMCMP_NUMBER 8
+#define PWMCH_NUM_NUMBER 4
+typedef struct {
+  RwReg      PWM_CLK;       /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
+  WoReg      PWM_ENA;       /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+  WoReg      PWM_DIS;       /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+  RoReg      PWM_SR;        /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+  WoReg      PWM_IER1;      /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
+  WoReg      PWM_IDR1;      /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
+  RoReg      PWM_IMR1;      /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
+  RoReg      PWM_ISR1;      /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
+  RwReg      PWM_SCM;       /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      PWM_SCUC;      /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
+  RwReg      PWM_SCUP;      /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
+  WoReg      PWM_SCUPUPD;   /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
+  WoReg      PWM_IER2;      /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
+  WoReg      PWM_IDR2;      /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
+  RoReg      PWM_IMR2;      /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
+  RoReg      PWM_ISR2;      /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
+  RwReg      PWM_OOV;       /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
+  RwReg      PWM_OS;        /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
+  WoReg      PWM_OSS;       /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
+  WoReg      PWM_OSC;       /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
+  WoReg      PWM_OSSUPD;    /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
+  WoReg      PWM_OSCUPD;    /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
+  RwReg      PWM_FMR;       /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
+  RoReg      PWM_FSR;       /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
+  WoReg      PWM_FCR;       /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
+  RwReg      PWM_FPV;       /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
+  RwReg      PWM_FPE;       /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
+  RoReg      Reserved2[3];
+  RwReg      PWM_ELMR[2];   /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
+  RoReg      Reserved3[11];
+  RwReg      PWM_SMMR;      /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
+  RoReg      Reserved4[12];
+  WoReg      PWM_WPCR;      /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
+  RoReg      PWM_WPSR;      /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
+  RoReg      Reserved5[7];
+  RwReg      PWM_TPR;       /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
+  RwReg      PWM_TCR;       /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
+  RoReg      Reserved6[2];
+  RwReg      PWM_TNPR;      /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
+  RwReg      PWM_TNCR;      /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
+  WoReg      PWM_PTCR;      /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
+  RoReg      PWM_PTSR;      /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
+  RoReg      Reserved7[2];
+  PwmCmp     PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
+  RoReg      Reserved8[20];
+  PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
+} Pwm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
+#define PWM_CLK_DIVA_Pos 0
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
+#define PWM_CLK_PREA_Pos 8
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
+#define PWM_CLK_DIVB_Pos 16
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
+#define PWM_CLK_PREB_Pos 24
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
+#define PWM_SCM_UPDM_Pos 16
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
+#define   PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
+#define PWM_SCM_PTRCS_Pos 21
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
+#define PWM_SCUP_UPR_Pos 0
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
+#define PWM_SCUP_UPRCNT_Pos 4
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
+#define PWM_SCUPUPD_UPRUPD_Pos 0
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
+#define PWM_FMR_FPOL_Pos 0
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
+#define PWM_FMR_FMOD_Pos 8
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
+#define PWM_FMR_FFIL_Pos 16
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
+#define PWM_FSR_FIV_Pos 0
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */
+#define PWM_FSR_FS_Pos 8
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
+#define PWM_FCR_FCLR_Pos 0
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
+#define PWM_FPE_FPE0_Pos 0
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
+#define PWM_FPE_FPE1_Pos 8
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
+#define PWM_FPE_FPE2_Pos 16
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
+#define PWM_FPE_FPE3_Pos 24
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
+#define PWM_WPCR_WPCMD_Pos 0
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
+#define PWM_WPCR_WPKEY_Pos 8
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPVSRC_Pos 16
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
+#define PWM_TPR_TXPTR_Pos 0
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
+#define PWM_TCR_TXCTR_Pos 0
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
+#define PWM_TNPR_TXNPTR_Pos 0
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
+#define PWM_TNCR_TXNCTR_Pos 0
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
+#define PWM_CMPV_CV_Pos 0
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
+#define PWM_CMPVUPD_CVUPD_Pos 0
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
+#define PWM_CMPM_CTR_Pos 4
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
+#define PWM_CMPM_CPR_Pos 8
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
+#define PWM_CMPM_CPRCNT_Pos 12
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
+#define PWM_CMPM_CUPR_Pos 16
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
+#define PWM_CMPM_CUPRCNT_Pos 20
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
+#define PWM_CMPMUPD_CTRUPD_Pos 4
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
+#define PWM_CMPMUPD_CPRUPD_Pos 8
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
+#define PWM_CMPMUPD_CUPRUPD_Pos 16
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
+#define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
+#define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
+#define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
+#define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
+#define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
+#define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
+#define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
+#define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
+#define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
+#define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
+#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
+#define PWM_CDTYUPD_CDTYUPD_Pos 0
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
+#define PWM_CPRDUPD_CPRDUPD_Pos 0
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
+#define PWM_DT_DTH_Pos 0
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
+#define PWM_DT_DTL_Pos 16
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
+#define PWM_DTUPD_DTHUPD_Pos 0
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
+#define PWM_DTUPD_DTLUPD_Pos 16
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S8_PWM_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_rstc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_rstc.h
new file mode 100644
index 0000000..2e3ab17
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_rstc.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_RSTC_COMPONENT_
+#define _SAM3S8_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_RSTC Reset Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rstc hardware registers */
+typedef struct {
+  WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+  RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+  RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S8_RSTC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_rtc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_rtc.h
new file mode 100644
index 0000000..509e0ba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_rtc.h
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_RTC_COMPONENT_
+#define _SAM3S8_RTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_RTC Real-time Clock */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtc hardware registers */
+typedef struct {
+  RwReg RTC_CR;     /**< \brief (Rtc Offset: 0x00) Control Register */
+  RwReg RTC_MR;     /**< \brief (Rtc Offset: 0x04) Mode Register */
+  RwReg RTC_TIMR;   /**< \brief (Rtc Offset: 0x08) Time Register */
+  RwReg RTC_CALR;   /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+  RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+  RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+  RoReg RTC_SR;     /**< \brief (Rtc Offset: 0x18) Status Register */
+  WoReg RTC_SCCR;   /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+  WoReg RTC_IER;    /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+  WoReg RTC_IDR;    /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+  RoReg RTC_IMR;    /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+  RoReg RTC_VER;    /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */
+#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */
+#define RTC_MR_CORRECTION_Pos 8
+#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR)  */
+#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))
+#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */
+#define RTC_MR_OUT0_Pos 16
+#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 Output Source Selection */
+#define   RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) no waveform, stuck at '0' */
+#define   RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */
+#define   RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */
+#define   RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */
+#define   RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */
+#define   RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) output toggles when alarm flag rises */
+#define   RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) output is a copy of the alarm flag */
+#define   RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) duty cycle programmable pulse */
+#define RTC_MR_OUT1_Pos 20
+#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */
+#define   RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) no waveform, stuck at '0' */
+#define   RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */
+#define   RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */
+#define   RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */
+#define   RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */
+#define   RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) output toggles when alarm flag rises */
+#define   RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) output is a copy of the alarm flag */
+#define   RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) duty cycle programmable pulse */
+#define RTC_MR_THIGH_Pos 24
+#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */
+#define   RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */
+#define   RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */
+#define   RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */
+#define   RTC_MR_THIGH_H_967US (0x3u << 24) /**< \brief (RTC_MR) 967 \xb5 s */
+#define   RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 \xb5 s */
+#define   RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 \xb5 s */
+#define   RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 \xb5 s */
+#define   RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 \xb5 s */
+#define RTC_MR_TPERIOD_Pos 28
+#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */
+#define   RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */
+#define   RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */
+#define   RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */
+#define   RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_RTC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_rtt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_rtt.h
new file mode 100644
index 0000000..8143794
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_rtt.h
@@ -0,0 +1,71 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_RTT_COMPONENT_
+#define _SAM3S8_RTT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_RTT Real-time Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtt hardware registers */
+typedef struct {
+  RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+  RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+  RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+  RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */
+#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_RTT_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_smc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_smc.h
new file mode 100644
index 0000000..a727cfa
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_smc.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SMC_COMPONENT_
+#define _SAM3S8_SMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Static Memory Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_SMC Static Memory Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief SmcCs_number hardware registers */
+typedef struct {
+  RwReg         SMC_SETUP;        /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
+  RwReg         SMC_PULSE;        /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
+  RwReg         SMC_CYCLE;        /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
+  RwReg         SMC_MODE;         /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */
+} SmcCs_number;
+/** \brief Smc hardware registers */
+#define SMCCS_NUMBER_NUMBER 5
+typedef struct {
+  SmcCs_number  SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */
+  RoReg         Reserved1[12];
+  RwReg         SMC_OCMS;         /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */
+  WoReg         SMC_KEY1;         /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */
+  WoReg         SMC_KEY2;         /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */
+  RoReg         Reserved2[22];
+  RwReg         SMC_WPMR;         /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */
+  RoReg         SMC_WPSR;         /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */
+} Smc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
+#define SMC_SETUP_NWE_SETUP_Pos 0
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
+#define SMC_SETUP_NRD_SETUP_Pos 16
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
+#define SMC_PULSE_NWE_PULSE_Pos 0
+#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
+#define SMC_PULSE_NRD_PULSE_Pos 16
+#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
+#define SMC_CYCLE_NWE_CYCLE_Pos 0
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
+#define SMC_CYCLE_NRD_CYCLE_Pos 16
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE)  */
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE)  */
+#define SMC_MODE_EXNW_MODE_Pos 4
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
+#define   SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
+#define   SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
+#define   SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
+#define SMC_MODE_DBW_Pos 12
+#define SMC_MODE_DBW_Msk (0x3u << SMC_MODE_DBW_Pos) /**< \brief (SMC_MODE) Data Bus Width */
+#define   SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
+#define   SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
+#define   SMC_MODE_DBW_32_BIT (0x2u << 12) /**< \brief (SMC_MODE) 32-bit bus */
+#define SMC_MODE_TDF_CYCLES_Pos 16
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
+#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */
+#define SMC_MODE_PS_Pos 28
+#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */
+#define   SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */
+#define   SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */
+#define   SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */
+#define   SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */
+/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
+#define SMC_OCMS_CS0SE (0x1u << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS1SE (0x1u << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS2SE (0x1u << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS3SE (0x1u << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */
+#define SMC_KEY1_KEY1_Pos 0
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
+/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */
+#define SMC_KEY2_KEY2_Pos 0
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
+/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */
+#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */
+#define SMC_WPMR_WPKEY_Pos 8
+#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */
+#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
+/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */
+#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */
+#define SMC_WPSR_WPVSRC_Pos 8
+#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_SMC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_spi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_spi.h
new file mode 100644
index 0000000..379ec38
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_spi.h
@@ -0,0 +1,226 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SPI_COMPONENT_
+#define _SAM3S8_SPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_SPI Serial Peripheral Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Spi hardware registers */
+typedef struct {
+  WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
+  RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
+  RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
+  WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+  RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
+  WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+  WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+  RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+  RoReg Reserved1[4];
+  RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
+  RoReg Reserved2[41];
+  RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+  RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved3[5];
+  RwReg SPI_RPR;       /**< \brief (Spi Offset: 0x100) Receive Pointer Register */
+  RwReg SPI_RCR;       /**< \brief (Spi Offset: 0x104) Receive Counter Register */
+  RwReg SPI_TPR;       /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */
+  RwReg SPI_TCR;       /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */
+  RwReg SPI_RNPR;      /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */
+  RwReg SPI_RNCR;      /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */
+  RwReg SPI_TNPR;      /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg SPI_TNCR;      /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg SPI_PTCR;      /**< \brief (Spi Offset: 0x120) Transfer Control Register */
+  RoReg SPI_PTSR;      /**< \brief (Spi Offset: 0x124) Transfer Status Register */
+} Spi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */
+#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */
+#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */
+#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */
+#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */
+#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */
+#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */
+#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */
+#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */
+#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */
+#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */
+#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */
+#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */
+#define SPI_WPMR_WPKEY_Pos 8
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */
+#define SPI_WPSR_WPVSRC_Pos 8
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */
+/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */
+#define SPI_RPR_RXPTR_Pos 0
+#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */
+#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))
+/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */
+#define SPI_RCR_RXCTR_Pos 0
+#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */
+#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))
+/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */
+#define SPI_TPR_TXPTR_Pos 0
+#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */
+#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))
+/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */
+#define SPI_TCR_TXCTR_Pos 0
+#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */
+#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))
+/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */
+#define SPI_RNPR_RXNPTR_Pos 0
+#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */
+#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))
+/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */
+#define SPI_RNCR_RXNCTR_Pos 0
+#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */
+#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))
+/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define SPI_TNPR_TXNPTR_Pos 0
+#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */
+#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))
+/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define SPI_TNCR_TXNCTR_Pos 0
+#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */
+#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))
+/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */
+#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */
+#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */
+#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */
+#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */
+/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */
+#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */
+#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_SPI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_ssc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_ssc.h
new file mode 100644
index 0000000..7130b8e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_ssc.h
@@ -0,0 +1,337 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SSC_COMPONENT_
+#define _SAM3S8_SSC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_SSC Synchronous Serial Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Ssc hardware registers */
+typedef struct {
+  WoReg SSC_CR;        /**< \brief (Ssc Offset: 0x0) Control Register */
+  RwReg SSC_CMR;       /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
+  RoReg Reserved1[2];
+  RwReg SSC_RCMR;      /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
+  RwReg SSC_RFMR;      /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
+  RwReg SSC_TCMR;      /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
+  RwReg SSC_TFMR;      /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
+  RoReg SSC_RHR;       /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
+  WoReg SSC_THR;       /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
+  RoReg Reserved2[2];
+  RoReg SSC_RSHR;      /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
+  RwReg SSC_TSHR;      /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
+  RwReg SSC_RC0R;      /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
+  RwReg SSC_RC1R;      /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
+  RoReg SSC_SR;        /**< \brief (Ssc Offset: 0x40) Status Register */
+  WoReg SSC_IER;       /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
+  WoReg SSC_IDR;       /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
+  RoReg SSC_IMR;       /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved3[37];
+  RwReg SSC_WPMR;      /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
+  RoReg SSC_WPSR;      /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[5];
+  RwReg SSC_RPR;       /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */
+  RwReg SSC_RCR;       /**< \brief (Ssc Offset: 0x104) Receive Counter Register */
+  RwReg SSC_TPR;       /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */
+  RwReg SSC_TCR;       /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */
+  RwReg SSC_RNPR;      /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */
+  RwReg SSC_RNCR;      /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */
+  RwReg SSC_TNPR;      /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg SSC_TNCR;      /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg SSC_PTCR;      /**< \brief (Ssc Offset: 0x120) Transfer Control Register */
+  RoReg SSC_PTSR;      /**< \brief (Ssc Offset: 0x124) Transfer Status Register */
+} Ssc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
+#define SSC_CMR_DIV_Pos 0
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
+#define SSC_RCMR_CKS_Pos 0
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
+#define   SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
+#define   SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
+#define   SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
+#define SSC_RCMR_CKO_Pos 2
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
+#define   SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
+#define SSC_RCMR_CKG_Pos 6
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
+#define   SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_START_Pos 8
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
+#define   SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define   SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
+#define   SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
+#define   SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
+#define   SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
+#define   SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
+#define   SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
+#define   SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
+#define   SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
+#define SSC_RCMR_STTDLY_Pos 16
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
+#define SSC_RCMR_PERIOD_Pos 24
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
+#define SSC_RFMR_DATLEN_Pos 0
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
+#define SSC_RFMR_DATNB_Pos 8
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
+#define SSC_RFMR_FSLEN_Pos 16
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
+#define SSC_RFMR_FSOS_Pos 20
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
+#define   SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
+#define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
+#define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
+#define   SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
+#define   SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
+#define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
+#define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
+#define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
+#define SSC_RFMR_FSLEN_EXT_Pos 28
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
+#define SSC_TCMR_CKS_Pos 0
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
+#define   SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
+#define   SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
+#define   SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
+#define SSC_TCMR_CKO_Pos 2
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
+#define   SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
+#define   SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
+#define SSC_TCMR_CKG_Pos 6
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
+#define   SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
+#define   SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
+#define SSC_TCMR_START_Pos 8
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
+#define   SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
+#define   SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
+#define   SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
+#define   SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
+#define   SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
+#define   SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
+#define   SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
+#define   SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
+#define   SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
+#define SSC_TCMR_STTDLY_Pos 16
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
+#define SSC_TCMR_PERIOD_Pos 24
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
+#define SSC_TFMR_DATLEN_Pos 0
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
+#define SSC_TFMR_DATNB_Pos 8
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
+#define SSC_TFMR_FSLEN_Pos 16
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
+#define SSC_TFMR_FSOS_Pos 20
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
+#define   SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
+#define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
+#define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
+#define   SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
+#define   SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
+#define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
+#define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
+#define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
+#define SSC_TFMR_FSLEN_EXT_Pos 28
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
+#define SSC_RHR_RDAT_Pos 0
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
+#define SSC_THR_TDAT_Pos 0
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
+#define SSC_RSHR_RSDAT_Pos 0
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
+#define SSC_TSHR_TSDAT_Pos 0
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
+#define SSC_RC0R_CP0_Pos 0
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
+#define SSC_RC1R_CP1_Pos 0
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
+#define SSC_SR_ENDTX (0x1u << 2) /**< \brief (SSC_SR) End of Transmission */
+#define SSC_SR_TXBUFE (0x1u << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
+#define SSC_SR_ENDRX (0x1u << 6) /**< \brief (SSC_SR) End of Reception */
+#define SSC_SR_RXBUFF (0x1u << 7) /**< \brief (SSC_SR) Receive Buffer Full */
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
+#define SSC_IER_ENDTX (0x1u << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */
+#define SSC_IER_TXBUFE (0x1u << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
+#define SSC_IER_ENDRX (0x1u << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */
+#define SSC_IER_RXBUFF (0x1u << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
+#define SSC_IDR_ENDTX (0x1u << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */
+#define SSC_IDR_TXBUFE (0x1u << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
+#define SSC_IDR_ENDRX (0x1u << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */
+#define SSC_IDR_RXBUFF (0x1u << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
+#define SSC_IMR_ENDTX (0x1u << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */
+#define SSC_IMR_TXBUFE (0x1u << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
+#define SSC_IMR_ENDRX (0x1u << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */
+#define SSC_IMR_RXBUFF (0x1u << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
+#define SSC_WPMR_WPKEY_Pos 8
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
+#define SSC_WPSR_WPVSRC_Pos 8
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
+/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */
+#define SSC_RPR_RXPTR_Pos 0
+#define SSC_RPR_RXPTR_Msk (0xffffffffu << SSC_RPR_RXPTR_Pos) /**< \brief (SSC_RPR) Receive Pointer Register */
+#define SSC_RPR_RXPTR(value) ((SSC_RPR_RXPTR_Msk & ((value) << SSC_RPR_RXPTR_Pos)))
+/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */
+#define SSC_RCR_RXCTR_Pos 0
+#define SSC_RCR_RXCTR_Msk (0xffffu << SSC_RCR_RXCTR_Pos) /**< \brief (SSC_RCR) Receive Counter Register */
+#define SSC_RCR_RXCTR(value) ((SSC_RCR_RXCTR_Msk & ((value) << SSC_RCR_RXCTR_Pos)))
+/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */
+#define SSC_TPR_TXPTR_Pos 0
+#define SSC_TPR_TXPTR_Msk (0xffffffffu << SSC_TPR_TXPTR_Pos) /**< \brief (SSC_TPR) Transmit Counter Register */
+#define SSC_TPR_TXPTR(value) ((SSC_TPR_TXPTR_Msk & ((value) << SSC_TPR_TXPTR_Pos)))
+/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */
+#define SSC_TCR_TXCTR_Pos 0
+#define SSC_TCR_TXCTR_Msk (0xffffu << SSC_TCR_TXCTR_Pos) /**< \brief (SSC_TCR) Transmit Counter Register */
+#define SSC_TCR_TXCTR(value) ((SSC_TCR_TXCTR_Msk & ((value) << SSC_TCR_TXCTR_Pos)))
+/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */
+#define SSC_RNPR_RXNPTR_Pos 0
+#define SSC_RNPR_RXNPTR_Msk (0xffffffffu << SSC_RNPR_RXNPTR_Pos) /**< \brief (SSC_RNPR) Receive Next Pointer */
+#define SSC_RNPR_RXNPTR(value) ((SSC_RNPR_RXNPTR_Msk & ((value) << SSC_RNPR_RXNPTR_Pos)))
+/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */
+#define SSC_RNCR_RXNCTR_Pos 0
+#define SSC_RNCR_RXNCTR_Msk (0xffffu << SSC_RNCR_RXNCTR_Pos) /**< \brief (SSC_RNCR) Receive Next Counter */
+#define SSC_RNCR_RXNCTR(value) ((SSC_RNCR_RXNCTR_Msk & ((value) << SSC_RNCR_RXNCTR_Pos)))
+/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define SSC_TNPR_TXNPTR_Pos 0
+#define SSC_TNPR_TXNPTR_Msk (0xffffffffu << SSC_TNPR_TXNPTR_Pos) /**< \brief (SSC_TNPR) Transmit Next Pointer */
+#define SSC_TNPR_TXNPTR(value) ((SSC_TNPR_TXNPTR_Msk & ((value) << SSC_TNPR_TXNPTR_Pos)))
+/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define SSC_TNCR_TXNCTR_Pos 0
+#define SSC_TNCR_TXNCTR_Msk (0xffffu << SSC_TNCR_TXNCTR_Pos) /**< \brief (SSC_TNCR) Transmit Counter Next */
+#define SSC_TNCR_TXNCTR(value) ((SSC_TNCR_TXNCTR_Msk & ((value) << SSC_TNCR_TXNCTR_Pos)))
+/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */
+#define SSC_PTCR_RXTEN (0x1u << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */
+#define SSC_PTCR_RXTDIS (0x1u << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */
+#define SSC_PTCR_TXTEN (0x1u << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */
+#define SSC_PTCR_TXTDIS (0x1u << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */
+/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */
+#define SSC_PTSR_RXTEN (0x1u << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */
+#define SSC_PTSR_TXTEN (0x1u << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_SSC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_supc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_supc.h
new file mode 100644
index 0000000..e266163
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_supc.h
@@ -0,0 +1,322 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SUPC_COMPONENT_
+#define _SAM3S8_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_SUPC Supply Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Supc hardware registers */
+typedef struct {
+  WoReg SUPC_CR;   /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+  RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+  RwReg SUPC_MR;   /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+  RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+  RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+  RoReg SUPC_SR;   /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */
+#define   SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */
+#define   SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP0 */
+#define   SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is not connected with low power debouncer. */
+#define   SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is connected with low power debouncer and can force a core wake up. */
+#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP1 */
+#define   SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) the WKUP1input pin is not connected with low power debouncer. */
+#define   SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) the WKUP1 input pin is connected with low power debouncer and can force a core wake up. */
+#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low power Debouncer Clear */
+#define   SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) a low power debounce event does not create an immediate clear on first half GPBR registers. */
+#define   SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers. */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+#define SUPC_WUMR_LPDBC_Pos 16
+#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low Power DeBounCer Period */
+#define   SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low power debouncer. */
+#define   SUPC_WUMR_LPDBC_2_RTCOUT0 (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 2 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_3_RTCOUT0 (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 3 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_4_RTCOUT0 (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 4 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_5_RTCOUT0 (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 5 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_6_RTCOUT0 (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 6 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_7_RTCOUT0 (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 7 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_8_RTCOUT0 (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 8 RTCOUT0 periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define   SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define   SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define   SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define   SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define   SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define   SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define   SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define   SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define   SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define   SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define   SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define   SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define   SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define   SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define   SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define   SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Type 0 */
+#define   SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Type 1 */
+#define   SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Type 2 */
+#define   SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Type 3 */
+#define   SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Type 4 */
+#define   SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Type 5 */
+#define   SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Type 6 */
+#define   SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Type 7 */
+#define   SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Type 8 */
+#define   SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Type 9 */
+#define   SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Type 10 */
+#define   SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Type 11 */
+#define   SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Type 12 */
+#define   SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Type 13 */
+#define   SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Type 14 */
+#define   SUPC_WUIR_WKUPT14_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT14_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Type 15 */
+#define   SUPC_WUIR_WKUPT15_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT15_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define   SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define   SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define   SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define   SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define   SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define   SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define   SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */
+#define   SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define   SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP0 */
+#define   SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP1 */
+#define   SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_SUPC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_tc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_tc.h
new file mode 100644
index 0000000..1b28eff
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_tc.h
@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_TC_COMPONENT_
+#define _SAM3S8_TC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_TC Timer Counter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief TcChannel hardware registers */
+typedef struct {
+  RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+  RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+  RwReg      TC_SMMR;       /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
+  RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
+  RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
+  RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
+  RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
+  RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+  RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+  RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+  RoReg      Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+  TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+  WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
+  RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+  WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+  WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+  RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+  RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+  RwReg      TC_FMR;        /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
+  RoReg      Reserved1[2];
+  RwReg      TC_WPMR;       /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
+#define TC_WPMR_WPKEY_Pos 8
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3S8_TC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_twi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_twi.h
new file mode 100644
index 0000000..5c3279d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_twi.h
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_TWI_COMPONENT_
+#define _SAM3S8_TWI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_TWI Two-wire Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Twi hardware registers */
+typedef struct {
+  WoReg TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
+  RwReg TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
+  RwReg TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+  RwReg TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+  RwReg TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+  RoReg Reserved1[3];
+  RoReg TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
+  WoReg TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+  WoReg TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+  RoReg TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+  RoReg TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+  WoReg TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+  RoReg Reserved2[50];
+  RwReg TWI_RPR;       /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+  RwReg TWI_RCR;       /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+  RwReg TWI_TPR;       /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+  RwReg TWI_TCR;       /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+  RwReg TWI_RNPR;      /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+  RwReg TWI_RNCR;      /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+  RwReg TWI_TNPR;      /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg TWI_TNCR;      /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg TWI_PTCR;      /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+  RoReg TWI_PTSR;      /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_TWI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_uart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_uart.h
new file mode 100644
index 0000000..0a7bc93
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_uart.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_UART_COMPONENT_
+#define _SAM3S8_UART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Uart hardware registers */
+typedef struct {
+  WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
+  RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
+  WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+  WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+  RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+  RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
+  RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+  WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+  RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+  RoReg Reserved1[55];
+  RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+  RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+  RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+  RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+  RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+  RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+  RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+  RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_UART_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_udp.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_udp.h
new file mode 100644
index 0000000..afae77b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_udp.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_UDP_COMPONENT_
+#define _SAM3S8_UDP_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR USB Device Port */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_UDP USB Device Port */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Udp hardware registers */
+typedef struct {
+  RoReg UDP_FRM_NUM;  /**< \brief (Udp Offset: 0x000) Frame Number Register */
+  RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */
+  RwReg UDP_FADDR;    /**< \brief (Udp Offset: 0x008) Function Address Register */
+  RoReg Reserved1[1];
+  WoReg UDP_IER;      /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */
+  WoReg UDP_IDR;      /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */
+  RoReg UDP_IMR;      /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */
+  RoReg UDP_ISR;      /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */
+  WoReg UDP_ICR;      /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */
+  RoReg Reserved2[1];
+  RwReg UDP_RST_EP;   /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */
+  RoReg Reserved3[1];
+  RwReg UDP_CSR[8];   /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */
+  RwReg UDP_FDR[8];   /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */
+  RoReg Reserved4[1];
+  RwReg UDP_TXVC;     /**< \brief (Udp Offset: 0x074) Transceiver Control Register */
+} Udp;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */
+#define UDP_FRM_NUM_FRM_NUM_Pos 0
+#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */
+#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */
+#define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */
+/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */
+#define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */
+#define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */
+#define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */
+#define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT)  */
+#define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */
+/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */
+#define UDP_FADDR_FADD_Pos 0
+#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */
+#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos)))
+#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */
+#define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */
+#define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */
+#define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */
+#define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */
+#define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */
+#define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */
+#define UDP_IER_EP6INT (0x1u << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */
+#define UDP_IER_EP7INT (0x1u << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */
+#define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */
+#define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */
+#define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER)  */
+#define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */
+#define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */
+#define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */
+#define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */
+#define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */
+#define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */
+#define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */
+#define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */
+#define UDP_IDR_EP6INT (0x1u << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */
+#define UDP_IDR_EP7INT (0x1u << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */
+#define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */
+#define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */
+#define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR)  */
+#define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */
+#define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */
+/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */
+#define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */
+#define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */
+#define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */
+#define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */
+#define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */
+#define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */
+#define UDP_IMR_EP6INT (0x1u << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */
+#define UDP_IMR_EP7INT (0x1u << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */
+#define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */
+#define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */
+#define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR)  */
+#define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */
+#define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */
+#define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */
+/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */
+#define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */
+#define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */
+#define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */
+#define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */
+#define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */
+#define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */
+#define UDP_ISR_EP6INT (0x1u << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */
+#define UDP_ISR_EP7INT (0x1u << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */
+#define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */
+#define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
+#define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR)  */
+#define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */
+#define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */
+#define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
+/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */
+#define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */
+#define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */
+#define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR)  */
+#define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */
+#define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */
+#define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */
+/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */
+#define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */
+#define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */
+#define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */
+#define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */
+#define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */
+#define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */
+#define UDP_RST_EP_EP6 (0x1u << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */
+#define UDP_RST_EP_EP7 (0x1u << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */
+/* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */
+#define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */
+#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */
+#define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[8]) Received Setup */
+#define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */
+#define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */
+#define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */
+#define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */
+#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */
+#define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */
+#define UDP_CSR_EPTYPE_Pos 8
+#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */
+#define   UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */
+#define   UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */
+#define   UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */
+#define   UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */
+#define   UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */
+#define   UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */
+#define   UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */
+#define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[8]) Data Toggle */
+#define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */
+#define UDP_CSR_RXBYTECNT_Pos 16
+#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */
+#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos)))
+/* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */
+#define UDP_FDR_FIFO_DATA_Pos 0
+#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[8]) FIFO Data Value */
+#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos)))
+/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */
+#define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */
+#define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pullup On */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_UDP_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_usart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_usart.h
new file mode 100644
index 0000000..134e4fd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_usart.h
@@ -0,0 +1,361 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_USART_COMPONENT_
+#define _SAM3S8_USART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Usart hardware registers */
+typedef struct {
+  WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
+  RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
+  WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+  WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+  RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+  RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+  RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+  WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+  RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+  RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+  RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+  RoReg Reserved1[5];
+  RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+  RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+  RoReg Reserved2[1];
+  RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+  RwReg US_MAN;        /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
+  RoReg Reserved3[36];
+  RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+  RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[4];
+  RoReg US_VERSION;    /**< \brief (Usart Offset: 0xFC) Version Register */
+  RwReg US_RPR;        /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+  RwReg US_RCR;        /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+  RwReg US_TPR;        /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+  RwReg US_TCR;        /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+  RwReg US_RNPR;       /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+  RwReg US_RNCR;       /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+  RwReg US_TNPR;       /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg US_TNCR;       /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg US_PTCR;       /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+  RoReg US_PTSR;       /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */
+#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
+#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define   US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */
+#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
+#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */
+#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */
+#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
+#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */
+#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */
+#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
+#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */
+#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */
+#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
+#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */
+#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */
+#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */
+#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */
+#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
+#define US_MAN_TX_PL_Pos 0
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
+#define US_MAN_TX_PP_Pos 8
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
+#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
+#define US_MAN_RX_PL_Pos 16
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
+#define US_MAN_RX_PP_Pos 24
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
+#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN)  */
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */
+#define US_VERSION_VERSION_Pos 0
+#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION)  */
+#define US_VERSION_MFN_Pos 16
+#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION)  */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_USART_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_wdt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_wdt.h
new file mode 100644
index 0000000..f7906e8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/component/component_wdt.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_WDT_COMPONENT_
+#define _SAM3S8_WDT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3S8_WDT Watchdog Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Wdt hardware registers */
+typedef struct {
+  WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+  RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+  RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAM3S8_WDT_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_acc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_acc.h
new file mode 100644
index 0000000..b1ca07c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_acc.h
@@ -0,0 +1,56 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_ACC_INSTANCE_
+#define _SAM3S8_ACC_INSTANCE_
+
+/* ========== Register definition for ACC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ACC_CR            (0x40040000U) /**< \brief (ACC) Control Register */
+#define REG_ACC_MR            (0x40040004U) /**< \brief (ACC) Mode Register */
+#define REG_ACC_IER           (0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
+#define REG_ACC_IDR           (0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
+#define REG_ACC_IMR           (0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
+#define REG_ACC_ISR           (0x40040030U) /**< \brief (ACC) Interrupt Status Register */
+#define REG_ACC_ACR           (0x40040094U) /**< \brief (ACC) Analog Control Register */
+#define REG_ACC_WPMR          (0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
+#define REG_ACC_WPSR          (0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
+#else
+#define REG_ACC_CR   (*(WoReg*)0x40040000U) /**< \brief (ACC) Control Register */
+#define REG_ACC_MR   (*(RwReg*)0x40040004U) /**< \brief (ACC) Mode Register */
+#define REG_ACC_IER  (*(WoReg*)0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
+#define REG_ACC_IDR  (*(WoReg*)0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
+#define REG_ACC_IMR  (*(RoReg*)0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
+#define REG_ACC_ISR  (*(RoReg*)0x40040030U) /**< \brief (ACC) Interrupt Status Register */
+#define REG_ACC_ACR  (*(RwReg*)0x40040094U) /**< \brief (ACC) Analog Control Register */
+#define REG_ACC_WPMR (*(RwReg*)0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
+#define REG_ACC_WPSR (*(RoReg*)0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_ACC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_adc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_adc.h
new file mode 100644
index 0000000..461d1fb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_adc.h
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_ADC_INSTANCE_
+#define _SAM3S8_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CR               (0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR               (0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1            (0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2            (0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER             (0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR             (0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR             (0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR             (0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER              (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR              (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR              (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR              (0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER             (0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR              (0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR              (0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR              (0x40038048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR              (0x4003804CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR              (0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR              (0x40038094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR             (0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR             (0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR              (0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR              (0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR             (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR             (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR             (0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR             (0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#else
+#define REG_ADC_CR      (*(WoReg*)0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR      (*(RwReg*)0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1   (*(RwReg*)0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2   (*(RwReg*)0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER    (*(WoReg*)0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR    (*(WoReg*)0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR    (*(RoReg*)0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR    (*(RoReg*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER     (*(WoReg*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR     (*(WoReg*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR     (*(RoReg*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR     (*(RoReg*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER    (*(RoReg*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR     (*(RwReg*)0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR     (*(RwReg*)0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR     (*(RwReg*)0x40038048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR     (*(RwReg*)0x4003804CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR     (*(RoReg*)0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR     (*(RwReg*)0x40038094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR    (*(RwReg*)0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR    (*(RoReg*)0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR     (*(RwReg*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR     (*(RwReg*)0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR    (*(RwReg*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR    (*(RwReg*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR    (*(WoReg*)0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR    (*(RoReg*)0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_ADC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_chipid.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_chipid.h
new file mode 100644
index 0000000..6e158d0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_chipid.h
@@ -0,0 +1,42 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_CHIPID_INSTANCE_
+#define _SAM3S8_CHIPID_INSTANCE_
+
+/* ========== Register definition for CHIPID peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CHIPID_CIDR          (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID          (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#else
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_CHIPID_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_crccu.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_crccu.h
new file mode 100644
index 0000000..ff435a8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_crccu.h
@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_CRCCU_INSTANCE_
+#define _SAM3S8_CRCCU_INSTANCE_
+
+/* ========== Register definition for CRCCU peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CRCCU_DSCR             (0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
+#define REG_CRCCU_DMA_EN           (0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
+#define REG_CRCCU_DMA_DIS          (0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
+#define REG_CRCCU_DMA_SR           (0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
+#define REG_CRCCU_DMA_IER          (0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
+#define REG_CRCCU_DMA_IDR          (0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
+#define REG_CRCCU_DMA_IMR          (0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
+#define REG_CRCCU_DMA_ISR          (0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
+#define REG_CRCCU_CR               (0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
+#define REG_CRCCU_MR               (0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
+#define REG_CRCCU_SR               (0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
+#define REG_CRCCU_IER              (0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
+#define REG_CRCCU_IDR              (0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
+#define REG_CRCCU_IMR              (0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
+#define REG_CRCCU_ISR              (0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
+#else
+#define REG_CRCCU_DSCR    (*(RwReg*)0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
+#define REG_CRCCU_DMA_EN  (*(WoReg*)0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
+#define REG_CRCCU_DMA_DIS (*(WoReg*)0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
+#define REG_CRCCU_DMA_SR  (*(RoReg*)0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
+#define REG_CRCCU_DMA_IER (*(WoReg*)0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
+#define REG_CRCCU_DMA_IDR (*(WoReg*)0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
+#define REG_CRCCU_DMA_IMR (*(RoReg*)0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
+#define REG_CRCCU_DMA_ISR (*(RoReg*)0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
+#define REG_CRCCU_CR      (*(WoReg*)0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
+#define REG_CRCCU_MR      (*(RwReg*)0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
+#define REG_CRCCU_SR      (*(RoReg*)0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
+#define REG_CRCCU_IER     (*(WoReg*)0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
+#define REG_CRCCU_IDR     (*(WoReg*)0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
+#define REG_CRCCU_IMR     (*(RoReg*)0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
+#define REG_CRCCU_ISR     (*(RoReg*)0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_CRCCU_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_dacc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_dacc.h
new file mode 100644
index 0000000..29d411d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_dacc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_DACC_INSTANCE_
+#define _SAM3S8_DACC_INSTANCE_
+
+/* ========== Register definition for DACC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DACC_CR            (0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR            (0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER          (0x4003C010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR          (0x4003C014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR          (0x4003C018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR           (0x4003C020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER           (0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR           (0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR           (0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR           (0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR           (0x4003C094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR          (0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR          (0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_TPR           (0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR           (0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_TNPR          (0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR          (0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR          (0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR          (0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#else
+#define REG_DACC_CR   (*(WoReg*)0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR   (*(RwReg*)0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER (*(WoReg*)0x4003C010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR (*(WoReg*)0x4003C014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR (*(RoReg*)0x4003C018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR  (*(WoReg*)0x4003C020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER  (*(WoReg*)0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR  (*(WoReg*)0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR  (*(RoReg*)0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR  (*(RoReg*)0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR  (*(RwReg*)0x4003C094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR (*(RwReg*)0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR (*(RoReg*)0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_TPR  (*(RwReg*)0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR  (*(RwReg*)0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_TNPR (*(RwReg*)0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR (*(RwReg*)0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR (*(WoReg*)0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR (*(RoReg*)0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_DACC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_efc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_efc.h
new file mode 100644
index 0000000..8d1bc3d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_efc.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_EFC_INSTANCE_
+#define _SAM3S8_EFC_INSTANCE_
+
+/* ========== Register definition for EFC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EFC_FMR           (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR           (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR           (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR           (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#else
+#define REG_EFC_FMR  (*(RwReg*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR  (*(WoReg*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR  (*(RoReg*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR  (*(RoReg*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_EFC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_gpbr.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_gpbr.h
new file mode 100644
index 0000000..b8d8b6b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_gpbr.h
@@ -0,0 +1,40 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_GPBR_INSTANCE_
+#define _SAM3S8_GPBR_INSTANCE_
+
+/* ========== Register definition for GPBR peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GPBR_GPBR            (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#else
+#define REG_GPBR_GPBR   (*(RwReg*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_GPBR_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_hsmci.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_hsmci.h
new file mode 100644
index 0000000..54b7fe9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_hsmci.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_HSMCI_INSTANCE_
+#define _SAM3S8_HSMCI_INSTANCE_
+
+/* ========== Register definition for HSMCI peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_HSMCI_CR                 (0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR                 (0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR               (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR               (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR               (0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR               (0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR               (0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR              (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR               (0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR                (0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR                (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR                 (0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER                (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR                (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR                (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_CFG                (0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR               (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR               (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_RPR                (0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
+#define REG_HSMCI_RCR                (0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
+#define REG_HSMCI_TPR                (0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
+#define REG_HSMCI_TCR                (0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
+#define REG_HSMCI_RNPR               (0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
+#define REG_HSMCI_RNCR               (0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
+#define REG_HSMCI_TNPR               (0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
+#define REG_HSMCI_TNCR               (0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
+#define REG_HSMCI_PTCR               (0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
+#define REG_HSMCI_PTSR               (0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
+#define REG_HSMCI_FIFO               (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#else
+#define REG_HSMCI_CR        (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR        (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR      (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR      (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR      (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR      (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR      (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR     (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR      (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR       (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR       (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR        (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER       (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR       (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR       (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_CFG       (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR      (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR      (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_RPR       (*(RwReg*)0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
+#define REG_HSMCI_RCR       (*(RwReg*)0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
+#define REG_HSMCI_TPR       (*(RwReg*)0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
+#define REG_HSMCI_TCR       (*(RwReg*)0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
+#define REG_HSMCI_RNPR      (*(RwReg*)0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
+#define REG_HSMCI_RNCR      (*(RwReg*)0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
+#define REG_HSMCI_TNPR      (*(RwReg*)0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
+#define REG_HSMCI_TNCR      (*(RwReg*)0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
+#define REG_HSMCI_PTCR      (*(WoReg*)0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
+#define REG_HSMCI_PTSR      (*(RoReg*)0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
+#define REG_HSMCI_FIFO      (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_HSMCI_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_matrix.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_matrix.h
new file mode 100644
index 0000000..f6a874d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_matrix.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_MATRIX_INSTANCE_
+#define _SAM3S8_MATRIX_INSTANCE_
+
+/* ========== Register definition for MATRIX peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MATRIX_MCFG             (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG             (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0            (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1            (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2            (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3            (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4            (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_CCFG_SYSIO              (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_CCFG_SMCNFCS            (0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */
+#define REG_MATRIX_WPMR             (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR             (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#else
+#define REG_MATRIX_MCFG    (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG    (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0   (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1   (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2   (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3   (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4   (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_CCFG_SYSIO     (*(RwReg*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_CCFG_SMCNFCS   (*(RwReg*)0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */
+#define REG_MATRIX_WPMR    (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR    (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_MATRIX_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_pioa.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_pioa.h
new file mode 100644
index 0000000..a3cb091
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_pioa.h
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PIOA_INSTANCE_
+#define _SAM3S8_PIOA_INSTANCE_
+
+/* ========== Register definition for PIOA peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOA_PER                (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR                (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR                (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER                (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR                (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR                (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER               (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR               (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR               (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR               (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR               (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR               (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR               (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER                (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR                (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR                (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR                (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER               (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR               (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR               (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR               (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER               (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR               (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR             (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR             (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER             (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR             (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR               (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR              (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER              (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR              (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER               (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR               (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR               (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER              (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR              (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR              (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR                (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR                (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR               (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR             (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR             (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR             (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR             (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR               (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR               (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT            (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#define REG_PIOA_PCMR               (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
+#define REG_PIOA_PCIER              (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
+#define REG_PIOA_PCIDR              (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
+#define REG_PIOA_PCIMR              (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
+#define REG_PIOA_PCISR              (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
+#define REG_PIOA_PCRHR              (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
+#define REG_PIOA_RPR                (0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */
+#define REG_PIOA_RCR                (0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */
+#define REG_PIOA_RNPR               (0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */
+#define REG_PIOA_RNCR               (0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */
+#define REG_PIOA_PTCR               (0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */
+#define REG_PIOA_PTSR               (0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */
+#else
+#define REG_PIOA_PER       (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR       (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR       (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER       (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR       (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR       (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER      (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR      (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR      (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR      (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR      (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR      (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR      (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER       (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR       (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR       (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR       (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER      (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR      (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR      (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR      (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER      (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR      (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR    (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR    (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER    (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR    (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR      (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR     (*(WoReg*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER     (*(WoReg*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR     (*(RoReg*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER      (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR      (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR      (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER     (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR     (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR     (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR       (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR       (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR      (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR    (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR    (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR    (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR    (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR      (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR      (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT   (*(RwReg*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#define REG_PIOA_PCMR      (*(RwReg*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
+#define REG_PIOA_PCIER     (*(WoReg*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
+#define REG_PIOA_PCIDR     (*(WoReg*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
+#define REG_PIOA_PCIMR     (*(RoReg*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
+#define REG_PIOA_PCISR     (*(RoReg*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
+#define REG_PIOA_PCRHR     (*(RoReg*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
+#define REG_PIOA_RPR       (*(RwReg*)0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */
+#define REG_PIOA_RCR       (*(RwReg*)0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */
+#define REG_PIOA_RNPR      (*(RwReg*)0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */
+#define REG_PIOA_RNCR      (*(RwReg*)0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */
+#define REG_PIOA_PTCR      (*(WoReg*)0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */
+#define REG_PIOA_PTSR      (*(RoReg*)0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_PIOA_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_piob.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_piob.h
new file mode 100644
index 0000000..f3d4955
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_piob.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PIOB_INSTANCE_
+#define _SAM3S8_PIOB_INSTANCE_
+
+/* ========== Register definition for PIOB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOB_PER                (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR                (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR                (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER                (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR                (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR                (0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER               (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR               (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR               (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR               (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR               (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR               (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR               (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER                (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR                (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR                (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR                (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER               (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR               (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR               (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR               (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER               (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR               (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR             (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR             (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER             (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR             (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR               (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR              (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER              (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR              (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER               (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR               (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR               (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER              (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR              (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR              (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR                (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR                (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR               (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR             (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR             (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR             (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR             (0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR               (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR               (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT            (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#define REG_PIOB_PCMR               (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
+#define REG_PIOB_PCIER              (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
+#define REG_PIOB_PCIDR              (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
+#define REG_PIOB_PCIMR              (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
+#define REG_PIOB_PCISR              (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
+#define REG_PIOB_PCRHR              (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
+#else
+#define REG_PIOB_PER       (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR       (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR       (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER       (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR       (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR       (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER      (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR      (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR      (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR      (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR      (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR      (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR      (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER       (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR       (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR       (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR       (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER      (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR      (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR      (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR      (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER      (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR      (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR    (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR    (*(WoReg*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER    (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR    (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR      (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR     (*(WoReg*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER     (*(WoReg*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR     (*(RoReg*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER      (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR      (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR      (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER     (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR     (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR     (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR       (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR       (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR      (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR    (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR    (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR    (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR    (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR      (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR      (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT   (*(RwReg*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#define REG_PIOB_PCMR      (*(RwReg*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
+#define REG_PIOB_PCIER     (*(WoReg*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
+#define REG_PIOB_PCIDR     (*(WoReg*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
+#define REG_PIOB_PCIMR     (*(RoReg*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
+#define REG_PIOB_PCISR     (*(RoReg*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
+#define REG_PIOB_PCRHR     (*(RoReg*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_PIOB_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_pioc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_pioc.h
new file mode 100644
index 0000000..2a22462
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_pioc.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PIOC_INSTANCE_
+#define _SAM3S8_PIOC_INSTANCE_
+
+/* ========== Register definition for PIOC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOC_PER                (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR                (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR                (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER                (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR                (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR                (0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER               (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR               (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR               (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR               (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR               (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR               (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR               (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER                (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR                (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR                (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR                (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER               (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR               (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR               (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR               (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER               (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR               (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR             (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR             (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER             (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR             (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR               (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR              (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER              (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR              (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER               (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR               (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR               (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER              (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR              (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR              (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR                (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR                (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR               (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR             (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR             (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR             (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR             (0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR               (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR               (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT            (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#define REG_PIOC_PCMR               (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
+#define REG_PIOC_PCIER              (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
+#define REG_PIOC_PCIDR              (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
+#define REG_PIOC_PCIMR              (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
+#define REG_PIOC_PCISR              (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
+#define REG_PIOC_PCRHR              (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
+#else
+#define REG_PIOC_PER       (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR       (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR       (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER       (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR       (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR       (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER      (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR      (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR      (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR      (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR      (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR      (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR      (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER       (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR       (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR       (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR       (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER      (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR      (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR      (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR      (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER      (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR      (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR    (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR    (*(WoReg*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER    (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR    (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR      (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR     (*(WoReg*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER     (*(WoReg*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR     (*(RoReg*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER      (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR      (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR      (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER     (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR     (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR     (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR       (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR       (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR      (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR    (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR    (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR    (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR    (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR      (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR      (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT   (*(RwReg*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#define REG_PIOC_PCMR      (*(RwReg*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
+#define REG_PIOC_PCIER     (*(WoReg*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
+#define REG_PIOC_PCIDR     (*(WoReg*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
+#define REG_PIOC_PCIMR     (*(RoReg*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
+#define REG_PIOC_PCISR     (*(RoReg*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
+#define REG_PIOC_PCRHR     (*(RoReg*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_PIOC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_pmc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_pmc.h
new file mode 100644
index 0000000..3143047
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_pmc.h
@@ -0,0 +1,90 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PMC_INSTANCE_
+#define _SAM3S8_PMC_INSTANCE_
+
+/* ========== Register definition for PMC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PMC_SCER            (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR            (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR            (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0           (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0           (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0           (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR            (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR           (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR          (0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_CKGR_PLLBR          (0x400E042CU) /**< \brief (PMC) PLLB Register */
+#define REG_PMC_MCKR            (0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB             (0x400E0438U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK             (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER             (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR             (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR              (0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR             (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR            (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR            (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR            (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR            (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR            (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1           (0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1           (0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1           (0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_OCR             (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
+#else
+#define REG_PMC_SCER   (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR   (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR   (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0  (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0  (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0  (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR   (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR  (*(RwReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_CKGR_PLLBR (*(RwReg*)0x400E042CU) /**< \brief (PMC) PLLB Register */
+#define REG_PMC_MCKR   (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB    (*(RwReg*)0x400E0438U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK    (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER    (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR    (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR     (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR    (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR   (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR   (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR   (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR   (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR   (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1  (*(WoReg*)0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1  (*(WoReg*)0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1  (*(RoReg*)0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_OCR    (*(RwReg*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_PMC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_pwm.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_pwm.h
new file mode 100644
index 0000000..c393d78
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_pwm.h
@@ -0,0 +1,240 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_PWM_INSTANCE_
+#define _SAM3S8_PWM_INSTANCE_
+
+/* ========== Register definition for PWM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PWM_CLK               (0x40020000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA               (0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS               (0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR                (0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1              (0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1              (0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1              (0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1              (0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM               (0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC              (0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP              (0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD           (0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2              (0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2              (0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2              (0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2              (0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV               (0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS                (0x40020048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS               (0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC               (0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD            (0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD            (0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR               (0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR               (0x40020060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR               (0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV               (0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE               (0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR              (0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR              (0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR              (0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR              (0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_TPR               (0x40020108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR               (0x4002010CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_TNPR              (0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR              (0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR              (0x40020120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR              (0x40020124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0             (0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0          (0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0             (0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0          (0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1             (0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1          (0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1             (0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1          (0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2             (0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2          (0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2             (0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2          (0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3             (0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3          (0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3             (0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3          (0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4             (0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4          (0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4             (0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4          (0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5             (0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5          (0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5             (0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5          (0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6             (0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6          (0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6             (0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6          (0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7             (0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7          (0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7             (0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7          (0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0              (0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0             (0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0          (0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0             (0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0          (0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0             (0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0               (0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0            (0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1              (0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1             (0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1          (0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1             (0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1          (0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1             (0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1               (0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1            (0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2              (0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2             (0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2          (0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2             (0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2          (0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2             (0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2               (0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2            (0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3              (0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3             (0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3          (0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3             (0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3          (0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3             (0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3               (0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3            (0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#else
+#define REG_PWM_CLK      (*(RwReg*)0x40020000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA      (*(WoReg*)0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS      (*(WoReg*)0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR       (*(RoReg*)0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1     (*(WoReg*)0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1     (*(WoReg*)0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1     (*(RoReg*)0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1     (*(RoReg*)0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM      (*(RwReg*)0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC     (*(RwReg*)0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP     (*(RwReg*)0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD  (*(WoReg*)0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2     (*(WoReg*)0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2     (*(WoReg*)0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2     (*(RoReg*)0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2     (*(RoReg*)0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV      (*(RwReg*)0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS       (*(RwReg*)0x40020048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS      (*(WoReg*)0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC      (*(WoReg*)0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD   (*(WoReg*)0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD   (*(WoReg*)0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR      (*(RwReg*)0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR      (*(RoReg*)0x40020060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR      (*(WoReg*)0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV      (*(RwReg*)0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE      (*(RwReg*)0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR     (*(RwReg*)0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR     (*(RwReg*)0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR     (*(WoReg*)0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR     (*(RoReg*)0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_TPR      (*(RwReg*)0x40020108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR      (*(RwReg*)0x4002010CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_TNPR     (*(RwReg*)0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR     (*(RwReg*)0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR     (*(WoReg*)0x40020120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR     (*(RoReg*)0x40020124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0    (*(RwReg*)0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0    (*(RwReg*)0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1    (*(RwReg*)0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1    (*(RwReg*)0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2    (*(RwReg*)0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2    (*(RwReg*)0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3    (*(RwReg*)0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3    (*(RwReg*)0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4    (*(RwReg*)0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4    (*(RwReg*)0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5    (*(RwReg*)0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5    (*(RwReg*)0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6    (*(RwReg*)0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6    (*(RwReg*)0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7    (*(RwReg*)0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7    (*(RwReg*)0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0     (*(RwReg*)0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0    (*(RwReg*)0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0    (*(RwReg*)0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0    (*(RoReg*)0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0      (*(RwReg*)0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0   (*(WoReg*)0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1     (*(RwReg*)0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1    (*(RwReg*)0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1    (*(RwReg*)0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1    (*(RoReg*)0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1      (*(RwReg*)0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1   (*(WoReg*)0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2     (*(RwReg*)0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2    (*(RwReg*)0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2    (*(RwReg*)0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2    (*(RoReg*)0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2      (*(RwReg*)0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2   (*(WoReg*)0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3     (*(RwReg*)0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3    (*(RwReg*)0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3    (*(RwReg*)0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3    (*(RoReg*)0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3      (*(RwReg*)0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3   (*(WoReg*)0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_PWM_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_rstc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_rstc.h
new file mode 100644
index 0000000..104f8d3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_rstc.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_RSTC_INSTANCE_
+#define _SAM3S8_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RSTC_CR          (0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR          (0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR          (0x400E1408U) /**< \brief (RSTC) Mode Register */
+#else
+#define REG_RSTC_CR (*(WoReg*)0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR (*(RoReg*)0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR (*(RwReg*)0x400E1408U) /**< \brief (RSTC) Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_RSTC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_rtc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_rtc.h
new file mode 100644
index 0000000..0cf603d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_rtc.h
@@ -0,0 +1,62 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_RTC_INSTANCE_
+#define _SAM3S8_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_CR              (0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR              (0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR            (0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR            (0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR          (0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR          (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR              (0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR            (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER             (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR             (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR             (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER             (0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#else
+#define REG_RTC_CR     (*(RwReg*)0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR     (*(RwReg*)0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR   (*(RwReg*)0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR   (*(RwReg*)0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR (*(RwReg*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR     (*(RoReg*)0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR   (*(WoReg*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER    (*(WoReg*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR    (*(WoReg*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR    (*(RoReg*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER    (*(RoReg*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_RTC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_rtt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_rtt.h
new file mode 100644
index 0000000..c352213
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_rtt.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_RTT_INSTANCE_
+#define _SAM3S8_RTT_INSTANCE_
+
+/* ========== Register definition for RTT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTT_MR          (0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR          (0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR          (0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR          (0x400E143CU) /**< \brief (RTT) Status Register */
+#else
+#define REG_RTT_MR (*(RwReg*)0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR (*(RwReg*)0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR (*(RoReg*)0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR (*(RoReg*)0x400E143CU) /**< \brief (RTT) Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_RTT_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_smc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_smc.h
new file mode 100644
index 0000000..dcc4974
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_smc.h
@@ -0,0 +1,88 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SMC_INSTANCE_
+#define _SAM3S8_SMC_INSTANCE_
+
+/* ========== Register definition for SMC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SMC_SETUP0          (0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0          (0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0          (0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_MODE0           (0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1          (0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1          (0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1          (0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_MODE1           (0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2          (0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2          (0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2          (0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_MODE2           (0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3          (0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3          (0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3          (0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_MODE3           (0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4          (0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4          (0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4          (0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_MODE4           (0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_OCMS            (0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */
+#define REG_SMC_KEY1            (0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2            (0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPMR            (0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
+#define REG_SMC_WPSR            (0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */
+#else
+#define REG_SMC_SETUP0 (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0 (*(RwReg*)0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0 (*(RwReg*)0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_MODE0  (*(RwReg*)0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1 (*(RwReg*)0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1 (*(RwReg*)0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1 (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_MODE1  (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2 (*(RwReg*)0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2 (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2 (*(RwReg*)0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_MODE2  (*(RwReg*)0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3 (*(RwReg*)0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3 (*(RwReg*)0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3 (*(RwReg*)0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_MODE3  (*(RwReg*)0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4 (*(RwReg*)0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4 (*(RwReg*)0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4 (*(RwReg*)0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_MODE4  (*(RwReg*)0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_OCMS   (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */
+#define REG_SMC_KEY1   (*(WoReg*)0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2   (*(WoReg*)0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPMR   (*(RwReg*)0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
+#define REG_SMC_WPSR   (*(RoReg*)0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_SMC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_spi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_spi.h
new file mode 100644
index 0000000..35675b8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_spi.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SPI_INSTANCE_
+#define _SAM3S8_SPI_INSTANCE_
+
+/* ========== Register definition for SPI peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SPI_CR              (0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR              (0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR             (0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR             (0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR              (0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER             (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR             (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR             (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR             (0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR            (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR            (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR             (0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR             (0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR             (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR             (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR            (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR            (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR            (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR            (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR            (0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR            (0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#else
+#define REG_SPI_CR     (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR     (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR    (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR    (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR     (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER    (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR    (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR    (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR    (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR   (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR   (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR    (*(RwReg*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR    (*(RwReg*)0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR    (*(RwReg*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR    (*(RwReg*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR   (*(RwReg*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR   (*(RwReg*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR   (*(RwReg*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR   (*(RwReg*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR   (*(WoReg*)0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR   (*(RoReg*)0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_SPI_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_ssc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_ssc.h
new file mode 100644
index 0000000..dbe9008
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_ssc.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SSC_INSTANCE_
+#define _SAM3S8_SSC_INSTANCE_
+
+/* ========== Register definition for SSC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SSC_CR            (0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR           (0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR          (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR          (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR          (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR          (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR           (0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR           (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR          (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR          (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R          (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R          (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR            (0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER           (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR           (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR           (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR          (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR          (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#define REG_SSC_RPR           (0x40004100U) /**< \brief (SSC) Receive Pointer Register */
+#define REG_SSC_RCR           (0x40004104U) /**< \brief (SSC) Receive Counter Register */
+#define REG_SSC_TPR           (0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
+#define REG_SSC_TCR           (0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
+#define REG_SSC_RNPR          (0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
+#define REG_SSC_RNCR          (0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
+#define REG_SSC_TNPR          (0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
+#define REG_SSC_TNCR          (0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
+#define REG_SSC_PTCR          (0x40004120U) /**< \brief (SSC) Transfer Control Register */
+#define REG_SSC_PTSR          (0x40004124U) /**< \brief (SSC) Transfer Status Register */
+#else
+#define REG_SSC_CR   (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR  (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR  (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR  (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR   (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER  (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR  (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR  (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#define REG_SSC_RPR  (*(RwReg*)0x40004100U) /**< \brief (SSC) Receive Pointer Register */
+#define REG_SSC_RCR  (*(RwReg*)0x40004104U) /**< \brief (SSC) Receive Counter Register */
+#define REG_SSC_TPR  (*(RwReg*)0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
+#define REG_SSC_TCR  (*(RwReg*)0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
+#define REG_SSC_RNPR (*(RwReg*)0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
+#define REG_SSC_RNCR (*(RwReg*)0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
+#define REG_SSC_TNPR (*(RwReg*)0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
+#define REG_SSC_TNCR (*(RwReg*)0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
+#define REG_SSC_PTCR (*(WoReg*)0x40004120U) /**< \brief (SSC) Transfer Control Register */
+#define REG_SSC_PTSR (*(RoReg*)0x40004124U) /**< \brief (SSC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_SSC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_supc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_supc.h
new file mode 100644
index 0000000..d84507d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_supc.h
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_SUPC_INSTANCE_
+#define _SAM3S8_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SUPC_CR            (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR          (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR            (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR          (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR          (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR            (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#else
+#define REG_SUPC_CR   (*(WoReg*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR   (*(RwReg*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR (*(RwReg*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR   (*(RoReg*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_SUPC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_tc0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_tc0.h
new file mode 100644
index 0000000..672e5c7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_tc0.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_TC0_INSTANCE_
+#define _SAM3S8_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC0_CCR0           (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0           (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0          (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0            (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0            (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0            (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0            (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0            (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0           (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0           (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0           (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1           (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1           (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1          (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1            (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1            (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1            (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1            (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1            (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1           (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1           (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1           (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2           (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2           (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2          (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2            (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2            (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2            (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2            (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2            (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2           (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2           (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2           (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR            (0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR            (0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER           (0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR           (0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR           (0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR           (0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR            (0x400100D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR           (0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#else
+#define REG_TC0_CCR0  (*(WoReg*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0  (*(RwReg*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0 (*(RwReg*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0   (*(RoReg*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0   (*(RwReg*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0   (*(RwReg*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0   (*(RwReg*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0   (*(RoReg*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0  (*(WoReg*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0  (*(WoReg*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0  (*(RoReg*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1  (*(WoReg*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1  (*(RwReg*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1 (*(RwReg*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1   (*(RoReg*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1   (*(RwReg*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1   (*(RwReg*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1   (*(RwReg*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1   (*(RoReg*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1  (*(WoReg*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1  (*(WoReg*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1  (*(RoReg*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2  (*(WoReg*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2  (*(RwReg*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2 (*(RwReg*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2   (*(RoReg*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2   (*(RwReg*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2   (*(RwReg*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2   (*(RwReg*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2   (*(RoReg*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2  (*(WoReg*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2  (*(WoReg*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2  (*(RoReg*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR   (*(WoReg*)0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR   (*(RwReg*)0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER  (*(WoReg*)0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR  (*(WoReg*)0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR  (*(RoReg*)0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR  (*(RoReg*)0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR   (*(RwReg*)0x400100D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR  (*(RwReg*)0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_TC0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_tc1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_tc1.h
new file mode 100644
index 0000000..7e78865
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_tc1.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_TC1_INSTANCE_
+#define _SAM3S8_TC1_INSTANCE_
+
+/* ========== Register definition for TC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC1_CCR0           (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0           (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0          (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0            (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0            (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0            (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0            (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0            (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0           (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0           (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0           (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1           (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1           (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1          (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1            (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1            (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1            (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1            (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1            (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1           (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1           (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1           (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2           (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2           (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2          (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2            (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2            (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2            (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2            (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2            (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2           (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2           (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2           (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR            (0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR            (0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER           (0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR           (0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR           (0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR           (0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR            (0x400140D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR           (0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#else
+#define REG_TC1_CCR0  (*(WoReg*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0  (*(RwReg*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0 (*(RwReg*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0   (*(RoReg*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0   (*(RwReg*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0   (*(RwReg*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0   (*(RwReg*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0   (*(RoReg*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0  (*(WoReg*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0  (*(WoReg*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0  (*(RoReg*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1  (*(WoReg*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1  (*(RwReg*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1 (*(RwReg*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1   (*(RoReg*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1   (*(RwReg*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1   (*(RwReg*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1   (*(RwReg*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1   (*(RoReg*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1  (*(WoReg*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1  (*(WoReg*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1  (*(RoReg*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2  (*(WoReg*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2  (*(RwReg*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2 (*(RwReg*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2   (*(RoReg*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2   (*(RwReg*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2   (*(RwReg*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2   (*(RwReg*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2   (*(RoReg*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2  (*(WoReg*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2  (*(WoReg*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2  (*(RoReg*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR   (*(WoReg*)0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR   (*(RwReg*)0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER  (*(WoReg*)0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR  (*(WoReg*)0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR  (*(RoReg*)0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR  (*(RoReg*)0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR   (*(RwReg*)0x400140D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR  (*(RwReg*)0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_TC1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_twi0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_twi0.h
new file mode 100644
index 0000000..d7647d0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_twi0.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_TWI0_INSTANCE_
+#define _SAM3S8_TWI0_INSTANCE_
+
+/* ========== Register definition for TWI0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TWI0_CR            (0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR           (0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR           (0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR          (0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR          (0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR            (0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER           (0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR           (0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR           (0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR           (0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR           (0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR           (0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR           (0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR           (0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR           (0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR          (0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR          (0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR          (0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR          (0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR          (0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR          (0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#else
+#define REG_TWI0_CR   (*(WoReg*)0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR  (*(RwReg*)0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR  (*(RwReg*)0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR (*(RwReg*)0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR (*(RwReg*)0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR   (*(RoReg*)0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER  (*(WoReg*)0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR  (*(WoReg*)0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR  (*(RoReg*)0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR  (*(RoReg*)0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR  (*(WoReg*)0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR  (*(RwReg*)0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR  (*(RwReg*)0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR  (*(RwReg*)0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR  (*(RwReg*)0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR (*(RwReg*)0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR (*(RwReg*)0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR (*(RwReg*)0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR (*(RwReg*)0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR (*(WoReg*)0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR (*(RoReg*)0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_TWI0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_twi1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_twi1.h
new file mode 100644
index 0000000..49e021b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_twi1.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_TWI1_INSTANCE_
+#define _SAM3S8_TWI1_INSTANCE_
+
+/* ========== Register definition for TWI1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TWI1_CR            (0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR           (0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR           (0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR          (0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR          (0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR            (0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER           (0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR           (0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR           (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR           (0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR           (0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR           (0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR           (0x4001C104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR           (0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR           (0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR          (0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR          (0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR          (0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR          (0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR          (0x4001C120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR          (0x4001C124U) /**< \brief (TWI1) Transfer Status Register */
+#else
+#define REG_TWI1_CR   (*(WoReg*)0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR  (*(RwReg*)0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR  (*(RwReg*)0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR (*(RwReg*)0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR (*(RwReg*)0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR   (*(RoReg*)0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER  (*(WoReg*)0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR  (*(WoReg*)0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR  (*(RoReg*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR  (*(RoReg*)0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR  (*(WoReg*)0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR  (*(RwReg*)0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR  (*(RwReg*)0x4001C104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR  (*(RwReg*)0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR  (*(RwReg*)0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR (*(RwReg*)0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR (*(RwReg*)0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR (*(RwReg*)0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR (*(RwReg*)0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR (*(WoReg*)0x4001C120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR (*(RoReg*)0x4001C124U) /**< \brief (TWI1) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_TWI1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_uart0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_uart0.h
new file mode 100644
index 0000000..d1751d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_uart0.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_UART0_INSTANCE_
+#define _SAM3S8_UART0_INSTANCE_
+
+/* ========== Register definition for UART0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UART0_CR            (0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR            (0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER           (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR           (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR           (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR            (0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR           (0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR           (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR          (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR           (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR           (0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR           (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR           (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR          (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR          (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR          (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR          (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR          (0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR          (0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#else
+#define REG_UART0_CR   (*(WoReg*)0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR   (*(RwReg*)0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER  (*(WoReg*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR  (*(WoReg*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR  (*(RoReg*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR   (*(RoReg*)0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR  (*(RoReg*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR  (*(WoReg*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR  (*(RwReg*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR  (*(RwReg*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR  (*(RwReg*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR  (*(RwReg*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_UART0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_uart1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_uart1.h
new file mode 100644
index 0000000..dd9478e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_uart1.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_UART1_INSTANCE_
+#define _SAM3S8_UART1_INSTANCE_
+
+/* ========== Register definition for UART1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UART1_CR            (0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR            (0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER           (0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR           (0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR           (0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR            (0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR           (0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR           (0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR          (0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#define REG_UART1_RPR           (0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
+#define REG_UART1_RCR           (0x400E0904U) /**< \brief (UART1) Receive Counter Register */
+#define REG_UART1_TPR           (0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
+#define REG_UART1_TCR           (0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
+#define REG_UART1_RNPR          (0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
+#define REG_UART1_RNCR          (0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
+#define REG_UART1_TNPR          (0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
+#define REG_UART1_TNCR          (0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
+#define REG_UART1_PTCR          (0x400E0920U) /**< \brief (UART1) Transfer Control Register */
+#define REG_UART1_PTSR          (0x400E0924U) /**< \brief (UART1) Transfer Status Register */
+#else
+#define REG_UART1_CR   (*(WoReg*)0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR   (*(RwReg*)0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER  (*(WoReg*)0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR  (*(WoReg*)0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR  (*(RoReg*)0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR   (*(RoReg*)0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR  (*(RoReg*)0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR  (*(WoReg*)0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#define REG_UART1_RPR  (*(RwReg*)0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
+#define REG_UART1_RCR  (*(RwReg*)0x400E0904U) /**< \brief (UART1) Receive Counter Register */
+#define REG_UART1_TPR  (*(RwReg*)0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
+#define REG_UART1_TCR  (*(RwReg*)0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
+#define REG_UART1_RNPR (*(RwReg*)0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
+#define REG_UART1_RNCR (*(RwReg*)0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
+#define REG_UART1_TNPR (*(RwReg*)0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
+#define REG_UART1_TNCR (*(RwReg*)0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
+#define REG_UART1_PTCR (*(WoReg*)0x400E0920U) /**< \brief (UART1) Transfer Control Register */
+#define REG_UART1_PTSR (*(RoReg*)0x400E0924U) /**< \brief (UART1) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_UART1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_udp.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_udp.h
new file mode 100644
index 0000000..4972c47
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_udp.h
@@ -0,0 +1,62 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_UDP_INSTANCE_
+#define _SAM3S8_UDP_INSTANCE_
+
+/* ========== Register definition for UDP peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UDP_FRM_NUM           (0x40034000U) /**< \brief (UDP) Frame Number Register */
+#define REG_UDP_GLB_STAT          (0x40034004U) /**< \brief (UDP) Global State Register */
+#define REG_UDP_FADDR             (0x40034008U) /**< \brief (UDP) Function Address Register */
+#define REG_UDP_IER               (0x40034010U) /**< \brief (UDP) Interrupt Enable Register */
+#define REG_UDP_IDR               (0x40034014U) /**< \brief (UDP) Interrupt Disable Register */
+#define REG_UDP_IMR               (0x40034018U) /**< \brief (UDP) Interrupt Mask Register */
+#define REG_UDP_ISR               (0x4003401CU) /**< \brief (UDP) Interrupt Status Register */
+#define REG_UDP_ICR               (0x40034020U) /**< \brief (UDP) Interrupt Clear Register */
+#define REG_UDP_RST_EP            (0x40034028U) /**< \brief (UDP) Reset Endpoint Register */
+#define REG_UDP_CSR               (0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */
+#define REG_UDP_FDR               (0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */
+#define REG_UDP_TXVC              (0x40034074U) /**< \brief (UDP) Transceiver Control Register */
+#else
+#define REG_UDP_FRM_NUM  (*(RoReg*)0x40034000U) /**< \brief (UDP) Frame Number Register */
+#define REG_UDP_GLB_STAT (*(RwReg*)0x40034004U) /**< \brief (UDP) Global State Register */
+#define REG_UDP_FADDR    (*(RwReg*)0x40034008U) /**< \brief (UDP) Function Address Register */
+#define REG_UDP_IER      (*(WoReg*)0x40034010U) /**< \brief (UDP) Interrupt Enable Register */
+#define REG_UDP_IDR      (*(WoReg*)0x40034014U) /**< \brief (UDP) Interrupt Disable Register */
+#define REG_UDP_IMR      (*(RoReg*)0x40034018U) /**< \brief (UDP) Interrupt Mask Register */
+#define REG_UDP_ISR      (*(RoReg*)0x4003401CU) /**< \brief (UDP) Interrupt Status Register */
+#define REG_UDP_ICR      (*(WoReg*)0x40034020U) /**< \brief (UDP) Interrupt Clear Register */
+#define REG_UDP_RST_EP   (*(RwReg*)0x40034028U) /**< \brief (UDP) Reset Endpoint Register */
+#define REG_UDP_CSR      (*(RwReg*)0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */
+#define REG_UDP_FDR      (*(RwReg*)0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */
+#define REG_UDP_TXVC     (*(RwReg*)0x40034074U) /**< \brief (UDP) Transceiver Control Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_UDP_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_usart0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_usart0.h
new file mode 100644
index 0000000..8d0f8ae
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_usart0.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_USART0_INSTANCE_
+#define _SAM3S8_USART0_INSTANCE_
+
+/* ========== Register definition for USART0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART0_CR            (0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR            (0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER           (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR           (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR           (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR           (0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR           (0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR           (0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR          (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR          (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR          (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI          (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER           (0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF            (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN           (0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR          (0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR          (0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_VERSION          (0x400240FCU) /**< \brief (USART0) Version Register */
+#define REG_USART0_RPR           (0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR           (0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR           (0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR           (0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR          (0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR          (0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR          (0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR          (0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR          (0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR          (0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#else
+#define REG_USART0_CR   (*(WoReg*)0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR   (*(RwReg*)0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER  (*(WoReg*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR  (*(WoReg*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR  (*(RoReg*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR  (*(RoReg*)0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR  (*(RoReg*)0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR  (*(WoReg*)0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR (*(RwReg*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR (*(RwReg*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR (*(RwReg*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI (*(RwReg*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER  (*(RoReg*)0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF   (*(RwReg*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN  (*(RwReg*)0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR (*(RwReg*)0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR (*(RoReg*)0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_VERSION (*(RoReg*)0x400240FCU) /**< \brief (USART0) Version Register */
+#define REG_USART0_RPR  (*(RwReg*)0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR  (*(RwReg*)0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR  (*(RwReg*)0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR  (*(RwReg*)0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR (*(RwReg*)0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR (*(RwReg*)0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR (*(RwReg*)0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR (*(RwReg*)0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR (*(WoReg*)0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR (*(RoReg*)0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_USART0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_usart1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_usart1.h
new file mode 100644
index 0000000..6164228
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_usart1.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_USART1_INSTANCE_
+#define _SAM3S8_USART1_INSTANCE_
+
+/* ========== Register definition for USART1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART1_CR            (0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR            (0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER           (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR           (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR           (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR           (0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR           (0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR           (0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR          (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR          (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR          (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI          (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER           (0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF            (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN           (0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR          (0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR          (0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_VERSION          (0x400280FCU) /**< \brief (USART1) Version Register */
+#define REG_USART1_RPR           (0x40028100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR           (0x40028104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR           (0x40028108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR           (0x4002810CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR          (0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR          (0x40028114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR          (0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR          (0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR          (0x40028120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR          (0x40028124U) /**< \brief (USART1) Transfer Status Register */
+#else
+#define REG_USART1_CR   (*(WoReg*)0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR   (*(RwReg*)0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER  (*(WoReg*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR  (*(WoReg*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR  (*(RoReg*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR  (*(RoReg*)0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR  (*(RoReg*)0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR  (*(WoReg*)0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR (*(RwReg*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR (*(RwReg*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR (*(RwReg*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI (*(RwReg*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER  (*(RoReg*)0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF   (*(RwReg*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN  (*(RwReg*)0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR (*(RwReg*)0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR (*(RoReg*)0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_VERSION (*(RoReg*)0x400280FCU) /**< \brief (USART1) Version Register */
+#define REG_USART1_RPR  (*(RwReg*)0x40028100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR  (*(RwReg*)0x40028104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR  (*(RwReg*)0x40028108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR  (*(RwReg*)0x4002810CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR (*(RwReg*)0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR (*(RwReg*)0x40028114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR (*(RwReg*)0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR (*(RwReg*)0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR (*(WoReg*)0x40028120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR (*(RoReg*)0x40028124U) /**< \brief (USART1) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_USART1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_usart2.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_usart2.h
new file mode 100644
index 0000000..a0b9fe0
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_usart2.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_USART2_INSTANCE_
+#define _SAM3S8_USART2_INSTANCE_
+
+/* ========== Register definition for USART2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART2_CR            (0x4002C000U) /**< \brief (USART2) Control Register */
+#define REG_USART2_MR            (0x4002C004U) /**< \brief (USART2) Mode Register */
+#define REG_USART2_IER           (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
+#define REG_USART2_IDR           (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
+#define REG_USART2_IMR           (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
+#define REG_USART2_CSR           (0x4002C014U) /**< \brief (USART2) Channel Status Register */
+#define REG_USART2_RHR           (0x4002C018U) /**< \brief (USART2) Receiver Holding Register */
+#define REG_USART2_THR           (0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */
+#define REG_USART2_BRGR          (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
+#define REG_USART2_RTOR          (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
+#define REG_USART2_TTGR          (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
+#define REG_USART2_FIDI          (0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */
+#define REG_USART2_NER           (0x4002C044U) /**< \brief (USART2) Number of Errors Register */
+#define REG_USART2_IF            (0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */
+#define REG_USART2_MAN           (0x4002C050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
+#define REG_USART2_WPMR          (0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */
+#define REG_USART2_WPSR          (0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */
+#define REG_USART2_VERSION          (0x4002C0FCU) /**< \brief (USART2) Version Register */
+#define REG_USART2_RPR           (0x4002C100U) /**< \brief (USART2) Receive Pointer Register */
+#define REG_USART2_RCR           (0x4002C104U) /**< \brief (USART2) Receive Counter Register */
+#define REG_USART2_TPR           (0x4002C108U) /**< \brief (USART2) Transmit Pointer Register */
+#define REG_USART2_TCR           (0x4002C10CU) /**< \brief (USART2) Transmit Counter Register */
+#define REG_USART2_RNPR          (0x4002C110U) /**< \brief (USART2) Receive Next Pointer Register */
+#define REG_USART2_RNCR          (0x4002C114U) /**< \brief (USART2) Receive Next Counter Register */
+#define REG_USART2_TNPR          (0x4002C118U) /**< \brief (USART2) Transmit Next Pointer Register */
+#define REG_USART2_TNCR          (0x4002C11CU) /**< \brief (USART2) Transmit Next Counter Register */
+#define REG_USART2_PTCR          (0x4002C120U) /**< \brief (USART2) Transfer Control Register */
+#define REG_USART2_PTSR          (0x4002C124U) /**< \brief (USART2) Transfer Status Register */
+#else
+#define REG_USART2_CR   (*(WoReg*)0x4002C000U) /**< \brief (USART2) Control Register */
+#define REG_USART2_MR   (*(RwReg*)0x4002C004U) /**< \brief (USART2) Mode Register */
+#define REG_USART2_IER  (*(WoReg*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
+#define REG_USART2_IDR  (*(WoReg*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
+#define REG_USART2_IMR  (*(RoReg*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
+#define REG_USART2_CSR  (*(RoReg*)0x4002C014U) /**< \brief (USART2) Channel Status Register */
+#define REG_USART2_RHR  (*(RoReg*)0x4002C018U) /**< \brief (USART2) Receiver Holding Register */
+#define REG_USART2_THR  (*(WoReg*)0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */
+#define REG_USART2_BRGR (*(RwReg*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
+#define REG_USART2_RTOR (*(RwReg*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
+#define REG_USART2_TTGR (*(RwReg*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
+#define REG_USART2_FIDI (*(RwReg*)0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */
+#define REG_USART2_NER  (*(RoReg*)0x4002C044U) /**< \brief (USART2) Number of Errors Register */
+#define REG_USART2_IF   (*(RwReg*)0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */
+#define REG_USART2_MAN  (*(RwReg*)0x4002C050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
+#define REG_USART2_WPMR (*(RwReg*)0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */
+#define REG_USART2_WPSR (*(RoReg*)0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */
+#define REG_USART2_VERSION (*(RoReg*)0x4002C0FCU) /**< \brief (USART2) Version Register */
+#define REG_USART2_RPR  (*(RwReg*)0x4002C100U) /**< \brief (USART2) Receive Pointer Register */
+#define REG_USART2_RCR  (*(RwReg*)0x4002C104U) /**< \brief (USART2) Receive Counter Register */
+#define REG_USART2_TPR  (*(RwReg*)0x4002C108U) /**< \brief (USART2) Transmit Pointer Register */
+#define REG_USART2_TCR  (*(RwReg*)0x4002C10CU) /**< \brief (USART2) Transmit Counter Register */
+#define REG_USART2_RNPR (*(RwReg*)0x4002C110U) /**< \brief (USART2) Receive Next Pointer Register */
+#define REG_USART2_RNCR (*(RwReg*)0x4002C114U) /**< \brief (USART2) Receive Next Counter Register */
+#define REG_USART2_TNPR (*(RwReg*)0x4002C118U) /**< \brief (USART2) Transmit Next Pointer Register */
+#define REG_USART2_TNCR (*(RwReg*)0x4002C11CU) /**< \brief (USART2) Transmit Next Counter Register */
+#define REG_USART2_PTCR (*(WoReg*)0x4002C120U) /**< \brief (USART2) Transfer Control Register */
+#define REG_USART2_PTSR (*(RoReg*)0x4002C124U) /**< \brief (USART2) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_USART2_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_wdt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_wdt.h
new file mode 100644
index 0000000..65f1728
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/instance/instance_wdt.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_WDT_INSTANCE_
+#define _SAM3S8_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CR          (0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR          (0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR          (0x400E1458U) /**< \brief (WDT) Status Register */
+#else
+#define REG_WDT_CR (*(WoReg*)0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR (*(RwReg*)0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR (*(RoReg*)0x400E1458U) /**< \brief (WDT) Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3S8_WDT_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/pio/pio_sam3s8b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/pio/pio_sam3s8b.h
new file mode 100644
index 0000000..327bcc9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/pio/pio_sam3s8b.h
@@ -0,0 +1,279 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8B_PIO_
+#define _SAM3S8B_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+
+#endif /* _SAM3S8B_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/pio/pio_sam3s8c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/pio/pio_sam3s8c.h
new file mode 100644
index 0000000..71de509
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/pio/pio_sam3s8c.h
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8C_PIO_
+#define _SAM3S8C_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC18A_A0       (1u << 18) /**< \brief Ebi signal: A0 */
+#define PIO_PC19A_A1       (1u << 19) /**< \brief Ebi signal: A1 */
+#define PIO_PC28A_A10      (1u << 28) /**< \brief Ebi signal: A10 */
+#define PIO_PC29A_A11      (1u << 29) /**< \brief Ebi signal: A11 */
+#define PIO_PC30A_A12      (1u << 30) /**< \brief Ebi signal: A12 */
+#define PIO_PC31A_A13      (1u << 31) /**< \brief Ebi signal: A13 */
+#define PIO_PA18C_A14      (1u << 18) /**< \brief Ebi signal: A14 */
+#define PIO_PA19C_A15      (1u << 19) /**< \brief Ebi signal: A15 */
+#define PIO_PA20C_A16      (1u << 20) /**< \brief Ebi signal: A16 */
+#define PIO_PA0C_A17       (1u << 0)  /**< \brief Ebi signal: A17 */
+#define PIO_PA1C_A18       (1u << 1)  /**< \brief Ebi signal: A18 */
+#define PIO_PA23C_A19      (1u << 23) /**< \brief Ebi signal: A19 */
+#define PIO_PC20A_A2       (1u << 20) /**< \brief Ebi signal: A2 */
+#define PIO_PA24C_A20      (1u << 24) /**< \brief Ebi signal: A20 */
+#define PIO_PC16A_A21      (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC16A_NANDALE  (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC17A_A22      (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC17A_NANDCLE  (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PA25C_A23      (1u << 25) /**< \brief Ebi signal: A23 */
+#define PIO_PC21A_A3       (1u << 21) /**< \brief Ebi signal: A3 */
+#define PIO_PC22A_A4       (1u << 22) /**< \brief Ebi signal: A4 */
+#define PIO_PC23A_A5       (1u << 23) /**< \brief Ebi signal: A5 */
+#define PIO_PC24A_A6       (1u << 24) /**< \brief Ebi signal: A6 */
+#define PIO_PC25A_A7       (1u << 25) /**< \brief Ebi signal: A7 */
+#define PIO_PC26A_A8       (1u << 26) /**< \brief Ebi signal: A8 */
+#define PIO_PC27A_A9       (1u << 27) /**< \brief Ebi signal: A9 */
+#define PIO_PC0A_D0        (1u << 0)  /**< \brief Ebi signal: D0 */
+#define PIO_PC1A_D1        (1u << 1)  /**< \brief Ebi signal: D1 */
+#define PIO_PC2A_D2        (1u << 2)  /**< \brief Ebi signal: D2 */
+#define PIO_PC3A_D3        (1u << 3)  /**< \brief Ebi signal: D3 */
+#define PIO_PC4A_D4        (1u << 4)  /**< \brief Ebi signal: D4 */
+#define PIO_PC5A_D5        (1u << 5)  /**< \brief Ebi signal: D5 */
+#define PIO_PC6A_D6        (1u << 6)  /**< \brief Ebi signal: D6 */
+#define PIO_PC7A_D7        (1u << 7)  /**< \brief Ebi signal: D7 */
+#define PIO_PC9A_NANDOE    (1u << 9)  /**< \brief Ebi signal: NANDOE */
+#define PIO_PC10A_NANDWE   (1u << 10) /**< \brief Ebi signal: NANDWE */
+#define PIO_PC14A_NCS0     (1u << 14) /**< \brief Ebi signal: NCS0 */
+#define PIO_PC15A_NCS1     (1u << 15) /**< \brief Ebi signal: NCS1 */
+#define PIO_PA22C_NCS2     (1u << 22) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC12A_NCS3     (1u << 12) /**< \brief Ebi signal: NCS3 */
+#define PIO_PC11A_NRD      (1u << 11) /**< \brief Ebi signal: NRD */
+#define PIO_PC13A_NWAIT    (1u << 13) /**< \brief Ebi signal: NWAIT */
+#define PIO_PC8A_NWE       (1u << 8)  /**< \brief Ebi signal: NWE */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PC17B_CTS2     (1u << 17) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PC16B_RTS2     (1u << 16) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PC9B_RXD2      (1u << 9)  /**< \brief Usart2 signal: RXD2 */
+#define PIO_PC14B_SCK2     (1u << 14) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PC10B_TXD2     (1u << 10) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM3S8C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/pio/pio_sam3sd8b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/pio/pio_sam3sd8b.h
new file mode 100644
index 0000000..409f8d8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/pio/pio_sam3sd8b.h
@@ -0,0 +1,279 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3SD8B_PIO_
+#define _SAM3SD8B_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+
+#endif /* _SAM3SD8B_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/pio/pio_sam3sd8c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/pio/pio_sam3sd8c.h
new file mode 100644
index 0000000..1d93566
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/pio/pio_sam3sd8c.h
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3SD8C_PIO_
+#define _SAM3SD8C_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC18A_A0       (1u << 18) /**< \brief Ebi signal: A0 */
+#define PIO_PC19A_A1       (1u << 19) /**< \brief Ebi signal: A1 */
+#define PIO_PC28A_A10      (1u << 28) /**< \brief Ebi signal: A10 */
+#define PIO_PC29A_A11      (1u << 29) /**< \brief Ebi signal: A11 */
+#define PIO_PC30A_A12      (1u << 30) /**< \brief Ebi signal: A12 */
+#define PIO_PC31A_A13      (1u << 31) /**< \brief Ebi signal: A13 */
+#define PIO_PA18C_A14      (1u << 18) /**< \brief Ebi signal: A14 */
+#define PIO_PA19C_A15      (1u << 19) /**< \brief Ebi signal: A15 */
+#define PIO_PA20C_A16      (1u << 20) /**< \brief Ebi signal: A16 */
+#define PIO_PA0C_A17       (1u << 0)  /**< \brief Ebi signal: A17 */
+#define PIO_PA1C_A18       (1u << 1)  /**< \brief Ebi signal: A18 */
+#define PIO_PA23C_A19      (1u << 23) /**< \brief Ebi signal: A19 */
+#define PIO_PC20A_A2       (1u << 20) /**< \brief Ebi signal: A2 */
+#define PIO_PA24C_A20      (1u << 24) /**< \brief Ebi signal: A20 */
+#define PIO_PC16A_A21      (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC16A_NANDALE  (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC17A_A22      (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC17A_NANDCLE  (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PA25C_A23      (1u << 25) /**< \brief Ebi signal: A23 */
+#define PIO_PC21A_A3       (1u << 21) /**< \brief Ebi signal: A3 */
+#define PIO_PC22A_A4       (1u << 22) /**< \brief Ebi signal: A4 */
+#define PIO_PC23A_A5       (1u << 23) /**< \brief Ebi signal: A5 */
+#define PIO_PC24A_A6       (1u << 24) /**< \brief Ebi signal: A6 */
+#define PIO_PC25A_A7       (1u << 25) /**< \brief Ebi signal: A7 */
+#define PIO_PC26A_A8       (1u << 26) /**< \brief Ebi signal: A8 */
+#define PIO_PC27A_A9       (1u << 27) /**< \brief Ebi signal: A9 */
+#define PIO_PC0A_D0        (1u << 0)  /**< \brief Ebi signal: D0 */
+#define PIO_PC1A_D1        (1u << 1)  /**< \brief Ebi signal: D1 */
+#define PIO_PC2A_D2        (1u << 2)  /**< \brief Ebi signal: D2 */
+#define PIO_PC3A_D3        (1u << 3)  /**< \brief Ebi signal: D3 */
+#define PIO_PC4A_D4        (1u << 4)  /**< \brief Ebi signal: D4 */
+#define PIO_PC5A_D5        (1u << 5)  /**< \brief Ebi signal: D5 */
+#define PIO_PC6A_D6        (1u << 6)  /**< \brief Ebi signal: D6 */
+#define PIO_PC7A_D7        (1u << 7)  /**< \brief Ebi signal: D7 */
+#define PIO_PC9A_NANDOE    (1u << 9)  /**< \brief Ebi signal: NANDOE */
+#define PIO_PC10A_NANDWE   (1u << 10) /**< \brief Ebi signal: NANDWE */
+#define PIO_PC14A_NCS0     (1u << 14) /**< \brief Ebi signal: NCS0 */
+#define PIO_PC15A_NCS1     (1u << 15) /**< \brief Ebi signal: NCS1 */
+#define PIO_PA22C_NCS2     (1u << 22) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC12A_NCS3     (1u << 12) /**< \brief Ebi signal: NCS3 */
+#define PIO_PC11A_NRD      (1u << 11) /**< \brief Ebi signal: NRD */
+#define PIO_PC13A_NWAIT    (1u << 13) /**< \brief Ebi signal: NWAIT */
+#define PIO_PC8A_NWE       (1u << 8)  /**< \brief Ebi signal: NWE */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PC17B_CTS2     (1u << 17) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PC16B_RTS2     (1u << 16) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PC9B_RXD2      (1u << 9)  /**< \brief Usart2 signal: RXD2 */
+#define PIO_PC14B_SCK2     (1u << 14) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PC10B_TXD2     (1u << 10) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM3SD8C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3s8b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3s8b.h
new file mode 100644
index 0000000..5079033
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3s8b.h
@@ -0,0 +1,489 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8B_
+#define _SAM3S8B_
+
+/** \addtogroup SAM3S8B_definitions SAM3S8B definitions
+  This file defines all structures and symbols for SAM3S8B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S8B specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3S8B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S8B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S8B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S8B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S8B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S8B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S8B Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S8B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S8B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S8B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S8B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3S8B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S8B USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S8B Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S8B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S8B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S8B Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S8B Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S8B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S8B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S8B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3S8B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S8B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S8B Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S8B CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S8B Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM3S8B USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controler */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S8B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S8B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S8B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3sd8.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s8b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x80000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (2048u)
+#define IFLASH0_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE                (0x10000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S8B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (64000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (35000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S8B_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3s8c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3s8c.h
new file mode 100644
index 0000000..ac55e6d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3s8c.h
@@ -0,0 +1,522 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8C_
+#define _SAM3S8C_
+
+/** \addtogroup SAM3S8C_definitions SAM3S8C definitions
+  This file defines all structures and symbols for SAM3S8C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3S8C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3S8C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3S8C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3S8C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3S8C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3S8C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3S8C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3S8C Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3S8C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3S8C UART 1 (UART1) */
+  SMC_IRQn             = 10, /**< 10 SAM3S8C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3S8C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3S8C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3S8C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3S8C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3S8C USART 1 (USART1) */
+  USART2_IRQn          = 16, /**< 16 SAM3S8C USART 2 (SAM3SD8 100 pins only) (USART2) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3S8C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3S8C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3S8C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3S8C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3S8C Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3S8C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3S8C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3S8C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3S8C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3S8C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3S8C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3S8C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3S8C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3S8C Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3S8C CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3S8C Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM3S8C USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pfnSMC_Handler;    /* 10 Static Memory Controller */
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pfnUSART2_Handler; /* 16 USART 2 (SAM3SD8 100 pins only) */
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controler */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
+  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
+  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3S8C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S8C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S8C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3sd8.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_SMC    (10) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (16) /**< \brief USART 2 (SAM3SD8 100 pins only) (USART2) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x4002C000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x4002C100U) /**< \brief (PDC_USART2) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x4002C000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x4002C100U) /**< \brief (PDC_USART2) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3S8C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3s8c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x80000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (2048u)
+#define IFLASH0_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE                (0x10000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3S8C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (64000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (35000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3S8C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3sd8.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3sd8.h
new file mode 100644
index 0000000..31c59da
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3sd8.h
@@ -0,0 +1,45 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3S8_
+#define _SAM3S8_
+
+#if defined __SAM3SD8B__
+  #include "sam3sd8b.h"
+#elif defined __SAM3SD8C__
+  #include "sam3sd8c.h"
+#elif defined __SAM3S8B__
+  #include "sam3s8b.h"
+#elif defined __SAM3S8C__
+  #include "sam3s8c.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAM3S8_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3sd8b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3sd8b.h
new file mode 100644
index 0000000..646c594
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3sd8b.h
@@ -0,0 +1,497 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3SD8B_
+#define _SAM3SD8B_
+
+/** \addtogroup SAM3SD8B_definitions SAM3SD8B definitions
+  This file defines all structures and symbols for SAM3SD8B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3SD8B specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3SD8B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3SD8B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3SD8B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3SD8B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3SD8B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3SD8B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3SD8B Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3SD8B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3SD8B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM3SD8B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3SD8B Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 14, /**< 14 SAM3SD8B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3SD8B USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3SD8B Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3SD8B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3SD8B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3SD8B Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3SD8B Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3SD8B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3SD8B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3SD8B Timer/Counter 2 (TC2) */
+  ADC_IRQn             = 29, /**< 29 SAM3SD8B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3SD8B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3SD8B Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3SD8B CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3SD8B Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM3SD8B USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controler */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pvReserved26;
+  void* pvReserved27;
+  void* pvReserved28;
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3SD8B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3SD8B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3SD8B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3sd8.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3SD8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3sd8b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH0_NB_OF_LOCK_BITS  (16u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IFLASH1_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE                (0x10000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE+IFLASH1_SIZE)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3SD8B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (64000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (35000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3SD8B_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3sd8c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3sd8c.h
new file mode 100644
index 0000000..58c7110
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/sam3sd8c.h
@@ -0,0 +1,530 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3SD8C_
+#define _SAM3SD8C_
+
+/** \addtogroup SAM3SD8C_definitions SAM3SD8C definitions
+  This file defines all structures and symbols for SAM3SD8C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3SD8C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3SD8C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3SD8C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3SD8C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3SD8C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3SD8C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3SD8C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM3SD8C Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM3SD8C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM3SD8C UART 1 (UART1) */
+  SMC_IRQn             = 10, /**< 10 SAM3SD8C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3SD8C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3SD8C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3SD8C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM3SD8C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM3SD8C USART 1 (USART1) */
+  USART2_IRQn          = 16, /**< 16 SAM3SD8C USART 2 (SAM3SD8 100 pins only) (USART2) */
+  HSMCI_IRQn           = 18, /**< 18 SAM3SD8C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM3SD8C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM3SD8C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM3SD8C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM3SD8C Synchronous Serial Controler (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM3SD8C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM3SD8C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM3SD8C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM3SD8C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM3SD8C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM3SD8C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM3SD8C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM3SD8C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM3SD8C Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM3SD8C CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM3SD8C Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM3SD8C USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pfnSMC_Handler;    /* 10 Static Memory Controller */
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pfnUSART2_Handler; /* 16 USART 2 (SAM3SD8 100 pins only) */
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controler */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
+  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
+  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3SD8C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3SD8C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3SD8C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3sd8.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3SD8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_SMC    (10) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (16) /**< \brief USART 2 (SAM3SD8 100 pins only) (USART2) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controler (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x4002C000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x4002C100U) /**< \brief (PDC_USART2) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x4002C000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x4002C100U) /**< \brief (PDC_USART2) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3SD8C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3sd8c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH0_NB_OF_LOCK_BITS  (16u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IFLASH1_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE                (0x10000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE+IFLASH1_SIZE)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3SD8C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (64000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (35000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3SD8C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/system_sam3sd8.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/system_sam3sd8.h
new file mode 100644
index 0000000..5fbfcdd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/include/system_sam3sd8.h
@@ -0,0 +1,58 @@
+/*! \file *********************************************************************
+ *
+ * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
+ *           for SAM3 devices.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef SYSTEM_SAM3SD8_H_INCLUDED
+#define SYSTEM_SAM3SD8_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#include 
+
+extern uint32_t SystemCoreClock;	/* System Clock Frequency (Core Clock) */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock with current core Clock 
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+/** 
+ * Initialize flash.
+ */
+void system_init_flash(uint32_t dw_clk);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* SYSTEM_SAM3SD8_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8_flash.ld
new file mode 100644
index 0000000..ecd5016
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8_sram.ld
new file mode 100644
index 0000000..7a42187
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8b_flash.ld
new file mode 100644
index 0000000..7cd4659
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8b_sram.ld
new file mode 100644
index 0000000..58aa97f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8c_flash.ld
new file mode 100644
index 0000000..7cd4659
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8c_sram.ld
new file mode 100644
index 0000000..58aa97f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3s_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8_flash.ld
new file mode 100644
index 0000000..cbf2c7a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash has two banks, one bank = 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3sd_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8_sram.ld
new file mode 100644
index 0000000..2605a96
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash has two banks, one bank = 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3sd_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8b_flash.ld
new file mode 100644
index 0000000..bf6fca9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8b_sram.ld
new file mode 100644
index 0000000..3f44674
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8c_flash.ld
new file mode 100644
index 0000000..bf6fca9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8c_sram.ld
new file mode 100644
index 0000000..3f44674
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/sam3sd_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/startup_sam3sd8.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/startup_sam3sd8.c
new file mode 100644
index 0000000..eff8efc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/as_gcc/startup_sam3sd8.c
@@ -0,0 +1,234 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3sd8.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_SMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_USART2_INSTANCE_
+void USART2_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_USART2_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ACC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDP_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM3S8_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3S8_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3S8_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3S8_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#ifdef _SAM3S8_USART2_INSTANCE_
+	(void*) USART2_Handler,  /* 16 USART 2 */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3S8_USART2_INSTANCE_ */
+	(void*) (0UL),           /* 17 Reserved */
+	(void*) HSMCI_Handler,   /* 18 MCI */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3S8_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3S8_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8_flash.ld
new file mode 100644
index 0000000..ecd5016
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8_sram.ld
new file mode 100644
index 0000000..7a42187
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8b_flash.ld
new file mode 100644
index 0000000..7cd4659
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8b_sram.ld
new file mode 100644
index 0000000..58aa97f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8c_flash.ld
new file mode 100644
index 0000000..7cd4659
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8c_sram.ld
new file mode 100644
index 0000000..58aa97f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3s_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8_flash.ld
new file mode 100644
index 0000000..cbf2c7a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash has two banks, one bank = 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3sd_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8_sram.ld
new file mode 100644
index 0000000..2605a96
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash has two banks, one bank = 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3sd_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8b_flash.ld
new file mode 100644
index 0000000..bf6fca9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8b_sram.ld
new file mode 100644
index 0000000..3f44674
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8c_flash.ld
new file mode 100644
index 0000000..bf6fca9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8c_sram.ld
new file mode 100644
index 0000000..3f44674
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/sam3sd_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/startup_sam3sd8.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/startup_sam3sd8.c
new file mode 100644
index 0000000..eff8efc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc/startup_sam3sd8.c
@@ -0,0 +1,234 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3sd8.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_SMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_USART2_INSTANCE_
+void USART2_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_USART2_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ACC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDP_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM3S8_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3S8_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3S8_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3S8_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#ifdef _SAM3S8_USART2_INSTANCE_
+	(void*) USART2_Handler,  /* 16 USART 2 */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3S8_USART2_INSTANCE_ */
+	(void*) (0UL),           /* 17 Reserved */
+	(void*) HSMCI_Handler,   /* 18 MCI */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3S8_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3S8_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8_flash.ld
new file mode 100644
index 0000000..ecd5016
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8_sram.ld
new file mode 100644
index 0000000..7a42187
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8b_flash.ld
new file mode 100644
index 0000000..7cd4659
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8b_sram.ld
new file mode 100644
index 0000000..58aa97f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8c_flash.ld
new file mode 100644
index 0000000..7cd4659
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8c_sram.ld
new file mode 100644
index 0000000..58aa97f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3s_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8_flash.ld
new file mode 100644
index 0000000..cbf2c7a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash has two banks, one bank = 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3sd_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8_sram.ld
new file mode 100644
index 0000000..2605a96
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash has two banks, one bank = 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3sd_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8b_flash.ld
new file mode 100644
index 0000000..bf6fca9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8b_sram.ld
new file mode 100644
index 0000000..3f44674
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8c_flash.ld
new file mode 100644
index 0000000..bf6fca9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8c_sram.ld
new file mode 100644
index 0000000..3f44674
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/sam3sd_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/startup_sam3sd8.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/startup_sam3sd8.c
new file mode 100644
index 0000000..eff8efc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_arm/startup_sam3sd8.c
@@ -0,0 +1,234 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3sd8.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_SMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_USART2_INSTANCE_
+void USART2_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_USART2_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ACC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDP_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM3S8_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3S8_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3S8_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3S8_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#ifdef _SAM3S8_USART2_INSTANCE_
+	(void*) USART2_Handler,  /* 16 USART 2 */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3S8_USART2_INSTANCE_ */
+	(void*) (0UL),           /* 17 Reserved */
+	(void*) HSMCI_Handler,   /* 18 MCI */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3S8_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3S8_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8_flash.ld
new file mode 100644
index 0000000..ecd5016
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8_sram.ld
new file mode 100644
index 0000000..7a42187
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8b_flash.ld
new file mode 100644
index 0000000..7cd4659
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8b_sram.ld
new file mode 100644
index 0000000..58aa97f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8c_flash.ld
new file mode 100644
index 0000000..7cd4659
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8c_sram.ld
new file mode 100644
index 0000000..58aa97f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3s_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8_flash.ld
new file mode 100644
index 0000000..cbf2c7a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8_flash.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash has two banks, one bank = 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3sd_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8_sram.ld
new file mode 100644
index 0000000..2605a96
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8_sram.ld
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* flash has two banks, one bank = 256K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3sd_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8b_flash.ld
new file mode 100644
index 0000000..bf6fca9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8b_sram.ld
new file mode 100644
index 0000000..3f44674
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8c_flash.ld
new file mode 100644
index 0000000..bf6fca9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8c_sram.ld
new file mode 100644
index 0000000..3f44674
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3sd8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/sam3sd_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/startup_sam3sd8.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/startup_sam3sd8.c
new file mode 100644
index 0000000..eff8efc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/gcc_atmel/startup_sam3sd8.c
@@ -0,0 +1,234 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3sd8.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_SMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_USART2_INSTANCE_
+void USART2_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_USART2_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3S8_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3S8_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ACC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDP_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM3S8_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3S8_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3S8_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3S8_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#ifdef _SAM3S8_USART2_INSTANCE_
+	(void*) USART2_Handler,  /* 16 USART 2 */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3S8_USART2_INSTANCE_ */
+	(void*) (0UL),           /* 17 Reserved */
+	(void*) HSMCI_Handler,   /* 18 MCI */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3S8_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3S8_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/sam3s8_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/sam3s8_flash.icf
new file mode 100644
index 0000000..074c453
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/sam3s8_flash.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00400000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2000FFFF;
+define symbol __ICFEDIT_region_ROM_start__  = 0x00400000;
+define symbol __ICFEDIT_region_ROM_end__    = 0x0047FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x3000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region     = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in ROM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/sam3s8_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/sam3s8_sram.icf
new file mode 100644
index 0000000..d054dd8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/sam3s8_sram.icf
@@ -0,0 +1,26 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in RAM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/sam3sd8_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/sam3sd8_flash.icf
new file mode 100644
index 0000000..d8bacb2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/sam3sd8_flash.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00400000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2000FFFF;
+define symbol __ICFEDIT_region_ROM_start__  = 0x00400000;
+define symbol __ICFEDIT_region_ROM_end__    = 0x0043FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x3000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region     = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in ROM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/sam3sd8_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/sam3sd8_sram.icf
new file mode 100644
index 0000000..e593845
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/sam3sd8_sram.icf
@@ -0,0 +1,27 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+/*place in RAM_region          { readonly, readwrite, block CSTACK, block HEAP };*/
+place in RAM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/startup_sam3sd8.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/startup_sam3sd8.c
new file mode 100644
index 0000000..af78062
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/iar/startup_sam3sd8.c
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3sd8.h"
+
+/* Initialize segments */
+extern uint32_t __cstack_start__;
+extern uint32_t __cstack_end__;
+
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+#pragma weak NMI_Handler=Dummy_Handler
+#pragma weak HardFault_Handler=Dummy_Handler
+#pragma weak MemManage_Handler=Dummy_Handler
+#pragma weak BusFault_Handler=Dummy_Handler
+#pragma weak UsageFault_Handler=Dummy_Handler
+#pragma weak SVC_Handler=Dummy_Handler
+#pragma weak DebugMon_Handler=Dummy_Handler
+#pragma weak PendSV_Handler=Dummy_Handler
+#pragma weak SysTick_Handler=Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak SUPC_Handler=Dummy_Handler
+#pragma weak RSTC_Handler=Dummy_Handler
+#pragma weak RTC_Handler=Dummy_Handler
+#pragma weak RTT_Handler=Dummy_Handler
+#pragma weak WDT_Handler=Dummy_Handler
+#pragma weak PMC_Handler=Dummy_Handler
+#pragma weak EFC_Handler=Dummy_Handler
+#pragma weak UART0_Handler=Dummy_Handler
+#pragma weak UART1_Handler=Dummy_Handler
+#pragma weak SMC_Handler=Dummy_Handler
+#pragma weak PIOA_Handler=Dummy_Handler
+#pragma weak PIOB_Handler=Dummy_Handler
+#pragma weak PIOC_Handler=Dummy_Handler
+#pragma weak USART0_Handler=Dummy_Handler
+#pragma weak USART1_Handler=Dummy_Handler
+#pragma weak HSMCI_Handler=Dummy_Handler
+#pragma weak TWI0_Handler=Dummy_Handler
+#pragma weak TWI1_Handler=Dummy_Handler
+#pragma weak SPI_Handler=Dummy_Handler
+#pragma weak SSC_Handler=Dummy_Handler
+#pragma weak TC0_Handler=Dummy_Handler
+#pragma weak TC1_Handler=Dummy_Handler
+#pragma weak TC2_Handler=Dummy_Handler
+#pragma weak TC3_Handler=Dummy_Handler
+#pragma weak TC4_Handler=Dummy_Handler
+#pragma weak TC5_Handler=Dummy_Handler
+#pragma weak ADC_Handler=Dummy_Handler
+#pragma weak DACC_Handler=Dummy_Handler
+#pragma weak PWM_Handler=Dummy_Handler
+#pragma weak CRCCU_Handler=Dummy_Handler
+#pragma weak ACC_Handler=Dummy_Handler
+#pragma weak UDP_Handler=Dummy_Handler
+
+/* Exception Table */
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section = ".intvec"
+#pragma location = ".intvec"
+const DeviceVectors __vector_table[] = {
+	(void*) (&__cstack_end__),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM3S8_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3S8_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3S8_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3S8_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#ifdef _SAM3S8_USART2_INSTANCE_
+	(void*) USART2_Handler,  /* 16 USART 2 */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3S8_USART2_INSTANCE_ */
+	(void*) (0UL),           /* 17 Reserved */
+	(void*) HSMCI_Handler,   /* 18 MCI */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM3S8_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM3S8_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+	uint32_t *pSrc = __section_begin(".intvec");
+
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+	__iar_program_start();
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/system_sam3sd8.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/system_sam3sd8.c
new file mode 100644
index 0000000..7db1834
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3sd8/source/system_sam3sd8.c
@@ -0,0 +1,195 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3sd8.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Clock settings (64MHz) */
+#define SYS_BOARD_OSCOUNT   (CKGR_MOR_MOSCXTST(0x8UL))
+#define SYS_BOARD_PLLAR     (CKGR_PLLAR_ONE \
+							| CKGR_PLLAR_MULA(0x1fUL) \
+							| CKGR_PLLAR_PLLACOUNT(0x3fUL) \
+							| CKGR_PLLAR_DIVA(0x3UL))
+#define SYS_BOARD_MCKR      (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)
+
+#define SYS_CKGR_MOR_KEY_VALUE	CKGR_MOR_KEY(0x37UL) /* Key to unlock MOR register */
+
+/* FIXME: should be generated by sock */
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+/**
+ * \brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit(void)
+{
+	/* Set FWS according to SYS_BOARD_MCKR configuration */
+	EFC->EEFC_FMR = EEFC_FMR_FWS(3);
+
+	/* Initialize main oscillator */
+	if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
+		PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
+			                     CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+		while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
+		}
+	}
+
+	/* Switch to 3-20MHz Xtal oscillator */
+	PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN |
+                             CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+
+	while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
+	}
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Initialize PLLA */
+	PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
+	while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
+	}
+
+	/* Switch to main clock */
+	PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Switch to PLLA */
+	PMC->PMC_MCKR = SYS_BOARD_MCKR;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	SystemCoreClock = CHIP_FREQ_CPU_MAX;
+}
+
+void SystemCoreClockUpdate(void)
+{
+	/* Determine clock frequency according to clock register values */
+	switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
+	case PMC_MCKR_CSS_SLOW_CLK:	/* Slow clock */
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_32K;
+		} else {
+			SystemCoreClock = CHIP_FREQ_SLCK_RC;
+		}
+		break;
+	case PMC_MCKR_CSS_MAIN_CLK:	/* Main clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	case PMC_MCKR_CSS_PLLA_CLK:	/* PLLA clock */
+	case PMC_MCKR_CSS_PLLB_CLK:	/* PLLB clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
+			SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
+				                          CKGR_PLLAR_MULA_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
+				                          CKGR_PLLAR_DIVA_Pos));
+		} else {
+			SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >>
+				                          CKGR_PLLBR_MULB_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >>
+				                          CKGR_PLLBR_DIVB_Pos));
+		}
+		break;
+	default:
+		break;
+	}
+
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
+		SystemCoreClock /= 3U;
+	} else {
+		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
+	}
+}
+
+/**
+ * Initialize flash.
+ */
+void system_init_flash(uint32_t dw_clk)
+{
+	/* Set FWS for embedded Flash access according to operating frequency */
+	if (dw_clk < CHIP_FREQ_FWS_0) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(0);
+	} else if (dw_clk < CHIP_FREQ_FWS_1) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(1);
+	} else if (dw_clk < CHIP_FREQ_FWS_2) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(2);
+	} else {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(3);
+	}
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_adc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_adc.h
new file mode 100644
index 0000000..da0f2fb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_adc.h
@@ -0,0 +1,241 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_ADC_COMPONENT_
+#define _SAM3U_ADC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM3U_ADC Analog-to-digital Converter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Adc hardware registers */
+typedef struct {
+  WoReg ADC_CR;        /**< \brief (Adc Offset: 0x00) Control Register */
+  RwReg ADC_MR;        /**< \brief (Adc Offset: 0x04) Mode Register */
+  RoReg Reserved1[2];
+  WoReg ADC_CHER;      /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+  WoReg ADC_CHDR;      /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+  RoReg ADC_CHSR;      /**< \brief (Adc Offset: 0x18) Channel Status Register */
+  RoReg ADC_SR;        /**< \brief (Adc Offset: 0x1C) Status Register */
+  RoReg ADC_LCDR;      /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+  WoReg ADC_IER;       /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC_IDR;       /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC_IMR;       /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC_CDR[8];    /**< \brief (Adc Offset: 0x30) Channel Data Register */
+  RoReg Reserved2[44];
+  RwReg ADC_RPR;       /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+  RwReg ADC_RCR;       /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+  RoReg Reserved3[2];
+  RwReg ADC_RNPR;      /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC_RNCR;      /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+  RoReg Reserved4[2];
+  WoReg ADC_PTCR;      /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+  RoReg ADC_PTSR;      /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define   ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define   ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define ADC_MR_TRGSEL(value) ((ADC_MR_TRGSEL_Msk & ((value) << ADC_MR_TRGSEL_Pos)))
+#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x6u << 1) /**< \brief (ADC_MR) External trigger */
+#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x0u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */
+#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */
+#define   ADC_MR_TRGSEL_ADC_TRIG4 (0x3u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG5 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
+#define   ADC_MR_LOWRES_BITS_10 (0x0u << 4) /**< \brief (ADC_MR) 10-bit resolution */
+#define   ADC_MR_LOWRES_BITS_8 (0x1u << 4) /**< \brief (ADC_MR) 8-bit resolution */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define   ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
+#define   ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0x7fu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define ADC_MR_STARTUP(value) ((ADC_MR_STARTUP_Msk & ((value) << ADC_MR_STARTUP_Pos)))
+#define ADC_MR_SHTIM_Pos 24
+#define ADC_MR_SHTIM_Msk (0xfu << ADC_MR_SHTIM_Pos) /**< \brief (ADC_MR) Sample & Hold Time */
+#define ADC_MR_SHTIM(value) ((ADC_MR_SHTIM_Msk & ((value) << ADC_MR_SHTIM_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+/* -------- ADC_SR : (ADC Offset: 0x1C) Status Register -------- */
+#define ADC_SR_EOC0 (0x1u << 0) /**< \brief (ADC_SR) End of Conversion 0 */
+#define ADC_SR_EOC1 (0x1u << 1) /**< \brief (ADC_SR) End of Conversion 1 */
+#define ADC_SR_EOC2 (0x1u << 2) /**< \brief (ADC_SR) End of Conversion 2 */
+#define ADC_SR_EOC3 (0x1u << 3) /**< \brief (ADC_SR) End of Conversion 3 */
+#define ADC_SR_EOC4 (0x1u << 4) /**< \brief (ADC_SR) End of Conversion 4 */
+#define ADC_SR_EOC5 (0x1u << 5) /**< \brief (ADC_SR) End of Conversion 5 */
+#define ADC_SR_EOC6 (0x1u << 6) /**< \brief (ADC_SR) End of Conversion 6 */
+#define ADC_SR_EOC7 (0x1u << 7) /**< \brief (ADC_SR) End of Conversion 7 */
+#define ADC_SR_OVRE0 (0x1u << 8) /**< \brief (ADC_SR) Overrun Error 0 */
+#define ADC_SR_OVRE1 (0x1u << 9) /**< \brief (ADC_SR) Overrun Error 1 */
+#define ADC_SR_OVRE2 (0x1u << 10) /**< \brief (ADC_SR) Overrun Error 2 */
+#define ADC_SR_OVRE3 (0x1u << 11) /**< \brief (ADC_SR) Overrun Error 3 */
+#define ADC_SR_OVRE4 (0x1u << 12) /**< \brief (ADC_SR) Overrun Error 4 */
+#define ADC_SR_OVRE5 (0x1u << 13) /**< \brief (ADC_SR) Overrun Error 5 */
+#define ADC_SR_OVRE6 (0x1u << 14) /**< \brief (ADC_SR) Overrun Error 6 */
+#define ADC_SR_OVRE7 (0x1u << 15) /**< \brief (ADC_SR) Overrun Error 7 */
+#define ADC_SR_DRDY (0x1u << 16) /**< \brief (ADC_SR) Data Ready */
+#define ADC_SR_GOVRE (0x1u << 17) /**< \brief (ADC_SR) General Overrun Error */
+#define ADC_SR_ENDRX (0x1u << 18) /**< \brief (ADC_SR) End of RX Buffer */
+#define ADC_SR_RXBUFF (0x1u << 19) /**< \brief (ADC_SR) RX Buffer Full */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0x3ffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_OVRE0 (0x1u << 8) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 0 */
+#define ADC_IER_OVRE1 (0x1u << 9) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 1 */
+#define ADC_IER_OVRE2 (0x1u << 10) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 2 */
+#define ADC_IER_OVRE3 (0x1u << 11) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 3 */
+#define ADC_IER_OVRE4 (0x1u << 12) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 4 */
+#define ADC_IER_OVRE5 (0x1u << 13) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 5 */
+#define ADC_IER_OVRE6 (0x1u << 14) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 6 */
+#define ADC_IER_OVRE7 (0x1u << 15) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 7 */
+#define ADC_IER_DRDY (0x1u << 16) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 17) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 18) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 19) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_OVRE0 (0x1u << 8) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 0 */
+#define ADC_IDR_OVRE1 (0x1u << 9) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 1 */
+#define ADC_IDR_OVRE2 (0x1u << 10) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 2 */
+#define ADC_IDR_OVRE3 (0x1u << 11) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 3 */
+#define ADC_IDR_OVRE4 (0x1u << 12) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 4 */
+#define ADC_IDR_OVRE5 (0x1u << 13) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 5 */
+#define ADC_IDR_OVRE6 (0x1u << 14) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 6 */
+#define ADC_IDR_OVRE7 (0x1u << 15) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 7 */
+#define ADC_IDR_DRDY (0x1u << 16) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 17) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 18) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 19) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_OVRE0 (0x1u << 8) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 0 */
+#define ADC_IMR_OVRE1 (0x1u << 9) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 1 */
+#define ADC_IMR_OVRE2 (0x1u << 10) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 2 */
+#define ADC_IMR_OVRE3 (0x1u << 11) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 3 */
+#define ADC_IMR_OVRE4 (0x1u << 12) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 4 */
+#define ADC_IMR_OVRE5 (0x1u << 13) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 5 */
+#define ADC_IMR_OVRE6 (0x1u << 14) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 6 */
+#define ADC_IMR_OVRE7 (0x1u << 15) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 7 */
+#define ADC_IMR_DRDY (0x1u << 16) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 17) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 18) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 19) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_CDR[8] : (ADC Offset: 0x30) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0x3ffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[8]) Converted Data */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_ADC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_adc12b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_adc12b.h
new file mode 100644
index 0000000..a36df4c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_adc12b.h
@@ -0,0 +1,258 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_ADC12B_COMPONENT_
+#define _SAM3U_ADC12B_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-Digital-Converter 12bits */
+/* ============================================================================= */
+/** \addtogroup SAM3U_ADC12B Analog-to-Digital-Converter 12bits */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Adc12b hardware registers */
+typedef struct {
+  WoReg ADC12B_CR;     /**< \brief (Adc12b Offset: 0x00) Control Register */
+  RwReg ADC12B_MR;     /**< \brief (Adc12b Offset: 0x04) Mode Register */
+  RoReg Reserved1[2];
+  WoReg ADC12B_CHER;   /**< \brief (Adc12b Offset: 0x10) Channel Enable Register */
+  WoReg ADC12B_CHDR;   /**< \brief (Adc12b Offset: 0x14) Channel Disable Register */
+  RoReg ADC12B_CHSR;   /**< \brief (Adc12b Offset: 0x18) Channel Status Register */
+  RoReg ADC12B_SR;     /**< \brief (Adc12b Offset: 0x1C) Status Register */
+  RoReg ADC12B_LCDR;   /**< \brief (Adc12b Offset: 0x20) Last Converted Data Register */
+  WoReg ADC12B_IER;    /**< \brief (Adc12b Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC12B_IDR;    /**< \brief (Adc12b Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC12B_IMR;    /**< \brief (Adc12b Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC12B_CDR[8]; /**< \brief (Adc12b Offset: 0x30) Channel Data Register */
+  RoReg Reserved2[5];
+  RwReg ADC12B_ACR;    /**< \brief (Adc12b Offset: 0x64) Analog Control Register */
+  RwReg ADC12B_EMR;    /**< \brief (Adc12b Offset: 0x68) Extended Mode Register */
+  RoReg Reserved3[37];
+  RwReg ADC12B_RPR;    /**< \brief (Adc12b Offset: 0x100) Receive Pointer Register */
+  RwReg ADC12B_RCR;    /**< \brief (Adc12b Offset: 0x104) Receive Counter Register */
+  RoReg Reserved4[2];
+  RwReg ADC12B_RNPR;   /**< \brief (Adc12b Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC12B_RNCR;   /**< \brief (Adc12b Offset: 0x114) Receive Next Counter Register */
+  RoReg Reserved5[2];
+  WoReg ADC12B_PTCR;   /**< \brief (Adc12b Offset: 0x120) Transfer Control Register */
+  RoReg ADC12B_PTSR;   /**< \brief (Adc12b Offset: 0x124) Transfer Status Register */
+} Adc12b;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ADC12B_CR : (ADC12B Offset: 0x00) Control Register -------- */
+#define ADC12B_CR_SWRST (0x1u << 0) /**< \brief (ADC12B_CR) Software Reset */
+#define ADC12B_CR_START (0x1u << 1) /**< \brief (ADC12B_CR) Start Conversion */
+/* -------- ADC12B_MR : (ADC12B Offset: 0x04) Mode Register -------- */
+#define ADC12B_MR_TRGEN (0x1u << 0) /**< \brief (ADC12B_MR) Trigger Enable */
+#define   ADC12B_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC12B_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define   ADC12B_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC12B_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC12B_MR_TRGSEL_Pos 1
+#define ADC12B_MR_TRGSEL_Msk (0x7u << ADC12B_MR_TRGSEL_Pos) /**< \brief (ADC12B_MR) Trigger Selection */
+#define ADC12B_MR_TRGSEL(value) ((ADC12B_MR_TRGSEL_Msk & ((value) << ADC12B_MR_TRGSEL_Pos)))
+#define   ADC12B_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC12B_MR) External trigger */
+#define   ADC12B_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC12B_MR) TIO Output of the Timer Counter Channel 0 */
+#define   ADC12B_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC12B_MR) TIO Output of the Timer Counter Channel 1 */
+#define   ADC12B_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC12B_MR) TIO Output of the Timer Counter Channel 2 */
+#define   ADC12B_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC12B_MR) PWM Event Line 0 */
+#define   ADC12B_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC12B_MR) PWM Event Line 1 */
+#define ADC12B_MR_LOWRES (0x1u << 4) /**< \brief (ADC12B_MR) Resolution */
+#define   ADC12B_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC12B_MR) 12-bit resolution */
+#define   ADC12B_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC12B_MR) 10-bit resolution */
+#define ADC12B_MR_SLEEP (0x1u << 5) /**< \brief (ADC12B_MR) Sleep Mode */
+#define   ADC12B_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC12B_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
+#define   ADC12B_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC12B_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
+#define ADC12B_MR_PRESCAL_Pos 8
+#define ADC12B_MR_PRESCAL_Msk (0xffu << ADC12B_MR_PRESCAL_Pos) /**< \brief (ADC12B_MR) Prescaler Rate Selection */
+#define ADC12B_MR_PRESCAL(value) ((ADC12B_MR_PRESCAL_Msk & ((value) << ADC12B_MR_PRESCAL_Pos)))
+#define ADC12B_MR_STARTUP_Pos 16
+#define ADC12B_MR_STARTUP_Msk (0xffu << ADC12B_MR_STARTUP_Pos) /**< \brief (ADC12B_MR) Start Up Time */
+#define ADC12B_MR_STARTUP(value) ((ADC12B_MR_STARTUP_Msk & ((value) << ADC12B_MR_STARTUP_Pos)))
+#define ADC12B_MR_SHTIM_Pos 24
+#define ADC12B_MR_SHTIM_Msk (0xfu << ADC12B_MR_SHTIM_Pos) /**< \brief (ADC12B_MR) Sample & Hold Time */
+#define ADC12B_MR_SHTIM(value) ((ADC12B_MR_SHTIM_Msk & ((value) << ADC12B_MR_SHTIM_Pos)))
+/* -------- ADC12B_CHER : (ADC12B Offset: 0x10) Channel Enable Register -------- */
+#define ADC12B_CHER_CH0 (0x1u << 0) /**< \brief (ADC12B_CHER) Channel 0 Enable */
+#define ADC12B_CHER_CH1 (0x1u << 1) /**< \brief (ADC12B_CHER) Channel 1 Enable */
+#define ADC12B_CHER_CH2 (0x1u << 2) /**< \brief (ADC12B_CHER) Channel 2 Enable */
+#define ADC12B_CHER_CH3 (0x1u << 3) /**< \brief (ADC12B_CHER) Channel 3 Enable */
+#define ADC12B_CHER_CH4 (0x1u << 4) /**< \brief (ADC12B_CHER) Channel 4 Enable */
+#define ADC12B_CHER_CH5 (0x1u << 5) /**< \brief (ADC12B_CHER) Channel 5 Enable */
+#define ADC12B_CHER_CH6 (0x1u << 6) /**< \brief (ADC12B_CHER) Channel 6 Enable */
+#define ADC12B_CHER_CH7 (0x1u << 7) /**< \brief (ADC12B_CHER) Channel 7 Enable */
+/* -------- ADC12B_CHDR : (ADC12B Offset: 0x14) Channel Disable Register -------- */
+#define ADC12B_CHDR_CH0 (0x1u << 0) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH1 (0x1u << 1) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH2 (0x1u << 2) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH3 (0x1u << 3) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH4 (0x1u << 4) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH5 (0x1u << 5) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH6 (0x1u << 6) /**< \brief (ADC12B_CHDR)  */
+#define ADC12B_CHDR_CH7 (0x1u << 7) /**< \brief (ADC12B_CHDR)  */
+/* -------- ADC12B_CHSR : (ADC12B Offset: 0x18) Channel Status Register -------- */
+#define ADC12B_CHSR_CH0 (0x1u << 0) /**< \brief (ADC12B_CHSR) Channel 0 Status */
+#define ADC12B_CHSR_CH1 (0x1u << 1) /**< \brief (ADC12B_CHSR) Channel 1 Status */
+#define ADC12B_CHSR_CH2 (0x1u << 2) /**< \brief (ADC12B_CHSR) Channel 2 Status */
+#define ADC12B_CHSR_CH3 (0x1u << 3) /**< \brief (ADC12B_CHSR) Channel 3 Status */
+#define ADC12B_CHSR_CH4 (0x1u << 4) /**< \brief (ADC12B_CHSR) Channel 4 Status */
+#define ADC12B_CHSR_CH5 (0x1u << 5) /**< \brief (ADC12B_CHSR) Channel 5 Status */
+#define ADC12B_CHSR_CH6 (0x1u << 6) /**< \brief (ADC12B_CHSR) Channel 6 Status */
+#define ADC12B_CHSR_CH7 (0x1u << 7) /**< \brief (ADC12B_CHSR) Channel 7 Status */
+/* -------- ADC12B_SR : (ADC12B Offset: 0x1C) Status Register -------- */
+#define ADC12B_SR_EOC0 (0x1u << 0) /**< \brief (ADC12B_SR) End of Conversion 0 */
+#define ADC12B_SR_EOC1 (0x1u << 1) /**< \brief (ADC12B_SR) End of Conversion 1 */
+#define ADC12B_SR_EOC2 (0x1u << 2) /**< \brief (ADC12B_SR) End of Conversion 2 */
+#define ADC12B_SR_EOC3 (0x1u << 3) /**< \brief (ADC12B_SR) End of Conversion 3 */
+#define ADC12B_SR_EOC4 (0x1u << 4) /**< \brief (ADC12B_SR) End of Conversion 4 */
+#define ADC12B_SR_EOC5 (0x1u << 5) /**< \brief (ADC12B_SR) End of Conversion 5 */
+#define ADC12B_SR_EOC6 (0x1u << 6) /**< \brief (ADC12B_SR) End of Conversion 6 */
+#define ADC12B_SR_EOC7 (0x1u << 7) /**< \brief (ADC12B_SR) End of Conversion 7 */
+#define ADC12B_SR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_SR) Overrun Error 0 */
+#define ADC12B_SR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_SR) Overrun Error 1 */
+#define ADC12B_SR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_SR) Overrun Error 2 */
+#define ADC12B_SR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_SR) Overrun Error 3 */
+#define ADC12B_SR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_SR) Overrun Error 4 */
+#define ADC12B_SR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_SR) Overrun Error 5 */
+#define ADC12B_SR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_SR) Overrun Error 6 */
+#define ADC12B_SR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_SR) Overrun Error 7 */
+#define ADC12B_SR_DRDY (0x1u << 16) /**< \brief (ADC12B_SR) Data Ready */
+#define ADC12B_SR_GOVRE (0x1u << 17) /**< \brief (ADC12B_SR) General Overrun Error */
+#define ADC12B_SR_ENDRX (0x1u << 18) /**< \brief (ADC12B_SR) End of RX Buffer */
+#define ADC12B_SR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_SR) RX Buffer Full */
+/* -------- ADC12B_LCDR : (ADC12B Offset: 0x20) Last Converted Data Register -------- */
+#define ADC12B_LCDR_LDATA_Pos 0
+#define ADC12B_LCDR_LDATA_Msk (0xfffu << ADC12B_LCDR_LDATA_Pos) /**< \brief (ADC12B_LCDR) Last Data Converted */
+/* -------- ADC12B_IER : (ADC12B Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC12B_IER_EOC0 (0x1u << 0) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 0 */
+#define ADC12B_IER_EOC1 (0x1u << 1) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 1 */
+#define ADC12B_IER_EOC2 (0x1u << 2) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 2 */
+#define ADC12B_IER_EOC3 (0x1u << 3) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 3 */
+#define ADC12B_IER_EOC4 (0x1u << 4) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 4 */
+#define ADC12B_IER_EOC5 (0x1u << 5) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 5 */
+#define ADC12B_IER_EOC6 (0x1u << 6) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 6 */
+#define ADC12B_IER_EOC7 (0x1u << 7) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 7 */
+#define ADC12B_IER_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 0 */
+#define ADC12B_IER_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 1 */
+#define ADC12B_IER_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 2 */
+#define ADC12B_IER_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 3 */
+#define ADC12B_IER_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 4 */
+#define ADC12B_IER_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 5 */
+#define ADC12B_IER_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 6 */
+#define ADC12B_IER_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 7 */
+#define ADC12B_IER_DRDY (0x1u << 16) /**< \brief (ADC12B_IER) Data Ready Interrupt Enable */
+#define ADC12B_IER_GOVRE (0x1u << 17) /**< \brief (ADC12B_IER) General Overrun Error Interrupt Enable */
+#define ADC12B_IER_ENDRX (0x1u << 18) /**< \brief (ADC12B_IER) End of Receive Buffer Interrupt Enable */
+#define ADC12B_IER_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC12B_IDR : (ADC12B Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC12B_IDR_EOC0 (0x1u << 0) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC12B_IDR_EOC1 (0x1u << 1) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC12B_IDR_EOC2 (0x1u << 2) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC12B_IDR_EOC3 (0x1u << 3) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC12B_IDR_EOC4 (0x1u << 4) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC12B_IDR_EOC5 (0x1u << 5) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC12B_IDR_EOC6 (0x1u << 6) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC12B_IDR_EOC7 (0x1u << 7) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC12B_IDR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 0 */
+#define ADC12B_IDR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 1 */
+#define ADC12B_IDR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 2 */
+#define ADC12B_IDR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 3 */
+#define ADC12B_IDR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 4 */
+#define ADC12B_IDR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 5 */
+#define ADC12B_IDR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 6 */
+#define ADC12B_IDR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 7 */
+#define ADC12B_IDR_DRDY (0x1u << 16) /**< \brief (ADC12B_IDR) Data Ready Interrupt Disable */
+#define ADC12B_IDR_GOVRE (0x1u << 17) /**< \brief (ADC12B_IDR) General Overrun Error Interrupt Disable */
+#define ADC12B_IDR_ENDRX (0x1u << 18) /**< \brief (ADC12B_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC12B_IDR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC12B_IMR : (ADC12B Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC12B_IMR_EOC0 (0x1u << 0) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC12B_IMR_EOC1 (0x1u << 1) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC12B_IMR_EOC2 (0x1u << 2) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC12B_IMR_EOC3 (0x1u << 3) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC12B_IMR_EOC4 (0x1u << 4) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC12B_IMR_EOC5 (0x1u << 5) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC12B_IMR_EOC6 (0x1u << 6) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC12B_IMR_EOC7 (0x1u << 7) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC12B_IMR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 0 */
+#define ADC12B_IMR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 1 */
+#define ADC12B_IMR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 2 */
+#define ADC12B_IMR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 3 */
+#define ADC12B_IMR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 4 */
+#define ADC12B_IMR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 5 */
+#define ADC12B_IMR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 6 */
+#define ADC12B_IMR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 7 */
+#define ADC12B_IMR_DRDY (0x1u << 16) /**< \brief (ADC12B_IMR) Data Ready Interrupt Mask */
+#define ADC12B_IMR_GOVRE (0x1u << 17) /**< \brief (ADC12B_IMR) General Overrun Error Interrupt Mask */
+#define ADC12B_IMR_ENDRX (0x1u << 18) /**< \brief (ADC12B_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC12B_IMR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC12B_CDR[8] : (ADC12B Offset: 0x30) Channel Data Register -------- */
+#define ADC12B_CDR_DATA_Pos 0
+#define ADC12B_CDR_DATA_Msk (0xfffu << ADC12B_CDR_DATA_Pos) /**< \brief (ADC12B_CDR[8]) Converted Data */
+/* -------- ADC12B_ACR : (ADC12B Offset: 0x64) Analog Control Register -------- */
+#define ADC12B_ACR_GAIN_Pos 0
+#define ADC12B_ACR_GAIN_Msk (0x3u << ADC12B_ACR_GAIN_Pos) /**< \brief (ADC12B_ACR) Input Gain */
+#define ADC12B_ACR_GAIN(value) ((ADC12B_ACR_GAIN_Msk & ((value) << ADC12B_ACR_GAIN_Pos)))
+#define ADC12B_ACR_IBCTL_Pos 8
+#define ADC12B_ACR_IBCTL_Msk (0x3u << ADC12B_ACR_IBCTL_Pos) /**< \brief (ADC12B_ACR) Bias Current Control */
+#define ADC12B_ACR_IBCTL(value) ((ADC12B_ACR_IBCTL_Msk & ((value) << ADC12B_ACR_IBCTL_Pos)))
+#define ADC12B_ACR_DIFF (0x1u << 16) /**< \brief (ADC12B_ACR) Differential Mode */
+#define ADC12B_ACR_OFFSET (0x1u << 17) /**< \brief (ADC12B_ACR) Input OFFSET */
+/* -------- ADC12B_EMR : (ADC12B Offset: 0x68) Extended Mode Register -------- */
+#define ADC12B_EMR_OFFMODES (0x1u << 0) /**< \brief (ADC12B_EMR) Off Mode if Sleep Bit (ADC12B_MR) = 1 */
+#define ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos 16
+#define ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk (0xffu << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos) /**< \brief (ADC12B_EMR) Startup Time */
+#define ADC12B_EMR_OFF_MODE_STARTUP_TIME(value) ((ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk & ((value) << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos)))
+/* -------- ADC12B_RPR : (ADC12B Offset: 0x100) Receive Pointer Register -------- */
+#define ADC12B_RPR_RXPTR_Pos 0
+#define ADC12B_RPR_RXPTR_Msk (0xffffffffu << ADC12B_RPR_RXPTR_Pos) /**< \brief (ADC12B_RPR) Receive Pointer Register */
+#define ADC12B_RPR_RXPTR(value) ((ADC12B_RPR_RXPTR_Msk & ((value) << ADC12B_RPR_RXPTR_Pos)))
+/* -------- ADC12B_RCR : (ADC12B Offset: 0x104) Receive Counter Register -------- */
+#define ADC12B_RCR_RXCTR_Pos 0
+#define ADC12B_RCR_RXCTR_Msk (0xffffu << ADC12B_RCR_RXCTR_Pos) /**< \brief (ADC12B_RCR) Receive Counter Register */
+#define ADC12B_RCR_RXCTR(value) ((ADC12B_RCR_RXCTR_Msk & ((value) << ADC12B_RCR_RXCTR_Pos)))
+/* -------- ADC12B_RNPR : (ADC12B Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC12B_RNPR_RXNPTR_Pos 0
+#define ADC12B_RNPR_RXNPTR_Msk (0xffffffffu << ADC12B_RNPR_RXNPTR_Pos) /**< \brief (ADC12B_RNPR) Receive Next Pointer */
+#define ADC12B_RNPR_RXNPTR(value) ((ADC12B_RNPR_RXNPTR_Msk & ((value) << ADC12B_RNPR_RXNPTR_Pos)))
+/* -------- ADC12B_RNCR : (ADC12B Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC12B_RNCR_RXNCTR_Pos 0
+#define ADC12B_RNCR_RXNCTR_Msk (0xffffu << ADC12B_RNCR_RXNCTR_Pos) /**< \brief (ADC12B_RNCR) Receive Next Counter */
+#define ADC12B_RNCR_RXNCTR(value) ((ADC12B_RNCR_RXNCTR_Msk & ((value) << ADC12B_RNCR_RXNCTR_Pos)))
+/* -------- ADC12B_PTCR : (ADC12B Offset: 0x120) Transfer Control Register -------- */
+#define ADC12B_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC12B_PTCR) Receiver Transfer Enable */
+#define ADC12B_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC12B_PTCR) Receiver Transfer Disable */
+#define ADC12B_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC12B_PTCR) Transmitter Transfer Enable */
+#define ADC12B_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC12B_PTCR) Transmitter Transfer Disable */
+/* -------- ADC12B_PTSR : (ADC12B Offset: 0x124) Transfer Status Register -------- */
+#define ADC12B_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC12B_PTSR) Receiver Transfer Enable */
+#define ADC12B_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC12B_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_ADC12B_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_chipid.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_chipid.h
new file mode 100644
index 0000000..f155f22
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_chipid.h
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_CHIPID_COMPONENT_
+#define _SAM3U_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM3U_CHIPID Chip Identifier */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Chipid hardware registers */
+typedef struct {
+  RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+  RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define   CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define   CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define   CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define   CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define   CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define   CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define   CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define   CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define   CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define   CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define   CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define   CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
+#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAM3U_CHIPID_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_dmac.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_dmac.h
new file mode 100644
index 0000000..83998b5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_dmac.h
@@ -0,0 +1,313 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_DMAC_COMPONENT_
+#define _SAM3U_DMAC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_DMAC DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief DmacCh_num hardware registers */
+typedef struct {
+  RwReg       DMAC_SADDR;     /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */
+  RwReg       DMAC_DADDR;     /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */
+  RwReg       DMAC_DSCR;      /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */
+  RwReg       DMAC_CTRLA;     /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */
+  RwReg       DMAC_CTRLB;     /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */
+  RwReg       DMAC_CFG;       /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */
+  RoReg       Reserved1[4];
+} DmacCh_num;
+/** \brief Dmac hardware registers */
+#define DMACCH_NUM_NUMBER 4
+typedef struct {
+  RwReg       DMAC_GCFG;      /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */
+  RwReg       DMAC_EN;        /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */
+  RwReg       DMAC_SREQ;      /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */
+  RwReg       DMAC_CREQ;      /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */
+  RwReg       DMAC_LAST;      /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */
+  RoReg       Reserved1[1];
+  WoReg       DMAC_EBCIER;    /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+  WoReg       DMAC_EBCIDR;    /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+  RoReg       DMAC_EBCIMR;    /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+  RoReg       DMAC_EBCISR;    /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+  WoReg       DMAC_CHER;      /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */
+  WoReg       DMAC_CHDR;      /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */
+  RoReg       DMAC_CHSR;      /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */
+  RoReg       Reserved2[2];
+  DmacCh_num  DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 3 */
+  RoReg       Reserved3[66];
+  RwReg       DMAC_WPMR;      /**< \brief (Dmac Offset: 0x1E4) DMAC Write Protect Mode Register */
+  RoReg       DMAC_WPSR;      /**< \brief (Dmac Offset: 0x1E8) DMAC Write Protect Status Register */
+} Dmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */
+#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) Arbiter Configuration */
+#define   DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) /**< \brief (DMAC_GCFG) Fixed priority arbiter. */
+#define   DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) /**< \brief (DMAC_GCFG) Modified round robin arbiter. */
+/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */
+#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN)  */
+/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */
+#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) Destination Request */
+/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */
+#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */
+#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) Destination Last */
+/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */
+#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) Access Error [3:0] */
+#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) Access Error [3:0] */
+#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) Access Error [3:0] */
+#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) Access Error [3:0] */
+/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */
+#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */
+#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */
+#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */
+#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) Access Error [3:0] */
+/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */
+#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */
+#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */
+#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */
+#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) Access Error [3:0] */
+/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */
+#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [3:0] */
+#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) Access Error [3:0] */
+#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) Access Error [3:0] */
+#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) Access Error [3:0] */
+#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) Access Error [3:0] */
+/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */
+#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) Enable [3:0] */
+#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) Enable [3:0] */
+#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) Enable [3:0] */
+#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) Enable [3:0] */
+#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) Suspend [3:0] */
+#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) Suspend [3:0] */
+#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) Suspend [3:0] */
+#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) Suspend [3:0] */
+#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) Keep on [3:0] */
+#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) Keep on [3:0] */
+#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) Keep on [3:0] */
+#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) Keep on [3:0] */
+/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */
+#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) Disable [3:0] */
+#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) Disable [3:0] */
+#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) Disable [3:0] */
+#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) Disable [3:0] */
+#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) Resume [3:0] */
+#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) Resume [3:0] */
+#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) Resume [3:0] */
+#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) Resume [3:0] */
+/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */
+#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) Enable [3:0] */
+#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) Enable [3:0] */
+#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) Enable [3:0] */
+#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) Enable [3:0] */
+#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) Suspend [3:0] */
+#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) Suspend [3:0] */
+#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) Suspend [3:0] */
+#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) Suspend [3:0] */
+#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) Empty [3:0] */
+#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) Empty [3:0] */
+#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) Empty [3:0] */
+#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) Empty [3:0] */
+#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) Stalled [3:0] */
+#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) Stalled [3:0] */
+#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) Stalled [3:0] */
+#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) Stalled [3:0] */
+/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */
+#define DMAC_SADDR_SADDR_Pos 0
+#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) /**< \brief (DMAC_SADDR) Channel x Source Address */
+#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos)))
+/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */
+#define DMAC_DADDR_DADDR_Pos 0
+#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) /**< \brief (DMAC_DADDR) Channel x Destination Address */
+#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos)))
+/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */
+#define DMAC_DSCR_DSCR_Pos 2
+#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) /**< \brief (DMAC_DSCR) Buffer Transfer Descriptor Address */
+#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos)))
+/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */
+#define DMAC_CTRLA_BTSIZE_Pos 0
+#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) Buffer Transfer Size */
+#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))
+#define DMAC_CTRLA_SCSIZE_Pos 16
+#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA) Source Chunk Transfer Size. */
+#define   DMAC_CTRLA_SCSIZE_CHK_1 (0x0u << 16) /**< \brief (DMAC_CTRLA) 1 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_4 (0x1u << 16) /**< \brief (DMAC_CTRLA) 4 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_8 (0x2u << 16) /**< \brief (DMAC_CTRLA) 8 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_16 (0x3u << 16) /**< \brief (DMAC_CTRLA) 16 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_32 (0x4u << 16) /**< \brief (DMAC_CTRLA) 32 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_64 (0x5u << 16) /**< \brief (DMAC_CTRLA) 64 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_128 (0x6u << 16) /**< \brief (DMAC_CTRLA) 128 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_256 (0x7u << 16) /**< \brief (DMAC_CTRLA) 256 data transferred */
+#define DMAC_CTRLA_DCSIZE_Pos 20
+#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA) Destination Chunk Transfer Size */
+#define   DMAC_CTRLA_DCSIZE_CHK_1 (0x0u << 20) /**< \brief (DMAC_CTRLA) 1 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_4 (0x1u << 20) /**< \brief (DMAC_CTRLA) 4 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_8 (0x2u << 20) /**< \brief (DMAC_CTRLA) 8 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_16 (0x3u << 20) /**< \brief (DMAC_CTRLA) 16 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_32 (0x4u << 20) /**< \brief (DMAC_CTRLA) 32 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_64 (0x5u << 20) /**< \brief (DMAC_CTRLA) 64 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_128 (0x6u << 20) /**< \brief (DMAC_CTRLA) 128 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_256 (0x7u << 20) /**< \brief (DMAC_CTRLA) 256 data transferred */
+#define DMAC_CTRLA_SRC_WIDTH_Pos 24
+#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Source */
+#define   DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
+#define   DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
+#define   DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
+#define DMAC_CTRLA_DST_WIDTH_Pos 28
+#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Destination */
+#define   DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
+#define   DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
+#define   DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
+#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA)  */
+/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */
+#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) Source Address Descriptor */
+#define   DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) /**< \brief (DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory. */
+#define   DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source. */
+#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) Destination Address Descriptor */
+#define   DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) /**< \brief (DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory. */
+#define   DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination. */
+#define DMAC_CTRLB_FC_Pos 21
+#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) Flow Control */
+#define   DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller */
+#define   DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller */
+#define   DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller */
+#define   DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller */
+#define DMAC_CTRLB_SRC_INCR_Pos 24
+#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source */
+#define   DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) /**< \brief (DMAC_CTRLB) The source address is incremented */
+#define   DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) /**< \brief (DMAC_CTRLB) The source address is decremented */
+#define   DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) /**< \brief (DMAC_CTRLB) The source address remains unchanged */
+#define DMAC_CTRLB_DST_INCR_Pos 28
+#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination */
+#define   DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) /**< \brief (DMAC_CTRLB) The destination address is incremented */
+#define   DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) /**< \brief (DMAC_CTRLB) The destination address is decremented */
+#define   DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) /**< \brief (DMAC_CTRLB) The destination address remains unchanged */
+#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB)  */
+/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */
+#define DMAC_CFG_SRC_PER_Pos 0
+#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) Source with Peripheral identifier */
+#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))
+#define DMAC_CFG_DST_PER_Pos 4
+#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) Destination with Peripheral identifier */
+#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))
+#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Source */
+#define   DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
+#define   DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Destination */
+#define   DMAC_CFG_DST_H2SEL_SW (0x0u << 13) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
+#define   DMAC_CFG_DST_H2SEL_HW (0x1u << 13) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) Stop On Done */
+#define   DMAC_CFG_SOD_DISABLE (0x0u << 16) /**< \brief (DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. */
+#define   DMAC_CFG_SOD_ENABLE (0x1u << 16) /**< \brief (DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. */
+#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock */
+#define   DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is disabled */
+#define   DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is enabled */
+#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) Bus Lock */
+#define   DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) /**< \brief (DMAC_CFG) AHB Bus Locking capability is disabled. */
+#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) Master Interface Arbiter Lock */
+#define   DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer. */
+#define   DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer. */
+#define DMAC_CFG_AHB_PROT_Pos 24
+#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) AHB Protection */
+#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))
+#define DMAC_CFG_FIFOCFG_Pos 28
+#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) FIFO Configuration */
+#define   DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) /**< \brief (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface. */
+#define   DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) /**< \brief (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced. */
+#define   DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) /**< \brief (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced. */
+/* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */
+#define DMAC_WPMR_WPEN (0x1u << 0) /**< \brief (DMAC_WPMR) Write Protect Enable */
+#define DMAC_WPMR_WPKEY_Pos 8
+#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) /**< \brief (DMAC_WPMR) Write Protect KEY */
+#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos)))
+/* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */
+#define DMAC_WPSR_WPVS (0x1u << 0) /**< \brief (DMAC_WPSR) Write Protect Violation Status */
+#define DMAC_WPSR_WPVSRC_Pos 8
+#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) /**< \brief (DMAC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_DMAC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_efc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_efc.h
new file mode 100644
index 0000000..57e9e76
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_efc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_EFC_COMPONENT_
+#define _SAM3U_EFC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_EFC Embedded Flash Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Efc hardware registers */
+typedef struct {
+  RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+  WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+  RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+  RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+
+#endif /* _SAM3U_EFC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_gpbr.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_gpbr.h
new file mode 100644
index 0000000..be86161
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_gpbr.h
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_GPBR_COMPONENT_
+#define _SAM3U_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM3U_GPBR General Purpose Backup Register */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Gpbr hardware registers */
+typedef struct {
+  RwReg SYS_GPBR[4]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SYS_GPBR[4] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[4]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_GPBR_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_hsmci.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_hsmci.h
new file mode 100644
index 0000000..1cc26d7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_hsmci.h
@@ -0,0 +1,337 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_HSMCI_COMPONENT_
+#define _SAM3U_HSMCI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3U_HSMCI High Speed MultiMedia Card Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Hsmci hardware registers */
+typedef struct {
+  WoReg HSMCI_CR;        /**< \brief (Hsmci Offset: 0x00) Control Register */
+  RwReg HSMCI_MR;        /**< \brief (Hsmci Offset: 0x04) Mode Register */
+  RwReg HSMCI_DTOR;      /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
+  RwReg HSMCI_SDCR;      /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
+  RwReg HSMCI_ARGR;      /**< \brief (Hsmci Offset: 0x10) Argument Register */
+  WoReg HSMCI_CMDR;      /**< \brief (Hsmci Offset: 0x14) Command Register */
+  RwReg HSMCI_BLKR;      /**< \brief (Hsmci Offset: 0x18) Block Register */
+  RwReg HSMCI_CSTOR;     /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
+  RoReg HSMCI_RSPR[4];   /**< \brief (Hsmci Offset: 0x20) Response Register */
+  RoReg HSMCI_RDR;       /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
+  WoReg HSMCI_TDR;       /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
+  RoReg Reserved1[2];
+  RoReg HSMCI_SR;        /**< \brief (Hsmci Offset: 0x40) Status Register */
+  WoReg HSMCI_IER;       /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
+  WoReg HSMCI_IDR;       /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
+  RoReg HSMCI_IMR;       /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
+  RwReg HSMCI_DMA;       /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */
+  RwReg HSMCI_CFG;       /**< \brief (Hsmci Offset: 0x54) Configuration Register */
+  RoReg Reserved2[35];
+  RwReg HSMCI_WPMR;      /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
+  RoReg HSMCI_WPSR;      /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved3[69];
+  RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
+} Hsmci;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
+#define HSMCI_MR_CLKDIV_Pos 0
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
+#define HSMCI_MR_PWSDIV_Pos 8
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
+#define HSMCI_DTOR_DTOCYC_Pos 0
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
+#define HSMCI_DTOR_DTOMUL_Pos 4
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
+#define   HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
+#define   HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
+#define   HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
+#define   HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
+#define   HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
+#define   HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
+#define   HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
+#define   HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
+#define HSMCI_SDCR_SDCSEL_Pos 0
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
+#define   HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
+#define   HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCBUS_Pos 6
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
+#define   HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
+#define   HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
+#define   HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
+#define HSMCI_ARGR_ARG_Pos 0
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
+#define HSMCI_CMDR_CMDNB_Pos 0
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
+#define HSMCI_CMDR_RSPTYP_Pos 6
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
+#define   HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
+#define   HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
+#define   HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
+#define   HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
+#define HSMCI_CMDR_SPCMD_Pos 8
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
+#define   HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
+#define   HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
+#define   HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
+#define   HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
+#define   HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
+#define   HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
+#define   HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
+#define   HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
+#define   HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
+#define   HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
+#define HSMCI_CMDR_TRCMD_Pos 16
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
+#define   HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
+#define   HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
+#define   HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
+#define   HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
+#define   HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
+#define HSMCI_CMDR_TRTYP_Pos 19
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
+#define   HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
+#define   HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
+#define   HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
+#define   HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
+#define   HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
+#define HSMCI_CMDR_IOSPCMD_Pos 24
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
+#define   HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
+#define   HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
+#define   HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
+#define HSMCI_BLKR_BCNT_Pos 0
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
+#define   HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
+#define   HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define   HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BLKLEN_Pos 16
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
+#define HSMCI_CSTOR_CSTOCYC_Pos 0
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
+#define HSMCI_CSTOR_CSTOMUL_Pos 4
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
+#define   HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
+#define   HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
+#define   HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
+#define   HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
+#define   HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
+#define   HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
+#define   HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
+#define   HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
+#define HSMCI_RSPR_RSP_Pos 0
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
+#define HSMCI_RDR_DATA_Pos 0
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
+#define HSMCI_TDR_DATA_Pos 0
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
+#define HSMCI_SR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR)  */
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
+#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */
+#define HSMCI_SR_DMADONE (0x1u << 25) /**< \brief (HSMCI_SR) DMA Transfer done */
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
+#define HSMCI_IER_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER)  */
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
+#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */
+#define HSMCI_IER_DMADONE (0x1u << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
+#define HSMCI_IDR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR)  */
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
+#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */
+#define HSMCI_IDR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
+#define HSMCI_IMR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR)  */
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
+#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */
+#define HSMCI_IMR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
+/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
+#define HSMCI_DMA_OFFSET_Pos 0
+#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */
+#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos)))
+#define HSMCI_DMA_CHKSIZE (0x1u << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */
+#define   HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */
+#define   HSMCI_DMA_CHKSIZE_4 (0x1u << 4) /**< \brief (HSMCI_DMA) 4 data available */
+#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */
+#define HSMCI_DMA_ROPT (0x1u << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
+#define HSMCI_WPMR_WP_KEY_Pos 8
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
+#define HSMCI_WPSR_WP_VS_Pos 0
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
+#define   HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
+#define   HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
+#define   HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
+#define   HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
+#define HSMCI_WPSR_WP_VSRC_Pos 8
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
+/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
+#define HSMCI_FIFO_DATA_Pos 0
+#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */
+#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_HSMCI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_matrix.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_matrix.h
new file mode 100644
index 0000000..4e74f21
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_matrix.h
@@ -0,0 +1,269 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_MATRIX_COMPONENT_
+#define _SAM3U_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM3U_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Matrix hardware registers */
+typedef struct {
+  RwReg MATRIX_MCFG[5];  /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+  RoReg Reserved1[11];
+  RwReg MATRIX_SCFG[10]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+  RoReg Reserved2[6];
+  RwReg MATRIX_PRAS0;    /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+  RoReg Reserved3[1];
+  RwReg MATRIX_PRAS1;    /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+  RoReg Reserved4[1];
+  RwReg MATRIX_PRAS2;    /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+  RoReg Reserved5[1];
+  RwReg MATRIX_PRAS3;    /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+  RoReg Reserved6[1];
+  RwReg MATRIX_PRAS4;    /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
+  RoReg Reserved7[1];
+  RwReg MATRIX_PRAS5;    /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */
+  RoReg Reserved8[1];
+  RwReg MATRIX_PRAS6;    /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */
+  RoReg Reserved9[1];
+  RwReg MATRIX_PRAS7;    /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */
+  RoReg Reserved10[1];
+  RwReg MATRIX_PRAS8;    /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */
+  RoReg Reserved11[1];
+  RwReg MATRIX_PRAS9;    /**< \brief (Matrix Offset: 0x00C8) Priority Register A for Slave 9 */
+  RoReg Reserved12[1];
+  RoReg Reserved13[12];
+  RwReg MATRIX_MRCR;     /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */
+  RoReg Reserved14[56];
+  RwReg MATRIX_WPMR;     /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+  RoReg MATRIX_WPSR;     /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- MATRIX_MCFG[5] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[5]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[10] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[10]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[10]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[10]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[10]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+#define MATRIX_PRAS0_M4PR_Pos 16
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+#define MATRIX_PRAS1_M4PR_Pos 16
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+#define MATRIX_PRAS2_M4PR_Pos 16
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+#define MATRIX_PRAS3_M4PR_Pos 16
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
+#define MATRIX_PRAS4_M0PR_Pos 0
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
+#define MATRIX_PRAS4_M1PR_Pos 4
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
+#define MATRIX_PRAS4_M2PR_Pos 8
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
+#define MATRIX_PRAS4_M3PR_Pos 12
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
+#define MATRIX_PRAS4_M4PR_Pos 16
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
+/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
+#define MATRIX_PRAS5_M0PR_Pos 0
+#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */
+#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))
+#define MATRIX_PRAS5_M1PR_Pos 4
+#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */
+#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))
+#define MATRIX_PRAS5_M2PR_Pos 8
+#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */
+#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))
+#define MATRIX_PRAS5_M3PR_Pos 12
+#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */
+#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))
+#define MATRIX_PRAS5_M4PR_Pos 16
+#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */
+#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))
+/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
+#define MATRIX_PRAS6_M0PR_Pos 0
+#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */
+#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))
+#define MATRIX_PRAS6_M1PR_Pos 4
+#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */
+#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))
+#define MATRIX_PRAS6_M2PR_Pos 8
+#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */
+#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))
+#define MATRIX_PRAS6_M3PR_Pos 12
+#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */
+#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))
+#define MATRIX_PRAS6_M4PR_Pos 16
+#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */
+#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))
+/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
+#define MATRIX_PRAS7_M0PR_Pos 0
+#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */
+#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))
+#define MATRIX_PRAS7_M1PR_Pos 4
+#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */
+#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))
+#define MATRIX_PRAS7_M2PR_Pos 8
+#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */
+#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))
+#define MATRIX_PRAS7_M3PR_Pos 12
+#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */
+#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))
+#define MATRIX_PRAS7_M4PR_Pos 16
+#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */
+#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))
+/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
+#define MATRIX_PRAS8_M0PR_Pos 0
+#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */
+#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))
+#define MATRIX_PRAS8_M1PR_Pos 4
+#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */
+#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))
+#define MATRIX_PRAS8_M2PR_Pos 8
+#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */
+#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))
+#define MATRIX_PRAS8_M3PR_Pos 12
+#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */
+#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))
+#define MATRIX_PRAS8_M4PR_Pos 16
+#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */
+#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))
+/* -------- MATRIX_PRAS9 : (MATRIX Offset: 0x00C8) Priority Register A for Slave 9 -------- */
+#define MATRIX_PRAS9_M0PR_Pos 0
+#define MATRIX_PRAS9_M0PR_Msk (0x3u << MATRIX_PRAS9_M0PR_Pos) /**< \brief (MATRIX_PRAS9) Master 0 Priority */
+#define MATRIX_PRAS9_M0PR(value) ((MATRIX_PRAS9_M0PR_Msk & ((value) << MATRIX_PRAS9_M0PR_Pos)))
+#define MATRIX_PRAS9_M1PR_Pos 4
+#define MATRIX_PRAS9_M1PR_Msk (0x3u << MATRIX_PRAS9_M1PR_Pos) /**< \brief (MATRIX_PRAS9) Master 1 Priority */
+#define MATRIX_PRAS9_M1PR(value) ((MATRIX_PRAS9_M1PR_Msk & ((value) << MATRIX_PRAS9_M1PR_Pos)))
+#define MATRIX_PRAS9_M2PR_Pos 8
+#define MATRIX_PRAS9_M2PR_Msk (0x3u << MATRIX_PRAS9_M2PR_Pos) /**< \brief (MATRIX_PRAS9) Master 2 Priority */
+#define MATRIX_PRAS9_M2PR(value) ((MATRIX_PRAS9_M2PR_Msk & ((value) << MATRIX_PRAS9_M2PR_Pos)))
+#define MATRIX_PRAS9_M3PR_Pos 12
+#define MATRIX_PRAS9_M3PR_Msk (0x3u << MATRIX_PRAS9_M3PR_Pos) /**< \brief (MATRIX_PRAS9) Master 3 Priority */
+#define MATRIX_PRAS9_M3PR(value) ((MATRIX_PRAS9_M3PR_Msk & ((value) << MATRIX_PRAS9_M3PR_Pos)))
+#define MATRIX_PRAS9_M4PR_Pos 16
+#define MATRIX_PRAS9_M4PR_Msk (0x3u << MATRIX_PRAS9_M4PR_Pos) /**< \brief (MATRIX_PRAS9) Master 4 Priority */
+#define MATRIX_PRAS9_M4PR(value) ((MATRIX_PRAS9_M4PR_Msk & ((value) << MATRIX_PRAS9_M4PR_Pos)))
+/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
+#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */
+#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */
+#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */
+#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */
+#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_MATRIX_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_pdc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_pdc.h
new file mode 100644
index 0000000..86883c1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_pdc.h
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PDC_COMPONENT_
+#define _SAM3U_PDC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_PDC Peripheral DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pdc hardware registers */
+typedef struct {
+  RwReg PERIPH_RPR;  /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
+  RwReg PERIPH_RCR;  /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
+  RwReg PERIPH_TPR;  /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
+  RwReg PERIPH_TCR;  /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
+  RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+  RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+  RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+  RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+  WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+  RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_PDC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_pio.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_pio.h
new file mode 100644
index 0000000..01a51fd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_pio.h
@@ -0,0 +1,1435 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PIO_COMPONENT_
+#define _SAM3U_PIO_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pio hardware registers */
+typedef struct {
+  WoReg PIO_PER;       /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+  WoReg PIO_PDR;       /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+  RoReg PIO_PSR;       /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+  RoReg Reserved1[1];
+  WoReg PIO_OER;       /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+  WoReg PIO_ODR;       /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+  RoReg PIO_OSR;       /**< \brief (Pio Offset: 0x0018) Output Status Register */
+  RoReg Reserved2[1];
+  WoReg PIO_IFER;      /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+  WoReg PIO_IFDR;      /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+  RoReg PIO_IFSR;      /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+  RoReg Reserved3[1];
+  WoReg PIO_SODR;      /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+  WoReg PIO_CODR;      /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+  RwReg PIO_ODSR;      /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+  RoReg PIO_PDSR;      /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+  WoReg PIO_IER;       /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+  WoReg PIO_IDR;       /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+  RoReg PIO_IMR;       /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+  RoReg PIO_ISR;       /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+  WoReg PIO_MDER;      /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+  WoReg PIO_MDDR;      /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+  RoReg PIO_MDSR;      /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+  RoReg Reserved4[1];
+  WoReg PIO_PUDR;      /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+  WoReg PIO_PUER;      /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+  RoReg PIO_PUSR;      /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+  RoReg Reserved5[1];
+  RwReg PIO_ABSR;      /**< \brief (Pio Offset: 0x0070) Peripheral AB Select Register */
+  RoReg Reserved6[3];
+  WoReg PIO_SCIFSR;    /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */
+  WoReg PIO_DIFSR;     /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */
+  RoReg PIO_IFDGSR;    /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */
+  RwReg PIO_SCDR;      /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+  RoReg Reserved7[4];
+  WoReg PIO_OWER;      /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+  WoReg PIO_OWDR;      /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+  RoReg PIO_OWSR;      /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+  RoReg Reserved8[1];
+  WoReg PIO_AIMER;     /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+  WoReg PIO_AIMDR;     /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
+  RoReg PIO_AIMMR;     /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+  RoReg Reserved9[1];
+  WoReg PIO_ESR;       /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+  WoReg PIO_LSR;       /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+  RoReg PIO_ELSR;      /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+  RoReg Reserved10[1];
+  WoReg PIO_FELLSR;    /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
+  WoReg PIO_REHLSR;    /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
+  RoReg PIO_FRLHSR;    /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+  RoReg Reserved11[1];
+  RoReg PIO_LOCKSR;    /**< \brief (Pio Offset: 0x00E0) Lock Status */
+  RwReg PIO_WPMR;      /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PIO_WPSR;      /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
+} Pio;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
+/* -------- PIO_ABSR : (PIO Offset: 0x0070) Peripheral AB Select Register -------- */
+#define PIO_ABSR_P0 (0x1u << 0) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P1 (0x1u << 1) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P2 (0x1u << 2) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P3 (0x1u << 3) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P4 (0x1u << 4) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P5 (0x1u << 5) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P6 (0x1u << 6) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P7 (0x1u << 7) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P8 (0x1u << 8) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P9 (0x1u << 9) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P10 (0x1u << 10) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P11 (0x1u << 11) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P12 (0x1u << 12) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P13 (0x1u << 13) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P14 (0x1u << 14) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P15 (0x1u << 15) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P16 (0x1u << 16) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P17 (0x1u << 17) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P18 (0x1u << 18) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P19 (0x1u << 19) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P20 (0x1u << 20) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P21 (0x1u << 21) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P22 (0x1u << 22) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P23 (0x1u << 23) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P24 (0x1u << 24) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P25 (0x1u << 25) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P26 (0x1u << 26) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P27 (0x1u << 27) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P28 (0x1u << 28) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P29 (0x1u << 29) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P30 (0x1u << 30) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P31 (0x1u << 31) /**< \brief (PIO_ABSR) Peripheral A Select. */
+/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */
+#define PIO_SCIFSR_P0 (0x1u << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P1 (0x1u << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P2 (0x1u << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P3 (0x1u << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P4 (0x1u << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P5 (0x1u << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P6 (0x1u << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P7 (0x1u << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P8 (0x1u << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P9 (0x1u << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P10 (0x1u << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P11 (0x1u << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P12 (0x1u << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P13 (0x1u << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P14 (0x1u << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P15 (0x1u << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P16 (0x1u << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P17 (0x1u << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P18 (0x1u << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P19 (0x1u << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P20 (0x1u << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P21 (0x1u << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P22 (0x1u << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P23 (0x1u << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P24 (0x1u << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P25 (0x1u << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P26 (0x1u << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P27 (0x1u << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P28 (0x1u << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P29 (0x1u << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P30 (0x1u << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P31 (0x1u << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */
+#define PIO_DIFSR_P0 (0x1u << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P1 (0x1u << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P2 (0x1u << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P3 (0x1u << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P4 (0x1u << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P5 (0x1u << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P6 (0x1u << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P7 (0x1u << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P8 (0x1u << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P9 (0x1u << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P10 (0x1u << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P11 (0x1u << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P12 (0x1u << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P13 (0x1u << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P14 (0x1u << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P15 (0x1u << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P16 (0x1u << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P17 (0x1u << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P18 (0x1u << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P19 (0x1u << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P20 (0x1u << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P21 (0x1u << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P22 (0x1u << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P23 (0x1u << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P24 (0x1u << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P25 (0x1u << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P26 (0x1u << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P27 (0x1u << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P28 (0x1u << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P29 (0x1u << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P30 (0x1u << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P31 (0x1u << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */
+#define PIO_IFDGSR_P0 (0x1u << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P1 (0x1u << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P2 (0x1u << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P3 (0x1u << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P4 (0x1u << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P5 (0x1u << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P6 (0x1u << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P7 (0x1u << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P8 (0x1u << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P9 (0x1u << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P10 (0x1u << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P11 (0x1u << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P12 (0x1u << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P13 (0x1u << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P14 (0x1u << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P15 (0x1u << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P16 (0x1u << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P17 (0x1u << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P18 (0x1u << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P19 (0x1u << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P20 (0x1u << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P21 (0x1u << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P22 (0x1u << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P23 (0x1u << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P24 (0x1u << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P25 (0x1u << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P26 (0x1u << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P27 (0x1u << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P28 (0x1u << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P29 (0x1u << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P30 (0x1u << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P31 (0x1u << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_PIO_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_pmc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_pmc.h
new file mode 100644
index 0000000..ab5dfb8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_pmc.h
@@ -0,0 +1,339 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PMC_COMPONENT_
+#define _SAM3U_PMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_PMC Power Management Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pmc hardware registers */
+typedef struct {
+  WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+  WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+  RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+  RoReg Reserved1[1];
+  WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+  WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+  RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+  RwReg CKGR_UCKR;     /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */
+  RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+  RoReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+  RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+  RoReg Reserved2[1];
+  RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+  RoReg Reserved3[3];
+  RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+  RoReg Reserved4[5];
+  WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+  WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+  RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
+  RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+  RwReg PMC_FSMR;      /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+  RwReg PMC_FSPR;      /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+  WoReg PMC_FOCR;      /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+  RoReg Reserved5[26];
+  RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+} Pmc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
+#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */
+#define CKGR_UCKR_UPLLCOUNT_Pos 20
+#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */
+#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define   PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLLClock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define   PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL Clock is selected */
+#define   PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define   PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define   PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define   PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define   PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define   PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define   PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define   PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_PMC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_pwm.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_pwm.h
new file mode 100644
index 0000000..81a02f2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_pwm.h
@@ -0,0 +1,538 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PWM_COMPONENT_
+#define _SAM3U_PWM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+  RwReg      PWM_CMR;       /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+  RwReg      PWM_CDTY;      /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+  RwReg      PWM_CDTYUPD;   /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
+  RwReg      PWM_CPRD;      /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
+  RwReg      PWM_CPRDUPD;   /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
+  RwReg      PWM_CCNT;      /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
+  RwReg      PWM_DT;        /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
+  RwReg      PWM_DTUPD;     /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
+} PwmCh_num;
+/** \brief PwmCmp hardware registers */
+typedef struct {
+  RwReg      PWM_CMPV;      /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
+  RwReg      PWM_CMPVUPD;   /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
+  RwReg      PWM_CMPM;      /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
+  RwReg      PWM_CMPMUPD;   /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
+} PwmCmp;
+/** \brief Pwm hardware registers */
+#define PWMCMP_NUMBER 8
+#define PWMCH_NUM_NUMBER 4
+typedef struct {
+  RwReg      PWM_CLK;       /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
+  WoReg      PWM_ENA;       /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+  WoReg      PWM_DIS;       /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+  RoReg      PWM_SR;        /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+  WoReg      PWM_IER1;      /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
+  WoReg      PWM_IDR1;      /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
+  RoReg      PWM_IMR1;      /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
+  RoReg      PWM_ISR1;      /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
+  RwReg      PWM_SCM;       /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      PWM_SCUC;      /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
+  RwReg      PWM_SCUP;      /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
+  WoReg      PWM_SCUPUPD;   /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
+  WoReg      PWM_IER2;      /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
+  WoReg      PWM_IDR2;      /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
+  RoReg      PWM_IMR2;      /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
+  RoReg      PWM_ISR2;      /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
+  RwReg      PWM_OOV;       /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
+  RwReg      PWM_OS;        /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
+  WoReg      PWM_OSS;       /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
+  WoReg      PWM_OSC;       /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
+  WoReg      PWM_OSSUPD;    /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
+  WoReg      PWM_OSCUPD;    /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
+  RwReg      PWM_FMR;       /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
+  RoReg      PWM_FSR;       /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
+  WoReg      PWM_FCR;       /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
+  RwReg      PWM_FPV;       /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
+  RwReg      PWM_FPE;       /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
+  RoReg      Reserved2[3];
+  RwReg      PWM_ELMR[2];   /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
+  RoReg      Reserved3[24];
+  WoReg      PWM_WPCR;      /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
+  RoReg      PWM_WPSR;      /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
+  RoReg      Reserved4[7];
+  RwReg      PWM_TPR;       /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
+  RwReg      PWM_TCR;       /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
+  RoReg      Reserved5[2];
+  RwReg      PWM_TNPR;      /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
+  RwReg      PWM_TNCR;      /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
+  WoReg      PWM_PTCR;      /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
+  RoReg      PWM_PTSR;      /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
+  RoReg      Reserved6[2];
+  PwmCmp     PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
+  RoReg      Reserved7[20];
+  PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
+} Pwm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
+#define PWM_CLK_DIVA_Pos 0
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
+#define PWM_CLK_PREA_Pos 8
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
+#define PWM_CLK_DIVB_Pos 16
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
+#define PWM_CLK_PREB_Pos 24
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
+#define PWM_SCM_UPDM_Pos 16
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
+#define   PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
+#define PWM_SCM_PTRCS_Pos 21
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
+#define PWM_SCUP_UPR_Pos 0
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
+#define PWM_SCUP_UPRCNT_Pos 4
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
+#define PWM_SCUPUPD_UPRUPD_Pos 0
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
+#define PWM_FMR_FPOL_Pos 0
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 3) */
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
+#define PWM_FMR_FMOD_Pos 8
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 3) */
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
+#define PWM_FMR_FFIL_Pos 16
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 3) */
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
+#define PWM_FSR_FIV_Pos 0
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 3) */
+#define PWM_FSR_FS_Pos 8
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 3) */
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
+#define PWM_FCR_FCLR_Pos 0
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 3) */
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
+#define PWM_FPE_FPE0_Pos 0
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 3) */
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
+#define PWM_FPE_FPE1_Pos 8
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 3) */
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
+#define PWM_FPE_FPE2_Pos 16
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 3) */
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
+#define PWM_FPE_FPE3_Pos 24
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 3) */
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
+#define PWM_WPCR_WPCMD_Pos 0
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
+#define PWM_WPCR_WPKEY_Pos 8
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPVSRC_Pos 16
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
+#define PWM_TPR_TXPTR_Pos 0
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
+#define PWM_TCR_TXCTR_Pos 0
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
+#define PWM_TNPR_TXNPTR_Pos 0
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
+#define PWM_TNCR_TXNCTR_Pos 0
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
+#define PWM_CMPV_CV_Pos 0
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
+#define PWM_CMPVUPD_CVUPD_Pos 0
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
+#define PWM_CMPM_CTR_Pos 4
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
+#define PWM_CMPM_CPR_Pos 8
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
+#define PWM_CMPM_CPRCNT_Pos 12
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
+#define PWM_CMPM_CUPR_Pos 16
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
+#define PWM_CMPM_CUPRCNT_Pos 20
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
+#define PWM_CMPMUPD_CTRUPD_Pos 4
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
+#define PWM_CMPMUPD_CPRUPD_Pos 8
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
+#define PWM_CMPMUPD_CUPRUPD_Pos 16
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
+#define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
+#define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
+#define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
+#define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
+#define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
+#define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
+#define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
+#define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
+#define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
+#define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
+#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
+#define PWM_CDTYUPD_CDTYUPD_Pos 0
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
+#define PWM_CPRDUPD_CPRDUPD_Pos 0
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
+#define PWM_DT_DTH_Pos 0
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
+#define PWM_DT_DTL_Pos 16
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
+#define PWM_DTUPD_DTHUPD_Pos 0
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
+#define PWM_DTUPD_DTLUPD_Pos 16
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_PWM_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_rstc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_rstc.h
new file mode 100644
index 0000000..15547d9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_rstc.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_RSTC_COMPONENT_
+#define _SAM3U_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_RSTC Reset Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rstc hardware registers */
+typedef struct {
+  WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+  RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+  RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_RSTC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_rtc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_rtc.h
new file mode 100644
index 0000000..02a8759
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_rtc.h
@@ -0,0 +1,168 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_RTC_COMPONENT_
+#define _SAM3U_RTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM3U_RTC Real-time Clock */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtc hardware registers */
+typedef struct {
+  RwReg RTC_CR;        /**< \brief (Rtc Offset: 0x00) Control Register */
+  RwReg RTC_MR;        /**< \brief (Rtc Offset: 0x04) Mode Register */
+  RwReg RTC_TIMR;      /**< \brief (Rtc Offset: 0x08) Time Register */
+  RwReg RTC_CALR;      /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+  RwReg RTC_TIMALR;    /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+  RwReg RTC_CALALR;    /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+  RoReg RTC_SR;        /**< \brief (Rtc Offset: 0x18) Status Register */
+  WoReg RTC_SCCR;      /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+  WoReg RTC_IER;       /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+  WoReg RTC_IDR;       /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+  RoReg RTC_IMR;       /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+  RoReg RTC_VER;       /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+  RoReg Reserved1[45];
+  RwReg RTC_WPMR;      /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */
+#define RTC_WPMR_WPKEY_Pos 8
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR)  */
+#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_RTC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_rtt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_rtt.h
new file mode 100644
index 0000000..ef55518
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_rtt.h
@@ -0,0 +1,69 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_RTT_COMPONENT_
+#define _SAM3U_RTT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3U_RTT Real-time Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtt hardware registers */
+typedef struct {
+  RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+  RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+  RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+  RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+
+#endif /* _SAM3U_RTT_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_smc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_smc.h
new file mode 100644
index 0000000..dbcf9a4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_smc.h
@@ -0,0 +1,485 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SMC_COMPONENT_
+#define _SAM3U_SMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Static Memory Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_SMC Static Memory Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief SmcCs_number hardware registers */
+typedef struct {
+  RwReg         SMC_SETUP;        /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
+  RwReg         SMC_PULSE;        /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
+  RwReg         SMC_CYCLE;        /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
+  RwReg         SMC_TIMINGS;      /**< \brief (SmcCs_number Offset: 0xC) SMC Timings Register */
+  RwReg         SMC_MODE;         /**< \brief (SmcCs_number Offset: 0x10) SMC Mode Register */
+} SmcCs_number;
+/** \brief Smc hardware registers */
+#define SMCCS_NUMBER_NUMBER 4
+typedef struct {
+  RwReg         SMC_CFG;          /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */
+  WoReg         SMC_CTRL;         /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */
+  RoReg         SMC_SR;           /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */
+  WoReg         SMC_IER;          /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */
+  WoReg         SMC_IDR;          /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */
+  RoReg         SMC_IMR;          /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */
+  RwReg         SMC_ADDR;         /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */
+  RwReg         SMC_BANK;         /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */
+  WoReg         SMC_ECC_CTRL;     /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */
+  RwReg         SMC_ECC_MD;       /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */
+  RoReg         SMC_ECC_SR1;      /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */
+  RoReg         SMC_ECC_PR0;      /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */
+  RoReg         SMC_ECC_PR1;      /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */
+  RoReg         SMC_ECC_SR2;      /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */
+  RoReg         SMC_ECC_PR2;      /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */
+  RoReg         SMC_ECC_PR3;      /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */
+  RoReg         SMC_ECC_PR4;      /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */
+  RoReg         SMC_ECC_PR5;      /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */
+  RoReg         SMC_ECC_PR6;      /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */
+  RoReg         SMC_ECC_PR7;      /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */
+  RoReg         SMC_ECC_PR8;      /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */
+  RoReg         SMC_ECC_PR9;      /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */
+  RoReg         SMC_ECC_PR10;     /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */
+  RoReg         SMC_ECC_PR11;     /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */
+  RoReg         SMC_ECC_PR12;     /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */
+  RoReg         SMC_ECC_PR13;     /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */
+  RoReg         SMC_ECC_PR14;     /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */
+  RoReg         SMC_ECC_PR15;     /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */
+  SmcCs_number  SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 3 */
+  RoReg         Reserved1[20];
+  RwReg         SMC_OCMS;         /**< \brief (Smc Offset: 0x110) SMC OCMS Register */
+  WoReg         SMC_KEY1;         /**< \brief (Smc Offset: 0x114) SMC OCMS KEY1 Register */
+  WoReg         SMC_KEY2;         /**< \brief (Smc Offset: 0x118) SMC OCMS KEY2 Register */
+  RoReg         Reserved2[50];
+  WoReg         SMC_WPCR;         /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */
+  RoReg         SMC_WPSR;         /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */
+} Smc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */
+#define SMC_CFG_PAGESIZE_Pos 0
+#define SMC_CFG_PAGESIZE_Msk (0x3u << SMC_CFG_PAGESIZE_Pos) /**< \brief (SMC_CFG)  */
+#define   SMC_CFG_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_CFG) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define   SMC_CFG_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_CFG) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define   SMC_CFG_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_CFG) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define   SMC_CFG_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_CFG) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_CFG_WSPARE (0x1u << 8) /**< \brief (SMC_CFG) Write Spare Area */
+#define SMC_CFG_RSPARE (0x1u << 9) /**< \brief (SMC_CFG) Read Spare Area */
+#define SMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */
+#define SMC_CFG_RBEDGE (0x1u << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */
+#define SMC_CFG_DTOCYC_Pos 16
+#define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) /**< \brief (SMC_CFG) Data Timeout Cycle Number */
+#define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos)))
+#define SMC_CFG_DTOMUL_Pos 20
+#define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) /**< \brief (SMC_CFG) Data Timeout Multiplier */
+#define   SMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (SMC_CFG) DTOCYC */
+#define   SMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (SMC_CFG) DTOCYC x 16 */
+#define   SMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (SMC_CFG) DTOCYC x 128 */
+#define   SMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (SMC_CFG) DTOCYC x 256 */
+#define   SMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (SMC_CFG) DTOCYC x 1024 */
+#define   SMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (SMC_CFG) DTOCYC x 4096 */
+#define   SMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (SMC_CFG) DTOCYC x 65536 */
+#define   SMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (SMC_CFG) DTOCYC x 1048576 */
+/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */
+#define SMC_CTRL_NFCEN (0x1u << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */
+#define SMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */
+/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */
+#define SMC_SR_SMCSTS (0x1u << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */
+#define SMC_SR_RB_RISE (0x1u << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */
+#define SMC_SR_RB_FALL (0x1u << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */
+#define SMC_SR_NFCBUSY (0x1u << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */
+#define SMC_SR_NFCWR (0x1u << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */
+#define SMC_SR_NFCSID_Pos 12
+#define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */
+#define SMC_SR_XFRDONE (0x1u << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */
+#define SMC_SR_CMDDONE (0x1u << 17) /**< \brief (SMC_SR) Command Done */
+#define SMC_SR_DTOE (0x1u << 20) /**< \brief (SMC_SR) Data Timeout Error */
+#define SMC_SR_UNDEF (0x1u << 21) /**< \brief (SMC_SR) Undefined Area Error */
+#define SMC_SR_AWB (0x1u << 22) /**< \brief (SMC_SR) Accessing While Busy */
+#define SMC_SR_NFCASE (0x1u << 23) /**< \brief (SMC_SR) NFC Access Size Error */
+#define SMC_SR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */
+/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */
+#define SMC_IER_RB_RISE (0x1u << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */
+#define SMC_IER_RB_FALL (0x1u << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */
+#define SMC_IER_XFRDONE (0x1u << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */
+#define SMC_IER_CMDDONE (0x1u << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */
+#define SMC_IER_DTOE (0x1u << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */
+#define SMC_IER_UNDEF (0x1u << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */
+#define SMC_IER_AWB (0x1u << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */
+#define SMC_IER_NFCASE (0x1u << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */
+#define SMC_IER_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */
+/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */
+#define SMC_IDR_RB_RISE (0x1u << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */
+#define SMC_IDR_RB_FALL (0x1u << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */
+#define SMC_IDR_XFRDONE (0x1u << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */
+#define SMC_IDR_CMDDONE (0x1u << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */
+#define SMC_IDR_DTOE (0x1u << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */
+#define SMC_IDR_UNDEF (0x1u << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */
+#define SMC_IDR_AWB (0x1u << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */
+#define SMC_IDR_NFCASE (0x1u << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */
+#define SMC_IDR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */
+/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */
+#define SMC_IMR_RB_RISE (0x1u << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */
+#define SMC_IMR_RB_FALL (0x1u << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */
+#define SMC_IMR_XFRDONE (0x1u << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */
+#define SMC_IMR_CMDDONE (0x1u << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */
+#define SMC_IMR_DTOE (0x1u << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */
+#define SMC_IMR_UNDEF (0x1u << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */
+#define SMC_IMR_AWB (0x1u << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */
+#define SMC_IMR_NFCASE (0x1u << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */
+#define SMC_IMR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */
+/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */
+#define SMC_ADDR_ADDR_CYCLE0_Pos 0
+#define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */
+#define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos)))
+/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */
+#define SMC_BANK_BANK_Pos 0
+#define SMC_BANK_BANK_Msk (0x7u << SMC_BANK_BANK_Pos) /**< \brief (SMC_BANK) Bank Identifier */
+#define SMC_BANK_BANK(value) ((SMC_BANK_BANK_Msk & ((value) << SMC_BANK_BANK_Pos)))
+/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */
+#define SMC_ECC_CTRL_RST (0x1u << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */
+#define SMC_ECC_CTRL_SWRST (0x1u << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */
+/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */
+#define SMC_ECC_MD_ECC_PAGESIZE_Pos 0
+#define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) /**< \brief (SMC_ECC_MD) ECC Page Size */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_ECC_MD) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_ECC_MD) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_ECC_MD) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_ECC_MD) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_ECC_MD_TYPCORREC_Pos 4
+#define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) /**< \brief (SMC_ECC_MD) Type of Correction */
+#define   SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for a page of 512/1024/2048/4096 Bytes  (for 8 or 16-bit NAND Flash) */
+#define   SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+#define   SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */
+#define SMC_ECC_SR1_RECERR0 (0x1u << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */
+#define SMC_ECC_SR1_ECCERR0_Pos 1
+#define SMC_ECC_SR1_ECCERR0_Msk (0x3u << SMC_ECC_SR1_ECCERR0_Pos) /**< \brief (SMC_ECC_SR1) ECC Error */
+#define SMC_ECC_SR1_RECERR1 (0x1u << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_ECCERR1 (0x1u << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_MULERR1 (0x1u << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_RECERR2 (0x1u << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_ECCERR2 (0x1u << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_MULERR2 (0x1u << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_RECERR3 (0x1u << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_ECCERR3 (0x1u << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_MULERR3 (0x1u << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_RECERR4 (0x1u << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_ECCERR4_Pos 17
+#define SMC_ECC_SR1_ECCERR4_Msk (0x3u << SMC_ECC_SR1_ECCERR4_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_RECERR5 (0x1u << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_ECCERR5_Pos 21
+#define SMC_ECC_SR1_ECCERR5_Msk (0x3u << SMC_ECC_SR1_ECCERR5_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_RECERR6 (0x1u << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_ECCERR6_Pos 25
+#define SMC_ECC_SR1_ECCERR6_Msk (0x3u << SMC_ECC_SR1_ECCERR6_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_RECERR7 (0x1u << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+#define SMC_ECC_SR1_ECCERR7_Pos 29
+#define SMC_ECC_SR1_ECCERR7_Msk (0x3u << SMC_ECC_SR1_ECCERR7_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */
+#define SMC_ECC_PR0_BITADDR_Pos 0
+#define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) /**< \brief (SMC_ECC_PR0) Bit Address */
+#define SMC_ECC_PR0_WORDADDR_Pos 4
+#define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) /**< \brief (SMC_ECC_PR0) Word Address */
+#define SMC_ECC_PR0_BITADDR_W9BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W9BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Msk (0x1ffu << SMC_ECC_PR0_WORDADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_Pos 12
+#define SMC_ECC_PR0_NPARITY_Msk (0xfffu << SMC_ECC_PR0_NPARITY_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+#define SMC_ECC_PR0_BITADDR_W8BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W8BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR0_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR0_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR0_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */
+#define SMC_ECC_PR1_NPARITY_Pos 0
+#define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_BITADDR_Pos 0
+#define SMC_ECC_PR1_BITADDR_Msk (0x7u << SMC_ECC_PR1_BITADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_WORDADDR_Pos 3
+#define SMC_ECC_PR1_WORDADDR_Msk (0x1ffu << SMC_ECC_PR1_WORDADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W9BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W9BIT_Msk (0xfffu << SMC_ECC_PR1_NPARITY_W9BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR1_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR1_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */
+#define SMC_ECC_SR2_RECERR8 (0x1u << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_ECCERR8_Pos 1
+#define SMC_ECC_SR2_ECCERR8_Msk (0x3u << SMC_ECC_SR2_ECCERR8_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_RECERR9 (0x1u << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_ECCERR9 (0x1u << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_MULERR9 (0x1u << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_RECERR10 (0x1u << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_ECCERR10 (0x1u << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_MULERR10 (0x1u << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_RECERR11 (0x1u << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_ECCERR11 (0x1u << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_MULERR11 (0x1u << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_RECERR12 (0x1u << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_ECCERR12_Pos 17
+#define SMC_ECC_SR2_ECCERR12_Msk (0x3u << SMC_ECC_SR2_ECCERR12_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_RECERR13 (0x1u << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_ECCERR13_Pos 21
+#define SMC_ECC_SR2_ECCERR13_Msk (0x3u << SMC_ECC_SR2_ECCERR13_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_RECERR14 (0x1u << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_ECCERR14_Pos 25
+#define SMC_ECC_SR2_ECCERR14_Msk (0x3u << SMC_ECC_SR2_ECCERR14_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_RECERR15 (0x1u << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */
+#define SMC_ECC_SR2_ECCERR15_Pos 29
+#define SMC_ECC_SR2_ECCERR15_Msk (0x3u << SMC_ECC_SR2_ECCERR15_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */
+/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */
+#define SMC_ECC_PR2_BITADDR_Pos 0
+#define SMC_ECC_PR2_BITADDR_Msk (0x7u << SMC_ECC_PR2_BITADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_WORDADDR_Pos 3
+#define SMC_ECC_PR2_WORDADDR_Msk (0x1ffu << SMC_ECC_PR2_WORDADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_Pos 12
+#define SMC_ECC_PR2_NPARITY_Msk (0xfffu << SMC_ECC_PR2_NPARITY_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR2_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR2_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR2_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */
+#define SMC_ECC_PR3_BITADDR_Pos 0
+#define SMC_ECC_PR3_BITADDR_Msk (0x7u << SMC_ECC_PR3_BITADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_WORDADDR_Pos 3
+#define SMC_ECC_PR3_WORDADDR_Msk (0x1ffu << SMC_ECC_PR3_WORDADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_Pos 12
+#define SMC_ECC_PR3_NPARITY_Msk (0xfffu << SMC_ECC_PR3_NPARITY_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR3_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR3_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR3_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */
+#define SMC_ECC_PR4_BITADDR_Pos 0
+#define SMC_ECC_PR4_BITADDR_Msk (0x7u << SMC_ECC_PR4_BITADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_WORDADDR_Pos 3
+#define SMC_ECC_PR4_WORDADDR_Msk (0x1ffu << SMC_ECC_PR4_WORDADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_Pos 12
+#define SMC_ECC_PR4_NPARITY_Msk (0xfffu << SMC_ECC_PR4_NPARITY_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR4_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR4_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR4_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */
+#define SMC_ECC_PR5_BITADDR_Pos 0
+#define SMC_ECC_PR5_BITADDR_Msk (0x7u << SMC_ECC_PR5_BITADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_WORDADDR_Pos 3
+#define SMC_ECC_PR5_WORDADDR_Msk (0x1ffu << SMC_ECC_PR5_WORDADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_Pos 12
+#define SMC_ECC_PR5_NPARITY_Msk (0xfffu << SMC_ECC_PR5_NPARITY_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR5_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR5_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR5_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */
+#define SMC_ECC_PR6_BITADDR_Pos 0
+#define SMC_ECC_PR6_BITADDR_Msk (0x7u << SMC_ECC_PR6_BITADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_WORDADDR_Pos 3
+#define SMC_ECC_PR6_WORDADDR_Msk (0x1ffu << SMC_ECC_PR6_WORDADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_Pos 12
+#define SMC_ECC_PR6_NPARITY_Msk (0xfffu << SMC_ECC_PR6_NPARITY_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR6_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR6_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR6_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */
+#define SMC_ECC_PR7_BITADDR_Pos 0
+#define SMC_ECC_PR7_BITADDR_Msk (0x7u << SMC_ECC_PR7_BITADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_WORDADDR_Pos 3
+#define SMC_ECC_PR7_WORDADDR_Msk (0x1ffu << SMC_ECC_PR7_WORDADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_Pos 12
+#define SMC_ECC_PR7_NPARITY_Msk (0xfffu << SMC_ECC_PR7_NPARITY_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR7_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR7_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR7_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */
+#define SMC_ECC_PR8_BITADDR_Pos 0
+#define SMC_ECC_PR8_BITADDR_Msk (0x7u << SMC_ECC_PR8_BITADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_WORDADDR_Pos 3
+#define SMC_ECC_PR8_WORDADDR_Msk (0xffu << SMC_ECC_PR8_WORDADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_NPARITY_Pos 12
+#define SMC_ECC_PR8_NPARITY_Msk (0x7ffu << SMC_ECC_PR8_NPARITY_Pos) /**< \brief (SMC_ECC_PR8) Parity N */
+/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */
+#define SMC_ECC_PR9_BITADDR_Pos 0
+#define SMC_ECC_PR9_BITADDR_Msk (0x7u << SMC_ECC_PR9_BITADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_WORDADDR_Pos 3
+#define SMC_ECC_PR9_WORDADDR_Msk (0xffu << SMC_ECC_PR9_WORDADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_NPARITY_Pos 12
+#define SMC_ECC_PR9_NPARITY_Msk (0x7ffu << SMC_ECC_PR9_NPARITY_Pos) /**< \brief (SMC_ECC_PR9) Parity N */
+/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */
+#define SMC_ECC_PR10_BITADDR_Pos 0
+#define SMC_ECC_PR10_BITADDR_Msk (0x7u << SMC_ECC_PR10_BITADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_WORDADDR_Pos 3
+#define SMC_ECC_PR10_WORDADDR_Msk (0xffu << SMC_ECC_PR10_WORDADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_NPARITY_Pos 12
+#define SMC_ECC_PR10_NPARITY_Msk (0x7ffu << SMC_ECC_PR10_NPARITY_Pos) /**< \brief (SMC_ECC_PR10) Parity N */
+/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */
+#define SMC_ECC_PR11_BITADDR_Pos 0
+#define SMC_ECC_PR11_BITADDR_Msk (0x7u << SMC_ECC_PR11_BITADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_WORDADDR_Pos 3
+#define SMC_ECC_PR11_WORDADDR_Msk (0xffu << SMC_ECC_PR11_WORDADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_NPARITY_Pos 12
+#define SMC_ECC_PR11_NPARITY_Msk (0x7ffu << SMC_ECC_PR11_NPARITY_Pos) /**< \brief (SMC_ECC_PR11) Parity N */
+/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */
+#define SMC_ECC_PR12_BITADDR_Pos 0
+#define SMC_ECC_PR12_BITADDR_Msk (0x7u << SMC_ECC_PR12_BITADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_WORDADDR_Pos 3
+#define SMC_ECC_PR12_WORDADDR_Msk (0xffu << SMC_ECC_PR12_WORDADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_NPARITY_Pos 12
+#define SMC_ECC_PR12_NPARITY_Msk (0x7ffu << SMC_ECC_PR12_NPARITY_Pos) /**< \brief (SMC_ECC_PR12) Parity N */
+/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */
+#define SMC_ECC_PR13_BITADDR_Pos 0
+#define SMC_ECC_PR13_BITADDR_Msk (0x7u << SMC_ECC_PR13_BITADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_WORDADDR_Pos 3
+#define SMC_ECC_PR13_WORDADDR_Msk (0xffu << SMC_ECC_PR13_WORDADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_NPARITY_Pos 12
+#define SMC_ECC_PR13_NPARITY_Msk (0x7ffu << SMC_ECC_PR13_NPARITY_Pos) /**< \brief (SMC_ECC_PR13) Parity N */
+/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */
+#define SMC_ECC_PR14_BITADDR_Pos 0
+#define SMC_ECC_PR14_BITADDR_Msk (0x7u << SMC_ECC_PR14_BITADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_WORDADDR_Pos 3
+#define SMC_ECC_PR14_WORDADDR_Msk (0xffu << SMC_ECC_PR14_WORDADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_NPARITY_Pos 12
+#define SMC_ECC_PR14_NPARITY_Msk (0x7ffu << SMC_ECC_PR14_NPARITY_Pos) /**< \brief (SMC_ECC_PR14) Parity N */
+/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */
+#define SMC_ECC_PR15_BITADDR_Pos 0
+#define SMC_ECC_PR15_BITADDR_Msk (0x7u << SMC_ECC_PR15_BITADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_WORDADDR_Pos 3
+#define SMC_ECC_PR15_WORDADDR_Msk (0xffu << SMC_ECC_PR15_WORDADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_NPARITY_Pos 12
+#define SMC_ECC_PR15_NPARITY_Msk (0x7ffu << SMC_ECC_PR15_NPARITY_Pos) /**< \brief (SMC_ECC_PR15) Parity N */
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
+#define SMC_SETUP_NWE_SETUP_Pos 0
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Write Access */
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
+#define SMC_SETUP_NRD_SETUP_Pos 16
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Read Access */
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
+#define SMC_PULSE_NWE_PULSE_Pos 0
+#define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
+#define SMC_PULSE_NRD_PULSE_Pos 16
+#define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
+#define SMC_CYCLE_NWE_CYCLE_Pos 0
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
+#define SMC_CYCLE_NRD_CYCLE_Pos 16
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
+/* -------- SMC_TIMINGS : (SMC Offset: N/A) SMC Timings Register -------- */
+#define SMC_TIMINGS_TCLR_Pos 0
+#define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) /**< \brief (SMC_TIMINGS) CLE to REN Low Delay */
+#define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos)))
+#define SMC_TIMINGS_TADL_Pos 4
+#define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) /**< \brief (SMC_TIMINGS) ALE to Data Start */
+#define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos)))
+#define SMC_TIMINGS_TAR_Pos 8
+#define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) /**< \brief (SMC_TIMINGS) ALE to REN Low Delay */
+#define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos)))
+#define SMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (SMC_TIMINGS) Off Chip Memory Scrambling Enable */
+#define SMC_TIMINGS_TRR_Pos 16
+#define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) /**< \brief (SMC_TIMINGS) Ready to REN Low Delay */
+#define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos)))
+#define SMC_TIMINGS_TWB_Pos 24
+#define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) /**< \brief (SMC_TIMINGS) WEN High to REN to Busy */
+#define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos)))
+#define SMC_TIMINGS_RBNSEL_Pos 28
+#define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) /**< \brief (SMC_TIMINGS) Ready/Busy Line Selection */
+#define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos)))
+#define SMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (SMC_TIMINGS) NAND Flash Selection */
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE)  */
+#define   SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NCS signal. */
+#define   SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NRD signal. */
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE)  */
+#define   SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (SMC_MODE) The Write operation is controller by the NCS signal. */
+#define   SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (SMC_MODE) The Write operation is controlled by the NWE signal. */
+#define SMC_MODE_EXNW_MODE_Pos 4
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
+#define   SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
+#define   SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
+#define   SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
+#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */
+#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */
+#define   SMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
+#define   SMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
+#define SMC_MODE_TDF_CYCLES_Pos 16
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
+/* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS Register -------- */
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
+#define SMC_OCMS_SRSE (0x1u << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */
+/* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC OCMS KEY1 Register -------- */
+#define SMC_KEY1_KEY1_Pos 0
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
+/* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC OCMS KEY2 Register -------- */
+#define SMC_KEY2_KEY2_Pos 0
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
+/* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */
+#define SMC_WPCR_WP_EN (0x1u << 0) /**< \brief (SMC_WPCR) Write Protection Enable */
+#define SMC_WPCR_WP_KEY_Pos 8
+#define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) /**< \brief (SMC_WPCR) Write Protection KEY password */
+#define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos)))
+/* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */
+#define SMC_WPSR_WP_VS_Pos 0
+#define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Status */
+#define SMC_WPSR_WP_VSRC_Pos 8
+#define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_SMC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_spi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_spi.h
new file mode 100644
index 0000000..ebca319
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_spi.h
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SPI_COMPONENT_
+#define _SAM3U_SPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3U_SPI Serial Peripheral Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Spi hardware registers */
+typedef struct {
+  WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
+  RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
+  RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
+  WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+  RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
+  WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+  WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+  RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+  RoReg Reserved1[4];
+  RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
+  RoReg Reserved2[41];
+  RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+  RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+} Spi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */
+#define SPI_WPMR_WPKEY_Pos 8
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */
+#define SPI_WPSR_WPVSRC_Pos 8
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_SPI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_ssc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_ssc.h
new file mode 100644
index 0000000..11a94c3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_ssc.h
@@ -0,0 +1,270 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SSC_COMPONENT_
+#define _SAM3U_SSC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_SSC Synchronous Serial Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Ssc hardware registers */
+typedef struct {
+  WoReg SSC_CR;        /**< \brief (Ssc Offset: 0x0) Control Register */
+  RwReg SSC_CMR;       /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
+  RoReg Reserved1[2];
+  RwReg SSC_RCMR;      /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
+  RwReg SSC_RFMR;      /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
+  RwReg SSC_TCMR;      /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
+  RwReg SSC_TFMR;      /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
+  RoReg SSC_RHR;       /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
+  WoReg SSC_THR;       /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
+  RoReg Reserved2[2];
+  RoReg SSC_RSHR;      /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
+  RwReg SSC_TSHR;      /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
+  RwReg SSC_RC0R;      /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
+  RwReg SSC_RC1R;      /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
+  RoReg SSC_SR;        /**< \brief (Ssc Offset: 0x40) Status Register */
+  WoReg SSC_IER;       /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
+  WoReg SSC_IDR;       /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
+  RoReg SSC_IMR;       /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved3[37];
+  RwReg SSC_WPMR;      /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
+  RoReg SSC_WPSR;      /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
+} Ssc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
+#define SSC_CMR_DIV_Pos 0
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
+#define SSC_RCMR_CKS_Pos 0
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
+#define   SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
+#define   SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
+#define   SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
+#define SSC_RCMR_CKO_Pos 2
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
+#define   SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
+#define SSC_RCMR_CKG_Pos 6
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
+#define   SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_START_Pos 8
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
+#define   SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define   SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
+#define   SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
+#define   SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
+#define   SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
+#define   SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
+#define   SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
+#define   SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
+#define   SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
+#define SSC_RCMR_STTDLY_Pos 16
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
+#define SSC_RCMR_PERIOD_Pos 24
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
+#define SSC_RFMR_DATLEN_Pos 0
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
+#define SSC_RFMR_DATNB_Pos 8
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
+#define SSC_RFMR_FSLEN_Pos 16
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
+#define SSC_RFMR_FSOS_Pos 20
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
+#define   SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
+#define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
+#define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
+#define   SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
+#define   SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
+#define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
+#define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
+#define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
+#define SSC_RFMR_FSLEN_EXT_Pos 28
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
+#define SSC_TCMR_CKS_Pos 0
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
+#define   SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
+#define   SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
+#define   SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
+#define SSC_TCMR_CKO_Pos 2
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
+#define   SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
+#define   SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
+#define SSC_TCMR_CKG_Pos 6
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
+#define   SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
+#define   SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
+#define SSC_TCMR_START_Pos 8
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
+#define   SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
+#define   SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
+#define   SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
+#define   SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
+#define   SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
+#define   SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
+#define   SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
+#define   SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
+#define   SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
+#define SSC_TCMR_STTDLY_Pos 16
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
+#define SSC_TCMR_PERIOD_Pos 24
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
+#define SSC_TFMR_DATLEN_Pos 0
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
+#define SSC_TFMR_DATNB_Pos 8
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
+#define SSC_TFMR_FSLEN_Pos 16
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
+#define SSC_TFMR_FSOS_Pos 20
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
+#define   SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
+#define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
+#define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
+#define   SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
+#define   SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
+#define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
+#define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
+#define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
+#define SSC_TFMR_FSLEN_EXT_Pos 28
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
+#define SSC_RHR_RDAT_Pos 0
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
+#define SSC_THR_TDAT_Pos 0
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
+#define SSC_RSHR_RSDAT_Pos 0
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
+#define SSC_TSHR_TSDAT_Pos 0
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
+#define SSC_RC0R_CP0_Pos 0
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
+#define SSC_RC1R_CP1_Pos 0
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
+#define SSC_WPMR_WPKEY_Pos 8
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
+#define SSC_WPSR_WPVSRC_Pos 8
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3U_SSC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_supc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_supc.h
new file mode 100644
index 0000000..4962fa6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_supc.h
@@ -0,0 +1,312 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SUPC_COMPONENT_
+#define _SAM3U_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3U_SUPC Supply Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Supc hardware registers */
+typedef struct {
+  WoReg SUPC_CR;   /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+  RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+  RwReg SUPC_MR;   /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+  RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+  RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+  RoReg SUPC_SR;   /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_VDDIORDYONREG (0x1u << 14) /**< \brief (SUPC_MR)  */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_FWUPEN (0x1u << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */
+#define   SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */
+#define   SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_FWUPDBC_Pos 8
+#define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer Period */
+#define   SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define   SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define   SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define   SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define   SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define   SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define   SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define   SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define   SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define   SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define   SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define   SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define   SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define   SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define   SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define   SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define   SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
+#define   SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
+#define   SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
+#define   SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
+#define   SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
+#define   SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
+#define   SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
+#define   SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
+#define   SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
+#define   SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
+#define   SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
+#define   SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
+#define   SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
+#define   SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
+#define   SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
+#define   SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
+#define   SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_FWUPS (0x1u << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */
+#define   SUPC_SR_FWUPS_NO (0x0u << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_FWUPS_PRESENT (0x1u << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define   SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define   SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define   SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define   SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define   SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define   SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define   SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */
+#define   SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define   SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_FWUPIS (0x1u << 12) /**< \brief (SUPC_SR) FWUP Input Status */
+#define   SUPC_SR_FWUPIS_LOW (0x0u << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */
+#define   SUPC_SR_FWUPIS_HIGH (0x1u << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+
+#endif /* _SAM3U_SUPC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_tc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_tc.h
new file mode 100644
index 0000000..284704c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_tc.h
@@ -0,0 +1,288 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_TC_COMPONENT_
+#define _SAM3U_TC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM3U_TC Timer Counter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief TcChannel hardware registers */
+typedef struct {
+  RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+  RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+  RoReg      Reserved1[2];
+  RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
+  RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
+  RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
+  RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
+  RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
+  RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+  RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+  RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+  RoReg      Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+  TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+  WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
+  RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+  WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+  WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+  RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+  RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
+
+/*@}*/
+
+
+#endif /* _SAM3U_TC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_twi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_twi.h
new file mode 100644
index 0000000..87277be
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_twi.h
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_TWI_COMPONENT_
+#define _SAM3U_TWI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3U_TWI Two-wire Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Twi hardware registers */
+typedef struct {
+  WoReg TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
+  RwReg TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
+  RwReg TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+  RwReg TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+  RwReg TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+  RoReg Reserved1[3];
+  RoReg TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
+  WoReg TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+  WoReg TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+  RoReg TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+  RoReg TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+  WoReg TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+  RoReg Reserved2[50];
+  RwReg TWI_RPR;       /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+  RwReg TWI_RCR;       /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+  RwReg TWI_TPR;       /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+  RwReg TWI_TCR;       /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+  RwReg TWI_RNPR;      /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+  RwReg TWI_RNCR;      /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+  RwReg TWI_TNPR;      /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg TWI_TNCR;      /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg TWI_PTCR;      /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+  RoReg TWI_PTSR;      /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_TWI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_uart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_uart.h
new file mode 100644
index 0000000..1ff2ad4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_uart.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_UART_COMPONENT_
+#define _SAM3U_UART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3U_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Uart hardware registers */
+typedef struct {
+  WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
+  RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
+  WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+  WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+  RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+  RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
+  RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+  WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+  RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+  RoReg Reserved1[55];
+  RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+  RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+  RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+  RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+  RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+  RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+  RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+  RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_UART_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_udphs.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_udphs.h
new file mode 100644
index 0000000..0bb9f57
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_udphs.h
@@ -0,0 +1,375 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_UDPHS_COMPONENT_
+#define _SAM3U_UDPHS_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR USB High Speed Device Port */
+/* ============================================================================= */
+/** \addtogroup SAM3U_UDPHS USB High Speed Device Port */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief UdphsDma hardware registers */
+typedef struct {
+  RwReg     UDPHS_DMANXTDSC;  /**< \brief (UdphsDma Offset: 0x0) UDPHS DMA Next Descriptor Address Register */
+  RwReg     UDPHS_DMAADDRESS; /**< \brief (UdphsDma Offset: 0x4) UDPHS DMA Channel Address Register */
+  RwReg     UDPHS_DMACONTROL; /**< \brief (UdphsDma Offset: 0x8) UDPHS DMA Channel Control Register */
+  RwReg     UDPHS_DMASTATUS;  /**< \brief (UdphsDma Offset: 0xC) UDPHS DMA Channel Status Register */
+} UdphsDma;
+/** \brief UdphsEpt hardware registers */
+typedef struct {
+  RwReg     UDPHS_EPTCFG;     /**< \brief (UdphsEpt Offset: 0x0) UDPHS Endpoint Configuration Register */
+  RwReg     UDPHS_EPTCTLENB;  /**< \brief (UdphsEpt Offset: 0x4) UDPHS Endpoint Control Enable Register */
+  RwReg     UDPHS_EPTCTLDIS;  /**< \brief (UdphsEpt Offset: 0x8) UDPHS Endpoint Control Disable Register */
+  RwReg     UDPHS_EPTCTL;     /**< \brief (UdphsEpt Offset: 0xC) UDPHS Endpoint Control Register */
+  RoReg     Reserved1[1];
+  RwReg     UDPHS_EPTSETSTA;  /**< \brief (UdphsEpt Offset: 0x14) UDPHS Endpoint Set Status Register */
+  RwReg     UDPHS_EPTCLRSTA;  /**< \brief (UdphsEpt Offset: 0x18) UDPHS Endpoint Clear Status Register */
+  RwReg     UDPHS_EPTSTA;     /**< \brief (UdphsEpt Offset: 0x1C) UDPHS Endpoint Status Register */
+} UdphsEpt;
+/** \brief Udphs hardware registers */
+#define UDPHSEPT_NUMBER 7
+#define UDPHSDMA_NUMBER 6
+typedef struct {
+  RwReg     UDPHS_CTRL;       /**< \brief (Udphs Offset: 0x00) UDPHS Control Register */
+  RoReg     UDPHS_FNUM;       /**< \brief (Udphs Offset: 0x04) UDPHS Frame Number Register */
+  RoReg     Reserved1[2];
+  RwReg     UDPHS_IEN;        /**< \brief (Udphs Offset: 0x10) UDPHS Interrupt Enable Register */
+  RoReg     UDPHS_INTSTA;     /**< \brief (Udphs Offset: 0x14) UDPHS Interrupt Status Register */
+  WoReg     UDPHS_CLRINT;     /**< \brief (Udphs Offset: 0x18) UDPHS Clear Interrupt Register */
+  WoReg     UDPHS_EPTRST;     /**< \brief (Udphs Offset: 0x1C) UDPHS Endpoints Reset Register */
+  RoReg     Reserved2[48];
+  RwReg     UDPHS_TST;        /**< \brief (Udphs Offset: 0xE0) UDPHS Test Register */
+  RoReg     Reserved3[3];
+  RoReg     UDPHS_IPNAME1;    /**< \brief (Udphs Offset: 0xF0) UDPHS Name1 Register */
+  RoReg     UDPHS_IPNAME2;    /**< \brief (Udphs Offset: 0xF4) UDPHS Name2 Register */
+  RoReg     UDPHS_IPFEATURES; /**< \brief (Udphs Offset: 0xF8) UDPHS Features Register */
+  RoReg     Reserved4[1];
+  UdphsEpt  UDPHS_EPT[UDPHSEPT_NUMBER]; /**< \brief (Udphs Offset: 0x100) endpoint = 0 .. 6 */
+  RoReg     Reserved5[72];
+  UdphsDma  UDPHS_DMA[UDPHSDMA_NUMBER]; /**< \brief (Udphs Offset: 0x300) channel = 0 .. 5 */
+} Udphs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UDPHS_CTRL : (UDPHS Offset: 0x00) UDPHS Control Register -------- */
+#define UDPHS_CTRL_DEV_ADDR_Pos 0
+#define UDPHS_CTRL_DEV_ADDR_Msk (0x7fu << UDPHS_CTRL_DEV_ADDR_Pos) /**< \brief (UDPHS_CTRL) UDPHS Address */
+#define UDPHS_CTRL_DEV_ADDR(value) ((UDPHS_CTRL_DEV_ADDR_Msk & ((value) << UDPHS_CTRL_DEV_ADDR_Pos)))
+#define UDPHS_CTRL_FADDR_EN (0x1u << 7) /**< \brief (UDPHS_CTRL) Function Address Enable */
+#define UDPHS_CTRL_EN_UDPHS (0x1u << 8) /**< \brief (UDPHS_CTRL) UDPHS Enable */
+#define UDPHS_CTRL_DETACH (0x1u << 9) /**< \brief (UDPHS_CTRL) Detach Command */
+#define UDPHS_CTRL_REWAKEUP (0x1u << 10) /**< \brief (UDPHS_CTRL) Send Remote Wake Up */
+#define UDPHS_CTRL_PULLD_DIS (0x1u << 11) /**< \brief (UDPHS_CTRL) Pull-Down Disable */
+/* -------- UDPHS_FNUM : (UDPHS Offset: 0x04) UDPHS Frame Number Register -------- */
+#define UDPHS_FNUM_MICRO_FRAME_NUM_Pos 0
+#define UDPHS_FNUM_MICRO_FRAME_NUM_Msk (0x7u << UDPHS_FNUM_MICRO_FRAME_NUM_Pos) /**< \brief (UDPHS_FNUM) Microframe Number */
+#define UDPHS_FNUM_FRAME_NUMBER_Pos 3
+#define UDPHS_FNUM_FRAME_NUMBER_Msk (0x7ffu << UDPHS_FNUM_FRAME_NUMBER_Pos) /**< \brief (UDPHS_FNUM) Frame Number as defined in the Packet Field Formats */
+#define UDPHS_FNUM_FNUM_ERR (0x1u << 31) /**< \brief (UDPHS_FNUM) Frame Number CRC Error */
+/* -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- */
+#define UDPHS_IEN_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_IEN) Suspend Interrupt Enable */
+#define UDPHS_IEN_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_IEN) Micro-SOF Interrupt Enable */
+#define UDPHS_IEN_INT_SOF (0x1u << 3) /**< \brief (UDPHS_IEN) SOF Interrupt Enable */
+#define UDPHS_IEN_ENDRESET (0x1u << 4) /**< \brief (UDPHS_IEN) End Of Reset Interrupt Enable */
+#define UDPHS_IEN_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_IEN) Wake Up CPU Interrupt Enable */
+#define UDPHS_IEN_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_IEN) End Of Resume Interrupt Enable */
+#define UDPHS_IEN_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_IEN) Upstream Resume Interrupt Enable */
+#define UDPHS_IEN_EPT_0 (0x1u << 8) /**< \brief (UDPHS_IEN) Endpoint 0 Interrupt Enable */
+#define UDPHS_IEN_EPT_1 (0x1u << 9) /**< \brief (UDPHS_IEN) Endpoint 1 Interrupt Enable */
+#define UDPHS_IEN_EPT_2 (0x1u << 10) /**< \brief (UDPHS_IEN) Endpoint 2 Interrupt Enable */
+#define UDPHS_IEN_EPT_3 (0x1u << 11) /**< \brief (UDPHS_IEN) Endpoint 3 Interrupt Enable */
+#define UDPHS_IEN_EPT_4 (0x1u << 12) /**< \brief (UDPHS_IEN) Endpoint 4 Interrupt Enable */
+#define UDPHS_IEN_EPT_5 (0x1u << 13) /**< \brief (UDPHS_IEN) Endpoint 5 Interrupt Enable */
+#define UDPHS_IEN_EPT_6 (0x1u << 14) /**< \brief (UDPHS_IEN) Endpoint 6 Interrupt Enable */
+#define UDPHS_IEN_DMA_1 (0x1u << 25) /**< \brief (UDPHS_IEN) DMA Channel 1 Interrupt Enable */
+#define UDPHS_IEN_DMA_2 (0x1u << 26) /**< \brief (UDPHS_IEN) DMA Channel 2 Interrupt Enable */
+#define UDPHS_IEN_DMA_3 (0x1u << 27) /**< \brief (UDPHS_IEN) DMA Channel 3 Interrupt Enable */
+#define UDPHS_IEN_DMA_4 (0x1u << 28) /**< \brief (UDPHS_IEN) DMA Channel 4 Interrupt Enable */
+#define UDPHS_IEN_DMA_5 (0x1u << 29) /**< \brief (UDPHS_IEN) DMA Channel 5 Interrupt Enable */
+#define UDPHS_IEN_DMA_6 (0x1u << 30) /**< \brief (UDPHS_IEN) DMA Channel 6 Interrupt Enable */
+/* -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- */
+#define UDPHS_INTSTA_SPEED (0x1u << 0) /**< \brief (UDPHS_INTSTA) Speed Status */
+#define UDPHS_INTSTA_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_INTSTA) Suspend Interrupt */
+#define UDPHS_INTSTA_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_INTSTA) Micro Start Of Frame Interrupt */
+#define UDPHS_INTSTA_INT_SOF (0x1u << 3) /**< \brief (UDPHS_INTSTA) Start Of Frame Interrupt */
+#define UDPHS_INTSTA_ENDRESET (0x1u << 4) /**< \brief (UDPHS_INTSTA) End Of Reset Interrupt */
+#define UDPHS_INTSTA_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_INTSTA) Wake Up CPU Interrupt */
+#define UDPHS_INTSTA_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_INTSTA) End Of Resume Interrupt */
+#define UDPHS_INTSTA_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_INTSTA) Upstream Resume Interrupt */
+#define UDPHS_INTSTA_EPT_0 (0x1u << 8) /**< \brief (UDPHS_INTSTA) Endpoint 0 Interrupt */
+#define UDPHS_INTSTA_EPT_1 (0x1u << 9) /**< \brief (UDPHS_INTSTA) Endpoint 1 Interrupt */
+#define UDPHS_INTSTA_EPT_2 (0x1u << 10) /**< \brief (UDPHS_INTSTA) Endpoint 2 Interrupt */
+#define UDPHS_INTSTA_EPT_3 (0x1u << 11) /**< \brief (UDPHS_INTSTA) Endpoint 3 Interrupt */
+#define UDPHS_INTSTA_EPT_4 (0x1u << 12) /**< \brief (UDPHS_INTSTA) Endpoint 4 Interrupt */
+#define UDPHS_INTSTA_EPT_5 (0x1u << 13) /**< \brief (UDPHS_INTSTA) Endpoint 5 Interrupt */
+#define UDPHS_INTSTA_EPT_6 (0x1u << 14) /**< \brief (UDPHS_INTSTA) Endpoint 6 Interrupt */
+#define UDPHS_INTSTA_DMA_1 (0x1u << 25) /**< \brief (UDPHS_INTSTA) DMA Channel 1 Interrupt */
+#define UDPHS_INTSTA_DMA_2 (0x1u << 26) /**< \brief (UDPHS_INTSTA) DMA Channel 2 Interrupt */
+#define UDPHS_INTSTA_DMA_3 (0x1u << 27) /**< \brief (UDPHS_INTSTA) DMA Channel 3 Interrupt */
+#define UDPHS_INTSTA_DMA_4 (0x1u << 28) /**< \brief (UDPHS_INTSTA) DMA Channel 4 Interrupt */
+#define UDPHS_INTSTA_DMA_5 (0x1u << 29) /**< \brief (UDPHS_INTSTA) DMA Channel 5 Interrupt */
+#define UDPHS_INTSTA_DMA_6 (0x1u << 30) /**< \brief (UDPHS_INTSTA) DMA Channel 6 Interrupt */
+/* -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- */
+#define UDPHS_CLRINT_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_CLRINT) Suspend Interrupt Clear */
+#define UDPHS_CLRINT_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_CLRINT) Micro Start Of Frame Interrupt Clear */
+#define UDPHS_CLRINT_INT_SOF (0x1u << 3) /**< \brief (UDPHS_CLRINT) Start Of Frame Interrupt Clear */
+#define UDPHS_CLRINT_ENDRESET (0x1u << 4) /**< \brief (UDPHS_CLRINT) End Of Reset Interrupt Clear */
+#define UDPHS_CLRINT_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_CLRINT) Wake Up CPU Interrupt Clear */
+#define UDPHS_CLRINT_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_CLRINT) End Of Resume Interrupt Clear */
+#define UDPHS_CLRINT_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_CLRINT) Upstream Resume Interrupt Clear */
+/* -------- UDPHS_EPTRST : (UDPHS Offset: 0x1C) UDPHS Endpoints Reset Register -------- */
+#define UDPHS_EPTRST_EPT_0 (0x1u << 0) /**< \brief (UDPHS_EPTRST) Endpoint 0 Reset */
+#define UDPHS_EPTRST_EPT_1 (0x1u << 1) /**< \brief (UDPHS_EPTRST) Endpoint 1 Reset */
+#define UDPHS_EPTRST_EPT_2 (0x1u << 2) /**< \brief (UDPHS_EPTRST) Endpoint 2 Reset */
+#define UDPHS_EPTRST_EPT_3 (0x1u << 3) /**< \brief (UDPHS_EPTRST) Endpoint 3 Reset */
+#define UDPHS_EPTRST_EPT_4 (0x1u << 4) /**< \brief (UDPHS_EPTRST) Endpoint 4 Reset */
+#define UDPHS_EPTRST_EPT_5 (0x1u << 5) /**< \brief (UDPHS_EPTRST) Endpoint 5 Reset */
+#define UDPHS_EPTRST_EPT_6 (0x1u << 6) /**< \brief (UDPHS_EPTRST) Endpoint 6 Reset */
+/* -------- UDPHS_TST : (UDPHS Offset: 0xE0) UDPHS Test Register -------- */
+#define UDPHS_TST_SPEED_CFG_Pos 0
+#define UDPHS_TST_SPEED_CFG_Msk (0x3u << UDPHS_TST_SPEED_CFG_Pos) /**< \brief (UDPHS_TST) Speed Configuration */
+#define   UDPHS_TST_SPEED_CFG_NORMAL (0x0u << 0) /**< \brief (UDPHS_TST) Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode */
+#define   UDPHS_TST_SPEED_CFG_HIGH_SPEED (0x2u << 0) /**< \brief (UDPHS_TST) Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. */
+#define   UDPHS_TST_SPEED_CFG_FULL_SPEED (0x3u << 0) /**< \brief (UDPHS_TST) Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. */
+#define UDPHS_TST_TST_J (0x1u << 2) /**< \brief (UDPHS_TST) Test J Mode */
+#define UDPHS_TST_TST_K (0x1u << 3) /**< \brief (UDPHS_TST) Test K Mode */
+#define UDPHS_TST_TST_PKT (0x1u << 4) /**< \brief (UDPHS_TST) Test Packet Mode */
+#define UDPHS_TST_OPMODE2 (0x1u << 5) /**< \brief (UDPHS_TST) OpMode2 */
+/* -------- UDPHS_IPNAME1 : (UDPHS Offset: 0xF0) UDPHS Name1 Register -------- */
+#define UDPHS_IPNAME1_IP_NAME1_Pos 0
+#define UDPHS_IPNAME1_IP_NAME1_Msk (0xffffffffu << UDPHS_IPNAME1_IP_NAME1_Pos) /**< \brief (UDPHS_IPNAME1)  */
+/* -------- UDPHS_IPNAME2 : (UDPHS Offset: 0xF4) UDPHS Name2 Register -------- */
+#define UDPHS_IPNAME2_IP_NAME2_Pos 0
+#define UDPHS_IPNAME2_IP_NAME2_Msk (0xffffffffu << UDPHS_IPNAME2_IP_NAME2_Pos) /**< \brief (UDPHS_IPNAME2)  */
+/* -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xF8) UDPHS Features Register -------- */
+#define UDPHS_IPFEATURES_EPT_NBR_MAX_Pos 0
+#define UDPHS_IPFEATURES_EPT_NBR_MAX_Msk (0xfu << UDPHS_IPFEATURES_EPT_NBR_MAX_Pos) /**< \brief (UDPHS_IPFEATURES) Max Number of Endpoints */
+#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos 4
+#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Msk (0x7u << UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos) /**< \brief (UDPHS_IPFEATURES) Number of DMA Channels */
+#define UDPHS_IPFEATURES_DMA_B_SIZ (0x1u << 7) /**< \brief (UDPHS_IPFEATURES) DMA Buffer Size */
+#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos 8
+#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Msk (0xfu << UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos) /**< \brief (UDPHS_IPFEATURES) DMA FIFO Depth in Words */
+#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos 12
+#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Msk (0x7u << UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos) /**< \brief (UDPHS_IPFEATURES) DPRAM Size */
+#define UDPHS_IPFEATURES_BW_DPRAM (0x1u << 15) /**< \brief (UDPHS_IPFEATURES) DPRAM Byte Write Capability */
+#define UDPHS_IPFEATURES_DATAB16_8 (0x1u << 16) /**< \brief (UDPHS_IPFEATURES) UTMI DataBus16_8 */
+#define UDPHS_IPFEATURES_ISO_EPT_1 (0x1u << 17) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_2 (0x1u << 18) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_3 (0x1u << 19) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_4 (0x1u << 20) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_5 (0x1u << 21) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_6 (0x1u << 22) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_7 (0x1u << 23) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_8 (0x1u << 24) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_9 (0x1u << 25) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_10 (0x1u << 26) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_11 (0x1u << 27) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_12 (0x1u << 28) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_13 (0x1u << 29) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_14 (0x1u << 30) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+#define UDPHS_IPFEATURES_ISO_EPT_15 (0x1u << 31) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
+/* -------- UDPHS_EPTCFG : (UDPHS Offset: N/A) UDPHS Endpoint Configuration Register -------- */
+#define UDPHS_EPTCFG_EPT_SIZE_Pos 0
+#define UDPHS_EPTCFG_EPT_SIZE_Msk (0x7u << UDPHS_EPTCFG_EPT_SIZE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Size */
+#define   UDPHS_EPTCFG_EPT_SIZE_8 (0x0u << 0) /**< \brief (UDPHS_EPTCFG) 8 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_16 (0x1u << 0) /**< \brief (UDPHS_EPTCFG) 16 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_32 (0x2u << 0) /**< \brief (UDPHS_EPTCFG) 32 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_64 (0x3u << 0) /**< \brief (UDPHS_EPTCFG) 64 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_128 (0x4u << 0) /**< \brief (UDPHS_EPTCFG) 128 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_256 (0x5u << 0) /**< \brief (UDPHS_EPTCFG) 256 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_512 (0x6u << 0) /**< \brief (UDPHS_EPTCFG) 512 bytes */
+#define   UDPHS_EPTCFG_EPT_SIZE_1024 (0x7u << 0) /**< \brief (UDPHS_EPTCFG) 1024 bytes */
+#define UDPHS_EPTCFG_EPT_DIR (0x1u << 3) /**< \brief (UDPHS_EPTCFG) Endpoint Direction */
+#define UDPHS_EPTCFG_EPT_TYPE_Pos 4
+#define UDPHS_EPTCFG_EPT_TYPE_Msk (0x3u << UDPHS_EPTCFG_EPT_TYPE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Type */
+#define   UDPHS_EPTCFG_EPT_TYPE_CTRL8 (0x0u << 4) /**< \brief (UDPHS_EPTCFG) Control endpoint */
+#define   UDPHS_EPTCFG_EPT_TYPE_ISO (0x1u << 4) /**< \brief (UDPHS_EPTCFG) Isochronous endpoint */
+#define   UDPHS_EPTCFG_EPT_TYPE_BULK (0x2u << 4) /**< \brief (UDPHS_EPTCFG) Bulk endpoint */
+#define   UDPHS_EPTCFG_EPT_TYPE_INT (0x3u << 4) /**< \brief (UDPHS_EPTCFG) Interrupt endpoint */
+#define UDPHS_EPTCFG_BK_NUMBER_Pos 6
+#define UDPHS_EPTCFG_BK_NUMBER_Msk (0x3u << UDPHS_EPTCFG_BK_NUMBER_Pos) /**< \brief (UDPHS_EPTCFG) Number of Banks */
+#define   UDPHS_EPTCFG_BK_NUMBER_0 (0x0u << 6) /**< \brief (UDPHS_EPTCFG) Zero bank, the endpoint is not mapped in memory */
+#define   UDPHS_EPTCFG_BK_NUMBER_1 (0x1u << 6) /**< \brief (UDPHS_EPTCFG) One bank (bank 0) */
+#define   UDPHS_EPTCFG_BK_NUMBER_2 (0x2u << 6) /**< \brief (UDPHS_EPTCFG) Double bank (Ping-Pong: bank0/bank1) */
+#define   UDPHS_EPTCFG_BK_NUMBER_3 (0x3u << 6) /**< \brief (UDPHS_EPTCFG) Triple bank (bank0/bank1/bank2) */
+#define UDPHS_EPTCFG_NB_TRANS_Pos 8
+#define UDPHS_EPTCFG_NB_TRANS_Msk (0x3u << UDPHS_EPTCFG_NB_TRANS_Pos) /**< \brief (UDPHS_EPTCFG) Number Of Transaction per Microframe */
+#define UDPHS_EPTCFG_NB_TRANS(value) ((UDPHS_EPTCFG_NB_TRANS_Msk & ((value) << UDPHS_EPTCFG_NB_TRANS_Pos)))
+#define UDPHS_EPTCFG_EPT_MAPD (0x1u << 31) /**< \brief (UDPHS_EPTCFG) Endpoint Mapped */
+/* -------- UDPHS_EPTCTLENB : (UDPHS Offset: N/A) UDPHS Endpoint Control Enable Register -------- */
+#define UDPHS_EPTCTLENB_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLENB) Endpoint Enable */
+#define UDPHS_EPTCTLENB_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLENB) Packet Auto-Valid Enable */
+#define UDPHS_EPTCTLENB_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLENB) Interrupts Disable DMA */
+#define UDPHS_EPTCTLENB_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLENB) NYET Disable (Only for High Speed Bulk OUT endpoints) */
+#define UDPHS_EPTCTLENB_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLENB) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLENB_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLENB) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLENB_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLENB) Overflow Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTLENB) Received OUT Data Interrupt Enable */
+#define UDPHS_EPTCTLENB_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLENB) Transmitted IN Data Complete Interrupt Enable */
+#define UDPHS_EPTCTLENB_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP/Error Flow Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP/Error Flow Interrupt Enable */
+#define UDPHS_EPTCTLENB_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN/Bank Flush Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN/Bank Flush Error Interrupt Enable */
+#define UDPHS_EPTCTLENB_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLENB) NAKOUT Interrupt Enable */
+#define UDPHS_EPTCTLENB_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLENB) Busy Bank Interrupt Enable */
+#define UDPHS_EPTCTLENB_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLENB) Short Packet Send/Short Packet Interrupt Enable */
+/* -------- UDPHS_EPTCTLDIS : (UDPHS Offset: N/A) UDPHS Endpoint Control Disable Register -------- */
+#define UDPHS_EPTCTLDIS_EPT_DISABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLDIS) Endpoint Disable */
+#define UDPHS_EPTCTLDIS_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLDIS) Packet Auto-Valid Disable */
+#define UDPHS_EPTCTLDIS_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLDIS) Interrupts Disable DMA */
+#define UDPHS_EPTCTLDIS_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLDIS) NYET Enable (Only for High Speed Bulk OUT endpoints) */
+#define UDPHS_EPTCTLDIS_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLDIS) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLDIS_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLDIS) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTLDIS_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLDIS) Overflow Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTLDIS) Received OUT Data Interrupt Disable */
+#define UDPHS_EPTCTLDIS_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLDIS) Transmitted IN Data Complete Interrupt Disable */
+#define UDPHS_EPTCTLDIS_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP/Error Flow Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP/Error Flow Interrupt Disable */
+#define UDPHS_EPTCTLDIS_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN/bank flush error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN/bank flush error Interrupt Disable */
+#define UDPHS_EPTCTLDIS_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLDIS) NAKOUT Interrupt Disable */
+#define UDPHS_EPTCTLDIS_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLDIS) Busy Bank Interrupt Disable */
+#define UDPHS_EPTCTLDIS_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLDIS) Short Packet Interrupt Disable */
+/* -------- UDPHS_EPTCTL : (UDPHS Offset: N/A) UDPHS Endpoint Control Register -------- */
+#define UDPHS_EPTCTL_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTL) Endpoint Enable */
+#define UDPHS_EPTCTL_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTL) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */
+#define UDPHS_EPTCTL_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTL) Interrupt Disables DMA */
+#define UDPHS_EPTCTL_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTL) NYET Disable (Only for High Speed Bulk OUT endpoints) */
+#define UDPHS_EPTCTL_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTL) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTL_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTL) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
+#define UDPHS_EPTCTL_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTL) Overflow Error Interrupt Enabled */
+#define UDPHS_EPTCTL_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTL) Received OUT Data Interrupt Enabled */
+#define UDPHS_EPTCTL_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTL) Transmitted IN Data Complete Interrupt Enabled */
+#define UDPHS_EPTCTL_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled */
+#define UDPHS_EPTCTL_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled */
+#define UDPHS_EPTCTL_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP/Error Flow Interrupt Enabled */
+#define UDPHS_EPTCTL_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP/Error Flow Interrupt Enabled */
+#define UDPHS_EPTCTL_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
+#define UDPHS_EPTCTL_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
+#define UDPHS_EPTCTL_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
+#define UDPHS_EPTCTL_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN/Bank Flush Error Interrupt Enabled */
+#define UDPHS_EPTCTL_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN/Bank Flush Error Interrupt Enabled */
+#define UDPHS_EPTCTL_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTL) NAKOUT Interrupt Enabled */
+#define UDPHS_EPTCTL_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTL) Busy Bank Interrupt Enabled */
+#define UDPHS_EPTCTL_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTL) Short Packet Interrupt Enabled */
+/* -------- UDPHS_EPTSETSTA : (UDPHS Offset: N/A) UDPHS Endpoint Set Status Register -------- */
+#define UDPHS_EPTSETSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSETSTA) Stall Handshake Request Set */
+#define UDPHS_EPTSETSTA_KILL_BANK (0x1u << 9) /**< \brief (UDPHS_EPTSETSTA) KILL Bank Set (for IN Endpoint) */
+#define UDPHS_EPTSETSTA_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTSETSTA) TX Packet Ready Set */
+/* -------- UDPHS_EPTCLRSTA : (UDPHS Offset: N/A) UDPHS Endpoint Clear Status Register -------- */
+#define UDPHS_EPTCLRSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTCLRSTA) Stall Handshake Request Clear */
+#define UDPHS_EPTCLRSTA_TOGGLESQ (0x1u << 6) /**< \brief (UDPHS_EPTCLRSTA) Data Toggle Clear */
+#define UDPHS_EPTCLRSTA_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCLRSTA) Received OUT Data Clear */
+#define UDPHS_EPTCLRSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCLRSTA) Transmitted IN Data Complete Clear */
+#define UDPHS_EPTCLRSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP/Error Flow Clear */
+#define UDPHS_EPTCLRSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP/Error Flow Clear */
+#define UDPHS_EPTCLRSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent/Number of Transaction Error Clear */
+#define UDPHS_EPTCLRSTA_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent/Number of Transaction Error Clear */
+#define UDPHS_EPTCLRSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN/Bank Flush Error Clear */
+#define UDPHS_EPTCLRSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN/Bank Flush Error Clear */
+#define UDPHS_EPTCLRSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCLRSTA) NAKOUT Clear */
+/* -------- UDPHS_EPTSTA : (UDPHS Offset: N/A) UDPHS Endpoint Status Register -------- */
+#define UDPHS_EPTSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSTA) Stall Handshake Request */
+#define UDPHS_EPTSTA_TOGGLESQ_STA_Pos 6
+#define UDPHS_EPTSTA_TOGGLESQ_STA_Msk (0x3u << UDPHS_EPTSTA_TOGGLESQ_STA_Pos) /**< \brief (UDPHS_EPTSTA) Toggle Sequencing */
+#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA0 (0x0u << 6) /**< \brief (UDPHS_EPTSTA) DATA0 */
+#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA1 (0x1u << 6) /**< \brief (UDPHS_EPTSTA) DATA1 */
+#define   UDPHS_EPTSTA_TOGGLESQ_STA_DATA2 (0x2u << 6) /**< \brief (UDPHS_EPTSTA) Data2 (only for High Bandwidth Isochronous Endpoint) */
+#define   UDPHS_EPTSTA_TOGGLESQ_STA_MDATA (0x3u << 6) /**< \brief (UDPHS_EPTSTA) MData (only for High Bandwidth Isochronous Endpoint) */
+#define UDPHS_EPTSTA_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTSTA) Overflow Error */
+#define UDPHS_EPTSTA_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank */
+#define UDPHS_EPTSTA_KILL_BANK (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank */
+#define UDPHS_EPTSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTSTA) Transmitted IN Data Complete */
+#define UDPHS_EPTSTA_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error */
+#define UDPHS_EPTSTA_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error */
+#define UDPHS_EPTSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP/Error Flow */
+#define UDPHS_EPTSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP/Error Flow */
+#define UDPHS_EPTSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */
+#define UDPHS_EPTSTA_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */
+#define UDPHS_EPTSTA_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */
+#define UDPHS_EPTSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN/Bank Flush Error */
+#define UDPHS_EPTSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN/Bank Flush Error */
+#define UDPHS_EPTSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTSTA) NAK OUT */
+#define UDPHS_EPTSTA_CURRENT_BANK_Pos 16
+#define UDPHS_EPTSTA_CURRENT_BANK_Msk (0x3u << UDPHS_EPTSTA_CURRENT_BANK_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction */
+#define UDPHS_EPTSTA_CONTROL_DIR_Pos 16
+#define UDPHS_EPTSTA_CONTROL_DIR_Msk (0x3u << UDPHS_EPTSTA_CONTROL_DIR_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction */
+#define UDPHS_EPTSTA_BUSY_BANK_STA_Pos 18
+#define UDPHS_EPTSTA_BUSY_BANK_STA_Msk (0x3u << UDPHS_EPTSTA_BUSY_BANK_STA_Pos) /**< \brief (UDPHS_EPTSTA) Busy Bank Number */
+#define   UDPHS_EPTSTA_BUSY_BANK_STA_1BUSYBANK (0x0u << 18) /**< \brief (UDPHS_EPTSTA) 1 busy bank */
+#define   UDPHS_EPTSTA_BUSY_BANK_STA_2BUSYBANKS (0x1u << 18) /**< \brief (UDPHS_EPTSTA) 2 busy banks */
+#define   UDPHS_EPTSTA_BUSY_BANK_STA_3BUSYBANKS (0x2u << 18) /**< \brief (UDPHS_EPTSTA) 3 busy banks */
+#define UDPHS_EPTSTA_BYTE_COUNT_Pos 20
+#define UDPHS_EPTSTA_BYTE_COUNT_Msk (0x7ffu << UDPHS_EPTSTA_BYTE_COUNT_Pos) /**< \brief (UDPHS_EPTSTA) UDPHS Byte Count */
+#define UDPHS_EPTSTA_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTSTA) Short Packet */
+/* -------- UDPHS_DMANXTDSC : (UDPHS Offset: N/A) UDPHS DMA Next Descriptor Address Register -------- */
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos 0
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UDPHS_DMANXTDSC)  */
+#define UDPHS_DMANXTDSC_NXT_DSC_ADD(value) ((UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos)))
+/* -------- UDPHS_DMAADDRESS : (UDPHS Offset: N/A) UDPHS DMA Channel Address Register -------- */
+#define UDPHS_DMAADDRESS_BUFF_ADD_Pos 0
+#define UDPHS_DMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UDPHS_DMAADDRESS_BUFF_ADD_Pos) /**< \brief (UDPHS_DMAADDRESS)  */
+#define UDPHS_DMAADDRESS_BUFF_ADD(value) ((UDPHS_DMAADDRESS_BUFF_ADD_Msk & ((value) << UDPHS_DMAADDRESS_BUFF_ADD_Pos)))
+/* -------- UDPHS_DMACONTROL : (UDPHS Offset: N/A) UDPHS DMA Channel Control Register -------- */
+#define UDPHS_DMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMACONTROL)  */
+#define UDPHS_DMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UDPHS_DMACONTROL) Load Next Channel Transfer Descriptor Enable (Command) */
+#define UDPHS_DMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UDPHS_DMACONTROL) End of Transfer Enable (Control) */
+#define UDPHS_DMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UDPHS_DMACONTROL) End of Buffer Enable (Control) */
+#define UDPHS_DMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UDPHS_DMACONTROL) End of Transfer Interrupt Enable */
+#define UDPHS_DMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UDPHS_DMACONTROL) End of Buffer Interrupt Enable */
+#define UDPHS_DMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UDPHS_DMACONTROL) Descriptor Loaded Interrupt Enable */
+#define UDPHS_DMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UDPHS_DMACONTROL) Burst Lock Enable */
+#define UDPHS_DMACONTROL_BUFF_LENGTH_Pos 16
+#define UDPHS_DMACONTROL_BUFF_LENGTH_Msk (0xffffu << UDPHS_DMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UDPHS_DMACONTROL) Buffer Byte Length (Write-only) */
+#define UDPHS_DMACONTROL_BUFF_LENGTH(value) ((UDPHS_DMACONTROL_BUFF_LENGTH_Msk & ((value) << UDPHS_DMACONTROL_BUFF_LENGTH_Pos)))
+/* -------- UDPHS_DMASTATUS : (UDPHS Offset: N/A) UDPHS DMA Channel Status Register -------- */
+#define UDPHS_DMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMASTATUS) Channel Enable Status */
+#define UDPHS_DMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UDPHS_DMASTATUS) Channel Active Status */
+#define UDPHS_DMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UDPHS_DMASTATUS) End of Channel Transfer Status */
+#define UDPHS_DMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UDPHS_DMASTATUS) End of Channel Buffer Status */
+#define UDPHS_DMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UDPHS_DMASTATUS) Descriptor Loaded Status */
+#define UDPHS_DMASTATUS_BUFF_COUNT_Pos 16
+#define UDPHS_DMASTATUS_BUFF_COUNT_Msk (0xffffu << UDPHS_DMASTATUS_BUFF_COUNT_Pos) /**< \brief (UDPHS_DMASTATUS) Buffer Byte Count */
+#define UDPHS_DMASTATUS_BUFF_COUNT(value) ((UDPHS_DMASTATUS_BUFF_COUNT_Msk & ((value) << UDPHS_DMASTATUS_BUFF_COUNT_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3U_UDPHS_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_usart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_usart.h
new file mode 100644
index 0000000..b96de73
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_usart.h
@@ -0,0 +1,355 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_USART_COMPONENT_
+#define _SAM3U_USART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3U_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Usart hardware registers */
+typedef struct {
+  WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
+  RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
+  WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+  WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+  RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+  RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+  RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+  WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+  RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+  RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+  RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+  RoReg Reserved1[5];
+  RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+  RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+  RoReg Reserved2[1];
+  RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+  RwReg US_MAN;        /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
+  RoReg Reserved3[36];
+  RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+  RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[5];
+  RwReg US_RPR;        /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+  RwReg US_RCR;        /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+  RwReg US_TPR;        /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+  RwReg US_TCR;        /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+  RwReg US_RNPR;       /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+  RwReg US_RNCR;       /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+  RwReg US_TNPR;       /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg US_TNCR;       /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg US_PTCR;       /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+  RoReg US_PTSR;       /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */
+#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
+#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define   US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */
+#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
+#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */
+#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */
+#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
+#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */
+#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */
+#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
+#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */
+#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */
+#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
+#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */
+#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */
+#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */
+#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */
+#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
+#define US_MAN_TX_PL_Pos 0
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
+#define US_MAN_TX_PP_Pos 8
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
+#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
+#define US_MAN_RX_PL_Pos 16
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
+#define US_MAN_RX_PP_Pos 24
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
+#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN)  */
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3U_USART_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_wdt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_wdt.h
new file mode 100644
index 0000000..7a5fa8e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/component/component_wdt.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_WDT_COMPONENT_
+#define _SAM3U_WDT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3U_WDT Watchdog Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Wdt hardware registers */
+typedef struct {
+  WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+  RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+  RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAM3U_WDT_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_adc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_adc.h
new file mode 100644
index 0000000..9319d46
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_adc.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_ADC_INSTANCE_
+#define _SAM3U_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CR              (0x400AC000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR              (0x400AC004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_CHER            (0x400AC010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR            (0x400AC014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR            (0x400AC018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_SR              (0x400AC01CU) /**< \brief (ADC) Status Register */
+#define REG_ADC_LCDR            (0x400AC020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER             (0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR             (0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR             (0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_CDR             (0x400AC030U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_RPR             (0x400AC100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR             (0x400AC104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR            (0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR            (0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR            (0x400AC120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR            (0x400AC124U) /**< \brief (ADC) Transfer Status Register */
+#else
+#define REG_ADC_CR     (*(WoReg*)0x400AC000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR     (*(RwReg*)0x400AC004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_CHER   (*(WoReg*)0x400AC010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR   (*(WoReg*)0x400AC014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR   (*(RoReg*)0x400AC018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_SR     (*(RoReg*)0x400AC01CU) /**< \brief (ADC) Status Register */
+#define REG_ADC_LCDR   (*(RoReg*)0x400AC020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER    (*(WoReg*)0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR    (*(WoReg*)0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR    (*(RoReg*)0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_CDR    (*(RoReg*)0x400AC030U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_RPR    (*(RwReg*)0x400AC100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR    (*(RwReg*)0x400AC104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR   (*(RwReg*)0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR   (*(RwReg*)0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR   (*(WoReg*)0x400AC120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR   (*(RoReg*)0x400AC124U) /**< \brief (ADC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_ADC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_adc12b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_adc12b.h
new file mode 100644
index 0000000..6eb92dd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_adc12b.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_ADC12B_INSTANCE_
+#define _SAM3U_ADC12B_INSTANCE_
+
+/* ========== Register definition for ADC12B peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC12B_CR              (0x400A8000U) /**< \brief (ADC12B) Control Register */
+#define REG_ADC12B_MR              (0x400A8004U) /**< \brief (ADC12B) Mode Register */
+#define REG_ADC12B_CHER            (0x400A8010U) /**< \brief (ADC12B) Channel Enable Register */
+#define REG_ADC12B_CHDR            (0x400A8014U) /**< \brief (ADC12B) Channel Disable Register */
+#define REG_ADC12B_CHSR            (0x400A8018U) /**< \brief (ADC12B) Channel Status Register */
+#define REG_ADC12B_SR              (0x400A801CU) /**< \brief (ADC12B) Status Register */
+#define REG_ADC12B_LCDR            (0x400A8020U) /**< \brief (ADC12B) Last Converted Data Register */
+#define REG_ADC12B_IER             (0x400A8024U) /**< \brief (ADC12B) Interrupt Enable Register */
+#define REG_ADC12B_IDR             (0x400A8028U) /**< \brief (ADC12B) Interrupt Disable Register */
+#define REG_ADC12B_IMR             (0x400A802CU) /**< \brief (ADC12B) Interrupt Mask Register */
+#define REG_ADC12B_CDR             (0x400A8030U) /**< \brief (ADC12B) Channel Data Register */
+#define REG_ADC12B_ACR             (0x400A8064U) /**< \brief (ADC12B) Analog Control Register */
+#define REG_ADC12B_EMR             (0x400A8068U) /**< \brief (ADC12B) Extended Mode Register */
+#define REG_ADC12B_RPR             (0x400A8100U) /**< \brief (ADC12B) Receive Pointer Register */
+#define REG_ADC12B_RCR             (0x400A8104U) /**< \brief (ADC12B) Receive Counter Register */
+#define REG_ADC12B_RNPR            (0x400A8110U) /**< \brief (ADC12B) Receive Next Pointer Register */
+#define REG_ADC12B_RNCR            (0x400A8114U) /**< \brief (ADC12B) Receive Next Counter Register */
+#define REG_ADC12B_PTCR            (0x400A8120U) /**< \brief (ADC12B) Transfer Control Register */
+#define REG_ADC12B_PTSR            (0x400A8124U) /**< \brief (ADC12B) Transfer Status Register */
+#else
+#define REG_ADC12B_CR     (*(WoReg*)0x400A8000U) /**< \brief (ADC12B) Control Register */
+#define REG_ADC12B_MR     (*(RwReg*)0x400A8004U) /**< \brief (ADC12B) Mode Register */
+#define REG_ADC12B_CHER   (*(WoReg*)0x400A8010U) /**< \brief (ADC12B) Channel Enable Register */
+#define REG_ADC12B_CHDR   (*(WoReg*)0x400A8014U) /**< \brief (ADC12B) Channel Disable Register */
+#define REG_ADC12B_CHSR   (*(RoReg*)0x400A8018U) /**< \brief (ADC12B) Channel Status Register */
+#define REG_ADC12B_SR     (*(RoReg*)0x400A801CU) /**< \brief (ADC12B) Status Register */
+#define REG_ADC12B_LCDR   (*(RoReg*)0x400A8020U) /**< \brief (ADC12B) Last Converted Data Register */
+#define REG_ADC12B_IER    (*(WoReg*)0x400A8024U) /**< \brief (ADC12B) Interrupt Enable Register */
+#define REG_ADC12B_IDR    (*(WoReg*)0x400A8028U) /**< \brief (ADC12B) Interrupt Disable Register */
+#define REG_ADC12B_IMR    (*(RoReg*)0x400A802CU) /**< \brief (ADC12B) Interrupt Mask Register */
+#define REG_ADC12B_CDR    (*(RoReg*)0x400A8030U) /**< \brief (ADC12B) Channel Data Register */
+#define REG_ADC12B_ACR    (*(RwReg*)0x400A8064U) /**< \brief (ADC12B) Analog Control Register */
+#define REG_ADC12B_EMR    (*(RwReg*)0x400A8068U) /**< \brief (ADC12B) Extended Mode Register */
+#define REG_ADC12B_RPR    (*(RwReg*)0x400A8100U) /**< \brief (ADC12B) Receive Pointer Register */
+#define REG_ADC12B_RCR    (*(RwReg*)0x400A8104U) /**< \brief (ADC12B) Receive Counter Register */
+#define REG_ADC12B_RNPR   (*(RwReg*)0x400A8110U) /**< \brief (ADC12B) Receive Next Pointer Register */
+#define REG_ADC12B_RNCR   (*(RwReg*)0x400A8114U) /**< \brief (ADC12B) Receive Next Counter Register */
+#define REG_ADC12B_PTCR   (*(WoReg*)0x400A8120U) /**< \brief (ADC12B) Transfer Control Register */
+#define REG_ADC12B_PTSR   (*(RoReg*)0x400A8124U) /**< \brief (ADC12B) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_ADC12B_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_chipid.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_chipid.h
new file mode 100644
index 0000000..cce713c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_chipid.h
@@ -0,0 +1,42 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_CHIPID_INSTANCE_
+#define _SAM3U_CHIPID_INSTANCE_
+
+/* ========== Register definition for CHIPID peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CHIPID_CIDR          (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID          (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#else
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_CHIPID_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_dmac.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_dmac.h
new file mode 100644
index 0000000..215505a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_dmac.h
@@ -0,0 +1,114 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_DMAC_INSTANCE_
+#define _SAM3U_DMAC_INSTANCE_
+
+/* ========== Register definition for DMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DMAC_GCFG            (0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */
+#define REG_DMAC_EN              (0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */
+#define REG_DMAC_SREQ            (0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */
+#define REG_DMAC_CREQ            (0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
+#define REG_DMAC_LAST            (0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
+#define REG_DMAC_EBCIER          (0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+#define REG_DMAC_EBCIDR          (0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+#define REG_DMAC_EBCIMR          (0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+#define REG_DMAC_EBCISR          (0x400B0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+#define REG_DMAC_CHER            (0x400B0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
+#define REG_DMAC_CHDR            (0x400B002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
+#define REG_DMAC_CHSR            (0x400B0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
+#define REG_DMAC_SADDR0          (0x400B003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
+#define REG_DMAC_DADDR0          (0x400B0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
+#define REG_DMAC_DSCR0           (0x400B0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
+#define REG_DMAC_CTRLA0          (0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
+#define REG_DMAC_CTRLB0          (0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
+#define REG_DMAC_CFG0            (0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
+#define REG_DMAC_SADDR1          (0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
+#define REG_DMAC_DADDR1          (0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
+#define REG_DMAC_DSCR1           (0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
+#define REG_DMAC_CTRLA1          (0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
+#define REG_DMAC_CTRLB1          (0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
+#define REG_DMAC_CFG1            (0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
+#define REG_DMAC_SADDR2          (0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
+#define REG_DMAC_DADDR2          (0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
+#define REG_DMAC_DSCR2           (0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
+#define REG_DMAC_CTRLA2          (0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
+#define REG_DMAC_CTRLB2          (0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
+#define REG_DMAC_CFG2            (0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
+#define REG_DMAC_SADDR3          (0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
+#define REG_DMAC_DADDR3          (0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
+#define REG_DMAC_DSCR3           (0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
+#define REG_DMAC_CTRLA3          (0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
+#define REG_DMAC_CTRLB3          (0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
+#define REG_DMAC_CFG3            (0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
+#define REG_DMAC_WPMR            (0x400B01E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */
+#define REG_DMAC_WPSR            (0x400B01E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */
+#else
+#define REG_DMAC_GCFG   (*(RwReg*)0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */
+#define REG_DMAC_EN     (*(RwReg*)0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */
+#define REG_DMAC_SREQ   (*(RwReg*)0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */
+#define REG_DMAC_CREQ   (*(RwReg*)0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
+#define REG_DMAC_LAST   (*(RwReg*)0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
+#define REG_DMAC_EBCIER (*(WoReg*)0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+#define REG_DMAC_EBCIDR (*(WoReg*)0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+#define REG_DMAC_EBCIMR (*(RoReg*)0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+#define REG_DMAC_EBCISR (*(RoReg*)0x400B0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+#define REG_DMAC_CHER   (*(WoReg*)0x400B0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
+#define REG_DMAC_CHDR   (*(WoReg*)0x400B002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
+#define REG_DMAC_CHSR   (*(RoReg*)0x400B0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
+#define REG_DMAC_SADDR0 (*(RwReg*)0x400B003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
+#define REG_DMAC_DADDR0 (*(RwReg*)0x400B0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
+#define REG_DMAC_DSCR0  (*(RwReg*)0x400B0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
+#define REG_DMAC_CTRLA0 (*(RwReg*)0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
+#define REG_DMAC_CTRLB0 (*(RwReg*)0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
+#define REG_DMAC_CFG0   (*(RwReg*)0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
+#define REG_DMAC_SADDR1 (*(RwReg*)0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
+#define REG_DMAC_DADDR1 (*(RwReg*)0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
+#define REG_DMAC_DSCR1  (*(RwReg*)0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
+#define REG_DMAC_CTRLA1 (*(RwReg*)0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
+#define REG_DMAC_CTRLB1 (*(RwReg*)0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
+#define REG_DMAC_CFG1   (*(RwReg*)0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
+#define REG_DMAC_SADDR2 (*(RwReg*)0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
+#define REG_DMAC_DADDR2 (*(RwReg*)0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
+#define REG_DMAC_DSCR2  (*(RwReg*)0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
+#define REG_DMAC_CTRLA2 (*(RwReg*)0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
+#define REG_DMAC_CTRLB2 (*(RwReg*)0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
+#define REG_DMAC_CFG2   (*(RwReg*)0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
+#define REG_DMAC_SADDR3 (*(RwReg*)0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
+#define REG_DMAC_DADDR3 (*(RwReg*)0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
+#define REG_DMAC_DSCR3  (*(RwReg*)0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
+#define REG_DMAC_CTRLA3 (*(RwReg*)0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
+#define REG_DMAC_CTRLB3 (*(RwReg*)0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
+#define REG_DMAC_CFG3   (*(RwReg*)0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
+#define REG_DMAC_WPMR   (*(RwReg*)0x400B01E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */
+#define REG_DMAC_WPSR   (*(RoReg*)0x400B01E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_DMAC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_efc0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_efc0.h
new file mode 100644
index 0000000..4069876
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_efc0.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_EFC0_INSTANCE_
+#define _SAM3U_EFC0_INSTANCE_
+
+/* ========== Register definition for EFC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EFC0_FMR           (0x400E0800U) /**< \brief (EFC0) EEFC Flash Mode Register */
+#define REG_EFC0_FCR           (0x400E0804U) /**< \brief (EFC0) EEFC Flash Command Register */
+#define REG_EFC0_FSR           (0x400E0808U) /**< \brief (EFC0) EEFC Flash Status Register */
+#define REG_EFC0_FRR           (0x400E080CU) /**< \brief (EFC0) EEFC Flash Result Register */
+#else
+#define REG_EFC0_FMR  (*(RwReg*)0x400E0800U) /**< \brief (EFC0) EEFC Flash Mode Register */
+#define REG_EFC0_FCR  (*(WoReg*)0x400E0804U) /**< \brief (EFC0) EEFC Flash Command Register */
+#define REG_EFC0_FSR  (*(RoReg*)0x400E0808U) /**< \brief (EFC0) EEFC Flash Status Register */
+#define REG_EFC0_FRR  (*(RoReg*)0x400E080CU) /**< \brief (EFC0) EEFC Flash Result Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_EFC0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_efc1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_efc1.h
new file mode 100644
index 0000000..cc15aba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_efc1.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_EFC1_INSTANCE_
+#define _SAM3U_EFC1_INSTANCE_
+
+/* ========== Register definition for EFC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EFC1_FMR           (0x400E0A00U) /**< \brief (EFC1) EEFC Flash Mode Register */
+#define REG_EFC1_FCR           (0x400E0A04U) /**< \brief (EFC1) EEFC Flash Command Register */
+#define REG_EFC1_FSR           (0x400E0A08U) /**< \brief (EFC1) EEFC Flash Status Register */
+#define REG_EFC1_FRR           (0x400E0A0CU) /**< \brief (EFC1) EEFC Flash Result Register */
+#else
+#define REG_EFC1_FMR  (*(RwReg*)0x400E0A00U) /**< \brief (EFC1) EEFC Flash Mode Register */
+#define REG_EFC1_FCR  (*(WoReg*)0x400E0A04U) /**< \brief (EFC1) EEFC Flash Command Register */
+#define REG_EFC1_FSR  (*(RoReg*)0x400E0A08U) /**< \brief (EFC1) EEFC Flash Status Register */
+#define REG_EFC1_FRR  (*(RoReg*)0x400E0A0CU) /**< \brief (EFC1) EEFC Flash Result Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_EFC1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_gpbr.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_gpbr.h
new file mode 100644
index 0000000..a17e51e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_gpbr.h
@@ -0,0 +1,40 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_GPBR_INSTANCE_
+#define _SAM3U_GPBR_INSTANCE_
+
+/* ========== Register definition for GPBR peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GPBR_GPBR            (0x400E1290U) /**< \brief (GPBR) General Purpose Backup Register */
+#else
+#define REG_GPBR_GPBR   (*(RwReg*)0x400E1290U) /**< \brief (GPBR) General Purpose Backup Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_GPBR_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_hsmci.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_hsmci.h
new file mode 100644
index 0000000..3386268
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_hsmci.h
@@ -0,0 +1,78 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_HSMCI_INSTANCE_
+#define _SAM3U_HSMCI_INSTANCE_
+
+/* ========== Register definition for HSMCI peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_HSMCI_CR                 (0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR                 (0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR               (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR               (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR               (0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR               (0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR               (0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR              (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR               (0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR                (0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR                (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR                 (0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER                (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR                (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR                (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_DMA                (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
+#define REG_HSMCI_CFG                (0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR               (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR               (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_FIFO               (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#else
+#define REG_HSMCI_CR        (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR        (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR      (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR      (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR      (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR      (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR      (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR     (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR      (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR       (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR       (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR        (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER       (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR       (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR       (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_DMA       (*(RwReg*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
+#define REG_HSMCI_CFG       (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR      (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR      (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_FIFO      (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_HSMCI_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_matrix.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_matrix.h
new file mode 100644
index 0000000..e7b1ed4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_matrix.h
@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_MATRIX_INSTANCE_
+#define _SAM3U_MATRIX_INSTANCE_
+
+/* ========== Register definition for MATRIX peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MATRIX_MCFG              (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG              (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0             (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1             (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2             (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3             (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4             (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_MATRIX_PRAS5             (0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
+#define REG_MATRIX_PRAS6             (0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
+#define REG_MATRIX_PRAS7             (0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
+#define REG_MATRIX_PRAS8             (0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
+#define REG_MATRIX_PRAS9             (0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
+#define REG_MATRIX_MRCR              (0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */
+#define REG_MATRIX_WPMR              (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR              (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#else
+#define REG_MATRIX_MCFG     (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG     (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0    (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1    (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2    (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3    (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4    (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_MATRIX_PRAS5    (*(RwReg*)0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
+#define REG_MATRIX_PRAS6    (*(RwReg*)0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
+#define REG_MATRIX_PRAS7    (*(RwReg*)0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
+#define REG_MATRIX_PRAS8    (*(RwReg*)0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
+#define REG_MATRIX_PRAS9    (*(RwReg*)0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
+#define REG_MATRIX_MRCR     (*(RwReg*)0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */
+#define REG_MATRIX_WPMR     (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR     (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_MATRIX_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_pioa.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_pioa.h
new file mode 100644
index 0000000..0915729
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_pioa.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PIOA_INSTANCE_
+#define _SAM3U_PIOA_INSTANCE_
+
+/* ========== Register definition for PIOA peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOA_PER             (0x400E0C00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR             (0x400E0C04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR             (0x400E0C08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER             (0x400E0C10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR             (0x400E0C14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR             (0x400E0C18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER            (0x400E0C20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR            (0x400E0C24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR            (0x400E0C28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR            (0x400E0C30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR            (0x400E0C34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR            (0x400E0C38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR            (0x400E0C3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER             (0x400E0C40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR             (0x400E0C44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR             (0x400E0C48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR             (0x400E0C4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER            (0x400E0C50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR            (0x400E0C54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR            (0x400E0C58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR            (0x400E0C60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER            (0x400E0C64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR            (0x400E0C68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABSR            (0x400E0C70U) /**< \brief (PIOA) Peripheral AB Select Register */
+#define REG_PIOA_SCIFSR          (0x400E0C80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
+#define REG_PIOA_DIFSR           (0x400E0C84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
+#define REG_PIOA_IFDGSR          (0x400E0C88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOA_SCDR            (0x400E0C8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_OWER            (0x400E0CA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR            (0x400E0CA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR            (0x400E0CA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER           (0x400E0CB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR           (0x400E0CB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR           (0x400E0CB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR             (0x400E0CC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR             (0x400E0CC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR            (0x400E0CC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR          (0x400E0CD0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR          (0x400E0CD4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR          (0x400E0CD8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR          (0x400E0CE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR            (0x400E0CE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR            (0x400E0CE8U) /**< \brief (PIOA) Write Protect Status Register */
+#else
+#define REG_PIOA_PER    (*(WoReg*)0x400E0C00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR    (*(WoReg*)0x400E0C04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR    (*(RoReg*)0x400E0C08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER    (*(WoReg*)0x400E0C10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR    (*(WoReg*)0x400E0C14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR    (*(RoReg*)0x400E0C18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER   (*(WoReg*)0x400E0C20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR   (*(WoReg*)0x400E0C24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR   (*(RoReg*)0x400E0C28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR   (*(WoReg*)0x400E0C30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR   (*(WoReg*)0x400E0C34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR   (*(RwReg*)0x400E0C38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR   (*(RoReg*)0x400E0C3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER    (*(WoReg*)0x400E0C40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR    (*(WoReg*)0x400E0C44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR    (*(RoReg*)0x400E0C48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR    (*(RoReg*)0x400E0C4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER   (*(WoReg*)0x400E0C50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR   (*(WoReg*)0x400E0C54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR   (*(RoReg*)0x400E0C58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR   (*(WoReg*)0x400E0C60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER   (*(WoReg*)0x400E0C64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR   (*(RoReg*)0x400E0C68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABSR   (*(RwReg*)0x400E0C70U) /**< \brief (PIOA) Peripheral AB Select Register */
+#define REG_PIOA_SCIFSR (*(WoReg*)0x400E0C80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
+#define REG_PIOA_DIFSR  (*(WoReg*)0x400E0C84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
+#define REG_PIOA_IFDGSR (*(RoReg*)0x400E0C88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOA_SCDR   (*(RwReg*)0x400E0C8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_OWER   (*(WoReg*)0x400E0CA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR   (*(WoReg*)0x400E0CA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR   (*(RoReg*)0x400E0CA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER  (*(WoReg*)0x400E0CB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR  (*(WoReg*)0x400E0CB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR  (*(RoReg*)0x400E0CB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR    (*(WoReg*)0x400E0CC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR    (*(WoReg*)0x400E0CC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR   (*(RoReg*)0x400E0CC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR (*(WoReg*)0x400E0CD0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR (*(WoReg*)0x400E0CD4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0CD8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0CE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR   (*(RwReg*)0x400E0CE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR   (*(RoReg*)0x400E0CE8U) /**< \brief (PIOA) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_PIOA_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_piob.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_piob.h
new file mode 100644
index 0000000..b374aba
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_piob.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PIOB_INSTANCE_
+#define _SAM3U_PIOB_INSTANCE_
+
+/* ========== Register definition for PIOB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOB_PER             (0x400E0E00U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR             (0x400E0E04U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR             (0x400E0E08U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER             (0x400E0E10U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR             (0x400E0E14U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR             (0x400E0E18U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER            (0x400E0E20U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR            (0x400E0E24U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR            (0x400E0E28U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR            (0x400E0E30U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR            (0x400E0E34U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR            (0x400E0E38U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR            (0x400E0E3CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER             (0x400E0E40U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR             (0x400E0E44U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR             (0x400E0E48U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR             (0x400E0E4CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER            (0x400E0E50U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR            (0x400E0E54U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR            (0x400E0E58U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR            (0x400E0E60U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER            (0x400E0E64U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR            (0x400E0E68U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABSR            (0x400E0E70U) /**< \brief (PIOB) Peripheral AB Select Register */
+#define REG_PIOB_SCIFSR          (0x400E0E80U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
+#define REG_PIOB_DIFSR           (0x400E0E84U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
+#define REG_PIOB_IFDGSR          (0x400E0E88U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOB_SCDR            (0x400E0E8CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_OWER            (0x400E0EA0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR            (0x400E0EA4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR            (0x400E0EA8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER           (0x400E0EB0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR           (0x400E0EB4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR           (0x400E0EB8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR             (0x400E0EC0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR             (0x400E0EC4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR            (0x400E0EC8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR          (0x400E0ED0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR          (0x400E0ED4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR          (0x400E0ED8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR          (0x400E0EE0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR            (0x400E0EE4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR            (0x400E0EE8U) /**< \brief (PIOB) Write Protect Status Register */
+#else
+#define REG_PIOB_PER    (*(WoReg*)0x400E0E00U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR    (*(WoReg*)0x400E0E04U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR    (*(RoReg*)0x400E0E08U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER    (*(WoReg*)0x400E0E10U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR    (*(WoReg*)0x400E0E14U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR    (*(RoReg*)0x400E0E18U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER   (*(WoReg*)0x400E0E20U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR   (*(WoReg*)0x400E0E24U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR   (*(RoReg*)0x400E0E28U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR   (*(WoReg*)0x400E0E30U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR   (*(WoReg*)0x400E0E34U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR   (*(RwReg*)0x400E0E38U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR   (*(RoReg*)0x400E0E3CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER    (*(WoReg*)0x400E0E40U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR    (*(WoReg*)0x400E0E44U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR    (*(RoReg*)0x400E0E48U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR    (*(RoReg*)0x400E0E4CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER   (*(WoReg*)0x400E0E50U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR   (*(WoReg*)0x400E0E54U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR   (*(RoReg*)0x400E0E58U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR   (*(WoReg*)0x400E0E60U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER   (*(WoReg*)0x400E0E64U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR   (*(RoReg*)0x400E0E68U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABSR   (*(RwReg*)0x400E0E70U) /**< \brief (PIOB) Peripheral AB Select Register */
+#define REG_PIOB_SCIFSR (*(WoReg*)0x400E0E80U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
+#define REG_PIOB_DIFSR  (*(WoReg*)0x400E0E84U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
+#define REG_PIOB_IFDGSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOB_SCDR   (*(RwReg*)0x400E0E8CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_OWER   (*(WoReg*)0x400E0EA0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR   (*(WoReg*)0x400E0EA4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR   (*(RoReg*)0x400E0EA8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER  (*(WoReg*)0x400E0EB0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR  (*(WoReg*)0x400E0EB4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR  (*(RoReg*)0x400E0EB8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR    (*(WoReg*)0x400E0EC0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR    (*(WoReg*)0x400E0EC4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR   (*(RoReg*)0x400E0EC8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR   (*(RwReg*)0x400E0EE4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR   (*(RoReg*)0x400E0EE8U) /**< \brief (PIOB) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_PIOB_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_pioc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_pioc.h
new file mode 100644
index 0000000..7f15d4d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_pioc.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PIOC_INSTANCE_
+#define _SAM3U_PIOC_INSTANCE_
+
+/* ========== Register definition for PIOC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOC_PER             (0x400E1000U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR             (0x400E1004U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR             (0x400E1008U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER             (0x400E1010U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR             (0x400E1014U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR             (0x400E1018U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER            (0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR            (0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR            (0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR            (0x400E1030U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR            (0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR            (0x400E1038U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR            (0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER             (0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR             (0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR             (0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR             (0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER            (0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR            (0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR            (0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR            (0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER            (0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR            (0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABSR            (0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */
+#define REG_PIOC_SCIFSR          (0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
+#define REG_PIOC_DIFSR           (0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
+#define REG_PIOC_IFDGSR          (0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOC_SCDR            (0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_OWER            (0x400E10A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR            (0x400E10A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR            (0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER           (0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR           (0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR           (0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR             (0x400E10C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR             (0x400E10C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR            (0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR          (0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR          (0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR          (0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR          (0x400E10E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR            (0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR            (0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */
+#else
+#define REG_PIOC_PER    (*(WoReg*)0x400E1000U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR    (*(WoReg*)0x400E1004U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR    (*(RoReg*)0x400E1008U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER    (*(WoReg*)0x400E1010U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR    (*(WoReg*)0x400E1014U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR    (*(RoReg*)0x400E1018U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER   (*(WoReg*)0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR   (*(WoReg*)0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR   (*(RoReg*)0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR   (*(WoReg*)0x400E1030U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR   (*(WoReg*)0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR   (*(RwReg*)0x400E1038U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR   (*(RoReg*)0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER    (*(WoReg*)0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR    (*(WoReg*)0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR    (*(RoReg*)0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR    (*(RoReg*)0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER   (*(WoReg*)0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR   (*(WoReg*)0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR   (*(RoReg*)0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR   (*(WoReg*)0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER   (*(WoReg*)0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR   (*(RoReg*)0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABSR   (*(RwReg*)0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */
+#define REG_PIOC_SCIFSR (*(WoReg*)0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
+#define REG_PIOC_DIFSR  (*(WoReg*)0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
+#define REG_PIOC_IFDGSR (*(RoReg*)0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOC_SCDR   (*(RwReg*)0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_OWER   (*(WoReg*)0x400E10A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR   (*(WoReg*)0x400E10A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR   (*(RoReg*)0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER  (*(WoReg*)0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR  (*(WoReg*)0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR  (*(RoReg*)0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR    (*(WoReg*)0x400E10C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR    (*(WoReg*)0x400E10C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR   (*(RoReg*)0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR   (*(RwReg*)0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR   (*(RoReg*)0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_PIOC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_pmc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_pmc.h
new file mode 100644
index 0000000..b70066e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_pmc.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PMC_INSTANCE_
+#define _SAM3U_PMC_INSTANCE_
+
+/* ========== Register definition for PMC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PMC_SCER            (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR            (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR            (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0           (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0           (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0           (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_UCKR           (0x400E041CU) /**< \brief (PMC) UTMI Clock Register */
+#define REG_CKGR_MOR            (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR           (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR          (0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR            (0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_PCK             (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER             (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR             (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR              (0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR             (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR            (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR            (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR            (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR            (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR            (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#else
+#define REG_PMC_SCER   (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR   (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR   (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0  (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0  (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0  (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_UCKR  (*(RwReg*)0x400E041CU) /**< \brief (PMC) UTMI Clock Register */
+#define REG_CKGR_MOR   (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR  (*(RoReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR   (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_PCK    (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER    (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR    (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR     (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR    (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR   (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR   (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR   (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR   (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR   (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_PMC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_pwm.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_pwm.h
new file mode 100644
index 0000000..cd0803d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_pwm.h
@@ -0,0 +1,238 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_PWM_INSTANCE_
+#define _SAM3U_PWM_INSTANCE_
+
+/* ========== Register definition for PWM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PWM_CLK               (0x4008C000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA               (0x4008C004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS               (0x4008C008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR                (0x4008C00CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1              (0x4008C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1              (0x4008C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1              (0x4008C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1              (0x4008C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM               (0x4008C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC              (0x4008C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP              (0x4008C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD           (0x4008C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2              (0x4008C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2              (0x4008C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2              (0x4008C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2              (0x4008C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV               (0x4008C044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS                (0x4008C048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS               (0x4008C04CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC               (0x4008C050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD            (0x4008C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD            (0x4008C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR               (0x4008C05CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR               (0x4008C060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR               (0x4008C064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV               (0x4008C068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE               (0x4008C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR              (0x4008C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_WPCR              (0x4008C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR              (0x4008C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_TPR               (0x4008C108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR               (0x4008C10CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_TNPR              (0x4008C118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR              (0x4008C11CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR              (0x4008C120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR              (0x4008C124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0             (0x4008C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0          (0x4008C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0             (0x4008C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0          (0x4008C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1             (0x4008C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1          (0x4008C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1             (0x4008C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1          (0x4008C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2             (0x4008C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2          (0x4008C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2             (0x4008C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2          (0x4008C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3             (0x4008C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3          (0x4008C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3             (0x4008C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3          (0x4008C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4             (0x4008C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4          (0x4008C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4             (0x4008C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4          (0x4008C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5             (0x4008C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5          (0x4008C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5             (0x4008C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5          (0x4008C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6             (0x4008C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6          (0x4008C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6             (0x4008C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6          (0x4008C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7             (0x4008C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7          (0x4008C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7             (0x4008C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7          (0x4008C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0              (0x4008C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0             (0x4008C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0          (0x4008C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0             (0x4008C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0          (0x4008C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0             (0x4008C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0               (0x4008C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0            (0x4008C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1              (0x4008C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1             (0x4008C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1          (0x4008C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1             (0x4008C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1          (0x4008C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1             (0x4008C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1               (0x4008C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1            (0x4008C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2              (0x4008C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2             (0x4008C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2          (0x4008C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2             (0x4008C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2          (0x4008C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2             (0x4008C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2               (0x4008C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2            (0x4008C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3              (0x4008C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3             (0x4008C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3          (0x4008C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3             (0x4008C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3          (0x4008C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3             (0x4008C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3               (0x4008C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3            (0x4008C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#else
+#define REG_PWM_CLK      (*(RwReg*)0x4008C000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA      (*(WoReg*)0x4008C004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS      (*(WoReg*)0x4008C008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR       (*(RoReg*)0x4008C00CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1     (*(WoReg*)0x4008C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1     (*(WoReg*)0x4008C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1     (*(RoReg*)0x4008C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1     (*(RoReg*)0x4008C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM      (*(RwReg*)0x4008C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC     (*(RwReg*)0x4008C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP     (*(RwReg*)0x4008C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD  (*(WoReg*)0x4008C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2     (*(WoReg*)0x4008C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2     (*(WoReg*)0x4008C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2     (*(RoReg*)0x4008C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2     (*(RoReg*)0x4008C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV      (*(RwReg*)0x4008C044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS       (*(RwReg*)0x4008C048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS      (*(WoReg*)0x4008C04CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC      (*(WoReg*)0x4008C050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD   (*(WoReg*)0x4008C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD   (*(WoReg*)0x4008C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR      (*(RwReg*)0x4008C05CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR      (*(RoReg*)0x4008C060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR      (*(WoReg*)0x4008C064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV      (*(RwReg*)0x4008C068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE      (*(RwReg*)0x4008C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR     (*(RwReg*)0x4008C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_WPCR     (*(WoReg*)0x4008C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR     (*(RoReg*)0x4008C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_TPR      (*(RwReg*)0x4008C108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR      (*(RwReg*)0x4008C10CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_TNPR     (*(RwReg*)0x4008C118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR     (*(RwReg*)0x4008C11CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR     (*(WoReg*)0x4008C120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR     (*(RoReg*)0x4008C124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0    (*(RwReg*)0x4008C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x4008C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0    (*(RwReg*)0x4008C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4008C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1    (*(RwReg*)0x4008C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x4008C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1    (*(RwReg*)0x4008C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4008C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2    (*(RwReg*)0x4008C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x4008C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2    (*(RwReg*)0x4008C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4008C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3    (*(RwReg*)0x4008C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x4008C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3    (*(RwReg*)0x4008C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4008C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4    (*(RwReg*)0x4008C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x4008C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4    (*(RwReg*)0x4008C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4008C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5    (*(RwReg*)0x4008C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x4008C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5    (*(RwReg*)0x4008C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4008C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6    (*(RwReg*)0x4008C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x4008C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6    (*(RwReg*)0x4008C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4008C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7    (*(RwReg*)0x4008C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x4008C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7    (*(RwReg*)0x4008C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x4008C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0     (*(RwReg*)0x4008C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0    (*(RwReg*)0x4008C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x4008C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0    (*(RwReg*)0x4008C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x4008C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0    (*(RoReg*)0x4008C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0      (*(RwReg*)0x4008C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0   (*(WoReg*)0x4008C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1     (*(RwReg*)0x4008C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1    (*(RwReg*)0x4008C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x4008C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1    (*(RwReg*)0x4008C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x4008C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1    (*(RoReg*)0x4008C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1      (*(RwReg*)0x4008C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1   (*(WoReg*)0x4008C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2     (*(RwReg*)0x4008C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2    (*(RwReg*)0x4008C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x4008C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2    (*(RwReg*)0x4008C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x4008C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2    (*(RoReg*)0x4008C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2      (*(RwReg*)0x4008C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2   (*(WoReg*)0x4008C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3     (*(RwReg*)0x4008C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3    (*(RwReg*)0x4008C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x4008C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3    (*(RwReg*)0x4008C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x4008C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3    (*(RoReg*)0x4008C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3      (*(RwReg*)0x4008C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3   (*(WoReg*)0x4008C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_PWM_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_rstc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_rstc.h
new file mode 100644
index 0000000..c196fdc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_rstc.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_RSTC_INSTANCE_
+#define _SAM3U_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RSTC_CR          (0x400E1200U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR          (0x400E1204U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR          (0x400E1208U) /**< \brief (RSTC) Mode Register */
+#else
+#define REG_RSTC_CR (*(WoReg*)0x400E1200U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR (*(RoReg*)0x400E1204U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR (*(RwReg*)0x400E1208U) /**< \brief (RSTC) Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_RSTC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_rtc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_rtc.h
new file mode 100644
index 0000000..267fc22
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_rtc.h
@@ -0,0 +1,64 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_RTC_INSTANCE_
+#define _SAM3U_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_CR              (0x400E1260U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR              (0x400E1264U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR            (0x400E1268U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR            (0x400E126CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR          (0x400E1270U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR          (0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR              (0x400E1278U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR            (0x400E127CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER             (0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR             (0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR             (0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER             (0x400E128CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR            (0x400E1344U) /**< \brief (RTC) Write Protect Mode Register */
+#else
+#define REG_RTC_CR     (*(RwReg*)0x400E1260U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR     (*(RwReg*)0x400E1264U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR   (*(RwReg*)0x400E1268U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR   (*(RwReg*)0x400E126CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1270U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR (*(RwReg*)0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR     (*(RoReg*)0x400E1278U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR   (*(WoReg*)0x400E127CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER    (*(WoReg*)0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR    (*(WoReg*)0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR    (*(RoReg*)0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER    (*(RoReg*)0x400E128CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR   (*(RwReg*)0x400E1344U) /**< \brief (RTC) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_RTC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_rtt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_rtt.h
new file mode 100644
index 0000000..69674c3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_rtt.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_RTT_INSTANCE_
+#define _SAM3U_RTT_INSTANCE_
+
+/* ========== Register definition for RTT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTT_MR          (0x400E1230U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR          (0x400E1234U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR          (0x400E1238U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR          (0x400E123CU) /**< \brief (RTT) Status Register */
+#else
+#define REG_RTT_MR (*(RwReg*)0x400E1230U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR (*(RwReg*)0x400E1234U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR (*(RoReg*)0x400E1238U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR (*(RoReg*)0x400E123CU) /**< \brief (RTT) Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_RTT_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_smc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_smc.h
new file mode 100644
index 0000000..bc1dde5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_smc.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SMC_INSTANCE_
+#define _SAM3U_SMC_INSTANCE_
+
+/* ========== Register definition for SMC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SMC_CFG               (0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
+#define REG_SMC_CTRL              (0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
+#define REG_SMC_SR                (0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
+#define REG_SMC_IER               (0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
+#define REG_SMC_IDR               (0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
+#define REG_SMC_IMR               (0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
+#define REG_SMC_ADDR              (0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
+#define REG_SMC_BANK              (0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
+#define REG_SMC_ECC_CTRL          (0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
+#define REG_SMC_ECC_MD            (0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
+#define REG_SMC_ECC_SR1           (0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
+#define REG_SMC_ECC_PR0           (0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
+#define REG_SMC_ECC_PR1           (0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
+#define REG_SMC_ECC_SR2           (0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
+#define REG_SMC_ECC_PR2           (0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
+#define REG_SMC_ECC_PR3           (0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
+#define REG_SMC_ECC_PR4           (0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
+#define REG_SMC_ECC_PR5           (0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
+#define REG_SMC_ECC_PR6           (0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
+#define REG_SMC_ECC_PR7           (0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
+#define REG_SMC_ECC_PR8           (0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
+#define REG_SMC_ECC_PR9           (0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
+#define REG_SMC_ECC_PR10          (0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
+#define REG_SMC_ECC_PR11          (0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
+#define REG_SMC_ECC_PR12          (0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
+#define REG_SMC_ECC_PR13          (0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
+#define REG_SMC_ECC_PR14          (0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
+#define REG_SMC_ECC_PR15          (0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
+#define REG_SMC_SETUP0            (0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0            (0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0            (0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_TIMINGS0          (0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
+#define REG_SMC_MODE0             (0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1            (0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1            (0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1            (0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_TIMINGS1          (0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
+#define REG_SMC_MODE1             (0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2            (0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2            (0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2            (0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_TIMINGS2          (0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
+#define REG_SMC_MODE2             (0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3            (0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3            (0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3            (0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_TIMINGS3          (0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
+#define REG_SMC_MODE3             (0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_OCMS              (0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
+#define REG_SMC_KEY1              (0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2              (0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPCR              (0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
+#define REG_SMC_WPSR              (0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
+#else
+#define REG_SMC_CFG      (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
+#define REG_SMC_CTRL     (*(WoReg*)0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
+#define REG_SMC_SR       (*(RoReg*)0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
+#define REG_SMC_IER      (*(WoReg*)0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
+#define REG_SMC_IDR      (*(WoReg*)0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
+#define REG_SMC_IMR      (*(RoReg*)0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
+#define REG_SMC_ADDR     (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
+#define REG_SMC_BANK     (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
+#define REG_SMC_ECC_CTRL (*(WoReg*)0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
+#define REG_SMC_ECC_MD   (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
+#define REG_SMC_ECC_SR1  (*(RoReg*)0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
+#define REG_SMC_ECC_PR0  (*(RoReg*)0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
+#define REG_SMC_ECC_PR1  (*(RoReg*)0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
+#define REG_SMC_ECC_SR2  (*(RoReg*)0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
+#define REG_SMC_ECC_PR2  (*(RoReg*)0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
+#define REG_SMC_ECC_PR3  (*(RoReg*)0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
+#define REG_SMC_ECC_PR4  (*(RoReg*)0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
+#define REG_SMC_ECC_PR5  (*(RoReg*)0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
+#define REG_SMC_ECC_PR6  (*(RoReg*)0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
+#define REG_SMC_ECC_PR7  (*(RoReg*)0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
+#define REG_SMC_ECC_PR8  (*(RoReg*)0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
+#define REG_SMC_ECC_PR9  (*(RoReg*)0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
+#define REG_SMC_ECC_PR10 (*(RoReg*)0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
+#define REG_SMC_ECC_PR11 (*(RoReg*)0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
+#define REG_SMC_ECC_PR12 (*(RoReg*)0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
+#define REG_SMC_ECC_PR13 (*(RoReg*)0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
+#define REG_SMC_ECC_PR14 (*(RoReg*)0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
+#define REG_SMC_ECC_PR15 (*(RoReg*)0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
+#define REG_SMC_SETUP0   (*(RwReg*)0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0   (*(RwReg*)0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0   (*(RwReg*)0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_TIMINGS0 (*(RwReg*)0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
+#define REG_SMC_MODE0    (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1   (*(RwReg*)0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1   (*(RwReg*)0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1   (*(RwReg*)0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_TIMINGS1 (*(RwReg*)0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
+#define REG_SMC_MODE1    (*(RwReg*)0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2   (*(RwReg*)0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2   (*(RwReg*)0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2   (*(RwReg*)0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_TIMINGS2 (*(RwReg*)0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
+#define REG_SMC_MODE2    (*(RwReg*)0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3   (*(RwReg*)0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3   (*(RwReg*)0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3   (*(RwReg*)0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_TIMINGS3 (*(RwReg*)0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
+#define REG_SMC_MODE3    (*(RwReg*)0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_OCMS     (*(RwReg*)0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
+#define REG_SMC_KEY1     (*(WoReg*)0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2     (*(WoReg*)0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPCR     (*(WoReg*)0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
+#define REG_SMC_WPSR     (*(RoReg*)0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_SMC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_spi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_spi.h
new file mode 100644
index 0000000..0b7faec
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_spi.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SPI_INSTANCE_
+#define _SAM3U_SPI_INSTANCE_
+
+/* ========== Register definition for SPI peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SPI_CR              (0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR              (0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR             (0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR             (0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR              (0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER             (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR             (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR             (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR             (0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR            (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR            (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#else
+#define REG_SPI_CR     (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR     (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR    (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR    (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR     (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER    (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR    (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR    (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR    (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR   (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR   (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_SPI_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_ssc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_ssc.h
new file mode 100644
index 0000000..e7e3004
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_ssc.h
@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SSC_INSTANCE_
+#define _SAM3U_SSC_INSTANCE_
+
+/* ========== Register definition for SSC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SSC_CR            (0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR           (0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR          (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR          (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR          (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR          (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR           (0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR           (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR          (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR          (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R          (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R          (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR            (0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER           (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR           (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR           (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR          (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR          (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#else
+#define REG_SSC_CR   (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR  (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR  (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR  (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR   (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER  (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR  (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR  (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_SSC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_supc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_supc.h
new file mode 100644
index 0000000..44efc8c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_supc.h
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_SUPC_INSTANCE_
+#define _SAM3U_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SUPC_CR            (0x400E1210U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR          (0x400E1214U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR            (0x400E1218U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR          (0x400E121CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR          (0x400E1220U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR            (0x400E1224U) /**< \brief (SUPC) Supply Controller Status Register */
+#else
+#define REG_SUPC_CR   (*(WoReg*)0x400E1210U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1214U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR   (*(RwReg*)0x400E1218U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR (*(RwReg*)0x400E121CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1220U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR   (*(RoReg*)0x400E1224U) /**< \brief (SUPC) Supply Controller Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_SUPC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_tc0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_tc0.h
new file mode 100644
index 0000000..a69b1ae
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_tc0.h
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_TC0_INSTANCE_
+#define _SAM3U_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC0_CCR0          (0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0          (0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_CV0           (0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0           (0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0           (0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0           (0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0           (0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0          (0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0          (0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0          (0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1          (0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1          (0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_CV1           (0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1           (0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1           (0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1           (0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1           (0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1          (0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1          (0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1          (0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2          (0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2          (0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_CV2           (0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2           (0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2           (0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2           (0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2           (0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2          (0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2          (0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2          (0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR           (0x400800C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR           (0x400800C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER          (0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR          (0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR          (0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR          (0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#else
+#define REG_TC0_CCR0 (*(WoReg*)0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0 (*(RwReg*)0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_CV0  (*(RoReg*)0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0  (*(RwReg*)0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0  (*(RwReg*)0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0  (*(RwReg*)0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0  (*(RoReg*)0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0 (*(WoReg*)0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0 (*(WoReg*)0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0 (*(RoReg*)0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1 (*(WoReg*)0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1 (*(RwReg*)0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_CV1  (*(RoReg*)0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1  (*(RwReg*)0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1  (*(RwReg*)0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1  (*(RwReg*)0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1  (*(RoReg*)0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1 (*(WoReg*)0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1 (*(WoReg*)0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1 (*(RoReg*)0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2 (*(WoReg*)0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2 (*(RwReg*)0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_CV2  (*(RoReg*)0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2  (*(RwReg*)0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2  (*(RwReg*)0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2  (*(RwReg*)0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2  (*(RoReg*)0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2 (*(WoReg*)0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2 (*(WoReg*)0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2 (*(RoReg*)0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR  (*(WoReg*)0x400800C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR  (*(RwReg*)0x400800C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER (*(WoReg*)0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR (*(WoReg*)0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR (*(RoReg*)0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR (*(RoReg*)0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_TC0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_twi0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_twi0.h
new file mode 100644
index 0000000..c8b0ed6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_twi0.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_TWI0_INSTANCE_
+#define _SAM3U_TWI0_INSTANCE_
+
+/* ========== Register definition for TWI0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TWI0_CR            (0x40084000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR           (0x40084004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR           (0x40084008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR          (0x4008400CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR          (0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR            (0x40084020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER           (0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR           (0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR           (0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR           (0x40084030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR           (0x40084034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR           (0x40084100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR           (0x40084104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR           (0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR           (0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR          (0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR          (0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR          (0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR          (0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR          (0x40084120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR          (0x40084124U) /**< \brief (TWI0) Transfer Status Register */
+#else
+#define REG_TWI0_CR   (*(WoReg*)0x40084000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR  (*(RwReg*)0x40084004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR  (*(RwReg*)0x40084008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR (*(RwReg*)0x4008400CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR (*(RwReg*)0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR   (*(RoReg*)0x40084020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER  (*(WoReg*)0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR  (*(WoReg*)0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR  (*(RoReg*)0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR  (*(RoReg*)0x40084030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR  (*(WoReg*)0x40084034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR  (*(RwReg*)0x40084100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR  (*(RwReg*)0x40084104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR  (*(RwReg*)0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR  (*(RwReg*)0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR (*(RwReg*)0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR (*(RwReg*)0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR (*(RwReg*)0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR (*(RwReg*)0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR (*(WoReg*)0x40084120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR (*(RoReg*)0x40084124U) /**< \brief (TWI0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_TWI0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_twi1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_twi1.h
new file mode 100644
index 0000000..a430000
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_twi1.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_TWI1_INSTANCE_
+#define _SAM3U_TWI1_INSTANCE_
+
+/* ========== Register definition for TWI1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TWI1_CR            (0x40088000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR           (0x40088004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR           (0x40088008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR          (0x4008800CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR          (0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR            (0x40088020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER           (0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR           (0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR           (0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR           (0x40088030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR           (0x40088034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR           (0x40088100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR           (0x40088104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR           (0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR           (0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR          (0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR          (0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR          (0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR          (0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR          (0x40088120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR          (0x40088124U) /**< \brief (TWI1) Transfer Status Register */
+#else
+#define REG_TWI1_CR   (*(WoReg*)0x40088000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR  (*(RwReg*)0x40088004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR  (*(RwReg*)0x40088008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR (*(RwReg*)0x4008800CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR (*(RwReg*)0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR   (*(RoReg*)0x40088020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER  (*(WoReg*)0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR  (*(WoReg*)0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR  (*(RoReg*)0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR  (*(RoReg*)0x40088030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR  (*(WoReg*)0x40088034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR  (*(RwReg*)0x40088100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR  (*(RwReg*)0x40088104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR  (*(RwReg*)0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR  (*(RwReg*)0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR (*(RwReg*)0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR (*(RwReg*)0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR (*(RwReg*)0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR (*(RwReg*)0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR (*(WoReg*)0x40088120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR (*(RoReg*)0x40088124U) /**< \brief (TWI1) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_TWI1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_uart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_uart.h
new file mode 100644
index 0000000..19ce45f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_uart.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_UART_INSTANCE_
+#define _SAM3U_UART_INSTANCE_
+
+/* ========== Register definition for UART peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UART_CR            (0x400E0600U) /**< \brief (UART) Control Register */
+#define REG_UART_MR            (0x400E0604U) /**< \brief (UART) Mode Register */
+#define REG_UART_IER           (0x400E0608U) /**< \brief (UART) Interrupt Enable Register */
+#define REG_UART_IDR           (0x400E060CU) /**< \brief (UART) Interrupt Disable Register */
+#define REG_UART_IMR           (0x400E0610U) /**< \brief (UART) Interrupt Mask Register */
+#define REG_UART_SR            (0x400E0614U) /**< \brief (UART) Status Register */
+#define REG_UART_RHR           (0x400E0618U) /**< \brief (UART) Receive Holding Register */
+#define REG_UART_THR           (0x400E061CU) /**< \brief (UART) Transmit Holding Register */
+#define REG_UART_BRGR          (0x400E0620U) /**< \brief (UART) Baud Rate Generator Register */
+#define REG_UART_RPR           (0x400E0700U) /**< \brief (UART) Receive Pointer Register */
+#define REG_UART_RCR           (0x400E0704U) /**< \brief (UART) Receive Counter Register */
+#define REG_UART_TPR           (0x400E0708U) /**< \brief (UART) Transmit Pointer Register */
+#define REG_UART_TCR           (0x400E070CU) /**< \brief (UART) Transmit Counter Register */
+#define REG_UART_RNPR          (0x400E0710U) /**< \brief (UART) Receive Next Pointer Register */
+#define REG_UART_RNCR          (0x400E0714U) /**< \brief (UART) Receive Next Counter Register */
+#define REG_UART_TNPR          (0x400E0718U) /**< \brief (UART) Transmit Next Pointer Register */
+#define REG_UART_TNCR          (0x400E071CU) /**< \brief (UART) Transmit Next Counter Register */
+#define REG_UART_PTCR          (0x400E0720U) /**< \brief (UART) Transfer Control Register */
+#define REG_UART_PTSR          (0x400E0724U) /**< \brief (UART) Transfer Status Register */
+#else
+#define REG_UART_CR   (*(WoReg*)0x400E0600U) /**< \brief (UART) Control Register */
+#define REG_UART_MR   (*(RwReg*)0x400E0604U) /**< \brief (UART) Mode Register */
+#define REG_UART_IER  (*(WoReg*)0x400E0608U) /**< \brief (UART) Interrupt Enable Register */
+#define REG_UART_IDR  (*(WoReg*)0x400E060CU) /**< \brief (UART) Interrupt Disable Register */
+#define REG_UART_IMR  (*(RoReg*)0x400E0610U) /**< \brief (UART) Interrupt Mask Register */
+#define REG_UART_SR   (*(RoReg*)0x400E0614U) /**< \brief (UART) Status Register */
+#define REG_UART_RHR  (*(RoReg*)0x400E0618U) /**< \brief (UART) Receive Holding Register */
+#define REG_UART_THR  (*(WoReg*)0x400E061CU) /**< \brief (UART) Transmit Holding Register */
+#define REG_UART_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART) Baud Rate Generator Register */
+#define REG_UART_RPR  (*(RwReg*)0x400E0700U) /**< \brief (UART) Receive Pointer Register */
+#define REG_UART_RCR  (*(RwReg*)0x400E0704U) /**< \brief (UART) Receive Counter Register */
+#define REG_UART_TPR  (*(RwReg*)0x400E0708U) /**< \brief (UART) Transmit Pointer Register */
+#define REG_UART_TCR  (*(RwReg*)0x400E070CU) /**< \brief (UART) Transmit Counter Register */
+#define REG_UART_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART) Receive Next Pointer Register */
+#define REG_UART_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART) Receive Next Counter Register */
+#define REG_UART_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART) Transmit Next Pointer Register */
+#define REG_UART_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART) Transmit Next Counter Register */
+#define REG_UART_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART) Transfer Control Register */
+#define REG_UART_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_UART_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_udphs.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_udphs.h
new file mode 100644
index 0000000..cfbcd21
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_udphs.h
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_UDPHS_INSTANCE_
+#define _SAM3U_UDPHS_INSTANCE_
+
+/* ========== Register definition for UDPHS peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UDPHS_CTRL                 (0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */
+#define REG_UDPHS_FNUM                 (0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */
+#define REG_UDPHS_IEN                  (0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */
+#define REG_UDPHS_INTSTA               (0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */
+#define REG_UDPHS_CLRINT               (0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */
+#define REG_UDPHS_EPTRST               (0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */
+#define REG_UDPHS_TST                  (0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */
+#define REG_UDPHS_IPNAME1              (0x400A40F0U) /**< \brief (UDPHS) UDPHS Name1 Register */
+#define REG_UDPHS_IPNAME2              (0x400A40F4U) /**< \brief (UDPHS) UDPHS Name2 Register */
+#define REG_UDPHS_IPFEATURES           (0x400A40F8U) /**< \brief (UDPHS) UDPHS Features Register */
+#define REG_UDPHS_EPTCFG0              (0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */
+#define REG_UDPHS_EPTCTLENB0           (0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */
+#define REG_UDPHS_EPTCTLDIS0           (0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */
+#define REG_UDPHS_EPTCTL0              (0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */
+#define REG_UDPHS_EPTSETSTA0           (0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */
+#define REG_UDPHS_EPTCLRSTA0           (0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */
+#define REG_UDPHS_EPTSTA0              (0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */
+#define REG_UDPHS_EPTCFG1              (0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */
+#define REG_UDPHS_EPTCTLENB1           (0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */
+#define REG_UDPHS_EPTCTLDIS1           (0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */
+#define REG_UDPHS_EPTCTL1              (0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */
+#define REG_UDPHS_EPTSETSTA1           (0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */
+#define REG_UDPHS_EPTCLRSTA1           (0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */
+#define REG_UDPHS_EPTSTA1              (0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */
+#define REG_UDPHS_EPTCFG2              (0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */
+#define REG_UDPHS_EPTCTLENB2           (0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */
+#define REG_UDPHS_EPTCTLDIS2           (0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */
+#define REG_UDPHS_EPTCTL2              (0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */
+#define REG_UDPHS_EPTSETSTA2           (0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */
+#define REG_UDPHS_EPTCLRSTA2           (0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */
+#define REG_UDPHS_EPTSTA2              (0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */
+#define REG_UDPHS_EPTCFG3              (0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */
+#define REG_UDPHS_EPTCTLENB3           (0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */
+#define REG_UDPHS_EPTCTLDIS3           (0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */
+#define REG_UDPHS_EPTCTL3              (0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */
+#define REG_UDPHS_EPTSETSTA3           (0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */
+#define REG_UDPHS_EPTCLRSTA3           (0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */
+#define REG_UDPHS_EPTSTA3              (0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */
+#define REG_UDPHS_EPTCFG4              (0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */
+#define REG_UDPHS_EPTCTLENB4           (0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */
+#define REG_UDPHS_EPTCTLDIS4           (0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */
+#define REG_UDPHS_EPTCTL4              (0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */
+#define REG_UDPHS_EPTSETSTA4           (0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */
+#define REG_UDPHS_EPTCLRSTA4           (0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */
+#define REG_UDPHS_EPTSTA4              (0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */
+#define REG_UDPHS_EPTCFG5              (0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */
+#define REG_UDPHS_EPTCTLENB5           (0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */
+#define REG_UDPHS_EPTCTLDIS5           (0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */
+#define REG_UDPHS_EPTCTL5              (0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */
+#define REG_UDPHS_EPTSETSTA5           (0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */
+#define REG_UDPHS_EPTCLRSTA5           (0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */
+#define REG_UDPHS_EPTSTA5              (0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */
+#define REG_UDPHS_EPTCFG6              (0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */
+#define REG_UDPHS_EPTCTLENB6           (0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */
+#define REG_UDPHS_EPTCTLDIS6           (0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */
+#define REG_UDPHS_EPTCTL6              (0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */
+#define REG_UDPHS_EPTSETSTA6           (0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */
+#define REG_UDPHS_EPTCLRSTA6           (0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */
+#define REG_UDPHS_EPTSTA6              (0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */
+#define REG_UDPHS_DMANXTDSC0           (0x400A4300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */
+#define REG_UDPHS_DMAADDRESS0          (0x400A4304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */
+#define REG_UDPHS_DMACONTROL0          (0x400A4308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */
+#define REG_UDPHS_DMASTATUS0           (0x400A430CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */
+#define REG_UDPHS_DMANXTDSC1           (0x400A4310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */
+#define REG_UDPHS_DMAADDRESS1          (0x400A4314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */
+#define REG_UDPHS_DMACONTROL1          (0x400A4318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */
+#define REG_UDPHS_DMASTATUS1           (0x400A431CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */
+#define REG_UDPHS_DMANXTDSC2           (0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */
+#define REG_UDPHS_DMAADDRESS2          (0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */
+#define REG_UDPHS_DMACONTROL2          (0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */
+#define REG_UDPHS_DMASTATUS2           (0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */
+#define REG_UDPHS_DMANXTDSC3           (0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */
+#define REG_UDPHS_DMAADDRESS3          (0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */
+#define REG_UDPHS_DMACONTROL3          (0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */
+#define REG_UDPHS_DMASTATUS3           (0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */
+#define REG_UDPHS_DMANXTDSC4           (0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */
+#define REG_UDPHS_DMAADDRESS4          (0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */
+#define REG_UDPHS_DMACONTROL4          (0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */
+#define REG_UDPHS_DMASTATUS4           (0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */
+#define REG_UDPHS_DMANXTDSC5           (0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */
+#define REG_UDPHS_DMAADDRESS5          (0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */
+#define REG_UDPHS_DMACONTROL5          (0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */
+#define REG_UDPHS_DMASTATUS5           (0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */
+#else
+#define REG_UDPHS_CTRL        (*(RwReg*)0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */
+#define REG_UDPHS_FNUM        (*(RoReg*)0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */
+#define REG_UDPHS_IEN         (*(RwReg*)0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */
+#define REG_UDPHS_INTSTA      (*(RoReg*)0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */
+#define REG_UDPHS_CLRINT      (*(WoReg*)0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */
+#define REG_UDPHS_EPTRST      (*(WoReg*)0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */
+#define REG_UDPHS_TST         (*(RwReg*)0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */
+#define REG_UDPHS_IPNAME1     (*(RoReg*)0x400A40F0U) /**< \brief (UDPHS) UDPHS Name1 Register */
+#define REG_UDPHS_IPNAME2     (*(RoReg*)0x400A40F4U) /**< \brief (UDPHS) UDPHS Name2 Register */
+#define REG_UDPHS_IPFEATURES  (*(RoReg*)0x400A40F8U) /**< \brief (UDPHS) UDPHS Features Register */
+#define REG_UDPHS_EPTCFG0     (*(RwReg*)0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */
+#define REG_UDPHS_EPTCTLENB0  (*(WoReg*)0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */
+#define REG_UDPHS_EPTCTLDIS0  (*(WoReg*)0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */
+#define REG_UDPHS_EPTCTL0     (*(RoReg*)0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */
+#define REG_UDPHS_EPTSETSTA0  (*(WoReg*)0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */
+#define REG_UDPHS_EPTCLRSTA0  (*(WoReg*)0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */
+#define REG_UDPHS_EPTSTA0     (*(RoReg*)0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */
+#define REG_UDPHS_EPTCFG1     (*(RwReg*)0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */
+#define REG_UDPHS_EPTCTLENB1  (*(WoReg*)0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */
+#define REG_UDPHS_EPTCTLDIS1  (*(WoReg*)0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */
+#define REG_UDPHS_EPTCTL1     (*(RoReg*)0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */
+#define REG_UDPHS_EPTSETSTA1  (*(WoReg*)0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */
+#define REG_UDPHS_EPTCLRSTA1  (*(WoReg*)0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */
+#define REG_UDPHS_EPTSTA1     (*(RoReg*)0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */
+#define REG_UDPHS_EPTCFG2     (*(RwReg*)0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */
+#define REG_UDPHS_EPTCTLENB2  (*(WoReg*)0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */
+#define REG_UDPHS_EPTCTLDIS2  (*(WoReg*)0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */
+#define REG_UDPHS_EPTCTL2     (*(RoReg*)0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */
+#define REG_UDPHS_EPTSETSTA2  (*(WoReg*)0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */
+#define REG_UDPHS_EPTCLRSTA2  (*(WoReg*)0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */
+#define REG_UDPHS_EPTSTA2     (*(RoReg*)0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */
+#define REG_UDPHS_EPTCFG3     (*(RwReg*)0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */
+#define REG_UDPHS_EPTCTLENB3  (*(WoReg*)0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */
+#define REG_UDPHS_EPTCTLDIS3  (*(WoReg*)0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */
+#define REG_UDPHS_EPTCTL3     (*(RoReg*)0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */
+#define REG_UDPHS_EPTSETSTA3  (*(WoReg*)0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */
+#define REG_UDPHS_EPTCLRSTA3  (*(WoReg*)0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */
+#define REG_UDPHS_EPTSTA3     (*(RoReg*)0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */
+#define REG_UDPHS_EPTCFG4     (*(RwReg*)0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */
+#define REG_UDPHS_EPTCTLENB4  (*(WoReg*)0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */
+#define REG_UDPHS_EPTCTLDIS4  (*(WoReg*)0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */
+#define REG_UDPHS_EPTCTL4     (*(RoReg*)0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */
+#define REG_UDPHS_EPTSETSTA4  (*(WoReg*)0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */
+#define REG_UDPHS_EPTCLRSTA4  (*(WoReg*)0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */
+#define REG_UDPHS_EPTSTA4     (*(RoReg*)0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */
+#define REG_UDPHS_EPTCFG5     (*(RwReg*)0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */
+#define REG_UDPHS_EPTCTLENB5  (*(WoReg*)0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */
+#define REG_UDPHS_EPTCTLDIS5  (*(WoReg*)0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */
+#define REG_UDPHS_EPTCTL5     (*(RoReg*)0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */
+#define REG_UDPHS_EPTSETSTA5  (*(WoReg*)0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */
+#define REG_UDPHS_EPTCLRSTA5  (*(WoReg*)0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */
+#define REG_UDPHS_EPTSTA5     (*(RoReg*)0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */
+#define REG_UDPHS_EPTCFG6     (*(RwReg*)0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */
+#define REG_UDPHS_EPTCTLENB6  (*(WoReg*)0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */
+#define REG_UDPHS_EPTCTLDIS6  (*(WoReg*)0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */
+#define REG_UDPHS_EPTCTL6     (*(RoReg*)0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */
+#define REG_UDPHS_EPTSETSTA6  (*(WoReg*)0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */
+#define REG_UDPHS_EPTCLRSTA6  (*(WoReg*)0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */
+#define REG_UDPHS_EPTSTA6     (*(RoReg*)0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */
+#define REG_UDPHS_DMANXTDSC0  (*(RwReg*)0x400A4300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */
+#define REG_UDPHS_DMAADDRESS0 (*(RwReg*)0x400A4304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */
+#define REG_UDPHS_DMACONTROL0 (*(RwReg*)0x400A4308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */
+#define REG_UDPHS_DMASTATUS0  (*(RwReg*)0x400A430CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */
+#define REG_UDPHS_DMANXTDSC1  (*(RwReg*)0x400A4310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */
+#define REG_UDPHS_DMAADDRESS1 (*(RwReg*)0x400A4314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */
+#define REG_UDPHS_DMACONTROL1 (*(RwReg*)0x400A4318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */
+#define REG_UDPHS_DMASTATUS1  (*(RwReg*)0x400A431CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */
+#define REG_UDPHS_DMANXTDSC2  (*(RwReg*)0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */
+#define REG_UDPHS_DMAADDRESS2 (*(RwReg*)0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */
+#define REG_UDPHS_DMACONTROL2 (*(RwReg*)0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */
+#define REG_UDPHS_DMASTATUS2  (*(RwReg*)0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */
+#define REG_UDPHS_DMANXTDSC3  (*(RwReg*)0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */
+#define REG_UDPHS_DMAADDRESS3 (*(RwReg*)0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */
+#define REG_UDPHS_DMACONTROL3 (*(RwReg*)0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */
+#define REG_UDPHS_DMASTATUS3  (*(RwReg*)0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */
+#define REG_UDPHS_DMANXTDSC4  (*(RwReg*)0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */
+#define REG_UDPHS_DMAADDRESS4 (*(RwReg*)0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */
+#define REG_UDPHS_DMACONTROL4 (*(RwReg*)0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */
+#define REG_UDPHS_DMASTATUS4  (*(RwReg*)0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */
+#define REG_UDPHS_DMANXTDSC5  (*(RwReg*)0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */
+#define REG_UDPHS_DMAADDRESS5 (*(RwReg*)0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */
+#define REG_UDPHS_DMACONTROL5 (*(RwReg*)0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */
+#define REG_UDPHS_DMASTATUS5  (*(RwReg*)0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_UDPHS_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_usart0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_usart0.h
new file mode 100644
index 0000000..b41d877
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_usart0.h
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_USART0_INSTANCE_
+#define _SAM3U_USART0_INSTANCE_
+
+/* ========== Register definition for USART0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART0_CR          (0x40090000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR          (0x40090004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER          (0x40090008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR          (0x4009000CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR          (0x40090010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR          (0x40090014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR          (0x40090018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR          (0x4009001CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR          (0x40090020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR          (0x40090024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR          (0x40090028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI          (0x40090040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER          (0x40090044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF          (0x4009004CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN          (0x40090050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR          (0x400900E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR          (0x400900E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_RPR          (0x40090100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR          (0x40090104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR          (0x40090108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR          (0x4009010CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR          (0x40090110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR          (0x40090114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR          (0x40090118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR          (0x4009011CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR          (0x40090120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR          (0x40090124U) /**< \brief (USART0) Transfer Status Register */
+#else
+#define REG_USART0_CR (*(WoReg*)0x40090000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR (*(RwReg*)0x40090004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER (*(WoReg*)0x40090008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR (*(WoReg*)0x4009000CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR (*(RoReg*)0x40090010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR (*(RoReg*)0x40090014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR (*(RoReg*)0x40090018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR (*(WoReg*)0x4009001CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR (*(RwReg*)0x40090020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR (*(RwReg*)0x40090024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR (*(RwReg*)0x40090028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI (*(RwReg*)0x40090040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER (*(RoReg*)0x40090044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF (*(RwReg*)0x4009004CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN (*(RwReg*)0x40090050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR (*(RwReg*)0x400900E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR (*(RoReg*)0x400900E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_RPR (*(RwReg*)0x40090100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR (*(RwReg*)0x40090104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR (*(RwReg*)0x40090108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR (*(RwReg*)0x4009010CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR (*(RwReg*)0x40090110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR (*(RwReg*)0x40090114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR (*(RwReg*)0x40090118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR (*(RwReg*)0x4009011CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR (*(WoReg*)0x40090120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR (*(RoReg*)0x40090124U) /**< \brief (USART0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_USART0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_usart1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_usart1.h
new file mode 100644
index 0000000..ecf9c6c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_usart1.h
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_USART1_INSTANCE_
+#define _SAM3U_USART1_INSTANCE_
+
+/* ========== Register definition for USART1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART1_CR          (0x40094000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR          (0x40094004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER          (0x40094008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR          (0x4009400CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR          (0x40094010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR          (0x40094014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR          (0x40094018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR          (0x4009401CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR          (0x40094020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR          (0x40094024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR          (0x40094028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI          (0x40094040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER          (0x40094044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF          (0x4009404CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN          (0x40094050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR          (0x400940E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR          (0x400940E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_RPR          (0x40094100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR          (0x40094104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR          (0x40094108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR          (0x4009410CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR          (0x40094110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR          (0x40094114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR          (0x40094118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR          (0x4009411CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR          (0x40094120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR          (0x40094124U) /**< \brief (USART1) Transfer Status Register */
+#else
+#define REG_USART1_CR (*(WoReg*)0x40094000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR (*(RwReg*)0x40094004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER (*(WoReg*)0x40094008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR (*(WoReg*)0x4009400CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR (*(RoReg*)0x40094010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR (*(RoReg*)0x40094014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR (*(RoReg*)0x40094018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR (*(WoReg*)0x4009401CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR (*(RwReg*)0x40094020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR (*(RwReg*)0x40094024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR (*(RwReg*)0x40094028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI (*(RwReg*)0x40094040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER (*(RoReg*)0x40094044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF (*(RwReg*)0x4009404CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN (*(RwReg*)0x40094050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR (*(RwReg*)0x400940E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR (*(RoReg*)0x400940E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_RPR (*(RwReg*)0x40094100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR (*(RwReg*)0x40094104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR (*(RwReg*)0x40094108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR (*(RwReg*)0x4009410CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR (*(RwReg*)0x40094110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR (*(RwReg*)0x40094114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR (*(RwReg*)0x40094118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR (*(RwReg*)0x4009411CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR (*(WoReg*)0x40094120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR (*(RoReg*)0x40094124U) /**< \brief (USART1) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_USART1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_usart2.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_usart2.h
new file mode 100644
index 0000000..bd1a982
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_usart2.h
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_USART2_INSTANCE_
+#define _SAM3U_USART2_INSTANCE_
+
+/* ========== Register definition for USART2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART2_CR          (0x40098000U) /**< \brief (USART2) Control Register */
+#define REG_USART2_MR          (0x40098004U) /**< \brief (USART2) Mode Register */
+#define REG_USART2_IER          (0x40098008U) /**< \brief (USART2) Interrupt Enable Register */
+#define REG_USART2_IDR          (0x4009800CU) /**< \brief (USART2) Interrupt Disable Register */
+#define REG_USART2_IMR          (0x40098010U) /**< \brief (USART2) Interrupt Mask Register */
+#define REG_USART2_CSR          (0x40098014U) /**< \brief (USART2) Channel Status Register */
+#define REG_USART2_RHR          (0x40098018U) /**< \brief (USART2) Receiver Holding Register */
+#define REG_USART2_THR          (0x4009801CU) /**< \brief (USART2) Transmitter Holding Register */
+#define REG_USART2_BRGR          (0x40098020U) /**< \brief (USART2) Baud Rate Generator Register */
+#define REG_USART2_RTOR          (0x40098024U) /**< \brief (USART2) Receiver Time-out Register */
+#define REG_USART2_TTGR          (0x40098028U) /**< \brief (USART2) Transmitter Timeguard Register */
+#define REG_USART2_FIDI          (0x40098040U) /**< \brief (USART2) FI DI Ratio Register */
+#define REG_USART2_NER          (0x40098044U) /**< \brief (USART2) Number of Errors Register */
+#define REG_USART2_IF          (0x4009804CU) /**< \brief (USART2) IrDA Filter Register */
+#define REG_USART2_MAN          (0x40098050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
+#define REG_USART2_WPMR          (0x400980E4U) /**< \brief (USART2) Write Protect Mode Register */
+#define REG_USART2_WPSR          (0x400980E8U) /**< \brief (USART2) Write Protect Status Register */
+#define REG_USART2_RPR          (0x40098100U) /**< \brief (USART2) Receive Pointer Register */
+#define REG_USART2_RCR          (0x40098104U) /**< \brief (USART2) Receive Counter Register */
+#define REG_USART2_TPR          (0x40098108U) /**< \brief (USART2) Transmit Pointer Register */
+#define REG_USART2_TCR          (0x4009810CU) /**< \brief (USART2) Transmit Counter Register */
+#define REG_USART2_RNPR          (0x40098110U) /**< \brief (USART2) Receive Next Pointer Register */
+#define REG_USART2_RNCR          (0x40098114U) /**< \brief (USART2) Receive Next Counter Register */
+#define REG_USART2_TNPR          (0x40098118U) /**< \brief (USART2) Transmit Next Pointer Register */
+#define REG_USART2_TNCR          (0x4009811CU) /**< \brief (USART2) Transmit Next Counter Register */
+#define REG_USART2_PTCR          (0x40098120U) /**< \brief (USART2) Transfer Control Register */
+#define REG_USART2_PTSR          (0x40098124U) /**< \brief (USART2) Transfer Status Register */
+#else
+#define REG_USART2_CR (*(WoReg*)0x40098000U) /**< \brief (USART2) Control Register */
+#define REG_USART2_MR (*(RwReg*)0x40098004U) /**< \brief (USART2) Mode Register */
+#define REG_USART2_IER (*(WoReg*)0x40098008U) /**< \brief (USART2) Interrupt Enable Register */
+#define REG_USART2_IDR (*(WoReg*)0x4009800CU) /**< \brief (USART2) Interrupt Disable Register */
+#define REG_USART2_IMR (*(RoReg*)0x40098010U) /**< \brief (USART2) Interrupt Mask Register */
+#define REG_USART2_CSR (*(RoReg*)0x40098014U) /**< \brief (USART2) Channel Status Register */
+#define REG_USART2_RHR (*(RoReg*)0x40098018U) /**< \brief (USART2) Receiver Holding Register */
+#define REG_USART2_THR (*(WoReg*)0x4009801CU) /**< \brief (USART2) Transmitter Holding Register */
+#define REG_USART2_BRGR (*(RwReg*)0x40098020U) /**< \brief (USART2) Baud Rate Generator Register */
+#define REG_USART2_RTOR (*(RwReg*)0x40098024U) /**< \brief (USART2) Receiver Time-out Register */
+#define REG_USART2_TTGR (*(RwReg*)0x40098028U) /**< \brief (USART2) Transmitter Timeguard Register */
+#define REG_USART2_FIDI (*(RwReg*)0x40098040U) /**< \brief (USART2) FI DI Ratio Register */
+#define REG_USART2_NER (*(RoReg*)0x40098044U) /**< \brief (USART2) Number of Errors Register */
+#define REG_USART2_IF (*(RwReg*)0x4009804CU) /**< \brief (USART2) IrDA Filter Register */
+#define REG_USART2_MAN (*(RwReg*)0x40098050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
+#define REG_USART2_WPMR (*(RwReg*)0x400980E4U) /**< \brief (USART2) Write Protect Mode Register */
+#define REG_USART2_WPSR (*(RoReg*)0x400980E8U) /**< \brief (USART2) Write Protect Status Register */
+#define REG_USART2_RPR (*(RwReg*)0x40098100U) /**< \brief (USART2) Receive Pointer Register */
+#define REG_USART2_RCR (*(RwReg*)0x40098104U) /**< \brief (USART2) Receive Counter Register */
+#define REG_USART2_TPR (*(RwReg*)0x40098108U) /**< \brief (USART2) Transmit Pointer Register */
+#define REG_USART2_TCR (*(RwReg*)0x4009810CU) /**< \brief (USART2) Transmit Counter Register */
+#define REG_USART2_RNPR (*(RwReg*)0x40098110U) /**< \brief (USART2) Receive Next Pointer Register */
+#define REG_USART2_RNCR (*(RwReg*)0x40098114U) /**< \brief (USART2) Receive Next Counter Register */
+#define REG_USART2_TNPR (*(RwReg*)0x40098118U) /**< \brief (USART2) Transmit Next Pointer Register */
+#define REG_USART2_TNCR (*(RwReg*)0x4009811CU) /**< \brief (USART2) Transmit Next Counter Register */
+#define REG_USART2_PTCR (*(WoReg*)0x40098120U) /**< \brief (USART2) Transfer Control Register */
+#define REG_USART2_PTSR (*(RoReg*)0x40098124U) /**< \brief (USART2) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_USART2_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_usart3.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_usart3.h
new file mode 100644
index 0000000..f832614
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_usart3.h
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_USART3_INSTANCE_
+#define _SAM3U_USART3_INSTANCE_
+
+/* ========== Register definition for USART3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART3_CR          (0x4009C000U) /**< \brief (USART3) Control Register */
+#define REG_USART3_MR          (0x4009C004U) /**< \brief (USART3) Mode Register */
+#define REG_USART3_IER          (0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */
+#define REG_USART3_IDR          (0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */
+#define REG_USART3_IMR          (0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */
+#define REG_USART3_CSR          (0x4009C014U) /**< \brief (USART3) Channel Status Register */
+#define REG_USART3_RHR          (0x4009C018U) /**< \brief (USART3) Receiver Holding Register */
+#define REG_USART3_THR          (0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */
+#define REG_USART3_BRGR          (0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */
+#define REG_USART3_RTOR          (0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */
+#define REG_USART3_TTGR          (0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */
+#define REG_USART3_FIDI          (0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */
+#define REG_USART3_NER          (0x4009C044U) /**< \brief (USART3) Number of Errors Register */
+#define REG_USART3_IF          (0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */
+#define REG_USART3_MAN          (0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
+#define REG_USART3_WPMR          (0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */
+#define REG_USART3_WPSR          (0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */
+#define REG_USART3_RPR          (0x4009C100U) /**< \brief (USART3) Receive Pointer Register */
+#define REG_USART3_RCR          (0x4009C104U) /**< \brief (USART3) Receive Counter Register */
+#define REG_USART3_TPR          (0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */
+#define REG_USART3_TCR          (0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */
+#define REG_USART3_RNPR          (0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */
+#define REG_USART3_RNCR          (0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */
+#define REG_USART3_TNPR          (0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */
+#define REG_USART3_TNCR          (0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */
+#define REG_USART3_PTCR          (0x4009C120U) /**< \brief (USART3) Transfer Control Register */
+#define REG_USART3_PTSR          (0x4009C124U) /**< \brief (USART3) Transfer Status Register */
+#else
+#define REG_USART3_CR (*(WoReg*)0x4009C000U) /**< \brief (USART3) Control Register */
+#define REG_USART3_MR (*(RwReg*)0x4009C004U) /**< \brief (USART3) Mode Register */
+#define REG_USART3_IER (*(WoReg*)0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */
+#define REG_USART3_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */
+#define REG_USART3_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */
+#define REG_USART3_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART3) Channel Status Register */
+#define REG_USART3_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART3) Receiver Holding Register */
+#define REG_USART3_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */
+#define REG_USART3_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */
+#define REG_USART3_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */
+#define REG_USART3_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */
+#define REG_USART3_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */
+#define REG_USART3_NER (*(RoReg*)0x4009C044U) /**< \brief (USART3) Number of Errors Register */
+#define REG_USART3_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */
+#define REG_USART3_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
+#define REG_USART3_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */
+#define REG_USART3_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */
+#define REG_USART3_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART3) Receive Pointer Register */
+#define REG_USART3_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART3) Receive Counter Register */
+#define REG_USART3_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */
+#define REG_USART3_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */
+#define REG_USART3_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */
+#define REG_USART3_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */
+#define REG_USART3_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */
+#define REG_USART3_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */
+#define REG_USART3_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART3) Transfer Control Register */
+#define REG_USART3_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART3) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_USART3_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_wdt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_wdt.h
new file mode 100644
index 0000000..c0d02ee
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/instance/instance_wdt.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_WDT_INSTANCE_
+#define _SAM3U_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CR          (0x400E1250U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR          (0x400E1254U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR          (0x400E1258U) /**< \brief (WDT) Status Register */
+#else
+#define REG_WDT_CR (*(WoReg*)0x400E1250U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR (*(RwReg*)0x400E1254U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR (*(RoReg*)0x400E1258U) /**< \brief (WDT) Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3U_WDT_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u1c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u1c.h
new file mode 100644
index 0000000..58ecbc3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u1c.h
@@ -0,0 +1,356 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U1C_PIO_
+#define _SAM3U1C_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15          (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16          (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17          (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18          (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19          (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20          (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21          (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22          (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23          (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24          (1u << 24) /**< \brief Pin Controlled by PB24 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PB5X1_AD0     (1u << 5)  /**< \brief Adc signal: AD0 */
+#define PIO_PB6X1_AD1     (1u << 6)  /**< \brief Adc signal: AD1 */
+#define PIO_PB7X1_AD2     (1u << 7)  /**< \brief Adc signal: AD2 */
+#define PIO_PB8X1_AD3     (1u << 8)  /**< \brief Adc signal: AD3 */
+#define PIO_PC28X1_AD4    (1u << 28) /**< \brief Adc signal: AD4 */
+#define PIO_PC29X1_AD5    (1u << 29) /**< \brief Adc signal: AD5 */
+#define PIO_PC30X1_AD6    (1u << 30) /**< \brief Adc signal: AD6 */
+#define PIO_PC31X1_AD7    (1u << 31) /**< \brief Adc signal: AD7 */
+#define PIO_PA17B_ADTRG   (1u << 17) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for ADC12B peripheral ========== */
+#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
+#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
+#define PIO_PB3X1_AD12B2  (1u << 3)  /**< \brief Adc12b signal: AD12B2 */
+#define PIO_PB4X1_AD12B3  (1u << 4)  /**< \brief Adc12b signal: AD12B3 */
+#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
+#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
+#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
+#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
+#define PIO_PA2B_AD12BTRG (1u << 2)  /**< \brief Adc12b signal: AD12BTRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PB7B_A0       (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB7B_NBS0     (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB8B_A1       (1u << 8)  /**< \brief Ebi signal: A1 */
+#define PIO_PC8A_A10      (1u << 8)  /**< \brief Ebi signal: A10 */
+#define PIO_PC9A_A11      (1u << 9)  /**< \brief Ebi signal: A11 */
+#define PIO_PC10A_A12     (1u << 10) /**< \brief Ebi signal: A12 */
+#define PIO_PC11A_A13     (1u << 11) /**< \brief Ebi signal: A13 */
+#define PIO_PC20A_A14     (1u << 20) /**< \brief Ebi signal: A14 */
+#define PIO_PC21A_A15     (1u << 21) /**< \brief Ebi signal: A15 */
+#define PIO_PC22A_A16     (1u << 22) /**< \brief Ebi signal: A16 */
+#define PIO_PC23A_A17     (1u << 23) /**< \brief Ebi signal: A17 */
+#define PIO_PC24A_A18     (1u << 24) /**< \brief Ebi signal: A18 */
+#define PIO_PC25A_A19     (1u << 25) /**< \brief Ebi signal: A19 */
+#define PIO_PB0B_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC0A_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC13A_A2      (1u << 13) /**< \brief Ebi signal: A2 */
+#define PIO_PC26A_A20     (1u << 26) /**< \brief Ebi signal: A20 */
+#define PIO_PB21A_A21     (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB22A_A22     (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC27A_A23     (1u << 27) /**< \brief Ebi signal: A23 */
+#define PIO_PB1B_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC1A_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC14A_A3      (1u << 14) /**< \brief Ebi signal: A3 */
+#define PIO_PB2B_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PC2A_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PB3B_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PC3A_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PB4B_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PC4A_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PB5B_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC5A_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC6A_A8       (1u << 6)  /**< \brief Ebi signal: A8 */
+#define PIO_PC7A_A9       (1u << 7)  /**< \brief Ebi signal: A9 */
+#define PIO_PB9A_D0       (1u << 9)  /**< \brief Ebi signal: D0 */
+#define PIO_PB10A_D1      (1u << 10) /**< \brief Ebi signal: D1 */
+#define PIO_PB27A_D10     (1u << 27) /**< \brief Ebi signal: D10 */
+#define PIO_PB28A_D11     (1u << 28) /**< \brief Ebi signal: D11 */
+#define PIO_PB29A_D12     (1u << 29) /**< \brief Ebi signal: D12 */
+#define PIO_PB30A_D13     (1u << 30) /**< \brief Ebi signal: D13 */
+#define PIO_PB31A_D14     (1u << 31) /**< \brief Ebi signal: D14 */
+#define PIO_PB6B_D15      (1u << 6)  /**< \brief Ebi signal: D15 */
+#define PIO_PB11A_D2      (1u << 11) /**< \brief Ebi signal: D2 */
+#define PIO_PB12A_D3      (1u << 12) /**< \brief Ebi signal: D3 */
+#define PIO_PB13A_D4      (1u << 13) /**< \brief Ebi signal: D4 */
+#define PIO_PB14A_D5      (1u << 14) /**< \brief Ebi signal: D5 */
+#define PIO_PB15A_D6      (1u << 15) /**< \brief Ebi signal: D6 */
+#define PIO_PB16A_D7      (1u << 16) /**< \brief Ebi signal: D7 */
+#define PIO_PB25A_D8      (1u << 25) /**< \brief Ebi signal: D8 */
+#define PIO_PB26A_D9      (1u << 26) /**< \brief Ebi signal: D9 */
+#define PIO_PB17A_NANDOE  (1u << 17) /**< \brief Ebi signal: NANDOE */
+#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
+#define PIO_PB18A_NANDWE  (1u << 18) /**< \brief Ebi signal: NANDWE */
+#define PIO_PB20A_NCS0    (1u << 20) /**< \brief Ebi signal: NCS0 */
+#define PIO_PA16B_NCS1    (1u << 16) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC12A_NCS1    (1u << 12) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC16A_NCS2    (1u << 16) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC17A_NCS3    (1u << 17) /**< \brief Ebi signal: NCS3 */
+#define PIO_PB19A_NRD     (1u << 19) /**< \brief Ebi signal: NRD */
+#define PIO_PC18A_NWAIT   (1u << 18) /**< \brief Ebi signal: NWAIT */
+#define PIO_PB23A_NWR0    (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PB23A_NWE     (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC15A_NWR1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PC15A_NBS1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA4A_MCCDA    (1u << 4)  /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA3A_MCCK     (1u << 3)  /**< \brief Hsmci signal: MCCK */
+#define PIO_PA5A_MCDA0    (1u << 5)  /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA6A_MCDA1    (1u << 6)  /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA7A_MCDA2    (1u << 7)  /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA8A_MCDA3    (1u << 8)  /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PC28B_MCDA4   (1u << 28) /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PC29B_MCDA5   (1u << 29) /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PC30B_MCDA6   (1u << 30) /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PC31B_MCDA7   (1u << 31) /**< \brief Hsmci signal: MCDA7 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA21B_PCK0    (1u << 21) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA27B_PCK0    (1u << 27) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA3B_PCK1     (1u << 3)  /**< \brief Pmc signal: PCK1 */
+#define PIO_PB24B_PCK1    (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PB23B_PCK2    (1u << 23) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA11B_PWMFI0  (1u << 11) /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA12B_PWMFI1  (1u << 12) /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PA18B_PWMFI2  (1u << 18) /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA4B_PWMH0    (1u << 4)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA28B_PWMH0   (1u << 28) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0    (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB13B_PWMH0   (1u << 13) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC24B_PWMH0   (1u << 24) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA5B_PWMH1    (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA29B_PWMH1   (1u << 29) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1    (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB14B_PWMH1   (1u << 14) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC25B_PWMH1   (1u << 25) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA6B_PWMH2    (1u << 6)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB2A_PWMH2    (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC26B_PWMH2   (1u << 26) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA20B_PWMH3   (1u << 20) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB3A_PWMH3    (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB16B_PWMH3   (1u << 16) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC27B_PWMH3   (1u << 27) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA7B_PWML0    (1u << 7)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PB17B_PWML0   (1u << 17) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB25B_PWML0   (1u << 25) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC6B_PWML0    (1u << 6)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC29A_PWML0   (1u << 29) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA8B_PWML1    (1u << 8)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PB18B_PWML1   (1u << 18) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB26B_PWML1   (1u << 26) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC7B_PWML1    (1u << 7)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC30A_PWML1   (1u << 30) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA9B_PWML2    (1u << 9)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PB19B_PWML2   (1u << 19) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB27B_PWML2   (1u << 27) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC8B_PWML2    (1u << 8)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PC31A_PWML2   (1u << 31) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA10B_PWML3   (1u << 10) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB20B_PWML3   (1u << 20) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB28B_PWML3   (1u << 28) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC9B_PWML3    (1u << 9)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC16B_PWML3   (1u << 16) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA13A_MISO    (1u << 13) /**< \brief Spi signal: MISO */
+#define PIO_PA14A_MOSI    (1u << 14) /**< \brief Spi signal: MOSI */
+#define PIO_PA16A_NPCS0   (1u << 16) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA0B_NPCS1    (1u << 0)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC3B_NPCS1    (1u << 3)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC19B_NPCS1   (1u << 19) /**< \brief Spi signal: NPCS1 */
+#define PIO_PA1B_NPCS2    (1u << 1)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC4B_NPCS2    (1u << 4)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC14B_NPCS2   (1u << 14) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA19B_NPCS3   (1u << 19) /**< \brief Spi signal: NPCS3 */
+#define PIO_PC5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA15A_SPCK    (1u << 15) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA27A_RD      (1u << 27) /**< \brief Ssc signal: RD */
+#define PIO_PA31A_RF      (1u << 31) /**< \brief Ssc signal: RF */
+#define PIO_PA29A_RK      (1u << 29) /**< \brief Ssc signal: RK */
+#define PIO_PA26A_TD      (1u << 26) /**< \brief Ssc signal: TD */
+#define PIO_PA30A_TF      (1u << 30) /**< \brief Ssc signal: TF */
+#define PIO_PA28A_TK      (1u << 28) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA2A_TCLK0    (1u << 2)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PB4A_TCLK1    (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA26B_TCLK2   (1u << 26) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA1A_TIOA0    (1u << 1)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PB5A_TIOA1    (1u << 5)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA30B_TIOA2   (1u << 30) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA0A_TIOB0    (1u << 0)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PB6A_TIOB1    (1u << 6)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA31B_TIOB2   (1u << 31) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA10A_TWCK0   (1u << 10) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA9A_TWD0     (1u << 9)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PA25A_TWCK1   (1u << 25) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PA24A_TWD1    (1u << 24) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA11A_URXD    (1u << 11) /**< \brief Uart signal: URXD */
+#define PIO_PA12A_UTXD    (1u << 12) /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB11B_DCD0    (1u << 11) /**< \brief Usart0 signal: DCD0 */
+#define PIO_PB10B_DSR0    (1u << 10) /**< \brief Usart0 signal: DSR0 */
+#define PIO_PB9B_DTR0     (1u << 9)  /**< \brief Usart0 signal: DTR0 */
+#define PIO_PB12B_RI0     (1u << 12) /**< \brief Usart0 signal: RI0 */
+#define PIO_PB7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA19A_RXD0    (1u << 19) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17A_SCK0    (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA18A_TXD0    (1u << 18) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA23B_CTS1    (1u << 23) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA22B_RTS1    (1u << 22) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA24B_SCK1    (1u << 24) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA20A_TXD1    (1u << 20) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB22B_CTS2    (1u << 22) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB21B_RTS2    (1u << 21) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PA23A_RXD2    (1u << 23) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PA25B_SCK2    (1u << 25) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PA22A_TXD2    (1u << 22) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PB15_IDX      47
+#define PIO_PB16_IDX      48
+#define PIO_PB17_IDX      49
+#define PIO_PB18_IDX      50
+#define PIO_PB19_IDX      51
+#define PIO_PB20_IDX      52
+#define PIO_PB21_IDX      53
+#define PIO_PB22_IDX      54
+#define PIO_PB23_IDX      55
+#define PIO_PB24_IDX      56
+
+#endif /* _SAM3U1C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u1e.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u1e.h
new file mode 100644
index 0000000..5550c20
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u1e.h
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U1E_PIO_
+#define _SAM3U1E_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15          (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16          (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17          (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18          (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19          (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20          (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21          (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22          (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23          (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24          (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25          (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26          (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27          (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28          (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29          (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30          (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31          (1u << 31) /**< \brief Pin Controlled by PB31 */
+#define PIO_PC0           (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1           (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2           (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3           (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4           (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5           (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6           (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7           (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8           (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9           (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10          (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11          (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12          (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13          (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14          (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15          (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16          (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17          (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18          (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19          (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20          (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21          (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22          (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23          (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24          (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25          (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26          (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27          (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28          (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29          (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30          (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31          (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PB5X1_AD0     (1u << 5)  /**< \brief Adc signal: AD0 */
+#define PIO_PB6X1_AD1     (1u << 6)  /**< \brief Adc signal: AD1 */
+#define PIO_PB7X1_AD2     (1u << 7)  /**< \brief Adc signal: AD2 */
+#define PIO_PB8X1_AD3     (1u << 8)  /**< \brief Adc signal: AD3 */
+#define PIO_PC28X1_AD4    (1u << 28) /**< \brief Adc signal: AD4 */
+#define PIO_PC29X1_AD5    (1u << 29) /**< \brief Adc signal: AD5 */
+#define PIO_PC30X1_AD6    (1u << 30) /**< \brief Adc signal: AD6 */
+#define PIO_PC31X1_AD7    (1u << 31) /**< \brief Adc signal: AD7 */
+#define PIO_PA17B_ADTRG   (1u << 17) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for ADC12B peripheral ========== */
+#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
+#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
+#define PIO_PB3X1_AD12B2  (1u << 3)  /**< \brief Adc12b signal: AD12B2 */
+#define PIO_PB4X1_AD12B3  (1u << 4)  /**< \brief Adc12b signal: AD12B3 */
+#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
+#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
+#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
+#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
+#define PIO_PA2B_AD12BTRG (1u << 2)  /**< \brief Adc12b signal: AD12BTRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PB7B_A0       (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB7B_NBS0     (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB8B_A1       (1u << 8)  /**< \brief Ebi signal: A1 */
+#define PIO_PC8A_A10      (1u << 8)  /**< \brief Ebi signal: A10 */
+#define PIO_PC9A_A11      (1u << 9)  /**< \brief Ebi signal: A11 */
+#define PIO_PC10A_A12     (1u << 10) /**< \brief Ebi signal: A12 */
+#define PIO_PC11A_A13     (1u << 11) /**< \brief Ebi signal: A13 */
+#define PIO_PC20A_A14     (1u << 20) /**< \brief Ebi signal: A14 */
+#define PIO_PC21A_A15     (1u << 21) /**< \brief Ebi signal: A15 */
+#define PIO_PC22A_A16     (1u << 22) /**< \brief Ebi signal: A16 */
+#define PIO_PC23A_A17     (1u << 23) /**< \brief Ebi signal: A17 */
+#define PIO_PC24A_A18     (1u << 24) /**< \brief Ebi signal: A18 */
+#define PIO_PC25A_A19     (1u << 25) /**< \brief Ebi signal: A19 */
+#define PIO_PB0B_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC0A_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC13A_A2      (1u << 13) /**< \brief Ebi signal: A2 */
+#define PIO_PC26A_A20     (1u << 26) /**< \brief Ebi signal: A20 */
+#define PIO_PB21A_A21     (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB22A_A22     (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC27A_A23     (1u << 27) /**< \brief Ebi signal: A23 */
+#define PIO_PB1B_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC1A_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC14A_A3      (1u << 14) /**< \brief Ebi signal: A3 */
+#define PIO_PB2B_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PC2A_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PB3B_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PC3A_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PB4B_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PC4A_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PB5B_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC5A_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC6A_A8       (1u << 6)  /**< \brief Ebi signal: A8 */
+#define PIO_PC7A_A9       (1u << 7)  /**< \brief Ebi signal: A9 */
+#define PIO_PB9A_D0       (1u << 9)  /**< \brief Ebi signal: D0 */
+#define PIO_PB10A_D1      (1u << 10) /**< \brief Ebi signal: D1 */
+#define PIO_PB27A_D10     (1u << 27) /**< \brief Ebi signal: D10 */
+#define PIO_PB28A_D11     (1u << 28) /**< \brief Ebi signal: D11 */
+#define PIO_PB29A_D12     (1u << 29) /**< \brief Ebi signal: D12 */
+#define PIO_PB30A_D13     (1u << 30) /**< \brief Ebi signal: D13 */
+#define PIO_PB31A_D14     (1u << 31) /**< \brief Ebi signal: D14 */
+#define PIO_PB6B_D15      (1u << 6)  /**< \brief Ebi signal: D15 */
+#define PIO_PB11A_D2      (1u << 11) /**< \brief Ebi signal: D2 */
+#define PIO_PB12A_D3      (1u << 12) /**< \brief Ebi signal: D3 */
+#define PIO_PB13A_D4      (1u << 13) /**< \brief Ebi signal: D4 */
+#define PIO_PB14A_D5      (1u << 14) /**< \brief Ebi signal: D5 */
+#define PIO_PB15A_D6      (1u << 15) /**< \brief Ebi signal: D6 */
+#define PIO_PB16A_D7      (1u << 16) /**< \brief Ebi signal: D7 */
+#define PIO_PB25A_D8      (1u << 25) /**< \brief Ebi signal: D8 */
+#define PIO_PB26A_D9      (1u << 26) /**< \brief Ebi signal: D9 */
+#define PIO_PB17A_NANDOE  (1u << 17) /**< \brief Ebi signal: NANDOE */
+#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
+#define PIO_PB18A_NANDWE  (1u << 18) /**< \brief Ebi signal: NANDWE */
+#define PIO_PB20A_NCS0    (1u << 20) /**< \brief Ebi signal: NCS0 */
+#define PIO_PA16B_NCS1    (1u << 16) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC12A_NCS1    (1u << 12) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC16A_NCS2    (1u << 16) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC17A_NCS3    (1u << 17) /**< \brief Ebi signal: NCS3 */
+#define PIO_PB19A_NRD     (1u << 19) /**< \brief Ebi signal: NRD */
+#define PIO_PC18A_NWAIT   (1u << 18) /**< \brief Ebi signal: NWAIT */
+#define PIO_PB23A_NWR0    (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PB23A_NWE     (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC15A_NWR1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PC15A_NBS1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA4A_MCCDA    (1u << 4)  /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA3A_MCCK     (1u << 3)  /**< \brief Hsmci signal: MCCK */
+#define PIO_PA5A_MCDA0    (1u << 5)  /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA6A_MCDA1    (1u << 6)  /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA7A_MCDA2    (1u << 7)  /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA8A_MCDA3    (1u << 8)  /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PC28B_MCDA4   (1u << 28) /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PC29B_MCDA5   (1u << 29) /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PC30B_MCDA6   (1u << 30) /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PC31B_MCDA7   (1u << 31) /**< \brief Hsmci signal: MCDA7 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA21B_PCK0    (1u << 21) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA27B_PCK0    (1u << 27) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA3B_PCK1     (1u << 3)  /**< \brief Pmc signal: PCK1 */
+#define PIO_PB24B_PCK1    (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PB23B_PCK2    (1u << 23) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA11B_PWMFI0  (1u << 11) /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA12B_PWMFI1  (1u << 12) /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PA18B_PWMFI2  (1u << 18) /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA4B_PWMH0    (1u << 4)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA28B_PWMH0   (1u << 28) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0    (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB13B_PWMH0   (1u << 13) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC24B_PWMH0   (1u << 24) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA5B_PWMH1    (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA29B_PWMH1   (1u << 29) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1    (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB14B_PWMH1   (1u << 14) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC25B_PWMH1   (1u << 25) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA6B_PWMH2    (1u << 6)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB2A_PWMH2    (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC26B_PWMH2   (1u << 26) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA20B_PWMH3   (1u << 20) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB3A_PWMH3    (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB16B_PWMH3   (1u << 16) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC27B_PWMH3   (1u << 27) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA7B_PWML0    (1u << 7)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PB17B_PWML0   (1u << 17) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB25B_PWML0   (1u << 25) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC6B_PWML0    (1u << 6)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC29A_PWML0   (1u << 29) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA8B_PWML1    (1u << 8)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PB18B_PWML1   (1u << 18) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB26B_PWML1   (1u << 26) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC7B_PWML1    (1u << 7)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC30A_PWML1   (1u << 30) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA9B_PWML2    (1u << 9)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PB19B_PWML2   (1u << 19) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB27B_PWML2   (1u << 27) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC8B_PWML2    (1u << 8)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PC31A_PWML2   (1u << 31) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA10B_PWML3   (1u << 10) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB20B_PWML3   (1u << 20) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB28B_PWML3   (1u << 28) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC9B_PWML3    (1u << 9)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC16B_PWML3   (1u << 16) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA13A_MISO    (1u << 13) /**< \brief Spi signal: MISO */
+#define PIO_PA14A_MOSI    (1u << 14) /**< \brief Spi signal: MOSI */
+#define PIO_PA16A_NPCS0   (1u << 16) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA0B_NPCS1    (1u << 0)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC3B_NPCS1    (1u << 3)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC19B_NPCS1   (1u << 19) /**< \brief Spi signal: NPCS1 */
+#define PIO_PA1B_NPCS2    (1u << 1)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC4B_NPCS2    (1u << 4)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC14B_NPCS2   (1u << 14) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA19B_NPCS3   (1u << 19) /**< \brief Spi signal: NPCS3 */
+#define PIO_PC5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA15A_SPCK    (1u << 15) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA27A_RD      (1u << 27) /**< \brief Ssc signal: RD */
+#define PIO_PA31A_RF      (1u << 31) /**< \brief Ssc signal: RF */
+#define PIO_PA29A_RK      (1u << 29) /**< \brief Ssc signal: RK */
+#define PIO_PA26A_TD      (1u << 26) /**< \brief Ssc signal: TD */
+#define PIO_PA30A_TF      (1u << 30) /**< \brief Ssc signal: TF */
+#define PIO_PA28A_TK      (1u << 28) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA2A_TCLK0    (1u << 2)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PB4A_TCLK1    (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA26B_TCLK2   (1u << 26) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA1A_TIOA0    (1u << 1)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PB5A_TIOA1    (1u << 5)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA30B_TIOA2   (1u << 30) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA0A_TIOB0    (1u << 0)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PB6A_TIOB1    (1u << 6)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA31B_TIOB2   (1u << 31) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA10A_TWCK0   (1u << 10) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA9A_TWD0     (1u << 9)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PA25A_TWCK1   (1u << 25) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PA24A_TWD1    (1u << 24) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA11A_URXD    (1u << 11) /**< \brief Uart signal: URXD */
+#define PIO_PA12A_UTXD    (1u << 12) /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB11B_DCD0    (1u << 11) /**< \brief Usart0 signal: DCD0 */
+#define PIO_PB10B_DSR0    (1u << 10) /**< \brief Usart0 signal: DSR0 */
+#define PIO_PB9B_DTR0     (1u << 9)  /**< \brief Usart0 signal: DTR0 */
+#define PIO_PB12B_RI0     (1u << 12) /**< \brief Usart0 signal: RI0 */
+#define PIO_PB7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA19A_RXD0    (1u << 19) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17A_SCK0    (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA18A_TXD0    (1u << 18) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA23B_CTS1    (1u << 23) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA22B_RTS1    (1u << 22) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA24B_SCK1    (1u << 24) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA20A_TXD1    (1u << 20) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB22B_CTS2    (1u << 22) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB21B_RTS2    (1u << 21) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PA23A_RXD2    (1u << 23) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PA25B_SCK2    (1u << 25) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PA22A_TXD2    (1u << 22) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio definition for USART3 peripheral ========== */
+#define PIO_PC10B_CTS3    (1u << 10) /**< \brief Usart3 signal: CTS3 */
+#define PIO_PC11B_RTS3    (1u << 11) /**< \brief Usart3 signal: RTS3 */
+#define PIO_PC13B_RXD3    (1u << 13) /**< \brief Usart3 signal: RXD3 */
+#define PIO_PC19A_SCK3    (1u << 19) /**< \brief Usart3 signal: SCK3 */
+#define PIO_PC12B_TXD3    (1u << 12) /**< \brief Usart3 signal: TXD3 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PB15_IDX      47
+#define PIO_PB16_IDX      48
+#define PIO_PB17_IDX      49
+#define PIO_PB18_IDX      50
+#define PIO_PB19_IDX      51
+#define PIO_PB20_IDX      52
+#define PIO_PB21_IDX      53
+#define PIO_PB22_IDX      54
+#define PIO_PB23_IDX      55
+#define PIO_PB24_IDX      56
+#define PIO_PB25_IDX      57
+#define PIO_PB26_IDX      58
+#define PIO_PB27_IDX      59
+#define PIO_PB28_IDX      60
+#define PIO_PB29_IDX      61
+#define PIO_PB30_IDX      62
+#define PIO_PB31_IDX      63
+#define PIO_PC0_IDX       64
+#define PIO_PC1_IDX       65
+#define PIO_PC2_IDX       66
+#define PIO_PC3_IDX       67
+#define PIO_PC4_IDX       68
+#define PIO_PC5_IDX       69
+#define PIO_PC6_IDX       70
+#define PIO_PC7_IDX       71
+#define PIO_PC8_IDX       72
+#define PIO_PC9_IDX       73
+#define PIO_PC10_IDX      74
+#define PIO_PC11_IDX      75
+#define PIO_PC12_IDX      76
+#define PIO_PC13_IDX      77
+#define PIO_PC14_IDX      78
+#define PIO_PC15_IDX      79
+#define PIO_PC16_IDX      80
+#define PIO_PC17_IDX      81
+#define PIO_PC18_IDX      82
+#define PIO_PC19_IDX      83
+#define PIO_PC20_IDX      84
+#define PIO_PC21_IDX      85
+#define PIO_PC22_IDX      86
+#define PIO_PC23_IDX      87
+#define PIO_PC24_IDX      88
+#define PIO_PC25_IDX      89
+#define PIO_PC26_IDX      90
+#define PIO_PC27_IDX      91
+#define PIO_PC28_IDX      92
+#define PIO_PC29_IDX      93
+#define PIO_PC30_IDX      94
+#define PIO_PC31_IDX      95
+
+#endif /* _SAM3U1E_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u2c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u2c.h
new file mode 100644
index 0000000..e915413
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u2c.h
@@ -0,0 +1,356 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U2C_PIO_
+#define _SAM3U2C_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15          (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16          (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17          (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18          (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19          (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20          (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21          (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22          (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23          (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24          (1u << 24) /**< \brief Pin Controlled by PB24 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PB5X1_AD0     (1u << 5)  /**< \brief Adc signal: AD0 */
+#define PIO_PB6X1_AD1     (1u << 6)  /**< \brief Adc signal: AD1 */
+#define PIO_PB7X1_AD2     (1u << 7)  /**< \brief Adc signal: AD2 */
+#define PIO_PB8X1_AD3     (1u << 8)  /**< \brief Adc signal: AD3 */
+#define PIO_PC28X1_AD4    (1u << 28) /**< \brief Adc signal: AD4 */
+#define PIO_PC29X1_AD5    (1u << 29) /**< \brief Adc signal: AD5 */
+#define PIO_PC30X1_AD6    (1u << 30) /**< \brief Adc signal: AD6 */
+#define PIO_PC31X1_AD7    (1u << 31) /**< \brief Adc signal: AD7 */
+#define PIO_PA17B_ADTRG   (1u << 17) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for ADC12B peripheral ========== */
+#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
+#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
+#define PIO_PB3X1_AD12B2  (1u << 3)  /**< \brief Adc12b signal: AD12B2 */
+#define PIO_PB4X1_AD12B3  (1u << 4)  /**< \brief Adc12b signal: AD12B3 */
+#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
+#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
+#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
+#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
+#define PIO_PA2B_AD12BTRG (1u << 2)  /**< \brief Adc12b signal: AD12BTRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PB7B_A0       (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB7B_NBS0     (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB8B_A1       (1u << 8)  /**< \brief Ebi signal: A1 */
+#define PIO_PC8A_A10      (1u << 8)  /**< \brief Ebi signal: A10 */
+#define PIO_PC9A_A11      (1u << 9)  /**< \brief Ebi signal: A11 */
+#define PIO_PC10A_A12     (1u << 10) /**< \brief Ebi signal: A12 */
+#define PIO_PC11A_A13     (1u << 11) /**< \brief Ebi signal: A13 */
+#define PIO_PC20A_A14     (1u << 20) /**< \brief Ebi signal: A14 */
+#define PIO_PC21A_A15     (1u << 21) /**< \brief Ebi signal: A15 */
+#define PIO_PC22A_A16     (1u << 22) /**< \brief Ebi signal: A16 */
+#define PIO_PC23A_A17     (1u << 23) /**< \brief Ebi signal: A17 */
+#define PIO_PC24A_A18     (1u << 24) /**< \brief Ebi signal: A18 */
+#define PIO_PC25A_A19     (1u << 25) /**< \brief Ebi signal: A19 */
+#define PIO_PB0B_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC0A_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC13A_A2      (1u << 13) /**< \brief Ebi signal: A2 */
+#define PIO_PC26A_A20     (1u << 26) /**< \brief Ebi signal: A20 */
+#define PIO_PB21A_A21     (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB22A_A22     (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC27A_A23     (1u << 27) /**< \brief Ebi signal: A23 */
+#define PIO_PB1B_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC1A_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC14A_A3      (1u << 14) /**< \brief Ebi signal: A3 */
+#define PIO_PB2B_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PC2A_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PB3B_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PC3A_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PB4B_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PC4A_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PB5B_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC5A_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC6A_A8       (1u << 6)  /**< \brief Ebi signal: A8 */
+#define PIO_PC7A_A9       (1u << 7)  /**< \brief Ebi signal: A9 */
+#define PIO_PB9A_D0       (1u << 9)  /**< \brief Ebi signal: D0 */
+#define PIO_PB10A_D1      (1u << 10) /**< \brief Ebi signal: D1 */
+#define PIO_PB27A_D10     (1u << 27) /**< \brief Ebi signal: D10 */
+#define PIO_PB28A_D11     (1u << 28) /**< \brief Ebi signal: D11 */
+#define PIO_PB29A_D12     (1u << 29) /**< \brief Ebi signal: D12 */
+#define PIO_PB30A_D13     (1u << 30) /**< \brief Ebi signal: D13 */
+#define PIO_PB31A_D14     (1u << 31) /**< \brief Ebi signal: D14 */
+#define PIO_PB6B_D15      (1u << 6)  /**< \brief Ebi signal: D15 */
+#define PIO_PB11A_D2      (1u << 11) /**< \brief Ebi signal: D2 */
+#define PIO_PB12A_D3      (1u << 12) /**< \brief Ebi signal: D3 */
+#define PIO_PB13A_D4      (1u << 13) /**< \brief Ebi signal: D4 */
+#define PIO_PB14A_D5      (1u << 14) /**< \brief Ebi signal: D5 */
+#define PIO_PB15A_D6      (1u << 15) /**< \brief Ebi signal: D6 */
+#define PIO_PB16A_D7      (1u << 16) /**< \brief Ebi signal: D7 */
+#define PIO_PB25A_D8      (1u << 25) /**< \brief Ebi signal: D8 */
+#define PIO_PB26A_D9      (1u << 26) /**< \brief Ebi signal: D9 */
+#define PIO_PB17A_NANDOE  (1u << 17) /**< \brief Ebi signal: NANDOE */
+#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
+#define PIO_PB18A_NANDWE  (1u << 18) /**< \brief Ebi signal: NANDWE */
+#define PIO_PB20A_NCS0    (1u << 20) /**< \brief Ebi signal: NCS0 */
+#define PIO_PA16B_NCS1    (1u << 16) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC12A_NCS1    (1u << 12) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC16A_NCS2    (1u << 16) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC17A_NCS3    (1u << 17) /**< \brief Ebi signal: NCS3 */
+#define PIO_PB19A_NRD     (1u << 19) /**< \brief Ebi signal: NRD */
+#define PIO_PC18A_NWAIT   (1u << 18) /**< \brief Ebi signal: NWAIT */
+#define PIO_PB23A_NWR0    (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PB23A_NWE     (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC15A_NWR1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PC15A_NBS1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA4A_MCCDA    (1u << 4)  /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA3A_MCCK     (1u << 3)  /**< \brief Hsmci signal: MCCK */
+#define PIO_PA5A_MCDA0    (1u << 5)  /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA6A_MCDA1    (1u << 6)  /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA7A_MCDA2    (1u << 7)  /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA8A_MCDA3    (1u << 8)  /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PC28B_MCDA4   (1u << 28) /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PC29B_MCDA5   (1u << 29) /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PC30B_MCDA6   (1u << 30) /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PC31B_MCDA7   (1u << 31) /**< \brief Hsmci signal: MCDA7 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA21B_PCK0    (1u << 21) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA27B_PCK0    (1u << 27) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA3B_PCK1     (1u << 3)  /**< \brief Pmc signal: PCK1 */
+#define PIO_PB24B_PCK1    (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PB23B_PCK2    (1u << 23) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA11B_PWMFI0  (1u << 11) /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA12B_PWMFI1  (1u << 12) /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PA18B_PWMFI2  (1u << 18) /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA4B_PWMH0    (1u << 4)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA28B_PWMH0   (1u << 28) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0    (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB13B_PWMH0   (1u << 13) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC24B_PWMH0   (1u << 24) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA5B_PWMH1    (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA29B_PWMH1   (1u << 29) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1    (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB14B_PWMH1   (1u << 14) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC25B_PWMH1   (1u << 25) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA6B_PWMH2    (1u << 6)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB2A_PWMH2    (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC26B_PWMH2   (1u << 26) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA20B_PWMH3   (1u << 20) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB3A_PWMH3    (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB16B_PWMH3   (1u << 16) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC27B_PWMH3   (1u << 27) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA7B_PWML0    (1u << 7)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PB17B_PWML0   (1u << 17) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB25B_PWML0   (1u << 25) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC6B_PWML0    (1u << 6)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC29A_PWML0   (1u << 29) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA8B_PWML1    (1u << 8)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PB18B_PWML1   (1u << 18) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB26B_PWML1   (1u << 26) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC7B_PWML1    (1u << 7)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC30A_PWML1   (1u << 30) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA9B_PWML2    (1u << 9)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PB19B_PWML2   (1u << 19) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB27B_PWML2   (1u << 27) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC8B_PWML2    (1u << 8)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PC31A_PWML2   (1u << 31) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA10B_PWML3   (1u << 10) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB20B_PWML3   (1u << 20) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB28B_PWML3   (1u << 28) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC9B_PWML3    (1u << 9)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC16B_PWML3   (1u << 16) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA13A_MISO    (1u << 13) /**< \brief Spi signal: MISO */
+#define PIO_PA14A_MOSI    (1u << 14) /**< \brief Spi signal: MOSI */
+#define PIO_PA16A_NPCS0   (1u << 16) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA0B_NPCS1    (1u << 0)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC3B_NPCS1    (1u << 3)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC19B_NPCS1   (1u << 19) /**< \brief Spi signal: NPCS1 */
+#define PIO_PA1B_NPCS2    (1u << 1)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC4B_NPCS2    (1u << 4)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC14B_NPCS2   (1u << 14) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA19B_NPCS3   (1u << 19) /**< \brief Spi signal: NPCS3 */
+#define PIO_PC5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA15A_SPCK    (1u << 15) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA27A_RD      (1u << 27) /**< \brief Ssc signal: RD */
+#define PIO_PA31A_RF      (1u << 31) /**< \brief Ssc signal: RF */
+#define PIO_PA29A_RK      (1u << 29) /**< \brief Ssc signal: RK */
+#define PIO_PA26A_TD      (1u << 26) /**< \brief Ssc signal: TD */
+#define PIO_PA30A_TF      (1u << 30) /**< \brief Ssc signal: TF */
+#define PIO_PA28A_TK      (1u << 28) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA2A_TCLK0    (1u << 2)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PB4A_TCLK1    (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA26B_TCLK2   (1u << 26) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA1A_TIOA0    (1u << 1)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PB5A_TIOA1    (1u << 5)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA30B_TIOA2   (1u << 30) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA0A_TIOB0    (1u << 0)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PB6A_TIOB1    (1u << 6)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA31B_TIOB2   (1u << 31) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA10A_TWCK0   (1u << 10) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA9A_TWD0     (1u << 9)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PA25A_TWCK1   (1u << 25) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PA24A_TWD1    (1u << 24) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA11A_URXD    (1u << 11) /**< \brief Uart signal: URXD */
+#define PIO_PA12A_UTXD    (1u << 12) /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB11B_DCD0    (1u << 11) /**< \brief Usart0 signal: DCD0 */
+#define PIO_PB10B_DSR0    (1u << 10) /**< \brief Usart0 signal: DSR0 */
+#define PIO_PB9B_DTR0     (1u << 9)  /**< \brief Usart0 signal: DTR0 */
+#define PIO_PB12B_RI0     (1u << 12) /**< \brief Usart0 signal: RI0 */
+#define PIO_PB7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA19A_RXD0    (1u << 19) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17A_SCK0    (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA18A_TXD0    (1u << 18) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA23B_CTS1    (1u << 23) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA22B_RTS1    (1u << 22) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA24B_SCK1    (1u << 24) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA20A_TXD1    (1u << 20) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB22B_CTS2    (1u << 22) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB21B_RTS2    (1u << 21) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PA23A_RXD2    (1u << 23) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PA25B_SCK2    (1u << 25) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PA22A_TXD2    (1u << 22) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PB15_IDX      47
+#define PIO_PB16_IDX      48
+#define PIO_PB17_IDX      49
+#define PIO_PB18_IDX      50
+#define PIO_PB19_IDX      51
+#define PIO_PB20_IDX      52
+#define PIO_PB21_IDX      53
+#define PIO_PB22_IDX      54
+#define PIO_PB23_IDX      55
+#define PIO_PB24_IDX      56
+
+#endif /* _SAM3U2C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u2e.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u2e.h
new file mode 100644
index 0000000..5f84fc1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u2e.h
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U2E_PIO_
+#define _SAM3U2E_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15          (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16          (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17          (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18          (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19          (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20          (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21          (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22          (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23          (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24          (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25          (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26          (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27          (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28          (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29          (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30          (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31          (1u << 31) /**< \brief Pin Controlled by PB31 */
+#define PIO_PC0           (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1           (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2           (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3           (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4           (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5           (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6           (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7           (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8           (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9           (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10          (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11          (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12          (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13          (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14          (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15          (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16          (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17          (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18          (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19          (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20          (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21          (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22          (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23          (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24          (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25          (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26          (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27          (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28          (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29          (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30          (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31          (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PB5X1_AD0     (1u << 5)  /**< \brief Adc signal: AD0 */
+#define PIO_PB6X1_AD1     (1u << 6)  /**< \brief Adc signal: AD1 */
+#define PIO_PB7X1_AD2     (1u << 7)  /**< \brief Adc signal: AD2 */
+#define PIO_PB8X1_AD3     (1u << 8)  /**< \brief Adc signal: AD3 */
+#define PIO_PC28X1_AD4    (1u << 28) /**< \brief Adc signal: AD4 */
+#define PIO_PC29X1_AD5    (1u << 29) /**< \brief Adc signal: AD5 */
+#define PIO_PC30X1_AD6    (1u << 30) /**< \brief Adc signal: AD6 */
+#define PIO_PC31X1_AD7    (1u << 31) /**< \brief Adc signal: AD7 */
+#define PIO_PA17B_ADTRG   (1u << 17) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for ADC12B peripheral ========== */
+#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
+#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
+#define PIO_PB3X1_AD12B2  (1u << 3)  /**< \brief Adc12b signal: AD12B2 */
+#define PIO_PB4X1_AD12B3  (1u << 4)  /**< \brief Adc12b signal: AD12B3 */
+#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
+#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
+#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
+#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
+#define PIO_PA2B_AD12BTRG (1u << 2)  /**< \brief Adc12b signal: AD12BTRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PB7B_A0       (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB7B_NBS0     (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB8B_A1       (1u << 8)  /**< \brief Ebi signal: A1 */
+#define PIO_PC8A_A10      (1u << 8)  /**< \brief Ebi signal: A10 */
+#define PIO_PC9A_A11      (1u << 9)  /**< \brief Ebi signal: A11 */
+#define PIO_PC10A_A12     (1u << 10) /**< \brief Ebi signal: A12 */
+#define PIO_PC11A_A13     (1u << 11) /**< \brief Ebi signal: A13 */
+#define PIO_PC20A_A14     (1u << 20) /**< \brief Ebi signal: A14 */
+#define PIO_PC21A_A15     (1u << 21) /**< \brief Ebi signal: A15 */
+#define PIO_PC22A_A16     (1u << 22) /**< \brief Ebi signal: A16 */
+#define PIO_PC23A_A17     (1u << 23) /**< \brief Ebi signal: A17 */
+#define PIO_PC24A_A18     (1u << 24) /**< \brief Ebi signal: A18 */
+#define PIO_PC25A_A19     (1u << 25) /**< \brief Ebi signal: A19 */
+#define PIO_PB0B_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC0A_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC13A_A2      (1u << 13) /**< \brief Ebi signal: A2 */
+#define PIO_PC26A_A20     (1u << 26) /**< \brief Ebi signal: A20 */
+#define PIO_PB21A_A21     (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB22A_A22     (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC27A_A23     (1u << 27) /**< \brief Ebi signal: A23 */
+#define PIO_PB1B_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC1A_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC14A_A3      (1u << 14) /**< \brief Ebi signal: A3 */
+#define PIO_PB2B_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PC2A_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PB3B_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PC3A_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PB4B_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PC4A_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PB5B_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC5A_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC6A_A8       (1u << 6)  /**< \brief Ebi signal: A8 */
+#define PIO_PC7A_A9       (1u << 7)  /**< \brief Ebi signal: A9 */
+#define PIO_PB9A_D0       (1u << 9)  /**< \brief Ebi signal: D0 */
+#define PIO_PB10A_D1      (1u << 10) /**< \brief Ebi signal: D1 */
+#define PIO_PB27A_D10     (1u << 27) /**< \brief Ebi signal: D10 */
+#define PIO_PB28A_D11     (1u << 28) /**< \brief Ebi signal: D11 */
+#define PIO_PB29A_D12     (1u << 29) /**< \brief Ebi signal: D12 */
+#define PIO_PB30A_D13     (1u << 30) /**< \brief Ebi signal: D13 */
+#define PIO_PB31A_D14     (1u << 31) /**< \brief Ebi signal: D14 */
+#define PIO_PB6B_D15      (1u << 6)  /**< \brief Ebi signal: D15 */
+#define PIO_PB11A_D2      (1u << 11) /**< \brief Ebi signal: D2 */
+#define PIO_PB12A_D3      (1u << 12) /**< \brief Ebi signal: D3 */
+#define PIO_PB13A_D4      (1u << 13) /**< \brief Ebi signal: D4 */
+#define PIO_PB14A_D5      (1u << 14) /**< \brief Ebi signal: D5 */
+#define PIO_PB15A_D6      (1u << 15) /**< \brief Ebi signal: D6 */
+#define PIO_PB16A_D7      (1u << 16) /**< \brief Ebi signal: D7 */
+#define PIO_PB25A_D8      (1u << 25) /**< \brief Ebi signal: D8 */
+#define PIO_PB26A_D9      (1u << 26) /**< \brief Ebi signal: D9 */
+#define PIO_PB17A_NANDOE  (1u << 17) /**< \brief Ebi signal: NANDOE */
+#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
+#define PIO_PB18A_NANDWE  (1u << 18) /**< \brief Ebi signal: NANDWE */
+#define PIO_PB20A_NCS0    (1u << 20) /**< \brief Ebi signal: NCS0 */
+#define PIO_PA16B_NCS1    (1u << 16) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC12A_NCS1    (1u << 12) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC16A_NCS2    (1u << 16) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC17A_NCS3    (1u << 17) /**< \brief Ebi signal: NCS3 */
+#define PIO_PB19A_NRD     (1u << 19) /**< \brief Ebi signal: NRD */
+#define PIO_PC18A_NWAIT   (1u << 18) /**< \brief Ebi signal: NWAIT */
+#define PIO_PB23A_NWR0    (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PB23A_NWE     (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC15A_NWR1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PC15A_NBS1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA4A_MCCDA    (1u << 4)  /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA3A_MCCK     (1u << 3)  /**< \brief Hsmci signal: MCCK */
+#define PIO_PA5A_MCDA0    (1u << 5)  /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA6A_MCDA1    (1u << 6)  /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA7A_MCDA2    (1u << 7)  /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA8A_MCDA3    (1u << 8)  /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PC28B_MCDA4   (1u << 28) /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PC29B_MCDA5   (1u << 29) /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PC30B_MCDA6   (1u << 30) /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PC31B_MCDA7   (1u << 31) /**< \brief Hsmci signal: MCDA7 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA21B_PCK0    (1u << 21) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA27B_PCK0    (1u << 27) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA3B_PCK1     (1u << 3)  /**< \brief Pmc signal: PCK1 */
+#define PIO_PB24B_PCK1    (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PB23B_PCK2    (1u << 23) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA11B_PWMFI0  (1u << 11) /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA12B_PWMFI1  (1u << 12) /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PA18B_PWMFI2  (1u << 18) /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA4B_PWMH0    (1u << 4)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA28B_PWMH0   (1u << 28) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0    (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB13B_PWMH0   (1u << 13) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC24B_PWMH0   (1u << 24) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA5B_PWMH1    (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA29B_PWMH1   (1u << 29) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1    (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB14B_PWMH1   (1u << 14) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC25B_PWMH1   (1u << 25) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA6B_PWMH2    (1u << 6)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB2A_PWMH2    (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC26B_PWMH2   (1u << 26) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA20B_PWMH3   (1u << 20) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB3A_PWMH3    (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB16B_PWMH3   (1u << 16) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC27B_PWMH3   (1u << 27) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA7B_PWML0    (1u << 7)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PB17B_PWML0   (1u << 17) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB25B_PWML0   (1u << 25) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC6B_PWML0    (1u << 6)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC29A_PWML0   (1u << 29) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA8B_PWML1    (1u << 8)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PB18B_PWML1   (1u << 18) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB26B_PWML1   (1u << 26) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC7B_PWML1    (1u << 7)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC30A_PWML1   (1u << 30) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA9B_PWML2    (1u << 9)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PB19B_PWML2   (1u << 19) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB27B_PWML2   (1u << 27) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC8B_PWML2    (1u << 8)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PC31A_PWML2   (1u << 31) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA10B_PWML3   (1u << 10) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB20B_PWML3   (1u << 20) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB28B_PWML3   (1u << 28) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC9B_PWML3    (1u << 9)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC16B_PWML3   (1u << 16) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA13A_MISO    (1u << 13) /**< \brief Spi signal: MISO */
+#define PIO_PA14A_MOSI    (1u << 14) /**< \brief Spi signal: MOSI */
+#define PIO_PA16A_NPCS0   (1u << 16) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA0B_NPCS1    (1u << 0)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC3B_NPCS1    (1u << 3)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC19B_NPCS1   (1u << 19) /**< \brief Spi signal: NPCS1 */
+#define PIO_PA1B_NPCS2    (1u << 1)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC4B_NPCS2    (1u << 4)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC14B_NPCS2   (1u << 14) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA19B_NPCS3   (1u << 19) /**< \brief Spi signal: NPCS3 */
+#define PIO_PC5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA15A_SPCK    (1u << 15) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA27A_RD      (1u << 27) /**< \brief Ssc signal: RD */
+#define PIO_PA31A_RF      (1u << 31) /**< \brief Ssc signal: RF */
+#define PIO_PA29A_RK      (1u << 29) /**< \brief Ssc signal: RK */
+#define PIO_PA26A_TD      (1u << 26) /**< \brief Ssc signal: TD */
+#define PIO_PA30A_TF      (1u << 30) /**< \brief Ssc signal: TF */
+#define PIO_PA28A_TK      (1u << 28) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA2A_TCLK0    (1u << 2)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PB4A_TCLK1    (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA26B_TCLK2   (1u << 26) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA1A_TIOA0    (1u << 1)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PB5A_TIOA1    (1u << 5)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA30B_TIOA2   (1u << 30) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA0A_TIOB0    (1u << 0)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PB6A_TIOB1    (1u << 6)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA31B_TIOB2   (1u << 31) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA10A_TWCK0   (1u << 10) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA9A_TWD0     (1u << 9)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PA25A_TWCK1   (1u << 25) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PA24A_TWD1    (1u << 24) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA11A_URXD    (1u << 11) /**< \brief Uart signal: URXD */
+#define PIO_PA12A_UTXD    (1u << 12) /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB11B_DCD0    (1u << 11) /**< \brief Usart0 signal: DCD0 */
+#define PIO_PB10B_DSR0    (1u << 10) /**< \brief Usart0 signal: DSR0 */
+#define PIO_PB9B_DTR0     (1u << 9)  /**< \brief Usart0 signal: DTR0 */
+#define PIO_PB12B_RI0     (1u << 12) /**< \brief Usart0 signal: RI0 */
+#define PIO_PB7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA19A_RXD0    (1u << 19) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17A_SCK0    (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA18A_TXD0    (1u << 18) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA23B_CTS1    (1u << 23) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA22B_RTS1    (1u << 22) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA24B_SCK1    (1u << 24) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA20A_TXD1    (1u << 20) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB22B_CTS2    (1u << 22) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB21B_RTS2    (1u << 21) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PA23A_RXD2    (1u << 23) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PA25B_SCK2    (1u << 25) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PA22A_TXD2    (1u << 22) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio definition for USART3 peripheral ========== */
+#define PIO_PC10B_CTS3    (1u << 10) /**< \brief Usart3 signal: CTS3 */
+#define PIO_PC11B_RTS3    (1u << 11) /**< \brief Usart3 signal: RTS3 */
+#define PIO_PC13B_RXD3    (1u << 13) /**< \brief Usart3 signal: RXD3 */
+#define PIO_PC19A_SCK3    (1u << 19) /**< \brief Usart3 signal: SCK3 */
+#define PIO_PC12B_TXD3    (1u << 12) /**< \brief Usart3 signal: TXD3 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PB15_IDX      47
+#define PIO_PB16_IDX      48
+#define PIO_PB17_IDX      49
+#define PIO_PB18_IDX      50
+#define PIO_PB19_IDX      51
+#define PIO_PB20_IDX      52
+#define PIO_PB21_IDX      53
+#define PIO_PB22_IDX      54
+#define PIO_PB23_IDX      55
+#define PIO_PB24_IDX      56
+#define PIO_PB25_IDX      57
+#define PIO_PB26_IDX      58
+#define PIO_PB27_IDX      59
+#define PIO_PB28_IDX      60
+#define PIO_PB29_IDX      61
+#define PIO_PB30_IDX      62
+#define PIO_PB31_IDX      63
+#define PIO_PC0_IDX       64
+#define PIO_PC1_IDX       65
+#define PIO_PC2_IDX       66
+#define PIO_PC3_IDX       67
+#define PIO_PC4_IDX       68
+#define PIO_PC5_IDX       69
+#define PIO_PC6_IDX       70
+#define PIO_PC7_IDX       71
+#define PIO_PC8_IDX       72
+#define PIO_PC9_IDX       73
+#define PIO_PC10_IDX      74
+#define PIO_PC11_IDX      75
+#define PIO_PC12_IDX      76
+#define PIO_PC13_IDX      77
+#define PIO_PC14_IDX      78
+#define PIO_PC15_IDX      79
+#define PIO_PC16_IDX      80
+#define PIO_PC17_IDX      81
+#define PIO_PC18_IDX      82
+#define PIO_PC19_IDX      83
+#define PIO_PC20_IDX      84
+#define PIO_PC21_IDX      85
+#define PIO_PC22_IDX      86
+#define PIO_PC23_IDX      87
+#define PIO_PC24_IDX      88
+#define PIO_PC25_IDX      89
+#define PIO_PC26_IDX      90
+#define PIO_PC27_IDX      91
+#define PIO_PC28_IDX      92
+#define PIO_PC29_IDX      93
+#define PIO_PC30_IDX      94
+#define PIO_PC31_IDX      95
+
+#endif /* _SAM3U2E_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u4c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u4c.h
new file mode 100644
index 0000000..047a2cc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u4c.h
@@ -0,0 +1,356 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U4C_PIO_
+#define _SAM3U4C_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15          (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16          (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17          (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18          (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19          (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20          (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21          (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22          (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23          (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24          (1u << 24) /**< \brief Pin Controlled by PB24 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PB5X1_AD0     (1u << 5)  /**< \brief Adc signal: AD0 */
+#define PIO_PB6X1_AD1     (1u << 6)  /**< \brief Adc signal: AD1 */
+#define PIO_PB7X1_AD2     (1u << 7)  /**< \brief Adc signal: AD2 */
+#define PIO_PB8X1_AD3     (1u << 8)  /**< \brief Adc signal: AD3 */
+#define PIO_PC28X1_AD4    (1u << 28) /**< \brief Adc signal: AD4 */
+#define PIO_PC29X1_AD5    (1u << 29) /**< \brief Adc signal: AD5 */
+#define PIO_PC30X1_AD6    (1u << 30) /**< \brief Adc signal: AD6 */
+#define PIO_PC31X1_AD7    (1u << 31) /**< \brief Adc signal: AD7 */
+#define PIO_PA17B_ADTRG   (1u << 17) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for ADC12B peripheral ========== */
+#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
+#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
+#define PIO_PB3X1_AD12B2  (1u << 3)  /**< \brief Adc12b signal: AD12B2 */
+#define PIO_PB4X1_AD12B3  (1u << 4)  /**< \brief Adc12b signal: AD12B3 */
+#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
+#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
+#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
+#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
+#define PIO_PA2B_AD12BTRG (1u << 2)  /**< \brief Adc12b signal: AD12BTRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PB7B_A0       (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB7B_NBS0     (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB8B_A1       (1u << 8)  /**< \brief Ebi signal: A1 */
+#define PIO_PC8A_A10      (1u << 8)  /**< \brief Ebi signal: A10 */
+#define PIO_PC9A_A11      (1u << 9)  /**< \brief Ebi signal: A11 */
+#define PIO_PC10A_A12     (1u << 10) /**< \brief Ebi signal: A12 */
+#define PIO_PC11A_A13     (1u << 11) /**< \brief Ebi signal: A13 */
+#define PIO_PC20A_A14     (1u << 20) /**< \brief Ebi signal: A14 */
+#define PIO_PC21A_A15     (1u << 21) /**< \brief Ebi signal: A15 */
+#define PIO_PC22A_A16     (1u << 22) /**< \brief Ebi signal: A16 */
+#define PIO_PC23A_A17     (1u << 23) /**< \brief Ebi signal: A17 */
+#define PIO_PC24A_A18     (1u << 24) /**< \brief Ebi signal: A18 */
+#define PIO_PC25A_A19     (1u << 25) /**< \brief Ebi signal: A19 */
+#define PIO_PB0B_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC0A_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC13A_A2      (1u << 13) /**< \brief Ebi signal: A2 */
+#define PIO_PC26A_A20     (1u << 26) /**< \brief Ebi signal: A20 */
+#define PIO_PB21A_A21     (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB22A_A22     (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC27A_A23     (1u << 27) /**< \brief Ebi signal: A23 */
+#define PIO_PB1B_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC1A_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC14A_A3      (1u << 14) /**< \brief Ebi signal: A3 */
+#define PIO_PB2B_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PC2A_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PB3B_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PC3A_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PB4B_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PC4A_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PB5B_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC5A_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC6A_A8       (1u << 6)  /**< \brief Ebi signal: A8 */
+#define PIO_PC7A_A9       (1u << 7)  /**< \brief Ebi signal: A9 */
+#define PIO_PB9A_D0       (1u << 9)  /**< \brief Ebi signal: D0 */
+#define PIO_PB10A_D1      (1u << 10) /**< \brief Ebi signal: D1 */
+#define PIO_PB27A_D10     (1u << 27) /**< \brief Ebi signal: D10 */
+#define PIO_PB28A_D11     (1u << 28) /**< \brief Ebi signal: D11 */
+#define PIO_PB29A_D12     (1u << 29) /**< \brief Ebi signal: D12 */
+#define PIO_PB30A_D13     (1u << 30) /**< \brief Ebi signal: D13 */
+#define PIO_PB31A_D14     (1u << 31) /**< \brief Ebi signal: D14 */
+#define PIO_PB6B_D15      (1u << 6)  /**< \brief Ebi signal: D15 */
+#define PIO_PB11A_D2      (1u << 11) /**< \brief Ebi signal: D2 */
+#define PIO_PB12A_D3      (1u << 12) /**< \brief Ebi signal: D3 */
+#define PIO_PB13A_D4      (1u << 13) /**< \brief Ebi signal: D4 */
+#define PIO_PB14A_D5      (1u << 14) /**< \brief Ebi signal: D5 */
+#define PIO_PB15A_D6      (1u << 15) /**< \brief Ebi signal: D6 */
+#define PIO_PB16A_D7      (1u << 16) /**< \brief Ebi signal: D7 */
+#define PIO_PB25A_D8      (1u << 25) /**< \brief Ebi signal: D8 */
+#define PIO_PB26A_D9      (1u << 26) /**< \brief Ebi signal: D9 */
+#define PIO_PB17A_NANDOE  (1u << 17) /**< \brief Ebi signal: NANDOE */
+#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
+#define PIO_PB18A_NANDWE  (1u << 18) /**< \brief Ebi signal: NANDWE */
+#define PIO_PB20A_NCS0    (1u << 20) /**< \brief Ebi signal: NCS0 */
+#define PIO_PA16B_NCS1    (1u << 16) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC12A_NCS1    (1u << 12) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC16A_NCS2    (1u << 16) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC17A_NCS3    (1u << 17) /**< \brief Ebi signal: NCS3 */
+#define PIO_PB19A_NRD     (1u << 19) /**< \brief Ebi signal: NRD */
+#define PIO_PC18A_NWAIT   (1u << 18) /**< \brief Ebi signal: NWAIT */
+#define PIO_PB23A_NWR0    (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PB23A_NWE     (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC15A_NWR1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PC15A_NBS1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA4A_MCCDA    (1u << 4)  /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA3A_MCCK     (1u << 3)  /**< \brief Hsmci signal: MCCK */
+#define PIO_PA5A_MCDA0    (1u << 5)  /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA6A_MCDA1    (1u << 6)  /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA7A_MCDA2    (1u << 7)  /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA8A_MCDA3    (1u << 8)  /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PC28B_MCDA4   (1u << 28) /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PC29B_MCDA5   (1u << 29) /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PC30B_MCDA6   (1u << 30) /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PC31B_MCDA7   (1u << 31) /**< \brief Hsmci signal: MCDA7 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA21B_PCK0    (1u << 21) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA27B_PCK0    (1u << 27) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA3B_PCK1     (1u << 3)  /**< \brief Pmc signal: PCK1 */
+#define PIO_PB24B_PCK1    (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PB23B_PCK2    (1u << 23) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA11B_PWMFI0  (1u << 11) /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA12B_PWMFI1  (1u << 12) /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PA18B_PWMFI2  (1u << 18) /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA4B_PWMH0    (1u << 4)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA28B_PWMH0   (1u << 28) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0    (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB13B_PWMH0   (1u << 13) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC24B_PWMH0   (1u << 24) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA5B_PWMH1    (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA29B_PWMH1   (1u << 29) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1    (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB14B_PWMH1   (1u << 14) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC25B_PWMH1   (1u << 25) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA6B_PWMH2    (1u << 6)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB2A_PWMH2    (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC26B_PWMH2   (1u << 26) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA20B_PWMH3   (1u << 20) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB3A_PWMH3    (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB16B_PWMH3   (1u << 16) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC27B_PWMH3   (1u << 27) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA7B_PWML0    (1u << 7)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PB17B_PWML0   (1u << 17) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB25B_PWML0   (1u << 25) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC6B_PWML0    (1u << 6)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC29A_PWML0   (1u << 29) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA8B_PWML1    (1u << 8)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PB18B_PWML1   (1u << 18) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB26B_PWML1   (1u << 26) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC7B_PWML1    (1u << 7)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC30A_PWML1   (1u << 30) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA9B_PWML2    (1u << 9)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PB19B_PWML2   (1u << 19) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB27B_PWML2   (1u << 27) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC8B_PWML2    (1u << 8)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PC31A_PWML2   (1u << 31) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA10B_PWML3   (1u << 10) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB20B_PWML3   (1u << 20) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB28B_PWML3   (1u << 28) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC9B_PWML3    (1u << 9)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC16B_PWML3   (1u << 16) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA13A_MISO    (1u << 13) /**< \brief Spi signal: MISO */
+#define PIO_PA14A_MOSI    (1u << 14) /**< \brief Spi signal: MOSI */
+#define PIO_PA16A_NPCS0   (1u << 16) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA0B_NPCS1    (1u << 0)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC3B_NPCS1    (1u << 3)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC19B_NPCS1   (1u << 19) /**< \brief Spi signal: NPCS1 */
+#define PIO_PA1B_NPCS2    (1u << 1)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC4B_NPCS2    (1u << 4)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC14B_NPCS2   (1u << 14) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA19B_NPCS3   (1u << 19) /**< \brief Spi signal: NPCS3 */
+#define PIO_PC5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA15A_SPCK    (1u << 15) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA27A_RD      (1u << 27) /**< \brief Ssc signal: RD */
+#define PIO_PA31A_RF      (1u << 31) /**< \brief Ssc signal: RF */
+#define PIO_PA29A_RK      (1u << 29) /**< \brief Ssc signal: RK */
+#define PIO_PA26A_TD      (1u << 26) /**< \brief Ssc signal: TD */
+#define PIO_PA30A_TF      (1u << 30) /**< \brief Ssc signal: TF */
+#define PIO_PA28A_TK      (1u << 28) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA2A_TCLK0    (1u << 2)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PB4A_TCLK1    (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA26B_TCLK2   (1u << 26) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA1A_TIOA0    (1u << 1)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PB5A_TIOA1    (1u << 5)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA30B_TIOA2   (1u << 30) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA0A_TIOB0    (1u << 0)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PB6A_TIOB1    (1u << 6)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA31B_TIOB2   (1u << 31) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA10A_TWCK0   (1u << 10) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA9A_TWD0     (1u << 9)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PA25A_TWCK1   (1u << 25) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PA24A_TWD1    (1u << 24) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA11A_URXD    (1u << 11) /**< \brief Uart signal: URXD */
+#define PIO_PA12A_UTXD    (1u << 12) /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB11B_DCD0    (1u << 11) /**< \brief Usart0 signal: DCD0 */
+#define PIO_PB10B_DSR0    (1u << 10) /**< \brief Usart0 signal: DSR0 */
+#define PIO_PB9B_DTR0     (1u << 9)  /**< \brief Usart0 signal: DTR0 */
+#define PIO_PB12B_RI0     (1u << 12) /**< \brief Usart0 signal: RI0 */
+#define PIO_PB7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA19A_RXD0    (1u << 19) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17A_SCK0    (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA18A_TXD0    (1u << 18) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA23B_CTS1    (1u << 23) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA22B_RTS1    (1u << 22) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA24B_SCK1    (1u << 24) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA20A_TXD1    (1u << 20) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB22B_CTS2    (1u << 22) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB21B_RTS2    (1u << 21) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PA23A_RXD2    (1u << 23) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PA25B_SCK2    (1u << 25) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PA22A_TXD2    (1u << 22) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PB15_IDX      47
+#define PIO_PB16_IDX      48
+#define PIO_PB17_IDX      49
+#define PIO_PB18_IDX      50
+#define PIO_PB19_IDX      51
+#define PIO_PB20_IDX      52
+#define PIO_PB21_IDX      53
+#define PIO_PB22_IDX      54
+#define PIO_PB23_IDX      55
+#define PIO_PB24_IDX      56
+
+#endif /* _SAM3U4C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u4e.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u4e.h
new file mode 100644
index 0000000..407fbc8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/pio/pio_sam3u4e.h
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U4E_PIO_
+#define _SAM3U4E_PIO_
+
+#define PIO_PA0           (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1           (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2           (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3           (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4           (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5           (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6           (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7           (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8           (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9           (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10          (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11          (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12          (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13          (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14          (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15          (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16          (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17          (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18          (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19          (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20          (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21          (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22          (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23          (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24          (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25          (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26          (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27          (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28          (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29          (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30          (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31          (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0           (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1           (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2           (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3           (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4           (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5           (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6           (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7           (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8           (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9           (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10          (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11          (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12          (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13          (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14          (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15          (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16          (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17          (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18          (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19          (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20          (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21          (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22          (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23          (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24          (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25          (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26          (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27          (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28          (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29          (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30          (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31          (1u << 31) /**< \brief Pin Controlled by PB31 */
+#define PIO_PC0           (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1           (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2           (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3           (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4           (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5           (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6           (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7           (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8           (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9           (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10          (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11          (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12          (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13          (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14          (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15          (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16          (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17          (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18          (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19          (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20          (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21          (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22          (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23          (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24          (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25          (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26          (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27          (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28          (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29          (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30          (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31          (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PB5X1_AD0     (1u << 5)  /**< \brief Adc signal: AD0 */
+#define PIO_PB6X1_AD1     (1u << 6)  /**< \brief Adc signal: AD1 */
+#define PIO_PB7X1_AD2     (1u << 7)  /**< \brief Adc signal: AD2 */
+#define PIO_PB8X1_AD3     (1u << 8)  /**< \brief Adc signal: AD3 */
+#define PIO_PC28X1_AD4    (1u << 28) /**< \brief Adc signal: AD4 */
+#define PIO_PC29X1_AD5    (1u << 29) /**< \brief Adc signal: AD5 */
+#define PIO_PC30X1_AD6    (1u << 30) /**< \brief Adc signal: AD6 */
+#define PIO_PC31X1_AD7    (1u << 31) /**< \brief Adc signal: AD7 */
+#define PIO_PA17B_ADTRG   (1u << 17) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for ADC12B peripheral ========== */
+#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
+#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
+#define PIO_PB3X1_AD12B2  (1u << 3)  /**< \brief Adc12b signal: AD12B2 */
+#define PIO_PB4X1_AD12B3  (1u << 4)  /**< \brief Adc12b signal: AD12B3 */
+#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
+#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
+#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
+#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
+#define PIO_PA2B_AD12BTRG (1u << 2)  /**< \brief Adc12b signal: AD12BTRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PB7B_A0       (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB7B_NBS0     (1u << 7)  /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PB8B_A1       (1u << 8)  /**< \brief Ebi signal: A1 */
+#define PIO_PC8A_A10      (1u << 8)  /**< \brief Ebi signal: A10 */
+#define PIO_PC9A_A11      (1u << 9)  /**< \brief Ebi signal: A11 */
+#define PIO_PC10A_A12     (1u << 10) /**< \brief Ebi signal: A12 */
+#define PIO_PC11A_A13     (1u << 11) /**< \brief Ebi signal: A13 */
+#define PIO_PC20A_A14     (1u << 20) /**< \brief Ebi signal: A14 */
+#define PIO_PC21A_A15     (1u << 21) /**< \brief Ebi signal: A15 */
+#define PIO_PC22A_A16     (1u << 22) /**< \brief Ebi signal: A16 */
+#define PIO_PC23A_A17     (1u << 23) /**< \brief Ebi signal: A17 */
+#define PIO_PC24A_A18     (1u << 24) /**< \brief Ebi signal: A18 */
+#define PIO_PC25A_A19     (1u << 25) /**< \brief Ebi signal: A19 */
+#define PIO_PB0B_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC0A_A2       (1u << 0)  /**< \brief Ebi signal: A2 */
+#define PIO_PC13A_A2      (1u << 13) /**< \brief Ebi signal: A2 */
+#define PIO_PC26A_A20     (1u << 26) /**< \brief Ebi signal: A20 */
+#define PIO_PB21A_A21     (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PB22A_A22     (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC27A_A23     (1u << 27) /**< \brief Ebi signal: A23 */
+#define PIO_PB1B_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC1A_A3       (1u << 1)  /**< \brief Ebi signal: A3 */
+#define PIO_PC14A_A3      (1u << 14) /**< \brief Ebi signal: A3 */
+#define PIO_PB2B_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PC2A_A4       (1u << 2)  /**< \brief Ebi signal: A4 */
+#define PIO_PB3B_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PC3A_A5       (1u << 3)  /**< \brief Ebi signal: A5 */
+#define PIO_PB4B_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PC4A_A6       (1u << 4)  /**< \brief Ebi signal: A6 */
+#define PIO_PB5B_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC5A_A7       (1u << 5)  /**< \brief Ebi signal: A7 */
+#define PIO_PC6A_A8       (1u << 6)  /**< \brief Ebi signal: A8 */
+#define PIO_PC7A_A9       (1u << 7)  /**< \brief Ebi signal: A9 */
+#define PIO_PB9A_D0       (1u << 9)  /**< \brief Ebi signal: D0 */
+#define PIO_PB10A_D1      (1u << 10) /**< \brief Ebi signal: D1 */
+#define PIO_PB27A_D10     (1u << 27) /**< \brief Ebi signal: D10 */
+#define PIO_PB28A_D11     (1u << 28) /**< \brief Ebi signal: D11 */
+#define PIO_PB29A_D12     (1u << 29) /**< \brief Ebi signal: D12 */
+#define PIO_PB30A_D13     (1u << 30) /**< \brief Ebi signal: D13 */
+#define PIO_PB31A_D14     (1u << 31) /**< \brief Ebi signal: D14 */
+#define PIO_PB6B_D15      (1u << 6)  /**< \brief Ebi signal: D15 */
+#define PIO_PB11A_D2      (1u << 11) /**< \brief Ebi signal: D2 */
+#define PIO_PB12A_D3      (1u << 12) /**< \brief Ebi signal: D3 */
+#define PIO_PB13A_D4      (1u << 13) /**< \brief Ebi signal: D4 */
+#define PIO_PB14A_D5      (1u << 14) /**< \brief Ebi signal: D5 */
+#define PIO_PB15A_D6      (1u << 15) /**< \brief Ebi signal: D6 */
+#define PIO_PB16A_D7      (1u << 16) /**< \brief Ebi signal: D7 */
+#define PIO_PB25A_D8      (1u << 25) /**< \brief Ebi signal: D8 */
+#define PIO_PB26A_D9      (1u << 26) /**< \brief Ebi signal: D9 */
+#define PIO_PB17A_NANDOE  (1u << 17) /**< \brief Ebi signal: NANDOE */
+#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
+#define PIO_PB18A_NANDWE  (1u << 18) /**< \brief Ebi signal: NANDWE */
+#define PIO_PB20A_NCS0    (1u << 20) /**< \brief Ebi signal: NCS0 */
+#define PIO_PA16B_NCS1    (1u << 16) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC12A_NCS1    (1u << 12) /**< \brief Ebi signal: NCS1 */
+#define PIO_PC16A_NCS2    (1u << 16) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC17A_NCS3    (1u << 17) /**< \brief Ebi signal: NCS3 */
+#define PIO_PB19A_NRD     (1u << 19) /**< \brief Ebi signal: NRD */
+#define PIO_PC18A_NWAIT   (1u << 18) /**< \brief Ebi signal: NWAIT */
+#define PIO_PB23A_NWR0    (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PB23A_NWE     (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC15A_NWR1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PC15A_NBS1    (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA4A_MCCDA    (1u << 4)  /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA3A_MCCK     (1u << 3)  /**< \brief Hsmci signal: MCCK */
+#define PIO_PA5A_MCDA0    (1u << 5)  /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA6A_MCDA1    (1u << 6)  /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA7A_MCDA2    (1u << 7)  /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA8A_MCDA3    (1u << 8)  /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PC28B_MCDA4   (1u << 28) /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PC29B_MCDA5   (1u << 29) /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PC30B_MCDA6   (1u << 30) /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PC31B_MCDA7   (1u << 31) /**< \brief Hsmci signal: MCDA7 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA21B_PCK0    (1u << 21) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA27B_PCK0    (1u << 27) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA3B_PCK1     (1u << 3)  /**< \brief Pmc signal: PCK1 */
+#define PIO_PB24B_PCK1    (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PB23B_PCK2    (1u << 23) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA11B_PWMFI0  (1u << 11) /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA12B_PWMFI1  (1u << 12) /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PA18B_PWMFI2  (1u << 18) /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA4B_PWMH0    (1u << 4)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA28B_PWMH0   (1u << 28) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0    (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB13B_PWMH0   (1u << 13) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC24B_PWMH0   (1u << 24) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA5B_PWMH1    (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA29B_PWMH1   (1u << 29) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1    (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB14B_PWMH1   (1u << 14) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC25B_PWMH1   (1u << 25) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA6B_PWMH2    (1u << 6)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB2A_PWMH2    (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB15B_PWMH2   (1u << 15) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC26B_PWMH2   (1u << 26) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA20B_PWMH3   (1u << 20) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB3A_PWMH3    (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB16B_PWMH3   (1u << 16) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC27B_PWMH3   (1u << 27) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA7B_PWML0    (1u << 7)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PB17B_PWML0   (1u << 17) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB25B_PWML0   (1u << 25) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC6B_PWML0    (1u << 6)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC29A_PWML0   (1u << 29) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA8B_PWML1    (1u << 8)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PB18B_PWML1   (1u << 18) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB26B_PWML1   (1u << 26) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC7B_PWML1    (1u << 7)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC30A_PWML1   (1u << 30) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA9B_PWML2    (1u << 9)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PB19B_PWML2   (1u << 19) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB27B_PWML2   (1u << 27) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC8B_PWML2    (1u << 8)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PC31A_PWML2   (1u << 31) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA10B_PWML3   (1u << 10) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB20B_PWML3   (1u << 20) /**< \brief Pwm signal: PWML3 */
+#define PIO_PB28B_PWML3   (1u << 28) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC9B_PWML3    (1u << 9)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC16B_PWML3   (1u << 16) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA13A_MISO    (1u << 13) /**< \brief Spi signal: MISO */
+#define PIO_PA14A_MOSI    (1u << 14) /**< \brief Spi signal: MOSI */
+#define PIO_PA16A_NPCS0   (1u << 16) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA0B_NPCS1    (1u << 0)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC3B_NPCS1    (1u << 3)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PC19B_NPCS1   (1u << 19) /**< \brief Spi signal: NPCS1 */
+#define PIO_PA1B_NPCS2    (1u << 1)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC4B_NPCS2    (1u << 4)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PC14B_NPCS2   (1u << 14) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA19B_NPCS3   (1u << 19) /**< \brief Spi signal: NPCS3 */
+#define PIO_PC5B_NPCS3    (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA15A_SPCK    (1u << 15) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA27A_RD      (1u << 27) /**< \brief Ssc signal: RD */
+#define PIO_PA31A_RF      (1u << 31) /**< \brief Ssc signal: RF */
+#define PIO_PA29A_RK      (1u << 29) /**< \brief Ssc signal: RK */
+#define PIO_PA26A_TD      (1u << 26) /**< \brief Ssc signal: TD */
+#define PIO_PA30A_TF      (1u << 30) /**< \brief Ssc signal: TF */
+#define PIO_PA28A_TK      (1u << 28) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA2A_TCLK0    (1u << 2)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PB4A_TCLK1    (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA26B_TCLK2   (1u << 26) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA1A_TIOA0    (1u << 1)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PB5A_TIOA1    (1u << 5)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA30B_TIOA2   (1u << 30) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA0A_TIOB0    (1u << 0)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PB6A_TIOB1    (1u << 6)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA31B_TIOB2   (1u << 31) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA10A_TWCK0   (1u << 10) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA9A_TWD0     (1u << 9)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PA25A_TWCK1   (1u << 25) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PA24A_TWD1    (1u << 24) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA11A_URXD    (1u << 11) /**< \brief Uart signal: URXD */
+#define PIO_PA12A_UTXD    (1u << 12) /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB8A_CTS0     (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB11B_DCD0    (1u << 11) /**< \brief Usart0 signal: DCD0 */
+#define PIO_PB10B_DSR0    (1u << 10) /**< \brief Usart0 signal: DSR0 */
+#define PIO_PB9B_DTR0     (1u << 9)  /**< \brief Usart0 signal: DTR0 */
+#define PIO_PB12B_RI0     (1u << 12) /**< \brief Usart0 signal: RI0 */
+#define PIO_PB7A_RTS0     (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA19A_RXD0    (1u << 19) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17A_SCK0    (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA18A_TXD0    (1u << 18) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA23B_CTS1    (1u << 23) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA22B_RTS1    (1u << 22) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1    (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA24B_SCK1    (1u << 24) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA20A_TXD1    (1u << 20) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB22B_CTS2    (1u << 22) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB21B_RTS2    (1u << 21) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PA23A_RXD2    (1u << 23) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PA25B_SCK2    (1u << 25) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PA22A_TXD2    (1u << 22) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio definition for USART3 peripheral ========== */
+#define PIO_PC10B_CTS3    (1u << 10) /**< \brief Usart3 signal: CTS3 */
+#define PIO_PC11B_RTS3    (1u << 11) /**< \brief Usart3 signal: RTS3 */
+#define PIO_PC13B_RXD3    (1u << 13) /**< \brief Usart3 signal: RXD3 */
+#define PIO_PC19A_SCK3    (1u << 19) /**< \brief Usart3 signal: SCK3 */
+#define PIO_PC12B_TXD3    (1u << 12) /**< \brief Usart3 signal: TXD3 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX       0
+#define PIO_PA1_IDX       1
+#define PIO_PA2_IDX       2
+#define PIO_PA3_IDX       3
+#define PIO_PA4_IDX       4
+#define PIO_PA5_IDX       5
+#define PIO_PA6_IDX       6
+#define PIO_PA7_IDX       7
+#define PIO_PA8_IDX       8
+#define PIO_PA9_IDX       9
+#define PIO_PA10_IDX      10
+#define PIO_PA11_IDX      11
+#define PIO_PA12_IDX      12
+#define PIO_PA13_IDX      13
+#define PIO_PA14_IDX      14
+#define PIO_PA15_IDX      15
+#define PIO_PA16_IDX      16
+#define PIO_PA17_IDX      17
+#define PIO_PA18_IDX      18
+#define PIO_PA19_IDX      19
+#define PIO_PA20_IDX      20
+#define PIO_PA21_IDX      21
+#define PIO_PA22_IDX      22
+#define PIO_PA23_IDX      23
+#define PIO_PA24_IDX      24
+#define PIO_PA25_IDX      25
+#define PIO_PA26_IDX      26
+#define PIO_PA27_IDX      27
+#define PIO_PA28_IDX      28
+#define PIO_PA29_IDX      29
+#define PIO_PA30_IDX      30
+#define PIO_PA31_IDX      31
+#define PIO_PB0_IDX       32
+#define PIO_PB1_IDX       33
+#define PIO_PB2_IDX       34
+#define PIO_PB3_IDX       35
+#define PIO_PB4_IDX       36
+#define PIO_PB5_IDX       37
+#define PIO_PB6_IDX       38
+#define PIO_PB7_IDX       39
+#define PIO_PB8_IDX       40
+#define PIO_PB9_IDX       41
+#define PIO_PB10_IDX      42
+#define PIO_PB11_IDX      43
+#define PIO_PB12_IDX      44
+#define PIO_PB13_IDX      45
+#define PIO_PB14_IDX      46
+#define PIO_PB15_IDX      47
+#define PIO_PB16_IDX      48
+#define PIO_PB17_IDX      49
+#define PIO_PB18_IDX      50
+#define PIO_PB19_IDX      51
+#define PIO_PB20_IDX      52
+#define PIO_PB21_IDX      53
+#define PIO_PB22_IDX      54
+#define PIO_PB23_IDX      55
+#define PIO_PB24_IDX      56
+#define PIO_PB25_IDX      57
+#define PIO_PB26_IDX      58
+#define PIO_PB27_IDX      59
+#define PIO_PB28_IDX      60
+#define PIO_PB29_IDX      61
+#define PIO_PB30_IDX      62
+#define PIO_PB31_IDX      63
+#define PIO_PC0_IDX       64
+#define PIO_PC1_IDX       65
+#define PIO_PC2_IDX       66
+#define PIO_PC3_IDX       67
+#define PIO_PC4_IDX       68
+#define PIO_PC5_IDX       69
+#define PIO_PC6_IDX       70
+#define PIO_PC7_IDX       71
+#define PIO_PC8_IDX       72
+#define PIO_PC9_IDX       73
+#define PIO_PC10_IDX      74
+#define PIO_PC11_IDX      75
+#define PIO_PC12_IDX      76
+#define PIO_PC13_IDX      77
+#define PIO_PC14_IDX      78
+#define PIO_PC15_IDX      79
+#define PIO_PC16_IDX      80
+#define PIO_PC17_IDX      81
+#define PIO_PC18_IDX      82
+#define PIO_PC19_IDX      83
+#define PIO_PC20_IDX      84
+#define PIO_PC21_IDX      85
+#define PIO_PC22_IDX      86
+#define PIO_PC23_IDX      87
+#define PIO_PC24_IDX      88
+#define PIO_PC25_IDX      89
+#define PIO_PC26_IDX      90
+#define PIO_PC27_IDX      91
+#define PIO_PC28_IDX      92
+#define PIO_PC29_IDX      93
+#define PIO_PC30_IDX      94
+#define PIO_PC31_IDX      95
+
+#endif /* _SAM3U4E_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u.h
new file mode 100644
index 0000000..6dd9e97
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u.h
@@ -0,0 +1,49 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U_
+#define _SAM3U_
+
+#if defined __SAM3U1C__
+  #include "sam3u1c.h"
+#elif defined __SAM3U1E__
+  #include "sam3u1e.h"
+#elif defined __SAM3U2C__
+  #include "sam3u2c.h"
+#elif defined __SAM3U2E__
+  #include "sam3u2e.h"
+#elif defined __SAM3U4C__
+  #include "sam3u4c.h"
+#elif defined __SAM3U4E__
+  #include "sam3u4e.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAM3U_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u1c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u1c.h
new file mode 100644
index 0000000..018e0ff
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u1c.h
@@ -0,0 +1,482 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U1C_
+#define _SAM3U1C_
+
+/** \addtogroup SAM3U1C_definitions SAM3U1C definitions
+  This file defines all structures and symbols for SAM3U1C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3U1C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3U1C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3U1C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3U1C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3U1C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3U1C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3U1C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3U1C Enhanced Embedded Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3U1C Enhanced Embedded Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3U1C Universal Asynchronous Receiver Transmitter (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3U1C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 10, /**< 10 SAM3U1C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 11, /**< 11 SAM3U1C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 13, /**< 13 SAM3U1C USART 0 (USART0) */
+  USART1_IRQn          = 14, /**< 14 SAM3U1C USART 1 (USART1) */
+  USART2_IRQn          = 15, /**< 15 SAM3U1C USART 2 (USART2) */
+  HSMCI_IRQn           = 17, /**< 17 SAM3U1C High Speed Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 18, /**< 18 SAM3U1C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 19, /**< 19 SAM3U1C Two-Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 20, /**< 20 SAM3U1C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 21, /**< 21 SAM3U1C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 22, /**< 22 SAM3U1C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 23, /**< 23 SAM3U1C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 24, /**< 24 SAM3U1C Timer Counter 2 (TC2) */
+  PWM_IRQn             = 25, /**< 25 SAM3U1C Pulse Width Modulation Controller (PWM) */
+  ADC12B_IRQn          = 26, /**< 26 SAM3U1C 12-bit ADC Controller (ADC12B) */
+  ADC_IRQn             = 27, /**< 27 SAM3U1C 10-bit ADC Controller (ADC) */
+  DMAC_IRQn            = 28, /**< 28 SAM3U1C DMA Controller (DMAC) */
+  UDPHS_IRQn           = 29, /**< 29 SAM3U1C USB Device High Speed (UDPHS) */
+
+  PERIPH_COUNT_IRQn    = 30  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC0_Handler;   /*  6 Enhanced Embedded Flash Controller 0 */
+  void* pfnEFC1_Handler;   /*  7 Enhanced Embedded Flash Controller 1 */
+  void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transmitter */
+  void* pfnSMC_Handler;    /*  9 Static Memory Controller */
+  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A, */
+  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
+  void* pvReserved12;
+  void* pfnUSART0_Handler; /* 13 USART 0 */
+  void* pfnUSART1_Handler; /* 14 USART 1 */
+  void* pfnUSART2_Handler; /* 15 USART 2 */
+  void* pvReserved16;
+  void* pfnHSMCI_Handler;  /* 17 High Speed Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 18 Two-Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 19 Two-Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 20 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 21 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 22 Timer Counter 0 */
+  void* pfnTC1_Handler;    /* 23 Timer Counter 1 */
+  void* pfnTC2_Handler;    /* 24 Timer Counter 2 */
+  void* pfnPWM_Handler;    /* 25 Pulse Width Modulation Controller */
+  void* pfnADC12B_Handler; /* 26 12-bit ADC Controller */
+  void* pfnADC_Handler;    /* 27 10-bit ADC Controller */
+  void* pfnDMAC_Handler;   /* 28 DMA Controller */
+  void* pfnUDPHS_Handler;  /* 29 USB Device High Speed */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void ADC12B_Handler     ( void );
+void DMAC_Handler       ( void );
+void EFC0_Handler       ( void );
+void EFC1_Handler       ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART_Handler       ( void );
+void UDPHS_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3U1C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U1C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U1C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3u.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_adc12b.h"
+#include "component/component_chipid.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udphs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_udphs.h"
+#include "instance/instance_adc12b.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI    (20) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (21) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (22) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (23) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (24) /**< \brief Timer Counter 2 (TC2) */
+#define ID_PWM    (25) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
+#define ID_ADC    (27) /**< \brief 10-bit ADC Controller (ADC) */
+#define ID_DMAC   (28) /**< \brief DMA Controller (DMAC) */
+#define ID_UDPHS  (29) /**< \brief USB Device High Speed (UDPHS) */
+
+#define ID_PERIPH_COUNT (30) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS      (0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     (0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        (0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS      ((Udphs  *)0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     ((Adc12b *)0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B ((Pdc    *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        ((Adc    *)0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3u1c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x10000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (256u)
+#define IRAM0_SIZE               (0x2000u)
+#define IRAM1_SIZE               (0x2000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE)
+#define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR      (0x00180000u) /**< Internal ROM base address */
+#define IRAM0_ADDR     (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR     (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR   (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3U1C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (96000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (24000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (72000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (84000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3U1C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u1e.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u1e.h
new file mode 100644
index 0000000..f11a7ce
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u1e.h
@@ -0,0 +1,496 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U1E_
+#define _SAM3U1E_
+
+/** \addtogroup SAM3U1E_definitions SAM3U1E definitions
+  This file defines all structures and symbols for SAM3U1E:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1E_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3U1E specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3U1E Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3U1E Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3U1E Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3U1E Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3U1E Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3U1E Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3U1E Enhanced Embedded Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3U1E Enhanced Embedded Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3U1E Universal Asynchronous Receiver Transmitter (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3U1E Static Memory Controller (SMC) */
+  PIOA_IRQn            = 10, /**< 10 SAM3U1E Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 11, /**< 11 SAM3U1E Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 12, /**< 12 SAM3U1E Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 13, /**< 13 SAM3U1E USART 0 (USART0) */
+  USART1_IRQn          = 14, /**< 14 SAM3U1E USART 1 (USART1) */
+  USART2_IRQn          = 15, /**< 15 SAM3U1E USART 2 (USART2) */
+  USART3_IRQn          = 16, /**< 16 SAM3U1E USART 3 (USART3) */
+  HSMCI_IRQn           = 17, /**< 17 SAM3U1E High Speed Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 18, /**< 18 SAM3U1E Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 19, /**< 19 SAM3U1E Two-Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 20, /**< 20 SAM3U1E Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 21, /**< 21 SAM3U1E Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 22, /**< 22 SAM3U1E Timer Counter 0 (TC0) */
+  TC1_IRQn             = 23, /**< 23 SAM3U1E Timer Counter 1 (TC1) */
+  TC2_IRQn             = 24, /**< 24 SAM3U1E Timer Counter 2 (TC2) */
+  PWM_IRQn             = 25, /**< 25 SAM3U1E Pulse Width Modulation Controller (PWM) */
+  ADC12B_IRQn          = 26, /**< 26 SAM3U1E 12-bit ADC Controller (ADC12B) */
+  ADC_IRQn             = 27, /**< 27 SAM3U1E 10-bit ADC Controller (ADC) */
+  DMAC_IRQn            = 28, /**< 28 SAM3U1E DMA Controller (DMAC) */
+  UDPHS_IRQn           = 29, /**< 29 SAM3U1E USB Device High Speed (UDPHS) */
+
+  PERIPH_COUNT_IRQn    = 30  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC0_Handler;   /*  6 Enhanced Embedded Flash Controller 0 */
+  void* pfnEFC1_Handler;   /*  7 Enhanced Embedded Flash Controller 1 */
+  void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transmitter */
+  void* pfnSMC_Handler;    /*  9 Static Memory Controller */
+  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A, */
+  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 12 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 13 USART 0 */
+  void* pfnUSART1_Handler; /* 14 USART 1 */
+  void* pfnUSART2_Handler; /* 15 USART 2 */
+  void* pfnUSART3_Handler; /* 16 USART 3 */
+  void* pfnHSMCI_Handler;  /* 17 High Speed Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 18 Two-Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 19 Two-Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 20 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 21 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 22 Timer Counter 0 */
+  void* pfnTC1_Handler;    /* 23 Timer Counter 1 */
+  void* pfnTC2_Handler;    /* 24 Timer Counter 2 */
+  void* pfnPWM_Handler;    /* 25 Pulse Width Modulation Controller */
+  void* pfnADC12B_Handler; /* 26 12-bit ADC Controller */
+  void* pfnADC_Handler;    /* 27 10-bit ADC Controller */
+  void* pfnDMAC_Handler;   /* 28 DMA Controller */
+  void* pfnUDPHS_Handler;  /* 29 USB Device High Speed */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void ADC12B_Handler     ( void );
+void DMAC_Handler       ( void );
+void EFC0_Handler       ( void );
+void EFC1_Handler       ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART_Handler       ( void );
+void UDPHS_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void USART3_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3U1E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U1E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U1E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3u.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U1E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1E_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_adc12b.h"
+#include "component/component_chipid.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udphs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1E_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_usart3.h"
+#include "instance/instance_udphs.h"
+#include "instance/instance_adc12b.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1E_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (12) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
+#define ID_USART3 (16) /**< \brief USART 3 (USART3) */
+#define ID_HSMCI  (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI    (20) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (21) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (22) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (23) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (24) /**< \brief Timer Counter 2 (TC2) */
+#define ID_PWM    (25) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
+#define ID_ADC    (27) /**< \brief 10-bit ADC Controller (ADC) */
+#define ID_DMAC   (28) /**< \brief DMA Controller (DMAC) */
+#define ID_UDPHS  (29) /**< \brief USB Device High Speed (UDPHS) */
+
+#define ID_PERIPH_COUNT (30) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1E_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     (0x4009C000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 (0x4009C100U) /**< \brief (PDC_USART3) Base Address */
+#define UDPHS      (0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     (0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        (0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1000U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     ((Usart  *)0x4009C000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART3) Base Address */
+#define UDPHS      ((Udphs  *)0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     ((Adc12b *)0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B ((Pdc    *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        ((Adc    *)0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1000U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U1E_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3u1e.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x10000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (256u)
+#define IRAM0_SIZE               (0x2000u)
+#define IRAM1_SIZE               (0x2000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE)
+#define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR      (0x00180000u) /**< Internal ROM base address */
+#define IRAM0_ADDR     (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR     (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR   (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3U1E */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (96000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (24000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (72000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (84000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3U1E_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u2c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u2c.h
new file mode 100644
index 0000000..e71bb63
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u2c.h
@@ -0,0 +1,482 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U2C_
+#define _SAM3U2C_
+
+/** \addtogroup SAM3U2C_definitions SAM3U2C definitions
+  This file defines all structures and symbols for SAM3U2C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3U2C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3U2C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3U2C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3U2C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3U2C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3U2C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3U2C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3U2C Enhanced Embedded Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3U2C Enhanced Embedded Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3U2C Universal Asynchronous Receiver Transmitter (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3U2C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 10, /**< 10 SAM3U2C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 11, /**< 11 SAM3U2C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 13, /**< 13 SAM3U2C USART 0 (USART0) */
+  USART1_IRQn          = 14, /**< 14 SAM3U2C USART 1 (USART1) */
+  USART2_IRQn          = 15, /**< 15 SAM3U2C USART 2 (USART2) */
+  HSMCI_IRQn           = 17, /**< 17 SAM3U2C High Speed Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 18, /**< 18 SAM3U2C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 19, /**< 19 SAM3U2C Two-Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 20, /**< 20 SAM3U2C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 21, /**< 21 SAM3U2C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 22, /**< 22 SAM3U2C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 23, /**< 23 SAM3U2C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 24, /**< 24 SAM3U2C Timer Counter 2 (TC2) */
+  PWM_IRQn             = 25, /**< 25 SAM3U2C Pulse Width Modulation Controller (PWM) */
+  ADC12B_IRQn          = 26, /**< 26 SAM3U2C 12-bit ADC Controller (ADC12B) */
+  ADC_IRQn             = 27, /**< 27 SAM3U2C 10-bit ADC Controller (ADC) */
+  DMAC_IRQn            = 28, /**< 28 SAM3U2C DMA Controller (DMAC) */
+  UDPHS_IRQn           = 29, /**< 29 SAM3U2C USB Device High Speed (UDPHS) */
+
+  PERIPH_COUNT_IRQn    = 30  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC0_Handler;   /*  6 Enhanced Embedded Flash Controller 0 */
+  void* pfnEFC1_Handler;   /*  7 Enhanced Embedded Flash Controller 1 */
+  void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transmitter */
+  void* pfnSMC_Handler;    /*  9 Static Memory Controller */
+  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A, */
+  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
+  void* pvReserved12;
+  void* pfnUSART0_Handler; /* 13 USART 0 */
+  void* pfnUSART1_Handler; /* 14 USART 1 */
+  void* pfnUSART2_Handler; /* 15 USART 2 */
+  void* pvReserved16;
+  void* pfnHSMCI_Handler;  /* 17 High Speed Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 18 Two-Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 19 Two-Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 20 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 21 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 22 Timer Counter 0 */
+  void* pfnTC1_Handler;    /* 23 Timer Counter 1 */
+  void* pfnTC2_Handler;    /* 24 Timer Counter 2 */
+  void* pfnPWM_Handler;    /* 25 Pulse Width Modulation Controller */
+  void* pfnADC12B_Handler; /* 26 12-bit ADC Controller */
+  void* pfnADC_Handler;    /* 27 10-bit ADC Controller */
+  void* pfnDMAC_Handler;   /* 28 DMA Controller */
+  void* pfnUDPHS_Handler;  /* 29 USB Device High Speed */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void ADC12B_Handler     ( void );
+void DMAC_Handler       ( void );
+void EFC0_Handler       ( void );
+void EFC1_Handler       ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART_Handler       ( void );
+void UDPHS_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3U2C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U2C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U2C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3u.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_adc12b.h"
+#include "component/component_chipid.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udphs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_udphs.h"
+#include "instance/instance_adc12b.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI    (20) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (21) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (22) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (23) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (24) /**< \brief Timer Counter 2 (TC2) */
+#define ID_PWM    (25) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
+#define ID_ADC    (27) /**< \brief 10-bit ADC Controller (ADC) */
+#define ID_DMAC   (28) /**< \brief DMA Controller (DMAC) */
+#define ID_UDPHS  (29) /**< \brief USB Device High Speed (UDPHS) */
+
+#define ID_PERIPH_COUNT (30) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS      (0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     (0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        (0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS      ((Udphs  *)0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     ((Adc12b *)0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B ((Pdc    *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        ((Adc    *)0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3u2c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x4000u)
+#define IRAM1_SIZE               (0x4000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE)
+#define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR      (0x00180000u) /**< Internal ROM base address */
+#define IRAM0_ADDR     (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR     (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR   (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3U2C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (96000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (24000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (72000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (84000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3U2C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u2e.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u2e.h
new file mode 100644
index 0000000..f28d0d4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u2e.h
@@ -0,0 +1,496 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U2E_
+#define _SAM3U2E_
+
+/** \addtogroup SAM3U2E_definitions SAM3U2E definitions
+  This file defines all structures and symbols for SAM3U2E:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2E_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3U2E specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3U2E Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3U2E Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3U2E Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3U2E Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3U2E Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3U2E Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3U2E Enhanced Embedded Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3U2E Enhanced Embedded Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3U2E Universal Asynchronous Receiver Transmitter (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3U2E Static Memory Controller (SMC) */
+  PIOA_IRQn            = 10, /**< 10 SAM3U2E Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 11, /**< 11 SAM3U2E Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 12, /**< 12 SAM3U2E Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 13, /**< 13 SAM3U2E USART 0 (USART0) */
+  USART1_IRQn          = 14, /**< 14 SAM3U2E USART 1 (USART1) */
+  USART2_IRQn          = 15, /**< 15 SAM3U2E USART 2 (USART2) */
+  USART3_IRQn          = 16, /**< 16 SAM3U2E USART 3 (USART3) */
+  HSMCI_IRQn           = 17, /**< 17 SAM3U2E High Speed Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 18, /**< 18 SAM3U2E Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 19, /**< 19 SAM3U2E Two-Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 20, /**< 20 SAM3U2E Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 21, /**< 21 SAM3U2E Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 22, /**< 22 SAM3U2E Timer Counter 0 (TC0) */
+  TC1_IRQn             = 23, /**< 23 SAM3U2E Timer Counter 1 (TC1) */
+  TC2_IRQn             = 24, /**< 24 SAM3U2E Timer Counter 2 (TC2) */
+  PWM_IRQn             = 25, /**< 25 SAM3U2E Pulse Width Modulation Controller (PWM) */
+  ADC12B_IRQn          = 26, /**< 26 SAM3U2E 12-bit ADC Controller (ADC12B) */
+  ADC_IRQn             = 27, /**< 27 SAM3U2E 10-bit ADC Controller (ADC) */
+  DMAC_IRQn            = 28, /**< 28 SAM3U2E DMA Controller (DMAC) */
+  UDPHS_IRQn           = 29, /**< 29 SAM3U2E USB Device High Speed (UDPHS) */
+
+  PERIPH_COUNT_IRQn    = 30  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC0_Handler;   /*  6 Enhanced Embedded Flash Controller 0 */
+  void* pfnEFC1_Handler;   /*  7 Enhanced Embedded Flash Controller 1 */
+  void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transmitter */
+  void* pfnSMC_Handler;    /*  9 Static Memory Controller */
+  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A, */
+  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 12 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 13 USART 0 */
+  void* pfnUSART1_Handler; /* 14 USART 1 */
+  void* pfnUSART2_Handler; /* 15 USART 2 */
+  void* pfnUSART3_Handler; /* 16 USART 3 */
+  void* pfnHSMCI_Handler;  /* 17 High Speed Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 18 Two-Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 19 Two-Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 20 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 21 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 22 Timer Counter 0 */
+  void* pfnTC1_Handler;    /* 23 Timer Counter 1 */
+  void* pfnTC2_Handler;    /* 24 Timer Counter 2 */
+  void* pfnPWM_Handler;    /* 25 Pulse Width Modulation Controller */
+  void* pfnADC12B_Handler; /* 26 12-bit ADC Controller */
+  void* pfnADC_Handler;    /* 27 10-bit ADC Controller */
+  void* pfnDMAC_Handler;   /* 28 DMA Controller */
+  void* pfnUDPHS_Handler;  /* 29 USB Device High Speed */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void ADC12B_Handler     ( void );
+void DMAC_Handler       ( void );
+void EFC0_Handler       ( void );
+void EFC1_Handler       ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART_Handler       ( void );
+void UDPHS_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void USART3_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3U2E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U2E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U2E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3u.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U2E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2E_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_adc12b.h"
+#include "component/component_chipid.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udphs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2E_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_usart3.h"
+#include "instance/instance_udphs.h"
+#include "instance/instance_adc12b.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2E_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (12) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
+#define ID_USART3 (16) /**< \brief USART 3 (USART3) */
+#define ID_HSMCI  (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI    (20) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (21) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (22) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (23) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (24) /**< \brief Timer Counter 2 (TC2) */
+#define ID_PWM    (25) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
+#define ID_ADC    (27) /**< \brief 10-bit ADC Controller (ADC) */
+#define ID_DMAC   (28) /**< \brief DMA Controller (DMAC) */
+#define ID_UDPHS  (29) /**< \brief USB Device High Speed (UDPHS) */
+
+#define ID_PERIPH_COUNT (30) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2E_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     (0x4009C000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 (0x4009C100U) /**< \brief (PDC_USART3) Base Address */
+#define UDPHS      (0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     (0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        (0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1000U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     ((Usart  *)0x4009C000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART3) Base Address */
+#define UDPHS      ((Udphs  *)0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     ((Adc12b *)0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B ((Pdc    *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        ((Adc    *)0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1000U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U2E_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3u2e.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x4000u)
+#define IRAM1_SIZE               (0x4000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE)
+#define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR      (0x00180000u) /**< Internal ROM base address */
+#define IRAM0_ADDR     (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR     (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR   (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3U2E */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (96000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (24000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (72000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (84000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3U2E_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u4c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u4c.h
new file mode 100644
index 0000000..57ec710
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u4c.h
@@ -0,0 +1,487 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U4C_
+#define _SAM3U4C_
+
+/** \addtogroup SAM3U4C_definitions SAM3U4C definitions
+  This file defines all structures and symbols for SAM3U4C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3U4C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3U4C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3U4C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3U4C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3U4C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3U4C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3U4C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3U4C Enhanced Embedded Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3U4C Enhanced Embedded Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3U4C Universal Asynchronous Receiver Transmitter (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3U4C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 10, /**< 10 SAM3U4C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 11, /**< 11 SAM3U4C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 13, /**< 13 SAM3U4C USART 0 (USART0) */
+  USART1_IRQn          = 14, /**< 14 SAM3U4C USART 1 (USART1) */
+  USART2_IRQn          = 15, /**< 15 SAM3U4C USART 2 (USART2) */
+  HSMCI_IRQn           = 17, /**< 17 SAM3U4C High Speed Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 18, /**< 18 SAM3U4C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 19, /**< 19 SAM3U4C Two-Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 20, /**< 20 SAM3U4C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 21, /**< 21 SAM3U4C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 22, /**< 22 SAM3U4C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 23, /**< 23 SAM3U4C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 24, /**< 24 SAM3U4C Timer Counter 2 (TC2) */
+  PWM_IRQn             = 25, /**< 25 SAM3U4C Pulse Width Modulation Controller (PWM) */
+  ADC12B_IRQn          = 26, /**< 26 SAM3U4C 12-bit ADC Controller (ADC12B) */
+  ADC_IRQn             = 27, /**< 27 SAM3U4C 10-bit ADC Controller (ADC) */
+  DMAC_IRQn            = 28, /**< 28 SAM3U4C DMA Controller (DMAC) */
+  UDPHS_IRQn           = 29, /**< 29 SAM3U4C USB Device High Speed (UDPHS) */
+
+  PERIPH_COUNT_IRQn    = 30  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC0_Handler;   /*  6 Enhanced Embedded Flash Controller 0 */
+  void* pfnEFC1_Handler;   /*  7 Enhanced Embedded Flash Controller 1 */
+  void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transmitter */
+  void* pfnSMC_Handler;    /*  9 Static Memory Controller */
+  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A, */
+  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
+  void* pvReserved12;
+  void* pfnUSART0_Handler; /* 13 USART 0 */
+  void* pfnUSART1_Handler; /* 14 USART 1 */
+  void* pfnUSART2_Handler; /* 15 USART 2 */
+  void* pvReserved16;
+  void* pfnHSMCI_Handler;  /* 17 High Speed Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 18 Two-Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 19 Two-Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 20 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 21 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 22 Timer Counter 0 */
+  void* pfnTC1_Handler;    /* 23 Timer Counter 1 */
+  void* pfnTC2_Handler;    /* 24 Timer Counter 2 */
+  void* pfnPWM_Handler;    /* 25 Pulse Width Modulation Controller */
+  void* pfnADC12B_Handler; /* 26 12-bit ADC Controller */
+  void* pfnADC_Handler;    /* 27 10-bit ADC Controller */
+  void* pfnDMAC_Handler;   /* 28 DMA Controller */
+  void* pfnUDPHS_Handler;  /* 29 USB Device High Speed */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void ADC12B_Handler     ( void );
+void DMAC_Handler       ( void );
+void EFC0_Handler       ( void );
+void EFC1_Handler       ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART_Handler       ( void );
+void UDPHS_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3U4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U4C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3u.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_adc12b.h"
+#include "component/component_chipid.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udphs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_udphs.h"
+#include "instance/instance_adc12b.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI    (20) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (21) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (22) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (23) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (24) /**< \brief Timer Counter 2 (TC2) */
+#define ID_PWM    (25) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
+#define ID_ADC    (27) /**< \brief 10-bit ADC Controller (ADC) */
+#define ID_DMAC   (28) /**< \brief DMA Controller (DMAC) */
+#define ID_UDPHS  (29) /**< \brief USB Device High Speed (UDPHS) */
+
+#define ID_PERIPH_COUNT (30) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS      (0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     (0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        (0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define UDPHS      ((Udphs  *)0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     ((Adc12b *)0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B ((Pdc    *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        ((Adc    *)0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3u4c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (8192u)
+#define IFLASH1_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x8000u)
+#define IRAM1_SIZE               (0x4000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE+IFLASH1_SIZE)
+#define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
+#define IFLASH1_ADDR   (0x00100000u) /**< Internal Flash 1 base address */
+#define IROM_ADDR      (0x00180000u) /**< Internal ROM base address */
+#define IRAM0_ADDR     (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR     (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR   (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3U4C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (96000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (24000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (72000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (84000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3U4C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u4e.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u4e.h
new file mode 100644
index 0000000..e98ebb4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/sam3u4e.h
@@ -0,0 +1,501 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3U4E_
+#define _SAM3U4E_
+
+/** \addtogroup SAM3U4E_definitions SAM3U4E definitions
+  This file defines all structures and symbols for SAM3U4E:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4E_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3U4E specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3U4E Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3U4E Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3U4E Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3U4E Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3U4E Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3U4E Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3U4E Enhanced Embedded Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3U4E Enhanced Embedded Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3U4E Universal Asynchronous Receiver Transmitter (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3U4E Static Memory Controller (SMC) */
+  PIOA_IRQn            = 10, /**< 10 SAM3U4E Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 11, /**< 11 SAM3U4E Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 12, /**< 12 SAM3U4E Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 13, /**< 13 SAM3U4E USART 0 (USART0) */
+  USART1_IRQn          = 14, /**< 14 SAM3U4E USART 1 (USART1) */
+  USART2_IRQn          = 15, /**< 15 SAM3U4E USART 2 (USART2) */
+  USART3_IRQn          = 16, /**< 16 SAM3U4E USART 3 (USART3) */
+  HSMCI_IRQn           = 17, /**< 17 SAM3U4E High Speed Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 18, /**< 18 SAM3U4E Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 19, /**< 19 SAM3U4E Two-Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 20, /**< 20 SAM3U4E Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 21, /**< 21 SAM3U4E Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 22, /**< 22 SAM3U4E Timer Counter 0 (TC0) */
+  TC1_IRQn             = 23, /**< 23 SAM3U4E Timer Counter 1 (TC1) */
+  TC2_IRQn             = 24, /**< 24 SAM3U4E Timer Counter 2 (TC2) */
+  PWM_IRQn             = 25, /**< 25 SAM3U4E Pulse Width Modulation Controller (PWM) */
+  ADC12B_IRQn          = 26, /**< 26 SAM3U4E 12-bit ADC Controller (ADC12B) */
+  ADC_IRQn             = 27, /**< 27 SAM3U4E 10-bit ADC Controller (ADC) */
+  DMAC_IRQn            = 28, /**< 28 SAM3U4E DMA Controller (DMAC) */
+  UDPHS_IRQn           = 29, /**< 29 SAM3U4E USB Device High Speed (UDPHS) */
+
+  PERIPH_COUNT_IRQn    = 30  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC0_Handler;   /*  6 Enhanced Embedded Flash Controller 0 */
+  void* pfnEFC1_Handler;   /*  7 Enhanced Embedded Flash Controller 1 */
+  void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transmitter */
+  void* pfnSMC_Handler;    /*  9 Static Memory Controller */
+  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A, */
+  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 12 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 13 USART 0 */
+  void* pfnUSART1_Handler; /* 14 USART 1 */
+  void* pfnUSART2_Handler; /* 15 USART 2 */
+  void* pfnUSART3_Handler; /* 16 USART 3 */
+  void* pfnHSMCI_Handler;  /* 17 High Speed Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 18 Two-Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 19 Two-Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 20 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 21 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 22 Timer Counter 0 */
+  void* pfnTC1_Handler;    /* 23 Timer Counter 1 */
+  void* pfnTC2_Handler;    /* 24 Timer Counter 2 */
+  void* pfnPWM_Handler;    /* 25 Pulse Width Modulation Controller */
+  void* pfnADC12B_Handler; /* 26 12-bit ADC Controller */
+  void* pfnADC_Handler;    /* 27 10-bit ADC Controller */
+  void* pfnDMAC_Handler;   /* 28 DMA Controller */
+  void* pfnUDPHS_Handler;  /* 29 USB Device High Speed */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void ADC12B_Handler     ( void );
+void DMAC_Handler       ( void );
+void EFC0_Handler       ( void );
+void EFC1_Handler       ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART_Handler       ( void );
+void UDPHS_Handler      ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void USART3_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3U4E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U4E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U4E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3u.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4E_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_adc12b.h"
+#include "component/component_chipid.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udphs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4E_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_usart3.h"
+#include "instance/instance_udphs.h"
+#include "instance/instance_adc12b.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4E_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (12) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
+#define ID_USART3 (16) /**< \brief USART 3 (USART3) */
+#define ID_HSMCI  (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (18) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (19) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI    (20) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (21) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (22) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (23) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (24) /**< \brief Timer Counter 2 (TC2) */
+#define ID_PWM    (25) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
+#define ID_ADC    (27) /**< \brief 10-bit ADC Controller (ADC) */
+#define ID_DMAC   (28) /**< \brief DMA Controller (DMAC) */
+#define ID_UDPHS  (29) /**< \brief USB Device High Speed (UDPHS) */
+
+#define ID_PERIPH_COUNT (30) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4E_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       (0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     (0x4009C000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 (0x4009C100U) /**< \brief (PDC_USART3) Base Address */
+#define UDPHS      (0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     (0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B (0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        (0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1000U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TWI0       ((Twi    *)0x40084000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40084100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40088000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40088100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x4008C000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x4008C100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40090000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40090100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40094000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40094100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x40098000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     ((Usart  *)0x4009C000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART3) Base Address */
+#define UDPHS      ((Udphs  *)0x400A4000U) /**< \brief (UDPHS     ) Base Address */
+#define ADC12B     ((Adc12b *)0x400A8000U) /**< \brief (ADC12B    ) Base Address */
+#define PDC_ADC12B ((Pdc    *)0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
+#define ADC        ((Adc    *)0x400AC000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400AC100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400B0000U) /**< \brief (DMAC      ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0600U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0800U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0A00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0C00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E0E00U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1000U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1200U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1210U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1230U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1250U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1260U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1290U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3U4E_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3u4e.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (8192u)
+#define IFLASH1_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x8000u)
+#define IRAM1_SIZE               (0x4000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE+IFLASH1_SIZE)
+#define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
+#define IFLASH1_ADDR   (0x00100000u) /**< Internal Flash 1 base address */
+#define IROM_ADDR      (0x00180000u) /**< Internal ROM base address */
+#define IRAM0_ADDR     (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR     (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR   (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3U4E */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (96000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (24000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (72000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (84000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3U4E_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/system_sam3u.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/system_sam3u.h
new file mode 100644
index 0000000..9456a8e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/include/system_sam3u.h
@@ -0,0 +1,58 @@
+/*! \file *********************************************************************
+ *
+ * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
+ *           for SAM3 devices.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef SYSTEM_SAM3U_H_INCLUDED
+#define SYSTEM_SAM3U_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#include 
+
+extern uint32_t SystemCoreClock;	/* System Clock Frequency (Core Clock) */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock with current core Clock 
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+/** 
+ * Initialize flash.
+ */
+void system_init_flash(uint32_t dw_clk);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* SYSTEM_SAM3U_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1_flash.ld
new file mode 100644
index 0000000..b69fc17
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1_flash.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rw) : ORIGIN = 0x00080000, LENGTH = 0x00010000 /* Flash0, 64K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00002000 /* Sram1, 8K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007E000, LENGTH = 0x00004000 /* sram, 16K */
+
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00010000 /* Flash0, 64K */
+	ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3u_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1_sram.ld
new file mode 100644
index 0000000..114b154
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1_sram.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00010000 /* Flash, 64K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00002000 /* Sram1, 8K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007E000, LENGTH = 0x00004000 /* sram, 16K */
+
+	rom (rx)    : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+	ram (rwx)   : ORIGIN = 0x20080000, LENGTH = 0x00002000 /* Sram1, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x900 ;
+
+INCLUDE sam3u_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1c_flash.ld
new file mode 100644
index 0000000..1c8225f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1c_sram.ld
new file mode 100644
index 0000000..33bb304
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1e_flash.ld
new file mode 100644
index 0000000..1c8225f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1e_sram.ld
new file mode 100644
index 0000000..33bb304
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u1e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2_flash.ld
new file mode 100644
index 0000000..ab3edff
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2_flash.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x00004000 /* sram, 32K */
+
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3u_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2_sram.ld
new file mode 100644
index 0000000..2a5b4bf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2_sram.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x00004000 /* sram, 32K */
+
+	rom (rx)    : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+	ram (rwx)   : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x900;
+
+INCLUDE sam3u_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2c_flash.ld
new file mode 100644
index 0000000..80c386c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2c_sram.ld
new file mode 100644
index 0000000..9a90683
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2e_flash.ld
new file mode 100644
index 0000000..80c386c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2e_sram.ld
new file mode 100644
index 0000000..9a90683
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u2e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4_flash.ld
new file mode 100644
index 0000000..519a170
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4_flash.ld
@@ -0,0 +1,52 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	flash1 (rx) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+
+	unified_flash (rx) : ORIGIN = 0x000E0000, LENGTH = 0x00040000 /* Flash, 256K */
+	unified_ram (rwx)  : ORIGIN = 0x20078000, LENGTH = 0x0000C000 /* sram, 48K */
+  
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3u_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4_sram.ld
new file mode 100644
index 0000000..6ff57bb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4_sram.ld
@@ -0,0 +1,52 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* flash0, 128K */
+	flash1 (rx) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* flash1, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* sram1, 16K */
+
+	unified_flash (rx) : ORIGIN = 0x000E0000, LENGTH = 0x00040000 /* Flash, 256K */
+	unified_ram (rwx)  : ORIGIN = 0x20078000, LENGTH = 0x0000C000 /* sram, 48K */
+
+	rom (rx)    : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	ram (rwx)   : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* sram1, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x900;
+
+INCLUDE sam3u_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4c_flash.ld
new file mode 100644
index 0000000..1123d51
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4c_sram.ld
new file mode 100644
index 0000000..eb224ce
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4e_flash.ld
new file mode 100644
index 0000000..1123d51
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4e_sram.ld
new file mode 100644
index 0000000..eb224ce
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u4e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/sam3u_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/startup_sam3u.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/startup_sam3u.c
new file mode 100644
index 0000000..6e03ffd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/as_gcc/startup_sam3u.c
@@ -0,0 +1,212 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3u.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3U_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3U_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART2_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3U_USART3_INSTANCE_
+void USART3_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3U_USART3_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC12B_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDPHS_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC0_Handler,    /* 6  EFC 0 */
+	(void*) EFC1_Handler,    /* 7  EFC 1 */
+	(void*) UART_Handler,    /* 8  UART */
+	(void*) SMC_Handler,     /* 9  SMC */
+	(void*) PIOA_Handler,    /* 10 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 11 Parallel IO Controller B */
+#ifdef _SAM3U_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 12 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 12 Reserved */
+#endif /* _SAM3U_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 13 USART 0 */
+	(void*) USART1_Handler,  /* 14 USART 1 */
+	(void*) USART2_Handler,  /* 15 USART 2 */
+#ifdef _SAM3U_USART3_INSTANCE_
+	(void*) USART3_Handler,  /* 16 USART 3 */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3U_USART3_INSTANCE_ */
+	(void*) HSMCI_Handler,   /* 17 MCI */
+	(void*) TWI0_Handler,    /* 18 TWI 0 */
+	(void*) TWI1_Handler,    /* 19 TWI 1 */
+	(void*) SPI_Handler,     /* 20 SPI */
+	(void*) SSC_Handler,     /* 21 SSC */
+	(void*) TC0_Handler,     /* 22 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 23 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 24 Timer Counter 2 */
+	(void*) PWM_Handler,     /* 25 PWM */
+	(void*) ADC12B_Handler,  /* 26 ADC12B controller */
+	(void*) ADC_Handler,     /* 27 ADC controller */
+	(void*) DMAC_Handler,    /* 28 DMA controller */
+	(void*) UDPHS_Handler    /* 29 USB High Speed Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < IRAM0_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1_flash.ld
new file mode 100644
index 0000000..b69fc17
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1_flash.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rw) : ORIGIN = 0x00080000, LENGTH = 0x00010000 /* Flash0, 64K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00002000 /* Sram1, 8K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007E000, LENGTH = 0x00004000 /* sram, 16K */
+
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00010000 /* Flash0, 64K */
+	ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3u_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1_sram.ld
new file mode 100644
index 0000000..114b154
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1_sram.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00010000 /* Flash, 64K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00002000 /* Sram1, 8K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007E000, LENGTH = 0x00004000 /* sram, 16K */
+
+	rom (rx)    : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+	ram (rwx)   : ORIGIN = 0x20080000, LENGTH = 0x00002000 /* Sram1, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x900 ;
+
+INCLUDE sam3u_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1c_flash.ld
new file mode 100644
index 0000000..1c8225f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1c_sram.ld
new file mode 100644
index 0000000..33bb304
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1e_flash.ld
new file mode 100644
index 0000000..1c8225f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1e_sram.ld
new file mode 100644
index 0000000..33bb304
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u1e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2_flash.ld
new file mode 100644
index 0000000..ab3edff
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2_flash.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x00004000 /* sram, 32K */
+
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3u_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2_sram.ld
new file mode 100644
index 0000000..2a5b4bf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2_sram.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x00004000 /* sram, 32K */
+
+	rom (rx)    : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+	ram (rwx)   : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x900;
+
+INCLUDE sam3u_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2c_flash.ld
new file mode 100644
index 0000000..80c386c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2c_sram.ld
new file mode 100644
index 0000000..9a90683
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2e_flash.ld
new file mode 100644
index 0000000..80c386c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2e_sram.ld
new file mode 100644
index 0000000..9a90683
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u2e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4_flash.ld
new file mode 100644
index 0000000..519a170
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4_flash.ld
@@ -0,0 +1,52 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	flash1 (rx) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+
+	unified_flash (rx) : ORIGIN = 0x000E0000, LENGTH = 0x00040000 /* Flash, 256K */
+	unified_ram (rwx)  : ORIGIN = 0x20078000, LENGTH = 0x0000C000 /* sram, 48K */
+  
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3u_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4_sram.ld
new file mode 100644
index 0000000..6ff57bb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4_sram.ld
@@ -0,0 +1,52 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* flash0, 128K */
+	flash1 (rx) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* flash1, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* sram1, 16K */
+
+	unified_flash (rx) : ORIGIN = 0x000E0000, LENGTH = 0x00040000 /* Flash, 256K */
+	unified_ram (rwx)  : ORIGIN = 0x20078000, LENGTH = 0x0000C000 /* sram, 48K */
+
+	rom (rx)    : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	ram (rwx)   : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* sram1, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x900;
+
+INCLUDE sam3u_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4c_flash.ld
new file mode 100644
index 0000000..1123d51
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4c_sram.ld
new file mode 100644
index 0000000..eb224ce
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4e_flash.ld
new file mode 100644
index 0000000..1123d51
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4e_sram.ld
new file mode 100644
index 0000000..eb224ce
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u4e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/sam3u_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/startup_sam3u.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/startup_sam3u.c
new file mode 100644
index 0000000..6e03ffd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc/startup_sam3u.c
@@ -0,0 +1,212 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3u.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3U_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3U_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART2_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3U_USART3_INSTANCE_
+void USART3_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3U_USART3_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC12B_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDPHS_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC0_Handler,    /* 6  EFC 0 */
+	(void*) EFC1_Handler,    /* 7  EFC 1 */
+	(void*) UART_Handler,    /* 8  UART */
+	(void*) SMC_Handler,     /* 9  SMC */
+	(void*) PIOA_Handler,    /* 10 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 11 Parallel IO Controller B */
+#ifdef _SAM3U_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 12 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 12 Reserved */
+#endif /* _SAM3U_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 13 USART 0 */
+	(void*) USART1_Handler,  /* 14 USART 1 */
+	(void*) USART2_Handler,  /* 15 USART 2 */
+#ifdef _SAM3U_USART3_INSTANCE_
+	(void*) USART3_Handler,  /* 16 USART 3 */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3U_USART3_INSTANCE_ */
+	(void*) HSMCI_Handler,   /* 17 MCI */
+	(void*) TWI0_Handler,    /* 18 TWI 0 */
+	(void*) TWI1_Handler,    /* 19 TWI 1 */
+	(void*) SPI_Handler,     /* 20 SPI */
+	(void*) SSC_Handler,     /* 21 SSC */
+	(void*) TC0_Handler,     /* 22 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 23 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 24 Timer Counter 2 */
+	(void*) PWM_Handler,     /* 25 PWM */
+	(void*) ADC12B_Handler,  /* 26 ADC12B controller */
+	(void*) ADC_Handler,     /* 27 ADC controller */
+	(void*) DMAC_Handler,    /* 28 DMA controller */
+	(void*) UDPHS_Handler    /* 29 USB High Speed Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < IRAM0_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1_flash.ld
new file mode 100644
index 0000000..b69fc17
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1_flash.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rw) : ORIGIN = 0x00080000, LENGTH = 0x00010000 /* Flash0, 64K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00002000 /* Sram1, 8K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007E000, LENGTH = 0x00004000 /* sram, 16K */
+
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00010000 /* Flash0, 64K */
+	ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3u_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1_sram.ld
new file mode 100644
index 0000000..114b154
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1_sram.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00010000 /* Flash, 64K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00002000 /* Sram1, 8K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007E000, LENGTH = 0x00004000 /* sram, 16K */
+
+	rom (rx)    : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+	ram (rwx)   : ORIGIN = 0x20080000, LENGTH = 0x00002000 /* Sram1, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x900 ;
+
+INCLUDE sam3u_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1c_flash.ld
new file mode 100644
index 0000000..1c8225f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1c_sram.ld
new file mode 100644
index 0000000..33bb304
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1e_flash.ld
new file mode 100644
index 0000000..1c8225f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1e_sram.ld
new file mode 100644
index 0000000..33bb304
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u1e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2_flash.ld
new file mode 100644
index 0000000..ab3edff
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2_flash.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x00004000 /* sram, 32K */
+
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3u_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2_sram.ld
new file mode 100644
index 0000000..2a5b4bf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2_sram.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x00004000 /* sram, 32K */
+
+	rom (rx)    : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+	ram (rwx)   : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x900;
+
+INCLUDE sam3u_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2c_flash.ld
new file mode 100644
index 0000000..80c386c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2c_sram.ld
new file mode 100644
index 0000000..9a90683
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2e_flash.ld
new file mode 100644
index 0000000..80c386c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2e_sram.ld
new file mode 100644
index 0000000..9a90683
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u2e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4_flash.ld
new file mode 100644
index 0000000..519a170
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4_flash.ld
@@ -0,0 +1,52 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	flash1 (rx) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+
+	unified_flash (rx) : ORIGIN = 0x000E0000, LENGTH = 0x00040000 /* Flash, 256K */
+	unified_ram (rwx)  : ORIGIN = 0x20078000, LENGTH = 0x0000C000 /* sram, 48K */
+  
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3u_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4_sram.ld
new file mode 100644
index 0000000..6ff57bb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4_sram.ld
@@ -0,0 +1,52 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* flash0, 128K */
+	flash1 (rx) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* flash1, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* sram1, 16K */
+
+	unified_flash (rx) : ORIGIN = 0x000E0000, LENGTH = 0x00040000 /* Flash, 256K */
+	unified_ram (rwx)  : ORIGIN = 0x20078000, LENGTH = 0x0000C000 /* sram, 48K */
+
+	rom (rx)    : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	ram (rwx)   : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* sram1, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x900;
+
+INCLUDE sam3u_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4c_flash.ld
new file mode 100644
index 0000000..1123d51
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4c_sram.ld
new file mode 100644
index 0000000..eb224ce
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4e_flash.ld
new file mode 100644
index 0000000..1123d51
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4e_sram.ld
new file mode 100644
index 0000000..eb224ce
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u4e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/sam3u_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/startup_sam3u.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/startup_sam3u.c
new file mode 100644
index 0000000..6e03ffd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_arm/startup_sam3u.c
@@ -0,0 +1,212 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3u.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3U_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3U_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART2_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3U_USART3_INSTANCE_
+void USART3_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3U_USART3_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC12B_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDPHS_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC0_Handler,    /* 6  EFC 0 */
+	(void*) EFC1_Handler,    /* 7  EFC 1 */
+	(void*) UART_Handler,    /* 8  UART */
+	(void*) SMC_Handler,     /* 9  SMC */
+	(void*) PIOA_Handler,    /* 10 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 11 Parallel IO Controller B */
+#ifdef _SAM3U_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 12 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 12 Reserved */
+#endif /* _SAM3U_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 13 USART 0 */
+	(void*) USART1_Handler,  /* 14 USART 1 */
+	(void*) USART2_Handler,  /* 15 USART 2 */
+#ifdef _SAM3U_USART3_INSTANCE_
+	(void*) USART3_Handler,  /* 16 USART 3 */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3U_USART3_INSTANCE_ */
+	(void*) HSMCI_Handler,   /* 17 MCI */
+	(void*) TWI0_Handler,    /* 18 TWI 0 */
+	(void*) TWI1_Handler,    /* 19 TWI 1 */
+	(void*) SPI_Handler,     /* 20 SPI */
+	(void*) SSC_Handler,     /* 21 SSC */
+	(void*) TC0_Handler,     /* 22 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 23 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 24 Timer Counter 2 */
+	(void*) PWM_Handler,     /* 25 PWM */
+	(void*) ADC12B_Handler,  /* 26 ADC12B controller */
+	(void*) ADC_Handler,     /* 27 ADC controller */
+	(void*) DMAC_Handler,    /* 28 DMA controller */
+	(void*) UDPHS_Handler    /* 29 USB High Speed Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < IRAM0_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1_flash.ld
new file mode 100644
index 0000000..b69fc17
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1_flash.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rw) : ORIGIN = 0x00080000, LENGTH = 0x00010000 /* Flash0, 64K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00002000 /* Sram1, 8K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007E000, LENGTH = 0x00004000 /* sram, 16K */
+
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00010000 /* Flash0, 64K */
+	ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3u_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1_sram.ld
new file mode 100644
index 0000000..114b154
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1_sram.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00010000 /* Flash, 64K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00002000 /* Sram1, 8K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007E000, LENGTH = 0x00004000 /* sram, 16K */
+
+	rom (rx)    : ORIGIN = 0x20000000, LENGTH = 0x00002000 /* Sram0, 8K */
+	ram (rwx)   : ORIGIN = 0x20080000, LENGTH = 0x00002000 /* Sram1, 8K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x900 ;
+
+INCLUDE sam3u_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1c_flash.ld
new file mode 100644
index 0000000..1c8225f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1c_sram.ld
new file mode 100644
index 0000000..33bb304
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1e_flash.ld
new file mode 100644
index 0000000..1c8225f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1e_sram.ld
new file mode 100644
index 0000000..33bb304
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u1e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u1_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2_flash.ld
new file mode 100644
index 0000000..ab3edff
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2_flash.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x00004000 /* sram, 32K */
+
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3u_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2_sram.ld
new file mode 100644
index 0000000..2a5b4bf
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2_sram.ld
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+
+	unified_ram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x00004000 /* sram, 32K */
+
+	rom (rx)    : ORIGIN = 0x20000000, LENGTH = 0x00004000 /* Sram0, 16K */
+	ram (rwx)   : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x900;
+
+INCLUDE sam3u_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2c_flash.ld
new file mode 100644
index 0000000..80c386c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2c_sram.ld
new file mode 100644
index 0000000..9a90683
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2e_flash.ld
new file mode 100644
index 0000000..80c386c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2e_sram.ld
new file mode 100644
index 0000000..9a90683
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u2e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u2_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4_flash.ld
new file mode 100644
index 0000000..519a170
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4_flash.ld
@@ -0,0 +1,52 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	flash1 (rx) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */
+
+	unified_flash (rx) : ORIGIN = 0x000E0000, LENGTH = 0x00040000 /* Flash, 256K */
+	unified_ram (rwx)  : ORIGIN = 0x20078000, LENGTH = 0x0000C000 /* sram, 48K */
+  
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */
+	ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3u_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4_sram.ld
new file mode 100644
index 0000000..6ff57bb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4_sram.ld
@@ -0,0 +1,52 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	flash0 (rx) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* flash0, 128K */
+	flash1 (rx) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* flash1, 128K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* sram1, 16K */
+
+	unified_flash (rx) : ORIGIN = 0x000E0000, LENGTH = 0x00040000 /* Flash, 256K */
+	unified_ram (rwx)  : ORIGIN = 0x20078000, LENGTH = 0x0000C000 /* sram, 48K */
+
+	rom (rx)    : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	ram (rwx)   : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* sram1, 16K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x900;
+
+INCLUDE sam3u_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4c_flash.ld
new file mode 100644
index 0000000..1123d51
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4c_sram.ld
new file mode 100644
index 0000000..eb224ce
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4e_flash.ld
new file mode 100644
index 0000000..1123d51
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4e_sram.ld
new file mode 100644
index 0000000..eb224ce
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u4e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3u4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/sam3u_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/startup_sam3u.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/startup_sam3u.c
new file mode 100644
index 0000000..6e03ffd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/gcc_atmel/startup_sam3u.c
@@ -0,0 +1,212 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3u.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3U_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3U_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART2_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3U_USART3_INSTANCE_
+void USART3_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3U_USART3_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC12B_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDPHS_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC0_Handler,    /* 6  EFC 0 */
+	(void*) EFC1_Handler,    /* 7  EFC 1 */
+	(void*) UART_Handler,    /* 8  UART */
+	(void*) SMC_Handler,     /* 9  SMC */
+	(void*) PIOA_Handler,    /* 10 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 11 Parallel IO Controller B */
+#ifdef _SAM3U_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 12 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 12 Reserved */
+#endif /* _SAM3U_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 13 USART 0 */
+	(void*) USART1_Handler,  /* 14 USART 1 */
+	(void*) USART2_Handler,  /* 15 USART 2 */
+#ifdef _SAM3U_USART3_INSTANCE_
+	(void*) USART3_Handler,  /* 16 USART 3 */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3U_USART3_INSTANCE_ */
+	(void*) HSMCI_Handler,   /* 17 MCI */
+	(void*) TWI0_Handler,    /* 18 TWI 0 */
+	(void*) TWI1_Handler,    /* 19 TWI 1 */
+	(void*) SPI_Handler,     /* 20 SPI */
+	(void*) SSC_Handler,     /* 21 SSC */
+	(void*) TC0_Handler,     /* 22 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 23 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 24 Timer Counter 2 */
+	(void*) PWM_Handler,     /* 25 PWM */
+	(void*) ADC12B_Handler,  /* 26 ADC12B controller */
+	(void*) ADC_Handler,     /* 27 ADC controller */
+	(void*) DMAC_Handler,    /* 28 DMA controller */
+	(void*) UDPHS_Handler    /* 29 USB High Speed Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < IRAM0_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u1_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u1_flash.icf
new file mode 100644
index 0000000..6fc4902
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u1_flash.icf
@@ -0,0 +1,46 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00080000; /*Add for CMSIS*/
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20000FFF;
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;
+define symbol __ICFEDIT_region_ROM0_start__  = 0x00080000;
+define symbol __ICFEDIT_region_ROM0_end__    = 0x0008FFFF;
+/*-Sizes-*/
+/*define symbol __ICFEDIT_size_cstack__        = 0x1000;*//*for nandflash*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/*-Specials-*/
+/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/
+/*define symbol __ICFEDIT_size_vectors__          = 0x100;*/ /*Referenced for CMSIS*/
+/*-Exports-*/
+/*export symbol __ICFEDIT_region_RAM_VECT_start__;*/
+export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/ /*Referenced for CMSIS*/
+/*define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/
+define region ROM0_region     = mem:[from __ICFEDIT_region_ROM0_start__ to __ICFEDIT_region_ROM0_end__];
+
+/*define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { };*/
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+/*place at start of ROM0_region { readonly section .vectors };*/ /*Referenced for CMSIS*/
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec }; /*Add for CMSIS*/
+place in ROM0_region          { readonly };
+place in RAM0_region          { readwrite, block HEAP };
+place in RAM1_region          { block CSTACK }; /* for nandflash*/
+/*place in RAM_VECT_region      { block RamVect };*/ /*Referenced for CMSIS*/
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u1_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u1_sram.icf
new file mode 100644
index 0000000..da701dd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u1_sram.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20000FFF;
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x900;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/*-Exports-*/
+export symbol __ICFEDIT_vector_start__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in RAM0_region          { readonly };
+place in RAM1_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u2_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u2_flash.icf
new file mode 100644
index 0000000..9b0f5fb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u2_flash.icf
@@ -0,0 +1,46 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00080000; /*Add for CMSIS*/
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20003FFF;
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;
+define symbol __ICFEDIT_region_ROM0_start__  = 0x00080000;
+define symbol __ICFEDIT_region_ROM0_end__    = 0x0009FFFF;
+/*-Sizes-*/
+/*define symbol __ICFEDIT_size_cstack__        = 0x1000;*//*for nandflash*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/*-Specials-*/
+/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/
+/*define symbol __ICFEDIT_size_vectors__          = 0x100;*/ /*Referenced for CMSIS*/
+/*-Exports-*/
+/*export symbol __ICFEDIT_region_RAM_VECT_start__;*/
+export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/ /*Referenced for CMSIS*/
+/*define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/
+define region ROM0_region     = mem:[from __ICFEDIT_region_ROM0_start__ to __ICFEDIT_region_ROM0_end__];
+
+/*define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { };*/
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+/*place at start of ROM0_region { readonly section .vectors };*/ /*Referenced for CMSIS*/
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec }; /*Add for CMSIS*/
+place in ROM0_region          { readonly };
+place in RAM0_region          { readwrite, block HEAP };
+place in RAM1_region          { block CSTACK }; /* for nandflash*/
+/*place in RAM_VECT_region      { block RamVect };*/ /*Referenced for CMSIS*/
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u2_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u2_sram.icf
new file mode 100644
index 0000000..2248a3f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u2_sram.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20003FFF;
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x900;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/*-Exports-*/
+export symbol __ICFEDIT_vector_start__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in RAM0_region          { readonly };
+place in RAM1_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u4_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u4_flash.icf
new file mode 100644
index 0000000..956230f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u4_flash.icf
@@ -0,0 +1,49 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00080000; /*Add for CMSIS*/
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20007FFF;
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;
+define symbol __ICFEDIT_region_ROM0_start__  = 0x00080000;
+define symbol __ICFEDIT_region_ROM0_end__    = 0x0009FFFF;
+define symbol __ICFEDIT_region_ROM1_start__  = 0x00100000;
+define symbol __ICFEDIT_region_ROM1_end__    = 0x0011FFFF;
+/*-Sizes-*/
+/*define symbol __ICFEDIT_size_cstack__        = 0x1000;*//*for nandflash*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/*-Specials-*/
+/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/
+/*define symbol __ICFEDIT_size_vectors__          = 0x100;*/ /*Referenced for CMSIS*/
+/*-Exports-*/
+/*export symbol __ICFEDIT_region_RAM_VECT_start__;*/
+export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/ /*Referenced for CMSIS*/
+/*define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/
+define region ROM0_region     = mem:[from __ICFEDIT_region_ROM0_start__ to __ICFEDIT_region_ROM0_end__];
+define region ROM1_region     = mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__];
+
+/*define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { };*/
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+/*place at start of ROM0_region { readonly section .vectors };*/ /*Referenced for CMSIS*/
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec }; /*Add for CMSIS*/
+place in ROM0_region          { readonly };
+place in RAM0_region          { readwrite, block HEAP };
+place in RAM1_region          { block CSTACK }; /* for nandflash*/
+/*place in RAM_VECT_region      { block RamVect };*/ /*Referenced for CMSIS*/
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u4_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u4_sram.icf
new file mode 100644
index 0000000..d7d3353
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/sam3u4_sram.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20007FFF;
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x900;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/*-Exports-*/
+export symbol __ICFEDIT_vector_start__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in RAM0_region          { readonly };
+place in RAM1_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/startup_sam3u.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/startup_sam3u.c
new file mode 100644
index 0000000..c08ee65
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/iar/startup_sam3u.c
@@ -0,0 +1,189 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3u.h"
+
+/* Initialize segments */
+extern uint32_t __cstack_start__;
+extern uint32_t __cstack_end__;
+
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+#pragma weak Reset_Handler
+#pragma weak NMI_Handler=Dummy_Handler
+#pragma weak HardFault_Handler=Dummy_Handler
+#pragma weak MemManage_Handler=Dummy_Handler
+#pragma weak BusFault_Handler=Dummy_Handler
+#pragma weak UsageFault_Handler=Dummy_Handler
+#pragma weak SVC_Handler=Dummy_Handler
+#pragma weak DebugMon_Handler=Dummy_Handler
+#pragma weak PendSV_Handler=Dummy_Handler
+#pragma weak SysTick_Handler=Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak ADC_Handler=Dummy_Handler
+#pragma weak ADC12B_Handler=Dummy_Handler
+#pragma weak DMAC_Handler=Dummy_Handler
+#pragma weak EFC0_Handler=Dummy_Handler
+#pragma weak EFC1_Handler=Dummy_Handler
+#pragma weak HSMCI_Handler=Dummy_Handler
+#pragma weak PIOA_Handler=Dummy_Handler
+#pragma weak PIOB_Handler=Dummy_Handler
+#pragma weak PIOC_Handler=Dummy_Handler
+#pragma weak PMC_Handler=Dummy_Handler
+#pragma weak PWM_Handler=Dummy_Handler
+#pragma weak RSTC_Handler=Dummy_Handler
+#pragma weak RTC_Handler=Dummy_Handler
+#pragma weak RTT_Handler=Dummy_Handler
+#pragma weak SMC_Handler=Dummy_Handler
+#pragma weak SPI_Handler=Dummy_Handler
+#pragma weak SSC_Handler=Dummy_Handler
+#pragma weak SUPC_Handler=Dummy_Handler
+#pragma weak TC0_Handler=Dummy_Handler
+#pragma weak TC1_Handler=Dummy_Handler
+#pragma weak TC2_Handler=Dummy_Handler
+#pragma weak TWI0_Handler=Dummy_Handler
+#pragma weak TWI1_Handler=Dummy_Handler
+#pragma weak UART_Handler=Dummy_Handler
+#pragma weak UDPHS_Handler=Dummy_Handler
+#pragma weak USART0_Handler=Dummy_Handler
+#pragma weak USART1_Handler=Dummy_Handler
+#pragma weak USART2_Handler=Dummy_Handler
+#pragma weak USART3_Handler=Dummy_Handler
+#pragma weak WDT_Handler=Dummy_Handler
+
+/* Exception Table */
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section = ".intvec"
+#pragma location = ".intvec"
+const DeviceVectors __vector_table[] = {
+	(void*) (&__cstack_end__),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC0_Handler,    /* 6  EEFC 0 */
+	(void*) EFC1_Handler,    /* 7  EEFC 1 */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) SMC_Handler,     /* 9  SMC */
+	(void*) PIOA_Handler,    /* 10 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 11 Parallel IO Controller B */
+#ifdef _SAM3U_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 12 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 12 Reserved */
+#endif /* _SAM3U_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 13 USART 0 */
+	(void*) USART1_Handler,  /* 14 USART 1 */
+	(void*) USART2_Handler,  /* 15 USART 2 */
+#ifdef _SAM3U_USART3_INSTANCE_
+	(void*) USART3_Handler,  /* 16 USART 3 */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3U_USART3_INSTANCE_ */
+	(void*) HSMCI_Handler,   /* 17 MCI */
+	(void*) TWI0_Handler,    /* 18 TWI 0 */
+	(void*) TWI1_Handler,    /* 19 TWI 1 */
+	(void*) SPI_Handler,     /* 20 SPI */
+	(void*) SSC_Handler,     /* 21 SSC */
+	(void*) TC0_Handler,     /* 22 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 23 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 24 Timer Counter 2 */
+	(void*) PWM_Handler,     /* 25 PWM */
+	(void*) ADC12B_Handler,  /* 26 ADC12B controller */
+	(void*) ADC_Handler,     /* 27 ADC controller */
+	(void*) DMAC_Handler,    /* 28 DMA controller */
+	(void*) UDPHS_Handler    /* 29 USB High Speed Port */
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+	uint32_t *pSrc = __section_begin(".intvec");
+
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < IRAM0_ADDR + IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+	__iar_program_start();
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/system_sam3u.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/system_sam3u.c
new file mode 100644
index 0000000..784edf2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3u/source/system_sam3u.c
@@ -0,0 +1,201 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3u.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Clock settings (96MHz) */
+#define SYS_BOARD_OSCOUNT   (CKGR_MOR_MOSCXTST(0x8UL))
+#define SYS_BOARD_PLLAR     (CKGR_PLLAR_ONE \
+							| CKGR_PLLAR_MULA(0xfUL) \
+							| CKGR_PLLAR_PLLACOUNT(0x3fUL) \
+							| CKGR_PLLAR_DIVA(0x1UL))
+#define SYS_BOARD_MCKR      (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)
+
+/* Clock Definitions */
+#define SYS_UTMIPLL     		(480000000UL)	/* UTMI PLL frequency */
+
+#define SYS_CKGR_MOR_KEY_VALUE	CKGR_MOR_KEY(0x37UL) /* Key to unlock MOR register */
+
+/* FIXME: should be generated by sock */
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+/**
+ * \brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit(void)
+{
+	/* Set FWS according to SYS_BOARD_MCKR configuration */
+	EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
+	EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
+
+	/* Initialize main oscillator */
+	if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
+		PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
+			                     CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+		while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
+		}
+	}
+
+	/* Switch to 3-20MHz Xtal oscillator */
+	PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN |
+                             CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+
+	while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
+	}
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Initialize PLLA */
+	PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
+	while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
+	}
+
+	/* Switch to main clock */
+	PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Switch to PLLA */
+	PMC->PMC_MCKR = SYS_BOARD_MCKR;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	SystemCoreClock = CHIP_FREQ_CPU_MAX;
+}
+
+void SystemCoreClockUpdate(void)
+{
+	/* Determine clock frequency according to clock register values */
+	switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
+	case PMC_MCKR_CSS_SLOW_CLK:	/* Slow clock */
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_32K;
+		} else {
+			SystemCoreClock = CHIP_FREQ_SLCK_RC;
+		}
+		break;
+	case PMC_MCKR_CSS_MAIN_CLK:	/* Main clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	case PMC_MCKR_CSS_PLLA_CLK:	/* PLLA clock */
+	case PMC_MCKR_CSS_UPLL_CLK:	/* UPLL clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
+			SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
+				                          CKGR_PLLAR_MULA_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
+				                           CKGR_PLLAR_DIVA_Pos));
+		} else {
+			SystemCoreClock = SYS_UTMIPLL / 2U;
+		}
+		break;
+	}
+
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
+		SystemCoreClock /= 3U;
+	} else {
+		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
+	}
+}
+
+/**
+ * Initialize flash.
+ */
+void system_init_flash(uint32_t dw_clk)
+{
+	/* Set FWS for embedded Flash access according to operating frequency */
+	if (dw_clk < CHIP_FREQ_FWS_0) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
+	} else if (dw_clk < CHIP_FREQ_FWS_1) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(1);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(1);
+	} else if (dw_clk < CHIP_FREQ_FWS_2) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(2);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(2);
+	} else if (dw_clk < CHIP_FREQ_FWS_3) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(3);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(3);
+	} else {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
+	}
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_adc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_adc.h
new file mode 100644
index 0000000..695dea3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_adc.h
@@ -0,0 +1,504 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_ADC_COMPONENT_
+#define _SAM3XA_ADC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_ADC Analog-to-digital Converter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Adc hardware registers */
+typedef struct {
+  WoReg ADC_CR;        /**< \brief (Adc Offset: 0x00) Control Register */
+  RwReg ADC_MR;        /**< \brief (Adc Offset: 0x04) Mode Register */
+  RwReg ADC_SEQR1;     /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
+  RwReg ADC_SEQR2;     /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
+  WoReg ADC_CHER;      /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+  WoReg ADC_CHDR;      /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+  RoReg ADC_CHSR;      /**< \brief (Adc Offset: 0x18) Channel Status Register */
+  RoReg Reserved1[1];
+  RoReg ADC_LCDR;      /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+  WoReg ADC_IER;       /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC_IDR;       /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC_IMR;       /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC_ISR;       /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[2];
+  RoReg ADC_OVER;      /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
+  RwReg ADC_EMR;       /**< \brief (Adc Offset: 0x40) Extended Mode Register */
+  RwReg ADC_CWR;       /**< \brief (Adc Offset: 0x44) Compare Window Register */
+  RwReg ADC_CGR;       /**< \brief (Adc Offset: 0x48) Channel Gain Register */
+  RwReg ADC_COR;       /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
+  RoReg ADC_CDR[16];   /**< \brief (Adc Offset: 0x50) Channel Data Register */
+  RoReg Reserved3[1];
+  RwReg ADC_ACR;       /**< \brief (Adc Offset: 0x94) Analog Control Register */
+  RoReg Reserved4[19];
+  RwReg ADC_WPMR;      /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ADC_WPSR;      /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved5[5];
+  RwReg ADC_RPR;       /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+  RwReg ADC_RCR;       /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+  RoReg Reserved6[2];
+  RwReg ADC_RNPR;      /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC_RNCR;      /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+  RoReg Reserved7[2];
+  WoReg ADC_PTCR;      /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+  RoReg ADC_PTSR;      /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define   ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define   ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External : ADCTRG */
+#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 1 */
+#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 2 */
+#define   ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
+#define   ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */
+#define   ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define   ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
+#define   ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
+#define   ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
+#define   ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */
+#define   ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */
+#define   ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define   ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */
+#define ADC_MR_SETTLING_Pos 20
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */
+#define   ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */
+#define   ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */
+#define   ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */
+#define ADC_MR_TRACKTIM_Pos 24
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
+#define ADC_MR_TRANSFER_Pos 28
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
+#define   ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */
+#define   ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
+#define ADC_SEQR1_USCH1_Pos 0
+#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
+#define ADC_SEQR1_USCH2_Pos 4
+#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
+#define ADC_SEQR1_USCH3_Pos 8
+#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
+#define ADC_SEQR1_USCH4_Pos 12
+#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
+#define ADC_SEQR1_USCH5_Pos 16
+#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
+#define ADC_SEQR1_USCH6_Pos 20
+#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
+#define ADC_SEQR1_USCH7_Pos 24
+#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
+#define ADC_SEQR1_USCH8_Pos 28
+#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
+#define ADC_SEQR2_USCH9_Pos 0
+#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
+#define ADC_SEQR2_USCH10_Pos 4
+#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
+#define ADC_SEQR2_USCH11_Pos 8
+#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
+#define ADC_SEQR2_USCH12_Pos 12
+#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
+#define ADC_SEQR2_USCH13_Pos 16
+#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
+#define ADC_SEQR2_USCH14_Pos 20
+#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
+#define ADC_SEQR2_USCH15_Pos 24
+#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
+#define ADC_SEQR2_USCH16_Pos 28
+#define ADC_SEQR2_USCH16_Msk (0xfu << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+#define ADC_LCDR_CHNB_Pos 12
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
+#define ADC_EMR_CMPMODE_Pos 0
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
+#define   ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define   ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
+#define   ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
+#define ADC_EMR_CMPSEL_Pos 4
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
+#define ADC_EMR_CMPFILTER_Pos 12
+#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */
+#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos)))
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
+#define ADC_CWR_LOWTHRES_Pos 0
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
+#define ADC_CWR_HIGHTHRES_Pos 16
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
+#define ADC_CGR_GAIN0_Pos 0
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))
+#define ADC_CGR_GAIN1_Pos 2
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))
+#define ADC_CGR_GAIN2_Pos 4
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))
+#define ADC_CGR_GAIN3_Pos 6
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))
+#define ADC_CGR_GAIN4_Pos 8
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))
+#define ADC_CGR_GAIN5_Pos 10
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))
+#define ADC_CGR_GAIN6_Pos 12
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))
+#define ADC_CGR_GAIN7_Pos 14
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))
+#define ADC_CGR_GAIN8_Pos 16
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))
+#define ADC_CGR_GAIN9_Pos 18
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))
+#define ADC_CGR_GAIN10_Pos 20
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))
+#define ADC_CGR_GAIN11_Pos 22
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))
+#define ADC_CGR_GAIN12_Pos 24
+#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */
+#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))
+#define ADC_CGR_GAIN13_Pos 26
+#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */
+#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))
+#define ADC_CGR_GAIN14_Pos 28
+#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */
+#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))
+#define ADC_CGR_GAIN15_Pos 30
+#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */
+#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */
+#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */
+#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */
+#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */
+#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */
+#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */
+#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */
+#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */
+#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */
+/* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[16]) Converted Data */
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
+#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */
+#define ADC_ACR_IBCTL_Pos 8
+#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */
+#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
+#define ADC_WPMR_WPKEY_Pos 8
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
+#define ADC_WPSR_WPVSRC_Pos 8
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_ADC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_can.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_can.h
new file mode 100644
index 0000000..cafb8fb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_can.h
@@ -0,0 +1,298 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CAN_COMPONENT_
+#define _SAM3XA_CAN_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Controller Area Network */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_CAN Controller Area Network */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief CanMb hardware registers */
+typedef struct {
+  RwReg  CAN_MMR;       /**< \brief (CanMb Offset: 0x0) Mailbox Mode Register */
+  RwReg  CAN_MAM;       /**< \brief (CanMb Offset: 0x4) Mailbox Acceptance Mask Register */
+  RwReg  CAN_MID;       /**< \brief (CanMb Offset: 0x8) Mailbox ID Register */
+  RwReg  CAN_MFID;      /**< \brief (CanMb Offset: 0xC) Mailbox Family ID Register */
+  RwReg  CAN_MSR;       /**< \brief (CanMb Offset: 0x10) Mailbox Status Register */
+  RwReg  CAN_MDL;       /**< \brief (CanMb Offset: 0x14) Mailbox Data Low Register */
+  RwReg  CAN_MDH;       /**< \brief (CanMb Offset: 0x18) Mailbox Data High Register */
+  RwReg  CAN_MCR;       /**< \brief (CanMb Offset: 0x1C) Mailbox Control Register */
+} CanMb;
+/** \brief Can hardware registers */
+#define CANMB_NUMBER 8
+typedef struct {
+  RwReg  CAN_MR;        /**< \brief (Can Offset: 0x0000) Mode Register */
+  WoReg  CAN_IER;       /**< \brief (Can Offset: 0x0004) Interrupt Enable Register */
+  WoReg  CAN_IDR;       /**< \brief (Can Offset: 0x0008) Interrupt Disable Register */
+  RoReg  CAN_IMR;       /**< \brief (Can Offset: 0x000C) Interrupt Mask Register */
+  RoReg  CAN_SR;        /**< \brief (Can Offset: 0x0010) Status Register */
+  RwReg  CAN_BR;        /**< \brief (Can Offset: 0x0014) Baudrate Register */
+  RoReg  CAN_TIM;       /**< \brief (Can Offset: 0x0018) Timer Register */
+  RoReg  CAN_TIMESTP;   /**< \brief (Can Offset: 0x001C) Timestamp Register */
+  RoReg  CAN_ECR;       /**< \brief (Can Offset: 0x0020) Error Counter Register */
+  WoReg  CAN_TCR;       /**< \brief (Can Offset: 0x0024) Transfer Command Register */
+  WoReg  CAN_ACR;       /**< \brief (Can Offset: 0x0028) Abort Command Register */
+  RoReg  Reserved1[46];
+  RwReg  CAN_WPMR;      /**< \brief (Can Offset: 0x00E4) Write Protect Mode Register */
+  RoReg  CAN_WPSR;      /**< \brief (Can Offset: 0x00E8) Write Protect Status Register */
+  RoReg  Reserved2[69];
+  CanMb  CAN_MB[CANMB_NUMBER]; /**< \brief (Can Offset: 0x200) MB = 0 .. 7 */
+} Can;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CAN_MR : (CAN Offset: 0x0000) Mode Register -------- */
+#define CAN_MR_CANEN (0x1u << 0) /**< \brief (CAN_MR) CAN Controller Enable */
+#define CAN_MR_LPM (0x1u << 1) /**< \brief (CAN_MR) Disable/Enable Low Power Mode */
+#define CAN_MR_ABM (0x1u << 2) /**< \brief (CAN_MR) Disable/Enable Autobaud/Listen mode */
+#define CAN_MR_OVL (0x1u << 3) /**< \brief (CAN_MR) Disable/Enable Overload Frame */
+#define CAN_MR_TEOF (0x1u << 4) /**< \brief (CAN_MR) Timestamp messages at each end of Frame */
+#define CAN_MR_TTM (0x1u << 5) /**< \brief (CAN_MR) Disable/Enable Time Triggered Mode */
+#define CAN_MR_TIMFRZ (0x1u << 6) /**< \brief (CAN_MR) Enable Timer Freeze */
+#define CAN_MR_DRPT (0x1u << 7) /**< \brief (CAN_MR) Disable Repeat */
+#define CAN_MR_RXSYNC_Pos 24
+#define CAN_MR_RXSYNC_Msk (0x7u << CAN_MR_RXSYNC_Pos) /**< \brief (CAN_MR) Reception Synchronization Stage (not readable) */
+#define   CAN_MR_RXSYNC_DOUBLE_PP (0x0u << 24) /**< \brief (CAN_MR) Rx Signal with Double Synchro Stages (2 Positive Edges) */
+#define   CAN_MR_RXSYNC_DOUBLE_PN (0x1u << 24) /**< \brief (CAN_MR) Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge) */
+#define   CAN_MR_RXSYNC_SINGLE_P (0x2u << 24) /**< \brief (CAN_MR) Rx Signal with Single Synchro Stage (Positive Edge) */
+#define   CAN_MR_RXSYNC_NONE (0x3u << 24) /**< \brief (CAN_MR) Rx Signal with No Synchro Stage */
+/* -------- CAN_IER : (CAN Offset: 0x0004) Interrupt Enable Register -------- */
+#define CAN_IER_MB0 (0x1u << 0) /**< \brief (CAN_IER) Mailbox 0 Interrupt Enable */
+#define CAN_IER_MB1 (0x1u << 1) /**< \brief (CAN_IER) Mailbox 1 Interrupt Enable */
+#define CAN_IER_MB2 (0x1u << 2) /**< \brief (CAN_IER) Mailbox 2 Interrupt Enable */
+#define CAN_IER_MB3 (0x1u << 3) /**< \brief (CAN_IER) Mailbox 3 Interrupt Enable */
+#define CAN_IER_MB4 (0x1u << 4) /**< \brief (CAN_IER) Mailbox 4 Interrupt Enable */
+#define CAN_IER_MB5 (0x1u << 5) /**< \brief (CAN_IER) Mailbox 5 Interrupt Enable */
+#define CAN_IER_MB6 (0x1u << 6) /**< \brief (CAN_IER) Mailbox 6 Interrupt Enable */
+#define CAN_IER_MB7 (0x1u << 7) /**< \brief (CAN_IER) Mailbox 7 Interrupt Enable */
+#define CAN_IER_ERRA (0x1u << 16) /**< \brief (CAN_IER) Error Active Mode Interrupt Enable */
+#define CAN_IER_WARN (0x1u << 17) /**< \brief (CAN_IER) Warning Limit Interrupt Enable */
+#define CAN_IER_ERRP (0x1u << 18) /**< \brief (CAN_IER) Error Passive Mode Interrupt Enable */
+#define CAN_IER_BOFF (0x1u << 19) /**< \brief (CAN_IER) Bus Off Mode Interrupt Enable */
+#define CAN_IER_SLEEP (0x1u << 20) /**< \brief (CAN_IER) Sleep Interrupt Enable */
+#define CAN_IER_WAKEUP (0x1u << 21) /**< \brief (CAN_IER) Wakeup Interrupt Enable */
+#define CAN_IER_TOVF (0x1u << 22) /**< \brief (CAN_IER) Timer Overflow Interrupt Enable */
+#define CAN_IER_TSTP (0x1u << 23) /**< \brief (CAN_IER) TimeStamp Interrupt Enable */
+#define CAN_IER_CERR (0x1u << 24) /**< \brief (CAN_IER) CRC Error Interrupt Enable */
+#define CAN_IER_SERR (0x1u << 25) /**< \brief (CAN_IER) Stuffing Error Interrupt Enable */
+#define CAN_IER_AERR (0x1u << 26) /**< \brief (CAN_IER) Acknowledgment Error Interrupt Enable */
+#define CAN_IER_FERR (0x1u << 27) /**< \brief (CAN_IER) Form Error Interrupt Enable */
+#define CAN_IER_BERR (0x1u << 28) /**< \brief (CAN_IER) Bit Error Interrupt Enable */
+/* -------- CAN_IDR : (CAN Offset: 0x0008) Interrupt Disable Register -------- */
+#define CAN_IDR_MB0 (0x1u << 0) /**< \brief (CAN_IDR) Mailbox 0 Interrupt Disable */
+#define CAN_IDR_MB1 (0x1u << 1) /**< \brief (CAN_IDR) Mailbox 1 Interrupt Disable */
+#define CAN_IDR_MB2 (0x1u << 2) /**< \brief (CAN_IDR) Mailbox 2 Interrupt Disable */
+#define CAN_IDR_MB3 (0x1u << 3) /**< \brief (CAN_IDR) Mailbox 3 Interrupt Disable */
+#define CAN_IDR_MB4 (0x1u << 4) /**< \brief (CAN_IDR) Mailbox 4 Interrupt Disable */
+#define CAN_IDR_MB5 (0x1u << 5) /**< \brief (CAN_IDR) Mailbox 5 Interrupt Disable */
+#define CAN_IDR_MB6 (0x1u << 6) /**< \brief (CAN_IDR) Mailbox 6 Interrupt Disable */
+#define CAN_IDR_MB7 (0x1u << 7) /**< \brief (CAN_IDR) Mailbox 7 Interrupt Disable */
+#define CAN_IDR_ERRA (0x1u << 16) /**< \brief (CAN_IDR) Error Active Mode Interrupt Disable */
+#define CAN_IDR_WARN (0x1u << 17) /**< \brief (CAN_IDR) Warning Limit Interrupt Disable */
+#define CAN_IDR_ERRP (0x1u << 18) /**< \brief (CAN_IDR) Error Passive Mode Interrupt Disable */
+#define CAN_IDR_BOFF (0x1u << 19) /**< \brief (CAN_IDR) Bus Off Mode Interrupt Disable */
+#define CAN_IDR_SLEEP (0x1u << 20) /**< \brief (CAN_IDR) Sleep Interrupt Disable */
+#define CAN_IDR_WAKEUP (0x1u << 21) /**< \brief (CAN_IDR) Wakeup Interrupt Disable */
+#define CAN_IDR_TOVF (0x1u << 22) /**< \brief (CAN_IDR) Timer Overflow Interrupt */
+#define CAN_IDR_TSTP (0x1u << 23) /**< \brief (CAN_IDR) TimeStamp Interrupt Disable */
+#define CAN_IDR_CERR (0x1u << 24) /**< \brief (CAN_IDR) CRC Error Interrupt Disable */
+#define CAN_IDR_SERR (0x1u << 25) /**< \brief (CAN_IDR) Stuffing Error Interrupt Disable */
+#define CAN_IDR_AERR (0x1u << 26) /**< \brief (CAN_IDR) Acknowledgment Error Interrupt Disable */
+#define CAN_IDR_FERR (0x1u << 27) /**< \brief (CAN_IDR) Form Error Interrupt Disable */
+#define CAN_IDR_BERR (0x1u << 28) /**< \brief (CAN_IDR) Bit Error Interrupt Disable */
+/* -------- CAN_IMR : (CAN Offset: 0x000C) Interrupt Mask Register -------- */
+#define CAN_IMR_MB0 (0x1u << 0) /**< \brief (CAN_IMR) Mailbox 0 Interrupt Mask */
+#define CAN_IMR_MB1 (0x1u << 1) /**< \brief (CAN_IMR) Mailbox 1 Interrupt Mask */
+#define CAN_IMR_MB2 (0x1u << 2) /**< \brief (CAN_IMR) Mailbox 2 Interrupt Mask */
+#define CAN_IMR_MB3 (0x1u << 3) /**< \brief (CAN_IMR) Mailbox 3 Interrupt Mask */
+#define CAN_IMR_MB4 (0x1u << 4) /**< \brief (CAN_IMR) Mailbox 4 Interrupt Mask */
+#define CAN_IMR_MB5 (0x1u << 5) /**< \brief (CAN_IMR) Mailbox 5 Interrupt Mask */
+#define CAN_IMR_MB6 (0x1u << 6) /**< \brief (CAN_IMR) Mailbox 6 Interrupt Mask */
+#define CAN_IMR_MB7 (0x1u << 7) /**< \brief (CAN_IMR) Mailbox 7 Interrupt Mask */
+#define CAN_IMR_ERRA (0x1u << 16) /**< \brief (CAN_IMR) Error Active Mode Interrupt Mask */
+#define CAN_IMR_WARN (0x1u << 17) /**< \brief (CAN_IMR) Warning Limit Interrupt Mask */
+#define CAN_IMR_ERRP (0x1u << 18) /**< \brief (CAN_IMR) Error Passive Mode Interrupt Mask */
+#define CAN_IMR_BOFF (0x1u << 19) /**< \brief (CAN_IMR) Bus Off Mode Interrupt Mask */
+#define CAN_IMR_SLEEP (0x1u << 20) /**< \brief (CAN_IMR) Sleep Interrupt Mask */
+#define CAN_IMR_WAKEUP (0x1u << 21) /**< \brief (CAN_IMR) Wakeup Interrupt Mask */
+#define CAN_IMR_TOVF (0x1u << 22) /**< \brief (CAN_IMR) Timer Overflow Interrupt Mask */
+#define CAN_IMR_TSTP (0x1u << 23) /**< \brief (CAN_IMR) Timestamp Interrupt Mask */
+#define CAN_IMR_CERR (0x1u << 24) /**< \brief (CAN_IMR) CRC Error Interrupt Mask */
+#define CAN_IMR_SERR (0x1u << 25) /**< \brief (CAN_IMR) Stuffing Error Interrupt Mask */
+#define CAN_IMR_AERR (0x1u << 26) /**< \brief (CAN_IMR) Acknowledgment Error Interrupt Mask */
+#define CAN_IMR_FERR (0x1u << 27) /**< \brief (CAN_IMR) Form Error Interrupt Mask */
+#define CAN_IMR_BERR (0x1u << 28) /**< \brief (CAN_IMR) Bit Error Interrupt Mask */
+/* -------- CAN_SR : (CAN Offset: 0x0010) Status Register -------- */
+#define CAN_SR_MB0 (0x1u << 0) /**< \brief (CAN_SR) Mailbox 0 Event */
+#define CAN_SR_MB1 (0x1u << 1) /**< \brief (CAN_SR) Mailbox 1 Event */
+#define CAN_SR_MB2 (0x1u << 2) /**< \brief (CAN_SR) Mailbox 2 Event */
+#define CAN_SR_MB3 (0x1u << 3) /**< \brief (CAN_SR) Mailbox 3 Event */
+#define CAN_SR_MB4 (0x1u << 4) /**< \brief (CAN_SR) Mailbox 4 Event */
+#define CAN_SR_MB5 (0x1u << 5) /**< \brief (CAN_SR) Mailbox 5 Event */
+#define CAN_SR_MB6 (0x1u << 6) /**< \brief (CAN_SR) Mailbox 6 Event */
+#define CAN_SR_MB7 (0x1u << 7) /**< \brief (CAN_SR) Mailbox 7 Event */
+#define CAN_SR_ERRA (0x1u << 16) /**< \brief (CAN_SR) Error Active Mode */
+#define CAN_SR_WARN (0x1u << 17) /**< \brief (CAN_SR) Warning Limit */
+#define CAN_SR_ERRP (0x1u << 18) /**< \brief (CAN_SR) Error Passive Mode */
+#define CAN_SR_BOFF (0x1u << 19) /**< \brief (CAN_SR) Bus Off Mode */
+#define CAN_SR_SLEEP (0x1u << 20) /**< \brief (CAN_SR) CAN controller in Low power Mode */
+#define CAN_SR_WAKEUP (0x1u << 21) /**< \brief (CAN_SR) CAN controller is not in Low power Mode */
+#define CAN_SR_TOVF (0x1u << 22) /**< \brief (CAN_SR) Timer Overflow */
+#define CAN_SR_TSTP (0x1u << 23) /**< \brief (CAN_SR)  */
+#define CAN_SR_CERR (0x1u << 24) /**< \brief (CAN_SR) Mailbox CRC Error */
+#define CAN_SR_SERR (0x1u << 25) /**< \brief (CAN_SR) Mailbox Stuffing Error */
+#define CAN_SR_AERR (0x1u << 26) /**< \brief (CAN_SR) Acknowledgment Error */
+#define CAN_SR_FERR (0x1u << 27) /**< \brief (CAN_SR) Form Error */
+#define CAN_SR_BERR (0x1u << 28) /**< \brief (CAN_SR) Bit Error */
+#define CAN_SR_RBSY (0x1u << 29) /**< \brief (CAN_SR) Receiver busy */
+#define CAN_SR_TBSY (0x1u << 30) /**< \brief (CAN_SR) Transmitter busy */
+#define CAN_SR_OVLSY (0x1u << 31) /**< \brief (CAN_SR) Overload busy */
+/* -------- CAN_BR : (CAN Offset: 0x0014) Baudrate Register -------- */
+#define CAN_BR_PHASE2_Pos 0
+#define CAN_BR_PHASE2_Msk (0x7u << CAN_BR_PHASE2_Pos) /**< \brief (CAN_BR) Phase 2 segment */
+#define CAN_BR_PHASE2(value) ((CAN_BR_PHASE2_Msk & ((value) << CAN_BR_PHASE2_Pos)))
+#define CAN_BR_PHASE1_Pos 4
+#define CAN_BR_PHASE1_Msk (0x7u << CAN_BR_PHASE1_Pos) /**< \brief (CAN_BR) Phase 1 segment */
+#define CAN_BR_PHASE1(value) ((CAN_BR_PHASE1_Msk & ((value) << CAN_BR_PHASE1_Pos)))
+#define CAN_BR_PROPAG_Pos 8
+#define CAN_BR_PROPAG_Msk (0x7u << CAN_BR_PROPAG_Pos) /**< \brief (CAN_BR) Programming time segment */
+#define CAN_BR_PROPAG(value) ((CAN_BR_PROPAG_Msk & ((value) << CAN_BR_PROPAG_Pos)))
+#define CAN_BR_SJW_Pos 12
+#define CAN_BR_SJW_Msk (0x3u << CAN_BR_SJW_Pos) /**< \brief (CAN_BR) Re-synchronization jump width */
+#define CAN_BR_SJW(value) ((CAN_BR_SJW_Msk & ((value) << CAN_BR_SJW_Pos)))
+#define CAN_BR_BRP_Pos 16
+#define CAN_BR_BRP_Msk (0x7fu << CAN_BR_BRP_Pos) /**< \brief (CAN_BR) Baudrate Prescaler. */
+#define CAN_BR_BRP(value) ((CAN_BR_BRP_Msk & ((value) << CAN_BR_BRP_Pos)))
+#define CAN_BR_SMP (0x1u << 24) /**< \brief (CAN_BR) Sampling Mode */
+#define   CAN_BR_SMP_ONCE (0x0u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled once at sample point. */
+#define   CAN_BR_SMP_THREE (0x1u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. */
+/* -------- CAN_TIM : (CAN Offset: 0x0018) Timer Register -------- */
+#define CAN_TIM_TIMER_Pos 0
+#define CAN_TIM_TIMER_Msk (0xffffu << CAN_TIM_TIMER_Pos) /**< \brief (CAN_TIM) Timer */
+/* -------- CAN_TIMESTP : (CAN Offset: 0x001C) Timestamp Register -------- */
+#define CAN_TIMESTP_MTIMESTAMP_Pos 0
+#define CAN_TIMESTP_MTIMESTAMP_Msk (0xffffu << CAN_TIMESTP_MTIMESTAMP_Pos) /**< \brief (CAN_TIMESTP) Timestamp */
+/* -------- CAN_ECR : (CAN Offset: 0x0020) Error Counter Register -------- */
+#define CAN_ECR_REC_Pos 0
+#define CAN_ECR_REC_Msk (0xffu << CAN_ECR_REC_Pos) /**< \brief (CAN_ECR) Receive Error Counter */
+#define CAN_ECR_TEC_Pos 16
+#define CAN_ECR_TEC_Msk (0xffu << CAN_ECR_TEC_Pos) /**< \brief (CAN_ECR) Transmit Error Counter */
+/* -------- CAN_TCR : (CAN Offset: 0x0024) Transfer Command Register -------- */
+#define CAN_TCR_MB0 (0x1u << 0) /**< \brief (CAN_TCR) Transfer Request for Mailbox 0 */
+#define CAN_TCR_MB1 (0x1u << 1) /**< \brief (CAN_TCR) Transfer Request for Mailbox 1 */
+#define CAN_TCR_MB2 (0x1u << 2) /**< \brief (CAN_TCR) Transfer Request for Mailbox 2 */
+#define CAN_TCR_MB3 (0x1u << 3) /**< \brief (CAN_TCR) Transfer Request for Mailbox 3 */
+#define CAN_TCR_MB4 (0x1u << 4) /**< \brief (CAN_TCR) Transfer Request for Mailbox 4 */
+#define CAN_TCR_MB5 (0x1u << 5) /**< \brief (CAN_TCR) Transfer Request for Mailbox 5 */
+#define CAN_TCR_MB6 (0x1u << 6) /**< \brief (CAN_TCR) Transfer Request for Mailbox 6 */
+#define CAN_TCR_MB7 (0x1u << 7) /**< \brief (CAN_TCR) Transfer Request for Mailbox 7 */
+#define CAN_TCR_TIMRST (0x1u << 31) /**< \brief (CAN_TCR) Timer Reset */
+/* -------- CAN_ACR : (CAN Offset: 0x0028) Abort Command Register -------- */
+#define CAN_ACR_MB0 (0x1u << 0) /**< \brief (CAN_ACR) Abort Request for Mailbox 0 */
+#define CAN_ACR_MB1 (0x1u << 1) /**< \brief (CAN_ACR) Abort Request for Mailbox 1 */
+#define CAN_ACR_MB2 (0x1u << 2) /**< \brief (CAN_ACR) Abort Request for Mailbox 2 */
+#define CAN_ACR_MB3 (0x1u << 3) /**< \brief (CAN_ACR) Abort Request for Mailbox 3 */
+#define CAN_ACR_MB4 (0x1u << 4) /**< \brief (CAN_ACR) Abort Request for Mailbox 4 */
+#define CAN_ACR_MB5 (0x1u << 5) /**< \brief (CAN_ACR) Abort Request for Mailbox 5 */
+#define CAN_ACR_MB6 (0x1u << 6) /**< \brief (CAN_ACR) Abort Request for Mailbox 6 */
+#define CAN_ACR_MB7 (0x1u << 7) /**< \brief (CAN_ACR) Abort Request for Mailbox 7 */
+/* -------- CAN_WPMR : (CAN Offset: 0x00E4) Write Protect Mode Register -------- */
+#define CAN_WPMR_WPEN (0x1u << 0) /**< \brief (CAN_WPMR) Write Protection Enable */
+#define CAN_WPMR_WPKEY_Pos 8
+#define CAN_WPMR_WPKEY_Msk (0xffffffu << CAN_WPMR_WPKEY_Pos) /**< \brief (CAN_WPMR) SPI Write Protection Key Password */
+#define CAN_WPMR_WPKEY(value) ((CAN_WPMR_WPKEY_Msk & ((value) << CAN_WPMR_WPKEY_Pos)))
+/* -------- CAN_WPSR : (CAN Offset: 0x00E8) Write Protect Status Register -------- */
+#define CAN_WPSR_WPVS (0x1u << 0) /**< \brief (CAN_WPSR) Write Protection Violation Status */
+#define CAN_WPSR_WPVSRC_Pos 8
+#define CAN_WPSR_WPVSRC_Msk (0xffu << CAN_WPSR_WPVSRC_Pos) /**< \brief (CAN_WPSR) Write Protection Violation Source */
+/* -------- CAN_MMR : (CAN Offset: N/A) Mailbox Mode Register -------- */
+#define CAN_MMR_MTIMEMARK_Pos 0
+#define CAN_MMR_MTIMEMARK_Msk (0xffffu << CAN_MMR_MTIMEMARK_Pos) /**< \brief (CAN_MMR) Mailbox Timemark */
+#define CAN_MMR_MTIMEMARK(value) ((CAN_MMR_MTIMEMARK_Msk & ((value) << CAN_MMR_MTIMEMARK_Pos)))
+#define CAN_MMR_PRIOR_Pos 16
+#define CAN_MMR_PRIOR_Msk (0xfu << CAN_MMR_PRIOR_Pos) /**< \brief (CAN_MMR) Mailbox Priority */
+#define CAN_MMR_PRIOR(value) ((CAN_MMR_PRIOR_Msk & ((value) << CAN_MMR_PRIOR_Pos)))
+#define CAN_MMR_MOT_Pos 24
+#define CAN_MMR_MOT_Msk (0x7u << CAN_MMR_MOT_Pos) /**< \brief (CAN_MMR) Mailbox Object Type */
+#define   CAN_MMR_MOT_MB_DISABLED (0x0u << 24) /**< \brief (CAN_MMR) Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. */
+#define   CAN_MMR_MOT_MB_RX (0x1u << 24) /**< \brief (CAN_MMR) Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. */
+#define   CAN_MMR_MOT_MB_RX_OVERWRITE (0x2u << 24) /**< \brief (CAN_MMR) Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. */
+#define   CAN_MMR_MOT_MB_TX (0x3u << 24) /**< \brief (CAN_MMR) Transmit mailbox. Mailbox is configured for transmission. */
+#define   CAN_MMR_MOT_MB_CONSUMER (0x4u << 24) /**< \brief (CAN_MMR) Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. */
+#define   CAN_MMR_MOT_MB_PRODUCER (0x5u << 24) /**< \brief (CAN_MMR) Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. */
+/* -------- CAN_MAM : (CAN Offset: N/A) Mailbox Acceptance Mask Register -------- */
+#define CAN_MAM_MIDvB_Pos 0
+#define CAN_MAM_MIDvB_Msk (0x3ffffu << CAN_MAM_MIDvB_Pos) /**< \brief (CAN_MAM) Complementary bits for identifier in extended frame mode */
+#define CAN_MAM_MIDvB(value) ((CAN_MAM_MIDvB_Msk & ((value) << CAN_MAM_MIDvB_Pos)))
+#define CAN_MAM_MIDvA_Pos 18
+#define CAN_MAM_MIDvA_Msk (0x7ffu << CAN_MAM_MIDvA_Pos) /**< \brief (CAN_MAM) Identifier for standard frame mode */
+#define CAN_MAM_MIDvA(value) ((CAN_MAM_MIDvA_Msk & ((value) << CAN_MAM_MIDvA_Pos)))
+#define CAN_MAM_MIDE (0x1u << 29) /**< \brief (CAN_MAM) Identifier Version */
+/* -------- CAN_MID : (CAN Offset: N/A) Mailbox ID Register -------- */
+#define CAN_MID_MIDvB_Pos 0
+#define CAN_MID_MIDvB_Msk (0x3ffffu << CAN_MID_MIDvB_Pos) /**< \brief (CAN_MID) Complementary bits for identifier in extended frame mode */
+#define CAN_MID_MIDvB(value) ((CAN_MID_MIDvB_Msk & ((value) << CAN_MID_MIDvB_Pos)))
+#define CAN_MID_MIDvA_Pos 18
+#define CAN_MID_MIDvA_Msk (0x7ffu << CAN_MID_MIDvA_Pos) /**< \brief (CAN_MID) Identifier for standard frame mode */
+#define CAN_MID_MIDvA(value) ((CAN_MID_MIDvA_Msk & ((value) << CAN_MID_MIDvA_Pos)))
+#define CAN_MID_MIDE (0x1u << 29) /**< \brief (CAN_MID) Identifier Version */
+/* -------- CAN_MFID : (CAN Offset: N/A) Mailbox Family ID Register -------- */
+#define CAN_MFID_MFID_Pos 0
+#define CAN_MFID_MFID_Msk (0x1fffffffu << CAN_MFID_MFID_Pos) /**< \brief (CAN_MFID) Family ID */
+/* -------- CAN_MSR : (CAN Offset: N/A) Mailbox Status Register -------- */
+#define CAN_MSR_MTIMESTAMP_Pos 0
+#define CAN_MSR_MTIMESTAMP_Msk (0xffffu << CAN_MSR_MTIMESTAMP_Pos) /**< \brief (CAN_MSR) Timer value */
+#define CAN_MSR_MDLC_Pos 16
+#define CAN_MSR_MDLC_Msk (0xfu << CAN_MSR_MDLC_Pos) /**< \brief (CAN_MSR) Mailbox Data Length Code */
+#define CAN_MSR_MRTR (0x1u << 20) /**< \brief (CAN_MSR) Mailbox Remote Transmission Request */
+#define CAN_MSR_MABT (0x1u << 22) /**< \brief (CAN_MSR) Mailbox Message Abort */
+#define CAN_MSR_MRDY (0x1u << 23) /**< \brief (CAN_MSR) Mailbox Ready */
+#define CAN_MSR_MMI (0x1u << 24) /**< \brief (CAN_MSR) Mailbox Message Ignored */
+/* -------- CAN_MDL : (CAN Offset: N/A) Mailbox Data Low Register -------- */
+#define CAN_MDL_MDL_Pos 0
+#define CAN_MDL_MDL_Msk (0xffffffffu << CAN_MDL_MDL_Pos) /**< \brief (CAN_MDL) Message Data Low Value */
+#define CAN_MDL_MDL(value) ((CAN_MDL_MDL_Msk & ((value) << CAN_MDL_MDL_Pos)))
+/* -------- CAN_MDH : (CAN Offset: N/A) Mailbox Data High Register -------- */
+#define CAN_MDH_MDH_Pos 0
+#define CAN_MDH_MDH_Msk (0xffffffffu << CAN_MDH_MDH_Pos) /**< \brief (CAN_MDH) Message Data High Value */
+#define CAN_MDH_MDH(value) ((CAN_MDH_MDH_Msk & ((value) << CAN_MDH_MDH_Pos)))
+/* -------- CAN_MCR : (CAN Offset: N/A) Mailbox Control Register -------- */
+#define CAN_MCR_MDLC_Pos 16
+#define CAN_MCR_MDLC_Msk (0xfu << CAN_MCR_MDLC_Pos) /**< \brief (CAN_MCR) Mailbox Data Length Code */
+#define CAN_MCR_MDLC(value) ((CAN_MCR_MDLC_Msk & ((value) << CAN_MCR_MDLC_Pos)))
+#define CAN_MCR_MRTR (0x1u << 20) /**< \brief (CAN_MCR) Mailbox Remote Transmission Request */
+#define CAN_MCR_MACR (0x1u << 22) /**< \brief (CAN_MCR) Abort Request for Mailbox x */
+#define CAN_MCR_MTCR (0x1u << 23) /**< \brief (CAN_MCR) Mailbox Transfer Command */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_CAN_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_chipid.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_chipid.h
new file mode 100644
index 0000000..f4bf270
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_chipid.h
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CHIPID_COMPONENT_
+#define _SAM3XA_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_CHIPID Chip Identifier */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Chipid hardware registers */
+typedef struct {
+  RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+  RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define   CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define   CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define   CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define   CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define   CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define   CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define   CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define   CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define   CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define   CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define   CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define   CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
+#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_CHIPID_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_dacc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_dacc.h
new file mode 100644
index 0000000..ebc61a2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_dacc.h
@@ -0,0 +1,210 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_DACC_COMPONENT_
+#define _SAM3XA_DACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_DACC Digital-to-Analog Converter Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Dacc hardware registers */
+typedef struct {
+  WoReg DACC_CR;       /**< \brief (Dacc Offset: 0x00) Control Register */
+  RwReg DACC_MR;       /**< \brief (Dacc Offset: 0x04) Mode Register */
+  RoReg Reserved1[2];
+  WoReg DACC_CHER;     /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
+  WoReg DACC_CHDR;     /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
+  RoReg DACC_CHSR;     /**< \brief (Dacc Offset: 0x18) Channel Status Register */
+  RoReg Reserved2[1];
+  WoReg DACC_CDR;      /**< \brief (Dacc Offset: 0x20) Conversion Data Register */
+  WoReg DACC_IER;      /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
+  WoReg DACC_IDR;      /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
+  RoReg DACC_IMR;      /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
+  RoReg DACC_ISR;      /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved3[24];
+  RwReg DACC_ACR;      /**< \brief (Dacc Offset: 0x94) Analog Current Register */
+  RoReg Reserved4[19];
+  RwReg DACC_WPMR;     /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */
+  RoReg DACC_WPSR;     /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */
+  RoReg Reserved5[7];
+  RwReg DACC_TPR;      /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
+  RwReg DACC_TCR;      /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
+  RoReg Reserved6[2];
+  RwReg DACC_TNPR;     /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg DACC_TNCR;     /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg DACC_PTCR;     /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
+  RoReg DACC_PTSR;     /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
+} Dacc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
+#define   DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */
+#define   DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */
+#define DACC_MR_TRGSEL_Pos 1
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define   DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */
+#define   DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */
+#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */
+#define DACC_MR_REFRESH_Pos 8
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
+#define DACC_MR_USER_SEL_Pos 16
+#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */
+#define   DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */
+#define   DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */
+#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */
+#define   DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */
+#define   DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */
+#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */
+#define   DACC_MR_MAXS_NORMAL (0x0u << 21) /**< \brief (DACC_MR) Normal Mode */
+#define   DACC_MR_MAXS_MAXIMUM (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode enabled */
+#define DACC_MR_STARTUP_Pos 24
+#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
+#define   DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */
+#define   DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */
+#define   DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */
+#define   DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */
+#define   DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */
+#define   DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */
+#define   DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */
+#define   DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */
+#define   DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */
+#define   DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */
+#define   DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */
+#define   DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */
+#define   DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */
+#define   DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */
+#define   DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */
+#define   DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */
+#define   DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */
+#define   DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */
+#define   DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */
+#define   DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */
+#define   DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */
+#define   DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */
+#define   DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */
+#define   DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */
+#define   DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */
+#define   DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */
+#define   DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */
+#define   DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */
+#define   DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */
+#define   DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */
+#define   DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */
+#define   DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
+/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */
+#define DACC_CDR_DATA_Pos 0
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */
+#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */
+#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */
+#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */
+#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */
+#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */
+#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */
+#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */
+#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */
+#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */
+#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */
+#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */
+#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
+#define DACC_ACR_IBCTLCH0_Pos 0
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
+#define DACC_ACR_IBCTLCH1_Pos 2
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
+#define DACC_ACR_IBCTLDACCORE_Pos 8
+#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */
+#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
+#define DACC_WPMR_WPKEY_Pos 8
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
+#define DACC_WPSR_WPROTADDR_Pos 8
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
+#define DACC_TPR_TXPTR_Pos 0
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
+#define DACC_TCR_TXCTR_Pos 0
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define DACC_TNPR_TXNPTR_Pos 0
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define DACC_TNCR_TXNCTR_Pos 0
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_DACC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_dmac.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_dmac.h
new file mode 100644
index 0000000..c57255c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_dmac.h
@@ -0,0 +1,367 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_DMAC_COMPONENT_
+#define _SAM3XA_DMAC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_DMAC DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief DmacCh_num hardware registers */
+typedef struct {
+  RwReg       DMAC_SADDR;     /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */
+  RwReg       DMAC_DADDR;     /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */
+  RwReg       DMAC_DSCR;      /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */
+  RwReg       DMAC_CTRLA;     /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */
+  RwReg       DMAC_CTRLB;     /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */
+  RwReg       DMAC_CFG;       /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */
+  RoReg       Reserved1[4];
+} DmacCh_num;
+/** \brief Dmac hardware registers */
+#define DMACCH_NUM_NUMBER 6
+typedef struct {
+  RwReg       DMAC_GCFG;      /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */
+  RwReg       DMAC_EN;        /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */
+  RwReg       DMAC_SREQ;      /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */
+  RwReg       DMAC_CREQ;      /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */
+  RwReg       DMAC_LAST;      /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */
+  RoReg       Reserved1[1];
+  WoReg       DMAC_EBCIER;    /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+  WoReg       DMAC_EBCIDR;    /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+  RoReg       DMAC_EBCIMR;    /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+  RoReg       DMAC_EBCISR;    /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+  WoReg       DMAC_CHER;      /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */
+  WoReg       DMAC_CHDR;      /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */
+  RoReg       DMAC_CHSR;      /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */
+  RoReg       Reserved2[2];
+  DmacCh_num  DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 5 */
+  RoReg       Reserved3[46];
+  RwReg       DMAC_WPMR;      /**< \brief (Dmac Offset: 0x1E4) DMAC Write Protect Mode Register */
+  RoReg       DMAC_WPSR;      /**< \brief (Dmac Offset: 0x1E8) DMAC Write Protect Status Register */
+} Dmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */
+#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) Arbiter Configuration */
+#define   DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) /**< \brief (DMAC_GCFG) Fixed priority arbiter. */
+#define   DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) /**< \brief (DMAC_GCFG) Modified round robin arbiter. */
+/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */
+#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN)  */
+/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */
+#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ4 (0x1u << 8) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ4 (0x1u << 9) /**< \brief (DMAC_SREQ) Destination Request */
+#define DMAC_SREQ_SSREQ5 (0x1u << 10) /**< \brief (DMAC_SREQ) Source Request */
+#define DMAC_SREQ_DSREQ5 (0x1u << 11) /**< \brief (DMAC_SREQ) Destination Request */
+/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */
+#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ4 (0x1u << 8) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ4 (0x1u << 9) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+#define DMAC_CREQ_SCREQ5 (0x1u << 10) /**< \brief (DMAC_CREQ) Source Chunk Request */
+#define DMAC_CREQ_DCREQ5 (0x1u << 11) /**< \brief (DMAC_CREQ) Destination Chunk Request */
+/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */
+#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST4 (0x1u << 8) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST4 (0x1u << 9) /**< \brief (DMAC_LAST) Destination Last */
+#define DMAC_LAST_SLAST5 (0x1u << 10) /**< \brief (DMAC_LAST) Source Last */
+#define DMAC_LAST_DLAST5 (0x1u << 11) /**< \brief (DMAC_LAST) Destination Last */
+/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */
+#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+#define DMAC_EBCIER_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIER) Access Error [5:0] */
+/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */
+#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+#define DMAC_EBCIDR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */
+/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */
+#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+#define DMAC_EBCIMR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */
+/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */
+#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */
+#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+#define DMAC_EBCISR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCISR) Access Error [5:0] */
+/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */
+#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA4 (0x1u << 4) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_ENA5 (0x1u << 5) /**< \brief (DMAC_CHER) Enable [5:0] */
+#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHER) Suspend [5:0] */
+#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP4 (0x1u << 28) /**< \brief (DMAC_CHER) Keep on [5:0] */
+#define DMAC_CHER_KEEP5 (0x1u << 29) /**< \brief (DMAC_CHER) Keep on [5:0] */
+/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */
+#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS4 (0x1u << 4) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_DIS5 (0x1u << 5) /**< \brief (DMAC_CHDR) Disable [5:0] */
+#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES4 (0x1u << 12) /**< \brief (DMAC_CHDR) Resume [5:0] */
+#define DMAC_CHDR_RES5 (0x1u << 13) /**< \brief (DMAC_CHDR) Resume [5:0] */
+/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */
+#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA4 (0x1u << 4) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_ENA5 (0x1u << 5) /**< \brief (DMAC_CHSR) Enable [5:0] */
+#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHSR) Suspend [5:0] */
+#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT4 (0x1u << 20) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_EMPT5 (0x1u << 21) /**< \brief (DMAC_CHSR) Empty [5:0] */
+#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL4 (0x1u << 28) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+#define DMAC_CHSR_STAL5 (0x1u << 29) /**< \brief (DMAC_CHSR) Stalled [5:0] */
+/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */
+#define DMAC_SADDR_SADDR_Pos 0
+#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) /**< \brief (DMAC_SADDR) Channel x Source Address */
+#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos)))
+/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */
+#define DMAC_DADDR_DADDR_Pos 0
+#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) /**< \brief (DMAC_DADDR) Channel x Destination Address */
+#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos)))
+/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */
+#define DMAC_DSCR_DSCR_Pos 2
+#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) /**< \brief (DMAC_DSCR) Buffer Transfer Descriptor Address */
+#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos)))
+/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */
+#define DMAC_CTRLA_BTSIZE_Pos 0
+#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) Buffer Transfer Size */
+#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))
+#define DMAC_CTRLA_SCSIZE_Pos 16
+#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA) Source Chunk Transfer Size. */
+#define   DMAC_CTRLA_SCSIZE_CHK_1 (0x0u << 16) /**< \brief (DMAC_CTRLA) 1 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_4 (0x1u << 16) /**< \brief (DMAC_CTRLA) 4 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_8 (0x2u << 16) /**< \brief (DMAC_CTRLA) 8 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_16 (0x3u << 16) /**< \brief (DMAC_CTRLA) 16 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_32 (0x4u << 16) /**< \brief (DMAC_CTRLA) 32 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_64 (0x5u << 16) /**< \brief (DMAC_CTRLA) 64 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_128 (0x6u << 16) /**< \brief (DMAC_CTRLA) 128 data transferred */
+#define   DMAC_CTRLA_SCSIZE_CHK_256 (0x7u << 16) /**< \brief (DMAC_CTRLA) 256 data transferred */
+#define DMAC_CTRLA_DCSIZE_Pos 20
+#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA) Destination Chunk Transfer Size */
+#define   DMAC_CTRLA_DCSIZE_CHK_1 (0x0u << 20) /**< \brief (DMAC_CTRLA) 1 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_4 (0x1u << 20) /**< \brief (DMAC_CTRLA) 4 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_8 (0x2u << 20) /**< \brief (DMAC_CTRLA) 8 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_16 (0x3u << 20) /**< \brief (DMAC_CTRLA) 16 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_32 (0x4u << 20) /**< \brief (DMAC_CTRLA) 32 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_64 (0x5u << 20) /**< \brief (DMAC_CTRLA) 64 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_128 (0x6u << 20) /**< \brief (DMAC_CTRLA) 128 data transferred */
+#define   DMAC_CTRLA_DCSIZE_CHK_256 (0x7u << 20) /**< \brief (DMAC_CTRLA) 256 data transferred */
+#define DMAC_CTRLA_SRC_WIDTH_Pos 24
+#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Source */
+#define   DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
+#define   DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
+#define   DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
+#define DMAC_CTRLA_DST_WIDTH_Pos 28
+#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Destination */
+#define   DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */
+#define   DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */
+#define   DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */
+#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA)  */
+/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */
+#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) Source Address Descriptor */
+#define   DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) /**< \brief (DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory. */
+#define   DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source. */
+#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) Destination Address Descriptor */
+#define   DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) /**< \brief (DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory. */
+#define   DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination. */
+#define DMAC_CTRLB_FC_Pos 21
+#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) Flow Control */
+#define   DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller */
+#define   DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller */
+#define   DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller */
+#define   DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller */
+#define DMAC_CTRLB_SRC_INCR_Pos 24
+#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source */
+#define   DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) /**< \brief (DMAC_CTRLB) The source address is incremented */
+#define   DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) /**< \brief (DMAC_CTRLB) The source address is decremented */
+#define   DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) /**< \brief (DMAC_CTRLB) The source address remains unchanged */
+#define DMAC_CTRLB_DST_INCR_Pos 28
+#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination */
+#define   DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) /**< \brief (DMAC_CTRLB) The destination address is incremented */
+#define   DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) /**< \brief (DMAC_CTRLB) The destination address is decremented */
+#define   DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) /**< \brief (DMAC_CTRLB) The destination address remains unchanged */
+#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB)  */
+/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */
+#define DMAC_CFG_SRC_PER_Pos 0
+#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) Source with Peripheral identifier */
+#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))
+#define DMAC_CFG_DST_PER_Pos 4
+#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) Destination with Peripheral identifier */
+#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))
+#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Source */
+#define   DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
+#define   DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Destination */
+#define   DMAC_CFG_DST_H2SEL_SW (0x0u << 13) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */
+#define   DMAC_CFG_DST_H2SEL_HW (0x1u << 13) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */
+#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) Stop On Done */
+#define   DMAC_CFG_SOD_DISABLE (0x0u << 16) /**< \brief (DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. */
+#define   DMAC_CFG_SOD_ENABLE (0x1u << 16) /**< \brief (DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. */
+#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock */
+#define   DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is disabled */
+#define   DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is enabled */
+#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) Bus Lock */
+#define   DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) /**< \brief (DMAC_CFG) AHB Bus Locking capability is disabled. */
+#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) Master Interface Arbiter Lock */
+#define   DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer. */
+#define   DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer. */
+#define DMAC_CFG_AHB_PROT_Pos 24
+#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) AHB Protection */
+#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))
+#define DMAC_CFG_FIFOCFG_Pos 28
+#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) FIFO Configuration */
+#define   DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) /**< \brief (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface. */
+#define   DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) /**< \brief (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced. */
+#define   DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) /**< \brief (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced. */
+/* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */
+#define DMAC_WPMR_WPEN (0x1u << 0) /**< \brief (DMAC_WPMR) Write Protect Enable */
+#define DMAC_WPMR_WPKEY_Pos 8
+#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) /**< \brief (DMAC_WPMR) Write Protect KEY */
+#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos)))
+/* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */
+#define DMAC_WPSR_WPVS (0x1u << 0) /**< \brief (DMAC_WPSR) Write Protect Violation Status */
+#define DMAC_WPSR_WPVSRC_Pos 8
+#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) /**< \brief (DMAC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_DMAC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_efc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_efc.h
new file mode 100644
index 0000000..3c2b96a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_efc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EFC_COMPONENT_
+#define _SAM3XA_EFC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_EFC Embedded Flash Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Efc hardware registers */
+typedef struct {
+  RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+  WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+  RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+  RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_EFC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_emac.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_emac.h
new file mode 100644
index 0000000..b43a504
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_emac.h
@@ -0,0 +1,335 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EMAC_COMPONENT_
+#define _SAM3XA_EMAC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_EMAC Ethernet MAC 10/100 */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief EmacSa hardware registers */
+typedef struct {
+  RwReg   EMAC_SAxB;    /**< \brief (EmacSa Offset: 0x0) Specific Address 1 Bottom Register */
+  RwReg   EMAC_SAxT;    /**< \brief (EmacSa Offset: 0x4) Specific Address 1 Top Register */
+} EmacSa;
+/** \brief Emac hardware registers */
+#define EMACSA_NUMBER 4
+typedef struct {
+  RwReg   EMAC_NCR;     /**< \brief (Emac Offset: 0x00) Network Control Register */
+  RwReg   EMAC_NCFGR;   /**< \brief (Emac Offset: 0x04) Network Configuration Register */
+  RoReg   EMAC_NSR;     /**< \brief (Emac Offset: 0x08) Network Status Register */
+  RoReg   Reserved1[2];
+  RwReg   EMAC_TSR;     /**< \brief (Emac Offset: 0x14) Transmit Status Register */
+  RwReg   EMAC_RBQP;    /**< \brief (Emac Offset: 0x18) Receive Buffer Queue Pointer Register */
+  RwReg   EMAC_TBQP;    /**< \brief (Emac Offset: 0x1C) Transmit Buffer Queue Pointer Register */
+  RwReg   EMAC_RSR;     /**< \brief (Emac Offset: 0x20) Receive Status Register */
+  RwReg   EMAC_ISR;     /**< \brief (Emac Offset: 0x24) Interrupt Status Register */
+  WoReg   EMAC_IER;     /**< \brief (Emac Offset: 0x28) Interrupt Enable Register */
+  WoReg   EMAC_IDR;     /**< \brief (Emac Offset: 0x2C) Interrupt Disable Register */
+  RoReg   EMAC_IMR;     /**< \brief (Emac Offset: 0x30) Interrupt Mask Register */
+  RwReg   EMAC_MAN;     /**< \brief (Emac Offset: 0x34) Phy Maintenance Register */
+  RwReg   EMAC_PTR;     /**< \brief (Emac Offset: 0x38) Pause Time Register */
+  RwReg   EMAC_PFR;     /**< \brief (Emac Offset: 0x3C) Pause Frames Received Register */
+  RwReg   EMAC_FTO;     /**< \brief (Emac Offset: 0x40) Frames Transmitted Ok Register */
+  RwReg   EMAC_SCF;     /**< \brief (Emac Offset: 0x44) Single Collision Frames Register */
+  RwReg   EMAC_MCF;     /**< \brief (Emac Offset: 0x48) Multiple Collision Frames Register */
+  RwReg   EMAC_FRO;     /**< \brief (Emac Offset: 0x4C) Frames Received Ok Register */
+  RwReg   EMAC_FCSE;    /**< \brief (Emac Offset: 0x50) Frame Check Sequence Errors Register */
+  RwReg   EMAC_ALE;     /**< \brief (Emac Offset: 0x54) Alignment Errors Register */
+  RwReg   EMAC_DTF;     /**< \brief (Emac Offset: 0x58) Deferred Transmission Frames Register */
+  RwReg   EMAC_LCOL;    /**< \brief (Emac Offset: 0x5C) Late Collisions Register */
+  RwReg   EMAC_ECOL;    /**< \brief (Emac Offset: 0x60) Excessive Collisions Register */
+  RwReg   EMAC_TUND;    /**< \brief (Emac Offset: 0x64) Transmit Underrun Errors Register */
+  RwReg   EMAC_CSE;     /**< \brief (Emac Offset: 0x68) Carrier Sense Errors Register */
+  RwReg   EMAC_RRE;     /**< \brief (Emac Offset: 0x6C) Receive Resource Errors Register */
+  RwReg   EMAC_ROV;     /**< \brief (Emac Offset: 0x70) Receive Overrun Errors Register */
+  RwReg   EMAC_RSE;     /**< \brief (Emac Offset: 0x74) Receive Symbol Errors Register */
+  RwReg   EMAC_ELE;     /**< \brief (Emac Offset: 0x78) Excessive Length Errors Register */
+  RwReg   EMAC_RJA;     /**< \brief (Emac Offset: 0x7C) Receive Jabbers Register */
+  RwReg   EMAC_USF;     /**< \brief (Emac Offset: 0x80) Undersize Frames Register */
+  RwReg   EMAC_STE;     /**< \brief (Emac Offset: 0x84) SQE Test Errors Register */
+  RwReg   EMAC_RLE;     /**< \brief (Emac Offset: 0x88) Received Length Field Mismatch Register */
+  RoReg   Reserved2[1];
+  RwReg   EMAC_HRB;     /**< \brief (Emac Offset: 0x90) Hash Register Bottom [31:0] Register */
+  RwReg   EMAC_HRT;     /**< \brief (Emac Offset: 0x94) Hash Register Top [63:32] Register */
+  EmacSa  EMAC_SA[EMACSA_NUMBER]; /**< \brief (Emac Offset: 0x98) sa = 1 .. 4 */
+  RwReg   EMAC_TID;     /**< \brief (Emac Offset: 0xB8) Type ID Checking Register */
+  RoReg   Reserved3[1];
+  RwReg   EMAC_USRIO;   /**< \brief (Emac Offset: 0xC0) User Input/Output Register */
+} Emac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- EMAC_NCR : (EMAC Offset: 0x00) Network Control Register -------- */
+#define EMAC_NCR_LB (0x1u << 0) /**< \brief (EMAC_NCR) LoopBack */
+#define EMAC_NCR_LLB (0x1u << 1) /**< \brief (EMAC_NCR) Loopback local */
+#define EMAC_NCR_RE (0x1u << 2) /**< \brief (EMAC_NCR) Receive enable */
+#define EMAC_NCR_TE (0x1u << 3) /**< \brief (EMAC_NCR) Transmit enable */
+#define EMAC_NCR_MPE (0x1u << 4) /**< \brief (EMAC_NCR) Management port enable */
+#define EMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (EMAC_NCR) Clear statistics registers */
+#define EMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (EMAC_NCR) Increment statistics registers */
+#define EMAC_NCR_WESTAT (0x1u << 7) /**< \brief (EMAC_NCR) Write enable for statistics registers */
+#define EMAC_NCR_BP (0x1u << 8) /**< \brief (EMAC_NCR) Back pressure */
+#define EMAC_NCR_TSTART (0x1u << 9) /**< \brief (EMAC_NCR) Start transmission */
+#define EMAC_NCR_THALT (0x1u << 10) /**< \brief (EMAC_NCR) Transmit halt */
+/* -------- EMAC_NCFGR : (EMAC Offset: 0x04) Network Configuration Register -------- */
+#define EMAC_NCFGR_SPD (0x1u << 0) /**< \brief (EMAC_NCFGR) Speed */
+#define EMAC_NCFGR_FD (0x1u << 1) /**< \brief (EMAC_NCFGR) Full Duplex */
+#define EMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (EMAC_NCFGR) Jumbo Frames */
+#define EMAC_NCFGR_CAF (0x1u << 4) /**< \brief (EMAC_NCFGR) Copy All Frames */
+#define EMAC_NCFGR_NBC (0x1u << 5) /**< \brief (EMAC_NCFGR) No Broadcast */
+#define EMAC_NCFGR_MTI (0x1u << 6) /**< \brief (EMAC_NCFGR) Multicast Hash Enable */
+#define EMAC_NCFGR_UNI (0x1u << 7) /**< \brief (EMAC_NCFGR) Unicast Hash Enable */
+#define EMAC_NCFGR_BIG (0x1u << 8) /**< \brief (EMAC_NCFGR) Receive 1536 bytes frames */
+#define EMAC_NCFGR_CLK_Pos 10
+#define EMAC_NCFGR_CLK_Msk (0x3u << EMAC_NCFGR_CLK_Pos) /**< \brief (EMAC_NCFGR) MDC clock divider */
+#define   EMAC_NCFGR_CLK_MCK_8 (0x0u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz). */
+#define   EMAC_NCFGR_CLK_MCK_16 (0x1u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz). */
+#define   EMAC_NCFGR_CLK_MCK_32 (0x2u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz). */
+#define   EMAC_NCFGR_CLK_MCK_64 (0x3u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz). */
+#define EMAC_NCFGR_RTY (0x1u << 12) /**< \brief (EMAC_NCFGR) Retry test */
+#define EMAC_NCFGR_PAE (0x1u << 13) /**< \brief (EMAC_NCFGR) Pause Enable */
+#define EMAC_NCFGR_RBOF_Pos 14
+#define EMAC_NCFGR_RBOF_Msk (0x3u << EMAC_NCFGR_RBOF_Pos) /**< \brief (EMAC_NCFGR) Receive Buffer Offset */
+#define   EMAC_NCFGR_RBOF_OFFSET_0 (0x0u << 14) /**< \brief (EMAC_NCFGR) No offset from start of receive buffer. */
+#define   EMAC_NCFGR_RBOF_OFFSET_1 (0x1u << 14) /**< \brief (EMAC_NCFGR) One-byte offset from start of receive buffer. */
+#define   EMAC_NCFGR_RBOF_OFFSET_2 (0x2u << 14) /**< \brief (EMAC_NCFGR) Two-byte offset from start of receive buffer. */
+#define   EMAC_NCFGR_RBOF_OFFSET_3 (0x3u << 14) /**< \brief (EMAC_NCFGR) Three-byte offset from start of receive buffer. */
+#define EMAC_NCFGR_RLCE (0x1u << 16) /**< \brief (EMAC_NCFGR) Receive Length field Checking Enable */
+#define EMAC_NCFGR_DRFCS (0x1u << 17) /**< \brief (EMAC_NCFGR) Discard Receive FCS */
+#define EMAC_NCFGR_EFRHD (0x1u << 18) /**< \brief (EMAC_NCFGR)  */
+#define EMAC_NCFGR_IRXFCS (0x1u << 19) /**< \brief (EMAC_NCFGR) Ignore RX FCS */
+/* -------- EMAC_NSR : (EMAC Offset: 0x08) Network Status Register -------- */
+#define EMAC_NSR_MDIO (0x1u << 1) /**< \brief (EMAC_NSR)  */
+#define EMAC_NSR_IDLE (0x1u << 2) /**< \brief (EMAC_NSR)  */
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
+#define EMAC_TSR_UBR (0x1u << 0) /**< \brief (EMAC_TSR) Used Bit Read */
+#define EMAC_TSR_COL (0x1u << 1) /**< \brief (EMAC_TSR) Collision Occurred */
+#define EMAC_TSR_RLES (0x1u << 2) /**< \brief (EMAC_TSR) Retry Limit exceeded */
+#define EMAC_TSR_TGO (0x1u << 3) /**< \brief (EMAC_TSR) Transmit Go */
+#define EMAC_TSR_BEX (0x1u << 4) /**< \brief (EMAC_TSR) Buffers exhausted mid frame */
+#define EMAC_TSR_COMP (0x1u << 5) /**< \brief (EMAC_TSR) Transmit Complete */
+#define EMAC_TSR_UND (0x1u << 6) /**< \brief (EMAC_TSR) Transmit Underrun */
+/* -------- EMAC_RBQP : (EMAC Offset: 0x18) Receive Buffer Queue Pointer Register -------- */
+#define EMAC_RBQP_ADDR_Pos 2
+#define EMAC_RBQP_ADDR_Msk (0x3fffffffu << EMAC_RBQP_ADDR_Pos) /**< \brief (EMAC_RBQP) Receive buffer queue pointer address */
+#define EMAC_RBQP_ADDR(value) ((EMAC_RBQP_ADDR_Msk & ((value) << EMAC_RBQP_ADDR_Pos)))
+/* -------- EMAC_TBQP : (EMAC Offset: 0x1C) Transmit Buffer Queue Pointer Register -------- */
+#define EMAC_TBQP_ADDR_Pos 2
+#define EMAC_TBQP_ADDR_Msk (0x3fffffffu << EMAC_TBQP_ADDR_Pos) /**< \brief (EMAC_TBQP) Transmit buffer queue pointer address */
+#define EMAC_TBQP_ADDR(value) ((EMAC_TBQP_ADDR_Msk & ((value) << EMAC_TBQP_ADDR_Pos)))
+/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
+#define EMAC_RSR_BNA (0x1u << 0) /**< \brief (EMAC_RSR) Buffer Not Available */
+#define EMAC_RSR_REC (0x1u << 1) /**< \brief (EMAC_RSR) Frame Received */
+#define EMAC_RSR_OVR (0x1u << 2) /**< \brief (EMAC_RSR) Receive Overrun */
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+#define EMAC_ISR_MFD (0x1u << 0) /**< \brief (EMAC_ISR) Management Frame Done */
+#define EMAC_ISR_RCOMP (0x1u << 1) /**< \brief (EMAC_ISR) Receive Complete */
+#define EMAC_ISR_RXUBR (0x1u << 2) /**< \brief (EMAC_ISR) Receive Used Bit Read */
+#define EMAC_ISR_TXUBR (0x1u << 3) /**< \brief (EMAC_ISR) Transmit Used Bit Read */
+#define EMAC_ISR_TUND (0x1u << 4) /**< \brief (EMAC_ISR) Ethernet Transmit Buffer Underrun */
+#define EMAC_ISR_RLEX (0x1u << 5) /**< \brief (EMAC_ISR) Retry Limit Exceeded */
+#define EMAC_ISR_TXERR (0x1u << 6) /**< \brief (EMAC_ISR) Transmit Error */
+#define EMAC_ISR_TCOMP (0x1u << 7) /**< \brief (EMAC_ISR) Transmit Complete */
+#define EMAC_ISR_ROVR (0x1u << 10) /**< \brief (EMAC_ISR) Receive Overrun */
+#define EMAC_ISR_HRESP (0x1u << 11) /**< \brief (EMAC_ISR) Hresp not OK */
+#define EMAC_ISR_PFRE (0x1u << 12) /**< \brief (EMAC_ISR) Pause Frame Received */
+#define EMAC_ISR_PTZ (0x1u << 13) /**< \brief (EMAC_ISR) Pause Time Zero */
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
+#define EMAC_IER_MFD (0x1u << 0) /**< \brief (EMAC_IER) Management Frame sent */
+#define EMAC_IER_RCOMP (0x1u << 1) /**< \brief (EMAC_IER) Receive Complete */
+#define EMAC_IER_RXUBR (0x1u << 2) /**< \brief (EMAC_IER) Receive Used Bit Read */
+#define EMAC_IER_TXUBR (0x1u << 3) /**< \brief (EMAC_IER) Transmit Used Bit Read */
+#define EMAC_IER_TUND (0x1u << 4) /**< \brief (EMAC_IER) Ethernet Transmit Buffer Underrun */
+#define EMAC_IER_RLE (0x1u << 5) /**< \brief (EMAC_IER) Retry Limit Exceeded */
+#define EMAC_IER_TXERR (0x1u << 6) /**< \brief (EMAC_IER)  */
+#define EMAC_IER_TCOMP (0x1u << 7) /**< \brief (EMAC_IER) Transmit Complete */
+#define EMAC_IER_ROVR (0x1u << 10) /**< \brief (EMAC_IER) Receive Overrun */
+#define EMAC_IER_HRESP (0x1u << 11) /**< \brief (EMAC_IER) Hresp not OK */
+#define EMAC_IER_PFR (0x1u << 12) /**< \brief (EMAC_IER) Pause Frame Received */
+#define EMAC_IER_PTZ (0x1u << 13) /**< \brief (EMAC_IER) Pause Time Zero */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2C) Interrupt Disable Register -------- */
+#define EMAC_IDR_MFD (0x1u << 0) /**< \brief (EMAC_IDR) Management Frame sent */
+#define EMAC_IDR_RCOMP (0x1u << 1) /**< \brief (EMAC_IDR) Receive Complete */
+#define EMAC_IDR_RXUBR (0x1u << 2) /**< \brief (EMAC_IDR) Receive Used Bit Read */
+#define EMAC_IDR_TXUBR (0x1u << 3) /**< \brief (EMAC_IDR) Transmit Used Bit Read */
+#define EMAC_IDR_TUND (0x1u << 4) /**< \brief (EMAC_IDR) Ethernet Transmit Buffer Underrun */
+#define EMAC_IDR_RLE (0x1u << 5) /**< \brief (EMAC_IDR) Retry Limit Exceeded */
+#define EMAC_IDR_TXERR (0x1u << 6) /**< \brief (EMAC_IDR)  */
+#define EMAC_IDR_TCOMP (0x1u << 7) /**< \brief (EMAC_IDR) Transmit Complete */
+#define EMAC_IDR_ROVR (0x1u << 10) /**< \brief (EMAC_IDR) Receive Overrun */
+#define EMAC_IDR_HRESP (0x1u << 11) /**< \brief (EMAC_IDR) Hresp not OK */
+#define EMAC_IDR_PFR (0x1u << 12) /**< \brief (EMAC_IDR) Pause Frame Received */
+#define EMAC_IDR_PTZ (0x1u << 13) /**< \brief (EMAC_IDR) Pause Time Zero */
+/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
+#define EMAC_IMR_MFD (0x1u << 0) /**< \brief (EMAC_IMR) Management Frame sent */
+#define EMAC_IMR_RCOMP (0x1u << 1) /**< \brief (EMAC_IMR) Receive Complete */
+#define EMAC_IMR_RXUBR (0x1u << 2) /**< \brief (EMAC_IMR) Receive Used Bit Read */
+#define EMAC_IMR_TXUBR (0x1u << 3) /**< \brief (EMAC_IMR) Transmit Used Bit Read */
+#define EMAC_IMR_TUND (0x1u << 4) /**< \brief (EMAC_IMR) Ethernet Transmit Buffer Underrun */
+#define EMAC_IMR_RLE (0x1u << 5) /**< \brief (EMAC_IMR) Retry Limit Exceeded */
+#define EMAC_IMR_TXERR (0x1u << 6) /**< \brief (EMAC_IMR)  */
+#define EMAC_IMR_TCOMP (0x1u << 7) /**< \brief (EMAC_IMR) Transmit Complete */
+#define EMAC_IMR_ROVR (0x1u << 10) /**< \brief (EMAC_IMR) Receive Overrun */
+#define EMAC_IMR_HRESP (0x1u << 11) /**< \brief (EMAC_IMR) Hresp not OK */
+#define EMAC_IMR_PFR (0x1u << 12) /**< \brief (EMAC_IMR) Pause Frame Received */
+#define EMAC_IMR_PTZ (0x1u << 13) /**< \brief (EMAC_IMR) Pause Time Zero */
+/* -------- EMAC_MAN : (EMAC Offset: 0x34) Phy Maintenance Register -------- */
+#define EMAC_MAN_DATA_Pos 0
+#define EMAC_MAN_DATA_Msk (0xffffu << EMAC_MAN_DATA_Pos) /**< \brief (EMAC_MAN)  */
+#define EMAC_MAN_DATA(value) ((EMAC_MAN_DATA_Msk & ((value) << EMAC_MAN_DATA_Pos)))
+#define EMAC_MAN_CODE_Pos 16
+#define EMAC_MAN_CODE_Msk (0x3u << EMAC_MAN_CODE_Pos) /**< \brief (EMAC_MAN)  */
+#define EMAC_MAN_CODE(value) ((EMAC_MAN_CODE_Msk & ((value) << EMAC_MAN_CODE_Pos)))
+#define EMAC_MAN_REGA_Pos 18
+#define EMAC_MAN_REGA_Msk (0x1fu << EMAC_MAN_REGA_Pos) /**< \brief (EMAC_MAN) Register Address */
+#define EMAC_MAN_REGA(value) ((EMAC_MAN_REGA_Msk & ((value) << EMAC_MAN_REGA_Pos)))
+#define EMAC_MAN_PHYA_Pos 23
+#define EMAC_MAN_PHYA_Msk (0x1fu << EMAC_MAN_PHYA_Pos) /**< \brief (EMAC_MAN) PHY Address */
+#define EMAC_MAN_PHYA(value) ((EMAC_MAN_PHYA_Msk & ((value) << EMAC_MAN_PHYA_Pos)))
+#define EMAC_MAN_RW_Pos 28
+#define EMAC_MAN_RW_Msk (0x3u << EMAC_MAN_RW_Pos) /**< \brief (EMAC_MAN) Read-write */
+#define EMAC_MAN_RW(value) ((EMAC_MAN_RW_Msk & ((value) << EMAC_MAN_RW_Pos)))
+#define EMAC_MAN_SOF_Pos 30
+#define EMAC_MAN_SOF_Msk (0x3u << EMAC_MAN_SOF_Pos) /**< \brief (EMAC_MAN) Start of frame */
+#define EMAC_MAN_SOF(value) ((EMAC_MAN_SOF_Msk & ((value) << EMAC_MAN_SOF_Pos)))
+/* -------- EMAC_PTR : (EMAC Offset: 0x38) Pause Time Register -------- */
+#define EMAC_PTR_PTIME_Pos 0
+#define EMAC_PTR_PTIME_Msk (0xffffu << EMAC_PTR_PTIME_Pos) /**< \brief (EMAC_PTR) Pause Time */
+#define EMAC_PTR_PTIME(value) ((EMAC_PTR_PTIME_Msk & ((value) << EMAC_PTR_PTIME_Pos)))
+/* -------- EMAC_PFR : (EMAC Offset: 0x3C) Pause Frames Received Register -------- */
+#define EMAC_PFR_FROK_Pos 0
+#define EMAC_PFR_FROK_Msk (0xffffu << EMAC_PFR_FROK_Pos) /**< \brief (EMAC_PFR) Pause Frames received OK */
+#define EMAC_PFR_FROK(value) ((EMAC_PFR_FROK_Msk & ((value) << EMAC_PFR_FROK_Pos)))
+/* -------- EMAC_FTO : (EMAC Offset: 0x40) Frames Transmitted Ok Register -------- */
+#define EMAC_FTO_FTOK_Pos 0
+#define EMAC_FTO_FTOK_Msk (0xffffffu << EMAC_FTO_FTOK_Pos) /**< \brief (EMAC_FTO) Frames Transmitted OK */
+#define EMAC_FTO_FTOK(value) ((EMAC_FTO_FTOK_Msk & ((value) << EMAC_FTO_FTOK_Pos)))
+/* -------- EMAC_SCF : (EMAC Offset: 0x44) Single Collision Frames Register -------- */
+#define EMAC_SCF_SCF_Pos 0
+#define EMAC_SCF_SCF_Msk (0xffffu << EMAC_SCF_SCF_Pos) /**< \brief (EMAC_SCF) Single Collision Frames */
+#define EMAC_SCF_SCF(value) ((EMAC_SCF_SCF_Msk & ((value) << EMAC_SCF_SCF_Pos)))
+/* -------- EMAC_MCF : (EMAC Offset: 0x48) Multiple Collision Frames Register -------- */
+#define EMAC_MCF_MCF_Pos 0
+#define EMAC_MCF_MCF_Msk (0xffffu << EMAC_MCF_MCF_Pos) /**< \brief (EMAC_MCF) Multicollision Frames */
+#define EMAC_MCF_MCF(value) ((EMAC_MCF_MCF_Msk & ((value) << EMAC_MCF_MCF_Pos)))
+/* -------- EMAC_FRO : (EMAC Offset: 0x4C) Frames Received Ok Register -------- */
+#define EMAC_FRO_FROK_Pos 0
+#define EMAC_FRO_FROK_Msk (0xffffffu << EMAC_FRO_FROK_Pos) /**< \brief (EMAC_FRO) Frames Received OK */
+#define EMAC_FRO_FROK(value) ((EMAC_FRO_FROK_Msk & ((value) << EMAC_FRO_FROK_Pos)))
+/* -------- EMAC_FCSE : (EMAC Offset: 0x50) Frame Check Sequence Errors Register -------- */
+#define EMAC_FCSE_FCSE_Pos 0
+#define EMAC_FCSE_FCSE_Msk (0xffu << EMAC_FCSE_FCSE_Pos) /**< \brief (EMAC_FCSE) Frame Check Sequence Errors */
+#define EMAC_FCSE_FCSE(value) ((EMAC_FCSE_FCSE_Msk & ((value) << EMAC_FCSE_FCSE_Pos)))
+/* -------- EMAC_ALE : (EMAC Offset: 0x54) Alignment Errors Register -------- */
+#define EMAC_ALE_ALE_Pos 0
+#define EMAC_ALE_ALE_Msk (0xffu << EMAC_ALE_ALE_Pos) /**< \brief (EMAC_ALE) Alignment Errors */
+#define EMAC_ALE_ALE(value) ((EMAC_ALE_ALE_Msk & ((value) << EMAC_ALE_ALE_Pos)))
+/* -------- EMAC_DTF : (EMAC Offset: 0x58) Deferred Transmission Frames Register -------- */
+#define EMAC_DTF_DTF_Pos 0
+#define EMAC_DTF_DTF_Msk (0xffffu << EMAC_DTF_DTF_Pos) /**< \brief (EMAC_DTF) Deferred Transmission Frames */
+#define EMAC_DTF_DTF(value) ((EMAC_DTF_DTF_Msk & ((value) << EMAC_DTF_DTF_Pos)))
+/* -------- EMAC_LCOL : (EMAC Offset: 0x5C) Late Collisions Register -------- */
+#define EMAC_LCOL_LCOL_Pos 0
+#define EMAC_LCOL_LCOL_Msk (0xffu << EMAC_LCOL_LCOL_Pos) /**< \brief (EMAC_LCOL) Late Collisions */
+#define EMAC_LCOL_LCOL(value) ((EMAC_LCOL_LCOL_Msk & ((value) << EMAC_LCOL_LCOL_Pos)))
+/* -------- EMAC_ECOL : (EMAC Offset: 0x60) Excessive Collisions Register -------- */
+#define EMAC_ECOL_EXCOL_Pos 0
+#define EMAC_ECOL_EXCOL_Msk (0xffu << EMAC_ECOL_EXCOL_Pos) /**< \brief (EMAC_ECOL) Excessive Collisions */
+#define EMAC_ECOL_EXCOL(value) ((EMAC_ECOL_EXCOL_Msk & ((value) << EMAC_ECOL_EXCOL_Pos)))
+/* -------- EMAC_TUND : (EMAC Offset: 0x64) Transmit Underrun Errors Register -------- */
+#define EMAC_TUND_TUND_Pos 0
+#define EMAC_TUND_TUND_Msk (0xffu << EMAC_TUND_TUND_Pos) /**< \brief (EMAC_TUND) Transmit Underruns */
+#define EMAC_TUND_TUND(value) ((EMAC_TUND_TUND_Msk & ((value) << EMAC_TUND_TUND_Pos)))
+/* -------- EMAC_CSE : (EMAC Offset: 0x68) Carrier Sense Errors Register -------- */
+#define EMAC_CSE_CSE_Pos 0
+#define EMAC_CSE_CSE_Msk (0xffu << EMAC_CSE_CSE_Pos) /**< \brief (EMAC_CSE) Carrier Sense Errors */
+#define EMAC_CSE_CSE(value) ((EMAC_CSE_CSE_Msk & ((value) << EMAC_CSE_CSE_Pos)))
+/* -------- EMAC_RRE : (EMAC Offset: 0x6C) Receive Resource Errors Register -------- */
+#define EMAC_RRE_RRE_Pos 0
+#define EMAC_RRE_RRE_Msk (0xffffu << EMAC_RRE_RRE_Pos) /**< \brief (EMAC_RRE) Receive Resource Errors */
+#define EMAC_RRE_RRE(value) ((EMAC_RRE_RRE_Msk & ((value) << EMAC_RRE_RRE_Pos)))
+/* -------- EMAC_ROV : (EMAC Offset: 0x70) Receive Overrun Errors Register -------- */
+#define EMAC_ROV_ROVR_Pos 0
+#define EMAC_ROV_ROVR_Msk (0xffu << EMAC_ROV_ROVR_Pos) /**< \brief (EMAC_ROV) Receive Overrun */
+#define EMAC_ROV_ROVR(value) ((EMAC_ROV_ROVR_Msk & ((value) << EMAC_ROV_ROVR_Pos)))
+/* -------- EMAC_RSE : (EMAC Offset: 0x74) Receive Symbol Errors Register -------- */
+#define EMAC_RSE_RSE_Pos 0
+#define EMAC_RSE_RSE_Msk (0xffu << EMAC_RSE_RSE_Pos) /**< \brief (EMAC_RSE) Receive Symbol Errors */
+#define EMAC_RSE_RSE(value) ((EMAC_RSE_RSE_Msk & ((value) << EMAC_RSE_RSE_Pos)))
+/* -------- EMAC_ELE : (EMAC Offset: 0x78) Excessive Length Errors Register -------- */
+#define EMAC_ELE_EXL_Pos 0
+#define EMAC_ELE_EXL_Msk (0xffu << EMAC_ELE_EXL_Pos) /**< \brief (EMAC_ELE) Excessive Length Errors */
+#define EMAC_ELE_EXL(value) ((EMAC_ELE_EXL_Msk & ((value) << EMAC_ELE_EXL_Pos)))
+/* -------- EMAC_RJA : (EMAC Offset: 0x7C) Receive Jabbers Register -------- */
+#define EMAC_RJA_RJB_Pos 0
+#define EMAC_RJA_RJB_Msk (0xffu << EMAC_RJA_RJB_Pos) /**< \brief (EMAC_RJA) Receive Jabbers */
+#define EMAC_RJA_RJB(value) ((EMAC_RJA_RJB_Msk & ((value) << EMAC_RJA_RJB_Pos)))
+/* -------- EMAC_USF : (EMAC Offset: 0x80) Undersize Frames Register -------- */
+#define EMAC_USF_USF_Pos 0
+#define EMAC_USF_USF_Msk (0xffu << EMAC_USF_USF_Pos) /**< \brief (EMAC_USF) Undersize frames */
+#define EMAC_USF_USF(value) ((EMAC_USF_USF_Msk & ((value) << EMAC_USF_USF_Pos)))
+/* -------- EMAC_STE : (EMAC Offset: 0x84) SQE Test Errors Register -------- */
+#define EMAC_STE_SQER_Pos 0
+#define EMAC_STE_SQER_Msk (0xffu << EMAC_STE_SQER_Pos) /**< \brief (EMAC_STE) SQE test errors */
+#define EMAC_STE_SQER(value) ((EMAC_STE_SQER_Msk & ((value) << EMAC_STE_SQER_Pos)))
+/* -------- EMAC_RLE : (EMAC Offset: 0x88) Received Length Field Mismatch Register -------- */
+#define EMAC_RLE_RLFM_Pos 0
+#define EMAC_RLE_RLFM_Msk (0xffu << EMAC_RLE_RLFM_Pos) /**< \brief (EMAC_RLE) Receive Length Field Mismatch */
+#define EMAC_RLE_RLFM(value) ((EMAC_RLE_RLFM_Msk & ((value) << EMAC_RLE_RLFM_Pos)))
+/* -------- EMAC_HRB : (EMAC Offset: 0x90) Hash Register Bottom [31:0] Register -------- */
+#define EMAC_HRB_ADDR_Pos 0
+#define EMAC_HRB_ADDR_Msk (0xffffffffu << EMAC_HRB_ADDR_Pos) /**< \brief (EMAC_HRB)  */
+#define EMAC_HRB_ADDR(value) ((EMAC_HRB_ADDR_Msk & ((value) << EMAC_HRB_ADDR_Pos)))
+/* -------- EMAC_HRT : (EMAC Offset: 0x94) Hash Register Top [63:32] Register -------- */
+#define EMAC_HRT_ADDR_Pos 0
+#define EMAC_HRT_ADDR_Msk (0xffffffffu << EMAC_HRT_ADDR_Pos) /**< \brief (EMAC_HRT)  */
+#define EMAC_HRT_ADDR(value) ((EMAC_HRT_ADDR_Msk & ((value) << EMAC_HRT_ADDR_Pos)))
+/* -------- EMAC_SAxB : (EMAC Offset: N/A) Specific Address 1 Bottom Register -------- */
+#define EMAC_SAxB_ADDR_Pos 0
+#define EMAC_SAxB_ADDR_Msk (0xffffffffu << EMAC_SAxB_ADDR_Pos) /**< \brief (EMAC_SAxB)  */
+#define EMAC_SAxB_ADDR(value) ((EMAC_SAxB_ADDR_Msk & ((value) << EMAC_SAxB_ADDR_Pos)))
+/* -------- EMAC_SAxT : (EMAC Offset: N/A) Specific Address 1 Top Register -------- */
+#define EMAC_SAxT_ADDR_Pos 0
+#define EMAC_SAxT_ADDR_Msk (0xffffu << EMAC_SAxT_ADDR_Pos) /**< \brief (EMAC_SAxT)  */
+#define EMAC_SAxT_ADDR(value) ((EMAC_SAxT_ADDR_Msk & ((value) << EMAC_SAxT_ADDR_Pos)))
+/* -------- EMAC_TID : (EMAC Offset: 0xB8) Type ID Checking Register -------- */
+#define EMAC_TID_TID_Pos 0
+#define EMAC_TID_TID_Msk (0xffffu << EMAC_TID_TID_Pos) /**< \brief (EMAC_TID) Type ID checking */
+#define EMAC_TID_TID(value) ((EMAC_TID_TID_Msk & ((value) << EMAC_TID_TID_Pos)))
+/* -------- EMAC_USRIO : (EMAC Offset: 0xC0) User Input/Output Register -------- */
+#define EMAC_USRIO_RMII (0x1u << 0) /**< \brief (EMAC_USRIO) Reduce MII */
+#define EMAC_USRIO_CLKEN (0x1u << 1) /**< \brief (EMAC_USRIO) Clock Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_EMAC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_gpbr.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_gpbr.h
new file mode 100644
index 0000000..df9f1eb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_gpbr.h
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_GPBR_COMPONENT_
+#define _SAM3XA_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_GPBR General Purpose Backup Register */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Gpbr hardware registers */
+typedef struct {
+  RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_GPBR_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_hsmci.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_hsmci.h
new file mode 100644
index 0000000..3351f78
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_hsmci.h
@@ -0,0 +1,341 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_HSMCI_COMPONENT_
+#define _SAM3XA_HSMCI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_HSMCI High Speed MultiMedia Card Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Hsmci hardware registers */
+typedef struct {
+  WoReg HSMCI_CR;        /**< \brief (Hsmci Offset: 0x00) Control Register */
+  RwReg HSMCI_MR;        /**< \brief (Hsmci Offset: 0x04) Mode Register */
+  RwReg HSMCI_DTOR;      /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
+  RwReg HSMCI_SDCR;      /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
+  RwReg HSMCI_ARGR;      /**< \brief (Hsmci Offset: 0x10) Argument Register */
+  WoReg HSMCI_CMDR;      /**< \brief (Hsmci Offset: 0x14) Command Register */
+  RwReg HSMCI_BLKR;      /**< \brief (Hsmci Offset: 0x18) Block Register */
+  RwReg HSMCI_CSTOR;     /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
+  RoReg HSMCI_RSPR[4];   /**< \brief (Hsmci Offset: 0x20) Response Register */
+  RoReg HSMCI_RDR;       /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
+  WoReg HSMCI_TDR;       /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
+  RoReg Reserved1[2];
+  RoReg HSMCI_SR;        /**< \brief (Hsmci Offset: 0x40) Status Register */
+  WoReg HSMCI_IER;       /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
+  WoReg HSMCI_IDR;       /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
+  RoReg HSMCI_IMR;       /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
+  RwReg HSMCI_DMA;       /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */
+  RwReg HSMCI_CFG;       /**< \brief (Hsmci Offset: 0x54) Configuration Register */
+  RoReg Reserved2[35];
+  RwReg HSMCI_WPMR;      /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
+  RoReg HSMCI_WPSR;      /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved3[69];
+  RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
+} Hsmci;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
+#define HSMCI_MR_CLKDIV_Pos 0
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
+#define HSMCI_MR_PWSDIV_Pos 8
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
+#define HSMCI_DTOR_DTOCYC_Pos 0
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
+#define HSMCI_DTOR_DTOMUL_Pos 4
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
+#define   HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
+#define   HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
+#define   HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
+#define   HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
+#define   HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
+#define   HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
+#define   HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
+#define   HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
+#define HSMCI_SDCR_SDCSEL_Pos 0
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
+#define   HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
+#define   HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) SDCARD/SDIO Slot B selected */
+#define   HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCBUS_Pos 6
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
+#define   HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
+#define   HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
+#define   HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
+#define HSMCI_ARGR_ARG_Pos 0
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
+#define HSMCI_CMDR_CMDNB_Pos 0
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
+#define HSMCI_CMDR_RSPTYP_Pos 6
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
+#define   HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
+#define   HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
+#define   HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
+#define   HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
+#define HSMCI_CMDR_SPCMD_Pos 8
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
+#define   HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
+#define   HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
+#define   HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
+#define   HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
+#define   HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
+#define   HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
+#define   HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
+#define   HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
+#define   HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
+#define   HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
+#define HSMCI_CMDR_TRCMD_Pos 16
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
+#define   HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
+#define   HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
+#define   HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
+#define   HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
+#define   HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
+#define HSMCI_CMDR_TRTYP_Pos 19
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
+#define   HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
+#define   HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
+#define   HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
+#define   HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
+#define   HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
+#define HSMCI_CMDR_IOSPCMD_Pos 24
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
+#define   HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
+#define   HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
+#define   HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
+#define HSMCI_BLKR_BCNT_Pos 0
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
+#define   HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
+#define   HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define   HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BLKLEN_Pos 16
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
+#define HSMCI_CSTOR_CSTOCYC_Pos 0
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
+#define HSMCI_CSTOR_CSTOMUL_Pos 4
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
+#define   HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
+#define   HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
+#define   HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
+#define   HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
+#define   HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
+#define   HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
+#define   HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
+#define   HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
+#define HSMCI_RSPR_RSP_Pos 0
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
+#define HSMCI_RDR_DATA_Pos 0
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
+#define HSMCI_TDR_DATA_Pos 0
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
+#define HSMCI_SR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_SR)  */
+#define HSMCI_SR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_SR)  */
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
+#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */
+#define HSMCI_SR_DMADONE (0x1u << 25) /**< \brief (HSMCI_SR) DMA Transfer done */
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
+#define HSMCI_IER_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IER)  */
+#define HSMCI_IER_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IER)  */
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
+#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */
+#define HSMCI_IER_DMADONE (0x1u << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
+#define HSMCI_IDR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IDR)  */
+#define HSMCI_IDR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IDR)  */
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
+#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */
+#define HSMCI_IDR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
+#define HSMCI_IMR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IMR)  */
+#define HSMCI_IMR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IMR)  */
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
+#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */
+#define HSMCI_IMR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
+/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
+#define HSMCI_DMA_OFFSET_Pos 0
+#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */
+#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos)))
+#define HSMCI_DMA_CHKSIZE (0x1u << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */
+#define   HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */
+#define   HSMCI_DMA_CHKSIZE_4 (0x1u << 4) /**< \brief (HSMCI_DMA) 4 data available */
+#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */
+#define HSMCI_DMA_ROPT (0x1u << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
+#define HSMCI_WPMR_WP_KEY_Pos 8
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
+#define HSMCI_WPSR_WP_VS_Pos 0
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
+#define   HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
+#define   HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
+#define   HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
+#define   HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
+#define HSMCI_WPSR_WP_VSRC_Pos 8
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
+/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
+#define HSMCI_FIFO_DATA_Pos 0
+#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */
+#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_HSMCI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_matrix.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_matrix.h
new file mode 100644
index 0000000..360c954
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_matrix.h
@@ -0,0 +1,285 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_MATRIX_COMPONENT_
+#define _SAM3XA_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Matrix hardware registers */
+typedef struct {
+  RwReg MATRIX_MCFG[6]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+  RoReg Reserved1[10];
+  RwReg MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+  RoReg Reserved2[7];
+  RwReg MATRIX_PRAS0;   /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+  RoReg Reserved3[1];
+  RwReg MATRIX_PRAS1;   /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+  RoReg Reserved4[1];
+  RwReg MATRIX_PRAS2;   /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+  RoReg Reserved5[1];
+  RwReg MATRIX_PRAS3;   /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+  RoReg Reserved6[1];
+  RwReg MATRIX_PRAS4;   /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
+  RoReg Reserved7[1];
+  RwReg MATRIX_PRAS5;   /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */
+  RoReg Reserved8[1];
+  RwReg MATRIX_PRAS6;   /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */
+  RoReg Reserved9[1];
+  RwReg MATRIX_PRAS7;   /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */
+  RoReg Reserved10[1];
+  RwReg MATRIX_PRAS8;   /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */
+  RoReg Reserved11[1];
+  RoReg Reserved12[14];
+  RwReg MATRIX_MRCR;    /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */
+  RoReg Reserved13[4];
+  RwReg CCFG_SYSIO;     /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */
+  RoReg Reserved14[51];
+  RwReg MATRIX_WPMR;    /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+  RoReg MATRIX_WPSR;    /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- MATRIX_MCFG[6] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[6]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[9]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+#define MATRIX_PRAS0_M4PR_Pos 16
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
+#define MATRIX_PRAS0_M5PR_Pos 20
+#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) /**< \brief (MATRIX_PRAS0) Master 5 Priority */
+#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+#define MATRIX_PRAS1_M4PR_Pos 16
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
+#define MATRIX_PRAS1_M5PR_Pos 20
+#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) /**< \brief (MATRIX_PRAS1) Master 5 Priority */
+#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+#define MATRIX_PRAS2_M4PR_Pos 16
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
+#define MATRIX_PRAS2_M5PR_Pos 20
+#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) /**< \brief (MATRIX_PRAS2) Master 5 Priority */
+#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+#define MATRIX_PRAS3_M4PR_Pos 16
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
+#define MATRIX_PRAS3_M5PR_Pos 20
+#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) /**< \brief (MATRIX_PRAS3) Master 5 Priority */
+#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos)))
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
+#define MATRIX_PRAS4_M0PR_Pos 0
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
+#define MATRIX_PRAS4_M1PR_Pos 4
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
+#define MATRIX_PRAS4_M2PR_Pos 8
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
+#define MATRIX_PRAS4_M3PR_Pos 12
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
+#define MATRIX_PRAS4_M4PR_Pos 16
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
+#define MATRIX_PRAS4_M5PR_Pos 20
+#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) /**< \brief (MATRIX_PRAS4) Master 5 Priority */
+#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos)))
+/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
+#define MATRIX_PRAS5_M0PR_Pos 0
+#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */
+#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))
+#define MATRIX_PRAS5_M1PR_Pos 4
+#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */
+#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))
+#define MATRIX_PRAS5_M2PR_Pos 8
+#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */
+#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))
+#define MATRIX_PRAS5_M3PR_Pos 12
+#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */
+#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))
+#define MATRIX_PRAS5_M4PR_Pos 16
+#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */
+#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))
+#define MATRIX_PRAS5_M5PR_Pos 20
+#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) /**< \brief (MATRIX_PRAS5) Master 5 Priority */
+#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos)))
+/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
+#define MATRIX_PRAS6_M0PR_Pos 0
+#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */
+#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))
+#define MATRIX_PRAS6_M1PR_Pos 4
+#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */
+#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))
+#define MATRIX_PRAS6_M2PR_Pos 8
+#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */
+#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))
+#define MATRIX_PRAS6_M3PR_Pos 12
+#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */
+#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))
+#define MATRIX_PRAS6_M4PR_Pos 16
+#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */
+#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))
+#define MATRIX_PRAS6_M5PR_Pos 20
+#define MATRIX_PRAS6_M5PR_Msk (0x3u << MATRIX_PRAS6_M5PR_Pos) /**< \brief (MATRIX_PRAS6) Master 5 Priority */
+#define MATRIX_PRAS6_M5PR(value) ((MATRIX_PRAS6_M5PR_Msk & ((value) << MATRIX_PRAS6_M5PR_Pos)))
+/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
+#define MATRIX_PRAS7_M0PR_Pos 0
+#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */
+#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))
+#define MATRIX_PRAS7_M1PR_Pos 4
+#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */
+#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))
+#define MATRIX_PRAS7_M2PR_Pos 8
+#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */
+#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))
+#define MATRIX_PRAS7_M3PR_Pos 12
+#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */
+#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))
+#define MATRIX_PRAS7_M4PR_Pos 16
+#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */
+#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))
+#define MATRIX_PRAS7_M5PR_Pos 20
+#define MATRIX_PRAS7_M5PR_Msk (0x3u << MATRIX_PRAS7_M5PR_Pos) /**< \brief (MATRIX_PRAS7) Master 5 Priority */
+#define MATRIX_PRAS7_M5PR(value) ((MATRIX_PRAS7_M5PR_Msk & ((value) << MATRIX_PRAS7_M5PR_Pos)))
+/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
+#define MATRIX_PRAS8_M0PR_Pos 0
+#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */
+#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))
+#define MATRIX_PRAS8_M1PR_Pos 4
+#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */
+#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))
+#define MATRIX_PRAS8_M2PR_Pos 8
+#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */
+#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))
+#define MATRIX_PRAS8_M3PR_Pos 12
+#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */
+#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))
+#define MATRIX_PRAS8_M4PR_Pos 16
+#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */
+#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))
+#define MATRIX_PRAS8_M5PR_Pos 20
+#define MATRIX_PRAS8_M5PR_Msk (0x3u << MATRIX_PRAS8_M5PR_Pos) /**< \brief (MATRIX_PRAS8) Master 5 Priority */
+#define MATRIX_PRAS8_M5PR(value) ((MATRIX_PRAS8_M5PR_Msk & ((value) << MATRIX_PRAS8_M5PR_Pos)))
+/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
+#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */
+#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */
+#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */
+#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */
+#define MATRIX_MRCR_RCB4_Pos 4
+#define MATRIX_MRCR_RCB4_Msk (0x3u << MATRIX_MRCR_RCB4_Pos) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */
+#define MATRIX_MRCR_RCB4(value) ((MATRIX_MRCR_RCB4_Msk & ((value) << MATRIX_MRCR_RCB4_Pos)))
+#define MATRIX_MRCR_RCB5 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 5 */
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PC0 or ERASE Assignment */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_MATRIX_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_pdc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_pdc.h
new file mode 100644
index 0000000..afb3522
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_pdc.h
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PDC_COMPONENT_
+#define _SAM3XA_PDC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PDC Peripheral DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pdc hardware registers */
+typedef struct {
+  RwReg PERIPH_RPR;  /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
+  RwReg PERIPH_RCR;  /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
+  RwReg PERIPH_TPR;  /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
+  RwReg PERIPH_TCR;  /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
+  RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+  RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+  RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+  RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+  WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+  RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_PDC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_pio.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_pio.h
new file mode 100644
index 0000000..8522954
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_pio.h
@@ -0,0 +1,1435 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIO_COMPONENT_
+#define _SAM3XA_PIO_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pio hardware registers */
+typedef struct {
+  WoReg PIO_PER;       /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+  WoReg PIO_PDR;       /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+  RoReg PIO_PSR;       /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+  RoReg Reserved1[1];
+  WoReg PIO_OER;       /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+  WoReg PIO_ODR;       /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+  RoReg PIO_OSR;       /**< \brief (Pio Offset: 0x0018) Output Status Register */
+  RoReg Reserved2[1];
+  WoReg PIO_IFER;      /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+  WoReg PIO_IFDR;      /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+  RoReg PIO_IFSR;      /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+  RoReg Reserved3[1];
+  WoReg PIO_SODR;      /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+  WoReg PIO_CODR;      /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+  RwReg PIO_ODSR;      /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+  RoReg PIO_PDSR;      /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+  WoReg PIO_IER;       /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+  WoReg PIO_IDR;       /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+  RoReg PIO_IMR;       /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+  RoReg PIO_ISR;       /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+  WoReg PIO_MDER;      /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+  WoReg PIO_MDDR;      /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+  RoReg PIO_MDSR;      /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+  RoReg Reserved4[1];
+  WoReg PIO_PUDR;      /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+  WoReg PIO_PUER;      /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+  RoReg PIO_PUSR;      /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+  RoReg Reserved5[1];
+  RwReg PIO_ABSR;      /**< \brief (Pio Offset: 0x0070) Peripheral AB Select Register */
+  RoReg Reserved6[3];
+  WoReg PIO_SCIFSR;    /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */
+  WoReg PIO_DIFSR;     /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */
+  RoReg PIO_IFDGSR;    /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */
+  RwReg PIO_SCDR;      /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+  RoReg Reserved7[4];
+  WoReg PIO_OWER;      /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+  WoReg PIO_OWDR;      /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+  RoReg PIO_OWSR;      /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+  RoReg Reserved8[1];
+  WoReg PIO_AIMER;     /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+  WoReg PIO_AIMDR;     /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
+  RoReg PIO_AIMMR;     /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+  RoReg Reserved9[1];
+  WoReg PIO_ESR;       /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+  WoReg PIO_LSR;       /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+  RoReg PIO_ELSR;      /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+  RoReg Reserved10[1];
+  WoReg PIO_FELLSR;    /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
+  WoReg PIO_REHLSR;    /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
+  RoReg PIO_FRLHSR;    /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+  RoReg Reserved11[1];
+  RoReg PIO_LOCKSR;    /**< \brief (Pio Offset: 0x00E0) Lock Status */
+  RwReg PIO_WPMR;      /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PIO_WPSR;      /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
+} Pio;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
+/* -------- PIO_ABSR : (PIO Offset: 0x0070) Peripheral AB Select Register -------- */
+#define PIO_ABSR_P0 (0x1u << 0) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P1 (0x1u << 1) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P2 (0x1u << 2) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P3 (0x1u << 3) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P4 (0x1u << 4) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P5 (0x1u << 5) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P6 (0x1u << 6) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P7 (0x1u << 7) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P8 (0x1u << 8) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P9 (0x1u << 9) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P10 (0x1u << 10) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P11 (0x1u << 11) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P12 (0x1u << 12) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P13 (0x1u << 13) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P14 (0x1u << 14) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P15 (0x1u << 15) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P16 (0x1u << 16) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P17 (0x1u << 17) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P18 (0x1u << 18) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P19 (0x1u << 19) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P20 (0x1u << 20) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P21 (0x1u << 21) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P22 (0x1u << 22) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P23 (0x1u << 23) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P24 (0x1u << 24) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P25 (0x1u << 25) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P26 (0x1u << 26) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P27 (0x1u << 27) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P28 (0x1u << 28) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P29 (0x1u << 29) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P30 (0x1u << 30) /**< \brief (PIO_ABSR) Peripheral A Select. */
+#define PIO_ABSR_P31 (0x1u << 31) /**< \brief (PIO_ABSR) Peripheral A Select. */
+/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */
+#define PIO_SCIFSR_P0 (0x1u << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P1 (0x1u << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P2 (0x1u << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P3 (0x1u << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P4 (0x1u << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P5 (0x1u << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P6 (0x1u << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P7 (0x1u << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P8 (0x1u << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P9 (0x1u << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P10 (0x1u << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P11 (0x1u << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P12 (0x1u << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P13 (0x1u << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P14 (0x1u << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P15 (0x1u << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P16 (0x1u << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P17 (0x1u << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P18 (0x1u << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P19 (0x1u << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P20 (0x1u << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P21 (0x1u << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P22 (0x1u << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P23 (0x1u << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P24 (0x1u << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P25 (0x1u << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P26 (0x1u << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P27 (0x1u << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P28 (0x1u << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P29 (0x1u << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P30 (0x1u << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+#define PIO_SCIFSR_P31 (0x1u << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */
+/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */
+#define PIO_DIFSR_P0 (0x1u << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P1 (0x1u << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P2 (0x1u << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P3 (0x1u << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P4 (0x1u << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P5 (0x1u << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P6 (0x1u << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P7 (0x1u << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P8 (0x1u << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P9 (0x1u << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P10 (0x1u << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P11 (0x1u << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P12 (0x1u << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P13 (0x1u << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P14 (0x1u << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P15 (0x1u << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P16 (0x1u << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P17 (0x1u << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P18 (0x1u << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P19 (0x1u << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P20 (0x1u << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P21 (0x1u << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P22 (0x1u << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P23 (0x1u << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P24 (0x1u << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P25 (0x1u << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P26 (0x1u << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P27 (0x1u << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P28 (0x1u << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P29 (0x1u << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P30 (0x1u << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+#define PIO_DIFSR_P31 (0x1u << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */
+/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */
+#define PIO_IFDGSR_P0 (0x1u << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P1 (0x1u << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P2 (0x1u << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P3 (0x1u << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P4 (0x1u << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P5 (0x1u << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P6 (0x1u << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P7 (0x1u << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P8 (0x1u << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P9 (0x1u << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P10 (0x1u << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P11 (0x1u << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P12 (0x1u << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P13 (0x1u << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P14 (0x1u << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P15 (0x1u << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P16 (0x1u << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P17 (0x1u << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P18 (0x1u << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P19 (0x1u << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P20 (0x1u << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P21 (0x1u << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P22 (0x1u << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P23 (0x1u << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P24 (0x1u << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P25 (0x1u << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P26 (0x1u << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P27 (0x1u << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P28 (0x1u << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P29 (0x1u << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P30 (0x1u << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFDGSR_P31 (0x1u << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_PIO_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_pmc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_pmc.h
new file mode 100644
index 0000000..a5cffc5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_pmc.h
@@ -0,0 +1,416 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PMC_COMPONENT_
+#define _SAM3XA_PMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PMC Power Management Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pmc hardware registers */
+typedef struct {
+  WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+  WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+  RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+  RoReg Reserved1[1];
+  WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+  WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+  RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+  RwReg CKGR_UCKR;     /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */
+  RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+  RoReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+  RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+  RoReg Reserved2[1];
+  RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+  RoReg Reserved3[1];
+  RwReg PMC_USB;       /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
+  RoReg Reserved4[1];
+  RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+  RoReg Reserved5[5];
+  WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+  WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+  RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
+  RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+  RwReg PMC_FSMR;      /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+  RwReg PMC_FSPR;      /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+  WoReg PMC_FOCR;      /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+  RoReg Reserved6[26];
+  RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved7[5];
+  WoReg PMC_PCER1;     /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
+  WoReg PMC_PCDR1;     /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
+  RoReg PMC_PCSR1;     /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
+  RwReg PMC_PCR;       /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */
+} Pmc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB OTG Clock (48 MHz, USB_48M) for UTMI */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB OTG Clock (48 MHz, USB_48M) for UTMI */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB OTG Clock (48 MHz, USB_48M) Clock Status */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
+#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
+#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
+#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
+/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
+#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */
+#define CKGR_UCKR_UPLLCOUNT_Pos 20
+#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */
+#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define   PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR)  */
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
+#define PMC_USB_USBDIV_Pos 8
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define   PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL Clock is selected */
+#define   PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define   PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define   PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define   PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define   PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define   PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define   PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define   PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
+#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */
+#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */
+#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */
+#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */
+#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */
+#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */
+#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */
+#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */
+#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */
+#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
+#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */
+#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */
+#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */
+#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */
+#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */
+#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */
+#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */
+#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */
+#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */
+#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
+#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */
+#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */
+#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */
+#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */
+#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */
+#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */
+#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */
+#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */
+#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */
+#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */
+/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */
+#define PMC_PCR_PID_Pos 0
+#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */
+#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
+#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */
+#define PMC_PCR_DIV_Pos 16
+#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */
+#define   PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */
+#define   PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */
+#define   PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */
+#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_PMC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_pwm.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_pwm.h
new file mode 100644
index 0000000..f2c29d8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_pwm.h
@@ -0,0 +1,667 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PWM_COMPONENT_
+#define _SAM3XA_PWM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+  RwReg      PWM_CMR;       /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+  RwReg      PWM_CDTY;      /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+  RwReg      PWM_CDTYUPD;   /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
+  RwReg      PWM_CPRD;      /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
+  RwReg      PWM_CPRDUPD;   /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
+  RwReg      PWM_CCNT;      /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
+  RwReg      PWM_DT;        /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
+  RwReg      PWM_DTUPD;     /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
+} PwmCh_num;
+/** \brief PwmCmp hardware registers */
+typedef struct {
+  RwReg      PWM_CMPV;      /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
+  RwReg      PWM_CMPVUPD;   /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
+  RwReg      PWM_CMPM;      /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
+  RwReg      PWM_CMPMUPD;   /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
+} PwmCmp;
+/** \brief Pwm hardware registers */
+#define PWMCMP_NUMBER 8
+#define PWMCH_NUM_NUMBER 8
+typedef struct {
+  RwReg      PWM_CLK;       /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
+  WoReg      PWM_ENA;       /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+  WoReg      PWM_DIS;       /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+  RoReg      PWM_SR;        /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+  WoReg      PWM_IER1;      /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
+  WoReg      PWM_IDR1;      /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
+  RoReg      PWM_IMR1;      /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
+  RoReg      PWM_ISR1;      /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
+  RwReg      PWM_SCM;       /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      PWM_SCUC;      /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
+  RwReg      PWM_SCUP;      /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
+  WoReg      PWM_SCUPUPD;   /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
+  WoReg      PWM_IER2;      /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
+  WoReg      PWM_IDR2;      /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
+  RoReg      PWM_IMR2;      /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
+  RoReg      PWM_ISR2;      /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
+  RwReg      PWM_OOV;       /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
+  RwReg      PWM_OS;        /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
+  WoReg      PWM_OSS;       /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
+  WoReg      PWM_OSC;       /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
+  WoReg      PWM_OSSUPD;    /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
+  WoReg      PWM_OSCUPD;    /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
+  RwReg      PWM_FMR;       /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
+  RoReg      PWM_FSR;       /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
+  WoReg      PWM_FCR;       /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
+  RwReg      PWM_FPV;       /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
+  RwReg      PWM_FPE1;      /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register 1 */
+  RwReg      PWM_FPE2;      /**< \brief (Pwm Offset: 0x70) PWM Fault Protection Enable Register 2 */
+  RoReg      Reserved2[2];
+  RwReg      PWM_ELMR[2];   /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
+  RoReg      Reserved3[11];
+  RwReg      PWM_SMMR;      /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
+  RoReg      Reserved4[12];
+  WoReg      PWM_WPCR;      /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
+  RoReg      PWM_WPSR;      /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
+  RoReg      Reserved5[7];
+  RwReg      PWM_TPR;       /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
+  RwReg      PWM_TCR;       /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
+  RoReg      Reserved6[2];
+  RwReg      PWM_TNPR;      /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
+  RwReg      PWM_TNCR;      /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
+  WoReg      PWM_PTCR;      /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
+  RoReg      PWM_PTSR;      /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
+  RoReg      Reserved7[2];
+  PwmCmp     PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
+  RoReg      Reserved8[20];
+  PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 7 */
+} Pwm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
+#define PWM_CLK_DIVA_Pos 0
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
+#define PWM_CLK_PREA_Pos 8
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
+#define PWM_CLK_DIVB_Pos 16
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
+#define PWM_CLK_PREB_Pos 24
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID4 (0x1u << 4) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID5 (0x1u << 5) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID6 (0x1u << 6) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID7 (0x1u << 7) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID4 (0x1u << 4) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID5 (0x1u << 5) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID6 (0x1u << 6) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID7 (0x1u << 7) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID4 (0x1u << 4) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID5 (0x1u << 5) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID6 (0x1u << 6) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID7 (0x1u << 7) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
+#define PWM_IER1_CHID4 (0x1u << 4) /**< \brief (PWM_IER1) Counter Event on Channel 4 Interrupt Enable */
+#define PWM_IER1_CHID5 (0x1u << 5) /**< \brief (PWM_IER1) Counter Event on Channel 5 Interrupt Enable */
+#define PWM_IER1_CHID6 (0x1u << 6) /**< \brief (PWM_IER1) Counter Event on Channel 6 Interrupt Enable */
+#define PWM_IER1_CHID7 (0x1u << 7) /**< \brief (PWM_IER1) Counter Event on Channel 7 Interrupt Enable */
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
+#define PWM_IER1_FCHID4 (0x1u << 20) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 4 Interrupt Enable */
+#define PWM_IER1_FCHID5 (0x1u << 21) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 5 Interrupt Enable */
+#define PWM_IER1_FCHID6 (0x1u << 22) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 6 Interrupt Enable */
+#define PWM_IER1_FCHID7 (0x1u << 23) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 7 Interrupt Enable */
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
+#define PWM_IDR1_CHID4 (0x1u << 4) /**< \brief (PWM_IDR1) Counter Event on Channel 4 Interrupt Disable */
+#define PWM_IDR1_CHID5 (0x1u << 5) /**< \brief (PWM_IDR1) Counter Event on Channel 5 Interrupt Disable */
+#define PWM_IDR1_CHID6 (0x1u << 6) /**< \brief (PWM_IDR1) Counter Event on Channel 6 Interrupt Disable */
+#define PWM_IDR1_CHID7 (0x1u << 7) /**< \brief (PWM_IDR1) Counter Event on Channel 7 Interrupt Disable */
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
+#define PWM_IDR1_FCHID4 (0x1u << 20) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 4 Interrupt Disable */
+#define PWM_IDR1_FCHID5 (0x1u << 21) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 5 Interrupt Disable */
+#define PWM_IDR1_FCHID6 (0x1u << 22) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 6 Interrupt Disable */
+#define PWM_IDR1_FCHID7 (0x1u << 23) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 7 Interrupt Disable */
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
+#define PWM_IMR1_CHID4 (0x1u << 4) /**< \brief (PWM_IMR1) Counter Event on Channel 4 Interrupt Mask */
+#define PWM_IMR1_CHID5 (0x1u << 5) /**< \brief (PWM_IMR1) Counter Event on Channel 5 Interrupt Mask */
+#define PWM_IMR1_CHID6 (0x1u << 6) /**< \brief (PWM_IMR1) Counter Event on Channel 6 Interrupt Mask */
+#define PWM_IMR1_CHID7 (0x1u << 7) /**< \brief (PWM_IMR1) Counter Event on Channel 7 Interrupt Mask */
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
+#define PWM_IMR1_FCHID4 (0x1u << 20) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 4 Interrupt Mask */
+#define PWM_IMR1_FCHID5 (0x1u << 21) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 5 Interrupt Mask */
+#define PWM_IMR1_FCHID6 (0x1u << 22) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 6 Interrupt Mask */
+#define PWM_IMR1_FCHID7 (0x1u << 23) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 7 Interrupt Mask */
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
+#define PWM_ISR1_CHID4 (0x1u << 4) /**< \brief (PWM_ISR1) Counter Event on Channel 4 */
+#define PWM_ISR1_CHID5 (0x1u << 5) /**< \brief (PWM_ISR1) Counter Event on Channel 5 */
+#define PWM_ISR1_CHID6 (0x1u << 6) /**< \brief (PWM_ISR1) Counter Event on Channel 6 */
+#define PWM_ISR1_CHID7 (0x1u << 7) /**< \brief (PWM_ISR1) Counter Event on Channel 7 */
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
+#define PWM_ISR1_FCHID4 (0x1u << 20) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 4 */
+#define PWM_ISR1_FCHID5 (0x1u << 21) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 5 */
+#define PWM_ISR1_FCHID6 (0x1u << 22) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 6 */
+#define PWM_ISR1_FCHID7 (0x1u << 23) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 7 */
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
+#define PWM_SCM_SYNC4 (0x1u << 4) /**< \brief (PWM_SCM) Synchronous Channel 4 */
+#define PWM_SCM_SYNC5 (0x1u << 5) /**< \brief (PWM_SCM) Synchronous Channel 5 */
+#define PWM_SCM_SYNC6 (0x1u << 6) /**< \brief (PWM_SCM) Synchronous Channel 6 */
+#define PWM_SCM_SYNC7 (0x1u << 7) /**< \brief (PWM_SCM) Synchronous Channel 7 */
+#define PWM_SCM_UPDM_Pos 16
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
+#define   PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
+#define PWM_SCM_PTRCS_Pos 21
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
+#define PWM_SCUP_UPR_Pos 0
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
+#define PWM_SCUP_UPRCNT_Pos 4
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
+#define PWM_SCUPUPD_UPRUPD_Pos 0
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
+#define PWM_OOV_OOVH4 (0x1u << 4) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 4 */
+#define PWM_OOV_OOVH5 (0x1u << 5) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 5 */
+#define PWM_OOV_OOVH6 (0x1u << 6) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 6 */
+#define PWM_OOV_OOVH7 (0x1u << 7) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 7 */
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
+#define PWM_OOV_OOVL4 (0x1u << 20) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 4 */
+#define PWM_OOV_OOVL5 (0x1u << 21) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 5 */
+#define PWM_OOV_OOVL6 (0x1u << 22) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 6 */
+#define PWM_OOV_OOVL7 (0x1u << 23) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 7 */
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
+#define PWM_OS_OSH4 (0x1u << 4) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 4 */
+#define PWM_OS_OSH5 (0x1u << 5) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 5 */
+#define PWM_OS_OSH6 (0x1u << 6) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 6 */
+#define PWM_OS_OSH7 (0x1u << 7) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 7 */
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
+#define PWM_OS_OSL4 (0x1u << 20) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 4 */
+#define PWM_OS_OSL5 (0x1u << 21) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 5 */
+#define PWM_OS_OSL6 (0x1u << 22) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 6 */
+#define PWM_OS_OSL7 (0x1u << 23) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 7 */
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSS_OSSH4 (0x1u << 4) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 4 */
+#define PWM_OSS_OSSH5 (0x1u << 5) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 5 */
+#define PWM_OSS_OSSH6 (0x1u << 6) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 6 */
+#define PWM_OSS_OSSH7 (0x1u << 7) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 7 */
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
+#define PWM_OSS_OSSL4 (0x1u << 20) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 4 */
+#define PWM_OSS_OSSL5 (0x1u << 21) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 5 */
+#define PWM_OSS_OSSL6 (0x1u << 22) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 6 */
+#define PWM_OSS_OSSL7 (0x1u << 23) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 7 */
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSC_OSCH4 (0x1u << 4) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 4 */
+#define PWM_OSC_OSCH5 (0x1u << 5) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 5 */
+#define PWM_OSC_OSCH6 (0x1u << 6) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 6 */
+#define PWM_OSC_OSCH7 (0x1u << 7) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 7 */
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
+#define PWM_OSC_OSCL4 (0x1u << 20) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 4 */
+#define PWM_OSC_OSCL5 (0x1u << 21) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 5 */
+#define PWM_OSC_OSCL6 (0x1u << 22) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 6 */
+#define PWM_OSC_OSCL7 (0x1u << 23) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 7 */
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSSUPD_OSSUPH4 (0x1u << 4) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 4 */
+#define PWM_OSSUPD_OSSUPH5 (0x1u << 5) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 5 */
+#define PWM_OSSUPD_OSSUPH6 (0x1u << 6) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 6 */
+#define PWM_OSSUPD_OSSUPH7 (0x1u << 7) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 7 */
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
+#define PWM_OSSUPD_OSSUPL4 (0x1u << 20) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 4 */
+#define PWM_OSSUPD_OSSUPL5 (0x1u << 21) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 5 */
+#define PWM_OSSUPD_OSSUPL6 (0x1u << 22) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 6 */
+#define PWM_OSSUPD_OSSUPL7 (0x1u << 23) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 7 */
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSCUPD_OSCUPH4 (0x1u << 4) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 4 */
+#define PWM_OSCUPD_OSCUPH5 (0x1u << 5) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 5 */
+#define PWM_OSCUPD_OSCUPH6 (0x1u << 6) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 6 */
+#define PWM_OSCUPD_OSCUPH7 (0x1u << 7) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 7 */
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
+#define PWM_OSCUPD_OSCUPL4 (0x1u << 20) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 4 */
+#define PWM_OSCUPD_OSCUPL5 (0x1u << 21) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 5 */
+#define PWM_OSCUPD_OSCUPDL6 (0x1u << 22) /**< \brief (PWM_OSCUPD)  */
+#define PWM_OSCUPD_OSCUPL7 (0x1u << 23) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 7 */
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
+#define PWM_FMR_FPOL_Pos 0
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
+#define PWM_FMR_FMOD_Pos 8
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
+#define PWM_FMR_FFIL_Pos 16
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
+#define PWM_FSR_FIV_Pos 0
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */
+#define PWM_FSR_FS_Pos 8
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
+#define PWM_FCR_FCLR_Pos 0
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
+#define PWM_FPV_FPVH4 (0x1u << 4) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 4 */
+#define PWM_FPV_FPVH5 (0x1u << 5) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 5 */
+#define PWM_FPV_FPVH6 (0x1u << 6) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 6 */
+#define PWM_FPV_FPVH7 (0x1u << 7) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 7 */
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
+#define PWM_FPV_FPVL4 (0x1u << 20) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 4 */
+#define PWM_FPV_FPVL5 (0x1u << 21) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 5 */
+#define PWM_FPV_FPVL6 (0x1u << 22) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 6 */
+#define PWM_FPV_FPVL7 (0x1u << 23) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 7 */
+/* -------- PWM_FPE1 : (PWM Offset: 0x6C) PWM Fault Protection Enable Register 1 -------- */
+#define PWM_FPE1_FPE0_Pos 0
+#define PWM_FPE1_FPE0_Msk (0xffu << PWM_FPE1_FPE0_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE0(value) ((PWM_FPE1_FPE0_Msk & ((value) << PWM_FPE1_FPE0_Pos)))
+#define PWM_FPE1_FPE1_Pos 8
+#define PWM_FPE1_FPE1_Msk (0xffu << PWM_FPE1_FPE1_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE1(value) ((PWM_FPE1_FPE1_Msk & ((value) << PWM_FPE1_FPE1_Pos)))
+#define PWM_FPE1_FPE2_Pos 16
+#define PWM_FPE1_FPE2_Msk (0xffu << PWM_FPE1_FPE2_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE2(value) ((PWM_FPE1_FPE2_Msk & ((value) << PWM_FPE1_FPE2_Pos)))
+#define PWM_FPE1_FPE3_Pos 24
+#define PWM_FPE1_FPE3_Msk (0xffu << PWM_FPE1_FPE3_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */
+#define PWM_FPE1_FPE3(value) ((PWM_FPE1_FPE3_Msk & ((value) << PWM_FPE1_FPE3_Pos)))
+/* -------- PWM_FPE2 : (PWM Offset: 0x70) PWM Fault Protection Enable Register 2 -------- */
+#define PWM_FPE2_FPE4_Pos 0
+#define PWM_FPE2_FPE4_Msk (0xffu << PWM_FPE2_FPE4_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 4 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE4(value) ((PWM_FPE2_FPE4_Msk & ((value) << PWM_FPE2_FPE4_Pos)))
+#define PWM_FPE2_FPE5_Pos 8
+#define PWM_FPE2_FPE5_Msk (0xffu << PWM_FPE2_FPE5_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 5 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE5(value) ((PWM_FPE2_FPE5_Msk & ((value) << PWM_FPE2_FPE5_Pos)))
+#define PWM_FPE2_FPE6_Pos 16
+#define PWM_FPE2_FPE6_Msk (0xffu << PWM_FPE2_FPE6_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 6 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE6(value) ((PWM_FPE2_FPE6_Msk & ((value) << PWM_FPE2_FPE6_Pos)))
+#define PWM_FPE2_FPE7_Pos 24
+#define PWM_FPE2_FPE7_Msk (0xffu << PWM_FPE2_FPE7_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 7 (fault input bit varies from 0 to 5) */
+#define PWM_FPE2_FPE7(value) ((PWM_FPE2_FPE7_Msk & ((value) << PWM_FPE2_FPE7_Pos)))
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN2 (0x1u << 2) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN3 (0x1u << 3) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN2 (0x1u << 18) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN3 (0x1u << 19) /**< \brief (PWM_SMMR) DOWN Count */
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
+#define PWM_WPCR_WPCMD_Pos 0
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
+#define PWM_WPCR_WPKEY_Pos 8
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPVSRC_Pos 16
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
+#define PWM_TPR_TXPTR_Pos 0
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
+#define PWM_TCR_TXCTR_Pos 0
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
+#define PWM_TNPR_TXNPTR_Pos 0
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
+#define PWM_TNCR_TXNCTR_Pos 0
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
+#define PWM_CMPV_CV_Pos 0
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
+#define PWM_CMPVUPD_CVUPD_Pos 0
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
+#define PWM_CMPM_CTR_Pos 4
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
+#define PWM_CMPM_CPR_Pos 8
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
+#define PWM_CMPM_CPRCNT_Pos 12
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
+#define PWM_CMPM_CUPR_Pos 16
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
+#define PWM_CMPM_CUPRCNT_Pos 20
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
+#define PWM_CMPMUPD_CTRUPD_Pos 4
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
+#define PWM_CMPMUPD_CPRUPD_Pos 8
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
+#define PWM_CMPMUPD_CUPRUPD_Pos 16
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
+#define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
+#define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
+#define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
+#define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
+#define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
+#define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
+#define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
+#define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
+#define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
+#define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
+#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
+#define PWM_CDTYUPD_CDTYUPD_Pos 0
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
+#define PWM_CPRDUPD_CPRDUPD_Pos 0
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
+#define PWM_DT_DTH_Pos 0
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
+#define PWM_DT_DTL_Pos 16
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
+#define PWM_DTUPD_DTHUPD_Pos 0
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
+#define PWM_DTUPD_DTLUPD_Pos 16
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_PWM_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_rstc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_rstc.h
new file mode 100644
index 0000000..c22778a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_rstc.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RSTC_COMPONENT_
+#define _SAM3XA_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_RSTC Reset Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rstc hardware registers */
+typedef struct {
+  WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+  RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+  RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_RSTC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_rtc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_rtc.h
new file mode 100644
index 0000000..2fc6fc8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_rtc.h
@@ -0,0 +1,168 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RTC_COMPONENT_
+#define _SAM3XA_RTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_RTC Real-time Clock */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtc hardware registers */
+typedef struct {
+  RwReg RTC_CR;        /**< \brief (Rtc Offset: 0x00) Control Register */
+  RwReg RTC_MR;        /**< \brief (Rtc Offset: 0x04) Mode Register */
+  RwReg RTC_TIMR;      /**< \brief (Rtc Offset: 0x08) Time Register */
+  RwReg RTC_CALR;      /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+  RwReg RTC_TIMALR;    /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+  RwReg RTC_CALALR;    /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+  RoReg RTC_SR;        /**< \brief (Rtc Offset: 0x18) Status Register */
+  WoReg RTC_SCCR;      /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+  WoReg RTC_IER;       /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+  WoReg RTC_IDR;       /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+  RoReg RTC_IMR;       /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+  RoReg RTC_VER;       /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+  RoReg Reserved1[45];
+  RwReg RTC_WPMR;      /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
+#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */
+#define RTC_WPMR_WPKEY_Pos 8
+#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR)  */
+#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_RTC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_rtt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_rtt.h
new file mode 100644
index 0000000..6f30e21
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_rtt.h
@@ -0,0 +1,69 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RTT_COMPONENT_
+#define _SAM3XA_RTT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_RTT Real-time Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtt hardware registers */
+typedef struct {
+  RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+  RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+  RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+  RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_RTT_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_sdramc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_sdramc.h
new file mode 100644
index 0000000..77965dd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_sdramc.h
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SDRAMC_COMPONENT_
+#define _SAM3XA_SDRAMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR SDRAM Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SDRAMC SDRAM Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Sdramc hardware registers */
+typedef struct {
+  RwReg SDRAMC_MR;    /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */
+  RwReg SDRAMC_TR;    /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */
+  RwReg SDRAMC_CR;    /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */
+  RoReg Reserved1[1];
+  RwReg SDRAMC_LPR;   /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */
+  WoReg SDRAMC_IER;   /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */
+  WoReg SDRAMC_IDR;   /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */
+  RoReg SDRAMC_IMR;   /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */
+  RoReg SDRAMC_ISR;   /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */
+  RwReg SDRAMC_MDR;   /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */
+  RwReg SDRAMC_CR1;   /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */
+  RwReg SDRAMC_OCMS;  /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register 1 */
+} Sdramc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */
+#define SDRAMC_MR_MODE_Pos 0
+#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */
+#define   SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */
+#define   SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */
+#define   SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */
+/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */
+#define SDRAMC_TR_COUNT_Pos 0
+#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */
+#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)))
+/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */
+#define SDRAMC_CR_NC_Pos 0
+#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */
+#define   SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */
+#define   SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */
+#define   SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */
+#define   SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */
+#define SDRAMC_CR_NR_Pos 2
+#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */
+#define   SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */
+#define   SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */
+#define   SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */
+#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */
+#define   SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */
+#define   SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */
+#define SDRAMC_CR_CAS_Pos 5
+#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */
+#define   SDRAMC_CR_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */
+#define   SDRAMC_CR_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */
+#define   SDRAMC_CR_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */
+#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */
+#define SDRAMC_CR_TWR_Pos 8
+#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */
+#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)))
+#define SDRAMC_CR_TRC_TRFC_Pos 12
+#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */
+#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)))
+#define SDRAMC_CR_TRP_Pos 16
+#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */
+#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)))
+#define SDRAMC_CR_TRCD_Pos 20
+#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */
+#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)))
+#define SDRAMC_CR_TRAS_Pos 24
+#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */
+#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)))
+#define SDRAMC_CR_TXSR_Pos 28
+#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */
+#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)))
+/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */
+#define SDRAMC_LPR_LPCB_Pos 0
+#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */
+#define   SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */
+#define   SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */
+#define   SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */
+#define   SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */
+#define SDRAMC_LPR_PASR_Pos 4
+#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */
+#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)))
+#define SDRAMC_LPR_TCSR_Pos 8
+#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */
+#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)))
+#define SDRAMC_LPR_DS_Pos 10
+#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */
+#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)))
+#define SDRAMC_LPR_TIMEOUT_Pos 12
+#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to define when low-power mode is enable */
+#define   SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. */
+#define   SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */
+#define   SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */
+/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */
+#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */
+/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */
+#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */
+/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */
+#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */
+/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */
+#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status */
+/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */
+#define SDRAMC_MDR_MD_Pos 0
+#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */
+#define   SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */
+#define   SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */
+/* -------- SDRAMC_CR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */
+#define SDRAMC_CR1_NC_Pos 0
+#define SDRAMC_CR1_NC_Msk (0x3u << SDRAMC_CR1_NC_Pos) /**< \brief (SDRAMC_CR1) Number of Column Bits */
+#define   SDRAMC_CR1_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR1) 8 column bits */
+#define   SDRAMC_CR1_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR1) 9 column bits */
+#define   SDRAMC_CR1_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR1) 10 column bits */
+#define   SDRAMC_CR1_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR1) 11 column bits */
+#define SDRAMC_CR1_NR_Pos 2
+#define SDRAMC_CR1_NR_Msk (0x3u << SDRAMC_CR1_NR_Pos) /**< \brief (SDRAMC_CR1) Number of Row Bits */
+#define   SDRAMC_CR1_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR1) 11 row bits */
+#define   SDRAMC_CR1_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR1) 12 row bits */
+#define   SDRAMC_CR1_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR1) 13 row bits */
+#define SDRAMC_CR1_NB (0x1u << 4) /**< \brief (SDRAMC_CR1) Number of Banks */
+#define   SDRAMC_CR1_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR1) 2 banks */
+#define   SDRAMC_CR1_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR1) 4 banks */
+#define SDRAMC_CR1_CAS_Pos 5
+#define SDRAMC_CR1_CAS_Msk (0x3u << SDRAMC_CR1_CAS_Pos) /**< \brief (SDRAMC_CR1) CAS Latency */
+#define   SDRAMC_CR1_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR1) 1 cycle CAS latency */
+#define   SDRAMC_CR1_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR1) 2 cycle CAS latency */
+#define   SDRAMC_CR1_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR1) 3 cycle CAS latency */
+#define SDRAMC_CR1_DBW (0x1u << 7) /**< \brief (SDRAMC_CR1) Data Bus Width */
+#define SDRAMC_CR1_TWR_Pos 8
+#define SDRAMC_CR1_TWR_Msk (0xfu << SDRAMC_CR1_TWR_Pos) /**< \brief (SDRAMC_CR1) Write Recovery Delay */
+#define SDRAMC_CR1_TWR(value) ((SDRAMC_CR1_TWR_Msk & ((value) << SDRAMC_CR1_TWR_Pos)))
+#define SDRAMC_CR1_TRC_TRFC_Pos 12
+#define SDRAMC_CR1_TRC_TRFC_Msk (0xfu << SDRAMC_CR1_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR1) Row Cycle Delay and Row Refresh Cycle */
+#define SDRAMC_CR1_TRC_TRFC(value) ((SDRAMC_CR1_TRC_TRFC_Msk & ((value) << SDRAMC_CR1_TRC_TRFC_Pos)))
+#define SDRAMC_CR1_TRP_Pos 16
+#define SDRAMC_CR1_TRP_Msk (0xfu << SDRAMC_CR1_TRP_Pos) /**< \brief (SDRAMC_CR1) Row Precharge Delay */
+#define SDRAMC_CR1_TRP(value) ((SDRAMC_CR1_TRP_Msk & ((value) << SDRAMC_CR1_TRP_Pos)))
+#define SDRAMC_CR1_TRCD_Pos 20
+#define SDRAMC_CR1_TRCD_Msk (0xfu << SDRAMC_CR1_TRCD_Pos) /**< \brief (SDRAMC_CR1) Row to Column Delay */
+#define SDRAMC_CR1_TRCD(value) ((SDRAMC_CR1_TRCD_Msk & ((value) << SDRAMC_CR1_TRCD_Pos)))
+#define SDRAMC_CR1_TRAS_Pos 24
+#define SDRAMC_CR1_TRAS_Msk (0xfu << SDRAMC_CR1_TRAS_Pos) /**< \brief (SDRAMC_CR1) Active to Precharge Delay */
+#define SDRAMC_CR1_TRAS(value) ((SDRAMC_CR1_TRAS_Msk & ((value) << SDRAMC_CR1_TRAS_Pos)))
+#define SDRAMC_CR1_TXSR_Pos 28
+#define SDRAMC_CR1_TXSR_Msk (0xfu << SDRAMC_CR1_TXSR_Pos) /**< \brief (SDRAMC_CR1) Exit Self Refresh to Active Delay */
+#define SDRAMC_CR1_TXSR(value) ((SDRAMC_CR1_TXSR_Msk & ((value) << SDRAMC_CR1_TXSR_Pos)))
+/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register 1 -------- */
+#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SDRAMC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_smc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_smc.h
new file mode 100644
index 0000000..314c44f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_smc.h
@@ -0,0 +1,484 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SMC_COMPONENT_
+#define _SAM3XA_SMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Static Memory Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SMC Static Memory Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief SmcCs_number hardware registers */
+typedef struct {
+  RwReg         SMC_SETUP;        /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
+  RwReg         SMC_PULSE;        /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
+  RwReg         SMC_CYCLE;        /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
+  RwReg         SMC_TIMINGS;      /**< \brief (SmcCs_number Offset: 0xC) SMC Timings Register */
+  RwReg         SMC_MODE;         /**< \brief (SmcCs_number Offset: 0x10) SMC Mode Register */
+} SmcCs_number;
+/** \brief Smc hardware registers */
+#define SMCCS_NUMBER_NUMBER 8
+typedef struct {
+  RwReg         SMC_CFG;          /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */
+  WoReg         SMC_CTRL;         /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */
+  RoReg         SMC_SR;           /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */
+  WoReg         SMC_IER;          /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */
+  WoReg         SMC_IDR;          /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */
+  RoReg         SMC_IMR;          /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */
+  RwReg         SMC_ADDR;         /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */
+  RwReg         SMC_BANK;         /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */
+  WoReg         SMC_ECC_CTRL;     /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */
+  RwReg         SMC_ECC_MD;       /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */
+  RoReg         SMC_ECC_SR1;      /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */
+  RoReg         SMC_ECC_PR0;      /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */
+  RoReg         SMC_ECC_PR1;      /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */
+  RoReg         SMC_ECC_SR2;      /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */
+  RoReg         SMC_ECC_PR2;      /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */
+  RoReg         SMC_ECC_PR3;      /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */
+  RoReg         SMC_ECC_PR4;      /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */
+  RoReg         SMC_ECC_PR5;      /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */
+  RoReg         SMC_ECC_PR6;      /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */
+  RoReg         SMC_ECC_PR7;      /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */
+  RoReg         SMC_ECC_PR8;      /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */
+  RoReg         SMC_ECC_PR9;      /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */
+  RoReg         SMC_ECC_PR10;     /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */
+  RoReg         SMC_ECC_PR11;     /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */
+  RoReg         SMC_ECC_PR12;     /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */
+  RoReg         SMC_ECC_PR13;     /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */
+  RoReg         SMC_ECC_PR14;     /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */
+  RoReg         SMC_ECC_PR15;     /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */
+  SmcCs_number  SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 7 */
+  RwReg         SMC_OCMS;         /**< \brief (Smc Offset: 0x110) SMC OCMS Register */
+  WoReg         SMC_KEY1;         /**< \brief (Smc Offset: 0x114) SMC OCMS KEY1 Register */
+  WoReg         SMC_KEY2;         /**< \brief (Smc Offset: 0x118) SMC OCMS KEY2 Register */
+  RoReg         Reserved1[50];
+  WoReg         SMC_WPCR;         /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */
+  RoReg         SMC_WPSR;         /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */
+} Smc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */
+#define SMC_CFG_PAGESIZE_Pos 0
+#define SMC_CFG_PAGESIZE_Msk (0x3u << SMC_CFG_PAGESIZE_Pos) /**< \brief (SMC_CFG)  */
+#define   SMC_CFG_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_CFG) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define   SMC_CFG_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_CFG) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define   SMC_CFG_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_CFG) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define   SMC_CFG_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_CFG) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_CFG_WSPARE (0x1u << 8) /**< \brief (SMC_CFG) Write Spare Area */
+#define SMC_CFG_RSPARE (0x1u << 9) /**< \brief (SMC_CFG) Read Spare Area */
+#define SMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */
+#define SMC_CFG_RBEDGE (0x1u << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */
+#define SMC_CFG_DTOCYC_Pos 16
+#define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) /**< \brief (SMC_CFG) Data Timeout Cycle Number */
+#define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos)))
+#define SMC_CFG_DTOMUL_Pos 20
+#define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) /**< \brief (SMC_CFG) Data Timeout Multiplier */
+#define   SMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (SMC_CFG) DTOCYC */
+#define   SMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (SMC_CFG) DTOCYC x 16 */
+#define   SMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (SMC_CFG) DTOCYC x 128 */
+#define   SMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (SMC_CFG) DTOCYC x 256 */
+#define   SMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (SMC_CFG) DTOCYC x 1024 */
+#define   SMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (SMC_CFG) DTOCYC x 4096 */
+#define   SMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (SMC_CFG) DTOCYC x 65536 */
+#define   SMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (SMC_CFG) DTOCYC x 1048576 */
+/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */
+#define SMC_CTRL_NFCEN (0x1u << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */
+#define SMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */
+/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */
+#define SMC_SR_SMCSTS (0x1u << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */
+#define SMC_SR_RB_RISE (0x1u << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */
+#define SMC_SR_RB_FALL (0x1u << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */
+#define SMC_SR_NFCBUSY (0x1u << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */
+#define SMC_SR_NFCWR (0x1u << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */
+#define SMC_SR_NFCSID_Pos 12
+#define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */
+#define SMC_SR_XFRDONE (0x1u << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */
+#define SMC_SR_CMDDONE (0x1u << 17) /**< \brief (SMC_SR) Command Done */
+#define SMC_SR_DTOE (0x1u << 20) /**< \brief (SMC_SR) Data Timeout Error */
+#define SMC_SR_UNDEF (0x1u << 21) /**< \brief (SMC_SR) Undefined Area Error */
+#define SMC_SR_AWB (0x1u << 22) /**< \brief (SMC_SR) Accessing While Busy */
+#define SMC_SR_NFCASE (0x1u << 23) /**< \brief (SMC_SR) NFC Access Size Error */
+#define SMC_SR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */
+/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */
+#define SMC_IER_RB_RISE (0x1u << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */
+#define SMC_IER_RB_FALL (0x1u << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */
+#define SMC_IER_XFRDONE (0x1u << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */
+#define SMC_IER_CMDDONE (0x1u << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */
+#define SMC_IER_DTOE (0x1u << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */
+#define SMC_IER_UNDEF (0x1u << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */
+#define SMC_IER_AWB (0x1u << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */
+#define SMC_IER_NFCASE (0x1u << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */
+#define SMC_IER_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */
+/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */
+#define SMC_IDR_RB_RISE (0x1u << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */
+#define SMC_IDR_RB_FALL (0x1u << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */
+#define SMC_IDR_XFRDONE (0x1u << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */
+#define SMC_IDR_CMDDONE (0x1u << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */
+#define SMC_IDR_DTOE (0x1u << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */
+#define SMC_IDR_UNDEF (0x1u << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */
+#define SMC_IDR_AWB (0x1u << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */
+#define SMC_IDR_NFCASE (0x1u << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */
+#define SMC_IDR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */
+/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */
+#define SMC_IMR_RB_RISE (0x1u << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */
+#define SMC_IMR_RB_FALL (0x1u << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */
+#define SMC_IMR_XFRDONE (0x1u << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */
+#define SMC_IMR_CMDDONE (0x1u << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */
+#define SMC_IMR_DTOE (0x1u << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */
+#define SMC_IMR_UNDEF (0x1u << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */
+#define SMC_IMR_AWB (0x1u << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */
+#define SMC_IMR_NFCASE (0x1u << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */
+#define SMC_IMR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */
+/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */
+#define SMC_ADDR_ADDR_CYCLE0_Pos 0
+#define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */
+#define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos)))
+/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */
+#define SMC_BANK_BANK_Pos 0
+#define SMC_BANK_BANK_Msk (0x7u << SMC_BANK_BANK_Pos) /**< \brief (SMC_BANK) Bank Identifier */
+#define SMC_BANK_BANK(value) ((SMC_BANK_BANK_Msk & ((value) << SMC_BANK_BANK_Pos)))
+/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */
+#define SMC_ECC_CTRL_RST (0x1u << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */
+#define SMC_ECC_CTRL_SWRST (0x1u << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */
+/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */
+#define SMC_ECC_MD_ECC_PAGESIZE_Pos 0
+#define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) /**< \brief (SMC_ECC_MD) ECC Page Size */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_ECC_MD) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_ECC_MD) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_ECC_MD) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
+#define   SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_ECC_MD) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
+#define SMC_ECC_MD_TYPCORREC_Pos 4
+#define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) /**< \brief (SMC_ECC_MD) Type of Correction */
+#define   SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for a page of 512/1024/2048/4096 Bytes  (for 8 or 16-bit NAND Flash) */
+#define   SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+#define   SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
+/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */
+#define SMC_ECC_SR1_RECERR0 (0x1u << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */
+#define SMC_ECC_SR1_ECCERR0_Pos 1
+#define SMC_ECC_SR1_ECCERR0_Msk (0x3u << SMC_ECC_SR1_ECCERR0_Pos) /**< \brief (SMC_ECC_SR1) ECC Error */
+#define SMC_ECC_SR1_RECERR1 (0x1u << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_ECCERR1 (0x1u << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_MULERR1 (0x1u << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
+#define SMC_ECC_SR1_RECERR2 (0x1u << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_ECCERR2 (0x1u << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_MULERR2 (0x1u << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
+#define SMC_ECC_SR1_RECERR3 (0x1u << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_ECCERR3 (0x1u << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_MULERR3 (0x1u << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
+#define SMC_ECC_SR1_RECERR4 (0x1u << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_ECCERR4_Pos 17
+#define SMC_ECC_SR1_ECCERR4_Msk (0x3u << SMC_ECC_SR1_ECCERR4_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
+#define SMC_ECC_SR1_RECERR5 (0x1u << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_ECCERR5_Pos 21
+#define SMC_ECC_SR1_ECCERR5_Msk (0x3u << SMC_ECC_SR1_ECCERR5_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
+#define SMC_ECC_SR1_RECERR6 (0x1u << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_ECCERR6_Pos 25
+#define SMC_ECC_SR1_ECCERR6_Msk (0x3u << SMC_ECC_SR1_ECCERR6_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
+#define SMC_ECC_SR1_RECERR7 (0x1u << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+#define SMC_ECC_SR1_ECCERR7_Pos 29
+#define SMC_ECC_SR1_ECCERR7_Msk (0x3u << SMC_ECC_SR1_ECCERR7_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
+/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */
+#define SMC_ECC_PR0_BITADDR_Pos 0
+#define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) /**< \brief (SMC_ECC_PR0) Bit Address */
+#define SMC_ECC_PR0_WORDADDR_Pos 4
+#define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) /**< \brief (SMC_ECC_PR0) Word Address */
+#define SMC_ECC_PR0_BITADDR_W9BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W9BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W9BIT_Msk (0x1ffu << SMC_ECC_PR0_WORDADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_Pos 12
+#define SMC_ECC_PR0_NPARITY_Msk (0xfffu << SMC_ECC_PR0_NPARITY_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+#define SMC_ECC_PR0_BITADDR_W8BIT_Pos 0
+#define SMC_ECC_PR0_BITADDR_W8BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR0_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR0_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR0_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR0_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR0_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
+/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */
+#define SMC_ECC_PR1_NPARITY_Pos 0
+#define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_BITADDR_Pos 0
+#define SMC_ECC_PR1_BITADDR_Msk (0x7u << SMC_ECC_PR1_BITADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_WORDADDR_Pos 3
+#define SMC_ECC_PR1_WORDADDR_Msk (0x1ffu << SMC_ECC_PR1_WORDADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W9BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W9BIT_Msk (0xfffu << SMC_ECC_PR1_NPARITY_W9BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR1_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR1_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR1_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR1_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR1_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
+/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */
+#define SMC_ECC_SR2_RECERR8 (0x1u << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_ECCERR8_Pos 1
+#define SMC_ECC_SR2_ECCERR8_Msk (0x3u << SMC_ECC_SR2_ECCERR8_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */
+#define SMC_ECC_SR2_RECERR9 (0x1u << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_ECCERR9 (0x1u << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_MULERR9 (0x1u << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */
+#define SMC_ECC_SR2_RECERR10 (0x1u << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_ECCERR10 (0x1u << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_MULERR10 (0x1u << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */
+#define SMC_ECC_SR2_RECERR11 (0x1u << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_ECCERR11 (0x1u << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_MULERR11 (0x1u << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */
+#define SMC_ECC_SR2_RECERR12 (0x1u << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_ECCERR12_Pos 17
+#define SMC_ECC_SR2_ECCERR12_Msk (0x3u << SMC_ECC_SR2_ECCERR12_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */
+#define SMC_ECC_SR2_RECERR13 (0x1u << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_ECCERR13_Pos 21
+#define SMC_ECC_SR2_ECCERR13_Msk (0x3u << SMC_ECC_SR2_ECCERR13_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */
+#define SMC_ECC_SR2_RECERR14 (0x1u << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_ECCERR14_Pos 25
+#define SMC_ECC_SR2_ECCERR14_Msk (0x3u << SMC_ECC_SR2_ECCERR14_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */
+#define SMC_ECC_SR2_RECERR15 (0x1u << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */
+#define SMC_ECC_SR2_ECCERR15_Pos 29
+#define SMC_ECC_SR2_ECCERR15_Msk (0x3u << SMC_ECC_SR2_ECCERR15_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */
+/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */
+#define SMC_ECC_PR2_BITADDR_Pos 0
+#define SMC_ECC_PR2_BITADDR_Msk (0x7u << SMC_ECC_PR2_BITADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_WORDADDR_Pos 3
+#define SMC_ECC_PR2_WORDADDR_Msk (0x1ffu << SMC_ECC_PR2_WORDADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_Pos 12
+#define SMC_ECC_PR2_NPARITY_Msk (0xfffu << SMC_ECC_PR2_NPARITY_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR2_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR2_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR2_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR2_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR2_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
+/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */
+#define SMC_ECC_PR3_BITADDR_Pos 0
+#define SMC_ECC_PR3_BITADDR_Msk (0x7u << SMC_ECC_PR3_BITADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_WORDADDR_Pos 3
+#define SMC_ECC_PR3_WORDADDR_Msk (0x1ffu << SMC_ECC_PR3_WORDADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_Pos 12
+#define SMC_ECC_PR3_NPARITY_Msk (0xfffu << SMC_ECC_PR3_NPARITY_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR3_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR3_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR3_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR3_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR3_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
+/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */
+#define SMC_ECC_PR4_BITADDR_Pos 0
+#define SMC_ECC_PR4_BITADDR_Msk (0x7u << SMC_ECC_PR4_BITADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_WORDADDR_Pos 3
+#define SMC_ECC_PR4_WORDADDR_Msk (0x1ffu << SMC_ECC_PR4_WORDADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_Pos 12
+#define SMC_ECC_PR4_NPARITY_Msk (0xfffu << SMC_ECC_PR4_NPARITY_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR4_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR4_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR4_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR4_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR4_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
+/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */
+#define SMC_ECC_PR5_BITADDR_Pos 0
+#define SMC_ECC_PR5_BITADDR_Msk (0x7u << SMC_ECC_PR5_BITADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_WORDADDR_Pos 3
+#define SMC_ECC_PR5_WORDADDR_Msk (0x1ffu << SMC_ECC_PR5_WORDADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_Pos 12
+#define SMC_ECC_PR5_NPARITY_Msk (0xfffu << SMC_ECC_PR5_NPARITY_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR5_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR5_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR5_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR5_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR5_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
+/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */
+#define SMC_ECC_PR6_BITADDR_Pos 0
+#define SMC_ECC_PR6_BITADDR_Msk (0x7u << SMC_ECC_PR6_BITADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_WORDADDR_Pos 3
+#define SMC_ECC_PR6_WORDADDR_Msk (0x1ffu << SMC_ECC_PR6_WORDADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_Pos 12
+#define SMC_ECC_PR6_NPARITY_Msk (0xfffu << SMC_ECC_PR6_NPARITY_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR6_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR6_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR6_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR6_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR6_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
+/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */
+#define SMC_ECC_PR7_BITADDR_Pos 0
+#define SMC_ECC_PR7_BITADDR_Msk (0x7u << SMC_ECC_PR7_BITADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_WORDADDR_Pos 3
+#define SMC_ECC_PR7_WORDADDR_Msk (0x1ffu << SMC_ECC_PR7_WORDADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_Pos 12
+#define SMC_ECC_PR7_NPARITY_Msk (0xfffu << SMC_ECC_PR7_NPARITY_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Pos 3
+#define SMC_ECC_PR7_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR7_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR7_NPARITY_W8BIT_Pos 12
+#define SMC_ECC_PR7_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR7_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
+/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */
+#define SMC_ECC_PR8_BITADDR_Pos 0
+#define SMC_ECC_PR8_BITADDR_Msk (0x7u << SMC_ECC_PR8_BITADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_WORDADDR_Pos 3
+#define SMC_ECC_PR8_WORDADDR_Msk (0xffu << SMC_ECC_PR8_WORDADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR8_NPARITY_Pos 12
+#define SMC_ECC_PR8_NPARITY_Msk (0x7ffu << SMC_ECC_PR8_NPARITY_Pos) /**< \brief (SMC_ECC_PR8) Parity N */
+/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */
+#define SMC_ECC_PR9_BITADDR_Pos 0
+#define SMC_ECC_PR9_BITADDR_Msk (0x7u << SMC_ECC_PR9_BITADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_WORDADDR_Pos 3
+#define SMC_ECC_PR9_WORDADDR_Msk (0xffu << SMC_ECC_PR9_WORDADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR9_NPARITY_Pos 12
+#define SMC_ECC_PR9_NPARITY_Msk (0x7ffu << SMC_ECC_PR9_NPARITY_Pos) /**< \brief (SMC_ECC_PR9) Parity N */
+/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */
+#define SMC_ECC_PR10_BITADDR_Pos 0
+#define SMC_ECC_PR10_BITADDR_Msk (0x7u << SMC_ECC_PR10_BITADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_WORDADDR_Pos 3
+#define SMC_ECC_PR10_WORDADDR_Msk (0xffu << SMC_ECC_PR10_WORDADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR10_NPARITY_Pos 12
+#define SMC_ECC_PR10_NPARITY_Msk (0x7ffu << SMC_ECC_PR10_NPARITY_Pos) /**< \brief (SMC_ECC_PR10) Parity N */
+/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */
+#define SMC_ECC_PR11_BITADDR_Pos 0
+#define SMC_ECC_PR11_BITADDR_Msk (0x7u << SMC_ECC_PR11_BITADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_WORDADDR_Pos 3
+#define SMC_ECC_PR11_WORDADDR_Msk (0xffu << SMC_ECC_PR11_WORDADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR11_NPARITY_Pos 12
+#define SMC_ECC_PR11_NPARITY_Msk (0x7ffu << SMC_ECC_PR11_NPARITY_Pos) /**< \brief (SMC_ECC_PR11) Parity N */
+/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */
+#define SMC_ECC_PR12_BITADDR_Pos 0
+#define SMC_ECC_PR12_BITADDR_Msk (0x7u << SMC_ECC_PR12_BITADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_WORDADDR_Pos 3
+#define SMC_ECC_PR12_WORDADDR_Msk (0xffu << SMC_ECC_PR12_WORDADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR12_NPARITY_Pos 12
+#define SMC_ECC_PR12_NPARITY_Msk (0x7ffu << SMC_ECC_PR12_NPARITY_Pos) /**< \brief (SMC_ECC_PR12) Parity N */
+/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */
+#define SMC_ECC_PR13_BITADDR_Pos 0
+#define SMC_ECC_PR13_BITADDR_Msk (0x7u << SMC_ECC_PR13_BITADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_WORDADDR_Pos 3
+#define SMC_ECC_PR13_WORDADDR_Msk (0xffu << SMC_ECC_PR13_WORDADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR13_NPARITY_Pos 12
+#define SMC_ECC_PR13_NPARITY_Msk (0x7ffu << SMC_ECC_PR13_NPARITY_Pos) /**< \brief (SMC_ECC_PR13) Parity N */
+/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */
+#define SMC_ECC_PR14_BITADDR_Pos 0
+#define SMC_ECC_PR14_BITADDR_Msk (0x7u << SMC_ECC_PR14_BITADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_WORDADDR_Pos 3
+#define SMC_ECC_PR14_WORDADDR_Msk (0xffu << SMC_ECC_PR14_WORDADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR14_NPARITY_Pos 12
+#define SMC_ECC_PR14_NPARITY_Msk (0x7ffu << SMC_ECC_PR14_NPARITY_Pos) /**< \brief (SMC_ECC_PR14) Parity N */
+/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */
+#define SMC_ECC_PR15_BITADDR_Pos 0
+#define SMC_ECC_PR15_BITADDR_Msk (0x7u << SMC_ECC_PR15_BITADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_WORDADDR_Pos 3
+#define SMC_ECC_PR15_WORDADDR_Msk (0xffu << SMC_ECC_PR15_WORDADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
+#define SMC_ECC_PR15_NPARITY_Pos 12
+#define SMC_ECC_PR15_NPARITY_Msk (0x7ffu << SMC_ECC_PR15_NPARITY_Pos) /**< \brief (SMC_ECC_PR15) Parity N */
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
+#define SMC_SETUP_NWE_SETUP_Pos 0
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Write Access */
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
+#define SMC_SETUP_NRD_SETUP_Pos 16
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Read Access */
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
+#define SMC_PULSE_NWE_PULSE_Pos 0
+#define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
+#define SMC_PULSE_NRD_PULSE_Pos 16
+#define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
+#define SMC_CYCLE_NWE_CYCLE_Pos 0
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
+#define SMC_CYCLE_NRD_CYCLE_Pos 16
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
+/* -------- SMC_TIMINGS : (SMC Offset: N/A) SMC Timings Register -------- */
+#define SMC_TIMINGS_TCLR_Pos 0
+#define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) /**< \brief (SMC_TIMINGS) CLE to REN Low Delay */
+#define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos)))
+#define SMC_TIMINGS_TADL_Pos 4
+#define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) /**< \brief (SMC_TIMINGS) ALE to Data Start */
+#define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos)))
+#define SMC_TIMINGS_TAR_Pos 8
+#define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) /**< \brief (SMC_TIMINGS) ALE to REN Low Delay */
+#define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos)))
+#define SMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (SMC_TIMINGS) Off Chip Memory Scrambling Enable */
+#define SMC_TIMINGS_TRR_Pos 16
+#define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) /**< \brief (SMC_TIMINGS) Ready to REN Low Delay */
+#define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos)))
+#define SMC_TIMINGS_TWB_Pos 24
+#define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) /**< \brief (SMC_TIMINGS) WEN High to REN to Busy */
+#define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos)))
+#define SMC_TIMINGS_RBNSEL_Pos 28
+#define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) /**< \brief (SMC_TIMINGS) Ready/Busy Line Selection */
+#define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos)))
+#define SMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (SMC_TIMINGS) NAND Flash Selection */
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE)  */
+#define   SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NCS signal. */
+#define   SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NRD signal. */
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE)  */
+#define   SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (SMC_MODE) The Write operation is controller by the NCS signal. */
+#define   SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (SMC_MODE) The Write operation is controlled by the NWE signal. */
+#define SMC_MODE_EXNW_MODE_Pos 4
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
+#define   SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
+#define   SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
+#define   SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
+#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */
+#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */
+#define   SMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
+#define   SMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
+#define SMC_MODE_TDF_CYCLES_Pos 16
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
+/* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS Register -------- */
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
+#define SMC_OCMS_SRSE (0x1u << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */
+/* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC OCMS KEY1 Register -------- */
+#define SMC_KEY1_KEY1_Pos 0
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
+/* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC OCMS KEY2 Register -------- */
+#define SMC_KEY2_KEY2_Pos 0
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
+/* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */
+#define SMC_WPCR_WP_EN (0x1u << 0) /**< \brief (SMC_WPCR) Write Protection Enable */
+#define SMC_WPCR_WP_KEY_Pos 8
+#define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) /**< \brief (SMC_WPCR) Write Protection KEY password */
+#define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos)))
+/* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */
+#define SMC_WPSR_WP_VS_Pos 0
+#define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Status */
+#define SMC_WPSR_WP_VSRC_Pos 8
+#define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SMC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_spi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_spi.h
new file mode 100644
index 0000000..4009384
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_spi.h
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SPI_COMPONENT_
+#define _SAM3XA_SPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SPI Serial Peripheral Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Spi hardware registers */
+typedef struct {
+  WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
+  RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
+  RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
+  WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+  RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
+  WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+  WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+  RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+  RoReg Reserved1[4];
+  RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
+  RoReg Reserved2[41];
+  RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+  RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+} Spi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */
+#define SPI_WPMR_WPKEY_Pos 8
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */
+#define SPI_WPSR_WPVSRC_Pos 8
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SPI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_ssc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_ssc.h
new file mode 100644
index 0000000..91592af
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_ssc.h
@@ -0,0 +1,270 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SSC_COMPONENT_
+#define _SAM3XA_SSC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SSC Synchronous Serial Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Ssc hardware registers */
+typedef struct {
+  WoReg SSC_CR;        /**< \brief (Ssc Offset: 0x0) Control Register */
+  RwReg SSC_CMR;       /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
+  RoReg Reserved1[2];
+  RwReg SSC_RCMR;      /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
+  RwReg SSC_RFMR;      /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
+  RwReg SSC_TCMR;      /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
+  RwReg SSC_TFMR;      /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
+  RoReg SSC_RHR;       /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
+  WoReg SSC_THR;       /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
+  RoReg Reserved2[2];
+  RoReg SSC_RSHR;      /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
+  RwReg SSC_TSHR;      /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
+  RwReg SSC_RC0R;      /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
+  RwReg SSC_RC1R;      /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
+  RoReg SSC_SR;        /**< \brief (Ssc Offset: 0x40) Status Register */
+  WoReg SSC_IER;       /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
+  WoReg SSC_IDR;       /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
+  RoReg SSC_IMR;       /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved3[37];
+  RwReg SSC_WPMR;      /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
+  RoReg SSC_WPSR;      /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
+} Ssc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
+#define SSC_CMR_DIV_Pos 0
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
+#define SSC_RCMR_CKS_Pos 0
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
+#define   SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
+#define   SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
+#define   SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
+#define SSC_RCMR_CKO_Pos 2
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
+#define   SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
+#define SSC_RCMR_CKG_Pos 6
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
+#define   SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_START_Pos 8
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
+#define   SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define   SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
+#define   SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
+#define   SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
+#define   SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
+#define   SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
+#define   SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
+#define   SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
+#define   SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
+#define SSC_RCMR_STTDLY_Pos 16
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
+#define SSC_RCMR_PERIOD_Pos 24
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
+#define SSC_RFMR_DATLEN_Pos 0
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
+#define SSC_RFMR_DATNB_Pos 8
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
+#define SSC_RFMR_FSLEN_Pos 16
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
+#define SSC_RFMR_FSOS_Pos 20
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
+#define   SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
+#define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
+#define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
+#define   SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
+#define   SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
+#define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
+#define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
+#define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
+#define SSC_RFMR_FSLEN_EXT_Pos 28
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
+#define SSC_TCMR_CKS_Pos 0
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
+#define   SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
+#define   SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
+#define   SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
+#define SSC_TCMR_CKO_Pos 2
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
+#define   SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
+#define   SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
+#define SSC_TCMR_CKG_Pos 6
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
+#define   SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
+#define   SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
+#define SSC_TCMR_START_Pos 8
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
+#define   SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
+#define   SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
+#define   SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
+#define   SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
+#define   SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
+#define   SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
+#define   SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
+#define   SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
+#define   SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
+#define SSC_TCMR_STTDLY_Pos 16
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
+#define SSC_TCMR_PERIOD_Pos 24
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
+#define SSC_TFMR_DATLEN_Pos 0
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
+#define SSC_TFMR_DATNB_Pos 8
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
+#define SSC_TFMR_FSLEN_Pos 16
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
+#define SSC_TFMR_FSOS_Pos 20
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
+#define   SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
+#define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
+#define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
+#define   SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
+#define   SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
+#define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
+#define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
+#define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
+#define SSC_TFMR_FSLEN_EXT_Pos 28
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
+#define SSC_RHR_RDAT_Pos 0
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
+#define SSC_THR_TDAT_Pos 0
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
+#define SSC_RSHR_RSDAT_Pos 0
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
+#define SSC_TSHR_TSDAT_Pos 0
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
+#define SSC_RC0R_CP0_Pos 0
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
+#define SSC_RC1R_CP1_Pos 0
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
+#define SSC_WPMR_WPKEY_Pos 8
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
+#define SSC_WPSR_WPVSRC_Pos 8
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SSC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_supc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_supc.h
new file mode 100644
index 0000000..0b861f9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_supc.h
@@ -0,0 +1,312 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SUPC_COMPONENT_
+#define _SAM3XA_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_SUPC Supply Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Supc hardware registers */
+typedef struct {
+  WoReg SUPC_CR;   /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+  RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+  RwReg SUPC_MR;   /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+  RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+  RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+  RoReg SUPC_SR;   /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_VDDIORDYONREG (0x1u << 14) /**< \brief (SUPC_MR)  */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_FWUPEN (0x1u << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */
+#define   SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */
+#define   SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_FWUPDBC_Pos 8
+#define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer Period */
+#define   SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define   SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define   SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define   SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define   SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define   SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define   SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define   SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define   SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define   SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define   SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define   SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define   SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define   SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define   SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define   SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define   SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
+#define   SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
+#define   SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
+#define   SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
+#define   SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
+#define   SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
+#define   SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
+#define   SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
+#define   SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
+#define   SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
+#define   SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
+#define   SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
+#define   SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
+#define   SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
+#define   SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
+#define   SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
+#define   SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_FWUPS (0x1u << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */
+#define   SUPC_SR_FWUPS_NO (0x0u << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_FWUPS_PRESENT (0x1u << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define   SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define   SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define   SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define   SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define   SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define   SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define   SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */
+#define   SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define   SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_FWUPIS (0x1u << 12) /**< \brief (SUPC_SR) FWUP Input Status */
+#define   SUPC_SR_FWUPIS_LOW (0x0u << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */
+#define   SUPC_SR_FWUPIS_HIGH (0x1u << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_SUPC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_tc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_tc.h
new file mode 100644
index 0000000..a42d932
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_tc.h
@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TC_COMPONENT_
+#define _SAM3XA_TC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_TC Timer Counter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief TcChannel hardware registers */
+typedef struct {
+  RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+  RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+  RwReg      TC_SMMR;       /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
+  RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
+  RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
+  RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
+  RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
+  RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+  RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+  RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+  RoReg      Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+  TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+  WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
+  RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+  WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+  WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+  RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+  RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+  RwReg      TC_FMR;        /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
+  RoReg      Reserved1[2];
+  RwReg      TC_WPMR;       /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
+#define TC_WPMR_WPKEY_Pos 8
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM3XA_TC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_trng.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_trng.h
new file mode 100644
index 0000000..04a2d9e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_trng.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TRNG_COMPONENT_
+#define _SAM3XA_TRNG_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR True Random Number Generator */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_TRNG True Random Number Generator */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Trng hardware registers */
+typedef struct {
+  WoReg TRNG_CR;       /**< \brief (Trng Offset: 0x00) Control Register */
+  RoReg Reserved1[3];
+  WoReg TRNG_IER;      /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */
+  WoReg TRNG_IDR;      /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */
+  RoReg TRNG_IMR;      /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */
+  RoReg TRNG_ISR;      /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */
+  RoReg Reserved2[12];
+  RoReg TRNG_ODATA;    /**< \brief (Trng Offset: 0x50) Output Data Register */
+} Trng;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */
+#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */
+#define TRNG_CR_KEY_Pos 8
+#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */
+#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)))
+/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */
+#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */
+/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */
+#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */
+/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */
+#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */
+/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */
+#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */
+/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */
+#define TRNG_ODATA_ODATA_Pos 0
+#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_TRNG_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_twi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_twi.h
new file mode 100644
index 0000000..d65a870
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_twi.h
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TWI_COMPONENT_
+#define _SAM3XA_TWI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_TWI Two-wire Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Twi hardware registers */
+typedef struct {
+  WoReg TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
+  RwReg TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
+  RwReg TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+  RwReg TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+  RwReg TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+  RoReg Reserved1[3];
+  RoReg TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
+  WoReg TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+  WoReg TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+  RoReg TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+  RoReg TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+  WoReg TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+  RoReg Reserved2[50];
+  RwReg TWI_RPR;       /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+  RwReg TWI_RCR;       /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+  RwReg TWI_TPR;       /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+  RwReg TWI_TCR;       /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+  RwReg TWI_RNPR;      /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+  RwReg TWI_RNCR;      /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+  RwReg TWI_TNPR;      /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg TWI_TNCR;      /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg TWI_PTCR;      /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+  RoReg TWI_PTSR;      /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_TWI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_uart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_uart.h
new file mode 100644
index 0000000..bbf4421
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_uart.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_UART_COMPONENT_
+#define _SAM3XA_UART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Uart hardware registers */
+typedef struct {
+  WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
+  RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
+  WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+  WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+  RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+  RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
+  RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+  WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+  RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+  RoReg Reserved1[55];
+  RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+  RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+  RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+  RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+  RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+  RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+  RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+  RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_UART_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_uotghs.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_uotghs.h
new file mode 100644
index 0000000..33f553f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_uotghs.h
@@ -0,0 +1,938 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_UOTGHS_COMPONENT_
+#define _SAM3XA_UOTGHS_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR USB On-The-Go Interface */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_UOTGHS USB On-The-Go Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief UotghsDevdma hardware registers */
+typedef struct {
+  RwReg         UOTGHS_DEVDMANXTDSC;   /**< \brief (UotghsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */
+  RwReg         UOTGHS_DEVDMAADDRESS;  /**< \brief (UotghsDevdma Offset: 0x4) Device DMA Channel Address Register */
+  RwReg         UOTGHS_DEVDMACONTROL;  /**< \brief (UotghsDevdma Offset: 0x8) Device DMA Channel Control Register */
+  RwReg         UOTGHS_DEVDMASTATUS;   /**< \brief (UotghsDevdma Offset: 0xC) Device DMA Channel Status Register */
+} UotghsDevdma;
+/** \brief UotghsHstdma hardware registers */
+typedef struct {
+  RwReg         UOTGHS_HSTDMANXTDSC;   /**< \brief (UotghsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */
+  RwReg         UOTGHS_HSTDMAADDRESS;  /**< \brief (UotghsHstdma Offset: 0x4) Host DMA Channel Address Register */
+  RwReg         UOTGHS_HSTDMACONTROL;  /**< \brief (UotghsHstdma Offset: 0x8) Host DMA Channel Control Register */
+  RwReg         UOTGHS_HSTDMASTATUS;   /**< \brief (UotghsHstdma Offset: 0xC) Host DMA Channel Status Register */
+} UotghsHstdma;
+/** \brief Uotghs hardware registers */
+#define UOTGHSDEVDMA_NUMBER 7
+#define UOTGHSHSTDMA_NUMBER 7
+typedef struct {
+  RwReg         UOTGHS_DEVCTRL;        /**< \brief (Uotghs Offset: 0x0000) Device General Control Register */
+  RoReg         UOTGHS_DEVISR;         /**< \brief (Uotghs Offset: 0x0004) Device Global Interrupt Status Register */
+  WoReg         UOTGHS_DEVICR;         /**< \brief (Uotghs Offset: 0x0008) Device Global Interrupt Clear Register */
+  WoReg         UOTGHS_DEVIFR;         /**< \brief (Uotghs Offset: 0x000C) Device Global Interrupt Set Register */
+  RoReg         UOTGHS_DEVIMR;         /**< \brief (Uotghs Offset: 0x0010) Device Global Interrupt Mask Register */
+  WoReg         UOTGHS_DEVIDR;         /**< \brief (Uotghs Offset: 0x0014) Device Global Interrupt Disable Register */
+  WoReg         UOTGHS_DEVIER;         /**< \brief (Uotghs Offset: 0x0018) Device Global Interrupt Enable Register */
+  RwReg         UOTGHS_DEVEPT;         /**< \brief (Uotghs Offset: 0x001C) Device Endpoint Register */
+  RoReg         UOTGHS_DEVFNUM;        /**< \brief (Uotghs Offset: 0x0020) Device Frame Number Register */
+  RoReg         Reserved1[55];
+  RwReg         UOTGHS_DEVEPTCFG[10];  /**< \brief (Uotghs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */
+  RoReg         Reserved2[2];
+  RoReg         UOTGHS_DEVEPTISR[10];  /**< \brief (Uotghs Offset: 0x130) Device Endpoint Status Register (n = 0) */
+  RoReg         Reserved3[2];
+  WoReg         UOTGHS_DEVEPTICR[10];  /**< \brief (Uotghs Offset: 0x160) Device Endpoint Clear Register (n = 0) */
+  RoReg         Reserved4[2];
+  WoReg         UOTGHS_DEVEPTIFR[10];  /**< \brief (Uotghs Offset: 0x190) Device Endpoint Set Register (n = 0) */
+  RoReg         Reserved5[2];
+  RoReg         UOTGHS_DEVEPTIMR[10];  /**< \brief (Uotghs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */
+  RoReg         Reserved6[2];
+  WoReg         UOTGHS_DEVEPTIER[10];  /**< \brief (Uotghs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */
+  RoReg         Reserved7[2];
+  WoReg         UOTGHS_DEVEPTIDR[10];  /**< \brief (Uotghs Offset: 0x220) Device Endpoint Disable Register (n = 0) */
+  RoReg         Reserved8[50];
+  UotghsDevdma  UOTGHS_DEVDMA[UOTGHSDEVDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x310) n = 1 .. 7 */
+  RoReg         Reserved9[32];
+  RwReg         UOTGHS_HSTCTRL;        /**< \brief (Uotghs Offset: 0x0400) Host General Control Register */
+  RoReg         UOTGHS_HSTISR;         /**< \brief (Uotghs Offset: 0x0404) Host Global Interrupt Status Register */
+  WoReg         UOTGHS_HSTICR;         /**< \brief (Uotghs Offset: 0x0408) Host Global Interrupt Clear Register */
+  WoReg         UOTGHS_HSTIFR;         /**< \brief (Uotghs Offset: 0x040C) Host Global Interrupt Set Register */
+  RoReg         UOTGHS_HSTIMR;         /**< \brief (Uotghs Offset: 0x0410) Host Global Interrupt Mask Register */
+  WoReg         UOTGHS_HSTIDR;         /**< \brief (Uotghs Offset: 0x0414) Host Global Interrupt Disable Register */
+  WoReg         UOTGHS_HSTIER;         /**< \brief (Uotghs Offset: 0x0418) Host Global Interrupt Enable Register */
+  RwReg         UOTGHS_HSTPIP;         /**< \brief (Uotghs Offset: 0x0041C) Host Pipe Register */
+  RwReg         UOTGHS_HSTFNUM;        /**< \brief (Uotghs Offset: 0x0420) Host Frame Number Register */
+  RwReg         UOTGHS_HSTADDR1;       /**< \brief (Uotghs Offset: 0x0424) Host Address 1 Register */
+  RwReg         UOTGHS_HSTADDR2;       /**< \brief (Uotghs Offset: 0x0428) Host Address 2 Register */
+  RwReg         UOTGHS_HSTADDR3;       /**< \brief (Uotghs Offset: 0x042C) Host Address 3 Register */
+  RoReg         Reserved10[52];
+  RwReg         UOTGHS_HSTPIPCFG[10];  /**< \brief (Uotghs Offset: 0x500) Host Pipe Configuration Register (n = 0) */
+  RoReg         Reserved11[2];
+  RoReg         UOTGHS_HSTPIPISR[10];  /**< \brief (Uotghs Offset: 0x530) Host Pipe Status Register (n = 0) */
+  RoReg         Reserved12[2];
+  WoReg         UOTGHS_HSTPIPICR[10];  /**< \brief (Uotghs Offset: 0x560) Host Pipe Clear Register (n = 0) */
+  RoReg         Reserved13[2];
+  WoReg         UOTGHS_HSTPIPIFR[10];  /**< \brief (Uotghs Offset: 0x590) Host Pipe Set Register (n = 0) */
+  RoReg         Reserved14[2];
+  RoReg         UOTGHS_HSTPIPIMR[10];  /**< \brief (Uotghs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */
+  RoReg         Reserved15[2];
+  WoReg         UOTGHS_HSTPIPIER[10];  /**< \brief (Uotghs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */
+  RoReg         Reserved16[2];
+  WoReg         UOTGHS_HSTPIPIDR[10];  /**< \brief (Uotghs Offset: 0x620) Host Pipe Disable Register (n = 0) */
+  RoReg         Reserved17[2];
+  RwReg         UOTGHS_HSTPIPINRQ[10]; /**< \brief (Uotghs Offset: 0x650) Host Pipe IN Request Register (n = 0) */
+  RoReg         Reserved18[2];
+  RwReg         UOTGHS_HSTPIPERR[10];  /**< \brief (Uotghs Offset: 0x680) Host Pipe Error Register (n = 0) */
+  RoReg         Reserved19[26];
+  UotghsHstdma  UOTGHS_HSTDMA[UOTGHSHSTDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x710) n = 1 .. 7 */
+  RoReg         Reserved20[32];
+  RwReg         UOTGHS_CTRL;           /**< \brief (Uotghs Offset: 0x0800) General Control Register */
+  RoReg         UOTGHS_SR;             /**< \brief (Uotghs Offset: 0x0804) General Status Register */
+  WoReg         UOTGHS_SCR;            /**< \brief (Uotghs Offset: 0x0808) General Status Clear Register */
+  WoReg         UOTGHS_SFR;            /**< \brief (Uotghs Offset: 0x080C) General Status Set Register */
+  RoReg         Reserved21[7];
+  RoReg         UOTGHS_FSM;            /**< \brief (Uotghs Offset: 0x082C) General Finite State Machine Register */
+} Uotghs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UOTGHS_DEVCTRL : (UOTGHS Offset: 0x0000) Device General Control Register -------- */
+#define UOTGHS_DEVCTRL_UADD_Pos 0
+#define UOTGHS_DEVCTRL_UADD_Msk (0x7fu << UOTGHS_DEVCTRL_UADD_Pos) /**< \brief (UOTGHS_DEVCTRL) USB Address */
+#define UOTGHS_DEVCTRL_UADD(value) ((UOTGHS_DEVCTRL_UADD_Msk & ((value) << UOTGHS_DEVCTRL_UADD_Pos)))
+#define UOTGHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (UOTGHS_DEVCTRL) Address Enable */
+#define UOTGHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (UOTGHS_DEVCTRL) Detach */
+#define UOTGHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (UOTGHS_DEVCTRL) Remote Wake-Up */
+#define UOTGHS_DEVCTRL_SPDCONF_Pos 10
+#define UOTGHS_DEVCTRL_SPDCONF_Msk (0x3u << UOTGHS_DEVCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_DEVCTRL) Mode Configuration */
+#define   UOTGHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. */
+#define   UOTGHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (UOTGHS_DEVCTRL) For a better consumption, if high-speed is not needed. */
+#define   UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (UOTGHS_DEVCTRL) Forced high speed. */
+#define   UOTGHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral remains in full-speed mode whatever the host speed capability. */
+#define UOTGHS_DEVCTRL_LS (0x1u << 12) /**< \brief (UOTGHS_DEVCTRL) Low-Speed Mode Force */
+#define UOTGHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (UOTGHS_DEVCTRL) Test mode J */
+#define UOTGHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (UOTGHS_DEVCTRL) Test mode K */
+#define UOTGHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (UOTGHS_DEVCTRL) Test packet mode */
+#define UOTGHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (UOTGHS_DEVCTRL) Specific Operational mode */
+/* -------- UOTGHS_DEVISR : (UOTGHS Offset: 0x0004) Device Global Interrupt Status Register -------- */
+#define UOTGHS_DEVISR_SUSP (0x1u << 0) /**< \brief (UOTGHS_DEVISR) Suspend Interrupt */
+#define UOTGHS_DEVISR_MSOF (0x1u << 1) /**< \brief (UOTGHS_DEVISR) Micro Start of Frame Interrupt */
+#define UOTGHS_DEVISR_SOF (0x1u << 2) /**< \brief (UOTGHS_DEVISR) Start of Frame Interrupt */
+#define UOTGHS_DEVISR_EORST (0x1u << 3) /**< \brief (UOTGHS_DEVISR) End of Reset Interrupt */
+#define UOTGHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (UOTGHS_DEVISR) Wake-Up Interrupt */
+#define UOTGHS_DEVISR_EORSM (0x1u << 5) /**< \brief (UOTGHS_DEVISR) End of Resume Interrupt */
+#define UOTGHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (UOTGHS_DEVISR) Upstream Resume Interrupt */
+#define UOTGHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVISR) Endpoint 0 Interrupt */
+#define UOTGHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVISR) Endpoint 1 Interrupt */
+#define UOTGHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVISR) Endpoint 2 Interrupt */
+#define UOTGHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVISR) Endpoint 3 Interrupt */
+#define UOTGHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVISR) Endpoint 4 Interrupt */
+#define UOTGHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVISR) Endpoint 5 Interrupt */
+#define UOTGHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVISR) Endpoint 6 Interrupt */
+#define UOTGHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVISR) Endpoint 7 Interrupt */
+#define UOTGHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVISR) Endpoint 8 Interrupt */
+#define UOTGHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVISR) Endpoint 9 Interrupt */
+#define UOTGHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVISR) DMA Channel 1 Interrupt */
+#define UOTGHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVISR) DMA Channel 2 Interrupt */
+#define UOTGHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVISR) DMA Channel 3 Interrupt */
+#define UOTGHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVISR) DMA Channel 4 Interrupt */
+#define UOTGHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVISR) DMA Channel 5 Interrupt */
+#define UOTGHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVISR) DMA Channel 6 Interrupt */
+/* -------- UOTGHS_DEVICR : (UOTGHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */
+#define UOTGHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (UOTGHS_DEVICR) Suspend Interrupt Clear */
+#define UOTGHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (UOTGHS_DEVICR) Micro Start of Frame Interrupt Clear */
+#define UOTGHS_DEVICR_SOFC (0x1u << 2) /**< \brief (UOTGHS_DEVICR) Start of Frame Interrupt Clear */
+#define UOTGHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (UOTGHS_DEVICR) End of Reset Interrupt Clear */
+#define UOTGHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (UOTGHS_DEVICR) Wake-Up Interrupt Clear */
+#define UOTGHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (UOTGHS_DEVICR) End of Resume Interrupt Clear */
+#define UOTGHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (UOTGHS_DEVICR) Upstream Resume Interrupt Clear */
+/* -------- UOTGHS_DEVIFR : (UOTGHS Offset: 0x000C) Device Global Interrupt Set Register -------- */
+#define UOTGHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (UOTGHS_DEVIFR) Suspend Interrupt Set */
+#define UOTGHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (UOTGHS_DEVIFR) Micro Start of Frame Interrupt Set */
+#define UOTGHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (UOTGHS_DEVIFR) Start of Frame Interrupt Set */
+#define UOTGHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (UOTGHS_DEVIFR) End of Reset Interrupt Set */
+#define UOTGHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (UOTGHS_DEVIFR) Wake-Up Interrupt Set */
+#define UOTGHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (UOTGHS_DEVIFR) End of Resume Interrupt Set */
+#define UOTGHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (UOTGHS_DEVIFR) Upstream Resume Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIFR) DMA Channel 1 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIFR) DMA Channel 2 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIFR) DMA Channel 3 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIFR) DMA Channel 4 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIFR) DMA Channel 5 Interrupt Set */
+#define UOTGHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIFR) DMA Channel 6 Interrupt Set */
+/* -------- UOTGHS_DEVIMR : (UOTGHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */
+#define UOTGHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (UOTGHS_DEVIMR) Suspend Interrupt Mask */
+#define UOTGHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (UOTGHS_DEVIMR) Micro Start of Frame Interrupt Mask */
+#define UOTGHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (UOTGHS_DEVIMR) Start of Frame Interrupt Mask */
+#define UOTGHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (UOTGHS_DEVIMR) End of Reset Interrupt Mask */
+#define UOTGHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (UOTGHS_DEVIMR) Wake-Up Interrupt Mask */
+#define UOTGHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (UOTGHS_DEVIMR) End of Resume Interrupt Mask */
+#define UOTGHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (UOTGHS_DEVIMR) Upstream Resume Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIMR) Endpoint 0 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIMR) Endpoint 1 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIMR) Endpoint 2 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIMR) Endpoint 3 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIMR) Endpoint 4 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIMR) Endpoint 5 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIMR) Endpoint 6 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIMR) Endpoint 7 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIMR) Endpoint 8 Interrupt Mask */
+#define UOTGHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIMR) Endpoint 9 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIMR) DMA Channel 1 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIMR) DMA Channel 2 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIMR) DMA Channel 3 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIMR) DMA Channel 4 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIMR) DMA Channel 5 Interrupt Mask */
+#define UOTGHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIMR) DMA Channel 6 Interrupt Mask */
+/* -------- UOTGHS_DEVIDR : (UOTGHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */
+#define UOTGHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (UOTGHS_DEVIDR) Suspend Interrupt Disable */
+#define UOTGHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (UOTGHS_DEVIDR) Micro Start of Frame Interrupt Disable */
+#define UOTGHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (UOTGHS_DEVIDR) Start of Frame Interrupt Disable */
+#define UOTGHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (UOTGHS_DEVIDR) End of Reset Interrupt Disable */
+#define UOTGHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (UOTGHS_DEVIDR) Wake-Up Interrupt Disable */
+#define UOTGHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (UOTGHS_DEVIDR) End of Resume Interrupt Disable */
+#define UOTGHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (UOTGHS_DEVIDR) Upstream Resume Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIDR) Endpoint 0 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIDR) Endpoint 1 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIDR) Endpoint 2 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIDR) Endpoint 3 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIDR) Endpoint 4 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIDR) Endpoint 5 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIDR) Endpoint 6 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIDR) Endpoint 7 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIDR) Endpoint 8 Interrupt Disable */
+#define UOTGHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIDR) Endpoint 9 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIDR) DMA Channel 1 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIDR) DMA Channel 2 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIDR) DMA Channel 3 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIDR) DMA Channel 4 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIDR) DMA Channel 5 Interrupt Disable */
+#define UOTGHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIDR) DMA Channel 6 Interrupt Disable */
+/* -------- UOTGHS_DEVIER : (UOTGHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */
+#define UOTGHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (UOTGHS_DEVIER) Suspend Interrupt Enable */
+#define UOTGHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (UOTGHS_DEVIER) Micro Start of Frame Interrupt Enable */
+#define UOTGHS_DEVIER_SOFES (0x1u << 2) /**< \brief (UOTGHS_DEVIER) Start of Frame Interrupt Enable */
+#define UOTGHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (UOTGHS_DEVIER) End of Reset Interrupt Enable */
+#define UOTGHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (UOTGHS_DEVIER) Wake-Up Interrupt Enable */
+#define UOTGHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (UOTGHS_DEVIER) End of Resume Interrupt Enable */
+#define UOTGHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (UOTGHS_DEVIER) Upstream Resume Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIER) Endpoint 0 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIER) Endpoint 1 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIER) Endpoint 2 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIER) Endpoint 3 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIER) Endpoint 4 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIER) Endpoint 5 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIER) Endpoint 6 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIER) Endpoint 7 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIER) Endpoint 8 Interrupt Enable */
+#define UOTGHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIER) Endpoint 9 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIER) DMA Channel 1 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIER) DMA Channel 2 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIER) DMA Channel 3 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIER) DMA Channel 4 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIER) DMA Channel 5 Interrupt Enable */
+#define UOTGHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIER) DMA Channel 6 Interrupt Enable */
+/* -------- UOTGHS_DEVEPT : (UOTGHS Offset: 0x001C) Device Endpoint Register -------- */
+#define UOTGHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Enable */
+#define UOTGHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Enable */
+#define UOTGHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Enable */
+#define UOTGHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Enable */
+#define UOTGHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Enable */
+#define UOTGHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Enable */
+#define UOTGHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Enable */
+#define UOTGHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Enable */
+#define UOTGHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Enable */
+#define UOTGHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Reset */
+#define UOTGHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Reset */
+#define UOTGHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Reset */
+#define UOTGHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Reset */
+#define UOTGHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Reset */
+#define UOTGHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Reset */
+#define UOTGHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Reset */
+#define UOTGHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Reset */
+#define UOTGHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Reset */
+/* -------- UOTGHS_DEVFNUM : (UOTGHS Offset: 0x0020) Device Frame Number Register -------- */
+#define UOTGHS_DEVFNUM_MFNUM_Pos 0
+#define UOTGHS_DEVFNUM_MFNUM_Msk (0x7u << UOTGHS_DEVFNUM_MFNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Micro Frame Number */
+#define UOTGHS_DEVFNUM_FNUM_Pos 3
+#define UOTGHS_DEVFNUM_FNUM_Msk (0x7ffu << UOTGHS_DEVFNUM_FNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Frame Number */
+#define UOTGHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (UOTGHS_DEVFNUM) Frame Number CRC Error */
+/* -------- UOTGHS_DEVEPTCFG[10] : (UOTGHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */
+#define UOTGHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Memory Allocate */
+#define UOTGHS_DEVEPTCFG_EPBK_Pos 2
+#define UOTGHS_DEVEPTCFG_EPBK_Msk (0x3u << UOTGHS_DEVEPTCFG_EPBK_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Banks */
+#define   UOTGHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Single-bank endpoint */
+#define   UOTGHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Double-bank endpoint */
+#define   UOTGHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Triple-bank endpoint */
+#define UOTGHS_DEVEPTCFG_EPSIZE_Pos 4
+#define UOTGHS_DEVEPTCFG_EPSIZE_Msk (0x7u << UOTGHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Size */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 8 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 16 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 32 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 64 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 128 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 256 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 512 bytes */
+#define   UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 1024 bytes */
+#define UOTGHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Direction */
+#define   UOTGHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) The endpoint direction is OUT. */
+#define   UOTGHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */
+#define UOTGHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (UOTGHS_DEVEPTCFG[10]) Automatic Switch */
+#define UOTGHS_DEVEPTCFG_EPTYPE_Pos 11
+#define UOTGHS_DEVEPTCFG_EPTYPE_Msk (0x3u << UOTGHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Type */
+#define   UOTGHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Control */
+#define   UOTGHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Isochronous */
+#define   UOTGHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Bulk */
+#define   UOTGHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Interrupt */
+#define UOTGHS_DEVEPTCFG_NBTRANS_Pos 13
+#define UOTGHS_DEVEPTCFG_NBTRANS_Msk (0x3u << UOTGHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Number of transaction per microframe for isochronous endpoint */
+#define   UOTGHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) reserved to endpoint that does not have the high-bandwidth isochronous capability. */
+#define   UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) default value: one transaction per micro-frame. */
+#define   UOTGHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) 2 transactions per micro-frame. This endpoint should be configured as double-bank. */
+#define   UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) 3 transactions per micro-frame. This endpoint should be configured as triple-bank. */
+/* -------- UOTGHS_DEVEPTISR[10] : (UOTGHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */
+#define UOTGHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (UOTGHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */
+#define UOTGHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (UOTGHS_DEVEPTISR[10]) Received OUT Data Interrupt */
+#define UOTGHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[10]) Received SETUP Interrupt */
+#define UOTGHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[10]) Underflow Interrupt */
+#define UOTGHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[10]) NAKed OUT Interrupt */
+#define UOTGHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[10]) High bandwidth isochronous IN Underflow Error Interrupt */
+#define UOTGHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[10]) NAKed IN Interrupt */
+#define UOTGHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */
+#define UOTGHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_DEVEPTISR[10]) Overflow Interrupt */
+#define UOTGHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[10]) STALLed Interrupt */
+#define UOTGHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[10]) CRC Error Interrupt */
+#define UOTGHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (UOTGHS_DEVEPTISR[10]) Short Packet Interrupt */
+#define UOTGHS_DEVEPTISR_DTSEQ_Pos 8
+#define UOTGHS_DEVEPTISR_DTSEQ_Msk (0x3u << UOTGHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Data Toggle Sequence */
+#define   UOTGHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data0 toggle sequence */
+#define   UOTGHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data1 toggle sequence */
+#define   UOTGHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data2 toggle sequence (for high-bandwidth isochronous endpoint) */
+#define   UOTGHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) MData toggle sequence (for high-bandwidth isochronous endpoint) */
+#define UOTGHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (UOTGHS_DEVEPTISR[10]) High-bandwidth isochronous OUT endpoint transaction error Interrupt */
+#define UOTGHS_DEVEPTISR_NBUSYBK_Pos 12
+#define UOTGHS_DEVEPTISR_NBUSYBK_Msk (0x3u << UOTGHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Number of Busy Banks */
+#define   UOTGHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 0 busy bank (all banks free) */
+#define   UOTGHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 1 busy bank */
+#define   UOTGHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 2 busy banks */
+#define   UOTGHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 3 busy banks */
+#define UOTGHS_DEVEPTISR_CURRBK_Pos 14
+#define UOTGHS_DEVEPTISR_CURRBK_Msk (0x3u << UOTGHS_DEVEPTISR_CURRBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Current Bank */
+#define   UOTGHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank0 */
+#define   UOTGHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank1 */
+#define   UOTGHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank2 */
+#define UOTGHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_DEVEPTISR[10]) Read-write Allowed */
+#define UOTGHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (UOTGHS_DEVEPTISR[10]) Control Direction */
+#define UOTGHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_DEVEPTISR[10]) Configuration OK Status */
+#define UOTGHS_DEVEPTISR_BYCT_Pos 20
+#define UOTGHS_DEVEPTISR_BYCT_Msk (0x7ffu << UOTGHS_DEVEPTISR_BYCT_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Byte Count */
+/* -------- UOTGHS_DEVEPTICR[10] : (UOTGHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */
+#define UOTGHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */
+#define UOTGHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */
+#define UOTGHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */
+#define UOTGHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[10]) Underflow Interrupt Clear */
+#define UOTGHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */
+#define UOTGHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[10]) High bandwidth isochronous IN Underflow Error Interrupt Clear */
+#define UOTGHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */
+#define UOTGHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
+#define UOTGHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTICR[10]) Overflow Interrupt Clear */
+#define UOTGHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[10]) STALLed Interrupt Clear */
+#define UOTGHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[10]) CRC Error Interrupt Clear */
+#define UOTGHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTICR[10]) Short Packet Interrupt Clear */
+/* -------- UOTGHS_DEVEPTIFR[10] : (UOTGHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */
+#define UOTGHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */
+#define UOTGHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */
+#define UOTGHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[10]) Underflow Interrupt Set */
+#define UOTGHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */
+#define UOTGHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[10]) High bandwidth isochronous IN Underflow Error Interrupt Set */
+#define UOTGHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */
+#define UOTGHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */
+#define UOTGHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIFR[10]) Overflow Interrupt Set */
+#define UOTGHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[10]) STALLed Interrupt Set */
+#define UOTGHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[10]) CRC Error Interrupt Set */
+#define UOTGHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIFR[10]) Short Packet Interrupt Set */
+#define UOTGHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */
+/* -------- UOTGHS_DEVEPTIMR[10] : (UOTGHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */
+#define UOTGHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIMR[10]) Received OUT Data Interrupt */
+#define UOTGHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[10]) Received SETUP Interrupt */
+#define UOTGHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[10]) Underflow Interrupt */
+#define UOTGHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[10]) NAKed OUT Interrupt */
+#define UOTGHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */
+#define UOTGHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[10]) NAKed IN Interrupt */
+#define UOTGHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */
+#define UOTGHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIMR[10]) Overflow Interrupt */
+#define UOTGHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[10]) STALLed Interrupt */
+#define UOTGHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[10]) CRC Error Interrupt */
+#define UOTGHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIMR[10]) Short Packet Interrupt */
+#define UOTGHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIMR[10]) MData Interrupt */
+#define UOTGHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIMR[10]) DataX Interrupt */
+#define UOTGHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIMR[10]) Transaction Error Interrupt */
+#define UOTGHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */
+#define UOTGHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIMR[10]) Kill IN Bank */
+#define UOTGHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIMR[10]) FIFO Control */
+#define UOTGHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */
+#define UOTGHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIMR[10]) NYET Token Disable */
+#define UOTGHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIMR[10]) Reset Data Toggle */
+#define UOTGHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIMR[10]) STALL Request */
+/* -------- UOTGHS_DEVEPTIER[10] : (UOTGHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */
+#define UOTGHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */
+#define UOTGHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */
+#define UOTGHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[10]) Underflow Interrupt Enable */
+#define UOTGHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */
+#define UOTGHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */
+#define UOTGHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */
+#define UOTGHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */
+#define UOTGHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIER[10]) Overflow Interrupt Enable */
+#define UOTGHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[10]) STALLed Interrupt Enable */
+#define UOTGHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[10]) CRC Error Interrupt Enable */
+#define UOTGHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIER[10]) Short Packet Interrupt Enable */
+#define UOTGHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIER[10]) MData Interrupt Enable */
+#define UOTGHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIER[10]) DataX Interrupt Enable */
+#define UOTGHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */
+#define UOTGHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */
+#define UOTGHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIER[10]) Kill IN Bank */
+#define UOTGHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */
+#define UOTGHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIER[10]) NYET Token Disable Enable */
+#define UOTGHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIER[10]) Reset Data Toggle Enable */
+#define UOTGHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIER[10]) STALL Request Enable */
+/* -------- UOTGHS_DEVEPTIDR[10] : (UOTGHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */
+#define UOTGHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[10]) Underflow Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIDR[10]) Overflow Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[10]) STALLed Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIDR[10]) MData Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIDR[10]) DataX Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */
+#define UOTGHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIDR[10]) FIFO Control Clear */
+#define UOTGHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */
+#define UOTGHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIDR[10]) NYET Token Disable Clear */
+#define UOTGHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIDR[10]) STALL Request Clear */
+/* -------- UOTGHS_DEVDMANXTDSC : (UOTGHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_DEVDMANXTDSC) Next Descriptor Address */
+#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))
+/* -------- UOTGHS_DEVDMAADDRESS : (UOTGHS Offset: N/A) Device DMA Channel Address Register -------- */
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos 0
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_DEVDMAADDRESS) Buffer Address */
+#define UOTGHS_DEVDMAADDRESS_BUFF_ADD(value) ((UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos)))
+/* -------- UOTGHS_DEVDMACONTROL : (UOTGHS Offset: N/A) Device DMA Channel Control Register -------- */
+#define UOTGHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMACONTROL) Channel Enable Command */
+#define UOTGHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
+#define UOTGHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Enable Control */
+#define UOTGHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Enable Control */
+#define UOTGHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Interrupt Enable */
+#define UOTGHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Interrupt Enable */
+#define UOTGHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */
+#define UOTGHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_DEVDMACONTROL) Burst Lock Enable */
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */
+#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))
+/* -------- UOTGHS_DEVDMASTATUS : (UOTGHS Offset: N/A) Device DMA Channel Status Register -------- */
+#define UOTGHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Enable Status */
+#define UOTGHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Active Status */
+#define UOTGHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Transfer Status */
+#define UOTGHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Buffer Status */
+#define UOTGHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_DEVDMASTATUS) Descriptor Loaded Status */
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos 16
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_DEVDMASTATUS) Buffer Byte Count */
+#define UOTGHS_DEVDMASTATUS_BUFF_COUNT(value) ((UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos)))
+/* -------- UOTGHS_HSTCTRL : (UOTGHS Offset: 0x0400) Host General Control Register -------- */
+#define UOTGHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (UOTGHS_HSTCTRL) Start of Frame Generation Enable */
+#define UOTGHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (UOTGHS_HSTCTRL) Send USB Reset */
+#define UOTGHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (UOTGHS_HSTCTRL) Send USB Resume */
+#define UOTGHS_HSTCTRL_SPDCONF_Pos 12
+#define UOTGHS_HSTCTRL_SPDCONF_Msk (0x3u << UOTGHS_HSTCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_HSTCTRL) Mode Configuration */
+#define   UOTGHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (UOTGHS_HSTCTRL) The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. */
+#define   UOTGHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (UOTGHS_HSTCTRL) For a better consumption, if high-speed is not needed. */
+#define   UOTGHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (UOTGHS_HSTCTRL) Forced high speed. */
+#define   UOTGHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (UOTGHS_HSTCTRL) The host remains to full-speed mode whatever the peripheral speed capability. */
+/* -------- UOTGHS_HSTISR : (UOTGHS Offset: 0x0404) Host Global Interrupt Status Register -------- */
+#define UOTGHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (UOTGHS_HSTISR) Device Connection Interrupt */
+#define UOTGHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (UOTGHS_HSTISR) Device Disconnection Interrupt */
+#define UOTGHS_HSTISR_RSTI (0x1u << 2) /**< \brief (UOTGHS_HSTISR) USB Reset Sent Interrupt */
+#define UOTGHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (UOTGHS_HSTISR) Downstream Resume Sent Interrupt */
+#define UOTGHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (UOTGHS_HSTISR) Upstream Resume Received Interrupt */
+#define UOTGHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (UOTGHS_HSTISR) Host Start of Frame Interrupt */
+#define UOTGHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (UOTGHS_HSTISR) Host Wake-Up Interrupt */
+#define UOTGHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTISR) Pipe 0 Interrupt */
+#define UOTGHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTISR) Pipe 1 Interrupt */
+#define UOTGHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTISR) Pipe 2 Interrupt */
+#define UOTGHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTISR) Pipe 3 Interrupt */
+#define UOTGHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTISR) Pipe 4 Interrupt */
+#define UOTGHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTISR) Pipe 5 Interrupt */
+#define UOTGHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTISR) Pipe 6 Interrupt */
+#define UOTGHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTISR) Pipe 7 Interrupt */
+#define UOTGHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTISR) Pipe 8 Interrupt */
+#define UOTGHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTISR) Pipe 9 Interrupt */
+#define UOTGHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTISR) DMA Channel 1 Interrupt */
+#define UOTGHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTISR) DMA Channel 2 Interrupt */
+#define UOTGHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTISR) DMA Channel 3 Interrupt */
+#define UOTGHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTISR) DMA Channel 4 Interrupt */
+#define UOTGHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTISR) DMA Channel 5 Interrupt */
+#define UOTGHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTISR) DMA Channel 6 Interrupt */
+/* -------- UOTGHS_HSTICR : (UOTGHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */
+#define UOTGHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (UOTGHS_HSTICR) Device Connection Interrupt Clear */
+#define UOTGHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (UOTGHS_HSTICR) Device Disconnection Interrupt Clear */
+#define UOTGHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (UOTGHS_HSTICR) USB Reset Sent Interrupt Clear */
+#define UOTGHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (UOTGHS_HSTICR) Downstream Resume Sent Interrupt Clear */
+#define UOTGHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (UOTGHS_HSTICR) Upstream Resume Received Interrupt Clear */
+#define UOTGHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (UOTGHS_HSTICR) Host Start of Frame Interrupt Clear */
+#define UOTGHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (UOTGHS_HSTICR) Host Wake-Up Interrupt Clear */
+/* -------- UOTGHS_HSTIFR : (UOTGHS Offset: 0x040C) Host Global Interrupt Set Register -------- */
+#define UOTGHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (UOTGHS_HSTIFR) Device Connection Interrupt Set */
+#define UOTGHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (UOTGHS_HSTIFR) Device Disconnection Interrupt Set */
+#define UOTGHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (UOTGHS_HSTIFR) USB Reset Sent Interrupt Set */
+#define UOTGHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (UOTGHS_HSTIFR) Downstream Resume Sent Interrupt Set */
+#define UOTGHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (UOTGHS_HSTIFR) Upstream Resume Received Interrupt Set */
+#define UOTGHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (UOTGHS_HSTIFR) Host Start of Frame Interrupt Set */
+#define UOTGHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (UOTGHS_HSTIFR) Host Wake-Up Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIFR) DMA Channel 1 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIFR) DMA Channel 2 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIFR) DMA Channel 3 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIFR) DMA Channel 4 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIFR) DMA Channel 5 Interrupt Set */
+#define UOTGHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIFR) DMA Channel 6 Interrupt Set */
+/* -------- UOTGHS_HSTIMR : (UOTGHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */
+#define UOTGHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (UOTGHS_HSTIMR) Device Connection Interrupt Enable */
+#define UOTGHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (UOTGHS_HSTIMR) Device Disconnection Interrupt Enable */
+#define UOTGHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (UOTGHS_HSTIMR) USB Reset Sent Interrupt Enable */
+#define UOTGHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (UOTGHS_HSTIMR) Downstream Resume Sent Interrupt Enable */
+#define UOTGHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (UOTGHS_HSTIMR) Upstream Resume Received Interrupt Enable */
+#define UOTGHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (UOTGHS_HSTIMR) Host Start of Frame Interrupt Enable */
+#define UOTGHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (UOTGHS_HSTIMR) Host Wake-Up Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIMR) Pipe 0 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIMR) Pipe 1 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIMR) Pipe 2 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIMR) Pipe 3 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIMR) Pipe 4 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIMR) Pipe 5 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIMR) Pipe 6 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIMR) Pipe 7 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIMR) Pipe 8 Interrupt Enable */
+#define UOTGHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIMR) Pipe 9 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIMR) DMA Channel 1 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIMR) DMA Channel 2 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIMR) DMA Channel 3 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIMR) DMA Channel 4 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIMR) DMA Channel 5 Interrupt Enable */
+#define UOTGHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIMR) DMA Channel 6 Interrupt Enable */
+/* -------- UOTGHS_HSTIDR : (UOTGHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */
+#define UOTGHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (UOTGHS_HSTIDR) Device Connection Interrupt Disable */
+#define UOTGHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (UOTGHS_HSTIDR) Device Disconnection Interrupt Disable */
+#define UOTGHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (UOTGHS_HSTIDR) USB Reset Sent Interrupt Disable */
+#define UOTGHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (UOTGHS_HSTIDR) Downstream Resume Sent Interrupt Disable */
+#define UOTGHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (UOTGHS_HSTIDR) Upstream Resume Received Interrupt Disable */
+#define UOTGHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTIDR) Host Start of Frame Interrupt Disable */
+#define UOTGHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (UOTGHS_HSTIDR) Host Wake-Up Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIDR) Pipe 0 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIDR) Pipe 1 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIDR) Pipe 2 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIDR) Pipe 3 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIDR) Pipe 4 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIDR) Pipe 5 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIDR) Pipe 6 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIDR) Pipe 7 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIDR) Pipe 8 Interrupt Disable */
+#define UOTGHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIDR) Pipe 9 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIDR) DMA Channel 1 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIDR) DMA Channel 2 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIDR) DMA Channel 3 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIDR) DMA Channel 4 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIDR) DMA Channel 5 Interrupt Disable */
+#define UOTGHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIDR) DMA Channel 6 Interrupt Disable */
+/* -------- UOTGHS_HSTIER : (UOTGHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */
+#define UOTGHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (UOTGHS_HSTIER) Device Connection Interrupt Enable */
+#define UOTGHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (UOTGHS_HSTIER) Device Disconnection Interrupt Enable */
+#define UOTGHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (UOTGHS_HSTIER) USB Reset Sent Interrupt Enable */
+#define UOTGHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (UOTGHS_HSTIER) Downstream Resume Sent Interrupt Enable */
+#define UOTGHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (UOTGHS_HSTIER) Upstream Resume Received Interrupt Enable */
+#define UOTGHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (UOTGHS_HSTIER) Host Start of Frame Interrupt Enable */
+#define UOTGHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (UOTGHS_HSTIER) Host Wake-Up Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIER) Pipe 0 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIER) Pipe 1 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIER) Pipe 2 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIER) Pipe 3 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIER) Pipe 4 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIER) Pipe 5 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIER) Pipe 6 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIER) Pipe 7 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIER) Pipe 8 Interrupt Enable */
+#define UOTGHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIER) Pipe 9 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIER) DMA Channel 1 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIER) DMA Channel 2 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIER) DMA Channel 3 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIER) DMA Channel 4 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIER) DMA Channel 5 Interrupt Enable */
+#define UOTGHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIER) DMA Channel 6 Interrupt Enable */
+/* -------- UOTGHS_HSTPIP : (UOTGHS Offset: 0x0041C) Host Pipe Register -------- */
+#define UOTGHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Enable */
+#define UOTGHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Enable */
+#define UOTGHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Enable */
+#define UOTGHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Enable */
+#define UOTGHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Enable */
+#define UOTGHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Enable */
+#define UOTGHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Enable */
+#define UOTGHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Enable */
+#define UOTGHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Enable */
+#define UOTGHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Reset */
+#define UOTGHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Reset */
+#define UOTGHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Reset */
+#define UOTGHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Reset */
+#define UOTGHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Reset */
+#define UOTGHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Reset */
+#define UOTGHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Reset */
+#define UOTGHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Reset */
+#define UOTGHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Reset */
+/* -------- UOTGHS_HSTFNUM : (UOTGHS Offset: 0x0420) Host Frame Number Register -------- */
+#define UOTGHS_HSTFNUM_MFNUM_Pos 0
+#define UOTGHS_HSTFNUM_MFNUM_Msk (0x7u << UOTGHS_HSTFNUM_MFNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Micro Frame Number */
+#define UOTGHS_HSTFNUM_MFNUM(value) ((UOTGHS_HSTFNUM_MFNUM_Msk & ((value) << UOTGHS_HSTFNUM_MFNUM_Pos)))
+#define UOTGHS_HSTFNUM_FNUM_Pos 3
+#define UOTGHS_HSTFNUM_FNUM_Msk (0x7ffu << UOTGHS_HSTFNUM_FNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Number */
+#define UOTGHS_HSTFNUM_FNUM(value) ((UOTGHS_HSTFNUM_FNUM_Msk & ((value) << UOTGHS_HSTFNUM_FNUM_Pos)))
+#define UOTGHS_HSTFNUM_FLENHIGH_Pos 16
+#define UOTGHS_HSTFNUM_FLENHIGH_Msk (0xffu << UOTGHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Length */
+#define UOTGHS_HSTFNUM_FLENHIGH(value) ((UOTGHS_HSTFNUM_FLENHIGH_Msk & ((value) << UOTGHS_HSTFNUM_FLENHIGH_Pos)))
+/* -------- UOTGHS_HSTADDR1 : (UOTGHS Offset: 0x0424) Host Address 1 Register -------- */
+#define UOTGHS_HSTADDR1_HSTADDRP0_Pos 0
+#define UOTGHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP0(value) ((UOTGHS_HSTADDR1_HSTADDRP0_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP0_Pos)))
+#define UOTGHS_HSTADDR1_HSTADDRP1_Pos 8
+#define UOTGHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP1(value) ((UOTGHS_HSTADDR1_HSTADDRP1_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP1_Pos)))
+#define UOTGHS_HSTADDR1_HSTADDRP2_Pos 16
+#define UOTGHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP2(value) ((UOTGHS_HSTADDR1_HSTADDRP2_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP2_Pos)))
+#define UOTGHS_HSTADDR1_HSTADDRP3_Pos 24
+#define UOTGHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */
+#define UOTGHS_HSTADDR1_HSTADDRP3(value) ((UOTGHS_HSTADDR1_HSTADDRP3_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP3_Pos)))
+/* -------- UOTGHS_HSTADDR2 : (UOTGHS Offset: 0x0428) Host Address 2 Register -------- */
+#define UOTGHS_HSTADDR2_HSTADDRP4_Pos 0
+#define UOTGHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP4(value) ((UOTGHS_HSTADDR2_HSTADDRP4_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP4_Pos)))
+#define UOTGHS_HSTADDR2_HSTADDRP5_Pos 8
+#define UOTGHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP5(value) ((UOTGHS_HSTADDR2_HSTADDRP5_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP5_Pos)))
+#define UOTGHS_HSTADDR2_HSTADDRP6_Pos 16
+#define UOTGHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP6(value) ((UOTGHS_HSTADDR2_HSTADDRP6_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP6_Pos)))
+#define UOTGHS_HSTADDR2_HSTADDRP7_Pos 24
+#define UOTGHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */
+#define UOTGHS_HSTADDR2_HSTADDRP7(value) ((UOTGHS_HSTADDR2_HSTADDRP7_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP7_Pos)))
+/* -------- UOTGHS_HSTADDR3 : (UOTGHS Offset: 0x042C) Host Address 3 Register -------- */
+#define UOTGHS_HSTADDR3_HSTADDRP8_Pos 0
+#define UOTGHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */
+#define UOTGHS_HSTADDR3_HSTADDRP8(value) ((UOTGHS_HSTADDR3_HSTADDRP8_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP8_Pos)))
+#define UOTGHS_HSTADDR3_HSTADDRP9_Pos 8
+#define UOTGHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */
+#define UOTGHS_HSTADDR3_HSTADDRP9(value) ((UOTGHS_HSTADDR3_HSTADDRP9_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP9_Pos)))
+/* -------- UOTGHS_HSTPIPCFG[10] : (UOTGHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */
+#define UOTGHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Memory Allocate */
+#define UOTGHS_HSTPIPCFG_PBK_Pos 2
+#define UOTGHS_HSTPIPCFG_PBK_Msk (0x3u << UOTGHS_HSTPIPCFG_PBK_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Banks */
+#define   UOTGHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Single-bank pipe */
+#define   UOTGHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Double-bank pipe */
+#define   UOTGHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Triple-bank pipe */
+#define UOTGHS_HSTPIPCFG_PSIZE_Pos 4
+#define UOTGHS_HSTPIPCFG_PSIZE_Msk (0x7u << UOTGHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Size */
+#define   UOTGHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 8 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 16 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 32 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 64 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 128 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 256 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 512 bytes */
+#define   UOTGHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 1024 bytes */
+#define UOTGHS_HSTPIPCFG_PTOKEN_Pos 8
+#define UOTGHS_HSTPIPCFG_PTOKEN_Msk (0x3u << UOTGHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Token */
+#define   UOTGHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) SETUP */
+#define   UOTGHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) IN */
+#define   UOTGHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) OUT */
+#define UOTGHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (UOTGHS_HSTPIPCFG[10]) Automatic Switch */
+#define UOTGHS_HSTPIPCFG_PTYPE_Pos 12
+#define UOTGHS_HSTPIPCFG_PTYPE_Msk (0x3u << UOTGHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Type */
+#define   UOTGHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Control */
+#define   UOTGHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Isochronous */
+#define   UOTGHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Bulk */
+#define   UOTGHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Interrupt */
+#define UOTGHS_HSTPIPCFG_PEPNUM_Pos 16
+#define UOTGHS_HSTPIPCFG_PEPNUM_Msk (0xfu << UOTGHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Endpoint Number */
+#define UOTGHS_HSTPIPCFG_PEPNUM(value) ((UOTGHS_HSTPIPCFG_PEPNUM_Msk & ((value) << UOTGHS_HSTPIPCFG_PEPNUM_Pos)))
+#define UOTGHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (UOTGHS_HSTPIPCFG[10]) Ping Enable */
+#define UOTGHS_HSTPIPCFG_INTFRQ_Pos 24
+#define UOTGHS_HSTPIPCFG_INTFRQ_Msk (0xffu << UOTGHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */
+#define UOTGHS_HSTPIPCFG_INTFRQ(value) ((UOTGHS_HSTPIPCFG_INTFRQ_Msk & ((value) << UOTGHS_HSTPIPCFG_INTFRQ_Pos)))
+#define UOTGHS_HSTPIPCFG_BINTERVAL_Pos 24
+#define UOTGHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << UOTGHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) bInterval parameter for the Bulk-Out/Ping transaction */
+#define UOTGHS_HSTPIPCFG_BINTERVAL(value) ((UOTGHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << UOTGHS_HSTPIPCFG_BINTERVAL_Pos)))
+/* -------- UOTGHS_HSTPIPISR[10] : (UOTGHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */
+#define UOTGHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (UOTGHS_HSTPIPISR[10]) Received IN Data Interrupt */
+#define UOTGHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (UOTGHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */
+#define UOTGHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */
+#define UOTGHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[10]) Underflow Interrupt */
+#define UOTGHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (UOTGHS_HSTPIPISR[10]) Pipe Error Interrupt */
+#define UOTGHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (UOTGHS_HSTPIPISR[10]) NAKed Interrupt */
+#define UOTGHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_HSTPIPISR[10]) Overflow Interrupt */
+#define UOTGHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[10]) Received STALLed Interrupt */
+#define UOTGHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[10]) CRC Error Interrupt */
+#define UOTGHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (UOTGHS_HSTPIPISR[10]) Short Packet Interrupt */
+#define UOTGHS_HSTPIPISR_DTSEQ_Pos 8
+#define UOTGHS_HSTPIPISR_DTSEQ_Msk (0x3u << UOTGHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Data Toggle Sequence */
+#define   UOTGHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_HSTPIPISR[10]) Data0 toggle sequence */
+#define   UOTGHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_HSTPIPISR[10]) Data1 toggle sequence */
+#define UOTGHS_HSTPIPISR_NBUSYBK_Pos 12
+#define UOTGHS_HSTPIPISR_NBUSYBK_Msk (0x3u << UOTGHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Number of Busy Banks */
+#define   UOTGHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 0 busy bank (all banks free) */
+#define   UOTGHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 1 busy bank */
+#define   UOTGHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 2 busy banks */
+#define   UOTGHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 3 busy banks */
+#define UOTGHS_HSTPIPISR_CURRBK_Pos 14
+#define UOTGHS_HSTPIPISR_CURRBK_Msk (0x3u << UOTGHS_HSTPIPISR_CURRBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Current Bank */
+#define   UOTGHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank0 */
+#define   UOTGHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank1 */
+#define   UOTGHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank2 */
+#define UOTGHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_HSTPIPISR[10]) Read-write Allowed */
+#define UOTGHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_HSTPIPISR[10]) Configuration OK Status */
+#define UOTGHS_HSTPIPISR_PBYCT_Pos 20
+#define UOTGHS_HSTPIPISR_PBYCT_Msk (0x7ffu << UOTGHS_HSTPIPISR_PBYCT_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Pipe Byte Count */
+/* -------- UOTGHS_HSTPIPICR[10] : (UOTGHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */
+#define UOTGHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */
+#define UOTGHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */
+#define UOTGHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */
+#define UOTGHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[10]) Underflow Interrupt Clear */
+#define UOTGHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPICR[10]) NAKed Interrupt Clear */
+#define UOTGHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPICR[10]) Overflow Interrupt Clear */
+#define UOTGHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */
+#define UOTGHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[10]) CRC Error Interrupt Clear */
+#define UOTGHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPICR[10]) Short Packet Interrupt Clear */
+/* -------- UOTGHS_HSTPIPIFR[10] : (UOTGHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */
+#define UOTGHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */
+#define UOTGHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */
+#define UOTGHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[10]) Underflow Interrupt Set */
+#define UOTGHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */
+#define UOTGHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIFR[10]) NAKed Interrupt Set */
+#define UOTGHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIFR[10]) Overflow Interrupt Set */
+#define UOTGHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */
+#define UOTGHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[10]) CRC Error Interrupt Set */
+#define UOTGHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIFR[10]) Short Packet Interrupt Set */
+#define UOTGHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIFR[10]) Number of Busy Banks Set */
+/* -------- UOTGHS_HSTPIPIMR[10] : (UOTGHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[10]) Underflow Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIMR[10]) NAKed Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIMR[10]) Overflow Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */
+#define UOTGHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIMR[10]) FIFO Control */
+#define UOTGHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */
+#define UOTGHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Freeze */
+#define UOTGHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIMR[10]) Reset Data Toggle */
+/* -------- UOTGHS_HSTPIPIER[10] : (UOTGHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */
+#define UOTGHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */
+#define UOTGHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */
+#define UOTGHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[10]) Underflow Interrupt Enable */
+#define UOTGHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */
+#define UOTGHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIER[10]) NAKed Interrupt Enable */
+#define UOTGHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIER[10]) Overflow Interrupt Enable */
+#define UOTGHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */
+#define UOTGHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[10]) CRC Error Interrupt Enable */
+#define UOTGHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIER[10]) Short Packet Interrupt Enable */
+#define UOTGHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIER[10]) Number of Busy Banks Enable */
+#define UOTGHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */
+#define UOTGHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Freeze Enable */
+#define UOTGHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIER[10]) Reset Data Toggle Enable */
+/* -------- UOTGHS_HSTPIPIDR[10] : (UOTGHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */
+#define UOTGHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[10]) Underflow Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIDR[10]) NAKed Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIDR[10]) Overflow Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */
+#define UOTGHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIDR[10]) Number of Busy Banks Disable */
+#define UOTGHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIDR[10]) FIFO Control Disable */
+#define UOTGHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */
+#define UOTGHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Freeze Disable */
+/* -------- UOTGHS_HSTPIPINRQ[10] : (UOTGHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */
+#define UOTGHS_HSTPIPINRQ_INRQ_Pos 0
+#define UOTGHS_HSTPIPINRQ_INRQ_Msk (0xffu << UOTGHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (UOTGHS_HSTPIPINRQ[10]) IN Request Number before Freeze */
+#define UOTGHS_HSTPIPINRQ_INRQ(value) ((UOTGHS_HSTPIPINRQ_INRQ_Msk & ((value) << UOTGHS_HSTPIPINRQ_INRQ_Pos)))
+#define UOTGHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (UOTGHS_HSTPIPINRQ[10]) IN Request Mode */
+/* -------- UOTGHS_HSTPIPERR[10] : (UOTGHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */
+#define UOTGHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (UOTGHS_HSTPIPERR[10]) Data Toggle Error */
+#define UOTGHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (UOTGHS_HSTPIPERR[10]) Data PID Error */
+#define UOTGHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (UOTGHS_HSTPIPERR[10]) PID Error */
+#define UOTGHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (UOTGHS_HSTPIPERR[10]) Time-Out Error */
+#define UOTGHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (UOTGHS_HSTPIPERR[10]) CRC16 Error */
+#define UOTGHS_HSTPIPERR_COUNTER_Pos 5
+#define UOTGHS_HSTPIPERR_COUNTER_Msk (0x3u << UOTGHS_HSTPIPERR_COUNTER_Pos) /**< \brief (UOTGHS_HSTPIPERR[10]) Error Counter */
+#define UOTGHS_HSTPIPERR_COUNTER(value) ((UOTGHS_HSTPIPERR_COUNTER_Msk & ((value) << UOTGHS_HSTPIPERR_COUNTER_Pos)))
+/* -------- UOTGHS_HSTDMANXTDSC : (UOTGHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_HSTDMANXTDSC) Next Descriptor Address */
+#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))
+/* -------- UOTGHS_HSTDMAADDRESS : (UOTGHS Offset: N/A) Host DMA Channel Address Register -------- */
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos 0
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_HSTDMAADDRESS) Buffer Address */
+#define UOTGHS_HSTDMAADDRESS_BUFF_ADD(value) ((UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos)))
+/* -------- UOTGHS_HSTDMACONTROL : (UOTGHS Offset: N/A) Host DMA Channel Control Register -------- */
+#define UOTGHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMACONTROL) Channel Enable Command */
+#define UOTGHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
+#define UOTGHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Enable (Control) */
+#define UOTGHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Enable Control */
+#define UOTGHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Interrupt Enable */
+#define UOTGHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Interrupt Enable */
+#define UOTGHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */
+#define UOTGHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_HSTDMACONTROL) Burst Lock Enable */
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */
+#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))
+/* -------- UOTGHS_HSTDMASTATUS : (UOTGHS Offset: N/A) Host DMA Channel Status Register -------- */
+#define UOTGHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Enable Status */
+#define UOTGHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Active Status */
+#define UOTGHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Transfer Status */
+#define UOTGHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Buffer Status */
+#define UOTGHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_HSTDMASTATUS) Descriptor Loaded Status */
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos 16
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_HSTDMASTATUS) Buffer Byte Count */
+#define UOTGHS_HSTDMASTATUS_BUFF_COUNT(value) ((UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos)))
+/* -------- UOTGHS_CTRL : (UOTGHS Offset: 0x0800) General Control Register -------- */
+#define UOTGHS_CTRL_IDTE (0x1u << 0) /**< \brief (UOTGHS_CTRL) ID Transition Interrupt Enable */
+#define UOTGHS_CTRL_VBUSTE (0x1u << 1) /**< \brief (UOTGHS_CTRL) VBus Transition Interrupt Enable */
+#define UOTGHS_CTRL_SRPE (0x1u << 2) /**< \brief (UOTGHS_CTRL) SRP Interrupt Enable */
+#define UOTGHS_CTRL_VBERRE (0x1u << 3) /**< \brief (UOTGHS_CTRL) VBus Error Interrupt Enable */
+#define UOTGHS_CTRL_BCERRE (0x1u << 4) /**< \brief (UOTGHS_CTRL) B-Connection Error Interrupt Enable */
+#define UOTGHS_CTRL_ROLEEXE (0x1u << 5) /**< \brief (UOTGHS_CTRL) Role Exchange Interrupt Enable */
+#define UOTGHS_CTRL_HNPERRE (0x1u << 6) /**< \brief (UOTGHS_CTRL) HNP Error Interrupt Enable */
+#define UOTGHS_CTRL_STOE (0x1u << 7) /**< \brief (UOTGHS_CTRL) Suspend Time-Out Interrupt Enable */
+#define UOTGHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (UOTGHS_CTRL) VBus Hardware Control */
+#define UOTGHS_CTRL_SRPSEL (0x1u << 9) /**< \brief (UOTGHS_CTRL) SRP Selection */
+#define UOTGHS_CTRL_SRPREQ (0x1u << 10) /**< \brief (UOTGHS_CTRL) SRP Request */
+#define UOTGHS_CTRL_HNPREQ (0x1u << 11) /**< \brief (UOTGHS_CTRL) HNP Request */
+#define UOTGHS_CTRL_OTGPADE (0x1u << 12) /**< \brief (UOTGHS_CTRL) OTG Pad Enable */
+#define UOTGHS_CTRL_VBUSPO (0x1u << 13) /**< \brief (UOTGHS_CTRL) VBus Polarity Off */
+#define UOTGHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (UOTGHS_CTRL) Freeze USB Clock */
+#define UOTGHS_CTRL_USBE (0x1u << 15) /**< \brief (UOTGHS_CTRL) UOTGHS Enable */
+#define UOTGHS_CTRL_TIMVALUE_Pos 16
+#define UOTGHS_CTRL_TIMVALUE_Msk (0x3u << UOTGHS_CTRL_TIMVALUE_Pos) /**< \brief (UOTGHS_CTRL) Timer Value */
+#define UOTGHS_CTRL_TIMVALUE(value) ((UOTGHS_CTRL_TIMVALUE_Msk & ((value) << UOTGHS_CTRL_TIMVALUE_Pos)))
+#define UOTGHS_CTRL_TIMPAGE_Pos 20
+#define UOTGHS_CTRL_TIMPAGE_Msk (0x3u << UOTGHS_CTRL_TIMPAGE_Pos) /**< \brief (UOTGHS_CTRL) Timer Page */
+#define UOTGHS_CTRL_TIMPAGE(value) ((UOTGHS_CTRL_TIMPAGE_Msk & ((value) << UOTGHS_CTRL_TIMPAGE_Pos)))
+#define UOTGHS_CTRL_UNLOCK (0x1u << 22) /**< \brief (UOTGHS_CTRL) Timer Access Unlock */
+#define UOTGHS_CTRL_UIDE (0x1u << 24) /**< \brief (UOTGHS_CTRL) UOTGID Pin Enable */
+#define   UOTGHS_CTRL_UIDE_UIMOD (0x0u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UIMOD bit. */
+#define   UOTGHS_CTRL_UIDE_UOTGID (0x1u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UOTGID input pin. */
+#define UOTGHS_CTRL_UIMOD (0x1u << 25) /**< \brief (UOTGHS_CTRL) UOTGHS Mode */
+#define   UOTGHS_CTRL_UIMOD_Host (0x0u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB host mode. */
+#define   UOTGHS_CTRL_UIMOD_Device (0x1u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB device mode. */
+/* -------- UOTGHS_SR : (UOTGHS Offset: 0x0804) General Status Register -------- */
+#define UOTGHS_SR_IDTI (0x1u << 0) /**< \brief (UOTGHS_SR) ID Transition Interrupt */
+#define UOTGHS_SR_VBUSTI (0x1u << 1) /**< \brief (UOTGHS_SR) VBus Transition Interrupt */
+#define UOTGHS_SR_SRPI (0x1u << 2) /**< \brief (UOTGHS_SR) SRP Interrupt */
+#define UOTGHS_SR_VBERRI (0x1u << 3) /**< \brief (UOTGHS_SR) VBus Error Interrupt */
+#define UOTGHS_SR_BCERRI (0x1u << 4) /**< \brief (UOTGHS_SR) B-Connection Error Interrupt */
+#define UOTGHS_SR_ROLEEXI (0x1u << 5) /**< \brief (UOTGHS_SR) Role Exchange Interrupt */
+#define UOTGHS_SR_HNPERRI (0x1u << 6) /**< \brief (UOTGHS_SR) HNP Error Interrupt */
+#define UOTGHS_SR_STOI (0x1u << 7) /**< \brief (UOTGHS_SR) Suspend Time-Out Interrupt */
+#define UOTGHS_SR_VBUSRQ (0x1u << 9) /**< \brief (UOTGHS_SR) VBus Request */
+#define UOTGHS_SR_ID (0x1u << 10) /**< \brief (UOTGHS_SR) UOTGID Pin State */
+#define UOTGHS_SR_VBUS (0x1u << 11) /**< \brief (UOTGHS_SR) VBus Level */
+#define UOTGHS_SR_SPEED_Pos 12
+#define UOTGHS_SR_SPEED_Msk (0x3u << UOTGHS_SR_SPEED_Pos) /**< \brief (UOTGHS_SR) Speed Status */
+#define   UOTGHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (UOTGHS_SR) Full-Speed mode */
+#define   UOTGHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (UOTGHS_SR) High-Speed mode */
+#define   UOTGHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (UOTGHS_SR) Low-Speed mode */
+#define UOTGHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (UOTGHS_SR) UTMI Clock Usable */
+/* -------- UOTGHS_SCR : (UOTGHS Offset: 0x0808) General Status Clear Register -------- */
+#define UOTGHS_SCR_IDTIC (0x1u << 0) /**< \brief (UOTGHS_SCR) ID Transition Interrupt Clear */
+#define UOTGHS_SCR_VBUSTIC (0x1u << 1) /**< \brief (UOTGHS_SCR) VBus Transition Interrupt Clear */
+#define UOTGHS_SCR_SRPIC (0x1u << 2) /**< \brief (UOTGHS_SCR) SRP Interrupt Clear */
+#define UOTGHS_SCR_VBERRIC (0x1u << 3) /**< \brief (UOTGHS_SCR) VBus Error Interrupt Clear */
+#define UOTGHS_SCR_BCERRIC (0x1u << 4) /**< \brief (UOTGHS_SCR) B-Connection Error Interrupt Clear */
+#define UOTGHS_SCR_ROLEEXIC (0x1u << 5) /**< \brief (UOTGHS_SCR) Role Exchange Interrupt Clear */
+#define UOTGHS_SCR_HNPERRIC (0x1u << 6) /**< \brief (UOTGHS_SCR) HNP Error Interrupt Clear */
+#define UOTGHS_SCR_STOIC (0x1u << 7) /**< \brief (UOTGHS_SCR) Suspend Time-Out Interrupt Clear */
+#define UOTGHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (UOTGHS_SCR) VBus Request Clear */
+/* -------- UOTGHS_SFR : (UOTGHS Offset: 0x080C) General Status Set Register -------- */
+#define UOTGHS_SFR_IDTIS (0x1u << 0) /**< \brief (UOTGHS_SFR) ID Transition Interrupt Set */
+#define UOTGHS_SFR_VBUSTIS (0x1u << 1) /**< \brief (UOTGHS_SFR) VBus Transition Interrupt Set */
+#define UOTGHS_SFR_SRPIS (0x1u << 2) /**< \brief (UOTGHS_SFR) SRP Interrupt Set */
+#define UOTGHS_SFR_VBERRIS (0x1u << 3) /**< \brief (UOTGHS_SFR) VBus Error Interrupt Set */
+#define UOTGHS_SFR_BCERRIS (0x1u << 4) /**< \brief (UOTGHS_SFR) B-Connection Error Interrupt Set */
+#define UOTGHS_SFR_ROLEEXIS (0x1u << 5) /**< \brief (UOTGHS_SFR) Role Exchange Interrupt Set */
+#define UOTGHS_SFR_HNPERRIS (0x1u << 6) /**< \brief (UOTGHS_SFR) HNP Error Interrupt Set */
+#define UOTGHS_SFR_STOIS (0x1u << 7) /**< \brief (UOTGHS_SFR) Suspend Time-Out Interrupt Set */
+#define UOTGHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (UOTGHS_SFR) VBus Request Set */
+/* -------- UOTGHS_FSM : (UOTGHS Offset: 0x082C) General Finite State Machine Register -------- */
+#define UOTGHS_FSM_DRDSTATE_Pos 0
+#define UOTGHS_FSM_DRDSTATE_Msk (0xfu << UOTGHS_FSM_DRDSTATE_Pos) /**< \brief (UOTGHS_FSM)  */
+#define   UOTGHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (UOTGHS_FSM) This is the start state for A-devices (when the ID pin is 0) */
+#define   UOTGHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */
+#define   UOTGHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */
+#define   UOTGHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device that operates in Host mode is operational. */
+#define   UOTGHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (UOTGHS_FSM) The A-device operating as a host is in the suspend mode. */
+#define   UOTGHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (UOTGHS_FSM) The A-device operates as a peripheral. */
+#define   UOTGHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */
+#define   UOTGHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */
+#define   UOTGHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */
+#define   UOTGHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (UOTGHS_FSM) This is the start state for B-device (when the ID pin is 1). */
+#define   UOTGHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the peripheral. */
+#define   UOTGHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */
+#define   UOTGHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host. */
+#define   UOTGHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */
+#define   UOTGHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the Host. */
+#define   UOTGHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_UOTGHS_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_usart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_usart.h
new file mode 100644
index 0000000..5d2f235
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_usart.h
@@ -0,0 +1,396 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_USART_COMPONENT_
+#define _SAM3XA_USART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Usart hardware registers */
+typedef struct {
+  WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
+  RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
+  WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+  WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+  RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+  RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+  RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+  WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+  RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+  RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+  RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+  RoReg Reserved1[5];
+  RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+  RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+  RoReg Reserved2[1];
+  RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+  RwReg US_MAN;        /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
+  RwReg US_LINMR;      /**< \brief (Usart Offset: 0x0054) LIN Mode Register */
+  RwReg US_LINIR;      /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */
+  RoReg Reserved3[34];
+  RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+  RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[5];
+  RwReg US_RPR;        /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+  RwReg US_RCR;        /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+  RwReg US_TPR;        /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+  RwReg US_TCR;        /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+  RwReg US_RNPR;       /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+  RwReg US_RNCR;       /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+  RwReg US_TNPR;       /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg US_TNCR;       /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg US_PTCR;       /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+  RoReg US_PTSR;       /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */
+#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
+#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define   US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN Master */
+#define   US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave */
+#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */
+#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */
+#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */
+#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
+#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */
+#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */
+#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */
+#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */
+#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */
+#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */
+#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */
+#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
+#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */
+#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */
+#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */
+#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */
+#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */
+#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */
+#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */
+#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
+#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */
+#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */
+#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */
+#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */
+#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt */
+#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received */
+#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received */
+#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
+#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error */
+#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error */
+#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error */
+#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error */
+#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
+#define US_MAN_TX_PL_Pos 0
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
+#define US_MAN_TX_PP_Pos 8
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
+#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
+#define US_MAN_RX_PL_Pos 16
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
+#define US_MAN_RX_PP_Pos 24
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
+#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN)  */
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
+/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */
+#define US_LINMR_NACT_Pos 0
+#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */
+#define   US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */
+#define   US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */
+#define   US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */
+#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */
+#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */
+#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */
+#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */
+#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */
+#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */
+#define US_LINMR_DLC_Pos 8
+#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */
+#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))
+#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) PDC Mode */
+/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */
+#define US_LINIR_IDCHR_Pos 0
+#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */
+#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_USART_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_wdt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_wdt.h
new file mode 100644
index 0000000..ded5d85
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/component/component_wdt.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_WDT_COMPONENT_
+#define _SAM3XA_WDT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM3XA_WDT Watchdog Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Wdt hardware registers */
+typedef struct {
+  WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+  RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+  RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAM3XA_WDT_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_adc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_adc.h
new file mode 100644
index 0000000..a0f1280
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_adc.h
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_ADC_INSTANCE_
+#define _SAM3XA_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CR               (0x400C0000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR               (0x400C0004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1            (0x400C0008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2            (0x400C000CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER             (0x400C0010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR             (0x400C0014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR             (0x400C0018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR             (0x400C0020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER              (0x400C0024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR              (0x400C0028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR              (0x400C002CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR              (0x400C0030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER             (0x400C003CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR              (0x400C0040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR              (0x400C0044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR              (0x400C0048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR              (0x400C004CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR              (0x400C0050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR              (0x400C0094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR             (0x400C00E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR             (0x400C00E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR              (0x400C0100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR              (0x400C0104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR             (0x400C0110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR             (0x400C0114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR             (0x400C0120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR             (0x400C0124U) /**< \brief (ADC) Transfer Status Register */
+#else
+#define REG_ADC_CR      (*(WoReg*)0x400C0000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR      (*(RwReg*)0x400C0004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1   (*(RwReg*)0x400C0008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2   (*(RwReg*)0x400C000CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER    (*(WoReg*)0x400C0010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR    (*(WoReg*)0x400C0014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR    (*(RoReg*)0x400C0018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR    (*(RoReg*)0x400C0020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER     (*(WoReg*)0x400C0024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR     (*(WoReg*)0x400C0028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR     (*(RoReg*)0x400C002CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR     (*(RoReg*)0x400C0030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER    (*(RoReg*)0x400C003CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR     (*(RwReg*)0x400C0040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR     (*(RwReg*)0x400C0044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR     (*(RwReg*)0x400C0048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR     (*(RwReg*)0x400C004CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR     (*(RoReg*)0x400C0050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR     (*(RwReg*)0x400C0094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR    (*(RwReg*)0x400C00E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR    (*(RoReg*)0x400C00E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR     (*(RwReg*)0x400C0100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR     (*(RwReg*)0x400C0104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR    (*(RwReg*)0x400C0110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR    (*(RwReg*)0x400C0114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR    (*(WoReg*)0x400C0120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR    (*(RoReg*)0x400C0124U) /**< \brief (ADC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_ADC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_can0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_can0.h
new file mode 100644
index 0000000..c9b52e8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_can0.h
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CAN0_INSTANCE_
+#define _SAM3XA_CAN0_INSTANCE_
+
+/* ========== Register definition for CAN0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CAN0_MR               (0x400B4000U) /**< \brief (CAN0) Mode Register */
+#define REG_CAN0_IER              (0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */
+#define REG_CAN0_IDR              (0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */
+#define REG_CAN0_IMR              (0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */
+#define REG_CAN0_SR               (0x400B4010U) /**< \brief (CAN0) Status Register */
+#define REG_CAN0_BR               (0x400B4014U) /**< \brief (CAN0) Baudrate Register */
+#define REG_CAN0_TIM              (0x400B4018U) /**< \brief (CAN0) Timer Register */
+#define REG_CAN0_TIMESTP          (0x400B401CU) /**< \brief (CAN0) Timestamp Register */
+#define REG_CAN0_ECR              (0x400B4020U) /**< \brief (CAN0) Error Counter Register */
+#define REG_CAN0_TCR              (0x400B4024U) /**< \brief (CAN0) Transfer Command Register */
+#define REG_CAN0_ACR              (0x400B4028U) /**< \brief (CAN0) Abort Command Register */
+#define REG_CAN0_WPMR             (0x400B40E4U) /**< \brief (CAN0) Write Protect Mode Register */
+#define REG_CAN0_WPSR             (0x400B40E8U) /**< \brief (CAN0) Write Protect Status Register */
+#define REG_CAN0_MMR0             (0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */
+#define REG_CAN0_MAM0             (0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN0_MID0             (0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */
+#define REG_CAN0_MFID0            (0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN0_MSR0             (0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */
+#define REG_CAN0_MDL0             (0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN0_MDH0             (0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */
+#define REG_CAN0_MCR0             (0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */
+#define REG_CAN0_MMR1             (0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */
+#define REG_CAN0_MAM1             (0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN0_MID1             (0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */
+#define REG_CAN0_MFID1            (0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN0_MSR1             (0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */
+#define REG_CAN0_MDL1             (0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN0_MDH1             (0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */
+#define REG_CAN0_MCR1             (0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */
+#define REG_CAN0_MMR2             (0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */
+#define REG_CAN0_MAM2             (0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN0_MID2             (0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */
+#define REG_CAN0_MFID2            (0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN0_MSR2             (0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */
+#define REG_CAN0_MDL2             (0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN0_MDH2             (0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */
+#define REG_CAN0_MCR2             (0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */
+#define REG_CAN0_MMR3             (0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */
+#define REG_CAN0_MAM3             (0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN0_MID3             (0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */
+#define REG_CAN0_MFID3            (0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN0_MSR3             (0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */
+#define REG_CAN0_MDL3             (0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN0_MDH3             (0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */
+#define REG_CAN0_MCR3             (0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */
+#define REG_CAN0_MMR4             (0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */
+#define REG_CAN0_MAM4             (0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN0_MID4             (0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */
+#define REG_CAN0_MFID4            (0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN0_MSR4             (0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */
+#define REG_CAN0_MDL4             (0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN0_MDH4             (0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */
+#define REG_CAN0_MCR4             (0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */
+#define REG_CAN0_MMR5             (0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */
+#define REG_CAN0_MAM5             (0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN0_MID5             (0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */
+#define REG_CAN0_MFID5            (0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN0_MSR5             (0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */
+#define REG_CAN0_MDL5             (0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN0_MDH5             (0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */
+#define REG_CAN0_MCR5             (0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */
+#define REG_CAN0_MMR6             (0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */
+#define REG_CAN0_MAM6             (0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN0_MID6             (0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */
+#define REG_CAN0_MFID6            (0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN0_MSR6             (0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */
+#define REG_CAN0_MDL6             (0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN0_MDH6             (0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */
+#define REG_CAN0_MCR6             (0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */
+#define REG_CAN0_MMR7             (0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */
+#define REG_CAN0_MAM7             (0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN0_MID7             (0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */
+#define REG_CAN0_MFID7            (0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN0_MSR7             (0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */
+#define REG_CAN0_MDL7             (0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN0_MDH7             (0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */
+#define REG_CAN0_MCR7             (0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */
+#else
+#define REG_CAN0_MR      (*(RwReg*)0x400B4000U) /**< \brief (CAN0) Mode Register */
+#define REG_CAN0_IER     (*(WoReg*)0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */
+#define REG_CAN0_IDR     (*(WoReg*)0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */
+#define REG_CAN0_IMR     (*(RoReg*)0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */
+#define REG_CAN0_SR      (*(RoReg*)0x400B4010U) /**< \brief (CAN0) Status Register */
+#define REG_CAN0_BR      (*(RwReg*)0x400B4014U) /**< \brief (CAN0) Baudrate Register */
+#define REG_CAN0_TIM     (*(RoReg*)0x400B4018U) /**< \brief (CAN0) Timer Register */
+#define REG_CAN0_TIMESTP (*(RoReg*)0x400B401CU) /**< \brief (CAN0) Timestamp Register */
+#define REG_CAN0_ECR     (*(RoReg*)0x400B4020U) /**< \brief (CAN0) Error Counter Register */
+#define REG_CAN0_TCR     (*(WoReg*)0x400B4024U) /**< \brief (CAN0) Transfer Command Register */
+#define REG_CAN0_ACR     (*(WoReg*)0x400B4028U) /**< \brief (CAN0) Abort Command Register */
+#define REG_CAN0_WPMR    (*(RwReg*)0x400B40E4U) /**< \brief (CAN0) Write Protect Mode Register */
+#define REG_CAN0_WPSR    (*(RoReg*)0x400B40E8U) /**< \brief (CAN0) Write Protect Status Register */
+#define REG_CAN0_MMR0    (*(RwReg*)0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */
+#define REG_CAN0_MAM0    (*(RwReg*)0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN0_MID0    (*(RwReg*)0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */
+#define REG_CAN0_MFID0   (*(RoReg*)0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN0_MSR0    (*(RoReg*)0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */
+#define REG_CAN0_MDL0    (*(RwReg*)0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN0_MDH0    (*(RwReg*)0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */
+#define REG_CAN0_MCR0    (*(WoReg*)0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */
+#define REG_CAN0_MMR1    (*(RwReg*)0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */
+#define REG_CAN0_MAM1    (*(RwReg*)0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN0_MID1    (*(RwReg*)0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */
+#define REG_CAN0_MFID1   (*(RoReg*)0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN0_MSR1    (*(RoReg*)0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */
+#define REG_CAN0_MDL1    (*(RwReg*)0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN0_MDH1    (*(RwReg*)0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */
+#define REG_CAN0_MCR1    (*(WoReg*)0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */
+#define REG_CAN0_MMR2    (*(RwReg*)0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */
+#define REG_CAN0_MAM2    (*(RwReg*)0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN0_MID2    (*(RwReg*)0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */
+#define REG_CAN0_MFID2   (*(RoReg*)0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN0_MSR2    (*(RoReg*)0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */
+#define REG_CAN0_MDL2    (*(RwReg*)0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN0_MDH2    (*(RwReg*)0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */
+#define REG_CAN0_MCR2    (*(WoReg*)0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */
+#define REG_CAN0_MMR3    (*(RwReg*)0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */
+#define REG_CAN0_MAM3    (*(RwReg*)0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN0_MID3    (*(RwReg*)0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */
+#define REG_CAN0_MFID3   (*(RoReg*)0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN0_MSR3    (*(RoReg*)0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */
+#define REG_CAN0_MDL3    (*(RwReg*)0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN0_MDH3    (*(RwReg*)0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */
+#define REG_CAN0_MCR3    (*(WoReg*)0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */
+#define REG_CAN0_MMR4    (*(RwReg*)0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */
+#define REG_CAN0_MAM4    (*(RwReg*)0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN0_MID4    (*(RwReg*)0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */
+#define REG_CAN0_MFID4   (*(RoReg*)0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN0_MSR4    (*(RoReg*)0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */
+#define REG_CAN0_MDL4    (*(RwReg*)0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN0_MDH4    (*(RwReg*)0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */
+#define REG_CAN0_MCR4    (*(WoReg*)0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */
+#define REG_CAN0_MMR5    (*(RwReg*)0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */
+#define REG_CAN0_MAM5    (*(RwReg*)0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN0_MID5    (*(RwReg*)0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */
+#define REG_CAN0_MFID5   (*(RoReg*)0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN0_MSR5    (*(RoReg*)0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */
+#define REG_CAN0_MDL5    (*(RwReg*)0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN0_MDH5    (*(RwReg*)0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */
+#define REG_CAN0_MCR5    (*(WoReg*)0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */
+#define REG_CAN0_MMR6    (*(RwReg*)0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */
+#define REG_CAN0_MAM6    (*(RwReg*)0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN0_MID6    (*(RwReg*)0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */
+#define REG_CAN0_MFID6   (*(RoReg*)0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN0_MSR6    (*(RoReg*)0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */
+#define REG_CAN0_MDL6    (*(RwReg*)0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN0_MDH6    (*(RwReg*)0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */
+#define REG_CAN0_MCR6    (*(WoReg*)0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */
+#define REG_CAN0_MMR7    (*(RwReg*)0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */
+#define REG_CAN0_MAM7    (*(RwReg*)0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN0_MID7    (*(RwReg*)0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */
+#define REG_CAN0_MFID7   (*(RoReg*)0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN0_MSR7    (*(RoReg*)0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */
+#define REG_CAN0_MDL7    (*(RwReg*)0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN0_MDH7    (*(RwReg*)0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */
+#define REG_CAN0_MCR7    (*(WoReg*)0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_CAN0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_can1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_can1.h
new file mode 100644
index 0000000..ee8f8da
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_can1.h
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CAN1_INSTANCE_
+#define _SAM3XA_CAN1_INSTANCE_
+
+/* ========== Register definition for CAN1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CAN1_MR               (0x400B8000U) /**< \brief (CAN1) Mode Register */
+#define REG_CAN1_IER              (0x400B8004U) /**< \brief (CAN1) Interrupt Enable Register */
+#define REG_CAN1_IDR              (0x400B8008U) /**< \brief (CAN1) Interrupt Disable Register */
+#define REG_CAN1_IMR              (0x400B800CU) /**< \brief (CAN1) Interrupt Mask Register */
+#define REG_CAN1_SR               (0x400B8010U) /**< \brief (CAN1) Status Register */
+#define REG_CAN1_BR               (0x400B8014U) /**< \brief (CAN1) Baudrate Register */
+#define REG_CAN1_TIM              (0x400B8018U) /**< \brief (CAN1) Timer Register */
+#define REG_CAN1_TIMESTP          (0x400B801CU) /**< \brief (CAN1) Timestamp Register */
+#define REG_CAN1_ECR              (0x400B8020U) /**< \brief (CAN1) Error Counter Register */
+#define REG_CAN1_TCR              (0x400B8024U) /**< \brief (CAN1) Transfer Command Register */
+#define REG_CAN1_ACR              (0x400B8028U) /**< \brief (CAN1) Abort Command Register */
+#define REG_CAN1_WPMR             (0x400B80E4U) /**< \brief (CAN1) Write Protect Mode Register */
+#define REG_CAN1_WPSR             (0x400B80E8U) /**< \brief (CAN1) Write Protect Status Register */
+#define REG_CAN1_MMR0             (0x400B8200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */
+#define REG_CAN1_MAM0             (0x400B8204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN1_MID0             (0x400B8208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */
+#define REG_CAN1_MFID0            (0x400B820CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN1_MSR0             (0x400B8210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */
+#define REG_CAN1_MDL0             (0x400B8214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN1_MDH0             (0x400B8218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */
+#define REG_CAN1_MCR0             (0x400B821CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */
+#define REG_CAN1_MMR1             (0x400B8220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */
+#define REG_CAN1_MAM1             (0x400B8224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN1_MID1             (0x400B8228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */
+#define REG_CAN1_MFID1            (0x400B822CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN1_MSR1             (0x400B8230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */
+#define REG_CAN1_MDL1             (0x400B8234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN1_MDH1             (0x400B8238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */
+#define REG_CAN1_MCR1             (0x400B823CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */
+#define REG_CAN1_MMR2             (0x400B8240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */
+#define REG_CAN1_MAM2             (0x400B8244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN1_MID2             (0x400B8248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */
+#define REG_CAN1_MFID2            (0x400B824CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN1_MSR2             (0x400B8250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */
+#define REG_CAN1_MDL2             (0x400B8254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN1_MDH2             (0x400B8258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */
+#define REG_CAN1_MCR2             (0x400B825CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */
+#define REG_CAN1_MMR3             (0x400B8260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */
+#define REG_CAN1_MAM3             (0x400B8264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN1_MID3             (0x400B8268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */
+#define REG_CAN1_MFID3            (0x400B826CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN1_MSR3             (0x400B8270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */
+#define REG_CAN1_MDL3             (0x400B8274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN1_MDH3             (0x400B8278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */
+#define REG_CAN1_MCR3             (0x400B827CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */
+#define REG_CAN1_MMR4             (0x400B8280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */
+#define REG_CAN1_MAM4             (0x400B8284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN1_MID4             (0x400B8288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */
+#define REG_CAN1_MFID4            (0x400B828CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN1_MSR4             (0x400B8290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */
+#define REG_CAN1_MDL4             (0x400B8294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN1_MDH4             (0x400B8298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */
+#define REG_CAN1_MCR4             (0x400B829CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */
+#define REG_CAN1_MMR5             (0x400B82A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */
+#define REG_CAN1_MAM5             (0x400B82A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN1_MID5             (0x400B82A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */
+#define REG_CAN1_MFID5            (0x400B82ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN1_MSR5             (0x400B82B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */
+#define REG_CAN1_MDL5             (0x400B82B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN1_MDH5             (0x400B82B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */
+#define REG_CAN1_MCR5             (0x400B82BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */
+#define REG_CAN1_MMR6             (0x400B82C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */
+#define REG_CAN1_MAM6             (0x400B82C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN1_MID6             (0x400B82C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */
+#define REG_CAN1_MFID6            (0x400B82CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN1_MSR6             (0x400B82D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */
+#define REG_CAN1_MDL6             (0x400B82D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN1_MDH6             (0x400B82D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */
+#define REG_CAN1_MCR6             (0x400B82DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */
+#define REG_CAN1_MMR7             (0x400B82E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */
+#define REG_CAN1_MAM7             (0x400B82E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN1_MID7             (0x400B82E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */
+#define REG_CAN1_MFID7            (0x400B82ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN1_MSR7             (0x400B82F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */
+#define REG_CAN1_MDL7             (0x400B82F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN1_MDH7             (0x400B82F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */
+#define REG_CAN1_MCR7             (0x400B82FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */
+#else
+#define REG_CAN1_MR      (*(RwReg*)0x400B8000U) /**< \brief (CAN1) Mode Register */
+#define REG_CAN1_IER     (*(WoReg*)0x400B8004U) /**< \brief (CAN1) Interrupt Enable Register */
+#define REG_CAN1_IDR     (*(WoReg*)0x400B8008U) /**< \brief (CAN1) Interrupt Disable Register */
+#define REG_CAN1_IMR     (*(RoReg*)0x400B800CU) /**< \brief (CAN1) Interrupt Mask Register */
+#define REG_CAN1_SR      (*(RoReg*)0x400B8010U) /**< \brief (CAN1) Status Register */
+#define REG_CAN1_BR      (*(RwReg*)0x400B8014U) /**< \brief (CAN1) Baudrate Register */
+#define REG_CAN1_TIM     (*(RoReg*)0x400B8018U) /**< \brief (CAN1) Timer Register */
+#define REG_CAN1_TIMESTP (*(RoReg*)0x400B801CU) /**< \brief (CAN1) Timestamp Register */
+#define REG_CAN1_ECR     (*(RoReg*)0x400B8020U) /**< \brief (CAN1) Error Counter Register */
+#define REG_CAN1_TCR     (*(WoReg*)0x400B8024U) /**< \brief (CAN1) Transfer Command Register */
+#define REG_CAN1_ACR     (*(WoReg*)0x400B8028U) /**< \brief (CAN1) Abort Command Register */
+#define REG_CAN1_WPMR    (*(RwReg*)0x400B80E4U) /**< \brief (CAN1) Write Protect Mode Register */
+#define REG_CAN1_WPSR    (*(RoReg*)0x400B80E8U) /**< \brief (CAN1) Write Protect Status Register */
+#define REG_CAN1_MMR0    (*(RwReg*)0x400B8200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */
+#define REG_CAN1_MAM0    (*(RwReg*)0x400B8204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */
+#define REG_CAN1_MID0    (*(RwReg*)0x400B8208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */
+#define REG_CAN1_MFID0   (*(RoReg*)0x400B820CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */
+#define REG_CAN1_MSR0    (*(RoReg*)0x400B8210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */
+#define REG_CAN1_MDL0    (*(RwReg*)0x400B8214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */
+#define REG_CAN1_MDH0    (*(RwReg*)0x400B8218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */
+#define REG_CAN1_MCR0    (*(WoReg*)0x400B821CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */
+#define REG_CAN1_MMR1    (*(RwReg*)0x400B8220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */
+#define REG_CAN1_MAM1    (*(RwReg*)0x400B8224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */
+#define REG_CAN1_MID1    (*(RwReg*)0x400B8228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */
+#define REG_CAN1_MFID1   (*(RoReg*)0x400B822CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */
+#define REG_CAN1_MSR1    (*(RoReg*)0x400B8230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */
+#define REG_CAN1_MDL1    (*(RwReg*)0x400B8234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */
+#define REG_CAN1_MDH1    (*(RwReg*)0x400B8238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */
+#define REG_CAN1_MCR1    (*(WoReg*)0x400B823CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */
+#define REG_CAN1_MMR2    (*(RwReg*)0x400B8240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */
+#define REG_CAN1_MAM2    (*(RwReg*)0x400B8244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */
+#define REG_CAN1_MID2    (*(RwReg*)0x400B8248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */
+#define REG_CAN1_MFID2   (*(RoReg*)0x400B824CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */
+#define REG_CAN1_MSR2    (*(RoReg*)0x400B8250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */
+#define REG_CAN1_MDL2    (*(RwReg*)0x400B8254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */
+#define REG_CAN1_MDH2    (*(RwReg*)0x400B8258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */
+#define REG_CAN1_MCR2    (*(WoReg*)0x400B825CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */
+#define REG_CAN1_MMR3    (*(RwReg*)0x400B8260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */
+#define REG_CAN1_MAM3    (*(RwReg*)0x400B8264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */
+#define REG_CAN1_MID3    (*(RwReg*)0x400B8268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */
+#define REG_CAN1_MFID3   (*(RoReg*)0x400B826CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */
+#define REG_CAN1_MSR3    (*(RoReg*)0x400B8270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */
+#define REG_CAN1_MDL3    (*(RwReg*)0x400B8274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */
+#define REG_CAN1_MDH3    (*(RwReg*)0x400B8278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */
+#define REG_CAN1_MCR3    (*(WoReg*)0x400B827CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */
+#define REG_CAN1_MMR4    (*(RwReg*)0x400B8280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */
+#define REG_CAN1_MAM4    (*(RwReg*)0x400B8284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */
+#define REG_CAN1_MID4    (*(RwReg*)0x400B8288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */
+#define REG_CAN1_MFID4   (*(RoReg*)0x400B828CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */
+#define REG_CAN1_MSR4    (*(RoReg*)0x400B8290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */
+#define REG_CAN1_MDL4    (*(RwReg*)0x400B8294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */
+#define REG_CAN1_MDH4    (*(RwReg*)0x400B8298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */
+#define REG_CAN1_MCR4    (*(WoReg*)0x400B829CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */
+#define REG_CAN1_MMR5    (*(RwReg*)0x400B82A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */
+#define REG_CAN1_MAM5    (*(RwReg*)0x400B82A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */
+#define REG_CAN1_MID5    (*(RwReg*)0x400B82A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */
+#define REG_CAN1_MFID5   (*(RoReg*)0x400B82ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */
+#define REG_CAN1_MSR5    (*(RoReg*)0x400B82B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */
+#define REG_CAN1_MDL5    (*(RwReg*)0x400B82B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */
+#define REG_CAN1_MDH5    (*(RwReg*)0x400B82B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */
+#define REG_CAN1_MCR5    (*(WoReg*)0x400B82BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */
+#define REG_CAN1_MMR6    (*(RwReg*)0x400B82C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */
+#define REG_CAN1_MAM6    (*(RwReg*)0x400B82C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */
+#define REG_CAN1_MID6    (*(RwReg*)0x400B82C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */
+#define REG_CAN1_MFID6   (*(RoReg*)0x400B82CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */
+#define REG_CAN1_MSR6    (*(RoReg*)0x400B82D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */
+#define REG_CAN1_MDL6    (*(RwReg*)0x400B82D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */
+#define REG_CAN1_MDH6    (*(RwReg*)0x400B82D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */
+#define REG_CAN1_MCR6    (*(WoReg*)0x400B82DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */
+#define REG_CAN1_MMR7    (*(RwReg*)0x400B82E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */
+#define REG_CAN1_MAM7    (*(RwReg*)0x400B82E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */
+#define REG_CAN1_MID7    (*(RwReg*)0x400B82E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */
+#define REG_CAN1_MFID7   (*(RoReg*)0x400B82ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */
+#define REG_CAN1_MSR7    (*(RoReg*)0x400B82F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */
+#define REG_CAN1_MDL7    (*(RwReg*)0x400B82F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */
+#define REG_CAN1_MDH7    (*(RwReg*)0x400B82F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */
+#define REG_CAN1_MCR7    (*(WoReg*)0x400B82FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_CAN1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_chipid.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_chipid.h
new file mode 100644
index 0000000..0715e43
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_chipid.h
@@ -0,0 +1,42 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_CHIPID_INSTANCE_
+#define _SAM3XA_CHIPID_INSTANCE_
+
+/* ========== Register definition for CHIPID peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CHIPID_CIDR          (0x400E0940U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID          (0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */
+#else
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0940U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_CHIPID_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_dacc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_dacc.h
new file mode 100644
index 0000000..1541cc7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_dacc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_DACC_INSTANCE_
+#define _SAM3XA_DACC_INSTANCE_
+
+/* ========== Register definition for DACC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DACC_CR            (0x400C8000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR            (0x400C8004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER          (0x400C8010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR          (0x400C8014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR          (0x400C8018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR           (0x400C8020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER           (0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR           (0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR           (0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR           (0x400C8030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR           (0x400C8094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR          (0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR          (0x400C80E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_TPR           (0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR           (0x400C810CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_TNPR          (0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR          (0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR          (0x400C8120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR          (0x400C8124U) /**< \brief (DACC) Transfer Status Register */
+#else
+#define REG_DACC_CR   (*(WoReg*)0x400C8000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR   (*(RwReg*)0x400C8004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER (*(WoReg*)0x400C8010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR (*(WoReg*)0x400C8014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR (*(RoReg*)0x400C8018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR  (*(WoReg*)0x400C8020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER  (*(WoReg*)0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR  (*(WoReg*)0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR  (*(RoReg*)0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR  (*(RoReg*)0x400C8030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR  (*(RwReg*)0x400C8094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR (*(RwReg*)0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR (*(RoReg*)0x400C80E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_TPR  (*(RwReg*)0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR  (*(RwReg*)0x400C810CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_TNPR (*(RwReg*)0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR (*(RwReg*)0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR (*(WoReg*)0x400C8120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR (*(RoReg*)0x400C8124U) /**< \brief (DACC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_DACC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_dmac.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_dmac.h
new file mode 100644
index 0000000..10e936b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_dmac.h
@@ -0,0 +1,138 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_DMAC_INSTANCE_
+#define _SAM3XA_DMAC_INSTANCE_
+
+/* ========== Register definition for DMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DMAC_GCFG            (0x400C4000U) /**< \brief (DMAC) DMAC Global Configuration Register */
+#define REG_DMAC_EN              (0x400C4004U) /**< \brief (DMAC) DMAC Enable Register */
+#define REG_DMAC_SREQ            (0x400C4008U) /**< \brief (DMAC) DMAC Software Single Request Register */
+#define REG_DMAC_CREQ            (0x400C400CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
+#define REG_DMAC_LAST            (0x400C4010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
+#define REG_DMAC_EBCIER          (0x400C4018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+#define REG_DMAC_EBCIDR          (0x400C401CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+#define REG_DMAC_EBCIMR          (0x400C4020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+#define REG_DMAC_EBCISR          (0x400C4024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+#define REG_DMAC_CHER            (0x400C4028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
+#define REG_DMAC_CHDR            (0x400C402CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
+#define REG_DMAC_CHSR            (0x400C4030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
+#define REG_DMAC_SADDR0          (0x400C403CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
+#define REG_DMAC_DADDR0          (0x400C4040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
+#define REG_DMAC_DSCR0           (0x400C4044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
+#define REG_DMAC_CTRLA0          (0x400C4048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
+#define REG_DMAC_CTRLB0          (0x400C404CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
+#define REG_DMAC_CFG0            (0x400C4050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
+#define REG_DMAC_SADDR1          (0x400C4064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
+#define REG_DMAC_DADDR1          (0x400C4068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
+#define REG_DMAC_DSCR1           (0x400C406CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
+#define REG_DMAC_CTRLA1          (0x400C4070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
+#define REG_DMAC_CTRLB1          (0x400C4074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
+#define REG_DMAC_CFG1            (0x400C4078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
+#define REG_DMAC_SADDR2          (0x400C408CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
+#define REG_DMAC_DADDR2          (0x400C4090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
+#define REG_DMAC_DSCR2           (0x400C4094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
+#define REG_DMAC_CTRLA2          (0x400C4098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
+#define REG_DMAC_CTRLB2          (0x400C409CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
+#define REG_DMAC_CFG2            (0x400C40A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
+#define REG_DMAC_SADDR3          (0x400C40B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
+#define REG_DMAC_DADDR3          (0x400C40B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
+#define REG_DMAC_DSCR3           (0x400C40BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
+#define REG_DMAC_CTRLA3          (0x400C40C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
+#define REG_DMAC_CTRLB3          (0x400C40C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
+#define REG_DMAC_CFG3            (0x400C40C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
+#define REG_DMAC_SADDR4          (0x400C40DCU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 4) */
+#define REG_DMAC_DADDR4          (0x400C40E0U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 4) */
+#define REG_DMAC_DSCR4           (0x400C40E4U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 4) */
+#define REG_DMAC_CTRLA4          (0x400C40E8U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 4) */
+#define REG_DMAC_CTRLB4          (0x400C40ECU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 4) */
+#define REG_DMAC_CFG4            (0x400C40F0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 4) */
+#define REG_DMAC_SADDR5          (0x400C4104U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 5) */
+#define REG_DMAC_DADDR5          (0x400C4108U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 5) */
+#define REG_DMAC_DSCR5           (0x400C410CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 5) */
+#define REG_DMAC_CTRLA5          (0x400C4110U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 5) */
+#define REG_DMAC_CTRLB5          (0x400C4114U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 5) */
+#define REG_DMAC_CFG5            (0x400C4118U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 5) */
+#define REG_DMAC_WPMR            (0x400C41E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */
+#define REG_DMAC_WPSR            (0x400C41E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */
+#else
+#define REG_DMAC_GCFG   (*(RwReg*)0x400C4000U) /**< \brief (DMAC) DMAC Global Configuration Register */
+#define REG_DMAC_EN     (*(RwReg*)0x400C4004U) /**< \brief (DMAC) DMAC Enable Register */
+#define REG_DMAC_SREQ   (*(RwReg*)0x400C4008U) /**< \brief (DMAC) DMAC Software Single Request Register */
+#define REG_DMAC_CREQ   (*(RwReg*)0x400C400CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
+#define REG_DMAC_LAST   (*(RwReg*)0x400C4010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
+#define REG_DMAC_EBCIER (*(WoReg*)0x400C4018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
+#define REG_DMAC_EBCIDR (*(WoReg*)0x400C401CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
+#define REG_DMAC_EBCIMR (*(RoReg*)0x400C4020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
+#define REG_DMAC_EBCISR (*(RoReg*)0x400C4024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
+#define REG_DMAC_CHER   (*(WoReg*)0x400C4028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
+#define REG_DMAC_CHDR   (*(WoReg*)0x400C402CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
+#define REG_DMAC_CHSR   (*(RoReg*)0x400C4030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
+#define REG_DMAC_SADDR0 (*(RwReg*)0x400C403CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
+#define REG_DMAC_DADDR0 (*(RwReg*)0x400C4040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
+#define REG_DMAC_DSCR0  (*(RwReg*)0x400C4044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
+#define REG_DMAC_CTRLA0 (*(RwReg*)0x400C4048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
+#define REG_DMAC_CTRLB0 (*(RwReg*)0x400C404CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
+#define REG_DMAC_CFG0   (*(RwReg*)0x400C4050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
+#define REG_DMAC_SADDR1 (*(RwReg*)0x400C4064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
+#define REG_DMAC_DADDR1 (*(RwReg*)0x400C4068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
+#define REG_DMAC_DSCR1  (*(RwReg*)0x400C406CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
+#define REG_DMAC_CTRLA1 (*(RwReg*)0x400C4070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
+#define REG_DMAC_CTRLB1 (*(RwReg*)0x400C4074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
+#define REG_DMAC_CFG1   (*(RwReg*)0x400C4078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
+#define REG_DMAC_SADDR2 (*(RwReg*)0x400C408CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
+#define REG_DMAC_DADDR2 (*(RwReg*)0x400C4090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
+#define REG_DMAC_DSCR2  (*(RwReg*)0x400C4094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
+#define REG_DMAC_CTRLA2 (*(RwReg*)0x400C4098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
+#define REG_DMAC_CTRLB2 (*(RwReg*)0x400C409CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
+#define REG_DMAC_CFG2   (*(RwReg*)0x400C40A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
+#define REG_DMAC_SADDR3 (*(RwReg*)0x400C40B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
+#define REG_DMAC_DADDR3 (*(RwReg*)0x400C40B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
+#define REG_DMAC_DSCR3  (*(RwReg*)0x400C40BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
+#define REG_DMAC_CTRLA3 (*(RwReg*)0x400C40C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
+#define REG_DMAC_CTRLB3 (*(RwReg*)0x400C40C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
+#define REG_DMAC_CFG3   (*(RwReg*)0x400C40C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
+#define REG_DMAC_SADDR4 (*(RwReg*)0x400C40DCU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 4) */
+#define REG_DMAC_DADDR4 (*(RwReg*)0x400C40E0U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 4) */
+#define REG_DMAC_DSCR4  (*(RwReg*)0x400C40E4U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 4) */
+#define REG_DMAC_CTRLA4 (*(RwReg*)0x400C40E8U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 4) */
+#define REG_DMAC_CTRLB4 (*(RwReg*)0x400C40ECU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 4) */
+#define REG_DMAC_CFG4   (*(RwReg*)0x400C40F0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 4) */
+#define REG_DMAC_SADDR5 (*(RwReg*)0x400C4104U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 5) */
+#define REG_DMAC_DADDR5 (*(RwReg*)0x400C4108U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 5) */
+#define REG_DMAC_DSCR5  (*(RwReg*)0x400C410CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 5) */
+#define REG_DMAC_CTRLA5 (*(RwReg*)0x400C4110U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 5) */
+#define REG_DMAC_CTRLB5 (*(RwReg*)0x400C4114U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 5) */
+#define REG_DMAC_CFG5   (*(RwReg*)0x400C4118U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 5) */
+#define REG_DMAC_WPMR   (*(RwReg*)0x400C41E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */
+#define REG_DMAC_WPSR   (*(RoReg*)0x400C41E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_DMAC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_efc0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_efc0.h
new file mode 100644
index 0000000..fb76726
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_efc0.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EFC0_INSTANCE_
+#define _SAM3XA_EFC0_INSTANCE_
+
+/* ========== Register definition for EFC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EFC0_FMR           (0x400E0A00U) /**< \brief (EFC0) EEFC Flash Mode Register */
+#define REG_EFC0_FCR           (0x400E0A04U) /**< \brief (EFC0) EEFC Flash Command Register */
+#define REG_EFC0_FSR           (0x400E0A08U) /**< \brief (EFC0) EEFC Flash Status Register */
+#define REG_EFC0_FRR           (0x400E0A0CU) /**< \brief (EFC0) EEFC Flash Result Register */
+#else
+#define REG_EFC0_FMR  (*(RwReg*)0x400E0A00U) /**< \brief (EFC0) EEFC Flash Mode Register */
+#define REG_EFC0_FCR  (*(WoReg*)0x400E0A04U) /**< \brief (EFC0) EEFC Flash Command Register */
+#define REG_EFC0_FSR  (*(RoReg*)0x400E0A08U) /**< \brief (EFC0) EEFC Flash Status Register */
+#define REG_EFC0_FRR  (*(RoReg*)0x400E0A0CU) /**< \brief (EFC0) EEFC Flash Result Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_EFC0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_efc1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_efc1.h
new file mode 100644
index 0000000..31034e2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_efc1.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EFC1_INSTANCE_
+#define _SAM3XA_EFC1_INSTANCE_
+
+/* ========== Register definition for EFC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EFC1_FMR           (0x400E0C00U) /**< \brief (EFC1) EEFC Flash Mode Register */
+#define REG_EFC1_FCR           (0x400E0C04U) /**< \brief (EFC1) EEFC Flash Command Register */
+#define REG_EFC1_FSR           (0x400E0C08U) /**< \brief (EFC1) EEFC Flash Status Register */
+#define REG_EFC1_FRR           (0x400E0C0CU) /**< \brief (EFC1) EEFC Flash Result Register */
+#else
+#define REG_EFC1_FMR  (*(RwReg*)0x400E0C00U) /**< \brief (EFC1) EEFC Flash Mode Register */
+#define REG_EFC1_FCR  (*(WoReg*)0x400E0C04U) /**< \brief (EFC1) EEFC Flash Command Register */
+#define REG_EFC1_FSR  (*(RoReg*)0x400E0C08U) /**< \brief (EFC1) EEFC Flash Status Register */
+#define REG_EFC1_FRR  (*(RoReg*)0x400E0C0CU) /**< \brief (EFC1) EEFC Flash Result Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_EFC1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_emac.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_emac.h
new file mode 100644
index 0000000..68cc253
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_emac.h
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_EMAC_INSTANCE_
+#define _SAM3XA_EMAC_INSTANCE_
+
+/* ========== Register definition for EMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EMAC_NCR            (0x400B0000U) /**< \brief (EMAC) Network Control Register */
+#define REG_EMAC_NCFGR          (0x400B0004U) /**< \brief (EMAC) Network Configuration Register */
+#define REG_EMAC_NSR            (0x400B0008U) /**< \brief (EMAC) Network Status Register */
+#define REG_EMAC_TSR            (0x400B0014U) /**< \brief (EMAC) Transmit Status Register */
+#define REG_EMAC_RBQP           (0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */
+#define REG_EMAC_TBQP           (0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */
+#define REG_EMAC_RSR            (0x400B0020U) /**< \brief (EMAC) Receive Status Register */
+#define REG_EMAC_ISR            (0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */
+#define REG_EMAC_IER            (0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */
+#define REG_EMAC_IDR            (0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */
+#define REG_EMAC_IMR            (0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */
+#define REG_EMAC_MAN            (0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */
+#define REG_EMAC_PTR            (0x400B0038U) /**< \brief (EMAC) Pause Time Register */
+#define REG_EMAC_PFR            (0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */
+#define REG_EMAC_FTO            (0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */
+#define REG_EMAC_SCF            (0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */
+#define REG_EMAC_MCF            (0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */
+#define REG_EMAC_FRO            (0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */
+#define REG_EMAC_FCSE           (0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */
+#define REG_EMAC_ALE            (0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */
+#define REG_EMAC_DTF            (0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */
+#define REG_EMAC_LCOL           (0x400B005CU) /**< \brief (EMAC) Late Collisions Register */
+#define REG_EMAC_ECOL           (0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */
+#define REG_EMAC_TUND           (0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */
+#define REG_EMAC_CSE            (0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */
+#define REG_EMAC_RRE            (0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */
+#define REG_EMAC_ROV            (0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */
+#define REG_EMAC_RSE            (0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */
+#define REG_EMAC_ELE            (0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */
+#define REG_EMAC_RJA            (0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */
+#define REG_EMAC_USF            (0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */
+#define REG_EMAC_STE            (0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */
+#define REG_EMAC_RLE            (0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */
+#define REG_EMAC_HRB            (0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */
+#define REG_EMAC_HRT            (0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */
+#define REG_EMAC_SA1B           (0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */
+#define REG_EMAC_SA1T           (0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */
+#define REG_EMAC_SA2B           (0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */
+#define REG_EMAC_SA2T           (0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */
+#define REG_EMAC_SA3B           (0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */
+#define REG_EMAC_SA3T           (0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */
+#define REG_EMAC_SA4B           (0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */
+#define REG_EMAC_SA4T           (0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */
+#define REG_EMAC_TID            (0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */
+#define REG_EMAC_USRIO          (0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */
+#else
+#define REG_EMAC_NCR   (*(RwReg*)0x400B0000U) /**< \brief (EMAC) Network Control Register */
+#define REG_EMAC_NCFGR (*(RwReg*)0x400B0004U) /**< \brief (EMAC) Network Configuration Register */
+#define REG_EMAC_NSR   (*(RoReg*)0x400B0008U) /**< \brief (EMAC) Network Status Register */
+#define REG_EMAC_TSR   (*(RwReg*)0x400B0014U) /**< \brief (EMAC) Transmit Status Register */
+#define REG_EMAC_RBQP  (*(RwReg*)0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */
+#define REG_EMAC_TBQP  (*(RwReg*)0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */
+#define REG_EMAC_RSR   (*(RwReg*)0x400B0020U) /**< \brief (EMAC) Receive Status Register */
+#define REG_EMAC_ISR   (*(RwReg*)0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */
+#define REG_EMAC_IER   (*(WoReg*)0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */
+#define REG_EMAC_IDR   (*(WoReg*)0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */
+#define REG_EMAC_IMR   (*(RoReg*)0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */
+#define REG_EMAC_MAN   (*(RwReg*)0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */
+#define REG_EMAC_PTR   (*(RwReg*)0x400B0038U) /**< \brief (EMAC) Pause Time Register */
+#define REG_EMAC_PFR   (*(RwReg*)0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */
+#define REG_EMAC_FTO   (*(RwReg*)0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */
+#define REG_EMAC_SCF   (*(RwReg*)0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */
+#define REG_EMAC_MCF   (*(RwReg*)0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */
+#define REG_EMAC_FRO   (*(RwReg*)0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */
+#define REG_EMAC_FCSE  (*(RwReg*)0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */
+#define REG_EMAC_ALE   (*(RwReg*)0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */
+#define REG_EMAC_DTF   (*(RwReg*)0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */
+#define REG_EMAC_LCOL  (*(RwReg*)0x400B005CU) /**< \brief (EMAC) Late Collisions Register */
+#define REG_EMAC_ECOL  (*(RwReg*)0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */
+#define REG_EMAC_TUND  (*(RwReg*)0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */
+#define REG_EMAC_CSE   (*(RwReg*)0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */
+#define REG_EMAC_RRE   (*(RwReg*)0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */
+#define REG_EMAC_ROV   (*(RwReg*)0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */
+#define REG_EMAC_RSE   (*(RwReg*)0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */
+#define REG_EMAC_ELE   (*(RwReg*)0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */
+#define REG_EMAC_RJA   (*(RwReg*)0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */
+#define REG_EMAC_USF   (*(RwReg*)0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */
+#define REG_EMAC_STE   (*(RwReg*)0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */
+#define REG_EMAC_RLE   (*(RwReg*)0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */
+#define REG_EMAC_HRB   (*(RwReg*)0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */
+#define REG_EMAC_HRT   (*(RwReg*)0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */
+#define REG_EMAC_SA1B  (*(RwReg*)0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */
+#define REG_EMAC_SA1T  (*(RwReg*)0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */
+#define REG_EMAC_SA2B  (*(RwReg*)0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */
+#define REG_EMAC_SA2T  (*(RwReg*)0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */
+#define REG_EMAC_SA3B  (*(RwReg*)0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */
+#define REG_EMAC_SA3T  (*(RwReg*)0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */
+#define REG_EMAC_SA4B  (*(RwReg*)0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */
+#define REG_EMAC_SA4T  (*(RwReg*)0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */
+#define REG_EMAC_TID   (*(RwReg*)0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */
+#define REG_EMAC_USRIO (*(RwReg*)0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_EMAC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_gpbr.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_gpbr.h
new file mode 100644
index 0000000..628eb1d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_gpbr.h
@@ -0,0 +1,40 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_GPBR_INSTANCE_
+#define _SAM3XA_GPBR_INSTANCE_
+
+/* ========== Register definition for GPBR peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GPBR_GPBR            (0x400E1A90U) /**< \brief (GPBR) General Purpose Backup Register */
+#else
+#define REG_GPBR_GPBR   (*(RwReg*)0x400E1A90U) /**< \brief (GPBR) General Purpose Backup Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_GPBR_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_hsmci.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_hsmci.h
new file mode 100644
index 0000000..db43127
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_hsmci.h
@@ -0,0 +1,78 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_HSMCI_INSTANCE_
+#define _SAM3XA_HSMCI_INSTANCE_
+
+/* ========== Register definition for HSMCI peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_HSMCI_CR                 (0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR                 (0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR               (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR               (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR               (0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR               (0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR               (0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR              (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR               (0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR                (0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR                (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR                 (0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER                (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR                (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR                (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_DMA                (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
+#define REG_HSMCI_CFG                (0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR               (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR               (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_FIFO               (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#else
+#define REG_HSMCI_CR        (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR        (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR      (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR      (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR      (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR      (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR      (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR     (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR      (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR       (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR       (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR        (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER       (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR       (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR       (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_DMA       (*(RwReg*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
+#define REG_HSMCI_CFG       (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR      (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR      (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_FIFO      (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_HSMCI_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_matrix.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_matrix.h
new file mode 100644
index 0000000..a226f4a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_matrix.h
@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_MATRIX_INSTANCE_
+#define _SAM3XA_MATRIX_INSTANCE_
+
+/* ========== Register definition for MATRIX peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MATRIX_MCFG             (0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG             (0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0            (0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1            (0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2            (0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3            (0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4            (0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_MATRIX_PRAS5            (0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
+#define REG_MATRIX_PRAS6            (0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
+#define REG_MATRIX_PRAS7            (0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
+#define REG_MATRIX_PRAS8            (0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
+#define REG_MATRIX_MRCR             (0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */
+#define REG_CCFG_SYSIO              (0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_MATRIX_WPMR             (0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR             (0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#else
+#define REG_MATRIX_MCFG    (*(RwReg*)0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG    (*(RwReg*)0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0   (*(RwReg*)0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1   (*(RwReg*)0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2   (*(RwReg*)0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3   (*(RwReg*)0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4   (*(RwReg*)0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_MATRIX_PRAS5   (*(RwReg*)0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
+#define REG_MATRIX_PRAS6   (*(RwReg*)0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
+#define REG_MATRIX_PRAS7   (*(RwReg*)0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
+#define REG_MATRIX_PRAS8   (*(RwReg*)0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
+#define REG_MATRIX_MRCR    (*(RwReg*)0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */
+#define REG_CCFG_SYSIO     (*(RwReg*)0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_MATRIX_WPMR    (*(RwReg*)0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR    (*(RoReg*)0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_MATRIX_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pioa.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pioa.h
new file mode 100644
index 0000000..b7c0867
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pioa.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOA_INSTANCE_
+#define _SAM3XA_PIOA_INSTANCE_
+
+/* ========== Register definition for PIOA peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOA_PER             (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR             (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR             (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER             (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR             (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR             (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER            (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR            (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR            (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR            (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR            (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR            (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR            (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER             (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR             (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR             (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR             (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER            (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR            (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR            (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR            (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER            (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR            (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABSR            (0x400E0E70U) /**< \brief (PIOA) Peripheral AB Select Register */
+#define REG_PIOA_SCIFSR          (0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
+#define REG_PIOA_DIFSR           (0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
+#define REG_PIOA_IFDGSR          (0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOA_SCDR            (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_OWER            (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR            (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR            (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER           (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR           (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR           (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR             (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR             (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR            (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR          (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR          (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR          (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR          (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR            (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR            (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#else
+#define REG_PIOA_PER    (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR    (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR    (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER    (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR    (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR    (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER   (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR   (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR   (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR   (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR   (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR   (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR   (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER    (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR    (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR    (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR    (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER   (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR   (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR   (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR   (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER   (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR   (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABSR   (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral AB Select Register */
+#define REG_PIOA_SCIFSR (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
+#define REG_PIOA_DIFSR  (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
+#define REG_PIOA_IFDGSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOA_SCDR   (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_OWER   (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR   (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR   (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER  (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR  (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR  (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR    (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR    (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR   (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR   (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR   (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PIOA_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_piob.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_piob.h
new file mode 100644
index 0000000..c9a608c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_piob.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOB_INSTANCE_
+#define _SAM3XA_PIOB_INSTANCE_
+
+/* ========== Register definition for PIOB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOB_PER             (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR             (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR             (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER             (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR             (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR             (0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER            (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR            (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR            (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR            (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR            (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR            (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR            (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER             (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR             (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR             (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR             (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER            (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR            (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR            (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR            (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER            (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR            (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABSR            (0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */
+#define REG_PIOB_SCIFSR          (0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
+#define REG_PIOB_DIFSR           (0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
+#define REG_PIOB_IFDGSR          (0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOB_SCDR            (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_OWER            (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR            (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR            (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER           (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR           (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR           (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR             (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR             (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR            (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR          (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR          (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR          (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR          (0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR            (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR            (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#else
+#define REG_PIOB_PER    (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR    (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR    (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER    (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR    (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR    (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER   (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR   (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR   (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR   (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR   (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR   (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR   (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER    (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR    (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR    (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR    (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER   (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR   (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR   (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR   (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER   (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR   (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABSR   (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */
+#define REG_PIOB_SCIFSR (*(WoReg*)0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
+#define REG_PIOB_DIFSR  (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
+#define REG_PIOB_IFDGSR (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOB_SCDR   (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_OWER   (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR   (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR   (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER  (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR  (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR  (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR    (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR    (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR   (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR   (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR   (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PIOB_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pioc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pioc.h
new file mode 100644
index 0000000..ccbee7b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pioc.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOC_INSTANCE_
+#define _SAM3XA_PIOC_INSTANCE_
+
+/* ========== Register definition for PIOC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOC_PER             (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR             (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR             (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER             (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR             (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR             (0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER            (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR            (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR            (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR            (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR            (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR            (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR            (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER             (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR             (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR             (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR             (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER            (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR            (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR            (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR            (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER            (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR            (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABSR            (0x400E1270U) /**< \brief (PIOC) Peripheral AB Select Register */
+#define REG_PIOC_SCIFSR          (0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
+#define REG_PIOC_DIFSR           (0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
+#define REG_PIOC_IFDGSR          (0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOC_SCDR            (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_OWER            (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR            (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR            (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER           (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR           (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR           (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR             (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR             (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR            (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR          (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR          (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR          (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR          (0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR            (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR            (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#else
+#define REG_PIOC_PER    (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR    (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR    (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER    (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR    (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR    (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER   (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR   (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR   (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR   (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR   (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR   (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR   (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER    (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR    (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR    (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR    (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER   (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR   (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR   (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR   (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER   (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR   (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABSR   (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral AB Select Register */
+#define REG_PIOC_SCIFSR (*(WoReg*)0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
+#define REG_PIOC_DIFSR  (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
+#define REG_PIOC_IFDGSR (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOC_SCDR   (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_OWER   (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR   (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR   (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER  (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR  (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR  (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR    (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR    (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR   (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR   (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR   (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PIOC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_piod.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_piod.h
new file mode 100644
index 0000000..b6d81ef
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_piod.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOD_INSTANCE_
+#define _SAM3XA_PIOD_INSTANCE_
+
+/* ========== Register definition for PIOD peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOD_PER             (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
+#define REG_PIOD_PDR             (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
+#define REG_PIOD_PSR             (0x400E1408U) /**< \brief (PIOD) PIO Status Register */
+#define REG_PIOD_OER             (0x400E1410U) /**< \brief (PIOD) Output Enable Register */
+#define REG_PIOD_ODR             (0x400E1414U) /**< \brief (PIOD) Output Disable Register */
+#define REG_PIOD_OSR             (0x400E1418U) /**< \brief (PIOD) Output Status Register */
+#define REG_PIOD_IFER            (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
+#define REG_PIOD_IFDR            (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
+#define REG_PIOD_IFSR            (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
+#define REG_PIOD_SODR            (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
+#define REG_PIOD_CODR            (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
+#define REG_PIOD_ODSR            (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
+#define REG_PIOD_PDSR            (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
+#define REG_PIOD_IER             (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
+#define REG_PIOD_IDR             (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
+#define REG_PIOD_IMR             (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
+#define REG_PIOD_ISR             (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
+#define REG_PIOD_MDER            (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
+#define REG_PIOD_MDDR            (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
+#define REG_PIOD_MDSR            (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
+#define REG_PIOD_PUDR            (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
+#define REG_PIOD_PUER            (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
+#define REG_PIOD_PUSR            (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
+#define REG_PIOD_ABSR            (0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */
+#define REG_PIOD_SCIFSR          (0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */
+#define REG_PIOD_DIFSR           (0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */
+#define REG_PIOD_IFDGSR          (0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOD_SCDR            (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
+#define REG_PIOD_OWER            (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
+#define REG_PIOD_OWDR            (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
+#define REG_PIOD_OWSR            (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
+#define REG_PIOD_AIMER           (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
+#define REG_PIOD_AIMDR           (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
+#define REG_PIOD_AIMMR           (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
+#define REG_PIOD_ESR             (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
+#define REG_PIOD_LSR             (0x400E14C4U) /**< \brief (PIOD) Level Select Register */
+#define REG_PIOD_ELSR            (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
+#define REG_PIOD_FELLSR          (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
+#define REG_PIOD_REHLSR          (0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
+#define REG_PIOD_FRLHSR          (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
+#define REG_PIOD_LOCKSR          (0x400E14E0U) /**< \brief (PIOD) Lock Status */
+#define REG_PIOD_WPMR            (0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */
+#define REG_PIOD_WPSR            (0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */
+#else
+#define REG_PIOD_PER    (*(WoReg*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
+#define REG_PIOD_PDR    (*(WoReg*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
+#define REG_PIOD_PSR    (*(RoReg*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */
+#define REG_PIOD_OER    (*(WoReg*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */
+#define REG_PIOD_ODR    (*(WoReg*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */
+#define REG_PIOD_OSR    (*(RoReg*)0x400E1418U) /**< \brief (PIOD) Output Status Register */
+#define REG_PIOD_IFER   (*(WoReg*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
+#define REG_PIOD_IFDR   (*(WoReg*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
+#define REG_PIOD_IFSR   (*(RoReg*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
+#define REG_PIOD_SODR   (*(WoReg*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
+#define REG_PIOD_CODR   (*(WoReg*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
+#define REG_PIOD_ODSR   (*(RwReg*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
+#define REG_PIOD_PDSR   (*(RoReg*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
+#define REG_PIOD_IER    (*(WoReg*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
+#define REG_PIOD_IDR    (*(WoReg*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
+#define REG_PIOD_IMR    (*(RoReg*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
+#define REG_PIOD_ISR    (*(RoReg*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
+#define REG_PIOD_MDER   (*(WoReg*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
+#define REG_PIOD_MDDR   (*(WoReg*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
+#define REG_PIOD_MDSR   (*(RoReg*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
+#define REG_PIOD_PUDR   (*(WoReg*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
+#define REG_PIOD_PUER   (*(WoReg*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
+#define REG_PIOD_PUSR   (*(RoReg*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
+#define REG_PIOD_ABSR   (*(RwReg*)0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */
+#define REG_PIOD_SCIFSR (*(WoReg*)0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */
+#define REG_PIOD_DIFSR  (*(WoReg*)0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */
+#define REG_PIOD_IFDGSR (*(RoReg*)0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOD_SCDR   (*(RwReg*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
+#define REG_PIOD_OWER   (*(WoReg*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
+#define REG_PIOD_OWDR   (*(WoReg*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
+#define REG_PIOD_OWSR   (*(RoReg*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
+#define REG_PIOD_AIMER  (*(WoReg*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
+#define REG_PIOD_AIMDR  (*(WoReg*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
+#define REG_PIOD_AIMMR  (*(RoReg*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
+#define REG_PIOD_ESR    (*(WoReg*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
+#define REG_PIOD_LSR    (*(WoReg*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */
+#define REG_PIOD_ELSR   (*(RoReg*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
+#define REG_PIOD_FELLSR (*(WoReg*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
+#define REG_PIOD_REHLSR (*(WoReg*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
+#define REG_PIOD_FRLHSR (*(RoReg*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
+#define REG_PIOD_LOCKSR (*(RoReg*)0x400E14E0U) /**< \brief (PIOD) Lock Status */
+#define REG_PIOD_WPMR   (*(RwReg*)0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */
+#define REG_PIOD_WPSR   (*(RoReg*)0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PIOD_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pioe.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pioe.h
new file mode 100644
index 0000000..c1cc542
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pioe.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOE_INSTANCE_
+#define _SAM3XA_PIOE_INSTANCE_
+
+/* ========== Register definition for PIOE peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOE_PER             (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
+#define REG_PIOE_PDR             (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
+#define REG_PIOE_PSR             (0x400E1608U) /**< \brief (PIOE) PIO Status Register */
+#define REG_PIOE_OER             (0x400E1610U) /**< \brief (PIOE) Output Enable Register */
+#define REG_PIOE_ODR             (0x400E1614U) /**< \brief (PIOE) Output Disable Register */
+#define REG_PIOE_OSR             (0x400E1618U) /**< \brief (PIOE) Output Status Register */
+#define REG_PIOE_IFER            (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
+#define REG_PIOE_IFDR            (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
+#define REG_PIOE_IFSR            (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
+#define REG_PIOE_SODR            (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
+#define REG_PIOE_CODR            (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
+#define REG_PIOE_ODSR            (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
+#define REG_PIOE_PDSR            (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
+#define REG_PIOE_IER             (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
+#define REG_PIOE_IDR             (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
+#define REG_PIOE_IMR             (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
+#define REG_PIOE_ISR             (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
+#define REG_PIOE_MDER            (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
+#define REG_PIOE_MDDR            (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
+#define REG_PIOE_MDSR            (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
+#define REG_PIOE_PUDR            (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
+#define REG_PIOE_PUER            (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
+#define REG_PIOE_PUSR            (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
+#define REG_PIOE_ABSR            (0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */
+#define REG_PIOE_SCIFSR          (0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */
+#define REG_PIOE_DIFSR           (0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */
+#define REG_PIOE_IFDGSR          (0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOE_SCDR            (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
+#define REG_PIOE_OWER            (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
+#define REG_PIOE_OWDR            (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
+#define REG_PIOE_OWSR            (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
+#define REG_PIOE_AIMER           (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
+#define REG_PIOE_AIMDR           (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */
+#define REG_PIOE_AIMMR           (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
+#define REG_PIOE_ESR             (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
+#define REG_PIOE_LSR             (0x400E16C4U) /**< \brief (PIOE) Level Select Register */
+#define REG_PIOE_ELSR            (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
+#define REG_PIOE_FELLSR          (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */
+#define REG_PIOE_REHLSR          (0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */
+#define REG_PIOE_FRLHSR          (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
+#define REG_PIOE_LOCKSR          (0x400E16E0U) /**< \brief (PIOE) Lock Status */
+#define REG_PIOE_WPMR            (0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */
+#define REG_PIOE_WPSR            (0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */
+#else
+#define REG_PIOE_PER    (*(WoReg*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
+#define REG_PIOE_PDR    (*(WoReg*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
+#define REG_PIOE_PSR    (*(RoReg*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */
+#define REG_PIOE_OER    (*(WoReg*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */
+#define REG_PIOE_ODR    (*(WoReg*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */
+#define REG_PIOE_OSR    (*(RoReg*)0x400E1618U) /**< \brief (PIOE) Output Status Register */
+#define REG_PIOE_IFER   (*(WoReg*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
+#define REG_PIOE_IFDR   (*(WoReg*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
+#define REG_PIOE_IFSR   (*(RoReg*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
+#define REG_PIOE_SODR   (*(WoReg*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
+#define REG_PIOE_CODR   (*(WoReg*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
+#define REG_PIOE_ODSR   (*(RwReg*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
+#define REG_PIOE_PDSR   (*(RoReg*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
+#define REG_PIOE_IER    (*(WoReg*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
+#define REG_PIOE_IDR    (*(WoReg*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
+#define REG_PIOE_IMR    (*(RoReg*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
+#define REG_PIOE_ISR    (*(RoReg*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
+#define REG_PIOE_MDER   (*(WoReg*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
+#define REG_PIOE_MDDR   (*(WoReg*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
+#define REG_PIOE_MDSR   (*(RoReg*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
+#define REG_PIOE_PUDR   (*(WoReg*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
+#define REG_PIOE_PUER   (*(WoReg*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
+#define REG_PIOE_PUSR   (*(RoReg*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
+#define REG_PIOE_ABSR   (*(RwReg*)0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */
+#define REG_PIOE_SCIFSR (*(WoReg*)0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */
+#define REG_PIOE_DIFSR  (*(WoReg*)0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */
+#define REG_PIOE_IFDGSR (*(RoReg*)0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOE_SCDR   (*(RwReg*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
+#define REG_PIOE_OWER   (*(WoReg*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
+#define REG_PIOE_OWDR   (*(WoReg*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
+#define REG_PIOE_OWSR   (*(RoReg*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
+#define REG_PIOE_AIMER  (*(WoReg*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
+#define REG_PIOE_AIMDR  (*(WoReg*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */
+#define REG_PIOE_AIMMR  (*(RoReg*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
+#define REG_PIOE_ESR    (*(WoReg*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
+#define REG_PIOE_LSR    (*(WoReg*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */
+#define REG_PIOE_ELSR   (*(RoReg*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
+#define REG_PIOE_FELLSR (*(WoReg*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */
+#define REG_PIOE_REHLSR (*(WoReg*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */
+#define REG_PIOE_FRLHSR (*(RoReg*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
+#define REG_PIOE_LOCKSR (*(RoReg*)0x400E16E0U) /**< \brief (PIOE) Lock Status */
+#define REG_PIOE_WPMR   (*(RwReg*)0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */
+#define REG_PIOE_WPSR   (*(RoReg*)0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PIOE_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_piof.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_piof.h
new file mode 100644
index 0000000..3e52677
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_piof.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PIOF_INSTANCE_
+#define _SAM3XA_PIOF_INSTANCE_
+
+/* ========== Register definition for PIOF peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOF_PER             (0x400E1800U) /**< \brief (PIOF) PIO Enable Register */
+#define REG_PIOF_PDR             (0x400E1804U) /**< \brief (PIOF) PIO Disable Register */
+#define REG_PIOF_PSR             (0x400E1808U) /**< \brief (PIOF) PIO Status Register */
+#define REG_PIOF_OER             (0x400E1810U) /**< \brief (PIOF) Output Enable Register */
+#define REG_PIOF_ODR             (0x400E1814U) /**< \brief (PIOF) Output Disable Register */
+#define REG_PIOF_OSR             (0x400E1818U) /**< \brief (PIOF) Output Status Register */
+#define REG_PIOF_IFER            (0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */
+#define REG_PIOF_IFDR            (0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */
+#define REG_PIOF_IFSR            (0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */
+#define REG_PIOF_SODR            (0x400E1830U) /**< \brief (PIOF) Set Output Data Register */
+#define REG_PIOF_CODR            (0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */
+#define REG_PIOF_ODSR            (0x400E1838U) /**< \brief (PIOF) Output Data Status Register */
+#define REG_PIOF_PDSR            (0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */
+#define REG_PIOF_IER             (0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */
+#define REG_PIOF_IDR             (0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */
+#define REG_PIOF_IMR             (0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */
+#define REG_PIOF_ISR             (0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */
+#define REG_PIOF_MDER            (0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */
+#define REG_PIOF_MDDR            (0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */
+#define REG_PIOF_MDSR            (0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */
+#define REG_PIOF_PUDR            (0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */
+#define REG_PIOF_PUER            (0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */
+#define REG_PIOF_PUSR            (0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */
+#define REG_PIOF_ABSR            (0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */
+#define REG_PIOF_SCIFSR          (0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */
+#define REG_PIOF_DIFSR           (0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */
+#define REG_PIOF_IFDGSR          (0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOF_SCDR            (0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */
+#define REG_PIOF_OWER            (0x400E18A0U) /**< \brief (PIOF) Output Write Enable */
+#define REG_PIOF_OWDR            (0x400E18A4U) /**< \brief (PIOF) Output Write Disable */
+#define REG_PIOF_OWSR            (0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */
+#define REG_PIOF_AIMER           (0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */
+#define REG_PIOF_AIMDR           (0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */
+#define REG_PIOF_AIMMR           (0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */
+#define REG_PIOF_ESR             (0x400E18C0U) /**< \brief (PIOF) Edge Select Register */
+#define REG_PIOF_LSR             (0x400E18C4U) /**< \brief (PIOF) Level Select Register */
+#define REG_PIOF_ELSR            (0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */
+#define REG_PIOF_FELLSR          (0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */
+#define REG_PIOF_REHLSR          (0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */
+#define REG_PIOF_FRLHSR          (0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */
+#define REG_PIOF_LOCKSR          (0x400E18E0U) /**< \brief (PIOF) Lock Status */
+#define REG_PIOF_WPMR            (0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */
+#define REG_PIOF_WPSR            (0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */
+#else
+#define REG_PIOF_PER    (*(WoReg*)0x400E1800U) /**< \brief (PIOF) PIO Enable Register */
+#define REG_PIOF_PDR    (*(WoReg*)0x400E1804U) /**< \brief (PIOF) PIO Disable Register */
+#define REG_PIOF_PSR    (*(RoReg*)0x400E1808U) /**< \brief (PIOF) PIO Status Register */
+#define REG_PIOF_OER    (*(WoReg*)0x400E1810U) /**< \brief (PIOF) Output Enable Register */
+#define REG_PIOF_ODR    (*(WoReg*)0x400E1814U) /**< \brief (PIOF) Output Disable Register */
+#define REG_PIOF_OSR    (*(RoReg*)0x400E1818U) /**< \brief (PIOF) Output Status Register */
+#define REG_PIOF_IFER   (*(WoReg*)0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */
+#define REG_PIOF_IFDR   (*(WoReg*)0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */
+#define REG_PIOF_IFSR   (*(RoReg*)0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */
+#define REG_PIOF_SODR   (*(WoReg*)0x400E1830U) /**< \brief (PIOF) Set Output Data Register */
+#define REG_PIOF_CODR   (*(WoReg*)0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */
+#define REG_PIOF_ODSR   (*(RwReg*)0x400E1838U) /**< \brief (PIOF) Output Data Status Register */
+#define REG_PIOF_PDSR   (*(RoReg*)0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */
+#define REG_PIOF_IER    (*(WoReg*)0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */
+#define REG_PIOF_IDR    (*(WoReg*)0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */
+#define REG_PIOF_IMR    (*(RoReg*)0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */
+#define REG_PIOF_ISR    (*(RoReg*)0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */
+#define REG_PIOF_MDER   (*(WoReg*)0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */
+#define REG_PIOF_MDDR   (*(WoReg*)0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */
+#define REG_PIOF_MDSR   (*(RoReg*)0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */
+#define REG_PIOF_PUDR   (*(WoReg*)0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */
+#define REG_PIOF_PUER   (*(WoReg*)0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */
+#define REG_PIOF_PUSR   (*(RoReg*)0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */
+#define REG_PIOF_ABSR   (*(RwReg*)0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */
+#define REG_PIOF_SCIFSR (*(WoReg*)0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */
+#define REG_PIOF_DIFSR  (*(WoReg*)0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */
+#define REG_PIOF_IFDGSR (*(RoReg*)0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */
+#define REG_PIOF_SCDR   (*(RwReg*)0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */
+#define REG_PIOF_OWER   (*(WoReg*)0x400E18A0U) /**< \brief (PIOF) Output Write Enable */
+#define REG_PIOF_OWDR   (*(WoReg*)0x400E18A4U) /**< \brief (PIOF) Output Write Disable */
+#define REG_PIOF_OWSR   (*(RoReg*)0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */
+#define REG_PIOF_AIMER  (*(WoReg*)0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */
+#define REG_PIOF_AIMDR  (*(WoReg*)0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */
+#define REG_PIOF_AIMMR  (*(RoReg*)0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */
+#define REG_PIOF_ESR    (*(WoReg*)0x400E18C0U) /**< \brief (PIOF) Edge Select Register */
+#define REG_PIOF_LSR    (*(WoReg*)0x400E18C4U) /**< \brief (PIOF) Level Select Register */
+#define REG_PIOF_ELSR   (*(RoReg*)0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */
+#define REG_PIOF_FELLSR (*(WoReg*)0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */
+#define REG_PIOF_REHLSR (*(WoReg*)0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */
+#define REG_PIOF_FRLHSR (*(RoReg*)0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */
+#define REG_PIOF_LOCKSR (*(RoReg*)0x400E18E0U) /**< \brief (PIOF) Lock Status */
+#define REG_PIOF_WPMR   (*(RwReg*)0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */
+#define REG_PIOF_WPSR   (*(RoReg*)0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PIOF_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pmc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pmc.h
new file mode 100644
index 0000000..37e16dd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pmc.h
@@ -0,0 +1,90 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PMC_INSTANCE_
+#define _SAM3XA_PMC_INSTANCE_
+
+/* ========== Register definition for PMC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PMC_SCER            (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR            (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR            (0x400E0608U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0           (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0           (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0           (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_UCKR           (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */
+#define REG_CKGR_MOR            (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR           (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR          (0x400E0628U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR            (0x400E0630U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB             (0x400E0638U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK             (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER             (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR             (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR              (0x400E0668U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR             (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR            (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR            (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR            (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR            (0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR            (0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1           (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1           (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1           (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_PCR             (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */
+#else
+#define REG_PMC_SCER   (*(WoReg*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR   (*(WoReg*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR   (*(RoReg*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0  (*(WoReg*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0  (*(WoReg*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0  (*(RoReg*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_UCKR  (*(RwReg*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */
+#define REG_CKGR_MOR   (*(RwReg*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR  (*(RoReg*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0628U) /**< \brief (PMC) PLLA Register */
+#define REG_PMC_MCKR   (*(RwReg*)0x400E0630U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB    (*(RwReg*)0x400E0638U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK    (*(RwReg*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER    (*(WoReg*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR    (*(WoReg*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR     (*(RoReg*)0x400E0668U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR    (*(RoReg*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR   (*(RwReg*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR   (*(RwReg*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR   (*(WoReg*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR   (*(RwReg*)0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR   (*(RoReg*)0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1  (*(WoReg*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1  (*(WoReg*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1  (*(RoReg*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_PCR    (*(RwReg*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PMC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pwm.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pwm.h
new file mode 100644
index 0000000..1adda68
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_pwm.h
@@ -0,0 +1,306 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_PWM_INSTANCE_
+#define _SAM3XA_PWM_INSTANCE_
+
+/* ========== Register definition for PWM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PWM_CLK               (0x40094000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA               (0x40094004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS               (0x40094008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR                (0x4009400CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1              (0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1              (0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1              (0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1              (0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM               (0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC              (0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP              (0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD           (0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2              (0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2              (0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2              (0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2              (0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV               (0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS                (0x40094048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS               (0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC               (0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD            (0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD            (0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR               (0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR               (0x40094060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR               (0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV               (0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE1              (0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */
+#define REG_PWM_FPE2              (0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */
+#define REG_PWM_ELMR              (0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR              (0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR              (0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR              (0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_TPR               (0x40094108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR               (0x4009410CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_TNPR              (0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR              (0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR              (0x40094120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR              (0x40094124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0             (0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0          (0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0             (0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0          (0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1             (0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1          (0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1             (0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1          (0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2             (0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2          (0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2             (0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2          (0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3             (0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3          (0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3             (0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3          (0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4             (0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4          (0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4             (0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4          (0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5             (0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5          (0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5             (0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5          (0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6             (0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6          (0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6             (0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6          (0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7             (0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7          (0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7             (0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7          (0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0              (0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0             (0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0          (0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0             (0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0          (0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0             (0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0               (0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0            (0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1              (0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1             (0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1          (0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1             (0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1          (0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1             (0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1               (0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1            (0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2              (0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2             (0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2          (0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2             (0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2          (0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2             (0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2               (0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2            (0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3              (0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3             (0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3          (0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3             (0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3          (0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3             (0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3               (0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3            (0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#define REG_PWM_CMR4              (0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */
+#define REG_PWM_CDTY4             (0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */
+#define REG_PWM_CDTYUPD4          (0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */
+#define REG_PWM_CPRD4             (0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */
+#define REG_PWM_CPRDUPD4          (0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */
+#define REG_PWM_CCNT4             (0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */
+#define REG_PWM_DT4               (0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */
+#define REG_PWM_DTUPD4            (0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */
+#define REG_PWM_CMR5              (0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */
+#define REG_PWM_CDTY5             (0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */
+#define REG_PWM_CDTYUPD5          (0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */
+#define REG_PWM_CPRD5             (0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */
+#define REG_PWM_CPRDUPD5          (0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */
+#define REG_PWM_CCNT5             (0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */
+#define REG_PWM_DT5               (0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */
+#define REG_PWM_DTUPD5            (0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */
+#define REG_PWM_CMR6              (0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */
+#define REG_PWM_CDTY6             (0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */
+#define REG_PWM_CDTYUPD6          (0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */
+#define REG_PWM_CPRD6             (0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */
+#define REG_PWM_CPRDUPD6          (0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */
+#define REG_PWM_CCNT6             (0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */
+#define REG_PWM_DT6               (0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */
+#define REG_PWM_DTUPD6            (0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */
+#define REG_PWM_CMR7              (0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */
+#define REG_PWM_CDTY7             (0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */
+#define REG_PWM_CDTYUPD7          (0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */
+#define REG_PWM_CPRD7             (0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */
+#define REG_PWM_CPRDUPD7          (0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */
+#define REG_PWM_CCNT7             (0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */
+#define REG_PWM_DT7               (0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */
+#define REG_PWM_DTUPD7            (0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */
+#else
+#define REG_PWM_CLK      (*(RwReg*)0x40094000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA      (*(WoReg*)0x40094004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS      (*(WoReg*)0x40094008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR       (*(RoReg*)0x4009400CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1     (*(WoReg*)0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1     (*(WoReg*)0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1     (*(RoReg*)0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1     (*(RoReg*)0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM      (*(RwReg*)0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC     (*(RwReg*)0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP     (*(RwReg*)0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD  (*(WoReg*)0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2     (*(WoReg*)0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2     (*(WoReg*)0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2     (*(RoReg*)0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2     (*(RoReg*)0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV      (*(RwReg*)0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS       (*(RwReg*)0x40094048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS      (*(WoReg*)0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC      (*(WoReg*)0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD   (*(WoReg*)0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD   (*(WoReg*)0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR      (*(RwReg*)0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR      (*(RoReg*)0x40094060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR      (*(WoReg*)0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV      (*(RwReg*)0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE1     (*(RwReg*)0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */
+#define REG_PWM_FPE2     (*(RwReg*)0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */
+#define REG_PWM_ELMR     (*(RwReg*)0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR     (*(RwReg*)0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR     (*(WoReg*)0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR     (*(RoReg*)0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_TPR      (*(RwReg*)0x40094108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR      (*(RwReg*)0x4009410CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_TNPR     (*(RwReg*)0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR     (*(RwReg*)0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR     (*(WoReg*)0x40094120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR     (*(RoReg*)0x40094124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0    (*(RwReg*)0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0    (*(RwReg*)0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1    (*(RwReg*)0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1    (*(RwReg*)0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2    (*(RwReg*)0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2    (*(RwReg*)0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3    (*(RwReg*)0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3    (*(RwReg*)0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4    (*(RwReg*)0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4    (*(RwReg*)0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5    (*(RwReg*)0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5    (*(RwReg*)0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6    (*(RwReg*)0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6    (*(RwReg*)0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7    (*(RwReg*)0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7    (*(RwReg*)0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0     (*(RwReg*)0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0    (*(RwReg*)0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0    (*(RwReg*)0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0    (*(RoReg*)0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0      (*(RwReg*)0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0   (*(WoReg*)0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1     (*(RwReg*)0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1    (*(RwReg*)0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1    (*(RwReg*)0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1    (*(RoReg*)0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1      (*(RwReg*)0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1   (*(WoReg*)0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2     (*(RwReg*)0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2    (*(RwReg*)0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2    (*(RwReg*)0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2    (*(RoReg*)0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2      (*(RwReg*)0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2   (*(WoReg*)0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3     (*(RwReg*)0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3    (*(RwReg*)0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3    (*(RwReg*)0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3    (*(RoReg*)0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3      (*(RwReg*)0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3   (*(WoReg*)0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#define REG_PWM_CMR4     (*(RwReg*)0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */
+#define REG_PWM_CDTY4    (*(RwReg*)0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */
+#define REG_PWM_CDTYUPD4 (*(WoReg*)0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */
+#define REG_PWM_CPRD4    (*(RwReg*)0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */
+#define REG_PWM_CPRDUPD4 (*(WoReg*)0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */
+#define REG_PWM_CCNT4    (*(RoReg*)0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */
+#define REG_PWM_DT4      (*(RwReg*)0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */
+#define REG_PWM_DTUPD4   (*(WoReg*)0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */
+#define REG_PWM_CMR5     (*(RwReg*)0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */
+#define REG_PWM_CDTY5    (*(RwReg*)0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */
+#define REG_PWM_CDTYUPD5 (*(WoReg*)0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */
+#define REG_PWM_CPRD5    (*(RwReg*)0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */
+#define REG_PWM_CPRDUPD5 (*(WoReg*)0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */
+#define REG_PWM_CCNT5    (*(RoReg*)0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */
+#define REG_PWM_DT5      (*(RwReg*)0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */
+#define REG_PWM_DTUPD5   (*(WoReg*)0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */
+#define REG_PWM_CMR6     (*(RwReg*)0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */
+#define REG_PWM_CDTY6    (*(RwReg*)0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */
+#define REG_PWM_CDTYUPD6 (*(WoReg*)0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */
+#define REG_PWM_CPRD6    (*(RwReg*)0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */
+#define REG_PWM_CPRDUPD6 (*(WoReg*)0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */
+#define REG_PWM_CCNT6    (*(RoReg*)0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */
+#define REG_PWM_DT6      (*(RwReg*)0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */
+#define REG_PWM_DTUPD6   (*(WoReg*)0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */
+#define REG_PWM_CMR7     (*(RwReg*)0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */
+#define REG_PWM_CDTY7    (*(RwReg*)0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */
+#define REG_PWM_CDTYUPD7 (*(WoReg*)0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */
+#define REG_PWM_CPRD7    (*(RwReg*)0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */
+#define REG_PWM_CPRDUPD7 (*(WoReg*)0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */
+#define REG_PWM_CCNT7    (*(RoReg*)0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */
+#define REG_PWM_DT7      (*(RwReg*)0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */
+#define REG_PWM_DTUPD7   (*(WoReg*)0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_PWM_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_rstc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_rstc.h
new file mode 100644
index 0000000..a7e4f32
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_rstc.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RSTC_INSTANCE_
+#define _SAM3XA_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RSTC_CR          (0x400E1A00U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR          (0x400E1A04U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR          (0x400E1A08U) /**< \brief (RSTC) Mode Register */
+#else
+#define REG_RSTC_CR (*(WoReg*)0x400E1A00U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR (*(RoReg*)0x400E1A04U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR (*(RwReg*)0x400E1A08U) /**< \brief (RSTC) Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_RSTC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_rtc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_rtc.h
new file mode 100644
index 0000000..750633e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_rtc.h
@@ -0,0 +1,64 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RTC_INSTANCE_
+#define _SAM3XA_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_CR              (0x400E1A60U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR              (0x400E1A64U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR            (0x400E1A68U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR            (0x400E1A6CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR          (0x400E1A70U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR          (0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR              (0x400E1A78U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR            (0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER             (0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR             (0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR             (0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER             (0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR            (0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */
+#else
+#define REG_RTC_CR     (*(RwReg*)0x400E1A60U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR     (*(RwReg*)0x400E1A64U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR   (*(RwReg*)0x400E1A68U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR   (*(RwReg*)0x400E1A6CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1A70U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR (*(RwReg*)0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR     (*(RoReg*)0x400E1A78U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR   (*(WoReg*)0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER    (*(WoReg*)0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR    (*(WoReg*)0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR    (*(RoReg*)0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER    (*(RoReg*)0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */
+#define REG_RTC_WPMR   (*(RwReg*)0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_RTC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_rtt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_rtt.h
new file mode 100644
index 0000000..f41d3e2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_rtt.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_RTT_INSTANCE_
+#define _SAM3XA_RTT_INSTANCE_
+
+/* ========== Register definition for RTT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTT_MR          (0x400E1A30U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR          (0x400E1A34U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR          (0x400E1A38U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR          (0x400E1A3CU) /**< \brief (RTT) Status Register */
+#else
+#define REG_RTT_MR (*(RwReg*)0x400E1A30U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR (*(RwReg*)0x400E1A34U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR (*(RoReg*)0x400E1A38U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR (*(RoReg*)0x400E1A3CU) /**< \brief (RTT) Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_RTT_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_sdramc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_sdramc.h
new file mode 100644
index 0000000..68dfe63
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_sdramc.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SDRAMC_INSTANCE_
+#define _SAM3XA_SDRAMC_INSTANCE_
+
+/* ========== Register definition for SDRAMC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SDRAMC_MR            (0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */
+#define REG_SDRAMC_TR            (0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
+#define REG_SDRAMC_CR            (0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
+#define REG_SDRAMC_LPR           (0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
+#define REG_SDRAMC_IER           (0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
+#define REG_SDRAMC_IDR           (0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
+#define REG_SDRAMC_IMR           (0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
+#define REG_SDRAMC_ISR           (0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
+#define REG_SDRAMC_MDR           (0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
+#define REG_SDRAMC_CR1           (0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
+#define REG_SDRAMC_OCMS          (0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */
+#else
+#define REG_SDRAMC_MR   (*(RwReg*)0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */
+#define REG_SDRAMC_TR   (*(RwReg*)0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
+#define REG_SDRAMC_CR   (*(RwReg*)0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
+#define REG_SDRAMC_LPR  (*(RwReg*)0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
+#define REG_SDRAMC_IER  (*(WoReg*)0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
+#define REG_SDRAMC_IDR  (*(WoReg*)0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
+#define REG_SDRAMC_IMR  (*(RoReg*)0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
+#define REG_SDRAMC_ISR  (*(RoReg*)0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
+#define REG_SDRAMC_MDR  (*(RwReg*)0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
+#define REG_SDRAMC_CR1  (*(RwReg*)0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
+#define REG_SDRAMC_OCMS (*(RwReg*)0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_smc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_smc.h
new file mode 100644
index 0000000..1298d3e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_smc.h
@@ -0,0 +1,184 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SMC_INSTANCE_
+#define _SAM3XA_SMC_INSTANCE_
+
+/* ========== Register definition for SMC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SMC_CFG               (0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
+#define REG_SMC_CTRL              (0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
+#define REG_SMC_SR                (0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
+#define REG_SMC_IER               (0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
+#define REG_SMC_IDR               (0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
+#define REG_SMC_IMR               (0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
+#define REG_SMC_ADDR              (0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
+#define REG_SMC_BANK              (0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
+#define REG_SMC_ECC_CTRL          (0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
+#define REG_SMC_ECC_MD            (0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
+#define REG_SMC_ECC_SR1           (0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
+#define REG_SMC_ECC_PR0           (0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
+#define REG_SMC_ECC_PR1           (0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
+#define REG_SMC_ECC_SR2           (0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
+#define REG_SMC_ECC_PR2           (0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
+#define REG_SMC_ECC_PR3           (0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
+#define REG_SMC_ECC_PR4           (0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
+#define REG_SMC_ECC_PR5           (0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
+#define REG_SMC_ECC_PR6           (0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
+#define REG_SMC_ECC_PR7           (0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
+#define REG_SMC_ECC_PR8           (0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
+#define REG_SMC_ECC_PR9           (0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
+#define REG_SMC_ECC_PR10          (0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
+#define REG_SMC_ECC_PR11          (0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
+#define REG_SMC_ECC_PR12          (0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
+#define REG_SMC_ECC_PR13          (0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
+#define REG_SMC_ECC_PR14          (0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
+#define REG_SMC_ECC_PR15          (0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
+#define REG_SMC_SETUP0            (0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0            (0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0            (0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_TIMINGS0          (0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
+#define REG_SMC_MODE0             (0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1            (0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1            (0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1            (0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_TIMINGS1          (0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
+#define REG_SMC_MODE1             (0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2            (0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2            (0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2            (0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_TIMINGS2          (0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
+#define REG_SMC_MODE2             (0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3            (0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3            (0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3            (0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_TIMINGS3          (0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
+#define REG_SMC_MODE3             (0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4            (0x400E00C0U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4            (0x400E00C4U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4            (0x400E00C8U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_TIMINGS4          (0x400E00CCU) /**< \brief (SMC) SMC Timings Register (CS_number = 4) */
+#define REG_SMC_MODE4             (0x400E00D0U) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_SETUP5            (0x400E00D4U) /**< \brief (SMC) SMC Setup Register (CS_number = 5) */
+#define REG_SMC_PULSE5            (0x400E00D8U) /**< \brief (SMC) SMC Pulse Register (CS_number = 5) */
+#define REG_SMC_CYCLE5            (0x400E00DCU) /**< \brief (SMC) SMC Cycle Register (CS_number = 5) */
+#define REG_SMC_TIMINGS5          (0x400E00E0U) /**< \brief (SMC) SMC Timings Register (CS_number = 5) */
+#define REG_SMC_MODE5             (0x400E00E4U) /**< \brief (SMC) SMC Mode Register (CS_number = 5) */
+#define REG_SMC_SETUP6            (0x400E00E8U) /**< \brief (SMC) SMC Setup Register (CS_number = 6) */
+#define REG_SMC_PULSE6            (0x400E00ECU) /**< \brief (SMC) SMC Pulse Register (CS_number = 6) */
+#define REG_SMC_CYCLE6            (0x400E00F0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 6) */
+#define REG_SMC_TIMINGS6          (0x400E00F4U) /**< \brief (SMC) SMC Timings Register (CS_number = 6) */
+#define REG_SMC_MODE6             (0x400E00F8U) /**< \brief (SMC) SMC Mode Register (CS_number = 6) */
+#define REG_SMC_SETUP7            (0x400E00FCU) /**< \brief (SMC) SMC Setup Register (CS_number = 7) */
+#define REG_SMC_PULSE7            (0x400E0100U) /**< \brief (SMC) SMC Pulse Register (CS_number = 7) */
+#define REG_SMC_CYCLE7            (0x400E0104U) /**< \brief (SMC) SMC Cycle Register (CS_number = 7) */
+#define REG_SMC_TIMINGS7          (0x400E0108U) /**< \brief (SMC) SMC Timings Register (CS_number = 7) */
+#define REG_SMC_MODE7             (0x400E010CU) /**< \brief (SMC) SMC Mode Register (CS_number = 7) */
+#define REG_SMC_OCMS              (0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
+#define REG_SMC_KEY1              (0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2              (0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPCR              (0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
+#define REG_SMC_WPSR              (0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
+#else
+#define REG_SMC_CFG      (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
+#define REG_SMC_CTRL     (*(WoReg*)0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
+#define REG_SMC_SR       (*(RoReg*)0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
+#define REG_SMC_IER      (*(WoReg*)0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
+#define REG_SMC_IDR      (*(WoReg*)0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
+#define REG_SMC_IMR      (*(RoReg*)0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
+#define REG_SMC_ADDR     (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
+#define REG_SMC_BANK     (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
+#define REG_SMC_ECC_CTRL (*(WoReg*)0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
+#define REG_SMC_ECC_MD   (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
+#define REG_SMC_ECC_SR1  (*(RoReg*)0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
+#define REG_SMC_ECC_PR0  (*(RoReg*)0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
+#define REG_SMC_ECC_PR1  (*(RoReg*)0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
+#define REG_SMC_ECC_SR2  (*(RoReg*)0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
+#define REG_SMC_ECC_PR2  (*(RoReg*)0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
+#define REG_SMC_ECC_PR3  (*(RoReg*)0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
+#define REG_SMC_ECC_PR4  (*(RoReg*)0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
+#define REG_SMC_ECC_PR5  (*(RoReg*)0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
+#define REG_SMC_ECC_PR6  (*(RoReg*)0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
+#define REG_SMC_ECC_PR7  (*(RoReg*)0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
+#define REG_SMC_ECC_PR8  (*(RoReg*)0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
+#define REG_SMC_ECC_PR9  (*(RoReg*)0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
+#define REG_SMC_ECC_PR10 (*(RoReg*)0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
+#define REG_SMC_ECC_PR11 (*(RoReg*)0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
+#define REG_SMC_ECC_PR12 (*(RoReg*)0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
+#define REG_SMC_ECC_PR13 (*(RoReg*)0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
+#define REG_SMC_ECC_PR14 (*(RoReg*)0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
+#define REG_SMC_ECC_PR15 (*(RoReg*)0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
+#define REG_SMC_SETUP0   (*(RwReg*)0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0   (*(RwReg*)0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0   (*(RwReg*)0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_TIMINGS0 (*(RwReg*)0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
+#define REG_SMC_MODE0    (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1   (*(RwReg*)0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1   (*(RwReg*)0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1   (*(RwReg*)0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_TIMINGS1 (*(RwReg*)0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
+#define REG_SMC_MODE1    (*(RwReg*)0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2   (*(RwReg*)0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2   (*(RwReg*)0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2   (*(RwReg*)0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_TIMINGS2 (*(RwReg*)0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
+#define REG_SMC_MODE2    (*(RwReg*)0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3   (*(RwReg*)0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3   (*(RwReg*)0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3   (*(RwReg*)0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_TIMINGS3 (*(RwReg*)0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
+#define REG_SMC_MODE3    (*(RwReg*)0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4   (*(RwReg*)0x400E00C0U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4   (*(RwReg*)0x400E00C4U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4   (*(RwReg*)0x400E00C8U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_TIMINGS4 (*(RwReg*)0x400E00CCU) /**< \brief (SMC) SMC Timings Register (CS_number = 4) */
+#define REG_SMC_MODE4    (*(RwReg*)0x400E00D0U) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_SETUP5   (*(RwReg*)0x400E00D4U) /**< \brief (SMC) SMC Setup Register (CS_number = 5) */
+#define REG_SMC_PULSE5   (*(RwReg*)0x400E00D8U) /**< \brief (SMC) SMC Pulse Register (CS_number = 5) */
+#define REG_SMC_CYCLE5   (*(RwReg*)0x400E00DCU) /**< \brief (SMC) SMC Cycle Register (CS_number = 5) */
+#define REG_SMC_TIMINGS5 (*(RwReg*)0x400E00E0U) /**< \brief (SMC) SMC Timings Register (CS_number = 5) */
+#define REG_SMC_MODE5    (*(RwReg*)0x400E00E4U) /**< \brief (SMC) SMC Mode Register (CS_number = 5) */
+#define REG_SMC_SETUP6   (*(RwReg*)0x400E00E8U) /**< \brief (SMC) SMC Setup Register (CS_number = 6) */
+#define REG_SMC_PULSE6   (*(RwReg*)0x400E00ECU) /**< \brief (SMC) SMC Pulse Register (CS_number = 6) */
+#define REG_SMC_CYCLE6   (*(RwReg*)0x400E00F0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 6) */
+#define REG_SMC_TIMINGS6 (*(RwReg*)0x400E00F4U) /**< \brief (SMC) SMC Timings Register (CS_number = 6) */
+#define REG_SMC_MODE6    (*(RwReg*)0x400E00F8U) /**< \brief (SMC) SMC Mode Register (CS_number = 6) */
+#define REG_SMC_SETUP7   (*(RwReg*)0x400E00FCU) /**< \brief (SMC) SMC Setup Register (CS_number = 7) */
+#define REG_SMC_PULSE7   (*(RwReg*)0x400E0100U) /**< \brief (SMC) SMC Pulse Register (CS_number = 7) */
+#define REG_SMC_CYCLE7   (*(RwReg*)0x400E0104U) /**< \brief (SMC) SMC Cycle Register (CS_number = 7) */
+#define REG_SMC_TIMINGS7 (*(RwReg*)0x400E0108U) /**< \brief (SMC) SMC Timings Register (CS_number = 7) */
+#define REG_SMC_MODE7    (*(RwReg*)0x400E010CU) /**< \brief (SMC) SMC Mode Register (CS_number = 7) */
+#define REG_SMC_OCMS     (*(RwReg*)0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
+#define REG_SMC_KEY1     (*(WoReg*)0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2     (*(WoReg*)0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPCR     (*(WoReg*)0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
+#define REG_SMC_WPSR     (*(RoReg*)0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_SMC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_spi0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_spi0.h
new file mode 100644
index 0000000..aca3ffb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_spi0.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SPI0_INSTANCE_
+#define _SAM3XA_SPI0_INSTANCE_
+
+/* ========== Register definition for SPI0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SPI0_CR              (0x40008000U) /**< \brief (SPI0) Control Register */
+#define REG_SPI0_MR              (0x40008004U) /**< \brief (SPI0) Mode Register */
+#define REG_SPI0_RDR             (0x40008008U) /**< \brief (SPI0) Receive Data Register */
+#define REG_SPI0_TDR             (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
+#define REG_SPI0_SR              (0x40008010U) /**< \brief (SPI0) Status Register */
+#define REG_SPI0_IER             (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
+#define REG_SPI0_IDR             (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
+#define REG_SPI0_IMR             (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
+#define REG_SPI0_CSR             (0x40008030U) /**< \brief (SPI0) Chip Select Register */
+#define REG_SPI0_WPMR            (0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */
+#define REG_SPI0_WPSR            (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
+#else
+#define REG_SPI0_CR     (*(WoReg*)0x40008000U) /**< \brief (SPI0) Control Register */
+#define REG_SPI0_MR     (*(RwReg*)0x40008004U) /**< \brief (SPI0) Mode Register */
+#define REG_SPI0_RDR    (*(RoReg*)0x40008008U) /**< \brief (SPI0) Receive Data Register */
+#define REG_SPI0_TDR    (*(WoReg*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
+#define REG_SPI0_SR     (*(RoReg*)0x40008010U) /**< \brief (SPI0) Status Register */
+#define REG_SPI0_IER    (*(WoReg*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
+#define REG_SPI0_IDR    (*(WoReg*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
+#define REG_SPI0_IMR    (*(RoReg*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
+#define REG_SPI0_CSR    (*(RwReg*)0x40008030U) /**< \brief (SPI0) Chip Select Register */
+#define REG_SPI0_WPMR   (*(RwReg*)0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */
+#define REG_SPI0_WPSR   (*(RoReg*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_SPI0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_spi1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_spi1.h
new file mode 100644
index 0000000..48ecc0e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_spi1.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SPI1_INSTANCE_
+#define _SAM3XA_SPI1_INSTANCE_
+
+/* ========== Register definition for SPI1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SPI1_CR              (0x4000C000U) /**< \brief (SPI1) Control Register */
+#define REG_SPI1_MR              (0x4000C004U) /**< \brief (SPI1) Mode Register */
+#define REG_SPI1_RDR             (0x4000C008U) /**< \brief (SPI1) Receive Data Register */
+#define REG_SPI1_TDR             (0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */
+#define REG_SPI1_SR              (0x4000C010U) /**< \brief (SPI1) Status Register */
+#define REG_SPI1_IER             (0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */
+#define REG_SPI1_IDR             (0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */
+#define REG_SPI1_IMR             (0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */
+#define REG_SPI1_CSR             (0x4000C030U) /**< \brief (SPI1) Chip Select Register */
+#define REG_SPI1_WPMR            (0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */
+#define REG_SPI1_WPSR            (0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */
+#else
+#define REG_SPI1_CR     (*(WoReg*)0x4000C000U) /**< \brief (SPI1) Control Register */
+#define REG_SPI1_MR     (*(RwReg*)0x4000C004U) /**< \brief (SPI1) Mode Register */
+#define REG_SPI1_RDR    (*(RoReg*)0x4000C008U) /**< \brief (SPI1) Receive Data Register */
+#define REG_SPI1_TDR    (*(WoReg*)0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */
+#define REG_SPI1_SR     (*(RoReg*)0x4000C010U) /**< \brief (SPI1) Status Register */
+#define REG_SPI1_IER    (*(WoReg*)0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */
+#define REG_SPI1_IDR    (*(WoReg*)0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */
+#define REG_SPI1_IMR    (*(RoReg*)0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */
+#define REG_SPI1_CSR    (*(RwReg*)0x4000C030U) /**< \brief (SPI1) Chip Select Register */
+#define REG_SPI1_WPMR   (*(RwReg*)0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */
+#define REG_SPI1_WPSR   (*(RoReg*)0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_SPI1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_ssc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_ssc.h
new file mode 100644
index 0000000..db174a2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_ssc.h
@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SSC_INSTANCE_
+#define _SAM3XA_SSC_INSTANCE_
+
+/* ========== Register definition for SSC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SSC_CR            (0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR           (0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR          (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR          (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR          (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR          (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR           (0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR           (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR          (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR          (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R          (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R          (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR            (0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER           (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR           (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR           (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR          (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR          (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#else
+#define REG_SSC_CR   (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR  (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR  (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR  (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR   (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER  (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR  (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR  (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_SSC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_supc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_supc.h
new file mode 100644
index 0000000..154fcda
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_supc.h
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_SUPC_INSTANCE_
+#define _SAM3XA_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SUPC_CR            (0x400E1A10U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR          (0x400E1A14U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR            (0x400E1A18U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR          (0x400E1A1CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR          (0x400E1A20U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR            (0x400E1A24U) /**< \brief (SUPC) Supply Controller Status Register */
+#else
+#define REG_SUPC_CR   (*(WoReg*)0x400E1A10U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1A14U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR   (*(RwReg*)0x400E1A18U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR (*(RwReg*)0x400E1A1CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1A20U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR   (*(RoReg*)0x400E1A24U) /**< \brief (SUPC) Supply Controller Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_SUPC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_tc0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_tc0.h
new file mode 100644
index 0000000..08be078
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_tc0.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TC0_INSTANCE_
+#define _SAM3XA_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC0_CCR0           (0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0           (0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0          (0x40080008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0            (0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0            (0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0            (0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0            (0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0            (0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0           (0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0           (0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0           (0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1           (0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1           (0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1          (0x40080048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1            (0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1            (0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1            (0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1            (0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1            (0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1           (0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1           (0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1           (0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2           (0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2           (0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2          (0x40080088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2            (0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2            (0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2            (0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2            (0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2            (0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2           (0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2           (0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2           (0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR            (0x400800C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR            (0x400800C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER           (0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR           (0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR           (0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR           (0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR            (0x400800D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR           (0x400800E4U) /**< \brief (TC0) Write Protect Mode Register */
+#else
+#define REG_TC0_CCR0  (*(WoReg*)0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0  (*(RwReg*)0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0 (*(RwReg*)0x40080008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0   (*(RoReg*)0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0   (*(RwReg*)0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0   (*(RwReg*)0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0   (*(RwReg*)0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0   (*(RoReg*)0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0  (*(WoReg*)0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0  (*(WoReg*)0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0  (*(RoReg*)0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1  (*(WoReg*)0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1  (*(RwReg*)0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1 (*(RwReg*)0x40080048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1   (*(RoReg*)0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1   (*(RwReg*)0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1   (*(RwReg*)0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1   (*(RwReg*)0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1   (*(RoReg*)0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1  (*(WoReg*)0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1  (*(WoReg*)0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1  (*(RoReg*)0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2  (*(WoReg*)0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2  (*(RwReg*)0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2 (*(RwReg*)0x40080088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2   (*(RoReg*)0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2   (*(RwReg*)0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2   (*(RwReg*)0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2   (*(RwReg*)0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2   (*(RoReg*)0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2  (*(WoReg*)0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2  (*(WoReg*)0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2  (*(RoReg*)0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR   (*(WoReg*)0x400800C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR   (*(RwReg*)0x400800C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER  (*(WoReg*)0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR  (*(WoReg*)0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR  (*(RoReg*)0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR  (*(RoReg*)0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR   (*(RwReg*)0x400800D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR  (*(RwReg*)0x400800E4U) /**< \brief (TC0) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_TC0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_tc1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_tc1.h
new file mode 100644
index 0000000..a4b9510
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_tc1.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TC1_INSTANCE_
+#define _SAM3XA_TC1_INSTANCE_
+
+/* ========== Register definition for TC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC1_CCR0           (0x40084000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0           (0x40084004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0          (0x40084008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0            (0x40084010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0            (0x40084014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0            (0x40084018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0            (0x4008401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0            (0x40084020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0           (0x40084024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0           (0x40084028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0           (0x4008402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1           (0x40084040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1           (0x40084044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1          (0x40084048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1            (0x40084050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1            (0x40084054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1            (0x40084058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1            (0x4008405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1            (0x40084060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1           (0x40084064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1           (0x40084068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1           (0x4008406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2           (0x40084080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2           (0x40084084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2          (0x40084088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2            (0x40084090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2            (0x40084094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2            (0x40084098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2            (0x4008409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2            (0x400840A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2           (0x400840A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2           (0x400840A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2           (0x400840ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR            (0x400840C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR            (0x400840C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER           (0x400840C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR           (0x400840CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR           (0x400840D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR           (0x400840D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR            (0x400840D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR           (0x400840E4U) /**< \brief (TC1) Write Protect Mode Register */
+#else
+#define REG_TC1_CCR0  (*(WoReg*)0x40084000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0  (*(RwReg*)0x40084004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0 (*(RwReg*)0x40084008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0   (*(RoReg*)0x40084010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0   (*(RwReg*)0x40084014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0   (*(RwReg*)0x40084018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0   (*(RwReg*)0x4008401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0   (*(RoReg*)0x40084020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0  (*(WoReg*)0x40084024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0  (*(WoReg*)0x40084028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0  (*(RoReg*)0x4008402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1  (*(WoReg*)0x40084040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1  (*(RwReg*)0x40084044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1 (*(RwReg*)0x40084048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1   (*(RoReg*)0x40084050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1   (*(RwReg*)0x40084054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1   (*(RwReg*)0x40084058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1   (*(RwReg*)0x4008405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1   (*(RoReg*)0x40084060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1  (*(WoReg*)0x40084064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1  (*(WoReg*)0x40084068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1  (*(RoReg*)0x4008406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2  (*(WoReg*)0x40084080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2  (*(RwReg*)0x40084084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2 (*(RwReg*)0x40084088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2   (*(RoReg*)0x40084090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2   (*(RwReg*)0x40084094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2   (*(RwReg*)0x40084098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2   (*(RwReg*)0x4008409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2   (*(RoReg*)0x400840A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2  (*(WoReg*)0x400840A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2  (*(WoReg*)0x400840A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2  (*(RoReg*)0x400840ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR   (*(WoReg*)0x400840C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR   (*(RwReg*)0x400840C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER  (*(WoReg*)0x400840C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR  (*(WoReg*)0x400840CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR  (*(RoReg*)0x400840D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR  (*(RoReg*)0x400840D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR   (*(RwReg*)0x400840D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR  (*(RwReg*)0x400840E4U) /**< \brief (TC1) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_TC1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_tc2.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_tc2.h
new file mode 100644
index 0000000..5846918
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_tc2.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TC2_INSTANCE_
+#define _SAM3XA_TC2_INSTANCE_
+
+/* ========== Register definition for TC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC2_CCR0           (0x40088000U) /**< \brief (TC2) Channel Control Register (channel = 0) */
+#define REG_TC2_CMR0           (0x40088004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */
+#define REG_TC2_SMMR0          (0x40088008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC2_CV0            (0x40088010U) /**< \brief (TC2) Counter Value (channel = 0) */
+#define REG_TC2_RA0            (0x40088014U) /**< \brief (TC2) Register A (channel = 0) */
+#define REG_TC2_RB0            (0x40088018U) /**< \brief (TC2) Register B (channel = 0) */
+#define REG_TC2_RC0            (0x4008801CU) /**< \brief (TC2) Register C (channel = 0) */
+#define REG_TC2_SR0            (0x40088020U) /**< \brief (TC2) Status Register (channel = 0) */
+#define REG_TC2_IER0           (0x40088024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */
+#define REG_TC2_IDR0           (0x40088028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */
+#define REG_TC2_IMR0           (0x4008802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */
+#define REG_TC2_CCR1           (0x40088040U) /**< \brief (TC2) Channel Control Register (channel = 1) */
+#define REG_TC2_CMR1           (0x40088044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */
+#define REG_TC2_SMMR1          (0x40088048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC2_CV1            (0x40088050U) /**< \brief (TC2) Counter Value (channel = 1) */
+#define REG_TC2_RA1            (0x40088054U) /**< \brief (TC2) Register A (channel = 1) */
+#define REG_TC2_RB1            (0x40088058U) /**< \brief (TC2) Register B (channel = 1) */
+#define REG_TC2_RC1            (0x4008805CU) /**< \brief (TC2) Register C (channel = 1) */
+#define REG_TC2_SR1            (0x40088060U) /**< \brief (TC2) Status Register (channel = 1) */
+#define REG_TC2_IER1           (0x40088064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */
+#define REG_TC2_IDR1           (0x40088068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */
+#define REG_TC2_IMR1           (0x4008806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */
+#define REG_TC2_CCR2           (0x40088080U) /**< \brief (TC2) Channel Control Register (channel = 2) */
+#define REG_TC2_CMR2           (0x40088084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */
+#define REG_TC2_SMMR2          (0x40088088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC2_CV2            (0x40088090U) /**< \brief (TC2) Counter Value (channel = 2) */
+#define REG_TC2_RA2            (0x40088094U) /**< \brief (TC2) Register A (channel = 2) */
+#define REG_TC2_RB2            (0x40088098U) /**< \brief (TC2) Register B (channel = 2) */
+#define REG_TC2_RC2            (0x4008809CU) /**< \brief (TC2) Register C (channel = 2) */
+#define REG_TC2_SR2            (0x400880A0U) /**< \brief (TC2) Status Register (channel = 2) */
+#define REG_TC2_IER2           (0x400880A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */
+#define REG_TC2_IDR2           (0x400880A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */
+#define REG_TC2_IMR2           (0x400880ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */
+#define REG_TC2_BCR            (0x400880C0U) /**< \brief (TC2) Block Control Register */
+#define REG_TC2_BMR            (0x400880C4U) /**< \brief (TC2) Block Mode Register */
+#define REG_TC2_QIER           (0x400880C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */
+#define REG_TC2_QIDR           (0x400880CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */
+#define REG_TC2_QIMR           (0x400880D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */
+#define REG_TC2_QISR           (0x400880D4U) /**< \brief (TC2) QDEC Interrupt Status Register */
+#define REG_TC2_FMR            (0x400880D8U) /**< \brief (TC2) Fault Mode Register */
+#define REG_TC2_WPMR           (0x400880E4U) /**< \brief (TC2) Write Protect Mode Register */
+#else
+#define REG_TC2_CCR0  (*(WoReg*)0x40088000U) /**< \brief (TC2) Channel Control Register (channel = 0) */
+#define REG_TC2_CMR0  (*(RwReg*)0x40088004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */
+#define REG_TC2_SMMR0 (*(RwReg*)0x40088008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC2_CV0   (*(RoReg*)0x40088010U) /**< \brief (TC2) Counter Value (channel = 0) */
+#define REG_TC2_RA0   (*(RwReg*)0x40088014U) /**< \brief (TC2) Register A (channel = 0) */
+#define REG_TC2_RB0   (*(RwReg*)0x40088018U) /**< \brief (TC2) Register B (channel = 0) */
+#define REG_TC2_RC0   (*(RwReg*)0x4008801CU) /**< \brief (TC2) Register C (channel = 0) */
+#define REG_TC2_SR0   (*(RoReg*)0x40088020U) /**< \brief (TC2) Status Register (channel = 0) */
+#define REG_TC2_IER0  (*(WoReg*)0x40088024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */
+#define REG_TC2_IDR0  (*(WoReg*)0x40088028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */
+#define REG_TC2_IMR0  (*(RoReg*)0x4008802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */
+#define REG_TC2_CCR1  (*(WoReg*)0x40088040U) /**< \brief (TC2) Channel Control Register (channel = 1) */
+#define REG_TC2_CMR1  (*(RwReg*)0x40088044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */
+#define REG_TC2_SMMR1 (*(RwReg*)0x40088048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC2_CV1   (*(RoReg*)0x40088050U) /**< \brief (TC2) Counter Value (channel = 1) */
+#define REG_TC2_RA1   (*(RwReg*)0x40088054U) /**< \brief (TC2) Register A (channel = 1) */
+#define REG_TC2_RB1   (*(RwReg*)0x40088058U) /**< \brief (TC2) Register B (channel = 1) */
+#define REG_TC2_RC1   (*(RwReg*)0x4008805CU) /**< \brief (TC2) Register C (channel = 1) */
+#define REG_TC2_SR1   (*(RoReg*)0x40088060U) /**< \brief (TC2) Status Register (channel = 1) */
+#define REG_TC2_IER1  (*(WoReg*)0x40088064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */
+#define REG_TC2_IDR1  (*(WoReg*)0x40088068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */
+#define REG_TC2_IMR1  (*(RoReg*)0x4008806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */
+#define REG_TC2_CCR2  (*(WoReg*)0x40088080U) /**< \brief (TC2) Channel Control Register (channel = 2) */
+#define REG_TC2_CMR2  (*(RwReg*)0x40088084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */
+#define REG_TC2_SMMR2 (*(RwReg*)0x40088088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC2_CV2   (*(RoReg*)0x40088090U) /**< \brief (TC2) Counter Value (channel = 2) */
+#define REG_TC2_RA2   (*(RwReg*)0x40088094U) /**< \brief (TC2) Register A (channel = 2) */
+#define REG_TC2_RB2   (*(RwReg*)0x40088098U) /**< \brief (TC2) Register B (channel = 2) */
+#define REG_TC2_RC2   (*(RwReg*)0x4008809CU) /**< \brief (TC2) Register C (channel = 2) */
+#define REG_TC2_SR2   (*(RoReg*)0x400880A0U) /**< \brief (TC2) Status Register (channel = 2) */
+#define REG_TC2_IER2  (*(WoReg*)0x400880A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */
+#define REG_TC2_IDR2  (*(WoReg*)0x400880A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */
+#define REG_TC2_IMR2  (*(RoReg*)0x400880ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */
+#define REG_TC2_BCR   (*(WoReg*)0x400880C0U) /**< \brief (TC2) Block Control Register */
+#define REG_TC2_BMR   (*(RwReg*)0x400880C4U) /**< \brief (TC2) Block Mode Register */
+#define REG_TC2_QIER  (*(WoReg*)0x400880C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */
+#define REG_TC2_QIDR  (*(WoReg*)0x400880CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */
+#define REG_TC2_QIMR  (*(RoReg*)0x400880D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */
+#define REG_TC2_QISR  (*(RoReg*)0x400880D4U) /**< \brief (TC2) QDEC Interrupt Status Register */
+#define REG_TC2_FMR   (*(RwReg*)0x400880D8U) /**< \brief (TC2) Fault Mode Register */
+#define REG_TC2_WPMR  (*(RwReg*)0x400880E4U) /**< \brief (TC2) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_TC2_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_trng.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_trng.h
new file mode 100644
index 0000000..af78925
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_trng.h
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TRNG_INSTANCE_
+#define _SAM3XA_TRNG_INSTANCE_
+
+/* ========== Register definition for TRNG peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TRNG_CR             (0x400BC000U) /**< \brief (TRNG) Control Register */
+#define REG_TRNG_IER            (0x400BC010U) /**< \brief (TRNG) Interrupt Enable Register */
+#define REG_TRNG_IDR            (0x400BC014U) /**< \brief (TRNG) Interrupt Disable Register */
+#define REG_TRNG_IMR            (0x400BC018U) /**< \brief (TRNG) Interrupt Mask Register */
+#define REG_TRNG_ISR            (0x400BC01CU) /**< \brief (TRNG) Interrupt Status Register */
+#define REG_TRNG_ODATA          (0x400BC050U) /**< \brief (TRNG) Output Data Register */
+#else
+#define REG_TRNG_CR    (*(WoReg*)0x400BC000U) /**< \brief (TRNG) Control Register */
+#define REG_TRNG_IER   (*(WoReg*)0x400BC010U) /**< \brief (TRNG) Interrupt Enable Register */
+#define REG_TRNG_IDR   (*(WoReg*)0x400BC014U) /**< \brief (TRNG) Interrupt Disable Register */
+#define REG_TRNG_IMR   (*(RoReg*)0x400BC018U) /**< \brief (TRNG) Interrupt Mask Register */
+#define REG_TRNG_ISR   (*(RoReg*)0x400BC01CU) /**< \brief (TRNG) Interrupt Status Register */
+#define REG_TRNG_ODATA (*(RoReg*)0x400BC050U) /**< \brief (TRNG) Output Data Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_TRNG_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_twi0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_twi0.h
new file mode 100644
index 0000000..fa20773
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_twi0.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TWI0_INSTANCE_
+#define _SAM3XA_TWI0_INSTANCE_
+
+/* ========== Register definition for TWI0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TWI0_CR            (0x4008C000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR           (0x4008C004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR           (0x4008C008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR          (0x4008C00CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR          (0x4008C010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR            (0x4008C020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER           (0x4008C024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR           (0x4008C028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR           (0x4008C02CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR           (0x4008C030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR           (0x4008C034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR           (0x4008C100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR           (0x4008C104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR           (0x4008C108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR           (0x4008C10CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR          (0x4008C110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR          (0x4008C114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR          (0x4008C118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR          (0x4008C11CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR          (0x4008C120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR          (0x4008C124U) /**< \brief (TWI0) Transfer Status Register */
+#else
+#define REG_TWI0_CR   (*(WoReg*)0x4008C000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR  (*(RwReg*)0x4008C004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR  (*(RwReg*)0x4008C008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR (*(RwReg*)0x4008C00CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR (*(RwReg*)0x4008C010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR   (*(RoReg*)0x4008C020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER  (*(WoReg*)0x4008C024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR  (*(WoReg*)0x4008C028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR  (*(RoReg*)0x4008C02CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR  (*(RoReg*)0x4008C030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR  (*(WoReg*)0x4008C034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR  (*(RwReg*)0x4008C100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR  (*(RwReg*)0x4008C104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR  (*(RwReg*)0x4008C108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR  (*(RwReg*)0x4008C10CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR (*(RwReg*)0x4008C110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR (*(RwReg*)0x4008C114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR (*(RwReg*)0x4008C118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR (*(RwReg*)0x4008C11CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR (*(WoReg*)0x4008C120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR (*(RoReg*)0x4008C124U) /**< \brief (TWI0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_TWI0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_twi1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_twi1.h
new file mode 100644
index 0000000..3427f61
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_twi1.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_TWI1_INSTANCE_
+#define _SAM3XA_TWI1_INSTANCE_
+
+/* ========== Register definition for TWI1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TWI1_CR            (0x40090000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR           (0x40090004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR           (0x40090008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR          (0x4009000CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR          (0x40090010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR            (0x40090020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER           (0x40090024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR           (0x40090028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR           (0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR           (0x40090030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR           (0x40090034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR           (0x40090100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR           (0x40090104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR           (0x40090108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR           (0x4009010CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR          (0x40090110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR          (0x40090114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR          (0x40090118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR          (0x4009011CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR          (0x40090120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR          (0x40090124U) /**< \brief (TWI1) Transfer Status Register */
+#else
+#define REG_TWI1_CR   (*(WoReg*)0x40090000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR  (*(RwReg*)0x40090004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR  (*(RwReg*)0x40090008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR (*(RwReg*)0x4009000CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR (*(RwReg*)0x40090010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR   (*(RoReg*)0x40090020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER  (*(WoReg*)0x40090024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR  (*(WoReg*)0x40090028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR  (*(RoReg*)0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR  (*(RoReg*)0x40090030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR  (*(WoReg*)0x40090034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR  (*(RwReg*)0x40090100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR  (*(RwReg*)0x40090104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR  (*(RwReg*)0x40090108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR  (*(RwReg*)0x4009010CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR (*(RwReg*)0x40090110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR (*(RwReg*)0x40090114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR (*(RwReg*)0x40090118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR (*(RwReg*)0x4009011CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR (*(WoReg*)0x40090120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR (*(RoReg*)0x40090124U) /**< \brief (TWI1) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_TWI1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_uart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_uart.h
new file mode 100644
index 0000000..9c8e1d5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_uart.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_UART_INSTANCE_
+#define _SAM3XA_UART_INSTANCE_
+
+/* ========== Register definition for UART peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UART_CR            (0x400E0800U) /**< \brief (UART) Control Register */
+#define REG_UART_MR            (0x400E0804U) /**< \brief (UART) Mode Register */
+#define REG_UART_IER           (0x400E0808U) /**< \brief (UART) Interrupt Enable Register */
+#define REG_UART_IDR           (0x400E080CU) /**< \brief (UART) Interrupt Disable Register */
+#define REG_UART_IMR           (0x400E0810U) /**< \brief (UART) Interrupt Mask Register */
+#define REG_UART_SR            (0x400E0814U) /**< \brief (UART) Status Register */
+#define REG_UART_RHR           (0x400E0818U) /**< \brief (UART) Receive Holding Register */
+#define REG_UART_THR           (0x400E081CU) /**< \brief (UART) Transmit Holding Register */
+#define REG_UART_BRGR          (0x400E0820U) /**< \brief (UART) Baud Rate Generator Register */
+#define REG_UART_RPR           (0x400E0900U) /**< \brief (UART) Receive Pointer Register */
+#define REG_UART_RCR           (0x400E0904U) /**< \brief (UART) Receive Counter Register */
+#define REG_UART_TPR           (0x400E0908U) /**< \brief (UART) Transmit Pointer Register */
+#define REG_UART_TCR           (0x400E090CU) /**< \brief (UART) Transmit Counter Register */
+#define REG_UART_RNPR          (0x400E0910U) /**< \brief (UART) Receive Next Pointer Register */
+#define REG_UART_RNCR          (0x400E0914U) /**< \brief (UART) Receive Next Counter Register */
+#define REG_UART_TNPR          (0x400E0918U) /**< \brief (UART) Transmit Next Pointer Register */
+#define REG_UART_TNCR          (0x400E091CU) /**< \brief (UART) Transmit Next Counter Register */
+#define REG_UART_PTCR          (0x400E0920U) /**< \brief (UART) Transfer Control Register */
+#define REG_UART_PTSR          (0x400E0924U) /**< \brief (UART) Transfer Status Register */
+#else
+#define REG_UART_CR   (*(WoReg*)0x400E0800U) /**< \brief (UART) Control Register */
+#define REG_UART_MR   (*(RwReg*)0x400E0804U) /**< \brief (UART) Mode Register */
+#define REG_UART_IER  (*(WoReg*)0x400E0808U) /**< \brief (UART) Interrupt Enable Register */
+#define REG_UART_IDR  (*(WoReg*)0x400E080CU) /**< \brief (UART) Interrupt Disable Register */
+#define REG_UART_IMR  (*(RoReg*)0x400E0810U) /**< \brief (UART) Interrupt Mask Register */
+#define REG_UART_SR   (*(RoReg*)0x400E0814U) /**< \brief (UART) Status Register */
+#define REG_UART_RHR  (*(RoReg*)0x400E0818U) /**< \brief (UART) Receive Holding Register */
+#define REG_UART_THR  (*(WoReg*)0x400E081CU) /**< \brief (UART) Transmit Holding Register */
+#define REG_UART_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART) Baud Rate Generator Register */
+#define REG_UART_RPR  (*(RwReg*)0x400E0900U) /**< \brief (UART) Receive Pointer Register */
+#define REG_UART_RCR  (*(RwReg*)0x400E0904U) /**< \brief (UART) Receive Counter Register */
+#define REG_UART_TPR  (*(RwReg*)0x400E0908U) /**< \brief (UART) Transmit Pointer Register */
+#define REG_UART_TCR  (*(RwReg*)0x400E090CU) /**< \brief (UART) Transmit Counter Register */
+#define REG_UART_RNPR (*(RwReg*)0x400E0910U) /**< \brief (UART) Receive Next Pointer Register */
+#define REG_UART_RNCR (*(RwReg*)0x400E0914U) /**< \brief (UART) Receive Next Counter Register */
+#define REG_UART_TNPR (*(RwReg*)0x400E0918U) /**< \brief (UART) Transmit Next Pointer Register */
+#define REG_UART_TNCR (*(RwReg*)0x400E091CU) /**< \brief (UART) Transmit Next Counter Register */
+#define REG_UART_PTCR (*(WoReg*)0x400E0920U) /**< \brief (UART) Transfer Control Register */
+#define REG_UART_PTSR (*(RoReg*)0x400E0924U) /**< \brief (UART) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_UART_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_uotghs.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_uotghs.h
new file mode 100644
index 0000000..fabdab1
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_uotghs.h
@@ -0,0 +1,234 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_UOTGHS_INSTANCE_
+#define _SAM3XA_UOTGHS_INSTANCE_
+
+/* ========== Register definition for UOTGHS peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UOTGHS_DEVCTRL                 (0x400AC000U) /**< \brief (UOTGHS) Device General Control Register */
+#define REG_UOTGHS_DEVISR                  (0x400AC004U) /**< \brief (UOTGHS) Device Global Interrupt Status Register */
+#define REG_UOTGHS_DEVICR                  (0x400AC008U) /**< \brief (UOTGHS) Device Global Interrupt Clear Register */
+#define REG_UOTGHS_DEVIFR                  (0x400AC00CU) /**< \brief (UOTGHS) Device Global Interrupt Set Register */
+#define REG_UOTGHS_DEVIMR                  (0x400AC010U) /**< \brief (UOTGHS) Device Global Interrupt Mask Register */
+#define REG_UOTGHS_DEVIDR                  (0x400AC014U) /**< \brief (UOTGHS) Device Global Interrupt Disable Register */
+#define REG_UOTGHS_DEVIER                  (0x400AC018U) /**< \brief (UOTGHS) Device Global Interrupt Enable Register */
+#define REG_UOTGHS_DEVEPT                  (0x400AC01CU) /**< \brief (UOTGHS) Device Endpoint Register */
+#define REG_UOTGHS_DEVFNUM                 (0x400AC020U) /**< \brief (UOTGHS) Device Frame Number Register */
+#define REG_UOTGHS_DEVEPTCFG               (0x400AC100U) /**< \brief (UOTGHS) Device Endpoint Configuration Register (n = 0) */
+#define REG_UOTGHS_DEVEPTISR               (0x400AC130U) /**< \brief (UOTGHS) Device Endpoint Status Register (n = 0) */
+#define REG_UOTGHS_DEVEPTICR               (0x400AC160U) /**< \brief (UOTGHS) Device Endpoint Clear Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIFR               (0x400AC190U) /**< \brief (UOTGHS) Device Endpoint Set Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIMR               (0x400AC1C0U) /**< \brief (UOTGHS) Device Endpoint Mask Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIER               (0x400AC1F0U) /**< \brief (UOTGHS) Device Endpoint Enable Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIDR               (0x400AC220U) /**< \brief (UOTGHS) Device Endpoint Disable Register (n = 0) */
+#define REG_UOTGHS_DEVDMANXTDSC1           (0x400AC310U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 1) */
+#define REG_UOTGHS_DEVDMAADDRESS1          (0x400AC314U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 1) */
+#define REG_UOTGHS_DEVDMACONTROL1          (0x400AC318U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 1) */
+#define REG_UOTGHS_DEVDMASTATUS1           (0x400AC31CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 1) */
+#define REG_UOTGHS_DEVDMANXTDSC2           (0x400AC320U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 2) */
+#define REG_UOTGHS_DEVDMAADDRESS2          (0x400AC324U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 2) */
+#define REG_UOTGHS_DEVDMACONTROL2          (0x400AC328U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 2) */
+#define REG_UOTGHS_DEVDMASTATUS2           (0x400AC32CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 2) */
+#define REG_UOTGHS_DEVDMANXTDSC3           (0x400AC330U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 3) */
+#define REG_UOTGHS_DEVDMAADDRESS3          (0x400AC334U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 3) */
+#define REG_UOTGHS_DEVDMACONTROL3          (0x400AC338U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 3) */
+#define REG_UOTGHS_DEVDMASTATUS3           (0x400AC33CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 3) */
+#define REG_UOTGHS_DEVDMANXTDSC4           (0x400AC340U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 4) */
+#define REG_UOTGHS_DEVDMAADDRESS4          (0x400AC344U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 4) */
+#define REG_UOTGHS_DEVDMACONTROL4          (0x400AC348U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 4) */
+#define REG_UOTGHS_DEVDMASTATUS4           (0x400AC34CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 4) */
+#define REG_UOTGHS_DEVDMANXTDSC5           (0x400AC350U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 5) */
+#define REG_UOTGHS_DEVDMAADDRESS5          (0x400AC354U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 5) */
+#define REG_UOTGHS_DEVDMACONTROL5          (0x400AC358U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 5) */
+#define REG_UOTGHS_DEVDMASTATUS5           (0x400AC35CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 5) */
+#define REG_UOTGHS_DEVDMANXTDSC6           (0x400AC360U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 6) */
+#define REG_UOTGHS_DEVDMAADDRESS6          (0x400AC364U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 6) */
+#define REG_UOTGHS_DEVDMACONTROL6          (0x400AC368U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 6) */
+#define REG_UOTGHS_DEVDMASTATUS6           (0x400AC36CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 6) */
+#define REG_UOTGHS_DEVDMANXTDSC7           (0x400AC370U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 7) */
+#define REG_UOTGHS_DEVDMAADDRESS7          (0x400AC374U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 7) */
+#define REG_UOTGHS_DEVDMACONTROL7          (0x400AC378U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 7) */
+#define REG_UOTGHS_DEVDMASTATUS7           (0x400AC37CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 7) */
+#define REG_UOTGHS_HSTCTRL                 (0x400AC400U) /**< \brief (UOTGHS) Host General Control Register */
+#define REG_UOTGHS_HSTISR                  (0x400AC404U) /**< \brief (UOTGHS) Host Global Interrupt Status Register */
+#define REG_UOTGHS_HSTICR                  (0x400AC408U) /**< \brief (UOTGHS) Host Global Interrupt Clear Register */
+#define REG_UOTGHS_HSTIFR                  (0x400AC40CU) /**< \brief (UOTGHS) Host Global Interrupt Set Register */
+#define REG_UOTGHS_HSTIMR                  (0x400AC410U) /**< \brief (UOTGHS) Host Global Interrupt Mask Register */
+#define REG_UOTGHS_HSTIDR                  (0x400AC414U) /**< \brief (UOTGHS) Host Global Interrupt Disable Register */
+#define REG_UOTGHS_HSTIER                  (0x400AC418U) /**< \brief (UOTGHS) Host Global Interrupt Enable Register */
+#define REG_UOTGHS_HSTPIP                  (0x400AC41CU) /**< \brief (UOTGHS) Host Pipe Register */
+#define REG_UOTGHS_HSTFNUM                 (0x400AC420U) /**< \brief (UOTGHS) Host Frame Number Register */
+#define REG_UOTGHS_HSTADDR1                (0x400AC424U) /**< \brief (UOTGHS) Host Address 1 Register */
+#define REG_UOTGHS_HSTADDR2                (0x400AC428U) /**< \brief (UOTGHS) Host Address 2 Register */
+#define REG_UOTGHS_HSTADDR3                (0x400AC42CU) /**< \brief (UOTGHS) Host Address 3 Register */
+#define REG_UOTGHS_HSTPIPCFG               (0x400AC500U) /**< \brief (UOTGHS) Host Pipe Configuration Register (n = 0) */
+#define REG_UOTGHS_HSTPIPISR               (0x400AC530U) /**< \brief (UOTGHS) Host Pipe Status Register (n = 0) */
+#define REG_UOTGHS_HSTPIPICR               (0x400AC560U) /**< \brief (UOTGHS) Host Pipe Clear Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIFR               (0x400AC590U) /**< \brief (UOTGHS) Host Pipe Set Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIMR               (0x400AC5C0U) /**< \brief (UOTGHS) Host Pipe Mask Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIER               (0x400AC5F0U) /**< \brief (UOTGHS) Host Pipe Enable Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIDR               (0x400AC620U) /**< \brief (UOTGHS) Host Pipe Disable Register (n = 0) */
+#define REG_UOTGHS_HSTPIPINRQ              (0x400AC650U) /**< \brief (UOTGHS) Host Pipe IN Request Register (n = 0) */
+#define REG_UOTGHS_HSTPIPERR               (0x400AC680U) /**< \brief (UOTGHS) Host Pipe Error Register (n = 0) */
+#define REG_UOTGHS_HSTDMANXTDSC1           (0x400AC710U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 1) */
+#define REG_UOTGHS_HSTDMAADDRESS1          (0x400AC714U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 1) */
+#define REG_UOTGHS_HSTDMACONTROL1          (0x400AC718U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 1) */
+#define REG_UOTGHS_HSTDMASTATUS1           (0x400AC71CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 1) */
+#define REG_UOTGHS_HSTDMANXTDSC2           (0x400AC720U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 2) */
+#define REG_UOTGHS_HSTDMAADDRESS2          (0x400AC724U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 2) */
+#define REG_UOTGHS_HSTDMACONTROL2          (0x400AC728U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 2) */
+#define REG_UOTGHS_HSTDMASTATUS2           (0x400AC72CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 2) */
+#define REG_UOTGHS_HSTDMANXTDSC3           (0x400AC730U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 3) */
+#define REG_UOTGHS_HSTDMAADDRESS3          (0x400AC734U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 3) */
+#define REG_UOTGHS_HSTDMACONTROL3          (0x400AC738U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 3) */
+#define REG_UOTGHS_HSTDMASTATUS3           (0x400AC73CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 3) */
+#define REG_UOTGHS_HSTDMANXTDSC4           (0x400AC740U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 4) */
+#define REG_UOTGHS_HSTDMAADDRESS4          (0x400AC744U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 4) */
+#define REG_UOTGHS_HSTDMACONTROL4          (0x400AC748U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 4) */
+#define REG_UOTGHS_HSTDMASTATUS4           (0x400AC74CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 4) */
+#define REG_UOTGHS_HSTDMANXTDSC5           (0x400AC750U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 5) */
+#define REG_UOTGHS_HSTDMAADDRESS5          (0x400AC754U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 5) */
+#define REG_UOTGHS_HSTDMACONTROL5          (0x400AC758U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 5) */
+#define REG_UOTGHS_HSTDMASTATUS5           (0x400AC75CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 5) */
+#define REG_UOTGHS_HSTDMANXTDSC6           (0x400AC760U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 6) */
+#define REG_UOTGHS_HSTDMAADDRESS6          (0x400AC764U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 6) */
+#define REG_UOTGHS_HSTDMACONTROL6          (0x400AC768U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 6) */
+#define REG_UOTGHS_HSTDMASTATUS6           (0x400AC76CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 6) */
+#define REG_UOTGHS_HSTDMANXTDSC7           (0x400AC770U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 7) */
+#define REG_UOTGHS_HSTDMAADDRESS7          (0x400AC774U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 7) */
+#define REG_UOTGHS_HSTDMACONTROL7          (0x400AC778U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 7) */
+#define REG_UOTGHS_HSTDMASTATUS7           (0x400AC77CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 7) */
+#define REG_UOTGHS_CTRL                    (0x400AC800U) /**< \brief (UOTGHS) General Control Register */
+#define REG_UOTGHS_SR                      (0x400AC804U) /**< \brief (UOTGHS) General Status Register */
+#define REG_UOTGHS_SCR                     (0x400AC808U) /**< \brief (UOTGHS) General Status Clear Register */
+#define REG_UOTGHS_SFR                     (0x400AC80CU) /**< \brief (UOTGHS) General Status Set Register */
+#define REG_UOTGHS_FSM                     (0x400AC82CU) /**< \brief (UOTGHS) General Finite State Machine Register */
+#else
+#define REG_UOTGHS_DEVCTRL        (*(RwReg*)0x400AC000U) /**< \brief (UOTGHS) Device General Control Register */
+#define REG_UOTGHS_DEVISR         (*(RoReg*)0x400AC004U) /**< \brief (UOTGHS) Device Global Interrupt Status Register */
+#define REG_UOTGHS_DEVICR         (*(WoReg*)0x400AC008U) /**< \brief (UOTGHS) Device Global Interrupt Clear Register */
+#define REG_UOTGHS_DEVIFR         (*(WoReg*)0x400AC00CU) /**< \brief (UOTGHS) Device Global Interrupt Set Register */
+#define REG_UOTGHS_DEVIMR         (*(RoReg*)0x400AC010U) /**< \brief (UOTGHS) Device Global Interrupt Mask Register */
+#define REG_UOTGHS_DEVIDR         (*(WoReg*)0x400AC014U) /**< \brief (UOTGHS) Device Global Interrupt Disable Register */
+#define REG_UOTGHS_DEVIER         (*(WoReg*)0x400AC018U) /**< \brief (UOTGHS) Device Global Interrupt Enable Register */
+#define REG_UOTGHS_DEVEPT         (*(RwReg*)0x400AC01CU) /**< \brief (UOTGHS) Device Endpoint Register */
+#define REG_UOTGHS_DEVFNUM        (*(RoReg*)0x400AC020U) /**< \brief (UOTGHS) Device Frame Number Register */
+#define REG_UOTGHS_DEVEPTCFG      (*(RwReg*)0x400AC100U) /**< \brief (UOTGHS) Device Endpoint Configuration Register (n = 0) */
+#define REG_UOTGHS_DEVEPTISR      (*(RoReg*)0x400AC130U) /**< \brief (UOTGHS) Device Endpoint Status Register (n = 0) */
+#define REG_UOTGHS_DEVEPTICR      (*(WoReg*)0x400AC160U) /**< \brief (UOTGHS) Device Endpoint Clear Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIFR      (*(WoReg*)0x400AC190U) /**< \brief (UOTGHS) Device Endpoint Set Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIMR      (*(RoReg*)0x400AC1C0U) /**< \brief (UOTGHS) Device Endpoint Mask Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIER      (*(WoReg*)0x400AC1F0U) /**< \brief (UOTGHS) Device Endpoint Enable Register (n = 0) */
+#define REG_UOTGHS_DEVEPTIDR      (*(WoReg*)0x400AC220U) /**< \brief (UOTGHS) Device Endpoint Disable Register (n = 0) */
+#define REG_UOTGHS_DEVDMANXTDSC1  (*(RwReg*)0x400AC310U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 1) */
+#define REG_UOTGHS_DEVDMAADDRESS1 (*(RwReg*)0x400AC314U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 1) */
+#define REG_UOTGHS_DEVDMACONTROL1 (*(RwReg*)0x400AC318U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 1) */
+#define REG_UOTGHS_DEVDMASTATUS1  (*(RwReg*)0x400AC31CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 1) */
+#define REG_UOTGHS_DEVDMANXTDSC2  (*(RwReg*)0x400AC320U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 2) */
+#define REG_UOTGHS_DEVDMAADDRESS2 (*(RwReg*)0x400AC324U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 2) */
+#define REG_UOTGHS_DEVDMACONTROL2 (*(RwReg*)0x400AC328U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 2) */
+#define REG_UOTGHS_DEVDMASTATUS2  (*(RwReg*)0x400AC32CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 2) */
+#define REG_UOTGHS_DEVDMANXTDSC3  (*(RwReg*)0x400AC330U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 3) */
+#define REG_UOTGHS_DEVDMAADDRESS3 (*(RwReg*)0x400AC334U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 3) */
+#define REG_UOTGHS_DEVDMACONTROL3 (*(RwReg*)0x400AC338U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 3) */
+#define REG_UOTGHS_DEVDMASTATUS3  (*(RwReg*)0x400AC33CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 3) */
+#define REG_UOTGHS_DEVDMANXTDSC4  (*(RwReg*)0x400AC340U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 4) */
+#define REG_UOTGHS_DEVDMAADDRESS4 (*(RwReg*)0x400AC344U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 4) */
+#define REG_UOTGHS_DEVDMACONTROL4 (*(RwReg*)0x400AC348U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 4) */
+#define REG_UOTGHS_DEVDMASTATUS4  (*(RwReg*)0x400AC34CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 4) */
+#define REG_UOTGHS_DEVDMANXTDSC5  (*(RwReg*)0x400AC350U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 5) */
+#define REG_UOTGHS_DEVDMAADDRESS5 (*(RwReg*)0x400AC354U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 5) */
+#define REG_UOTGHS_DEVDMACONTROL5 (*(RwReg*)0x400AC358U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 5) */
+#define REG_UOTGHS_DEVDMASTATUS5  (*(RwReg*)0x400AC35CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 5) */
+#define REG_UOTGHS_DEVDMANXTDSC6  (*(RwReg*)0x400AC360U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 6) */
+#define REG_UOTGHS_DEVDMAADDRESS6 (*(RwReg*)0x400AC364U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 6) */
+#define REG_UOTGHS_DEVDMACONTROL6 (*(RwReg*)0x400AC368U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 6) */
+#define REG_UOTGHS_DEVDMASTATUS6  (*(RwReg*)0x400AC36CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 6) */
+#define REG_UOTGHS_DEVDMANXTDSC7  (*(RwReg*)0x400AC370U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 7) */
+#define REG_UOTGHS_DEVDMAADDRESS7 (*(RwReg*)0x400AC374U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 7) */
+#define REG_UOTGHS_DEVDMACONTROL7 (*(RwReg*)0x400AC378U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 7) */
+#define REG_UOTGHS_DEVDMASTATUS7  (*(RwReg*)0x400AC37CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 7) */
+#define REG_UOTGHS_HSTCTRL        (*(RwReg*)0x400AC400U) /**< \brief (UOTGHS) Host General Control Register */
+#define REG_UOTGHS_HSTISR         (*(RoReg*)0x400AC404U) /**< \brief (UOTGHS) Host Global Interrupt Status Register */
+#define REG_UOTGHS_HSTICR         (*(WoReg*)0x400AC408U) /**< \brief (UOTGHS) Host Global Interrupt Clear Register */
+#define REG_UOTGHS_HSTIFR         (*(WoReg*)0x400AC40CU) /**< \brief (UOTGHS) Host Global Interrupt Set Register */
+#define REG_UOTGHS_HSTIMR         (*(RoReg*)0x400AC410U) /**< \brief (UOTGHS) Host Global Interrupt Mask Register */
+#define REG_UOTGHS_HSTIDR         (*(WoReg*)0x400AC414U) /**< \brief (UOTGHS) Host Global Interrupt Disable Register */
+#define REG_UOTGHS_HSTIER         (*(WoReg*)0x400AC418U) /**< \brief (UOTGHS) Host Global Interrupt Enable Register */
+#define REG_UOTGHS_HSTPIP         (*(RwReg*)0x400AC41CU) /**< \brief (UOTGHS) Host Pipe Register */
+#define REG_UOTGHS_HSTFNUM        (*(RwReg*)0x400AC420U) /**< \brief (UOTGHS) Host Frame Number Register */
+#define REG_UOTGHS_HSTADDR1       (*(RwReg*)0x400AC424U) /**< \brief (UOTGHS) Host Address 1 Register */
+#define REG_UOTGHS_HSTADDR2       (*(RwReg*)0x400AC428U) /**< \brief (UOTGHS) Host Address 2 Register */
+#define REG_UOTGHS_HSTADDR3       (*(RwReg*)0x400AC42CU) /**< \brief (UOTGHS) Host Address 3 Register */
+#define REG_UOTGHS_HSTPIPCFG      (*(RwReg*)0x400AC500U) /**< \brief (UOTGHS) Host Pipe Configuration Register (n = 0) */
+#define REG_UOTGHS_HSTPIPISR      (*(RoReg*)0x400AC530U) /**< \brief (UOTGHS) Host Pipe Status Register (n = 0) */
+#define REG_UOTGHS_HSTPIPICR      (*(WoReg*)0x400AC560U) /**< \brief (UOTGHS) Host Pipe Clear Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIFR      (*(WoReg*)0x400AC590U) /**< \brief (UOTGHS) Host Pipe Set Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIMR      (*(RoReg*)0x400AC5C0U) /**< \brief (UOTGHS) Host Pipe Mask Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIER      (*(WoReg*)0x400AC5F0U) /**< \brief (UOTGHS) Host Pipe Enable Register (n = 0) */
+#define REG_UOTGHS_HSTPIPIDR      (*(WoReg*)0x400AC620U) /**< \brief (UOTGHS) Host Pipe Disable Register (n = 0) */
+#define REG_UOTGHS_HSTPIPINRQ     (*(RwReg*)0x400AC650U) /**< \brief (UOTGHS) Host Pipe IN Request Register (n = 0) */
+#define REG_UOTGHS_HSTPIPERR      (*(RwReg*)0x400AC680U) /**< \brief (UOTGHS) Host Pipe Error Register (n = 0) */
+#define REG_UOTGHS_HSTDMANXTDSC1  (*(RwReg*)0x400AC710U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 1) */
+#define REG_UOTGHS_HSTDMAADDRESS1 (*(RwReg*)0x400AC714U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 1) */
+#define REG_UOTGHS_HSTDMACONTROL1 (*(RwReg*)0x400AC718U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 1) */
+#define REG_UOTGHS_HSTDMASTATUS1  (*(RwReg*)0x400AC71CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 1) */
+#define REG_UOTGHS_HSTDMANXTDSC2  (*(RwReg*)0x400AC720U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 2) */
+#define REG_UOTGHS_HSTDMAADDRESS2 (*(RwReg*)0x400AC724U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 2) */
+#define REG_UOTGHS_HSTDMACONTROL2 (*(RwReg*)0x400AC728U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 2) */
+#define REG_UOTGHS_HSTDMASTATUS2  (*(RwReg*)0x400AC72CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 2) */
+#define REG_UOTGHS_HSTDMANXTDSC3  (*(RwReg*)0x400AC730U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 3) */
+#define REG_UOTGHS_HSTDMAADDRESS3 (*(RwReg*)0x400AC734U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 3) */
+#define REG_UOTGHS_HSTDMACONTROL3 (*(RwReg*)0x400AC738U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 3) */
+#define REG_UOTGHS_HSTDMASTATUS3  (*(RwReg*)0x400AC73CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 3) */
+#define REG_UOTGHS_HSTDMANXTDSC4  (*(RwReg*)0x400AC740U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 4) */
+#define REG_UOTGHS_HSTDMAADDRESS4 (*(RwReg*)0x400AC744U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 4) */
+#define REG_UOTGHS_HSTDMACONTROL4 (*(RwReg*)0x400AC748U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 4) */
+#define REG_UOTGHS_HSTDMASTATUS4  (*(RwReg*)0x400AC74CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 4) */
+#define REG_UOTGHS_HSTDMANXTDSC5  (*(RwReg*)0x400AC750U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 5) */
+#define REG_UOTGHS_HSTDMAADDRESS5 (*(RwReg*)0x400AC754U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 5) */
+#define REG_UOTGHS_HSTDMACONTROL5 (*(RwReg*)0x400AC758U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 5) */
+#define REG_UOTGHS_HSTDMASTATUS5  (*(RwReg*)0x400AC75CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 5) */
+#define REG_UOTGHS_HSTDMANXTDSC6  (*(RwReg*)0x400AC760U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 6) */
+#define REG_UOTGHS_HSTDMAADDRESS6 (*(RwReg*)0x400AC764U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 6) */
+#define REG_UOTGHS_HSTDMACONTROL6 (*(RwReg*)0x400AC768U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 6) */
+#define REG_UOTGHS_HSTDMASTATUS6  (*(RwReg*)0x400AC76CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 6) */
+#define REG_UOTGHS_HSTDMANXTDSC7  (*(RwReg*)0x400AC770U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 7) */
+#define REG_UOTGHS_HSTDMAADDRESS7 (*(RwReg*)0x400AC774U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 7) */
+#define REG_UOTGHS_HSTDMACONTROL7 (*(RwReg*)0x400AC778U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 7) */
+#define REG_UOTGHS_HSTDMASTATUS7  (*(RwReg*)0x400AC77CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 7) */
+#define REG_UOTGHS_CTRL           (*(RwReg*)0x400AC800U) /**< \brief (UOTGHS) General Control Register */
+#define REG_UOTGHS_SR             (*(RoReg*)0x400AC804U) /**< \brief (UOTGHS) General Status Register */
+#define REG_UOTGHS_SCR            (*(WoReg*)0x400AC808U) /**< \brief (UOTGHS) General Status Clear Register */
+#define REG_UOTGHS_SFR            (*(WoReg*)0x400AC80CU) /**< \brief (UOTGHS) General Status Set Register */
+#define REG_UOTGHS_FSM            (*(RoReg*)0x400AC82CU) /**< \brief (UOTGHS) General Finite State Machine Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_UOTGHS_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_usart0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_usart0.h
new file mode 100644
index 0000000..d5ece71
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_usart0.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_USART0_INSTANCE_
+#define _SAM3XA_USART0_INSTANCE_
+
+/* ========== Register definition for USART0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART0_CR          (0x40098000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR          (0x40098004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER          (0x40098008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR          (0x4009800CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR          (0x40098010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR          (0x40098014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR          (0x40098018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR          (0x4009801CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR          (0x40098020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR          (0x40098024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR          (0x40098028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI          (0x40098040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER          (0x40098044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF          (0x4009804CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN          (0x40098050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_LINMR          (0x40098054U) /**< \brief (USART0) LIN Mode Register */
+#define REG_USART0_LINIR          (0x40098058U) /**< \brief (USART0) LIN Identifier Register */
+#define REG_USART0_WPMR          (0x400980E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR          (0x400980E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_RPR          (0x40098100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR          (0x40098104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR          (0x40098108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR          (0x4009810CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR          (0x40098110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR          (0x40098114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR          (0x40098118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR          (0x4009811CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR          (0x40098120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR          (0x40098124U) /**< \brief (USART0) Transfer Status Register */
+#else
+#define REG_USART0_CR (*(WoReg*)0x40098000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR (*(RwReg*)0x40098004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER (*(WoReg*)0x40098008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR (*(WoReg*)0x4009800CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR (*(RoReg*)0x40098010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR (*(RoReg*)0x40098014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR (*(RoReg*)0x40098018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR (*(WoReg*)0x4009801CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR (*(RwReg*)0x40098020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR (*(RwReg*)0x40098024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR (*(RwReg*)0x40098028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI (*(RwReg*)0x40098040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER (*(RoReg*)0x40098044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF (*(RwReg*)0x4009804CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN (*(RwReg*)0x40098050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_LINMR (*(RwReg*)0x40098054U) /**< \brief (USART0) LIN Mode Register */
+#define REG_USART0_LINIR (*(RwReg*)0x40098058U) /**< \brief (USART0) LIN Identifier Register */
+#define REG_USART0_WPMR (*(RwReg*)0x400980E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR (*(RoReg*)0x400980E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_RPR (*(RwReg*)0x40098100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR (*(RwReg*)0x40098104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR (*(RwReg*)0x40098108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR (*(RwReg*)0x4009810CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR (*(RwReg*)0x40098110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR (*(RwReg*)0x40098114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR (*(RwReg*)0x40098118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR (*(RwReg*)0x4009811CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR (*(WoReg*)0x40098120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR (*(RoReg*)0x40098124U) /**< \brief (USART0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_USART0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_usart1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_usart1.h
new file mode 100644
index 0000000..daf475b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_usart1.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_USART1_INSTANCE_
+#define _SAM3XA_USART1_INSTANCE_
+
+/* ========== Register definition for USART1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART1_CR          (0x4009C000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR          (0x4009C004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER          (0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR          (0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR          (0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR          (0x4009C014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR          (0x4009C018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR          (0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR          (0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR          (0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR          (0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI          (0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER          (0x4009C044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF          (0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN          (0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_LINMR          (0x4009C054U) /**< \brief (USART1) LIN Mode Register */
+#define REG_USART1_LINIR          (0x4009C058U) /**< \brief (USART1) LIN Identifier Register */
+#define REG_USART1_WPMR          (0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR          (0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_RPR          (0x4009C100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR          (0x4009C104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR          (0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR          (0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR          (0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR          (0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR          (0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR          (0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR          (0x4009C120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR          (0x4009C124U) /**< \brief (USART1) Transfer Status Register */
+#else
+#define REG_USART1_CR (*(WoReg*)0x4009C000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR (*(RwReg*)0x4009C004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER (*(WoReg*)0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER (*(RoReg*)0x4009C044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_LINMR (*(RwReg*)0x4009C054U) /**< \brief (USART1) LIN Mode Register */
+#define REG_USART1_LINIR (*(RwReg*)0x4009C058U) /**< \brief (USART1) LIN Identifier Register */
+#define REG_USART1_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART1) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_USART1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_usart2.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_usart2.h
new file mode 100644
index 0000000..0891093
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_usart2.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_USART2_INSTANCE_
+#define _SAM3XA_USART2_INSTANCE_
+
+/* ========== Register definition for USART2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART2_CR          (0x400A0000U) /**< \brief (USART2) Control Register */
+#define REG_USART2_MR          (0x400A0004U) /**< \brief (USART2) Mode Register */
+#define REG_USART2_IER          (0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */
+#define REG_USART2_IDR          (0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */
+#define REG_USART2_IMR          (0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */
+#define REG_USART2_CSR          (0x400A0014U) /**< \brief (USART2) Channel Status Register */
+#define REG_USART2_RHR          (0x400A0018U) /**< \brief (USART2) Receiver Holding Register */
+#define REG_USART2_THR          (0x400A001CU) /**< \brief (USART2) Transmitter Holding Register */
+#define REG_USART2_BRGR          (0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */
+#define REG_USART2_RTOR          (0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */
+#define REG_USART2_TTGR          (0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */
+#define REG_USART2_FIDI          (0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */
+#define REG_USART2_NER          (0x400A0044U) /**< \brief (USART2) Number of Errors Register */
+#define REG_USART2_IF          (0x400A004CU) /**< \brief (USART2) IrDA Filter Register */
+#define REG_USART2_MAN          (0x400A0050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
+#define REG_USART2_LINMR          (0x400A0054U) /**< \brief (USART2) LIN Mode Register */
+#define REG_USART2_LINIR          (0x400A0058U) /**< \brief (USART2) LIN Identifier Register */
+#define REG_USART2_WPMR          (0x400A00E4U) /**< \brief (USART2) Write Protect Mode Register */
+#define REG_USART2_WPSR          (0x400A00E8U) /**< \brief (USART2) Write Protect Status Register */
+#define REG_USART2_RPR          (0x400A0100U) /**< \brief (USART2) Receive Pointer Register */
+#define REG_USART2_RCR          (0x400A0104U) /**< \brief (USART2) Receive Counter Register */
+#define REG_USART2_TPR          (0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */
+#define REG_USART2_TCR          (0x400A010CU) /**< \brief (USART2) Transmit Counter Register */
+#define REG_USART2_RNPR          (0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */
+#define REG_USART2_RNCR          (0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */
+#define REG_USART2_TNPR          (0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */
+#define REG_USART2_TNCR          (0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */
+#define REG_USART2_PTCR          (0x400A0120U) /**< \brief (USART2) Transfer Control Register */
+#define REG_USART2_PTSR          (0x400A0124U) /**< \brief (USART2) Transfer Status Register */
+#else
+#define REG_USART2_CR (*(WoReg*)0x400A0000U) /**< \brief (USART2) Control Register */
+#define REG_USART2_MR (*(RwReg*)0x400A0004U) /**< \brief (USART2) Mode Register */
+#define REG_USART2_IER (*(WoReg*)0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */
+#define REG_USART2_IDR (*(WoReg*)0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */
+#define REG_USART2_IMR (*(RoReg*)0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */
+#define REG_USART2_CSR (*(RoReg*)0x400A0014U) /**< \brief (USART2) Channel Status Register */
+#define REG_USART2_RHR (*(RoReg*)0x400A0018U) /**< \brief (USART2) Receiver Holding Register */
+#define REG_USART2_THR (*(WoReg*)0x400A001CU) /**< \brief (USART2) Transmitter Holding Register */
+#define REG_USART2_BRGR (*(RwReg*)0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */
+#define REG_USART2_RTOR (*(RwReg*)0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */
+#define REG_USART2_TTGR (*(RwReg*)0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */
+#define REG_USART2_FIDI (*(RwReg*)0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */
+#define REG_USART2_NER (*(RoReg*)0x400A0044U) /**< \brief (USART2) Number of Errors Register */
+#define REG_USART2_IF (*(RwReg*)0x400A004CU) /**< \brief (USART2) IrDA Filter Register */
+#define REG_USART2_MAN (*(RwReg*)0x400A0050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
+#define REG_USART2_LINMR (*(RwReg*)0x400A0054U) /**< \brief (USART2) LIN Mode Register */
+#define REG_USART2_LINIR (*(RwReg*)0x400A0058U) /**< \brief (USART2) LIN Identifier Register */
+#define REG_USART2_WPMR (*(RwReg*)0x400A00E4U) /**< \brief (USART2) Write Protect Mode Register */
+#define REG_USART2_WPSR (*(RoReg*)0x400A00E8U) /**< \brief (USART2) Write Protect Status Register */
+#define REG_USART2_RPR (*(RwReg*)0x400A0100U) /**< \brief (USART2) Receive Pointer Register */
+#define REG_USART2_RCR (*(RwReg*)0x400A0104U) /**< \brief (USART2) Receive Counter Register */
+#define REG_USART2_TPR (*(RwReg*)0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */
+#define REG_USART2_TCR (*(RwReg*)0x400A010CU) /**< \brief (USART2) Transmit Counter Register */
+#define REG_USART2_RNPR (*(RwReg*)0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */
+#define REG_USART2_RNCR (*(RwReg*)0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */
+#define REG_USART2_TNPR (*(RwReg*)0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */
+#define REG_USART2_TNCR (*(RwReg*)0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */
+#define REG_USART2_PTCR (*(WoReg*)0x400A0120U) /**< \brief (USART2) Transfer Control Register */
+#define REG_USART2_PTSR (*(RoReg*)0x400A0124U) /**< \brief (USART2) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_USART2_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_usart3.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_usart3.h
new file mode 100644
index 0000000..df12c98
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_usart3.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_USART3_INSTANCE_
+#define _SAM3XA_USART3_INSTANCE_
+
+/* ========== Register definition for USART3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART3_CR          (0x400A4000U) /**< \brief (USART3) Control Register */
+#define REG_USART3_MR          (0x400A4004U) /**< \brief (USART3) Mode Register */
+#define REG_USART3_IER          (0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */
+#define REG_USART3_IDR          (0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */
+#define REG_USART3_IMR          (0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */
+#define REG_USART3_CSR          (0x400A4014U) /**< \brief (USART3) Channel Status Register */
+#define REG_USART3_RHR          (0x400A4018U) /**< \brief (USART3) Receiver Holding Register */
+#define REG_USART3_THR          (0x400A401CU) /**< \brief (USART3) Transmitter Holding Register */
+#define REG_USART3_BRGR          (0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */
+#define REG_USART3_RTOR          (0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */
+#define REG_USART3_TTGR          (0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */
+#define REG_USART3_FIDI          (0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */
+#define REG_USART3_NER          (0x400A4044U) /**< \brief (USART3) Number of Errors Register */
+#define REG_USART3_IF          (0x400A404CU) /**< \brief (USART3) IrDA Filter Register */
+#define REG_USART3_MAN          (0x400A4050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
+#define REG_USART3_LINMR          (0x400A4054U) /**< \brief (USART3) LIN Mode Register */
+#define REG_USART3_LINIR          (0x400A4058U) /**< \brief (USART3) LIN Identifier Register */
+#define REG_USART3_WPMR          (0x400A40E4U) /**< \brief (USART3) Write Protect Mode Register */
+#define REG_USART3_WPSR          (0x400A40E8U) /**< \brief (USART3) Write Protect Status Register */
+#define REG_USART3_RPR          (0x400A4100U) /**< \brief (USART3) Receive Pointer Register */
+#define REG_USART3_RCR          (0x400A4104U) /**< \brief (USART3) Receive Counter Register */
+#define REG_USART3_TPR          (0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */
+#define REG_USART3_TCR          (0x400A410CU) /**< \brief (USART3) Transmit Counter Register */
+#define REG_USART3_RNPR          (0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */
+#define REG_USART3_RNCR          (0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */
+#define REG_USART3_TNPR          (0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */
+#define REG_USART3_TNCR          (0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */
+#define REG_USART3_PTCR          (0x400A4120U) /**< \brief (USART3) Transfer Control Register */
+#define REG_USART3_PTSR          (0x400A4124U) /**< \brief (USART3) Transfer Status Register */
+#else
+#define REG_USART3_CR (*(WoReg*)0x400A4000U) /**< \brief (USART3) Control Register */
+#define REG_USART3_MR (*(RwReg*)0x400A4004U) /**< \brief (USART3) Mode Register */
+#define REG_USART3_IER (*(WoReg*)0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */
+#define REG_USART3_IDR (*(WoReg*)0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */
+#define REG_USART3_IMR (*(RoReg*)0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */
+#define REG_USART3_CSR (*(RoReg*)0x400A4014U) /**< \brief (USART3) Channel Status Register */
+#define REG_USART3_RHR (*(RoReg*)0x400A4018U) /**< \brief (USART3) Receiver Holding Register */
+#define REG_USART3_THR (*(WoReg*)0x400A401CU) /**< \brief (USART3) Transmitter Holding Register */
+#define REG_USART3_BRGR (*(RwReg*)0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */
+#define REG_USART3_RTOR (*(RwReg*)0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */
+#define REG_USART3_TTGR (*(RwReg*)0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */
+#define REG_USART3_FIDI (*(RwReg*)0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */
+#define REG_USART3_NER (*(RoReg*)0x400A4044U) /**< \brief (USART3) Number of Errors Register */
+#define REG_USART3_IF (*(RwReg*)0x400A404CU) /**< \brief (USART3) IrDA Filter Register */
+#define REG_USART3_MAN (*(RwReg*)0x400A4050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
+#define REG_USART3_LINMR (*(RwReg*)0x400A4054U) /**< \brief (USART3) LIN Mode Register */
+#define REG_USART3_LINIR (*(RwReg*)0x400A4058U) /**< \brief (USART3) LIN Identifier Register */
+#define REG_USART3_WPMR (*(RwReg*)0x400A40E4U) /**< \brief (USART3) Write Protect Mode Register */
+#define REG_USART3_WPSR (*(RoReg*)0x400A40E8U) /**< \brief (USART3) Write Protect Status Register */
+#define REG_USART3_RPR (*(RwReg*)0x400A4100U) /**< \brief (USART3) Receive Pointer Register */
+#define REG_USART3_RCR (*(RwReg*)0x400A4104U) /**< \brief (USART3) Receive Counter Register */
+#define REG_USART3_TPR (*(RwReg*)0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */
+#define REG_USART3_TCR (*(RwReg*)0x400A410CU) /**< \brief (USART3) Transmit Counter Register */
+#define REG_USART3_RNPR (*(RwReg*)0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */
+#define REG_USART3_RNCR (*(RwReg*)0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */
+#define REG_USART3_TNPR (*(RwReg*)0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */
+#define REG_USART3_TNCR (*(RwReg*)0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */
+#define REG_USART3_PTCR (*(WoReg*)0x400A4120U) /**< \brief (USART3) Transfer Control Register */
+#define REG_USART3_PTSR (*(RoReg*)0x400A4124U) /**< \brief (USART3) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_USART3_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_wdt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_wdt.h
new file mode 100644
index 0000000..a122b9a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/instance/instance_wdt.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_WDT_INSTANCE_
+#define _SAM3XA_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CR          (0x400E1A50U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR          (0x400E1A54U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR          (0x400E1A58U) /**< \brief (WDT) Status Register */
+#else
+#define REG_WDT_CR (*(WoReg*)0x400E1A50U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR (*(RwReg*)0x400E1A54U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR (*(RoReg*)0x400E1A58U) /**< \brief (WDT) Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM3XA_WDT_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3a4c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3a4c.h
new file mode 100644
index 0000000..ea8d691
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3a4c.h
@@ -0,0 +1,338 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3A4C_PIO_
+#define _SAM3A4C_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+
+#endif /* _SAM3A4C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3a8c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3a8c.h
new file mode 100644
index 0000000..95f0adc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3a8c.h
@@ -0,0 +1,338 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3A8C_PIO_
+#define _SAM3A8C_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+
+#endif /* _SAM3A8C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x4c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x4c.h
new file mode 100644
index 0000000..485251d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x4c.h
@@ -0,0 +1,358 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X4C_PIO_
+#define _SAM3X4C_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EMAC peripheral ========== */
+#define PIO_PC13B_ECOL       (1u << 13) /**< \brief Emac signal: ECOL */
+#define PIO_PC10B_ECRS       (1u << 10) /**< \brief Emac signal: ECRS */
+#define PIO_PB4A_ECRSDV      (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB4A_ERXDV       (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB8A_EMDC        (1u << 8)  /**< \brief Emac signal: EMDC */
+#define PIO_PB9A_EMDIO       (1u << 9)  /**< \brief Emac signal: EMDIO */
+#define PIO_PB5A_ERX0        (1u << 5)  /**< \brief Emac signal: ERX0 */
+#define PIO_PB6A_ERX1        (1u << 6)  /**< \brief Emac signal: ERX1 */
+#define PIO_PC11B_ERX2       (1u << 11) /**< \brief Emac signal: ERX2 */
+#define PIO_PC12B_ERX3       (1u << 12) /**< \brief Emac signal: ERX3 */
+#define PIO_PC14B_ERXCK      (1u << 14) /**< \brief Emac signal: ERXCK */
+#define PIO_PB7A_ERXER       (1u << 7)  /**< \brief Emac signal: ERXER */
+#define PIO_PB2A_ETX0        (1u << 2)  /**< \brief Emac signal: ETX0 */
+#define PIO_PB3A_ETX1        (1u << 3)  /**< \brief Emac signal: ETX1 */
+#define PIO_PC15B_ETX2       (1u << 15) /**< \brief Emac signal: ETX2 */
+#define PIO_PC16B_ETX3       (1u << 16) /**< \brief Emac signal: ETX3 */
+#define PIO_PB0A_ETXCK       (1u << 0)  /**< \brief Emac signal: ETXCK */
+#define PIO_PB1A_ETXEN       (1u << 1)  /**< \brief Emac signal: ETXEN */
+#define PIO_PC17B_ETXER      (1u << 17) /**< \brief Emac signal: ETXER */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+
+#endif /* _SAM3X4C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x4e.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x4e.h
new file mode 100644
index 0000000..9238858
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x4e.h
@@ -0,0 +1,552 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X4E_PIO_
+#define _SAM3X4E_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+#define PIO_PC0              (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1              (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2              (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3              (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4              (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5              (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6              (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7              (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8              (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9              (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10             (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11             (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12             (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13             (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14             (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15             (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16             (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17             (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18             (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19             (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20             (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21             (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22             (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23             (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24             (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25             (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26             (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27             (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28             (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29             (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30             (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PD0              (1u << 0)  /**< \brief Pin Controlled by PD0 */
+#define PIO_PD1              (1u << 1)  /**< \brief Pin Controlled by PD1 */
+#define PIO_PD2              (1u << 2)  /**< \brief Pin Controlled by PD2 */
+#define PIO_PD3              (1u << 3)  /**< \brief Pin Controlled by PD3 */
+#define PIO_PD4              (1u << 4)  /**< \brief Pin Controlled by PD4 */
+#define PIO_PD5              (1u << 5)  /**< \brief Pin Controlled by PD5 */
+#define PIO_PD6              (1u << 6)  /**< \brief Pin Controlled by PD6 */
+#define PIO_PD7              (1u << 7)  /**< \brief Pin Controlled by PD7 */
+#define PIO_PD8              (1u << 8)  /**< \brief Pin Controlled by PD8 */
+#define PIO_PD9              (1u << 9)  /**< \brief Pin Controlled by PD9 */
+#define PIO_PD10             (1u << 10) /**< \brief Pin Controlled by PD10 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC21A_A0         (1u << 21) /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PC21A_NBS0       (1u << 21) /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PC22A_A1         (1u << 22) /**< \brief Ebi signal: A1 */
+#define PIO_PD0A_A10         (1u << 0)  /**< \brief Ebi signal: A10 */
+#define PIO_PD22A_A10        (1u << 22) /**< \brief Ebi signal: A10 */
+#define PIO_PD1A_A11         (1u << 1)  /**< \brief Ebi signal: A11 */
+#define PIO_PD23A_A11        (1u << 23) /**< \brief Ebi signal: A11 */
+#define PIO_PD2A_A12         (1u << 2)  /**< \brief Ebi signal: A12 */
+#define PIO_PD24A_A12        (1u << 24) /**< \brief Ebi signal: A12 */
+#define PIO_PD3A_A13         (1u << 3)  /**< \brief Ebi signal: A13 */
+#define PIO_PD25A_A13        (1u << 25) /**< \brief Ebi signal: A13 */
+#define PIO_PD4A_A14         (1u << 4)  /**< \brief Ebi signal: A14 */
+#define PIO_PD26A_A14        (1u << 26) /**< \brief Ebi signal: A14 */
+#define PIO_PD5A_A15         (1u << 5)  /**< \brief Ebi signal: A15 */
+#define PIO_PD27A_A15        (1u << 27) /**< \brief Ebi signal: A15 */
+#define PIO_PD6A_A16         (1u << 6)  /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD6A_BA0         (1u << 6)  /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD28A_A16        (1u << 28) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD28A_BA0        (1u << 28) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD7A_A17         (1u << 7)  /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD7A_BA1         (1u << 7)  /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD29A_A17        (1u << 29) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD29A_BA1        (1u << 29) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PA25B_A18        (1u << 25) /**< \brief Ebi signal: A18 */
+#define PIO_PB10B_A18        (1u << 10) /**< \brief Ebi signal: A18 */
+#define PIO_PD30A_A18        (1u << 30) /**< \brief Ebi signal: A18 */
+#define PIO_PA26B_A19        (1u << 26) /**< \brief Ebi signal: A19 */
+#define PIO_PB11B_A19        (1u << 11) /**< \brief Ebi signal: A19 */
+#define PIO_PE0A_A19         (1u << 0)  /**< \brief Ebi signal: A19 */
+#define PIO_PC23A_A2         (1u << 23) /**< \brief Ebi signal: A2 */
+#define PIO_PA18B_A20        (1u << 18) /**< \brief Ebi signal: A20 */
+#define PIO_PA27B_A20        (1u << 27) /**< \brief Ebi signal: A20 */
+#define PIO_PE1A_A20         (1u << 1)  /**< \brief Ebi signal: A20 */
+#define PIO_PD8A_A21         (1u << 8)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PD8A_NANDALE     (1u << 8)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PE2A_A21         (1u << 2)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PE2A_NANDALE     (1u << 2)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PD9A_A22         (1u << 9)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PD9A_NANDCLE     (1u << 9)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE3A_A22         (1u << 3)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE3A_NANDCLE     (1u << 3)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE4A_A23         (1u << 4)  /**< \brief Ebi signal: A23 */
+#define PIO_PC24A_A3         (1u << 24) /**< \brief Ebi signal: A3 */
+#define PIO_PC25A_A4         (1u << 25) /**< \brief Ebi signal: A4 */
+#define PIO_PC26A_A5         (1u << 26) /**< \brief Ebi signal: A5 */
+#define PIO_PD17A_A5         (1u << 17) /**< \brief Ebi signal: A5 */
+#define PIO_PC27A_A6         (1u << 27) /**< \brief Ebi signal: A6 */
+#define PIO_PD18A_A6         (1u << 18) /**< \brief Ebi signal: A6 */
+#define PIO_PC28A_A7         (1u << 28) /**< \brief Ebi signal: A7 */
+#define PIO_PD19A_A7         (1u << 19) /**< \brief Ebi signal: A7 */
+#define PIO_PC29A_A8         (1u << 29) /**< \brief Ebi signal: A8 */
+#define PIO_PD20A_A8         (1u << 20) /**< \brief Ebi signal: A8 */
+#define PIO_PC30A_A9         (1u << 30) /**< \brief Ebi signal: A9 */
+#define PIO_PD21A_A9         (1u << 21) /**< \brief Ebi signal: A9 */
+#define PIO_PD16A_CAS        (1u << 16) /**< \brief Ebi signal: CAS */
+#define PIO_PC2A_D0          (1u << 2)  /**< \brief Ebi signal: D0 */
+#define PIO_PC3A_D1          (1u << 3)  /**< \brief Ebi signal: D1 */
+#define PIO_PC12A_D10        (1u << 12) /**< \brief Ebi signal: D10 */
+#define PIO_PC13A_D11        (1u << 13) /**< \brief Ebi signal: D11 */
+#define PIO_PC14A_D12        (1u << 14) /**< \brief Ebi signal: D12 */
+#define PIO_PC15A_D13        (1u << 15) /**< \brief Ebi signal: D13 */
+#define PIO_PC16A_D14        (1u << 16) /**< \brief Ebi signal: D14 */
+#define PIO_PC17A_D15        (1u << 17) /**< \brief Ebi signal: D15 */
+#define PIO_PC4A_D2          (1u << 4)  /**< \brief Ebi signal: D2 */
+#define PIO_PC5A_D3          (1u << 5)  /**< \brief Ebi signal: D3 */
+#define PIO_PC6A_D4          (1u << 6)  /**< \brief Ebi signal: D4 */
+#define PIO_PC7A_D5          (1u << 7)  /**< \brief Ebi signal: D5 */
+#define PIO_PC8A_D6          (1u << 8)  /**< \brief Ebi signal: D6 */
+#define PIO_PC9A_D7          (1u << 9)  /**< \brief Ebi signal: D7 */
+#define PIO_PC10A_D8         (1u << 10) /**< \brief Ebi signal: D8 */
+#define PIO_PC11A_D9         (1u << 11) /**< \brief Ebi signal: D9 */
+#define PIO_PC19A_NANDOE     (1u << 19) /**< \brief Ebi signal: NANDOE */
+#define PIO_PA2B_NANDRDY     (1u << 2)  /**< \brief Ebi signal: NANDRDY */
+#define PIO_PC20A_NANDWE     (1u << 20) /**< \brief Ebi signal: NANDWE */
+#define PIO_PA6B_NCS0        (1u << 6)  /**< \brief Ebi signal: NCS0 */
+#define PIO_PA7B_NCS1        (1u << 7)  /**< \brief Ebi signal: NCS1 */
+#define PIO_PB24B_NCS2       (1u << 24) /**< \brief Ebi signal: NCS2 */
+#define PIO_PB27A_NCS3       (1u << 27) /**< \brief Ebi signal: NCS3 */
+#define PIO_PE5A_NCS4        (1u << 5)  /**< \brief Ebi signal: NCS4 */
+#define PIO_PE6A_NCS5        (1u << 6)  /**< \brief Ebi signal: NCS5 */
+#define PIO_PE18B_NCS6       (1u << 18) /**< \brief Ebi signal: NCS6 */
+#define PIO_PE27A_NCS7       (1u << 27) /**< \brief Ebi signal: NCS7 */
+#define PIO_PA29B_NRD        (1u << 29) /**< \brief Ebi signal: NRD */
+#define PIO_PA4B_NWAIT       (1u << 4)  /**< \brief Ebi signal: NWAIT */
+#define PIO_PC18A_NWR0       (1u << 18) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC18A_NWE        (1u << 18) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PD10A_NWR1       (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PD10A_NBS1       (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PD15A_RAS        (1u << 15) /**< \brief Ebi signal: RAS */
+#define PIO_PD11A_SDA10      (1u << 11) /**< \brief Ebi signal: SDA10 */
+#define PIO_PD13A_SDCKE      (1u << 13) /**< \brief Ebi signal: SDCKE */
+#define PIO_PD12A_SDCS       (1u << 12) /**< \brief Ebi signal: SDCS */
+#define PIO_PD14A_SDWE       (1u << 14) /**< \brief Ebi signal: SDWE */
+/* ========== Pio definition for EMAC peripheral ========== */
+#define PIO_PC13B_ECOL       (1u << 13) /**< \brief Emac signal: ECOL */
+#define PIO_PC10B_ECRS       (1u << 10) /**< \brief Emac signal: ECRS */
+#define PIO_PB4A_ECRSDV      (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB4A_ERXDV       (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB8A_EMDC        (1u << 8)  /**< \brief Emac signal: EMDC */
+#define PIO_PB9A_EMDIO       (1u << 9)  /**< \brief Emac signal: EMDIO */
+#define PIO_PB5A_ERX0        (1u << 5)  /**< \brief Emac signal: ERX0 */
+#define PIO_PB6A_ERX1        (1u << 6)  /**< \brief Emac signal: ERX1 */
+#define PIO_PC11B_ERX2       (1u << 11) /**< \brief Emac signal: ERX2 */
+#define PIO_PC12B_ERX3       (1u << 12) /**< \brief Emac signal: ERX3 */
+#define PIO_PC14B_ERXCK      (1u << 14) /**< \brief Emac signal: ERXCK */
+#define PIO_PB7A_ERXER       (1u << 7)  /**< \brief Emac signal: ERXER */
+#define PIO_PB2A_ETX0        (1u << 2)  /**< \brief Emac signal: ETX0 */
+#define PIO_PB3A_ETX1        (1u << 3)  /**< \brief Emac signal: ETX1 */
+#define PIO_PC15B_ETX2       (1u << 15) /**< \brief Emac signal: ETX2 */
+#define PIO_PC16B_ETX3       (1u << 16) /**< \brief Emac signal: ETX3 */
+#define PIO_PB0A_ETXCK       (1u << 0)  /**< \brief Emac signal: ETXCK */
+#define PIO_PB1A_ETXEN       (1u << 1)  /**< \brief Emac signal: ETXEN */
+#define PIO_PC17B_ETXER      (1u << 17) /**< \brief Emac signal: ETXER */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TC2 peripheral ========== */
+#define PIO_PC27B_TCLK6      (1u << 27) /**< \brief Tc2 signal: TCLK6 */
+#define PIO_PC30B_TCLK7      (1u << 30) /**< \brief Tc2 signal: TCLK7 */
+#define PIO_PD9B_TCLK8       (1u << 9)  /**< \brief Tc2 signal: TCLK8 */
+#define PIO_PC25B_TIOA6      (1u << 25) /**< \brief Tc2 signal: TIOA6 */
+#define PIO_PC28B_TIOA7      (1u << 28) /**< \brief Tc2 signal: TIOA7 */
+#define PIO_PD7B_TIOA8       (1u << 7)  /**< \brief Tc2 signal: TIOA8 */
+#define PIO_PC26B_TIOB6      (1u << 26) /**< \brief Tc2 signal: TIOB6 */
+#define PIO_PC29B_TIOB7      (1u << 29) /**< \brief Tc2 signal: TIOB7 */
+#define PIO_PD8B_TIOB8       (1u << 8)  /**< \brief Tc2 signal: TIOB8 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio definition for USART3 peripheral ========== */
+#define PIO_PF4A_CTS3        (1u << 4)  /**< \brief Usart3 signal: CTS3 */
+#define PIO_PF5A_RTS3        (1u << 5)  /**< \brief Usart3 signal: RTS3 */
+#define PIO_PD5B_RXD3        (1u << 5)  /**< \brief Usart3 signal: RXD3 */
+#define PIO_PE16B_SCK3       (1u << 16) /**< \brief Usart3 signal: SCK3 */
+#define PIO_PD4B_TXD3        (1u << 4)  /**< \brief Usart3 signal: TXD3 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+#define PIO_PC0_IDX          64
+#define PIO_PC1_IDX          65
+#define PIO_PC2_IDX          66
+#define PIO_PC3_IDX          67
+#define PIO_PC4_IDX          68
+#define PIO_PC5_IDX          69
+#define PIO_PC6_IDX          70
+#define PIO_PC7_IDX          71
+#define PIO_PC8_IDX          72
+#define PIO_PC9_IDX          73
+#define PIO_PC10_IDX         74
+#define PIO_PC11_IDX         75
+#define PIO_PC12_IDX         76
+#define PIO_PC13_IDX         77
+#define PIO_PC14_IDX         78
+#define PIO_PC15_IDX         79
+#define PIO_PC16_IDX         80
+#define PIO_PC17_IDX         81
+#define PIO_PC18_IDX         82
+#define PIO_PC19_IDX         83
+#define PIO_PC20_IDX         84
+#define PIO_PC21_IDX         85
+#define PIO_PC22_IDX         86
+#define PIO_PC23_IDX         87
+#define PIO_PC24_IDX         88
+#define PIO_PC25_IDX         89
+#define PIO_PC26_IDX         90
+#define PIO_PC27_IDX         91
+#define PIO_PC28_IDX         92
+#define PIO_PC29_IDX         93
+#define PIO_PC30_IDX         94
+#define PIO_PD0_IDX          96
+#define PIO_PD1_IDX          97
+#define PIO_PD2_IDX          98
+#define PIO_PD3_IDX          99
+#define PIO_PD4_IDX          100
+#define PIO_PD5_IDX          101
+#define PIO_PD6_IDX          102
+#define PIO_PD7_IDX          103
+#define PIO_PD8_IDX          104
+#define PIO_PD9_IDX          105
+#define PIO_PD10_IDX         106
+
+#endif /* _SAM3X4E_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x8c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x8c.h
new file mode 100644
index 0000000..a8abe7f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x8c.h
@@ -0,0 +1,358 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X8C_PIO_
+#define _SAM3X8C_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EMAC peripheral ========== */
+#define PIO_PC13B_ECOL       (1u << 13) /**< \brief Emac signal: ECOL */
+#define PIO_PC10B_ECRS       (1u << 10) /**< \brief Emac signal: ECRS */
+#define PIO_PB4A_ECRSDV      (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB4A_ERXDV       (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB8A_EMDC        (1u << 8)  /**< \brief Emac signal: EMDC */
+#define PIO_PB9A_EMDIO       (1u << 9)  /**< \brief Emac signal: EMDIO */
+#define PIO_PB5A_ERX0        (1u << 5)  /**< \brief Emac signal: ERX0 */
+#define PIO_PB6A_ERX1        (1u << 6)  /**< \brief Emac signal: ERX1 */
+#define PIO_PC11B_ERX2       (1u << 11) /**< \brief Emac signal: ERX2 */
+#define PIO_PC12B_ERX3       (1u << 12) /**< \brief Emac signal: ERX3 */
+#define PIO_PC14B_ERXCK      (1u << 14) /**< \brief Emac signal: ERXCK */
+#define PIO_PB7A_ERXER       (1u << 7)  /**< \brief Emac signal: ERXER */
+#define PIO_PB2A_ETX0        (1u << 2)  /**< \brief Emac signal: ETX0 */
+#define PIO_PB3A_ETX1        (1u << 3)  /**< \brief Emac signal: ETX1 */
+#define PIO_PC15B_ETX2       (1u << 15) /**< \brief Emac signal: ETX2 */
+#define PIO_PC16B_ETX3       (1u << 16) /**< \brief Emac signal: ETX3 */
+#define PIO_PB0A_ETXCK       (1u << 0)  /**< \brief Emac signal: ETXCK */
+#define PIO_PB1A_ETXEN       (1u << 1)  /**< \brief Emac signal: ETXEN */
+#define PIO_PC17B_ETXER      (1u << 17) /**< \brief Emac signal: ETXER */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+
+#endif /* _SAM3X8C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x8e.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x8e.h
new file mode 100644
index 0000000..29c0954
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x8e.h
@@ -0,0 +1,552 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X8E_PIO_
+#define _SAM3X8E_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+#define PIO_PC0              (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1              (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2              (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3              (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4              (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5              (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6              (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7              (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8              (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9              (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10             (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11             (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12             (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13             (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14             (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15             (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16             (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17             (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18             (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19             (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20             (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21             (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22             (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23             (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24             (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25             (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26             (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27             (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28             (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29             (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30             (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PD0              (1u << 0)  /**< \brief Pin Controlled by PD0 */
+#define PIO_PD1              (1u << 1)  /**< \brief Pin Controlled by PD1 */
+#define PIO_PD2              (1u << 2)  /**< \brief Pin Controlled by PD2 */
+#define PIO_PD3              (1u << 3)  /**< \brief Pin Controlled by PD3 */
+#define PIO_PD4              (1u << 4)  /**< \brief Pin Controlled by PD4 */
+#define PIO_PD5              (1u << 5)  /**< \brief Pin Controlled by PD5 */
+#define PIO_PD6              (1u << 6)  /**< \brief Pin Controlled by PD6 */
+#define PIO_PD7              (1u << 7)  /**< \brief Pin Controlled by PD7 */
+#define PIO_PD8              (1u << 8)  /**< \brief Pin Controlled by PD8 */
+#define PIO_PD9              (1u << 9)  /**< \brief Pin Controlled by PD9 */
+#define PIO_PD10             (1u << 10) /**< \brief Pin Controlled by PD10 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC21A_A0         (1u << 21) /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PC21A_NBS0       (1u << 21) /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PC22A_A1         (1u << 22) /**< \brief Ebi signal: A1 */
+#define PIO_PD0A_A10         (1u << 0)  /**< \brief Ebi signal: A10 */
+#define PIO_PD22A_A10        (1u << 22) /**< \brief Ebi signal: A10 */
+#define PIO_PD1A_A11         (1u << 1)  /**< \brief Ebi signal: A11 */
+#define PIO_PD23A_A11        (1u << 23) /**< \brief Ebi signal: A11 */
+#define PIO_PD2A_A12         (1u << 2)  /**< \brief Ebi signal: A12 */
+#define PIO_PD24A_A12        (1u << 24) /**< \brief Ebi signal: A12 */
+#define PIO_PD3A_A13         (1u << 3)  /**< \brief Ebi signal: A13 */
+#define PIO_PD25A_A13        (1u << 25) /**< \brief Ebi signal: A13 */
+#define PIO_PD4A_A14         (1u << 4)  /**< \brief Ebi signal: A14 */
+#define PIO_PD26A_A14        (1u << 26) /**< \brief Ebi signal: A14 */
+#define PIO_PD5A_A15         (1u << 5)  /**< \brief Ebi signal: A15 */
+#define PIO_PD27A_A15        (1u << 27) /**< \brief Ebi signal: A15 */
+#define PIO_PD6A_A16         (1u << 6)  /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD6A_BA0         (1u << 6)  /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD28A_A16        (1u << 28) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD28A_BA0        (1u << 28) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD7A_A17         (1u << 7)  /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD7A_BA1         (1u << 7)  /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD29A_A17        (1u << 29) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD29A_BA1        (1u << 29) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PA25B_A18        (1u << 25) /**< \brief Ebi signal: A18 */
+#define PIO_PB10B_A18        (1u << 10) /**< \brief Ebi signal: A18 */
+#define PIO_PD30A_A18        (1u << 30) /**< \brief Ebi signal: A18 */
+#define PIO_PA26B_A19        (1u << 26) /**< \brief Ebi signal: A19 */
+#define PIO_PB11B_A19        (1u << 11) /**< \brief Ebi signal: A19 */
+#define PIO_PE0A_A19         (1u << 0)  /**< \brief Ebi signal: A19 */
+#define PIO_PC23A_A2         (1u << 23) /**< \brief Ebi signal: A2 */
+#define PIO_PA18B_A20        (1u << 18) /**< \brief Ebi signal: A20 */
+#define PIO_PA27B_A20        (1u << 27) /**< \brief Ebi signal: A20 */
+#define PIO_PE1A_A20         (1u << 1)  /**< \brief Ebi signal: A20 */
+#define PIO_PD8A_A21         (1u << 8)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PD8A_NANDALE     (1u << 8)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PE2A_A21         (1u << 2)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PE2A_NANDALE     (1u << 2)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PD9A_A22         (1u << 9)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PD9A_NANDCLE     (1u << 9)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE3A_A22         (1u << 3)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE3A_NANDCLE     (1u << 3)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE4A_A23         (1u << 4)  /**< \brief Ebi signal: A23 */
+#define PIO_PC24A_A3         (1u << 24) /**< \brief Ebi signal: A3 */
+#define PIO_PC25A_A4         (1u << 25) /**< \brief Ebi signal: A4 */
+#define PIO_PC26A_A5         (1u << 26) /**< \brief Ebi signal: A5 */
+#define PIO_PD17A_A5         (1u << 17) /**< \brief Ebi signal: A5 */
+#define PIO_PC27A_A6         (1u << 27) /**< \brief Ebi signal: A6 */
+#define PIO_PD18A_A6         (1u << 18) /**< \brief Ebi signal: A6 */
+#define PIO_PC28A_A7         (1u << 28) /**< \brief Ebi signal: A7 */
+#define PIO_PD19A_A7         (1u << 19) /**< \brief Ebi signal: A7 */
+#define PIO_PC29A_A8         (1u << 29) /**< \brief Ebi signal: A8 */
+#define PIO_PD20A_A8         (1u << 20) /**< \brief Ebi signal: A8 */
+#define PIO_PC30A_A9         (1u << 30) /**< \brief Ebi signal: A9 */
+#define PIO_PD21A_A9         (1u << 21) /**< \brief Ebi signal: A9 */
+#define PIO_PD16A_CAS        (1u << 16) /**< \brief Ebi signal: CAS */
+#define PIO_PC2A_D0          (1u << 2)  /**< \brief Ebi signal: D0 */
+#define PIO_PC3A_D1          (1u << 3)  /**< \brief Ebi signal: D1 */
+#define PIO_PC12A_D10        (1u << 12) /**< \brief Ebi signal: D10 */
+#define PIO_PC13A_D11        (1u << 13) /**< \brief Ebi signal: D11 */
+#define PIO_PC14A_D12        (1u << 14) /**< \brief Ebi signal: D12 */
+#define PIO_PC15A_D13        (1u << 15) /**< \brief Ebi signal: D13 */
+#define PIO_PC16A_D14        (1u << 16) /**< \brief Ebi signal: D14 */
+#define PIO_PC17A_D15        (1u << 17) /**< \brief Ebi signal: D15 */
+#define PIO_PC4A_D2          (1u << 4)  /**< \brief Ebi signal: D2 */
+#define PIO_PC5A_D3          (1u << 5)  /**< \brief Ebi signal: D3 */
+#define PIO_PC6A_D4          (1u << 6)  /**< \brief Ebi signal: D4 */
+#define PIO_PC7A_D5          (1u << 7)  /**< \brief Ebi signal: D5 */
+#define PIO_PC8A_D6          (1u << 8)  /**< \brief Ebi signal: D6 */
+#define PIO_PC9A_D7          (1u << 9)  /**< \brief Ebi signal: D7 */
+#define PIO_PC10A_D8         (1u << 10) /**< \brief Ebi signal: D8 */
+#define PIO_PC11A_D9         (1u << 11) /**< \brief Ebi signal: D9 */
+#define PIO_PC19A_NANDOE     (1u << 19) /**< \brief Ebi signal: NANDOE */
+#define PIO_PA2B_NANDRDY     (1u << 2)  /**< \brief Ebi signal: NANDRDY */
+#define PIO_PC20A_NANDWE     (1u << 20) /**< \brief Ebi signal: NANDWE */
+#define PIO_PA6B_NCS0        (1u << 6)  /**< \brief Ebi signal: NCS0 */
+#define PIO_PA7B_NCS1        (1u << 7)  /**< \brief Ebi signal: NCS1 */
+#define PIO_PB24B_NCS2       (1u << 24) /**< \brief Ebi signal: NCS2 */
+#define PIO_PB27A_NCS3       (1u << 27) /**< \brief Ebi signal: NCS3 */
+#define PIO_PE5A_NCS4        (1u << 5)  /**< \brief Ebi signal: NCS4 */
+#define PIO_PE6A_NCS5        (1u << 6)  /**< \brief Ebi signal: NCS5 */
+#define PIO_PE18B_NCS6       (1u << 18) /**< \brief Ebi signal: NCS6 */
+#define PIO_PE27A_NCS7       (1u << 27) /**< \brief Ebi signal: NCS7 */
+#define PIO_PA29B_NRD        (1u << 29) /**< \brief Ebi signal: NRD */
+#define PIO_PA4B_NWAIT       (1u << 4)  /**< \brief Ebi signal: NWAIT */
+#define PIO_PC18A_NWR0       (1u << 18) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC18A_NWE        (1u << 18) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PD10A_NWR1       (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PD10A_NBS1       (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PD15A_RAS        (1u << 15) /**< \brief Ebi signal: RAS */
+#define PIO_PD11A_SDA10      (1u << 11) /**< \brief Ebi signal: SDA10 */
+#define PIO_PD13A_SDCKE      (1u << 13) /**< \brief Ebi signal: SDCKE */
+#define PIO_PD12A_SDCS       (1u << 12) /**< \brief Ebi signal: SDCS */
+#define PIO_PD14A_SDWE       (1u << 14) /**< \brief Ebi signal: SDWE */
+/* ========== Pio definition for EMAC peripheral ========== */
+#define PIO_PC13B_ECOL       (1u << 13) /**< \brief Emac signal: ECOL */
+#define PIO_PC10B_ECRS       (1u << 10) /**< \brief Emac signal: ECRS */
+#define PIO_PB4A_ECRSDV      (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB4A_ERXDV       (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB8A_EMDC        (1u << 8)  /**< \brief Emac signal: EMDC */
+#define PIO_PB9A_EMDIO       (1u << 9)  /**< \brief Emac signal: EMDIO */
+#define PIO_PB5A_ERX0        (1u << 5)  /**< \brief Emac signal: ERX0 */
+#define PIO_PB6A_ERX1        (1u << 6)  /**< \brief Emac signal: ERX1 */
+#define PIO_PC11B_ERX2       (1u << 11) /**< \brief Emac signal: ERX2 */
+#define PIO_PC12B_ERX3       (1u << 12) /**< \brief Emac signal: ERX3 */
+#define PIO_PC14B_ERXCK      (1u << 14) /**< \brief Emac signal: ERXCK */
+#define PIO_PB7A_ERXER       (1u << 7)  /**< \brief Emac signal: ERXER */
+#define PIO_PB2A_ETX0        (1u << 2)  /**< \brief Emac signal: ETX0 */
+#define PIO_PB3A_ETX1        (1u << 3)  /**< \brief Emac signal: ETX1 */
+#define PIO_PC15B_ETX2       (1u << 15) /**< \brief Emac signal: ETX2 */
+#define PIO_PC16B_ETX3       (1u << 16) /**< \brief Emac signal: ETX3 */
+#define PIO_PB0A_ETXCK       (1u << 0)  /**< \brief Emac signal: ETXCK */
+#define PIO_PB1A_ETXEN       (1u << 1)  /**< \brief Emac signal: ETXEN */
+#define PIO_PC17B_ETXER      (1u << 17) /**< \brief Emac signal: ETXER */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TC2 peripheral ========== */
+#define PIO_PC27B_TCLK6      (1u << 27) /**< \brief Tc2 signal: TCLK6 */
+#define PIO_PC30B_TCLK7      (1u << 30) /**< \brief Tc2 signal: TCLK7 */
+#define PIO_PD9B_TCLK8       (1u << 9)  /**< \brief Tc2 signal: TCLK8 */
+#define PIO_PC25B_TIOA6      (1u << 25) /**< \brief Tc2 signal: TIOA6 */
+#define PIO_PC28B_TIOA7      (1u << 28) /**< \brief Tc2 signal: TIOA7 */
+#define PIO_PD7B_TIOA8       (1u << 7)  /**< \brief Tc2 signal: TIOA8 */
+#define PIO_PC26B_TIOB6      (1u << 26) /**< \brief Tc2 signal: TIOB6 */
+#define PIO_PC29B_TIOB7      (1u << 29) /**< \brief Tc2 signal: TIOB7 */
+#define PIO_PD8B_TIOB8       (1u << 8)  /**< \brief Tc2 signal: TIOB8 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio definition for USART3 peripheral ========== */
+#define PIO_PF4A_CTS3        (1u << 4)  /**< \brief Usart3 signal: CTS3 */
+#define PIO_PF5A_RTS3        (1u << 5)  /**< \brief Usart3 signal: RTS3 */
+#define PIO_PD5B_RXD3        (1u << 5)  /**< \brief Usart3 signal: RXD3 */
+#define PIO_PE16B_SCK3       (1u << 16) /**< \brief Usart3 signal: SCK3 */
+#define PIO_PD4B_TXD3        (1u << 4)  /**< \brief Usart3 signal: TXD3 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+#define PIO_PC0_IDX          64
+#define PIO_PC1_IDX          65
+#define PIO_PC2_IDX          66
+#define PIO_PC3_IDX          67
+#define PIO_PC4_IDX          68
+#define PIO_PC5_IDX          69
+#define PIO_PC6_IDX          70
+#define PIO_PC7_IDX          71
+#define PIO_PC8_IDX          72
+#define PIO_PC9_IDX          73
+#define PIO_PC10_IDX         74
+#define PIO_PC11_IDX         75
+#define PIO_PC12_IDX         76
+#define PIO_PC13_IDX         77
+#define PIO_PC14_IDX         78
+#define PIO_PC15_IDX         79
+#define PIO_PC16_IDX         80
+#define PIO_PC17_IDX         81
+#define PIO_PC18_IDX         82
+#define PIO_PC19_IDX         83
+#define PIO_PC20_IDX         84
+#define PIO_PC21_IDX         85
+#define PIO_PC22_IDX         86
+#define PIO_PC23_IDX         87
+#define PIO_PC24_IDX         88
+#define PIO_PC25_IDX         89
+#define PIO_PC26_IDX         90
+#define PIO_PC27_IDX         91
+#define PIO_PC28_IDX         92
+#define PIO_PC29_IDX         93
+#define PIO_PC30_IDX         94
+#define PIO_PD0_IDX          96
+#define PIO_PD1_IDX          97
+#define PIO_PD2_IDX          98
+#define PIO_PD3_IDX          99
+#define PIO_PD4_IDX          100
+#define PIO_PD5_IDX          101
+#define PIO_PD6_IDX          102
+#define PIO_PD7_IDX          103
+#define PIO_PD8_IDX          104
+#define PIO_PD9_IDX          105
+#define PIO_PD10_IDX         106
+
+#endif /* _SAM3X8E_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x8h.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x8h.h
new file mode 100644
index 0000000..8ab1ed2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/pio/pio_sam3x8h.h
@@ -0,0 +1,680 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X8H_PIO_
+#define _SAM3X8H_PIO_
+
+#define PIO_PA0              (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1              (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2              (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3              (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4              (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5              (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6              (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7              (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8              (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9              (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10             (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11             (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12             (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13             (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14             (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15             (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16             (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17             (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18             (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19             (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20             (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21             (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22             (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23             (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24             (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25             (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26             (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27             (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28             (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29             (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30             (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31             (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0              (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1              (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2              (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3              (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4              (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5              (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6              (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7              (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8              (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9              (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10             (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11             (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12             (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13             (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14             (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PB15             (1u << 15) /**< \brief Pin Controlled by PB15 */
+#define PIO_PB16             (1u << 16) /**< \brief Pin Controlled by PB16 */
+#define PIO_PB17             (1u << 17) /**< \brief Pin Controlled by PB17 */
+#define PIO_PB18             (1u << 18) /**< \brief Pin Controlled by PB18 */
+#define PIO_PB19             (1u << 19) /**< \brief Pin Controlled by PB19 */
+#define PIO_PB20             (1u << 20) /**< \brief Pin Controlled by PB20 */
+#define PIO_PB21             (1u << 21) /**< \brief Pin Controlled by PB21 */
+#define PIO_PB22             (1u << 22) /**< \brief Pin Controlled by PB22 */
+#define PIO_PB23             (1u << 23) /**< \brief Pin Controlled by PB23 */
+#define PIO_PB24             (1u << 24) /**< \brief Pin Controlled by PB24 */
+#define PIO_PB25             (1u << 25) /**< \brief Pin Controlled by PB25 */
+#define PIO_PB26             (1u << 26) /**< \brief Pin Controlled by PB26 */
+#define PIO_PB27             (1u << 27) /**< \brief Pin Controlled by PB27 */
+#define PIO_PB28             (1u << 28) /**< \brief Pin Controlled by PB28 */
+#define PIO_PB29             (1u << 29) /**< \brief Pin Controlled by PB29 */
+#define PIO_PB30             (1u << 30) /**< \brief Pin Controlled by PB30 */
+#define PIO_PB31             (1u << 31) /**< \brief Pin Controlled by PB31 */
+#define PIO_PC0              (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1              (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2              (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3              (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4              (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5              (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6              (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7              (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8              (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9              (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10             (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11             (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12             (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13             (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14             (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15             (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16             (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17             (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18             (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19             (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20             (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21             (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22             (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23             (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24             (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25             (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26             (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27             (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28             (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29             (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30             (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PD0              (1u << 0)  /**< \brief Pin Controlled by PD0 */
+#define PIO_PD1              (1u << 1)  /**< \brief Pin Controlled by PD1 */
+#define PIO_PD2              (1u << 2)  /**< \brief Pin Controlled by PD2 */
+#define PIO_PD3              (1u << 3)  /**< \brief Pin Controlled by PD3 */
+#define PIO_PD4              (1u << 4)  /**< \brief Pin Controlled by PD4 */
+#define PIO_PD5              (1u << 5)  /**< \brief Pin Controlled by PD5 */
+#define PIO_PD6              (1u << 6)  /**< \brief Pin Controlled by PD6 */
+#define PIO_PD7              (1u << 7)  /**< \brief Pin Controlled by PD7 */
+#define PIO_PD8              (1u << 8)  /**< \brief Pin Controlled by PD8 */
+#define PIO_PD9              (1u << 9)  /**< \brief Pin Controlled by PD9 */
+#define PIO_PD10             (1u << 10) /**< \brief Pin Controlled by PD10 */
+#define PIO_PD11             (1u << 11) /**< \brief Pin Controlled by PD11 */
+#define PIO_PD12             (1u << 12) /**< \brief Pin Controlled by PD12 */
+#define PIO_PD13             (1u << 13) /**< \brief Pin Controlled by PD13 */
+#define PIO_PD14             (1u << 14) /**< \brief Pin Controlled by PD14 */
+#define PIO_PD15             (1u << 15) /**< \brief Pin Controlled by PD15 */
+#define PIO_PD16             (1u << 16) /**< \brief Pin Controlled by PD16 */
+#define PIO_PD17             (1u << 17) /**< \brief Pin Controlled by PD17 */
+#define PIO_PD18             (1u << 18) /**< \brief Pin Controlled by PD18 */
+#define PIO_PD19             (1u << 19) /**< \brief Pin Controlled by PD19 */
+#define PIO_PD20             (1u << 20) /**< \brief Pin Controlled by PD20 */
+#define PIO_PD21             (1u << 21) /**< \brief Pin Controlled by PD21 */
+#define PIO_PD22             (1u << 22) /**< \brief Pin Controlled by PD22 */
+#define PIO_PD23             (1u << 23) /**< \brief Pin Controlled by PD23 */
+#define PIO_PD24             (1u << 24) /**< \brief Pin Controlled by PD24 */
+#define PIO_PD25             (1u << 25) /**< \brief Pin Controlled by PD25 */
+#define PIO_PD26             (1u << 26) /**< \brief Pin Controlled by PD26 */
+#define PIO_PD27             (1u << 27) /**< \brief Pin Controlled by PD27 */
+#define PIO_PD28             (1u << 28) /**< \brief Pin Controlled by PD28 */
+#define PIO_PD29             (1u << 29) /**< \brief Pin Controlled by PD29 */
+#define PIO_PD30             (1u << 30) /**< \brief Pin Controlled by PD30 */
+#define PIO_PE0              (1u << 0)  /**< \brief Pin Controlled by PE0 */
+#define PIO_PE1              (1u << 1)  /**< \brief Pin Controlled by PE1 */
+#define PIO_PE2              (1u << 2)  /**< \brief Pin Controlled by PE2 */
+#define PIO_PE3              (1u << 3)  /**< \brief Pin Controlled by PE3 */
+#define PIO_PE4              (1u << 4)  /**< \brief Pin Controlled by PE4 */
+#define PIO_PE5              (1u << 5)  /**< \brief Pin Controlled by PE5 */
+#define PIO_PE6              (1u << 6)  /**< \brief Pin Controlled by PE6 */
+#define PIO_PE7              (1u << 7)  /**< \brief Pin Controlled by PE7 */
+#define PIO_PE8              (1u << 8)  /**< \brief Pin Controlled by PE8 */
+#define PIO_PE9              (1u << 9)  /**< \brief Pin Controlled by PE9 */
+#define PIO_PE10             (1u << 10) /**< \brief Pin Controlled by PE10 */
+#define PIO_PE11             (1u << 11) /**< \brief Pin Controlled by PE11 */
+#define PIO_PE12             (1u << 12) /**< \brief Pin Controlled by PE12 */
+#define PIO_PE13             (1u << 13) /**< \brief Pin Controlled by PE13 */
+#define PIO_PE14             (1u << 14) /**< \brief Pin Controlled by PE14 */
+#define PIO_PE15             (1u << 15) /**< \brief Pin Controlled by PE15 */
+#define PIO_PE16             (1u << 16) /**< \brief Pin Controlled by PE16 */
+#define PIO_PE17             (1u << 17) /**< \brief Pin Controlled by PE17 */
+#define PIO_PE18             (1u << 18) /**< \brief Pin Controlled by PE18 */
+#define PIO_PE19             (1u << 19) /**< \brief Pin Controlled by PE19 */
+#define PIO_PE20             (1u << 20) /**< \brief Pin Controlled by PE20 */
+#define PIO_PE21             (1u << 21) /**< \brief Pin Controlled by PE21 */
+#define PIO_PE22             (1u << 22) /**< \brief Pin Controlled by PE22 */
+#define PIO_PE23             (1u << 23) /**< \brief Pin Controlled by PE23 */
+#define PIO_PE24             (1u << 24) /**< \brief Pin Controlled by PE24 */
+#define PIO_PE25             (1u << 25) /**< \brief Pin Controlled by PE25 */
+#define PIO_PE26             (1u << 26) /**< \brief Pin Controlled by PE26 */
+#define PIO_PE27             (1u << 27) /**< \brief Pin Controlled by PE27 */
+#define PIO_PE28             (1u << 28) /**< \brief Pin Controlled by PE28 */
+#define PIO_PE29             (1u << 29) /**< \brief Pin Controlled by PE29 */
+#define PIO_PE30             (1u << 30) /**< \brief Pin Controlled by PE30 */
+#define PIO_PE31             (1u << 31) /**< \brief Pin Controlled by PE31 */
+#define PIO_PF0              (1u << 0)  /**< \brief Pin Controlled by PF0 */
+#define PIO_PF1              (1u << 1)  /**< \brief Pin Controlled by PF1 */
+#define PIO_PF2              (1u << 2)  /**< \brief Pin Controlled by PF2 */
+#define PIO_PF3              (1u << 3)  /**< \brief Pin Controlled by PF3 */
+#define PIO_PF4              (1u << 4)  /**< \brief Pin Controlled by PF4 */
+#define PIO_PF5              (1u << 5)  /**< \brief Pin Controlled by PF5 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA2X1_AD0        (1u << 2)  /**< \brief Adc signal: AD0 */
+#define PIO_PA3X1_AD1        (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PA3X1_WKUP1      (1u << 3)  /**< \brief Adc signal: AD1/WKUP1 */
+#define PIO_PB17X1_AD10      (1u << 17) /**< \brief Adc signal: AD10 */
+#define PIO_PB18X1_AD11      (1u << 18) /**< \brief Adc signal: AD11 */
+#define PIO_PB19X1_AD12      (1u << 19) /**< \brief Adc signal: AD12 */
+#define PIO_PB20X1_AD13      (1u << 20) /**< \brief Adc signal: AD13 */
+#define PIO_PB21X1_AD14      (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PB21X1_WKUP13    (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */
+#define PIO_PA4X1_AD2        (1u << 4)  /**< \brief Adc signal: AD2 */
+#define PIO_PA6X1_AD3        (1u << 6)  /**< \brief Adc signal: AD3 */
+#define PIO_PA22X1_AD4       (1u << 22) /**< \brief Adc signal: AD4 */
+#define PIO_PA23X1_AD5       (1u << 23) /**< \brief Adc signal: AD5 */
+#define PIO_PA24X1_AD6       (1u << 24) /**< \brief Adc signal: AD6 */
+#define PIO_PA16X1_AD7       (1u << 16) /**< \brief Adc signal: AD7 */
+#define PIO_PB12X1_AD8       (1u << 12) /**< \brief Adc signal: AD8 */
+#define PIO_PB13X1_AD9       (1u << 13) /**< \brief Adc signal: AD9 */
+#define PIO_PA11B_ADTRG      (1u << 11) /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for CAN0 peripheral ========== */
+#define PIO_PA1A_CANRX0      (1u << 1)  /**< \brief Can0 signal: CANRX0 */
+#define PIO_PA0A_CANTX0      (1u << 0)  /**< \brief Can0 signal: CANTX0 */
+/* ========== Pio definition for CAN1 peripheral ========== */
+#define PIO_PB15A_CANRX1     (1u << 15) /**< \brief Can1 signal: CANRX1 */
+#define PIO_PB14A_CANTX1     (1u << 14) /**< \brief Can1 signal: CANTX1 */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB15X1_DAC0      (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB15X1_WKUP12    (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */
+#define PIO_PB16X1_DAC1      (1u << 16) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA10B_DATRG      (1u << 10) /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC21A_A0         (1u << 21) /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PC21A_NBS0       (1u << 21) /**< \brief Ebi signal: A0/NBS0 */
+#define PIO_PC22A_A1         (1u << 22) /**< \brief Ebi signal: A1 */
+#define PIO_PD0A_A10         (1u << 0)  /**< \brief Ebi signal: A10 */
+#define PIO_PD22A_A10        (1u << 22) /**< \brief Ebi signal: A10 */
+#define PIO_PD1A_A11         (1u << 1)  /**< \brief Ebi signal: A11 */
+#define PIO_PD23A_A11        (1u << 23) /**< \brief Ebi signal: A11 */
+#define PIO_PD2A_A12         (1u << 2)  /**< \brief Ebi signal: A12 */
+#define PIO_PD24A_A12        (1u << 24) /**< \brief Ebi signal: A12 */
+#define PIO_PD3A_A13         (1u << 3)  /**< \brief Ebi signal: A13 */
+#define PIO_PD25A_A13        (1u << 25) /**< \brief Ebi signal: A13 */
+#define PIO_PD4A_A14         (1u << 4)  /**< \brief Ebi signal: A14 */
+#define PIO_PD26A_A14        (1u << 26) /**< \brief Ebi signal: A14 */
+#define PIO_PD5A_A15         (1u << 5)  /**< \brief Ebi signal: A15 */
+#define PIO_PD27A_A15        (1u << 27) /**< \brief Ebi signal: A15 */
+#define PIO_PD6A_A16         (1u << 6)  /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD6A_BA0         (1u << 6)  /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD28A_A16        (1u << 28) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD28A_BA0        (1u << 28) /**< \brief Ebi signal: A16/BA0 */
+#define PIO_PD7A_A17         (1u << 7)  /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD7A_BA1         (1u << 7)  /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD29A_A17        (1u << 29) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PD29A_BA1        (1u << 29) /**< \brief Ebi signal: A17/BA1 */
+#define PIO_PA25B_A18        (1u << 25) /**< \brief Ebi signal: A18 */
+#define PIO_PB10B_A18        (1u << 10) /**< \brief Ebi signal: A18 */
+#define PIO_PD30A_A18        (1u << 30) /**< \brief Ebi signal: A18 */
+#define PIO_PA26B_A19        (1u << 26) /**< \brief Ebi signal: A19 */
+#define PIO_PB11B_A19        (1u << 11) /**< \brief Ebi signal: A19 */
+#define PIO_PE0A_A19         (1u << 0)  /**< \brief Ebi signal: A19 */
+#define PIO_PC23A_A2         (1u << 23) /**< \brief Ebi signal: A2 */
+#define PIO_PA18B_A20        (1u << 18) /**< \brief Ebi signal: A20 */
+#define PIO_PA27B_A20        (1u << 27) /**< \brief Ebi signal: A20 */
+#define PIO_PE1A_A20         (1u << 1)  /**< \brief Ebi signal: A20 */
+#define PIO_PD8A_A21         (1u << 8)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PD8A_NANDALE     (1u << 8)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PE2A_A21         (1u << 2)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PE2A_NANDALE     (1u << 2)  /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PD9A_A22         (1u << 9)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PD9A_NANDCLE     (1u << 9)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE3A_A22         (1u << 3)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE3A_NANDCLE     (1u << 3)  /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PE4A_A23         (1u << 4)  /**< \brief Ebi signal: A23 */
+#define PIO_PC24A_A3         (1u << 24) /**< \brief Ebi signal: A3 */
+#define PIO_PC25A_A4         (1u << 25) /**< \brief Ebi signal: A4 */
+#define PIO_PC26A_A5         (1u << 26) /**< \brief Ebi signal: A5 */
+#define PIO_PD17A_A5         (1u << 17) /**< \brief Ebi signal: A5 */
+#define PIO_PC27A_A6         (1u << 27) /**< \brief Ebi signal: A6 */
+#define PIO_PD18A_A6         (1u << 18) /**< \brief Ebi signal: A6 */
+#define PIO_PC28A_A7         (1u << 28) /**< \brief Ebi signal: A7 */
+#define PIO_PD19A_A7         (1u << 19) /**< \brief Ebi signal: A7 */
+#define PIO_PC29A_A8         (1u << 29) /**< \brief Ebi signal: A8 */
+#define PIO_PD20A_A8         (1u << 20) /**< \brief Ebi signal: A8 */
+#define PIO_PC30A_A9         (1u << 30) /**< \brief Ebi signal: A9 */
+#define PIO_PD21A_A9         (1u << 21) /**< \brief Ebi signal: A9 */
+#define PIO_PD16A_CAS        (1u << 16) /**< \brief Ebi signal: CAS */
+#define PIO_PC2A_D0          (1u << 2)  /**< \brief Ebi signal: D0 */
+#define PIO_PC3A_D1          (1u << 3)  /**< \brief Ebi signal: D1 */
+#define PIO_PC12A_D10        (1u << 12) /**< \brief Ebi signal: D10 */
+#define PIO_PC13A_D11        (1u << 13) /**< \brief Ebi signal: D11 */
+#define PIO_PC14A_D12        (1u << 14) /**< \brief Ebi signal: D12 */
+#define PIO_PC15A_D13        (1u << 15) /**< \brief Ebi signal: D13 */
+#define PIO_PC16A_D14        (1u << 16) /**< \brief Ebi signal: D14 */
+#define PIO_PC17A_D15        (1u << 17) /**< \brief Ebi signal: D15 */
+#define PIO_PC4A_D2          (1u << 4)  /**< \brief Ebi signal: D2 */
+#define PIO_PC5A_D3          (1u << 5)  /**< \brief Ebi signal: D3 */
+#define PIO_PC6A_D4          (1u << 6)  /**< \brief Ebi signal: D4 */
+#define PIO_PC7A_D5          (1u << 7)  /**< \brief Ebi signal: D5 */
+#define PIO_PC8A_D6          (1u << 8)  /**< \brief Ebi signal: D6 */
+#define PIO_PC9A_D7          (1u << 9)  /**< \brief Ebi signal: D7 */
+#define PIO_PC10A_D8         (1u << 10) /**< \brief Ebi signal: D8 */
+#define PIO_PC11A_D9         (1u << 11) /**< \brief Ebi signal: D9 */
+#define PIO_PC19A_NANDOE     (1u << 19) /**< \brief Ebi signal: NANDOE */
+#define PIO_PA2B_NANDRDY     (1u << 2)  /**< \brief Ebi signal: NANDRDY */
+#define PIO_PC20A_NANDWE     (1u << 20) /**< \brief Ebi signal: NANDWE */
+#define PIO_PA6B_NCS0        (1u << 6)  /**< \brief Ebi signal: NCS0 */
+#define PIO_PA7B_NCS1        (1u << 7)  /**< \brief Ebi signal: NCS1 */
+#define PIO_PB24B_NCS2       (1u << 24) /**< \brief Ebi signal: NCS2 */
+#define PIO_PB27A_NCS3       (1u << 27) /**< \brief Ebi signal: NCS3 */
+#define PIO_PE5A_NCS4        (1u << 5)  /**< \brief Ebi signal: NCS4 */
+#define PIO_PE6A_NCS5        (1u << 6)  /**< \brief Ebi signal: NCS5 */
+#define PIO_PE18B_NCS6       (1u << 18) /**< \brief Ebi signal: NCS6 */
+#define PIO_PE27A_NCS7       (1u << 27) /**< \brief Ebi signal: NCS7 */
+#define PIO_PA29B_NRD        (1u << 29) /**< \brief Ebi signal: NRD */
+#define PIO_PA4B_NWAIT       (1u << 4)  /**< \brief Ebi signal: NWAIT */
+#define PIO_PC18A_NWR0       (1u << 18) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PC18A_NWE        (1u << 18) /**< \brief Ebi signal: NWR0/NWE */
+#define PIO_PD10A_NWR1       (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PD10A_NBS1       (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */
+#define PIO_PD15A_RAS        (1u << 15) /**< \brief Ebi signal: RAS */
+#define PIO_PD11A_SDA10      (1u << 11) /**< \brief Ebi signal: SDA10 */
+#define PIO_PD13A_SDCKE      (1u << 13) /**< \brief Ebi signal: SDCKE */
+#define PIO_PD12A_SDCS       (1u << 12) /**< \brief Ebi signal: SDCS */
+#define PIO_PD14A_SDWE       (1u << 14) /**< \brief Ebi signal: SDWE */
+/* ========== Pio definition for EMAC peripheral ========== */
+#define PIO_PC13B_ECOL       (1u << 13) /**< \brief Emac signal: ECOL */
+#define PIO_PC10B_ECRS       (1u << 10) /**< \brief Emac signal: ECRS */
+#define PIO_PB4A_ECRSDV      (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB4A_ERXDV       (1u << 4)  /**< \brief Emac signal: ECRSDV/ERXDV */
+#define PIO_PB8A_EMDC        (1u << 8)  /**< \brief Emac signal: EMDC */
+#define PIO_PB9A_EMDIO       (1u << 9)  /**< \brief Emac signal: EMDIO */
+#define PIO_PB5A_ERX0        (1u << 5)  /**< \brief Emac signal: ERX0 */
+#define PIO_PB6A_ERX1        (1u << 6)  /**< \brief Emac signal: ERX1 */
+#define PIO_PC11B_ERX2       (1u << 11) /**< \brief Emac signal: ERX2 */
+#define PIO_PC12B_ERX3       (1u << 12) /**< \brief Emac signal: ERX3 */
+#define PIO_PC14B_ERXCK      (1u << 14) /**< \brief Emac signal: ERXCK */
+#define PIO_PB7A_ERXER       (1u << 7)  /**< \brief Emac signal: ERXER */
+#define PIO_PB2A_ETX0        (1u << 2)  /**< \brief Emac signal: ETX0 */
+#define PIO_PB3A_ETX1        (1u << 3)  /**< \brief Emac signal: ETX1 */
+#define PIO_PC15B_ETX2       (1u << 15) /**< \brief Emac signal: ETX2 */
+#define PIO_PC16B_ETX3       (1u << 16) /**< \brief Emac signal: ETX3 */
+#define PIO_PB0A_ETXCK       (1u << 0)  /**< \brief Emac signal: ETXCK */
+#define PIO_PB1A_ETXEN       (1u << 1)  /**< \brief Emac signal: ETXEN */
+#define PIO_PC17B_ETXER      (1u << 17) /**< \brief Emac signal: ETXER */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA20A_MCCDA      (1u << 20) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PE20B_MCCDB      (1u << 20) /**< \brief Hsmci signal: MCCDB */
+#define PIO_PA19A_MCCK       (1u << 19) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA21A_MCDA0      (1u << 21) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA22A_MCDA1      (1u << 22) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA23A_MCDA2      (1u << 23) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA24A_MCDA3      (1u << 24) /**< \brief Hsmci signal: MCDA3 */
+#define PIO_PD0B_MCDA4       (1u << 0)  /**< \brief Hsmci signal: MCDA4 */
+#define PIO_PD1B_MCDA5       (1u << 1)  /**< \brief Hsmci signal: MCDA5 */
+#define PIO_PD2B_MCDA6       (1u << 2)  /**< \brief Hsmci signal: MCDA6 */
+#define PIO_PD3B_MCDA7       (1u << 3)  /**< \brief Hsmci signal: MCDA7 */
+#define PIO_PE22B_MCDB0      (1u << 22) /**< \brief Hsmci signal: MCDB0 */
+#define PIO_PE24B_MCDB1      (1u << 24) /**< \brief Hsmci signal: MCDB1 */
+#define PIO_PE26B_MCDB2      (1u << 26) /**< \brief Hsmci signal: MCDB2 */
+#define PIO_PE27B_MCDB3      (1u << 27) /**< \brief Hsmci signal: MCDB3 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA1B_PCK0        (1u << 1)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB22B_PCK0       (1u << 22) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA24B_PCK1       (1u << 24) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA30B_PCK1       (1u << 30) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA28B_PCK2       (1u << 28) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2       (1u << 31) /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA5B_PWMFI0      (1u << 5)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA3B_PWMFI1      (1u << 3)  /**< \brief Pwm signal: PWMFI1 */
+#define PIO_PD6B_PWMFI2      (1u << 6)  /**< \brief Pwm signal: PWMFI2 */
+#define PIO_PA8B_PWMH0       (1u << 8)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB12B_PWMH0      (1u << 12) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC3B_PWMH0       (1u << 3)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PE15A_PWMH0      (1u << 15) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA19B_PWMH1      (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB13B_PWMH1      (1u << 13) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC5B_PWMH1       (1u << 5)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PE16A_PWMH1      (1u << 16) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA13B_PWMH2      (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB14B_PWMH2      (1u << 14) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC7B_PWMH2       (1u << 7)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB15B_PWMH3      (1u << 15) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC9B_PWMH3       (1u << 9)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PF3A_PWMH3       (1u << 3)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC20B_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PE20A_PWMH4      (1u << 20) /**< \brief Pwm signal: PWMH4 */
+#define PIO_PC19B_PWMH5      (1u << 19) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PE22A_PWMH5      (1u << 22) /**< \brief Pwm signal: PWMH5 */
+#define PIO_PC18B_PWMH6      (1u << 18) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE24A_PWMH6      (1u << 24) /**< \brief Pwm signal: PWMH6 */
+#define PIO_PE26A_PWMH7      (1u << 26) /**< \brief Pwm signal: PWMH7 */
+#define PIO_PA21B_PWML0      (1u << 21) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB16B_PWML0      (1u << 16) /**< \brief Pwm signal: PWML0 */
+#define PIO_PC2B_PWML0       (1u << 2)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PE18A_PWML0      (1u << 18) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA12B_PWML1      (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB17B_PWML1      (1u << 17) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC4B_PWML1       (1u << 4)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PA20B_PWML2      (1u << 20) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB18B_PWML2      (1u << 18) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC6B_PWML2       (1u << 6)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PE17A_PWML2      (1u << 17) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA0B_PWML3       (1u << 0)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB19B_PWML3      (1u << 19) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC8B_PWML3       (1u << 8)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PB6B_PWML4       (1u << 6)  /**< \brief Pwm signal: PWML4 */
+#define PIO_PC21B_PWML4      (1u << 21) /**< \brief Pwm signal: PWML4 */
+#define PIO_PE19A_PWML4      (1u << 19) /**< \brief Pwm signal: PWML4 */
+#define PIO_PB7B_PWML5       (1u << 7)  /**< \brief Pwm signal: PWML5 */
+#define PIO_PC22B_PWML5      (1u << 22) /**< \brief Pwm signal: PWML5 */
+#define PIO_PE21A_PWML5      (1u << 21) /**< \brief Pwm signal: PWML5 */
+#define PIO_PB8B_PWML6       (1u << 8)  /**< \brief Pwm signal: PWML6 */
+#define PIO_PC23B_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PE23A_PWML6      (1u << 23) /**< \brief Pwm signal: PWML6 */
+#define PIO_PB9B_PWML7       (1u << 9)  /**< \brief Pwm signal: PWML7 */
+#define PIO_PC24B_PWML7      (1u << 24) /**< \brief Pwm signal: PWML7 */
+#define PIO_PE25A_PWML7      (1u << 25) /**< \brief Pwm signal: PWML7 */
+/* ========== Pio definition for SPI0 peripheral ========== */
+#define PIO_PA25A_SPI0_MISO  (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */
+#define PIO_PA26A_SPI0_MOSI  (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */
+#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */
+#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */
+#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */
+#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */
+#define PIO_PA27A_SPI0_SPCK  (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */
+/* ========== Pio definition for SPI1 peripheral ========== */
+#define PIO_PE28A_SPI1_MISO  (1u << 28) /**< \brief Spi1 signal: SPI1_MISO */
+#define PIO_PE29A_SPI1_MOSI  (1u << 29) /**< \brief Spi1 signal: SPI1_MOSI */
+#define PIO_PE31A_SPI1_NPCS0 (1u << 31) /**< \brief Spi1 signal: SPI1_NPCS0 */
+#define PIO_PF0A_SPI1_NPCS1  (1u << 0)  /**< \brief Spi1 signal: SPI1_NPCS1 */
+#define PIO_PF1A_SPI1_NPCS2  (1u << 1)  /**< \brief Spi1 signal: SPI1_NPCS2 */
+#define PIO_PF2A_SPI1_NPCS3  (1u << 2)  /**< \brief Spi1 signal: SPI1_NPCS3 */
+#define PIO_PE30A_SPI1_SPCK  (1u << 30) /**< \brief Spi1 signal: SPI1_SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PB18A_RD         (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PB17A_RF         (1u << 17) /**< \brief Ssc signal: RF */
+#define PIO_PB19A_RK         (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA16B_TD         (1u << 16) /**< \brief Ssc signal: TD */
+#define PIO_PA15B_TF         (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA14B_TK         (1u << 14) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PB26B_TCLK0      (1u << 26) /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA4A_TCLK1       (1u << 4)  /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA7A_TCLK2       (1u << 7)  /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PB25B_TIOA0      (1u << 25) /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA2A_TIOA1       (1u << 2)  /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA5A_TIOA2       (1u << 5)  /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PB27B_TIOB0      (1u << 27) /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA3A_TIOB1       (1u << 3)  /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA6A_TIOB2       (1u << 6)  /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PA22B_TCLK3      (1u << 22) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PA23B_TCLK4      (1u << 23) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PB16A_TCLK5      (1u << 16) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PB0B_TIOA3       (1u << 0)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PE9A_TIOA3       (1u << 9)  /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PB2B_TIOA4       (1u << 2)  /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PE11A_TIOA4      (1u << 11) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PB4B_TIOA5       (1u << 4)  /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PE13A_TIOA5      (1u << 13) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PB1B_TIOB3       (1u << 1)  /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PE10A_TIOB3      (1u << 10) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PB3B_TIOB4       (1u << 3)  /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PE12A_TIOB4      (1u << 12) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PB5B_TIOB5       (1u << 5)  /**< \brief Tc1 signal: TIOB5 */
+#define PIO_PE14A_TIOB5      (1u << 14) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TC2 peripheral ========== */
+#define PIO_PC27B_TCLK6      (1u << 27) /**< \brief Tc2 signal: TCLK6 */
+#define PIO_PC30B_TCLK7      (1u << 30) /**< \brief Tc2 signal: TCLK7 */
+#define PIO_PD9B_TCLK8       (1u << 9)  /**< \brief Tc2 signal: TCLK8 */
+#define PIO_PC25B_TIOA6      (1u << 25) /**< \brief Tc2 signal: TIOA6 */
+#define PIO_PC28B_TIOA7      (1u << 28) /**< \brief Tc2 signal: TIOA7 */
+#define PIO_PD7B_TIOA8       (1u << 7)  /**< \brief Tc2 signal: TIOA8 */
+#define PIO_PC26B_TIOB6      (1u << 26) /**< \brief Tc2 signal: TIOB6 */
+#define PIO_PC29B_TIOB7      (1u << 29) /**< \brief Tc2 signal: TIOB7 */
+#define PIO_PD8B_TIOB8       (1u << 8)  /**< \brief Tc2 signal: TIOB8 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA18A_TWCK0      (1u << 18) /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA17A_TWD0       (1u << 17) /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB13A_TWCK1      (1u << 13) /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB12A_TWD1       (1u << 12) /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART peripheral ========== */
+#define PIO_PA8A_URXD        (1u << 8)  /**< \brief Uart signal: URXD */
+#define PIO_PA9A_UTXD        (1u << 9)  /**< \brief Uart signal: UTXD */
+/* ========== Pio definition for UOTGHS peripheral ========== */
+#define PIO_PB11A_UOTGID     (1u << 11) /**< \brief Uotghs signal: UOTGID */
+#define PIO_PB10A_UOTGVBOF   (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PB26A_CTS0       (1u << 26) /**< \brief Usart0 signal: CTS0 */
+#define PIO_PB25A_RTS0       (1u << 25) /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA10A_RXD0       (1u << 10) /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA17B_SCK0       (1u << 17) /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA11A_TXD0       (1u << 11) /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA15A_CTS1       (1u << 15) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA14A_RTS1       (1u << 14) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA12A_RXD1       (1u << 12) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA16A_SCK1       (1u << 16) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA13A_TXD1       (1u << 13) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio definition for USART2 peripheral ========== */
+#define PIO_PB23A_CTS2       (1u << 23) /**< \brief Usart2 signal: CTS2 */
+#define PIO_PB22A_RTS2       (1u << 22) /**< \brief Usart2 signal: RTS2 */
+#define PIO_PB21A_RXD2       (1u << 21) /**< \brief Usart2 signal: RXD2 */
+#define PIO_PB24A_SCK2       (1u << 24) /**< \brief Usart2 signal: SCK2 */
+#define PIO_PB20A_TXD2       (1u << 20) /**< \brief Usart2 signal: TXD2 */
+/* ========== Pio definition for USART3 peripheral ========== */
+#define PIO_PF4A_CTS3        (1u << 4)  /**< \brief Usart3 signal: CTS3 */
+#define PIO_PF5A_RTS3        (1u << 5)  /**< \brief Usart3 signal: RTS3 */
+#define PIO_PD5B_RXD3        (1u << 5)  /**< \brief Usart3 signal: RXD3 */
+#define PIO_PE16B_SCK3       (1u << 16) /**< \brief Usart3 signal: SCK3 */
+#define PIO_PD4B_TXD3        (1u << 4)  /**< \brief Usart3 signal: TXD3 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX          0
+#define PIO_PA1_IDX          1
+#define PIO_PA2_IDX          2
+#define PIO_PA3_IDX          3
+#define PIO_PA4_IDX          4
+#define PIO_PA5_IDX          5
+#define PIO_PA6_IDX          6
+#define PIO_PA7_IDX          7
+#define PIO_PA8_IDX          8
+#define PIO_PA9_IDX          9
+#define PIO_PA10_IDX         10
+#define PIO_PA11_IDX         11
+#define PIO_PA12_IDX         12
+#define PIO_PA13_IDX         13
+#define PIO_PA14_IDX         14
+#define PIO_PA15_IDX         15
+#define PIO_PA16_IDX         16
+#define PIO_PA17_IDX         17
+#define PIO_PA18_IDX         18
+#define PIO_PA19_IDX         19
+#define PIO_PA20_IDX         20
+#define PIO_PA21_IDX         21
+#define PIO_PA22_IDX         22
+#define PIO_PA23_IDX         23
+#define PIO_PA24_IDX         24
+#define PIO_PA25_IDX         25
+#define PIO_PA26_IDX         26
+#define PIO_PA27_IDX         27
+#define PIO_PA28_IDX         28
+#define PIO_PA29_IDX         29
+#define PIO_PA30_IDX         30
+#define PIO_PA31_IDX         31
+#define PIO_PB0_IDX          32
+#define PIO_PB1_IDX          33
+#define PIO_PB2_IDX          34
+#define PIO_PB3_IDX          35
+#define PIO_PB4_IDX          36
+#define PIO_PB5_IDX          37
+#define PIO_PB6_IDX          38
+#define PIO_PB7_IDX          39
+#define PIO_PB8_IDX          40
+#define PIO_PB9_IDX          41
+#define PIO_PB10_IDX         42
+#define PIO_PB11_IDX         43
+#define PIO_PB12_IDX         44
+#define PIO_PB13_IDX         45
+#define PIO_PB14_IDX         46
+#define PIO_PB15_IDX         47
+#define PIO_PB16_IDX         48
+#define PIO_PB17_IDX         49
+#define PIO_PB18_IDX         50
+#define PIO_PB19_IDX         51
+#define PIO_PB20_IDX         52
+#define PIO_PB21_IDX         53
+#define PIO_PB22_IDX         54
+#define PIO_PB23_IDX         55
+#define PIO_PB24_IDX         56
+#define PIO_PB25_IDX         57
+#define PIO_PB26_IDX         58
+#define PIO_PB27_IDX         59
+#define PIO_PB28_IDX         60
+#define PIO_PB29_IDX         61
+#define PIO_PB30_IDX         62
+#define PIO_PB31_IDX         63
+#define PIO_PC0_IDX          64
+#define PIO_PC1_IDX          65
+#define PIO_PC2_IDX          66
+#define PIO_PC3_IDX          67
+#define PIO_PC4_IDX          68
+#define PIO_PC5_IDX          69
+#define PIO_PC6_IDX          70
+#define PIO_PC7_IDX          71
+#define PIO_PC8_IDX          72
+#define PIO_PC9_IDX          73
+#define PIO_PC10_IDX         74
+#define PIO_PC11_IDX         75
+#define PIO_PC12_IDX         76
+#define PIO_PC13_IDX         77
+#define PIO_PC14_IDX         78
+#define PIO_PC15_IDX         79
+#define PIO_PC16_IDX         80
+#define PIO_PC17_IDX         81
+#define PIO_PC18_IDX         82
+#define PIO_PC19_IDX         83
+#define PIO_PC20_IDX         84
+#define PIO_PC21_IDX         85
+#define PIO_PC22_IDX         86
+#define PIO_PC23_IDX         87
+#define PIO_PC24_IDX         88
+#define PIO_PC25_IDX         89
+#define PIO_PC26_IDX         90
+#define PIO_PC27_IDX         91
+#define PIO_PC28_IDX         92
+#define PIO_PC29_IDX         93
+#define PIO_PC30_IDX         94
+#define PIO_PD0_IDX          96
+#define PIO_PD1_IDX          97
+#define PIO_PD2_IDX          98
+#define PIO_PD3_IDX          99
+#define PIO_PD4_IDX          100
+#define PIO_PD5_IDX          101
+#define PIO_PD6_IDX          102
+#define PIO_PD7_IDX          103
+#define PIO_PD8_IDX          104
+#define PIO_PD9_IDX          105
+#define PIO_PD10_IDX         106
+#define PIO_PD11_IDX         107
+#define PIO_PD12_IDX         108
+#define PIO_PD13_IDX         109
+#define PIO_PD14_IDX         110
+#define PIO_PD15_IDX         111
+#define PIO_PD16_IDX         112
+#define PIO_PD17_IDX         113
+#define PIO_PD18_IDX         114
+#define PIO_PD19_IDX         115
+#define PIO_PD20_IDX         116
+#define PIO_PD21_IDX         117
+#define PIO_PD22_IDX         118
+#define PIO_PD23_IDX         119
+#define PIO_PD24_IDX         120
+#define PIO_PD25_IDX         121
+#define PIO_PD26_IDX         122
+#define PIO_PD27_IDX         123
+#define PIO_PD28_IDX         124
+#define PIO_PD29_IDX         125
+#define PIO_PD30_IDX         126
+#define PIO_PE0_IDX          128
+#define PIO_PE1_IDX          129
+#define PIO_PE2_IDX          130
+#define PIO_PE3_IDX          131
+#define PIO_PE4_IDX          132
+#define PIO_PE5_IDX          133
+#define PIO_PE6_IDX          134
+#define PIO_PE7_IDX          135
+#define PIO_PE8_IDX          136
+#define PIO_PE9_IDX          137
+#define PIO_PE10_IDX         138
+#define PIO_PE11_IDX         139
+#define PIO_PE12_IDX         140
+#define PIO_PE13_IDX         141
+#define PIO_PE14_IDX         142
+#define PIO_PE15_IDX         143
+#define PIO_PE16_IDX         144
+#define PIO_PE17_IDX         145
+#define PIO_PE18_IDX         146
+#define PIO_PE19_IDX         147
+#define PIO_PE20_IDX         148
+#define PIO_PE21_IDX         149
+#define PIO_PE22_IDX         150
+#define PIO_PE23_IDX         151
+#define PIO_PE24_IDX         152
+#define PIO_PE25_IDX         153
+#define PIO_PE26_IDX         154
+#define PIO_PE27_IDX         155
+#define PIO_PE28_IDX         156
+#define PIO_PE29_IDX         157
+#define PIO_PE30_IDX         158
+#define PIO_PE31_IDX         159
+#define PIO_PF0_IDX          160
+#define PIO_PF1_IDX          161
+#define PIO_PF2_IDX          162
+#define PIO_PF3_IDX          163
+#define PIO_PF4_IDX          164
+#define PIO_PF5_IDX          165
+
+#endif /* _SAM3X8H_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3a4c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3a4c.h
new file mode 100644
index 0000000..ad3054a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3a4c.h
@@ -0,0 +1,536 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3A4C_
+#define _SAM3A4C_
+
+/** \addtogroup SAM3A4C_definitions SAM3A4C definitions
+  This file defines all structures and symbols for SAM3A4C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A4C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3A4C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3A4C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3A4C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3A4C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3A4C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3A4C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3A4C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3A4C Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3A4C Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3A4C Universal Asynchronous Receiver Transceiver (UART) */
+  PIOA_IRQn            = 11, /**< 11 SAM3A4C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3A4C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 17, /**< 17 SAM3A4C USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3A4C USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3A4C USART 2 (USART2) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3A4C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3A4C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3A4C Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3A4C Serial Peripheral Interface (SPI0) */
+  SSC_IRQn             = 26, /**< 26 SAM3A4C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3A4C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3A4C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3A4C Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3A4C Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3A4C Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3A4C Timer Counter 5 (TC5) */
+  PWM_IRQn             = 36, /**< 36 SAM3A4C Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3A4C ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3A4C DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3A4C DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3A4C USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3A4C True Random Number Generator (TRNG) */
+  CAN0_IRQn            = 43, /**< 43 SAM3A4C CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44, /**< 44 SAM3A4C CAN Controller 1 (CAN1) */
+
+  PERIPH_COUNT_IRQn    = 45  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC0_Handler;   /*  6 Enhanced Flash Controller 0 */
+  void* pfnEFC1_Handler;   /*  7 Enhanced Flash Controller 1 */
+  void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transceiver */
+  void* pvReserved9;
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A, */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pfnUSART0_Handler; /* 17 USART 0 */
+  void* pfnUSART1_Handler; /* 18 USART 1 */
+  void* pfnUSART2_Handler; /* 19 USART 2 */
+  void* pvReserved20;
+  void* pfnHSMCI_Handler;  /* 21 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 22 Two-Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 23 Two-Wire Interface 1 */
+  void* pfnSPI0_Handler;   /* 24 Serial Peripheral Interface */
+  void* pvReserved25;
+  void* pfnSSC_Handler;    /* 26 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 27 Timer Counter 0 */
+  void* pfnTC1_Handler;    /* 28 Timer Counter 1 */
+  void* pfnTC2_Handler;    /* 29 Timer Counter 2 */
+  void* pfnTC3_Handler;    /* 30 Timer Counter 3 */
+  void* pfnTC4_Handler;    /* 31 Timer Counter 4 */
+  void* pfnTC5_Handler;    /* 32 Timer Counter 5 */
+  void* pvReserved33;
+  void* pvReserved34;
+  void* pvReserved35;
+  void* pfnPWM_Handler;    /* 36 Pulse Width Modulation Controller */
+  void* pfnADC_Handler;    /* 37 ADC Controller */
+  void* pfnDACC_Handler;   /* 38 DAC Controller */
+  void* pfnDMAC_Handler;   /* 39 DMA Controller */
+  void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */
+  void* pfnTRNG_Handler;   /* 41 True Random Number Generator */
+  void* pvReserved42;
+  void* pfnCAN0_Handler;   /* 43 CAN Controller 0 */
+  void* pfnCAN1_Handler;   /* 44 CAN Controller 1 */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void CAN0_Handler       ( void );
+void CAN1_Handler       ( void );
+void DACC_Handler       ( void );
+void DMAC_Handler       ( void );
+void EFC0_Handler       ( void );
+void EFC1_Handler       ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI0_Handler       ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TRNG_Handler       ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART_Handler       ( void );
+void UOTGHS_Handler     ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3A4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3A4C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3A4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3xa.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3A4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A4C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A4C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A4C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+
+#define ID_PERIPH_COUNT (45) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A4C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A4C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3a4c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x8000u)
+#define IRAM1_SIZE               (0x8000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE+IFLASH1_SIZE)
+#define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3A4C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (84000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3A4C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3a8c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3a8c.h
new file mode 100644
index 0000000..c4c9505
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3a8c.h
@@ -0,0 +1,536 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3A8C_
+#define _SAM3A8C_
+
+/** \addtogroup SAM3A8C_definitions SAM3A8C definitions
+  This file defines all structures and symbols for SAM3A8C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A8C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3A8C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3A8C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3A8C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3A8C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3A8C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3A8C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3A8C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3A8C Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3A8C Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3A8C Universal Asynchronous Receiver Transceiver (UART) */
+  PIOA_IRQn            = 11, /**< 11 SAM3A8C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3A8C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 17, /**< 17 SAM3A8C USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3A8C USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3A8C USART 2 (USART2) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3A8C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3A8C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3A8C Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3A8C Serial Peripheral Interface (SPI0) */
+  SSC_IRQn             = 26, /**< 26 SAM3A8C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3A8C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3A8C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3A8C Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3A8C Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3A8C Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3A8C Timer Counter 5 (TC5) */
+  PWM_IRQn             = 36, /**< 36 SAM3A8C Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3A8C ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3A8C DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3A8C DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3A8C USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3A8C True Random Number Generator (TRNG) */
+  CAN0_IRQn            = 43, /**< 43 SAM3A8C CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44, /**< 44 SAM3A8C CAN Controller 1 (CAN1) */
+
+  PERIPH_COUNT_IRQn    = 45  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC0_Handler;   /*  6 Enhanced Flash Controller 0 */
+  void* pfnEFC1_Handler;   /*  7 Enhanced Flash Controller 1 */
+  void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transceiver */
+  void* pvReserved9;
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A, */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pfnUSART0_Handler; /* 17 USART 0 */
+  void* pfnUSART1_Handler; /* 18 USART 1 */
+  void* pfnUSART2_Handler; /* 19 USART 2 */
+  void* pvReserved20;
+  void* pfnHSMCI_Handler;  /* 21 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 22 Two-Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 23 Two-Wire Interface 1 */
+  void* pfnSPI0_Handler;   /* 24 Serial Peripheral Interface */
+  void* pvReserved25;
+  void* pfnSSC_Handler;    /* 26 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 27 Timer Counter 0 */
+  void* pfnTC1_Handler;    /* 28 Timer Counter 1 */
+  void* pfnTC2_Handler;    /* 29 Timer Counter 2 */
+  void* pfnTC3_Handler;    /* 30 Timer Counter 3 */
+  void* pfnTC4_Handler;    /* 31 Timer Counter 4 */
+  void* pfnTC5_Handler;    /* 32 Timer Counter 5 */
+  void* pvReserved33;
+  void* pvReserved34;
+  void* pvReserved35;
+  void* pfnPWM_Handler;    /* 36 Pulse Width Modulation Controller */
+  void* pfnADC_Handler;    /* 37 ADC Controller */
+  void* pfnDACC_Handler;   /* 38 DAC Controller */
+  void* pfnDMAC_Handler;   /* 39 DMA Controller */
+  void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */
+  void* pfnTRNG_Handler;   /* 41 True Random Number Generator */
+  void* pvReserved42;
+  void* pfnCAN0_Handler;   /* 43 CAN Controller 0 */
+  void* pfnCAN1_Handler;   /* 44 CAN Controller 1 */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void CAN0_Handler       ( void );
+void CAN1_Handler       ( void );
+void DACC_Handler       ( void );
+void DMAC_Handler       ( void );
+void EFC0_Handler       ( void );
+void EFC1_Handler       ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI0_Handler       ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TRNG_Handler       ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART_Handler       ( void );
+void UOTGHS_Handler     ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3A8C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3A8C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3A8C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3xa.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3A8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A8C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A8C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A8C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+
+#define ID_PERIPH_COUNT (45) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A8C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3A8C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3a8c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IRAM0_SIZE               (0x10000u)
+#define IRAM1_SIZE               (0x8000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE+IFLASH1_SIZE)
+#define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3A8C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (84000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3A8C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x4c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x4c.h
new file mode 100644
index 0000000..4eefb65
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x4c.h
@@ -0,0 +1,543 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X4C_
+#define _SAM3X4C_
+
+/** \addtogroup SAM3X4C_definitions SAM3X4C definitions
+  This file defines all structures and symbols for SAM3X4C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3X4C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3X4C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3X4C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3X4C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3X4C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3X4C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3X4C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3X4C Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3X4C Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3X4C Universal Asynchronous Receiver Transceiver (UART) */
+  PIOA_IRQn            = 11, /**< 11 SAM3X4C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3X4C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 17, /**< 17 SAM3X4C USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3X4C USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3X4C USART 2 (USART2) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3X4C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3X4C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3X4C Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3X4C Serial Peripheral Interface (SPI0) */
+  SSC_IRQn             = 26, /**< 26 SAM3X4C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3X4C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3X4C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3X4C Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3X4C Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3X4C Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3X4C Timer Counter 5 (TC5) */
+  PWM_IRQn             = 36, /**< 36 SAM3X4C Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3X4C ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3X4C DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3X4C DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3X4C USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3X4C True Random Number Generator (TRNG) */
+  EMAC_IRQn            = 42, /**< 42 SAM3X4C Ethernet MAC (EMAC) */
+  CAN0_IRQn            = 43, /**< 43 SAM3X4C CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44, /**< 44 SAM3X4C CAN Controller 1 (CAN1) */
+
+  PERIPH_COUNT_IRQn    = 45  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC0_Handler;   /*  6 Enhanced Flash Controller 0 */
+  void* pfnEFC1_Handler;   /*  7 Enhanced Flash Controller 1 */
+  void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transceiver */
+  void* pvReserved9;
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A, */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pfnUSART0_Handler; /* 17 USART 0 */
+  void* pfnUSART1_Handler; /* 18 USART 1 */
+  void* pfnUSART2_Handler; /* 19 USART 2 */
+  void* pvReserved20;
+  void* pfnHSMCI_Handler;  /* 21 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 22 Two-Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 23 Two-Wire Interface 1 */
+  void* pfnSPI0_Handler;   /* 24 Serial Peripheral Interface */
+  void* pvReserved25;
+  void* pfnSSC_Handler;    /* 26 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 27 Timer Counter 0 */
+  void* pfnTC1_Handler;    /* 28 Timer Counter 1 */
+  void* pfnTC2_Handler;    /* 29 Timer Counter 2 */
+  void* pfnTC3_Handler;    /* 30 Timer Counter 3 */
+  void* pfnTC4_Handler;    /* 31 Timer Counter 4 */
+  void* pfnTC5_Handler;    /* 32 Timer Counter 5 */
+  void* pvReserved33;
+  void* pvReserved34;
+  void* pvReserved35;
+  void* pfnPWM_Handler;    /* 36 Pulse Width Modulation Controller */
+  void* pfnADC_Handler;    /* 37 ADC Controller */
+  void* pfnDACC_Handler;   /* 38 DAC Controller */
+  void* pfnDMAC_Handler;   /* 39 DMA Controller */
+  void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */
+  void* pfnTRNG_Handler;   /* 41 True Random Number Generator */
+  void* pfnEMAC_Handler;   /* 42 Ethernet MAC */
+  void* pfnCAN0_Handler;   /* 43 CAN Controller 0 */
+  void* pfnCAN1_Handler;   /* 44 CAN Controller 1 */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void CAN0_Handler       ( void );
+void CAN1_Handler       ( void );
+void DACC_Handler       ( void );
+void DMAC_Handler       ( void );
+void EFC0_Handler       ( void );
+void EFC1_Handler       ( void );
+void EMAC_Handler       ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI0_Handler       ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TRNG_Handler       ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART_Handler       ( void );
+void UOTGHS_Handler     ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3X4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X4C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3xa.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_emac.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_emac.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_EMAC   (42) /**< \brief Ethernet MAC (EMAC) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+
+#define ID_PERIPH_COUNT (45) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       (0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       ((Emac   *)0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3x4c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x8000u)
+#define IRAM1_SIZE               (0x8000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE+IFLASH1_SIZE)
+#define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3X4C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (84000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3X4C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x4e.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x4e.h
new file mode 100644
index 0000000..4bdbc3b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x4e.h
@@ -0,0 +1,583 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X4E_
+#define _SAM3X4E_
+
+/** \addtogroup SAM3X4E_definitions SAM3X4E definitions
+  This file defines all structures and symbols for SAM3X4E:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4E_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3X4E specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3X4E Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3X4E Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3X4E Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3X4E Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3X4E Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3X4E Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3X4E Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3X4E Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3X4E Universal Asynchronous Receiver Transceiver (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3X4E Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3X4E Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3X4E Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3X4E Parallel I/O Controller C (PIOC) */
+  PIOD_IRQn            = 14, /**< 14 SAM3X4E Parallel I/O Controller D (PIOD) */
+  USART0_IRQn          = 17, /**< 17 SAM3X4E USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3X4E USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3X4E USART 2 (USART2) */
+  USART3_IRQn          = 20, /**< 20 SAM3X4E USART 3 (USART3) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3X4E Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3X4E Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3X4E Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3X4E Serial Peripheral Interface (SPI0) */
+  SSC_IRQn             = 26, /**< 26 SAM3X4E Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3X4E Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3X4E Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3X4E Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3X4E Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3X4E Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3X4E Timer Counter 5 (TC5) */
+  TC6_IRQn             = 33, /**< 33 SAM3X4E Timer Counter 6 (TC6) */
+  TC7_IRQn             = 34, /**< 34 SAM3X4E Timer Counter 7 (TC7) */
+  TC8_IRQn             = 35, /**< 35 SAM3X4E Timer Counter 8 (TC8) */
+  PWM_IRQn             = 36, /**< 36 SAM3X4E Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3X4E ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3X4E DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3X4E DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3X4E USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3X4E True Random Number Generator (TRNG) */
+  EMAC_IRQn            = 42, /**< 42 SAM3X4E Ethernet MAC (EMAC) */
+  CAN0_IRQn            = 43, /**< 43 SAM3X4E CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44, /**< 44 SAM3X4E CAN Controller 1 (CAN1) */
+
+  PERIPH_COUNT_IRQn    = 45  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC0_Handler;   /*  6 Enhanced Flash Controller 0 */
+  void* pfnEFC1_Handler;   /*  7 Enhanced Flash Controller 1 */
+  void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transceiver */
+  void* pfnSMC_Handler;    /*  9 Static Memory Controller */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A, */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnPIOD_Handler;   /* 14 Parallel I/O Controller D */
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pfnUSART0_Handler; /* 17 USART 0 */
+  void* pfnUSART1_Handler; /* 18 USART 1 */
+  void* pfnUSART2_Handler; /* 19 USART 2 */
+  void* pfnUSART3_Handler; /* 20 USART 3 */
+  void* pfnHSMCI_Handler;  /* 21 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 22 Two-Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 23 Two-Wire Interface 1 */
+  void* pfnSPI0_Handler;   /* 24 Serial Peripheral Interface */
+  void* pvReserved25;
+  void* pfnSSC_Handler;    /* 26 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 27 Timer Counter 0 */
+  void* pfnTC1_Handler;    /* 28 Timer Counter 1 */
+  void* pfnTC2_Handler;    /* 29 Timer Counter 2 */
+  void* pfnTC3_Handler;    /* 30 Timer Counter 3 */
+  void* pfnTC4_Handler;    /* 31 Timer Counter 4 */
+  void* pfnTC5_Handler;    /* 32 Timer Counter 5 */
+  void* pfnTC6_Handler;    /* 33 Timer Counter 6 */
+  void* pfnTC7_Handler;    /* 34 Timer Counter 7 */
+  void* pfnTC8_Handler;    /* 35 Timer Counter 8 */
+  void* pfnPWM_Handler;    /* 36 Pulse Width Modulation Controller */
+  void* pfnADC_Handler;    /* 37 ADC Controller */
+  void* pfnDACC_Handler;   /* 38 DAC Controller */
+  void* pfnDMAC_Handler;   /* 39 DMA Controller */
+  void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */
+  void* pfnTRNG_Handler;   /* 41 True Random Number Generator */
+  void* pfnEMAC_Handler;   /* 42 Ethernet MAC */
+  void* pfnCAN0_Handler;   /* 43 CAN Controller 0 */
+  void* pfnCAN1_Handler;   /* 44 CAN Controller 1 */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void CAN0_Handler       ( void );
+void CAN1_Handler       ( void );
+void DACC_Handler       ( void );
+void DMAC_Handler       ( void );
+void EFC0_Handler       ( void );
+void EFC1_Handler       ( void );
+void EMAC_Handler       ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PIOD_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI0_Handler       ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TC6_Handler        ( void );
+void TC7_Handler        ( void );
+void TC8_Handler        ( void );
+void TRNG_Handler       ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART_Handler       ( void );
+void UOTGHS_Handler     ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void USART3_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3X4E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X4E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X4E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3xa.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4E_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_emac.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4E_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_tc2.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_usart3.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_emac.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_piod.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4E_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_PIOD   (14) /**< \brief Parallel I/O Controller D (PIOD) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_USART3 (20) /**< \brief USART 3 (USART3) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_TC6    (33) /**< \brief Timer Counter 6 (TC6) */
+#define ID_TC7    (34) /**< \brief Timer Counter 7 (TC7) */
+#define ID_TC8    (35) /**< \brief Timer Counter 8 (TC8) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_EMAC   (42) /**< \brief Ethernet MAC (EMAC) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+
+#define ID_PERIPH_COUNT (45) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4E_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TC2        (0x40088000U) /**< \brief (TC2       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     (0x400A4000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       (0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define PIOD       (0x400E1400U) /**< \brief (PIOD      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TC2        ((Tc     *)0x40088000U) /**< \brief (TC2       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     ((Usart  *)0x400A4000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 ((Pdc    *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       ((Emac   *)0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define PIOD       ((Pio    *)0x400E1400U) /**< \brief (PIOD      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X4E_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3x4e.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x8000u)
+#define IRAM1_SIZE               (0x8000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE+IFLASH1_SIZE)
+#define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3X4E */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (84000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3X4E_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x8c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x8c.h
new file mode 100644
index 0000000..f5438cc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x8c.h
@@ -0,0 +1,543 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X8C_
+#define _SAM3X8C_
+
+/** \addtogroup SAM3X8C_definitions SAM3X8C definitions
+  This file defines all structures and symbols for SAM3X8C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3X8C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3X8C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3X8C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3X8C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3X8C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3X8C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3X8C Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3X8C Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3X8C Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3X8C Universal Asynchronous Receiver Transceiver (UART) */
+  PIOA_IRQn            = 11, /**< 11 SAM3X8C Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3X8C Parallel I/O Controller B (PIOB) */
+  USART0_IRQn          = 17, /**< 17 SAM3X8C USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3X8C USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3X8C USART 2 (USART2) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3X8C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3X8C Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3X8C Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3X8C Serial Peripheral Interface (SPI0) */
+  SSC_IRQn             = 26, /**< 26 SAM3X8C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3X8C Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3X8C Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3X8C Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3X8C Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3X8C Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3X8C Timer Counter 5 (TC5) */
+  PWM_IRQn             = 36, /**< 36 SAM3X8C Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3X8C ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3X8C DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3X8C DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3X8C USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3X8C True Random Number Generator (TRNG) */
+  EMAC_IRQn            = 42, /**< 42 SAM3X8C Ethernet MAC (EMAC) */
+  CAN0_IRQn            = 43, /**< 43 SAM3X8C CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44, /**< 44 SAM3X8C CAN Controller 1 (CAN1) */
+
+  PERIPH_COUNT_IRQn    = 45  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC0_Handler;   /*  6 Enhanced Flash Controller 0 */
+  void* pfnEFC1_Handler;   /*  7 Enhanced Flash Controller 1 */
+  void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transceiver */
+  void* pvReserved9;
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A, */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pvReserved13;
+  void* pvReserved14;
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pfnUSART0_Handler; /* 17 USART 0 */
+  void* pfnUSART1_Handler; /* 18 USART 1 */
+  void* pfnUSART2_Handler; /* 19 USART 2 */
+  void* pvReserved20;
+  void* pfnHSMCI_Handler;  /* 21 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 22 Two-Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 23 Two-Wire Interface 1 */
+  void* pfnSPI0_Handler;   /* 24 Serial Peripheral Interface */
+  void* pvReserved25;
+  void* pfnSSC_Handler;    /* 26 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 27 Timer Counter 0 */
+  void* pfnTC1_Handler;    /* 28 Timer Counter 1 */
+  void* pfnTC2_Handler;    /* 29 Timer Counter 2 */
+  void* pfnTC3_Handler;    /* 30 Timer Counter 3 */
+  void* pfnTC4_Handler;    /* 31 Timer Counter 4 */
+  void* pfnTC5_Handler;    /* 32 Timer Counter 5 */
+  void* pvReserved33;
+  void* pvReserved34;
+  void* pvReserved35;
+  void* pfnPWM_Handler;    /* 36 Pulse Width Modulation Controller */
+  void* pfnADC_Handler;    /* 37 ADC Controller */
+  void* pfnDACC_Handler;   /* 38 DAC Controller */
+  void* pfnDMAC_Handler;   /* 39 DMA Controller */
+  void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */
+  void* pfnTRNG_Handler;   /* 41 True Random Number Generator */
+  void* pfnEMAC_Handler;   /* 42 Ethernet MAC */
+  void* pfnCAN0_Handler;   /* 43 CAN Controller 0 */
+  void* pfnCAN1_Handler;   /* 44 CAN Controller 1 */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void CAN0_Handler       ( void );
+void CAN1_Handler       ( void );
+void DACC_Handler       ( void );
+void DMAC_Handler       ( void );
+void EFC0_Handler       ( void );
+void EFC1_Handler       ( void );
+void EMAC_Handler       ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI0_Handler       ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TRNG_Handler       ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART_Handler       ( void );
+void UOTGHS_Handler     ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3X8C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X8C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X8C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3xa.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_emac.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_emac.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_EMAC   (42) /**< \brief Ethernet MAC (EMAC) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+
+#define ID_PERIPH_COUNT (45) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       (0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       ((Emac   *)0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3x8c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IRAM0_SIZE               (0x10000u)
+#define IRAM1_SIZE               (0x8000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE+IFLASH1_SIZE)
+#define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3X8C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (84000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3X8C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x8e.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x8e.h
new file mode 100644
index 0000000..4abf35f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x8e.h
@@ -0,0 +1,583 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X8E_
+#define _SAM3X8E_
+
+/** \addtogroup SAM3X8E_definitions SAM3X8E definitions
+  This file defines all structures and symbols for SAM3X8E:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8E_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3X8E specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3X8E Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3X8E Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3X8E Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3X8E Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3X8E Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3X8E Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3X8E Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3X8E Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3X8E Universal Asynchronous Receiver Transceiver (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3X8E Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3X8E Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3X8E Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3X8E Parallel I/O Controller C (PIOC) */
+  PIOD_IRQn            = 14, /**< 14 SAM3X8E Parallel I/O Controller D (PIOD) */
+  USART0_IRQn          = 17, /**< 17 SAM3X8E USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3X8E USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3X8E USART 2 (USART2) */
+  USART3_IRQn          = 20, /**< 20 SAM3X8E USART 3 (USART3) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3X8E Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3X8E Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3X8E Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3X8E Serial Peripheral Interface (SPI0) */
+  SSC_IRQn             = 26, /**< 26 SAM3X8E Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3X8E Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3X8E Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3X8E Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3X8E Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3X8E Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3X8E Timer Counter 5 (TC5) */
+  TC6_IRQn             = 33, /**< 33 SAM3X8E Timer Counter 6 (TC6) */
+  TC7_IRQn             = 34, /**< 34 SAM3X8E Timer Counter 7 (TC7) */
+  TC8_IRQn             = 35, /**< 35 SAM3X8E Timer Counter 8 (TC8) */
+  PWM_IRQn             = 36, /**< 36 SAM3X8E Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3X8E ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3X8E DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3X8E DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3X8E USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3X8E True Random Number Generator (TRNG) */
+  EMAC_IRQn            = 42, /**< 42 SAM3X8E Ethernet MAC (EMAC) */
+  CAN0_IRQn            = 43, /**< 43 SAM3X8E CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44, /**< 44 SAM3X8E CAN Controller 1 (CAN1) */
+
+  PERIPH_COUNT_IRQn    = 45  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC0_Handler;   /*  6 Enhanced Flash Controller 0 */
+  void* pfnEFC1_Handler;   /*  7 Enhanced Flash Controller 1 */
+  void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transceiver */
+  void* pfnSMC_Handler;    /*  9 Static Memory Controller */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A, */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnPIOD_Handler;   /* 14 Parallel I/O Controller D */
+  void* pvReserved15;
+  void* pvReserved16;
+  void* pfnUSART0_Handler; /* 17 USART 0 */
+  void* pfnUSART1_Handler; /* 18 USART 1 */
+  void* pfnUSART2_Handler; /* 19 USART 2 */
+  void* pfnUSART3_Handler; /* 20 USART 3 */
+  void* pfnHSMCI_Handler;  /* 21 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 22 Two-Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 23 Two-Wire Interface 1 */
+  void* pfnSPI0_Handler;   /* 24 Serial Peripheral Interface */
+  void* pvReserved25;
+  void* pfnSSC_Handler;    /* 26 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 27 Timer Counter 0 */
+  void* pfnTC1_Handler;    /* 28 Timer Counter 1 */
+  void* pfnTC2_Handler;    /* 29 Timer Counter 2 */
+  void* pfnTC3_Handler;    /* 30 Timer Counter 3 */
+  void* pfnTC4_Handler;    /* 31 Timer Counter 4 */
+  void* pfnTC5_Handler;    /* 32 Timer Counter 5 */
+  void* pfnTC6_Handler;    /* 33 Timer Counter 6 */
+  void* pfnTC7_Handler;    /* 34 Timer Counter 7 */
+  void* pfnTC8_Handler;    /* 35 Timer Counter 8 */
+  void* pfnPWM_Handler;    /* 36 Pulse Width Modulation Controller */
+  void* pfnADC_Handler;    /* 37 ADC Controller */
+  void* pfnDACC_Handler;   /* 38 DAC Controller */
+  void* pfnDMAC_Handler;   /* 39 DMA Controller */
+  void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */
+  void* pfnTRNG_Handler;   /* 41 True Random Number Generator */
+  void* pfnEMAC_Handler;   /* 42 Ethernet MAC */
+  void* pfnCAN0_Handler;   /* 43 CAN Controller 0 */
+  void* pfnCAN1_Handler;   /* 44 CAN Controller 1 */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void CAN0_Handler       ( void );
+void CAN1_Handler       ( void );
+void DACC_Handler       ( void );
+void DMAC_Handler       ( void );
+void EFC0_Handler       ( void );
+void EFC1_Handler       ( void );
+void EMAC_Handler       ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PIOD_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI0_Handler       ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TC6_Handler        ( void );
+void TC7_Handler        ( void );
+void TC8_Handler        ( void );
+void TRNG_Handler       ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART_Handler       ( void );
+void UOTGHS_Handler     ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void USART3_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3X8E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X8E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X8E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3xa.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8E_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_emac.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8E_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_tc2.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_usart3.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_emac.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_piod.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8E_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_PIOD   (14) /**< \brief Parallel I/O Controller D (PIOD) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_USART3 (20) /**< \brief USART 3 (USART3) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_TC6    (33) /**< \brief Timer Counter 6 (TC6) */
+#define ID_TC7    (34) /**< \brief Timer Counter 7 (TC7) */
+#define ID_TC8    (35) /**< \brief Timer Counter 8 (TC8) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_EMAC   (42) /**< \brief Ethernet MAC (EMAC) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+
+#define ID_PERIPH_COUNT (45) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8E_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TC2        (0x40088000U) /**< \brief (TC2       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     (0x400A4000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       (0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define PIOD       (0x400E1400U) /**< \brief (PIOD      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TC2        ((Tc     *)0x40088000U) /**< \brief (TC2       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     ((Usart  *)0x400A4000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 ((Pdc    *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       ((Emac   *)0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define PIOD       ((Pio    *)0x400E1400U) /**< \brief (PIOD      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8E_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3x8e.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IRAM0_SIZE               (0x10000u)
+#define IRAM1_SIZE               (0x8000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE+IFLASH1_SIZE)
+#define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3X8E */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (84000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3X8E_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x8h.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x8h.h
new file mode 100644
index 0000000..100a0f4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3x8h.h
@@ -0,0 +1,608 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3X8H_
+#define _SAM3X8H_
+
+/** \addtogroup SAM3X8H_definitions SAM3X8H definitions
+  This file defines all structures and symbols for SAM3X8H:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8H_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M3 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M3 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M3 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M3 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M3 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M3 System Tick Interrupt       */
+/******  SAM3X8H specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM3X8H Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM3X8H Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM3X8H Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM3X8H Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM3X8H Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM3X8H Power Management Controller (PMC) */
+  EFC0_IRQn            =  6, /**<  6 SAM3X8H Enhanced Flash Controller 0 (EFC0) */
+  EFC1_IRQn            =  7, /**<  7 SAM3X8H Enhanced Flash Controller 1 (EFC1) */
+  UART_IRQn            =  8, /**<  8 SAM3X8H Universal Asynchronous Receiver Transceiver (UART) */
+  SMC_IRQn             =  9, /**<  9 SAM3X8H Static Memory Controller (SMC) */
+  SDRAMC_IRQn          = 10, /**< 10 SAM3X8H Synchronous Dynamic RAM Controller (SDRAMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM3X8H Parallel I/O Controller A, (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM3X8H Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM3X8H Parallel I/O Controller C (PIOC) */
+  PIOD_IRQn            = 14, /**< 14 SAM3X8H Parallel I/O Controller D (PIOD) */
+  PIOE_IRQn            = 15, /**< 15 SAM3X8H Parallel I/O Controller E (PIOE) */
+  PIOF_IRQn            = 16, /**< 16 SAM3X8H Parallel I/O Controller F (PIOF) */
+  USART0_IRQn          = 17, /**< 17 SAM3X8H USART 0 (USART0) */
+  USART1_IRQn          = 18, /**< 18 SAM3X8H USART 1 (USART1) */
+  USART2_IRQn          = 19, /**< 19 SAM3X8H USART 2 (USART2) */
+  USART3_IRQn          = 20, /**< 20 SAM3X8H USART 3 (USART3) */
+  HSMCI_IRQn           = 21, /**< 21 SAM3X8H Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 22, /**< 22 SAM3X8H Two-Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 23, /**< 23 SAM3X8H Two-Wire Interface 1 (TWI1) */
+  SPI0_IRQn            = 24, /**< 24 SAM3X8H Serial Peripheral Interface (SPI0) */
+  SPI1_IRQn            = 25, /**< 25 SAM3X8H Serial Peripheral Interface (SPI1) */
+  SSC_IRQn             = 26, /**< 26 SAM3X8H Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 27, /**< 27 SAM3X8H Timer Counter 0 (TC0) */
+  TC1_IRQn             = 28, /**< 28 SAM3X8H Timer Counter 1 (TC1) */
+  TC2_IRQn             = 29, /**< 29 SAM3X8H Timer Counter 2 (TC2) */
+  TC3_IRQn             = 30, /**< 30 SAM3X8H Timer Counter 3 (TC3) */
+  TC4_IRQn             = 31, /**< 31 SAM3X8H Timer Counter 4 (TC4) */
+  TC5_IRQn             = 32, /**< 32 SAM3X8H Timer Counter 5 (TC5) */
+  TC6_IRQn             = 33, /**< 33 SAM3X8H Timer Counter 6 (TC6) */
+  TC7_IRQn             = 34, /**< 34 SAM3X8H Timer Counter 7 (TC7) */
+  TC8_IRQn             = 35, /**< 35 SAM3X8H Timer Counter 8 (TC8) */
+  PWM_IRQn             = 36, /**< 36 SAM3X8H Pulse Width Modulation Controller (PWM) */
+  ADC_IRQn             = 37, /**< 37 SAM3X8H ADC Controller (ADC) */
+  DACC_IRQn            = 38, /**< 38 SAM3X8H DAC Controller (DACC) */
+  DMAC_IRQn            = 39, /**< 39 SAM3X8H DMA Controller (DMAC) */
+  UOTGHS_IRQn          = 40, /**< 40 SAM3X8H USB OTG High Speed (UOTGHS) */
+  TRNG_IRQn            = 41, /**< 41 SAM3X8H True Random Number Generator (TRNG) */
+  EMAC_IRQn            = 42, /**< 42 SAM3X8H Ethernet MAC (EMAC) */
+  CAN0_IRQn            = 43, /**< 43 SAM3X8H CAN Controller 0 (CAN0) */
+  CAN1_IRQn            = 44, /**< 44 SAM3X8H CAN Controller 1 (CAN1) */
+
+  PERIPH_COUNT_IRQn    = 45  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC0_Handler;   /*  6 Enhanced Flash Controller 0 */
+  void* pfnEFC1_Handler;   /*  7 Enhanced Flash Controller 1 */
+  void* pfnUART_Handler;   /*  8 Universal Asynchronous Receiver Transceiver */
+  void* pfnSMC_Handler;    /*  9 Static Memory Controller */
+  void* pfnSDRAMC_Handler; /* 10 Synchronous Dynamic RAM Controller */
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A, */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnPIOD_Handler;   /* 14 Parallel I/O Controller D */
+  void* pfnPIOE_Handler;   /* 15 Parallel I/O Controller E */
+  void* pfnPIOF_Handler;   /* 16 Parallel I/O Controller F */
+  void* pfnUSART0_Handler; /* 17 USART 0 */
+  void* pfnUSART1_Handler; /* 18 USART 1 */
+  void* pfnUSART2_Handler; /* 19 USART 2 */
+  void* pfnUSART3_Handler; /* 20 USART 3 */
+  void* pfnHSMCI_Handler;  /* 21 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 22 Two-Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 23 Two-Wire Interface 1 */
+  void* pfnSPI0_Handler;   /* 24 Serial Peripheral Interface */
+  void* pfnSPI1_Handler;   /* 25 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 26 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 27 Timer Counter 0 */
+  void* pfnTC1_Handler;    /* 28 Timer Counter 1 */
+  void* pfnTC2_Handler;    /* 29 Timer Counter 2 */
+  void* pfnTC3_Handler;    /* 30 Timer Counter 3 */
+  void* pfnTC4_Handler;    /* 31 Timer Counter 4 */
+  void* pfnTC5_Handler;    /* 32 Timer Counter 5 */
+  void* pfnTC6_Handler;    /* 33 Timer Counter 6 */
+  void* pfnTC7_Handler;    /* 34 Timer Counter 7 */
+  void* pfnTC8_Handler;    /* 35 Timer Counter 8 */
+  void* pfnPWM_Handler;    /* 36 Pulse Width Modulation Controller */
+  void* pfnADC_Handler;    /* 37 ADC Controller */
+  void* pfnDACC_Handler;   /* 38 DAC Controller */
+  void* pfnDMAC_Handler;   /* 39 DMA Controller */
+  void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */
+  void* pfnTRNG_Handler;   /* 41 True Random Number Generator */
+  void* pfnEMAC_Handler;   /* 42 Ethernet MAC */
+  void* pfnCAN0_Handler;   /* 43 CAN Controller 0 */
+  void* pfnCAN1_Handler;   /* 44 CAN Controller 1 */
+} DeviceVectors;
+
+/* Cortex-M3 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ADC_Handler        ( void );
+void CAN0_Handler       ( void );
+void CAN1_Handler       ( void );
+void DACC_Handler       ( void );
+void DMAC_Handler       ( void );
+void EFC0_Handler       ( void );
+void EFC1_Handler       ( void );
+void EMAC_Handler       ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PIOD_Handler       ( void );
+void PIOE_Handler       ( void );
+void PIOF_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SDRAMC_Handler     ( void );
+void SMC_Handler        ( void );
+void SPI0_Handler       ( void );
+void SPI1_Handler       ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TC6_Handler        ( void );
+void TC7_Handler        ( void );
+void TC8_Handler        ( void );
+void TRNG_Handler       ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART_Handler       ( void );
+void UOTGHS_Handler     ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void USART2_Handler     ( void );
+void USART3_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+
+#define __CM3_REV              0x0200 /**< SAM3X8H core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X8H does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X8H uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam3xa.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8H */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8H_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_adc.h"
+#include "component/component_can.h"
+#include "component/component_chipid.h"
+#include "component/component_dacc.h"
+#include "component/component_dmac.h"
+#include "component/component_efc.h"
+#include "component/component_emac.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_sdramc.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_trng.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_uotghs.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8H_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi0.h"
+#include "instance/instance_spi1.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_tc2.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_usart2.h"
+#include "instance/instance_usart3.h"
+#include "instance/instance_uotghs.h"
+#include "instance/instance_emac.h"
+#include "instance/instance_can0.h"
+#include "instance/instance_can1.h"
+#include "instance/instance_trng.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dmac.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_sdramc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_efc0.h"
+#include "instance/instance_efc1.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_piod.h"
+#include "instance/instance_pioe.h"
+#include "instance/instance_piof.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8H_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC0   ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */
+#define ID_EFC1   ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */
+#define ID_UART   ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */
+#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
+#define ID_SDRAMC (10) /**< \brief Synchronous Dynamic RAM Controller (SDRAMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A, (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_PIOD   (14) /**< \brief Parallel I/O Controller D (PIOD) */
+#define ID_PIOE   (15) /**< \brief Parallel I/O Controller E (PIOE) */
+#define ID_PIOF   (16) /**< \brief Parallel I/O Controller F (PIOF) */
+#define ID_USART0 (17) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (18) /**< \brief USART 1 (USART1) */
+#define ID_USART2 (19) /**< \brief USART 2 (USART2) */
+#define ID_USART3 (20) /**< \brief USART 3 (USART3) */
+#define ID_HSMCI  (21) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (22) /**< \brief Two-Wire Interface 0 (TWI0) */
+#define ID_TWI1   (23) /**< \brief Two-Wire Interface 1 (TWI1) */
+#define ID_SPI0   (24) /**< \brief Serial Peripheral Interface (SPI0) */
+#define ID_SPI1   (25) /**< \brief Serial Peripheral Interface (SPI1) */
+#define ID_SSC    (26) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (27) /**< \brief Timer Counter 0 (TC0) */
+#define ID_TC1    (28) /**< \brief Timer Counter 1 (TC1) */
+#define ID_TC2    (29) /**< \brief Timer Counter 2 (TC2) */
+#define ID_TC3    (30) /**< \brief Timer Counter 3 (TC3) */
+#define ID_TC4    (31) /**< \brief Timer Counter 4 (TC4) */
+#define ID_TC5    (32) /**< \brief Timer Counter 5 (TC5) */
+#define ID_TC6    (33) /**< \brief Timer Counter 6 (TC6) */
+#define ID_TC7    (34) /**< \brief Timer Counter 7 (TC7) */
+#define ID_TC8    (35) /**< \brief Timer Counter 8 (TC8) */
+#define ID_PWM    (36) /**< \brief Pulse Width Modulation Controller (PWM) */
+#define ID_ADC    (37) /**< \brief ADC Controller (ADC) */
+#define ID_DACC   (38) /**< \brief DAC Controller (DACC) */
+#define ID_DMAC   (39) /**< \brief DMA Controller (DMAC) */
+#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */
+#define ID_TRNG   (41) /**< \brief True Random Number Generator (TRNG) */
+#define ID_EMAC   (42) /**< \brief Ethernet MAC (EMAC) */
+#define ID_CAN0   (43) /**< \brief CAN Controller 0 (CAN0) */
+#define ID_CAN1   (44) /**< \brief CAN Controller 1 (CAN1) */
+
+#define ID_PERIPH_COUNT (45) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8H_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       (0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define SPI1       (0x4000C000U) /**< \brief (SPI1      ) Base Address */
+#define TC0        (0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TC2        (0x40088000U) /**< \brief (TC2       ) Base Address */
+#define TWI0       (0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     (0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     (0x400A4000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */
+#define UOTGHS     (0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       (0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       (0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       (0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       (0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        (0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       (0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       (0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define SDRAMC     (0x400E0200U) /**< \brief (SDRAMC    ) Base Address */
+#define MATRIX     (0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       (0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   (0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     (0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       (0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       (0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define PIOD       (0x400E1400U) /**< \brief (PIOD      ) Base Address */
+#define PIOE       (0x400E1600U) /**< \brief (PIOE      ) Base Address */
+#define PIOF       (0x400E1800U) /**< \brief (PIOF      ) Base Address */
+#define RSTC       (0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define SPI0       ((Spi    *)0x40008000U) /**< \brief (SPI0      ) Base Address */
+#define SPI1       ((Spi    *)0x4000C000U) /**< \brief (SPI1      ) Base Address */
+#define TC0        ((Tc     *)0x40080000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40084000U) /**< \brief (TC1       ) Base Address */
+#define TC2        ((Tc     *)0x40088000U) /**< \brief (TC2       ) Base Address */
+#define TWI0       ((Twi    *)0x4008C000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x4008C100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x40090000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x40090100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40094000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40094100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40098000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40098100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x4009C000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */
+#define USART2     ((Usart  *)0x400A0000U) /**< \brief (USART2    ) Base Address */
+#define PDC_USART2 ((Pdc    *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */
+#define USART3     ((Usart  *)0x400A4000U) /**< \brief (USART3    ) Base Address */
+#define PDC_USART3 ((Pdc    *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */
+#define UOTGHS     ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS    ) Base Address */
+#define EMAC       ((Emac   *)0x400B0000U) /**< \brief (EMAC      ) Base Address */
+#define CAN0       ((Can    *)0x400B4000U) /**< \brief (CAN0      ) Base Address */
+#define CAN1       ((Can    *)0x400B8000U) /**< \brief (CAN1      ) Base Address */
+#define TRNG       ((Trng   *)0x400BC000U) /**< \brief (TRNG      ) Base Address */
+#define ADC        ((Adc    *)0x400C0000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x400C0100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DMAC       ((Dmac   *)0x400C4000U) /**< \brief (DMAC      ) Base Address */
+#define DACC       ((Dacc   *)0x400C8000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x400C8100U) /**< \brief (PDC_DACC  ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define SDRAMC     ((Sdramc *)0x400E0200U) /**< \brief (SDRAMC    ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0400U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0600U) /**< \brief (PMC       ) Base Address */
+#define UART       ((Uart   *)0x400E0800U) /**< \brief (UART      ) Base Address */
+#define PDC_UART   ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART  ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0940U) /**< \brief (CHIPID    ) Base Address */
+#define EFC0       ((Efc    *)0x400E0A00U) /**< \brief (EFC0      ) Base Address */
+#define EFC1       ((Efc    *)0x400E0C00U) /**< \brief (EFC1      ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define PIOD       ((Pio    *)0x400E1400U) /**< \brief (PIOD      ) Base Address */
+#define PIOE       ((Pio    *)0x400E1600U) /**< \brief (PIOE      ) Base Address */
+#define PIOF       ((Pio    *)0x400E1800U) /**< \brief (PIOF      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1A00U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1A10U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1A30U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1A50U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1A60U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1A90U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+/** \addtogroup SAM3X8H_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam3x8h.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IRAM0_SIZE               (0x10000u)
+#define IRAM1_SIZE               (0x8000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE+IFLASH1_SIZE)
+#define IRAM_SIZE                (IRAM0_SIZE+IRAM1_SIZE)
+
+#define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
+#if defined IFLASH0_SIZE
+#define IFLASH1_ADDR    (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
+#endif
+#define IROM_ADDR       (0x00100000u) /**< Internal ROM base address */
+#define IRAM0_ADDR      (0x20000000u) /**< Internal RAM 0 base address */
+#define IRAM1_ADDR      (0x20080000u) /**< Internal RAM 1 base address */
+#define NFC_RAM_ADDR    (0x20100000u) /**< NAND Flash Controller RAM base address */
+#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */
+#define EBI_CS0_ADDR    (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR    (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR    (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR    (0x63000000u) /**< EBI Chip Select 3 base address */
+#define EBI_CS4_ADDR    (0x64000000u) /**< EBI Chip Select 4 base address */
+#define EBI_CS5_ADDR    (0x65000000u) /**< EBI Chip Select 5 base address */
+#define EBI_CS6_ADDR    (0x66000000u) /**< EBI Chip Select 6 base address */
+#define EBI_CS7_ADDR    (0x67000000u) /**< EBI Chip Select 7 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM3X8H */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (84000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (22500000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (34000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (53000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (78000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM3X8H_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3xa.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3xa.h
new file mode 100644
index 0000000..375752b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/sam3xa.h
@@ -0,0 +1,51 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM3XA_
+#define _SAM3XA_
+
+#if defined __SAM3A4C__
+  #include "sam3a4c.h"
+#elif defined __SAM3A8C__
+  #include "sam3a8c.h"
+#elif defined __SAM3X4C__
+  #include "sam3x4c.h"
+#elif defined __SAM3X4E__
+  #include "sam3x4e.h"
+#elif defined __SAM3X8C__
+  #include "sam3x8c.h"
+#elif defined __SAM3X8E__
+  #include "sam3x8e.h"
+#elif defined __SAM3X8H__
+  #include "sam3x8h.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAM3XA_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/system_sam3xa.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/system_sam3xa.h
new file mode 100644
index 0000000..504024e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/include/system_sam3xa.h
@@ -0,0 +1,58 @@
+/*! \file *********************************************************************
+ *
+ * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
+ *           for SAM3 devices.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef SYSTEM_SAM3X_H_INCLUDED
+#define SYSTEM_SAM3X_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#include 
+
+extern uint32_t SystemCoreClock;	/* System Clock Frequency (Core Clock) */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock with current core Clock 
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+/** 
+ * Initialize flash.
+ */
+void system_init_flash(uint32_t dw_clk);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* SYSTEM_SAM3X_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a4_flash.ld
new file mode 100644
index 0000000..bda7ede
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a4_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a4_sram.ld
new file mode 100644
index 0000000..bfc2e10
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a4_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a4c_flash.ld
new file mode 100644
index 0000000..5a9c8da
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a4c_sram.ld
new file mode 100644
index 0000000..441f66c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a8_flash.ld
new file mode 100644
index 0000000..8508410
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a8_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a8_sram.ld
new file mode 100644
index 0000000..59fff23
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a8_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a8c_flash.ld
new file mode 100644
index 0000000..cdcd211
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a8c_sram.ld
new file mode 100644
index 0000000..25ab29b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3a_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4_flash.ld
new file mode 100644
index 0000000..ad161d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4_sram.ld
new file mode 100644
index 0000000..280533f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4c_flash.ld
new file mode 100644
index 0000000..5ec8086
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4c_sram.ld
new file mode 100644
index 0000000..380ced7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4e_flash.ld
new file mode 100644
index 0000000..5ec8086
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4e_sram.ld
new file mode 100644
index 0000000..380ced7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x4e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8_flash.ld
new file mode 100644
index 0000000..e42ee75
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8_sram.ld
new file mode 100644
index 0000000..644dd8a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8c_flash.ld
new file mode 100644
index 0000000..12a1c58
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8c_sram.ld
new file mode 100644
index 0000000..41c492f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8e_flash.ld
new file mode 100644
index 0000000..12a1c58
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8e_sram.ld
new file mode 100644
index 0000000..41c492f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8h_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8h_flash.ld
new file mode 100644
index 0000000..12a1c58
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8h_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8h_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8h_sram.ld
new file mode 100644
index 0000000..41c492f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x8h_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/sam3x_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/startup_sam3xa.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/startup_sam3xa.c
new file mode 100644
index 0000000..55e9e8b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/as_gcc/startup_sam3xa.c
@@ -0,0 +1,292 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3xa.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_SMC_INSTANCE_ */
+#ifdef _SAM3XA_SDRAMC_INSTANCE_
+void SDRAMC_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_PIOC_INSTANCE_ */
+#ifdef _SAM3XA_PIOD_INSTANCE_
+void PIOD_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_PIOD_INSTANCE_ */
+#ifdef _SAM3XA_PIOE_INSTANCE_
+void PIOE_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_PIOE_INSTANCE_ */
+#ifdef _SAM3XA_PIOF_INSTANCE_
+void PIOF_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_PIOF_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART2_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_USART3_INSTANCE_
+void USART3_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_USART3_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_SPI1_INSTANCE_
+void SPI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_SPI1_INSTANCE_ */
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_TC2_INSTANCE_
+void TC6_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC7_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC8_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_TC2_INSTANCE_ */
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UOTGHS_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_EMAC_INSTANCE_
+void EMAC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_EMAC_INSTANCE_ */
+void CAN0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CAN1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /*  0  Supply Controller */
+	(void*) RSTC_Handler,    /*  1  Reset Controller */
+	(void*) RTC_Handler,     /*  2  Real Time Clock */
+	(void*) RTT_Handler,     /*  3  Real Time Timer */
+	(void*) WDT_Handler,     /*  4  Watchdog Timer */
+	(void*) PMC_Handler,     /*  5  PMC */
+	(void*) EFC0_Handler,    /*  6  EFC 0 */
+	(void*) EFC1_Handler,    /*  7  EFC 1 */
+	(void*) UART_Handler,    /*  8  UART */
+#ifdef _SAM3XA_SMC_INSTANCE_
+	(void*) SMC_Handler,     /*  9  SMC */
+#else
+	(void*) (0UL),           /*  9 Reserved */
+#endif /* _SAM3XA_SMC_INSTANCE_ */
+#ifdef _SAM3XA_SDRAMC_INSTANCE_
+	(void*) SDRAMC_Handler,  /* 10  SDRAMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3XA_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3XA_PIOC_INSTANCE_ */
+#ifdef _SAM3XA_PIOD_INSTANCE_
+	(void*) PIOD_Handler,    /* 14 Parallel IO Controller D */
+#else
+	(void*) (0UL),           /* 14 Reserved */
+#endif /* _SAM3XA_PIOD_INSTANCE_ */
+#ifdef _SAM3XA_PIOE_INSTANCE_
+	(void*) PIOE_Handler,    /* 15 Parallel IO Controller E */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3XA_PIOE_INSTANCE_ */
+#ifdef _SAM3XA_PIOF_INSTANCE_
+	(void*) PIOF_Handler,    /* 16 Parallel IO Controller F */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3XA_PIOF_INSTANCE_ */
+	(void*) USART0_Handler,  /* 17 USART 0 */
+	(void*) USART1_Handler,  /* 18 USART 1 */
+	(void*) USART2_Handler,  /* 19 USART 2 */
+#ifdef _SAM3XA_USART3_INSTANCE_
+	(void*) USART3_Handler,  /* 20 USART 3 */
+#else
+	(void*) (0UL),           /* 20 Reserved */
+#endif /* _SAM3XA_USART3_INSTANCE_ */
+	(void*) HSMCI_Handler,   /* 21 MCI */
+	(void*) TWI0_Handler,    /* 22 TWI 0 */
+	(void*) TWI1_Handler,    /* 23 TWI 1 */
+	(void*) SPI0_Handler,    /* 24 SPI 0 */
+#ifdef _SAM3XA_SPI1_INSTANCE_
+	(void*) SPI1_Handler,    /* 25 SPI 1 */
+#else
+	(void*) (0UL),           /* 25 Reserved */
+#endif /* _SAM3XA_SPI1_INSTANCE_ */
+	(void*) SSC_Handler,     /* 26 SSC */
+	(void*) TC0_Handler,     /* 27 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 28 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 29 Timer Counter 2 */
+	(void*) TC3_Handler,     /* 30 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 31 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 32 Timer Counter 5 */
+#ifdef _SAM3XA_TC2_INSTANCE_
+	(void*) TC6_Handler,     /* 33 Timer Counter 6 */
+	(void*) TC7_Handler,     /* 34 Timer Counter 7 */
+	(void*) TC8_Handler,     /* 35 Timer Counter 8 */
+#else
+	(void*) (0UL),           /* 33 Reserved */
+	(void*) (0UL),           /* 34 Reserved */
+	(void*) (0UL),           /* 35 Reserved */
+#endif /* _SAM3XA_TC2_INSTANCE_ */
+	(void*) PWM_Handler,     /* 36 PWM */
+	(void*) ADC_Handler,     /* 37 ADC controller */
+	(void*) DACC_Handler,    /* 38 DAC controller */
+	(void*) DMAC_Handler,    /* 39 DMA Controller */
+	(void*) UOTGHS_Handler,  /* 40 USB OTG High Speed */
+	(void*) TRNG_Handler,    /* 41 True Random Number Generator */
+#ifdef _SAM3XA_EMAC_INSTANCE_
+	(void*) EMAC_Handler,    /* 42 Ethernet MAC */
+#else
+	(void*) (0UL),           /* 42 Reserved */
+#endif /* _SAM3XA_EMAC_INSTANCE_ */
+	(void*) CAN0_Handler,    /* 43 CAN Controller 0 */
+	(void*) CAN1_Handler    /* 44 CAN Controller 1 */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < NFC_RAM_ADDR)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a4_flash.ld
new file mode 100644
index 0000000..bda7ede
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a4_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a4_sram.ld
new file mode 100644
index 0000000..bfc2e10
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a4_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a4c_flash.ld
new file mode 100644
index 0000000..5a9c8da
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a4c_sram.ld
new file mode 100644
index 0000000..441f66c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a8_flash.ld
new file mode 100644
index 0000000..8508410
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a8_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a8_sram.ld
new file mode 100644
index 0000000..59fff23
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a8_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a8c_flash.ld
new file mode 100644
index 0000000..cdcd211
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a8c_sram.ld
new file mode 100644
index 0000000..25ab29b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3a_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4_flash.ld
new file mode 100644
index 0000000..ad161d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4_sram.ld
new file mode 100644
index 0000000..280533f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4c_flash.ld
new file mode 100644
index 0000000..5ec8086
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4c_sram.ld
new file mode 100644
index 0000000..380ced7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4e_flash.ld
new file mode 100644
index 0000000..5ec8086
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4e_sram.ld
new file mode 100644
index 0000000..380ced7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x4e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8_flash.ld
new file mode 100644
index 0000000..e42ee75
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8_sram.ld
new file mode 100644
index 0000000..644dd8a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8c_flash.ld
new file mode 100644
index 0000000..12a1c58
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8c_sram.ld
new file mode 100644
index 0000000..41c492f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8e_flash.ld
new file mode 100644
index 0000000..12a1c58
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8e_sram.ld
new file mode 100644
index 0000000..41c492f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8h_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8h_flash.ld
new file mode 100644
index 0000000..12a1c58
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8h_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8h_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8h_sram.ld
new file mode 100644
index 0000000..41c492f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x8h_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/sam3x_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/startup_sam3xa.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/startup_sam3xa.c
new file mode 100644
index 0000000..698df1d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc/startup_sam3xa.c
@@ -0,0 +1,206 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3xa.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+// Arduino: we must setup hardware before doing this
+// void __libc_init_array(void);
+
+// Arduino: handlers weak symbols moved into main
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /*  0  Supply Controller */
+	(void*) RSTC_Handler,    /*  1  Reset Controller */
+	(void*) RTC_Handler,     /*  2  Real Time Clock */
+	(void*) RTT_Handler,     /*  3  Real Time Timer */
+	(void*) WDT_Handler,     /*  4  Watchdog Timer */
+	(void*) PMC_Handler,     /*  5  PMC */
+	(void*) EFC0_Handler,    /*  6  EFC 0 */
+	(void*) EFC1_Handler,    /*  7  EFC 1 */
+	(void*) UART_Handler,    /*  8  UART */
+#ifdef _SAM3XA_SMC_INSTANCE_
+	(void*) SMC_Handler,     /*  9  SMC */
+#else
+	(void*) (0UL),           /*  9 Reserved */
+#endif /* _SAM3XA_SMC_INSTANCE_ */
+#ifdef _SAM3XA_SDRAMC_INSTANCE_
+	(void*) SDRAMC_Handler,  /* 10  SDRAMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3XA_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3XA_PIOC_INSTANCE_ */
+#ifdef _SAM3XA_PIOD_INSTANCE_
+	(void*) PIOD_Handler,    /* 14 Parallel IO Controller D */
+#else
+	(void*) (0UL),           /* 14 Reserved */
+#endif /* _SAM3XA_PIOD_INSTANCE_ */
+#ifdef _SAM3XA_PIOE_INSTANCE_
+	(void*) PIOE_Handler,    /* 15 Parallel IO Controller E */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3XA_PIOE_INSTANCE_ */
+#ifdef _SAM3XA_PIOF_INSTANCE_
+	(void*) PIOF_Handler,    /* 16 Parallel IO Controller F */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3XA_PIOF_INSTANCE_ */
+	(void*) USART0_Handler,  /* 17 USART 0 */
+	(void*) USART1_Handler,  /* 18 USART 1 */
+	(void*) USART2_Handler,  /* 19 USART 2 */
+#ifdef _SAM3XA_USART3_INSTANCE_
+	(void*) USART3_Handler,  /* 20 USART 3 */
+#else
+	(void*) (0UL),           /* 20 Reserved */
+#endif /* _SAM3XA_USART3_INSTANCE_ */
+	(void*) HSMCI_Handler,   /* 21 MCI */
+	(void*) TWI0_Handler,    /* 22 TWI 0 */
+	(void*) TWI1_Handler,    /* 23 TWI 1 */
+	(void*) SPI0_Handler,    /* 24 SPI 0 */
+#ifdef _SAM3XA_SPI1_INSTANCE_
+	(void*) SPI1_Handler,    /* 25 SPI 1 */
+#else
+	(void*) (0UL),           /* 25 Reserved */
+#endif /* _SAM3XA_SPI1_INSTANCE_ */
+	(void*) SSC_Handler,     /* 26 SSC */
+	(void*) TC0_Handler,     /* 27 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 28 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 29 Timer Counter 2 */
+	(void*) TC3_Handler,     /* 30 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 31 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 32 Timer Counter 5 */
+#ifdef _SAM3XA_TC2_INSTANCE_
+	(void*) TC6_Handler,     /* 33 Timer Counter 6 */
+	(void*) TC7_Handler,     /* 34 Timer Counter 7 */
+	(void*) TC8_Handler,     /* 35 Timer Counter 8 */
+#else
+	(void*) (0UL),           /* 33 Reserved */
+	(void*) (0UL),           /* 34 Reserved */
+	(void*) (0UL),           /* 35 Reserved */
+#endif /* _SAM3XA_TC2_INSTANCE_ */
+	(void*) PWM_Handler,     /* 36 PWM */
+	(void*) ADC_Handler,     /* 37 ADC controller */
+	(void*) DACC_Handler,    /* 38 DAC controller */
+	(void*) DMAC_Handler,    /* 39 DMA Controller */
+	(void*) UOTGHS_Handler,  /* 40 USB OTG High Speed */
+	(void*) TRNG_Handler,    /* 41 True Random Number Generator */
+#ifdef _SAM3XA_EMAC_INSTANCE_
+	(void*) EMAC_Handler,    /* 42 Ethernet MAC */
+#else
+	(void*) (0UL),           /* 42 Reserved */
+#endif /* _SAM3XA_EMAC_INSTANCE_ */
+	(void*) CAN0_Handler,    /* 43 CAN Controller 0 */
+	(void*) CAN1_Handler    /* 44 CAN Controller 1 */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < NFC_RAM_ADDR)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+
+	// Arduino: we must setup hardware before doing this
+	//__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a4_flash.ld
new file mode 100644
index 0000000..bda7ede
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a4_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a4_sram.ld
new file mode 100644
index 0000000..bfc2e10
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a4_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a4c_flash.ld
new file mode 100644
index 0000000..5a9c8da
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a4c_sram.ld
new file mode 100644
index 0000000..441f66c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a8_flash.ld
new file mode 100644
index 0000000..8508410
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a8_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a8_sram.ld
new file mode 100644
index 0000000..59fff23
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a8_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a8c_flash.ld
new file mode 100644
index 0000000..cdcd211
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a8c_sram.ld
new file mode 100644
index 0000000..25ab29b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3a_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4_flash.ld
new file mode 100644
index 0000000..ad161d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4_sram.ld
new file mode 100644
index 0000000..280533f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4c_flash.ld
new file mode 100644
index 0000000..5ec8086
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4c_sram.ld
new file mode 100644
index 0000000..380ced7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4e_flash.ld
new file mode 100644
index 0000000..5ec8086
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4e_sram.ld
new file mode 100644
index 0000000..380ced7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x4e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8_flash.ld
new file mode 100644
index 0000000..e42ee75
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8_sram.ld
new file mode 100644
index 0000000..644dd8a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8c_flash.ld
new file mode 100644
index 0000000..12a1c58
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8c_sram.ld
new file mode 100644
index 0000000..41c492f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8e_flash.ld
new file mode 100644
index 0000000..12a1c58
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8e_sram.ld
new file mode 100644
index 0000000..41c492f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8h_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8h_flash.ld
new file mode 100644
index 0000000..12a1c58
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8h_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8h_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8h_sram.ld
new file mode 100644
index 0000000..41c492f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x8h_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/sam3x_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/startup_sam3xa.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/startup_sam3xa.c
new file mode 100644
index 0000000..d4690a7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_arm/startup_sam3xa.c
@@ -0,0 +1,292 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3xa.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_SMC_INSTANCE_ */
+#ifdef _SAM3XA_SDRAMC_INSTANCE_
+void SDRAMC_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_PIOC_INSTANCE_ */
+#ifdef _SAM3XA_PIOD_INSTANCE_
+void PIOD_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_PIOD_INSTANCE_ */
+#ifdef _SAM3XA_PIOE_INSTANCE_
+void PIOE_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_PIOE_INSTANCE_ */
+#ifdef _SAM3XA_PIOF_INSTANCE_
+void PIOF_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_PIOF_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART2_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_USART3_INSTANCE_
+void USART3_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_USART3_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_SPI1_INSTANCE_
+void SPI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_SPI1_INSTANCE_ */
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_TC2_INSTANCE_
+void TC6_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC7_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC8_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_TC2_INSTANCE_ */
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UOTGHS_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_EMAC_INSTANCE_
+void EMAC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_EMAC_INSTANCE_ */
+void CAN0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CAN1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /*  0  Supply Controller */
+	(void*) RSTC_Handler,    /*  1  Reset Controller */
+	(void*) RTC_Handler,     /*  2  Real Time Clock */
+	(void*) RTT_Handler,     /*  3  Real Time Timer */
+	(void*) WDT_Handler,     /*  4  Watchdog Timer */
+	(void*) PMC_Handler,     /*  5  PMC */
+	(void*) EFC0_Handler,    /*  6  EFC 0 */
+	(void*) EFC1_Handler,    /*  7  EFC 1 */
+	(void*) UART_Handler,    /*  8  UART */
+#ifdef _SAM3XA_SMC_INSTANCE_
+	(void*) SMC_Handler,     /*  9  SMC */
+#else
+	(void*) (0UL),           /*  9 Reserved */
+#endif /* _SAM3XA_SMC_INSTANCE_ */
+#ifdef _SAM3XA_SDRAMC_INSTANCE_
+	(void*) SDRAMC_Handler,  /* 10  SDRAMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3XA_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3XA_PIOC_INSTANCE_ */
+#ifdef _SAM3XA_PIOD_INSTANCE_
+	(void*) PIOD_Handler,    /* 14 Parallel IO Controller D */
+#else
+	(void*) (0UL),           /* 14 Reserved */
+#endif /* _SAM3XA_PIOD_INSTANCE_ */
+#ifdef _SAM3XA_PIOE_INSTANCE_
+	(void*) PIOE_Handler,    /* 15 Parallel IO Controller E */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3XA_PIOE_INSTANCE_ */
+#ifdef _SAM3XA_PIOF_INSTANCE_
+	(void*) PIOF_Handler,    /* 16 Parallel IO Controller F */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3XA_PIOF_INSTANCE_ */
+	(void*) USART0_Handler,  /* 17 USART 0 */
+	(void*) USART1_Handler,  /* 18 USART 1 */
+	(void*) USART2_Handler,  /* 19 USART 2 */
+#ifdef _SAM3XA_USART3_INSTANCE_
+	(void*) USART3_Handler,  /* 20 USART 3 */
+#else
+	(void*) (0UL),           /* 20 Reserved */
+#endif /* _SAM3XA_USART3_INSTANCE_ */
+	(void*) HSMCI_Handler,   /* 21 MCI */
+	(void*) TWI0_Handler,    /* 22 TWI 0 */
+	(void*) TWI1_Handler,    /* 23 TWI 1 */
+	(void*) SPI0_Handler,    /* 24 SPI 0 */
+#ifdef _SAM3XA_SPI1_INSTANCE_
+	(void*) SPI1_Handler,    /* 25 SPI 1 */
+#else
+	(void*) (0UL),           /* 25 Reserved */
+#endif /* _SAM3XA_SPI1_INSTANCE_ */
+	(void*) SSC_Handler,     /* 26 SSC */
+	(void*) TC0_Handler,     /* 27 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 28 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 29 Timer Counter 2 */
+	(void*) TC3_Handler,     /* 30 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 31 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 32 Timer Counter 5 */
+#ifdef _SAM3XA_TC2_INSTANCE_
+	(void*) TC6_Handler,     /* 33 Timer Counter 6 */
+	(void*) TC7_Handler,     /* 34 Timer Counter 7 */
+	(void*) TC8_Handler,     /* 35 Timer Counter 8 */
+#else
+	(void*) (0UL),           /* 33 Reserved */
+	(void*) (0UL),           /* 34 Reserved */
+	(void*) (0UL),           /* 35 Reserved */
+#endif /* _SAM3XA_TC2_INSTANCE_ */
+	(void*) PWM_Handler,     /* 36 PWM */
+	(void*) ADC_Handler,     /* 37 ADC controller */
+	(void*) DACC_Handler,    /* 38 DAC controller */
+	(void*) DMAC_Handler,    /* 39 DMA Controller */
+	(void*) UOTGHS_Handler,  /* 40 USB OTG High Speed */
+	(void*) TRNG_Handler,    /* 41 True Random Number Generator */
+#ifdef _SAM3XA_EMAC_INSTANCE_
+	(void*) EMAC_Handler,    /* 42 Ethernet MAC */
+#else
+	(void*) (0UL),           /* 42 Reserved */
+#endif /* _SAM3XA_EMAC_INSTANCE_ */
+	(void*) CAN0_Handler,    /* 43 CAN Controller 0 */
+	(void*) CAN1_Handler     /* 44 CAN Controller 1 */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < NFC_RAM_ADDR)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a4_flash.ld
new file mode 100644
index 0000000..bda7ede
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a4_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a4_sram.ld
new file mode 100644
index 0000000..bfc2e10
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a4_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a4c_flash.ld
new file mode 100644
index 0000000..5a9c8da
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a4c_sram.ld
new file mode 100644
index 0000000..441f66c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a8_flash.ld
new file mode 100644
index 0000000..8508410
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a8_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a8_sram.ld
new file mode 100644
index 0000000..59fff23
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a8_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3a_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a8c_flash.ld
new file mode 100644
index 0000000..cdcd211
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a8c_sram.ld
new file mode 100644
index 0000000..25ab29b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3a8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3a_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4_flash.ld
new file mode 100644
index 0000000..ad161d2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4_sram.ld
new file mode 100644
index 0000000..280533f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* sram0, 32K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20078000, LENGTH = 0x00010000 /* sram, 64K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4c_flash.ld
new file mode 100644
index 0000000..5ec8086
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4c_sram.ld
new file mode 100644
index 0000000..380ced7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4e_flash.ld
new file mode 100644
index 0000000..5ec8086
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4e_sram.ld
new file mode 100644
index 0000000..380ced7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x4e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x4_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8_flash.ld
new file mode 100644
index 0000000..e42ee75
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8_flash.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8_sram.ld
new file mode 100644
index 0000000..644dd8a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8_sram.ld
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+INCLUDE sam3x_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8c_flash.ld
new file mode 100644
index 0000000..12a1c58
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8c_sram.ld
new file mode 100644
index 0000000..41c492f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8e_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8e_flash.ld
new file mode 100644
index 0000000..12a1c58
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8e_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8e_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8e_sram.ld
new file mode 100644
index 0000000..41c492f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8e_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8h_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8h_flash.ld
new file mode 100644
index 0000000..12a1c58
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8h_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8h_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8h_sram.ld
new file mode 100644
index 0000000..41c492f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x8h_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam3x8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/sam3x_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/startup_sam3xa.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/startup_sam3xa.c
new file mode 100644
index 0000000..d4690a7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/gcc_atmel/startup_sam3xa.c
@@ -0,0 +1,292 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3xa.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_SMC_INSTANCE_ */
+#ifdef _SAM3XA_SDRAMC_INSTANCE_
+void SDRAMC_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_PIOC_INSTANCE_ */
+#ifdef _SAM3XA_PIOD_INSTANCE_
+void PIOD_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_PIOD_INSTANCE_ */
+#ifdef _SAM3XA_PIOE_INSTANCE_
+void PIOE_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_PIOE_INSTANCE_ */
+#ifdef _SAM3XA_PIOF_INSTANCE_
+void PIOF_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_PIOF_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void USART2_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_USART3_INSTANCE_
+void USART3_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_USART3_INSTANCE_ */
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_SPI1_INSTANCE_
+void SPI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_SPI1_INSTANCE_ */
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_TC2_INSTANCE_
+void TC6_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC7_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC8_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_TC2_INSTANCE_ */
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UOTGHS_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TRNG_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM3XA_EMAC_INSTANCE_
+void EMAC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM3XA_EMAC_INSTANCE_ */
+void CAN0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CAN1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /*  0  Supply Controller */
+	(void*) RSTC_Handler,    /*  1  Reset Controller */
+	(void*) RTC_Handler,     /*  2  Real Time Clock */
+	(void*) RTT_Handler,     /*  3  Real Time Timer */
+	(void*) WDT_Handler,     /*  4  Watchdog Timer */
+	(void*) PMC_Handler,     /*  5  PMC */
+	(void*) EFC0_Handler,    /*  6  EFC 0 */
+	(void*) EFC1_Handler,    /*  7  EFC 1 */
+	(void*) UART_Handler,    /*  8  UART */
+#ifdef _SAM3XA_SMC_INSTANCE_
+	(void*) SMC_Handler,     /*  9  SMC */
+#else
+	(void*) (0UL),           /*  9 Reserved */
+#endif /* _SAM3XA_SMC_INSTANCE_ */
+#ifdef _SAM3XA_SDRAMC_INSTANCE_
+	(void*) SDRAMC_Handler,  /* 10  SDRAMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3XA_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3XA_PIOC_INSTANCE_ */
+#ifdef _SAM3XA_PIOD_INSTANCE_
+	(void*) PIOD_Handler,    /* 14 Parallel IO Controller D */
+#else
+	(void*) (0UL),           /* 14 Reserved */
+#endif /* _SAM3XA_PIOD_INSTANCE_ */
+#ifdef _SAM3XA_PIOE_INSTANCE_
+	(void*) PIOE_Handler,    /* 15 Parallel IO Controller E */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3XA_PIOE_INSTANCE_ */
+#ifdef _SAM3XA_PIOF_INSTANCE_
+	(void*) PIOF_Handler,    /* 16 Parallel IO Controller F */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3XA_PIOF_INSTANCE_ */
+	(void*) USART0_Handler,  /* 17 USART 0 */
+	(void*) USART1_Handler,  /* 18 USART 1 */
+	(void*) USART2_Handler,  /* 19 USART 2 */
+#ifdef _SAM3XA_USART3_INSTANCE_
+	(void*) USART3_Handler,  /* 20 USART 3 */
+#else
+	(void*) (0UL),           /* 20 Reserved */
+#endif /* _SAM3XA_USART3_INSTANCE_ */
+	(void*) HSMCI_Handler,   /* 21 MCI */
+	(void*) TWI0_Handler,    /* 22 TWI 0 */
+	(void*) TWI1_Handler,    /* 23 TWI 1 */
+	(void*) SPI0_Handler,    /* 24 SPI 0 */
+#ifdef _SAM3XA_SPI1_INSTANCE_
+	(void*) SPI1_Handler,    /* 25 SPI 1 */
+#else
+	(void*) (0UL),           /* 25 Reserved */
+#endif /* _SAM3XA_SPI1_INSTANCE_ */
+	(void*) SSC_Handler,     /* 26 SSC */
+	(void*) TC0_Handler,     /* 27 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 28 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 29 Timer Counter 2 */
+	(void*) TC3_Handler,     /* 30 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 31 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 32 Timer Counter 5 */
+#ifdef _SAM3XA_TC2_INSTANCE_
+	(void*) TC6_Handler,     /* 33 Timer Counter 6 */
+	(void*) TC7_Handler,     /* 34 Timer Counter 7 */
+	(void*) TC8_Handler,     /* 35 Timer Counter 8 */
+#else
+	(void*) (0UL),           /* 33 Reserved */
+	(void*) (0UL),           /* 34 Reserved */
+	(void*) (0UL),           /* 35 Reserved */
+#endif /* _SAM3XA_TC2_INSTANCE_ */
+	(void*) PWM_Handler,     /* 36 PWM */
+	(void*) ADC_Handler,     /* 37 ADC controller */
+	(void*) DACC_Handler,    /* 38 DAC controller */
+	(void*) DMAC_Handler,    /* 39 DMA Controller */
+	(void*) UOTGHS_Handler,  /* 40 USB OTG High Speed */
+	(void*) TRNG_Handler,    /* 41 True Random Number Generator */
+#ifdef _SAM3XA_EMAC_INSTANCE_
+	(void*) EMAC_Handler,    /* 42 Ethernet MAC */
+#else
+	(void*) (0UL),           /* 42 Reserved */
+#endif /* _SAM3XA_EMAC_INSTANCE_ */
+	(void*) CAN0_Handler,    /* 43 CAN Controller 0 */
+	(void*) CAN1_Handler     /* 44 CAN Controller 1 */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < NFC_RAM_ADDR)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3a4_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3a4_flash.icf
new file mode 100644
index 0000000..8cefabb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3a4_flash.icf
@@ -0,0 +1,63 @@
+/*-  SRAM0 memory region -*/
+define symbol __region_RAM0_size__          = 0x8000 ;
+define symbol __region_RAM0_start__         = 0x20000000 ;
+define symbol __region_RAM0_end__           = __region_RAM0_start__+__region_RAM0_size__-1 ;
+
+export symbol __region_RAM0_size__ ;
+export symbol __region_RAM0_start__ ;
+export symbol __region_RAM0_end__ ;
+
+/*-  SRAM1 memory region -*/
+define symbol __region_RAM1_size__          = 0x8000 ;
+define symbol __region_RAM1_start__         = 0x20080000 ;
+define symbol __region_RAM1_end__           = __region_RAM1_start__+__region_RAM1_size__-1 ;
+
+export symbol __region_RAM1_size__ ;
+export symbol __region_RAM1_start__ ;
+export symbol __region_RAM1_end__ ;
+
+/*- Continous SRAM region (SRAM0 is mirrored) -*/
+define symbol __region_RAM_size__           = __region_RAM0_size__+__region_RAM1_size__ ;
+define symbol __region_RAM_start__          = __region_RAM1_start__-__region_RAM0_size__ ;
+define symbol __region_RAM_end__            = __region_RAM1_end__ ;
+
+export symbol __region_RAM_size__ ;
+export symbol __region_RAM_start__ ;
+export symbol __region_RAM_end__ ;
+
+/*- NFC SRAM region -*/
+define symbol __region_NFC_RAM_start__      = 0x20100000 ;
+define symbol __region_NFC_RAM_end__        = 0x20100FFF ;
+
+export symbol __region_NFC_RAM_start__ ;
+export symbol __region_NFC_RAM_end__ ;
+
+/*- Flash region -*/
+define symbol __region_ROM_size__           = 0x00040000 ;
+define symbol __region_ROM_start__          = 0x00080000 ;
+define symbol __region_ROM_end__            = __region_ROM_start__+__region_ROM_size__-1 ;
+
+export symbol __region_ROM_size__ ;
+export symbol __region_ROM_start__ ;
+export symbol __region_ROM_end__ ;
+
+/*-Vector table start*/
+define symbol __vector_start__              = __region_ROM_start__ ;
+
+/*-Sizes-*/
+define symbol __size_cstack__               = 0x2000 ;
+define symbol __size_heap__                 = 0x2000 ;
+
+define memory mem with size                 = 4G ;
+define region RAM_region                    = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region ROM_region                    = mem:[from __region_ROM_start__ to __region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__vector_start__ { readonly section .intvec };
+place in ROM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3a4_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3a4_sram.icf
new file mode 100644
index 0000000..763159a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3a4_sram.icf
@@ -0,0 +1,53 @@
+/*-  SRAM0 memory region -*/
+define symbol __region_RAM0_size__          = 0x8000 ;
+define symbol __region_RAM0_start__         = 0x20000000 ;
+define symbol __region_RAM0_end__           = __region_RAM0_start__+__region_RAM0_size__-1 ;
+
+export symbol __region_RAM0_size__ ;
+export symbol __region_RAM0_start__ ;
+export symbol __region_RAM0_end__ ;
+
+/*-  SRAM1 memory region -*/
+define symbol __region_RAM1_size__          = 0x8000 ;
+define symbol __region_RAM1_start__         = 0x20080000 ;
+define symbol __region_RAM1_end__           = __region_RAM1_start__+__region_RAM1_size__-1 ;
+
+export symbol __region_RAM1_size__ ;
+export symbol __region_RAM1_start__ ;
+export symbol __region_RAM1_end__ ;
+
+/*- Continous SRAM region (SRAM0 is mirrored) -*/
+define symbol __region_RAM_size__           = __region_RAM0_size__+__region_RAM1_size__ ;
+define symbol __region_RAM_start__          = __region_RAM1_start__-__region_RAM0_size__ ;
+define symbol __region_RAM_end__            = __region_RAM1_end__ ;
+
+export symbol __region_RAM_size__ ;
+export symbol __region_RAM_start__ ;
+export symbol __region_RAM_end__ ;
+
+/*- NFC SRAM region -*/
+define symbol __region_NFC_RAM_start__      = 0x20100000 ;
+define symbol __region_NFC_RAM_end__        = 0x20100FFF ;
+
+export symbol __region_NFC_RAM_start__ ;
+export symbol __region_NFC_RAM_end__ ;
+
+/*-Vector table start*/
+define symbol __vector_start__              = __region_RAM_start__ ;
+
+/*-Sizes-*/
+define symbol __size_cstack__               = 0x2000 ;
+define symbol __size_heap__                 = 0x2000 ;
+
+define memory mem with size                 = 4G ;
+define region RAM_region                    = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__vector_start__ { readonly section .intvec };
+place in RAM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3x4_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3x4_flash.icf
new file mode 100644
index 0000000..8cefabb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3x4_flash.icf
@@ -0,0 +1,63 @@
+/*-  SRAM0 memory region -*/
+define symbol __region_RAM0_size__          = 0x8000 ;
+define symbol __region_RAM0_start__         = 0x20000000 ;
+define symbol __region_RAM0_end__           = __region_RAM0_start__+__region_RAM0_size__-1 ;
+
+export symbol __region_RAM0_size__ ;
+export symbol __region_RAM0_start__ ;
+export symbol __region_RAM0_end__ ;
+
+/*-  SRAM1 memory region -*/
+define symbol __region_RAM1_size__          = 0x8000 ;
+define symbol __region_RAM1_start__         = 0x20080000 ;
+define symbol __region_RAM1_end__           = __region_RAM1_start__+__region_RAM1_size__-1 ;
+
+export symbol __region_RAM1_size__ ;
+export symbol __region_RAM1_start__ ;
+export symbol __region_RAM1_end__ ;
+
+/*- Continous SRAM region (SRAM0 is mirrored) -*/
+define symbol __region_RAM_size__           = __region_RAM0_size__+__region_RAM1_size__ ;
+define symbol __region_RAM_start__          = __region_RAM1_start__-__region_RAM0_size__ ;
+define symbol __region_RAM_end__            = __region_RAM1_end__ ;
+
+export symbol __region_RAM_size__ ;
+export symbol __region_RAM_start__ ;
+export symbol __region_RAM_end__ ;
+
+/*- NFC SRAM region -*/
+define symbol __region_NFC_RAM_start__      = 0x20100000 ;
+define symbol __region_NFC_RAM_end__        = 0x20100FFF ;
+
+export symbol __region_NFC_RAM_start__ ;
+export symbol __region_NFC_RAM_end__ ;
+
+/*- Flash region -*/
+define symbol __region_ROM_size__           = 0x00040000 ;
+define symbol __region_ROM_start__          = 0x00080000 ;
+define symbol __region_ROM_end__            = __region_ROM_start__+__region_ROM_size__-1 ;
+
+export symbol __region_ROM_size__ ;
+export symbol __region_ROM_start__ ;
+export symbol __region_ROM_end__ ;
+
+/*-Vector table start*/
+define symbol __vector_start__              = __region_ROM_start__ ;
+
+/*-Sizes-*/
+define symbol __size_cstack__               = 0x2000 ;
+define symbol __size_heap__                 = 0x2000 ;
+
+define memory mem with size                 = 4G ;
+define region RAM_region                    = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region ROM_region                    = mem:[from __region_ROM_start__ to __region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__vector_start__ { readonly section .intvec };
+place in ROM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3x4_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3x4_sram.icf
new file mode 100644
index 0000000..763159a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3x4_sram.icf
@@ -0,0 +1,53 @@
+/*-  SRAM0 memory region -*/
+define symbol __region_RAM0_size__          = 0x8000 ;
+define symbol __region_RAM0_start__         = 0x20000000 ;
+define symbol __region_RAM0_end__           = __region_RAM0_start__+__region_RAM0_size__-1 ;
+
+export symbol __region_RAM0_size__ ;
+export symbol __region_RAM0_start__ ;
+export symbol __region_RAM0_end__ ;
+
+/*-  SRAM1 memory region -*/
+define symbol __region_RAM1_size__          = 0x8000 ;
+define symbol __region_RAM1_start__         = 0x20080000 ;
+define symbol __region_RAM1_end__           = __region_RAM1_start__+__region_RAM1_size__-1 ;
+
+export symbol __region_RAM1_size__ ;
+export symbol __region_RAM1_start__ ;
+export symbol __region_RAM1_end__ ;
+
+/*- Continous SRAM region (SRAM0 is mirrored) -*/
+define symbol __region_RAM_size__           = __region_RAM0_size__+__region_RAM1_size__ ;
+define symbol __region_RAM_start__          = __region_RAM1_start__-__region_RAM0_size__ ;
+define symbol __region_RAM_end__            = __region_RAM1_end__ ;
+
+export symbol __region_RAM_size__ ;
+export symbol __region_RAM_start__ ;
+export symbol __region_RAM_end__ ;
+
+/*- NFC SRAM region -*/
+define symbol __region_NFC_RAM_start__      = 0x20100000 ;
+define symbol __region_NFC_RAM_end__        = 0x20100FFF ;
+
+export symbol __region_NFC_RAM_start__ ;
+export symbol __region_NFC_RAM_end__ ;
+
+/*-Vector table start*/
+define symbol __vector_start__              = __region_RAM_start__ ;
+
+/*-Sizes-*/
+define symbol __size_cstack__               = 0x2000 ;
+define symbol __size_heap__                 = 0x2000 ;
+
+define memory mem with size                 = 4G ;
+define region RAM_region                    = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__vector_start__ { readonly section .intvec };
+place in RAM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3x8_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3x8_flash.icf
new file mode 100644
index 0000000..c67dd50
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3x8_flash.icf
@@ -0,0 +1,63 @@
+/*-  SRAM0 memory region -*/
+define symbol __region_RAM0_size__          = 0x10000 ;
+define symbol __region_RAM0_start__         = 0x20000000 ;
+define symbol __region_RAM0_end__           = __region_RAM0_start__+__region_RAM0_size__-1 ;
+
+export symbol __region_RAM0_size__ ;
+export symbol __region_RAM0_start__ ;
+export symbol __region_RAM0_end__ ;
+
+/*-  SRAM1 memory region -*/
+define symbol __region_RAM1_size__          = 0x8000 ;
+define symbol __region_RAM1_start__         = 0x20080000 ;
+define symbol __region_RAM1_end__           = __region_RAM1_start__+__region_RAM1_size__-1 ;
+
+export symbol __region_RAM1_size__ ;
+export symbol __region_RAM1_start__ ;
+export symbol __region_RAM1_end__ ;
+
+/*- Continous SRAM region (SRAM0 is mirrored) -*/
+define symbol __region_RAM_size__           = __region_RAM0_size__+__region_RAM1_size__ ;
+define symbol __region_RAM_start__          = __region_RAM1_start__-__region_RAM0_size__ ;
+define symbol __region_RAM_end__            = __region_RAM1_end__ ;
+
+export symbol __region_RAM_size__ ;
+export symbol __region_RAM_start__ ;
+export symbol __region_RAM_end__ ;
+
+/*- NFC SRAM region -*/
+define symbol __region_NFC_RAM_start__      = 0x20100000 ;
+define symbol __region_NFC_RAM_end__        = 0x20100FFF ;
+
+export symbol __region_NFC_RAM_start__ ;
+export symbol __region_NFC_RAM_end__ ;
+
+/*- Flash region -*/
+define symbol __region_ROM_size__           = 0x00080000 ;
+define symbol __region_ROM_start__          = 0x00080000 ;
+define symbol __region_ROM_end__            = __region_ROM_start__+__region_ROM_size__-1 ;
+
+export symbol __region_ROM_size__ ;
+export symbol __region_ROM_start__ ;
+export symbol __region_ROM_end__ ;
+
+/*-Vector table start*/
+define symbol __vector_start__              = __region_ROM_start__ ;
+
+/*-Sizes-*/
+define symbol __size_cstack__               = 0x2000 ;
+define symbol __size_heap__                 = 0x2000 ;
+
+define memory mem with size                 = 4G ;
+define region RAM_region                    = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region ROM_region                    = mem:[from __region_ROM_start__ to __region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__vector_start__ { readonly section .intvec };
+place in ROM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3x8_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3x8_sram.icf
new file mode 100644
index 0000000..ae3140a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/sam3x8_sram.icf
@@ -0,0 +1,53 @@
+/*-  SRAM0 memory region -*/
+define symbol __region_RAM0_size__          = 0x10000 ;
+define symbol __region_RAM0_start__         = 0x20000000 ;
+define symbol __region_RAM0_end__           = __region_RAM0_start__+__region_RAM0_size__-1 ;
+
+export symbol __region_RAM0_size__ ;
+export symbol __region_RAM0_start__ ;
+export symbol __region_RAM0_end__ ;
+
+/*-  SRAM1 memory region -*/
+define symbol __region_RAM1_size__          = 0x8000 ;
+define symbol __region_RAM1_start__         = 0x20080000 ;
+define symbol __region_RAM1_end__           = __region_RAM1_start__+__region_RAM1_size__-1 ;
+
+export symbol __region_RAM1_size__ ;
+export symbol __region_RAM1_start__ ;
+export symbol __region_RAM1_end__ ;
+
+/*- Continous SRAM region (SRAM0 is mirrored) -*/
+define symbol __region_RAM_size__           = __region_RAM0_size__+__region_RAM1_size__ ;
+define symbol __region_RAM_start__          = __region_RAM1_start__-__region_RAM0_size__ ;
+define symbol __region_RAM_end__            = __region_RAM1_end__ ;
+
+export symbol __region_RAM_size__ ;
+export symbol __region_RAM_start__ ;
+export symbol __region_RAM_end__ ;
+
+/*- NFC SRAM region -*/
+define symbol __region_NFC_RAM_start__      = 0x20100000 ;
+define symbol __region_NFC_RAM_end__        = 0x20100FFF ;
+
+export symbol __region_NFC_RAM_start__ ;
+export symbol __region_NFC_RAM_end__ ;
+
+/*-Vector table start*/
+define symbol __vector_start__              = __region_RAM_start__ ;
+
+/*-Sizes-*/
+define symbol __size_cstack__               = 0x2000 ;
+define symbol __size_heap__                 = 0x2000 ;
+
+define memory mem with size                 = 4G ;
+define region RAM_region                    = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__vector_start__ { readonly section .intvec };
+place in RAM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/startup_sam3xa.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/startup_sam3xa.c
new file mode 100644
index 0000000..123287d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/iar/startup_sam3xa.c
@@ -0,0 +1,272 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam3xa.h"
+
+/* Initialize segments */
+extern uint32_t __cstack_start__;
+extern uint32_t __cstack_end__;
+
+
+extern void __iar_program_start(void);
+extern int __low_level_init(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+#pragma weak NMI_Handler=Dummy_Handler
+#pragma weak HardFault_Handler=Dummy_Handler
+#pragma weak MemManage_Handler=Dummy_Handler
+#pragma weak BusFault_Handler=Dummy_Handler
+#pragma weak UsageFault_Handler=Dummy_Handler
+#pragma weak SVC_Handler=Dummy_Handler
+#pragma weak DebugMon_Handler=Dummy_Handler
+#pragma weak PendSV_Handler=Dummy_Handler
+#pragma weak SysTick_Handler=Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak SUPC_Handler=Dummy_Handler
+#pragma weak RSTC_Handler=Dummy_Handler
+#pragma weak RTC_Handler=Dummy_Handler
+#pragma weak RTT_Handler=Dummy_Handler
+#pragma weak WDT_Handler=Dummy_Handler
+#pragma weak PMC_Handler=Dummy_Handler
+#pragma weak EFC0_Handler=Dummy_Handler
+#pragma weak EFC1_Handler=Dummy_Handler
+#pragma weak UART_Handler=Dummy_Handler
+#ifdef _SAM3XA_SMC_INSTANCE_
+#pragma weak SMC_Handler=Dummy_Handler
+#endif /* _SAM3XA_SMC_INSTANCE_ */
+#ifdef _SAM3XA_SDRAMC_INSTANCE_
+#pragma weak SDRAMC_Handler=Dummy_Handler
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
+#pragma weak PIOA_Handler=Dummy_Handler
+#pragma weak PIOB_Handler=Dummy_Handler
+#ifdef _SAM3XA_PIOC_INSTANCE_
+#pragma weak PIOC_Handler=Dummy_Handler
+#endif /* _SAM3XA_PIOC_INSTANCE_ */
+#ifdef _SAM3XA_PIOD_INSTANCE_
+#pragma weak PIOD_Handler=Dummy_Handler
+#endif /* _SAM3XA_PIOD_INSTANCE_ */
+#ifdef _SAM3XA_PIOE_INSTANCE_
+#pragma weak PIOE_Handler=Dummy_Handler
+#endif /* _SAM3XA_PIOE_INSTANCE_ */
+#ifdef _SAM3XA_PIOF_INSTANCE_
+#pragma weak PIOF_Handler=Dummy_Handler
+#endif /* _SAM3XA_PIOF_INSTANCE_ */
+#pragma weak USART0_Handler=Dummy_Handler
+#pragma weak USART1_Handler=Dummy_Handler
+#pragma weak USART2_Handler=Dummy_Handler
+#ifdef _SAM3XA_USART3_INSTANCE_
+#pragma weak USART3_Handler=Dummy_Handler
+#endif /* _SAM3XA_USART3_INSTANCE_ */
+#pragma weak HSMCI_Handler=Dummy_Handler
+#pragma weak TWI0_Handler=Dummy_Handler
+#pragma weak TWI1_Handler=Dummy_Handler
+#pragma weak SPI0_Handler=Dummy_Handler
+#ifdef _SAM3XA_SPI1_INSTANCE_
+#pragma weak SPI1_Handler=Dummy_Handler
+#endif /* _SAM3XA_SPI1_INSTANCE_ */
+#pragma weak SSC_Handler=Dummy_Handler
+#pragma weak TC0_Handler=Dummy_Handler
+#pragma weak TC1_Handler=Dummy_Handler
+#pragma weak TC2_Handler=Dummy_Handler
+#pragma weak TC3_Handler=Dummy_Handler
+#pragma weak TC4_Handler=Dummy_Handler
+#pragma weak TC5_Handler=Dummy_Handler
+#ifdef _SAM3XA_TC2_INSTANCE_
+#pragma weak TC6_Handler=Dummy_Handler
+#pragma weak TC7_Handler=Dummy_Handler
+#pragma weak TC8_Handler=Dummy_Handler
+#endif /* _SAM3XA_TC2_INSTANCE_ */
+#pragma weak PWM_Handler=Dummy_Handler
+#pragma weak ADC_Handler=Dummy_Handler
+#pragma weak DACC_Handler=Dummy_Handler
+#pragma weak DMAC_Handler=Dummy_Handler
+#pragma weak UOTGHS_Handler=Dummy_Handler
+#pragma weak TRNG_Handler=Dummy_Handler
+#ifdef _SAM3XA_EMAC_INSTANCE_
+#pragma weak EMAC_Handler=Dummy_Handler
+#endif /* _SAM3XA_EMAC_INSTANCE_ */
+#pragma weak CAN0_Handler=Dummy_Handler
+#pragma weak CAN1_Handler=Dummy_Handler
+
+/* Exception Table */
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section = ".intvec"
+#pragma location = ".intvec"
+const DeviceVectors __vector_table[] = {
+	(void*) (&__cstack_end__),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /*  0  Supply Controller */
+	(void*) RSTC_Handler,    /*  1  Reset Controller */
+	(void*) RTC_Handler,     /*  2  Real Time Clock */
+	(void*) RTT_Handler,     /*  3  Real Time Timer */
+	(void*) WDT_Handler,     /*  4  Watchdog Timer */
+	(void*) PMC_Handler,     /*  5  PMC */
+	(void*) EFC0_Handler,    /*  6  EFC 0 */
+	(void*) EFC1_Handler,    /*  7  EFC 1 */
+	(void*) UART_Handler,    /*  8  UART */
+#ifdef _SAM3XA_SMC_INSTANCE_
+	(void*) SMC_Handler,     /*  9  SMC */
+#else
+	(void*) (0UL),           /*  9 Reserved */
+#endif /* _SAM3XA_SMC_INSTANCE_ */
+#ifdef _SAM3XA_SDRAMC_INSTANCE_
+	(void*) SDRAMC_Handler,  /* 10  SDRAMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM3XA_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM3XA_PIOC_INSTANCE_ */
+#ifdef _SAM3XA_PIOD_INSTANCE_
+	(void*) PIOD_Handler,    /* 14 Parallel IO Controller D */
+#else
+	(void*) (0UL),           /* 14 Reserved */
+#endif /* _SAM3XA_PIOD_INSTANCE_ */
+#ifdef _SAM3XA_PIOE_INSTANCE_
+	(void*) PIOE_Handler,    /* 15 Parallel IO Controller E */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM3XA_PIOE_INSTANCE_ */
+#ifdef _SAM3XA_PIOF_INSTANCE_
+	(void*) PIOF_Handler,    /* 16 Parallel IO Controller F */
+#else
+	(void*) (0UL),           /* 16 Reserved */
+#endif /* _SAM3XA_PIOF_INSTANCE_ */
+	(void*) USART0_Handler,  /* 17 USART 0 */
+	(void*) USART1_Handler,  /* 18 USART 1 */
+	(void*) USART2_Handler,  /* 19 USART 2 */
+#ifdef _SAM3XA_USART3_INSTANCE_
+	(void*) USART3_Handler,  /* 20 USART 3 */
+#else
+	(void*) (0UL),           /* 20 Reserved */
+#endif /* _SAM3XA_USART3_INSTANCE_ */
+	(void*) HSMCI_Handler,   /* 21 MCI */
+	(void*) TWI0_Handler,    /* 22 TWI 0 */
+	(void*) TWI1_Handler,    /* 23 TWI 1 */
+	(void*) SPI0_Handler,    /* 24 SPI 0 */
+#ifdef _SAM3XA_SPI1_INSTANCE_
+	(void*) SPI1_Handler,    /* 25 SPI 1 */
+#else
+	(void*) (0UL),           /* 25 Reserved */
+#endif /* _SAM3XA_SPI1_INSTANCE_ */
+	(void*) SSC_Handler,     /* 26 SSC */
+	(void*) TC0_Handler,     /* 27 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 28 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 29 Timer Counter 2 */
+	(void*) TC3_Handler,     /* 30 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 31 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 32 Timer Counter 5 */
+#ifdef _SAM3XA_TC2_INSTANCE_
+	(void*) TC6_Handler,     /* 33 Timer Counter 6 */
+	(void*) TC7_Handler,     /* 34 Timer Counter 7 */
+	(void*) TC8_Handler,     /* 35 Timer Counter 8 */
+#else
+	(void*) (0UL),           /* 33 Reserved */
+	(void*) (0UL),           /* 34 Reserved */
+	(void*) (0UL),           /* 35 Reserved */
+#endif /* _SAM3XA_TC2_INSTANCE_ */
+	(void*) PWM_Handler,     /* 36 PWM */
+	(void*) ADC_Handler,     /* 37 ADC controller */
+	(void*) DACC_Handler,    /* 38 DAC controller */
+	(void*) DMAC_Handler,    /* 39 DMA Controller */
+	(void*) UOTGHS_Handler,  /* 40 USB OTG High Speed */
+	(void*) TRNG_Handler,    /* 41 True Random Number Generator */
+#ifdef _SAM3XA_EMAC_INSTANCE_
+	(void*) EMAC_Handler,    /* 42 Ethernet MAC */
+#else
+	(void*) (0UL),           /* 42 Reserved */
+#endif /* _SAM3XA_EMAC_INSTANCE_ */
+	(void*) CAN0_Handler,    /* 43 CAN Controller 0 */
+	(void*) CAN1_Handler     /* 44 CAN Controller 1 */
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+	uint32_t *pSrc = __section_begin(".intvec");
+
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < NFC_RAM_ADDR)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+	__iar_program_start();
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/system_sam3xa.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/system_sam3xa.c
new file mode 100644
index 0000000..229c10d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam3xa/source/system_sam3xa.c
@@ -0,0 +1,191 @@
+/*! \file *********************************************************************
+ *
+ * \brief Provides the low-level initialization functions that called 
+ * on chip startup.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based 
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#include "sam3xa.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Clock settings (84MHz) */
+#define SYS_BOARD_OSCOUNT   (CKGR_MOR_MOSCXTST(0x8))
+#define SYS_BOARD_PLLAR     (CKGR_PLLAR_ONE \
+							| CKGR_PLLAR_MULA(0xdUL) \
+							| CKGR_PLLAR_PLLACOUNT(0x3fUL) \
+							| CKGR_PLLAR_DIVA(0x1UL))
+#define SYS_BOARD_MCKR      (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)
+
+/* Clock Definitions */
+#define SYS_UTMIPLL     		(480000000UL)	/* UTMI PLL frequency */
+
+#define SYS_CKGR_MOR_KEY_VALUE	CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
+
+/* FIXME: should be generated by sock */
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+/**
+ * \brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit(void)
+{
+	/* Set FWS according to SYS_BOARD_MCKR configuration */
+	EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
+	EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
+
+	/* Initialize main oscillator */
+	if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
+		PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | 
+			                     CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+		while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
+		}
+	}
+
+	/* Switch to 3-20MHz Xtal oscillator */
+	PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | 
+	                           CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+
+	while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
+	}
+ 	PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | 
+		                     PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Initialize PLLA */
+	PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
+	while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
+	}
+
+	/* Switch to main clock */
+	PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Switch to PLLA */
+	PMC->PMC_MCKR = SYS_BOARD_MCKR;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	SystemCoreClock = CHIP_FREQ_CPU_MAX;
+}
+
+void SystemCoreClockUpdate(void)
+{
+	/* Determine clock frequency according to clock register values */
+	switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
+	case PMC_MCKR_CSS_SLOW_CLK:	/* Slow clock */
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_32K;
+		} else {
+			SystemCoreClock = CHIP_FREQ_SLCK_RC;
+		}
+		break;
+	case PMC_MCKR_CSS_MAIN_CLK:	/* Main clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	case PMC_MCKR_CSS_PLLA_CLK:	/* PLLA clock */
+	case PMC_MCKR_CSS_UPLL_CLK:	/* UPLL clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
+			SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> 
+				                            CKGR_PLLAR_MULA_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> 
+				                             CKGR_PLLAR_DIVA_Pos));
+		} else {
+			SystemCoreClock = SYS_UTMIPLL / 2U;
+		}
+		break;
+	}
+
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
+		SystemCoreClock /= 3U;
+	} else {
+		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> 
+			                          PMC_MCKR_PRES_Pos);
+	}
+}
+
+/** 
+ * Initialize flash.
+ */
+void system_init_flash(uint32_t dw_clk)
+{
+	/* Set FWS for embedded Flash access according to operating frequency */
+	if (dw_clk < CHIP_FREQ_FWS_0) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
+	} else if (dw_clk < CHIP_FREQ_FWS_1) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(1);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(1);
+	} else if (dw_clk < CHIP_FREQ_FWS_2) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(2);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(2);
+	} else if (dw_clk < CHIP_FREQ_FWS_3) {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(3);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(3);
+	} else {
+		EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
+		EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
+	}
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4.h
new file mode 100644
index 0000000..b7d72c3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4.h
@@ -0,0 +1,40 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4_INCLUDED_
+#define _SAM4_INCLUDED_
+
+#if (defined __SAM4S16C__) || (defined __SAM4S16B__) || /* SAM4S16 */ \
+    (defined __SAM4S8C__) || (defined __SAM4S8B__)     /* SAM4S8 */
+  #include "sam4s/include/sam4s.h"
+#else
+  #error Device not supported.
+#endif
+
+#endif /* _SAM4_INCLUDED_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_acc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_acc.h
new file mode 100644
index 0000000..64599a8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_acc.h
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_ACC_COMPONENT_
+#define _SAM4S_ACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog Comparator Controller */
+/* ============================================================================= */
+/** \addtogroup SAM4S_ACC Analog Comparator Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Acc hardware registers */
+typedef struct {
+  WoReg ACC_CR;        /**< \brief (Acc Offset: 0x00) Control Register */
+  RwReg ACC_MR;        /**< \brief (Acc Offset: 0x04) Mode Register */
+  RoReg Reserved1[7];
+  WoReg ACC_IER;       /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */
+  WoReg ACC_IDR;       /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */
+  RoReg ACC_IMR;       /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ACC_ISR;       /**< \brief (Acc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[24];
+  RwReg ACC_ACR;       /**< \brief (Acc Offset: 0x94) Analog Control Register */
+  RoReg Reserved3[19];
+  RwReg ACC_WPMR;      /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ACC_WPSR;      /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */
+} Acc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
+#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) SoftWare ReSeT */
+/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
+#define ACC_MR_SELMINUS_Pos 0
+#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) SELection for MINUS comparator input */
+#define   ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) SelectTS */
+#define   ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */
+#define   ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */
+#define   ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */
+#define   ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */
+#define   ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */
+#define   ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */
+#define   ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */
+#define ACC_MR_SELPLUS_Pos 4
+#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) SELection for PLUS comparator input */
+#define   ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */
+#define   ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */
+#define   ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */
+#define   ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */
+#define   ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */
+#define   ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */
+#define   ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */
+#define   ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */
+#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator ENable */
+#define   ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog Comparator Disabled. */
+#define   ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enabled. */
+#define ACC_MR_EDGETYP_Pos 9
+#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) EDGE TYPe */
+#define   ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) only rising edge of comparator output */
+#define   ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) falling edge of comparator output */
+#define   ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) any edge of comparator output */
+#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) INVert comparator output */
+#define   ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog Comparator output is directly processed. */
+#define   ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog Comparator output is inverted prior to being processed. */
+#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) SELection of Fault Source */
+#define   ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) the CF flag is used to drive the FAULT output. */
+#define   ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) the output of the Analog Comparator flag is used to drive the FAULT output. */
+#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */
+#define   ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) the FAULT output is tied to 0. */
+#define   ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) the FAULT output is driven by the signal defined by SELFS. */
+/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
+#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */
+/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
+#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */
+/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */
+/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
+#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */
+#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */
+#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR)  */
+/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
+#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current SELection */
+#define   ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) low power option. */
+#define   ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) high speed option. */
+#define ACC_ACR_HYST_Pos 1
+#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) HYSTeresis selection */
+#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
+/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protect Enable */
+#define ACC_WPMR_WPKEY_Pos 8
+#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protect KEY */
+#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
+/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */
+#define ACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */
+
+/*@}*/
+
+
+#endif /* _SAM4S_ACC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_adc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_adc.h
new file mode 100644
index 0000000..ab198ed
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_adc.h
@@ -0,0 +1,506 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_ADC_COMPONENT_
+#define _SAM4S_ADC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
+/* ============================================================================= */
+/** \addtogroup SAM4S_ADC Analog-to-digital Converter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Adc hardware registers */
+typedef struct {
+  WoReg ADC_CR;        /**< \brief (Adc Offset: 0x00) Control Register */
+  RwReg ADC_MR;        /**< \brief (Adc Offset: 0x04) Mode Register */
+  RwReg ADC_SEQR1;     /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
+  RwReg ADC_SEQR2;     /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
+  WoReg ADC_CHER;      /**< \brief (Adc Offset: 0x10) Channel Enable Register */
+  WoReg ADC_CHDR;      /**< \brief (Adc Offset: 0x14) Channel Disable Register */
+  RoReg ADC_CHSR;      /**< \brief (Adc Offset: 0x18) Channel Status Register */
+  RoReg Reserved1[1];
+  RoReg ADC_LCDR;      /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
+  WoReg ADC_IER;       /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
+  WoReg ADC_IDR;       /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
+  RoReg ADC_IMR;       /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
+  RoReg ADC_ISR;       /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved2[2];
+  RoReg ADC_OVER;      /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
+  RwReg ADC_EMR;       /**< \brief (Adc Offset: 0x40) Extended Mode Register */
+  RwReg ADC_CWR;       /**< \brief (Adc Offset: 0x44) Compare Window Register */
+  RwReg ADC_CGR;       /**< \brief (Adc Offset: 0x48) Channel Gain Register */
+  RwReg ADC_COR;       /**< \brief (Adc Offset: 0x4C) Channel Offset Register */
+  RoReg ADC_CDR[16];   /**< \brief (Adc Offset: 0x50) Channel Data Register */
+  RoReg Reserved3[1];
+  RwReg ADC_ACR;       /**< \brief (Adc Offset: 0x94) Analog Control Register */
+  RoReg Reserved4[19];
+  RwReg ADC_WPMR;      /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
+  RoReg ADC_WPSR;      /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved5[5];
+  RwReg ADC_RPR;       /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
+  RwReg ADC_RCR;       /**< \brief (Adc Offset: 0x104) Receive Counter Register */
+  RoReg Reserved6[2];
+  RwReg ADC_RNPR;      /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
+  RwReg ADC_RNCR;      /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
+  RoReg Reserved7[2];
+  WoReg ADC_PTCR;      /**< \brief (Adc Offset: 0x120) Transfer Control Register */
+  RoReg ADC_PTSR;      /**< \brief (Adc Offset: 0x124) Transfer Status Register */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
+#define ADC_CR_AUTOCAL (0x1u << 3) /**< \brief (ADC_CR) Automatic Calibration of ADC */
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
+#define   ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
+#define   ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
+#define ADC_MR_TRGSEL_Pos 1
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
+#define   ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */
+#define   ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */
+#define   ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */
+#define   ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */
+#define   ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
+#define   ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */
+#define   ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
+#define   ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
+#define   ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
+#define   ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
+#define   ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */
+#define   ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */
+#define   ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */
+#define ADC_MR_PRESCAL_Pos 8
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
+#define ADC_MR_STARTUP_Pos 16
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
+#define   ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */
+#define   ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */
+#define ADC_MR_SETTLING_Pos 20
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */
+#define   ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */
+#define   ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */
+#define   ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */
+#define   ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */
+#define ADC_MR_TRACKTIM_Pos 24
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
+#define ADC_MR_TRANSFER_Pos 28
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
+#define   ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. */
+#define   ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. */
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
+#define ADC_SEQR1_USCH1_Pos 0
+#define ADC_SEQR1_USCH1_Msk (0x7u << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
+#define ADC_SEQR1_USCH2_Pos 4
+#define ADC_SEQR1_USCH2_Msk (0x7u << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
+#define ADC_SEQR1_USCH3_Pos 8
+#define ADC_SEQR1_USCH3_Msk (0x7u << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
+#define ADC_SEQR1_USCH4_Pos 12
+#define ADC_SEQR1_USCH4_Msk (0x7u << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
+#define ADC_SEQR1_USCH5_Pos 16
+#define ADC_SEQR1_USCH5_Msk (0x7u << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
+#define ADC_SEQR1_USCH6_Pos 20
+#define ADC_SEQR1_USCH6_Msk (0x7u << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
+#define ADC_SEQR1_USCH7_Pos 24
+#define ADC_SEQR1_USCH7_Msk (0x7u << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
+#define ADC_SEQR1_USCH8_Pos 28
+#define ADC_SEQR1_USCH8_Msk (0x7u << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
+#define ADC_SEQR2_USCH9_Pos 0
+#define ADC_SEQR2_USCH9_Msk (0x7u << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
+#define ADC_SEQR2_USCH10_Pos 4
+#define ADC_SEQR2_USCH10_Msk (0x7u << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
+#define ADC_SEQR2_USCH11_Pos 8
+#define ADC_SEQR2_USCH11_Msk (0x7u << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
+#define ADC_SEQR2_USCH12_Pos 12
+#define ADC_SEQR2_USCH12_Msk (0x7u << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
+#define ADC_SEQR2_USCH13_Pos 16
+#define ADC_SEQR2_USCH13_Msk (0x7u << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
+#define ADC_SEQR2_USCH14_Pos 20
+#define ADC_SEQR2_USCH14_Msk (0x7u << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
+#define ADC_SEQR2_USCH15_Pos 24
+#define ADC_SEQR2_USCH15_Msk (0x7u << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
+#define ADC_SEQR2_USCH16_Pos 28
+#define ADC_SEQR2_USCH16_Msk (0x7u << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
+#define ADC_LCDR_LDATA_Pos 0
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
+#define ADC_LCDR_CHNB_Pos 12
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
+#define ADC_IER_EOCAL (0x1u << 23) /**< \brief (ADC_IER) End of Calibration Sequence */
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
+#define ADC_IDR_EOCAL (0x1u << 23) /**< \brief (ADC_IDR) End of Calibration Sequence */
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
+#define ADC_IMR_EOCAL (0x1u << 23) /**< \brief (ADC_IMR) End of Calibration Sequence */
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
+#define ADC_ISR_EOCAL (0x1u << 23) /**< \brief (ADC_ISR) End of Calibration Sequence */
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
+#define ADC_EMR_CMPMODE_Pos 0
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
+#define   ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
+#define   ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
+#define   ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
+#define   ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
+#define ADC_EMR_CMPSEL_Pos 4
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of the ADC_LDCR register */
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
+#define ADC_CWR_LOWTHRES_Pos 0
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
+#define ADC_CWR_HIGHTHRES_Pos 16
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */
+#define ADC_CGR_GAIN0_Pos 0
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))
+#define ADC_CGR_GAIN1_Pos 2
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))
+#define ADC_CGR_GAIN2_Pos 4
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))
+#define ADC_CGR_GAIN3_Pos 6
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))
+#define ADC_CGR_GAIN4_Pos 8
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))
+#define ADC_CGR_GAIN5_Pos 10
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))
+#define ADC_CGR_GAIN6_Pos 12
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))
+#define ADC_CGR_GAIN7_Pos 14
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))
+#define ADC_CGR_GAIN8_Pos 16
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))
+#define ADC_CGR_GAIN9_Pos 18
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))
+#define ADC_CGR_GAIN10_Pos 20
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))
+#define ADC_CGR_GAIN11_Pos 22
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))
+#define ADC_CGR_GAIN12_Pos 24
+#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */
+#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))
+#define ADC_CGR_GAIN13_Pos 26
+#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */
+#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))
+#define ADC_CGR_GAIN14_Pos 28
+#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */
+#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))
+#define ADC_CGR_GAIN15_Pos 30
+#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */
+#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */
+#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */
+#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */
+#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */
+#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */
+#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */
+#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */
+#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */
+#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */
+/* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */
+#define ADC_CDR_DATA_Pos 0
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[16]) Converted Data */
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */
+#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */
+#define ADC_ACR_IBCTL_Pos 8
+#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */
+#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
+#define ADC_WPMR_WPKEY_Pos 8
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
+#define ADC_WPSR_WPVSRC_Pos 8
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
+#define ADC_RPR_RXPTR_Pos 0
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
+#define ADC_RCR_RXCTR_Pos 0
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
+#define ADC_RNPR_RXNPTR_Pos 0
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
+#define ADC_RNCR_RXNCTR_Pos 0
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM4S_ADC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_chipid.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_chipid.h
new file mode 100644
index 0000000..571386e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_chipid.h
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_CHIPID_COMPONENT_
+#define _SAM4S_CHIPID_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Chip Identifier */
+/* ============================================================================= */
+/** \addtogroup SAM4S_CHIPID Chip Identifier */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Chipid hardware registers */
+typedef struct {
+  RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
+  RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
+} Chipid;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
+#define CHIPID_CIDR_VERSION_Pos 0
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
+#define CHIPID_CIDR_EPROC_Pos 5
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
+#define   CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
+#define   CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
+#define   CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
+#define   CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
+#define   CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
+#define   CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
+#define   CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
+#define CHIPID_CIDR_NVPSIZ_Pos 8
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
+#define   CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_NVPSIZ2_Pos 12
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR)  */
+#define   CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
+#define   CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
+#define   CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
+#define CHIPID_CIDR_SRAMSIZ_Pos 16
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
+#define   CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
+#define   CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
+#define CHIPID_CIDR_ARCH_Pos 20
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
+#define   CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
+#define   CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
+#define   CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
+#define   CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
+#define   CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
+#define   CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
+#define   CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
+#define   CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
+#define   CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
+#define   CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
+#define   CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3ASAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC or SAM4AxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XSAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxCor SAM4XxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XSAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxEor SAM4XxE Series (144-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3XSAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxGor or SAM4XxG Series  (208/217-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SSAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxA or SAM4SxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SSAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxBor SAM4SxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SSAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxCor SAM4SxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
+#define   CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
+#define   CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
+#define   CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
+#define CHIPID_CIDR_NVPTYP_Pos 28
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
+#define   CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
+#define   CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
+#define   CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
+#define   CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size      NVPSIZ2 is Flash size */
+#define   CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
+#define CHIPID_EXID_EXID_Pos 0
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
+
+/*@}*/
+
+
+#endif /* _SAM4S_CHIPID_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_crccu.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_crccu.h
new file mode 100644
index 0000000..79161ee
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_crccu.h
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_CRCCU_COMPONENT_
+#define _SAM4S_CRCCU_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */
+/* ============================================================================= */
+/** \addtogroup SAM4S_CRCCU Cyclic Redundancy Check Calculation Unit */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Crccu hardware registers */
+typedef struct {
+  RwReg CRCCU_DSCR;    /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */
+  RoReg Reserved1[1];
+  WoReg CRCCU_DMA_EN;  /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */
+  WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */
+  RoReg CRCCU_DMA_SR;  /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */
+  WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */
+  WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */
+  RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */
+  RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */
+  RoReg Reserved2[4];
+  WoReg CRCCU_CR;      /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */
+  RwReg CRCCU_MR;      /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */
+  RoReg CRCCU_SR;      /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */
+  WoReg CRCCU_IER;     /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */
+  WoReg CRCCU_IDR;     /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */
+  RoReg CRCCU_IMR;     /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */
+  RoReg CRCCU_ISR;     /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */
+} Crccu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */
+#define CRCCU_DSCR_DSCR_Pos 9
+#define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */
+#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos)))
+/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */
+#define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */
+/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */
+#define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */
+/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */
+#define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */
+/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */
+#define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */
+/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */
+#define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */
+/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */
+#define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */
+/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */
+#define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */
+/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */
+#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */
+/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */
+#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */
+#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */
+#define CRCCU_MR_PTYPE_Pos 2
+#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */
+#define   CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */
+#define   CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */
+#define   CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */
+#define CRCCU_MR_DIVIDER_Pos 4
+#define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */
+#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)))
+/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */
+#define CRCCU_SR_CRC_Pos 0
+#define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */
+/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */
+#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */
+/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */
+#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */
+/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */
+#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */
+/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */
+#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */
+
+/*@}*/
+
+
+#endif /* _SAM4S_CRCCU_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_dacc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_dacc.h
new file mode 100644
index 0000000..5a08414
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_dacc.h
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_DACC_COMPONENT_
+#define _SAM4S_DACC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
+/* ============================================================================= */
+/** \addtogroup SAM4S_DACC Digital-to-Analog Converter Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Dacc hardware registers */
+typedef struct {
+  WoReg DACC_CR;       /**< \brief (Dacc Offset: 0x00) Control Register */
+  RwReg DACC_MR;       /**< \brief (Dacc Offset: 0x04) Mode Register */
+  RoReg Reserved1[2];
+  WoReg DACC_CHER;     /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
+  WoReg DACC_CHDR;     /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
+  RoReg DACC_CHSR;     /**< \brief (Dacc Offset: 0x18) Channel Status Register */
+  RoReg Reserved2[1];
+  WoReg DACC_CDR;      /**< \brief (Dacc Offset: 0x20) Conversion Data Register */
+  WoReg DACC_IER;      /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
+  WoReg DACC_IDR;      /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
+  RoReg DACC_IMR;      /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
+  RoReg DACC_ISR;      /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
+  RoReg Reserved3[24];
+  RwReg DACC_ACR;      /**< \brief (Dacc Offset: 0x94) Analog Current Register */
+  RoReg Reserved4[19];
+  RwReg DACC_WPMR;     /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */
+  RoReg DACC_WPSR;     /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */
+  RoReg Reserved5[7];
+  RwReg DACC_TPR;      /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
+  RwReg DACC_TCR;      /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
+  RoReg Reserved6[2];
+  RwReg DACC_TNPR;     /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg DACC_TNCR;     /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg DACC_PTCR;     /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
+  RoReg DACC_PTSR;     /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
+} Dacc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
+#define   DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */
+#define   DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */
+#define DACC_MR_TRGSEL_Pos 1
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define   DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */
+#define   DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */
+#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */
+#define DACC_MR_REFRESH_Pos 8
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
+#define DACC_MR_USER_SEL_Pos 16
+#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */
+#define   DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */
+#define   DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */
+#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */
+#define   DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */
+#define   DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */
+#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */
+#define DACC_MR_STARTUP_Pos 24
+#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
+#define   DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */
+#define   DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */
+#define   DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */
+#define   DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */
+#define   DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */
+#define   DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */
+#define   DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */
+#define   DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */
+#define   DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */
+#define   DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */
+#define   DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */
+#define   DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */
+#define   DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */
+#define   DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */
+#define   DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */
+#define   DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */
+#define   DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */
+#define   DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */
+#define   DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */
+#define   DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */
+#define   DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */
+#define   DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */
+#define   DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */
+#define   DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */
+#define   DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */
+#define   DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */
+#define   DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */
+#define   DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */
+#define   DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */
+#define   DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */
+#define   DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */
+#define   DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
+/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */
+#define DACC_CDR_DATA_Pos 0
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */
+#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */
+#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */
+#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */
+#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */
+#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */
+#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */
+#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */
+#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */
+#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */
+#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */
+#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */
+#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
+#define DACC_ACR_IBCTLCH0_Pos 0
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
+#define DACC_ACR_IBCTLCH1_Pos 2
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
+#define DACC_ACR_IBCTLDACCORE_Pos 8
+#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */
+#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
+#define DACC_WPMR_WPKEY_Pos 8
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
+#define DACC_WPSR_WPROTADDR_Pos 8
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
+#define DACC_TPR_TXPTR_Pos 0
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
+#define DACC_TCR_TXCTR_Pos 0
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define DACC_TNPR_TXNPTR_Pos 0
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define DACC_TNCR_TXNCTR_Pos 0
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM4S_DACC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_efc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_efc.h
new file mode 100644
index 0000000..106357c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_efc.h
@@ -0,0 +1,78 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_EFC_COMPONENT_
+#define _SAM4S_EFC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Embedded Flash Controller */
+/* ============================================================================= */
+/** \addtogroup SAM4S_EFC Embedded Flash Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Efc hardware registers */
+typedef struct {
+  RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
+  WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
+  RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
+  RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
+} Efc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
+#define EEFC_FMR_FWS_Pos 8
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
+#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loops Optimization Enable */
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
+#define EEFC_FCR_FCMD_Pos 0
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_FCR_FARG_Pos 8
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
+#define EEFC_FCR_FKEY_Pos 24
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
+#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status */
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
+#define EEFC_FRR_FVALUE_Pos 0
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
+
+/*@}*/
+
+
+#endif /* _SAM4S_EFC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_gpbr.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_gpbr.h
new file mode 100644
index 0000000..bf34083
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_gpbr.h
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_GPBR_COMPONENT_
+#define _SAM4S_GPBR_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR General Purpose Backup Register */
+/* ============================================================================= */
+/** \addtogroup SAM4S_GPBR General Purpose Backup Register */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Gpbr hardware registers */
+typedef struct {
+  RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
+} Gpbr;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
+#define SYS_GPBR_GPBR_VALUE_Pos 0
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM4S_GPBR_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_hsmci.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_hsmci.h
new file mode 100644
index 0000000..0b39e2d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_hsmci.h
@@ -0,0 +1,384 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_HSMCI_COMPONENT_
+#define _SAM4S_HSMCI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
+/* ============================================================================= */
+/** \addtogroup SAM4S_HSMCI High Speed MultiMedia Card Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Hsmci hardware registers */
+typedef struct {
+  WoReg HSMCI_CR;        /**< \brief (Hsmci Offset: 0x00) Control Register */
+  RwReg HSMCI_MR;        /**< \brief (Hsmci Offset: 0x04) Mode Register */
+  RwReg HSMCI_DTOR;      /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
+  RwReg HSMCI_SDCR;      /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
+  RwReg HSMCI_ARGR;      /**< \brief (Hsmci Offset: 0x10) Argument Register */
+  WoReg HSMCI_CMDR;      /**< \brief (Hsmci Offset: 0x14) Command Register */
+  RwReg HSMCI_BLKR;      /**< \brief (Hsmci Offset: 0x18) Block Register */
+  RwReg HSMCI_CSTOR;     /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
+  RoReg HSMCI_RSPR[4];   /**< \brief (Hsmci Offset: 0x20) Response Register */
+  RoReg HSMCI_RDR;       /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
+  WoReg HSMCI_TDR;       /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
+  RoReg Reserved1[2];
+  RoReg HSMCI_SR;        /**< \brief (Hsmci Offset: 0x40) Status Register */
+  WoReg HSMCI_IER;       /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
+  WoReg HSMCI_IDR;       /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
+  RoReg HSMCI_IMR;       /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved2[1];
+  RwReg HSMCI_CFG;       /**< \brief (Hsmci Offset: 0x54) Configuration Register */
+  RoReg Reserved3[35];
+  RwReg HSMCI_WPMR;      /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
+  RoReg HSMCI_WPSR;      /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved4[5];
+  RwReg HSMCI_RPR;       /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */
+  RwReg HSMCI_RCR;       /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */
+  RwReg HSMCI_TPR;       /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */
+  RwReg HSMCI_TCR;       /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */
+  RwReg HSMCI_RNPR;      /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */
+  RwReg HSMCI_RNCR;      /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */
+  RwReg HSMCI_TNPR;      /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */
+  RwReg HSMCI_TNCR;      /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */
+  WoReg HSMCI_PTCR;      /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */
+  RoReg HSMCI_PTSR;      /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */
+  RoReg Reserved5[54];
+  RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
+} Hsmci;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
+#define HSMCI_MR_CLKDIV_Pos 0
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
+#define HSMCI_MR_PWSDIV_Pos 8
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR)  */
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
+#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
+#define HSMCI_DTOR_DTOCYC_Pos 0
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
+#define HSMCI_DTOR_DTOMUL_Pos 4
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
+#define   HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
+#define   HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
+#define   HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
+#define   HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
+#define   HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
+#define   HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
+#define   HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
+#define   HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
+#define HSMCI_SDCR_SDCSEL_Pos 0
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
+#define   HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
+#define   HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
+#define   HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
+#define HSMCI_SDCR_SDCBUS_Pos 6
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
+#define   HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
+#define   HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
+#define   HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
+#define HSMCI_ARGR_ARG_Pos 0
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
+#define HSMCI_CMDR_CMDNB_Pos 0
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
+#define HSMCI_CMDR_RSPTYP_Pos 6
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
+#define   HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
+#define   HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
+#define   HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
+#define   HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
+#define HSMCI_CMDR_SPCMD_Pos 8
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
+#define   HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
+#define   HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
+#define   HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
+#define   HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
+#define   HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
+#define   HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
+#define   HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
+#define   HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
+#define   HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
+#define   HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
+#define   HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
+#define HSMCI_CMDR_TRCMD_Pos 16
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
+#define   HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
+#define   HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
+#define   HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
+#define   HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
+#define   HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
+#define HSMCI_CMDR_TRTYP_Pos 19
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
+#define   HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
+#define   HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
+#define   HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
+#define   HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
+#define   HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
+#define HSMCI_CMDR_IOSPCMD_Pos 24
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
+#define   HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
+#define   HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
+#define   HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
+#define   HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
+#define HSMCI_BLKR_BCNT_Pos 0
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
+#define   HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
+#define   HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define   HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
+#define HSMCI_BLKR_BLKLEN_Pos 16
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
+#define HSMCI_CSTOR_CSTOCYC_Pos 0
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
+#define HSMCI_CSTOR_CSTOMUL_Pos 4
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
+#define   HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
+#define   HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
+#define   HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
+#define   HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
+#define   HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
+#define   HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
+#define   HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
+#define   HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
+#define HSMCI_RSPR_RSP_Pos 0
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
+#define HSMCI_RDR_DATA_Pos 0
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
+#define HSMCI_TDR_DATA_Pos 0
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
+#define HSMCI_SR_ENDRX (0x1u << 6) /**< \brief (HSMCI_SR) End of RX Buffer */
+#define HSMCI_SR_ENDTX (0x1u << 7) /**< \brief (HSMCI_SR) End of TX Buffer */
+#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
+#define HSMCI_SR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_SR) RX Buffer Full */
+#define HSMCI_SR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
+#define HSMCI_IER_ENDRX (0x1u << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */
+#define HSMCI_IER_ENDTX (0x1u << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */
+#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
+#define HSMCI_IER_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */
+#define HSMCI_IER_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
+#define HSMCI_IDR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */
+#define HSMCI_IDR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */
+#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
+#define HSMCI_IDR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */
+#define HSMCI_IDR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
+#define HSMCI_IMR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */
+#define HSMCI_IMR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */
+#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
+#define HSMCI_IMR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */
+#define HSMCI_IMR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
+#define HSMCI_WPMR_WP_KEY_Pos 8
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
+#define HSMCI_WPSR_WP_VS_Pos 0
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
+#define   HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
+#define   HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
+#define   HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
+#define   HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
+#define HSMCI_WPSR_WP_VSRC_Pos 8
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
+/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */
+#define HSMCI_RPR_RXPTR_Pos 0
+#define HSMCI_RPR_RXPTR_Msk (0xffffffffu << HSMCI_RPR_RXPTR_Pos) /**< \brief (HSMCI_RPR) Receive Pointer Register */
+#define HSMCI_RPR_RXPTR(value) ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos)))
+/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */
+#define HSMCI_RCR_RXCTR_Pos 0
+#define HSMCI_RCR_RXCTR_Msk (0xffffu << HSMCI_RCR_RXCTR_Pos) /**< \brief (HSMCI_RCR) Receive Counter Register */
+#define HSMCI_RCR_RXCTR(value) ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos)))
+/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */
+#define HSMCI_TPR_TXPTR_Pos 0
+#define HSMCI_TPR_TXPTR_Msk (0xffffffffu << HSMCI_TPR_TXPTR_Pos) /**< \brief (HSMCI_TPR) Transmit Counter Register */
+#define HSMCI_TPR_TXPTR(value) ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos)))
+/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */
+#define HSMCI_TCR_TXCTR_Pos 0
+#define HSMCI_TCR_TXCTR_Msk (0xffffu << HSMCI_TCR_TXCTR_Pos) /**< \brief (HSMCI_TCR) Transmit Counter Register */
+#define HSMCI_TCR_TXCTR(value) ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos)))
+/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */
+#define HSMCI_RNPR_RXNPTR_Pos 0
+#define HSMCI_RNPR_RXNPTR_Msk (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos) /**< \brief (HSMCI_RNPR) Receive Next Pointer */
+#define HSMCI_RNPR_RXNPTR(value) ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos)))
+/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */
+#define HSMCI_RNCR_RXNCTR_Pos 0
+#define HSMCI_RNCR_RXNCTR_Msk (0xffffu << HSMCI_RNCR_RXNCTR_Pos) /**< \brief (HSMCI_RNCR) Receive Next Counter */
+#define HSMCI_RNCR_RXNCTR(value) ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos)))
+/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define HSMCI_TNPR_TXNPTR_Pos 0
+#define HSMCI_TNPR_TXNPTR_Msk (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */
+#define HSMCI_TNPR_TXNPTR(value) ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos)))
+/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define HSMCI_TNCR_TXNCTR_Pos 0
+#define HSMCI_TNCR_TXNCTR_Msk (0xffffu << HSMCI_TNCR_TXNCTR_Pos) /**< \brief (HSMCI_TNCR) Transmit Counter Next */
+#define HSMCI_TNCR_TXNCTR(value) ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos)))
+/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */
+#define HSMCI_PTCR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */
+#define HSMCI_PTCR_RXTDIS (0x1u << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */
+#define HSMCI_PTCR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */
+#define HSMCI_PTCR_TXTDIS (0x1u << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */
+/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */
+#define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */
+#define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM4S_HSMCI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_matrix.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_matrix.h
new file mode 100644
index 0000000..1a1d5b8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_matrix.h
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_MATRIX_COMPONENT_
+#define _SAM4S_MATRIX_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR AHB Bus Matrix */
+/* ============================================================================= */
+/** \addtogroup SAM4S_MATRIX AHB Bus Matrix */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Matrix hardware registers */
+typedef struct {
+  RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
+  RoReg Reserved1[12];
+  RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
+  RoReg Reserved2[11];
+  RwReg MATRIX_PRAS0;   /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
+  RoReg Reserved3[1];
+  RwReg MATRIX_PRAS1;   /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
+  RoReg Reserved4[1];
+  RwReg MATRIX_PRAS2;   /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
+  RoReg Reserved5[1];
+  RwReg MATRIX_PRAS3;   /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
+  RoReg Reserved6[1];
+  RwReg MATRIX_PRAS4;   /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
+  RoReg Reserved7[1];
+  RoReg Reserved8[27];
+  RwReg CCFG_SYSIO;     /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */
+  RoReg Reserved9[1];
+  RwReg CCFG_SMCNFCS;   /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */
+  RoReg Reserved10[49];
+  RwReg MATRIX_WPMR;    /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
+  RoReg MATRIX_WPSR;    /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
+} Matrix;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
+#define MATRIX_MCFG_ULBT_Pos 0
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
+/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[5]) Default Master Type */
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
+#define MATRIX_SCFG_ARBT_Pos 24
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
+#define MATRIX_PRAS0_M0PR_Pos 0
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
+#define MATRIX_PRAS0_M1PR_Pos 4
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
+#define MATRIX_PRAS0_M2PR_Pos 8
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
+#define MATRIX_PRAS0_M3PR_Pos 12
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
+#define MATRIX_PRAS0_M4PR_Pos 16
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
+#define MATRIX_PRAS1_M0PR_Pos 0
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
+#define MATRIX_PRAS1_M1PR_Pos 4
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
+#define MATRIX_PRAS1_M2PR_Pos 8
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
+#define MATRIX_PRAS1_M3PR_Pos 12
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
+#define MATRIX_PRAS1_M4PR_Pos 16
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
+#define MATRIX_PRAS2_M0PR_Pos 0
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
+#define MATRIX_PRAS2_M1PR_Pos 4
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
+#define MATRIX_PRAS2_M2PR_Pos 8
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
+#define MATRIX_PRAS2_M3PR_Pos 12
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
+#define MATRIX_PRAS2_M4PR_Pos 16
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
+#define MATRIX_PRAS3_M0PR_Pos 0
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
+#define MATRIX_PRAS3_M1PR_Pos 4
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
+#define MATRIX_PRAS3_M2PR_Pos 8
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
+#define MATRIX_PRAS3_M3PR_Pos 12
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
+#define MATRIX_PRAS3_M4PR_Pos 16
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
+#define MATRIX_PRAS4_M0PR_Pos 0
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
+#define MATRIX_PRAS4_M1PR_Pos 4
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
+#define MATRIX_PRAS4_M2PR_Pos 8
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
+#define MATRIX_PRAS4_M3PR_Pos 12
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
+#define MATRIX_PRAS4_M4PR_Pos 16
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */
+#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */
+#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */
+#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */
+#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */
+#define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */
+#define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */
+/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */
+#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */
+#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
+#define MATRIX_WPMR_WPKEY_Pos 8
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
+#define MATRIX_WPSR_WPVSRC_Pos 8
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM4S_MATRIX_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_pdc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_pdc.h
new file mode 100644
index 0000000..0244294
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_pdc.h
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_PDC_COMPONENT_
+#define _SAM4S_PDC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
+/* ============================================================================= */
+/** \addtogroup SAM4S_PDC Peripheral DMA Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pdc hardware registers */
+typedef struct {
+  RwReg PERIPH_RPR;  /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
+  RwReg PERIPH_RCR;  /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
+  RwReg PERIPH_TPR;  /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
+  RwReg PERIPH_TCR;  /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
+  RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
+  RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
+  RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
+  RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
+  WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
+  RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
+} Pdc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
+#define PERIPH_RPR_RXPTR_Pos 0
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
+#define PERIPH_RCR_RXCTR_Pos 0
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
+#define PERIPH_TPR_TXPTR_Pos 0
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
+#define PERIPH_TCR_TXCTR_Pos 0
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
+#define PERIPH_RNPR_RXNPTR_Pos 0
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
+#define PERIPH_RNCR_RXNCTR_Pos 0
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
+#define PERIPH_TNPR_TXNPTR_Pos 0
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
+#define PERIPH_TNCR_TXNCTR_Pos 0
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM4S_PDC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_pio.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_pio.h
new file mode 100644
index 0000000..484404d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_pio.h
@@ -0,0 +1,1642 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_PIO_COMPONENT_
+#define _SAM4S_PIO_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
+/* ============================================================================= */
+/** \addtogroup SAM4S_PIO Parallel Input/Output Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pio hardware registers */
+typedef struct {
+  WoReg PIO_PER;        /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
+  WoReg PIO_PDR;        /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
+  RoReg PIO_PSR;        /**< \brief (Pio Offset: 0x0008) PIO Status Register */
+  RoReg Reserved1[1];
+  WoReg PIO_OER;        /**< \brief (Pio Offset: 0x0010) Output Enable Register */
+  WoReg PIO_ODR;        /**< \brief (Pio Offset: 0x0014) Output Disable Register */
+  RoReg PIO_OSR;        /**< \brief (Pio Offset: 0x0018) Output Status Register */
+  RoReg Reserved2[1];
+  WoReg PIO_IFER;       /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
+  WoReg PIO_IFDR;       /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
+  RoReg PIO_IFSR;       /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
+  RoReg Reserved3[1];
+  WoReg PIO_SODR;       /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
+  WoReg PIO_CODR;       /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
+  RwReg PIO_ODSR;       /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
+  RoReg PIO_PDSR;       /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
+  WoReg PIO_IER;        /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
+  WoReg PIO_IDR;        /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
+  RoReg PIO_IMR;        /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
+  RoReg PIO_ISR;        /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
+  WoReg PIO_MDER;       /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
+  WoReg PIO_MDDR;       /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
+  RoReg PIO_MDSR;       /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
+  RoReg Reserved4[1];
+  WoReg PIO_PUDR;       /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
+  WoReg PIO_PUER;       /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
+  RoReg PIO_PUSR;       /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
+  RoReg Reserved5[1];
+  RwReg PIO_ABCDSR[2];  /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
+  RoReg Reserved6[2];
+  WoReg PIO_IFSCDR;     /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */
+  WoReg PIO_IFSCER;     /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */
+  RoReg PIO_IFSCSR;     /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */
+  RwReg PIO_SCDR;       /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
+  WoReg PIO_PPDDR;      /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
+  WoReg PIO_PPDER;      /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
+  RoReg PIO_PPDSR;      /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
+  RoReg Reserved7[1];
+  WoReg PIO_OWER;       /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
+  WoReg PIO_OWDR;       /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
+  RoReg PIO_OWSR;       /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
+  RoReg Reserved8[1];
+  WoReg PIO_AIMER;      /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
+  WoReg PIO_AIMDR;      /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */
+  RoReg PIO_AIMMR;      /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
+  RoReg Reserved9[1];
+  WoReg PIO_ESR;        /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
+  WoReg PIO_LSR;        /**< \brief (Pio Offset: 0x00C4) Level Select Register */
+  RoReg PIO_ELSR;       /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
+  RoReg Reserved10[1];
+  WoReg PIO_FELLSR;     /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */
+  WoReg PIO_REHLSR;     /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */
+  RoReg PIO_FRLHSR;     /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
+  RoReg Reserved11[1];
+  RoReg PIO_LOCKSR;     /**< \brief (Pio Offset: 0x00E0) Lock Status */
+  RwReg PIO_WPMR;       /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PIO_WPSR;       /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved12[5];
+  RwReg PIO_SCHMITT;    /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
+  RoReg Reserved13[19];
+  RwReg PIO_PCMR;       /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */
+  WoReg PIO_PCIER;      /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */
+  WoReg PIO_PCIDR;      /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */
+  RoReg PIO_PCIMR;      /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */
+  RoReg PIO_PCISR;      /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */
+  RoReg PIO_PCRHR;      /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */
+  RwReg PIO_RPR;        /**< \brief (Pio Offset: 0x168) Receive Pointer Register */
+  RwReg PIO_RCR;        /**< \brief (Pio Offset: 0x16C) Receive Counter Register */
+  RoReg Reserved14[2];
+  RwReg PIO_RNPR;       /**< \brief (Pio Offset: 0x178) Receive Next Pointer Register */
+  RwReg PIO_RNCR;       /**< \brief (Pio Offset: 0x17C) Receive Next Counter Register */
+  RoReg Reserved15[2];
+  WoReg PIO_PTCR;       /**< \brief (Pio Offset: 0x188) Transfer Control Register */
+  RoReg PIO_PTSR;       /**< \brief (Pio Offset: 0x18C) Transfer Status Register */
+} Pio;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */
+/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
+#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */
+/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
+#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */
+/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
+#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */
+/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
+#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
+#define PIO_SCDR_DIV_Pos 0
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR)  */
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
+/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
+#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */
+/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
+#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */
+#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */
+/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
+#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */
+#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */
+#define PIO_WPMR_WPKEY_Pos 8
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */
+#define PIO_WPSR_WPVSRC_Pos 8
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */
+/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
+#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT)  */
+#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT)  */
+/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */
+#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */
+#define PIO_PCMR_DSIZE_Pos 4
+#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */
+#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos)))
+#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */
+#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */
+#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */
+/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */
+#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */
+#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */
+#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */
+#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */
+/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */
+#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */
+#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */
+#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */
+#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */
+/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */
+#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */
+#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */
+#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */
+#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */
+/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */
+#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */
+#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */
+#define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */
+#define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */
+/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */
+#define PIO_PCRHR_RDATA_Pos 0
+#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */
+/* -------- PIO_RPR : (PIO Offset: 0x168) Receive Pointer Register -------- */
+#define PIO_RPR_RXPTR_Pos 0
+#define PIO_RPR_RXPTR_Msk (0xffffffffu << PIO_RPR_RXPTR_Pos) /**< \brief (PIO_RPR) Receive Pointer Register */
+#define PIO_RPR_RXPTR(value) ((PIO_RPR_RXPTR_Msk & ((value) << PIO_RPR_RXPTR_Pos)))
+/* -------- PIO_RCR : (PIO Offset: 0x16C) Receive Counter Register -------- */
+#define PIO_RCR_RXCTR_Pos 0
+#define PIO_RCR_RXCTR_Msk (0xffffu << PIO_RCR_RXCTR_Pos) /**< \brief (PIO_RCR) Receive Counter Register */
+#define PIO_RCR_RXCTR(value) ((PIO_RCR_RXCTR_Msk & ((value) << PIO_RCR_RXCTR_Pos)))
+/* -------- PIO_RNPR : (PIO Offset: 0x178) Receive Next Pointer Register -------- */
+#define PIO_RNPR_RXNPTR_Pos 0
+#define PIO_RNPR_RXNPTR_Msk (0xffffffffu << PIO_RNPR_RXNPTR_Pos) /**< \brief (PIO_RNPR) Receive Next Pointer */
+#define PIO_RNPR_RXNPTR(value) ((PIO_RNPR_RXNPTR_Msk & ((value) << PIO_RNPR_RXNPTR_Pos)))
+/* -------- PIO_RNCR : (PIO Offset: 0x17C) Receive Next Counter Register -------- */
+#define PIO_RNCR_RXNCTR_Pos 0
+#define PIO_RNCR_RXNCTR_Msk (0xffffu << PIO_RNCR_RXNCTR_Pos) /**< \brief (PIO_RNCR) Receive Next Counter */
+#define PIO_RNCR_RXNCTR(value) ((PIO_RNCR_RXNCTR_Msk & ((value) << PIO_RNCR_RXNCTR_Pos)))
+/* -------- PIO_PTCR : (PIO Offset: 0x188) Transfer Control Register -------- */
+#define PIO_PTCR_RXTEN (0x1u << 0) /**< \brief (PIO_PTCR) Receiver Transfer Enable */
+#define PIO_PTCR_RXTDIS (0x1u << 1) /**< \brief (PIO_PTCR) Receiver Transfer Disable */
+#define PIO_PTCR_TXTEN (0x1u << 8) /**< \brief (PIO_PTCR) Transmitter Transfer Enable */
+#define PIO_PTCR_TXTDIS (0x1u << 9) /**< \brief (PIO_PTCR) Transmitter Transfer Disable */
+/* -------- PIO_PTSR : (PIO Offset: 0x18C) Transfer Status Register -------- */
+#define PIO_PTSR_RXTEN (0x1u << 0) /**< \brief (PIO_PTSR) Receiver Transfer Enable */
+#define PIO_PTSR_TXTEN (0x1u << 8) /**< \brief (PIO_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM4S_PIO_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_pmc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_pmc.h
new file mode 100644
index 0000000..240b5d9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_pmc.h
@@ -0,0 +1,401 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_PMC_COMPONENT_
+#define _SAM4S_PMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Power Management Controller */
+/* ============================================================================= */
+/** \addtogroup SAM4S_PMC Power Management Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Pmc hardware registers */
+typedef struct {
+  WoReg PMC_SCER;      /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
+  WoReg PMC_SCDR;      /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
+  RoReg PMC_SCSR;      /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
+  RoReg Reserved1[1];
+  WoReg PMC_PCER0;     /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
+  WoReg PMC_PCDR0;     /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
+  RoReg PMC_PCSR0;     /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
+  RoReg Reserved2[1];
+  RwReg CKGR_MOR;      /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
+  RwReg CKGR_MCFR;     /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
+  RwReg CKGR_PLLAR;    /**< \brief (Pmc Offset: 0x0028) PLLA Register */
+  RwReg CKGR_PLLBR;    /**< \brief (Pmc Offset: 0x002C) PLLB Register */
+  RwReg PMC_MCKR;      /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
+  RoReg Reserved3[1];
+  RwReg PMC_USB;       /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
+  RoReg Reserved4[1];
+  RwReg PMC_PCK[3];    /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
+  RoReg Reserved5[5];
+  WoReg PMC_IER;       /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
+  WoReg PMC_IDR;       /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
+  RoReg PMC_SR;        /**< \brief (Pmc Offset: 0x0068) Status Register */
+  RoReg PMC_IMR;       /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
+  RwReg PMC_FSMR;      /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
+  RwReg PMC_FSPR;      /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
+  WoReg PMC_FOCR;      /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
+  RoReg Reserved6[26];
+  RwReg PMC_WPMR;      /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
+  RoReg PMC_WPSR;      /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
+  RoReg Reserved7[5];
+  WoReg PMC_PCER1;     /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
+  WoReg PMC_PCDR1;     /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
+  RoReg PMC_PCSR1;     /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
+  RoReg Reserved8[1];
+  RwReg PMC_OCR;       /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */
+} Pmc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
+#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
+#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
+#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
+#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
+#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
+#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
+#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command */
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
+#define CKGR_MOR_MOSCRCF_Pos 4
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
+#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
+#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
+#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
+#define CKGR_MOR_MOSCXTST_Pos 8
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
+#define CKGR_MOR_KEY_Pos 16
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
+#define CKGR_MCFR_MAINF_Pos 0
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
+#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
+#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
+#define CKGR_PLLAR_DIVA_Pos 0
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
+#define CKGR_PLLAR_PLLACOUNT_Pos 8
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
+#define CKGR_PLLAR_MULA_Pos 16
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
+/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */
+#define CKGR_PLLBR_DIVB_Pos 0
+#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */
+#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos)))
+#define CKGR_PLLBR_PLLBCOUNT_Pos 8
+#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */
+#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos)))
+#define CKGR_PLLBR_MULB_Pos 16
+#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */
+#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos)))
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
+#define PMC_MCKR_CSS_Pos 0
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
+#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
+#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
+#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
+#define   PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLBClock is selected */
+#define PMC_MCKR_PRES_Pos 4
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
+#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
+#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
+#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
+#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
+#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
+#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
+#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
+#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */
+#define PMC_MCKR_PLLBDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
+#define PMC_USB_USBDIV_Pos 8
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
+#define PMC_PCK_CSS_Pos 0
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
+#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
+#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
+#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
+#define   PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */
+#define   PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
+#define PMC_PCK_PRES_Pos 4
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
+#define   PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
+#define   PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
+#define   PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
+#define   PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
+#define   PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
+#define   PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
+#define   PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
+#define PMC_IER_LOCKB (0x1u << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
+#define PMC_IDR_LOCKB (0x1u << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
+#define PMC_SR_LOCKB (0x1u << 2) /**< \brief (PMC_SR) PLLB Lock Status */
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
+#define PMC_IMR_LOCKB (0x1u << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
+#define PMC_FSMR_FLPM_Pos 21
+#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low Power Mode */
+#define   PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby mode when system enters wait mode */
+#define   PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in deep power down mode when system enters wait mode */
+#define   PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) idle mode */
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
+#define PMC_WPMR_WPKEY_Pos 8
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
+#define PMC_WPSR_WPVSRC_Pos 8
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
+/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
+#define PMC_OCR_CAL4_Pos 0
+#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */
+#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
+#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */
+#define PMC_OCR_CAL8_Pos 8
+#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */
+#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
+#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */
+#define PMC_OCR_CAL12_Pos 16
+#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */
+#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
+#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */
+
+/*@}*/
+
+
+#endif /* _SAM4S_PMC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_pwm.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_pwm.h
new file mode 100644
index 0000000..0eea8d3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_pwm.h
@@ -0,0 +1,545 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_PWM_COMPONENT_
+#define _SAM4S_PWM_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
+/* ============================================================================= */
+/** \addtogroup SAM4S_PWM Pulse Width Modulation Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief PwmCh_num hardware registers */
+typedef struct {
+  RwReg      PWM_CMR;       /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
+  RwReg      PWM_CDTY;      /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
+  RwReg      PWM_CDTYUPD;   /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
+  RwReg      PWM_CPRD;      /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
+  RwReg      PWM_CPRDUPD;   /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
+  RwReg      PWM_CCNT;      /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
+  RwReg      PWM_DT;        /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
+  RwReg      PWM_DTUPD;     /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
+} PwmCh_num;
+/** \brief PwmCmp hardware registers */
+typedef struct {
+  RwReg      PWM_CMPV;      /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
+  RwReg      PWM_CMPVUPD;   /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
+  RwReg      PWM_CMPM;      /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
+  RwReg      PWM_CMPMUPD;   /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
+} PwmCmp;
+/** \brief Pwm hardware registers */
+#define PWMCMP_NUMBER 8
+#define PWMCH_NUM_NUMBER 4
+typedef struct {
+  RwReg      PWM_CLK;       /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
+  WoReg      PWM_ENA;       /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
+  WoReg      PWM_DIS;       /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
+  RoReg      PWM_SR;        /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
+  WoReg      PWM_IER1;      /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
+  WoReg      PWM_IDR1;      /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
+  RoReg      PWM_IMR1;      /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
+  RoReg      PWM_ISR1;      /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
+  RwReg      PWM_SCM;       /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      PWM_SCUC;      /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
+  RwReg      PWM_SCUP;      /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
+  WoReg      PWM_SCUPUPD;   /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
+  WoReg      PWM_IER2;      /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
+  WoReg      PWM_IDR2;      /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
+  RoReg      PWM_IMR2;      /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
+  RoReg      PWM_ISR2;      /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
+  RwReg      PWM_OOV;       /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
+  RwReg      PWM_OS;        /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
+  WoReg      PWM_OSS;       /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
+  WoReg      PWM_OSC;       /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
+  WoReg      PWM_OSSUPD;    /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
+  WoReg      PWM_OSCUPD;    /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
+  RwReg      PWM_FMR;       /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
+  RoReg      PWM_FSR;       /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
+  WoReg      PWM_FCR;       /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
+  RwReg      PWM_FPV;       /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
+  RwReg      PWM_FPE;       /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
+  RoReg      Reserved2[3];
+  RwReg      PWM_ELMR[2];   /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
+  RoReg      Reserved3[11];
+  RwReg      PWM_SMMR;      /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
+  RoReg      Reserved4[12];
+  WoReg      PWM_WPCR;      /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
+  RoReg      PWM_WPSR;      /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
+  RoReg      Reserved5[7];
+  RwReg      PWM_TPR;       /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
+  RwReg      PWM_TCR;       /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
+  RoReg      Reserved6[2];
+  RwReg      PWM_TNPR;      /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
+  RwReg      PWM_TNCR;      /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
+  WoReg      PWM_PTCR;      /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
+  RoReg      PWM_PTSR;      /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
+  RoReg      Reserved7[2];
+  PwmCmp     PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
+  RoReg      Reserved8[20];
+  PwmCh_num  PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
+} Pwm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
+#define PWM_CLK_DIVA_Pos 0
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
+#define PWM_CLK_PREA_Pos 8
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
+#define PWM_CLK_DIVB_Pos 16
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
+#define PWM_CLK_PREB_Pos 24
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
+#define PWM_SCM_UPDM_Pos 16
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
+#define   PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
+#define   PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
+#define PWM_SCM_PTRCS_Pos 21
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
+#define PWM_SCUP_UPR_Pos 0
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
+#define PWM_SCUP_UPRCNT_Pos 4
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
+#define PWM_SCUPUPD_UPRUPD_Pos 0
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
+#define PWM_FMR_FPOL_Pos 0
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
+#define PWM_FMR_FMOD_Pos 8
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
+#define PWM_FMR_FFIL_Pos 16
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
+#define PWM_FSR_FIV_Pos 0
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */
+#define PWM_FSR_FS_Pos 8
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
+#define PWM_FCR_FCLR_Pos 0
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
+#define PWM_FPE_FPE0_Pos 0
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
+#define PWM_FPE_FPE1_Pos 8
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
+#define PWM_FPE_FPE2_Pos 16
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
+#define PWM_FPE_FPE3_Pos 24
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
+#define PWM_WPCR_WPCMD_Pos 0
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
+#define PWM_WPCR_WPKEY_Pos 8
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
+#define PWM_WPSR_WPVSRC_Pos 16
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
+#define PWM_TPR_TXPTR_Pos 0
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
+#define PWM_TCR_TXCTR_Pos 0
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
+#define PWM_TNPR_TXNPTR_Pos 0
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
+#define PWM_TNCR_TXNCTR_Pos 0
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
+#define PWM_CMPV_CV_Pos 0
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
+#define PWM_CMPVUPD_CVUPD_Pos 0
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
+#define PWM_CMPM_CTR_Pos 4
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
+#define PWM_CMPM_CPR_Pos 8
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
+#define PWM_CMPM_CPRCNT_Pos 12
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
+#define PWM_CMPM_CUPR_Pos 16
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
+#define PWM_CMPM_CUPRCNT_Pos 20
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
+#define PWM_CMPMUPD_CTRUPD_Pos 4
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
+#define PWM_CMPMUPD_CPRUPD_Pos 8
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
+#define PWM_CMPMUPD_CUPRUPD_Pos 16
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
+#define PWM_CMR_CPRE_Pos 0
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
+#define   PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
+#define   PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
+#define   PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
+#define   PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
+#define   PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
+#define   PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
+#define   PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
+#define   PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
+#define   PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
+#define   PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
+#define   PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
+#define   PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
+#define   PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
+#define PWM_CDTY_CDTY_Pos 0
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
+#define PWM_CDTYUPD_CDTYUPD_Pos 0
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
+#define PWM_CPRD_CPRD_Pos 0
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
+#define PWM_CPRDUPD_CPRDUPD_Pos 0
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
+#define PWM_CCNT_CNT_Pos 0
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
+#define PWM_DT_DTH_Pos 0
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
+#define PWM_DT_DTL_Pos 16
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
+#define PWM_DTUPD_DTHUPD_Pos 0
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
+#define PWM_DTUPD_DTLUPD_Pos 16
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM4S_PWM_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_rstc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_rstc.h
new file mode 100644
index 0000000..396d876
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_rstc.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_RSTC_COMPONENT_
+#define _SAM4S_RSTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Reset Controller */
+/* ============================================================================= */
+/** \addtogroup SAM4S_RSTC Reset Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rstc hardware registers */
+typedef struct {
+  WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
+  RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
+  RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
+} Rstc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
+#define RSTC_CR_KEY_Pos 24
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
+#define RSTC_SR_RSTTYP_Pos 8
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_Pos 8
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
+#define RSTC_MR_KEY_Pos 24
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM4S_RSTC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_rtc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_rtc.h
new file mode 100644
index 0000000..705bcf5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_rtc.h
@@ -0,0 +1,219 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_RTC_COMPONENT_
+#define _SAM4S_RTC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Clock */
+/* ============================================================================= */
+/** \addtogroup SAM4S_RTC Real-time Clock */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtc hardware registers */
+typedef struct {
+  RwReg RTC_CR;     /**< \brief (Rtc Offset: 0x00) Control Register */
+  RwReg RTC_MR;     /**< \brief (Rtc Offset: 0x04) Mode Register */
+  RwReg RTC_TIMR;   /**< \brief (Rtc Offset: 0x08) Time Register */
+  RwReg RTC_CALR;   /**< \brief (Rtc Offset: 0x0C) Calendar Register */
+  RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
+  RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
+  RoReg RTC_SR;     /**< \brief (Rtc Offset: 0x18) Status Register */
+  WoReg RTC_SCCR;   /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
+  WoReg RTC_IER;    /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
+  WoReg RTC_IDR;    /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
+  RoReg RTC_IMR;    /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
+  RoReg RTC_VER;    /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
+#define RTC_CR_TIMEVSEL_Pos 8
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
+#define   RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
+#define   RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
+#define   RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
+#define   RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
+#define RTC_CR_CALEVSEL_Pos 16
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
+#define   RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
+#define   RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
+#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */
+#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */
+#define RTC_MR_CORRECTION_Pos 8
+#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR)  */
+#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))
+#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */
+#define RTC_MR_OUT0_Pos 16
+#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 Output Source Selection */
+#define   RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) no waveform, stuck at '0' */
+#define   RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */
+#define   RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */
+#define   RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */
+#define   RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */
+#define   RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) output toggles when alarm flag rises */
+#define   RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) output is a copy of the alarm flag */
+#define   RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) duty cycle programmable pulse */
+#define RTC_MR_OUT1_Pos 20
+#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */
+#define   RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) no waveform, stuck at '0' */
+#define   RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */
+#define   RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */
+#define   RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */
+#define   RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */
+#define   RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) output toggles when alarm flag rises */
+#define   RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) output is a copy of the alarm flag */
+#define   RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) duty cycle programmable pulse */
+#define RTC_MR_THIGH_Pos 24
+#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */
+#define   RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */
+#define   RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */
+#define   RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */
+#define   RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 \xb5 s */
+#define   RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 \xb5 s */
+#define   RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 \xb5 s */
+#define   RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 \xb5 s */
+#define   RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 \xb5 s */
+#define RTC_MR_TPERIOD_Pos 28
+#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */
+#define   RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */
+#define   RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */
+#define   RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */
+#define   RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
+#define RTC_TIMR_SEC_Pos 0
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
+#define RTC_TIMR_MIN_Pos 8
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
+#define RTC_TIMR_HOUR_Pos 16
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
+#define RTC_CALR_CENT_Pos 0
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
+#define RTC_CALR_YEAR_Pos 8
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
+#define RTC_CALR_MONTH_Pos 16
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
+#define RTC_CALR_DAY_Pos 21
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
+#define RTC_CALR_DATE_Pos 24
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
+#define RTC_TIMALR_SEC_Pos 0
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
+#define RTC_TIMALR_MIN_Pos 8
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
+#define RTC_TIMALR_HOUR_Pos 16
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
+#define RTC_CALALR_MONTH_Pos 16
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
+#define RTC_CALALR_DATE_Pos 24
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
+#define   RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */
+#define   RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
+#define   RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */
+#define   RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
+#define   RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */
+#define   RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
+#define   RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */
+#define   RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
+#define   RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */
+#define   RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */
+#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */
+#define   RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of RTC_SR. */
+#define   RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
+#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
+#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
+#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
+
+/*@}*/
+
+
+#endif /* _SAM4S_RTC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_rtt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_rtt.h
new file mode 100644
index 0000000..0c1ea28
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_rtt.h
@@ -0,0 +1,69 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_RTT_COMPONENT_
+#define _SAM4S_RTT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Real-time Timer */
+/* ============================================================================= */
+/** \addtogroup SAM4S_RTT Real-time Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Rtt hardware registers */
+typedef struct {
+  RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
+  RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
+  RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
+  RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
+} Rtt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
+#define RTT_MR_RTPRES_Pos 0
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
+#define RTT_AR_ALMV_Pos 0
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
+#define RTT_VR_CRTV_Pos 0
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
+
+/*@}*/
+
+
+#endif /* _SAM4S_RTT_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_smc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_smc.h
new file mode 100644
index 0000000..597fce6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_smc.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_SMC_COMPONENT_
+#define _SAM4S_SMC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Static Memory Controller */
+/* ============================================================================= */
+/** \addtogroup SAM4S_SMC Static Memory Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief SmcCs_number hardware registers */
+typedef struct {
+  RwReg         SMC_SETUP;        /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
+  RwReg         SMC_PULSE;        /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
+  RwReg         SMC_CYCLE;        /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
+  RwReg         SMC_MODE;         /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */
+} SmcCs_number;
+/** \brief Smc hardware registers */
+#define SMCCS_NUMBER_NUMBER 5
+typedef struct {
+  SmcCs_number  SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */
+  RoReg         Reserved1[12];
+  RwReg         SMC_OCMS;         /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */
+  WoReg         SMC_KEY1;         /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */
+  WoReg         SMC_KEY2;         /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */
+  RoReg         Reserved2[22];
+  RwReg         SMC_WPMR;         /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */
+  RoReg         SMC_WPSR;         /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */
+} Smc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
+#define SMC_SETUP_NWE_SETUP_Pos 0
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
+#define SMC_SETUP_NRD_SETUP_Pos 16
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
+#define SMC_PULSE_NWE_PULSE_Pos 0
+#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
+#define SMC_PULSE_NRD_PULSE_Pos 16
+#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
+#define SMC_CYCLE_NWE_CYCLE_Pos 0
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
+#define SMC_CYCLE_NRD_CYCLE_Pos 16
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE)  */
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE)  */
+#define SMC_MODE_EXNW_MODE_Pos 4
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
+#define   SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
+#define   SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
+#define   SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
+#define SMC_MODE_DBW_Pos 12
+#define SMC_MODE_DBW_Msk (0x3u << SMC_MODE_DBW_Pos) /**< \brief (SMC_MODE) Data Bus Width */
+#define   SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
+#define   SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
+#define   SMC_MODE_DBW_32_BIT (0x2u << 12) /**< \brief (SMC_MODE) 32-bit bus */
+#define SMC_MODE_TDF_CYCLES_Pos 16
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
+#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */
+#define SMC_MODE_PS_Pos 28
+#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */
+#define   SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */
+#define   SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */
+#define   SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */
+#define   SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */
+/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
+#define SMC_OCMS_CS0SE (0x1u << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS1SE (0x1u << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS2SE (0x1u << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+#define SMC_OCMS_CS3SE (0x1u << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */
+/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */
+#define SMC_KEY1_KEY1_Pos 0
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
+/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */
+#define SMC_KEY2_KEY2_Pos 0
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
+/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */
+#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */
+#define SMC_WPMR_WPKEY_Pos 8
+#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */
+#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
+/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */
+#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */
+#define SMC_WPSR_WPVSRC_Pos 8
+#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */
+
+/*@}*/
+
+
+#endif /* _SAM4S_SMC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_spi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_spi.h
new file mode 100644
index 0000000..e73e789
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_spi.h
@@ -0,0 +1,226 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_SPI_COMPONENT_
+#define _SAM4S_SPI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
+/* ============================================================================= */
+/** \addtogroup SAM4S_SPI Serial Peripheral Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Spi hardware registers */
+typedef struct {
+  WoReg SPI_CR;        /**< \brief (Spi Offset: 0x00) Control Register */
+  RwReg SPI_MR;        /**< \brief (Spi Offset: 0x04) Mode Register */
+  RoReg SPI_RDR;       /**< \brief (Spi Offset: 0x08) Receive Data Register */
+  WoReg SPI_TDR;       /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
+  RoReg SPI_SR;        /**< \brief (Spi Offset: 0x10) Status Register */
+  WoReg SPI_IER;       /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
+  WoReg SPI_IDR;       /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
+  RoReg SPI_IMR;       /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
+  RoReg Reserved1[4];
+  RwReg SPI_CSR[4];    /**< \brief (Spi Offset: 0x30) Chip Select Register */
+  RoReg Reserved2[41];
+  RwReg SPI_WPMR;      /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
+  RoReg SPI_WPSR;      /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
+  RoReg Reserved3[5];
+  RwReg SPI_RPR;       /**< \brief (Spi Offset: 0x100) Receive Pointer Register */
+  RwReg SPI_RCR;       /**< \brief (Spi Offset: 0x104) Receive Counter Register */
+  RwReg SPI_TPR;       /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */
+  RwReg SPI_TCR;       /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */
+  RwReg SPI_RNPR;      /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */
+  RwReg SPI_RNCR;      /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */
+  RwReg SPI_TNPR;      /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg SPI_TNCR;      /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg SPI_PTCR;      /**< \brief (Spi Offset: 0x120) Transfer Control Register */
+  RoReg SPI_PTSR;      /**< \brief (Spi Offset: 0x124) Transfer Status Register */
+} Spi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
+#define SPI_MR_PCS_Pos 16
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
+#define SPI_MR_DLYBCS_Pos 24
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
+#define SPI_RDR_RD_Pos 0
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
+#define SPI_RDR_PCS_Pos 16
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
+#define SPI_TDR_TD_Pos 0
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
+#define SPI_TDR_PCS_Pos 16
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
+#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */
+#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */
+#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */
+#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
+#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */
+#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */
+#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */
+#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
+#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */
+#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */
+#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */
+#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
+#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */
+#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */
+#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */
+#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
+#define SPI_CSR_BITS_Pos 4
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
+#define   SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
+#define   SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
+#define   SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
+#define   SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
+#define   SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
+#define   SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
+#define   SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
+#define   SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
+#define   SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
+#define SPI_CSR_SCBR_Pos 8
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
+#define SPI_CSR_DLYBS_Pos 16
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
+#define SPI_CSR_DLYBCT_Pos 24
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */
+#define SPI_WPMR_WPKEY_Pos 8
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */
+#define SPI_WPSR_WPVSRC_Pos 8
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */
+/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */
+#define SPI_RPR_RXPTR_Pos 0
+#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */
+#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))
+/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */
+#define SPI_RCR_RXCTR_Pos 0
+#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */
+#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))
+/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */
+#define SPI_TPR_TXPTR_Pos 0
+#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */
+#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))
+/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */
+#define SPI_TCR_TXCTR_Pos 0
+#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */
+#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))
+/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */
+#define SPI_RNPR_RXNPTR_Pos 0
+#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */
+#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))
+/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */
+#define SPI_RNCR_RXNCTR_Pos 0
+#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */
+#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))
+/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define SPI_TNPR_TXNPTR_Pos 0
+#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */
+#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))
+/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define SPI_TNCR_TXNCTR_Pos 0
+#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */
+#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))
+/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */
+#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */
+#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */
+#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */
+#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */
+/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */
+#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */
+#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM4S_SPI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_ssc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_ssc.h
new file mode 100644
index 0000000..6200498
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_ssc.h
@@ -0,0 +1,337 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_SSC_COMPONENT_
+#define _SAM4S_SSC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
+/* ============================================================================= */
+/** \addtogroup SAM4S_SSC Synchronous Serial Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Ssc hardware registers */
+typedef struct {
+  WoReg SSC_CR;        /**< \brief (Ssc Offset: 0x0) Control Register */
+  RwReg SSC_CMR;       /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
+  RoReg Reserved1[2];
+  RwReg SSC_RCMR;      /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
+  RwReg SSC_RFMR;      /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
+  RwReg SSC_TCMR;      /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
+  RwReg SSC_TFMR;      /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
+  RoReg SSC_RHR;       /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
+  WoReg SSC_THR;       /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
+  RoReg Reserved2[2];
+  RoReg SSC_RSHR;      /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
+  RwReg SSC_TSHR;      /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
+  RwReg SSC_RC0R;      /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
+  RwReg SSC_RC1R;      /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
+  RoReg SSC_SR;        /**< \brief (Ssc Offset: 0x40) Status Register */
+  WoReg SSC_IER;       /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
+  WoReg SSC_IDR;       /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
+  RoReg SSC_IMR;       /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
+  RoReg Reserved3[37];
+  RwReg SSC_WPMR;      /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
+  RoReg SSC_WPSR;      /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[5];
+  RwReg SSC_RPR;       /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */
+  RwReg SSC_RCR;       /**< \brief (Ssc Offset: 0x104) Receive Counter Register */
+  RwReg SSC_TPR;       /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */
+  RwReg SSC_TCR;       /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */
+  RwReg SSC_RNPR;      /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */
+  RwReg SSC_RNCR;      /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */
+  RwReg SSC_TNPR;      /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */
+  RwReg SSC_TNCR;      /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */
+  WoReg SSC_PTCR;      /**< \brief (Ssc Offset: 0x120) Transfer Control Register */
+  RoReg SSC_PTSR;      /**< \brief (Ssc Offset: 0x124) Transfer Status Register */
+} Ssc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
+#define SSC_CMR_DIV_Pos 0
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
+#define SSC_RCMR_CKS_Pos 0
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
+#define   SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
+#define   SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
+#define   SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
+#define SSC_RCMR_CKO_Pos 2
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
+#define   SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
+#define SSC_RCMR_CKG_Pos 6
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
+#define   SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
+#define   SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
+#define   SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
+#define SSC_RCMR_START_Pos 8
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
+#define   SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
+#define   SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
+#define   SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
+#define   SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
+#define   SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
+#define   SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
+#define   SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
+#define   SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
+#define   SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
+#define SSC_RCMR_STTDLY_Pos 16
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
+#define SSC_RCMR_PERIOD_Pos 24
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
+#define SSC_RFMR_DATLEN_Pos 0
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
+#define SSC_RFMR_DATNB_Pos 8
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
+#define SSC_RFMR_FSLEN_Pos 16
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
+#define SSC_RFMR_FSOS_Pos 20
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
+#define   SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
+#define   SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
+#define   SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
+#define   SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
+#define   SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
+#define   SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
+#define   SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
+#define   SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
+#define SSC_RFMR_FSLEN_EXT_Pos 28
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
+#define SSC_TCMR_CKS_Pos 0
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
+#define   SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
+#define   SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
+#define   SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
+#define SSC_TCMR_CKO_Pos 2
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
+#define   SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
+#define   SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
+#define SSC_TCMR_CKG_Pos 6
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
+#define   SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
+#define   SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
+#define   SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
+#define SSC_TCMR_START_Pos 8
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
+#define   SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
+#define   SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
+#define   SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
+#define   SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
+#define   SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
+#define   SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
+#define   SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
+#define   SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
+#define   SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
+#define SSC_TCMR_STTDLY_Pos 16
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
+#define SSC_TCMR_PERIOD_Pos 24
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
+#define SSC_TFMR_DATLEN_Pos 0
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
+#define SSC_TFMR_DATNB_Pos 8
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
+#define SSC_TFMR_FSLEN_Pos 16
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
+#define SSC_TFMR_FSOS_Pos 20
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
+#define   SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
+#define   SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
+#define   SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
+#define   SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
+#define   SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
+#define   SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
+#define   SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
+#define   SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
+#define SSC_TFMR_FSLEN_EXT_Pos 28
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
+#define SSC_RHR_RDAT_Pos 0
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
+#define SSC_THR_TDAT_Pos 0
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
+#define SSC_RSHR_RSDAT_Pos 0
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
+#define SSC_TSHR_TSDAT_Pos 0
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
+#define SSC_RC0R_CP0_Pos 0
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
+#define SSC_RC1R_CP1_Pos 0
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
+#define SSC_SR_ENDTX (0x1u << 2) /**< \brief (SSC_SR) End of Transmission */
+#define SSC_SR_TXBUFE (0x1u << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
+#define SSC_SR_ENDRX (0x1u << 6) /**< \brief (SSC_SR) End of Reception */
+#define SSC_SR_RXBUFF (0x1u << 7) /**< \brief (SSC_SR) Receive Buffer Full */
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
+#define SSC_IER_ENDTX (0x1u << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */
+#define SSC_IER_TXBUFE (0x1u << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
+#define SSC_IER_ENDRX (0x1u << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */
+#define SSC_IER_RXBUFF (0x1u << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
+#define SSC_IDR_ENDTX (0x1u << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */
+#define SSC_IDR_TXBUFE (0x1u << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
+#define SSC_IDR_ENDRX (0x1u << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */
+#define SSC_IDR_RXBUFF (0x1u << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
+#define SSC_IMR_ENDTX (0x1u << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */
+#define SSC_IMR_TXBUFE (0x1u << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
+#define SSC_IMR_ENDRX (0x1u << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */
+#define SSC_IMR_RXBUFF (0x1u << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
+#define SSC_WPMR_WPKEY_Pos 8
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
+#define SSC_WPSR_WPVSRC_Pos 8
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
+/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */
+#define SSC_RPR_RXPTR_Pos 0
+#define SSC_RPR_RXPTR_Msk (0xffffffffu << SSC_RPR_RXPTR_Pos) /**< \brief (SSC_RPR) Receive Pointer Register */
+#define SSC_RPR_RXPTR(value) ((SSC_RPR_RXPTR_Msk & ((value) << SSC_RPR_RXPTR_Pos)))
+/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */
+#define SSC_RCR_RXCTR_Pos 0
+#define SSC_RCR_RXCTR_Msk (0xffffu << SSC_RCR_RXCTR_Pos) /**< \brief (SSC_RCR) Receive Counter Register */
+#define SSC_RCR_RXCTR(value) ((SSC_RCR_RXCTR_Msk & ((value) << SSC_RCR_RXCTR_Pos)))
+/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */
+#define SSC_TPR_TXPTR_Pos 0
+#define SSC_TPR_TXPTR_Msk (0xffffffffu << SSC_TPR_TXPTR_Pos) /**< \brief (SSC_TPR) Transmit Counter Register */
+#define SSC_TPR_TXPTR(value) ((SSC_TPR_TXPTR_Msk & ((value) << SSC_TPR_TXPTR_Pos)))
+/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */
+#define SSC_TCR_TXCTR_Pos 0
+#define SSC_TCR_TXCTR_Msk (0xffffu << SSC_TCR_TXCTR_Pos) /**< \brief (SSC_TCR) Transmit Counter Register */
+#define SSC_TCR_TXCTR(value) ((SSC_TCR_TXCTR_Msk & ((value) << SSC_TCR_TXCTR_Pos)))
+/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */
+#define SSC_RNPR_RXNPTR_Pos 0
+#define SSC_RNPR_RXNPTR_Msk (0xffffffffu << SSC_RNPR_RXNPTR_Pos) /**< \brief (SSC_RNPR) Receive Next Pointer */
+#define SSC_RNPR_RXNPTR(value) ((SSC_RNPR_RXNPTR_Msk & ((value) << SSC_RNPR_RXNPTR_Pos)))
+/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */
+#define SSC_RNCR_RXNCTR_Pos 0
+#define SSC_RNCR_RXNCTR_Msk (0xffffu << SSC_RNCR_RXNCTR_Pos) /**< \brief (SSC_RNCR) Receive Next Counter */
+#define SSC_RNCR_RXNCTR(value) ((SSC_RNCR_RXNCTR_Msk & ((value) << SSC_RNCR_RXNCTR_Pos)))
+/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */
+#define SSC_TNPR_TXNPTR_Pos 0
+#define SSC_TNPR_TXNPTR_Msk (0xffffffffu << SSC_TNPR_TXNPTR_Pos) /**< \brief (SSC_TNPR) Transmit Next Pointer */
+#define SSC_TNPR_TXNPTR(value) ((SSC_TNPR_TXNPTR_Msk & ((value) << SSC_TNPR_TXNPTR_Pos)))
+/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */
+#define SSC_TNCR_TXNCTR_Pos 0
+#define SSC_TNCR_TXNCTR_Msk (0xffffu << SSC_TNCR_TXNCTR_Pos) /**< \brief (SSC_TNCR) Transmit Counter Next */
+#define SSC_TNCR_TXNCTR(value) ((SSC_TNCR_TXNCTR_Msk & ((value) << SSC_TNCR_TXNCTR_Pos)))
+/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */
+#define SSC_PTCR_RXTEN (0x1u << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */
+#define SSC_PTCR_RXTDIS (0x1u << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */
+#define SSC_PTCR_TXTEN (0x1u << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */
+#define SSC_PTCR_TXTDIS (0x1u << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */
+/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */
+#define SSC_PTSR_RXTEN (0x1u << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */
+#define SSC_PTSR_TXTEN (0x1u << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM4S_SSC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_supc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_supc.h
new file mode 100644
index 0000000..266a770
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_supc.h
@@ -0,0 +1,322 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_SUPC_COMPONENT_
+#define _SAM4S_SUPC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Supply Controller */
+/* ============================================================================= */
+/** \addtogroup SAM4S_SUPC Supply Controller */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Supc hardware registers */
+typedef struct {
+  WoReg SUPC_CR;   /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
+  RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
+  RwReg SUPC_MR;   /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
+  RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
+  RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
+  RoReg SUPC_SR;   /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
+} Supc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
+#define   SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
+#define   SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
+#define   SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
+#define SUPC_CR_KEY_Pos 24
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
+#define SUPC_SMMR_SMTH_Pos 0
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
+#define   SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
+#define   SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
+#define   SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
+#define   SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
+#define   SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
+#define   SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
+#define   SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
+#define   SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
+#define   SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
+#define   SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
+#define   SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
+#define   SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
+#define   SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
+#define   SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
+#define   SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
+#define   SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
+#define SUPC_SMMR_SMSMPL_Pos 8
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
+#define   SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
+#define   SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
+#define   SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
+#define   SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
+#define   SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
+#define   SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
+#define   SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
+#define   SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
+#define   SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
+#define   SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
+#define   SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
+#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */
+#define   SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */
+#define   SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
+#define   SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
+#define   SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
+#define SUPC_MR_KEY_Pos 24
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
+#define   SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
+#define   SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
+#define   SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
+#define   SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
+#define   SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
+#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP0 */
+#define   SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is not connected with low power debouncer. */
+#define   SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is connected with low power debouncer and can force a core wake up. */
+#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP1 */
+#define   SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) the WKUP1input pin is not connected with low power debouncer. */
+#define   SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) the WKUP1 input pin is connected with low power debouncer and can force a core wake up. */
+#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low power Debouncer Clear */
+#define   SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) a low power debounce event does not create an immediate clear on first half GPBR registers. */
+#define   SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers. */
+#define SUPC_WUMR_WKUPDBC_Pos 12
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
+#define   SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
+#define   SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
+#define   SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
+#define SUPC_WUMR_LPDBC_Pos 16
+#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low Power DeBounCer Period */
+#define   SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low power debouncer. */
+#define   SUPC_WUMR_LPDBC_2_RTCOUT0 (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 2 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_3_RTCOUT0 (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 3 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_4_RTCOUT0 (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 4 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_5_RTCOUT0 (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 5 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_6_RTCOUT0 (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 6 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_7_RTCOUT0 (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 7 RTCOUT0 periods */
+#define   SUPC_WUMR_LPDBC_8_RTCOUT0 (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 8 RTCOUT0 periods */
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
+#define   SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
+#define   SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
+#define   SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
+#define   SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
+#define   SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
+#define   SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
+#define   SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
+#define   SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
+#define   SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
+#define   SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
+#define   SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
+#define   SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
+#define   SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
+#define   SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
+#define   SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
+#define   SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
+#define   SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Type 0 */
+#define   SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Type 1 */
+#define   SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Type 2 */
+#define   SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Type 3 */
+#define   SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Type 4 */
+#define   SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Type 5 */
+#define   SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Type 6 */
+#define   SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Type 7 */
+#define   SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Type 8 */
+#define   SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Type 9 */
+#define   SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Type 10 */
+#define   SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Type 11 */
+#define   SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Type 12 */
+#define   SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Type 13 */
+#define   SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Type 14 */
+#define   SUPC_WUIR_WKUPT14_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT14_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Type 15 */
+#define   SUPC_WUIR_WKUPT15_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */
+#define   SUPC_WUIR_WKUPT15_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
+#define   SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
+#define   SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
+#define   SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
+#define   SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
+#define   SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define   SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
+#define   SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
+#define   SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
+#define   SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */
+#define   SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
+#define   SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
+#define   SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
+#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP0 */
+#define   SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP1 */
+#define   SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
+#define   SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
+#define   SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
+#define   SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
+#define   SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
+#define   SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
+#define   SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
+#define   SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
+#define   SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
+#define   SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
+#define   SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
+#define   SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
+#define   SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
+#define   SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
+#define   SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
+#define   SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
+#define   SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
+#define   SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
+#define   SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
+
+/*@}*/
+
+
+#endif /* _SAM4S_SUPC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_tc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_tc.h
new file mode 100644
index 0000000..06e661a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_tc.h
@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_TC_COMPONENT_
+#define _SAM4S_TC_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Timer Counter */
+/* ============================================================================= */
+/** \addtogroup SAM4S_TC Timer Counter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief TcChannel hardware registers */
+typedef struct {
+  RwReg      TC_CCR;        /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
+  RwReg      TC_CMR;        /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
+  RwReg      TC_SMMR;       /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
+  RoReg      Reserved1[1];
+  RwReg      TC_CV;         /**< \brief (TcChannel Offset: 0x10) Counter Value */
+  RwReg      TC_RA;         /**< \brief (TcChannel Offset: 0x14) Register A */
+  RwReg      TC_RB;         /**< \brief (TcChannel Offset: 0x18) Register B */
+  RwReg      TC_RC;         /**< \brief (TcChannel Offset: 0x1C) Register C */
+  RwReg      TC_SR;         /**< \brief (TcChannel Offset: 0x20) Status Register */
+  RwReg      TC_IER;        /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
+  RwReg      TC_IDR;        /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
+  RwReg      TC_IMR;        /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
+  RoReg      Reserved2[4];
+} TcChannel;
+/** \brief Tc hardware registers */
+#define TCCHANNEL_NUMBER 3
+typedef struct {
+  TcChannel  TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
+  WoReg      TC_BCR;        /**< \brief (Tc Offset: 0xC0) Block Control Register */
+  RwReg      TC_BMR;        /**< \brief (Tc Offset: 0xC4) Block Mode Register */
+  WoReg      TC_QIER;       /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
+  WoReg      TC_QIDR;       /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
+  RoReg      TC_QIMR;       /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
+  RoReg      TC_QISR;       /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
+  RwReg      TC_FMR;        /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
+  RoReg      Reserved1[2];
+  RwReg      TC_WPMR;       /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
+#define TC_CMR_TCCLKS_Pos 0
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
+#define   TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
+#define   TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
+#define   TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
+#define   TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
+#define TC_CMR_BURST_Pos 4
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
+#define   TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
+#define   TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
+#define TC_CMR_ETRGEDG_Pos 8
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
+#define   TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
+#define   TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
+#define TC_CMR_LDRA_Pos 16
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
+#define   TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_LDRB_Pos 18
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
+#define   TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
+#define   TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
+#define   TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
+#define TC_CMR_EEVTEDG_Pos 8
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
+#define   TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
+#define   TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
+#define   TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
+#define   TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
+#define TC_CMR_EEVT_Pos 10
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
+#define   TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
+#define   TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
+#define   TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
+#define   TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
+#define TC_CMR_WAVSEL_Pos 13
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
+#define   TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
+#define   TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
+#define TC_CMR_ACPA_Pos 16
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
+#define   TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ACPC_Pos 18
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
+#define   TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_AEEVT_Pos 20
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
+#define   TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
+#define   TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_ASWTRG_Pos 22
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
+#define   TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
+#define   TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPB_Pos 24
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
+#define   TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BCPC_Pos 26
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
+#define   TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BEEVT_Pos 28
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
+#define   TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
+#define TC_CMR_BSWTRG_Pos 30
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
+#define   TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
+#define   TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
+#define   TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
+#define   TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
+#define TC_CV_CV_Pos 0
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
+#define TC_RA_RA_Pos 0
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
+#define TC_RB_RB_Pos 0
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
+#define TC_RC_RC_Pos 0
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
+#define TC_BMR_TC0XC0S_Pos 0
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
+#define   TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
+#define   TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
+#define   TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
+#define TC_BMR_TC1XC1S_Pos 2
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
+#define   TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
+#define   TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
+#define   TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
+#define TC_BMR_TC2XC2S_Pos 4
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
+#define   TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
+#define   TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
+#define   TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR)  */
+#define TC_BMR_MAXFILT_Pos 20
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) DIRection */
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
+#define TC_WPMR_WPKEY_Pos 8
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
+
+/*@}*/
+
+
+#endif /* _SAM4S_TC_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_twi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_twi.h
new file mode 100644
index 0000000..a8dbdc5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_twi.h
@@ -0,0 +1,217 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_TWI_COMPONENT_
+#define _SAM4S_TWI_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Two-wire Interface */
+/* ============================================================================= */
+/** \addtogroup SAM4S_TWI Two-wire Interface */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Twi hardware registers */
+typedef struct {
+  WoReg TWI_CR;        /**< \brief (Twi Offset: 0x00) Control Register */
+  RwReg TWI_MMR;       /**< \brief (Twi Offset: 0x04) Master Mode Register */
+  RwReg TWI_SMR;       /**< \brief (Twi Offset: 0x08) Slave Mode Register */
+  RwReg TWI_IADR;      /**< \brief (Twi Offset: 0x0C) Internal Address Register */
+  RwReg TWI_CWGR;      /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
+  RoReg Reserved1[3];
+  RoReg TWI_SR;        /**< \brief (Twi Offset: 0x20) Status Register */
+  WoReg TWI_IER;       /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
+  WoReg TWI_IDR;       /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
+  RoReg TWI_IMR;       /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
+  RoReg TWI_RHR;       /**< \brief (Twi Offset: 0x30) Receive Holding Register */
+  WoReg TWI_THR;       /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
+  RoReg Reserved2[50];
+  RwReg TWI_RPR;       /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
+  RwReg TWI_RCR;       /**< \brief (Twi Offset: 0x104) Receive Counter Register */
+  RwReg TWI_TPR;       /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
+  RwReg TWI_TCR;       /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
+  RwReg TWI_RNPR;      /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
+  RwReg TWI_RNCR;      /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
+  RwReg TWI_TNPR;      /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
+  RwReg TWI_TNCR;      /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
+  WoReg TWI_PTCR;      /**< \brief (Twi Offset: 0x120) Transfer Control Register */
+  RoReg TWI_PTSR;      /**< \brief (Twi Offset: 0x124) Transfer Status Register */
+} Twi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
+#define TWI_MMR_IADRSZ_Pos 8
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
+#define   TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
+#define   TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
+#define   TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
+#define   TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
+#define TWI_MMR_DADR_Pos 16
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
+#define TWI_SMR_SADR_Pos 16
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
+#define TWI_IADR_IADR_Pos 0
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
+#define TWI_CWGR_CLDIV_Pos 0
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
+#define TWI_CWGR_CHDIV_Pos 8
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
+#define TWI_CWGR_CKDIV_Pos 16
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
+#define TWI_RHR_RXDATA_Pos 0
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
+#define TWI_THR_TXDATA_Pos 0
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
+#define TWI_RPR_RXPTR_Pos 0
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
+#define TWI_RCR_RXCTR_Pos 0
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
+#define TWI_TPR_TXPTR_Pos 0
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
+#define TWI_TCR_TXCTR_Pos 0
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
+#define TWI_RNPR_RXNPTR_Pos 0
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
+#define TWI_RNCR_RXNCTR_Pos 0
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
+#define TWI_TNPR_TXNPTR_Pos 0
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
+#define TWI_TNCR_TXNCTR_Pos 0
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM4S_TWI_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_uart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_uart.h
new file mode 100644
index 0000000..3765bea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_uart.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_UART_COMPONENT_
+#define _SAM4S_UART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM4S_UART Universal Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Uart hardware registers */
+typedef struct {
+  WoReg UART_CR;       /**< \brief (Uart Offset: 0x0000) Control Register */
+  RwReg UART_MR;       /**< \brief (Uart Offset: 0x0004) Mode Register */
+  WoReg UART_IER;      /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
+  WoReg UART_IDR;      /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
+  RoReg UART_IMR;      /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
+  RoReg UART_SR;       /**< \brief (Uart Offset: 0x0014) Status Register */
+  RoReg UART_RHR;      /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
+  WoReg UART_THR;      /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
+  RwReg UART_BRGR;     /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
+  RoReg Reserved1[55];
+  RwReg UART_RPR;      /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
+  RwReg UART_RCR;      /**< \brief (Uart Offset: 0x104) Receive Counter Register */
+  RwReg UART_TPR;      /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
+  RwReg UART_TCR;      /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
+  RwReg UART_RNPR;     /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
+  RwReg UART_RNCR;     /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
+  RwReg UART_TNPR;     /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg UART_TNCR;     /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg UART_PTCR;     /**< \brief (Uart Offset: 0x120) Transfer Control Register */
+  RoReg UART_PTSR;     /**< \brief (Uart Offset: 0x124) Transfer Status Register */
+} Uart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
+#define UART_MR_PAR_Pos 9
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
+#define   UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
+#define   UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
+#define   UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
+#define   UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
+#define   UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
+#define UART_MR_CHMODE_Pos 14
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
+#define   UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
+#define   UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
+#define   UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
+#define   UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
+#define UART_RHR_RXCHR_Pos 0
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
+#define UART_THR_TXCHR_Pos 0
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define UART_BRGR_CD_Pos 0
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
+#define UART_RPR_RXPTR_Pos 0
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
+#define UART_RCR_RXCTR_Pos 0
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
+#define UART_TPR_TXPTR_Pos 0
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
+#define UART_TCR_TXCTR_Pos 0
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
+#define UART_RNPR_RXNPTR_Pos 0
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
+#define UART_RNCR_RXNCTR_Pos 0
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define UART_TNPR_TXNPTR_Pos 0
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define UART_TNCR_TXNCTR_Pos 0
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM4S_UART_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_udp.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_udp.h
new file mode 100644
index 0000000..899eb9f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_udp.h
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_UDP_COMPONENT_
+#define _SAM4S_UDP_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR USB Device Port */
+/* ============================================================================= */
+/** \addtogroup SAM4S_UDP USB Device Port */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Udp hardware registers */
+typedef struct {
+  RoReg UDP_FRM_NUM;  /**< \brief (Udp Offset: 0x000) Frame Number Register */
+  RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */
+  RwReg UDP_FADDR;    /**< \brief (Udp Offset: 0x008) Function Address Register */
+  RoReg Reserved1[1];
+  WoReg UDP_IER;      /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */
+  WoReg UDP_IDR;      /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */
+  RoReg UDP_IMR;      /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */
+  RoReg UDP_ISR;      /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */
+  WoReg UDP_ICR;      /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */
+  RoReg Reserved2[1];
+  RwReg UDP_RST_EP;   /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */
+  RoReg Reserved3[1];
+  RwReg UDP_CSR[8];   /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */
+  RwReg UDP_FDR[8];   /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */
+  RoReg Reserved4[1];
+  RwReg UDP_TXVC;     /**< \brief (Udp Offset: 0x074) Transceiver Control Register */
+} Udp;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */
+#define UDP_FRM_NUM_FRM_NUM_Pos 0
+#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */
+#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */
+#define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */
+/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */
+#define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */
+#define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */
+#define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */
+#define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT)  */
+#define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */
+/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */
+#define UDP_FADDR_FADD_Pos 0
+#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */
+#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos)))
+#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */
+/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */
+#define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */
+#define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */
+#define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */
+#define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */
+#define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */
+#define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */
+#define UDP_IER_EP6INT (0x1u << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */
+#define UDP_IER_EP7INT (0x1u << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */
+#define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */
+#define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */
+#define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER)  */
+#define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */
+#define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */
+/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */
+#define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */
+#define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */
+#define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */
+#define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */
+#define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */
+#define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */
+#define UDP_IDR_EP6INT (0x1u << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */
+#define UDP_IDR_EP7INT (0x1u << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */
+#define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */
+#define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */
+#define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR)  */
+#define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */
+#define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */
+/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */
+#define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */
+#define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */
+#define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */
+#define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */
+#define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */
+#define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */
+#define UDP_IMR_EP6INT (0x1u << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */
+#define UDP_IMR_EP7INT (0x1u << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */
+#define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */
+#define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */
+#define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR)  */
+#define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */
+#define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */
+#define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */
+/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */
+#define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */
+#define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */
+#define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */
+#define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */
+#define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */
+#define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */
+#define UDP_ISR_EP6INT (0x1u << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */
+#define UDP_ISR_EP7INT (0x1u << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */
+#define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */
+#define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
+#define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR)  */
+#define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */
+#define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */
+#define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */
+/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */
+#define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */
+#define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */
+#define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR)  */
+#define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */
+#define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */
+#define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */
+/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */
+#define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */
+#define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */
+#define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */
+#define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */
+#define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */
+#define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */
+#define UDP_RST_EP_EP6 (0x1u << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */
+#define UDP_RST_EP_EP7 (0x1u << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */
+/* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */
+#define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */
+#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */
+#define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[8]) Received Setup */
+#define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */
+#define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */
+#define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */
+#define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */
+#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */
+#define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */
+#define UDP_CSR_EPTYPE_Pos 8
+#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */
+#define   UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */
+#define   UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */
+#define   UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */
+#define   UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */
+#define   UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */
+#define   UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */
+#define   UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */
+#define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[8]) Data Toggle */
+#define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */
+#define UDP_CSR_RXBYTECNT_Pos 16
+#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */
+#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos)))
+/* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */
+#define UDP_FDR_FIFO_DATA_Pos 0
+#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[8]) FIFO Data Value */
+#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos)))
+/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */
+#define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */
+#define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pullup On */
+
+/*@}*/
+
+
+#endif /* _SAM4S_UDP_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_usart.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_usart.h
new file mode 100644
index 0000000..bb04687
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_usart.h
@@ -0,0 +1,361 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_USART_COMPONENT_
+#define _SAM4S_USART_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
+/* ============================================================================= */
+/** \addtogroup SAM4S_USART Universal Synchronous Asynchronous Receiver Transmitter */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Usart hardware registers */
+typedef struct {
+  WoReg US_CR;         /**< \brief (Usart Offset: 0x0000) Control Register */
+  RwReg US_MR;         /**< \brief (Usart Offset: 0x0004) Mode Register */
+  WoReg US_IER;        /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
+  WoReg US_IDR;        /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
+  RoReg US_IMR;        /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
+  RoReg US_CSR;        /**< \brief (Usart Offset: 0x0014) Channel Status Register */
+  RoReg US_RHR;        /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
+  WoReg US_THR;        /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
+  RwReg US_BRGR;       /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
+  RwReg US_RTOR;       /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
+  RwReg US_TTGR;       /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
+  RoReg Reserved1[5];
+  RwReg US_FIDI;       /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
+  RoReg US_NER;        /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
+  RoReg Reserved2[1];
+  RwReg US_IF;         /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
+  RwReg US_MAN;        /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
+  RoReg Reserved3[36];
+  RwReg US_WPMR;       /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
+  RoReg US_WPSR;       /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
+  RoReg Reserved4[4];
+  RoReg US_VERSION;    /**< \brief (Usart Offset: 0xFC) Version Register */
+  RwReg US_RPR;        /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
+  RwReg US_RCR;        /**< \brief (Usart Offset: 0x104) Receive Counter Register */
+  RwReg US_TPR;        /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
+  RwReg US_TCR;        /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
+  RwReg US_RNPR;       /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
+  RwReg US_RNCR;       /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
+  RwReg US_TNPR;       /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
+  RwReg US_TNCR;       /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
+  WoReg US_PTCR;       /**< \brief (Usart Offset: 0x120) Transfer Control Register */
+  RoReg US_PTSR;       /**< \brief (Usart Offset: 0x124) Transfer Status Register */
+} Usart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
+#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */
+#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
+#define US_MR_USART_MODE_Pos 0
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR)  */
+#define   US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
+#define   US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
+#define   US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
+#define   US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */
+#define   US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
+#define   US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
+#define   US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
+#define   US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
+#define   US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
+#define US_MR_USCLKS_Pos 4
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
+#define   US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
+#define   US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
+#define   US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
+#define US_MR_CHRL_Pos 6
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
+#define   US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
+#define   US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
+#define   US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
+#define   US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
+#define US_MR_PAR_Pos 9
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
+#define   US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
+#define   US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
+#define   US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
+#define   US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
+#define   US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
+#define   US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
+#define US_MR_NBSTOP_Pos 12
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
+#define   US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
+#define   US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
+#define   US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
+#define US_MR_CHMODE_Pos 14
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
+#define   US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
+#define   US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
+#define   US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
+#define   US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
+#define US_MR_MAX_ITERATION_Pos 24
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR)  */
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
+#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */
+#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */
+#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
+#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */
+#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */
+#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
+#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */
+#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */
+#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
+#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */
+#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */
+#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
+#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */
+#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */
+#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
+#define US_RHR_RXCHR_Pos 0
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
+#define US_THR_TXCHR_Pos 0
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
+#define US_BRGR_CD_Pos 0
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
+#define US_BRGR_FP_Pos 16
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
+#define US_RTOR_TO_Pos 0
+#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
+#define US_TTGR_TG_Pos 0
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
+#define US_FIDI_FI_DI_RATIO_Pos 0
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
+#define US_NER_NB_ERRORS_Pos 0
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
+#define US_IF_IRDA_FILTER_Pos 0
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
+#define US_MAN_TX_PL_Pos 0
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
+#define US_MAN_TX_PP_Pos 8
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
+#define   US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
+#define US_MAN_RX_PL_Pos 16
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
+#define US_MAN_RX_PP_Pos 24
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
+#define   US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
+#define   US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
+#define   US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
+#define   US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN)  */
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
+#define US_WPMR_WPKEY_Pos 8
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
+#define US_WPSR_WPVSRC_Pos 8
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
+/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */
+#define US_VERSION_VERSION_Pos 0
+#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION)  */
+#define US_VERSION_MFN_Pos 16
+#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION)  */
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
+#define US_RPR_RXPTR_Pos 0
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
+#define US_RCR_RXCTR_Pos 0
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
+#define US_TPR_TXPTR_Pos 0
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
+#define US_TCR_TXCTR_Pos 0
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
+#define US_RNPR_RXNPTR_Pos 0
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
+#define US_RNCR_RXNCTR_Pos 0
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
+#define US_TNPR_TXNPTR_Pos 0
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
+#define US_TNCR_TXNCTR_Pos 0
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
+
+/*@}*/
+
+
+#endif /* _SAM4S_USART_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_wdt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_wdt.h
new file mode 100644
index 0000000..2a8a373
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/component/component_wdt.h
@@ -0,0 +1,72 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_WDT_COMPONENT_
+#define _SAM4S_WDT_COMPONENT_
+
+/* ============================================================================= */
+/**  SOFTWARE API DEFINITION FOR Watchdog Timer */
+/* ============================================================================= */
+/** \addtogroup SAM4S_WDT Watchdog Timer */
+/*@{*/
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief Wdt hardware registers */
+typedef struct {
+  WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
+  RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
+  RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
+#define WDT_CR_KEY_Pos 24
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
+#define WDT_MR_WDV_Pos 0
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
+#define WDT_MR_WDD_Pos 16
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
+
+/*@}*/
+
+
+#endif /* _SAM4S_WDT_COMPONENT_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_acc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_acc.h
new file mode 100644
index 0000000..6ba06bd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_acc.h
@@ -0,0 +1,56 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_ACC_INSTANCE_
+#define _SAM4S_ACC_INSTANCE_
+
+/* ========== Register definition for ACC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ACC_CR            (0x40040000U) /**< \brief (ACC) Control Register */
+#define REG_ACC_MR            (0x40040004U) /**< \brief (ACC) Mode Register */
+#define REG_ACC_IER           (0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
+#define REG_ACC_IDR           (0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
+#define REG_ACC_IMR           (0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
+#define REG_ACC_ISR           (0x40040030U) /**< \brief (ACC) Interrupt Status Register */
+#define REG_ACC_ACR           (0x40040094U) /**< \brief (ACC) Analog Control Register */
+#define REG_ACC_WPMR          (0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
+#define REG_ACC_WPSR          (0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
+#else
+#define REG_ACC_CR   (*(WoReg*)0x40040000U) /**< \brief (ACC) Control Register */
+#define REG_ACC_MR   (*(RwReg*)0x40040004U) /**< \brief (ACC) Mode Register */
+#define REG_ACC_IER  (*(WoReg*)0x40040024U) /**< \brief (ACC) Interrupt Enable Register */
+#define REG_ACC_IDR  (*(WoReg*)0x40040028U) /**< \brief (ACC) Interrupt Disable Register */
+#define REG_ACC_IMR  (*(RoReg*)0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */
+#define REG_ACC_ISR  (*(RoReg*)0x40040030U) /**< \brief (ACC) Interrupt Status Register */
+#define REG_ACC_ACR  (*(RwReg*)0x40040094U) /**< \brief (ACC) Analog Control Register */
+#define REG_ACC_WPMR (*(RwReg*)0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */
+#define REG_ACC_WPSR (*(RoReg*)0x400400E8U) /**< \brief (ACC) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_ACC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_adc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_adc.h
new file mode 100644
index 0000000..c643c74
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_adc.h
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_ADC_INSTANCE_
+#define _SAM4S_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CR               (0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR               (0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1            (0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2            (0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER             (0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR             (0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR             (0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR             (0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER              (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR              (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR              (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR              (0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER             (0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR              (0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR              (0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR              (0x40038048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR              (0x4003804CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR              (0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR              (0x40038094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR             (0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR             (0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR              (0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR              (0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR             (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR             (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR             (0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR             (0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#else
+#define REG_ADC_CR      (*(WoReg*)0x40038000U) /**< \brief (ADC) Control Register */
+#define REG_ADC_MR      (*(RwReg*)0x40038004U) /**< \brief (ADC) Mode Register */
+#define REG_ADC_SEQR1   (*(RwReg*)0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
+#define REG_ADC_SEQR2   (*(RwReg*)0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
+#define REG_ADC_CHER    (*(WoReg*)0x40038010U) /**< \brief (ADC) Channel Enable Register */
+#define REG_ADC_CHDR    (*(WoReg*)0x40038014U) /**< \brief (ADC) Channel Disable Register */
+#define REG_ADC_CHSR    (*(RoReg*)0x40038018U) /**< \brief (ADC) Channel Status Register */
+#define REG_ADC_LCDR    (*(RoReg*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */
+#define REG_ADC_IER     (*(WoReg*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
+#define REG_ADC_IDR     (*(WoReg*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
+#define REG_ADC_IMR     (*(RoReg*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
+#define REG_ADC_ISR     (*(RoReg*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */
+#define REG_ADC_OVER    (*(RoReg*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */
+#define REG_ADC_EMR     (*(RwReg*)0x40038040U) /**< \brief (ADC) Extended Mode Register */
+#define REG_ADC_CWR     (*(RwReg*)0x40038044U) /**< \brief (ADC) Compare Window Register */
+#define REG_ADC_CGR     (*(RwReg*)0x40038048U) /**< \brief (ADC) Channel Gain Register */
+#define REG_ADC_COR     (*(RwReg*)0x4003804CU) /**< \brief (ADC) Channel Offset Register */
+#define REG_ADC_CDR     (*(RoReg*)0x40038050U) /**< \brief (ADC) Channel Data Register */
+#define REG_ADC_ACR     (*(RwReg*)0x40038094U) /**< \brief (ADC) Analog Control Register */
+#define REG_ADC_WPMR    (*(RwReg*)0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
+#define REG_ADC_WPSR    (*(RoReg*)0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
+#define REG_ADC_RPR     (*(RwReg*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */
+#define REG_ADC_RCR     (*(RwReg*)0x40038104U) /**< \brief (ADC) Receive Counter Register */
+#define REG_ADC_RNPR    (*(RwReg*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
+#define REG_ADC_RNCR    (*(RwReg*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
+#define REG_ADC_PTCR    (*(WoReg*)0x40038120U) /**< \brief (ADC) Transfer Control Register */
+#define REG_ADC_PTSR    (*(RoReg*)0x40038124U) /**< \brief (ADC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_ADC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_chipid.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_chipid.h
new file mode 100644
index 0000000..231fc18
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_chipid.h
@@ -0,0 +1,42 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_CHIPID_INSTANCE_
+#define _SAM4S_CHIPID_INSTANCE_
+
+/* ========== Register definition for CHIPID peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CHIPID_CIDR          (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID          (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#else
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_CHIPID_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_crccu.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_crccu.h
new file mode 100644
index 0000000..d491cae
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_crccu.h
@@ -0,0 +1,68 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_CRCCU_INSTANCE_
+#define _SAM4S_CRCCU_INSTANCE_
+
+/* ========== Register definition for CRCCU peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CRCCU_DSCR             (0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
+#define REG_CRCCU_DMA_EN           (0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
+#define REG_CRCCU_DMA_DIS          (0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
+#define REG_CRCCU_DMA_SR           (0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
+#define REG_CRCCU_DMA_IER          (0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
+#define REG_CRCCU_DMA_IDR          (0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
+#define REG_CRCCU_DMA_IMR          (0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
+#define REG_CRCCU_DMA_ISR          (0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
+#define REG_CRCCU_CR               (0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
+#define REG_CRCCU_MR               (0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
+#define REG_CRCCU_SR               (0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
+#define REG_CRCCU_IER              (0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
+#define REG_CRCCU_IDR              (0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
+#define REG_CRCCU_IMR              (0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
+#define REG_CRCCU_ISR              (0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
+#else
+#define REG_CRCCU_DSCR    (*(RwReg*)0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
+#define REG_CRCCU_DMA_EN  (*(WoReg*)0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
+#define REG_CRCCU_DMA_DIS (*(WoReg*)0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
+#define REG_CRCCU_DMA_SR  (*(RoReg*)0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
+#define REG_CRCCU_DMA_IER (*(WoReg*)0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
+#define REG_CRCCU_DMA_IDR (*(WoReg*)0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
+#define REG_CRCCU_DMA_IMR (*(RoReg*)0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
+#define REG_CRCCU_DMA_ISR (*(RoReg*)0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
+#define REG_CRCCU_CR      (*(WoReg*)0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
+#define REG_CRCCU_MR      (*(RwReg*)0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
+#define REG_CRCCU_SR      (*(RoReg*)0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
+#define REG_CRCCU_IER     (*(WoReg*)0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
+#define REG_CRCCU_IDR     (*(WoReg*)0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
+#define REG_CRCCU_IMR     (*(RoReg*)0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
+#define REG_CRCCU_ISR     (*(RoReg*)0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_CRCCU_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_dacc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_dacc.h
new file mode 100644
index 0000000..8404777
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_dacc.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_DACC_INSTANCE_
+#define _SAM4S_DACC_INSTANCE_
+
+/* ========== Register definition for DACC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DACC_CR            (0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR            (0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER          (0x4003C010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR          (0x4003C014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR          (0x4003C018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR           (0x4003C020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER           (0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR           (0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR           (0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR           (0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR           (0x4003C094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR          (0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR          (0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_TPR           (0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR           (0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_TNPR          (0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR          (0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR          (0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR          (0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#else
+#define REG_DACC_CR   (*(WoReg*)0x4003C000U) /**< \brief (DACC) Control Register */
+#define REG_DACC_MR   (*(RwReg*)0x4003C004U) /**< \brief (DACC) Mode Register */
+#define REG_DACC_CHER (*(WoReg*)0x4003C010U) /**< \brief (DACC) Channel Enable Register */
+#define REG_DACC_CHDR (*(WoReg*)0x4003C014U) /**< \brief (DACC) Channel Disable Register */
+#define REG_DACC_CHSR (*(RoReg*)0x4003C018U) /**< \brief (DACC) Channel Status Register */
+#define REG_DACC_CDR  (*(WoReg*)0x4003C020U) /**< \brief (DACC) Conversion Data Register */
+#define REG_DACC_IER  (*(WoReg*)0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */
+#define REG_DACC_IDR  (*(WoReg*)0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */
+#define REG_DACC_IMR  (*(RoReg*)0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */
+#define REG_DACC_ISR  (*(RoReg*)0x4003C030U) /**< \brief (DACC) Interrupt Status Register */
+#define REG_DACC_ACR  (*(RwReg*)0x4003C094U) /**< \brief (DACC) Analog Current Register */
+#define REG_DACC_WPMR (*(RwReg*)0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */
+#define REG_DACC_WPSR (*(RoReg*)0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */
+#define REG_DACC_TPR  (*(RwReg*)0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
+#define REG_DACC_TCR  (*(RwReg*)0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
+#define REG_DACC_TNPR (*(RwReg*)0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
+#define REG_DACC_TNCR (*(RwReg*)0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
+#define REG_DACC_PTCR (*(WoReg*)0x4003C120U) /**< \brief (DACC) Transfer Control Register */
+#define REG_DACC_PTSR (*(RoReg*)0x4003C124U) /**< \brief (DACC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_DACC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_efc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_efc.h
new file mode 100644
index 0000000..a7550de
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_efc.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_EFC_INSTANCE_
+#define _SAM4S_EFC_INSTANCE_
+
+/* ========== Register definition for EFC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EFC_FMR           (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR           (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR           (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR           (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#else
+#define REG_EFC_FMR  (*(RwReg*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
+#define REG_EFC_FCR  (*(WoReg*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
+#define REG_EFC_FSR  (*(RoReg*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
+#define REG_EFC_FRR  (*(RoReg*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_EFC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_gpbr.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_gpbr.h
new file mode 100644
index 0000000..0f85cd9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_gpbr.h
@@ -0,0 +1,40 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_GPBR_INSTANCE_
+#define _SAM4S_GPBR_INSTANCE_
+
+/* ========== Register definition for GPBR peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GPBR_GPBR            (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#else
+#define REG_GPBR_GPBR   (*(RwReg*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_GPBR_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_hsmci.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_hsmci.h
new file mode 100644
index 0000000..645c5b3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_hsmci.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_HSMCI_INSTANCE_
+#define _SAM4S_HSMCI_INSTANCE_
+
+/* ========== Register definition for HSMCI peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_HSMCI_CR                 (0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR                 (0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR               (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR               (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR               (0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR               (0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR               (0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR              (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR               (0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR                (0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR                (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR                 (0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER                (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR                (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR                (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_CFG                (0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR               (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR               (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_RPR                (0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
+#define REG_HSMCI_RCR                (0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
+#define REG_HSMCI_TPR                (0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
+#define REG_HSMCI_TCR                (0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
+#define REG_HSMCI_RNPR               (0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
+#define REG_HSMCI_RNCR               (0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
+#define REG_HSMCI_TNPR               (0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
+#define REG_HSMCI_TNCR               (0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
+#define REG_HSMCI_PTCR               (0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
+#define REG_HSMCI_PTSR               (0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
+#define REG_HSMCI_FIFO               (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#else
+#define REG_HSMCI_CR        (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */
+#define REG_HSMCI_MR        (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */
+#define REG_HSMCI_DTOR      (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
+#define REG_HSMCI_SDCR      (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
+#define REG_HSMCI_ARGR      (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */
+#define REG_HSMCI_CMDR      (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */
+#define REG_HSMCI_BLKR      (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */
+#define REG_HSMCI_CSTOR     (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
+#define REG_HSMCI_RSPR      (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */
+#define REG_HSMCI_RDR       (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */
+#define REG_HSMCI_TDR       (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
+#define REG_HSMCI_SR        (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */
+#define REG_HSMCI_IER       (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
+#define REG_HSMCI_IDR       (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
+#define REG_HSMCI_IMR       (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
+#define REG_HSMCI_CFG       (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */
+#define REG_HSMCI_WPMR      (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
+#define REG_HSMCI_WPSR      (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
+#define REG_HSMCI_RPR       (*(RwReg*)0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
+#define REG_HSMCI_RCR       (*(RwReg*)0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
+#define REG_HSMCI_TPR       (*(RwReg*)0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
+#define REG_HSMCI_TCR       (*(RwReg*)0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
+#define REG_HSMCI_RNPR      (*(RwReg*)0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
+#define REG_HSMCI_RNCR      (*(RwReg*)0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
+#define REG_HSMCI_TNPR      (*(RwReg*)0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
+#define REG_HSMCI_TNCR      (*(RwReg*)0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
+#define REG_HSMCI_PTCR      (*(WoReg*)0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
+#define REG_HSMCI_PTSR      (*(RoReg*)0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
+#define REG_HSMCI_FIFO      (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_HSMCI_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_matrix.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_matrix.h
new file mode 100644
index 0000000..85c83bc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_matrix.h
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_MATRIX_INSTANCE_
+#define _SAM4S_MATRIX_INSTANCE_
+
+/* ========== Register definition for MATRIX peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MATRIX_MCFG             (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG             (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0            (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1            (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2            (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3            (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4            (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_CCFG_SYSIO              (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_CCFG_SMCNFCS            (0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */
+#define REG_MATRIX_WPMR             (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR             (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#else
+#define REG_MATRIX_MCFG    (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
+#define REG_MATRIX_SCFG    (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
+#define REG_MATRIX_PRAS0   (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
+#define REG_MATRIX_PRAS1   (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
+#define REG_MATRIX_PRAS2   (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
+#define REG_MATRIX_PRAS3   (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
+#define REG_MATRIX_PRAS4   (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
+#define REG_CCFG_SYSIO     (*(RwReg*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
+#define REG_CCFG_SMCNFCS   (*(RwReg*)0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */
+#define REG_MATRIX_WPMR    (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
+#define REG_MATRIX_WPSR    (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_MATRIX_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_pioa.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_pioa.h
new file mode 100644
index 0000000..7d042a2
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_pioa.h
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_PIOA_INSTANCE_
+#define _SAM4S_PIOA_INSTANCE_
+
+/* ========== Register definition for PIOA peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOA_PER                (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR                (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR                (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER                (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR                (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR                (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER               (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR               (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR               (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR               (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR               (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR               (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR               (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER                (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR                (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR                (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR                (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER               (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR               (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR               (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR               (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER               (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR               (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR             (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR             (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER             (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR             (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR               (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR              (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER              (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR              (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER               (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR               (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR               (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER              (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR              (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR              (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR                (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR                (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR               (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR             (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR             (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR             (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR             (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR               (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR               (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT            (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#define REG_PIOA_PCMR               (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
+#define REG_PIOA_PCIER              (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
+#define REG_PIOA_PCIDR              (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
+#define REG_PIOA_PCIMR              (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
+#define REG_PIOA_PCISR              (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
+#define REG_PIOA_PCRHR              (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
+#define REG_PIOA_RPR                (0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */
+#define REG_PIOA_RCR                (0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */
+#define REG_PIOA_RNPR               (0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */
+#define REG_PIOA_RNCR               (0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */
+#define REG_PIOA_PTCR               (0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */
+#define REG_PIOA_PTSR               (0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */
+#else
+#define REG_PIOA_PER       (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
+#define REG_PIOA_PDR       (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
+#define REG_PIOA_PSR       (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
+#define REG_PIOA_OER       (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
+#define REG_PIOA_ODR       (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
+#define REG_PIOA_OSR       (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
+#define REG_PIOA_IFER      (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
+#define REG_PIOA_IFDR      (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
+#define REG_PIOA_IFSR      (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
+#define REG_PIOA_SODR      (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
+#define REG_PIOA_CODR      (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
+#define REG_PIOA_ODSR      (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
+#define REG_PIOA_PDSR      (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
+#define REG_PIOA_IER       (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
+#define REG_PIOA_IDR       (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
+#define REG_PIOA_IMR       (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
+#define REG_PIOA_ISR       (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
+#define REG_PIOA_MDER      (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
+#define REG_PIOA_MDDR      (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
+#define REG_PIOA_MDSR      (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
+#define REG_PIOA_PUDR      (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
+#define REG_PIOA_PUER      (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
+#define REG_PIOA_PUSR      (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
+#define REG_PIOA_ABCDSR    (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
+#define REG_PIOA_IFSCDR    (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
+#define REG_PIOA_IFSCER    (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
+#define REG_PIOA_IFSCSR    (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
+#define REG_PIOA_SCDR      (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
+#define REG_PIOA_PPDDR     (*(WoReg*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
+#define REG_PIOA_PPDER     (*(WoReg*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
+#define REG_PIOA_PPDSR     (*(RoReg*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
+#define REG_PIOA_OWER      (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
+#define REG_PIOA_OWDR      (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
+#define REG_PIOA_OWSR      (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
+#define REG_PIOA_AIMER     (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
+#define REG_PIOA_AIMDR     (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
+#define REG_PIOA_AIMMR     (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
+#define REG_PIOA_ESR       (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
+#define REG_PIOA_LSR       (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
+#define REG_PIOA_ELSR      (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
+#define REG_PIOA_FELLSR    (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
+#define REG_PIOA_REHLSR    (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
+#define REG_PIOA_FRLHSR    (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
+#define REG_PIOA_LOCKSR    (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
+#define REG_PIOA_WPMR      (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
+#define REG_PIOA_WPSR      (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
+#define REG_PIOA_SCHMITT   (*(RwReg*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
+#define REG_PIOA_PCMR      (*(RwReg*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
+#define REG_PIOA_PCIER     (*(WoReg*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
+#define REG_PIOA_PCIDR     (*(WoReg*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
+#define REG_PIOA_PCIMR     (*(RoReg*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
+#define REG_PIOA_PCISR     (*(RoReg*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
+#define REG_PIOA_PCRHR     (*(RoReg*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
+#define REG_PIOA_RPR       (*(RwReg*)0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */
+#define REG_PIOA_RCR       (*(RwReg*)0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */
+#define REG_PIOA_RNPR      (*(RwReg*)0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */
+#define REG_PIOA_RNCR      (*(RwReg*)0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */
+#define REG_PIOA_PTCR      (*(WoReg*)0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */
+#define REG_PIOA_PTSR      (*(RoReg*)0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_PIOA_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_piob.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_piob.h
new file mode 100644
index 0000000..aac037e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_piob.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_PIOB_INSTANCE_
+#define _SAM4S_PIOB_INSTANCE_
+
+/* ========== Register definition for PIOB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOB_PER                (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR                (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR                (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER                (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR                (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR                (0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER               (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR               (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR               (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR               (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR               (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR               (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR               (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER                (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR                (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR                (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR                (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER               (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR               (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR               (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR               (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER               (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR               (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR             (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR             (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER             (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR             (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR               (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR              (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER              (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR              (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER               (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR               (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR               (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER              (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR              (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR              (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR                (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR                (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR               (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR             (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR             (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR             (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR             (0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR               (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR               (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT            (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#define REG_PIOB_PCMR               (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
+#define REG_PIOB_PCIER              (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
+#define REG_PIOB_PCIDR              (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
+#define REG_PIOB_PCIMR              (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
+#define REG_PIOB_PCISR              (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
+#define REG_PIOB_PCRHR              (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
+#else
+#define REG_PIOB_PER       (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
+#define REG_PIOB_PDR       (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
+#define REG_PIOB_PSR       (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
+#define REG_PIOB_OER       (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
+#define REG_PIOB_ODR       (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
+#define REG_PIOB_OSR       (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
+#define REG_PIOB_IFER      (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
+#define REG_PIOB_IFDR      (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
+#define REG_PIOB_IFSR      (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
+#define REG_PIOB_SODR      (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
+#define REG_PIOB_CODR      (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
+#define REG_PIOB_ODSR      (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
+#define REG_PIOB_PDSR      (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
+#define REG_PIOB_IER       (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
+#define REG_PIOB_IDR       (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
+#define REG_PIOB_IMR       (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
+#define REG_PIOB_ISR       (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
+#define REG_PIOB_MDER      (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
+#define REG_PIOB_MDDR      (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
+#define REG_PIOB_MDSR      (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
+#define REG_PIOB_PUDR      (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
+#define REG_PIOB_PUER      (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
+#define REG_PIOB_PUSR      (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
+#define REG_PIOB_ABCDSR    (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
+#define REG_PIOB_IFSCDR    (*(WoReg*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
+#define REG_PIOB_IFSCER    (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
+#define REG_PIOB_IFSCSR    (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
+#define REG_PIOB_SCDR      (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
+#define REG_PIOB_PPDDR     (*(WoReg*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
+#define REG_PIOB_PPDER     (*(WoReg*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
+#define REG_PIOB_PPDSR     (*(RoReg*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
+#define REG_PIOB_OWER      (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
+#define REG_PIOB_OWDR      (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
+#define REG_PIOB_OWSR      (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
+#define REG_PIOB_AIMER     (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
+#define REG_PIOB_AIMDR     (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
+#define REG_PIOB_AIMMR     (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
+#define REG_PIOB_ESR       (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
+#define REG_PIOB_LSR       (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
+#define REG_PIOB_ELSR      (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
+#define REG_PIOB_FELLSR    (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
+#define REG_PIOB_REHLSR    (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
+#define REG_PIOB_FRLHSR    (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
+#define REG_PIOB_LOCKSR    (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
+#define REG_PIOB_WPMR      (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
+#define REG_PIOB_WPSR      (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
+#define REG_PIOB_SCHMITT   (*(RwReg*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
+#define REG_PIOB_PCMR      (*(RwReg*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
+#define REG_PIOB_PCIER     (*(WoReg*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
+#define REG_PIOB_PCIDR     (*(WoReg*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
+#define REG_PIOB_PCIMR     (*(RoReg*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
+#define REG_PIOB_PCISR     (*(RoReg*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
+#define REG_PIOB_PCRHR     (*(RoReg*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_PIOB_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_pioc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_pioc.h
new file mode 100644
index 0000000..a23259e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_pioc.h
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_PIOC_INSTANCE_
+#define _SAM4S_PIOC_INSTANCE_
+
+/* ========== Register definition for PIOC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PIOC_PER                (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR                (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR                (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER                (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR                (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR                (0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER               (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR               (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR               (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR               (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR               (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR               (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR               (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER                (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR                (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR                (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR                (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER               (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR               (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR               (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR               (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER               (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR               (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR             (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR             (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER             (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR             (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR               (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR              (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER              (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR              (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER               (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR               (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR               (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER              (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR              (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR              (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR                (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR                (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR               (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR             (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR             (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR             (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR             (0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR               (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR               (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT            (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#define REG_PIOC_PCMR               (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
+#define REG_PIOC_PCIER              (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
+#define REG_PIOC_PCIDR              (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
+#define REG_PIOC_PCIMR              (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
+#define REG_PIOC_PCISR              (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
+#define REG_PIOC_PCRHR              (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
+#else
+#define REG_PIOC_PER       (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
+#define REG_PIOC_PDR       (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
+#define REG_PIOC_PSR       (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
+#define REG_PIOC_OER       (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
+#define REG_PIOC_ODR       (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
+#define REG_PIOC_OSR       (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
+#define REG_PIOC_IFER      (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
+#define REG_PIOC_IFDR      (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
+#define REG_PIOC_IFSR      (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
+#define REG_PIOC_SODR      (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
+#define REG_PIOC_CODR      (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
+#define REG_PIOC_ODSR      (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
+#define REG_PIOC_PDSR      (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
+#define REG_PIOC_IER       (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
+#define REG_PIOC_IDR       (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
+#define REG_PIOC_IMR       (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
+#define REG_PIOC_ISR       (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
+#define REG_PIOC_MDER      (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
+#define REG_PIOC_MDDR      (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
+#define REG_PIOC_MDSR      (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
+#define REG_PIOC_PUDR      (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
+#define REG_PIOC_PUER      (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
+#define REG_PIOC_PUSR      (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
+#define REG_PIOC_ABCDSR    (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
+#define REG_PIOC_IFSCDR    (*(WoReg*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
+#define REG_PIOC_IFSCER    (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
+#define REG_PIOC_IFSCSR    (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
+#define REG_PIOC_SCDR      (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
+#define REG_PIOC_PPDDR     (*(WoReg*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
+#define REG_PIOC_PPDER     (*(WoReg*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
+#define REG_PIOC_PPDSR     (*(RoReg*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
+#define REG_PIOC_OWER      (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
+#define REG_PIOC_OWDR      (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
+#define REG_PIOC_OWSR      (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
+#define REG_PIOC_AIMER     (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
+#define REG_PIOC_AIMDR     (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
+#define REG_PIOC_AIMMR     (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
+#define REG_PIOC_ESR       (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
+#define REG_PIOC_LSR       (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
+#define REG_PIOC_ELSR      (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
+#define REG_PIOC_FELLSR    (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
+#define REG_PIOC_REHLSR    (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
+#define REG_PIOC_FRLHSR    (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
+#define REG_PIOC_LOCKSR    (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
+#define REG_PIOC_WPMR      (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
+#define REG_PIOC_WPSR      (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
+#define REG_PIOC_SCHMITT   (*(RwReg*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
+#define REG_PIOC_PCMR      (*(RwReg*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
+#define REG_PIOC_PCIER     (*(WoReg*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
+#define REG_PIOC_PCIDR     (*(WoReg*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
+#define REG_PIOC_PCIMR     (*(RoReg*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
+#define REG_PIOC_PCISR     (*(RoReg*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
+#define REG_PIOC_PCRHR     (*(RoReg*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_PIOC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_pmc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_pmc.h
new file mode 100644
index 0000000..f79da72
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_pmc.h
@@ -0,0 +1,90 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_PMC_INSTANCE_
+#define _SAM4S_PMC_INSTANCE_
+
+/* ========== Register definition for PMC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PMC_SCER            (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR            (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR            (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0           (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0           (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0           (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR            (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR           (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR          (0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_CKGR_PLLBR          (0x400E042CU) /**< \brief (PMC) PLLB Register */
+#define REG_PMC_MCKR            (0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB             (0x400E0438U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK             (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER             (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR             (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR              (0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR             (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR            (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR            (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR            (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR            (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR            (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1           (0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1           (0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1           (0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_OCR             (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
+#else
+#define REG_PMC_SCER   (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
+#define REG_PMC_SCDR   (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
+#define REG_PMC_SCSR   (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
+#define REG_PMC_PCER0  (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
+#define REG_PMC_PCDR0  (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
+#define REG_PMC_PCSR0  (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
+#define REG_CKGR_MOR   (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
+#define REG_CKGR_MCFR  (*(RwReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */
+#define REG_CKGR_PLLBR (*(RwReg*)0x400E042CU) /**< \brief (PMC) PLLB Register */
+#define REG_PMC_MCKR   (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
+#define REG_PMC_USB    (*(RwReg*)0x400E0438U) /**< \brief (PMC) USB Clock Register */
+#define REG_PMC_PCK    (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
+#define REG_PMC_IER    (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
+#define REG_PMC_IDR    (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
+#define REG_PMC_SR     (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
+#define REG_PMC_IMR    (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
+#define REG_PMC_FSMR   (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
+#define REG_PMC_FSPR   (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
+#define REG_PMC_FOCR   (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
+#define REG_PMC_WPMR   (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
+#define REG_PMC_WPSR   (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
+#define REG_PMC_PCER1  (*(WoReg*)0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
+#define REG_PMC_PCDR1  (*(WoReg*)0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
+#define REG_PMC_PCSR1  (*(RoReg*)0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
+#define REG_PMC_OCR    (*(RwReg*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_PMC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_pwm.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_pwm.h
new file mode 100644
index 0000000..8337fbd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_pwm.h
@@ -0,0 +1,240 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_PWM_INSTANCE_
+#define _SAM4S_PWM_INSTANCE_
+
+/* ========== Register definition for PWM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PWM_CLK               (0x40020000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA               (0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS               (0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR                (0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1              (0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1              (0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1              (0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1              (0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM               (0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC              (0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP              (0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD           (0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2              (0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2              (0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2              (0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2              (0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV               (0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS                (0x40020048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS               (0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC               (0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD            (0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD            (0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR               (0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR               (0x40020060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR               (0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV               (0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE               (0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR              (0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR              (0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR              (0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR              (0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_TPR               (0x40020108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR               (0x4002010CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_TNPR              (0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR              (0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR              (0x40020120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR              (0x40020124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0             (0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0          (0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0             (0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0          (0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1             (0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1          (0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1             (0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1          (0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2             (0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2          (0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2             (0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2          (0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3             (0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3          (0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3             (0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3          (0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4             (0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4          (0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4             (0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4          (0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5             (0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5          (0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5             (0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5          (0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6             (0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6          (0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6             (0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6          (0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7             (0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7          (0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7             (0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7          (0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0              (0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0             (0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0          (0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0             (0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0          (0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0             (0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0               (0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0            (0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1              (0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1             (0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1          (0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1             (0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1          (0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1             (0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1               (0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1            (0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2              (0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2             (0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2          (0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2             (0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2          (0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2             (0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2               (0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2            (0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3              (0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3             (0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3          (0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3             (0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3          (0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3             (0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3               (0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3            (0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#else
+#define REG_PWM_CLK      (*(RwReg*)0x40020000U) /**< \brief (PWM) PWM Clock Register */
+#define REG_PWM_ENA      (*(WoReg*)0x40020004U) /**< \brief (PWM) PWM Enable Register */
+#define REG_PWM_DIS      (*(WoReg*)0x40020008U) /**< \brief (PWM) PWM Disable Register */
+#define REG_PWM_SR       (*(RoReg*)0x4002000CU) /**< \brief (PWM) PWM Status Register */
+#define REG_PWM_IER1     (*(WoReg*)0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
+#define REG_PWM_IDR1     (*(WoReg*)0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
+#define REG_PWM_IMR1     (*(RoReg*)0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
+#define REG_PWM_ISR1     (*(RoReg*)0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
+#define REG_PWM_SCM      (*(RwReg*)0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
+#define REG_PWM_SCUC     (*(RwReg*)0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
+#define REG_PWM_SCUP     (*(RwReg*)0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
+#define REG_PWM_SCUPUPD  (*(WoReg*)0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
+#define REG_PWM_IER2     (*(WoReg*)0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
+#define REG_PWM_IDR2     (*(WoReg*)0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
+#define REG_PWM_IMR2     (*(RoReg*)0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
+#define REG_PWM_ISR2     (*(RoReg*)0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
+#define REG_PWM_OOV      (*(RwReg*)0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */
+#define REG_PWM_OS       (*(RwReg*)0x40020048U) /**< \brief (PWM) PWM Output Selection Register */
+#define REG_PWM_OSS      (*(WoReg*)0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */
+#define REG_PWM_OSC      (*(WoReg*)0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */
+#define REG_PWM_OSSUPD   (*(WoReg*)0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
+#define REG_PWM_OSCUPD   (*(WoReg*)0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
+#define REG_PWM_FMR      (*(RwReg*)0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */
+#define REG_PWM_FSR      (*(RoReg*)0x40020060U) /**< \brief (PWM) PWM Fault Status Register */
+#define REG_PWM_FCR      (*(WoReg*)0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */
+#define REG_PWM_FPV      (*(RwReg*)0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */
+#define REG_PWM_FPE      (*(RwReg*)0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
+#define REG_PWM_ELMR     (*(RwReg*)0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
+#define REG_PWM_SMMR     (*(RwReg*)0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
+#define REG_PWM_WPCR     (*(WoReg*)0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */
+#define REG_PWM_WPSR     (*(RoReg*)0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */
+#define REG_PWM_TPR      (*(RwReg*)0x40020108U) /**< \brief (PWM) Transmit Pointer Register */
+#define REG_PWM_TCR      (*(RwReg*)0x4002010CU) /**< \brief (PWM) Transmit Counter Register */
+#define REG_PWM_TNPR     (*(RwReg*)0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */
+#define REG_PWM_TNCR     (*(RwReg*)0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */
+#define REG_PWM_PTCR     (*(WoReg*)0x40020120U) /**< \brief (PWM) Transfer Control Register */
+#define REG_PWM_PTSR     (*(RoReg*)0x40020124U) /**< \brief (PWM) Transfer Status Register */
+#define REG_PWM_CMPV0    (*(RwReg*)0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
+#define REG_PWM_CMPM0    (*(RwReg*)0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
+#define REG_PWM_CMPV1    (*(RwReg*)0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
+#define REG_PWM_CMPM1    (*(RwReg*)0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
+#define REG_PWM_CMPV2    (*(RwReg*)0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
+#define REG_PWM_CMPM2    (*(RwReg*)0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
+#define REG_PWM_CMPV3    (*(RwReg*)0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
+#define REG_PWM_CMPM3    (*(RwReg*)0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
+#define REG_PWM_CMPV4    (*(RwReg*)0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
+#define REG_PWM_CMPM4    (*(RwReg*)0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
+#define REG_PWM_CMPV5    (*(RwReg*)0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
+#define REG_PWM_CMPM5    (*(RwReg*)0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
+#define REG_PWM_CMPV6    (*(RwReg*)0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
+#define REG_PWM_CMPM6    (*(RwReg*)0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
+#define REG_PWM_CMPV7    (*(RwReg*)0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
+#define REG_PWM_CMPM7    (*(RwReg*)0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
+#define REG_PWM_CMR0     (*(RwReg*)0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
+#define REG_PWM_CDTY0    (*(RwReg*)0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
+#define REG_PWM_CPRD0    (*(RwReg*)0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
+#define REG_PWM_CCNT0    (*(RoReg*)0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
+#define REG_PWM_DT0      (*(RwReg*)0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
+#define REG_PWM_DTUPD0   (*(WoReg*)0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
+#define REG_PWM_CMR1     (*(RwReg*)0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
+#define REG_PWM_CDTY1    (*(RwReg*)0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
+#define REG_PWM_CPRD1    (*(RwReg*)0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
+#define REG_PWM_CCNT1    (*(RoReg*)0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
+#define REG_PWM_DT1      (*(RwReg*)0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
+#define REG_PWM_DTUPD1   (*(WoReg*)0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
+#define REG_PWM_CMR2     (*(RwReg*)0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
+#define REG_PWM_CDTY2    (*(RwReg*)0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
+#define REG_PWM_CPRD2    (*(RwReg*)0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
+#define REG_PWM_CCNT2    (*(RoReg*)0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
+#define REG_PWM_DT2      (*(RwReg*)0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
+#define REG_PWM_DTUPD2   (*(WoReg*)0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
+#define REG_PWM_CMR3     (*(RwReg*)0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
+#define REG_PWM_CDTY3    (*(RwReg*)0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
+#define REG_PWM_CPRD3    (*(RwReg*)0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
+#define REG_PWM_CCNT3    (*(RoReg*)0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
+#define REG_PWM_DT3      (*(RwReg*)0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
+#define REG_PWM_DTUPD3   (*(WoReg*)0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_PWM_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_rstc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_rstc.h
new file mode 100644
index 0000000..ca21215
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_rstc.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_RSTC_INSTANCE_
+#define _SAM4S_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RSTC_CR          (0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR          (0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR          (0x400E1408U) /**< \brief (RSTC) Mode Register */
+#else
+#define REG_RSTC_CR (*(WoReg*)0x400E1400U) /**< \brief (RSTC) Control Register */
+#define REG_RSTC_SR (*(RoReg*)0x400E1404U) /**< \brief (RSTC) Status Register */
+#define REG_RSTC_MR (*(RwReg*)0x400E1408U) /**< \brief (RSTC) Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_RSTC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_rtc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_rtc.h
new file mode 100644
index 0000000..abcc8dc
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_rtc.h
@@ -0,0 +1,62 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_RTC_INSTANCE_
+#define _SAM4S_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_CR              (0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR              (0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR            (0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR            (0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR          (0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR          (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR              (0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR            (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER             (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR             (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR             (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER             (0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#else
+#define REG_RTC_CR     (*(RwReg*)0x400E1460U) /**< \brief (RTC) Control Register */
+#define REG_RTC_MR     (*(RwReg*)0x400E1464U) /**< \brief (RTC) Mode Register */
+#define REG_RTC_TIMR   (*(RwReg*)0x400E1468U) /**< \brief (RTC) Time Register */
+#define REG_RTC_CALR   (*(RwReg*)0x400E146CU) /**< \brief (RTC) Calendar Register */
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */
+#define REG_RTC_CALALR (*(RwReg*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
+#define REG_RTC_SR     (*(RoReg*)0x400E1478U) /**< \brief (RTC) Status Register */
+#define REG_RTC_SCCR   (*(WoReg*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
+#define REG_RTC_IER    (*(WoReg*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
+#define REG_RTC_IDR    (*(WoReg*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
+#define REG_RTC_IMR    (*(RoReg*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
+#define REG_RTC_VER    (*(RoReg*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_RTC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_rtt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_rtt.h
new file mode 100644
index 0000000..2aa56ab
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_rtt.h
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_RTT_INSTANCE_
+#define _SAM4S_RTT_INSTANCE_
+
+/* ========== Register definition for RTT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTT_MR          (0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR          (0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR          (0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR          (0x400E143CU) /**< \brief (RTT) Status Register */
+#else
+#define REG_RTT_MR (*(RwReg*)0x400E1430U) /**< \brief (RTT) Mode Register */
+#define REG_RTT_AR (*(RwReg*)0x400E1434U) /**< \brief (RTT) Alarm Register */
+#define REG_RTT_VR (*(RoReg*)0x400E1438U) /**< \brief (RTT) Value Register */
+#define REG_RTT_SR (*(RoReg*)0x400E143CU) /**< \brief (RTT) Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_RTT_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_smc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_smc.h
new file mode 100644
index 0000000..0256a8a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_smc.h
@@ -0,0 +1,88 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_SMC_INSTANCE_
+#define _SAM4S_SMC_INSTANCE_
+
+/* ========== Register definition for SMC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SMC_SETUP0          (0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0          (0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0          (0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_MODE0           (0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1          (0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1          (0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1          (0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_MODE1           (0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2          (0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2          (0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2          (0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_MODE2           (0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3          (0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3          (0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3          (0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_MODE3           (0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4          (0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4          (0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4          (0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_MODE4           (0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_OCMS            (0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */
+#define REG_SMC_KEY1            (0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2            (0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPMR            (0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
+#define REG_SMC_WPSR            (0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */
+#else
+#define REG_SMC_SETUP0 (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
+#define REG_SMC_PULSE0 (*(RwReg*)0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
+#define REG_SMC_CYCLE0 (*(RwReg*)0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
+#define REG_SMC_MODE0  (*(RwReg*)0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
+#define REG_SMC_SETUP1 (*(RwReg*)0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
+#define REG_SMC_PULSE1 (*(RwReg*)0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
+#define REG_SMC_CYCLE1 (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
+#define REG_SMC_MODE1  (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
+#define REG_SMC_SETUP2 (*(RwReg*)0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
+#define REG_SMC_PULSE2 (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
+#define REG_SMC_CYCLE2 (*(RwReg*)0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
+#define REG_SMC_MODE2  (*(RwReg*)0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
+#define REG_SMC_SETUP3 (*(RwReg*)0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
+#define REG_SMC_PULSE3 (*(RwReg*)0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
+#define REG_SMC_CYCLE3 (*(RwReg*)0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
+#define REG_SMC_MODE3  (*(RwReg*)0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
+#define REG_SMC_SETUP4 (*(RwReg*)0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */
+#define REG_SMC_PULSE4 (*(RwReg*)0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */
+#define REG_SMC_CYCLE4 (*(RwReg*)0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */
+#define REG_SMC_MODE4  (*(RwReg*)0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */
+#define REG_SMC_OCMS   (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */
+#define REG_SMC_KEY1   (*(WoReg*)0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
+#define REG_SMC_KEY2   (*(WoReg*)0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
+#define REG_SMC_WPMR   (*(RwReg*)0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
+#define REG_SMC_WPSR   (*(RoReg*)0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_SMC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_spi.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_spi.h
new file mode 100644
index 0000000..d315420
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_spi.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_SPI_INSTANCE_
+#define _SAM4S_SPI_INSTANCE_
+
+/* ========== Register definition for SPI peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SPI_CR              (0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR              (0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR             (0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR             (0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR              (0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER             (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR             (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR             (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR             (0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR            (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR            (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR             (0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR             (0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR             (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR             (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR            (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR            (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR            (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR            (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR            (0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR            (0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#else
+#define REG_SPI_CR     (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */
+#define REG_SPI_MR     (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */
+#define REG_SPI_RDR    (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */
+#define REG_SPI_TDR    (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */
+#define REG_SPI_SR     (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */
+#define REG_SPI_IER    (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
+#define REG_SPI_IDR    (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
+#define REG_SPI_IMR    (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
+#define REG_SPI_CSR    (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */
+#define REG_SPI_WPMR   (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
+#define REG_SPI_WPSR   (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
+#define REG_SPI_RPR    (*(RwReg*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */
+#define REG_SPI_RCR    (*(RwReg*)0x40008104U) /**< \brief (SPI) Receive Counter Register */
+#define REG_SPI_TPR    (*(RwReg*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
+#define REG_SPI_TCR    (*(RwReg*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
+#define REG_SPI_RNPR   (*(RwReg*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
+#define REG_SPI_RNCR   (*(RwReg*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
+#define REG_SPI_TNPR   (*(RwReg*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
+#define REG_SPI_TNCR   (*(RwReg*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
+#define REG_SPI_PTCR   (*(WoReg*)0x40008120U) /**< \brief (SPI) Transfer Control Register */
+#define REG_SPI_PTSR   (*(RoReg*)0x40008124U) /**< \brief (SPI) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_SPI_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_ssc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_ssc.h
new file mode 100644
index 0000000..04278ae
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_ssc.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_SSC_INSTANCE_
+#define _SAM4S_SSC_INSTANCE_
+
+/* ========== Register definition for SSC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SSC_CR            (0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR           (0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR          (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR          (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR          (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR          (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR           (0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR           (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR          (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR          (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R          (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R          (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR            (0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER           (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR           (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR           (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR          (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR          (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#define REG_SSC_RPR           (0x40004100U) /**< \brief (SSC) Receive Pointer Register */
+#define REG_SSC_RCR           (0x40004104U) /**< \brief (SSC) Receive Counter Register */
+#define REG_SSC_TPR           (0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
+#define REG_SSC_TCR           (0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
+#define REG_SSC_RNPR          (0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
+#define REG_SSC_RNCR          (0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
+#define REG_SSC_TNPR          (0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
+#define REG_SSC_TNCR          (0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
+#define REG_SSC_PTCR          (0x40004120U) /**< \brief (SSC) Transfer Control Register */
+#define REG_SSC_PTSR          (0x40004124U) /**< \brief (SSC) Transfer Status Register */
+#else
+#define REG_SSC_CR   (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */
+#define REG_SSC_CMR  (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
+#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
+#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
+#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
+#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
+#define REG_SSC_RHR  (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
+#define REG_SSC_THR  (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
+#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
+#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
+#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
+#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
+#define REG_SSC_SR   (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */
+#define REG_SSC_IER  (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
+#define REG_SSC_IDR  (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
+#define REG_SSC_IMR  (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
+#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
+#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
+#define REG_SSC_RPR  (*(RwReg*)0x40004100U) /**< \brief (SSC) Receive Pointer Register */
+#define REG_SSC_RCR  (*(RwReg*)0x40004104U) /**< \brief (SSC) Receive Counter Register */
+#define REG_SSC_TPR  (*(RwReg*)0x40004108U) /**< \brief (SSC) Transmit Pointer Register */
+#define REG_SSC_TCR  (*(RwReg*)0x4000410CU) /**< \brief (SSC) Transmit Counter Register */
+#define REG_SSC_RNPR (*(RwReg*)0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */
+#define REG_SSC_RNCR (*(RwReg*)0x40004114U) /**< \brief (SSC) Receive Next Counter Register */
+#define REG_SSC_TNPR (*(RwReg*)0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */
+#define REG_SSC_TNCR (*(RwReg*)0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */
+#define REG_SSC_PTCR (*(WoReg*)0x40004120U) /**< \brief (SSC) Transfer Control Register */
+#define REG_SSC_PTSR (*(RoReg*)0x40004124U) /**< \brief (SSC) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_SSC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_supc.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_supc.h
new file mode 100644
index 0000000..4593970
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_supc.h
@@ -0,0 +1,50 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_SUPC_INSTANCE_
+#define _SAM4S_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SUPC_CR            (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR          (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR            (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR          (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR          (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR            (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#else
+#define REG_SUPC_CR   (*(WoReg*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
+#define REG_SUPC_MR   (*(RwReg*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
+#define REG_SUPC_WUMR (*(RwReg*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
+#define REG_SUPC_SR   (*(RoReg*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_SUPC_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_tc0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_tc0.h
new file mode 100644
index 0000000..a315f27
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_tc0.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_TC0_INSTANCE_
+#define _SAM4S_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC0_CCR0           (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0           (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0          (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0            (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0            (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0            (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0            (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0            (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0           (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0           (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0           (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1           (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1           (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1          (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1            (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1            (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1            (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1            (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1            (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1           (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1           (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1           (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2           (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2           (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2          (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2            (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2            (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2            (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2            (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2            (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2           (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2           (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2           (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR            (0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR            (0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER           (0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR           (0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR           (0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR           (0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR            (0x400100D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR           (0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#else
+#define REG_TC0_CCR0  (*(WoReg*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
+#define REG_TC0_CMR0  (*(RwReg*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
+#define REG_TC0_SMMR0 (*(RwReg*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC0_CV0   (*(RoReg*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
+#define REG_TC0_RA0   (*(RwReg*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
+#define REG_TC0_RB0   (*(RwReg*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
+#define REG_TC0_RC0   (*(RwReg*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
+#define REG_TC0_SR0   (*(RoReg*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
+#define REG_TC0_IER0  (*(WoReg*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
+#define REG_TC0_IDR0  (*(WoReg*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
+#define REG_TC0_IMR0  (*(RoReg*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
+#define REG_TC0_CCR1  (*(WoReg*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
+#define REG_TC0_CMR1  (*(RwReg*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
+#define REG_TC0_SMMR1 (*(RwReg*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC0_CV1   (*(RoReg*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
+#define REG_TC0_RA1   (*(RwReg*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
+#define REG_TC0_RB1   (*(RwReg*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
+#define REG_TC0_RC1   (*(RwReg*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
+#define REG_TC0_SR1   (*(RoReg*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
+#define REG_TC0_IER1  (*(WoReg*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
+#define REG_TC0_IDR1  (*(WoReg*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
+#define REG_TC0_IMR1  (*(RoReg*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
+#define REG_TC0_CCR2  (*(WoReg*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
+#define REG_TC0_CMR2  (*(RwReg*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
+#define REG_TC0_SMMR2 (*(RwReg*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC0_CV2   (*(RoReg*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
+#define REG_TC0_RA2   (*(RwReg*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
+#define REG_TC0_RB2   (*(RwReg*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
+#define REG_TC0_RC2   (*(RwReg*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
+#define REG_TC0_SR2   (*(RoReg*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
+#define REG_TC0_IER2  (*(WoReg*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
+#define REG_TC0_IDR2  (*(WoReg*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
+#define REG_TC0_IMR2  (*(RoReg*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
+#define REG_TC0_BCR   (*(WoReg*)0x400100C0U) /**< \brief (TC0) Block Control Register */
+#define REG_TC0_BMR   (*(RwReg*)0x400100C4U) /**< \brief (TC0) Block Mode Register */
+#define REG_TC0_QIER  (*(WoReg*)0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
+#define REG_TC0_QIDR  (*(WoReg*)0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
+#define REG_TC0_QIMR  (*(RoReg*)0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
+#define REG_TC0_QISR  (*(RoReg*)0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
+#define REG_TC0_FMR   (*(RwReg*)0x400100D8U) /**< \brief (TC0) Fault Mode Register */
+#define REG_TC0_WPMR  (*(RwReg*)0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_TC0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_tc1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_tc1.h
new file mode 100644
index 0000000..5080f60
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_tc1.h
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_TC1_INSTANCE_
+#define _SAM4S_TC1_INSTANCE_
+
+/* ========== Register definition for TC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC1_CCR0           (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0           (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0          (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0            (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0            (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0            (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0            (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0            (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0           (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0           (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0           (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1           (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1           (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1          (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1            (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1            (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1            (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1            (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1            (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1           (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1           (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1           (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2           (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2           (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2          (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2            (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2            (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2            (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2            (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2            (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2           (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2           (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2           (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR            (0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR            (0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER           (0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR           (0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR           (0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR           (0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR            (0x400140D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR           (0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#else
+#define REG_TC1_CCR0  (*(WoReg*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
+#define REG_TC1_CMR0  (*(RwReg*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
+#define REG_TC1_SMMR0 (*(RwReg*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
+#define REG_TC1_CV0   (*(RoReg*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
+#define REG_TC1_RA0   (*(RwReg*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
+#define REG_TC1_RB0   (*(RwReg*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
+#define REG_TC1_RC0   (*(RwReg*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
+#define REG_TC1_SR0   (*(RoReg*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
+#define REG_TC1_IER0  (*(WoReg*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
+#define REG_TC1_IDR0  (*(WoReg*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
+#define REG_TC1_IMR0  (*(RoReg*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
+#define REG_TC1_CCR1  (*(WoReg*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
+#define REG_TC1_CMR1  (*(RwReg*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
+#define REG_TC1_SMMR1 (*(RwReg*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
+#define REG_TC1_CV1   (*(RoReg*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
+#define REG_TC1_RA1   (*(RwReg*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
+#define REG_TC1_RB1   (*(RwReg*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
+#define REG_TC1_RC1   (*(RwReg*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
+#define REG_TC1_SR1   (*(RoReg*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
+#define REG_TC1_IER1  (*(WoReg*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
+#define REG_TC1_IDR1  (*(WoReg*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
+#define REG_TC1_IMR1  (*(RoReg*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
+#define REG_TC1_CCR2  (*(WoReg*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
+#define REG_TC1_CMR2  (*(RwReg*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
+#define REG_TC1_SMMR2 (*(RwReg*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
+#define REG_TC1_CV2   (*(RoReg*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
+#define REG_TC1_RA2   (*(RwReg*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
+#define REG_TC1_RB2   (*(RwReg*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
+#define REG_TC1_RC2   (*(RwReg*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
+#define REG_TC1_SR2   (*(RoReg*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
+#define REG_TC1_IER2  (*(WoReg*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
+#define REG_TC1_IDR2  (*(WoReg*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
+#define REG_TC1_IMR2  (*(RoReg*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
+#define REG_TC1_BCR   (*(WoReg*)0x400140C0U) /**< \brief (TC1) Block Control Register */
+#define REG_TC1_BMR   (*(RwReg*)0x400140C4U) /**< \brief (TC1) Block Mode Register */
+#define REG_TC1_QIER  (*(WoReg*)0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
+#define REG_TC1_QIDR  (*(WoReg*)0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
+#define REG_TC1_QIMR  (*(RoReg*)0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
+#define REG_TC1_QISR  (*(RoReg*)0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
+#define REG_TC1_FMR   (*(RwReg*)0x400140D8U) /**< \brief (TC1) Fault Mode Register */
+#define REG_TC1_WPMR  (*(RwReg*)0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_TC1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_twi0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_twi0.h
new file mode 100644
index 0000000..065efad
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_twi0.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_TWI0_INSTANCE_
+#define _SAM4S_TWI0_INSTANCE_
+
+/* ========== Register definition for TWI0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TWI0_CR            (0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR           (0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR           (0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR          (0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR          (0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR            (0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER           (0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR           (0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR           (0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR           (0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR           (0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR           (0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR           (0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR           (0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR           (0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR          (0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR          (0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR          (0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR          (0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR          (0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR          (0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#else
+#define REG_TWI0_CR   (*(WoReg*)0x40018000U) /**< \brief (TWI0) Control Register */
+#define REG_TWI0_MMR  (*(RwReg*)0x40018004U) /**< \brief (TWI0) Master Mode Register */
+#define REG_TWI0_SMR  (*(RwReg*)0x40018008U) /**< \brief (TWI0) Slave Mode Register */
+#define REG_TWI0_IADR (*(RwReg*)0x4001800CU) /**< \brief (TWI0) Internal Address Register */
+#define REG_TWI0_CWGR (*(RwReg*)0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
+#define REG_TWI0_SR   (*(RoReg*)0x40018020U) /**< \brief (TWI0) Status Register */
+#define REG_TWI0_IER  (*(WoReg*)0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
+#define REG_TWI0_IDR  (*(WoReg*)0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
+#define REG_TWI0_IMR  (*(RoReg*)0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
+#define REG_TWI0_RHR  (*(RoReg*)0x40018030U) /**< \brief (TWI0) Receive Holding Register */
+#define REG_TWI0_THR  (*(WoReg*)0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
+#define REG_TWI0_RPR  (*(RwReg*)0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
+#define REG_TWI0_RCR  (*(RwReg*)0x40018104U) /**< \brief (TWI0) Receive Counter Register */
+#define REG_TWI0_TPR  (*(RwReg*)0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
+#define REG_TWI0_TCR  (*(RwReg*)0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
+#define REG_TWI0_RNPR (*(RwReg*)0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
+#define REG_TWI0_RNCR (*(RwReg*)0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
+#define REG_TWI0_TNPR (*(RwReg*)0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
+#define REG_TWI0_TNCR (*(RwReg*)0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
+#define REG_TWI0_PTCR (*(WoReg*)0x40018120U) /**< \brief (TWI0) Transfer Control Register */
+#define REG_TWI0_PTSR (*(RoReg*)0x40018124U) /**< \brief (TWI0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_TWI0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_twi1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_twi1.h
new file mode 100644
index 0000000..ef97006
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_twi1.h
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_TWI1_INSTANCE_
+#define _SAM4S_TWI1_INSTANCE_
+
+/* ========== Register definition for TWI1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TWI1_CR            (0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR           (0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR           (0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR          (0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR          (0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR            (0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER           (0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR           (0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR           (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR           (0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR           (0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR           (0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR           (0x4001C104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR           (0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR           (0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR          (0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR          (0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR          (0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR          (0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR          (0x4001C120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR          (0x4001C124U) /**< \brief (TWI1) Transfer Status Register */
+#else
+#define REG_TWI1_CR   (*(WoReg*)0x4001C000U) /**< \brief (TWI1) Control Register */
+#define REG_TWI1_MMR  (*(RwReg*)0x4001C004U) /**< \brief (TWI1) Master Mode Register */
+#define REG_TWI1_SMR  (*(RwReg*)0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
+#define REG_TWI1_IADR (*(RwReg*)0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
+#define REG_TWI1_CWGR (*(RwReg*)0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
+#define REG_TWI1_SR   (*(RoReg*)0x4001C020U) /**< \brief (TWI1) Status Register */
+#define REG_TWI1_IER  (*(WoReg*)0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
+#define REG_TWI1_IDR  (*(WoReg*)0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
+#define REG_TWI1_IMR  (*(RoReg*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
+#define REG_TWI1_RHR  (*(RoReg*)0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
+#define REG_TWI1_THR  (*(WoReg*)0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
+#define REG_TWI1_RPR  (*(RwReg*)0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */
+#define REG_TWI1_RCR  (*(RwReg*)0x4001C104U) /**< \brief (TWI1) Receive Counter Register */
+#define REG_TWI1_TPR  (*(RwReg*)0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */
+#define REG_TWI1_TCR  (*(RwReg*)0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */
+#define REG_TWI1_RNPR (*(RwReg*)0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */
+#define REG_TWI1_RNCR (*(RwReg*)0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */
+#define REG_TWI1_TNPR (*(RwReg*)0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */
+#define REG_TWI1_TNCR (*(RwReg*)0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */
+#define REG_TWI1_PTCR (*(WoReg*)0x4001C120U) /**< \brief (TWI1) Transfer Control Register */
+#define REG_TWI1_PTSR (*(RoReg*)0x4001C124U) /**< \brief (TWI1) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_TWI1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_uart0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_uart0.h
new file mode 100644
index 0000000..4bfb08f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_uart0.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_UART0_INSTANCE_
+#define _SAM4S_UART0_INSTANCE_
+
+/* ========== Register definition for UART0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UART0_CR            (0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR            (0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER           (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR           (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR           (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR            (0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR           (0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR           (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR          (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR           (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR           (0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR           (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR           (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR          (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR          (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR          (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR          (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR          (0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR          (0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#else
+#define REG_UART0_CR   (*(WoReg*)0x400E0600U) /**< \brief (UART0) Control Register */
+#define REG_UART0_MR   (*(RwReg*)0x400E0604U) /**< \brief (UART0) Mode Register */
+#define REG_UART0_IER  (*(WoReg*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
+#define REG_UART0_IDR  (*(WoReg*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
+#define REG_UART0_IMR  (*(RoReg*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
+#define REG_UART0_SR   (*(RoReg*)0x400E0614U) /**< \brief (UART0) Status Register */
+#define REG_UART0_RHR  (*(RoReg*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */
+#define REG_UART0_THR  (*(WoReg*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
+#define REG_UART0_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
+#define REG_UART0_RPR  (*(RwReg*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
+#define REG_UART0_RCR  (*(RwReg*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */
+#define REG_UART0_TPR  (*(RwReg*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
+#define REG_UART0_TCR  (*(RwReg*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
+#define REG_UART0_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
+#define REG_UART0_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
+#define REG_UART0_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
+#define REG_UART0_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
+#define REG_UART0_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */
+#define REG_UART0_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_UART0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_uart1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_uart1.h
new file mode 100644
index 0000000..c71ae11
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_uart1.h
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_UART1_INSTANCE_
+#define _SAM4S_UART1_INSTANCE_
+
+/* ========== Register definition for UART1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UART1_CR            (0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR            (0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER           (0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR           (0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR           (0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR            (0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR           (0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR           (0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR          (0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#define REG_UART1_RPR           (0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
+#define REG_UART1_RCR           (0x400E0904U) /**< \brief (UART1) Receive Counter Register */
+#define REG_UART1_TPR           (0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
+#define REG_UART1_TCR           (0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
+#define REG_UART1_RNPR          (0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
+#define REG_UART1_RNCR          (0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
+#define REG_UART1_TNPR          (0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
+#define REG_UART1_TNCR          (0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
+#define REG_UART1_PTCR          (0x400E0920U) /**< \brief (UART1) Transfer Control Register */
+#define REG_UART1_PTSR          (0x400E0924U) /**< \brief (UART1) Transfer Status Register */
+#else
+#define REG_UART1_CR   (*(WoReg*)0x400E0800U) /**< \brief (UART1) Control Register */
+#define REG_UART1_MR   (*(RwReg*)0x400E0804U) /**< \brief (UART1) Mode Register */
+#define REG_UART1_IER  (*(WoReg*)0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
+#define REG_UART1_IDR  (*(WoReg*)0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
+#define REG_UART1_IMR  (*(RoReg*)0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
+#define REG_UART1_SR   (*(RoReg*)0x400E0814U) /**< \brief (UART1) Status Register */
+#define REG_UART1_RHR  (*(RoReg*)0x400E0818U) /**< \brief (UART1) Receive Holding Register */
+#define REG_UART1_THR  (*(WoReg*)0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
+#define REG_UART1_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
+#define REG_UART1_RPR  (*(RwReg*)0x400E0900U) /**< \brief (UART1) Receive Pointer Register */
+#define REG_UART1_RCR  (*(RwReg*)0x400E0904U) /**< \brief (UART1) Receive Counter Register */
+#define REG_UART1_TPR  (*(RwReg*)0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */
+#define REG_UART1_TCR  (*(RwReg*)0x400E090CU) /**< \brief (UART1) Transmit Counter Register */
+#define REG_UART1_RNPR (*(RwReg*)0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */
+#define REG_UART1_RNCR (*(RwReg*)0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */
+#define REG_UART1_TNPR (*(RwReg*)0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */
+#define REG_UART1_TNCR (*(RwReg*)0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */
+#define REG_UART1_PTCR (*(WoReg*)0x400E0920U) /**< \brief (UART1) Transfer Control Register */
+#define REG_UART1_PTSR (*(RoReg*)0x400E0924U) /**< \brief (UART1) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_UART1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_udp.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_udp.h
new file mode 100644
index 0000000..13f8a8c
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_udp.h
@@ -0,0 +1,62 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_UDP_INSTANCE_
+#define _SAM4S_UDP_INSTANCE_
+
+/* ========== Register definition for UDP peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_UDP_FRM_NUM           (0x40034000U) /**< \brief (UDP) Frame Number Register */
+#define REG_UDP_GLB_STAT          (0x40034004U) /**< \brief (UDP) Global State Register */
+#define REG_UDP_FADDR             (0x40034008U) /**< \brief (UDP) Function Address Register */
+#define REG_UDP_IER               (0x40034010U) /**< \brief (UDP) Interrupt Enable Register */
+#define REG_UDP_IDR               (0x40034014U) /**< \brief (UDP) Interrupt Disable Register */
+#define REG_UDP_IMR               (0x40034018U) /**< \brief (UDP) Interrupt Mask Register */
+#define REG_UDP_ISR               (0x4003401CU) /**< \brief (UDP) Interrupt Status Register */
+#define REG_UDP_ICR               (0x40034020U) /**< \brief (UDP) Interrupt Clear Register */
+#define REG_UDP_RST_EP            (0x40034028U) /**< \brief (UDP) Reset Endpoint Register */
+#define REG_UDP_CSR               (0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */
+#define REG_UDP_FDR               (0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */
+#define REG_UDP_TXVC              (0x40034074U) /**< \brief (UDP) Transceiver Control Register */
+#else
+#define REG_UDP_FRM_NUM  (*(RoReg*)0x40034000U) /**< \brief (UDP) Frame Number Register */
+#define REG_UDP_GLB_STAT (*(RwReg*)0x40034004U) /**< \brief (UDP) Global State Register */
+#define REG_UDP_FADDR    (*(RwReg*)0x40034008U) /**< \brief (UDP) Function Address Register */
+#define REG_UDP_IER      (*(WoReg*)0x40034010U) /**< \brief (UDP) Interrupt Enable Register */
+#define REG_UDP_IDR      (*(WoReg*)0x40034014U) /**< \brief (UDP) Interrupt Disable Register */
+#define REG_UDP_IMR      (*(RoReg*)0x40034018U) /**< \brief (UDP) Interrupt Mask Register */
+#define REG_UDP_ISR      (*(RoReg*)0x4003401CU) /**< \brief (UDP) Interrupt Status Register */
+#define REG_UDP_ICR      (*(WoReg*)0x40034020U) /**< \brief (UDP) Interrupt Clear Register */
+#define REG_UDP_RST_EP   (*(RwReg*)0x40034028U) /**< \brief (UDP) Reset Endpoint Register */
+#define REG_UDP_CSR      (*(RwReg*)0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */
+#define REG_UDP_FDR      (*(RwReg*)0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */
+#define REG_UDP_TXVC     (*(RwReg*)0x40034074U) /**< \brief (UDP) Transceiver Control Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_UDP_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_usart0.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_usart0.h
new file mode 100644
index 0000000..8d2dc13
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_usart0.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_USART0_INSTANCE_
+#define _SAM4S_USART0_INSTANCE_
+
+/* ========== Register definition for USART0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART0_CR            (0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR            (0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER           (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR           (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR           (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR           (0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR           (0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR           (0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR          (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR          (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR          (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI          (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER           (0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF            (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN           (0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR          (0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR          (0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_VERSION          (0x400240FCU) /**< \brief (USART0) Version Register */
+#define REG_USART0_RPR           (0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR           (0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR           (0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR           (0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR          (0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR          (0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR          (0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR          (0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR          (0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR          (0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#else
+#define REG_USART0_CR   (*(WoReg*)0x40024000U) /**< \brief (USART0) Control Register */
+#define REG_USART0_MR   (*(RwReg*)0x40024004U) /**< \brief (USART0) Mode Register */
+#define REG_USART0_IER  (*(WoReg*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
+#define REG_USART0_IDR  (*(WoReg*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
+#define REG_USART0_IMR  (*(RoReg*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
+#define REG_USART0_CSR  (*(RoReg*)0x40024014U) /**< \brief (USART0) Channel Status Register */
+#define REG_USART0_RHR  (*(RoReg*)0x40024018U) /**< \brief (USART0) Receiver Holding Register */
+#define REG_USART0_THR  (*(WoReg*)0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
+#define REG_USART0_BRGR (*(RwReg*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
+#define REG_USART0_RTOR (*(RwReg*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
+#define REG_USART0_TTGR (*(RwReg*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
+#define REG_USART0_FIDI (*(RwReg*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
+#define REG_USART0_NER  (*(RoReg*)0x40024044U) /**< \brief (USART0) Number of Errors Register */
+#define REG_USART0_IF   (*(RwReg*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
+#define REG_USART0_MAN  (*(RwReg*)0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
+#define REG_USART0_WPMR (*(RwReg*)0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
+#define REG_USART0_WPSR (*(RoReg*)0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
+#define REG_USART0_VERSION (*(RoReg*)0x400240FCU) /**< \brief (USART0) Version Register */
+#define REG_USART0_RPR  (*(RwReg*)0x40024100U) /**< \brief (USART0) Receive Pointer Register */
+#define REG_USART0_RCR  (*(RwReg*)0x40024104U) /**< \brief (USART0) Receive Counter Register */
+#define REG_USART0_TPR  (*(RwReg*)0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
+#define REG_USART0_TCR  (*(RwReg*)0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
+#define REG_USART0_RNPR (*(RwReg*)0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
+#define REG_USART0_RNCR (*(RwReg*)0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
+#define REG_USART0_TNPR (*(RwReg*)0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
+#define REG_USART0_TNCR (*(RwReg*)0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
+#define REG_USART0_PTCR (*(WoReg*)0x40024120U) /**< \brief (USART0) Transfer Control Register */
+#define REG_USART0_PTSR (*(RoReg*)0x40024124U) /**< \brief (USART0) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_USART0_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_usart1.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_usart1.h
new file mode 100644
index 0000000..6ff0a11
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_usart1.h
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_USART1_INSTANCE_
+#define _SAM4S_USART1_INSTANCE_
+
+/* ========== Register definition for USART1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USART1_CR            (0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR            (0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER           (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR           (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR           (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR           (0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR           (0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR           (0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR          (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR          (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR          (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI          (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER           (0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF            (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN           (0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR          (0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR          (0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_VERSION          (0x400280FCU) /**< \brief (USART1) Version Register */
+#define REG_USART1_RPR           (0x40028100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR           (0x40028104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR           (0x40028108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR           (0x4002810CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR          (0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR          (0x40028114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR          (0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR          (0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR          (0x40028120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR          (0x40028124U) /**< \brief (USART1) Transfer Status Register */
+#else
+#define REG_USART1_CR   (*(WoReg*)0x40028000U) /**< \brief (USART1) Control Register */
+#define REG_USART1_MR   (*(RwReg*)0x40028004U) /**< \brief (USART1) Mode Register */
+#define REG_USART1_IER  (*(WoReg*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
+#define REG_USART1_IDR  (*(WoReg*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
+#define REG_USART1_IMR  (*(RoReg*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
+#define REG_USART1_CSR  (*(RoReg*)0x40028014U) /**< \brief (USART1) Channel Status Register */
+#define REG_USART1_RHR  (*(RoReg*)0x40028018U) /**< \brief (USART1) Receiver Holding Register */
+#define REG_USART1_THR  (*(WoReg*)0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
+#define REG_USART1_BRGR (*(RwReg*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
+#define REG_USART1_RTOR (*(RwReg*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
+#define REG_USART1_TTGR (*(RwReg*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
+#define REG_USART1_FIDI (*(RwReg*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
+#define REG_USART1_NER  (*(RoReg*)0x40028044U) /**< \brief (USART1) Number of Errors Register */
+#define REG_USART1_IF   (*(RwReg*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
+#define REG_USART1_MAN  (*(RwReg*)0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
+#define REG_USART1_WPMR (*(RwReg*)0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
+#define REG_USART1_WPSR (*(RoReg*)0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
+#define REG_USART1_VERSION (*(RoReg*)0x400280FCU) /**< \brief (USART1) Version Register */
+#define REG_USART1_RPR  (*(RwReg*)0x40028100U) /**< \brief (USART1) Receive Pointer Register */
+#define REG_USART1_RCR  (*(RwReg*)0x40028104U) /**< \brief (USART1) Receive Counter Register */
+#define REG_USART1_TPR  (*(RwReg*)0x40028108U) /**< \brief (USART1) Transmit Pointer Register */
+#define REG_USART1_TCR  (*(RwReg*)0x4002810CU) /**< \brief (USART1) Transmit Counter Register */
+#define REG_USART1_RNPR (*(RwReg*)0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */
+#define REG_USART1_RNCR (*(RwReg*)0x40028114U) /**< \brief (USART1) Receive Next Counter Register */
+#define REG_USART1_TNPR (*(RwReg*)0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */
+#define REG_USART1_TNCR (*(RwReg*)0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */
+#define REG_USART1_PTCR (*(WoReg*)0x40028120U) /**< \brief (USART1) Transfer Control Register */
+#define REG_USART1_PTSR (*(RoReg*)0x40028124U) /**< \brief (USART1) Transfer Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_USART1_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_wdt.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_wdt.h
new file mode 100644
index 0000000..f4f1e95
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/instance/instance_wdt.h
@@ -0,0 +1,44 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_WDT_INSTANCE_
+#define _SAM4S_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CR          (0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR          (0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR          (0x400E1458U) /**< \brief (WDT) Status Register */
+#else
+#define REG_WDT_CR (*(WoReg*)0x400E1450U) /**< \brief (WDT) Control Register */
+#define REG_WDT_MR (*(RwReg*)0x400E1454U) /**< \brief (WDT) Mode Register */
+#define REG_WDT_SR (*(RoReg*)0x400E1458U) /**< \brief (WDT) Status Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#endif /* _SAM4S_WDT_INSTANCE_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/pio/pio_sam4s16b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/pio/pio_sam4s16b.h
new file mode 100644
index 0000000..3a23597
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/pio/pio_sam4s16b.h
@@ -0,0 +1,353 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S16B_PIO_
+#define _SAM4S16B_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM4S16B_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/pio/pio_sam4s16c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/pio/pio_sam4s16c.h
new file mode 100644
index 0000000..b296045
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/pio/pio_sam4s16c.h
@@ -0,0 +1,397 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S16C_PIO_
+#define _SAM4S16C_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC18A_A0       (1u << 18) /**< \brief Ebi signal: A0 */
+#define PIO_PC19A_A1       (1u << 19) /**< \brief Ebi signal: A1 */
+#define PIO_PC28A_A10      (1u << 28) /**< \brief Ebi signal: A10 */
+#define PIO_PC29A_A11      (1u << 29) /**< \brief Ebi signal: A11 */
+#define PIO_PC30A_A12      (1u << 30) /**< \brief Ebi signal: A12 */
+#define PIO_PC31A_A13      (1u << 31) /**< \brief Ebi signal: A13 */
+#define PIO_PA18C_A14      (1u << 18) /**< \brief Ebi signal: A14 */
+#define PIO_PA19C_A15      (1u << 19) /**< \brief Ebi signal: A15 */
+#define PIO_PA20C_A16      (1u << 20) /**< \brief Ebi signal: A16 */
+#define PIO_PA0C_A17       (1u << 0)  /**< \brief Ebi signal: A17 */
+#define PIO_PA1C_A18       (1u << 1)  /**< \brief Ebi signal: A18 */
+#define PIO_PA23C_A19      (1u << 23) /**< \brief Ebi signal: A19 */
+#define PIO_PC20A_A2       (1u << 20) /**< \brief Ebi signal: A2 */
+#define PIO_PA24C_A20      (1u << 24) /**< \brief Ebi signal: A20 */
+#define PIO_PC16A_A21      (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC16A_NANDALE  (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC17A_A22      (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC17A_NANDCLE  (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PA25C_A23      (1u << 25) /**< \brief Ebi signal: A23 */
+#define PIO_PC21A_A3       (1u << 21) /**< \brief Ebi signal: A3 */
+#define PIO_PC22A_A4       (1u << 22) /**< \brief Ebi signal: A4 */
+#define PIO_PC23A_A5       (1u << 23) /**< \brief Ebi signal: A5 */
+#define PIO_PC24A_A6       (1u << 24) /**< \brief Ebi signal: A6 */
+#define PIO_PC25A_A7       (1u << 25) /**< \brief Ebi signal: A7 */
+#define PIO_PC26A_A8       (1u << 26) /**< \brief Ebi signal: A8 */
+#define PIO_PC27A_A9       (1u << 27) /**< \brief Ebi signal: A9 */
+#define PIO_PC0A_D0        (1u << 0)  /**< \brief Ebi signal: D0 */
+#define PIO_PC1A_D1        (1u << 1)  /**< \brief Ebi signal: D1 */
+#define PIO_PC2A_D2        (1u << 2)  /**< \brief Ebi signal: D2 */
+#define PIO_PC3A_D3        (1u << 3)  /**< \brief Ebi signal: D3 */
+#define PIO_PC4A_D4        (1u << 4)  /**< \brief Ebi signal: D4 */
+#define PIO_PC5A_D5        (1u << 5)  /**< \brief Ebi signal: D5 */
+#define PIO_PC6A_D6        (1u << 6)  /**< \brief Ebi signal: D6 */
+#define PIO_PC7A_D7        (1u << 7)  /**< \brief Ebi signal: D7 */
+#define PIO_PC9A_NANDOE    (1u << 9)  /**< \brief Ebi signal: NANDOE */
+#define PIO_PC10A_NANDWE   (1u << 10) /**< \brief Ebi signal: NANDWE */
+#define PIO_PC14A_NCS0     (1u << 14) /**< \brief Ebi signal: NCS0 */
+#define PIO_PC15A_NCS1     (1u << 15) /**< \brief Ebi signal: NCS1 */
+#define PIO_PA22C_NCS2     (1u << 22) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC12A_NCS3     (1u << 12) /**< \brief Ebi signal: NCS3 */
+#define PIO_PC11A_NRD      (1u << 11) /**< \brief Ebi signal: NRD */
+#define PIO_PC13A_NWAIT    (1u << 13) /**< \brief Ebi signal: NWAIT */
+#define PIO_PC8A_NWE       (1u << 8)  /**< \brief Ebi signal: NWE */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM4S16C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/pio/pio_sam4s8b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/pio/pio_sam4s8b.h
new file mode 100644
index 0000000..cd537f8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/pio/pio_sam4s8b.h
@@ -0,0 +1,353 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S8B_PIO_
+#define _SAM4S8B_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM4S8B_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/pio/pio_sam4s8c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/pio/pio_sam4s8c.h
new file mode 100644
index 0000000..fc32463
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/pio/pio_sam4s8c.h
@@ -0,0 +1,397 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S8C_PIO_
+#define _SAM4S8C_PIO_
+
+#define PIO_PA0            (1u << 0)  /**< \brief Pin Controlled by PA0 */
+#define PIO_PA1            (1u << 1)  /**< \brief Pin Controlled by PA1 */
+#define PIO_PA2            (1u << 2)  /**< \brief Pin Controlled by PA2 */
+#define PIO_PA3            (1u << 3)  /**< \brief Pin Controlled by PA3 */
+#define PIO_PA4            (1u << 4)  /**< \brief Pin Controlled by PA4 */
+#define PIO_PA5            (1u << 5)  /**< \brief Pin Controlled by PA5 */
+#define PIO_PA6            (1u << 6)  /**< \brief Pin Controlled by PA6 */
+#define PIO_PA7            (1u << 7)  /**< \brief Pin Controlled by PA7 */
+#define PIO_PA8            (1u << 8)  /**< \brief Pin Controlled by PA8 */
+#define PIO_PA9            (1u << 9)  /**< \brief Pin Controlled by PA9 */
+#define PIO_PA10           (1u << 10) /**< \brief Pin Controlled by PA10 */
+#define PIO_PA11           (1u << 11) /**< \brief Pin Controlled by PA11 */
+#define PIO_PA12           (1u << 12) /**< \brief Pin Controlled by PA12 */
+#define PIO_PA13           (1u << 13) /**< \brief Pin Controlled by PA13 */
+#define PIO_PA14           (1u << 14) /**< \brief Pin Controlled by PA14 */
+#define PIO_PA15           (1u << 15) /**< \brief Pin Controlled by PA15 */
+#define PIO_PA16           (1u << 16) /**< \brief Pin Controlled by PA16 */
+#define PIO_PA17           (1u << 17) /**< \brief Pin Controlled by PA17 */
+#define PIO_PA18           (1u << 18) /**< \brief Pin Controlled by PA18 */
+#define PIO_PA19           (1u << 19) /**< \brief Pin Controlled by PA19 */
+#define PIO_PA20           (1u << 20) /**< \brief Pin Controlled by PA20 */
+#define PIO_PA21           (1u << 21) /**< \brief Pin Controlled by PA21 */
+#define PIO_PA22           (1u << 22) /**< \brief Pin Controlled by PA22 */
+#define PIO_PA23           (1u << 23) /**< \brief Pin Controlled by PA23 */
+#define PIO_PA24           (1u << 24) /**< \brief Pin Controlled by PA24 */
+#define PIO_PA25           (1u << 25) /**< \brief Pin Controlled by PA25 */
+#define PIO_PA26           (1u << 26) /**< \brief Pin Controlled by PA26 */
+#define PIO_PA27           (1u << 27) /**< \brief Pin Controlled by PA27 */
+#define PIO_PA28           (1u << 28) /**< \brief Pin Controlled by PA28 */
+#define PIO_PA29           (1u << 29) /**< \brief Pin Controlled by PA29 */
+#define PIO_PA30           (1u << 30) /**< \brief Pin Controlled by PA30 */
+#define PIO_PA31           (1u << 31) /**< \brief Pin Controlled by PA31 */
+#define PIO_PB0            (1u << 0)  /**< \brief Pin Controlled by PB0 */
+#define PIO_PB1            (1u << 1)  /**< \brief Pin Controlled by PB1 */
+#define PIO_PB2            (1u << 2)  /**< \brief Pin Controlled by PB2 */
+#define PIO_PB3            (1u << 3)  /**< \brief Pin Controlled by PB3 */
+#define PIO_PB4            (1u << 4)  /**< \brief Pin Controlled by PB4 */
+#define PIO_PB5            (1u << 5)  /**< \brief Pin Controlled by PB5 */
+#define PIO_PB6            (1u << 6)  /**< \brief Pin Controlled by PB6 */
+#define PIO_PB7            (1u << 7)  /**< \brief Pin Controlled by PB7 */
+#define PIO_PB8            (1u << 8)  /**< \brief Pin Controlled by PB8 */
+#define PIO_PB9            (1u << 9)  /**< \brief Pin Controlled by PB9 */
+#define PIO_PB10           (1u << 10) /**< \brief Pin Controlled by PB10 */
+#define PIO_PB11           (1u << 11) /**< \brief Pin Controlled by PB11 */
+#define PIO_PB12           (1u << 12) /**< \brief Pin Controlled by PB12 */
+#define PIO_PB13           (1u << 13) /**< \brief Pin Controlled by PB13 */
+#define PIO_PB14           (1u << 14) /**< \brief Pin Controlled by PB14 */
+#define PIO_PC0            (1u << 0)  /**< \brief Pin Controlled by PC0 */
+#define PIO_PC1            (1u << 1)  /**< \brief Pin Controlled by PC1 */
+#define PIO_PC2            (1u << 2)  /**< \brief Pin Controlled by PC2 */
+#define PIO_PC3            (1u << 3)  /**< \brief Pin Controlled by PC3 */
+#define PIO_PC4            (1u << 4)  /**< \brief Pin Controlled by PC4 */
+#define PIO_PC5            (1u << 5)  /**< \brief Pin Controlled by PC5 */
+#define PIO_PC6            (1u << 6)  /**< \brief Pin Controlled by PC6 */
+#define PIO_PC7            (1u << 7)  /**< \brief Pin Controlled by PC7 */
+#define PIO_PC8            (1u << 8)  /**< \brief Pin Controlled by PC8 */
+#define PIO_PC9            (1u << 9)  /**< \brief Pin Controlled by PC9 */
+#define PIO_PC10           (1u << 10) /**< \brief Pin Controlled by PC10 */
+#define PIO_PC11           (1u << 11) /**< \brief Pin Controlled by PC11 */
+#define PIO_PC12           (1u << 12) /**< \brief Pin Controlled by PC12 */
+#define PIO_PC13           (1u << 13) /**< \brief Pin Controlled by PC13 */
+#define PIO_PC14           (1u << 14) /**< \brief Pin Controlled by PC14 */
+#define PIO_PC15           (1u << 15) /**< \brief Pin Controlled by PC15 */
+#define PIO_PC16           (1u << 16) /**< \brief Pin Controlled by PC16 */
+#define PIO_PC17           (1u << 17) /**< \brief Pin Controlled by PC17 */
+#define PIO_PC18           (1u << 18) /**< \brief Pin Controlled by PC18 */
+#define PIO_PC19           (1u << 19) /**< \brief Pin Controlled by PC19 */
+#define PIO_PC20           (1u << 20) /**< \brief Pin Controlled by PC20 */
+#define PIO_PC21           (1u << 21) /**< \brief Pin Controlled by PC21 */
+#define PIO_PC22           (1u << 22) /**< \brief Pin Controlled by PC22 */
+#define PIO_PC23           (1u << 23) /**< \brief Pin Controlled by PC23 */
+#define PIO_PC24           (1u << 24) /**< \brief Pin Controlled by PC24 */
+#define PIO_PC25           (1u << 25) /**< \brief Pin Controlled by PC25 */
+#define PIO_PC26           (1u << 26) /**< \brief Pin Controlled by PC26 */
+#define PIO_PC27           (1u << 27) /**< \brief Pin Controlled by PC27 */
+#define PIO_PC28           (1u << 28) /**< \brief Pin Controlled by PC28 */
+#define PIO_PC29           (1u << 29) /**< \brief Pin Controlled by PC29 */
+#define PIO_PC30           (1u << 30) /**< \brief Pin Controlled by PC30 */
+#define PIO_PC31           (1u << 31) /**< \brief Pin Controlled by PC31 */
+/* ========== Pio definition for ADC peripheral ========== */
+#define PIO_PA17X1_AD0     (1u << 17) /**< \brief Adc signal: AD0 */
+#define PIO_PA18X1_AD1     (1u << 18) /**< \brief Adc signal: AD1 */
+#define PIO_PC13X1_AD10    (1u << 13) /**< \brief Adc signal: AD10 */
+#define PIO_PC15X1_AD11    (1u << 15) /**< \brief Adc signal: AD11 */
+#define PIO_PC12X1_AD12    (1u << 12) /**< \brief Adc signal: AD12 */
+#define PIO_PC29X1_AD13    (1u << 29) /**< \brief Adc signal: AD13 */
+#define PIO_PC30X1_AD14    (1u << 30) /**< \brief Adc signal: AD14 */
+#define PIO_PA19X1_AD2     (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA19X1_WKUP9   (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
+#define PIO_PA20X1_AD3     (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PA20X1_WKUP10  (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
+#define PIO_PB0X1_AD4      (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB0X1_RTCOUT0  (1u << 0)  /**< \brief Adc signal: AD4/RTCOUT0 */
+#define PIO_PB1X1_AD5      (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB1X1_RTCOUT1  (1u << 1)  /**< \brief Adc signal: AD5/RTCOUT1 */
+#define PIO_PB2X1_AD6      (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB2X1_WKUP12   (1u << 2)  /**< \brief Adc signal: AD6/WKUP12 */
+#define PIO_PB3X1_AD7      (1u << 3)  /**< \brief Adc signal: AD7 */
+#define PIO_PA21X1_AD8     (1u << 21) /**< \brief Adc signal: AD8 */
+#define PIO_PA22X1_AD9     (1u << 22) /**< \brief Adc signal: AD9 */
+#define PIO_PA8B_ADTRG     (1u << 8)  /**< \brief Adc signal: ADTRG */
+/* ========== Pio definition for DACC peripheral ========== */
+#define PIO_PB13X1_DAC0    (1u << 13) /**< \brief Dacc signal: DAC0 */
+#define PIO_PB14X1_DAC1    (1u << 14) /**< \brief Dacc signal: DAC1 */
+#define PIO_PA2C_DATRG     (1u << 2)  /**< \brief Dacc signal: DATRG */
+/* ========== Pio definition for EBI peripheral ========== */
+#define PIO_PC18A_A0       (1u << 18) /**< \brief Ebi signal: A0 */
+#define PIO_PC19A_A1       (1u << 19) /**< \brief Ebi signal: A1 */
+#define PIO_PC28A_A10      (1u << 28) /**< \brief Ebi signal: A10 */
+#define PIO_PC29A_A11      (1u << 29) /**< \brief Ebi signal: A11 */
+#define PIO_PC30A_A12      (1u << 30) /**< \brief Ebi signal: A12 */
+#define PIO_PC31A_A13      (1u << 31) /**< \brief Ebi signal: A13 */
+#define PIO_PA18C_A14      (1u << 18) /**< \brief Ebi signal: A14 */
+#define PIO_PA19C_A15      (1u << 19) /**< \brief Ebi signal: A15 */
+#define PIO_PA20C_A16      (1u << 20) /**< \brief Ebi signal: A16 */
+#define PIO_PA0C_A17       (1u << 0)  /**< \brief Ebi signal: A17 */
+#define PIO_PA1C_A18       (1u << 1)  /**< \brief Ebi signal: A18 */
+#define PIO_PA23C_A19      (1u << 23) /**< \brief Ebi signal: A19 */
+#define PIO_PC20A_A2       (1u << 20) /**< \brief Ebi signal: A2 */
+#define PIO_PA24C_A20      (1u << 24) /**< \brief Ebi signal: A20 */
+#define PIO_PC16A_A21      (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC16A_NANDALE  (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
+#define PIO_PC17A_A22      (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PC17A_NANDCLE  (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
+#define PIO_PA25C_A23      (1u << 25) /**< \brief Ebi signal: A23 */
+#define PIO_PC21A_A3       (1u << 21) /**< \brief Ebi signal: A3 */
+#define PIO_PC22A_A4       (1u << 22) /**< \brief Ebi signal: A4 */
+#define PIO_PC23A_A5       (1u << 23) /**< \brief Ebi signal: A5 */
+#define PIO_PC24A_A6       (1u << 24) /**< \brief Ebi signal: A6 */
+#define PIO_PC25A_A7       (1u << 25) /**< \brief Ebi signal: A7 */
+#define PIO_PC26A_A8       (1u << 26) /**< \brief Ebi signal: A8 */
+#define PIO_PC27A_A9       (1u << 27) /**< \brief Ebi signal: A9 */
+#define PIO_PC0A_D0        (1u << 0)  /**< \brief Ebi signal: D0 */
+#define PIO_PC1A_D1        (1u << 1)  /**< \brief Ebi signal: D1 */
+#define PIO_PC2A_D2        (1u << 2)  /**< \brief Ebi signal: D2 */
+#define PIO_PC3A_D3        (1u << 3)  /**< \brief Ebi signal: D3 */
+#define PIO_PC4A_D4        (1u << 4)  /**< \brief Ebi signal: D4 */
+#define PIO_PC5A_D5        (1u << 5)  /**< \brief Ebi signal: D5 */
+#define PIO_PC6A_D6        (1u << 6)  /**< \brief Ebi signal: D6 */
+#define PIO_PC7A_D7        (1u << 7)  /**< \brief Ebi signal: D7 */
+#define PIO_PC9A_NANDOE    (1u << 9)  /**< \brief Ebi signal: NANDOE */
+#define PIO_PC10A_NANDWE   (1u << 10) /**< \brief Ebi signal: NANDWE */
+#define PIO_PC14A_NCS0     (1u << 14) /**< \brief Ebi signal: NCS0 */
+#define PIO_PC15A_NCS1     (1u << 15) /**< \brief Ebi signal: NCS1 */
+#define PIO_PA22C_NCS2     (1u << 22) /**< \brief Ebi signal: NCS2 */
+#define PIO_PC12A_NCS3     (1u << 12) /**< \brief Ebi signal: NCS3 */
+#define PIO_PC11A_NRD      (1u << 11) /**< \brief Ebi signal: NRD */
+#define PIO_PC13A_NWAIT    (1u << 13) /**< \brief Ebi signal: NWAIT */
+#define PIO_PC8A_NWE       (1u << 8)  /**< \brief Ebi signal: NWE */
+/* ========== Pio definition for HSMCI peripheral ========== */
+#define PIO_PA28C_MCCDA    (1u << 28) /**< \brief Hsmci signal: MCCDA */
+#define PIO_PA29C_MCCK     (1u << 29) /**< \brief Hsmci signal: MCCK */
+#define PIO_PA30C_MCDA0    (1u << 30) /**< \brief Hsmci signal: MCDA0 */
+#define PIO_PA31C_MCDA1    (1u << 31) /**< \brief Hsmci signal: MCDA1 */
+#define PIO_PA26C_MCDA2    (1u << 26) /**< \brief Hsmci signal: MCDA2 */
+#define PIO_PA27C_MCDA3    (1u << 27) /**< \brief Hsmci signal: MCDA3 */
+/* ========== Pio definition for PIOA peripheral ========== */
+#define PIO_PA24D_PIODC0   (1u << 24) /**< \brief Pioa signal: PIODC0 */
+#define PIO_PA25D_PIODC1   (1u << 25) /**< \brief Pioa signal: PIODC1 */
+#define PIO_PA26D_PIODC2   (1u << 26) /**< \brief Pioa signal: PIODC2 */
+#define PIO_PA27D_PIODC3   (1u << 27) /**< \brief Pioa signal: PIODC3 */
+#define PIO_PA28D_PIODC4   (1u << 28) /**< \brief Pioa signal: PIODC4 */
+#define PIO_PA29D_PIODC5   (1u << 29) /**< \brief Pioa signal: PIODC5 */
+#define PIO_PA30D_PIODC6   (1u << 30) /**< \brief Pioa signal: PIODC6 */
+#define PIO_PA31D_PIODC7   (1u << 31) /**< \brief Pioa signal: PIODC7 */
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */
+/* ========== Pio definition for PMC peripheral ========== */
+#define PIO_PA6B_PCK0      (1u << 6)  /**< \brief Pmc signal: PCK0 */
+#define PIO_PB13B_PCK0     (1u << 13) /**< \brief Pmc signal: PCK0 */
+#define PIO_PA17B_PCK1     (1u << 17) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA21B_PCK1     (1u << 21) /**< \brief Pmc signal: PCK1 */
+#define PIO_PA18B_PCK2     (1u << 18) /**< \brief Pmc signal: PCK2 */
+#define PIO_PA31B_PCK2     (1u << 31) /**< \brief Pmc signal: PCK2 */
+#define PIO_PB3B_PCK2      (1u << 3)  /**< \brief Pmc signal: PCK2 */
+/* ========== Pio definition for PWM peripheral ========== */
+#define PIO_PA9C_PWMFI0    (1u << 9)  /**< \brief Pwm signal: PWMFI0 */
+#define PIO_PA0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA11B_PWMH0    (1u << 11) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA23B_PWMH0    (1u << 23) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PB0A_PWMH0     (1u << 0)  /**< \brief Pwm signal: PWMH0 */
+#define PIO_PC18B_PWMH0    (1u << 18) /**< \brief Pwm signal: PWMH0 */
+#define PIO_PA1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA12B_PWMH1    (1u << 12) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA24B_PWMH1    (1u << 24) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PB1A_PWMH1     (1u << 1)  /**< \brief Pwm signal: PWMH1 */
+#define PIO_PC19B_PWMH1    (1u << 19) /**< \brief Pwm signal: PWMH1 */
+#define PIO_PA2A_PWMH2     (1u << 2)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA13B_PWMH2    (1u << 13) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA25B_PWMH2    (1u << 25) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PB4B_PWMH2     (1u << 4)  /**< \brief Pwm signal: PWMH2 */
+#define PIO_PC20B_PWMH2    (1u << 20) /**< \brief Pwm signal: PWMH2 */
+#define PIO_PA7B_PWMH3     (1u << 7)  /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA17C_PWMH3    (1u << 17) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PB14B_PWMH3    (1u << 14) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PC21B_PWMH3    (1u << 21) /**< \brief Pwm signal: PWMH3 */
+#define PIO_PA19B_PWML0    (1u << 19) /**< \brief Pwm signal: PWML0 */
+#define PIO_PB5B_PWML0     (1u << 5)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC0B_PWML0     (1u << 0)  /**< \brief Pwm signal: PWML0 */
+#define PIO_PC13B_PWML0    (1u << 13) /**< \brief Pwm signal: PWML0 */
+#define PIO_PA20B_PWML1    (1u << 20) /**< \brief Pwm signal: PWML1 */
+#define PIO_PB12A_PWML1    (1u << 12) /**< \brief Pwm signal: PWML1 */
+#define PIO_PC1B_PWML1     (1u << 1)  /**< \brief Pwm signal: PWML1 */
+#define PIO_PC15B_PWML1    (1u << 15) /**< \brief Pwm signal: PWML1 */
+#define PIO_PA16C_PWML2    (1u << 16) /**< \brief Pwm signal: PWML2 */
+#define PIO_PA30A_PWML2    (1u << 30) /**< \brief Pwm signal: PWML2 */
+#define PIO_PB13A_PWML2    (1u << 13) /**< \brief Pwm signal: PWML2 */
+#define PIO_PC2B_PWML2     (1u << 2)  /**< \brief Pwm signal: PWML2 */
+#define PIO_PA15C_PWML3    (1u << 15) /**< \brief Pwm signal: PWML3 */
+#define PIO_PC3B_PWML3     (1u << 3)  /**< \brief Pwm signal: PWML3 */
+#define PIO_PC22B_PWML3    (1u << 22) /**< \brief Pwm signal: PWML3 */
+/* ========== Pio definition for SPI peripheral ========== */
+#define PIO_PA12A_MISO     (1u << 12) /**< \brief Spi signal: MISO */
+#define PIO_PA13A_MOSI     (1u << 13) /**< \brief Spi signal: MOSI */
+#define PIO_PA11A_NPCS0    (1u << 11) /**< \brief Spi signal: NPCS0 */
+#define PIO_PA9B_NPCS1     (1u << 9)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA31A_NPCS1    (1u << 31) /**< \brief Spi signal: NPCS1 */
+#define PIO_PB14A_NPCS1    (1u << 14) /**< \brief Spi signal: NPCS1 */
+#define PIO_PC4B_NPCS1     (1u << 4)  /**< \brief Spi signal: NPCS1 */
+#define PIO_PA10B_NPCS2    (1u << 10) /**< \brief Spi signal: NPCS2 */
+#define PIO_PA30B_NPCS2    (1u << 30) /**< \brief Spi signal: NPCS2 */
+#define PIO_PB2B_NPCS2     (1u << 2)  /**< \brief Spi signal: NPCS2 */
+#define PIO_PA3B_NPCS3     (1u << 3)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA5B_NPCS3     (1u << 5)  /**< \brief Spi signal: NPCS3 */
+#define PIO_PA22B_NPCS3    (1u << 22) /**< \brief Spi signal: NPCS3 */
+#define PIO_PA14A_SPCK     (1u << 14) /**< \brief Spi signal: SPCK */
+/* ========== Pio definition for SSC peripheral ========== */
+#define PIO_PA18A_RD       (1u << 18) /**< \brief Ssc signal: RD */
+#define PIO_PA20A_RF       (1u << 20) /**< \brief Ssc signal: RF */
+#define PIO_PA19A_RK       (1u << 19) /**< \brief Ssc signal: RK */
+#define PIO_PA17A_TD       (1u << 17) /**< \brief Ssc signal: TD */
+#define PIO_PA15A_TF       (1u << 15) /**< \brief Ssc signal: TF */
+#define PIO_PA16A_TK       (1u << 16) /**< \brief Ssc signal: TK */
+/* ========== Pio definition for TC0 peripheral ========== */
+#define PIO_PA4B_TCLK0     (1u << 4)  /**< \brief Tc0 signal: TCLK0 */
+#define PIO_PA28B_TCLK1    (1u << 28) /**< \brief Tc0 signal: TCLK1 */
+#define PIO_PA29B_TCLK2    (1u << 29) /**< \brief Tc0 signal: TCLK2 */
+#define PIO_PA0B_TIOA0     (1u << 0)  /**< \brief Tc0 signal: TIOA0 */
+#define PIO_PA15B_TIOA1    (1u << 15) /**< \brief Tc0 signal: TIOA1 */
+#define PIO_PA26B_TIOA2    (1u << 26) /**< \brief Tc0 signal: TIOA2 */
+#define PIO_PA1B_TIOB0     (1u << 1)  /**< \brief Tc0 signal: TIOB0 */
+#define PIO_PA16B_TIOB1    (1u << 16) /**< \brief Tc0 signal: TIOB1 */
+#define PIO_PA27B_TIOB2    (1u << 27) /**< \brief Tc0 signal: TIOB2 */
+/* ========== Pio definition for TC1 peripheral ========== */
+#define PIO_PC25B_TCLK3    (1u << 25) /**< \brief Tc1 signal: TCLK3 */
+#define PIO_PC28B_TCLK4    (1u << 28) /**< \brief Tc1 signal: TCLK4 */
+#define PIO_PC31B_TCLK5    (1u << 31) /**< \brief Tc1 signal: TCLK5 */
+#define PIO_PC23B_TIOA3    (1u << 23) /**< \brief Tc1 signal: TIOA3 */
+#define PIO_PC26B_TIOA4    (1u << 26) /**< \brief Tc1 signal: TIOA4 */
+#define PIO_PC29B_TIOA5    (1u << 29) /**< \brief Tc1 signal: TIOA5 */
+#define PIO_PC24B_TIOB3    (1u << 24) /**< \brief Tc1 signal: TIOB3 */
+#define PIO_PC27B_TIOB4    (1u << 27) /**< \brief Tc1 signal: TIOB4 */
+#define PIO_PC30B_TIOB5    (1u << 30) /**< \brief Tc1 signal: TIOB5 */
+/* ========== Pio definition for TWI0 peripheral ========== */
+#define PIO_PA4A_TWCK0     (1u << 4)  /**< \brief Twi0 signal: TWCK0 */
+#define PIO_PA3A_TWD0      (1u << 3)  /**< \brief Twi0 signal: TWD0 */
+/* ========== Pio definition for TWI1 peripheral ========== */
+#define PIO_PB5A_TWCK1     (1u << 5)  /**< \brief Twi1 signal: TWCK1 */
+#define PIO_PB4A_TWD1      (1u << 4)  /**< \brief Twi1 signal: TWD1 */
+/* ========== Pio definition for UART0 peripheral ========== */
+#define PIO_PA9A_URXD0     (1u << 9)  /**< \brief Uart0 signal: URXD0 */
+#define PIO_PA10A_UTXD0    (1u << 10) /**< \brief Uart0 signal: UTXD0 */
+/* ========== Pio definition for UART1 peripheral ========== */
+#define PIO_PB2A_URXD1     (1u << 2)  /**< \brief Uart1 signal: URXD1 */
+#define PIO_PB3A_UTXD1     (1u << 3)  /**< \brief Uart1 signal: UTXD1 */
+/* ========== Pio definition for USART0 peripheral ========== */
+#define PIO_PA8A_CTS0      (1u << 8)  /**< \brief Usart0 signal: CTS0 */
+#define PIO_PA7A_RTS0      (1u << 7)  /**< \brief Usart0 signal: RTS0 */
+#define PIO_PA5A_RXD0      (1u << 5)  /**< \brief Usart0 signal: RXD0 */
+#define PIO_PA2B_SCK0      (1u << 2)  /**< \brief Usart0 signal: SCK0 */
+#define PIO_PA6A_TXD0      (1u << 6)  /**< \brief Usart0 signal: TXD0 */
+/* ========== Pio definition for USART1 peripheral ========== */
+#define PIO_PA25A_CTS1     (1u << 25) /**< \brief Usart1 signal: CTS1 */
+#define PIO_PA26A_DCD1     (1u << 26) /**< \brief Usart1 signal: DCD1 */
+#define PIO_PA28A_DSR1     (1u << 28) /**< \brief Usart1 signal: DSR1 */
+#define PIO_PA27A_DTR1     (1u << 27) /**< \brief Usart1 signal: DTR1 */
+#define PIO_PA29A_RI1      (1u << 29) /**< \brief Usart1 signal: RI1 */
+#define PIO_PA24A_RTS1     (1u << 24) /**< \brief Usart1 signal: RTS1 */
+#define PIO_PA21A_RXD1     (1u << 21) /**< \brief Usart1 signal: RXD1 */
+#define PIO_PA23A_SCK1     (1u << 23) /**< \brief Usart1 signal: SCK1 */
+#define PIO_PA22A_TXD1     (1u << 22) /**< \brief Usart1 signal: TXD1 */
+/* ========== Pio indexes ========== */
+#define PIO_PA0_IDX        0
+#define PIO_PA1_IDX        1
+#define PIO_PA2_IDX        2
+#define PIO_PA3_IDX        3
+#define PIO_PA4_IDX        4
+#define PIO_PA5_IDX        5
+#define PIO_PA6_IDX        6
+#define PIO_PA7_IDX        7
+#define PIO_PA8_IDX        8
+#define PIO_PA9_IDX        9
+#define PIO_PA10_IDX       10
+#define PIO_PA11_IDX       11
+#define PIO_PA12_IDX       12
+#define PIO_PA13_IDX       13
+#define PIO_PA14_IDX       14
+#define PIO_PA15_IDX       15
+#define PIO_PA16_IDX       16
+#define PIO_PA17_IDX       17
+#define PIO_PA18_IDX       18
+#define PIO_PA19_IDX       19
+#define PIO_PA20_IDX       20
+#define PIO_PA21_IDX       21
+#define PIO_PA22_IDX       22
+#define PIO_PA23_IDX       23
+#define PIO_PA24_IDX       24
+#define PIO_PA25_IDX       25
+#define PIO_PA26_IDX       26
+#define PIO_PA27_IDX       27
+#define PIO_PA28_IDX       28
+#define PIO_PA29_IDX       29
+#define PIO_PA30_IDX       30
+#define PIO_PA31_IDX       31
+#define PIO_PB0_IDX        32
+#define PIO_PB1_IDX        33
+#define PIO_PB2_IDX        34
+#define PIO_PB3_IDX        35
+#define PIO_PB4_IDX        36
+#define PIO_PB5_IDX        37
+#define PIO_PB6_IDX        38
+#define PIO_PB7_IDX        39
+#define PIO_PB8_IDX        40
+#define PIO_PB9_IDX        41
+#define PIO_PB10_IDX       42
+#define PIO_PB11_IDX       43
+#define PIO_PB12_IDX       44
+#define PIO_PB13_IDX       45
+#define PIO_PB14_IDX       46
+#define PIO_PC0_IDX        64
+#define PIO_PC1_IDX        65
+#define PIO_PC2_IDX        66
+#define PIO_PC3_IDX        67
+#define PIO_PC4_IDX        68
+#define PIO_PC5_IDX        69
+#define PIO_PC6_IDX        70
+#define PIO_PC7_IDX        71
+#define PIO_PC8_IDX        72
+#define PIO_PC9_IDX        73
+#define PIO_PC10_IDX       74
+#define PIO_PC11_IDX       75
+#define PIO_PC12_IDX       76
+#define PIO_PC13_IDX       77
+#define PIO_PC14_IDX       78
+#define PIO_PC15_IDX       79
+#define PIO_PC16_IDX       80
+#define PIO_PC17_IDX       81
+#define PIO_PC18_IDX       82
+#define PIO_PC19_IDX       83
+#define PIO_PC20_IDX       84
+#define PIO_PC21_IDX       85
+#define PIO_PC22_IDX       86
+#define PIO_PC23_IDX       87
+#define PIO_PC24_IDX       88
+#define PIO_PC25_IDX       89
+#define PIO_PC26_IDX       90
+#define PIO_PC27_IDX       91
+#define PIO_PC28_IDX       92
+#define PIO_PC29_IDX       93
+#define PIO_PC30_IDX       94
+#define PIO_PC31_IDX       95
+
+#endif /* _SAM4S8C_PIO_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s.h
new file mode 100644
index 0000000..8c34830
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s.h
@@ -0,0 +1,45 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S_
+#define _SAM4S_
+
+#if defined __SAM4S8B__
+  #include "sam4s8b.h"
+#elif defined __SAM4S8C__
+  #include "sam4s8c.h"
+#elif defined __SAM4S16B__
+  #include "sam4s16b.h"
+#elif defined __SAM4S16C__
+  #include "sam4s16c.h"
+#else
+  #error Library does not support the specified device.
+#endif
+
+#endif /* _SAM4S_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s16b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s16b.h
new file mode 100644
index 0000000..08eef56
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s16b.h
@@ -0,0 +1,507 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S16B_
+#define _SAM4S16B_
+
+/** \addtogroup SAM4S16B_definitions SAM4S16B definitions
+  This file defines all structures and symbols for SAM4S16B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM4S16B */
+/* ************************************************************************** */
+/** \addtogroup SAM4S16B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M4 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M4 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M4 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M4 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M4 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M4 System Tick Interrupt       */
+/******  SAM4S16B specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM4S16B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM4S16B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM4S16B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM4S16B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM4S16B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM4S16B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM4S16B Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM4S16B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM4S16B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM4S16B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM4S16B Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM4S16B Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM4S16B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM4S16B USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM4S16B Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM4S16B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM4S16B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM4S16B Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM4S16B Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM4S16B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM4S16B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM4S16B Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM4S16B Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM4S16B Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM4S16B Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM4S16B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM4S16B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM4S16B Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM4S16B CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM4S16B Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM4S16B USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
+  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
+  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M4 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV              0x0000 /**< SAM4S16B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM4S16B does provide a MPU */
+#define __FPU_PRESENT          0      /**< SAM4S16B does not provide a FPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM4S16B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam4s.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM4S16B */
+/* ************************************************************************** */
+/** \addtogroup SAM4S16B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM4S16B */
+/* ************************************************************************** */
+/** \addtogroup SAM4S16B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM4S16B */
+/* ************************************************************************** */
+/** \addtogroup SAM4S16B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM4S16B */
+/* ************************************************************************** */
+/** \addtogroup SAM4S16B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM4S16B */
+/* ************************************************************************** */
+/** \addtogroup SAM4S16B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam4s16b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM4S16B */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x100000u)
+#define IFLASH0_PAGE_SIZE        (512u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (2048u)
+#define IFLASH0_NB_OF_LOCK_BITS  (128u)
+#define IRAM_SIZE                (0x20000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM4S16B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (120000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+#define CHIP_FREQ_FWS_4                 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM4S16B_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s16c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s16c.h
new file mode 100644
index 0000000..1c8a4ff
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s16c.h
@@ -0,0 +1,514 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S16C_
+#define _SAM4S16C_
+
+/** \addtogroup SAM4S16C_definitions SAM4S16C definitions
+  This file defines all structures and symbols for SAM4S16C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM4S16C */
+/* ************************************************************************** */
+/** \addtogroup SAM4S16C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M4 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M4 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M4 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M4 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M4 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M4 System Tick Interrupt       */
+/******  SAM4S16C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM4S16C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM4S16C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM4S16C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM4S16C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM4S16C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM4S16C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM4S16C Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM4S16C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM4S16C UART 1 (UART1) */
+  SMC_IRQn             = 10, /**< 10 SAM4S16C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM4S16C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM4S16C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM4S16C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM4S16C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM4S16C USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM4S16C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM4S16C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM4S16C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM4S16C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM4S16C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM4S16C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM4S16C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM4S16C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM4S16C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM4S16C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM4S16C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM4S16C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM4S16C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM4S16C Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM4S16C CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM4S16C Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM4S16C USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pfnSMC_Handler;    /* 10 Static Memory Controller */
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
+  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
+  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M4 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV              0x0000 /**< SAM4S16C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM4S16C does provide a MPU */
+#define __FPU_PRESENT          0      /**< SAM4S16C does not provide a FPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM4S16C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam4s.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM4S16C */
+/* ************************************************************************** */
+/** \addtogroup SAM4S16C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM4S16C */
+/* ************************************************************************** */
+/** \addtogroup SAM4S16C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM4S16C */
+/* ************************************************************************** */
+/** \addtogroup SAM4S16C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_SMC    (10) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM4S16C */
+/* ************************************************************************** */
+/** \addtogroup SAM4S16C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM4S16C */
+/* ************************************************************************** */
+/** \addtogroup SAM4S16C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam4s16c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM4S16C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x100000u)
+#define IFLASH0_PAGE_SIZE        (512u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (2048u)
+#define IFLASH0_NB_OF_LOCK_BITS  (128u)
+#define IRAM_SIZE                (0x20000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM4S16C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (120000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+#define CHIP_FREQ_FWS_4                 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM4S16C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s8b.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s8b.h
new file mode 100644
index 0000000..e417158
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s8b.h
@@ -0,0 +1,507 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S8B_
+#define _SAM4S8B_
+
+/** \addtogroup SAM4S8B_definitions SAM4S8B definitions
+  This file defines all structures and symbols for SAM4S8B:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM4S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM4S8B_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M4 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M4 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M4 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M4 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M4 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M4 System Tick Interrupt       */
+/******  SAM4S8B specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM4S8B Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM4S8B Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM4S8B Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM4S8B Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM4S8B Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM4S8B Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM4S8B Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM4S8B UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM4S8B UART 1 (UART1) */
+  PIOA_IRQn            = 11, /**< 11 SAM4S8B Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM4S8B Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM4S8B Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM4S8B USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM4S8B USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM4S8B Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM4S8B Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM4S8B Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM4S8B Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM4S8B Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM4S8B Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM4S8B Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM4S8B Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM4S8B Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM4S8B Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM4S8B Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM4S8B Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM4S8B Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM4S8B Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM4S8B CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM4S8B Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM4S8B USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pvReserved10;
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
+  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
+  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M4 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV              0x0000 /**< SAM4S8B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM4S8B does provide a MPU */
+#define __FPU_PRESENT          0      /**< SAM4S8B does not provide a FPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM4S8B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam4s.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM4S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM4S8B_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM4S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM4S8B_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM4S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM4S8B_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM4S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM4S8B_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM4S8B */
+/* ************************************************************************** */
+/** \addtogroup SAM4S8B_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam4s8b.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM4S8B */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x80000u)
+#define IFLASH0_PAGE_SIZE        (512u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH0_NB_OF_LOCK_BITS  (64u)
+#define IRAM_SIZE                (0x20000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM4S8B */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (120000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+#define CHIP_FREQ_FWS_4                 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM4S8B_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s8c.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s8c.h
new file mode 100644
index 0000000..c2b5b20
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/sam4s8c.h
@@ -0,0 +1,514 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _SAM4S8C_
+#define _SAM4S8C_
+
+/** \addtogroup SAM4S8C_definitions SAM4S8C definitions
+  This file defines all structures and symbols for SAM4S8C:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include 
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#else
+typedef volatile       uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+#endif
+typedef volatile       uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile       uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+#endif
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAM4S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM4S8C_cmsis CMSIS Definitions */
+/*@{*/
+
+/**< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers ******************************/
+  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
+  MemoryManagement_IRQn = -12, /**<  4 Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn         = -11, /**<  5 Cortex-M4 Bus Fault Interrupt         */
+  UsageFault_IRQn       = -10, /**<  6 Cortex-M4 Usage Fault Interrupt       */
+  SVCall_IRQn           = -5,  /**< 11 Cortex-M4 SV Call Interrupt           */
+  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M4 Debug Monitor Interrupt     */
+  PendSV_IRQn           = -2,  /**< 14 Cortex-M4 Pend SV Interrupt           */
+  SysTick_IRQn          = -1,  /**< 15 Cortex-M4 System Tick Interrupt       */
+/******  SAM4S8C specific Interrupt Numbers *********************************/
+
+  SUPC_IRQn            =  0, /**<  0 SAM4S8C Supply Controller (SUPC) */
+  RSTC_IRQn            =  1, /**<  1 SAM4S8C Reset Controller (RSTC) */
+  RTC_IRQn             =  2, /**<  2 SAM4S8C Real Time Clock (RTC) */
+  RTT_IRQn             =  3, /**<  3 SAM4S8C Real Time Timer (RTT) */
+  WDT_IRQn             =  4, /**<  4 SAM4S8C Watchdog Timer (WDT) */
+  PMC_IRQn             =  5, /**<  5 SAM4S8C Power Management Controller (PMC) */
+  EFC_IRQn             =  6, /**<  6 SAM4S8C Enhanced Embedded Flash Controller (EFC) */
+  UART0_IRQn           =  8, /**<  8 SAM4S8C UART 0 (UART0) */
+  UART1_IRQn           =  9, /**<  9 SAM4S8C UART 1 (UART1) */
+  SMC_IRQn             = 10, /**< 10 SAM4S8C Static Memory Controller (SMC) */
+  PIOA_IRQn            = 11, /**< 11 SAM4S8C Parallel I/O Controller A (PIOA) */
+  PIOB_IRQn            = 12, /**< 12 SAM4S8C Parallel I/O Controller B (PIOB) */
+  PIOC_IRQn            = 13, /**< 13 SAM4S8C Parallel I/O Controller C (PIOC) */
+  USART0_IRQn          = 14, /**< 14 SAM4S8C USART 0 (USART0) */
+  USART1_IRQn          = 15, /**< 15 SAM4S8C USART 1 (USART1) */
+  HSMCI_IRQn           = 18, /**< 18 SAM4S8C Multimedia Card Interface (HSMCI) */
+  TWI0_IRQn            = 19, /**< 19 SAM4S8C Two Wire Interface 0 (TWI0) */
+  TWI1_IRQn            = 20, /**< 20 SAM4S8C Two Wire Interface 1 (TWI1) */
+  SPI_IRQn             = 21, /**< 21 SAM4S8C Serial Peripheral Interface (SPI) */
+  SSC_IRQn             = 22, /**< 22 SAM4S8C Synchronous Serial Controller (SSC) */
+  TC0_IRQn             = 23, /**< 23 SAM4S8C Timer/Counter 0 (TC0) */
+  TC1_IRQn             = 24, /**< 24 SAM4S8C Timer/Counter 1 (TC1) */
+  TC2_IRQn             = 25, /**< 25 SAM4S8C Timer/Counter 2 (TC2) */
+  TC3_IRQn             = 26, /**< 26 SAM4S8C Timer/Counter 3 (TC3) */
+  TC4_IRQn             = 27, /**< 27 SAM4S8C Timer/Counter 4 (TC4) */
+  TC5_IRQn             = 28, /**< 28 SAM4S8C Timer/Counter 5 (TC5) */
+  ADC_IRQn             = 29, /**< 29 SAM4S8C Analog To Digital Converter (ADC) */
+  DACC_IRQn            = 30, /**< 30 SAM4S8C Digital To Analog Converter (DACC) */
+  PWM_IRQn             = 31, /**< 31 SAM4S8C Pulse Width Modulation (PWM) */
+  CRCCU_IRQn           = 32, /**< 32 SAM4S8C CRC Calculation Unit (CRCCU) */
+  ACC_IRQn             = 33, /**< 33 SAM4S8C Analog Comparator (ACC) */
+  UDP_IRQn             = 34, /**< 34 SAM4S8C USB Device Port (UDP) */
+
+  PERIPH_COUNT_IRQn    = 35  /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;
+  void* pfnNMI_Handler;
+  void* pfnHardFault_Handler;
+  void* pfnMemManage_Handler;
+  void* pfnBusFault_Handler;
+  void* pfnUsageFault_Handler;
+  void* pfnReserved1_Handler;
+  void* pfnReserved2_Handler;
+  void* pfnReserved3_Handler;
+  void* pfnReserved4_Handler;
+  void* pfnSVC_Handler;
+  void* pfnDebugMon_Handler;
+  void* pfnReserved5_Handler;
+  void* pfnPendSV_Handler;
+  void* pfnSysTick_Handler;
+
+  /* Peripheral handlers */
+  void* pfnSUPC_Handler;   /*  0 Supply Controller */
+  void* pfnRSTC_Handler;   /*  1 Reset Controller */
+  void* pfnRTC_Handler;    /*  2 Real Time Clock */
+  void* pfnRTT_Handler;    /*  3 Real Time Timer */
+  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
+  void* pfnPMC_Handler;    /*  5 Power Management Controller */
+  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
+  void* pvReserved7;
+  void* pfnUART0_Handler;  /*  8 UART 0 */
+  void* pfnUART1_Handler;  /*  9 UART 1 */
+  void* pfnSMC_Handler;    /* 10 Static Memory Controller */
+  void* pfnPIOA_Handler;   /* 11 Parallel I/O Controller A */
+  void* pfnPIOB_Handler;   /* 12 Parallel I/O Controller B */
+  void* pfnPIOC_Handler;   /* 13 Parallel I/O Controller C */
+  void* pfnUSART0_Handler; /* 14 USART 0 */
+  void* pfnUSART1_Handler; /* 15 USART 1 */
+  void* pvReserved16;
+  void* pvReserved17;
+  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
+  void* pfnTWI0_Handler;   /* 19 Two Wire Interface 0 */
+  void* pfnTWI1_Handler;   /* 20 Two Wire Interface 1 */
+  void* pfnSPI_Handler;    /* 21 Serial Peripheral Interface */
+  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
+  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
+  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
+  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
+  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
+  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
+  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
+  void* pfnADC_Handler;    /* 29 Analog To Digital Converter */
+  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
+  void* pfnPWM_Handler;    /* 31 Pulse Width Modulation */
+  void* pfnCRCCU_Handler;  /* 32 CRC Calculation Unit */
+  void* pfnACC_Handler;    /* 33 Analog Comparator */
+  void* pfnUDP_Handler;    /* 34 USB Device Port */
+} DeviceVectors;
+
+/* Cortex-M4 core handlers */
+void Reset_Handler      ( void );
+void NMI_Handler        ( void );
+void HardFault_Handler  ( void );
+void MemManage_Handler  ( void );
+void BusFault_Handler   ( void );
+void UsageFault_Handler ( void );
+void SVC_Handler        ( void );
+void DebugMon_Handler   ( void );
+void PendSV_Handler     ( void );
+void SysTick_Handler    ( void );
+
+/* Peripherals handlers */
+void ACC_Handler        ( void );
+void ADC_Handler        ( void );
+void CRCCU_Handler      ( void );
+void DACC_Handler       ( void );
+void EFC_Handler        ( void );
+void HSMCI_Handler      ( void );
+void PIOA_Handler       ( void );
+void PIOB_Handler       ( void );
+void PIOC_Handler       ( void );
+void PMC_Handler        ( void );
+void PWM_Handler        ( void );
+void RSTC_Handler       ( void );
+void RTC_Handler        ( void );
+void RTT_Handler        ( void );
+void SMC_Handler        ( void );
+void SPI_Handler        ( void );
+void SSC_Handler        ( void );
+void SUPC_Handler       ( void );
+void TC0_Handler        ( void );
+void TC1_Handler        ( void );
+void TC2_Handler        ( void );
+void TC3_Handler        ( void );
+void TC4_Handler        ( void );
+void TC5_Handler        ( void );
+void TWI0_Handler       ( void );
+void TWI1_Handler       ( void );
+void UART0_Handler      ( void );
+void UART1_Handler      ( void );
+void UDP_Handler        ( void );
+void USART0_Handler     ( void );
+void USART1_Handler     ( void );
+void WDT_Handler        ( void );
+
+/**
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+
+#define __CM4_REV              0x0000 /**< SAM4S8C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM4S8C does provide a MPU */
+#define __FPU_PRESENT          0      /**< SAM4S8C does not provide a FPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM4S8C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
+
+/*
+ * \brief CMSIS includes
+ */
+
+#include 
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_sam4s.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAM4S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM4S8C_api Peripheral Software API */
+/*@{*/
+
+#include "component/component_acc.h"
+#include "component/component_adc.h"
+#include "component/component_chipid.h"
+#include "component/component_crccu.h"
+#include "component/component_dacc.h"
+#include "component/component_efc.h"
+#include "component/component_gpbr.h"
+#include "component/component_hsmci.h"
+#include "component/component_matrix.h"
+#include "component/component_pdc.h"
+#include "component/component_pio.h"
+#include "component/component_pmc.h"
+#include "component/component_pwm.h"
+#include "component/component_rstc.h"
+#include "component/component_rtc.h"
+#include "component/component_rtt.h"
+#include "component/component_smc.h"
+#include "component/component_spi.h"
+#include "component/component_ssc.h"
+#include "component/component_supc.h"
+#include "component/component_tc.h"
+#include "component/component_twi.h"
+#include "component/component_uart.h"
+#include "component/component_udp.h"
+#include "component/component_usart.h"
+#include "component/component_wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   REGISTER ACCESS DEFINITIONS FOR SAM4S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM4S8C_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/instance_hsmci.h"
+#include "instance/instance_ssc.h"
+#include "instance/instance_spi.h"
+#include "instance/instance_tc0.h"
+#include "instance/instance_tc1.h"
+#include "instance/instance_twi0.h"
+#include "instance/instance_twi1.h"
+#include "instance/instance_pwm.h"
+#include "instance/instance_usart0.h"
+#include "instance/instance_usart1.h"
+#include "instance/instance_udp.h"
+#include "instance/instance_adc.h"
+#include "instance/instance_dacc.h"
+#include "instance/instance_acc.h"
+#include "instance/instance_crccu.h"
+#include "instance/instance_smc.h"
+#include "instance/instance_matrix.h"
+#include "instance/instance_pmc.h"
+#include "instance/instance_uart0.h"
+#include "instance/instance_chipid.h"
+#include "instance/instance_uart1.h"
+#include "instance/instance_efc.h"
+#include "instance/instance_pioa.h"
+#include "instance/instance_piob.h"
+#include "instance/instance_pioc.h"
+#include "instance/instance_rstc.h"
+#include "instance/instance_supc.h"
+#include "instance/instance_rtt.h"
+#include "instance/instance_wdt.h"
+#include "instance/instance_rtc.h"
+#include "instance/instance_gpbr.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   PERIPHERAL ID DEFINITIONS FOR SAM4S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM4S8C_id Peripheral Ids Definitions */
+/*@{*/
+
+#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
+#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
+#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
+#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
+#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
+#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
+#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
+#define ID_UART0  ( 8) /**< \brief UART 0 (UART0) */
+#define ID_UART1  ( 9) /**< \brief UART 1 (UART1) */
+#define ID_SMC    (10) /**< \brief Static Memory Controller (SMC) */
+#define ID_PIOA   (11) /**< \brief Parallel I/O Controller A (PIOA) */
+#define ID_PIOB   (12) /**< \brief Parallel I/O Controller B (PIOB) */
+#define ID_PIOC   (13) /**< \brief Parallel I/O Controller C (PIOC) */
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
+#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
+#define ID_TWI0   (19) /**< \brief Two Wire Interface 0 (TWI0) */
+#define ID_TWI1   (20) /**< \brief Two Wire Interface 1 (TWI1) */
+#define ID_SPI    (21) /**< \brief Serial Peripheral Interface (SPI) */
+#define ID_SSC    (22) /**< \brief Synchronous Serial Controller (SSC) */
+#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
+#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
+#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
+#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
+#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
+#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
+#define ID_ADC    (29) /**< \brief Analog To Digital Converter (ADC) */
+#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
+#define ID_PWM    (31) /**< \brief Pulse Width Modulation (PWM) */
+#define ID_CRCCU  (32) /**< \brief CRC Calculation Unit (CRCCU) */
+#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
+#define ID_UDP    (34) /**< \brief USB Device Port (UDP) */
+
+#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAM4S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM4S8C_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define HSMCI      (0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        (0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    (0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        (0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    (0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        (0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        (0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       (0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   (0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       (0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   (0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        (0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    (0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     (0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     (0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        (0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        (0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    (0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       (0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   (0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        (0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      (0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        (0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     (0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        (0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      (0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     (0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      (0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        (0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       (0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   (0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       (0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       (0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       (0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       (0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        (0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        (0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        (0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       (0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#else
+#define HSMCI      ((Hsmci  *)0x40000000U) /**< \brief (HSMCI     ) Base Address */
+#define PDC_HSMCI  ((Pdc    *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
+#define SSC        ((Ssc    *)0x40004000U) /**< \brief (SSC       ) Base Address */
+#define PDC_SSC    ((Pdc    *)0x40004100U) /**< \brief (PDC_SSC   ) Base Address */
+#define SPI        ((Spi    *)0x40008000U) /**< \brief (SPI       ) Base Address */
+#define PDC_SPI    ((Pdc    *)0x40008100U) /**< \brief (PDC_SPI   ) Base Address */
+#define TC0        ((Tc     *)0x40010000U) /**< \brief (TC0       ) Base Address */
+#define TC1        ((Tc     *)0x40014000U) /**< \brief (TC1       ) Base Address */
+#define TWI0       ((Twi    *)0x40018000U) /**< \brief (TWI0      ) Base Address */
+#define PDC_TWI0   ((Pdc    *)0x40018100U) /**< \brief (PDC_TWI0  ) Base Address */
+#define TWI1       ((Twi    *)0x4001C000U) /**< \brief (TWI1      ) Base Address */
+#define PDC_TWI1   ((Pdc    *)0x4001C100U) /**< \brief (PDC_TWI1  ) Base Address */
+#define PWM        ((Pwm    *)0x40020000U) /**< \brief (PWM       ) Base Address */
+#define PDC_PWM    ((Pdc    *)0x40020100U) /**< \brief (PDC_PWM   ) Base Address */
+#define USART0     ((Usart  *)0x40024000U) /**< \brief (USART0    ) Base Address */
+#define PDC_USART0 ((Pdc    *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
+#define USART1     ((Usart  *)0x40028000U) /**< \brief (USART1    ) Base Address */
+#define PDC_USART1 ((Pdc    *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
+#define UDP        ((Udp    *)0x40034000U) /**< \brief (UDP       ) Base Address */
+#define ADC        ((Adc    *)0x40038000U) /**< \brief (ADC       ) Base Address */
+#define PDC_ADC    ((Pdc    *)0x40038100U) /**< \brief (PDC_ADC   ) Base Address */
+#define DACC       ((Dacc   *)0x4003C000U) /**< \brief (DACC      ) Base Address */
+#define PDC_DACC   ((Pdc    *)0x4003C100U) /**< \brief (PDC_DACC  ) Base Address */
+#define ACC        ((Acc    *)0x40040000U) /**< \brief (ACC       ) Base Address */
+#define CRCCU      ((Crccu  *)0x40044000U) /**< \brief (CRCCU     ) Base Address */
+#define SMC        ((Smc    *)0x400E0000U) /**< \brief (SMC       ) Base Address */
+#define MATRIX     ((Matrix *)0x400E0200U) /**< \brief (MATRIX    ) Base Address */
+#define PMC        ((Pmc    *)0x400E0400U) /**< \brief (PMC       ) Base Address */
+#define UART0      ((Uart   *)0x400E0600U) /**< \brief (UART0     ) Base Address */
+#define PDC_UART0  ((Pdc    *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
+#define CHIPID     ((Chipid *)0x400E0740U) /**< \brief (CHIPID    ) Base Address */
+#define UART1      ((Uart   *)0x400E0800U) /**< \brief (UART1     ) Base Address */
+#define PDC_UART1  ((Pdc    *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
+#define EFC        ((Efc    *)0x400E0A00U) /**< \brief (EFC       ) Base Address */
+#define PIOA       ((Pio    *)0x400E0E00U) /**< \brief (PIOA      ) Base Address */
+#define PDC_PIOA   ((Pdc    *)0x400E0F68U) /**< \brief (PDC_PIOA  ) Base Address */
+#define PIOB       ((Pio    *)0x400E1000U) /**< \brief (PIOB      ) Base Address */
+#define PIOC       ((Pio    *)0x400E1200U) /**< \brief (PIOC      ) Base Address */
+#define RSTC       ((Rstc   *)0x400E1400U) /**< \brief (RSTC      ) Base Address */
+#define SUPC       ((Supc   *)0x400E1410U) /**< \brief (SUPC      ) Base Address */
+#define RTT        ((Rtt    *)0x400E1430U) /**< \brief (RTT       ) Base Address */
+#define WDT        ((Wdt    *)0x400E1450U) /**< \brief (WDT       ) Base Address */
+#define RTC        ((Rtc    *)0x400E1460U) /**< \brief (RTC       ) Base Address */
+#define GPBR       ((Gpbr   *)0x400E1490U) /**< \brief (GPBR      ) Base Address */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAM4S8C */
+/* ************************************************************************** */
+/** \addtogroup SAM4S8C_pio Peripheral Pio Definitions */
+/*@{*/
+
+#include "pio/pio_sam4s8c.h"
+/*@}*/
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAM4S8C */
+/* ************************************************************************** */
+
+#define IFLASH0_SIZE             (0x80000u)
+#define IFLASH0_PAGE_SIZE        (512u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH0_NB_OF_LOCK_BITS  (64u)
+#define IRAM_SIZE                (0x20000u)
+#define IFLASH_SIZE              (IFLASH0_SIZE)
+
+#define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
+#define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
+
+/* ************************************************************************** */
+/*   ELECTRICAL DEFINITIONS FOR SAM4S8C */
+/* ************************************************************************** */
+
+/* Device characteristics */
+#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
+#define CHIP_FREQ_SLCK_RC               (32000UL)
+#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
+#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
+#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
+#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
+#define CHIP_FREQ_CPU_MAX               (120000000UL)
+#define CHIP_FREQ_XTAL_32K              (32768UL)
+#define CHIP_FREQ_XTAL_12M              (12000000UL)
+
+/* Embedded Flash Write Wait State */
+#define CHIP_FLASH_WRITE_WAIT_STATE     (6U)
+
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
+#define CHIP_FREQ_FWS_0                 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
+#define CHIP_FREQ_FWS_1                 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
+#define CHIP_FREQ_FWS_2                 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
+#define CHIP_FREQ_FWS_3                 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
+#define CHIP_FREQ_FWS_4                 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _SAM4S8C_ */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/system_sam4s.h b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/system_sam4s.h
new file mode 100644
index 0000000..27e6b05
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/include/system_sam4s.h
@@ -0,0 +1,58 @@
+/*! \file *********************************************************************
+ *
+ * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
+ *           for SAM4 devices.
+ *
+ * $asf_license$
+ *
+ * \par Purpose
+ *
+ * This file provides basic support for Cortex-M processor based
+ * microcontrollers.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+#ifndef SYSTEM_SAM4S_H_INCLUDED
+#define SYSTEM_SAM4S_H_INCLUDED
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#include 
+
+extern uint32_t SystemCoreClock;	/* System Clock Frequency (Core Clock) */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void);
+
+/**
+ * Initialize flash.
+ */
+void system_init_flash(uint32_t dw_clk);
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+#endif /* SYSTEM_SAM4S_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16_flash.ld
new file mode 100644
index 0000000..de4d089
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16_flash.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal FLASH on the SAM4S16
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* flash, 1024K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16_sram.ld
new file mode 100644
index 0000000..e81654f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16_sram.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal SRAM on the SAM4S16
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* flash, 1024K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16b_flash.ld
new file mode 100644
index 0000000..d17bb71
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16b_sram.ld
new file mode 100644
index 0000000..038ad37
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16c_flash.ld
new file mode 100644
index 0000000..d17bb71
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16c_sram.ld
new file mode 100644
index 0000000..038ad37
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s16c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8_flash.ld
new file mode 100644
index 0000000..d50c9af
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8_flash.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal FLASH on the SAM4S8
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8_sram.ld
new file mode 100644
index 0000000..8863ae4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8_sram.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal SRAM on the SAM4S8
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8b_flash.ld
new file mode 100644
index 0000000..665a6ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8b_sram.ld
new file mode 100644
index 0000000..28497d6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8c_flash.ld
new file mode 100644
index 0000000..665a6ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8c_sram.ld
new file mode 100644
index 0000000..28497d6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/sam4s_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/startup_sam4s.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/startup_sam4s.c
new file mode 100644
index 0000000..39971cb
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/as_gcc/startup_sam4s.c
@@ -0,0 +1,235 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam4s.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_SMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_USART1_INSTANCE_
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_USART1_INSTANCE_ */
+#ifdef _SAM4S_HSMCI_INSTANCE_
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_HSMCI_INSTANCE_ */
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ACC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDP_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM4S_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM3S_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM4S_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM4S_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM4S_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM4S_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+#ifdef _SAM4S_HSMCI_INSTANCE_
+	(void*) HSMCI_Handler,   /* 18 MCI */
+#else
+	(void*) (0UL),           /* 18 Reserved */
+#endif /* _SAM4S_HSMCI_INSTANCE_ */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM4S_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM4S_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16_flash.ld
new file mode 100644
index 0000000..de4d089
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16_flash.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal FLASH on the SAM4S16
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* flash, 1024K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16_sram.ld
new file mode 100644
index 0000000..e81654f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16_sram.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal SRAM on the SAM4S16
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* flash, 1024K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16b_flash.ld
new file mode 100644
index 0000000..d17bb71
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16b_sram.ld
new file mode 100644
index 0000000..038ad37
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16c_flash.ld
new file mode 100644
index 0000000..d17bb71
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16c_sram.ld
new file mode 100644
index 0000000..038ad37
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s16c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8_flash.ld
new file mode 100644
index 0000000..d50c9af
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8_flash.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal FLASH on the SAM4S8
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8_sram.ld
new file mode 100644
index 0000000..8863ae4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8_sram.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal SRAM on the SAM4S8
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8b_flash.ld
new file mode 100644
index 0000000..665a6ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8b_sram.ld
new file mode 100644
index 0000000..28497d6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8c_flash.ld
new file mode 100644
index 0000000..665a6ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8c_sram.ld
new file mode 100644
index 0000000..28497d6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/sam4s_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/startup_sam4s.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/startup_sam4s.c
new file mode 100644
index 0000000..0592740
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc/startup_sam4s.c
@@ -0,0 +1,235 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam4s.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_SMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_USART1_INSTANCE_
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_USART1_INSTANCE_ */
+#ifdef _SAM4S_HSMCI_INSTANCE_
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_HSMCI_INSTANCE_ */
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ACC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDP_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM4S_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM4S_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM4S_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM4S_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM4S_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM4S_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+#ifdef _SAM4S_HSMCI_INSTANCE_
+	(void*) HSMCI_Handler,   /* 18 MCI */
+#else
+	(void*) (0UL),           /* 18 Reserved */
+#endif /* _SAM4S_HSMCI_INSTANCE_ */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM4S_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM4S_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16_flash.ld
new file mode 100644
index 0000000..de4d089
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16_flash.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal FLASH on the SAM4S16
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* flash, 1024K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16_sram.ld
new file mode 100644
index 0000000..e81654f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16_sram.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal SRAM on the SAM4S16
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* flash, 1024K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16b_flash.ld
new file mode 100644
index 0000000..d17bb71
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16b_sram.ld
new file mode 100644
index 0000000..038ad37
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16c_flash.ld
new file mode 100644
index 0000000..d17bb71
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16c_sram.ld
new file mode 100644
index 0000000..038ad37
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s16c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8_flash.ld
new file mode 100644
index 0000000..d50c9af
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8_flash.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal FLASH on the SAM4S8
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8_sram.ld
new file mode 100644
index 0000000..8863ae4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8_sram.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal SRAM on the SAM4S8
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8b_flash.ld
new file mode 100644
index 0000000..665a6ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8b_sram.ld
new file mode 100644
index 0000000..28497d6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8c_flash.ld
new file mode 100644
index 0000000..665a6ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8c_sram.ld
new file mode 100644
index 0000000..28497d6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/sam4s_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/startup_sam4s.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/startup_sam4s.c
new file mode 100644
index 0000000..0592740
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_arm/startup_sam4s.c
@@ -0,0 +1,235 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam4s.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_SMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_USART1_INSTANCE_
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_USART1_INSTANCE_ */
+#ifdef _SAM4S_HSMCI_INSTANCE_
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_HSMCI_INSTANCE_ */
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ACC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDP_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM4S_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM4S_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM4S_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM4S_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM4S_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM4S_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+#ifdef _SAM4S_HSMCI_INSTANCE_
+	(void*) HSMCI_Handler,   /* 18 MCI */
+#else
+	(void*) (0UL),           /* 18 Reserved */
+#endif /* _SAM4S_HSMCI_INSTANCE_ */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM4S_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM4S_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16_flash.ld
new file mode 100644
index 0000000..de4d089
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16_flash.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal FLASH on the SAM4S16
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* flash, 1024K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16_sram.ld
new file mode 100644
index 0000000..e81654f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16_sram.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal SRAM on the SAM4S16
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* flash, 1024K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16b_flash.ld
new file mode 100644
index 0000000..d17bb71
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16b_sram.ld
new file mode 100644
index 0000000..038ad37
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16c_flash.ld
new file mode 100644
index 0000000..d17bb71
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16c_sram.ld
new file mode 100644
index 0000000..038ad37
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s16c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s16_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8_flash.ld
new file mode 100644
index 0000000..d50c9af
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8_flash.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal FLASH on the SAM4S8
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8_sram.ld
new file mode 100644
index 0000000..8863ae4
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8_sram.ld
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ *      Linker script for running in internal SRAM on the SAM4S8
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* flash, 512K */
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000;
+
+INCLUDE sam4s_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8b_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8b_flash.ld
new file mode 100644
index 0000000..665a6ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8b_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8b_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8b_sram.ld
new file mode 100644
index 0000000..28497d6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8b_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8c_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8c_flash.ld
new file mode 100644
index 0000000..665a6ea
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8c_flash.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_flash.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8c_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8c_sram.ld
new file mode 100644
index 0000000..28497d6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s8c_sram.ld
@@ -0,0 +1,30 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+INCLUDE sam4s8_sram.ld
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s_flash.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s_flash.ld
new file mode 100644
index 0000000..802bd59
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s_flash.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s_sram.ld b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s_sram.ld
new file mode 100644
index 0000000..b035a42
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/sam4s_sram.ld
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/startup_sam4s.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/startup_sam4s.c
new file mode 100644
index 0000000..0592740
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/gcc_atmel/startup_sam4s.c
@@ -0,0 +1,235 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam4s.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M4 core handlers */
+void NMI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void MemManage_Handler  ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void BusFault_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DebugMon_Handler   ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler    ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SUPC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RSTC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EFC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART0_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UART1_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_SMC_INSTANCE_
+void SMC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_SMC_INSTANCE_ */
+void PIOA_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PIOB_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_PIOC_INSTANCE_
+void PIOC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_PIOC_INSTANCE_ */
+void USART0_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_USART1_INSTANCE_
+void USART1_Handler     ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_USART1_INSTANCE_ */
+#ifdef _SAM4S_HSMCI_INSTANCE_
+void HSMCI_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_HSMCI_INSTANCE_ */
+void TWI0_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TWI1_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SPI_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SSC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC2_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef _SAM4S_TC1_INSTANCE_
+void TC3_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif /* _SAM4S_TC1_INSTANCE_ */
+void ADC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DACC_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PWM_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void CRCCU_Handler      ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void ACC_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void UDP_Handler        ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+	/* Configure Initial Stack Pointer, using linker-generated symbols */
+	(void*) (&_estack),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM4S_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM4S_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM4S_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM4S_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM4S_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM4S_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+#ifdef _SAM4S_HSMCI_INSTANCE_
+	(void*) HSMCI_Handler,   /* 18 MCI */
+#else
+	(void*) (0UL),           /* 18 Reserved */
+#endif /* _SAM4S_HSMCI_INSTANCE_ */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM4S_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM4S_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+	uint32_t *pSrc, *pDest;
+
+	/* Initialize the relocate segment */
+	pSrc = &_etext;
+	pDest = &_srelocate;
+
+	if (pSrc != pDest) {
+		for (; pDest < &_erelocate;) {
+			*pDest++ = *pSrc++;
+		}
+	}
+
+	/* Clear the zero segment */
+	for (pDest = &_szero; pDest < &_ezero;) {
+		*pDest++ = 0;
+	}
+
+	/* Set the vector table base address */
+	pSrc = (uint32_t *) & _sfixed;
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	/* Initialize the C library */
+	__libc_init_array();
+
+	/* Branch to main function */
+	main();
+
+	/* Infinite loop */
+	while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+	while (1) {
+	}
+}
+
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/sam4s16_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/sam4s16_flash.icf
new file mode 100644
index 0000000..16203e3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/sam4s16_flash.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2001FFFF;
+define symbol __ICFEDIT_region_ROM_start__  = 0x00400000;
+define symbol __ICFEDIT_region_ROM_end__    = 0x004FFFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region     = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/sam4s16_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/sam4s16_sram.icf
new file mode 100644
index 0000000..8d3df52
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/sam4s16_sram.icf
@@ -0,0 +1,25 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2001FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/sam4s8_flash.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/sam4s8_flash.icf
new file mode 100644
index 0000000..7dc2615
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/sam4s8_flash.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00400000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2001FFFF;
+define symbol __ICFEDIT_region_ROM_start__  = 0x00400000;
+define symbol __ICFEDIT_region_ROM_end__    = 0x0047FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ROM_region     = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/sam4s8_sram.icf b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/sam4s8_sram.icf
new file mode 100644
index 0000000..8d3df52
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/sam4s8_sram.icf
@@ -0,0 +1,25 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2001FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM_region     = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy with packing=none { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in RAM_region          { readonly };
+place in RAM_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/startup_sam4s.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/startup_sam4s.c
new file mode 100644
index 0000000..59e7be3
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/iar/startup_sam4s.c
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam4s.h"
+
+typedef void (*intfunc) (void);
+typedef union { intfunc __fun; void * __ptr; } intvec_elem;
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M3 core handlers */
+#pragma weak NMI_Handler=Dummy_Handler
+#pragma weak HardFault_Handler=Dummy_Handler
+#pragma weak MemManage_Handler=Dummy_Handler
+#pragma weak BusFault_Handler=Dummy_Handler
+#pragma weak UsageFault_Handler=Dummy_Handler
+#pragma weak SVC_Handler=Dummy_Handler
+#pragma weak DebugMon_Handler=Dummy_Handler
+#pragma weak PendSV_Handler=Dummy_Handler
+#pragma weak SysTick_Handler=Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak SUPC_Handler=Dummy_Handler
+#pragma weak RSTC_Handler=Dummy_Handler
+#pragma weak RTC_Handler=Dummy_Handler
+#pragma weak RTT_Handler=Dummy_Handler
+#pragma weak WDT_Handler=Dummy_Handler
+#pragma weak PMC_Handler=Dummy_Handler
+#pragma weak EFC_Handler=Dummy_Handler
+#pragma weak UART0_Handler=Dummy_Handler
+#pragma weak UART1_Handler=Dummy_Handler
+#ifdef _SAM4S_SMC_INSTANCE_
+#pragma weak SMC_Handler=Dummy_Handler
+#endif /* _SAM4S_SMC_INSTANCE_ */
+#pragma weak PIOA_Handler=Dummy_Handler
+#pragma weak PIOB_Handler=Dummy_Handler
+#ifdef _SAM4S_PIOC_INSTANCE_
+#pragma weak PIOC_Handler=Dummy_Handler
+#endif /* _SAM4S_PIOC_INSTANCE_ */
+#pragma weak USART0_Handler=Dummy_Handler
+#ifdef _SAM4S_USART1_INSTANCE_
+#pragma weak USART1_Handler=Dummy_Handler
+#endif /* _SAM4S_USART1_INSTANCE_ */
+#ifdef _SAM4S_HSMCI_INSTANCE_
+#pragma weak HSMCI_Handler=Dummy_Handler
+#endif /* _SAM4S_HSMCI_INSTANCE_ */
+#pragma weak TWI0_Handler=Dummy_Handler
+#pragma weak TWI1_Handler=Dummy_Handler
+#pragma weak SPI_Handler=Dummy_Handler
+#pragma weak SSC_Handler=Dummy_Handler
+#pragma weak TC0_Handler=Dummy_Handler
+#pragma weak TC1_Handler=Dummy_Handler
+#pragma weak TC2_Handler=Dummy_Handler
+#ifdef _SAM4S_TC1_INSTANCE_
+#pragma weak TC3_Handler=Dummy_Handler
+#pragma weak TC4_Handler=Dummy_Handler
+#pragma weak TC5_Handler=Dummy_Handler
+#endif /* _SAM4S_TC1_INSTANCE_ */
+#pragma weak ADC_Handler=Dummy_Handler
+#pragma weak DACC_Handler=Dummy_Handler
+#pragma weak PWM_Handler=Dummy_Handler
+#pragma weak CRCCU_Handler=Dummy_Handler
+#pragma weak ACC_Handler=Dummy_Handler
+#pragma weak UDP_Handler=Dummy_Handler
+
+/* Exception Table */
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section = ".intvec"
+#pragma location = ".intvec"
+const DeviceVectors __vector_table[] = {
+	(void*) (&__cstack_end__),
+	(void*) Reset_Handler,
+
+	(void*) NMI_Handler,
+	(void*) HardFault_Handler,
+	(void*) MemManage_Handler,
+	(void*) BusFault_Handler,
+	(void*) UsageFault_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) (0UL),           /* Reserved */
+	(void*) SVC_Handler,
+	(void*) DebugMon_Handler,
+	(void*) (0UL),           /* Reserved */
+	(void*) PendSV_Handler,
+	(void*) SysTick_Handler,
+
+	/* Configurable interrupts */
+	(void*) SUPC_Handler,    /* 0  Supply Controller */
+	(void*) RSTC_Handler,    /* 1  Reset Controller */
+	(void*) RTC_Handler,     /* 2  Real Time Clock */
+	(void*) RTT_Handler,     /* 3  Real Time Timer */
+	(void*) WDT_Handler,     /* 4  Watchdog Timer */
+	(void*) PMC_Handler,     /* 5  PMC */
+	(void*) EFC_Handler,     /* 6  EEFC */
+	(void*) (0UL),           /* 7  Reserved */
+	(void*) UART0_Handler,   /* 8  UART0 */
+	(void*) UART1_Handler,   /* 9  UART1 */
+#ifdef _SAM4S_SMC_INSTANCE_
+	(void*) SMC_Handler,     /* 10 SMC */
+#else
+	(void*) (0UL),           /* 10 Reserved */
+#endif /* _SAM4S_SMC_INSTANCE_ */
+	(void*) PIOA_Handler,    /* 11 Parallel IO Controller A */
+	(void*) PIOB_Handler,    /* 12 Parallel IO Controller B */
+#ifdef _SAM4S_PIOC_INSTANCE_
+	(void*) PIOC_Handler,    /* 13 Parallel IO Controller C */
+#else
+	(void*) (0UL),           /* 13 Reserved */
+#endif /* _SAM4S_PIOC_INSTANCE_ */
+	(void*) USART0_Handler,  /* 14 USART 0 */
+#ifdef _SAM4S_USART1_INSTANCE_
+	(void*) USART1_Handler,  /* 15 USART 1 */
+#else
+	(void*) (0UL),           /* 15 Reserved */
+#endif /* _SAM4S_USART1_INSTANCE_ */
+	(void*) (0UL),           /* 16 Reserved */
+	(void*) (0UL),           /* 17 Reserved */
+#ifdef _SAM4S_HSMCI_INSTANCE_
+	(void*) HSMCI_Handler,   /* 18 MCI */
+#else
+	(void*) (0UL),           /* 18 Reserved */
+#endif /* _SAM4S_HSMCI_INSTANCE_ */
+	(void*) TWI0_Handler,    /* 19 TWI 0 */
+	(void*) TWI1_Handler,    /* 20 TWI 1 */
+	(void*) SPI_Handler,     /* 21 SPI */
+	(void*) SSC_Handler,     /* 22 SSC */
+	(void*) TC0_Handler,     /* 23 Timer Counter 0 */
+	(void*) TC1_Handler,     /* 24 Timer Counter 1 */
+	(void*) TC2_Handler,     /* 25 Timer Counter 2 */
+#ifdef _SAM4S_TC1_INSTANCE_
+	(void*) TC3_Handler,     /* 26 Timer Counter 3 */
+	(void*) TC4_Handler,     /* 27 Timer Counter 4 */
+	(void*) TC5_Handler,     /* 28 Timer Counter 5 */
+#else
+	(void*) (0UL),           /* 26 Reserved */
+	(void*) (0UL),           /* 27 Reserved */
+	(void*) (0UL),           /* 28 Reserved */
+#endif /* _SAM4S_TC1_INSTANCE_ */
+	(void*) ADC_Handler,     /* 29 ADC controller */
+	(void*) DACC_Handler,    /* 30 DAC controller */
+	(void*) PWM_Handler,     /* 31 PWM */
+	(void*) CRCCU_Handler,   /* 32 CRC Calculation Unit */
+	(void*) ACC_Handler,     /* 33 Analog Comparator */
+	(void*) UDP_Handler      /* 34 USB Device Port */
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+	uint32_t *pSrc = __section_begin(".intvec");
+
+	SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+	if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < (uint32_t) IRAM_ADDR + (uint32_t) IRAM_SIZE)) {
+		SCB->VTOR |= (1UL) << SCB_VTOR_TBLBASE_Pos;
+	}
+
+	return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+	__iar_program_start();
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/system_sam4s.c b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/system_sam4s.c
new file mode 100644
index 0000000..e2d1094
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/ATMEL/sam4s/source/system_sam4s.c
@@ -0,0 +1,198 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "sam4s.h"
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/* @endcond */
+
+/* Clock Settings (120MHz) */
+#define SYS_BOARD_OSCOUNT   (CKGR_MOR_MOSCXTST(0x8U))
+#define SYS_BOARD_PLLAR     (CKGR_PLLAR_ONE \
+							| CKGR_PLLAR_MULA(0x13U) \
+							| CKGR_PLLAR_PLLACOUNT(0x3fU) \
+							| CKGR_PLLAR_DIVA(0x1U))
+#define SYS_BOARD_MCKR      (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)
+
+#define SYS_CKGR_MOR_KEY_VALUE	CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
+
+/* FIXME: should be generated by sock */
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+/**
+ * \brief Setup the microcontroller system.
+ * Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit(void)
+{
+	/* Set FWS according to SYS_BOARD_MCKR configuration */
+	EFC->EEFC_FMR = EEFC_FMR_FWS(4);
+
+	/* Initialize main oscillator */
+	if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
+		PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
+			                     CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+		while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
+		}
+	}
+
+	/* Switch to 3-20MHz Xtal oscillator */
+	PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
+	                           CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+
+	while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
+	}
+		PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) |
+			                    PMC_MCKR_CSS_MAIN_CLK;
+		while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Initialize PLLA */
+	PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
+	while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
+	}
+
+	/* Switch to main clock */
+	PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	/* Switch to PLLA */
+	PMC->PMC_MCKR = SYS_BOARD_MCKR;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
+	}
+
+	SystemCoreClock = CHIP_FREQ_CPU_MAX;
+}
+
+void SystemCoreClockUpdate(void)
+{
+	/* Determine clock frequency according to clock register values */
+	switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) {
+	case PMC_MCKR_CSS_SLOW_CLK:	/* Slow clock */
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_32K;
+		} else {
+			SystemCoreClock = CHIP_FREQ_SLCK_RC;
+		}
+		break;
+	case PMC_MCKR_CSS_MAIN_CLK:	/* Main clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		break;
+	case PMC_MCKR_CSS_PLLA_CLK:	/* PLLA clock */
+	case PMC_MCKR_CSS_PLLB_CLK:	/* PLLB clock */
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
+			SystemCoreClock = CHIP_FREQ_XTAL_12M;
+		} else {
+			SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
+
+			switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
+			case CKGR_MOR_MOSCRCF_4_MHz:
+				break;
+			case CKGR_MOR_MOSCRCF_8_MHz:
+				SystemCoreClock *= 2U;
+				break;
+			case CKGR_MOR_MOSCRCF_12_MHz:
+				SystemCoreClock *= 3U;
+				break;
+			default:
+				break;
+			}
+		}
+		if ((uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
+			SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
+				                          CKGR_PLLAR_MULA_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
+				                          CKGR_PLLAR_DIVA_Pos));
+		} else {
+			SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >>
+				                           CKGR_PLLBR_MULB_Pos) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >>
+				                               CKGR_PLLBR_DIVB_Pos));
+		}
+		break;
+	default:
+		break;
+	}
+
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
+		SystemCoreClock /= 3U;
+	} else {
+		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
+	}
+}
+
+/**
+ * Initialize flash.
+ */
+void system_init_flash(uint32_t dw_clk)
+{
+	/* Set FWS for embedded Flash access according to operating frequency */
+	if (dw_clk < CHIP_FREQ_FWS_0) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(0);
+	} else if (dw_clk < CHIP_FREQ_FWS_1) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(1);
+	} else if (dw_clk < CHIP_FREQ_FWS_2) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(2);
+	} else if (dw_clk < CHIP_FREQ_FWS_3) {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(3);
+	} else {
+		EFC->EEFC_FMR = EEFC_FMR_FWS(4);
+	}
+}
+
+/* @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/* @endcond */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/ReadMe.txt b/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/ReadMe.txt
new file mode 100644
index 0000000..ba985a9
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/ReadMe.txt
@@ -0,0 +1,64 @@
+/*****************************************************************************
+ * @file     ReadMe.txt
+ * @purpose  Explanation how to use the Device folder and template files 
+ * @version  V2.10
+ * @date     25. July 2011
+ *****************************************************************************/
+
+Following directory structure and template files are given:
+
+  - 
+      |
+      +-- 
+            |
+            +-- Include
+            |     +- .h                           header file 
+            |     +- system_Device.h                      system include file 
+            +-- Source
+                  |
+                  + Templates
+                      +- system_.c                system source file 
+                      |
+                      +-- ARM
+                      |    +- startup_.s          startup file for ARMCC
+                      |
+                      +-- GCC
+                      |
+                      +-- IAR
+
+
+Copy the complete folder including files and replace:
+  - folder name 'Vendor' with the abbreviation for the device vendor  e.g.: NXP. 
+  - folder name 'Device' with your specific device name e.g.: LPC17xx.
+  - in the filenames 'Device' with your specific device name e.g.: LPC17xx. 
+
+
+The template files contain comments starting with 'ToDo: '
+There it is described what you need to do.
+
+
+The template files contain following placeholder:
+
+  
+   should be replaced with your specific device name.
+   e.g.: LPC17xx
+  
+  
+   should be replaced with a specific device interrupt name.
+  e.g.: TIM1 for Timer#1 interrupt.
+
+  
+   should be replaced with a dedicated device family
+  abbreviation (e.g.: LPC for LPC17xx device family)
+
+  Cortex-M#
+  Cortex-M# can be replaced with the specific Cortex-M number
+  e.g.: Cortex-M3
+
+
+
+Note:
+  Template files (i.e. startup_Device.s, system_Device.c) are application
+  specific and therefore expected to be copied into the application project
+  folder prior to use!
+  
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/Vendor/Device/Include/Device.h b/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/Vendor/Device/Include/Device.h
new file mode 100644
index 0000000..317e898
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/Vendor/Device/Include/Device.h
@@ -0,0 +1,204 @@
+/**************************************************************************//**
+ * @file     .h
+ * @brief    CMSIS Cortex-M# Core Peripheral Access Layer Header File 
+ *           for the Device Series ...
+ * @version  V2.10
+ * @date     20. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef _H      /* ToDo: replace '' with your device name */
+#define _H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* ToDo: replace '' with your device name; add your doxyGen comment   */
+/** @addtogroup _Definitions  Definitions
+  This file defines all structures and symbols for :
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - Peripheral definitions
+  @{
+*/
+
+
+/******************************************************************************/
+/*                Processor and Core Peripherals                              */
+/******************************************************************************/
+/** @addtogroup _CMSIS Device CMSIS Definitions
+  Configuration of the Cortex-M# Processor and Core Peripherals
+  @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/******  Cortex-M# Processor Exceptions Numbers ***************************************************/
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device                   */
+  NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
+  HardFault_IRQn                = -13,      /*!<  3 Hard Fault Interrupt                          */
+  SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
+  PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
+  SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M3 / Cortex-M4 device       */
+  NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
+  MemoryManagement_IRQn         = -12,      /*!<  4 Memory Management Interrupt                   */
+  BusFault_IRQn                 = -11,      /*!<  5 Bus Fault Interrupt                           */
+  UsageFault_IRQn               = -10,      /*!<  6 Usage Fault Interrupt                         */
+  SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
+  DebugMonitor_IRQn             = -4,       /*!< 12 Debug Monitor Interrupt                       */
+  PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
+  SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */
+
+/******  Device Specific Interrupt Numbers ********************************************************/
+/* ToDo: add here your device specific external interrupt numbers
+         according the interrupt handlers defined in startup_Device.s
+         eg.: Interrupt for Timer#1       TIM1_IRQHandler   ->   TIM1_IRQn                        */
+  _IRQn        = 0,        /*!< Device Interrupt                                 */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M# Processor and Core Peripherals */
+/* ToDo: set the defines according your Device                                                    */
+/* ToDo: define the correct core revision
+         __CM0_REV if your device is a CORTEX-M0 device
+         __CM3_REV if your device is a CORTEX-M3 device
+         __CM4_REV if your device is a CORTEX-M4 device                                           */
+#define __CM#_REV                 0x0201    /*!< Core Revision r2p1                               */
+#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+#define __MPU_PRESENT             1         /*!< MPU present or not                               */
+/* ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4                                       */
+#define __FPU_PRESENT                      /*!< FPU present or not                                */
+
+/*@}*/ /* end of group _CMSIS */
+
+
+/* ToDo: include the correct core_cm#.h file
+         core_cm0.h if your device is a CORTEX-M0 device
+         core_cm3.h if your device is a CORTEX-M3 device
+         core_cm4.h if your device is a CORTEX-M4 device                                          */
+#include                        /* Cortex-M# processor and core peripherals           */
+/* ToDo: include your system_.h file
+         replace '' with your device name                                                 */
+#include "system_.h"                /*  System  include file                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+/** @addtogroup _Peripherals  Peripherals
+   Device Specific Peripheral registers structures
+  @{
+*/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/* ToDo: add here your device specific peripheral access structure typedefs
+         following is an example for a timer                                  */
+
+/*------------- 16-bit Timer/Event Counter (TMR) -----------------------------*/
+/** @addtogroup _TMR  16-bit Timer/Event Counter (TMR)
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t EN;                         /*!< Offset: 0x0000   Timer Enable Register           */               
+  __IO uint32_t RUN;                        /*!< Offset: 0x0004   Timer RUN Register              */
+  __IO uint32_t CR;                         /*!< Offset: 0x0008   Timer Control Register          */
+  __IO uint32_t MOD;                        /*!< Offset: 0x000C   Timer Mode Register             */
+       uint32_t RESERVED0[1];
+  __IO uint32_t ST;                         /*!< Offset: 0x0014   Timer Status Register           */
+  __IO uint32_t IM;                         /*!< Offset: 0x0018   Interrupt Mask Register         */
+  __IO uint32_t UC;                         /*!< Offset: 0x001C   Timer Up Counter Register       */
+  __IO uint32_t RG0                         /*!< Offset: 0x0020   Timer Register                  */
+       uint32_t RESERVED1[2];
+  __IO uint32_t CP;                         /*!< Offset: 0x002C   Capture register                */
+} _TMR_TypeDef;
+/*@}*/ /* end of group _TMR */
+
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+/*@}*/ /* end of group _Peripherals */
+
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* ToDo: add here your device peripherals base addresses                
+         following is an example for timer                                    */
+/** @addtogroup _MemoryMap  Memory Mapping
+  @{
+*/
+
+/* Peripheral and SRAM base address */
+#define _FLASH_BASE       (0x00000000UL)                              /*!< (FLASH     ) Base Address */
+#define _SRAM_BASE        (0x20000000UL)                              /*!< (SRAM      ) Base Address */
+#define _PERIPH_BASE      (0x40000000UL)                              /*!< (Peripheral) Base Address */
+
+/* Peripheral memory map */
+#define TIM0_BASE         (_PERIPH_BASE)          /*!< (Timer0    ) Base Address */
+#define TIM1_BASE         (_PERIPH_BASE + 0x0800) /*!< (Timer1    ) Base Address */
+#define TIM2_BASE         (_PERIPH_BASE + 0x1000) /*!< (Timer2    ) Base Address */
+/*@}*/ /* end of group _MemoryMap */
+
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+/* ToDo: add here your device peripherals pointer definitions                
+         following is an example for timer                                    */
+
+/** @addtogroup _PeripheralDecl  Peripheral Declaration
+  @{
+*/
+
+#define _TIM0        ((_TMR_TypeDef *) TIM0_BASE)
+#define _TIM1        ((_TMR_TypeDef *) TIM0_BASE)
+#define _TIM2        ((_TMR_TypeDef *) TIM0_BASE)
+/*@}*/ /* end of group _PeripheralDecl */
+
+/*@}*/ /* end of group _Definitions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _H */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/Vendor/Device/Include/system_Device.h b/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/Vendor/Device/Include/system_Device.h
new file mode 100644
index 0000000..b3f3c5b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/Vendor/Device/Include/system_Device.h
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file     system_.h
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Header File
+ *           for the Device Series ...
+ * @version  V2.10
+ * @date     20. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef SYSTEM__H   /* ToDo: replace '' with your device name */
+#define SYSTEM__H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM__H */
diff --git a/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/Vendor/Device/Source/Templates/ARM/startup_Device.s b/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/Vendor/Device/Source/Templates/ARM/startup_Device.s
new file mode 100644
index 0000000..380634b
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/Vendor/Device/Source/Templates/ARM/startup_Device.s
@@ -0,0 +1,182 @@
+;/*****************************************************************************
+; * @file:    startup_.s
+; * @purpose: CMSIS Cortex-M# Core Device Startup File for the 
+; *           Device  
+; * @version: V2.10
+; * @date:    20. July 2011
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2010 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+; ToDo:  Add here the vectors for the device specific external interrupts handler
+                DCD     _IRQHandler       ;  0: Default
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+
+Default_Handler PROC
+; ToDo:  Add here the export definition for the device specific external interrupts handler 
+                EXPORT  _IRQHandler         [WEAK]
+
+; ToDo:  Add here the names for the device specific external interrupts handler
+_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/Vendor/Device/Source/Templates/system_Device.c b/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/Vendor/Device/Source/Templates/system_Device.c
new file mode 100644
index 0000000..0417f57
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Device/_Template_Vendor/Vendor/Device/Source/Templates/system_Device.c
@@ -0,0 +1,82 @@
+/**************************************************************************//**
+ * @file     system_.c
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Source File
+ *           for the Device Series ...
+ * @version  V2.10
+ * @date     20. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include 
+#include ".h"
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+    
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+/* ToDo: add here your necessary defines for device initialization     
+         following is an example for different system frequencies             */
+#define __HSI             ( 6000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+#define __SYS_OSC_CLK     (    ___HSI)    /* Main oscillator frequency        */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/* ToDo: initialize SystemCoreClock with the system core clock frequency value
+         achieved after system intitialization.
+         This means system core clock frequency after call to SystemInit()    */
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;  /*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+/* ToDo: add code to calculate the system frequency based upon the current
+         register settings.
+         This function can be used to retrieve the system core clock frequeny
+         after user changed register sittings.                                */
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+/* ToDo: add code to initialize the system
+         do not use global variables because this function is called before
+         reaching pre-main. RW section maybe overwritten afterwards.          */
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/conf_board.h b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/conf_board.h
new file mode 100644
index 0000000..75917bd
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/conf_board.h
@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef CONF_BOARD_H_INCLUDED
+#define CONF_BOARD_H_INCLUDED
+
+#define SAM3S_EK                       (1)
+#define SAM3S_EK2                      (2)
+#define SAM3N_EK                       (3)
+#define SAM3U_EK                       (4)
+#define SAM3X_EK                       (5)
+#define SAM4S_EK                       (6)
+
+#ifndef BOARD
+#  error "BOARD is not defined"
+#endif
+
+#if BOARD == SAM3S_EK
+#  define LED0_PIO		PIOA
+#  define LED0_MASK		(0x01UL << 19)
+#endif /* SAM3S_EK */
+
+#if BOARD == SAM3S_EK2
+#  define LED0_PIO		PIOA
+#  define LED0_MASK		(0x01UL << 19)
+#endif /* SAM3S_EK2 */
+
+#if BOARD == SAM3N_EK
+#  define LED0_PIO		PIOA
+#  define LED0_MASK		(0x01UL << 23)
+#endif /* SAM3N_EK */
+
+#if BOARD == SAM3U_EK
+#  define LED0_PIO		PIOB
+#  define LED0_MASK		(0x01UL << 0)
+#endif /* SAM3U_EK */
+
+#if BOARD == SAM3X_EK
+#  define LED0_PIO		PIOB
+#  define LED0_MASK		(0x01UL << 12)
+#endif /* SAM3X_EK */
+
+#if BOARD == SAM4S_EK
+#  define LED0_PIO		PIOA
+#  define LED0_MASK		(0x01UL << 19)
+#endif /* SAM4S_EK */
+
+#endif /* CONF_BOARD_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/Makefile b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/Makefile
new file mode 100644
index 0000000..2573603
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/Makefile
@@ -0,0 +1,75 @@
+# ----------------------------------------------------------------------------
+#         ATMEL Microcontroller Software Support 
+# ----------------------------------------------------------------------------
+# Copyright (c) 2010, Atmel Corporation
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following condition is met:
+#
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the disclaimer below.
+#
+# Atmel's name may not be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# ----------------------------------------------------------------------------
+
+# make inner variables
+.DEFAULT_GOAL := all
+
+# custom variables
+BUILD_NUMBER := 
+BUILDS := 
+CLEANS :=
+
+# Build macro
+define BUILD_SERIES
+
+# output test number information
+$(info Defining cmsis_example_$(1)_build and cmsis_example_$(1)_clean)
+
+# add the incoming targets to global targets
+BUILDS += cmsis_example_$(1)_build
+CLEANS += cmsis_example_$(1)_clean
+BUILD_NUMBER += x
+
+.PHONY: cmsis_example_$(1)_build
+cmsis_example_$(1)_build:
+	@echo --- 
+	@echo --- 
+	@echo --- Making $(1)
+	@echo --- 
+	@$(MAKE) CHIP=$(1) -f cmsis_example.mk
+	
+.PHONY: cmsis_example_$(1)_clean
+cmsis_example_$(1)_clean:
+	@echo --- 
+	@echo --- 
+	@echo --- Cleaning $(1)
+	@echo --- 
+	@$(MAKE) CHIP=$(1) clean -f cmsis_example.mk
+endef
+
+# define SAM series
+include sam_series.mk
+
+$(foreach SERIES, $(SAM_SERIES), $(eval $(call BUILD_SERIES,$(SERIES))))
+
+# output test number information
+$(info Number of devices to be tested $(words $(BUILD_NUMBER)) /  $(words $(SAM_SERIES)))
+
+all: $(BUILDS)
+
+clean: $(CLEANS)
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/build.bat b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/build.bat
new file mode 100644
index 0000000..a56554a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/build.bat
@@ -0,0 +1 @@
+@cs-make --no-builtin-rules --no-builtin-variables >log.txt 2>&1
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/build_debug.bat b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/build_debug.bat
new file mode 100644
index 0000000..32df4a6
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/build_debug.bat
@@ -0,0 +1 @@
+@cs-make --no-builtin-rules --no-builtin-variables -d >log_debug.txt 2>&1
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/cmsis_example.mk b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/cmsis_example.mk
new file mode 100644
index 0000000..8b686be
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/cmsis_example.mk
@@ -0,0 +1,195 @@
+# ----------------------------------------------------------------------------
+#         ATMEL Microcontroller Software Support
+# ----------------------------------------------------------------------------
+# Copyright (c) 2010, Atmel Corporation
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following condition is met:
+#
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the disclaimer below.
+#
+# Atmel's name may not be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# ----------------------------------------------------------------------------
+
+#-------------------------------------------------------------------------------
+#        User-modifiable options
+#-------------------------------------------------------------------------------
+
+ifeq ('$(CHIP)','')
+$(error CHIP not defined)
+endif
+
+include sam_series.mk
+
+# fill the needed variables
+ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3N)))
+
+BOARD:=SAM3N_EK
+SERIES:=sam3n
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3S)))
+
+BOARD:=SAM3S_EK
+SERIES:=sam3s
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3SD8)))
+
+BOARD:=SAM3S_EK2
+SERIES:=sam3sd8
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3U)))
+
+BOARD:=SAM3U_EK
+SERIES:=sam3u
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3XA)))
+
+BOARD:=SAM3X_EK
+SERIES:=sam3xa
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM4S)))
+
+BOARD:=SAM4S_EK
+SERIES:=sam4s
+
+endif
+
+
+# Defines which are the available memory targets for the device.
+MEMORIES = sram flash
+
+# Optimization level, put in comment for debugging
+OPTIMIZATION = -Os
+
+# Output directories
+BIN = $(CHIP)_bin
+OBJ = $(CHIP)_obj
+
+# Output file basename
+OUTPUT_BIN = $(BIN)/cmsis_example_$(BOARD)_$(CHIP)
+
+# GCC toolchain provider
+GCC_TOOLCHAIN=gcc
+
+#-------------------------------------------------------------------------------
+#		Tools
+#-------------------------------------------------------------------------------
+
+# Toolchain prefix when cross-compiling
+CROSS_COMPILE = arm-none-eabi-
+
+CMSIS_ROOT=../../..
+CMSIS_PATH=$(CMSIS_ROOT)/CMSIS/Include
+SAM_PATH=$(CMSIS_ROOT)/Device/ATMEL
+DEVICE_PATH=$(SAM_PATH)/$(SERIES)/source
+
+LIBS = -Wl,--start-group -lgcc -lc -Wl,--end-group
+
+LIB_PATH+=-L=/lib/thumb2
+LIB_PATH+=-L"$(realpath $(DEVICE_PATH)/$(GCC_TOOLCHAIN))"
+
+# Compilation tools
+CC = $(CROSS_COMPILE)gcc
+LD = $(CROSS_COMPILE)ld
+SIZE = $(CROSS_COMPILE)size
+STRIP = $(CROSS_COMPILE)strip
+OBJCOPY = $(CROSS_COMPILE)objcopy
+GDB = $(CROSS_COMPILE)gdb
+NM = $(CROSS_COMPILE)nm
+RM = cs-rm
+
+# Flags
+INCLUDES := -I"$(CMSIS_PATH)"
+INCLUDES += -I"$(SAM_PATH)"
+INCLUDES += -I"$(SAM_PATH)/$(SERIES)/include"
+
+CFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
+CFLAGS += -Werror-implicit-function-declaration -Wmain -Wparentheses
+CFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CFLAGS += -Wshadow -Wpointer-arith -Wbad-function-cast -Wwrite-strings
+CFLAGS += -Wsign-compare -Waggregate-return -Wstrict-prototypes
+CFLAGS += -Wmissing-prototypes -Wmissing-declarations
+CFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CFLAGS += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long
+CFLAGS += -Wunreachable-code
+CFLAGS += -Wcast-align
+#CFLAGS += -Wmissing-noreturn
+#CFLAGS += -Wconversion
+
+# To reduce application size use only integer printf function.
+CFLAGS += -Dprintf=iprintf
+
+# -mlong-calls  -Wall
+CFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -ffunction-sections
+CFLAGS += -g $(OPTIMIZATION) $(INCLUDES) -D__$(CHIP)__ -DBOARD=$(BOARD)
+ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -g $(OPTIMIZATION) $(INCLUDES) -D__$(CHIP)__ -D__ASSEMBLY__
+LDFLAGS= -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols
+#LD_OPTIONAL=-Wl,--print-gc-sections -Wl,--stats
+
+#-------------------------------------------------------------------------------
+#		Files
+#-------------------------------------------------------------------------------
+
+# Directories where source files can be found
+
+VPATH += ..
+VPATH += $(DEVICE_PATH)
+VPATH += $(DEVICE_PATH)/$(GCC_TOOLCHAIN)
+
+# Objects built from C source files
+C_OBJECTS += main.o
+C_OBJECTS += startup_$(SERIES).o
+C_OBJECTS += system_$(SERIES).o
+
+# Append OBJ and BIN directories to output filename
+OUTPUT := $(BIN)/$(OUTPUT_BIN)
+
+#-------------------------------------------------------------------------------
+#		Rules
+#-------------------------------------------------------------------------------
+
+all: $(BIN) $(OBJ) $(MEMORIES)
+
+$(BIN) $(OBJ):
+	-@mkdir $@
+
+define RULES
+C_OBJECTS_$(1) = $(addprefix $(OBJ)/$(1)_, $(C_OBJECTS))
+ASM_OBJECTS_$(1) = $(addprefix $(OBJ)/$(1)_, $(ASM_OBJECTS))
+
+$(1): $$(ASM_OBJECTS_$(1)) $$(C_OBJECTS_$(1))
+	$(CC) $(LIB_PATH) $(LDFLAGS) $(LD_OPTIONAL) -T"$(realpath $(DEVICE_PATH)/$(GCC_TOOLCHAIN)/$(CHIP)_$$@.ld)" -Wl,-Map,"$(OUTPUT_BIN)_$$@.map" -o "$(OUTPUT_BIN)_$$@.elf" $$^ $(LIBS)
+	@$(NM) "$(OUTPUT_BIN)_$$@.elf" >"$(OUTPUT_BIN)_$$@.elf.txt"
+	@$(OBJCOPY) -O binary "$(OUTPUT_BIN)_$$@.elf" "$(OUTPUT_BIN)_$$@.bin"
+	@$(SIZE) $$^ "$(OUTPUT_BIN)_$$@.elf"
+
+$$(C_OBJECTS_$(1)): $(OBJ)/$(1)_%.o: %.c Makefile $(OBJ) $(BIN)
+	@$(CC) $(CFLAGS) -D$(1) -c -o $$@ $$<
+
+$$(ASM_OBJECTS_$(1)): $(OBJ)/$(1)_%.o: %.S Makefile $(OBJ) $(BIN)
+	@$(CC) $(ASFLAGS) -D$(1) -c -o $$@ $$<
+
+debug_$(1): $(1)
+	$(GDB) -x "$(CHIP)_$(1).gdb" -ex "reset" -readnow -se "$(OUTPUT_BIN)_$(1).elf"
+endef
+
+$(foreach MEMORY, $(MEMORIES), $(eval $(call RULES,$(MEMORY))))
+
+clean:
+	-$(RM) -fR $(OBJ) $(BIN)
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3n_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3n_ek_flash.gdb
new file mode 100644
index 0000000..344beda
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3n_ek_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3N.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3N4C
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x00400000)
+#set *0x400004 = *0x400004 & 0xFFFFFFFE
+mon reg pc=(0x00400004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3n_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3n_ek_sram.gdb
new file mode 100644
index 0000000..ac5d63a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3n_ek_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3N.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3s_ek2_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3s_ek2_flash.gdb
new file mode 100644
index 0000000..095a174
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3s_ek2_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3S.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3S4C
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x400000)
+#set *0x400004 = *0x400004 & 0xFFFFFFFE
+mon reg pc=(0x400004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3s_ek2_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3s_ek2_sram.gdb
new file mode 100644
index 0000000..e936ff7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3s_ek2_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3S.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3s_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3s_ek_flash.gdb
new file mode 100644
index 0000000..095a174
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3s_ek_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3S.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3S4C
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x400000)
+#set *0x400004 = *0x400004 & 0xFFFFFFFE
+mon reg pc=(0x400004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3s_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3s_ek_sram.gdb
new file mode 100644
index 0000000..e936ff7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3s_ek_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3S.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3u_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3u_ek_flash.gdb
new file mode 100644
index 0000000..70933c7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3u_ek_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3U.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3U4E
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1200 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x80000)
+#set *0x80004 = *0x80004 & 0xFFFFFFFE
+mon reg pc=(0x80004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3u_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3u_ek_sram.gdb
new file mode 100644
index 0000000..b658487
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3u_ek_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3U.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1200 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3x_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3x_ek_flash.gdb
new file mode 100644
index 0000000..dc1acb8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3x_ek_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3X.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3X8H
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1a00 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x80000)
+#set *0x80004 = *0x80004 & 0xFFFFFFFE
+mon reg pc=(0x80004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3x_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3x_ek_sram.gdb
new file mode 100644
index 0000000..a3f4293
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam3x_ek_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3X.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1a00 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam4s_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam4s_ek_flash.gdb
new file mode 100644
index 0000000..4482476
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam4s_ek_flash.gdb
@@ -0,0 +1,32 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device (Should be AT91SAM4S16C, but it is not available now)
+monitor flash device = AT91SAM4S16C
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral  (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initializing PC and stack pointer
+mon reg sp=(0x400000)
+mon reg pc=(0x400004)
+info reg
+
+# end of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam4s_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam4s_ek_sram.gdb
new file mode 100644
index 0000000..0834162
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam4s_ek_sram.gdb
@@ -0,0 +1,27 @@
+#*************************************************
+#
+#  Connect to J-Link and debug application in sram.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral  (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initializing PC and stack pointer
+mon reg sp=(0x20000000)
+mon reg pc=(0x20000004)
+info reg
+
+# end of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam_series.mk b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam_series.mk
new file mode 100644
index 0000000..bd9d190
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc/sam_series.mk
@@ -0,0 +1,37 @@
+# ----------------------------------------------------------------------------
+#         ATMEL Microcontroller Software Support
+# ----------------------------------------------------------------------------
+# Copyright (c) 2010, Atmel Corporation
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following condition is met:
+#
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the disclaimer below.
+#
+# Atmel's name may not be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# ----------------------------------------------------------------------------
+
+# define SAM series
+SAM3N=SAM3N00A SAM3N00B SAM3N0A SAM3N0B SAM3N0C SAM3N1A SAM3N1B SAM3N1C SAM3N2A SAM3N2B SAM3N2C SAM3N4A SAM3N4B SAM3N4C
+SAM3S=SAM3S1A SAM3S1B SAM3S1C SAM3S2A SAM3S2B SAM3S2C SAM3S4A SAM3S4B SAM3S4C
+SAM3SD8=SAM3S8B SAM3S8C SAM3SD8B SAM3SD8C
+SAM3U=SAM3U1C SAM3U1E SAM3U2C SAM3U2E SAM3U4C SAM3U4E
+SAM3XA=SAM3A4C SAM3A8C SAM3X4C SAM3X4E SAM3X8C SAM3X8E SAM3X8H
+SAM4S=SAM4S8B SAM4S8C SAM4S16B SAM4S16C
+
+SAM_SERIES=$(SAM3N) $(SAM3S) $(SAM3SD8) $(SAM3U) $(SAM3XA) $(SAM4S)
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/Makefile b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/Makefile
new file mode 100644
index 0000000..2573603
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/Makefile
@@ -0,0 +1,75 @@
+# ----------------------------------------------------------------------------
+#         ATMEL Microcontroller Software Support 
+# ----------------------------------------------------------------------------
+# Copyright (c) 2010, Atmel Corporation
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following condition is met:
+#
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the disclaimer below.
+#
+# Atmel's name may not be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# ----------------------------------------------------------------------------
+
+# make inner variables
+.DEFAULT_GOAL := all
+
+# custom variables
+BUILD_NUMBER := 
+BUILDS := 
+CLEANS :=
+
+# Build macro
+define BUILD_SERIES
+
+# output test number information
+$(info Defining cmsis_example_$(1)_build and cmsis_example_$(1)_clean)
+
+# add the incoming targets to global targets
+BUILDS += cmsis_example_$(1)_build
+CLEANS += cmsis_example_$(1)_clean
+BUILD_NUMBER += x
+
+.PHONY: cmsis_example_$(1)_build
+cmsis_example_$(1)_build:
+	@echo --- 
+	@echo --- 
+	@echo --- Making $(1)
+	@echo --- 
+	@$(MAKE) CHIP=$(1) -f cmsis_example.mk
+	
+.PHONY: cmsis_example_$(1)_clean
+cmsis_example_$(1)_clean:
+	@echo --- 
+	@echo --- 
+	@echo --- Cleaning $(1)
+	@echo --- 
+	@$(MAKE) CHIP=$(1) clean -f cmsis_example.mk
+endef
+
+# define SAM series
+include sam_series.mk
+
+$(foreach SERIES, $(SAM_SERIES), $(eval $(call BUILD_SERIES,$(SERIES))))
+
+# output test number information
+$(info Number of devices to be tested $(words $(BUILD_NUMBER)) /  $(words $(SAM_SERIES)))
+
+all: $(BUILDS)
+
+clean: $(CLEANS)
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/build.bat b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/build.bat
new file mode 100644
index 0000000..aa4e396
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/build.bat
@@ -0,0 +1 @@
+@make --no-builtin-rules --no-builtin-variables >log.txt 2>&1
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/build_debug.bat b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/build_debug.bat
new file mode 100644
index 0000000..d605bee
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/build_debug.bat
@@ -0,0 +1 @@
+@make --no-builtin-rules --no-builtin-variables -d >log_debug.txt 2>&1
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/cmsis_example.mk b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/cmsis_example.mk
new file mode 100644
index 0000000..1db5047
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/cmsis_example.mk
@@ -0,0 +1,195 @@
+# ----------------------------------------------------------------------------
+#         ATMEL Microcontroller Software Support
+# ----------------------------------------------------------------------------
+# Copyright (c) 2010, Atmel Corporation
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following condition is met:
+#
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the disclaimer below.
+#
+# Atmel's name may not be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# ----------------------------------------------------------------------------
+
+#-------------------------------------------------------------------------------
+#        User-modifiable options
+#-------------------------------------------------------------------------------
+
+ifeq ('$(CHIP)','')
+$(error CHIP not defined)
+endif
+
+include sam_series.mk
+
+# fill the needed variables
+ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3N)))
+
+BOARD:=SAM3N_EK
+SERIES:=sam3n
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3S)))
+
+BOARD:=SAM3S_EK
+SERIES:=sam3s
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3SD8)))
+
+BOARD:=SAM3S_EK2
+SERIES:=sam3sd8
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3U)))
+
+BOARD:=SAM3U_EK
+SERIES:=sam3u
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3XA)))
+
+BOARD:=SAM3X_EK
+SERIES:=sam3xa
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM4S)))
+
+BOARD:=SAM4S_EK
+SERIES:=sam4s
+
+endif
+
+
+# Defines which are the available memory targets for the device.
+MEMORIES = sram flash
+
+# Optimization level, put in comment for debugging
+OPTIMIZATION = -Os
+
+# Output directories
+BIN = $(CHIP)_bin
+OBJ = $(CHIP)_obj
+
+# Output file basename
+OUTPUT_BIN = $(BIN)/cmsis_example_$(BOARD)_$(CHIP)
+
+# GCC toolchain provider
+GCC_TOOLCHAIN=gcc_arm
+
+#-------------------------------------------------------------------------------
+#		Tools
+#-------------------------------------------------------------------------------
+
+# Toolchain prefix when cross-compiling
+CROSS_COMPILE = arm-none-eabi-
+
+CMSIS_ROOT=../../..
+CMSIS_PATH=$(CMSIS_ROOT)/CMSIS/Include
+SAM_PATH=$(CMSIS_ROOT)/Device/ATMEL
+DEVICE_PATH=$(SAM_PATH)/$(SERIES)/source
+
+LIBS = -Wl,--start-group -lgcc -lc -Wl,--end-group
+
+LIB_PATH+=-L=/lib/thumb2
+LIB_PATH+=-L"$(realpath $(DEVICE_PATH)/$(GCC_TOOLCHAIN))"
+
+# Compilation tools
+CC = $(CROSS_COMPILE)gcc
+LD = $(CROSS_COMPILE)ld
+SIZE = $(CROSS_COMPILE)size
+STRIP = $(CROSS_COMPILE)strip
+OBJCOPY = $(CROSS_COMPILE)objcopy
+GDB = $(CROSS_COMPILE)gdb
+NM = $(CROSS_COMPILE)nm
+RM = rm
+
+# Flags
+INCLUDES := -I"$(CMSIS_PATH)"
+INCLUDES += -I"$(SAM_PATH)"
+INCLUDES += -I"$(SAM_PATH)/$(SERIES)/include"
+
+CFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
+CFLAGS += -Werror-implicit-function-declaration -Wmain -Wparentheses
+CFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CFLAGS += -Wshadow -Wpointer-arith -Wbad-function-cast -Wwrite-strings
+CFLAGS += -Wsign-compare -Waggregate-return -Wstrict-prototypes
+CFLAGS += -Wmissing-prototypes -Wmissing-declarations
+CFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CFLAGS += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long
+CFLAGS += -Wunreachable-code
+CFLAGS += -Wcast-align
+#CFLAGS += -Wmissing-noreturn
+#CFLAGS += -Wconversion
+
+# To reduce application size use only integer printf function.
+CFLAGS += -Dprintf=iprintf
+
+# -mlong-calls  -Wall
+CFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -ffunction-sections
+CFLAGS += -g $(OPTIMIZATION) $(INCLUDES) -D__$(CHIP)__ -DBOARD=$(BOARD)
+ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -g $(OPTIMIZATION) $(INCLUDES) -D__$(CHIP)__ -D__ASSEMBLY__
+LDFLAGS= -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols
+#LD_OPTIONAL=-Wl,--print-gc-sections -Wl,--stats
+
+#-------------------------------------------------------------------------------
+#		Files
+#-------------------------------------------------------------------------------
+
+# Directories where source files can be found
+
+VPATH += ..
+VPATH += $(DEVICE_PATH)
+VPATH += $(DEVICE_PATH)/$(GCC_TOOLCHAIN)
+
+# Objects built from C source files
+C_OBJECTS += main.o
+C_OBJECTS += startup_$(SERIES).o
+C_OBJECTS += system_$(SERIES).o
+
+# Append OBJ and BIN directories to output filename
+OUTPUT := $(BIN)/$(OUTPUT_BIN)
+
+#-------------------------------------------------------------------------------
+#		Rules
+#-------------------------------------------------------------------------------
+
+all: $(BIN) $(OBJ) $(MEMORIES)
+
+$(BIN) $(OBJ):
+	-@mkdir $@
+
+define RULES
+C_OBJECTS_$(1) = $(addprefix $(OBJ)/$(1)_, $(C_OBJECTS))
+ASM_OBJECTS_$(1) = $(addprefix $(OBJ)/$(1)_, $(ASM_OBJECTS))
+
+$(1): $$(ASM_OBJECTS_$(1)) $$(C_OBJECTS_$(1))
+	$(CC) $(LIB_PATH) $(LDFLAGS) $(LD_OPTIONAL) -T"$(realpath $(DEVICE_PATH)/$(GCC_TOOLCHAIN)/$(CHIP)_$$@.ld)" -Wl,-Map,"$(OUTPUT_BIN)_$$@.map" -o "$(OUTPUT_BIN)_$$@.elf" $$^ $(LIBS)
+	@$(NM) "$(OUTPUT_BIN)_$$@.elf" >"$(OUTPUT_BIN)_$$@.elf.txt"
+	@$(OBJCOPY) -O binary "$(OUTPUT_BIN)_$$@.elf" "$(OUTPUT_BIN)_$$@.bin"
+	@$(SIZE) $$^ "$(OUTPUT_BIN)_$$@.elf"
+
+$$(C_OBJECTS_$(1)): $(OBJ)/$(1)_%.o: %.c Makefile $(OBJ) $(BIN)
+	@$(CC) $(CFLAGS) -D$(1) -c -o $$@ $$<
+
+$$(ASM_OBJECTS_$(1)): $(OBJ)/$(1)_%.o: %.S Makefile $(OBJ) $(BIN)
+	@$(CC) $(ASFLAGS) -D$(1) -c -o $$@ $$<
+
+debug_$(1): $(1)
+	$(GDB) -x "$(CHIP)_$(1).gdb" -ex "reset" -readnow -se "$(OUTPUT_BIN)_$(1).elf"
+endef
+
+$(foreach MEMORY, $(MEMORIES), $(eval $(call RULES,$(MEMORY))))
+
+clean:
+	-$(RM) -fR $(OBJ) $(BIN)
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/coreutils-5.3.0-GnuWin32.README b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/coreutils-5.3.0-GnuWin32.README
new file mode 100644
index 0000000..cd2b84e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/coreutils-5.3.0-GnuWin32.README
@@ -0,0 +1,151 @@
+* CoreUtils-5.3.0 for Windows *
+===============================
+
+What is it?
+-----------
+CoreUtils: collection of basic file, shell and text manipulation utilities
+
+Description
+-----------
+The GNU Core Utilities are the basic file, shell and text manipulation utilities
+of the GNU operating system. These are the core utilities which are expected to
+exist on every operating system. 
+
+File utilities:
+
+- chgrp: Changes file group ownership. 
+- chown: Changes file ownership. 
+- chmod: Changes file permissions. 
+- cp: Copies files. 
+- dd: Copies and converts a file. 
+- df: Shows disk free space on filesystems. 
+- dir: Gives a brief directory listing. 
+- dircolors: Setup program for the color output of GNU ls. 
+- du: Shows disk usage on filesystems. 
+- install: Copies file and sets its permissions. 
+- ln: Creates file links. 
+- ls: Lists directory contents. 
+- mkdir: Creates directories. 
+- mkfifo: Creates FIFOs (named pipes). 
+- mknod: Creates special files. 
+- mv: Moves files. 
+- rm: Removes (deletes) files. 
+- rmdir: Removes empty directories. 
+- shred: Destroy data in files. 
+- sync: Synchronizes filesystem buffers and disk. 
+- touch: Changes file timestamps. 
+- vdir: Long directory listing.
+
+
+Text utilities:
+
+- cat: concatenates and prints files on the standard output
+- cksum: checksum and count the bytes in a file
+- comm: compares two sorted files line by line
+- csplit: splits a file into sections determined by context lines
+- cut: remove sections from each line of files
+- expand: convert tabs to spaces
+- fmt: simple optimal text formatter
+- fold: wrap each input line to fit in specified width
+- head: output the first part of files
+- join: join lines of two files on a common field
+- md5sum: compute and check MD5 messsage digest
+- nl: number lines of files
+- od: dump files in octal and other formats
+- paste: merge lines of files
+- ptx: produce a permuted index of file contents
+- pr: convert text files for printing
+- shasum: compute and check SHA1 message digest
+- sort: sort lines of text files
+- split: split a file into pieces
+- sum: checksum and count the blocks in a file
+- tac: concatenates and prints files in reverse
+- tail: outputs the last part of files
+- tr: translates or deletes characters
+- tsort: perform topological sort
+- unexpand: convert spaces to tabs
+- uniq: remove duplicate lines from a sorted file
+- wc: prints the number of bytes, words, and lines in files
+
+
+Shell utilities:
+
+- [ - Check file types and compare values 
+- basename - Removes the path prefix from a given pathname. 
+- chroot - Changes the root directory. 
+- date - Prints/sets the system date and time. 
+- dirname - Removes the last level or filename from a given pathname. 
+- echo - Prints a line of text. 
+- env - Displays/modifies the environment. 
+- expr - Evaluates expressions. 
+- factor - Prints prime factors. 
+- false - Returns an unsuccessful exit status. 
+- groups - Print the groups that the user is a member of. 
+- hostid - Print the numeric identifier for the current host 
+- hostname - Print or set the machine name. 
+- id - Print real/effective uid/gid. 
+- logname - Print current login name. 
+- nice - Modify scheduling priority. 
+- nohup - Allows a command to continue running after logging out. 
+- pathchk - Check file name portability. 
+- pinky - Lightweight finger 
+- printenv - Prints environment variables. 
+- printf - Formats and prints data. 
+- pwd - Print the current working directory. 
+- seq - Print numeric sequences. 
+- sleep - Suspends execution for a specified time. 
+- stty - Print/change terminal settings. 
+- su - Allows you to adopt the id of another user or superuser. 
+- tee - Sends output to multiple files. 
+- test - Evaluates an expression. 
+- true - Returns a successful exit status. 
+- tty - Print terminal name. 
+- uname - Print system information. 
+- users - Print current user names. 
+- who - Print a list of all users currently logged in. 
+- whoami - Print effective user id. 
+- yes - Print a string repeatedly. 
+	 
+Homepage
+--------
+http://www.gnu.org/software/coreutils
+	 
+System
+------
+- MS-Windows 95 / 98 / ME / NT / 2000 / XP with msvcrt.dll
+- if msvcrt.dll is not in your Windows/System folder, get it from
+  Microsoft 
+  or by installing Internet Explorer 4.0 or higher
+   
+- libintl-2  
+- libiconv-2  
+
+Notes
+-----
+- Bugs and questions on this MS-Windows port: gnuwin32@users.sourceforge.net
+
+Package Availability
+--------------------
+- in: http://gnuwin32.sourceforge.net
+Installation
+------------
+The MS-Windows version of ln implements soft links as MS-Windows
+shortcuts. If necessary, it adds the extension .lnk
+Hard links are implemented as copies on MS-Windows-95 / 98 / ME,
+and as hard linls on MS-Windows-NT / 2000 / XP.
+
+Sources
+-------
+- coreutils-5.3.0-src.zip
+
+Compilation
+-----------
+The package has been compiled with GNU auto-tools, GNU make, and Mingw
+(GCC for MS-Windows). Any differences from the original sources are given
+in coreutils-5.3.0-GnuWin32.diffs in coreutils-5.3.0-src.zip. Libraries needed
+for compilation can be found at the lines starting with 'LIBS = ' in the
+Makefiles. Usually, these are standard libraries provided with Mingw, or
+libraries from the package itself; 'gw32c' refers to the libgw32c package,
+which provides MS-Windows substitutes or stubs for functions normally found in
+Unix. For more information, see: http://gnuwin32.sourceforge.net/compile.html
+and http://gnuwin32.sourceforge.net/packages/libgw32c.htm.
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/libiconv2.dll b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/libiconv2.dll
new file mode 100644
index 0000000..747073f
Binary files /dev/null and b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/libiconv2.dll differ
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/libintl3.dll b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/libintl3.dll
new file mode 100644
index 0000000..4f309be
Binary files /dev/null and b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/libintl3.dll differ
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/log.txt b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/log.txt
new file mode 100644
index 0000000..a2c2c8f
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/log.txt
@@ -0,0 +1,845 @@
+Defining cmsis_example_SAM3N00A_build and cmsis_example_SAM3N00A_clean
+Defining cmsis_example_SAM3N00B_build and cmsis_example_SAM3N00B_clean
+Defining cmsis_example_SAM3N0A_build and cmsis_example_SAM3N0A_clean
+Defining cmsis_example_SAM3N0B_build and cmsis_example_SAM3N0B_clean
+Defining cmsis_example_SAM3N0C_build and cmsis_example_SAM3N0C_clean
+Defining cmsis_example_SAM3N1A_build and cmsis_example_SAM3N1A_clean
+Defining cmsis_example_SAM3N1B_build and cmsis_example_SAM3N1B_clean
+Defining cmsis_example_SAM3N1C_build and cmsis_example_SAM3N1C_clean
+Defining cmsis_example_SAM3N2A_build and cmsis_example_SAM3N2A_clean
+Defining cmsis_example_SAM3N2B_build and cmsis_example_SAM3N2B_clean
+Defining cmsis_example_SAM3N2C_build and cmsis_example_SAM3N2C_clean
+Defining cmsis_example_SAM3N4A_build and cmsis_example_SAM3N4A_clean
+Defining cmsis_example_SAM3N4B_build and cmsis_example_SAM3N4B_clean
+Defining cmsis_example_SAM3N4C_build and cmsis_example_SAM3N4C_clean
+Defining cmsis_example_SAM3S1A_build and cmsis_example_SAM3S1A_clean
+Defining cmsis_example_SAM3S1B_build and cmsis_example_SAM3S1B_clean
+Defining cmsis_example_SAM3S1C_build and cmsis_example_SAM3S1C_clean
+Defining cmsis_example_SAM3S2A_build and cmsis_example_SAM3S2A_clean
+Defining cmsis_example_SAM3S2B_build and cmsis_example_SAM3S2B_clean
+Defining cmsis_example_SAM3S2C_build and cmsis_example_SAM3S2C_clean
+Defining cmsis_example_SAM3S4A_build and cmsis_example_SAM3S4A_clean
+Defining cmsis_example_SAM3S4B_build and cmsis_example_SAM3S4B_clean
+Defining cmsis_example_SAM3S4C_build and cmsis_example_SAM3S4C_clean
+Defining cmsis_example_SAM3S8B_build and cmsis_example_SAM3S8B_clean
+Defining cmsis_example_SAM3S8C_build and cmsis_example_SAM3S8C_clean
+Defining cmsis_example_SAM3SD8B_build and cmsis_example_SAM3SD8B_clean
+Defining cmsis_example_SAM3SD8C_build and cmsis_example_SAM3SD8C_clean
+Defining cmsis_example_SAM3U1C_build and cmsis_example_SAM3U1C_clean
+Defining cmsis_example_SAM3U1E_build and cmsis_example_SAM3U1E_clean
+Defining cmsis_example_SAM3U2C_build and cmsis_example_SAM3U2C_clean
+Defining cmsis_example_SAM3U2E_build and cmsis_example_SAM3U2E_clean
+Defining cmsis_example_SAM3U4C_build and cmsis_example_SAM3U4C_clean
+Defining cmsis_example_SAM3U4E_build and cmsis_example_SAM3U4E_clean
+Defining cmsis_example_SAM3A4C_build and cmsis_example_SAM3A4C_clean
+Defining cmsis_example_SAM3A8C_build and cmsis_example_SAM3A8C_clean
+Defining cmsis_example_SAM3X4C_build and cmsis_example_SAM3X4C_clean
+Defining cmsis_example_SAM3X4E_build and cmsis_example_SAM3X4E_clean
+Defining cmsis_example_SAM3X8C_build and cmsis_example_SAM3X8C_clean
+Defining cmsis_example_SAM3X8E_build and cmsis_example_SAM3X8E_clean
+Defining cmsis_example_SAM3X8H_build and cmsis_example_SAM3X8H_clean
+Defining cmsis_example_SAM4S8B_build and cmsis_example_SAM4S8B_clean
+Defining cmsis_example_SAM4S8C_build and cmsis_example_SAM4S8C_clean
+Defining cmsis_example_SAM4S16B_build and cmsis_example_SAM4S16B_clean
+Defining cmsis_example_SAM4S16C_build and cmsis_example_SAM4S16C_clean
+Number of devices to be tested 44 /  44
+--- 
+--- 
+--- Making SAM3N00A
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N00A_sram.ld" -Wl,-Map,"SAM3N00A_bin/cmsis_example_SAM3N_EK_SAM3N00A_sram.map" -o "SAM3N00A_bin/cmsis_example_SAM3N_EK_SAM3N00A_sram.elf" SAM3N00A_obj/sram_main.o SAM3N00A_obj/sram_startup_sam3n.o SAM3N00A_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N00A_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N00A_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N00A_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N00A_bin/cmsis_example_SAM3N_EK_SAM3N00A_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N00A_flash.ld" -Wl,-Map,"SAM3N00A_bin/cmsis_example_SAM3N_EK_SAM3N00A_flash.map" -o "SAM3N00A_bin/cmsis_example_SAM3N_EK_SAM3N00A_flash.elf" SAM3N00A_obj/flash_main.o SAM3N00A_obj/flash_startup_sam3n.o SAM3N00A_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N00A_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N00A_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N00A_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N00A_bin/cmsis_example_SAM3N_EK_SAM3N00A_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3N00B
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N00B_sram.ld" -Wl,-Map,"SAM3N00B_bin/cmsis_example_SAM3N_EK_SAM3N00B_sram.map" -o "SAM3N00B_bin/cmsis_example_SAM3N_EK_SAM3N00B_sram.elf" SAM3N00B_obj/sram_main.o SAM3N00B_obj/sram_startup_sam3n.o SAM3N00B_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N00B_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N00B_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N00B_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N00B_bin/cmsis_example_SAM3N_EK_SAM3N00B_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N00B_flash.ld" -Wl,-Map,"SAM3N00B_bin/cmsis_example_SAM3N_EK_SAM3N00B_flash.map" -o "SAM3N00B_bin/cmsis_example_SAM3N_EK_SAM3N00B_flash.elf" SAM3N00B_obj/flash_main.o SAM3N00B_obj/flash_startup_sam3n.o SAM3N00B_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N00B_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N00B_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N00B_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N00B_bin/cmsis_example_SAM3N_EK_SAM3N00B_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3N0A
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N0A_sram.ld" -Wl,-Map,"SAM3N0A_bin/cmsis_example_SAM3N_EK_SAM3N0A_sram.map" -o "SAM3N0A_bin/cmsis_example_SAM3N_EK_SAM3N0A_sram.elf" SAM3N0A_obj/sram_main.o SAM3N0A_obj/sram_startup_sam3n.o SAM3N0A_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N0A_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N0A_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N0A_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N0A_bin/cmsis_example_SAM3N_EK_SAM3N0A_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N0A_flash.ld" -Wl,-Map,"SAM3N0A_bin/cmsis_example_SAM3N_EK_SAM3N0A_flash.map" -o "SAM3N0A_bin/cmsis_example_SAM3N_EK_SAM3N0A_flash.elf" SAM3N0A_obj/flash_main.o SAM3N0A_obj/flash_startup_sam3n.o SAM3N0A_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N0A_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N0A_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N0A_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N0A_bin/cmsis_example_SAM3N_EK_SAM3N0A_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3N0B
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N0B_sram.ld" -Wl,-Map,"SAM3N0B_bin/cmsis_example_SAM3N_EK_SAM3N0B_sram.map" -o "SAM3N0B_bin/cmsis_example_SAM3N_EK_SAM3N0B_sram.elf" SAM3N0B_obj/sram_main.o SAM3N0B_obj/sram_startup_sam3n.o SAM3N0B_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N0B_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N0B_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N0B_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N0B_bin/cmsis_example_SAM3N_EK_SAM3N0B_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N0B_flash.ld" -Wl,-Map,"SAM3N0B_bin/cmsis_example_SAM3N_EK_SAM3N0B_flash.map" -o "SAM3N0B_bin/cmsis_example_SAM3N_EK_SAM3N0B_flash.elf" SAM3N0B_obj/flash_main.o SAM3N0B_obj/flash_startup_sam3n.o SAM3N0B_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N0B_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N0B_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N0B_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N0B_bin/cmsis_example_SAM3N_EK_SAM3N0B_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3N0C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N0C_sram.ld" -Wl,-Map,"SAM3N0C_bin/cmsis_example_SAM3N_EK_SAM3N0C_sram.map" -o "SAM3N0C_bin/cmsis_example_SAM3N_EK_SAM3N0C_sram.elf" SAM3N0C_obj/sram_main.o SAM3N0C_obj/sram_startup_sam3n.o SAM3N0C_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N0C_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N0C_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N0C_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N0C_bin/cmsis_example_SAM3N_EK_SAM3N0C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N0C_flash.ld" -Wl,-Map,"SAM3N0C_bin/cmsis_example_SAM3N_EK_SAM3N0C_flash.map" -o "SAM3N0C_bin/cmsis_example_SAM3N_EK_SAM3N0C_flash.elf" SAM3N0C_obj/flash_main.o SAM3N0C_obj/flash_startup_sam3n.o SAM3N0C_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N0C_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N0C_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N0C_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N0C_bin/cmsis_example_SAM3N_EK_SAM3N0C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3N1A
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N1A_sram.ld" -Wl,-Map,"SAM3N1A_bin/cmsis_example_SAM3N_EK_SAM3N1A_sram.map" -o "SAM3N1A_bin/cmsis_example_SAM3N_EK_SAM3N1A_sram.elf" SAM3N1A_obj/sram_main.o SAM3N1A_obj/sram_startup_sam3n.o SAM3N1A_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N1A_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N1A_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N1A_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N1A_bin/cmsis_example_SAM3N_EK_SAM3N1A_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N1A_flash.ld" -Wl,-Map,"SAM3N1A_bin/cmsis_example_SAM3N_EK_SAM3N1A_flash.map" -o "SAM3N1A_bin/cmsis_example_SAM3N_EK_SAM3N1A_flash.elf" SAM3N1A_obj/flash_main.o SAM3N1A_obj/flash_startup_sam3n.o SAM3N1A_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N1A_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N1A_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N1A_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N1A_bin/cmsis_example_SAM3N_EK_SAM3N1A_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3N1B
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N1B_sram.ld" -Wl,-Map,"SAM3N1B_bin/cmsis_example_SAM3N_EK_SAM3N1B_sram.map" -o "SAM3N1B_bin/cmsis_example_SAM3N_EK_SAM3N1B_sram.elf" SAM3N1B_obj/sram_main.o SAM3N1B_obj/sram_startup_sam3n.o SAM3N1B_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N1B_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N1B_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N1B_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N1B_bin/cmsis_example_SAM3N_EK_SAM3N1B_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N1B_flash.ld" -Wl,-Map,"SAM3N1B_bin/cmsis_example_SAM3N_EK_SAM3N1B_flash.map" -o "SAM3N1B_bin/cmsis_example_SAM3N_EK_SAM3N1B_flash.elf" SAM3N1B_obj/flash_main.o SAM3N1B_obj/flash_startup_sam3n.o SAM3N1B_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N1B_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N1B_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N1B_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N1B_bin/cmsis_example_SAM3N_EK_SAM3N1B_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3N1C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N1C_sram.ld" -Wl,-Map,"SAM3N1C_bin/cmsis_example_SAM3N_EK_SAM3N1C_sram.map" -o "SAM3N1C_bin/cmsis_example_SAM3N_EK_SAM3N1C_sram.elf" SAM3N1C_obj/sram_main.o SAM3N1C_obj/sram_startup_sam3n.o SAM3N1C_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N1C_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N1C_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N1C_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N1C_bin/cmsis_example_SAM3N_EK_SAM3N1C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N1C_flash.ld" -Wl,-Map,"SAM3N1C_bin/cmsis_example_SAM3N_EK_SAM3N1C_flash.map" -o "SAM3N1C_bin/cmsis_example_SAM3N_EK_SAM3N1C_flash.elf" SAM3N1C_obj/flash_main.o SAM3N1C_obj/flash_startup_sam3n.o SAM3N1C_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N1C_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N1C_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N1C_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N1C_bin/cmsis_example_SAM3N_EK_SAM3N1C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3N2A
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N2A_sram.ld" -Wl,-Map,"SAM3N2A_bin/cmsis_example_SAM3N_EK_SAM3N2A_sram.map" -o "SAM3N2A_bin/cmsis_example_SAM3N_EK_SAM3N2A_sram.elf" SAM3N2A_obj/sram_main.o SAM3N2A_obj/sram_startup_sam3n.o SAM3N2A_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N2A_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N2A_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N2A_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N2A_bin/cmsis_example_SAM3N_EK_SAM3N2A_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N2A_flash.ld" -Wl,-Map,"SAM3N2A_bin/cmsis_example_SAM3N_EK_SAM3N2A_flash.map" -o "SAM3N2A_bin/cmsis_example_SAM3N_EK_SAM3N2A_flash.elf" SAM3N2A_obj/flash_main.o SAM3N2A_obj/flash_startup_sam3n.o SAM3N2A_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N2A_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N2A_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N2A_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N2A_bin/cmsis_example_SAM3N_EK_SAM3N2A_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3N2B
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N2B_sram.ld" -Wl,-Map,"SAM3N2B_bin/cmsis_example_SAM3N_EK_SAM3N2B_sram.map" -o "SAM3N2B_bin/cmsis_example_SAM3N_EK_SAM3N2B_sram.elf" SAM3N2B_obj/sram_main.o SAM3N2B_obj/sram_startup_sam3n.o SAM3N2B_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N2B_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N2B_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N2B_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N2B_bin/cmsis_example_SAM3N_EK_SAM3N2B_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N2B_flash.ld" -Wl,-Map,"SAM3N2B_bin/cmsis_example_SAM3N_EK_SAM3N2B_flash.map" -o "SAM3N2B_bin/cmsis_example_SAM3N_EK_SAM3N2B_flash.elf" SAM3N2B_obj/flash_main.o SAM3N2B_obj/flash_startup_sam3n.o SAM3N2B_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N2B_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N2B_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N2B_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N2B_bin/cmsis_example_SAM3N_EK_SAM3N2B_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3N2C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N2C_sram.ld" -Wl,-Map,"SAM3N2C_bin/cmsis_example_SAM3N_EK_SAM3N2C_sram.map" -o "SAM3N2C_bin/cmsis_example_SAM3N_EK_SAM3N2C_sram.elf" SAM3N2C_obj/sram_main.o SAM3N2C_obj/sram_startup_sam3n.o SAM3N2C_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N2C_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N2C_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N2C_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N2C_bin/cmsis_example_SAM3N_EK_SAM3N2C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N2C_flash.ld" -Wl,-Map,"SAM3N2C_bin/cmsis_example_SAM3N_EK_SAM3N2C_flash.map" -o "SAM3N2C_bin/cmsis_example_SAM3N_EK_SAM3N2C_flash.elf" SAM3N2C_obj/flash_main.o SAM3N2C_obj/flash_startup_sam3n.o SAM3N2C_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N2C_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N2C_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N2C_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N2C_bin/cmsis_example_SAM3N_EK_SAM3N2C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3N4A
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N4A_sram.ld" -Wl,-Map,"SAM3N4A_bin/cmsis_example_SAM3N_EK_SAM3N4A_sram.map" -o "SAM3N4A_bin/cmsis_example_SAM3N_EK_SAM3N4A_sram.elf" SAM3N4A_obj/sram_main.o SAM3N4A_obj/sram_startup_sam3n.o SAM3N4A_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N4A_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N4A_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N4A_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N4A_bin/cmsis_example_SAM3N_EK_SAM3N4A_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N4A_flash.ld" -Wl,-Map,"SAM3N4A_bin/cmsis_example_SAM3N_EK_SAM3N4A_flash.map" -o "SAM3N4A_bin/cmsis_example_SAM3N_EK_SAM3N4A_flash.elf" SAM3N4A_obj/flash_main.o SAM3N4A_obj/flash_startup_sam3n.o SAM3N4A_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N4A_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N4A_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N4A_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N4A_bin/cmsis_example_SAM3N_EK_SAM3N4A_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3N4B
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N4B_sram.ld" -Wl,-Map,"SAM3N4B_bin/cmsis_example_SAM3N_EK_SAM3N4B_sram.map" -o "SAM3N4B_bin/cmsis_example_SAM3N_EK_SAM3N4B_sram.elf" SAM3N4B_obj/sram_main.o SAM3N4B_obj/sram_startup_sam3n.o SAM3N4B_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N4B_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N4B_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N4B_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N4B_bin/cmsis_example_SAM3N_EK_SAM3N4B_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N4B_flash.ld" -Wl,-Map,"SAM3N4B_bin/cmsis_example_SAM3N_EK_SAM3N4B_flash.map" -o "SAM3N4B_bin/cmsis_example_SAM3N_EK_SAM3N4B_flash.elf" SAM3N4B_obj/flash_main.o SAM3N4B_obj/flash_startup_sam3n.o SAM3N4B_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N4B_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N4B_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N4B_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N4B_bin/cmsis_example_SAM3N_EK_SAM3N4B_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3N4C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N4C_sram.ld" -Wl,-Map,"SAM3N4C_bin/cmsis_example_SAM3N_EK_SAM3N4C_sram.map" -o "SAM3N4C_bin/cmsis_example_SAM3N_EK_SAM3N4C_sram.elf" SAM3N4C_obj/sram_main.o SAM3N4C_obj/sram_startup_sam3n.o SAM3N4C_obj/sram_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N4C_obj/sram_main.o
+    310	      0	      0	    310	    136	SAM3N4C_obj/sram_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N4C_obj/sram_system_sam3n.o
+    796	      4	    544	   1344	    540	SAM3N4C_bin/cmsis_example_SAM3N_EK_SAM3N4C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3n/source/gcc_atmel/SAM3N4C_flash.ld" -Wl,-Map,"SAM3N4C_bin/cmsis_example_SAM3N_EK_SAM3N4C_flash.map" -o "SAM3N4C_bin/cmsis_example_SAM3N_EK_SAM3N4C_flash.elf" SAM3N4C_obj/flash_main.o SAM3N4C_obj/flash_startup_sam3n.o SAM3N4C_obj/flash_system_sam3n.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3N4C_obj/flash_main.o
+    310	      0	      0	    310	    136	SAM3N4C_obj/flash_startup_sam3n.o
+    400	      4	      0	    404	    194	SAM3N4C_obj/flash_system_sam3n.o
+    796	      4	    548	   1348	    544	SAM3N4C_bin/cmsis_example_SAM3N_EK_SAM3N4C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3S1A
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S1A_sram.ld" -Wl,-Map,"SAM3S1A_bin/cmsis_example_SAM3S_EK_SAM3S1A_sram.map" -o "SAM3S1A_bin/cmsis_example_SAM3S_EK_SAM3S1A_sram.elf" SAM3S1A_obj/sram_main.o SAM3S1A_obj/sram_startup_sam3s.o SAM3S1A_obj/sram_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S1A_obj/sram_main.o
+    322	      0	      0	    322	    142	SAM3S1A_obj/sram_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S1A_obj/sram_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S1A_bin/cmsis_example_SAM3S_EK_SAM3S1A_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S1A_flash.ld" -Wl,-Map,"SAM3S1A_bin/cmsis_example_SAM3S_EK_SAM3S1A_flash.map" -o "SAM3S1A_bin/cmsis_example_SAM3S_EK_SAM3S1A_flash.elf" SAM3S1A_obj/flash_main.o SAM3S1A_obj/flash_startup_sam3s.o SAM3S1A_obj/flash_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S1A_obj/flash_main.o
+    322	      0	      0	    322	    142	SAM3S1A_obj/flash_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S1A_obj/flash_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S1A_bin/cmsis_example_SAM3S_EK_SAM3S1A_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3S1B
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S1B_sram.ld" -Wl,-Map,"SAM3S1B_bin/cmsis_example_SAM3S_EK_SAM3S1B_sram.map" -o "SAM3S1B_bin/cmsis_example_SAM3S_EK_SAM3S1B_sram.elf" SAM3S1B_obj/sram_main.o SAM3S1B_obj/sram_startup_sam3s.o SAM3S1B_obj/sram_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S1B_obj/sram_main.o
+    322	      0	      0	    322	    142	SAM3S1B_obj/sram_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S1B_obj/sram_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S1B_bin/cmsis_example_SAM3S_EK_SAM3S1B_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S1B_flash.ld" -Wl,-Map,"SAM3S1B_bin/cmsis_example_SAM3S_EK_SAM3S1B_flash.map" -o "SAM3S1B_bin/cmsis_example_SAM3S_EK_SAM3S1B_flash.elf" SAM3S1B_obj/flash_main.o SAM3S1B_obj/flash_startup_sam3s.o SAM3S1B_obj/flash_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S1B_obj/flash_main.o
+    322	      0	      0	    322	    142	SAM3S1B_obj/flash_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S1B_obj/flash_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S1B_bin/cmsis_example_SAM3S_EK_SAM3S1B_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3S1C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S1C_sram.ld" -Wl,-Map,"SAM3S1C_bin/cmsis_example_SAM3S_EK_SAM3S1C_sram.map" -o "SAM3S1C_bin/cmsis_example_SAM3S_EK_SAM3S1C_sram.elf" SAM3S1C_obj/sram_main.o SAM3S1C_obj/sram_startup_sam3s.o SAM3S1C_obj/sram_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S1C_obj/sram_main.o
+    322	      0	      0	    322	    142	SAM3S1C_obj/sram_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S1C_obj/sram_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S1C_bin/cmsis_example_SAM3S_EK_SAM3S1C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S1C_flash.ld" -Wl,-Map,"SAM3S1C_bin/cmsis_example_SAM3S_EK_SAM3S1C_flash.map" -o "SAM3S1C_bin/cmsis_example_SAM3S_EK_SAM3S1C_flash.elf" SAM3S1C_obj/flash_main.o SAM3S1C_obj/flash_startup_sam3s.o SAM3S1C_obj/flash_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S1C_obj/flash_main.o
+    322	      0	      0	    322	    142	SAM3S1C_obj/flash_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S1C_obj/flash_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S1C_bin/cmsis_example_SAM3S_EK_SAM3S1C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3S2A
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S2A_sram.ld" -Wl,-Map,"SAM3S2A_bin/cmsis_example_SAM3S_EK_SAM3S2A_sram.map" -o "SAM3S2A_bin/cmsis_example_SAM3S_EK_SAM3S2A_sram.elf" SAM3S2A_obj/sram_main.o SAM3S2A_obj/sram_startup_sam3s.o SAM3S2A_obj/sram_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S2A_obj/sram_main.o
+    322	      0	      0	    322	    142	SAM3S2A_obj/sram_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S2A_obj/sram_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S2A_bin/cmsis_example_SAM3S_EK_SAM3S2A_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S2A_flash.ld" -Wl,-Map,"SAM3S2A_bin/cmsis_example_SAM3S_EK_SAM3S2A_flash.map" -o "SAM3S2A_bin/cmsis_example_SAM3S_EK_SAM3S2A_flash.elf" SAM3S2A_obj/flash_main.o SAM3S2A_obj/flash_startup_sam3s.o SAM3S2A_obj/flash_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S2A_obj/flash_main.o
+    322	      0	      0	    322	    142	SAM3S2A_obj/flash_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S2A_obj/flash_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S2A_bin/cmsis_example_SAM3S_EK_SAM3S2A_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3S2B
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S2B_sram.ld" -Wl,-Map,"SAM3S2B_bin/cmsis_example_SAM3S_EK_SAM3S2B_sram.map" -o "SAM3S2B_bin/cmsis_example_SAM3S_EK_SAM3S2B_sram.elf" SAM3S2B_obj/sram_main.o SAM3S2B_obj/sram_startup_sam3s.o SAM3S2B_obj/sram_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S2B_obj/sram_main.o
+    322	      0	      0	    322	    142	SAM3S2B_obj/sram_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S2B_obj/sram_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S2B_bin/cmsis_example_SAM3S_EK_SAM3S2B_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S2B_flash.ld" -Wl,-Map,"SAM3S2B_bin/cmsis_example_SAM3S_EK_SAM3S2B_flash.map" -o "SAM3S2B_bin/cmsis_example_SAM3S_EK_SAM3S2B_flash.elf" SAM3S2B_obj/flash_main.o SAM3S2B_obj/flash_startup_sam3s.o SAM3S2B_obj/flash_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S2B_obj/flash_main.o
+    322	      0	      0	    322	    142	SAM3S2B_obj/flash_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S2B_obj/flash_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S2B_bin/cmsis_example_SAM3S_EK_SAM3S2B_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3S2C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S2C_sram.ld" -Wl,-Map,"SAM3S2C_bin/cmsis_example_SAM3S_EK_SAM3S2C_sram.map" -o "SAM3S2C_bin/cmsis_example_SAM3S_EK_SAM3S2C_sram.elf" SAM3S2C_obj/sram_main.o SAM3S2C_obj/sram_startup_sam3s.o SAM3S2C_obj/sram_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S2C_obj/sram_main.o
+    322	      0	      0	    322	    142	SAM3S2C_obj/sram_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S2C_obj/sram_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S2C_bin/cmsis_example_SAM3S_EK_SAM3S2C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S2C_flash.ld" -Wl,-Map,"SAM3S2C_bin/cmsis_example_SAM3S_EK_SAM3S2C_flash.map" -o "SAM3S2C_bin/cmsis_example_SAM3S_EK_SAM3S2C_flash.elf" SAM3S2C_obj/flash_main.o SAM3S2C_obj/flash_startup_sam3s.o SAM3S2C_obj/flash_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S2C_obj/flash_main.o
+    322	      0	      0	    322	    142	SAM3S2C_obj/flash_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S2C_obj/flash_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S2C_bin/cmsis_example_SAM3S_EK_SAM3S2C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3S4A
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S4A_sram.ld" -Wl,-Map,"SAM3S4A_bin/cmsis_example_SAM3S_EK_SAM3S4A_sram.map" -o "SAM3S4A_bin/cmsis_example_SAM3S_EK_SAM3S4A_sram.elf" SAM3S4A_obj/sram_main.o SAM3S4A_obj/sram_startup_sam3s.o SAM3S4A_obj/sram_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S4A_obj/sram_main.o
+    322	      0	      0	    322	    142	SAM3S4A_obj/sram_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S4A_obj/sram_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S4A_bin/cmsis_example_SAM3S_EK_SAM3S4A_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S4A_flash.ld" -Wl,-Map,"SAM3S4A_bin/cmsis_example_SAM3S_EK_SAM3S4A_flash.map" -o "SAM3S4A_bin/cmsis_example_SAM3S_EK_SAM3S4A_flash.elf" SAM3S4A_obj/flash_main.o SAM3S4A_obj/flash_startup_sam3s.o SAM3S4A_obj/flash_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S4A_obj/flash_main.o
+    322	      0	      0	    322	    142	SAM3S4A_obj/flash_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S4A_obj/flash_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S4A_bin/cmsis_example_SAM3S_EK_SAM3S4A_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3S4B
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S4B_sram.ld" -Wl,-Map,"SAM3S4B_bin/cmsis_example_SAM3S_EK_SAM3S4B_sram.map" -o "SAM3S4B_bin/cmsis_example_SAM3S_EK_SAM3S4B_sram.elf" SAM3S4B_obj/sram_main.o SAM3S4B_obj/sram_startup_sam3s.o SAM3S4B_obj/sram_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S4B_obj/sram_main.o
+    322	      0	      0	    322	    142	SAM3S4B_obj/sram_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S4B_obj/sram_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S4B_bin/cmsis_example_SAM3S_EK_SAM3S4B_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S4B_flash.ld" -Wl,-Map,"SAM3S4B_bin/cmsis_example_SAM3S_EK_SAM3S4B_flash.map" -o "SAM3S4B_bin/cmsis_example_SAM3S_EK_SAM3S4B_flash.elf" SAM3S4B_obj/flash_main.o SAM3S4B_obj/flash_startup_sam3s.o SAM3S4B_obj/flash_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S4B_obj/flash_main.o
+    322	      0	      0	    322	    142	SAM3S4B_obj/flash_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S4B_obj/flash_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S4B_bin/cmsis_example_SAM3S_EK_SAM3S4B_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3S4C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S4C_sram.ld" -Wl,-Map,"SAM3S4C_bin/cmsis_example_SAM3S_EK_SAM3S4C_sram.map" -o "SAM3S4C_bin/cmsis_example_SAM3S_EK_SAM3S4C_sram.elf" SAM3S4C_obj/sram_main.o SAM3S4C_obj/sram_startup_sam3s.o SAM3S4C_obj/sram_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S4C_obj/sram_main.o
+    322	      0	      0	    322	    142	SAM3S4C_obj/sram_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S4C_obj/sram_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S4C_bin/cmsis_example_SAM3S_EK_SAM3S4C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3s/source/gcc_atmel/SAM3S4C_flash.ld" -Wl,-Map,"SAM3S4C_bin/cmsis_example_SAM3S_EK_SAM3S4C_flash.map" -o "SAM3S4C_bin/cmsis_example_SAM3S_EK_SAM3S4C_flash.elf" SAM3S4C_obj/flash_main.o SAM3S4C_obj/flash_startup_sam3s.o SAM3S4C_obj/flash_system_sam3s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S4C_obj/flash_main.o
+    322	      0	      0	    322	    142	SAM3S4C_obj/flash_startup_sam3s.o
+    412	      4	      0	    416	    1a0	SAM3S4C_obj/flash_system_sam3s.o
+    808	      4	    548	   1360	    550	SAM3S4C_bin/cmsis_example_SAM3S_EK_SAM3S4C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3S8B
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel/SAM3S8B_sram.ld" -Wl,-Map,"SAM3S8B_bin/cmsis_example_SAM3S_EK2_SAM3S8B_sram.map" -o "SAM3S8B_bin/cmsis_example_SAM3S_EK2_SAM3S8B_sram.elf" SAM3S8B_obj/sram_main.o SAM3S8B_obj/sram_startup_sam3sd8.o SAM3S8B_obj/sram_system_sam3sd8.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S8B_obj/sram_main.o
+    322	      0	      0	    322	    142	SAM3S8B_obj/sram_startup_sam3sd8.o
+    412	      4	      0	    416	    1a0	SAM3S8B_obj/sram_system_sam3sd8.o
+    808	      4	    548	   1360	    550	SAM3S8B_bin/cmsis_example_SAM3S_EK2_SAM3S8B_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel/SAM3S8B_flash.ld" -Wl,-Map,"SAM3S8B_bin/cmsis_example_SAM3S_EK2_SAM3S8B_flash.map" -o "SAM3S8B_bin/cmsis_example_SAM3S_EK2_SAM3S8B_flash.elf" SAM3S8B_obj/flash_main.o SAM3S8B_obj/flash_startup_sam3sd8.o SAM3S8B_obj/flash_system_sam3sd8.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S8B_obj/flash_main.o
+    322	      0	      0	    322	    142	SAM3S8B_obj/flash_startup_sam3sd8.o
+    412	      4	      0	    416	    1a0	SAM3S8B_obj/flash_system_sam3sd8.o
+    808	      4	    548	   1360	    550	SAM3S8B_bin/cmsis_example_SAM3S_EK2_SAM3S8B_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3S8C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel/SAM3S8C_sram.ld" -Wl,-Map,"SAM3S8C_bin/cmsis_example_SAM3S_EK2_SAM3S8C_sram.map" -o "SAM3S8C_bin/cmsis_example_SAM3S_EK2_SAM3S8C_sram.elf" SAM3S8C_obj/sram_main.o SAM3S8C_obj/sram_startup_sam3sd8.o SAM3S8C_obj/sram_system_sam3sd8.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S8C_obj/sram_main.o
+    322	      0	      0	    322	    142	SAM3S8C_obj/sram_startup_sam3sd8.o
+    412	      4	      0	    416	    1a0	SAM3S8C_obj/sram_system_sam3sd8.o
+    808	      4	    548	   1360	    550	SAM3S8C_bin/cmsis_example_SAM3S_EK2_SAM3S8C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel/SAM3S8C_flash.ld" -Wl,-Map,"SAM3S8C_bin/cmsis_example_SAM3S_EK2_SAM3S8C_flash.map" -o "SAM3S8C_bin/cmsis_example_SAM3S_EK2_SAM3S8C_flash.elf" SAM3S8C_obj/flash_main.o SAM3S8C_obj/flash_startup_sam3sd8.o SAM3S8C_obj/flash_system_sam3sd8.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3S8C_obj/flash_main.o
+    322	      0	      0	    322	    142	SAM3S8C_obj/flash_startup_sam3sd8.o
+    412	      4	      0	    416	    1a0	SAM3S8C_obj/flash_system_sam3sd8.o
+    808	      4	    548	   1360	    550	SAM3S8C_bin/cmsis_example_SAM3S_EK2_SAM3S8C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3SD8B
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel/SAM3SD8B_sram.ld" -Wl,-Map,"SAM3SD8B_bin/cmsis_example_SAM3S_EK2_SAM3SD8B_sram.map" -o "SAM3SD8B_bin/cmsis_example_SAM3S_EK2_SAM3SD8B_sram.elf" SAM3SD8B_obj/sram_main.o SAM3SD8B_obj/sram_startup_sam3sd8.o SAM3SD8B_obj/sram_system_sam3sd8.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3SD8B_obj/sram_main.o
+    322	      0	      0	    322	    142	SAM3SD8B_obj/sram_startup_sam3sd8.o
+    412	      4	      0	    416	    1a0	SAM3SD8B_obj/sram_system_sam3sd8.o
+    808	      4	    548	   1360	    550	SAM3SD8B_bin/cmsis_example_SAM3S_EK2_SAM3SD8B_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel/SAM3SD8B_flash.ld" -Wl,-Map,"SAM3SD8B_bin/cmsis_example_SAM3S_EK2_SAM3SD8B_flash.map" -o "SAM3SD8B_bin/cmsis_example_SAM3S_EK2_SAM3SD8B_flash.elf" SAM3SD8B_obj/flash_main.o SAM3SD8B_obj/flash_startup_sam3sd8.o SAM3SD8B_obj/flash_system_sam3sd8.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3SD8B_obj/flash_main.o
+    322	      0	      0	    322	    142	SAM3SD8B_obj/flash_startup_sam3sd8.o
+    412	      4	      0	    416	    1a0	SAM3SD8B_obj/flash_system_sam3sd8.o
+    808	      4	    548	   1360	    550	SAM3SD8B_bin/cmsis_example_SAM3S_EK2_SAM3SD8B_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3SD8C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel/SAM3SD8C_sram.ld" -Wl,-Map,"SAM3SD8C_bin/cmsis_example_SAM3S_EK2_SAM3SD8C_sram.map" -o "SAM3SD8C_bin/cmsis_example_SAM3S_EK2_SAM3SD8C_sram.elf" SAM3SD8C_obj/sram_main.o SAM3SD8C_obj/sram_startup_sam3sd8.o SAM3SD8C_obj/sram_system_sam3sd8.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3SD8C_obj/sram_main.o
+    322	      0	      0	    322	    142	SAM3SD8C_obj/sram_startup_sam3sd8.o
+    412	      4	      0	    416	    1a0	SAM3SD8C_obj/sram_system_sam3sd8.o
+    808	      4	    548	   1360	    550	SAM3SD8C_bin/cmsis_example_SAM3S_EK2_SAM3SD8C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3sd8/source/gcc_atmel/SAM3SD8C_flash.ld" -Wl,-Map,"SAM3SD8C_bin/cmsis_example_SAM3S_EK2_SAM3SD8C_flash.map" -o "SAM3SD8C_bin/cmsis_example_SAM3S_EK2_SAM3SD8C_flash.elf" SAM3SD8C_obj/flash_main.o SAM3SD8C_obj/flash_startup_sam3sd8.o SAM3SD8C_obj/flash_system_sam3sd8.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3SD8C_obj/flash_main.o
+    322	      0	      0	    322	    142	SAM3SD8C_obj/flash_startup_sam3sd8.o
+    412	      4	      0	    416	    1a0	SAM3SD8C_obj/flash_system_sam3sd8.o
+    808	      4	    548	   1360	    550	SAM3SD8C_bin/cmsis_example_SAM3S_EK2_SAM3SD8C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3U1C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel/SAM3U1C_sram.ld" -Wl,-Map,"SAM3U1C_bin/cmsis_example_SAM3U_EK_SAM3U1C_sram.map" -o "SAM3U1C_bin/cmsis_example_SAM3U_EK_SAM3U1C_sram.elf" SAM3U1C_obj/sram_main.o SAM3U1C_obj/sram_startup_sam3u.o SAM3U1C_obj/sram_system_sam3u.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3U1C_obj/sram_main.o
+    302	      0	      0	    302	    12e	SAM3U1C_obj/sram_startup_sam3u.o
+    436	      4	      0	    440	    1b8	SAM3U1C_obj/sram_system_sam3u.o
+    788	      4	    544	   1336	    538	SAM3U1C_bin/cmsis_example_SAM3U_EK_SAM3U1C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel/SAM3U1C_flash.ld" -Wl,-Map,"SAM3U1C_bin/cmsis_example_SAM3U_EK_SAM3U1C_flash.map" -o "SAM3U1C_bin/cmsis_example_SAM3U_EK_SAM3U1C_flash.elf" SAM3U1C_obj/flash_main.o SAM3U1C_obj/flash_startup_sam3u.o SAM3U1C_obj/flash_system_sam3u.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3U1C_obj/flash_main.o
+    302	      0	      0	    302	    12e	SAM3U1C_obj/flash_startup_sam3u.o
+    436	      4	      0	    440	    1b8	SAM3U1C_obj/flash_system_sam3u.o
+    788	      4	    548	   1340	    53c	SAM3U1C_bin/cmsis_example_SAM3U_EK_SAM3U1C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3U1E
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel/SAM3U1E_sram.ld" -Wl,-Map,"SAM3U1E_bin/cmsis_example_SAM3U_EK_SAM3U1E_sram.map" -o "SAM3U1E_bin/cmsis_example_SAM3U_EK_SAM3U1E_sram.elf" SAM3U1E_obj/sram_main.o SAM3U1E_obj/sram_startup_sam3u.o SAM3U1E_obj/sram_system_sam3u.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3U1E_obj/sram_main.o
+    302	      0	      0	    302	    12e	SAM3U1E_obj/sram_startup_sam3u.o
+    436	      4	      0	    440	    1b8	SAM3U1E_obj/sram_system_sam3u.o
+    788	      4	    544	   1336	    538	SAM3U1E_bin/cmsis_example_SAM3U_EK_SAM3U1E_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel/SAM3U1E_flash.ld" -Wl,-Map,"SAM3U1E_bin/cmsis_example_SAM3U_EK_SAM3U1E_flash.map" -o "SAM3U1E_bin/cmsis_example_SAM3U_EK_SAM3U1E_flash.elf" SAM3U1E_obj/flash_main.o SAM3U1E_obj/flash_startup_sam3u.o SAM3U1E_obj/flash_system_sam3u.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3U1E_obj/flash_main.o
+    302	      0	      0	    302	    12e	SAM3U1E_obj/flash_startup_sam3u.o
+    436	      4	      0	    440	    1b8	SAM3U1E_obj/flash_system_sam3u.o
+    788	      4	    548	   1340	    53c	SAM3U1E_bin/cmsis_example_SAM3U_EK_SAM3U1E_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3U2C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel/SAM3U2C_sram.ld" -Wl,-Map,"SAM3U2C_bin/cmsis_example_SAM3U_EK_SAM3U2C_sram.map" -o "SAM3U2C_bin/cmsis_example_SAM3U_EK_SAM3U2C_sram.elf" SAM3U2C_obj/sram_main.o SAM3U2C_obj/sram_startup_sam3u.o SAM3U2C_obj/sram_system_sam3u.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3U2C_obj/sram_main.o
+    302	      0	      0	    302	    12e	SAM3U2C_obj/sram_startup_sam3u.o
+    436	      4	      0	    440	    1b8	SAM3U2C_obj/sram_system_sam3u.o
+    788	      4	    544	   1336	    538	SAM3U2C_bin/cmsis_example_SAM3U_EK_SAM3U2C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel/SAM3U2C_flash.ld" -Wl,-Map,"SAM3U2C_bin/cmsis_example_SAM3U_EK_SAM3U2C_flash.map" -o "SAM3U2C_bin/cmsis_example_SAM3U_EK_SAM3U2C_flash.elf" SAM3U2C_obj/flash_main.o SAM3U2C_obj/flash_startup_sam3u.o SAM3U2C_obj/flash_system_sam3u.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3U2C_obj/flash_main.o
+    302	      0	      0	    302	    12e	SAM3U2C_obj/flash_startup_sam3u.o
+    436	      4	      0	    440	    1b8	SAM3U2C_obj/flash_system_sam3u.o
+    788	      4	    548	   1340	    53c	SAM3U2C_bin/cmsis_example_SAM3U_EK_SAM3U2C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3U2E
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel/SAM3U2E_sram.ld" -Wl,-Map,"SAM3U2E_bin/cmsis_example_SAM3U_EK_SAM3U2E_sram.map" -o "SAM3U2E_bin/cmsis_example_SAM3U_EK_SAM3U2E_sram.elf" SAM3U2E_obj/sram_main.o SAM3U2E_obj/sram_startup_sam3u.o SAM3U2E_obj/sram_system_sam3u.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3U2E_obj/sram_main.o
+    302	      0	      0	    302	    12e	SAM3U2E_obj/sram_startup_sam3u.o
+    436	      4	      0	    440	    1b8	SAM3U2E_obj/sram_system_sam3u.o
+    788	      4	    544	   1336	    538	SAM3U2E_bin/cmsis_example_SAM3U_EK_SAM3U2E_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel/SAM3U2E_flash.ld" -Wl,-Map,"SAM3U2E_bin/cmsis_example_SAM3U_EK_SAM3U2E_flash.map" -o "SAM3U2E_bin/cmsis_example_SAM3U_EK_SAM3U2E_flash.elf" SAM3U2E_obj/flash_main.o SAM3U2E_obj/flash_startup_sam3u.o SAM3U2E_obj/flash_system_sam3u.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3U2E_obj/flash_main.o
+    302	      0	      0	    302	    12e	SAM3U2E_obj/flash_startup_sam3u.o
+    436	      4	      0	    440	    1b8	SAM3U2E_obj/flash_system_sam3u.o
+    788	      4	    548	   1340	    53c	SAM3U2E_bin/cmsis_example_SAM3U_EK_SAM3U2E_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3U4C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel/SAM3U4C_sram.ld" -Wl,-Map,"SAM3U4C_bin/cmsis_example_SAM3U_EK_SAM3U4C_sram.map" -o "SAM3U4C_bin/cmsis_example_SAM3U_EK_SAM3U4C_sram.elf" SAM3U4C_obj/sram_main.o SAM3U4C_obj/sram_startup_sam3u.o SAM3U4C_obj/sram_system_sam3u.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3U4C_obj/sram_main.o
+    302	      0	      0	    302	    12e	SAM3U4C_obj/sram_startup_sam3u.o
+    436	      4	      0	    440	    1b8	SAM3U4C_obj/sram_system_sam3u.o
+    788	      4	    544	   1336	    538	SAM3U4C_bin/cmsis_example_SAM3U_EK_SAM3U4C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel/SAM3U4C_flash.ld" -Wl,-Map,"SAM3U4C_bin/cmsis_example_SAM3U_EK_SAM3U4C_flash.map" -o "SAM3U4C_bin/cmsis_example_SAM3U_EK_SAM3U4C_flash.elf" SAM3U4C_obj/flash_main.o SAM3U4C_obj/flash_startup_sam3u.o SAM3U4C_obj/flash_system_sam3u.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3U4C_obj/flash_main.o
+    302	      0	      0	    302	    12e	SAM3U4C_obj/flash_startup_sam3u.o
+    436	      4	      0	    440	    1b8	SAM3U4C_obj/flash_system_sam3u.o
+    788	      4	    548	   1340	    53c	SAM3U4C_bin/cmsis_example_SAM3U_EK_SAM3U4C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3U4E
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel/SAM3U4E_sram.ld" -Wl,-Map,"SAM3U4E_bin/cmsis_example_SAM3U_EK_SAM3U4E_sram.map" -o "SAM3U4E_bin/cmsis_example_SAM3U_EK_SAM3U4E_sram.elf" SAM3U4E_obj/sram_main.o SAM3U4E_obj/sram_startup_sam3u.o SAM3U4E_obj/sram_system_sam3u.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3U4E_obj/sram_main.o
+    302	      0	      0	    302	    12e	SAM3U4E_obj/sram_startup_sam3u.o
+    436	      4	      0	    440	    1b8	SAM3U4E_obj/sram_system_sam3u.o
+    788	      4	    544	   1336	    538	SAM3U4E_bin/cmsis_example_SAM3U_EK_SAM3U4E_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3u/source/gcc_atmel/SAM3U4E_flash.ld" -Wl,-Map,"SAM3U4E_bin/cmsis_example_SAM3U_EK_SAM3U4E_flash.map" -o "SAM3U4E_bin/cmsis_example_SAM3U_EK_SAM3U4E_flash.elf" SAM3U4E_obj/flash_main.o SAM3U4E_obj/flash_startup_sam3u.o SAM3U4E_obj/flash_system_sam3u.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3U4E_obj/flash_main.o
+    302	      0	      0	    302	    12e	SAM3U4E_obj/flash_startup_sam3u.o
+    436	      4	      0	    440	    1b8	SAM3U4E_obj/flash_system_sam3u.o
+    788	      4	    548	   1340	    53c	SAM3U4E_bin/cmsis_example_SAM3U_EK_SAM3U4E_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3A4C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3A4C_sram.ld" -Wl,-Map,"SAM3A4C_bin/cmsis_example_SAM3X_EK_SAM3A4C_sram.map" -o "SAM3A4C_bin/cmsis_example_SAM3X_EK_SAM3A4C_sram.elf" SAM3A4C_obj/sram_main.o SAM3A4C_obj/sram_startup_sam3xa.o SAM3A4C_obj/sram_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3A4C_obj/sram_main.o
+    362	      0	      0	    362	    16a	SAM3A4C_obj/sram_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3A4C_obj/sram_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3A4C_bin/cmsis_example_SAM3X_EK_SAM3A4C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3A4C_flash.ld" -Wl,-Map,"SAM3A4C_bin/cmsis_example_SAM3X_EK_SAM3A4C_flash.map" -o "SAM3A4C_bin/cmsis_example_SAM3X_EK_SAM3A4C_flash.elf" SAM3A4C_obj/flash_main.o SAM3A4C_obj/flash_startup_sam3xa.o SAM3A4C_obj/flash_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3A4C_obj/flash_main.o
+    362	      0	      0	    362	    16a	SAM3A4C_obj/flash_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3A4C_obj/flash_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3A4C_bin/cmsis_example_SAM3X_EK_SAM3A4C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3A8C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3A8C_sram.ld" -Wl,-Map,"SAM3A8C_bin/cmsis_example_SAM3X_EK_SAM3A8C_sram.map" -o "SAM3A8C_bin/cmsis_example_SAM3X_EK_SAM3A8C_sram.elf" SAM3A8C_obj/sram_main.o SAM3A8C_obj/sram_startup_sam3xa.o SAM3A8C_obj/sram_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3A8C_obj/sram_main.o
+    362	      0	      0	    362	    16a	SAM3A8C_obj/sram_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3A8C_obj/sram_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3A8C_bin/cmsis_example_SAM3X_EK_SAM3A8C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3A8C_flash.ld" -Wl,-Map,"SAM3A8C_bin/cmsis_example_SAM3X_EK_SAM3A8C_flash.map" -o "SAM3A8C_bin/cmsis_example_SAM3X_EK_SAM3A8C_flash.elf" SAM3A8C_obj/flash_main.o SAM3A8C_obj/flash_startup_sam3xa.o SAM3A8C_obj/flash_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3A8C_obj/flash_main.o
+    362	      0	      0	    362	    16a	SAM3A8C_obj/flash_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3A8C_obj/flash_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3A8C_bin/cmsis_example_SAM3X_EK_SAM3A8C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3X4C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3X4C_sram.ld" -Wl,-Map,"SAM3X4C_bin/cmsis_example_SAM3X_EK_SAM3X4C_sram.map" -o "SAM3X4C_bin/cmsis_example_SAM3X_EK_SAM3X4C_sram.elf" SAM3X4C_obj/sram_main.o SAM3X4C_obj/sram_startup_sam3xa.o SAM3X4C_obj/sram_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3X4C_obj/sram_main.o
+    362	      0	      0	    362	    16a	SAM3X4C_obj/sram_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3X4C_obj/sram_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3X4C_bin/cmsis_example_SAM3X_EK_SAM3X4C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3X4C_flash.ld" -Wl,-Map,"SAM3X4C_bin/cmsis_example_SAM3X_EK_SAM3X4C_flash.map" -o "SAM3X4C_bin/cmsis_example_SAM3X_EK_SAM3X4C_flash.elf" SAM3X4C_obj/flash_main.o SAM3X4C_obj/flash_startup_sam3xa.o SAM3X4C_obj/flash_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3X4C_obj/flash_main.o
+    362	      0	      0	    362	    16a	SAM3X4C_obj/flash_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3X4C_obj/flash_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3X4C_bin/cmsis_example_SAM3X_EK_SAM3X4C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3X4E
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3X4E_sram.ld" -Wl,-Map,"SAM3X4E_bin/cmsis_example_SAM3X_EK_SAM3X4E_sram.map" -o "SAM3X4E_bin/cmsis_example_SAM3X_EK_SAM3X4E_sram.elf" SAM3X4E_obj/sram_main.o SAM3X4E_obj/sram_startup_sam3xa.o SAM3X4E_obj/sram_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3X4E_obj/sram_main.o
+    362	      0	      0	    362	    16a	SAM3X4E_obj/sram_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3X4E_obj/sram_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3X4E_bin/cmsis_example_SAM3X_EK_SAM3X4E_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3X4E_flash.ld" -Wl,-Map,"SAM3X4E_bin/cmsis_example_SAM3X_EK_SAM3X4E_flash.map" -o "SAM3X4E_bin/cmsis_example_SAM3X_EK_SAM3X4E_flash.elf" SAM3X4E_obj/flash_main.o SAM3X4E_obj/flash_startup_sam3xa.o SAM3X4E_obj/flash_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3X4E_obj/flash_main.o
+    362	      0	      0	    362	    16a	SAM3X4E_obj/flash_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3X4E_obj/flash_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3X4E_bin/cmsis_example_SAM3X_EK_SAM3X4E_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3X8C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3X8C_sram.ld" -Wl,-Map,"SAM3X8C_bin/cmsis_example_SAM3X_EK_SAM3X8C_sram.map" -o "SAM3X8C_bin/cmsis_example_SAM3X_EK_SAM3X8C_sram.elf" SAM3X8C_obj/sram_main.o SAM3X8C_obj/sram_startup_sam3xa.o SAM3X8C_obj/sram_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3X8C_obj/sram_main.o
+    362	      0	      0	    362	    16a	SAM3X8C_obj/sram_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3X8C_obj/sram_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3X8C_bin/cmsis_example_SAM3X_EK_SAM3X8C_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3X8C_flash.ld" -Wl,-Map,"SAM3X8C_bin/cmsis_example_SAM3X_EK_SAM3X8C_flash.map" -o "SAM3X8C_bin/cmsis_example_SAM3X_EK_SAM3X8C_flash.elf" SAM3X8C_obj/flash_main.o SAM3X8C_obj/flash_startup_sam3xa.o SAM3X8C_obj/flash_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3X8C_obj/flash_main.o
+    362	      0	      0	    362	    16a	SAM3X8C_obj/flash_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3X8C_obj/flash_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3X8C_bin/cmsis_example_SAM3X_EK_SAM3X8C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3X8E
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3X8E_sram.ld" -Wl,-Map,"SAM3X8E_bin/cmsis_example_SAM3X_EK_SAM3X8E_sram.map" -o "SAM3X8E_bin/cmsis_example_SAM3X_EK_SAM3X8E_sram.elf" SAM3X8E_obj/sram_main.o SAM3X8E_obj/sram_startup_sam3xa.o SAM3X8E_obj/sram_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3X8E_obj/sram_main.o
+    362	      0	      0	    362	    16a	SAM3X8E_obj/sram_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3X8E_obj/sram_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3X8E_bin/cmsis_example_SAM3X_EK_SAM3X8E_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3X8E_flash.ld" -Wl,-Map,"SAM3X8E_bin/cmsis_example_SAM3X_EK_SAM3X8E_flash.map" -o "SAM3X8E_bin/cmsis_example_SAM3X_EK_SAM3X8E_flash.elf" SAM3X8E_obj/flash_main.o SAM3X8E_obj/flash_startup_sam3xa.o SAM3X8E_obj/flash_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3X8E_obj/flash_main.o
+    362	      0	      0	    362	    16a	SAM3X8E_obj/flash_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3X8E_obj/flash_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3X8E_bin/cmsis_example_SAM3X_EK_SAM3X8E_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM3X8H
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3X8H_sram.ld" -Wl,-Map,"SAM3X8H_bin/cmsis_example_SAM3X_EK_SAM3X8H_sram.map" -o "SAM3X8H_bin/cmsis_example_SAM3X_EK_SAM3X8H_sram.elf" SAM3X8H_obj/sram_main.o SAM3X8H_obj/sram_startup_sam3xa.o SAM3X8H_obj/sram_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3X8H_obj/sram_main.o
+    362	      0	      0	    362	    16a	SAM3X8H_obj/sram_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3X8H_obj/sram_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3X8H_bin/cmsis_example_SAM3X_EK_SAM3X8H_sram.elf
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam3xa/source/gcc_atmel/SAM3X8H_flash.ld" -Wl,-Map,"SAM3X8H_bin/cmsis_example_SAM3X_EK_SAM3X8H_flash.map" -o "SAM3X8H_bin/cmsis_example_SAM3X_EK_SAM3X8H_flash.elf" SAM3X8H_obj/flash_main.o SAM3X8H_obj/flash_startup_sam3xa.o SAM3X8H_obj/flash_system_sam3xa.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM3X8H_obj/flash_main.o
+    362	      0	      0	    362	    16a	SAM3X8H_obj/flash_startup_sam3xa.o
+    436	      4	      0	    440	    1b8	SAM3X8H_obj/flash_system_sam3xa.o
+    848	      4	    548	   1400	    578	SAM3X8H_bin/cmsis_example_SAM3X_EK_SAM3X8H_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM4S8B
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+../../../Device/ATMEL/sam4s/source/system_sam4s.c:176:6: warning: no previous prototype for 'system_init_flash' [-Wmissing-prototypes]
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel/SAM4S8B_sram.ld" -Wl,-Map,"SAM4S8B_bin/cmsis_example_SAM4S_EK_SAM4S8B_sram.map" -o "SAM4S8B_bin/cmsis_example_SAM4S_EK_SAM4S8B_sram.elf" SAM4S8B_obj/sram_main.o SAM4S8B_obj/sram_startup_sam4s.o SAM4S8B_obj/sram_system_sam4s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM4S8B_obj/sram_main.o
+    298	      0	      0	    298	    12a	SAM4S8B_obj/sram_startup_sam4s.o
+    412	      4	      0	    416	    1a0	SAM4S8B_obj/sram_system_sam4s.o
+    784	      4	    548	   1336	    538	SAM4S8B_bin/cmsis_example_SAM4S_EK_SAM4S8B_sram.elf
+../../../Device/ATMEL/sam4s/source/system_sam4s.c:176:6: warning: no previous prototype for 'system_init_flash' [-Wmissing-prototypes]
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel/SAM4S8B_flash.ld" -Wl,-Map,"SAM4S8B_bin/cmsis_example_SAM4S_EK_SAM4S8B_flash.map" -o "SAM4S8B_bin/cmsis_example_SAM4S_EK_SAM4S8B_flash.elf" SAM4S8B_obj/flash_main.o SAM4S8B_obj/flash_startup_sam4s.o SAM4S8B_obj/flash_system_sam4s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM4S8B_obj/flash_main.o
+    298	      0	      0	    298	    12a	SAM4S8B_obj/flash_startup_sam4s.o
+    412	      4	      0	    416	    1a0	SAM4S8B_obj/flash_system_sam4s.o
+    784	      4	    548	   1336	    538	SAM4S8B_bin/cmsis_example_SAM4S_EK_SAM4S8B_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM4S8C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+../../../Device/ATMEL/sam4s/source/system_sam4s.c:176:6: warning: no previous prototype for 'system_init_flash' [-Wmissing-prototypes]
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel/SAM4S8C_sram.ld" -Wl,-Map,"SAM4S8C_bin/cmsis_example_SAM4S_EK_SAM4S8C_sram.map" -o "SAM4S8C_bin/cmsis_example_SAM4S_EK_SAM4S8C_sram.elf" SAM4S8C_obj/sram_main.o SAM4S8C_obj/sram_startup_sam4s.o SAM4S8C_obj/sram_system_sam4s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM4S8C_obj/sram_main.o
+    298	      0	      0	    298	    12a	SAM4S8C_obj/sram_startup_sam4s.o
+    412	      4	      0	    416	    1a0	SAM4S8C_obj/sram_system_sam4s.o
+    784	      4	    548	   1336	    538	SAM4S8C_bin/cmsis_example_SAM4S_EK_SAM4S8C_sram.elf
+../../../Device/ATMEL/sam4s/source/system_sam4s.c:176:6: warning: no previous prototype for 'system_init_flash' [-Wmissing-prototypes]
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel/SAM4S8C_flash.ld" -Wl,-Map,"SAM4S8C_bin/cmsis_example_SAM4S_EK_SAM4S8C_flash.map" -o "SAM4S8C_bin/cmsis_example_SAM4S_EK_SAM4S8C_flash.elf" SAM4S8C_obj/flash_main.o SAM4S8C_obj/flash_startup_sam4s.o SAM4S8C_obj/flash_system_sam4s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM4S8C_obj/flash_main.o
+    298	      0	      0	    298	    12a	SAM4S8C_obj/flash_startup_sam4s.o
+    412	      4	      0	    416	    1a0	SAM4S8C_obj/flash_system_sam4s.o
+    784	      4	    548	   1336	    538	SAM4S8C_bin/cmsis_example_SAM4S_EK_SAM4S8C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM4S16B
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+../../../Device/ATMEL/sam4s/source/system_sam4s.c:176:6: warning: no previous prototype for 'system_init_flash' [-Wmissing-prototypes]
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel/SAM4S16B_sram.ld" -Wl,-Map,"SAM4S16B_bin/cmsis_example_SAM4S_EK_SAM4S16B_sram.map" -o "SAM4S16B_bin/cmsis_example_SAM4S_EK_SAM4S16B_sram.elf" SAM4S16B_obj/sram_main.o SAM4S16B_obj/sram_startup_sam4s.o SAM4S16B_obj/sram_system_sam4s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM4S16B_obj/sram_main.o
+    298	      0	      0	    298	    12a	SAM4S16B_obj/sram_startup_sam4s.o
+    412	      4	      0	    416	    1a0	SAM4S16B_obj/sram_system_sam4s.o
+    784	      4	    548	   1336	    538	SAM4S16B_bin/cmsis_example_SAM4S_EK_SAM4S16B_sram.elf
+../../../Device/ATMEL/sam4s/source/system_sam4s.c:176:6: warning: no previous prototype for 'system_init_flash' [-Wmissing-prototypes]
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel/SAM4S16B_flash.ld" -Wl,-Map,"SAM4S16B_bin/cmsis_example_SAM4S_EK_SAM4S16B_flash.map" -o "SAM4S16B_bin/cmsis_example_SAM4S_EK_SAM4S16B_flash.elf" SAM4S16B_obj/flash_main.o SAM4S16B_obj/flash_startup_sam4s.o SAM4S16B_obj/flash_system_sam4s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM4S16B_obj/flash_main.o
+    298	      0	      0	    298	    12a	SAM4S16B_obj/flash_startup_sam4s.o
+    412	      4	      0	    416	    1a0	SAM4S16B_obj/flash_system_sam4s.o
+    784	      4	    548	   1336	    538	SAM4S16B_bin/cmsis_example_SAM4S_EK_SAM4S16B_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+--- 
+--- 
+--- Making SAM4S16C
+--- 
+make[1]: Entering directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
+../../../Device/ATMEL/sam4s/source/system_sam4s.c:176:6: warning: no previous prototype for 'system_init_flash' [-Wmissing-prototypes]
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel/SAM4S16C_sram.ld" -Wl,-Map,"SAM4S16C_bin/cmsis_example_SAM4S_EK_SAM4S16C_sram.map" -o "SAM4S16C_bin/cmsis_example_SAM4S_EK_SAM4S16C_sram.elf" SAM4S16C_obj/sram_main.o SAM4S16C_obj/sram_startup_sam4s.o SAM4S16C_obj/sram_system_sam4s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM4S16C_obj/sram_main.o
+    298	      0	      0	    298	    12a	SAM4S16C_obj/sram_startup_sam4s.o
+    412	      4	      0	    416	    1a0	SAM4S16C_obj/sram_system_sam4s.o
+    784	      4	    548	   1336	    538	SAM4S16C_bin/cmsis_example_SAM4S_EK_SAM4S16C_sram.elf
+../../../Device/ATMEL/sam4s/source/system_sam4s.c:176:6: warning: no previous prototype for 'system_init_flash' [-Wmissing-prototypes]
+arm-none-eabi-gcc -L=/lib/thumb2 -L"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel" -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols  -T"S:/CMSIS_svn/trunk/Device/ATMEL/sam4s/source/gcc_atmel/SAM4S16C_flash.ld" -Wl,-Map,"SAM4S16C_bin/cmsis_example_SAM4S_EK_SAM4S16C_flash.map" -o "SAM4S16C_bin/cmsis_example_SAM4S_EK_SAM4S16C_flash.elf" SAM4S16C_obj/flash_main.o SAM4S16C_obj/flash_startup_sam4s.o SAM4S16C_obj/flash_system_sam4s.o -Wl,--start-group -lgcc -lc -Wl,--end-group
+   text	   data	    bss	    dec	    hex	filename
+    136	      0	      4	    140	     8c	SAM4S16C_obj/flash_main.o
+    298	      0	      0	    298	    12a	SAM4S16C_obj/flash_startup_sam4s.o
+    412	      4	      0	    416	    1a0	SAM4S16C_obj/flash_system_sam4s.o
+    784	      4	    548	   1336	    538	SAM4S16C_bin/cmsis_example_SAM4S_EK_SAM4S16C_flash.elf
+make[1]: Leaving directory `S:/CMSIS_svn/trunk/Examples/cmsis_example/gcc_atmel'
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/make-3.81-GnuWin32.README b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/make-3.81-GnuWin32.README
new file mode 100644
index 0000000..a144a66
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/make-3.81-GnuWin32.README
@@ -0,0 +1,50 @@
+* Make-3.81 for Windows *
+=========================
+
+What is it?
+-----------
+Make: GNU make utility to maintain groups of programs
+
+Description
+-----------
+Make is a tool which controls the generation of executables and other non-source files of a program from the program's source files. Make gets its knowledge of how to build your program from a file called the makefile, which lists each of the non-source files and how to compute it from other files. When you write a program, you should write a makefile for it, so that it is possible to use Make to build and install the program. Capabilities of Make - Make enables the end user to build and install your package without knowing the details of how that is done -- because these details are recorded in the makefile that you supply. - Make figures out automatically which files it needs to update, based on which source files have changed. It also automatically determines the proper order for updating files, in case one non-source file depends on another non-source file. As a result, if you change a few source files and then run Make, it does not need to recompile all of your program. It updates only those non-source files that depend directly or indirectly on the source files that you changed. - Make is not limited to any particular language. For each non-source file in the program, the makefile specifies the shell commands to compute it. These shell commands can run a compiler to produce an object file, the linker to produce an executable, ar to update a library, or TeX or Makeinfo to format documentation. - Make is not limited to building a package. You can also use Make to control installing or deinstalling a package, generate tags tables for it, or anything else you want to do often enough to make it worth while writing down how to do it.
+	 
+Homepage
+--------
+http://www.gnu.org/software/make
+	 
+System
+------
+- Win32, i.e. MS-Windows 95 / 98 / ME / NT / 2000 / XP / 2003 with msvcrt.dll
+- if msvcrt.dll is not in your Windows/System folder, get it from
+  Microsoft 
+  or by installing Internet Explorer 4.0 or higher
+   
+- libintl3  
+- libiconv2  
+
+Notes
+-----
+- Bugs and questions on this MS-Windows port: gnuwin32@users.sourceforge.net
+
+Package Availability
+--------------------
+- in: http://gnuwin32.sourceforge.net
+Installation
+------------
+
+Sources
+-------
+- make-3.81-src.zip
+
+Compilation
+-----------
+The package has been compiled with GNU auto-tools, GNU make, and Mingw
+(GCC for MS-Windows). Any differences from the original sources are given
+in make-3.81-GnuWin32.diffs in make-3.81-src.zip. Libraries needed
+for compilation can be found at the lines starting with 'LIBS = ' in the
+Makefiles. Usually, these are standard libraries provided with Mingw, or
+libraries from the package itself; 'gw32c' refers to the libgw32c package,
+which provides MS-Windows substitutes or stubs for functions normally found in
+Unix. For more information, see: http://gnuwin32.sourceforge.net/compile.html
+and http://gnuwin32.sourceforge.net/packages/libgw32c.htm.
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/make.exe b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/make.exe
new file mode 100644
index 0000000..58d49e3
Binary files /dev/null and b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/make.exe differ
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/rm.exe b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/rm.exe
new file mode 100644
index 0000000..8e79306
Binary files /dev/null and b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/rm.exe differ
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3n_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3n_ek_flash.gdb
new file mode 100644
index 0000000..344beda
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3n_ek_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3N.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3N4C
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x00400000)
+#set *0x400004 = *0x400004 & 0xFFFFFFFE
+mon reg pc=(0x00400004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3n_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3n_ek_sram.gdb
new file mode 100644
index 0000000..ac5d63a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3n_ek_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3N.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3s_ek2_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3s_ek2_flash.gdb
new file mode 100644
index 0000000..095a174
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3s_ek2_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3S.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3S4C
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x400000)
+#set *0x400004 = *0x400004 & 0xFFFFFFFE
+mon reg pc=(0x400004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3s_ek2_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3s_ek2_sram.gdb
new file mode 100644
index 0000000..e936ff7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3s_ek2_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3S.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3s_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3s_ek_flash.gdb
new file mode 100644
index 0000000..095a174
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3s_ek_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3S.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3S4C
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x400000)
+#set *0x400004 = *0x400004 & 0xFFFFFFFE
+mon reg pc=(0x400004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3s_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3s_ek_sram.gdb
new file mode 100644
index 0000000..e936ff7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3s_ek_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3S.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3u_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3u_ek_flash.gdb
new file mode 100644
index 0000000..70933c7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3u_ek_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3U.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3U4E
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1200 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x80000)
+#set *0x80004 = *0x80004 & 0xFFFFFFFE
+mon reg pc=(0x80004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3u_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3u_ek_sram.gdb
new file mode 100644
index 0000000..b658487
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3u_ek_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3U.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1200 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3x_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3x_ek_flash.gdb
new file mode 100644
index 0000000..dc1acb8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3x_ek_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3X.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3X8H
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1a00 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x80000)
+#set *0x80004 = *0x80004 & 0xFFFFFFFE
+mon reg pc=(0x80004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3x_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3x_ek_sram.gdb
new file mode 100644
index 0000000..a3f4293
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam3x_ek_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3X.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1a00 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam4s_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam4s_ek_flash.gdb
new file mode 100644
index 0000000..4482476
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam4s_ek_flash.gdb
@@ -0,0 +1,32 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device (Should be AT91SAM4S16C, but it is not available now)
+monitor flash device = AT91SAM4S16C
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral  (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initializing PC and stack pointer
+mon reg sp=(0x400000)
+mon reg pc=(0x400004)
+info reg
+
+# end of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam4s_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam4s_ek_sram.gdb
new file mode 100644
index 0000000..0834162
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam4s_ek_sram.gdb
@@ -0,0 +1,27 @@
+#*************************************************
+#
+#  Connect to J-Link and debug application in sram.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral  (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initializing PC and stack pointer
+mon reg sp=(0x20000000)
+mon reg pc=(0x20000004)
+info reg
+
+# end of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam_series.mk b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam_series.mk
new file mode 100644
index 0000000..c08a476
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_arm/sam_series.mk
@@ -0,0 +1,37 @@
+# ----------------------------------------------------------------------------
+#         ATMEL Microcontroller Software Support 
+# ----------------------------------------------------------------------------
+# Copyright (c) 2010, Atmel Corporation
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following condition is met:
+#
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the disclaimer below.
+#
+# Atmel's name may not be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# ----------------------------------------------------------------------------
+
+# define SAM series
+SAM3N=SAM3N00A SAM3N00B SAM3N0A SAM3N0B SAM3N0C SAM3N1A SAM3N1B SAM3N1C SAM3N2A SAM3N2B SAM3N2C SAM3N4A SAM3N4B SAM3N4C
+SAM3S=SAM3S1A SAM3S1B SAM3S1C SAM3S2A SAM3S2B SAM3S2C SAM3S4A SAM3S4B SAM3S4C
+SAM3SD8=SAM3S8B SAM3S8C SAM3SD8B SAM3SD8C
+SAM3U=SAM3U1C SAM3U1E SAM3U2C SAM3U2E SAM3U4C SAM3U4E
+SAM3XA=SAM3A4C SAM3A8C SAM3X4C SAM3X4E SAM3X8C SAM3X8E SAM3X8H
+SAM4S=SAM4S8B SAM4S8C SAM4S16B SAM4S16C
+
+SAM_SERIES=$(SAM3N) $(SAM3S) $(SAM3SD8) $(SAM3U) $(SAM3XA) $(SAM4S)
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/Makefile b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/Makefile
new file mode 100644
index 0000000..2573603
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/Makefile
@@ -0,0 +1,75 @@
+# ----------------------------------------------------------------------------
+#         ATMEL Microcontroller Software Support 
+# ----------------------------------------------------------------------------
+# Copyright (c) 2010, Atmel Corporation
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following condition is met:
+#
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the disclaimer below.
+#
+# Atmel's name may not be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# ----------------------------------------------------------------------------
+
+# make inner variables
+.DEFAULT_GOAL := all
+
+# custom variables
+BUILD_NUMBER := 
+BUILDS := 
+CLEANS :=
+
+# Build macro
+define BUILD_SERIES
+
+# output test number information
+$(info Defining cmsis_example_$(1)_build and cmsis_example_$(1)_clean)
+
+# add the incoming targets to global targets
+BUILDS += cmsis_example_$(1)_build
+CLEANS += cmsis_example_$(1)_clean
+BUILD_NUMBER += x
+
+.PHONY: cmsis_example_$(1)_build
+cmsis_example_$(1)_build:
+	@echo --- 
+	@echo --- 
+	@echo --- Making $(1)
+	@echo --- 
+	@$(MAKE) CHIP=$(1) -f cmsis_example.mk
+	
+.PHONY: cmsis_example_$(1)_clean
+cmsis_example_$(1)_clean:
+	@echo --- 
+	@echo --- 
+	@echo --- Cleaning $(1)
+	@echo --- 
+	@$(MAKE) CHIP=$(1) clean -f cmsis_example.mk
+endef
+
+# define SAM series
+include sam_series.mk
+
+$(foreach SERIES, $(SAM_SERIES), $(eval $(call BUILD_SERIES,$(SERIES))))
+
+# output test number information
+$(info Number of devices to be tested $(words $(BUILD_NUMBER)) /  $(words $(SAM_SERIES)))
+
+all: $(BUILDS)
+
+clean: $(CLEANS)
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/build.bat b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/build.bat
new file mode 100644
index 0000000..aa4e396
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/build.bat
@@ -0,0 +1 @@
+@make --no-builtin-rules --no-builtin-variables >log.txt 2>&1
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/build_debug.bat b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/build_debug.bat
new file mode 100644
index 0000000..d605bee
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/build_debug.bat
@@ -0,0 +1 @@
+@make --no-builtin-rules --no-builtin-variables -d >log_debug.txt 2>&1
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/cmsis_example.mk b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/cmsis_example.mk
new file mode 100644
index 0000000..991114d
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/cmsis_example.mk
@@ -0,0 +1,197 @@
+# ----------------------------------------------------------------------------
+#         ATMEL Microcontroller Software Support
+# ----------------------------------------------------------------------------
+# Copyright (c) 2010, Atmel Corporation
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following condition is met:
+#
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the disclaimer below.
+#
+# Atmel's name may not be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# ----------------------------------------------------------------------------
+
+#-------------------------------------------------------------------------------
+#        User-modifiable options
+#-------------------------------------------------------------------------------
+
+ifeq ('$(CHIP)','')
+$(error CHIP not defined)
+endif
+
+include sam_series.mk
+
+# fill the needed variables
+ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3N)))
+
+BOARD:=SAM3N_EK
+SERIES:=sam3n
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3S)))
+
+BOARD:=SAM3S_EK
+SERIES:=sam3s
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3SD8)))
+
+BOARD:=SAM3S_EK2
+SERIES:=sam3sd8
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3U)))
+
+BOARD:=SAM3U_EK
+SERIES:=sam3u
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM3XA)))
+
+BOARD:=SAM3X_EK
+SERIES:=sam3xa
+
+else ifeq ($(CHIP),$(findstring $(CHIP), $(SAM4S)))
+
+BOARD:=SAM4S_EK
+SERIES:=sam4s
+
+endif
+
+
+# Defines which are the available memory targets for the device.
+MEMORIES = sram flash
+
+# Optimization level, put in comment for debugging
+OPTIMIZATION = -Os
+
+# Output directories
+BIN = $(CHIP)_bin
+OBJ = $(CHIP)_obj
+
+# Output file basename
+OUTPUT_BIN = $(BIN)/cmsis_example_$(BOARD)_$(CHIP)
+
+# GCC toolchain provider
+GCC_TOOLCHAIN=gcc_atmel
+
+#-------------------------------------------------------------------------------
+#		Tools
+#-------------------------------------------------------------------------------
+
+# Toolchain prefix when cross-compiling
+CROSS_COMPILE = arm-none-eabi-
+
+CMSIS_ROOT=../../..
+CMSIS_PATH=$(CMSIS_ROOT)/CMSIS/Include
+SAM_PATH=$(CMSIS_ROOT)/Device/ATMEL
+DEVICE_PATH=$(SAM_PATH)/$(SERIES)/source
+
+LIBS = -Wl,--start-group -lgcc -lc -Wl,--end-group
+
+LIB_PATH+=-L=/lib/thumb2
+LIB_PATH+=-L"$(realpath $(DEVICE_PATH)/$(GCC_TOOLCHAIN))"
+
+# Compilation tools
+CC = $(CROSS_COMPILE)gcc
+LD = $(CROSS_COMPILE)ld
+SIZE = $(CROSS_COMPILE)size
+STRIP = $(CROSS_COMPILE)strip
+OBJCOPY = $(CROSS_COMPILE)objcopy
+GDB = $(CROSS_COMPILE)gdb
+NM = $(CROSS_COMPILE)nm
+RM = rm
+
+# Flags
+INCLUDES := -I"$(CMSIS_PATH)"
+INCLUDES += -I"$(SAM_PATH)"
+INCLUDES += -I"$(SAM_PATH)/$(SERIES)/include"
+
+CFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
+CFLAGS += -Werror-implicit-function-declaration -Wmain -Wparentheses
+CFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CFLAGS += -Wshadow -Wpointer-arith -Wbad-function-cast -Wwrite-strings
+CFLAGS += -Wsign-compare -Waggregate-return -Wstrict-prototypes
+CFLAGS += -Wmissing-prototypes -Wmissing-declarations
+CFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CFLAGS += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long
+CFLAGS += -Wunreachable-code
+CFLAGS += -Wcast-align
+#CFLAGS += -Wmissing-noreturn
+#CFLAGS += -Wconversion
+
+# To reduce application size use only integer printf function.
+CFLAGS += -Dprintf=iprintf
+
+# CFLAGS += -mlong-calls -Wall
+# CFLAGS += -ansi
+CFLAGS += -std=c99 
+CFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -ffunction-sections
+CFLAGS += -g $(OPTIMIZATION) $(INCLUDES) -D__$(CHIP)__ -DBOARD=$(BOARD)
+ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -g $(OPTIMIZATION) $(INCLUDES) -D__$(CHIP)__ -D__ASSEMBLY__
+LDFLAGS= -mcpu=cortex-m3 -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--defsym=STACK_SIZE=0x200 -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols
+#LD_OPTIONAL=-Wl,--print-gc-sections -Wl,--stats
+
+#-------------------------------------------------------------------------------
+#		Files
+#-------------------------------------------------------------------------------
+
+# Directories where source files can be found
+
+VPATH += ..
+VPATH += $(DEVICE_PATH)
+VPATH += $(DEVICE_PATH)/$(GCC_TOOLCHAIN)
+
+# Objects built from C source files
+C_OBJECTS += main.o
+C_OBJECTS += startup_$(SERIES).o
+C_OBJECTS += system_$(SERIES).o
+
+# Append OBJ and BIN directories to output filename
+OUTPUT := $(BIN)/$(OUTPUT_BIN)
+
+#-------------------------------------------------------------------------------
+#		Rules
+#-------------------------------------------------------------------------------
+
+all: $(BIN) $(OBJ) $(MEMORIES)
+
+$(BIN) $(OBJ):
+	-@mkdir $@
+
+define RULES
+C_OBJECTS_$(1) = $(addprefix $(OBJ)/$(1)_, $(C_OBJECTS))
+ASM_OBJECTS_$(1) = $(addprefix $(OBJ)/$(1)_, $(ASM_OBJECTS))
+
+$(1): $$(ASM_OBJECTS_$(1)) $$(C_OBJECTS_$(1))
+	$(CC) $(LIB_PATH) $(LDFLAGS) $(LD_OPTIONAL) -T"$(realpath $(DEVICE_PATH)/$(GCC_TOOLCHAIN)/$(CHIP)_$$@.ld)" -Wl,-Map,"$(OUTPUT_BIN)_$$@.map" -o "$(OUTPUT_BIN)_$$@.elf" $$^ $(LIBS)
+	@$(NM) "$(OUTPUT_BIN)_$$@.elf" >"$(OUTPUT_BIN)_$$@.elf.txt"
+	@$(OBJCOPY) -O binary "$(OUTPUT_BIN)_$$@.elf" "$(OUTPUT_BIN)_$$@.bin"
+	@$(SIZE) $$^ "$(OUTPUT_BIN)_$$@.elf"
+
+$$(C_OBJECTS_$(1)): $(OBJ)/$(1)_%.o: %.c Makefile $(OBJ) $(BIN)
+	@$(CC) $(CFLAGS) -D$(1) -c -o $$@ $$<
+
+$$(ASM_OBJECTS_$(1)): $(OBJ)/$(1)_%.o: %.S Makefile $(OBJ) $(BIN)
+	@$(CC) $(ASFLAGS) -D$(1) -c -o $$@ $$<
+
+debug_$(1): $(1)
+	$(GDB) -x "$(CHIP)_$(1).gdb" -ex "reset" -readnow -se "$(OUTPUT_BIN)_$(1).elf"
+endef
+
+$(foreach MEMORY, $(MEMORIES), $(eval $(call RULES,$(MEMORY))))
+
+clean:
+	-$(RM) -fR $(OBJ) $(BIN)
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/coreutils-5.3.0-GnuWin32.README b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/coreutils-5.3.0-GnuWin32.README
new file mode 100644
index 0000000..cd2b84e
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/coreutils-5.3.0-GnuWin32.README
@@ -0,0 +1,151 @@
+* CoreUtils-5.3.0 for Windows *
+===============================
+
+What is it?
+-----------
+CoreUtils: collection of basic file, shell and text manipulation utilities
+
+Description
+-----------
+The GNU Core Utilities are the basic file, shell and text manipulation utilities
+of the GNU operating system. These are the core utilities which are expected to
+exist on every operating system. 
+
+File utilities:
+
+- chgrp: Changes file group ownership. 
+- chown: Changes file ownership. 
+- chmod: Changes file permissions. 
+- cp: Copies files. 
+- dd: Copies and converts a file. 
+- df: Shows disk free space on filesystems. 
+- dir: Gives a brief directory listing. 
+- dircolors: Setup program for the color output of GNU ls. 
+- du: Shows disk usage on filesystems. 
+- install: Copies file and sets its permissions. 
+- ln: Creates file links. 
+- ls: Lists directory contents. 
+- mkdir: Creates directories. 
+- mkfifo: Creates FIFOs (named pipes). 
+- mknod: Creates special files. 
+- mv: Moves files. 
+- rm: Removes (deletes) files. 
+- rmdir: Removes empty directories. 
+- shred: Destroy data in files. 
+- sync: Synchronizes filesystem buffers and disk. 
+- touch: Changes file timestamps. 
+- vdir: Long directory listing.
+
+
+Text utilities:
+
+- cat: concatenates and prints files on the standard output
+- cksum: checksum and count the bytes in a file
+- comm: compares two sorted files line by line
+- csplit: splits a file into sections determined by context lines
+- cut: remove sections from each line of files
+- expand: convert tabs to spaces
+- fmt: simple optimal text formatter
+- fold: wrap each input line to fit in specified width
+- head: output the first part of files
+- join: join lines of two files on a common field
+- md5sum: compute and check MD5 messsage digest
+- nl: number lines of files
+- od: dump files in octal and other formats
+- paste: merge lines of files
+- ptx: produce a permuted index of file contents
+- pr: convert text files for printing
+- shasum: compute and check SHA1 message digest
+- sort: sort lines of text files
+- split: split a file into pieces
+- sum: checksum and count the blocks in a file
+- tac: concatenates and prints files in reverse
+- tail: outputs the last part of files
+- tr: translates or deletes characters
+- tsort: perform topological sort
+- unexpand: convert spaces to tabs
+- uniq: remove duplicate lines from a sorted file
+- wc: prints the number of bytes, words, and lines in files
+
+
+Shell utilities:
+
+- [ - Check file types and compare values 
+- basename - Removes the path prefix from a given pathname. 
+- chroot - Changes the root directory. 
+- date - Prints/sets the system date and time. 
+- dirname - Removes the last level or filename from a given pathname. 
+- echo - Prints a line of text. 
+- env - Displays/modifies the environment. 
+- expr - Evaluates expressions. 
+- factor - Prints prime factors. 
+- false - Returns an unsuccessful exit status. 
+- groups - Print the groups that the user is a member of. 
+- hostid - Print the numeric identifier for the current host 
+- hostname - Print or set the machine name. 
+- id - Print real/effective uid/gid. 
+- logname - Print current login name. 
+- nice - Modify scheduling priority. 
+- nohup - Allows a command to continue running after logging out. 
+- pathchk - Check file name portability. 
+- pinky - Lightweight finger 
+- printenv - Prints environment variables. 
+- printf - Formats and prints data. 
+- pwd - Print the current working directory. 
+- seq - Print numeric sequences. 
+- sleep - Suspends execution for a specified time. 
+- stty - Print/change terminal settings. 
+- su - Allows you to adopt the id of another user or superuser. 
+- tee - Sends output to multiple files. 
+- test - Evaluates an expression. 
+- true - Returns a successful exit status. 
+- tty - Print terminal name. 
+- uname - Print system information. 
+- users - Print current user names. 
+- who - Print a list of all users currently logged in. 
+- whoami - Print effective user id. 
+- yes - Print a string repeatedly. 
+	 
+Homepage
+--------
+http://www.gnu.org/software/coreutils
+	 
+System
+------
+- MS-Windows 95 / 98 / ME / NT / 2000 / XP with msvcrt.dll
+- if msvcrt.dll is not in your Windows/System folder, get it from
+  Microsoft 
+  or by installing Internet Explorer 4.0 or higher
+   
+- libintl-2  
+- libiconv-2  
+
+Notes
+-----
+- Bugs and questions on this MS-Windows port: gnuwin32@users.sourceforge.net
+
+Package Availability
+--------------------
+- in: http://gnuwin32.sourceforge.net
+Installation
+------------
+The MS-Windows version of ln implements soft links as MS-Windows
+shortcuts. If necessary, it adds the extension .lnk
+Hard links are implemented as copies on MS-Windows-95 / 98 / ME,
+and as hard linls on MS-Windows-NT / 2000 / XP.
+
+Sources
+-------
+- coreutils-5.3.0-src.zip
+
+Compilation
+-----------
+The package has been compiled with GNU auto-tools, GNU make, and Mingw
+(GCC for MS-Windows). Any differences from the original sources are given
+in coreutils-5.3.0-GnuWin32.diffs in coreutils-5.3.0-src.zip. Libraries needed
+for compilation can be found at the lines starting with 'LIBS = ' in the
+Makefiles. Usually, these are standard libraries provided with Mingw, or
+libraries from the package itself; 'gw32c' refers to the libgw32c package,
+which provides MS-Windows substitutes or stubs for functions normally found in
+Unix. For more information, see: http://gnuwin32.sourceforge.net/compile.html
+and http://gnuwin32.sourceforge.net/packages/libgw32c.htm.
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diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/make-3.81-GnuWin32.README b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/make-3.81-GnuWin32.README
new file mode 100644
index 0000000..a144a66
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/make-3.81-GnuWin32.README
@@ -0,0 +1,50 @@
+* Make-3.81 for Windows *
+=========================
+
+What is it?
+-----------
+Make: GNU make utility to maintain groups of programs
+
+Description
+-----------
+Make is a tool which controls the generation of executables and other non-source files of a program from the program's source files. Make gets its knowledge of how to build your program from a file called the makefile, which lists each of the non-source files and how to compute it from other files. When you write a program, you should write a makefile for it, so that it is possible to use Make to build and install the program. Capabilities of Make - Make enables the end user to build and install your package without knowing the details of how that is done -- because these details are recorded in the makefile that you supply. - Make figures out automatically which files it needs to update, based on which source files have changed. It also automatically determines the proper order for updating files, in case one non-source file depends on another non-source file. As a result, if you change a few source files and then run Make, it does not need to recompile all of your program. It updates only those non-source files that depend directly or indirectly on the source files that you changed. - Make is not limited to any particular language. For each non-source file in the program, the makefile specifies the shell commands to compute it. These shell commands can run a compiler to produce an object file, the linker to produce an executable, ar to update a library, or TeX or Makeinfo to format documentation. - Make is not limited to building a package. You can also use Make to control installing or deinstalling a package, generate tags tables for it, or anything else you want to do often enough to make it worth while writing down how to do it.
+	 
+Homepage
+--------
+http://www.gnu.org/software/make
+	 
+System
+------
+- Win32, i.e. MS-Windows 95 / 98 / ME / NT / 2000 / XP / 2003 with msvcrt.dll
+- if msvcrt.dll is not in your Windows/System folder, get it from
+  Microsoft 
+  or by installing Internet Explorer 4.0 or higher
+   
+- libintl3  
+- libiconv2  
+
+Notes
+-----
+- Bugs and questions on this MS-Windows port: gnuwin32@users.sourceforge.net
+
+Package Availability
+--------------------
+- in: http://gnuwin32.sourceforge.net
+Installation
+------------
+
+Sources
+-------
+- make-3.81-src.zip
+
+Compilation
+-----------
+The package has been compiled with GNU auto-tools, GNU make, and Mingw
+(GCC for MS-Windows). Any differences from the original sources are given
+in make-3.81-GnuWin32.diffs in make-3.81-src.zip. Libraries needed
+for compilation can be found at the lines starting with 'LIBS = ' in the
+Makefiles. Usually, these are standard libraries provided with Mingw, or
+libraries from the package itself; 'gw32c' refers to the libgw32c package,
+which provides MS-Windows substitutes or stubs for functions normally found in
+Unix. For more information, see: http://gnuwin32.sourceforge.net/compile.html
+and http://gnuwin32.sourceforge.net/packages/libgw32c.htm.
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--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3n_ek_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3N.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3N4C
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x00400000)
+#set *0x400004 = *0x400004 & 0xFFFFFFFE
+mon reg pc=(0x00400004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3n_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3n_ek_sram.gdb
new file mode 100644
index 0000000..ac5d63a
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3n_ek_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3N.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3s_ek2_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3s_ek2_flash.gdb
new file mode 100644
index 0000000..095a174
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3s_ek2_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3S.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3S4C
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x400000)
+#set *0x400004 = *0x400004 & 0xFFFFFFFE
+mon reg pc=(0x400004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3s_ek2_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3s_ek2_sram.gdb
new file mode 100644
index 0000000..e936ff7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3s_ek2_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3S.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3s_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3s_ek_flash.gdb
new file mode 100644
index 0000000..095a174
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3s_ek_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3S.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3S4C
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x400000)
+#set *0x400004 = *0x400004 & 0xFFFFFFFE
+mon reg pc=(0x400004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3s_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3s_ek_sram.gdb
new file mode 100644
index 0000000..e936ff7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3s_ek_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3S.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3u_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3u_ek_flash.gdb
new file mode 100644
index 0000000..70933c7
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3u_ek_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3U.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3U4E
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1200 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x80000)
+#set *0x80004 = *0x80004 & 0xFFFFFFFE
+mon reg pc=(0x80004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3u_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3u_ek_sram.gdb
new file mode 100644
index 0000000..b658487
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3u_ek_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3U.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1200 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3x_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3x_ek_flash.gdb
new file mode 100644
index 0000000..dc1acb8
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3x_ek_flash.gdb
@@ -0,0 +1,35 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3X.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3X8H
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1a00 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x80000)
+#set *0x80004 = *0x80004 & 0xFFFFFFFE
+mon reg pc=(0x80004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3x_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3x_ek_sram.gdb
new file mode 100644
index 0000000..a3f4293
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam3x_ek_sram.gdb
@@ -0,0 +1,29 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3X.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1a00 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam4s_ek_flash.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam4s_ek_flash.gdb
new file mode 100644
index 0000000..4482476
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam4s_ek_flash.gdb
@@ -0,0 +1,32 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device (Should be AT91SAM4S16C, but it is not available now)
+monitor flash device = AT91SAM4S16C
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral  (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initializing PC and stack pointer
+mon reg sp=(0x400000)
+mon reg pc=(0x400004)
+info reg
+
+# end of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam4s_ek_sram.gdb b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam4s_ek_sram.gdb
new file mode 100644
index 0000000..0834162
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam4s_ek_sram.gdb
@@ -0,0 +1,27 @@
+#*************************************************
+#
+#  Connect to J-Link and debug application in sram.
+#
+
+# define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Load the program
+load
+
+# Reset peripheral  (RSTC_CR)
+set *0x400e1400 = 0xA5000004
+
+# Initializing PC and stack pointer
+mon reg sp=(0x20000000)
+mon reg pc=(0x20000004)
+info reg
+
+# end of 'reset' command
+end
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam_series.mk b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam_series.mk
new file mode 100644
index 0000000..c08a476
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/gcc_atmel/sam_series.mk
@@ -0,0 +1,37 @@
+# ----------------------------------------------------------------------------
+#         ATMEL Microcontroller Software Support 
+# ----------------------------------------------------------------------------
+# Copyright (c) 2010, Atmel Corporation
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following condition is met:
+#
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the disclaimer below.
+#
+# Atmel's name may not be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# ----------------------------------------------------------------------------
+
+# define SAM series
+SAM3N=SAM3N00A SAM3N00B SAM3N0A SAM3N0B SAM3N0C SAM3N1A SAM3N1B SAM3N1C SAM3N2A SAM3N2B SAM3N2C SAM3N4A SAM3N4B SAM3N4C
+SAM3S=SAM3S1A SAM3S1B SAM3S1C SAM3S2A SAM3S2B SAM3S2C SAM3S4A SAM3S4B SAM3S4C
+SAM3SD8=SAM3S8B SAM3S8C SAM3SD8B SAM3SD8C
+SAM3U=SAM3U1C SAM3U1E SAM3U2C SAM3U2E SAM3U4C SAM3U4E
+SAM3XA=SAM3A4C SAM3A8C SAM3X4C SAM3X4E SAM3X8C SAM3X8E SAM3X8H
+SAM4S=SAM4S8B SAM4S8C SAM4S16B SAM4S16C
+
+SAM_SERIES=$(SAM3N) $(SAM3S) $(SAM3SD8) $(SAM3U) $(SAM3XA) $(SAM4S)
diff --git a/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/main.c b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/main.c
new file mode 100644
index 0000000..4d0a1d5
--- /dev/null
+++ b/hardware/digistump/sam/system/CMSIS/Examples/cmsis_example/main.c
@@ -0,0 +1,158 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \brief CMSIS Example
+ * \mainpage CMSIS Example
+ *
+ * \section Purpose
+ *
+ * The cmsis example will help new users get familiar with
+ * basic cmsis utilities of SAM3 and SAM4 microcontrollers.
+ *
+ * The example will execute the following tests:
+ * - The application will flash the LED per second. The second 
+ * is calculated by the standard system tick interface of cmsis.
+ *
+ * \section Requirements
+ *
+ * This package can be used with SAM3 and SAM4 evaluation kits.
+ *
+ * \section Description
+ * The cmsis example will use the system tick of the Cortex-M.
+ *
+ * \section Usage
+ *
+ * -# Build the program and download it into the evaluation board. Please
+ *    refer to the
+ *    
+ *    SAM-BA User Guide, the
+ *    
+ *    GNU-Based Software Development application note or the
+ *    
+ *    IAR EWARM User Guide, depending on the solutions that users choose.
+ *
+ */
+
+#include "sam.h"
+
+#include "conf_board.h"
+
+__INLINE static void delay_ms(uint32_t dw_dly_ticks);
+__INLINE static void led_config(void);
+__INLINE static void led_on(uint32_t dw_led);
+__INLINE static void led_off(uint32_t dw_led);
+
+/* Systick Counter */
+static volatile uint32_t dw_ms_ticks = 0U;
+
+/**
+ * \brief SysTick_Handler.
+ */
+void SysTick_Handler(void)
+{
+	/* Increment counter necessary in delay(). */
+	dw_ms_ticks++;
+}
+
+/**
+ * \brief Delay number of tick Systicks (happens every 1 ms).
+ */
+__INLINE static void delay_ms(uint32_t dw_dly_ticks)
+{
+	uint32_t dw_cur_ticks;
+
+	dw_cur_ticks = dw_ms_ticks;
+	while ((dw_ms_ticks - dw_cur_ticks) < dw_dly_ticks) {
+	}
+}
+
+ /**
+  * \brief Configure LED pins.
+  */
+__INLINE static void led_config(void)
+{
+	/* Set up LED pins. */
+	LED0_PIO->PIO_PER = LED0_MASK;
+	LED0_PIO->PIO_OER = LED0_MASK;
+	LED0_PIO->PIO_PUDR = LED0_MASK;
+}
+
+/**
+ * \brief Switch on LED.
+ */
+__INLINE static void led_on(uint32_t dw_led)
+{
+	/* Turn On LED. */
+	LED0_PIO->PIO_CODR = dw_led;
+}
+
+/**
+ * \brief Switch off LED.
+ */
+__INLINE static void led_off(uint32_t dw_led)
+{
+	/* Turn Off LED. */
+	LED0_PIO->PIO_SODR = dw_led;
+}
+
+/**
+ * \brief Application entry point.
+ *
+ * \return Unused (ANSI-C compatibility).
+ */
+int main(void)
+{
+	/* Initilize the SAM3 system */
+	SystemInit();
+
+	WDT->WDT_MR = WDT_MR_WDDIS;
+
+	/* Set up SysTick Timer for 1 msec interrupts. */
+	if (SysTick_Config(SystemCoreClock / (uint32_t) 1000)) {
+		/* Capture error. */
+		while (1) {
+		}
+	}
+
+	led_config();
+
+	/* Flash the LED. */
+	while (1) {
+		/* Turn on the LED. */
+		led_on(LED0_MASK);
+		/* Delay  1000 Msec. */
+		delay_ms((uint32_t) 1000);
+
+		/* Turn off the LED. */
+		led_off(LED0_MASK);
+		/* Delay  1000 Msec. */
+		delay_ms((uint32_t) 1000);
+	}
+}
diff --git a/hardware/digistump/sam/system/CMSIS/Version 2.10 b/hardware/digistump/sam/system/CMSIS/Version 2.10
new file mode 100644
index 0000000..e69de29
diff --git a/hardware/digistump/sam/system/libsam/build_gcc/Makefile b/hardware/digistump/sam/system/libsam/build_gcc/Makefile
new file mode 100644
index 0000000..a04d3ca
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/build_gcc/Makefile
@@ -0,0 +1,130 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Makefile for compiling libchip
+
+SUBMAKE_OPTIONS=--no-builtin-rules --no-builtin-variables --no-print-directory
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+
+# libsam_sam3s4c_gcc_rel.a libsam_sam3u4e_gcc_rel.a libsam_sam3x8e_gcc_rel.a libsam_sam3x8h_gcc_rel.a
+all: libsam_sam3s4c_gcc_dbg.a libsam_sam3u4e_gcc_dbg.a libsam_sam3x8e_gcc_dbg.a libsam_sam3x8h_gcc_dbg.a arduino_due_x
+
+.PHONY: arduino_due_u
+arduino_due_u:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Making $@
+	@echo ---
+	@$(MAKE) CHIP=__SAM3U4E__ $(SUBMAKE_OPTIONS) OUTPUT_BIN=../../../variants/arduino_due_u -f sam3.mk
+	@echo ------------------------------------------------------------------------------------
+
+.PHONY: arduino_due_x
+arduino_due_x:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Making $@
+	@echo ---
+	@$(MAKE) CHIP=__SAM3X8E__ $(SUBMAKE_OPTIONS) OUTPUT_BIN=../../../variants/arduino_due_x -f sam3.mk
+	@echo ------------------------------------------------------------------------------------
+
+.PHONY: libsam_sam3s4c_gcc_dbg.a
+libsam_sam3s4c_gcc_dbg.a:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Making $@
+	@echo ---
+	@$(MAKE) CHIP=__SAM3S4C__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
+	@echo ------------------------------------------------------------------------------------
+
+.PHONY: libsam_sam3s4c_gcc_rel.a
+libsam_sam3s4c_gcc_rel.a:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Making $@
+	@echo ---
+	@$(MAKE) CHIP=__SAM3S4C__ $(SUBMAKE_OPTIONS) -f sam3.mk
+	@echo ------------------------------------------------------------------------------------
+
+.PHONY: libsam_sam3u4e_gcc_dbg.a
+libsam_sam3u4e_gcc_dbg.a:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Making $@
+	@echo ---
+	@$(MAKE) CHIP=__SAM3U4E__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
+	@echo ------------------------------------------------------------------------------------
+
+.PHONY: libsam_sam3u4e_gcc_rel.a
+libsam_sam3u4e_gcc_rel.a:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Making $@
+	@echo ---
+	@$(MAKE) CHIP=__SAM3U4E__ $(SUBMAKE_OPTIONS) -f sam3.mk
+	@echo ------------------------------------------------------------------------------------
+
+.PHONY: libsam_sam3x8e_gcc_dbg.a
+libsam_sam3x8e_gcc_dbg.a:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Making $@
+	@echo ---
+	@$(MAKE) CHIP=__SAM3X8E__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
+	@echo ------------------------------------------------------------------------------------
+
+.PHONY: libsam_sam3x8e_gcc_rel.a
+libsam_sam3x8e_gcc_rel.a:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Making $@
+	@echo ---
+	@$(MAKE) CHIP=__SAM3X8E__ $(SUBMAKE_OPTIONS) -f sam3.mk
+	@echo ------------------------------------------------------------------------------------
+
+.PHONY: libsam_sam3x8h_gcc_dbg.a
+libsam_sam3x8h_gcc_dbg.a:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Making $@
+	@echo ---
+	@$(MAKE) CHIP=__SAM3X8H__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
+	@echo ------------------------------------------------------------------------------------
+
+.PHONY: libsam_sam3x8h_gcc_rel.a
+libsam_sam3x8h_gcc_rel.a:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Making $@
+	@echo ---
+	@$(MAKE) CHIP=__SAM3X8H__ $(SUBMAKE_OPTIONS) -f sam3.mk
+	@echo ------------------------------------------------------------------------------------
+
+.PHONY: clean
+clean:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Cleaning sam3s4c release and debug
+	@$(MAKE) CHIP=__SAM3S4C__ $(SUBMAKE_OPTIONS) -f sam3.mk $@
+	@$(MAKE) CHIP=__SAM3S4C__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk $@
+
+	@echo --- Cleaning sam3u4e release and debug
+	@$(MAKE) CHIP=__SAM3U4E__ $(SUBMAKE_OPTIONS) -f sam3.mk $@
+	@$(MAKE) CHIP=__SAM3U4E__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk $@
+
+	@echo --- Cleaning sam3x8e release and debug
+	@$(MAKE) CHIP=__SAM3X8E__ $(SUBMAKE_OPTIONS) -f sam3.mk $@
+	@$(MAKE) CHIP=__SAM3X8E__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk $@
+
+	@echo --- Cleaning sam3x8h release and debug
+	@$(MAKE) CHIP=__SAM3X8H__ $(SUBMAKE_OPTIONS) -f sam3.mk $@
+	@$(MAKE) CHIP=__SAM3X8H__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk $@
+	@echo ------------------------------------------------------------------------------------
+
+
diff --git a/hardware/digistump/sam/system/libsam/build_gcc/debug.mk b/hardware/digistump/sam/system/libsam/build_gcc/debug.mk
new file mode 100644
index 0000000..d071674
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/build_gcc/debug.mk
@@ -0,0 +1,25 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -g -O0 -DDEBUG
diff --git a/hardware/digistump/sam/system/libsam/build_gcc/gcc.mk b/hardware/digistump/sam/system/libsam/build_gcc/gcc.mk
new file mode 100644
index 0000000..c65fbd7
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/build_gcc/gcc.mk
@@ -0,0 +1,63 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Tool suffix when cross-compiling
+CROSS_COMPILE = $(ARM_GCC_TOOLCHAIN)/arm-none-eabi-
+
+# Compilation tools
+AR = $(CROSS_COMPILE)ar
+CC = $(CROSS_COMPILE)gcc
+AS = $(CROSS_COMPILE)as
+NM = $(CROSS_COMPILE)nm
+ifeq ($(OS),Windows_NT)
+RM=cs-rm -Rf
+#RM=del /s /f
+else
+RM=rm -Rf
+endif
+
+SEP=/
+
+# ---------------------------------------------------------------------------------------
+# C Flags
+
+CFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
+CFLAGS += -Werror-implicit-function-declaration -Wmain -Wparentheses
+CFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CFLAGS += -Wshadow -Wpointer-arith -Wbad-function-cast -Wwrite-strings
+CFLAGS += -Wsign-compare -Waggregate-return -Wstrict-prototypes
+CFLAGS += -Wmissing-prototypes -Wmissing-declarations
+CFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CFLAGS += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long
+CFLAGS += -Wunreachable-code
+CFLAGS += -Wcast-align
+#CFLAGS += -Wmissing-noreturn
+#CFLAGS += -Wconversion
+
+# To reduce application size use only integer printf function.
+CFLAGS += -Dprintf=iprintf
+
+CFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections -fdata-sections -std=c99
+CFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP)
+
+
+# ---------------------------------------------------------------------------------------
+# ASM Flags
+
+ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -a -g $(INCLUDES)
diff --git a/hardware/digistump/sam/system/libsam/build_gcc/release.mk b/hardware/digistump/sam/system/libsam/build_gcc/release.mk
new file mode 100644
index 0000000..0d15157
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/build_gcc/release.mk
@@ -0,0 +1,25 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -Os
diff --git a/hardware/digistump/sam/system/libsam/build_gcc/sam3.mk b/hardware/digistump/sam/system/libsam/build_gcc/sam3.mk
new file mode 100644
index 0000000..17d95ea
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/build_gcc/sam3.mk
@@ -0,0 +1,189 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Makefile for compiling libchip
+.SUFFIXES: .o .a .c .s
+SUB_MAKEFILES=debug.mk gcc.mk release.mk win.mk sam3s.mk
+
+LIBNAME=libsam
+TOOLCHAIN=gcc
+
+ifeq ($(OS),Windows_NT)
+DEV_NUL=NUL
+else
+DEV_NUL=/dev/null
+endif
+
+ifeq ($(CHIP),)
+$(error CHIP not defined)
+endif
+
+#CHIP_NAME=$(subst __,,$(CHIP))
+#CHIP_NAME=$(subst __,,$(call lc,$(CHIP)))
+
+#-------------------------------------------------------------------------------
+# Path
+#-------------------------------------------------------------------------------
+
+# Output directories
+OUTPUT_BIN = ../../../cores/arduino
+
+# Libraries
+PROJECT_BASE_PATH = ..
+CMSIS_ROOT_PATH = $(PROJECT_BASE_PATH)/../CMSIS
+
+ifeq ($(CHIP), __SAM3S4C__)
+CHIP_NAME=sam3s4c
+CHIP_SERIE=sam3s
+else ifeq ($(CHIP), __SAM3U4E__)
+CHIP_NAME=sam3u4e
+CHIP_SERIE=sam3u
+else ifeq ($(CHIP), __SAM3N4C__)
+CHIP_NAME=sam3n4c
+CHIP_SERIE=sam3n
+else ifeq ($(CHIP), __SAM3X8E__)
+CHIP_NAME=sam3x8e
+CHIP_SERIE=sam3xa
+else ifeq ($(CHIP), __SAM3X8H__)
+CHIP_NAME=sam3x8h
+CHIP_SERIE=sam3xa
+else
+endif
+
+CMSIS_ARM_PATH=$(CMSIS_ROOT_PATH)/CMSIS/Include
+CMSIS_ATMEL_PATH=$(CMSIS_ROOT_PATH)/Device/ATMEL
+CMSIS_CHIP_PATH=$(CMSIS_ROOT_PATH)/Device/ATMEL/$(CHIP_SERIE)
+
+#-------------------------------------------------------------------------------
+# Files
+#-------------------------------------------------------------------------------
+
+vpath %.h $(PROJECT_BASE_PATH)/include $(CMSIS_ATMEL_PATH) $(CMSIS_CHIP_PATH)/include
+vpath %.c $(PROJECT_BASE_PATH)/source $(CMSIS_ARM_PATH) $(CMSIS_CHIP_PATH)/source
+
+VPATH+=$(PROJECT_BASE_PATH)/source
+VPATH+=$(CMSIS_ARM_PATH)
+VPATH+=$(CMSIS_CHIP_PATH)/include
+VPATH+=$(CMSIS_CHIP_PATH)/source/
+VPATH+=$(CMSIS_CHIP_PATH)/source/gcc
+
+INCLUDES = -I$(PROJECT_BASE_PATH)
+INCLUDES += -I$(PROJECT_BASE_PATH)/include
+INCLUDES += -I$(CMSIS_ARM_PATH)
+INCLUDES += -I$(CMSIS_ATMEL_PATH)
+INCLUDES += -I$(CMSIS_CHIP_PATH)/include
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+include debug.mk
+else
+include release.mk
+endif
+
+#-------------------------------------------------------------------------------
+# Tools
+#-------------------------------------------------------------------------------
+
+include $(TOOLCHAIN).mk
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+OUTPUT_OBJ=debug
+OUTPUT_LIB=$(LIBNAME)_$(CHIP_NAME)_$(TOOLCHAIN)_dbg.a
+else
+OUTPUT_OBJ=release
+OUTPUT_LIB=$(LIBNAME)_$(CHIP_NAME)_$(TOOLCHAIN)_rel.a
+endif
+
+OUTPUT_PATH=$(OUTPUT_OBJ)_$(CHIP_NAME)
+
+#-------------------------------------------------------------------------------
+# C source files and objects
+#-------------------------------------------------------------------------------
+C_SRC=$(wildcard $(PROJECT_BASE_PATH)/source/*.c)
+C_SRC+=$(wildcard $(CMSIS_CHIP_PATH)/source/*.c)
+C_SRC+=$(wildcard $(CMSIS_CHIP_PATH)/source/gcc/*.c)
+
+C_OBJ_TEMP=$(patsubst %.c, %.o, $(notdir $(C_SRC)))
+
+# during development, remove some files
+C_OBJ_FILTER=
+
+C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Assembler source files and objects
+#-------------------------------------------------------------------------------
+A_SRC=$(wildcard $(PROJECT_BASE_PATH)/source/*.s)
+
+A_OBJ_TEMP=$(patsubst %.s, %.o, $(notdir $(A_SRC)))
+
+# during development, remove some files
+A_OBJ_FILTER=
+
+A_OBJ=$(filter-out $(A_OBJ_FILTER), $(A_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+all: $(CHIP)
+
+$(CHIP): create_output $(OUTPUT_LIB)
+
+.PHONY: create_output
+create_output:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Preparing $(CHIP) files $(OUTPUT_PATH) to $(OUTPUT_BIN)
+#	@echo -------------------------
+#	@echo *$(C_SRC)
+#	@echo -------------------------
+#	@echo *$(C_OBJ)
+#	@echo -------------------------
+#	@echo *$(addprefix $(OUTPUT_PATH)/, $(C_OBJ))
+#	@echo -------------------------
+#	@echo *$(A_SRC)
+#	@echo -------------------------
+
+	-@mkdir $(subst /,$(SEP),$(OUTPUT_BIN)) 1>$(DEV_NUL) 2>&1
+	-@mkdir $(OUTPUT_PATH) 1>$(DEV_NUL) 2>&1
+	@echo ------------------------------------------------------------------------------------
+
+$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: %.c
+#	"$(CC)" -v -c $(CFLAGS) -Wa,aln=$(subst .o,.s,$@) $< -o $@
+	@"$(CC)" -c $(CFLAGS) $< -o $@
+#	"$(CC)" -c $(CFLAGS) $< -o $@
+
+$(addprefix $(OUTPUT_PATH)/,$(A_OBJ)): $(OUTPUT_PATH)/%.o: %.s
+	@"$(AS)" -c $(ASFLAGS) $< -o $@
+
+$(OUTPUT_LIB): $(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(A_OBJ))
+	@"$(AR)" -r "$(OUTPUT_BIN)/$@" $^
+	@"$(NM)" "$(OUTPUT_BIN)/$@" > "$(OUTPUT_BIN)/$@.txt"
+
+.PHONY: clean
+clean:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Cleaning $(CHIP) files $(OUTPUT_PATH) $(subst /,$(SEP),$(OUTPUT_BIN)/$(OUTPUT_LIB))
+	-@$(RM) $(OUTPUT_PATH) 1>$(DEV_NUL) 2>&1
+	-@$(RM) $(subst /,$(SEP),$(OUTPUT_BIN)/$(OUTPUT_LIB)) 1>$(DEV_NUL) 2>&1
+	-@$(RM) $(subst /,$(SEP),$(OUTPUT_BIN)/$(OUTPUT_LIB)).txt 1>$(DEV_NUL) 2>&1
+	@echo ------------------------------------------------------------------------------------
+
+# dependencies
+$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: $(PROJECT_BASE_PATH)/chip.h $(wildcard $(PROJECT_BASE_PATH)/include/*.h) $(wildcard $(CMSIS_BASE_PATH)/*.h)
+
diff --git a/hardware/digistump/sam/system/libsam/build_iar/libsam.ewd b/hardware/digistump/sam/system/libsam/build_iar/libsam.ewd
new file mode 100644
index 0000000..2570bbc
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/build_iar/libsam.ewd
@@ -0,0 +1,3447 @@
+
+
+
+  2
+  
+    Debug
+    
+      ARM
+    
+    1
+    
+      C-SPY
+      2
+      
+        22
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ARMSIM_ID
+      2
+      
+        1
+        1
+        1
+        
+        
+        
+        
+      
+    
+    
+      ANGEL_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      GDBSERVER_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARROM_ID
+      2
+      
+        1
+        1
+        1
+        
+        
+        
+        
+        
+      
+    
+    
+      JLINK_ID
+      2
+      
+        13
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      LMIFTDI_ID
+      2
+      
+        2
+        1
+        1
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      MACRAIGOR_ID
+      2
+      
+        3
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      PEMICRO_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      RDI_ID
+      2
+      
+        2
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      STLINK_ID
+      2
+      
+        2
+        1
+        1
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      THIRDPARTY_ID
+      2
+      
+        0
+        1
+        1
+        
+        
+        
+        
+      
+    
+    
+      
+        $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+        0
+      
+      
+        $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+        0
+      
+      
+        $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+        1
+      
+      
+        $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+        0
+      
+      
+        $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin
+        1
+      
+    
+  
+  
+    Release
+    
+      ARM
+    
+    0
+    
+      C-SPY
+      2
+      
+        22
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      ARMSIM_ID
+      2
+      
+        1
+        1
+        0
+        
+        
+        
+        
+      
+    
+    
+      ANGEL_ID
+      2
+      
+        0
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      GDBSERVER_ID
+      2
+      
+        0
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      IARROM_ID
+      2
+      
+        1
+        1
+        0
+        
+        
+        
+        
+        
+      
+    
+    
+      JLINK_ID
+      2
+      
+        13
+        1
+        0
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
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+      0
+      
+    
+  
+  
+    cmsis
+    
+      sam3s
+      
+        include
+        
+          component
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\acc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\adc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\chipid.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\crccu.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\dacc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\efc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\gpbr.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\hsmci.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\matrix.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\pdc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\pio.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\pmc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\pwm.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\rstc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\rtc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\rtt.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\smc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\spi.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\ssc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\supc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\tc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\twi.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\uart.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\udp.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\usart.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\component\wdt.h
+          
+        
+        
+          instance
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\acc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\adc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\chipid.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\crccu.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\dacc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\efc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\gpbr.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\hsmci.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\matrix.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\pioa.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\piob.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\pioc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\pmc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\pwm.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\rstc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\rtc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\rtt.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\smc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\spi.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\ssc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\supc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\tc0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\tc1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\twi0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\twi1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\uart0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\uart1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\udp.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\usart0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\usart1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\instance\wdt.h
+          
+        
+        
+          pio
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s1a.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s1b.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s1c.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s2a.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s2b.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s2c.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s4a.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s4b.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\include\pio\sam3s4c.h
+          
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s1a.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s1b.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s1c.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s2a.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s2b.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s2c.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s4a.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s4b.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3s\include\sam3s4c.h
+        
+      
+      
+        source
+        
+          templates
+          
+            iar
+            
+              $PROJ_DIR$\..\cmsis\sam3s\source\templates\iar\startup_sam3s.c
+            
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\source\templates\exceptions.c
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\source\templates\exceptions.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\source\templates\system_sam3s.c
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3s\source\templates\system_sam3s.h
+          
+        
+      
+    
+    
+      sam3u
+      
+        Debug
+      
+      
+        include
+        
+          component
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\adc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\adc12b.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\chipid.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\dmac.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\efc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\gpbr.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\hsmci.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\matrix.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\pdc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\pio.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\pmc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\pwm.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\rstc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\rtc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\rtt.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\smc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\spi.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\ssc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\supc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\tc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\twi.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\uart.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\udphs.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\usart.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\component\wdt.h
+          
+        
+        
+          instance
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\adc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\adc12b.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\chipid.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\dmac.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\efc0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\efc1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\gpbr.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\hsmci.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\matrix.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\pioa.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\piob.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\pioc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\pmc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\pwm.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\rstc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\rtc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\rtt.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\smc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\spi.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\ssc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\supc.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\tc0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\twi0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\twi1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\uart.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\udphs.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\usart0.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\usart1.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\usart2.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\usart3.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\instance\wdt.h
+          
+        
+        
+          pio
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\pio\sam3u1c.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\pio\sam3u1e.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\pio\sam3u2c.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\pio\sam3u2e.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\pio\sam3u4c.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\include\pio\sam3u4e.h
+          
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u1c.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u1e.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u2c.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u2e.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u4c.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\sam3u4e.h
+        
+        
+          $PROJ_DIR$\..\cmsis\sam3u\include\system_sam3u.h
+        
+      
+      
+        source
+        
+          templates
+          
+            iar
+            
+              $PROJ_DIR$\..\cmsis\sam3u\source\templates\iar\startup_sam3u.c
+            
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\source\templates\exceptions.c
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\source\templates\exceptions.h
+          
+          
+            $PROJ_DIR$\..\cmsis\sam3u\source\templates\system_sam3u.c
+          
+        
+      
+    
+  
+  
+    include
+    
+      $PROJ_DIR$\..\include\adc.h
+    
+    
+      $PROJ_DIR$\..\include\pio.h
+    
+    
+      $PROJ_DIR$\..\include\pio_it.h
+    
+    
+      $PROJ_DIR$\..\include\pmc.h
+    
+    
+      $PROJ_DIR$\..\include\pwmc.h
+    
+    
+      $PROJ_DIR$\..\include\rtc.h
+    
+    
+      $PROJ_DIR$\..\include\rtt.h
+    
+    
+      $PROJ_DIR$\..\include\sam3.h
+    
+    
+      $PROJ_DIR$\..\include\spi.h
+    
+    
+      $PROJ_DIR$\..\include\tc.h
+    
+    
+      $PROJ_DIR$\..\include\timetick.h
+    
+    
+      $PROJ_DIR$\..\include\twi.h
+    
+    
+      $PROJ_DIR$\..\include\usart.h
+    
+    
+      $PROJ_DIR$\..\include\wdt.h
+    
+  
+  
+    source
+    
+      $PROJ_DIR$\..\source\adc.c
+    
+    
+      $PROJ_DIR$\..\source\pio.c
+    
+    
+      $PROJ_DIR$\..\source\pio_it.c
+      
+        Debug
+        Debug_sam3s
+      
+    
+    
+      $PROJ_DIR$\..\source\pmc.c
+    
+    
+      $PROJ_DIR$\..\source\pwmc.c
+    
+    
+      $PROJ_DIR$\..\source\rtc.c
+    
+    
+      $PROJ_DIR$\..\source\rtt.c
+    
+    
+      $PROJ_DIR$\..\source\spi.c
+    
+    
+      $PROJ_DIR$\..\source\tc.c
+    
+    
+      $PROJ_DIR$\..\source\timetick.c
+    
+    
+      $PROJ_DIR$\..\source\twi.c
+    
+    
+      $PROJ_DIR$\..\source\usart.c
+    
+    
+      $PROJ_DIR$\..\source\wdt.c
+    
+  
+  
+    $PROJ_DIR$\..\chip.h
+  
+
+
+
diff --git a/hardware/digistump/sam/system/libsam/build_iar/libsam.eww b/hardware/digistump/sam/system/libsam/build_iar/libsam.eww
new file mode 100644
index 0000000..1e4c9ea
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/build_iar/libsam.eww
@@ -0,0 +1,39 @@
+
+
+
+  
+    $WS_DIR$\..\..\..\cores\sam\build_iar\libarduino.ewp
+  
+  
+    $WS_DIR$\libsam.ewp
+  
+  
+    $WS_DIR$\..\..\..\variants\sam3s_ek\build_iar\libvariant_sam3s_ek.ewp
+  
+  
+    $WS_DIR$\..\..\..\cores\sam\validation\build_iar\test.ewp
+  
+  
+    
+      all_debug_sam3s
+      
+        libsam
+        Debug
+      
+      
+        libarduino
+        Debug
+      
+      
+        libsam3s_ek
+        Debug
+      
+      
+        test
+        Debug
+      
+    
+  
+
+
+
diff --git a/hardware/digistump/sam/system/libsam/chip.h b/hardware/digistump/sam/system/libsam/chip.h
new file mode 100644
index 0000000..13bc36e
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/chip.h
@@ -0,0 +1,77 @@
+/*
+  Copyright (c) 2011 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef _LIB_SAM_
+#define _LIB_SAM_
+
+/*
+ * Core and peripherals registers definitions
+ */
+#include "sam.h"
+
+/* Define attribute */
+#if defined (  __GNUC__  ) /* GCC CS3 */
+    #define WEAK __attribute__ ((weak))
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
+    #define WEAK __weak
+#endif
+
+/* Define NO_INIT attribute */
+#if defined (  __GNUC__  )
+    #define NO_INIT
+#elif defined ( __ICCARM__ )
+    #define NO_INIT __no_init
+#endif
+
+/*
+ * Peripherals
+ */
+#include "include/adc.h"
+#if (SAM3XA_SERIES) || (SAM3N_SERIES) || (SAM3S_SERIES)
+#include "include/dacc.h"
+#endif // (SAM3XA_SERIES) || (SAM3N_SERIES) || (SAM3S_SERIES)
+
+#include "include/interrupt_sam_nvic.h"
+#include "include/efc.h"
+#include "include/gpbr.h"
+#include "include/pio.h"
+#include "include/pmc.h"
+#include "include/pwmc.h"
+#include "include/rstc.h"
+#include "include/rtc.h"
+#include "include/rtt.h"
+#include "include/spi.h"
+#include "include/ssc.h"
+#include "include/tc.h"
+#include "include/twi.h"
+#include "include/usart.h"
+#include "include/wdt.h"
+
+#include "include/timetick.h"
+#include "include/USB_device.h"
+#include "include/USB_host.h"
+
+#if (SAM3XA_SERIES)
+#include "include/can.h"
+#include "include/emac.h"
+#include "include/trng.h"
+#include "include/uotghs_device.h"
+#include "include/uotghs_host.h"
+#endif /* (SAM3XA_SERIES) */
+
+#endif /* _LIB_SAM_ */
diff --git a/hardware/digistump/sam/system/libsam/include/USB_device.h b/hardware/digistump/sam/system/libsam/include/USB_device.h
new file mode 100644
index 0000000..5beffac
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/USB_device.h
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef USB_DEVICE_H_INCLUDED
+#define USB_DEVICE_H_INCLUDED
+
+#include 
+
+extern void UDD_WaitIN(void);
+extern void UDD_WaitOUT(void);
+extern void UDD_ClearIN(void);
+extern void UDD_ClearOUT(void);
+extern uint32_t UDD_WaitForINOrOUT(void);
+extern void UDD_ClearRxFlag(unsigned char bEndpoint);
+extern uint32_t UDD_ReceivedSetupInt(void);
+extern void UDD_ClearSetupInt(void);
+extern uint32_t UDD_ReadWriteAllowed(uint32_t ep);
+extern uint32_t UDD_FifoByteCount(uint32_t ep);
+extern uint8_t UDD_FifoFree(void);
+extern void UDD_ReleaseRX(uint32_t ep);
+extern void UDD_ReleaseTX(uint32_t ep);
+extern uint8_t UDD_FrameNumber(void);
+extern uint8_t UDD_GetConfiguration(void);
+
+extern uint32_t UDD_Send(uint32_t ep, const void* data, uint32_t len);
+extern void UDD_Send8(uint32_t ep,  uint8_t data );
+extern uint8_t UDD_Recv8(uint32_t ep);
+extern void UDD_Recv(uint32_t ep, uint8_t* data, uint32_t len);
+
+extern void UDD_InitEndpoints(const uint32_t* eps_table, const uint32_t ul_eps_table_size);
+extern void UDD_InitControl(int end);
+extern uint32_t UDD_Init(void);
+extern void UDD_InitEP( uint32_t ul_ep, uint32_t ul_ep_cfg );
+
+extern void UDD_Attach(void);
+extern void UDD_Detach(void);
+
+extern void UDD_SetStack(void (*pf_isr)(void));
+extern void UDD_SetAddress(uint32_t addr);
+extern void UDD_Stall(void);
+extern uint32_t UDD_GetFrameNumber(void);
+
+/*! \name Usual Types
+ */
+
+//! @{
+
+typedef unsigned char           Bool; //!< Boolean.
+#ifndef __cplusplus
+#if !defined(__bool_true_false_are_defined)
+typedef unsigned char           bool; //!< Boolean.
+#endif
+#endif
+typedef int8_t                  S8;  //!< 8-bit signed integer.
+typedef uint8_t                 U8;  //!< 8-bit unsigned integer.
+typedef int16_t                 S16;  //!< 16-bit signed integer.
+typedef uint16_t                U16;  //!< 16-bit unsigned integer.
+typedef uint16_t                le16_t;
+typedef uint16_t                be16_t;
+typedef int32_t                 S32;  //!< 32-bit signed integer.
+typedef uint32_t                U32;  //!< 32-bit unsigned integer.
+typedef uint32_t                le32_t;
+typedef uint32_t                be32_t;
+typedef int64_t                 S64;  //!< 64-bit signed integer.
+typedef uint64_t                U64;  //!< 64-bit unsigned integer.
+typedef float                   F32;  //!< 32-bit floating-point number.
+typedef double                  F64;  //!< 64-bit floating-point number.
+typedef uint32_t                iram_size_t;
+
+//! @}
+
+/*! \name Bit-Field Handling
+ */
+//! @{
+
+/*! \brief Reads the bits of a value specified by a given bit-mask.
+ *
+ * \param value Value to read bits from.
+ * \param mask  Bit-mask indicating bits to read.
+ *
+ * \return Read bits.
+ */
+#define Rd_bits( value, mask)        ((value) & (mask))
+
+/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue  C lvalue to write bits to.
+ * \param mask    Bit-mask indicating bits to write.
+ * \param bits    Bits to write.
+ *
+ * \return Resulting value with written bits.
+ */
+#define Wr_bits(lvalue, mask, bits)  ((lvalue) = ((lvalue) & ~(mask)) |\
+                                                 ((bits  ) &  (mask)))
+
+/*! \brief Tests the bits of a value specified by a given bit-mask.
+ *
+ * \param value Value of which to test bits.
+ * \param mask  Bit-mask indicating bits to test.
+ *
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.
+ */
+#define Tst_bits( value, mask)  (Rd_bits(value, mask) != 0)
+
+/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue  C lvalue of which to clear bits.
+ * \param mask    Bit-mask indicating bits to clear.
+ *
+ * \return Resulting value with cleared bits.
+ */
+#define Clr_bits(lvalue, mask)  ((lvalue) &= ~(mask))
+
+/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue  C lvalue of which to set bits.
+ * \param mask    Bit-mask indicating bits to set.
+ *
+ * \return Resulting value with set bits.
+ */
+#define Set_bits(lvalue, mask)  ((lvalue) |=  (mask))
+
+/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue  C lvalue of which to toggle bits.
+ * \param mask    Bit-mask indicating bits to toggle.
+ *
+ * \return Resulting value with toggled bits.
+ */
+#define Tgl_bits(lvalue, mask)  ((lvalue) ^=  (mask))
+
+/*! \brief Reads the bit-field of a value specified by a given bit-mask.
+ *
+ * \param value Value to read a bit-field from.
+ * \param mask  Bit-mask indicating the bit-field to read.
+ *
+ * \return Read bit-field.
+ */
+#define Rd_bitfield( value, mask)           (Rd_bits( value, mask) >> ctz(mask))
+
+/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue    C lvalue to write a bit-field to.
+ * \param mask      Bit-mask indicating the bit-field to write.
+ * \param bitfield  Bit-field to write.
+ *
+ * \return Resulting value with written bit-field.
+ */
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))
+
+//! @}
+
+/*! \name Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
+ *
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
+ * equivalent to writing U32.
+ */
+
+//! @{
+
+#define TPASTE2( a, b)                            a##b
+#define TPASTE3( a, b, c)                         a##b##c
+#define TPASTE4( a, b, c, d)                      a##b##c##d
+#define TPASTE5( a, b, c, d, e)                   a##b##c##d##e
+#define TPASTE6( a, b, c, d, e, f)                a##b##c##d##e##f
+#define TPASTE7( a, b, c, d, e, f, g)             a##b##c##d##e##f##g
+#define TPASTE8( a, b, c, d, e, f, g, h)          a##b##c##d##e##f##g##h
+#define TPASTE9( a, b, c, d, e, f, g, h, i)       a##b##c##d##e##f##g##h##i
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j)    a##b##c##d##e##f##g##h##i##j
+
+//! @}
+
+/*! \name Absolute Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
+ *
+ * No restriction of use if the tokens are \#defined.
+ *
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
+ * as 32 is equivalent to writing U32.
+ */
+
+//! @{
+
+#define ATPASTE2( a, b)                           TPASTE2( a, b)
+#define ATPASTE3( a, b, c)                        TPASTE3( a, b, c)
+#define ATPASTE4( a, b, c, d)                     TPASTE4( a, b, c, d)
+#define ATPASTE5( a, b, c, d, e)                  TPASTE5( a, b, c, d, e)
+#define ATPASTE6( a, b, c, d, e, f)               TPASTE6( a, b, c, d, e, f)
+#define ATPASTE7( a, b, c, d, e, f, g)            TPASTE7( a, b, c, d, e, f, g)
+#define ATPASTE8( a, b, c, d, e, f, g, h)         TPASTE8( a, b, c, d, e, f, g, h)
+#define ATPASTE9( a, b, c, d, e, f, g, h, i)      TPASTE9( a, b, c, d, e, f, g, h, i)
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j)   TPASTE10(a, b, c, d, e, f, g, h, i, j)
+
+//! @}
+
+/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param u Value of which to count the trailing zero bits.
+ *
+ * \return The count of trailing zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#   define ctz(u)              __builtin_ctz(u)
+#else
+#   define ctz(u)              ((u) & (1ul <<  0) ?  0 : \
+                                (u) & (1ul <<  1) ?  1 : \
+                                (u) & (1ul <<  2) ?  2 : \
+                                (u) & (1ul <<  3) ?  3 : \
+                                (u) & (1ul <<  4) ?  4 : \
+                                (u) & (1ul <<  5) ?  5 : \
+                                (u) & (1ul <<  6) ?  6 : \
+                                (u) & (1ul <<  7) ?  7 : \
+                                (u) & (1ul <<  8) ?  8 : \
+                                (u) & (1ul <<  9) ?  9 : \
+                                (u) & (1ul << 10) ? 10 : \
+                                (u) & (1ul << 11) ? 11 : \
+                                (u) & (1ul << 12) ? 12 : \
+                                (u) & (1ul << 13) ? 13 : \
+                                (u) & (1ul << 14) ? 14 : \
+                                (u) & (1ul << 15) ? 15 : \
+                                (u) & (1ul << 16) ? 16 : \
+                                (u) & (1ul << 17) ? 17 : \
+                                (u) & (1ul << 18) ? 18 : \
+                                (u) & (1ul << 19) ? 19 : \
+                                (u) & (1ul << 20) ? 20 : \
+                                (u) & (1ul << 21) ? 21 : \
+                                (u) & (1ul << 22) ? 22 : \
+                                (u) & (1ul << 23) ? 23 : \
+                                (u) & (1ul << 24) ? 24 : \
+                                (u) & (1ul << 25) ? 25 : \
+                                (u) & (1ul << 26) ? 26 : \
+                                (u) & (1ul << 27) ? 27 : \
+                                (u) & (1ul << 28) ? 28 : \
+                                (u) & (1ul << 29) ? 29 : \
+                                (u) & (1ul << 30) ? 30 : \
+                                (u) & (1ul << 31) ? 31 : \
+                                32)
+#endif
+
+/*! \name Zero-Bit Counting
+ *
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when
+ * applied to constant expressions (values known at compile time), so they are
+ * more optimized than the use of the corresponding assembly instructions and
+ * they can be used as constant expressions e.g. to initialize objects having
+ * static storage duration, and like the corresponding assembly instructions
+ * when applied to non-constant expressions (values unknown at compile time), so
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz
+ * ensure a possible and optimized behavior for both constant and non-constant
+ * expressions.
+ */
+//! @{
+
+/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param u Value of which to count the leading zero bits.
+ *
+ * \return The count of leading zero bits in \a u.
+ */
+#if (defined __GNUC__) || (defined __CC_ARM)
+#   define clz(u)              __builtin_clz(u)
+#elif (defined __ICCARM__)
+#   define clz(u)              __CLZ(u)
+#else
+#   define clz(u)              (((u) == 0)          ? 32 : \
+                                ((u) & (1ul << 31)) ?  0 : \
+                                ((u) & (1ul << 30)) ?  1 : \
+                                ((u) & (1ul << 29)) ?  2 : \
+                                ((u) & (1ul << 28)) ?  3 : \
+                                ((u) & (1ul << 27)) ?  4 : \
+                                ((u) & (1ul << 26)) ?  5 : \
+                                ((u) & (1ul << 25)) ?  6 : \
+                                ((u) & (1ul << 24)) ?  7 : \
+                                ((u) & (1ul << 23)) ?  8 : \
+                                ((u) & (1ul << 22)) ?  9 : \
+                                ((u) & (1ul << 21)) ? 10 : \
+                                ((u) & (1ul << 20)) ? 11 : \
+                                ((u) & (1ul << 19)) ? 12 : \
+                                ((u) & (1ul << 18)) ? 13 : \
+                                ((u) & (1ul << 17)) ? 14 : \
+                                ((u) & (1ul << 16)) ? 15 : \
+                                ((u) & (1ul << 15)) ? 16 : \
+                                ((u) & (1ul << 14)) ? 17 : \
+                                ((u) & (1ul << 13)) ? 18 : \
+                                ((u) & (1ul << 12)) ? 19 : \
+                                ((u) & (1ul << 11)) ? 20 : \
+                                ((u) & (1ul << 10)) ? 21 : \
+                                ((u) & (1ul <<  9)) ? 22 : \
+                                ((u) & (1ul <<  8)) ? 23 : \
+                                ((u) & (1ul <<  7)) ? 24 : \
+                                ((u) & (1ul <<  6)) ? 25 : \
+                                ((u) & (1ul <<  5)) ? 26 : \
+                                ((u) & (1ul <<  4)) ? 27 : \
+                                ((u) & (1ul <<  3)) ? 28 : \
+                                ((u) & (1ul <<  2)) ? 29 : \
+                                ((u) & (1ul <<  1)) ? 30 : \
+                                31)
+#endif
+
+/*! \name Mathematics
+ *
+ * The same considerations as for clz and ctz apply here but GCC does not
+ * provide built-in functions to access the assembly instructions abs, min and
+ * max and it does not produce them by itself in most cases, so two sets of
+ * macros are defined here:
+ *   - Abs, Min and Max to apply to constant expressions (values known at
+ *     compile time);
+ *   - abs, min and max to apply to non-constant expressions (values unknown at
+ *     compile time), abs is found in stdlib.h.
+ */
+//! @{
+
+/*! \brief Takes the absolute value of \a a.
+ *
+ * \param a Input value.
+ *
+ * \return Absolute value of \a a.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Abs(a)              (((a) <  0 ) ? -(a) : (a))
+
+/*! \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Min(a, b)           (((a) < (b)) ?  (a) : (b))
+
+/*! \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Max(a, b)           (((a) > (b)) ?  (a) : (b))
+
+// abs() is already defined by stdlib.h
+
+/*! \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define min(a, b)   Min(a, b)
+
+/*! \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define max(a, b)   Max(a, b)
+
+//! @}
+
+#endif /* USB_DEVICE_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/USB_host.h b/hardware/digistump/sam/system/libsam/include/USB_host.h
new file mode 100644
index 0000000..43d559e
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/USB_host.h
@@ -0,0 +1,70 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef USB_HOST_H_INCLUDED
+#define USB_HOST_H_INCLUDED
+
+#include 
+
+#define tokSETUP		UOTGHS_HSTPIPCFG_PTOKEN_SETUP
+#define tokIN			UOTGHS_HSTPIPCFG_PTOKEN_IN
+#define tokOUT			UOTGHS_HSTPIPCFG_PTOKEN_OUT
+#define tokINHS			UOTGHS_HSTPIPCFG_PTOKEN_IN
+#define tokOUTHS		UOTGHS_HSTPIPCFG_PTOKEN_OUT
+
+//! \brief Device speed
+/*typedef enum {
+	UHD_SPEED_LOW  = 0,
+	UHD_SPEED_FULL = 1,
+	UHD_SPEED_HIGH = 2,
+} uhd_speed_t;*/
+
+//! States of USBB interface
+typedef enum {
+	UHD_STATE_NO_VBUS = 0,
+	UHD_STATE_DISCONNECTED = 1,
+	UHD_STATE_CONNECTED = 2,
+	UHD_STATE_ERROR = 3,
+} uhd_vbus_state_t;
+
+//extern uhd_speed_t uhd_get_speed(void);
+
+extern void UHD_SetStack(void (*pf_isr)(void));
+extern void UHD_Init(void);
+extern void UHD_BusReset(void);
+extern uhd_vbus_state_t UHD_GetVBUSState(void);
+extern uint32_t UHD_Pipe0_Alloc(uint32_t ul_add, uint32_t ul_ep_size);
+extern uint32_t UHD_Pipe_Alloc(uint32_t ul_dev_addr, uint32_t ul_dev_ep, uint32_t ul_type, uint32_t ul_dir, uint32_t ul_maxsize, uint32_t ul_interval, uint32_t ul_nb_bank);
+extern void UHD_Pipe_Free(uint32_t ul_pipe);
+extern uint32_t UHD_Pipe_Read(uint32_t ul_pipe, uint32_t ul_size, uint8_t* data);
+extern void UHD_Pipe_Write(uint32_t ul_pipe, uint32_t ul_size, uint8_t* data);
+extern void UHD_Pipe_Send(uint32_t ul_pipe, uint32_t ul_token_type);
+extern uint32_t UHD_Pipe_Is_Transfer_Complete(uint32_t ul_pipe, uint32_t ul_token_type);
+
+#endif /* USB_HOST_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/adc.h b/hardware/digistump/sam/system/libsam/include/adc.h
new file mode 100644
index 0000000..c3168fb
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/adc.h
@@ -0,0 +1,248 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef ADC_H_INCLUDED
+#define ADC_H_INCLUDED
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/* The max adc sample freq definition*/
+#define ADC_FREQ_MAX   20000000
+/* The min adc sample freq definition*/
+#define ADC_FREQ_MIN    1000000
+/* The normal adc startup time*/
+#define ADC_STARTUP_NORM     40
+/* The fast adc startup time*/
+#define ADC_STARTUP_FAST     12
+
+/* Definitions for ADC resolution */
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
+enum adc_resolution_t {
+	ADC_10_BITS = ADC_MR_LOWRES_BITS_10,    /* ADC 10-bit resolution */
+	ADC_12_BITS = ADC_MR_LOWRES_BITS_12     /* ADC 12-bit resolution */
+};
+#elif SAM3N_SERIES
+enum adc_resolution_t {
+	ADC_8_BITS = ADC_MR_LOWRES_BITS_8,      /* ADC 8-bit resolution */
+	ADC_10_BITS = ADC_MR_LOWRES_BITS_10     /* ADC 10-bit resolution */
+} ;
+#elif SAM3U_SERIES
+enum adc_resolution_t {
+	ADC_8_BITS = ADC_MR_LOWRES_BITS_8,      /* ADC 8-bit resolution */
+	ADC_10_BITS = ADC12B_MR_LOWRES_BITS_10, /* ADC 10-bit resolution */
+ 	ADC_12_BITS = ADC12B_MR_LOWRES_BITS_12  /* ADC 12-bit resolution */
+} ;
+#endif
+
+/* Definitions for ADC trigger */
+enum adc_trigger_t {
+	ADC_TRIG_SW = ADC_MR_TRGEN_DIS,  /* Starting a conversion is only possible by software. */
+	ADC_TRIG_EXT = ((ADC_MR_TRGSEL_ADC_TRIG0 << ADC_MR_TRGSEL_Pos) &
+									ADC_MR_TRGSEL_Msk) | ADC_MR_TRGEN,  /* External trigger */
+	ADC_TRIG_TIO_CH_0 = (ADC_MR_TRGSEL_ADC_TRIG1  & ADC_MR_TRGSEL_Msk) |
+											ADC_MR_TRGEN,  /* TIO Output of the Timer Counter Channel 0 */
+	ADC_TRIG_TIO_CH_1 = (ADC_MR_TRGSEL_ADC_TRIG2  & ADC_MR_TRGSEL_Msk) |
+											ADC_MR_TRGEN,  /* TIO Output of the Timer Counter Channel 1 */
+	ADC_TRIG_TIO_CH_2 = (ADC_MR_TRGSEL_ADC_TRIG3  & ADC_MR_TRGSEL_Msk) |
+											ADC_MR_TRGEN,  /* TIO Output of the Timer Counter Channel 2 */
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES || SAM3U_SERIES
+	ADC_TRIG_PWM_EVENT_LINE_0 = (ADC_MR_TRGSEL_ADC_TRIG4  & ADC_MR_TRGSEL_Msk) |
+															ADC_MR_TRGEN, /* PWM Event Line 0 */
+	ADC_TRIG_PWM_EVENT_LINE_1 = (ADC_MR_TRGSEL_ADC_TRIG5  & ADC_MR_TRGSEL_Msk) |
+															ADC_MR_TRGEN  /* PWM Event Line 1 */
+#endif
+} ;
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/* Definitions for ADC channel number */
+enum adc_channel_num_t {
+	ADC_CHANNEL_0  = 0,
+	ADC_CHANNEL_1  = 1,
+	ADC_CHANNEL_2  = 2,
+	ADC_CHANNEL_3  = 3,
+	ADC_CHANNEL_4  = 4,
+	ADC_CHANNEL_5  = 5,
+	ADC_CHANNEL_6  = 6,
+	ADC_CHANNEL_7  = 7,
+	ADC_CHANNEL_8  = 8,
+	ADC_CHANNEL_9  = 9,
+	ADC_CHANNEL_10 = 10,
+	ADC_CHANNEL_11 = 11,
+	ADC_CHANNEL_12 = 12,
+	ADC_CHANNEL_13 = 13,
+	ADC_CHANNEL_14 = 14,
+	ADC_TEMPERATURE_SENSOR = 15,
+} ;
+#elif SAM3U_SERIES
+/* Definitions for ADC channel number */
+enum adc_channel_num_t {
+	ADC_CHANNEL_0  = 0,
+	ADC_CHANNEL_1  = 1,
+	ADC_CHANNEL_2  = 2,
+	ADC_CHANNEL_3  = 3,
+	ADC_CHANNEL_4  = 4,
+	ADC_CHANNEL_5  = 5,
+	ADC_CHANNEL_6  = 6,
+	ADC_CHANNEL_7  = 7,
+} ;
+#endif
+/* Definitions for ADC gain value */
+enum adc_gainvalue_t{
+	ADC_GAINVALUE_0 = 0,
+	ADC_GAINVALUE_1 = 1,
+	ADC_GAINVALUE_2 = 2,
+	ADC_GAINVALUE_3 = 3
+};
+/* Definitions for ADC analog settling time */
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
+enum adc_settling_time_t{
+	ADC_SETTLING_TIME_0 = ADC_MR_SETTLING_AST3,
+	ADC_SETTLING_TIME_1 = ADC_MR_SETTLING_AST5,
+	ADC_SETTLING_TIME_2 = ADC_MR_SETTLING_AST9,
+	ADC_SETTLING_TIME_3 = ADC_MR_SETTLING_AST17
+};
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+uint32_t adc_init(Adc *p_adc, const uint32_t ul_mck,
+                            const uint32_t ul_adc_clock, const uint8_t uc_startup);
+void adc_configure_trigger(Adc *p_adc, const enum adc_trigger_t trigger,
+				const uint8_t uc_freerun);
+void adc_configure_power_save(Adc *p_adc, const uint8_t uc_sleep, const uint8_t uc_fwup);
+void adc_configure_sequence(Adc *p_adc, const enum adc_channel_num_t ch_list[],
+                                                               const uint8_t uc_num);
+void adc_enable_tag(Adc *p_adc);
+void adc_disable_tag(Adc *p_adc);
+enum adc_channel_num_t adc_get_tag(const Adc *p_adc);
+void adc_start_sequencer(Adc *p_adc);
+void adc_stop_sequencer(Adc *p_adc);
+void adc_set_comparison_mode(Adc *p_adc, const uint8_t uc_mode);
+uint32_t adc_get_comparison_mode(const Adc *p_adc);
+void adc_set_comparison_window(Adc *p_adc, const uint16_t us_low_threshold,
+                                                                        const uint16_t us_high_threshold);
+void adc_set_comparison_channel(Adc *p_adc, const enum adc_channel_num_t channel);
+void adc_set_writeprotect(Adc *p_adc, const uint32_t ul_enable);
+uint32_t adc_get_writeprotect_status(const Adc *p_adc);
+void adc_check(Adc* p_adc, const uint32_t ul_mck);
+uint32_t adc_get_overrun_status(const Adc *p_adc);
+#elif SAM3U_SERIES
+uint32_t adc_init(Adc * p_adc, const uint32_t ul_mck, const uint32_t ul_adc_clock,
+		const uint32_t ul_startuptime);
+void adc_configure_trigger(Adc *p_adc, const enum adc_trigger_t trigger);
+void adc_configure_power_save(Adc *p_adc, const uint8_t uc_sleep);
+#endif
+
+void adc_set_resolution(Adc *p_adc, const enum adc_resolution_t resolution);
+void adc_start(Adc *p_adc);
+void adc_stop(Adc *p_adc);
+void adc_enable_channel(Adc *p_adc, const enum adc_channel_num_t adc_ch);
+void adc_disable_channel(Adc *p_adc, const enum adc_channel_num_t adc_ch);
+void adc_enable_all_channel(Adc *p_adc);
+void adc_disable_all_channel(Adc *p_adc);
+uint32_t adc_get_channel_status(const Adc *p_adc, const enum adc_channel_num_t adc_ch);
+uint32_t adc_get_channel_value(const Adc *p_adc,const  enum adc_channel_num_t adc_ch);
+uint32_t adc_get_latest_value(const Adc *p_adc);
+uint32_t adc_get_actual_adc_clock(const Adc *p_adc, const uint32_t ul_mck);
+void adc_enable_interrupt(Adc *p_adc, const uint32_t ul_source);
+void adc_disable_interrupt(Adc *p_adc, const uint32_t ul_source);
+uint32_t adc_get_status(const Adc *p_adc);
+uint32_t adc_get_interrupt_mask(const Adc *p_adc);
+Pdc *adc_get_pdc_base(const Adc *p_adc);
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
+void adc_configure_timing(Adc *p_adc, const uint8_t uc_tracking,
+                                         const enum adc_settling_time_t settling, const uint8_t uc_transfer);
+void adc_enable_anch( Adc *p_adc );
+void adc_disable_anch( Adc *p_adc );
+void adc_enable_channel_differential_input(Adc *p_adc, const enum adc_channel_num_t channel);
+void adc_disable_channel_differential_input(Adc *p_adc, const enum adc_channel_num_t channel);
+void adc_enable_channel_input_offset(Adc *p_adc, const enum adc_channel_num_t channel);
+void adc_disable_channel_input_offset(Adc *p_adc, const enum adc_channel_num_t channel);
+void adc_set_channel_input_gain(Adc *p_adc, const enum adc_channel_num_t channel,
+                                                       const enum adc_gainvalue_t uc_gain);
+void adc_set_bias_current(Adc *p_adc, const uint8_t uc_ibctl);
+void adc_enable_ts(Adc *p_adc);
+void adc_disable_ts(Adc *p_adc);
+#elif SAM3N_SERIES
+void adc_configure_timing(Adc *p_adc, const uint8_t uc_tracking);
+#elif SAM3U_SERIES
+void adc_configure_timing(Adc *p_adc, const uint32_t ul_sh);
+#endif
+
+#if  SAM3SD8_SERIES || SAM4S_SERIES
+void adc_set_calibmode(Adc *p_adc);
+#endif
+
+#if SAM3U_SERIES
+uint32_t adc12b_init(Adc12b *p_adc, const uint32_t ul_mck, const uint32_t ul_adc_clock,
+                                   const uint32_t ul_startuptime, const uint32_t ul_offmode_startuptime);
+void adc12b_set_resolution(Adc12b *p_adc, const enum adc_resolution_t resolution);
+void adc12b_configure_trigger(Adc12b *p_adc, const enum adc_trigger_t trigger);
+void adc12b_configure_power_save(Adc12b *p_adc, const uint8_t uc_sleep, const uint8_t uc_offmode);
+void adc12b_configure_timing(Adc12b *p_adc, const uint32_t ul_sh);
+void adc12b_start(Adc12b *p_adc);
+void adc12b_stop(Adc12b *p_adc);
+void adc12b_enable_channel(Adc12b *p_adc, const enum adc_channel_num_t adc_ch);
+void adc12b_disable_channel(Adc12b *p_adc, const enum adc_channel_num_t adc_ch);
+void adc12b_enable_all_channel(Adc12b *p_adc);
+void adc12b_disable_all_channel(Adc12b *p_adc);
+uint32_t adc12b_get_channel_status(const Adc12b *p_adc,const enum adc_channel_num_t adc_ch);
+uint32_t adc12b_get_channel_value(const Adc12b *p_adc, const enum adc_channel_num_t adc_ch);
+uint32_t adc12b_get_latest_value(const Adc12b *p_adc);
+void adc12b_enable_differential_input(Adc12b *p_adc);
+void adc12b_disable_differential_input(Adc12b *p_adc);
+void adc12b_enable_input_offset(Adc12b *p_adc);
+void adc12b_disable_input_offset(Adc12b *p_adc);
+void adc12b_set_input_gain(Adc12b *p_adc, const enum adc_gainvalue_t uc_gain);
+uint32_t adc12b_get_actual_adc_clock(const Adc12b *p_adc, const uint32_t ul_mck);
+void adc12b_enable_interrupt(Adc12b *p_adc, const uint32_t ul_source);
+void adc12b_disable_interrupt(Adc12b *p_adc, const uint32_t ul_source);
+uint32_t adc12b_get_interrupt_mask(const Adc12b *p_adc);
+uint32_t adc12b_get_status(const Adc12b *p_adc);
+void adc12b_set_bias_current(Adc12b *p_adc, const uint8_t uc_ibctl);
+Pdc *adc12b_get_pdc_base(const Adc12b *p_adc);
+#endif
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* ADC_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/can.h b/hardware/digistump/sam/system/libsam/include/can.h
new file mode 100644
index 0000000..5cbc6f0
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/can.h
@@ -0,0 +1,492 @@
+/**
+ * \file
+ *
+ * \brief Controller Area Network (CAN) driver module for SAM.
+ *
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef CAN_H_INCLUDED
+#define CAN_H_INCLUDED
+
+#include "../chip.h"
+
+/** @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/** @endcond */
+
+/** Define the Mailbox mask for eight mailboxes. */
+#define GLOBAL_MAILBOX_MASK           0x000000ff
+
+/** Disable all interrupt mask */
+#define CAN_DISABLE_ALL_INTERRUPT_MASK 0xffffffff
+
+/** Define the typical baudrate for CAN communication in KHz. */
+#define CAN_BPS_1000K                 1000
+#define CAN_BPS_800K                  800
+#define CAN_BPS_500K                  500
+#define CAN_BPS_250K                  250
+#define CAN_BPS_125K                  125
+#define CAN_BPS_50K                   50
+#define CAN_BPS_25K                   25
+#define CAN_BPS_10K                   10
+#define CAN_BPS_5K                    5
+
+/** Define the mailbox mode. */
+#define CAN_MB_DISABLE_MODE           0
+#define CAN_MB_RX_MODE                1
+#define CAN_MB_RX_OVER_WR_MODE        2
+#define CAN_MB_TX_MODE                3
+#define CAN_MB_CONSUMER_MODE          4
+#define CAN_MB_PRODUCER_MODE          5
+
+/** Define CAN mailbox transfer status code. */
+#define CAN_MAILBOX_TRANSFER_OK       0     //! Read from or write into mailbox successfully.
+#define CAN_MAILBOX_NOT_READY         0x01  //! Receiver is empty or transmitter is busy.
+#define CAN_MAILBOX_RX_OVER           0x02  //! Message overwriting happens or there're messages lost in different receive modes.
+#define CAN_MAILBOX_RX_NEED_RD_AGAIN  0x04  //! Application needs to re-read the data register in Receive with Overwrite mode.
+
+/** Define the struct for CAN message mailbox. */
+typedef struct {
+	uint32_t ul_mb_idx;
+	uint8_t uc_obj_type;  //! Mailbox object type, one of the six different objects.
+	uint8_t uc_id_ver;    //! 0 stands for standard frame, 1 stands for extended frame.
+	uint8_t uc_length;    //! Received data length or transmitted data length.
+	uint8_t uc_tx_prio;   //! Mailbox priority, no effect in receive mode.
+	uint32_t ul_status;   //! Mailbox status register value.
+	uint32_t ul_id_msk;   //! No effect in transmit mode.
+	uint32_t ul_id;       //! Received frame ID or the frame ID to be transmitted.
+	uint32_t ul_fid;      //! Family ID.
+	uint32_t ul_datal;
+	uint32_t ul_datah;
+} can_mb_conf_t;
+
+/**
+ * \defgroup sam_driver_can_group Controller Area Network (CAN) Driver
+ *
+ * See \ref sam_can_quickstart.
+ *
+ * \par Purpose
+ *
+ * The CAN controller provides all the features required to implement
+ * the serial communication protocol CAN defined by Robert Bosch GmbH,
+ * the CAN specification. This is a driver for configuration, enabling,
+ * disabling and use of the CAN peripheral.
+ *
+ * @{
+ */
+
+uint32_t can_init(Can *p_can, uint32_t ul_mck, uint32_t ul_baudrate);
+
+void can_enable(Can *p_can);
+void can_disable(Can *p_can);
+
+void can_disable_low_power_mode(Can *p_can);
+void can_enable_low_power_mode(Can *p_can);
+
+void can_disable_autobaud_listen_mode(Can *p_can);
+void can_enable_autobaud_listen_mode(Can *p_can);
+
+void can_disable_overload_frame(Can *p_can);
+void can_enable_overload_frame(Can *p_can);
+
+void can_set_timestamp_capture_point(Can *p_can, uint32_t ul_flag);
+
+void can_disable_time_triggered_mode(Can *p_can);
+void can_enable_time_triggered_mode(Can *p_can);
+
+void can_disable_timer_freeze(Can *p_can);
+void can_enable_timer_freeze(Can *p_can);
+
+void can_disable_tx_repeat(Can *p_can);
+void can_enable_tx_repeat(Can *p_can);
+
+void can_set_rx_sync_stage(Can *p_can, uint32_t ul_stage);
+
+void can_enable_interrupt(Can *p_can, uint32_t dw_mask);
+void can_disable_interrupt(Can *p_can, uint32_t dw_mask);
+
+uint32_t can_get_interrupt_mask(Can *p_can);
+
+uint32_t can_get_status(Can *p_can);
+
+uint32_t can_get_internal_timer_value(Can *p_can);
+
+uint32_t can_get_timestamp_value(Can *p_can);
+
+uint8_t can_get_tx_error_cnt(Can *p_can);
+uint8_t can_get_rx_error_cnt(Can *p_can);
+
+void can_reset_internal_timer(Can *p_can);
+
+void can_global_send_transfer_cmd(Can *p_can, uint8_t uc_mask);
+void can_global_send_abort_cmd(Can *p_can, uint8_t uc_mask);
+
+/*
+ * Mailbox functions
+ */
+void can_mailbox_set_timemark(Can *p_can, uint8_t uc_index, uint16_t us_cnt);
+uint32_t can_mailbox_get_status(Can *p_can, uint8_t uc_index);
+void can_mailbox_send_transfer_cmd(Can *p_can, uint8_t uc_index);
+void can_mailbox_send_abort_cmd(Can *p_can, uint8_t uc_index);
+void can_mailbox_init(Can *p_can, can_mb_conf_t *p_mailbox);
+uint32_t can_mailbox_read(Can *p_can, can_mb_conf_t *p_mailbox);
+uint32_t can_mailbox_write(Can *p_can, can_mb_conf_t *p_mailbox);
+uint32_t can_mailbox_tx_remote_frame(Can *p_can, can_mb_conf_t *p_mailbox);
+void can_reset_all_mailbox(Can *p_can);
+
+// from wilfredo
+uint32_t can_reset_mailbox_data(can_mb_conf_t *p_mailbox);
+
+/** @} */
+
+/** @cond 0 */
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/** @endcond */
+
+/**
+ * \page sam_can_quickstart Quickstart guide for SAM CAN module.
+ *
+ * This is the quickstart guide for the \ref sam_drivers_can_group "SAM CAN module",
+ * with step-by-step instructions on how to configure and use the drivers in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section can_basic_use_case Basic use case
+ * In this basic use case, as CAN module needs to work in network, two CAN modules
+ * need to be configured. CAN0 mailbox 0 is configured as transmitter, and CAN1 mailbox 0
+ * is configured as receiver. The communication baudrate is 1Mbit/s.
+ *
+ * \section can_basic_use_case_setup Setup steps
+ *
+ * \subsection can_basic_use_case_setup_prereq Prerequisites
+ *  - \ref group_pmc "Power Management Controller driver"
+ *  - \ref group_sn65hvd234_transceiver "CAN transceiver driver"
+ *
+ * \subsection can_basic_use_case_setup_code Example code
+ * Add to application initialization:
+ * \code
+ *    can_mb_conf_t can0_mailbox;
+ *    can_mb_conf_t can1_mailbox;
+ *
+ *    pmc_enable_periph_clk(ID_CAN0);
+ *    pmc_enable_periph_clk(ID_CAN1);
+ *
+ *    can_init(CAN0, ul_sysclk, CAN_BPS_1000K);
+ *    can_init(CAN1, ul_sysclk, CAN_BPS_1000K);
+ *
+ *    can_reset_all_mailbox(CAN0);
+ *    can_reset_all_mailbox(CAN1);
+ *
+ *    can1_mailbox.ul_mb_idx = 0;
+ *    can1_mailbox.uc_obj_type = CAN_MB_RX_MODE;
+ *    can1_mailbox.ul_id_msk = CAN_MAM_MIDvA_Msk | CAN_MAM_MIDvB_Msk;
+ *    can1_mailbox.ul_id = CAN_MID_MIDvA(0x07);
+ *    can_mailbox_init(CAN1, &can1_mailbox);
+ *
+ *    can0_mailbox.ul_mb_idx = 0;
+ *    can0_mailbox.uc_obj_type = CAN_MB_TX_MODE;
+ *    can0_mailbox.uc_tx_prio = 15;
+ *    can0_mailbox.uc_id_ver = 0;
+ *    can0_mailbox.ul_id_msk = 0;
+ *    can_mailbox_init(CAN0, &can0_mailbox);
+ *
+ *    can0_mailbox.ul_id = CAN_MID_MIDvA(0x07);
+ *    can0_mailbox.ul_datal = 0x12345678;
+ *    can0_mailbox.ul_datah = 0x87654321;
+ *    can0_mailbox.uc_length = 8;
+ *    can_mailbox_write(CAN0, &can0_mailbox);
+ * \endcode
+ *
+ * \subsection can_basic_use_case_setup_flow Workflow
+ * -# Define the CAN0 and CAN1 Transfer mailbox structure:
+ *   - \code
+ *    can_mb_conf_t can0_mailbox;
+ *    can_mb_conf_t can1_mailbox;
+ *   \endcode
+ * -# Enable the module clock for CAN0 and CAN1:
+ *   - \code
+ *    pmc_enable_periph_clk(ID_CAN0);
+ *    pmc_enable_periph_clk(ID_CAN1);
+ *   \endcode
+ * -# Initialize CAN0 and CAN1, baudrate is 1Mb/s:
+ *   - \code
+ *    can_init(CAN0, ul_sysclk, CAN_BPS_1000K);
+ *    can_init(CAN1, ul_sysclk, CAN_BPS_1000K);
+ *   \endcode
+ *   - \note The CAN transceiver should be configured before initializing the CAN module.
+ * -# Reset all CAN0 and CAN1 mailboxes:
+ *   - \code
+ *    can_reset_all_mailbox(CAN0);
+ *    can_reset_all_mailbox(CAN1);
+ *   \endcode
+ * -# Initialize CAN1 mailbox 0 as receiver, frame ID is 0x07:
+ *   - \code
+ *    can1_mailbox.ul_mb_idx = 0;
+ *    can1_mailbox.uc_obj_type = CAN_MB_RX_MODE;
+ *    can1_mailbox.ul_id_msk = CAN_MAM_MIDvA_Msk | CAN_MAM_MIDvB_Msk;
+ *    can1_mailbox.ul_id = CAN_MID_MIDvA(0x07);
+ *    can_mailbox_init(CAN1, &can1_mailbox);
+ *   \endcode
+ * -# Initialize CAN0 mailbox 0 as transmitter, transmit priority is 15:
+ *   - \code
+ *    can0_mailbox.ul_mb_idx = 0;
+ *    can0_mailbox.uc_obj_type = CAN_MB_TX_MODE;
+ *    can0_mailbox.uc_tx_prio = 15;
+ *    can0_mailbox.uc_id_ver = 0;
+ *    can0_mailbox.ul_id_msk = 0;
+ *    can_mailbox_init(CAN0, &can0_mailbox);
+ *   \endcode
+ * -# Prepare transmit ID, data and data length in CAN0 mailbox 0:
+ *   - \code
+ *    can0_mailbox.ul_id = CAN_MID_MIDvA(0x07);
+ *    can0_mailbox.ul_datal = 0x12345678;
+ *    can0_mailbox.ul_datah = 0x87654321;
+ *    can0_mailbox.uc_length = 8;
+ *    can_mailbox_write(CAN0, &can0_mailbox);
+ *   \endcode
+ *
+ * \section can_basic_use_case_usage Usage steps
+ *
+ * \subsection can_basic_use_case_usage_code Example code
+ * Add to, e.g., main loop in application C-file:
+ * \code
+ *    can_global_send_transfer_cmd(CAN0, CAN_TCR_MB0);
+ *
+ *    while (!(can_mailbox_get_status(CAN1, 0) & CAN_MSR_MRDY)) {
+ *    }
+ *
+ *    can_mailbox_read(CAN1, &can1_mailbox);
+ * \endcode
+ *
+ * \subsection can_basic_use_case_usage_flow Workflow
+ * -# Send out data in CAN0 mailbox 0:
+ *   - \code can_global_send_transfer_cmd(CAN0, CAN_TCR_MB0); \endcode
+ * -# Wait for CAN1 mailbox 0 to receive the data:
+ *   - \code
+ *    while (!(can_mailbox_get_status(CAN1, 0) & CAN_MSR_MRDY)) {
+ *    }
+ *   \endcode
+ * -# Read the received data from CAN1 mailbox 0:
+ *   - \code can_mailbox_read(CAN1, &can1_mailbox); \endcode
+ *
+ * \section can_use_cases Advanced use cases
+ * For more advanced use of the CAN driver, see the following use cases:
+ * - \subpage can_use_case_1 : Two CAN modules work in PRODUCER and CONSUMER mode
+ * respectively, use CAN interrupt handler to check whether the communication has been
+ * completed.
+ */
+
+/**
+ * \page can_use_case_1 Use case #1
+ *
+ * In this use case, CAN0 mailbox 0 works in PRODUCER mode, and CAN1 mailbox 0
+ * works in CONSUMER mode. While CAN1 mailbox 0 receives a data frame from the bus,
+ * an interrupt is triggered.
+ *
+ * \section can_use_case_1_setup Setup steps
+ *
+ * \subsection can_basic_use_case_setup_prereq Prerequisites
+ *  - \ref group_pmc "Power Management Controller driver"
+ *  - \ref group_sn65hvd234_transceiver "CAN transceiver driver"
+ *
+ * \subsection can_use_case_1_setup_code Example code
+ * Add to application C-file:
+ * \code
+ *    can_mb_conf_t can0_mailbox;
+ *    can_mb_conf_t can1_mailbox;
+ *    volatile uint32_t g_ul_recv_status = 0;
+ * \endcode
+ *
+ * \code
+ *    void CAN1_Handler(void)
+ *    {
+ *        uint32_t ul_status;
+ *
+ *        ul_status = can_mailbox_get_status(CAN1, 0);
+ *        if ((ul_status & CAN_MSR_MRDY) == CAN_MSR_MRDY) {
+ *            can1_mailbox.ul_mb_idx = 0;
+ *            can1_mailbox.ul_status = ul_status;
+ *            can_mailbox_read(CAN1, &can1_mailbox);
+ *            g_ul_recv_status = 1;
+ *        }
+ *    }
+ * \endcode
+ *
+ * \code
+ *    pmc_enable_periph_clk(ID_CAN0);
+ *    pmc_enable_periph_clk(ID_CAN1);
+ *
+ *    can_init(CAN0, ul_sysclk, CAN_BPS_1000K);
+ *    can_init(CAN1, ul_sysclk, CAN_BPS_1000K);
+ *
+ *    can_reset_all_mailbox(CAN0);
+ *    can_reset_all_mailbox(CAN1);
+ *
+ *    can0_mailbox.ul_mb_idx = 0;
+ *    can0_mailbox.uc_obj_type = CAN_MB_PRODUCER_MODE;
+ *    can0_mailbox.ul_id_msk = 0;
+ *    can0_mailbox.ul_id = CAN_MID_MIDvA(0x0b);
+ *    can_mailbox_init(CAN0, &can0_mailbox);
+ *
+ *    can0_mailbox.ul_datal = 0x11223344;
+ *    can0_mailbox.ul_datah = 0x44332211;
+ *    can0_mailbox.uc_length = 8;
+ *    can_mailbox_write(CAN0, &can0_mailbox);
+ *
+ *    can1_mailbox.ul_mb_idx = 0;
+ *    can1_mailbox.uc_obj_type = CAN_MB_CONSUMER_MODE;
+ *    can1_mailbox.uc_tx_prio = 15;
+ *    can1_mailbox.ul_id_msk = CAN_MID_MIDvA_Msk | CAN_MID_MIDvB_Msk;
+ *    can1_mailbox.ul_id = CAN_MID_MIDvA(0x0b);
+ *    can_mailbox_init(CAN1, &can1_mailbox);
+ *
+ *    can_enable_interrupt(CAN1, CAN_IER_MB0);
+ *    NVIC_EnableIRQ(CAN1_IRQn);
+ * \endcode
+ *
+ * \subsection can_use_case_1_setup_flow Workflow
+ * -# Define the CAN0 and CAN1 Transfer mailbox structure:
+ *   - \code
+ *    can_mb_conf_t can0_mailbox;
+ *    can_mb_conf_t can1_mailbox;
+ *   \endcode
+ * -# Define the receive flag that is changed in CAN1 ISR handler:
+ *   - \code volatile uint32_t g_ul_recv_status = 0; \endcode
+ * -# Define the CAN1 ISR handler in the application:
+ *   - \code void CAN1_Handler(void); \endcode
+ * -# In CAN1_Handler(), get CAN1 mailbox 0 status:
+ *   - \code ul_status = can_mailbox_get_status(CAN1, 0); \endcode
+ * -# In CAN1_Handler(), check whether the mailbox 0 has received a data frame:
+ *   - \code
+ *    if ((ul_status & CAN_MSR_MRDY) == CAN_MSR_MRDY) {
+ *        can1_mailbox.ul_mb_idx = 0;
+ *        can1_mailbox.ul_status = ul_status;
+ *        can_mailbox_read(CAN1, &can1_mailbox);
+ *        g_ul_recv_status = 1;
+ *    }
+ *   \endcode
+ * -# In CAN1_Handler(), if mailbox 0 is ready, read the received data from CAN1 mailbox 0:
+ *   - \code
+ *    can1_mailbox.ul_mb_idx = 0;
+ *    can1_mailbox.ul_status = ul_status;
+ *    can_mailbox_read(CAN1, &can1_mailbox);
+ *   \endcode
+ * -# In CAN1_Handler(), if mailbox 0 is ready, set up the receive flag:
+ *   - \code g_ul_recv_status = 1; \endcode
+ * -# Enable the module clock for CAN0 and CAN1:
+ *   - \code
+ *    pmc_enable_periph_clk(ID_CAN0);
+ *    pmc_enable_periph_clk(ID_CAN1);
+ *   \endcode
+ * -# Initialize CAN0 and CAN1, baudrate is 1Mb/s:
+ *   - \code
+ *    can_init(CAN0, ul_sysclk, CAN_BPS_1000K);
+ *    can_init(CAN1, ul_sysclk, CAN_BPS_1000K);
+ *   \endcode
+ *   - \note The CAN transceiver should be configured before initializing the CAN module.
+ * -# Reset all CAN0 and CAN1 mailboxes:
+ *   - \code
+ *    can_reset_all_mailbox(CAN0);
+ *    can_reset_all_mailbox(CAN1);
+ *   \endcode
+ * -# Initialize CAN0 mailbox 0 as PRODUCER:
+ *   - \code
+ *    can0_mailbox.ul_mb_idx = 0;
+ *    can0_mailbox.uc_obj_type = CAN_MB_PRODUCER_MODE;
+ *    can0_mailbox.ul_id_msk = 0;
+ *    can0_mailbox.ul_id = CAN_MID_MIDvA(0x0b);
+ *    can_mailbox_init(CAN0, &can0_mailbox);
+ *   \endcode
+ * -# Prepare the response information when it receives a remote frame:
+ *   - \code
+ *    can0_mailbox.ul_datal = 0x11223344;
+ *    can0_mailbox.ul_datah = 0x44332211;
+ *    can0_mailbox.uc_length = 8;
+ *    can_mailbox_write(CAN0, &can0_mailbox);
+ *   \endcode
+ * -# Initialize CAN1 mailbox 0 as CONSUMER:
+ *   - \code
+ *    can1_mailbox.ul_mb_idx = 0;
+ *    can1_mailbox.uc_obj_type = CAN_MB_CONSUMER_MODE;
+ *    can1_mailbox.uc_tx_prio = 15;
+ *    can1_mailbox.ul_id_msk = CAN_MID_MIDvA_Msk | CAN_MID_MIDvB_Msk;
+ *    can1_mailbox.ul_id = CAN_MID_MIDvA(0x0b);
+ *    can_mailbox_init(CAN1, &can1_mailbox);
+ *   \endcode
+ * -# Enable the CAN1 mailbox 0 interrupt:
+ *   - \code
+ *    can_enable_interrupt(CAN1, CAN_IER_MB0);
+ *    NVIC_EnableIRQ(CAN1_IRQn);
+ *   \endcode
+ *
+ * \section can_use_case_1_usage Usage steps
+ *
+ * \subsection can_use_case_1_usage_code Example code
+ * \code
+ *    can_global_send_transfer_cmd(CAN0, CAN_TCR_MB0);
+ *    can_global_send_transfer_cmd(CAN1, CAN_TCR_MB0);
+ *
+ *    while (!g_ul_recv_status) {
+ *    }
+ * \endcode
+ *
+ * \subsection can_use_case_1_usage_flow Workflow
+ * -# Enable CAN0 mailbox 0 to receive remote frame and respond it:
+ *   - \code can_global_send_transfer_cmd(CAN0, CAN_TCR_MB0); \endcode
+ * -# Enable CAN1 mailbox 0 to send out a remote frame and then receive data frame from bus:
+ *   - \code can_global_send_transfer_cmd(CAN1, CAN_TCR_MB0); \endcode
+ * -# Wait for the communication to be completed.
+ *   - \code
+ *    while (!g_ul_recv_status) {
+ *    }
+ *   \endcode
+ */
+
+#endif /* CAN_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/dacc.h b/hardware/digistump/sam/system/libsam/include/dacc.h
new file mode 100644
index 0000000..81342d1
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/dacc.h
@@ -0,0 +1,102 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef DACC_H_INCLUDED
+#define DACC_H_INCLUDED
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+//! DACC return codes
+typedef enum dacc_rc {
+	DACC_RC_OK = 0,        //!< Operation OK
+	DACC_RC_INVALID_PARAM  //!< Invalid parameter
+} dacc_rc_t;
+
+#if SAM3N_SERIES
+//! DACC resolution in number of data bits
+# define DACC_RESOLUTION     10
+#else
+//! DACC resolution in number of data bits
+# define DACC_RESOLUTION     12
+#endif
+//! DACC max data value
+#define DACC_MAX_DATA       ((1 << DACC_RESOLUTION) - 1)
+
+void dacc_reset(Dacc *p_dacc);
+uint32_t dacc_set_trigger(Dacc *p_dacc, uint32_t ul_trigger);
+void dacc_disable_trigger(Dacc *p_dacc);
+uint32_t dacc_set_transfer_mode(Dacc *p_dacc, uint32_t ul_mode);
+void dacc_enable_interrupt(Dacc *p_dacc, uint32_t ul_interrupt_mask);
+void dacc_disable_interrupt(Dacc *p_dacc, uint32_t ul_interrupt_mask);
+uint32_t dacc_get_interrupt_mask(Dacc *p_dacc);
+uint32_t dacc_get_interrupt_status(Dacc *p_dacc);
+void dacc_write_conversion_data(Dacc *p_dacc, uint32_t ul_data);
+void dacc_set_writeprotect(Dacc *p_dacc, uint32_t ul_enable);
+uint32_t dacc_get_writeprotect_status(Dacc *p_dacc);
+Pdc *dacc_get_pdc_base(Dacc *p_dacc);
+
+#if (SAM3N_SERIES) || defined(__DOXYGEN__)
+void dacc_enable(Dacc *p_dacc);
+void dacc_disable(Dacc *p_dacc);
+uint32_t dacc_set_timing(Dacc *p_dacc, uint32_t ul_startup,
+		uint32_t ul_clock_divider);
+#endif /* (SAM3N_SERIES) */
+
+#if (SAM3S_SERIES) || (SAM3XA_SERIES) || (SAM4S_SERIES) || defined(__DOXYGEN__)
+uint32_t dacc_set_channel_selection(Dacc *p_dacc, uint32_t ul_channel);
+void dacc_enable_flexible_selection(Dacc *p_dacc);
+
+uint32_t dacc_set_power_save(Dacc *p_dacc, uint32_t ul_sleep_mode,
+		uint32_t ul_fast_wakeup_mode);
+uint32_t dacc_set_timing(Dacc *p_dacc, uint32_t ul_refresh, uint32_t ul_maxs,
+		uint32_t ul_startup);
+uint32_t dacc_enable_channel(Dacc *p_dacc, uint32_t ul_channel);
+uint32_t dacc_disable_channel(Dacc *p_dacc, uint32_t ul_channel);
+uint32_t dacc_get_channel_status(Dacc *p_dacc);
+uint32_t dacc_set_analog_control(Dacc *p_dacc, uint32_t ul_analog_control);
+uint32_t dacc_get_analog_control(Dacc *p_dacc);
+#endif /* (SAM3S_SERIES) || (SAM3XA_SERIES) */
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* DACC_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/efc.h b/hardware/digistump/sam/system/libsam/include/efc.h
new file mode 100644
index 0000000..07f78bb
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/efc.h
@@ -0,0 +1,132 @@
+/**
+ * \file
+ *
+ * \brief Embedded Flash Controller (EFC) driver for SAM.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef EFC_H_INCLUDED
+#define EFC_H_INCLUDED
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/*! \name EFC return codes */
+//! @{
+typedef enum efc_rc {
+	EFC_RC_OK = 0,	    //!< Operation OK
+	EFC_RC_YES = 0,	    //!< Yes
+	EFC_RC_NO = 1,	    //!< No
+	EFC_RC_ERROR = 1,	//!< General error
+	EFC_RC_INVALID,	    //!< Invalid argument input
+	EFC_RC_NOT_SUPPORT = 0xFFFFFFFF	//!< Operation is not supported
+} efc_rc_t;
+//! @}
+
+/*! \name EFC command */
+//! @{
+#define EFC_FCMD_GETD    0x00	//!< Get Flash Descriptor
+#define EFC_FCMD_WP      0x01	//!< Write page
+#define EFC_FCMD_WPL     0x02	//!< Write page and lock
+#define EFC_FCMD_EWP     0x03	//!< Erase page and write page
+#define EFC_FCMD_EWPL    0x04	//!< Erase page and write page then lock
+#define EFC_FCMD_EA      0x05	//!< Erase all
+#if (SAM3SD8_SERIES)
+#define EFC_FCMD_EPL     0x06	//!< Erase plane
+#endif
+#if (SAM4S_SERIES)
+#define EFC_FCMD_EPA     0x07	//!< Erase pages
+#endif
+#define EFC_FCMD_SLB     0x08	//!< Set Lock Bit
+#define EFC_FCMD_CLB     0x09	//!< Clear Lock Bit
+#define EFC_FCMD_GLB     0x0A	//!< Get Lock Bit
+#define EFC_FCMD_SGPB    0x0B	//!< Set GPNVM Bit
+#define EFC_FCMD_CGPB    0x0C	//!< Clear GPNVM Bit
+#define EFC_FCMD_GGPB    0x0D	//!< Get GPNVM Bit
+#define EFC_FCMD_STUI    0x0E	//!< Start unique ID
+#define EFC_FCMD_SPUI    0x0F	//!< Stop unique ID
+#if (SAM3S_SERIES || SAM3N_SERIES || SAM3XA_SERIES || SAM4S_SERIES)
+#define EFC_FCMD_GCALB   0x10	//!< Get CALIB Bit
+#endif
+#if (SAM4S_SERIES)
+#define EFC_FCMD_ES      0x11 //!< Erase sector
+#define EFC_FCMD_WUS		 0x12 //!< Write user signature
+#define EFC_FCMD_EUS		 0x13	//!< Erase user signature
+#define EFC_FCMD_STUS		 0x14	//!< Start read user signature
+#define EFC_FCMD_SPUS		 0x15	//!< Stop read user signature
+#endif
+//! @}
+
+/*! The IAP function entry address */
+#define CHIP_FLASH_IAP_ADDRESS  (IROM_ADDR + 8)
+
+/*! \name EFC access mode */
+//! @{
+#define EFC_ACCESS_MODE_128    0
+#define EFC_ACCESS_MODE_64     EEFC_FMR_FAM
+//! @}
+
+uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws);
+void efc_enable_frdy_interrupt(Efc *p_efc);
+void efc_disable_frdy_interrupt(Efc *p_efc);
+void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode);
+uint32_t efc_get_flash_access_mode(Efc *p_efc);
+void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws);
+uint32_t efc_get_wait_state(Efc *p_efc);
+uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command,	uint32_t ul_argument);
+uint32_t efc_get_status(Efc *p_efc);
+uint32_t efc_get_result(Efc *p_efc);
+uint32_t efc_perform_read_sequence(Efc *p_efc, uint32_t ul_cmd_st, uint32_t ul_cmd_sp, uint32_t *p_ul_buf, uint32_t ul_size);
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* EFC_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/emac.h b/hardware/digistump/sam/system/libsam/include/emac.h
new file mode 100644
index 0000000..cdcd03d
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/emac.h
@@ -0,0 +1,1225 @@
+ /**
+ * \file
+ *
+ * \brief EMAC (Ethernet MAC) driver for SAM.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef EMAC_H_INCLUDED
+#define EMAC_H_INCLUDED
+
+#include "../chip.h"
+//#include "conf_eth.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/** The buffer addresses written into the descriptors must be aligned, so the
+    last few bits are zero.  These bits have special meaning for the EMAC
+    peripheral and cannot be used as part of the address. */
+#define EMAC_RXD_ADDR_MASK      0xFFFFFFFC
+#define EMAC_RXD_WRAP         (1ul << 1)  /**< Wrap bit */
+#define EMAC_RXD_OWNERSHIP    (1ul << 0)  /**< Ownership bit */
+
+#define EMAC_RXD_BROADCAST    (1ul << 31) /**< Broadcast detected */
+#define EMAC_RXD_MULTIHASH    (1ul << 30) /**< Multicast hash match */
+#define EMAC_RXD_UNIHASH      (1ul << 29) /**< Unicast hash match */
+#define EMAC_RXD_EXTADDR      (1ul << 28) /**< External address match */
+#define EMAC_RXD_ADDR1        (1ul << 26) /**< Address 1 match */
+#define EMAC_RXD_ADDR2        (1ul << 25) /**< Address 2 match */
+#define EMAC_RXD_ADDR3        (1ul << 24) /**< Address 3 match */
+#define EMAC_RXD_ADDR4        (1ul << 23) /**< Address 4 match */
+#define EMAC_RXD_TYPE         (1ul << 22) /**< Type ID match */
+#define EMAC_RXD_VLAN         (1ul << 21) /**< VLAN tag detected */
+#define EMAC_RXD_PRIORITY     (1ul << 20) /**< Priority tag detected */
+#define EMAC_RXD_PRIORITY_MASK  (3ul << 17) /**< VLAN priority */
+#define EMAC_RXD_CFI          (1ul << 16) /**< Concatenation Format Indicator only if bit 21 is set */
+#define EMAC_RXD_EOF          (1ul << 15) /**< End of frame */
+#define EMAC_RXD_SOF          (1ul << 14) /**< Start of frame */
+#define EMAC_RXD_OFFSET_MASK                /**< Receive buffer offset */
+#define EMAC_RXD_LEN_MASK       (0xFFF)     /**< Length of frame including FCS (if selected) */
+#define EMAC_RXD_LENJUMBO_MASK  (0x3FFF)    /**< Jumbo frame length */
+
+#define EMAC_TXD_USED         (1ul << 31) /**< Frame is transmitted */
+#define EMAC_TXD_WRAP         (1ul << 30) /**< Last descriptor */
+#define EMAC_TXD_ERROR        (1ul << 29) /**< Retry limit exceeded, error */
+#define EMAC_TXD_UNDERRUN     (1ul << 28) /**< Transmit underrun */
+#define EMAC_TXD_EXHAUSTED    (1ul << 27) /**< Buffer exhausted */
+#define EMAC_TXD_NOCRC        (1ul << 16) /**< No CRC */
+#define EMAC_TXD_LAST         (1ul << 15) /**< Last buffer in frame */
+#define EMAC_TXD_LEN_MASK       (0x7FF)     /**< Length of buffer */
+
+/** The MAC can support frame lengths up to 1536 bytes */
+#define EMAC_FRAME_LENTGH_MAX       1536
+
+#define EMAC_RX_UNITSIZE            128     /**< Fixed size for RX buffer  */
+#define EMAC_TX_UNITSIZE            1518    /**< Size for ETH frame length */
+
+/** EMAC clock speed */
+#define EMAC_CLOCK_SPEED_160MHZ        (160*1000*1000)
+#define EMAC_CLOCK_SPEED_80MHZ          (80*1000*1000)
+#define EMAC_CLOCK_SPEED_40MHZ          (40*1000*1000)
+#define EMAC_CLOCK_SPEED_20MHZ          (20*1000*1000)
+
+/** EMAC maintain code default value*/
+#define EMAC_MAN_CODE_VALUE    (10)
+
+/** EMAC maintain start of frame default value*/
+#define EMAC_MAN_SOF_VALUE     (1)
+
+/** EMAC maintain read/write*/
+#define EMAC_MAN_RW_TYPE       (2)
+
+/** EMAC maintain read only*/
+#define EMAC_MAN_READ_ONLY     (1)
+
+/** EMAC address length */
+#define EMAC_ADDR_LENGTH       (6)
+
+/**
+ * \brief Return codes for EMAC APIs.
+ */
+typedef enum {
+	EMAC_OK = 0,         /** Operation OK */
+	EMAC_TIMEOUT = 1,    /** EMAC operation timeout */
+	EMAC_TX_BUSY,        /** TX in progress */
+	EMAC_RX_NULL,        /** No data received */
+	EMAC_SIZE_TOO_SMALL, /** Buffer size not enough */
+	EMAC_PARAM,          /** Parameter error, TX packet invalid or RX size too small */
+	EMAC_INVALID = 0xFF, /* Invalid */
+} emac_status_t;
+
+#if defined __ICCARM__
+#pragma pack(4)    /* IAR */
+#define __attribute__(...)    /* IAR */
+#endif /* IAR */
+
+/** Receive buffer descriptor struct */
+typedef struct emac_rx_descriptor {
+	union emac_rx_addr {
+		uint32_t val;
+		struct emac_rx_addr_bm {
+			uint32_t b_ownership:1, /**< User clear, EMAC sets this to 1 once it has successfully written a frame to memory */
+			b_wrap:1,   /**< Marks last descriptor in receive buffer */
+			addr_dw:30; /**< Address in number of DW */
+		} bm;
+	} addr; /**< Address, Wrap & Ownership */
+	union emac_rx_status {
+		uint32_t val;
+		struct emac_rx_status_bm {
+			uint32_t len:12,       /** Length of frame including FCS */
+			offset:2,              /** Receive buffer offset,  bits 13:12 of frame length for jumbo frame */
+			b_sof:1,               /** Start of frame */
+			b_eof:1,               /** End of frame */
+			b_cfi:1,               /** Concatenation Format Indicator */
+			vlan_priority:3,       /** VLAN priority (if VLAN detected) */
+			b_priority_detected:1, /** Priority tag detected */
+			b_vlan_detected:1,     /**< VLAN tag detected */
+			b_type_id_match:1,     /**< Type ID match */
+			b_addr4match:1,        /**< Address register 4 match */
+			b_addr3match:1,        /**< Address register 3 match */
+			b_addr2match:1,        /**< Address register 2 match */
+			b_addr1match:1,        /**< Address register 1 match */
+			reserved:1,
+			b_ext_addr_match:1,    /**< External address match */
+			b_uni_hash_match:1,    /**< Unicast hash match */
+			b_multi_hash_match:1,  /**< Multicast hash match */
+			b_boardcast_detect:1;  /**< Global broadcast address detected */
+		} bm;
+	} status;
+} __attribute__ ((packed, aligned(8))) emac_rx_descriptor_t; /* GCC */
+
+/** Transmit buffer descriptor struct */
+typedef struct emac_tx_descriptor {
+	uint32_t addr;
+	union emac_tx_status {
+		uint32_t val;
+		struct emac_tx_status_bm {
+			uint32_t len:11, /**< Length of buffer */
+			reserved:4,
+			b_last_buffer:1, /**< Last buffer (in the current frame) */
+			b_no_crc:1,      /**< No CRC */
+			reserved1:10,
+			b_exhausted:1,   /**< Buffer exhausted in mid frame */
+			b_underrun:1,    /**< Transmit underrun */
+			b_error:1,       /**< Retry limit exceeded, error detected */
+			b_wrap:1,        /**< Marks last descriptor in TD list */
+			b_used:1;        /**< User clear, EMAC sets this to 1 once a frame has been successfully transmitted */
+		} bm;
+	} status;
+} __attribute__ ((packed, aligned(8))) emac_tx_descriptor_t; /* GCC */
+
+#ifdef __ICCARM__ /* IAR */
+#pragma pack()
+#endif
+
+/**
+ * \brief Input parameters when initializing the emac module mode.
+ */
+typedef struct emac_options {
+	/*  Enable/Disable CopyAllFrame */
+	uint8_t uc_copy_all_frame;
+	/* Enable/Disable NoBroadCast */
+	uint8_t uc_no_boardcast;
+	/* MAC address */
+	uint8_t uc_mac_addr[EMAC_ADDR_LENGTH];
+} emac_options_t;
+
+/** RX callback */
+typedef void (*emac_dev_tx_cb_t) (uint32_t ul_status);
+/** Wakeup callback */
+typedef void (*emac_dev_wakeup_cb_t) (void);
+
+/**
+ * EMAC driver structure.
+ */
+typedef struct emac_device {
+
+	/** Pointer to HW register base */
+	Emac *p_hw;
+	/**
+	 * Pointer to allocated TX buffer.
+	 * Section 3.6 of AMBA 2.0 spec states that burst should not cross
+	 * 1K Boundaries.
+	 * Receive buffer manager writes are burst of 2 words => 3 lsb bits
+	 * of the address shall be set to 0.
+	 */
+	uint8_t *p_tx_buffer;
+	/** Pointer to allocated RX buffer */
+	uint8_t *p_rx_buffer;
+	/** Pointer to Rx TDs (must be 8-byte aligned) */
+	emac_rx_descriptor_t *p_rx_dscr;
+	/** Pointer to Tx TDs (must be 8-byte aligned) */
+	emac_tx_descriptor_t *p_tx_dscr;
+	/** Optional callback to be invoked once a frame has been received */
+	emac_dev_tx_cb_t func_rx_cb;
+	/** Optional callback to be invoked once several TDs have been released */
+	emac_dev_wakeup_cb_t func_wakeup_cb;
+	/** Optional callback list to be invoked once TD has been processed */
+	emac_dev_tx_cb_t *func_tx_cb_list;
+	/** RX TD list size */
+	uint16_t us_rx_list_size;
+	/** RX index for current processing TD */
+	uint16_t us_rx_idx;
+	/** TX TD list size */
+	uint16_t us_tx_list_size;
+	/** Circular buffer head pointer by upper layer (buffer to be sent) */
+	uint16_t us_tx_head;
+	/** Circular buffer tail pointer incremented by handlers (buffer sent) */
+	uint16_t us_tx_tail;
+
+	/** Number of free TD before wakeup callback is invoked */
+	uint8_t uc_wakeup_threshold;
+} emac_device_t;
+
+/**
+ * \brief Write network control value.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param ul_ncr   Network control value.
+ */
+static inline void emac_network_control(Emac* p_emac, uint32_t ul_ncr)
+{
+	p_emac->EMAC_NCR = ul_ncr;
+}
+
+/**
+ * \brief Get network control value.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ */
+
+static inline uint32_t emac_get_network_control(Emac* p_emac)
+{
+	return p_emac->EMAC_NCR;
+}
+
+/**
+ * \brief Enable/Disable EMAC receive.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable EMAC receiver, else to enable it.
+ */
+static inline void emac_enable_receive(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCR |= EMAC_NCR_RE;
+	} else {
+		p_emac->EMAC_NCR &= ~EMAC_NCR_RE;
+	}
+}
+
+/**
+ * \brief Enable/Disable EMAC transmit.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable EMAC transmit, else to enable it.
+ */
+static inline void emac_enable_transmit(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCR |= EMAC_NCR_TE;
+	} else {
+		p_emac->EMAC_NCR &= ~EMAC_NCR_TE;
+	}
+}
+
+/**
+ * \brief Enable/Disable EMAC management.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable EMAC management, else to enable it.
+ */
+static inline void emac_enable_management(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCR |= EMAC_NCR_MPE;
+	} else {
+		p_emac->EMAC_NCR &= ~EMAC_NCR_MPE;
+	}
+}
+
+/**
+ * \brief Clear all statistics registers.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ */
+static inline void emac_clear_statistics(Emac* p_emac)
+{
+	p_emac->EMAC_NCR |= EMAC_NCR_CLRSTAT;
+}
+
+/**
+ * \brief Increase all statistics registers.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ */
+static inline void emac_increase_statistics(Emac* p_emac)
+{
+	p_emac->EMAC_NCR |= EMAC_NCR_INCSTAT;
+}
+
+/**
+ * \brief Enable/Disable statistics registers writing.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable the statistics registers writing, else to enable it.
+ */
+static inline void emac_enable_statistics_write(Emac* p_emac,
+		uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCR |= EMAC_NCR_WESTAT;
+	} else {
+		p_emac->EMAC_NCR &= ~EMAC_NCR_WESTAT;
+	}
+}
+
+/**
+ * \brief In half-duplex mode, forces collisions on all received frames.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable the back pressure, else to enable it.
+ */
+static inline void emac_enable_back_pressure(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCR |= EMAC_NCR_BP;
+	} else {
+		p_emac->EMAC_NCR &= ~EMAC_NCR_BP;
+	}
+}
+
+/**
+ * \brief Start transmission.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ */
+static inline void emac_start_transmission(Emac* p_emac)
+{
+	p_emac->EMAC_NCR |= EMAC_NCR_TSTART;
+}
+
+/**
+ * \brief Halt transmission.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ */
+static inline void emac_halt_transmission(Emac* p_emac)
+{
+	p_emac->EMAC_NCR |= EMAC_NCR_THALT;
+}
+
+/**
+ * \brief Set up network configuration register.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+  * \param ul_cfg   Network configuration value.
+ */
+static inline void emac_set_configure(Emac* p_emac, uint32_t ul_cfg)
+{
+	p_emac->EMAC_NCFGR = ul_cfg;
+}
+
+/**
+ * \brief Get network configuration.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ *
+ * \return Network configuration.
+ */
+static inline uint32_t emac_get_configure(Emac* p_emac)
+{
+	return p_emac->EMAC_NCFGR;
+}
+
+/**
+ * \brief Set speed.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_speed 1 to indicate 100Mbps, 0 to 10Mbps.
+ */
+static inline void emac_set_speed(Emac* p_emac, uint8_t uc_speed)
+{
+	if (uc_speed) {
+		p_emac->EMAC_NCFGR |= EMAC_NCFGR_SPD;
+	} else {
+		p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_SPD;
+	}
+}
+
+/**
+ * \brief Enable/Disable Full-Duplex mode.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable the Full-Duplex mode, else to enable it.
+ */
+static inline void emac_enable_full_duplex(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCFGR |= EMAC_NCFGR_FD;
+	} else {
+		p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_FD;
+	}
+}
+
+/**
+ * \brief Enable/Disable Copy(Receive) All Valid Frames.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable copying all valid frames, else to enable it.
+ */
+static inline void emac_enable_copy_all(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCFGR |= EMAC_NCFGR_CAF;
+	} else {
+		p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_CAF;
+	}
+}
+
+/**
+ * \brief Enable/Disable jumbo frames (up to 10240 bytes).
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable the jumbo frames, else to enable it.
+ */
+static inline void emac_enable_jumbo_frames(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCFGR |= EMAC_NCFGR_JFRAME;
+	} else {
+		p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_JFRAME;
+	}
+}
+
+/**
+ * \brief Disable/Enable broadcast receiving.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   1 to disable the broadcast, else to enable it.
+ */
+static inline void emac_disable_broadcast(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCFGR |= EMAC_NCFGR_NBC;
+	} else {
+		p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_NBC;
+	}
+}
+
+/**
+ * \brief Enable/Disable multicast hash.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable the multicast hash, else to enable it.
+ */
+static inline void emac_enable_multicast_hash(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCFGR |= EMAC_NCFGR_UNI;
+	} else {
+		p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_UNI;
+	}
+}
+
+/**
+ * \brief Enable/Disable big frames (over 1518, up to 1536).
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable big frames else to enable it.
+ */
+static inline void emac_enable_big_frame(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCFGR |= EMAC_NCFGR_BIG;
+	} else {
+		p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_BIG;
+	}
+}
+
+/**
+ * \brief Set MDC clock divider.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param ul_mck   EMAC MCK.
+ *
+ * \return EMAC_OK if successfully.
+ */
+static inline uint8_t emac_set_clock(Emac* p_emac, uint32_t ul_mck)
+{
+	uint32_t ul_clk;
+
+	if (ul_mck > EMAC_CLOCK_SPEED_160MHZ) {
+		return EMAC_INVALID;
+	} else if (ul_mck > EMAC_CLOCK_SPEED_80MHZ) {
+		ul_clk = EMAC_NCFGR_CLK_MCK_64;
+	} else if (ul_mck > EMAC_CLOCK_SPEED_40MHZ) {
+		ul_clk = EMAC_NCFGR_CLK_MCK_32;
+	} else if (ul_mck > EMAC_CLOCK_SPEED_20MHZ) {
+		ul_clk = EMAC_NCFGR_CLK_MCK_16;
+	} else {
+		ul_clk = EMAC_NCFGR_CLK_MCK_8;
+	}
+
+	p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_CLK_Msk;
+	p_emac->EMAC_NCFGR |= ul_clk;
+
+	return EMAC_OK;
+}
+
+/**
+ * \brief Enable/Disable retry test.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable the EMAC receiver, else to enable it.
+ */
+static inline void emac_enable_retry_test(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCFGR |= EMAC_NCFGR_RTY;
+	} else {
+		p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_RTY;
+	}
+}
+
+/**
+ * \brief Enable/Disable pause (when a valid pause frame is received).
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable pause frame, else to enable it.
+ */
+static inline void emac_enable_pause_frame(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCFGR |= EMAC_NCFGR_PAE;
+	} else {
+		p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_PAE;
+	}
+}
+
+/**
+ * \brief Set receive buffer offset to 0 ~ 3.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ */
+static inline void emac_set_rx_buffer_offset(Emac* p_emac, uint8_t uc_offset)
+{
+	p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_RBOF_Msk;
+	p_emac->EMAC_NCFGR |=
+			(EMAC_NCFGR_RBOF_Msk & ((uc_offset) << EMAC_NCFGR_RBOF_Pos));
+}
+
+/**
+ * \brief Enable/Disable receive length field checking.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable receive length field checking, else to enable it.
+ */
+static inline void emac_enable_rx_length_check(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCFGR |= EMAC_NCFGR_RLCE;
+	} else {
+		p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_RLCE;
+	}
+}
+
+/**
+ * \brief Enable/Disable discarding FCS field of received frames.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable discarding FCS field of received frames, else to enable it.
+ */
+static inline void emac_enable_discard_fcs(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCFGR |= EMAC_NCFGR_DRFCS;
+	} else {
+		p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_DRFCS;
+	}
+}
+
+
+/**
+ * \brief Enable/Disable frames to be received in half-duplex mode
+ * while transmitting.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable the received in half-duplex mode, else to enable it.
+ */
+static inline void emac_enable_efrhd(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCFGR |= EMAC_NCFGR_EFRHD;
+	} else {
+		p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_EFRHD;
+	}
+}
+
+/**
+ * \brief Enable/Disable ignore RX FCS.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable ignore RX FCS, else to enable it.
+ */
+static inline void emac_enable_ignore_rx_fcs(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_NCFGR |= EMAC_NCFGR_IRXFCS;
+	} else {
+		p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_IRXFCS;
+	}
+}
+
+/**
+ * \brief Get Network Status.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ *
+ * \return Network status.
+ */
+static inline uint32_t emac_get_status(Emac* p_emac)
+{
+	return p_emac->EMAC_NSR;
+}
+
+/**
+ * \brief Get MDIO IN pin status.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ *
+ * \return MDIO IN pin status.
+ */
+static inline uint8_t emac_get_MDIO(Emac* p_emac)
+{
+	return ((p_emac->EMAC_NSR & EMAC_NSR_MDIO) > 0);
+}
+
+/**
+ * \brief Check if PHY is idle.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ *
+ * \return  1 if PHY is idle.
+ */
+static inline uint8_t emac_is_phy_idle(Emac* p_emac)
+{
+	return ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) > 0);
+}
+
+/**
+ * \brief Return transmit status.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ *
+ * \return  Transmit status.
+ */
+static inline uint32_t emac_get_tx_status(Emac* p_emac)
+{
+	return p_emac->EMAC_TSR;
+}
+
+/**
+ * \brief Clear transmit status.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param ul_status   Transmit status.
+ */
+static inline void emac_clear_tx_status(Emac* p_emac, uint32_t ul_status)
+{
+	p_emac->EMAC_TSR = ul_status;
+}
+
+/**
+ * \brief Return receive status.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ */
+static inline uint32_t emac_get_rx_status(Emac* p_emac)
+{
+	return p_emac->EMAC_RSR;
+}
+
+/**
+ * \brief Clear receive status.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param ul_status   Receive status.
+ */
+static inline void emac_clear_rx_status(Emac* p_emac, uint32_t ul_status)
+{
+	p_emac->EMAC_RSR = ul_status;
+}
+
+/**
+ * \brief Set Rx Queue.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param ul_addr   Rx queue address.
+ */
+static inline void emac_set_rx_queue(Emac* p_emac, uint32_t ul_addr)
+{
+	p_emac->EMAC_RBQP = EMAC_RBQP_ADDR_Msk & ul_addr;
+}
+
+/**
+ * \brief Get Rx Queue Address.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ *
+ * \return  Rx queue address.
+ */
+static inline uint32_t emac_get_rx_queue(Emac* p_emac)
+{
+	return p_emac->EMAC_RBQP;
+}
+
+/**
+ * \brief Set Tx Queue.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param ul_addr  Tx queue address.
+ */
+static inline void emac_set_tx_queue(Emac* p_emac, uint32_t ul_addr)
+{
+	p_emac->EMAC_TBQP = EMAC_TBQP_ADDR_Msk & ul_addr;
+}
+
+/**
+ * \brief Get Tx Queue.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ *
+ * \return  Rx queue address.
+ */
+static inline uint32_t emac_get_tx_queue(Emac* p_emac)
+{
+	return p_emac->EMAC_TBQP;
+}
+
+/**
+ * \brief Enable interrupt(s).
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param ul_source   Interrupt source(s) to be enabled.
+ */
+static inline void emac_enable_interrupt(Emac* p_emac, uint32_t ul_source)
+{
+	p_emac->EMAC_IER = ul_source;
+}
+
+/**
+ * \brief Disable interrupt(s).
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param ul_source   Interrupt source(s) to be disabled.
+ */
+static inline void emac_disable_interrupt(Emac* p_emac, uint32_t ul_source)
+{
+	p_emac->EMAC_IDR = ul_source;
+}
+
+/**
+ * \brief Return interrupt status.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ *
+ * \return Interrupt status.
+ */
+static inline uint32_t emac_get_interrupt_status(Emac* p_emac)
+{
+	return p_emac->EMAC_ISR;
+}
+
+/**
+ * \brief Return interrupt mask.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ *
+ * \return Interrupt mask.
+ */
+static inline uint32_t emac_get_interrupt_mask(Emac* p_emac)
+{
+	return p_emac->EMAC_IMR;
+}
+
+/**
+ * \brief Execute PHY maintenance command.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_phy_addr   PHY address.
+ * \param uc_reg_addr   Register address.
+ * \param uc_rw   1 to Read, 0 to write.
+ * \param us_data   Data to be performed, write only.
+ */
+static inline void emac_maintain_phy(Emac* p_emac,
+		uint8_t uc_phy_addr, uint8_t uc_reg_addr, uint8_t uc_rw,
+		uint16_t us_data)
+{
+	/* Wait until bus idle */
+	while ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) == 0);
+	/* Write maintain register */
+	p_emac->EMAC_MAN = EMAC_MAN_CODE(EMAC_MAN_CODE_VALUE)
+			| EMAC_MAN_SOF(EMAC_MAN_SOF_VALUE)
+			| EMAC_MAN_PHYA(uc_phy_addr)
+			| EMAC_MAN_REGA(uc_reg_addr)
+			| EMAC_MAN_RW((uc_rw ? EMAC_MAN_RW_TYPE : EMAC_MAN_READ_ONLY))
+			| EMAC_MAN_DATA(us_data);
+}
+
+/**
+ * \brief Get PHY maintenance data returned.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ *
+ * \return Get PHY data.
+ */
+static inline uint16_t emac_get_phy_data(Emac* p_emac)
+{
+	/* Wait until bus idle */
+	while ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) == 0);
+	/* Return data */
+	return (uint16_t) (p_emac->EMAC_MAN & EMAC_MAN_DATA_Msk);
+}
+
+/**
+ * \brief Set pause time.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param us_pause_time   Pause time.
+ */
+static inline void emac_set_pause_time(Emac* p_emac, uint16_t us_pause_time)
+{
+	p_emac->EMAC_PTR = us_pause_time;
+}
+
+/**
+ * \brief Set Hash.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param ul_hash_top   Hash top.
+ * \param ul_hash_bottom   Hash bottom.
+ */
+static inline void emac_set_hash(Emac* p_emac, uint32_t ul_hash_top,
+		uint32_t ul_hash_bottom)
+{
+	p_emac->EMAC_HRB = ul_hash_bottom;
+	p_emac->EMAC_HRT = ul_hash_top;
+}
+
+/**
+ * \brief Set 64 bits Hash.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param ull_hash   64 bits hash value.
+ */
+static inline void emac_set_hash64(Emac* p_emac, uint64_t ull_hash)
+{
+	p_emac->EMAC_HRB = (uint32_t) ull_hash;
+	p_emac->EMAC_HRT = (uint32_t) (ull_hash >> 32);
+}
+
+/**
+ * \brief Set MAC Address.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_index  EMAC specific address register index.
+ * \param p_mac_addr  EMAC address.
+ */
+static inline void emac_set_address(Emac* p_emac, uint8_t uc_index,
+		uint8_t* p_mac_addr)
+{
+	p_emac->EMAC_SA[uc_index].EMAC_SAxB = (p_mac_addr[3] << 24)
+			| (p_mac_addr[2] << 16)
+			| (p_mac_addr[1] << 8)
+			| (p_mac_addr[0]);
+	p_emac->EMAC_SA[uc_index].EMAC_SAxT = (p_mac_addr[5] << 8)
+			| (p_mac_addr[4]);
+}
+
+/**
+ * \brief Set MAC Address via 2 dword.
+  *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_index  EMAC specific address register index.
+ * \param ul_mac_top  EMAC top address.
+ * \param ul_mac_bottom  EMAC bottom address.
+ */
+static inline void emac_set_address32(Emac* p_emac, uint8_t uc_index,
+		uint32_t ul_mac_top, uint32_t ul_mac_bottom)
+{
+	p_emac->EMAC_SA[uc_index].EMAC_SAxB = ul_mac_bottom;
+	p_emac->EMAC_SA[uc_index].EMAC_SAxT = ul_mac_top;
+}
+
+/**
+ * \brief Set MAC Address via int64.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_index  EMAC specific address register index.
+ * \param ull_mac  64-bit EMAC address.
+ */
+static inline void emac_set_address64(Emac* p_emac, uint8_t uc_index,
+		uint64_t ull_mac)
+{
+	p_emac->EMAC_SA[uc_index].EMAC_SAxB = (uint32_t) ull_mac;
+	p_emac->EMAC_SA[uc_index].EMAC_SAxT = (uint32_t) (ull_mac >> 32);
+}
+
+/**
+ * \brief Set type ID.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param us_type_id   Type to be set.
+ */
+static inline void emac_set_type_id(Emac* p_emac, uint16_t us_type_id)
+{
+	p_emac->EMAC_TID = EMAC_TID_TID(us_type_id);
+}
+
+/**
+ * \brief Get type ID.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ *
+ * \return Type ID.
+ */
+static inline uint16_t emac_get_type_id(Emac* p_emac)
+{
+	return (p_emac->EMAC_TID & EMAC_TID_TID_Msk);
+}
+
+/**
+ * \brief Enable/Disable RMII.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable the RMII mode, else to enable it.
+ */
+static inline void emac_enable_rmii(Emac* p_emac, uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_USRIO |= EMAC_USRIO_RMII;
+	} else {
+		p_emac->EMAC_USRIO &= ~EMAC_USRIO_RMII;
+	}
+}
+
+/**
+ * \brief Enable/Disable transceiver input clock.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_enable   0 to disable transceiver input clock, else to enable it.
+ */
+static inline void emac_enable_transceiver_clock(Emac* p_emac,
+		uint8_t uc_enable)
+{
+	if (uc_enable) {
+		p_emac->EMAC_USRIO |= EMAC_USRIO_CLKEN;
+	} else {
+		p_emac->EMAC_USRIO &= ~EMAC_USRIO_CLKEN;
+	}
+}
+
+uint8_t emac_phy_read(Emac* p_emac, uint8_t uc_phy_address, uint8_t uc_address,
+		uint32_t* p_value);
+uint8_t emac_phy_write(Emac* p_emac, uint8_t uc_phy_address,
+		uint8_t uc_address, uint32_t ul_value);
+void emac_dev_init(Emac* p_emac, emac_device_t* p_emac_dev,
+		emac_options_t* p_opt);
+uint32_t emac_dev_read(emac_device_t* p_emac_dev, uint8_t* p_frame,
+		uint32_t ul_frame_size, uint32_t* p_rcv_size);
+uint32_t emac_dev_write(emac_device_t* p_emac_dev, void *p_buffer,
+		uint32_t ul_size, emac_dev_tx_cb_t func_tx_cb);
+uint32_t emac_dev_get_tx_load(emac_device_t* p_emac_dev);
+void emac_dev_set_rx_callback(emac_device_t* p_emac_dev,
+		emac_dev_tx_cb_t func_rx_cb);
+uint8_t emac_dev_set_tx_wakeup_callback(emac_device_t* p_emac_dev,
+		emac_dev_wakeup_cb_t func_wakeup, uint8_t uc_threshold);
+void emac_dev_reset(emac_device_t* p_emac_dev);
+void emac_handler(emac_device_t* p_emac_dev);
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/**
+ * \page emac_quickstart Quickstart guide for EMAC driver.
+ *
+ * This is the quickstart guide for the \ref emac_group "Ethernet MAC",
+ * with step-by-step instructions on how to configure and use the driver in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section emac_basic_use_case Basic use case
+ * In the basic use case, the EMAC driver are configured for:
+ * - PHY component DM9161A is used
+ * - EMAC uses RMII mode
+ * - The number of receive buffer is 16
+ * - The number of transfer buffer is 8
+ * - MAC address is set to 00-04-25-1c-a0-02
+ * - IP address is set to 192.168.0.2
+ * - IP address is set to 192.168.0.2
+ * - Gateway is set to 192.168.0.1
+ * - Network mask is 255.255.255.0
+ * - PHY operation max retry count is 1000000
+ * - EMAC is configured to not support copy all frame and support broadcast
+ * - The reset PIN of DM9161A is connected to the NRST of SAM3X
+ * - The data will be read from the ethernet
+ *
+ * \section emac_basic_use_case_setup Setup steps
+ *
+ * \subsection emac_basic_use_case_setup_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (sysclock)"
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"
+ * -# \ref pmc_group "Power Management Controller (pmc)"
+ * -# \ref sam_drivers_rstc_group "Reset Controller (RSTC)"
+ * -# \ref dm9161a_ethernet_phy_group "PHY component (DM9161A)"
+ *
+ * \subsection emac_basic_use_case_setup_code Example code
+ * Content of conf_eth.h
+ * \code
+ * #define EMAC_RX_BUFFERS                               16
+ * #define EMAC_TX_BUFFERS                               8
+ * #define MAC_PHY_RETRY_MAX                             1000000
+ * #define ETHERNET_CONF_ETHADDR0                        0x00
+ * #define ETHERNET_CONF_ETHADDR0                        0x00
+ * #define ETHERNET_CONF_ETHADDR1                        0x04
+ * #define ETHERNET_CONF_ETHADDR2                        0x25
+ * #define ETHERNET_CONF_ETHADDR3                        0x1C
+ * #define ETHERNET_CONF_ETHADDR4                        0xA0
+ * #define ETHERNET_CONF_ETHADDR5                        0x02
+ * #define ETHERNET_CONF_IPADDR0                         192
+ * #define ETHERNET_CONF_IPADDR1                         168
+ * #define ETHERNET_CONF_IPADDR2                         0
+ * #define ETHERNET_CONF_IPADDR3                         2
+ * #define ETHERNET_CONF_GATEWAY_ADDR0                   192
+ * #define ETHERNET_CONF_GATEWAY_ADDR1                   168
+ * #define ETHERNET_CONF_GATEWAY_ADDR2                   0
+ * #define ETHERNET_CONF_GATEWAY_ADDR3                   1
+ * #define ETHERNET_CONF_NET_MASK0                       255
+ * #define ETHERNET_CONF_NET_MASK1                       255
+ * #define ETHERNET_CONF_NET_MASK2                       255
+ * #define ETHERNET_CONF_NET_MASK3                       0
+ * #define ETH_PHY_MODE                                  BOARD_EMAC_MODE_RMII
+ * \endcode
+ *
+ * A specific emac device and the receive data buffer must be defined; another ul_frm_size should be defined
+ * to trace the actual size of the data received.
+ * \code
+ * static emac_device_t gs_emac_dev;
+ * static volatile uint8_t gs_uc_eth_buffer[EMAC_FRAME_LENTGH_MAX];
+ *
+ * uint32_t ul_frm_size;
+ * \endcode
+ *
+ * Add to application C-file:
+ * \code
+ *   void emac_init(void)
+ *   {
+ *       sysclk_init();
+ *
+ *       board_init();
+ *
+ *       rstc_set_external_reset(RSTC, 13);
+ *       rstc_reset_extern(RSTC);
+ *       while (rstc_get_status(RSTC) & RSTC_SR_NRSTL) {
+ *       };
+ *
+ *       ul_delay = sysclk_get_cpu_hz() / 1000 / 3 * 400;
+ *       while (ul_delay--);
+ *
+ *       pmc_enable_periph_clk(ID_EMAC);
+ *
+ *       emac_option.uc_copy_all_frame = 0;
+ *       emac_option.uc_no_boardcast = 0;
+ *       memcpy(emac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address));
+ *       gs_emac_dev.p_hw = EMAC;
+ *
+ *       emac_dev_init(EMAC, &gs_emac_dev, &emac_option);
+ *
+ *       NVIC_EnableIRQ(EMAC_IRQn);
+ *
+ *       ethernet_phy_init(EMAC, BOARD_EMAC_PHY_ADDR, sysclk_get_cpu_hz()
+ *
+ *       ethernet_phy_auto_negotiate(EMAC, BOARD_EMAC_PHY_ADDR
+ *
+ *       ethernet_phy_set_link(EMAC, BOARD_EMAC_PHY_ADDR, 1)
+ * \endcode
+ *
+ * \subsection emac_basic_use_case_setup_flow Workflow
+ * -# Ensure that conf_emac.h is present and contains the
+ * following configuration symbol. This configuration file is used
+ * by the driver and should not be included by the user.
+ *   - \code
+ *        #define EMAC_RX_BUFFERS                               16
+ *        #define EMAC_TX_BUFFERS                               8
+ *        #define MAC_PHY_RETRY_MAX                             1000000
+ *        #define ETHERNET_CONF_ETHADDR0                        0x00
+ *        #define ETHERNET_CONF_ETHADDR0                        0x00
+ *        #define ETHERNET_CONF_ETHADDR1                        0x04
+ *        #define ETHERNET_CONF_ETHADDR2                        0x25
+ *        #define ETHERNET_CONF_ETHADDR3                        0x1C
+ *        #define ETHERNET_CONF_ETHADDR4                        0xA0
+ *        #define ETHERNET_CONF_ETHADDR5                        0x02
+ *        #define ETHERNET_CONF_IPADDR0                         192
+ *        #define ETHERNET_CONF_IPADDR1                         168
+ *        #define ETHERNET_CONF_IPADDR2                         0
+ *        #define ETHERNET_CONF_IPADDR3                         2
+ *        #define ETHERNET_CONF_GATEWAY_ADDR0                   192
+ *        #define ETHERNET_CONF_GATEWAY_ADDR1                   168
+ *        #define ETHERNET_CONF_GATEWAY_ADDR2                   0
+ *        #define ETHERNET_CONF_GATEWAY_ADDR3                   1
+ *        #define ETHERNET_CONF_NET_MASK0                       255
+ *        #define ETHERNET_CONF_NET_MASK1                       255
+ *        #define ETHERNET_CONF_NET_MASK2                       255
+ *        #define ETHERNET_CONF_NET_MASK3                       0
+ *        #define ETH_PHY_MODE                                  BOARD_EMAC_MODE_RMII
+ *   \endcode
+ * -# Enable the system clock:
+ *   - \code sysclk_init(); \endcode
+ * -# Enable PIO configurations for EMAC:
+ *   - \code board_init(); \endcode
+ * -# Reset PHY; this is required by the DM9161A component:
+ *   - \code
+ *         rstc_set_external_reset(RSTC, 13);
+ *         rstc_reset_extern(RSTC);
+ *         while (rstc_get_status(RSTC) & RSTC_SR_NRSTL) {
+ *         };
+ * \endcode
+ * -# Wait for PHY ready:
+ *   - \code
+ *         ul_delay = sysclk_get_cpu_hz() / 1000 / 3 * 400;
+ *         while (ul_delay--);
+ * \endcode
+ * -# Enable PMC clock for EMAC:
+ *   - \code pmc_enable_periph_clk(ID_EMAC); \endcode
+ * -# Set the EMAC options; it's set to copy all frame and support broadcast:
+ *   - \code
+ *         emac_option.uc_copy_all_frame = 0;
+ *         emac_option.uc_no_boardcast = 0;
+ *         memcpy(emac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address));
+ *         gs_emac_dev.p_hw = EMAC;
+ * \endcode
+ * -# Initialize EMAC device with the filled option:
+ *   - \code
+ *         emac_dev_init(EMAC, &gs_emac_dev, &emac_option);
+ * \endcode
+ * -# Enable the interrupt service for EMAC:
+ *   - \code
+ *         NVIC_EnableIRQ(EMAC_IRQn);
+ * \endcode
+ * -# Initialize the PHY component:
+ *   - \code
+ *         ethernet_phy_init(EMAC, BOARD_EMAC_PHY_ADDR, sysclk_get_cpu_hz());
+ * \endcode
+  * -# The link will be established based on auto negotiation.
+ *   - \code
+ *         ethernet_phy_auto_negotiate(EMAC, BOARD_EMAC_PHY_ADDR);
+ * \endcode
+ * -# Establish the ethernet link; the network can be worked from now on:
+ *   - \code
+ *         ethernet_phy_set_link(EMAC, BOARD_EMAC_PHY_ADDR, 1);
+ * \endcode
+ *
+ * \section emac_basic_use_case_usage Usage steps
+ * \subsection emac_basic_use_case_usage_code Example code
+ * Add to, e.g., main loop in application C-file:
+ * \code
+ *    emac_dev_read(&gs_emac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size));
+ * \endcode
+ *
+ * \subsection emac_basic_use_case_usage_flow Workflow
+ * -# Start reading the data from the ethernet:
+ *   - \code emac_dev_read(&gs_emac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size)); \endcode
+ */
+
+#endif /* EMAC_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/gpbr.h b/hardware/digistump/sam/system/libsam/include/gpbr.h
new file mode 100644
index 0000000..531af5d
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/gpbr.h
@@ -0,0 +1,80 @@
+/**
+ * \file
+ *
+ * \brief General Purpose Backup Registers (GPBR) driver for SAM.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef GPBR_H_INCLUDED
+#define GPBR_H_INCLUDED
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/** GPBR register number type */
+typedef enum gpbr_num_type {
+	GPBR0 = 0,
+	GPBR1,
+	GPBR2,
+	GPBR3,
+	GPBR4,
+	GPBR5,
+	GPBR6,
+	GPBR7
+} gpbr_num_t;
+
+uint32_t gpbr_read(gpbr_num_t ul_reg_num);
+void gpbr_write(gpbr_num_t ul_reg_num, uint32_t ul_value);
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* GPBR_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/interrupt_sam_nvic.h b/hardware/digistump/sam/system/libsam/include/interrupt_sam_nvic.h
new file mode 100644
index 0000000..5fd78bd
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/interrupt_sam_nvic.h
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef UTILS_INTERRUPT_INTERRUPT_H
+#define UTILS_INTERRUPT_INTERRUPT_H
+
+#include "../chip.h"
+
+/**
+ * \weakgroup interrupt_group
+ *
+ * @{
+ */
+
+/**
+ * \name Interrupt Service Routine definition
+ *
+ * @{
+ */
+
+/**
+ * \brief Define service routine
+ *
+ * \note For NVIC devices the interrupt service routines are predefined to
+ *       add to vector table in binary generation, so there is no service
+ *       register at run time. The routine collections are in exceptions.h.
+ *
+ * Usage:
+ * \code
+ * ISR(foo_irq_handler)
+ * {
+ *      // Function definition
+ *      ...
+ * }
+ * \endcode
+ *
+ * \param func Name for the function.
+ */
+#  define ISR(func)    \
+	void func (void)
+
+/**
+ * \brief Initialize interrupt vectors
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to initialize them, except defined the vector function with
+ * right name.
+ *
+ * This must be called prior to \ref irq_register_handler.
+ */
+#  define irq_initialize_vectors()                     \
+	do {                                           \
+	} while(0)
+
+/**
+ * \brief Register handler for interrupt
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to register them, except defined the vector function with
+ * right name.
+ *
+ * Usage:
+ * \code
+ * irq_initialize_vectors();
+ * irq_register_handler(foo_irq_handler);
+ * \endcode
+ *
+ * \note The function \a func must be defined with the \ref ISR macro.
+ * \note The functions prototypes can be found in the device exception header
+ *       files (exceptions.h).
+ */
+#  define irq_register_handler(...)                    \
+	do {                                           \
+	} while(0)
+
+//@}
+
+#  define cpu_irq_enable()                             \
+	do {                                           \
+		g_interrupt_enabled = 1;            \
+		__DMB();                               \
+		__enable_irq();                        \
+	} while (0)
+#  define cpu_irq_disable()                            \
+	do {                                           \
+		__disable_irq();                       \
+		__DMB();                               \
+		g_interrupt_enabled = 0;           \
+	} while (0)
+
+typedef uint32_t irqflags_t;
+extern int g_interrupt_enabled;
+
+static inline irqflags_t cpu_irq_save(void)
+{
+	irqflags_t flags = g_interrupt_enabled;
+	cpu_irq_disable();
+	return flags;
+}
+
+static inline int cpu_irq_is_enabled_flags(irqflags_t flags)
+{
+	return (flags);
+}
+
+static inline void cpu_irq_restore(irqflags_t flags)
+{
+	if (cpu_irq_is_enabled_flags(flags))
+		cpu_irq_enable();
+}
+
+#define cpu_irq_is_enabled()    g_interrupt_enabled
+
+/**
+ * \weakgroup interrupt_deprecated_group
+ * @{
+ */
+
+#define Enable_global_interrupt()            cpu_irq_enable()
+#define Disable_global_interrupt()           cpu_irq_disable()
+#define Is_global_interrupt_enabled()        cpu_irq_is_enabled()
+
+//@}
+
+//@}
+
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */
diff --git a/hardware/digistump/sam/system/libsam/include/pio.h b/hardware/digistump/sam/system/libsam/include/pio.h
new file mode 100644
index 0000000..0938e9a
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/pio.h
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _PIO_
+#define _PIO_
+
+/*
+ *         Headers
+ */
+
+#include "../chip.h"
+
+#include 
+
+/*
+ *         Global Definitions
+ */
+typedef enum _EPioType
+{
+  PIO_NOT_A_PIN, /* Not under control of a peripheral. */
+  PIO_PERIPH_A, /* The pin is controlled by the associated signal of peripheral A. */
+  PIO_PERIPH_B, /* The pin is controlled by the associated signal of peripheral B. */
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+  PIO_PERIPH_C, /* The pin is controlled by the associated signal of peripheral C. */
+  PIO_PERIPH_D, /* The pin is controlled by the associated signal of peripheral D. */
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+  PIO_INPUT, /* The pin is an input. */
+  PIO_OUTPUT_0, /* The pin is an output and has a default level of 0. */
+  PIO_OUTPUT_1 /* The pin is an output and has a default level of 1. */
+} EPioType ;
+
+
+/*  Default pin configuration (no attribute). */
+#define PIO_DEFAULT                 (0u << 0)
+/*  The internal pin pull-up is active. */
+#define PIO_PULLUP                  (1u << 0)
+/*  The internal glitch filter is active. */
+#define PIO_DEGLITCH                (1u << 1)
+/*  The pin is open-drain. */
+#define PIO_OPENDRAIN               (1u << 2)
+
+/*  The internal debouncing filter is active. */
+#define PIO_DEBOUNCE                (1u << 3)
+
+/*  Enable additional interrupt modes. */
+#define PIO_IT_AIME                 (1u << 4)
+
+/*  Interrupt High Level/Rising Edge detection is active. */
+#define PIO_IT_RE_OR_HL             (1u << 5)
+/*  Interrupt Edge detection is active. */
+#define PIO_IT_EDGE                 (1u << 6)
+
+/*  Low level interrupt is active */
+#define PIO_IT_LOW_LEVEL            (0               | 0 | PIO_IT_AIME)
+/*  High level interrupt is active */
+#define PIO_IT_HIGH_LEVEL           (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME)
+/*  Falling edge interrupt is active */
+#define PIO_IT_FALL_EDGE            (0               | PIO_IT_EDGE | PIO_IT_AIME)
+/*  Rising edge interrupt is active */
+#define PIO_IT_RISE_EDGE            (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*
+ *  The #attribute# field is a bitmask that can either be set to PIO_DEFAULt,
+ *  or combine (using bitwise OR '|') any number of the following constants:
+ *     - PIO_PULLUP
+ *     - PIO_DEGLITCH
+ *     - PIO_DEBOUNCE
+ *     - PIO_OPENDRAIN
+ *     - PIO_IT_LOW_LEVEL
+ *     - PIO_IT_HIGH_LEVEL
+ *     - PIO_IT_FALL_EDGE
+ *     - PIO_IT_RISE_EDGE
+ */
+
+
+/*
+ *         Global Functions
+ */
+extern void PIO_DisableInterrupt( Pio* pPio, const uint32_t dwMask ) ;
+extern void PIO_PullUp( Pio* pPio, const uint32_t dwMask, const uint32_t dwPullUpEnable ) ;
+extern void PIO_SetDebounceFilter( Pio* pPio, const uint32_t dwMask, const uint32_t dwCuttOff ) ;
+
+extern void PIO_Set( Pio* pPio, const uint32_t dwMask ) ;
+extern void PIO_Clear( Pio* pPio, const uint32_t dwMask ) ;
+extern uint32_t PIO_Get( Pio* pPio, const EPioType dwType, const uint32_t dwMask ) ;
+
+extern void PIO_SetPeripheral( Pio* pPio, const EPioType dwType, const uint32_t dwMask ) ;
+extern void PIO_SetInput( Pio* pPio, uint32_t dwMask, uint32_t dwAttribute ) ;
+extern void PIO_SetOutput( Pio* pPio, uint32_t dwMask, uint32_t dwDefaultValue,
+                                      uint32_t dwMultiDriveEnable, uint32_t dwPullUpEnable ) ;
+
+extern uint32_t PIO_Configure( Pio* pPio, const EPioType dwType, const uint32_t dwMask, const uint32_t dwAttribute ) ;
+
+extern uint32_t PIO_GetOutputDataStatus( const Pio* pPio, const uint32_t dwMask ) ;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PIO_ */
+
diff --git a/hardware/digistump/sam/system/libsam/include/pio_it.h b/hardware/digistump/sam/system/libsam/include/pio_it.h
new file mode 100644
index 0000000..ccb54ba
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/pio_it.h
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \par Purpose
+ *
+ *  Configuration and handling of interrupts on PIO status changes. The API
+ *  provided here have several advantages over the traditional PIO interrupt
+ *  configuration approach:
+ *     - It is highly portable
+ *     - It automatically demultiplexes interrupts when multiples pins have been
+ *       configured on a single PIO controller
+ *     - It allows a group of pins to share the same interrupt
+ *
+ *  However, it also has several minor drawbacks that may prevent from using it
+ *  in particular applications:
+ *     - It enables the clocks of all PIO controllers
+ *     - PIO controllers all share the same interrupt handler, which does the
+ *       demultiplexing and can be slower than direct configuration
+ *     - It reserves space for a fixed number of interrupts, which can be
+ *       increased by modifying the appropriate constant in pio_it.c.
+ *
+ *  \par Usage
+ *
+ *  -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts()
+ *     with the desired priority (0 ... 7).
+ *  -# Configure a status change interrupt on one or more pin(s) with
+ *     PIO_ConfigureIt().
+ *  -# Enable & disable interrupts on pins using PIO_EnableIt() and
+ *     PIO_DisableIt().
+ */
+
+#ifndef _PIO_IT_
+#define _PIO_IT_
+
+/*
+ *         Headers
+ */
+
+#include "pio.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*
+ *         Global functions
+ */
+
+extern void PIO_InitializeInterrupts( uint32_t dwPriority ) ;
+
+extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) ) ;
+
+extern void PIO_EnableIt( const Pio* pPio, const uint32_t dwMask ) ;
+extern void PIO_DisableIt( const Pio* pPio, const uint32_t dwMask ) ;
+
+extern void PIO_IT_InterruptHandler( void ) ;
+
+extern void PioInterruptHandler( uint32_t id, Pio *pPio ) ;
+
+extern void PIO_CaptureHandler( void ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PIO_IT_ */
+
diff --git a/hardware/digistump/sam/system/libsam/include/pmc.h b/hardware/digistump/sam/system/libsam/include/pmc.h
new file mode 100644
index 0000000..45e7698
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/pmc.h
@@ -0,0 +1,424 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+#ifndef PMC_H_INCLUDED
+#define PMC_H_INCLUDED
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/** Bit mask for peripheral clocks (PCER0) */
+#define PMC_MASK_STATUS0        (0xFFFFFFFC)
+
+/** Bit mask for peripheral clocks (PCER1) */
+#define PMC_MASK_STATUS1        (0xFFFFFFFF)
+
+/** Loop counter timeout value */
+#define PMC_TIMEOUT             (2048)
+
+/** Key to unlock CKGR_MOR register */
+#define PMC_CKGR_MOR_KEY_VALUE  CKGR_MOR_KEY(0x37)
+
+/** Key used to write SUPC registers */
+#define SUPC_KEY_VALUE          ((uint32_t) 0xA5)
+
+/** PMC xtal statup time */
+#define PMC_XTAL_STARTUP_TIME   (0x3F)
+
+/** Mask to access fast startup input */
+#define PMC_FAST_STARTUP_Msk    (0xFFFFu)
+
+/** PMC_WPMR Write Protect KEY, unlock it */
+#define PMC_WPMR_WPKEY_VALUE    PMC_WPMR_WPKEY((uint32_t) 0x504D43)
+
+/** Using external oscillator */
+#define PMC_OSC_XTAL            0
+
+/** Oscillator in bypass mode */
+#define PMC_OSC_BYPASS          1
+
+#define PMC_PCK_0               0 /* PCK0 ID */
+#define PMC_PCK_1               1 /* PCK1 ID */
+#define PMC_PCK_2               2 /* PCK2 ID */
+
+/**
+ * \name Master clock (MCK) Source and Prescaler configuration
+ *
+ * The following functions may be used to select the clock source and
+ * prescaler for the master clock.
+ */
+//@{
+
+void pmc_mck_set_prescaler(uint32_t ul_pres);
+void pmc_mck_set_source(uint32_t ul_source);
+uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres);
+uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres);
+uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres);
+#if (SAM3S_SERIES || SAM4S_SERIES)
+uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres);
+#endif
+#if (SAM3XA_SERIES || SAM3U_SERIES)
+uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres);
+#endif
+
+//@}
+
+/**
+ * \name Slow clock (SLCK) oscillator and configuration
+ *
+ */
+//@{
+
+void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass);
+uint32_t pmc_osc_is_ready_32kxtal(void);
+
+//@}
+
+/**
+ * \name Main Clock (MAINCK) oscillator and configuration
+ *
+ */
+//@{
+
+void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf);
+void pmc_osc_enable_fastrc(uint32_t ul_rc);
+void pmc_osc_disable_fastrc(void);
+void pmc_switch_mainck_to_xtal(uint32_t ul_bypass);
+void pmc_osc_disable_xtal(uint32_t ul_bypass);
+uint32_t pmc_osc_is_ready_mainck(void);
+
+//@}
+
+/**
+ * \name PLL oscillator and configuration
+ *
+ */
+//@{
+
+void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva);
+void pmc_disable_pllack(void);
+uint32_t pmc_is_locked_pllack(void);
+
+#if (SAM3S_SERIES || SAM4S_SERIES)
+void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb);
+void pmc_disable_pllbck(void);
+uint32_t pmc_is_locked_pllbck(void);
+#endif
+
+#if (SAM3XA_SERIES || SAM3U_SERIES)
+void pmc_enable_upll_clock(void);
+void pmc_disable_upll_clock(void);
+uint32_t pmc_is_locked_upll(void);
+#endif
+
+//@}
+
+/**
+ * \name Peripherals clock configuration
+ *
+ */
+//@{
+
+uint32_t pmc_enable_periph_clk(uint32_t ul_id);
+uint32_t pmc_disable_periph_clk(uint32_t ul_id);
+void pmc_enable_all_periph_clk(void);
+void pmc_disable_all_periph_clk(void);
+uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id);
+
+//@}
+
+/**
+ * \name Programmable clock Source and Prescaler configuration
+ *
+ * The following functions may be used to select the clock source and
+ * prescaler for the specified programmable clock.
+ */
+//@{
+
+void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres);
+void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source);
+uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres);
+uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres);
+uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres);
+#if (SAM3S_SERIES || SAM4S_SERIES)
+uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres);
+#endif
+#if (SAM3XA_SERIES || SAM3U_SERIES)
+uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres);
+#endif
+void pmc_enable_pck(uint32_t ul_id);
+void pmc_disable_pck(uint32_t ul_id);
+void pmc_enable_all_pck(void);
+void pmc_disable_all_pck(void);
+uint32_t pmc_is_pck_enabled(uint32_t ul_id);
+
+//@}
+
+/**
+ * \name USB clock configuration
+ *
+ */
+//@{
+
+#if (SAM3S_SERIES || SAM3XA_SERIES || SAM4S_SERIES)
+void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv);
+#endif
+#if (SAM3S_SERIES || SAM4S_SERIES)
+void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv);
+#endif
+#if (SAM3XA_SERIES)
+void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv);
+#endif
+#if (SAM3S_SERIES || SAM3XA_SERIES || SAM4S_SERIES)
+void pmc_enable_udpck(void);
+void pmc_disable_udpck(void);
+#endif
+
+//@}
+
+/**
+ * \name Interrupt and status management
+ *
+ */
+//@{
+
+void pmc_enable_interrupt(uint32_t ul_sources);
+void pmc_disable_interrupt(uint32_t ul_sources);
+uint32_t pmc_get_interrupt_mask(void);
+uint32_t pmc_get_status(void);
+
+//@}
+
+/**
+ * \name Power management
+ *
+ * The following functions are used to configure sleep mode and additionnal
+ * wake up inputs.
+ */
+//@{
+
+void pmc_set_fast_startup_input(uint32_t ul_inputs);
+void pmc_clr_fast_startup_input(uint32_t ul_inputs);
+void pmc_enable_sleepmode(uint8_t uc_type);
+void pmc_enable_waitmode(void);
+void pmc_enable_backupmode(void);
+
+//@}
+
+/**
+ * \name Write protection
+ *
+ */
+//@{
+
+void pmc_set_writeprotect(uint32_t ul_enable);
+uint32_t pmc_get_writeprotect_status(void);
+
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+//! @}
+
+/**
+ * \page sam_pmc_quickstart Quick start guide for the SAM PMC module
+ *
+ * This is the quick start guide for the \ref pmc_group "PMC module", with
+ * step-by-step instructions on how to configure and use the driver in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section pmc_use_cases PMC use cases
+ * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources
+ * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks
+ *
+ * \section pmc_basic_use_case Basic use case - Switch Main Clock sources
+ * In this use case, the PMC module is configured for a variety of system clock
+ * sources and speeds. A LED is used to visually indicate the current clock
+ * speed as the source is switched.
+ *
+ * \section pmc_basic_use_case_setup Setup
+ *
+ * \subsection pmc_basic_use_case_setup_prereq Prerequisites
+ * -# \ref gpio_group "General Purpose I/O Management (gpio)"
+ *
+ * \subsection pmc_basic_use_case_setup_code Code
+ * The following function needs to be added to the user application, to flash a
+ * board LED a variable number of times at a rate given in CPU ticks.
+ *
+ * \code
+ * #define FLASH_TICK_COUNT   0x00012345
+ *
+ * void flash_led(uint32_t tick_count, uint8_t flash_count)
+ * {
+ *     SysTick->CTRL = SysTick_CTRL_ENABLE_Msk;
+ *     SysTick->LOAD = tick_count;
+ *
+ *     while (flash_count--)
+ *     {
+ *         gpio_toggle_pin(LED0_GPIO);
+ *         while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));
+ *         gpio_toggle_pin(LED0_GPIO);
+ *         while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));
+ *     }
+ * }
+ * \endcode
+ *
+ * \section pmc_basic_use_case_usage Use case
+ *
+ * \subsection pmc_basic_use_case_usage_code Example code
+ * Add to application C-file:
+ * \code
+ *    for (;;)
+ *    {
+ *        pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);
+ *        flash_led(FLASH_TICK_COUNT, 5);
+ *        pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);
+ *        flash_led(FLASH_TICK_COUNT, 5);
+ *        pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);
+ *        flash_led(FLASH_TICK_COUNT, 5);
+ *        pmc_switch_mainck_to_xtal(0);
+ *        flash_led(FLASH_TICK_COUNT, 5);
+ *    }
+ * \endcode
+ *
+ * \subsection pmc_basic_use_case_usage_flow Workflow
+ * -# Wrap the code in an infinite loop:
+ *   \code
+ *   for (;;)
+ *   \endcode
+ * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash
+ *    a LED on the board several times:
+ *   \code
+ *   pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);
+ *   flash_led(FLASH_TICK_COUNT, 5);
+ *   \endcode
+ * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash
+ *    a LED on the board several times:
+ *   \code
+ *   pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);
+ *   flash_led(FLASH_TICK_COUNT, 5);
+ *   \endcode
+ * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash
+ *    a LED on the board several times:
+ *   \code
+ *   pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);
+ *   flash_led(FLASH_TICK_COUNT, 5);
+ *   \endcode
+ * -# Switch the Master CPU frequency to the external crystal oscillator, flash
+ *    a LED on the board several times:
+ *   \code
+ *   pmc_switch_mainck_to_xtal(0);
+ *   flash_led(FLASH_TICK_COUNT, 5);
+ *   \endcode
+ */
+
+/**
+ * \page pmc_use_case_2 Use case #2 - Configure Programmable Clocks
+ * In this use case, the PMC module is configured to start the Slow Clock from
+ * an attached 32KHz crystal, and start one of the Programmable Clock modules
+ * sourced from the Slow Clock divided down with a prescale factor of 64.
+ *
+ * \section pmc_use_case_2_setup Setup
+ *
+ * \subsection pmc_use_case_2_setup_prereq Prerequisites
+ * -# \ref pio_group "Parallel Input/Output Controller (pio)"
+ *
+ * \subsection pmc_use_case_2_setup_code Code
+ * The following code must be added to the user application:
+ * \code
+ * 	pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);
+ * \endcode
+ *
+ * \subsection pmc_use_case_2_setup_code_workflow Workflow
+ * -# Configure the PCK1 pin to output on a specific port pin (in this case,
+ *    PIOA pin 17) of the microcontroller.
+ *   \code
+ *   pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);
+ *   \endcode
+ *   \note The peripheral selection and pin will vary according to your selected
+ *       SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O
+ *       Lines" of your device's datasheet.
+ *
+ * \section pmc_use_case_2_usage Use case
+ * The generated PCK1 clock output can be viewed on an oscilloscope attached to
+ * the correct pin of the microcontroller.
+ *
+ * \subsection pmc_use_case_2_usage_code Example code
+ * Add to application C-file:
+ * \code
+ *  pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);
+ *  pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);
+ *  pmc_enable_pck(PMC_PCK_1);
+ *
+ *  for (;;)
+ *  {
+ *      // Do Nothing
+ *  }
+ * \endcode
+ *
+ * \subsection pmc_use_case_2_usage_flow Workflow
+ * -# Switch the Slow Clock source input to an external 32KHz crystal:
+ *   \code
+ *   pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);
+ *   \endcode
+ * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock,
+ *    with a prescaler of 64:
+ *   \code
+ *   pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);
+ *   \endcode
+ * -# Enable Programmable Clock module PCK1:
+ *   \code
+ *   pmc_enable_pck(PMC_PCK_1);
+ *   \endcode
+ * -# Enter an infinite loop:
+ *   \code
+ *   for (;;)
+ *   {
+ *      // Do Nothing
+ *   }
+ *   \endcode
+ */
+
+#endif /* PMC_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/pwmc.h b/hardware/digistump/sam/system/libsam/include/pwmc.h
new file mode 100644
index 0000000..a88b544
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/pwmc.h
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \par Purpose
+ *
+ * Interface for configuration the Pulse Width Modulation Controller (PWM) peripheral.
+ *
+ * \par Usage
+ *
+ *    -# Configures PWM clocks A & B to run at the given frequencies using
+ *       \ref PWMC_ConfigureClocks().
+ *    -# Configure PWMC channel using \ref PWMC_ConfigureChannel(), \ref PWMC_ConfigureChannelExt()
+ *       \ref PWMC_SetPeriod(), \ref PWMC_SetDutyCycle() and \ref PWMC_SetDeadTime().
+ *    -# Enable & disable channel using \ref PWMC_EnableChannel() and
+ *       \ref PWMC_DisableChannel().
+ *    -# Enable & disable the period interrupt for the given PWM channel using
+ *       \ref PWMC_EnableChannelIt() and \ref PWMC_DisableChannelIt().
+ *    -# Enable & disable the selected interrupts sources on a PWMC peripheral
+ *       using  \ref PWMC_EnableIt() and \ref PWMC_DisableIt().
+ *    -# Control syncronous channel using \ref PWMC_ConfigureSyncChannel(),
+ *       \ref PWMC_SetSyncChannelUpdatePeriod() and \ref PWMC_SetSyncChannelUpdateUnlock().
+ *    -# Control PWM override output using \ref PWMC_SetOverrideValue(),
+ *       \ref PWMC_EnableOverrideOutput() and \ref PWMC_DisableOverrideOutput().
+ *    -# Send data through the transmitter using \ref PWMC_WriteBuffer().
+ *
+ */
+
+#ifndef _PWMC_
+#define _PWMC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "../chip.h"
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void PWMC_ConfigureChannel( Pwm* pPwm, uint32_t ul_channel, uint32_t prescaler, uint32_t alignment, uint32_t polarity ) ;
+extern void PWMC_ConfigureChannelExt( Pwm* pPwm, uint32_t ul_channel, uint32_t prescaler, uint32_t alignment, uint32_t polarity,
+                                      uint32_t countEventSelect, uint32_t DTEnable, uint32_t DTHInverte, uint32_t DTLInverte ) ;
+
+extern void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck ) ;
+extern void PWMC_SetPeriod( Pwm* pPwm, uint32_t ul_channel, uint16_t period ) ;
+extern void PWMC_SetDutyCycle( Pwm* pPwm, uint32_t ul_channel, uint16_t duty ) ;
+extern void PWMC_SetDeadTime( Pwm* pPwm, uint32_t ul_channel, uint16_t timeH, uint16_t timeL ) ;
+extern void PWMC_ConfigureSyncChannel( Pwm* pPwm, uint32_t ul_channels, uint32_t updateMode, uint32_t requestMode, uint32_t requestComparisonSelect ) ;
+extern void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period ) ;
+extern void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm ) ;
+extern void PWMC_EnableChannel( Pwm* pPwm, uint32_t ul_channel ) ;
+extern void PWMC_DisableChannel( Pwm* pPwm, uint32_t ul_channel ) ;
+extern void PWMC_EnableChannelIt( Pwm* pPwm, uint32_t ul_channel ) ;
+extern void PWMC_DisableChannelIt( Pwm* pPwm, uint32_t ul_channel ) ;
+extern void PWMC_EnableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2 ) ;
+extern void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2 ) ;
+extern uint8_t PWMC_WriteBuffer(Pwm *pwmc, void *buffer, uint32_t length ) ;
+extern void PWMC_SetOverrideValue( Pwm* pPwm, uint32_t value ) ;
+extern void PWMC_EnableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync ) ;
+extern void PWMC_DisableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync ) ;
+extern void PWMC_SetFaultMode( Pwm* pPwm, uint32_t mode ) ;
+extern void PWMC_FaultClear( Pwm* pPwm, uint32_t fault ) ;
+extern void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value ) ;
+extern void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t ul_channel, uint32_t value ) ;
+extern void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, uint32_t value, uint32_t mode ) ;
+extern void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PWMC_ */
+
diff --git a/hardware/digistump/sam/system/libsam/include/rstc.h b/hardware/digistump/sam/system/libsam/include/rstc.h
new file mode 100644
index 0000000..6edb070
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/rstc.h
@@ -0,0 +1,78 @@
+/**
+ * \file
+ *
+ * \brief Reset Controller (RSTC) driver for SAM.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef RSTC_H_INCLUDED
+#define RSTC_H_INCLUDED
+
+#include "../chip.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Definitions of Reset Controller Status */
+/** Reset cause */
+#define RSTC_GENERAL_RESET   (0 << RSTC_SR_RSTTYP_Pos)
+#define RSTC_BACKUP_RESET    (1 << RSTC_SR_RSTTYP_Pos)
+#define RSTC_WATCHDOG_RESET  (2 << RSTC_SR_RSTTYP_Pos)
+#define RSTC_SOFTWARE_RESET  (3 << RSTC_SR_RSTTYP_Pos)
+#define RSTC_USER_RESET      (4 << RSTC_SR_RSTTYP_Pos)
+/** NRST Pin Level */
+#define RSTC_NRST_LOW   (LOW << 16)
+#define RSTC_NRST_HIGH  (HIGH << 16)
+
+void rstc_set_external_reset(Rstc* p_rstc, const uint32_t ul_length);
+void rstc_enable_user_reset(Rstc* p_rstc);
+void rstc_disable_user_reset(Rstc* p_rstc);
+void rstc_enable_user_reset_interrupt(Rstc* p_rstc);
+void rstc_disable_user_reset_interrupt(Rstc* p_rstc);
+void rstc_start_software_reset(Rstc* p_rstc);
+void rstc_reset_extern(Rstc *p_rstc);
+uint32_t rstc_get_status(Rstc* p_rstc);
+uint32_t rstc_get_reset_cause(Rstc* p_rstc);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RSTC_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/rtc.h b/hardware/digistump/sam/system/libsam/include/rtc.h
new file mode 100644
index 0000000..d705b16
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/rtc.h
@@ -0,0 +1,97 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Interface for Real Time Clock (RTC) controller.
+ *
+ */
+
+#ifndef _RTC_
+#define _RTC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "../chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Definitions
+ *----------------------------------------------------------------------------*/
+
+#define RTC_HOUR_BIT_LEN_MASK   0x3F
+#define RTC_MIN_BIT_LEN_MASK    0x7F
+#define RTC_SEC_BIT_LEN_MASK    0x7F
+#define RTC_CENT_BIT_LEN_MASK   0x7F
+#define RTC_YEAR_BIT_LEN_MASK   0xFF
+#define RTC_MONTH_BIT_LEN_MASK  0x1F
+#define RTC_DATE_BIT_LEN_MASK   0x3F
+#define RTC_WEEK_BIT_LEN_MASK   0x07
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void RTC_SetHourMode( Rtc* pRtc, uint32_t dwMode ) ;
+
+extern uint32_t RTC_GetHourMode( Rtc* pRtc ) ;
+
+extern void RTC_EnableIt( Rtc* pRtc, uint32_t dwSources ) ;
+
+extern void RTC_DisableIt( Rtc* pRtc, uint32_t dwSources ) ;
+
+extern int RTC_SetTime( Rtc* pRtc, uint8_t ucHour, uint8_t ucMinute, uint8_t ucSecond ) ;
+
+extern void RTC_GetTime( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond ) ;
+
+extern int RTC_SetTimeAlarm( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond ) ;
+
+extern void RTC_GetDate( Rtc* pRtc, uint16_t *pwYear, uint8_t *pucMonth, uint8_t *pucDay, uint8_t *pucWeek ) ;
+
+extern int RTC_SetDate( Rtc* pRtc, uint16_t wYear, uint8_t ucMonth, uint8_t ucDay, uint8_t ucWeek ) ;
+
+extern int RTC_SetDateAlarm( Rtc* pRtc, uint8_t *pucMonth, uint8_t *pucDay ) ;
+
+extern void RTC_ClearSCCR( Rtc* pRtc, uint32_t dwMask ) ;
+
+extern uint32_t RTC_GetSR( Rtc* pRtc, uint32_t dwMask ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _RTC_ */
+
diff --git a/hardware/digistump/sam/system/libsam/include/rtt.h b/hardware/digistump/sam/system/libsam/include/rtt.h
new file mode 100644
index 0000000..9d66945
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/rtt.h
@@ -0,0 +1,82 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \par Purpose
+ *
+ * Interface for Real Time Timer (RTT) controller.
+ *
+ * \par Usage
+ *
+ * -# Changes the prescaler value of the given RTT and restarts it
+ *    using \ref RTT_SetPrescaler().
+ * -# Get current value of the RTT using \ref RTT_GetTime().
+ * -# Enables the specified RTT interrupt using \ref RTT_EnableIT().
+ * -# Get the status register value of the given RTT using \ref RTT_GetStatus().
+ * -# Configures the RTT to generate an alarm at the given time
+ *    using \ref RTT_SetAlarm().
+ */
+
+#ifndef _RTT_
+#define _RTT_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "../chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void RTT_SetPrescaler( Rtt* pRtt, uint16_t wPrescaler ) ;
+
+extern uint32_t RTT_GetTime( Rtt* pRtt ) ;
+
+extern void RTT_EnableIT( Rtt* pRtt, uint32_t dwSources ) ;
+
+extern uint32_t RTT_GetStatus( Rtt *pRtt ) ;
+
+extern void RTT_SetAlarm( Rtt *pRtt, uint32_t dwTime ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef RTT_H */
+
diff --git a/hardware/digistump/sam/system/libsam/include/spi.h b/hardware/digistump/sam/system/libsam/include/spi.h
new file mode 100644
index 0000000..fad8f8f
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/spi.h
@@ -0,0 +1,117 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Interface for Serial Peripheral Interface (SPI) controller.
+ *
+ */
+
+#ifndef _SPI_
+#define _SPI_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "../chip.h"
+
+/*----------------------------------------------------------------------------
+ *        Macros
+ *----------------------------------------------------------------------------*/
+
+/**
+ *
+ * Here are several macros which should be used when configuring a SPI
+ * peripheral.
+ *
+ * \section spi_configuration_macros SPI Configuration Macros
+ * - \ref SPI_PCS
+ * - \ref SPI_SCBR
+ * - \ref SPI_DLYBS
+ * - \ref SPI_DLYBCT
+ */
+
+/** Calculate the PCS field value given the chip select NPCS value */
+#define SPI_PCS(npcs)       ((~(1 << (npcs)) & 0xF) << 16)
+
+/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */
+#define SPI_SCBR(baudrate, masterClock) ((uint32_t) ((masterClock) / (baudrate)) << 8)
+
+/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
+#define SPI_DLYBS(delay, masterClock) ((uint32_t) ((((masterClock) / 1000000) * (delay)) / 1000) << 16)
+
+/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */
+#define SPI_DLYBCT(delay, masterClock) ((uint32_t) ((((masterClock) / 1000000) * (delay)) / 32000) << 24)
+
+/*------------------------------------------------------------------------------ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void SPI_Enable( Spi* spi ) ;
+extern void SPI_Disable( Spi* spi ) ;
+extern void SPI_EnableIt( Spi* spi, uint32_t dwSources ) ;
+extern void SPI_DisableIt( Spi* spi, uint32_t dwSources ) ;
+
+extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration ) ;
+extern void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration ) ;
+
+extern uint32_t SPI_Read( Spi* spi ) ;
+extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData ) ;
+
+extern uint32_t SPI_GetStatus( Spi* spi ) ;
+extern uint32_t SPI_IsFinished( Spi* pSpi ) ;
+
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+extern void SPI_PdcEnableTx( Spi* spi ) ;
+extern void SPI_PdcDisableTx( Spi* spi ) ;
+extern void SPI_PdcEnableRx( Spi* spi ) ;
+extern void SPI_PdcDisableRx( Spi* spi ) ;
+
+extern void SPI_PdcSetTx( Spi* spi, void* pvTxBuf, uint32_t dwTxCount, void* pvTxNextBuf, uint32_t dwTxNextCount ) ;
+extern void SPI_PdcSetRx( Spi* spi, void* pvRxBuf, uint32_t dwRxCount, void* pvRxNextBuf, uint32_t dwRxNextCount ) ;
+
+extern uint32_t SPI_WriteBuffer( Spi* spi, void* pvBuffer, uint32_t dwLength ) ;
+
+extern uint32_t SPI_ReadBuffer( Spi* spi, void* pvBuffer, uint32_t dwLength ) ;
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _SPI_ */
+
diff --git a/hardware/digistump/sam/system/libsam/include/ssc.h b/hardware/digistump/sam/system/libsam/include/ssc.h
new file mode 100644
index 0000000..4af8091
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/ssc.h
@@ -0,0 +1,210 @@
+/**
+ * \file
+ *
+ * \brief Synchronous Serial Controller (SSC) driver for SAM.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef SSC_H_INCLUDED
+#define SSC_H_INCLUDED
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+//! Receive stop selection.
+#define SSC_RX_STOP_COMPARE_0        0
+#define SSC_RX_STOP_COMPARE_0_1      1
+
+//! Compare register ID.
+#define COMPARE_ID0                  0
+#define COMPARE_ID1                  1
+
+//! SSC module default timeout. */
+#define SSC_DEFAULT_TIMEOUT          10000
+
+//! \brief SSC driver return codes.
+enum ssc_return_code {
+	SSC_RC_OK = 0,              //!< OK
+	SSC_RC_YES = 0,             //!< Yes
+	SSC_RC_NO = 1,              //!< No
+	SSC_RC_ERROR = 1,           //!< General error
+	SSC_RC_INVALID = 0xFFFFFFFF //!< Parameter invalid
+};
+
+//! Data frame structure.
+typedef struct {
+	//! Data bits length per transfer, should be 0 to 31.
+	uint32_t ul_datlen;
+	//! Bit sequence LSBF or MSBF.
+	//! For receiver configuration, SSC_RFMR_MSBF or 0.
+	//! For transmitter configuration, SSC_TFMR_MSBF or 0.
+	uint32_t ul_msbf;
+	//! Data number per frame, should be 0 to 15.
+	uint32_t ul_datnb;
+	//! Frame Sync. length should be 0 to 15.
+	uint32_t ul_fslen;
+	//! Frame Sync. length extension field, should be 0 to 15.
+	uint32_t ul_fslen_ext;
+	//! Frame Sync. output selection.
+	//! For receiver configuration, one of SSC_RFMR_FSOS_NONE, SSC_RFMR_FSOS_NEGATIVE, SSC_RFMR_FSOS_POSITIVE,
+	//! SSC_RFMR_FSOS_LOW, SSC_RFMR_FSOS_HIGH or SSC_RFMR_FSOS_TOGGLING.
+	//! For transmitter configuration, one of SSC_TFMR_FSOS_NONE, SSC_TFMR_FSOS_NEGATIVE, SSC_TFMR_FSOS_POSITIVE
+	//! SSC_TFMR_FSOS_LOW, SSC_TFMR_FSOS_HIGH, SSC_TFMR_FSOS_TOGGLING,
+	uint32_t ul_fsos;
+	//! Frame Sync. edge detection.
+	//! For receiver configuration, SSC_RFMR_FSEDGE_POSITIVE or SSC_RFMR_FSEDGE_NEGATIVE.
+	//! For transmitter configuration, SSC_TFMR_FSEDGE_POSITIVE or SSC_TFMR_FSEDGE_NEGATIVE.
+	uint32_t ul_fsedge;
+} data_frame_opt_t;
+
+//! Clock mode structure.
+typedef struct {
+	//! Communication clock selection.
+	//! For receiver configuration, one of SSC_RCMR_CKS_MCK, SSC_RCMR_CKS_TK or SSC_RCMR_CKS_RK.
+	//! For transmitter configuration, one of SSC_TCMR_CKS_MCK, SSC_TCMR_CKS_TK or SSC_TCMR_CKS_RK.
+	uint32_t ul_cks;
+	//! Communication clock output mode selection.
+	//! For receiver configuration, one of SSC_RCMR_CKO_NONE, SSC_RCMR_CKO_CONTINUOUS or SSC_RCMR_CKO_TRANSFER.
+	//! For transmitter configuration, one of SSC_TCMR_CKO_NONE, SSC_TCMR_CKO_CONTINUOUS or SSC_TCMR_CKO_TRANSFER.
+	uint32_t ul_cko;
+	//! Communication clock inversion.
+	//! For receiver configuration, SSC_RCMR_CKI or 0.
+	//! For transmitter configuration, SSC_TCMR_CKI or 0.
+	uint32_t ul_cki;
+	//! Communication clock gating selection.
+	//! For receiver configuration, one of SSC_RCMR_CKG_NONE, SSC_RCMR_CKG_CONTINUOUS and SSC_RCMR_CKG_TRANSFER.
+	//! For transmitter configuration, one of SSC_TCMR_CKG_NONE, SSC_TCMR_CKG_CONTINUOUS and SSC_TCMR_CKG_TRANSFER.
+	uint32_t ul_ckg;
+	//! Period divider selection, should be 0 to 255.
+	uint32_t ul_period;
+	//! Communication start delay, should be 0 to 255.
+	uint32_t ul_sttdly;
+	//! Communication start selection.
+	//! For receiver configuration, one of SSC_RCMR_START_CONTINUOUS, SSC_RCMR_START_TRANSMIT, SSC_RCMR_START_RF_LOW,
+	//! SSC_RCMR_START_RF_HIGH, SSC_RCMR_START_RF_FALLING, SSC_RCMR_START_RF_RISING, SSC_RCMR_START_RF_LEVEL,
+	//! SSC_RCMR_START_RF_EDGE or SSC_RCMR_START_CMP_0.
+	//! For transmitter configuration, one of SSC_TCMR_START_CONTINUOUS, SSC_TCMR_START_TRANSMIT, SSC_TCMR_START_RF_LOW,
+	//! SSC_TCMR_START_RF_HIGH, SSC_TCMR_START_RF_FALLING, SSC_TCMR_START_RF_RISING, SSC_TCMR_START_RF_LEVEL,
+	//! SSC_TCMR_START_RF_EDGE or SSC_TCMR_START_CMP_0.
+	uint32_t ul_start_sel;
+} clock_opt_t;
+
+//! SSC working role in I2S mode.
+#define SSC_I2S_MASTER_OUT    (1 << 0) //! Working mode for transmitter as master.
+#define SSC_I2S_MASTER_IN     (1 << 1) //! Working mode for receiver as master.
+#define SSC_I2S_SLAVE_OUT     (1 << 2) //! Working mode for transmitter as slave.
+#define SSC_I2S_SLAVE_IN      (1 << 3) //! Working mode for receiver as slave.
+
+//! Bit for SSC Audio channel left.
+#define SSC_AUDIO_CH_LEFT     (1 << 0)
+//! Bit for SSC Audio channel right.
+#define SSC_AUDIO_CH_RIGHT    (1 << 1)
+//! SSC Audio Channel modes.
+enum {
+	//! Mono, left channel enabled.
+	SSC_AUDIO_MONO_LEFT = (SSC_AUDIO_CH_LEFT),
+	//! Mono, right channel enabled.
+	SSC_AUDIO_MONO_RIGHT = (SSC_AUDIO_CH_RIGHT),
+	//! Stereo, two channels.
+	SSC_AUDIO_STERO = (SSC_AUDIO_CH_LEFT | SSC_AUDIO_CH_RIGHT)
+};
+
+uint32_t ssc_set_clock_divider(Ssc *p_ssc, uint32_t ul_bitclock, uint32_t ul_mck);
+void ssc_i2s_set_transmitter(Ssc *p_ssc, uint32_t ul_mode,
+		uint32_t ul_cks, uint32_t ul_ch_mode, uint32_t ul_datlen);
+void ssc_i2s_set_receiver(Ssc *p_ssc, uint32_t ul_mode,
+		uint32_t ul_cks, uint32_t ul_ch_mode, uint32_t ul_datlen);
+void ssc_reset(Ssc *p_ssc);
+void ssc_enable_rx(Ssc *p_ssc);
+void ssc_disable_rx(Ssc *p_ssc);
+void ssc_enable_tx(Ssc *p_ssc);
+void ssc_disable_tx(Ssc *p_ssc);
+void ssc_set_normal_mode(Ssc *p_ssc);
+void ssc_set_loop_mode(Ssc *p_ssc);
+void ssc_set_rx_stop_selection(Ssc *p_ssc, uint32_t ul_sel);
+void ssc_set_td_default_level(Ssc *p_ssc, uint32_t ul_level);
+void ssc_enable_tx_frame_sync_data(Ssc *p_ssc);
+void ssc_disable_tx_frame_sync_data(Ssc *p_ssc);
+void ssc_set_receiver(Ssc *p_ssc, clock_opt_t *p_rx_clk_opt, data_frame_opt_t *p_rx_data_frame);
+void ssc_set_transmitter(Ssc *p_ssc, clock_opt_t *p_tx_clk_opt, data_frame_opt_t *p_tx_data_frame);
+void ssc_set_rx_compare(Ssc *p_ssc, uint32_t ul_id, uint32_t ul_value);
+uint32_t ssc_get_rx_compare(Ssc *p_ssc, uint32_t ul_id);
+void ssc_enable_interrupt(Ssc *p_ssc, uint32_t ul_sources);
+void ssc_disable_interrupt(Ssc *p_ssc, uint32_t ul_sources);
+uint32_t ssc_get_interrupt_mask(Ssc *p_ssc);
+uint32_t ssc_get_status(Ssc *p_ssc);
+uint32_t ssc_is_tx_ready(Ssc *p_ssc);
+uint32_t ssc_is_tx_empty(Ssc *p_ssc);
+uint32_t ssc_is_rx_ready(Ssc *p_ssc);
+uint32_t ssc_is_tx_enabled(Ssc *p_ssc);
+uint32_t ssc_is_rx_enabled(Ssc *p_ssc);
+#if (defined _SAM3S_) || (defined _SAM4S_)
+uint32_t ssc_is_rx_buf_end(Ssc *p_ssc);
+uint32_t ssc_is_tx_buf_end(Ssc *p_ssc);
+uint32_t ssc_is_rx_buf_full(Ssc *p_ssc);
+uint32_t ssc_is_tx_buf_empty(Ssc *p_ssc);
+Pdc *ssc_get_pdc_base(Ssc *p_ssc);
+#endif
+uint32_t ssc_write(Ssc *p_ssc, uint32_t ul_frame);
+uint32_t ssc_read(Ssc *p_ssc, uint32_t *ul_data);
+void ssc_write_sync_data(Ssc *p_ssc, uint32_t ul_frame);
+uint32_t ssc_read_sync_data(Ssc *p_ssc);
+#if ((defined _SAM3XA_) || (defined _SAM3U_))
+void *ssc_get_tx_access(Ssc *p_ssc);
+void *ssc_get_rx_access(Ssc *p_ssc);
+#endif
+void ssc_set_writeprotect(Ssc *p_ssc, uint32_t ul_enable);
+uint32_t ssc_get_writeprotect_status(Ssc *p_ssc);
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* SSC_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/tc.h b/hardware/digistump/sam/system/libsam/include/tc.h
new file mode 100644
index 0000000..2923a98
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/tc.h
@@ -0,0 +1,86 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \section Purpose
+ *
+ *  Interface for configuring and using Timer Counter (TC) peripherals.
+ *
+ *  \section Usage
+ *  -# Optionally, use TC_FindMckDivisor() to let the program find the best
+ *     TCCLKS field value automatically.
+ *  -# Configure a Timer Counter in the desired mode using TC_Configure().
+ *  -# Start or stop the timer clock using TC_Start() and TC_Stop().
+ */
+
+#ifndef _TC_
+#define _TC_
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "../chip.h"
+
+#include 
+
+/*------------------------------------------------------------------------------
+ *         Global functions
+ *------------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode ) ;
+
+extern void TC_Start( Tc *pTc, uint32_t dwChannel ) ;
+
+extern void TC_Stop( Tc *pTc, uint32_t dwChannel ) ;
+
+extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK ) ;
+
+extern uint32_t TC_ReadCV(Tc *p_tc, uint32_t ul_channel);
+
+extern uint32_t TC_GetStatus(Tc *p_tc, uint32_t ul_channel);
+
+extern void TC_SetRA(Tc *tc, uint32_t chan, uint32_t v) ;
+
+extern void TC_SetRB(Tc *tc, uint32_t chan, uint32_t v) ;
+
+extern void TC_SetRC(Tc *tc, uint32_t chan, uint32_t v) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _TC_ */
+
diff --git a/hardware/digistump/sam/system/libsam/include/timetick.h b/hardware/digistump/sam/system/libsam/include/timetick.h
new file mode 100644
index 0000000..e42255d
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/timetick.h
@@ -0,0 +1,78 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \par Purpose
+ *
+ *  Methods and definitions for Global time tick and wait functions.
+ *
+ *  Defines a common and simpliest use of Time Tick, to increase tickCount
+ *  every 1ms, the application can get this value through GetTickCount().
+ *
+ *  \par Usage
+ *
+ *  -# Configure the System Tick with TimeTick_Configure() when MCK changed
+ *     \note
+ *     Must be done before any invoke of GetTickCount(), Wait() or Sleep().
+ *  -# Uses GetTickCount to get current tick value.
+ *  -# Uses Wait to wait several ms.
+ *  -# Uses Sleep to enter wait for interrupt mode to wait several ms.
+ *
+ */
+
+#ifndef _TIMETICK_
+#define _TIMETICK_
+
+/*----------------------------------------------------------------------------
+ *         Headers
+ *----------------------------------------------------------------------------*/
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *         Definitions
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ *         Global functions
+ *----------------------------------------------------------------------------*/
+
+extern uint32_t TimeTick_Configure( uint32_t dwNew_MCK ) ;
+
+extern void TimeTick_Increment( void ) ;
+
+extern uint32_t GetTickCount( void ) ;
+
+extern void Wait( volatile uint32_t dwMs ) ;
+
+extern void Sleep( volatile uint32_t dwMs ) ;
+
+#endif /* _TIMETICK_ */
diff --git a/hardware/digistump/sam/system/libsam/include/trng.h b/hardware/digistump/sam/system/libsam/include/trng.h
new file mode 100644
index 0000000..3b5f0dc
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/trng.h
@@ -0,0 +1,73 @@
+/**
+ * \file
+ *
+ * \brief API for SAM TRNG.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef TRNG_H_INCLUDED
+#define TRNG_H_INCLUDED
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+void trng_enable(Trng *p_trng);
+void trng_disable(Trng *p_trng);
+void trng_enable_interrupt(Trng *p_trng);
+void trng_disable_interrupt(Trng *p_trng);
+uint32_t trng_get_interrupt_mask(Trng *p_trng);
+uint32_t trng_get_interrupt_status(Trng *p_trng);
+uint32_t trng_read_output_data(Trng *p_trng);
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#endif /* TRNG_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/twi.h b/hardware/digistump/sam/system/libsam/include/twi.h
new file mode 100644
index 0000000..3d383f4
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/twi.h
@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Interface for configuration the Two Wire Interface (TWI) peripheral.
+ *
+ */
+
+#ifndef _TWI_
+#define _TWI_
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "../chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Macros
+ *----------------------------------------------------------------------------*/
+/* Returns 1 if the TXRDY bit (ready to transmit data) is set in the given status register value.*/
+#define TWI_STATUS_TXRDY(status) (((status) & TWI_SR_TXRDY) == TWI_SR_TXRDY)
+
+/* Returns 1 if the RXRDY bit (ready to receive data) is set in the given status register value.*/
+#define TWI_STATUS_RXRDY(status) (((status) & TWI_SR_RXRDY) == TWI_SR_RXRDY)
+
+/* Returns 1 if the TXCOMP bit (transfer complete) is set in the given status register value.*/
+#define TWI_STATUS_TXCOMP(status) (((status) & TWI_SR_TXCOMP) == TWI_SR_TXCOMP)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        External function
+ *----------------------------------------------------------------------------*/
+
+extern void TWI_ConfigureMaster(Twi *pTwi, uint32_t twck, uint32_t mck);
+
+extern void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress);
+
+extern void TWI_Stop(Twi *pTwi);
+
+extern void TWI_StartRead(
+    Twi *pTwi,
+    uint8_t address,
+    uint32_t iaddress,
+    uint8_t isize);
+
+extern uint8_t TWI_ReadByte(Twi *pTwi);
+
+extern void TWI_WriteByte(Twi *pTwi, uint8_t byte);
+
+extern void TWI_StartWrite(
+    Twi *pTwi,
+    uint8_t address,
+    uint32_t iaddress,
+    uint8_t isize,
+    uint8_t byte);
+
+extern uint8_t TWI_ByteReceived(Twi *pTwi);
+
+extern uint8_t TWI_ByteSent(Twi *pTwi);
+
+extern uint8_t TWI_TransferComplete(Twi *pTwi);
+
+extern void TWI_EnableIt(Twi *pTwi, uint32_t sources);
+
+extern void TWI_DisableIt(Twi *pTwi, uint32_t sources);
+
+extern uint32_t TWI_GetStatus(Twi *pTwi);
+
+extern uint32_t TWI_GetMaskedStatus(Twi *pTwi);
+
+extern void TWI_SendSTOPCondition(Twi *pTwi);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _TWI_ */
diff --git a/hardware/digistump/sam/system/libsam/include/udp.h b/hardware/digistump/sam/system/libsam/include/udp.h
new file mode 100644
index 0000000..e298735
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/udp.h
@@ -0,0 +1,33 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef UDPHS_H_INCLUDED
+#define UDPHS_H_INCLUDED
+
+#endif /* UDPHS_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/udphs.h b/hardware/digistump/sam/system/libsam/include/udphs.h
new file mode 100644
index 0000000..6656f06
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/udphs.h
@@ -0,0 +1,91 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef UDPHS_H_INCLUDED
+#define UDPHS_H_INCLUDED
+
+#define NUM_IT_MAX 3
+
+#define EP_SINGLE_64 0x32	// EP0
+#define EP_DOUBLE_64 0x36	// Other endpoints
+
+
+// Endpoint 0:
+#define EP_TYPE_CONTROL				UDPHS_EPTCFG_EPT_SIZE_64 \
+                                  | UDPHS_EPTCFG_EPT_TYPE_CTRL8 \
+                                  | UDPHS_EPTCFG_BK_NUMBER_1
+#ifdef CDC_ENABLED
+#define EP_TYPE_BULK_IN				UDPHS_EPTCFG_EPT_SIZE_512 \
+                                  | UDPHS_EPTCFG_EPT_DIR \
+                                  | UDPHS_EPTCFG_EPT_TYPE_BULK \
+                                  | UDPHS_EPTCFG_BK_NUMBER_2
+#define EP_TYPE_BULK_OUT			UDPHS_EPTCFG_EPT_SIZE_512 \
+                                  | UDPHS_EPTCFG_EPT_TYPE_BULK \
+                                  | UDPHS_EPTCFG_BK_NUMBER_2
+#define EP_TYPE_INTERRUPT_IN		UDPHS_EPTCFG_EPT_SIZE_64 \
+                                  | UDPHS_EPTCFG_EPT_DIR \
+                                  | UDPHS_EPTCFG_EPT_TYPE_INT \
+                                  | UDPHS_EPTCFG_BK_NUMBER_2
+#endif
+
+#ifdef HID_ENABLED
+#define EP_TYPE_INTERRUPT_IN_HID	UDPHS_EPTCFG_EPT_SIZE_64 \
+                                  | UDPHS_EPTCFG_EPT_DIR \
+                                  | UDPHS_EPTCFG_EPT_TYPE_INT \
+                                  | UDPHS_EPTCFG_BK_NUMBER_2
+#endif
+
+#define EP_TYPE_INTERRUPT_OUT		UDPHS_EPTCFG_EPT_SIZE_64 \
+                                  | UDPHS_EPTCFG_EPT_TYPE_INT \
+                                  | UDPHS_EPTCFG_EPT_TYPE_INT \
+                                  | UDPHS_EPTCFG_BK_NUMBER_1
+#define EP_TYPE_ISOCHRONOUS_IN		UDPHS_EPTCFG_EPT_SIZE_1024 \
+                                  | UDPHS_EPTCFG_EPT_DIR \
+                                  | UDPHS_EPTCFG_EPT_TYPE_ISO \
+                                  | UDPHS_EPTCFG_BK_NUMBER_3
+#define EP_TYPE_ISOCHRONOUS_OUT		UDPHS_EPTCFG_EPT_SIZE_1024 \
+                                  | UDPHS_EPTCFG_EPT_TYPE_ISO \
+                                  | UDPHS_EPTCFG_BK_NUMBER_3
+
+
+#ifndef TXLED1
+#define TXLED0
+#define RXLED0
+#define TXLED1
+#define RXLED1
+#endif
+
+
+#define UDFNUML ((UDPHS->UDPHS_FNUM & UDPHS_FNUM_FRAME_NUMBER_Msk)>>3)
+
+#define USB_RECV_TIMEOUT
+
+#define UDPHS_EPTFIFO (0x20180000) // (UDPHS_EPTFIFO) Base Address
+
+#endif /* UDPHS_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/uotghs_device.h b/hardware/digistump/sam/system/libsam/include/uotghs_device.h
new file mode 100644
index 0000000..e2ae944
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/uotghs_device.h
@@ -0,0 +1,751 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef UOTGHS_DEVICE_H_INCLUDED
+#define UOTGHS_DEVICE_H_INCLUDED
+
+
+#define MAX_ENDPOINTS	10
+#define EP0				0
+#define EP0_SIZE		64
+#define EPX_SIZE		512
+
+#define EP_SINGLE_64 (0x32UL) // EP0
+#define EP_DOUBLE_64 (0x36UL) // Other endpoints
+
+// Control Endpoint
+#define EP_TYPE_CONTROL				(UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | \
+									UOTGHS_DEVEPTCFG_EPTYPE_CTRL |     \
+									UOTGHS_DEVEPTCFG_EPBK_1_BANK |     \
+									UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
+									UOTGHS_DEVEPTCFG_ALLOC)
+
+// CDC Endpoints
+#define EP_TYPE_BULK_IN				(UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE | \
+									UOTGHS_DEVEPTCFG_EPDIR_IN |         \
+									UOTGHS_DEVEPTCFG_EPTYPE_BLK |       \
+									UOTGHS_DEVEPTCFG_EPBK_2_BANK |      \
+									UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS |  \
+									UOTGHS_DEVEPTCFG_ALLOC)
+
+#define EP_TYPE_BULK_OUT          	(UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE | \
+									UOTGHS_DEVEPTCFG_EPTYPE_BLK |       \
+									UOTGHS_DEVEPTCFG_EPBK_2_BANK |      \
+									UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS |  \
+									UOTGHS_DEVEPTCFG_ALLOC)
+
+#define EP_TYPE_INTERRUPT_IN      	(UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | \
+									UOTGHS_DEVEPTCFG_EPDIR_IN |        \
+									UOTGHS_DEVEPTCFG_EPTYPE_INTRPT |   \
+									UOTGHS_DEVEPTCFG_EPBK_2_BANK |     \
+									UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
+									UOTGHS_DEVEPTCFG_ALLOC)
+
+// HID Endpoints
+#define EP_TYPE_INTERRUPT_IN_HID	(UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | \
+									UOTGHS_DEVEPTCFG_EPDIR_IN |        \
+									UOTGHS_DEVEPTCFG_EPTYPE_INTRPT |   \
+									UOTGHS_DEVEPTCFG_EPBK_2_BANK |     \
+									UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
+									UOTGHS_DEVEPTCFG_ALLOC)
+
+// Various definitions
+#define EP_TYPE_INTERRUPT_OUT		(UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE | \
+									UOTGHS_DEVEPTCFG_EPTYPE_INTRPT |   \
+									UOTGHS_DEVEPTCFG_EPTYPE_INTRPT |   \
+									UOTGHS_DEVEPTCFG_EPBK_1_BANK |     \
+									UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS | \
+									UOTGHS_DEVEPTCFG_ALLOC)
+
+#define EP_TYPE_ISOCHRONOUS_IN		(UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE | \
+									UOTGHS_DEVEPTCFG_EPDIR_IN |          \
+									UOTGHS_DEVEPTCFG_EPTYPE_ISO |        \
+									UOTGHS_DEVEPTCFG_EPBK_3_BANK |       \
+									UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS |   \
+									UOTGHS_DEVEPTCFG_ALLOC)
+
+#define EP_TYPE_ISOCHRONOUS_OUT		(UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE | \
+									UOTGHS_DEVEPTCFG_EPTYPE_ISO |        \
+									UOTGHS_DEVEPTCFG_EPBK_3_BANK |       \
+									UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS |   \
+									UOTGHS_DEVEPTCFG_ALLOC)
+
+//! \ingroup usb_device_group
+//! \defgroup udd_group USB Device Driver (UDD)
+//! UOTGHS low-level driver for USB device mode
+//!
+//! @{
+
+#ifndef UOTGHS_DEVEPTCFG_EPDIR_Pos
+// Bit pos is not defined in SAM header file but we need it.
+# define UOTGHS_DEVEPTCFG_EPDIR_Pos 8
+#endif
+
+//! @name UOTGHS Device IP properties
+//! These macros give access to IP properties
+//! @{
+  //! Get maximal number of endpoints
+#define udd_get_endpoint_max_nbr()             (9)
+#define UDD_MAX_PEP_NB                         (udd_get_endpoint_max_nbr() + 1)
+  //! Get maximal number of banks of endpoints
+#define udd_get_endpoint_bank_max_nbr(ep)      ((ep == 0) ? 1 : (( ep <= 2) ? 3 : 2))
+  //! Get maximal size of endpoint (3X, 1024/64)
+#define udd_get_endpoint_size_max(ep)          (((ep) == 0) ? 64 : 512)  // for bulk
+  //! Get DMA support of endpoints
+#define Is_udd_endpoint_dma_supported(ep)      ((((ep) >= 1) && ((ep) <= 6)) ? true : false)
+  //! Get High Band Width support of endpoints
+#define Is_udd_endpoint_high_bw_supported(ep)  (((ep) >= 2) ? true : false)
+//! @}
+
+//! @name UOTGHS Device speeds management
+//! @{
+  //! Enable/disable device low-speed mode
+#define udd_low_speed_enable()               (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_LS))
+#define udd_low_speed_disable()              (Clr_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_LS))
+  //! Test if device low-speed mode is forced
+#define Is_udd_low_speed_enable()            (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_LS))
+
+  //! Enable high speed mode
+#define udd_high_speed_enable()          (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_Msk, 0))
+  //! Disable high speed mode
+#define udd_high_speed_disable()         (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_Msk, 3))
+  //! Test if controller is in full speed mode
+#define Is_udd_full_speed_mode()         (Rd_bitfield(UOTGHS->UOTGHS_SR, UOTGHS_SR_SPEED_Msk) == UOTGHS_SR_SPEED_FULL_SPEED)
+//! @}
+
+//! @name UOTGHS Device HS test mode management
+//! @{
+#ifdef UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED
+  //! Enable high speed test mode
+# define udd_enable_hs_test_mode()        (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_SPDCONF_Msk, 2))
+# define udd_enable_hs_test_mode_j()      (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_TSTJ))
+# define udd_enable_hs_test_mode_k()      (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_TSTK))
+# define udd_enable_hs_test_mode_packet() (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_TSTPCKT))
+#endif
+//! @}
+
+//! @name UOTGHS Device vbus management
+//! @{
+#define udd_enable_vbus_interrupt()       (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
+#define udd_disable_vbus_interrupt()      (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
+#define Is_udd_vbus_interrupt_enabled()   (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
+#define Is_udd_vbus_high()                (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUS))
+#define Is_udd_vbus_low()                 (!Is_udd_vbus_high())
+#define udd_ack_vbus_transition()         (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_VBUSTIC)
+#define udd_raise_vbus_transition()       (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_VBUSTIS)
+#define Is_udd_vbus_transition()          (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUSTI))
+//! @}
+
+
+//! @name UOTGHS device attach control
+//! These macros manage the UOTGHS Device attach.
+//! @{
+  //! Detaches from USB bus
+#define udd_detach_device()               (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_DETACH))
+  //! Attaches to USB bus
+#define udd_attach_device()               (Clr_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_DETACH))
+  //! Test if the device is detached
+#define Is_udd_detached()                 (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_DETACH))
+//! @}
+
+
+//! @name UOTGHS device bus events control
+//! These macros manage the UOTGHS Device bus events.
+//! @{
+
+//! Initiates a remote wake-up event
+//! @{
+#define udd_initiate_remote_wake_up()     (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_RMWKUP))
+#define Is_udd_pending_remote_wake_up()   (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_RMWKUP))
+//! @}
+
+//! Manage upstream resume event (=remote wakeup)
+//! The USB driver sends a resume signal called "Upstream Resume"
+//! @{
+#define udd_enable_remote_wake_up_interrupt()     (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_UPRSMES)
+#define udd_disable_remote_wake_up_interrupt()    (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_UPRSMEC)
+#define Is_udd_remote_wake_up_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_UPRSME))
+#define udd_ack_remote_wake_up_start()            (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_UPRSMC)
+#define udd_raise_remote_wake_up_start()          (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_UPRSMS)
+#define Is_udd_remote_wake_up_start()             (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_UPRSM))
+//! @}
+
+//! Manage downstream resume event (=remote wakeup from host)
+//! The USB controller detects a valid "End of Resume" signal initiated by the host
+//! @{
+#define udd_enable_resume_interrupt()             (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_EORSMES)
+#define udd_disable_resume_interrupt()            (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_EORSMEC)
+#define Is_udd_resume_interrupt_enabled()         (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_EORSME))
+#define udd_ack_resume()                          (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_EORSMC)
+#define udd_raise_resume()                        (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_EORSMS)
+#define Is_udd_resume()                           (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_EORSM))
+//! @}
+
+//! Manage wake-up event (=usb line activity)
+//! The USB controller is reactivated by a filtered non-idle signal from the lines
+//! @{
+#define udd_enable_wake_up_interrupt()            (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_WAKEUPES)
+#define udd_disable_wake_up_interrupt()           (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_WAKEUPEC)
+#define Is_udd_wake_up_interrupt_enabled()        (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_WAKEUPE))
+#define udd_ack_wake_up()                         (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_WAKEUPC)
+#define udd_raise_wake_up()                       (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_WAKEUPS)
+#define Is_udd_wake_up()                          (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_WAKEUP))
+//! @}
+
+//! Manage reset event
+//! Set when a USB "End of Reset" has been detected
+//! @{
+#define udd_enable_reset_interrupt()              (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_EORSTES)
+#define udd_disable_reset_interrupt()             (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_EORSTEC)
+#define Is_udd_reset_interrupt_enabled()          (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_EORSTE))
+#define udd_ack_reset()                           (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_EORSTC)
+#define udd_raise_reset()                         (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_EORSTS)
+#define Is_udd_reset()                            (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_EORST))
+//! @}
+
+//! Manage start of frame event
+//! @{
+#define udd_enable_sof_interrupt()                (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_SOFES)
+#define udd_disable_sof_interrupt()               (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_SOFEC)
+#define Is_udd_sof_interrupt_enabled()            (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_SOFE))
+#define udd_ack_sof()                             (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_SOFC)
+#define udd_raise_sof()                           (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_SOFS)
+#define Is_udd_sof()                              (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_SOF))
+#define udd_frame_number()                        (Rd_bitfield(UOTGHS->UOTGHS_DEVFNUM, UOTGHS_DEVFNUM_FNUM_Msk))
+#define Is_udd_frame_number_crc_error()           (Tst_bits(UOTGHS->UOTGHS_DEVFNUM, UOTGHS_DEVFNUM_FNCERR))
+//! @}
+
+//! Manage Micro start of frame event (High Speed Only)
+//! @{
+#define udd_enable_msof_interrupt()               (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_MSOFES)
+#define udd_disable_msof_interrupt()              (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_MSOFEC)
+#define Is_udd_msof_interrupt_enabled()           (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_MSOFE))
+#define udd_ack_msof()                            (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVIMR_MSOFE)
+#define udd_raise_msof()                          (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_MSOFS)
+#define Is_udd_msof()                             (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_MSOF))
+#define udd_micro_frame_number()                  \
+	(Rd_bitfield(UOTGHS->UOTGHS_DEVFNUM, (UOTGHS_DEVFNUM_FNUM_Msk|UOTGHS_DEVFNUM_MFNUM_Msk)))
+//! @}
+
+//! Manage suspend event
+//! @{
+#define udd_enable_suspend_interrupt()            (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_SUSPES)
+#define udd_disable_suspend_interrupt()           (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_SUSPEC)
+#define Is_udd_suspend_interrupt_enabled()        (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_SUSPE))
+#define udd_ack_suspend()                         (UOTGHS->UOTGHS_DEVICR = UOTGHS_DEVICR_SUSPC)
+#define udd_raise_suspend()                       (UOTGHS->UOTGHS_DEVIFR = UOTGHS_DEVIFR_SUSPS)
+#define Is_udd_suspend()                          (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_SUSP))
+//! @}
+
+//! @}
+
+//! @name UOTGHS device address control
+//! These macros manage the UOTGHS Device address.
+//! @{
+  //! enables USB device address
+#define udd_enable_address()                      (Set_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_ADDEN))
+  //! disables USB device address
+#define udd_disable_address()                     (Clr_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_ADDEN))
+#define Is_udd_address_enabled()                  (Tst_bits(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_ADDEN))
+  //! configures the USB device address
+#define udd_configure_address(addr)               (Wr_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_UADD_Msk, addr))
+  //! gets the currently configured USB device address
+#define udd_get_configured_address()              (Rd_bitfield(UOTGHS->UOTGHS_DEVCTRL, UOTGHS_DEVCTRL_UADD_Msk))
+//! @}
+
+
+//! @name UOTGHS Device endpoint drivers
+//! These macros manage the common features of the endpoints.
+//! @{
+
+//! Generic macro for UOTGHS registers that can be arrayed
+//! @{
+#define UOTGHS_ARRAY(reg,index)                   ((&(UOTGHS->reg))[(index)])
+//! @}
+
+//! @name UOTGHS Device endpoint configuration
+//! @{
+  //! enables the selected endpoint
+#define udd_enable_endpoint(ep)                   (Set_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPEN0 << (ep)))
+  //! disables the selected endpoint
+#define udd_disable_endpoint(ep)                  (Clr_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPEN0 << (ep)))
+  //! tests if the selected endpoint is enabled
+#define Is_udd_endpoint_enabled(ep)               (Tst_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPEN0 << (ep)))
+  //! resets the selected endpoint
+#define udd_reset_endpoint(ep)                                         \
+	do {                                                               \
+		Set_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)); \
+		Clr_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)); \
+	} while (0)
+  //! Tests if the selected endpoint is being reset
+#define Is_udd_resetting_endpoint(ep)             (Tst_bits(UOTGHS->UOTGHS_DEVEPT, UOTGHS_DEVEPT_EPRST0 << (ep)))
+
+  //! Configures the selected endpoint type
+#define udd_configure_endpoint_type(ep, type)     (Wr_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPTYPE_Msk, type))
+  //! Gets the configured selected endpoint type
+#define udd_get_endpoint_type(ep)                 (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPTYPE_Msk))
+  //! Enables the bank autoswitch for the selected endpoint
+#define udd_enable_endpoint_bank_autoswitch(ep)   (Set_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_AUTOSW))
+  //! Disables the bank autoswitch for the selected endpoint
+#define udd_disable_endpoint_bank_autoswitch(ep)    (Clr_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_AUTOSW))
+#define Is_udd_endpoint_bank_autoswitch_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_AUTOSW))
+  //! Configures the selected endpoint direction
+#define udd_configure_endpoint_direction(ep, dir) (Wr_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPDIR, dir))
+  //! Gets the configured selected endpoint direction
+#define udd_get_endpoint_direction(ep)            (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPDIR))
+#define Is_udd_endpoint_in(ep)                    (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPDIR))
+  //! Bounds given integer size to allowed range and rounds it up to the nearest
+  //! available greater size, then applies register format of UOTGHS controller
+  //! for endpoint size bit-field.
+#define udd_format_endpoint_size(size)            (32 - clz(((uint32_t)min(max(size, 8), 1024) << 1) - 1) - 1 - 3)
+  //! Configures the selected endpoint size
+#define udd_configure_endpoint_size(ep, size)     (Wr_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPSIZE_Msk, udd_format_endpoint_size(size)))
+  //! Gets the configured selected endpoint size
+#define udd_get_endpoint_size(ep)                 (8 << Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPSIZE_Msk))
+  //! Configures the selected endpoint number of banks
+#define udd_configure_endpoint_bank(ep, bank)     (Wr_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPBK_Msk, bank))
+  //! Gets the configured selected endpoint number of banks
+#define udd_get_endpoint_bank(ep)                 (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPBK_Msk)+1)
+  //! Allocates the configuration selected endpoint in DPRAM memory
+#define udd_allocate_memory(ep)                   (Set_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_ALLOC))
+  //! un-allocates the configuration selected endpoint in DPRAM memory
+#define udd_unallocate_memory(ep)                 (Clr_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_ALLOC))
+#define Is_udd_memory_allocated(ep)               (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_ALLOC))
+
+  //! Configures selected endpoint in one step
+#define udd_configure_endpoint(ep, type, dir, size, bank) (\
+	Wr_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTCFG[0], ep), UOTGHS_DEVEPTCFG_EPTYPE_Msk |\
+			UOTGHS_DEVEPTCFG_EPDIR  |\
+			UOTGHS_DEVEPTCFG_EPSIZE_Msk |\
+			UOTGHS_DEVEPTCFG_EPBK_Msk ,   \
+			(((uint32_t)(type) << UOTGHS_DEVEPTCFG_EPTYPE_Pos) & UOTGHS_DEVEPTCFG_EPTYPE_Msk) |\
+			(((uint32_t)(dir ) << UOTGHS_DEVEPTCFG_EPDIR_Pos ) & UOTGHS_DEVEPTCFG_EPDIR) |\
+			( (uint32_t)udd_format_endpoint_size(size) << UOTGHS_DEVEPTCFG_EPSIZE_Pos) |\
+			(((uint32_t)(bank) << UOTGHS_DEVEPTCFG_EPBK_Pos) & UOTGHS_DEVEPTCFG_EPBK_Msk))\
+)
+  //! Tests if current endpoint is configured
+#define Is_udd_endpoint_configured(ep)            (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_CFGOK))
+  //! Returns the control direction
+#define udd_control_direction()                   (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], EP_CONTROL), UOTGHS_DEVEPTISR_CTRLDIR))
+
+  //! Resets the data toggle sequence
+#define udd_reset_data_toggle(ep)                 (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_RSTDTS)
+  //! Tests if the data toggle sequence is being reset
+#define Is_udd_data_toggle_reset(ep)              (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_RSTDT))
+  //! Returns data toggle
+#define udd_data_toggle(ep)                       (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_DTSEQ_Msk))
+//! @}
+
+
+//! @name UOTGHS Device control endpoint
+//! These macros control the endpoints.
+//! @{
+
+//! @name UOTGHS Device control endpoint interrupts
+//! These macros control the endpoints interrupts.
+//! @{
+  //! Enables the selected endpoint interrupt
+#define udd_enable_endpoint_interrupt(ep)         (UOTGHS->UOTGHS_DEVIER = UOTGHS_DEVIER_PEP_0 << (ep))
+  //! Disables the selected endpoint interrupt
+#define udd_disable_endpoint_interrupt(ep)        (UOTGHS->UOTGHS_DEVIDR = UOTGHS_DEVIDR_PEP_0 << (ep))
+  //! Tests if the selected endpoint interrupt is enabled
+#define Is_udd_endpoint_interrupt_enabled(ep)     (Tst_bits(UOTGHS->UOTGHS_DEVIMR, UOTGHS_DEVIMR_PEP_0 << (ep)))
+  //! Tests if an interrupt is triggered by the selected endpoint
+#define Is_udd_endpoint_interrupt(ep)             (Tst_bits(UOTGHS->UOTGHS_DEVISR, UOTGHS_DEVISR_PEP_0 << (ep)))
+  //! Returns the lowest endpoint number generating an endpoint interrupt or MAX_PEP_NB if none
+#define udd_get_interrupt_endpoint_number()       (ctz(((UOTGHS->UOTGHS_DEVISR >> UOTGHS_DEVISR_PEP_Pos) & \
+                                                   (UOTGHS->UOTGHS_DEVIMR >> UOTGHS_DEVIMR_PEP_Pos)) |     \
+                                                   (1 << MAX_PEP_NB)))
+#define UOTGHS_DEVISR_PEP_Pos   12
+#define UOTGHS_DEVIMR_PEP_Pos   12
+//! @}
+
+//! @name UOTGHS Device control endpoint errors
+//! These macros control the endpoint errors.
+//! @{
+  //! Enables the STALL handshake
+#define udd_enable_stall_handshake(ep)            (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_STALLRQS)
+  //! Disables the STALL handshake
+#define udd_disable_stall_handshake(ep)           (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_STALLRQC)
+  //! Tests if STALL handshake request is running
+#define Is_udd_endpoint_stall_requested(ep)       (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_STALLRQ))
+  //! Tests if STALL sent
+#define Is_udd_stall(ep)                          (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_STALLEDI))
+  //! ACKs STALL sent
+#define udd_ack_stall(ep)                         (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_STALLEDIC)
+  //! Raises STALL sent
+#define udd_raise_stall(ep)                       (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_STALLEDIS)
+  //! Enables STALL sent interrupt
+#define udd_enable_stall_interrupt(ep)            (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_STALLEDES)
+  //! Disables STALL sent interrupt
+#define udd_disable_stall_interrupt(ep)           (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_STALLEDEC)
+  //! Tests if STALL sent interrupt is enabled
+#define Is_udd_stall_interrupt_enabled(ep)        (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_STALLEDE))
+
+  //! Tests if NAK OUT received
+#define Is_udd_nak_out(ep)                        (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_NAKOUTI))
+  //! ACKs NAK OUT received
+#define udd_ack_nak_out(ep)                       (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_NAKOUTIC)
+  //! Raises NAK OUT received
+#define udd_raise_nak_out(ep)                     (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_NAKOUTIS)
+  //! Enables NAK OUT interrupt
+#define udd_enable_nak_out_interrupt(ep)          (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_NAKOUTES)
+  //! Disables NAK OUT interrupt
+#define udd_disable_nak_out_interrupt(ep)         (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_NAKOUTEC)
+  //! Tests if NAK OUT interrupt is enabled
+#define Is_udd_nak_out_interrupt_enabled(ep)      (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_NAKOUTE))
+
+  //! Tests if NAK IN received
+#define Is_udd_nak_in(ep)                         (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_NAKINI))
+  //! ACKs NAK IN received
+#define udd_ack_nak_in(ep)                        (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_NAKINIC)
+  //! Raises NAK IN received
+#define udd_raise_nak_in(ep)                      (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_NAKINIS)
+  //! Enables NAK IN interrupt
+#define udd_enable_nak_in_interrupt(ep)           (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_NAKINES)
+  //! Disables NAK IN interrupt
+#define udd_disable_nak_in_interrupt(ep)          (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_NAKINEC)
+  //! Tests if NAK IN interrupt is enabled
+#define Is_udd_nak_in_interrupt_enabled(ep)       (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_NAKINE))
+
+  //! ACKs endpoint isochronous overflow interrupt
+#define udd_ack_overflow_interrupt(ep)            (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_OVERFIC)
+  //! Raises endpoint isochronous overflow interrupt
+#define udd_raise_overflow_interrupt(ep)          (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_OVERFIS)
+  //! Tests if an overflow occurs
+#define Is_udd_overflow(ep)                       (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_OVERFI))
+  //! Enables overflow interrupt
+#define udd_enable_overflow_interrupt(ep)         (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_OVERFES)
+  //! Disables overflow interrupt
+#define udd_disable_overflow_interrupt(ep)        (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_OVERFEC)
+  //! Tests if overflow interrupt is enabled
+#define Is_udd_overflow_interrupt_enabled(ep)     (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_OVERFE))
+
+  //! ACKs endpoint isochronous underflow interrupt
+#define udd_ack_underflow_interrupt(ep)           (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_UNDERFIC)
+  //! Raises endpoint isochronous underflow interrupt
+#define udd_raise_underflow_interrupt(ep)         (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_UNDERFIS)
+  //! Tests if an underflow occurs
+#define Is_udd_underflow(ep)                      (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_UNDERFI))
+  //! Enables underflow interrupt
+#define udd_enable_underflow_interrupt(ep)        (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_UNDERFES)
+  //! Disables underflow interrupt
+#define udd_disable_underflow_interrupt(ep)       (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_UNDERFEC)
+  //! Tests if underflow interrupt is enabled
+#define Is_udd_underflow_interrupt_enabled(ep)    (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_UNDERFE))
+
+  //! Tests if CRC ERROR ISO OUT detected
+#define Is_udd_crc_error(ep)                      (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_CRCERRI))
+  //! ACKs CRC ERROR ISO OUT detected
+#define udd_ack_crc_error(ep)                     (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_CRCERRIC)
+  //! Raises CRC ERROR ISO OUT detected
+#define udd_raise_crc_error(ep)                   (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_CRCERRIS)
+  //! Enables CRC ERROR ISO OUT detected interrupt
+#define udd_enable_crc_error_interrupt(ep)        (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_CRCERRES)
+  //! Disables CRC ERROR ISO OUT detected interrupt
+#define udd_disable_crc_error_interrupt(ep)       (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_CRCERREC)
+  //! Tests if CRC ERROR ISO OUT detected interrupt is enabled
+#define Is_udd_crc_error_interrupt_enabled(ep)    (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_CRCERRE))
+//! @}
+
+//! @name UOTGHS Device control endpoint transfer
+//! These macros control the endpoint transfer.
+//! @{
+
+  //! Tests if endpoint read allowed
+#define Is_udd_read_enabled(ep)                   (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_RWALL))
+  //! Tests if endpoint write allowed
+#define Is_udd_write_enabled(ep)                  (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_RWALL))
+
+  //! Returns the byte count
+#define udd_byte_count(ep)                        (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_BYCT_Msk))
+  //! Clears FIFOCON bit
+#define udd_ack_fifocon(ep)                       (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_FIFOCONC)
+  //! Tests if FIFOCON bit set
+#define Is_udd_fifocon(ep)                        (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_FIFOCON))
+
+  //! Returns the number of busy banks
+#define udd_nb_busy_bank(ep)                      (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_NBUSYBK_Msk))
+  //! Returns the number of the current bank
+#define udd_current_bank(ep)                      (Rd_bitfield(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_CURRBK_Msk))
+  //! Kills last bank
+#define udd_kill_last_in_bank(ep)                 (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_KILLBKS)
+#define Is_udd_kill_last(ep)                      (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_KILLBK))
+  //! Tests if last bank killed
+#define Is_udd_last_in_bank_killed(ep)            (!Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_KILLBK))
+  //! Forces all banks full (OUT) or free (IN) interrupt
+#define udd_force_bank_interrupt(ep)              (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_NBUSYBKS)
+  //! Unforces all banks full (OUT) or free (IN) interrupt
+#define udd_unforce_bank_interrupt(ep)            (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_NBUSYBKS)
+  //! Enables all banks full (OUT) or free (IN) interrupt
+#define udd_enable_bank_interrupt(ep)             (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_NBUSYBKES)
+  //! Disables all banks full (OUT) or free (IN) interrupt
+#define udd_disable_bank_interrupt(ep)            (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_NBUSYBKEC)
+  //! Tests if all banks full (OUT) or free (IN) interrupt enabled
+#define Is_udd_bank_interrupt_enabled(ep)         (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_NBUSYBKE))
+
+  //! Tests if SHORT PACKET received
+#define Is_udd_short_packet(ep)                   (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_SHORTPACKET))
+  //! ACKs SHORT PACKET received
+#define udd_ack_short_packet(ep)                  (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_SHORTPACKETC)
+  //! Raises SHORT PACKET received
+#define udd_raise_short_packet(ep)                (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_SHORTPACKETS)
+  //! Enables SHORT PACKET received interrupt
+#define udd_enable_short_packet_interrupt(ep)     (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_SHORTPACKETES)
+  //! Disables SHORT PACKET received interrupt
+#define udd_disable_short_packet_interrupt(ep)    (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_SHORTPACKETEC)
+  //! Tests if SHORT PACKET received interrupt is enabled
+#define Is_udd_short_packet_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_SHORTPACKETE))
+
+  //! Tests if SETUP received
+#define Is_udd_setup_received(ep)                    (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_RXSTPI))
+  //! ACKs SETUP received
+#define udd_ack_setup_received(ep)                   (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_RXSTPIC)
+  //! Raises SETUP received
+#define udd_raise_setup_received(ep)                 (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_RXSTPIS)
+  //! Enables SETUP received interrupt
+#define udd_enable_setup_received_interrupt(ep)      (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_RXSTPES)
+  //! Disables SETUP received interrupt
+#define udd_disable_setup_received_interrupt(ep)     (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_RXSTPEC)
+  //! Tests if SETUP received interrupt is enabled
+#define Is_udd_setup_received_interrupt_enabled(ep)  (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_RXSTPE))
+
+  //! Tests if OUT received
+#define Is_udd_out_received(ep)                   (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_RXOUTI))
+  //! ACKs OUT received
+#define udd_ack_out_received(ep)                  (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_RXOUTIC)
+  //! Raises OUT received
+#define udd_raise_out_received(ep)                (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_RXOUTIS)
+  //! Enables OUT received interrupt
+#define udd_enable_out_received_interrupt(ep)     (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_RXOUTES)
+  //! Disables OUT received interrupt
+#define udd_disable_out_received_interrupt(ep)    (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_RXOUTEC)
+  //! Tests if OUT received interrupt is enabled
+#define Is_udd_out_received_interrupt_enabled(ep) (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_RXOUTE))
+
+  //! Tests if IN sending
+#define Is_udd_in_send(ep)                        (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTISR[0], ep), UOTGHS_DEVEPTISR_TXINI))
+  //! ACKs IN sending
+#define udd_ack_in_send(ep)                       (UOTGHS_ARRAY(UOTGHS_DEVEPTICR[0], ep) = UOTGHS_DEVEPTICR_TXINIC)
+  //! Raises IN sending
+#define udd_raise_in_send(ep)                     (UOTGHS_ARRAY(UOTGHS_DEVEPTIFR[0], ep) = UOTGHS_DEVEPTIFR_TXINIS)
+  //! Enables IN sending interrupt
+#define udd_enable_in_send_interrupt(ep)          (UOTGHS_ARRAY(UOTGHS_DEVEPTIER[0], ep) = UOTGHS_DEVEPTIER_TXINES)
+  //! Disables IN sending interrupt
+#define udd_disable_in_send_interrupt(ep)         (UOTGHS_ARRAY(UOTGHS_DEVEPTIDR[0], ep) = UOTGHS_DEVEPTIDR_TXINEC)
+  //! Tests if IN sending interrupt is enabled
+#define Is_udd_in_send_interrupt_enabled(ep)      (Tst_bits(UOTGHS_ARRAY(UOTGHS_DEVEPTIMR[0], ep), UOTGHS_DEVEPTIMR_TXINE))
+
+
+  //! 8-bit access to FIFO data register of selected endpoint.
+  //! @param ep Endpoint of which to access FIFO data register
+  //! @return Volatile 8-bit data pointer to FIFO data register
+  //! @warning It is up to the user of this macro to make sure that all accesses
+  //! are aligned with their natural boundaries
+  //! @warning It is up to the user of this macro to make sure that used HSB
+  //! addresses are identical to the DPRAM internal pointer modulo 32 bits.
+#define udd_get_endpoint_fifo_access8(ep) \
+		(((volatile uint8_t (*)[0x8000])UOTGHS_RAM_ADDR)[(ep)])
+
+//! @}
+
+/*********************************************************************************************************************/
+
+//! @name UOTGHS IP properties
+//! These macros give access to IP properties (not defined in 3X)
+//! @{
+   //! Get IP name part 1 or 2
+#define otg_get_ip_name()
+#define otg_data_memory_barrier()
+   //! Get IP version
+#define otg_get_ip_version()
+   //! Get DPRAM size (FIFO maximal size) in bytes
+#define otg_get_dpram_size()
+   //! Get size of USBB PB address space
+#define otg_get_ip_paddress_size()
+//! @}
+
+//! @name UOTGHS OTG ID pin management
+//! The ID pin come from the USB OTG connector (A and B receptable) and
+//! allows to select the USB mode host or device.
+//! The USBB hardware can manage it automaticaly. This feature is optional.
+//! When otg_ID_PIN equals true in conf_usb_host.h, the USB_ID must be defined in board.h.
+//!
+//! @{
+   //! PIO, PIO ID and MASK for USB_ID according to configuration from OTG_ID
+#define OTG_ID_PIN                          USB_ID_GPIO
+#define OTG_ID_FUNCTION                     USB_ID_FLAGS
+   //! Input USB_ID from its pin
+#define otg_input_id_pin() do {                     \
+    pio_configure_pin(OTG_ID_PIN, OTG_ID_FUNCTION); \
+} while (0)
+
+   //! Enable external OTG_ID pin (listened to by USB)
+#define otg_enable_id_pin()                 (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIDE))
+   //! Disable external OTG_ID pin (ignored by USB)
+#define otg_disable_id_pin()                (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIDE))
+   //! Test if external OTG_ID pin enabled (listened to by USB)
+#define Is_otg_id_pin_enabled()             (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIDE))
+   //! Disable external OTG_ID pin and force device mode
+#define otg_force_device_mode()             (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD), otg_disable_id_pin())
+   //! Test if device mode is forced
+#define Is_otg_device_mode_forced()         (!Is_otg_id_pin_enabled() && Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD))
+   //! Disable external OTG_ID pin and force host mode
+#define otg_force_host_mode()               (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD), otg_disable_id_pin())
+   //! Test if host mode is forced
+#define Is_otg_host_mode_forced()           (!Is_otg_id_pin_enabled() && !Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UIMOD))
+
+//! @name UOTGHS OTG ID pin interrupt management
+//! These macros manage the ID pin interrupt
+//! @{
+#define otg_enable_id_interrupt()           (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_IDTE))
+#define otg_disable_id_interrupt()          (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_IDTE))
+#define Is_otg_id_interrupt_enabled()       (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_IDTE))
+#define Is_otg_id_device()                  (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_ID))
+#define Is_otg_id_host()                    (!Is_otg_id_device())
+#define otg_ack_id_transition()             (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_IDTIC)
+#define otg_raise_id_transition()           (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_IDTIS)
+#define Is_otg_id_transition()              (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_IDTI))
+//! @}
+
+//! @name USBB OTG Vbus management
+//! @{
+#define otg_enable_vbus_interrupt()         (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
+#define otg_disable_vbus_interrupt()        (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
+#define Is_otg_vbus_interrupt_enabled()     (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSTE))
+#define Is_otg_vbus_high()                  (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUS))
+#define Is_otg_vbus_low()                   (!Is_otg_vbus_high())
+#define otg_ack_vbus_transition()           (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_VBUSTIC)
+#define otg_raise_vbus_transition()         (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_VBUSTIS)
+#define Is_otg_vbus_transition()            (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUSTI))
+//! @}
+
+//! @name UOTGHS OTG main management
+//! These macros allows to enable/disable pad and UOTGHS hardware
+//! @{
+  //! Enable USB macro
+#define otg_enable()                        (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_USBE))
+  //! Disable USB macro
+#define otg_disable()                       (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_USBE))
+#define Is_otg_enabled()                    (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_USBE))
+
+  //! Enable OTG pad
+#define otg_enable_pad()                    (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_OTGPADE))
+  //! Disable OTG pad
+#define otg_disable_pad()                   (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_OTGPADE))
+#define Is_otg_pad_enabled()                (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_OTGPADE))
+
+  //! Check Clock Usable
+  //! For parts with HS feature, this one corresponding at UTMI clock
+#define Is_otg_clock_usable()               (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_CLKUSABLE))
+
+  //! Stop (freeze) internal USB clock
+#define otg_freeze_clock()                  (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_FRZCLK))
+#define otg_unfreeze_clock()                (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_FRZCLK))
+#define Is_otg_clock_frozen()               (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_FRZCLK))
+
+  //! Configure time-out of specified OTG timer
+#define otg_configure_timeout(timer, timeout) (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\
+                                             Wr_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMPAGE_Msk, timer),\
+                                             Wr_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMVALUE_Msk, timeout),\
+                                             Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK))
+  //! Get configured time-out of specified OTG timer
+#define otg_get_timeout(timer)              (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\
+                                             Wr_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMPAGE_Msk, timer),\
+                                             Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_UNLOCK),\
+                                             Rd_bitfield(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_TIMVALUE_Msk))
+
+
+  //! Get the dual-role device state of the internal USB finite state machine of the UOTGHS controller
+#define otg_get_fsm_drd_state()             (Rd_bitfield(UOTGHS->UOTGHS_FSM, UOTGHS_FSM_DRDSTATE_Msk))
+//! @}
+
+//! @name UOTGHS OTG hardware protocol
+//! These macros manages the hardware OTG protocol
+//! @{
+  //! Initiates a Host Negociation Protocol
+#define otg_device_initiate_hnp()             (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ))
+  //! Accepts a Host Negociation Protocol
+#define otg_host_accept_hnp()                 (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ))
+  //! Rejects a Host Negociation Protocol
+#define otg_host_reject_hnp()                 (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ))
+  //! initiates a Session Request Protocol
+#define otg_device_initiate_srp()             (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPREQ))
+  //! Selects VBus as SRP method
+#define otg_select_vbus_srp_method()          (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPSEL))
+#define Is_otg_vbus_srp_method_selected()     (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPSEL))
+  //! Selects data line as SRP method
+#define otg_select_data_srp_method()          (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPSEL))
+#define Is_otg_data_srp_method_selected()     (!Is_otg_vbus_srp_method_selected())
+  //! Tests if a HNP occurs
+#define Is_otg_hnp()                          (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPREQ))
+  //! Tests if a SRP from device occurs
+#define Is_otg_device_srp()                   (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPREQ))
+
+  //! Enables HNP error interrupt
+#define otg_enable_hnp_error_interrupt()      (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPERRE))
+  //! Disables HNP error interrupt
+#define otg_disable_hnp_error_interrupt()     (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPERRE))
+#define Is_otg_hnp_error_interrupt_enabled()  (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_HNPERRE))
+  //! ACKs HNP error interrupt
+#define otg_ack_hnp_error_interrupt()         (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_HNPERRIC)
+  //! Raises HNP error interrupt
+#define otg_raise_hnp_error_interrupt()       (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_HNPERRIS)
+  //! Tests if a HNP error occurs
+#define Is_otg_hnp_error_interrupt()          (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_HNPERRI))
+
+  //! Enables role exchange interrupt
+#define otg_enable_role_exchange_interrupt()      (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_ROLEEXE))
+  //! Disables role exchange interrupt
+#define otg_disable_role_exchange_interrupt()     (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_ROLEEXE))
+#define Is_otg_role_exchange_interrupt_enabled()  (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_ROLEEXE))
+  //! ACKs role exchange interrupt
+#define otg_ack_role_exchange_interrupt()         (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_ROLEEXIC)
+  //! Raises role exchange interrupt
+#define otg_raise_role_exchange_interrupt()       (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_ROLEEXIS)
+  //! Tests if a role exchange occurs
+#define Is_otg_role_exchange_interrupt()          (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_ROLEEXI))
+
+  //! Eenables SRP interrupt
+#define otg_enable_srp_interrupt()          (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPE))
+  //! Disables SRP interrupt
+#define otg_disable_srp_interrupt()         (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPE))
+#define Is_otg_srp_interrupt_enabled()      (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_SRPE))
+  //! ACKs SRP interrupt
+#define otg_ack_srp_interrupt()             (UOTGHS->UOTGHS_SCR = UOTGHS_SCR_SRPIC)
+  //! Raises SRP interrupt
+#define otg_raise_srp_interrupt()           (UOTGHS->UOTGHS_SFR = UOTGHS_SFR_SRPIS)
+  //! Tests if a SRP occurs
+#define Is_otg_srp_interrupt()              (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_SRPI))
+//! @}
+
+//! @}
+
+
+#endif /* UOTGHS_DEVICE_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/uotghs_host.h b/hardware/digistump/sam/system/libsam/include/uotghs_host.h
new file mode 100644
index 0000000..bb16793
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/uotghs_host.h
@@ -0,0 +1,389 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef UOTGHS_HOST_H_INCLUDED
+#define UOTGHS_HOST_H_INCLUDED
+
+//! \ingroup usb_host_group
+//! \defgroup uhd_group USB Host Driver (UHD)
+//! UOTGHS low-level driver for USB host mode
+//!
+//! @{
+
+//! @name UOTGHS Host IP properties
+//!
+//! @{
+//! Get maximal number of endpoints
+#define uhd_get_pipe_max_nbr()                (9)
+#define UOTGHS_EPT_NUM                        (uhd_get_pipe_max_nbr()+1)
+//! @}
+
+//! @name Host Vbus line control
+//!
+//! VBOF is an optional output pin which allows to enable or disable
+//! the external VBus generator.
+//!
+//! @{
+//! Enables hardware control of USB_VBOF output pin when a Vbus error occur
+#define uhd_enable_vbus_error_hw_control()    (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSHWC))
+//! Disables hardware control of USB_VBOF output pin when a Vbus error occur
+#define uhd_disable_vbus_error_hw_control()   (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSHWC))
+
+//! Pin and function for USB_VBOF according to configuration from USB_VBOF
+#define USB_VBOF_PIN            USB_VBOF_GPIO
+#define USB_VBOF_FUNCTION       USB_VBOF_FLAGS
+//! Output USB_VBOF onto its pin
+#define uhd_output_vbof_pin() do {\
+	pio_configure_pin(USB_VBOF_PIN, USB_VBOF_FUNCTION); \
+} while (0)
+
+//! Set USB_VBOF output pin polarity
+#define uhd_set_vbof_active_high()            (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSPO))
+#define uhd_set_vbof_active_low()             (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBUSPO))
+//! Requests VBus activation
+#define uhd_enable_vbus()                     (Set_bits(UOTGHS->UOTGHS_SFR, UOTGHS_SR_VBUSRQ))
+//! Requests VBus deactivation
+#define uhd_disable_vbus()                    (Set_bits(UOTGHS->UOTGHS_SCR, UOTGHS_SR_VBUSRQ))
+//! Tests if VBus activation has been requested
+#define Is_uhd_vbus_enabled()                 (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBUSRQ))
+//! @}
+
+//! @name Host Vbus line monitoring
+//!
+//! The VBus level is always checked by USBC hardware.
+//!
+//! @{
+#define uhd_enable_vbus_error_interrupt()     (Set_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBERRE))
+#define uhd_disable_vbus_error_interrupt()    (Clr_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBERRE))
+#define Is_uhd_vbus_error_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBERRE))
+#define uhd_ack_vbus_error_interrupt()        (Set_bits(UOTGHS->UOTGHS_SCR, UOTGHS_SCR_VBERRIC))
+#define Is_uhd_vbus_error_interrupt()         (Tst_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_VBERRI))
+//! @}
+
+#define uhd_ack_errors_interrupt()            (UOTGHS->UOTGHS_SCR = (UOTGHS_SCR_VBERRIC|UOTGHS_SCR_BCERRIC|UOTGHS_SCR_HNPERRIC|UOTGHS_SCR_STOIC))
+#define Is_uhd_errors_interrupt()             (Tst_bits(UOTGHS->UOTGHS_CTRL, UOTGHS_CTRL_VBERRE|UOTGHS_CTRL_BCERRE|UOTGHS_CTRL_HNPERRE|UOTGHS_CTRL_STOE))
+#define uhd_enable_suspend_error_interrupt()
+#define uhd_enable_hnp_error_interrupt()
+#define uhd_enable_bconn_error_interrupt()
+
+//! @name USB device connection/disconnection monitoring
+//! @{
+#define uhd_enable_connection_int()           (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_DCONNIES)
+#define uhd_disable_connection_int()          (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_DCONNIEC)
+#define Is_uhd_connection_int_enabled()       (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_DCONNIE))
+#define uhd_ack_connection()                  (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_DCONNIC)
+#define Is_uhd_connection()                   (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_DCONNI))
+
+#define uhd_enable_disconnection_int()        (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_DDISCIES)
+#define uhd_disable_disconnection_int()       (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_DDISCIEC)
+#define Is_uhd_disconnection_int_enabled()    (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_DDISCIE))
+#define uhd_ack_disconnection()               (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_DDISCIC)
+#define Is_uhd_disconnection()                (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_DDISCI))
+//! @}
+
+//! @name USB device speed control
+//! @{
+#define uhd_get_speed_mode()                  (Rd_bits(UOTGHS->UOTGHS_SR, UOTGHS_SR_SPEED_Msk))
+#define Is_uhd_low_speed_mode()                 (uhd_get_speed_mode() == UOTGHS_SR_SPEED_LOW_SPEED)
+#define Is_uhd_full_speed_mode()                (uhd_get_speed_mode() == UOTGHS_SR_SPEED_FULL_SPEED)
+#define Is_uhd_high_speed_mode()                (uhd_get_speed_mode() == UOTGHS_SR_SPEED_HIGH_SPEED)
+//! Enable high speed mode
+# define uhd_enable_high_speed_mode()        (Wr_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SPDCONF_Msk, UOTGHS_HSTCTRL_SPDCONF_HIGH_SPEED))
+//! Disable high speed mode
+# define uhd_disable_high_speed_mode()       (Wr_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SPDCONF_Msk, UOTGHS_HSTCTRL_SPDCONF_FORCED_FS))
+//! @}
+
+//! @name Bus events control
+//! These macros manage the bus events: reset, SOF, resume, wakeup.
+//! @{
+
+//! Initiates a reset event
+//! @{
+#define uhd_start_reset()                            (Set_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESET))
+#define Is_uhd_starting_reset()                      (Tst_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESET))
+#define uhd_stop_reset()                             (Clr_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESET))
+
+#define uhd_enable_reset_sent_interrupt()            (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_RSTIES)
+#define uhd_disable_reset_sent_interrupt()           (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_RSTIEC)
+#define Is_uhd_reset_sent_interrupt_enabled()        (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_RSTIE))
+#define uhd_ack_reset_sent()                         (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_RSTIC)
+#define Is_uhd_reset_sent()                          (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_RSTI))
+//! @}
+
+//! Initiates a SOF events
+//! @{
+#define uhd_enable_sof()                             (Set_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SOFE))
+#define uhd_disable_sof()                            (Clr_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SOFE))
+#define Is_uhd_sof_enabled()                         (Tst_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_SOFE))
+#define uhd_get_sof_number()                         ((UOTGHS->UOTGHS_HSTFNUM&UOTGHS_HSTFNUM_FNUM_Msk)>>UOTGHS_HSTFNUM_FNUM_Pos)
+#define uhd_get_microsof_number()                    ((UOTGHS->UOTGHS_HSTFNUM&UOTGHS_HSTFNUM_MFNUM_Msk)>>UOTGHS_HSTFNUM_MFNUM_Pos)
+#define uhd_get_frame_position()                     (Rd_bits(UOTGHS->UOTGHS_HSTFNUM, UOTGHS_HSTFNUM_FLENHIGH_Msk))
+#define uhd_enable_sof_interrupt()                   (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_HSOFIES)
+#define uhd_disable_sof_interrupt()                  (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_HSOFIEC)
+#define Is_uhd_sof_interrupt_enabled()               (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_HSOFIE))
+#define uhd_ack_sof()                                (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_HSOFIC)
+#define Is_uhd_sof()                                 (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_HSOFI))
+//! @}
+
+//! Initiates a resume event
+//! It is called downstream resume event.
+//! @{
+#define uhd_send_resume()                            (Set_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESUME))
+#define Is_uhd_sending_resume()                      (Tst_bits(UOTGHS->UOTGHS_HSTCTRL, UOTGHS_HSTCTRL_RESUME))
+
+#define uhd_enable_downstream_resume_interrupt()     (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_RSMEDIES)
+#define uhd_disable_downstream_resume_interrupt()    (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_RSMEDIEC)
+#define Is_uhd_downstream_resume_interrupt_enabled() (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_RSMEDIE))
+#define uhd_ack_downstream_resume()                  (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_RSMEDIC)
+#define Is_uhd_downstream_resume()                   (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_RSMEDI))
+//! @}
+
+//! Detection of a wake-up event
+//! A wake-up event is received when the host controller is in the suspend mode:
+//! - and an upstream resume from the peripheral is detected.
+//! - and a peripheral disconnection is detected.
+//! @{
+#define uhd_enable_wakeup_interrupt()                (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_HWUPIES)
+#define uhd_disable_wakeup_interrupt()               (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_HWUPIEC)
+#define Is_uhd_wakeup_interrupt_enabled()            (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_HWUPIE))
+#define uhd_ack_wakeup()                             (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_HWUPIC)
+#define Is_uhd_wakeup()                              (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_HWUPI))
+
+#define uhd_enable_upstream_resume_interrupt()       (UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTIER_RXRSMIES)
+#define uhd_disable_upstream_resume_interrupt()      (UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_RXRSMIEC)
+#define Is_uhd_upstream_resume_interrupt_enabled()   (Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_RXRSMIE))
+#define uhd_ack_upstream_resume()                    (UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_RXRSMIC)
+#define Is_uhd_upstream_resume()                     (Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_RXRSMI))
+//! @}
+//! @}
+
+
+//! @name Pipes management
+//! @{
+
+//! USB address of pipes
+//! @{
+#define uhd_configure_address(p, addr) \
+		(Wr_bitfield((&UOTGHS->UOTGHS_HSTADDR1)[(p)>>2], \
+		UOTGHS_HSTADDR1_HSTADDRP0_Msk << (((p)&0x03)<<3), addr))
+#define uhd_get_configured_address(p) \
+		(Rd_bitfield((&UOTGHS->UOTGHS_HSTADDR1)[(p)>>2], \
+		UOTGHS_HSTADDR1_HSTADDRP0_Msk << (((p)&0x03)<<3)))
+//! @}
+
+//! Pipe enable
+//! Enable, disable, reset, freeze
+//! @{
+#define uhd_enable_pipe(p) \
+		(Set_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p)))
+#define uhd_disable_pipe(p) \
+		(Clr_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p)))
+#define Is_uhd_pipe_enabled(p) \
+		(Tst_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p)))
+#define uhd_reset_pipe(p) \
+		(Set_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p))); \
+		(Clr_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p)))
+#define Is_uhd_resetting_pipe(p) \
+		(Tst_bits(UOTGHS->UOTGHS_HSTPIP, UOTGHS_HSTPIP_PEN0 << (p)))
+#define uhd_freeze_pipe(p)                       (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_PFREEZES)
+#define uhd_unfreeze_pipe(p)                     (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_PFREEZEC)
+#define Is_uhd_pipe_frozen(p)                    (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_PFREEZE))
+#define uhd_reset_data_toggle(p)                 (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_RSTDTS)
+#define Is_uhd_data_toggle_reset(p)              (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_RSTDT))
+//! @}
+
+//! Pipe configuration
+//! @{
+#define uhd_configure_pipe_int_req_freq(p,freq)  (Wr_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_INTFRQ_Msk, (freq)))
+#define uhd_get_pipe_int_req_freq(p)             (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_INTFRQ_Msk))
+#define uhd_configure_pipe_endpoint_number(p,ep) (Wr_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PEPNUM_Msk, (ep)))
+#define uhd_get_pipe_endpoint_address(p) \
+		(uhd_is_pipe_in(p) ?\
+			(uhd_get_pipe_endpoint_number(p) | USB_EP_DIR_IN) :\
+			(uhd_get_pipe_endpoint_number(p) | USB_EP_DIR_OUT))
+#define uhd_get_pipe_endpoint_number(p)          (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], (UOTGHS_HSTPIPCFG_PEPNUM_Msk)))
+#define uhd_configure_pipe_type(p, type)         (Wr_bitfield(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PTYPE_Msk, type))
+#define uhd_get_pipe_type(p)                     (Rd_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PTYPE_Msk))
+#define uhd_enable_pipe_bank_autoswitch(p)       (Set_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_AUTOSW))
+#define uhd_disable_pipe_bank_autoswitch(p)      (Clr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_AUTOSW))
+#define Is_uhd_pipe_bank_autoswitch_enabled(p)   (Tst_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_AUTOSW))
+#define uhd_configure_pipe_token(p, token)       (Wr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PTOKEN_Msk, token))
+#define uhd_get_pipe_token(p)                    (Rd_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PTOKEN_Msk))
+#define uhd_is_pipe_in(p)                        (UOTGHS_HSTPIPCFG_PTOKEN_IN==uhd_get_pipe_token(p))
+#define uhd_is_pipe_out(p)                       (UOTGHS_HSTPIPCFG_PTOKEN_OUT==uhd_get_pipe_token(p))
+//! Bounds given integer size to allowed range and rounds it up to the nearest
+//! available greater size, then applies register format of UOTGHS controller
+//! for pipe size bit-field.
+#define uhd_format_pipe_size(size) \
+		(32 - clz(((uint32_t)min(max(size, 8), 1024) << 1) - 1) - 1 - 3)
+#define uhd_configure_pipe_size(p,size) \
+		(Wr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PSIZE_Msk, uhd_format_pipe_size(size)))
+#define uhd_get_pipe_size(p)                     (8<<((Rd_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], (UOTGHS_HSTPIPCFG_PSIZE_Msk)))>> UOTGHS_HSTPIPCFG_PSIZE_Pos))
+#define uhd_configure_pipe_bank(p,bank)          (Wr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PBK_Msk, (bank)))
+#define uhd_get_pipe_bank(p)                     (Rd_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PBK_Msk))
+#define uhd_allocate_memory(p)                   (Set_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_ALLOC))
+#define uhd_unallocate_memory(p)                 (Clr_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_ALLOC))
+#define Is_uhd_memory_allocated(p)               (Tst_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_ALLOC))
+
+//! Enable PING management only available in HS mode
+#  define uhd_enable_ping(p)                     (Set_bits(UOTGHS->UOTGHS_HSTPIPCFG[p], UOTGHS_HSTPIPCFG_PINGEN))
+//#endif
+#define uhd_configure_pipe(p, freq, ep_num, type, token, size, bank, bank_switch) \
+	(UOTGHS->UOTGHS_HSTPIPCFG[p] = \
+		(bank)|\
+		((uhd_format_pipe_size(size)<UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_CFGOK))
+//! @}
+
+//! Pipe main interrupts management
+//! @{
+#define uhd_enable_pipe_interrupt(p) 		(UOTGHS->UOTGHS_HSTIER = (UOTGHS_HSTIER_PEP_0 << (p)))
+#define uhd_disable_pipe_interrupt(p) 		(UOTGHS->UOTGHS_HSTIDR = (UOTGHS_HSTIDR_PEP_0 << (p)))
+#define Is_uhd_pipe_interrupt_enabled(p) 	(Tst_bits(UOTGHS->UOTGHS_HSTIMR, UOTGHS_HSTIMR_PEP_0 << (p)))
+#define Is_uhd_pipe_interrupt(p) 		(Tst_bits(UOTGHS->UOTGHS_HSTISR, UOTGHS_HSTISR_PEP_0 << (p)))
+//! returns the lowest pipe number generating a pipe interrupt or UOTGHS_EPT_NUM if none
+#define uhd_get_interrupt_pipe_number() \
+	(ctz(((UOTGHS->UOTGHS_HSTISR >> 8) & (UOTGHS->UOTGHS_HSTIMR >> 8)) | (1 << UOTGHS_EPT_NUM)))
+//! @}
+
+//! Pipe overflow and underflow for isochronous and interrupt endpoints
+//! @{
+#define uhd_enable_overflow_interrupt(p)         (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_OVERFIES)
+#define uhd_disable_overflow_interrupt(p)        (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_OVERFIEC)
+#define Is_uhd_overflow_interrupt_enabled(p)     (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_OVERFIE))
+#define uhd_ack_overflow_interrupt(p)            (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_OVERFIC)
+#define Is_uhd_overflow(p)                       (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_OVERFI))
+
+#define uhd_enable_underflow_interrupt(p)        (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_UNDERFIES)
+#define uhd_disable_underflow_interrupt(p)       (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_UNDERFIEC)
+#define Is_uhd_underflow_interrupt_enabled(p)    (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_UNDERFIE))
+#define uhd_ack_underflow_interrupt(p)           (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_UNDERFIC)
+#define Is_uhd_underflow(p)                      (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_UNDERFI))
+//! @}
+
+//! USB packet errors management
+//! @{
+#define uhd_enable_stall_interrupt(p)            (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_RXSTALLDES)
+#define uhd_disable_stall_interrupt(p)           (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_RXSTALLDEC)
+#define Is_uhd_stall_interrupt_enabled(p)        (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_RXSTALLDE))
+#define uhd_ack_stall(p)                         (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_RXSTALLDIC)
+#define Is_uhd_stall(p)                          (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_RXSTALLDI))
+
+#define uhd_enable_pipe_error_interrupt(p)       (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_PERRES)
+#define uhd_disable_pipe_error_interrupt(p)      (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_PERREC)
+#define Is_uhd_pipe_error_interrupt_enabled(p)   (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_PERRE))
+#define uhd_ack_all_errors(p)                    (UOTGHS->UOTGHS_HSTPIPERR[p] = 0UL)
+#define Is_uhd_pipe_error(p)                     (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_PERRI))
+#define uhd_error_status(p)                      (UOTGHS->UOTGHS_HSTPIPERR[p])
+#define Is_uhd_bad_data_toggle(p)                (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_DATATGL))
+#define Is_uhd_data_pid_error(p)                 (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_DATAPID))
+#define Is_uhd_pid_error(p)                      (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_PID))
+#define Is_uhd_timeout_error(p)                  (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_TIMEOUT))
+#define Is_uhd_crc16_error(p)                    (Tst_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_CRC16))
+#define uhd_get_error_counter(p)                 (Rd_bits(UOTGHS->UOTGHS_HSTPIPERR[p], UOTGHS_HSTPIPERR_COUNTER))
+//! @}
+
+//! Pipe data management
+//! @{
+#define uhd_data_toggle(p)                       (Rd_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_DTSEQ))
+
+#define uhd_enable_bank_interrupt(p)             (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_NBUSYBKES)
+#define uhd_disable_bank_interrupt(p)            (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_NBUSYBKEC)
+#define Is_uhd_bank_interrupt_enabled(p)         (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_NBUSYBKE))
+#define uhd_nb_busy_bank(p)                      (Rd_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_NBUSYBK_Msk))
+#define uhd_current_bank(p)                      (Rd_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_CURRBK_Msk ))
+
+#define uhd_enable_short_packet_interrupt(p)     (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_SHORTPACKETES)
+#define uhd_disable_short_packet_interrupt(p)    (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_SHORTPACKETIEC)
+#define Is_uhd_short_packet_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_SHORTPACKETIE))  )
+#define uhd_ack_short_packet(p)                  (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_SHORTPACKETIC)
+#define Is_uhd_short_packet(p)                   (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_SHORTPACKETI))
+#define uhd_byte_count(p)                        (Rd_bitfield(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_PBYCT_Msk))
+
+#define Is_uhd_fifocon(p)                        (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_FIFOCON))
+#define uhd_ack_fifocon(p)                       (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_FIFOCONC)
+
+#define uhd_enable_setup_ready_interrupt(p)      (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_TXSTPES)
+#define uhd_disable_setup_ready_interrupt(p)     (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_TXSTPEC)
+#define Is_uhd_setup_ready_interrupt_enabled(p)  (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_TXSTPE))
+#define uhd_ack_setup_ready(p)                   (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_TXSTPIC)
+#define Is_uhd_setup_ready(p)                    (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_TXSTPI))
+
+#define uhd_enable_in_received_interrupt(p)      (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_RXINES)
+#define uhd_disable_in_received_interrupt(p)     (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_RXINEC)
+#define Is_uhd_in_received_interrupt_enabled(p)  (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_RXINE))
+#define uhd_ack_in_received(p)                   (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_RXINIC)
+#define Is_uhd_in_received(p)                    (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_RXINI))
+
+#define uhd_enable_out_ready_interrupt(p)        (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_TXOUTES)
+#define uhd_disable_out_ready_interrupt(p)       (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_TXOUTEC)
+#define Is_uhd_out_ready_interrupt_enabled(p)    (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_TXOUTE))
+#define uhd_ack_out_ready(p)                     (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_TXOUTIC)
+#define Is_uhd_out_ready(p)                      (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_TXOUTI))
+#define uhd_raise_out_ready(p)                   (UOTGHS->UOTGHS_HSTPIPIFR[p] = UOTGHS_HSTPIPIFR_TXOUTIS)
+
+#define uhd_enable_nak_received_interrupt(p)     (UOTGHS->UOTGHS_HSTPIPIER[p] = UOTGHS_HSTPIPIER_NAKEDES)
+#define uhd_disable_nak_received_interrupt(p)    (UOTGHS->UOTGHS_HSTPIPIDR[p] = UOTGHS_HSTPIPIDR_NAKEDEC)
+#define Is_uhd_nak_received_interrupt_enabled(p) (Tst_bits(UOTGHS->UOTGHS_HSTPIPIMR[p], UOTGHS_HSTPIPIMR_NAKEDE))
+#define uhd_ack_nak_received(p)                  (UOTGHS->UOTGHS_HSTPIPICR[p] = UOTGHS_HSTPIPICR_NAKEDIC)
+#define Is_uhd_nak_received(p)                   (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_NAKEDI))
+
+#define Is_uhd_read_enabled(p)                   (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_RWALL))
+#define Is_uhd_write_enabled(p)                  (Tst_bits(UOTGHS->UOTGHS_HSTPIPISR[p], UOTGHS_HSTPIPISR_RWALL ))
+
+#define uhd_enable_continuous_in_mode(p)         (Set_bits(UOTGHS->UOTGHS_HSTPIPINRQ[p], UOTGHS_HSTPIPINRQ_INMODE))
+#define uhd_disable_continuous_in_mode(p)        (Clr_bits(UOTGHS->UOTGHS_HSTPIPINRQ[p], UOTGHS_HSTPIPINRQ_INMODE))
+#define Is_uhd_continuous_in_mode_enabled(p)     (Tst_bits(UOTGHS->UOTGHS_HSTPIPINRQ[p], UOTGHS_HSTPIPINRQ_INMODE))
+
+#define uhd_in_request_number(p, in_num)         (Set_bits(UOTGHS->UOTGHS_HSTPIPINRQ[p], (in_num)-1))
+#define uhd_get_in_request_number(p)             (((Rd_bits(UOTGHS->UOTGHS_HSTPIPINRQ[p], UOTGHS_HSTPIPINRQ_INRQ_Msk))>>UOTGHS_HSTPIPINRQ_INRQ_Pos)+1)
+//! @}
+
+//! Maximum transfer size on USB DMA
+#define UHD_PIPE_MAX_TRANS 0x8000
+
+//! Get 64-, 32-, 16- or 8-bit access to FIFO data register of selected pipe.
+//! @param p      Target Pipe number
+//! @param scale  Data scale in bits: 64, 32, 16 or 8
+//! @return       Volatile 64-, 32-, 16- or 8-bit data pointer to FIFO data register
+//! @warning It is up to the user of this macro to make sure that all accesses
+//! are aligned with their natural boundaries except 64-bit accesses which
+//! require only 32-bit alignment.
+//! @warning It is up to the user of this macro to make sure that used HSB
+//! addresses are identical to the DPRAM internal pointer modulo 32 bits.
+#define uhd_get_pipe_fifo_access(p, scale) \
+	(((volatile TPASTE2(U, scale) (*)[UHD_PIPE_MAX_TRANS / ((scale) / 8)])UOTGHS_RAM_ADDR)[(p)])
+
+#endif /* UOTGHS_HOST_H_INCLUDED */
diff --git a/hardware/digistump/sam/system/libsam/include/usart.h b/hardware/digistump/sam/system/libsam/include/usart.h
new file mode 100644
index 0000000..1a152e0
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/usart.h
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \par Purpose
+ *
+ * This module provides several definitions and methods for using an USART
+ * peripheral.
+ *
+ * \par Usage
+ *
+ * -# Enable the USART peripheral clock in the PMC.
+ * -# Enable the required USART PIOs (see pio.h).
+ * -# Configure the UART by calling USART_Configure.
+ * -# Enable the transmitter and/or the receiver of the USART using
+ *    USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
+ * -# Send data through the USART using the USART_Write and
+ *    USART_WriteBuffer methods.
+ * -# Receive data from the USART using the USART_Read and
+ *    USART_ReadBuffer functions; the availability of data can be polled
+ *    with USART_IsDataAvailable.
+ * -# Disable the transmitter and/or the receiver of the USART with
+ *    USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
+ */
+
+#ifndef _USART_
+#define _USART_
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "../chip.h"
+
+#include 
+
+/*------------------------------------------------------------------------------
+ *         Definitions
+ *------------------------------------------------------------------------------*/
+
+/** \section USART_mode USART modes
+ * This section lists several common operating modes for an USART peripheral.
+ *
+ * \b Modes
+ * - USART_MODE_ASYNCHRONOUS
+ * - USART_MODE_IRDA
+ */
+
+/** Basic asynchronous mode, i.e. 8 bits no parity.*/
+#define USART_MODE_ASYNCHRONOUS        (US_MR_CHRL_8_BIT | US_MR_PAR_NO)
+
+/** IRDA mode*/
+#define USART_MODE_IRDA                (AT91C_US_USMODE_IRDA | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_FILTER)
+
+/** SPI mode*/
+#define AT91C_US_USMODE_SPIM     0xE
+#define US_SPI_CPOL_0           (0x0<<16)
+#define US_SPI_CPHA_0            (0x0<<8)
+#define US_SPI_CPOL_1            (0x1<<16)
+#define US_SPI_CPHA_1            (0x1<<8)
+#define US_SPI_BPMODE_0    (US_SPI_CPOL_0|US_SPI_CPHA_1)
+#define US_SPI_BPMODE_1    (US_SPI_CPOL_0|US_SPI_CPHA_0)
+#define US_SPI_BPMODE_2    (US_SPI_CPOL_1|US_SPI_CPHA_1)
+#define US_SPI_BPMODE_3    (US_SPI_CPOL_1|US_SPI_CPHA_0)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/*         Exported functions                                                   */
+/*------------------------------------------------------------------------------*/
+
+extern void USART_Configure( Usart *usart, uint32_t mode, uint32_t baudrate, uint32_t masterClock ) ;
+extern uint32_t USART_GetStatus( Usart *usart ) ;
+extern void USART_EnableIt( Usart *usart,uint32_t mode ) ;
+extern void USART_DisableIt( Usart *usart,uint32_t mode ) ;
+extern void USART_SetTransmitterEnabled( Usart *usart, uint8_t enabled ) ;
+
+extern void USART_SetReceiverEnabled( Usart *usart, uint8_t enabled ) ;
+
+extern void USART_Write( Usart *usart, uint16_t data, volatile uint32_t timeOut ) ;
+
+extern uint8_t USART_WriteBuffer( Usart *usart, void *buffer, uint32_t size ) ;
+
+extern uint16_t USART_Read( Usart *usart, volatile uint32_t timeOut ) ;
+
+extern uint8_t USART_ReadBuffer( Usart *usart, void *buffer, uint32_t size ) ;
+
+extern uint8_t USART_IsDataAvailable( Usart *usart ) ;
+
+extern void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter);
+
+extern void USART_PutChar( Usart *usart, uint8_t c ) ;
+
+extern uint32_t USART_IsRxReady( Usart *usart ) ;
+
+extern uint8_t USART_GetChar( Usart *usart ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _USART_ */
+
diff --git a/hardware/digistump/sam/system/libsam/include/wdt.h b/hardware/digistump/sam/system/libsam/include/wdt.h
new file mode 100644
index 0000000..c76db01
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/include/wdt.h
@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \section Purpose
+ * Interface for Watchdog Timer (WDT) controller.
+ *
+ * \section Usage
+ * -# Enable watchdog with given mode using \ref WDT_Enable().
+ * -# Disable watchdog using \ref WDT_Disable()
+ * -# Restart the watchdog using \ref WDT_Restart().
+ * -# Get watchdog status using \ref  WDT_GetStatus().
+ * -# Caculate watchdog period value using \ref WDT_GetPeriod().
+ */
+
+#ifndef _WDT_
+#define _WDT_
+
+#include "../chip.h"
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode ) ;
+
+extern void WDT_Disable( Wdt* pWDT ) ;
+
+extern void WDT_Restart( Wdt* pWDT ) ;
+
+extern uint32_t WDT_GetStatus( Wdt* pWDT ) ;
+
+extern uint32_t WDT_GetPeriod( uint32_t dwMs ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _WDT_ */
+
diff --git a/hardware/digistump/sam/system/libsam/readme.txt b/hardware/digistump/sam/system/libsam/readme.txt
new file mode 100644
index 0000000..350b3cf
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/readme.txt
@@ -0,0 +1,33 @@
+Makefile into build_gcc folder build the SAM peripheral library and put it into ../../../cores/sam Arduino API folder
+
+/*
+ %atmel_license%
+*/
+=
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License 
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2010, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
diff --git a/hardware/digistump/sam/system/libsam/source/adc.c b/hardware/digistump/sam/system/libsam/source/adc.c
new file mode 100644
index 0000000..c06cd60
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/adc.c
@@ -0,0 +1,962 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/**
+ * \defgroup sam_drivers_adc_group Analog-to-digital Converter (ADC)
+ *
+ * Driver for the Analog-to-digital Converter. This driver provides access to the main
+ * features of the ADC controller.
+ *
+ * @{
+ */
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES
+/**
+ * \brief Initialize the given ADC with the specified ADC clock and startup time.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_mck Main clock of the device (value in Hz).
+ * \param ul_adc_clock Analog-to-Digital conversion clock (value in Hz).
+ * \param uc_startup ADC start up time. Please refer to the product datasheet
+ * for details.
+ *
+ * \return 0 on success.
+ */
+uint32_t adc_init(Adc *p_adc, const uint32_t ul_mck,
+		const uint32_t ul_adc_clock, const uint8_t uc_startup)
+{
+	uint32_t ul_prescal;
+
+	/*  Reset the controller. */
+	p_adc->ADC_CR = ADC_CR_SWRST;
+
+	/* Reset Mode Register. */
+	p_adc->ADC_MR = 0;
+
+	/* Reset PDC transfer. */
+	p_adc->ADC_PTCR = (ADC_PTCR_RXTDIS | ADC_PTCR_TXTDIS);
+	p_adc->ADC_RCR = 0;
+	p_adc->ADC_RNCR = 0;
+
+	ul_prescal = ul_mck / (2 * ul_adc_clock) - 1;
+	p_adc->ADC_MR |= ADC_MR_PRESCAL(ul_prescal) |
+			((uc_startup << ADC_MR_STARTUP_Pos) &
+			ADC_MR_STARTUP_Msk);
+	return 0;
+}
+#elif SAM3XA_SERIES
+/**
+ * \brief Initialize the given ADC with the specified ADC clock and startup time.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_mck Main clock of the device (value in Hz).
+ * \param ul_adc_clock Analog-to-Digital conversion clock (value in Hz).
+ * \param uc_startup ADC start up time. Please refer to the product datasheet
+ * for details.
+ *
+ * \return 0 on success.
+ */
+uint32_t adc_init(Adc *p_adc, const uint32_t ul_mck,
+		const uint32_t ul_adc_clock, const uint8_t uc_startuptime)
+{
+	uint32_t startup_table[] = { 0, 8, 16, 24, 64, 80, 96, 112, 512, 576, 640, 704, 768, 832, 896, 960 };
+	uint32_t ul_prescal, ul_startup,  ul_mr_startup, ul_real_adc_clock;
+	p_adc->ADC_CR = ADC_CR_SWRST;
+
+	/* Reset Mode Register. */
+	p_adc->ADC_MR = 0;
+
+	/* Reset PDC transfer. */
+	p_adc->ADC_PTCR = (ADC_PTCR_RXTDIS | ADC_PTCR_TXTDIS);
+	p_adc->ADC_RCR = 0;
+	p_adc->ADC_RNCR = 0;
+	if (ul_mck % (2 * ul_adc_clock)) {
+		// Division with reminder
+		ul_prescal = ul_mck / (2 * ul_adc_clock);
+	} else {
+		// Whole division
+		ul_prescal = ul_mck / (2 * ul_adc_clock) - 1;
+	}
+	ul_real_adc_clock = ul_mck / (2 * (ul_prescal + 1));
+
+	// ADC clocks needed to get ul_startuptime uS
+	ul_startup = (ul_real_adc_clock / 1000000) * uc_startuptime;
+
+	// Find correct MR_STARTUP value from conversion table
+	for (ul_mr_startup=0; ul_mr_startup<16; ul_mr_startup++) {
+		if (startup_table[ul_mr_startup] >= ul_startup)
+			break;
+	}
+	if (ul_mr_startup==16)
+		return -1;
+	p_adc->ADC_MR |= ADC_MR_PRESCAL(ul_prescal) |
+			((ul_mr_startup << ADC_MR_STARTUP_Pos) & ADC_MR_STARTUP_Msk);
+	return 0;
+}
+#elif SAM3U_SERIES
+/**
+ * \brief Initialize the given ADC with the specified ADC clock and startup time.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_mck Main clock of the device (value in Hz).
+ * \param ul_adc_clock Analog-to-Digital conversion clock (in Hz).
+ * \param ul_startuptime ADC startup time value (value in us).
+ * Please refer to the product datasheet for details.
+ * \param ul_offmode_startuptime  ADC off mode startup time value (in us).
+ * Please refer to the product datasheet for details.
+ *
+ * \return 0 on success.
+ */
+uint32_t adc_init(Adc *p_adc, const uint32_t ul_mck, const uint32_t ul_adc_clock,
+		const uint32_t ul_startuptime)
+{
+	uint32_t ul_prescal, ul_startup;
+	p_adc->ADC_CR = ADC_CR_SWRST;
+
+	/* Reset Mode Register. */
+	p_adc->ADC_MR = 0;
+
+	/* Reset PDC transfer. */
+	p_adc->ADC_PTCR = (ADC_PTCR_RXTDIS | ADC_PTCR_TXTDIS);
+	p_adc->ADC_RCR = 0;
+	p_adc->ADC_RNCR = 0;
+	ul_prescal = ul_mck / (2 * ul_adc_clock) - 1;
+	ul_startup = ((ul_adc_clock / 1000000) * ul_startuptime / 8) - 1;
+	p_adc->ADC_MR |= ADC_MR_PRESCAL(ul_prescal) |
+			((ul_startup << ADC_MR_STARTUP_Pos) &
+			ADC_MR_STARTUP_Msk);
+	return 0;
+}
+
+#endif
+
+/**
+ * \brief Configure the conversion resolution.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param resolution ADC resolution.
+ *
+ */
+void adc_set_resolution(Adc *p_adc,const enum adc_resolution_t resolution)
+{
+	p_adc->ADC_MR |= (resolution << 4) & ADC_MR_LOWRES;
+}
+
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Configure conversion trigger and free run mode.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param trigger Conversion trigger.
+ * \param uc_freerun ADC_MR_FREERUN_ON enables freerun mode,
+ * ADC_MR_FREERUN_OFF disables freerun mode.
+ *
+ */
+void adc_configure_trigger(Adc *p_adc, const enum adc_trigger_t trigger,
+		uint8_t uc_freerun)
+{
+	p_adc->ADC_MR |= trigger | ((uc_freerun << 7) & ADC_MR_FREERUN);
+}
+#elif SAM3U_SERIES
+/**
+ * \brief Configure conversion trigger and free run mode.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param trigger Conversion trigger.
+ */
+void adc_configure_trigger(Adc *p_adc, const enum adc_trigger_t trigger)
+{
+	p_adc->ADC_MR |= trigger;
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Configures ADC power saving mode.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param uc_sleep ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference voltage
+ * circuitry ON between conversions.
+ * ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry OFF
+ * between conversions.
+ * \param uc_fwup ADC_MR_FWUP_OFF configures sleep mode as uc_sleep setting,
+ * ADC_MR_FWUP_ON keeps voltage reference ON and ADC Core OFF between conversions.
+ */
+void adc_configure_power_save(Adc *p_adc, const uint8_t uc_sleep, const uint8_t uc_fwup)
+{
+	p_adc->ADC_MR |= (((uc_sleep << 5) & ADC_MR_SLEEP) |
+			((uc_fwup << 6) & ADC_MR_FWUP));
+}
+#elif SAM3U_SERIES
+/**
+ * \brief Configure ADC power saving mode.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param uc_sleep ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference
+ * voltage circuitry ON between conversions.
+ * ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry
+ * OFF between conversions.
+ * \param uc_offmode 0 for Standby Mode (if Sleep Bit = 1), 1 for Off Mode.
+ */
+void adc_configure_power_save(Adc *p_adc, const uint8_t uc_sleep)
+{
+	p_adc->ADC_MR |= ((uc_sleep << 5) & ADC_MR_SLEEP);
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Configure conversion sequence.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ch_list Channel sequence list.
+ * \param number Number of channels in the list.
+ */
+void adc_configure_sequence(Adc *p_adc, const enum adc_channel_num_t ch_list[],
+		uint8_t uc_num)
+{
+	uint8_t uc_counter;
+	if (uc_num < 8) {
+		for (uc_counter = 0; uc_counter < uc_num; uc_counter++) {
+			p_adc->ADC_SEQR1 |=
+					ch_list[uc_counter] << (4 * uc_counter);
+		}
+	} else {
+		for (uc_counter = 0; uc_counter < 8; uc_counter++) {
+			p_adc->ADC_SEQR1 |=
+					ch_list[uc_counter] << (4 * uc_counter);
+		}
+		for (uc_counter = 0; uc_counter < uc_num - 8; uc_counter++) {
+			p_adc->ADC_SEQR2 |=
+					ch_list[uc_counter] << (4 * uc_counter);
+		}
+	}
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES ||  SAM3XA_SERIES
+/**
+ * \brief Configure ADC timing.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param uc_tracking ADC tracking time = uc_tracking / ADC clock.
+ * \param uc_settling Analog settling time = (uc_settling + 1) / ADC clock.
+ * \param uc_transfer Data transfer time = (uc_transfer * 2 + 3) / ADC clock.
+ */
+void adc_configure_timing(Adc *p_adc, const uint8_t uc_tracking,
+		const enum adc_settling_time_t settling,const uint8_t uc_transfer)
+{
+	p_adc->ADC_MR |= ADC_MR_TRANSFER(uc_transfer)
+			| settling | ADC_MR_TRACKTIM(uc_tracking);
+}
+#elif  SAM3N_SERIES
+/**
+ * \brief Configure ADC timing.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param uc_tracking ADC tracking time = uc_tracking / ADC clock.
+ */
+void adc_configure_timing(Adc *p_adc, const uint8_t uc_tracking)
+{
+	p_adc->ADC_MR |= ADC_MR_TRACKTIM(uc_tracking);
+}
+#elif SAM3U_SERIES
+/**
+ * \brief Configure ADC timing.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_sh ADC sample and hold time = uc_sh / ADC clock.
+ */
+void adc_configure_timing(Adc *p_adc, const uint32_t ul_sh)
+{
+	p_adc->ADC_MR |= ADC_MR_SHTIM(ul_sh);
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
+/**
+ * \brief Enable analog change.
+ *
+ * \note It allows different analog settings for each channel.
+ *
+ * \param p_Adc Pointer to an ADC instance.
+ */
+void adc_enable_anch(Adc *p_adc)
+{
+	p_adc->ADC_MR |= ADC_MR_ANACH;
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
+/**
+ * \brief Disable analog change.
+ *
+ * \note DIFF0, GAIN0 and OFF0 are used for all channels.
+ *
+ * \param p_Adc Pointer to an ADC instance.
+ */
+void adc_disable_anch(Adc *p_adc)
+{
+	p_adc->ADC_MR &= ~ADC_MR_ANACH;
+}
+#endif
+
+/**
+ * \brief Start analog-to-digital conversion.
+ *
+ * \note If one of the hardware event is selected as ADC trigger,
+ * this function can NOT start analog to digital conversion.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+
+void adc_start(Adc *p_adc)
+{
+	p_adc->ADC_CR = ADC_CR_START;
+}
+
+/**
+ * \brief Stop analog-to-digital conversion.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc_stop(Adc *p_adc)
+{
+	p_adc->ADC_CR = ADC_CR_SWRST;
+}
+
+/**
+ * \brief Enable the specified ADC channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param adc_ch ADC channel number.
+ */
+void adc_enable_channel(Adc *p_adc, const enum adc_channel_num_t adc_ch)
+{
+	p_adc->ADC_CHER = 1 << adc_ch;
+}
+
+/**
+ * \brief Enable all ADC channels.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc_enable_all_channel(Adc *p_adc)
+{
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+	p_adc->ADC_CHER = 0xFFFF;
+#elif SAM3U_SERIES
+	p_adc->ADC_CHER = 0xFF;
+#endif
+}
+
+/**
+ * \brief Disable the specified ADC channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param adc_ch ADC channel number.
+ */
+void adc_disable_channel(Adc *p_adc, const enum adc_channel_num_t adc_ch)
+{
+	p_adc->ADC_CHDR = 1 << adc_ch;
+}
+
+/**
+ * \brief Disable all ADC channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc_disable_all_channel(Adc *p_adc)
+{
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+	p_adc->ADC_CHDR = 0xFFFF;
+#elif SAM3U_SERIES
+	p_adc->ADC_CHDR = 0xFF;
+#endif
+}
+
+/**
+ * \brief Read the ADC channel status.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param adc_ch ADC channel number.
+ *
+ * \retval 1 if channel is enabled.
+ * \retval 0 if channel is disabled.
+ */
+uint32_t adc_get_channel_status(const Adc *p_adc, const enum adc_channel_num_t adc_ch)
+{
+	return p_adc->ADC_CHSR & (1 << adc_ch);
+}
+
+/**
+ * \brief Read the ADC result data of the specified channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param adc_ch ADC channel number.
+ *
+ * \return ADC value of the specified channel.
+ */
+uint32_t adc_get_channel_value(const Adc *p_adc, const enum adc_channel_num_t adc_ch)
+{
+	uint32_t ul_data = 0;
+
+	if (15 >= adc_ch) {
+		ul_data = *(p_adc->ADC_CDR + adc_ch);
+	}
+
+	return ul_data;
+}
+
+/**
+ * \brief Read the last ADC result data.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ *
+ * \return ADC latest value.
+ */
+uint32_t adc_get_latest_value(const Adc *p_adc)
+{
+	return p_adc->ADC_LCDR;
+}
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Enable TAG option so that the number of the last converted channel
+ * can be indicated.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc_enable_tag(Adc *p_adc)
+{
+	p_adc->ADC_EMR |= ADC_EMR_TAG;
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Disable TAG option.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc_disable_tag(Adc *p_adc)
+{
+	p_adc->ADC_EMR &= ~ADC_EMR_TAG;
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Indicate the last converted channel.
+ *
+ * \note If TAG option is NOT enabled before, an incorrect channel
+ * number is returned.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ *
+ * \return The last converted channel number.
+ */
+enum adc_channel_num_t adc_get_tag(const Adc *p_adc)
+{
+	return (p_adc->ADC_LCDR & ADC_LCDR_CHNB_Msk) >> ADC_LCDR_CHNB_Pos;
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Enable conversion sequencer.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc_start_sequencer(Adc *p_adc)
+{
+	p_adc->ADC_MR |= ADC_MR_USEQ;
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Disable conversion sequencer.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc_stop_sequencer(Adc *p_adc)
+{
+	p_adc->ADC_MR &= ~ADC_MR_USEQ;
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Configure comparison mode.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param uc_mode ADC comparison mode.
+ */
+void adc_set_comparison_mode(Adc *p_adc, const uint8_t uc_mode)
+{
+	p_adc->ADC_EMR &= (uint32_t) ~ (ADC_EMR_CMPMODE_Msk);
+	p_adc->ADC_EMR |= (uc_mode & ADC_EMR_CMPMODE_Msk);
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Get comparison mode.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ *
+ * \retval Compare mode value.
+ */
+uint32_t adc_get_comparison_mode(const Adc *p_adc)
+{
+	return p_adc->ADC_EMR & ADC_EMR_CMPMODE_Msk;
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Configure ADC compare window.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param w_low_threshold Low threshold of compare window.
+ * \param w_high_threshold High threshold of compare window.
+ */
+void adc_set_comparison_window(Adc *p_adc, const uint16_t us_low_threshold,
+		const uint16_t us_high_threshold)
+{
+	p_adc->ADC_CWR = ADC_CWR_LOWTHRES(us_low_threshold) |
+			ADC_CWR_HIGHTHRES(us_high_threshold);
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Configure comparison selected channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param channel ADC channel number.
+ */
+void adc_set_comparison_channel(Adc *p_adc, const enum adc_channel_num_t channel)
+{
+	if (channel < 16) {
+		p_adc->ADC_EMR &= (uint32_t) ~ (ADC_EMR_CMPALL);
+		p_adc->ADC_EMR &= (uint32_t) ~ (ADC_EMR_CMPSEL_Msk);
+		p_adc->ADC_EMR |= (channel << ADC_EMR_CMPSEL_Pos);
+	} else {
+		p_adc->ADC_EMR |= ADC_EMR_CMPALL;
+	}
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
+/**
+ * \brief Enable differential input for the specified channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param channel ADC channel number.
+ */
+void adc_enable_channel_differential_input(Adc *p_adc, const enum adc_channel_num_t channel)
+{
+	p_adc->ADC_COR |= 0x01u << (16 + channel);
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
+/**
+ * \brief Disable differential input for the specified channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param channel ADC channel number.
+ */
+void adc_disable_channel_differential_input(Adc *p_adc, const enum adc_channel_num_t channel)
+{
+	uint32_t ul_temp;
+	ul_temp = p_adc->ADC_COR;
+	p_adc->ADC_COR &= 0xfffeffffu << channel;
+	p_adc->ADC_COR |= ul_temp;
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
+/**
+ * \brief Enable analog signal offset for the specified channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param channel ADC channel number.
+ */
+void adc_enable_channel_input_offset(Adc *p_adc, const enum adc_channel_num_t channel)
+{
+	p_adc->ADC_COR |= 0x01u << channel;
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
+/**
+ * \brief Disable analog signal offset for the specified channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param channel ADC channel number.
+ */
+void adc_disable_channel_input_offset(Adc *p_adc, const enum adc_channel_num_t channel)
+{
+	uint32_t ul_temp;
+	ul_temp = p_adc->ADC_COR;
+	p_adc->ADC_COR &= (0xfffffffeu << channel);
+	p_adc->ADC_COR |= ul_temp;
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
+/**
+ * \brief Configure input gain for the specified channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param channel ADC channel number.
+ * \param gain Gain value for the input.
+ */
+void adc_set_channel_input_gain(Adc *p_adc, const enum adc_channel_num_t channel,
+		const enum adc_gainvalue_t gain)
+{
+	p_adc->ADC_CGR |= (0x03u << (2 * channel)) & (gain << (2 * channel));
+}
+#endif
+
+#if SAM3SD8_SERIES || SAM4S_SERIES
+/**
+ * \brief Set ADC auto calibration mode.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc_set_calibmode(Adc * p_adc)
+{
+	p_adc->ADC_CR |= ADC_CR_AUTOCAL;
+}
+#endif
+
+/**
+ * \brief Return the actual ADC clock.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_mck Main clock of the device (in Hz).
+ *
+ * \return The actual ADC clock (in Hz).
+ */
+uint32_t adc_get_actual_adc_clock(const Adc *p_adc, const uint32_t ul_mck)
+{
+	uint32_t ul_adcfreq;
+	uint32_t ul_prescal;
+
+	/* ADCClock = MCK / ( (PRESCAL+1) * 2 ) */
+	ul_prescal = ((p_adc->ADC_MR & ADC_MR_PRESCAL_Msk) >> ADC_MR_PRESCAL_Pos);
+	ul_adcfreq = ul_mck / ((ul_prescal + 1) * 2);
+	return ul_adcfreq;
+}
+
+/**
+ * \brief Enable ADC interrupts.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_source Interrupts to be enabled.
+ */
+void adc_enable_interrupt(Adc *p_adc, const uint32_t ul_source)
+{
+	p_adc->ADC_IER = ul_source;
+}
+
+/**
+ * \brief Disable ADC interrupts.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_source Interrupts to be disabled.
+ */
+void adc_disable_interrupt(Adc *p_adc, const uint32_t ul_source)
+{
+	p_adc->ADC_IDR = ul_source;
+}
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Get ADC interrupt and overrun error status.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ *
+ * \return ADC status structure.
+ */
+uint32_t adc_get_status(const Adc *p_adc)
+{
+	return p_adc->ADC_ISR;
+}
+
+/**
+ * \brief Get ADC interrupt and overrun error status.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ *
+ * \return ADC status structure.
+ */
+uint32_t adc_get_overrun_status(const Adc *p_adc)
+{
+	return p_adc->ADC_OVER;
+}
+#elif SAM3U_SERIES
+/**
+ * \brief Read ADC interrupt and overrun error status.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ *
+ * \retval ADC status structure.
+ */
+uint32_t adc_get_status(const Adc *p_adc)
+{
+	return p_adc->ADC_SR;
+}
+#endif
+
+/**
+ * \brief Read ADC interrupt mask.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ *
+ * \return The interrupt mask value.
+ */
+uint32_t adc_get_interrupt_mask(const Adc *p_adc)
+{
+	return p_adc->ADC_IMR;
+}
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
+/**
+ * \brief Adapt performance versus power consumption.
+ *
+ * \note Please refer to ADC Characteristics in the product datasheet
+ * for more details.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ibctl ADC Bias current control.
+ */
+void adc_set_bias_current(Adc *p_adc, const uint8_t uc_ibctl)
+{
+	p_adc->ADC_ACR |= ADC_ACR_IBCTL(uc_ibctl);
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
+/**
+ * \brief Turn on temperature sensor.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc_enable_ts(Adc *p_adc)
+{
+	p_adc->ADC_ACR |= ADC_ACR_TSON;
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3XA_SERIES
+/**
+ * \brief Turn off temperature sensor.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc_disable_ts(Adc *p_adc)
+{
+	p_adc->ADC_ACR &= ~ADC_ACR_TSON;
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Enable or disable write protection of ADC registers.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_enable 1 to enable, 0 to disable.
+ */
+void adc_set_writeprotect(Adc *p_adc, const uint32_t ul_enable)
+{
+	p_adc->ADC_WPMR |= ADC_WPMR_WPKEY(ul_enable);
+}
+#endif
+
+#if SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3XA_SERIES
+/**
+ * \brief Indicate write protect status.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ *
+ * \return 0 if the peripheral is not protected, or 16-bit write protect
+ * violation Status.
+ */
+uint32_t adc_get_writeprotect_status(const Adc *p_adc)
+{
+	return p_adc->ADC_WPSR & ADC_WPSR_WPVS;
+}
+#endif
+
+#if 0
+/**
+ * \brief calcul_startup
+ */
+static uint32_t calcul_startup(const uint32_t ul_startup)
+{
+	uint32_t ul_startup_value = 0;
+
+	if (ul_startup == 0)
+		ul_startup_value = 0;
+	else if (ul_startup == 1)
+		ul_startup_value = 8;
+	else if (ul_startup == 2)
+		ul_startup_value = 16;
+	else if (ul_startup == 3)
+		ul_startup_value = 24;
+	else if (ul_startup == 4)
+		ul_startup_value = 64;
+	else if (ul_startup == 5)
+		ul_startup_value = 80;
+	else if (ul_startup == 6)
+		ul_startup_value = 96;
+	else if (ul_startup == 7)
+		ul_startup_value = 112;
+	else if (ul_startup == 8)
+		ul_startup_value = 512;
+	else if (ul_startup == 9)
+		ul_startup_value = 576;
+	else if (ul_startup == 10)
+		ul_startup_value = 640;
+	else if (ul_startup == 11)
+		ul_startup_value = 704;
+	else if (ul_startup == 12)
+		ul_startup_value = 768;
+	else if (ul_startup == 13)
+		ul_startup_value = 832;
+	else if (ul_startup == 14)
+		ul_startup_value = 896;
+	else if (ul_startup == 15)
+		ul_startup_value = 960;
+
+	return ul_startup_value;
+}
+
+/**
+ * \brief Check ADC configurations.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_mck Main clock of the device (in Hz).
+ */
+void adc_check(Adc *p_adc, const uint32_t ul_mck)
+{
+	uint32_t ul_adcfreq;
+	uint32_t ul_prescal;
+	uint32_t ul_startup;
+
+	/* ADCClock = MCK / ( (PRESCAL+1) * 2 ) */
+	ul_prescal = ((p_adc->ADC_MR & ADC_MR_PRESCAL_Msk) >>
+			ADC_MR_PRESCAL_Pos);
+	ul_adcfreq = ul_mck / ((ul_prescal + 1) * 2);
+	printf("ADC clock frequency = %d Hz\r\n", (int)ul_adcfreq);
+
+	if (ul_adcfreq < ADC_FREQ_MIN) {
+		printf("adc frequency too low (out of specification: %d Hz)\r\n",
+			(int)ADC_FREQ_MIN);
+	}
+	if (ul_adcfreq > ADC_FREQ_MAX) {
+		printf("adc frequency too high (out of specification: %d Hz)\r\n",
+			(int)ADC_FREQ_MAX);
+	}
+
+	ul_startup = ((p_adc->ADC_MR & ADC_MR_STARTUP_Msk) >>
+			ADC_MR_STARTUP_Pos);
+	if (!(p_adc->ADC_MR & ADC_MR_SLEEP_SLEEP)) {
+		/* 40ms */
+		if (ADC_STARTUP_NORM * ul_adcfreq / 1000000 >
+				calcul_startup(ul_startup)) {
+			printf("Startup time too small: %d, programmed: %d\r\n",
+					(int)(ADC_STARTUP_NORM * ul_adcfreq /
+							1000000),
+					(int)calcul_startup(ul_startup));
+		}
+	} else {
+		if (p_adc->ADC_MR & ADC_MR_FREERUN_ON) {
+			puts("FreeRun forbidden in sleep mode\r");
+		}
+		if (!(p_adc->ADC_MR & ADC_MR_FWUP_ON)) {
+			/* Sleep 40ms */
+			if (ADC_STARTUP_NORM * ul_adcfreq / 1000000 >
+					calcul_startup(ul_startup)) {
+				printf("Startup time too small: %d, programmed: %d\r\n",
+					(int)(ADC_STARTUP_NORM * ul_adcfreq / 1000000),
+					(int)(calcul_startup(ul_startup)));
+			}
+		} else {
+			if (p_adc->ADC_MR & ADC_MR_FWUP_ON) {
+				/* Fast Wake Up Sleep Mode: 12ms */
+				if (ADC_STARTUP_FAST * ul_adcfreq / 1000000 >
+						calcul_startup(ul_startup)) {
+					printf("Startup time too small: %d, programmed: %d\r\n",
+						(int)(ADC_STARTUP_NORM * ul_adcfreq / 1000000),
+						(int)(calcul_startup(ul_startup)));
+				}
+			}
+		}
+	}
+}
+#endif
+
+/**
+ * \brief Get PDC registers base address.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ *
+ * \return ADC PDC register base address.
+ */
+Pdc *adc_get_pdc_base(const Adc *p_adc)
+{
+	return PDC_ADC;
+}
+
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
\ No newline at end of file
diff --git a/hardware/digistump/sam/system/libsam/source/adc12_sam3u.c b/hardware/digistump/sam/system/libsam/source/adc12_sam3u.c
new file mode 100644
index 0000000..77def4d
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/adc12_sam3u.c
@@ -0,0 +1,399 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/**
+ * \defgroup sam_drivers_adc_group Analog-to-digital Converter (ADC)
+ *
+ * Driver for the Analog-to-digital Converter. This driver provides access to the main
+ * features of the ADC controller.
+ *
+ * @{
+ */
+
+#if SAM3U_SERIES
+
+/**
+ * \brief Initialize the given ADC with the specified ADC clock and startup time.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_mck Main clock of the device (in Hz).
+ * \param ul_adc_clock Analog-to-Digital conversion clock (in Hz).
+ * \param ul_startuptime ADC startup time value (value in us).
+ * Please refer to the product datasheet for more details.
+ * \param ul_offmode_startuptime ADC off mode startup time value (value in us).
+ * Please refer to the product datasheet for more details.
+ *
+ * \return 0 on success.
+ */
+uint32_t adc12b_init(Adc12b *p_adc, const uint32_t ul_mck, const uint32_t ul_adc_clock,
+		const uint32_t ul_startuptime, const uint32_t ul_offmode_startuptime)
+{
+	uint32_t ul_prescal, ul_startup, ul_offmode;
+	p_adc->ADC12B_CR = ADC12B_CR_SWRST;
+
+	/* Reset Mode Register */
+	p_adc->ADC12B_MR = 0;
+
+	/* Reset PDC transfer */
+	p_adc->ADC12B_PTCR = (ADC12B_PTCR_RXTDIS | ADC12B_PTCR_TXTDIS);
+	p_adc->ADC12B_RCR = 0;
+	p_adc->ADC12B_RNCR = 0;
+	ul_prescal = ul_mck / (2 * ul_adc_clock) - 1;
+	ul_startup = ((ul_adc_clock / 1000000) * ul_startuptime / 8) - 1;
+	ul_offmode = ((ul_adc_clock / 1000000) * ul_offmode_startuptime / 8) -
+			1;
+	p_adc->ADC12B_MR |=
+			ADC12B_MR_PRESCAL(ul_prescal) | ((ul_startup <<
+					ADC12B_MR_STARTUP_Pos) &
+			ADC12B_MR_STARTUP_Msk);
+	p_adc->ADC12B_EMR |= (ul_offmode << 16) & (0xffu << 16);
+	return 0;
+}
+
+/**
+ * \brief Configure conversion resolution.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param resolution ADC resolution.
+ */
+void adc12b_set_resolution(Adc12b *p_adc, const enum adc_resolution_t resolution)
+{
+	p_adc->ADC12B_MR |= (resolution << 4) & ADC12B_MR_LOWRES;
+}
+
+/**
+ * \brief Configure conversion trigger and free run mode.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param trigger Conversion trigger.
+ */
+void adc12b_configure_trigger(Adc12b *p_adc, const enum adc_trigger_t trigger)
+{
+	p_adc->ADC12B_MR |= trigger;
+}
+
+/**
+ * \brief Configure ADC power saving mode.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param uc_sleep ADC_MR_SLEEP_NORMAL keeps the ADC Core and reference
+ * voltage circuitry ON between conversions.
+ * ADC_MR_SLEEP_SLEEP keeps the ADC Core and reference voltage circuitry
+ * OFF between conversions.
+ * \param uc_offmode 0 Standby Mode (if Sleep Bit = 1), 1 Off Mode.
+ */
+void adc12b_configure_power_save(Adc12b *p_adc, const uint8_t uc_sleep,
+		uint8_t uc_offmode)
+{
+	p_adc->ADC12B_MR |= ((uc_sleep << 5) & ADC12B_MR_SLEEP);
+	p_adc->ADC12B_EMR |= uc_offmode;
+}
+
+/**
+ * \brief Configure ADC timing.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_sh ADC sample and hold time = uc_sh / ADC clock.
+ */
+void adc12b_configure_timing(Adc12b *p_adc, const uint32_t ul_sh)
+{
+	p_adc->ADC12B_MR |= ADC12B_MR_SHTIM(ul_sh);
+}
+
+/**
+ * \brief Start ADC conversion.
+ *
+ * \note If one of the hardware event is selected as ADC trigger,
+ * this function can NOT start ADC conversion.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc12b_start(Adc12b *p_adc)
+{
+	p_adc->ADC12B_CR = ADC12B_CR_START;
+}
+
+/**
+ * \brief Stop ADC conversion.
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc12b_stop(Adc12b *p_adc)
+{
+	p_adc->ADC12B_CR = ADC12B_CR_SWRST;
+}
+
+/**
+ * \brief Enable the specified ADC channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param adc_ch ADC channel number.
+ */
+void adc12b_enable_channel(Adc12b *p_adc, const enum adc_channel_num_t adc_ch)
+{
+	p_adc->ADC12B_CHER = 1 << adc_ch;
+}
+
+/**
+ * \brief Enable all ADC channels.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc12b_enable_all_channel(Adc12b *p_adc)
+{
+	p_adc->ADC12B_CHER = 0xFF;
+}
+
+/**
+ * \brief Disable the specified ADC channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param adc_ch ADC channel number.
+ */
+void adc12b_disable_channel(Adc12b *p_adc, const enum adc_channel_num_t adc_ch)
+{
+	p_adc->ADC12B_CHDR = 1 << adc_ch;
+}
+
+/**
+ * \brief Disable all ADC channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc12b_disable_all_channel(Adc12b *p_adc)
+{
+	p_adc->ADC12B_CHDR = 0xFF;
+}
+
+/**
+ * \brief Read the ADC channel status.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param adc_ch ADC channel number.
+ *
+ * \retval 1 if channel is enabled.
+ * \retval 0 if channel is disabled.
+ */
+uint32_t adc12b_get_channel_status(const Adc12b *p_adc, const enum adc_channel_num_t adc_ch)
+{
+	return p_adc->ADC12B_CHSR & (1 << adc_ch);
+}
+
+/**
+ * \brief Read the ADC result data of the specified channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param adc_ch ADC channel number.
+ *
+ * \return ADC value of the specified channel.
+ */
+uint32_t adc12b_get_channel_value(const Adc12b *p_adc,const enum adc_channel_num_t adc_ch)
+{
+	uint32_t dwData = 0;
+
+	if (15 >= adc_ch) {
+		dwData = *(p_adc->ADC12B_CDR + adc_ch);
+	}
+
+	return dwData;
+}
+
+/**
+ * \brief Read the last ADC result data.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ *
+ * \return ADC latest value.
+ */
+uint32_t adc12b_get_latest_value(const Adc12b *p_adc)
+{
+	return p_adc->ADC12B_LCDR;
+}
+
+/**
+ * \brief Enable differential input for all channels.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc12b_enable_differential_input(Adc12b *p_adc)
+{
+	p_adc->ADC12B_ACR |= (0x01u << 16);
+}
+
+/**
+ * \brief Disable differential input for the specified channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc12b_disable_differential_input(Adc12b *p_adc)
+{
+	p_adc->ADC12B_ACR &= (0x01u << 16);
+}
+
+/**
+ * \brief Enable analog signal offset for the specified channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc12b_enable_input_offset(Adc12b *p_adc)
+{
+	p_adc->ADC12B_ACR |= (0x01u << 17);
+}
+
+/**
+ * \brief Disable analog signal offset for the specified channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ */
+void adc12b_disable_input_offset(Adc12b *p_adc)
+{
+	p_adc->ADC12B_ACR &= (0x01u << 17);
+}
+
+/**
+ * \brief Configure input gain for the specified channel.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param gain Gain value for the input.
+ */
+void adc12b_set_input_gain(Adc12b *p_adc, const enum adc_gainvalue_t gain)
+{
+	p_adc->ADC12B_ACR |= (0x03u & gain);
+}
+
+/**
+ * \brief Return the actual ADC clock.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_mck Main clock of the device (in Hz).
+ *
+ * \retval 0 The actual ADC clock (in Hz).
+ */
+uint32_t adc12b_get_actual_adc_clock(const Adc12b *p_adc, const uint32_t ul_mck)
+{
+	uint32_t ul_adcfreq;
+	uint32_t ul_prescal;
+
+	/* ADCClock = MCK / ( (PRESCAL+1) * 2 ) */
+	ul_prescal = ((p_adc->ADC12B_MR & ADC12B_MR_PRESCAL_Msk) >>
+			ADC12B_MR_PRESCAL_Pos);
+	ul_adcfreq = ul_mck / ((ul_prescal + 1) * 2);
+	return ul_adcfreq;
+}
+
+/**
+ * \brief Enable ADC interrupts.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_source Interrupts to be enabled.
+ */
+void adc12b_enable_interrupt(Adc12b *p_adc, const uint32_t ul_source)
+{
+	p_adc->ADC12B_IER = ul_source;
+}
+
+/**
+ * \brief Disable ADC interrupts.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param ul_source Interrupts to be disabled.
+ */
+void adc12b_disable_interrupt(Adc12b *p_adc, const uint32_t ul_source)
+{
+	p_adc->ADC12B_IDR = ul_source;
+}
+
+/** \brief Read ADC interrupt mask.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ *
+ * \return The interrupt mask value.
+ */
+uint32_t adc12b_get_interrupt_mask(const Adc12b *p_adc)
+{
+	return p_adc->ADC12B_IMR;
+}
+
+/**
+ * \brief Read ADC interrupt status.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ *
+ * \retval ADC interrupt status.
+ */
+uint32_t adc12b_get_status(const Adc12b *p_adc)
+{
+	return p_adc->ADC12B_SR;
+}
+
+/**
+ * \brief Adapt performance versus power consumption.
+ *
+ * \note Please refer to ADC Characteristics in the product datasheet
+ * for more details.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ * \param uc_ibctl ADC Bias current control.
+ */
+void adc12b_set_bias_current(Adc12b *p_adc, const uint8_t uc_ibctl)
+{
+	p_adc->ADC12B_ACR |= ADC12B_ACR_IBCTL(uc_ibctl);
+}
+
+/**
+ * \brief Get PDC registers base address.
+ *
+ * \param p_adc Pointer to an ADC instance.
+ *
+ * \return ADC PDC register base address.
+ */
+Pdc *adc12b_get_pdc_base(const Adc12b *p_adc)
+{
+	return PDC_ADC12B;
+}
+#endif // SAM3U_SERIES
+
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
diff --git a/hardware/digistump/sam/system/libsam/source/can.c b/hardware/digistump/sam/system/libsam/source/can.c
new file mode 100644
index 0000000..5fed79a
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/can.c
@@ -0,0 +1,804 @@
+/**
+ * \file
+ *
+ * \brief Controller Area Network (CAN) driver module for SAM.
+ *
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "../chip.h"
+#include 
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#if SAM3XA_SERIES
+
+
+/** Define the timemark mask. */
+#define TIMEMARK_MASK              0x0000ffff
+
+/* CAN timeout for synchronization. */
+#define CAN_TIMEOUT                100000
+
+/** The max value for CAN baudrate prescale. */
+#define CAN_BAUDRATE_MAX_DIV       128
+
+/** Define the scope for TQ. */
+#define CAN_MIN_TQ_NUM             8
+#define CAN_MAX_TQ_NUM             25
+
+/** Define the fixed bit time value. */
+#define CAN_BIT_SYNC               1
+#define CAN_BIT_IPT                2
+
+typedef struct {
+	uint8_t uc_tq;      //! CAN_BIT_SYNC + uc_prog + uc_phase1 + uc_phase2 = uc_tq, 8 <= uc_tq <= 25.
+	uint8_t uc_prog;    //! Propagation segment, (3-bits + 1), 1~8;
+	uint8_t uc_phase1;  //! Phase segment 1, (3-bits + 1), 1~8;
+	uint8_t uc_phase2;  //! Phase segment 2, (3-bits + 1), 1~8, CAN_BIT_IPT <= uc_phase2;
+	uint8_t uc_sjw;     //! Resynchronization jump width, (2-bits + 1), min(uc_phase1, 4);
+	uint8_t uc_sp;      //! Sample point value, 0~100 in percent.
+} can_bit_timing_t;
+
+/** Values of bit time register for different baudrates, Sample point = ((1 + uc_prog + uc_phase1) / uc_tq) * 100%. */
+const can_bit_timing_t can_bit_time[] = {
+	{8,   (2 + 1), (1 + 1), (1 + 1), (2 + 1), 75},
+	{9,   (1 + 1), (2 + 1), (2 + 1), (1 + 1), 67},
+	{10,  (2 + 1), (2 + 1), (2 + 1), (2 + 1), 70},
+	{11,  (3 + 1), (2 + 1), (2 + 1), (3 + 1), 72},
+	{12,  (2 + 1), (3 + 1), (3 + 1), (3 + 1), 67},
+	{13,  (3 + 1), (3 + 1), (3 + 1), (3 + 1), 77},
+	{14,  (3 + 1), (3 + 1), (4 + 1), (3 + 1), 64},
+	{15,  (3 + 1), (4 + 1), (4 + 1), (3 + 1), 67},
+	{16,  (4 + 1), (4 + 1), (4 + 1), (3 + 1), 69},
+	{17,  (5 + 1), (4 + 1), (4 + 1), (3 + 1), 71},
+	{18,  (4 + 1), (5 + 1), (5 + 1), (3 + 1), 67},
+	{19,  (5 + 1), (5 + 1), (5 + 1), (3 + 1), 68},
+	{20,  (6 + 1), (5 + 1), (5 + 1), (3 + 1), 70},
+	{21,  (7 + 1), (5 + 1), (5 + 1), (3 + 1), 71},
+	{22,  (6 + 1), (6 + 1), (6 + 1), (3 + 1), 68},
+	{23,  (7 + 1), (7 + 1), (6 + 1), (3 + 1), 70},
+	{24,  (6 + 1), (7 + 1), (7 + 1), (3 + 1), 67},
+	{25,  (7 + 1), (7 + 1), (7 + 1), (3 + 1), 68}
+};
+
+/**
+ * \brief Configure CAN baudrate.
+ *
+ * \param p_can       Pointer to a CAN peripheral instance.
+ * \param ul_mck      The input main clock for the CAN module.
+ * \param ul_baudrate Baudrate value (kB/s), allowed values:
+ *                    1000, 800, 500, 250, 125, 50, 25, 10, 5.
+ *
+ * \retval Set the baudrate successfully or not.
+ */
+static uint32_t can_set_baudrate(Can *p_can, uint32_t ul_mck, uint32_t ul_baudrate)
+{
+	uint8_t uc_tq;
+	uint8_t uc_prescale;
+	uint32_t ul_mod;
+	uint32_t ul_cur_mod;
+	can_bit_timing_t *p_bit_time;
+
+	/* Check whether the baudrate prescale will be greater than the max divide value. */
+	if (((ul_mck + (ul_baudrate * CAN_MAX_TQ_NUM * 1000 - 1)) /
+		(ul_baudrate * CAN_MAX_TQ_NUM * 1000)) > CAN_BAUDRATE_MAX_DIV) {
+		return 0;
+	}
+
+	/* Check whether the input MCK is too small. */
+	if (ul_mck  < ul_baudrate * CAN_MIN_TQ_NUM * 1000) {
+		return 0;
+	}
+
+	/* Initialize it as the minimum Time Quantum. */
+	uc_tq = CAN_MIN_TQ_NUM;
+
+	/* Initialize the remainder as the max value. When the remainder is 0, get the right TQ number. */
+	ul_mod = 0xffffffff;
+	/* Find out the approximate Time Quantum according to the baudrate. */
+	for (uint8_t i = CAN_MIN_TQ_NUM; i <= CAN_MAX_TQ_NUM; i++) {
+		if ((ul_mck / (ul_baudrate * i * 1000)) <= CAN_BAUDRATE_MAX_DIV) {
+			ul_cur_mod = ul_mck % (ul_baudrate * i * 1000);
+			if (ul_cur_mod < ul_mod){
+				ul_mod = ul_cur_mod;
+				uc_tq = i;
+				if (!ul_mod) {
+					break;
+				}
+			}
+		}
+	}
+
+	/* Calculate the baudrate prescale value. */
+	uc_prescale = ul_mck / (ul_baudrate * uc_tq * 1000);
+
+	/* Get the right CAN BIT Timing group. */
+	p_bit_time = (can_bit_timing_t *)&can_bit_time[uc_tq - CAN_MIN_TQ_NUM];
+
+	/* Before modifying the CANBR register, disable the CAN controller. */
+	can_disable(p_can);
+
+	/* Write into the CAN baudrate register. */
+	p_can->CAN_BR = CAN_BR_PHASE2(p_bit_time->uc_phase2 - 1) |
+					CAN_BR_PHASE1(p_bit_time->uc_phase1 - 1) |
+					CAN_BR_PROPAG(p_bit_time->uc_prog - 1) |
+					CAN_BR_SJW(p_bit_time->uc_sjw - 1) |
+					CAN_BR_BRP(uc_prescale - 1);
+	return 1;
+}
+
+
+/**
+ * \brief Initialize CAN controller.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ * \param ul_mck CAN module input clock.
+ * \param ul_baudrate CAN communication baudrate in kbs.
+ *
+ * \retval 0 If failed to initialize the CAN module; otherwise successful.
+ *
+ * \note PMC clock for CAN peripheral should be enabled before calling this function.
+ */
+uint32_t can_init(Can *p_can, uint32_t ul_mck, uint32_t ul_baudrate)
+{
+	uint32_t ul_flag;
+	uint32_t ul_tick;
+
+	/* Initialize the baudrate for CAN module. */
+	ul_flag = can_set_baudrate(p_can, ul_mck, ul_baudrate);
+	if (ul_flag == 0) {
+		return 0;
+	}
+
+	/* Reset the CAN eight message mailbox. */
+	can_reset_all_mailbox(p_can);
+
+	/* Enable the CAN controller. */
+	can_enable(p_can);
+
+	/* Wait until the CAN is synchronized with the bus activity. */
+	ul_flag = 0;
+	ul_tick = 0;
+	while (!(ul_flag & CAN_SR_WAKEUP) && (ul_tick < CAN_TIMEOUT)) {
+		ul_flag = can_get_status(p_can);
+		ul_tick++;
+	}
+
+	/* Timeout or the CAN module has been synchronized with the bus. */
+	if (CAN_TIMEOUT == ul_tick) {
+		return 0;
+	} else {
+		return 1;
+	}
+}
+
+/**
+ * \brief Enable CAN Controller.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_enable(Can *p_can)
+{
+	p_can->CAN_MR |= CAN_MR_CANEN;
+}
+
+/**
+ * \brief Disable CAN Controller.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_disable(Can *p_can)
+{
+	p_can->CAN_MR &= ~CAN_MR_CANEN;
+}
+
+/**
+ * \brief Disable CAN Controller low power mode.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_disable_low_power_mode(Can *p_can)
+{
+	p_can->CAN_MR &= ~CAN_MR_LPM;
+}
+
+/**
+ * \brief Enable CAN Controller low power mode.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_enable_low_power_mode(Can *p_can)
+{
+	p_can->CAN_MR |= CAN_MR_LPM;
+}
+
+/**
+ * \brief Disable CAN Controller autobaud/listen mode.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_disable_autobaud_listen_mode(Can *p_can)
+{
+	p_can->CAN_MR &= ~CAN_MR_ABM;
+}
+
+/**
+ * \brief Enable CAN Controller autobaud/listen mode.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_enable_autobaud_listen_mode(Can *p_can)
+{
+	p_can->CAN_MR |= CAN_MR_ABM;
+}
+
+/**
+ * \brief CAN Controller won't generate overload frame.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_disable_overload_frame(Can *p_can)
+{
+	p_can->CAN_MR &= ~CAN_MR_OVL;
+}
+
+/**
+ * \brief CAN Controller will generate an overload frame after each successful
+ * reception for mailboxes configured in Receive mode, Producer and Consumer.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_enable_overload_frame(Can *p_can)
+{
+	p_can->CAN_MR |= CAN_MR_OVL;
+}
+
+/**
+ * \brief Configure the timestamp capture point, at the start or the end of frame.
+ *
+ * \param p_can   Pointer to a CAN peripheral instance.
+ * \param ul_flag 0: Timestamp is captured at each start of frame;
+ *                1: Timestamp is captured at each end of frame.
+ */
+void can_set_timestamp_capture_point(Can *p_can, uint32_t ul_flag)
+{
+	if (ul_flag) {
+		p_can->CAN_MR |= CAN_MR_TEOF;
+	} else {
+		p_can->CAN_MR &= ~CAN_MR_TEOF;
+	}
+}
+
+/**
+ * \brief Disable CAN Controller time triggered mode.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_disable_time_triggered_mode(Can *p_can)
+{
+	p_can->CAN_MR &= ~CAN_MR_TTM;
+}
+
+/**
+ * \brief Enable CAN Controller time triggered mode.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_enable_time_triggered_mode(Can *p_can)
+{
+	p_can->CAN_MR |= CAN_MR_TTM;
+}
+
+/**
+ * \brief Disable CAN Controller timer freeze.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_disable_timer_freeze(Can *p_can)
+{
+	p_can->CAN_MR &= ~CAN_MR_TIMFRZ;
+}
+
+/**
+ * \brief Enable CAN Controller timer freeze.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_enable_timer_freeze(Can *p_can)
+{
+	p_can->CAN_MR |= CAN_MR_TIMFRZ;
+}
+
+/**
+ * \brief Disable CAN Controller transmit repeat function.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_disable_tx_repeat(Can *p_can)
+{
+	p_can->CAN_MR |= CAN_MR_DRPT;
+}
+
+/**
+ * \brief Enable CAN Controller transmit repeat function.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ */
+void can_enable_tx_repeat(Can *p_can)
+{
+	p_can->CAN_MR &= ~CAN_MR_DRPT;
+}
+
+/**
+ * \brief Configure CAN Controller reception synchronization stage.
+ *
+ * \param p_can    Pointer to a CAN peripheral instance.
+ * \param ul_stage The reception stage to be configured.
+ *
+ * \note This is just for debug purpose only.
+ */
+void can_set_rx_sync_stage(Can *p_can, uint32_t ul_stage)
+{
+	p_can->CAN_MR = (p_can->CAN_MR & ~CAN_MR_RXSYNC_Msk) | ul_stage;
+}
+
+/**
+ * \brief Enable CAN interrupt.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ * \param dw_mask Interrupt to be enabled.
+ */
+void can_enable_interrupt(Can *p_can, uint32_t dw_mask)
+{
+	p_can->CAN_IER = dw_mask;
+}
+
+/**
+ * \brief Disable CAN interrupt.
+ *
+ * \param p_can  Pointer to a CAN peripheral instance.
+ * \param dw_mask Interrupt to be disabled.
+ */
+void can_disable_interrupt(Can *p_can, uint32_t dw_mask)
+{
+	p_can->CAN_IDR = dw_mask;
+}
+
+/**
+ * \brief Get CAN Interrupt Mask.
+ *
+ * \param p_can Pointer to a CAN peripheral instance.
+ *
+ * \retval CAN interrupt mask.
+ */
+uint32_t can_get_interrupt_mask(Can *p_can)
+{
+	return (p_can->CAN_IMR);
+}
+
+/**
+ * \brief Get CAN status.
+ *
+ * \param p_can Pointer to a CAN peripheral instance.
+ *
+ * \retval CAN status.
+ */
+uint32_t can_get_status(Can *p_can)
+{
+	return (p_can->CAN_SR);
+}
+
+/**
+ * \brief Get the 16-bit free-running internal timer count.
+ *
+ * \param p_can Pointer to a CAN peripheral instance.
+ *
+ * \retval The internal CAN free-running timer counter.
+ */
+uint32_t can_get_internal_timer_value(Can *p_can)
+{
+	return (p_can->CAN_TIM);
+}
+
+/**
+ * \brief Get CAN timestamp register value.
+ *
+ * \param p_can Pointer to a CAN peripheral instance.
+ *
+ * \retval The timestamp value.
+ */
+uint32_t can_get_timestamp_value(Can *p_can)
+{
+	return (p_can->CAN_TIMESTP);
+}
+
+/**
+ * \brief Get CAN transmit error counter.
+ *
+ * \param p_can Pointer to a CAN peripheral instance.
+ *
+ * \retval Transmit error counter.
+ */
+uint8_t can_get_tx_error_cnt(Can *p_can)
+{
+	return (uint8_t) (p_can->CAN_ECR >> CAN_ECR_TEC_Pos);
+}
+
+/**
+ * \brief Get CAN receive error counter.
+ *
+ * \param p_can Pointer to a CAN peripheral instance.
+ *
+ * \retval Receive error counter.
+ */
+uint8_t can_get_rx_error_cnt(Can *p_can)
+{
+	return (uint8_t) (p_can->CAN_ECR >> CAN_ECR_REC_Pos);
+}
+
+/**
+ * \brief Reset the internal free-running 16-bit timer.
+ *
+ * \param p_can Pointer to a CAN peripheral instance.
+ *
+ * \note If the internal timer counter is frozen, this function automatically
+ * re-enables it.
+ */
+void can_reset_internal_timer(Can *p_can)
+{
+	p_can->CAN_TCR |= CAN_TCR_TIMRST;
+}
+
+/**
+ * \brief Send global transfer request.
+ *
+ * \param p_can   Pointer to a CAN peripheral instance.
+ * \param uc_mask Mask for mailboxes that are requested to transfer.
+ */
+void can_global_send_transfer_cmd(Can *p_can, uint8_t uc_mask)
+{
+	uint32_t ul_reg;
+
+	ul_reg = p_can->CAN_TCR & ((uint32_t)~GLOBAL_MAILBOX_MASK);
+	p_can->CAN_TCR = ul_reg | uc_mask;
+}
+
+/**
+ * \brief Send global abort request.
+ *
+ * \param p_can   Pointer to a CAN peripheral instance.
+ * \param uc_mask Mask for mailboxes that are requested to abort.
+ */
+void can_global_send_abort_cmd(Can *p_can, uint8_t uc_mask)
+{
+	uint32_t ul_reg;
+
+	ul_reg = p_can->CAN_ACR & ((uint32_t)~GLOBAL_MAILBOX_MASK);
+	p_can->CAN_ACR = ul_reg | uc_mask;
+}
+
+/**
+ * \brief Configure the timemark for the mailbox.
+ *
+ * \param p_can    Pointer to a CAN peripheral instance.
+ * \param uc_index Indicate which mailbox is to be configured.
+ * \param us_cnt   The timemark to be set.
+ *
+ * \note The timemark is active in Time Triggered mode only.
+ */
+void can_mailbox_set_timemark(Can *p_can, uint8_t uc_index, uint16_t us_cnt)
+{
+	uint32_t ul_reg;
+
+	ul_reg = p_can->CAN_MB[uc_index].CAN_MMR & ((uint32_t)~TIMEMARK_MASK);
+	p_can->CAN_MB[uc_index].CAN_MMR = ul_reg | us_cnt;
+}
+
+/**
+ * \brief Get status of the mailbox.
+ *
+ * \param p_can    Pointer to a CAN peripheral instance.
+ * \param uc_index Indicate which mailbox is to be read.
+ *
+ * \retval The mailbox status.
+ */
+uint32_t can_mailbox_get_status(Can *p_can, uint8_t uc_index)
+{
+	return (p_can->CAN_MB[uc_index].CAN_MSR);
+}
+
+/**
+ * \brief Send single mailbox transfer request.
+ *
+ * \param p_can   Pointer to a CAN peripheral instance.
+ * \param uc_index Indicate which mailbox is to be configured.
+ */
+void can_mailbox_send_transfer_cmd(Can *p_can, uint8_t uc_index)
+{
+	p_can->CAN_MB[uc_index].CAN_MCR |= CAN_MCR_MTCR;
+}
+
+/**
+ * \brief Send single mailbox abort request.
+ *
+ * \param p_can    Pointer to a CAN peripheral instance.
+ * \param uc_index Indicate which mailbox is to be configured.
+ */
+void can_mailbox_send_abort_cmd(Can *p_can, uint8_t uc_index)
+{
+	p_can->CAN_MB[uc_index].CAN_MCR |= CAN_MCR_MACR;
+}
+
+/**
+ * \brief Initialize the mailbox in different mode and set up related configuration.
+ *
+ * \param p_can    Pointer to a CAN peripheral instance.
+ * \param p_mailbox Pointer to a CAN mailbox instance.
+ */
+void can_mailbox_init(Can *p_can, can_mb_conf_t *p_mailbox)
+{
+	uint8_t uc_index;
+
+	uc_index = (uint8_t)p_mailbox->ul_mb_idx;
+	/* Check the object type of the mailbox. If it's used to disable the mailbox, reset the whole mailbox. */
+	if (!p_mailbox->uc_obj_type) {
+		p_can->CAN_MB[uc_index].CAN_MMR = 0;
+		p_can->CAN_MB[uc_index].CAN_MAM = 0;
+		p_can->CAN_MB[uc_index].CAN_MID = 0;
+		p_can->CAN_MB[uc_index].CAN_MDL = 0;
+		p_can->CAN_MB[uc_index].CAN_MDH = 0;
+		p_can->CAN_MB[uc_index].CAN_MCR = 0;
+		return;
+	}
+
+	/* Set the priority in Transmit mode. */
+	p_can->CAN_MB[uc_index].CAN_MMR = (p_can->CAN_MB[uc_index].CAN_MMR &
+		~CAN_MMR_PRIOR_Msk) | (p_mailbox-> uc_tx_prio << CAN_MMR_PRIOR_Pos);
+
+	/* Set the message ID and message acceptance mask for the mailbox in other modes. */
+	if (p_mailbox->uc_id_ver) {
+		p_can->CAN_MB[uc_index].CAN_MAM = p_mailbox->ul_id_msk | CAN_MAM_MIDE;
+		p_can->CAN_MB[uc_index].CAN_MID = p_mailbox->ul_id | CAN_MAM_MIDE;
+	} else {
+		p_can->CAN_MB[uc_index].CAN_MAM = p_mailbox->ul_id_msk;
+		p_can->CAN_MB[uc_index].CAN_MID = p_mailbox->ul_id;
+	}
+
+	/* Set up mailbox in one of the five different modes. */
+	p_can->CAN_MB[uc_index].CAN_MMR = (p_can->CAN_MB[uc_index].CAN_MMR &
+		~CAN_MMR_MOT_Msk) | (p_mailbox-> uc_obj_type << CAN_MMR_MOT_Pos);
+}
+
+/**
+ * \brief Read receive information for the mailbox.
+ *
+ * \param p_can     Pointer to a CAN peripheral instance.
+ * \param p_mailbox Pointer to a CAN mailbox instance.
+ *
+ * \retval Different CAN mailbox transfer status.
+ *
+ * \note Read the mailbox status before calling this function.
+ */
+uint32_t can_mailbox_read(Can *p_can, can_mb_conf_t *p_mailbox)
+{
+	uint32_t ul_status;
+	uint8_t uc_index;
+	uint32_t ul_retval;
+
+	ul_retval = 0;
+	uc_index = (uint8_t)p_mailbox->ul_mb_idx;
+	ul_status = p_mailbox->ul_status;
+
+	/* Check whether there is overwriting happening in Receive with Overwrite mode,
+	   or there're messages lost in Receive mode. */
+	if ((ul_status & CAN_MSR_MRDY) && (ul_status & CAN_MSR_MMI)) {
+		ul_retval = CAN_MAILBOX_RX_OVER;
+	}
+
+	/* Read the message family ID. */
+	p_mailbox->ul_fid = p_can->CAN_MB[uc_index].CAN_MFID & CAN_MFID_MFID_Msk;
+
+	/* Read received data length. */
+	p_mailbox->uc_length = (ul_status & CAN_MSR_MDLC_Msk) >> CAN_MSR_MDLC_Pos;
+
+	/* Read received data. */
+	p_mailbox->ul_datal = p_can->CAN_MB[uc_index].CAN_MDL;
+	if (p_mailbox->uc_length > 4) {
+		p_mailbox->ul_datah = p_can->CAN_MB[uc_index].CAN_MDH;
+	}
+
+	/* Read the mailbox status again to check whether the software needs to re-read mailbox data register. */
+	p_mailbox->ul_status = p_can->CAN_MB[uc_index].CAN_MSR;
+	ul_status = p_mailbox->ul_status;
+	if (ul_status & CAN_MSR_MMI) {
+		ul_retval |= CAN_MAILBOX_RX_NEED_RD_AGAIN;
+	} else {
+		ul_retval |= CAN_MAILBOX_TRANSFER_OK;
+	}
+
+	/* Enable next receive process. */
+	can_mailbox_send_transfer_cmd(p_can, uc_index);
+
+	return ul_retval;
+}
+
+/**
+ * \brief Prepare transmit information and write them into the mailbox.
+ *
+ * \param p_can     Pointer to a CAN peripheral instance.
+ * \param p_mailbox Pointer to a CAN mailbox instance.
+ *
+ * \retval CAN_MAILBOX_NOT_READY: Failed because mailbox isn't ready.
+ *       CAN_MAILBOX_TRANSFER_OK: Successfully write message into mailbox.
+ *
+ * \note After calling this function, the mailbox message won't be sent out until
+ * can_mailbox_send_transfer_cmd() is called.
+ */
+uint32_t can_mailbox_write(Can *p_can, can_mb_conf_t *p_mailbox)
+{
+	uint32_t ul_status;
+	uint8_t uc_index;
+
+	uc_index = (uint8_t)p_mailbox->ul_mb_idx;
+	/* Read the mailbox status firstly to check whether the mailbox is ready or not. */
+	p_mailbox->ul_status = can_mailbox_get_status(p_can, uc_index);
+	ul_status = p_mailbox->ul_status;
+	if (!(ul_status & CAN_MSR_MRDY)) {
+		return CAN_MAILBOX_NOT_READY;
+	}
+
+	/* Write transmit identifier. */
+	if (p_mailbox->uc_id_ver) {
+		p_can->CAN_MB[uc_index].CAN_MID = p_mailbox->ul_id | CAN_MAM_MIDE;
+	} else {
+		p_can->CAN_MB[uc_index].CAN_MID = p_mailbox->ul_id;
+	}
+
+	/* Write transmit data into mailbox data register. */
+	p_can->CAN_MB[uc_index].CAN_MDL = p_mailbox->ul_datal;
+	if (p_mailbox->uc_length > 4) {
+		p_can->CAN_MB[uc_index].CAN_MDH = p_mailbox->ul_datah;
+	}
+
+	/* Write transmit data length into mailbox control register. */
+	p_can->CAN_MB[uc_index].CAN_MCR = (p_can->CAN_MB[uc_index].CAN_MCR &
+			~CAN_MCR_MDLC_Msk) | CAN_MCR_MDLC(p_mailbox->uc_length);
+
+	return CAN_MAILBOX_TRANSFER_OK;
+}
+
+/**
+ * \brief Require to send out a remote frame.
+ *
+ * \param p_can    Pointer to a CAN peripheral instance.
+ * \param p_mailbox Pointer to a CAN mailbox instance.
+ *
+ * \retval CAN_MAILBOX_NOT_READY: Failed because mailbox isn't ready for transmitting message.
+ *       CAN_MAILBOX_TRANSFER_OK: Successfully send out a remote frame.
+ */
+uint32_t can_mailbox_tx_remote_frame(Can *p_can, can_mb_conf_t *p_mailbox)
+{
+	uint32_t ul_status;
+	uint8_t uc_index;
+
+	uc_index = (uint8_t)p_mailbox->ul_mb_idx;
+	/* Read the mailbox status firstly to check whether the mailbox is ready or not. */
+	p_mailbox->ul_status = p_can->CAN_MB[uc_index].CAN_MSR;
+	ul_status = p_mailbox->ul_status;
+	if (!(ul_status & CAN_MSR_MRDY)) {
+		return CAN_MAILBOX_NOT_READY;
+	}
+
+	/* Write transmit identifier. */
+	if (p_mailbox->uc_id_ver) {
+		p_can->CAN_MB[uc_index].CAN_MID = p_mailbox->ul_id | CAN_MAM_MIDE;
+	} else {
+		p_can->CAN_MB[uc_index].CAN_MID = p_mailbox->ul_id;
+	}
+
+	/* Set the RTR bit in the sent frame. */
+	p_can->CAN_MB[uc_index].CAN_MCR |= CAN_MCR_MRTR;
+
+	/* Set the MBx bit in the Transfer Command Register to send out the remote frame. */
+	can_global_send_transfer_cmd(p_can, (1 << uc_index));
+
+	return CAN_MAILBOX_TRANSFER_OK;
+}
+
+/**
+ * \brief Reset the eight mailboxes.
+ *
+ * \param p_can Pointer to a CAN peripheral instance.
+ */
+void can_reset_all_mailbox(Can *p_can)
+{
+	can_mb_conf_t mb_config_t;
+
+	/* Set the mailbox object type parameter to disable the mailbox. */
+	mb_config_t.uc_obj_type = CAN_MB_DISABLE_MODE;
+
+	for (uint8_t i = 0; i < CANMB_NUMBER; i++) {
+		mb_config_t.ul_mb_idx = i;
+		can_mailbox_init(p_can, &mb_config_t);
+	}
+}
+
+// from wilfredo
+uint32_t can_reset_mailbox_data(can_mb_conf_t *p_mailbox)
+{
+   if ( p_mailbox == NULL )
+   {
+     return 1U ;
+   }
+
+#if 0
+	p_mailbox->ul_mb_idx = 0;
+	p_mailbox->uc_obj_type = 0;
+	p_mailbox->uc_id_ver = 0;
+	p_mailbox->uc_length = 0;
+	p_mailbox->uc_tx_prio = 0;
+	p_mailbox->ul_status = 0;
+	p_mailbox->ul_id_msk = 0;
+	p_mailbox->ul_id = 0;
+	p_mailbox->ul_fid = 0;
+	p_mailbox->ul_datal = 0;
+	p_mailbox->ul_datah = 0;
+#else
+  memset( p_mailbox, 0, sizeof( can_mb_conf_t ) ) ;
+#endif
+
+  return 0U ;
+}
+
+#endif // SAM3XA_SERIES
+
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
diff --git a/hardware/digistump/sam/system/libsam/source/dacc.c b/hardware/digistump/sam/system/libsam/source/dacc.c
new file mode 100644
index 0000000..0637909
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/dacc.c
@@ -0,0 +1,486 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#if (SAM3XA_SERIES) || (SAM3N_SERIES) || (SAM3S_SERIES)
+
+/**
+ * \defgroup sam_drivers_dacc_group Digital-to-Analog Converter Controller (DACC)
+ *
+ * \par Purpose
+ *
+ * Driver for the Digital-to-Analog Converter Controller. It provides access to the main
+ * features of the DAC controller.
+ *
+ * \par Usage
+ *
+ * -# DACC clock should be enabled before using it.
+ *    - \ref pmc_enable_periph_clk() can be used to enable the clock.
+ * -# Reset DACC with \ref dacc_reset().
+ * -# If DACC can be enabled/disabled, uses \ref dacc_enable() and
+ *    \ref dacc_disable().
+ * -# Initialize DACC timing with \ref dacc_set_timing() (different DAC
+ *    peripheral may require different parameters).
+ * -# Write conversion data with \ref dacc_write_conversion_data().
+ * -# Configure trigger with \ref dacc_set_trigger()
+ *    and \ref dacc_disable_trigger().
+ * -# Configure FIFO transfer mode with \ref dacc_set_transfer_mode().
+ * -# Control interrupts with \ref dacc_enable_interrupt(),
+ *    \ref dacc_disable_interrupt(), \ref dacc_get_interrupt_mask() and
+ *    \ref dacc_get_interrupt_status().
+ * -# DACC registers support write protect with \ref dacc_set_writeprotect()
+ *    and \ref dacc_get_writeprotect_status().
+ * -# If the DACC can work with PDC, use \ref dacc_get_pdc_base() to get
+ *    PDC register base for the DAC controller.
+ * -# If the DACC has several channels to process, the following functions can
+ *    be used:
+ *    - Enable/Disable TAG and select output channel selection by
+ *      \ref dacc_set_channel_selection(),
+ *      \ref dacc_enable_flexible_channel_selection().
+ *    - Enable/disable channel by \ref dacc_enable_channel() /
+ *      \ref dacc_disable_channel(), get channel status by
+ *      \ref dacc_get_channel_status().
+ *
+ * \section dependencies Dependencies
+ * This driver does not depend on other modules.
+ *
+ * @{
+ */
+
+//! Max channel number
+#if (SAM3N_SERIES)
+# define MAX_CH_NB        0
+#else
+# define MAX_CH_NB        1
+#endif
+
+//! DACC Write Protect Key "DAC" in ASCII
+#define DACC_WP_KEY     (0x444143)
+
+/**
+ * \brief Reset DACC.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ */
+void dacc_reset(Dacc *p_dacc)
+{
+	p_dacc->DACC_CR = DACC_CR_SWRST;
+}
+
+/**
+ * \brief Enable trigger and set the trigger source.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ * \param ul_trigger Trigger source number.
+ *
+ * \return \ref DACC_RC_OK for OK.
+ */
+uint32_t dacc_set_trigger(Dacc *p_dacc, uint32_t ul_trigger)
+{
+	uint32_t mr = p_dacc->DACC_MR & (~(DACC_MR_TRGSEL_Msk));
+#if (SAM3N_SERIES)
+	p_dacc->DACC_MR = mr
+		| DACC_MR_TRGEN
+		| ((ul_trigger << DACC_MR_TRGSEL_Pos) & DACC_MR_TRGSEL_Msk);
+#else
+	p_dacc->DACC_MR = mr | DACC_MR_TRGEN_EN | DACC_MR_TRGSEL(ul_trigger);
+#endif
+	return DACC_RC_OK;
+}
+
+/**
+ * \brief Disable trigger (free run mode).
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ */
+void dacc_disable_trigger(Dacc *p_dacc)
+{
+	p_dacc->DACC_MR &= ~DACC_MR_TRGEN;
+}
+
+/**
+ * \brief Set the transfer mode.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ * \param ul_mode Transfer mode configuration.
+ *
+ * \return \ref DACC_RC_OK for OK.
+ */
+uint32_t dacc_set_transfer_mode(Dacc *p_dacc, uint32_t ul_mode)
+{
+	if (ul_mode) {
+#if (SAM3N_SERIES)
+		p_dacc->DACC_MR |= DACC_MR_WORD;
+#else
+		p_dacc->DACC_MR |= DACC_MR_WORD_WORD;
+#endif
+	} else {
+#if (SAM3N_SERIES)
+		p_dacc->DACC_MR &= (~DACC_MR_WORD);
+#else
+		p_dacc->DACC_MR &= (~DACC_MR_WORD_WORD);
+#endif
+	}
+	return DACC_RC_OK;
+}
+
+/**
+ * \brief Enable DACC interrupts.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ * \param ul_interrupt_mask The interrupt mask.
+ */
+void dacc_enable_interrupt(Dacc *p_dacc, uint32_t ul_interrupt_mask)
+{
+	p_dacc->DACC_IER = ul_interrupt_mask;
+}
+
+/**
+ * \brief Disable DACC interrupts.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ * \param ul_interrupt_mask The interrupt mask.
+ */
+void dacc_disable_interrupt(Dacc *p_dacc, uint32_t ul_interrupt_mask)
+{
+	p_dacc->DACC_IDR = ul_interrupt_mask;
+}
+
+/**
+ * \brief Get the interrupt mask.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ *
+ * \return The interrupt mask.
+ */
+uint32_t dacc_get_interrupt_mask(Dacc *p_dacc)
+{
+	return p_dacc->DACC_IMR;
+}
+
+/**
+ * \brief Get the interrupt status.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ *
+ * \return The interrupt status.
+ */
+uint32_t dacc_get_interrupt_status(Dacc *p_dacc)
+{
+	return p_dacc->DACC_ISR;
+}
+
+/**
+ * \brief Write data to conversion register.
+ *
+ * \note The \a ul_data could be output data or data with channel TAG when
+ * flexible mode is used.
+ *
+ * In flexible mode the 2 bits, DACC_CDR[13:12] which are otherwise unused,
+ * are employed to select the channel in the same way as with the USER_SEL
+ * field. Finally, if the WORD field is set, the 2 bits, DACC_CDR[13:12] are
+ * used for channel selection of the first data and the 2 bits,
+ * DACC_CDR[29:28] for channel selection of the second data.
+ *
+ * \see dacc_enable_flexible_selection()
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ * \param ul_data The data to be transferred to analog value.
+ */
+void dacc_write_conversion_data(Dacc *p_dacc, uint32_t ul_data)
+{
+	p_dacc->DACC_CDR = ul_data;
+}
+
+/**
+ * \brief Enable or disable write protect of DACC registers.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ * \param ul_enable 1 to enable, 0 to disable.
+ */
+void dacc_set_writeprotect(Dacc *p_dacc, uint32_t ul_enable)
+{
+	if (ul_enable) {
+		p_dacc->DACC_WPMR = DACC_WPMR_WPKEY(DACC_WP_KEY)
+			          | DACC_WPMR_WPEN;
+	} else {
+		p_dacc->DACC_WPMR = DACC_WPMR_WPKEY(DACC_WP_KEY);
+	}
+}
+
+/**
+ * \brief Get the write protect status.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ *
+ * \return Write protect status.
+ */
+uint32_t dacc_get_writeprotect_status(Dacc *p_dacc)
+{
+	return p_dacc->DACC_WPSR;
+}
+
+/**
+ * \brief Get PDC registers base address.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ *
+ * \return DACC PDC register base address.
+ */
+Pdc *dacc_get_pdc_base(Dacc *p_dacc)
+{
+	p_dacc = p_dacc;
+	return PDC_DACC;
+}
+
+#if (SAM3N_SERIES) || defined(__DOXYGEN__)
+/**
+ * \brief Enable DACC.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ */
+void dacc_enable(Dacc *p_dacc)
+{
+	p_dacc->DACC_MR |= DACC_MR_DACEN;
+}
+
+/**
+ * \brief Disable DACC.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ *
+ * \return \ref DACC_RC_OK for OK.
+ */
+void dacc_disable(Dacc *p_dacc)
+{
+	p_dacc->DACC_MR &= (~DACC_MR_DACEN);
+}
+
+/**
+ * \brief Set the DACC timing.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ * \param ul_startup Startup time selection.
+ * \param ul_clock_divider Clock divider for internal trigger.
+ *
+ * \return \ref DACC_RC_OK for OK.
+ */
+uint32_t dacc_set_timing(Dacc *p_dacc, uint32_t ul_startup,
+		uint32_t ul_clock_divider)
+{
+	uint32_t mr = p_dacc->DACC_MR
+		& ~(DACC_MR_STARTUP_Msk | DACC_MR_CLKDIV_Msk);
+	p_dacc->DACC_MR = mr | DACC_MR_STARTUP(ul_startup)
+		| DACC_MR_CLKDIV(ul_clock_divider);
+	return DACC_RC_OK;
+}
+#endif /* #if (SAM3N_SERIES) */
+
+#if (SAM3S_SERIES) || (SAM3XA_SERIES) || (SAM4S_SERIES) || defined(__DOXYGEN__)
+/**
+ * \brief Disable flexible (TAG) mode and select a channel for DAC outputs.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ * \param ul_channel Channel to select.
+ *
+ * \return \ref DACC_RC_OK if successful.
+ */
+uint32_t dacc_set_channel_selection(Dacc *p_dacc, uint32_t ul_channel)
+{
+	uint32_t mr = p_dacc->DACC_MR & (~DACC_MR_USER_SEL_Msk);
+	if (ul_channel > MAX_CH_NB) {
+		return DACC_RC_INVALID_PARAM;
+	}
+	mr &= ~(DACC_MR_TAG);
+	mr |= ul_channel << DACC_MR_USER_SEL_Pos;
+	p_dacc->DACC_MR = mr;
+	return DACC_RC_OK;
+}
+
+/**
+ * \brief Enable the flexible channel selection mode (TAG).
+ *
+ * In this mode the 2 bits, DACC_CDR[13:12] which are otherwise unused, are
+ * employed to select the channel in the same way as with the USER_SEL field.
+ * Finally, if the WORD field is set, the 2 bits, DACC_CDR[13:12] are used
+ * for channel selection of the first data and the 2 bits, DACC_CDR[29:28]
+ * for channel selection of the second data.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ */
+void dacc_enable_flexible_selection(Dacc *p_dacc)
+{
+	p_dacc->DACC_MR |= DACC_MR_TAG;
+}
+
+/**
+ * \brief Set the power save mode.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ * \param ul_sleep_mode Sleep mode configuration.
+ * \param ul_fast_wakeup_mode Fast wakeup mode configuration.
+ *
+ * \return \ref DACC_RC_OK if successful.
+ */
+uint32_t dacc_set_power_save(Dacc *p_dacc,
+		uint32_t ul_sleep_mode, uint32_t ul_fast_wakeup_mode)
+{
+	if (ul_sleep_mode) {
+		p_dacc->DACC_MR |= DACC_MR_SLEEP;
+	} else {
+		p_dacc->DACC_MR &= (~DACC_MR_SLEEP);
+	}
+	if (ul_fast_wakeup_mode) {
+		p_dacc->DACC_MR |= DACC_MR_FASTWKUP;
+	} else {
+		p_dacc->DACC_MR &= (~DACC_MR_FASTWKUP);
+	}
+	return DACC_RC_OK;
+}
+
+/**
+ * \brief Set DACC timings.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ * \param ul_refresh Refresh period setting value.
+ * \param ul_maxs Max speed mode configuration.
+ * \param ul_startup Startup time selection.
+ *
+ * \return \ref DACC_RC_OK for OK.
+ */
+uint32_t dacc_set_timing(Dacc *p_dacc,
+		uint32_t ul_refresh, uint32_t ul_maxs, uint32_t ul_startup)
+{
+	uint32_t mr = p_dacc->DACC_MR
+		& (~(DACC_MR_REFRESH_Msk | DACC_MR_STARTUP_Msk));
+	mr |= DACC_MR_REFRESH(ul_refresh);
+	if (ul_maxs) {
+		mr |= DACC_MR_MAXS;
+	} else {
+		mr &= ~DACC_MR_MAXS;
+	}
+	mr |= (DACC_MR_STARTUP_Msk & ((ul_startup) << DACC_MR_STARTUP_Pos));
+	p_dacc->DACC_MR = mr;
+	return DACC_RC_OK;
+}
+
+/**
+ * \brief Enable DACC channel.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ * \param ul_channel The output channel to enable.
+ *
+ * \return \ref DACC_RC_OK for OK.
+ */
+uint32_t dacc_enable_channel(Dacc *p_dacc, uint32_t ul_channel)
+{
+	if (ul_channel > MAX_CH_NB)
+		return DACC_RC_INVALID_PARAM;
+
+	p_dacc->DACC_CHER = DACC_CHER_CH0 << ul_channel;
+	return DACC_RC_OK;
+}
+
+/**
+ * \brief Disable DACC channel.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ * \param ul_channel The output channel to disable.
+ *
+ * \return \ref DACC_RC_OK for OK.
+ */
+uint32_t dacc_disable_channel(Dacc *p_dacc, uint32_t ul_channel)
+{
+	if (ul_channel > MAX_CH_NB) {
+		return DACC_RC_INVALID_PARAM;
+	}
+	p_dacc->DACC_CHDR = DACC_CHDR_CH0 << ul_channel;
+	return DACC_RC_OK;
+}
+
+/**
+ * \brief Get the channel status.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ *
+ * \return DACC channel status.
+ */
+uint32_t dacc_get_channel_status(Dacc *p_dacc)
+{
+	return p_dacc->DACC_CHSR;
+}
+
+/**
+ * \brief Set the analog control value.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ * \param ul_analog_control Analog control configuration.
+ *
+ * \return \ref DACC_RC_OK for OK.
+ */
+uint32_t dacc_set_analog_control(Dacc *p_dacc, uint32_t ul_analog_control)
+{
+	p_dacc->DACC_ACR = ul_analog_control;
+	return DACC_RC_OK;
+}
+
+/**
+ * \brief Get the analog control value.
+ *
+ * \param p_dacc Pointer to a DACC instance.
+ *
+ * \return Current setting of analog control.
+ */
+uint32_t dacc_get_analog_control(Dacc *p_dacc)
+{
+	return p_dacc->DACC_ACR;
+}
+#endif /* (SAM3S_SERIES) || (SAM3XA_SERIES) */
+
+//@}
+
+#endif // SAM3XA_SERIES
+
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
diff --git a/hardware/digistump/sam/system/libsam/source/efc.c b/hardware/digistump/sam/system/libsam/source/efc.c
new file mode 100644
index 0000000..364926f
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/efc.c
@@ -0,0 +1,402 @@
+/**
+ * \file
+ *
+ * \brief Enhanced Embedded Flash Controller (EEFC) driver for SAM.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "../chip.h"
+#include 
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/**
+ * \defgroup sam_drivers_efc_group Enhanced Embedded Flash Controller (EEFC)
+ *
+ * The Enhanced Embedded Flash Controller ensures the interface of the Flash block with
+ * the 32-bit internal bus.
+ *
+ * @{
+ */
+
+/* Address definition for read operation */
+#if (SAM3XA_SERIES || SAM3U_SERIES /*|| SAM4SD16 || SAM4SD32*/)
+# define READ_BUFF_ADDR0    IFLASH0_ADDR
+# define READ_BUFF_ADDR1    IFLASH1_ADDR
+#elif (SAM3S_SERIES || SAM3N_SERIES)
+# define READ_BUFF_ADDR     IFLASH_ADDR
+#elif (SAM3U_SERIES || SAM4S_SERIES)
+# define READ_BUFF_ADDR     IFLASH0_ADDR
+#else
+# warning Only reading unique id for sam3 is implemented.
+#endif
+
+/* Flash Writing Protection Key */
+#define FWP_KEY    0x5Au
+
+#if SAM4S_SERIES
+#define EEFC_FCR_FCMD(value) \
+    ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
+#define EEFC_ERROR_FLAGS  (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR)
+#else
+#define EEFC_ERROR_FLAGS  (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE)
+#endif
+
+
+
+/*
+ * Local function declaration.
+ * Because they are RAM functions, they need 'extern' declaration.
+ */
+extern void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr);
+extern uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr);
+
+/**
+ * \brief Initialize the EFC controller.
+ *
+ * \param ul_access_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit.
+ * \param ul_fws The number of wait states in cycle (no shift).
+ *
+ * \return 0 if successful.
+ */
+uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws)
+{
+	efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws));
+	return EFC_RC_OK;
+}
+
+/**
+ * \brief Enable the flash ready interrupt.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ */
+void efc_enable_frdy_interrupt(Efc *p_efc)
+{
+	uint32_t ul_fmr = p_efc->EEFC_FMR;
+
+	efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FRDY);
+}
+
+/**
+ * \brief Disable the flash ready interrupt.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ */
+void efc_disable_frdy_interrupt(Efc *p_efc)
+{
+	uint32_t ul_fmr = p_efc->EEFC_FMR;
+
+	efc_write_fmr(p_efc, ul_fmr & (~EEFC_FMR_FRDY));
+}
+
+/**
+ * \brief Set flash access mode.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ * \param ul_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit.
+ */
+void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode)
+{
+	uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FAM);
+
+	efc_write_fmr(p_efc, ul_fmr | ul_mode);
+}
+
+/**
+ * \brief Get flash access mode.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ *
+ * \return 0 for 128-bit or EEFC_FMR_FAM for 64-bit.
+ */
+uint32_t efc_get_flash_access_mode(Efc *p_efc)
+{
+	return (p_efc->EEFC_FMR & EEFC_FMR_FAM);
+}
+
+/**
+ * \brief Set flash wait state.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ * \param ul_fws The number of wait states in cycle (no shift).
+ */
+void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws)
+{
+	uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FWS_Msk);
+
+	efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FWS(ul_fws));
+}
+
+/**
+ * \brief Get flash wait state.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ *
+ * \return The number of wait states in cycle (no shift).
+ */
+uint32_t efc_get_wait_state(Efc *p_efc)
+{
+	return ((p_efc->EEFC_FMR & EEFC_FMR_FWS_Msk) >> EEFC_FMR_FWS_Pos);
+}
+
+/**
+ * \brief Perform the given command and wait until its completion (or an error).
+ *
+ * \note Unique ID commands are not supported, use efc_read_unique_id.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ * \param ul_command Command to perform.
+ * \param ul_argument Optional command argument.
+ *
+ * \note This function will automatically choose to use IAP function.
+ *
+ * \return 0 if successful, otherwise returns an error code.
+ */
+uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command,
+		uint32_t ul_argument)
+{
+	// Unique ID commands are not supported.
+	if (ul_command == EFC_FCMD_STUI || ul_command == EFC_FCMD_SPUI) {
+		return EFC_RC_NOT_SUPPORT;
+	}
+
+#if (SAM3XA_SERIES || SAM3U4)
+	// Use IAP function with 2 parameters in ROM.
+	static uint32_t(*iap_perform_command) (uint32_t, uint32_t);
+	uint32_t ul_efc_nb = (p_efc == EFC0) ? 0 : 1;
+
+	iap_perform_command =
+			(uint32_t(*)(uint32_t, uint32_t))
+			*((uint32_t *) CHIP_FLASH_IAP_ADDRESS);
+	iap_perform_command(ul_efc_nb,
+			EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(ul_argument) |
+			EEFC_FCR_FCMD(ul_command));
+	return (p_efc->EEFC_FSR & EEFC_ERROR_FLAGS);
+#elif (SAM3N_SERIES || SAM3S_SERIES || SAM4S_SERIES || SAM3U_SERIES)
+	// Use IAP function with 2 parameter in ROM.
+	static uint32_t(*iap_perform_command) (uint32_t, uint32_t);
+
+	iap_perform_command =
+			(uint32_t(*)(uint32_t, uint32_t))
+			*((uint32_t *) CHIP_FLASH_IAP_ADDRESS);
+#if SAM4S_SERIES
+    uint32_t ul_efc_nb = (p_efc == EFC0) ? 0 : 1;
+	iap_perform_command(ul_efc_nb,
+			EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(ul_argument) |
+			EEFC_FCR_FCMD(ul_command));
+#else
+	iap_perform_command(0,
+			EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(ul_argument) |
+			EEFC_FCR_FCMD(ul_command));
+#endif
+	return (p_efc->EEFC_FSR & EEFC_ERROR_FLAGS);
+#else
+	// Use RAM Function.
+	return efc_perform_fcr(p_efc,
+			EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(ul_argument) |
+			EEFC_FCR_FCMD(ul_command));
+
+#endif
+}
+
+/**
+ * \brief Get the current status of the EEFC.
+ *
+ * \note This function clears the value of some status bits (FLOCKE, FCMDE).
+ *
+ * \param p_efc Pointer to an EFC instance.
+ *
+ * \return The current status.
+ */
+uint32_t efc_get_status(Efc *p_efc)
+{
+	return p_efc->EEFC_FSR;
+}
+
+/**
+ * \brief Get the result of the last executed command.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ *
+ * \return The result of the last executed command.
+ */
+uint32_t efc_get_result(Efc *p_efc)
+{
+	return p_efc->EEFC_FRR;
+}
+
+/**
+ * \brief Perform read sequence. Supported sequences are read Unique ID and
+ * read User Signature
+ *
+ * \param p_efc Pointer to an EFC instance.
+ * \param ul_cmd_st Start command to perform.
+ * \param ul_cmd_sp Stop command to perform.
+ * \param p_ul_buf Pointer to an data buffer.
+ * \param ul_size Buffer size.
+ *
+ * \return 0 if successful, otherwise returns an error code.
+ */
+#ifdef __ICCARM__
+__ramfunc
+#else
+__attribute__ ((section(".ramfunc")))
+#endif
+uint32_t efc_perform_read_sequence(Efc *p_efc,
+		uint32_t ul_cmd_st, uint32_t ul_cmd_sp,
+		uint32_t *p_ul_buf, uint32_t ul_size)
+{
+	volatile uint32_t ul_status;
+	uint32_t ul_cnt;
+
+#if (SAM3U4 || SAM3XA_SERIES /*|| SAM4SD16 || SAM4SD32*/)
+	uint32_t *p_ul_data =
+			(uint32_t *) ((p_efc == EFC0) ?
+			READ_BUFF_ADDR0 : READ_BUFF_ADDR1);
+#elif (SAM3S_SERIES || SAM4S_SERIES || SAM3N_SERIES || SAM3U_SERIES)
+	uint32_t *p_ul_data = (uint32_t *) READ_BUFF_ADDR;
+#else
+	return EFC_RC_NOT_SUPPORT;
+#endif
+
+	if (p_ul_buf == NULL) {
+		return EFC_RC_INVALID;
+	}
+
+	p_efc->EEFC_FMR |= (0x1u << 16);
+
+	/* Send the Start Read command */
+#if SAM4S_SERIES
+	p_efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0)
+			| EEFC_FCR_FCMD(ul_cmd_st);
+#else
+    p_efc->EEFC_FCR = EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0)
+			| EEFC_FCR_FCMD(ul_cmd_st);
+#endif
+	/* Wait for the FRDY bit in the Flash Programming Status Register
+	 * (EEFC_FSR) falls.
+	 */
+	do {
+		ul_status = p_efc->EEFC_FSR;
+	} while ((ul_status & EEFC_FSR_FRDY) == EEFC_FSR_FRDY);
+
+	/* The data is located in the first address of the Flash
+	 * memory mapping.
+	 */
+	for (ul_cnt = 0; ul_cnt < ul_size; ul_cnt++) {
+		p_ul_buf[ul_cnt] = p_ul_data[ul_cnt];
+	}
+
+	/* To stop the read mode */
+	p_efc->EEFC_FCR =
+#if SAM4S_SERIES
+			EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) |
+			EEFC_FCR_FCMD(ul_cmd_sp);
+#else
+			EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) |
+			EEFC_FCR_FCMD(ul_cmd_sp);
+#endif
+	/* Wait for the FRDY bit in the Flash Programming Status Register (EEFC_FSR)
+	 * rises.
+	 */
+	do {
+		ul_status = p_efc->EEFC_FSR;
+	} while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY);
+
+	p_efc->EEFC_FMR &= ~(0x1u << 16);
+
+	return EFC_RC_OK;
+}
+
+/**
+ * \brief Set mode register.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ * \param ul_fmr Value of mode register
+ */
+#ifdef __ICCARM__
+__ramfunc
+#else
+__attribute__ ((section(".ramfunc")))
+#endif
+void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr)
+{
+	p_efc->EEFC_FMR = ul_fmr;
+}
+
+/**
+ * \brief Perform command.
+ *
+ * \param p_efc Pointer to an EFC instance.
+ * \param ul_fcr Flash command.
+ *
+ * \return The current status.
+ */
+#ifdef __ICCARM__
+__ramfunc
+#else
+__attribute__ ((section(".ramfunc")))
+#endif
+uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr)
+{
+	volatile uint32_t ul_status;
+
+	p_efc->EEFC_FCR = ul_fcr;
+	do {
+		ul_status = p_efc->EEFC_FSR;
+	} while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY);
+
+	return (ul_status & EEFC_ERROR_FLAGS);
+}
+
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
diff --git a/hardware/digistump/sam/system/libsam/source/emac.c b/hardware/digistump/sam/system/libsam/source/emac.c
new file mode 100644
index 0000000..c023fc2
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/emac.c
@@ -0,0 +1,802 @@
+ /**
+ * \file
+ *
+ * \brief EMAC (Ethernet MAC) driver for SAM.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "../chip.h"
+#include 
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#if SAM3XA_SERIES
+
+/**
+ * \defgroup emac_group Ethernet Media Access Controller
+ *
+ * See \ref emac_quickstart.
+ *
+ * Driver for the EMAC (Ethernet Media Access Controller).
+ * This file contains basic functions for the EMAC, with support for all modes, settings
+ * and clock speeds.
+ *
+ * \section dependencies Dependencies
+ * This driver does not depend on other modules.
+ *
+ * @{
+ */
+
+#define EMAC_RX_BUFFERS                               16
+#define EMAC_TX_BUFFERS                               8
+#define MAC_PHY_RETRY_MAX                             1000000
+
+
+/** TX descriptor lists */
+#ifdef __ICCARM__ /* IAR */
+#pragma data_alignment=8
+#endif
+static emac_tx_descriptor_t gs_tx_desc[EMAC_TX_BUFFERS];
+/** TX callback lists */
+static emac_dev_tx_cb_t gs_tx_callback[EMAC_TX_BUFFERS];
+/** RX descriptors lists */
+#ifdef __ICCARM__ /* IAR */
+#pragma data_alignment=8
+#endif
+static emac_rx_descriptor_t gs_rx_desc[EMAC_RX_BUFFERS];
+/** Send Buffer. Section 3.6 of AMBA 2.0 spec states that burst should not cross the
+ * 1K Boundaries. Receive buffer manager write operations are burst of 2 words => 3 lsb bits
+ * of the address shall be set to 0.
+ */
+#ifdef __ICCARM__ /* IAR */
+#pragma data_alignment=8
+#endif
+static uint8_t gs_uc_tx_buffer[EMAC_TX_BUFFERS * EMAC_TX_UNITSIZE]
+		__attribute__ ((aligned(8)));
+
+#ifdef __ICCARM__ /* IAR */
+#pragma data_alignment=8
+#endif
+/** Receive Buffer */
+static uint8_t gs_uc_rx_buffer[EMAC_RX_BUFFERS * EMAC_RX_UNITSIZE]
+		__attribute__ ((aligned(8)));
+
+/**
+ * EMAC device memory management struct.
+ */
+typedef struct emac_dev_mem {
+	/* Pointer to allocated buffer for RX. The address should be 8-byte aligned
+	and the size should be EMAC_RX_UNITSIZE * wRxSize. */
+	uint8_t *p_rx_buffer;
+	/* Pointer to allocated RX descriptor list. */
+	emac_rx_descriptor_t *p_rx_dscr;
+	/* RX size, in number of registered units (RX descriptors). */
+	uint16_t us_rx_size;
+	/* Pointer to allocated buffer for TX. The address should be 8-byte aligned
+	and the size should be EMAC_TX_UNITSIZE * wTxSize. */
+	uint8_t *p_tx_buffer;
+	/* Pointer to allocated TX descriptor list. */
+	emac_tx_descriptor_t *p_tx_dscr;
+	/* TX size, in number of registered units (TX descriptors). */
+	uint16_t us_tx_size;
+} emac_dev_mem_t;
+
+/** Return count in buffer */
+#define CIRC_CNT(head,tail,size) (((head) - (tail)) % (size))
+
+/*
+ * Return space available, from 0 to size-1.
+ * Always leave one free char as a completely full buffer that has (head == tail),
+ * which is the same as empty.
+ */
+#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
+
+/** Circular buffer is empty ? */
+#define CIRC_EMPTY(head, tail)     (head == tail)
+/** Clear circular buffer */
+#define CIRC_CLEAR(head, tail)     (head = tail = 0)
+
+/** Increment head or tail */
+static void circ_inc(uint16_t *headortail, uint32_t size)
+{
+        (*headortail)++;
+        if((*headortail) >= size) {
+            (*headortail) = 0;
+        }
+}
+
+/**
+ * \brief Wait PHY operation to be completed.
+ *
+ * \param p_emac HW controller address.
+ * \param ul_retry The retry times, 0 to wait forever until completeness.
+ *
+ * Return EMAC_OK if the operation is completed successfully.
+ */
+static uint8_t emac_wait_phy(Emac* p_emac, const uint32_t ul_retry)
+{
+	volatile uint32_t ul_retry_count = 0;
+
+	while (!emac_is_phy_idle(p_emac)) {
+		if (ul_retry == 0) {
+			continue;
+		}
+
+		ul_retry_count++;
+
+		if (ul_retry_count >= ul_retry) {
+			return EMAC_TIMEOUT;
+		}
+	}
+	return EMAC_OK;
+}
+
+/**
+ * \brief Disable transfer, reset registers and descriptor lists.
+ *
+ * \param p_dev Pointer to EMAC driver instance.
+ *
+ */
+static void emac_reset_tx_mem(emac_device_t* p_dev)
+{
+	Emac *p_hw = p_dev->p_hw;
+	uint8_t *p_tx_buff = p_dev->p_tx_buffer;
+	emac_tx_descriptor_t *p_td = p_dev->p_tx_dscr;
+
+	uint32_t ul_index;
+	uint32_t ul_address;
+
+	/* Disable TX */
+	emac_enable_transmit(p_hw, 0);
+
+	/* Set up the TX descriptors */
+	CIRC_CLEAR(p_dev->us_tx_head, p_dev->us_tx_tail);
+	for (ul_index = 0; ul_index < p_dev->us_tx_list_size; ul_index++) {
+		ul_address = (uint32_t) (&(p_tx_buff[ul_index * EMAC_TX_UNITSIZE]));
+		p_td[ul_index].addr = ul_address;
+		p_td[ul_index].status.val = EMAC_TXD_USED;
+	}
+	p_td[p_dev->us_tx_list_size - 1].status.val =
+			EMAC_TXD_USED | EMAC_TXD_WRAP;
+
+	/* Set transmit buffer queue */
+	emac_set_tx_queue(p_hw, (uint32_t) p_td);
+}
+
+/**
+ * \brief Disable receiver, reset registers and descriptor list.
+ *
+ * \param p_drv Pointer to EMAC Driver instance.
+ */
+static void emac_reset_rx_mem(emac_device_t* p_dev)
+{
+	Emac *p_hw = p_dev->p_hw;
+	uint8_t *p_rx_buff = p_dev->p_rx_buffer;
+	emac_rx_descriptor_t *pRd = p_dev->p_rx_dscr;
+
+	uint32_t ul_index;
+	uint32_t ul_address;
+
+	/* Disable RX */
+	emac_enable_receive(p_hw, 0);
+
+	/* Set up the RX descriptors */
+	p_dev->us_rx_idx = 0;
+	for (ul_index = 0; ul_index < p_dev->us_rx_list_size; ul_index++) {
+		ul_address = (uint32_t) (&(p_rx_buff[ul_index * EMAC_RX_UNITSIZE]));
+		pRd[ul_index].addr.val = ul_address & EMAC_RXD_ADDR_MASK;
+		pRd[ul_index].status.val = 0;
+	}
+	pRd[p_dev->us_rx_list_size - 1].addr.val |= EMAC_RXD_WRAP;
+
+	/* Set receive buffer queue */
+	emac_set_rx_queue(p_hw, (uint32_t) pRd);
+}
+
+
+/**
+ * \brief Initialize the allocated buffer lists for EMAC driver to transfer data.
+ * Must be invoked after emac_dev_init() but before RX/TX starts.
+ *
+ * \note If input address is not 8-byte aligned, the address is automatically
+ *       adjusted and the list size is reduced by one.
+ *
+ * \param p_emac Pointer to EMAC instance.
+ * \param p_emac_dev Pointer to EMAC device instance.
+ * \param p_dev_mm Pointer to the EMAC memory management control block.
+ * \param p_tx_cb Pointer to allocated TX callback list.
+ *
+ * \return EMAC_OK or EMAC_PARAM.
+ */
+static uint8_t emac_init_mem(Emac* p_emac, emac_device_t* p_emac_dev,
+		emac_dev_mem_t* p_dev_mm,
+		emac_dev_tx_cb_t* p_tx_cb)
+{
+	if (p_dev_mm->us_rx_size <= 1 || p_dev_mm->us_tx_size <= 1 || p_tx_cb == NULL) {
+		return EMAC_PARAM;
+	}
+
+	/* Assign RX buffers */
+	if (((uint32_t) p_dev_mm->p_rx_buffer & 0x7)
+			|| ((uint32_t) p_dev_mm->p_rx_dscr & 0x7)) {
+		p_dev_mm->us_rx_size--;
+	}
+	p_emac_dev->p_rx_buffer =
+			(uint8_t *) ((uint32_t) p_dev_mm->p_rx_buffer & 0xFFFFFFF8);
+	p_emac_dev->p_rx_dscr =
+			(emac_rx_descriptor_t *) ((uint32_t) p_dev_mm->p_rx_dscr
+			& 0xFFFFFFF8);
+	p_emac_dev->us_rx_list_size = p_dev_mm->us_rx_size;
+
+	/* Assign TX buffers */
+	if (((uint32_t) p_dev_mm->p_tx_buffer & 0x7)
+			|| ((uint32_t) p_dev_mm->p_tx_dscr & 0x7)) {
+		p_dev_mm->us_tx_size--;
+	}
+	p_emac_dev->p_tx_buffer =
+			(uint8_t *) ((uint32_t) p_dev_mm->p_tx_buffer & 0xFFFFFFF8);
+	p_emac_dev->p_tx_dscr =
+			(emac_tx_descriptor_t *) ((uint32_t) p_dev_mm->p_tx_dscr
+			& 0xFFFFFFF8);
+	p_emac_dev->us_tx_list_size = p_dev_mm->us_tx_size;
+	p_emac_dev->func_tx_cb_list = p_tx_cb;
+
+	/* Reset TX & RX */
+	emac_reset_rx_mem(p_emac_dev);
+	emac_reset_tx_mem(p_emac_dev);
+
+	/* Enable Rx and Tx, plus the statistics register */
+	emac_enable_transmit(p_emac, 1);
+	emac_enable_receive(p_emac, 1);
+	emac_enable_statistics_write(p_emac, 1);
+
+	/* Set up the interrupts for transmission and errors */
+	emac_enable_interrupt(p_emac,
+			EMAC_IER_RXUBR | /* Enable receive used bit read interrupt. */
+			EMAC_IER_TUND  | /* Enable transmit underrun interrupt. */
+			EMAC_IER_RLE   | /* Enable retry limit  exceeded interrupt. */
+			EMAC_IER_TXERR | /* Enable transmit buffers exhausted in mid-frame interrupt. */
+			EMAC_IER_TCOMP | /* Enable transmit complete interrupt. */
+			EMAC_IER_ROVR  | /* Enable receive overrun interrupt. */
+			EMAC_IER_HRESP | /* Enable Hresp not OK interrupt. */
+			EMAC_IER_PFR   | /* Enable pause frame received interrupt. */
+			EMAC_IER_PTZ);   /* Enable pause time zero interrupt. */
+
+	return EMAC_OK;
+}
+
+/**
+ * \brief Read the PHY register.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_phy_address PHY address.
+ * \param uc_address Register address.
+ * \param p_value Pointer to a 32-bit location to store read data.
+ *
+ * \Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout.
+ */
+uint8_t emac_phy_read(Emac* p_emac, uint8_t uc_phy_address, uint8_t uc_address,
+		uint32_t* p_value)
+{
+	emac_maintain_phy(p_emac, uc_phy_address, uc_address, 1, 0);
+
+	if (emac_wait_phy(p_emac, MAC_PHY_RETRY_MAX) == EMAC_TIMEOUT) {
+		return EMAC_TIMEOUT;
+	}
+	*p_value = emac_get_phy_data(p_emac);
+	return EMAC_OK;
+}
+
+/**
+ * \brief Write the PHY register.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param uc_phy_address PHY Address.
+ * \param uc_address Register Address.
+ * \param ul_value Data to write, actually 16-bit data.
+ *
+ * \Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout.
+ */
+uint8_t emac_phy_write(Emac* p_emac, uint8_t uc_phy_address,
+		uint8_t uc_address, uint32_t ul_value)
+{
+	emac_maintain_phy(p_emac, uc_phy_address, uc_address, 0, ul_value);
+
+	if (emac_wait_phy(p_emac, MAC_PHY_RETRY_MAX) == EMAC_TIMEOUT) {
+		return EMAC_TIMEOUT;
+	}
+	return EMAC_OK;
+}
+
+/**
+ * \brief Initialize the EMAC driver.
+ *
+ * \param p_emac   Pointer to the EMAC instance.
+ * \param p_emac_dev Pointer to the EMAC device instance.
+ * \param p_opt EMAC configure options.
+ */
+void emac_dev_init(Emac* p_emac, emac_device_t* p_emac_dev,
+		emac_options_t* p_opt)
+{
+	emac_dev_mem_t emac_dev_mm;
+
+	/* Disable TX & RX and more */
+	emac_network_control(p_emac, 0);
+	emac_disable_interrupt(p_emac, ~0u);
+
+	emac_clear_statistics(p_emac);
+
+	/* Clear all status bits in the receive status register. */
+	emac_clear_rx_status(p_emac, EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA);
+
+	/* Clear all status bits in the transmit status register */
+	emac_clear_tx_status(p_emac, EMAC_TSR_UBR | EMAC_TSR_COL | EMAC_TSR_RLES
+			| EMAC_TSR_BEX | EMAC_TSR_COMP | EMAC_TSR_UND);
+
+	/* Clear interrupts */
+	emac_get_interrupt_status(p_emac);
+
+	/* Enable the copy of data into the buffers
+	   ignore broadcasts, and not copy FCS. */
+	emac_set_configure(p_emac,
+			emac_get_configure(p_emac) | EMAC_NCFGR_DRFCS | EMAC_NCFGR_PAE);
+
+	emac_enable_copy_all(p_emac, p_opt->uc_copy_all_frame);
+	emac_disable_broadcast(p_emac, p_opt->uc_no_boardcast);
+
+	/* Fill in EMAC device memory management */
+	emac_dev_mm.p_rx_buffer = gs_uc_rx_buffer;
+	emac_dev_mm.p_rx_dscr = gs_rx_desc;
+	emac_dev_mm.us_rx_size = EMAC_RX_BUFFERS;
+
+	emac_dev_mm.p_tx_buffer = gs_uc_tx_buffer;
+	emac_dev_mm.p_tx_dscr = gs_tx_desc;
+	emac_dev_mm.us_tx_size = EMAC_TX_BUFFERS;
+
+	emac_init_mem(p_emac, p_emac_dev, &emac_dev_mm, gs_tx_callback);
+
+	emac_set_address(p_emac, 0, p_opt->uc_mac_addr);
+
+}
+
+/**
+ * \brief Frames can be read from the EMAC in multiple sections.
+ * Read ul_frame_size bytes from the EMAC receive buffers to pcTo.
+ * p_rcv_size is the size of the entire frame.  Generally emac_read
+ * will be repeatedly called until the sum of all the ul_frame_size equals
+ * the value of p_rcv_size.
+ *
+ * \param p_emac_dev Pointer to the EMAC device instance.
+ * \param p_frame Address of the frame buffer.
+ * \param ul_frame_size  Length of the frame.
+ * \param p_rcv_size   Received frame size.
+ *
+ * \return EMAC_OK if receiving frame successfully, otherwise failed.
+ */
+uint32_t emac_dev_read(emac_device_t* p_emac_dev, uint8_t* p_frame,
+		uint32_t ul_frame_size, uint32_t* p_rcv_size)
+{
+	uint16_t us_buffer_length;
+	uint32_t tmp_ul_frame_size = 0;
+	uint8_t *p_tmp_frame = 0;
+	uint16_t us_tmp_idx = p_emac_dev->us_rx_idx;
+	emac_rx_descriptor_t *p_rx_td =
+			&p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx];
+	int8_t c_is_frame = 0;
+
+	if (p_frame == NULL)
+		return EMAC_PARAM;
+
+	/* Set the default return value */
+	*p_rcv_size = 0;
+
+	/* Process received RX descriptor */
+	while ((p_rx_td->addr.val & EMAC_RXD_OWNERSHIP) == EMAC_RXD_OWNERSHIP) {
+		/* A start of frame has been received, discard previous fragments */
+		if ((p_rx_td->status.val & EMAC_RXD_SOF) == EMAC_RXD_SOF) {
+			/* Skip previous fragment */
+			while (us_tmp_idx != p_emac_dev->us_rx_idx) {
+				p_rx_td = &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx];
+				p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP);
+
+				circ_inc(&p_emac_dev->us_rx_idx, p_emac_dev->us_rx_list_size);
+			}
+			/* Reset the temporary frame pointer */
+			p_tmp_frame = p_frame;
+			tmp_ul_frame_size = 0;
+			/* Start to gather buffers in a frame */
+			c_is_frame = 1;
+		}
+
+		/* Increment the pointer */
+		circ_inc(&us_tmp_idx, p_emac_dev->us_rx_list_size);
+
+		/* Copy data in the frame buffer */
+		if (c_is_frame) {
+			if (us_tmp_idx == p_emac_dev->us_rx_idx) {
+				do {
+					p_rx_td = &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx];
+					p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP);
+					circ_inc(&p_emac_dev->us_rx_idx, p_emac_dev->us_rx_list_size);
+
+				} while (us_tmp_idx != p_emac_dev->us_rx_idx);
+
+				return EMAC_RX_NULL;
+			}
+			/* Copy the buffer into the application frame */
+			us_buffer_length = EMAC_RX_UNITSIZE;
+			if ((tmp_ul_frame_size + us_buffer_length) > ul_frame_size) {
+				us_buffer_length = ul_frame_size - tmp_ul_frame_size;
+			}
+
+			memcpy(p_tmp_frame,
+					(void *)(p_rx_td->addr.val & EMAC_RXD_ADDR_MASK),
+					us_buffer_length);
+			p_tmp_frame += us_buffer_length;
+			tmp_ul_frame_size += us_buffer_length;
+
+			/* An end of frame has been received, return the data */
+			if ((p_rx_td->status.val & EMAC_RXD_EOF) == EMAC_RXD_EOF) {
+				/* Frame size from the EMAC */
+				*p_rcv_size = (p_rx_td->status.val & EMAC_RXD_LEN_MASK);
+
+				/* All data have been copied in the application frame buffer => release TD */
+				while (p_emac_dev->us_rx_idx != us_tmp_idx) {
+					p_rx_td = &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx];
+					p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP);
+					circ_inc(&p_emac_dev->us_rx_idx, p_emac_dev->us_rx_list_size);
+				}
+
+				/* Application frame buffer is too small so that all data have not been copied */
+				if (tmp_ul_frame_size < *p_rcv_size) {
+					return EMAC_SIZE_TOO_SMALL;
+				}
+
+				return EMAC_OK;
+			}
+		}
+		/* SOF has not been detected, skip the fragment */
+		else {
+			p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP);
+			p_emac_dev->us_rx_idx = us_tmp_idx;
+		}
+
+		/* Process the next buffer */
+		p_rx_td = &p_emac_dev->p_rx_dscr[us_tmp_idx];
+	}
+
+	return EMAC_RX_NULL;
+}
+
+/**
+ * \brief Send ulLength bytes from pcFrom. This copies the buffer to one of the
+ * EMAC Tx buffers, and then indicates to the EMAC that the buffer is ready.
+ * If lEndOfFrame is true then the data being copied is the end of the frame
+ * and the frame can be transmitted.
+ *
+ * \param p_emac_dev Pointer to the EMAC device instance.
+ * \param p_buffer       Pointer to the data buffer.
+ * \param ul_size    Length of the frame.
+ * \param func_tx_cb  Transmit callback function.
+ *
+ * \return Length sent.
+ */
+uint32_t emac_dev_write(emac_device_t* p_emac_dev, void *p_buffer,
+		uint32_t ul_size, emac_dev_tx_cb_t func_tx_cb)
+{
+
+	volatile emac_tx_descriptor_t *p_tx_td;
+	volatile emac_dev_tx_cb_t *p_func_tx_cb;
+
+	Emac *p_hw = p_emac_dev->p_hw;
+
+
+	/* Check parameter */
+	if (ul_size > EMAC_TX_UNITSIZE) {
+		return EMAC_PARAM;
+	}
+
+	/* Pointers to the current transmit descriptor */
+	p_tx_td = &p_emac_dev->p_tx_dscr[p_emac_dev->us_tx_head];
+
+	/* If no free TxTd, buffer can't be sent, schedule the wakeup callback */
+	if (CIRC_SPACE(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail,
+					p_emac_dev->us_tx_list_size) == 0) {
+		return EMAC_TX_BUSY;
+	}
+
+	/* Pointers to the current Tx callback */
+	p_func_tx_cb = &p_emac_dev->func_tx_cb_list[p_emac_dev->us_tx_head];
+
+	/* Set up/copy data to transmission buffer */
+	if (p_buffer && ul_size) {
+		/* Driver manages the ring buffer */
+		memcpy((void *)p_tx_td->addr, p_buffer, ul_size);
+	}
+
+	/* Tx callback */
+	*p_func_tx_cb = func_tx_cb;
+
+	/* Update transmit descriptor status */
+
+	/* The buffer size defined is the length of ethernet frame,
+	   so it's always the last buffer of the frame. */
+	if (p_emac_dev->us_tx_head == p_emac_dev->us_tx_list_size - 1) {
+		p_tx_td->status.val =
+				(ul_size & EMAC_TXD_LEN_MASK) | EMAC_TXD_LAST
+				| EMAC_TXD_WRAP;
+	} else {
+		p_tx_td->status.val =
+				(ul_size & EMAC_TXD_LEN_MASK) | EMAC_TXD_LAST;
+	}
+
+	circ_inc(&p_emac_dev->us_tx_head, p_emac_dev->us_tx_list_size);
+
+	/* Now start to transmit if it is still not done */
+	emac_start_transmission(p_hw);
+
+	return EMAC_OK;
+}
+
+/**
+ * \brief Get current load of transmit.
+ *
+ * \param p_emac_dev Pointer to the EMAC device instance.
+ *
+ * \return Current load of transmit.
+ */
+uint32_t emac_dev_get_tx_load(emac_device_t* p_emac_dev)
+{
+	uint16_t us_head = p_emac_dev->us_tx_head;
+	uint16_t us_tail = p_emac_dev->us_tx_tail;
+	return CIRC_CNT(us_head, us_tail, p_emac_dev->us_tx_list_size);
+}
+
+/**
+ * \brief Register/Clear RX callback. Callback will be invoked after the next received
+ * frame.
+ *
+ * When emac_dev_read() returns EMAC_RX_NULL, the application task calls
+ * emac_dev_set_rx_callback() to register func_rx_cb() callback and enters suspend state.
+ * The callback is in charge to resume the task once a new frame has been
+ * received. The next time emac_dev_read() is called, it will be successful.
+ *
+ * This function is usually invoked from the RX callback itself with NULL
+ * callback, to unregister. Once the callback has resumed the application task,
+ * there is no need to invoke the callback again.
+ *
+ * \param p_emac_dev Pointer to the EMAC device instance.
+ * \param func_tx_cb  Receive callback function.
+ */
+void emac_dev_set_rx_callback(emac_device_t* p_emac_dev,
+		emac_dev_tx_cb_t func_rx_cb)
+{
+	Emac *p_hw = p_emac_dev->p_hw;
+
+	if (func_rx_cb == NULL) {
+		emac_disable_interrupt(p_hw, EMAC_IDR_RCOMP);
+		p_emac_dev->func_rx_cb = NULL;
+	} else {
+		p_emac_dev->func_rx_cb = func_rx_cb;
+		emac_enable_interrupt(p_hw, EMAC_IER_RCOMP);
+	}
+}
+
+/**
+ *  \brief Register/Clear TX wakeup callback.
+ *
+ * When emac_dev_write() returns EMAC_TX_BUSY (all transmit descriptor busy), the application
+ * task calls emac_dev_set_tx_wakeup_callback() to register func_wakeup() callback and
+ * enters suspend state. The callback is in charge to resume the task once
+ * several transmit descriptors have been released. The next time emac_dev_write() will be called,
+ * it shall be successful.
+ *
+ * This function is usually invoked with NULL callback from the TX wakeup
+ * callback itself, to unregister. Once the callback has resumed the
+ * application task, there is no need to invoke the callback again.
+ *
+ * \param p_emac_dev   Pointer to EMAC device instance.
+ * \param func_wakeup    Pointer to wakeup callback function.
+ * \param uc_threshold Number of free transmit descriptor before wakeup callback invoked.
+ *
+ * \return EMAC_OK, EMAC_PARAM on parameter error.
+ */
+uint8_t emac_dev_set_tx_wakeup_callback(emac_device_t* p_emac_dev,
+		emac_dev_wakeup_cb_t func_wakeup_cb, uint8_t uc_threshold)
+{
+	if (func_wakeup_cb == NULL) {
+		p_emac_dev->func_wakeup_cb = NULL;
+	} else {
+		if (uc_threshold <= p_emac_dev->us_tx_list_size) {
+			p_emac_dev->func_wakeup_cb = func_wakeup_cb;
+			p_emac_dev->uc_wakeup_threshold = uc_threshold;
+		} else {
+			return EMAC_PARAM;
+		}
+	}
+
+	return EMAC_OK;
+}
+
+
+/**
+ * \brief Reset TX & RX queue & statistics.
+ *
+ * \param p_emac_dev   Pointer to EMAC device instance.
+ */
+void emac_dev_reset(emac_device_t* p_emac_dev)
+{
+	Emac *p_hw = p_emac_dev->p_hw;
+
+	emac_reset_rx_mem(p_emac_dev);
+	emac_reset_tx_mem(p_emac_dev);
+	emac_network_control(p_hw, EMAC_NCR_TE | EMAC_NCR_RE
+			| EMAC_NCR_WESTAT | EMAC_NCR_CLRSTAT);
+}
+
+
+/**
+ * \brief EMAC Interrupt handler.
+ *
+ * \param p_emac_dev   Pointer to EMAC device instance.
+ */
+void emac_handler(emac_device_t* p_emac_dev)
+{
+	Emac *p_hw = p_emac_dev->p_hw;
+
+	emac_tx_descriptor_t *p_tx_td;
+	emac_dev_tx_cb_t *p_tx_cb;
+	volatile uint32_t ul_isr;
+	volatile uint32_t ul_rsr;
+	volatile uint32_t ul_tsr;
+	uint32_t ul_rx_status_flag;
+	uint32_t ul_tx_status_flag;
+
+	ul_isr = emac_get_interrupt_status(p_hw);
+	ul_rsr = emac_get_rx_status(p_hw);
+	ul_tsr = emac_get_tx_status(p_hw);
+
+	ul_isr &= ~(emac_get_interrupt_mask(p_hw) | 0xFFC300);
+
+	/* RX packet */
+	if ((ul_isr & EMAC_ISR_RCOMP) || (ul_rsr & EMAC_RSR_REC)) {
+		ul_rx_status_flag = EMAC_RSR_REC;
+
+		/* Check OVR */
+		if (ul_rsr & EMAC_RSR_OVR) {
+			ul_rx_status_flag |= EMAC_RSR_OVR;
+		}
+		/* Check BNA */
+		if (ul_rsr & EMAC_RSR_BNA) {
+			ul_rx_status_flag |= EMAC_RSR_BNA;
+		}
+		/* Clear status */
+		emac_clear_rx_status(p_hw, ul_rx_status_flag);
+
+		/* Invoke callbacks */
+		if (p_emac_dev->func_rx_cb) {
+			p_emac_dev->func_rx_cb(ul_rx_status_flag);
+		}
+	}
+
+	/* TX packet */
+	if ((ul_isr & EMAC_ISR_TCOMP) || (ul_tsr & EMAC_TSR_COMP)) {
+
+		ul_tx_status_flag = EMAC_TSR_COMP;
+
+		/* A frame transmitted */
+
+		/* Check RLE */
+		if (ul_tsr & EMAC_TSR_RLES) {
+			/* Status RLE & Number of discarded buffers */
+			ul_tx_status_flag = EMAC_TSR_RLES | CIRC_CNT(p_emac_dev->us_tx_head,
+					p_emac_dev->us_tx_tail, p_emac_dev->us_tx_list_size);
+			p_tx_cb = &p_emac_dev->func_tx_cb_list[p_emac_dev->us_tx_tail];
+			emac_reset_tx_mem(p_emac_dev);
+			emac_enable_transmit(p_hw, 1);
+		}
+		/* Check COL */
+		if (ul_tsr & EMAC_TSR_COL) {
+			ul_tx_status_flag |= EMAC_TSR_COL;
+		}
+		/* Check BEX */
+		if (ul_tsr & EMAC_TSR_BEX) {
+			ul_tx_status_flag |= EMAC_TSR_BEX;
+		}
+		/* Check UND */
+		if (ul_tsr & EMAC_TSR_UND) {
+			ul_tx_status_flag |= EMAC_TSR_UND;
+		}
+		/* Clear status */
+		emac_clear_tx_status(p_hw, ul_tx_status_flag);
+
+		if (!CIRC_EMPTY(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail)) {
+			/* Check the buffers */
+			do {
+				p_tx_td = &p_emac_dev->p_tx_dscr[p_emac_dev->us_tx_tail];
+				p_tx_cb = &p_emac_dev->func_tx_cb_list[p_emac_dev->us_tx_tail];
+				/* Any error? Exit if buffer has not been sent yet */
+				if ((p_tx_td->status.val & EMAC_TXD_USED) == 0) {
+					break;
+				}
+
+				/* Notify upper layer that a packet has been sent */
+				if (*p_tx_cb) {
+					(*p_tx_cb) (ul_tx_status_flag);
+				}
+
+				circ_inc(&p_emac_dev->us_tx_tail, p_emac_dev->us_tx_list_size);
+			} while (CIRC_CNT(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail,
+							p_emac_dev->us_tx_list_size));
+		}
+
+		if (ul_tsr & EMAC_TSR_RLES) {
+			/* Notify upper layer RLE */
+			if (*p_tx_cb) {
+				(*p_tx_cb) (ul_tx_status_flag);
+			}
+		}
+
+		/* If a wakeup has been scheduled, notify upper layer that it can
+		   send other packets, and the sending will be successful. */
+		if ((CIRC_SPACE(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail,
+				p_emac_dev->us_tx_list_size) >= p_emac_dev->uc_wakeup_threshold)
+				&& p_emac_dev->func_wakeup_cb) {
+			p_emac_dev->func_wakeup_cb();
+		}
+	}
+}
+
+//@}
+
+#endif // SAM3XA_SERIES
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
diff --git a/hardware/digistump/sam/system/libsam/source/gpbr.c b/hardware/digistump/sam/system/libsam/source/gpbr.c
new file mode 100644
index 0000000..83d34eb
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/gpbr.c
@@ -0,0 +1,94 @@
+/**
+ * \file
+ *
+ * \brief General Purpose Backup Registers (GPBR) driver for SAM.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "gpbr.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/**
+ * \defgroup sam_drivers_gpbr_group General Purpose Backup Registers (GPBR)
+ *
+ * Driver for the General Purpose Backup Registers. This driver provides access 
+ * to the main features of the GPBR controller.
+ *
+ * @{
+ */
+
+/**
+ * \brief Read the specified backup register.
+ *
+ * \param ul_reg_num General purpose backup register number.
+ * 
+ * \return Value of the specified backup register.
+ */
+uint32_t gpbr_read(gpbr_num_t ul_reg_num)
+{
+	return GPBR->SYS_GPBR[ul_reg_num];
+}
+
+/**
+ * \brief Write a value to the specified backup register.
+ *
+ * \param ul_reg_num General purpose backup register number.
+ * \param ul_value Value to be written.
+ */
+void gpbr_write(gpbr_num_t ul_reg_num, uint32_t ul_value)
+{
+	GPBR->SYS_GPBR[ul_reg_num] = ul_value;
+}
+
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
diff --git a/hardware/digistump/sam/system/libsam/source/interrupt_sam_nvic.c b/hardware/digistump/sam/system/libsam/source/interrupt_sam_nvic.c
new file mode 100644
index 0000000..bbfe172
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/interrupt_sam_nvic.c
@@ -0,0 +1,33 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "interrupt_sam_nvic.h"
+
+//! Global NVIC interrupt enable status (by default it's enabled)
+int g_interrupt_enabled = 1;
diff --git a/hardware/digistump/sam/system/libsam/source/pio.c b/hardware/digistump/sam/system/libsam/source/pio.c
new file mode 100644
index 0000000..3450cbb
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/pio.c
@@ -0,0 +1,386 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \file */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+/**
+ * \brief Configures Pio pin internal pull-up.
+ *
+ * \param pPio            Pointer to a PIO controller.
+ * \param dwMask          Bitmask of one or more pin(s) to configure.
+ * \param dwPullUpEnable  Indicates if the pin(s) internal pull-up shall be configured.
+ */
+extern void PIO_DisableInterrupt( Pio *pPio, const uint32_t dwMask )
+{
+    /* Disable interrupts on the pin */
+    pPio->PIO_IDR = dwMask ;
+}
+
+/**
+ * \brief Configures Pio pin internal pull-up.
+ *
+ * \param pPio            Pointer to a PIO controller.
+ * \param dwMask          Bitmask of one or more pin(s) to configure.
+ * \param dwPullUpEnable  Indicates if the pin(s) internal pull-up shall be configured.
+ */
+extern void PIO_PullUp( Pio *pPio, const uint32_t dwMask, const uint32_t dwPullUpEnable )
+{
+    /* Enable the pull-up(s) if necessary */
+    if ( dwPullUpEnable )
+    {
+        pPio->PIO_PUER = dwMask ;
+    }
+    else
+    {
+        pPio->PIO_PUDR = dwMask ;
+    }
+}
+
+/**
+ * \brief Configures Glitch or Debouncing filter for input.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ * \param cuttoff  Cutt off frequency for debounce filter.
+ */
+extern void PIO_SetDebounceFilter( Pio* pPio, const uint32_t dwMask, const uint32_t dwCuttOff )
+{
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+    pPio->PIO_IFSCER = dwMask ; /* set Debouncing, 0 bit field no effect */
+#elif (defined _SAM3XA_) || (defined _SAM3U_)
+    pPio->PIO_DIFSR = dwMask ; /* set Debouncing, 0 bit field no effect */
+#else
+    #error "The specified chip is not supported."
+#endif
+    pPio->PIO_SCDR = ((32678/(2*(dwCuttOff))) - 1) & 0x3FFF; /* the lowest 14 bits work */
+}
+
+/**
+ * \brief Sets a high output level on all the PIOs defined in the given Pin instance.
+ * This has no immediate effects on PIOs that are not output, but the PIO
+ * controller will memorize the value they are changed to outputs.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ */
+extern void PIO_Set( Pio* pPio, const uint32_t dwMask )
+{
+    pPio->PIO_SODR = dwMask ;
+}
+
+/**
+ * \brief Returns 1 if one or more PIO of the given Pin instance currently have
+ * a high level; otherwise returns 0. This method returns the actual value that
+ * is being read on the pin. To return the supposed output value of a pin, use
+ * PIO_GetOutputDataStatus() instead.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ *
+ * \return 1 if the Pin instance contains at least one PIO that currently has
+ * a high level; otherwise 0.
+ */
+extern uint32_t PIO_Get( Pio* pPio, const EPioType dwType, const uint32_t dwMask )
+{
+    uint32_t dwReg ;
+
+    if ( (dwType == PIO_OUTPUT_0) || (dwType == PIO_OUTPUT_1) )
+    {
+        dwReg = pPio->PIO_ODSR ;
+    }
+    else
+    {
+        dwReg = pPio->PIO_PDSR ;
+    }
+
+    if ( (dwReg & dwMask) == 0 )
+    {
+        return 0 ;
+    }
+    else
+    {
+        return 1 ;
+    }
+}
+
+/**
+ * \brief Sets a low output level on all the PIOs defined in the given Pin instance.
+ * This has no immediate effects on PIOs that are not output, but the PIO
+ * controller will memorize the value they are changed to outputs.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ */
+extern void PIO_Clear( Pio* pPio, const uint32_t dwMask )
+{
+    pPio->PIO_CODR = dwMask ;
+}
+
+/**
+ * \brief Configures one pin of a PIO controller as being controlled by specific peripheral.
+ *
+ * \param pPio    Pointer to a PIO controller.
+ * \param dwType  PIO type.
+ * \param dwMask  Bitmask of one or more pin(s) to configure.
+ */
+extern void PIO_SetPeripheral( Pio* pPio, EPioType dwType, uint32_t dwMask )
+{
+    uint32_t dwSR ;
+
+    /* Disable interrupts on the pin(s) */
+    pPio->PIO_IDR = dwMask ;
+
+    switch ( dwType )
+    {
+        case PIO_PERIPH_A :
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+            dwSR = pPio->PIO_ABCDSR[0] ;
+            pPio->PIO_ABCDSR[0] &= (~dwMask & dwSR) ;
+
+            dwSR = pPio->PIO_ABCDSR[1];
+            pPio->PIO_ABCDSR[1] &= (~dwMask & dwSR) ;
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+
+#if (defined _SAM3U_) || (defined _SAM3XA_)
+            dwSR = pPio->PIO_ABSR ;
+            pPio->PIO_ABSR &= (~dwMask & dwSR) ;
+#endif /* (defined _SAM3U_) || (defined _SAM3XA_) */
+        break ;
+
+        case PIO_PERIPH_B :
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+            dwSR = pPio->PIO_ABCDSR[0] ;
+            pPio->PIO_ABCDSR[0] = (dwMask | dwSR) ;
+
+            dwSR = pPio->PIO_ABCDSR[1] ;
+            pPio->PIO_ABCDSR[1] &= (~dwMask & dwSR) ;
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+
+#if (defined _SAM3U_) || (defined _SAM3XA_)
+            dwSR = pPio->PIO_ABSR ;
+            pPio->PIO_ABSR = (dwMask | dwSR) ;
+#endif /* (defined _SAM3U_) || (defined _SAM3XA_) */
+        break ;
+
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+        case PIO_PERIPH_C :
+            dwSR = pPio->PIO_ABCDSR[0] ;
+            pPio->PIO_ABCDSR[0] &= (~dwMask & dwSR) ;
+
+            dwSR = pPio->PIO_ABCDSR[1] ;
+            pPio->PIO_ABCDSR[1] = (dwMask | dwSR) ;
+        break ;
+
+        case PIO_PERIPH_D :
+            dwSR = pPio->PIO_ABCDSR[0] ;
+            pPio->PIO_ABCDSR[0] = (dwMask | dwSR) ;
+
+            dwSR = pPio->PIO_ABCDSR[1] ;
+            pPio->PIO_ABCDSR[1] = (dwMask | dwSR) ;
+        break ;
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+
+        // other types are invalid in this function
+        case PIO_INPUT :
+        case PIO_OUTPUT_0 :
+        case PIO_OUTPUT_1 :
+        case PIO_NOT_A_PIN :
+        return ;
+    }
+
+    // Remove the pins from under the control of PIO
+    pPio->PIO_PDR = dwMask ;
+}
+
+/**
+ * \brief Configures one or more pin(s) or a PIO controller as inputs. Optionally,
+ * the corresponding internal pull-up(s) and glitch filter(s) can be enabled.
+ *
+ * \param pPio        Pointer to a PIO controller.
+ * \param dwMask      Bitmask indicating which pin(s) to configure as input(s).
+ * \param dwAttribute .
+ */
+extern void PIO_SetInput( Pio* pPio, uint32_t dwMask, uint32_t dwAttribute )
+{
+    PIO_DisableInterrupt( pPio, dwMask ) ;
+    PIO_PullUp( pPio, dwMask, dwAttribute & PIO_PULLUP ) ;
+
+    /* Enable Input Filter if necessary */
+    if ( dwAttribute & (PIO_DEGLITCH | PIO_DEBOUNCE) )
+    {
+        pPio->PIO_IFER = dwMask ;
+    }
+    else
+    {
+        pPio->PIO_IFDR = dwMask ;
+    }
+
+    /* Enable de-glitch or de-bounce if necessary */
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+    if ( dwAttribute & PIO_DEGLITCH )
+    {
+        pPio->PIO_IFSCDR = dwMask ;
+    }
+    else
+    {
+        if ( dwAttribute & PIO_DEBOUNCE )
+        {
+            pPio->PIO_IFSCER = dwMask ;
+        }
+    }
+#elif (defined _SAM3U_) || (defined _SAM3XA_)
+    if ( dwAttribute & PIO_DEGLITCH )
+    {
+        pPio->PIO_SCIFSR = dwMask ;
+    }
+    else
+    {
+        if ( dwAttribute & PIO_DEBOUNCE )
+        {
+            pPio->PIO_SCIFSR = dwMask ;
+        }
+    }
+#else
+    #error "The specified chip is not supported."
+#endif
+
+    /* Configure pin as input */
+    pPio->PIO_ODR = dwMask ;
+    pPio->PIO_PER = dwMask ;
+}
+
+/**
+ * \brief Configures one or more pin(s) of a PIO controller as outputs, with the
+ * given default value. Optionally, the multi-drive feature can be enabled
+ * on the pin(s).
+ *
+ * \param pPio              Pointer to a PIO controller.
+ * \param dwMask            Bitmask indicating which pin(s) to configure.
+ * \param defaultValue      Default level on the pin(s).
+ * \param enableMultiDrive  Indicates if the pin(s) shall be configured as open-drain.
+ * \param enablePullUp      Indicates if the pin shall have its pull-up activated.
+ */
+extern void PIO_SetOutput( Pio* pPio, uint32_t dwMask, uint32_t dwDefaultValue,
+                                      uint32_t dwMultiDriveEnable, uint32_t dwPullUpEnable )
+{
+    PIO_DisableInterrupt( pPio, dwMask ) ;
+    PIO_PullUp( pPio, dwMask, dwPullUpEnable ) ;
+
+    /* Enable multi-drive if necessary */
+    if ( dwMultiDriveEnable )
+    {
+        pPio->PIO_MDER = dwMask ;
+    }
+    else
+    {
+        pPio->PIO_MDDR = dwMask ;
+    }
+
+    /* Set default value */
+    if ( dwDefaultValue )
+    {
+        pPio->PIO_SODR = dwMask ;
+    }
+    else
+    {
+        pPio->PIO_CODR = dwMask ;
+    }
+
+    /* Configure pin(s) as output(s) */
+    pPio->PIO_OER = dwMask ;
+    pPio->PIO_PER = dwMask ;
+}
+
+/**
+ *
+ * \return 1 if the pins have been configured properly; otherwise 0.
+ */
+extern uint32_t PIO_Configure( Pio* pPio, const EPioType dwType, const uint32_t dwMask, const uint32_t dwAttribute )
+{
+    /* Configure pins */
+    switch ( dwType )
+    {
+        case PIO_PERIPH_A :
+        case PIO_PERIPH_B :
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+        case PIO_PERIPH_C :
+        case PIO_PERIPH_D :
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+            /* Put the pin under control of peripheral */
+            PIO_SetPeripheral( pPio, dwType, dwMask ) ;
+            /* Disable interrupts on the pin(s) */
+            PIO_DisableInterrupt( pPio, dwMask ) ;
+            /* Enable Pullup */
+            PIO_PullUp( pPio, dwMask, (dwAttribute & PIO_PULLUP) ) ;
+        break;
+
+        case PIO_INPUT :
+            PIO_SetInput( pPio, dwMask, dwAttribute ) ;
+        break;
+
+        case PIO_OUTPUT_0 :
+        case PIO_OUTPUT_1 :
+            PIO_SetOutput( pPio, dwMask, (dwType == PIO_OUTPUT_1),
+                          (dwAttribute & PIO_OPENDRAIN) ? 1 : 0,
+                          (dwAttribute & PIO_PULLUP) ? 1 : 0);
+        break ;
+
+        default :
+        return 0 ;
+    }
+
+    return 1 ;
+}
+
+/**
+ * \brief Returns 1 if one or more PIO of the given Pin are configured to output a
+ * high level (even if they are not output).
+ * To get the actual value of the pin, use PIO_Get() instead.
+ *
+ * \param pPio  Pointer to a Pin instance describing one or more pins.
+ *
+ * \return 1 if the Pin instance contains at least one PIO that is configured
+ * to output a high level; otherwise 0.
+ */
+extern uint32_t PIO_GetOutputDataStatus( const Pio* pPio, const uint32_t dwMask )
+{
+  /* Test if pin is under control of PIO */
+  if ( (pPio->PIO_PSR & dwMask) != 0 )
+  {
+    /* Test if pin is configured as output */
+    if ( (pPio->PIO_OSR & dwMask) != 0 )
+    {
+      return 1 ;
+    }
+  }
+
+  return 0 ;
+}
+
diff --git a/hardware/digistump/sam/system/libsam/source/pmc.c b/hardware/digistump/sam/system/libsam/source/pmc.c
new file mode 100644
index 0000000..b01dc60
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/pmc.c
@@ -0,0 +1,1046 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "chip.h"
+
+#if (SAM3N_SERIES)
+# define MAX_PERIPH_ID    31
+#elif (SAM3XA_SERIES)
+# define MAX_PERIPH_ID    44
+#elif (SAM3U_SERIES)
+# define MAX_PERIPH_ID    29
+#elif (SAM3S_SERIES || SAM4S_SERIES)
+# define MAX_PERIPH_ID    34
+#endif
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/**
+ * \defgroup sam_drivers_pmc_group Power Management Controller (PMC)
+ *
+ * \par Purpose
+ *
+ * The Power Management Controller (PMC) optimizes power consumption by controlling
+ * all system and user peripheral clocks. The PMC enables/disables the clock inputs
+ * to many of the peripherals and the Cortex-M Processor.
+ *
+ * @{
+ */
+
+/**
+ * \brief Set the prescaler of the MCK.
+ *
+ * \param ul_pres Prescaler value.
+ */
+void pmc_mck_set_prescaler(uint32_t ul_pres)
+{
+	PMC->PMC_MCKR =
+			(PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
+}
+
+/**
+ * \brief Set the source of the MCK.
+ *
+ * \param ul_source Source selection value.
+ */
+void pmc_mck_set_source(uint32_t ul_source)
+{
+	PMC->PMC_MCKR =
+			(PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source;
+	while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
+}
+
+/**
+ * \brief Switch master clock source selection to slow clock.
+ *
+ * \param ul_pres Processor clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)
+{
+	uint32_t ul_timeout;
+
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_SLOW_CLK;
+	for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); --ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
+	for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); --ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * \brief Switch master clock source selection to main clock.
+ *
+ * \param ul_pres Processor clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)
+{
+	uint32_t ul_timeout;
+
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
+			PMC_MCKR_CSS_MAIN_CLK;
+	for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+			--ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
+	for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+			--ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * \brief Switch master clock source selection to PLLA clock.
+ *
+ * \param ul_pres Processor clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)
+{
+	uint32_t ul_timeout;
+
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
+	for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+			--ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
+			PMC_MCKR_CSS_PLLA_CLK;
+
+	for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+			--ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+#if (SAM3S_SERIES || SAM4S_SERIES)
+/**
+ * \brief Switch master clock source selection to PLLB clock.
+ *
+ * \param ul_pres Processor clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres)
+{
+	uint32_t ul_timeout;
+
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
+	for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+			--ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
+			PMC_MCKR_CSS_PLLB_CLK;
+	for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+			--ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+#if (SAM3XA_SERIES || SAM3U_SERIES)
+/**
+ * \brief Switch master clock source selection to UPLL clock.
+ *
+ * \param ul_pres Processor clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres)
+{
+	uint32_t ul_timeout;
+
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
+	for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+			--ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
+			PMC_MCKR_CSS_UPLL_CLK;
+	for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
+			--ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+/**
+ * \brief Switch slow clock source selection to external 32k (Xtal or Bypass).
+ *
+ * \note This function disables the PLLs.
+ *
+ * \note Switching SCLK back to 32krc is only possible by shutting down the VDDIO
+ * power supply.
+ *
+ * \param ul_bypass 0 for Xtal, 1 for bypass.
+ */
+void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass)
+{
+	/* Set Bypass mode if required */
+	if (ul_bypass == 1) {
+		SUPC->SUPC_MR |= SUPC_MR_KEY(SUPC_KEY_VALUE) |
+				SUPC_MR_OSCBYPASS;
+	}
+
+	SUPC->SUPC_CR |= SUPC_CR_KEY(SUPC_KEY_VALUE) | SUPC_CR_XTALSEL;
+}
+
+/**
+ * \brief Check if the external 32k Xtal is ready.
+ *
+ * \retval 1 External 32k Xtal is ready.
+ * \retval 0 External 32k Xtal is not ready.
+ */
+uint32_t pmc_osc_is_ready_32kxtal(void)
+{
+	return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL)
+			&& (PMC->PMC_SR & PMC_SR_OSCSELS));
+}
+
+/**
+ * \brief Switch main clock source selection to internal fast RC.
+ *
+ * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz).
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ * \retval 2 Invalid frequency.
+ */
+void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf)
+{
+	uint32_t ul_needXTEN = 0;
+
+	/* Enable Fast RC oscillator but DO NOT switch to RC now */
+	if (PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN) {
+		PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
+				PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN |
+				ul_moscrcf;
+	} else {
+		ul_needXTEN = 1;
+		PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
+				PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN |
+				CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST(PMC_XTAL_STARTUP_TIME) |
+				ul_moscrcf;
+	}
+
+	/* Wait the Fast RC to stabilize */
+	while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
+
+	/* Switch to Fast RC */
+	PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | PMC_CKGR_MOR_KEY_VALUE;
+
+	// BUG FIX : clock_example3_SAM3S_SERIES does not switch sclk->mainck with XT disabled.
+	if (ul_needXTEN) {
+		PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
+				PMC_CKGR_MOR_KEY_VALUE;
+	}
+}
+
+/**
+ * \brief Enable fast RC oscillator.
+ *
+ * \param ul_rc Fast RC oscillator(4/8/12Mhz).
+ */
+void pmc_osc_enable_fastrc(uint32_t ul_rc)
+{
+	/* Enable Fast RC oscillator but DO NOT switch to RC now. Keep MOSCSEL to 1 */
+	PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL |
+			CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCRCEN | ul_rc;
+	/* Wait the Fast RC to stabilize */
+	while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
+}
+
+/**
+ * \brief Disable the internal fast RC.
+ */
+void pmc_osc_disable_fastrc(void)
+{
+	/* Disable Fast RC oscillator */
+	PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN) | PMC_CKGR_MOR_KEY_VALUE;
+}
+
+/**
+ * \brief Switch main clock source selection to external Xtal/Bypass.
+ * The function may switch MCK to SCLK if MCK source is MAINCK to avoid any
+ * system crash.
+ *
+ * \note If used in Xtal mode, the Xtal is automatically enabled.
+ *
+ * \param ul_bypass 0 for Xtal, 1 for bypass.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+void pmc_switch_mainck_to_xtal(uint32_t ul_bypass)
+{
+	/* Enable Main Xtal oscillator */
+	if (ul_bypass) {
+		PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
+				PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTBY |
+				CKGR_MOR_MOSCSEL;
+	} else {
+		PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
+				PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTEN |
+				CKGR_MOR_MOSCXTST(PMC_XTAL_STARTUP_TIME);
+		/* Wait the Xtal to stabilize */
+		while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
+
+		PMC->CKGR_MOR |= PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL;
+	}
+}
+
+/**
+ * \brief Disable the external Xtal.
+ *
+ * \param ul_bypass 0 for Xtal, 1 for bypass.
+ */
+void pmc_osc_disable_xtal(uint32_t ul_bypass)
+{
+	/* Disable xtal oscillator */
+	if (ul_bypass) {
+		PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
+				PMC_CKGR_MOR_KEY_VALUE;
+	} else {
+		PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
+				PMC_CKGR_MOR_KEY_VALUE;
+	}
+}
+
+/**
+ * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one
+ * of Xtal, bypass or internal RC.
+ *
+ * \retval 1 Xtal is ready.
+ * \retval 0 Xtal is not ready.
+ */
+uint32_t pmc_osc_is_ready_mainck(void)
+{
+	return PMC->PMC_SR & PMC_SR_MOSCSELS;
+}
+
+/**
+ * \brief Enable PLLA clock.
+ *
+ * \param mula PLLA multiplier.
+ * \param pllacount PLLA counter.
+ * \param diva Divider.
+ */
+void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)
+{
+	pmc_disable_pllack(); // Hardware BUG FIX : first disable the PLL to unlock the lock!
+	// It occurs when re-enabling the PLL with the same parameters.
+
+	PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) |
+			CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
+	while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);
+}
+
+/**
+ * \brief Disable PLLA clock.
+ */
+void pmc_disable_pllack(void)
+{
+	PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);
+}
+
+/**
+ * \brief Is PLLA locked?
+ *
+ * \retval 0 Not locked.
+ * \retval 1 Locked.
+ */
+uint32_t pmc_is_locked_pllack(void)
+{
+	return (PMC->PMC_SR & PMC_SR_LOCKA);
+}
+
+#if (SAM3S_SERIES || SAM4S_SERIES)
+/**
+ * \brief Enable PLLB clock.
+ *
+ * \param mulb PLLB multiplier.
+ * \param pllbcount PLLB counter.
+ * \param divb Divider.
+ */
+void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)
+{
+	pmc_disable_pllbck(); // Hardware BUG FIX : first disable the PLL to unlock the lock!
+	// It occurs when re-enabling the PLL with the same parameters.
+	PMC->CKGR_PLLBR =
+			CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount)
+			| CKGR_PLLBR_MULB(mulb);
+	while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0);
+}
+
+/**
+ * \brief Disable PLLB clock.
+ */
+void pmc_disable_pllbck(void)
+{
+	PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);
+}
+
+/**
+ * \brief Is PLLB locked?
+ *
+ * \retval 0 Not locked.
+ * \retval 1 Locked.
+ */
+uint32_t pmc_is_locked_pllbck(void)
+{
+	return (PMC->PMC_SR & PMC_SR_LOCKB);
+}
+#endif
+
+#if (SAM3XA_SERIES || SAM3U_SERIES)
+/**
+ * \brief Enable UPLL clock.
+ */
+void pmc_enable_upll_clock(void)
+{
+	PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN;
+
+	/* Wait UTMI PLL Lock Status */
+	while (!(PMC->PMC_SR & PMC_SR_LOCKU));
+}
+
+/**
+ * \brief Disable UPLL clock.
+ */
+void pmc_disable_upll_clock(void)
+{
+	PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
+}
+
+/**
+ * \brief Is UPLL locked?
+ *
+ * \retval 0 Not locked.
+ * \retval 1 Locked.
+ */
+uint32_t pmc_is_locked_upll(void)
+{
+	return (PMC->PMC_SR & PMC_SR_LOCKU);
+}
+#endif
+
+/**
+ * \brief Enable the specified peripheral clock.
+ *
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
+ *
+ * \param ul_id Peripheral ID (ID_xxx).
+ *
+ * \retval 0 Success.
+ * \retval 1 Invalid parameter.
+ */
+uint32_t pmc_enable_periph_clk(uint32_t ul_id)
+{
+	if (ul_id > MAX_PERIPH_ID) {
+		return 1;
+	}
+
+	if (ul_id < 32) {
+		if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) {
+			PMC->PMC_PCER0 = 1 << ul_id;
+		}
+#if (SAM3S_SERIES || SAM3XA_SERIES || SAM4S_SERIES)
+	} else {
+		ul_id -= 32;
+		if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) {
+			PMC->PMC_PCER1 = 1 << ul_id;
+		}
+#endif
+	}
+
+	return 0;
+}
+
+/**
+ * \brief Disable the specified peripheral clock.
+ *
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
+ *
+ * \param ul_id Peripheral ID (ID_xxx).
+ *
+ * \retval 0 Success.
+ * \retval 1 Invalid parameter.
+ */
+uint32_t pmc_disable_periph_clk(uint32_t ul_id)
+{
+	if (ul_id > MAX_PERIPH_ID) {
+		return 1;
+	}
+
+	if (ul_id < 32) {
+		if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) {
+			PMC->PMC_PCDR0 = 1 << ul_id;
+		}
+#if (SAM3S_SERIES || SAM3XA_SERIES || SAM4S_SERIES)
+	} else {
+		ul_id -= 32;
+		if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) {
+			PMC->PMC_PCDR1 = 1 << ul_id;
+		}
+#endif
+	}
+	return 0;
+}
+
+/**
+ * \brief Enable all peripheral clocks.
+ */
+void pmc_enable_all_periph_clk(void)
+{
+	PMC->PMC_PCER0 = PMC_MASK_STATUS0;
+	while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0);
+
+#if (SAM3S_SERIES || SAM3XA_SERIES || SAM4S_SERIES)
+	PMC->PMC_PCER1 = PMC_MASK_STATUS1;
+	while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1);
+#endif
+}
+
+/**
+ * \brief Disable all peripheral clocks.
+ */
+void pmc_disable_all_periph_clk(void)
+{
+	PMC->PMC_PCDR0 = PMC_MASK_STATUS0;
+	while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0);
+
+#if (SAM3S_SERIES || SAM3XA_SERIES || SAM4S_SERIES)
+	PMC->PMC_PCDR1 = PMC_MASK_STATUS1;
+	while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0);
+#endif
+}
+
+/**
+ * \brief Check if the specified peripheral clock is enabled.
+ *
+ * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
+ *
+ * \param ul_id Peripheral ID (ID_xxx).
+ *
+ * \retval 0 Peripheral clock is disabled or unknown.
+ * \retval 1 Peripheral clock is enabled.
+ */
+uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id)
+{
+	if (ul_id > MAX_PERIPH_ID) {
+		return 0;
+	}
+
+#if (SAM3S_SERIES || SAM3XA_SERIES || SAM4S_SERIES)
+	if (ul_id < 32) {
+#endif
+		if ((PMC->PMC_PCSR0 & (1u << ul_id))) {
+			return 1;
+		} else {
+			return 0;
+		}
+#if (SAM3S_SERIES || SAM3XA_SERIES || SAM4S_SERIES)
+	} else {
+		ul_id -= 32;
+		if ((PMC->PMC_PCSR1 & (1u << ul_id))) {
+			return 1;
+		} else {
+			return 0;
+		}
+	}
+#endif
+}
+
+/**
+ * \brief Set the prescaler for the specified programmable clock.
+ *
+ * \param ul_id Peripheral ID.
+ * \param ul_pres Prescaler value.
+ */
+void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres)
+{
+	PMC->PMC_PCK[ul_id] =
+			(PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres;
+	while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
+			&& !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
+}
+
+/**
+ * \brief Set the source oscillator for the specified programmable clock.
+ *
+ * \param ul_id Peripheral ID.
+ * \param ul_source Source selection value.
+ */
+void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source)
+{
+	PMC->PMC_PCK[ul_id] =
+			(PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source;
+	while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
+			&& !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
+}
+
+/**
+ * \brief Switch programmable clock source selection to slow clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ * \param ul_pres Programmable clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres)
+{
+	uint32_t ul_timeout;
+
+	PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres;
+	for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
+			--ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * \brief Switch programmable clock source selection to main clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ * \param ul_pres Programmable clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)
+{
+	uint32_t ul_timeout;
+
+	PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres;
+	for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
+			--ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * \brief Switch programmable clock source selection to PLLA clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ * \param ul_pres Programmable clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres)
+{
+	uint32_t ul_timeout;
+
+	PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres;
+	for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
+			--ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+#if (SAM3S_SERIES || SAM4S_SERIES)
+/**
+ * \brief Switch programmable clock source selection to PLLB clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ * \param ul_pres Programmable clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres)
+{
+	uint32_t ul_timeout;
+
+	PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres;
+	for (ul_timeout = PMC_TIMEOUT;
+			!(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
+			--ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+#if (SAM3XA_SERIES || SAM3U_SERIES)
+/**
+ * \brief Switch programmable clock source selection to UPLL clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ * \param ul_pres Programmable clock prescaler.
+ *
+ * \retval 0 Success.
+ * \retval 1 Timeout error.
+ */
+uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres)
+{
+	uint32_t ul_timeout;
+
+	PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres;
+	for (ul_timeout = PMC_TIMEOUT;
+			!(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
+			--ul_timeout) {
+		if (ul_timeout == 0) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+/**
+ * \brief Enable the specified programmable clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ */
+void pmc_enable_pck(uint32_t ul_id)
+{
+	PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id;
+}
+
+/**
+ * \brief Disable the specified programmable clock.
+ *
+ * \param ul_id Id of the programmable clock.
+ */
+void pmc_disable_pck(uint32_t ul_id)
+{
+	PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id;
+}
+
+/**
+ * \brief Enable all programmable clocks.
+ */
+void pmc_enable_all_pck(void)
+{
+	PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2;
+}
+
+/**
+ * \brief Disable all programmable clocks.
+ */
+void pmc_disable_all_pck(void)
+{
+	PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2;
+}
+
+/**
+ * \brief Check if the specified programmable clock is enabled.
+ *
+ * \param ul_id Id of the programmable clock.
+ *
+ * \retval 0 Programmable clock is disabled or unknown.
+ * \retval 1 Programmable clock is enabled.
+ */
+uint32_t pmc_is_pck_enabled(uint32_t ul_id)
+{
+	if (ul_id > 2) {
+		return 0;
+	}
+
+	return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id));
+}
+
+#if (SAM3S_SERIES || SAM3XA_SERIES || SAM4S_SERIES)
+/**
+ * \brief Switch UDP (USB) clock source selection to PLLA clock.
+ *
+ * \param ul_usbdiv Clock divisor.
+ */
+void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv)
+{
+	PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
+}
+#endif
+
+#if (SAM3S_SERIES || SAM4S_SERIES)
+/**
+ * \brief Switch UDP (USB) clock source selection to PLLB clock.
+ *
+ * \param ul_usbdiv Clock divisor.
+ */
+void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv)
+{
+	PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
+}
+#endif
+
+#if (SAM3XA_SERIES)
+/**
+ * \brief Switch UDP (USB) clock source selection to UPLL clock.
+ *
+ * \param dw_usbdiv Clock divisor.
+ */
+void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv)
+{
+	PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv);
+}
+#endif
+
+#if (SAM3S_SERIES || SAM3XA_SERIES || SAM4S_SERIES)
+/**
+ * \brief Enable UDP (USB) clock.
+ */
+void pmc_enable_udpck(void)
+{
+# if (SAM3S_SERIES || SAM4S_SERIES)
+	PMC->PMC_SCER = PMC_SCER_UDP;
+# else
+	PMC->PMC_SCER = PMC_SCER_UOTGCLK;
+# endif
+}
+
+/**
+ * \brief Disable UDP (USB) clock.
+ */
+void pmc_disable_udpck(void)
+{
+# if (SAM3S_SERIES || SAM4S_SERIES)
+	PMC->PMC_SCDR = PMC_SCDR_UDP;
+# else
+	PMC->PMC_SCDR = PMC_SCDR_UOTGCLK;
+# endif
+}
+#endif
+
+/**
+ * \brief Enable PMC interrupts.
+ *
+ * \param ul_sources Interrupt sources bit map.
+ */
+void pmc_enable_interrupt(uint32_t ul_sources)
+{
+	PMC->PMC_IER = ul_sources;
+}
+
+/**
+ * \brief Disable PMC interrupts.
+ *
+ * \param ul_sources Interrupt sources bit map.
+ */
+void pmc_disable_interrupt(uint32_t ul_sources)
+{
+	PMC->PMC_IDR = ul_sources;
+}
+
+/**
+ * \brief Get PMC interrupt mask.
+ *
+ * \return The interrupt mask value.
+ */
+uint32_t pmc_get_interrupt_mask(void)
+{
+	return PMC->PMC_IMR;
+}
+
+/**
+ * \brief Get current status.
+ *
+ * \return The current PMC status.
+ */
+uint32_t pmc_get_status(void)
+{
+	return PMC->PMC_SR;
+}
+
+/**
+ * \brief Set the wake-up inputs for fast startup mode registers (event generation).
+ *
+ * \param ul_inputs Wake up inputs to enable.
+ */
+void pmc_set_fast_startup_input(uint32_t ul_inputs)
+{
+	ul_inputs &= (~ PMC_FAST_STARTUP_Msk);
+	PMC->PMC_FSMR |= ul_inputs;
+}
+
+/**
+ * \brief Clear the wake-up inputs for fast startup mode registers (remove event generation).
+ *
+ * \param ul_inputs Wake up inputs to disable.
+ */
+void pmc_clr_fast_startup_input(uint32_t ul_inputs)
+{
+	ul_inputs &= (~ PMC_FAST_STARTUP_Msk);
+	PMC->PMC_FSMR &= ~ul_inputs;
+}
+
+/**
+ * \brief Enable Sleep Mode.
+ * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0)
+ *
+ * \param uc_type 0 for wait for interrupt, 1 for wait for event.
+ */
+void pmc_enable_sleepmode(uint8_t uc_type)
+{
+	PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode
+	SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep
+
+	if (uc_type == 0) {
+		__WFI();
+	} else {
+		__WFE();
+	}
+}
+
+/**
+ * \brief Enable Wait Mode.
+ * Enter condition: WFE + (SLEEPDEEP bit = 0) + (LPM bit = 1)
+ */
+void pmc_enable_waitmode(void)
+{
+	uint32_t i;
+
+	PMC->PMC_FSMR |= PMC_FSMR_LPM; // Enter Wait mode
+	SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep
+	__WFE();
+
+	/* Waiting for MOSCRCEN bit cleared is strongly recommended
+	 * to ensure that the core will not execute undesired instructions
+	 */
+	for (i = 0; i < 500; i++) {
+		__NOP();
+	}
+	while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
+}
+
+/**
+ * \brief Enable Backup Mode.
+ * Enter condition: WFE + (SLEEPDEEP bit = 1)
+ */
+void pmc_enable_backupmode(void)
+{
+	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+	__WFE();
+}
+
+/**
+ * \brief Enable or disable write protect of PMC registers.
+ *
+ * \param ul_enable 1 to enable, 0 to disable.
+ */
+void pmc_set_writeprotect(uint32_t ul_enable)
+{
+	if (ul_enable) {
+		PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE | PMC_WPMR_WPEN;
+	} else {
+		PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE;
+	}
+}
+
+/**
+ * \brief Return write protect status.
+ *
+ * \retval 0 Protection disabled.
+ * \retval 1 Protection enabled.
+ */
+uint32_t pmc_get_writeprotect_status(void)
+{
+	return PMC->PMC_WPMR & PMC_WPMR_WPEN;
+}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
diff --git a/hardware/digistump/sam/system/libsam/source/pwmc.c b/hardware/digistump/sam/system/libsam/source/pwmc.c
new file mode 100644
index 0000000..7d816c4
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/pwmc.c
@@ -0,0 +1,624 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup pwm_module Working with PWM
+ * The PWM driver provides the interface to configure and use the PWM
+ * peripheral.
+ *
+ * The PWM macrocell controls square output waveforms of 4 channels.
+ * Characteristics of output waveforms such as period, duty-cycle,
+ * dead-time can be configured.\n
+ * Some of PWM channels can be linked together as synchronous ul_channel and
+ * duty-cycle of synchronous channels can be updated by PDC automaticly.
+ *
+ * Before enabling the channels, they must have been configured first.
+ * The main settings include:
+ * 
    
+ * 
  • Configuration of the clock generator.
    • 
+ * 
  • Selection of the clock for each ul_channel.
    • 
+ * 
  • Configuration of output waveform characteristics, such as period, duty-cycle etc.
    • 
+ * 
  • Configuration for synchronous channels if needed.
    • 
+ *    - Selection of the synchronous channels.
+ *    - Selection of the moment when the WRDY flag and the corresponding PDC
+ *      transfer request are set (PTRM and PTRCS in the PWM_SCM register).
+ *    - Configuration of the update mode (UPDM in the PWM_SCM register).
+ *    - Configuration of the update period (UPR in the PWM_SCUP register).
+ * 

+ *
+ * After the channels is enabled, the user must use respective update registers
+ * to change the wave characteristics to prevent unexpected output waveform.
+ * i.e. PWM_CDTYUPDx register should be used if user want to change duty-cycle
+ * when the ul_channel is enabled.
+ *
+ * For more accurate information, please look at the PWM section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref pwmc.c\n
+ * \ref pwmc.h.\n
+ */
+/*@{*/
+/*@}*/
+
+/**
+ * \file
+ *
+ * Implementation of the Pulse Width Modulation Controller (PWM) peripheral.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+#include 
+
+/*----------------------------------------------------------------------------
+ *         Local functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Finds a prescaler/divisor couple to generate the desired frequency
+ * from MCK.
+ *
+ * Returns the value to enter in PWM_CLK or 0 if the configuration cannot be
+ * met.
+ *
+ * \param frequency  Desired frequency in Hz.
+ * \param mck  Master clock frequency in Hz.
+ */
+static uint16_t FindClockConfiguration(
+    uint32_t frequency,
+    uint32_t mck)
+{
+    uint32_t divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024};
+    uint8_t divisor = 0;
+    uint32_t prescaler;
+
+    assert(frequency < mck);
+
+    /* Find prescaler and divisor values */
+    prescaler = (mck / divisors[divisor]) / frequency;
+    while ((prescaler > 255) && (divisor < 11)) {
+
+        divisor++;
+        prescaler = (mck / divisors[divisor]) / frequency;
+    }
+
+    /* Return result */
+    if ( divisor < 11 )
+    {
+//        TRACE_DEBUG( "Found divisor=%u and prescaler=%u for freq=%uHz\n\r", divisors[divisor], prescaler, frequency ) ;
+
+        return prescaler | (divisor << 8) ;
+    }
+    else
+    {
+        return 0 ;
+    }
+}
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Configures PWM a ul_channel with the given parameters, basic configure function.
+ *
+ * The PWM controller must have been clocked in the PMC prior to calling this
+ * function.
+ * Beware: this function disables the ul_channel. It waits until disable is effective.
+ *
+ * \param ul_channel  Channel number.
+ * \param prescaler  Channel prescaler.
+ * \param alignment  Channel alignment.
+ * \param polarity  Channel polarity.
+ */
+void PWMC_ConfigureChannel( Pwm* pPwm, uint32_t ul_channel, uint32_t prescaler, uint32_t alignment, uint32_t polarity )
+{
+    pPwm->PWM_CH_NUM[0].PWM_CMR = 1;
+
+//    assert(prescaler < PWM_CMR0_CPRE_MCKB);
+    assert((alignment & (uint32_t)~PWM_CMR_CALG) == 0);
+    assert((polarity & (uint32_t)~PWM_CMR_CPOL) == 0);
+
+    /* Disable ul_channel (effective at the end of the current period) */
+    if ((pPwm->PWM_SR & (1 << ul_channel)) != 0) {
+        pPwm->PWM_DIS = 1 << ul_channel;
+        while ((pPwm->PWM_SR & (1 << ul_channel)) != 0);
+    }
+
+    /* Configure ul_channel */
+    pPwm->PWM_CH_NUM[ul_channel].PWM_CMR = prescaler | alignment | polarity;
+}
+
+/**
+ * \brief Configures PWM a ul_channel with the given parameters, extend configure function.
+ *
+ * The PWM controller must have been clocked in the PMC prior to calling this
+ * function.
+ * Beware: this function disables the ul_channel. It waits until disable is effective.
+ *
+ * \param ul_channel            Channel number.
+ * \param prescaler          Channel prescaler.
+ * \param alignment          Channel alignment.
+ * \param polarity           Channel polarity.
+ * \param countEventSelect   Channel counter event selection.
+ * \param DTEnable           Channel dead time generator enable.
+ * \param DTHInverte         Channel Dead-Time PWMHx output Inverted.
+ * \param DTLInverte         Channel Dead-Time PWMHx output Inverted.
+ */
+void PWMC_ConfigureChannelExt( Pwm* pPwm, uint32_t ul_channel, uint32_t prescaler, uint32_t alignment, uint32_t polarity,
+                               uint32_t countEventSelect, uint32_t DTEnable, uint32_t DTHInverte, uint32_t DTLInverte )
+{
+//    assert(prescaler < PWM_CMR0_CPRE_MCKB);
+    assert((alignment & (uint32_t)~PWM_CMR_CALG) == 0);
+    assert((polarity & (uint32_t)~PWM_CMR_CPOL) == 0);
+    assert((countEventSelect & (uint32_t)~PWM_CMR_CES) == 0);
+    assert((DTEnable & (uint32_t)~PWM_CMR_DTE) == 0);
+    assert((DTHInverte & (uint32_t)~PWM_CMR_DTHI) == 0);
+    assert((DTLInverte & (uint32_t)~PWM_CMR_DTLI) == 0);
+
+    /* Disable ul_channel (effective at the end of the current period) */
+    if ((pPwm->PWM_SR & (1 << ul_channel)) != 0) {
+        pPwm->PWM_DIS = 1 << ul_channel;
+        while ((pPwm->PWM_SR & (1 << ul_channel)) != 0);
+    }
+
+    /* Configure ul_channel */
+    pPwm->PWM_CH_NUM[ul_channel].PWM_CMR = prescaler | alignment | polarity |
+        countEventSelect | DTEnable | DTHInverte | DTLInverte;
+}
+
+/**
+ * \brief Configures PWM clocks A & B to run at the given frequencies.
+ *
+ * This function finds the best MCK divisor and prescaler values automatically.
+ *
+ * \param clka  Desired clock A frequency (0 if not used).
+ * \param clkb  Desired clock B frequency (0 if not used).
+ * \param mck  Master clock frequency.
+ */
+void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck)
+{
+    uint32_t mode = 0;
+    uint32_t result;
+
+    /* Clock A */
+    if (clka != 0) {
+
+        result = FindClockConfiguration(clka, mck);
+        assert( result != 0 ) ;
+        mode |= result;
+    }
+
+    /* Clock B */
+    if (clkb != 0) {
+
+        result = FindClockConfiguration(clkb, mck);
+        assert( result != 0 ) ;
+        mode |= (result << 16);
+    }
+
+    /* Configure clocks */
+//    TRACE_DEBUG( "Setting PWM_CLK = 0x%08X\n\r", mode ) ;
+    PWM->PWM_CLK = mode;
+}
+
+/**
+ * \brief Sets the period value used by a PWM ul_channel.
+ *
+ * This function writes directly to the CPRD register if the ul_channel is disabled;
+ * otherwise, it uses the update register CPRDUPD.
+ *
+ * \param ul_channel Channel number.
+ * \param period  Period value.
+ */
+void PWMC_SetPeriod( Pwm* pPwm, uint32_t ul_channel, uint16_t period)
+{
+    /* If ul_channel is disabled, write to CPRD */
+    if ((pPwm->PWM_SR & (1 << ul_channel)) == 0) {
+
+        pPwm->PWM_CH_NUM[ul_channel].PWM_CPRD = period;
+    }
+    /* Otherwise use update register */
+    else {
+
+        pPwm->PWM_CH_NUM[ul_channel].PWM_CPRDUPD = period;
+    }
+}
+
+/**
+ * \brief Sets the duty cycle used by a PWM ul_channel.
+ * This function writes directly to the CDTY register if the ul_channel is disabled;
+ * otherwise it uses the update register CDTYUPD.
+ * Note that the duty cycle must always be inferior or equal to the ul_channel
+ * period.
+ *
+ * \param ul_channel  Channel number.
+ * \param duty     Duty cycle value.
+ */
+void PWMC_SetDutyCycle( Pwm* pPwm, uint32_t ul_channel, uint16_t duty)
+{
+    assert(duty <= pPwm->PWM_CH_NUM[ul_channel].PWM_CPRD);
+
+    /* If ul_channel is disabled, write to CDTY */
+    if ((pPwm->PWM_SR & (1 << ul_channel)) == 0) {
+
+        pPwm->PWM_CH_NUM[ul_channel].PWM_CDTY = duty;
+    }
+    /* Otherwise use update register */
+    else {
+
+        pPwm->PWM_CH_NUM[ul_channel].PWM_CDTYUPD = duty;
+    }
+}
+
+/**
+ * \brief Sets the dead time used by a PWM ul_channel.
+ * This function writes directly to the DT register if the ul_channel is disabled;
+ * otherwise it uses the update register DTUPD.
+ * Note that the dead time must always be inferior or equal to the ul_channel
+ * period.
+ *
+ * \param ul_channel  Channel number.
+ * \param timeH    Dead time value for PWMHx output.
+ * \param timeL    Dead time value for PWMLx output.
+ */
+void PWMC_SetDeadTime( Pwm* pPwm, uint32_t ul_channel, uint16_t timeH, uint16_t timeL)
+{
+    assert(timeH <= pPwm->PWM_CH_NUM[ul_channel].PWM_CPRD);
+    assert(timeL <= pPwm->PWM_CH_NUM[ul_channel].PWM_CPRD);
+
+    /* If ul_channel is disabled, write to DT */
+    if ((pPwm->PWM_SR & (1 << ul_channel)) == 0) {
+
+        pPwm->PWM_CH_NUM[ul_channel].PWM_DT = timeH | (timeL << 16);
+    }
+    /* Otherwise use update register */
+    else {
+        pPwm->PWM_CH_NUM[ul_channel].PWM_DTUPD = timeH | (timeL << 16);
+    }
+}
+
+/**
+ * \brief Configures Syncronous ul_channel with the given parameters.
+ * Beware: At this time, the channels should be disabled.
+ *
+ * \param channels                 Bitwise OR of Syncronous channels.
+ * \param updateMode               Syncronous ul_channel update mode.
+ * \param requestMode              PDC transfer request mode.
+ * \param requestComparisonSelect  PDC transfer request comparison selection.
+ */
+void PWMC_ConfigureSyncChannel( Pwm* pPwm, uint32_t ul_channels, uint32_t updateMode, uint32_t requestMode, uint32_t requestComparisonSelect )
+{
+    pPwm->PWM_SCM = ul_channels | updateMode | requestMode | requestComparisonSelect;
+}
+
+/**
+ * \brief Sets the update period of the synchronous channels.
+ * This function writes directly to the SCUP register if the ul_channel #0 is disabled;
+ * otherwise it uses the update register SCUPUPD.
+ *
+ * \param period   update period.
+ */
+void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period )
+{
+    /* If ul_channel is disabled, write to SCUP */
+    if ((pPwm->PWM_SR & (1 << 0)) == 0) {
+
+        pPwm->PWM_SCUP = period;
+    }
+    /* Otherwise use update register */
+    else {
+
+        pPwm->PWM_SCUPUPD = period;
+    }
+}
+
+/**
+ * \brief Sets synchronous channels update unlock.
+ *
+ * Note: If the UPDM field is set to 0, writing the UPDULOCK bit to 1
+ * triggers the update of the period value, the duty-cycle and
+ * the dead-time values of synchronous channels at the beginning
+ * of the next PWM period. If the field UPDM is set to 1 or 2,
+ * writing the UPDULOCK bit to 1 triggers only the update of
+ * the period value and of the dead-time values of synchronous channels.
+ * This bit is automatically reset when the update is done.
+ */
+void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm )
+{
+    pPwm->PWM_SCUC = PWM_SCUC_UPDULOCK;
+}
+
+/**
+ * \brief Enables the given PWM ul_channel.
+ *
+ * This does NOT enable the corresponding pin;this must be done in the user code.
+ *
+ * \param ul_channel  Channel number.
+ */
+void PWMC_EnableChannel( Pwm* pPwm, uint32_t ul_channel)
+{
+    pPwm->PWM_ENA = 1 << ul_channel;
+}
+
+/**
+ * \brief Disables the given PWM ul_channel.
+ *
+ * Beware, ul_channel will be effectively disabled at the end of the current period.
+ * Application can check ul_channel is disabled using the following wait loop:
+ * while ((PWM->PWM_SR & (1 << ul_channel)) != 0);
+ *
+ * \param ul_channel  Channel number.
+ */
+void PWMC_DisableChannel( Pwm* pPwm, uint32_t ul_channel)
+{
+    pPwm->PWM_DIS = 1 << ul_channel;
+}
+
+/**
+ * \brief Enables the period interrupt for the given PWM ul_channel.
+ *
+ * \param ul_channel  Channel number.
+ */
+void PWMC_EnableChannelIt( Pwm* pPwm, uint32_t ul_channel)
+{
+    pPwm->PWM_IER1 = 1 << ul_channel;
+}
+
+/**
+ * \brief Disables the period interrupt for the given PWM ul_channel.
+ *
+ * \param ul_channel  Channel number.
+ */
+void PWMC_DisableChannelIt( Pwm* pPwm, uint32_t ul_channel)
+{
+    pPwm->PWM_IDR1 = 1 << ul_channel;
+}
+
+/**
+ * \brief Enables the selected interrupts sources on a PWMC peripheral.
+ *
+ * \param sources1  Bitwise OR of selected interrupt sources of PWM_IER1.
+ * \param sources2  Bitwise OR of selected interrupt sources of PWM_IER2.
+ */
+void PWMC_EnableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2)
+{
+    pPwm->PWM_IER1 = sources1;
+    pPwm->PWM_IER2 = sources2;
+}
+
+/**
+ * \brief Disables the selected interrupts sources on a PWMC peripheral.
+ *
+ * \param sources1  Bitwise OR of selected interrupt sources of PWM_IDR1.
+ * \param sources2  Bitwise OR of selected interrupt sources of PWM_IDR2.
+ */
+void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2)
+{
+    pPwm->PWM_IDR1 = sources1;
+    pPwm->PWM_IDR2 = sources2;
+}
+
+/**
+ * \brief Sends the contents of buffer through a PWMC peripheral, using the PDC to
+ * take care of the transfer.
+ *
+ * Note: Duty cycle of syncronous channels can update by PDC
+ *       when the field UPDM (Update Mode) in the PWM_SCM register is set to 2.
+ *
+ * \param pwmc      Pointer to an Pwm instance.
+ * \param pvBuffer  Data buffer to send.
+ * \param length    Length of the data buffer.
+ */
+uint8_t PWMC_WriteBuffer( Pwm *pwmc, void* pvBuffer, uint32_t length)
+{
+    /* Check if first bank is free */
+    if (pwmc->PWM_TCR == 0) {
+
+        pwmc->PWM_TPR = (uint32_t) pvBuffer;
+        pwmc->PWM_TCR = length;
+        pwmc->PWM_PTCR = PERIPH_PTCR_TXTEN;
+        return 1;
+    }
+    /* Check if second bank is free */
+    else if (pwmc->PWM_TNCR == 0) {
+
+        pwmc->PWM_TNPR = (uint32_t) pvBuffer;
+        pwmc->PWM_TNCR = length;
+        return 1;
+    }
+
+    /* No free banks */
+    return 0;
+}
+
+/**
+ * \brief Set PWM output override value.
+ *
+ * \param value  Bitwise OR of output override value.
+ */
+void PWMC_SetOverrideValue( Pwm* pPwm, uint32_t value)
+{
+    pPwm->PWM_OOV = value;
+}
+
+/**
+ * \brief Enalbe override output.
+ *
+ * \param value  Bitwise OR of output selection.
+ * \param sync   0: enable the output asyncronously, 1: enable it syncronously
+ */
+void PWMC_EnableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync)
+{
+    if (sync) {
+
+        pPwm->PWM_OSSUPD = value;
+    } else {
+
+        pPwm->PWM_OSS = value;
+    }
+}
+
+/**
+ * \brief Disalbe override output.
+ *
+ * \param value  Bitwise OR of output selection.
+ * \param sync   0: enable the output asyncronously, 1: enable it syncronously
+ */
+void PWMC_DisableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync)
+{
+    if (sync) {
+
+        pPwm->PWM_OSCUPD = value;
+    } else {
+
+        pPwm->PWM_OSC = value;
+    }
+}
+
+/**
+ * \brief Set PWM fault mode.
+ *
+ * \param mode  Bitwise OR of fault mode.
+ */
+void PWMC_SetFaultMode( Pwm* pPwm, uint32_t mode)
+{
+    pPwm->PWM_FMR = mode;
+}
+
+/**
+ * \brief PWM fault clear.
+ *
+ * \param fault  Bitwise OR of fault to clear.
+ */
+void PWMC_FaultClear( Pwm* pPwm, uint32_t fault)
+{
+    pPwm->PWM_FCR = fault;
+}
+
+/**
+ * \brief Set PWM fault protection value.
+ *
+ * \param value  Bitwise OR of fault protection value.
+ */
+void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value)
+{
+    pPwm->PWM_FPV = value;
+}
+
+/**
+ * \brief Enable PWM fault protection.
+ *
+ * \param value  Bitwise OR of FPEx[y].
+ */
+void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t ul_channel, uint32_t ul_value)
+{
+	/* Fault Protection Enable Register */
+	uint32_t ul_fault_enable_reg = 0;
+
+#if (SAM3XA_SERIES)
+	if (ul_channel < 4)
+  {
+		ul_channel *= 8;
+		ul_fault_enable_reg = pPwm->PWM_FPE1;
+		ul_fault_enable_reg &= ~(0xFF << ul_channel);
+		ul_fault_enable_reg |= (ul_value << ul_channel);
+		pPwm->PWM_FPE1 = ul_fault_enable_reg;
+	}
+  else
+  {
+		ul_channel -= 4;
+		ul_channel *= 8;
+		ul_fault_enable_reg = pPwm->PWM_FPE2;
+		ul_fault_enable_reg &= ~(0xFF << ul_channel);
+		ul_fault_enable_reg |= (ul_value << ul_channel);
+		pPwm->PWM_FPE2 = ul_fault_enable_reg;
+	}
+#endif
+
+#if (SAM3U_SERIES || SAM3S_SERIES || SAM3SD8_SERIES || SAM4S_SERIES)
+	ul_channel *= 8;
+	ul_fault_enable_reg = pPwm->PWM_FPE;
+	ul_fault_enable_reg &= ~(0xFF << ul_channel);
+	ul_fault_enable_reg |= (ul_value << ul_channel);
+	pPwm->PWM_FPE = ul_fault_enable_reg;
+#endif
+}
+
+/**
+ * \brief Configure comparison unit.
+ *
+ * \param x     comparison x index
+ * \param value comparison x value.
+ * \param mode  comparison x mode
+ */
+void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, uint32_t value, uint32_t mode)
+{
+    assert(x < 8);
+
+    /* If ul_channel is disabled, write to CMPxM & CMPxV */
+    if ((pPwm->PWM_SR & (1 << 0)) == 0) {
+        pPwm->PWM_CMP[x].PWM_CMPM = mode;
+        pPwm->PWM_CMP[x].PWM_CMPV = value;
+    }
+    /* Otherwise use update register */
+    else {
+        pPwm->PWM_CMP[x].PWM_CMPMUPD = mode;
+        pPwm->PWM_CMP[x].PWM_CMPVUPD = value;
+    }
+}
+
+/**
+ * \brief Configure event line mode.
+ *
+ * \param x    Line x
+ * \param mode Bitwise OR of line mode selection
+ */
+void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode)
+{
+    assert(x < 2);
+
+    if (x == 0)
+    {
+        pPwm->PWM_ELMR[0] = mode;
+    }
+    else
+    {
+        if (x == 1)
+        {
+            pPwm->PWM_ELMR[1] = mode;
+        }
+    }
+}
diff --git a/hardware/digistump/sam/system/libsam/source/rstc.c b/hardware/digistump/sam/system/libsam/source/rstc.c
new file mode 100644
index 0000000..d911c1d
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/rstc.c
@@ -0,0 +1,193 @@
+/**
+ * \file
+ *
+ * \brief Reset Controller (RSTC) driver for SAM.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+ 
+#include "rstc.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/**
+ * \defgroup sam_drivers_rstc_group Reset Controller (RSTC)
+ *
+ * Driver for the RSTC (Reset Controller). This driver provides access to the main 
+ * features of the Reset controller.
+ *
+ * @{
+ */
+
+#define RSTC_KEY  0xA5000000
+
+/**
+ * \brief Set external reset length.
+ *
+ * \param p_rstc Pointer to an RSTC instance.
+ * \param ul_length The length of external reset.
+ */
+void rstc_set_external_reset(Rstc *p_rstc, const uint32_t ul_length)
+{
+	uint32_t mode = p_rstc->RSTC_MR;
+
+	mode &= ~(RSTC_MR_ERSTL_Msk | RSTC_MR_KEY_Msk);
+	mode |= (RSTC_MR_ERSTL(ul_length) | RSTC_KEY);
+
+	p_rstc->RSTC_MR = mode;
+}
+
+/**
+ * \brief Enable user reset.
+ *
+ * \param p_rstc Pointer to an RSTC instance.
+ */
+void rstc_enable_user_reset(Rstc *p_rstc)
+{
+	uint32_t mode = p_rstc->RSTC_MR;
+
+	mode &= ~RSTC_MR_KEY_Msk;
+	mode |= (RSTC_MR_URSTEN | RSTC_KEY);
+
+	p_rstc->RSTC_MR = mode;
+}
+
+/**
+ * \brief Disable user reset.
+ *
+ * \param p_rstc Pointer to an RSTC instance.
+ */
+void rstc_disable_user_reset(Rstc *p_rstc)
+{
+	uint32_t mode = p_rstc->RSTC_MR;
+
+	mode &= ~(RSTC_MR_URSTEN | RSTC_MR_KEY_Msk);
+	mode |= RSTC_KEY;
+
+	p_rstc->RSTC_MR = mode;
+}
+
+/**
+ * \brief Enable user reset interrupt.
+ *
+ * \param p_rstc Pointer to an RSTC instance.
+ */
+void rstc_enable_user_reset_interrupt(Rstc *p_rstc)
+{
+	uint32_t mode = p_rstc->RSTC_MR;
+
+	mode &= ~RSTC_MR_KEY_Msk;
+	mode |= (RSTC_MR_URSTIEN | RSTC_KEY);
+
+	p_rstc->RSTC_MR = mode;
+}
+
+/**
+ * \brief Disable user reset interrupt.
+ *
+ * \param p_rstc Pointer to an RSTC instance.
+ */
+void rstc_disable_user_reset_interrupt(Rstc *p_rstc)
+{
+	uint32_t mode = p_rstc->RSTC_MR;
+
+	mode &= ~(RSTC_MR_URSTIEN | RSTC_MR_KEY_Msk);
+	mode |= RSTC_KEY;
+
+	p_rstc->RSTC_MR = mode;
+}
+
+/**
+ * \brief Perform software reset.
+ *
+ * \param p_rstc Pointer to an RSTC instance.
+ */
+void rstc_start_software_reset(Rstc *p_rstc)
+{
+	p_rstc->RSTC_CR = RSTC_KEY | RSTC_CR_PROCRST | RSTC_CR_PERRST;
+}
+
+/**
+ * \brief Asserts the NRST pin for external resets.
+ *
+ * \param p_rstc   Pointer to an RSTC instance.
+ */
+void rstc_reset_extern(Rstc *p_rstc)
+{
+	p_rstc->RSTC_CR = RSTC_KEY | RSTC_CR_EXTRST;
+}
+
+/**
+ * \brief Get RSTC status.
+ *
+ * \param p_rstc Pointer to an RSTC instance.
+ *
+ * \return RSTC status.
+ */
+uint32_t rstc_get_status(Rstc *p_rstc)
+{
+	return p_rstc->RSTC_SR;
+}
+
+/**
+ * \brief Get reset cause.
+ *
+ * \param p_rstc Pointer to an RSTC instance.
+ *
+ * \return The last reset cause.
+ */
+uint32_t rstc_get_reset_cause(Rstc *p_rstc)
+{
+	return (p_rstc->RSTC_SR & RSTC_SR_RSTTYP_Msk);
+}
+
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
diff --git a/hardware/digistump/sam/system/libsam/source/rtc.c b/hardware/digistump/sam/system/libsam/source/rtc.c
new file mode 100644
index 0000000..2fe8566
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/rtc.c
@@ -0,0 +1,450 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup rtc_module Working with RTC
+ * The RTC driver provides the interface to configure and use the RTC
+ * peripheral.
+ *
+ * It manages date, time, and alarms.\n
+ * This timer is clocked by the 32kHz system clock, and is not impacted by
+ * power management settings (PMC). To be accurate, it is better to use an
+ * external 32kHz crystal instead of the internal 32kHz RC.\n
+ *
+ * It uses BCD format, and time can be set in AM/PM or 24h mode through a
+ * configuration bit in the mode register.\n
+ *
+ * To update date or time, the user has to follow these few steps :
+ * 
    
+ * 
  • Set UPDTIM and/or UPDCAL bit(s) in RTC_CR,
    • 
+ * 
  • Polling or IRQ on the ACKUPD bit of RTC_CR,
    • 
+ * 
  • Clear ACKUPD bit in RTC_SCCR,
    • 
+ * 
  • Update Time and/or Calendar values in RTC_TIMR/RTC_CALR (BCD format),
    • 
+ * 
  • Clear UPDTIM and/or UPDCAL bit in RTC_CR.
    • 
+ * 

+ * An alarm can be set to happen on month, date, hours, minutes or seconds,
+ * by setting the proper "Enable" bit of each of these fields in the Time and
+ * Calendar registers.
+ * This allows a large number of configurations to be available for the user.
+ * Alarm occurence can be detected even by polling or interrupt.
+ *
+ * A check of the validity of the date and time format and values written by the user is automatically done.
+ * Errors are reported through the Valid Entry Register.
+ *
+ * For more accurate information, please look at the RTC section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref rtc.c\n
+ * \ref rtc.h.\n
+*/
+/*@{*/
+/*@}*/
+
+
+/**
+ * \file
+ *
+ * Implementation of Real Time Clock (RTC) controller.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Sets the RTC in either 12 or 24 hour mode.
+ *
+ * \param mode  Hour mode.
+ */
+extern void RTC_SetHourMode( Rtc* pRtc, uint32_t dwMode )
+{
+    assert((dwMode & 0xFFFFFFFE) == 0);
+
+    pRtc->RTC_MR = dwMode ;
+}
+
+/**
+ * \brief Gets the RTC mode.
+ *
+ * \return Hour mode.
+ */
+extern uint32_t RTC_GetHourMode( Rtc* pRtc )
+{
+    uint32_t dwMode ;
+
+    dwMode = pRtc->RTC_MR;
+    dwMode &= 0xFFFFFFFE;
+
+    return dwMode ;
+}
+
+/**
+ * \brief Enables the selected interrupt sources of the RTC.
+ *
+ * \param sources  Interrupt sources to enable.
+ */
+extern void RTC_EnableIt( Rtc* pRtc, uint32_t dwSources )
+{
+    assert((dwSources & (uint32_t)(~0x1F)) == 0);
+
+    pRtc->RTC_IER = dwSources ;
+}
+
+/**
+* \brief Disables the selected interrupt sources of the RTC.
+*
+* \param sources  Interrupt sources to disable.
+*/
+extern void RTC_DisableIt( Rtc* pRtc, uint32_t dwSources )
+{
+    assert((dwSources & (uint32_t)(~0x1F)) == 0);
+
+    pRtc->RTC_IDR = dwSources ;
+}
+
+/**
+ * \brief Sets the current time in the RTC.
+ *
+ * \note In successive update operations, the user must wait at least one second
+ * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these
+ * bits again. Please look at the RTC section of the datasheet for detail.
+ *
+ * \param ucHour    Current hour in 12 or 24 hour mode.
+ * \param ucMinute  Current minute.
+ * \param ucSecond  Current second.
+ *
+ * \return 0 sucess, 1 fail to set
+ */
+extern int RTC_SetTime( Rtc* pRtc, uint8_t ucHour, uint8_t ucMinute, uint8_t ucSecond )
+{
+    uint32_t dwTime=0 ;
+    uint8_t ucHour_bcd ;
+    uint8_t ucMin_bcd ;
+    uint8_t ucSec_bcd ;
+
+    /* if 12-hour mode, set AMPM bit */
+    if ( (pRtc->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD )
+    {
+        if ( ucHour > 12 )
+        {
+            ucHour -= 12 ;
+            dwTime |= RTC_TIMR_AMPM ;
+        }
+    }
+    ucHour_bcd = (ucHour%10)   | ((ucHour/10)<<4) ;
+    ucMin_bcd  = (ucMinute%10) | ((ucMinute/10)<<4) ;
+    ucSec_bcd  = (ucSecond%10) | ((ucSecond/10)<<4) ;
+
+    /* value overflow */
+    if ( (ucHour_bcd & (uint8_t)(~RTC_HOUR_BIT_LEN_MASK)) |
+         (ucMin_bcd & (uint8_t)(~RTC_MIN_BIT_LEN_MASK)) |
+         (ucSec_bcd & (uint8_t)(~RTC_SEC_BIT_LEN_MASK)))
+    {
+        return 1 ;
+    }
+
+    dwTime = ucSec_bcd | (ucMin_bcd << 8) | (ucHour_bcd<<16) ;
+
+    pRtc->RTC_CR |= RTC_CR_UPDTIM ;
+    while ((pRtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;
+    pRtc->RTC_SCCR = RTC_SCCR_ACKCLR ;
+    pRtc->RTC_TIMR = dwTime ;
+    pRtc->RTC_CR &= (uint32_t)(~RTC_CR_UPDTIM) ;
+    pRtc->RTC_SCCR |= RTC_SCCR_SECCLR ;
+
+    return (int)(pRtc->RTC_VER & RTC_VER_NVTIM) ;
+}
+
+/**
+ * \brief Retrieves the current time as stored in the RTC in several variables.
+ *
+ * \param pucHour    If not null, current hour is stored in this variable.
+ * \param pucMinute  If not null, current minute is stored in this variable.
+ * \param pucSecond  If not null, current second is stored in this variable.
+ */
+extern void RTC_GetTime( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond )
+{
+    uint32_t dwTime ;
+
+    /* Get current RTC time */
+    dwTime = pRtc->RTC_TIMR ;
+    while ( dwTime != pRtc->RTC_TIMR )
+    {
+        dwTime = pRtc->RTC_TIMR ;
+    }
+
+    /* Hour */
+    if ( pucHour )
+    {
+        *pucHour = ((dwTime & 0x00300000) >> 20) * 10
+                 + ((dwTime & 0x000F0000) >> 16);
+
+        if ( (dwTime & RTC_TIMR_AMPM) == RTC_TIMR_AMPM )
+        {
+            *pucHour += 12 ;
+        }
+    }
+
+    /* Minute */
+    if ( pucMinute )
+    {
+        *pucMinute = ((dwTime & 0x00007000) >> 12) * 10
+                   + ((dwTime & 0x00000F00) >> 8);
+    }
+
+    /* Second */
+    if ( pucSecond )
+    {
+        *pucSecond = ((dwTime & 0x00000070) >> 4) * 10
+                   + (dwTime & 0x0000000F);
+    }
+}
+
+/**
+ * \brief Sets a time alarm on the RTC.
+ * The match is performed only on the provided variables;
+ * Setting all pointers to 0 disables the time alarm.
+ *
+ * \note In AM/PM mode, the hour value must have bit #7 set for PM, cleared for
+ * AM (as expected in the time registers).
+ *
+ * \param pucHour    If not null, the time alarm will hour-match this value.
+ * \param pucMinute  If not null, the time alarm will minute-match this value.
+ * \param pucSecond  If not null, the time alarm will second-match this value.
+ *
+ * \return 0 success, 1 fail to set
+ */
+extern int RTC_SetTimeAlarm( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond )
+{
+    uint32_t dwAlarm=0 ;
+
+    /* Hour */
+    if ( pucHour )
+    {
+        dwAlarm |= RTC_TIMALR_HOUREN | ((*pucHour / 10) << 20) | ((*pucHour % 10) << 16);
+    }
+
+    /* Minute */
+    if ( pucMinute )
+    {
+        dwAlarm |= RTC_TIMALR_MINEN | ((*pucMinute / 10) << 12) | ((*pucMinute % 10) << 8);
+    }
+
+    /* Second */
+    if ( pucSecond )
+    {
+        dwAlarm |= RTC_TIMALR_SECEN | ((*pucSecond / 10) << 4) | (*pucSecond % 10);
+    }
+
+    pRtc->RTC_TIMALR = dwAlarm ;
+
+    return (int)(pRtc->RTC_VER & RTC_VER_NVTIMALR) ;
+}
+
+/**
+ * \brief Retrieves the current year, month and day from the RTC.
+ * Month, day and week values are numbered starting at 1.
+ *
+ * \param pYwear  Current year (optional).
+ * \param pucMonth  Current month (optional).
+ * \param pucDay  Current day (optional).
+ * \param pucWeek  Current day in current week (optional).
+ */
+extern void RTC_GetDate( Rtc* pRtc, uint16_t *pwYear, uint8_t *pucMonth, uint8_t *pucDay, uint8_t *pucWeek )
+{
+    uint32_t dwDate ;
+
+    /* Get current date (multiple reads are necessary to insure a stable value) */
+    do
+    {
+        dwDate = pRtc->RTC_CALR ;
+    }
+    while ( dwDate != pRtc->RTC_CALR ) ;
+
+    /* Retrieve year */
+    if ( pwYear )
+    {
+        *pwYear = (((dwDate  >> 4) & 0x7) * 1000)
+                 + ((dwDate & 0xF) * 100)
+                 + (((dwDate >> 12) & 0xF) * 10)
+                 + ((dwDate >> 8) & 0xF);
+    }
+
+    /* Retrieve month */
+    if ( pucMonth )
+    {
+        *pucMonth = (((dwDate >> 20) & 1) * 10) + ((dwDate >> 16) & 0xF);
+    }
+
+    /* Retrieve day */
+    if ( pucDay )
+    {
+        *pucDay = (((dwDate >> 28) & 0x3) * 10) + ((dwDate >> 24) & 0xF);
+    }
+
+    /* Retrieve week */
+    if ( pucWeek )
+    {
+        *pucWeek = ((dwDate >> 21) & 0x7);
+    }
+}
+
+/**
+ * \brief Sets the current year, month and day in the RTC.
+ * Month, day and week values must be numbered starting from 1.
+ *
+ * \note In successive update operations, the user must wait at least one second
+ * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these
+ * bits again. Please look at the RTC section of the datasheet for detail.
+ *
+ * \param wYear  Current year.
+ * \param ucMonth Current month.
+ * \param ucDay   Current day.
+ * \param ucWeek  Day number in current week.
+ *
+ * \return 0 success, 1 fail to set
+ */
+extern int RTC_SetDate( Rtc* pRtc, uint16_t wYear, uint8_t ucMonth, uint8_t ucDay, uint8_t ucWeek )
+{
+    uint32_t wDate ;
+    uint8_t ucCent_bcd ;
+    uint8_t ucYear_bcd ;
+    uint8_t ucMonth_bcd ;
+    uint8_t ucDay_bcd ;
+    uint8_t ucWeek_bcd ;
+
+    ucCent_bcd  = ((wYear/100)%10) | ((wYear/1000)<<4);
+    ucYear_bcd  = (wYear%10) | (((wYear/10)%10)<<4);
+    ucMonth_bcd = ((ucMonth%10) | (ucMonth/10)<<4);
+    ucDay_bcd   = ((ucDay%10) | (ucDay/10)<<4);
+    ucWeek_bcd  = ((ucWeek%10) | (ucWeek/10)<<4);
+
+    /* value over flow */
+    if ( (ucCent_bcd & (uint8_t)(~RTC_CENT_BIT_LEN_MASK)) |
+         (ucYear_bcd & (uint8_t)(~RTC_YEAR_BIT_LEN_MASK)) |
+         (ucMonth_bcd & (uint8_t)(~RTC_MONTH_BIT_LEN_MASK)) |
+         (ucWeek_bcd & (uint8_t)(~RTC_WEEK_BIT_LEN_MASK)) |
+         (ucDay_bcd & (uint8_t)(~RTC_DATE_BIT_LEN_MASK))
+       )
+    {
+        return 1 ;
+    }
+
+
+    /* Convert values to date register value */
+    wDate = ucCent_bcd |
+            (ucYear_bcd << 8) |
+            (ucMonth_bcd << 16) |
+            (ucWeek_bcd << 21) |
+            (ucDay_bcd << 24);
+
+    /* Update calendar register  */
+    pRtc->RTC_CR |= RTC_CR_UPDCAL ;
+    while ((pRtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;
+
+    pRtc->RTC_SCCR = RTC_SCCR_ACKCLR;
+    pRtc->RTC_CALR = wDate ;
+    pRtc->RTC_CR &= (uint32_t)(~RTC_CR_UPDCAL) ;
+    pRtc->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */
+
+    return (int)(pRtc->RTC_VER & RTC_VER_NVCAL) ;
+}
+
+/**
+ * \brief Sets a date alarm in the RTC.
+ * The alarm will match only the provided values;
+ * Passing a null-pointer disables the corresponding field match.
+ *
+ * \param pucMonth If not null, the RTC alarm will month-match this value.
+ * \param pucDay   If not null, the RTC alarm will day-match this value.
+ *
+ * \return 0 success, 1 fail to set
+ */
+extern int RTC_SetDateAlarm( Rtc* pRtc, uint8_t *pucMonth, uint8_t *pucDay )
+{
+    uint32_t dwAlarm ;
+
+    dwAlarm = ((pucMonth) || (pucDay)) ? (0) : (0x01010000);
+
+    /* Compute alarm field value */
+    if ( pucMonth )
+    {
+        dwAlarm |= RTC_CALALR_MTHEN | ((*pucMonth / 10) << 20) | ((*pucMonth % 10) << 16);
+    }
+
+    if ( pucDay )
+    {
+        dwAlarm |= RTC_CALALR_DATEEN | ((*pucDay / 10) << 28) | ((*pucDay % 10) << 24);
+    }
+
+    /* Set alarm */
+    pRtc->RTC_CALALR = dwAlarm ;
+
+    return (int)(pRtc->RTC_VER & RTC_VER_NVCALALR) ;
+}
+
+/**
+ * \brief Clear flag bits of status clear command register in the RTC.
+ *
+ * \param mask Bits mask of cleared events
+ */
+extern void RTC_ClearSCCR( Rtc* pRtc, uint32_t dwMask )
+{
+    /* Clear all flag bits in status clear command register */
+    dwMask &= RTC_SCCR_ACKCLR | RTC_SCCR_ALRCLR | RTC_SCCR_SECCLR | RTC_SCCR_TIMCLR | RTC_SCCR_CALCLR ;
+
+    pRtc->RTC_SCCR = dwMask ;
+}
+
+/**
+ * \brief Get flag bits of status register in the RTC.
+ *
+ * \param mask Bits mask of Status Register
+ *
+ * \return Status register & mask
+ */
+extern uint32_t RTC_GetSR( Rtc* pRtc, uint32_t dwMask )
+{
+    uint32_t dwEvent ;
+
+    dwEvent = pRtc->RTC_SR ;
+
+    return (dwEvent & dwMask) ;
+}
+
diff --git a/hardware/digistump/sam/system/libsam/source/rtt.c b/hardware/digistump/sam/system/libsam/source/rtt.c
new file mode 100644
index 0000000..41dd333
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/rtt.c
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup rtt_module Working with RTT
+ * The RTT driver provides the interface to configure and use the RTT
+ * peripheral.
+ *
+ * The Real-time Timer is used to count elapsed seconds.\n
+ * This timer is clocked by the 32kHz system clock divided by a programmable
+ * 16-bit balue. To be accurate, it is better to use an
+ * external 32kHz crystal instead of the internal 32kHz RC.\n
+ *
+ * To count elapsed seconds, the user could follow these few steps:
+ * 
    
+ * 
  • Programming PTPRES in RTT_MR to feeding the timer with a 1Hz signal.
    • 
+ * 
  • Writing the bit RTTRST in RTT_MR to restart the timer with new settings.
    • 
+ * 

+ *
+ * An alarm can be set to happen on second by setting alarm value in RTT_AR.
+ * Alarm occurence can be detected by polling or interrupt.
+ *
+ * For more accurate information, please look at the RTT section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref rtt.c\n
+ * \ref rtt.h.\n
+ */
+/*@{*/
+/*@}*/
+
+/**
+ * \file
+ *
+ * Implementation of Real Time Timer (RTT) controller.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Changes the prescaler value of the given RTT and restarts it.
+ *
+ * \note This function disables RTT interrupt sources.
+ *
+ * \param rtt  Pointer to a Rtt instance.
+ * \param prescaler  Prescaler value for the RTT.
+ */
+void RTT_SetPrescaler(Rtt *rtt, uint16_t prescaler)
+{
+    rtt->RTT_MR = (prescaler |  RTT_MR_RTTRST);
+}
+
+/**
+ * \brief Returns the current value of the RTT timer value.
+ *
+ * \param rtt  Pointer to a Rtt instance.
+ */
+uint32_t RTT_GetTime(Rtt *rtt)
+{
+    return rtt->RTT_VR;
+}
+
+/**
+ * \brief Enables the specified RTT interrupt sources.
+ *
+ * \param rtt  Pointer to a Rtt instance.
+ * \param sources  Bitmask of interrupts to enable.
+ */
+void RTT_EnableIT(Rtt *rtt, uint32_t sources)
+{
+    assert( (sources & 0x0004FFFF) == 0 ) ;
+    rtt->RTT_MR |= sources;
+}
+
+/**
+ * \brief Returns the status register value of the given RTT.
+ *
+ * \param rtt  Pointer to an Rtt instance.
+ */
+uint32_t RTT_GetStatus(Rtt *rtt)
+{
+    return rtt->RTT_SR;
+}
+
+/**
+ * \brief Configures the RTT to generate an alarm at the given time.
+ *
+ * \param pRtt  Pointer to an Rtt instance.
+ * \param time  Alarm time.
+ */
+void RTT_SetAlarm(Rtt *pRtt, uint32_t time)
+{
+    assert(time > 0);
+
+    pRtt->RTT_AR = time - 1;
+}
diff --git a/hardware/digistump/sam/system/libsam/source/spi.c b/hardware/digistump/sam/system/libsam/source/spi.c
new file mode 100644
index 0000000..be3638f
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/spi.c
@@ -0,0 +1,352 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup spi_module Working with SPI
+ * The SPI driver provides the interface to configure and use the SPI
+ * peripheral.
+ *
+ * The Serial Peripheral Interface (SPI) circuit is a synchronous serial
+ * data link that provides communication with external devices in Master
+ * or Slave Mode.
+ *
+ * To use the SPI, the user has to follow these few steps:
+ * -# Enable the SPI pins required by the application (see pio.h).
+ * -# Configure the SPI using the \ref SPI_Configure(). This enables the
+ *    peripheral clock. The mode register is loaded with the given value.
+ * -# Configure all the necessary chip selects with \ref SPI_ConfigureNPCS().
+ * -# Enable the SPI by calling \ref SPI_Enable().
+ * -# Send/receive data using \ref SPI_Write() and \ref SPI_Read(). Note that \ref SPI_Read()
+ *    must be called after \ref SPI_Write() to retrieve the last value read.
+ * -# Send/receive data using the PDC with the \ref SPI_WriteBuffer() and
+ *    \ref SPI_ReadBuffer() functions.
+ * -# Disable the SPI by calling \ref SPI_Disable().
+ *
+ * For more accurate information, please look at the SPI section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref spi.c\n
+ * \ref spi.h.\n
+*/
+/*@{*/
+/*@}*/
+
+/**
+ * \file
+ *
+ * Implementation of Serial Peripheral Interface (SPI) controller.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Enables a SPI peripheral.
+ *
+ * \param spi  Pointer to an Spi instance.
+ */
+extern void SPI_Enable( Spi* spi )
+{
+    spi->SPI_CR = SPI_CR_SPIEN ;
+}
+
+/**
+ * \brief Disables a SPI peripheral.
+ *
+ * \param spi  Pointer to an Spi instance.
+ */
+extern void SPI_Disable( Spi* spi )
+{
+    spi->SPI_CR = SPI_CR_SPIDIS ;
+}
+
+/**
+ * \brief Enables one or more interrupt sources of a SPI peripheral.
+ *
+ * \param spi  Pointer to an Spi instance.
+ * \param sources Bitwise OR of selected interrupt sources.
+ */
+extern void SPI_EnableIt( Spi* spi, uint32_t dwSources )
+{
+    spi->SPI_IER = dwSources ;
+}
+
+/**
+ * \brief Disables one or more interrupt sources of a SPI peripheral.
+ *
+ * \param spi  Pointer to an Spi instance.
+ * \param sources Bitwise OR of selected interrupt sources.
+ */
+extern void SPI_DisableIt( Spi* spi, uint32_t dwSources )
+{
+    spi->SPI_IDR = dwSources ;
+}
+
+/**
+ * \brief Configures a SPI peripheral as specified. The configuration can be computed
+ * using several macros (see \ref spi_configuration_macros).
+ *
+ * \param spi  Pointer to an Spi instance.
+ * \param id   Peripheral ID of the SPI.
+ * \param configuration  Value of the SPI configuration register.
+ */
+extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration )
+{
+    pmc_enable_periph_clk( dwId ) ;
+    spi->SPI_CR = SPI_CR_SPIDIS ;
+
+    /* Execute a software reset of the SPI twice */
+    spi->SPI_CR = SPI_CR_SWRST ;
+    spi->SPI_CR = SPI_CR_SWRST ;
+    spi->SPI_MR = dwConfiguration ;
+}
+
+
+/**
+ * \brief Configures a chip select of a SPI peripheral. The chip select configuration
+ * is computed using several macros (see \ref spi_configuration_macros).
+ *
+ * \param spi   Pointer to an Spi instance.
+ * \param npcs  Chip select to configure (0, 1, 2 or 3).
+ * \param configuration  Desired chip select configuration.
+ */
+void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration )
+{
+    spi->SPI_CSR[dwNpcs] = dwConfiguration ;
+}
+
+/**
+ * \brief Get the current status register of the given SPI peripheral.
+ * \note This resets the internal value of the status register, so further
+ * read may yield different values.
+ * \param spi   Pointer to a Spi instance.
+ * \return  SPI status register.
+ */
+extern uint32_t SPI_GetStatus( Spi* spi )
+{
+    return spi->SPI_SR ;
+}
+
+/**
+ * \brief Reads and returns the last word of data received by a SPI peripheral. This
+ * method must be called after a successful SPI_Write call.
+ *
+ * \param spi  Pointer to an Spi instance.
+ *
+ * \return readed data.
+ */
+extern uint32_t SPI_Read( Spi* spi )
+{
+    while ( (spi->SPI_SR & SPI_SR_RDRF) == 0 ) ;
+
+    return spi->SPI_RDR & 0xFFFF ;
+}
+
+/**
+ * \brief Sends data through a SPI peripheral. If the SPI is configured to use a fixed
+ * peripheral select, the npcs value is meaningless. Otherwise, it identifies
+ * the component which shall be addressed.
+ *
+ * \param spi   Pointer to an Spi instance.
+ * \param npcs  Chip select of the component to address (0, 1, 2 or 3).
+ * \param data  Word of data to send.
+ */
+extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData )
+{
+    /* Send data */
+    while ( (spi->SPI_SR & SPI_SR_TXEMPTY) == 0 ) ;
+    spi->SPI_TDR = wData | SPI_PCS( dwNpcs ) ;
+    while ( (spi->SPI_SR & SPI_SR_TDRE) == 0 ) ;
+}
+
+/**
+ * \brief Check if SPI transfer finish.
+ *
+ * \param spi  Pointer to an Spi instance.
+ *
+ * \return Returns 1 if there is no pending write operation on the SPI; otherwise
+ * returns 0.
+ */
+extern uint32_t SPI_IsFinished( Spi* spi )
+{
+    return ((spi->SPI_SR & SPI_SR_TXEMPTY) != 0) ;
+}
+
+#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
+/**
+ * \brief Enable Spi PDC transmit
+ * \param spi  Pointer to an Spi instance.
+*/
+extern void SPI_PdcEnableTx( Spi* spi )
+{
+    spi->SPI_PTCR = SPI_PTCR_TXTEN ;
+}
+
+/**
+ * \brief Disable Spi PDC transmit
+ * \param spi  Pointer to an Spi instance.
+*/
+extern void SPI_PdcDisableTx( Spi* spi )
+{
+    spi->SPI_PTCR = SPI_PTCR_TXTDIS ;
+}
+
+/**
+ * \brief Enable Spi PDC receive
+ * \param spi  Pointer to an Spi instance.
+*/
+extern void SPI_PdcEnableRx( Spi* spi )
+{
+    spi->SPI_PTCR = SPI_PTCR_RXTEN ;
+}
+
+/**
+ * \brief Disable Spi PDC receive
+ * \param spi  Pointer to an Spi instance.
+*/
+extern void SPI_PdcDisableRx( Spi* spi )
+{
+    spi->SPI_PTCR = SPI_PTCR_RXTDIS ;
+}
+
+/**
+ * \brief Set PDC transmit and next transmit buffer address and size.
+ *
+ * \param spi    Pointer to an Spi instance.
+ * \param txBuf  PDC transmit buffer address.
+ * \param txCount  Length in bytes of the transmit buffer.
+ * \param txNextBuf  PDC next transmit buffer address.
+ * \param txNextCount  Length in bytes of the next transmit buffer.
+ */
+extern void SPI_PdcSetTx( Spi* spi, void* pvTxBuf, uint32_t dwTxCount, void* pvTxNextBuf, uint32_t dwTxNextCount )
+{
+    spi->SPI_TPR = (uint32_t)pvTxBuf ;
+    spi->SPI_TCR = dwTxCount ;
+    spi->SPI_TNPR = (uint32_t)pvTxNextBuf ;
+    spi->SPI_TNCR = dwTxNextCount ;
+}
+
+/**
+ * \brief Set PDC receive and next receive buffer address and size.
+ *
+ * \param spi    Pointer to an Spi instance.
+ * \param rxBuf  PDC receive buffer address.
+ * \param rxCount  Length in bytes of the receive buffer.
+ * \param rxNextBuf  PDC next receive buffer address.
+ * \param rxNextCount  Length in bytes of the next receive buffer.
+ */
+extern void SPI_PdcSetRx( Spi* spi, void* pvRxBuf, uint32_t dwRxCount, void* pvRxNextBuf, uint32_t dwRxNextCount )
+{
+    spi->SPI_RPR = (uint32_t)pvRxBuf ;
+    spi->SPI_RCR = dwRxCount ;
+    spi->SPI_RNPR = (uint32_t)pvRxNextBuf ;
+    spi->SPI_RNCR = dwRxNextCount ;
+}
+
+/**
+ * \brief Sends the contents of buffer through a SPI peripheral, using the PDC to
+ * take care of the transfer.
+ *
+ * \param spi     Pointer to an Spi instance.
+ * \param buffer  Data buffer to send.
+ * \param length  Length of the data buffer.
+ */
+extern uint32_t SPI_WriteBuffer( Spi* spi, void* pvBuffer, uint32_t dwLength )
+{
+    /* Check if first bank is free */
+    if ( spi->SPI_TCR == 0 )
+    {
+        spi->SPI_TPR = (uint32_t)pvBuffer ;
+        spi->SPI_TCR = dwLength ;
+        spi->SPI_PTCR = PERIPH_PTCR_TXTEN ;
+
+        return 1 ;
+    }
+    /* Check if second bank is free */
+    else
+    {
+        if ( spi->SPI_TNCR == 0 )
+        {
+            spi->SPI_TNPR = (uint32_t)pvBuffer ;
+            spi->SPI_TNCR = dwLength ;
+
+            return 1 ;
+        }
+    }
+
+    /* No free banks */
+    return 0 ;
+}
+
+/**
+ * \brief Reads data from a SPI peripheral until the provided buffer is filled. This
+ * method does NOT need to be called after SPI_Write or SPI_WriteBuffer.
+ *
+ * \param spi     Pointer to an Spi instance.
+ * \param buffer  Data buffer to store incoming bytes.
+ * \param length  Length in bytes of the data buffer.
+ */
+extern uint32_t SPI_ReadBuffer( Spi* spi, void *pvBuffer, uint32_t dwLength )
+{
+    /* Check if the first bank is free */
+    if ( spi->SPI_RCR == 0 )
+    {
+        spi->SPI_RPR = (uint32_t)pvBuffer ;
+        spi->SPI_RCR = dwLength ;
+        spi->SPI_PTCR = PERIPH_PTCR_RXTEN ;
+
+        return 1 ;
+    }
+    /* Check if second bank is free */
+    else
+    {
+        if ( spi->SPI_RNCR == 0 )
+        {
+            spi->SPI_RNPR = (uint32_t)pvBuffer ;
+            spi->SPI_RNCR = dwLength ;
+            return 1 ;
+        }
+    }
+
+    /* No free bank */
+    return 0 ;
+}
+
+#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
+
diff --git a/hardware/digistump/sam/system/libsam/source/ssc.c b/hardware/digistump/sam/system/libsam/source/ssc.c
new file mode 100644
index 0000000..ca18a69
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/ssc.c
@@ -0,0 +1,835 @@
+/**
+ * \file
+ *
+ * \brief Synchronous Serial Controller (SSC) driver for SAM.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include 
+#include "ssc.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/**
+ * \defgroup sam_drivers_ssc_group Synchronous Serial Controller (SSC)
+ *
+ * The Synchronous Serial Controller (SSC) provides a synchronous communication
+ * link with external devices. It supports many serial synchronous communication
+ * protocols generally used in audio and telecom applications such as I2S,
+ * Short Frame Sync, Long Frame Sync, etc.
+ * This is a driver for configuration and use of the SSC peripheral.
+ *
+ * @{
+ */
+
+#define SSC_WPKEY SSC_WPMR_WPKEY(0x535343)
+
+/**
+ * \brief Set up clock.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param ul_bitrate Desired bit clock.
+ * \param ul_mck MCK clock.
+ *
+ * \retval SSC_RC_YES Success.
+ * \retval SSC_RC_NO Invalid input value.
+ */
+uint32_t ssc_set_clock_divider(Ssc *p_ssc, uint32_t ul_bitrate,
+		uint32_t ul_mck)
+{
+	if (ul_mck && ul_bitrate) {
+		p_ssc->SSC_CMR = SSC_CMR_DIV(((ul_mck + ul_bitrate) / ul_bitrate) >> 1);
+		return SSC_RC_YES;
+	} else {
+		return SSC_RC_NO;
+	}
+}
+
+/**
+ * \brief Setup for I2S transmitter.
+ *
+ * \note If working in master mode, the divided clock needs to be configured before
+ * calling this function according to the sample rate and ul_datlen field.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param ul_mode Working mode, SSC_I2S_MASTER_OUT or SSC_I2S_SLAVE_OUT.
+ * \param ul_cks Source clock selection while working in SSC_I2S_SLAVE_OUT mode.
+ * \param ul_ch_mode Channel mode, stereo or mono.
+ * \param ul_datlen Data length for one channel.
+ */
+void ssc_i2s_set_transmitter(Ssc *p_ssc, uint32_t ul_mode,
+		uint32_t ul_cks, uint32_t ul_ch_mode, uint32_t ul_datlen)
+{
+	clock_opt_t tx_clk_option;
+	data_frame_opt_t tx_data_frame_option;
+
+	/* Initialize the local variable. */
+	memset((uint8_t *)&tx_clk_option, 0, sizeof(clock_opt_t));
+	memset((uint8_t *)&tx_data_frame_option, 0, sizeof(data_frame_opt_t));
+
+	/* Data start: MonoLeft-Falling, MonoRight-Rising, Stero-Edge. */
+	switch (ul_ch_mode) {
+	case SSC_AUDIO_MONO_RIGHT:
+		tx_clk_option.ul_start_sel = SSC_TCMR_START_RF_RISING;
+		break;
+	case SSC_AUDIO_MONO_LEFT:
+		tx_clk_option.ul_start_sel = SSC_TCMR_START_RF_FALLING;
+		break;
+	case SSC_AUDIO_STERO:
+		tx_clk_option.ul_start_sel = SSC_TCMR_START_RF_EDGE;
+		break;
+	}
+	if (ul_mode & SSC_I2S_MASTER_OUT) {
+		/* Stereo has 2 data words, and mono has only one data word. */
+		if (SSC_AUDIO_STERO == ul_ch_mode) {
+			tx_data_frame_option.ul_datnb = 1;
+		} else {
+			tx_data_frame_option.ul_datnb = 0;
+		}
+
+		/* Configure TCMR Settings. */
+		tx_clk_option.ul_cks = SSC_TCMR_CKS_MCK;
+		tx_clk_option.ul_cko = SSC_TCMR_CKO_CONTINUOUS;
+		tx_clk_option.ul_cki = 0;
+		tx_clk_option.ul_ckg = SSC_RCMR_CKG_NONE;
+		/* The delay is defined by I2S protocol. */
+		tx_clk_option.ul_sttdly = 1;
+		tx_clk_option.ul_period = ul_datlen - 1;
+
+		/* Configure TFMR Settings. */
+		tx_data_frame_option.ul_datlen = ul_datlen - 1;
+		tx_data_frame_option.ul_msbf = SSC_TFMR_MSBF;
+		tx_data_frame_option.ul_fslen = ul_datlen - 1;
+		tx_data_frame_option.ul_fsos = SSC_TFMR_FSOS_NEGATIVE;
+		tx_data_frame_option.ul_fsedge = SSC_TFMR_FSEDGE_POSITIVE;
+	} else if (ul_mode & SSC_I2S_SLAVE_OUT) {
+		/* Configure TCMR Settings. */
+		tx_clk_option.ul_cks = ul_cks;
+		tx_clk_option.ul_cko = SSC_TCMR_CKO_NONE;
+		tx_clk_option.ul_cki = 0;
+		tx_clk_option.ul_ckg = SSC_RCMR_CKG_NONE;
+		tx_clk_option.ul_sttdly = 1;
+		tx_clk_option.ul_period = 0;
+
+		/* Configure TFMR Settings. */
+		tx_data_frame_option.ul_datlen = ul_datlen - 1;
+		tx_data_frame_option.ul_msbf = SSC_TFMR_MSBF;
+		tx_data_frame_option.ul_fslen = 0;
+		tx_data_frame_option.ul_fsos = SSC_TFMR_FSOS_NONE;
+		tx_data_frame_option.ul_fsedge = SSC_TFMR_FSEDGE_POSITIVE;
+	}
+	/* Configure the default level on TD pin. */
+	ssc_set_td_default_level(p_ssc, 0);
+
+	/* Configure the SSC transmitter. */
+	ssc_set_transmitter(p_ssc, &tx_clk_option, &tx_data_frame_option);
+}
+
+/**
+ * \brief Setup for I2S receiver.
+ *
+ * \note If working in master mode, the divided clock needs to be configured before
+ * calling this function according to the sample rate and ul_datlen field.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param ul_mode Working mode, SSC_I2S_MASTER_IN or SSC_I2S_SLAVE_IN.
+ * \param ul_cks Source clock selection while working in SSC_I2S_SLAVE_IN mode.
+ * \param ul_ch_mode Channel mode, stereo or mono.
+ * \param ul_datlen Data length for one channel.
+ */
+void ssc_i2s_set_receiver(Ssc *p_ssc, uint32_t ul_mode,
+		uint32_t ul_cks, uint32_t ul_ch_mode, uint32_t ul_datlen)
+{
+	clock_opt_t rx_clk_option;
+	data_frame_opt_t rx_data_frame_option;
+
+	/* Initialize the local variable. */
+	memset((uint8_t *)&rx_clk_option, 0, sizeof(clock_opt_t));
+	memset((uint8_t *)&rx_data_frame_option, 0, sizeof(data_frame_opt_t));
+
+	/* Data start: MonoLeft-Falling, MonoRight-Rising, Stero-Edge. */
+	switch (ul_ch_mode) {
+	case SSC_AUDIO_MONO_RIGHT:
+		rx_clk_option.ul_start_sel = SSC_RCMR_START_RF_RISING;
+		break;
+	case SSC_AUDIO_MONO_LEFT:
+		rx_clk_option.ul_start_sel = SSC_RCMR_START_RF_FALLING;
+		break;
+	case SSC_AUDIO_STERO:
+		rx_clk_option.ul_start_sel = SSC_RCMR_START_RF_EDGE;
+		break;
+	}
+	if (ul_mode & SSC_I2S_MASTER_IN) {
+		/* Stereo has 2 data words, and mono has only one data word. */
+		if (SSC_AUDIO_STERO == ul_ch_mode) {
+			rx_data_frame_option.ul_datnb = 1;
+		} else {
+			rx_data_frame_option.ul_datnb = 0;
+		}
+
+		/* Configure RCMR Settings. */
+		rx_clk_option.ul_cks = SSC_TCMR_CKS_MCK;
+		rx_clk_option.ul_cko = SSC_TCMR_CKO_CONTINUOUS;
+		rx_clk_option.ul_cki = 0;
+		rx_clk_option.ul_ckg = SSC_RCMR_CKG_NONE;
+		rx_clk_option.ul_sttdly = 1;
+		rx_clk_option.ul_period = ul_datlen - 1;
+
+		/* Configure RFMR Settings. */
+		rx_data_frame_option.ul_datlen = ul_datlen - 1;
+		rx_data_frame_option.ul_msbf = SSC_TFMR_MSBF;
+		rx_data_frame_option.ul_fslen = ul_datlen - 1;
+		rx_data_frame_option.ul_fsos = SSC_TFMR_FSOS_NEGATIVE;
+		rx_data_frame_option.ul_fsedge = SSC_TFMR_FSEDGE_POSITIVE;
+	} else if (ul_mode & SSC_I2S_SLAVE_IN) {
+		/* Configure TCMR Settings. */
+		rx_clk_option.ul_cks = ul_cks;
+		rx_clk_option.ul_cko = SSC_TCMR_CKO_NONE;
+		rx_clk_option.ul_cki = 0;
+		rx_clk_option.ul_ckg = SSC_RCMR_CKG_NONE;
+		rx_clk_option.ul_sttdly = 1;
+		rx_clk_option.ul_period = 0;
+
+		/* Configure TFMR Settings. */
+		rx_data_frame_option.ul_datlen = ul_datlen - 1;
+		rx_data_frame_option.ul_msbf = SSC_TFMR_MSBF;
+		rx_data_frame_option.ul_fslen = 0;
+		rx_data_frame_option.ul_fsos = SSC_TFMR_FSOS_NONE;
+		rx_data_frame_option.ul_fsedge = SSC_TFMR_FSEDGE_POSITIVE;
+	}
+
+	/* Configure the SSC receiver. */
+	ssc_set_receiver(p_ssc, &rx_clk_option, &rx_data_frame_option);
+}
+
+/**
+ * \brief Reset SSC module.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ */
+void ssc_reset(Ssc *p_ssc)
+{
+	p_ssc->SSC_CR = SSC_CR_SWRST;
+	p_ssc->SSC_CMR = 0;
+	p_ssc->SSC_RCMR = 0;
+	p_ssc->SSC_RFMR = 0;
+	p_ssc->SSC_TCMR = 0;
+	p_ssc->SSC_TFMR = 0;
+}
+
+/**
+ * \brief Enable SSC receiver.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ */
+void ssc_enable_rx(Ssc *p_ssc)
+{
+	p_ssc->SSC_CR = SSC_CR_RXEN;
+}
+
+/**
+ * \brief Disable SSC receiver.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ */
+void ssc_disable_rx(Ssc *p_ssc)
+{
+	p_ssc->SSC_CR = SSC_CR_RXDIS;
+}
+
+/**
+ * \brief Enable SSC Transmitter.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ */
+void ssc_enable_tx(Ssc *p_ssc)
+{
+	p_ssc->SSC_CR = SSC_CR_TXEN;
+}
+
+/**
+ * \brief Disable SSC Transmitter.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ */
+void ssc_disable_tx(Ssc *p_ssc)
+{
+	p_ssc->SSC_CR = SSC_CR_TXDIS;
+}
+
+/**
+ * \brief Configure SSC to work in normal mode.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ */
+void ssc_set_normal_mode(Ssc *p_ssc)
+{
+	p_ssc->SSC_RFMR &= ~SSC_RFMR_LOOP;
+}
+
+/**
+ * \brief Configure SSC to work in loop mode.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ */
+void ssc_set_loop_mode(Ssc *p_ssc)
+{
+	p_ssc->SSC_RFMR |= SSC_RFMR_LOOP;
+}
+
+/**
+ * \brief Configure SSC receive stop selection.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param ul_sel Compare 0 used or Compare both 0 & 1 used.
+ */
+void ssc_set_rx_stop_selection(Ssc *p_ssc, uint32_t ul_sel)
+{
+	if (SSC_RX_STOP_COMPARE_0_1 == ul_sel) {
+		p_ssc->SSC_RCMR |= SSC_RCMR_STOP;
+	} else if (SSC_RX_STOP_COMPARE_0 == ul_sel) {
+		p_ssc->SSC_RCMR &= ~SSC_RCMR_STOP;
+	}
+}
+
+/**
+ * \brief Configure SSC default level driven on the TD pin while
+ * out of transmission.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param ul_level The default driven level of TD pin.
+ */
+void ssc_set_td_default_level(Ssc *p_ssc, uint32_t ul_level)
+{
+	if (ul_level) {
+		p_ssc->SSC_TFMR |= SSC_TFMR_DATDEF;
+	} else {
+		p_ssc->SSC_TFMR &= ~SSC_TFMR_DATDEF;
+	}
+}
+
+/**
+ * \brief The TD line is driven with the SSC_TSHR register value
+ * during the transmission of the Transmit Frame Sync Signal.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ */
+void ssc_enable_tx_frame_sync_data(Ssc *p_ssc)
+{
+	p_ssc->SSC_TFMR |= SSC_TFMR_FSDEN;
+}
+
+/**
+ * \brief The TD line is driven with the default value during the Transmit
+ * Frame Sync signal.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ */
+void ssc_disable_tx_frame_sync_data(Ssc *p_ssc)
+{
+	p_ssc->SSC_TFMR &= ~SSC_TFMR_FSDEN;
+}
+
+/**
+ * \brief Configure SSC receiver clock mode and date frame configuration.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param p_rx_clk_opt Pointer to the receiver clock configuration structure.
+ * \param p_rx_data_frame Pointer to the receiver data frame configuration structure.
+ */
+void ssc_set_receiver(Ssc *p_ssc, clock_opt_t *p_rx_clk_opt,
+		data_frame_opt_t *p_rx_data_frame)
+{
+	if (p_rx_clk_opt == NULL) {
+		p_ssc->SSC_RCMR = 0;
+	} else {
+		p_ssc->SSC_RCMR |= p_rx_clk_opt->ul_cks |
+				p_rx_clk_opt->ul_cko | p_rx_clk_opt->ul_cki |
+				p_rx_clk_opt->ul_ckg |
+				p_rx_clk_opt->ul_start_sel |
+				SSC_RCMR_PERIOD(p_rx_clk_opt->ul_period) |
+				SSC_RCMR_STTDLY(p_rx_clk_opt->ul_sttdly);
+	}
+
+	if (p_rx_data_frame == NULL) {
+		p_ssc->SSC_RFMR = 0;
+	} else {
+		p_ssc->SSC_RFMR |= SSC_RFMR_DATLEN(p_rx_data_frame->ul_datlen) |
+				p_rx_data_frame->ul_msbf |
+				SSC_RFMR_DATNB(p_rx_data_frame->ul_datnb) |
+				SSC_RFMR_FSLEN(p_rx_data_frame->ul_fslen) |
+				SSC_RFMR_FSLEN_EXT(p_rx_data_frame->ul_fslen_ext) |
+				p_rx_data_frame->ul_fsos |
+				p_rx_data_frame->ul_fsedge;
+	}
+}
+
+/**
+ * \brief Configure SSC transmitter clock mode and date frame configuration.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param p_tx_clk_opt Pointer to the transmitter clock configuration structure.
+ * \param p_tx_data_frame Pointer to the transmitter data frame configuration structure.
+ */
+void ssc_set_transmitter(Ssc *p_ssc, clock_opt_t *p_tx_clk_opt,
+		data_frame_opt_t *p_tx_data_frame)
+{
+	if (p_tx_clk_opt == NULL) {
+		p_ssc->SSC_TCMR = 0;
+	} else {
+		p_ssc->SSC_TCMR |= p_tx_clk_opt->ul_cks |
+				p_tx_clk_opt->ul_cko | p_tx_clk_opt->ul_cki |
+				p_tx_clk_opt->ul_ckg |
+				p_tx_clk_opt->ul_start_sel |
+				SSC_RCMR_PERIOD(p_tx_clk_opt->ul_period) |
+				SSC_RCMR_STTDLY(p_tx_clk_opt->ul_sttdly);
+	}
+
+	if (p_tx_data_frame == NULL) {
+		p_ssc->SSC_TFMR = 0;
+	} else {
+		p_ssc->SSC_TFMR |= SSC_RFMR_DATLEN(p_tx_data_frame->ul_datlen) |
+				p_tx_data_frame->ul_msbf |
+				SSC_RFMR_DATNB(p_tx_data_frame->ul_datnb) |
+				SSC_RFMR_FSLEN(p_tx_data_frame->ul_fslen) |
+				SSC_RFMR_FSLEN_EXT(p_tx_data_frame->ul_fslen_ext) |
+				p_tx_data_frame->ul_fsos |
+				p_tx_data_frame->ul_fsedge;
+	}
+}
+
+/**
+ * \brief Configure SSC Receive Compare Register.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param ul_id Compare register ID.
+ * \param ul_value Value to configure.
+ */
+void ssc_set_rx_compare(Ssc *p_ssc, uint32_t ul_id, uint32_t ul_value)
+{
+	switch (ul_id) {
+	case COMPARE_ID0:
+		p_ssc->SSC_RC0R = ul_value;
+		break;
+	case COMPARE_ID1:
+		p_ssc->SSC_RC1R = ul_value;
+		break;
+	}
+}
+
+/**
+ * \brief Get SSC Receive Compare Register.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param ul_id Compare register ID.
+ *
+ * \return Receive Compare Register value for the specified ul_id, otherwise SSC_RC_INVALID.
+ */
+uint32_t ssc_get_rx_compare(Ssc *p_ssc, uint32_t ul_id)
+{
+	switch (ul_id) {
+	case COMPARE_ID0:
+		return p_ssc->SSC_RC0R;
+	case COMPARE_ID1:
+		return p_ssc->SSC_RC1R;
+	default:
+		return SSC_RC_INVALID;
+	}
+}
+
+/**
+ * \brief Enable SSC interrupts.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param ul_sources Interrupts to be enabled.
+ */
+void ssc_enable_interrupt(Ssc *p_ssc, uint32_t ul_sources)
+{
+	p_ssc->SSC_IER = ul_sources;
+}
+
+/**
+ * \brief Disable SSC interrupts.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param ul_sources Interrupts to be enabled.
+ */
+void ssc_disable_interrupt(Ssc *p_ssc, uint32_t ul_sources)
+{
+	p_ssc->SSC_IDR = ul_sources;
+}
+
+/**
+ * \brief Read SSC interrupt mask.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \return The interrupt mask value.
+ */
+uint32_t ssc_get_interrupt_mask(Ssc *p_ssc)
+{
+	return p_ssc->SSC_IMR;
+}
+
+/**
+ * \brief Read SSC status.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \return The SSC status value.
+ */
+uint32_t ssc_get_status(Ssc *p_ssc)
+{
+	return p_ssc->SSC_SR;
+}
+
+/**
+ * \brief Check if data has been loaded in SSC_THR and is waiting to be loaded
+ * in the Transmit Shift Register (TSR).
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \retval SSC_RC_YES There is no data in the SSC_THR.
+ * \retval SSC_RC_NO There is one data in the SSC_THR.
+ */
+uint32_t ssc_is_tx_ready(Ssc *p_ssc)
+{
+	if (p_ssc->SSC_SR & SSC_SR_TXRDY) {
+		return SSC_RC_YES;
+	}
+	return SSC_RC_NO;
+}
+
+/**
+ * \brief Check if the last data written in SSC_THR has been loaded in TSR
+ * and the last data loaded in TSR has been transmitted.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \retval SSC_RC_YES Both of the two registers are empty.
+ * \retval SSC_RC_NO At least one of the two registers is not empty.
+ */
+uint32_t ssc_is_tx_empty(Ssc *p_ssc)
+{
+	if (p_ssc->SSC_SR & SSC_SR_TXEMPTY) {
+		return SSC_RC_YES;
+	}
+	return SSC_RC_NO;
+}
+
+/**
+ * \brief Check if data has been received and loaded in SSC_RHR.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \retval SSC_RC_YES There is one data in the SSC_RHR.
+ * \retval SSC_RC_NO There is no data in the SSC_RHR.
+ */
+uint32_t ssc_is_rx_ready(Ssc *p_ssc)
+{
+	if (p_ssc->SSC_SR & SSC_SR_RXRDY) {
+		return SSC_RC_YES;
+	}
+	return SSC_RC_NO;
+}
+
+/**
+ * \brief Check if transmitter is enabled.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \retval SSC_RC_YES The transmitter is enabled.
+ * \retval SSC_RC_NO The transmitter is disabled.
+ */
+uint32_t ssc_is_tx_enabled(Ssc *p_ssc)
+{
+	if (p_ssc->SSC_SR & SSC_SR_TXEN) {
+		return SSC_RC_YES;
+	}
+	return SSC_RC_NO;
+}
+
+/**
+ * \brief Check if receiver is enabled.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \retval SSC_RC_YES The receiver is enabled.
+ * \retval SSC_RC_NO The receiver is disabled.
+ */
+uint32_t ssc_is_rx_enabled(Ssc *p_ssc)
+{
+	if (p_ssc->SSC_SR & SSC_SR_RXEN) {
+		return SSC_RC_YES;
+	}
+	return SSC_RC_NO;
+}
+
+#if (SAM3S_SERIES) || (SAM4S_SERIES)
+/**
+ * \brief Check if one receive buffer is filled.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \retval SSC_RC_YES Receive Counter has reached zero.
+ * \retval SSC_RC_NO Data is written on the Receive Counter Register or
+ * Receive Next Counter Register.
+ */
+uint32_t ssc_is_rx_buf_end(Ssc *p_ssc)
+{
+	if (p_ssc->SSC_SR & SSC_SR_ENDRX) {
+		return SSC_RC_YES;
+	}
+	return SSC_RC_NO;
+}
+
+/**
+ * \brief Check if the register SSC_TCR has reached 0.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \retval SSC_RC_YES The register SSC_TCR has reached 0.
+ * \retval SSC_RC_NO The register SSC_TCR hasn't reached 0.
+ */
+uint32_t ssc_is_tx_buf_end(Ssc *p_ssc)
+{
+	if (p_ssc->SSC_SR & SSC_SR_ENDTX) {
+		return SSC_RC_YES;
+	}
+	return SSC_RC_NO;
+}
+
+/**
+ * \brief Check if both receive buffers are full.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \retval SSC_RC_YES Both of the two receive buffers have reached 0.
+ * \retval SSC_RC_NO One of the two receive buffers hasn't reached 0.
+ */
+uint32_t ssc_is_rx_buf_full(Ssc *p_ssc)
+{
+	if (p_ssc->SSC_SR & SSC_SR_RXBUFF) {
+		return SSC_RC_YES;
+	}
+	return SSC_RC_NO;
+}
+
+/**
+ * \brief Check if both transmit buffers are empty.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \retval SSC_RC_YES Both of the two transmit buffers have reached 0.
+ * \retval SSC_RC_NO One of the two transmit buffers hasn't reached 0.
+ */
+uint32_t ssc_is_tx_buf_empty(Ssc *p_ssc)
+{
+	if (p_ssc->SSC_SR & SSC_SR_TXBUFE) {
+		return SSC_RC_YES;
+	}
+	return SSC_RC_NO;
+}
+
+/**
+ * \brief Get SSC PDC registers base address.
+ *
+ * \param p_ssc Pointer to SSC registers set instance.
+ *
+ * \return SSC PDC registers base address for PDC driver to access.
+ */
+Pdc *ssc_get_pdc_base(Ssc *p_ssc)
+{
+	return (Pdc *)&(p_ssc->SSC_RPR);
+}
+#endif // (SAM3S_SERIES) || (SAM4S_SERIES)
+
+/**
+ * \brief Write to SSC Transmit Holding Register.
+ * Send data through SSC Data frame.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param ul_frame Frame data to be transmitted.
+ *
+ * \retval SSC_RC_ERROR Time-out.
+ * \retval SSC_RC_OK Success.
+ *
+ */
+uint32_t ssc_write(Ssc *p_ssc, uint32_t ul_frame)
+{
+	uint32_t ul_timeout = SSC_DEFAULT_TIMEOUT;
+
+	while (!(p_ssc->SSC_SR & SSC_SR_TXEMPTY)) {
+		if (!ul_timeout--) {
+			return SSC_RC_ERROR;
+		}
+	}
+
+	p_ssc->SSC_THR = ul_frame;
+	return SSC_RC_OK;
+}
+
+/**
+ * \brief Read from SSC Receive Holding Register.
+ * Read data that is received in SSC Data frame.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param ul_data Pointer to the location where to store the received data.
+ *
+ * \retval SSC_RC_ERROR Time-out.
+ * \retval SSC_RC_OK Success.
+ */
+uint32_t ssc_read(Ssc *p_ssc, uint32_t *ul_data)
+{
+	uint32_t ul_timeout = SSC_DEFAULT_TIMEOUT;
+
+	while (!(p_ssc->SSC_SR & SSC_SR_RXRDY)) {
+		if (!ul_timeout--) {
+			return SSC_RC_ERROR;
+		}
+	}
+
+	*ul_data = p_ssc->SSC_RHR;
+	return SSC_RC_OK;
+}
+
+/**
+ * \brief Write to SSC Transmit Synchronization Holding Register.
+ * Send data through SSC Synchronization frame. If there is sync data that needs to be
+ * transmitted, call this function first to send out the sync data, and then call the
+ * ssc_write() function to send out application data.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param ul_frame Frame Synchronization data.
+ */
+void ssc_write_sync_data(Ssc *p_ssc, uint32_t ul_frame)
+{
+	p_ssc->SSC_TSHR = ul_frame;
+}
+
+/**
+ * \brief Read from SSC Receive Synchronization Holding Register.
+ * Read data that is received in SSC Synchronization frame. When the sync data is actually
+ * used, after successfully reading the application data by calling ssc_read(), call
+ * this function, and the return sync data is useful.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \return Current RSHR value.
+ */
+uint32_t ssc_read_sync_data(Ssc *p_ssc)
+{
+	return p_ssc->SSC_RSHR;
+}
+
+#if (SAM3XA_SERIES || SAM3U_SERIES)
+/**
+ * \brief Get Transmit address for DMA operation.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \return Transmitting address for DMA access.
+ */
+void *ssc_get_tx_access(Ssc *p_ssc)
+{
+	return (void *)&(p_ssc->SSC_THR);
+}
+
+/**
+ * \brief Get Receive address for DMA operation.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \return Transmitting address for DMA access.
+ */
+void *ssc_get_rx_access(Ssc *p_ssc)
+{
+	return (void *)&(p_ssc->SSC_RHR);
+}
+#endif // (SAM3XA_SERIES || SAM3U_SERIES)
+
+/**
+ * \brief Enable or disable write protection of SSC registers.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ * \param ul_enable 1 to enable, 0 to disable.
+ */
+void ssc_set_writeprotect(Ssc *p_ssc, uint32_t ul_enable)
+{
+	if (ul_enable) {
+		p_ssc->SSC_WPMR = SSC_WPKEY | SSC_WPMR_WPEN;
+	} else {
+		p_ssc->SSC_WPMR = SSC_WPKEY;
+	}
+}
+
+/**
+ * \brief Indicate write protect status.
+ *
+ * \param p_ssc Pointer to an SSC instance.
+ *
+ * \return 0 if the peripheral is not protected. Write Protect Violation Status otherwise.
+ */
+uint32_t ssc_get_writeprotect_status(Ssc *p_ssc)
+{
+	uint32_t ul_reg_val;
+
+	ul_reg_val = p_ssc->SSC_WPMR;
+	if (ul_reg_val & SSC_WPMR_WPEN) {
+		return (ul_reg_val & SSC_WPSR_WPVSRC_Msk) >> SSC_WPSR_WPVSRC_Pos;
+	} else {
+		return 0;
+	}
+}
+
+//@}
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
diff --git a/hardware/digistump/sam/system/libsam/source/tc.c b/hardware/digistump/sam/system/libsam/source/tc.c
new file mode 100644
index 0000000..24bdcb1
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/tc.c
@@ -0,0 +1,236 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Implementation of Timer Counter (TC).
+ *
+ */
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+
+/*------------------------------------------------------------------------------
+ *         Global functions
+ *------------------------------------------------------------------------------*/
+
+/**
+ * \brief Configures a Timer Counter Channel
+ *
+ * Configures a Timer Counter to operate in the given mode. Timer is stopped
+ * after configuration and must be restarted with TC_Start(). All the
+ * interrupts of the timer are also disabled.
+ *
+ * \param pTc  Pointer to a Tc instance.
+ * \param channel Channel number.
+ * \param mode  Operating mode (TC_CMR value).
+ */
+extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode )
+{
+    TcChannel* pTcCh ;
+
+    assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;
+    pTcCh = pTc->TC_CHANNEL+dwChannel ;
+
+    /*  Disable TC clock */
+    pTcCh->TC_CCR = TC_CCR_CLKDIS ;
+
+    /*  Disable interrupts */
+    pTcCh->TC_IDR = 0xFFFFFFFF ;
+
+    /*  Clear status register */
+    pTcCh->TC_SR ;
+
+    /*  Set mode */
+    pTcCh->TC_CMR = dwMode ;
+}
+
+/**
+ * \brief Reset and Start the TC Channel
+ *
+ * Enables the timer clock and performs a software reset to start the counting.
+ *
+ * \param pTc  Pointer to a Tc instance.
+ * \param dwChannel Channel number.
+ */
+extern void TC_Start( Tc *pTc, uint32_t dwChannel )
+{
+    TcChannel* pTcCh ;
+
+    assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;
+
+    pTcCh = pTc->TC_CHANNEL+dwChannel ;
+    pTcCh->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG ;
+}
+
+/**
+ * \brief Stop TC Channel
+ *
+ * Disables the timer clock, stopping the counting.
+ *
+ * \param pTc     Pointer to a Tc instance.
+ * \param dwChannel Channel number.
+ */
+extern void TC_Stop(Tc *pTc, uint32_t dwChannel )
+{
+    TcChannel* pTcCh ;
+
+    assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ;
+
+    pTcCh = pTc->TC_CHANNEL+dwChannel ;
+    pTcCh->TC_CCR = TC_CCR_CLKDIS ;
+}
+
+/**
+ * \brief Find best MCK divisor
+ *
+ * Finds the best MCK divisor given the timer frequency and MCK. The result
+ * is guaranteed to satisfy the following equation:
+ * \code
+ *   (MCK / (DIV * 65536)) <= freq <= (MCK / DIV)
+ * \endcode
+ * with DIV being the highest possible value.
+ *
+ * \param dwFreq  Desired timer frequency.
+ * \param dwMCk  Master clock frequency.
+ * \param dwDiv  Divisor value.
+ * \param dwTcClks  TCCLKS field value for divisor.
+ * \param dwBoardMCK  Board clock frequency.
+ *
+ * \return 1 if a proper divisor has been found, otherwise 0.
+ */
+extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK )
+{
+    const uint32_t adwDivisors[5] = { 2, 8, 32, 128, dwBoardMCK / 32768 } ;
+
+    uint32_t dwIndex = 0 ;
+
+    /*  Satisfy lower bound */
+    while ( dwFreq < ((dwMCk / adwDivisors[dwIndex]) / 65536) )
+    {
+        dwIndex++ ;
+
+        /*  If no divisor can be found, return 0 */
+        if ( dwIndex == (sizeof( adwDivisors )/sizeof( adwDivisors[0] ))  )
+        {
+            return 0 ;
+        }
+    }
+
+    /*  Try to maximize DIV while satisfying upper bound */
+    while ( dwIndex < 4 )
+    {
+
+        if ( dwFreq > (dwMCk / adwDivisors[dwIndex + 1]) )
+        {
+            break ;
+        }
+        dwIndex++ ;
+    }
+
+    /*  Store results */
+    if ( dwDiv )
+    {
+        *dwDiv = adwDivisors[dwIndex] ;
+    }
+    if ( dwTcClks )
+    {
+        *dwTcClks = dwIndex ;
+    }
+
+    return 1 ;
+}
+
+/**
+ * \brief Read Timer Counter Counter Value on the selected TC & channel.
+ *
+ * \param p_tc Pointer to a TC instance.
+ * \param ul_channel Channel to configure.
+ *
+ * \return RC value.
+ */
+uint32_t TC_ReadCV(Tc *p_tc, uint32_t ul_channel){
+	return p_tc->TC_CHANNEL[ul_channel].TC_CV;
+}
+
+/**
+ * \brief Get current status on the selected channel.
+ *
+ * \param p_tc Pointer to a TC instance.
+ * \param ul_channel Channel to configure.
+ *
+ * \return The current TC status.
+ */
+uint32_t TC_GetStatus(Tc *p_tc, uint32_t ul_channel)
+{
+	TcChannel *tc_channel;
+
+	tc_channel = p_tc->TC_CHANNEL + ul_channel;
+	return tc_channel->TC_SR;
+}
+
+/**
+ * \brief Set RA on the selected channel.
+ *
+ * \param tc Pointer to a TC instance.
+ * \param chan Channel to configure.
+ * \param v New value for RA.
+ */
+void TC_SetRA(Tc *tc, uint32_t chan, uint32_t v) {
+	tc->TC_CHANNEL[chan].TC_RA = v;
+}
+
+/**
+ * \brief Set RB on the selected channel.
+ *
+ * \param tc Pointer to a TC instance.
+ * \param chan Channel to configure.
+ * \param v New value for RB.
+ */
+void TC_SetRB(Tc *tc, uint32_t chan, uint32_t v) {
+	tc->TC_CHANNEL[chan].TC_RB = v;
+}
+
+/**
+ * \brief Set RC on the selected channel.
+ *
+ * \param tc Pointer to a TC instance.
+ * \param chan Channel to configure.
+ * \param v New value for RC.
+ */
+void TC_SetRC(Tc *tc, uint32_t chan, uint32_t v) {
+	tc->TC_CHANNEL[chan].TC_RC = v;
+}
+
diff --git a/hardware/digistump/sam/system/libsam/source/timetick.c b/hardware/digistump/sam/system/libsam/source/timetick.c
new file mode 100644
index 0000000..1661dca
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/timetick.c
@@ -0,0 +1,118 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *  Implement simple system tick usage.
+ */
+
+/*----------------------------------------------------------------------------
+ *         Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+/*----------------------------------------------------------------------------
+ *         Local variables
+ *----------------------------------------------------------------------------*/
+
+/** Tick Counter united by ms */
+static volatile uint32_t _dwTickCount=0 ;
+
+/*----------------------------------------------------------------------------
+ *         Exported Functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ *  \brief Handler for Sytem Tick interrupt.
+ */
+extern void TimeTick_Increment( void )
+{
+    _dwTickCount++ ;
+}
+
+/**
+ *  \brief Configures the SAM3 SysTick & reset tickCount.
+ *  Systick interrupt handler will generates 1ms interrupt and increase a
+ *  tickCount.
+ *  \param dwNew_MCK  Current master clock.
+ */
+extern uint32_t TimeTick_Configure( uint32_t dwNew_MCK )
+{
+    _dwTickCount = 0 ;
+
+    return SysTick_Config( dwNew_MCK/1000 ) ;
+}
+
+/**
+ *  \brief Get current Tick Count, in ms.
+ */
+extern uint32_t GetTickCount( void )
+{
+    return _dwTickCount ;
+}
+
+/**
+ *  \brief Sync Wait for several ms
+ */
+extern void Wait( volatile uint32_t dwMs )
+{
+    uint32_t dwStart ;
+    uint32_t dwCurrent ;
+
+    dwStart = _dwTickCount ;
+    do
+    {
+        dwCurrent = _dwTickCount ;
+    } while ( dwCurrent - dwStart < dwMs ) ;
+}
+
+/**
+ *  \brief Sync Sleep for several ms
+ */
+extern void Sleep( volatile uint32_t dwMs )
+{
+    uint32_t dwStart ;
+    uint32_t dwCurrent ;
+
+    dwStart = _dwTickCount ;
+
+    do
+    {
+        dwCurrent = _dwTickCount ;
+
+        if ( dwCurrent - dwStart > dwMs )
+        {
+            break ;
+        }
+
+        __WFI() ;
+    } while( 1 ) ;
+}
+
diff --git a/hardware/digistump/sam/system/libsam/source/trng.c b/hardware/digistump/sam/system/libsam/source/trng.c
new file mode 100644
index 0000000..747f73d
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/trng.c
@@ -0,0 +1,160 @@
+/**
+ * \file
+ *
+ * \brief TRNG driver for SAM.
+ *
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \defgroup group_sam_drivers_trng TRNG - True Random Number Generator
+ *
+ * Driver for the TRNG (True Random Number Generator). This driver provides access
+ * to the main features of the TRNG controller.
+ *
+ * \{
+ */
+
+#include "../chip.h"
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+#if SAM3XA_SERIES
+
+/* TRNG Security Key Value */
+#define TRNG_KEY  0x524E47
+
+/**
+ * \brief Enable TRNG.
+ *
+ * \param p_trng  Pointer to a TRNG instance.
+ *
+ */
+void trng_enable(Trng *p_trng)
+{
+	p_trng->TRNG_CR = TRNG_CR_ENABLE | TRNG_CR_KEY(TRNG_KEY);
+}
+
+/**
+ * \brief Disable TRNG.
+ *
+ * \param p_trng  Pointer to a TRNG instance.
+ *
+ */
+void trng_disable(Trng *p_trng)
+{
+	p_trng->TRNG_CR = TRNG_CR_KEY(TRNG_KEY);
+}
+
+/**
+ * \brief Enable TRNG interrupt.
+ *
+ * \param p_trng  Pointer to a TRNG instance.
+ *
+ */
+void trng_enable_interrupt(Trng *p_trng)
+{
+	p_trng->TRNG_IER = TRNG_IER_DATRDY;
+}
+
+/**
+ * \brief Disable TRNG interrupt.
+ *
+ * \param p_trng  Pointer to a TRNG instance.
+ *
+ */
+void trng_disable_interrupt(Trng *p_trng)
+{
+	p_trng->TRNG_IDR = TRNG_IER_DATRDY;
+}
+
+/**
+ * \brief Get TRNG interrupt mask.
+ *
+ * \param p_trng  Pointer to a TRNG instance.
+ *
+ * \retval The interrupt mask value.
+ */
+uint32_t trng_get_interrupt_mask(Trng *p_trng)
+{
+	return p_trng->TRNG_IMR;
+}
+
+/**
+ * \brief Get TRNG interrupt status.
+ *
+ * \param p_trng  Pointer to a TRNG instance.
+ *
+ * \retval The interrupt status value.
+ */
+uint32_t trng_get_interrupt_status(Trng *p_trng)
+{
+	return p_trng->TRNG_ISR;
+}
+
+/**
+ * \brief Read TRNG output data.
+ *
+ * \param p_trng  Pointer to a TRNG instance.
+ *
+ * \retval The output data value.
+ */
+uint32_t trng_read_output_data(Trng *p_trng)
+{
+	return p_trng->TRNG_ODATA;
+}
+
+#endif // SAM3XA_SERIES
+
+/// @cond 0
+/**INDENT-OFF**/
+#ifdef __cplusplus
+}
+#endif
+/**INDENT-ON**/
+/// @endcond
+
+/**
+ * \}
+ */
diff --git a/hardware/digistump/sam/system/libsam/source/twi.c b/hardware/digistump/sam/system/libsam/source/twi.c
new file mode 100644
index 0000000..2a961f6
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/twi.c
@@ -0,0 +1,380 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup twi_module Working with TWI
+ * The TWI driver provides the interface to configure and use the TWI
+ * peripheral.
+ *
+ * \section Usage
+ * 
    
+ * 
  •  Configures a TWI peripheral to operate in master mode, at the given
+ * frequency (in Hz) using TWI_Configure(). 
    • 
+ * 
  •  Sends a STOP condition on the TWI using TWI_Stop().
    • 
+ * 
  •  Starts a read operation on the TWI bus with the specified slave using
+ * TWI_StartRead(). Data must then be read using TWI_ReadByte() whenever
+ * a byte is available (poll using TWI_ByteReceived()).
    • 
+ * 
  •  Starts a write operation on the TWI to access the selected slave using
+ * TWI_StartWrite(). A byte of data must be provided to start the write;
+ * other bytes are written next.
    • 
+ * 
  •  Sends a byte of data to one of the TWI slaves on the bus using TWI_WriteByte().
+ * This function must be called once before TWI_StartWrite() with the first byte of data
+ * to send, then it shall be called repeatedly after that to send the remaining bytes.
    • 
+ * 
  •  Check if a byte has been received and can be read on the given TWI
+ * peripheral using TWI_ByteReceived().<
+ * Check if a byte has been sent using TWI_ByteSent().
    • 
+ * 
  •  Check if the current transmission is complete (the STOP has been sent)
+ * using TWI_TransferComplete().
    • 
+ * 
  •  Enables & disable the selected interrupts sources on a TWI peripheral
+ * using TWI_EnableIt() and TWI_DisableIt().
    • 
+ * 
  •  Get current status register of the given TWI peripheral using
+ * TWI_GetStatus(). Get current status register of the given TWI peripheral, but
+ * masking interrupt sources which are not currently enabled using
+ * TWI_GetMaskedStatus().
    • 
+ * 

+ * For more accurate information, please look at the TWI section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref twi.c\n
+ * \ref twi.h.\n
+*/
+/*@{*/
+/*@}*/
+
+/**
+ * \file
+ *
+ * Implementation of Two Wire Interface (TWI).
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Configures a TWI peripheral to operate in master mode, at the given
+ * frequency (in Hz). The duty cycle of the TWI clock is set to 50%.
+ * \param pTwi  Pointer to an Twi instance.
+ * \param twck  Desired TWI clock frequency.
+ * \param mck  Master clock frequency.
+ */
+void TWI_ConfigureMaster( Twi* pTwi, uint32_t dwTwCk, uint32_t dwMCk )
+{
+    uint32_t dwCkDiv = 0 ;
+    uint32_t dwClDiv ;
+    uint32_t dwOk = 0 ;
+
+    assert( pTwi ) ;
+
+    /* SVEN: TWI Slave Mode Enabled */
+    pTwi->TWI_CR = TWI_CR_SVEN ;
+    /* Reset the TWI */
+    pTwi->TWI_CR = TWI_CR_SWRST ;
+    pTwi->TWI_RHR ;
+
+    /* TWI Slave Mode Disabled, TWI Master Mode Disabled. */
+    pTwi->TWI_CR = TWI_CR_SVDIS ;
+    pTwi->TWI_CR = TWI_CR_MSDIS ;
+
+    /* Set master mode */
+    pTwi->TWI_CR = TWI_CR_MSEN ;
+
+    /* Configure clock */
+    while ( !dwOk )
+    {
+        dwClDiv = ((dwMCk / (2 * dwTwCk)) - 4) / (1<TWI_CWGR = 0 ;
+    pTwi->TWI_CWGR = (dwCkDiv << 16) | (dwClDiv << 8) | dwClDiv ;
+}
+
+/**
+ * \brief Configures a TWI peripheral to operate in slave mode.
+ * \param pTwi  Pointer to an Twi instance.
+ * \param slaveAddress Slave address.
+ */
+void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress)
+{
+    uint32_t i;
+
+    /* TWI software reset */
+    pTwi->TWI_CR = TWI_CR_SWRST;
+    pTwi->TWI_RHR;
+
+    /* Wait at least 10 ms */
+    for (i=0; i < 1000000; i++);
+
+    /* TWI Slave Mode Disabled, TWI Master Mode Disabled*/
+    pTwi->TWI_CR = TWI_CR_SVDIS | TWI_CR_MSDIS;
+
+    /* Configure slave address. */
+    pTwi->TWI_SMR = 0;
+    pTwi->TWI_SMR = TWI_SMR_SADR(slaveAddress);
+
+    /* SVEN: TWI Slave Mode Enabled */
+    pTwi->TWI_CR = TWI_CR_SVEN;
+
+    /* Wait at least 10 ms */
+    for (i=0; i < 1000000; i++);
+    assert( (pTwi->TWI_CR & TWI_CR_SVDIS)!= TWI_CR_SVDIS ) ;
+}
+
+/**
+ * \brief Sends a STOP condition on the TWI.
+ * \param pTwi  Pointer to an Twi instance.
+ */
+void TWI_Stop( Twi *pTwi )
+{
+    assert( pTwi != NULL ) ;
+
+    pTwi->TWI_CR = TWI_CR_STOP;
+}
+
+/**
+ * \brief Starts a read operation on the TWI bus with the specified slave, it returns
+ * immediately. Data must then be read using TWI_ReadByte() whenever a byte is
+ * available (poll using TWI_ByteReceived()).
+ * \param pTwi  Pointer to an Twi instance.
+ * \param address  Slave address on the bus.
+ * \param iaddress  Optional internal address bytes.
+ * \param isize  Number of internal address bytes.
+ */
+void TWI_StartRead(
+    Twi *pTwi,
+    uint8_t address,
+    uint32_t iaddress,
+    uint8_t isize)
+{
+    assert( pTwi != NULL ) ;
+    assert( (address & 0x80) == 0 ) ;
+    assert( (iaddress & 0xFF000000) == 0 ) ;
+    assert( isize < 4 ) ;
+
+    /* Set slave address and number of internal address bytes. */
+    pTwi->TWI_MMR = 0;
+    pTwi->TWI_MMR = (isize << 8) | TWI_MMR_MREAD | (address << 16);
+
+    /* Set internal address bytes */
+    pTwi->TWI_IADR = 0;
+    pTwi->TWI_IADR = iaddress;
+
+    /* Send START condition */
+    pTwi->TWI_CR = TWI_CR_START;
+}
+
+/**
+ * \brief Reads a byte from the TWI bus. The read operation must have been started
+ * using TWI_StartRead() and a byte must be available (check with TWI_ByteReceived()).
+ * \param pTwi  Pointer to an Twi instance.
+ * \return byte read.
+ */
+uint8_t TWI_ReadByte(Twi *pTwi)
+{
+    assert( pTwi != NULL ) ;
+
+    return pTwi->TWI_RHR;
+}
+
+/**
+ * \brief Sends a byte of data to one of the TWI slaves on the bus.
+ * \note This function must be called once before TWI_StartWrite() with
+ * the first byte of data  to send, then it shall be called repeatedly
+ * after that to send the remaining bytes.
+ * \param pTwi  Pointer to an Twi instance.
+ * \param byte  Byte to send.
+ */
+void TWI_WriteByte(Twi *pTwi, uint8_t byte)
+{
+    assert( pTwi != NULL ) ;
+
+    pTwi->TWI_THR = byte;
+}
+
+/**
+ * \brief Starts a write operation on the TWI to access the selected slave, then
+ *  returns immediately. A byte of data must be provided to start the write;
+ * other bytes are written next.
+ * after that to send the remaining bytes.
+ * \param pTwi  Pointer to an Twi instance.
+ * \param address  Address of slave to acccess on the bus.
+ * \param iaddress  Optional slave internal address.
+ * \param isize  Number of internal address bytes.
+ * \param byte  First byte to send.
+ */
+void TWI_StartWrite(
+    Twi *pTwi,
+    uint8_t address,
+    uint32_t iaddress,
+    uint8_t isize,
+    uint8_t byte)
+{
+    assert( pTwi != NULL ) ;
+    assert( (address & 0x80) == 0 ) ;
+    assert( (iaddress & 0xFF000000) == 0 ) ;
+    assert( isize < 4 ) ;
+
+    /* Set slave address and number of internal address bytes. */
+    pTwi->TWI_MMR = 0;
+    pTwi->TWI_MMR = (isize << 8) | (address << 16);
+
+    /* Set internal address bytes. */
+    pTwi->TWI_IADR = 0;
+    pTwi->TWI_IADR = iaddress;
+
+    /* Write first byte to send.*/
+    TWI_WriteByte(pTwi, byte);
+}
+
+/**
+ * \brief Check if a byte have been receiced from TWI.
+ * \param pTwi  Pointer to an Twi instance.
+ * \return 1 if a byte has been received and can be read on the given TWI
+ * peripheral; otherwise, returns 0. This function resets the status register.
+ */
+uint8_t TWI_ByteReceived(Twi *pTwi)
+{
+    return ((pTwi->TWI_SR & TWI_SR_RXRDY) == TWI_SR_RXRDY);
+}
+
+/**
+ * \brief Check if a byte have been sent to TWI.
+ * \param pTwi  Pointer to an Twi instance.
+ * \return 1 if a byte has been sent  so another one can be stored for
+ * transmission; otherwise returns 0. This function clears the status register.
+ */
+uint8_t TWI_ByteSent(Twi *pTwi)
+{
+    return ((pTwi->TWI_SR & TWI_SR_TXRDY) == TWI_SR_TXRDY);
+}
+
+/**
+ * \brief Check if current transmission is complet.
+ * \param pTwi  Pointer to an Twi instance.
+ * \return  1 if the current transmission is complete (the STOP has been sent);
+ * otherwise returns 0.
+ */
+uint8_t TWI_TransferComplete(Twi *pTwi)
+{
+    return ((pTwi->TWI_SR & TWI_SR_TXCOMP) == TWI_SR_TXCOMP);
+}
+
+/**
+ * \brief Enables the selected interrupts sources on a TWI peripheral.
+ * \param pTwi  Pointer to an Twi instance.
+ * \param sources  Bitwise OR of selected interrupt sources.
+ */
+void TWI_EnableIt(Twi *pTwi, uint32_t sources)
+{
+    assert( pTwi != NULL ) ;
+    assert( (sources & 0xFFFFF088) == 0 ) ;
+
+    pTwi->TWI_IER = sources;
+}
+
+/**
+ * \brief Disables the selected interrupts sources on a TWI peripheral.
+ * \param pTwi  Pointer to an Twi instance.
+ * \param sources  Bitwise OR of selected interrupt sources.
+ */
+void TWI_DisableIt(Twi *pTwi, uint32_t sources)
+{
+    assert( pTwi != NULL ) ;
+    assert( (sources & 0xFFFFF088) == 0 ) ;
+
+    pTwi->TWI_IDR = sources;
+}
+
+/**
+ * \brief Get the current status register of the given TWI peripheral.
+ * \note This resets the internal value of the status register, so further
+ * read may yield different values.
+ * \param pTwi  Pointer to an Twi instance.
+ * \return  TWI status register.
+ */
+uint32_t TWI_GetStatus(Twi *pTwi)
+{
+    assert( pTwi != NULL ) ;
+
+    return pTwi->TWI_SR;
+}
+
+/**
+ * \brief Returns the current status register of the given TWI peripheral, but
+ * masking interrupt sources which are not currently enabled.
+ * \note This resets the internal value of the status register, so further
+ * read may yield different values.
+ * \param pTwi  Pointer to an Twi instance.
+ */
+uint32_t TWI_GetMaskedStatus(Twi *pTwi)
+{
+    uint32_t status;
+
+    assert( pTwi != NULL ) ;
+
+    status = pTwi->TWI_SR;
+    status &= pTwi->TWI_IMR;
+
+    return status;
+}
+
+/**
+ * \brief  Sends a STOP condition. STOP Condition is sent just after completing
+ *  the current byte transmission in master read mode.
+ * \param pTwi  Pointer to an Twi instance.
+ */
+void TWI_SendSTOPCondition(Twi *pTwi)
+{
+    assert( pTwi != NULL ) ;
+
+    pTwi->TWI_CR |= TWI_CR_STOP;
+}
+
diff --git a/hardware/digistump/sam/system/libsam/source/udp.c b/hardware/digistump/sam/system/libsam/source/udp.c
new file mode 100644
index 0000000..7d90f3e
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/udp.c
@@ -0,0 +1,38 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "chip.h"
+
+#if SAM3S_SERIES || SAM4S_SERIES
+
+#include "USB_device.h"
+#include "udp.h"
+
+
+#endif /* SAM3S_SERIES || SAM4S_SERIES */
diff --git a/hardware/digistump/sam/system/libsam/source/udphs.c b/hardware/digistump/sam/system/libsam/source/udphs.c
new file mode 100644
index 0000000..0655551
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/udphs.c
@@ -0,0 +1,471 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "chip.h"
+
+#if 0 //SAM3U_SERIES
+
+#include "USB_device.h"
+#include "udphs.h"
+
+/// Max size of the FMA FIFO
+#define EPT_VIRTUAL_SIZE  (16384u)
+#define SHIFT_INTERUPT    (8u)
+
+int _cmark;
+int _cend;
+
+// Global variable for endpoint number
+unsigned int NumEndpoint=0;
+
+
+void USBD_WaitIN(void)
+{
+//	while (!(UEINTX & (1<UDPHS_EPT[0].UDPHS_EPTSTA & UDPHS_EPTSTA_TX_PK_RDY));
+}
+
+void USBD_WaitOUT(void)
+{
+//	while (!(UEINTX & (1<UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & UDPHS_EPTSTA_RX_BK_RDY));
+}
+
+void USBD_ClearIN(void)
+{
+//	UEINTX = ~(1<UDPHS_EPT[NumEndpoint].UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_TX_COMPLT;
+}
+
+void USBD_ClearOUT(void)
+{
+//	UEINTX = ~(1<UDPHS_EPT[NumEndpoint].UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_BK_RDY;
+}
+
+uint8_t USBD_WaitForINOrOUT(void)
+{
+//	while (!(UEINTX & ((1<UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & (UDPHS_EPTSTA_RX_BK_RDY | UDPHS_EPTSTA_TX_PK_RDY)));
+  return (UDPHS->UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & UDPHS_EPTSTA_RX_BK_RDY) == 0;
+}
+
+void USBD_ClearRxFlag(unsigned char bEndpoint)
+{
+  UDPHS->UDPHS_EPT[NumEndpoint].UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_RX_BK_RDY;
+}
+
+void USBD_Stall(void)
+{
+//	UECONX = (1<UDPHS_EPT[NumEndpoint].UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_FRCESTALL;
+}
+
+uint8_t USBD_Stalled(void)
+{
+//	return UEINTX & (1<UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & UDPHS_EPTSTA_FRCESTALL));
+}
+
+uint8_t USBD_ReceivedSetupInt(void)
+{
+//	return UEINTX & (1<UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & UDPHS_EPTSTA_RX_SETUP) );
+}
+
+void USBD_ClearSetupInt(void)
+{
+//	UEINTX = ~((1<UDPHS_EPT[NumEndpoint].UDPHS_EPTCLRSTA = UDPHS_EPTSTA_RX_SETUP | UDPHS_EPTCLRSTA_RX_BK_RDY | UDPHS_EPTCLRSTA_TX_COMPLT;
+}
+
+uint8_t USBD_ReadWriteAllowed(void)
+{
+	//return UEINTX & (1<UOTGHS_DEVEPTISR[ep] & UOTGHS_DEVEPTISR_BYCT_Msk) >> UOTGHS_DEVEPTISR_BYCT_Pos);
+  // SAM3U //AT91C_UDPHS_BYTE_COUNT (0x7FF << 20)
+  return ((UDPHS->UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & UDPHS_EPTSTA_BYTE_COUNT_Msk) >> UDPHS_EPTSTA_BYTE_COUNT_Pos);
+}
+
+uint8_t USBD_FifoFree(void)
+{
+//	return UEINTX & (1<UDPHS_EPT[NumEndpoint].UDPHS_EPTSTA & UDPHS_EPTSTA_TX_PK_RDY ));
+}
+
+void USBD_ReleaseRX(void)
+{
+	UEINTX = 0x6B;	// FIFOCON=0 NAKINI=1 RWAL=1 NAKOUTI=0 RXSTPI=1 RXOUTI=0 STALLEDI=1 TXINI=1
+}
+
+void USBD_ReleaseTX()
+{
+	UEINTX = 0x3A;	// FIFOCON=0 NAKINI=0 RWAL=1 NAKOUTI=1 RXSTPI=1 RXOUTI=0 STALLEDI=1 TXINI=0
+}
+
+uint8_t USBD_FrameNumber(void)
+{
+	return UDFNUML;
+}
+
+uint8_t USBD_GetConfiguration(void)
+{
+	return _usbConfiguration;
+}
+
+
+
+void USBD_Recv(volatile uint8_t* data, uint8_t count)
+{
+  uint8_t     *pFifo;
+
+  pFifo = (uint8_t*)((uint32_t *)UDPHS_RAM_ADDR + (EPT_VIRTUAL_SIZE * NumEndpoint));
+
+  while (count--)
+  {
+    *data++ = pFifo[0];
+  }
+
+//	RXLED1;					// light the RX LED
+//	RxLEDPulse = TX_RX_LED_PULSE_MS;
+}
+
+uint8_t USBD_Recv8(void)
+{
+    uint8_t     *pFifo;
+
+//	RXLED1;					// light the RX LED
+//	RxLEDPulse = TX_RX_LED_PULSE_MS;
+
+    pFifo = (uint8_t*)((uint32_t *)UDPHS_RAM_ADDR + (EPT_VIRTUAL_SIZE * NumEndpoint));
+
+//	return UEDATX;
+    return (pFifo[0]);
+}
+
+void USBD_Send8(uint8_t d)
+{
+    uint8_t     *pFifo;
+    pFifo = (uint8_t*)((uint32_t *)UDPHS_RAM_ADDR + (EPT_VIRTUAL_SIZE * NumEndpoint));
+//	UEDATX = d;
+    pFifo[0] =d;
+}
+
+//	Blocking Send of data to an endpoint
+int USBD_Send(uint8_t ep, const void* d, int len)
+{
+	if (!_usbConfiguration)
+		return -1;
+
+	int r = len;
+	const uint8_t* data = (const uint8_t*)d;
+	uint8_t zero = ep & TRANSFER_ZERO;
+	uint8_t timeout = 250;		// 250ms timeout on send? TODO
+	while (len)
+	{
+		uint8_t n = USB_SendSpace(ep);
+		if (n == 0)
+		{
+			if (!(--timeout))
+				return -1;
+			delay(1);
+			continue;
+		}
+
+		if (n > len)
+			n = len;
+		len -= n;
+		{
+			SetEP(ep);
+			if (ep & TRANSFER_ZERO)
+			{
+				while (n--)
+					Send8(0);
+			}
+			else if (ep & TRANSFER_PGM)
+			{
+				while (n--)
+					Send8(*data++);
+			}
+			else
+			{
+				while (n--)
+					Send8(*data++);
+			}
+//			if (!ReadWriteAllowed() || ((len == 0) && (ep & TRANSFER_RELEASE)))	// Release full buffer
+//				ReleaseTX();
+		}
+	}
+	TXLED1;					// light the TX LED
+	TxLEDPulse = TX_RX_LED_PULSE_MS;
+	return r;
+}
+
+
+//	Space in send EP
+uint8_t USBD_SendSpace(uint8_t ep)
+{
+	SetEP(ep);
+	if (!ReadWriteAllowed())
+  {
+		return 0;
+  }
+
+	return 64 - FifoByteCount();
+}
+
+//	Number of bytes, assumes a rx endpoint
+uint8_t USBD_Available(uint8_t ep)
+{
+	SetEP(ep);
+
+	return FifoByteCount();
+}
+
+void USBD_InitEP(uint8_t index, uint8_t type, uint8_t size)
+{
+	UENUM = index;
+	UECONX = 1;
+	UECFG0X = type;
+	UECFG1X = size;
+}
+
+
+void USBD_InitEndpoints(void)
+{
+	for (uint8_t i = 1; i < sizeof(_initEndpoints); i++)
+	{
+        // Reset Endpoint Fifos
+        UDPHS->UDPHS_EPT[i].UDPHS_EPTCLRSTA = UDPHS_EPTCLRSTA_TOGGLESQ | UDPHS_EPTCLRSTA_FRCESTALL;
+        UDPHS->UDPHS_EPTRST = 1<UDPHS_EPT[i].UDPHS_EPTCFG = _initEndpoints[i];
+
+        while( (signed int)UDPHS_EPTCFG_EPT_MAPD != (signed int)((UDPHS->UDPHS_EPT[i].UDPHS_EPTCFG) & (unsigned int)UDPHS_EPTCFG_EPT_MAPD) )
+        ;
+        UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_EPT_ENABL;
+
+        //		UECFG1X = EP_DOUBLE_64;
+	}
+///\//	UERST = 0x7E;	// And reset them
+///\//	UERST = 0;
+}
+
+void USBD_InitControl(int end)
+{
+	SetEP(0);
+  UDPHS->UDPHS_EPT[0].UDPHS_EPTCFG = _initEndpoints[0];
+
+  while( (signed int)UDPHS_EPTCFG_EPT_MAPD != (signed int)((UDPHS->UDPHS_EPT[0].UDPHS_EPTCFG) & (unsigned int)UDPHS_EPTCFG_EPT_MAPD) )
+  ;
+
+  UDPHS->UDPHS_EPT[0].UDPHS_EPTCTLENB = UDPHS_EPTCTLENB_RX_BK_RDY
+                                       | UDPHS_EPTCTLENB_RX_SETUP
+                                       | UDPHS_EPTCTLENB_EPT_ENABL;
+
+	_cmark = 0;
+	_cend = end;
+}
+
+void UDPHS_Handler( void )
+{
+    unsigned int  status;
+    unsigned char numIT;
+
+    // Get interrupts status
+    status = UDPHS->UDPHS_INTSTA & UDPHS->UDPHS_IEN;
+
+    // Handle all UDPHS interrupts
+    while (status != 0) {
+
+        //	Start of Frame - happens every millisecond so we use it for TX and RX LED one-shot timing, too
+        if ((status & UDPHS_IEN_INT_SOF) != 0) {
+
+#ifdef CDC_ENABLED
+            USB_Flush(CDC_TX);				// Send a tx frame if found
+#endif
+
+            // check whether the one-shot period has elapsed.  if so, turn off the LED
+            if (TxLEDPulse && !(--TxLEDPulse))
+                TXLED0;
+            if (RxLEDPulse && !(--RxLEDPulse))
+                RXLED0;
+
+            // Acknowledge interrupt
+            UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_INT_SOF;
+            status &= ~UDPHS_IEN_INT_SOF;
+        }
+        // Suspend
+        // This interrupt is always treated last (hence the '==')
+        else if (status == UDPHS_IEN_DET_SUSPD) {
+
+            //UDPHS_DisableBIAS();
+
+            // Enable wakeup
+            UDPHS->UDPHS_IEN |= UDPHS_IEN_WAKE_UP | UDPHS_IEN_ENDOFRSM;
+            UDPHS->UDPHS_IEN &= ~UDPHS_IEN_DET_SUSPD;
+
+            // Acknowledge interrupt
+            UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_DET_SUSPD | UDPHS_CLRINT_WAKE_UP;
+
+            //UDPHS_DisableUsbClock();
+
+        }
+        // Resume
+        else if( ((status & UDPHS_IEN_WAKE_UP) != 0)      // line activity
+              || ((status & UDPHS_IEN_ENDOFRSM) != 0))  { // pc wakeup
+            {
+
+                //UDPHS_EnableUsbClock();
+                //UDPHS_EnableBIAS();
+
+                UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_WAKE_UP | UDPHS_CLRINT_ENDOFRSM
+                		| UDPHS_CLRINT_DET_SUSPD;
+
+                UDPHS->UDPHS_IEN |= UDPHS_IEN_ENDOFRSM | UDPHS_IEN_DET_SUSPD;
+                UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_WAKE_UP | UDPHS_CLRINT_ENDOFRSM;
+                UDPHS->UDPHS_IEN &= ~UDPHS_IEN_WAKE_UP;
+            }
+        }
+        // End of Reset
+        else if ((status & UDPHS_IEN_ENDRESET) == UDPHS_IEN_ENDRESET) {
+
+        	InitControl(0);	// init ep0
+            _usbConfiguration = 0;			// not configured yet
+            //UEIENX = 1 << RXSTPE;			// Enable interrupts for ep0
+
+            //UDPHS_ResetEndpoints();
+            //UDPHS_DisableEndpoints();
+            //USBD_ConfigureEndpoint(0);
+            UDPHS->UDPHS_IEN |= (1<UDPHS_CLRINT = UDPHS_CLRINT_WAKE_UP | UDPHS_CLRINT_DET_SUSPD;
+
+            //// Enable the Start Of Frame (SOF) interrupt if needed
+            UDPHS->UDPHS_IEN |= UDPHS_IEN_INT_SOF;
+
+            // Acknowledge end of bus reset interrupt
+            UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_ENDRESET;
+
+            UDPHS->UDPHS_IEN |= UDPHS_IEN_DET_SUSPD;
+        }
+        // Handle upstream resume interrupt
+        else if (status & UDPHS_IEN_UPSTR_RES) {
+
+            // - Acknowledge the IT
+            UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_UPSTR_RES;
+        }
+        // Endpoint interrupts
+        else {
+            // Handle endpoint interrupts
+            for (numIT = 0; numIT < NUM_IT_MAX; numIT++) {
+
+                if ((status & (1 << SHIFT_INTERUPT << numIT)) != 0) {
+                	USB_ISR();
+                    //EndpointHandler(numIT); // TODO: interrupt for bulk
+                }
+            }
+        }
+        // Retrieve new interrupt status
+        status = UDPHS->UDPHS_INTSTA & UDPHS->UDPHS_IEN;
+    }
+}
+
+void USBD_Attach( void )
+{/*
+	_usbConfiguration = 0;
+
+	//UHWCON = 0x01;						// power internal reg
+	//USBCON = (1<PMC_PCER = (1 << ID_UDPHS);
+    // Enable 480MHZ
+    //AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_PLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN;
+    CKGR->CKGR_UCKR |= ((0xf << 20) & (3 << 20)) | AT91C_CKGR_UPLLEN;
+    // Wait until UTMI PLL is locked
+    while ((PMC->PMC_SR & PMC_LOCKU) == 0);
+
+    // Reset and enable IP UDPHS
+    UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_EN_UDPHS;
+    UDPHS->UDPHS_CTRL |= UDPHS_CTRL_EN_UDPHS;
+
+	//USBCON = ((1<UDPHS_IEN = 0;
+    UDPHS->UDPHS_CLRINT = UDPHS_CLRINT_UPSTR_RES
+                                   | UDPHS_CLRINT_ENDOFRSM
+                                   | UDPHS_CLRINT_WAKE_UP
+                                   | UDPHS_CLRINT_ENDRESET
+                                   | UDPHS_CLRINT_INT_SOF
+                                   | UDPHS_CLRINT_MICRO_SOF
+                                   | UDPHS_CLRINT_DET_SUSPD;
+
+    // Enable interrupts for EOR (End of Reset), wake up and SOF (start of frame)
+    //UDIEN = (1<UDPHS_IEN = UDPHS_IEN_ENDOFRSM
+                                | UDPHS_IEN_WAKE_UP
+                                | UDPHS_IEN_DET_SUSPD;
+
+	// enable attach resistor
+	//UDCON = 0;
+    UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_DETACH;   // Pull Up on DP
+    UDPHS->UDPHS_CTRL |= UDPHS_CTRL_PULLD_DIS; // Disable Pull Down
+
+	TX_RX_LED_INIT;
+*/}
+
+void USBD_Detach( void )
+{
+  UDPHS->UDPHS_CTRL |= UDPHS_CTRL_DETACH; // detach
+  UDPHS->UDPHS_CTRL &= ~UDPHS_CTRL_PULLD_DIS; // Enable Pull Down
+}
+
+#endif /* SAM3U_SERIES */
diff --git a/hardware/digistump/sam/system/libsam/source/uotghs.c b/hardware/digistump/sam/system/libsam/source/uotghs.c
new file mode 100644
index 0000000..1fe00fc
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/uotghs.c
@@ -0,0 +1,42 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "chip.h"
+
+#if SAM3XA_SERIES
+
+void (*gpf_isr)(void) = (0UL);
+
+void UOTGHS_Handler( void )
+{
+	if (gpf_isr)
+		gpf_isr();
+}
+
+#endif /* SAM3XA_SERIES */
diff --git a/hardware/digistump/sam/system/libsam/source/uotghs_device.c b/hardware/digistump/sam/system/libsam/source/uotghs_device.c
new file mode 100644
index 0000000..6ffa357
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/uotghs_device.c
@@ -0,0 +1,334 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "chip.h"
+#include 
+
+#if SAM3XA_SERIES
+
+//#define TRACE_UOTGHS_DEVICE(x)	x
+#define TRACE_UOTGHS_DEVICE(x)
+
+extern void (*gpf_isr)(void);
+
+static volatile uint32_t ul_send_fifo_ptr[MAX_ENDPOINTS];
+static volatile uint32_t ul_recv_fifo_ptr[MAX_ENDPOINTS];
+
+void UDD_SetStack(void (*pf_isr)(void))
+{
+	gpf_isr = pf_isr;
+}
+
+uint32_t UDD_Init(void)
+{
+	uint32_t i;
+
+	for (i = 0; i < MAX_ENDPOINTS; ++i)
+	{
+		ul_send_fifo_ptr[i] = 0;
+		ul_recv_fifo_ptr[i] = 0;
+	}
+
+	// Enables the USB Clock
+	pmc_enable_periph_clk(ID_UOTGHS);
+	pmc_enable_upll_clock();
+	pmc_switch_udpck_to_upllck(0); // div=0+1
+	pmc_enable_udpck();
+
+	// Configure interrupts
+	NVIC_SetPriority((IRQn_Type) ID_UOTGHS, 0UL);
+	NVIC_EnableIRQ((IRQn_Type) ID_UOTGHS);
+
+	// Always authorize asynchrone USB interrupts to exit from sleep mode
+	//   for SAM3 USB wake up device except BACKUP mode
+	//pmc_set_fast_startup_input(PMC_FSMR_USBAL);
+
+	// ID pin not used then force device mode
+	otg_disable_id_pin();
+	otg_force_device_mode();
+
+	// Enable USB hardware
+	otg_disable_pad();
+	otg_enable_pad();
+	otg_enable();
+	otg_unfreeze_clock();
+
+	// Check USB clock
+	//while (!Is_otg_clock_usable())
+	//	;
+
+	// Enable High Speed
+	udd_low_speed_disable();
+	udd_high_speed_enable();
+
+	//otg_ack_vbus_transition();
+	// Force Vbus interrupt in case of Vbus always with a high level
+	// This is possible with a short timing between a Host mode stop/start.
+	/*if (Is_otg_vbus_high()) {
+		otg_raise_vbus_transition();
+	}
+	otg_enable_vbus_interrupt();*/
+	otg_freeze_clock();
+
+	return 0UL ;
+}
+
+void UDD_Attach(void)
+{
+	irqflags_t flags = cpu_irq_save();
+
+	TRACE_UOTGHS_DEVICE(printf("=> UDD_Attach\r\n");)
+
+	otg_unfreeze_clock();
+
+	// Check USB clock because the source can be a PLL
+	while (!Is_otg_clock_usable());
+
+	// Authorize attach if Vbus is present
+	udd_attach_device();
+
+	// Enable USB line events
+	udd_enable_reset_interrupt();
+//	udd_enable_sof_interrupt();
+
+	cpu_irq_restore(flags);
+}
+
+void UDD_Detach(void)
+{
+	TRACE_UOTGHS_DEVICE(printf("=> UDD_Detach\r\n");)
+	UOTGHS->UOTGHS_DEVCTRL |= UOTGHS_DEVCTRL_DETACH;
+}
+
+void UDD_InitEP( uint32_t ul_ep_nb, uint32_t ul_ep_cfg )
+{
+	ul_ep_nb = ul_ep_nb & 0xF; // EP range is 0..9, hence mask is 0xF.
+
+	TRACE_UOTGHS_DEVICE(printf("=> UDD_InitEP : init EP %lu\r\n", ul_ep_nb);)
+
+	// Configure EP
+	UOTGHS->UOTGHS_DEVEPTCFG[ul_ep_nb] = ul_ep_cfg;
+	// Enable EP
+	udd_enable_endpoint(ul_ep_nb);
+
+	if (!Is_udd_endpoint_configured(ul_ep_nb)) {
+		TRACE_UOTGHS_DEVICE(printf("=> UDD_InitEP : ERROR FAILED TO INIT EP %lu\r\n", ul_ep_nb);)
+		while(1);
+	}
+}
+
+
+void UDD_InitEndpoints(const uint32_t* eps_table, const uint32_t ul_eps_table_size)
+{
+	uint32_t ul_ep_nb ;
+
+	for (ul_ep_nb = 1; ul_ep_nb < ul_eps_table_size; ul_ep_nb++)
+	{
+		// Configure EP
+		UOTGHS->UOTGHS_DEVEPTCFG[ul_ep_nb] = eps_table[ul_ep_nb];
+		// Enable EP
+		udd_enable_endpoint(ul_ep_nb);
+
+		if (!Is_udd_endpoint_configured(ul_ep_nb)) {
+			TRACE_UOTGHS_DEVICE(printf("=> UDD_InitEP : ERROR FAILED TO INIT EP %lu\r\n", ul_ep_nb);)
+			while(1);
+		}
+	}
+}
+
+// Wait until ready to accept IN packet.
+void UDD_WaitIN(void)
+{
+	while (!(UOTGHS->UOTGHS_DEVEPTISR[EP0] & UOTGHS_DEVEPTISR_TXINI))
+		;
+}
+
+void UDD_WaitOUT(void)
+{
+	while (!(UOTGHS->UOTGHS_DEVEPTISR[EP0] & UOTGHS_DEVEPTISR_RXOUTI))
+		;
+}
+
+// Send packet.
+void UDD_ClearIN(void)
+{
+	TRACE_UOTGHS_DEVICE(printf("=> UDD_ClearIN: sent %lu bytes\r\n", ul_send_fifo_ptr[EP0]);)
+
+	UOTGHS->UOTGHS_DEVEPTICR[EP0] = UOTGHS_DEVEPTICR_TXINIC;
+	ul_send_fifo_ptr[EP0] = 0;
+}
+
+void UDD_ClearOUT(void)
+{
+	UOTGHS->UOTGHS_DEVEPTICR[EP0] = UOTGHS_DEVEPTICR_RXOUTIC;
+	ul_recv_fifo_ptr[EP0] = 0;
+}
+
+// Wait for IN FIFO to be ready to accept data or OUT FIFO to receive data.
+// Return true if new IN FIFO buffer available.
+uint32_t UDD_WaitForINOrOUT(void)
+{
+	while (!(UOTGHS->UOTGHS_DEVEPTISR[EP0] & (UOTGHS_DEVEPTISR_TXINI | UOTGHS_DEVEPTISR_RXOUTI)))
+		;
+	return ((UOTGHS->UOTGHS_DEVEPTISR[EP0] & UOTGHS_DEVEPTISR_RXOUTI) == 0);
+}
+
+uint32_t UDD_ReceivedSetupInt(void)
+{
+	return UOTGHS->UOTGHS_DEVEPTISR[EP0] & UOTGHS_DEVEPTISR_RXSTPI;
+}
+
+void UDD_ClearSetupInt(void)
+{
+	UOTGHS->UOTGHS_DEVEPTICR[EP0] = (UOTGHS_DEVEPTICR_RXSTPIC);
+}
+
+uint32_t UDD_Send(uint32_t ep, const void* data, uint32_t len)
+{
+	const uint8_t *ptr_src = data;
+	uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
+	uint32_t i;
+
+	TRACE_UOTGHS_DEVICE(printf("=> UDD_Send (1): ep=%lu ul_send_fifo_ptr=%lu len=%lu\r\n", ep, ul_send_fifo_ptr[ep], len);)
+
+	while( UOTGHS_DEVEPTISR_TXINI != (UOTGHS->UOTGHS_DEVEPTISR[ep] & UOTGHS_DEVEPTISR_TXINI )) {}
+
+	if (ep == EP0)
+	{
+		if (ul_send_fifo_ptr[ep] + len > EP0_SIZE)
+			len = EP0_SIZE - ul_send_fifo_ptr[ep];
+	}
+	else
+	{
+		ul_send_fifo_ptr[ep] = 0;
+	}
+	for (i = 0, ptr_dest += ul_send_fifo_ptr[ep]; i < len; ++i)
+		*ptr_dest++ = *ptr_src++;
+
+	ul_send_fifo_ptr[ep] += i;
+
+	if (ep == EP0)
+	{
+		TRACE_UOTGHS_DEVICE(printf("=> UDD_Send (2): ep=%lu ptr_dest=%lu maxlen=%d\r\n", ep, ul_send_fifo_ptr[ep], EP0_SIZE);)
+		if (ul_send_fifo_ptr[ep] == EP0_SIZE)
+		{
+			UDD_ClearIN();	// Fifo is full, release this packet  // UOTGHS->UOTGHS_DEVEPTICR[EP0] = UOTGHS_DEVEPTICR_TXINIC;
+        }
+	}
+	else
+	{
+		UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_TXINIC;
+		UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_FIFOCONC;
+	}
+	return len;
+}
+
+void UDD_Send8(uint32_t ep,  uint8_t data )
+{
+	uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
+
+	TRACE_UOTGHS_DEVICE(printf("=> UDD_Send8 : ul_send_fifo_ptr=%lu data=0x%x\r\n", ul_send_fifo_ptr[ep], data);)
+
+	ptr_dest[ul_send_fifo_ptr[ep]] = data;
+	ul_send_fifo_ptr[ep] += 1;
+}
+
+uint8_t UDD_Recv8(uint32_t ep)
+{
+	uint8_t *ptr_dest = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
+	uint8_t data = ptr_dest[ul_recv_fifo_ptr[ep]];
+
+	TRACE_UOTGHS_DEVICE(printf("=> UDD_Recv8 : ul_recv_fifo_ptr=%lu\r\n", ul_recv_fifo_ptr[ep]);)
+
+	ul_recv_fifo_ptr[ep] += 1;
+	return data;
+}
+
+void UDD_Recv(uint32_t ep, uint8_t* data, uint32_t len)
+{
+	uint8_t *ptr_src = (uint8_t *) &udd_get_endpoint_fifo_access8(ep);
+	uint8_t *ptr_dest = data;
+	uint32_t i;
+
+	for (i = 0, ptr_src += ul_recv_fifo_ptr[ep]; i < len; ++i)
+		*ptr_dest++ = *ptr_src++;
+
+	ul_recv_fifo_ptr[ep] += i;
+}
+
+void UDD_Stall(void)
+{
+	UOTGHS->UOTGHS_DEVEPT = (UOTGHS_DEVEPT_EPEN0 << EP0);
+	UOTGHS->UOTGHS_DEVEPTIER[EP0] = UOTGHS_DEVEPTIER_STALLRQS;
+}
+
+
+uint32_t UDD_FifoByteCount(uint32_t ep)
+{
+	return ((UOTGHS->UOTGHS_DEVEPTISR[ep] & UOTGHS_DEVEPTISR_BYCT_Msk) >> UOTGHS_DEVEPTISR_BYCT_Pos);
+}
+
+void UDD_ReleaseRX(uint32_t ep)
+{
+	TRACE_UOTGHS_DEVICE(puts("=> UDD_ReleaseRX\r\n");)
+//	UOTGHS->UOTGHS_DEVEPTICR[ep] = (UOTGHS_DEVEPTICR_NAKOUTIC | UOTGHS_DEVEPTICR_RXOUTIC);
+	UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_RXOUTIC;
+	UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_FIFOCONC;
+	ul_recv_fifo_ptr[ep] = 0;
+}
+
+void UDD_ReleaseTX(uint32_t ep)
+{
+	TRACE_UOTGHS_DEVICE(printf("=> UDD_ReleaseTX ep=%lu\r\n", ep);)
+//	UOTGHS->UOTGHS_DEVEPTICR[ep] = (UOTGHS_DEVEPTICR_NAKINIC | UOTGHS_DEVEPTICR_RXOUTIC | UOTGHS_DEVEPTICR_TXINIC);
+	UOTGHS->UOTGHS_DEVEPTICR[ep] = UOTGHS_DEVEPTICR_TXINIC;
+	UOTGHS->UOTGHS_DEVEPTIDR[ep] = UOTGHS_DEVEPTIDR_FIFOCONC;
+	ul_send_fifo_ptr[ep] = 0;
+}
+
+// Return true if the current bank is not full.
+uint32_t UDD_ReadWriteAllowed(uint32_t ep)
+{
+	return (UOTGHS->UOTGHS_DEVEPTISR[ep] & UOTGHS_DEVEPTISR_RWALL);
+}
+
+void UDD_SetAddress(uint32_t addr)
+{
+	TRACE_UOTGHS_DEVICE(printf("=> UDD_SetAddress : setting address to %lu\r\n", addr);)
+
+	udd_configure_address(addr);
+	udd_enable_address();
+}
+
+uint32_t UDD_GetFrameNumber(void)
+{
+	return udd_frame_number();
+}
+
+#endif /* SAM3XA_SERIES */
diff --git a/hardware/digistump/sam/system/libsam/source/uotghs_host.c b/hardware/digistump/sam/system/libsam/source/uotghs_host.c
new file mode 100644
index 0000000..e7fe572
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/uotghs_host.c
@@ -0,0 +1,490 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#include "chip.h"
+#include 
+
+#if SAM3XA_SERIES
+
+//#define TRACE_UOTGHS_HOST(x)	x
+#define TRACE_UOTGHS_HOST(x)
+
+extern void (*gpf_isr)(void);
+
+// Handle UOTGHS Host driver state
+static uhd_vbus_state_t uhd_state = UHD_STATE_NO_VBUS;
+
+/**
+ * \brief Interrupt sub routine for USB Host state machine management.
+ */
+static void UHD_ISR(void)
+{
+	// Manage dis/connection event
+	if (Is_uhd_disconnection() && Is_uhd_disconnection_int_enabled()) {
+		TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : Disconnection INT\r\n");)
+		uhd_ack_disconnection();
+		uhd_disable_disconnection_int();
+		// Stop reset signal, in case of disconnection during reset
+		uhd_stop_reset();
+		// Disable wakeup/resumes interrupts,
+		// in case of disconnection during suspend mode
+		//UOTGHS->UOTGHS_HSTIDR = UOTGHS_HSTIDR_HWUPIEC
+		//		| UOTGHS_HSTIDR_RSMEDIEC
+		//		| UOTGHS_HSTIDR_RXRSMIEC;
+		uhd_ack_connection();
+		uhd_enable_connection_int();
+		uhd_state = UHD_STATE_DISCONNECTED;
+		return;
+	}
+	if (Is_uhd_connection() && Is_uhd_connection_int_enabled()) {
+		TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : Connection INT\r\n");)
+		uhd_ack_connection();
+		uhd_disable_connection_int();
+		uhd_ack_disconnection();
+		uhd_enable_disconnection_int();
+		//uhd_enable_sof();
+		uhd_state = UHD_STATE_CONNECTED;
+		return;
+	}
+
+	// Manage Vbus error
+	if (Is_uhd_vbus_error_interrupt())
+	{
+		TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : VBUS error INT\r\n");)
+		uhd_ack_vbus_error_interrupt();
+		uhd_state = UHD_STATE_DISCONNECTED; //UHD_STATE_ERROR;
+		return;
+	}
+
+	// Check USB clock ready after asynchronous interrupt
+	while (!Is_otg_clock_usable())
+		;
+	otg_unfreeze_clock();
+
+	// Manage Vbus state change
+	if (Is_otg_vbus_transition())
+	{
+		otg_ack_vbus_transition();
+		if (Is_otg_vbus_high())
+		{
+			TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : VBUS transition INT : UHD_STATE_DISCONNECT\r\n");)
+			uhd_state = UHD_STATE_DISCONNECTED;
+		}
+		else
+		{
+			TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : VBUS transition INT : UHD_STATE_NO_VBUS\r\n");)
+			otg_freeze_clock();
+			uhd_state = UHD_STATE_NO_VBUS;
+		}
+		TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : VBUS transition INT : done.\r\n");)
+		return;
+	}
+
+	// Other errors
+	if (Is_uhd_errors_interrupt())
+	{
+		TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : Other error INT\r\n");)
+		uhd_ack_errors_interrupt();
+		return;
+	}
+}
+
+/**
+ * \brief Set the interrupt sub routines callback for USB interrupts.
+ *
+ * \param pf_isr the ISR address.
+ */
+void UHD_SetStack(void (*pf_isr)(void))
+{
+	gpf_isr = pf_isr;
+}
+
+/**
+ * \brief Initialize the UOTGHS host driver.
+ */
+void UHD_Init(void)
+{
+	irqflags_t flags;
+
+	// To avoid USB interrupt before end of initialization
+	flags = cpu_irq_save();
+
+	// Setup USB Host interrupt callback
+	UHD_SetStack(&UHD_ISR);
+
+	// Enables the USB Clock
+	pmc_enable_upll_clock();
+	pmc_switch_udpck_to_upllck(0); // div=0+1
+	pmc_enable_udpck();
+	pmc_enable_periph_clk(ID_UOTGHS);
+
+	// Always authorize asynchronous USB interrupts to exit of sleep mode
+	// For SAM3 USB wake up device except BACKUP mode
+	NVIC_SetPriority((IRQn_Type) ID_UOTGHS, 0);
+	NVIC_EnableIRQ((IRQn_Type) ID_UOTGHS);
+
+	// ID pin not used then force host mode
+	otg_disable_id_pin();
+	otg_force_host_mode();
+
+	// Signal is active low (because all SAM3X Pins are high after startup)
+	// Hence VBOF must be low after connection request to power up the remote device
+	// uhd_set_vbof_active_low();
+
+	// According to the Arduino Due circuit the VBOF must be active high to power up the remote device
+	uhd_set_vbof_active_high();
+
+	otg_enable_pad();
+	otg_enable();
+
+	otg_unfreeze_clock();
+
+	// Check USB clock
+	while (!Is_otg_clock_usable())
+		;
+
+	// Clear all interrupts that may have been set by a previous host mode
+	UOTGHS->UOTGHS_HSTICR = UOTGHS_HSTICR_DCONNIC | UOTGHS_HSTICR_DDISCIC
+			| UOTGHS_HSTICR_HSOFIC  | UOTGHS_HSTICR_HWUPIC
+			| UOTGHS_HSTICR_RSMEDIC | UOTGHS_HSTICR_RSTIC
+			| UOTGHS_HSTICR_RXRSMIC;
+
+	otg_ack_vbus_transition();
+
+	// Enable Vbus change and error interrupts
+	// Disable automatic Vbus control after Vbus error
+	Set_bits(UOTGHS->UOTGHS_CTRL,
+		UOTGHS_CTRL_VBUSHWC | UOTGHS_CTRL_VBUSTE | UOTGHS_CTRL_VBERRE);
+
+	uhd_enable_vbus();
+
+	// Force Vbus interrupt when Vbus is always high
+	// This is possible due to a short timing between a Host mode stop/start.
+	if (Is_otg_vbus_high())
+	{
+		otg_raise_vbus_transition();
+	}
+
+	// Enable main control interrupt
+	// Connection, SOF and reset
+	UOTGHS->UOTGHS_HSTIER = UOTGHS_HSTICR_DCONNIC;
+
+	otg_freeze_clock();
+
+	uhd_state = UHD_STATE_NO_VBUS;
+
+	cpu_irq_restore(flags);
+}
+
+/**
+ * \brief Trigger a USB bus reset.
+ */
+void UHD_BusReset(void)
+{
+	uhd_start_reset();
+}
+
+/**
+ * \brief Get VBUS state.
+ *
+ * \return VBUS status.
+ */
+uhd_vbus_state_t UHD_GetVBUSState(void)
+{
+	return uhd_state;
+}
+
+/*uhd_speed_t uhd_get_speed(void)
+{
+	switch (uhd_get_speed_mode())
+	{
+		case UOTGHS_SR_SPEED_HIGH_SPEED:
+			return UHD_SPEED_HIGH;
+
+		case UOTGHS_SR_SPEED_FULL_SPEED:
+			return UHD_SPEED_FULL;
+
+		case UOTGHS_SR_SPEED_LOW_SPEED:
+			return UHD_SPEED_LOW;
+
+		default:
+			return UHD_SPEED_LOW;
+	}
+}*/
+
+/**
+ * \brief Allocate FIFO for pipe 0.
+ *
+ * \param ul_add Address of remote device for pipe 0.
+ * \param ul_ep_size Actual size of the FIFO in bytes.
+ *
+ * \retval 0 success.
+ * \retval 1 error.
+ */
+uint32_t UHD_Pipe0_Alloc(uint32_t ul_add, uint32_t ul_ep_size)
+{
+	if (ul_ep_size < 8)
+	{
+		TRACE_UOTGHS_HOST(printf("/!\\ UHD_EP0_Alloc : incorrect pipe size!\r\n");)
+		return 1;
+	}
+
+	if (Is_uhd_pipe_enabled(0))
+	{
+		// Pipe is already allocated
+		return 0;
+	}
+
+	uhd_enable_pipe(0);
+	uhd_configure_pipe(0, 	// Pipe 0
+			0, 				// No frequency
+			0, 				// Enpoint 0
+			UOTGHS_HSTPIPCFG_PTYPE_CTRL,
+			UOTGHS_HSTPIPCFG_PTOKEN_SETUP,
+			ul_ep_size,
+			UOTGHS_HSTPIPCFG_PBK_1_BANK, 0);
+
+	uhd_allocate_memory(0);
+
+	if (!Is_uhd_pipe_configured(0))
+	{
+		TRACE_UOTGHS_HOST(printf("/!\\ UHD_EP0_Alloc : incorrect pipe settings!\r\n");)
+		uhd_disable_pipe(0);
+		return 1;
+	}
+
+	uhd_configure_address(0, ul_add);
+
+	return 0;
+}
+
+/**
+ * \brief Allocate a new pipe.
+ *
+ * \note UOTGHS maximum pipe number is limited to 10, meaning that only a limited
+ * amount of devices can be connected. Unfortunately, using only one pipe shared accross
+ * various endpoints and devices is not possible because the UOTGHS IP does not allow to
+ * change the data toggle value through register interface.
+ *
+ * \param ul_dev_addr Address of remote device.
+ * \param ul_dev_ep Targeted endpoint of remote device.
+ * \param ul_type Pipe type.
+ * \param ul_dir Pipe direction.
+ * \param ul_maxsize Pipe size.
+ * \param ul_interval Polling interval (if applicable to pipe type).
+ * \param ul_nb_bank Number of banks associated with this pipe.
+ *
+ * \return the newly allocated pipe number on success, 0 otherwise.
+ */
+uint32_t UHD_Pipe_Alloc(uint32_t ul_dev_addr, uint32_t ul_dev_ep, uint32_t ul_type, uint32_t ul_dir, uint32_t ul_maxsize, uint32_t ul_interval, uint32_t ul_nb_bank)
+{
+	uint32_t ul_pipe = 1;
+
+	for (ul_pipe = 1; ul_pipe < UOTGHS_EPT_NUM; ++ul_pipe)
+	{
+		if (Is_uhd_pipe_enabled(ul_pipe))
+		{
+			continue;
+		}
+
+		uhd_enable_pipe(ul_pipe);
+
+		uhd_configure_pipe(ul_pipe, ul_interval, ul_dev_ep, ul_type, ul_dir,
+				ul_maxsize, ul_nb_bank, UOTGHS_HSTPIPCFG_AUTOSW);
+
+		uhd_allocate_memory(ul_pipe);
+
+		if (!Is_uhd_pipe_configured(ul_pipe))
+		{
+			uhd_disable_pipe(ul_pipe);
+			return 0;
+		}
+
+		uhd_configure_address(ul_pipe, ul_dev_addr);
+
+		// Pipe is configured and allocated successfully
+		return ul_pipe;
+	}
+
+	return 0;
+}
+
+/**
+ * \brief Free a pipe.
+ *
+ * \param ul_pipe Pipe number to free.
+ */
+void UHD_Pipe_Free(uint32_t ul_pipe)
+{
+	// Unalloc pipe
+	uhd_disable_pipe(ul_pipe);
+	uhd_unallocate_memory(ul_pipe);
+	uhd_reset_pipe(ul_pipe);
+}
+
+/**
+ * \brief Read from a pipe.
+ *
+ * \param ul_pipe Pipe number.
+ * \param ul_size Maximum number of data to read.
+ * \param data Buffer to store the data.
+ *
+ * \return number of data read.
+ */
+uint32_t UHD_Pipe_Read(uint32_t ul_pipe, uint32_t ul_size, uint8_t* data)
+{
+	uint8_t *ptr_ep_data = 0;
+	uint8_t nb_byte_received = 0;
+	uint32_t ul_nb_trans = 0;
+
+	// Get information to read data
+	nb_byte_received = uhd_byte_count(ul_pipe);
+
+	ptr_ep_data = (uint8_t *) & uhd_get_pipe_fifo_access(ul_pipe, 8);
+
+	// Copy data from pipe to payload buffer
+	while (ul_size && nb_byte_received) {
+		*data++ = *ptr_ep_data++;
+		ul_nb_trans++;
+		ul_size--;
+		nb_byte_received--;
+	}
+
+	return ul_nb_trans;
+}
+
+/**
+ * \brief Write into a pipe.
+ *
+ * \param ul_pipe Pipe number.
+ * \param ul_size Maximum number of data to read.
+ * \param data Buffer containing data to write.
+ */
+void UHD_Pipe_Write(uint32_t ul_pipe, uint32_t ul_size, uint8_t* data)
+{
+	volatile uint8_t *ptr_ep_data = 0;
+	uint32_t i = 0;
+
+	// Check pipe
+	if (!Is_uhd_pipe_enabled(ul_pipe))
+	{
+		// Endpoint not valid
+		TRACE_UOTGHS_HOST(printf("/!\\ UHD_EP_Send : pipe is not enabled!\r\n");)
+		return;
+	}
+
+	ptr_ep_data = (volatile uint8_t *)&uhd_get_pipe_fifo_access(ul_pipe, 8);
+	for (i = 0; i < ul_size; ++i)
+		*ptr_ep_data++ = *data++;
+}
+
+/**
+ * \brief Send a pipe content.
+ *
+ * \param ul_pipe Pipe number.
+ * \param ul_token_type Token type.
+ */
+void UHD_Pipe_Send(uint32_t ul_pipe, uint32_t ul_token_type)
+{
+	// Check pipe
+	if (!Is_uhd_pipe_enabled(ul_pipe))
+	{
+		// Endpoint not valid
+		TRACE_UOTGHS_HOST(printf("/!\\ UHD_EP_Send : pipe %lu is not enabled!\r\n", ul_pipe);)
+		return;
+	}
+
+	// Set token type for zero length packet
+	// When actually using the FIFO, pipe token MUST be configured first
+	uhd_configure_pipe_token(ul_pipe, ul_token_type);
+
+	// Clear interrupt flags
+	uhd_ack_setup_ready(ul_pipe);
+	uhd_ack_in_received(ul_pipe);
+	uhd_ack_out_ready(ul_pipe);
+	uhd_ack_short_packet(ul_pipe);
+	uhd_ack_nak_received(ul_pipe);
+
+	// Send actual packet
+	uhd_ack_fifocon(ul_pipe);
+	uhd_unfreeze_pipe(ul_pipe);
+}
+
+/**
+ * \brief Check for pipe transfer completion.
+ *
+ * \param ul_pipe Pipe number.
+ * \param ul_token_type Token type.
+ *
+ * \retval 0 transfer is not complete.
+ * \retval 1 transfer is complete.
+ */
+uint32_t UHD_Pipe_Is_Transfer_Complete(uint32_t ul_pipe, uint32_t ul_token_type)
+{
+	// Check for transfer completion depending on token type
+	switch (ul_token_type)
+	{
+		case UOTGHS_HSTPIPCFG_PTOKEN_SETUP:
+			if (Is_uhd_setup_ready(ul_pipe))
+			{
+				uhd_freeze_pipe(ul_pipe);
+				uhd_ack_setup_ready(ul_pipe);
+				return 1;
+			}
+
+		case UOTGHS_HSTPIPCFG_PTOKEN_IN:
+			if (Is_uhd_in_received(ul_pipe))
+			{
+				// In case of low USB speed and with a high CPU frequency,
+				// a ACK from host can be always running on USB line
+				// then wait end of ACK on IN pipe.
+				while(!Is_uhd_pipe_frozen(ul_pipe))
+					;
+
+				// IN packet received
+				uhd_ack_in_received(ul_pipe);
+
+				return 1;
+			}
+
+		case UOTGHS_HSTPIPCFG_PTOKEN_OUT:
+			if (Is_uhd_out_ready(ul_pipe))
+			{
+				// OUT packet sent
+				uhd_freeze_pipe(ul_pipe);
+				uhd_ack_out_ready(ul_pipe);
+
+				return 1;
+			}
+	}
+
+	return 0;
+}
+
+#endif /* SAM3XA_SERIES */
diff --git a/hardware/digistump/sam/system/libsam/source/usart.c b/hardware/digistump/sam/system/libsam/source/usart.c
new file mode 100644
index 0000000..d196132
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/usart.c
@@ -0,0 +1,409 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup usart_module Working with USART
+ * The USART driver provides the interface to configure and use the USART peripheral.\n
+ *
+ * The USART supports several kinds of comminication modes such as full-duplex asynchronous/
+ * synchronous serial commnunication,RS485 with driver control signal,ISO7816,SPI and Test modes.
+ *
+ * To start a USART transfer with \ref AT91SAM3S_PDC "PDC" support, the user could follow these steps:
+ * 
    
+ * 
  •  Configure USART with expected mode and baudrate(see \ref USART_Configure), which could be done by:
+ * -# Resetting and disabling transmitter and receiver by setting US_CR(Control Register). 
    • 
+ * -# Conifguring the USART in a specific mode by setting USART_MODE bits in US_MR(Mode Register) 
+ * -# Setting baudrate which is different from mode to mode.
+   
+ * 
  •  Enable transmitter or receiver respectively by set US_CR_TXEN or US_CR_RXEN in US_CR.
    • 
+ * 
  •  Read from or write to the peripheral with  \ref USART_ReadBuffer or \ref USART_WriteBuffer.
+        These operations could be done by polling or interruption. 
    • 
+ * 
  •  For polling, check the status bit US_CSR_ENDRX/US_CSR_RXBUFF (READ) or US_CSR_ENDTX/
+        US_CSR_TXBUFE (WRITE).  
    • 
+ * 
  •  For interruption,"enable" the status bit through US_IER and
+        realize the hanler with USARTx_IrqHandler according to IRQ vector
+        table which is defined in board_cstartup_.c
+        To enable the interruption of USART,it should be configured with priority and enabled first through
+        NVIC .
    • 
+ * 

+ *
+ * For more accurate information, please look at the USART section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref usart.c\n
+ * \ref usart.h\n
+*/
+
+
+
+/**
+ * \file
+ *
+ * Implementation of USART (Universal Synchronous Asynchronous Receiver Transmitter)
+ * controller.
+ *
+ */
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include 
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Local definitions
+ *----------------------------------------------------------------------------*/
+
+
+/*------------------------------------------------------------------------------
+ *         Exported functions
+ *------------------------------------------------------------------------------*/
+
+/**
+ * \brief Configures an USART peripheral with the specified parameters.
+ *
+ *
+ *  \param usart  Pointer to the USART peripheral to configure.
+ *  \param mode  Desired value for the USART mode register (see the datasheet).
+ *  \param baudrate  Baudrate at which the USART should operate (in Hz).
+ *  \param masterClock  Frequency of the system master clock (in Hz).
+ */
+void USART_Configure(Usart *usart,
+                            uint32_t mode,
+                            uint32_t baudrate,
+                            uint32_t masterClock)
+{
+    /* Reset and disable receiver & transmitter*/
+    usart->US_CR = US_CR_RSTRX | US_CR_RSTTX
+                   | US_CR_RXDIS | US_CR_TXDIS;
+
+    /* Configure mode*/
+    usart->US_MR = mode;
+
+    /* Configure baudrate*/
+    /* Asynchronous, no oversampling*/
+    if ( ((mode & US_MR_SYNC) == 0) && ((mode & US_MR_OVER) == 0) )
+    {
+        usart->US_BRGR = (masterClock / baudrate) / 16;
+    }
+
+    if( ((mode & US_MR_USART_MODE_SPI_MASTER) == US_MR_USART_MODE_SPI_MASTER)
+     || ((mode & US_MR_SYNC) == US_MR_SYNC))
+    {
+        if( (mode & US_MR_USCLKS_Msk) == US_MR_USCLKS_MCK)
+        {
+            usart->US_BRGR = masterClock / baudrate;
+        }
+        else
+        {
+            if ( (mode & US_MR_USCLKS_DIV) == US_MR_USCLKS_DIV)
+            {
+                usart->US_BRGR = masterClock / baudrate / 8;
+            }
+        }
+    }
+    /* TODO other modes*/
+}
+/**
+ * \brief Enables or disables the transmitter of an USART peripheral.
+ *
+ *
+ * \param usart  Pointer to an USART peripheral
+ * \param enabled  If true, the transmitter is enabled; otherwise it is
+ *                disabled.
+ */
+void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled)
+{
+    if (enabled) {
+
+        usart->US_CR = US_CR_TXEN;
+    }
+    else {
+
+        usart->US_CR = US_CR_TXDIS;
+    }
+}
+
+/**
+ * \brief Enables or disables the receiver of an USART peripheral
+ *
+ *
+ * \param usart  Pointer to an USART peripheral
+ * \param enabled  If true, the receiver is enabled; otherwise it is disabled.
+ */
+void USART_SetReceiverEnabled(Usart *usart,
+                                     uint8_t enabled)
+{
+    if (enabled) {
+
+        usart->US_CR = US_CR_RXEN;
+    }
+    else {
+
+        usart->US_CR = US_CR_RXDIS;
+    }
+}
+
+/**
+ * \brief Sends one packet of data through the specified USART peripheral. This
+ * function operates synchronously, so it only returns when the data has been
+ * actually sent.
+ *
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param data  Data to send including 9nth bit and sync field if necessary (in
+ *        the same format as the US_THR register in the datasheet).
+ * \param timeOut  Time out value (0 = no timeout).
+ */
+void USART_Write(
+    Usart *usart,
+    uint16_t data,
+    volatile uint32_t timeOut)
+{
+    if (timeOut == 0) {
+
+        while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
+    }
+    else {
+
+        while ((usart->US_CSR & US_CSR_TXEMPTY) == 0) {
+
+            if (timeOut == 0) {
+
+//                TRACE_ERROR("USART_Write: Timed out.\n\r");
+                return;
+            }
+            timeOut--;
+        }
+    }
+
+    usart->US_THR = data;
+}
+
+/**
+ * \brief Sends the contents of a data buffer through the specified USART peripheral.
+ * This function returns immediately (1 if the buffer has been queued, 0
+ * otherwise); poll the ENDTX and TXBUFE bits of the USART status register
+ * to check for the transfer completion.
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param buffer  Pointer to the data buffer to send.
+ * \param size  Size of the data buffer (in bytes).
+ */
+uint8_t USART_WriteBuffer(
+    Usart *usart,
+    void *buffer,
+    uint32_t size)
+{
+    /* Check if the first PDC bank is free*/
+    if ((usart->US_TCR == 0) && (usart->US_TNCR == 0)) {
+
+        usart->US_TPR = (uint32_t) buffer;
+        usart->US_TCR = size;
+        usart->US_PTCR = US_PTCR_TXTEN;
+
+        return 1;
+    }
+    /* Check if the second PDC bank is free*/
+    else if (usart->US_TNCR == 0) {
+
+        usart->US_TNPR = (uint32_t) buffer;
+        usart->US_TNCR = size;
+
+        return 1;
+    }
+    else {
+
+        return 0;
+    }
+}
+
+
+/**
+ * \brief  Reads and return a packet of data on the specified USART peripheral. This
+ * function operates asynchronously, so it waits until some data has been
+ * received.
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param timeOut  Time out value (0 -> no timeout).
+ */
+uint16_t USART_Read(
+    Usart *usart,
+    volatile uint32_t timeOut)
+{
+    if (timeOut == 0) {
+
+        while ((usart->US_CSR & US_CSR_RXRDY) == 0);
+    }
+    else {
+
+        while ((usart->US_CSR & US_CSR_RXRDY) == 0) {
+
+            if (timeOut == 0) {
+
+//                TRACE_ERROR( "USART_Read: Timed out.\n\r" ) ;
+                return 0;
+            }
+            timeOut--;
+        }
+    }
+
+    return usart->US_RHR;
+}
+
+/**
+ * \brief  Reads data from an USART peripheral, filling the provided buffer until it
+ * becomes full. This function returns immediately with 1 if the buffer has
+ * been queued for transmission; otherwise 0.
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param buffer  Pointer to the buffer where the received data will be stored.
+ * \param size  Size of the data buffer (in bytes).
+ */
+uint8_t USART_ReadBuffer(Usart *usart,
+                                      void *buffer,
+                                      uint32_t size)
+{
+    /* Check if the first PDC bank is free*/
+    if ((usart->US_RCR == 0) && (usart->US_RNCR == 0)) {
+
+        usart->US_RPR = (uint32_t) buffer;
+        usart->US_RCR = size;
+        usart->US_PTCR = US_PTCR_RXTEN;
+
+        return 1;
+    }
+    /* Check if the second PDC bank is free*/
+    else if (usart->US_RNCR == 0) {
+
+        usart->US_RNPR = (uint32_t) buffer;
+        usart->US_RNCR = size;
+
+        return 1;
+    }
+    else {
+
+        return 0;
+    }
+}
+
+/**
+ * \brief  Returns 1 if some data has been received and can be read from an USART;
+ * otherwise returns 0.
+ *
+ * \param usart  Pointer to an Usart instance.
+ */
+uint8_t USART_IsDataAvailable(Usart *usart)
+{
+    if ((usart->US_CSR & US_CSR_RXRDY) != 0) {
+
+        return 1;
+    }
+    else {
+
+        return 0;
+    }
+}
+
+/**
+ * \brief  Sets the filter value for the IRDA demodulator.
+ *
+ * \param pUsart  Pointer to an Usart instance.
+ * \param filter  Filter value.
+ */
+void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter)
+{
+    assert( pUsart != NULL ) ;
+
+    pUsart->US_IF = filter;
+}
+
+/**
+ * \brief  Sends one packet of data through the specified USART peripheral. This
+ * function operates synchronously, so it only returns when the data has been
+ * actually sent.
+ *
+ * \param usart  Pointer to an USART peripheral.
+ * \param c  Character to send
+ */
+void USART_PutChar(
+    Usart *usart,
+    uint8_t c)
+{
+    /* Wait for the transmitter to be ready*/
+    while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
+
+    /* Send character*/
+    usart->US_THR = c;
+
+    /* Wait for the transfer to complete*/
+    while ((usart->US_CSR & US_CSR_TXEMPTY) == 0);
+}
+
+/**
+ * \brief   Return 1 if a character can be read in USART
+ */
+uint32_t USART_IsRxReady(Usart *usart)
+{
+    return (usart->US_CSR & US_CSR_RXRDY);
+}
+/**
+ * \brief   Get present status
+ */
+uint32_t USART_GetStatus(Usart *usart)
+{
+    return usart->US_CSR;
+}
+/**
+ * \brief   Enable interrupt
+ */
+void USART_EnableIt(Usart *usart,uint32_t mode)
+{
+    usart->US_IER = mode;
+}
+/**
+ * \brief   Disable interrupt
+ */
+void USART_DisableIt(Usart *usart,uint32_t mode)
+{
+    usart->US_IDR = mode;
+}
+/**
+ * \brief  Reads and returns a character from the USART.
+ *
+ * \note This function is synchronous (i.e. uses polling).
+ * \param usart  Pointer to an USART peripheral.
+ * \return Character received.
+ */
+uint8_t USART_GetChar(Usart *usart)
+{
+    while ((usart->US_CSR & US_CSR_RXRDY) == 0);
+    return usart->US_RHR;
+}
diff --git a/hardware/digistump/sam/system/libsam/source/wdt.c b/hardware/digistump/sam/system/libsam/source/wdt.c
new file mode 100644
index 0000000..45287aa
--- /dev/null
+++ b/hardware/digistump/sam/system/libsam/source/wdt.c
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2011-2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Implementation of Watchdog Timer (WDT) controller.
+ *
+ */
+
+/** \addtogroup wdt_module Working with WDT
+ * The WDT driver provides the interface to configure and use the WDT
+ * peripheral.
+ *
+ * The WDT can be used to prevent system lock-up if the software becomes
+ * trapped in a deadlock. It can generate a general reset or a processor
+ * reset only. It is clocked by slow clock divided by 128.
+ *
+ * The WDT is running at reset with 16 seconds watchdog period (slow clock at 32.768 kHz)
+ * and external reset generation enabled. The user must either disable it or
+ * reprogram it to meet the application requires.
+ *
+ * To use the WDT, the user could follow these few steps:
+ * 
    
+ * 
  • Enable watchdog with given mode using \ref WDT_Enable().
+ * 
  • Restart the watchdog using \ref WDT_Restart() within the watchdog period.
+ * 

+ *
+ * For more accurate information, please look at the WDT section of the
+ * Datasheet.
+ *
+ * \note
+ * The Watchdog Mode Register (WDT_MR) can be written only once.\n
+ *
+ * Related files :\n
+ * \ref wdt.c\n
+ * \ref wdt.h.\n
+ */
+/*@{*/
+/*@}*/
+
+/*---------------------------------------------------------------------------
+ *        Headers
+ *---------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include 
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Enable watchdog with given mode.
+ *
+ * \note The Watchdog Mode Register (WDT_MR) can be written only once.
+ * Only a processor reset resets it.
+ *
+ * \param dwMode   WDT mode to be set
+ */
+extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode )
+{
+    pWDT->WDT_MR = dwMode ;
+}
+
+/**
+ * \brief Disable watchdog.
+ *
+ * \note The Watchdog Mode Register (WDT_MR) can be written only once.
+ * Only a processor reset resets it.
+ */
+extern void WDT_Disable( Wdt* pWDT )
+{
+    pWDT->WDT_MR = WDT_MR_WDDIS;
+}
+
+/**
+ * \brief Watchdog restart.
+ */
+extern void WDT_Restart( Wdt* pWDT )
+{
+    pWDT->WDT_CR = 0xA5000001;
+}
+
+/**
+ * \brief Watchdog get status.
+ */
+extern uint32_t WDT_GetStatus( Wdt* pWDT )
+{
+    return (pWDT->WDT_SR & 0x3) ;
+}
+
+/**
+ * \brief Watchdog get period.
+ *
+ * \param dwMs   desired watchdog period in millisecond.
+ */
+extern uint32_t WDT_GetPeriod( uint32_t dwMs )
+{
+    if ( (dwMs < 4) || (dwMs > 16000) )
+    {
+        return 0 ;
+    }
+    return ((dwMs << 8) / 1000) ;
+}
diff --git a/hardware/digistump/sam/variants/digix/build_gcc/Makefile b/hardware/digistump/sam/variants/digix/build_gcc/Makefile
new file mode 100644
index 0000000..4332f36
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/build_gcc/Makefile
@@ -0,0 +1,42 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+SUBMAKE_OPTIONS=--no-builtin-rules --no-builtin-variables --no-print-directory
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+
+all: arduino_due_x
+
+.PHONY: arduino_due_x
+arduino_due_x:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Making variant arduino_due_x
+	@$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libvariant_arduino_due_x.mk
+#	@$(MAKE) $(SUBMAKE_OPTIONS) -f libvariant_arduino_due_x.mk
+	@echo ------------------------------------------------------------------------------------
+
+.PHONY: clean
+clean:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Cleaning variant arduino_due_x
+	@$(MAKE) DEBUG=1 $(SUBMAKE_OPTIONS) -f libvariant_arduino_due_x.mk $@
+#	@$(MAKE) $(SUBMAKE_OPTIONS) -f libvariant_arduino_due_x.mk $@
+	@echo ------------------------------------------------------------------------------------
+
diff --git a/hardware/digistump/sam/variants/digix/build_gcc/debug.mk b/hardware/digistump/sam/variants/digix/build_gcc/debug.mk
new file mode 100644
index 0000000..d071674
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/build_gcc/debug.mk
@@ -0,0 +1,25 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -g -O0 -DDEBUG
diff --git a/hardware/digistump/sam/variants/digix/build_gcc/gcc.mk b/hardware/digistump/sam/variants/digix/build_gcc/gcc.mk
new file mode 100644
index 0000000..32f35d2
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/build_gcc/gcc.mk
@@ -0,0 +1,82 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Tool suffix when cross-compiling
+CROSS_COMPILE = $(ARM_GCC_TOOLCHAIN)/arm-none-eabi-
+
+# Compilation tools
+AR = $(CROSS_COMPILE)ar
+CC = $(CROSS_COMPILE)gcc
+CXX = $(CROSS_COMPILE)g++
+AS = $(CROSS_COMPILE)as
+NM = $(CROSS_COMPILE)nm
+ifeq ($(OS),Windows_NT)
+RM=cs-rm -Rf
+else
+RM=rm -Rf
+endif
+
+SEP=\\
+
+# ---------------------------------------------------------------------------------------
+# C Flags
+
+CFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
+CFLAGS += -Werror-implicit-function-declaration -Wmain -Wparentheses
+CFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CFLAGS += -Wshadow -Wpointer-arith -Wbad-function-cast -Wwrite-strings
+CFLAGS += -Wsign-compare -Waggregate-return -Wstrict-prototypes
+CFLAGS += -Wmissing-prototypes -Wmissing-declarations
+CFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CFLAGS += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long
+CFLAGS += -Wunreachable-code
+CFLAGS += -Wcast-align
+#CFLAGS += -Wmissing-noreturn
+#CFLAGS += -Wconversion
+
+CFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections -fdata-sections -nostdlib -std=c99
+CFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) -D$(VARIANT)
+
+# To reduce application size use only integer printf function.
+CFLAGS += -Dprintf=iprintf
+
+# ---------------------------------------------------------------------------------------
+# CPP Flags
+
+CPPFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2
+CPPFLAGS += -Wmain -Wparentheses -Wcast-align -Wunreachable-code
+CPPFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CPPFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CPPFLAGS += -Wshadow -Wpointer-arith -Wwrite-strings
+CPPFLAGS += -Wsign-compare -Waggregate-return -Wmissing-declarations
+CPPFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CPPFLAGS += -Wpacked -Wredundant-decls -Winline -Wlong-long
+#CPPFLAGS += -Wmissing-noreturn
+#CPPFLAGS += -Wconversion
+
+CPPFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -std=c++98
+CPPFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP)
+
+# To reduce application size use only integer printf function.
+CPPFLAGS += -Dprintf=iprintf
+
+# ---------------------------------------------------------------------------------------
+# ASM Flags
+
+ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -g $(OPTIMIZATION) $(INCLUDES)
diff --git a/hardware/digistump/sam/variants/digix/build_gcc/libvariant_arduino_due_x.mk b/hardware/digistump/sam/variants/digix/build_gcc/libvariant_arduino_due_x.mk
new file mode 100644
index 0000000..3f8b1b7
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/build_gcc/libvariant_arduino_due_x.mk
@@ -0,0 +1,184 @@
+#
+#  Copyright (c) 2012 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Makefile for compiling libArduino
+.SUFFIXES: .o .a .c .s
+
+CHIP=__SAM3X8E__
+VARIANT=arduino_due_x
+LIBNAME=libvariant_$(VARIANT)
+TOOLCHAIN=gcc
+
+#-------------------------------------------------------------------------------
+# Path
+#-------------------------------------------------------------------------------
+
+# Output directories
+OUTPUT_BIN = ../../../cores/arduino
+
+# Libraries
+PROJECT_BASE_PATH = ..
+SYSTEM_PATH = ../../../system
+CMSIS_ROOT_PATH = $(SYSTEM_PATH)/CMSIS
+CMSIS_ARM_PATH=$(CMSIS_ROOT_PATH)/CMSIS/Include
+CMSIS_ATMEL_PATH=$(CMSIS_ROOT_PATH)/Device/ATMEL
+#CMSIS_CHIP_PATH=$(CMSIS_ROOT_PATH)/Device/ATMEL/$(CHIP_SERIE)
+
+ARDUINO_PATH = ../../../cores/arduino
+VARIANT_BASE_PATH = ../../../variants
+VARIANT_PATH = ../../../variants/$(VARIANT)
+
+#-------------------------------------------------------------------------------
+# Files
+#-------------------------------------------------------------------------------
+
+#vpath %.h $(PROJECT_BASE_PATH) $(SYSTEM_PATH) $(VARIANT_PATH)
+vpath %.cpp $(PROJECT_BASE_PATH)
+
+VPATH+=$(PROJECT_BASE_PATH)
+
+INCLUDES =
+#INCLUDES += -I$(PROJECT_BASE_PATH)
+INCLUDES += -I$(ARDUINO_PATH)
+INCLUDES += -I$(ARDUINO_PATH)/USB
+INCLUDES += -I$(SYSTEM_PATH)
+INCLUDES += -I$(SYSTEM_PATH)/libsam
+INCLUDES += -I$(SYSTEM_PATH)/USBHost
+INCLUDES += -I$(VARIANT_BASE_PATH)
+INCLUDES += -I$(VARIANT_PATH)
+INCLUDES += -I$(CMSIS_ARM_PATH)
+INCLUDES += -I$(CMSIS_ATMEL_PATH)
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+include debug.mk
+else
+include release.mk
+endif
+
+#-------------------------------------------------------------------------------
+# Tools
+#-------------------------------------------------------------------------------
+
+include $(TOOLCHAIN).mk
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+OUTPUT_OBJ=debug
+OUTPUT_LIB_POSTFIX=dbg
+else
+OUTPUT_OBJ=release
+OUTPUT_LIB_POSTFIX=rel
+endif
+
+OUTPUT_LIB=$(LIBNAME)_$(TOOLCHAIN)_$(OUTPUT_LIB_POSTFIX).a
+OUTPUT_PATH=$(OUTPUT_OBJ)_$(VARIANT)
+
+#-------------------------------------------------------------------------------
+# C source files and objects
+#-------------------------------------------------------------------------------
+C_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.c)
+
+C_OBJ_TEMP = $(patsubst %.c, %.o, $(notdir $(C_SRC)))
+
+# during development, remove some files
+C_OBJ_FILTER=
+
+C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# CPP source files and objects
+#-------------------------------------------------------------------------------
+CPP_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.cpp)
+
+CPP_OBJ_TEMP = $(patsubst %.cpp, %.o, $(notdir $(CPP_SRC)))
+
+# during development, remove some files
+CPP_OBJ_FILTER=
+
+CPP_OBJ=$(filter-out $(CPP_OBJ_FILTER), $(CPP_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Assembler source files and objects
+#-------------------------------------------------------------------------------
+A_SRC=$(wildcard $(PROJECT_BASE_PATH)/*.s)
+
+A_OBJ_TEMP=$(patsubst %.s, %.o, $(notdir $(A_SRC)))
+
+# during development, remove some files
+A_OBJ_FILTER=
+
+A_OBJ=$(filter-out $(A_OBJ_FILTER), $(A_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+all: $(VARIANT)
+
+$(VARIANT): create_output $(OUTPUT_LIB)
+
+.PHONY: create_output
+create_output:
+	@echo ------------------------------------------------------------------------------------
+	@echo -------------------------
+	@echo --- Preparing variant $(VARIANT) files in $(OUTPUT_PATH) $(OUTPUT_BIN)
+	@echo -------------------------
+#	@echo *$(INCLUDES)
+#	@echo -------------------------
+#	@echo *$(C_SRC)
+#	@echo -------------------------
+#	@echo *$(C_OBJ)
+#	@echo -------------------------
+#	@echo *$(addprefix $(OUTPUT_PATH)/, $(C_OBJ))
+#	@echo -------------------------
+#	@echo *$(CPP_SRC)
+#	@echo -------------------------
+#	@echo *$(CPP_OBJ)
+#	@echo -------------------------
+#	@echo *$(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ))
+#	@echo -------------------------
+#	@echo *$(A_SRC)
+#	@echo -------------------------
+
+	-@mkdir $(OUTPUT_PATH) 1>NUL 2>&1
+	@echo ------------------------------------------------------------------------------------
+
+$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: %.c
+#	@"$(CC)" -v -c $(CFLAGS) $< -o $@
+	@"$(CC)" -c $(CFLAGS) $< -o $@
+
+$(addprefix $(OUTPUT_PATH)/,$(CPP_OBJ)): $(OUTPUT_PATH)/%.o: %.cpp
+#	@"$(CC)" -c $(CPPFLAGS) $< -o $@
+	@"$(CC)" -xc++ -c $(CPPFLAGS) $< -o $@
+
+$(addprefix $(OUTPUT_PATH)/,$(A_OBJ)): $(OUTPUT_PATH)/%.o: %.s
+	@"$(AS)" -c $(ASFLAGS) $< -o $@
+
+$(OUTPUT_LIB): $(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(CPP_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(A_OBJ))
+	@"$(AR)" -v -r "$(OUTPUT_BIN)/$@" $^
+	@"$(NM)" "$(OUTPUT_BIN)/$@" > "$(OUTPUT_BIN)/$@.txt"
+
+
+.PHONY: clean
+clean:
+	@echo ------------------------------------------------------------------------------------
+	@echo --- Cleaning $(VARIANT) files [$(OUTPUT_PATH)$(SEP)*.o]
+	-@$(RM) $(OUTPUT_PATH) 1>NUL 2>&1
+	-@$(RM) $(OUTPUT_BIN)/$(OUTPUT_LIB) 1>NUL 2>&1
+	@echo ------------------------------------------------------------------------------------
+
diff --git a/hardware/digistump/sam/variants/digix/build_gcc/release.mk b/hardware/digistump/sam/variants/digix/build_gcc/release.mk
new file mode 100644
index 0000000..0d15157
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/build_gcc/release.mk
@@ -0,0 +1,25 @@
+#
+#  Copyright (c) 2011 Arduino.  All right reserved.
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+#  See the GNU Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+#
+
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -Os
diff --git a/hardware/digistump/sam/variants/digix/debug_scripts/gcc/arduino_due_x_flash.gdb b/hardware/digistump/sam/variants/digix/debug_scripts/gcc/arduino_due_x_flash.gdb
new file mode 100644
index 0000000..4e8375b
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/debug_scripts/gcc/arduino_due_x_flash.gdb
@@ -0,0 +1,37 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in flash on SAM3X.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3X8E
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1a00 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x80000)
+#set *0x80004 = *0x80004 & 0xFFFFFFFE
+mon reg pc=(0x80004)
+
+info reg
+
+break main
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/variants/digix/debug_scripts/gcc/arduino_due_x_sram.gdb b/hardware/digistump/sam/variants/digix/debug_scripts/gcc/arduino_due_x_sram.gdb
new file mode 100644
index 0000000..15a1792
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/debug_scripts/gcc/arduino_due_x_sram.gdb
@@ -0,0 +1,37 @@
+#*******************************************************
+#
+#  Connect to J-Link and debug application in sram on SAM3X.
+#
+
+# Define 'reset' command
+define reset
+
+# Connect to the J-Link gdb server
+target remote localhost:2331
+
+# Reset the chip to get to a known state
+monitor reset
+
+# Select flash device
+monitor flash device = AT91SAM3X8E
+
+# Enable flash download and flash breakpoints
+monitor flash download = 1
+
+# Load the program
+load
+
+# Reset peripheral (RSTC_CR)
+set *0x400e1a00 = 0xA5000004
+
+# Initialize PC and stack pointer
+mon reg sp=(0x20000000)
+#set *0x20000004 = *0x20000004 & 0xFFFFFFFE
+mon reg pc=(0x20000004)
+
+info reg
+
+break main
+
+# End of 'reset' command
+end
diff --git a/hardware/digistump/sam/variants/digix/debug_scripts/iar/arduino_due_flash.mac b/hardware/digistump/sam/variants/digix/debug_scripts/iar/arduino_due_flash.mac
new file mode 100644
index 0000000..9595835
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/debug_scripts/iar/arduino_due_flash.mac
@@ -0,0 +1,44 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any  kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: at91sam3u-ek-flash.mac
+//  User setup file for CSPY debugger.
+// ---------------------------------------------------------
+__var __mac_i;
+__var __mac_pt;
+
+/*********************************************************************
+*
+*       execUserReset()
+*/
+execUserReset()
+{
+    __message "------------------------------ execUserReset ---------------------------------";
+    __message "-------------------------------Set PC Reset ----------------------------------";
+
+    __hwReset(0);
+
+    // perpheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1200,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserPreload()
+*/
+execUserPreload()
+{
+    __message "------------------------------ execUserPreload ---------------------------------";
+
+    __hwReset(0);                          //* Hardware Reset: CPU is automatically halted after the reset
+
+    // perpheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1200,"Memory");
+}
diff --git a/hardware/digistump/sam/variants/digix/debug_scripts/iar/arduino_due_sram.mac b/hardware/digistump/sam/variants/digix/debug_scripts/iar/arduino_due_sram.mac
new file mode 100644
index 0000000..ba86029
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/debug_scripts/iar/arduino_due_sram.mac
@@ -0,0 +1,44 @@
+// ---------------------------------------------------------
+//   ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any  kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+//  File: at91sam3u-ek-sram.mac
+//  User setup file for CSPY debugger.
+// ---------------------------------------------------------
+__var __mac_i;
+__var __mac_pt;
+
+/*********************************************************************
+*
+*       execUserReset()
+*/
+execUserReset()
+{
+    __message "------------------------------ execUserReset ---------------------------------";
+    __message "-------------------------------Set PC Reset ----------------------------------";
+
+     //__hwReset(50);
+
+    // perpheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1200,"Memory");
+}
+
+/*********************************************************************
+*
+*       execUserPreload()
+*/
+execUserPreload()
+{
+    __message "------------------------------ execUserPreload ---------------------------------";
+
+    __hwReset(0);                          //* Hardware Reset: CPU is automatically halted after the reset
+    
+    // perpheral reset RSTC_CR
+    __writeMemory32(0xA5000004,0x400e1200,"Memory");
+}
diff --git a/hardware/digistump/sam/variants/digix/libsam_sam3x8e_gcc_rel.a b/hardware/digistump/sam/variants/digix/libsam_sam3x8e_gcc_rel.a
new file mode 100644
index 0000000..7768e87
Binary files /dev/null and b/hardware/digistump/sam/variants/digix/libsam_sam3x8e_gcc_rel.a differ
diff --git a/hardware/digistump/sam/variants/digix/libsam_sam3x8e_gcc_rel.a.txt b/hardware/digistump/sam/variants/digix/libsam_sam3x8e_gcc_rel.a.txt
new file mode 100644
index 0000000..061d158
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/libsam_sam3x8e_gcc_rel.a.txt
@@ -0,0 +1,575 @@
+
+adc10_sam3u.o:
+
+adc12_sam3u.o:
+
+adc_sam3snxa.o:
+
+pio.o:
+00000000 T PIO_Clear
+00000000 T PIO_Configure
+00000000 T PIO_DisableInterrupt
+00000000 T PIO_Get
+00000000 T PIO_GetOutputDataStatus
+00000000 T PIO_PullUp
+00000000 T PIO_Set
+00000000 T PIO_SetDebounceFilter
+00000000 T PIO_SetInput
+00000000 T PIO_SetOutput
+00000000 T PIO_SetPeripheral
+
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+00000000 T pmc_clr_fast_startup_input
+00000000 T pmc_disable_all_pck
+00000000 T pmc_disable_all_periph_clk
+00000000 T pmc_disable_interrupt
+00000000 T pmc_disable_pck
+00000000 T pmc_disable_periph_clk
+00000000 T pmc_disable_pllack
+00000000 T pmc_disable_udpck
+00000000 T pmc_disable_upll_clock
+00000000 T pmc_enable_all_pck
+00000000 T pmc_enable_all_periph_clk
+00000000 T pmc_enable_backupmode
+00000000 T pmc_enable_interrupt
+00000000 T pmc_enable_pck
+00000000 T pmc_enable_periph_clk
+00000000 T pmc_enable_pllack
+00000000 T pmc_enable_sleepmode
+00000000 T pmc_enable_udpck
+00000000 T pmc_enable_upll_clock
+00000000 T pmc_enable_waitmode
+00000000 T pmc_get_interrupt_mask
+00000000 T pmc_get_status
+00000000 T pmc_get_writeprotect_status
+00000000 T pmc_is_locked_pllack
+00000000 T pmc_is_locked_upll
+00000000 T pmc_is_pck_enabled
+00000000 T pmc_is_periph_clk_enabled
+00000000 T pmc_mck_set_prescaler
+00000000 T pmc_mck_set_source
+00000000 T pmc_osc_disable_fastrc
+00000000 T pmc_osc_disable_xtal
+00000000 T pmc_osc_enable_fastrc
+00000000 T pmc_osc_is_ready_32kxtal
+00000000 T pmc_osc_is_ready_mainck
+00000000 T pmc_pck_set_prescaler
+00000000 T pmc_pck_set_source
+00000000 T pmc_set_fast_startup_input
+00000000 T pmc_set_writeprotect
+00000000 T pmc_switch_mainck_to_fastrc
+00000000 T pmc_switch_mainck_to_xtal
+00000000 T pmc_switch_mck_to_mainck
+00000000 T pmc_switch_mck_to_pllack
+00000000 T pmc_switch_mck_to_sclk
+00000000 T pmc_switch_mck_to_upllck
+00000000 T pmc_switch_pck_to_mainck
+00000000 T pmc_switch_pck_to_pllack
+00000000 T pmc_switch_pck_to_sclk
+00000000 T pmc_switch_pck_to_upllck
+00000000 T pmc_switch_sclk_to_32kxtal
+00000000 T pmc_switch_udpck_to_pllack
+00000000 T pmc_switch_udpck_to_upllck
+
+pwmc.o:
+00000000 r C.9.8049
+00000000 t FindClockConfiguration
+00000000 T PWMC_ConfigureChannel
+00000000 T PWMC_ConfigureChannelExt
+00000000 T PWMC_ConfigureClocks
+00000000 T PWMC_ConfigureComparisonUnit
+00000000 T PWMC_ConfigureEventLineMode
+00000000 T PWMC_ConfigureSyncChannel
+00000000 T PWMC_DisableChannel
+00000000 T PWMC_DisableChannelIt
+00000000 T PWMC_DisableIt
+00000000 T PWMC_DisableOverrideOutput
+00000000 T PWMC_EnableChannel
+00000000 T PWMC_EnableChannelIt
+00000000 T PWMC_EnableFaultProtection
+00000000 T PWMC_EnableIt
+00000000 T PWMC_EnableOverrideOutput
+00000000 T PWMC_FaultClear
+00000000 T PWMC_SetDeadTime
+00000000 T PWMC_SetDutyCycle
+00000000 T PWMC_SetFaultMode
+00000000 T PWMC_SetFaultProtectionValue
+00000000 T PWMC_SetOverrideValue
+00000000 T PWMC_SetPeriod
+00000000 T PWMC_SetSyncChannelUpdatePeriod
+00000000 T PWMC_SetSyncChannelUpdateUnlock
+00000000 T PWMC_WriteBuffer
+         U __assert_func
+00000000 r __func__.6631
+00000000 r __func__.6642
+00000000 r __func__.6657
+00000000 r __func__.6668
+00000000 r __func__.6679
+00000000 r __func__.6686
+00000000 r __func__.6770
+00000000 r __func__.6776
+
+rtc.o:
+00000000 T RTC_ClearSCCR
+00000000 T RTC_DisableIt
+00000000 T RTC_EnableIt
+00000000 T RTC_GetDate
+00000000 T RTC_GetHourMode
+00000000 T RTC_GetSR
+00000000 T RTC_GetTime
+00000000 T RTC_SetDate
+00000000 T RTC_SetDateAlarm
+00000000 T RTC_SetHourMode
+00000000 T RTC_SetTime
+00000000 T RTC_SetTimeAlarm
+         U __assert_func
+00000000 r __func__.6628
+00000000 r __func__.6637
+00000000 r __func__.6642
+
+rtt.o:
+00000000 T RTT_EnableIT
+00000000 T RTT_GetStatus
+00000000 T RTT_GetTime
+00000000 T RTT_SetAlarm
+00000000 T RTT_SetPrescaler
+         U __assert_func
+00000000 r __func__.6635
+00000000 r __func__.6643
+
+spi.o:
+00000000 T SPI_Configure
+00000000 T SPI_ConfigureNPCS
+00000000 T SPI_Disable
+00000000 T SPI_DisableIt
+00000000 T SPI_Enable
+00000000 T SPI_EnableIt
+00000000 T SPI_GetStatus
+00000000 T SPI_IsFinished
+00000000 T SPI_Read
+00000000 T SPI_Write
+         U pmc_enable_periph_clk
+
+tc.o:
+00000000 T TC_Configure
+00000000 T TC_FindMckDivisor
+00000000 T TC_GetStatus
+00000000 T TC_ReadCV
+00000000 T TC_SetRA
+00000000 T TC_SetRB
+00000000 T TC_SetRC
+00000000 T TC_Start
+00000000 T TC_Stop
+         U __assert_func
+00000000 r __func__.6630
+00000000 r __func__.6636
+00000000 r __func__.6642
+
+timetick.o:
+00000000 T GetTickCount
+00000000 T Sleep
+00000000 T TimeTick_Configure
+00000000 T TimeTick_Increment
+00000000 T Wait
+00000000 b _dwTickCount
+
+twi.o:
+00000000 T TWI_ByteReceived
+00000000 T TWI_ByteSent
+00000000 T TWI_ConfigureMaster
+00000000 T TWI_ConfigureSlave
+00000000 T TWI_DisableIt
+00000000 T TWI_EnableIt
+00000000 T TWI_GetMaskedStatus
+00000000 T TWI_GetStatus
+00000000 T TWI_ReadByte
+00000000 T TWI_SendSTOPCondition
+00000000 T TWI_StartRead
+00000000 T TWI_StartWrite
+00000000 T TWI_Stop
+00000000 T TWI_TransferComplete
+00000000 T TWI_WriteByte
+         U __assert_func
+00000000 r __func__.7003
+00000000 r __func__.7018
+00000000 r __func__.7022
+00000000 r __func__.7029
+00000000 r __func__.7033
+00000000 r __func__.7038
+00000000 r __func__.7046
+00000000 r __func__.7060
+00000000 r __func__.7065
+00000000 r __func__.7069
+00000000 r __func__.7074
+00000000 r __func__.7078
+
+usart.o:
+00000000 T USART_Configure
+00000000 T USART_DisableIt
+00000000 T USART_EnableIt
+00000000 T USART_GetChar
+00000000 T USART_GetStatus
+00000000 T USART_IsDataAvailable
+00000000 T USART_IsRxReady
+00000000 T USART_PutChar
+00000000 T USART_Read
+00000000 T USART_ReadBuffer
+00000000 T USART_SetIrdaFilter
+00000000 T USART_SetReceiverEnabled
+00000000 T USART_SetTransmitterEnabled
+00000000 T USART_Write
+00000000 T USART_WriteBuffer
+         U __assert_func
+00000000 r __func__.6924
+
+wdt.o:
+00000000 T WDT_Disable
+00000000 T WDT_Enable
+00000000 T WDT_GetPeriod
+00000000 T WDT_GetStatus
+00000000 T WDT_Restart
+
+system_sam3xa.o:
+00000000 D SystemCoreClock
+00000000 T SystemCoreClockUpdate
+00000000 T SystemInit
+00000000 T system_init_flash
+
+startup_sam3xa.o:
+         U ADC_Handler
+         U BusFault_Handler
+         U CAN0_Handler
+         U CAN1_Handler
+         U DACC_Handler
+         U DMAC_Handler
+         U DebugMon_Handler
+         U EFC0_Handler
+         U EFC1_Handler
+         U EMAC_Handler
+         U HSMCI_Handler
+         U HardFault_Handler
+         U MemManage_Handler
+         U NMI_Handler
+         U PIOA_Handler
+         U PIOB_Handler
+         U PIOC_Handler
+         U PIOD_Handler
+         U PMC_Handler
+         U PWM_Handler
+         U PendSV_Handler
+         U RSTC_Handler
+         U RTC_Handler
+         U RTT_Handler
+00000000 T Reset_Handler
+         U SMC_Handler
+         U SPI0_Handler
+         U SSC_Handler
+         U SUPC_Handler
+         U SVC_Handler
+         U SysTick_Handler
+         U TC0_Handler
+         U TC1_Handler
+         U TC2_Handler
+         U TC3_Handler
+         U TC4_Handler
+         U TC5_Handler
+         U TC6_Handler
+         U TC7_Handler
+         U TC8_Handler
+         U TRNG_Handler
+         U TWI0_Handler
+         U TWI1_Handler
+         U UART_Handler
+         U UOTGHS_Handler
+         U USART0_Handler
+         U USART1_Handler
+         U USART2_Handler
+         U USART3_Handler
+         U UsageFault_Handler
+         U WDT_Handler
+         U _erelocate
+         U _estack
+         U _etext
+         U _ezero
+         U _sfixed
+         U _srelocate
+         U _szero
+00000000 R exception_table
+         U main
+
+adc.o:
+00000000 r C.0.8141
+00000000 T adc_configure_power_save
+00000000 T adc_configure_sequence
+00000000 T adc_configure_timing
+00000000 T adc_configure_trigger
+00000000 T adc_disable_all_channel
+00000000 T adc_disable_anch
+00000000 T adc_disable_channel
+00000000 T adc_disable_channel_differential_input
+00000000 T adc_disable_channel_input_offset
+00000000 T adc_disable_interrupt
+00000000 T adc_disable_tag
+00000000 T adc_disable_ts
+00000000 T adc_enable_all_channel
+00000000 T adc_enable_anch
+00000000 T adc_enable_channel
+00000000 T adc_enable_channel_differential_input
+00000000 T adc_enable_channel_input_offset
+00000000 T adc_enable_interrupt
+00000000 T adc_enable_tag
+00000000 T adc_enable_ts
+00000000 T adc_get_actual_adc_clock
+00000000 T adc_get_channel_status
+00000000 T adc_get_channel_value
+00000000 T adc_get_comparison_mode
+00000000 T adc_get_interrupt_mask
+00000000 T adc_get_latest_value
+00000000 T adc_get_overrun_status
+00000000 T adc_get_pdc_base
+00000000 T adc_get_status
+00000000 T adc_get_tag
+00000000 T adc_get_writeprotect_status
+00000000 T adc_init
+00000000 T adc_set_bias_current
+00000000 T adc_set_channel_input_gain
+00000000 T adc_set_comparison_channel
+00000000 T adc_set_comparison_mode
+00000000 T adc_set_comparison_window
+00000000 T adc_set_resolution
+00000000 T adc_set_writeprotect
+00000000 T adc_start
+00000000 T adc_start_sequencer
+00000000 T adc_stop
+00000000 T adc_stop_sequencer
+
+udp.o:
+
+udphs.o:
+
+uotghs.o:
+00000000 T UOTGHS_Handler
+00000000 B gpf_isr
+
+interrupt_sam_nvic.o:
+00000000 D g_interrupt_enabled
+
+uotghs_device.o:
+00000000 T UDD_Attach
+00000000 T UDD_ClearIN
+00000000 T UDD_ClearOUT
+00000000 T UDD_ClearSetupInt
+00000000 T UDD_Detach
+00000000 T UDD_FifoByteCount
+00000000 T UDD_GetFrameNumber
+00000000 T UDD_Init
+00000000 T UDD_InitEP
+00000000 T UDD_InitEndpoints
+00000000 T UDD_ReadWriteAllowed
+00000000 T UDD_ReceivedSetupInt
+00000000 T UDD_Recv
+00000000 T UDD_Recv8
+00000000 T UDD_ReleaseRX
+00000000 T UDD_ReleaseTX
+00000000 T UDD_Send
+00000000 T UDD_Send8
+00000000 T UDD_SetAddress
+00000000 T UDD_SetStack
+00000000 T UDD_Stall
+00000000 T UDD_WaitForINOrOUT
+00000000 T UDD_WaitIN
+00000000 T UDD_WaitOUT
+         U g_interrupt_enabled
+         U gpf_isr
+         U pmc_enable_periph_clk
+         U pmc_enable_udpck
+         U pmc_enable_upll_clock
+         U pmc_switch_udpck_to_upllck
+00000000 b ul_recv_fifo_ptr
+00000000 b ul_send_fifo_ptr
+
+uotghs_host.o:
+00000000 T UHD_BusReset
+00000000 T UHD_GetVBUSState
+00000000 t UHD_ISR
+00000000 T UHD_Init
+00000000 T UHD_Pipe0_Alloc
+00000000 T UHD_Pipe_Alloc
+00000000 T UHD_Pipe_Free
+00000000 T UHD_Pipe_Is_Transfer_Complete
+00000000 T UHD_Pipe_Read
+00000000 T UHD_Pipe_Send
+00000000 T UHD_Pipe_Write
+00000000 T UHD_SetStack
+         U g_interrupt_enabled
+         U gpf_isr
+         U pmc_enable_periph_clk
+         U pmc_enable_udpck
+         U pmc_enable_upll_clock
+         U pmc_switch_udpck_to_upllck
+00000000 b uhd_state
+
+dacc.o:
+00000000 T dacc_disable_channel
+00000000 T dacc_disable_interrupt
+00000000 T dacc_disable_trigger
+00000000 T dacc_enable_channel
+00000000 T dacc_enable_flexible_selection
+00000000 T dacc_enable_interrupt
+00000000 T dacc_get_analog_control
+00000000 T dacc_get_channel_status
+00000000 T dacc_get_interrupt_mask
+00000000 T dacc_get_interrupt_status
+00000000 T dacc_get_pdc_base
+00000000 T dacc_get_writeprotect_status
+00000000 T dacc_reset
+00000000 T dacc_set_analog_control
+00000000 T dacc_set_channel_selection
+00000000 T dacc_set_power_save
+00000000 T dacc_set_timing
+00000000 T dacc_set_transfer_mode
+00000000 T dacc_set_trigger
+00000000 T dacc_set_writeprotect
+00000000 T dacc_write_conversion_data
+
+can.o:
+00000000 R can_bit_time
+00000000 T can_disable
+00000000 T can_disable_autobaud_listen_mode
+00000000 T can_disable_interrupt
+00000000 T can_disable_low_power_mode
+00000000 T can_disable_overload_frame
+00000000 T can_disable_time_triggered_mode
+00000000 T can_disable_timer_freeze
+00000000 T can_disable_tx_repeat
+00000000 T can_enable
+00000000 T can_enable_autobaud_listen_mode
+00000000 T can_enable_interrupt
+00000000 T can_enable_low_power_mode
+00000000 T can_enable_overload_frame
+00000000 T can_enable_time_triggered_mode
+00000000 T can_enable_timer_freeze
+00000000 T can_enable_tx_repeat
+00000000 T can_get_internal_timer_value
+00000000 T can_get_interrupt_mask
+00000000 T can_get_rx_error_cnt
+00000000 T can_get_status
+00000000 T can_get_timestamp_value
+00000000 T can_get_tx_error_cnt
+00000000 T can_global_send_abort_cmd
+00000000 T can_global_send_transfer_cmd
+00000000 T can_init
+00000000 T can_mailbox_get_status
+00000000 T can_mailbox_init
+00000000 T can_mailbox_read
+00000000 T can_mailbox_send_abort_cmd
+00000000 T can_mailbox_send_transfer_cmd
+00000000 T can_mailbox_set_timemark
+00000000 T can_mailbox_tx_remote_frame
+00000000 T can_mailbox_write
+00000000 T can_reset_all_mailbox
+00000000 T can_reset_internal_timer
+00000000 T can_reset_mailbox_data
+00000000 T can_set_rx_sync_stage
+00000000 T can_set_timestamp_capture_point
+         U memset
+
+efc.o:
+00000000 T efc_disable_frdy_interrupt
+00000000 T efc_enable_frdy_interrupt
+00000000 T efc_get_flash_access_mode
+00000000 T efc_get_result
+00000000 T efc_get_status
+00000000 T efc_get_wait_state
+00000000 T efc_init
+00000000 T efc_perform_command
+00000070 T efc_perform_fcr
+00000000 T efc_perform_read_sequence
+00000000 T efc_set_flash_access_mode
+00000000 T efc_set_wait_state
+0000006c T efc_write_fmr
+00000000 b iap_perform_command.6905
+
+gpbr.o:
+00000000 T gpbr_read
+00000000 T gpbr_write
+
+ssc.o:
+         U memset
+00000000 T ssc_disable_interrupt
+00000000 T ssc_disable_rx
+00000000 T ssc_disable_tx
+00000000 T ssc_disable_tx_frame_sync_data
+00000000 T ssc_enable_interrupt
+00000000 T ssc_enable_rx
+00000000 T ssc_enable_tx
+00000000 T ssc_enable_tx_frame_sync_data
+00000000 T ssc_get_interrupt_mask
+00000000 T ssc_get_rx_access
+00000000 T ssc_get_rx_compare
+00000000 T ssc_get_status
+00000000 T ssc_get_tx_access
+00000000 T ssc_get_writeprotect_status
+00000000 T ssc_i2s_set_receiver
+00000000 T ssc_i2s_set_transmitter
+00000000 T ssc_is_rx_enabled
+00000000 T ssc_is_rx_ready
+00000000 T ssc_is_tx_empty
+00000000 T ssc_is_tx_enabled
+00000000 T ssc_is_tx_ready
+00000000 T ssc_read
+00000000 T ssc_read_sync_data
+00000000 T ssc_reset
+00000000 T ssc_set_clock_divider
+00000000 T ssc_set_loop_mode
+00000000 T ssc_set_normal_mode
+00000000 T ssc_set_receiver
+00000000 T ssc_set_rx_compare
+00000000 T ssc_set_rx_stop_selection
+00000000 T ssc_set_td_default_level
+00000000 T ssc_set_transmitter
+00000000 T ssc_set_writeprotect
+00000000 T ssc_write
+00000000 T ssc_write_sync_data
+
+trng.o:
+00000000 T trng_disable
+00000000 T trng_disable_interrupt
+00000000 T trng_enable
+00000000 T trng_enable_interrupt
+00000000 T trng_get_interrupt_mask
+00000000 T trng_get_interrupt_status
+00000000 T trng_read_output_data
+
+rstc.o:
+00000000 T rstc_disable_user_reset
+00000000 T rstc_disable_user_reset_interrupt
+00000000 T rstc_enable_user_reset
+00000000 T rstc_enable_user_reset_interrupt
+00000000 T rstc_get_reset_cause
+00000000 T rstc_get_status
+00000000 T rstc_reset_extern
+00000000 T rstc_set_external_reset
+00000000 T rstc_start_software_reset
+
+emac.o:
+00000000 t circ_inc
+00000000 T emac_dev_get_tx_load
+00000000 T emac_dev_init
+00000000 T emac_dev_read
+00000000 T emac_dev_reset
+00000000 T emac_dev_set_rx_callback
+00000000 T emac_dev_set_tx_wakeup_callback
+00000000 T emac_dev_write
+00000000 T emac_handler
+00000000 T emac_phy_read
+00000000 T emac_phy_write
+00000000 t emac_reset_rx_mem
+00000000 t emac_reset_tx_mem
+00000000 t emac_wait_phy.clone.1
+00000000 b gs_rx_desc
+00000000 b gs_tx_callback
+00000000 b gs_tx_desc
+00000000 b gs_uc_rx_buffer
+00000000 b gs_uc_tx_buffer
+         U memcpy
\ No newline at end of file
diff --git a/hardware/digistump/sam/variants/digix/linker_scripts/gcc/flash.ld b/hardware/digistump/sam/variants/digix/linker_scripts/gcc/flash.ld
new file mode 100644
index 0000000..53f2b5f
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/linker_scripts/gcc/flash.ld
@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss ALIGN(4) (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+       used for linker to calculate size of stack sections, and assign
+       values to stack symbols later */
+    .stack_dummy :
+    {
+        *(.stack*)
+    } > ram
+
+    /* Set stack top to end of ram, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(ram) + LENGTH(ram);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(_sstack = __StackLimit);
+    PROVIDE(_estack = __StackTop);
+}
diff --git a/hardware/digistump/sam/variants/digix/linker_scripts/gcc/sram.ld b/hardware/digistump/sam/variants/digix/linker_scripts/gcc/sram.ld
new file mode 100644
index 0000000..2a0d54e
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/linker_scripts/gcc/sram.ld
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------------
+ *         SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2012, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+	rom (rx)    : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */
+	sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */
+	sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */
+	ram (rwx)   : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */
+}
+
+/* The stack size used by the application. NOTE: you need to adjust  */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000 ;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > ram
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ram
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _end = . ;
+}
+
diff --git a/hardware/digistump/sam/variants/digix/linker_scripts/iar/flash.icf b/hardware/digistump/sam/variants/digix/linker_scripts/iar/flash.icf
new file mode 100644
index 0000000..956230f
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/linker_scripts/iar/flash.icf
@@ -0,0 +1,49 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x00080000; /*Add for CMSIS*/
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20007FFF;
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;
+define symbol __ICFEDIT_region_ROM0_start__  = 0x00080000;
+define symbol __ICFEDIT_region_ROM0_end__    = 0x0009FFFF;
+define symbol __ICFEDIT_region_ROM1_start__  = 0x00100000;
+define symbol __ICFEDIT_region_ROM1_end__    = 0x0011FFFF;
+/*-Sizes-*/
+/*define symbol __ICFEDIT_size_cstack__        = 0x1000;*//*for nandflash*/
+define symbol __ICFEDIT_size_cstack__        = 0x2000;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/*-Specials-*/
+/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/
+/*define symbol __ICFEDIT_size_vectors__          = 0x100;*/ /*Referenced for CMSIS*/
+/*-Exports-*/
+/*export symbol __ICFEDIT_region_RAM_VECT_start__;*/
+export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/ /*Referenced for CMSIS*/
+/*define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/
+define region ROM0_region     = mem:[from __ICFEDIT_region_ROM0_start__ to __ICFEDIT_region_ROM0_end__];
+define region ROM1_region     = mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__];
+
+/*define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { };*/
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+/*place at start of ROM0_region { readonly section .vectors };*/ /*Referenced for CMSIS*/
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec }; /*Add for CMSIS*/
+place in ROM0_region          { readonly };
+place in RAM0_region          { readwrite, block HEAP };
+place in RAM1_region          { block CSTACK }; /* for nandflash*/
+/*place in RAM_VECT_region      { block RamVect };*/ /*Referenced for CMSIS*/
\ No newline at end of file
diff --git a/hardware/digistump/sam/variants/digix/linker_scripts/iar/sram.icf b/hardware/digistump/sam/variants/digix/linker_scripts/iar/sram.icf
new file mode 100644
index 0000000..d7d3353
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/linker_scripts/iar/sram.icf
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Vector table start*/
+define symbol __ICFEDIT_vector_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM0_start__  = 0x20000000;
+define symbol __ICFEDIT_region_RAM0_end__    = 0x20007FFF;
+define symbol __ICFEDIT_region_RAM1_start__  = 0x20080000;
+define symbol __ICFEDIT_region_RAM1_end__    = 0x20083FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__        = 0x900;
+define symbol __ICFEDIT_size_heap__          = 0x200;
+/*-Exports-*/
+export symbol __ICFEDIT_vector_start__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size   = 4G;
+define region RAM0_region     = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__];
+define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
+/*define region RAM_region      = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] |
+                                mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/
+
+/* define block RamVect   with alignment = 8, size = __ICFEDIT_size_vectors__  { }; */
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_vector_start__ { readonly section .intvec };
+place in RAM0_region          { readonly };
+place in RAM1_region          { readwrite, block CSTACK, block HEAP };
diff --git a/hardware/digistump/sam/variants/digix/pins_arduino.h b/hardware/digistump/sam/variants/digix/pins_arduino.h
new file mode 100644
index 0000000..4e279aa
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/pins_arduino.h
@@ -0,0 +1,21 @@
+/*
+  Copyright (c) 2011 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+// API compatibility
+#include "variant.h"
+
diff --git a/hardware/digistump/sam/variants/digix/variant.cpp b/hardware/digistump/sam/variants/digix/variant.cpp
new file mode 100644
index 0000000..60e93af
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/variant.cpp
@@ -0,0 +1,442 @@
+/*
+  Copyright (c) 2011 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include "variant.h"
+
+/*
+ * DUE Board pin   |  PORT  | Label
+ * ----------------+--------+-------
+ *   0             |  PA8   | "RX0"
+ *   1             |  PA9   | "TX0"
+ *   2       TIOA0 |  PB25  |
+ *   3       TIOA7 |  PC28  |
+ *   4       NPCS1 |  PA29  |
+ *           TIOB6 |  PC26  |
+ *   5       TIOA6 |  PC25  |
+ *   6       PWML7 |  PC24  |
+ *   7       PWML6 |  PC23  |
+ *   8       PWML5 |  PC22  |
+ *   9       PWML4 |  PC21  |
+ *  10       NPCS0 |  PA28  |
+ *           TIOB7 |  PC29  |
+ *  11       TIOA8 |  PD7   |
+ *  12       TIOB8 |  PD8   |
+ *  13       TIOB0 |  PB27  | LED AMBER "L"
+ *  14       TXD3  |  PD4   | "TX3"
+ *  15       RXD3  |  PD5   | "RX3"
+ *  16       TXD1  |  PA13  | "TX2"
+ *  17       RXD1  |  PA12  | "RX2"
+ *  18       TXD0  |  PA11  | "TX1"
+ *  19       RXD0  |  PA10  | "RX1"
+ *  20             |  PB12  | "SDA"
+ *  21             |  PB13  | "SCL"
+ *  22             |  PB26  |
+ *  23             |  PA14  |
+ *  24             |  PA15  |
+ *  25             |  PD0   |
+ *  26             |  PD1   |
+ *  27             |  PD2   |
+ *  28             |  PD3   |
+ *  29             |  PD6   |
+ *  30             |  PD9   |
+ *  31             |  PA7   |
+ *  32             |  PD10  |
+ *  33             |  PC1   |
+ *  34             |  PC2   |
+ *  35             |  PC3   |
+ *  36             |  PC4   |
+ *  37             |  PC5   |
+ *  38             |  PC6   |
+ *  39             |  PC7   |
+ *  40             |  PC8   |
+ *  41             |  PC9   |
+ *  42             |  PA19  |
+ *  43             |  PA20  |
+ *  44             |  PC19  |
+ *  45             |  PC18  |
+ *  46             |  PC17  |
+ *  47             |  PC16  |
+ *  48             |  PC15  |
+ *  49             |  PC14  |
+ *  50             |  PC13  |
+ *  51             |  PC12  |
+ *  52       NPCS2 |  PB21  |
+ *  53             |  PB14  |
+ *  54             |  PA16  | "A0"
+ *  55             |  PA24  | "A1"
+ *  56             |  PA23  | "A2"
+ *  57             |  PA22  | "A3"
+ *  58       TIOB2 |  PA6   | "A4"
+ *  69             |  PA4   | "A5"
+ *  60       TIOB1 |  PA3   | "A6"
+ *  61       TIOA1 |  PA2   | "A7"
+ *  62             |  PB17  | "A8"
+ *  63             |  PB18  | "A9"
+ *  64             |  PB19  | "A10"
+ *  65             |  PB20  | "A11"
+ *  66             |  PB15  | "DAC0"
+ *  67             |  PB16  | "DAC1"
+ *  68             |  PA1   | "CANRX"
+ *  69             |  PA0   | "CANTX"
+ *  70             |  PA17  | "SDA1"
+ *  71             |  PA18  | "SCL1"
+ *  72             |  PC30  | LED AMBER "RX"
+ *  73             |  PA21  | LED AMBER "TX"
+ *  74       MISO  |  PA25  |
+ *  75       MOSI  |  PA26  |
+ *  76       SCLK  |  PA27  |
+ *  77       NPCS0 |  PA28  |
+ *  78       NPCS3 |  PB23  | unconnected!
+ *
+ * USB pin         |  PORT
+ * ----------------+--------
+ *  ID             |  PB11
+ *  VBOF           |  PB10
+ *
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Pins descriptions
+ */
+extern const PinDescription g_APinDescription[]=
+{
+  // 0 .. 53 - Digital pins
+  // ----------------------
+  // 0/1 - UART (Serial)
+  { PIOA, PIO_PA8A_URXD,     ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT,  PIN_ATTR_DIGITAL,                 NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // URXD
+  { PIOA, PIO_PA9A_UTXD,     ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT,  PIN_ATTR_DIGITAL,                 NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // UTXD
+
+  // 2
+  { PIOB, PIO_PB25B_TIOA0,   ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_TIMER), NO_ADC, NO_ADC, NOT_ON_PWM,  TC0_CHA0     }, // TIOA0
+  { PIOC, PIO_PC28B_TIOA7,   ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_TIMER), NO_ADC, NO_ADC, NOT_ON_PWM,  TC2_CHA7     }, // TIOA7
+  { PIOC, PIO_PC26B_TIOB6,   ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_TIMER), NO_ADC, NO_ADC, NOT_ON_PWM,  TC2_CHB6     }, // TIOB6
+
+  // 5
+  { PIOC, PIO_PC25B_TIOA6,   ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_TIMER), NO_ADC, NO_ADC, NOT_ON_PWM,  TC2_CHA6     }, // TIOA6
+  { PIOC, PIO_PC24B_PWML7,   ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM),   NO_ADC, NO_ADC, PWM_CH7,     NOT_ON_TIMER }, // PWML7
+  { PIOC, PIO_PC23B_PWML6,   ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM),   NO_ADC, NO_ADC, PWM_CH6,     NOT_ON_TIMER }, // PWML6
+  { PIOC, PIO_PC22B_PWML5,   ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM),   NO_ADC, NO_ADC, PWM_CH5,     NOT_ON_TIMER }, // PWML5
+  { PIOC, PIO_PC21B_PWML4,   ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM),   NO_ADC, NO_ADC, PWM_CH4,     NOT_ON_TIMER }, // PWML4
+  // 10
+  { PIOC, PIO_PC29B_TIOB7,   ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_TIMER), NO_ADC, NO_ADC, NOT_ON_PWM,  TC2_CHB7     }, // TIOB7
+  { PIOD, PIO_PD7B_TIOA8,    ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_TIMER), NO_ADC, NO_ADC, NOT_ON_PWM,  TC2_CHA8     }, // TIOA8
+  { PIOD, PIO_PD8B_TIOB8,    ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_TIMER), NO_ADC, NO_ADC, NOT_ON_PWM,  TC2_CHB8     }, // TIOB8
+
+  // 13 - AMBER LED
+  { PIOB, PIO_PB27B_TIOB0,   ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_TIMER), NO_ADC, NO_ADC, NOT_ON_PWM,  TC0_CHB0     }, // TIOB0
+
+  // 14/15 - USART3 (Serial3)
+  { PIOD, PIO_PD4B_TXD3,     ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // TXD3
+  { PIOD, PIO_PD5B_RXD3,     ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // RXD3
+
+  // 16/17 - USART1 (Serial2)
+  { PIOA, PIO_PA13A_TXD1,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // TXD1
+  { PIOA, PIO_PA12A_RXD1,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // RXD1
+
+  // 18/19 - USART0 (Serial1)
+  { PIOA, PIO_PA11A_TXD0,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // TXD0
+  { PIOA, PIO_PA10A_RXD0,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // RXD0
+
+  // 20/21 - TWI1
+  { PIOB, PIO_PB12A_TWD1,    ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // TWD1 - SDA0
+  { PIOB, PIO_PB13A_TWCK1,   ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // TWCK1 - SCL0
+
+  // 22
+  { PIOB, PIO_PB26,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 22
+  { PIOA, PIO_PA14,          ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 23
+  { PIOA, PIO_PA15,          ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 24
+  { PIOD, PIO_PD0,           ID_PIOD, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 25
+
+  // 26
+  { PIOD, PIO_PD1,           ID_PIOD, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 26
+  { PIOD, PIO_PD2,           ID_PIOD, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 27
+  { PIOD, PIO_PD3,           ID_PIOD, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 28
+  { PIOD, PIO_PD6,           ID_PIOD, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 29
+
+  // 30
+  { PIOD, PIO_PD9,           ID_PIOD, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 30
+  { PIOA, PIO_PA7,           ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 31
+  { PIOD, PIO_PD10,          ID_PIOD, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 32
+  { PIOC, PIO_PC1,           ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 33
+
+  // 34
+  { PIOC, PIO_PC2,           ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 34
+  { PIOC, PIO_PC3,           ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 35
+  { PIOC, PIO_PC4,           ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 36
+  { PIOC, PIO_PC5,           ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 37
+
+  // 38
+  { PIOC, PIO_PC6,           ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 38
+  { PIOC, PIO_PC7,           ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 39
+  { PIOC, PIO_PC8,           ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 40
+  { PIOC, PIO_PC9,           ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 41
+
+  // 42
+  { PIOA, PIO_PA19,          ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 42
+  { PIOA, PIO_PA20,          ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 43
+  { PIOC, PIO_PC19,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 44
+  { PIOC, PIO_PC18,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 45
+
+  // 46
+  { PIOC, PIO_PC17,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 46
+  { PIOC, PIO_PC16,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 47
+  { PIOC, PIO_PC15,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 48
+  { PIOC, PIO_PC14,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 49
+
+  // 50
+  { PIOC, PIO_PC13,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 50
+  { PIOC, PIO_PC12,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 51
+  { PIOB, PIO_PB21,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 52
+  { PIOB, PIO_PB14,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // PIN 53
+
+
+  // 54 .. 65 - Analog pins
+  // ----------------------
+  { PIOA, PIO_PA16X1_AD7,    ID_PIOA, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC0,   ADC7,   NOT_ON_PWM,  NOT_ON_TIMER }, // AD0
+  { PIOA, PIO_PA24X1_AD6,    ID_PIOA, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC1,   ADC6,   NOT_ON_PWM,  NOT_ON_TIMER }, // AD1
+  { PIOA, PIO_PA23X1_AD5,    ID_PIOA, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC2,   ADC5,   NOT_ON_PWM,  NOT_ON_TIMER }, // AD2
+  { PIOA, PIO_PA22X1_AD4,    ID_PIOA, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC3,   ADC4,   NOT_ON_PWM,  NOT_ON_TIMER }, // AD3
+  // 58
+  { PIOA, PIO_PA6X1_AD3,     ID_PIOA, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC4,   ADC3,   NOT_ON_PWM,  TC0_CHB2     }, // AD4
+  { PIOA, PIO_PA4X1_AD2,     ID_PIOA, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC5,   ADC2,   NOT_ON_PWM,  NOT_ON_TIMER }, // AD5
+  { PIOA, PIO_PA3X1_AD1,     ID_PIOA, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC6,   ADC1,   NOT_ON_PWM,  TC0_CHB1     }, // AD6
+  { PIOA, PIO_PA2X1_AD0,     ID_PIOA, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC7,   ADC0,   NOT_ON_PWM,  TC0_CHA1     }, // AD7
+  // 62
+  { PIOB, PIO_PB17X1_AD10,   ID_PIOB, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC8,   ADC10,  NOT_ON_PWM,  NOT_ON_TIMER }, // AD8
+  { PIOB, PIO_PB18X1_AD11,   ID_PIOB, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC9,   ADC11,  NOT_ON_PWM,  NOT_ON_TIMER }, // AD9
+  { PIOB, PIO_PB19X1_AD12,   ID_PIOB, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC10,  ADC12,  NOT_ON_PWM,  NOT_ON_TIMER }, // AD10
+  { PIOB, PIO_PB20X1_AD13,   ID_PIOB, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC11,  ADC13,  NOT_ON_PWM,  NOT_ON_TIMER }, // AD11
+
+  // 66/67 - DAC0/DAC1
+  { PIOB, PIO_PB15X1_DAC0,   ID_PIOB, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC12,  DA0,    NOT_ON_PWM,  NOT_ON_TIMER }, // DAC0
+  { PIOB, PIO_PB16X1_DAC1,   ID_PIOB, PIO_INPUT,    PIO_DEFAULT, PIN_ATTR_ANALOG,                   ADC13,  DA1,    NOT_ON_PWM,  NOT_ON_TIMER }, // DAC1
+
+  // 68/69 - CANRX0/CANTX0
+  { PIOA, PIO_PA1A_CANRX0,   ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  ADC14,  NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // CANRX
+  { PIOA, PIO_PA0A_CANTX0,   ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  ADC15,  NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // CANTX
+
+  // 70/71 - TWI0
+  { PIOA, PIO_PA17A_TWD0,    ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // TWD0 - SDA1
+  { PIOA, PIO_PA18A_TWCK0,   ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // TWCK0 - SCL1
+
+  // 72/73 - LEDs
+  { PIOC, PIO_PC30,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // LED AMBER RXL
+  { PIOA, PIO_PA21,          ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // LED AMBER TXL
+
+  // 74/75/76 - SPI
+  { PIOA, PIO_PA25A_SPI0_MISO,ID_PIOA,PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // MISO
+  { PIOA, PIO_PA26A_SPI0_MOSI,ID_PIOA,PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // MOSI
+  { PIOA, PIO_PA27A_SPI0_SPCK,ID_PIOA,PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // SPCK
+
+  // 77 - SPI CS0
+  { PIOA, PIO_PA28A_SPI0_NPCS0,ID_PIOA,PIO_PERIPH_A,PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // NPCS0
+
+  // 78 - SPI CS3 (unconnected)
+  { PIOB, PIO_PB23B_SPI0_NPCS3,ID_PIOB,PIO_PERIPH_B,PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // NPCS3
+
+  // 79 .. 84 - "All pins" masks
+
+  // 79 - TWI0 all pins
+  { PIOA, PIO_PA17A_TWD0|PIO_PA18A_TWCK0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), NO_ADC, NO_ADC, NOT_ON_PWM, NOT_ON_TIMER },
+  // 80 - TWI1 all pins
+  { PIOB, PIO_PB12A_TWD1|PIO_PB13A_TWCK1, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), NO_ADC, NO_ADC, NOT_ON_PWM, NOT_ON_TIMER },
+  // 81 - UART (Serial) all pins
+  { PIOA, PIO_PA8A_URXD|PIO_PA9A_UTXD, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), NO_ADC, NO_ADC, NOT_ON_PWM, NOT_ON_TIMER },
+  // 82 - USART0 (Serial1) all pins
+  { PIOA, PIO_PA11A_TXD0|PIO_PA10A_RXD0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), NO_ADC, NO_ADC, NOT_ON_PWM, NOT_ON_TIMER },
+  // 83 - USART1 (Serial2) all pins
+  { PIOA, PIO_PA13A_TXD1|PIO_PA12A_RXD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), NO_ADC, NO_ADC, NOT_ON_PWM, NOT_ON_TIMER },
+  // 84 - USART3 (Serial3) all pins
+  { PIOD, PIO_PD4B_TXD3|PIO_PD5B_RXD3, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), NO_ADC, NO_ADC, NOT_ON_PWM, NOT_ON_TIMER },
+
+  // 85 - USB
+  { PIOB, PIO_PB11A_UOTGID|PIO_PB10A_UOTGVBOF, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // ID - VBOF
+
+  // 86 - SPI CS2
+  { PIOB, PIO_PB21B_SPI0_NPCS2, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // NPCS2
+
+  // 87 - SPI CS1
+  { PIOA, PIO_PA29A_SPI0_NPCS1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // NPCS1
+
+  // 88/89 - CANRX1/CANTX1 (same physical pin for 66/53)
+  { PIOB, PIO_PB15A_CANRX1,     ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // CANRX1
+  { PIOB, PIO_PB14A_CANTX1,     ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, // CANTX1
+
+//DIGIX Definitions
+  { PIOB, PIO_PB0,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //90
+  { PIOB, PIO_PB1,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //91
+  { PIOB, PIO_PB2,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //92
+  { PIOB, PIO_PB3,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //93
+  { PIOB, PIO_PB4,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //94
+  { PIOB, PIO_PB5,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //95
+  { PIOB, PIO_PB6,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //96
+  { PIOB, PIO_PB7,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //97
+  { PIOB, PIO_PB8,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //98
+  { PIOB, PIO_PB9,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //99
+  { PIOA, PIO_PA5,          ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER },  //100 
+  { PIOB, PIO_PB22,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //101
+  { PIOB, PIO_PB23,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //102
+  { PIOB, PIO_PB24,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //103
+  { PIOC, PIO_PC27,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER },  //104
+  { PIOC, PIO_PC20,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //105
+  { PIOC, PIO_PC11,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //106
+  { PIOC, PIO_PC10,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //107
+  { PIOA, PIO_PA21,          ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER },  //108
+  { PIOC, PIO_PC30,          ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //109
+  { PIOB, PIO_PB29,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //110
+  { PIOB, PIO_PB30,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //111
+  { PIOB, PIO_PB31,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //112
+  { PIOB, PIO_PB28,          ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL,                  NO_ADC, NO_ADC, NOT_ON_PWM,  NOT_ON_TIMER }, //113
+
+
+
+
+  // END
+  { NULL, 0, 0, PIO_NOT_A_PIN, PIO_DEFAULT, 0, NO_ADC, NO_ADC, NOT_ON_PWM, NOT_ON_TIMER }
+} ;
+
+#ifdef __cplusplus
+}
+#endif
+
+/*
+ * UART objects
+ */
+RingBuffer rx_buffer1;
+
+UARTClass Serial0(UART, UART_IRQn, ID_UART, &rx_buffer1);
+
+// IT handlers
+void UART_Handler(void)
+{
+  Serial0.IrqHandler();
+}
+
+// ----------------------------------------------------------------------------
+/*
+ * USART objects
+ */
+RingBuffer rx_buffer2;
+RingBuffer rx_buffer3;
+RingBuffer rx_buffer4;
+
+USARTClass Serial1(USART0, USART0_IRQn, ID_USART0, &rx_buffer2);
+USARTClass Serial2(USART1, USART1_IRQn, ID_USART1, &rx_buffer3);
+USARTClass Serial3(USART3, USART3_IRQn, ID_USART3, &rx_buffer4);
+
+// IT handlers
+void USART0_Handler(void)
+{
+  Serial1.IrqHandler();
+}
+
+void USART1_Handler(void)
+{
+  Serial2.IrqHandler();
+}
+
+void USART3_Handler(void)
+{
+  Serial3.IrqHandler();
+}
+
+// ----------------------------------------------------------------------------
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void __libc_init_array(void);
+
+void init( void )
+{
+  SystemInit();
+
+  // Set Systick to 1ms interval, common to all SAM3 variants
+  if (SysTick_Config(SystemCoreClock / 1000))
+  {
+    // Capture error
+    while (true);
+  }
+
+  // Disable watchdog
+  WDT_Disable(WDT);
+
+  // Initialize C library
+  __libc_init_array();
+
+  // Disable pull-up on every pin
+  for (int i = 0; i < PINS_COUNT; i++)
+	  digitalWrite(i, LOW);
+
+  // Enable parallel access on PIO output data registers
+  PIOA->PIO_OWER = 0xFFFFFFFF;
+  PIOB->PIO_OWER = 0xFFFFFFFF;
+  PIOC->PIO_OWER = 0xFFFFFFFF;
+  PIOD->PIO_OWER = 0xFFFFFFFF;
+
+  // Initialize Serial port U(S)ART pins
+  PIO_Configure(
+    g_APinDescription[PINS_UART].pPort,
+    g_APinDescription[PINS_UART].ulPinType,
+    g_APinDescription[PINS_UART].ulPin,
+    g_APinDescription[PINS_UART].ulPinConfiguration);
+  digitalWrite(0, HIGH); // Enable pullup for RX0
+  PIO_Configure(
+    g_APinDescription[PINS_USART0].pPort,
+    g_APinDescription[PINS_USART0].ulPinType,
+    g_APinDescription[PINS_USART0].ulPin,
+    g_APinDescription[PINS_USART0].ulPinConfiguration);
+  PIO_Configure(
+    g_APinDescription[PINS_USART1].pPort,
+    g_APinDescription[PINS_USART1].ulPinType,
+    g_APinDescription[PINS_USART1].ulPin,
+    g_APinDescription[PINS_USART1].ulPinConfiguration);
+  PIO_Configure(
+    g_APinDescription[PINS_USART3].pPort,
+    g_APinDescription[PINS_USART3].ulPinType,
+    g_APinDescription[PINS_USART3].ulPin,
+    g_APinDescription[PINS_USART3].ulPinConfiguration);
+
+  // Initialize USB pins
+  PIO_Configure(
+    g_APinDescription[PINS_USB].pPort,
+    g_APinDescription[PINS_USB].ulPinType,
+    g_APinDescription[PINS_USB].ulPin,
+    g_APinDescription[PINS_USB].ulPinConfiguration);
+
+  // Initialize Analog Controller
+  pmc_enable_periph_clk(ID_ADC);
+  adc_init(ADC, SystemCoreClock, ADC_FREQ_MAX, ADC_STARTUP_FAST);
+  adc_configure_timing(ADC, 0, ADC_SETTLING_TIME_3, 1);
+  adc_configure_trigger(ADC, ADC_TRIG_SW, 0); // Disable hardware trigger.
+  adc_disable_interrupt(ADC, 0xFFFFFFFF); // Disable all ADC interrupts.
+  adc_disable_all_channel(ADC);
+
+  // Initialize analogOutput module
+  analogOutputInit();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/hardware/digistump/sam/variants/digix/variant.h b/hardware/digistump/sam/variants/digix/variant.h
new file mode 100644
index 0000000..87df285
--- /dev/null
+++ b/hardware/digistump/sam/variants/digix/variant.h
@@ -0,0 +1,213 @@
+/*
+  Copyright (c) 2011 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef _VARIANT_ARDUINO_DUE_X_
+#define _VARIANT_ARDUINO_DUE_X_
+
+/*----------------------------------------------------------------------------
+ *        Definitions
+ *----------------------------------------------------------------------------*/
+
+/** Frequency of the board main oscillator */
+#define VARIANT_MAINOSC   12000000
+
+/** Master clock frequency */
+#define VARIANT_MCK     84000000
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "Arduino.h"
+#ifdef __cplusplus
+#include "UARTClass.h"
+#include "USARTClass.h"
+#endif
+
+#ifdef __cplusplus
+extern "C"{
+#endif // __cplusplus
+
+/**
+ * Libc porting layers
+ */
+#if defined (  __GNUC__  ) /* GCC CS3 */
+#    include  /** RedHat Newlib minimal stub */
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Pins
+ *----------------------------------------------------------------------------*/
+
+// Number of pins defined in PinDescription array
+#define PINS_COUNT           (79u)
+#define NUM_DIGITAL_PINS     (53u)
+#define NUM_ANALOG_INPUTS    (12u)
+
+// Interrupts
+#define digitalPinToInterrupt(p)  ((p) < NUM_DIGITAL_PINS ? (p) : -1)
+
+// LEDs
+#define PIN_LED_13           (13u)
+#define PIN_LED_RXL          (72u)
+#define PIN_LED_TXL          (73u)
+#define PIN_LED              PIN_LED_13
+#define PIN_LED2             PIN_LED_RXL
+#define PIN_LED3             PIN_LED_TXL
+#define LED_BUILTIN          13
+
+/*
+ * SPI Interfaces
+ */
+#define SPI_INTERFACES_COUNT 1
+
+#define SPI_INTERFACE        SPI0
+#define SPI_INTERFACE_ID     ID_SPI0
+#define SPI_CHANNELS_NUM 4
+#define PIN_SPI_SS0          (77u)
+#define PIN_SPI_SS1          (87u)
+#define PIN_SPI_SS2          (86u)
+#define PIN_SPI_SS3          (78u)
+#define PIN_SPI_MOSI         (75u)
+#define PIN_SPI_MISO         (74u)
+#define PIN_SPI_SCK          (76u)
+#define BOARD_SPI_SS0        (10u)
+#define BOARD_SPI_SS1        (4u)
+#define BOARD_SPI_SS2        (52u)
+#define BOARD_SPI_SS3        PIN_SPI_SS3
+#define BOARD_SPI_DEFAULT_SS BOARD_SPI_SS3
+
+#define BOARD_PIN_TO_SPI_PIN(x) \
+  (x==BOARD_SPI_SS0 ? PIN_SPI_SS0 : \
+  (x==BOARD_SPI_SS1 ? PIN_SPI_SS1 : \
+  (x==BOARD_SPI_SS2 ? PIN_SPI_SS2 : PIN_SPI_SS3 )))
+#define BOARD_PIN_TO_SPI_CHANNEL(x) \
+  (x==BOARD_SPI_SS0 ? 0 : \
+  (x==BOARD_SPI_SS1 ? 1 : \
+  (x==BOARD_SPI_SS2 ? 2 : 3)))
+
+static const uint8_t SS   = BOARD_SPI_SS0;
+static const uint8_t SS1  = BOARD_SPI_SS1;
+static const uint8_t SS2  = BOARD_SPI_SS2;
+static const uint8_t SS3  = BOARD_SPI_SS3;
+static const uint8_t MOSI = PIN_SPI_MOSI;
+static const uint8_t MISO = PIN_SPI_MISO;
+static const uint8_t SCK  = PIN_SPI_SCK;
+
+/*
+ * Wire Interfaces
+ */
+#define WIRE_INTERFACES_COUNT 2
+
+#define PIN_WIRE_SDA         (20u)
+#define PIN_WIRE_SCL         (21u)
+#define WIRE_INTERFACE       TWI1
+#define WIRE_INTERFACE_ID    ID_TWI1
+#define WIRE_ISR_HANDLER     TWI1_Handler
+
+#define PIN_WIRE1_SDA        (70u)
+#define PIN_WIRE1_SCL        (71u)
+#define WIRE1_INTERFACE      TWI0
+#define WIRE1_INTERFACE_ID   ID_TWI0
+#define WIRE1_ISR_HANDLER    TWI0_Handler
+
+/*
+ * UART/USART Interfaces
+ */
+// Serial0
+#define PINS_UART            (81u)
+// Serial1
+#define PINS_USART0          (82u)
+// Serial2
+#define PINS_USART1          (83u)
+// Serial3
+#define PINS_USART3          (84u)
+
+/*
+ * USB Interfaces
+ */
+#define PINS_USB             (85u)
+
+/*
+ * Analog pins
+ */
+static const uint8_t A0  = 54;
+static const uint8_t A1  = 55;
+static const uint8_t A2  = 56;
+static const uint8_t A3  = 57;
+static const uint8_t A4  = 58;
+static const uint8_t A5  = 59;
+static const uint8_t A6  = 60;
+static const uint8_t A7  = 61;
+static const uint8_t A8  = 62;
+static const uint8_t A9  = 63;
+static const uint8_t A10 = 64;
+static const uint8_t A11 = 65;
+static const uint8_t DAC0 = 66;
+static const uint8_t DAC1 = 67;
+static const uint8_t CANRX = 68;
+static const uint8_t CANTX = 69;
+#define ADC_RESOLUTION    12
+
+/*
+ * DACC
+ */
+#define DACC_INTERFACE    DACC
+#define DACC_INTERFACE_ID ID_DACC
+#define DACC_RESOLUTION   12
+#define DACC_ISR_HANDLER    DACC_Handler
+#define DACC_ISR_ID         DACC_IRQn
+
+/*
+ * PWM
+ */
+#define PWM_INTERFACE   PWM
+#define PWM_INTERFACE_ID  ID_PWM
+#define PWM_FREQUENCY   1000
+#define PWM_MAX_DUTY_CYCLE  255
+#define PWM_MIN_DUTY_CYCLE  0
+#define PWM_RESOLUTION    8
+
+/*
+ * TC
+ */
+#define TC_INTERFACE        TC0
+#define TC_INTERFACE_ID     ID_TC0
+#define TC_FREQUENCY        1000
+#define TC_MAX_DUTY_CYCLE   255
+#define TC_MIN_DUTY_CYCLE   0
+#define TC_RESOLUTION   8
+
+#ifdef __cplusplus
+}
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+
+extern UARTClass Serial0;
+extern USARTClass Serial1;
+extern USARTClass Serial2;
+extern USARTClass Serial3;
+
+#endif
+
+#endif /* _VARIANT_ARDUINO_DUE_X_ */